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authorChander Kashyap <chander.kashyap@linaro.org>2013-06-18 11:29:35 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-06-18 15:09:35 -0400
commit34dcedfbf97bc1c91c20f341e4ff4f70e53a0644 (patch)
tree58a432e93bc9eba10dead08b8449d2f96e9e82e7
parent1609027fc2f4e3784c64a57654c16b9c4f2d10db (diff)
ARM: dts: Add initial device tree support for EXYNOS5420
Add initial device tree nodes for EXYNOS5420 SoC and SMDK5420 board. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts33
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi103
3 files changed, 137 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 56ffdde091fa..13575103594d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
57 exynos5440-sd5v1.dtb \ 57 exynos5440-sd5v1.dtb \
58 exynos5250-smdk5250.dtb \ 58 exynos5250-smdk5250.dtb \
59 exynos5250-snow.dtb \ 59 exynos5250-snow.dtb \
60 exynos5420-smdk5420.dtb \
60 exynos5440-ssdk5440.dtb 61 exynos5440-ssdk5440.dtb
61dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 62dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
62 ecx-2000.dtb 63 ecx-2000.dtb
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
1/*
2 * SAMSUNG SMDK5420 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13#include "exynos5420.dtsi"
14
15/ {
16 model = "Samsung SMDK5420 board based on EXYNOS5420";
17 compatible = "samsung,smdk5420", "samsung,exynos5420";
18
19 memory {
20 reg = <0x20000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttySAC2,115200 init=/linuxrc";
25 };
26
27 fixed-rate-clocks {
28 oscclk {
29 compatible = "samsung,exynos5420-oscclk";
30 clock-frequency = <24000000>;
31 };
32 };
33};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8474d63fc5e5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,103 @@
1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "exynos5.dtsi"
17/ {
18 compatible = "samsung,exynos5420";
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a15";
27 reg = <0x0>;
28 clock-frequency = <1800000000>;
29 };
30
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a15";
34 reg = <0x1>;
35 clock-frequency = <1800000000>;
36 };
37
38 cpu2: cpu@2 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <0x2>;
42 clock-frequency = <1800000000>;
43 };
44
45 cpu3: cpu@3 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a15";
48 reg = <0x3>;
49 clock-frequency = <1800000000>;
50 };
51 };
52
53 clock: clock-controller@0x10010000 {
54 compatible = "samsung,exynos5420-clock";
55 reg = <0x10010000 0x30000>;
56 #clock-cells = <1>;
57 };
58
59 mct@101C0000 {
60 compatible = "samsung,exynos4210-mct";
61 reg = <0x101C0000 0x800>;
62 interrupt-controller;
63 #interrups-cells = <1>;
64 interrupt-parent = <&mct_map>;
65 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
66 clocks = <&clock 1>, <&clock 315>;
67 clock-names = "fin_pll", "mct";
68
69 mct_map: mct-map {
70 #interrupt-cells = <1>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 interrupt-map = <0 &combiner 23 3>,
74 <1 &combiner 23 4>,
75 <2 &combiner 25 2>,
76 <3 &combiner 25 3>,
77 <4 &gic 0 120 0>,
78 <5 &gic 0 121 0>,
79 <6 &gic 0 122 0>,
80 <7 &gic 0 123 0>;
81 };
82 };
83
84 serial@12C00000 {
85 clocks = <&clock 257>, <&clock 128>;
86 clock-names = "uart", "clk_uart_baud0";
87 };
88
89 serial@12C10000 {
90 clocks = <&clock 258>, <&clock 129>;
91 clock-names = "uart", "clk_uart_baud0";
92 };
93
94 serial@12C20000 {
95 clocks = <&clock 259>, <&clock 130>;
96 clock-names = "uart", "clk_uart_baud0";
97 };
98
99 serial@12C30000 {
100 clocks = <&clock 260>, <&clock 131>;
101 clock-names = "uart", "clk_uart_baud0";
102 };
103};