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authorChander Kashyap <chander.kashyap@linaro.org>2013-06-18 11:29:34 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-06-18 15:09:34 -0400
commit1609027fc2f4e3784c64a57654c16b9c4f2d10db (patch)
tree62ef0c375b2fb746e215f0afb337c114daabd125
parentc6fd0fe85ab761829102b60d590d0fdd71a649bd (diff)
clk: exynos5420: register clocks using common clock framework
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt201
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c762
3 files changed, 964 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
new file mode 100644
index 000000000000..9bcc4b1bff51
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -0,0 +1,201 @@
1* Samsung Exynos5420 Clock Controller
2
3The Exynos5420 clock controller generates and supplies clock to various
4controllers within the Exynos5420 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32 sclk_uart0 128
33 sclk_uart1 129
34 sclk_uart2 130
35 sclk_uart3 131
36 sclk_mmc0 132
37 sclk_mmc1 133
38 sclk_mmc2 134
39 sclk_spi0 135
40 sclk_spi1 136
41 sclk_spi2 137
42 sclk_i2s1 138
43 sclk_i2s2 139
44 sclk_pcm1 140
45 sclk_pcm2 141
46 sclk_spdif 142
47 sclk_hdmi 143
48 sclk_pixel 144
49 sclk_dp1 145
50 sclk_mipi1 146
51 sclk_fimd1 147
52 sclk_maudio0 148
53 sclk_maupcm0 149
54 sclk_usbd300 150
55 sclk_usbd301 151
56 sclk_usbphy300 152
57 sclk_usbphy301 153
58 sclk_unipro 154
59 sclk_pwm 155
60 sclk_gscl_wa 156
61 sclk_gscl_wb 157
62
63 [Peripheral Clock Gates]
64
65 Clock ID
66 ----------------------------
67
68 aclk66_peric 256
69 uart0 257
70 uart1 258
71 uart2 259
72 uart3 260
73 i2c0 261
74 i2c1 262
75 i2c2 263
76 i2c3 264
77 i2c4 265
78 i2c5 266
79 i2c6 267
80 i2c7 268
81 i2c_hdmi 269
82 tsadc 270
83 spi0 271
84 spi1 272
85 spi2 273
86 keyif 274
87 i2s1 275
88 i2s2 276
89 pcm1 277
90 pcm2 278
91 pwm 279
92 spdif 280
93 i2c8 281
94 i2c9 282
95 i2c10 283
96 aclk66_psgen 300
97 chipid 301
98 sysreg 302
99 tzpc0 303
100 tzpc1 304
101 tzpc2 305
102 tzpc3 306
103 tzpc4 307
104 tzpc5 308
105 tzpc6 309
106 tzpc7 310
107 tzpc8 311
108 tzpc9 312
109 hdmi_cec 313
110 seckey 314
111 mct 315
112 wdt 316
113 rtc 317
114 tmu 318
115 tmu_gpu 319
116 pclk66_gpio 330
117 aclk200_fsys2 350
118 mmc0 351
119 mmc1 352
120 mmc2 353
121 sromc 354
122 ufs 355
123 aclk200_fsys 360
124 tsi 361
125 pdma0 362
126 pdma1 363
127 rtic 364
128 usbh20 365
129 usbd300 366
130 usbd301 377
131 aclk400_mscl 380
132 mscl0 381
133 mscl1 382
134 mscl2 383
135 smmu_mscl0 384
136 smmu_mscl1 385
137 smmu_mscl2 386
138 aclk333 400
139 mfc 401
140 smmu_mfcl 402
141 smmu_mfcr 403
142 aclk200_disp1 410
143 dsim1 411
144 dp1 412
145 hdmi 413
146 aclk300_disp1 420
147 fimd1 421
148 smmu_fimd1 422
149 aclk166 430
150 mixer 431
151 aclk266 440
152 rotator 441
153 mdma1 442
154 smmu_rotator 443
155 smmu_mdma1 444
156 aclk300_jpeg 450
157 jpeg 451
158 jpeg2 452
159 smmu_jpeg 453
160 aclk300_gscl 460
161 smmu_gscl0 461
162 smmu_gscl1 462
163 gscl_wa 463
164 gscl_wb 464
165 gscl0 465
166 gscl1 466
167 clk_3aa 467
168 aclk266_g2d 470
169 sss 471
170 slim_sss 472
171 mdma0 473
172 aclk333_g2d 480
173 g2d 481
174 aclk333_432_gscl 490
175 smmu_3aa 491
176 smmu_fimcl0 492
177 smmu_fimcl1 493
178 smmu_fimcl3 494
179 fimc_lite3 495
180 aclk_g3d 500
181 g3d 501
182
183Example 1: An example of a clock controller node is listed below.
184
185 clock: clock-controller@0x10010000 {
186 compatible = "samsung,exynos5420-clock";
187 reg = <0x10010000 0x30000>;
188 #clock-cells = <1>;
189 };
190
191Example 2: UART controller node that consumes the clock generated by the clock
192 controller. Refer to the standard clock bindings for information
193 about 'clocks' and 'clock-names' property.
194
195 serial@13820000 {
196 compatible = "samsung,exynos4210-uart";
197 reg = <0x13820000 0x100>;
198 interrupts = <0 54 0>;
199 clocks = <&clock 259>, <&clock 130>;
200 clock-names = "uart", "clk_uart_baud0";
201 };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 187681013bdb..5d4d432cc4ac 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,5 +5,6 @@
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o 5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
9obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
new file mode 100644
index 000000000000..68a96cbd4936
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -0,0 +1,762 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5420 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22#define SRC_CPU 0x200
23#define DIV_CPU0 0x500
24#define DIV_CPU1 0x504
25#define GATE_BUS_CPU 0x700
26#define GATE_SCLK_CPU 0x800
27#define SRC_TOP0 0x10200
28#define SRC_TOP1 0x10204
29#define SRC_TOP2 0x10208
30#define SRC_TOP3 0x1020c
31#define SRC_TOP4 0x10210
32#define SRC_TOP5 0x10214
33#define SRC_TOP6 0x10218
34#define SRC_TOP7 0x1021c
35#define SRC_DISP10 0x1022c
36#define SRC_MAU 0x10240
37#define SRC_FSYS 0x10244
38#define SRC_PERIC0 0x10250
39#define SRC_PERIC1 0x10254
40#define SRC_TOP10 0x10280
41#define SRC_TOP11 0x10284
42#define SRC_TOP12 0x10288
43#define SRC_MASK_DISP10 0x1032c
44#define SRC_MASK_FSYS 0x10340
45#define SRC_MASK_PERIC0 0x10350
46#define SRC_MASK_PERIC1 0x10354
47#define DIV_TOP0 0x10500
48#define DIV_TOP1 0x10504
49#define DIV_TOP2 0x10508
50#define DIV_DISP10 0x1052c
51#define DIV_MAU 0x10544
52#define DIV_FSYS0 0x10548
53#define DIV_FSYS1 0x1054c
54#define DIV_FSYS2 0x10550
55#define DIV_PERIC0 0x10558
56#define DIV_PERIC1 0x1055c
57#define DIV_PERIC2 0x10560
58#define DIV_PERIC3 0x10564
59#define DIV_PERIC4 0x10568
60#define GATE_BUS_TOP 0x10700
61#define GATE_BUS_FSYS0 0x10740
62#define GATE_BUS_PERIC 0x10750
63#define GATE_BUS_PERIC1 0x10754
64#define GATE_BUS_PERIS0 0x10760
65#define GATE_BUS_PERIS1 0x10764
66#define GATE_IP_GSCL0 0x10910
67#define GATE_IP_GSCL1 0x10920
68#define GATE_IP_MFC 0x1092c
69#define GATE_IP_DISP1 0x10928
70#define GATE_IP_G3D 0x10930
71#define GATE_IP_GEN 0x10934
72#define GATE_IP_MSCL 0x10970
73#define GATE_TOP_SCLK_GSCL 0x10820
74#define GATE_TOP_SCLK_DISP1 0x10828
75#define GATE_TOP_SCLK_MAU 0x1083c
76#define GATE_TOP_SCLK_FSYS 0x10840
77#define GATE_TOP_SCLK_PERIC 0x10850
78#define SRC_CDREX 0x20200
79#define SRC_KFC 0x28200
80#define DIV_KFC0 0x28500
81
82enum exynos5420_clks {
83 none,
84
85 /* core clocks */
86 fin_pll,
87
88 /* gate for special clocks (sclk) */
89 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
90 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
91 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
92 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
93 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
94 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
95
96 /* gate clocks */
97 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
98 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
99 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
100 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
101 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
102 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
103 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
104 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
105 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
106 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
107 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
108 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
109 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
110 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
111 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
112 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
113
114 nr_clks,
115};
116
117/*
118 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle.
120 */
121static __initdata unsigned long exynos5420_clk_regs[] = {
122 SRC_CPU,
123 DIV_CPU0,
124 DIV_CPU1,
125 GATE_BUS_CPU,
126 GATE_SCLK_CPU,
127 SRC_TOP0,
128 SRC_TOP1,
129 SRC_TOP2,
130 SRC_TOP3,
131 SRC_TOP4,
132 SRC_TOP5,
133 SRC_TOP6,
134 SRC_TOP7,
135 SRC_DISP10,
136 SRC_MAU,
137 SRC_FSYS,
138 SRC_PERIC0,
139 SRC_PERIC1,
140 SRC_TOP10,
141 SRC_TOP11,
142 SRC_TOP12,
143 SRC_MASK_DISP10,
144 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1,
147 DIV_TOP0,
148 DIV_TOP1,
149 DIV_TOP2,
150 DIV_DISP10,
151 DIV_MAU,
152 DIV_FSYS0,
153 DIV_FSYS1,
154 DIV_FSYS2,
155 DIV_PERIC0,
156 DIV_PERIC1,
157 DIV_PERIC2,
158 DIV_PERIC3,
159 DIV_PERIC4,
160 GATE_BUS_TOP,
161 GATE_BUS_FSYS0,
162 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1,
166 GATE_IP_GSCL0,
167 GATE_IP_GSCL1,
168 GATE_IP_MFC,
169 GATE_IP_DISP1,
170 GATE_IP_G3D,
171 GATE_IP_GEN,
172 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX,
179 SRC_KFC,
180 DIV_KFC0,
181};
182
183/* list of all parent clocks */
184PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
185 "sclk_mpll", "sclk_spll" };
186PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" };
187PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" };
188PNAME(apll_p) = { "fin_pll", "fout_apll", };
189PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
190PNAME(cpll_p) = { "fin_pll", "fout_cpll", };
191PNAME(dpll_p) = { "fin_pll", "fout_dpll", };
192PNAME(epll_p) = { "fin_pll", "fout_epll", };
193PNAME(ipll_p) = { "fin_pll", "fout_ipll", };
194PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
195PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
196PNAME(rpll_p) = { "fin_pll", "fout_rpll", };
197PNAME(spll_p) = { "fin_pll", "fout_spll", };
198PNAME(vpll_p) = { "fin_pll", "fout_vpll", };
199
200PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
201PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
202 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
203PNAME(group3_p) = { "sclk_rpll", "sclk_spll" };
204PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
205PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" };
206
207PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" };
208PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
209
210PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
211PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" };
212
213PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
214PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" };
215
216PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
217PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" };
218
219PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
220PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" };
221
222PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
223PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" };
224
225PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
226PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" };
227
228PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
229PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" };
230
231PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
232PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" };
233
234PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
235PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" };
236
237PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
238PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" };
239
240PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
241PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" };
242
243PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
244PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" };
245
246PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
247PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" };
248
249PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
250PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" };
251
252PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
253 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
254PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
255 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
256PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
257 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
258PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
259 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
260PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
261PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
262 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
263
264/* fixed rate clocks generated outside the soc */
265struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
266 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
267};
268
269/* fixed rate clocks generated inside the soc */
270struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
271 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
272 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
273 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
274 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
275 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
276};
277
278struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
279 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
280};
281
282struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
283 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
284 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
285 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
286 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
287 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
288 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
289
290 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
291
292 MUX_A(none, "mout_aclk400_mscl", group1_p,
293 SRC_TOP0, 4, 2, "aclk400_mscl"),
294 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
295 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
296 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
297
298 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
299 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
300 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
301 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
302 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
303
304 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
305 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
306 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
307 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
308 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
309 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
310
311 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
312 SRC_TOP3, 4, 1),
313 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
314 SRC_TOP3, 8, 1, "aclk200_disp1"),
315 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
316 SRC_TOP3, 12, 1),
317 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
318 SRC_TOP3, 28, 1),
319
320 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
321 SRC_TOP4, 0, 1),
322 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
323 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
324 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
325 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
326
327 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
328 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
329 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
330 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
331 SRC_TOP5, 16, 1, "aclkg3d"),
332 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
333 SRC_TOP5, 20, 1),
334 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
335 SRC_TOP5, 24, 1),
336 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
337 SRC_TOP5, 28, 1),
338
339 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
340 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
341 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
342 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
343 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
344 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
345 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
346 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
347
348 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
349 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
350 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
351 SRC_TOP10, 12, 1),
352 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
353
354 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
355 SRC_TOP11, 0, 1),
356 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
357 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
358 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
359 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
360
361 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
362 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
363 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
364 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
365 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
366 SRC_TOP12, 24, 1),
367 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
368
369 /* DISP1 Block */
370 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
371 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
372 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
373 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
374 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
375
376 /* MAU Block */
377 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
378
379 /* FSYS Block */
380 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
381 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
382 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
383 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
384 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
385 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
386
387 /* PERIC Block */
388 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
389 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
390 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
391 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
392 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
393 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
394 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
395 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
396 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
397 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
398 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
399 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
400};
401
402struct samsung_div_clock exynos5420_div_clks[] __initdata = {
403 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
404 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
405 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
406 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
407 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
408
409 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
410 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
411 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
412 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
413 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
414
415 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
416 DIV_TOP1, 0, 3),
417 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
418 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
419 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
420 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
421
422 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
423 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
424 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
425 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
426 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
427 DIV_TOP2, 24, 3, "aclk300_disp1"),
428 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
429
430 /* DISP1 Block */
431 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
432 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
433 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
434 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
435
436 /* Audio Block */
437 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
438 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
439
440 /* USB3.0 */
441 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
442 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
443 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
444 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
445
446 /* MMC */
447 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
448 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
449 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
450
451 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
452
453 /* UART and PWM */
454 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
455 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
456 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
457 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
458 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
459
460 /* SPI */
461 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
462 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
463 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
464
465 /* PCM */
466 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
467 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
468
469 /* Audio - I2S */
470 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
471 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
472 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
473 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
474 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
475
476 /* SPI Pre-Ratio */
477 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
478 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
479 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
480};
481
482struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
483 /* TODO: Re-verify the CG bits for all the gate clocks */
484 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
485
486 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
487 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
488 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
489 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
490
491 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
492 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
493 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
494 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
495 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
496 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
497 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
498 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
499 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
500 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
501 GATE(0, "pclk66_gpio", "mout_sw_aclk66",
502 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
503 GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
504 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
505 GATE(0, "aclk66_peric", "mout_aclk66_peric",
506 GATE_BUS_TOP, 11, 0, 0),
507 GATE(0, "aclk166", "mout_user_aclk166",
508 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
509 GATE(0, "aclk333", "mout_aclk333",
510 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
511
512 /* sclk */
513 GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
514 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
515 GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
516 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
517 GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
518 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
519 GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
520 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
521 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
522 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
523 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
524 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
525 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
526 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
527 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
528 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
529 GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
530 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
531 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
532 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
533 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
534 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
535 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
536 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
537 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
538 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
539
540 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
541 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
542 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
543 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
544 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
545 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
546 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
547 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
548 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
549 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
551 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
553 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
554
555 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
556 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
557
558 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
559 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
561 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
562
563 /* Display */
564 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
565 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
567 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
569 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
571 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
573 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
574
575 /* Maudio Block */
576 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
577 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
578 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
579 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
580 /* FSYS */
581 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
582 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
583 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
584 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
585 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
586 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
587 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
588 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
589 GATE(sromc, "sromc", "aclk200_fsys2",
590 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
591 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
592 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
593 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
594
595 /* UART */
596 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
597 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
598 GATE_A(uart2, "uart2", "aclk66_peric",
599 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
600 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
601 /* I2C */
602 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
603 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
604 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
605 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
606 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
607 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
608 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
609 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
610 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
611 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
612 /* SPI */
613 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
614 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
615 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
616 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
617 /* I2S */
618 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
619 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
620 /* PCM */
621 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
622 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
623 /* PWM */
624 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
625 /* SPDIF */
626 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
627
628 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
629 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
630 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
631
632 GATE(chipid, "chipid", "aclk66_psgen",
633 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
634 GATE(sysreg, "sysreg", "aclk66_psgen",
635 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
636 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
637 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
638 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
639 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
640 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
641 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
642 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
643 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
644 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
645 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
646
647 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
648 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
649 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
650 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
651 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
652 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
653
654 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
655 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
656 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
657
658 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
659 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
660 GATE_IP_GSCL1, 3, 0, 0),
661 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
662 GATE_IP_GSCL1, 4, 0, 0),
663 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
664 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
665 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
668 GATE_IP_GSCL1, 16, 0, 0),
669 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
670 GATE_IP_GSCL1, 17, 0, 0),
671
672 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
673 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
674 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
675 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
676 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
677 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
678
679 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
680 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
681 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
682
683 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
684
685 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
686 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
687 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
688 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
689 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
690 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
691 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
692
693 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
694 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
695 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
696 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
697 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
698 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
699};
700
701static __initdata struct of_device_id ext_clk_match[] = {
702 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
703 { },
704};
705
706/* register exynos5420 clocks */
707void __init exynos5420_clk_init(struct device_node *np)
708{
709 void __iomem *reg_base;
710 struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
711 struct clk *rpll, *spll, *vpll;
712
713 if (np) {
714 reg_base = of_iomap(np, 0);
715 if (!reg_base)
716 panic("%s: failed to map registers\n", __func__);
717 } else {
718 panic("%s: unable to determine soc\n", __func__);
719 }
720
721 samsung_clk_init(np, reg_base, nr_clks,
722 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
723 NULL, 0);
724 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
725 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
726 ext_clk_match);
727
728 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
729 reg_base + 0x100);
730 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
731 reg_base + 0x20110);
732 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
733 reg_base + 0x10120);
734 dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
735 reg_base + 0x10128);
736 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
737 reg_base + 0x10130);
738 ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
739 reg_base + 0x10150);
740 kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
741 reg_base + 0x28100);
742 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
743 reg_base + 0x10180);
744 rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
745 reg_base + 0x10140);
746 spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
747 reg_base + 0x10160);
748 vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
749 reg_base + 0x10170);
750
751 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
752 ARRAY_SIZE(exynos5420_fixed_rate_clks));
753 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
754 ARRAY_SIZE(exynos5420_fixed_factor_clks));
755 samsung_clk_register_mux(exynos5420_mux_clks,
756 ARRAY_SIZE(exynos5420_mux_clks));
757 samsung_clk_register_div(exynos5420_div_clks,
758 ARRAY_SIZE(exynos5420_div_clks));
759 samsung_clk_register_gate(exynos5420_gate_clks,
760 ARRAY_SIZE(exynos5420_gate_clks));
761}
762CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 20:14:51 -0400