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authorKevin Hilman <khilman@linaro.org>2013-10-09 16:21:51 -0400
committerKevin Hilman <khilman@linaro.org>2013-10-09 16:22:03 -0400
commit3197e4a123d90a2ece9488267a05fcb52766e52d (patch)
tree38a32b51c47ddf9507c9f0f14d77fba7dfd07d29
parent32d7962d37138216a47c2c908969cab737fd3b3c (diff)
parent37078732998e51c2645db99e7434ccc6774dafed (diff)
Merge tag 'dt-3.13' of git://git.infradead.org/linux-mvebu into next/dt
From Jason Cooper: mvebu dt changes for v3.13 - mvebu - add MSI - new compatible string for mv64xxx-i2c - dove - use the pre-processor - define the MBus nodes - add PCIe controllers - add Globalscale D3Plug - relocate internal registers nodes * tag 'dt-3.13' of git://git.infradead.org/linux-mvebu: ARM: dove: add initial DT file for Globalscale D3Plug ARM: dove: add PCIe controllers to SoC DT ARM: dove: relocate internal registers device nodes ARM: dove: add MBus DT node ARM: dove: add MBUS_ID macro to Dove DT ARM: dove: use preprocessor on device tree files ARM: mvebu: link PCIe controllers to the MSI controller ARM: mvebu: the MPIC now provides MSI controller features ARM: dts: mvebu: Update with the new compatible string for mv64xxx-i2c Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi3
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi9
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi10
-rw-r--r--arch/arm/boot/dts/dove-cm-a510.dts2
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts2
-rw-r--r--arch/arm/boot/dts/dove-d2plug.dts2
-rw-r--r--arch/arm/boot/dts/dove-d3plug.dts103
-rw-r--r--arch/arm/boot/dts/dove-dove-db.dts2
-rw-r--r--arch/arm/boot/dts/dove.dtsi1009
13 files changed, 670 insertions, 476 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a5534c0e71ef..c4e7fa0d3e67 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
49dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 49dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
50 dove-cubox.dtb \ 50 dove-cubox.dtb \
51 dove-d2plug.dtb \ 51 dove-d2plug.dtb \
52 dove-d3plug.dtb \
52 dove-dove-db.dtb 53 dove-dove-db.dtb
53dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 54dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
54 exynos4210-smdkv310.dtb \ 55 exynos4210-smdkv310.dtb \
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 1de2dae0fdae..534e1be80df2 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -113,6 +113,7 @@
113 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
114 #size-cells = <1>; 114 #size-cells = <1>;
115 interrupt-controller; 115 interrupt-controller;
116 msi-controller;
116 }; 117 };
117 118
118 coherency-fabric@20200 { 119 coherency-fabric@20200 {
@@ -176,7 +177,6 @@
176 177
177 i2c0: i2c@11000 { 178 i2c0: i2c@11000 {
178 compatible = "marvell,mv64xxx-i2c"; 179 compatible = "marvell,mv64xxx-i2c";
179 reg = <0x11000 0x20>;
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <0>; 181 #size-cells = <0>;
182 interrupts = <31>; 182 interrupts = <31>;
@@ -187,7 +187,6 @@
187 187
188 i2c1: i2c@11100 { 188 i2c1: i2c@11100 {
189 compatible = "marvell,mv64xxx-i2c"; 189 compatible = "marvell,mv64xxx-i2c";
190 reg = <0x11100 0x20>;
191 #address-cells = <1>; 190 #address-cells = <1>;
192 #size-cells = <0>; 191 #size-cells = <0>;
193 interrupts = <32>; 192 interrupts = <32>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index e134d7a90c9a..7a4b82e71aaf 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -44,6 +44,7 @@
44 #address-cells = <3>; 44 #address-cells = <3>;
45 #size-cells = <2>; 45 #size-cells = <2>;
46 46
47 msi-parent = <&mpic>;
47 bus-range = <0x00 0xff>; 48 bus-range = <0x00 0xff>;
48 49
49 ranges = 50 ranges =
@@ -218,6 +219,14 @@
218 }; 219 };
219 }; 220 };
220 221
222 i2c0: i2c@11000 {
223 reg = <0x11000 0x20>;
224 };
225
226 i2c1: i2c@11100 {
227 reg = <0x11100 0x20>;
228 };
229
221 usb@50000 { 230 usb@50000 {
222 clocks = <&coreclk 0>; 231 clocks = <&coreclk 0>;
223 }; 232 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 0358a33cba48..3f5e6121c730 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -57,6 +57,7 @@
57 #address-cells = <3>; 57 #address-cells = <3>;
58 #size-cells = <2>; 58 #size-cells = <2>;
59 59
60 msi-parent = <&mpic>;
60 bus-range = <0x00 0xff>; 61 bus-range = <0x00 0xff>;
61 62
62 ranges = 63 ranges =
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 0e82c5062243..3e9fd1353f89 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -58,6 +58,7 @@
58 #address-cells = <3>; 58 #address-cells = <3>;
59 #size-cells = <2>; 59 #size-cells = <2>;
60 60
61 msi-parent = <&mpic>;
61 bus-range = <0x00 0xff>; 62 bus-range = <0x00 0xff>;
62 63
63 ranges = 64 ranges =
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index e82c1b80af17..31ba6d8fbadf 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -74,6 +74,7 @@
74 #address-cells = <3>; 74 #address-cells = <3>;
75 #size-cells = <2>; 75 #size-cells = <2>;
76 76
77 msi-parent = <&mpic>;
77 bus-range = <0x00 0xff>; 78 bus-range = <0x00 0xff>;
78 79
79 ranges = 80 ranges =
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index def125c0eeaa..84fcd861b6e7 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -145,6 +145,16 @@
145 }; 145 };
146 }; 146 };
147 147
148 i2c0: i2c@11000 {
149 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
150 reg = <0x11000 0x100>;
151 };
152
153 i2c1: i2c@11100 {
154 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
155 reg = <0x11100 0x100>;
156 };
157
148 usb@50000 { 158 usb@50000 {
149 clocks = <&gateclk 18>; 159 clocks = <&gateclk 18>;
150 }; 160 };
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
index 61a8062e56de..50c0d6904497 100644
--- a/arch/arm/boot/dts/dove-cm-a510.dts
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Compulab CM-A510"; 6 model = "Compulab CM-A510";
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 022646ef4b38..4af59b6dce0f 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "SolidRun CuBox"; 6 model = "SolidRun CuBox";
diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts
index e2222ce94f2f..c11d3636c8e5 100644
--- a/arch/arm/boot/dts/dove-d2plug.dts
+++ b/arch/arm/boot/dts/dove-d2plug.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Globalscale D2Plug"; 6 model = "Globalscale D2Plug";
diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts
new file mode 100644
index 000000000000..f5f59bb5a534
--- /dev/null
+++ b/arch/arm/boot/dts/dove-d3plug.dts
@@ -0,0 +1,103 @@
1/dts-v1/;
2
3#include "dove.dtsi"
4
5/ {
6 model = "Globalscale D3Plug";
7 compatible = "globalscale,d3plug", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait";
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
21 pinctrl-names = "default";
22
23 wlan-act {
24 label = "wlan-act";
25 gpios = <&gpio0 0 1>;
26 };
27
28 wlan-ap {
29 label = "wlan-ap";
30 gpios = <&gpio0 1 1>;
31 };
32
33 status {
34 label = "status";
35 gpios = <&gpio0 2 1>;
36 };
37 };
38
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 usb_power: regulator@1 {
45 compatible = "regulator-fixed";
46 reg = <1>;
47 regulator-name = "USB Power";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 enable-active-high;
51 regulator-always-on;
52 regulator-boot-on;
53 gpio = <&gpio0 8 0>;
54 pinctrl-0 = <&pmx_gpio_8>;
55 pinctrl-names = "default";
56 };
57 };
58};
59
60&uart0 { status = "okay"; };
61&sata0 { status = "okay"; };
62&i2c0 { status = "okay"; };
63
64/* Samsung M8G2F eMMC */
65&sdio0 {
66 status = "okay";
67 non-removable;
68 bus-width = <4>;
69};
70
71/* Marvell SD8787 WLAN/BT */
72&sdio1 {
73 status = "okay";
74 non-removable;
75};
76
77&spi0 {
78 status = "okay";
79
80 /* spi0.0: 2M Flash Macronix MX25L1605D */
81 spi-flash@0 {
82 compatible = "st,m25l1605d";
83 spi-max-frequency = <86000000>;
84 reg = <0>;
85 };
86};
87
88&pcie {
89 status = "okay";
90 /* Fresco Logic USB3.0 xHCI controller */
91 pcie-port@0 {
92 status = "okay";
93 reset-gpios = <&gpio0 26 1>;
94 reset-delay-us = <20000>;
95 pinctrl-0 = <&pmx_camera_gpio>;
96 pinctrl-names = "default";
97 };
98 /* Mini-PCIe slot */
99 pcie-port@1 {
100 status = "okay";
101 reset-gpios = <&gpio0 25 1>;
102 };
103};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
index e5a920beab45..bb725dca3a10 100644
--- a/arch/arm/boot/dts/dove-dove-db.dts
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Marvell DB-MV88AP510-BP Development Board"; 6 model = "Marvell DB-MV88AP510-BP Development Board";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index cc279166646f..499abadf86f0 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -1,8 +1,11 @@
1/include/ "skeleton.dtsi" 1/include/ "skeleton.dtsi"
2 2
3#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
4
3/ { 5/ {
4 compatible = "marvell,dove"; 6 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 7 model = "Marvell Armada 88AP510 SoC";
8 interrupt-parent = <&intc>;
6 9
7 aliases { 10 aliases {
8 gpio0 = &gpio0; 11 gpio0 = &gpio0;
@@ -27,482 +30,548 @@
27 marvell,tauros2-cache-features = <0>; 30 marvell,tauros2-cache-features = <0>;
28 }; 31 };
29 32
30 soc@f1000000 { 33 mbus {
31 compatible = "simple-bus"; 34 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
32 #address-cells = <1>; 35 #address-cells = <2>;
33 #size-cells = <1>; 36 #size-cells = <1>;
34 interrupt-parent = <&intc>; 37 controller = <&mbusc>;
35 38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
36 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ 39 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
37 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ 40
38 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ 41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
39 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ 42 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
40 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ 43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
41 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ 44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
42 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ 45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
43 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ 46
44 47 pcie: pcie-controller {
45 timer: timer@20300 { 48 compatible = "marvell,dove-pcie";
46 compatible = "marvell,orion-timer";
47 reg = <0x20300 0x20>;
48 interrupt-parent = <&bridge_intc>;
49 interrupts = <1>, <2>;
50 clocks = <&core_clk 0>;
51 };
52
53 intc: main-interrupt-ctrl@20200 {
54 compatible = "marvell,orion-intc";
55 interrupt-controller;
56 #interrupt-cells = <1>;
57 reg = <0x20200 0x10>, <0x20210 0x10>;
58 };
59
60 bridge_intc: bridge-interrupt-ctrl@20110 {
61 compatible = "marvell,orion-bridge-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 reg = <0x20110 0x8>;
65 interrupts = <0>;
66 marvell,#interrupts = <5>;
67 };
68
69 core_clk: core-clocks@d0214 {
70 compatible = "marvell,dove-core-clock";
71 reg = <0xd0214 0x4>;
72 #clock-cells = <1>;
73 };
74
75 gate_clk: clock-gating-ctrl@d0038 {
76 compatible = "marvell,dove-gating-clock";
77 reg = <0xd0038 0x4>;
78 clocks = <&core_clk 0>;
79 #clock-cells = <1>;
80 };
81
82 thermal: thermal-diode@d001c {
83 compatible = "marvell,dove-thermal";
84 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
85 };
86
87 uart0: serial@12000 {
88 compatible = "ns16550a";
89 reg = <0x12000 0x100>;
90 reg-shift = <2>;
91 interrupts = <7>;
92 clocks = <&core_clk 0>;
93 status = "disabled"; 49 status = "disabled";
94 }; 50 device_type = "pci";
95 51 #address-cells = <3>;
96 uart1: serial@12100 { 52 #size-cells = <2>;
97 compatible = "ns16550a"; 53
98 reg = <0x12100 0x100>; 54 msi-parent = <&intc>;
99 reg-shift = <2>; 55 bus-range = <0x00 0xff>;
100 interrupts = <8>; 56
101 clocks = <&core_clk 0>; 57 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
102 pinctrl-0 = <&pmx_uart1>; 58 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
103 pinctrl-names = "default"; 59 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
104 status = "disabled"; 60 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
105 }; 61 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
106 62 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
107 uart2: serial@12200 { 63
108 compatible = "ns16550a"; 64 pcie-port@0 {
109 reg = <0x12000 0x100>; 65 device_type = "pci";
110 reg-shift = <2>; 66 status = "disabled";
111 interrupts = <9>; 67 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
112 clocks = <&core_clk 0>; 68 reg = <0x0800 0 0 0 0>;
113 status = "disabled"; 69 clocks = <&gate_clk 4>;
114 }; 70 marvell,pcie-port = <0>;
115 71
116 uart3: serial@12300 { 72 #address-cells = <3>;
117 compatible = "ns16550a"; 73 #size-cells = <2>;
118 reg = <0x12100 0x100>; 74 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
119 reg-shift = <2>; 75 0x81000000 0 0 0x81000000 0x1 0 1 0>;
120 interrupts = <10>; 76
121 clocks = <&core_clk 0>; 77 #interrupt-cells = <1>;
122 status = "disabled"; 78 interrupt-map-mask = <0 0 0 0>;
123 }; 79 interrupt-map = <0 0 0 0 &intc 16>;
124 80 };
125 gpio0: gpio-ctrl@d0400 { 81
126 compatible = "marvell,orion-gpio"; 82 pcie-port@1 {
127 #gpio-cells = <2>; 83 device_type = "pci";
128 gpio-controller; 84 status = "disabled";
129 reg = <0xd0400 0x20>; 85 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
130 ngpios = <32>; 86 reg = <0x1000 0 0 0 0>;
131 interrupt-controller; 87 clocks = <&gate_clk 5>;
132 #interrupt-cells = <2>; 88 marvell,pcie-port = <1>;
133 interrupts = <12>, <13>, <14>, <60>; 89
134 }; 90 #address-cells = <3>;
135 91 #size-cells = <2>;
136 gpio1: gpio-ctrl@d0420 { 92 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
137 compatible = "marvell,orion-gpio"; 93 0x81000000 0 0 0x81000000 0x2 0 1 0>;
138 #gpio-cells = <2>; 94
139 gpio-controller; 95 #interrupt-cells = <1>;
140 reg = <0xd0420 0x20>; 96 interrupt-map-mask = <0 0 0 0>;
141 ngpios = <32>; 97 interrupt-map = <0 0 0 0 &intc 18>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 interrupts = <61>;
145 };
146
147 gpio2: gpio-ctrl@e8400 {
148 compatible = "marvell,orion-gpio";
149 #gpio-cells = <2>;
150 gpio-controller;
151 reg = <0xe8400 0x0c>;
152 ngpios = <8>;
153 };
154
155 pinctrl: pin-ctrl@d0200 {
156 compatible = "marvell,dove-pinctrl";
157 reg = <0xd0200 0x10>;
158 clocks = <&gate_clk 22>;
159
160 pmx_gpio_0: pmx-gpio-0 {
161 marvell,pins = "mpp0";
162 marvell,function = "gpio";
163 };
164
165 pmx_gpio_1: pmx-gpio-1 {
166 marvell,pins = "mpp1";
167 marvell,function = "gpio";
168 };
169
170 pmx_gpio_2: pmx-gpio-2 {
171 marvell,pins = "mpp2";
172 marvell,function = "gpio";
173 };
174
175 pmx_gpio_3: pmx-gpio-3 {
176 marvell,pins = "mpp3";
177 marvell,function = "gpio";
178 };
179
180 pmx_gpio_4: pmx-gpio-4 {
181 marvell,pins = "mpp4";
182 marvell,function = "gpio";
183 };
184
185 pmx_gpio_5: pmx-gpio-5 {
186 marvell,pins = "mpp5";
187 marvell,function = "gpio";
188 };
189
190 pmx_gpio_6: pmx-gpio-6 {
191 marvell,pins = "mpp6";
192 marvell,function = "gpio";
193 };
194
195 pmx_gpio_7: pmx-gpio-7 {
196 marvell,pins = "mpp7";
197 marvell,function = "gpio";
198 };
199
200 pmx_gpio_8: pmx-gpio-8 {
201 marvell,pins = "mpp8";
202 marvell,function = "gpio";
203 };
204
205 pmx_gpio_9: pmx-gpio-9 {
206 marvell,pins = "mpp9";
207 marvell,function = "gpio";
208 };
209
210 pmx_gpio_10: pmx-gpio-10 {
211 marvell,pins = "mpp10";
212 marvell,function = "gpio";
213 };
214
215 pmx_gpio_11: pmx-gpio-11 {
216 marvell,pins = "mpp11";
217 marvell,function = "gpio";
218 };
219
220 pmx_gpio_12: pmx-gpio-12 {
221 marvell,pins = "mpp12";
222 marvell,function = "gpio";
223 };
224
225 pmx_gpio_13: pmx-gpio-13 {
226 marvell,pins = "mpp13";
227 marvell,function = "gpio";
228 };
229
230 pmx_gpio_14: pmx-gpio-14 {
231 marvell,pins = "mpp14";
232 marvell,function = "gpio";
233 };
234
235 pmx_gpio_15: pmx-gpio-15 {
236 marvell,pins = "mpp15";
237 marvell,function = "gpio";
238 };
239
240 pmx_gpio_16: pmx-gpio-16 {
241 marvell,pins = "mpp16";
242 marvell,function = "gpio";
243 };
244
245 pmx_gpio_17: pmx-gpio-17 {
246 marvell,pins = "mpp17";
247 marvell,function = "gpio";
248 };
249
250 pmx_gpio_18: pmx-gpio-18 {
251 marvell,pins = "mpp18";
252 marvell,function = "gpio";
253 };
254
255 pmx_gpio_19: pmx-gpio-19 {
256 marvell,pins = "mpp19";
257 marvell,function = "gpio";
258 };
259
260 pmx_gpio_20: pmx-gpio-20 {
261 marvell,pins = "mpp20";
262 marvell,function = "gpio";
263 };
264
265 pmx_gpio_21: pmx-gpio-21 {
266 marvell,pins = "mpp21";
267 marvell,function = "gpio";
268 }; 98 };
269
270 pmx_camera: pmx-camera {
271 marvell,pins = "mpp_camera";
272 marvell,function = "camera";
273 };
274
275 pmx_camera_gpio: pmx-camera-gpio {
276 marvell,pins = "mpp_camera";
277 marvell,function = "gpio";
278 };
279
280 pmx_sdio0: pmx-sdio0 {
281 marvell,pins = "mpp_sdio0";
282 marvell,function = "sdio0";
283 };
284
285 pmx_sdio0_gpio: pmx-sdio0-gpio {
286 marvell,pins = "mpp_sdio0";
287 marvell,function = "gpio";
288 };
289
290 pmx_sdio1: pmx-sdio1 {
291 marvell,pins = "mpp_sdio1";
292 marvell,function = "sdio1";
293 };
294
295 pmx_sdio1_gpio: pmx-sdio1-gpio {
296 marvell,pins = "mpp_sdio1";
297 marvell,function = "gpio";
298 };
299
300 pmx_audio1_gpio: pmx-audio1-gpio {
301 marvell,pins = "mpp_audio1";
302 marvell,function = "gpio";
303 };
304
305 pmx_spi0: pmx-spi0 {
306 marvell,pins = "mpp_spi0";
307 marvell,function = "spi0";
308 };
309
310 pmx_spi0_gpio: pmx-spi0-gpio {
311 marvell,pins = "mpp_spi0";
312 marvell,function = "gpio";
313 };
314
315 pmx_uart1: pmx-uart1 {
316 marvell,pins = "mpp_uart1";
317 marvell,function = "uart1";
318 };
319
320 pmx_uart1_gpio: pmx-uart1-gpio {
321 marvell,pins = "mpp_uart1";
322 marvell,function = "gpio";
323 };
324
325 pmx_nand: pmx-nand {
326 marvell,pins = "mpp_nand";
327 marvell,function = "nand";
328 };
329
330 pmx_nand_gpo: pmx-nand-gpo {
331 marvell,pins = "mpp_nand";
332 marvell,function = "gpo";
333 };
334 };
335
336 spi0: spi-ctrl@10600 {
337 compatible = "marvell,orion-spi";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 cell-index = <0>;
341 interrupts = <6>;
342 reg = <0x10600 0x28>;
343 clocks = <&core_clk 0>;
344 pinctrl-0 = <&pmx_spi0>;
345 pinctrl-names = "default";
346 status = "disabled";
347 }; 99 };
348 100
349 spi1: spi-ctrl@14600 { 101 internal-regs {
350 compatible = "marvell,orion-spi"; 102 compatible = "simple-bus";
351 #address-cells = <1>; 103 #address-cells = <1>;
352 #size-cells = <0>; 104 #size-cells = <1>;
353 cell-index = <1>; 105 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
354 interrupts = <5>; 106 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
355 reg = <0x14600 0x28>; 107 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
356 clocks = <&core_clk 0>; 108 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
357 status = "disabled"; 109
358 }; 110 mbusc: mbus-ctrl@20000 {
359 111 compatible = "marvell,mbus-controller";
360 i2c0: i2c-ctrl@11000 { 112 reg = <0x20000 0x80>, <0x800100 0x8>;
361 compatible = "marvell,mv64xxx-i2c"; 113 };
362 reg = <0x11000 0x20>; 114
363 #address-cells = <1>; 115 timer: timer@20300 {
364 #size-cells = <0>; 116 compatible = "marvell,orion-timer";
365 interrupts = <11>; 117 reg = <0x20300 0x20>;
366 clock-frequency = <400000>; 118 interrupt-parent = <&bridge_intc>;
367 timeout-ms = <1000>; 119 interrupts = <1>, <2>;
368 clocks = <&core_clk 0>; 120 clocks = <&core_clk 0>;
369 status = "disabled"; 121 };
370 }; 122
371 123 intc: main-interrupt-ctrl@20200 {
372 ehci0: usb-host@50000 { 124 compatible = "marvell,orion-intc";
373 compatible = "marvell,orion-ehci"; 125 interrupt-controller;
374 reg = <0x50000 0x1000>; 126 #interrupt-cells = <1>;
375 interrupts = <24>; 127 reg = <0x20200 0x10>, <0x20210 0x10>;
376 clocks = <&gate_clk 0>; 128 };
377 status = "okay"; 129
378 }; 130 bridge_intc: bridge-interrupt-ctrl@20110 {
379 131 compatible = "marvell,orion-bridge-intc";
380 ehci1: usb-host@51000 { 132 interrupt-controller;
381 compatible = "marvell,orion-ehci"; 133 #interrupt-cells = <1>;
382 reg = <0x51000 0x1000>; 134 reg = <0x20110 0x8>;
383 interrupts = <25>; 135 interrupts = <0>;
384 clocks = <&gate_clk 1>; 136 marvell,#interrupts = <5>;
385 status = "okay"; 137 };
386 }; 138
387 139 core_clk: core-clocks@d0214 {
388 sdio0: sdio-host@92000 { 140 compatible = "marvell,dove-core-clock";
389 compatible = "marvell,dove-sdhci"; 141 reg = <0xd0214 0x4>;
390 reg = <0x92000 0x100>; 142 #clock-cells = <1>;
391 interrupts = <35>, <37>; 143 };
392 clocks = <&gate_clk 8>; 144
393 pinctrl-0 = <&pmx_sdio0>; 145 gate_clk: clock-gating-ctrl@d0038 {
394 pinctrl-names = "default"; 146 compatible = "marvell,dove-gating-clock";
395 status = "disabled"; 147 reg = <0xd0038 0x4>;
396 }; 148 clocks = <&core_clk 0>;
397 149 #clock-cells = <1>;
398 sdio1: sdio-host@90000 { 150 };
399 compatible = "marvell,dove-sdhci"; 151
400 reg = <0x90000 0x100>; 152 thermal: thermal-diode@d001c {
401 interrupts = <36>, <38>; 153 compatible = "marvell,dove-thermal";
402 clocks = <&gate_clk 9>; 154 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
403 pinctrl-0 = <&pmx_sdio1>; 155 };
404 pinctrl-names = "default"; 156
405 status = "disabled"; 157 uart0: serial@12000 {
406 }; 158 compatible = "ns16550a";
407 159 reg = <0x12000 0x100>;
408 sata0: sata-host@a0000 { 160 reg-shift = <2>;
409 compatible = "marvell,orion-sata"; 161 interrupts = <7>;
410 reg = <0xa0000 0x2400>; 162 clocks = <&core_clk 0>;
411 interrupts = <62>; 163 status = "disabled";
412 clocks = <&gate_clk 3>; 164 };
413 nr-ports = <1>; 165
414 status = "disabled"; 166 uart1: serial@12100 {
415 }; 167 compatible = "ns16550a";
416 168 reg = <0x12100 0x100>;
417 rtc: real-time-clock@d8500 { 169 reg-shift = <2>;
418 compatible = "marvell,orion-rtc"; 170 interrupts = <8>;
419 reg = <0xd8500 0x20>; 171 clocks = <&core_clk 0>;
420 }; 172 pinctrl-0 = <&pmx_uart1>;
421 173 pinctrl-names = "default";
422 crypto: crypto-engine@30000 { 174 status = "disabled";
423 compatible = "marvell,orion-crypto"; 175 };
424 reg = <0x30000 0x10000>, 176
425 <0xc8000000 0x800>; 177 uart2: serial@12200 {
426 reg-names = "regs", "sram"; 178 compatible = "ns16550a";
427 interrupts = <31>; 179 reg = <0x12000 0x100>;
428 clocks = <&gate_clk 15>; 180 reg-shift = <2>;
429 status = "okay"; 181 interrupts = <9>;
430 }; 182 clocks = <&core_clk 0>;
431 183 status = "disabled";
432 xor0: dma-engine@60800 { 184 };
433 compatible = "marvell,orion-xor"; 185
434 reg = <0x60800 0x100 186 uart3: serial@12300 {
435 0x60a00 0x100>; 187 compatible = "ns16550a";
436 clocks = <&gate_clk 23>; 188 reg = <0x12100 0x100>;
437 status = "okay"; 189 reg-shift = <2>;
438 190 interrupts = <10>;
439 channel0 { 191 clocks = <&core_clk 0>;
440 interrupts = <39>; 192 status = "disabled";
441 dmacap,memcpy; 193 };
442 dmacap,xor; 194
443 }; 195 gpio0: gpio-ctrl@d0400 {
444 196 compatible = "marvell,orion-gpio";
445 channel1 { 197 #gpio-cells = <2>;
446 interrupts = <40>; 198 gpio-controller;
447 dmacap,memset; 199 reg = <0xd0400 0x20>;
448 dmacap,memcpy; 200 ngpios = <32>;
449 dmacap,xor; 201 interrupt-controller;
450 }; 202 #interrupt-cells = <2>;
451 }; 203 interrupts = <12>, <13>, <14>, <60>;
452 204 };
453 xor1: dma-engine@60900 { 205
454 compatible = "marvell,orion-xor"; 206 gpio1: gpio-ctrl@d0420 {
455 reg = <0x60900 0x100 207 compatible = "marvell,orion-gpio";
456 0x60b00 0x100>; 208 #gpio-cells = <2>;
457 clocks = <&gate_clk 24>; 209 gpio-controller;
458 status = "okay"; 210 reg = <0xd0420 0x20>;
459 211 ngpios = <32>;
460 channel0 { 212 interrupt-controller;
461 interrupts = <42>; 213 #interrupt-cells = <2>;
462 dmacap,memcpy; 214 interrupts = <61>;
463 dmacap,xor; 215 };
464 }; 216
465 217 gpio2: gpio-ctrl@e8400 {
466 channel1 { 218 compatible = "marvell,orion-gpio";
467 interrupts = <43>; 219 #gpio-cells = <2>;
468 dmacap,memset; 220 gpio-controller;
469 dmacap,memcpy; 221 reg = <0xe8400 0x0c>;
470 dmacap,xor; 222 ngpios = <8>;
471 }; 223 };
472 }; 224
473 225 pinctrl: pin-ctrl@d0200 {
474 mdio: mdio-bus@72004 { 226 compatible = "marvell,dove-pinctrl";
475 compatible = "marvell,orion-mdio"; 227 reg = <0xd0200 0x10>;
476 #address-cells = <1>; 228 clocks = <&gate_clk 22>;
477 #size-cells = <0>; 229
478 reg = <0x72004 0x84>; 230 pmx_gpio_0: pmx-gpio-0 {
479 interrupts = <30>; 231 marvell,pins = "mpp0";
480 clocks = <&gate_clk 2>; 232 marvell,function = "gpio";
481 status = "disabled"; 233 };
482 234
483 ethphy: ethernet-phy { 235 pmx_gpio_1: pmx-gpio-1 {
484 device-type = "ethernet-phy"; 236 marvell,pins = "mpp1";
485 /* set phy address in board file */ 237 marvell,function = "gpio";
486 }; 238 };
487 }; 239
488 240 pmx_gpio_2: pmx-gpio-2 {
489 eth: ethernet-controller@72000 { 241 marvell,pins = "mpp2";
490 compatible = "marvell,orion-eth"; 242 marvell,function = "gpio";
491 #address-cells = <1>; 243 };
492 #size-cells = <0>; 244
493 reg = <0x72000 0x4000>; 245 pmx_gpio_3: pmx-gpio-3 {
494 clocks = <&gate_clk 2>; 246 marvell,pins = "mpp3";
495 marvell,tx-checksum-limit = <1600>; 247 marvell,function = "gpio";
496 status = "disabled"; 248 };
497 249
498 ethernet-port@0 { 250 pmx_gpio_4: pmx-gpio-4 {
499 device_type = "network"; 251 marvell,pins = "mpp4";
500 compatible = "marvell,orion-eth-port"; 252 marvell,function = "gpio";
501 reg = <0>; 253 };
502 interrupts = <29>; 254
503 /* overwrite MAC address in bootloader */ 255 pmx_gpio_5: pmx-gpio-5 {
504 local-mac-address = [00 00 00 00 00 00]; 256 marvell,pins = "mpp5";
505 phy-handle = <&ethphy>; 257 marvell,function = "gpio";
258 };
259
260 pmx_gpio_6: pmx-gpio-6 {
261 marvell,pins = "mpp6";
262 marvell,function = "gpio";
263 };
264
265 pmx_gpio_7: pmx-gpio-7 {
266 marvell,pins = "mpp7";
267 marvell,function = "gpio";
268 };
269
270 pmx_gpio_8: pmx-gpio-8 {
271 marvell,pins = "mpp8";
272 marvell,function = "gpio";
273 };
274
275 pmx_gpio_9: pmx-gpio-9 {
276 marvell,pins = "mpp9";
277 marvell,function = "gpio";
278 };
279
280 pmx_gpio_10: pmx-gpio-10 {
281 marvell,pins = "mpp10";
282 marvell,function = "gpio";
283 };
284
285 pmx_gpio_11: pmx-gpio-11 {
286 marvell,pins = "mpp11";
287 marvell,function = "gpio";
288 };
289
290 pmx_gpio_12: pmx-gpio-12 {
291 marvell,pins = "mpp12";
292 marvell,function = "gpio";
293 };
294
295 pmx_gpio_13: pmx-gpio-13 {
296 marvell,pins = "mpp13";
297 marvell,function = "gpio";
298 };
299
300 pmx_gpio_14: pmx-gpio-14 {
301 marvell,pins = "mpp14";
302 marvell,function = "gpio";
303 };
304
305 pmx_gpio_15: pmx-gpio-15 {
306 marvell,pins = "mpp15";
307 marvell,function = "gpio";
308 };
309
310 pmx_gpio_16: pmx-gpio-16 {
311 marvell,pins = "mpp16";
312 marvell,function = "gpio";
313 };
314
315 pmx_gpio_17: pmx-gpio-17 {
316 marvell,pins = "mpp17";
317 marvell,function = "gpio";
318 };
319
320 pmx_gpio_18: pmx-gpio-18 {
321 marvell,pins = "mpp18";
322 marvell,function = "gpio";
323 };
324
325 pmx_gpio_19: pmx-gpio-19 {
326 marvell,pins = "mpp19";
327 marvell,function = "gpio";
328 };
329
330 pmx_gpio_20: pmx-gpio-20 {
331 marvell,pins = "mpp20";
332 marvell,function = "gpio";
333 };
334
335 pmx_gpio_21: pmx-gpio-21 {
336 marvell,pins = "mpp21";
337 marvell,function = "gpio";
338 };
339
340 pmx_camera: pmx-camera {
341 marvell,pins = "mpp_camera";
342 marvell,function = "camera";
343 };
344
345 pmx_camera_gpio: pmx-camera-gpio {
346 marvell,pins = "mpp_camera";
347 marvell,function = "gpio";
348 };
349
350 pmx_sdio0: pmx-sdio0 {
351 marvell,pins = "mpp_sdio0";
352 marvell,function = "sdio0";
353 };
354
355 pmx_sdio0_gpio: pmx-sdio0-gpio {
356 marvell,pins = "mpp_sdio0";
357 marvell,function = "gpio";
358 };
359
360 pmx_sdio1: pmx-sdio1 {
361 marvell,pins = "mpp_sdio1";
362 marvell,function = "sdio1";
363 };
364
365 pmx_sdio1_gpio: pmx-sdio1-gpio {
366 marvell,pins = "mpp_sdio1";
367 marvell,function = "gpio";
368 };
369
370 pmx_audio1_gpio: pmx-audio1-gpio {
371 marvell,pins = "mpp_audio1";
372 marvell,function = "gpio";
373 };
374
375 pmx_spi0: pmx-spi0 {
376 marvell,pins = "mpp_spi0";
377 marvell,function = "spi0";
378 };
379
380 pmx_spi0_gpio: pmx-spi0-gpio {
381 marvell,pins = "mpp_spi0";
382 marvell,function = "gpio";
383 };
384
385 pmx_uart1: pmx-uart1 {
386 marvell,pins = "mpp_uart1";
387 marvell,function = "uart1";
388 };
389
390 pmx_uart1_gpio: pmx-uart1-gpio {
391 marvell,pins = "mpp_uart1";
392 marvell,function = "gpio";
393 };
394
395 pmx_nand: pmx-nand {
396 marvell,pins = "mpp_nand";
397 marvell,function = "nand";
398 };
399
400 pmx_nand_gpo: pmx-nand-gpo {
401 marvell,pins = "mpp_nand";
402 marvell,function = "gpo";
403 };
404 };
405
406 spi0: spi-ctrl@10600 {
407 compatible = "marvell,orion-spi";
408 #address-cells = <1>;
409 #size-cells = <0>;
410 cell-index = <0>;
411 interrupts = <6>;
412 reg = <0x10600 0x28>;
413 clocks = <&core_clk 0>;
414 pinctrl-0 = <&pmx_spi0>;
415 pinctrl-names = "default";
416 status = "disabled";
417 };
418
419 spi1: spi-ctrl@14600 {
420 compatible = "marvell,orion-spi";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 cell-index = <1>;
424 interrupts = <5>;
425 reg = <0x14600 0x28>;
426 clocks = <&core_clk 0>;
427 status = "disabled";
428 };
429
430 i2c0: i2c-ctrl@11000 {
431 compatible = "marvell,mv64xxx-i2c";
432 reg = <0x11000 0x20>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 interrupts = <11>;
436 clock-frequency = <400000>;
437 timeout-ms = <1000>;
438 clocks = <&core_clk 0>;
439 status = "disabled";
440 };
441
442 ehci0: usb-host@50000 {
443 compatible = "marvell,orion-ehci";
444 reg = <0x50000 0x1000>;
445 interrupts = <24>;
446 clocks = <&gate_clk 0>;
447 status = "okay";
448 };
449
450 ehci1: usb-host@51000 {
451 compatible = "marvell,orion-ehci";
452 reg = <0x51000 0x1000>;
453 interrupts = <25>;
454 clocks = <&gate_clk 1>;
455 status = "okay";
456 };
457
458 sdio0: sdio-host@92000 {
459 compatible = "marvell,dove-sdhci";
460 reg = <0x92000 0x100>;
461 interrupts = <35>, <37>;
462 clocks = <&gate_clk 8>;
463 pinctrl-0 = <&pmx_sdio0>;
464 pinctrl-names = "default";
465 status = "disabled";
466 };
467
468 sdio1: sdio-host@90000 {
469 compatible = "marvell,dove-sdhci";
470 reg = <0x90000 0x100>;
471 interrupts = <36>, <38>;
472 clocks = <&gate_clk 9>;
473 pinctrl-0 = <&pmx_sdio1>;
474 pinctrl-names = "default";
475 status = "disabled";
476 };
477
478 sata0: sata-host@a0000 {
479 compatible = "marvell,orion-sata";
480 reg = <0xa0000 0x2400>;
481 interrupts = <62>;
482 clocks = <&gate_clk 3>;
483 nr-ports = <1>;
484 status = "disabled";
485 };
486
487 rtc: real-time-clock@d8500 {
488 compatible = "marvell,orion-rtc";
489 reg = <0xd8500 0x20>;
490 };
491
492 crypto: crypto-engine@30000 {
493 compatible = "marvell,orion-crypto";
494 reg = <0x30000 0x10000>,
495 <0xffffe000 0x800>;
496 reg-names = "regs", "sram";
497 interrupts = <31>;
498 clocks = <&gate_clk 15>;
499 status = "okay";
500 };
501
502 xor0: dma-engine@60800 {
503 compatible = "marvell,orion-xor";
504 reg = <0x60800 0x100
505 0x60a00 0x100>;
506 clocks = <&gate_clk 23>;
507 status = "okay";
508
509 channel0 {
510 interrupts = <39>;
511 dmacap,memcpy;
512 dmacap,xor;
513 };
514
515 channel1 {
516 interrupts = <40>;
517 dmacap,memcpy;
518 dmacap,xor;
519 };
520 };
521
522 xor1: dma-engine@60900 {
523 compatible = "marvell,orion-xor";
524 reg = <0x60900 0x100
525 0x60b00 0x100>;
526 clocks = <&gate_clk 24>;
527 status = "okay";
528
529 channel0 {
530 interrupts = <42>;
531 dmacap,memcpy;
532 dmacap,xor;
533 };
534
535 channel1 {
536 interrupts = <43>;
537 dmacap,memcpy;
538 dmacap,xor;
539 };
540 };
541
542 mdio: mdio-bus@72004 {
543 compatible = "marvell,orion-mdio";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 reg = <0x72004 0x84>;
547 interrupts = <30>;
548 clocks = <&gate_clk 2>;
549 status = "disabled";
550
551 ethphy: ethernet-phy {
552 device-type = "ethernet-phy";
553 /* set phy address in board file */
554 };
555 };
556
557 eth: ethernet-ctrl@72000 {
558 compatible = "marvell,orion-eth";
559 #address-cells = <1>;
560 #size-cells = <0>;
561 reg = <0x72000 0x4000>;
562 clocks = <&gate_clk 2>;
563 marvell,tx-checksum-limit = <1600>;
564 status = "disabled";
565
566 ethernet-port@0 {
567 device_type = "network";
568 compatible = "marvell,orion-eth-port";
569 reg = <0>;
570 interrupts = <29>;
571 /* overwrite MAC address in bootloader */
572 local-mac-address = [00 00 00 00 00 00];
573 phy-handle = <&ethphy>;
574 };
506 }; 575 };
507 }; 576 };
508 }; 577 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 02:27:54 -0400