Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d7165 clk: samsung: exynos4: fix g3d clocks
c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244af3 clk: samsung: exynos5260: fix typo in clock name
e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks

7 files changed, 257 insertions, 20 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index aadc9c59e2d1..f57d9dd9ea85 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -7,6 +7,8 @@ Required Properties:
 
 - compatible: should be one of the following.
   - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
+  - "samsung,exynos3250-cmu-dmc" - controller compatible with
+    Exynos3250 SoC for Dynamic Memory Controller domain.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
@@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in
 dt-bindings/clock/exynos3250.h header and can be used in device
 tree sources.
 
-Example 1: An example of a clock controller node is listed below.
+Example 1: Examples of clock controller nodes are listed below.
 
         cmu: clock-controller@10030000 {
                 compatible = "samsung,exynos3250-cmu";
@@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below.
                 #clock-cells = <1>;
         };
 
+        cmu_dmc: clock-controller@105C0000 {
+                compatible = "samsung,exynos3250-cmu-dmc";
+                reg = <0x105C0000 0x2000>;
+                #clock-cells = <1>;
+        };
+
 Example 2: UART controller node that consumes the clock generated by the clock
            controller. Refer to the standard clock bindings for information
            about 'clocks' and 'clock-names' property.
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 1d52de6370d5..72bf1b573788 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -163,6 +163,12 @@
                         #clock-cells = <1>;
                 };
 
+                cmu_dmc: clock-controller@105C0000 {
+                        compatible = "samsung,exynos3250-cmu-dmc";
+                        reg = <0x105C0000 0x2000>;
+                        #clock-cells = <1>;
+                };
+
                 rtc: rtc@10070000 {
                         compatible = "samsung,s3c6410-rtc";
                         reg = <0x10070000 0x100>;
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index dc85f8e7a2d7..6e6cca392082 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -110,7 +110,14 @@ enum exynos3250_plls {
         nr_plls
 };
 
+/* list of PLLs in DMC block to be registered */
+enum exynos3250_dmc_plls {
+        bpll, epll,
+        nr_dmc_plls
+};
+
 static void __iomem *reg_base;
+static void __iomem *dmc_reg_base;
 
 /*
  * Support for CMU save/restore across system suspends
@@ -266,6 +273,7 @@ PNAME(group_sclk_cam_blk_p)	= { "xxti", "xusbxti",
                                     "none", "none", "none",
                                     "none", "div_mpll_pre",
                                     "mout_epll_user", "mout_vpll",
+                                    "none", "none", "none",
                                     "div_cam_blk_320", };
 PNAME(group_sclk_fimd0_p)       = { "xxti", "xusbxti",
                                     "m_bitclkhsdiv4_2l", "none",
@@ -353,8 +361,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 
         /* SRC_FSYS */
         MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
-        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
-        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
+        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 
         /* SRC_PERIL0 */
         MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
@@ -423,7 +431,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
         DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
         DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
                 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
-        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
+        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
 
         /* DIV_FSYS0 */
         DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
@@ -724,6 +732,25 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
         { /* sentinel */ }
 };
 
+/* EPLL */
+static struct samsung_pll_rate_table exynos3250_epll_rates[] = {
+        PLL_36XX_RATE(800000000, 200, 3, 1,     0),
+        PLL_36XX_RATE(288000000,  96, 2, 2,     0),
+        PLL_36XX_RATE(192000000, 128, 2, 3,     0),
+        PLL_36XX_RATE(144000000,  96, 2, 3,     0),
+        PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
+        PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
+        PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
+        PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
+        PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
+        PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
+        PLL_36XX_RATE( 50000000, 200, 3, 5,     0),
+        PLL_36XX_RATE( 49152002, 131, 2, 5,  4719),
+        PLL_36XX_RATE( 48000000, 128, 2, 5,     0),
+        PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),
+        { /* sentinel */ }
+};
+
 /* VPLL */
 static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
         PLL_36XX_RATE(600000000, 100, 2, 1,     0),
@@ -821,3 +848,172 @@ static void __init exynos3250_cmu_init(struct device_node *np)
         samsung_clk_of_add_provider(np, ctx);
 }
 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define BPLL_LOCK               0x0118
+#define BPLL_CON0               0x0218
+#define BPLL_CON1               0x021c
+#define BPLL_CON2               0x0220
+#define SRC_DMC                 0x0300
+#define DIV_DMC1                0x0504
+#define GATE_BUS_DMC0           0x0700
+#define GATE_BUS_DMC1           0x0704
+#define GATE_BUS_DMC2           0x0708
+#define GATE_BUS_DMC3           0x070c
+#define GATE_SCLK_DMC           0x0800
+#define GATE_IP_DMC0            0x0900
+#define GATE_IP_DMC1            0x0904
+#define EPLL_LOCK               0x1110