clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation

The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index b0c660b484ee..940f02837b82 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -517,7 +517,7 @@ static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata
         FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
         FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
         FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
-        FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
+        FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
 };
 
 static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
@@ -719,7 +719,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
         DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
         DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
         DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-        DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
+        DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
         DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
         DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
         DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -768,7 +768,6 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
         DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
         DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
         DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-        DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
         DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
         DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
                         CLK_SET_RATE_PARENT, 0),
@@ -1485,7 +1484,7 @@ static void __init exynos4_clk_init(struct device_node *np,
                 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
                 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
                 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-                _get_rate("arm_clk"));
+                _get_rate("div_core2"));
 }