diff options
author | Markos Chandras <markos.chandras@imgtec.com> | 2014-04-14 10:42:31 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-30 09:57:44 -0400 |
commit | 16d21a812f6bfcbfa84ccc19d38abe797c71b73e (patch) | |
tree | c4f59ef3ae131b04ab53a6c5baf9cbfee5724694 | |
parent | a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61 (diff) |
MIPS: uasm: Add mflo uasm instruction
It will be used later on by bpf-jit
[ralf@linux-mips.org: Resolved conflict.]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-rw-r--r-- | arch/mips/include/asm/uasm.h | 1 | ||||
-rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm-micromips.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm-mips.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/uasm.c | 12 |
5 files changed, 11 insertions, 5 deletions
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 95954ba24d31..719a88401afa 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h | |||
@@ -133,6 +133,7 @@ Ip_u2s3u1(_lw); | |||
133 | Ip_u3u1u2(_lwx); | 133 | Ip_u3u1u2(_lwx); |
134 | Ip_u1u2u3(_mfc0); | 134 | Ip_u1u2u3(_mfc0); |
135 | Ip_u1(_mfhi); | 135 | Ip_u1(_mfhi); |
136 | Ip_u1(_mflo); | ||
136 | Ip_u1u2u3(_mtc0); | 137 | Ip_u1u2u3(_mtc0); |
137 | Ip_u3u1u2(_mul); | 138 | Ip_u3u1u2(_mul); |
138 | Ip_u3u1u2(_or); | 139 | Ip_u3u1u2(_or); |
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 67933839ce6a..4b7160259292 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h | |||
@@ -316,6 +316,7 @@ enum mm_32axf_minor_op { | |||
316 | mm_mfhi32_op = 0x035, | 316 | mm_mfhi32_op = 0x035, |
317 | mm_jalr_op = 0x03c, | 317 | mm_jalr_op = 0x03c, |
318 | mm_tlbr_op = 0x04d, | 318 | mm_tlbr_op = 0x04d, |
319 | mm_mflo32_op = 0x075, | ||
319 | mm_jalrhb_op = 0x07c, | 320 | mm_jalrhb_op = 0x07c, |
320 | mm_tlbwi_op = 0x08d, | 321 | mm_tlbwi_op = 0x08d, |
321 | mm_tlbwr_op = 0x0cd, | 322 | mm_tlbwr_op = 0x0cd, |
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c index 9d42f1066a1f..1c390a1f3862 100644 --- a/arch/mips/mm/uasm-micromips.c +++ b/arch/mips/mm/uasm-micromips.c | |||
@@ -89,6 +89,7 @@ static struct insn insn_table_MM[] = { | |||
89 | { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, | 89 | { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, |
90 | { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, | 90 | { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, |
91 | { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, | 91 | { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, |
92 | { insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS }, | ||
92 | { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, | 93 | { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, |
93 | { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD }, | 94 | { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD }, |
94 | { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, | 95 | { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, |
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index 9dd15168e849..4f9114b2ff34 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c | |||
@@ -96,6 +96,7 @@ static struct insn insn_table[] = { | |||
96 | { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, | 96 | { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, |
97 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, | 97 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, |
98 | { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD }, | 98 | { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD }, |
99 | { insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD }, | ||
99 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, | 100 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
100 | { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, | 101 | { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, |
101 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, | 102 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 1c8bed31ec3d..8cf1fb21cedf 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -51,11 +51,12 @@ enum opcode { | |||
51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, | 51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, |
52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, | 52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, |
53 | insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, | 53 | insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, |
54 | insn_mfc0, insn_mfhi, insn_mtc0, insn_mul, insn_or, insn_ori, insn_pref, | 54 | insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul, insn_or, |
55 | insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, | 55 | insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, |
56 | insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, | 56 | insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra, insn_srl, |
57 | insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, | 57 | insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, |
58 | insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield, | 58 | insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, |
59 | insn_xori, insn_yield, | ||
59 | }; | 60 | }; |
60 | 61 | ||
61 | struct insn { | 62 | struct insn { |
@@ -276,6 +277,7 @@ I_u1s2(_lui) | |||
276 | I_u2s3u1(_lw) | 277 | I_u2s3u1(_lw) |
277 | I_u1u2u3(_mfc0) | 278 | I_u1u2u3(_mfc0) |
278 | I_u1(_mfhi) | 279 | I_u1(_mfhi) |
280 | I_u1(_mflo) | ||
279 | I_u1u2u3(_mtc0) | 281 | I_u1u2u3(_mtc0) |
280 | I_u3u1u2(_mul) | 282 | I_u3u1u2(_mul) |
281 | I_u2u1u3(_ori) | 283 | I_u2u1u3(_ori) |