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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-10 21:27:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-10 21:27:51 -0400
commit12250d843e8489ee00b5b7726da855e51694e792 (patch)
tree905d1577a3d91cf9906628dd65648b0006c1893f
parentda06a8d7bed2f3bfc12979384b2d1247ec4873db (diff)
parent62885f59a26195d9f6a3f8c795225dfbab62a110 (diff)
Merge branch 'i2c-embedded/for-next' of git://git.pengutronix.de/git/wsa/linux
Pull i2c-embedded changes from Wolfram Sang: "The changes for i2c-embedded include: - massive rework of the omap driver - massive rework of the at91 driver. In fact, the old driver gets removed; I am okay with this approach since the old driver was depending on BROKEN and its limitations made it practically unusable, so people used bitbanging instead. But even if there are users, there is no platform_data or module parameter which would need to be converted. It is just another driver doing I2C transfers, just way better. Modifications of arch/arm/at91 related files have proper acks from the maintainer. - new driver for R-Car I2C - devicetree and generic_clock conversions and fixes - usual driver fixes and changes. The rework patches have come a long way and lots of people have been involved in creating/testing them. Most patches have been in linux-next at least since 3.6-rc5. A few have been added in the last week, I have to admit. An unexpected (but welcome :)) peak in private life is the cause for that. The "late" patches shouldn't cause any merge conflicts and I will have a special eye on them during the stabilization phase. This is an exception and I want to have the patches in place properly in time again for the next kernels." * 'i2c-embedded/for-next' of git://git.pengutronix.de/git/wsa/linux: (44 commits) MXS: Implement DMA support into mxs-i2c i2c: add Renesas R-Car I2C driver i2c: s3c2410: use clk_prepare_enable and clk_disable_unprepare ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints i2c: nomadik: Add Device Tree support to the Nomadik I2C driver i2c: algo: pca: Fix chip reset function for PCA9665 i2c: mpc: Wait for STOP to hit the bus i2c: davinci: preparation for switch to common clock framework omap-i2c: fix incorrect log message when using a device tree i2c: omap: sanitize exit path i2c: omap: switch over to autosuspend API i2c: omap: remove unnecessary pm_runtime_suspended check i2c: omap: switch to threaded IRQ support i2c: omap: remove redundant status read i2c: omap: get rid of the "complete" label i2c: omap: resize fifos before each message i2c: omap: simplify IRQ exit path i2c: omap: always return IRQ_HANDLED i2c: omap: simplify errata check i2c: omap: bus: add a receiver flag ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/i2c/atmel-i2c.txt30
-rw-r--r--Documentation/devicetree/bindings/i2c/davinci.txt28
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mxs.txt2
-rw-r--r--Documentation/devicetree/bindings/i2c/nomadik.txt23
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi10
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi10
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts12
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi30
-rw-r--r--arch/arm/boot/dts/imx28.dtsi2
-rw-r--r--arch/arm/mach-at91/at91rm9200.c1
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c3
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c8
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c14
-rw-r--r--arch/arm/mach-at91/at91sam9263.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c4
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c10
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c3
-rw-r--r--arch/arm/mach-at91/include/mach/at91_twi.h68
-rw-r--r--arch/arm/plat-omap/i2c.c21
-rw-r--r--drivers/i2c/algos/i2c-algo-pca.c27
-rw-r--r--drivers/i2c/busses/Kconfig27
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-at91.c667
-rw-r--r--drivers/i2c/busses/i2c-davinci.c58
-rw-r--r--drivers/i2c/busses/i2c-imx.c6
-rw-r--r--drivers/i2c/busses/i2c-mpc.c18
-rw-r--r--drivers/i2c/busses/i2c-mxs.c269
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c52
-rw-r--r--drivers/i2c/busses/i2c-omap.c474
-rw-r--r--drivers/i2c/busses/i2c-rcar.c709
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c18
-rw-r--r--include/linux/i2c-algo-pca.h1
-rw-r--r--include/linux/i2c-omap.h1
-rw-r--r--include/linux/i2c/i2c-rcar.h10
-rw-r--r--include/linux/platform_data/i2c-nomadik.h2
46 files changed, 2096 insertions, 597 deletions
diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
new file mode 100644
index 000000000000..b689a0d9441c
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
@@ -0,0 +1,30 @@
1I2C for Atmel platforms
2
3Required properties :
4- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c"
6 or "atmel,at91sam9x5-i2c"
7- reg: physical base address of the controller and length of memory mapped
8 region.
9- interrupts: interrupt number to the cpu.
10- #address-cells = <1>;
11- #size-cells = <0>;
12
13Optional properties:
14- Child nodes conforming to i2c bus binding
15
16Examples :
17
18i2c0: i2c@fff84000 {
19 compatible = "atmel,at91sam9g20-i2c";
20 reg = <0xfff84000 0x100>;
21 interrupts = <12 4 6>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 24c512@50 {
26 compatible = "24c512";
27 reg = <0x50>;
28 pagesize = <128>;
29 }
30}
diff --git a/Documentation/devicetree/bindings/i2c/davinci.txt b/Documentation/devicetree/bindings/i2c/davinci.txt
new file mode 100644
index 000000000000..2dc935b4113d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/davinci.txt
@@ -0,0 +1,28 @@
1* Texas Instruments Davinci I2C
2
3This file provides information, what the device node for the
4davinci i2c interface contain.
5
6Required properties:
7- compatible: "ti,davinci-i2c";
8- reg : Offset and length of the register set for the device
9
10Recommended properties :
11- interrupts : standard interrupt property.
12- clock-frequency : desired I2C bus clock frequency in Hz.
13
14Example (enbw_cmc board):
15 i2c@1c22000 {
16 compatible = "ti,davinci-i2c";
17 reg = <0x22000 0x1000>;
18 clock-frequency = <100000>;
19 interrupts = <15>;
20 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 dtt@48 {
25 compatible = "national,lm75";
26 reg = <0x48>;
27 };
28 };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
index 30ac3a0557f7..7a3fe9e5f4cb 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
@@ -6,6 +6,7 @@ Required properties:
6- interrupts: Should contain ERROR and DMA interrupts 6- interrupts: Should contain ERROR and DMA interrupts
7- clock-frequency: Desired I2C bus clock frequency in Hz. 7- clock-frequency: Desired I2C bus clock frequency in Hz.
8 Only 100000Hz and 400000Hz modes are supported. 8 Only 100000Hz and 400000Hz modes are supported.
9- fsl,i2c-dma-channel: APBX DMA channel for the I2C
9 10
10Examples: 11Examples:
11 12
@@ -16,4 +17,5 @@ i2c0: i2c@80058000 {
16 reg = <0x80058000 2000>; 17 reg = <0x80058000 2000>;
17 interrupts = <111 68>; 18 interrupts = <111 68>;
18 clock-frequency = <100000>; 19 clock-frequency = <100000>;
20 fsl,i2c-dma-channel = <6>;
19}; 21};
diff --git a/Documentation/devicetree/bindings/i2c/nomadik.txt b/Documentation/devicetree/bindings/i2c/nomadik.txt
new file mode 100644
index 000000000000..72065b0ff680
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nomadik.txt
@@ -0,0 +1,23 @@
1I2C for Nomadik based systems
2
3Required (non-standard) properties:
4 - Nil
5
6Recommended (non-standard) properties:
7 - clock-frequency : Maximum bus clock frequency for the device
8
9Optional (non-standard) properties:
10 - Nil
11
12Example :
13
14i2c@80004000 {
15 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
16 reg = <0x80004000 0x1000>;
17 interrupts = <0 21 0x4>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 v-i2c-supply = <&db8500_vape_reg>;
21
22 clock-frequency = <400000>;
23};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7c95f76398de..d410581a5a85 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -28,6 +28,7 @@
28 gpio2 = &pioC; 28 gpio2 = &pioC;
29 tcb0 = &tcb0; 29 tcb0 = &tcb0;
30 tcb1 = &tcb1; 30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
31 }; 32 };
32 cpus { 33 cpus {
33 cpu@0 { 34 cpu@0 {
@@ -202,6 +203,15 @@
202 status = "disabled"; 203 status = "disabled";
203 }; 204 };
204 205
206 i2c0: i2c@fffac000 {
207 compatible = "atmel,at91sam9260-i2c";
208 reg = <0xfffac000 0x100>;
209 interrupts = <11 4 6>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213 };
214
205 adc0: adc@fffe0000 { 215 adc0: adc@fffe0000 {
206 compatible = "atmel,at91sam9260-adc"; 216 compatible = "atmel,at91sam9260-adc";
207 reg = <0xfffe0000 0x100>; 217 reg = <0xfffe0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 195019b7ca0e..3e6e5c1abbf3 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -24,6 +24,7 @@
24 gpio3 = &pioD; 24 gpio3 = &pioD;
25 gpio4 = &pioE; 25 gpio4 = &pioE;
26 tcb0 = &tcb0; 26 tcb0 = &tcb0;
27 i2c0 = &i2c0;
27 }; 28 };
28 cpus { 29 cpus {
29 cpu@0 { 30 cpu@0 {
@@ -185,6 +186,15 @@
185 interrupts = <24 4 2>; 186 interrupts = <24 4 2>;
186 status = "disabled"; 187 status = "disabled";
187 }; 188 };
189
190 i2c0: i2c@fff88000 {
191 compatible = "atmel,at91sam9263-i2c";
192 reg = <0xfff88000 0x100>;
193 interrupts = <13 4 6>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 status = "disabled";
197 };
188 }; 198 };
189 199
190 nand0: nand@40000000 { 200 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 2a1d1ca8bd86..75ce6e760016 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -18,6 +18,10 @@
18 18
19 ahb { 19 ahb {
20 apb { 20 apb {
21 i2c0: i2c@fffac000 {
22 compatible = "atmel,at91sam9g20-i2c";
23 };
24
21 adc0: adc@fffe0000 { 25 adc0: adc@fffe0000 {
22 atmel,adc-startup-time = <40>; 26 atmel,adc-startup-time = <40>;
23 }; 27 };
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 96514c134e54..877c08f06763 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,18 @@
32 phy-mode = "rmii"; 32 phy-mode = "rmii";
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35
36 i2c0: i2c@f8010000 {
37 status = "okay";
38 };
39
40 i2c1: i2c@f8014000 {
41 status = "okay";
42 };
43
44 i2c2: i2c@f8018000 {
45 status = "okay";
46 };
35 }; 47 };
36 48
37 usb0: ohci@00600000 { 49 usb0: ohci@00600000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 63751b1e744b..3add030d61f8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -29,6 +29,8 @@
29 gpio4 = &pioE; 29 gpio4 = &pioE;
30 tcb0 = &tcb0; 30 tcb0 = &tcb0;
31 tcb1 = &tcb1; 31 tcb1 = &tcb1;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
32 }; 34 };
33 cpus { 35 cpus {
34 cpu@0 { 36 cpu@0 {
@@ -206,6 +208,24 @@
206 status = "disabled"; 208 status = "disabled";
207 }; 209 };
208 210
211 i2c0: i2c@fff84000 {
212 compatible = "atmel,at91sam9g10-i2c";
213 reg = <0xfff84000 0x100>;
214 interrupts = <12 4 6>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@fff88000 {
221 compatible = "atmel,at91sam9g10-i2c";
222 reg = <0xfff88000 0x100>;
223 interrupts = <13 4 6>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 status = "disabled";
227 };
228
209 adc0: adc@fffb0000 { 229 adc0: adc@fffb0000 {
210 compatible = "atmel,at91sam9260-adc"; 230 compatible = "atmel,at91sam9260-adc";
211 reg = <0xfffb0000 0x100>; 231 reg = <0xfffb0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd13111..15e1dd43f625 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -46,6 +46,14 @@
46 phy-mode = "rmii"; 46 phy-mode = "rmii";
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49
50 i2c0: i2c@fff84000 {
51 status = "okay";
52 };
53
54 i2c1: i2c@fff88000 {
55 status = "okay";
56 };
49 }; 57 };
50 58
51 nand0: nand@40000000 { 59 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ef9336ae9614..82508d68aa7e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -26,6 +26,8 @@
26 gpio3 = &pioD; 26 gpio3 = &pioD;
27 tcb0 = &tcb0; 27 tcb0 = &tcb0;
28 tcb1 = &tcb1; 28 tcb1 = &tcb1;
29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
29 }; 31 };
30 cpus { 32 cpus {
31 cpu@0 { 33 cpu@0 {
@@ -182,6 +184,24 @@
182 atmel,use-dma-tx; 184 atmel,use-dma-tx;
183 status = "disabled"; 185 status = "disabled";
184 }; 186 };
187
188 i2c0: i2c@f8010000 {
189 compatible = "atmel,at91sam9x5-i2c";
190 reg = <0xf8010000 0x100>;
191 interrupts = <9 4 6>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 status = "disabled";
195 };
196
197 i2c1: i2c@f8014000 {
198 compatible = "atmel,at91sam9x5-i2c";
199 reg = <0xf8014000 0x100>;
200 interrupts = <10 4 6>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 status = "disabled";
204 };
185 }; 205 };
186 206
187 nand0: nand@40000000 { 207 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index f4e43e38f3a1..912b2c283d6f 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -37,6 +37,14 @@
37 dbgu: serial@fffff200 { 37 dbgu: serial@fffff200 {
38 status = "okay"; 38 status = "okay";
39 }; 39 };
40
41 i2c0: i2c@f8010000 {
42 status = "okay";
43 };
44
45 i2c1: i2c@f8014000 {
46 status = "okay";
47 };
40 }; 48 };
41 49
42 nand0: nand@40000000 { 50 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8a387a8d61b7..03fc136421c5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -27,6 +27,9 @@
27 gpio3 = &pioD; 27 gpio3 = &pioD;
28 tcb0 = &tcb0; 28 tcb0 = &tcb0;
29 tcb1 = &tcb1; 29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
30 }; 33 };
31 cpus { 34 cpus {
32 cpu@0 { 35 cpu@0 {
@@ -196,6 +199,33 @@
196 status = "disabled"; 199 status = "disabled";
197 }; 200 };
198 201
202 i2c0: i2c@f8010000 {
203 compatible = "atmel,at91sam9x5-i2c";
204 reg = <0xf8010000 0x100>;
205 interrupts = <9 4 6>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 status = "disabled";
209 };
210
211 i2c1: i2c@f8014000 {
212 compatible = "atmel,at91sam9x5-i2c";
213 reg = <0xf8014000 0x100>;
214 interrupts = <10 4 6>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
218 };
219
220 i2c2: i2c@f8018000 {
221 compatible = "atmel,at91sam9x5-i2c";
222 reg = <0xf8018000 0x100>;
223 interrupts = <11 4 6>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 status = "disabled";
227 };
228
199 adc0: adc@f804c000 { 229 adc0: adc@f804c000 {
200 compatible = "atmel,at91sam9260-adc"; 230 compatible = "atmel,at91sam9260-adc";
201 reg = <0xf804c000 0x100>; 231 reg = <0xf804c000 0x100>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 59fbfba23df8..e16d63155480 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -764,6 +764,7 @@
764 reg = <0x80058000 0x2000>; 764 reg = <0x80058000 0x2000>;
765 interrupts = <111 68>; 765 interrupts = <111 68>;
766 clock-frequency = <100000>; 766 clock-frequency = <100000>;
767 fsl,i2c-dma-channel = <6>;
767 status = "disabled"; 768 status = "disabled";
768 }; 769 };
769 770
@@ -774,6 +775,7 @@
774 reg = <0x8005a000 0x2000>; 775 reg = <0x8005a000 0x2000>;
775 interrupts = <110 69>; 776 interrupts = <110 69>;
776 clock-frequency = <100000>; 777 clock-frequency = <100000>;
778 fsl,i2c-dma-channel = <7>;
777 status = "disabled"; 779 status = "disabled";
778 }; 780 };
779 781
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6f50c6722276..b4f0565aff63 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -187,6 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
187 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 187 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
188 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 188 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
189 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), 189 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
190 /* fake hclk clock */ 191 /* fake hclk clock */
191 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 192 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
192 CLKDEV_CON_ID("pioA", &pioA_clk), 193 CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 9ac427a702da..a563189cdfc3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -511,7 +511,7 @@ static struct resource twi_resources[] = {
511}; 511};
512 512
513static struct platform_device at91rm9200_twi_device = { 513static struct platform_device at91rm9200_twi_device = {
514 .name = "at91_i2c", 514 .name = "i2c-at91rm9200",
515 .id = -1, 515 .id = -1,
516 .resource = twi_resources, 516 .resource = twi_resources,
517 .num_resources = ARRAY_SIZE(twi_resources), 517 .num_resources = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26a4668..ad29f93f20ca 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -211,6 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
211 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), 211 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
212 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), 212 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
213 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), 213 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
214 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
215 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20", &twi_clk),
214 /* more usart lookup table for DT entries */ 216 /* more usart lookup table for DT entries */
215 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 217 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
216 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), 218 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
@@ -219,6 +221,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
219 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), 221 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
220 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk), 222 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
221 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), 223 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
222 /* more tc lookup table for DT entries */ 225 /* more tc lookup table for DT entries */
223 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), 226 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
224 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), 227 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index af50ff3281c7..a76b8684f52d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -421,7 +421,6 @@ static struct resource twi_resources[] = {
421}; 421};
422 422
423static struct platform_device at91sam9260_twi_device = { 423static struct platform_device at91sam9260_twi_device = {
424 .name = "at91_i2c",
425 .id = -1, 424 .id = -1,
426 .resource = twi_resources, 425 .resource = twi_resources,
427 .num_resources = ARRAY_SIZE(twi_resources), 426 .num_resources = ARRAY_SIZE(twi_resources),
@@ -429,6 +428,13 @@ static struct platform_device at91sam9260_twi_device = {
429 428
430void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 429void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
431{ 430{
431 /* IP version is not the same on 9260 and g20 */
432 if (cpu_is_at91sam9g20()) {
433 at91sam9260_twi_device.name = "i2c-at91sam9g20";
434 } else {
435 at91sam9260_twi_device.name = "i2c-at91sam9260";
436 }
437
432 /* pins used for TWI interface */ 438 /* pins used for TWI interface */
433 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ 439 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
434 at91_set_multi_drive(AT91_PIN_PA23, 1); 440 at91_set_multi_drive(AT91_PIN_PA23, 1);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index f40762c5fede..8d999eb1a137 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -178,6 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
178 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 178 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
179 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), 179 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
180 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), 180 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
181 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk),
182 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk),
181 CLKDEV_CON_ID("pioA", &pioA_clk), 183 CLKDEV_CON_ID("pioA", &pioA_clk),
182 CLKDEV_CON_ID("pioB", &pioB_clk), 184 CLKDEV_CON_ID("pioB", &pioB_clk),
183 CLKDEV_CON_ID("pioC", &pioC_clk), 185 CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 11e9fa835cde..9752f17efba9 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -317,7 +317,6 @@ static struct resource twi_resources[] = {
317}; 317};
318 318
319static struct platform_device at91sam9261_twi_device = { 319static struct platform_device at91sam9261_twi_device = {
320 .name = "at91_i2c",
321 .id = -1, 320 .id = -1,
322 .resource = twi_resources, 321 .resource = twi_resources,
323 .num_resources = ARRAY_SIZE(twi_resources), 322 .num_resources = ARRAY_SIZE(twi_resources),
@@ -325,12 +324,19 @@ static struct platform_device at91sam9261_twi_device = {
325 324
326void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 325void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
327{ 326{
327 /* IP version is not the same on 9261 and g10 */
328 if (cpu_is_at91sam9g10()) {
329 at91sam9261_twi_device.name = "i2c-at91sam9g10";
330 /* I2C PIO must not be configured as open-drain on this chip */
331 } else {
332 at91sam9261_twi_device.name = "i2c-at91sam9261";
333 at91_set_multi_drive(AT91_PIN_PA7, 1);
334 at91_set_multi_drive(AT91_PIN_PA8, 1);
335 }
336
328 /* pins used for TWI interface */ 337 /* pins used for TWI interface */
329 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ 338 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
330 at91_set_multi_drive(AT91_PIN_PA7, 1);
331
332 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ 339 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
333 at91_set_multi_drive(AT91_PIN_PA8, 1);
334 340
335 i2c_register_board_info(0, devices, nr_devices); 341 i2c_register_board_info(0, devices, nr_devices);
336 platform_device_register(&at91sam9261_twi_device); 342 platform_device_register(&at91sam9261_twi_device);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 144ef5de51b6..6a01d0360dfb 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -193,6 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), 193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), 194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), 195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
196 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
196 /* fake hclk clock */ 197 /* fake hclk clock */
197 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 198 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
198 CLKDEV_CON_ID("pioA", &pioA_clk), 199 CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -210,6 +211,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
210 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk), 211 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
211 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), 212 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
212 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), 213 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
214 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
213}; 215};
214 216
215static struct clk_lookup usart_clocks_lookups[] = { 217static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7c0898fe20fa..8dde220b42b6 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -599,7 +599,7 @@ static struct resource twi_resources[] = {
599}; 599};
600 600
601static struct platform_device at91sam9263_twi_device = { 601static struct platform_device at91sam9263_twi_device = {
602 .name = "at91_i2c", 602 .name = "i2c-at91sam9260",
603 .id = -1, 603 .id = -1,
604 .resource = twi_resources, 604 .resource = twi_resources,
605 .num_resources = ARRAY_SIZE(twi_resources), 605 .num_resources = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd52e3c..84af1b506d92 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
237 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), 237 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
238 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), 238 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
239 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), 239 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
240 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
241 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
240 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 242 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
241 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 243 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
242 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), 244 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
@@ -254,6 +256,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
254 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk), 256 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
255 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk), 257 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
256 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk), 258 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
259 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
260 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
257 /* fake hclk clock */ 261 /* fake hclk clock */
258 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 262 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
259 CLKDEV_CON_ID("pioA", &pioA_clk), 263 CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index e4c3b3709204..b1596072dcc2 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -653,7 +653,7 @@ static struct resource twi0_resources[] = {
653}; 653};
654 654
655static struct platform_device at91sam9g45_twi0_device = { 655static struct platform_device at91sam9g45_twi0_device = {
656 .name = "at91_i2c", 656 .name = "i2c-at91sam9g10",
657 .id = 0, 657 .id = 0,
658 .resource = twi0_resources, 658 .resource = twi0_resources,
659 .num_resources = ARRAY_SIZE(twi0_resources), 659 .num_resources = ARRAY_SIZE(twi0_resources),
@@ -673,7 +673,7 @@ static struct resource twi1_resources[] = {
673}; 673};
674 674
675static struct platform_device at91sam9g45_twi1_device = { 675static struct platform_device at91sam9g45_twi1_device = {
676 .name = "at91_i2c", 676 .name = "i2c-at91sam9g10",
677 .id = 1, 677 .id = 1,
678 .resource = twi1_resources, 678 .resource = twi1_resources,
679 .num_resources = ARRAY_SIZE(twi1_resources), 679 .num_resources = ARRAY_SIZE(twi1_resources),
@@ -686,18 +686,12 @@ void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, in
686 /* pins used for TWI interface */ 686 /* pins used for TWI interface */
687 if (i2c_id == 0) { 687 if (i2c_id == 0) {
688 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */ 688 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
689 at91_set_multi_drive(AT91_PIN_PA20, 1);
690
691 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */ 689 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
692 at91_set_multi_drive(AT91_PIN_PA21, 1);
693 690
694 platform_device_register(&at91sam9g45_twi0_device); 691 platform_device_register(&at91sam9g45_twi0_device);
695 } else { 692 } else {
696 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */ 693 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
697 at91_set_multi_drive(AT91_PIN_PB10, 1);
698
699 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */ 694 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
700 at91_set_multi_drive(AT91_PIN_PB11, 1);
701 695
702 platform_device_register(&at91sam9g45_twi1_device); 696 platform_device_register(&at91sam9g45_twi1_device);
703 } 697 }
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 08494664ab78..732d3d3f4ec5 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), 169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), 170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), 171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
172 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
172 CLKDEV_CON_ID("pioA", &pioAB_clk), 174 CLKDEV_CON_ID("pioA", &pioAB_clk),
173 CLKDEV_CON_ID("pioB", &pioAB_clk), 175 CLKDEV_CON_ID("pioB", &pioAB_clk),
174 CLKDEV_CON_ID("pioC", &pioCD_clk), 176 CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72ce50a50de5..72e908412222 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -186,6 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), 186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
187 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 187 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
188 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 188 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
189 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
189 CLKDEV_CON_ID("pioA", &pioA_clk), 191 CLKDEV_CON_ID("pioA", &pioA_clk),
190 CLKDEV_CON_ID("pioB", &pioB_clk), 192 CLKDEV_CON_ID("pioB", &pioB_clk),
191 CLKDEV_CON_ID("pioC", &pioC_clk), 193 CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index deafea0e493d..d6ca0543ce8d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -346,7 +346,7 @@ static struct resource twi_resources[] = {
346}; 346};
347 347
348static struct platform_device at91sam9rl_twi_device = { 348static struct platform_device at91sam9rl_twi_device = {
349 .name = "at91_i2c", 349 .name = "i2c-at91sam9g20",
350 .id = -1, 350 .id = -1,
351 .resource = twi_resources, 351 .resource = twi_resources,
352 .num_resources = ARRAY_SIZE(twi_resources), 352 .num_resources = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d06672..e5035380dcbc 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,6 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
231 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk), 231 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
232 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk), 232 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
233 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk), 233 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
234 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
235 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
236 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
234 CLKDEV_CON_ID("pioA", &pioAB_clk), 237 CLKDEV_CON_ID("pioA", &pioAB_clk),
235 CLKDEV_CON_ID("pioB", &pioAB_clk), 238 CLKDEV_CON_ID("pioB", &pioAB_clk),
236 CLKDEV_CON_ID("pioC", &pioCD_clk), 239 CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h
deleted file mode 100644
index bb2880f6ba37..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_twi.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_twi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Two-wire Interface (TWI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_TWI_H
17#define AT91_TWI_H
18
19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
25#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
26#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
27
28#define AT91_TWI_MMR 0x04 /* Master Mode Register */
29#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
30#define AT91_TWI_IADRSZ_NO (0 << 8)
31#define AT91_TWI_IADRSZ_1 (1 << 8)
32#define AT91_TWI_IADRSZ_2 (2 << 8)
33#define AT91_TWI_IADRSZ_3 (3 << 8)
34#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
35#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
36
37#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
38#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
39
40#define AT91_TWI_IADR 0x0c /* Internal Address Register */
41
42#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
43#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
44#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
45#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
46
47#define AT91_TWI_SR 0x20 /* Status Register */
48#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
49#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
50#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
51#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
52#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
53#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
54#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
55#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
56#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
57#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
58#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
59#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
60
61#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
62#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
63#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
64#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
65#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
66
67#endif
68
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 6013831a043e..a5683a84c6ee 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,14 +26,12 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c-omap.h>
30#include <linux/slab.h> 29#include <linux/slab.h>
31#include <linux/err.h> 30#include <linux/err.h>
32#include <linux/clk.h> 31#include <linux/clk.h>
33 32
34#include <mach/irqs.h> 33#include <mach/irqs.h>
35#include <plat/i2c.h> 34#include <plat/i2c.h>
36#include <plat/omap-pm.h>
37#include <plat/omap_device.h> 35#include <plat/omap_device.h>
38 36
39#define OMAP_I2C_SIZE 0x3f 37#define OMAP_I2C_SIZE 0x3f
@@ -129,16 +127,6 @@ static inline int omap1_i2c_add_bus(int bus_id)
129 127
130 128
131#ifdef CONFIG_ARCH_OMAP2PLUS 129#ifdef CONFIG_ARCH_OMAP2PLUS
132/*
133 * XXX This function is a temporary compatibility wrapper - only
134 * needed until the I2C driver can be converted to call
135 * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
136 */
137static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
138{
139 omap_pm_set_max_mpu_wakeup_lat(dev, t);
140}
141
142static inline int omap2_i2c_add_bus(int bus_id) 130static inline int omap2_i2c_add_bus(int bus_id)
143{ 131{
144 int l; 132 int l;
@@ -170,15 +158,6 @@ static inline int omap2_i2c_add_bus(int bus_id)
170 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; 158 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
171 pdata->flags = dev_attr->flags; 159 pdata->flags = dev_attr->flags;
172 160
173 /*
174 * When waiting for completion of a i2c transfer, we need to
175 * set a wake up latency constraint for the MPU. This is to
176 * ensure quick enough wakeup from idle, when transfer
177 * completes.
178 * Only omap3 has support for constraints
179 */
180 if (cpu_is_omap34xx())
181 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
182 pdev = omap_device_build(name, bus_id, oh, pdata, 161 pdev = omap_device_build(name, bus_id, oh, pdata,
183 sizeof(struct omap_i2c_bus_platform_data), 162 sizeof(struct omap_i2c_bus_platform_data),
184 NULL, 0, 0); 163 NULL, 0, 0);
diff --git a/drivers/i2c/algos/i2c-algo-pca.c b/drivers/i2c/algos/i2c-algo-pca.c
index 6f5f98d69af7..f892a424009b 100644
--- a/drivers/i2c/algos/i2c-algo-pca.c
+++ b/drivers/i2c/algos/i2c-algo-pca.c
@@ -46,14 +46,19 @@ static int i2c_debug;
46#define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val) 46#define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val)
47#define pca_get_con(adap) pca_inw(adap, I2C_PCA_CON) 47#define pca_get_con(adap) pca_inw(adap, I2C_PCA_CON)
48#define pca_wait(adap) adap->wait_for_completion(adap->data) 48#define pca_wait(adap) adap->wait_for_completion(adap->data)
49#define pca_reset(adap) adap->reset_chip(adap->data)
50 49
51static void pca9665_reset(void *pd) 50static void pca_reset(struct i2c_algo_pca_data *adap)
52{ 51{
53 struct i2c_algo_pca_data *adap = pd; 52 if (adap->chip == I2C_PCA_CHIP_9665) {
54 pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_IPRESET); 53 /* Ignore the reset function from the module,
55 pca_outw(adap, I2C_PCA_IND, 0xA5); 54 * we can use the parallel bus reset.
56 pca_outw(adap, I2C_PCA_IND, 0x5A); 55 */
56 pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_IPRESET);
57 pca_outw(adap, I2C_PCA_IND, 0xA5);
58 pca_outw(adap, I2C_PCA_IND, 0x5A);
59 } else {
60 adap->reset_chip(adap->data);
61 }
57} 62}
58 63
59/* 64/*
@@ -378,11 +383,12 @@ static unsigned int pca_probe_chip(struct i2c_adapter *adap)
378 pca_outw(pca_data, I2C_PCA_INDPTR, I2C_PCA_IADR); 383 pca_outw(pca_data, I2C_PCA_INDPTR, I2C_PCA_IADR);
379 if (pca_inw(pca_data, I2C_PCA_IND) == 0xAA) { 384 if (pca_inw(pca_data, I2C_PCA_IND) == 0xAA) {
380 printk(KERN_INFO "%s: PCA9665 detected.\n", adap->name); 385 printk(KERN_INFO "%s: PCA9665 detected.\n", adap->name);
381 return I2C_PCA_CHIP_9665; 386 pca_data->chip = I2C_PCA_CHIP_9665;
382 } else { 387 } else {
383 printk(KERN_INFO "%s: PCA9564 detected.\n", adap->name); 388 printk(KERN_INFO "%s: PCA9564 detected.\n", adap->name);
384 return I2C_PCA_CHIP_9564; 389 pca_data->chip = I2C_PCA_CHIP_9564;
385 } 390 }
391 return pca_data->chip;
386} 392}
387 393
388static int pca_init(struct i2c_adapter *adap) 394static int pca_init(struct i2c_adapter *adap)
@@ -456,11 +462,6 @@ static int pca_init(struct i2c_adapter *adap)
456 */ 462 */
457 int raise_fall_time; 463 int raise_fall_time;
458 464
459 /* Ignore the reset function from the module,
460 * we can use the parallel bus reset
461 */
462 pca_data->reset_chip = pca9665_reset;
463
464 if (pca_data->i2c_clock > 1265800) { 465 if (pca_data->i2c_clock > 1265800) {
465 printk(KERN_WARNING "%s: I2C clock speed too high." 466 printk(KERN_WARNING "%s: I2C clock speed too high."
466 " Using 1265.8kHz.\n", adap->name); 467 " Using 1265.8kHz.\n", adap->name);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index ff01c389e2da..65dd599a0262 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -294,18 +294,21 @@ comment "I2C system bus drivers (mostly embedded / system-on-chip)"
294 294
295config I2C_AT91 295config I2C_AT91
296 tristate "Atmel AT91 I2C Two-Wire interface (TWI)" 296 tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
297 depends on ARCH_AT91 && EXPERIMENTAL && BROKEN 297 depends on ARCH_AT91 && EXPERIMENTAL
298 help 298 help
299 This supports the use of the I2C interface on Atmel AT91 299 This supports the use of the I2C interface on Atmel AT91
300 processors. 300 processors.
301 301
302 This driver is BROKEN because the controller which it uses 302 A serious problem is that there is no documented way to issue
303 will easily trigger RX overrun and TX underrun errors. Using 303 repeated START conditions for more than two messages, as needed
304 low I2C clock rates may partially work around those issues
305 on some systems. Another serious problem is that there is no
306 documented way to issue repeated START conditions, as needed
307 to support combined I2C messages. Use the i2c-gpio driver 304 to support combined I2C messages. Use the i2c-gpio driver
308 unless your system can cope with those limitations. 305 unless your system can cope with this limitation.
306
307 Caution! at91rm9200, at91sam9261, at91sam9260, at91sam9263 devices
308 don't have clock stretching in transmission mode. For that reason,
309 you can encounter underrun issues causing premature stop sendings if
310 the latency to fill the transmission register is too long. If you
311 are facing this situation, use the i2c-gpio driver.
309 312
310config I2C_AU1550 313config I2C_AU1550
311 tristate "Au1550/Au1200/Au1300 SMBus interface" 314 tristate "Au1550/Au1200/Au1300 SMBus interface"
@@ -718,6 +721,16 @@ config I2C_XLR
718 This driver can also be built as a module. If so, the module 721 This driver can also be built as a module. If so, the module
719 will be called i2c-xlr. 722 will be called i2c-xlr.
720 723
724config I2C_RCAR
725 tristate "Renesas R-Car I2C Controller"
726 depends on ARCH_SHMOBILE && I2C
727 help
728 If you say yes to this option, support will be included for the
729 R-Car I2C controller.
730
731 This driver can also be built as a module. If so, the module
732 will be called i2c-rcar.
733
721comment "External I2C/SMBus adapter drivers" 734comment "External I2C/SMBus adapter drivers"
722 735
723config I2C_DIOLAN_U2C 736config I2C_DIOLAN_U2C
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 37c4182cc98b..2d33d62952c1 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
71obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 71obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
72obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o 72obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
73obj-$(CONFIG_I2C_XLR) += i2c-xlr.o 73obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
74obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
74 75
75# External I2C/SMBus adapter drivers 76# External I2C/SMBus adapter drivers
76obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o 77obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index e24484beef07..aa59a254be2c 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -1,315 +1,554 @@
1/* 1/*
2 i2c Support for Atmel's AT91 Two-Wire Interface (TWI) 2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
3 3 *
4 Copyright (C) 2004 Rick Bronson 4 * Copyright (C) 2011 Weinmann Medical GmbH
5 Converted to 2.6 by Andrew Victor <andrew@sanpeople.com> 5 * Author: Nikolaus Voss <n.voss@weinmann.de>
6 6 *
7 Borrowed heavily from original work by: 7 * Evolved from original work by:
8 Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> 8 * Copyright (C) 2004 Rick Bronson
9 9 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
10 This program is free software; you can redistribute it and/or modify 10 *
11 it under the terms of the GNU General Public License as published by 11 * Borrowed heavily from original work by:
12 the Free Software Foundation; either version 2 of the License, or 12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
13 (at your option) any later version. 13 *
14*/ 14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */
15 19
16#include <linux/module.h> 20#include <linux/clk.h>
17#include <linux/kernel.h> 21#include <linux/completion.h>
18#include <linux/err.h> 22#include <linux/err.h>
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/delay.h>
22#include <linux/i2c.h> 23#include <linux/i2c.h>
23#include <linux/init.h> 24#include <linux/interrupt.h>
24#include <linux/clk.h>
25#include <linux/platform_device.h>
26#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/of_i2c.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32
33#define TWI_CLK_HZ 100000 /* max 400 Kbits/s */
34#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
35
36/* AT91 TWI register definitions */
37#define AT91_TWI_CR 0x0000 /* Control Register */
38#define AT91_TWI_START 0x0001 /* Send a Start Condition */
39#define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */
40#define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
41#define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
42#define AT91_TWI_SWRST 0x0080 /* Software Reset */
43
44#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
45#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
46#define AT91_TWI_MREAD 0x1000 /* Master Read Direction */
47
48#define AT91_TWI_IADR 0x000c /* Internal Address Register */
49
50#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
51
52#define AT91_TWI_SR 0x0020 /* Status Register */
53#define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */
54#define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */
55#define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */
27 56
28#include <mach/at91_twi.h> 57#define AT91_TWI_OVRE 0x0040 /* Overrun Error */
29#include <mach/board.h> 58#define AT91_TWI_UNRE 0x0080 /* Underrun Error */
30#include <mach/cpu.h> 59#define AT91_TWI_NACK 0x0100 /* Not Acknowledged */
31 60
32#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */ 61#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
62#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
63#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
64#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
65#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
33 66
67struct at91_twi_pdata {
68 unsigned clk_max_div;
69 unsigned clk_offset;
70 bool has_unre_flag;
71};
72
73struct at91_twi_dev {
74 struct device *dev;
75 void __iomem *base;
76 struct completion cmd_complete;
77 struct clk *clk;
78 u8 *buf;
79 size_t buf_len;
80 struct i2c_msg *msg;
81 int irq;
82 unsigned transfer_status;
83 struct i2c_adapter adapter;
84 unsigned twi_cwgr_reg;
85 struct at91_twi_pdata *pdata;
86};
34 87
35static struct clk *twi_clk; 88static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
36static void __iomem *twi_base; 89{
90 return readl_relaxed(dev->base + reg);
91}
92
93static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
94{
95 writel_relaxed(val, dev->base + reg);
96}
37 97
38#define at91_twi_read(reg) __raw_readl(twi_base + (reg)) 98static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
39#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg)) 99{
100 at91_twi_write(dev, AT91_TWI_IDR,
101 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
102}
40 103
104static void at91_init_twi_bus(struct at91_twi_dev *dev)
105{
106 at91_disable_twi_interrupts(dev);
107 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
108 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
109 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
110 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
111}
41 112
42/* 113/*
43 * Initialize the TWI hardware registers. 114 * Calculate symmetric clock as stated in datasheet:
115 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
44 */ 116 */
45static void __devinit at91_twi_hwinit(void) 117static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
46{ 118{
47 unsigned long cdiv, ckdiv; 119 int ckdiv, cdiv, div;
48 120 struct at91_twi_pdata *pdata = dev->pdata;
49 at91_twi_write(AT91_TWI_IDR, 0xffffffff); /* Disable all interrupts */ 121 int offset = pdata->clk_offset;
50 at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); /* Reset peripheral */ 122 int max_ckdiv = pdata->clk_max_div;
51 at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */ 123
52 124 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
53 /* Calcuate clock dividers */ 125 2 * twi_clk) - offset);
54 cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3; 126 ckdiv = fls(div >> 8);
55 cdiv = cdiv + 1; /* round up */ 127 cdiv = div >> ckdiv;
56 ckdiv = 0; 128
57 while (cdiv > 255) { 129 if (ckdiv > max_ckdiv) {
58 ckdiv++; 130 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
59 cdiv = cdiv >> 1; 131 ckdiv, max_ckdiv);
132 ckdiv = max_ckdiv;
133 cdiv = 255;
60 } 134 }
61 135
62 if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */ 136 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
63 if (ckdiv > 5) { 137 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
64 printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n"); 138}
65 ckdiv = 5;
66 }
67 }
68 139
69 at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv); 140static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
141{
142 if (dev->buf_len <= 0)
143 return;
144
145 at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
146
147 /* send stop when last byte has been written */
148 if (--dev->buf_len == 0)
149 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
150
151 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
152
153 ++dev->buf;
70} 154}
71 155
72/* 156static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
73 * Poll the i2c status register until the specified bit is set.
74 * Returns 0 if timed out (100 msec).
75 */
76static short at91_poll_status(unsigned long bit)
77{ 157{
78 int loop_cntr = 10000; 158 if (dev->buf_len <= 0)
159 return;
160
161 *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
162 --dev->buf_len;
163
164 /* handle I2C_SMBUS_BLOCK_DATA */
165 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
166 dev->msg->flags &= ~I2C_M_RECV_LEN;
167 dev->buf_len += *dev->buf;
168 dev->msg->len = dev->buf_len + 1;
169 dev_dbg(dev->dev, "received block length %d\n", dev->buf_len);
170 }
171
172 /* send stop if second but last byte has been read */
173 if (dev->buf_len == 1)
174 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
79 175
80 do { 176 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
81 udelay(10);
82 } while (!(at91_twi_read(AT91_TWI_SR) & bit) && (--loop_cntr > 0));
83 177
84 return (loop_cntr > 0); 178 ++dev->buf;
85} 179}
86 180
87static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length) 181static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
88{ 182{
89 /* Send Start */ 183 struct at91_twi_dev *dev = dev_id;
90 at91_twi_write(AT91_TWI_CR, AT91_TWI_START); 184 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
91 185 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
92 /* Read data */ 186
93 while (length--) { 187 if (!irqstatus)
94 if (!length) /* need to send Stop before reading last byte */ 188 return IRQ_NONE;
95 at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP); 189 else if (irqstatus & AT91_TWI_RXRDY)
96 if (!at91_poll_status(AT91_TWI_RXRDY)) { 190 at91_twi_read_next_byte(dev);
97 dev_dbg(&adap->dev, "RXRDY timeout\n"); 191 else if (irqstatus & AT91_TWI_TXRDY)
98 return -ETIMEDOUT; 192 at91_twi_write_next_byte(dev);
99 } 193
100 *buf++ = (at91_twi_read(AT91_TWI_RHR) & 0xff); 194 /* catch error flags */
195 dev->transfer_status |= status;
196
197 if (irqstatus & AT91_TWI_TXCOMP) {
198 at91_disable_twi_interrupts(dev);
199 complete(&dev->cmd_complete);
101 } 200 }
102 201
103 return 0; 202 return IRQ_HANDLED;
104} 203}
105 204
106static int xfer_write(struct i2c_adapter *adap, unsigned char *buf, int length) 205static int at91_do_twi_transfer(struct at91_twi_dev *dev)
107{ 206{
108 /* Load first byte into transmitter */ 207 int ret;
109 at91_twi_write(AT91_TWI_THR, *buf++); 208 bool has_unre_flag = dev->pdata->has_unre_flag;
110 209
111 /* Send Start */ 210 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
112 at91_twi_write(AT91_TWI_CR, AT91_TWI_START); 211 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
113 212
114 do { 213 INIT_COMPLETION(dev->cmd_complete);
115 if (!at91_poll_status(AT91_TWI_TXRDY)) { 214 dev->transfer_status = 0;
116 dev_dbg(&adap->dev, "TXRDY timeout\n"); 215 if (dev->msg->flags & I2C_M_RD) {
117 return -ETIMEDOUT; 216 unsigned start_flags = AT91_TWI_START;
118 }
119 217
120 length--; /* byte was transmitted */ 218 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
219 dev_err(dev->dev, "RXRDY still set!");
220 at91_twi_read(dev, AT91_TWI_RHR);
221 }
121 222
122 if (length > 0) /* more data to send? */ 223 /* if only one byte is to be read, immediately stop transfer */
123 at91_twi_write(AT91_TWI_THR, *buf++); 224 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
124 } while (length); 225 start_flags |= AT91_TWI_STOP;
226 at91_twi_write(dev, AT91_TWI_CR, start_flags);
227 at91_twi_write(dev, AT91_TWI_IER,
228 AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
229 } else {
230 at91_twi_write_next_byte(dev);
231 at91_twi_write(dev, AT91_TWI_IER,
232 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
233 }
125 234
126 /* Send Stop */ 235 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
127 at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP); 236 dev->adapter.timeout);
237 if (ret == 0) {
238 dev_err(dev->dev, "controller timed out\n");
239 at91_init_twi_bus(dev);
240 return -ETIMEDOUT;
241 }
242 if (dev->transfer_status & AT91_TWI_NACK) {
243 dev_dbg(dev->dev, "received nack\n");
244 return -EREMOTEIO;
245 }
246 if (dev->transfer_status & AT91_TWI_OVRE) {
247 dev_err(dev->dev, "overrun while reading\n");
248 return -EIO;
249 }
250 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
251 dev_err(dev->dev, "underrun while writing\n");
252 return -EIO;
253 }
254 dev_dbg(dev->dev, "transfer complete\n");
128 255
129 return 0; 256 return 0;
130} 257}
131 258
132/* 259static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
133 * Generic i2c master transfer entrypoint.
134 *
135 * Note: We do not use Atmel's feature of storing the "internal device address".
136 * Instead the "internal device address" has to be written using a separate
137 * i2c message.
138 * http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html
139 */
140static int at91_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
141{ 260{
142 int i, ret; 261 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
262 int ret;
263 unsigned int_addr_flag = 0;
264 struct i2c_msg *m_start = msg;
143 265
144 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); 266 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
145 267
146 for (i = 0; i < num; i++) { 268 /*
147 dev_dbg(&adap->dev, " #%d: %sing %d byte%s %s 0x%02x\n", i, 269 * The hardware can handle at most two messages concatenated by a
148 pmsg->flags & I2C_M_RD ? "read" : "writ", 270 * repeated start via it's internal address feature.
149 pmsg->len, pmsg->len > 1 ? "s" : "", 271 */
150 pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr); 272 if (num > 2) {
151 273 dev_err(dev->dev,
152 at91_twi_write(AT91_TWI_MMR, (pmsg->addr << 16) 274 "cannot handle more than two concatenated messages.\n");
153 | ((pmsg->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); 275 return 0;
154 276 } else if (num == 2) {
155 if (pmsg->len && pmsg->buf) { /* sanity check */ 277 int internal_address = 0;
156 if (pmsg->flags & I2C_M_RD) 278 int i;
157 ret = xfer_read(adap, pmsg->buf, pmsg->len); 279
158 else 280 if (msg->flags & I2C_M_RD) {
159 ret = xfer_write(adap, pmsg->buf, pmsg->len); 281 dev_err(dev->dev, "first transfer must be write.\n");
160 282 return -EINVAL;
161 if (ret)
162 return ret;
163
164 /* Wait until transfer is finished */
165 if (!at91_poll_status(AT91_TWI_TXCOMP)) {
166 dev_dbg(&adap->dev, "TXCOMP timeout\n");
167 return -ETIMEDOUT;
168 }
169 } 283 }
170 dev_dbg(&adap->dev, "transfer complete\n"); 284 if (msg->len > 3) {
171 pmsg++; /* next message */ 285 dev_err(dev->dev, "first message size must be <= 3.\n");
286 return -EINVAL;
287 }
288
289 /* 1st msg is put into the internal address, start with 2nd */
290 m_start = &msg[1];
291 for (i = 0; i < msg->len; ++i) {
292 const unsigned addr = msg->buf[msg->len - 1 - i];
293
294 internal_address |= addr << (8 * i);
295 int_addr_flag += AT91_TWI_IADRSZ_1;
296 }
297 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
172 } 298 }
173 return i; 299
300 at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
301 | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
302
303 dev->buf_len = m_start->len;
304 dev->buf = m_start->buf;
305 dev->msg = m_start;
306
307 ret = at91_do_twi_transfer(dev);
308
309 return (ret < 0) ? ret : num;
174} 310}
175 311
176/* 312static u32 at91_twi_func(struct i2c_adapter *adapter)
177 * Return list of supported functionality.
178 */
179static u32 at91_func(struct i2c_adapter *adapter)
180{ 313{
181 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 314 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
315 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
182} 316}
183 317
184static struct i2c_algorithm at91_algorithm = { 318static struct i2c_algorithm at91_twi_algorithm = {
185 .master_xfer = at91_xfer, 319 .master_xfer = at91_twi_xfer,
186 .functionality = at91_func, 320 .functionality = at91_twi_func,
187}; 321};
188 322
189/* 323static struct at91_twi_pdata at91rm9200_config = {
190 * Main initialization routine. 324 .clk_max_div = 5,
191 */ 325 .clk_offset = 3,
192static int __devinit at91_i2c_probe(struct platform_device *pdev) 326 .has_unre_flag = true,
193{ 327};
194 struct i2c_adapter *adapter;
195 struct resource *res;
196 int rc;
197 328
198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 329static struct at91_twi_pdata at91sam9261_config = {
199 if (!res) 330 .clk_max_div = 5,
200 return -ENXIO; 331 .clk_offset = 4,
332 .has_unre_flag = false,
333};
201 334
202 if (!request_mem_region(res->start, resource_size(res), "at91_i2c")) 335static struct at91_twi_pdata at91sam9260_config = {
203 return -EBUSY; 336 .clk_max_div = 7,
337 .clk_offset = 4,
338 .has_unre_flag = false,
339};
340
341static struct at91_twi_pdata at91sam9g20_config = {
342 .clk_max_div = 7,
343 .clk_offset = 4,
344 .has_unre_flag = false,
345};
346
347static struct at91_twi_pdata at91sam9g10_config = {
348 .clk_max_div = 7,
349 .clk_offset = 4,
350 .has_unre_flag = false,
351};
204 352
205 twi_base = ioremap(res->start, resource_size(res)); 353static struct at91_twi_pdata at91sam9x5_config = {
206 if (!twi_base) { 354 .clk_max_div = 7,
207 rc = -ENOMEM; 355 .clk_offset = 4,
208 goto fail0; 356 .has_unre_flag = false,
357};
358
359static const struct platform_device_id at91_twi_devtypes[] = {
360 {
361 .name = "i2c-at91rm9200",
362 .driver_data = (unsigned long) &at91rm9200_config,
363 }, {
364 .name = "i2c-at91sam9261",
365 .driver_data = (unsigned long) &at91sam9261_config,
366 }, {
367 .name = "i2c-at91sam9260",
368 .driver_data = (unsigned long) &at91sam9260_config,
369 }, {
370 .name = "i2c-at91sam9g20",
371 .driver_data = (unsigned long) &at91sam9g20_config,
372 }, {
373 .name = "i2c-at91sam9g10",
374 .driver_data = (unsigned long) &at91sam9g10_config,
375 }, {
376 /* sentinel */
209 } 377 }
378};
210 379
211 twi_clk = clk_get(NULL, "twi_clk"); 380#if defined(CONFIG_OF)
212 if (IS_ERR(twi_clk)) { 381static const struct of_device_id atmel_twi_dt_ids[] = {
213 dev_err(&pdev->dev, "no clock defined\n"); 382 {
214 rc = -ENODEV; 383 .compatible = "atmel,at91sam9260-i2c",
215 goto fail1; 384 .data = &at91sam9260_config,
385 } , {
386 .compatible = "atmel,at91sam9g20-i2c",
387 .data = &at91sam9g20_config,
388 } , {
389 .compatible = "atmel,at91sam9g10-i2c",
390 .data = &at91sam9g10_config,
391 }, {
392 .compatible = "atmel,at91sam9x5-i2c",
393 .data = &at91sam9x5_config,
394 }, {
395 /* sentinel */
216 } 396 }
397};
398MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
399#else
400#define atmel_twi_dt_ids NULL
401#endif
217 402
218 adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL); 403static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
219 if (adapter == NULL) { 404 struct platform_device *pdev)
220 dev_err(&pdev->dev, "can't allocate inteface!\n"); 405{
221 rc = -ENOMEM; 406 if (pdev->dev.of_node) {
222 goto fail2; 407 const struct of_device_id *match;
408 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
409 if (!match)
410 return NULL;
411 return match->data;
223 } 412 }
224 snprintf(adapter->name, sizeof(adapter->name), "AT91"); 413 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
225 adapter->algo = &at91_algorithm; 414}
226 adapter->class = I2C_CLASS_HWMON; 415
227 adapter->dev.parent = &pdev->dev; 416static int __devinit at91_twi_probe(struct platform_device *pdev)
228 /* adapter->id == 0 ... only one TWI controller for now */ 417{
418 struct at91_twi_dev *dev;
419 struct resource *mem;
420 int rc;
421
422 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
423 if (!dev)
424 return -ENOMEM;
425 init_completion(&dev->cmd_complete);
426 dev->dev = &pdev->dev;
427
428 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429 if (!mem)
430 return -ENODEV;
431
432 dev->pdata = at91_twi_get_driver_data(pdev);
433 if (!dev->pdata)
434 return -ENODEV;
229 435
230 platform_set_drvdata(pdev, adapter); 436 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
437 if (!dev->base)
438 return -EBUSY;
231 439
232 clk_enable(twi_clk); /* enable peripheral clock */ 440 dev->irq = platform_get_irq(pdev, 0);
233 at91_twi_hwinit(); /* initialize TWI controller */ 441 if (dev->irq < 0)
442 return dev->irq;
234 443
235 rc = i2c_add_numbered_adapter(adapter); 444 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
445 dev_name(dev->dev), dev);
236 if (rc) { 446 if (rc) {
237 dev_err(&pdev->dev, "Adapter %s registration failed\n", 447 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
238 adapter->name); 448 return rc;
239 goto fail3;
240 } 449 }
241 450
242 dev_info(&pdev->dev, "AT91 i2c bus driver.\n"); 451 platform_set_drvdata(pdev, dev);
243 return 0;
244 452
245fail3: 453 dev->clk = devm_clk_get(dev->dev, NULL);
246 platform_set_drvdata(pdev, NULL); 454 if (IS_ERR(dev->clk)) {
247 kfree(adapter); 455 dev_err(dev->dev, "no clock defined\n");
248 clk_disable(twi_clk); 456 return -ENODEV;
249fail2: 457 }
250 clk_put(twi_clk); 458 clk_prepare_enable(dev->clk);
251fail1: 459
252 iounmap(twi_base); 460 at91_calc_twi_clock(dev, TWI_CLK_HZ);
253fail0: 461 at91_init_twi_bus(dev);
254 release_mem_region(res->start, resource_size(res)); 462
463 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
464 i2c_set_adapdata(&dev->adapter, dev);
465 dev->adapter.owner = THIS_MODULE;
466 dev->adapter.class = I2C_CLASS_HWMON;
467 dev->adapter.algo = &at91_twi_algorithm;
468 dev->adapter.dev.parent = dev->dev;
469 dev->adapter.nr = pdev->id;
470 dev->adapter.timeout = AT91_I2C_TIMEOUT;
471 dev->adapter.dev.of_node = pdev->dev.of_node;
472
473 rc = i2c_add_numbered_adapter(&dev->adapter);
474 if (rc) {
475 dev_err(dev->dev, "Adapter %s registration failed\n",
476 dev->adapter.name);
477 clk_disable_unprepare(dev->clk);
478 return rc;
479 }
255 480
256 return rc; 481 of_i2c_register_devices(&dev->adapter);
482
483 dev_info(dev->dev, "AT91 i2c bus driver.\n");
484 return 0;
257} 485}
258 486
259static int __devexit at91_i2c_remove(struct platform_device *pdev) 487static int __devexit at91_twi_remove(struct platform_device *pdev)
260{ 488{
261 struct i2c_adapter *adapter = platform_get_drvdata(pdev); 489 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
262 struct resource *res;
263 int rc; 490 int rc;
264 491
265 rc = i2c_del_adapter(adapter); 492 rc = i2c_del_adapter(&dev->adapter);
266 platform_set_drvdata(pdev, NULL); 493 clk_disable_unprepare(dev->clk);
267
268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 iounmap(twi_base);
270 release_mem_region(res->start, resource_size(res));
271
272 clk_disable(twi_clk); /* disable peripheral clock */
273 clk_put(twi_clk);
274 494
275 return rc; 495 return rc;
276} 496}
277 497
278#ifdef CONFIG_PM 498#ifdef CONFIG_PM
279 499
280/* NOTE: could save a few mA by keeping clock off outside of at91_xfer... */ 500static int at91_twi_runtime_suspend(struct device *dev)
281
282static int at91_i2c_suspend(struct device *dev)
283{ 501{
284 clk_disable(twi_clk); 502 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
503
504 clk_disable(twi_dev->clk);
505
285 return 0; 506 return 0;
286} 507}
287 508
288static int at91_i2c_resume(struct device *dev) 509static int at91_twi_runtime_resume(struct device *dev)
289{ 510{
290 return clk_enable(twi_clk); 511 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
512
513 return clk_enable(twi_dev->clk);
291} 514}
292 515
293static SIMPLE_DEV_PM_OPS(at91_i2c_pm, at91_i2c_suspend, at91_i2c_resume); 516static const struct dev_pm_ops at91_twi_pm = {
294#define AT91_I2C_PM (&at91_i2c_pm) 517 .runtime_suspend = at91_twi_runtime_suspend,
518 .runtime_resume = at91_twi_runtime_resume,
519};
295 520
521#define at91_twi_pm_ops (&at91_twi_pm)
296#else 522#else
297#define AT91_I2C_PM NULL 523#define at91_twi_pm_ops NULL
298#endif 524#endif
299 525
300static struct platform_driver at91_i2c_driver = { 526static struct platform_driver at91_twi_driver = {
301 .probe = at91_i2c_probe, 527 .probe = at91_twi_probe,
302 .remove = __devexit_p(at91_i2c_remove), 528 .remove = __devexit_p(at91_twi_remove),
529 .id_table = at91_twi_devtypes,
303 .driver = { 530 .driver = {
304 .name = "at91_i2c", 531 .name = "at91_i2c",
305 .owner = THIS_MODULE, 532 .owner = THIS_MODULE,
306 .pm = AT91_I2C_PM, 533 .of_match_table = atmel_twi_dt_ids,
534 .pm = at91_twi_pm_ops,
307 }, 535 },
308}; 536};
309 537
310module_platform_driver(at91_i2c_driver); 538static int __init at91_twi_init(void)
539{
540 return platform_driver_register(&at91_twi_driver);
541}
542
543static void __exit at91_twi_exit(void)
544{
545 platform_driver_unregister(&at91_twi_driver);
546}
547
548subsys_initcall(at91_twi_init);
549module_exit(at91_twi_exit);
311 550
312MODULE_AUTHOR("Rick Bronson"); 551MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
313MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); 552MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
314MODULE_LICENSE("GPL"); 553MODULE_LICENSE("GPL");
315MODULE_ALIAS("platform:at91_i2c"); 554MODULE_ALIAS("platform:at91_i2c");
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 79a2542d8c41..6a0a55319449 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -38,6 +38,8 @@
38#include <linux/slab.h> 38#include <linux/slab.h>
39#include <linux/cpufreq.h> 39#include <linux/cpufreq.h>
40#include <linux/gpio.h> 40#include <linux/gpio.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
41 43
42#include <mach/hardware.h> 44#include <mach/hardware.h>
43#include <linux/platform_data/i2c-davinci.h> 45#include <linux/platform_data/i2c-davinci.h>
@@ -114,6 +116,7 @@ struct davinci_i2c_dev {
114 struct completion xfr_complete; 116 struct completion xfr_complete;
115 struct notifier_block freq_transition; 117 struct notifier_block freq_transition;
116#endif 118#endif
119 struct davinci_i2c_platform_data *pdata;
117}; 120};
118 121
119/* default platform data to use if not supplied in the platform_device */ 122/* default platform data to use if not supplied in the platform_device */
@@ -155,7 +158,7 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin)
155static void i2c_recover_bus(struct davinci_i2c_dev *dev) 158static void i2c_recover_bus(struct davinci_i2c_dev *dev)
156{ 159{
157 u32 flag = 0; 160 u32 flag = 0;
158 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 161 struct davinci_i2c_platform_data *pdata = dev->pdata;
159 162
160 dev_err(dev->dev, "initiating i2c bus recovery\n"); 163 dev_err(dev->dev, "initiating i2c bus recovery\n");
161 /* Send NACK to the slave */ 164 /* Send NACK to the slave */
@@ -163,8 +166,7 @@ static void i2c_recover_bus(struct davinci_i2c_dev *dev)
163 flag |= DAVINCI_I2C_MDR_NACK; 166 flag |= DAVINCI_I2C_MDR_NACK;
164 /* write the data into mode register */ 167 /* write the data into mode register */
165 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 168 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
166 if (pdata) 169 generic_i2c_clock_pulse(pdata->scl_pin);
167 generic_i2c_clock_pulse(pdata->scl_pin);
168 /* Send STOP */ 170 /* Send STOP */
169 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 171 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
170 flag |= DAVINCI_I2C_MDR_STP; 172 flag |= DAVINCI_I2C_MDR_STP;
@@ -187,7 +189,7 @@ static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
187 189
188static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 190static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
189{ 191{
190 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 192 struct davinci_i2c_platform_data *pdata = dev->pdata;
191 u16 psc; 193 u16 psc;
192 u32 clk; 194 u32 clk;
193 u32 d; 195 u32 d;
@@ -235,10 +237,7 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
235 */ 237 */
236static int i2c_davinci_init(struct davinci_i2c_dev *dev) 238static int i2c_davinci_init(struct davinci_i2c_dev *dev)
237{ 239{
238 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 240 struct davinci_i2c_platform_data *pdata = dev->pdata;
239
240 if (!pdata)
241 pdata = &davinci_i2c_platform_data_default;
242 241
243 /* put I2C into reset */ 242 /* put I2C into reset */
244 davinci_i2c_reset_ctrl(dev, 0); 243 davinci_i2c_reset_ctrl(dev, 0);
@@ -260,6 +259,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev)
260 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 259 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
261 pdata->bus_freq, pdata->bus_delay); 260 pdata->bus_freq, pdata->bus_delay);
262 261
262
263 /* Take the I2C module out of reset: */ 263 /* Take the I2C module out of reset: */
264 davinci_i2c_reset_ctrl(dev, 1); 264 davinci_i2c_reset_ctrl(dev, 1);
265 265
@@ -308,13 +308,11 @@ static int
308i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 308i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
309{ 309{
310 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 310 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
311 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 311 struct davinci_i2c_platform_data *pdata = dev->pdata;
312 u32 flag; 312 u32 flag;
313 u16 w; 313 u16 w;
314 int r; 314 int r;
315 315
316 if (!pdata)
317 pdata = &davinci_i2c_platform_data_default;
318 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 316 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
319 if (pdata->bus_delay) 317 if (pdata->bus_delay)
320 udelay(pdata->bus_delay); 318 udelay(pdata->bus_delay);
@@ -635,6 +633,12 @@ static struct i2c_algorithm i2c_davinci_algo = {
635 .functionality = i2c_davinci_func, 633 .functionality = i2c_davinci_func,
636}; 634};
637 635
636static const struct of_device_id davinci_i2c_of_match[] = {
637 {.compatible = "ti,davinci-i2c", },
638 {},
639};
640MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
641
638static int davinci_i2c_probe(struct platform_device *pdev) 642static int davinci_i2c_probe(struct platform_device *pdev)
639{ 643{
640 struct davinci_i2c_dev *dev; 644 struct davinci_i2c_dev *dev;
@@ -674,14 +678,33 @@ static int davinci_i2c_probe(struct platform_device *pdev)
674#endif 678#endif
675 dev->dev = get_device(&pdev->dev); 679 dev->dev = get_device(&pdev->dev);
676 dev->irq = irq->start; 680 dev->irq = irq->start;
681 dev->pdata = dev->dev->platform_data;
677 platform_set_drvdata(pdev, dev); 682 platform_set_drvdata(pdev, dev);
678 683
684 if (!dev->pdata && pdev->dev.of_node) {
685 u32 prop;
686
687 dev->pdata = devm_kzalloc(&pdev->dev,
688 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
689 if (!dev->pdata) {
690 r = -ENOMEM;
691 goto err_free_mem;
692 }
693 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
694 sizeof(struct davinci_i2c_platform_data));
695 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
696 &prop))
697 dev->pdata->bus_freq = prop / 1000;
698 } else if (!dev->pdata) {
699 dev->pdata = &davinci_i2c_platform_data_default;
700 }
701
679 dev->clk = clk_get(&pdev->dev, NULL); 702 dev->clk = clk_get(&pdev->dev, NULL);
680 if (IS_ERR(dev->clk)) { 703 if (IS_ERR(dev->clk)) {
681 r = -ENODEV; 704 r = -ENODEV;
682 goto err_free_mem; 705 goto err_free_mem;
683 } 706 }
684 clk_enable(dev->clk); 707 clk_prepare_enable(dev->clk);
685 708
686 dev->base = ioremap(mem->start, resource_size(mem)); 709 dev->base = ioremap(mem->start, resource_size(mem));
687 if (!dev->base) { 710 if (!dev->base) {
@@ -711,6 +734,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
711 adap->algo = &i2c_davinci_algo; 734 adap->algo = &i2c_davinci_algo;
712 adap->dev.parent = &pdev->dev; 735 adap->dev.parent = &pdev->dev;
713 adap->timeout = DAVINCI_I2C_TIMEOUT; 736 adap->timeout = DAVINCI_I2C_TIMEOUT;
737 adap->dev.of_node = pdev->dev.of_node;
714 738
715 adap->nr = pdev->id; 739 adap->nr = pdev->id;
716 r = i2c_add_numbered_adapter(adap); 740 r = i2c_add_numbered_adapter(adap);
@@ -718,6 +742,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
718 dev_err(&pdev->dev, "failure adding adapter\n"); 742 dev_err(&pdev->dev, "failure adding adapter\n");
719 goto err_free_irq; 743 goto err_free_irq;
720 } 744 }
745 of_i2c_register_devices(adap);
721 746
722 return 0; 747 return 0;
723 748
@@ -726,7 +751,7 @@ err_free_irq:
726err_unuse_clocks: 751err_unuse_clocks:
727 iounmap(dev->base); 752 iounmap(dev->base);
728err_mem_ioremap: 753err_mem_ioremap:
729 clk_disable(dev->clk); 754 clk_disable_unprepare(dev->clk);
730 clk_put(dev->clk); 755 clk_put(dev->clk);
731 dev->clk = NULL; 756 dev->clk = NULL;
732err_free_mem: 757err_free_mem:
@@ -750,7 +775,7 @@ static int davinci_i2c_remove(struct platform_device *pdev)
750 i2c_del_adapter(&dev->adapter); 775 i2c_del_adapter(&dev->adapter);
751 put_device(&pdev->dev); 776 put_device(&pdev->dev);
752 777
753 clk_disable(dev->clk); 778 clk_disable_unprepare(dev->clk);
754 clk_put(dev->clk); 779 clk_put(dev->clk);
755 dev->clk = NULL; 780 dev->clk = NULL;
756 781
@@ -772,7 +797,7 @@ static int davinci_i2c_suspend(struct device *dev)
772 797
773 /* put I2C into reset */ 798 /* put I2C into reset */
774 davinci_i2c_reset_ctrl(i2c_dev, 0); 799 davinci_i2c_reset_ctrl(i2c_dev, 0);
775 clk_disable(i2c_dev->clk); 800 clk_disable_unprepare(i2c_dev->clk);
776 801
777 return 0; 802 return 0;
778} 803}
@@ -782,7 +807,7 @@ static int davinci_i2c_resume(struct device *dev)
782 struct platform_device *pdev = to_platform_device(dev); 807 struct platform_device *pdev = to_platform_device(dev);
783 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 808 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
784 809
785 clk_enable(i2c_dev->clk); 810 clk_prepare_enable(i2c_dev->clk);
786 /* take I2C out of reset */ 811 /* take I2C out of reset */
787 davinci_i2c_reset_ctrl(i2c_dev, 1); 812 davinci_i2c_reset_ctrl(i2c_dev, 1);
788 813
@@ -809,6 +834,7 @@ static struct platform_driver davinci_i2c_driver = {
809 .name = "i2c_davinci", 834 .name = "i2c_davinci",
810 .owner = THIS_MODULE, 835 .owner = THIS_MODULE,
811 .pm = davinci_i2c_pm_ops, 836 .pm = davinci_i2c_pm_ops,
837 .of_match_table = of_match_ptr(davinci_i2c_of_match),
812 }, 838 },
813}; 839};
814 840
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index b7907ba7448a..2ef162d148cb 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -272,9 +272,9 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
272 272
273 /* dev_dbg() can't be used, because adapter is not yet registered */ 273 /* dev_dbg() can't be used, because adapter is not yet registered */
274#ifdef CONFIG_I2C_DEBUG_BUS 274#ifdef CONFIG_I2C_DEBUG_BUS
275 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n", 275 dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
276 __func__, i2c_clk_rate, div); 276 __func__, i2c_clk_rate, div);
277 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n", 277 dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
278 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]); 278 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
279#endif 279#endif
280} 280}
@@ -564,7 +564,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
564 resource_size(res), res->start); 564 resource_size(res), res->start);
565 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 565 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
566 i2c_imx->adapter.name); 566 i2c_imx->adapter.name);
567 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 567 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
568 568
569 return 0; /* Return OK */ 569 return 0; /* Return OK */
570} 570}
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 57f7703ce2e8..ca86430cb4a2 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -576,7 +576,23 @@ static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
576 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 576 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
577 } 577 }
578 } 578 }
579 mpc_i2c_stop(i2c); 579 mpc_i2c_stop(i2c); /* Initiate STOP */
580 orig_jiffies = jiffies;
581 /* Wait until STOP is seen, allow up to 1 s */
582 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
583 if (time_after(jiffies, orig_jiffies + HZ)) {
584 u8 status = readb(i2c->base + MPC_I2C_SR);
585
586 dev_dbg(i2c->dev, "timeout\n");
587 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
588 writeb(status & ~CSR_MAL,
589 i2c->base + MPC_I2C_SR);
590 mpc_i2c_fixup(i2c);
591 }
592 return -EIO;
593 }
594 cond_resched();
595 }
580 return (ret < 0) ? ret : num; 596 return (ret < 0) ? ret : num;
581} 597}
582 598
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 51f05b8520ed..1f58197062cf 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -7,8 +7,6 @@
7 * 7 *
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 * 9 *
10 * TODO: add dma-support if platform-support for it is available
11 *
12 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or 12 * the Free Software Foundation; either version 2 of the License, or
@@ -31,9 +29,16 @@
31#include <linux/of.h> 29#include <linux/of.h>
32#include <linux/of_device.h> 30#include <linux/of_device.h>
33#include <linux/of_i2c.h> 31#include <linux/of_i2c.h>
32#include <linux/dma-mapping.h>
33#include <linux/dmaengine.h>
34#include <linux/fsl/mxs-dma.h>
34 35
35#define DRIVER_NAME "mxs-i2c" 36#define DRIVER_NAME "mxs-i2c"
36 37
38static bool use_pioqueue;
39module_param(use_pioqueue, bool, 0);
40MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA");
41
37#define MXS_I2C_CTRL0 (0x00) 42#define MXS_I2C_CTRL0 (0x00)
38#define MXS_I2C_CTRL0_SET (0x04) 43#define MXS_I2C_CTRL0_SET (0x04)
39 44
@@ -146,6 +151,16 @@ struct mxs_i2c_dev {
146 u32 cmd_err; 151 u32 cmd_err;
147 struct i2c_adapter adapter; 152 struct i2c_adapter adapter;
148 const struct mxs_i2c_speed_config *speed; 153 const struct mxs_i2c_speed_config *speed;
154
155 /* DMA support components */
156 bool dma_mode;
157 int dma_channel;
158 struct dma_chan *dmach;
159 struct mxs_dma_data dma_data;
160 uint32_t pio_data[2];
161 uint32_t addr_data;
162 struct scatterlist sg_io[2];
163 bool dma_read;
149}; 164};
150 165
151static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) 166static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
@@ -157,7 +172,11 @@ static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
157 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); 172 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
158 173
159 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 174 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
160 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 175 if (i2c->dma_mode)
176 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
177 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
178 else
179 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
161 i2c->regs + MXS_I2C_QUEUECTRL_SET); 180 i2c->regs + MXS_I2C_QUEUECTRL_SET);
162} 181}
163 182
@@ -248,6 +267,150 @@ static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
248 return 0; 267 return 0;
249} 268}
250 269
270static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
271{
272 if (i2c->dma_read) {
273 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
274 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
275 } else {
276 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
277 }
278}
279
280static void mxs_i2c_dma_irq_callback(void *param)
281{
282 struct mxs_i2c_dev *i2c = param;
283
284 complete(&i2c->cmd_complete);
285 mxs_i2c_dma_finish(i2c);
286}
287
288static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
289 struct i2c_msg *msg, uint32_t flags)
290{
291 struct dma_async_tx_descriptor *desc;
292 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
293
294 if (msg->flags & I2C_M_RD) {
295 i2c->dma_read = 1;
296 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
297
298 /*
299 * SELECT command.
300 */
301
302 /* Queue the PIO register write transfer. */
303 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
304 desc = dmaengine_prep_slave_sg(i2c->dmach,
305 (struct scatterlist *)&i2c->pio_data[0],
306 1, DMA_TRANS_NONE, 0);
307 if (!desc) {
308 dev_err(i2c->dev,
309 "Failed to get PIO reg. write descriptor.\n");
310 goto select_init_pio_fail;
311 }
312
313 /* Queue the DMA data transfer. */
314 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
315 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
316 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
317 DMA_MEM_TO_DEV,
318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
319 if (!desc) {
320 dev_err(i2c->dev,
321 "Failed to get DMA data write descriptor.\n");
322 goto select_init_dma_fail;
323 }
324
325 /*
326 * READ command.
327 */
328
329 /* Queue the PIO register write transfer. */
330 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
331 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
332 desc = dmaengine_prep_slave_sg(i2c->dmach,
333 (struct scatterlist *)&i2c->pio_data[1],
334 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
335 if (!desc) {
336 dev_err(i2c->dev,
337 "Failed to get PIO reg. write descriptor.\n");
338 goto select_init_dma_fail;
339 }
340
341 /* Queue the DMA data transfer. */
342 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
343 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
344 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
345 DMA_DEV_TO_MEM,
346 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
347 if (!desc) {
348 dev_err(i2c->dev,
349 "Failed to get DMA data write descriptor.\n");
350 goto read_init_dma_fail;
351 }
352 } else {
353 i2c->dma_read = 0;
354 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
355
356 /*
357 * WRITE command.
358 */
359
360 /* Queue the PIO register write transfer. */
361 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
362 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
363 desc = dmaengine_prep_slave_sg(i2c->dmach,
364 (struct scatterlist *)&i2c->pio_data[0],
365 1, DMA_TRANS_NONE, 0);
366 if (!desc) {
367 dev_err(i2c->dev,
368 "Failed to get PIO reg. write descriptor.\n");
369 goto write_init_pio_fail;
370 }
371
372 /* Queue the DMA data transfer. */
373 sg_init_table(i2c->sg_io, 2);
374 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
375 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
376 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
377 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
378 DMA_MEM_TO_DEV,
379 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
380 if (!desc) {
381 dev_err(i2c->dev,
382 "Failed to get DMA data write descriptor.\n");
383 goto write_init_dma_fail;
384 }
385 }
386
387 /*
388 * The last descriptor must have this callback,
389 * to finish the DMA transaction.
390 */
391 desc->callback = mxs_i2c_dma_irq_callback;
392 desc->callback_param = i2c;
393
394 /* Start the transfer. */
395 dmaengine_submit(desc);
396 dma_async_issue_pending(i2c->dmach);
397 return 0;
398
399/* Read failpath. */
400read_init_dma_fail:
401 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
402select_init_dma_fail:
403 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
404select_init_pio_fail:
405 return -EINVAL;
406
407/* Write failpath. */
408write_init_dma_fail:
409 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
410write_init_pio_fail:
411 return -EINVAL;
412}
413
251/* 414/*
252 * Low level master read/write transaction. 415 * Low level master read/write transaction.
253 */ 416 */
@@ -258,6 +421,8 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
258 int ret; 421 int ret;
259 int flags; 422 int flags;
260 423
424 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
425
261 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 426 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
262 msg->addr, msg->len, msg->flags, stop); 427 msg->addr, msg->len, msg->flags, stop);
263 428
@@ -267,23 +432,29 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
267 init_completion(&i2c->cmd_complete); 432 init_completion(&i2c->cmd_complete);
268 i2c->cmd_err = 0; 433 i2c->cmd_err = 0;
269 434
270 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; 435 if (i2c->dma_mode) {
271 436 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
272 if (msg->flags & I2C_M_RD) 437 if (ret)
273 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags); 438 return ret;
274 else 439 } else {
275 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len, 440 if (msg->flags & I2C_M_RD) {
276 flags); 441 mxs_i2c_pioq_setup_read(i2c, msg->addr,
442 msg->len, flags);
443 } else {
444 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf,
445 msg->len, flags);
446 }
277 447
278 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, 448 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
279 i2c->regs + MXS_I2C_QUEUECTRL_SET); 449 i2c->regs + MXS_I2C_QUEUECTRL_SET);
450 }
280 451
281 ret = wait_for_completion_timeout(&i2c->cmd_complete, 452 ret = wait_for_completion_timeout(&i2c->cmd_complete,
282 msecs_to_jiffies(1000)); 453 msecs_to_jiffies(1000));
283 if (ret == 0) 454 if (ret == 0)
284 goto timeout; 455 goto timeout;
285 456
286 if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) { 457 if (!i2c->dma_mode && !i2c->cmd_err && (msg->flags & I2C_M_RD)) {
287 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len); 458 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
288 if (ret) 459 if (ret)
289 goto timeout; 460 goto timeout;
@@ -301,6 +472,8 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
301 472
302timeout: 473timeout:
303 dev_dbg(i2c->dev, "Timeout!\n"); 474 dev_dbg(i2c->dev, "Timeout!\n");
475 if (i2c->dma_mode)
476 mxs_i2c_dma_finish(i2c);
304 mxs_i2c_reset(i2c); 477 mxs_i2c_reset(i2c);
305 return -ETIMEDOUT; 478 return -ETIMEDOUT;
306} 479}
@@ -342,11 +515,13 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
342 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ 515 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
343 i2c->cmd_err = -EIO; 516 i2c->cmd_err = -EIO;
344 517
345 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & 518 if (!i2c->dma_mode) {
346 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; 519 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
520 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
347 521
348 if (is_last_cmd || i2c->cmd_err) 522 if (is_last_cmd || i2c->cmd_err)
349 complete(&i2c->cmd_complete); 523 complete(&i2c->cmd_complete);
524 }
350 525
351 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); 526 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
352 527
@@ -358,6 +533,21 @@ static const struct i2c_algorithm mxs_i2c_algo = {
358 .functionality = mxs_i2c_func, 533 .functionality = mxs_i2c_func,
359}; 534};
360 535
536static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
537{
538 struct mxs_i2c_dev *i2c = param;
539
540 if (!mxs_dma_is_apbx(chan))
541 return false;
542
543 if (chan->chan_id != i2c->dma_channel)
544 return false;
545
546 chan->private = &i2c->dma_data;
547
548 return true;
549}
550
361static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) 551static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
362{ 552{
363 uint32_t speed; 553 uint32_t speed;
@@ -365,6 +555,26 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
365 struct device_node *node = dev->of_node; 555 struct device_node *node = dev->of_node;
366 int ret; 556 int ret;
367 557
558 /*
559 * The MXS I2C DMA mode is prefered and enabled by default.
560 * The PIO mode is still supported, but should be used only
561 * for debuging purposes etc.
562 */
563 i2c->dma_mode = !use_pioqueue;
564 if (!i2c->dma_mode)
565 dev_info(dev, "Using PIOQUEUE mode for I2C transfers!\n");
566
567 /*
568 * TODO: This is a temporary solution and should be changed
569 * to use generic DMA binding later when the helpers get in.
570 */
571 ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
572 &i2c->dma_channel);
573 if (ret) {
574 dev_warn(dev, "Failed to get DMA channel, using PIOQUEUE!\n");
575 i2c->dma_mode = 0;
576 }
577
368 ret = of_property_read_u32(node, "clock-frequency", &speed); 578 ret = of_property_read_u32(node, "clock-frequency", &speed);
369 if (ret) 579 if (ret)
370 dev_warn(dev, "No I2C speed selected, using 100kHz\n"); 580 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
@@ -384,7 +594,8 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
384 struct pinctrl *pinctrl; 594 struct pinctrl *pinctrl;
385 struct resource *res; 595 struct resource *res;
386 resource_size_t res_size; 596 resource_size_t res_size;
387 int err, irq; 597 int err, irq, dmairq;
598 dma_cap_mask_t mask;
388 599
389 pinctrl = devm_pinctrl_get_select_default(dev); 600 pinctrl = devm_pinctrl_get_select_default(dev);
390 if (IS_ERR(pinctrl)) 601 if (IS_ERR(pinctrl))
@@ -395,7 +606,10 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
395 return -ENOMEM; 606 return -ENOMEM;
396 607
397 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
398 if (!res) 609 irq = platform_get_irq(pdev, 0);
610 dmairq = platform_get_irq(pdev, 1);
611
612 if (!res || irq < 0 || dmairq < 0)
399 return -ENOENT; 613 return -ENOENT;
400 614
401 res_size = resource_size(res); 615 res_size = resource_size(res);
@@ -406,10 +620,6 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
406 if (!i2c->regs) 620 if (!i2c->regs)
407 return -EBUSY; 621 return -EBUSY;
408 622
409 irq = platform_get_irq(pdev, 0);
410 if (irq < 0)
411 return irq;
412
413 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); 623 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
414 if (err) 624 if (err)
415 return err; 625 return err;
@@ -423,6 +633,18 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
423 return err; 633 return err;
424 } 634 }
425 635
636 /* Setup the DMA */
637 if (i2c->dma_mode) {
638 dma_cap_zero(mask);
639 dma_cap_set(DMA_SLAVE, mask);
640 i2c->dma_data.chan_irq = dmairq;
641 i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
642 if (!i2c->dmach) {
643 dev_err(dev, "Failed to request dma\n");
644 return -ENODEV;
645 }
646 }
647
426 platform_set_drvdata(pdev, i2c); 648 platform_set_drvdata(pdev, i2c);
427 649
428 /* Do reset to enforce correct startup after pinmuxing */ 650 /* Do reset to enforce correct startup after pinmuxing */
@@ -458,6 +680,9 @@ static int __devexit mxs_i2c_remove(struct platform_device *pdev)
458 if (ret) 680 if (ret)
459 return -EBUSY; 681 return -EBUSY;
460 682
683 if (i2c->dmach)
684 dma_release_channel(i2c->dmach);
685
461 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); 686 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
462 687
463 platform_set_drvdata(pdev, NULL); 688 platform_set_drvdata(pdev, NULL);
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 61b00edacb08..698d7acb0f08 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -22,9 +22,10 @@
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/regulator/consumer.h>
26#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
27#include <linux/platform_data/i2c-nomadik.h> 26#include <linux/platform_data/i2c-nomadik.h>
27#include <linux/of.h>
28#include <linux/of_i2c.h>
28 29
29#define DRIVER_NAME "nmk-i2c" 30#define DRIVER_NAME "nmk-i2c"
30 31
@@ -146,7 +147,6 @@ struct i2c_nmk_client {
146 * @stop: stop condition. 147 * @stop: stop condition.
147 * @xfer_complete: acknowledge completion for a I2C message. 148 * @xfer_complete: acknowledge completion for a I2C message.
148 * @result: controller propogated result. 149 * @result: controller propogated result.
149 * @regulator: pointer to i2c regulator.
150 * @busy: Busy doing transfer. 150 * @busy: Busy doing transfer.
151 */ 151 */
152struct nmk_i2c_dev { 152struct nmk_i2c_dev {
@@ -160,7 +160,6 @@ struct nmk_i2c_dev {
160 int stop; 160 int stop;
161 struct completion xfer_complete; 161 struct completion xfer_complete;
162 int result; 162 int result;
163 struct regulator *regulator;
164 bool busy; 163 bool busy;
165}; 164};
166 165
@@ -643,8 +642,6 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
643 642
644 dev->busy = true; 643 dev->busy = true;
645 644
646 if (dev->regulator)
647 regulator_enable(dev->regulator);
648 pm_runtime_get_sync(&dev->adev->dev); 645 pm_runtime_get_sync(&dev->adev->dev);
649 646
650 clk_enable(dev->clk); 647 clk_enable(dev->clk);
@@ -676,8 +673,6 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
676out: 673out:
677 clk_disable(dev->clk); 674 clk_disable(dev->clk);
678 pm_runtime_put_sync(&dev->adev->dev); 675 pm_runtime_put_sync(&dev->adev->dev);
679 if (dev->regulator)
680 regulator_disable(dev->regulator);
681 676
682 dev->busy = false; 677 dev->busy = false;
683 678
@@ -920,18 +915,42 @@ static struct nmk_i2c_controller u8500_i2c = {
920 .sm = I2C_FREQ_MODE_FAST, 915 .sm = I2C_FREQ_MODE_FAST,
921}; 916};
922 917
918static void nmk_i2c_of_probe(struct device_node *np,
919 struct nmk_i2c_controller *pdata)
920{
921 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
922
923 /* This driver only supports 'standard' and 'fast' modes of operation. */
924 if (pdata->clk_freq <= 100000)
925 pdata->sm = I2C_FREQ_MODE_STANDARD;
926 else
927 pdata->sm = I2C_FREQ_MODE_FAST;
928}
929
923static atomic_t adapter_id = ATOMIC_INIT(0); 930static atomic_t adapter_id = ATOMIC_INIT(0);
924 931
925static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 932static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
926{ 933{
927 int ret = 0; 934 int ret = 0;
928 struct nmk_i2c_controller *pdata = adev->dev.platform_data; 935 struct nmk_i2c_controller *pdata = adev->dev.platform_data;
936 struct device_node *np = adev->dev.of_node;
929 struct nmk_i2c_dev *dev; 937 struct nmk_i2c_dev *dev;
930 struct i2c_adapter *adap; 938 struct i2c_adapter *adap;
931 939
932 if (!pdata) 940 if (!pdata) {
933 /* No i2c configuration found, using the default. */ 941 if (np) {
934 pdata = &u8500_i2c; 942 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
943 if (!pdata) {
944 ret = -ENOMEM;
945 goto err_no_mem;
946 }
947 /* Provide the default configuration as a base. */
948 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller));
949 nmk_i2c_of_probe(np, pdata);
950 } else
951 /* No i2c configuration found, using the default. */
952 pdata = &u8500_i2c;
953 }
935 954
936 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 955 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
937 if (!dev) { 956 if (!dev) {
@@ -957,12 +976,6 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
957 goto err_irq; 976 goto err_irq;
958 } 977 }
959 978
960 dev->regulator = regulator_get(&adev->dev, "v-i2c");
961 if (IS_ERR(dev->regulator)) {
962 dev_warn(&adev->dev, "could not get i2c regulator\n");
963 dev->regulator = NULL;
964 }
965
966 pm_suspend_ignore_children(&adev->dev, true); 979 pm_suspend_ignore_children(&adev->dev, true);
967 980
968 dev->clk = clk_get(&adev->dev, NULL); 981 dev->clk = clk_get(&adev->dev, NULL);
@@ -973,6 +986,7 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
973 } 986 }
974 987
975 adap = &dev->adap; 988 adap = &dev->adap;
989 adap->dev.of_node = np;
976 adap->dev.parent = &adev->dev; 990 adap->dev.parent = &adev->dev;
977 adap->owner = THIS_MODULE; 991 adap->owner = THIS_MODULE;
978 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 992 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
@@ -1002,6 +1016,8 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1002 goto err_add_adap; 1016 goto err_add_adap;
1003 } 1017 }
1004 1018
1019 of_i2c_register_devices(adap);
1020
1005 pm_runtime_put(&adev->dev); 1021 pm_runtime_put(&adev->dev);
1006 1022
1007 return 0; 1023 return 0;
@@ -1009,8 +1025,6 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1009 err_add_adap: 1025 err_add_adap:
1010 clk_put(dev->clk); 1026 clk_put(dev->clk);
1011 err_no_clk: 1027 err_no_clk:
1012 if (dev->regulator)
1013 regulator_put(dev->regulator);
1014 free_irq(dev->irq, dev); 1028 free_irq(dev->irq, dev);
1015 err_irq: 1029 err_irq:
1016 iounmap(dev->virtbase); 1030 iounmap(dev->virtbase);
@@ -1038,8 +1052,6 @@ static int nmk_i2c_remove(struct amba_device *adev)
1038 if (res) 1052 if (res)
1039 release_mem_region(res->start, resource_size(res)); 1053 release_mem_region(res->start, resource_size(res));
1040 clk_put(dev->clk); 1054 clk_put(dev->clk);
1041 if (dev->regulator)
1042 regulator_put(dev->regulator);
1043 pm_runtime_disable(&adev->dev); 1055 pm_runtime_disable(&adev->dev);
1044 amba_set_drvdata(adev, NULL); 1056 amba_set_drvdata(adev, NULL);
1045 kfree(dev); 1057 kfree(dev);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index a0e49f6aaf96..db31eaed6ea5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,6 +43,7 @@
43#include <linux/slab.h> 43#include <linux/slab.h>
44#include <linux/i2c-omap.h> 44#include <linux/i2c-omap.h>
45#include <linux/pm_runtime.h> 45#include <linux/pm_runtime.h>
46#include <linux/pm_qos.h>
46 47
47/* I2C controller revisions */ 48/* I2C controller revisions */
48#define OMAP_I2C_OMAP1_REV_2 0x20 49#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -55,6 +56,9 @@
55/* timeout waiting for the controller to respond */ 56/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 57#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57 58
59/* timeout for pm runtime autosuspend */
60#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
61
58/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 62/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
59enum { 63enum {
60 OMAP_I2C_REV_REG = 0, 64 OMAP_I2C_REV_REG = 0,
@@ -176,15 +180,15 @@ enum {
176#define I2C_OMAP_ERRATA_I462 (1 << 1) 180#define I2C_OMAP_ERRATA_I462 (1 << 1)
177 181
178struct omap_i2c_dev { 182struct omap_i2c_dev {
183 spinlock_t lock; /* IRQ synchronization */
179 struct device *dev; 184 struct device *dev;
180 void __iomem *base; /* virtual */ 185 void __iomem *base; /* virtual */
181 int irq; 186 int irq;
182 int reg_shift; /* bit shift for I2C register addresses */ 187 int reg_shift; /* bit shift for I2C register addresses */
183 struct completion cmd_complete; 188 struct completion cmd_complete;
184 struct resource *ioarea; 189 struct resource *ioarea;
185 u32 latency; /* maximum mpu wkup latency */ 190 u32 latency; /* maximum MPU wkup latency */
186 void (*set_mpu_wkup_lat)(struct device *dev, 191 struct pm_qos_request pm_qos_request;
187 long latency);
188 u32 speed; /* Speed of bus in kHz */ 192 u32 speed; /* Speed of bus in kHz */
189 u32 dtrev; /* extra revision from DT */ 193 u32 dtrev; /* extra revision from DT */
190 u32 flags; 194 u32 flags;
@@ -193,12 +197,14 @@ struct omap_i2c_dev {
193 u8 *regs; 197 u8 *regs;
194 size_t buf_len; 198 size_t buf_len;
195 struct i2c_adapter adapter; 199 struct i2c_adapter adapter;
200 u8 threshold;
196 u8 fifo_size; /* use as flag and value 201 u8 fifo_size; /* use as flag and value
197 * fifo_size==0 implies no fifo 202 * fifo_size==0 implies no fifo
198 * if set, should be trsh+1 203 * if set, should be trsh+1
199 */ 204 */
200 u8 rev; 205 u8 rev;
201 unsigned b_hw:1; /* bad h/w fixes */ 206 unsigned b_hw:1; /* bad h/w fixes */
207 unsigned receiver:1; /* true when we're in receiver mode */
202 u16 iestate; /* Saved interrupt register */ 208 u16 iestate; /* Saved interrupt register */
203 u16 pscstate; 209 u16 pscstate;
204 u16 scllstate; 210 u16 scllstate;
@@ -417,13 +423,6 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
417 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); 423 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
418 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); 424 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
419 425
420 if (dev->fifo_size) {
421 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
422 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
423 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
424 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
425 }
426
427 /* Take the I2C module out of reset: */ 426 /* Take the I2C module out of reset: */
428 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 427 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
429 428
@@ -461,6 +460,43 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
461 return 0; 460 return 0;
462} 461}
463 462
463static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
464{
465 u16 buf;
466
467 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
468 return;
469
470 /*
471 * Set up notification threshold based on message size. We're doing
472 * this to try and avoid draining feature as much as possible. Whenever
473 * we have big messages to transfer (bigger than our total fifo size)
474 * then we might use draining feature to transfer the remaining bytes.
475 */
476
477 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
478
479 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
480
481 if (is_rx) {
482 /* Clear RX Threshold */
483 buf &= ~(0x3f << 8);
484 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
485 } else {
486 /* Clear TX Threshold */
487 buf &= ~0x3f;
488 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
489 }
490
491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
492
493 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
494 dev->b_hw = 1; /* Enable hardware fixes */
495
496 /* calculate wakeup latency constraint for MPU */
497 dev->latency = (1000000 * dev->threshold) / (1000 * dev->speed / 8);
498}
499
464/* 500/*
465 * Low level master read/write transaction. 501 * Low level master read/write transaction.
466 */ 502 */
@@ -477,6 +513,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
477 if (msg->len == 0) 513 if (msg->len == 0)
478 return -EINVAL; 514 return -EINVAL;
479 515
516 dev->receiver = !!(msg->flags & I2C_M_RD);
517 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
518
480 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); 519 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
481 520
482 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 521 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
@@ -590,8 +629,16 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
590 if (r < 0) 629 if (r < 0)
591 goto out; 630 goto out;
592 631
593 if (dev->set_mpu_wkup_lat != NULL) 632 /*
594 dev->set_mpu_wkup_lat(dev->dev, dev->latency); 633 * When waiting for completion of a i2c transfer, we need to
634 * set a wake up latency constraint for the MPU. This is to
635 * ensure quick enough wakeup from idle, when transfer
636 * completes.
637 */
638 if (dev->latency)
639 pm_qos_add_request(&dev->pm_qos_request,
640 PM_QOS_CPU_DMA_LATENCY,
641 dev->latency);
595 642
596 for (i = 0; i < num; i++) { 643 for (i = 0; i < num; i++) {
597 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 644 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
@@ -599,15 +646,16 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
599 break; 646 break;
600 } 647 }
601 648
602 if (dev->set_mpu_wkup_lat != NULL) 649 if (dev->latency)
603 dev->set_mpu_wkup_lat(dev->dev, -1); 650 pm_qos_remove_request(&dev->pm_qos_request);
604 651
605 if (r == 0) 652 if (r == 0)
606 r = num; 653 r = num;
607 654
608 omap_i2c_wait_for_bb(dev); 655 omap_i2c_wait_for_bb(dev);
609out: 656out:
610 pm_runtime_put(dev->dev); 657 pm_runtime_mark_last_busy(dev->dev);
658 pm_runtime_put_autosuspend(dev->dev);
611 return r; 659 return r;
612} 660}
613 661
@@ -725,186 +773,252 @@ omap_i2c_omap1_isr(int this_irq, void *dev_id)
725 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 773 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
726 * them from the memory to the I2C interface. 774 * them from the memory to the I2C interface.
727 */ 775 */
728static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err) 776static int errata_omap3_i462(struct omap_i2c_dev *dev)
729{ 777{
730 unsigned long timeout = 10000; 778 unsigned long timeout = 10000;
779 u16 stat;
731 780
732 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { 781 do {
733 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 782 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
734 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | 783 if (stat & OMAP_I2C_STAT_XUDF)
784 break;
785
786 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
787 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
735 OMAP_I2C_STAT_XDR)); 788 OMAP_I2C_STAT_XDR));
736 return -ETIMEDOUT; 789 if (stat & OMAP_I2C_STAT_NACK) {
790 dev->cmd_err |= OMAP_I2C_STAT_NACK;
791 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
792 }
793
794 if (stat & OMAP_I2C_STAT_AL) {
795 dev_err(dev->dev, "Arbitration lost\n");
796 dev->cmd_err |= OMAP_I2C_STAT_AL;
797 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
798 }
799
800 return -EIO;
737 } 801 }
738 802
739 cpu_relax(); 803 cpu_relax();
740 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 804 } while (--timeout);
741 }
742 805
743 if (!timeout) { 806 if (!timeout) {
744 dev_err(dev->dev, "timeout waiting on XUDF bit\n"); 807 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
745 return 0; 808 return 0;
746 } 809 }
747 810
748 *err |= OMAP_I2C_STAT_XUDF;
749 return 0; 811 return 0;
750} 812}
751 813
814static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
815 bool is_rdr)
816{
817 u16 w;
818
819 while (num_bytes--) {
820 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
821 *dev->buf++ = w;
822 dev->buf_len--;
823
824 /*
825 * Data reg in 2430, omap3 and
826 * omap4 is 8 bit wide
827 */
828 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
829 *dev->buf++ = w >> 8;
830 dev->buf_len--;
831 }
832 }
833}
834
835static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
836 bool is_xdr)
837{
838 u16 w;
839
840 while (num_bytes--) {
841 w = *dev->buf++;
842 dev->buf_len--;
843
844 /*
845 * Data reg in 2430, omap3 and
846 * omap4 is 8 bit wide
847 */
848 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
849 w |= *dev->buf++ << 8;
850 dev->buf_len--;
851 }
852
853 if (dev->errata & I2C_OMAP_ERRATA_I462) {
854 int ret;
855
856 ret = errata_omap3_i462(dev);
857 if (ret < 0)
858 return ret;
859 }
860
861 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
862 }
863
864 return 0;
865}
866
867static irqreturn_t
868omap_i2c_isr(int irq, void *dev_id)
869{
870 struct omap_i2c_dev *dev = dev_id;
871 irqreturn_t ret = IRQ_HANDLED;
872 u16 mask;
873 u16 stat;
874
875 spin_lock(&dev->lock);
876 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
877 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
878
879 if (stat & mask)
880 ret = IRQ_WAKE_THREAD;
881
882 spin_unlock(&dev->lock);
883
884 return ret;
885}
886
752static irqreturn_t 887static irqreturn_t
753omap_i2c_isr(int this_irq, void *dev_id) 888omap_i2c_isr_thread(int this_irq, void *dev_id)
754{ 889{
755 struct omap_i2c_dev *dev = dev_id; 890 struct omap_i2c_dev *dev = dev_id;
891 unsigned long flags;
756 u16 bits; 892 u16 bits;
757 u16 stat, w; 893 u16 stat;
758 int err, count = 0; 894 int err = 0, count = 0;
895
896 spin_lock_irqsave(&dev->lock, flags);
897 do {
898 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
899 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
900 stat &= bits;
901
902 /* If we're in receiver mode, ignore XDR/XRDY */
903 if (dev->receiver)
904 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
905 else
906 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
759 907
760 if (pm_runtime_suspended(dev->dev)) 908 if (!stat) {
761 return IRQ_NONE; 909 /* my work here is done */
910 goto out;
911 }
762 912
763 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
764 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
765 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); 913 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
766 if (count++ == 100) { 914 if (count++ == 100) {
767 dev_warn(dev->dev, "Too much work in one IRQ\n"); 915 dev_warn(dev->dev, "Too much work in one IRQ\n");
768 break; 916 break;
769 } 917 }
770 918
771 err = 0; 919 if (stat & OMAP_I2C_STAT_NACK) {
772complete:
773 /*
774 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
775 * acked after the data operation is complete.
776 * Ref: TRM SWPU114Q Figure 18-31
777 */
778 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
779 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
780 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
781
782 if (stat & OMAP_I2C_STAT_NACK)
783 err |= OMAP_I2C_STAT_NACK; 920 err |= OMAP_I2C_STAT_NACK;
921 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
922 break;
923 }
784 924
785 if (stat & OMAP_I2C_STAT_AL) { 925 if (stat & OMAP_I2C_STAT_AL) {
786 dev_err(dev->dev, "Arbitration lost\n"); 926 dev_err(dev->dev, "Arbitration lost\n");
787 err |= OMAP_I2C_STAT_AL; 927 err |= OMAP_I2C_STAT_AL;
928 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
929 break;
788 } 930 }
931
789 /* 932 /*
790 * ProDB0017052: Clear ARDY bit twice 933 * ProDB0017052: Clear ARDY bit twice
791 */ 934 */
792 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 935 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
793 OMAP_I2C_STAT_AL)) { 936 OMAP_I2C_STAT_AL)) {
794 omap_i2c_ack_stat(dev, stat & 937 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
795 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | 938 OMAP_I2C_STAT_RDR |
796 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR | 939 OMAP_I2C_STAT_XRDY |
797 OMAP_I2C_STAT_ARDY)); 940 OMAP_I2C_STAT_XDR |
798 omap_i2c_complete_cmd(dev, err); 941 OMAP_I2C_STAT_ARDY));
799 return IRQ_HANDLED; 942 break;
800 } 943 }
801 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { 944
945 if (stat & OMAP_I2C_STAT_RDR) {
802 u8 num_bytes = 1; 946 u8 num_bytes = 1;
803 947
948 if (dev->fifo_size)
949 num_bytes = dev->buf_len;
950
951 omap_i2c_receive_data(dev, num_bytes, true);
952
804 if (dev->errata & I2C_OMAP_ERRATA_I207) 953 if (dev->errata & I2C_OMAP_ERRATA_I207)
805 i2c_omap_errata_i207(dev, stat); 954 i2c_omap_errata_i207(dev, stat);
806 955
807 if (dev->fifo_size) { 956 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
808 if (stat & OMAP_I2C_STAT_RRDY) 957 break;
809 num_bytes = dev->fifo_size; 958 }
810 else /* read RXSTAT on RDR interrupt */ 959
811 num_bytes = (omap_i2c_read_reg(dev, 960 if (stat & OMAP_I2C_STAT_RRDY) {
812 OMAP_I2C_BUFSTAT_REG) 961 u8 num_bytes = 1;
813 >> 8) & 0x3F; 962
814 } 963 if (dev->threshold)
815 while (num_bytes) { 964 num_bytes = dev->threshold;
816 num_bytes--; 965
817 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 966 omap_i2c_receive_data(dev, num_bytes, false);
818 if (dev->buf_len) { 967 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
819 *dev->buf++ = w;
820 dev->buf_len--;
821 /*
822 * Data reg in 2430, omap3 and
823 * omap4 is 8 bit wide
824 */
825 if (dev->flags &
826 OMAP_I2C_FLAG_16BIT_DATA_REG) {
827 if (dev->buf_len) {
828 *dev->buf++ = w >> 8;
829 dev->buf_len--;
830 }
831 }
832 } else {
833 if (stat & OMAP_I2C_STAT_RRDY)
834 dev_err(dev->dev,
835 "RRDY IRQ while no data"
836 " requested\n");
837 if (stat & OMAP_I2C_STAT_RDR)
838 dev_err(dev->dev,
839 "RDR IRQ while no data"
840 " requested\n");
841 break;
842 }
843 }
844 omap_i2c_ack_stat(dev,
845 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
846 continue; 968 continue;
847 } 969 }
848 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { 970
971 if (stat & OMAP_I2C_STAT_XDR) {
849 u8 num_bytes = 1; 972 u8 num_bytes = 1;
850 if (dev->fifo_size) { 973 int ret;
851 if (stat & OMAP_I2C_STAT_XRDY) 974
852 num_bytes = dev->fifo_size; 975 if (dev->fifo_size)
853 else /* read TXSTAT on XDR interrupt */ 976 num_bytes = dev->buf_len;
854 num_bytes = omap_i2c_read_reg(dev, 977
855 OMAP_I2C_BUFSTAT_REG) 978 ret = omap_i2c_transmit_data(dev, num_bytes, true);
856 & 0x3F; 979 if (ret < 0)
857 } 980 break;
858 while (num_bytes) { 981
859 num_bytes--; 982 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
860 w = 0; 983 break;
861 if (dev->buf_len) { 984 }
862 w = *dev->buf++; 985
863 dev->buf_len--; 986 if (stat & OMAP_I2C_STAT_XRDY) {
864 /* 987 u8 num_bytes = 1;
865 * Data reg in 2430, omap3 and 988 int ret;
866 * omap4 is 8 bit wide 989
867 */ 990 if (dev->threshold)
868 if (dev->flags & 991 num_bytes = dev->threshold;
869 OMAP_I2C_FLAG_16BIT_DATA_REG) { 992
870 if (dev->buf_len) { 993 ret = omap_i2c_transmit_data(dev, num_bytes, false);
871 w |= *dev->buf++ << 8; 994 if (ret < 0)
872 dev->buf_len--; 995 break;
873 } 996
874 } 997 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
875 } else {
876 if (stat & OMAP_I2C_STAT_XRDY)
877 dev_err(dev->dev,
878 "XRDY IRQ while no "
879 "data to send\n");
880 if (stat & OMAP_I2C_STAT_XDR)
881 dev_err(dev->dev,
882 "XDR IRQ while no "
883 "data to send\n");
884 break;
885 }
886
887 if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
888 errata_omap3_i462(dev, &stat, &err))
889 goto complete;
890
891 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
892 }
893 omap_i2c_ack_stat(dev,
894 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
895 continue; 998 continue;
896 } 999 }
1000
897 if (stat & OMAP_I2C_STAT_ROVR) { 1001 if (stat & OMAP_I2C_STAT_ROVR) {
898 dev_err(dev->dev, "Receive overrun\n"); 1002 dev_err(dev->dev, "Receive overrun\n");
899 dev->cmd_err |= OMAP_I2C_STAT_ROVR; 1003 err |= OMAP_I2C_STAT_ROVR;
1004 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1005 break;
900 } 1006 }
1007
901 if (stat & OMAP_I2C_STAT_XUDF) { 1008 if (stat & OMAP_I2C_STAT_XUDF) {
902 dev_err(dev->dev, "Transmit underflow\n"); 1009 dev_err(dev->dev, "Transmit underflow\n");
903 dev->cmd_err |= OMAP_I2C_STAT_XUDF; 1010 err |= OMAP_I2C_STAT_XUDF;
1011 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1012 break;
904 } 1013 }
905 } 1014 } while (stat);
1015
1016 omap_i2c_complete_cmd(dev, err);
1017
1018out:
1019 spin_unlock_irqrestore(&dev->lock, flags);
906 1020
907 return count ? IRQ_HANDLED : IRQ_NONE; 1021 return IRQ_HANDLED;
908} 1022}
909 1023
910static const struct i2c_algorithm omap_i2c_algo = { 1024static const struct i2c_algorithm omap_i2c_algo = {
@@ -943,12 +1057,12 @@ omap_i2c_probe(struct platform_device *pdev)
943{ 1057{
944 struct omap_i2c_dev *dev; 1058 struct omap_i2c_dev *dev;
945 struct i2c_adapter *adap; 1059 struct i2c_adapter *adap;
946 struct resource *mem, *irq, *ioarea; 1060 struct resource *mem;
947 const struct omap_i2c_bus_platform_data *pdata = 1061 const struct omap_i2c_bus_platform_data *pdata =
948 pdev->dev.platform_data; 1062 pdev->dev.platform_data;
949 struct device_node *node = pdev->dev.of_node; 1063 struct device_node *node = pdev->dev.of_node;
950 const struct of_device_id *match; 1064 const struct of_device_id *match;
951 irq_handler_t isr; 1065 int irq;
952 int r; 1066 int r;
953 1067
954 /* NOTE: driver uses the static register mapping */ 1068 /* NOTE: driver uses the static register mapping */
@@ -957,23 +1071,23 @@ omap_i2c_probe(struct platform_device *pdev)
957 dev_err(&pdev->dev, "no mem resource?\n"); 1071 dev_err(&pdev->dev, "no mem resource?\n");
958 return -ENODEV; 1072 return -ENODEV;
959 } 1073 }
960 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1074
961 if (!irq) { 1075 irq = platform_get_irq(pdev, 0);
1076 if (irq < 0) {
962 dev_err(&pdev->dev, "no irq resource?\n"); 1077 dev_err(&pdev->dev, "no irq resource?\n");
963 return -ENODEV; 1078 return irq;
964 } 1079 }
965 1080
966 ioarea = request_mem_region(mem->start, resource_size(mem), 1081 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
967 pdev->name); 1082 if (!dev) {
968 if (!ioarea) { 1083 dev_err(&pdev->dev, "Menory allocation failed\n");
969 dev_err(&pdev->dev, "I2C region already claimed\n"); 1084 return -ENOMEM;
970 return -EBUSY;
971 } 1085 }
972 1086
973 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); 1087 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
974 if (!dev) { 1088 if (!dev->base) {
975 r = -ENOMEM; 1089 dev_err(&pdev->dev, "I2C region already claimed\n");
976 goto err_release_region; 1090 return -ENOMEM;
977 } 1091 }
978 1092
979 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 1093 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
@@ -990,17 +1104,13 @@ omap_i2c_probe(struct platform_device *pdev)
990 } else if (pdata != NULL) { 1104 } else if (pdata != NULL) {
991 dev->speed = pdata->clkrate; 1105 dev->speed = pdata->clkrate;
992 dev->flags = pdata->flags; 1106 dev->flags = pdata->flags;
993 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
994 dev->dtrev = pdata->rev; 1107 dev->dtrev = pdata->rev;
995 } 1108 }
996 1109
997 dev->dev = &pdev->dev; 1110 dev->dev = &pdev->dev;
998 dev->irq = irq->start; 1111 dev->irq = irq;
999 dev->base = ioremap(mem->start, resource_size(mem)); 1112
1000 if (!dev->base) { 1113 spin_lock_init(&dev->lock);
1001 r = -ENOMEM;
1002 goto err_free_mem;
1003 }
1004 1114
1005 platform_set_drvdata(pdev, dev); 1115 platform_set_drvdata(pdev, dev);
1006 init_completion(&dev->cmd_complete); 1116 init_completion(&dev->cmd_complete);
@@ -1013,6 +1123,9 @@ omap_i2c_probe(struct platform_device *pdev)
1013 dev->regs = (u8 *)reg_map_ip_v1; 1123 dev->regs = (u8 *)reg_map_ip_v1;
1014 1124
1015 pm_runtime_enable(dev->dev); 1125 pm_runtime_enable(dev->dev);
1126 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1127 pm_runtime_use_autosuspend(dev->dev);
1128
1016 r = pm_runtime_get_sync(dev->dev); 1129 r = pm_runtime_get_sync(dev->dev);
1017 if (IS_ERR_VALUE(r)) 1130 if (IS_ERR_VALUE(r))
1018 goto err_free_mem; 1131 goto err_free_mem;
@@ -1042,32 +1155,31 @@ omap_i2c_probe(struct platform_device *pdev)
1042 1155
1043 dev->fifo_size = (dev->fifo_size / 2); 1156 dev->fifo_size = (dev->fifo_size / 2);
1044 1157
1045 if (dev->rev >= OMAP_I2C_REV_ON_3630_4430) 1158 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
1046 dev->b_hw = 0; /* Disable hardware fixes */
1047 else
1048 dev->b_hw = 1; /* Enable hardware fixes */ 1159 dev->b_hw = 1; /* Enable hardware fixes */
1049 1160
1050 /* calculate wakeup latency constraint for MPU */ 1161 /* calculate wakeup latency constraint for MPU */
1051 if (dev->set_mpu_wkup_lat != NULL) 1162 dev->latency = (1000000 * dev->fifo_size) /
1052 dev->latency = (1000000 * dev->fifo_size) / 1163 (1000 * dev->speed / 8);
1053 (1000 * dev->speed / 8);
1054 } 1164 }
1055 1165
1056 /* reset ASAP, clearing any IRQs */ 1166 /* reset ASAP, clearing any IRQs */
1057 omap_i2c_init(dev); 1167 omap_i2c_init(dev);
1058 1168
1059 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr : 1169 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1060 omap_i2c_isr; 1170 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1061 r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev); 1171 IRQF_NO_SUSPEND, pdev->name, dev);
1172 else
1173 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1174 omap_i2c_isr, omap_i2c_isr_thread,
1175 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1176 pdev->name, dev);
1062 1177
1063 if (r) { 1178 if (r) {
1064 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 1179 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1065 goto err_unuse_clocks; 1180 goto err_unuse_clocks;
1066 } 1181 }
1067 1182
1068 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
1069 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1070
1071 adap = &dev->adapter; 1183 adap = &dev->adapter;
1072 i2c_set_adapdata(adap, dev); 1184 i2c_set_adapdata(adap, dev);
1073 adap->owner = THIS_MODULE; 1185 adap->owner = THIS_MODULE;
@@ -1082,27 +1194,25 @@ omap_i2c_probe(struct platform_device *pdev)
1082 r = i2c_add_numbered_adapter(adap); 1194 r = i2c_add_numbered_adapter(adap);
1083 if (r) { 1195 if (r) {
1084 dev_err(dev->dev, "failure adding adapter\n"); 1196 dev_err(dev->dev, "failure adding adapter\n");
1085 goto err_free_irq; 1197 goto err_unuse_clocks;
1086 } 1198 }
1087 1199
1200 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
1201 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1202
1088 of_i2c_register_devices(adap); 1203 of_i2c_register_devices(adap);
1089 1204
1090 pm_runtime_put(dev->dev); 1205 pm_runtime_mark_last_busy(dev->dev);
1206 pm_runtime_put_autosuspend(dev->dev);
1091 1207
1092 return 0; 1208 return 0;
1093 1209
1094err_free_irq:
1095 free_irq(dev->irq, dev);
1096err_unuse_clocks: 1210err_unuse_clocks:
1097 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1211 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1098 pm_runtime_put(dev->dev); 1212 pm_runtime_put(dev->dev);
1099 iounmap(dev->base);
1100 pm_runtime_disable(&pdev->dev); 1213 pm_runtime_disable(&pdev->dev);
1101err_free_mem: 1214err_free_mem:
1102 platform_set_drvdata(pdev, NULL); 1215 platform_set_drvdata(pdev, NULL);
1103 kfree(dev);
1104err_release_region:
1105 release_mem_region(mem->start, resource_size(mem));
1106 1216
1107 return r; 1217 return r;
1108} 1218}
@@ -1110,12 +1220,10 @@ err_release_region:
1110static int __devexit omap_i2c_remove(struct platform_device *pdev) 1220static int __devexit omap_i2c_remove(struct platform_device *pdev)
1111{ 1221{
1112 struct omap_i2c_dev *dev = platform_get_drvdata(pdev); 1222 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1113 struct resource *mem;
1114 int ret; 1223 int ret;
1115 1224
1116 platform_set_drvdata(pdev, NULL); 1225 platform_set_drvdata(pdev, NULL);
1117 1226
1118 free_irq(dev->irq, dev);
1119 i2c_del_adapter(&dev->adapter); 1227 i2c_del_adapter(&dev->adapter);
1120 ret = pm_runtime_get_sync(&pdev->dev); 1228 ret = pm_runtime_get_sync(&pdev->dev);
1121 if (IS_ERR_VALUE(ret)) 1229 if (IS_ERR_VALUE(ret))
@@ -1124,10 +1232,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
1124 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1232 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1125 pm_runtime_put(&pdev->dev); 1233 pm_runtime_put(&pdev->dev);
1126 pm_runtime_disable(&pdev->dev); 1234 pm_runtime_disable(&pdev->dev);
1127 iounmap(dev->base);
1128 kfree(dev);
1129 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 release_mem_region(mem->start, resource_size(mem));
1131 return 0; 1235 return 0;
1132} 1236}
1133 1237
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
new file mode 100644
index 000000000000..f9399d163af2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -0,0 +1,709 @@
1/*
2 * drivers/i2c/busses/i2c-rcar.c
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
9 *
10 * This file used out-of-tree driver i2c-rcar.c
11 * Copyright (C) 2011-2012 Renesas Electronics Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26#include <linux/clk.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/i2c.h>
33#include <linux/i2c/i2c-rcar.h>
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/platform_device.h>
37#include <linux/pm_runtime.h>
38#include <linux/slab.h>
39#include <linux/spinlock.h>
40
41/* register offsets */
42#define ICSCR 0x00 /* slave ctrl */
43#define ICMCR 0x04 /* master ctrl */
44#define ICSSR 0x08 /* slave status */
45#define ICMSR 0x0C /* master status */
46#define ICSIER 0x10 /* slave irq enable */
47#define ICMIER 0x14 /* master irq enable */
48#define ICCCR 0x18 /* clock dividers */
49#define ICSAR 0x1C /* slave address */
50#define ICMAR 0x20 /* master address */
51#define ICRXTX 0x24 /* data port */
52
53/* ICMCR */
54#define MDBS (1 << 7) /* non-fifo mode switch */
55#define FSCL (1 << 6) /* override SCL pin */
56#define FSDA (1 << 5) /* override SDA pin */
57#define OBPC (1 << 4) /* override pins */
58#define MIE (1 << 3) /* master if enable */
59#define TSBE (1 << 2)
60#define FSB (1 << 1) /* force stop bit */
61#define ESG (1 << 0) /* en startbit gen */
62
63/* ICMSR */
64#define MNR (1 << 6) /* nack received */
65#define MAL (1 << 5) /* arbitration lost */
66#define MST (1 << 4) /* sent a stop */
67#define MDE (1 << 3)
68#define MDT (1 << 2)
69#define MDR (1 << 1)
70#define MAT (1 << 0) /* slave addr xfer done */
71
72/* ICMIE */
73#define MNRE (1 << 6) /* nack irq en */
74#define MALE (1 << 5) /* arblos irq en */
75#define MSTE (1 << 4) /* stop irq en */
76#define MDEE (1 << 3)
77#define MDTE (1 << 2)
78#define MDRE (1 << 1)
79#define MATE (1 << 0) /* address sent irq en */
80
81
82enum {
83 RCAR_BUS_PHASE_ADDR,
84 RCAR_BUS_PHASE_DATA,
85 RCAR_BUS_PHASE_STOP,
86};
87
88enum {
89 RCAR_IRQ_CLOSE,
90 RCAR_IRQ_OPEN_FOR_SEND,
91 RCAR_IRQ_OPEN_FOR_RECV,
92 RCAR_IRQ_OPEN_FOR_STOP,
93};
94
95/*
96 * flags
97 */
98#define ID_LAST_MSG (1 << 0)
99#define ID_IOERROR (1 << 1)
100#define ID_DONE (1 << 2)
101#define ID_ARBLOST (1 << 3)
102#define ID_NACK (1 << 4)
103
104struct rcar_i2c_priv {
105 void __iomem *io;
106 struct i2c_adapter adap;
107 struct i2c_msg *msg;
108
109 spinlock_t lock;
110 wait_queue_head_t wait;
111
112 int pos;
113 int irq;
114 u32 icccr;
115 u32 flags;
116};
117
118#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
119#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
120
121#define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
122#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
123
124#define LOOP_TIMEOUT 1024
125
126/*
127 * basic functions
128 */
129static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
130{
131 writel(val, priv->io + reg);
132}
133
134static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
135{
136 return readl(priv->io + reg);
137}
138
139static void rcar_i2c_init(struct rcar_i2c_priv *priv)
140{
141 /*
142 * reset slave mode.
143 * slave mode is not used on this driver
144 */
145 rcar_i2c_write(priv, ICSIER, 0);
146 rcar_i2c_write(priv, ICSAR, 0);
147 rcar_i2c_write(priv, ICSCR, 0);
148 rcar_i2c_write(priv, ICSSR, 0);
149
150 /* reset master mode */
151 rcar_i2c_write(priv, ICMIER, 0);
152 rcar_i2c_write(priv, ICMCR, 0);
153 rcar_i2c_write(priv, ICMSR, 0);
154 rcar_i2c_write(priv, ICMAR, 0);
155}
156
157static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open)
158{
159 u32 val = MNRE | MALE | MSTE | MATE; /* default */
160
161 switch (open) {
162 case RCAR_IRQ_OPEN_FOR_SEND:
163 val |= MDEE; /* default + send */
164 break;
165 case RCAR_IRQ_OPEN_FOR_RECV:
166 val |= MDRE; /* default + read */
167 break;
168 case RCAR_IRQ_OPEN_FOR_STOP:
169 val = MSTE; /* stop irq only */
170 break;
171 case RCAR_IRQ_CLOSE:
172 default:
173 val = 0; /* all close */
174 break;
175 }
176 rcar_i2c_write(priv, ICMIER, val);
177}
178
179static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
180{
181 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
182}
183
184/*
185 * bus control functions
186 */
187static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
188{
189 int i;
190
191 for (i = 0; i < LOOP_TIMEOUT; i++) {
192 /* make sure that bus is not busy */
193 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
194 return 0;
195 udelay(1);
196 }
197
198 return -EBUSY;
199}
200
201static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase)
202{
203 switch (phase) {
204 case RCAR_BUS_PHASE_ADDR:
205 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG);
206 break;
207 case RCAR_BUS_PHASE_DATA:
208 rcar_i2c_write(priv, ICMCR, MDBS | MIE);
209 break;
210 case RCAR_BUS_PHASE_STOP:
211 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB);
212 break;
213 }
214}
215
216/*
217 * clock function
218 */
219static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
220 u32 bus_speed,
221 struct device *dev)
222{
223 struct clk *clkp = clk_get(NULL, "peripheral_clk");
224 u32 scgd, cdf;
225 u32 round, ick;
226 u32 scl;
227
228 if (!clkp) {
229 dev_err(dev, "there is no peripheral_clk\n");
230 return -EIO;
231 }
232
233 /*
234 * calculate SCL clock
235 * see
236 * ICCCR
237 *
238 * ick = clkp / (1 + CDF)
239 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
240 *
241 * ick : I2C internal clock < 20 MHz
242 * ticf : I2C SCL falling time = 35 ns here
243 * tr : I2C SCL rising time = 200 ns here
244 * intd : LSI internal delay = 50 ns here
245 * clkp : peripheral_clk
246 * F[] : integer up-valuation
247 */
248 for (cdf = 0; cdf < 4; cdf++) {
249 ick = clk_get_rate(clkp) / (1 + cdf);
250 if (ick < 20000000)
251 goto ick_find;
252 }
253 dev_err(dev, "there is no best CDF\n");
254 return -EIO;
255
256ick_find:
257 /*
258 * it is impossible to calculate large scale
259 * number on u32. separate it
260 *
261 * F[(ticf + tr + intd) * ick]
262 * = F[(35 + 200 + 50)ns * ick]
263 * = F[285 * ick / 1000000000]
264 * = F[(ick / 1000000) * 285 / 1000]
265 */
266 round = (ick + 500000) / 1000000 * 285;
267 round = (round + 500) / 1000;
268
269 /*
270 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
271 *
272 * Calculation result (= SCL) should be less than
273 * bus_speed for hardware safety
274 */
275 for (scgd = 0; scgd < 0x40; scgd++) {
276 scl = ick / (20 + (scgd * 8) + round);
277 if (scl <= bus_speed)
278 goto scgd_find;
279 }
280 dev_err(dev, "it is impossible to calculate best SCL\n");
281 return -EIO;
282
283scgd_find:
284 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
285 scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd);
286
287 /*
288 * keep icccr value
289 */
290 priv->icccr = (scgd << 2 | cdf);
291
292 return 0;
293}
294
295static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv)
296{
297 rcar_i2c_write(priv, ICCCR, priv->icccr);
298}
299
300/*
301 * status functions
302 */
303static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv)
304{
305 return rcar_i2c_read(priv, ICMSR);
306}
307
308#define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
309static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
310{
311 rcar_i2c_write(priv, ICMSR, ~bit);
312}
313
314/*
315 * recv/send functions
316 */
317static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
318{
319 rcar_i2c_set_addr(priv, 1);
320 rcar_i2c_status_clear(priv);
321 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
322 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV);
323
324 return 0;
325}
326
327static int rcar_i2c_send(struct rcar_i2c_priv *priv)
328{
329 int ret;
330
331 /*
332 * It should check bus status when send case
333 */
334 ret = rcar_i2c_bus_barrier(priv);
335 if (ret < 0)
336 return ret;
337
338 rcar_i2c_set_addr(priv, 0);
339 rcar_i2c_status_clear(priv);
340 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
341 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND);
342
343 return 0;
344}
345
346#define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE))
347#define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR))
348
349/*
350 * interrupt functions
351 */
352static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
353{
354 struct i2c_msg *msg = priv->msg;
355
356 /*
357 * FIXME
358 * sometimes, unknown interrupt happened.
359 * Do nothing
360 */
361 if (!(msr & MDE))
362 return 0;
363
364 /*
365 * If address transfer phase finished,
366 * goto data phase.
367 */
368 if (msr & MAT)
369 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
370
371 if (priv->pos < msg->len) {
372 /*
373 * Prepare next data to ICRXTX register.
374 * This data will go to _SHIFT_ register.
375 *
376 * *
377 * [ICRXTX] -> [SHIFT] -> [I2C bus]
378 */
379 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
380 priv->pos++;
381
382 } else {
383 /*
384 * The last data was pushed to ICRXTX on _PREV_ empty irq.
385 * It is on _SHIFT_ register, and will sent to I2C bus.
386 *
387 * *
388 * [ICRXTX] -> [SHIFT] -> [I2C bus]
389 */
390
391 if (priv->flags & ID_LAST_MSG)
392 /*
393 * If current msg is the _LAST_ msg,
394 * prepare stop condition here.
395 * ID_DONE will be set on STOP irq.
396 */
397 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
398 else
399 /*
400 * If current msg is _NOT_ last msg,
401 * it doesn't call stop phase.
402 * thus, there is no STOP irq.
403 * return ID_DONE here.
404 */
405 return ID_DONE;
406 }
407
408 rcar_i2c_send_restart(priv);
409
410 return 0;
411}
412
413static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
414{
415 struct i2c_msg *msg = priv->msg;
416
417 /*
418 * FIXME
419 * sometimes, unknown interrupt happened.
420 * Do nothing
421 */
422 if (!(msr & MDR))
423 return 0;
424
425 if (msr & MAT) {
426 /*
427 * Address transfer phase finished,
428 * but, there is no data at this point.
429 * Do nothing.
430 */
431 } else if (priv->pos < msg->len) {
432 /*
433 * get received data
434 */
435 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
436 priv->pos++;
437 }
438
439 /*
440 * If next received data is the _LAST_,
441 * go to STOP phase,
442 * otherwise, go to DATA phase.
443 */
444 if (priv->pos + 1 >= msg->len)
445 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
446 else
447 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
448
449 rcar_i2c_recv_restart(priv);
450
451 return 0;
452}
453
454static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
455{
456 struct rcar_i2c_priv *priv = ptr;
457 struct device *dev = rcar_i2c_priv_to_dev(priv);
458 u32 msr;
459
460 /*-------------- spin lock -----------------*/
461 spin_lock(&priv->lock);
462
463 msr = rcar_i2c_status_get(priv);
464
465 /*
466 * Arbitration lost
467 */
468 if (msr & MAL) {
469 /*
470 * CAUTION
471 *
472 * When arbitration lost, device become _slave_ mode.
473 */
474 dev_dbg(dev, "Arbitration Lost\n");
475 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
476 goto out;
477 }
478
479 /*
480 * Stop
481 */
482 if (msr & MST) {
483 dev_dbg(dev, "Stop\n");
484 rcar_i2c_flags_set(priv, ID_DONE);
485 goto out;
486 }
487
488 /*
489 * Nack
490 */
491 if (msr & MNR) {
492 dev_dbg(dev, "Nack\n");
493
494 /* go to stop phase */
495 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
496 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP);
497 rcar_i2c_flags_set(priv, ID_NACK);
498 goto out;
499 }
500
501 /*
502 * recv/send
503 */
504 if (rcar_i2c_is_recv(priv))
505 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
506 else
507 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
508
509out:
510 if (rcar_i2c_flags_has(priv, ID_DONE)) {
511 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE);
512 rcar_i2c_status_clear(priv);
513 wake_up(&priv->wait);
514 }
515
516 spin_unlock(&priv->lock);
517 /*-------------- spin unlock -----------------*/
518
519 return IRQ_HANDLED;
520}
521
522static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
523 struct i2c_msg *msgs,
524 int num)
525{
526 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
527 struct device *dev = rcar_i2c_priv_to_dev(priv);
528 unsigned long flags;
529 int i, ret, timeout;
530
531 pm_runtime_get_sync(dev);
532
533 /*-------------- spin lock -----------------*/
534 spin_lock_irqsave(&priv->lock, flags);
535
536 rcar_i2c_init(priv);
537 rcar_i2c_clock_start(priv);
538
539 spin_unlock_irqrestore(&priv->lock, flags);
540 /*-------------- spin unlock -----------------*/
541
542 ret = -EINVAL;
543 for (i = 0; i < num; i++) {
544 /*-------------- spin lock -----------------*/
545 spin_lock_irqsave(&priv->lock, flags);
546
547 /* init each data */
548 priv->msg = &msgs[i];
549 priv->pos = 0;
550 priv->flags = 0;
551 if (priv->msg == &msgs[num - 1])
552 rcar_i2c_flags_set(priv, ID_LAST_MSG);
553
554 /* start send/recv */
555 if (rcar_i2c_is_recv(priv))
556 ret = rcar_i2c_recv(priv);
557 else
558 ret = rcar_i2c_send(priv);
559
560 spin_unlock_irqrestore(&priv->lock, flags);
561 /*-------------- spin unlock -----------------*/
562
563 if (ret < 0)
564 break;
565
566 /*
567 * wait result
568 */
569 timeout = wait_event_timeout(priv->wait,
570 rcar_i2c_flags_has(priv, ID_DONE),
571 5 * HZ);
572 if (!timeout) {
573 ret = -ETIMEDOUT;
574 break;
575 }
576
577 /*
578 * error handling
579 */
580 if (rcar_i2c_flags_has(priv, ID_NACK)) {
581 ret = -EREMOTEIO;
582 break;
583 }
584
585 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
586 ret = -EAGAIN;
587 break;
588 }
589
590 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
591 ret = -EIO;
592 break;
593 }
594
595 ret = i + 1; /* The number of transfer */
596 }
597
598 pm_runtime_put(dev);
599
600 if (ret < 0)
601 dev_err(dev, "error %d : %x\n", ret, priv->flags);
602
603 return ret;
604}
605
606static u32 rcar_i2c_func(struct i2c_adapter *adap)
607{
608 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
609}
610
611static const struct i2c_algorithm rcar_i2c_algo = {
612 .master_xfer = rcar_i2c_master_xfer,
613 .functionality = rcar_i2c_func,
614};
615
616static int __devinit rcar_i2c_probe(struct platform_device *pdev)
617{
618 struct i2c_rcar_platform_data *pdata = pdev->dev.platform_data;
619 struct rcar_i2c_priv *priv;
620 struct i2c_adapter *adap;
621 struct resource *res;
622 struct device *dev = &pdev->dev;
623 u32 bus_speed;
624 int ret;
625
626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627 if (!res) {
628 dev_err(dev, "no mmio resources\n");
629 return -ENODEV;
630 }
631
632 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
633 if (!priv) {
634 dev_err(dev, "no mem for private data\n");
635 return -ENOMEM;
636 }
637
638 bus_speed = 100000; /* default 100 kHz */
639 if (pdata && pdata->bus_speed)
640 bus_speed = pdata->bus_speed;
641 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
642 if (ret < 0)
643 return ret;
644
645 priv->io = devm_ioremap(dev, res->start, resource_size(res));
646 if (!priv->io) {
647 dev_err(dev, "cannot ioremap\n");
648 return -ENODEV;
649 }
650
651 priv->irq = platform_get_irq(pdev, 0);
652 init_waitqueue_head(&priv->wait);
653 spin_lock_init(&priv->lock);
654
655 adap = &priv->adap;
656 adap->nr = pdev->id;
657 adap->algo = &rcar_i2c_algo;
658 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
659 adap->retries = 3;
660 adap->dev.parent = dev;
661 i2c_set_adapdata(adap, priv);
662 strlcpy(adap->name, pdev->name, sizeof(adap->name));
663
664 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0,
665 dev_name(dev), priv);
666 if (ret < 0) {
667 dev_err(dev, "cannot get irq %d\n", priv->irq);
668 return ret;
669 }
670
671 ret = i2c_add_numbered_adapter(adap);
672 if (ret < 0) {
673 dev_err(dev, "reg adap failed: %d\n", ret);
674 return ret;
675 }
676
677 pm_runtime_enable(dev);
678 platform_set_drvdata(pdev, priv);
679
680 dev_info(dev, "probed\n");
681
682 return 0;
683}
684
685static int __devexit rcar_i2c_remove(struct platform_device *pdev)
686{
687 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
688 struct device *dev = &pdev->dev;
689
690 i2c_del_adapter(&priv->adap);
691 pm_runtime_disable(dev);
692
693 return 0;
694}
695
696static struct platform_driver rcar_i2c_drv = {
697 .driver = {
698 .name = "i2c-rcar",
699 .owner = THIS_MODULE,
700 },
701 .probe = rcar_i2c_probe,
702 .remove = __devexit_p(rcar_i2c_remove),
703};
704
705module_platform_driver(rcar_i2c_drv);
706
707MODULE_LICENSE("GPL");
708MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
709MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 4d07dea9bca9..3e0335f1fc60 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -601,14 +601,14 @@ static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
601 int ret; 601 int ret;
602 602
603 pm_runtime_get_sync(&adap->dev); 603 pm_runtime_get_sync(&adap->dev);
604 clk_enable(i2c->clk); 604 clk_prepare_enable(i2c->clk);
605 605
606 for (retry = 0; retry < adap->retries; retry++) { 606 for (retry = 0; retry < adap->retries; retry++) {
607 607
608 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 608 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
609 609
610 if (ret != -EAGAIN) { 610 if (ret != -EAGAIN) {
611 clk_disable(i2c->clk); 611 clk_disable_unprepare(i2c->clk);
612 pm_runtime_put(&adap->dev); 612 pm_runtime_put(&adap->dev);
613 return ret; 613 return ret;
614 } 614 }
@@ -618,7 +618,7 @@ static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
618 udelay(100); 618 udelay(100);
619 } 619 }
620 620
621 clk_disable(i2c->clk); 621 clk_disable_unprepare(i2c->clk);
622 pm_runtime_put(&adap->dev); 622 pm_runtime_put(&adap->dev);
623 return -EREMOTEIO; 623 return -EREMOTEIO;
624} 624}
@@ -977,7 +977,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
977 977
978 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 978 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
979 979
980 clk_enable(i2c->clk); 980 clk_prepare_enable(i2c->clk);
981 981
982 /* map the registers */ 982 /* map the registers */
983 983
@@ -1065,7 +1065,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
1065 pm_runtime_enable(&i2c->adap.dev); 1065 pm_runtime_enable(&i2c->adap.dev);
1066 1066
1067 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1067 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1068 clk_disable(i2c->clk); 1068 clk_disable_unprepare(i2c->clk);
1069 return 0; 1069 return 0;
1070 1070
1071 err_cpufreq: 1071 err_cpufreq:
@@ -1082,7 +1082,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
1082 kfree(i2c->ioarea); 1082 kfree(i2c->ioarea);
1083 1083
1084 err_clk: 1084 err_clk:
1085 clk_disable(i2c->clk); 1085 clk_disable_unprepare(i2c->clk);
1086 clk_put(i2c->clk); 1086 clk_put(i2c->clk);
1087 1087
1088 err_noclk: 1088 err_noclk:
@@ -1106,7 +1106,7 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
1106 i2c_del_adapter(&i2c->adap); 1106 i2c_del_adapter(&i2c->adap);
1107 free_irq(i2c->irq, i2c); 1107 free_irq(i2c->irq, i2c);
1108 1108
1109 clk_disable(i2c->clk); 1109 clk_disable_unprepare(i2c->clk);
1110 clk_put(i2c->clk); 1110 clk_put(i2c->clk);
1111 1111
1112 iounmap(i2c->regs); 1112 iounmap(i2c->regs);
@@ -1135,9 +1135,9 @@ static int s3c24xx_i2c_resume(struct device *dev)
1135 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1135 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1136 1136
1137 i2c->suspended = 0; 1137 i2c->suspended = 0;
1138 clk_enable(i2c->clk); 1138 clk_prepare_enable(i2c->clk);
1139 s3c24xx_i2c_init(i2c); 1139 s3c24xx_i2c_init(i2c);
1140 clk_disable(i2c->clk); 1140 clk_disable_unprepare(i2c->clk);
1141 1141
1142 return 0; 1142 return 0;
1143} 1143}
diff --git a/include/linux/i2c-algo-pca.h b/include/linux/i2c-algo-pca.h
index 1364d62e2fbe..a3c3ecd59f08 100644
--- a/include/linux/i2c-algo-pca.h
+++ b/include/linux/i2c-algo-pca.h
@@ -62,6 +62,7 @@ struct i2c_algo_pca_data {
62 * 330000, 288000, 217000, 146000, 88000, 59000, 44000, 36000 62 * 330000, 288000, 217000, 146000, 88000, 59000, 44000, 36000
63 * For PCA9665, use the frequency you want here. */ 63 * For PCA9665, use the frequency you want here. */
64 unsigned int i2c_clock; 64 unsigned int i2c_clock;
65 unsigned int chip;
65}; 66};
66 67
67int i2c_pca_add_bus(struct i2c_adapter *); 68int i2c_pca_add_bus(struct i2c_adapter *);
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 92a0dc75bc74..df804ba73e0b 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -34,7 +34,6 @@ struct omap_i2c_bus_platform_data {
34 u32 clkrate; 34 u32 clkrate;
35 u32 rev; 35 u32 rev;
36 u32 flags; 36 u32 flags;
37 void (*set_mpu_wkup_lat)(struct device *dev, long set);
38}; 37};
39 38
40#endif 39#endif
diff --git a/include/linux/i2c/i2c-rcar.h b/include/linux/i2c/i2c-rcar.h
new file mode 100644
index 000000000000..496f5c2b23c9
--- /dev/null
+++ b/include/linux/i2c/i2c-rcar.h
@@ -0,0 +1,10 @@
1#ifndef __I2C_R_CAR_H__
2#define __I2C_R_CAR_H__
3
4#include <linux/platform_device.h>
5
6struct i2c_rcar_platform_data {
7 u32 bus_speed;
8};
9
10#endif /* __I2C_R_CAR_H__ */
diff --git a/include/linux/platform_data/i2c-nomadik.h b/include/linux/platform_data/i2c-nomadik.h
index c2303c3e4803..3a8be9cdc95c 100644
--- a/include/linux/platform_data/i2c-nomadik.h
+++ b/include/linux/platform_data/i2c-nomadik.h
@@ -28,7 +28,7 @@ enum i2c_freq_mode {
28 * @sm: speed mode 28 * @sm: speed mode
29 */ 29 */
30struct nmk_i2c_controller { 30struct nmk_i2c_controller {
31 unsigned long clk_freq; 31 u32 clk_freq;
32 unsigned short slsu; 32 unsigned short slsu;
33 unsigned char tft; 33 unsigned char tft;
34 unsigned char rft; 34 unsigned char rft;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 16:23:36 -0400