Merge remote-tracking branch 'shesselba/for-mvebu/pinctrl-dove' into mvebu/pinctrl

8 files changed, 202 insertions, 113 deletions

diff --git a/Documentation/devicetree/bindings/arm/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell,dove.txt
new file mode 100644
index 000000000000..aaaf64c56e44
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,dove.txt
@@ -0,0 +1,22 @@
+Marvell Dove Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with a Marvell Dove SoC shall have the following properties:
+
+Required root node property:
+- compatible: must contain "marvell,dove";
+
+* Global Configuration registers
+
+Global Configuration registers of Dove SoC are shared by a syscon node.
+
+Required properties:
+- compatible: must contain "marvell,dove-global-config" and "syscon".
+- reg: base address and size of the Global Configuration registers.
+
+Example:
+
+gconf: global-config@e802c {
+        compatible = "marvell,dove-global-config", "syscon";
+        reg = <0xe802c 0x14>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
index 01ef408e205f..adda2a8d1d52 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -5,6 +5,7 @@ part and usage.
 
 Required properties:
 - compatible: "marvell,88f6710-pinctrl"
+- reg: register specifier of MPP registers
 
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index bfa0a2e5e0cb..373dbccd7ab0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
 Required properties:
 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
               "marvell,mv78460-pinctrl"
+- reg: register specifier of MPP registers
 
 This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
 
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index 50ec3512a292..cf52477cc7ee 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
 Required properties:
 - compatible: "marvell,dove-pinctrl"
 - clocks: (optional) phandle of pdma clock
+- reg: register specifiers of MPP, MPP4, and PMU MPP registers
 
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 95daf6335c37..730444a9a4de 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -8,6 +8,7 @@ Required properties:
               "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
               "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
               "marvell,98dx4122-pinctrl"
+- reg: register specifier of MPP registers
 
 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
index 0a26c3aa4e6d..0c09f4eb2af0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -37,7 +37,7 @@ uart1: serial@12100 {
 
 pinctrl: pinctrl@d0200 {
         compatible = "marvell,dove-pinctrl";
-        reg = <0xd0200 0x20>;
+        reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
 
         pmx_uart1_sw: pmx-uart1-sw {
                 marvell,pins = "mpp_uart1";
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 366fa541ee91..8dc4948c1202 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -8,6 +8,7 @@ config PINCTRL_MVEBU
 config PINCTRL_DOVE
         bool
         select PINCTRL_MVEBU
+        select MFD_SYSCON
 
 config PINCTRL_KIRKWOOD
         bool
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index da9ca26360fd..9e7ff651c018 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -18,40 +18,53 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
 #include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
 
 #include "pinctrl-mvebu.h"
 
-#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
-#define DOVE_MPP_VIRT_BASE              (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
-#define DOVE_PMU_MPP_GENERAL_CTRL       (DOVE_MPP_VIRT_BASE + 0x10)
-#define  DOVE_AU0_AC97_SEL              BIT(16)
-#define DOVE_PMU_SIGNAL_SELECT_0        (DOVE_SB_REGS_VIRT_BASE + 0xd802C)
-#define DOVE_PMU_SIGNAL_SELECT_1        (DOVE_SB_REGS_VIRT_BASE + 0xd8030)
-#define DOVE_GLOBAL_CONFIG_1            (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
-#define DOVE_GLOBAL_CONFIG_1            (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
-#define  DOVE_TWSI_ENABLE_OPTION1       BIT(7)
-#define DOVE_GLOBAL_CONFIG_2            (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
-#define  DOVE_TWSI_ENABLE_OPTION2       BIT(20)
-#define  DOVE_TWSI_ENABLE_OPTION3       BIT(21)
-#define  DOVE_TWSI_OPTION3_GPIO         BIT(22)
-#define DOVE_SSP_CTRL_STATUS_1          (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
-#define  DOVE_SSP_ON_AU1                BIT(0)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
-#define  DOVE_AU1_SPDIFO_GPIO_EN        BIT(1)
-#define  DOVE_NAND_GPIO_EN              BIT(0)
-#define DOVE_GPIO_LO_VIRT_BASE          (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
-#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
-#define  DOVE_SPI_GPIO_SEL              BIT(5)
-#define  DOVE_UART1_GPIO_SEL            BIT(4)
-#define  DOVE_AU1_GPIO_SEL              BIT(3)
-#define  DOVE_CAM_GPIO_SEL              BIT(2)
-#define  DOVE_SD1_GPIO_SEL              BIT(1)
-#define  DOVE_SD0_GPIO_SEL              BIT(0)
+/* Internal registers can be configured at any 1 MiB aligned address */
+#define INT_REGS_MASK           ~(SZ_1M - 1)
+#define MPP4_REGS_OFFS          0xd0440
+#define PMU_REGS_OFFS           0xd802c
+#define GC_REGS_OFFS            0xe802c
+
+/* MPP Base registers */
+#define PMU_MPP_GENERAL_CTRL    0x10
+#define  AU0_AC97_SEL           BIT(16)
+
+/* MPP Control 4 register */
+#define SPI_GPIO_SEL            BIT(5)
+#define UART1_GPIO_SEL          BIT(4)
+#define AU1_GPIO_SEL            BIT(3)
+#define CAM_GPIO_SEL            BIT(2)
+#define SD1_GPIO_SEL            BIT(1)
+#define SD0_GPIO_SEL            BIT(0)
+
+/* PMU Signal Select registers */
+#define PMU_SIGNAL_SELECT_0     0x00
+#define PMU_SIGNAL_SELECT_1     0x04
+
+/* Global Config regmap registers */
+#define GLOBAL_CONFIG_1         0x00
+#define  TWSI_ENABLE_OPTION1    BIT(7)
+#define GLOBAL_CONFIG_2         0x04
+#define  TWSI_ENABLE_OPTION2    BIT(20)
+#define  TWSI_ENABLE_OPTION3    BIT(21)
+#define  TWSI_OPTION3_GPIO      BIT(22)
+#define SSP_CTRL_STATUS_1       0x08
+#define  SSP_ON_AU1             BIT(0)
+#define MPP_GENERAL_CONFIG      0x10
+#define  AU1_SPDIFO_GPIO_EN     BIT(1)
+#define  NAND_GPIO_EN           BIT(0)
 
 #define CONFIG_PMU      BIT(4)
 
 static void __iomem *mpp_base;
+static void __iomem *mpp4_base;
+static void __iomem *pmu_base;
+static struct regmap *gconfmap;
 
 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config)
 {
@@ -67,13 +80,13 @@ static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config)
 {
         unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
         unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
-        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
         unsigned long func;
 
         if ((pmu & BIT(pid)) == 0)
                 return default_mpp_ctrl_get(mpp_base, pid, config);
 
-        func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
+        func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
         *config = (func >> shift) & MVEBU_MPP_MASK;
         *config |= CONFIG_PMU;
 
@@ -84,43 +97,43 @@ static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config)
 {
         unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
         unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
-        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
         unsigned long func;
 
         if ((config & CONFIG_PMU) == 0) {
-                writel(pmu & ~BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL);
+                writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
                 return default_mpp_ctrl_set(mpp_base, pid, config);
         }
 
-        writel(pmu | BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL);
-        func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
+        writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
+        func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
         func &= ~(MVEBU_MPP_MASK << shift);
         func |= (config & MVEBU_MPP_MASK) << shift;
-        writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
+        writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
 
         return 0;
 }
 
 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config)
 {
-        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mpp4 = readl(mpp4_base);
         unsigned long mask;
 
         switch (pid) {
         case 24: /* mpp_camera */
-                mask = DOVE_CAM_GPIO_SEL;
+                mask = CAM_GPIO_SEL;
                 break;
         case 40: /* mpp_sdio0 */
-                mask = DOVE_SD0_GPIO_SEL;
+                mask = SD0_GPIO_SEL;
                 break;
         case 46: /* mpp_sdio1 */
-                mask = DOVE_SD1_GPIO_SEL;
+                mask = SD1_GPIO_SEL;
                 break;
         case 58: /* mpp_spi0 */
-                mask = DOVE_SPI_GPIO_SEL;
+                mask = SPI_GPIO_SEL;
                 break;
         case 62: /* mpp_uart1 */
-                mask = DOVE_UART1_GPIO_SEL;
+                mask = UART1_GPIO_SEL;
                 break;
         default:
                 return -EINVAL;
@@ -133,24 +146,24 @@ static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config)
 
 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config)
 {
-        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mpp4 = readl(mpp4_base);
         unsigned long mask;
 
         switch (pid) {
         case 24: /* mpp_camera */
-                mask = DOVE_CAM_GPIO_SEL;
+                mask = CAM_GPIO_SEL;
                 break;
         case 40: /* mpp_sdio0 */
-                mask = DOVE_SD0_GPIO_SEL;
+                mask = SD0_GPIO_SEL;
                 break;
         case 46: /* mpp_sdio1 */
-                mask = DOVE_SD1_GPIO_SEL;
+                mask = SD1_GPIO_SEL;
                 break;
         case 58: /* mpp_spi0 */
-                mask = DOVE_SPI_GPIO_SEL;
+                mask = SPI_GPIO_SEL;
                 break;
         case 62: /* mpp_uart1 */
-                mask = DOVE_UART1_GPIO_SEL;
+                mask = UART1_GPIO_SEL;
                 break;
         default:
                 return -EINVAL;
@@ -160,69 +173,69 @@ static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config)
         if (config)
                 mpp4 |= mask;
 
-        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+        writel(mpp4, mpp4_base);
 
         return 0;
 }
 
 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config)
 {
-        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        unsigned int gmpp;
 
-        *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+        regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
+        *config = ((gmpp & NAND_GPIO_EN) != 0);
 
         return 0;
 }
 
 static int dove_nand_ctrl_set(unsigned pid, unsigned long config)
 {
-        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
-
-        gmpp &= ~DOVE_NAND_GPIO_EN;
-        if (config)
-                gmpp |= DOVE_NAND_GPIO_EN;
-
-        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
-
+        regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
+                           NAND_GPIO_EN,
+                           (config) ? NAND_GPIO_EN : 0);
         return 0;
 }
 
 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config)
 {
-        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
 
-        *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+        *config = ((pmu & AU0_AC97_SEL) != 0);
 
         return 0;
 }
 
 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config)
 {
-        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
 
-        pmu &= ~DOVE_AU0_AC97_SEL;
+        pmu &= ~AU0_AC97_SEL;
         if (config)
-                pmu |= DOVE_AU0_AC97_SEL;
-        writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+                pmu |= AU0_AC97_SEL;
+        writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL);
 
         return 0;
 }
 
 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config)
 {
-        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
-        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
-        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
-        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+        unsigned int mpp4 = readl(mpp4_base);
+        unsigned int sspc1;
+        unsigned int gmpp;
+        unsigned int gcfg2;
+
+        regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
+        regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
+        regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
 
         *config = 0;
-        if (mpp4 & DOVE_AU1_GPIO_SEL)
+        if (mpp4 & AU1_GPIO_SEL)
                 *config |= BIT(3);
-        if (sspc1 & DOVE_SSP_ON_AU1)
+        if (sspc1 & SSP_ON_AU1)
                 *config |= BIT(2);
-        if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+        if (gmpp & AU1_SPDIFO_GPIO_EN)
                 *config |= BIT(1);
-        if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+        if (gcfg2 & TWSI_OPTION3_GPIO)
                 *config |= BIT(0);
 
         /* SSP/TWSI only if I2S1 not set*/
@@ -236,32 +249,22 @@ static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config)
 
 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config)
 {
-        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
-        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
-        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
-        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+        unsigned int mpp4 = readl(mpp4_base);
 
-        /*
-         * clear all audio1 related bits before configure
-         */
-        gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
-        gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
-        sspc1 &= ~DOVE_SSP_ON_AU1;
-        mpp4 &= ~DOVE_AU1_GPIO_SEL;
-
-        if (config & BIT(0))
-                gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
-        if (config & BIT(1))
-                gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
-        if (config & BIT(2))
-                sspc1 |= DOVE_SSP_ON_AU1;
+        mpp4 &= ~AU1_GPIO_SEL;
         if (config & BIT(3))
-                mpp4 |= DOVE_AU1_GPIO_SEL;
-
-        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
-        writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
-        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
-        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+                mpp4 |= AU1_GPIO_SEL;
+        writel(mpp4, mpp4_base);
+
+        regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
+                           SSP_ON_AU1,
+                           (config & BIT(2)) ? SSP_ON_AU1 : 0);
+        regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
+                           AU1_SPDIFO_GPIO_EN,
+                           (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
+        regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
+                           TWSI_OPTION3_GPIO,
+                           (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
 
         return 0;
 }
@@ -307,15 +310,18 @@ static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input)
 
 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config)
 {
-        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
-        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+        unsigned int gcfg1;
+        unsigned int gcfg2;
+
+        regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
+        regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
 
         *config = 0;
-        if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+        if (gcfg1 & TWSI_ENABLE_OPTION1)
                 *config = 1;
-        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+        else if (gcfg2 & TWSI_ENABLE_OPTION2)
                 *config = 2;
-        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+        else if (gcfg2 & TWSI_ENABLE_OPTION3)
                 *config = 3;
 
         return 0;
@@ -323,26 +329,27 @@ static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config)
 
 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config)
 {
-        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
-        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
-
-        gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
-        gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
+        unsigned int gcfg1 = 0;
+        unsigned int gcfg2 = 0;
 
         switch (config) {
         case 1:
-                gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+                gcfg1 = TWSI_ENABLE_OPTION1;
                 break;
         case 2:
-                gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+                gcfg2 = TWSI_ENABLE_OPTION2;
                 break;
         case 3:
-                gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+                gcfg2 = TWSI_ENABLE_OPTION3;
                 break;
         }
 
-        writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
-        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+        regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
+                           TWSI_ENABLE_OPTION1,
+                           gcfg1);
+        regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
+                           TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
+                           gcfg2);
 
         return 0;
 }
@@ -749,9 +756,17 @@ static struct of_device_id dove_pinctrl_of_match[] = {
         { }
 };
 
+static struct regmap_config gc_regmap_config = {
+        .reg_bits = 32,
+        .val_bits = 32,
+        .reg_stride = 4,
+        .max_register = 5,
+};
+
 static int dove_pinctrl_probe(struct platform_device *pdev)
 {
-        struct resource *res;
+        struct resource *res, *mpp_res;
+        struct resource fb_res;
         const struct of_device_id *match =
                 of_match_device(dove_pinctrl_of_match, &pdev->dev);
         pdev->dev.platform_data = (void *)match->data;
@@ -767,11 +782,58 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
         }
         clk_prepare_enable(clk);
 
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        mpp_base = devm_ioremap_resource(&pdev->dev, res);
+        mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res);
         if (IS_ERR(mpp_base))
                 return PTR_ERR(mpp_base);
 
+        /* prepare fallback resource */
+        memcpy(&fb_res, mpp_res, sizeof(struct resource));
+        fb_res.start = 0;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
+                adjust_resource(&fb_res,
+                        (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
+                res = &fb_res;
+        }
+
+        mpp4_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(mpp4_base))
+                return PTR_ERR(mpp4_base);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+        if (!res) {
+                dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
+                adjust_resource(&fb_res,
+                        (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
+                res = &fb_res;
+        }
+
+        pmu_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pmu_base))
+                return PTR_ERR(pmu_base);
+
+        gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
+        if (IS_ERR(gconfmap)) {
+                void __iomem *gc_base;
+
+                dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
+                adjust_resource(&fb_res,
+                        (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
+                gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
+                if (IS_ERR(gc_base))
+                        return PTR_ERR(gc_base);
+                gconfmap = devm_regmap_init_mmio(&pdev->dev,
+                                                 gc_base, &gc_regmap_config);
+                if (IS_ERR(gconfmap))
+                        return PTR_ERR(gconfmap);
+        }
+
+        /* Warn on any missing DT resource */
+        WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
+
         return mvebu_pinctrl_probe(pdev);
 }