aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging/brcm80211/include
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/staging/brcm80211/include')
-rw-r--r--drivers/staging/brcm80211/include/brcm_hw_ids.h59
-rw-r--r--drivers/staging/brcm80211/include/brcmu_utils.h301
-rw-r--r--drivers/staging/brcm80211/include/brcmu_wifi.h243
-rw-r--r--drivers/staging/brcm80211/include/chipcommon.h281
-rw-r--r--drivers/staging/brcm80211/include/defs.h112
-rw-r--r--drivers/staging/brcm80211/include/soc.h95
6 files changed, 1091 insertions, 0 deletions
diff --git a/drivers/staging/brcm80211/include/brcm_hw_ids.h b/drivers/staging/brcm80211/include/brcm_hw_ids.h
new file mode 100644
index 00000000000..5fb17d53c9b
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcm_hw_ids.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_HW_IDS_H_
18#define _BRCM_HW_IDS_H_
19
20#define BCM4325_D11DUAL_ID 0x431b
21#define BCM4325_D11G_ID 0x431c
22#define BCM4325_D11A_ID 0x431d
23
24#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
25#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
26#define BCM4329_D11NDUAL_ID 0x432e
27
28#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
29#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
30#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
31
32#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
33#define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
34
35#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
36
37#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
38#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
39
40#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
41
42/* Chip IDs */
43#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
44#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
45
46#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
47#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
48#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
49#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
50#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
51#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
52#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
53#define BCM4325_CHIP_ID 0x4325 /* 4325 chipcommon chipid */
54#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
55#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
56#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
57#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
58
59#endif /* _BRCM_HW_IDS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_utils.h b/drivers/staging/brcm80211/include/brcmu_utils.h
new file mode 100644
index 00000000000..2d54cc5f4b1
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcmu_utils.h
@@ -0,0 +1,301 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMU_UTILS_H_
18#define _BRCMU_UTILS_H_
19
20#include <linux/skbuff.h>
21
22/* Buffer structure for collecting string-formatted data
23* using brcmu_bprintf() API.
24* Use brcmu_binit() to initialize before use
25*/
26
27struct brcmu_strbuf {
28 char *buf; /* pointer to current position in origbuf */
29 unsigned int size; /* current (residual) size in bytes */
30 char *origbuf; /* unmodified pointer to orignal buffer */
31 unsigned int origsize; /* unmodified orignal buffer size in bytes */
32};
33
34/*
35 * Spin at most 'us' microseconds while 'exp' is true.
36 * Caller should explicitly test 'exp' when this completes
37 * and take appropriate error action if 'exp' is still true.
38 */
39#define SPINWAIT(exp, us) { \
40 uint countdown = (us) + 9; \
41 while ((exp) && (countdown >= 10)) {\
42 udelay(10); \
43 countdown -= 10; \
44 } \
45}
46
47/* osl multi-precedence packet queue */
48#ifndef PKTQ_LEN_DEFAULT
49#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
50#endif
51#ifndef PKTQ_MAX_PREC
52#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
53#endif
54
55struct pktq_prec {
56 struct sk_buff *head; /* first packet to dequeue */
57 struct sk_buff *tail; /* last packet to dequeue */
58 u16 len; /* number of queued packets */
59 u16 max; /* maximum number of queued packets */
60};
61
62/* multi-priority pkt queue */
63struct pktq {
64 u16 num_prec; /* number of precedences in use */
65 u16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
66 u16 max; /* total max packets */
67 u16 len; /* total number of packets */
68 /*
69 * q array must be last since # of elements can be either
70 * PKTQ_MAX_PREC or 1
71 */
72 struct pktq_prec q[PKTQ_MAX_PREC];
73};
74
75/* fn(pkt, arg). return true if pkt belongs to if */
76typedef bool(*ifpkt_cb_t) (struct sk_buff *, void *);
77
78/* operations on a specific precedence in packet queue */
79
80#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
81#define pktq_plen(pq, prec) ((pq)->q[prec].len)
82#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
83#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
84#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
85
86#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
87#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
88
89extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
90 struct sk_buff *p);
91extern struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
92 struct sk_buff *p);
93extern struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
94extern struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
95
96/* packet primitives */
97extern struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
98extern void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
99
100/* Empty the queue at particular precedence level */
101extern void brcmu_pktq_pflush(struct pktq *pq, int prec,
102 bool dir, ifpkt_cb_t fn, void *arg);
103
104/* operations on a set of precedences in packet queue */
105
106extern int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
107extern struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
108 int *prec_out);
109
110/* operations on packet queue as a whole */
111
112#define pktq_len(pq) ((int)(pq)->len)
113#define pktq_max(pq) ((int)(pq)->max)
114#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
115#define pktq_full(pq) ((pq)->len >= (pq)->max)
116#define pktq_empty(pq) ((pq)->len == 0)
117
118/* operations for single precedence queues */
119#define pktenq(pq, p) brcmu_pktq_penq(((struct pktq *)pq), 0, (p))
120#define pktenq_head(pq, p)\
121 brcmu_pktq_penq_head(((struct pktq *)pq), 0, (p))
122#define pktdeq(pq) brcmu_pktq_pdeq(((struct pktq *)pq), 0)
123#define pktdeq_tail(pq) brcmu_pktq_pdeq_tail(((struct pktq *)pq), 0)
124#define pktqinit(pq, len) brcmu_pktq_init(((struct pktq *)pq), 1, len)
125
126extern void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
127/* prec_out may be NULL if caller is not interested in return value */
128extern struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
129extern void brcmu_pktq_flush(struct pktq *pq, bool dir,
130 ifpkt_cb_t fn, void *arg);
131
132/* externs */
133/* packet */
134extern uint brcmu_pktfrombuf(struct sk_buff *p,
135 uint offset, int len, unsigned char *buf);
136extern uint brcmu_pkttotlen(struct sk_buff *p);
137
138/* ethernet address */
139extern int brcmu_ether_atoe(char *p, u8 *ea);
140
141/* ip address */
142struct ipv4_addr;
143
144#ifdef BCMDBG
145extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
146#else
147#define brcmu_prpkt(a, b)
148#endif /* BCMDBG */
149
150/* Support for sharing code across in-driver iovar implementations.
151 * The intent is that a driver use this structure to map iovar names
152 * to its (private) iovar identifiers, and the lookup function to
153 * find the entry. Macros are provided to map ids and get/set actions
154 * into a single number space for a switch statement.
155 */
156
157/* iovar structure */
158struct brcmu_iovar {
159 const char *name; /* name for lookup and display */
160 u16 varid; /* id for switch */
161 u16 flags; /* driver-specific flag bits */
162 u16 type; /* base type of argument */
163 u16 minlen; /* min length for buffer vars */
164};
165
166/* varid definitions are per-driver, may use these get/set bits */
167
168/* IOVar action bits for id mapping */
169#define IOV_GET 0 /* Get an iovar */
170#define IOV_SET 1 /* Set an iovar */
171
172/* Varid to actionid mapping */
173#define IOV_GVAL(id) ((id)*2)
174#define IOV_SVAL(id) (((id)*2)+IOV_SET)
175#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
176#define IOV_ID(actionid) (actionid >> 1)
177
178extern const struct
179brcmu_iovar *brcmu_iovar_lookup(const struct brcmu_iovar *table,
180 const char *name);
181extern int brcmu_iovar_lencheck(const struct brcmu_iovar *table, void *arg,
182 int len, bool set);
183
184/* Base type definitions */
185#define IOVT_VOID 0 /* no value (implictly set only) */
186#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
187#define IOVT_INT8 2 /* integer values are range-checked */
188#define IOVT_UINT8 3 /* unsigned int 8 bits */
189#define IOVT_INT16 4 /* int 16 bits */
190#define IOVT_UINT16 5 /* unsigned int 16 bits */
191#define IOVT_INT32 6 /* int 32 bits */
192#define IOVT_UINT32 7 /* unsigned int 32 bits */
193#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
194#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
195
196/* ** driver/apps-shared section ** */
197
198#define BCME_STRLEN 64 /* Max string length for BCM errors */
199
200#ifndef ABS
201#define ABS(a) (((a) < 0) ? -(a) : (a))
202#endif /* ABS */
203
204#define CEIL(x, y) (((x) + ((y)-1)) / (y))
205#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
206
207/* map physical to virtual I/O */
208#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), \
209 (unsigned long)(size))
210
211/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
212#define PKTBUFSZ 2048
213
214#define OSL_SYSUPTIME() ((u32)jiffies * (1000 / HZ))
215
216#ifndef setbit
217#ifndef NBBY /* the BSD family defines NBBY */
218#define NBBY 8 /* 8 bits per byte */
219#endif /* #ifndef NBBY */
220#define setbit(a, i) (((u8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
221#define clrbit(a, i) (((u8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
222#define isset(a, i) (((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
223#define isclr(a, i) ((((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
224#endif /* setbit */
225
226#define NBITS(type) (sizeof(type) * 8)
227#define NBITVAL(nbits) (1 << (nbits))
228#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
229#define NBITMASK(nbits) MAXBITVAL(nbits)
230#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
231
232/* basic mux operation - can be optimized on several architectures */
233#define MUX(pred, true, false) ((pred) ? (true) : (false))
234
235/* modulo inc/dec - assumes x E [0, bound - 1] */
236#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
237#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
238
239/* modulo inc/dec, bound = 2^k */
240#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
241#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
242
243/* modulo add/sub - assumes x, y E [0, bound - 1] */
244#define MODADD(x, y, bound) \
245 MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
246#define MODSUB(x, y, bound) \
247 MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
248
249/* module add/sub, bound = 2^k */
250#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
251#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
252
253/* crc defines */
254#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
255#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
256#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
257#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
258
259/* brcmu_format_flags() bit description structure */
260struct brcmu_bit_desc {
261 u32 bit;
262 const char *name;
263};
264
265/* tag_ID/length/value_buffer tuple */
266struct brcmu_tlv {
267 u8 id;
268 u8 len;
269 u8 data[1];
270};
271
272#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
273
274/* externs */
275/* crc */
276extern u8 brcmu_crc8(u8 *p, uint nbytes, u8 crc);
277
278/* format/print */
279#if defined(BCMDBG)
280extern int brcmu_format_flags(const struct brcmu_bit_desc *bd, u32 flags,
281 char *buf, int len);
282extern int brcmu_format_hex(char *str, const void *bytes, int len);
283#endif
284
285extern char *brcmu_chipname(uint chipid, char *buf, uint len);
286
287extern struct brcmu_tlv *brcmu_parse_tlvs(void *buf, int buflen,
288 uint key);
289
290/* power conversion */
291extern u16 brcmu_qdbm_to_mw(u8 qdbm);
292extern u8 brcmu_mw_to_qdbm(u16 mw);
293
294extern void brcmu_binit(struct brcmu_strbuf *b, char *buf, uint size);
295extern int brcmu_bprintf(struct brcmu_strbuf *b, const char *fmt, ...);
296
297extern uint brcmu_mkiovar(char *name, char *data, uint datalen,
298 char *buf, uint len);
299extern uint brcmu_bitcount(u8 *bitmap, uint bytelength);
300
301#endif /* _BRCMU_UTILS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_wifi.h b/drivers/staging/brcm80211/include/brcmu_wifi.h
new file mode 100644
index 00000000000..fde592bd917
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcmu_wifi.h
@@ -0,0 +1,243 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCMU_WIFI_H_
18#define _BRCMU_WIFI_H_
19
20#include <linux/if_ether.h> /* for ETH_ALEN */
21#include <linux/ieee80211.h> /* for WLAN_PMKID_LEN */
22
23/* A chanspec holds the channel number, band, bandwidth and control sideband */
24typedef u16 chanspec_t;
25
26/* channel defines */
27#define CH_UPPER_SB 0x01
28#define CH_LOWER_SB 0x02
29#define CH_EWA_VALID 0x04
30#define CH_20MHZ_APART 4
31#define CH_10MHZ_APART 2
32#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
33#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
34#define BRCM_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL /* legacy define */
35#define MAXCHANNEL 224 /* max # supported channels. The max channel no is 216,
36 * this is that + 1 rounded up to a multiple of NBBY (8).
37 * DO NOT MAKE it > 255: channels are u8's all over
38 */
39
40#define WL_CHANSPEC_CHAN_MASK 0x00ff
41#define WL_CHANSPEC_CHAN_SHIFT 0
42
43#define WL_CHANSPEC_CTL_SB_MASK 0x0300
44#define WL_CHANSPEC_CTL_SB_SHIFT 8
45#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
46#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
47#define WL_CHANSPEC_CTL_SB_NONE 0x0300
48
49#define WL_CHANSPEC_BW_MASK 0x0C00
50#define WL_CHANSPEC_BW_SHIFT 10
51#define WL_CHANSPEC_BW_10 0x0400
52#define WL_CHANSPEC_BW_20 0x0800
53#define WL_CHANSPEC_BW_40 0x0C00
54
55#define WL_CHANSPEC_BAND_MASK 0xf000
56#define WL_CHANSPEC_BAND_SHIFT 12
57#define WL_CHANSPEC_BAND_5G 0x1000
58#define WL_CHANSPEC_BAND_2G 0x2000
59#define INVCHANSPEC 255
60
61/* used to calculate the chan_freq = chan_factor * 500Mhz + 5 * chan_number */
62#define WF_CHAN_FACTOR_2_4_G 4814 /* 2.4 GHz band, 2407 MHz */
63#define WF_CHAN_FACTOR_5_G 10000 /* 5 GHz band, 5000 MHz */
64#define WF_CHAN_FACTOR_4_G 8000 /* 4.9 GHz band for Japan */
65
66/* channel defines */
67#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
68#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
69 ((channel) + CH_10MHZ_APART) : 0)
70#define CHSPEC_BANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : \
71 BAND_2G_INDEX)
72#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
73 WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
74 WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
75#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
76 ((channel) + CH_20MHZ_APART) : 0)
77#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
78 ((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
79 ((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
80 WL_CHANSPEC_BAND_5G))
81#define CHSPEC_CHANNEL(chspec) ((u8)((chspec) & WL_CHANSPEC_CHAN_MASK))
82#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
83
84#ifdef WL11N_20MHZONLY
85
86#define CHSPEC_CTL_SB(chspec) WL_CHANSPEC_CTL_SB_NONE
87#define CHSPEC_BW(chspec) WL_CHANSPEC_BW_20
88#define CHSPEC_IS10(chspec) 0
89#define CHSPEC_IS20(chspec) 1
90#ifndef CHSPEC_IS40
91#define CHSPEC_IS40(chspec) 0
92#endif
93
94#else /* !WL11N_20MHZONLY */
95
96#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
97#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
98#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
99#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
100#ifndef CHSPEC_IS40
101#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
102#endif
103
104#endif /* !WL11N_20MHZONLY */
105
106#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
107#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
108#define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
109#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
110#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
111#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
112 (LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
113 (UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
114#define CHSPEC2BAND(chspec) (CHSPEC_IS5G(chspec) ? BRCM_BAND_5G : BRCM_BAND_2G)
115
116#define CHANSPEC_STR_LEN 8
117
118/* defined rate in 500kbps */
119#define BRCM_MAXRATE 108 /* in 500kbps units */
120#define BRCM_RATE_1M 2 /* in 500kbps units */
121#define BRCM_RATE_2M 4 /* in 500kbps units */
122#define BRCM_RATE_5M5 11 /* in 500kbps units */
123#define BRCM_RATE_11M 22 /* in 500kbps units */
124#define BRCM_RATE_6M 12 /* in 500kbps units */
125#define BRCM_RATE_9M 18 /* in 500kbps units */
126#define BRCM_RATE_12M 24 /* in 500kbps units */
127#define BRCM_RATE_18M 36 /* in 500kbps units */
128#define BRCM_RATE_24M 48 /* in 500kbps units */
129#define BRCM_RATE_36M 72 /* in 500kbps units */
130#define BRCM_RATE_48M 96 /* in 500kbps units */
131#define BRCM_RATE_54M 108 /* in 500kbps units */
132
133#define BRCM_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
134
135#define MCSSET_LEN 16
136
137#define AC_BITMAP_TST(ab, ac) (((ab) & (1 << (ac))) != 0)
138
139/*
140 * Verify the chanspec is using a legal set of parameters, i.e. that the
141 * chanspec specified a band, bw, ctl_sb and channel and that the
142 * combination could be legal given any set of circumstances.
143 * RETURNS: true is the chanspec is malformed, false if it looks good.
144 */
145extern bool brcmu_chspec_malformed(chanspec_t chanspec);
146
147/*
148 * This function returns the channel number that control traffic is being sent on, for legacy
149 * channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
150 * sideband depending on the chanspec selected
151 */
152extern u8 brcmu_chspec_ctlchan(chanspec_t chspec);
153
154/*
155 * Return the channel number for a given frequency and base frequency.
156 * The returned channel number is relative to the given base frequency.
157 * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
158 * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
159 *
160 * Frequency is specified in MHz.
161 * The base frequency is specified as (start_factor * 500 kHz).
162 * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
163 * 2.4 GHz and 5 GHz bands.
164 *
165 * The returned channel will be in the range [1, 14] in the 2.4 GHz band
166 * and [0, 200] otherwise.
167 * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
168 * frequency is not a 2.4 GHz channel, or if the frequency is not and even
169 * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
170 *
171 * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
172 */
173extern int brcmu_mhz2channel(uint freq, uint start_factor);
174
175/* Enumerate crypto algorithms */
176#define CRYPTO_ALGO_OFF 0
177#define CRYPTO_ALGO_WEP1 1
178#define CRYPTO_ALGO_TKIP 2
179#define CRYPTO_ALGO_WEP128 3
180#define CRYPTO_ALGO_AES_CCM 4
181#define CRYPTO_ALGO_AES_RESERVED1 5
182#define CRYPTO_ALGO_AES_RESERVED2 6
183#define CRYPTO_ALGO_NALG 7
184
185/* wireless security bitvec */
186#define WEP_ENABLED 0x0001
187#define TKIP_ENABLED 0x0002
188#define AES_ENABLED 0x0004
189#define WSEC_SWFLAG 0x0008
190#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
191
192/* WPA authentication mode bitvec */
193#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
194#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
195#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
196#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
197#define WPA_AUTH_RESERVED1 0x0008
198#define WPA_AUTH_RESERVED2 0x0010
199 /* #define WPA_AUTH_8021X 0x0020 *//* 802.1x, reserved */
200#define WPA2_AUTH_RESERVED1 0x0020
201#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
202#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
203#define WPA2_AUTH_RESERVED3 0x0200
204#define WPA2_AUTH_RESERVED4 0x0400
205#define WPA2_AUTH_RESERVED5 0x0800
206
207/* pmkid */
208#define MAXPMKID 16
209
210#define DOT11_DEFAULT_RTS_LEN 2347
211#define DOT11_DEFAULT_FRAG_LEN 2346
212
213#define DOT11_ICV_AES_LEN 8
214#define DOT11_QOS_LEN 2
215#define DOT11_IV_MAX_LEN 8
216#define DOT11_A4_HDR_LEN 30
217
218#define HT_CAP_RX_STBC_NO 0x0
219#define HT_CAP_RX_STBC_ONE_STREAM 0x1
220
221typedef struct _pmkid {
222 u8 BSSID[ETH_ALEN];
223 u8 PMKID[WLAN_PMKID_LEN];
224} pmkid_t;
225
226typedef struct _pmkid_list {
227 u32 npmkid;
228 pmkid_t pmkid[1];
229} pmkid_list_t;
230
231typedef struct _pmkid_cand {
232 u8 BSSID[ETH_ALEN];
233 u8 preauth;
234} pmkid_cand_t;
235
236typedef struct _pmkid_cand_list {
237 u32 npmkid_cand;
238 pmkid_cand_t pmkid_cand[1];
239} pmkid_cand_list_t;
240
241typedef u8 ac_bitmap_t;
242
243#endif /* _BRCMU_WIFI_H_ */
diff --git a/drivers/staging/brcm80211/include/chipcommon.h b/drivers/staging/brcm80211/include/chipcommon.h
new file mode 100644
index 00000000000..296582aced6
--- /dev/null
+++ b/drivers/staging/brcm80211/include/chipcommon.h
@@ -0,0 +1,281 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _SBCHIPC_H
18#define _SBCHIPC_H
19
20#include "defs.h" /* for PAD macro */
21
22typedef volatile struct {
23 u32 chipid; /* 0x0 */
24 u32 capabilities;
25 u32 corecontrol; /* corerev >= 1 */
26 u32 bist;
27
28 /* OTP */
29 u32 otpstatus; /* 0x10, corerev >= 10 */
30 u32 otpcontrol;
31 u32 otpprog;
32 u32 otplayout; /* corerev >= 23 */
33
34 /* Interrupt control */
35 u32 intstatus; /* 0x20 */
36 u32 intmask;
37
38 /* Chip specific regs */
39 u32 chipcontrol; /* 0x28, rev >= 11 */
40 u32 chipstatus; /* 0x2c, rev >= 11 */
41
42 /* Jtag Master */
43 u32 jtagcmd; /* 0x30, rev >= 10 */
44 u32 jtagir;
45 u32 jtagdr;
46 u32 jtagctrl;
47
48 /* serial flash interface registers */
49 u32 flashcontrol; /* 0x40 */
50 u32 flashaddress;
51 u32 flashdata;
52 u32 PAD[1];
53
54 /* Silicon backplane configuration broadcast control */
55 u32 broadcastaddress; /* 0x50 */
56 u32 broadcastdata;
57
58 /* gpio - cleared only by power-on-reset */
59 u32 gpiopullup; /* 0x58, corerev >= 20 */
60 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
61 u32 gpioin; /* 0x60 */
62 u32 gpioout; /* 0x64 */
63 u32 gpioouten; /* 0x68 */
64 u32 gpiocontrol; /* 0x6C */
65 u32 gpiointpolarity; /* 0x70 */
66 u32 gpiointmask; /* 0x74 */
67
68 /* GPIO events corerev >= 11 */
69 u32 gpioevent;
70 u32 gpioeventintmask;
71
72 /* Watchdog timer */
73 u32 watchdog; /* 0x80 */
74
75 /* GPIO events corerev >= 11 */
76 u32 gpioeventintpolarity;
77
78 /* GPIO based LED powersave registers corerev >= 16 */
79 u32 gpiotimerval; /* 0x88 */
80 u32 gpiotimeroutmask;
81
82 /* clock control */
83 u32 clockcontrol_n; /* 0x90 */
84 u32 clockcontrol_sb; /* aka m0 */
85 u32 clockcontrol_pci; /* aka m1 */
86 u32 clockcontrol_m2; /* mii/uart/mipsref */
87 u32 clockcontrol_m3; /* cpu */
88 u32 clkdiv; /* corerev >= 3 */
89 u32 gpiodebugsel; /* corerev >= 28 */
90 u32 capabilities_ext; /* 0xac */
91
92 /* pll delay registers (corerev >= 4) */
93 u32 pll_on_delay; /* 0xb0 */
94 u32 fref_sel_delay;
95 u32 slow_clk_ctl; /* 5 < corerev < 10 */
96 u32 PAD;
97
98 /* Instaclock registers (corerev >= 10) */
99 u32 system_clk_ctl; /* 0xc0 */
100 u32 clkstatestretch;
101 u32 PAD[2];
102
103 /* Indirect backplane access (corerev >= 22) */
104 u32 bp_addrlow; /* 0xd0 */
105 u32 bp_addrhigh;
106 u32 bp_data;
107 u32 PAD;
108 u32 bp_indaccess;
109 u32 PAD[3];
110
111 /* More clock dividers (corerev >= 32) */
112 u32 clkdiv2;
113 u32 PAD[2];
114
115 /* In AI chips, pointer to erom */
116 u32 eromptr; /* 0xfc */
117
118 /* ExtBus control registers (corerev >= 3) */
119 u32 pcmcia_config; /* 0x100 */
120 u32 pcmcia_memwait;
121 u32 pcmcia_attrwait;
122 u32 pcmcia_iowait;
123 u32 ide_config;
124 u32 ide_memwait;
125 u32 ide_attrwait;
126 u32 ide_iowait;
127 u32 prog_config;
128 u32 prog_waitcount;
129 u32 flash_config;
130 u32 flash_waitcount;
131 u32 SECI_config; /* 0x130 SECI configuration */
132 u32 PAD[3];
133
134 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
135 u32 eci_output; /* 0x140 */
136 u32 eci_control;
137 u32 eci_inputlo;
138 u32 eci_inputmi;
139 u32 eci_inputhi;
140 u32 eci_inputintpolaritylo;
141 u32 eci_inputintpolaritymi;
142 u32 eci_inputintpolarityhi;
143 u32 eci_intmasklo;
144 u32 eci_intmaskmi;
145 u32 eci_intmaskhi;
146 u32 eci_eventlo;
147 u32 eci_eventmi;
148 u32 eci_eventhi;
149 u32 eci_eventmasklo;
150 u32 eci_eventmaskmi;
151 u32 eci_eventmaskhi;
152 u32 PAD[3];
153
154 /* SROM interface (corerev >= 32) */
155 u32 sromcontrol; /* 0x190 */
156 u32 sromaddress;
157 u32 sromdata;
158 u32 PAD[17];
159
160 /* Clock control and hardware workarounds (corerev >= 20) */
161 u32 clk_ctl_st; /* 0x1e0 */
162 u32 hw_war;
163 u32 PAD[70];
164
165 /* UARTs */
166 u8 uart0data; /* 0x300 */
167 u8 uart0imr;
168 u8 uart0fcr;
169 u8 uart0lcr;
170 u8 uart0mcr;
171 u8 uart0lsr;
172 u8 uart0msr;
173 u8 uart0scratch;
174 u8 PAD[248]; /* corerev >= 1 */
175
176 u8 uart1data; /* 0x400 */
177 u8 uart1imr;
178 u8 uart1fcr;
179 u8 uart1lcr;
180 u8 uart1mcr;
181 u8 uart1lsr;
182 u8 uart1msr;
183 u8 uart1scratch;
184 u32 PAD[126];
185
186 /* PMU registers (corerev >= 20) */
187 u32 pmucontrol; /* 0x600 */
188 u32 pmucapabilities;
189 u32 pmustatus;
190 u32 res_state;
191 u32 res_pending;
192 u32 pmutimer;
193 u32 min_res_mask;
194 u32 max_res_mask;
195 u32 res_table_sel;
196 u32 res_dep_mask;
197 u32 res_updn_timer;
198 u32 res_timer;
199 u32 clkstretch;
200 u32 pmuwatchdog;
201 u32 gpiosel; /* 0x638, rev >= 1 */
202 u32 gpioenable; /* 0x63c, rev >= 1 */
203 u32 res_req_timer_sel;
204 u32 res_req_timer;
205 u32 res_req_mask;
206 u32 PAD;
207 u32 chipcontrol_addr; /* 0x650 */
208 u32 chipcontrol_data; /* 0x654 */
209 u32 regcontrol_addr;
210 u32 regcontrol_data;
211 u32 pllcontrol_addr;
212 u32 pllcontrol_data;
213 u32 pmustrapopt; /* 0x668, corerev >= 28 */
214 u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
215 u32 PAD[100];
216 u16 sromotp[768];
217} chipcregs_t;
218
219/* chipid */
220#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
221#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
222#define CID_REV_SHIFT 16 /* Chip Revision shift */
223#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
224#define CID_PKG_SHIFT 20 /* Package Option shift */
225#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
226#define CID_CC_SHIFT 24
227#define CID_TYPE_MASK 0xf0000000 /* Chip Type */
228#define CID_TYPE_SHIFT 28
229
230/* capabilities */
231#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
232#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
233#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
234#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
235#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
236#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
237#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
238#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
239#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
240#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
241#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
242#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
243#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
244#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
245#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
246#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
247#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
248#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
249#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
250#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
251#define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */
252
253#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
254#define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */
255
256/* pmucapabilities */
257#define PCAP_REV_MASK 0x000000ff
258#define PCAP_RC_MASK 0x00001f00
259#define PCAP_RC_SHIFT 8
260#define PCAP_TC_MASK 0x0001e000
261#define PCAP_TC_SHIFT 13
262#define PCAP_PC_MASK 0x001e0000
263#define PCAP_PC_SHIFT 17
264#define PCAP_VC_MASK 0x01e00000
265#define PCAP_VC_SHIFT 21
266#define PCAP_CC_MASK 0x1e000000
267#define PCAP_CC_SHIFT 25
268#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
269#define PCAP5_PC_SHIFT 17
270#define PCAP5_VC_MASK 0x07c00000
271#define PCAP5_VC_SHIFT 22
272#define PCAP5_CC_MASK 0xf8000000
273#define PCAP5_CC_SHIFT 27
274
275/*
276* Maximum delay for the PMU state transition in us.
277* This is an upper bound intended for spinwaits etc.
278*/
279#define PMU_MAX_TRANSITION_DLY 15000
280
281#endif /* _SBCHIPC_H */
diff --git a/drivers/staging/brcm80211/include/defs.h b/drivers/staging/brcm80211/include/defs.h
new file mode 100644
index 00000000000..8b3e17dec15
--- /dev/null
+++ b/drivers/staging/brcm80211/include/defs.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_DEFS_H_
18#define _BRCM_DEFS_H_
19
20#include <linux/types.h>
21
22#define SI_BUS 0
23#define PCI_BUS 1
24#define PCMCIA_BUS 2
25#define SDIO_BUS 3
26#define JTAG_BUS 4
27#define USB_BUS 5
28#define SPI_BUS 6
29
30#ifndef OFF
31#define OFF 0
32#endif
33
34#ifndef ON
35#define ON 1 /* ON = 1 */
36#endif
37
38#define AUTO (-1) /* Auto = -1 */
39
40/*
41 * Priority definitions according 802.1D
42 */
43#define PRIO_8021D_NONE 2
44#define PRIO_8021D_BK 1
45#define PRIO_8021D_BE 0
46#define PRIO_8021D_EE 3
47#define PRIO_8021D_CL 4
48#define PRIO_8021D_VI 5
49#define PRIO_8021D_VO 6
50#define PRIO_8021D_NC 7
51
52#define MAXPRIO 7
53#define NUMPRIO (MAXPRIO + 1)
54
55#define WL_NUMRATES 16 /* max # of rates in a rateset */
56
57typedef struct wl_rateset {
58 u32 count; /* # rates in this set */
59 u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
60} wl_rateset_t;
61
62#define BRCM_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */
63
64#define BRCM_SET_CHANNEL 30
65#define BRCM_SET_SRL 32
66#define BRCM_SET_LRL 34
67
68#define BRCM_SET_RATESET 72
69#define BRCM_SET_BCNPRD 76
70#define BRCM_GET_CURR_RATESET 114 /* current rateset */
71#define BRCM_GET_PHYLIST 180
72
73/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
74#define WL_RADIO_SW_DISABLE (1<<0)
75#define WL_RADIO_HW_DISABLE (1<<1)
76#define WL_RADIO_MPC_DISABLE (1<<2)
77#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any channel */
78
79/* Override bit for SET_TXPWR. if set, ignore other level limits */
80#define WL_TXPWR_OVERRIDE (1U<<31)
81
82/* band types */
83#define BRCM_BAND_AUTO 0 /* auto-select */
84#define BRCM_BAND_5G 1 /* 5 Ghz */
85#define BRCM_BAND_2G 2 /* 2.4 Ghz */
86#define BRCM_BAND_ALL 3 /* all bands */
87
88/* Values for PM */
89#define PM_OFF 0
90#define PM_MAX 1
91
92/* Message levels */
93#define LOG_ERROR_VAL 0x00000001
94#define LOG_TRACE_VAL 0x00000002
95
96#define PM_OFF 0
97#define PM_MAX 1
98#define PM_FAST 2
99
100/*
101 * Sonics Configuration Space Registers.
102 */
103#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
104
105/* cpp contortions to concatenate w/arg prescan */
106#ifndef PAD
107#define _PADLINE(line) pad ## line
108#define _XSTR(line) _PADLINE(line)
109#define PAD _XSTR(__LINE__)
110#endif
111
112#endif /* _BRCM_DEFS_H_ */
diff --git a/drivers/staging/brcm80211/include/soc.h b/drivers/staging/brcm80211/include/soc.h
new file mode 100644
index 00000000000..6e5a705c493
--- /dev/null
+++ b/drivers/staging/brcm80211/include/soc.h
@@ -0,0 +1,95 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SOC_H
18#define _BRCM_SOC_H
19
20#ifdef SI_ENUM_BASE_VARIABLE
21#define SI_ENUM_BASE (sii->pub.si_enum_base)
22#else
23#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
24#endif /* SI_ENUM_BASE_VARIABLE */
25
26/* core codes */
27#define NODEV_CORE_ID 0x700 /* Invalid coreid */
28#define CC_CORE_ID 0x800 /* chipcommon core */
29#define ILINE20_CORE_ID 0x801 /* iline20 core */
30#define SRAM_CORE_ID 0x802 /* sram core */
31#define SDRAM_CORE_ID 0x803 /* sdram core */
32#define PCI_CORE_ID 0x804 /* pci core */
33#define MIPS_CORE_ID 0x805 /* mips core */
34#define ENET_CORE_ID 0x806 /* enet mac core */
35#define CODEC_CORE_ID 0x807 /* v90 codec core */
36#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
37#define ADSL_CORE_ID 0x809 /* ADSL core */
38#define ILINE100_CORE_ID 0x80a /* iline100 core */
39#define IPSEC_CORE_ID 0x80b /* ipsec core */
40#define UTOPIA_CORE_ID 0x80c /* utopia core */
41#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
42#define SOCRAM_CORE_ID 0x80e /* internal memory core */
43#define MEMC_CORE_ID 0x80f /* memc sdram core */
44#define OFDM_CORE_ID 0x810 /* OFDM phy core */
45#define EXTIF_CORE_ID 0x811 /* external interface core */
46#define D11_CORE_ID 0x812 /* 802.11 MAC core */
47#define APHY_CORE_ID 0x813 /* 802.11a phy core */
48#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
49#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
50#define MIPS33_CORE_ID 0x816 /* mips3302 core */
51#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
52#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
53#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
54#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
55#define SDIOH_CORE_ID 0x81b /* sdio host core */
56#define ROBO_CORE_ID 0x81c /* roboswitch core */
57#define ATA100_CORE_ID 0x81d /* parallel ATA core */
58#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
59#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
60#define PCIE_CORE_ID 0x820 /* pci express core */
61#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
62#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
63#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
64#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
65#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
66#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
67#define PMU_CORE_ID 0x827 /* PMU core */
68#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
69#define SDIOD_CORE_ID 0x829 /* SDIO device core */
70#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
71#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
72#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
73#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
74#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
75#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
76#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
77#define SC_CORE_ID 0x831 /* shared common core */
78#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
79#define SPIH_CORE_ID 0x833 /* SPI host core */
80#define I2S_CORE_ID 0x834 /* I2S core */
81#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
82#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
83#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
84#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
85 * unused address ranges
86 */
87
88/* Common core control flags */
89#define SICF_BIST_EN 0x8000
90#define SICF_PME_EN 0x4000
91#define SICF_CORE_BITS 0x3ffc
92#define SICF_FGC 0x0002
93#define SICF_CLOCK_EN 0x0001
94
95#endif /* _BRCM_SOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-29 21:24:25 -0400