Added missing tegra files.HEADmaster

6 files changed, 1091 insertions, 0 deletions

diff --git a/drivers/staging/brcm80211/include/brcm_hw_ids.h b/drivers/staging/brcm80211/include/brcm_hw_ids.h
new file mode 100644
index 00000000000..5fb17d53c9b
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcm_hw_ids.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_HW_IDS_H_
+#define _BRCM_HW_IDS_H_
+
+#define BCM4325_D11DUAL_ID      0x431b
+#define BCM4325_D11G_ID         0x431c
+#define BCM4325_D11A_ID         0x431d
+
+#define BCM4329_D11N2G_ID       0x432f  /* 4329 802.11n 2.4G device */
+#define BCM4329_D11N5G_ID       0x4330  /* 4329 802.11n 5G device */
+#define BCM4329_D11NDUAL_ID     0x432e
+
+#define BCM4319_D11N_ID         0x4337  /* 4319 802.11n dualband device */
+#define BCM4319_D11N2G_ID       0x4338  /* 4319 802.11n 2.4G device */
+#define BCM4319_D11N5G_ID       0x4339  /* 4319 802.11n 5G device */
+
+#define BCM43224_D11N_ID        0x4353  /* 43224 802.11n dualband device */
+#define BCM43224_D11N_ID_VEN1   0x0576  /* Vendor specific 43224 802.11n db */
+
+#define BCM43225_D11N2G_ID      0x4357  /* 43225 802.11n 2.4GHz device */
+
+#define BCM43236_D11N_ID        0x4346  /* 43236 802.11n dualband device */
+#define BCM43236_D11N2G_ID      0x4347  /* 43236 802.11n 2.4GHz device */
+
+#define BCM4313_D11N2G_ID       0x4727  /* 4313 802.11n 2.4G device */
+
+/* Chip IDs */
+#define BCM4313_CHIP_ID         0x4313  /* 4313 chip id */
+#define BCM4319_CHIP_ID         0x4319  /* 4319 chip id */
+
+#define BCM43224_CHIP_ID        43224   /* 43224 chipcommon chipid */
+#define BCM43225_CHIP_ID        43225   /* 43225 chipcommon chipid */
+#define BCM43421_CHIP_ID        43421   /* 43421 chipcommon chipid */
+#define BCM43235_CHIP_ID        43235   /* 43235 chipcommon chipid */
+#define BCM43236_CHIP_ID        43236   /* 43236 chipcommon chipid */
+#define BCM43238_CHIP_ID        43238   /* 43238 chipcommon chipid */
+#define BCM4329_CHIP_ID         0x4329  /* 4329 chipcommon chipid */
+#define BCM4325_CHIP_ID         0x4325  /* 4325 chipcommon chipid */
+#define BCM4331_CHIP_ID         0x4331  /* 4331 chipcommon chipid */
+#define BCM4336_CHIP_ID         0x4336  /* 4336 chipcommon chipid */
+#define BCM4330_CHIP_ID         0x4330  /* 4330 chipcommon chipid */
+#define BCM6362_CHIP_ID         0x6362  /* 6362 chipcommon chipid */
+
+#endif                          /* _BRCM_HW_IDS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_utils.h b/drivers/staging/brcm80211/include/brcmu_utils.h
new file mode 100644
index 00000000000..2d54cc5f4b1
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcmu_utils.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCMU_UTILS_H_
+#define _BRCMU_UTILS_H_
+
+#include <linux/skbuff.h>
+
+/* Buffer structure for collecting string-formatted data
+* using brcmu_bprintf() API.
+* Use brcmu_binit() to initialize before use
+*/
+
+struct brcmu_strbuf {
+        char *buf;      /* pointer to current position in origbuf */
+        unsigned int size;      /* current (residual) size in bytes */
+        char *origbuf;  /* unmodified pointer to orignal buffer */
+        unsigned int origsize;  /* unmodified orignal buffer size in bytes */
+};
+
+/*
+ * Spin at most 'us' microseconds while 'exp' is true.
+ * Caller should explicitly test 'exp' when this completes
+ * and take appropriate error action if 'exp' is still true.
+ */
+#define SPINWAIT(exp, us) { \
+        uint countdown = (us) + 9; \
+        while ((exp) && (countdown >= 10)) {\
+                udelay(10); \
+                countdown -= 10; \
+        } \
+}
+
+/* osl multi-precedence packet queue */
+#ifndef PKTQ_LEN_DEFAULT
+#define PKTQ_LEN_DEFAULT        128     /* Max 128 packets */
+#endif
+#ifndef PKTQ_MAX_PREC
+#define PKTQ_MAX_PREC           16      /* Maximum precedence levels */
+#endif
+
+struct pktq_prec {
+        struct sk_buff *head;   /* first packet to dequeue */
+        struct sk_buff *tail;   /* last packet to dequeue */
+        u16 len;                /* number of queued packets */
+        u16 max;                /* maximum number of queued packets */
+};
+
+/* multi-priority pkt queue */
+struct pktq {
+        u16 num_prec;   /* number of precedences in use */
+        u16 hi_prec;    /* rapid dequeue hint (>= highest non-empty prec) */
+        u16 max;        /* total max packets */
+        u16 len;        /* total number of packets */
+        /*
+         * q array must be last since # of elements can be either
+         * PKTQ_MAX_PREC or 1
+         */
+        struct pktq_prec q[PKTQ_MAX_PREC];
+};
+
+/* fn(pkt, arg).  return true if pkt belongs to if */
+typedef bool(*ifpkt_cb_t) (struct sk_buff *, void *);
+
+/* operations on a specific precedence in packet queue */
+
+#define pktq_psetmax(pq, prec, _max)    ((pq)->q[prec].max = (_max))
+#define pktq_plen(pq, prec)             ((pq)->q[prec].len)
+#define pktq_pavail(pq, prec)           ((pq)->q[prec].max - (pq)->q[prec].len)
+#define pktq_pfull(pq, prec)            ((pq)->q[prec].len >= (pq)->q[prec].max)
+#define pktq_pempty(pq, prec)           ((pq)->q[prec].len == 0)
+
+#define pktq_ppeek(pq, prec)            ((pq)->q[prec].head)
+#define pktq_ppeek_tail(pq, prec)       ((pq)->q[prec].tail)
+
+extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
+                                 struct sk_buff *p);
+extern struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
+                                      struct sk_buff *p);
+extern struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
+extern struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
+
+/* packet primitives */
+extern struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
+extern void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
+
+/* Empty the queue at particular precedence level */
+extern void brcmu_pktq_pflush(struct pktq *pq, int prec,
+        bool dir, ifpkt_cb_t fn, void *arg);
+
+/* operations on a set of precedences in packet queue */
+
+extern int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
+extern struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
+        int *prec_out);
+
+/* operations on packet queue as a whole */
+
+#define pktq_len(pq)                    ((int)(pq)->len)
+#define pktq_max(pq)                    ((int)(pq)->max)
+#define pktq_avail(pq)                  ((int)((pq)->max - (pq)->len))
+#define pktq_full(pq)                   ((pq)->len >= (pq)->max)
+#define pktq_empty(pq)                  ((pq)->len == 0)
+
+/* operations for single precedence queues */
+#define pktenq(pq, p)           brcmu_pktq_penq(((struct pktq *)pq), 0, (p))
+#define pktenq_head(pq, p)\
+        brcmu_pktq_penq_head(((struct pktq *)pq), 0, (p))
+#define pktdeq(pq)              brcmu_pktq_pdeq(((struct pktq *)pq), 0)
+#define pktdeq_tail(pq)         brcmu_pktq_pdeq_tail(((struct pktq *)pq), 0)
+#define pktqinit(pq, len)       brcmu_pktq_init(((struct pktq *)pq), 1, len)
+
+extern void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
+/* prec_out may be NULL if caller is not interested in return value */
+extern struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
+extern void brcmu_pktq_flush(struct pktq *pq, bool dir,
+        ifpkt_cb_t fn, void *arg);
+
+/* externs */
+/* packet */
+extern uint brcmu_pktfrombuf(struct sk_buff *p,
+        uint offset, int len, unsigned char *buf);
+extern uint brcmu_pkttotlen(struct sk_buff *p);
+
+/* ethernet address */
+extern int brcmu_ether_atoe(char *p, u8 *ea);
+
+/* ip address */
+struct ipv4_addr;
+
+#ifdef BCMDBG
+extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
+#else
+#define brcmu_prpkt(a, b)
+#endif                          /* BCMDBG */
+
+/* Support for sharing code across in-driver iovar implementations.
+ * The intent is that a driver use this structure to map iovar names
+ * to its (private) iovar identifiers, and the lookup function to
+ * find the entry.  Macros are provided to map ids and get/set actions
+ * into a single number space for a switch statement.
+ */
+
+/* iovar structure */
+struct brcmu_iovar {
+        const char *name;       /* name for lookup and display */
+        u16 varid;      /* id for switch */
+        u16 flags;      /* driver-specific flag bits */
+        u16 type;       /* base type of argument */
+        u16 minlen;     /* min length for buffer vars */
+};
+
+/* varid definitions are per-driver, may use these get/set bits */
+
+/* IOVar action bits for id mapping */
+#define IOV_GET 0               /* Get an iovar */
+#define IOV_SET 1               /* Set an iovar */
+
+/* Varid to actionid mapping */
+#define IOV_GVAL(id)            ((id)*2)
+#define IOV_SVAL(id)            (((id)*2)+IOV_SET)
+#define IOV_ISSET(actionid)     ((actionid & IOV_SET) == IOV_SET)
+#define IOV_ID(actionid)        (actionid >> 1)
+
+extern const struct
+brcmu_iovar *brcmu_iovar_lookup(const struct brcmu_iovar *table,
+                                const char *name);
+extern int brcmu_iovar_lencheck(const struct brcmu_iovar *table, void *arg,
+                                int len, bool set);
+
+/* Base type definitions */
+#define IOVT_VOID       0       /* no value (implictly set only) */
+#define IOVT_BOOL       1       /* any value ok (zero/nonzero) */
+#define IOVT_INT8       2       /* integer values are range-checked */
+#define IOVT_UINT8      3       /* unsigned int 8 bits */
+#define IOVT_INT16      4       /* int 16 bits */
+#define IOVT_UINT16     5       /* unsigned int 16 bits */
+#define IOVT_INT32      6       /* int 32 bits */
+#define IOVT_UINT32     7       /* unsigned int 32 bits */
+#define IOVT_BUFFER     8       /* buffer is size-checked as per minlen */
+#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
+
+/* ** driver/apps-shared section ** */
+
+#define BCME_STRLEN             64      /* Max string length for BCM errors */
+
+#ifndef ABS
+#define ABS(a)                  (((a) < 0) ? -(a) : (a))
+#endif                          /* ABS */
+
+#define CEIL(x, y)              (((x) + ((y)-1)) / (y))
+#define ISPOWEROF2(x)           ((((x)-1)&(x)) == 0)
+
+/* map physical to virtual I/O */
+#define REG_MAP(pa, size)       ioremap_nocache((unsigned long)(pa), \
+                                        (unsigned long)(size))
+
+/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
+#define PKTBUFSZ        2048
+
+#define OSL_SYSUPTIME()         ((u32)jiffies * (1000 / HZ))
+
+#ifndef setbit
+#ifndef NBBY                    /* the BSD family defines NBBY */
+#define NBBY    8               /* 8 bits per byte */
+#endif                          /* #ifndef NBBY */
+#define setbit(a, i)    (((u8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
+#define clrbit(a, i)    (((u8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
+#define isset(a, i)     (((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
+#define isclr(a, i)     ((((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
+#endif                          /* setbit */
+
+#define NBITS(type)     (sizeof(type) * 8)
+#define NBITVAL(nbits)  (1 << (nbits))
+#define MAXBITVAL(nbits)        ((1 << (nbits)) - 1)
+#define NBITMASK(nbits) MAXBITVAL(nbits)
+#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
+
+/* basic mux operation - can be optimized on several architectures */
+#define MUX(pred, true, false) ((pred) ? (true) : (false))
+
+/* modulo inc/dec - assumes x E [0, bound - 1] */
+#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
+#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
+
+/* modulo inc/dec, bound = 2^k */
+#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
+#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
+
+/* modulo add/sub - assumes x, y E [0, bound - 1] */
+#define MODADD(x, y, bound) \
+        MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
+#define MODSUB(x, y, bound) \
+        MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
+
+/* module add/sub, bound = 2^k */
+#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
+#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
+
+/* crc defines */
+#define CRC8_INIT_VALUE  0xff   /* Initial CRC8 checksum value */
+#define CRC8_GOOD_VALUE  0x9f   /* Good final CRC8 checksum value */
+#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
+#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
+
+/* brcmu_format_flags() bit description structure */
+struct brcmu_bit_desc {
+        u32 bit;
+        const char *name;
+};
+
+/* tag_ID/length/value_buffer tuple */
+struct brcmu_tlv {
+        u8 id;
+        u8 len;
+        u8 data[1];
+};
+
+#define ETHER_ADDR_STR_LEN      18      /* 18-bytes of Ethernet address buffer length */
+
+/* externs */
+/* crc */
+extern u8 brcmu_crc8(u8 *p, uint nbytes, u8 crc);
+
+/* format/print */
+#if defined(BCMDBG)
+extern int brcmu_format_flags(const struct brcmu_bit_desc *bd, u32 flags,
+                              char *buf, int len);
+extern int brcmu_format_hex(char *str, const void *bytes, int len);
+#endif
+
+extern char *brcmu_chipname(uint chipid, char *buf, uint len);
+
+extern struct brcmu_tlv *brcmu_parse_tlvs(void *buf, int buflen,
+                                          uint key);
+
+/* power conversion */
+extern u16 brcmu_qdbm_to_mw(u8 qdbm);
+extern u8 brcmu_mw_to_qdbm(u16 mw);
+
+extern void brcmu_binit(struct brcmu_strbuf *b, char *buf, uint size);
+extern int brcmu_bprintf(struct brcmu_strbuf *b, const char *fmt, ...);
+
+extern uint brcmu_mkiovar(char *name, char *data, uint datalen,
+                          char *buf, uint len);
+extern uint brcmu_bitcount(u8 *bitmap, uint bytelength);
+
+#endif                          /* _BRCMU_UTILS_H_ */
diff --git a/drivers/staging/brcm80211/include/brcmu_wifi.h b/drivers/staging/brcm80211/include/brcmu_wifi.h
new file mode 100644
index 00000000000..fde592bd917
--- /dev/null
+++ b/drivers/staging/brcm80211/include/brcmu_wifi.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCMU_WIFI_H_
+#define _BRCMU_WIFI_H_
+
+#include <linux/if_ether.h>             /* for ETH_ALEN */
+#include <linux/ieee80211.h>            /* for WLAN_PMKID_LEN */
+
+/* A chanspec holds the channel number, band, bandwidth and control sideband */
+typedef u16 chanspec_t;
+
+/* channel defines */
+#define CH_UPPER_SB                     0x01
+#define CH_LOWER_SB                     0x02
+#define CH_EWA_VALID                    0x04
+#define CH_20MHZ_APART                  4
+#define CH_10MHZ_APART                  2
+#define CH_5MHZ_APART                   1       /* 2G band channels are 5 Mhz apart */
+#define CH_MAX_2G_CHANNEL               14      /* Max channel in 2G band */
+#define BRCM_MAX_2G_CHANNEL     CH_MAX_2G_CHANNEL       /* legacy define */
+#define MAXCHANNEL              224     /* max # supported channels. The max channel no is 216,
+                                         * this is that + 1 rounded up to a multiple of NBBY (8).
+                                         * DO NOT MAKE it > 255: channels are u8's all over
+                                         */
+
+#define WL_CHANSPEC_CHAN_MASK           0x00ff
+#define WL_CHANSPEC_CHAN_SHIFT          0
+
+#define WL_CHANSPEC_CTL_SB_MASK         0x0300
+#define WL_CHANSPEC_CTL_SB_SHIFT             8
+#define WL_CHANSPEC_CTL_SB_LOWER        0x0100
+#define WL_CHANSPEC_CTL_SB_UPPER        0x0200
+#define WL_CHANSPEC_CTL_SB_NONE         0x0300
+
+#define WL_CHANSPEC_BW_MASK             0x0C00
+#define WL_CHANSPEC_BW_SHIFT                10
+#define WL_CHANSPEC_BW_10               0x0400
+#define WL_CHANSPEC_BW_20               0x0800
+#define WL_CHANSPEC_BW_40               0x0C00
+
+#define WL_CHANSPEC_BAND_MASK           0xf000
+#define WL_CHANSPEC_BAND_SHIFT          12
+#define WL_CHANSPEC_BAND_5G             0x1000
+#define WL_CHANSPEC_BAND_2G             0x2000
+#define INVCHANSPEC                     255
+
+/* used to calculate the chan_freq = chan_factor * 500Mhz + 5 * chan_number */
+#define WF_CHAN_FACTOR_2_4_G            4814    /* 2.4 GHz band, 2407 MHz */
+#define WF_CHAN_FACTOR_5_G              10000   /* 5   GHz band, 5000 MHz */
+#define WF_CHAN_FACTOR_4_G              8000    /* 4.9 GHz band for Japan */
+
+/* channel defines */
+#define LOWER_20_SB(channel)    (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
+#define UPPER_20_SB(channel)    (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
+                                ((channel) + CH_10MHZ_APART) : 0)
+#define CHSPEC_BANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : \
+                                                       BAND_2G_INDEX)
+#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
+                                WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
+                                WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
+#define NEXT_20MHZ_CHAN(channel)        (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
+                                        ((channel) + CH_20MHZ_APART) : 0)
+#define CH40MHZ_CHSPEC(channel, ctlsb)  (chanspec_t) \
+                                        ((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
+                                        ((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
+                                        WL_CHANSPEC_BAND_5G))
+#define CHSPEC_CHANNEL(chspec)  ((u8)((chspec) & WL_CHANSPEC_CHAN_MASK))
+#define CHSPEC_BAND(chspec)     ((chspec) & WL_CHANSPEC_BAND_MASK)
+
+#ifdef WL11N_20MHZONLY
+
+#define CHSPEC_CTL_SB(chspec)   WL_CHANSPEC_CTL_SB_NONE
+#define CHSPEC_BW(chspec)       WL_CHANSPEC_BW_20
+#define CHSPEC_IS10(chspec)     0
+#define CHSPEC_IS20(chspec)     1
+#ifndef CHSPEC_IS40
+#define CHSPEC_IS40(chspec)     0
+#endif
+
+#else                           /* !WL11N_20MHZONLY */
+
+#define CHSPEC_CTL_SB(chspec)   ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
+#define CHSPEC_BW(chspec)       ((chspec) & WL_CHANSPEC_BW_MASK)
+#define CHSPEC_IS10(chspec)     (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
+#define CHSPEC_IS20(chspec)     (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
+#ifndef CHSPEC_IS40
+#define CHSPEC_IS40(chspec)     (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
+#endif
+
+#endif                          /* !WL11N_20MHZONLY */
+
+#define CHSPEC_IS5G(chspec)     (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
+#define CHSPEC_IS2G(chspec)     (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
+#define CHSPEC_SB_NONE(chspec)  (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
+#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
+#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
+#define CHSPEC_CTL_CHAN(chspec)  ((CHSPEC_SB_LOWER(chspec)) ? \
+                                  (LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
+                                  (UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
+#define CHSPEC2BAND(chspec) (CHSPEC_IS5G(chspec) ? BRCM_BAND_5G : BRCM_BAND_2G)
+
+#define CHANSPEC_STR_LEN    8
+
+/* defined rate in 500kbps */
+#define BRCM_MAXRATE    108     /* in 500kbps units */
+#define BRCM_RATE_1M    2       /* in 500kbps units */
+#define BRCM_RATE_2M    4       /* in 500kbps units */
+#define BRCM_RATE_5M5   11      /* in 500kbps units */
+#define BRCM_RATE_11M   22      /* in 500kbps units */
+#define BRCM_RATE_6M    12      /* in 500kbps units */
+#define BRCM_RATE_9M    18      /* in 500kbps units */
+#define BRCM_RATE_12M   24      /* in 500kbps units */
+#define BRCM_RATE_18M   36      /* in 500kbps units */
+#define BRCM_RATE_24M   48      /* in 500kbps units */
+#define BRCM_RATE_36M   72      /* in 500kbps units */
+#define BRCM_RATE_48M   96      /* in 500kbps units */
+#define BRCM_RATE_54M   108     /* in 500kbps units */
+
+#define BRCM_2G_25MHZ_OFFSET            5       /* 2.4GHz band channel offset */
+
+#define MCSSET_LEN      16
+
+#define AC_BITMAP_TST(ab, ac)   (((ab) & (1 << (ac))) != 0)
+
+/*
+ * Verify the chanspec is using a legal set of parameters, i.e. that the
+ * chanspec specified a band, bw, ctl_sb and channel and that the
+ * combination could be legal given any set of circumstances.
+ * RETURNS: true is the chanspec is malformed, false if it looks good.
+ */
+extern bool brcmu_chspec_malformed(chanspec_t chanspec);
+
+/*
+ * This function returns the channel number that control traffic is being sent on, for legacy
+ * channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
+ * sideband depending on the chanspec selected
+ */
+extern u8 brcmu_chspec_ctlchan(chanspec_t chspec);
+
+/*
+ * Return the channel number for a given frequency and base frequency.
+ * The returned channel number is relative to the given base frequency.
+ * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
+ * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
+ *
+ * Frequency is specified in MHz.
+ * The base frequency is specified as (start_factor * 500 kHz).
+ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
+ * 2.4 GHz and 5 GHz bands.
+ *
+ * The returned channel will be in the range [1, 14] in the 2.4 GHz band
+ * and [0, 200] otherwise.
+ * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
+ * frequency is not a 2.4 GHz channel, or if the frequency is not and even
+ * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
+ *
+ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
+ */
+extern int brcmu_mhz2channel(uint freq, uint start_factor);
+
+/* Enumerate crypto algorithms */
+#define CRYPTO_ALGO_OFF                 0
+#define CRYPTO_ALGO_WEP1                1
+#define CRYPTO_ALGO_TKIP                2
+#define CRYPTO_ALGO_WEP128              3
+#define CRYPTO_ALGO_AES_CCM             4
+#define CRYPTO_ALGO_AES_RESERVED1       5
+#define CRYPTO_ALGO_AES_RESERVED2       6
+#define CRYPTO_ALGO_NALG                7
+
+/* wireless security bitvec */
+#define WEP_ENABLED             0x0001
+#define TKIP_ENABLED            0x0002
+#define AES_ENABLED             0x0004
+#define WSEC_SWFLAG             0x0008
+#define SES_OW_ENABLED          0x0040  /* to go into transition mode without setting wep */
+
+/* WPA authentication mode bitvec */
+#define WPA_AUTH_DISABLED       0x0000  /* Legacy (i.e., non-WPA) */
+#define WPA_AUTH_NONE           0x0001  /* none (IBSS) */
+#define WPA_AUTH_UNSPECIFIED    0x0002  /* over 802.1x */
+#define WPA_AUTH_PSK            0x0004  /* Pre-shared key */
+#define WPA_AUTH_RESERVED1      0x0008
+#define WPA_AUTH_RESERVED2      0x0010
+                                        /* #define WPA_AUTH_8021X 0x0020 *//* 802.1x, reserved */
+#define WPA2_AUTH_RESERVED1     0x0020
+#define WPA2_AUTH_UNSPECIFIED   0x0040  /* over 802.1x */
+#define WPA2_AUTH_PSK           0x0080  /* Pre-shared key */
+#define WPA2_AUTH_RESERVED3     0x0200
+#define WPA2_AUTH_RESERVED4     0x0400
+#define WPA2_AUTH_RESERVED5     0x0800
+
+/* pmkid */
+#define MAXPMKID                16
+
+#define DOT11_DEFAULT_RTS_LEN           2347
+#define DOT11_DEFAULT_FRAG_LEN          2346
+
+#define DOT11_ICV_AES_LEN               8
+#define DOT11_QOS_LEN                   2
+#define DOT11_IV_MAX_LEN                8
+#define DOT11_A4_HDR_LEN                30
+
+#define HT_CAP_RX_STBC_NO               0x0
+#define HT_CAP_RX_STBC_ONE_STREAM       0x1
+
+typedef struct _pmkid {
+        u8 BSSID[ETH_ALEN];
+        u8 PMKID[WLAN_PMKID_LEN];
+} pmkid_t;
+
+typedef struct _pmkid_list {
+        u32 npmkid;
+        pmkid_t pmkid[1];
+} pmkid_list_t;
+
+typedef struct _pmkid_cand {
+        u8 BSSID[ETH_ALEN];
+        u8 preauth;
+} pmkid_cand_t;
+
+typedef struct _pmkid_cand_list {
+        u32 npmkid_cand;
+        pmkid_cand_t pmkid_cand[1];
+} pmkid_cand_list_t;
+
+typedef u8 ac_bitmap_t;
+
+#endif                          /* _BRCMU_WIFI_H_ */
diff --git a/drivers/staging/brcm80211/include/chipcommon.h b/drivers/staging/brcm80211/include/chipcommon.h
new file mode 100644
index 00000000000..296582aced6
--- /dev/null
+++ b/drivers/staging/brcm80211/include/chipcommon.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SBCHIPC_H
+#define _SBCHIPC_H
+
+#include "defs.h"               /* for PAD macro */
+
+typedef volatile struct {
+        u32 chipid;             /* 0x0 */
+        u32 capabilities;
+        u32 corecontrol;        /* corerev >= 1 */
+        u32 bist;
+
+        /* OTP */
+        u32 otpstatus;  /* 0x10, corerev >= 10 */
+        u32 otpcontrol;
+        u32 otpprog;
+        u32 otplayout;  /* corerev >= 23 */
+
+        /* Interrupt control */
+        u32 intstatus;  /* 0x20 */
+        u32 intmask;
+
+        /* Chip specific regs */
+        u32 chipcontrol;        /* 0x28, rev >= 11 */
+        u32 chipstatus; /* 0x2c, rev >= 11 */
+
+        /* Jtag Master */
+        u32 jtagcmd;            /* 0x30, rev >= 10 */
+        u32 jtagir;
+        u32 jtagdr;
+        u32 jtagctrl;
+
+        /* serial flash interface registers */
+        u32 flashcontrol;       /* 0x40 */
+        u32 flashaddress;
+        u32 flashdata;
+        u32 PAD[1];
+
+        /* Silicon backplane configuration broadcast control */
+        u32 broadcastaddress;   /* 0x50 */
+        u32 broadcastdata;
+
+        /* gpio - cleared only by power-on-reset */
+        u32 gpiopullup; /* 0x58, corerev >= 20 */
+        u32 gpiopulldown;       /* 0x5c, corerev >= 20 */
+        u32 gpioin;             /* 0x60 */
+        u32 gpioout;            /* 0x64 */
+        u32 gpioouten;  /* 0x68 */
+        u32 gpiocontrol;        /* 0x6C */
+        u32 gpiointpolarity;    /* 0x70 */
+        u32 gpiointmask;        /* 0x74 */
+
+        /* GPIO events corerev >= 11 */
+        u32 gpioevent;
+        u32 gpioeventintmask;
+
+        /* Watchdog timer */
+        u32 watchdog;   /* 0x80 */
+
+        /* GPIO events corerev >= 11 */
+        u32 gpioeventintpolarity;
+
+        /* GPIO based LED powersave registers corerev >= 16 */
+        u32 gpiotimerval;       /* 0x88 */
+        u32 gpiotimeroutmask;
+
+        /* clock control */
+        u32 clockcontrol_n;     /* 0x90 */
+        u32 clockcontrol_sb;    /* aka m0 */
+        u32 clockcontrol_pci;   /* aka m1 */
+        u32 clockcontrol_m2;    /* mii/uart/mipsref */
+        u32 clockcontrol_m3;    /* cpu */
+        u32 clkdiv;             /* corerev >= 3 */
+        u32 gpiodebugsel;       /* corerev >= 28 */
+        u32 capabilities_ext;   /* 0xac  */
+
+        /* pll delay registers (corerev >= 4) */
+        u32 pll_on_delay;       /* 0xb0 */
+        u32 fref_sel_delay;
+        u32 slow_clk_ctl;       /* 5 < corerev < 10 */
+        u32 PAD;
+
+        /* Instaclock registers (corerev >= 10) */
+        u32 system_clk_ctl;     /* 0xc0 */
+        u32 clkstatestretch;
+        u32 PAD[2];
+
+        /* Indirect backplane access (corerev >= 22) */
+        u32 bp_addrlow; /* 0xd0 */
+        u32 bp_addrhigh;
+        u32 bp_data;
+        u32 PAD;
+        u32 bp_indaccess;
+        u32 PAD[3];
+
+        /* More clock dividers (corerev >= 32) */
+        u32 clkdiv2;
+        u32 PAD[2];
+
+        /* In AI chips, pointer to erom */
+        u32 eromptr;            /* 0xfc */
+
+        /* ExtBus control registers (corerev >= 3) */
+        u32 pcmcia_config;      /* 0x100 */
+        u32 pcmcia_memwait;
+        u32 pcmcia_attrwait;
+        u32 pcmcia_iowait;
+        u32 ide_config;
+        u32 ide_memwait;
+        u32 ide_attrwait;
+        u32 ide_iowait;
+        u32 prog_config;
+        u32 prog_waitcount;
+        u32 flash_config;
+        u32 flash_waitcount;
+        u32 SECI_config;        /* 0x130 SECI configuration */
+        u32 PAD[3];
+
+        /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
+        u32 eci_output; /* 0x140 */
+        u32 eci_control;
+        u32 eci_inputlo;
+        u32 eci_inputmi;
+        u32 eci_inputhi;
+        u32 eci_inputintpolaritylo;
+        u32 eci_inputintpolaritymi;
+        u32 eci_inputintpolarityhi;
+        u32 eci_intmasklo;
+        u32 eci_intmaskmi;
+        u32 eci_intmaskhi;
+        u32 eci_eventlo;
+        u32 eci_eventmi;
+        u32 eci_eventhi;
+        u32 eci_eventmasklo;
+        u32 eci_eventmaskmi;
+        u32 eci_eventmaskhi;
+        u32 PAD[3];
+
+        /* SROM interface (corerev >= 32) */
+        u32 sromcontrol;        /* 0x190 */
+        u32 sromaddress;
+        u32 sromdata;
+        u32 PAD[17];
+
+        /* Clock control and hardware workarounds (corerev >= 20) */
+        u32 clk_ctl_st; /* 0x1e0 */
+        u32 hw_war;
+        u32 PAD[70];
+
+        /* UARTs */
+        u8 uart0data;   /* 0x300 */
+        u8 uart0imr;
+        u8 uart0fcr;
+        u8 uart0lcr;
+        u8 uart0mcr;
+        u8 uart0lsr;
+        u8 uart0msr;
+        u8 uart0scratch;
+        u8 PAD[248];            /* corerev >= 1 */
+
+        u8 uart1data;   /* 0x400 */
+        u8 uart1imr;
+        u8 uart1fcr;
+        u8 uart1lcr;
+        u8 uart1mcr;
+        u8 uart1lsr;
+        u8 uart1msr;
+        u8 uart1scratch;
+        u32 PAD[126];
+
+        /* PMU registers (corerev >= 20) */
+        u32 pmucontrol; /* 0x600 */
+        u32 pmucapabilities;
+        u32 pmustatus;
+        u32 res_state;
+        u32 res_pending;
+        u32 pmutimer;
+        u32 min_res_mask;
+        u32 max_res_mask;
+        u32 res_table_sel;
+        u32 res_dep_mask;
+        u32 res_updn_timer;
+        u32 res_timer;
+        u32 clkstretch;
+        u32 pmuwatchdog;
+        u32 gpiosel;            /* 0x638, rev >= 1 */
+        u32 gpioenable; /* 0x63c, rev >= 1 */
+        u32 res_req_timer_sel;
+        u32 res_req_timer;
+        u32 res_req_mask;
+        u32 PAD;
+        u32 chipcontrol_addr;   /* 0x650 */
+        u32 chipcontrol_data;   /* 0x654 */
+        u32 regcontrol_addr;
+        u32 regcontrol_data;
+        u32 pllcontrol_addr;
+        u32 pllcontrol_data;
+        u32 pmustrapopt;        /* 0x668, corerev >= 28 */
+        u32 pmu_xtalfreq;       /* 0x66C, pmurev >= 10 */
+        u32 PAD[100];
+        u16 sromotp[768];
+} chipcregs_t;
+
+/* chipid */
+#define CID_ID_MASK             0x0000ffff      /* Chip Id mask */
+#define CID_REV_MASK            0x000f0000      /* Chip Revision mask */
+#define CID_REV_SHIFT           16      /* Chip Revision shift */
+#define CID_PKG_MASK            0x00f00000      /* Package Option mask */
+#define CID_PKG_SHIFT           20      /* Package Option shift */
+#define CID_CC_MASK             0x0f000000      /* CoreCount (corerev >= 4) */
+#define CID_CC_SHIFT            24
+#define CID_TYPE_MASK           0xf0000000      /* Chip Type */
+#define CID_TYPE_SHIFT          28
+
+/* capabilities */
+#define CC_CAP_UARTS_MASK       0x00000003      /* Number of UARTs */
+#define CC_CAP_MIPSEB           0x00000004      /* MIPS is in big-endian mode */
+#define CC_CAP_UCLKSEL          0x00000018      /* UARTs clock select */
+#define CC_CAP_UINTCLK          0x00000008      /* UARTs are driven by internal divided clock */
+#define CC_CAP_UARTGPIO         0x00000020      /* UARTs own GPIOs 15:12 */
+#define CC_CAP_EXTBUS_MASK      0x000000c0      /* External bus mask */
+#define CC_CAP_EXTBUS_NONE      0x00000000      /* No ExtBus present */
+#define CC_CAP_EXTBUS_FULL      0x00000040      /* ExtBus: PCMCIA, IDE & Prog */
+#define CC_CAP_EXTBUS_PROG      0x00000080      /* ExtBus: ProgIf only */
+#define CC_CAP_FLASH_MASK       0x00000700      /* Type of flash */
+#define CC_CAP_PLL_MASK         0x00038000      /* Type of PLL */
+#define CC_CAP_PWR_CTL          0x00040000      /* Power control */
+#define CC_CAP_OTPSIZE          0x00380000      /* OTP Size (0 = none) */
+#define CC_CAP_OTPSIZE_SHIFT    19      /* OTP Size shift */
+#define CC_CAP_OTPSIZE_BASE     5       /* OTP Size base */
+#define CC_CAP_JTAGP            0x00400000      /* JTAG Master Present */
+#define CC_CAP_ROM              0x00800000      /* Internal boot rom active */
+#define CC_CAP_BKPLN64          0x08000000      /* 64-bit backplane */
+#define CC_CAP_PMU              0x10000000      /* PMU Present, rev >= 20 */
+#define CC_CAP_SROM             0x40000000      /* Srom Present, rev >= 32 */
+#define CC_CAP_NFLASH           0x80000000      /* Nand flash present, rev >= 35 */
+
+#define CC_CAP2_SECI            0x00000001      /* SECI Present, rev >= 36 */
+#define CC_CAP2_GSIO            0x00000002      /* GSIO (spi/i2c) present, rev >= 37 */
+
+/* pmucapabilities */
+#define PCAP_REV_MASK   0x000000ff
+#define PCAP_RC_MASK    0x00001f00
+#define PCAP_RC_SHIFT   8
+#define PCAP_TC_MASK    0x0001e000
+#define PCAP_TC_SHIFT   13
+#define PCAP_PC_MASK    0x001e0000
+#define PCAP_PC_SHIFT   17
+#define PCAP_VC_MASK    0x01e00000
+#define PCAP_VC_SHIFT   21
+#define PCAP_CC_MASK    0x1e000000
+#define PCAP_CC_SHIFT   25
+#define PCAP5_PC_MASK   0x003e0000      /* PMU corerev >= 5 */
+#define PCAP5_PC_SHIFT  17
+#define PCAP5_VC_MASK   0x07c00000
+#define PCAP5_VC_SHIFT  22
+#define PCAP5_CC_MASK   0xf8000000
+#define PCAP5_CC_SHIFT  27
+
+/*
+* Maximum delay for the PMU state transition in us.
+* This is an upper bound intended for spinwaits etc.
+*/
+#define PMU_MAX_TRANSITION_DLY  15000
+
+#endif                          /* _SBCHIPC_H */
diff --git a/drivers/staging/brcm80211/include/defs.h b/drivers/staging/brcm80211/include/defs.h
new file mode 100644
index 00000000000..8b3e17dec15
--- /dev/null
+++ b/drivers/staging/brcm80211/include/defs.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_DEFS_H_
+#define _BRCM_DEFS_H_
+
+#include <linux/types.h>
+
+#define SI_BUS                  0
+#define PCI_BUS                 1
+#define PCMCIA_BUS              2
+#define SDIO_BUS                3
+#define JTAG_BUS                4
+#define USB_BUS                 5
+#define SPI_BUS                 6
+
+#ifndef OFF
+#define OFF     0
+#endif
+
+#ifndef ON
+#define ON      1               /* ON = 1 */
+#endif
+
+#define AUTO    (-1)            /* Auto = -1 */
+
+/*
+ * Priority definitions according 802.1D
+ */
+#define PRIO_8021D_NONE         2
+#define PRIO_8021D_BK           1
+#define PRIO_8021D_BE           0
+#define PRIO_8021D_EE           3
+#define PRIO_8021D_CL           4
+#define PRIO_8021D_VI           5
+#define PRIO_8021D_VO           6
+#define PRIO_8021D_NC           7
+
+#define MAXPRIO                 7
+#define NUMPRIO                 (MAXPRIO + 1)
+
+#define WL_NUMRATES             16      /* max # of rates in a rateset */
+
+typedef struct wl_rateset {
+        u32 count;              /* # rates in this set */
+        u8 rates[WL_NUMRATES];  /* rates in 500kbps units w/hi bit set if basic */
+} wl_rateset_t;
+
+#define BRCM_CNTRY_BUF_SZ       4       /* Country string is 3 bytes + NUL */
+
+#define BRCM_SET_CHANNEL                                30
+#define BRCM_SET_SRL                            32
+#define BRCM_SET_LRL                            34
+
+#define BRCM_SET_RATESET                                72
+#define BRCM_SET_BCNPRD                         76
+#define BRCM_GET_CURR_RATESET                   114     /* current rateset */
+#define BRCM_GET_PHYLIST                                180
+
+/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
+#define WL_RADIO_SW_DISABLE             (1<<0)
+#define WL_RADIO_HW_DISABLE             (1<<1)
+#define WL_RADIO_MPC_DISABLE            (1<<2)
+#define WL_RADIO_COUNTRY_DISABLE        (1<<3)  /* some countries don't support any channel */
+
+/* Override bit for SET_TXPWR.  if set, ignore other level limits */
+#define WL_TXPWR_OVERRIDE       (1U<<31)
+
+/* band types */
+#define BRCM_BAND_AUTO          0       /* auto-select */
+#define BRCM_BAND_5G            1       /* 5 Ghz */
+#define BRCM_BAND_2G            2       /* 2.4 Ghz */
+#define BRCM_BAND_ALL           3       /* all bands */
+
+/* Values for PM */
+#define PM_OFF  0
+#define PM_MAX  1
+
+/* Message levels */
+#define LOG_ERROR_VAL           0x00000001
+#define LOG_TRACE_VAL           0x00000002
+
+#define PM_OFF  0
+#define PM_MAX  1
+#define PM_FAST 2
+
+/*
+ * Sonics Configuration Space Registers.
+ */
+#define SBCONFIGOFF             0xf00   /* core sbconfig regs are top 256bytes of regs */
+
+/* cpp contortions to concatenate w/arg prescan */
+#ifndef PAD
+#define _PADLINE(line)  pad ## line
+#define _XSTR(line)     _PADLINE(line)
+#define PAD             _XSTR(__LINE__)
+#endif
+
+#endif                          /* _BRCM_DEFS_H_ */
diff --git a/drivers/staging/brcm80211/include/soc.h b/drivers/staging/brcm80211/include/soc.h
new file mode 100644
index 00000000000..6e5a705c493
--- /dev/null
+++ b/drivers/staging/brcm80211/include/soc.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_SOC_H
+#define _BRCM_SOC_H
+
+#ifdef SI_ENUM_BASE_VARIABLE
+#define SI_ENUM_BASE            (sii->pub.si_enum_base)
+#else
+#define SI_ENUM_BASE            0x18000000      /* Enumeration space base */
+#endif                          /* SI_ENUM_BASE_VARIABLE */
+
+/* core codes */
+#define NODEV_CORE_ID           0x700   /* Invalid coreid */
+#define CC_CORE_ID              0x800   /* chipcommon core */
+#define ILINE20_CORE_ID         0x801   /* iline20 core */
+#define SRAM_CORE_ID            0x802   /* sram core */
+#define SDRAM_CORE_ID           0x803   /* sdram core */
+#define PCI_CORE_ID             0x804   /* pci core */
+#define MIPS_CORE_ID            0x805   /* mips core */
+#define ENET_CORE_ID            0x806   /* enet mac core */
+#define CODEC_CORE_ID           0x807   /* v90 codec core */
+#define USB_CORE_ID             0x808   /* usb 1.1 host/device core */
+#define ADSL_CORE_ID            0x809   /* ADSL core */
+#define ILINE100_CORE_ID        0x80a   /* iline100 core */
+#define IPSEC_CORE_ID           0x80b   /* ipsec core */
+#define UTOPIA_CORE_ID          0x80c   /* utopia core */
+#define PCMCIA_CORE_ID          0x80d   /* pcmcia core */
+#define SOCRAM_CORE_ID          0x80e   /* internal memory core */
+#define MEMC_CORE_ID            0x80f   /* memc sdram core */
+#define OFDM_CORE_ID            0x810   /* OFDM phy core */
+#define EXTIF_CORE_ID           0x811   /* external interface core */
+#define D11_CORE_ID             0x812   /* 802.11 MAC core */
+#define APHY_CORE_ID            0x813   /* 802.11a phy core */
+#define BPHY_CORE_ID            0x814   /* 802.11b phy core */
+#define GPHY_CORE_ID            0x815   /* 802.11g phy core */
+#define MIPS33_CORE_ID          0x816   /* mips3302 core */
+#define USB11H_CORE_ID          0x817   /* usb 1.1 host core */
+#define USB11D_CORE_ID          0x818   /* usb 1.1 device core */
+#define USB20H_CORE_ID          0x819   /* usb 2.0 host core */
+#define USB20D_CORE_ID          0x81a   /* usb 2.0 device core */
+#define SDIOH_CORE_ID           0x81b   /* sdio host core */
+#define ROBO_CORE_ID            0x81c   /* roboswitch core */
+#define ATA100_CORE_ID          0x81d   /* parallel ATA core */
+#define SATAXOR_CORE_ID         0x81e   /* serial ATA & XOR DMA core */
+#define GIGETH_CORE_ID          0x81f   /* gigabit ethernet core */
+#define PCIE_CORE_ID            0x820   /* pci express core */
+#define NPHY_CORE_ID            0x821   /* 802.11n 2x2 phy core */
+#define SRAMC_CORE_ID           0x822   /* SRAM controller core */
+#define MINIMAC_CORE_ID         0x823   /* MINI MAC/phy core */
+#define ARM11_CORE_ID           0x824   /* ARM 1176 core */
+#define ARM7S_CORE_ID           0x825   /* ARM7tdmi-s core */
+#define LPPHY_CORE_ID           0x826   /* 802.11a/b/g phy core */
+#define PMU_CORE_ID             0x827   /* PMU core */
+#define SSNPHY_CORE_ID          0x828   /* 802.11n single-stream phy core */
+#define SDIOD_CORE_ID           0x829   /* SDIO device core */
+#define ARMCM3_CORE_ID          0x82a   /* ARM Cortex M3 core */
+#define HTPHY_CORE_ID           0x82b   /* 802.11n 4x4 phy core */
+#define MIPS74K_CORE_ID         0x82c   /* mips 74k core */
+#define GMAC_CORE_ID            0x82d   /* Gigabit MAC core */
+#define DMEMC_CORE_ID           0x82e   /* DDR1/2 memory controller core */
+#define PCIERC_CORE_ID          0x82f   /* PCIE Root Complex core */
+#define OCP_CORE_ID             0x830   /* OCP2OCP bridge core */
+#define SC_CORE_ID              0x831   /* shared common core */
+#define AHB_CORE_ID             0x832   /* OCP2AHB bridge core */
+#define SPIH_CORE_ID            0x833   /* SPI host core */
+#define I2S_CORE_ID             0x834   /* I2S core */
+#define DMEMS_CORE_ID           0x835   /* SDR/DDR1 memory controller core */
+#define DEF_SHIM_COMP           0x837   /* SHIM component in ubus/6362 */
+#define OOB_ROUTER_CORE_ID      0x367   /* OOB router core ID */
+#define DEF_AI_COMP             0xfff   /* Default component, in ai chips it maps all
+                                         * unused address ranges
+                                         */
+
+/* Common core control flags */
+#define SICF_BIST_EN            0x8000
+#define SICF_PME_EN             0x4000
+#define SICF_CORE_BITS          0x3ffc
+#define SICF_FGC                0x0002
+#define SICF_CLOCK_EN           0x0001
+
+#endif                          /* _BRCM_SOC_H */