1 files changed, 166 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcmdhd/include/sbsdio.h b/drivers/net/wireless/bcmdhd/include/sbsdio.h
new file mode 100644
index 00000000000..4280d5bf9c1
--- /dev/null
+++ b/drivers/net/wireless/bcmdhd/include/sbsdio.h
@@ -0,0 +1,166 @@
+/*
+ * SDIO device core hardware definitions.
+ * sdio is a portion of the pcmcia core in core rev 3 - rev 8
+ *
+ * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
+ *
+ * Copyright (C) 1999-2011, Broadcom Corporation
+ * 
+ *         Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2 (the "GPL"),
+ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
+ * following added to such license:
+ * 
+ *      As a special exception, the copyright holders of this software give you
+ * permission to link this software with independent modules, and to copy and
+ * distribute the resulting executable under terms of your choice, provided that
+ * you also meet, for each linked independent module, the terms and conditions of
+ * the license of that module.  An independent module is a module which is not
+ * derived from this software.  The special exception does not apply to any
+ * modifications of the software.
+ * 
+ *      Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a license
+ * other than the GPL, without Broadcom's express prior written consent.
+ *
+ * $Id: sbsdio.h,v 13.34 2009-03-11 20:27:16 Exp $
+ */
+#ifndef _SBSDIO_H
+#define _SBSDIO_H
+#define SBSDIO_NUM_FUNCTION             3       /* as of sdiod rev 0, supports 3 functions */
+/* function 1 miscellaneous registers */
+#define SBSDIO_SPROM_CS                 0x10000         /* sprom command and status */
+#define SBSDIO_SPROM_INFO               0x10001         /* sprom info register */
+#define SBSDIO_SPROM_DATA_LOW           0x10002         /* sprom indirect access data byte 0 */
+#define SBSDIO_SPROM_DATA_HIGH          0x10003         /* sprom indirect access data byte 1 */
+#define SBSDIO_SPROM_ADDR_LOW           0x10004         /* sprom indirect access addr byte 0 */
+#define SBSDIO_SPROM_ADDR_HIGH          0x10005         /* sprom indirect access addr byte 0 */
+#define SBSDIO_CHIP_CTRL_DATA           0x10006         /* xtal_pu (gpio) output */
+#define SBSDIO_CHIP_CTRL_EN             0x10007         /* xtal_pu (gpio) enable */
+#define SBSDIO_WATERMARK                0x10008         /* rev < 7, watermark for sdio device */
+#define SBSDIO_DEVICE_CTL               0x10009         /* control busy signal generation */
+/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
+#define SBSDIO_FUNC1_SBADDRLOW          0x1000A         /* SB Address Window Low (b15) */
+#define SBSDIO_FUNC1_SBADDRMID          0x1000B         /* SB Address Window Mid (b23:b16) */
+#define SBSDIO_FUNC1_SBADDRHIGH         0x1000C         /* SB Address Window High (b31:b24)    */
+#define SBSDIO_FUNC1_FRAMECTRL          0x1000D         /* Frame Control (frame term/abort) */
+#define SBSDIO_FUNC1_CHIPCLKCSR         0x1000E         /* ChipClockCSR (ALP/HT ctl/status) */
+#define SBSDIO_FUNC1_SDIOPULLUP         0x1000F         /* SdioPullUp (on cmd, d0-d2) */
+#define SBSDIO_FUNC1_WFRAMEBCLO         0x10019         /* Write Frame Byte Count Low */
+#define SBSDIO_FUNC1_WFRAMEBCHI         0x1001A         /* Write Frame Byte Count High */
+#define SBSDIO_FUNC1_RFRAMEBCLO         0x1001B         /* Read Frame Byte Count Low */
+#define SBSDIO_FUNC1_RFRAMEBCHI         0x1001C         /* Read Frame Byte Count High */
+#define SBSDIO_FUNC1_MISC_REG_START     0x10000         /* f1 misc register start */
+#define SBSDIO_FUNC1_MISC_REG_LIMIT     0x1001C         /* f1 misc register end */
+/* SBSDIO_SPROM_CS */
+#define SBSDIO_SPROM_IDLE               0
+#define SBSDIO_SPROM_WRITE              1
+#define SBSDIO_SPROM_READ               2
+#define SBSDIO_SPROM_WEN                4
+#define SBSDIO_SPROM_WDS                7
+#define SBSDIO_SPROM_DONE               8
+/* SBSDIO_SPROM_INFO */
+#define SROM_SZ_MASK                    0x03            /* SROM size, 1: 4k, 2: 16k */
+#define SROM_BLANK                      0x04            /* depreciated in corerev 6 */
+#define SROM_OTP                        0x80            /* OTP present */
+/* SBSDIO_CHIP_CTRL */
+#define SBSDIO_CHIP_CTRL_XTAL           0x01            /* or'd with onchip xtal_pu,
+                                                         * 1: power on oscillator
+                                                         * (for 4318 only)
+                                                         */
+/* SBSDIO_WATERMARK */
+#define SBSDIO_WATERMARK_MASK           0x7f            /* number of words - 1 for sd device
+                                                         * to wait before sending data to host
+                                                         */
+/* SBSDIO_DEVICE_CTL */
+#define SBSDIO_DEVCTL_SETBUSY           0x01            /* 1: device will assert busy signal when
+                                                         * receiving CMD53
+                                                         */
+#define SBSDIO_DEVCTL_SPI_INTR_SYNC     0x02            /* 1: assertion of sdio interrupt is
+                                                         * synchronous to the sdio clock
+                                                         */
+#define SBSDIO_DEVCTL_CA_INT_ONLY       0x04            /* 1: mask all interrupts to host
+                                                         * except the chipActive (rev 8)
+                                                         */
+#define SBSDIO_DEVCTL_PADS_ISO          0x08            /* 1: isolate internal sdio signals, put
+                                                         * external pads in tri-state; requires
+                                                         * sdio bus power cycle to clear (rev 9)
+                                                         */
+#define SBSDIO_DEVCTL_SB_RST_CTL        0x30            /* Force SD->SB reset mapping (rev 11) */
+#define SBSDIO_DEVCTL_RST_CORECTL       0x00            /*   Determined by CoreControl bit */
+#define SBSDIO_DEVCTL_RST_BPRESET       0x10            /*   Force backplane reset */
+#define SBSDIO_DEVCTL_RST_NOBPRESET     0x20            /*   Force no backplane reset */
+/* SBSDIO_FUNC1_CHIPCLKCSR */
+#define SBSDIO_FORCE_ALP                0x01            /* Force ALP request to backplane */
+#define SBSDIO_FORCE_HT                 0x02            /* Force HT request to backplane */
+#define SBSDIO_FORCE_ILP                0x04            /* Force ILP request to backplane */
+#define SBSDIO_ALP_AVAIL_REQ            0x08            /* Make ALP ready (power up xtal) */
+#define SBSDIO_HT_AVAIL_REQ             0x10            /* Make HT ready (power up PLL) */
+#define SBSDIO_FORCE_HW_CLKREQ_OFF      0x20            /* Squelch clock requests from HW */
+#define SBSDIO_ALP_AVAIL                0x40            /* Status: ALP is ready */
+#define SBSDIO_HT_AVAIL                 0x80            /* Status: HT is ready */
+/* In rev8, actual avail bits followed original docs */
+#define SBSDIO_Rev8_HT_AVAIL            0x40
+#define SBSDIO_Rev8_ALP_AVAIL           0x80
+#define SBSDIO_AVBITS                   (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
+#define SBSDIO_ALPAV(regval)            ((regval) & SBSDIO_AVBITS)
+#define SBSDIO_HTAV(regval)             (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
+#define SBSDIO_ALPONLY(regval)          (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
+#define SBSDIO_CLKAV(regval, alponly)   (SBSDIO_ALPAV(regval) && \
+                                        (alponly ? 1 : SBSDIO_HTAV(regval)))
+/* SBSDIO_FUNC1_SDIOPULLUP */
+#define SBSDIO_PULLUP_D0                0x01            /* Enable D0/MISO pullup */
+#define SBSDIO_PULLUP_D1                0x02            /* Enable D1/INT# pullup */
+#define SBSDIO_PULLUP_D2                0x04            /* Enable D2 pullup */
+#define SBSDIO_PULLUP_CMD               0x08            /* Enable CMD/MOSI pullup */
+#define SBSDIO_PULLUP_ALL               0x0f            /* All valid bits */
+/* function 1 OCP space */
+#define SBSDIO_SB_OFT_ADDR_MASK         0x07FFF         /* sb offset addr is <= 15 bits, 32k */
+#define SBSDIO_SB_OFT_ADDR_LIMIT        0x08000
+#define SBSDIO_SB_ACCESS_2_4B_FLAG      0x08000         /* with b15, maps to 32-bit SB access */
+/* some duplication with sbsdpcmdev.h here */
+/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
+#define SBSDIO_SBADDRLOW_MASK           0x80            /* Valid bits in SBADDRLOW */
+#define SBSDIO_SBADDRMID_MASK           0xff            /* Valid bits in SBADDRMID */
+#define SBSDIO_SBADDRHIGH_MASK          0xffU           /* Valid bits in SBADDRHIGH */
+#define SBSDIO_SBWINDOW_MASK            0xffff8000      /* Address bits from SBADDR regs */
+/* direct(mapped) cis space */
+#define SBSDIO_CIS_BASE_COMMON          0x1000          /* MAPPED common CIS address */
+#define SBSDIO_CIS_SIZE_LIMIT           0x200           /* maximum bytes in one CIS */
+#define SBSDIO_OTP_CIS_SIZE_LIMIT       0x078           /* maximum bytes OTP CIS */
+#define SBSDIO_CIS_OFT_ADDR_MASK        0x1FFFF         /* cis offset addr is < 17 bits */
+#define SBSDIO_CIS_MANFID_TUPLE_LEN     6               /* manfid tuple length, include tuple,
+                                                         * link bytes
+                                                         */
+/* indirect cis access (in sprom) */
+#define SBSDIO_SPROM_CIS_OFFSET         0x8             /* 8 control bytes first, CIS starts from
+                                                         * 8th byte
+                                                         */
+#define SBSDIO_BYTEMODE_DATALEN_MAX     64              /* sdio byte mode: maximum length of one
+                                                         * data comamnd
+                                                         */
+#define SBSDIO_CORE_ADDR_MASK           0x1FFFF         /* sdio core function one address mask */
+#endif  /* _SBSDIO_H */

diff --git a/drivers/net/wireless/bcmdhd/include/sbsdio.h b/drivers/net/wireless/bcmdhd/include/sbsdio.h new file mode 100644 index 00000000000..4280d5bf9c1 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbsdio.h
@@ -0,0 +1,166 @@
	1	/*
	2	* SDIO device core hardware definitions.
	3	* sdio is a portion of the pcmcia core in core rev 3 - rev 8
	4	*
	5	* SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
	6	*
	7	* Copyright (C) 1999-2011, Broadcom Corporation
	8	*
	9	* Unless you and Broadcom execute a separate written software license
	10	* agreement governing use of this software, this software is licensed to you
	11	* under the terms of the GNU General Public License version 2 (the "GPL"),
	12	* available at http://www.broadcom.com/licenses/GPLv2.php, with the
	13	* following added to such license:
	14	*
	15	* As a special exception, the copyright holders of this software give you
	16	* permission to link this software with independent modules, and to copy and
	17	* distribute the resulting executable under terms of your choice, provided that
	18	* you also meet, for each linked independent module, the terms and conditions of
	19	* the license of that module. An independent module is a module which is not
	20	* derived from this software. The special exception does not apply to any
	21	* modifications of the software.
	22	*
	23	* Notwithstanding the above, under no circumstances may you combine this
	24	* software in any way with any other Broadcom software provided under a license
	25	* other than the GPL, without Broadcom's express prior written consent.
	26	*
	27	* $Id: sbsdio.h,v 13.34 2009-03-11 20:27:16 Exp $
	28	*/
	29
	30	#ifndef _SBSDIO_H
	31	#define _SBSDIO_H
	32
	33	#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
	34
	35	/* function 1 miscellaneous registers */
	36	#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
	37	#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
	38	#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
	39	#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
	40	#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
	41	#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
	42	#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
	43	#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
	44	#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
	45	#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
	46
	47	/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
	48	#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
	49	#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
	50	#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
	51	#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
	52	#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
	53	#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
	54	#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
	55	#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
	56	#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
	57	#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
	58
	59	#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
	60	#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
	61
	62	/* SBSDIO_SPROM_CS */
	63	#define SBSDIO_SPROM_IDLE 0
	64	#define SBSDIO_SPROM_WRITE 1
	65	#define SBSDIO_SPROM_READ 2
	66	#define SBSDIO_SPROM_WEN 4
	67	#define SBSDIO_SPROM_WDS 7
	68	#define SBSDIO_SPROM_DONE 8
	69
	70	/* SBSDIO_SPROM_INFO */
	71	#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
	72	#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
	73	#define SROM_OTP 0x80 /* OTP present */
	74
	75	/* SBSDIO_CHIP_CTRL */
	76	#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
	77	* 1: power on oscillator
	78	* (for 4318 only)
	79	*/
	80	/* SBSDIO_WATERMARK */
	81	#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
	82	* to wait before sending data to host
	83	*/
	84
	85	/* SBSDIO_DEVICE_CTL */
	86	#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
	87	* receiving CMD53
	88	*/
	89	#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
	90	* synchronous to the sdio clock
	91	*/
	92	#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
	93	* except the chipActive (rev 8)
	94	*/
	95	#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
	96	* external pads in tri-state; requires
	97	* sdio bus power cycle to clear (rev 9)
	98	*/
	99	#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
	100	#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
	101	#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
	102	#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
	103
	104
	105	/* SBSDIO_FUNC1_CHIPCLKCSR */
	106	#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
	107	#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
	108	#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
	109	#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
	110	#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
	111	#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
	112	#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
	113	#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
	114	/* In rev8, actual avail bits followed original docs */
	115	#define SBSDIO_Rev8_HT_AVAIL 0x40
	116	#define SBSDIO_Rev8_ALP_AVAIL 0x80
	117
	118	#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL \| SBSDIO_ALP_AVAIL)
	119	#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
	120	#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
	121	#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
	122	#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
	123	(alponly ? 1 : SBSDIO_HTAV(regval)))
	124
	125	/* SBSDIO_FUNC1_SDIOPULLUP */
	126	#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
	127	#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
	128	#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
	129	#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
	130	#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
	131
	132	/* function 1 OCP space */
	133	#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
	134	#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
	135	#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
	136
	137	/* some duplication with sbsdpcmdev.h here */
	138	/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
	139	#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
	140	#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
	141	#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
	142	#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
	143
	144	/* direct(mapped) cis space */
	145	#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
	146	#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
	147	#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
	148
	149	#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
	150
	151	#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
	152	* link bytes
	153	*/
	154
	155	/* indirect cis access (in sprom) */
	156	#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
	157	* 8th byte
	158	*/
	159
	160	#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
	161	* data comamnd
	162	*/
	163
	164	#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
	165
	166	#endif /* _SBSDIO_H */