diff options
Diffstat (limited to 'drivers/net/wireless/bcmdhd/include')
61 files changed, 17240 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcmdhd/include/Makefile b/drivers/net/wireless/bcmdhd/include/Makefile new file mode 100644 index 00000000000..c07266fd6fd --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/Makefile | |||
@@ -0,0 +1,53 @@ | |||
1 | #!/bin/bash | ||
2 | # | ||
3 | # This script serves following purpose: | ||
4 | # | ||
5 | # 1. It generates native version information by querying | ||
6 | # automerger maintained database to see where src/include | ||
7 | # came from | ||
8 | # 2. For select components, as listed in compvers.sh | ||
9 | # it generates component version files | ||
10 | # | ||
11 | # Copyright 2005, Broadcom, Inc. | ||
12 | # | ||
13 | # $Id: Makefile 241702 2011-02-19 00:41:03Z automrgr $ | ||
14 | # | ||
15 | |||
16 | SRCBASE := .. | ||
17 | |||
18 | TARGETS := epivers.h | ||
19 | |||
20 | ifdef VERBOSE | ||
21 | export VERBOSE | ||
22 | endif | ||
23 | |||
24 | all release: epivers compvers | ||
25 | |||
26 | # Generate epivers.h for native branch version | ||
27 | epivers: | ||
28 | bash epivers.sh | ||
29 | |||
30 | # Generate epivers.h for native branch version | ||
31 | compvers: | ||
32 | @if [ -s "compvers.sh" ]; then \ | ||
33 | echo "Generating component versions, if any"; \ | ||
34 | bash compvers.sh; \ | ||
35 | else \ | ||
36 | echo "Skipping component version generation"; \ | ||
37 | fi | ||
38 | |||
39 | # Generate epivers.h for native branch version | ||
40 | clean_compvers: | ||
41 | @if [ -s "compvers.sh" ]; then \ | ||
42 | echo "bash compvers.sh clean"; \ | ||
43 | bash compvers.sh clean; \ | ||
44 | else \ | ||
45 | echo "Skipping component version clean"; \ | ||
46 | fi | ||
47 | |||
48 | clean: | ||
49 | rm -f $(TARGETS) *.prev | ||
50 | |||
51 | clean_all: clean clean_compvers | ||
52 | |||
53 | .PHONY: all release clean epivers compvers clean_compvers | ||
diff --git a/drivers/net/wireless/bcmdhd/include/aidmp.h b/drivers/net/wireless/bcmdhd/include/aidmp.h new file mode 100644 index 00000000000..375df443a29 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/aidmp.h | |||
@@ -0,0 +1,377 @@ | |||
1 | /* | ||
2 | * Broadcom AMBA Interconnect definitions. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: aidmp.h,v 13.4.14.1 2010-03-09 18:40:06 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _AIDMP_H | ||
29 | #define _AIDMP_H | ||
30 | |||
31 | |||
32 | #define MFGID_ARM 0x43b | ||
33 | #define MFGID_BRCM 0x4bf | ||
34 | #define MFGID_MIPS 0x4a7 | ||
35 | |||
36 | |||
37 | #define CC_SIM 0 | ||
38 | #define CC_EROM 1 | ||
39 | #define CC_CORESIGHT 9 | ||
40 | #define CC_VERIF 0xb | ||
41 | #define CC_OPTIMO 0xd | ||
42 | #define CC_GEN 0xe | ||
43 | #define CC_PRIMECELL 0xf | ||
44 | |||
45 | |||
46 | #define ER_EROMENTRY 0x000 | ||
47 | #define ER_REMAPCONTROL 0xe00 | ||
48 | #define ER_REMAPSELECT 0xe04 | ||
49 | #define ER_MASTERSELECT 0xe10 | ||
50 | #define ER_ITCR 0xf00 | ||
51 | #define ER_ITIP 0xf04 | ||
52 | |||
53 | |||
54 | #define ER_TAG 0xe | ||
55 | #define ER_TAG1 0x6 | ||
56 | #define ER_VALID 1 | ||
57 | #define ER_CI 0 | ||
58 | #define ER_MP 2 | ||
59 | #define ER_ADD 4 | ||
60 | #define ER_END 0xe | ||
61 | #define ER_BAD 0xffffffff | ||
62 | |||
63 | |||
64 | #define CIA_MFG_MASK 0xfff00000 | ||
65 | #define CIA_MFG_SHIFT 20 | ||
66 | #define CIA_CID_MASK 0x000fff00 | ||
67 | #define CIA_CID_SHIFT 8 | ||
68 | #define CIA_CCL_MASK 0x000000f0 | ||
69 | #define CIA_CCL_SHIFT 4 | ||
70 | |||
71 | |||
72 | #define CIB_REV_MASK 0xff000000 | ||
73 | #define CIB_REV_SHIFT 24 | ||
74 | #define CIB_NSW_MASK 0x00f80000 | ||
75 | #define CIB_NSW_SHIFT 19 | ||
76 | #define CIB_NMW_MASK 0x0007c000 | ||
77 | #define CIB_NMW_SHIFT 14 | ||
78 | #define CIB_NSP_MASK 0x00003e00 | ||
79 | #define CIB_NSP_SHIFT 9 | ||
80 | #define CIB_NMP_MASK 0x000001f0 | ||
81 | #define CIB_NMP_SHIFT 4 | ||
82 | |||
83 | |||
84 | #define MPD_MUI_MASK 0x0000ff00 | ||
85 | #define MPD_MUI_SHIFT 8 | ||
86 | #define MPD_MP_MASK 0x000000f0 | ||
87 | #define MPD_MP_SHIFT 4 | ||
88 | |||
89 | |||
90 | #define AD_ADDR_MASK 0xfffff000 | ||
91 | #define AD_SP_MASK 0x00000f00 | ||
92 | #define AD_SP_SHIFT 8 | ||
93 | #define AD_ST_MASK 0x000000c0 | ||
94 | #define AD_ST_SHIFT 6 | ||
95 | #define AD_ST_SLAVE 0x00000000 | ||
96 | #define AD_ST_BRIDGE 0x00000040 | ||
97 | #define AD_ST_SWRAP 0x00000080 | ||
98 | #define AD_ST_MWRAP 0x000000c0 | ||
99 | #define AD_SZ_MASK 0x00000030 | ||
100 | #define AD_SZ_SHIFT 4 | ||
101 | #define AD_SZ_4K 0x00000000 | ||
102 | #define AD_SZ_8K 0x00000010 | ||
103 | #define AD_SZ_16K 0x00000020 | ||
104 | #define AD_SZ_SZD 0x00000030 | ||
105 | #define AD_AG32 0x00000008 | ||
106 | #define AD_ADDR_ALIGN 0x00000fff | ||
107 | #define AD_SZ_BASE 0x00001000 | ||
108 | |||
109 | |||
110 | #define SD_SZ_MASK 0xfffff000 | ||
111 | #define SD_SG32 0x00000008 | ||
112 | #define SD_SZ_ALIGN 0x00000fff | ||
113 | |||
114 | |||
115 | #ifndef _LANGUAGE_ASSEMBLY | ||
116 | |||
117 | typedef volatile struct _aidmp { | ||
118 | uint32 oobselina30; | ||
119 | uint32 oobselina74; | ||
120 | uint32 PAD[6]; | ||
121 | uint32 oobselinb30; | ||
122 | uint32 oobselinb74; | ||
123 | uint32 PAD[6]; | ||
124 | uint32 oobselinc30; | ||
125 | uint32 oobselinc74; | ||
126 | uint32 PAD[6]; | ||
127 | uint32 oobselind30; | ||
128 | uint32 oobselind74; | ||
129 | uint32 PAD[38]; | ||
130 | uint32 oobselouta30; | ||
131 | uint32 oobselouta74; | ||
132 | uint32 PAD[6]; | ||
133 | uint32 oobseloutb30; | ||
134 | uint32 oobseloutb74; | ||
135 | uint32 PAD[6]; | ||
136 | uint32 oobseloutc30; | ||
137 | uint32 oobseloutc74; | ||
138 | uint32 PAD[6]; | ||
139 | uint32 oobseloutd30; | ||
140 | uint32 oobseloutd74; | ||
141 | uint32 PAD[38]; | ||
142 | uint32 oobsynca; | ||
143 | uint32 oobseloutaen; | ||
144 | uint32 PAD[6]; | ||
145 | uint32 oobsyncb; | ||
146 | uint32 oobseloutben; | ||
147 | uint32 PAD[6]; | ||
148 | uint32 oobsyncc; | ||
149 | uint32 oobseloutcen; | ||
150 | uint32 PAD[6]; | ||
151 | uint32 oobsyncd; | ||
152 | uint32 oobseloutden; | ||
153 | uint32 PAD[38]; | ||
154 | uint32 oobaextwidth; | ||
155 | uint32 oobainwidth; | ||
156 | uint32 oobaoutwidth; | ||
157 | uint32 PAD[5]; | ||
158 | uint32 oobbextwidth; | ||
159 | uint32 oobbinwidth; | ||
160 | uint32 oobboutwidth; | ||
161 | uint32 PAD[5]; | ||
162 | uint32 oobcextwidth; | ||
163 | uint32 oobcinwidth; | ||
164 | uint32 oobcoutwidth; | ||
165 | uint32 PAD[5]; | ||
166 | uint32 oobdextwidth; | ||
167 | uint32 oobdinwidth; | ||
168 | uint32 oobdoutwidth; | ||
169 | uint32 PAD[37]; | ||
170 | uint32 ioctrlset; | ||
171 | uint32 ioctrlclear; | ||
172 | uint32 ioctrl; | ||
173 | uint32 PAD[61]; | ||
174 | uint32 iostatus; | ||
175 | uint32 PAD[127]; | ||
176 | uint32 ioctrlwidth; | ||
177 | uint32 iostatuswidth; | ||
178 | uint32 PAD[62]; | ||
179 | uint32 resetctrl; | ||
180 | uint32 resetstatus; | ||
181 | uint32 resetreadid; | ||
182 | uint32 resetwriteid; | ||
183 | uint32 PAD[60]; | ||
184 | uint32 errlogctrl; | ||
185 | uint32 errlogdone; | ||
186 | uint32 errlogstatus; | ||
187 | uint32 errlogaddrlo; | ||
188 | uint32 errlogaddrhi; | ||
189 | uint32 errlogid; | ||
190 | uint32 errloguser; | ||
191 | uint32 errlogflags; | ||
192 | uint32 PAD[56]; | ||
193 | uint32 intstatus; | ||
194 | uint32 PAD[127]; | ||
195 | uint32 config; | ||
196 | uint32 PAD[63]; | ||
197 | uint32 itcr; | ||
198 | uint32 PAD[3]; | ||
199 | uint32 itipooba; | ||
200 | uint32 itipoobb; | ||
201 | uint32 itipoobc; | ||
202 | uint32 itipoobd; | ||
203 | uint32 PAD[4]; | ||
204 | uint32 itipoobaout; | ||
205 | uint32 itipoobbout; | ||
206 | uint32 itipoobcout; | ||
207 | uint32 itipoobdout; | ||
208 | uint32 PAD[4]; | ||
209 | uint32 itopooba; | ||
210 | uint32 itopoobb; | ||
211 | uint32 itopoobc; | ||
212 | uint32 itopoobd; | ||
213 | uint32 PAD[4]; | ||
214 | uint32 itopoobain; | ||
215 | uint32 itopoobbin; | ||
216 | uint32 itopoobcin; | ||
217 | uint32 itopoobdin; | ||
218 | uint32 PAD[4]; | ||
219 | uint32 itopreset; | ||
220 | uint32 PAD[15]; | ||
221 | uint32 peripherialid4; | ||
222 | uint32 peripherialid5; | ||
223 | uint32 peripherialid6; | ||
224 | uint32 peripherialid7; | ||
225 | uint32 peripherialid0; | ||
226 | uint32 peripherialid1; | ||
227 | uint32 peripherialid2; | ||
228 | uint32 peripherialid3; | ||
229 | uint32 componentid0; | ||
230 | uint32 componentid1; | ||
231 | uint32 componentid2; | ||
232 | uint32 componentid3; | ||
233 | } aidmp_t; | ||
234 | |||
235 | #endif | ||
236 | |||
237 | |||
238 | #define OOB_BUSCONFIG 0x020 | ||
239 | #define OOB_STATUSA 0x100 | ||
240 | #define OOB_STATUSB 0x104 | ||
241 | #define OOB_STATUSC 0x108 | ||
242 | #define OOB_STATUSD 0x10c | ||
243 | #define OOB_ENABLEA0 0x200 | ||
244 | #define OOB_ENABLEA1 0x204 | ||
245 | #define OOB_ENABLEA2 0x208 | ||
246 | #define OOB_ENABLEA3 0x20c | ||
247 | #define OOB_ENABLEB0 0x280 | ||
248 | #define OOB_ENABLEB1 0x284 | ||
249 | #define OOB_ENABLEB2 0x288 | ||
250 | #define OOB_ENABLEB3 0x28c | ||
251 | #define OOB_ENABLEC0 0x300 | ||
252 | #define OOB_ENABLEC1 0x304 | ||
253 | #define OOB_ENABLEC2 0x308 | ||
254 | #define OOB_ENABLEC3 0x30c | ||
255 | #define OOB_ENABLED0 0x380 | ||
256 | #define OOB_ENABLED1 0x384 | ||
257 | #define OOB_ENABLED2 0x388 | ||
258 | #define OOB_ENABLED3 0x38c | ||
259 | #define OOB_ITCR 0xf00 | ||
260 | #define OOB_ITIPOOBA 0xf10 | ||
261 | #define OOB_ITIPOOBB 0xf14 | ||
262 | #define OOB_ITIPOOBC 0xf18 | ||
263 | #define OOB_ITIPOOBD 0xf1c | ||
264 | #define OOB_ITOPOOBA 0xf30 | ||
265 | #define OOB_ITOPOOBB 0xf34 | ||
266 | #define OOB_ITOPOOBC 0xf38 | ||
267 | #define OOB_ITOPOOBD 0xf3c | ||
268 | |||
269 | |||
270 | #define AI_OOBSELINA30 0x000 | ||
271 | #define AI_OOBSELINA74 0x004 | ||
272 | #define AI_OOBSELINB30 0x020 | ||
273 | #define AI_OOBSELINB74 0x024 | ||
274 | #define AI_OOBSELINC30 0x040 | ||
275 | #define AI_OOBSELINC74 0x044 | ||
276 | #define AI_OOBSELIND30 0x060 | ||
277 | #define AI_OOBSELIND74 0x064 | ||
278 | #define AI_OOBSELOUTA30 0x100 | ||
279 | #define AI_OOBSELOUTA74 0x104 | ||
280 | #define AI_OOBSELOUTB30 0x120 | ||
281 | #define AI_OOBSELOUTB74 0x124 | ||
282 | #define AI_OOBSELOUTC30 0x140 | ||
283 | #define AI_OOBSELOUTC74 0x144 | ||
284 | #define AI_OOBSELOUTD30 0x160 | ||
285 | #define AI_OOBSELOUTD74 0x164 | ||
286 | #define AI_OOBSYNCA 0x200 | ||
287 | #define AI_OOBSELOUTAEN 0x204 | ||
288 | #define AI_OOBSYNCB 0x220 | ||
289 | #define AI_OOBSELOUTBEN 0x224 | ||
290 | #define AI_OOBSYNCC 0x240 | ||
291 | #define AI_OOBSELOUTCEN 0x244 | ||
292 | #define AI_OOBSYNCD 0x260 | ||
293 | #define AI_OOBSELOUTDEN 0x264 | ||
294 | #define AI_OOBAEXTWIDTH 0x300 | ||
295 | #define AI_OOBAINWIDTH 0x304 | ||
296 | #define AI_OOBAOUTWIDTH 0x308 | ||
297 | #define AI_OOBBEXTWIDTH 0x320 | ||
298 | #define AI_OOBBINWIDTH 0x324 | ||
299 | #define AI_OOBBOUTWIDTH 0x328 | ||
300 | #define AI_OOBCEXTWIDTH 0x340 | ||
301 | #define AI_OOBCINWIDTH 0x344 | ||
302 | #define AI_OOBCOUTWIDTH 0x348 | ||
303 | #define AI_OOBDEXTWIDTH 0x360 | ||
304 | #define AI_OOBDINWIDTH 0x364 | ||
305 | #define AI_OOBDOUTWIDTH 0x368 | ||
306 | |||
307 | |||
308 | #define AI_IOCTRLSET 0x400 | ||
309 | #define AI_IOCTRLCLEAR 0x404 | ||
310 | #define AI_IOCTRL 0x408 | ||
311 | #define AI_IOSTATUS 0x500 | ||
312 | #define AI_RESETCTRL 0x800 | ||
313 | #define AI_RESETSTATUS 0x804 | ||
314 | |||
315 | |||
316 | #define AI_IOCTRLWIDTH 0x700 | ||
317 | #define AI_IOSTATUSWIDTH 0x704 | ||
318 | |||
319 | #define AI_RESETREADID 0x808 | ||
320 | #define AI_RESETWRITEID 0x80c | ||
321 | #define AI_ERRLOGCTRL 0xa00 | ||
322 | #define AI_ERRLOGDONE 0xa04 | ||
323 | #define AI_ERRLOGSTATUS 0xa08 | ||
324 | #define AI_ERRLOGADDRLO 0xa0c | ||
325 | #define AI_ERRLOGADDRHI 0xa10 | ||
326 | #define AI_ERRLOGID 0xa14 | ||
327 | #define AI_ERRLOGUSER 0xa18 | ||
328 | #define AI_ERRLOGFLAGS 0xa1c | ||
329 | #define AI_INTSTATUS 0xa00 | ||
330 | #define AI_CONFIG 0xe00 | ||
331 | #define AI_ITCR 0xf00 | ||
332 | #define AI_ITIPOOBA 0xf10 | ||
333 | #define AI_ITIPOOBB 0xf14 | ||
334 | #define AI_ITIPOOBC 0xf18 | ||
335 | #define AI_ITIPOOBD 0xf1c | ||
336 | #define AI_ITIPOOBAOUT 0xf30 | ||
337 | #define AI_ITIPOOBBOUT 0xf34 | ||
338 | #define AI_ITIPOOBCOUT 0xf38 | ||
339 | #define AI_ITIPOOBDOUT 0xf3c | ||
340 | #define AI_ITOPOOBA 0xf50 | ||
341 | #define AI_ITOPOOBB 0xf54 | ||
342 | #define AI_ITOPOOBC 0xf58 | ||
343 | #define AI_ITOPOOBD 0xf5c | ||
344 | #define AI_ITOPOOBAIN 0xf70 | ||
345 | #define AI_ITOPOOBBIN 0xf74 | ||
346 | #define AI_ITOPOOBCIN 0xf78 | ||
347 | #define AI_ITOPOOBDIN 0xf7c | ||
348 | #define AI_ITOPRESET 0xf90 | ||
349 | #define AI_PERIPHERIALID4 0xfd0 | ||
350 | #define AI_PERIPHERIALID5 0xfd4 | ||
351 | #define AI_PERIPHERIALID6 0xfd8 | ||
352 | #define AI_PERIPHERIALID7 0xfdc | ||
353 | #define AI_PERIPHERIALID0 0xfe0 | ||
354 | #define AI_PERIPHERIALID1 0xfe4 | ||
355 | #define AI_PERIPHERIALID2 0xfe8 | ||
356 | #define AI_PERIPHERIALID3 0xfec | ||
357 | #define AI_COMPONENTID0 0xff0 | ||
358 | #define AI_COMPONENTID1 0xff4 | ||
359 | #define AI_COMPONENTID2 0xff8 | ||
360 | #define AI_COMPONENTID3 0xffc | ||
361 | |||
362 | |||
363 | #define AIRC_RESET 1 | ||
364 | |||
365 | |||
366 | #define AICFG_OOB 0x00000020 | ||
367 | #define AICFG_IOS 0x00000010 | ||
368 | #define AICFG_IOC 0x00000008 | ||
369 | #define AICFG_TO 0x00000004 | ||
370 | #define AICFG_ERRL 0x00000002 | ||
371 | #define AICFG_RST 0x00000001 | ||
372 | |||
373 | |||
374 | #define OOB_SEL_OUTEN_B_5 15 | ||
375 | #define OOB_SEL_OUTEN_B_6 23 | ||
376 | |||
377 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmcdc.h b/drivers/net/wireless/bcmdhd/include/bcmcdc.h new file mode 100644 index 00000000000..ce45c50d964 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmcdc.h | |||
@@ -0,0 +1,121 @@ | |||
1 | /* | ||
2 | * CDC network driver ioctl/indication encoding | ||
3 | * Broadcom 802.11abg Networking Device Driver | ||
4 | * | ||
5 | * Definitions subject to change without notice. | ||
6 | * | ||
7 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
8 | * | ||
9 | * Unless you and Broadcom execute a separate written software license | ||
10 | * agreement governing use of this software, this software is licensed to you | ||
11 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
12 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
13 | * following added to such license: | ||
14 | * | ||
15 | * As a special exception, the copyright holders of this software give you | ||
16 | * permission to link this software with independent modules, and to copy and | ||
17 | * distribute the resulting executable under terms of your choice, provided that | ||
18 | * you also meet, for each linked independent module, the terms and conditions of | ||
19 | * the license of that module. An independent module is a module which is not | ||
20 | * derived from this software. The special exception does not apply to any | ||
21 | * modifications of the software. | ||
22 | * | ||
23 | * Notwithstanding the above, under no circumstances may you combine this | ||
24 | * software in any way with any other Broadcom software provided under a license | ||
25 | * other than the GPL, without Broadcom's express prior written consent. | ||
26 | * | ||
27 | * $Id: bcmcdc.h,v 13.25.10.3 2010-12-22 23:47:26 Exp $ | ||
28 | */ | ||
29 | |||
30 | #ifndef _bcmcdc_h_ | ||
31 | #define _bcmcdc_h_ | ||
32 | #include <proto/ethernet.h> | ||
33 | |||
34 | typedef struct cdc_ioctl { | ||
35 | uint32 cmd; | ||
36 | uint32 len; | ||
37 | uint32 flags; | ||
38 | uint32 status; | ||
39 | } cdc_ioctl_t; | ||
40 | |||
41 | |||
42 | #define CDC_MAX_MSG_SIZE ETHER_MAX_LEN | ||
43 | |||
44 | |||
45 | #define CDCL_IOC_OUTLEN_MASK 0x0000FFFF | ||
46 | |||
47 | #define CDCL_IOC_OUTLEN_SHIFT 0 | ||
48 | #define CDCL_IOC_INLEN_MASK 0xFFFF0000 | ||
49 | #define CDCL_IOC_INLEN_SHIFT 16 | ||
50 | |||
51 | |||
52 | #define CDCF_IOC_ERROR 0x01 | ||
53 | #define CDCF_IOC_SET 0x02 | ||
54 | #define CDCF_IOC_OVL_IDX_MASK 0x3c | ||
55 | #define CDCF_IOC_OVL_RSV 0x40 | ||
56 | #define CDCF_IOC_OVL 0x80 | ||
57 | #define CDCF_IOC_ACTION_MASK 0xfe | ||
58 | #define CDCF_IOC_ACTION_SHIFT 1 | ||
59 | #define CDCF_IOC_IF_MASK 0xF000 | ||
60 | #define CDCF_IOC_IF_SHIFT 12 | ||
61 | #define CDCF_IOC_ID_MASK 0xFFFF0000 | ||
62 | #define CDCF_IOC_ID_SHIFT 16 | ||
63 | |||
64 | #define CDC_IOC_IF_IDX(flags) (((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT) | ||
65 | #define CDC_IOC_ID(flags) (((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT) | ||
66 | |||
67 | #define CDC_GET_IF_IDX(hdr) \ | ||
68 | ((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)) | ||
69 | #define CDC_SET_IF_IDX(hdr, idx) \ | ||
70 | ((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | ((idx) << CDCF_IOC_IF_SHIFT))) | ||
71 | |||
72 | |||
73 | |||
74 | #define BDC_HEADER_LEN 4 | ||
75 | |||
76 | #define BDC_PROTO_VER_1 1 | ||
77 | #define BDC_PROTO_VER 2 | ||
78 | |||
79 | #define BDC_FLAG_VER_MASK 0xf0 | ||
80 | #define BDC_FLAG_VER_SHIFT 4 | ||
81 | |||
82 | #define BDC_FLAG__UNUSED 0x03 | ||
83 | #define BDC_FLAG_SUM_GOOD 0x04 | ||
84 | #define BDC_FLAG_SUM_NEEDED 0x08 | ||
85 | |||
86 | #define BDC_PRIORITY_MASK 0x7 | ||
87 | |||
88 | #define BDC_FLAG2_FC_FLAG 0x10 | ||
89 | |||
90 | #define BDC_PRIORITY_FC_SHIFT 4 | ||
91 | |||
92 | #define BDC_FLAG2_IF_MASK 0x0f | ||
93 | #define BDC_FLAG2_IF_SHIFT 0 | ||
94 | #define BDC_FLAG2_PAD_MASK 0xf0 | ||
95 | #define BDC_FLAG_PAD_MASK 0x03 | ||
96 | #define BDC_FLAG2_PAD_SHIFT 2 | ||
97 | #define BDC_FLAG_PAD_SHIFT 0 | ||
98 | #define BDC_FLAG2_PAD_IDX 0x3c | ||
99 | #define BDC_FLAG_PAD_IDX 0x03 | ||
100 | #define BDC_GET_PAD_LEN(hdr) \ | ||
101 | ((int)(((((hdr)->flags2) & BDC_FLAG2_PAD_MASK) >> BDC_FLAG2_PAD_SHIFT) | \ | ||
102 | ((((hdr)->flags) & BDC_FLAG_PAD_MASK) >> BDC_FLAG_PAD_SHIFT))) | ||
103 | #define BDC_SET_PAD_LEN(hdr, idx) \ | ||
104 | ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_PAD_MASK) | \ | ||
105 | (((idx) & BDC_FLAG2_PAD_IDX) << BDC_FLAG2_PAD_SHIFT))); \ | ||
106 | ((hdr)->flags = (((hdr)->flags & ~BDC_FLAG_PAD_MASK) | \ | ||
107 | (((idx) & BDC_FLAG_PAD_IDX) << BDC_FLAG_PAD_SHIFT))) | ||
108 | |||
109 | #define BDC_GET_IF_IDX(hdr) \ | ||
110 | ((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT)) | ||
111 | #define BDC_SET_IF_IDX(hdr, idx) \ | ||
112 | ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | ((idx) << BDC_FLAG2_IF_SHIFT))) | ||
113 | |||
114 | struct bdc_header { | ||
115 | uint8 flags; | ||
116 | uint8 priority; | ||
117 | uint8 flags2; | ||
118 | uint8 dataOffset; | ||
119 | }; | ||
120 | |||
121 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmdefs.h b/drivers/net/wireless/bcmdhd/include/bcmdefs.h new file mode 100644 index 00000000000..da1fd5e4eac --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmdefs.h | |||
@@ -0,0 +1,196 @@ | |||
1 | /* | ||
2 | * Misc system wide definitions | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmdefs.h,v 13.68.2.8 2011-01-08 04:04:19 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _bcmdefs_h_ | ||
29 | #define _bcmdefs_h_ | ||
30 | |||
31 | |||
32 | |||
33 | #define bcmreclaimed 0 | ||
34 | #define _data _data | ||
35 | #define _fn _fn | ||
36 | #define _data _data | ||
37 | #define _fn _fn | ||
38 | #define _fn _fn | ||
39 | #define CONST const | ||
40 | #define BCMFASTPATH | ||
41 | |||
42 | |||
43 | |||
44 | |||
45 | #define _data _data | ||
46 | #define _fn _fn | ||
47 | #define _fn _fn | ||
48 | #define STATIC static | ||
49 | |||
50 | |||
51 | #define SI_BUS 0 | ||
52 | #define PCI_BUS 1 | ||
53 | #define PCMCIA_BUS 2 | ||
54 | #define SDIO_BUS 3 | ||
55 | #define JTAG_BUS 4 | ||
56 | #define USB_BUS 5 | ||
57 | #define SPI_BUS 6 | ||
58 | #define RPC_BUS 7 | ||
59 | |||
60 | |||
61 | #ifdef BCMBUSTYPE | ||
62 | #define BUSTYPE(bus) (BCMBUSTYPE) | ||
63 | #else | ||
64 | #define BUSTYPE(bus) (bus) | ||
65 | #endif | ||
66 | |||
67 | |||
68 | #ifdef BCMCHIPTYPE | ||
69 | #define CHIPTYPE(bus) (BCMCHIPTYPE) | ||
70 | #else | ||
71 | #define CHIPTYPE(bus) (bus) | ||
72 | #endif | ||
73 | |||
74 | |||
75 | |||
76 | #if defined(BCMSPROMBUS) | ||
77 | #define SPROMBUS (BCMSPROMBUS) | ||
78 | #elif defined(SI_PCMCIA_SROM) | ||
79 | #define SPROMBUS (PCMCIA_BUS) | ||
80 | #else | ||
81 | #define SPROMBUS (PCI_BUS) | ||
82 | #endif | ||
83 | |||
84 | |||
85 | #ifdef BCMCHIPID | ||
86 | #define CHIPID(chip) (BCMCHIPID) | ||
87 | #else | ||
88 | #define CHIPID(chip) (chip) | ||
89 | #endif | ||
90 | |||
91 | #ifdef BCMCHIPREV | ||
92 | #define CHIPREV(rev) (BCMCHIPREV) | ||
93 | #else | ||
94 | #define CHIPREV(rev) (rev) | ||
95 | #endif | ||
96 | |||
97 | |||
98 | #define DMADDR_MASK_32 0x0 | ||
99 | #define DMADDR_MASK_30 0xc0000000 | ||
100 | #define DMADDR_MASK_0 0xffffffff | ||
101 | |||
102 | #define DMADDRWIDTH_30 30 | ||
103 | #define DMADDRWIDTH_32 32 | ||
104 | #define DMADDRWIDTH_63 63 | ||
105 | #define DMADDRWIDTH_64 64 | ||
106 | |||
107 | #ifdef BCMDMA64OSL | ||
108 | typedef struct { | ||
109 | uint32 loaddr; | ||
110 | uint32 hiaddr; | ||
111 | } dma64addr_t; | ||
112 | |||
113 | typedef dma64addr_t dmaaddr_t; | ||
114 | #define PHYSADDRHI(_pa) ((_pa).hiaddr) | ||
115 | #define PHYSADDRHISET(_pa, _val) \ | ||
116 | do { \ | ||
117 | (_pa).hiaddr = (_val); \ | ||
118 | } while (0) | ||
119 | #define PHYSADDRLO(_pa) ((_pa).loaddr) | ||
120 | #define PHYSADDRLOSET(_pa, _val) \ | ||
121 | do { \ | ||
122 | (_pa).loaddr = (_val); \ | ||
123 | } while (0) | ||
124 | |||
125 | #else | ||
126 | typedef unsigned long dmaaddr_t; | ||
127 | #define PHYSADDRHI(_pa) (0) | ||
128 | #define PHYSADDRHISET(_pa, _val) | ||
129 | #define PHYSADDRLO(_pa) ((_pa)) | ||
130 | #define PHYSADDRLOSET(_pa, _val) \ | ||
131 | do { \ | ||
132 | (_pa) = (_val); \ | ||
133 | } while (0) | ||
134 | #endif | ||
135 | |||
136 | |||
137 | typedef struct { | ||
138 | dmaaddr_t addr; | ||
139 | uint32 length; | ||
140 | } hnddma_seg_t; | ||
141 | |||
142 | #define MAX_DMA_SEGS 4 | ||
143 | |||
144 | |||
145 | typedef struct { | ||
146 | void *oshdmah; | ||
147 | uint origsize; | ||
148 | uint nsegs; | ||
149 | hnddma_seg_t segs[MAX_DMA_SEGS]; | ||
150 | } hnddma_seg_map_t; | ||
151 | |||
152 | |||
153 | |||
154 | |||
155 | #if defined(BCM_RPC_NOCOPY) || defined(BCM_RCP_TXNOCOPY) | ||
156 | |||
157 | #define BCMEXTRAHDROOM 220 | ||
158 | #else | ||
159 | #define BCMEXTRAHDROOM 172 | ||
160 | #endif | ||
161 | |||
162 | |||
163 | #define BCMDONGLEHDRSZ 12 | ||
164 | #define BCMDONGLEPADSZ 16 | ||
165 | |||
166 | #define BCMDONGLEOVERHEAD (BCMDONGLEHDRSZ + BCMDONGLEPADSZ) | ||
167 | |||
168 | |||
169 | #if defined(BCMASSERT_LOG) | ||
170 | #define BCMASSERT_SUPPORT | ||
171 | #endif | ||
172 | |||
173 | |||
174 | #define BITFIELD_MASK(width) \ | ||
175 | (((unsigned)1 << (width)) - 1) | ||
176 | #define GFIELD(val, field) \ | ||
177 | (((val) >> field ## _S) & field ## _M) | ||
178 | #define SFIELD(val, field, bits) \ | ||
179 | (((val) & (~(field ## _M << field ## _S))) | \ | ||
180 | ((unsigned)(bits) << field ## _S)) | ||
181 | |||
182 | |||
183 | #ifdef BCMSMALL | ||
184 | #undef BCMSPACE | ||
185 | #define bcmspace FALSE | ||
186 | #else | ||
187 | #define BCMSPACE | ||
188 | #define bcmspace TRUE | ||
189 | #endif | ||
190 | |||
191 | |||
192 | #define MAXSZ_NVRAM_VARS 4096 | ||
193 | |||
194 | #define LOCATOR_EXTERN static | ||
195 | |||
196 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmdevs.h b/drivers/net/wireless/bcmdhd/include/bcmdevs.h new file mode 100644 index 00000000000..4f707c0c692 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmdevs.h | |||
@@ -0,0 +1,182 @@ | |||
1 | /* | ||
2 | * Broadcom device-specific manifest constants. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmdevs.h,v 13.285.2.39 2011-02-04 05:03:16 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _BCMDEVS_H | ||
29 | #define _BCMDEVS_H | ||
30 | |||
31 | |||
32 | #define VENDOR_EPIGRAM 0xfeda | ||
33 | #define VENDOR_BROADCOM 0x14e4 | ||
34 | #define VENDOR_SI_IMAGE 0x1095 | ||
35 | #define VENDOR_TI 0x104c | ||
36 | #define VENDOR_RICOH 0x1180 | ||
37 | #define VENDOR_JMICRON 0x197b | ||
38 | |||
39 | |||
40 | |||
41 | #define VENDOR_BROADCOM_PCMCIA 0x02d0 | ||
42 | |||
43 | |||
44 | #define VENDOR_BROADCOM_SDIO 0x00BF | ||
45 | |||
46 | |||
47 | #define BCM_DNGL_VID 0x0a5c | ||
48 | #define BCM_DNGL_BL_PID_4328 0xbd12 | ||
49 | #define BCM_DNGL_BL_PID_4322 0xbd13 | ||
50 | #define BCM_DNGL_BL_PID_4319 0xbd16 | ||
51 | #define BCM_DNGL_BL_PID_43236 0xbd17 | ||
52 | #define BCM_DNGL_BL_PID_4332 0xbd18 | ||
53 | #define BCM_DNGL_BL_PID_4330 0xbd19 | ||
54 | #define BCM_DNGL_BL_PID_43239 0xbd1b | ||
55 | #define BCM_DNGL_BDC_PID 0x0bdc | ||
56 | #define BCM_DNGL_JTAG_PID 0x4a44 | ||
57 | #define BCM4325_D11DUAL_ID 0x431b | ||
58 | #define BCM4325_D11G_ID 0x431c | ||
59 | #define BCM4325_D11A_ID 0x431d | ||
60 | #define BCM4321_D11N_ID 0x4328 | ||
61 | #define BCM4321_D11N2G_ID 0x4329 | ||
62 | #define BCM4321_D11N5G_ID 0x432a | ||
63 | #define BCM4322_D11N_ID 0x432b | ||
64 | #define BCM4322_D11N2G_ID 0x432c | ||
65 | #define BCM4322_D11N5G_ID 0x432d | ||
66 | #define BCM4329_D11N_ID 0x432e | ||
67 | #define BCM4329_D11N2G_ID 0x432f | ||
68 | #define BCM4329_D11N5G_ID 0x4330 | ||
69 | #define BCM4315_D11DUAL_ID 0x4334 | ||
70 | #define BCM4315_D11G_ID 0x4335 | ||
71 | #define BCM4315_D11A_ID 0x4336 | ||
72 | #define BCM4319_D11N_ID 0x4337 | ||
73 | #define BCM4319_D11N2G_ID 0x4338 | ||
74 | #define BCM4319_D11N5G_ID 0x4339 | ||
75 | #define BCM43231_D11N2G_ID 0x4340 | ||
76 | #define BCM43221_D11N2G_ID 0x4341 | ||
77 | #define BCM43222_D11N_ID 0x4350 | ||
78 | #define BCM43222_D11N2G_ID 0x4351 | ||
79 | #define BCM43222_D11N5G_ID 0x4352 | ||
80 | #define BCM43224_D11N_ID 0x4353 | ||
81 | #define BCM43224_D11N_ID_VEN1 0x0576 | ||
82 | #define BCM43226_D11N_ID 0x4354 | ||
83 | #define BCM43236_D11N_ID 0x4346 | ||
84 | #define BCM43236_D11N2G_ID 0x4347 | ||
85 | #define BCM43236_D11N5G_ID 0x4348 | ||
86 | #define BCM43225_D11N2G_ID 0x4357 | ||
87 | #define BCM43421_D11N_ID 0xA99D | ||
88 | #define BCM4313_D11N2G_ID 0x4727 | ||
89 | #define BCM4330_D11N_ID 0x4360 | ||
90 | #define BCM4330_D11N2G_ID 0x4361 | ||
91 | #define BCM4330_D11N5G_ID 0x4362 | ||
92 | #define BCM4336_D11N_ID 0x4343 | ||
93 | #define BCM6362_D11N_ID 0x435f | ||
94 | #define BCM4331_D11N_ID 0x4331 | ||
95 | #define BCM4331_D11N2G_ID 0x4332 | ||
96 | #define BCM4331_D11N5G_ID 0x4333 | ||
97 | #define BCM43237_D11N_ID 0x4355 | ||
98 | #define BCM43237_D11N5G_ID 0x4356 | ||
99 | #define BCM43227_D11N2G_ID 0x4358 | ||
100 | #define BCM43228_D11N_ID 0x4359 | ||
101 | #define BCM43228_D11N5G_ID 0x435a | ||
102 | #define BCM43362_D11N_ID 0x4363 | ||
103 | #define BCM43239_D11N_ID 0x4370 | ||
104 | |||
105 | |||
106 | #define SDIOH_FPGA_ID 0x43f2 | ||
107 | #define SPIH_FPGA_ID 0x43f5 | ||
108 | #define BCM4710_DEVICE_ID 0x4710 | ||
109 | #define BCM27XX_SDIOH_ID 0x2702 | ||
110 | #define PCIXX21_FLASHMEDIA0_ID 0x8033 | ||
111 | #define PCIXX21_SDIOH0_ID 0x8034 | ||
112 | #define PCIXX21_FLASHMEDIA_ID 0x803b | ||
113 | #define PCIXX21_SDIOH_ID 0x803c | ||
114 | #define R5C822_SDIOH_ID 0x0822 | ||
115 | #define JMICRON_SDIOH_ID 0x2381 | ||
116 | |||
117 | |||
118 | #define BCM4306_CHIP_ID 0x4306 | ||
119 | #define BCM4311_CHIP_ID 0x4311 | ||
120 | #define BCM43111_CHIP_ID 43111 | ||
121 | #define BCM43112_CHIP_ID 43112 | ||
122 | #define BCM4312_CHIP_ID 0x4312 | ||
123 | #define BCM4313_CHIP_ID 0x4313 | ||
124 | #define BCM4315_CHIP_ID 0x4315 | ||
125 | #define BCM4318_CHIP_ID 0x4318 | ||
126 | #define BCM4319_CHIP_ID 0x4319 | ||
127 | #define BCM4320_CHIP_ID 0x4320 | ||
128 | #define BCM4321_CHIP_ID 0x4321 | ||
129 | #define BCM4322_CHIP_ID 0x4322 | ||
130 | #define BCM43221_CHIP_ID 43221 | ||
131 | #define BCM43222_CHIP_ID 43222 | ||
132 | #define BCM43224_CHIP_ID 43224 | ||
133 | #define BCM43225_CHIP_ID 43225 | ||
134 | #define BCM43227_CHIP_ID 43227 | ||
135 | #define BCM43228_CHIP_ID 43228 | ||
136 | #define BCM43226_CHIP_ID 43226 | ||
137 | #define BCM43231_CHIP_ID 43231 | ||
138 | #define BCM43234_CHIP_ID 43234 | ||
139 | #define BCM43235_CHIP_ID 43235 | ||
140 | #define BCM43236_CHIP_ID 43236 | ||
141 | #define BCM43237_CHIP_ID 43237 | ||
142 | #define BCM43238_CHIP_ID 43238 | ||
143 | #define BCM43239_CHIP_ID 43239 | ||
144 | #define BCM43420_CHIP_ID 43420 | ||
145 | #define BCM43421_CHIP_ID 43421 | ||
146 | #define BCM43428_CHIP_ID 43428 | ||
147 | #define BCM43431_CHIP_ID 43431 | ||
148 | #define BCM4325_CHIP_ID 0x4325 | ||
149 | #define BCM4328_CHIP_ID 0x4328 | ||
150 | #define BCM4329_CHIP_ID 0x4329 | ||
151 | #define BCM4331_CHIP_ID 0x4331 | ||
152 | #define BCM4336_CHIP_ID 0x4336 | ||
153 | #define BCM43362_CHIP_ID 43362 | ||
154 | #define BCM4330_CHIP_ID 0x4330 | ||
155 | #define BCM4402_CHIP_ID 0x4402 | ||
156 | #define BCM4704_CHIP_ID 0x4704 | ||
157 | #define BCM4710_CHIP_ID 0x4710 | ||
158 | #define BCM4712_CHIP_ID 0x4712 | ||
159 | #define BCM4785_CHIP_ID 0x4785 | ||
160 | #define BCM5350_CHIP_ID 0x5350 | ||
161 | #define BCM5352_CHIP_ID 0x5352 | ||
162 | #define BCM5354_CHIP_ID 0x5354 | ||
163 | #define BCM5365_CHIP_ID 0x5365 | ||
164 | |||
165 | |||
166 | #define BCM4303_PKG_ID 2 | ||
167 | #define BCM4309_PKG_ID 1 | ||
168 | #define BCM4712LARGE_PKG_ID 0 | ||
169 | #define BCM4712SMALL_PKG_ID 1 | ||
170 | #define BCM4712MID_PKG_ID 2 | ||
171 | #define BCM4328USBD11G_PKG_ID 2 | ||
172 | #define BCM4328USBDUAL_PKG_ID 3 | ||
173 | #define BCM4328SDIOD11G_PKG_ID 4 | ||
174 | #define BCM4328SDIODUAL_PKG_ID 5 | ||
175 | #define BCM4329_289PIN_PKG_ID 0 | ||
176 | #define BCM4329_182PIN_PKG_ID 1 | ||
177 | #define BCM5354E_PKG_ID 1 | ||
178 | #define HDLSIM5350_PKG_ID 1 | ||
179 | #define HDLSIM_PKG_ID 14 | ||
180 | #define HWSIM_PKG_ID 15 | ||
181 | |||
182 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmendian.h b/drivers/net/wireless/bcmdhd/include/bcmendian.h new file mode 100644 index 00000000000..04b07ecb804 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmendian.h | |||
@@ -0,0 +1,279 @@ | |||
1 | /* | ||
2 | * Byte order utilities | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmendian.h,v 1.36 2009-11-09 05:29:43 Exp $ | ||
25 | * | ||
26 | * This file by default provides proper behavior on little-endian architectures. | ||
27 | * On big-endian architectures, IL_BIGENDIAN should be defined. | ||
28 | */ | ||
29 | |||
30 | |||
31 | #ifndef _BCMENDIAN_H_ | ||
32 | #define _BCMENDIAN_H_ | ||
33 | |||
34 | #include <typedefs.h> | ||
35 | |||
36 | |||
37 | #define BCMSWAP16(val) \ | ||
38 | ((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \ | ||
39 | (((uint16)(val) & (uint16)0xff00U) >> 8))) | ||
40 | |||
41 | |||
42 | #define BCMSWAP32(val) \ | ||
43 | ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \ | ||
44 | (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \ | ||
45 | (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \ | ||
46 | (((uint32)(val) & (uint32)0xff000000U) >> 24))) | ||
47 | |||
48 | |||
49 | #define BCMSWAP32BY16(val) \ | ||
50 | ((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \ | ||
51 | (((uint32)(val) & (uint32)0xffff0000U) >> 16))) | ||
52 | |||
53 | |||
54 | #ifndef hton16 | ||
55 | #define HTON16(i) BCMSWAP16(i) | ||
56 | #define hton16(i) bcmswap16(i) | ||
57 | #define HTON32(i) BCMSWAP32(i) | ||
58 | #define hton32(i) bcmswap32(i) | ||
59 | #define NTOH16(i) BCMSWAP16(i) | ||
60 | #define ntoh16(i) bcmswap16(i) | ||
61 | #define NTOH32(i) BCMSWAP32(i) | ||
62 | #define ntoh32(i) bcmswap32(i) | ||
63 | #define LTOH16(i) (i) | ||
64 | #define ltoh16(i) (i) | ||
65 | #define LTOH32(i) (i) | ||
66 | #define ltoh32(i) (i) | ||
67 | #define HTOL16(i) (i) | ||
68 | #define htol16(i) (i) | ||
69 | #define HTOL32(i) (i) | ||
70 | #define htol32(i) (i) | ||
71 | #endif | ||
72 | |||
73 | #define ltoh16_buf(buf, i) | ||
74 | #define htol16_buf(buf, i) | ||
75 | |||
76 | |||
77 | #define load32_ua(a) ltoh32_ua(a) | ||
78 | #define store32_ua(a, v) htol32_ua_store(v, a) | ||
79 | #define load16_ua(a) ltoh16_ua(a) | ||
80 | #define store16_ua(a, v) htol16_ua_store(v, a) | ||
81 | |||
82 | #define _LTOH16_UA(cp) ((cp)[0] | ((cp)[1] << 8)) | ||
83 | #define _LTOH32_UA(cp) ((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24)) | ||
84 | #define _NTOH16_UA(cp) (((cp)[0] << 8) | (cp)[1]) | ||
85 | #define _NTOH32_UA(cp) (((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3]) | ||
86 | |||
87 | #define ltoh_ua(ptr) \ | ||
88 | (sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \ | ||
89 | sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)(ptr)) : \ | ||
90 | sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \ | ||
91 | *(uint8 *)0) | ||
92 | |||
93 | #define ntoh_ua(ptr) \ | ||
94 | (sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \ | ||
95 | sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)(ptr)) : \ | ||
96 | sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \ | ||
97 | *(uint8 *)0) | ||
98 | |||
99 | #ifdef __GNUC__ | ||
100 | |||
101 | |||
102 | |||
103 | #define bcmswap16(val) ({ \ | ||
104 | uint16 _val = (val); \ | ||
105 | BCMSWAP16(_val); \ | ||
106 | }) | ||
107 | |||
108 | #define bcmswap32(val) ({ \ | ||
109 | uint32 _val = (val); \ | ||
110 | BCMSWAP32(_val); \ | ||
111 | }) | ||
112 | |||
113 | #define bcmswap32by16(val) ({ \ | ||
114 | uint32 _val = (val); \ | ||
115 | BCMSWAP32BY16(_val); \ | ||
116 | }) | ||
117 | |||
118 | #define bcmswap16_buf(buf, len) ({ \ | ||
119 | uint16 *_buf = (uint16 *)(buf); \ | ||
120 | uint _wds = (len) / 2; \ | ||
121 | while (_wds--) { \ | ||
122 | *_buf = bcmswap16(*_buf); \ | ||
123 | _buf++; \ | ||
124 | } \ | ||
125 | }) | ||
126 | |||
127 | #define htol16_ua_store(val, bytes) ({ \ | ||
128 | uint16 _val = (val); \ | ||
129 | uint8 *_bytes = (uint8 *)(bytes); \ | ||
130 | _bytes[0] = _val & 0xff; \ | ||
131 | _bytes[1] = _val >> 8; \ | ||
132 | }) | ||
133 | |||
134 | #define htol32_ua_store(val, bytes) ({ \ | ||
135 | uint32 _val = (val); \ | ||
136 | uint8 *_bytes = (uint8 *)(bytes); \ | ||
137 | _bytes[0] = _val & 0xff; \ | ||
138 | _bytes[1] = (_val >> 8) & 0xff; \ | ||
139 | _bytes[2] = (_val >> 16) & 0xff; \ | ||
140 | _bytes[3] = _val >> 24; \ | ||
141 | }) | ||
142 | |||
143 | #define hton16_ua_store(val, bytes) ({ \ | ||
144 | uint16 _val = (val); \ | ||
145 | uint8 *_bytes = (uint8 *)(bytes); \ | ||
146 | _bytes[0] = _val >> 8; \ | ||
147 | _bytes[1] = _val & 0xff; \ | ||
148 | }) | ||
149 | |||
150 | #define hton32_ua_store(val, bytes) ({ \ | ||
151 | uint32 _val = (val); \ | ||
152 | uint8 *_bytes = (uint8 *)(bytes); \ | ||
153 | _bytes[0] = _val >> 24; \ | ||
154 | _bytes[1] = (_val >> 16) & 0xff; \ | ||
155 | _bytes[2] = (_val >> 8) & 0xff; \ | ||
156 | _bytes[3] = _val & 0xff; \ | ||
157 | }) | ||
158 | |||
159 | #define ltoh16_ua(bytes) ({ \ | ||
160 | const uint8 *_bytes = (const uint8 *)(bytes); \ | ||
161 | _LTOH16_UA(_bytes); \ | ||
162 | }) | ||
163 | |||
164 | #define ltoh32_ua(bytes) ({ \ | ||
165 | const uint8 *_bytes = (const uint8 *)(bytes); \ | ||
166 | _LTOH32_UA(_bytes); \ | ||
167 | }) | ||
168 | |||
169 | #define ntoh16_ua(bytes) ({ \ | ||
170 | const uint8 *_bytes = (const uint8 *)(bytes); \ | ||
171 | _NTOH16_UA(_bytes); \ | ||
172 | }) | ||
173 | |||
174 | #define ntoh32_ua(bytes) ({ \ | ||
175 | const uint8 *_bytes = (const uint8 *)(bytes); \ | ||
176 | _NTOH32_UA(_bytes); \ | ||
177 | }) | ||
178 | |||
179 | #else | ||
180 | |||
181 | |||
182 | static INLINE uint16 | ||
183 | bcmswap16(uint16 val) | ||
184 | { | ||
185 | return BCMSWAP16(val); | ||
186 | } | ||
187 | |||
188 | static INLINE uint32 | ||
189 | bcmswap32(uint32 val) | ||
190 | { | ||
191 | return BCMSWAP32(val); | ||
192 | } | ||
193 | |||
194 | static INLINE uint32 | ||
195 | bcmswap32by16(uint32 val) | ||
196 | { | ||
197 | return BCMSWAP32BY16(val); | ||
198 | } | ||
199 | |||
200 | |||
201 | |||
202 | |||
203 | static INLINE void | ||
204 | bcmswap16_buf(uint16 *buf, uint len) | ||
205 | { | ||
206 | len = len / 2; | ||
207 | |||
208 | while (len--) { | ||
209 | *buf = bcmswap16(*buf); | ||
210 | buf++; | ||
211 | } | ||
212 | } | ||
213 | |||
214 | |||
215 | static INLINE void | ||
216 | htol16_ua_store(uint16 val, uint8 *bytes) | ||
217 | { | ||
218 | bytes[0] = val & 0xff; | ||
219 | bytes[1] = val >> 8; | ||
220 | } | ||
221 | |||
222 | |||
223 | static INLINE void | ||
224 | htol32_ua_store(uint32 val, uint8 *bytes) | ||
225 | { | ||
226 | bytes[0] = val & 0xff; | ||
227 | bytes[1] = (val >> 8) & 0xff; | ||
228 | bytes[2] = (val >> 16) & 0xff; | ||
229 | bytes[3] = val >> 24; | ||
230 | } | ||
231 | |||
232 | |||
233 | static INLINE void | ||
234 | hton16_ua_store(uint16 val, uint8 *bytes) | ||
235 | { | ||
236 | bytes[0] = val >> 8; | ||
237 | bytes[1] = val & 0xff; | ||
238 | } | ||
239 | |||
240 | |||
241 | static INLINE void | ||
242 | hton32_ua_store(uint32 val, uint8 *bytes) | ||
243 | { | ||
244 | bytes[0] = val >> 24; | ||
245 | bytes[1] = (val >> 16) & 0xff; | ||
246 | bytes[2] = (val >> 8) & 0xff; | ||
247 | bytes[3] = val & 0xff; | ||
248 | } | ||
249 | |||
250 | |||
251 | static INLINE uint16 | ||
252 | ltoh16_ua(const void *bytes) | ||
253 | { | ||
254 | return _LTOH16_UA((const uint8 *)bytes); | ||
255 | } | ||
256 | |||
257 | |||
258 | static INLINE uint32 | ||
259 | ltoh32_ua(const void *bytes) | ||
260 | { | ||
261 | return _LTOH32_UA((const uint8 *)bytes); | ||
262 | } | ||
263 | |||
264 | |||
265 | static INLINE uint16 | ||
266 | ntoh16_ua(const void *bytes) | ||
267 | { | ||
268 | return _NTOH16_UA((const uint8 *)bytes); | ||
269 | } | ||
270 | |||
271 | |||
272 | static INLINE uint32 | ||
273 | ntoh32_ua(const void *bytes) | ||
274 | { | ||
275 | return _NTOH32_UA((const uint8 *)bytes); | ||
276 | } | ||
277 | |||
278 | #endif | ||
279 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmpcispi.h b/drivers/net/wireless/bcmdhd/include/bcmpcispi.h new file mode 100644 index 00000000000..fd148c591d8 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmpcispi.h | |||
@@ -0,0 +1,181 @@ | |||
1 | /* | ||
2 | * Broadcom PCI-SPI Host Controller Register Definitions | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmpcispi.h,v 13.15.112.1 2010-11-15 18:22:12 Exp $ | ||
25 | */ | ||
26 | #ifndef _BCM_PCI_SPI_H | ||
27 | #define _BCM_PCI_SPI_H | ||
28 | |||
29 | /* cpp contortions to concatenate w/arg prescan */ | ||
30 | #ifndef PAD | ||
31 | #define _PADLINE(line) pad ## line | ||
32 | #define _XSTR(line) _PADLINE(line) | ||
33 | #define PAD _XSTR(__LINE__) | ||
34 | #endif /* PAD */ | ||
35 | |||
36 | |||
37 | typedef volatile struct { | ||
38 | uint32 spih_ctrl; /* 0x00 SPI Control Register */ | ||
39 | uint32 spih_stat; /* 0x04 SPI Status Register */ | ||
40 | uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */ | ||
41 | uint32 spih_ext; /* 0x0C SPI Extension Register */ | ||
42 | uint32 PAD[4]; /* 0x10-0x1F PADDING */ | ||
43 | |||
44 | uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */ | ||
45 | uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */ | ||
46 | uint32 PAD[6]; /* 0x28-0x3F PADDING */ | ||
47 | |||
48 | uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */ | ||
49 | uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */ | ||
50 | /* 1=Active High) */ | ||
51 | uint32 spih_int_mask; /* 0x48 SPI Interrupt Mask */ | ||
52 | uint32 spih_int_status; /* 0x4C SPI Interrupt Status */ | ||
53 | uint32 PAD[4]; /* 0x50-0x5F PADDING */ | ||
54 | |||
55 | uint32 spih_hex_disp; /* 0x60 SPI 4-digit hex display value */ | ||
56 | uint32 spih_current_ma; /* 0x64 SPI SD card current consumption in mA */ | ||
57 | uint32 PAD[1]; /* 0x68 PADDING */ | ||
58 | uint32 spih_disp_sel; /* 0x6c SPI 4-digit hex display mode select (1=current) */ | ||
59 | uint32 PAD[4]; /* 0x70-0x7F PADDING */ | ||
60 | uint32 PAD[8]; /* 0x80-0x9F PADDING */ | ||
61 | uint32 PAD[8]; /* 0xA0-0xBF PADDING */ | ||
62 | uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */ | ||
63 | uint32 spih_pll_status; /* 0xC4 PLL Status Register */ | ||
64 | uint32 spih_xtal_freq; /* 0xC8 External Clock Frequency in units of 10000Hz */ | ||
65 | uint32 spih_clk_count; /* 0xCC External Clock Count Register */ | ||
66 | |||
67 | } spih_regs_t; | ||
68 | |||
69 | typedef volatile struct { | ||
70 | uint32 cfg_space[0x40]; /* 0x000-0x0FF PCI Configuration Space (Read Only) */ | ||
71 | uint32 P_IMG_CTRL0; /* 0x100 PCI Image0 Control Register */ | ||
72 | |||
73 | uint32 P_BA0; /* 0x104 32 R/W PCI Image0 Base Address register */ | ||
74 | uint32 P_AM0; /* 0x108 32 R/W PCI Image0 Address Mask register */ | ||
75 | uint32 P_TA0; /* 0x10C 32 R/W PCI Image0 Translation Address register */ | ||
76 | uint32 P_IMG_CTRL1; /* 0x110 32 R/W PCI Image1 Control register */ | ||
77 | uint32 P_BA1; /* 0x114 32 R/W PCI Image1 Base Address register */ | ||
78 | uint32 P_AM1; /* 0x118 32 R/W PCI Image1 Address Mask register */ | ||
79 | uint32 P_TA1; /* 0x11C 32 R/W PCI Image1 Translation Address register */ | ||
80 | uint32 P_IMG_CTRL2; /* 0x120 32 R/W PCI Image2 Control register */ | ||
81 | uint32 P_BA2; /* 0x124 32 R/W PCI Image2 Base Address register */ | ||
82 | uint32 P_AM2; /* 0x128 32 R/W PCI Image2 Address Mask register */ | ||
83 | uint32 P_TA2; /* 0x12C 32 R/W PCI Image2 Translation Address register */ | ||
84 | uint32 P_IMG_CTRL3; /* 0x130 32 R/W PCI Image3 Control register */ | ||
85 | uint32 P_BA3; /* 0x134 32 R/W PCI Image3 Base Address register */ | ||
86 | uint32 P_AM3; /* 0x138 32 R/W PCI Image3 Address Mask register */ | ||
87 | uint32 P_TA3; /* 0x13C 32 R/W PCI Image3 Translation Address register */ | ||
88 | uint32 P_IMG_CTRL4; /* 0x140 32 R/W PCI Image4 Control register */ | ||
89 | uint32 P_BA4; /* 0x144 32 R/W PCI Image4 Base Address register */ | ||
90 | uint32 P_AM4; /* 0x148 32 R/W PCI Image4 Address Mask register */ | ||
91 | uint32 P_TA4; /* 0x14C 32 R/W PCI Image4 Translation Address register */ | ||
92 | uint32 P_IMG_CTRL5; /* 0x150 32 R/W PCI Image5 Control register */ | ||
93 | uint32 P_BA5; /* 0x154 32 R/W PCI Image5 Base Address register */ | ||
94 | uint32 P_AM5; /* 0x158 32 R/W PCI Image5 Address Mask register */ | ||
95 | uint32 P_TA5; /* 0x15C 32 R/W PCI Image5 Translation Address register */ | ||
96 | uint32 P_ERR_CS; /* 0x160 32 R/W PCI Error Control and Status register */ | ||
97 | uint32 P_ERR_ADDR; /* 0x164 32 R PCI Erroneous Address register */ | ||
98 | uint32 P_ERR_DATA; /* 0x168 32 R PCI Erroneous Data register */ | ||
99 | |||
100 | uint32 PAD[5]; /* 0x16C-0x17F PADDING */ | ||
101 | |||
102 | uint32 WB_CONF_SPC_BAR; /* 0x180 32 R WISHBONE Configuration Space Base Address */ | ||
103 | uint32 W_IMG_CTRL1; /* 0x184 32 R/W WISHBONE Image1 Control register */ | ||
104 | uint32 W_BA1; /* 0x188 32 R/W WISHBONE Image1 Base Address register */ | ||
105 | uint32 W_AM1; /* 0x18C 32 R/W WISHBONE Image1 Address Mask register */ | ||
106 | uint32 W_TA1; /* 0x190 32 R/W WISHBONE Image1 Translation Address reg */ | ||
107 | uint32 W_IMG_CTRL2; /* 0x194 32 R/W WISHBONE Image2 Control register */ | ||
108 | uint32 W_BA2; /* 0x198 32 R/W WISHBONE Image2 Base Address register */ | ||
109 | uint32 W_AM2; /* 0x19C 32 R/W WISHBONE Image2 Address Mask register */ | ||
110 | uint32 W_TA2; /* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */ | ||
111 | uint32 W_IMG_CTRL3; /* 0x1A4 32 R/W WISHBONE Image3 Control register */ | ||
112 | uint32 W_BA3; /* 0x1A8 32 R/W WISHBONE Image3 Base Address register */ | ||
113 | uint32 W_AM3; /* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */ | ||
114 | uint32 W_TA3; /* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */ | ||
115 | uint32 W_IMG_CTRL4; /* 0x1B4 32 R/W WISHBONE Image4 Control register */ | ||
116 | uint32 W_BA4; /* 0x1B8 32 R/W WISHBONE Image4 Base Address register */ | ||
117 | uint32 W_AM4; /* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */ | ||
118 | uint32 W_TA4; /* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */ | ||
119 | uint32 W_IMG_CTRL5; /* 0x1C4 32 R/W WISHBONE Image5 Control register */ | ||
120 | uint32 W_BA5; /* 0x1C8 32 R/W WISHBONE Image5 Base Address register */ | ||
121 | uint32 W_AM5; /* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */ | ||
122 | uint32 W_TA5; /* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */ | ||
123 | uint32 W_ERR_CS; /* 0x1D4 32 R/W WISHBONE Error Control and Status reg */ | ||
124 | uint32 W_ERR_ADDR; /* 0x1D8 32 R WISHBONE Erroneous Address register */ | ||
125 | uint32 W_ERR_DATA; /* 0x1DC 32 R WISHBONE Erroneous Data register */ | ||
126 | uint32 CNF_ADDR; /* 0x1E0 32 R/W Configuration Cycle register */ | ||
127 | uint32 CNF_DATA; /* 0x1E4 32 R/W Configuration Cycle Generation Data reg */ | ||
128 | |||
129 | uint32 INT_ACK; /* 0x1E8 32 R Interrupt Acknowledge register */ | ||
130 | uint32 ICR; /* 0x1EC 32 R/W Interrupt Control register */ | ||
131 | uint32 ISR; /* 0x1F0 32 R/W Interrupt Status register */ | ||
132 | } spih_pciregs_t; | ||
133 | |||
134 | /* | ||
135 | * PCI Core interrupt enable and status bit definitions. | ||
136 | */ | ||
137 | |||
138 | /* PCI Core ICR Register bit definitions */ | ||
139 | #define PCI_INT_PROP_EN (1 << 0) /* Interrupt Propagation Enable */ | ||
140 | #define PCI_WB_ERR_INT_EN (1 << 1) /* Wishbone Error Interrupt Enable */ | ||
141 | #define PCI_PCI_ERR_INT_EN (1 << 2) /* PCI Error Interrupt Enable */ | ||
142 | #define PCI_PAR_ERR_INT_EN (1 << 3) /* Parity Error Interrupt Enable */ | ||
143 | #define PCI_SYS_ERR_INT_EN (1 << 4) /* System Error Interrupt Enable */ | ||
144 | #define PCI_SOFTWARE_RESET (1U << 31) /* Software reset of the PCI Core. */ | ||
145 | |||
146 | |||
147 | /* PCI Core ISR Register bit definitions */ | ||
148 | #define PCI_INT_PROP_ST (1 << 0) /* Interrupt Propagation Status */ | ||
149 | #define PCI_WB_ERR_INT_ST (1 << 1) /* Wishbone Error Interrupt Status */ | ||
150 | #define PCI_PCI_ERR_INT_ST (1 << 2) /* PCI Error Interrupt Status */ | ||
151 | #define PCI_PAR_ERR_INT_ST (1 << 3) /* Parity Error Interrupt Status */ | ||
152 | #define PCI_SYS_ERR_INT_ST (1 << 4) /* System Error Interrupt Status */ | ||
153 | |||
154 | |||
155 | /* Registers on the Wishbone bus */ | ||
156 | #define SPIH_CTLR_INTR (1 << 0) /* SPI Host Controller Core Interrupt */ | ||
157 | #define SPIH_DEV_INTR (1 << 1) /* SPI Device Interrupt */ | ||
158 | #define SPIH_WFIFO_INTR (1 << 2) /* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */ | ||
159 | |||
160 | /* GPIO Bit definitions */ | ||
161 | #define SPIH_CS (1 << 0) /* SPI Chip Select (active low) */ | ||
162 | #define SPIH_SLOT_POWER (1 << 1) /* SD Card Slot Power Enable */ | ||
163 | #define SPIH_CARD_DETECT (1 << 2) /* SD Card Detect */ | ||
164 | |||
165 | /* SPI Status Register Bit definitions */ | ||
166 | #define SPIH_STATE_MASK 0x30 /* SPI Transfer State Machine state mask */ | ||
167 | #define SPIH_STATE_SHIFT 4 /* SPI Transfer State Machine state shift */ | ||
168 | #define SPIH_WFFULL (1 << 3) /* SPI Write FIFO Full */ | ||
169 | #define SPIH_WFEMPTY (1 << 2) /* SPI Write FIFO Empty */ | ||
170 | #define SPIH_RFFULL (1 << 1) /* SPI Read FIFO Full */ | ||
171 | #define SPIH_RFEMPTY (1 << 0) /* SPI Read FIFO Empty */ | ||
172 | |||
173 | #define SPIH_EXT_CLK (1U << 31) /* Use External Clock as PLL Clock source. */ | ||
174 | |||
175 | #define SPIH_PLL_NO_CLK (1 << 1) /* Set to 1 if the PLL's input clock is lost. */ | ||
176 | #define SPIH_PLL_LOCKED (1 << 3) /* Set to 1 when the PLL is locked. */ | ||
177 | |||
178 | /* Spin bit loop bound check */ | ||
179 | #define SPI_SPIN_BOUND 0xf4240 /* 1 million */ | ||
180 | |||
181 | #endif /* _BCM_PCI_SPI_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmperf.h b/drivers/net/wireless/bcmdhd/include/bcmperf.h new file mode 100644 index 00000000000..a3985cf2937 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmperf.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * Performance counters software interface. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmperf.h,v 13.5 2007-09-14 22:00:59 Exp $ | ||
25 | */ | ||
26 | /* essai */ | ||
27 | #ifndef _BCMPERF_H_ | ||
28 | #define _BCMPERF_H_ | ||
29 | /* get cache hits and misses */ | ||
30 | #define BCMPERF_ENABLE_INSTRCOUNT() | ||
31 | #define BCMPERF_ENABLE_ICACHE_MISS() | ||
32 | #define BCMPERF_ENABLE_ICACHE_HIT() | ||
33 | #define BCMPERF_GETICACHE_MISS(x) ((x) = 0) | ||
34 | #define BCMPERF_GETICACHE_HIT(x) ((x) = 0) | ||
35 | #define BCMPERF_GETINSTRCOUNT(x) ((x) = 0) | ||
36 | #endif /* _BCMPERF_H_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdbus.h b/drivers/net/wireless/bcmdhd/include/bcmsdbus.h new file mode 100644 index 00000000000..5fda5e9b5df --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdbus.h | |||
@@ -0,0 +1,120 @@ | |||
1 | /* | ||
2 | * Definitions for API from sdio common code (bcmsdh) to individual | ||
3 | * host controller drivers. | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: bcmsdbus.h,v 13.17.86.2 2010-12-23 01:13:20 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _sdio_api_h_ | ||
29 | #define _sdio_api_h_ | ||
30 | |||
31 | |||
32 | #define SDIOH_API_RC_SUCCESS (0x00) | ||
33 | #define SDIOH_API_RC_FAIL (0x01) | ||
34 | #define SDIOH_API_SUCCESS(status) (status == 0) | ||
35 | |||
36 | #define SDIOH_READ 0 /* Read request */ | ||
37 | #define SDIOH_WRITE 1 /* Write request */ | ||
38 | |||
39 | #define SDIOH_DATA_FIX 0 /* Fixed addressing */ | ||
40 | #define SDIOH_DATA_INC 1 /* Incremental addressing */ | ||
41 | |||
42 | #define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */ | ||
43 | #define SDIOH_CMD_TYPE_APPEND 1 /* Append command */ | ||
44 | #define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */ | ||
45 | |||
46 | #define SDIOH_DATA_PIO 0 /* PIO mode */ | ||
47 | #define SDIOH_DATA_DMA 1 /* DMA mode */ | ||
48 | |||
49 | |||
50 | typedef int SDIOH_API_RC; | ||
51 | |||
52 | /* SDio Host structure */ | ||
53 | typedef struct sdioh_info sdioh_info_t; | ||
54 | |||
55 | /* callback function, taking one arg */ | ||
56 | typedef void (*sdioh_cb_fn_t)(void *); | ||
57 | |||
58 | /* attach, return handler on success, NULL if failed. | ||
59 | * The handler shall be provided by all subsequent calls. No local cache | ||
60 | * cfghdl points to the starting address of pci device mapped memory | ||
61 | */ | ||
62 | extern sdioh_info_t * sdioh_attach(osl_t *osh, void *cfghdl, uint irq); | ||
63 | extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *si); | ||
64 | extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, sdioh_cb_fn_t fn, void *argh); | ||
65 | extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si); | ||
66 | |||
67 | /* query whether SD interrupt is enabled or not */ | ||
68 | extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff); | ||
69 | |||
70 | /* enable or disable SD interrupt */ | ||
71 | extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable); | ||
72 | |||
73 | #if defined(DHD_DEBUG) | ||
74 | extern bool sdioh_interrupt_pending(sdioh_info_t *si); | ||
75 | #endif | ||
76 | |||
77 | /* read or write one byte using cmd52 */ | ||
78 | extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, uint addr, uint8 *byte); | ||
79 | |||
80 | /* read or write 2/4 bytes using cmd53 */ | ||
81 | extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, uint rw, uint fnc, | ||
82 | uint addr, uint32 *word, uint nbyte); | ||
83 | |||
84 | /* read or write any buffer using cmd53 */ | ||
85 | extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, uint fix_inc, | ||
86 | uint rw, uint fnc_num, uint32 addr, uint regwidth, uint32 buflen, uint8 *buffer, | ||
87 | void *pkt); | ||
88 | |||
89 | /* get cis data */ | ||
90 | extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, uint8 *cis, uint32 length); | ||
91 | |||
92 | extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data); | ||
93 | extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data); | ||
94 | |||
95 | /* query number of io functions */ | ||
96 | extern uint sdioh_query_iofnum(sdioh_info_t *si); | ||
97 | |||
98 | /* handle iovars */ | ||
99 | extern int sdioh_iovar_op(sdioh_info_t *si, const char *name, | ||
100 | void *params, int plen, void *arg, int len, bool set); | ||
101 | |||
102 | /* Issue abort to the specified function and clear controller as needed */ | ||
103 | extern int sdioh_abort(sdioh_info_t *si, uint fnc); | ||
104 | |||
105 | /* Start and Stop SDIO without re-enumerating the SD card. */ | ||
106 | extern int sdioh_start(sdioh_info_t *si, int stage); | ||
107 | extern int sdioh_stop(sdioh_info_t *si); | ||
108 | |||
109 | /* Wait system lock free */ | ||
110 | extern int sdioh_waitlockfree(sdioh_info_t *si); | ||
111 | |||
112 | /* Reset and re-initialize the device */ | ||
113 | extern int sdioh_sdio_reset(sdioh_info_t *si); | ||
114 | |||
115 | /* Helper function */ | ||
116 | void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh); | ||
117 | |||
118 | |||
119 | |||
120 | #endif /* _sdio_api_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdh.h b/drivers/net/wireless/bcmdhd/include/bcmsdh.h new file mode 100644 index 00000000000..4e3affde6b0 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdh.h | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * SDIO host client driver interface of Broadcom HNBU | ||
3 | * export functions to client drivers | ||
4 | * abstract OS and BUS specific details of SDIO | ||
5 | * | ||
6 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
7 | * | ||
8 | * Unless you and Broadcom execute a separate written software license | ||
9 | * agreement governing use of this software, this software is licensed to you | ||
10 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
11 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
12 | * following added to such license: | ||
13 | * | ||
14 | * As a special exception, the copyright holders of this software give you | ||
15 | * permission to link this software with independent modules, and to copy and | ||
16 | * distribute the resulting executable under terms of your choice, provided that | ||
17 | * you also meet, for each linked independent module, the terms and conditions of | ||
18 | * the license of that module. An independent module is a module which is not | ||
19 | * derived from this software. The special exception does not apply to any | ||
20 | * modifications of the software. | ||
21 | * | ||
22 | * Notwithstanding the above, under no circumstances may you combine this | ||
23 | * software in any way with any other Broadcom software provided under a license | ||
24 | * other than the GPL, without Broadcom's express prior written consent. | ||
25 | * | ||
26 | * $Id: bcmsdh.h,v 13.46.52.3 2010-10-19 00:41:44 Exp $ | ||
27 | */ | ||
28 | |||
29 | #ifndef _bcmsdh_h_ | ||
30 | #define _bcmsdh_h_ | ||
31 | |||
32 | #define BCMSDH_ERROR_VAL 0x0001 /* Error */ | ||
33 | #define BCMSDH_INFO_VAL 0x0002 /* Info */ | ||
34 | extern const uint bcmsdh_msglevel; | ||
35 | |||
36 | #define BCMSDH_ERROR(x) | ||
37 | #define BCMSDH_INFO(x) | ||
38 | |||
39 | /* forward declarations */ | ||
40 | typedef struct bcmsdh_info bcmsdh_info_t; | ||
41 | typedef void (*bcmsdh_cb_fn_t)(void *); | ||
42 | |||
43 | /* Attach and build an interface to the underlying SD host driver. | ||
44 | * - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh. | ||
45 | * - Returns the bcmsdh handle and virtual address base for register access. | ||
46 | * The returned handle should be used in all subsequent calls, but the bcmsh | ||
47 | * implementation may maintain a single "default" handle (e.g. the first or | ||
48 | * most recent one) to enable single-instance implementations to pass NULL. | ||
49 | */ | ||
50 | extern bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq); | ||
51 | |||
52 | /* Detach - freeup resources allocated in attach */ | ||
53 | extern int bcmsdh_detach(osl_t *osh, void *sdh); | ||
54 | |||
55 | /* Query if SD device interrupts are enabled */ | ||
56 | extern bool bcmsdh_intr_query(void *sdh); | ||
57 | |||
58 | /* Enable/disable SD interrupt */ | ||
59 | extern int bcmsdh_intr_enable(void *sdh); | ||
60 | extern int bcmsdh_intr_disable(void *sdh); | ||
61 | |||
62 | /* Register/deregister device interrupt handler. */ | ||
63 | extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh); | ||
64 | extern int bcmsdh_intr_dereg(void *sdh); | ||
65 | |||
66 | #if defined(DHD_DEBUG) | ||
67 | /* Query pending interrupt status from the host controller */ | ||
68 | extern bool bcmsdh_intr_pending(void *sdh); | ||
69 | #endif | ||
70 | |||
71 | #ifdef BCMLXSDMMC | ||
72 | extern int bcmsdh_claim_host_and_lock(void *sdh); | ||
73 | extern int bcmsdh_release_host_and_unlock(void *sdh); | ||
74 | #endif /* BCMLXSDMMC */ | ||
75 | |||
76 | /* Register a callback to be called if and when bcmsdh detects | ||
77 | * device removal. No-op in the case of non-removable/hardwired devices. | ||
78 | */ | ||
79 | extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh); | ||
80 | |||
81 | /* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface). | ||
82 | * fn: function number | ||
83 | * addr: unmodified SDIO-space address | ||
84 | * data: data byte to write | ||
85 | * err: pointer to error code (or NULL) | ||
86 | */ | ||
87 | extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err); | ||
88 | extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err); | ||
89 | |||
90 | /* Read/Write 4bytes from/to cfg space */ | ||
91 | extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err); | ||
92 | extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err); | ||
93 | |||
94 | /* Read CIS content for specified function. | ||
95 | * fn: function whose CIS is being requested (0 is common CIS) | ||
96 | * cis: pointer to memory location to place results | ||
97 | * length: number of bytes to read | ||
98 | * Internally, this routine uses the values from the cis base regs (0x9-0xB) | ||
99 | * to form an SDIO-space address to read the data from. | ||
100 | */ | ||
101 | extern int bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length); | ||
102 | |||
103 | /* Synchronous access to device (client) core registers via CMD53 to F1. | ||
104 | * addr: backplane address (i.e. >= regsva from attach) | ||
105 | * size: register width in bytes (2 or 4) | ||
106 | * data: data for register write | ||
107 | */ | ||
108 | extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size); | ||
109 | extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data); | ||
110 | |||
111 | /* Indicate if last reg read/write failed */ | ||
112 | extern bool bcmsdh_regfail(void *sdh); | ||
113 | |||
114 | /* Buffer transfer to/from device (client) core via cmd53. | ||
115 | * fn: function number | ||
116 | * addr: backplane address (i.e. >= regsva from attach) | ||
117 | * flags: backplane width, address increment, sync/async | ||
118 | * buf: pointer to memory data buffer | ||
119 | * nbytes: number of bytes to transfer to/from buf | ||
120 | * pkt: pointer to packet associated with buf (if any) | ||
121 | * complete: callback function for command completion (async only) | ||
122 | * handle: handle for completion callback (first arg in callback) | ||
123 | * Returns 0 or error code. | ||
124 | * NOTE: Async operation is not currently supported. | ||
125 | */ | ||
126 | typedef void (*bcmsdh_cmplt_fn_t)(void *handle, int status, bool sync_waiting); | ||
127 | extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, | ||
128 | uint8 *buf, uint nbytes, void *pkt, | ||
129 | bcmsdh_cmplt_fn_t complete, void *handle); | ||
130 | extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, | ||
131 | uint8 *buf, uint nbytes, void *pkt, | ||
132 | bcmsdh_cmplt_fn_t complete, void *handle); | ||
133 | |||
134 | /* Flags bits */ | ||
135 | #define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */ | ||
136 | #define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */ | ||
137 | #define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */ | ||
138 | |||
139 | /* Pending (non-error) return code */ | ||
140 | #define BCME_PENDING 1 | ||
141 | |||
142 | /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). | ||
143 | * rw: read or write (0/1) | ||
144 | * addr: direct SDIO address | ||
145 | * buf: pointer to memory data buffer | ||
146 | * nbytes: number of bytes to transfer to/from buf | ||
147 | * Returns 0 or error code. | ||
148 | */ | ||
149 | extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes); | ||
150 | |||
151 | /* Issue an abort to the specified function */ | ||
152 | extern int bcmsdh_abort(void *sdh, uint fn); | ||
153 | |||
154 | /* Start SDIO Host Controller communication */ | ||
155 | extern int bcmsdh_start(void *sdh, int stage); | ||
156 | |||
157 | /* Stop SDIO Host Controller communication */ | ||
158 | extern int bcmsdh_stop(void *sdh); | ||
159 | |||
160 | /* Wait system lock free */ | ||
161 | extern int bcmsdh_waitlockfree(void *sdh); | ||
162 | |||
163 | /* Returns the "Device ID" of target device on the SDIO bus. */ | ||
164 | extern int bcmsdh_query_device(void *sdh); | ||
165 | |||
166 | /* Returns the number of IO functions reported by the device */ | ||
167 | extern uint bcmsdh_query_iofnum(void *sdh); | ||
168 | |||
169 | /* Miscellaneous knob tweaker. */ | ||
170 | extern int bcmsdh_iovar_op(void *sdh, const char *name, | ||
171 | void *params, int plen, void *arg, int len, bool set); | ||
172 | |||
173 | /* Reset and reinitialize the device */ | ||
174 | extern int bcmsdh_reset(bcmsdh_info_t *sdh); | ||
175 | |||
176 | /* helper functions */ | ||
177 | |||
178 | extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh); | ||
179 | |||
180 | /* callback functions */ | ||
181 | typedef struct { | ||
182 | /* attach to device */ | ||
183 | void *(*attach)(uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot, | ||
184 | uint16 func, uint bustype, void * regsva, osl_t * osh, | ||
185 | void * param, void *dev); | ||
186 | /* detach from device */ | ||
187 | void (*detach)(void *ch); | ||
188 | } bcmsdh_driver_t; | ||
189 | |||
190 | /* platform specific/high level functions */ | ||
191 | extern int bcmsdh_register(bcmsdh_driver_t *driver); | ||
192 | extern void bcmsdh_unregister(void); | ||
193 | extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device); | ||
194 | extern void bcmsdh_device_remove(void * sdh); | ||
195 | |||
196 | #if defined(OOB_INTR_ONLY) | ||
197 | extern int bcmsdh_register_oob_intr(void * dhdp); | ||
198 | extern void bcmsdh_unregister_oob_intr(void); | ||
199 | extern void bcmsdh_oob_intr_set(bool enable); | ||
200 | #endif /* defined(OOB_INTR_ONLY) */ | ||
201 | /* Function to pass device-status bits to DHD. */ | ||
202 | extern uint32 bcmsdh_get_dstatus(void *sdh); | ||
203 | |||
204 | /* Function to return current window addr */ | ||
205 | extern uint32 bcmsdh_cur_sbwad(void *sdh); | ||
206 | |||
207 | /* Function to pass chipid and rev to lower layers for controlling pr's */ | ||
208 | extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev); | ||
209 | |||
210 | |||
211 | #endif /* _bcmsdh_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h b/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h new file mode 100644 index 00000000000..d188c4ec7d5 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h | |||
@@ -0,0 +1,122 @@ | |||
1 | /* | ||
2 | * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmsdh_sdmmc.h,v 13.5.88.1 2010-12-23 01:13:20 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef __BCMSDH_SDMMC_H__ | ||
28 | #define __BCMSDH_SDMMC_H__ | ||
29 | |||
30 | #define sd_err(x) | ||
31 | #define sd_trace(x) | ||
32 | #define sd_info(x) | ||
33 | #define sd_debug(x) | ||
34 | #define sd_data(x) | ||
35 | #define sd_ctrl(x) | ||
36 | |||
37 | #define sd_sync_dma(sd, read, nbytes) | ||
38 | #define sd_init_dma(sd) | ||
39 | #define sd_ack_intr(sd) | ||
40 | #define sd_wakeup(sd); | ||
41 | |||
42 | /* Allocate/init/free per-OS private data */ | ||
43 | extern int sdioh_sdmmc_osinit(sdioh_info_t *sd); | ||
44 | extern void sdioh_sdmmc_osfree(sdioh_info_t *sd); | ||
45 | |||
46 | #define sd_log(x) | ||
47 | |||
48 | #define SDIOH_ASSERT(exp) \ | ||
49 | do { if (!(exp)) \ | ||
50 | printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \ | ||
51 | } while (0) | ||
52 | |||
53 | #define BLOCK_SIZE_4318 64 | ||
54 | #define BLOCK_SIZE_4328 512 | ||
55 | |||
56 | /* internal return code */ | ||
57 | #define SUCCESS 0 | ||
58 | #define ERROR 1 | ||
59 | |||
60 | /* private bus modes */ | ||
61 | #define SDIOH_MODE_SD4 2 | ||
62 | #define CLIENT_INTR 0x100 /* Get rid of this! */ | ||
63 | |||
64 | struct sdioh_info { | ||
65 | osl_t *osh; /* osh handler */ | ||
66 | bool client_intr_enabled; /* interrupt connnected flag */ | ||
67 | bool intr_handler_valid; /* client driver interrupt handler valid */ | ||
68 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ | ||
69 | void *intr_handler_arg; /* argument to call interrupt handler */ | ||
70 | uint16 intmask; /* Current active interrupts */ | ||
71 | void *sdos_info; /* Pointer to per-OS private data */ | ||
72 | |||
73 | uint irq; /* Client irq */ | ||
74 | int intrcount; /* Client interrupts */ | ||
75 | |||
76 | bool sd_use_dma; /* DMA on CMD53 */ | ||
77 | bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ | ||
78 | /* Must be on for sd_multiblock to be effective */ | ||
79 | bool use_client_ints; /* If this is false, make sure to restore */ | ||
80 | int sd_mode; /* SD1/SD4/SPI */ | ||
81 | int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ | ||
82 | uint8 num_funcs; /* Supported funcs on client */ | ||
83 | uint32 com_cis_ptr; | ||
84 | uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; | ||
85 | uint max_dma_len; | ||
86 | uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */ | ||
87 | // SDDMA_DESCRIPTOR SGList[32]; /* Scatter/Gather DMA List */ | ||
88 | }; | ||
89 | |||
90 | /************************************************************ | ||
91 | * Internal interfaces: per-port references into bcmsdh_sdmmc.c | ||
92 | */ | ||
93 | |||
94 | /* Global message bits */ | ||
95 | extern uint sd_msglevel; | ||
96 | |||
97 | /* OS-independent interrupt handler */ | ||
98 | extern bool check_client_intr(sdioh_info_t *sd); | ||
99 | |||
100 | /* Core interrupt enable/disable of device interrupts */ | ||
101 | extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd); | ||
102 | extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd); | ||
103 | |||
104 | |||
105 | /************************************************************** | ||
106 | * Internal interfaces: bcmsdh_sdmmc.c references to per-port code | ||
107 | */ | ||
108 | |||
109 | /* Register mapping routines */ | ||
110 | extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size); | ||
111 | extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size); | ||
112 | |||
113 | /* Interrupt (de)registration routines */ | ||
114 | extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq); | ||
115 | extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd); | ||
116 | |||
117 | typedef struct _BCMSDH_SDMMC_INSTANCE { | ||
118 | sdioh_info_t *sd; | ||
119 | struct sdio_func *func[SDIOD_MAX_IOFUNCS]; | ||
120 | } BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE; | ||
121 | |||
122 | #endif /* __BCMSDH_SDMMC_H__ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h b/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h new file mode 100644 index 00000000000..ee29b5c08a5 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /* | ||
2 | * Broadcom SDIO/PCMCIA | ||
3 | * Software-specific definitions shared between device and host side | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: bcmsdpcm.h,v 13.4.90.2 2010-05-12 04:14:25 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _bcmsdpcm_h_ | ||
29 | #define _bcmsdpcm_h_ | ||
30 | |||
31 | /* | ||
32 | * Software allocation of To SB Mailbox resources | ||
33 | */ | ||
34 | |||
35 | /* intstatus bits */ | ||
36 | #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ | ||
37 | #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ | ||
38 | #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ | ||
39 | #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ | ||
40 | |||
41 | #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) | ||
42 | |||
43 | /* tosbmailbox bits corresponding to intstatus bits */ | ||
44 | #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ | ||
45 | #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ | ||
46 | #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ | ||
47 | #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ | ||
48 | #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ | ||
49 | |||
50 | /* tosbmailboxdata */ | ||
51 | #define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */ | ||
52 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */ | ||
53 | |||
54 | /* | ||
55 | * Software allocation of To Host Mailbox resources | ||
56 | */ | ||
57 | |||
58 | /* intstatus bits */ | ||
59 | #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ | ||
60 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ | ||
61 | #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ | ||
62 | #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ | ||
63 | |||
64 | #define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT) | ||
65 | |||
66 | /* tohostmailbox bits corresponding to intstatus bits */ | ||
67 | #define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */ | ||
68 | #define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */ | ||
69 | #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ | ||
70 | #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ | ||
71 | #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ | ||
72 | |||
73 | /* tohostmailboxdata */ | ||
74 | #define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */ | ||
75 | #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */ | ||
76 | #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ | ||
77 | #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ | ||
78 | #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ | ||
79 | |||
80 | #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ | ||
81 | #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ | ||
82 | |||
83 | #define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */ | ||
84 | #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */ | ||
85 | |||
86 | /* | ||
87 | * Software-defined protocol header | ||
88 | */ | ||
89 | |||
90 | /* Current protocol version */ | ||
91 | #define SDPCM_PROT_VERSION 4 | ||
92 | |||
93 | /* SW frame header */ | ||
94 | #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ | ||
95 | #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ | ||
96 | |||
97 | #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ | ||
98 | #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ | ||
99 | #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ | ||
100 | |||
101 | #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ | ||
102 | #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ | ||
103 | #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ | ||
104 | |||
105 | /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */ | ||
106 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ | ||
107 | #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ | ||
108 | #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ | ||
109 | #define SDPCM_NEXTLEN_OFFSET 2 | ||
110 | |||
111 | /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ | ||
112 | #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ | ||
113 | #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) | ||
114 | #define SDPCM_DOFFSET_MASK 0xff000000 | ||
115 | #define SDPCM_DOFFSET_SHIFT 24 | ||
116 | |||
117 | #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ | ||
118 | #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff) | ||
119 | #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ | ||
120 | #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) | ||
121 | #define SDPCM_VERSION_OFFSET 6 /* Version # */ | ||
122 | #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) | ||
123 | #define SDPCM_UNUSED_OFFSET 7 /* Spare */ | ||
124 | #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) | ||
125 | |||
126 | #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ | ||
127 | |||
128 | /* logical channel numbers */ | ||
129 | #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ | ||
130 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ | ||
131 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ | ||
132 | #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ | ||
133 | #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ | ||
134 | #define SDPCM_MAX_CHANNEL 15 | ||
135 | |||
136 | #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */ | ||
137 | |||
138 | #define SDPCM_FLAG_RESVD0 0x01 | ||
139 | #define SDPCM_FLAG_RESVD1 0x02 | ||
140 | #define SDPCM_FLAG_GSPI_TXENAB 0x04 | ||
141 | #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ | ||
142 | |||
143 | /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ | ||
144 | #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) | ||
145 | |||
146 | #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) | ||
147 | |||
148 | /* For TEST_CHANNEL packets, define another 4-byte header */ | ||
149 | #define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); | ||
150 | * Semantics of Ext byte depend on command. | ||
151 | * Len is current or requested frame length, not | ||
152 | * including test header; sent little-endian. | ||
153 | */ | ||
154 | #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ | ||
155 | #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ | ||
156 | #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ | ||
157 | #define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */ | ||
158 | #define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */ | ||
159 | |||
160 | /* Handy macro for filling in datagen packets with a pattern */ | ||
161 | #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) | ||
162 | |||
163 | /* | ||
164 | * Software counters (first part matches hardware counters) | ||
165 | */ | ||
166 | |||
167 | typedef volatile struct { | ||
168 | uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ | ||
169 | uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ | ||
170 | uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ | ||
171 | uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ | ||
172 | uint32 abort; /* AbortCount, SDIO: aborts */ | ||
173 | uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ | ||
174 | uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ | ||
175 | uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ | ||
176 | uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ | ||
177 | uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ | ||
178 | uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ | ||
179 | uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ | ||
180 | uint32 rxdescuflo; /* receive descriptor underflows */ | ||
181 | uint32 rxfifooflo; /* receive fifo overflows */ | ||
182 | uint32 txfifouflo; /* transmit fifo underflows */ | ||
183 | uint32 runt; /* runt (too short) frames recv'd from bus */ | ||
184 | uint32 badlen; /* frame's rxh len does not match its hw tag len */ | ||
185 | uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ | ||
186 | uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ | ||
187 | uint32 rxfcrc; /* frame rx header indicates crc error */ | ||
188 | uint32 rxfwoos; /* frame rx header indicates write out of sync */ | ||
189 | uint32 rxfwft; /* frame rx header indicates write frame termination */ | ||
190 | uint32 rxfabort; /* frame rx header indicates frame aborted */ | ||
191 | uint32 woosint; /* write out of sync interrupt */ | ||
192 | uint32 roosint; /* read out of sync interrupt */ | ||
193 | uint32 rftermint; /* read frame terminate interrupt */ | ||
194 | uint32 wftermint; /* write frame terminate interrupt */ | ||
195 | } sdpcmd_cnt_t; | ||
196 | |||
197 | /* | ||
198 | * Register Access Macros | ||
199 | */ | ||
200 | |||
201 | #define SDIODREV_IS(var, val) ((var) == (val)) | ||
202 | #define SDIODREV_GE(var, val) ((var) >= (val)) | ||
203 | #define SDIODREV_GT(var, val) ((var) > (val)) | ||
204 | #define SDIODREV_LT(var, val) ((var) < (val)) | ||
205 | #define SDIODREV_LE(var, val) ((var) <= (val)) | ||
206 | |||
207 | #define SDIODDMAREG32(h, dir, chnl) \ | ||
208 | ((dir) == DMA_TX ? \ | ||
209 | (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \ | ||
210 | (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) | ||
211 | |||
212 | #define SDIODDMAREG64(h, dir, chnl) \ | ||
213 | ((dir) == DMA_TX ? \ | ||
214 | (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \ | ||
215 | (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) | ||
216 | |||
217 | #define SDIODDMAREG(h, dir, chnl) \ | ||
218 | (SDIODREV_LT((h)->corerev, 1) ? \ | ||
219 | SDIODDMAREG32((h), (dir), (chnl)) : \ | ||
220 | SDIODDMAREG64((h), (dir), (chnl))) | ||
221 | |||
222 | #define PCMDDMAREG(h, dir, chnl) \ | ||
223 | ((dir) == DMA_TX ? \ | ||
224 | (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \ | ||
225 | (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv)) | ||
226 | |||
227 | #define SDPCMDMAREG(h, dir, chnl, coreid) \ | ||
228 | ((coreid) == SDIOD_CORE_ID ? \ | ||
229 | SDIODDMAREG(h, dir, chnl) : \ | ||
230 | PCMDDMAREG(h, dir, chnl)) | ||
231 | |||
232 | #define SDIODFIFOREG(h, corerev) \ | ||
233 | (SDIODREV_LT((corerev), 1) ? \ | ||
234 | ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \ | ||
235 | ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo))) | ||
236 | |||
237 | #define PCMDFIFOREG(h) \ | ||
238 | ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo)) | ||
239 | |||
240 | #define SDPCMFIFOREG(h, coreid, corerev) \ | ||
241 | ((coreid) == SDIOD_CORE_ID ? \ | ||
242 | SDIODFIFOREG(h, corerev) : \ | ||
243 | PCMDFIFOREG(h)) | ||
244 | |||
245 | /* | ||
246 | * Shared structure between dongle and the host. | ||
247 | * The structure contains pointers to trap or assert information. | ||
248 | */ | ||
249 | #define SDPCM_SHARED_VERSION 0x0001 | ||
250 | #define SDPCM_SHARED_VERSION_MASK 0x00FF | ||
251 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | ||
252 | #define SDPCM_SHARED_ASSERT 0x0200 | ||
253 | #define SDPCM_SHARED_TRAP 0x0400 | ||
254 | #define SDPCM_SHARED_IN_BRPT 0x0800 | ||
255 | #define SDPCM_SHARED_SET_BRPT 0x1000 | ||
256 | #define SDPCM_SHARED_PENDING_BRPT 0x2000 | ||
257 | |||
258 | typedef struct { | ||
259 | uint32 flags; | ||
260 | uint32 trap_addr; | ||
261 | uint32 assert_exp_addr; | ||
262 | uint32 assert_file_addr; | ||
263 | uint32 assert_line; | ||
264 | uint32 console_addr; /* Address of hndrte_cons_t */ | ||
265 | uint32 msgtrace_addr; | ||
266 | uint32 brpt_addr; | ||
267 | } sdpcm_shared_t; | ||
268 | |||
269 | extern sdpcm_shared_t sdpcm_shared; | ||
270 | |||
271 | /* Function can be used to notify host of FW halt */ | ||
272 | extern void sdpcmd_fwhalt(void); | ||
273 | |||
274 | #endif /* _bcmsdpcm_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdspi.h b/drivers/net/wireless/bcmdhd/include/bcmsdspi.h new file mode 100644 index 00000000000..0bff355f8ff --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdspi.h | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * SD-SPI Protocol Conversion - BCMSDH->SPI Translation Layer | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmsdspi.h,v 13.11.86.1 2010-11-15 18:14:56 Exp $ | ||
25 | */ | ||
26 | #ifndef _BCM_SD_SPI_H | ||
27 | #define _BCM_SD_SPI_H | ||
28 | |||
29 | /* global msglevel for debug messages - bitvals come from sdiovar.h */ | ||
30 | |||
31 | #define sd_err(x) | ||
32 | #define sd_trace(x) | ||
33 | #define sd_info(x) | ||
34 | #define sd_debug(x) | ||
35 | #define sd_data(x) | ||
36 | #define sd_ctrl(x) | ||
37 | |||
38 | #define sd_log(x) | ||
39 | |||
40 | #define SDIOH_ASSERT(exp) \ | ||
41 | do { if (!(exp)) \ | ||
42 | printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \ | ||
43 | } while (0) | ||
44 | |||
45 | #define BLOCK_SIZE_4318 64 | ||
46 | #define BLOCK_SIZE_4328 512 | ||
47 | |||
48 | /* internal return code */ | ||
49 | #define SUCCESS 0 | ||
50 | #undef ERROR | ||
51 | #define ERROR 1 | ||
52 | |||
53 | /* private bus modes */ | ||
54 | #define SDIOH_MODE_SPI 0 | ||
55 | |||
56 | #define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */ | ||
57 | #define USE_MULTIBLOCK 0x4 | ||
58 | |||
59 | struct sdioh_info { | ||
60 | uint cfg_bar; /* pci cfg address for bar */ | ||
61 | uint32 caps; /* cached value of capabilities reg */ | ||
62 | uint bar0; /* BAR0 for PCI Device */ | ||
63 | osl_t *osh; /* osh handler */ | ||
64 | void *controller; /* Pointer to SPI Controller's private data struct */ | ||
65 | |||
66 | uint lockcount; /* nest count of sdspi_lock() calls */ | ||
67 | bool client_intr_enabled; /* interrupt connnected flag */ | ||
68 | bool intr_handler_valid; /* client driver interrupt handler valid */ | ||
69 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ | ||
70 | void *intr_handler_arg; /* argument to call interrupt handler */ | ||
71 | bool initialized; /* card initialized */ | ||
72 | uint32 target_dev; /* Target device ID */ | ||
73 | uint32 intmask; /* Current active interrupts */ | ||
74 | void *sdos_info; /* Pointer to per-OS private data */ | ||
75 | |||
76 | uint32 controller_type; /* Host controller type */ | ||
77 | uint8 version; /* Host Controller Spec Compliance Version */ | ||
78 | uint irq; /* Client irq */ | ||
79 | uint32 intrcount; /* Client interrupts */ | ||
80 | uint32 local_intrcount; /* Controller interrupts */ | ||
81 | bool host_init_done; /* Controller initted */ | ||
82 | bool card_init_done; /* Client SDIO interface initted */ | ||
83 | bool polled_mode; /* polling for command completion */ | ||
84 | |||
85 | bool sd_use_dma; /* DMA on CMD53 */ | ||
86 | bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ | ||
87 | /* Must be on for sd_multiblock to be effective */ | ||
88 | bool use_client_ints; /* If this is false, make sure to restore */ | ||
89 | bool got_hcint; /* Host Controller interrupt. */ | ||
90 | /* polling hack in wl_linux.c:wl_timer() */ | ||
91 | int adapter_slot; /* Maybe dealing with multiple slots/controllers */ | ||
92 | int sd_mode; /* SD1/SD4/SPI */ | ||
93 | int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ | ||
94 | uint32 data_xfer_count; /* Current register transfer size */ | ||
95 | uint32 cmd53_wr_data; /* Used to pass CMD53 write data */ | ||
96 | uint32 card_response; /* Used to pass back response status byte */ | ||
97 | uint32 card_rsp_data; /* Used to pass back response data word */ | ||
98 | uint16 card_rca; /* Current Address */ | ||
99 | uint8 num_funcs; /* Supported funcs on client */ | ||
100 | uint32 com_cis_ptr; | ||
101 | uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; | ||
102 | void *dma_buf; | ||
103 | ulong dma_phys; | ||
104 | int r_cnt; /* rx count */ | ||
105 | int t_cnt; /* tx_count */ | ||
106 | }; | ||
107 | |||
108 | /************************************************************ | ||
109 | * Internal interfaces: per-port references into bcmsdspi.c | ||
110 | */ | ||
111 | |||
112 | /* Global message bits */ | ||
113 | extern uint sd_msglevel; | ||
114 | |||
115 | /************************************************************** | ||
116 | * Internal interfaces: bcmsdspi.c references to per-port code | ||
117 | */ | ||
118 | |||
119 | /* Register mapping routines */ | ||
120 | extern uint32 *spi_reg_map(osl_t *osh, uintptr addr, int size); | ||
121 | extern void spi_reg_unmap(osl_t *osh, uintptr addr, int size); | ||
122 | |||
123 | /* Interrupt (de)registration routines */ | ||
124 | extern int spi_register_irq(sdioh_info_t *sd, uint irq); | ||
125 | extern void spi_free_irq(uint irq, sdioh_info_t *sd); | ||
126 | |||
127 | /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */ | ||
128 | extern void spi_lock(sdioh_info_t *sd); | ||
129 | extern void spi_unlock(sdioh_info_t *sd); | ||
130 | |||
131 | /* Allocate/init/free per-OS private data */ | ||
132 | extern int spi_osinit(sdioh_info_t *sd); | ||
133 | extern void spi_osfree(sdioh_info_t *sd); | ||
134 | |||
135 | #endif /* _BCM_SD_SPI_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdstd.h b/drivers/net/wireless/bcmdhd/include/bcmsdstd.h new file mode 100644 index 00000000000..0f4c0267dbc --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmsdstd.h | |||
@@ -0,0 +1,267 @@ | |||
1 | /* | ||
2 | * 'Standard' SDIO HOST CONTROLLER driver | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmsdstd.h,v 13.21.2.6 2010-11-15 18:14:01 Exp $ | ||
25 | */ | ||
26 | #ifndef _BCM_SD_STD_H | ||
27 | #define _BCM_SD_STD_H | ||
28 | |||
29 | /* global msglevel for debug messages - bitvals come from sdiovar.h */ | ||
30 | #define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0) | ||
31 | #define sd_trace(x) | ||
32 | #define sd_info(x) | ||
33 | #define sd_debug(x) | ||
34 | #define sd_data(x) | ||
35 | #define sd_ctrl(x) | ||
36 | #define sd_dma(x) | ||
37 | |||
38 | #define sd_sync_dma(sd, read, nbytes) | ||
39 | #define sd_init_dma(sd) | ||
40 | #define sd_ack_intr(sd) | ||
41 | #define sd_wakeup(sd); | ||
42 | /* Allocate/init/free per-OS private data */ | ||
43 | extern int sdstd_osinit(sdioh_info_t *sd); | ||
44 | extern void sdstd_osfree(sdioh_info_t *sd); | ||
45 | |||
46 | #define sd_log(x) | ||
47 | |||
48 | #define SDIOH_ASSERT(exp) \ | ||
49 | do { if (!(exp)) \ | ||
50 | printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \ | ||
51 | } while (0) | ||
52 | |||
53 | #define BLOCK_SIZE_4318 64 | ||
54 | #define BLOCK_SIZE_4328 512 | ||
55 | |||
56 | /* internal return code */ | ||
57 | #define SUCCESS 0 | ||
58 | #define ERROR 1 | ||
59 | |||
60 | /* private bus modes */ | ||
61 | #define SDIOH_MODE_SPI 0 | ||
62 | #define SDIOH_MODE_SD1 1 | ||
63 | #define SDIOH_MODE_SD4 2 | ||
64 | |||
65 | #define MAX_SLOTS 6 /* For PCI: Only 6 BAR entries => 6 slots */ | ||
66 | #define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */ | ||
67 | |||
68 | #define SDIOH_TYPE_ARASAN_HDK 1 | ||
69 | #define SDIOH_TYPE_BCM27XX 2 | ||
70 | #define SDIOH_TYPE_TI_PCIXX21 4 /* TI PCIxx21 Standard Host Controller */ | ||
71 | #define SDIOH_TYPE_RICOH_R5C822 5 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */ | ||
72 | #define SDIOH_TYPE_JMICRON 6 /* JMicron Standard SDIO Host Controller */ | ||
73 | |||
74 | /* For linux, allow yielding for dongle */ | ||
75 | #define BCMSDYIELD | ||
76 | |||
77 | /* Expected card status value for CMD7 */ | ||
78 | #define SDIOH_CMD7_EXP_STATUS 0x00001E00 | ||
79 | |||
80 | #define RETRIES_LARGE 100000 | ||
81 | #define RETRIES_SMALL 100 | ||
82 | |||
83 | |||
84 | #define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */ | ||
85 | #define USE_MULTIBLOCK 0x4 | ||
86 | |||
87 | #define USE_FIFO 0x8 /* Fifo vs non-fifo */ | ||
88 | |||
89 | #define CLIENT_INTR 0x100 /* Get rid of this! */ | ||
90 | |||
91 | #define HC_INTR_RETUNING 0x1000 | ||
92 | |||
93 | |||
94 | struct sdioh_info { | ||
95 | uint cfg_bar; /* pci cfg address for bar */ | ||
96 | uint32 caps; /* cached value of capabilities reg */ | ||
97 | uint32 curr_caps; /* max current capabilities reg */ | ||
98 | |||
99 | osl_t *osh; /* osh handler */ | ||
100 | volatile char *mem_space; /* pci device memory va */ | ||
101 | uint lockcount; /* nest count of sdstd_lock() calls */ | ||
102 | bool client_intr_enabled; /* interrupt connnected flag */ | ||
103 | bool intr_handler_valid; /* client driver interrupt handler valid */ | ||
104 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ | ||
105 | void *intr_handler_arg; /* argument to call interrupt handler */ | ||
106 | bool initialized; /* card initialized */ | ||
107 | uint target_dev; /* Target device ID */ | ||
108 | uint16 intmask; /* Current active interrupts */ | ||
109 | void *sdos_info; /* Pointer to per-OS private data */ | ||
110 | |||
111 | uint32 controller_type; /* Host controller type */ | ||
112 | uint8 version; /* Host Controller Spec Compliance Version */ | ||
113 | uint irq; /* Client irq */ | ||
114 | int intrcount; /* Client interrupts */ | ||
115 | int local_intrcount; /* Controller interrupts */ | ||
116 | bool host_init_done; /* Controller initted */ | ||
117 | bool card_init_done; /* Client SDIO interface initted */ | ||
118 | bool polled_mode; /* polling for command completion */ | ||
119 | |||
120 | bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ | ||
121 | /* Must be on for sd_multiblock to be effective */ | ||
122 | bool use_client_ints; /* If this is false, make sure to restore */ | ||
123 | /* polling hack in wl_linux.c:wl_timer() */ | ||
124 | int adapter_slot; /* Maybe dealing with multiple slots/controllers */ | ||
125 | int sd_mode; /* SD1/SD4/SPI */ | ||
126 | int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ | ||
127 | uint32 data_xfer_count; /* Current transfer */ | ||
128 | uint16 card_rca; /* Current Address */ | ||
129 | int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */ | ||
130 | uint8 num_funcs; /* Supported funcs on client */ | ||
131 | uint32 com_cis_ptr; | ||
132 | uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; | ||
133 | void *dma_buf; /* DMA Buffer virtual address */ | ||
134 | ulong dma_phys; /* DMA Buffer physical address */ | ||
135 | void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */ | ||
136 | ulong adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */ | ||
137 | |||
138 | /* adjustments needed to make the dma align properly */ | ||
139 | void *dma_start_buf; | ||
140 | ulong dma_start_phys; | ||
141 | uint alloced_dma_size; | ||
142 | void *adma2_dscr_start_buf; | ||
143 | ulong adma2_dscr_start_phys; | ||
144 | uint alloced_adma2_dscr_size; | ||
145 | |||
146 | int r_cnt; /* rx count */ | ||
147 | int t_cnt; /* tx_count */ | ||
148 | bool got_hcint; /* local interrupt flag */ | ||
149 | uint16 last_intrstatus; /* to cache intrstatus */ | ||
150 | int host_UHSISupported; /* whether UHSI is supported for HC. */ | ||
151 | int card_UHSI_voltage_Supported; /* whether UHSI is supported for | ||
152 | * Card in terms of Voltage [1.8 or 3.3]. | ||
153 | */ | ||
154 | int global_UHSI_Supp; /* type of UHSI support in both host and card. | ||
155 | * HOST_SDR_UNSUPP: capabilities not supported/matched | ||
156 | * HOST_SDR_12_25: SDR12 and SDR25 supported | ||
157 | * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd | ||
158 | */ | ||
159 | int sd3_dat_state; /* data transfer state used for retuning check */ | ||
160 | int sd3_tun_state; /* tuning state used for retuning check */ | ||
161 | bool sd3_tuning_reqd; /* tuning requirement parameter */ | ||
162 | uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */ | ||
163 | }; | ||
164 | |||
165 | #define DMA_MODE_NONE 0 | ||
166 | #define DMA_MODE_SDMA 1 | ||
167 | #define DMA_MODE_ADMA1 2 | ||
168 | #define DMA_MODE_ADMA2 3 | ||
169 | #define DMA_MODE_ADMA2_64 4 | ||
170 | #define DMA_MODE_AUTO -1 | ||
171 | |||
172 | #define USE_DMA(sd) ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE)) | ||
173 | |||
174 | /* SDIO Host Control Register DMA Mode Definitions */ | ||
175 | #define SDIOH_SDMA_MODE 0 | ||
176 | #define SDIOH_ADMA1_MODE 1 | ||
177 | #define SDIOH_ADMA2_MODE 2 | ||
178 | #define SDIOH_ADMA2_64_MODE 3 | ||
179 | |||
180 | #define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */ | ||
181 | #define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */ | ||
182 | #define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */ | ||
183 | #define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */ | ||
184 | #define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */ | ||
185 | #define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */ | ||
186 | #define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */ | ||
187 | #define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */ | ||
188 | |||
189 | /* States for Tuning and corr data */ | ||
190 | #define TUNING_IDLE 0 | ||
191 | #define TUNING_START 1 | ||
192 | #define TUNING_START_AFTER_DAT 2 | ||
193 | #define TUNING_ONGOING 3 | ||
194 | |||
195 | #define DATA_TRANSFER_IDLE 0 | ||
196 | #define DATA_TRANSFER_ONGOING 1 | ||
197 | |||
198 | /* ADMA2 Descriptor Table Entry for 32-bit Address */ | ||
199 | typedef struct adma2_dscr_32b { | ||
200 | uint32 len_attr; | ||
201 | uint32 phys_addr; | ||
202 | } adma2_dscr_32b_t; | ||
203 | |||
204 | /* ADMA1 Descriptor Table Entry */ | ||
205 | typedef struct adma1_dscr { | ||
206 | uint32 phys_addr_attr; | ||
207 | } adma1_dscr_t; | ||
208 | |||
209 | /************************************************************ | ||
210 | * Internal interfaces: per-port references into bcmsdstd.c | ||
211 | */ | ||
212 | |||
213 | /* Global message bits */ | ||
214 | extern uint sd_msglevel; | ||
215 | |||
216 | /* OS-independent interrupt handler */ | ||
217 | extern bool check_client_intr(sdioh_info_t *sd); | ||
218 | |||
219 | /* Core interrupt enable/disable of device interrupts */ | ||
220 | extern void sdstd_devintr_on(sdioh_info_t *sd); | ||
221 | extern void sdstd_devintr_off(sdioh_info_t *sd); | ||
222 | |||
223 | /* Enable/disable interrupts for local controller events */ | ||
224 | extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err); | ||
225 | extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err); | ||
226 | |||
227 | /* Wait for specified interrupt and error bits to be set */ | ||
228 | extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err); | ||
229 | |||
230 | |||
231 | /************************************************************** | ||
232 | * Internal interfaces: bcmsdstd.c references to per-port code | ||
233 | */ | ||
234 | |||
235 | /* Register mapping routines */ | ||
236 | extern uint32 *sdstd_reg_map(osl_t *osh, int32 addr, int size); | ||
237 | extern void sdstd_reg_unmap(osl_t *osh, int32 addr, int size); | ||
238 | |||
239 | /* Interrupt (de)registration routines */ | ||
240 | extern int sdstd_register_irq(sdioh_info_t *sd, uint irq); | ||
241 | extern void sdstd_free_irq(uint irq, sdioh_info_t *sd); | ||
242 | |||
243 | /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */ | ||
244 | extern void sdstd_lock(sdioh_info_t *sd); | ||
245 | extern void sdstd_unlock(sdioh_info_t *sd); | ||
246 | extern void sdstd_waitlockfree(sdioh_info_t *sd); | ||
247 | |||
248 | /* OS-specific wait-for-interrupt-or-status */ | ||
249 | extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits); | ||
250 | |||
251 | /* used by bcmsdstd_linux [implemented in sdstd] */ | ||
252 | extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd); | ||
253 | extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd); | ||
254 | extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd); | ||
255 | extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd); | ||
256 | extern int sdstd_3_get_tune_state(sdioh_info_t *sd); | ||
257 | extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state); | ||
258 | extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd); | ||
259 | extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd); | ||
260 | extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode); | ||
261 | |||
262 | /* used by sdstd [implemented in bcmsdstd_linux/ndis] */ | ||
263 | extern void sdstd_3_start_tuning(sdioh_info_t *sd); | ||
264 | extern void sdstd_3_osinit_tuning(sdioh_info_t *sd); | ||
265 | extern void sdstd_3_osclean_tuning(sdioh_info_t *sd); | ||
266 | |||
267 | #endif /* _BCM_SD_STD_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmspi.h b/drivers/net/wireless/bcmdhd/include/bcmspi.h new file mode 100644 index 00000000000..0eb2a30c9a8 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmspi.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * Broadcom SPI Low-Level Hardware Driver API | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmspi.h,v 13.5.112.1 2010-11-15 18:13:09 Exp $ | ||
25 | */ | ||
26 | #ifndef _BCM_SPI_H | ||
27 | #define _BCM_SPI_H | ||
28 | |||
29 | extern void spi_devintr_off(sdioh_info_t *sd); | ||
30 | extern void spi_devintr_on(sdioh_info_t *sd); | ||
31 | extern bool spi_start_clock(sdioh_info_t *sd, uint16 new_sd_divisor); | ||
32 | extern bool spi_controller_highspeed_mode(sdioh_info_t *sd, bool hsmode); | ||
33 | extern bool spi_check_client_intr(sdioh_info_t *sd, int *is_dev_intr); | ||
34 | extern bool spi_hw_attach(sdioh_info_t *sd); | ||
35 | extern bool spi_hw_detach(sdioh_info_t *sd); | ||
36 | extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen); | ||
37 | extern void spi_spinbits(sdioh_info_t *sd); | ||
38 | extern void spi_waitbits(sdioh_info_t *sd, bool yield); | ||
39 | |||
40 | #endif /* _BCM_SPI_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmutils.h b/drivers/net/wireless/bcmdhd/include/bcmutils.h new file mode 100644 index 00000000000..530036f0ba7 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmutils.h | |||
@@ -0,0 +1,708 @@ | |||
1 | /* | ||
2 | * Misc useful os-independent macros and functions. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmutils.h,v 13.236.2.16 2011-01-26 00:45:06 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _bcmutils_h_ | ||
29 | #define _bcmutils_h_ | ||
30 | |||
31 | #define bcm_strcpy_s(dst, noOfElements, src) strcpy((dst), (src)) | ||
32 | #define bcm_strncpy_s(dst, noOfElements, src, count) strncpy((dst), (src), (count)) | ||
33 | #define bcm_strcat_s(dst, noOfElements, src) strcat((dst), (src)) | ||
34 | |||
35 | #ifdef __cplusplus | ||
36 | extern "C" { | ||
37 | #endif | ||
38 | |||
39 | |||
40 | #define _BCM_U 0x01 | ||
41 | #define _BCM_L 0x02 | ||
42 | #define _BCM_D 0x04 | ||
43 | #define _BCM_C 0x08 | ||
44 | #define _BCM_P 0x10 | ||
45 | #define _BCM_S 0x20 | ||
46 | #define _BCM_X 0x40 | ||
47 | #define _BCM_SP 0x80 | ||
48 | |||
49 | extern const unsigned char bcm_ctype[]; | ||
50 | #define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)]) | ||
51 | |||
52 | #define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0) | ||
53 | #define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0) | ||
54 | #define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0) | ||
55 | #define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0) | ||
56 | #define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0) | ||
57 | #define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0) | ||
58 | #define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0) | ||
59 | #define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0) | ||
60 | #define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0) | ||
61 | #define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0) | ||
62 | #define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0) | ||
63 | #define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c)) | ||
64 | #define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c)) | ||
65 | |||
66 | |||
67 | |||
68 | struct bcmstrbuf { | ||
69 | char *buf; | ||
70 | unsigned int size; | ||
71 | char *origbuf; | ||
72 | unsigned int origsize; | ||
73 | }; | ||
74 | |||
75 | |||
76 | #ifdef BCMDRIVER | ||
77 | #include <osl.h> | ||
78 | |||
79 | #define GPIO_PIN_NOTDEFINED 0x20 | ||
80 | |||
81 | |||
82 | #define SPINWAIT(exp, us) { \ | ||
83 | uint countdown = (us) + 9; \ | ||
84 | while ((exp) && (countdown >= 10)) {\ | ||
85 | OSL_DELAY(10); \ | ||
86 | countdown -= 10; \ | ||
87 | } \ | ||
88 | } | ||
89 | |||
90 | |||
91 | #ifndef PKTQ_LEN_DEFAULT | ||
92 | #define PKTQ_LEN_DEFAULT 128 | ||
93 | #endif | ||
94 | #ifndef PKTQ_MAX_PREC | ||
95 | #define PKTQ_MAX_PREC 16 | ||
96 | #endif | ||
97 | |||
98 | typedef struct pktq_prec { | ||
99 | void *head; | ||
100 | void *tail; | ||
101 | uint16 len; | ||
102 | uint16 max; | ||
103 | } pktq_prec_t; | ||
104 | |||
105 | |||
106 | |||
107 | struct pktq { | ||
108 | uint16 num_prec; | ||
109 | uint16 hi_prec; | ||
110 | uint16 max; | ||
111 | uint16 len; | ||
112 | |||
113 | struct pktq_prec q[PKTQ_MAX_PREC]; | ||
114 | }; | ||
115 | |||
116 | |||
117 | struct spktq { | ||
118 | uint16 num_prec; | ||
119 | uint16 hi_prec; | ||
120 | uint16 max; | ||
121 | uint16 len; | ||
122 | |||
123 | struct pktq_prec q[1]; | ||
124 | }; | ||
125 | |||
126 | #define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--) | ||
127 | |||
128 | |||
129 | typedef bool (*ifpkt_cb_t)(void*, int); | ||
130 | |||
131 | #ifdef BCMPKTPOOL | ||
132 | #define POOL_ENAB(pool) ((pool) && (pool)->inited) | ||
133 | #if defined(BCM4329C0) | ||
134 | #define SHARED_POOL (pktpool_shared_ptr) | ||
135 | #else | ||
136 | #define SHARED_POOL (pktpool_shared) | ||
137 | #endif | ||
138 | #else | ||
139 | #define POOL_ENAB(bus) 0 | ||
140 | #define SHARED_POOL ((struct pktpool *)NULL) | ||
141 | #endif | ||
142 | |||
143 | #ifndef PKTPOOL_LEN_MAX | ||
144 | #define PKTPOOL_LEN_MAX 40 | ||
145 | #endif | ||
146 | #define PKTPOOL_CB_MAX 3 | ||
147 | |||
148 | struct pktpool; | ||
149 | typedef void (*pktpool_cb_t)(struct pktpool *pool, void *arg); | ||
150 | typedef struct { | ||
151 | pktpool_cb_t cb; | ||
152 | void *arg; | ||
153 | } pktpool_cbinfo_t; | ||
154 | |||
155 | #ifdef BCMDBG_POOL | ||
156 | |||
157 | #define POOL_IDLE 0 | ||
158 | #define POOL_RXFILL 1 | ||
159 | #define POOL_RXDH 2 | ||
160 | #define POOL_RXD11 3 | ||
161 | #define POOL_TXDH 4 | ||
162 | #define POOL_TXD11 5 | ||
163 | #define POOL_AMPDU 6 | ||
164 | #define POOL_TXENQ 7 | ||
165 | |||
166 | typedef struct { | ||
167 | void *p; | ||
168 | uint32 cycles; | ||
169 | uint32 dur; | ||
170 | } pktpool_dbg_t; | ||
171 | |||
172 | typedef struct { | ||
173 | uint8 txdh; | ||
174 | uint8 txd11; | ||
175 | uint8 enq; | ||
176 | uint8 rxdh; | ||
177 | uint8 rxd11; | ||
178 | uint8 rxfill; | ||
179 | uint8 idle; | ||
180 | } pktpool_stats_t; | ||
181 | #endif | ||
182 | |||
183 | typedef struct pktpool { | ||
184 | bool inited; | ||
185 | uint16 r; | ||
186 | uint16 w; | ||
187 | uint16 len; | ||
188 | uint16 maxlen; | ||
189 | uint16 plen; | ||
190 | bool istx; | ||
191 | bool empty; | ||
192 | uint8 cbtoggle; | ||
193 | uint8 cbcnt; | ||
194 | uint8 ecbcnt; | ||
195 | bool emptycb_disable; | ||
196 | pktpool_cbinfo_t cbs[PKTPOOL_CB_MAX]; | ||
197 | pktpool_cbinfo_t ecbs[PKTPOOL_CB_MAX]; | ||
198 | void *q[PKTPOOL_LEN_MAX + 1]; | ||
199 | |||
200 | #ifdef BCMDBG_POOL | ||
201 | uint8 dbg_cbcnt; | ||
202 | pktpool_cbinfo_t dbg_cbs[PKTPOOL_CB_MAX]; | ||
203 | uint16 dbg_qlen; | ||
204 | pktpool_dbg_t dbg_q[PKTPOOL_LEN_MAX + 1]; | ||
205 | #endif | ||
206 | } pktpool_t; | ||
207 | |||
208 | #if defined(BCM4329C0) | ||
209 | extern pktpool_t *pktpool_shared_ptr; | ||
210 | #else | ||
211 | extern pktpool_t *pktpool_shared; | ||
212 | #endif | ||
213 | |||
214 | extern int pktpool_init(osl_t *osh, pktpool_t *pktp, int *pktplen, int plen, bool istx); | ||
215 | extern int pktpool_deinit(osl_t *osh, pktpool_t *pktp); | ||
216 | extern int pktpool_fill(osl_t *osh, pktpool_t *pktp, bool minimal); | ||
217 | extern void* pktpool_get(pktpool_t *pktp); | ||
218 | extern void pktpool_free(pktpool_t *pktp, void *p); | ||
219 | extern int pktpool_add(pktpool_t *pktp, void *p); | ||
220 | extern uint16 pktpool_avail(pktpool_t *pktp); | ||
221 | extern int pktpool_avail_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg); | ||
222 | extern int pktpool_empty_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg); | ||
223 | extern int pktpool_setmaxlen(pktpool_t *pktp, uint16 maxlen); | ||
224 | extern void pktpool_emptycb_disable(pktpool_t *pktp, bool disable); | ||
225 | |||
226 | #define POOLPTR(pp) ((pktpool_t *)(pp)) | ||
227 | #define pktpool_len(pp) (POOLPTR(pp)->len - 1) | ||
228 | #define pktpool_plen(pp) (POOLPTR(pp)->plen) | ||
229 | #define pktpool_maxlen(pp) (POOLPTR(pp)->maxlen) | ||
230 | |||
231 | #ifdef BCMDBG_POOL | ||
232 | extern int pktpool_dbg_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg); | ||
233 | extern int pktpool_start_trigger(pktpool_t *pktp, void *p); | ||
234 | extern int pktpool_dbg_dump(pktpool_t *pktp); | ||
235 | extern int pktpool_dbg_notify(pktpool_t *pktp); | ||
236 | extern int pktpool_stats_dump(pktpool_t *pktp, pktpool_stats_t *stats); | ||
237 | #endif | ||
238 | |||
239 | |||
240 | |||
241 | struct ether_addr; | ||
242 | |||
243 | extern int ether_isbcast(const void *ea); | ||
244 | extern int ether_isnulladdr(const void *ea); | ||
245 | |||
246 | |||
247 | |||
248 | #define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max)) | ||
249 | #define pktq_plen(pq, prec) ((pq)->q[prec].len) | ||
250 | #define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len) | ||
251 | #define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max) | ||
252 | #define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0) | ||
253 | |||
254 | #define pktq_ppeek(pq, prec) ((pq)->q[prec].head) | ||
255 | #define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail) | ||
256 | |||
257 | extern void *pktq_penq(struct pktq *pq, int prec, void *p); | ||
258 | extern void *pktq_penq_head(struct pktq *pq, int prec, void *p); | ||
259 | extern void *pktq_pdeq(struct pktq *pq, int prec); | ||
260 | extern void *pktq_pdeq_tail(struct pktq *pq, int prec); | ||
261 | |||
262 | extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir, | ||
263 | ifpkt_cb_t fn, int arg); | ||
264 | |||
265 | extern bool pktq_pdel(struct pktq *pq, void *p, int prec); | ||
266 | |||
267 | |||
268 | |||
269 | extern int pktq_mlen(struct pktq *pq, uint prec_bmp); | ||
270 | extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out); | ||
271 | |||
272 | |||
273 | |||
274 | #define pktq_len(pq) ((int)(pq)->len) | ||
275 | #define pktq_max(pq) ((int)(pq)->max) | ||
276 | #define pktq_avail(pq) ((int)((pq)->max - (pq)->len)) | ||
277 | #define pktq_full(pq) ((pq)->len >= (pq)->max) | ||
278 | #define pktq_empty(pq) ((pq)->len == 0) | ||
279 | |||
280 | |||
281 | #define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p)) | ||
282 | #define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p)) | ||
283 | #define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0) | ||
284 | #define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0) | ||
285 | #define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len) | ||
286 | |||
287 | extern void pktq_init(struct pktq *pq, int num_prec, int max_len); | ||
288 | |||
289 | extern void *pktq_deq(struct pktq *pq, int *prec_out); | ||
290 | extern void *pktq_deq_tail(struct pktq *pq, int *prec_out); | ||
291 | extern void *pktq_peek(struct pktq *pq, int *prec_out); | ||
292 | extern void *pktq_peek_tail(struct pktq *pq, int *prec_out); | ||
293 | extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg); | ||
294 | |||
295 | |||
296 | |||
297 | extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf); | ||
298 | extern uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf); | ||
299 | extern uint pkttotlen(osl_t *osh, void *p); | ||
300 | extern void *pktlast(osl_t *osh, void *p); | ||
301 | extern uint pktsegcnt(osl_t *osh, void *p); | ||
302 | |||
303 | |||
304 | extern uint pktsetprio(void *pkt, bool update_vtag); | ||
305 | #define PKTPRIO_VDSCP 0x100 | ||
306 | #define PKTPRIO_VLAN 0x200 | ||
307 | #define PKTPRIO_UPD 0x400 | ||
308 | #define PKTPRIO_DSCP 0x800 | ||
309 | |||
310 | |||
311 | extern int bcm_atoi(char *s); | ||
312 | extern ulong bcm_strtoul(char *cp, char **endp, uint base); | ||
313 | extern char *bcmstrstr(char *haystack, char *needle); | ||
314 | extern char *bcmstrcat(char *dest, const char *src); | ||
315 | extern char *bcmstrncat(char *dest, const char *src, uint size); | ||
316 | extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen); | ||
317 | char* bcmstrtok(char **string, const char *delimiters, char *tokdelim); | ||
318 | int bcmstricmp(const char *s1, const char *s2); | ||
319 | int bcmstrnicmp(const char* s1, const char* s2, int cnt); | ||
320 | |||
321 | |||
322 | |||
323 | extern char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf); | ||
324 | extern int bcm_ether_atoe(char *p, struct ether_addr *ea); | ||
325 | |||
326 | |||
327 | struct ipv4_addr; | ||
328 | extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf); | ||
329 | |||
330 | |||
331 | extern void bcm_mdelay(uint ms); | ||
332 | |||
333 | extern char *getvar(char *vars, const char *name); | ||
334 | extern int getintvar(char *vars, const char *name); | ||
335 | extern int getintvararray(char *vars, const char *name, int index); | ||
336 | extern int getintvararraysize(char *vars, const char *name); | ||
337 | extern uint getgpiopin(char *vars, char *pin_name, uint def_pin); | ||
338 | #define bcm_perf_enable() | ||
339 | #define bcmstats(fmt) | ||
340 | #define bcmlog(fmt, a1, a2) | ||
341 | #define bcmdumplog(buf, size) *buf = '\0' | ||
342 | #define bcmdumplogent(buf, idx) -1 | ||
343 | |||
344 | #define bcmtslog(tstamp, fmt, a1, a2) | ||
345 | #define bcmprinttslogs() | ||
346 | #define bcmprinttstamp(us) | ||
347 | |||
348 | extern char *bcm_nvram_vars(uint *length); | ||
349 | extern int bcm_nvram_cache(void *sih); | ||
350 | |||
351 | |||
352 | |||
353 | |||
354 | typedef struct bcm_iovar { | ||
355 | const char *name; | ||
356 | uint16 varid; | ||
357 | uint16 flags; | ||
358 | uint16 type; | ||
359 | uint16 minlen; | ||
360 | } bcm_iovar_t; | ||
361 | |||
362 | |||
363 | |||
364 | |||
365 | #define IOV_GET 0 | ||
366 | #define IOV_SET 1 | ||
367 | |||
368 | |||
369 | #define IOV_GVAL(id) ((id)*2) | ||
370 | #define IOV_SVAL(id) (((id)*2)+IOV_SET) | ||
371 | #define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET) | ||
372 | #define IOV_ID(actionid) (actionid >> 1) | ||
373 | |||
374 | |||
375 | |||
376 | extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name); | ||
377 | extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set); | ||
378 | #if defined(WLTINYDUMP) || defined(WLMSG_INFORM) || defined(WLMSG_ASSOC) || \ | ||
379 | defined(WLMSG_PRPKT) || defined(WLMSG_WSEC) | ||
380 | extern int bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len); | ||
381 | #endif | ||
382 | #endif | ||
383 | |||
384 | |||
385 | #define IOVT_VOID 0 | ||
386 | #define IOVT_BOOL 1 | ||
387 | #define IOVT_INT8 2 | ||
388 | #define IOVT_UINT8 3 | ||
389 | #define IOVT_INT16 4 | ||
390 | #define IOVT_UINT16 5 | ||
391 | #define IOVT_INT32 6 | ||
392 | #define IOVT_UINT32 7 | ||
393 | #define IOVT_BUFFER 8 | ||
394 | #define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER) | ||
395 | |||
396 | |||
397 | #define BCM_IOV_TYPE_INIT { \ | ||
398 | "void", \ | ||
399 | "bool", \ | ||
400 | "int8", \ | ||
401 | "uint8", \ | ||
402 | "int16", \ | ||
403 | "uint16", \ | ||
404 | "int32", \ | ||
405 | "uint32", \ | ||
406 | "buffer", \ | ||
407 | "" } | ||
408 | |||
409 | #define BCM_IOVT_IS_INT(type) (\ | ||
410 | (type == IOVT_BOOL) || \ | ||
411 | (type == IOVT_INT8) || \ | ||
412 | (type == IOVT_UINT8) || \ | ||
413 | (type == IOVT_INT16) || \ | ||
414 | (type == IOVT_UINT16) || \ | ||
415 | (type == IOVT_INT32) || \ | ||
416 | (type == IOVT_UINT32)) | ||
417 | |||
418 | |||
419 | |||
420 | #define BCME_STRLEN 64 | ||
421 | #define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST)) | ||
422 | |||
423 | |||
424 | |||
425 | |||
426 | #define BCME_OK 0 | ||
427 | #define BCME_ERROR -1 | ||
428 | #define BCME_BADARG -2 | ||
429 | #define BCME_BADOPTION -3 | ||
430 | #define BCME_NOTUP -4 | ||
431 | #define BCME_NOTDOWN -5 | ||
432 | #define BCME_NOTAP -6 | ||
433 | #define BCME_NOTSTA -7 | ||
434 | #define BCME_BADKEYIDX -8 | ||
435 | #define BCME_RADIOOFF -9 | ||
436 | #define BCME_NOTBANDLOCKED -10 | ||
437 | #define BCME_NOCLK -11 | ||
438 | #define BCME_BADRATESET -12 | ||
439 | #define BCME_BADBAND -13 | ||
440 | #define BCME_BUFTOOSHORT -14 | ||
441 | #define BCME_BUFTOOLONG -15 | ||
442 | #define BCME_BUSY -16 | ||
443 | #define BCME_NOTASSOCIATED -17 | ||
444 | #define BCME_BADSSIDLEN -18 | ||
445 | #define BCME_OUTOFRANGECHAN -19 | ||
446 | #define BCME_BADCHAN -20 | ||
447 | #define BCME_BADADDR -21 | ||
448 | #define BCME_NORESOURCE -22 | ||
449 | #define BCME_UNSUPPORTED -23 | ||
450 | #define BCME_BADLEN -24 | ||
451 | #define BCME_NOTREADY -25 | ||
452 | #define BCME_EPERM -26 | ||
453 | #define BCME_NOMEM -27 | ||
454 | #define BCME_ASSOCIATED -28 | ||
455 | #define BCME_RANGE -29 | ||
456 | #define BCME_NOTFOUND -30 | ||
457 | #define BCME_WME_NOT_ENABLED -31 | ||
458 | #define BCME_TSPEC_NOTFOUND -32 | ||
459 | #define BCME_ACM_NOTSUPPORTED -33 | ||
460 | #define BCME_NOT_WME_ASSOCIATION -34 | ||
461 | #define BCME_SDIO_ERROR -35 | ||
462 | #define BCME_DONGLE_DOWN -36 | ||
463 | #define BCME_VERSION -37 | ||
464 | #define BCME_TXFAIL -38 | ||
465 | #define BCME_RXFAIL -39 | ||
466 | #define BCME_NODEVICE -40 | ||
467 | #define BCME_NMODE_DISABLED -41 | ||
468 | #define BCME_NONRESIDENT -42 | ||
469 | #define BCME_LAST BCME_NONRESIDENT | ||
470 | |||
471 | |||
472 | #define BCMERRSTRINGTABLE { \ | ||
473 | "OK", \ | ||
474 | "Undefined error", \ | ||
475 | "Bad Argument", \ | ||
476 | "Bad Option", \ | ||
477 | "Not up", \ | ||
478 | "Not down", \ | ||
479 | "Not AP", \ | ||
480 | "Not STA", \ | ||
481 | "Bad Key Index", \ | ||
482 | "Radio Off", \ | ||
483 | "Not band locked", \ | ||
484 | "No clock", \ | ||
485 | "Bad Rate valueset", \ | ||
486 | "Bad Band", \ | ||
487 | "Buffer too short", \ | ||
488 | "Buffer too long", \ | ||
489 | "Busy", \ | ||
490 | "Not Associated", \ | ||
491 | "Bad SSID len", \ | ||
492 | "Out of Range Channel", \ | ||
493 | "Bad Channel", \ | ||
494 | "Bad Address", \ | ||
495 | "Not Enough Resources", \ | ||
496 | "Unsupported", \ | ||
497 | "Bad length", \ | ||
498 | "Not Ready", \ | ||
499 | "Not Permitted", \ | ||
500 | "No Memory", \ | ||
501 | "Associated", \ | ||
502 | "Not In Range", \ | ||
503 | "Not Found", \ | ||
504 | "WME Not Enabled", \ | ||
505 | "TSPEC Not Found", \ | ||
506 | "ACM Not Supported", \ | ||
507 | "Not WME Association", \ | ||
508 | "SDIO Bus Error", \ | ||
509 | "Dongle Not Accessible", \ | ||
510 | "Incorrect version", \ | ||
511 | "TX Failure", \ | ||
512 | "RX Failure", \ | ||
513 | "Device Not Present", \ | ||
514 | "NMODE Disabled", \ | ||
515 | "Nonresident overlay access", \ | ||
516 | } | ||
517 | |||
518 | #ifndef ABS | ||
519 | #define ABS(a) (((a) < 0)?-(a):(a)) | ||
520 | #endif | ||
521 | |||
522 | #ifndef MIN | ||
523 | #define MIN(a, b) (((a) < (b))?(a):(b)) | ||
524 | #endif | ||
525 | |||
526 | #ifndef MAX | ||
527 | #define MAX(a, b) (((a) > (b))?(a):(b)) | ||
528 | #endif | ||
529 | |||
530 | #define CEIL(x, y) (((x) + ((y)-1)) / (y)) | ||
531 | #define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) | ||
532 | #define ISALIGNED(a, x) (((uintptr)(a) & ((x)-1)) == 0) | ||
533 | #define ALIGN_ADDR(addr, boundary) (void *)(((uintptr)(addr) + (boundary) - 1) \ | ||
534 | & ~((boundary) - 1)) | ||
535 | #define ISPOWEROF2(x) ((((x)-1)&(x)) == 0) | ||
536 | #define VALID_MASK(mask) !((mask) & ((mask) + 1)) | ||
537 | #ifndef OFFSETOF | ||
538 | #define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member) | ||
539 | #endif | ||
540 | #ifndef ARRAYSIZE | ||
541 | #define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0])) | ||
542 | #endif | ||
543 | |||
544 | |||
545 | extern void *_bcmutils_dummy_fn; | ||
546 | #define REFERENCE_FUNCTION(f) (_bcmutils_dummy_fn = (void *)(f)) | ||
547 | |||
548 | |||
549 | #ifndef setbit | ||
550 | #ifndef NBBY | ||
551 | #define NBBY 8 | ||
552 | #endif | ||
553 | #define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY)) | ||
554 | #define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) | ||
555 | #define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) | ||
556 | #define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) | ||
557 | #endif | ||
558 | |||
559 | #define NBITS(type) (sizeof(type) * 8) | ||
560 | #define NBITVAL(nbits) (1 << (nbits)) | ||
561 | #define MAXBITVAL(nbits) ((1 << (nbits)) - 1) | ||
562 | #define NBITMASK(nbits) MAXBITVAL(nbits) | ||
563 | #define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8) | ||
564 | |||
565 | |||
566 | #define MUX(pred, true, false) ((pred) ? (true) : (false)) | ||
567 | |||
568 | |||
569 | #define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1) | ||
570 | #define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1) | ||
571 | |||
572 | |||
573 | #define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1)) | ||
574 | #define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1)) | ||
575 | |||
576 | |||
577 | #define MODADD(x, y, bound) \ | ||
578 | MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y)) | ||
579 | #define MODSUB(x, y, bound) \ | ||
580 | MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y)) | ||
581 | |||
582 | |||
583 | #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1)) | ||
584 | #define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1)) | ||
585 | |||
586 | |||
587 | #define CRC8_INIT_VALUE 0xff | ||
588 | #define CRC8_GOOD_VALUE 0x9f | ||
589 | #define CRC16_INIT_VALUE 0xffff | ||
590 | #define CRC16_GOOD_VALUE 0xf0b8 | ||
591 | #define CRC32_INIT_VALUE 0xffffffff | ||
592 | #define CRC32_GOOD_VALUE 0xdebb20e3 | ||
593 | |||
594 | |||
595 | typedef struct bcm_bit_desc { | ||
596 | uint32 bit; | ||
597 | const char* name; | ||
598 | } bcm_bit_desc_t; | ||
599 | |||
600 | |||
601 | typedef struct bcm_tlv { | ||
602 | uint8 id; | ||
603 | uint8 len; | ||
604 | uint8 data[1]; | ||
605 | } bcm_tlv_t; | ||
606 | |||
607 | |||
608 | #define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len)) | ||
609 | |||
610 | |||
611 | #define ETHER_ADDR_STR_LEN 18 | ||
612 | |||
613 | |||
614 | |||
615 | static INLINE void | ||
616 | xor_128bit_block(const uint8 *src1, const uint8 *src2, uint8 *dst) | ||
617 | { | ||
618 | if ( | ||
619 | #ifdef __i386__ | ||
620 | 1 || | ||
621 | #endif | ||
622 | (((uintptr)src1 | (uintptr)src2 | (uintptr)dst) & 3) == 0) { | ||
623 | |||
624 | |||
625 | ((uint32 *)dst)[0] = ((const uint32 *)src1)[0] ^ ((const uint32 *)src2)[0]; | ||
626 | ((uint32 *)dst)[1] = ((const uint32 *)src1)[1] ^ ((const uint32 *)src2)[1]; | ||
627 | ((uint32 *)dst)[2] = ((const uint32 *)src1)[2] ^ ((const uint32 *)src2)[2]; | ||
628 | ((uint32 *)dst)[3] = ((const uint32 *)src1)[3] ^ ((const uint32 *)src2)[3]; | ||
629 | } else { | ||
630 | |||
631 | int k; | ||
632 | for (k = 0; k < 16; k++) | ||
633 | dst[k] = src1[k] ^ src2[k]; | ||
634 | } | ||
635 | } | ||
636 | |||
637 | |||
638 | |||
639 | extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc); | ||
640 | extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc); | ||
641 | extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc); | ||
642 | |||
643 | #if defined(DHD_DEBUG) || defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || \ | ||
644 | defined(WLMSG_ASSOC) | ||
645 | extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len); | ||
646 | #endif | ||
647 | |||
648 | #if defined(DHD_DEBUG) || defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || \ | ||
649 | defined(WLMSG_ASSOC) || defined(WLMEDIA_PEAKRATE) | ||
650 | extern int bcm_format_hex(char *str, const void *bytes, int len); | ||
651 | #endif | ||
652 | |||
653 | extern const char *bcm_crypto_algo_name(uint algo); | ||
654 | extern char *bcm_chipname(uint chipid, char *buf, uint len); | ||
655 | extern char *bcm_brev_str(uint32 brev, char *buf); | ||
656 | extern void printbig(char *buf); | ||
657 | extern void prhex(const char *msg, uchar *buf, uint len); | ||
658 | |||
659 | |||
660 | extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen); | ||
661 | extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key); | ||
662 | extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key); | ||
663 | |||
664 | |||
665 | extern const char *bcmerrorstr(int bcmerror); | ||
666 | |||
667 | |||
668 | typedef uint32 mbool; | ||
669 | #define mboolset(mb, bit) ((mb) |= (bit)) | ||
670 | #define mboolclr(mb, bit) ((mb) &= ~(bit)) | ||
671 | #define mboolisset(mb, bit) (((mb) & (bit)) != 0) | ||
672 | #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val))) | ||
673 | |||
674 | |||
675 | extern uint16 bcm_qdbm_to_mw(uint8 qdbm); | ||
676 | extern uint8 bcm_mw_to_qdbm(uint16 mw); | ||
677 | |||
678 | |||
679 | struct fielddesc { | ||
680 | const char *nameandfmt; | ||
681 | uint32 offset; | ||
682 | uint32 len; | ||
683 | }; | ||
684 | |||
685 | extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size); | ||
686 | extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...); | ||
687 | extern void bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount); | ||
688 | extern int bcm_cmp_bytes(uchar *arg1, uchar *arg2, uint8 nbytes); | ||
689 | extern void bcm_print_bytes(char *name, const uchar *cdata, int len); | ||
690 | |||
691 | typedef uint32 (*bcmutl_rdreg_rtn)(void *arg0, uint arg1, uint32 offset); | ||
692 | extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, uint arg1, struct fielddesc *str, | ||
693 | char *buf, uint32 bufsize); | ||
694 | |||
695 | extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len); | ||
696 | extern uint bcm_bitcount(uint8 *bitmap, uint bytelength); | ||
697 | |||
698 | |||
699 | |||
700 | #define SSID_FMT_BUF_LEN ((4 * DOT11_MAX_SSID_LEN) + 1) | ||
701 | |||
702 | unsigned int process_nvram_vars(char *varbuf, unsigned int len); | ||
703 | |||
704 | #ifdef __cplusplus | ||
705 | } | ||
706 | #endif | ||
707 | |||
708 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/bcmwifi.h b/drivers/net/wireless/bcmdhd/include/bcmwifi.h new file mode 100644 index 00000000000..45f3c0312dc --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/bcmwifi.h | |||
@@ -0,0 +1,165 @@ | |||
1 | /* | ||
2 | * Misc utility routines for WL and Apps | ||
3 | * This header file housing the define and function prototype use by | ||
4 | * both the wl driver, tools & Apps. | ||
5 | * | ||
6 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
7 | * | ||
8 | * Unless you and Broadcom execute a separate written software license | ||
9 | * agreement governing use of this software, this software is licensed to you | ||
10 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
11 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
12 | * following added to such license: | ||
13 | * | ||
14 | * As a special exception, the copyright holders of this software give you | ||
15 | * permission to link this software with independent modules, and to copy and | ||
16 | * distribute the resulting executable under terms of your choice, provided that | ||
17 | * you also meet, for each linked independent module, the terms and conditions of | ||
18 | * the license of that module. An independent module is a module which is not | ||
19 | * derived from this software. The special exception does not apply to any | ||
20 | * modifications of the software. | ||
21 | * | ||
22 | * Notwithstanding the above, under no circumstances may you combine this | ||
23 | * software in any way with any other Broadcom software provided under a license | ||
24 | * other than the GPL, without Broadcom's express prior written consent. | ||
25 | * | ||
26 | * $Id: bcmwifi.h,v 1.29.6.3 2010-08-03 17:47:04 Exp $ | ||
27 | */ | ||
28 | |||
29 | |||
30 | #ifndef _bcmwifi_h_ | ||
31 | #define _bcmwifi_h_ | ||
32 | |||
33 | |||
34 | |||
35 | typedef uint16 chanspec_t; | ||
36 | |||
37 | |||
38 | #define CH_UPPER_SB 0x01 | ||
39 | #define CH_LOWER_SB 0x02 | ||
40 | #define CH_EWA_VALID 0x04 | ||
41 | #define CH_20MHZ_APART 4 | ||
42 | #define CH_10MHZ_APART 2 | ||
43 | #define CH_5MHZ_APART 1 | ||
44 | #define CH_MAX_2G_CHANNEL 14 | ||
45 | #define WLC_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL | ||
46 | #define MAXCHANNEL 224 | ||
47 | |||
48 | #define WL_CHANSPEC_CHAN_MASK 0x00ff | ||
49 | #define WL_CHANSPEC_CHAN_SHIFT 0 | ||
50 | |||
51 | #define WL_CHANSPEC_CTL_SB_MASK 0x0300 | ||
52 | #define WL_CHANSPEC_CTL_SB_SHIFT 8 | ||
53 | #define WL_CHANSPEC_CTL_SB_LOWER 0x0100 | ||
54 | #define WL_CHANSPEC_CTL_SB_UPPER 0x0200 | ||
55 | #define WL_CHANSPEC_CTL_SB_NONE 0x0300 | ||
56 | |||
57 | #define WL_CHANSPEC_BW_MASK 0x0C00 | ||
58 | #define WL_CHANSPEC_BW_SHIFT 10 | ||
59 | #define WL_CHANSPEC_BW_10 0x0400 | ||
60 | #define WL_CHANSPEC_BW_20 0x0800 | ||
61 | #define WL_CHANSPEC_BW_40 0x0C00 | ||
62 | |||
63 | #define WL_CHANSPEC_BAND_MASK 0xf000 | ||
64 | #define WL_CHANSPEC_BAND_SHIFT 12 | ||
65 | #define WL_CHANSPEC_BAND_5G 0x1000 | ||
66 | #define WL_CHANSPEC_BAND_2G 0x2000 | ||
67 | #define INVCHANSPEC 255 | ||
68 | |||
69 | |||
70 | #define WF_CHAN_FACTOR_2_4_G 4814 | ||
71 | #define WF_CHAN_FACTOR_5_G 10000 | ||
72 | #define WF_CHAN_FACTOR_4_G 8000 | ||
73 | |||
74 | |||
75 | #define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0) | ||
76 | #define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \ | ||
77 | ((channel) + CH_10MHZ_APART) : 0) | ||
78 | #define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX) | ||
79 | #define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \ | ||
80 | WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \ | ||
81 | WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G)) | ||
82 | #define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \ | ||
83 | ((channel) + CH_20MHZ_APART) : 0) | ||
84 | #define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \ | ||
85 | ((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \ | ||
86 | ((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \ | ||
87 | WL_CHANSPEC_BAND_5G)) | ||
88 | #define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK)) | ||
89 | #define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK) | ||
90 | |||
91 | |||
92 | #define CHSPEC_CTL_SB(chspec) (chspec & WL_CHANSPEC_CTL_SB_MASK) | ||
93 | #define CHSPEC_BW(chspec) (chspec & WL_CHANSPEC_BW_MASK) | ||
94 | |||
95 | #ifdef WL11N_20MHZONLY | ||
96 | |||
97 | #define CHSPEC_IS10(chspec) 0 | ||
98 | #define CHSPEC_IS20(chspec) 1 | ||
99 | #ifndef CHSPEC_IS40 | ||
100 | #define CHSPEC_IS40(chspec) 0 | ||
101 | #endif | ||
102 | |||
103 | #else | ||
104 | |||
105 | #define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10) | ||
106 | #define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20) | ||
107 | #ifndef CHSPEC_IS40 | ||
108 | #define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40) | ||
109 | #endif | ||
110 | |||
111 | #endif | ||
112 | |||
113 | #define CHSPEC_IS20_UNCOND(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20) | ||
114 | |||
115 | #define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G) | ||
116 | #define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G) | ||
117 | #define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE) | ||
118 | #define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER) | ||
119 | #define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER) | ||
120 | #define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \ | ||
121 | (LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \ | ||
122 | (UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK)))) | ||
123 | #define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G) | ||
124 | |||
125 | #define CHANSPEC_STR_LEN 8 | ||
126 | |||
127 | |||
128 | #define WLC_MAXRATE 108 | ||
129 | #define WLC_RATE_1M 2 | ||
130 | #define WLC_RATE_2M 4 | ||
131 | #define WLC_RATE_5M5 11 | ||
132 | #define WLC_RATE_11M 22 | ||
133 | #define WLC_RATE_6M 12 | ||
134 | #define WLC_RATE_9M 18 | ||
135 | #define WLC_RATE_12M 24 | ||
136 | #define WLC_RATE_18M 36 | ||
137 | #define WLC_RATE_24M 48 | ||
138 | #define WLC_RATE_36M 72 | ||
139 | #define WLC_RATE_48M 96 | ||
140 | #define WLC_RATE_54M 108 | ||
141 | |||
142 | #define WLC_2G_25MHZ_OFFSET 5 | ||
143 | |||
144 | |||
145 | extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf); | ||
146 | |||
147 | |||
148 | extern chanspec_t wf_chspec_aton(char *a); | ||
149 | |||
150 | |||
151 | extern bool wf_chspec_malformed(chanspec_t chanspec); | ||
152 | |||
153 | |||
154 | extern uint8 wf_chspec_ctlchan(chanspec_t chspec); | ||
155 | |||
156 | |||
157 | extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec); | ||
158 | |||
159 | |||
160 | extern int wf_mhz2channel(uint freq, uint start_factor); | ||
161 | |||
162 | |||
163 | extern int wf_channel2mhz(uint channel, uint start_factor); | ||
164 | |||
165 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/dhdioctl.h b/drivers/net/wireless/bcmdhd/include/dhdioctl.h new file mode 100644 index 00000000000..9661dac2603 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/dhdioctl.h | |||
@@ -0,0 +1,129 @@ | |||
1 | /* | ||
2 | * Definitions for ioctls to access DHD iovars. | ||
3 | * Based on wlioctl.h (for Broadcom 802.11abg driver). | ||
4 | * (Moves towards generic ioctls for BCM drivers/iovars.) | ||
5 | * | ||
6 | * Definitions subject to change without notice. | ||
7 | * | ||
8 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
9 | * | ||
10 | * Unless you and Broadcom execute a separate written software license | ||
11 | * agreement governing use of this software, this software is licensed to you | ||
12 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
13 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
14 | * following added to such license: | ||
15 | * | ||
16 | * As a special exception, the copyright holders of this software give you | ||
17 | * permission to link this software with independent modules, and to copy and | ||
18 | * distribute the resulting executable under terms of your choice, provided that | ||
19 | * you also meet, for each linked independent module, the terms and conditions of | ||
20 | * the license of that module. An independent module is a module which is not | ||
21 | * derived from this software. The special exception does not apply to any | ||
22 | * modifications of the software. | ||
23 | * | ||
24 | * Notwithstanding the above, under no circumstances may you combine this | ||
25 | * software in any way with any other Broadcom software provided under a license | ||
26 | * other than the GPL, without Broadcom's express prior written consent. | ||
27 | * | ||
28 | * $Id: dhdioctl.h,v 13.11.10.1 2010-12-22 23:47:26 Exp $ | ||
29 | */ | ||
30 | |||
31 | #ifndef _dhdioctl_h_ | ||
32 | #define _dhdioctl_h_ | ||
33 | |||
34 | #include <typedefs.h> | ||
35 | |||
36 | |||
37 | /* require default structure packing */ | ||
38 | #define BWL_DEFAULT_PACKING | ||
39 | #include <packed_section_start.h> | ||
40 | |||
41 | |||
42 | /* Linux network driver ioctl encoding */ | ||
43 | typedef struct dhd_ioctl { | ||
44 | uint cmd; /* common ioctl definition */ | ||
45 | void *buf; /* pointer to user buffer */ | ||
46 | uint len; /* length of user buffer */ | ||
47 | bool set; /* get or set request (optional) */ | ||
48 | uint used; /* bytes read or written (optional) */ | ||
49 | uint needed; /* bytes needed (optional) */ | ||
50 | uint driver; /* to identify target driver */ | ||
51 | } dhd_ioctl_t; | ||
52 | |||
53 | /* Underlying BUS definition */ | ||
54 | enum { | ||
55 | BUS_TYPE_USB = 0, /* for USB dongles */ | ||
56 | BUS_TYPE_SDIO /* for SDIO dongles */ | ||
57 | }; | ||
58 | |||
59 | /* per-driver magic numbers */ | ||
60 | #define DHD_IOCTL_MAGIC 0x00444944 | ||
61 | |||
62 | /* bump this number if you change the ioctl interface */ | ||
63 | #define DHD_IOCTL_VERSION 1 | ||
64 | |||
65 | #define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */ | ||
66 | #define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */ | ||
67 | |||
68 | /* common ioctl definitions */ | ||
69 | #define DHD_GET_MAGIC 0 | ||
70 | #define DHD_GET_VERSION 1 | ||
71 | #define DHD_GET_VAR 2 | ||
72 | #define DHD_SET_VAR 3 | ||
73 | |||
74 | /* message levels */ | ||
75 | #define DHD_ERROR_VAL 0x0001 | ||
76 | #define DHD_TRACE_VAL 0x0002 | ||
77 | #define DHD_INFO_VAL 0x0004 | ||
78 | #define DHD_DATA_VAL 0x0008 | ||
79 | #define DHD_CTL_VAL 0x0010 | ||
80 | #define DHD_TIMER_VAL 0x0020 | ||
81 | #define DHD_HDRS_VAL 0x0040 | ||
82 | #define DHD_BYTES_VAL 0x0080 | ||
83 | #define DHD_INTR_VAL 0x0100 | ||
84 | #define DHD_LOG_VAL 0x0200 | ||
85 | #define DHD_GLOM_VAL 0x0400 | ||
86 | #define DHD_EVENT_VAL 0x0800 | ||
87 | #define DHD_BTA_VAL 0x1000 | ||
88 | #define DHD_ISCAN_VAL 0x2000 | ||
89 | #define DHD_ARPOE_VAL 0x4000 | ||
90 | |||
91 | #ifdef SDTEST | ||
92 | /* For pktgen iovar */ | ||
93 | typedef struct dhd_pktgen { | ||
94 | uint version; /* To allow structure change tracking */ | ||
95 | uint freq; /* Max ticks between tx/rx attempts */ | ||
96 | uint count; /* Test packets to send/rcv each attempt */ | ||
97 | uint print; /* Print counts every <print> attempts */ | ||
98 | uint total; /* Total packets (or bursts) */ | ||
99 | uint minlen; /* Minimum length of packets to send */ | ||
100 | uint maxlen; /* Maximum length of packets to send */ | ||
101 | uint numsent; /* Count of test packets sent */ | ||
102 | uint numrcvd; /* Count of test packets received */ | ||
103 | uint numfail; /* Count of test send failures */ | ||
104 | uint mode; /* Test mode (type of test packets) */ | ||
105 | uint stop; /* Stop after this many tx failures */ | ||
106 | } dhd_pktgen_t; | ||
107 | |||
108 | /* Version in case structure changes */ | ||
109 | #define DHD_PKTGEN_VERSION 2 | ||
110 | |||
111 | /* Type of test packets to use */ | ||
112 | #define DHD_PKTGEN_ECHO 1 /* Send echo requests */ | ||
113 | #define DHD_PKTGEN_SEND 2 /* Send discard packets */ | ||
114 | #define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */ | ||
115 | #define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous tx dongle */ | ||
116 | #endif /* SDTEST */ | ||
117 | |||
118 | /* Enter idle immediately (no timeout) */ | ||
119 | #define DHD_IDLE_IMMEDIATE (-1) | ||
120 | |||
121 | /* Values for idleclock iovar: other values are the sd_divisor to use when idle */ | ||
122 | #define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change when idle */ | ||
123 | #define DHD_IDLE_STOP (-1) /* Request SD clock be stopped (and use SD1 mode) */ | ||
124 | |||
125 | |||
126 | /* require default structure packing */ | ||
127 | #include <packed_section_end.h> | ||
128 | |||
129 | #endif /* _dhdioctl_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/epivers.h b/drivers/net/wireless/bcmdhd/include/epivers.h new file mode 100644 index 00000000000..ae1f975bdb6 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/epivers.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * | ||
22 | * $Id: epivers.h.in,v 13.32.4.1 2010-09-17 00:39:18 $ | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | |||
27 | #ifndef _epivers_h_ | ||
28 | #define _epivers_h_ | ||
29 | |||
30 | #define EPI_MAJOR_VERSION 5 | ||
31 | |||
32 | #define EPI_MINOR_VERSION 90 | ||
33 | |||
34 | #define EPI_RC_NUMBER 125 | ||
35 | |||
36 | #define EPI_INCREMENTAL_NUMBER 94 | ||
37 | |||
38 | #define EPI_BUILD_NUMBER 0 | ||
39 | |||
40 | #define EPI_VERSION 5, 90, 125, 94 | ||
41 | |||
42 | #define EPI_VERSION_NUM 0x055a7d5e | ||
43 | |||
44 | #define EPI_VERSION_DEV 5.90.125 | ||
45 | |||
46 | |||
47 | #define EPI_VERSION_STR "5.90.125.94" | ||
48 | |||
49 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/hndpmu.h b/drivers/net/wireless/bcmdhd/include/hndpmu.h new file mode 100644 index 00000000000..51c51b9734a --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/hndpmu.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * HND SiliconBackplane PMU support. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: hndpmu.h,v 13.35.8.5 2011-02-11 00:56:32 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _hndpmu_h_ | ||
28 | #define _hndpmu_h_ | ||
29 | |||
30 | |||
31 | extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on); | ||
32 | extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength); | ||
33 | |||
34 | #endif /* _hndpmu_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/hndrte_armtrap.h b/drivers/net/wireless/bcmdhd/include/hndrte_armtrap.h new file mode 100644 index 00000000000..8b9615c35f3 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/hndrte_armtrap.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * HNDRTE arm trap handling. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: hndrte_armtrap.h,v 13.4.14.1 2011-02-05 00:04:30 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _hndrte_armtrap_h | ||
28 | #define _hndrte_armtrap_h | ||
29 | |||
30 | |||
31 | /* ARM trap handling */ | ||
32 | |||
33 | /* Trap types defined by ARM (see arminc.h) */ | ||
34 | |||
35 | /* Trap locations in lo memory */ | ||
36 | #define TRAP_STRIDE 4 | ||
37 | #define FIRST_TRAP TR_RST | ||
38 | #define LAST_TRAP (TR_FIQ * TRAP_STRIDE) | ||
39 | |||
40 | #if defined(__ARM_ARCH_4T__) | ||
41 | #define MAX_TRAP_TYPE (TR_FIQ + 1) | ||
42 | #elif defined(__ARM_ARCH_7M__) | ||
43 | #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS) | ||
44 | #endif /* __ARM_ARCH_7M__ */ | ||
45 | |||
46 | /* The trap structure is defined here as offsets for assembly */ | ||
47 | #define TR_TYPE 0x00 | ||
48 | #define TR_EPC 0x04 | ||
49 | #define TR_CPSR 0x08 | ||
50 | #define TR_SPSR 0x0c | ||
51 | #define TR_REGS 0x10 | ||
52 | #define TR_REG(n) (TR_REGS + (n) * 4) | ||
53 | #define TR_SP TR_REG(13) | ||
54 | #define TR_LR TR_REG(14) | ||
55 | #define TR_PC TR_REG(15) | ||
56 | |||
57 | #define TRAP_T_SIZE 80 | ||
58 | |||
59 | #ifndef _LANGUAGE_ASSEMBLY | ||
60 | |||
61 | #include <typedefs.h> | ||
62 | |||
63 | typedef struct _trap_struct { | ||
64 | uint32 type; | ||
65 | uint32 epc; | ||
66 | uint32 cpsr; | ||
67 | uint32 spsr; | ||
68 | uint32 r0; | ||
69 | uint32 r1; | ||
70 | uint32 r2; | ||
71 | uint32 r3; | ||
72 | uint32 r4; | ||
73 | uint32 r5; | ||
74 | uint32 r6; | ||
75 | uint32 r7; | ||
76 | uint32 r8; | ||
77 | uint32 r9; | ||
78 | uint32 r10; | ||
79 | uint32 r11; | ||
80 | uint32 r12; | ||
81 | uint32 r13; | ||
82 | uint32 r14; | ||
83 | uint32 pc; | ||
84 | } trap_t; | ||
85 | |||
86 | #endif /* !_LANGUAGE_ASSEMBLY */ | ||
87 | |||
88 | #endif /* _hndrte_armtrap_h */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/hndrte_cons.h b/drivers/net/wireless/bcmdhd/include/hndrte_cons.h new file mode 100644 index 00000000000..b9ede53af70 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/hndrte_cons.h | |||
@@ -0,0 +1,68 @@ | |||
1 | /* | ||
2 | * Console support for hndrte. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: hndrte_cons.h,v 13.4.10.4 2011-02-05 00:08:20 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _HNDRTE_CONS_H | ||
28 | #define _HNDRTE_CONS_H | ||
29 | |||
30 | #include <typedefs.h> | ||
31 | |||
32 | #define CBUF_LEN (128) | ||
33 | |||
34 | #define LOG_BUF_LEN 1024 | ||
35 | |||
36 | typedef struct { | ||
37 | uint32 buf; /* Can't be pointer on (64-bit) hosts */ | ||
38 | uint buf_size; | ||
39 | uint idx; | ||
40 | char *_buf_compat; /* redundant pointer for backward compat. */ | ||
41 | } hndrte_log_t; | ||
42 | |||
43 | typedef struct { | ||
44 | /* Virtual UART | ||
45 | * When there is no UART (e.g. Quickturn), the host should write a complete | ||
46 | * input line directly into cbuf and then write the length into vcons_in. | ||
47 | * This may also be used when there is a real UART (at risk of conflicting with | ||
48 | * the real UART). vcons_out is currently unused. | ||
49 | */ | ||
50 | volatile uint vcons_in; | ||
51 | volatile uint vcons_out; | ||
52 | |||
53 | /* Output (logging) buffer | ||
54 | * Console output is written to a ring buffer log_buf at index log_idx. | ||
55 | * The host may read the output when it sees log_idx advance. | ||
56 | * Output will be lost if the output wraps around faster than the host polls. | ||
57 | */ | ||
58 | hndrte_log_t log; | ||
59 | |||
60 | /* Console input line buffer | ||
61 | * Characters are read one at a time into cbuf until <CR> is received, then | ||
62 | * the buffer is processed as a command line. Also used for virtual UART. | ||
63 | */ | ||
64 | uint cbuf_idx; | ||
65 | char cbuf[CBUF_LEN]; | ||
66 | } hndrte_cons_t; | ||
67 | |||
68 | #endif /* _HNDRTE_CONS_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/hndsoc.h b/drivers/net/wireless/bcmdhd/include/hndsoc.h new file mode 100644 index 00000000000..4e26121c388 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/hndsoc.h | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * Broadcom HND chip & on-chip-interconnect-related definitions. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: hndsoc.h,v 13.11 2009-12-03 23:52:31 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _HNDSOC_H | ||
28 | #define _HNDSOC_H | ||
29 | |||
30 | /* Include the soci specific files */ | ||
31 | #include <sbconfig.h> | ||
32 | #include <aidmp.h> | ||
33 | |||
34 | /* | ||
35 | * SOC Interconnect Address Map. | ||
36 | * All regions may not exist on all chips. | ||
37 | */ | ||
38 | #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ | ||
39 | #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ | ||
40 | #define SI_PCI_MEM_SZ (64 * 1024 * 1024) | ||
41 | #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ | ||
42 | #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ | ||
43 | #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ | ||
44 | |||
45 | #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ | ||
46 | |||
47 | #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ | ||
48 | #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ | ||
49 | #define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software | ||
50 | * convenience and could be changed if we | ||
51 | * make any larger chips | ||
52 | */ | ||
53 | |||
54 | #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ | ||
55 | #define SI_FASTRAM_SWAPPED 0x19800000 | ||
56 | |||
57 | #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ | ||
58 | #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ | ||
59 | #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ | ||
60 | #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ | ||
61 | #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ | ||
62 | #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ | ||
63 | #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ | ||
64 | #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ | ||
65 | #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ | ||
66 | #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ | ||
67 | |||
68 | #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ | ||
69 | #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ | ||
70 | #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ | ||
71 | #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 | ||
72 | * (2 ZettaBytes), low 32 bits | ||
73 | */ | ||
74 | #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 | ||
75 | * (2 ZettaBytes), high 32 bits | ||
76 | */ | ||
77 | |||
78 | /* core codes */ | ||
79 | #define NODEV_CORE_ID 0x700 /* Invalid coreid */ | ||
80 | #define CC_CORE_ID 0x800 /* chipcommon core */ | ||
81 | #define ILINE20_CORE_ID 0x801 /* iline20 core */ | ||
82 | #define SRAM_CORE_ID 0x802 /* sram core */ | ||
83 | #define SDRAM_CORE_ID 0x803 /* sdram core */ | ||
84 | #define PCI_CORE_ID 0x804 /* pci core */ | ||
85 | #define MIPS_CORE_ID 0x805 /* mips core */ | ||
86 | #define ENET_CORE_ID 0x806 /* enet mac core */ | ||
87 | #define CODEC_CORE_ID 0x807 /* v90 codec core */ | ||
88 | #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ | ||
89 | #define ADSL_CORE_ID 0x809 /* ADSL core */ | ||
90 | #define ILINE100_CORE_ID 0x80a /* iline100 core */ | ||
91 | #define IPSEC_CORE_ID 0x80b /* ipsec core */ | ||
92 | #define UTOPIA_CORE_ID 0x80c /* utopia core */ | ||
93 | #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ | ||
94 | #define SOCRAM_CORE_ID 0x80e /* internal memory core */ | ||
95 | #define MEMC_CORE_ID 0x80f /* memc sdram core */ | ||
96 | #define OFDM_CORE_ID 0x810 /* OFDM phy core */ | ||
97 | #define EXTIF_CORE_ID 0x811 /* external interface core */ | ||
98 | #define D11_CORE_ID 0x812 /* 802.11 MAC core */ | ||
99 | #define APHY_CORE_ID 0x813 /* 802.11a phy core */ | ||
100 | #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ | ||
101 | #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ | ||
102 | #define MIPS33_CORE_ID 0x816 /* mips3302 core */ | ||
103 | #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ | ||
104 | #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ | ||
105 | #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ | ||
106 | #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ | ||
107 | #define SDIOH_CORE_ID 0x81b /* sdio host core */ | ||
108 | #define ROBO_CORE_ID 0x81c /* roboswitch core */ | ||
109 | #define ATA100_CORE_ID 0x81d /* parallel ATA core */ | ||
110 | #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ | ||
111 | #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ | ||
112 | #define PCIE_CORE_ID 0x820 /* pci express core */ | ||
113 | #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ | ||
114 | #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ | ||
115 | #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ | ||
116 | #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ | ||
117 | #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ | ||
118 | #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ | ||
119 | #define PMU_CORE_ID 0x827 /* PMU core */ | ||
120 | #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ | ||
121 | #define SDIOD_CORE_ID 0x829 /* SDIO device core */ | ||
122 | #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ | ||
123 | #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ | ||
124 | #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ | ||
125 | #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ | ||
126 | #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ | ||
127 | #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ | ||
128 | #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ | ||
129 | #define SC_CORE_ID 0x831 /* shared common core */ | ||
130 | #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ | ||
131 | #define SPIH_CORE_ID 0x833 /* SPI host core */ | ||
132 | #define I2S_CORE_ID 0x834 /* I2S core */ | ||
133 | #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ | ||
134 | #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ | ||
135 | #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ | ||
136 | #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all | ||
137 | * unused address ranges | ||
138 | */ | ||
139 | |||
140 | /* There are TWO constants on all HND chips: SI_ENUM_BASE above, | ||
141 | * and chipcommon being the first core: | ||
142 | */ | ||
143 | #define SI_CC_IDX 0 | ||
144 | |||
145 | /* SOC Interconnect types (aka chip types) */ | ||
146 | #define SOCI_SB 0 | ||
147 | #define SOCI_AI 1 | ||
148 | #define SOCI_UBUS 2 | ||
149 | |||
150 | /* Common core control flags */ | ||
151 | #define SICF_BIST_EN 0x8000 | ||
152 | #define SICF_PME_EN 0x4000 | ||
153 | #define SICF_CORE_BITS 0x3ffc | ||
154 | #define SICF_FGC 0x0002 | ||
155 | #define SICF_CLOCK_EN 0x0001 | ||
156 | |||
157 | /* Common core status flags */ | ||
158 | #define SISF_BIST_DONE 0x8000 | ||
159 | #define SISF_BIST_ERROR 0x4000 | ||
160 | #define SISF_GATED_CLK 0x2000 | ||
161 | #define SISF_DMA64 0x1000 | ||
162 | #define SISF_CORE_BITS 0x0fff | ||
163 | |||
164 | /* A register that is common to all cores to | ||
165 | * communicate w/PMU regarding clock control. | ||
166 | */ | ||
167 | #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ | ||
168 | |||
169 | /* clk_ctl_st register */ | ||
170 | #define CCS_FORCEALP 0x00000001 /* force ALP request */ | ||
171 | #define CCS_FORCEHT 0x00000002 /* force HT request */ | ||
172 | #define CCS_FORCEILP 0x00000004 /* force ILP request */ | ||
173 | #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ | ||
174 | #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ | ||
175 | #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ | ||
176 | #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ | ||
177 | #define CCS_ERSRC_REQ_SHIFT 8 | ||
178 | #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ | ||
179 | #define CCS_HTAVAIL 0x00020000 /* HT is available */ | ||
180 | #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ | ||
181 | #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ | ||
182 | #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ | ||
183 | #define CCS_ERSRC_STS_SHIFT 24 | ||
184 | |||
185 | #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ | ||
186 | #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ | ||
187 | |||
188 | /* Not really related to SOC Interconnect, but a couple of software | ||
189 | * conventions for the use the flash space: | ||
190 | */ | ||
191 | |||
192 | /* Minumum amount of flash we support */ | ||
193 | #define FLASH_MIN 0x00020000 /* Minimum flash size */ | ||
194 | |||
195 | /* A boot/binary may have an embedded block that describes its size */ | ||
196 | #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ | ||
197 | #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ | ||
198 | #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ | ||
199 | #define BISZ_TXTST_IDX 1 /* 1: text start */ | ||
200 | #define BISZ_TXTEND_IDX 2 /* 2: text end */ | ||
201 | #define BISZ_DATAST_IDX 3 /* 3: data start */ | ||
202 | #define BISZ_DATAEND_IDX 4 /* 4: data end */ | ||
203 | #define BISZ_BSSST_IDX 5 /* 5: bss start */ | ||
204 | #define BISZ_BSSEND_IDX 6 /* 6: bss end */ | ||
205 | #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ | ||
206 | |||
207 | #endif /* _HNDSOC_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/htsf.h b/drivers/net/wireless/bcmdhd/include/htsf.h new file mode 100644 index 00000000000..379fbbe37db --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/htsf.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Time stamps for latency measurements | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: htsf.h,v 1.1.2.4 2011-01-21 08:27:03 Exp $ | ||
25 | */ | ||
26 | #ifndef _HTSF_H_ | ||
27 | #define _HTSF_H_ | ||
28 | |||
29 | #define HTSFMAGIC 0xCDCDABAB /* in network order for tcpdump */ | ||
30 | #define HTSFENDMAGIC 0xEFEFABAB /* to distinguish from RT2 magic */ | ||
31 | #define HTSF_HOSTOFFSET 102 | ||
32 | #define HTSF_DNGLOFFSET HTSF_HOSTOFFSET - 4 | ||
33 | #define HTSF_DNGLOFFSET2 HTSF_HOSTOFFSET + 106 | ||
34 | #define HTSF_MIN_PKTLEN 200 | ||
35 | #define ETHER_TYPE_BRCM_PKTDLYSTATS 0x886d | ||
36 | |||
37 | typedef enum htsfts_type { | ||
38 | T10, | ||
39 | T20, | ||
40 | T30, | ||
41 | T40, | ||
42 | T50, | ||
43 | T60, | ||
44 | T70, | ||
45 | T80, | ||
46 | T90, | ||
47 | TA0, | ||
48 | TE0 | ||
49 | } htsf_timestamp_t; | ||
50 | |||
51 | typedef struct { | ||
52 | uint32 magic; | ||
53 | uint32 prio; | ||
54 | uint32 seqnum; | ||
55 | uint32 misc; | ||
56 | uint32 c10; | ||
57 | uint32 t10; | ||
58 | uint32 c20; | ||
59 | uint32 t20; | ||
60 | uint32 t30; | ||
61 | uint32 t40; | ||
62 | uint32 t50; | ||
63 | uint32 t60; | ||
64 | uint32 t70; | ||
65 | uint32 t80; | ||
66 | uint32 t90; | ||
67 | uint32 cA0; | ||
68 | uint32 tA0; | ||
69 | uint32 cE0; | ||
70 | uint32 tE0; | ||
71 | uint32 endmagic; | ||
72 | } htsfts_t; | ||
73 | |||
74 | #endif /* _HTSF_H_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/linux_osl.h b/drivers/net/wireless/bcmdhd/include/linux_osl.h new file mode 100644 index 00000000000..1ec136eb70d --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/linux_osl.h | |||
@@ -0,0 +1,431 @@ | |||
1 | /* | ||
2 | * Linux OS Independent Layer | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: linux_osl.h,v 13.158.6.3 2010-12-22 23:47:26 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _linux_osl_h_ | ||
29 | #define _linux_osl_h_ | ||
30 | |||
31 | #include <typedefs.h> | ||
32 | |||
33 | |||
34 | extern void * osl_os_open_image(char * filename); | ||
35 | extern int osl_os_get_image_block(char * buf, int len, void * image); | ||
36 | extern void osl_os_close_image(void * image); | ||
37 | |||
38 | |||
39 | #ifdef BCMDRIVER | ||
40 | |||
41 | |||
42 | extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag); | ||
43 | extern void osl_detach(osl_t *osh); | ||
44 | |||
45 | |||
46 | extern uint32 g_assert_type; | ||
47 | |||
48 | |||
49 | #if defined(BCMASSERT_LOG) | ||
50 | #define ASSERT(exp) \ | ||
51 | do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0) | ||
52 | extern void osl_assert(char *exp, char *file, int line); | ||
53 | #else | ||
54 | #ifdef __GNUC__ | ||
55 | #define GCC_VERSION \ | ||
56 | (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) | ||
57 | #if GCC_VERSION > 30100 | ||
58 | #define ASSERT(exp) do {} while (0) | ||
59 | #else | ||
60 | |||
61 | #define ASSERT(exp) | ||
62 | #endif | ||
63 | #endif | ||
64 | #endif | ||
65 | |||
66 | |||
67 | #define OSL_DELAY(usec) osl_delay(usec) | ||
68 | extern void osl_delay(uint usec); | ||
69 | |||
70 | #define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \ | ||
71 | osl_pcmcia_read_attr((osh), (offset), (buf), (size)) | ||
72 | #define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \ | ||
73 | osl_pcmcia_write_attr((osh), (offset), (buf), (size)) | ||
74 | extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size); | ||
75 | extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size); | ||
76 | |||
77 | |||
78 | #define OSL_PCI_READ_CONFIG(osh, offset, size) \ | ||
79 | osl_pci_read_config((osh), (offset), (size)) | ||
80 | #define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \ | ||
81 | osl_pci_write_config((osh), (offset), (size), (val)) | ||
82 | extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size); | ||
83 | extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val); | ||
84 | |||
85 | |||
86 | #define OSL_PCI_BUS(osh) osl_pci_bus(osh) | ||
87 | #define OSL_PCI_SLOT(osh) osl_pci_slot(osh) | ||
88 | extern uint osl_pci_bus(osl_t *osh); | ||
89 | extern uint osl_pci_slot(osl_t *osh); | ||
90 | |||
91 | |||
92 | typedef struct { | ||
93 | bool pkttag; | ||
94 | uint pktalloced; | ||
95 | bool mmbus; | ||
96 | pktfree_cb_fn_t tx_fn; | ||
97 | void *tx_ctx; | ||
98 | } osl_pubinfo_t; | ||
99 | |||
100 | #define PKTFREESETCB(osh, _tx_fn, _tx_ctx) \ | ||
101 | do { \ | ||
102 | ((osl_pubinfo_t*)osh)->tx_fn = _tx_fn; \ | ||
103 | ((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx; \ | ||
104 | } while (0) | ||
105 | |||
106 | |||
107 | |||
108 | #define BUS_SWAP32(v) (v) | ||
109 | |||
110 | #define MALLOC(osh, size) osl_malloc((osh), (size)) | ||
111 | #define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size)) | ||
112 | #define MALLOCED(osh) osl_malloced((osh)) | ||
113 | extern void *osl_malloc(osl_t *osh, uint size); | ||
114 | extern void osl_mfree(osl_t *osh, void *addr, uint size); | ||
115 | extern uint osl_malloced(osl_t *osh); | ||
116 | |||
117 | #define NATIVE_MALLOC(osh, size) kmalloc(size, GFP_ATOMIC) | ||
118 | #define NATIVE_MFREE(osh, addr, size) kfree(addr) | ||
119 | |||
120 | #define MALLOC_FAILED(osh) osl_malloc_failed((osh)) | ||
121 | extern uint osl_malloc_failed(osl_t *osh); | ||
122 | |||
123 | |||
124 | #define DMA_CONSISTENT_ALIGN osl_dma_consistent_align() | ||
125 | #define DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \ | ||
126 | osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap)) | ||
127 | #define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \ | ||
128 | osl_dma_free_consistent((osh), (void*)(va), (size), (pa)) | ||
129 | extern uint osl_dma_consistent_align(void); | ||
130 | extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align, uint *tot, ulong *pap); | ||
131 | extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa); | ||
132 | |||
133 | |||
134 | #define DMA_TX 1 | ||
135 | #define DMA_RX 2 | ||
136 | |||
137 | |||
138 | #define DMA_MAP(osh, va, size, direction, p, dmah) \ | ||
139 | osl_dma_map((osh), (va), (size), (direction)) | ||
140 | #define DMA_UNMAP(osh, pa, size, direction, p, dmah) \ | ||
141 | osl_dma_unmap((osh), (pa), (size), (direction)) | ||
142 | extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction); | ||
143 | extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction); | ||
144 | |||
145 | |||
146 | #define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0) | ||
147 | |||
148 | |||
149 | #include <bcmsdh.h> | ||
150 | #define OSL_WRITE_REG(osh, r, v) (bcmsdh_reg_write(NULL, (uintptr)(r), sizeof(*(r)), (v))) | ||
151 | #define OSL_READ_REG(osh, r) (bcmsdh_reg_read(NULL, (uintptr)(r), sizeof(*(r)))) | ||
152 | |||
153 | #define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \ | ||
154 | mmap_op else bus_op | ||
155 | #define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \ | ||
156 | mmap_op : bus_op | ||
157 | |||
158 | #define OSL_ERROR(bcmerror) osl_error(bcmerror) | ||
159 | extern int osl_error(int bcmerror); | ||
160 | |||
161 | |||
162 | #define PKTBUFSZ 2048 | ||
163 | |||
164 | |||
165 | |||
166 | #define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ)) | ||
167 | #define printf(fmt, args...) printk(fmt , ## args) | ||
168 | #include <linux/kernel.h> | ||
169 | #include <linux/string.h> | ||
170 | |||
171 | #define bcopy(src, dst, len) memcpy((dst), (src), (len)) | ||
172 | #define bcmp(b1, b2, len) memcmp((b1), (b2), (len)) | ||
173 | #define bzero(b, len) memset((b), '\0', (len)) | ||
174 | |||
175 | |||
176 | |||
177 | #ifndef __mips__ | ||
178 | #define R_REG(osh, r) (\ | ||
179 | SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \ | ||
180 | sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \ | ||
181 | readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \ | ||
182 | ) | ||
183 | #else | ||
184 | #define R_REG(osh, r) (\ | ||
185 | SELECT_BUS_READ(osh, \ | ||
186 | ({ \ | ||
187 | __typeof(*(r)) __osl_v; \ | ||
188 | __asm__ __volatile__("sync"); \ | ||
189 | switch (sizeof(*(r))) { \ | ||
190 | case sizeof(uint8): __osl_v = \ | ||
191 | readb((volatile uint8*)(r)); break; \ | ||
192 | case sizeof(uint16): __osl_v = \ | ||
193 | readw((volatile uint16*)(r)); break; \ | ||
194 | case sizeof(uint32): __osl_v = \ | ||
195 | readl((volatile uint32*)(r)); break; \ | ||
196 | } \ | ||
197 | __asm__ __volatile__("sync"); \ | ||
198 | __osl_v; \ | ||
199 | }), \ | ||
200 | ({ \ | ||
201 | __typeof(*(r)) __osl_v; \ | ||
202 | __asm__ __volatile__("sync"); \ | ||
203 | __osl_v = OSL_READ_REG(osh, r); \ | ||
204 | __asm__ __volatile__("sync"); \ | ||
205 | __osl_v; \ | ||
206 | })) \ | ||
207 | ) | ||
208 | #endif | ||
209 | |||
210 | #define W_REG(osh, r, v) do { \ | ||
211 | SELECT_BUS_WRITE(osh, \ | ||
212 | switch (sizeof(*(r))) { \ | ||
213 | case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \ | ||
214 | case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \ | ||
215 | case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \ | ||
216 | }, \ | ||
217 | (OSL_WRITE_REG(osh, r, v))); \ | ||
218 | } while (0) | ||
219 | |||
220 | |||
221 | #define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v)) | ||
222 | #define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v)) | ||
223 | |||
224 | |||
225 | #define bcopy(src, dst, len) memcpy((dst), (src), (len)) | ||
226 | #define bcmp(b1, b2, len) memcmp((b1), (b2), (len)) | ||
227 | #define bzero(b, len) memset((b), '\0', (len)) | ||
228 | |||
229 | |||
230 | #ifdef __mips__ | ||
231 | #include <asm/addrspace.h> | ||
232 | #define OSL_UNCACHED(va) ((void *)KSEG1ADDR((va))) | ||
233 | #define OSL_CACHED(va) ((void *)KSEG0ADDR((va))) | ||
234 | #else | ||
235 | #define OSL_UNCACHED(va) ((void *)va) | ||
236 | #define OSL_CACHED(va) ((void *)va) | ||
237 | #endif | ||
238 | |||
239 | |||
240 | #if defined(__i386__) | ||
241 | #define OSL_GETCYCLES(x) rdtscl((x)) | ||
242 | #else | ||
243 | #define OSL_GETCYCLES(x) ((x) = 0) | ||
244 | #endif | ||
245 | |||
246 | |||
247 | #define BUSPROBE(val, addr) ({ (val) = R_REG(NULL, (addr)); 0; }) | ||
248 | |||
249 | |||
250 | #if !defined(CONFIG_MMC_MSM7X00A) | ||
251 | #define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size)) | ||
252 | #else | ||
253 | #define REG_MAP(pa, size) (void *)(0) | ||
254 | #endif | ||
255 | #define REG_UNMAP(va) iounmap((va)) | ||
256 | |||
257 | |||
258 | #define R_SM(r) *(r) | ||
259 | #define W_SM(r, v) (*(r) = (v)) | ||
260 | #define BZERO_SM(r, len) memset((r), '\0', (len)) | ||
261 | |||
262 | |||
263 | #include <linuxver.h> | ||
264 | |||
265 | |||
266 | #define PKTGET(osh, len, send) osl_pktget((osh), (len)) | ||
267 | #define PKTDUP(osh, skb) osl_pktdup((osh), (skb)) | ||
268 | #define PKTLIST_DUMP(osh, buf) | ||
269 | #define PKTDBG_TRACE(osh, pkt, bit) | ||
270 | #define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send)) | ||
271 | #ifdef DHD_USE_STATIC_BUF | ||
272 | #define PKTGET_STATIC(osh, len, send) osl_pktget_static((osh), (len)) | ||
273 | #define PKTFREE_STATIC(osh, skb, send) osl_pktfree_static((osh), (skb), (send)) | ||
274 | #endif | ||
275 | #define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data) | ||
276 | #define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len) | ||
277 | #define PKTHEADROOM(osh, skb) (PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head)) | ||
278 | #define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail)) | ||
279 | #define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next) | ||
280 | #define PKTSETNEXT(osh, skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x)) | ||
281 | #define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len)) | ||
282 | #define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes)) | ||
283 | #define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes)) | ||
284 | #define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb)) | ||
285 | #define PKTALLOCED(osh) ((osl_pubinfo_t *)(osh))->pktalloced | ||
286 | #define PKTSETPOOL(osh, skb, x, y) do {} while (0) | ||
287 | #define PKTPOOL(osh, skb) FALSE | ||
288 | #define PKTSHRINK(osh, m) (m) | ||
289 | |||
290 | #ifdef CTFPOOL | ||
291 | #define CTFPOOL_REFILL_THRESH 3 | ||
292 | typedef struct ctfpool { | ||
293 | void *head; | ||
294 | spinlock_t lock; | ||
295 | uint max_obj; | ||
296 | uint curr_obj; | ||
297 | uint obj_size; | ||
298 | uint refills; | ||
299 | uint fast_allocs; | ||
300 | uint fast_frees; | ||
301 | uint slow_allocs; | ||
302 | } ctfpool_t; | ||
303 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) | ||
304 | #define FASTBUF (1 << 4) | ||
305 | #define CTFBUF (1 << 5) | ||
306 | #define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) |= FASTBUF) | ||
307 | #define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) &= (~FASTBUF)) | ||
308 | #define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) |= CTFBUF) | ||
309 | #define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) &= (~CTFBUF)) | ||
310 | #define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & FASTBUF) | ||
311 | #define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & CTFBUF) | ||
312 | #define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->mac_len) | ||
313 | #else | ||
314 | #define FASTBUF (1 << 0) | ||
315 | #define CTFBUF (1 << 1) | ||
316 | #define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) |= FASTBUF) | ||
317 | #define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) &= (~FASTBUF)) | ||
318 | #define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) |= CTFBUF) | ||
319 | #define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) &= (~CTFBUF)) | ||
320 | #define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) & FASTBUF) | ||
321 | #define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) & CTFBUF) | ||
322 | #define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->__unused) | ||
323 | #endif | ||
324 | |||
325 | #define CTFPOOLPTR(osh, skb) (((struct sk_buff*)(skb))->sk) | ||
326 | #define CTFPOOLHEAD(osh, skb) (((ctfpool_t *)((struct sk_buff*)(skb))->sk)->head) | ||
327 | |||
328 | extern void *osl_ctfpool_add(osl_t *osh); | ||
329 | extern void osl_ctfpool_replenish(osl_t *osh, uint thresh); | ||
330 | extern int32 osl_ctfpool_init(osl_t *osh, uint numobj, uint size); | ||
331 | extern void osl_ctfpool_cleanup(osl_t *osh); | ||
332 | extern void osl_ctfpool_stats(osl_t *osh, void *b); | ||
333 | #endif | ||
334 | |||
335 | #ifdef HNDCTF | ||
336 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) | ||
337 | #define SKIPCT (1 << 6) | ||
338 | #define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len |= SKIPCT) | ||
339 | #define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len &= (~SKIPCT)) | ||
340 | #define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len & SKIPCT) | ||
341 | #else | ||
342 | #define SKIPCT (1 << 2) | ||
343 | #define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused |= SKIPCT) | ||
344 | #define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused &= (~SKIPCT)) | ||
345 | #define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused & SKIPCT) | ||
346 | #endif | ||
347 | #else | ||
348 | #define PKTSETSKIPCT(osh, skb) | ||
349 | #define PKTCLRSKIPCT(osh, skb) | ||
350 | #define PKTSKIPCT(osh, skb) | ||
351 | #endif | ||
352 | |||
353 | extern void osl_pktfree(osl_t *osh, void *skb, bool send); | ||
354 | extern void *osl_pktget_static(osl_t *osh, uint len); | ||
355 | extern void osl_pktfree_static(osl_t *osh, void *skb, bool send); | ||
356 | |||
357 | extern void *osl_pktget(osl_t *osh, uint len); | ||
358 | extern void *osl_pktdup(osl_t *osh, void *skb); | ||
359 | |||
360 | |||
361 | static INLINE void * | ||
362 | osl_pkt_frmnative(osl_pubinfo_t *osh, void *pkt) | ||
363 | { | ||
364 | struct sk_buff *nskb; | ||
365 | |||
366 | if (osh->pkttag) | ||
367 | bzero((void*)((struct sk_buff*)pkt)->cb, OSL_PKTTAG_SZ); | ||
368 | |||
369 | |||
370 | for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) { | ||
371 | osh->pktalloced++; | ||
372 | } | ||
373 | |||
374 | return (void *)pkt; | ||
375 | } | ||
376 | #define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_pubinfo_t *)osh), (struct sk_buff*)(skb)) | ||
377 | |||
378 | |||
379 | static INLINE struct sk_buff * | ||
380 | osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) | ||
381 | { | ||
382 | struct sk_buff *nskb; | ||
383 | |||
384 | if (osh->pkttag) | ||
385 | bzero(((struct sk_buff*)pkt)->cb, OSL_PKTTAG_SZ); | ||
386 | |||
387 | |||
388 | for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) { | ||
389 | osh->pktalloced--; | ||
390 | } | ||
391 | |||
392 | return (struct sk_buff *)pkt; | ||
393 | } | ||
394 | #define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osl_pubinfo_t *)(osh), (pkt)) | ||
395 | |||
396 | #define PKTLINK(skb) (((struct sk_buff*)(skb))->prev) | ||
397 | #define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x)) | ||
398 | #define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority) | ||
399 | #define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x)) | ||
400 | #define PKTSUMNEEDED(skb) (((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW) | ||
401 | #define PKTSETSUMGOOD(skb, x) (((struct sk_buff*)(skb))->ip_summed = \ | ||
402 | ((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE)) | ||
403 | |||
404 | #define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned) | ||
405 | |||
406 | |||
407 | |||
408 | #else | ||
409 | |||
410 | |||
411 | |||
412 | #define ASSERT(exp) do {} while (0) | ||
413 | |||
414 | |||
415 | #define MALLOC(o, l) malloc(l) | ||
416 | #define MFREE(o, p, l) free(p) | ||
417 | #include <stdlib.h> | ||
418 | |||
419 | |||
420 | #include <string.h> | ||
421 | |||
422 | |||
423 | #include <stdio.h> | ||
424 | |||
425 | |||
426 | extern void bcopy(const void *src, void *dst, size_t len); | ||
427 | extern int bcmp(const void *b1, const void *b2, size_t len); | ||
428 | extern void bzero(void *b, size_t len); | ||
429 | #endif | ||
430 | |||
431 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/linuxver.h b/drivers/net/wireless/bcmdhd/include/linuxver.h new file mode 100644 index 00000000000..96844db2f05 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/linuxver.h | |||
@@ -0,0 +1,593 @@ | |||
1 | /* | ||
2 | * Linux-specific abstractions to gain some independence from linux kernel versions. | ||
3 | * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences. | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: linuxver.h,v 13.53.2.2 2010-12-22 23:47:26 Exp $ | ||
26 | */ | ||
27 | |||
28 | |||
29 | #ifndef _linuxver_h_ | ||
30 | #define _linuxver_h_ | ||
31 | |||
32 | #include <linux/version.h> | ||
33 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) | ||
34 | #include <linux/config.h> | ||
35 | #else | ||
36 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) | ||
37 | #include <generated/autoconf.h> | ||
38 | #else | ||
39 | #include <linux/autoconf.h> | ||
40 | #endif | ||
41 | #endif | ||
42 | #include <linux/module.h> | ||
43 | |||
44 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0)) | ||
45 | |||
46 | #ifdef __UNDEF_NO_VERSION__ | ||
47 | #undef __NO_VERSION__ | ||
48 | #else | ||
49 | #define __NO_VERSION__ | ||
50 | #endif | ||
51 | #endif | ||
52 | |||
53 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0) | ||
54 | #define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i") | ||
55 | #define module_param_string(_name_, _string_, _size_, _perm_) \ | ||
56 | MODULE_PARM(_string_, "c" __MODULE_STRING(_size_)) | ||
57 | #endif | ||
58 | |||
59 | |||
60 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9)) | ||
61 | #include <linux/malloc.h> | ||
62 | #else | ||
63 | #include <linux/slab.h> | ||
64 | #endif | ||
65 | |||
66 | #include <linux/types.h> | ||
67 | #include <linux/init.h> | ||
68 | #include <linux/mm.h> | ||
69 | #include <linux/string.h> | ||
70 | #include <linux/pci.h> | ||
71 | #include <linux/interrupt.h> | ||
72 | #include <linux/netdevice.h> | ||
73 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) | ||
74 | #include <linux/semaphore.h> | ||
75 | #endif | ||
76 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) | ||
77 | #undef IP_TOS | ||
78 | #endif | ||
79 | #include <asm/io.h> | ||
80 | |||
81 | #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) | ||
82 | #include <linux/workqueue.h> | ||
83 | #else | ||
84 | #include <linux/tqueue.h> | ||
85 | #ifndef work_struct | ||
86 | #define work_struct tq_struct | ||
87 | #endif | ||
88 | #ifndef INIT_WORK | ||
89 | #define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data)) | ||
90 | #endif | ||
91 | #ifndef schedule_work | ||
92 | #define schedule_work(_work) schedule_task((_work)) | ||
93 | #endif | ||
94 | #ifndef flush_scheduled_work | ||
95 | #define flush_scheduled_work() flush_scheduled_tasks() | ||
96 | #endif | ||
97 | #endif | ||
98 | |||
99 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) | ||
100 | #define MY_INIT_WORK(_work, _func) INIT_WORK(_work, _func) | ||
101 | #else | ||
102 | #define MY_INIT_WORK(_work, _func) INIT_WORK(_work, _func, _work) | ||
103 | typedef void (*work_func_t)(void *work); | ||
104 | #endif | ||
105 | |||
106 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) | ||
107 | |||
108 | #ifndef IRQ_NONE | ||
109 | typedef void irqreturn_t; | ||
110 | #define IRQ_NONE | ||
111 | #define IRQ_HANDLED | ||
112 | #define IRQ_RETVAL(x) | ||
113 | #endif | ||
114 | #else | ||
115 | typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs); | ||
116 | #endif | ||
117 | |||
118 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18) | ||
119 | #define IRQF_SHARED SA_SHIRQ | ||
120 | #endif | ||
121 | |||
122 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17) | ||
123 | #ifdef CONFIG_NET_RADIO | ||
124 | #define CONFIG_WIRELESS_EXT | ||
125 | #endif | ||
126 | #endif | ||
127 | |||
128 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67) | ||
129 | #define MOD_INC_USE_COUNT | ||
130 | #define MOD_DEC_USE_COUNT | ||
131 | #endif | ||
132 | |||
133 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32) | ||
134 | #include <linux/sched.h> | ||
135 | #endif | ||
136 | |||
137 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29) | ||
138 | #include <net/lib80211.h> | ||
139 | #endif | ||
140 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29) | ||
141 | #include <linux/ieee80211.h> | ||
142 | #else | ||
143 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14) | ||
144 | #include <net/ieee80211.h> | ||
145 | #endif | ||
146 | #endif | ||
147 | |||
148 | |||
149 | #ifndef __exit | ||
150 | #define __exit | ||
151 | #endif | ||
152 | #ifndef __devexit | ||
153 | #define __devexit | ||
154 | #endif | ||
155 | #ifndef __devinit | ||
156 | #define __devinit __init | ||
157 | #endif | ||
158 | #ifndef __devinitdata | ||
159 | #define __devinitdata | ||
160 | #endif | ||
161 | #ifndef __devexit_p | ||
162 | #define __devexit_p(x) x | ||
163 | #endif | ||
164 | |||
165 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) | ||
166 | |||
167 | #define pci_get_drvdata(dev) (dev)->sysdata | ||
168 | #define pci_set_drvdata(dev, value) (dev)->sysdata = (value) | ||
169 | |||
170 | |||
171 | |||
172 | struct pci_device_id { | ||
173 | unsigned int vendor, device; | ||
174 | unsigned int subvendor, subdevice; | ||
175 | unsigned int class, class_mask; | ||
176 | unsigned long driver_data; | ||
177 | }; | ||
178 | |||
179 | struct pci_driver { | ||
180 | struct list_head node; | ||
181 | char *name; | ||
182 | const struct pci_device_id *id_table; | ||
183 | int (*probe)(struct pci_dev *dev, | ||
184 | const struct pci_device_id *id); | ||
185 | void (*remove)(struct pci_dev *dev); | ||
186 | void (*suspend)(struct pci_dev *dev); | ||
187 | void (*resume)(struct pci_dev *dev); | ||
188 | }; | ||
189 | |||
190 | #define MODULE_DEVICE_TABLE(type, name) | ||
191 | #define PCI_ANY_ID (~0) | ||
192 | |||
193 | |||
194 | #define pci_module_init pci_register_driver | ||
195 | extern int pci_register_driver(struct pci_driver *drv); | ||
196 | extern void pci_unregister_driver(struct pci_driver *drv); | ||
197 | |||
198 | #endif | ||
199 | |||
200 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)) | ||
201 | #define pci_module_init pci_register_driver | ||
202 | #endif | ||
203 | |||
204 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18)) | ||
205 | #ifdef MODULE | ||
206 | #define module_init(x) int init_module(void) { return x(); } | ||
207 | #define module_exit(x) void cleanup_module(void) { x(); } | ||
208 | #else | ||
209 | #define module_init(x) __initcall(x); | ||
210 | #define module_exit(x) __exitcall(x); | ||
211 | #endif | ||
212 | #endif | ||
213 | |||
214 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31) | ||
215 | #define WL_USE_NETDEV_OPS | ||
216 | #else | ||
217 | #undef WL_USE_NETDEV_OPS | ||
218 | #endif | ||
219 | |||
220 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)) && defined(CONFIG_RFKILL_INPUT) | ||
221 | #define WL_CONFIG_RFKILL_INPUT | ||
222 | #else | ||
223 | #undef WL_CONFIG_RFKILL_INPUT | ||
224 | #endif | ||
225 | |||
226 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48)) | ||
227 | #define list_for_each(pos, head) \ | ||
228 | for (pos = (head)->next; pos != (head); pos = pos->next) | ||
229 | #endif | ||
230 | |||
231 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13)) | ||
232 | #define pci_resource_start(dev, bar) ((dev)->base_address[(bar)]) | ||
233 | #elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44)) | ||
234 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) | ||
235 | #endif | ||
236 | |||
237 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23)) | ||
238 | #define pci_enable_device(dev) do { } while (0) | ||
239 | #endif | ||
240 | |||
241 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14)) | ||
242 | #define net_device device | ||
243 | #endif | ||
244 | |||
245 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42)) | ||
246 | |||
247 | |||
248 | |||
249 | #ifndef PCI_DMA_TODEVICE | ||
250 | #define PCI_DMA_TODEVICE 1 | ||
251 | #define PCI_DMA_FROMDEVICE 2 | ||
252 | #endif | ||
253 | |||
254 | typedef u32 dma_addr_t; | ||
255 | |||
256 | |||
257 | static inline int get_order(unsigned long size) | ||
258 | { | ||
259 | int order; | ||
260 | |||
261 | size = (size-1) >> (PAGE_SHIFT-1); | ||
262 | order = -1; | ||
263 | do { | ||
264 | size >>= 1; | ||
265 | order++; | ||
266 | } while (size); | ||
267 | return order; | ||
268 | } | ||
269 | |||
270 | static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, | ||
271 | dma_addr_t *dma_handle) | ||
272 | { | ||
273 | void *ret; | ||
274 | int gfp = GFP_ATOMIC | GFP_DMA; | ||
275 | |||
276 | ret = (void *)__get_free_pages(gfp, get_order(size)); | ||
277 | |||
278 | if (ret != NULL) { | ||
279 | memset(ret, 0, size); | ||
280 | *dma_handle = virt_to_bus(ret); | ||
281 | } | ||
282 | return ret; | ||
283 | } | ||
284 | static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, | ||
285 | void *vaddr, dma_addr_t dma_handle) | ||
286 | { | ||
287 | free_pages((unsigned long)vaddr, get_order(size)); | ||
288 | } | ||
289 | #define pci_map_single(cookie, address, size, dir) virt_to_bus(address) | ||
290 | #define pci_unmap_single(cookie, address, size, dir) | ||
291 | |||
292 | #endif | ||
293 | |||
294 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43)) | ||
295 | |||
296 | #define dev_kfree_skb_any(a) dev_kfree_skb(a) | ||
297 | #define netif_down(dev) do { (dev)->start = 0; } while (0) | ||
298 | |||
299 | |||
300 | #ifndef _COMPAT_NETDEVICE_H | ||
301 | |||
302 | |||
303 | |||
304 | #define dev_kfree_skb_irq(a) dev_kfree_skb(a) | ||
305 | #define netif_wake_queue(dev) \ | ||
306 | do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0) | ||
307 | #define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy) | ||
308 | |||
309 | static inline void netif_start_queue(struct net_device *dev) | ||
310 | { | ||
311 | dev->tbusy = 0; | ||
312 | dev->interrupt = 0; | ||
313 | dev->start = 1; | ||
314 | } | ||
315 | |||
316 | #define netif_queue_stopped(dev) (dev)->tbusy | ||
317 | #define netif_running(dev) (dev)->start | ||
318 | |||
319 | #endif | ||
320 | |||
321 | #define netif_device_attach(dev) netif_start_queue(dev) | ||
322 | #define netif_device_detach(dev) netif_stop_queue(dev) | ||
323 | |||
324 | |||
325 | #define tasklet_struct tq_struct | ||
326 | static inline void tasklet_schedule(struct tasklet_struct *tasklet) | ||
327 | { | ||
328 | queue_task(tasklet, &tq_immediate); | ||
329 | mark_bh(IMMEDIATE_BH); | ||
330 | } | ||
331 | |||
332 | static inline void tasklet_init(struct tasklet_struct *tasklet, | ||
333 | void (*func)(unsigned long), | ||
334 | unsigned long data) | ||
335 | { | ||
336 | tasklet->next = NULL; | ||
337 | tasklet->sync = 0; | ||
338 | tasklet->routine = (void (*)(void *))func; | ||
339 | tasklet->data = (void *)data; | ||
340 | } | ||
341 | #define tasklet_kill(tasklet) { do {} while (0); } | ||
342 | |||
343 | |||
344 | #define del_timer_sync(timer) del_timer(timer) | ||
345 | |||
346 | #else | ||
347 | |||
348 | #define netif_down(dev) | ||
349 | |||
350 | #endif | ||
351 | |||
352 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3)) | ||
353 | |||
354 | |||
355 | #define PREPARE_TQUEUE(_tq, _routine, _data) \ | ||
356 | do { \ | ||
357 | (_tq)->routine = _routine; \ | ||
358 | (_tq)->data = _data; \ | ||
359 | } while (0) | ||
360 | |||
361 | |||
362 | #define INIT_TQUEUE(_tq, _routine, _data) \ | ||
363 | do { \ | ||
364 | INIT_LIST_HEAD(&(_tq)->list); \ | ||
365 | (_tq)->sync = 0; \ | ||
366 | PREPARE_TQUEUE((_tq), (_routine), (_data)); \ | ||
367 | } while (0) | ||
368 | |||
369 | #endif | ||
370 | |||
371 | |||
372 | #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 9) | ||
373 | #define PCI_SAVE_STATE(a, b) pci_save_state(a) | ||
374 | #define PCI_RESTORE_STATE(a, b) pci_restore_state(a) | ||
375 | #else | ||
376 | #define PCI_SAVE_STATE(a, b) pci_save_state(a, b) | ||
377 | #define PCI_RESTORE_STATE(a, b) pci_restore_state(a, b) | ||
378 | #endif | ||
379 | |||
380 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6)) | ||
381 | static inline int | ||
382 | pci_save_state(struct pci_dev *dev, u32 *buffer) | ||
383 | { | ||
384 | int i; | ||
385 | if (buffer) { | ||
386 | for (i = 0; i < 16; i++) | ||
387 | pci_read_config_dword(dev, i * 4, &buffer[i]); | ||
388 | } | ||
389 | return 0; | ||
390 | } | ||
391 | |||
392 | static inline int | ||
393 | pci_restore_state(struct pci_dev *dev, u32 *buffer) | ||
394 | { | ||
395 | int i; | ||
396 | |||
397 | if (buffer) { | ||
398 | for (i = 0; i < 16; i++) | ||
399 | pci_write_config_dword(dev, i * 4, buffer[i]); | ||
400 | } | ||
401 | |||
402 | else { | ||
403 | for (i = 0; i < 6; i ++) | ||
404 | pci_write_config_dword(dev, | ||
405 | PCI_BASE_ADDRESS_0 + (i * 4), | ||
406 | pci_resource_start(dev, i)); | ||
407 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | ||
408 | } | ||
409 | return 0; | ||
410 | } | ||
411 | #endif | ||
412 | |||
413 | |||
414 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19)) | ||
415 | #define read_c0_count() read_32bit_cp0_register(CP0_COUNT) | ||
416 | #endif | ||
417 | |||
418 | |||
419 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) | ||
420 | #ifndef SET_MODULE_OWNER | ||
421 | #define SET_MODULE_OWNER(dev) do {} while (0) | ||
422 | #define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT | ||
423 | #define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT | ||
424 | #else | ||
425 | #define OLD_MOD_INC_USE_COUNT do {} while (0) | ||
426 | #define OLD_MOD_DEC_USE_COUNT do {} while (0) | ||
427 | #endif | ||
428 | #else | ||
429 | #ifndef SET_MODULE_OWNER | ||
430 | #define SET_MODULE_OWNER(dev) do {} while (0) | ||
431 | #endif | ||
432 | #ifndef MOD_INC_USE_COUNT | ||
433 | #define MOD_INC_USE_COUNT do {} while (0) | ||
434 | #endif | ||
435 | #ifndef MOD_DEC_USE_COUNT | ||
436 | #define MOD_DEC_USE_COUNT do {} while (0) | ||
437 | #endif | ||
438 | #define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT | ||
439 | #define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT | ||
440 | #endif | ||
441 | |||
442 | #ifndef SET_NETDEV_DEV | ||
443 | #define SET_NETDEV_DEV(net, pdev) do {} while (0) | ||
444 | #endif | ||
445 | |||
446 | #ifndef HAVE_FREE_NETDEV | ||
447 | #define free_netdev(dev) kfree(dev) | ||
448 | #endif | ||
449 | |||
450 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) | ||
451 | |||
452 | #define af_packet_priv data | ||
453 | #endif | ||
454 | |||
455 | |||
456 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11) | ||
457 | #define DRV_SUSPEND_STATE_TYPE pm_message_t | ||
458 | #else | ||
459 | #define DRV_SUSPEND_STATE_TYPE uint32 | ||
460 | #endif | ||
461 | |||
462 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) | ||
463 | #define CHECKSUM_HW CHECKSUM_PARTIAL | ||
464 | #endif | ||
465 | |||
466 | typedef struct { | ||
467 | void *parent; | ||
468 | struct task_struct *p_task; | ||
469 | long thr_pid; | ||
470 | int prio; | ||
471 | struct semaphore sema; | ||
472 | bool terminated; | ||
473 | struct completion completed; | ||
474 | } tsk_ctl_t; | ||
475 | |||
476 | |||
477 | |||
478 | |||
479 | #ifdef DHD_DEBUG | ||
480 | #define DBG_THR(x) printk x | ||
481 | #else | ||
482 | #define DBG_THR(x) | ||
483 | #endif | ||
484 | |||
485 | #define SMP_RD_BARRIER_DEPENDS(x) smp_rmb(x) | ||
486 | |||
487 | |||
488 | #define PROC_START(thread_func, owner, tsk_ctl, flags) \ | ||
489 | { \ | ||
490 | sema_init(&((tsk_ctl)->sema), 0); \ | ||
491 | init_completion(&((tsk_ctl)->completed)); \ | ||
492 | (tsk_ctl)->parent = owner; \ | ||
493 | (tsk_ctl)->terminated = FALSE; \ | ||
494 | (tsk_ctl)->thr_pid = kernel_thread(thread_func, tsk_ctl, flags); \ | ||
495 | if ((tsk_ctl)->thr_pid > 0) \ | ||
496 | wait_for_completion(&((tsk_ctl)->completed)); \ | ||
497 | DBG_THR(("%s thr:%lx started\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ | ||
498 | } | ||
499 | |||
500 | #define PROC_STOP(tsk_ctl) \ | ||
501 | { \ | ||
502 | (tsk_ctl)->terminated = TRUE; \ | ||
503 | smp_wmb(); \ | ||
504 | up(&((tsk_ctl)->sema)); \ | ||
505 | wait_for_completion(&((tsk_ctl)->completed)); \ | ||
506 | DBG_THR(("%s thr:%lx terminated OK\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ | ||
507 | (tsk_ctl)->thr_pid = -1; \ | ||
508 | } | ||
509 | |||
510 | |||
511 | |||
512 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) | ||
513 | #define KILL_PROC(nr, sig) \ | ||
514 | { \ | ||
515 | struct task_struct *tsk; \ | ||
516 | struct pid *pid; \ | ||
517 | pid = find_get_pid((pid_t)nr); \ | ||
518 | tsk = pid_task(pid, PIDTYPE_PID); \ | ||
519 | if (tsk) send_sig(sig, tsk, 1); \ | ||
520 | } | ||
521 | #else | ||
522 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \ | ||
523 | KERNEL_VERSION(2, 6, 30)) | ||
524 | #define KILL_PROC(pid, sig) \ | ||
525 | { \ | ||
526 | struct task_struct *tsk; \ | ||
527 | tsk = find_task_by_vpid(pid); \ | ||
528 | if (tsk) send_sig(sig, tsk, 1); \ | ||
529 | } | ||
530 | #else | ||
531 | #define KILL_PROC(pid, sig) \ | ||
532 | { \ | ||
533 | kill_proc(pid, sig, 1); \ | ||
534 | } | ||
535 | #endif | ||
536 | #endif | ||
537 | |||
538 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) | ||
539 | #include <linux/time.h> | ||
540 | #include <linux/wait.h> | ||
541 | #else | ||
542 | #include <linux/sched.h> | ||
543 | |||
544 | #define __wait_event_interruptible_timeout(wq, condition, ret) \ | ||
545 | do { \ | ||
546 | wait_queue_t __wait; \ | ||
547 | init_waitqueue_entry(&__wait, current); \ | ||
548 | \ | ||
549 | add_wait_queue(&wq, &__wait); \ | ||
550 | for (;;) { \ | ||
551 | set_current_state(TASK_INTERRUPTIBLE); \ | ||
552 | if (condition) \ | ||
553 | break; \ | ||
554 | if (!signal_pending(current)) { \ | ||
555 | ret = schedule_timeout(ret); \ | ||
556 | if (!ret) \ | ||
557 | break; \ | ||
558 | continue; \ | ||
559 | } \ | ||
560 | ret = -ERESTARTSYS; \ | ||
561 | break; \ | ||
562 | } \ | ||
563 | current->state = TASK_RUNNING; \ | ||
564 | remove_wait_queue(&wq, &__wait); \ | ||
565 | } while (0) | ||
566 | |||
567 | #define wait_event_interruptible_timeout(wq, condition, timeout) \ | ||
568 | ({ \ | ||
569 | long __ret = timeout; \ | ||
570 | if (!(condition)) \ | ||
571 | __wait_event_interruptible_timeout(wq, condition, __ret); \ | ||
572 | __ret; \ | ||
573 | }) | ||
574 | |||
575 | #endif | ||
576 | |||
577 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29) | ||
578 | #define WL_DEV_IF(dev) ((wl_if_t*)netdev_priv(dev)) | ||
579 | #else | ||
580 | #define WL_DEV_IF(dev) ((wl_if_t*)(dev)->priv) | ||
581 | #endif | ||
582 | |||
583 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20) | ||
584 | #define WL_ISR(i, d, p) wl_isr((i), (d)) | ||
585 | #else | ||
586 | #define WL_ISR(i, d, p) wl_isr((i), (d), (p)) | ||
587 | #endif | ||
588 | |||
589 | #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) | ||
590 | #define netdev_priv(dev) dev->priv | ||
591 | #endif | ||
592 | |||
593 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/miniopt.h b/drivers/net/wireless/bcmdhd/include/miniopt.h new file mode 100644 index 00000000000..f468420f534 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/miniopt.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * Command line options parser. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * $Id: miniopt.h,v 1.3 2009-01-15 00:06:54 Exp $ | ||
24 | */ | ||
25 | |||
26 | |||
27 | #ifndef MINI_OPT_H | ||
28 | #define MINI_OPT_H | ||
29 | |||
30 | #ifdef __cplusplus | ||
31 | extern "C" { | ||
32 | #endif | ||
33 | |||
34 | /* ---- Include Files ---------------------------------------------------- */ | ||
35 | /* ---- Constants and Types ---------------------------------------------- */ | ||
36 | |||
37 | #define MINIOPT_MAXKEY 128 /* Max options */ | ||
38 | typedef struct miniopt { | ||
39 | |||
40 | /* These are persistent after miniopt_init() */ | ||
41 | const char* name; /* name for prompt in error strings */ | ||
42 | const char* flags; /* option chars that take no args */ | ||
43 | bool longflags; /* long options may be flags */ | ||
44 | bool opt_end; /* at end of options (passed a "--") */ | ||
45 | |||
46 | /* These are per-call to miniopt() */ | ||
47 | |||
48 | int consumed; /* number of argv entries cosumed in | ||
49 | * the most recent call to miniopt() | ||
50 | */ | ||
51 | bool positional; | ||
52 | bool good_int; /* 'val' member is the result of a sucessful | ||
53 | * strtol conversion of the option value | ||
54 | */ | ||
55 | char opt; | ||
56 | char key[MINIOPT_MAXKEY]; | ||
57 | char* valstr; /* positional param, or value for the option, | ||
58 | * or null if the option had | ||
59 | * no accompanying value | ||
60 | */ | ||
61 | uint uval; /* strtol translation of valstr */ | ||
62 | int val; /* strtol translation of valstr */ | ||
63 | } miniopt_t; | ||
64 | |||
65 | void miniopt_init(miniopt_t *t, const char* name, const char* flags, bool longflags); | ||
66 | int miniopt(miniopt_t *t, char **argv); | ||
67 | |||
68 | |||
69 | /* ---- Variable Externs ------------------------------------------------- */ | ||
70 | /* ---- Function Prototypes ---------------------------------------------- */ | ||
71 | |||
72 | |||
73 | #ifdef __cplusplus | ||
74 | } | ||
75 | #endif | ||
76 | |||
77 | #endif /* MINI_OPT_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/msgtrace.h b/drivers/net/wireless/bcmdhd/include/msgtrace.h new file mode 100644 index 00000000000..721d42100f2 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/msgtrace.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Trace messages sent over HBUS | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: msgtrace.h,v 1.4 2009-04-10 04:15:32 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _MSGTRACE_H | ||
28 | #define _MSGTRACE_H | ||
29 | |||
30 | #ifndef _TYPEDEFS_H_ | ||
31 | #include <typedefs.h> | ||
32 | #endif | ||
33 | |||
34 | |||
35 | /* This marks the start of a packed structure section. */ | ||
36 | #include <packed_section_start.h> | ||
37 | |||
38 | #define MSGTRACE_VERSION 1 | ||
39 | |||
40 | /* Message trace header */ | ||
41 | typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr { | ||
42 | uint8 version; | ||
43 | uint8 spare; | ||
44 | uint16 len; /* Len of the trace */ | ||
45 | uint32 seqnum; /* Sequence number of message. Useful if the messsage has been lost | ||
46 | * because of DMA error or a bus reset (ex: SDIO Func2) | ||
47 | */ | ||
48 | uint32 discarded_bytes; /* Number of discarded bytes because of trace overflow */ | ||
49 | uint32 discarded_printf; /* Number of discarded printf because of trace overflow */ | ||
50 | } BWL_POST_PACKED_STRUCT msgtrace_hdr_t; | ||
51 | |||
52 | #define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t) | ||
53 | |||
54 | /* The hbus driver generates traces when sending a trace message. This causes endless traces. | ||
55 | * This flag must be set to TRUE in any hbus traces. The flag is reset in the function msgtrace_put. | ||
56 | * This prevents endless traces but generates hasardous lost of traces only in bus device code. | ||
57 | * It is recommendat to set this flag in macro SD_TRACE but not in SD_ERROR for avoiding missing | ||
58 | * hbus error traces. hbus error trace should not generates endless traces. | ||
59 | */ | ||
60 | extern bool msgtrace_hbus_trace; | ||
61 | |||
62 | typedef void (*msgtrace_func_send_t)(void *hdl1, void *hdl2, uint8 *hdr, | ||
63 | uint16 hdrlen, uint8 *buf, uint16 buflen); | ||
64 | extern void msgtrace_start(void); | ||
65 | extern void msgtrace_stop(void); | ||
66 | extern void msgtrace_sent(void); | ||
67 | extern void msgtrace_put(char *buf, int count); | ||
68 | extern void msgtrace_init(void *hdl1, void *hdl2, msgtrace_func_send_t func_send); | ||
69 | extern bool msgtrace_event_enabled(void); | ||
70 | |||
71 | /* This marks the end of a packed structure section. */ | ||
72 | #include <packed_section_end.h> | ||
73 | |||
74 | #endif /* _MSGTRACE_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/osl.h b/drivers/net/wireless/bcmdhd/include/osl.h new file mode 100644 index 00000000000..80248ee7604 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/osl.h | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * OS Abstraction Layer | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: osl.h,v 13.44.96.1 2010-05-20 11:09:18 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _osl_h_ | ||
29 | #define _osl_h_ | ||
30 | |||
31 | |||
32 | typedef struct osl_info osl_t; | ||
33 | typedef struct osl_dmainfo osldma_t; | ||
34 | |||
35 | #define OSL_PKTTAG_SZ 32 | ||
36 | |||
37 | |||
38 | typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status); | ||
39 | |||
40 | |||
41 | #include <linux_osl.h> | ||
42 | |||
43 | #ifndef PKTDBG_TRACE | ||
44 | #define PKTDBG_TRACE(osh, pkt, bit) | ||
45 | #endif | ||
46 | |||
47 | |||
48 | |||
49 | #define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val))) | ||
50 | |||
51 | #ifndef AND_REG | ||
52 | #define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v)) | ||
53 | #endif | ||
54 | |||
55 | #ifndef OR_REG | ||
56 | #define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v)) | ||
57 | #endif | ||
58 | |||
59 | #if !defined(OSL_SYSUPTIME) | ||
60 | #define OSL_SYSUPTIME() (0) | ||
61 | #define OSL_SYSUPTIME_SUPPORT FALSE | ||
62 | #else | ||
63 | #define OSL_SYSUPTIME_SUPPORT TRUE | ||
64 | #endif | ||
65 | |||
66 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/packed_section_end.h b/drivers/net/wireless/bcmdhd/include/packed_section_end.h new file mode 100644 index 00000000000..5d4a8767807 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/packed_section_end.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * Declare directives for structure packing. No padding will be provided | ||
3 | * between the members of packed structures, and therefore, there is no | ||
4 | * guarantee that structure members will be aligned. | ||
5 | * | ||
6 | * Declaring packed structures is compiler specific. In order to handle all | ||
7 | * cases, packed structures should be delared as: | ||
8 | * | ||
9 | * #include <packed_section_start.h> | ||
10 | * | ||
11 | * typedef BWL_PRE_PACKED_STRUCT struct foobar_t { | ||
12 | * some_struct_members; | ||
13 | * } BWL_POST_PACKED_STRUCT foobar_t; | ||
14 | * | ||
15 | * #include <packed_section_end.h> | ||
16 | * | ||
17 | * | ||
18 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
19 | * | ||
20 | * Unless you and Broadcom execute a separate written software license | ||
21 | * agreement governing use of this software, this software is licensed to you | ||
22 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
23 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
24 | * following added to such license: | ||
25 | * | ||
26 | * As a special exception, the copyright holders of this software give you | ||
27 | * permission to link this software with independent modules, and to copy and | ||
28 | * distribute the resulting executable under terms of your choice, provided that | ||
29 | * you also meet, for each linked independent module, the terms and conditions of | ||
30 | * the license of that module. An independent module is a module which is not | ||
31 | * derived from this software. The special exception does not apply to any | ||
32 | * modifications of the software. | ||
33 | * | ||
34 | * Notwithstanding the above, under no circumstances may you combine this | ||
35 | * software in any way with any other Broadcom software provided under a license | ||
36 | * other than the GPL, without Broadcom's express prior written consent. | ||
37 | * $Id: packed_section_end.h,v 1.4 2008-12-09 23:43:22 Exp $ | ||
38 | */ | ||
39 | |||
40 | |||
41 | |||
42 | |||
43 | #ifdef BWL_PACKED_SECTION | ||
44 | #undef BWL_PACKED_SECTION | ||
45 | #else | ||
46 | #error "BWL_PACKED_SECTION is NOT defined!" | ||
47 | #endif | ||
48 | |||
49 | |||
50 | |||
51 | |||
52 | |||
53 | #undef BWL_PRE_PACKED_STRUCT | ||
54 | #undef BWL_POST_PACKED_STRUCT | ||
diff --git a/drivers/net/wireless/bcmdhd/include/packed_section_start.h b/drivers/net/wireless/bcmdhd/include/packed_section_start.h new file mode 100644 index 00000000000..da2fed68afa --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/packed_section_start.h | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | * Declare directives for structure packing. No padding will be provided | ||
3 | * between the members of packed structures, and therefore, there is no | ||
4 | * guarantee that structure members will be aligned. | ||
5 | * | ||
6 | * Declaring packed structures is compiler specific. In order to handle all | ||
7 | * cases, packed structures should be delared as: | ||
8 | * | ||
9 | * #include <packed_section_start.h> | ||
10 | * | ||
11 | * typedef BWL_PRE_PACKED_STRUCT struct foobar_t { | ||
12 | * some_struct_members; | ||
13 | * } BWL_POST_PACKED_STRUCT foobar_t; | ||
14 | * | ||
15 | * #include <packed_section_end.h> | ||
16 | * | ||
17 | * | ||
18 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
19 | * | ||
20 | * Unless you and Broadcom execute a separate written software license | ||
21 | * agreement governing use of this software, this software is licensed to you | ||
22 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
23 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
24 | * following added to such license: | ||
25 | * | ||
26 | * As a special exception, the copyright holders of this software give you | ||
27 | * permission to link this software with independent modules, and to copy and | ||
28 | * distribute the resulting executable under terms of your choice, provided that | ||
29 | * you also meet, for each linked independent module, the terms and conditions of | ||
30 | * the license of that module. An independent module is a module which is not | ||
31 | * derived from this software. The special exception does not apply to any | ||
32 | * modifications of the software. | ||
33 | * | ||
34 | * Notwithstanding the above, under no circumstances may you combine this | ||
35 | * software in any way with any other Broadcom software provided under a license | ||
36 | * other than the GPL, without Broadcom's express prior written consent. | ||
37 | * $Id: packed_section_start.h,v 1.4.124.1 2010-09-17 00:47:03 Exp $ | ||
38 | */ | ||
39 | |||
40 | |||
41 | |||
42 | |||
43 | #ifdef BWL_PACKED_SECTION | ||
44 | #error "BWL_PACKED_SECTION is already defined!" | ||
45 | #else | ||
46 | #define BWL_PACKED_SECTION | ||
47 | #endif | ||
48 | |||
49 | |||
50 | |||
51 | |||
52 | |||
53 | #if defined(__GNUC__) | ||
54 | #define BWL_PRE_PACKED_STRUCT | ||
55 | #define BWL_POST_PACKED_STRUCT __attribute__ ((packed)) | ||
56 | #elif defined(__CC_ARM) | ||
57 | #define BWL_PRE_PACKED_STRUCT __packed | ||
58 | #define BWL_POST_PACKED_STRUCT | ||
59 | #else | ||
60 | #error "Unknown compiler!" | ||
61 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/pcicfg.h b/drivers/net/wireless/bcmdhd/include/pcicfg.h new file mode 100644 index 00000000000..fae063a72f1 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/pcicfg.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * pcicfg.h: PCI configuration constants and structures. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: pcicfg.h,v 1.50 2009-12-07 21:56:06 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _h_pcicfg_ | ||
29 | #define _h_pcicfg_ | ||
30 | |||
31 | |||
32 | #define PCI_CFG_VID 0 | ||
33 | #define PCI_CFG_CMD 4 | ||
34 | #define PCI_CFG_REV 8 | ||
35 | #define PCI_CFG_BAR0 0x10 | ||
36 | #define PCI_CFG_BAR1 0x14 | ||
37 | #define PCI_BAR0_WIN 0x80 | ||
38 | #define PCI_INT_STATUS 0x90 | ||
39 | #define PCI_INT_MASK 0x94 | ||
40 | |||
41 | #define PCIE_EXTCFG_OFFSET 0x100 | ||
42 | #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) | ||
43 | #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) | ||
44 | |||
45 | #define PCI_BAR0_WINSZ (16 * 1024) | ||
46 | |||
47 | |||
48 | #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) | ||
49 | #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) | ||
50 | #define PCI_16KBB0_WINSZ (16 * 1024) | ||
51 | |||
52 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/802.11.h b/drivers/net/wireless/bcmdhd/include/proto/802.11.h new file mode 100644 index 00000000000..2342cb38314 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/802.11.h | |||
@@ -0,0 +1,1731 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * | ||
22 | * Fundamental types and constants relating to 802.11 | ||
23 | * | ||
24 | * $Id: 802.11.h,v 9.260.2.6 2010-12-15 21:41:14 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _802_11_H_ | ||
29 | #define _802_11_H_ | ||
30 | |||
31 | #ifndef _TYPEDEFS_H_ | ||
32 | #include <typedefs.h> | ||
33 | #endif | ||
34 | |||
35 | #ifndef _NET_ETHERNET_H_ | ||
36 | #include <proto/ethernet.h> | ||
37 | #endif | ||
38 | |||
39 | #include <proto/wpa.h> | ||
40 | |||
41 | |||
42 | #include <packed_section_start.h> | ||
43 | |||
44 | |||
45 | #define DOT11_TU_TO_US 1024 | ||
46 | |||
47 | |||
48 | #define DOT11_A3_HDR_LEN 24 | ||
49 | #define DOT11_A4_HDR_LEN 30 | ||
50 | #define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN | ||
51 | #define DOT11_FCS_LEN 4 | ||
52 | #define DOT11_ICV_LEN 4 | ||
53 | #define DOT11_ICV_AES_LEN 8 | ||
54 | #define DOT11_QOS_LEN 2 | ||
55 | #define DOT11_HTC_LEN 4 | ||
56 | |||
57 | #define DOT11_KEY_INDEX_SHIFT 6 | ||
58 | #define DOT11_IV_LEN 4 | ||
59 | #define DOT11_IV_TKIP_LEN 8 | ||
60 | #define DOT11_IV_AES_OCB_LEN 4 | ||
61 | #define DOT11_IV_AES_CCM_LEN 8 | ||
62 | #define DOT11_IV_MAX_LEN 8 | ||
63 | |||
64 | |||
65 | #define DOT11_MAX_MPDU_BODY_LEN 2304 | ||
66 | |||
67 | #define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \ | ||
68 | DOT11_QOS_LEN + \ | ||
69 | DOT11_IV_AES_CCM_LEN + \ | ||
70 | DOT11_MAX_MPDU_BODY_LEN + \ | ||
71 | DOT11_ICV_LEN + \ | ||
72 | DOT11_FCS_LEN) | ||
73 | |||
74 | #define DOT11_MAX_SSID_LEN 32 | ||
75 | |||
76 | |||
77 | #define DOT11_DEFAULT_RTS_LEN 2347 | ||
78 | #define DOT11_MAX_RTS_LEN 2347 | ||
79 | |||
80 | |||
81 | #define DOT11_MIN_FRAG_LEN 256 | ||
82 | #define DOT11_MAX_FRAG_LEN 2346 | ||
83 | #define DOT11_DEFAULT_FRAG_LEN 2346 | ||
84 | |||
85 | |||
86 | #define DOT11_MIN_BEACON_PERIOD 1 | ||
87 | #define DOT11_MAX_BEACON_PERIOD 0xFFFF | ||
88 | |||
89 | |||
90 | #define DOT11_MIN_DTIM_PERIOD 1 | ||
91 | #define DOT11_MAX_DTIM_PERIOD 0xFF | ||
92 | |||
93 | |||
94 | #define DOT11_LLC_SNAP_HDR_LEN 8 | ||
95 | #define DOT11_OUI_LEN 3 | ||
96 | BWL_PRE_PACKED_STRUCT struct dot11_llc_snap_header { | ||
97 | uint8 dsap; | ||
98 | uint8 ssap; | ||
99 | uint8 ctl; | ||
100 | uint8 oui[DOT11_OUI_LEN]; | ||
101 | uint16 type; | ||
102 | } BWL_POST_PACKED_STRUCT; | ||
103 | |||
104 | |||
105 | #define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN) | ||
106 | |||
107 | |||
108 | |||
109 | BWL_PRE_PACKED_STRUCT struct dot11_header { | ||
110 | uint16 fc; | ||
111 | uint16 durid; | ||
112 | struct ether_addr a1; | ||
113 | struct ether_addr a2; | ||
114 | struct ether_addr a3; | ||
115 | uint16 seq; | ||
116 | struct ether_addr a4; | ||
117 | } BWL_POST_PACKED_STRUCT; | ||
118 | |||
119 | |||
120 | |||
121 | BWL_PRE_PACKED_STRUCT struct dot11_rts_frame { | ||
122 | uint16 fc; | ||
123 | uint16 durid; | ||
124 | struct ether_addr ra; | ||
125 | struct ether_addr ta; | ||
126 | } BWL_POST_PACKED_STRUCT; | ||
127 | #define DOT11_RTS_LEN 16 | ||
128 | |||
129 | BWL_PRE_PACKED_STRUCT struct dot11_cts_frame { | ||
130 | uint16 fc; | ||
131 | uint16 durid; | ||
132 | struct ether_addr ra; | ||
133 | } BWL_POST_PACKED_STRUCT; | ||
134 | #define DOT11_CTS_LEN 10 | ||
135 | |||
136 | BWL_PRE_PACKED_STRUCT struct dot11_ack_frame { | ||
137 | uint16 fc; | ||
138 | uint16 durid; | ||
139 | struct ether_addr ra; | ||
140 | } BWL_POST_PACKED_STRUCT; | ||
141 | #define DOT11_ACK_LEN 10 | ||
142 | |||
143 | BWL_PRE_PACKED_STRUCT struct dot11_ps_poll_frame { | ||
144 | uint16 fc; | ||
145 | uint16 durid; | ||
146 | struct ether_addr bssid; | ||
147 | struct ether_addr ta; | ||
148 | } BWL_POST_PACKED_STRUCT; | ||
149 | #define DOT11_PS_POLL_LEN 16 | ||
150 | |||
151 | BWL_PRE_PACKED_STRUCT struct dot11_cf_end_frame { | ||
152 | uint16 fc; | ||
153 | uint16 durid; | ||
154 | struct ether_addr ra; | ||
155 | struct ether_addr bssid; | ||
156 | } BWL_POST_PACKED_STRUCT; | ||
157 | #define DOT11_CS_END_LEN 16 | ||
158 | |||
159 | |||
160 | BWL_PRE_PACKED_STRUCT struct dot11_action_wifi_vendor_specific { | ||
161 | uint8 category; | ||
162 | uint8 OUI[3]; | ||
163 | uint8 type; | ||
164 | uint8 subtype; | ||
165 | uint8 data[1040]; | ||
166 | } BWL_POST_PACKED_STRUCT; | ||
167 | typedef struct dot11_action_wifi_vendor_specific dot11_action_wifi_vendor_specific_t; | ||
168 | |||
169 | |||
170 | BWL_PRE_PACKED_STRUCT struct dot11_action_vs_frmhdr { | ||
171 | uint8 category; | ||
172 | uint8 OUI[3]; | ||
173 | uint8 type; | ||
174 | uint8 subtype; | ||
175 | uint8 data[1]; | ||
176 | } BWL_POST_PACKED_STRUCT; | ||
177 | typedef struct dot11_action_vs_frmhdr dot11_action_vs_frmhdr_t; | ||
178 | #define DOT11_ACTION_VS_HDR_LEN 6 | ||
179 | |||
180 | #define BCM_ACTION_OUI_BYTE0 0x00 | ||
181 | #define BCM_ACTION_OUI_BYTE1 0x90 | ||
182 | #define BCM_ACTION_OUI_BYTE2 0x4c | ||
183 | |||
184 | |||
185 | #define DOT11_BA_CTL_POLICY_NORMAL 0x0000 | ||
186 | #define DOT11_BA_CTL_POLICY_NOACK 0x0001 | ||
187 | #define DOT11_BA_CTL_POLICY_MASK 0x0001 | ||
188 | |||
189 | #define DOT11_BA_CTL_MTID 0x0002 | ||
190 | #define DOT11_BA_CTL_COMPRESSED 0x0004 | ||
191 | |||
192 | #define DOT11_BA_CTL_NUMMSDU_MASK 0x0FC0 | ||
193 | #define DOT11_BA_CTL_NUMMSDU_SHIFT 6 | ||
194 | |||
195 | #define DOT11_BA_CTL_TID_MASK 0xF000 | ||
196 | #define DOT11_BA_CTL_TID_SHIFT 12 | ||
197 | |||
198 | |||
199 | BWL_PRE_PACKED_STRUCT struct dot11_ctl_header { | ||
200 | uint16 fc; | ||
201 | uint16 durid; | ||
202 | struct ether_addr ra; | ||
203 | struct ether_addr ta; | ||
204 | } BWL_POST_PACKED_STRUCT; | ||
205 | #define DOT11_CTL_HDR_LEN 16 | ||
206 | |||
207 | |||
208 | BWL_PRE_PACKED_STRUCT struct dot11_bar { | ||
209 | uint16 bar_control; | ||
210 | uint16 seqnum; | ||
211 | } BWL_POST_PACKED_STRUCT; | ||
212 | #define DOT11_BAR_LEN 4 | ||
213 | |||
214 | #define DOT11_BA_BITMAP_LEN 128 | ||
215 | #define DOT11_BA_CMP_BITMAP_LEN 8 | ||
216 | |||
217 | BWL_PRE_PACKED_STRUCT struct dot11_ba { | ||
218 | uint16 ba_control; | ||
219 | uint16 seqnum; | ||
220 | uint8 bitmap[DOT11_BA_BITMAP_LEN]; | ||
221 | } BWL_POST_PACKED_STRUCT; | ||
222 | #define DOT11_BA_LEN 4 | ||
223 | |||
224 | |||
225 | BWL_PRE_PACKED_STRUCT struct dot11_management_header { | ||
226 | uint16 fc; | ||
227 | uint16 durid; | ||
228 | struct ether_addr da; | ||
229 | struct ether_addr sa; | ||
230 | struct ether_addr bssid; | ||
231 | uint16 seq; | ||
232 | } BWL_POST_PACKED_STRUCT; | ||
233 | #define DOT11_MGMT_HDR_LEN 24 | ||
234 | |||
235 | |||
236 | |||
237 | BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb { | ||
238 | uint32 timestamp[2]; | ||
239 | uint16 beacon_interval; | ||
240 | uint16 capability; | ||
241 | } BWL_POST_PACKED_STRUCT; | ||
242 | #define DOT11_BCN_PRB_LEN 12 | ||
243 | #define DOT11_BCN_PRB_FIXED_LEN 12 | ||
244 | |||
245 | BWL_PRE_PACKED_STRUCT struct dot11_auth { | ||
246 | uint16 alg; | ||
247 | uint16 seq; | ||
248 | uint16 status; | ||
249 | } BWL_POST_PACKED_STRUCT; | ||
250 | #define DOT11_AUTH_FIXED_LEN 6 | ||
251 | |||
252 | BWL_PRE_PACKED_STRUCT struct dot11_assoc_req { | ||
253 | uint16 capability; | ||
254 | uint16 listen; | ||
255 | } BWL_POST_PACKED_STRUCT; | ||
256 | #define DOT11_ASSOC_REQ_FIXED_LEN 4 | ||
257 | |||
258 | BWL_PRE_PACKED_STRUCT struct dot11_reassoc_req { | ||
259 | uint16 capability; | ||
260 | uint16 listen; | ||
261 | struct ether_addr ap; | ||
262 | } BWL_POST_PACKED_STRUCT; | ||
263 | #define DOT11_REASSOC_REQ_FIXED_LEN 10 | ||
264 | |||
265 | BWL_PRE_PACKED_STRUCT struct dot11_assoc_resp { | ||
266 | uint16 capability; | ||
267 | uint16 status; | ||
268 | uint16 aid; | ||
269 | } BWL_POST_PACKED_STRUCT; | ||
270 | #define DOT11_ASSOC_RESP_FIXED_LEN 6 | ||
271 | |||
272 | BWL_PRE_PACKED_STRUCT struct dot11_action_measure { | ||
273 | uint8 category; | ||
274 | uint8 action; | ||
275 | uint8 token; | ||
276 | uint8 data[1]; | ||
277 | } BWL_POST_PACKED_STRUCT; | ||
278 | #define DOT11_ACTION_MEASURE_LEN 3 | ||
279 | |||
280 | BWL_PRE_PACKED_STRUCT struct dot11_action_ht_ch_width { | ||
281 | uint8 category; | ||
282 | uint8 action; | ||
283 | uint8 ch_width; | ||
284 | } BWL_POST_PACKED_STRUCT; | ||
285 | |||
286 | BWL_PRE_PACKED_STRUCT struct dot11_action_ht_mimops { | ||
287 | uint8 category; | ||
288 | uint8 action; | ||
289 | uint8 control; | ||
290 | } BWL_POST_PACKED_STRUCT; | ||
291 | |||
292 | #define SM_PWRSAVE_ENABLE 1 | ||
293 | #define SM_PWRSAVE_MODE 2 | ||
294 | |||
295 | |||
296 | BWL_PRE_PACKED_STRUCT struct dot11_power_cnst { | ||
297 | uint8 id; | ||
298 | uint8 len; | ||
299 | uint8 power; | ||
300 | } BWL_POST_PACKED_STRUCT; | ||
301 | typedef struct dot11_power_cnst dot11_power_cnst_t; | ||
302 | |||
303 | BWL_PRE_PACKED_STRUCT struct dot11_power_cap { | ||
304 | uint8 min; | ||
305 | uint8 max; | ||
306 | } BWL_POST_PACKED_STRUCT; | ||
307 | typedef struct dot11_power_cap dot11_power_cap_t; | ||
308 | |||
309 | BWL_PRE_PACKED_STRUCT struct dot11_tpc_rep { | ||
310 | uint8 id; | ||
311 | uint8 len; | ||
312 | uint8 tx_pwr; | ||
313 | uint8 margin; | ||
314 | } BWL_POST_PACKED_STRUCT; | ||
315 | typedef struct dot11_tpc_rep dot11_tpc_rep_t; | ||
316 | #define DOT11_MNG_IE_TPC_REPORT_LEN 2 | ||
317 | |||
318 | BWL_PRE_PACKED_STRUCT struct dot11_supp_channels { | ||
319 | uint8 id; | ||
320 | uint8 len; | ||
321 | uint8 first_channel; | ||
322 | uint8 num_channels; | ||
323 | } BWL_POST_PACKED_STRUCT; | ||
324 | typedef struct dot11_supp_channels dot11_supp_channels_t; | ||
325 | |||
326 | |||
327 | BWL_PRE_PACKED_STRUCT struct dot11_extch { | ||
328 | uint8 id; | ||
329 | uint8 len; | ||
330 | uint8 extch; | ||
331 | } BWL_POST_PACKED_STRUCT; | ||
332 | typedef struct dot11_extch dot11_extch_ie_t; | ||
333 | |||
334 | BWL_PRE_PACKED_STRUCT struct dot11_brcm_extch { | ||
335 | uint8 id; | ||
336 | uint8 len; | ||
337 | uint8 oui[3]; | ||
338 | uint8 type; | ||
339 | uint8 extch; | ||
340 | } BWL_POST_PACKED_STRUCT; | ||
341 | typedef struct dot11_brcm_extch dot11_brcm_extch_ie_t; | ||
342 | |||
343 | #define BRCM_EXTCH_IE_LEN 5 | ||
344 | #define BRCM_EXTCH_IE_TYPE 53 | ||
345 | #define DOT11_EXTCH_IE_LEN 1 | ||
346 | #define DOT11_EXT_CH_MASK 0x03 | ||
347 | #define DOT11_EXT_CH_UPPER 0x01 | ||
348 | #define DOT11_EXT_CH_LOWER 0x03 | ||
349 | #define DOT11_EXT_CH_NONE 0x00 | ||
350 | |||
351 | BWL_PRE_PACKED_STRUCT struct dot11_action_frmhdr { | ||
352 | uint8 category; | ||
353 | uint8 action; | ||
354 | uint8 data[1]; | ||
355 | } BWL_POST_PACKED_STRUCT; | ||
356 | #define DOT11_ACTION_FRMHDR_LEN 2 | ||
357 | |||
358 | |||
359 | BWL_PRE_PACKED_STRUCT struct dot11_channel_switch { | ||
360 | uint8 id; | ||
361 | uint8 len; | ||
362 | uint8 mode; | ||
363 | uint8 channel; | ||
364 | uint8 count; | ||
365 | } BWL_POST_PACKED_STRUCT; | ||
366 | typedef struct dot11_channel_switch dot11_chan_switch_ie_t; | ||
367 | |||
368 | #define DOT11_SWITCH_IE_LEN 3 | ||
369 | |||
370 | #define DOT11_CSA_MODE_ADVISORY 0 | ||
371 | #define DOT11_CSA_MODE_NO_TX 1 | ||
372 | |||
373 | BWL_PRE_PACKED_STRUCT struct dot11_action_switch_channel { | ||
374 | uint8 category; | ||
375 | uint8 action; | ||
376 | dot11_chan_switch_ie_t chan_switch_ie; | ||
377 | dot11_brcm_extch_ie_t extch_ie; | ||
378 | } BWL_POST_PACKED_STRUCT; | ||
379 | |||
380 | BWL_PRE_PACKED_STRUCT struct dot11_csa_body { | ||
381 | uint8 mode; | ||
382 | uint8 reg; | ||
383 | uint8 channel; | ||
384 | uint8 count; | ||
385 | } BWL_POST_PACKED_STRUCT; | ||
386 | |||
387 | |||
388 | BWL_PRE_PACKED_STRUCT struct dot11_ext_csa { | ||
389 | uint8 id; | ||
390 | uint8 len; | ||
391 | struct dot11_csa_body b; | ||
392 | } BWL_POST_PACKED_STRUCT; | ||
393 | typedef struct dot11_ext_csa dot11_ext_csa_ie_t; | ||
394 | #define DOT11_EXT_CSA_IE_LEN 4 | ||
395 | |||
396 | BWL_PRE_PACKED_STRUCT struct dot11_action_ext_csa { | ||
397 | uint8 category; | ||
398 | uint8 action; | ||
399 | dot11_ext_csa_ie_t chan_switch_ie; | ||
400 | } BWL_POST_PACKED_STRUCT; | ||
401 | |||
402 | BWL_PRE_PACKED_STRUCT struct dot11y_action_ext_csa { | ||
403 | uint8 category; | ||
404 | uint8 action; | ||
405 | struct dot11_csa_body b; | ||
406 | } BWL_POST_PACKED_STRUCT; | ||
407 | |||
408 | BWL_PRE_PACKED_STRUCT struct dot11_obss_coex { | ||
409 | uint8 id; | ||
410 | uint8 len; | ||
411 | uint8 info; | ||
412 | } BWL_POST_PACKED_STRUCT; | ||
413 | typedef struct dot11_obss_coex dot11_obss_coex_t; | ||
414 | #define DOT11_OBSS_COEXINFO_LEN 1 | ||
415 | |||
416 | #define DOT11_OBSS_COEX_INFO_REQ 0x01 | ||
417 | #define DOT11_OBSS_COEX_40MHZ_INTOLERANT 0x02 | ||
418 | #define DOT11_OBSS_COEX_20MHZ_WIDTH_REQ 0x04 | ||
419 | |||
420 | BWL_PRE_PACKED_STRUCT struct dot11_obss_chanlist { | ||
421 | uint8 id; | ||
422 | uint8 len; | ||
423 | uint8 regclass; | ||
424 | uint8 chanlist[1]; | ||
425 | } BWL_POST_PACKED_STRUCT; | ||
426 | typedef struct dot11_obss_chanlist dot11_obss_chanlist_t; | ||
427 | #define DOT11_OBSS_CHANLIST_FIXED_LEN 1 | ||
428 | |||
429 | BWL_PRE_PACKED_STRUCT struct dot11_extcap_ie { | ||
430 | uint8 id; | ||
431 | uint8 len; | ||
432 | uint8 cap; | ||
433 | } BWL_POST_PACKED_STRUCT; | ||
434 | typedef struct dot11_extcap_ie dot11_extcap_ie_t; | ||
435 | #define DOT11_EXTCAP_LEN 1 | ||
436 | |||
437 | |||
438 | |||
439 | #define DOT11_MEASURE_TYPE_BASIC 0 | ||
440 | #define DOT11_MEASURE_TYPE_CCA 1 | ||
441 | #define DOT11_MEASURE_TYPE_RPI 2 | ||
442 | #define DOT11_MEASURE_TYPE_CHLOAD 3 | ||
443 | #define DOT11_MEASURE_TYPE_NOISE 4 | ||
444 | #define DOT11_MEASURE_TYPE_BEACON 5 | ||
445 | #define DOT11_MEASURE_TYPE_FRAME 6 | ||
446 | #define DOT11_MEASURE_TYPE_STATS 7 | ||
447 | #define DOT11_MEASURE_TYPE_LCI 8 | ||
448 | #define DOT11_MEASURE_TYPE_TXSTREAM 9 | ||
449 | #define DOT11_MEASURE_TYPE_PAUSE 255 | ||
450 | |||
451 | |||
452 | #define DOT11_MEASURE_MODE_PARALLEL (1<<0) | ||
453 | #define DOT11_MEASURE_MODE_ENABLE (1<<1) | ||
454 | #define DOT11_MEASURE_MODE_REQUEST (1<<2) | ||
455 | #define DOT11_MEASURE_MODE_REPORT (1<<3) | ||
456 | #define DOT11_MEASURE_MODE_DUR (1<<4) | ||
457 | |||
458 | #define DOT11_MEASURE_MODE_LATE (1<<0) | ||
459 | #define DOT11_MEASURE_MODE_INCAPABLE (1<<1) | ||
460 | #define DOT11_MEASURE_MODE_REFUSED (1<<2) | ||
461 | |||
462 | #define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0)) | ||
463 | #define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1)) | ||
464 | #define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2)) | ||
465 | #define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3)) | ||
466 | #define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4)) | ||
467 | |||
468 | BWL_PRE_PACKED_STRUCT struct dot11_meas_req { | ||
469 | uint8 id; | ||
470 | uint8 len; | ||
471 | uint8 token; | ||
472 | uint8 mode; | ||
473 | uint8 type; | ||
474 | uint8 channel; | ||
475 | uint8 start_time[8]; | ||
476 | uint16 duration; | ||
477 | } BWL_POST_PACKED_STRUCT; | ||
478 | typedef struct dot11_meas_req dot11_meas_req_t; | ||
479 | #define DOT11_MNG_IE_MREQ_LEN 14 | ||
480 | |||
481 | #define DOT11_MNG_IE_MREQ_FIXED_LEN 3 | ||
482 | |||
483 | BWL_PRE_PACKED_STRUCT struct dot11_meas_rep { | ||
484 | uint8 id; | ||
485 | uint8 len; | ||
486 | uint8 token; | ||
487 | uint8 mode; | ||
488 | uint8 type; | ||
489 | BWL_PRE_PACKED_STRUCT union | ||
490 | { | ||
491 | BWL_PRE_PACKED_STRUCT struct { | ||
492 | uint8 channel; | ||
493 | uint8 start_time[8]; | ||
494 | uint16 duration; | ||
495 | uint8 map; | ||
496 | } BWL_POST_PACKED_STRUCT basic; | ||
497 | uint8 data[1]; | ||
498 | } BWL_POST_PACKED_STRUCT rep; | ||
499 | } BWL_POST_PACKED_STRUCT; | ||
500 | typedef struct dot11_meas_rep dot11_meas_rep_t; | ||
501 | |||
502 | |||
503 | #define DOT11_MNG_IE_MREP_FIXED_LEN 3 | ||
504 | |||
505 | BWL_PRE_PACKED_STRUCT struct dot11_meas_rep_basic { | ||
506 | uint8 channel; | ||
507 | uint8 start_time[8]; | ||
508 | uint16 duration; | ||
509 | uint8 map; | ||
510 | } BWL_POST_PACKED_STRUCT; | ||
511 | typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t; | ||
512 | #define DOT11_MEASURE_BASIC_REP_LEN 12 | ||
513 | |||
514 | BWL_PRE_PACKED_STRUCT struct dot11_quiet { | ||
515 | uint8 id; | ||
516 | uint8 len; | ||
517 | uint8 count; | ||
518 | uint8 period; | ||
519 | uint16 duration; | ||
520 | uint16 offset; | ||
521 | } BWL_POST_PACKED_STRUCT; | ||
522 | typedef struct dot11_quiet dot11_quiet_t; | ||
523 | |||
524 | BWL_PRE_PACKED_STRUCT struct chan_map_tuple { | ||
525 | uint8 channel; | ||
526 | uint8 map; | ||
527 | } BWL_POST_PACKED_STRUCT; | ||
528 | typedef struct chan_map_tuple chan_map_tuple_t; | ||
529 | |||
530 | BWL_PRE_PACKED_STRUCT struct dot11_ibss_dfs { | ||
531 | uint8 id; | ||
532 | uint8 len; | ||
533 | uint8 eaddr[ETHER_ADDR_LEN]; | ||
534 | uint8 interval; | ||
535 | chan_map_tuple_t map[1]; | ||
536 | } BWL_POST_PACKED_STRUCT; | ||
537 | typedef struct dot11_ibss_dfs dot11_ibss_dfs_t; | ||
538 | |||
539 | |||
540 | #define WME_OUI "\x00\x50\xf2" | ||
541 | #define WME_OUI_LEN 3 | ||
542 | #define WME_OUI_TYPE 2 | ||
543 | #define WME_VER 1 | ||
544 | #define WME_TYPE 2 | ||
545 | #define WME_SUBTYPE_IE 0 | ||
546 | #define WME_SUBTYPE_PARAM_IE 1 | ||
547 | #define WME_SUBTYPE_TSPEC 2 | ||
548 | |||
549 | |||
550 | #define AC_BE 0 | ||
551 | #define AC_BK 1 | ||
552 | #define AC_VI 2 | ||
553 | #define AC_VO 3 | ||
554 | #define AC_COUNT 4 | ||
555 | |||
556 | typedef uint8 ac_bitmap_t; | ||
557 | |||
558 | #define AC_BITMAP_NONE 0x0 | ||
559 | #define AC_BITMAP_ALL 0xf | ||
560 | #define AC_BITMAP_TST(ab, ac) (((ab) & (1 << (ac))) != 0) | ||
561 | #define AC_BITMAP_SET(ab, ac) (((ab) |= (1 << (ac)))) | ||
562 | #define AC_BITMAP_RESET(ab, ac) (((ab) &= ~(1 << (ac)))) | ||
563 | |||
564 | |||
565 | BWL_PRE_PACKED_STRUCT struct wme_ie { | ||
566 | uint8 oui[3]; | ||
567 | uint8 type; | ||
568 | uint8 subtype; | ||
569 | uint8 version; | ||
570 | uint8 qosinfo; | ||
571 | } BWL_POST_PACKED_STRUCT; | ||
572 | typedef struct wme_ie wme_ie_t; | ||
573 | #define WME_IE_LEN 7 | ||
574 | |||
575 | BWL_PRE_PACKED_STRUCT struct edcf_acparam { | ||
576 | uint8 ACI; | ||
577 | uint8 ECW; | ||
578 | uint16 TXOP; | ||
579 | } BWL_POST_PACKED_STRUCT; | ||
580 | typedef struct edcf_acparam edcf_acparam_t; | ||
581 | |||
582 | |||
583 | BWL_PRE_PACKED_STRUCT struct wme_param_ie { | ||
584 | uint8 oui[3]; | ||
585 | uint8 type; | ||
586 | uint8 subtype; | ||
587 | uint8 version; | ||
588 | uint8 qosinfo; | ||
589 | uint8 rsvd; | ||
590 | edcf_acparam_t acparam[AC_COUNT]; | ||
591 | } BWL_POST_PACKED_STRUCT; | ||
592 | typedef struct wme_param_ie wme_param_ie_t; | ||
593 | #define WME_PARAM_IE_LEN 24 | ||
594 | |||
595 | |||
596 | #define WME_QI_AP_APSD_MASK 0x80 | ||
597 | #define WME_QI_AP_APSD_SHIFT 7 | ||
598 | #define WME_QI_AP_COUNT_MASK 0x0f | ||
599 | #define WME_QI_AP_COUNT_SHIFT 0 | ||
600 | |||
601 | |||
602 | #define WME_QI_STA_MAXSPLEN_MASK 0x60 | ||
603 | #define WME_QI_STA_MAXSPLEN_SHIFT 5 | ||
604 | #define WME_QI_STA_APSD_ALL_MASK 0xf | ||
605 | #define WME_QI_STA_APSD_ALL_SHIFT 0 | ||
606 | #define WME_QI_STA_APSD_BE_MASK 0x8 | ||
607 | #define WME_QI_STA_APSD_BE_SHIFT 3 | ||
608 | #define WME_QI_STA_APSD_BK_MASK 0x4 | ||
609 | #define WME_QI_STA_APSD_BK_SHIFT 2 | ||
610 | #define WME_QI_STA_APSD_VI_MASK 0x2 | ||
611 | #define WME_QI_STA_APSD_VI_SHIFT 1 | ||
612 | #define WME_QI_STA_APSD_VO_MASK 0x1 | ||
613 | #define WME_QI_STA_APSD_VO_SHIFT 0 | ||
614 | |||
615 | |||
616 | #define EDCF_AIFSN_MIN 1 | ||
617 | #define EDCF_AIFSN_MAX 15 | ||
618 | #define EDCF_AIFSN_MASK 0x0f | ||
619 | #define EDCF_ACM_MASK 0x10 | ||
620 | #define EDCF_ACI_MASK 0x60 | ||
621 | #define EDCF_ACI_SHIFT 5 | ||
622 | #define EDCF_AIFSN_SHIFT 12 | ||
623 | |||
624 | |||
625 | #define EDCF_ECW_MIN 0 | ||
626 | #define EDCF_ECW_MAX 15 | ||
627 | #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) | ||
628 | #define EDCF_ECWMIN_MASK 0x0f | ||
629 | #define EDCF_ECWMAX_MASK 0xf0 | ||
630 | #define EDCF_ECWMAX_SHIFT 4 | ||
631 | |||
632 | |||
633 | #define EDCF_TXOP_MIN 0 | ||
634 | #define EDCF_TXOP_MAX 65535 | ||
635 | #define EDCF_TXOP2USEC(txop) ((txop) << 5) | ||
636 | |||
637 | |||
638 | #define NON_EDCF_AC_BE_ACI_STA 0x02 | ||
639 | |||
640 | |||
641 | #define EDCF_AC_BE_ACI_STA 0x03 | ||
642 | #define EDCF_AC_BE_ECW_STA 0xA4 | ||
643 | #define EDCF_AC_BE_TXOP_STA 0x0000 | ||
644 | #define EDCF_AC_BK_ACI_STA 0x27 | ||
645 | #define EDCF_AC_BK_ECW_STA 0xA4 | ||
646 | #define EDCF_AC_BK_TXOP_STA 0x0000 | ||
647 | #define EDCF_AC_VI_ACI_STA 0x42 | ||
648 | #define EDCF_AC_VI_ECW_STA 0x43 | ||
649 | #define EDCF_AC_VI_TXOP_STA 0x005e | ||
650 | #define EDCF_AC_VO_ACI_STA 0x62 | ||
651 | #define EDCF_AC_VO_ECW_STA 0x32 | ||
652 | #define EDCF_AC_VO_TXOP_STA 0x002f | ||
653 | |||
654 | |||
655 | #define EDCF_AC_BE_ACI_AP 0x03 | ||
656 | #define EDCF_AC_BE_ECW_AP 0x64 | ||
657 | #define EDCF_AC_BE_TXOP_AP 0x0000 | ||
658 | #define EDCF_AC_BK_ACI_AP 0x27 | ||
659 | #define EDCF_AC_BK_ECW_AP 0xA4 | ||
660 | #define EDCF_AC_BK_TXOP_AP 0x0000 | ||
661 | #define EDCF_AC_VI_ACI_AP 0x41 | ||
662 | #define EDCF_AC_VI_ECW_AP 0x43 | ||
663 | #define EDCF_AC_VI_TXOP_AP 0x005e | ||
664 | #define EDCF_AC_VO_ACI_AP 0x61 | ||
665 | #define EDCF_AC_VO_ECW_AP 0x32 | ||
666 | #define EDCF_AC_VO_TXOP_AP 0x002f | ||
667 | |||
668 | |||
669 | BWL_PRE_PACKED_STRUCT struct edca_param_ie { | ||
670 | uint8 qosinfo; | ||
671 | uint8 rsvd; | ||
672 | edcf_acparam_t acparam[AC_COUNT]; | ||
673 | } BWL_POST_PACKED_STRUCT; | ||
674 | typedef struct edca_param_ie edca_param_ie_t; | ||
675 | #define EDCA_PARAM_IE_LEN 18 | ||
676 | |||
677 | |||
678 | BWL_PRE_PACKED_STRUCT struct qos_cap_ie { | ||
679 | uint8 qosinfo; | ||
680 | } BWL_POST_PACKED_STRUCT; | ||
681 | typedef struct qos_cap_ie qos_cap_ie_t; | ||
682 | |||
683 | BWL_PRE_PACKED_STRUCT struct dot11_qbss_load_ie { | ||
684 | uint8 id; | ||
685 | uint8 length; | ||
686 | uint16 station_count; | ||
687 | uint8 channel_utilization; | ||
688 | uint16 aac; | ||
689 | } BWL_POST_PACKED_STRUCT; | ||
690 | typedef struct dot11_qbss_load_ie dot11_qbss_load_ie_t; | ||
691 | |||
692 | |||
693 | #define FIXED_MSDU_SIZE 0x8000 | ||
694 | #define MSDU_SIZE_MASK 0x7fff | ||
695 | |||
696 | |||
697 | |||
698 | #define INTEGER_SHIFT 13 | ||
699 | #define FRACTION_MASK 0x1FFF | ||
700 | |||
701 | |||
702 | BWL_PRE_PACKED_STRUCT struct dot11_management_notification { | ||
703 | uint8 category; | ||
704 | uint8 action; | ||
705 | uint8 token; | ||
706 | uint8 status; | ||
707 | uint8 data[1]; | ||
708 | } BWL_POST_PACKED_STRUCT; | ||
709 | #define DOT11_MGMT_NOTIFICATION_LEN 4 | ||
710 | |||
711 | |||
712 | #define WME_ADDTS_REQUEST 0 | ||
713 | #define WME_ADDTS_RESPONSE 1 | ||
714 | #define WME_DELTS_REQUEST 2 | ||
715 | |||
716 | |||
717 | #define WME_ADMISSION_ACCEPTED 0 | ||
718 | #define WME_INVALID_PARAMETERS 1 | ||
719 | #define WME_ADMISSION_REFUSED 3 | ||
720 | |||
721 | |||
722 | #define BCN_PRB_SSID(body) ((char*)(body) + DOT11_BCN_PRB_LEN) | ||
723 | |||
724 | |||
725 | #define DOT11_OPEN_SYSTEM 0 | ||
726 | #define DOT11_SHARED_KEY 1 | ||
727 | #define DOT11_OPEN_SHARED 2 | ||
728 | #define DOT11_FAST_BSS 3 | ||
729 | #define DOT11_CHALLENGE_LEN 128 | ||
730 | |||
731 | |||
732 | #define FC_PVER_MASK 0x3 | ||
733 | #define FC_PVER_SHIFT 0 | ||
734 | #define FC_TYPE_MASK 0xC | ||
735 | #define FC_TYPE_SHIFT 2 | ||
736 | #define FC_SUBTYPE_MASK 0xF0 | ||
737 | #define FC_SUBTYPE_SHIFT 4 | ||
738 | #define FC_TODS 0x100 | ||
739 | #define FC_TODS_SHIFT 8 | ||
740 | #define FC_FROMDS 0x200 | ||
741 | #define FC_FROMDS_SHIFT 9 | ||
742 | #define FC_MOREFRAG 0x400 | ||
743 | #define FC_MOREFRAG_SHIFT 10 | ||
744 | #define FC_RETRY 0x800 | ||
745 | #define FC_RETRY_SHIFT 11 | ||
746 | #define FC_PM 0x1000 | ||
747 | #define FC_PM_SHIFT 12 | ||
748 | #define FC_MOREDATA 0x2000 | ||
749 | #define FC_MOREDATA_SHIFT 13 | ||
750 | #define FC_WEP 0x4000 | ||
751 | #define FC_WEP_SHIFT 14 | ||
752 | #define FC_ORDER 0x8000 | ||
753 | #define FC_ORDER_SHIFT 15 | ||
754 | |||
755 | |||
756 | #define SEQNUM_SHIFT 4 | ||
757 | #define SEQNUM_MAX 0x1000 | ||
758 | #define FRAGNUM_MASK 0xF | ||
759 | |||
760 | |||
761 | |||
762 | |||
763 | #define FC_TYPE_MNG 0 | ||
764 | #define FC_TYPE_CTL 1 | ||
765 | #define FC_TYPE_DATA 2 | ||
766 | |||
767 | |||
768 | #define FC_SUBTYPE_ASSOC_REQ 0 | ||
769 | #define FC_SUBTYPE_ASSOC_RESP 1 | ||
770 | #define FC_SUBTYPE_REASSOC_REQ 2 | ||
771 | #define FC_SUBTYPE_REASSOC_RESP 3 | ||
772 | #define FC_SUBTYPE_PROBE_REQ 4 | ||
773 | #define FC_SUBTYPE_PROBE_RESP 5 | ||
774 | #define FC_SUBTYPE_BEACON 8 | ||
775 | #define FC_SUBTYPE_ATIM 9 | ||
776 | #define FC_SUBTYPE_DISASSOC 10 | ||
777 | #define FC_SUBTYPE_AUTH 11 | ||
778 | #define FC_SUBTYPE_DEAUTH 12 | ||
779 | #define FC_SUBTYPE_ACTION 13 | ||
780 | #define FC_SUBTYPE_ACTION_NOACK 14 | ||
781 | |||
782 | |||
783 | #define FC_SUBTYPE_CTL_WRAPPER 7 | ||
784 | #define FC_SUBTYPE_BLOCKACK_REQ 8 | ||
785 | #define FC_SUBTYPE_BLOCKACK 9 | ||
786 | #define FC_SUBTYPE_PS_POLL 10 | ||
787 | #define FC_SUBTYPE_RTS 11 | ||
788 | #define FC_SUBTYPE_CTS 12 | ||
789 | #define FC_SUBTYPE_ACK 13 | ||
790 | #define FC_SUBTYPE_CF_END 14 | ||
791 | #define FC_SUBTYPE_CF_END_ACK 15 | ||
792 | |||
793 | |||
794 | #define FC_SUBTYPE_DATA 0 | ||
795 | #define FC_SUBTYPE_DATA_CF_ACK 1 | ||
796 | #define FC_SUBTYPE_DATA_CF_POLL 2 | ||
797 | #define FC_SUBTYPE_DATA_CF_ACK_POLL 3 | ||
798 | #define FC_SUBTYPE_NULL 4 | ||
799 | #define FC_SUBTYPE_CF_ACK 5 | ||
800 | #define FC_SUBTYPE_CF_POLL 6 | ||
801 | #define FC_SUBTYPE_CF_ACK_POLL 7 | ||
802 | #define FC_SUBTYPE_QOS_DATA 8 | ||
803 | #define FC_SUBTYPE_QOS_DATA_CF_ACK 9 | ||
804 | #define FC_SUBTYPE_QOS_DATA_CF_POLL 10 | ||
805 | #define FC_SUBTYPE_QOS_DATA_CF_ACK_POLL 11 | ||
806 | #define FC_SUBTYPE_QOS_NULL 12 | ||
807 | #define FC_SUBTYPE_QOS_CF_POLL 14 | ||
808 | #define FC_SUBTYPE_QOS_CF_ACK_POLL 15 | ||
809 | |||
810 | |||
811 | #define FC_SUBTYPE_ANY_QOS(s) (((s) & 8) != 0) | ||
812 | #define FC_SUBTYPE_ANY_NULL(s) (((s) & 4) != 0) | ||
813 | #define FC_SUBTYPE_ANY_CF_POLL(s) (((s) & 2) != 0) | ||
814 | #define FC_SUBTYPE_ANY_CF_ACK(s) (((s) & 1) != 0) | ||
815 | |||
816 | |||
817 | #define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK) | ||
818 | |||
819 | #define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT)) | ||
820 | |||
821 | #define FC_SUBTYPE(fc) (((fc) & FC_SUBTYPE_MASK) >> FC_SUBTYPE_SHIFT) | ||
822 | #define FC_TYPE(fc) (((fc) & FC_TYPE_MASK) >> FC_TYPE_SHIFT) | ||
823 | |||
824 | #define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ) | ||
825 | #define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP) | ||
826 | #define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ) | ||
827 | #define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP) | ||
828 | #define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ) | ||
829 | #define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP) | ||
830 | #define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON) | ||
831 | #define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC) | ||
832 | #define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH) | ||
833 | #define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH) | ||
834 | #define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION) | ||
835 | #define FC_ACTION_NOACK FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION_NOACK) | ||
836 | |||
837 | #define FC_CTL_WRAPPER FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTL_WRAPPER) | ||
838 | #define FC_BLOCKACK_REQ FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_BLOCKACK_REQ) | ||
839 | #define FC_BLOCKACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_BLOCKACK) | ||
840 | #define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL) | ||
841 | #define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS) | ||
842 | #define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS) | ||
843 | #define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK) | ||
844 | #define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END) | ||
845 | #define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK) | ||
846 | |||
847 | #define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA) | ||
848 | #define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL) | ||
849 | #define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK) | ||
850 | #define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA) | ||
851 | #define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL) | ||
852 | |||
853 | |||
854 | |||
855 | |||
856 | #define QOS_PRIO_SHIFT 0 | ||
857 | #define QOS_PRIO_MASK 0x0007 | ||
858 | #define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT) | ||
859 | |||
860 | |||
861 | #define QOS_TID_SHIFT 0 | ||
862 | #define QOS_TID_MASK 0x000f | ||
863 | #define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT) | ||
864 | |||
865 | |||
866 | #define QOS_EOSP_SHIFT 4 | ||
867 | #define QOS_EOSP_MASK 0x0010 | ||
868 | #define QOS_EOSP(qos) (((qos) & QOS_EOSP_MASK) >> QOS_EOSP_SHIFT) | ||
869 | |||
870 | |||
871 | #define QOS_ACK_NORMAL_ACK 0 | ||
872 | #define QOS_ACK_NO_ACK 1 | ||
873 | #define QOS_ACK_NO_EXP_ACK 2 | ||
874 | #define QOS_ACK_BLOCK_ACK 3 | ||
875 | #define QOS_ACK_SHIFT 5 | ||
876 | #define QOS_ACK_MASK 0x0060 | ||
877 | #define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT) | ||
878 | |||
879 | |||
880 | #define QOS_AMSDU_SHIFT 7 | ||
881 | #define QOS_AMSDU_MASK 0x0080 | ||
882 | |||
883 | |||
884 | |||
885 | |||
886 | |||
887 | |||
888 | #define DOT11_MNG_AUTH_ALGO_LEN 2 | ||
889 | #define DOT11_MNG_AUTH_SEQ_LEN 2 | ||
890 | #define DOT11_MNG_BEACON_INT_LEN 2 | ||
891 | #define DOT11_MNG_CAP_LEN 2 | ||
892 | #define DOT11_MNG_AP_ADDR_LEN 6 | ||
893 | #define DOT11_MNG_LISTEN_INT_LEN 2 | ||
894 | #define DOT11_MNG_REASON_LEN 2 | ||
895 | #define DOT11_MNG_AID_LEN 2 | ||
896 | #define DOT11_MNG_STATUS_LEN 2 | ||
897 | #define DOT11_MNG_TIMESTAMP_LEN 8 | ||
898 | |||
899 | |||
900 | #define DOT11_AID_MASK 0x3fff | ||
901 | |||
902 | |||
903 | #define DOT11_RC_RESERVED 0 | ||
904 | #define DOT11_RC_UNSPECIFIED 1 | ||
905 | #define DOT11_RC_AUTH_INVAL 2 | ||
906 | #define DOT11_RC_DEAUTH_LEAVING 3 | ||
907 | #define DOT11_RC_INACTIVITY 4 | ||
908 | #define DOT11_RC_BUSY 5 | ||
909 | #define DOT11_RC_INVAL_CLASS_2 6 | ||
910 | #define DOT11_RC_INVAL_CLASS_3 7 | ||
911 | #define DOT11_RC_DISASSOC_LEAVING 8 | ||
912 | #define DOT11_RC_NOT_AUTH 9 | ||
913 | #define DOT11_RC_BAD_PC 10 | ||
914 | #define DOT11_RC_BAD_CHANNELS 11 | ||
915 | |||
916 | |||
917 | |||
918 | #define DOT11_RC_UNSPECIFIED_QOS 32 | ||
919 | #define DOT11_RC_INSUFFCIENT_BW 33 | ||
920 | #define DOT11_RC_EXCESSIVE_FRAMES 34 | ||
921 | #define DOT11_RC_TX_OUTSIDE_TXOP 35 | ||
922 | #define DOT11_RC_LEAVING_QBSS 36 | ||
923 | #define DOT11_RC_BAD_MECHANISM 37 | ||
924 | #define DOT11_RC_SETUP_NEEDED 38 | ||
925 | #define DOT11_RC_TIMEOUT 39 | ||
926 | |||
927 | #define DOT11_RC_MAX 23 | ||
928 | |||
929 | |||
930 | #define DOT11_SC_SUCCESS 0 | ||
931 | #define DOT11_SC_FAILURE 1 | ||
932 | #define DOT11_SC_CAP_MISMATCH 10 | ||
933 | #define DOT11_SC_REASSOC_FAIL 11 | ||
934 | #define DOT11_SC_ASSOC_FAIL 12 | ||
935 | #define DOT11_SC_AUTH_MISMATCH 13 | ||
936 | #define DOT11_SC_AUTH_SEQ 14 | ||
937 | #define DOT11_SC_AUTH_CHALLENGE_FAIL 15 | ||
938 | #define DOT11_SC_AUTH_TIMEOUT 16 | ||
939 | #define DOT11_SC_ASSOC_BUSY_FAIL 17 | ||
940 | #define DOT11_SC_ASSOC_RATE_MISMATCH 18 | ||
941 | #define DOT11_SC_ASSOC_SHORT_REQUIRED 19 | ||
942 | #define DOT11_SC_ASSOC_PBCC_REQUIRED 20 | ||
943 | #define DOT11_SC_ASSOC_AGILITY_REQUIRED 21 | ||
944 | #define DOT11_SC_ASSOC_SPECTRUM_REQUIRED 22 | ||
945 | #define DOT11_SC_ASSOC_BAD_POWER_CAP 23 | ||
946 | #define DOT11_SC_ASSOC_BAD_SUP_CHANNELS 24 | ||
947 | #define DOT11_SC_ASSOC_SHORTSLOT_REQUIRED 25 | ||
948 | #define DOT11_SC_ASSOC_ERPBCC_REQUIRED 26 | ||
949 | #define DOT11_SC_ASSOC_DSSOFDM_REQUIRED 27 | ||
950 | |||
951 | #define DOT11_SC_DECLINED 37 | ||
952 | #define DOT11_SC_INVALID_PARAMS 38 | ||
953 | #define DOT11_SC_INVALID_AKMP 43 | ||
954 | #define DOT11_SC_INVALID_MDID 54 | ||
955 | #define DOT11_SC_INVALID_FTIE 55 | ||
956 | |||
957 | |||
958 | #define DOT11_MNG_DS_PARAM_LEN 1 | ||
959 | #define DOT11_MNG_IBSS_PARAM_LEN 2 | ||
960 | |||
961 | |||
962 | #define DOT11_MNG_TIM_FIXED_LEN 3 | ||
963 | #define DOT11_MNG_TIM_DTIM_COUNT 0 | ||
964 | #define DOT11_MNG_TIM_DTIM_PERIOD 1 | ||
965 | #define DOT11_MNG_TIM_BITMAP_CTL 2 | ||
966 | #define DOT11_MNG_TIM_PVB 3 | ||
967 | |||
968 | |||
969 | #define TLV_TAG_OFF 0 | ||
970 | #define TLV_LEN_OFF 1 | ||
971 | #define TLV_HDR_LEN 2 | ||
972 | #define TLV_BODY_OFF 2 | ||
973 | |||
974 | |||
975 | #define DOT11_MNG_SSID_ID 0 | ||
976 | #define DOT11_MNG_RATES_ID 1 | ||
977 | #define DOT11_MNG_FH_PARMS_ID 2 | ||
978 | #define DOT11_MNG_DS_PARMS_ID 3 | ||
979 | #define DOT11_MNG_CF_PARMS_ID 4 | ||
980 | #define DOT11_MNG_TIM_ID 5 | ||
981 | #define DOT11_MNG_IBSS_PARMS_ID 6 | ||
982 | #define DOT11_MNG_COUNTRY_ID 7 | ||
983 | #define DOT11_MNG_HOPPING_PARMS_ID 8 | ||
984 | #define DOT11_MNG_HOPPING_TABLE_ID 9 | ||
985 | #define DOT11_MNG_REQUEST_ID 10 | ||
986 | #define DOT11_MNG_QBSS_LOAD_ID 11 | ||
987 | #define DOT11_MNG_EDCA_PARAM_ID 12 | ||
988 | #define DOT11_MNG_CHALLENGE_ID 16 | ||
989 | #define DOT11_MNG_PWR_CONSTRAINT_ID 32 | ||
990 | #define DOT11_MNG_PWR_CAP_ID 33 | ||
991 | #define DOT11_MNG_TPC_REQUEST_ID 34 | ||
992 | #define DOT11_MNG_TPC_REPORT_ID 35 | ||
993 | #define DOT11_MNG_SUPP_CHANNELS_ID 36 | ||
994 | #define DOT11_MNG_CHANNEL_SWITCH_ID 37 | ||
995 | #define DOT11_MNG_MEASURE_REQUEST_ID 38 | ||
996 | #define DOT11_MNG_MEASURE_REPORT_ID 39 | ||
997 | #define DOT11_MNG_QUIET_ID 40 | ||
998 | #define DOT11_MNG_IBSS_DFS_ID 41 | ||
999 | #define DOT11_MNG_ERP_ID 42 | ||
1000 | #define DOT11_MNG_TS_DELAY_ID 43 | ||
1001 | #define DOT11_MNG_HT_CAP 45 | ||
1002 | #define DOT11_MNG_QOS_CAP_ID 46 | ||
1003 | #define DOT11_MNG_NONERP_ID 47 | ||
1004 | #define DOT11_MNG_RSN_ID 48 | ||
1005 | #define DOT11_MNG_EXT_RATES_ID 50 | ||
1006 | #define DOT11_MNG_AP_CHREP_ID 51 | ||
1007 | #define DOT11_MNG_NBR_REP_ID 52 | ||
1008 | #define DOT11_MNG_MDIE_ID 54 | ||
1009 | #define DOT11_MNG_FTIE_ID 55 | ||
1010 | #define DOT11_MNG_FT_TI_ID 56 | ||
1011 | #define DOT11_MNG_REGCLASS_ID 59 | ||
1012 | #define DOT11_MNG_EXT_CSA_ID 60 | ||
1013 | #define DOT11_MNG_HT_ADD 61 | ||
1014 | #define DOT11_MNG_EXT_CHANNEL_OFFSET 62 | ||
1015 | |||
1016 | |||
1017 | #define DOT11_MNG_RRM_CAP_ID 70 | ||
1018 | #define DOT11_MNG_HT_BSS_COEXINFO_ID 72 | ||
1019 | #define DOT11_MNG_HT_BSS_CHANNEL_REPORT_ID 73 | ||
1020 | #define DOT11_MNG_HT_OBSS_ID 74 | ||
1021 | #define DOT11_MNG_EXT_CAP 127 | ||
1022 | #define DOT11_MNG_WPA_ID 221 | ||
1023 | #define DOT11_MNG_PROPR_ID 221 | ||
1024 | |||
1025 | #define DOT11_MNG_VS_ID 221 | ||
1026 | |||
1027 | |||
1028 | #define DOT11_RATE_BASIC 0x80 | ||
1029 | #define DOT11_RATE_MASK 0x7F | ||
1030 | |||
1031 | |||
1032 | #define DOT11_MNG_ERP_LEN 1 | ||
1033 | #define DOT11_MNG_NONERP_PRESENT 0x01 | ||
1034 | #define DOT11_MNG_USE_PROTECTION 0x02 | ||
1035 | #define DOT11_MNG_BARKER_PREAMBLE 0x04 | ||
1036 | |||
1037 | #define DOT11_MGN_TS_DELAY_LEN 4 | ||
1038 | #define TS_DELAY_FIELD_SIZE 4 | ||
1039 | |||
1040 | |||
1041 | #define DOT11_CAP_ESS 0x0001 | ||
1042 | #define DOT11_CAP_IBSS 0x0002 | ||
1043 | #define DOT11_CAP_POLLABLE 0x0004 | ||
1044 | #define DOT11_CAP_POLL_RQ 0x0008 | ||
1045 | #define DOT11_CAP_PRIVACY 0x0010 | ||
1046 | #define DOT11_CAP_SHORT 0x0020 | ||
1047 | #define DOT11_CAP_PBCC 0x0040 | ||
1048 | #define DOT11_CAP_AGILITY 0x0080 | ||
1049 | #define DOT11_CAP_SPECTRUM 0x0100 | ||
1050 | #define DOT11_CAP_SHORTSLOT 0x0400 | ||
1051 | #define DOT11_CAP_RRM 0x1000 | ||
1052 | #define DOT11_CAP_CCK_OFDM 0x2000 | ||
1053 | |||
1054 | |||
1055 | #define DOT11_OBSS_COEX_MNG_SUPPORT 0x01 | ||
1056 | |||
1057 | |||
1058 | #define DOT11_ACTION_HDR_LEN 2 | ||
1059 | #define DOT11_ACTION_CAT_OFF 0 | ||
1060 | #define DOT11_ACTION_ACT_OFF 1 | ||
1061 | |||
1062 | |||
1063 | #define DOT11_ACTION_CAT_ERR_MASK 0x80 | ||
1064 | #define DOT11_ACTION_CAT_MASK 0x7F | ||
1065 | #define DOT11_ACTION_CAT_SPECT_MNG 0 | ||
1066 | #define DOT11_ACTION_CAT_QOS 1 | ||
1067 | #define DOT11_ACTION_CAT_DLS 2 | ||
1068 | #define DOT11_ACTION_CAT_BLOCKACK 3 | ||
1069 | #define DOT11_ACTION_CAT_PUBLIC 4 | ||
1070 | #define DOT11_ACTION_CAT_RRM 5 | ||
1071 | #define DOT11_ACTION_CAT_FBT 6 | ||
1072 | #define DOT11_ACTION_CAT_HT 7 | ||
1073 | #define DOT11_ACTION_CAT_BSSMGMT 10 | ||
1074 | #define DOT11_ACTION_NOTIFICATION 17 | ||
1075 | #define DOT11_ACTION_CAT_VS 127 | ||
1076 | |||
1077 | |||
1078 | #define DOT11_SM_ACTION_M_REQ 0 | ||
1079 | #define DOT11_SM_ACTION_M_REP 1 | ||
1080 | #define DOT11_SM_ACTION_TPC_REQ 2 | ||
1081 | #define DOT11_SM_ACTION_TPC_REP 3 | ||
1082 | #define DOT11_SM_ACTION_CHANNEL_SWITCH 4 | ||
1083 | #define DOT11_SM_ACTION_EXT_CSA 5 | ||
1084 | |||
1085 | |||
1086 | #define DOT11_ACTION_ID_HT_CH_WIDTH 0 | ||
1087 | #define DOT11_ACTION_ID_HT_MIMO_PS 1 | ||
1088 | |||
1089 | |||
1090 | #define DOT11_PUB_ACTION_BSS_COEX_MNG 0 | ||
1091 | #define DOT11_PUB_ACTION_CHANNEL_SWITCH 4 | ||
1092 | |||
1093 | |||
1094 | #define DOT11_BA_ACTION_ADDBA_REQ 0 | ||
1095 | #define DOT11_BA_ACTION_ADDBA_RESP 1 | ||
1096 | #define DOT11_BA_ACTION_DELBA 2 | ||
1097 | |||
1098 | |||
1099 | #define DOT11_ADDBA_PARAM_AMSDU_SUP 0x0001 | ||
1100 | #define DOT11_ADDBA_PARAM_POLICY_MASK 0x0002 | ||
1101 | #define DOT11_ADDBA_PARAM_POLICY_SHIFT 1 | ||
1102 | #define DOT11_ADDBA_PARAM_TID_MASK 0x003c | ||
1103 | #define DOT11_ADDBA_PARAM_TID_SHIFT 2 | ||
1104 | #define DOT11_ADDBA_PARAM_BSIZE_MASK 0xffc0 | ||
1105 | #define DOT11_ADDBA_PARAM_BSIZE_SHIFT 6 | ||
1106 | |||
1107 | #define DOT11_ADDBA_POLICY_DELAYED 0 | ||
1108 | #define DOT11_ADDBA_POLICY_IMMEDIATE 1 | ||
1109 | |||
1110 | BWL_PRE_PACKED_STRUCT struct dot11_addba_req { | ||
1111 | uint8 category; | ||
1112 | uint8 action; | ||
1113 | uint8 token; | ||
1114 | uint16 addba_param_set; | ||
1115 | uint16 timeout; | ||
1116 | uint16 start_seqnum; | ||
1117 | } BWL_POST_PACKED_STRUCT; | ||
1118 | typedef struct dot11_addba_req dot11_addba_req_t; | ||
1119 | #define DOT11_ADDBA_REQ_LEN 9 | ||
1120 | |||
1121 | BWL_PRE_PACKED_STRUCT struct dot11_addba_resp { | ||
1122 | uint8 category; | ||
1123 | uint8 action; | ||
1124 | uint8 token; | ||
1125 | uint16 status; | ||
1126 | uint16 addba_param_set; | ||
1127 | uint16 timeout; | ||
1128 | } BWL_POST_PACKED_STRUCT; | ||
1129 | typedef struct dot11_addba_resp dot11_addba_resp_t; | ||
1130 | #define DOT11_ADDBA_RESP_LEN 9 | ||
1131 | |||
1132 | |||
1133 | #define DOT11_DELBA_PARAM_INIT_MASK 0x0800 | ||
1134 | #define DOT11_DELBA_PARAM_INIT_SHIFT 11 | ||
1135 | #define DOT11_DELBA_PARAM_TID_MASK 0xf000 | ||
1136 | #define DOT11_DELBA_PARAM_TID_SHIFT 12 | ||
1137 | |||
1138 | BWL_PRE_PACKED_STRUCT struct dot11_delba { | ||
1139 | uint8 category; | ||
1140 | uint8 action; | ||
1141 | uint16 delba_param_set; | ||
1142 | uint16 reason; | ||
1143 | } BWL_POST_PACKED_STRUCT; | ||
1144 | typedef struct dot11_delba dot11_delba_t; | ||
1145 | #define DOT11_DELBA_LEN 6 | ||
1146 | |||
1147 | |||
1148 | |||
1149 | |||
1150 | |||
1151 | #define DOT11_RRM_CAP_LEN 5 | ||
1152 | BWL_PRE_PACKED_STRUCT struct dot11_rrm_cap_ie { | ||
1153 | uint8 cap[DOT11_RRM_CAP_LEN]; | ||
1154 | } BWL_POST_PACKED_STRUCT; | ||
1155 | typedef struct dot11_rrm_cap_ie dot11_rrm_cap_ie_t; | ||
1156 | |||
1157 | |||
1158 | #define DOT11_RRM_CAP_LINK 0 | ||
1159 | #define DOT11_RRM_CAP_NEIGHBOR_REPORT 1 | ||
1160 | #define DOT11_RRM_CAP_PARALLEL 2 | ||
1161 | #define DOT11_RRM_CAP_REPEATED 3 | ||
1162 | #define DOT11_RRM_CAP_BCN_PASSIVE 4 | ||
1163 | #define DOT11_RRM_CAP_BCN_ACTIVE 5 | ||
1164 | #define DOT11_RRM_CAP_BCN_TABLE 6 | ||
1165 | #define DOT11_RRM_CAP_BCN_REP_COND 7 | ||
1166 | #define DOT11_RRM_CAP_AP_CHANREP 16 | ||
1167 | |||
1168 | |||
1169 | #define DOT11_RM_ACTION_RM_REQ 0 | ||
1170 | #define DOT11_RM_ACTION_RM_REP 1 | ||
1171 | #define DOT11_RM_ACTION_LM_REQ 2 | ||
1172 | #define DOT11_RM_ACTION_LM_REP 3 | ||
1173 | #define DOT11_RM_ACTION_NR_REQ 4 | ||
1174 | #define DOT11_RM_ACTION_NR_REP 5 | ||
1175 | |||
1176 | |||
1177 | BWL_PRE_PACKED_STRUCT struct dot11_rm_action { | ||
1178 | uint8 category; | ||
1179 | uint8 action; | ||
1180 | uint8 token; | ||
1181 | uint8 data[1]; | ||
1182 | } BWL_POST_PACKED_STRUCT; | ||
1183 | typedef struct dot11_rm_action dot11_rm_action_t; | ||
1184 | #define DOT11_RM_ACTION_LEN 3 | ||
1185 | |||
1186 | BWL_PRE_PACKED_STRUCT struct dot11_rmreq { | ||
1187 | uint8 category; | ||
1188 | uint8 action; | ||
1189 | uint8 token; | ||
1190 | uint16 reps; | ||
1191 | } BWL_POST_PACKED_STRUCT; | ||
1192 | typedef struct dot11_rmreq dot11_rmreq_t; | ||
1193 | #define DOT11_RMREQ_LEN 5 | ||
1194 | |||
1195 | BWL_PRE_PACKED_STRUCT struct dot11_rm_ie { | ||
1196 | uint8 id; | ||
1197 | uint8 len; | ||
1198 | uint8 token; | ||
1199 | uint8 mode; | ||
1200 | uint8 type; | ||
1201 | } BWL_POST_PACKED_STRUCT; | ||
1202 | typedef struct dot11_rm_ie dot11_rm_ie_t; | ||
1203 | #define DOT11_RM_IE_LEN 5 | ||
1204 | |||
1205 | |||
1206 | #define DOT11_RMREQ_MODE_PARALLEL 1 | ||
1207 | #define DOT11_RMREQ_MODE_ENABLE 2 | ||
1208 | #define DOT11_RMREQ_MODE_REQUEST 4 | ||
1209 | #define DOT11_RMREQ_MODE_REPORT 8 | ||
1210 | #define DOT11_RMREQ_MODE_DURMAND 0x10 | ||
1211 | |||
1212 | |||
1213 | #define DOT11_RMREP_MODE_LATE 1 | ||
1214 | #define DOT11_RMREP_MODE_INCAPABLE 2 | ||
1215 | #define DOT11_RMREP_MODE_REFUSED 4 | ||
1216 | |||
1217 | BWL_PRE_PACKED_STRUCT struct dot11_rmreq_bcn { | ||
1218 | uint8 id; | ||
1219 | uint8 len; | ||
1220 | uint8 token; | ||
1221 | uint8 mode; | ||
1222 | uint8 type; | ||
1223 | uint8 reg; | ||
1224 | uint8 channel; | ||
1225 | uint16 interval; | ||
1226 | uint16 duration; | ||
1227 | uint8 bcn_mode; | ||
1228 | struct ether_addr bssid; | ||
1229 | } BWL_POST_PACKED_STRUCT; | ||
1230 | typedef struct dot11_rmreq_bcn dot11_rmreq_bcn_t; | ||
1231 | #define DOT11_RMREQ_BCN_LEN 18 | ||
1232 | |||
1233 | BWL_PRE_PACKED_STRUCT struct dot11_rmrep_bcn { | ||
1234 | uint8 reg; | ||
1235 | uint8 channel; | ||
1236 | uint32 starttime[2]; | ||
1237 | uint16 duration; | ||
1238 | uint8 frame_info; | ||
1239 | uint8 rcpi; | ||
1240 | uint8 rsni; | ||
1241 | struct ether_addr bssid; | ||
1242 | uint8 antenna_id; | ||
1243 | uint32 parent_tsf; | ||
1244 | } BWL_POST_PACKED_STRUCT; | ||
1245 | typedef struct dot11_rmrep_bcn dot11_rmrep_bcn_t; | ||
1246 | #define DOT11_RMREP_BCN_LEN 26 | ||
1247 | |||
1248 | |||
1249 | #define DOT11_RMREQ_BCN_PASSIVE 0 | ||
1250 | #define DOT11_RMREQ_BCN_ACTIVE 1 | ||
1251 | #define DOT11_RMREQ_BCN_TABLE 2 | ||
1252 | |||
1253 | |||
1254 | #define DOT11_RMREQ_BCN_SSID_ID 0 | ||
1255 | #define DOT11_RMREQ_BCN_REPINFO_ID 1 | ||
1256 | #define DOT11_RMREQ_BCN_REPDET_ID 2 | ||
1257 | #define DOT11_RMREQ_BCN_REQUEST_ID 10 | ||
1258 | #define DOT11_RMREQ_BCN_APCHREP_ID 51 | ||
1259 | |||
1260 | |||
1261 | #define DOT11_RMREQ_BCN_REPDET_FIXED 0 | ||
1262 | #define DOT11_RMREQ_BCN_REPDET_REQUEST 1 | ||
1263 | #define DOT11_RMREQ_BCN_REPDET_ALL 2 | ||
1264 | |||
1265 | |||
1266 | #define DOT11_RMREP_BCN_FRM_BODY 1 | ||
1267 | |||
1268 | |||
1269 | BWL_PRE_PACKED_STRUCT struct dot11_rmrep_nbr { | ||
1270 | struct ether_addr bssid; | ||
1271 | uint32 bssid_info; | ||
1272 | uint8 reg; | ||
1273 | uint8 channel; | ||
1274 | uint8 phytype; | ||
1275 | } BWL_POST_PACKED_STRUCT; | ||
1276 | typedef struct dot11_rmrep_nbr dot11_rmrep_nbr_t; | ||
1277 | #define DOT11_RMREP_NBR_LEN 13 | ||
1278 | |||
1279 | |||
1280 | #define DOT11_BSSTYPE_INFRASTRUCTURE 0 | ||
1281 | #define DOT11_BSSTYPE_INDEPENDENT 1 | ||
1282 | #define DOT11_BSSTYPE_ANY 2 | ||
1283 | #define DOT11_SCANTYPE_ACTIVE 0 | ||
1284 | #define DOT11_SCANTYPE_PASSIVE 1 | ||
1285 | |||
1286 | |||
1287 | BWL_PRE_PACKED_STRUCT struct dot11_lmreq { | ||
1288 | uint8 category; | ||
1289 | uint8 action; | ||
1290 | uint8 token; | ||
1291 | uint8 txpwr; | ||
1292 | uint8 maxtxpwr; | ||
1293 | } BWL_POST_PACKED_STRUCT; | ||
1294 | typedef struct dot11_lmreq dot11_lmreq_t; | ||
1295 | #define DOT11_LMREQ_LEN 5 | ||
1296 | |||
1297 | BWL_PRE_PACKED_STRUCT struct dot11_lmrep { | ||
1298 | uint8 category; | ||
1299 | uint8 action; | ||
1300 | uint8 token; | ||
1301 | dot11_tpc_rep_t tpc; | ||
1302 | uint8 rxant; | ||
1303 | uint8 txant; | ||
1304 | uint8 rcpi; | ||
1305 | uint8 rsni; | ||
1306 | } BWL_POST_PACKED_STRUCT; | ||
1307 | typedef struct dot11_lmrep dot11_lmrep_t; | ||
1308 | #define DOT11_LMREP_LEN 11 | ||
1309 | |||
1310 | |||
1311 | #define PREN_PREAMBLE 24 | ||
1312 | #define PREN_MM_EXT 12 | ||
1313 | #define PREN_PREAMBLE_EXT 4 | ||
1314 | |||
1315 | |||
1316 | #define RIFS_11N_TIME 2 | ||
1317 | |||
1318 | |||
1319 | |||
1320 | #define HT_SIG1_MCS_MASK 0x00007F | ||
1321 | #define HT_SIG1_CBW 0x000080 | ||
1322 | #define HT_SIG1_HT_LENGTH 0xFFFF00 | ||
1323 | |||
1324 | |||
1325 | #define HT_SIG2_SMOOTHING 0x000001 | ||
1326 | #define HT_SIG2_NOT_SOUNDING 0x000002 | ||
1327 | #define HT_SIG2_RESERVED 0x000004 | ||
1328 | #define HT_SIG2_AGGREGATION 0x000008 | ||
1329 | #define HT_SIG2_STBC_MASK 0x000030 | ||
1330 | #define HT_SIG2_STBC_SHIFT 4 | ||
1331 | #define HT_SIG2_FEC_CODING 0x000040 | ||
1332 | #define HT_SIG2_SHORT_GI 0x000080 | ||
1333 | #define HT_SIG2_ESS_MASK 0x000300 | ||
1334 | #define HT_SIG2_ESS_SHIFT 8 | ||
1335 | #define HT_SIG2_CRC 0x03FC00 | ||
1336 | #define HT_SIG2_TAIL 0x1C0000 | ||
1337 | |||
1338 | |||
1339 | #define APHY_SLOT_TIME 9 | ||
1340 | #define APHY_SIFS_TIME 16 | ||
1341 | #define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME)) | ||
1342 | #define APHY_PREAMBLE_TIME 16 | ||
1343 | #define APHY_SIGNAL_TIME 4 | ||
1344 | #define APHY_SYMBOL_TIME 4 | ||
1345 | #define APHY_SERVICE_NBITS 16 | ||
1346 | #define APHY_TAIL_NBITS 6 | ||
1347 | #define APHY_CWMIN 15 | ||
1348 | |||
1349 | |||
1350 | #define BPHY_SLOT_TIME 20 | ||
1351 | #define BPHY_SIFS_TIME 10 | ||
1352 | #define BPHY_DIFS_TIME 50 | ||
1353 | #define BPHY_PLCP_TIME 192 | ||
1354 | #define BPHY_PLCP_SHORT_TIME 96 | ||
1355 | #define BPHY_CWMIN 31 | ||
1356 | |||
1357 | |||
1358 | #define DOT11_OFDM_SIGNAL_EXTENSION 6 | ||
1359 | |||
1360 | #define PHY_CWMAX 1023 | ||
1361 | |||
1362 | #define DOT11_MAXNUMFRAGS 16 | ||
1363 | |||
1364 | |||
1365 | typedef struct d11cnt { | ||
1366 | uint32 txfrag; | ||
1367 | uint32 txmulti; | ||
1368 | uint32 txfail; | ||
1369 | uint32 txretry; | ||
1370 | uint32 txretrie; | ||
1371 | uint32 rxdup; | ||
1372 | uint32 txrts; | ||
1373 | uint32 txnocts; | ||
1374 | uint32 txnoack; | ||
1375 | uint32 rxfrag; | ||
1376 | uint32 rxmulti; | ||
1377 | uint32 rxcrc; | ||
1378 | uint32 txfrmsnt; | ||
1379 | uint32 rxundec; | ||
1380 | } d11cnt_t; | ||
1381 | |||
1382 | |||
1383 | #define BRCM_PROP_OUI "\x00\x90\x4C" | ||
1384 | |||
1385 | |||
1386 | |||
1387 | #define BRCM_OUI "\x00\x10\x18" | ||
1388 | |||
1389 | |||
1390 | BWL_PRE_PACKED_STRUCT struct brcm_ie { | ||
1391 | uint8 id; | ||
1392 | uint8 len; | ||
1393 | uint8 oui[3]; | ||
1394 | uint8 ver; | ||
1395 | uint8 assoc; | ||
1396 | uint8 flags; | ||
1397 | uint8 flags1; | ||
1398 | uint16 amsdu_mtu_pref; | ||
1399 | } BWL_POST_PACKED_STRUCT; | ||
1400 | typedef struct brcm_ie brcm_ie_t; | ||
1401 | #define BRCM_IE_LEN 11 | ||
1402 | #define BRCM_IE_VER 2 | ||
1403 | #define BRCM_IE_LEGACY_AES_VER 1 | ||
1404 | |||
1405 | |||
1406 | #ifdef WLAFTERBURNER | ||
1407 | #define BRF_ABCAP 0x1 | ||
1408 | #define BRF_ABRQRD 0x2 | ||
1409 | #define BRF_ABCOUNTER_MASK 0xf0 | ||
1410 | #define BRF_ABCOUNTER_SHIFT 4 | ||
1411 | #endif | ||
1412 | #define BRF_LZWDS 0x4 | ||
1413 | #define BRF_BLOCKACK 0x8 | ||
1414 | |||
1415 | |||
1416 | #define BRF1_AMSDU 0x1 | ||
1417 | #define BRF1_WMEPS 0x4 | ||
1418 | #define BRF1_PSOFIX 0x8 | ||
1419 | #define BRF1_RX_LARGE_AGG 0x10 | ||
1420 | #define BRF1_SOFTAP 0x40 | ||
1421 | |||
1422 | #ifdef WLAFTERBURNER | ||
1423 | #define AB_WDS_TIMEOUT_MAX 15 | ||
1424 | #define AB_WDS_TIMEOUT_MIN 1 | ||
1425 | #endif | ||
1426 | |||
1427 | #define AB_GUARDCOUNT 10 | ||
1428 | |||
1429 | |||
1430 | BWL_PRE_PACKED_STRUCT struct vndr_ie { | ||
1431 | uchar id; | ||
1432 | uchar len; | ||
1433 | uchar oui [3]; | ||
1434 | uchar data [1]; | ||
1435 | } BWL_POST_PACKED_STRUCT; | ||
1436 | typedef struct vndr_ie vndr_ie_t; | ||
1437 | |||
1438 | #define VNDR_IE_HDR_LEN 2 | ||
1439 | #define VNDR_IE_MIN_LEN 3 | ||
1440 | #define VNDR_IE_MAX_LEN 256 | ||
1441 | |||
1442 | |||
1443 | #define MCSSET_LEN 16 | ||
1444 | #define MAX_MCS_NUM (128) | ||
1445 | |||
1446 | BWL_PRE_PACKED_STRUCT struct ht_cap_ie { | ||
1447 | uint16 cap; | ||
1448 | uint8 params; | ||
1449 | uint8 supp_mcs[MCSSET_LEN]; | ||
1450 | uint16 ext_htcap; | ||
1451 | uint32 txbf_cap; | ||
1452 | uint8 as_cap; | ||
1453 | } BWL_POST_PACKED_STRUCT; | ||
1454 | typedef struct ht_cap_ie ht_cap_ie_t; | ||
1455 | |||
1456 | |||
1457 | |||
1458 | BWL_PRE_PACKED_STRUCT struct ht_prop_cap_ie { | ||
1459 | uint8 id; | ||
1460 | uint8 len; | ||
1461 | uint8 oui[3]; | ||
1462 | uint8 type; | ||
1463 | ht_cap_ie_t cap_ie; | ||
1464 | } BWL_POST_PACKED_STRUCT; | ||
1465 | typedef struct ht_prop_cap_ie ht_prop_cap_ie_t; | ||
1466 | |||
1467 | #define HT_PROP_IE_OVERHEAD 4 | ||
1468 | #define HT_CAP_IE_LEN 26 | ||
1469 | #define HT_CAP_IE_TYPE 51 | ||
1470 | |||
1471 | #define HT_CAP_LDPC_CODING 0x0001 | ||
1472 | #define HT_CAP_40MHZ 0x0002 | ||
1473 | #define HT_CAP_MIMO_PS_MASK 0x000C | ||
1474 | #define HT_CAP_MIMO_PS_SHIFT 0x0002 | ||
1475 | #define HT_CAP_MIMO_PS_OFF 0x0003 | ||
1476 | #define HT_CAP_MIMO_PS_RTS 0x0001 | ||
1477 | #define HT_CAP_MIMO_PS_ON 0x0000 | ||
1478 | #define HT_CAP_GF 0x0010 | ||
1479 | #define HT_CAP_SHORT_GI_20 0x0020 | ||
1480 | #define HT_CAP_SHORT_GI_40 0x0040 | ||
1481 | #define HT_CAP_TX_STBC 0x0080 | ||
1482 | #define HT_CAP_RX_STBC_MASK 0x0300 | ||
1483 | #define HT_CAP_RX_STBC_SHIFT 8 | ||
1484 | #define HT_CAP_DELAYED_BA 0x0400 | ||
1485 | #define HT_CAP_MAX_AMSDU 0x0800 | ||
1486 | #define HT_CAP_DSSS_CCK 0x1000 | ||
1487 | #define HT_CAP_PSMP 0x2000 | ||
1488 | #define HT_CAP_40MHZ_INTOLERANT 0x4000 | ||
1489 | #define HT_CAP_LSIG_TXOP 0x8000 | ||
1490 | |||
1491 | #define HT_CAP_RX_STBC_NO 0x0 | ||
1492 | #define HT_CAP_RX_STBC_ONE_STREAM 0x1 | ||
1493 | #define HT_CAP_RX_STBC_TWO_STREAM 0x2 | ||
1494 | #define HT_CAP_RX_STBC_THREE_STREAM 0x3 | ||
1495 | |||
1496 | #define HT_MAX_AMSDU 7935 | ||
1497 | #define HT_MIN_AMSDU 3835 | ||
1498 | |||
1499 | #define HT_PARAMS_RX_FACTOR_MASK 0x03 | ||
1500 | #define HT_PARAMS_DENSITY_MASK 0x1C | ||
1501 | #define HT_PARAMS_DENSITY_SHIFT 2 | ||
1502 | |||
1503 | |||
1504 | #define AMPDU_MAX_MPDU_DENSITY 7 | ||
1505 | #define AMPDU_RX_FACTOR_8K 0 | ||
1506 | #define AMPDU_RX_FACTOR_16K 1 | ||
1507 | #define AMPDU_RX_FACTOR_32K 2 | ||
1508 | #define AMPDU_RX_FACTOR_64K 3 | ||
1509 | #define AMPDU_RX_FACTOR_BASE 8*1024 | ||
1510 | |||
1511 | #define AMPDU_DELIMITER_LEN 4 | ||
1512 | #define AMPDU_DELIMITER_LEN_MAX 63 | ||
1513 | |||
1514 | BWL_PRE_PACKED_STRUCT struct ht_add_ie { | ||
1515 | uint8 ctl_ch; | ||
1516 | uint8 byte1; | ||
1517 | uint16 opmode; | ||
1518 | uint16 misc_bits; | ||
1519 | uint8 basic_mcs[MCSSET_LEN]; | ||
1520 | } BWL_POST_PACKED_STRUCT; | ||
1521 | typedef struct ht_add_ie ht_add_ie_t; | ||
1522 | |||
1523 | |||
1524 | |||
1525 | BWL_PRE_PACKED_STRUCT struct ht_prop_add_ie { | ||
1526 | uint8 id; | ||
1527 | uint8 len; | ||
1528 | uint8 oui[3]; | ||
1529 | uint8 type; | ||
1530 | ht_add_ie_t add_ie; | ||
1531 | } BWL_POST_PACKED_STRUCT; | ||
1532 | typedef struct ht_prop_add_ie ht_prop_add_ie_t; | ||
1533 | |||
1534 | #define HT_ADD_IE_LEN 22 | ||
1535 | #define HT_ADD_IE_TYPE 52 | ||
1536 | |||
1537 | |||
1538 | #define HT_BW_ANY 0x04 | ||
1539 | #define HT_RIFS_PERMITTED 0x08 | ||
1540 | |||
1541 | |||
1542 | #define HT_OPMODE_MASK 0x0003 | ||
1543 | #define HT_OPMODE_SHIFT 0 | ||
1544 | #define HT_OPMODE_PURE 0x0000 | ||
1545 | #define HT_OPMODE_OPTIONAL 0x0001 | ||
1546 | #define HT_OPMODE_HT20IN40 0x0002 | ||
1547 | #define HT_OPMODE_MIXED 0x0003 | ||
1548 | #define HT_OPMODE_NONGF 0x0004 | ||
1549 | #define DOT11N_TXBURST 0x0008 | ||
1550 | #define DOT11N_OBSS_NONHT 0x0010 | ||
1551 | |||
1552 | |||
1553 | #define HT_BASIC_STBC_MCS 0x007f | ||
1554 | #define HT_DUAL_STBC_PROT 0x0080 | ||
1555 | #define HT_SECOND_BCN 0x0100 | ||
1556 | #define HT_LSIG_TXOP 0x0200 | ||
1557 | #define HT_PCO_ACTIVE 0x0400 | ||
1558 | #define HT_PCO_PHASE 0x0800 | ||
1559 | |||
1560 | |||
1561 | #define DOT11N_2G_TXBURST_LIMIT 6160 | ||
1562 | #define DOT11N_5G_TXBURST_LIMIT 3080 | ||
1563 | |||
1564 | |||
1565 | #define GET_HT_OPMODE(add_ie) ((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \ | ||
1566 | >> HT_OPMODE_SHIFT) | ||
1567 | #define HT_MIXEDMODE_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \ | ||
1568 | == HT_OPMODE_MIXED) | ||
1569 | #define HT_HT20_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \ | ||
1570 | == HT_OPMODE_HT20IN40) | ||
1571 | #define HT_OPTIONAL_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \ | ||
1572 | == HT_OPMODE_OPTIONAL) | ||
1573 | #define HT_USE_PROTECTION(add_ie) (HT_HT20_PRESENT((add_ie)) || \ | ||
1574 | HT_MIXEDMODE_PRESENT((add_ie))) | ||
1575 | #define HT_NONGF_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_NONGF) \ | ||
1576 | == HT_OPMODE_NONGF) | ||
1577 | #define DOT11N_TXBURST_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & DOT11N_TXBURST) \ | ||
1578 | == DOT11N_TXBURST) | ||
1579 | #define DOT11N_OBSS_NONHT_PRESENT(add_ie) ((ltoh16_ua(&add_ie->opmode) & DOT11N_OBSS_NONHT) \ | ||
1580 | == DOT11N_OBSS_NONHT) | ||
1581 | |||
1582 | BWL_PRE_PACKED_STRUCT struct obss_params { | ||
1583 | uint16 passive_dwell; | ||
1584 | uint16 active_dwell; | ||
1585 | uint16 bss_widthscan_interval; | ||
1586 | uint16 passive_total; | ||
1587 | uint16 active_total; | ||
1588 | uint16 chanwidth_transition_dly; | ||
1589 | uint16 activity_threshold; | ||
1590 | } BWL_POST_PACKED_STRUCT; | ||
1591 | typedef struct obss_params obss_params_t; | ||
1592 | |||
1593 | BWL_PRE_PACKED_STRUCT struct dot11_obss_ie { | ||
1594 | uint8 id; | ||
1595 | uint8 len; | ||
1596 | obss_params_t obss_params; | ||
1597 | } BWL_POST_PACKED_STRUCT; | ||
1598 | typedef struct dot11_obss_ie dot11_obss_ie_t; | ||
1599 | #define DOT11_OBSS_SCAN_IE_LEN sizeof(obss_params_t) | ||
1600 | |||
1601 | |||
1602 | #define HT_CTRL_LA_TRQ 0x00000002 | ||
1603 | #define HT_CTRL_LA_MAI 0x0000003C | ||
1604 | #define HT_CTRL_LA_MAI_SHIFT 2 | ||
1605 | #define HT_CTRL_LA_MAI_MRQ 0x00000004 | ||
1606 | #define HT_CTRL_LA_MAI_MSI 0x00000038 | ||
1607 | #define HT_CTRL_LA_MFSI 0x000001C0 | ||
1608 | #define HT_CTRL_LA_MFSI_SHIFT 6 | ||
1609 | #define HT_CTRL_LA_MFB_ASELC 0x0000FE00 | ||
1610 | #define HT_CTRL_LA_MFB_ASELC_SH 9 | ||
1611 | #define HT_CTRL_LA_ASELC_CMD 0x00000C00 | ||
1612 | #define HT_CTRL_LA_ASELC_DATA 0x0000F000 | ||
1613 | #define HT_CTRL_CAL_POS 0x00030000 | ||
1614 | #define HT_CTRL_CAL_SEQ 0x000C0000 | ||
1615 | #define HT_CTRL_CSI_STEERING 0x00C00000 | ||
1616 | #define HT_CTRL_CSI_STEER_SHIFT 22 | ||
1617 | #define HT_CTRL_CSI_STEER_NFB 0 | ||
1618 | #define HT_CTRL_CSI_STEER_CSI 1 | ||
1619 | #define HT_CTRL_CSI_STEER_NCOM 2 | ||
1620 | #define HT_CTRL_CSI_STEER_COM 3 | ||
1621 | #define HT_CTRL_NDP_ANNOUNCE 0x01000000 | ||
1622 | #define HT_CTRL_AC_CONSTRAINT 0x40000000 | ||
1623 | #define HT_CTRL_RDG_MOREPPDU 0x80000000 | ||
1624 | |||
1625 | #define HT_OPMODE_OPTIONAL 0x0001 | ||
1626 | #define HT_OPMODE_HT20IN40 0x0002 | ||
1627 | #define HT_OPMODE_MIXED 0x0003 | ||
1628 | #define HT_OPMODE_NONGF 0x0004 | ||
1629 | #define DOT11N_TXBURST 0x0008 | ||
1630 | #define DOT11N_OBSS_NONHT 0x0010 | ||
1631 | |||
1632 | |||
1633 | |||
1634 | #define WPA_OUI "\x00\x50\xF2" | ||
1635 | #define WPA_OUI_LEN 3 | ||
1636 | #define WPA_OUI_TYPE 1 | ||
1637 | #define WPA_VERSION 1 | ||
1638 | #define WPA2_OUI "\x00\x0F\xAC" | ||
1639 | #define WPA2_OUI_LEN 3 | ||
1640 | #define WPA2_VERSION 1 | ||
1641 | #define WPA2_VERSION_LEN 2 | ||
1642 | |||
1643 | |||
1644 | #define WPS_OUI "\x00\x50\xF2" | ||
1645 | #define WPS_OUI_LEN 3 | ||
1646 | #define WPS_OUI_TYPE 4 | ||
1647 | |||
1648 | |||
1649 | #define WFA_OUI "\x50\x6F\x9A" | ||
1650 | #define WFA_OUI_LEN 3 | ||
1651 | |||
1652 | #define WFA_OUI_TYPE_WPA 1 | ||
1653 | #define WFA_OUI_TYPE_WPS 4 | ||
1654 | #define WFA_OUI_TYPE_TPC 8 | ||
1655 | #define WFA_OUI_TYPE_P2P 9 | ||
1656 | |||
1657 | |||
1658 | #define RSN_AKM_NONE 0 | ||
1659 | #define RSN_AKM_UNSPECIFIED 1 | ||
1660 | #define RSN_AKM_PSK 2 | ||
1661 | #define RSN_AKM_FBT_1X 3 | ||
1662 | #define RSN_AKM_FBT_PSK 4 | ||
1663 | |||
1664 | |||
1665 | #define DOT11_MAX_DEFAULT_KEYS 4 | ||
1666 | #define DOT11_MAX_KEY_SIZE 32 | ||
1667 | #define DOT11_MAX_IV_SIZE 16 | ||
1668 | #define DOT11_EXT_IV_FLAG (1<<5) | ||
1669 | #define DOT11_WPA_KEY_RSC_LEN 8 | ||
1670 | |||
1671 | #define WEP1_KEY_SIZE 5 | ||
1672 | #define WEP1_KEY_HEX_SIZE 10 | ||
1673 | #define WEP128_KEY_SIZE 13 | ||
1674 | #define WEP128_KEY_HEX_SIZE 26 | ||
1675 | #define TKIP_MIC_SIZE 8 | ||
1676 | #define TKIP_EOM_SIZE 7 | ||
1677 | #define TKIP_EOM_FLAG 0x5a | ||
1678 | #define TKIP_KEY_SIZE 32 | ||
1679 | #define TKIP_MIC_AUTH_TX 16 | ||
1680 | #define TKIP_MIC_AUTH_RX 24 | ||
1681 | #define TKIP_MIC_SUP_RX TKIP_MIC_AUTH_TX | ||
1682 | #define TKIP_MIC_SUP_TX TKIP_MIC_AUTH_RX | ||
1683 | #define AES_KEY_SIZE 16 | ||
1684 | #define AES_MIC_SIZE 8 | ||
1685 | |||
1686 | |||
1687 | #define WCN_OUI "\x00\x50\xf2" | ||
1688 | #define WCN_TYPE 4 | ||
1689 | |||
1690 | |||
1691 | |||
1692 | |||
1693 | |||
1694 | BWL_PRE_PACKED_STRUCT struct dot11_mdid_ie { | ||
1695 | uint8 id; | ||
1696 | uint8 len; | ||
1697 | uint16 mdid; | ||
1698 | uint8 cap; | ||
1699 | } BWL_POST_PACKED_STRUCT; | ||
1700 | typedef struct dot11_mdid_ie dot11_mdid_ie_t; | ||
1701 | |||
1702 | #define FBT_MDID_CAP_OVERDS 0x01 | ||
1703 | #define FBT_MDID_CAP_RRP 0x02 | ||
1704 | |||
1705 | |||
1706 | BWL_PRE_PACKED_STRUCT struct dot11_ft_ie { | ||
1707 | uint8 id; | ||
1708 | uint8 len; | ||
1709 | uint16 mic_control; | ||
1710 | uint8 mic[16]; | ||
1711 | uint8 anonce[32]; | ||
1712 | uint8 snonce[32]; | ||
1713 | } BWL_POST_PACKED_STRUCT; | ||
1714 | typedef struct dot11_ft_ie dot11_ft_ie_t; | ||
1715 | |||
1716 | |||
1717 | BWL_PRE_PACKED_STRUCT struct dot11_gtk_ie { | ||
1718 | uint8 id; | ||
1719 | uint8 len; | ||
1720 | uint16 key_info; | ||
1721 | uint8 key_len; | ||
1722 | uint8 rsc[8]; | ||
1723 | uint8 data[1]; | ||
1724 | } BWL_POST_PACKED_STRUCT; | ||
1725 | typedef struct dot11_gtk_ie dot11_gtk_ie_t; | ||
1726 | |||
1727 | |||
1728 | |||
1729 | #include <packed_section_end.h> | ||
1730 | |||
1731 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/802.11_bta.h b/drivers/net/wireless/bcmdhd/include/proto/802.11_bta.h new file mode 100644 index 00000000000..4ccfab02056 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/802.11_bta.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * BT-AMP (BlueTooth Alternate Mac and Phy) 802.11 PAL (Protocol Adaptation Layer) | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: 802.11_bta.h,v 9.2 2008-10-28 23:27:13 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _802_11_BTA_H_ | ||
28 | #define _802_11_BTA_H_ | ||
29 | |||
30 | #define BT_SIG_SNAP_MPROT "\xAA\xAA\x03\x00\x19\x58" | ||
31 | |||
32 | /* BT-AMP 802.11 PAL Protocols */ | ||
33 | #define BTA_PROT_L2CAP 1 | ||
34 | #define BTA_PROT_ACTIVITY_REPORT 2 | ||
35 | #define BTA_PROT_SECURITY 3 | ||
36 | #define BTA_PROT_LINK_SUPERVISION_REQUEST 4 | ||
37 | #define BTA_PROT_LINK_SUPERVISION_REPLY 5 | ||
38 | |||
39 | /* BT-AMP 802.11 PAL AMP_ASSOC Type IDs */ | ||
40 | #define BTA_TYPE_ID_MAC_ADDRESS 1 | ||
41 | #define BTA_TYPE_ID_PREFERRED_CHANNELS 2 | ||
42 | #define BTA_TYPE_ID_CONNECTED_CHANNELS 3 | ||
43 | #define BTA_TYPE_ID_CAPABILITIES 4 | ||
44 | #define BTA_TYPE_ID_VERSION 5 | ||
45 | #endif /* _802_11_bta_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/802.11e.h b/drivers/net/wireless/bcmdhd/include/proto/802.11e.h new file mode 100644 index 00000000000..ce8ad083f28 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/802.11e.h | |||
@@ -0,0 +1,131 @@ | |||
1 | /* | ||
2 | * 802.11e protocol header file | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: 802.11e.h,v 1.6 2008-12-01 22:55:11 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _802_11e_H_ | ||
28 | #define _802_11e_H_ | ||
29 | |||
30 | #ifndef _TYPEDEFS_H_ | ||
31 | #include <typedefs.h> | ||
32 | #endif | ||
33 | |||
34 | /* This marks the start of a packed structure section. */ | ||
35 | #include <packed_section_start.h> | ||
36 | |||
37 | |||
38 | /* WME Traffic Specification (TSPEC) element */ | ||
39 | #define WME_TSPEC_HDR_LEN 2 /* WME TSPEC header length */ | ||
40 | #define WME_TSPEC_BODY_OFF 2 /* WME TSPEC body offset */ | ||
41 | |||
42 | #define WME_CATEGORY_CODE_OFFSET 0 /* WME Category code offset */ | ||
43 | #define WME_ACTION_CODE_OFFSET 1 /* WME Action code offset */ | ||
44 | #define WME_TOKEN_CODE_OFFSET 2 /* WME Token code offset */ | ||
45 | #define WME_STATUS_CODE_OFFSET 3 /* WME Status code offset */ | ||
46 | |||
47 | BWL_PRE_PACKED_STRUCT struct tsinfo { | ||
48 | uint8 octets[3]; | ||
49 | } BWL_POST_PACKED_STRUCT; | ||
50 | |||
51 | typedef struct tsinfo tsinfo_t; | ||
52 | |||
53 | /* 802.11e TSPEC IE */ | ||
54 | typedef BWL_PRE_PACKED_STRUCT struct tspec { | ||
55 | uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */ | ||
56 | uint8 type; /* WME_TYPE */ | ||
57 | uint8 subtype; /* WME_SUBTYPE_TSPEC */ | ||
58 | uint8 version; /* WME_VERSION */ | ||
59 | tsinfo_t tsinfo; /* TS Info bit field */ | ||
60 | uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */ | ||
61 | uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */ | ||
62 | uint32 min_srv_interval; /* Minimum Service Interval (us) */ | ||
63 | uint32 max_srv_interval; /* Maximum Service Interval (us) */ | ||
64 | uint32 inactivity_interval; /* Inactivity Interval (us) */ | ||
65 | uint32 suspension_interval; /* Suspension Interval (us) */ | ||
66 | uint32 srv_start_time; /* Service Start Time (us) */ | ||
67 | uint32 min_data_rate; /* Minimum Data Rate (bps) */ | ||
68 | uint32 mean_data_rate; /* Mean Data Rate (bps) */ | ||
69 | uint32 peak_data_rate; /* Peak Data Rate (bps) */ | ||
70 | uint32 max_burst_size; /* Maximum Burst Size (bytes) */ | ||
71 | uint32 delay_bound; /* Delay Bound (us) */ | ||
72 | uint32 min_phy_rate; /* Minimum PHY Rate (bps) */ | ||
73 | uint16 surplus_bw; /* Surplus Bandwidth Allowance (range 1.0-8.0) */ | ||
74 | uint16 medium_time; /* Medium Time (32 us/s periods) */ | ||
75 | } BWL_POST_PACKED_STRUCT tspec_t; | ||
76 | |||
77 | #define WME_TSPEC_LEN (sizeof(tspec_t)) /* not including 2-bytes of header */ | ||
78 | |||
79 | /* ts_info */ | ||
80 | /* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */ | ||
81 | #define TS_INFO_TID_SHIFT 1 /* TS info. TID shift */ | ||
82 | #define TS_INFO_TID_MASK (0xf << TS_INFO_TID_SHIFT) /* TS info. TID mask */ | ||
83 | #define TS_INFO_CONTENTION_SHIFT 7 /* TS info. contention shift */ | ||
84 | #define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT) /* TS info. contention mask */ | ||
85 | #define TS_INFO_DIRECTION_SHIFT 5 /* TS info. direction shift */ | ||
86 | #define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT) /* TS info. direction mask */ | ||
87 | #define TS_INFO_PSB_SHIFT 2 /* TS info. PSB bit Shift */ | ||
88 | #define TS_INFO_PSB_MASK (1 << TS_INFO_PSB_SHIFT) /* TS info. PSB mask */ | ||
89 | #define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT) /* TS info. uplink */ | ||
90 | #define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT) /* TS info. downlink */ | ||
91 | #define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT) /* TS info. bidirectional */ | ||
92 | #define TS_INFO_USER_PRIO_SHIFT 3 /* TS info. user priority shift */ | ||
93 | /* TS info. user priority mask */ | ||
94 | #define TS_INFO_USER_PRIO_MASK (0x7 << TS_INFO_USER_PRIO_SHIFT) | ||
95 | |||
96 | /* Macro to get/set bit(s) field in TSINFO */ | ||
97 | #define WLC_CAC_GET_TID(pt) ((((pt).octets[0]) & TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT) | ||
98 | #define WLC_CAC_GET_DIR(pt) ((((pt).octets[0]) & \ | ||
99 | TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT) | ||
100 | #define WLC_CAC_GET_PSB(pt) ((((pt).octets[1]) & TS_INFO_PSB_MASK) >> TS_INFO_PSB_SHIFT) | ||
101 | #define WLC_CAC_GET_USER_PRIO(pt) ((((pt).octets[1]) & \ | ||
102 | TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT) | ||
103 | |||
104 | #define WLC_CAC_SET_TID(pt, id) ((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \ | ||
105 | ((id) << TS_INFO_TID_SHIFT)) | ||
106 | #define WLC_CAC_SET_USER_PRIO(pt, prio) ((((pt).octets[0]) & (~TS_INFO_USER_PRIO_MASK)) | \ | ||
107 | ((prio) << TS_INFO_USER_PRIO_SHIFT)) | ||
108 | |||
109 | /* 802.11e QBSS Load IE */ | ||
110 | #define QBSS_LOAD_IE_LEN 5 /* QBSS Load IE length */ | ||
111 | #define QBSS_LOAD_AAC_OFF 3 /* AAC offset in IE */ | ||
112 | |||
113 | #define CAC_ADDTS_RESP_TIMEOUT 300 /* default ADDTS response timeout in ms */ | ||
114 | |||
115 | /* 802.11e ADDTS status code */ | ||
116 | #define DOT11E_STATUS_ADMISSION_ACCEPTED 0 /* TSPEC Admission accepted status */ | ||
117 | #define DOT11E_STATUS_ADDTS_INVALID_PARAM 1 /* TSPEC invalid parameter status */ | ||
118 | #define DOT11E_STATUS_ADDTS_REFUSED_NSBW 3 /* ADDTS refused (non-sufficient BW) */ | ||
119 | #define DOT11E_STATUS_ADDTS_REFUSED_AWHILE 47 /* ADDTS refused but could retry later */ | ||
120 | |||
121 | /* 802.11e DELTS status code */ | ||
122 | #define DOT11E_STATUS_QSTA_LEAVE_QBSS 36 /* STA leave QBSS */ | ||
123 | #define DOT11E_STATUS_END_TS 37 /* END TS */ | ||
124 | #define DOT11E_STATUS_UNKNOWN_TS 38 /* UNKNOWN TS */ | ||
125 | #define DOT11E_STATUS_QSTA_REQ_TIMEOUT 39 /* STA ADDTS request timeout */ | ||
126 | |||
127 | |||
128 | /* This marks the end of a packed structure section. */ | ||
129 | #include <packed_section_end.h> | ||
130 | |||
131 | #endif /* _802_11e_CAC_H_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/802.1d.h b/drivers/net/wireless/bcmdhd/include/proto/802.1d.h new file mode 100644 index 00000000000..cf206250246 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/802.1d.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * | ||
22 | * Fundamental types and constants relating to 802.1D | ||
23 | * | ||
24 | * $Id: 802.1d.h,v 9.3 2007-04-10 21:33:06 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _802_1_D_ | ||
29 | #define _802_1_D_ | ||
30 | |||
31 | |||
32 | #define PRIO_8021D_NONE 2 | ||
33 | #define PRIO_8021D_BK 1 | ||
34 | #define PRIO_8021D_BE 0 | ||
35 | #define PRIO_8021D_EE 3 | ||
36 | #define PRIO_8021D_CL 4 | ||
37 | #define PRIO_8021D_VI 5 | ||
38 | #define PRIO_8021D_VO 6 | ||
39 | #define PRIO_8021D_NC 7 | ||
40 | #define MAXPRIO 7 | ||
41 | #define NUMPRIO (MAXPRIO + 1) | ||
42 | |||
43 | #define ALLPRIO -1 | ||
44 | |||
45 | |||
46 | #define PRIO2PREC(prio) \ | ||
47 | (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? ((prio^2)) : (prio)) | ||
48 | |||
49 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/bcmeth.h b/drivers/net/wireless/bcmdhd/include/proto/bcmeth.h new file mode 100644 index 00000000000..46fa4c9f89e --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/bcmeth.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * Broadcom Ethernettype protocol definitions | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bcmeth.h,v 9.12 2009-12-29 19:57:18 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | |||
29 | |||
30 | #ifndef _BCMETH_H_ | ||
31 | #define _BCMETH_H_ | ||
32 | |||
33 | #ifndef _TYPEDEFS_H_ | ||
34 | #include <typedefs.h> | ||
35 | #endif | ||
36 | |||
37 | |||
38 | #include <packed_section_start.h> | ||
39 | |||
40 | |||
41 | |||
42 | |||
43 | |||
44 | |||
45 | |||
46 | #define BCMILCP_SUBTYPE_RATE 1 | ||
47 | #define BCMILCP_SUBTYPE_LINK 2 | ||
48 | #define BCMILCP_SUBTYPE_CSA 3 | ||
49 | #define BCMILCP_SUBTYPE_LARQ 4 | ||
50 | #define BCMILCP_SUBTYPE_VENDOR 5 | ||
51 | #define BCMILCP_SUBTYPE_FLH 17 | ||
52 | |||
53 | #define BCMILCP_SUBTYPE_VENDOR_LONG 32769 | ||
54 | #define BCMILCP_SUBTYPE_CERT 32770 | ||
55 | #define BCMILCP_SUBTYPE_SES 32771 | ||
56 | |||
57 | |||
58 | #define BCMILCP_BCM_SUBTYPE_RESERVED 0 | ||
59 | #define BCMILCP_BCM_SUBTYPE_EVENT 1 | ||
60 | #define BCMILCP_BCM_SUBTYPE_SES 2 | ||
61 | |||
62 | |||
63 | #define BCMILCP_BCM_SUBTYPE_DPT 4 | ||
64 | |||
65 | #define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8 | ||
66 | #define BCMILCP_BCM_SUBTYPEHDR_VERSION 0 | ||
67 | |||
68 | |||
69 | typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr | ||
70 | { | ||
71 | uint16 subtype; | ||
72 | uint16 length; | ||
73 | uint8 version; | ||
74 | uint8 oui[3]; | ||
75 | |||
76 | uint16 usr_subtype; | ||
77 | } BWL_POST_PACKED_STRUCT bcmeth_hdr_t; | ||
78 | |||
79 | |||
80 | |||
81 | #include <packed_section_end.h> | ||
82 | |||
83 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h b/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h new file mode 100644 index 00000000000..30ec848c40a --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h | |||
@@ -0,0 +1,312 @@ | |||
1 | /* | ||
2 | * Broadcom Event protocol definitions | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * Dependencies: proto/bcmeth.h | ||
25 | * | ||
26 | * $Id: bcmevent.h,v 9.64.2.9 2011-02-01 06:24:21 Exp $ | ||
27 | * | ||
28 | */ | ||
29 | |||
30 | |||
31 | |||
32 | |||
33 | #ifndef _BCMEVENT_H_ | ||
34 | #define _BCMEVENT_H_ | ||
35 | |||
36 | #ifndef _TYPEDEFS_H_ | ||
37 | #include <typedefs.h> | ||
38 | #endif | ||
39 | |||
40 | |||
41 | #include <packed_section_start.h> | ||
42 | |||
43 | #define BCM_EVENT_MSG_VERSION 2 | ||
44 | #define BCM_MSG_IFNAME_MAX 16 | ||
45 | |||
46 | |||
47 | #define WLC_EVENT_MSG_LINK 0x01 | ||
48 | #define WLC_EVENT_MSG_FLUSHTXQ 0x02 | ||
49 | #define WLC_EVENT_MSG_GROUP 0x04 | ||
50 | #define WLC_EVENT_MSG_UNKBSS 0x08 | ||
51 | #define WLC_EVENT_MSG_UNKIF 0x10 | ||
52 | |||
53 | |||
54 | |||
55 | |||
56 | typedef BWL_PRE_PACKED_STRUCT struct | ||
57 | { | ||
58 | uint16 version; | ||
59 | uint16 flags; | ||
60 | uint32 event_type; | ||
61 | uint32 status; | ||
62 | uint32 reason; | ||
63 | uint32 auth_type; | ||
64 | uint32 datalen; | ||
65 | struct ether_addr addr; | ||
66 | char ifname[BCM_MSG_IFNAME_MAX]; | ||
67 | } BWL_POST_PACKED_STRUCT wl_event_msg_v1_t; | ||
68 | |||
69 | |||
70 | typedef BWL_PRE_PACKED_STRUCT struct | ||
71 | { | ||
72 | uint16 version; | ||
73 | uint16 flags; | ||
74 | uint32 event_type; | ||
75 | uint32 status; | ||
76 | uint32 reason; | ||
77 | uint32 auth_type; | ||
78 | uint32 datalen; | ||
79 | struct ether_addr addr; | ||
80 | char ifname[BCM_MSG_IFNAME_MAX]; | ||
81 | uint8 ifidx; | ||
82 | uint8 bsscfgidx; | ||
83 | } BWL_POST_PACKED_STRUCT wl_event_msg_t; | ||
84 | |||
85 | |||
86 | typedef BWL_PRE_PACKED_STRUCT struct bcm_event { | ||
87 | struct ether_header eth; | ||
88 | bcmeth_hdr_t bcm_hdr; | ||
89 | wl_event_msg_t event; | ||
90 | |||
91 | } BWL_POST_PACKED_STRUCT bcm_event_t; | ||
92 | |||
93 | #define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - sizeof(struct ether_header)) | ||
94 | |||
95 | |||
96 | #define WLC_E_SET_SSID 0 | ||
97 | #define WLC_E_JOIN 1 | ||
98 | #define WLC_E_START 2 | ||
99 | #define WLC_E_AUTH 3 | ||
100 | #define WLC_E_AUTH_IND 4 | ||
101 | #define WLC_E_DEAUTH 5 | ||
102 | #define WLC_E_DEAUTH_IND 6 | ||
103 | #define WLC_E_ASSOC 7 | ||
104 | #define WLC_E_ASSOC_IND 8 | ||
105 | #define WLC_E_REASSOC 9 | ||
106 | #define WLC_E_REASSOC_IND 10 | ||
107 | #define WLC_E_DISASSOC 11 | ||
108 | #define WLC_E_DISASSOC_IND 12 | ||
109 | #define WLC_E_QUIET_START 13 | ||
110 | #define WLC_E_QUIET_END 14 | ||
111 | #define WLC_E_BEACON_RX 15 | ||
112 | #define WLC_E_LINK 16 | ||
113 | #define WLC_E_MIC_ERROR 17 | ||
114 | #define WLC_E_NDIS_LINK 18 | ||
115 | #define WLC_E_ROAM 19 | ||
116 | #define WLC_E_TXFAIL 20 | ||
117 | #define WLC_E_PMKID_CACHE 21 | ||
118 | #define WLC_E_RETROGRADE_TSF 22 | ||
119 | #define WLC_E_PRUNE 23 | ||
120 | #define WLC_E_AUTOAUTH 24 | ||
121 | #define WLC_E_EAPOL_MSG 25 | ||
122 | #define WLC_E_SCAN_COMPLETE 26 | ||
123 | #define WLC_E_ADDTS_IND 27 | ||
124 | #define WLC_E_DELTS_IND 28 | ||
125 | #define WLC_E_BCNSENT_IND 29 | ||
126 | #define WLC_E_BCNRX_MSG 30 | ||
127 | #define WLC_E_BCNLOST_MSG 31 | ||
128 | #define WLC_E_ROAM_PREP 32 | ||
129 | #define WLC_E_PFN_NET_FOUND 33 | ||
130 | #define WLC_E_PFN_NET_LOST 34 | ||
131 | #define WLC_E_RESET_COMPLETE 35 | ||
132 | #define WLC_E_JOIN_START 36 | ||
133 | #define WLC_E_ROAM_START 37 | ||
134 | #define WLC_E_ASSOC_START 38 | ||
135 | #define WLC_E_IBSS_ASSOC 39 | ||
136 | #define WLC_E_RADIO 40 | ||
137 | #define WLC_E_PSM_WATCHDOG 41 | ||
138 | #define WLC_E_PROBREQ_MSG 44 | ||
139 | #define WLC_E_SCAN_CONFIRM_IND 45 | ||
140 | #define WLC_E_PSK_SUP 46 | ||
141 | #define WLC_E_COUNTRY_CODE_CHANGED 47 | ||
142 | #define WLC_E_EXCEEDED_MEDIUM_TIME 48 | ||
143 | #define WLC_E_ICV_ERROR 49 | ||
144 | #define WLC_E_UNICAST_DECODE_ERROR 50 | ||
145 | #define WLC_E_MULTICAST_DECODE_ERROR 51 | ||
146 | #define WLC_E_TRACE 52 | ||
147 | #define WLC_E_BTA_HCI_EVENT 53 | ||
148 | #define WLC_E_IF 54 | ||
149 | #ifdef WLP2P | ||
150 | #define WLC_E_P2P_DISC_LISTEN_COMPLETE 55 | ||
151 | #endif | ||
152 | #define WLC_E_RSSI 56 | ||
153 | #define WLC_E_PFN_SCAN_COMPLETE 57 | ||
154 | #define WLC_E_EXTLOG_MSG 58 | ||
155 | #define WLC_E_ACTION_FRAME 59 | ||
156 | #define WLC_E_ACTION_FRAME_COMPLETE 60 | ||
157 | #define WLC_E_PRE_ASSOC_IND 61 | ||
158 | #define WLC_E_PRE_REASSOC_IND 62 | ||
159 | #define WLC_E_CHANNEL_ADOPTED 63 | ||
160 | #define WLC_E_AP_STARTED 64 | ||
161 | #define WLC_E_DFS_AP_STOP 65 | ||
162 | #define WLC_E_DFS_AP_RESUME 66 | ||
163 | #define WLC_E_WAI_STA_EVENT 67 | ||
164 | #define WLC_E_WAI_MSG 68 | ||
165 | #define WLC_E_ESCAN_RESULT 69 | ||
166 | #define WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE 70 | ||
167 | #if defined(WLP2P) | ||
168 | #define WLC_E_PROBRESP_MSG 71 | ||
169 | #define WLC_E_P2P_PROBREQ_MSG 72 | ||
170 | #endif | ||
171 | #define WLC_E_DCS_REQUEST 73 | ||
172 | |||
173 | #define WLC_E_FIFO_CREDIT_MAP 74 | ||
174 | |||
175 | #define WLC_E_ACTION_FRAME_RX 75 | ||
176 | #define WLC_E_WAKE_EVENT 76 | ||
177 | #define WLC_E_RM_COMPLETE 77 | ||
178 | #define WLC_E_HTSFSYNC 78 | ||
179 | #define WLC_E_OVERLAY_REQ 79 | ||
180 | #define WLC_E_CSA_COMPLETE_IND 80 | ||
181 | #define WLC_E_EXCESS_PM_WAKE_EVENT 81 | ||
182 | #define WLC_E_PFN_SCAN_NONE 82 | ||
183 | #define WLC_E_PFN_SCAN_ALLGONE 83 | ||
184 | #define WLC_E_GTK_PLUMBED 84 | ||
185 | #define WLC_E_LAST 85 | ||
186 | |||
187 | |||
188 | typedef struct { | ||
189 | uint event; | ||
190 | const char *name; | ||
191 | } bcmevent_name_t; | ||
192 | |||
193 | extern const bcmevent_name_t bcmevent_names[]; | ||
194 | extern const int bcmevent_names_size; | ||
195 | |||
196 | |||
197 | #define WLC_E_STATUS_SUCCESS 0 | ||
198 | #define WLC_E_STATUS_FAIL 1 | ||
199 | #define WLC_E_STATUS_TIMEOUT 2 | ||
200 | #define WLC_E_STATUS_NO_NETWORKS 3 | ||
201 | #define WLC_E_STATUS_ABORT 4 | ||
202 | #define WLC_E_STATUS_NO_ACK 5 | ||
203 | #define WLC_E_STATUS_UNSOLICITED 6 | ||
204 | #define WLC_E_STATUS_ATTEMPT 7 | ||
205 | #define WLC_E_STATUS_PARTIAL 8 | ||
206 | #define WLC_E_STATUS_NEWSCAN 9 | ||
207 | #define WLC_E_STATUS_NEWASSOC 10 | ||
208 | #define WLC_E_STATUS_11HQUIET 11 | ||
209 | #define WLC_E_STATUS_SUPPRESS 12 | ||
210 | #define WLC_E_STATUS_NOCHANS 13 | ||
211 | #define WLC_E_STATUS_CS_ABORT 15 | ||
212 | #define WLC_E_STATUS_ERROR 16 | ||
213 | |||
214 | |||
215 | #define WLC_E_REASON_INITIAL_ASSOC 0 | ||
216 | #define WLC_E_REASON_LOW_RSSI 1 | ||
217 | #define WLC_E_REASON_DEAUTH 2 | ||
218 | #define WLC_E_REASON_DISASSOC 3 | ||
219 | #define WLC_E_REASON_BCNS_LOST 4 | ||
220 | #define WLC_E_REASON_MINTXRATE 9 | ||
221 | #define WLC_E_REASON_TXFAIL 10 | ||
222 | |||
223 | |||
224 | #define WLC_E_REASON_FAST_ROAM_FAILED 5 | ||
225 | #define WLC_E_REASON_DIRECTED_ROAM 6 | ||
226 | #define WLC_E_REASON_TSPEC_REJECTED 7 | ||
227 | #define WLC_E_REASON_BETTER_AP 8 | ||
228 | |||
229 | |||
230 | #define WLC_E_PRUNE_ENCR_MISMATCH 1 | ||
231 | #define WLC_E_PRUNE_BCAST_BSSID 2 | ||
232 | #define WLC_E_PRUNE_MAC_DENY 3 | ||
233 | #define WLC_E_PRUNE_MAC_NA 4 | ||
234 | #define WLC_E_PRUNE_REG_PASSV 5 | ||
235 | #define WLC_E_PRUNE_SPCT_MGMT 6 | ||
236 | #define WLC_E_PRUNE_RADAR 7 | ||
237 | #define WLC_E_RSN_MISMATCH 8 | ||
238 | #define WLC_E_PRUNE_NO_COMMON_RATES 9 | ||
239 | #define WLC_E_PRUNE_BASIC_RATES 10 | ||
240 | #define WLC_E_PRUNE_CIPHER_NA 12 | ||
241 | #define WLC_E_PRUNE_KNOWN_STA 13 | ||
242 | #define WLC_E_PRUNE_WDS_PEER 15 | ||
243 | #define WLC_E_PRUNE_QBSS_LOAD 16 | ||
244 | #define WLC_E_PRUNE_HOME_AP 17 | ||
245 | |||
246 | |||
247 | #define WLC_E_SUP_OTHER 0 | ||
248 | #define WLC_E_SUP_DECRYPT_KEY_DATA 1 | ||
249 | #define WLC_E_SUP_BAD_UCAST_WEP128 2 | ||
250 | #define WLC_E_SUP_BAD_UCAST_WEP40 3 | ||
251 | #define WLC_E_SUP_UNSUP_KEY_LEN 4 | ||
252 | #define WLC_E_SUP_PW_KEY_CIPHER 5 | ||
253 | #define WLC_E_SUP_MSG3_TOO_MANY_IE 6 | ||
254 | #define WLC_E_SUP_MSG3_IE_MISMATCH 7 | ||
255 | #define WLC_E_SUP_NO_INSTALL_FLAG 8 | ||
256 | #define WLC_E_SUP_MSG3_NO_GTK 9 | ||
257 | #define WLC_E_SUP_GRP_KEY_CIPHER 10 | ||
258 | #define WLC_E_SUP_GRP_MSG1_NO_GTK 11 | ||
259 | #define WLC_E_SUP_GTK_DECRYPT_FAIL 12 | ||
260 | #define WLC_E_SUP_SEND_FAIL 13 | ||
261 | #define WLC_E_SUP_DEAUTH 14 | ||
262 | #define WLC_E_SUP_WPA_PSK_TMO 15 | ||
263 | |||
264 | |||
265 | |||
266 | typedef BWL_PRE_PACKED_STRUCT struct wl_event_rx_frame_data { | ||
267 | uint16 version; | ||
268 | uint16 channel; | ||
269 | int32 rssi; | ||
270 | uint32 mactime; | ||
271 | uint32 rate; | ||
272 | } BWL_POST_PACKED_STRUCT wl_event_rx_frame_data_t; | ||
273 | |||
274 | #define BCM_RX_FRAME_DATA_VERSION 1 | ||
275 | |||
276 | |||
277 | typedef struct wl_event_data_if { | ||
278 | uint8 ifidx; | ||
279 | uint8 opcode; | ||
280 | uint8 reserved; | ||
281 | uint8 bssidx; | ||
282 | uint8 role; | ||
283 | } wl_event_data_if_t; | ||
284 | |||
285 | |||
286 | #define WLC_E_IF_ADD 1 | ||
287 | #define WLC_E_IF_DEL 2 | ||
288 | #define WLC_E_IF_CHANGE 3 | ||
289 | |||
290 | |||
291 | #define WLC_E_IF_ROLE_STA 0 | ||
292 | #define WLC_E_IF_ROLE_AP 1 | ||
293 | #define WLC_E_IF_ROLE_WDS 2 | ||
294 | #define WLC_E_IF_ROLE_P2P_GO 3 | ||
295 | #define WLC_E_IF_ROLE_P2P_CLIENT 4 | ||
296 | #define WLC_E_IF_ROLE_BTA_CREATOR 5 | ||
297 | #define WLC_E_IF_ROLE_BTA_ACCEPTOR 6 | ||
298 | |||
299 | |||
300 | #define WLC_E_LINK_BCN_LOSS 1 | ||
301 | #define WLC_E_LINK_DISASSOC 2 | ||
302 | #define WLC_E_LINK_ASSOC_REC 3 | ||
303 | #define WLC_E_LINK_BSSCFG_DIS 4 | ||
304 | |||
305 | |||
306 | #define WLC_E_OVL_DOWNLOAD 0 | ||
307 | #define WLC_E_OVL_UPDATE_IND 1 | ||
308 | |||
309 | |||
310 | #include <packed_section_end.h> | ||
311 | |||
312 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/bcmip.h b/drivers/net/wireless/bcmdhd/include/proto/bcmip.h new file mode 100644 index 00000000000..8a8f3146d56 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/bcmip.h | |||
@@ -0,0 +1,154 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * | ||
22 | * Fundamental constants relating to IP Protocol | ||
23 | * | ||
24 | * $Id: bcmip.h,v 9.19 2009-11-10 20:08:33 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _bcmip_h_ | ||
29 | #define _bcmip_h_ | ||
30 | |||
31 | #ifndef _TYPEDEFS_H_ | ||
32 | #include <typedefs.h> | ||
33 | #endif | ||
34 | |||
35 | |||
36 | #include <packed_section_start.h> | ||
37 | |||
38 | |||
39 | |||
40 | #define IP_VER_OFFSET 0x0 | ||
41 | #define IP_VER_MASK 0xf0 | ||
42 | #define IP_VER_SHIFT 4 | ||
43 | #define IP_VER_4 4 | ||
44 | #define IP_VER_6 6 | ||
45 | |||
46 | #define IP_VER(ip_body) \ | ||
47 | ((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT) | ||
48 | |||
49 | #define IP_PROT_ICMP 0x1 | ||
50 | #define IP_PROT_TCP 0x6 | ||
51 | #define IP_PROT_UDP 0x11 | ||
52 | |||
53 | |||
54 | #define IPV4_VER_HL_OFFSET 0 | ||
55 | #define IPV4_TOS_OFFSET 1 | ||
56 | #define IPV4_PKTLEN_OFFSET 2 | ||
57 | #define IPV4_PKTFLAG_OFFSET 6 | ||
58 | #define IPV4_PROT_OFFSET 9 | ||
59 | #define IPV4_CHKSUM_OFFSET 10 | ||
60 | #define IPV4_SRC_IP_OFFSET 12 | ||
61 | #define IPV4_DEST_IP_OFFSET 16 | ||
62 | #define IPV4_OPTIONS_OFFSET 20 | ||
63 | |||
64 | |||
65 | #define IPV4_VER_MASK 0xf0 | ||
66 | #define IPV4_VER_SHIFT 4 | ||
67 | |||
68 | #define IPV4_HLEN_MASK 0x0f | ||
69 | #define IPV4_HLEN(ipv4_body) (4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK)) | ||
70 | |||
71 | #define IPV4_ADDR_LEN 4 | ||
72 | |||
73 | #define IPV4_ADDR_NULL(a) ((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \ | ||
74 | ((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0) | ||
75 | |||
76 | #define IPV4_ADDR_BCAST(a) ((((uint8 *)(a))[0] & ((uint8 *)(a))[1] & \ | ||
77 | ((uint8 *)(a))[2] & ((uint8 *)(a))[3]) == 0xff) | ||
78 | |||
79 | #define IPV4_TOS_DSCP_MASK 0xfc | ||
80 | #define IPV4_TOS_DSCP_SHIFT 2 | ||
81 | |||
82 | #define IPV4_TOS(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET]) | ||
83 | |||
84 | #define IPV4_TOS_PREC_MASK 0xe0 | ||
85 | #define IPV4_TOS_PREC_SHIFT 5 | ||
86 | |||
87 | #define IPV4_TOS_LOWDELAY 0x10 | ||
88 | #define IPV4_TOS_THROUGHPUT 0x8 | ||
89 | #define IPV4_TOS_RELIABILITY 0x4 | ||
90 | |||
91 | #define IPV4_PROT(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET]) | ||
92 | |||
93 | #define IPV4_FRAG_RESV 0x8000 | ||
94 | #define IPV4_FRAG_DONT 0x4000 | ||
95 | #define IPV4_FRAG_MORE 0x2000 | ||
96 | #define IPV4_FRAG_OFFSET_MASK 0x1fff | ||
97 | |||
98 | #define IPV4_ADDR_STR_LEN 16 | ||
99 | |||
100 | |||
101 | BWL_PRE_PACKED_STRUCT struct ipv4_addr { | ||
102 | uint8 addr[IPV4_ADDR_LEN]; | ||
103 | } BWL_POST_PACKED_STRUCT; | ||
104 | |||
105 | BWL_PRE_PACKED_STRUCT struct ipv4_hdr { | ||
106 | uint8 version_ihl; | ||
107 | uint8 tos; | ||
108 | uint16 tot_len; | ||
109 | uint16 id; | ||
110 | uint16 frag; | ||
111 | uint8 ttl; | ||
112 | uint8 prot; | ||
113 | uint16 hdr_chksum; | ||
114 | uint8 src_ip[IPV4_ADDR_LEN]; | ||
115 | uint8 dst_ip[IPV4_ADDR_LEN]; | ||
116 | } BWL_POST_PACKED_STRUCT; | ||
117 | |||
118 | |||
119 | #define IPV6_PAYLOAD_LEN_OFFSET 4 | ||
120 | #define IPV6_NEXT_HDR_OFFSET 6 | ||
121 | #define IPV6_HOP_LIMIT_OFFSET 7 | ||
122 | #define IPV6_SRC_IP_OFFSET 8 | ||
123 | #define IPV6_DEST_IP_OFFSET 24 | ||
124 | |||
125 | |||
126 | #define IPV6_TRAFFIC_CLASS(ipv6_body) \ | ||
127 | (((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \ | ||
128 | ((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4)) | ||
129 | |||
130 | #define IPV6_FLOW_LABEL(ipv6_body) \ | ||
131 | (((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \ | ||
132 | (((uint8 *)(ipv6_body))[2] << 8) | \ | ||
133 | (((uint8 *)(ipv6_body))[3])) | ||
134 | |||
135 | #define IPV6_PAYLOAD_LEN(ipv6_body) \ | ||
136 | ((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \ | ||
137 | ((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1]) | ||
138 | |||
139 | #define IPV6_NEXT_HDR(ipv6_body) \ | ||
140 | (((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET]) | ||
141 | |||
142 | #define IPV6_PROT(ipv6_body) IPV6_NEXT_HDR(ipv6_body) | ||
143 | |||
144 | #define IPV6_ADDR_LEN 16 | ||
145 | |||
146 | |||
147 | #define IP_TOS46(ip_body) \ | ||
148 | (IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \ | ||
149 | IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0) | ||
150 | |||
151 | |||
152 | #include <packed_section_end.h> | ||
153 | |||
154 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/bt_amp_hci.h b/drivers/net/wireless/bcmdhd/include/proto/bt_amp_hci.h new file mode 100644 index 00000000000..89c11817915 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/bt_amp_hci.h | |||
@@ -0,0 +1,442 @@ | |||
1 | /* | ||
2 | * BT-AMP (BlueTooth Alternate Mac and Phy) HCI (Host/Controller Interface) | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: bt_amp_hci.h,v 9.14.8.2 2010-09-10 18:37:47 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _bt_amp_hci_h | ||
28 | #define _bt_amp_hci_h | ||
29 | |||
30 | /* This marks the start of a packed structure section. */ | ||
31 | #include <packed_section_start.h> | ||
32 | |||
33 | |||
34 | /* AMP HCI CMD packet format */ | ||
35 | typedef BWL_PRE_PACKED_STRUCT struct amp_hci_cmd { | ||
36 | uint16 opcode; | ||
37 | uint8 plen; | ||
38 | uint8 parms[1]; | ||
39 | } BWL_POST_PACKED_STRUCT amp_hci_cmd_t; | ||
40 | |||
41 | #define HCI_CMD_PREAMBLE_SIZE OFFSETOF(amp_hci_cmd_t, parms) | ||
42 | #define HCI_CMD_DATA_SIZE 255 | ||
43 | |||
44 | /* AMP HCI CMD opcode layout */ | ||
45 | #define HCI_CMD_OPCODE(ogf, ocf) ((((ogf) & 0x3F) << 10) | ((ocf) & 0x03FF)) | ||
46 | #define HCI_CMD_OGF(opcode) ((uint8)(((opcode) >> 10) & 0x3F)) | ||
47 | #define HCI_CMD_OCF(opcode) ((opcode) & 0x03FF) | ||
48 | |||
49 | /* AMP HCI command opcodes */ | ||
50 | #define HCI_Read_Failed_Contact_Counter HCI_CMD_OPCODE(0x05, 0x0001) | ||
51 | #define HCI_Reset_Failed_Contact_Counter HCI_CMD_OPCODE(0x05, 0x0002) | ||
52 | #define HCI_Read_Link_Quality HCI_CMD_OPCODE(0x05, 0x0003) | ||
53 | #define HCI_Read_Local_AMP_Info HCI_CMD_OPCODE(0x05, 0x0009) | ||
54 | #define HCI_Read_Local_AMP_ASSOC HCI_CMD_OPCODE(0x05, 0x000A) | ||
55 | #define HCI_Write_Remote_AMP_ASSOC HCI_CMD_OPCODE(0x05, 0x000B) | ||
56 | #define HCI_Create_Physical_Link HCI_CMD_OPCODE(0x01, 0x0035) | ||
57 | #define HCI_Accept_Physical_Link_Request HCI_CMD_OPCODE(0x01, 0x0036) | ||
58 | #define HCI_Disconnect_Physical_Link HCI_CMD_OPCODE(0x01, 0x0037) | ||
59 | #define HCI_Create_Logical_Link HCI_CMD_OPCODE(0x01, 0x0038) | ||
60 | #define HCI_Accept_Logical_Link HCI_CMD_OPCODE(0x01, 0x0039) | ||
61 | #define HCI_Disconnect_Logical_Link HCI_CMD_OPCODE(0x01, 0x003A) | ||
62 | #define HCI_Logical_Link_Cancel HCI_CMD_OPCODE(0x01, 0x003B) | ||
63 | #define HCI_Flow_Spec_Modify HCI_CMD_OPCODE(0x01, 0x003C) | ||
64 | #define HCI_Write_Flow_Control_Mode HCI_CMD_OPCODE(0x01, 0x0067) | ||
65 | #define HCI_Read_Best_Effort_Flush_Timeout HCI_CMD_OPCODE(0x01, 0x0069) | ||
66 | #define HCI_Write_Best_Effort_Flush_Timeout HCI_CMD_OPCODE(0x01, 0x006A) | ||
67 | #define HCI_Short_Range_Mode HCI_CMD_OPCODE(0x01, 0x006B) | ||
68 | #define HCI_Reset HCI_CMD_OPCODE(0x03, 0x0003) | ||
69 | #define HCI_Read_Connection_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0015) | ||
70 | #define HCI_Write_Connection_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0016) | ||
71 | #define HCI_Read_Link_Supervision_Timeout HCI_CMD_OPCODE(0x03, 0x0036) | ||
72 | #define HCI_Write_Link_Supervision_Timeout HCI_CMD_OPCODE(0x03, 0x0037) | ||
73 | #define HCI_Enhanced_Flush HCI_CMD_OPCODE(0x03, 0x005F) | ||
74 | #define HCI_Read_Logical_Link_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0061) | ||
75 | #define HCI_Write_Logical_Link_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0062) | ||
76 | #define HCI_Set_Event_Mask_Page_2 HCI_CMD_OPCODE(0x03, 0x0063) | ||
77 | #define HCI_Read_Location_Data_Command HCI_CMD_OPCODE(0x03, 0x0064) | ||
78 | #define HCI_Write_Location_Data_Command HCI_CMD_OPCODE(0x03, 0x0065) | ||
79 | #define HCI_Read_Local_Version_Info HCI_CMD_OPCODE(0x04, 0x0001) | ||
80 | #define HCI_Read_Local_Supported_Commands HCI_CMD_OPCODE(0x04, 0x0002) | ||
81 | #define HCI_Read_Buffer_Size HCI_CMD_OPCODE(0x04, 0x0005) | ||
82 | #define HCI_Read_Data_Block_Size HCI_CMD_OPCODE(0x04, 0x000A) | ||
83 | |||
84 | /* AMP HCI command parameters */ | ||
85 | typedef BWL_PRE_PACKED_STRUCT struct read_local_cmd_parms { | ||
86 | uint8 plh; | ||
87 | uint8 offset[2]; /* length so far */ | ||
88 | uint8 max_remote[2]; | ||
89 | } BWL_POST_PACKED_STRUCT read_local_cmd_parms_t; | ||
90 | |||
91 | typedef BWL_PRE_PACKED_STRUCT struct write_remote_cmd_parms { | ||
92 | uint8 plh; | ||
93 | uint8 offset[2]; | ||
94 | uint8 len[2]; | ||
95 | uint8 frag[1]; | ||
96 | } BWL_POST_PACKED_STRUCT write_remote_cmd_parms_t; | ||
97 | |||
98 | typedef BWL_PRE_PACKED_STRUCT struct phy_link_cmd_parms { | ||
99 | uint8 plh; | ||
100 | uint8 key_length; | ||
101 | uint8 key_type; | ||
102 | uint8 key[1]; | ||
103 | } BWL_POST_PACKED_STRUCT phy_link_cmd_parms_t; | ||
104 | |||
105 | typedef BWL_PRE_PACKED_STRUCT struct dis_phy_link_cmd_parms { | ||
106 | uint8 plh; | ||
107 | uint8 reason; | ||
108 | } BWL_POST_PACKED_STRUCT dis_phy_link_cmd_parms_t; | ||
109 | |||
110 | typedef BWL_PRE_PACKED_STRUCT struct log_link_cmd_parms { | ||
111 | uint8 plh; | ||
112 | uint8 txflow[16]; | ||
113 | uint8 rxflow[16]; | ||
114 | } BWL_POST_PACKED_STRUCT log_link_cmd_parms_t; | ||
115 | |||
116 | typedef BWL_PRE_PACKED_STRUCT struct ext_flow_spec { | ||
117 | uint8 id; | ||
118 | uint8 service_type; | ||
119 | uint8 max_sdu[2]; | ||
120 | uint8 sdu_ia_time[4]; | ||
121 | uint8 access_latency[4]; | ||
122 | uint8 flush_timeout[4]; | ||
123 | } BWL_POST_PACKED_STRUCT ext_flow_spec_t; | ||
124 | |||
125 | typedef BWL_PRE_PACKED_STRUCT struct log_link_cancel_cmd_parms { | ||
126 | uint8 plh; | ||
127 | uint8 tx_fs_ID; | ||
128 | } BWL_POST_PACKED_STRUCT log_link_cancel_cmd_parms_t; | ||
129 | |||
130 | typedef BWL_PRE_PACKED_STRUCT struct flow_spec_mod_cmd_parms { | ||
131 | uint8 llh[2]; | ||
132 | uint8 txflow[16]; | ||
133 | uint8 rxflow[16]; | ||
134 | } BWL_POST_PACKED_STRUCT flow_spec_mod_cmd_parms_t; | ||
135 | |||
136 | typedef BWL_PRE_PACKED_STRUCT struct plh_pad { | ||
137 | uint8 plh; | ||
138 | uint8 pad; | ||
139 | } BWL_POST_PACKED_STRUCT plh_pad_t; | ||
140 | |||
141 | typedef BWL_PRE_PACKED_STRUCT union hci_handle { | ||
142 | uint16 bredr; | ||
143 | plh_pad_t amp; | ||
144 | } BWL_POST_PACKED_STRUCT hci_handle_t; | ||
145 | |||
146 | typedef BWL_PRE_PACKED_STRUCT struct ls_to_cmd_parms { | ||
147 | hci_handle_t handle; | ||
148 | uint8 timeout[2]; | ||
149 | } BWL_POST_PACKED_STRUCT ls_to_cmd_parms_t; | ||
150 | |||
151 | typedef BWL_PRE_PACKED_STRUCT struct befto_cmd_parms { | ||
152 | uint8 llh[2]; | ||
153 | uint8 befto[4]; | ||
154 | } BWL_POST_PACKED_STRUCT befto_cmd_parms_t; | ||
155 | |||
156 | typedef BWL_PRE_PACKED_STRUCT struct srm_cmd_parms { | ||
157 | uint8 plh; | ||
158 | uint8 srm; | ||
159 | } BWL_POST_PACKED_STRUCT srm_cmd_parms_t; | ||
160 | |||
161 | typedef BWL_PRE_PACKED_STRUCT struct ld_cmd_parms { | ||
162 | uint8 ld_aware; | ||
163 | uint8 ld[2]; | ||
164 | uint8 ld_opts; | ||
165 | uint8 l_opts; | ||
166 | } BWL_POST_PACKED_STRUCT ld_cmd_parms_t; | ||
167 | |||
168 | typedef BWL_PRE_PACKED_STRUCT struct eflush_cmd_parms { | ||
169 | uint8 llh[2]; | ||
170 | uint8 packet_type; | ||
171 | } BWL_POST_PACKED_STRUCT eflush_cmd_parms_t; | ||
172 | |||
173 | /* Generic AMP extended flow spec service types */ | ||
174 | #define EFS_SVCTYPE_NO_TRAFFIC 0 | ||
175 | #define EFS_SVCTYPE_BEST_EFFORT 1 | ||
176 | #define EFS_SVCTYPE_GUARANTEED 2 | ||
177 | |||
178 | /* AMP HCI event packet format */ | ||
179 | typedef BWL_PRE_PACKED_STRUCT struct amp_hci_event { | ||
180 | uint8 ecode; | ||
181 | uint8 plen; | ||
182 | uint8 parms[1]; | ||
183 | } BWL_POST_PACKED_STRUCT amp_hci_event_t; | ||
184 | |||
185 | #define HCI_EVT_PREAMBLE_SIZE OFFSETOF(amp_hci_event_t, parms) | ||
186 | |||
187 | /* AMP HCI event codes */ | ||
188 | #define HCI_Command_Complete 0x0E | ||
189 | #define HCI_Command_Status 0x0F | ||
190 | #define HCI_Flush_Occurred 0x11 | ||
191 | #define HCI_Enhanced_Flush_Complete 0x39 | ||
192 | #define HCI_Physical_Link_Complete 0x40 | ||
193 | #define HCI_Channel_Select 0x41 | ||
194 | #define HCI_Disconnect_Physical_Link_Complete 0x42 | ||
195 | #define HCI_Logical_Link_Complete 0x45 | ||
196 | #define HCI_Disconnect_Logical_Link_Complete 0x46 | ||
197 | #define HCI_Flow_Spec_Modify_Complete 0x47 | ||
198 | #define HCI_Number_of_Completed_Data_Blocks 0x48 | ||
199 | #define HCI_Short_Range_Mode_Change_Complete 0x4C | ||
200 | #define HCI_Status_Change_Event 0x4D | ||
201 | #define HCI_Vendor_Specific 0xFF | ||
202 | |||
203 | /* AMP HCI event mask bit positions */ | ||
204 | #define HCI_Physical_Link_Complete_Event_Mask 0x0001 | ||
205 | #define HCI_Channel_Select_Event_Mask 0x0002 | ||
206 | #define HCI_Disconnect_Physical_Link_Complete_Event_Mask 0x0004 | ||
207 | #define HCI_Logical_Link_Complete_Event_Mask 0x0020 | ||
208 | #define HCI_Disconnect_Logical_Link_Complete_Event_Mask 0x0040 | ||
209 | #define HCI_Flow_Spec_Modify_Complete_Event_Mask 0x0080 | ||
210 | #define HCI_Number_of_Completed_Data_Blocks_Event_Mask 0x0100 | ||
211 | #define HCI_Short_Range_Mode_Change_Complete_Event_Mask 0x1000 | ||
212 | #define HCI_Status_Change_Event_Mask 0x2000 | ||
213 | #define HCI_All_Event_Mask 0x31e7 | ||
214 | |||
215 | /* AMP HCI event parameters */ | ||
216 | typedef BWL_PRE_PACKED_STRUCT struct cmd_status_parms { | ||
217 | uint8 status; | ||
218 | uint8 cmdpkts; | ||
219 | uint16 opcode; | ||
220 | } BWL_POST_PACKED_STRUCT cmd_status_parms_t; | ||
221 | |||
222 | typedef BWL_PRE_PACKED_STRUCT struct cmd_complete_parms { | ||
223 | uint8 cmdpkts; | ||
224 | uint16 opcode; | ||
225 | uint8 parms[1]; | ||
226 | } BWL_POST_PACKED_STRUCT cmd_complete_parms_t; | ||
227 | |||
228 | typedef BWL_PRE_PACKED_STRUCT struct flush_occurred_evt_parms { | ||
229 | uint16 handle; | ||
230 | } BWL_POST_PACKED_STRUCT flush_occurred_evt_parms_t; | ||
231 | |||
232 | typedef BWL_PRE_PACKED_STRUCT struct write_remote_evt_parms { | ||
233 | uint8 status; | ||
234 | uint8 plh; | ||
235 | } BWL_POST_PACKED_STRUCT write_remote_evt_parms_t; | ||
236 | |||
237 | typedef BWL_PRE_PACKED_STRUCT struct read_local_evt_parms { | ||
238 | uint8 status; | ||
239 | uint8 plh; | ||
240 | uint16 len; | ||
241 | uint8 frag[1]; | ||
242 | } BWL_POST_PACKED_STRUCT read_local_evt_parms_t; | ||
243 | |||
244 | typedef BWL_PRE_PACKED_STRUCT struct read_local_info_evt_parms { | ||
245 | uint8 status; | ||
246 | uint8 AMP_status; | ||
247 | uint32 bandwidth; | ||
248 | uint32 gbandwidth; | ||
249 | uint32 latency; | ||
250 | uint32 PDU_size; | ||
251 | uint8 ctrl_type; | ||
252 | uint16 PAL_cap; | ||
253 | uint16 AMP_ASSOC_len; | ||
254 | uint32 max_flush_timeout; | ||
255 | uint32 be_flush_timeout; | ||
256 | } BWL_POST_PACKED_STRUCT read_local_info_evt_parms_t; | ||
257 | |||
258 | typedef BWL_PRE_PACKED_STRUCT struct log_link_evt_parms { | ||
259 | uint8 status; | ||
260 | uint16 llh; | ||
261 | uint8 plh; | ||
262 | uint8 tx_fs_ID; | ||
263 | } BWL_POST_PACKED_STRUCT log_link_evt_parms_t; | ||
264 | |||
265 | typedef BWL_PRE_PACKED_STRUCT struct disc_log_link_evt_parms { | ||
266 | uint8 status; | ||
267 | uint16 llh; | ||
268 | uint8 reason; | ||
269 | } BWL_POST_PACKED_STRUCT disc_log_link_evt_parms_t; | ||
270 | |||
271 | typedef BWL_PRE_PACKED_STRUCT struct log_link_cancel_evt_parms { | ||
272 | uint8 status; | ||
273 | uint8 plh; | ||
274 | uint8 tx_fs_ID; | ||
275 | } BWL_POST_PACKED_STRUCT log_link_cancel_evt_parms_t; | ||
276 | |||
277 | typedef BWL_PRE_PACKED_STRUCT struct flow_spec_mod_evt_parms { | ||
278 | uint8 status; | ||
279 | uint16 llh; | ||
280 | } BWL_POST_PACKED_STRUCT flow_spec_mod_evt_parms_t; | ||
281 | |||
282 | typedef BWL_PRE_PACKED_STRUCT struct phy_link_evt_parms { | ||
283 | uint8 status; | ||
284 | uint8 plh; | ||
285 | } BWL_POST_PACKED_STRUCT phy_link_evt_parms_t; | ||
286 | |||
287 | typedef BWL_PRE_PACKED_STRUCT struct dis_phy_link_evt_parms { | ||
288 | uint8 status; | ||
289 | uint8 plh; | ||
290 | uint8 reason; | ||
291 | } BWL_POST_PACKED_STRUCT dis_phy_link_evt_parms_t; | ||
292 | |||
293 | typedef BWL_PRE_PACKED_STRUCT struct read_ls_to_evt_parms { | ||
294 | uint8 status; | ||
295 | hci_handle_t handle; | ||
296 | uint16 timeout; | ||
297 | } BWL_POST_PACKED_STRUCT read_ls_to_evt_parms_t; | ||
298 | |||
299 | typedef BWL_PRE_PACKED_STRUCT struct read_lla_ca_to_evt_parms { | ||
300 | uint8 status; | ||
301 | uint16 timeout; | ||
302 | } BWL_POST_PACKED_STRUCT read_lla_ca_to_evt_parms_t; | ||
303 | |||
304 | typedef BWL_PRE_PACKED_STRUCT struct read_data_block_size_evt_parms { | ||
305 | uint8 status; | ||
306 | uint16 ACL_pkt_len; | ||
307 | uint16 data_block_len; | ||
308 | uint16 data_block_num; | ||
309 | } BWL_POST_PACKED_STRUCT read_data_block_size_evt_parms_t; | ||
310 | |||
311 | typedef BWL_PRE_PACKED_STRUCT struct data_blocks { | ||
312 | uint16 handle; | ||
313 | uint16 pkts; | ||
314 | uint16 blocks; | ||
315 | } BWL_POST_PACKED_STRUCT data_blocks_t; | ||
316 | |||
317 | typedef BWL_PRE_PACKED_STRUCT struct num_completed_data_blocks_evt_parms { | ||
318 | uint16 num_blocks; | ||
319 | uint8 num_handles; | ||
320 | data_blocks_t completed[1]; | ||
321 | } BWL_POST_PACKED_STRUCT num_completed_data_blocks_evt_parms_t; | ||
322 | |||
323 | typedef BWL_PRE_PACKED_STRUCT struct befto_evt_parms { | ||
324 | uint8 status; | ||
325 | uint32 befto; | ||
326 | } BWL_POST_PACKED_STRUCT befto_evt_parms_t; | ||
327 | |||
328 | typedef BWL_PRE_PACKED_STRUCT struct srm_evt_parms { | ||
329 | uint8 status; | ||
330 | uint8 plh; | ||
331 | uint8 srm; | ||
332 | } BWL_POST_PACKED_STRUCT srm_evt_parms_t; | ||
333 | |||
334 | typedef BWL_PRE_PACKED_STRUCT struct contact_counter_evt_parms { | ||
335 | uint8 status; | ||
336 | uint8 llh[2]; | ||
337 | uint16 counter; | ||
338 | } BWL_POST_PACKED_STRUCT contact_counter_evt_parms_t; | ||
339 | |||
340 | typedef BWL_PRE_PACKED_STRUCT struct contact_counter_reset_evt_parms { | ||
341 | uint8 status; | ||
342 | uint8 llh[2]; | ||
343 | } BWL_POST_PACKED_STRUCT contact_counter_reset_evt_parms_t; | ||
344 | |||
345 | typedef BWL_PRE_PACKED_STRUCT struct read_linkq_evt_parms { | ||
346 | uint8 status; | ||
347 | hci_handle_t handle; | ||
348 | uint8 link_quality; | ||
349 | } BWL_POST_PACKED_STRUCT read_linkq_evt_parms_t; | ||
350 | |||
351 | typedef BWL_PRE_PACKED_STRUCT struct ld_evt_parms { | ||
352 | uint8 status; | ||
353 | uint8 ld_aware; | ||
354 | uint8 ld[2]; | ||
355 | uint8 ld_opts; | ||
356 | uint8 l_opts; | ||
357 | } BWL_POST_PACKED_STRUCT ld_evt_parms_t; | ||
358 | |||
359 | typedef BWL_PRE_PACKED_STRUCT struct eflush_complete_evt_parms { | ||
360 | uint16 handle; | ||
361 | } BWL_POST_PACKED_STRUCT eflush_complete_evt_parms_t; | ||
362 | |||
363 | typedef BWL_PRE_PACKED_STRUCT struct vendor_specific_evt_parms { | ||
364 | uint8 len; | ||
365 | uint8 parms[1]; | ||
366 | } BWL_POST_PACKED_STRUCT vendor_specific_evt_parms_t; | ||
367 | |||
368 | typedef BWL_PRE_PACKED_STRUCT struct local_version_info_evt_parms { | ||
369 | uint8 status; | ||
370 | uint8 hci_version; | ||
371 | uint16 hci_revision; | ||
372 | uint8 pal_version; | ||
373 | uint16 mfg_name; | ||
374 | uint16 pal_subversion; | ||
375 | } BWL_POST_PACKED_STRUCT local_version_info_evt_parms_t; | ||
376 | |||
377 | #define MAX_SUPPORTED_CMD_BYTE 64 | ||
378 | typedef BWL_PRE_PACKED_STRUCT struct local_supported_cmd_evt_parms { | ||
379 | uint8 status; | ||
380 | uint8 cmd[MAX_SUPPORTED_CMD_BYTE]; | ||
381 | } BWL_POST_PACKED_STRUCT local_supported_cmd_evt_parms_t; | ||
382 | |||
383 | typedef BWL_PRE_PACKED_STRUCT struct status_change_evt_parms { | ||
384 | uint8 status; | ||
385 | uint8 amp_status; | ||
386 | } BWL_POST_PACKED_STRUCT status_change_evt_parms_t; | ||
387 | |||
388 | /* AMP HCI error codes */ | ||
389 | #define HCI_SUCCESS 0x00 | ||
390 | #define HCI_ERR_ILLEGAL_COMMAND 0x01 | ||
391 | #define HCI_ERR_NO_CONNECTION 0x02 | ||
392 | #define HCI_ERR_MEMORY_FULL 0x07 | ||
393 | #define HCI_ERR_CONNECTION_TIMEOUT 0x08 | ||
394 | #define HCI_ERR_MAX_NUM_OF_CONNECTIONS 0x09 | ||
395 | #define HCI_ERR_CONNECTION_EXISTS 0x0B | ||
396 | #define HCI_ERR_CONNECTION_DISALLOWED 0x0C | ||
397 | #define HCI_ERR_CONNECTION_ACCEPT_TIMEOUT 0x10 | ||
398 | #define HCI_ERR_UNSUPPORTED_VALUE 0x11 | ||
399 | #define HCI_ERR_ILLEGAL_PARAMETER_FMT 0x12 | ||
400 | #define HCI_ERR_CONN_TERM_BY_LOCAL_HOST 0x16 | ||
401 | #define HCI_ERR_UNSPECIFIED 0x1F | ||
402 | #define HCI_ERR_UNIT_KEY_USED 0x26 | ||
403 | #define HCI_ERR_QOS_REJECTED 0x2D | ||
404 | #define HCI_ERR_PARAM_OUT_OF_RANGE 0x30 | ||
405 | #define HCI_ERR_NO_SUITABLE_CHANNEL 0x39 | ||
406 | #define HCI_ERR_CHANNEL_MOVE 0xFF | ||
407 | |||
408 | /* AMP HCI ACL Data packet format */ | ||
409 | typedef BWL_PRE_PACKED_STRUCT struct amp_hci_ACL_data { | ||
410 | uint16 handle; /* 12-bit connection handle + 2-bit PB and 2-bit BC flags */ | ||
411 | uint16 dlen; /* data total length */ | ||
412 | uint8 data[1]; | ||
413 | } BWL_POST_PACKED_STRUCT amp_hci_ACL_data_t; | ||
414 | |||
415 | #define HCI_ACL_DATA_PREAMBLE_SIZE OFFSETOF(amp_hci_ACL_data_t, data) | ||
416 | |||
417 | #define HCI_ACL_DATA_BC_FLAGS (0x0 << 14) | ||
418 | #define HCI_ACL_DATA_PB_FLAGS (0x3 << 12) | ||
419 | |||
420 | #define HCI_ACL_DATA_HANDLE(handle) ((handle) & 0x0fff) | ||
421 | #define HCI_ACL_DATA_FLAGS(handle) ((handle) >> 12) | ||
422 | |||
423 | /* AMP Activity Report packet formats */ | ||
424 | typedef BWL_PRE_PACKED_STRUCT struct amp_hci_activity_report { | ||
425 | uint8 ScheduleKnown; | ||
426 | uint8 NumReports; | ||
427 | uint8 data[1]; | ||
428 | } BWL_POST_PACKED_STRUCT amp_hci_activity_report_t; | ||
429 | |||
430 | typedef BWL_PRE_PACKED_STRUCT struct amp_hci_activity_report_triple { | ||
431 | uint32 StartTime; | ||
432 | uint32 Duration; | ||
433 | uint32 Periodicity; | ||
434 | } BWL_POST_PACKED_STRUCT amp_hci_activity_report_triple_t; | ||
435 | |||
436 | #define HCI_AR_SCHEDULE_KNOWN 0x01 | ||
437 | |||
438 | |||
439 | /* This marks the end of a packed structure section. */ | ||
440 | #include <packed_section_end.h> | ||
441 | |||
442 | #endif /* _bt_amp_hci_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/eapol.h b/drivers/net/wireless/bcmdhd/include/proto/eapol.h new file mode 100644 index 00000000000..5781d1312e3 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/eapol.h | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | * 802.1x EAPOL definitions | ||
3 | * | ||
4 | * See | ||
5 | * IEEE Std 802.1X-2001 | ||
6 | * IEEE 802.1X RADIUS Usage Guidelines | ||
7 | * | ||
8 | * Copyright (C) 2002 Broadcom Corporation | ||
9 | * | ||
10 | * $Id: eapol.h,v 9.23.86.1 2010-09-02 18:09:39 Exp $ | ||
11 | */ | ||
12 | |||
13 | #ifndef _eapol_h_ | ||
14 | #define _eapol_h_ | ||
15 | |||
16 | #ifndef _TYPEDEFS_H_ | ||
17 | #include <typedefs.h> | ||
18 | #endif | ||
19 | |||
20 | /* This marks the start of a packed structure section. */ | ||
21 | #include <packed_section_start.h> | ||
22 | |||
23 | #include <bcmcrypto/aeskeywrap.h> | ||
24 | |||
25 | /* EAPOL for 802.3/Ethernet */ | ||
26 | typedef struct { | ||
27 | struct ether_header eth; /* 802.3/Ethernet header */ | ||
28 | unsigned char version; /* EAPOL protocol version */ | ||
29 | unsigned char type; /* EAPOL type */ | ||
30 | unsigned short length; /* Length of body */ | ||
31 | unsigned char body[1]; /* Body (optional) */ | ||
32 | } eapol_header_t; | ||
33 | |||
34 | #define EAPOL_HEADER_LEN 18 | ||
35 | |||
36 | /* EAPOL version */ | ||
37 | #define WPA2_EAPOL_VERSION 2 | ||
38 | #define WPA_EAPOL_VERSION 1 | ||
39 | #define LEAP_EAPOL_VERSION 1 | ||
40 | #define SES_EAPOL_VERSION 1 | ||
41 | |||
42 | /* EAPOL types */ | ||
43 | #define EAP_PACKET 0 | ||
44 | #define EAPOL_START 1 | ||
45 | #define EAPOL_LOGOFF 2 | ||
46 | #define EAPOL_KEY 3 | ||
47 | #define EAPOL_ASF 4 | ||
48 | |||
49 | /* EAPOL-Key types */ | ||
50 | #define EAPOL_RC4_KEY 1 | ||
51 | #define EAPOL_WPA2_KEY 2 /* 802.11i/WPA2 */ | ||
52 | #define EAPOL_WPA_KEY 254 /* WPA */ | ||
53 | |||
54 | /* RC4 EAPOL-Key header field sizes */ | ||
55 | #define EAPOL_KEY_REPLAY_LEN 8 | ||
56 | #define EAPOL_KEY_IV_LEN 16 | ||
57 | #define EAPOL_KEY_SIG_LEN 16 | ||
58 | |||
59 | /* RC4 EAPOL-Key */ | ||
60 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
61 | unsigned char type; /* Key Descriptor Type */ | ||
62 | unsigned short length; /* Key Length (unaligned) */ | ||
63 | unsigned char replay[EAPOL_KEY_REPLAY_LEN]; /* Replay Counter */ | ||
64 | unsigned char iv[EAPOL_KEY_IV_LEN]; /* Key IV */ | ||
65 | unsigned char index; /* Key Flags & Index */ | ||
66 | unsigned char signature[EAPOL_KEY_SIG_LEN]; /* Key Signature */ | ||
67 | unsigned char key[1]; /* Key (optional) */ | ||
68 | } BWL_POST_PACKED_STRUCT eapol_key_header_t; | ||
69 | |||
70 | #define EAPOL_KEY_HEADER_LEN 44 | ||
71 | |||
72 | /* RC4 EAPOL-Key flags */ | ||
73 | #define EAPOL_KEY_FLAGS_MASK 0x80 | ||
74 | #define EAPOL_KEY_BROADCAST 0 | ||
75 | #define EAPOL_KEY_UNICAST 0x80 | ||
76 | |||
77 | /* RC4 EAPOL-Key index */ | ||
78 | #define EAPOL_KEY_INDEX_MASK 0x7f | ||
79 | |||
80 | /* WPA/802.11i/WPA2 EAPOL-Key header field sizes */ | ||
81 | #define EAPOL_WPA_KEY_REPLAY_LEN 8 | ||
82 | #define EAPOL_WPA_KEY_NONCE_LEN 32 | ||
83 | #define EAPOL_WPA_KEY_IV_LEN 16 | ||
84 | #define EAPOL_WPA_KEY_RSC_LEN 8 | ||
85 | #define EAPOL_WPA_KEY_ID_LEN 8 | ||
86 | #define EAPOL_WPA_KEY_MIC_LEN 16 | ||
87 | #define EAPOL_WPA_KEY_DATA_LEN (EAPOL_WPA_MAX_KEY_SIZE + AKW_BLOCK_LEN) | ||
88 | #define EAPOL_WPA_MAX_KEY_SIZE 32 | ||
89 | |||
90 | /* WPA EAPOL-Key */ | ||
91 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
92 | unsigned char type; /* Key Descriptor Type */ | ||
93 | unsigned short key_info; /* Key Information (unaligned) */ | ||
94 | unsigned short key_len; /* Key Length (unaligned) */ | ||
95 | unsigned char replay[EAPOL_WPA_KEY_REPLAY_LEN]; /* Replay Counter */ | ||
96 | unsigned char nonce[EAPOL_WPA_KEY_NONCE_LEN]; /* Nonce */ | ||
97 | unsigned char iv[EAPOL_WPA_KEY_IV_LEN]; /* Key IV */ | ||
98 | unsigned char rsc[EAPOL_WPA_KEY_RSC_LEN]; /* Key RSC */ | ||
99 | unsigned char id[EAPOL_WPA_KEY_ID_LEN]; /* WPA:Key ID, 802.11i/WPA2: Reserved */ | ||
100 | unsigned char mic[EAPOL_WPA_KEY_MIC_LEN]; /* Key MIC */ | ||
101 | unsigned short data_len; /* Key Data Length */ | ||
102 | unsigned char data[EAPOL_WPA_KEY_DATA_LEN]; /* Key data */ | ||
103 | } BWL_POST_PACKED_STRUCT eapol_wpa_key_header_t; | ||
104 | |||
105 | #define EAPOL_WPA_KEY_LEN 95 | ||
106 | |||
107 | /* WPA/802.11i/WPA2 KEY KEY_INFO bits */ | ||
108 | #define WPA_KEY_DESC_V1 0x01 | ||
109 | #define WPA_KEY_DESC_V2 0x02 | ||
110 | #define WPA_KEY_DESC_V3 0x03 | ||
111 | #define WPA_KEY_PAIRWISE 0x08 | ||
112 | #define WPA_KEY_INSTALL 0x40 | ||
113 | #define WPA_KEY_ACK 0x80 | ||
114 | #define WPA_KEY_MIC 0x100 | ||
115 | #define WPA_KEY_SECURE 0x200 | ||
116 | #define WPA_KEY_ERROR 0x400 | ||
117 | #define WPA_KEY_REQ 0x800 | ||
118 | |||
119 | /* WPA-only KEY KEY_INFO bits */ | ||
120 | #define WPA_KEY_INDEX_0 0x00 | ||
121 | #define WPA_KEY_INDEX_1 0x10 | ||
122 | #define WPA_KEY_INDEX_2 0x20 | ||
123 | #define WPA_KEY_INDEX_3 0x30 | ||
124 | #define WPA_KEY_INDEX_MASK 0x30 | ||
125 | #define WPA_KEY_INDEX_SHIFT 0x04 | ||
126 | |||
127 | /* 802.11i/WPA2-only KEY KEY_INFO bits */ | ||
128 | #define WPA_KEY_ENCRYPTED_DATA 0x1000 | ||
129 | |||
130 | /* Key Data encapsulation */ | ||
131 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
132 | uint8 type; | ||
133 | uint8 length; | ||
134 | uint8 oui[3]; | ||
135 | uint8 subtype; | ||
136 | uint8 data[1]; | ||
137 | } BWL_POST_PACKED_STRUCT eapol_wpa2_encap_data_t; | ||
138 | |||
139 | #define EAPOL_WPA2_ENCAP_DATA_HDR_LEN 6 | ||
140 | |||
141 | #define WPA2_KEY_DATA_SUBTYPE_GTK 1 | ||
142 | #define WPA2_KEY_DATA_SUBTYPE_STAKEY 2 | ||
143 | #define WPA2_KEY_DATA_SUBTYPE_MAC 3 | ||
144 | #define WPA2_KEY_DATA_SUBTYPE_PMKID 4 | ||
145 | |||
146 | /* GTK encapsulation */ | ||
147 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
148 | uint8 flags; | ||
149 | uint8 reserved; | ||
150 | uint8 gtk[EAPOL_WPA_MAX_KEY_SIZE]; | ||
151 | } BWL_POST_PACKED_STRUCT eapol_wpa2_key_gtk_encap_t; | ||
152 | |||
153 | #define EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN 2 | ||
154 | |||
155 | #define WPA2_GTK_INDEX_MASK 0x03 | ||
156 | #define WPA2_GTK_INDEX_SHIFT 0x00 | ||
157 | |||
158 | #define WPA2_GTK_TRANSMIT 0x04 | ||
159 | |||
160 | /* STAKey encapsulation */ | ||
161 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
162 | uint8 reserved[2]; | ||
163 | uint8 mac[ETHER_ADDR_LEN]; | ||
164 | uint8 stakey[EAPOL_WPA_MAX_KEY_SIZE]; | ||
165 | } BWL_POST_PACKED_STRUCT eapol_wpa2_key_stakey_encap_t; | ||
166 | |||
167 | #define WPA2_KEY_DATA_PAD 0xdd | ||
168 | |||
169 | |||
170 | /* This marks the end of a packed structure section. */ | ||
171 | #include <packed_section_end.h> | ||
172 | |||
173 | #endif /* _eapol_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/ethernet.h b/drivers/net/wireless/bcmdhd/include/proto/ethernet.h new file mode 100644 index 00000000000..6a6dd14c1bb --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/ethernet.h | |||
@@ -0,0 +1,162 @@ | |||
1 | /* | ||
2 | * From FreeBSD 2.2.7: Fundamental constants relating to ethernet. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: ethernet.h,v 9.56 2009-10-15 22:54:58 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _NET_ETHERNET_H_ | ||
29 | #define _NET_ETHERNET_H_ | ||
30 | |||
31 | #ifndef _TYPEDEFS_H_ | ||
32 | #include "typedefs.h" | ||
33 | #endif | ||
34 | |||
35 | |||
36 | #include <packed_section_start.h> | ||
37 | |||
38 | |||
39 | |||
40 | #define ETHER_ADDR_LEN 6 | ||
41 | |||
42 | |||
43 | #define ETHER_TYPE_LEN 2 | ||
44 | |||
45 | |||
46 | #define ETHER_CRC_LEN 4 | ||
47 | |||
48 | |||
49 | #define ETHER_HDR_LEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) | ||
50 | |||
51 | |||
52 | #define ETHER_MIN_LEN 64 | ||
53 | |||
54 | |||
55 | #define ETHER_MIN_DATA 46 | ||
56 | |||
57 | |||
58 | #define ETHER_MAX_LEN 1518 | ||
59 | |||
60 | |||
61 | #define ETHER_MAX_DATA 1500 | ||
62 | |||
63 | |||
64 | #define ETHER_TYPE_MIN 0x0600 | ||
65 | #define ETHER_TYPE_IP 0x0800 | ||
66 | #define ETHER_TYPE_ARP 0x0806 | ||
67 | #define ETHER_TYPE_8021Q 0x8100 | ||
68 | #define ETHER_TYPE_BRCM 0x886c | ||
69 | #define ETHER_TYPE_802_1X 0x888e | ||
70 | #define ETHER_TYPE_802_1X_PREAUTH 0x88c7 | ||
71 | #define ETHER_TYPE_WAI 0x88b4 | ||
72 | |||
73 | |||
74 | |||
75 | #define ETHER_BRCM_SUBTYPE_LEN 4 | ||
76 | #define ETHER_BRCM_CRAM 1 | ||
77 | |||
78 | |||
79 | #define ETHER_DEST_OFFSET (0 * ETHER_ADDR_LEN) | ||
80 | #define ETHER_SRC_OFFSET (1 * ETHER_ADDR_LEN) | ||
81 | #define ETHER_TYPE_OFFSET (2 * ETHER_ADDR_LEN) | ||
82 | |||
83 | |||
84 | #define ETHER_IS_VALID_LEN(foo) \ | ||
85 | ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN) | ||
86 | |||
87 | #define ETHER_FILL_MCAST_ADDR_FROM_IP(ea, mgrp_ip) { \ | ||
88 | ((uint8 *)ea)[0] = 0x01; \ | ||
89 | ((uint8 *)ea)[1] = 0x00; \ | ||
90 | ((uint8 *)ea)[2] = 0x5e; \ | ||
91 | ((uint8 *)ea)[3] = ((mgrp_ip) >> 16) & 0x7f; \ | ||
92 | ((uint8 *)ea)[4] = ((mgrp_ip) >> 8) & 0xff; \ | ||
93 | ((uint8 *)ea)[5] = ((mgrp_ip) >> 0) & 0xff; \ | ||
94 | } | ||
95 | |||
96 | #ifndef __INCif_etherh | ||
97 | |||
98 | BWL_PRE_PACKED_STRUCT struct ether_header { | ||
99 | uint8 ether_dhost[ETHER_ADDR_LEN]; | ||
100 | uint8 ether_shost[ETHER_ADDR_LEN]; | ||
101 | uint16 ether_type; | ||
102 | } BWL_POST_PACKED_STRUCT; | ||
103 | |||
104 | |||
105 | BWL_PRE_PACKED_STRUCT struct ether_addr { | ||
106 | uint8 octet[ETHER_ADDR_LEN]; | ||
107 | } BWL_POST_PACKED_STRUCT; | ||
108 | #endif | ||
109 | |||
110 | |||
111 | #define ETHER_SET_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2)) | ||
112 | #define ETHER_IS_LOCALADDR(ea) (((uint8 *)(ea))[0] & 2) | ||
113 | #define ETHER_CLR_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & 0xd)) | ||
114 | #define ETHER_TOGGLE_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] ^ 2)) | ||
115 | |||
116 | |||
117 | #define ETHER_SET_UNICAST(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1)) | ||
118 | |||
119 | |||
120 | #define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1) | ||
121 | |||
122 | |||
123 | |||
124 | #define ether_cmp(a, b) (!(((short*)a)[0] == ((short*)b)[0]) | \ | ||
125 | !(((short*)a)[1] == ((short*)b)[1]) | \ | ||
126 | !(((short*)a)[2] == ((short*)b)[2])) | ||
127 | |||
128 | |||
129 | #define ether_copy(s, d) { \ | ||
130 | ((short*)d)[0] = ((short*)s)[0]; \ | ||
131 | ((short*)d)[1] = ((short*)s)[1]; \ | ||
132 | ((short*)d)[2] = ((short*)s)[2]; } | ||
133 | |||
134 | |||
135 | static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}}; | ||
136 | static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}}; | ||
137 | |||
138 | #define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \ | ||
139 | ((uint8 *)(ea))[1] & \ | ||
140 | ((uint8 *)(ea))[2] & \ | ||
141 | ((uint8 *)(ea))[3] & \ | ||
142 | ((uint8 *)(ea))[4] & \ | ||
143 | ((uint8 *)(ea))[5]) == 0xff) | ||
144 | #define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \ | ||
145 | ((uint8 *)(ea))[1] | \ | ||
146 | ((uint8 *)(ea))[2] | \ | ||
147 | ((uint8 *)(ea))[3] | \ | ||
148 | ((uint8 *)(ea))[4] | \ | ||
149 | ((uint8 *)(ea))[5]) == 0) | ||
150 | |||
151 | |||
152 | #define ETHER_MOVE_HDR(d, s) \ | ||
153 | do { \ | ||
154 | struct ether_header t; \ | ||
155 | t = *(struct ether_header *)(s); \ | ||
156 | *(struct ether_header *)(d) = t; \ | ||
157 | } while (0) | ||
158 | |||
159 | |||
160 | #include <packed_section_end.h> | ||
161 | |||
162 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/p2p.h b/drivers/net/wireless/bcmdhd/include/proto/p2p.h new file mode 100644 index 00000000000..4a0c9d1ddc3 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/p2p.h | |||
@@ -0,0 +1,512 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * | ||
22 | * Fundamental types and constants relating to WFA P2P (aka WiFi Direct) | ||
23 | * | ||
24 | * $Id: p2p.h,v 9.17.2.4 2010-12-15 21:41:21 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _P2P_H_ | ||
28 | #define _P2P_H_ | ||
29 | |||
30 | #ifndef _TYPEDEFS_H_ | ||
31 | #include <typedefs.h> | ||
32 | #endif | ||
33 | #include <wlioctl.h> | ||
34 | #include <proto/802.11.h> | ||
35 | |||
36 | /* This marks the start of a packed structure section. */ | ||
37 | #include <packed_section_start.h> | ||
38 | |||
39 | |||
40 | /* WiFi P2P OUI values */ | ||
41 | #define P2P_OUI WFA_OUI /* WiFi P2P OUI */ | ||
42 | #define P2P_VER WFA_OUI_TYPE_P2P /* P2P version: 9=WiFi P2P v1.0 */ | ||
43 | |||
44 | #define P2P_IE_ID 0xdd /* P2P IE element ID */ | ||
45 | |||
46 | /* WiFi P2P IE */ | ||
47 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_ie { | ||
48 | uint8 id; /* IE ID: 0xDD */ | ||
49 | uint8 len; /* IE length */ | ||
50 | uint8 OUI[3]; /* WiFi P2P specific OUI: P2P_OUI */ | ||
51 | uint8 oui_type; /* Identifies P2P version: P2P_VER */ | ||
52 | uint8 subelts[1]; /* variable length subelements */ | ||
53 | } BWL_POST_PACKED_STRUCT; | ||
54 | typedef struct wifi_p2p_ie wifi_p2p_ie_t; | ||
55 | |||
56 | #define P2P_IE_FIXED_LEN 6 | ||
57 | |||
58 | #define P2P_ATTR_ID_OFF 0 | ||
59 | #define P2P_ATTR_LEN_OFF 1 | ||
60 | #define P2P_ATTR_DATA_OFF 3 | ||
61 | |||
62 | #define P2P_ATTR_HDR_LEN 3 /* ID + 2-byte length field spec 1.02 */ | ||
63 | |||
64 | /* P2P IE Subelement IDs from WiFi P2P Technical Spec 1.00 */ | ||
65 | #define P2P_SEID_STATUS 0 /* Status */ | ||
66 | #define P2P_SEID_MINOR_RC 1 /* Minor Reason Code */ | ||
67 | #define P2P_SEID_P2P_INFO 2 /* P2P Capability (capabilities info) */ | ||
68 | #define P2P_SEID_DEV_ID 3 /* P2P Device ID */ | ||
69 | #define P2P_SEID_INTENT 4 /* Group Owner Intent */ | ||
70 | #define P2P_SEID_CFG_TIMEOUT 5 /* Configuration Timeout */ | ||
71 | #define P2P_SEID_CHANNEL 6 /* Channel */ | ||
72 | #define P2P_SEID_GRP_BSSID 7 /* P2P Group BSSID */ | ||
73 | #define P2P_SEID_XT_TIMING 8 /* Extended Listen Timing */ | ||
74 | #define P2P_SEID_INTINTADDR 9 /* Intended P2P Interface Address */ | ||
75 | #define P2P_SEID_P2P_MGBTY 10 /* P2P Manageability */ | ||
76 | #define P2P_SEID_CHAN_LIST 11 /* Channel List */ | ||
77 | #define P2P_SEID_ABSENCE 12 /* Notice of Absence */ | ||
78 | #define P2P_SEID_DEV_INFO 13 /* Device Info */ | ||
79 | #define P2P_SEID_GROUP_INFO 14 /* Group Info */ | ||
80 | #define P2P_SEID_GROUP_ID 15 /* Group ID */ | ||
81 | #define P2P_SEID_P2P_IF 16 /* P2P Interface */ | ||
82 | #define P2P_SEID_VNDR 221 /* Vendor-specific subelement */ | ||
83 | |||
84 | #define P2P_SE_VS_ID_SERVICES 0x1b /* BRCM proprietary subel: L2 Services */ | ||
85 | |||
86 | |||
87 | /* WiFi P2P IE subelement: P2P Capability (capabilities info) */ | ||
88 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_info_se_s { | ||
89 | uint8 eltId; /* SE ID: P2P_SEID_P2P_INFO */ | ||
90 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
91 | uint8 dev; /* Device Capability Bitmap */ | ||
92 | uint8 group; /* Group Capability Bitmap */ | ||
93 | } BWL_POST_PACKED_STRUCT; | ||
94 | typedef struct wifi_p2p_info_se_s wifi_p2p_info_se_t; | ||
95 | |||
96 | /* P2P Capability subelement's Device Capability Bitmap bit values */ | ||
97 | #define P2P_CAPSE_DEV_SERVICE_DIS 0x1 /* Service Discovery */ | ||
98 | #define P2P_CAPSE_DEV_CLIENT_DIS 0x2 /* Client Discoverability */ | ||
99 | #define P2P_CAPSE_DEV_CONCURRENT 0x4 /* Concurrent Operation */ | ||
100 | #define P2P_CAPSE_DEV_INFRA_MAN 0x8 /* P2P Infrastructure Managed */ | ||
101 | #define P2P_CAPSE_DEV_LIMIT 0x10 /* P2P Device Limit */ | ||
102 | #define P2P_CAPSE_INVITE_PROC 0x20 /* P2P Invitation Procedure */ | ||
103 | |||
104 | /* P2P Capability subelement's Group Capability Bitmap bit values */ | ||
105 | #define P2P_CAPSE_GRP_OWNER 0x1 /* P2P Group Owner */ | ||
106 | #define P2P_CAPSE_PERSIST_GRP 0x2 /* Persistent P2P Group */ | ||
107 | #define P2P_CAPSE_GRP_LIMIT 0x4 /* P2P Group Limit */ | ||
108 | #define P2P_CAPSE_GRP_INTRA_BSS 0x8 /* Intra-BSS Distribution */ | ||
109 | #define P2P_CAPSE_GRP_X_CONNECT 0x10 /* Cross Connection */ | ||
110 | #define P2P_CAPSE_GRP_PERSISTENT 0x20 /* Persistent Reconnect */ | ||
111 | #define P2P_CAPSE_GRP_FORMATION 0x40 /* Group Formation */ | ||
112 | |||
113 | |||
114 | /* WiFi P2P IE subelement: Group Owner Intent */ | ||
115 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_intent_se_s { | ||
116 | uint8 eltId; /* SE ID: P2P_SEID_INTENT */ | ||
117 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
118 | uint8 intent; /* Intent Value 0...15 (0=legacy 15=master only) */ | ||
119 | } BWL_POST_PACKED_STRUCT; | ||
120 | typedef struct wifi_p2p_intent_se_s wifi_p2p_intent_se_t; | ||
121 | |||
122 | /* WiFi P2P IE subelement: Configuration Timeout */ | ||
123 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_cfg_tmo_se_s { | ||
124 | uint8 eltId; /* SE ID: P2P_SEID_CFG_TIMEOUT */ | ||
125 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
126 | uint8 go_tmo; /* GO config timeout in units of 10 ms */ | ||
127 | uint8 client_tmo; /* Client config timeout in units of 10 ms */ | ||
128 | } BWL_POST_PACKED_STRUCT; | ||
129 | typedef struct wifi_p2p_cfg_tmo_se_s wifi_p2p_cfg_tmo_se_t; | ||
130 | |||
131 | |||
132 | /* WiFi P2P IE subelement: Status */ | ||
133 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_status_se_s { | ||
134 | uint8 eltId; /* SE ID: P2P_SEID_STATUS */ | ||
135 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
136 | uint8 status; /* Status Code: P2P_STATSE_* */ | ||
137 | } BWL_POST_PACKED_STRUCT; | ||
138 | typedef struct wifi_p2p_status_se_s wifi_p2p_status_se_t; | ||
139 | |||
140 | /* Status subelement Status Code definitions */ | ||
141 | #define P2P_STATSE_SUCCESS 0 | ||
142 | /* Success */ | ||
143 | #define P2P_STATSE_FAIL_INFO_CURR_UNAVAIL 1 | ||
144 | /* Failed, information currently unavailable */ | ||
145 | #define P2P_STATSE_PASSED_UP P2P_STATSE_FAIL_INFO_CURR_UNAVAIL | ||
146 | /* Old name for above in P2P spec 1.08 and older */ | ||
147 | #define P2P_STATSE_FAIL_INCOMPAT_PARAMS 2 | ||
148 | /* Failed, incompatible parameters */ | ||
149 | #define P2P_STATSE_FAIL_LIMIT_REACHED 3 | ||
150 | /* Failed, limit reached */ | ||
151 | #define P2P_STATSE_FAIL_INVALID_PARAMS 4 | ||
152 | /* Failed, invalid parameters */ | ||
153 | #define P2P_STATSE_FAIL_UNABLE_TO_ACCOM 5 | ||
154 | /* Failed, unable to accomodate request */ | ||
155 | #define P2P_STATSE_FAIL_PROTO_ERROR 6 | ||
156 | /* Failed, previous protocol error or disruptive behaviour */ | ||
157 | #define P2P_STATSE_FAIL_NO_COMMON_CHAN 7 | ||
158 | /* Failed, no common channels */ | ||
159 | #define P2P_STATSE_FAIL_UNKNOWN_GROUP 8 | ||
160 | /* Failed, unknown P2P Group */ | ||
161 | #define P2P_STATSE_FAIL_INTENT 9 | ||
162 | /* Failed, both peers indicated Intent 15 in GO Negotiation */ | ||
163 | #define P2P_STATSE_FAIL_INCOMPAT_PROVIS 10 | ||
164 | /* Failed, incompatible provisioning method */ | ||
165 | #define P2P_STATSE_FAIL_USER_REJECT 11 | ||
166 | /* Failed, rejected by user */ | ||
167 | |||
168 | /* WiFi P2P IE attribute: Extended Listen Timing */ | ||
169 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_ext_se_s { | ||
170 | uint8 eltId; /* ID: P2P_SEID_EXT_TIMING */ | ||
171 | uint8 len[2]; /* length not including eltId, len fields */ | ||
172 | uint8 avail[2]; /* availibility period */ | ||
173 | uint8 interval[2]; /* availibility interval */ | ||
174 | } BWL_POST_PACKED_STRUCT; | ||
175 | typedef struct wifi_p2p_ext_se_s wifi_p2p_ext_se_t; | ||
176 | |||
177 | #define P2P_EXT_MIN 10 /* minimum 10ms */ | ||
178 | |||
179 | /* WiFi P2P IE subelement: Intended P2P Interface Address */ | ||
180 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_intintad_se_s { | ||
181 | uint8 eltId; /* SE ID: P2P_SEID_INTINTADDR */ | ||
182 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
183 | uint8 mac[6]; /* intended P2P interface MAC address */ | ||
184 | } BWL_POST_PACKED_STRUCT; | ||
185 | typedef struct wifi_p2p_intintad_se_s wifi_p2p_intintad_se_t; | ||
186 | |||
187 | /* WiFi P2P IE subelement: Channel */ | ||
188 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_channel_se_s { | ||
189 | uint8 eltId; /* SE ID: P2P_SEID_STATUS */ | ||
190 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
191 | uint8 band; /* Regulatory Class (band) */ | ||
192 | uint8 channel; /* Channel */ | ||
193 | } BWL_POST_PACKED_STRUCT; | ||
194 | typedef struct wifi_p2p_channel_se_s wifi_p2p_channel_se_t; | ||
195 | |||
196 | |||
197 | /* Channel Entry structure within the Channel List SE */ | ||
198 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_entry_s { | ||
199 | uint8 band; /* Regulatory Class (band) */ | ||
200 | uint8 num_channels; /* # of channels in the channel list */ | ||
201 | uint8 channels[WL_NUMCHANNELS]; /* Channel List */ | ||
202 | } BWL_POST_PACKED_STRUCT; | ||
203 | typedef struct wifi_p2p_chanlist_entry_s wifi_p2p_chanlist_entry_t; | ||
204 | #define WIFI_P2P_CHANLIST_SE_MAX_ENTRIES 2 | ||
205 | |||
206 | /* WiFi P2P IE subelement: Channel List */ | ||
207 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_se_s { | ||
208 | uint8 eltId; /* SE ID: P2P_SEID_STATUS */ | ||
209 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
210 | uint8 country[3]; /* Country String */ | ||
211 | uint8 num_entries; /* # of channel entries */ | ||
212 | wifi_p2p_chanlist_entry_t entries[WIFI_P2P_CHANLIST_SE_MAX_ENTRIES]; | ||
213 | /* Channel Entry List */ | ||
214 | } BWL_POST_PACKED_STRUCT; | ||
215 | typedef struct wifi_p2p_chanlist_se_s wifi_p2p_chanlist_se_t; | ||
216 | |||
217 | /* WiFi P2P IE's Device Info subelement */ | ||
218 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_devinfo_se_s { | ||
219 | uint8 eltId; /* SE ID: P2P_SEID_DEVINFO */ | ||
220 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
221 | uint8 mac[6]; /* P2P Device MAC address */ | ||
222 | uint16 wps_cfg_meths; /* Config Methods: reg_prototlv.h WPS_CONFMET_* */ | ||
223 | uint8 pri_devtype[8]; /* Primary Device Type */ | ||
224 | } BWL_POST_PACKED_STRUCT; | ||
225 | typedef struct wifi_p2p_devinfo_se_s wifi_p2p_devinfo_se_t; | ||
226 | |||
227 | #define P2P_DEV_TYPE_LEN 8 | ||
228 | |||
229 | /* WiFi P2P IE's Group Info subelement Client Info Descriptor */ | ||
230 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_cid_fixed_s { | ||
231 | uint8 len; | ||
232 | uint8 devaddr[ETHER_ADDR_LEN]; /* P2P Device Address */ | ||
233 | uint8 ifaddr[ETHER_ADDR_LEN]; /* P2P Interface Address */ | ||
234 | uint8 devcap; /* Device Capability */ | ||
235 | uint8 cfg_meths[2]; /* Config Methods: reg_prototlv.h WPS_CONFMET_* */ | ||
236 | uint8 pridt[P2P_DEV_TYPE_LEN]; /* Primary Device Type */ | ||
237 | uint8 secdts; /* Number of Secondary Device Types */ | ||
238 | } BWL_POST_PACKED_STRUCT; | ||
239 | typedef struct wifi_p2p_cid_fixed_s wifi_p2p_cid_fixed_t; | ||
240 | |||
241 | /* WiFi P2P IE's Device ID subelement */ | ||
242 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_devid_se_s { | ||
243 | uint8 eltId; | ||
244 | uint8 len[2]; | ||
245 | struct ether_addr addr; /* P2P Device MAC address */ | ||
246 | } BWL_POST_PACKED_STRUCT; | ||
247 | typedef struct wifi_p2p_devid_se_s wifi_p2p_devid_se_t; | ||
248 | |||
249 | /* WiFi P2P IE subelement: P2P Manageability */ | ||
250 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_mgbt_se_s { | ||
251 | uint8 eltId; /* SE ID: P2P_SEID_P2P_MGBTY */ | ||
252 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
253 | uint8 mg_bitmap; /* manageability bitmap */ | ||
254 | } BWL_POST_PACKED_STRUCT; | ||
255 | typedef struct wifi_p2p_mgbt_se_s wifi_p2p_mgbt_se_t; | ||
256 | /* mg_bitmap field bit values */ | ||
257 | #define P2P_MGBTSE_P2PDEVMGMT_FLAG 0x1 /* AP supports Managed P2P Device */ | ||
258 | |||
259 | /* WiFi P2P IE subelement: Group Info */ | ||
260 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_grpinfo_se_s { | ||
261 | uint8 eltId; /* SE ID: P2P_SEID_GROUP_INFO */ | ||
262 | uint8 len[2]; /* SE length not including eltId, len fields */ | ||
263 | } BWL_POST_PACKED_STRUCT; | ||
264 | typedef struct wifi_p2p_grpinfo_se_s wifi_p2p_grpinfo_se_t; | ||
265 | |||
266 | |||
267 | /* WiFi P2P Action Frame */ | ||
268 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_action_frame { | ||
269 | uint8 category; /* P2P_AF_CATEGORY */ | ||
270 | uint8 OUI[3]; /* OUI - P2P_OUI */ | ||
271 | uint8 type; /* OUI Type - P2P_VER */ | ||
272 | uint8 subtype; /* OUI Subtype - P2P_AF_* */ | ||
273 | uint8 dialog_token; /* nonzero, identifies req/resp tranaction */ | ||
274 | uint8 elts[1]; /* Variable length information elements. Max size = | ||
275 | * ACTION_FRAME_SIZE - sizeof(this structure) - 1 | ||
276 | */ | ||
277 | } BWL_POST_PACKED_STRUCT; | ||
278 | typedef struct wifi_p2p_action_frame wifi_p2p_action_frame_t; | ||
279 | #define P2P_AF_CATEGORY 0x7f | ||
280 | |||
281 | #define P2P_AF_FIXED_LEN 7 | ||
282 | |||
283 | /* WiFi P2P Action Frame OUI Subtypes */ | ||
284 | #define P2P_AF_NOTICE_OF_ABSENCE 0 /* Notice of Absence */ | ||
285 | #define P2P_AF_PRESENCE_REQ 1 /* P2P Presence Request */ | ||
286 | #define P2P_AF_PRESENCE_RSP 2 /* P2P Presence Response */ | ||
287 | #define P2P_AF_GO_DISC_REQ 3 /* GO Discoverability Request */ | ||
288 | |||
289 | |||
290 | /* WiFi P2P Public Action Frame */ | ||
291 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_pub_act_frame { | ||
292 | uint8 category; /* P2P_PUB_AF_CATEGORY */ | ||
293 | uint8 action; /* P2P_PUB_AF_ACTION */ | ||
294 | uint8 oui[3]; /* P2P_OUI */ | ||
295 | uint8 oui_type; /* OUI type - P2P_VER */ | ||
296 | uint8 subtype; /* OUI subtype - P2P_TYPE_* */ | ||
297 | uint8 dialog_token; /* nonzero, identifies req/rsp transaction */ | ||
298 | uint8 elts[1]; /* Variable length information elements. Max size = | ||
299 | * ACTION_FRAME_SIZE - sizeof(this structure) - 1 | ||
300 | */ | ||
301 | } BWL_POST_PACKED_STRUCT; | ||
302 | typedef struct wifi_p2p_pub_act_frame wifi_p2p_pub_act_frame_t; | ||
303 | #define P2P_PUB_AF_FIXED_LEN 8 | ||
304 | #define P2P_PUB_AF_CATEGORY 0x04 | ||
305 | #define P2P_PUB_AF_ACTION 0x09 | ||
306 | |||
307 | /* WiFi P2P Public Action Frame OUI Subtypes */ | ||
308 | #define P2P_PAF_GON_REQ 0 /* Group Owner Negotiation Req */ | ||
309 | #define P2P_PAF_GON_RSP 1 /* Group Owner Negotiation Rsp */ | ||
310 | #define P2P_PAF_GON_CONF 2 /* Group Owner Negotiation Confirm */ | ||
311 | #define P2P_PAF_INVITE_REQ 3 /* P2P Invitation Request */ | ||
312 | #define P2P_PAF_INVITE_RSP 4 /* P2P Invitation Response */ | ||
313 | #define P2P_PAF_DEVDIS_REQ 5 /* Device Discoverability Request */ | ||
314 | #define P2P_PAF_DEVDIS_RSP 6 /* Device Discoverability Response */ | ||
315 | #define P2P_PAF_PROVDIS_REQ 7 /* Provision Discovery Request */ | ||
316 | #define P2P_PAF_PROVDIS_RSP 8 /* Provision Discovery Request */ | ||
317 | |||
318 | /* TODO: Stop using these obsolete aliases for P2P_PAF_GON_* */ | ||
319 | #define P2P_TYPE_MNREQ P2P_PAF_GON_REQ | ||
320 | #define P2P_TYPE_MNRSP P2P_PAF_GON_RSP | ||
321 | #define P2P_TYPE_MNCONF P2P_PAF_GON_CONF | ||
322 | |||
323 | /* WiFi P2P IE subelement: Notice of Absence */ | ||
324 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_desc { | ||
325 | uint8 cnt_type; /* Count/Type */ | ||
326 | uint32 duration; /* Duration */ | ||
327 | uint32 interval; /* Interval */ | ||
328 | uint32 start; /* Start Time */ | ||
329 | } BWL_POST_PACKED_STRUCT; | ||
330 | typedef struct wifi_p2p_noa_desc wifi_p2p_noa_desc_t; | ||
331 | |||
332 | BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_se { | ||
333 | uint8 eltId; /* Subelement ID */ | ||
334 | uint8 len[2]; /* Length */ | ||
335 | uint8 index; /* Index */ | ||
336 | uint8 ops_ctw_parms; /* CTWindow and OppPS Parameters */ | ||
337 | wifi_p2p_noa_desc_t desc[1]; /* Notice of Absence Descriptor(s) */ | ||
338 | } BWL_POST_PACKED_STRUCT; | ||
339 | typedef struct wifi_p2p_noa_se wifi_p2p_noa_se_t; | ||
340 | |||
341 | #define P2P_NOA_SE_FIXED_LEN 5 | ||
342 | |||
343 | /* cnt_type field values */ | ||
344 | #define P2P_NOA_DESC_CNT_RESERVED 0 /* reserved and should not be used */ | ||
345 | #define P2P_NOA_DESC_CNT_REPEAT 255 /* continuous schedule */ | ||
346 | #define P2P_NOA_DESC_TYPE_PREFERRED 1 /* preferred values */ | ||
347 | #define P2P_NOA_DESC_TYPE_ACCEPTABLE 2 /* acceptable limits */ | ||
348 | |||
349 | /* ctw_ops_parms field values */ | ||
350 | #define P2P_NOA_CTW_MASK 0x7f | ||
351 | #define P2P_NOA_OPS_MASK 0x80 | ||
352 | #define P2P_NOA_OPS_SHIFT 7 | ||
353 | |||
354 | #define P2P_CTW_MIN 10 /* minimum 10TU */ | ||
355 | |||
356 | /* | ||
357 | * P2P Service Discovery related | ||
358 | */ | ||
359 | #define P2PSD_ACTION_CATEGORY 0x04 | ||
360 | /* Public action frame */ | ||
361 | #define P2PSD_ACTION_ID_GAS_IREQ 0x0a | ||
362 | /* Action value for GAS Initial Request AF */ | ||
363 | #define P2PSD_ACTION_ID_GAS_IRESP 0x0b | ||
364 | /* Action value for GAS Initial Response AF */ | ||
365 | #define P2PSD_ACTION_ID_GAS_CREQ 0x0c | ||
366 | /* Action value for GAS Comback Request AF */ | ||
367 | #define P2PSD_ACTION_ID_GAS_CRESP 0x0d | ||
368 | /* Action value for GAS Comback Response AF */ | ||
369 | #define P2PSD_AD_EID 0x6c | ||
370 | /* Advertisement Protocol IE ID */ | ||
371 | #define P2PSD_ADP_TUPLE_QLMT_PAMEBI 0x00 | ||
372 | /* Query Response Length Limit 7 bits plus PAME-BI 1 bit */ | ||
373 | #define P2PSD_ADP_PROTO_ID 0x00 | ||
374 | /* Advertisement Protocol ID. Always 0 for P2P SD */ | ||
375 | #define P2PSD_GAS_OUI P2P_OUI | ||
376 | /* WFA OUI */ | ||
377 | #define P2PSD_GAS_OUI_SUBTYPE P2P_VER | ||
378 | /* OUI Subtype for GAS IE */ | ||
379 | #define P2PSD_GAS_NQP_INFOID 0xDDDD | ||
380 | /* NQP Query Info ID: 56797 */ | ||
381 | #define P2PSD_GAS_COMEBACKDEALY 0x00 | ||
382 | /* Not used in the Native GAS protocol */ | ||
383 | |||
384 | /* Service Protocol Type */ | ||
385 | typedef enum p2psd_svc_protype { | ||
386 | SVC_RPOTYPE_ALL = 0, | ||
387 | SVC_RPOTYPE_BONJOUR = 1, | ||
388 | SVC_RPOTYPE_UPNP = 2, | ||
389 | SVC_RPOTYPE_WSD = 3, | ||
390 | SVC_RPOTYPE_VENDOR = 255 | ||
391 | } p2psd_svc_protype_t; | ||
392 | |||
393 | /* Service Discovery response status code */ | ||
394 | typedef enum { | ||
395 | P2PSD_RESP_STATUS_SUCCESS = 0, | ||
396 | P2PSD_RESP_STATUS_PROTYPE_NA = 1, | ||
397 | P2PSD_RESP_STATUS_DATA_NA = 2, | ||
398 | P2PSD_RESP_STATUS_BAD_REQUEST = 3 | ||
399 | } p2psd_resp_status_t; | ||
400 | |||
401 | /* Advertisement Protocol IE tuple field */ | ||
402 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_tpl { | ||
403 | uint8 llm_pamebi; /* Query Response Length Limit bit 0-6, set to 0 plus | ||
404 | * Pre-Associated Message Exchange BSSID Independent bit 7, set to 0 | ||
405 | */ | ||
406 | uint8 adp_id; /* Advertisement Protocol ID: 0 for NQP Native Query Protocol */ | ||
407 | } BWL_POST_PACKED_STRUCT; | ||
408 | typedef struct wifi_p2psd_adp_tpl wifi_p2psd_adp_tpl_t; | ||
409 | |||
410 | /* Advertisement Protocol IE */ | ||
411 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_ie { | ||
412 | uint8 id; /* IE ID: 0x6c - 108 */ | ||
413 | uint8 len; /* IE length */ | ||
414 | wifi_p2psd_adp_tpl_t adp_tpl; /* Advertisement Protocol Tuple field. Only one | ||
415 | * tuple is defined for P2P Service Discovery | ||
416 | */ | ||
417 | } BWL_POST_PACKED_STRUCT; | ||
418 | typedef struct wifi_p2psd_adp_ie wifi_p2psd_adp_ie_t; | ||
419 | |||
420 | /* NQP Vendor-specific Content */ | ||
421 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_nqp_query_vsc { | ||
422 | uint8 oui_subtype; /* OUI Subtype: 0x09 */ | ||
423 | uint16 svc_updi; /* Service Update Indicator */ | ||
424 | uint8 svc_tlvs[1]; /* wifi_p2psd_qreq_tlv_t type for service request, | ||
425 | * wifi_p2psd_qresp_tlv_t type for service response | ||
426 | */ | ||
427 | } BWL_POST_PACKED_STRUCT; | ||
428 | typedef struct wifi_p2psd_nqp_query_vsc wifi_p2psd_nqp_query_vsc_t; | ||
429 | |||
430 | /* Service Request TLV */ | ||
431 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_tlv { | ||
432 | uint16 len; /* Length: 5 plus size of Query Data */ | ||
433 | uint8 svc_prot; /* Service Protocol Type */ | ||
434 | uint8 svc_tscid; /* Service Transaction ID */ | ||
435 | uint8 query_data[1]; /* Query Data, passed in from above Layer 2 */ | ||
436 | } BWL_POST_PACKED_STRUCT; | ||
437 | typedef struct wifi_p2psd_qreq_tlv wifi_p2psd_qreq_tlv_t; | ||
438 | |||
439 | /* Query Request Frame, defined in generic format, instead of NQP specific */ | ||
440 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_frame { | ||
441 | uint16 info_id; /* Info ID: 0xDDDD */ | ||
442 | uint16 len; /* Length of service request TLV, 5 plus the size of request data */ | ||
443 | uint8 oui[3]; /* WFA OUI: 0x0050F2 */ | ||
444 | uint8 qreq_vsc[1]; /* Vendor-specific Content: wifi_p2psd_nqp_query_vsc_t type for NQP */ | ||
445 | |||
446 | } BWL_POST_PACKED_STRUCT; | ||
447 | typedef struct wifi_p2psd_qreq_frame wifi_p2psd_qreq_frame_t; | ||
448 | |||
449 | /* GAS Initial Request AF body, "elts" in wifi_p2p_pub_act_frame */ | ||
450 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_ireq_frame { | ||
451 | wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */ | ||
452 | uint16 qreq_len; /* Query Request Length */ | ||
453 | uint8 qreq_frm[1]; /* Query Request Frame wifi_p2psd_qreq_frame_t */ | ||
454 | } BWL_POST_PACKED_STRUCT; | ||
455 | typedef struct wifi_p2psd_gas_ireq_frame wifi_p2psd_gas_ireq_frame_t; | ||
456 | |||
457 | /* Service Response TLV */ | ||
458 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_tlv { | ||
459 | uint16 len; /* Length: 5 plus size of Query Data */ | ||
460 | uint8 svc_prot; /* Service Protocol Type */ | ||
461 | uint8 svc_tscid; /* Service Transaction ID */ | ||
462 | uint8 status; /* Value defined in Table 57 of P2P spec. */ | ||
463 | uint8 query_data[1]; /* Response Data, passed in from above Layer 2 */ | ||
464 | } BWL_POST_PACKED_STRUCT; | ||
465 | typedef struct wifi_p2psd_qresp_tlv wifi_p2psd_qresp_tlv_t; | ||
466 | |||
467 | /* Query Response Frame, defined in generic format, instead of NQP specific */ | ||
468 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_frame { | ||
469 | uint16 info_id; /* Info ID: 0xDDDD */ | ||
470 | uint16 len; /* Lenth of service response TLV, 6 plus the size of resp data */ | ||
471 | uint8 oui[3]; /* WFA OUI: 0x0050F2 */ | ||
472 | uint8 qresp_vsc[1]; /* Vendor-specific Content: wifi_p2psd_qresp_tlv_t type for NQP */ | ||
473 | |||
474 | } BWL_POST_PACKED_STRUCT; | ||
475 | typedef struct wifi_p2psd_qresp_frame wifi_p2psd_qresp_frame_t; | ||
476 | |||
477 | /* GAS Initial Response AF body, "elts" in wifi_p2p_pub_act_frame */ | ||
478 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_iresp_frame { | ||
479 | uint16 status; /* Value defined in Table 7-23 of IEEE P802.11u */ | ||
480 | uint16 cb_delay; /* GAS Comeback Delay */ | ||
481 | wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */ | ||
482 | uint16 qresp_len; /* Query Response Length */ | ||
483 | uint8 qresp_frm[1]; /* Query Response Frame wifi_p2psd_qresp_frame_t */ | ||
484 | } BWL_POST_PACKED_STRUCT; | ||
485 | typedef struct wifi_p2psd_gas_iresp_frame wifi_p2psd_gas_iresp_frame_t; | ||
486 | |||
487 | /* GAS Comeback Response AF body, "elts" in wifi_p2p_pub_act_frame */ | ||
488 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_cresp_frame { | ||
489 | uint16 status; /* Value defined in Table 7-23 of IEEE P802.11u */ | ||
490 | uint8 fragment_id; /* Fragmentation ID */ | ||
491 | uint16 cb_delay; /* GAS Comeback Delay */ | ||
492 | wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */ | ||
493 | uint16 qresp_len; /* Query Response Length */ | ||
494 | uint8 qresp_frm[1]; /* Query Response Frame wifi_p2psd_qresp_frame_t */ | ||
495 | } BWL_POST_PACKED_STRUCT; | ||
496 | typedef struct wifi_p2psd_gas_cresp_frame wifi_p2psd_gas_cresp_frame_t; | ||
497 | |||
498 | /* Wi-Fi GAS Public Action Frame */ | ||
499 | BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_pub_act_frame { | ||
500 | uint8 category; /* 0x04 Public Action Frame */ | ||
501 | uint8 action; /* 0x6c Advertisement Protocol */ | ||
502 | uint8 dialog_token; /* nonzero, identifies req/rsp transaction */ | ||
503 | uint8 query_data[1]; /* Query Data. wifi_p2psd_gas_ireq_frame_t | ||
504 | * or wifi_p2psd_gas_iresp_frame_t format | ||
505 | */ | ||
506 | } BWL_POST_PACKED_STRUCT; | ||
507 | typedef struct wifi_p2psd_gas_pub_act_frame wifi_p2psd_gas_pub_act_frame_t; | ||
508 | |||
509 | /* This marks the end of a packed structure section. */ | ||
510 | #include <packed_section_end.h> | ||
511 | |||
512 | #endif /* _P2P_H_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/sdspi.h b/drivers/net/wireless/bcmdhd/include/proto/sdspi.h new file mode 100644 index 00000000000..7fe4fbce310 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/sdspi.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * SD-SPI Protocol Standard | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: sdspi.h,v 9.2.120.1 2010-11-15 17:56:25 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _SD_SPI_H | ||
28 | #define _SD_SPI_H | ||
29 | |||
30 | #define SPI_START_M BITFIELD_MASK(1) /* Bit [31] - Start Bit */ | ||
31 | #define SPI_START_S 31 | ||
32 | #define SPI_DIR_M BITFIELD_MASK(1) /* Bit [30] - Direction */ | ||
33 | #define SPI_DIR_S 30 | ||
34 | #define SPI_CMD_INDEX_M BITFIELD_MASK(6) /* Bits [29:24] - Command number */ | ||
35 | #define SPI_CMD_INDEX_S 24 | ||
36 | #define SPI_RW_M BITFIELD_MASK(1) /* Bit [23] - Read=0, Write=1 */ | ||
37 | #define SPI_RW_S 23 | ||
38 | #define SPI_FUNC_M BITFIELD_MASK(3) /* Bits [22:20] - Function Number */ | ||
39 | #define SPI_FUNC_S 20 | ||
40 | #define SPI_RAW_M BITFIELD_MASK(1) /* Bit [19] - Read After Wr */ | ||
41 | #define SPI_RAW_S 19 | ||
42 | #define SPI_STUFF_M BITFIELD_MASK(1) /* Bit [18] - Stuff bit */ | ||
43 | #define SPI_STUFF_S 18 | ||
44 | #define SPI_BLKMODE_M BITFIELD_MASK(1) /* Bit [19] - Blockmode 1=blk */ | ||
45 | #define SPI_BLKMODE_S 19 | ||
46 | #define SPI_OPCODE_M BITFIELD_MASK(1) /* Bit [18] - OP Code */ | ||
47 | #define SPI_OPCODE_S 18 | ||
48 | #define SPI_ADDR_M BITFIELD_MASK(17) /* Bits [17:1] - Address */ | ||
49 | #define SPI_ADDR_S 1 | ||
50 | #define SPI_STUFF0_M BITFIELD_MASK(1) /* Bit [0] - Stuff bit */ | ||
51 | #define SPI_STUFF0_S 0 | ||
52 | |||
53 | #define SPI_RSP_START_M BITFIELD_MASK(1) /* Bit [7] - Start Bit (always 0) */ | ||
54 | #define SPI_RSP_START_S 7 | ||
55 | #define SPI_RSP_PARAM_ERR_M BITFIELD_MASK(1) /* Bit [6] - Parameter Error */ | ||
56 | #define SPI_RSP_PARAM_ERR_S 6 | ||
57 | #define SPI_RSP_RFU5_M BITFIELD_MASK(1) /* Bit [5] - RFU (Always 0) */ | ||
58 | #define SPI_RSP_RFU5_S 5 | ||
59 | #define SPI_RSP_FUNC_ERR_M BITFIELD_MASK(1) /* Bit [4] - Function number error */ | ||
60 | #define SPI_RSP_FUNC_ERR_S 4 | ||
61 | #define SPI_RSP_CRC_ERR_M BITFIELD_MASK(1) /* Bit [3] - COM CRC Error */ | ||
62 | #define SPI_RSP_CRC_ERR_S 3 | ||
63 | #define SPI_RSP_ILL_CMD_M BITFIELD_MASK(1) /* Bit [2] - Illegal Command error */ | ||
64 | #define SPI_RSP_ILL_CMD_S 2 | ||
65 | #define SPI_RSP_RFU1_M BITFIELD_MASK(1) /* Bit [1] - RFU (Always 0) */ | ||
66 | #define SPI_RSP_RFU1_S 1 | ||
67 | #define SPI_RSP_IDLE_M BITFIELD_MASK(1) /* Bit [0] - In idle state */ | ||
68 | #define SPI_RSP_IDLE_S 0 | ||
69 | |||
70 | /* SD-SPI Protocol Definitions */ | ||
71 | #define SDSPI_COMMAND_LEN 6 /* Number of bytes in an SD command */ | ||
72 | #define SDSPI_START_BLOCK 0xFE /* SD Start Block Token */ | ||
73 | #define SDSPI_IDLE_PAD 0xFF /* SD-SPI idle value for MOSI */ | ||
74 | #define SDSPI_START_BIT_MASK 0x80 | ||
75 | |||
76 | #endif /* _SD_SPI_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/vlan.h b/drivers/net/wireless/bcmdhd/include/proto/vlan.h new file mode 100644 index 00000000000..07fa7e499c2 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/vlan.h | |||
@@ -0,0 +1,70 @@ | |||
1 | /* | ||
2 | * 802.1Q VLAN protocol definitions | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: vlan.h,v 9.7 2009-03-13 01:11:50 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _vlan_h_ | ||
29 | #define _vlan_h_ | ||
30 | |||
31 | #ifndef _TYPEDEFS_H_ | ||
32 | #include <typedefs.h> | ||
33 | #endif | ||
34 | |||
35 | |||
36 | #include <packed_section_start.h> | ||
37 | |||
38 | #define VLAN_VID_MASK 0xfff | ||
39 | #define VLAN_CFI_SHIFT 12 | ||
40 | #define VLAN_PRI_SHIFT 13 | ||
41 | |||
42 | #define VLAN_PRI_MASK 7 | ||
43 | |||
44 | #define VLAN_TAG_LEN 4 | ||
45 | #define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN) | ||
46 | |||
47 | #define VLAN_TPID 0x8100 | ||
48 | |||
49 | struct ethervlan_header { | ||
50 | uint8 ether_dhost[ETHER_ADDR_LEN]; | ||
51 | uint8 ether_shost[ETHER_ADDR_LEN]; | ||
52 | uint16 vlan_type; | ||
53 | uint16 vlan_tag; | ||
54 | uint16 ether_type; | ||
55 | }; | ||
56 | |||
57 | #define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN) | ||
58 | |||
59 | |||
60 | |||
61 | #include <packed_section_end.h> | ||
62 | |||
63 | #define ETHERVLAN_MOVE_HDR(d, s) \ | ||
64 | do { \ | ||
65 | struct ethervlan_header t; \ | ||
66 | t = *(struct ethervlan_header *)(s); \ | ||
67 | *(struct ethervlan_header *)(d) = t; \ | ||
68 | } while (0) | ||
69 | |||
70 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/proto/wpa.h b/drivers/net/wireless/bcmdhd/include/proto/wpa.h new file mode 100644 index 00000000000..1ff06dc7942 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/proto/wpa.h | |||
@@ -0,0 +1,160 @@ | |||
1 | /* | ||
2 | * Fundamental types and constants relating to WPA | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: wpa.h,v 1.19 2009-07-13 08:29:58 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _proto_wpa_h_ | ||
29 | #define _proto_wpa_h_ | ||
30 | |||
31 | #include <typedefs.h> | ||
32 | #include <proto/ethernet.h> | ||
33 | |||
34 | |||
35 | |||
36 | #include <packed_section_start.h> | ||
37 | |||
38 | |||
39 | |||
40 | |||
41 | #define DOT11_RC_INVALID_WPA_IE 13 | ||
42 | #define DOT11_RC_MIC_FAILURE 14 | ||
43 | #define DOT11_RC_4WH_TIMEOUT 15 | ||
44 | #define DOT11_RC_GTK_UPDATE_TIMEOUT 16 | ||
45 | #define DOT11_RC_WPA_IE_MISMATCH 17 | ||
46 | #define DOT11_RC_INVALID_MC_CIPHER 18 | ||
47 | #define DOT11_RC_INVALID_UC_CIPHER 19 | ||
48 | #define DOT11_RC_INVALID_AKMP 20 | ||
49 | #define DOT11_RC_BAD_WPA_VERSION 21 | ||
50 | #define DOT11_RC_INVALID_WPA_CAP 22 | ||
51 | #define DOT11_RC_8021X_AUTH_FAIL 23 | ||
52 | |||
53 | #define WPA2_PMKID_LEN 16 | ||
54 | |||
55 | |||
56 | typedef BWL_PRE_PACKED_STRUCT struct | ||
57 | { | ||
58 | uint8 tag; | ||
59 | uint8 length; | ||
60 | uint8 oui[3]; | ||
61 | uint8 oui_type; | ||
62 | BWL_PRE_PACKED_STRUCT struct { | ||
63 | uint8 low; | ||
64 | uint8 high; | ||
65 | } BWL_POST_PACKED_STRUCT version; | ||
66 | } BWL_POST_PACKED_STRUCT wpa_ie_fixed_t; | ||
67 | #define WPA_IE_OUITYPE_LEN 4 | ||
68 | #define WPA_IE_FIXED_LEN 8 | ||
69 | #define WPA_IE_TAG_FIXED_LEN 6 | ||
70 | |||
71 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
72 | uint8 tag; | ||
73 | uint8 length; | ||
74 | BWL_PRE_PACKED_STRUCT struct { | ||
75 | uint8 low; | ||
76 | uint8 high; | ||
77 | } BWL_POST_PACKED_STRUCT version; | ||
78 | } BWL_POST_PACKED_STRUCT wpa_rsn_ie_fixed_t; | ||
79 | #define WPA_RSN_IE_FIXED_LEN 4 | ||
80 | #define WPA_RSN_IE_TAG_FIXED_LEN 2 | ||
81 | typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN]; | ||
82 | |||
83 | |||
84 | typedef BWL_PRE_PACKED_STRUCT struct | ||
85 | { | ||
86 | uint8 oui[3]; | ||
87 | uint8 type; | ||
88 | } BWL_POST_PACKED_STRUCT wpa_suite_t, wpa_suite_mcast_t; | ||
89 | #define WPA_SUITE_LEN 4 | ||
90 | |||
91 | |||
92 | typedef BWL_PRE_PACKED_STRUCT struct | ||
93 | { | ||
94 | BWL_PRE_PACKED_STRUCT struct { | ||
95 | uint8 low; | ||
96 | uint8 high; | ||
97 | } BWL_POST_PACKED_STRUCT count; | ||
98 | wpa_suite_t list[1]; | ||
99 | } BWL_POST_PACKED_STRUCT wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t; | ||
100 | #define WPA_IE_SUITE_COUNT_LEN 2 | ||
101 | typedef BWL_PRE_PACKED_STRUCT struct | ||
102 | { | ||
103 | BWL_PRE_PACKED_STRUCT struct { | ||
104 | uint8 low; | ||
105 | uint8 high; | ||
106 | } BWL_POST_PACKED_STRUCT count; | ||
107 | wpa_pmkid_t list[1]; | ||
108 | } BWL_POST_PACKED_STRUCT wpa_pmkid_list_t; | ||
109 | |||
110 | |||
111 | #define WPA_CIPHER_NONE 0 | ||
112 | #define WPA_CIPHER_WEP_40 1 | ||
113 | #define WPA_CIPHER_TKIP 2 | ||
114 | #define WPA_CIPHER_AES_OCB 3 | ||
115 | #define WPA_CIPHER_AES_CCM 4 | ||
116 | #define WPA_CIPHER_WEP_104 5 | ||
117 | |||
118 | |||
119 | #define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \ | ||
120 | (cipher) == WPA_CIPHER_WEP_40 || \ | ||
121 | (cipher) == WPA_CIPHER_WEP_104 || \ | ||
122 | (cipher) == WPA_CIPHER_TKIP || \ | ||
123 | (cipher) == WPA_CIPHER_AES_OCB || \ | ||
124 | (cipher) == WPA_CIPHER_AES_CCM) | ||
125 | |||
126 | |||
127 | #define WPA_TKIP_CM_DETECT 60 | ||
128 | #define WPA_TKIP_CM_BLOCK 60 | ||
129 | |||
130 | |||
131 | #define RSN_CAP_LEN 2 | ||
132 | |||
133 | |||
134 | #define RSN_CAP_PREAUTH 0x0001 | ||
135 | #define RSN_CAP_NOPAIRWISE 0x0002 | ||
136 | #define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C | ||
137 | #define RSN_CAP_PTK_REPLAY_CNTR_SHIFT 2 | ||
138 | #define RSN_CAP_GTK_REPLAY_CNTR_MASK 0x0030 | ||
139 | #define RSN_CAP_GTK_REPLAY_CNTR_SHIFT 4 | ||
140 | #define RSN_CAP_1_REPLAY_CNTR 0 | ||
141 | #define RSN_CAP_2_REPLAY_CNTRS 1 | ||
142 | #define RSN_CAP_4_REPLAY_CNTRS 2 | ||
143 | #define RSN_CAP_16_REPLAY_CNTRS 3 | ||
144 | |||
145 | |||
146 | #define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS | ||
147 | #define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS | ||
148 | #define WPA_CAP_REPLAY_CNTR_SHIFT RSN_CAP_PTK_REPLAY_CNTR_SHIFT | ||
149 | #define WPA_CAP_REPLAY_CNTR_MASK RSN_CAP_PTK_REPLAY_CNTR_MASK | ||
150 | |||
151 | |||
152 | #define WPA_CAP_LEN RSN_CAP_LEN | ||
153 | |||
154 | #define WPA_CAP_WPA2_PREAUTH RSN_CAP_PREAUTH | ||
155 | |||
156 | |||
157 | |||
158 | #include <packed_section_end.h> | ||
159 | |||
160 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbchipc.h b/drivers/net/wireless/bcmdhd/include/sbchipc.h new file mode 100644 index 00000000000..cbd37490f1c --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbchipc.h | |||
@@ -0,0 +1,1615 @@ | |||
1 | /* | ||
2 | * SiliconBackplane Chipcommon core hardware definitions. | ||
3 | * | ||
4 | * The chipcommon core provides chip identification, SB control, | ||
5 | * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, | ||
6 | * GPIO interface, extbus, and support for serial and parallel flashes. | ||
7 | * | ||
8 | * $Id: sbchipc.h,v 13.169.2.14 2011-02-10 23:43:55 Exp $ | ||
9 | * | ||
10 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
11 | * | ||
12 | * Unless you and Broadcom execute a separate written software license | ||
13 | * agreement governing use of this software, this software is licensed to you | ||
14 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
15 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
16 | * following added to such license: | ||
17 | * | ||
18 | * As a special exception, the copyright holders of this software give you | ||
19 | * permission to link this software with independent modules, and to copy and | ||
20 | * distribute the resulting executable under terms of your choice, provided that | ||
21 | * you also meet, for each linked independent module, the terms and conditions of | ||
22 | * the license of that module. An independent module is a module which is not | ||
23 | * derived from this software. The special exception does not apply to any | ||
24 | * modifications of the software. | ||
25 | * | ||
26 | * Notwithstanding the above, under no circumstances may you combine this | ||
27 | * software in any way with any other Broadcom software provided under a license | ||
28 | * other than the GPL, without Broadcom's express prior written consent. | ||
29 | */ | ||
30 | |||
31 | |||
32 | #ifndef _SBCHIPC_H | ||
33 | #define _SBCHIPC_H | ||
34 | |||
35 | #ifndef _LANGUAGE_ASSEMBLY | ||
36 | |||
37 | |||
38 | #ifndef PAD | ||
39 | #define _PADLINE(line) pad ## line | ||
40 | #define _XSTR(line) _PADLINE(line) | ||
41 | #define PAD _XSTR(__LINE__) | ||
42 | #endif | ||
43 | |||
44 | typedef volatile struct { | ||
45 | uint32 chipid; | ||
46 | uint32 capabilities; | ||
47 | uint32 corecontrol; | ||
48 | uint32 bist; | ||
49 | |||
50 | |||
51 | uint32 otpstatus; | ||
52 | uint32 otpcontrol; | ||
53 | uint32 otpprog; | ||
54 | uint32 otplayout; | ||
55 | |||
56 | |||
57 | uint32 intstatus; | ||
58 | uint32 intmask; | ||
59 | |||
60 | |||
61 | uint32 chipcontrol; | ||
62 | uint32 chipstatus; | ||
63 | |||
64 | |||
65 | uint32 jtagcmd; | ||
66 | uint32 jtagir; | ||
67 | uint32 jtagdr; | ||
68 | uint32 jtagctrl; | ||
69 | |||
70 | |||
71 | uint32 flashcontrol; | ||
72 | uint32 flashaddress; | ||
73 | uint32 flashdata; | ||
74 | uint32 PAD[1]; | ||
75 | |||
76 | |||
77 | uint32 broadcastaddress; | ||
78 | uint32 broadcastdata; | ||
79 | |||
80 | |||
81 | uint32 gpiopullup; | ||
82 | uint32 gpiopulldown; | ||
83 | uint32 gpioin; | ||
84 | uint32 gpioout; | ||
85 | uint32 gpioouten; | ||
86 | uint32 gpiocontrol; | ||
87 | uint32 gpiointpolarity; | ||
88 | uint32 gpiointmask; | ||
89 | |||
90 | |||
91 | uint32 gpioevent; | ||
92 | uint32 gpioeventintmask; | ||
93 | |||
94 | |||
95 | uint32 watchdog; | ||
96 | |||
97 | |||
98 | uint32 gpioeventintpolarity; | ||
99 | |||
100 | |||
101 | uint32 gpiotimerval; | ||
102 | uint32 gpiotimeroutmask; | ||
103 | |||
104 | |||
105 | uint32 clockcontrol_n; | ||
106 | uint32 clockcontrol_sb; | ||
107 | uint32 clockcontrol_pci; | ||
108 | uint32 clockcontrol_m2; | ||
109 | uint32 clockcontrol_m3; | ||
110 | uint32 clkdiv; | ||
111 | uint32 gpiodebugsel; | ||
112 | uint32 capabilities_ext; | ||
113 | |||
114 | |||
115 | uint32 pll_on_delay; | ||
116 | uint32 fref_sel_delay; | ||
117 | uint32 slow_clk_ctl; | ||
118 | uint32 PAD; | ||
119 | |||
120 | |||
121 | uint32 system_clk_ctl; | ||
122 | uint32 clkstatestretch; | ||
123 | uint32 PAD[2]; | ||
124 | |||
125 | |||
126 | uint32 bp_addrlow; | ||
127 | uint32 bp_addrhigh; | ||
128 | uint32 bp_data; | ||
129 | uint32 PAD; | ||
130 | uint32 bp_indaccess; | ||
131 | |||
132 | uint32 gsioctrl; | ||
133 | uint32 gsioaddress; | ||
134 | uint32 gsiodata; | ||
135 | |||
136 | |||
137 | uint32 clkdiv2; | ||
138 | uint32 PAD[2]; | ||
139 | |||
140 | |||
141 | uint32 eromptr; | ||
142 | |||
143 | |||
144 | uint32 pcmcia_config; | ||
145 | uint32 pcmcia_memwait; | ||
146 | uint32 pcmcia_attrwait; | ||
147 | uint32 pcmcia_iowait; | ||
148 | uint32 ide_config; | ||
149 | uint32 ide_memwait; | ||
150 | uint32 ide_attrwait; | ||
151 | uint32 ide_iowait; | ||
152 | uint32 prog_config; | ||
153 | uint32 prog_waitcount; | ||
154 | uint32 flash_config; | ||
155 | uint32 flash_waitcount; | ||
156 | uint32 PAD[4]; | ||
157 | uint32 PAD[40]; | ||
158 | |||
159 | |||
160 | |||
161 | uint32 clk_ctl_st; | ||
162 | uint32 hw_war; | ||
163 | uint32 PAD[70]; | ||
164 | |||
165 | |||
166 | uint8 uart0data; | ||
167 | uint8 uart0imr; | ||
168 | uint8 uart0fcr; | ||
169 | uint8 uart0lcr; | ||
170 | uint8 uart0mcr; | ||
171 | uint8 uart0lsr; | ||
172 | uint8 uart0msr; | ||
173 | uint8 uart0scratch; | ||
174 | uint8 PAD[248]; | ||
175 | |||
176 | uint8 uart1data; | ||
177 | uint8 uart1imr; | ||
178 | uint8 uart1fcr; | ||
179 | uint8 uart1lcr; | ||
180 | uint8 uart1mcr; | ||
181 | uint8 uart1lsr; | ||
182 | uint8 uart1msr; | ||
183 | uint8 uart1scratch; | ||
184 | uint32 PAD[126]; | ||
185 | |||
186 | |||
187 | |||
188 | uint32 pmucontrol; | ||
189 | uint32 pmucapabilities; | ||
190 | uint32 pmustatus; | ||
191 | uint32 res_state; | ||
192 | uint32 res_pending; | ||
193 | uint32 pmutimer; | ||
194 | uint32 min_res_mask; | ||
195 | uint32 max_res_mask; | ||
196 | uint32 res_table_sel; | ||
197 | uint32 res_dep_mask; | ||
198 | uint32 res_updn_timer; | ||
199 | uint32 res_timer; | ||
200 | uint32 clkstretch; | ||
201 | uint32 pmuwatchdog; | ||
202 | uint32 gpiosel; | ||
203 | uint32 gpioenable; | ||
204 | uint32 res_req_timer_sel; | ||
205 | uint32 res_req_timer; | ||
206 | uint32 res_req_mask; | ||
207 | uint32 PAD; | ||
208 | uint32 chipcontrol_addr; | ||
209 | uint32 chipcontrol_data; | ||
210 | uint32 regcontrol_addr; | ||
211 | uint32 regcontrol_data; | ||
212 | uint32 pllcontrol_addr; | ||
213 | uint32 pllcontrol_data; | ||
214 | uint32 pmustrapopt; | ||
215 | uint32 pmu_xtalfreq; | ||
216 | uint32 PAD[100]; | ||
217 | uint16 sromotp[768]; | ||
218 | } chipcregs_t; | ||
219 | |||
220 | #endif | ||
221 | |||
222 | |||
223 | #define CC_CHIPID 0 | ||
224 | #define CC_CAPABILITIES 4 | ||
225 | #define CC_CHIPST 0x2c | ||
226 | #define CC_EROMPTR 0xfc | ||
227 | |||
228 | |||
229 | #define CC_OTPST 0x10 | ||
230 | #define CC_JTAGCMD 0x30 | ||
231 | #define CC_JTAGIR 0x34 | ||
232 | #define CC_JTAGDR 0x38 | ||
233 | #define CC_JTAGCTRL 0x3c | ||
234 | #define CC_GPIOPU 0x58 | ||
235 | #define CC_GPIOPD 0x5c | ||
236 | #define CC_GPIOIN 0x60 | ||
237 | #define CC_GPIOOUT 0x64 | ||
238 | #define CC_GPIOOUTEN 0x68 | ||
239 | #define CC_GPIOCTRL 0x6c | ||
240 | #define CC_GPIOPOL 0x70 | ||
241 | #define CC_GPIOINTM 0x74 | ||
242 | #define CC_WATCHDOG 0x80 | ||
243 | #define CC_CLKC_N 0x90 | ||
244 | #define CC_CLKC_M0 0x94 | ||
245 | #define CC_CLKC_M1 0x98 | ||
246 | #define CC_CLKC_M2 0x9c | ||
247 | #define CC_CLKC_M3 0xa0 | ||
248 | #define CC_CLKDIV 0xa4 | ||
249 | #define CC_SYS_CLK_CTL 0xc0 | ||
250 | #define CC_CLK_CTL_ST SI_CLK_CTL_ST | ||
251 | #define PMU_CTL 0x600 | ||
252 | #define PMU_CAP 0x604 | ||
253 | #define PMU_ST 0x608 | ||
254 | #define PMU_RES_STATE 0x60c | ||
255 | #define PMU_TIMER 0x614 | ||
256 | #define PMU_MIN_RES_MASK 0x618 | ||
257 | #define PMU_MAX_RES_MASK 0x61c | ||
258 | #define CC_CHIPCTL_ADDR 0x650 | ||
259 | #define CC_CHIPCTL_DATA 0x654 | ||
260 | #define PMU_REG_CONTROL_ADDR 0x658 | ||
261 | #define PMU_REG_CONTROL_DATA 0x65C | ||
262 | #define PMU_PLL_CONTROL_ADDR 0x660 | ||
263 | #define PMU_PLL_CONTROL_DATA 0x664 | ||
264 | #define CC_SROM_OTP 0x800 | ||
265 | |||
266 | |||
267 | #define CID_ID_MASK 0x0000ffff | ||
268 | #define CID_REV_MASK 0x000f0000 | ||
269 | #define CID_REV_SHIFT 16 | ||
270 | #define CID_PKG_MASK 0x00f00000 | ||
271 | #define CID_PKG_SHIFT 20 | ||
272 | #define CID_CC_MASK 0x0f000000 | ||
273 | #define CID_CC_SHIFT 24 | ||
274 | #define CID_TYPE_MASK 0xf0000000 | ||
275 | #define CID_TYPE_SHIFT 28 | ||
276 | |||
277 | |||
278 | #define CC_CAP_UARTS_MASK 0x00000003 | ||
279 | #define CC_CAP_MIPSEB 0x00000004 | ||
280 | #define CC_CAP_UCLKSEL 0x00000018 | ||
281 | #define CC_CAP_UINTCLK 0x00000008 | ||
282 | #define CC_CAP_UARTGPIO 0x00000020 | ||
283 | #define CC_CAP_EXTBUS_MASK 0x000000c0 | ||
284 | #define CC_CAP_EXTBUS_NONE 0x00000000 | ||
285 | #define CC_CAP_EXTBUS_FULL 0x00000040 | ||
286 | #define CC_CAP_EXTBUS_PROG 0x00000080 | ||
287 | #define CC_CAP_FLASH_MASK 0x00000700 | ||
288 | #define CC_CAP_PLL_MASK 0x00038000 | ||
289 | #define CC_CAP_PWR_CTL 0x00040000 | ||
290 | #define CC_CAP_OTPSIZE 0x00380000 | ||
291 | #define CC_CAP_OTPSIZE_SHIFT 19 | ||
292 | #define CC_CAP_OTPSIZE_BASE 5 | ||
293 | #define CC_CAP_JTAGP 0x00400000 | ||
294 | #define CC_CAP_ROM 0x00800000 | ||
295 | #define CC_CAP_BKPLN64 0x08000000 | ||
296 | #define CC_CAP_PMU 0x10000000 | ||
297 | #define CC_CAP_ECI 0x20000000 | ||
298 | #define CC_CAP_SROM 0x40000000 | ||
299 | #define CC_CAP_NFLASH 0x80000000 | ||
300 | |||
301 | #define CC_CAP2_SECI 0x00000001 | ||
302 | #define CC_CAP2_GSIO 0x00000002 | ||
303 | |||
304 | |||
305 | #define CC_CAP_EXT_SECI_PRESENT 0x00000001 | ||
306 | |||
307 | |||
308 | #define PLL_NONE 0x00000000 | ||
309 | #define PLL_TYPE1 0x00010000 | ||
310 | #define PLL_TYPE2 0x00020000 | ||
311 | #define PLL_TYPE3 0x00030000 | ||
312 | #define PLL_TYPE4 0x00008000 | ||
313 | #define PLL_TYPE5 0x00018000 | ||
314 | #define PLL_TYPE6 0x00028000 | ||
315 | #define PLL_TYPE7 0x00038000 | ||
316 | |||
317 | |||
318 | #define ILP_CLOCK 32000 | ||
319 | |||
320 | |||
321 | #define ALP_CLOCK 20000000 | ||
322 | |||
323 | |||
324 | #define HT_CLOCK 80000000 | ||
325 | |||
326 | |||
327 | #define CC_UARTCLKO 0x00000001 | ||
328 | #define CC_SE 0x00000002 | ||
329 | #define CC_ASYNCGPIO 0x00000004 | ||
330 | #define CC_UARTCLKEN 0x00000008 | ||
331 | |||
332 | |||
333 | #define CHIPCTRL_4321A0_DEFAULT 0x3a4 | ||
334 | #define CHIPCTRL_4321A1_DEFAULT 0x0a4 | ||
335 | #define CHIPCTRL_4321_PLL_DOWN 0x800000 | ||
336 | |||
337 | |||
338 | #define OTPS_OL_MASK 0x000000ff | ||
339 | #define OTPS_OL_MFG 0x00000001 | ||
340 | #define OTPS_OL_OR1 0x00000002 | ||
341 | #define OTPS_OL_OR2 0x00000004 | ||
342 | #define OTPS_OL_GU 0x00000008 | ||
343 | #define OTPS_GUP_MASK 0x00000f00 | ||
344 | #define OTPS_GUP_SHIFT 8 | ||
345 | #define OTPS_GUP_HW 0x00000100 | ||
346 | #define OTPS_GUP_SW 0x00000200 | ||
347 | #define OTPS_GUP_CI 0x00000400 | ||
348 | #define OTPS_GUP_FUSE 0x00000800 | ||
349 | #define OTPS_READY 0x00001000 | ||
350 | #define OTPS_RV(x) (1 << (16 + (x))) | ||
351 | #define OTPS_RV_MASK 0x0fff0000 | ||
352 | |||
353 | |||
354 | #define OTPC_PROGSEL 0x00000001 | ||
355 | #define OTPC_PCOUNT_MASK 0x0000000e | ||
356 | #define OTPC_PCOUNT_SHIFT 1 | ||
357 | #define OTPC_VSEL_MASK 0x000000f0 | ||
358 | #define OTPC_VSEL_SHIFT 4 | ||
359 | #define OTPC_TMM_MASK 0x00000700 | ||
360 | #define OTPC_TMM_SHIFT 8 | ||
361 | #define OTPC_ODM 0x00000800 | ||
362 | #define OTPC_PROGEN 0x80000000 | ||
363 | |||
364 | |||
365 | #define OTPP_COL_MASK 0x000000ff | ||
366 | #define OTPP_COL_SHIFT 0 | ||
367 | #define OTPP_ROW_MASK 0x0000ff00 | ||
368 | #define OTPP_ROW_SHIFT 8 | ||
369 | #define OTPP_OC_MASK 0x0f000000 | ||
370 | #define OTPP_OC_SHIFT 24 | ||
371 | #define OTPP_READERR 0x10000000 | ||
372 | #define OTPP_VALUE_MASK 0x20000000 | ||
373 | #define OTPP_VALUE_SHIFT 29 | ||
374 | #define OTPP_START_BUSY 0x80000000 | ||
375 | #define OTPP_READ 0x40000000 | ||
376 | |||
377 | |||
378 | #define OTP_CISFORMAT_NEW 0x80000000 | ||
379 | |||
380 | |||
381 | #define OTPPOC_READ 0 | ||
382 | #define OTPPOC_BIT_PROG 1 | ||
383 | #define OTPPOC_VERIFY 3 | ||
384 | #define OTPPOC_INIT 4 | ||
385 | #define OTPPOC_SET 5 | ||
386 | #define OTPPOC_RESET 6 | ||
387 | #define OTPPOC_OCST 7 | ||
388 | #define OTPPOC_ROW_LOCK 8 | ||
389 | #define OTPPOC_PRESCN_TEST 9 | ||
390 | |||
391 | |||
392 | |||
393 | #define JTAGM_CREV_OLD 10 | ||
394 | #define JTAGM_CREV_IRP 22 | ||
395 | #define JTAGM_CREV_RTI 28 | ||
396 | |||
397 | |||
398 | #define JCMD_START 0x80000000 | ||
399 | #define JCMD_BUSY 0x80000000 | ||
400 | #define JCMD_STATE_MASK 0x60000000 | ||
401 | #define JCMD_STATE_TLR 0x00000000 | ||
402 | #define JCMD_STATE_PIR 0x20000000 | ||
403 | #define JCMD_STATE_PDR 0x40000000 | ||
404 | #define JCMD_STATE_RTI 0x60000000 | ||
405 | #define JCMD0_ACC_MASK 0x0000f000 | ||
406 | #define JCMD0_ACC_IRDR 0x00000000 | ||
407 | #define JCMD0_ACC_DR 0x00001000 | ||
408 | #define JCMD0_ACC_IR 0x00002000 | ||
409 | #define JCMD0_ACC_RESET 0x00003000 | ||
410 | #define JCMD0_ACC_IRPDR 0x00004000 | ||
411 | #define JCMD0_ACC_PDR 0x00005000 | ||
412 | #define JCMD0_IRW_MASK 0x00000f00 | ||
413 | #define JCMD_ACC_MASK 0x000f0000 | ||
414 | #define JCMD_ACC_IRDR 0x00000000 | ||
415 | #define JCMD_ACC_DR 0x00010000 | ||
416 | #define JCMD_ACC_IR 0x00020000 | ||
417 | #define JCMD_ACC_RESET 0x00030000 | ||
418 | #define JCMD_ACC_IRPDR 0x00040000 | ||
419 | #define JCMD_ACC_PDR 0x00050000 | ||
420 | #define JCMD_ACC_PIR 0x00060000 | ||
421 | #define JCMD_ACC_IRDR_I 0x00070000 | ||
422 | #define JCMD_ACC_DR_I 0x00080000 | ||
423 | #define JCMD_IRW_MASK 0x00001f00 | ||
424 | #define JCMD_IRW_SHIFT 8 | ||
425 | #define JCMD_DRW_MASK 0x0000003f | ||
426 | |||
427 | |||
428 | #define JCTRL_FORCE_CLK 4 | ||
429 | #define JCTRL_EXT_EN 2 | ||
430 | #define JCTRL_EN 1 | ||
431 | |||
432 | |||
433 | #define CLKD_SFLASH 0x0f000000 | ||
434 | #define CLKD_SFLASH_SHIFT 24 | ||
435 | #define CLKD_OTP 0x000f0000 | ||
436 | #define CLKD_OTP_SHIFT 16 | ||
437 | #define CLKD_JTAG 0x00000f00 | ||
438 | #define CLKD_JTAG_SHIFT 8 | ||
439 | #define CLKD_UART 0x000000ff | ||
440 | |||
441 | #define CLKD2_SROM 0x00000003 | ||
442 | |||
443 | |||
444 | #define CI_GPIO 0x00000001 | ||
445 | #define CI_EI 0x00000002 | ||
446 | #define CI_TEMP 0x00000004 | ||
447 | #define CI_SIRQ 0x00000008 | ||
448 | #define CI_ECI 0x00000010 | ||
449 | #define CI_PMU 0x00000020 | ||
450 | #define CI_UART 0x00000040 | ||
451 | #define CI_WDRESET 0x80000000 | ||
452 | |||
453 | |||
454 | #define SCC_SS_MASK 0x00000007 | ||
455 | #define SCC_SS_LPO 0x00000000 | ||
456 | #define SCC_SS_XTAL 0x00000001 | ||
457 | #define SCC_SS_PCI 0x00000002 | ||
458 | #define SCC_LF 0x00000200 | ||
459 | #define SCC_LP 0x00000400 | ||
460 | #define SCC_FS 0x00000800 | ||
461 | #define SCC_IP 0x00001000 | ||
462 | #define SCC_XC 0x00002000 | ||
463 | #define SCC_XP 0x00004000 | ||
464 | #define SCC_CD_MASK 0xffff0000 | ||
465 | #define SCC_CD_SHIFT 16 | ||
466 | |||
467 | |||
468 | #define SYCC_IE 0x00000001 | ||
469 | #define SYCC_AE 0x00000002 | ||
470 | #define SYCC_FP 0x00000004 | ||
471 | #define SYCC_AR 0x00000008 | ||
472 | #define SYCC_HR 0x00000010 | ||
473 | #define SYCC_CD_MASK 0xffff0000 | ||
474 | #define SYCC_CD_SHIFT 16 | ||
475 | |||
476 | |||
477 | #define BPIA_BYTEEN 0x0000000f | ||
478 | #define BPIA_SZ1 0x00000001 | ||
479 | #define BPIA_SZ2 0x00000003 | ||
480 | #define BPIA_SZ4 0x00000007 | ||
481 | #define BPIA_SZ8 0x0000000f | ||
482 | #define BPIA_WRITE 0x00000100 | ||
483 | #define BPIA_START 0x00000200 | ||
484 | #define BPIA_BUSY 0x00000200 | ||
485 | #define BPIA_ERROR 0x00000400 | ||
486 | |||
487 | |||
488 | #define CF_EN 0x00000001 | ||
489 | #define CF_EM_MASK 0x0000000e | ||
490 | #define CF_EM_SHIFT 1 | ||
491 | #define CF_EM_FLASH 0 | ||
492 | #define CF_EM_SYNC 2 | ||
493 | #define CF_EM_PCMCIA 4 | ||
494 | #define CF_DS 0x00000010 | ||
495 | #define CF_BS 0x00000020 | ||
496 | #define CF_CD_MASK 0x000000c0 | ||
497 | #define CF_CD_SHIFT 6 | ||
498 | #define CF_CD_DIV2 0x00000000 | ||
499 | #define CF_CD_DIV3 0x00000040 | ||
500 | #define CF_CD_DIV4 0x00000080 | ||
501 | #define CF_CE 0x00000100 | ||
502 | #define CF_SB 0x00000200 | ||
503 | |||
504 | |||
505 | #define PM_W0_MASK 0x0000003f | ||
506 | #define PM_W1_MASK 0x00001f00 | ||
507 | #define PM_W1_SHIFT 8 | ||
508 | #define PM_W2_MASK 0x001f0000 | ||
509 | #define PM_W2_SHIFT 16 | ||
510 | #define PM_W3_MASK 0x1f000000 | ||
511 | #define PM_W3_SHIFT 24 | ||
512 | |||
513 | |||
514 | #define PA_W0_MASK 0x0000003f | ||
515 | #define PA_W1_MASK 0x00001f00 | ||
516 | #define PA_W1_SHIFT 8 | ||
517 | #define PA_W2_MASK 0x001f0000 | ||
518 | #define PA_W2_SHIFT 16 | ||
519 | #define PA_W3_MASK 0x1f000000 | ||
520 | #define PA_W3_SHIFT 24 | ||
521 | |||
522 | |||
523 | #define PI_W0_MASK 0x0000003f | ||
524 | #define PI_W1_MASK 0x00001f00 | ||
525 | #define PI_W1_SHIFT 8 | ||
526 | #define PI_W2_MASK 0x001f0000 | ||
527 | #define PI_W2_SHIFT 16 | ||
528 | #define PI_W3_MASK 0x1f000000 | ||
529 | #define PI_W3_SHIFT 24 | ||
530 | |||
531 | |||
532 | #define PW_W0_MASK 0x0000001f | ||
533 | #define PW_W1_MASK 0x00001f00 | ||
534 | #define PW_W1_SHIFT 8 | ||
535 | #define PW_W2_MASK 0x001f0000 | ||
536 | #define PW_W2_SHIFT 16 | ||
537 | #define PW_W3_MASK 0x1f000000 | ||
538 | #define PW_W3_SHIFT 24 | ||
539 | |||
540 | #define PW_W0 0x0000000c | ||
541 | #define PW_W1 0x00000a00 | ||
542 | #define PW_W2 0x00020000 | ||
543 | #define PW_W3 0x01000000 | ||
544 | |||
545 | |||
546 | #define FW_W0_MASK 0x0000003f | ||
547 | #define FW_W1_MASK 0x00001f00 | ||
548 | #define FW_W1_SHIFT 8 | ||
549 | #define FW_W2_MASK 0x001f0000 | ||
550 | #define FW_W2_SHIFT 16 | ||
551 | #define FW_W3_MASK 0x1f000000 | ||
552 | #define FW_W3_SHIFT 24 | ||
553 | |||
554 | |||
555 | #define SRC_START 0x80000000 | ||
556 | #define SRC_BUSY 0x80000000 | ||
557 | #define SRC_OPCODE 0x60000000 | ||
558 | #define SRC_OP_READ 0x00000000 | ||
559 | #define SRC_OP_WRITE 0x20000000 | ||
560 | #define SRC_OP_WRDIS 0x40000000 | ||
561 | #define SRC_OP_WREN 0x60000000 | ||
562 | #define SRC_OTPSEL 0x00000010 | ||
563 | #define SRC_LOCK 0x00000008 | ||
564 | #define SRC_SIZE_MASK 0x00000006 | ||
565 | #define SRC_SIZE_1K 0x00000000 | ||
566 | #define SRC_SIZE_4K 0x00000002 | ||
567 | #define SRC_SIZE_16K 0x00000004 | ||
568 | #define SRC_SIZE_SHIFT 1 | ||
569 | #define SRC_PRESENT 0x00000001 | ||
570 | |||
571 | |||
572 | #define PCTL_ILP_DIV_MASK 0xffff0000 | ||
573 | #define PCTL_ILP_DIV_SHIFT 16 | ||
574 | #define PCTL_PLL_PLLCTL_UPD 0x00000400 | ||
575 | #define PCTL_NOILP_ON_WAIT 0x00000200 | ||
576 | #define PCTL_HT_REQ_EN 0x00000100 | ||
577 | #define PCTL_ALP_REQ_EN 0x00000080 | ||
578 | #define PCTL_XTALFREQ_MASK 0x0000007c | ||
579 | #define PCTL_XTALFREQ_SHIFT 2 | ||
580 | #define PCTL_ILP_DIV_EN 0x00000002 | ||
581 | #define PCTL_LPO_SEL 0x00000001 | ||
582 | |||
583 | |||
584 | #define CSTRETCH_HT 0xffff0000 | ||
585 | #define CSTRETCH_ALP 0x0000ffff | ||
586 | |||
587 | |||
588 | #define GPIO_ONTIME_SHIFT 16 | ||
589 | |||
590 | |||
591 | #define CN_N1_MASK 0x3f | ||
592 | #define CN_N2_MASK 0x3f00 | ||
593 | #define CN_N2_SHIFT 8 | ||
594 | #define CN_PLLC_MASK 0xf0000 | ||
595 | #define CN_PLLC_SHIFT 16 | ||
596 | |||
597 | |||
598 | #define CC_M1_MASK 0x3f | ||
599 | #define CC_M2_MASK 0x3f00 | ||
600 | #define CC_M2_SHIFT 8 | ||
601 | #define CC_M3_MASK 0x3f0000 | ||
602 | #define CC_M3_SHIFT 16 | ||
603 | #define CC_MC_MASK 0x1f000000 | ||
604 | #define CC_MC_SHIFT 24 | ||
605 | |||
606 | |||
607 | #define CC_F6_2 0x02 | ||
608 | #define CC_F6_3 0x03 | ||
609 | #define CC_F6_4 0x05 | ||
610 | #define CC_F6_5 0x09 | ||
611 | #define CC_F6_6 0x11 | ||
612 | #define CC_F6_7 0x21 | ||
613 | |||
614 | #define CC_F5_BIAS 5 | ||
615 | |||
616 | #define CC_MC_BYPASS 0x08 | ||
617 | #define CC_MC_M1 0x04 | ||
618 | #define CC_MC_M1M2 0x02 | ||
619 | #define CC_MC_M1M2M3 0x01 | ||
620 | #define CC_MC_M1M3 0x11 | ||
621 | |||
622 | |||
623 | #define CC_T2_BIAS 2 | ||
624 | #define CC_T2M2_BIAS 3 | ||
625 | |||
626 | #define CC_T2MC_M1BYP 1 | ||
627 | #define CC_T2MC_M2BYP 2 | ||
628 | #define CC_T2MC_M3BYP 4 | ||
629 | |||
630 | |||
631 | #define CC_T6_MMASK 1 | ||
632 | #define CC_T6_M0 120000000 | ||
633 | #define CC_T6_M1 100000000 | ||
634 | #define SB2MIPS_T6(sb) (2 * (sb)) | ||
635 | |||
636 | |||
637 | #define CC_CLOCK_BASE1 24000000 | ||
638 | #define CC_CLOCK_BASE2 12500000 | ||
639 | |||
640 | |||
641 | #define CLKC_5350_N 0x0311 | ||
642 | #define CLKC_5350_M 0x04020009 | ||
643 | |||
644 | |||
645 | #define FLASH_NONE 0x000 | ||
646 | #define SFLASH_ST 0x100 | ||
647 | #define SFLASH_AT 0x200 | ||
648 | #define PFLASH 0x700 | ||
649 | |||
650 | |||
651 | #define CC_CFG_EN 0x0001 | ||
652 | #define CC_CFG_EM_MASK 0x000e | ||
653 | #define CC_CFG_EM_ASYNC 0x0000 | ||
654 | #define CC_CFG_EM_SYNC 0x0002 | ||
655 | #define CC_CFG_EM_PCMCIA 0x0004 | ||
656 | #define CC_CFG_EM_IDE 0x0006 | ||
657 | #define CC_CFG_DS 0x0010 | ||
658 | #define CC_CFG_CD_MASK 0x00e0 | ||
659 | #define CC_CFG_CE 0x0100 | ||
660 | #define CC_CFG_SB 0x0200 | ||
661 | #define CC_CFG_IS 0x0400 | ||
662 | |||
663 | |||
664 | #define CC_EB_BASE 0x1a000000 | ||
665 | #define CC_EB_PCMCIA_MEM 0x1a000000 | ||
666 | #define CC_EB_PCMCIA_IO 0x1a200000 | ||
667 | #define CC_EB_PCMCIA_CFG 0x1a400000 | ||
668 | #define CC_EB_IDE 0x1a800000 | ||
669 | #define CC_EB_PCMCIA1_MEM 0x1a800000 | ||
670 | #define CC_EB_PCMCIA1_IO 0x1aa00000 | ||
671 | #define CC_EB_PCMCIA1_CFG 0x1ac00000 | ||
672 | #define CC_EB_PROGIF 0x1b000000 | ||
673 | |||
674 | |||
675 | |||
676 | #define SFLASH_OPCODE 0x000000ff | ||
677 | #define SFLASH_ACTION 0x00000700 | ||
678 | #define SFLASH_CS_ACTIVE 0x00001000 | ||
679 | #define SFLASH_START 0x80000000 | ||
680 | #define SFLASH_BUSY SFLASH_START | ||
681 | |||
682 | |||
683 | #define SFLASH_ACT_OPONLY 0x0000 | ||
684 | #define SFLASH_ACT_OP1D 0x0100 | ||
685 | #define SFLASH_ACT_OP3A 0x0200 | ||
686 | #define SFLASH_ACT_OP3A1D 0x0300 | ||
687 | #define SFLASH_ACT_OP3A4D 0x0400 | ||
688 | #define SFLASH_ACT_OP3A4X4D 0x0500 | ||
689 | #define SFLASH_ACT_OP3A1X4D 0x0700 | ||
690 | |||
691 | |||
692 | #define SFLASH_ST_WREN 0x0006 | ||
693 | #define SFLASH_ST_WRDIS 0x0004 | ||
694 | #define SFLASH_ST_RDSR 0x0105 | ||
695 | #define SFLASH_ST_WRSR 0x0101 | ||
696 | #define SFLASH_ST_READ 0x0303 | ||
697 | #define SFLASH_ST_PP 0x0302 | ||
698 | #define SFLASH_ST_SE 0x02d8 | ||
699 | #define SFLASH_ST_BE 0x00c7 | ||
700 | #define SFLASH_ST_DP 0x00b9 | ||
701 | #define SFLASH_ST_RES 0x03ab | ||
702 | #define SFLASH_ST_CSA 0x1000 | ||
703 | #define SFLASH_ST_SSE 0x0220 | ||
704 | |||
705 | |||
706 | #define SFLASH_ST_WIP 0x01 | ||
707 | #define SFLASH_ST_WEL 0x02 | ||
708 | #define SFLASH_ST_BP_MASK 0x1c | ||
709 | #define SFLASH_ST_BP_SHIFT 2 | ||
710 | #define SFLASH_ST_SRWD 0x80 | ||
711 | |||
712 | |||
713 | #define SFLASH_AT_READ 0x07e8 | ||
714 | #define SFLASH_AT_PAGE_READ 0x07d2 | ||
715 | #define SFLASH_AT_BUF1_READ | ||
716 | #define SFLASH_AT_BUF2_READ | ||
717 | #define SFLASH_AT_STATUS 0x01d7 | ||
718 | #define SFLASH_AT_BUF1_WRITE 0x0384 | ||
719 | #define SFLASH_AT_BUF2_WRITE 0x0387 | ||
720 | #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 | ||
721 | #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 | ||
722 | #define SFLASH_AT_BUF1_PROGRAM 0x0288 | ||
723 | #define SFLASH_AT_BUF2_PROGRAM 0x0289 | ||
724 | #define SFLASH_AT_PAGE_ERASE 0x0281 | ||
725 | #define SFLASH_AT_BLOCK_ERASE 0x0250 | ||
726 | #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 | ||
727 | #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 | ||
728 | #define SFLASH_AT_BUF1_LOAD 0x0253 | ||
729 | #define SFLASH_AT_BUF2_LOAD 0x0255 | ||
730 | #define SFLASH_AT_BUF1_COMPARE 0x0260 | ||
731 | #define SFLASH_AT_BUF2_COMPARE 0x0261 | ||
732 | #define SFLASH_AT_BUF1_REPROGRAM 0x0258 | ||
733 | #define SFLASH_AT_BUF2_REPROGRAM 0x0259 | ||
734 | |||
735 | |||
736 | #define SFLASH_AT_READY 0x80 | ||
737 | #define SFLASH_AT_MISMATCH 0x40 | ||
738 | #define SFLASH_AT_ID_MASK 0x38 | ||
739 | #define SFLASH_AT_ID_SHIFT 3 | ||
740 | |||
741 | |||
742 | #define GSIO_START 0x80000000 | ||
743 | #define GSIO_BUSY GSIO_START | ||
744 | |||
745 | |||
746 | |||
747 | #define UART_RX 0 | ||
748 | #define UART_TX 0 | ||
749 | #define UART_DLL 0 | ||
750 | #define UART_IER 1 | ||
751 | #define UART_DLM 1 | ||
752 | #define UART_IIR 2 | ||
753 | #define UART_FCR 2 | ||
754 | #define UART_LCR 3 | ||
755 | #define UART_MCR 4 | ||
756 | #define UART_LSR 5 | ||
757 | #define UART_MSR 6 | ||
758 | #define UART_SCR 7 | ||
759 | #define UART_LCR_DLAB 0x80 | ||
760 | #define UART_LCR_WLEN8 0x03 | ||
761 | #define UART_MCR_OUT2 0x08 | ||
762 | #define UART_MCR_LOOP 0x10 | ||
763 | #define UART_LSR_RX_FIFO 0x80 | ||
764 | #define UART_LSR_TDHR 0x40 | ||
765 | #define UART_LSR_THRE 0x20 | ||
766 | #define UART_LSR_BREAK 0x10 | ||
767 | #define UART_LSR_FRAMING 0x08 | ||
768 | #define UART_LSR_PARITY 0x04 | ||
769 | #define UART_LSR_OVERRUN 0x02 | ||
770 | #define UART_LSR_RXRDY 0x01 | ||
771 | #define UART_FCR_FIFO_ENABLE 1 | ||
772 | |||
773 | |||
774 | #define UART_IIR_FIFO_MASK 0xc0 | ||
775 | #define UART_IIR_INT_MASK 0xf | ||
776 | #define UART_IIR_MDM_CHG 0x0 | ||
777 | #define UART_IIR_NOINT 0x1 | ||
778 | #define UART_IIR_THRE 0x2 | ||
779 | #define UART_IIR_RCVD_DATA 0x4 | ||
780 | #define UART_IIR_RCVR_STATUS 0x6 | ||
781 | #define UART_IIR_CHAR_TIME 0xc | ||
782 | |||
783 | |||
784 | #define UART_IER_EDSSI 8 | ||
785 | #define UART_IER_ELSI 4 | ||
786 | #define UART_IER_ETBEI 2 | ||
787 | #define UART_IER_ERBFI 1 | ||
788 | |||
789 | |||
790 | #define PST_EXTLPOAVAIL 0x0100 | ||
791 | #define PST_WDRESET 0x0080 | ||
792 | #define PST_INTPEND 0x0040 | ||
793 | #define PST_SBCLKST 0x0030 | ||
794 | #define PST_SBCLKST_ILP 0x0010 | ||
795 | #define PST_SBCLKST_ALP 0x0020 | ||
796 | #define PST_SBCLKST_HT 0x0030 | ||
797 | #define PST_ALPAVAIL 0x0008 | ||
798 | #define PST_HTAVAIL 0x0004 | ||
799 | #define PST_RESINIT 0x0003 | ||
800 | |||
801 | |||
802 | #define PCAP_REV_MASK 0x000000ff | ||
803 | #define PCAP_RC_MASK 0x00001f00 | ||
804 | #define PCAP_RC_SHIFT 8 | ||
805 | #define PCAP_TC_MASK 0x0001e000 | ||
806 | #define PCAP_TC_SHIFT 13 | ||
807 | #define PCAP_PC_MASK 0x001e0000 | ||
808 | #define PCAP_PC_SHIFT 17 | ||
809 | #define PCAP_VC_MASK 0x01e00000 | ||
810 | #define PCAP_VC_SHIFT 21 | ||
811 | #define PCAP_CC_MASK 0x1e000000 | ||
812 | #define PCAP_CC_SHIFT 25 | ||
813 | #define PCAP5_PC_MASK 0x003e0000 | ||
814 | #define PCAP5_PC_SHIFT 17 | ||
815 | #define PCAP5_VC_MASK 0x07c00000 | ||
816 | #define PCAP5_VC_SHIFT 22 | ||
817 | #define PCAP5_CC_MASK 0xf8000000 | ||
818 | #define PCAP5_CC_SHIFT 27 | ||
819 | |||
820 | |||
821 | |||
822 | #define PRRT_TIME_MASK 0x03ff | ||
823 | #define PRRT_INTEN 0x0400 | ||
824 | #define PRRT_REQ_ACTIVE 0x0800 | ||
825 | #define PRRT_ALP_REQ 0x1000 | ||
826 | #define PRRT_HT_REQ 0x2000 | ||
827 | |||
828 | |||
829 | #define PMURES_BIT(bit) (1 << (bit)) | ||
830 | |||
831 | |||
832 | #define PMURES_MAX_RESNUM 30 | ||
833 | |||
834 | |||
835 | #define PMU_CHIPCTL0 0 | ||
836 | |||
837 | |||
838 | #define PMU_CC1_CLKREQ_TYPE_SHIFT 19 | ||
839 | #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) | ||
840 | |||
841 | #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 | ||
842 | #define CLKREQ_TYPE_CONFIG_PUSHPULL 1 | ||
843 | |||
844 | |||
845 | #define PMU_CHIPCTL1 1 | ||
846 | #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 | ||
847 | |||
848 | #define PMU_CC1_IF_TYPE_MASK 0x00000030 | ||
849 | #define PMU_CC1_IF_TYPE_RMII 0x00000000 | ||
850 | #define PMU_CC1_IF_TYPE_MII 0x00000010 | ||
851 | #define PMU_CC1_IF_TYPE_RGMII 0x00000020 | ||
852 | |||
853 | #define PMU_CC1_SW_TYPE_MASK 0x000000c0 | ||
854 | #define PMU_CC1_SW_TYPE_EPHY 0x00000000 | ||
855 | #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 | ||
856 | #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 | ||
857 | #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 | ||
858 | |||
859 | |||
860 | |||
861 | |||
862 | |||
863 | #define PMU0_PLL0_PLLCTL0 0 | ||
864 | #define PMU0_PLL0_PC0_PDIV_MASK 1 | ||
865 | #define PMU0_PLL0_PC0_PDIV_FREQ 25000 | ||
866 | #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 | ||
867 | #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 | ||
868 | #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 | ||
869 | |||
870 | |||
871 | #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 | ||
872 | #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 | ||
873 | #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 | ||
874 | #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 | ||
875 | #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 | ||
876 | #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 | ||
877 | #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 | ||
878 | #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 | ||
879 | |||
880 | |||
881 | #define PMU0_PLL0_PLLCTL1 1 | ||
882 | #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 | ||
883 | #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 | ||
884 | #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 | ||
885 | #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 | ||
886 | #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 | ||
887 | |||
888 | |||
889 | #define PMU0_PLL0_PLLCTL2 2 | ||
890 | #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf | ||
891 | #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 | ||
892 | |||
893 | |||
894 | |||
895 | #define PMU1_PLL0_PLLCTL0 0 | ||
896 | #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 | ||
897 | #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 | ||
898 | #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 | ||
899 | #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 | ||
900 | |||
901 | |||
902 | #define PMU1_PLL0_PLLCTL1 1 | ||
903 | #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff | ||
904 | #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 | ||
905 | #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 | ||
906 | #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 | ||
907 | #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 | ||
908 | #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 | ||
909 | #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 | ||
910 | #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 | ||
911 | #define PMU1_PLL0_PC1_M4DIV_BY_9 9 | ||
912 | #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 | ||
913 | #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 | ||
914 | |||
915 | #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 | ||
916 | #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | ||
917 | #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | ||
918 | |||
919 | |||
920 | #define PMU1_PLL0_PLLCTL2 2 | ||
921 | #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff | ||
922 | #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 | ||
923 | #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc | ||
924 | #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 | ||
925 | #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 | ||
926 | #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 | ||
927 | #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 | ||
928 | #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 | ||
929 | #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 | ||
930 | #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 | ||
931 | #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 | ||
932 | #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 | ||
933 | #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 | ||
934 | #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | ||
935 | #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | ||
936 | |||
937 | |||
938 | #define PMU1_PLL0_PLLCTL3 3 | ||
939 | #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff | ||
940 | #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 | ||
941 | |||
942 | |||
943 | #define PMU1_PLL0_PLLCTL4 4 | ||
944 | |||
945 | |||
946 | #define PMU1_PLL0_PLLCTL5 5 | ||
947 | #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 | ||
948 | #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 | ||
949 | |||
950 | |||
951 | #define PMU2_PHY_PLL_PLLCTL 4 | ||
952 | #define PMU2_SI_PLL_PLLCTL 10 | ||
953 | |||
954 | |||
955 | |||
956 | |||
957 | #define PMU2_PLL_PLLCTL0 0 | ||
958 | #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 | ||
959 | #define PMU2_PLL_PC0_P1DIV_SHIFT 20 | ||
960 | #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 | ||
961 | #define PMU2_PLL_PC0_P2DIV_SHIFT 24 | ||
962 | |||
963 | |||
964 | #define PMU2_PLL_PLLCTL1 1 | ||
965 | #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff | ||
966 | #define PMU2_PLL_PC1_M1DIV_SHIFT 0 | ||
967 | #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 | ||
968 | #define PMU2_PLL_PC1_M2DIV_SHIFT 8 | ||
969 | #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 | ||
970 | #define PMU2_PLL_PC1_M3DIV_SHIFT 16 | ||
971 | #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 | ||
972 | #define PMU2_PLL_PC1_M4DIV_SHIFT 24 | ||
973 | |||
974 | |||
975 | #define PMU2_PLL_PLLCTL2 2 | ||
976 | #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff | ||
977 | #define PMU2_PLL_PC2_M5DIV_SHIFT 0 | ||
978 | #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 | ||
979 | #define PMU2_PLL_PC2_M6DIV_SHIFT 8 | ||
980 | #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 | ||
981 | #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 | ||
982 | #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 | ||
983 | #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 | ||
984 | |||
985 | |||
986 | #define PMU2_PLL_PLLCTL3 3 | ||
987 | #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff | ||
988 | #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 | ||
989 | |||
990 | |||
991 | #define PMU2_PLL_PLLCTL4 4 | ||
992 | |||
993 | |||
994 | #define PMU2_PLL_PLLCTL5 5 | ||
995 | #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 | ||
996 | #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 | ||
997 | #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 | ||
998 | #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 | ||
999 | #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 | ||
1000 | #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 | ||
1001 | #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 | ||
1002 | #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 | ||
1003 | #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 | ||
1004 | #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 | ||
1005 | #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 | ||
1006 | #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 | ||
1007 | |||
1008 | |||
1009 | #define PMU5_PLL_P1P2_OFF 0 | ||
1010 | #define PMU5_PLL_P1_MASK 0x0f000000 | ||
1011 | #define PMU5_PLL_P1_SHIFT 24 | ||
1012 | #define PMU5_PLL_P2_MASK 0x00f00000 | ||
1013 | #define PMU5_PLL_P2_SHIFT 20 | ||
1014 | #define PMU5_PLL_M14_OFF 1 | ||
1015 | #define PMU5_PLL_MDIV_MASK 0x000000ff | ||
1016 | #define PMU5_PLL_MDIV_WIDTH 8 | ||
1017 | #define PMU5_PLL_NM5_OFF 2 | ||
1018 | #define PMU5_PLL_NDIV_MASK 0xfff00000 | ||
1019 | #define PMU5_PLL_NDIV_SHIFT 20 | ||
1020 | #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 | ||
1021 | #define PMU5_PLL_NDIV_MODE_SHIFT 17 | ||
1022 | #define PMU5_PLL_FMAB_OFF 3 | ||
1023 | #define PMU5_PLL_MRAT_MASK 0xf0000000 | ||
1024 | #define PMU5_PLL_MRAT_SHIFT 28 | ||
1025 | #define PMU5_PLL_ABRAT_MASK 0x08000000 | ||
1026 | #define PMU5_PLL_ABRAT_SHIFT 27 | ||
1027 | #define PMU5_PLL_FDIV_MASK 0x07ffffff | ||
1028 | #define PMU5_PLL_PLLCTL_OFF 4 | ||
1029 | #define PMU5_PLL_PCHI_OFF 5 | ||
1030 | #define PMU5_PLL_PCHI_MASK 0x0000003f | ||
1031 | |||
1032 | |||
1033 | #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF | ||
1034 | #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 | ||
1035 | #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 | ||
1036 | |||
1037 | |||
1038 | #define PMU5_MAINPLL_CPU 1 | ||
1039 | #define PMU5_MAINPLL_MEM 2 | ||
1040 | #define PMU5_MAINPLL_SI 3 | ||
1041 | |||
1042 | #define PMU7_PLL_PLLCTL7 7 | ||
1043 | #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 | ||
1044 | #define PMU7_PLL_CTL7_M4DIV_SHIFT 24 | ||
1045 | #define PMU7_PLL_CTL7_M4DIV_BY_6 6 | ||
1046 | #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc | ||
1047 | #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 | ||
1048 | #define PMU7_PLL_PLLCTL8 8 | ||
1049 | #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff | ||
1050 | #define PMU7_PLL_CTL8_M5DIV_SHIFT 0 | ||
1051 | #define PMU7_PLL_CTL8_M5DIV_BY_8 8 | ||
1052 | #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc | ||
1053 | #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 | ||
1054 | #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 | ||
1055 | #define PMU7_PLL_CTL8_M6DIV_SHIFT 8 | ||
1056 | #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc | ||
1057 | #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 | ||
1058 | #define PMU7_PLL_PLLCTL11 11 | ||
1059 | #define PMU7_PLL_PLLCTL11_MASK 0xffffff00 | ||
1060 | #define PMU7_PLL_PLLCTL11_VAL 0x22222200 | ||
1061 | |||
1062 | |||
1063 | #define PMU4716_MAINPLL_PLL0 12 | ||
1064 | |||
1065 | |||
1066 | #define PMU5356_MAINPLL_PLL0 0 | ||
1067 | #define PMU5357_MAINPLL_PLL0 0 | ||
1068 | |||
1069 | |||
1070 | #define RES4716_PROC_PLL_ON 0x00000040 | ||
1071 | #define RES4716_PROC_HT_AVAIL 0x00000080 | ||
1072 | |||
1073 | |||
1074 | #define CCTRL_471X_I2S_PINS_ENABLE 0x0080 | ||
1075 | |||
1076 | |||
1077 | |||
1078 | #define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 | ||
1079 | #define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 | ||
1080 | |||
1081 | |||
1082 | #define RES5354_EXT_SWITCHER_PWM 0 | ||
1083 | #define RES5354_BB_SWITCHER_PWM 1 | ||
1084 | #define RES5354_BB_SWITCHER_BURST 2 | ||
1085 | #define RES5354_BB_EXT_SWITCHER_BURST 3 | ||
1086 | #define RES5354_ILP_REQUEST 4 | ||
1087 | #define RES5354_RADIO_SWITCHER_PWM 5 | ||
1088 | #define RES5354_RADIO_SWITCHER_BURST 6 | ||
1089 | #define RES5354_ROM_SWITCH 7 | ||
1090 | #define RES5354_PA_REF_LDO 8 | ||
1091 | #define RES5354_RADIO_LDO 9 | ||
1092 | #define RES5354_AFE_LDO 10 | ||
1093 | #define RES5354_PLL_LDO 11 | ||
1094 | #define RES5354_BG_FILTBYP 12 | ||
1095 | #define RES5354_TX_FILTBYP 13 | ||
1096 | #define RES5354_RX_FILTBYP 14 | ||
1097 | #define RES5354_XTAL_PU 15 | ||
1098 | #define RES5354_XTAL_EN 16 | ||
1099 | #define RES5354_BB_PLL_FILTBYP 17 | ||
1100 | #define RES5354_RF_PLL_FILTBYP 18 | ||
1101 | #define RES5354_BB_PLL_PU 19 | ||
1102 | |||
1103 | |||
1104 | #define CCTRL5357_EXTPA (1<<14) | ||
1105 | #define CCTRL5357_ANT_MUX_2o3 (1<<15) | ||
1106 | |||
1107 | |||
1108 | #define RES4328_EXT_SWITCHER_PWM 0 | ||
1109 | #define RES4328_BB_SWITCHER_PWM 1 | ||
1110 | #define RES4328_BB_SWITCHER_BURST 2 | ||
1111 | #define RES4328_BB_EXT_SWITCHER_BURST 3 | ||
1112 | #define RES4328_ILP_REQUEST 4 | ||
1113 | #define RES4328_RADIO_SWITCHER_PWM 5 | ||
1114 | #define RES4328_RADIO_SWITCHER_BURST 6 | ||
1115 | #define RES4328_ROM_SWITCH 7 | ||
1116 | #define RES4328_PA_REF_LDO 8 | ||
1117 | #define RES4328_RADIO_LDO 9 | ||
1118 | #define RES4328_AFE_LDO 10 | ||
1119 | #define RES4328_PLL_LDO 11 | ||
1120 | #define RES4328_BG_FILTBYP 12 | ||
1121 | #define RES4328_TX_FILTBYP 13 | ||
1122 | #define RES4328_RX_FILTBYP 14 | ||
1123 | #define RES4328_XTAL_PU 15 | ||
1124 | #define RES4328_XTAL_EN 16 | ||
1125 | #define RES4328_BB_PLL_FILTBYP 17 | ||
1126 | #define RES4328_RF_PLL_FILTBYP 18 | ||
1127 | #define RES4328_BB_PLL_PU 19 | ||
1128 | |||
1129 | |||
1130 | #define RES4325_BUCK_BOOST_BURST 0 | ||
1131 | #define RES4325_CBUCK_BURST 1 | ||
1132 | #define RES4325_CBUCK_PWM 2 | ||
1133 | #define RES4325_CLDO_CBUCK_BURST 3 | ||
1134 | #define RES4325_CLDO_CBUCK_PWM 4 | ||
1135 | #define RES4325_BUCK_BOOST_PWM 5 | ||
1136 | #define RES4325_ILP_REQUEST 6 | ||
1137 | #define RES4325_ABUCK_BURST 7 | ||
1138 | #define RES4325_ABUCK_PWM 8 | ||
1139 | #define RES4325_LNLDO1_PU 9 | ||
1140 | #define RES4325_OTP_PU 10 | ||
1141 | #define RES4325_LNLDO3_PU 11 | ||
1142 | #define RES4325_LNLDO4_PU 12 | ||
1143 | #define RES4325_XTAL_PU 13 | ||
1144 | #define RES4325_ALP_AVAIL 14 | ||
1145 | #define RES4325_RX_PWRSW_PU 15 | ||
1146 | #define RES4325_TX_PWRSW_PU 16 | ||
1147 | #define RES4325_RFPLL_PWRSW_PU 17 | ||
1148 | #define RES4325_LOGEN_PWRSW_PU 18 | ||
1149 | #define RES4325_AFE_PWRSW_PU 19 | ||
1150 | #define RES4325_BBPLL_PWRSW_PU 20 | ||
1151 | #define RES4325_HT_AVAIL 21 | ||
1152 | |||
1153 | |||
1154 | #define RES4325B0_CBUCK_LPOM 1 | ||
1155 | #define RES4325B0_CBUCK_BURST 2 | ||
1156 | #define RES4325B0_CBUCK_PWM 3 | ||
1157 | #define RES4325B0_CLDO_PU 4 | ||
1158 | |||
1159 | |||
1160 | #define RES4325C1_LNLDO2_PU 12 | ||
1161 | |||
1162 | |||
1163 | #define CST4325_SPROM_OTP_SEL_MASK 0x00000003 | ||
1164 | #define CST4325_DEFCIS_SEL 0 | ||
1165 | #define CST4325_SPROM_SEL 1 | ||
1166 | #define CST4325_OTP_SEL 2 | ||
1167 | #define CST4325_OTP_PWRDN 3 | ||
1168 | #define CST4325_SDIO_USB_MODE_MASK 0x00000004 | ||
1169 | #define CST4325_SDIO_USB_MODE_SHIFT 2 | ||
1170 | #define CST4325_RCAL_VALID_MASK 0x00000008 | ||
1171 | #define CST4325_RCAL_VALID_SHIFT 3 | ||
1172 | #define CST4325_RCAL_VALUE_MASK 0x000001f0 | ||
1173 | #define CST4325_RCAL_VALUE_SHIFT 4 | ||
1174 | #define CST4325_PMUTOP_2B_MASK 0x00000200 | ||
1175 | #define CST4325_PMUTOP_2B_SHIFT 9 | ||
1176 | |||
1177 | #define RES4329_RESERVED0 0 | ||
1178 | #define RES4329_CBUCK_LPOM 1 | ||
1179 | #define RES4329_CBUCK_BURST 2 | ||
1180 | #define RES4329_CBUCK_PWM 3 | ||
1181 | #define RES4329_CLDO_PU 4 | ||
1182 | #define RES4329_PALDO_PU 5 | ||
1183 | #define RES4329_ILP_REQUEST 6 | ||
1184 | #define RES4329_RESERVED7 7 | ||
1185 | #define RES4329_RESERVED8 8 | ||
1186 | #define RES4329_LNLDO1_PU 9 | ||
1187 | #define RES4329_OTP_PU 10 | ||
1188 | #define RES4329_RESERVED11 11 | ||
1189 | #define RES4329_LNLDO2_PU 12 | ||
1190 | #define RES4329_XTAL_PU 13 | ||
1191 | #define RES4329_ALP_AVAIL 14 | ||
1192 | #define RES4329_RX_PWRSW_PU 15 | ||
1193 | #define RES4329_TX_PWRSW_PU 16 | ||
1194 | #define RES4329_RFPLL_PWRSW_PU 17 | ||
1195 | #define RES4329_LOGEN_PWRSW_PU 18 | ||
1196 | #define RES4329_AFE_PWRSW_PU 19 | ||
1197 | #define RES4329_BBPLL_PWRSW_PU 20 | ||
1198 | #define RES4329_HT_AVAIL 21 | ||
1199 | |||
1200 | #define CST4329_SPROM_OTP_SEL_MASK 0x00000003 | ||
1201 | #define CST4329_DEFCIS_SEL 0 | ||
1202 | #define CST4329_SPROM_SEL 1 | ||
1203 | #define CST4329_OTP_SEL 2 | ||
1204 | #define CST4329_OTP_PWRDN 3 | ||
1205 | #define CST4329_SPI_SDIO_MODE_MASK 0x00000004 | ||
1206 | #define CST4329_SPI_SDIO_MODE_SHIFT 2 | ||
1207 | |||
1208 | |||
1209 | #define CST4312_SPROM_OTP_SEL_MASK 0x00000003 | ||
1210 | #define CST4312_DEFCIS_SEL 0 | ||
1211 | #define CST4312_SPROM_SEL 1 | ||
1212 | #define CST4312_OTP_SEL 2 | ||
1213 | #define CST4312_OTP_BAD 3 | ||
1214 | |||
1215 | |||
1216 | #define RES4312_SWITCHER_BURST 0 | ||
1217 | #define RES4312_SWITCHER_PWM 1 | ||
1218 | #define RES4312_PA_REF_LDO 2 | ||
1219 | #define RES4312_CORE_LDO_BURST 3 | ||
1220 | #define RES4312_CORE_LDO_PWM 4 | ||
1221 | #define RES4312_RADIO_LDO 5 | ||
1222 | #define RES4312_ILP_REQUEST 6 | ||
1223 | #define RES4312_BG_FILTBYP 7 | ||
1224 | #define RES4312_TX_FILTBYP 8 | ||
1225 | #define RES4312_RX_FILTBYP 9 | ||
1226 | #define RES4312_XTAL_PU 10 | ||
1227 | #define RES4312_ALP_AVAIL 11 | ||
1228 | #define RES4312_BB_PLL_FILTBYP 12 | ||
1229 | #define RES4312_RF_PLL_FILTBYP 13 | ||
1230 | #define RES4312_HT_AVAIL 14 | ||
1231 | |||
1232 | |||
1233 | #define RES4322_RF_LDO 0 | ||
1234 | #define RES4322_ILP_REQUEST 1 | ||
1235 | #define RES4322_XTAL_PU 2 | ||
1236 | #define RES4322_ALP_AVAIL 3 | ||
1237 | #define RES4322_SI_PLL_ON 4 | ||
1238 | #define RES4322_HT_SI_AVAIL 5 | ||
1239 | #define RES4322_PHY_PLL_ON 6 | ||
1240 | #define RES4322_HT_PHY_AVAIL 7 | ||
1241 | #define RES4322_OTP_PU 8 | ||
1242 | |||
1243 | |||
1244 | #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 | ||
1245 | #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 | ||
1246 | #define CST4322_SPROM_OTP_SEL_SHIFT 6 | ||
1247 | #define CST4322_NO_SPROM_OTP 0 | ||
1248 | #define CST4322_SPROM_PRESENT 1 | ||
1249 | #define CST4322_OTP_PRESENT 2 | ||
1250 | #define CST4322_PCI_OR_USB 0x00000100 | ||
1251 | #define CST4322_BOOT_MASK 0x00000600 | ||
1252 | #define CST4322_BOOT_SHIFT 9 | ||
1253 | #define CST4322_BOOT_FROM_SRAM 0 | ||
1254 | #define CST4322_BOOT_FROM_ROM 1 | ||
1255 | #define CST4322_BOOT_FROM_FLASH 2 | ||
1256 | #define CST4322_BOOT_FROM_INVALID 3 | ||
1257 | #define CST4322_ILP_DIV_EN 0x00000800 | ||
1258 | #define CST4322_FLASH_TYPE_MASK 0x00001000 | ||
1259 | #define CST4322_FLASH_TYPE_SHIFT 12 | ||
1260 | #define CST4322_FLASH_TYPE_SHIFT_ST 0 | ||
1261 | #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 | ||
1262 | #define CST4322_ARM_TAP_SEL 0x00002000 | ||
1263 | #define CST4322_RES_INIT_MODE_MASK 0x0000c000 | ||
1264 | #define CST4322_RES_INIT_MODE_SHIFT 14 | ||
1265 | #define CST4322_RES_INIT_MODE_ILPAVAIL 0 | ||
1266 | #define CST4322_RES_INIT_MODE_ILPREQ 1 | ||
1267 | #define CST4322_RES_INIT_MODE_ALPAVAIL 2 | ||
1268 | #define CST4322_RES_INIT_MODE_HTAVAIL 3 | ||
1269 | #define CST4322_PCIPLLCLK_GATING 0x00010000 | ||
1270 | #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 | ||
1271 | #define CST4322_PCI_CARDBUS_MODE 0x00040000 | ||
1272 | |||
1273 | |||
1274 | #define CCTRL43224_GPIO_TOGGLE 0x8000 | ||
1275 | #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 | ||
1276 | #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 | ||
1277 | |||
1278 | |||
1279 | #define RES43236_REGULATOR 0 | ||
1280 | #define RES43236_ILP_REQUEST 1 | ||
1281 | #define RES43236_XTAL_PU 2 | ||
1282 | #define RES43236_ALP_AVAIL 3 | ||
1283 | #define RES43236_SI_PLL_ON 4 | ||
1284 | #define RES43236_HT_SI_AVAIL 5 | ||
1285 | |||
1286 | |||
1287 | #define CCTRL43236_BT_COEXIST (1<<0) | ||
1288 | #define CCTRL43236_SECI (1<<1) | ||
1289 | #define CCTRL43236_EXT_LNA (1<<2) | ||
1290 | #define CCTRL43236_ANT_MUX_2o3 (1<<3) | ||
1291 | #define CCTRL43236_GSIO (1<<4) | ||
1292 | |||
1293 | |||
1294 | #define CST43236_SFLASH_MASK 0x00000040 | ||
1295 | #define CST43236_OTP_SEL_MASK 0x00000080 | ||
1296 | #define CST43236_OTP_SEL_SHIFT 7 | ||
1297 | #define CST43236_HSIC_MASK 0x00000100 | ||
1298 | #define CST43236_BP_CLK 0x00000200 | ||
1299 | #define CST43236_BOOT_MASK 0x00001800 | ||
1300 | #define CST43236_BOOT_SHIFT 11 | ||
1301 | #define CST43236_BOOT_FROM_SRAM 0 | ||
1302 | #define CST43236_BOOT_FROM_ROM 1 | ||
1303 | #define CST43236_BOOT_FROM_FLASH 2 | ||
1304 | #define CST43236_BOOT_FROM_INVALID 3 | ||
1305 | |||
1306 | |||
1307 | #define RES43237_REGULATOR 0 | ||
1308 | #define RES43237_ILP_REQUEST 1 | ||
1309 | #define RES43237_XTAL_PU 2 | ||
1310 | #define RES43237_ALP_AVAIL 3 | ||
1311 | #define RES43237_SI_PLL_ON 4 | ||
1312 | #define RES43237_HT_SI_AVAIL 5 | ||
1313 | |||
1314 | |||
1315 | #define CCTRL43237_BT_COEXIST (1<<0) | ||
1316 | #define CCTRL43237_SECI (1<<1) | ||
1317 | #define CCTRL43237_EXT_LNA (1<<2) | ||
1318 | #define CCTRL43237_ANT_MUX_2o3 (1<<3) | ||
1319 | #define CCTRL43237_GSIO (1<<4) | ||
1320 | |||
1321 | |||
1322 | #define CST43237_SFLASH_MASK 0x00000040 | ||
1323 | #define CST43237_OTP_SEL_MASK 0x00000080 | ||
1324 | #define CST43237_OTP_SEL_SHIFT 7 | ||
1325 | #define CST43237_HSIC_MASK 0x00000100 | ||
1326 | #define CST43237_BP_CLK 0x00000200 | ||
1327 | #define CST43237_BOOT_MASK 0x00001800 | ||
1328 | #define CST43237_BOOT_SHIFT 11 | ||
1329 | #define CST43237_BOOT_FROM_SRAM 0 | ||
1330 | #define CST43237_BOOT_FROM_ROM 1 | ||
1331 | #define CST43237_BOOT_FROM_FLASH 2 | ||
1332 | #define CST43237_BOOT_FROM_INVALID 3 | ||
1333 | |||
1334 | |||
1335 | #define RES43239_OTP_PU 9 | ||
1336 | #define RES43239_MACPHY_CLKAVAIL 23 | ||
1337 | #define RES43239_HT_AVAIL 24 | ||
1338 | |||
1339 | |||
1340 | #define CST43239_SPROM_MASK 0x00000002 | ||
1341 | #define CST43239_SFLASH_MASK 0x00000004 | ||
1342 | #define CST43239_RES_INIT_MODE_SHIFT 7 | ||
1343 | #define CST43239_RES_INIT_MODE_MASK 0x000001f0 | ||
1344 | #define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) | ||
1345 | #define CST43239_CHIPMODE_USB20D(cs) ((cs) & !(1 << 15)) | ||
1346 | #define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) | ||
1347 | #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) | ||
1348 | |||
1349 | |||
1350 | #define CCTRL43239_XTAL_STRENGTH(ctl) ((ctl & 0x3F) << 12) | ||
1351 | |||
1352 | |||
1353 | |||
1354 | |||
1355 | #define RES4315_CBUCK_LPOM 1 | ||
1356 | #define RES4315_CBUCK_BURST 2 | ||
1357 | #define RES4315_CBUCK_PWM 3 | ||
1358 | #define RES4315_CLDO_PU 4 | ||
1359 | #define RES4315_PALDO_PU 5 | ||
1360 | #define RES4315_ILP_REQUEST 6 | ||
1361 | #define RES4315_LNLDO1_PU 9 | ||
1362 | #define RES4315_OTP_PU 10 | ||
1363 | #define RES4315_LNLDO2_PU 12 | ||
1364 | #define RES4315_XTAL_PU 13 | ||
1365 | #define RES4315_ALP_AVAIL 14 | ||
1366 | #define RES4315_RX_PWRSW_PU 15 | ||
1367 | #define RES4315_TX_PWRSW_PU 16 | ||
1368 | #define RES4315_RFPLL_PWRSW_PU 17 | ||
1369 | #define RES4315_LOGEN_PWRSW_PU 18 | ||
1370 | #define RES4315_AFE_PWRSW_PU 19 | ||
1371 | #define RES4315_BBPLL_PWRSW_PU 20 | ||
1372 | #define RES4315_HT_AVAIL 21 | ||
1373 | |||
1374 | |||
1375 | #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 | ||
1376 | #define CST4315_DEFCIS_SEL 0x00000000 | ||
1377 | #define CST4315_SPROM_SEL 0x00000001 | ||
1378 | #define CST4315_OTP_SEL 0x00000002 | ||
1379 | #define CST4315_OTP_PWRDN 0x00000003 | ||
1380 | #define CST4315_SDIO_MODE 0x00000004 | ||
1381 | #define CST4315_RCAL_VALID 0x00000008 | ||
1382 | #define CST4315_RCAL_VALUE_MASK 0x000001f0 | ||
1383 | #define CST4315_RCAL_VALUE_SHIFT 4 | ||
1384 | #define CST4315_PALDO_EXTPNP 0x00000200 | ||
1385 | #define CST4315_CBUCK_MODE_MASK 0x00000c00 | ||
1386 | #define CST4315_CBUCK_MODE_BURST 0x00000400 | ||
1387 | #define CST4315_CBUCK_MODE_LPBURST 0x00000c00 | ||
1388 | |||
1389 | |||
1390 | #define RES4319_CBUCK_LPOM 1 | ||
1391 | #define RES4319_CBUCK_BURST 2 | ||
1392 | #define RES4319_CBUCK_PWM 3 | ||
1393 | #define RES4319_CLDO_PU 4 | ||
1394 | #define RES4319_PALDO_PU 5 | ||
1395 | #define RES4319_ILP_REQUEST 6 | ||
1396 | #define RES4319_LNLDO1_PU 9 | ||
1397 | #define RES4319_OTP_PU 10 | ||
1398 | #define RES4319_LNLDO2_PU 12 | ||
1399 | #define RES4319_XTAL_PU 13 | ||
1400 | #define RES4319_ALP_AVAIL 14 | ||
1401 | #define RES4319_RX_PWRSW_PU 15 | ||
1402 | #define RES4319_TX_PWRSW_PU 16 | ||
1403 | #define RES4319_RFPLL_PWRSW_PU 17 | ||
1404 | #define RES4319_LOGEN_PWRSW_PU 18 | ||
1405 | #define RES4319_AFE_PWRSW_PU 19 | ||
1406 | #define RES4319_BBPLL_PWRSW_PU 20 | ||
1407 | #define RES4319_HT_AVAIL 21 | ||
1408 | |||
1409 | |||
1410 | #define CST4319_SPI_CPULESSUSB 0x00000001 | ||
1411 | #define CST4319_SPI_CLK_POL 0x00000002 | ||
1412 | #define CST4319_SPI_CLK_PH 0x00000008 | ||
1413 | #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 | ||
1414 | #define CST4319_SPROM_OTP_SEL_SHIFT 6 | ||
1415 | #define CST4319_DEFCIS_SEL 0x00000000 | ||
1416 | #define CST4319_SPROM_SEL 0x00000040 | ||
1417 | #define CST4319_OTP_SEL 0x00000080 | ||
1418 | #define CST4319_OTP_PWRDN 0x000000c0 | ||
1419 | #define CST4319_SDIO_USB_MODE 0x00000100 | ||
1420 | #define CST4319_REMAP_SEL_MASK 0x00000600 | ||
1421 | #define CST4319_ILPDIV_EN 0x00000800 | ||
1422 | #define CST4319_XTAL_PD_POL 0x00001000 | ||
1423 | #define CST4319_LPO_SEL 0x00002000 | ||
1424 | #define CST4319_RES_INIT_MODE 0x0000c000 | ||
1425 | #define CST4319_PALDO_EXTPNP 0x00010000 | ||
1426 | #define CST4319_CBUCK_MODE_MASK 0x00060000 | ||
1427 | #define CST4319_CBUCK_MODE_BURST 0x00020000 | ||
1428 | #define CST4319_CBUCK_MODE_LPBURST 0x00060000 | ||
1429 | #define CST4319_RCAL_VALID 0x01000000 | ||
1430 | #define CST4319_RCAL_VALUE_MASK 0x3e000000 | ||
1431 | #define CST4319_RCAL_VALUE_SHIFT 25 | ||
1432 | |||
1433 | #define PMU1_PLL0_CHIPCTL0 0 | ||
1434 | #define PMU1_PLL0_CHIPCTL1 1 | ||
1435 | #define PMU1_PLL0_CHIPCTL2 2 | ||
1436 | #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000 | ||
1437 | #define CCTL_4319USB_XTAL_SEL_SHIFT 19 | ||
1438 | #define CCTL_4319USB_48MHZ_PLL_SEL 1 | ||
1439 | #define CCTL_4319USB_24MHZ_PLL_SEL 2 | ||
1440 | |||
1441 | |||
1442 | #define RES4336_CBUCK_LPOM 0 | ||
1443 | #define RES4336_CBUCK_BURST 1 | ||
1444 | #define RES4336_CBUCK_LP_PWM 2 | ||
1445 | #define RES4336_CBUCK_PWM 3 | ||
1446 | #define RES4336_CLDO_PU 4 | ||
1447 | #define RES4336_DIS_INT_RESET_PD 5 | ||
1448 | #define RES4336_ILP_REQUEST 6 | ||
1449 | #define RES4336_LNLDO_PU 7 | ||
1450 | #define RES4336_LDO3P3_PU 8 | ||
1451 | #define RES4336_OTP_PU 9 | ||
1452 | #define RES4336_XTAL_PU 10 | ||
1453 | #define RES4336_ALP_AVAIL 11 | ||
1454 | #define RES4336_RADIO_PU 12 | ||
1455 | #define RES4336_BG_PU 13 | ||
1456 | #define RES4336_VREG1p4_PU_PU 14 | ||
1457 | #define RES4336_AFE_PWRSW_PU 15 | ||
1458 | #define RES4336_RX_PWRSW_PU 16 | ||
1459 | #define RES4336_TX_PWRSW_PU 17 | ||
1460 | #define RES4336_BB_PWRSW_PU 18 | ||
1461 | #define RES4336_SYNTH_PWRSW_PU 19 | ||
1462 | #define RES4336_MISC_PWRSW_PU 20 | ||
1463 | #define RES4336_LOGEN_PWRSW_PU 21 | ||
1464 | #define RES4336_BBPLL_PWRSW_PU 22 | ||
1465 | #define RES4336_MACPHY_CLKAVAIL 23 | ||
1466 | #define RES4336_HT_AVAIL 24 | ||
1467 | #define RES4336_RSVD 25 | ||
1468 | |||
1469 | |||
1470 | #define CST4336_SPI_MODE_MASK 0x00000001 | ||
1471 | #define CST4336_SPROM_PRESENT 0x00000002 | ||
1472 | #define CST4336_OTP_PRESENT 0x00000004 | ||
1473 | #define CST4336_ARMREMAP_0 0x00000008 | ||
1474 | #define CST4336_ILPDIV_EN_MASK 0x00000010 | ||
1475 | #define CST4336_ILPDIV_EN_SHIFT 4 | ||
1476 | #define CST4336_XTAL_PD_POL_MASK 0x00000020 | ||
1477 | #define CST4336_XTAL_PD_POL_SHIFT 5 | ||
1478 | #define CST4336_LPO_SEL_MASK 0x00000040 | ||
1479 | #define CST4336_LPO_SEL_SHIFT 6 | ||
1480 | #define CST4336_RES_INIT_MODE_MASK 0x00000180 | ||
1481 | #define CST4336_RES_INIT_MODE_SHIFT 7 | ||
1482 | #define CST4336_CBUCK_MODE_MASK 0x00000600 | ||
1483 | #define CST4336_CBUCK_MODE_SHIFT 9 | ||
1484 | |||
1485 | |||
1486 | #define PCTL_4336_SERIAL_ENAB (1 << 24) | ||
1487 | |||
1488 | |||
1489 | #define RES4330_CBUCK_LPOM 0 | ||
1490 | #define RES4330_CBUCK_BURST 1 | ||
1491 | #define RES4330_CBUCK_LP_PWM 2 | ||
1492 | #define RES4330_CBUCK_PWM 3 | ||
1493 | #define RES4330_CLDO_PU 4 | ||
1494 | #define RES4330_DIS_INT_RESET_PD 5 | ||
1495 | #define RES4330_ILP_REQUEST 6 | ||
1496 | #define RES4330_LNLDO_PU 7 | ||
1497 | #define RES4330_LDO3P3_PU 8 | ||
1498 | #define RES4330_OTP_PU 9 | ||
1499 | #define RES4330_XTAL_PU 10 | ||
1500 | #define RES4330_ALP_AVAIL 11 | ||
1501 | #define RES4330_RADIO_PU 12 | ||
1502 | #define RES4330_BG_PU 13 | ||
1503 | #define RES4330_VREG1p4_PU_PU 14 | ||
1504 | #define RES4330_AFE_PWRSW_PU 15 | ||
1505 | #define RES4330_RX_PWRSW_PU 16 | ||
1506 | #define RES4330_TX_PWRSW_PU 17 | ||
1507 | #define RES4330_BB_PWRSW_PU 18 | ||
1508 | #define RES4330_SYNTH_PWRSW_PU 19 | ||
1509 | #define RES4330_MISC_PWRSW_PU 20 | ||
1510 | #define RES4330_LOGEN_PWRSW_PU 21 | ||
1511 | #define RES4330_BBPLL_PWRSW_PU 22 | ||
1512 | #define RES4330_MACPHY_CLKAVAIL 23 | ||
1513 | #define RES4330_HT_AVAIL 24 | ||
1514 | #define RES4330_5gRX_PWRSW_PU 25 | ||
1515 | #define RES4330_5gTX_PWRSW_PU 26 | ||
1516 | #define RES4330_5g_LOGEN_PWRSW_PU 27 | ||
1517 | |||
1518 | |||
1519 | #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) | ||
1520 | #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) | ||
1521 | #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) | ||
1522 | #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) | ||
1523 | #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) | ||
1524 | #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) | ||
1525 | #define CST4330_OTP_PRESENT 0x00000010 | ||
1526 | #define CST4330_LPO_AUTODET_EN 0x00000020 | ||
1527 | #define CST4330_ARMREMAP_0 0x00000040 | ||
1528 | #define CST4330_SPROM_PRESENT 0x00000080 | ||
1529 | #define CST4330_ILPDIV_EN 0x00000100 | ||
1530 | #define CST4330_LPO_SEL 0x00000200 | ||
1531 | #define CST4330_RES_INIT_MODE_SHIFT 10 | ||
1532 | #define CST4330_RES_INIT_MODE_MASK 0x00000c00 | ||
1533 | #define CST4330_CBUCK_MODE_SHIFT 12 | ||
1534 | #define CST4330_CBUCK_MODE_MASK 0x00003000 | ||
1535 | #define CST4330_CBUCK_POWER_OK 0x00004000 | ||
1536 | #define CST4330_BB_PLL_LOCKED 0x00008000 | ||
1537 | #define SOCDEVRAM_4330_BP_ADDR 0x1E000000 | ||
1538 | #define SOCDEVRAM_4330_ARM_ADDR 0x00800000 | ||
1539 | |||
1540 | |||
1541 | #define PCTL_4330_SERIAL_ENAB (1 << 24) | ||
1542 | |||
1543 | |||
1544 | #define CCTRL_4330_GPIO_SEL 0x00000001 | ||
1545 | #define CCTRL_4330_ERCX_SEL 0x00000002 | ||
1546 | #define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 | ||
1547 | #define CCTRL_4330_JTAG_DISABLE 0x00000008 | ||
1548 | |||
1549 | |||
1550 | #define RES4313_BB_PU_RSRC 0 | ||
1551 | #define RES4313_ILP_REQ_RSRC 1 | ||
1552 | #define RES4313_XTAL_PU_RSRC 2 | ||
1553 | #define RES4313_ALP_AVAIL_RSRC 3 | ||
1554 | #define RES4313_RADIO_PU_RSRC 4 | ||
1555 | #define RES4313_BG_PU_RSRC 5 | ||
1556 | #define RES4313_VREG1P4_PU_RSRC 6 | ||
1557 | #define RES4313_AFE_PWRSW_RSRC 7 | ||
1558 | #define RES4313_RX_PWRSW_RSRC 8 | ||
1559 | #define RES4313_TX_PWRSW_RSRC 9 | ||
1560 | #define RES4313_BB_PWRSW_RSRC 10 | ||
1561 | #define RES4313_SYNTH_PWRSW_RSRC 11 | ||
1562 | #define RES4313_MISC_PWRSW_RSRC 12 | ||
1563 | #define RES4313_BB_PLL_PWRSW_RSRC 13 | ||
1564 | #define RES4313_HT_AVAIL_RSRC 14 | ||
1565 | #define RES4313_MACPHY_CLK_AVAIL_RSRC 15 | ||
1566 | |||
1567 | |||
1568 | #define CST4313_SPROM_PRESENT 1 | ||
1569 | #define CST4313_OTP_PRESENT 2 | ||
1570 | #define CST4313_SPROM_OTP_SEL_MASK 0x00000002 | ||
1571 | #define CST4313_SPROM_OTP_SEL_SHIFT 0 | ||
1572 | |||
1573 | |||
1574 | #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 | ||
1575 | |||
1576 | |||
1577 | #define RES43228_NOT_USED 0 | ||
1578 | #define RES43228_ILP_REQUEST 1 | ||
1579 | #define RES43228_XTAL_PU 2 | ||
1580 | #define RES43228_ALP_AVAIL 3 | ||
1581 | #define RES43228_PLL_EN 4 | ||
1582 | #define RES43228_HT_PHY_AVAIL 5 | ||
1583 | |||
1584 | |||
1585 | #define CST43228_ILP_DIV_EN 0x1 | ||
1586 | #define CST43228_OTP_PRESENT 0x2 | ||
1587 | #define CST43228_SERDES_REFCLK_PADSEL 0x4 | ||
1588 | #define CST43228_SDIO_MODE 0x8 | ||
1589 | #define CST43228_SDIO_OTP_PRESENT 0x10 | ||
1590 | #define CST43228_SDIO_RESET 0x20 | ||
1591 | |||
1592 | |||
1593 | #define PMU_MAX_TRANSITION_DLY 15000 | ||
1594 | |||
1595 | |||
1596 | #define PMURES_UP_TRANSITION 2 | ||
1597 | |||
1598 | |||
1599 | |||
1600 | |||
1601 | |||
1602 | #define ECI_BW_20 0x0 | ||
1603 | #define ECI_BW_25 0x1 | ||
1604 | #define ECI_BW_30 0x2 | ||
1605 | #define ECI_BW_35 0x3 | ||
1606 | #define ECI_BW_40 0x4 | ||
1607 | #define ECI_BW_45 0x5 | ||
1608 | #define ECI_BW_50 0x6 | ||
1609 | #define ECI_BW_ALL 0x7 | ||
1610 | |||
1611 | |||
1612 | #define WLAN_NUM_ANT1 TXANT_0 | ||
1613 | #define WLAN_NUM_ANT2 TXANT_1 | ||
1614 | |||
1615 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbconfig.h b/drivers/net/wireless/bcmdhd/include/sbconfig.h new file mode 100644 index 00000000000..76f05ae34bd --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbconfig.h | |||
@@ -0,0 +1,276 @@ | |||
1 | /* | ||
2 | * Broadcom SiliconBackplane hardware register definitions. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: sbconfig.h,v 13.70 2008-03-28 19:17:04 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _SBCONFIG_H | ||
29 | #define _SBCONFIG_H | ||
30 | |||
31 | |||
32 | #ifndef PAD | ||
33 | #define _PADLINE(line) pad ## line | ||
34 | #define _XSTR(line) _PADLINE(line) | ||
35 | #define PAD _XSTR(__LINE__) | ||
36 | #endif | ||
37 | |||
38 | |||
39 | #define SB_BUS_SIZE 0x10000 | ||
40 | #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE) | ||
41 | #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) | ||
42 | |||
43 | |||
44 | #define SBCONFIGOFF 0xf00 | ||
45 | #define SBCONFIGSIZE 256 | ||
46 | |||
47 | #define SBIPSFLAG 0x08 | ||
48 | #define SBTPSFLAG 0x18 | ||
49 | #define SBTMERRLOGA 0x48 | ||
50 | #define SBTMERRLOG 0x50 | ||
51 | #define SBADMATCH3 0x60 | ||
52 | #define SBADMATCH2 0x68 | ||
53 | #define SBADMATCH1 0x70 | ||
54 | #define SBIMSTATE 0x90 | ||
55 | #define SBINTVEC 0x94 | ||
56 | #define SBTMSTATELOW 0x98 | ||
57 | #define SBTMSTATEHIGH 0x9c | ||
58 | #define SBBWA0 0xa0 | ||
59 | #define SBIMCONFIGLOW 0xa8 | ||
60 | #define SBIMCONFIGHIGH 0xac | ||
61 | #define SBADMATCH0 0xb0 | ||
62 | #define SBTMCONFIGLOW 0xb8 | ||
63 | #define SBTMCONFIGHIGH 0xbc | ||
64 | #define SBBCONFIG 0xc0 | ||
65 | #define SBBSTATE 0xc8 | ||
66 | #define SBACTCNFG 0xd8 | ||
67 | #define SBFLAGST 0xe8 | ||
68 | #define SBIDLOW 0xf8 | ||
69 | #define SBIDHIGH 0xfc | ||
70 | |||
71 | |||
72 | |||
73 | #define SBIMERRLOGA 0xea8 | ||
74 | #define SBIMERRLOG 0xeb0 | ||
75 | #define SBTMPORTCONNID0 0xed8 | ||
76 | #define SBTMPORTLOCK0 0xef8 | ||
77 | |||
78 | #ifndef _LANGUAGE_ASSEMBLY | ||
79 | |||
80 | typedef volatile struct _sbconfig { | ||
81 | uint32 PAD[2]; | ||
82 | uint32 sbipsflag; | ||
83 | uint32 PAD[3]; | ||
84 | uint32 sbtpsflag; | ||
85 | uint32 PAD[11]; | ||
86 | uint32 sbtmerrloga; | ||
87 | uint32 PAD; | ||
88 | uint32 sbtmerrlog; | ||
89 | uint32 PAD[3]; | ||
90 | uint32 sbadmatch3; | ||
91 | uint32 PAD; | ||
92 | uint32 sbadmatch2; | ||
93 | uint32 PAD; | ||
94 | uint32 sbadmatch1; | ||
95 | uint32 PAD[7]; | ||
96 | uint32 sbimstate; | ||
97 | uint32 sbintvec; | ||
98 | uint32 sbtmstatelow; | ||
99 | uint32 sbtmstatehigh; | ||
100 | uint32 sbbwa0; | ||
101 | uint32 PAD; | ||
102 | uint32 sbimconfiglow; | ||
103 | uint32 sbimconfighigh; | ||
104 | uint32 sbadmatch0; | ||
105 | uint32 PAD; | ||
106 | uint32 sbtmconfiglow; | ||
107 | uint32 sbtmconfighigh; | ||
108 | uint32 sbbconfig; | ||
109 | uint32 PAD; | ||
110 | uint32 sbbstate; | ||
111 | uint32 PAD[3]; | ||
112 | uint32 sbactcnfg; | ||
113 | uint32 PAD[3]; | ||
114 | uint32 sbflagst; | ||
115 | uint32 PAD[3]; | ||
116 | uint32 sbidlow; | ||
117 | uint32 sbidhigh; | ||
118 | } sbconfig_t; | ||
119 | |||
120 | #endif | ||
121 | |||
122 | |||
123 | #define SBIPS_INT1_MASK 0x3f | ||
124 | #define SBIPS_INT1_SHIFT 0 | ||
125 | #define SBIPS_INT2_MASK 0x3f00 | ||
126 | #define SBIPS_INT2_SHIFT 8 | ||
127 | #define SBIPS_INT3_MASK 0x3f0000 | ||
128 | #define SBIPS_INT3_SHIFT 16 | ||
129 | #define SBIPS_INT4_MASK 0x3f000000 | ||
130 | #define SBIPS_INT4_SHIFT 24 | ||
131 | |||
132 | |||
133 | #define SBTPS_NUM0_MASK 0x3f | ||
134 | #define SBTPS_F0EN0 0x40 | ||
135 | |||
136 | |||
137 | #define SBTMEL_CM 0x00000007 | ||
138 | #define SBTMEL_CI 0x0000ff00 | ||
139 | #define SBTMEL_EC 0x0f000000 | ||
140 | #define SBTMEL_ME 0x80000000 | ||
141 | |||
142 | |||
143 | #define SBIM_PC 0xf | ||
144 | #define SBIM_AP_MASK 0x30 | ||
145 | #define SBIM_AP_BOTH 0x00 | ||
146 | #define SBIM_AP_TS 0x10 | ||
147 | #define SBIM_AP_TK 0x20 | ||
148 | #define SBIM_AP_RSV 0x30 | ||
149 | #define SBIM_IBE 0x20000 | ||
150 | #define SBIM_TO 0x40000 | ||
151 | #define SBIM_BY 0x01800000 | ||
152 | #define SBIM_RJ 0x02000000 | ||
153 | |||
154 | |||
155 | #define SBTML_RESET 0x0001 | ||
156 | #define SBTML_REJ_MASK 0x0006 | ||
157 | #define SBTML_REJ 0x0002 | ||
158 | #define SBTML_TMPREJ 0x0004 | ||
159 | |||
160 | #define SBTML_SICF_SHIFT 16 | ||
161 | |||
162 | |||
163 | #define SBTMH_SERR 0x0001 | ||
164 | #define SBTMH_INT 0x0002 | ||
165 | #define SBTMH_BUSY 0x0004 | ||
166 | #define SBTMH_TO 0x0020 | ||
167 | |||
168 | #define SBTMH_SISF_SHIFT 16 | ||
169 | |||
170 | |||
171 | #define SBBWA_TAB0_MASK 0xffff | ||
172 | #define SBBWA_TAB1_MASK 0xffff | ||
173 | #define SBBWA_TAB1_SHIFT 16 | ||
174 | |||
175 | |||
176 | #define SBIMCL_STO_MASK 0x7 | ||
177 | #define SBIMCL_RTO_MASK 0x70 | ||
178 | #define SBIMCL_RTO_SHIFT 4 | ||
179 | #define SBIMCL_CID_MASK 0xff0000 | ||
180 | #define SBIMCL_CID_SHIFT 16 | ||
181 | |||
182 | |||
183 | #define SBIMCH_IEM_MASK 0xc | ||
184 | #define SBIMCH_TEM_MASK 0x30 | ||
185 | #define SBIMCH_TEM_SHIFT 4 | ||
186 | #define SBIMCH_BEM_MASK 0xc0 | ||
187 | #define SBIMCH_BEM_SHIFT 6 | ||
188 | |||
189 | |||
190 | #define SBAM_TYPE_MASK 0x3 | ||
191 | #define SBAM_AD64 0x4 | ||
192 | #define SBAM_ADINT0_MASK 0xf8 | ||
193 | #define SBAM_ADINT0_SHIFT 3 | ||
194 | #define SBAM_ADINT1_MASK 0x1f8 | ||
195 | #define SBAM_ADINT1_SHIFT 3 | ||
196 | #define SBAM_ADINT2_MASK 0x1f8 | ||
197 | #define SBAM_ADINT2_SHIFT 3 | ||
198 | #define SBAM_ADEN 0x400 | ||
199 | #define SBAM_ADNEG 0x800 | ||
200 | #define SBAM_BASE0_MASK 0xffffff00 | ||
201 | #define SBAM_BASE0_SHIFT 8 | ||
202 | #define SBAM_BASE1_MASK 0xfffff000 | ||
203 | #define SBAM_BASE1_SHIFT 12 | ||
204 | #define SBAM_BASE2_MASK 0xffff0000 | ||
205 | #define SBAM_BASE2_SHIFT 16 | ||
206 | |||
207 | |||
208 | #define SBTMCL_CD_MASK 0xff | ||
209 | #define SBTMCL_CO_MASK 0xf800 | ||
210 | #define SBTMCL_CO_SHIFT 11 | ||
211 | #define SBTMCL_IF_MASK 0xfc0000 | ||
212 | #define SBTMCL_IF_SHIFT 18 | ||
213 | #define SBTMCL_IM_MASK 0x3000000 | ||
214 | #define SBTMCL_IM_SHIFT 24 | ||
215 | |||
216 | |||
217 | #define SBTMCH_BM_MASK 0x3 | ||
218 | #define SBTMCH_RM_MASK 0x3 | ||
219 | #define SBTMCH_RM_SHIFT 2 | ||
220 | #define SBTMCH_SM_MASK 0x30 | ||
221 | #define SBTMCH_SM_SHIFT 4 | ||
222 | #define SBTMCH_EM_MASK 0x300 | ||
223 | #define SBTMCH_EM_SHIFT 8 | ||
224 | #define SBTMCH_IM_MASK 0xc00 | ||
225 | #define SBTMCH_IM_SHIFT 10 | ||
226 | |||
227 | |||
228 | #define SBBC_LAT_MASK 0x3 | ||
229 | #define SBBC_MAX0_MASK 0xf0000 | ||
230 | #define SBBC_MAX0_SHIFT 16 | ||
231 | #define SBBC_MAX1_MASK 0xf00000 | ||
232 | #define SBBC_MAX1_SHIFT 20 | ||
233 | |||
234 | |||
235 | #define SBBS_SRD 0x1 | ||
236 | #define SBBS_HRD 0x2 | ||
237 | |||
238 | |||
239 | #define SBIDL_CS_MASK 0x3 | ||
240 | #define SBIDL_AR_MASK 0x38 | ||
241 | #define SBIDL_AR_SHIFT 3 | ||
242 | #define SBIDL_SYNCH 0x40 | ||
243 | #define SBIDL_INIT 0x80 | ||
244 | #define SBIDL_MINLAT_MASK 0xf00 | ||
245 | #define SBIDL_MINLAT_SHIFT 8 | ||
246 | #define SBIDL_MAXLAT 0xf000 | ||
247 | #define SBIDL_MAXLAT_SHIFT 12 | ||
248 | #define SBIDL_FIRST 0x10000 | ||
249 | #define SBIDL_CW_MASK 0xc0000 | ||
250 | #define SBIDL_CW_SHIFT 18 | ||
251 | #define SBIDL_TP_MASK 0xf00000 | ||
252 | #define SBIDL_TP_SHIFT 20 | ||
253 | #define SBIDL_IP_MASK 0xf000000 | ||
254 | #define SBIDL_IP_SHIFT 24 | ||
255 | #define SBIDL_RV_MASK 0xf0000000 | ||
256 | #define SBIDL_RV_SHIFT 28 | ||
257 | #define SBIDL_RV_2_2 0x00000000 | ||
258 | #define SBIDL_RV_2_3 0x10000000 | ||
259 | |||
260 | |||
261 | #define SBIDH_RC_MASK 0x000f | ||
262 | #define SBIDH_RCE_MASK 0x7000 | ||
263 | #define SBIDH_RCE_SHIFT 8 | ||
264 | #define SBCOREREV(sbidh) \ | ||
265 | ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) | ||
266 | #define SBIDH_CC_MASK 0x8ff0 | ||
267 | #define SBIDH_CC_SHIFT 4 | ||
268 | #define SBIDH_VC_MASK 0xffff0000 | ||
269 | #define SBIDH_VC_SHIFT 16 | ||
270 | |||
271 | #define SB_COMMIT 0xfd8 | ||
272 | |||
273 | |||
274 | #define SB_VEND_BCM 0x4243 | ||
275 | |||
276 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbhnddma.h b/drivers/net/wireless/bcmdhd/include/sbhnddma.h new file mode 100644 index 00000000000..05d0587bc20 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbhnddma.h | |||
@@ -0,0 +1,327 @@ | |||
1 | /* | ||
2 | * Generic Broadcom Home Networking Division (HND) DMA engine HW interface | ||
3 | * This supports the following chips: BCM42xx, 44xx, 47xx . | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: sbhnddma.h,v 13.20.2.3 2010-10-14 22:21:29 Exp $ | ||
26 | */ | ||
27 | |||
28 | |||
29 | #ifndef _sbhnddma_h_ | ||
30 | #define _sbhnddma_h_ | ||
31 | |||
32 | |||
33 | |||
34 | |||
35 | |||
36 | |||
37 | |||
38 | typedef volatile struct { | ||
39 | uint32 control; | ||
40 | uint32 addr; | ||
41 | uint32 ptr; | ||
42 | uint32 status; | ||
43 | } dma32regs_t; | ||
44 | |||
45 | typedef volatile struct { | ||
46 | dma32regs_t xmt; | ||
47 | dma32regs_t rcv; | ||
48 | } dma32regp_t; | ||
49 | |||
50 | typedef volatile struct { | ||
51 | uint32 fifoaddr; | ||
52 | uint32 fifodatalow; | ||
53 | uint32 fifodatahigh; | ||
54 | uint32 pad; | ||
55 | } dma32diag_t; | ||
56 | |||
57 | |||
58 | typedef volatile struct { | ||
59 | uint32 ctrl; | ||
60 | uint32 addr; | ||
61 | } dma32dd_t; | ||
62 | |||
63 | |||
64 | #define D32RINGALIGN_BITS 12 | ||
65 | #define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) | ||
66 | #define D32RINGALIGN (1 << D32RINGALIGN_BITS) | ||
67 | |||
68 | #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) | ||
69 | |||
70 | |||
71 | #define XC_XE ((uint32)1 << 0) | ||
72 | #define XC_SE ((uint32)1 << 1) | ||
73 | #define XC_LE ((uint32)1 << 2) | ||
74 | #define XC_FL ((uint32)1 << 4) | ||
75 | #define XC_PD ((uint32)1 << 11) | ||
76 | #define XC_AE ((uint32)3 << 16) | ||
77 | #define XC_AE_SHIFT 16 | ||
78 | #define XC_BL_MASK 0x001C0000 | ||
79 | #define XC_BL_SHIFT 18 | ||
80 | |||
81 | |||
82 | #define XP_LD_MASK 0xfff | ||
83 | |||
84 | |||
85 | #define XS_CD_MASK 0x0fff | ||
86 | #define XS_XS_MASK 0xf000 | ||
87 | #define XS_XS_SHIFT 12 | ||
88 | #define XS_XS_DISABLED 0x0000 | ||
89 | #define XS_XS_ACTIVE 0x1000 | ||
90 | #define XS_XS_IDLE 0x2000 | ||
91 | #define XS_XS_STOPPED 0x3000 | ||
92 | #define XS_XS_SUSP 0x4000 | ||
93 | #define XS_XE_MASK 0xf0000 | ||
94 | #define XS_XE_SHIFT 16 | ||
95 | #define XS_XE_NOERR 0x00000 | ||
96 | #define XS_XE_DPE 0x10000 | ||
97 | #define XS_XE_DFU 0x20000 | ||
98 | #define XS_XE_BEBR 0x30000 | ||
99 | #define XS_XE_BEDA 0x40000 | ||
100 | #define XS_AD_MASK 0xfff00000 | ||
101 | #define XS_AD_SHIFT 20 | ||
102 | |||
103 | |||
104 | #define RC_RE ((uint32)1 << 0) | ||
105 | #define RC_RO_MASK 0xfe | ||
106 | #define RC_RO_SHIFT 1 | ||
107 | #define RC_FM ((uint32)1 << 8) | ||
108 | #define RC_SH ((uint32)1 << 9) | ||
109 | #define RC_OC ((uint32)1 << 10) | ||
110 | #define RC_PD ((uint32)1 << 11) | ||
111 | #define RC_AE ((uint32)3 << 16) | ||
112 | #define RC_AE_SHIFT 16 | ||
113 | #define RC_BL_MASK 0x001C0000 | ||
114 | #define RC_BL_SHIFT 18 | ||
115 | |||
116 | |||
117 | #define RP_LD_MASK 0xfff | ||
118 | |||
119 | |||
120 | #define RS_CD_MASK 0x0fff | ||
121 | #define RS_RS_MASK 0xf000 | ||
122 | #define RS_RS_SHIFT 12 | ||
123 | #define RS_RS_DISABLED 0x0000 | ||
124 | #define RS_RS_ACTIVE 0x1000 | ||
125 | #define RS_RS_IDLE 0x2000 | ||
126 | #define RS_RS_STOPPED 0x3000 | ||
127 | #define RS_RE_MASK 0xf0000 | ||
128 | #define RS_RE_SHIFT 16 | ||
129 | #define RS_RE_NOERR 0x00000 | ||
130 | #define RS_RE_DPE 0x10000 | ||
131 | #define RS_RE_DFO 0x20000 | ||
132 | #define RS_RE_BEBW 0x30000 | ||
133 | #define RS_RE_BEDA 0x40000 | ||
134 | #define RS_AD_MASK 0xfff00000 | ||
135 | #define RS_AD_SHIFT 20 | ||
136 | |||
137 | |||
138 | #define FA_OFF_MASK 0xffff | ||
139 | #define FA_SEL_MASK 0xf0000 | ||
140 | #define FA_SEL_SHIFT 16 | ||
141 | #define FA_SEL_XDD 0x00000 | ||
142 | #define FA_SEL_XDP 0x10000 | ||
143 | #define FA_SEL_RDD 0x40000 | ||
144 | #define FA_SEL_RDP 0x50000 | ||
145 | #define FA_SEL_XFD 0x80000 | ||
146 | #define FA_SEL_XFP 0x90000 | ||
147 | #define FA_SEL_RFD 0xc0000 | ||
148 | #define FA_SEL_RFP 0xd0000 | ||
149 | #define FA_SEL_RSD 0xe0000 | ||
150 | #define FA_SEL_RSP 0xf0000 | ||
151 | |||
152 | |||
153 | #define CTRL_BC_MASK 0x00001fff | ||
154 | #define CTRL_AE ((uint32)3 << 16) | ||
155 | #define CTRL_AE_SHIFT 16 | ||
156 | #define CTRL_PARITY ((uint32)3 << 18) | ||
157 | #define CTRL_EOT ((uint32)1 << 28) | ||
158 | #define CTRL_IOC ((uint32)1 << 29) | ||
159 | #define CTRL_EOF ((uint32)1 << 30) | ||
160 | #define CTRL_SOF ((uint32)1 << 31) | ||
161 | |||
162 | |||
163 | #define CTRL_CORE_MASK 0x0ff00000 | ||
164 | |||
165 | |||
166 | |||
167 | |||
168 | typedef volatile struct { | ||
169 | uint32 control; | ||
170 | uint32 ptr; | ||
171 | uint32 addrlow; | ||
172 | uint32 addrhigh; | ||
173 | uint32 status0; | ||
174 | uint32 status1; | ||
175 | } dma64regs_t; | ||
176 | |||
177 | typedef volatile struct { | ||
178 | dma64regs_t tx; | ||
179 | dma64regs_t rx; | ||
180 | } dma64regp_t; | ||
181 | |||
182 | typedef volatile struct { | ||
183 | uint32 fifoaddr; | ||
184 | uint32 fifodatalow; | ||
185 | uint32 fifodatahigh; | ||
186 | uint32 pad; | ||
187 | } dma64diag_t; | ||
188 | |||
189 | |||
190 | typedef volatile struct { | ||
191 | uint32 ctrl1; | ||
192 | uint32 ctrl2; | ||
193 | uint32 addrlow; | ||
194 | uint32 addrhigh; | ||
195 | } dma64dd_t; | ||
196 | |||
197 | |||
198 | #define D64RINGALIGN_BITS 13 | ||
199 | #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) | ||
200 | #define D64RINGALIGN (1 << D64RINGALIGN_BITS) | ||
201 | |||
202 | #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) | ||
203 | |||
204 | |||
205 | #define D64_DEF_USBBURSTLEN 2 | ||
206 | #define D64_DEF_SDIOBURSTLEN 1 | ||
207 | |||
208 | |||
209 | #define D64_XC_XE 0x00000001 | ||
210 | #define D64_XC_SE 0x00000002 | ||
211 | #define D64_XC_LE 0x00000004 | ||
212 | #define D64_XC_FL 0x00000010 | ||
213 | #define D64_XC_PD 0x00000800 | ||
214 | #define D64_XC_AE 0x00030000 | ||
215 | #define D64_XC_AE_SHIFT 16 | ||
216 | #define D64_XC_BL_MASK 0x001C0000 | ||
217 | #define D64_XC_BL_SHIFT 18 | ||
218 | |||
219 | |||
220 | #define D64_XP_LD_MASK 0x00000fff | ||
221 | |||
222 | |||
223 | #define D64_XS0_CD_MASK 0x00001fff | ||
224 | #define D64_XS0_XS_MASK 0xf0000000 | ||
225 | #define D64_XS0_XS_SHIFT 28 | ||
226 | #define D64_XS0_XS_DISABLED 0x00000000 | ||
227 | #define D64_XS0_XS_ACTIVE 0x10000000 | ||
228 | #define D64_XS0_XS_IDLE 0x20000000 | ||
229 | #define D64_XS0_XS_STOPPED 0x30000000 | ||
230 | #define D64_XS0_XS_SUSP 0x40000000 | ||
231 | |||
232 | #define D64_XS1_AD_MASK 0x00001fff | ||
233 | #define D64_XS1_XE_MASK 0xf0000000 | ||
234 | #define D64_XS1_XE_SHIFT 28 | ||
235 | #define D64_XS1_XE_NOERR 0x00000000 | ||
236 | #define D64_XS1_XE_DPE 0x10000000 | ||
237 | #define D64_XS1_XE_DFU 0x20000000 | ||
238 | #define D64_XS1_XE_DTE 0x30000000 | ||
239 | #define D64_XS1_XE_DESRE 0x40000000 | ||
240 | #define D64_XS1_XE_COREE 0x50000000 | ||
241 | |||
242 | |||
243 | #define D64_RC_RE 0x00000001 | ||
244 | #define D64_RC_RO_MASK 0x000000fe | ||
245 | #define D64_RC_RO_SHIFT 1 | ||
246 | #define D64_RC_FM 0x00000100 | ||
247 | #define D64_RC_SH 0x00000200 | ||
248 | #define D64_RC_OC 0x00000400 | ||
249 | #define D64_RC_PD 0x00000800 | ||
250 | #define D64_RC_AE 0x00030000 | ||
251 | #define D64_RC_AE_SHIFT 16 | ||
252 | #define D64_RC_BL_MASK 0x001C0000 | ||
253 | #define D64_RC_BL_SHIFT 18 | ||
254 | |||
255 | |||
256 | #define DMA_CTRL_PEN (1 << 0) | ||
257 | #define DMA_CTRL_ROC (1 << 1) | ||
258 | #define DMA_CTRL_RXMULTI (1 << 2) | ||
259 | #define DMA_CTRL_UNFRAMED (1 << 3) | ||
260 | #define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4) | ||
261 | |||
262 | |||
263 | #define D64_RP_LD_MASK 0x00000fff | ||
264 | |||
265 | |||
266 | #define D64_RS0_CD_MASK 0x00001fff | ||
267 | #define D64_RS0_RS_MASK 0xf0000000 | ||
268 | #define D64_RS0_RS_SHIFT 28 | ||
269 | #define D64_RS0_RS_DISABLED 0x00000000 | ||
270 | #define D64_RS0_RS_ACTIVE 0x10000000 | ||
271 | #define D64_RS0_RS_IDLE 0x20000000 | ||
272 | #define D64_RS0_RS_STOPPED 0x30000000 | ||
273 | #define D64_RS0_RS_SUSP 0x40000000 | ||
274 | |||
275 | #define D64_RS1_AD_MASK 0x0001ffff | ||
276 | #define D64_RS1_RE_MASK 0xf0000000 | ||
277 | #define D64_RS1_RE_SHIFT 28 | ||
278 | #define D64_RS1_RE_NOERR 0x00000000 | ||
279 | #define D64_RS1_RE_DPO 0x10000000 | ||
280 | #define D64_RS1_RE_DFU 0x20000000 | ||
281 | #define D64_RS1_RE_DTE 0x30000000 | ||
282 | #define D64_RS1_RE_DESRE 0x40000000 | ||
283 | #define D64_RS1_RE_COREE 0x50000000 | ||
284 | |||
285 | |||
286 | #define D64_FA_OFF_MASK 0xffff | ||
287 | #define D64_FA_SEL_MASK 0xf0000 | ||
288 | #define D64_FA_SEL_SHIFT 16 | ||
289 | #define D64_FA_SEL_XDD 0x00000 | ||
290 | #define D64_FA_SEL_XDP 0x10000 | ||
291 | #define D64_FA_SEL_RDD 0x40000 | ||
292 | #define D64_FA_SEL_RDP 0x50000 | ||
293 | #define D64_FA_SEL_XFD 0x80000 | ||
294 | #define D64_FA_SEL_XFP 0x90000 | ||
295 | #define D64_FA_SEL_RFD 0xc0000 | ||
296 | #define D64_FA_SEL_RFP 0xd0000 | ||
297 | #define D64_FA_SEL_RSD 0xe0000 | ||
298 | #define D64_FA_SEL_RSP 0xf0000 | ||
299 | |||
300 | |||
301 | #define D64_CTRL_COREFLAGS 0x0ff00000 | ||
302 | #define D64_CTRL1_EOT ((uint32)1 << 28) | ||
303 | #define D64_CTRL1_IOC ((uint32)1 << 29) | ||
304 | #define D64_CTRL1_EOF ((uint32)1 << 30) | ||
305 | #define D64_CTRL1_SOF ((uint32)1 << 31) | ||
306 | |||
307 | |||
308 | #define D64_CTRL2_BC_MASK 0x00007fff | ||
309 | #define D64_CTRL2_AE 0x00030000 | ||
310 | #define D64_CTRL2_AE_SHIFT 16 | ||
311 | #define D64_CTRL2_PARITY 0x00040000 | ||
312 | |||
313 | |||
314 | #define D64_CTRL_CORE_MASK 0x0ff00000 | ||
315 | |||
316 | #define D64_RX_FRM_STS_LEN 0x0000ffff | ||
317 | #define D64_RX_FRM_STS_OVFL 0x00800000 | ||
318 | #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 | ||
319 | #define D64_RX_FRM_STS_DATATYPE 0xf0000000 | ||
320 | |||
321 | |||
322 | typedef volatile struct { | ||
323 | uint16 len; | ||
324 | uint16 flags; | ||
325 | } dma_rxh_t; | ||
326 | |||
327 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbpcmcia.h b/drivers/net/wireless/bcmdhd/include/sbpcmcia.h new file mode 100644 index 00000000000..aba914bd014 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbpcmcia.h | |||
@@ -0,0 +1,109 @@ | |||
1 | /* | ||
2 | * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: sbpcmcia.h,v 13.48.12.6 2010-11-04 09:39:42 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _SBPCMCIA_H | ||
29 | #define _SBPCMCIA_H | ||
30 | |||
31 | |||
32 | |||
33 | |||
34 | #define PCMCIA_FCR (0x700 / 2) | ||
35 | |||
36 | #define FCR0_OFF 0 | ||
37 | #define FCR1_OFF (0x40 / 2) | ||
38 | #define FCR2_OFF (0x80 / 2) | ||
39 | #define FCR3_OFF (0xc0 / 2) | ||
40 | |||
41 | #define PCMCIA_FCR0 (0x700 / 2) | ||
42 | #define PCMCIA_FCR1 (0x740 / 2) | ||
43 | #define PCMCIA_FCR2 (0x780 / 2) | ||
44 | #define PCMCIA_FCR3 (0x7c0 / 2) | ||
45 | |||
46 | |||
47 | |||
48 | #define PCMCIA_COR 0 | ||
49 | |||
50 | #define COR_RST 0x80 | ||
51 | #define COR_LEV 0x40 | ||
52 | #define COR_IRQEN 0x04 | ||
53 | #define COR_BLREN 0x01 | ||
54 | #define COR_FUNEN 0x01 | ||
55 | |||
56 | |||
57 | #define PCICIA_FCSR (2 / 2) | ||
58 | #define PCICIA_PRR (4 / 2) | ||
59 | #define PCICIA_SCR (6 / 2) | ||
60 | #define PCICIA_ESR (8 / 2) | ||
61 | |||
62 | |||
63 | #define PCM_MEMOFF 0x0000 | ||
64 | #define F0_MEMOFF 0x1000 | ||
65 | #define F1_MEMOFF 0x2000 | ||
66 | #define F2_MEMOFF 0x3000 | ||
67 | #define F3_MEMOFF 0x4000 | ||
68 | |||
69 | |||
70 | #define MEM_ADDR0 (0x728 / 2) | ||
71 | #define MEM_ADDR1 (0x72a / 2) | ||
72 | #define MEM_ADDR2 (0x72c / 2) | ||
73 | |||
74 | |||
75 | #define PCMCIA_ADDR0 (0x072e / 2) | ||
76 | #define PCMCIA_ADDR1 (0x0730 / 2) | ||
77 | #define PCMCIA_ADDR2 (0x0732 / 2) | ||
78 | |||
79 | #define MEM_SEG (0x0734 / 2) | ||
80 | #define SROM_CS (0x0736 / 2) | ||
81 | #define SROM_DATAL (0x0738 / 2) | ||
82 | #define SROM_DATAH (0x073a / 2) | ||
83 | #define SROM_ADDRL (0x073c / 2) | ||
84 | #define SROM_ADDRH (0x073e / 2) | ||
85 | #define SROM_INFO2 (0x0772 / 2) | ||
86 | #define SROM_INFO (0x07be / 2) | ||
87 | |||
88 | |||
89 | #define SROM_IDLE 0 | ||
90 | #define SROM_WRITE 1 | ||
91 | #define SROM_READ 2 | ||
92 | #define SROM_WEN 4 | ||
93 | #define SROM_WDS 7 | ||
94 | #define SROM_DONE 8 | ||
95 | |||
96 | |||
97 | #define SRI_SZ_MASK 0x03 | ||
98 | #define SRI_BLANK 0x04 | ||
99 | #define SRI_OTP 0x80 | ||
100 | |||
101 | |||
102 | |||
103 | #define SBTML_INT_ACK 0x40000 | ||
104 | #define SBTML_INT_EN 0x20000 | ||
105 | |||
106 | |||
107 | #define SBTMH_INT_STATUS 0x40000 | ||
108 | |||
109 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbsdio.h b/drivers/net/wireless/bcmdhd/include/sbsdio.h new file mode 100644 index 00000000000..4280d5bf9c1 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbsdio.h | |||
@@ -0,0 +1,166 @@ | |||
1 | /* | ||
2 | * SDIO device core hardware definitions. | ||
3 | * sdio is a portion of the pcmcia core in core rev 3 - rev 8 | ||
4 | * | ||
5 | * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode. | ||
6 | * | ||
7 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
8 | * | ||
9 | * Unless you and Broadcom execute a separate written software license | ||
10 | * agreement governing use of this software, this software is licensed to you | ||
11 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
12 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
13 | * following added to such license: | ||
14 | * | ||
15 | * As a special exception, the copyright holders of this software give you | ||
16 | * permission to link this software with independent modules, and to copy and | ||
17 | * distribute the resulting executable under terms of your choice, provided that | ||
18 | * you also meet, for each linked independent module, the terms and conditions of | ||
19 | * the license of that module. An independent module is a module which is not | ||
20 | * derived from this software. The special exception does not apply to any | ||
21 | * modifications of the software. | ||
22 | * | ||
23 | * Notwithstanding the above, under no circumstances may you combine this | ||
24 | * software in any way with any other Broadcom software provided under a license | ||
25 | * other than the GPL, without Broadcom's express prior written consent. | ||
26 | * | ||
27 | * $Id: sbsdio.h,v 13.34 2009-03-11 20:27:16 Exp $ | ||
28 | */ | ||
29 | |||
30 | #ifndef _SBSDIO_H | ||
31 | #define _SBSDIO_H | ||
32 | |||
33 | #define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */ | ||
34 | |||
35 | /* function 1 miscellaneous registers */ | ||
36 | #define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */ | ||
37 | #define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */ | ||
38 | #define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */ | ||
39 | #define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */ | ||
40 | #define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */ | ||
41 | #define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */ | ||
42 | #define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */ | ||
43 | #define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */ | ||
44 | #define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */ | ||
45 | #define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ | ||
46 | |||
47 | /* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */ | ||
48 | #define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */ | ||
49 | #define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */ | ||
50 | #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */ | ||
51 | #define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */ | ||
52 | #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */ | ||
53 | #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */ | ||
54 | #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */ | ||
55 | #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */ | ||
56 | #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */ | ||
57 | #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */ | ||
58 | |||
59 | #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ | ||
60 | #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */ | ||
61 | |||
62 | /* SBSDIO_SPROM_CS */ | ||
63 | #define SBSDIO_SPROM_IDLE 0 | ||
64 | #define SBSDIO_SPROM_WRITE 1 | ||
65 | #define SBSDIO_SPROM_READ 2 | ||
66 | #define SBSDIO_SPROM_WEN 4 | ||
67 | #define SBSDIO_SPROM_WDS 7 | ||
68 | #define SBSDIO_SPROM_DONE 8 | ||
69 | |||
70 | /* SBSDIO_SPROM_INFO */ | ||
71 | #define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ | ||
72 | #define SROM_BLANK 0x04 /* depreciated in corerev 6 */ | ||
73 | #define SROM_OTP 0x80 /* OTP present */ | ||
74 | |||
75 | /* SBSDIO_CHIP_CTRL */ | ||
76 | #define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu, | ||
77 | * 1: power on oscillator | ||
78 | * (for 4318 only) | ||
79 | */ | ||
80 | /* SBSDIO_WATERMARK */ | ||
81 | #define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device | ||
82 | * to wait before sending data to host | ||
83 | */ | ||
84 | |||
85 | /* SBSDIO_DEVICE_CTL */ | ||
86 | #define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when | ||
87 | * receiving CMD53 | ||
88 | */ | ||
89 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is | ||
90 | * synchronous to the sdio clock | ||
91 | */ | ||
92 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host | ||
93 | * except the chipActive (rev 8) | ||
94 | */ | ||
95 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put | ||
96 | * external pads in tri-state; requires | ||
97 | * sdio bus power cycle to clear (rev 9) | ||
98 | */ | ||
99 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */ | ||
100 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */ | ||
101 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */ | ||
102 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */ | ||
103 | |||
104 | |||
105 | /* SBSDIO_FUNC1_CHIPCLKCSR */ | ||
106 | #define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ | ||
107 | #define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */ | ||
108 | #define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */ | ||
109 | #define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */ | ||
110 | #define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */ | ||
111 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */ | ||
112 | #define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */ | ||
113 | #define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */ | ||
114 | /* In rev8, actual avail bits followed original docs */ | ||
115 | #define SBSDIO_Rev8_HT_AVAIL 0x40 | ||
116 | #define SBSDIO_Rev8_ALP_AVAIL 0x80 | ||
117 | |||
118 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) | ||
119 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | ||
120 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | ||
121 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | ||
122 | #define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \ | ||
123 | (alponly ? 1 : SBSDIO_HTAV(regval))) | ||
124 | |||
125 | /* SBSDIO_FUNC1_SDIOPULLUP */ | ||
126 | #define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */ | ||
127 | #define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */ | ||
128 | #define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */ | ||
129 | #define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */ | ||
130 | #define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */ | ||
131 | |||
132 | /* function 1 OCP space */ | ||
133 | #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */ | ||
134 | #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 | ||
135 | #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */ | ||
136 | |||
137 | /* some duplication with sbsdpcmdev.h here */ | ||
138 | /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ | ||
139 | #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ | ||
140 | #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ | ||
141 | #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ | ||
142 | #define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */ | ||
143 | |||
144 | /* direct(mapped) cis space */ | ||
145 | #define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */ | ||
146 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */ | ||
147 | #define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */ | ||
148 | |||
149 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */ | ||
150 | |||
151 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple, | ||
152 | * link bytes | ||
153 | */ | ||
154 | |||
155 | /* indirect cis access (in sprom) */ | ||
156 | #define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from | ||
157 | * 8th byte | ||
158 | */ | ||
159 | |||
160 | #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one | ||
161 | * data comamnd | ||
162 | */ | ||
163 | |||
164 | #define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */ | ||
165 | |||
166 | #endif /* _SBSDIO_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h b/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h new file mode 100644 index 00000000000..107a8b07c9e --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h | |||
@@ -0,0 +1,293 @@ | |||
1 | /* | ||
2 | * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific | ||
3 | * device core support | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: sbsdpcmdev.h,v 13.38 2009-09-22 22:56:45 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _sbsdpcmdev_h_ | ||
29 | #define _sbsdpcmdev_h_ | ||
30 | |||
31 | /* cpp contortions to concatenate w/arg prescan */ | ||
32 | #ifndef PAD | ||
33 | #define _PADLINE(line) pad ## line | ||
34 | #define _XSTR(line) _PADLINE(line) | ||
35 | #define PAD _XSTR(__LINE__) | ||
36 | #endif /* PAD */ | ||
37 | |||
38 | |||
39 | typedef volatile struct { | ||
40 | dma64regs_t xmt; /* dma tx */ | ||
41 | uint32 PAD[2]; | ||
42 | dma64regs_t rcv; /* dma rx */ | ||
43 | uint32 PAD[2]; | ||
44 | } dma64p_t; | ||
45 | |||
46 | /* dma64 sdiod corerev >= 1 */ | ||
47 | typedef volatile struct { | ||
48 | dma64p_t dma64regs[2]; | ||
49 | dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */ | ||
50 | uint32 PAD[92]; | ||
51 | } sdiodma64_t; | ||
52 | |||
53 | /* dma32 sdiod corerev == 0 */ | ||
54 | typedef volatile struct { | ||
55 | dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */ | ||
56 | dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */ | ||
57 | uint32 PAD[108]; | ||
58 | } sdiodma32_t; | ||
59 | |||
60 | /* dma32 regs for pcmcia core */ | ||
61 | typedef volatile struct { | ||
62 | dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ | ||
63 | dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ | ||
64 | uint32 PAD[116]; | ||
65 | } pcmdma32_t; | ||
66 | |||
67 | /* core registers */ | ||
68 | typedef volatile struct { | ||
69 | uint32 corecontrol; /* CoreControl, 0x000, rev8 */ | ||
70 | uint32 corestatus; /* CoreStatus, 0x004, rev8 */ | ||
71 | uint32 PAD[1]; | ||
72 | uint32 biststatus; /* BistStatus, 0x00c, rev8 */ | ||
73 | |||
74 | /* PCMCIA access */ | ||
75 | uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ | ||
76 | uint16 PAD[1]; | ||
77 | uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ | ||
78 | uint16 PAD[1]; | ||
79 | uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ | ||
80 | uint16 PAD[1]; | ||
81 | uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ | ||
82 | uint16 PAD[1]; | ||
83 | |||
84 | /* interrupt */ | ||
85 | uint32 intstatus; /* IntStatus, 0x020, rev8 */ | ||
86 | uint32 hostintmask; /* IntHostMask, 0x024, rev8 */ | ||
87 | uint32 intmask; /* IntSbMask, 0x028, rev8 */ | ||
88 | uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ | ||
89 | uint32 sbintmask; /* SBIntMask, 0x030, rev8 */ | ||
90 | uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */ | ||
91 | uint32 PAD[2]; | ||
92 | uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ | ||
93 | uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ | ||
94 | uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ | ||
95 | uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ | ||
96 | |||
97 | /* synchronized access to registers in SDIO clock domain */ | ||
98 | uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */ | ||
99 | uint32 PAD[3]; | ||
100 | |||
101 | /* PCMCIA frame control */ | ||
102 | uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ | ||
103 | uint8 PAD[3]; | ||
104 | uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */ | ||
105 | uint8 PAD[155]; | ||
106 | |||
107 | /* interrupt batching control */ | ||
108 | uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ | ||
109 | uint32 PAD[3]; | ||
110 | |||
111 | /* counters */ | ||
112 | uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ | ||
113 | uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ | ||
114 | uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ | ||
115 | uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ | ||
116 | uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ | ||
117 | uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ | ||
118 | uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ | ||
119 | uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ | ||
120 | uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ | ||
121 | uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ | ||
122 | uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ | ||
123 | uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ | ||
124 | uint32 PAD[40]; | ||
125 | uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ | ||
126 | uint32 PAD[7]; | ||
127 | |||
128 | /* DMA engines */ | ||
129 | volatile union { | ||
130 | pcmdma32_t pcm32; | ||
131 | sdiodma32_t sdiod32; | ||
132 | sdiodma64_t sdiod64; | ||
133 | } dma; | ||
134 | |||
135 | /* SDIO/PCMCIA CIS region */ | ||
136 | char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */ | ||
137 | |||
138 | /* PCMCIA function control registers */ | ||
139 | char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ | ||
140 | uint16 PAD[55]; | ||
141 | |||
142 | /* PCMCIA backplane access */ | ||
143 | uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ | ||
144 | uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ | ||
145 | uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ | ||
146 | uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ | ||
147 | uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ | ||
148 | uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ | ||
149 | uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ | ||
150 | uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ | ||
151 | uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ | ||
152 | uint16 PAD[31]; | ||
153 | |||
154 | /* sprom "size" & "blank" info */ | ||
155 | uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ | ||
156 | uint32 PAD[464]; | ||
157 | |||
158 | /* Sonics SiliconBackplane registers */ | ||
159 | sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ | ||
160 | } sdpcmd_regs_t; | ||
161 | |||
162 | /* corecontrol */ | ||
163 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | ||
164 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */ | ||
165 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | ||
166 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */ | ||
167 | #define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */ | ||
168 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */ | ||
169 | |||
170 | /* corestatus */ | ||
171 | #define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */ | ||
172 | #define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */ | ||
173 | #define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */ | ||
174 | |||
175 | #define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */ | ||
176 | #define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */ | ||
177 | #define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */ | ||
178 | #define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */ | ||
179 | |||
180 | /* intstatus */ | ||
181 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | ||
182 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | ||
183 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | ||
184 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | ||
185 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | ||
186 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | ||
187 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | ||
188 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | ||
189 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | ||
190 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | ||
191 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | ||
192 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | ||
193 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | ||
194 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | ||
195 | #define I_PC (1 << 10) /* descriptor error */ | ||
196 | #define I_PD (1 << 11) /* data error */ | ||
197 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | ||
198 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | ||
199 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | ||
200 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | ||
201 | #define I_RI (1 << 16) /* Receive Interrupt */ | ||
202 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | ||
203 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | ||
204 | #define I_XI (1 << 24) /* Transmit Interrupt */ | ||
205 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | ||
206 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | ||
207 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | ||
208 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | ||
209 | #define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */ | ||
210 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | ||
211 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | ||
212 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */ | ||
213 | #define I_DMA (I_RI | I_XI | I_ERRORS) | ||
214 | |||
215 | /* sbintstatus */ | ||
216 | #define I_SB_SERR (1 << 8) /* Backplane SError (write) */ | ||
217 | #define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */ | ||
218 | #define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */ | ||
219 | |||
220 | /* sdioaccess */ | ||
221 | #define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */ | ||
222 | #define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */ | ||
223 | #define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */ | ||
224 | #define SDA_WRITE 0x01000000 /* Write bit */ | ||
225 | #define SDA_READ 0x00000000 /* Write bit cleared for Read */ | ||
226 | #define SDA_BUSY 0x80000000 /* Busy bit */ | ||
227 | |||
228 | /* sdioaccess-accessible register address spaces */ | ||
229 | #define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */ | ||
230 | #define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */ | ||
231 | #define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */ | ||
232 | #define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */ | ||
233 | |||
234 | /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */ | ||
235 | #define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */ | ||
236 | #define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */ | ||
237 | #define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */ | ||
238 | #define SDA_DEVICECONTROL 0x009 /* DeviceControl */ | ||
239 | #define SDA_SBADDRLOW 0x00a /* SbAddrLow */ | ||
240 | #define SDA_SBADDRMID 0x00b /* SbAddrMid */ | ||
241 | #define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */ | ||
242 | #define SDA_FRAMECTRL 0x00d /* FrameCtrl */ | ||
243 | #define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */ | ||
244 | #define SDA_SDIOPULLUP 0x00f /* SdioPullUp */ | ||
245 | #define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */ | ||
246 | #define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */ | ||
247 | #define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */ | ||
248 | #define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */ | ||
249 | |||
250 | /* SDA_F2WATERMARK */ | ||
251 | #define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */ | ||
252 | |||
253 | /* SDA_SBADDRLOW */ | ||
254 | #define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */ | ||
255 | |||
256 | /* SDA_SBADDRMID */ | ||
257 | #define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */ | ||
258 | |||
259 | /* SDA_SBADDRHIGH */ | ||
260 | #define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */ | ||
261 | |||
262 | /* SDA_FRAMECTRL */ | ||
263 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | ||
264 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | ||
265 | #define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */ | ||
266 | #define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */ | ||
267 | |||
268 | /* pcmciaframectrl */ | ||
269 | #define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | ||
270 | #define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | ||
271 | |||
272 | /* intrcvlazy */ | ||
273 | #define IRL_TO_MASK 0x00ffffff /* timeout */ | ||
274 | #define IRL_FC_MASK 0xff000000 /* frame count */ | ||
275 | #define IRL_FC_SHIFT 24 /* frame count */ | ||
276 | |||
277 | /* rx header */ | ||
278 | typedef volatile struct { | ||
279 | uint16 len; | ||
280 | uint16 flags; | ||
281 | } sdpcmd_rxh_t; | ||
282 | |||
283 | /* rx header flags */ | ||
284 | #define RXF_CRC 0x0001 /* CRC error detected */ | ||
285 | #define RXF_WOOS 0x0002 /* write frame out of sync */ | ||
286 | #define RXF_WF_TERM 0x0004 /* write frame terminated */ | ||
287 | #define RXF_ABORT 0x0008 /* write frame aborted */ | ||
288 | #define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */ | ||
289 | |||
290 | /* HW frame tag */ | ||
291 | #define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */ | ||
292 | |||
293 | #endif /* _sbsdpcmdev_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sbsocram.h b/drivers/net/wireless/bcmdhd/include/sbsocram.h new file mode 100644 index 00000000000..1cba4223890 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sbsocram.h | |||
@@ -0,0 +1,186 @@ | |||
1 | /* | ||
2 | * BCM47XX Sonics SiliconBackplane embedded ram core | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: sbsocram.h,v 13.15 2009-10-02 16:55:44 Exp $ | ||
25 | */ | ||
26 | |||
27 | |||
28 | #ifndef _SBSOCRAM_H | ||
29 | #define _SBSOCRAM_H | ||
30 | |||
31 | #ifndef _LANGUAGE_ASSEMBLY | ||
32 | |||
33 | |||
34 | #ifndef PAD | ||
35 | #define _PADLINE(line) pad ## line | ||
36 | #define _XSTR(line) _PADLINE(line) | ||
37 | #define PAD _XSTR(__LINE__) | ||
38 | #endif | ||
39 | |||
40 | |||
41 | typedef volatile struct sbsocramregs { | ||
42 | uint32 coreinfo; | ||
43 | uint32 bwalloc; | ||
44 | uint32 extracoreinfo; | ||
45 | uint32 biststat; | ||
46 | uint32 bankidx; | ||
47 | uint32 standbyctrl; | ||
48 | |||
49 | uint32 errlogstatus; | ||
50 | uint32 errlogaddr; | ||
51 | |||
52 | uint32 cambankidx; | ||
53 | uint32 cambankstandbyctrl; | ||
54 | uint32 cambankpatchctrl; | ||
55 | uint32 cambankpatchtblbaseaddr; | ||
56 | uint32 cambankcmdreg; | ||
57 | uint32 cambankdatareg; | ||
58 | uint32 cambankmaskreg; | ||
59 | uint32 PAD[1]; | ||
60 | uint32 bankinfo; | ||
61 | uint32 PAD[15]; | ||
62 | uint32 extmemconfig; | ||
63 | uint32 extmemparitycsr; | ||
64 | uint32 extmemparityerrdata; | ||
65 | uint32 extmemparityerrcnt; | ||
66 | uint32 extmemwrctrlandsize; | ||
67 | uint32 PAD[84]; | ||
68 | uint32 workaround; | ||
69 | uint32 pwrctl; | ||
70 | uint32 PAD[133]; | ||
71 | uint32 sr_control; | ||
72 | uint32 sr_status; | ||
73 | uint32 sr_address; | ||
74 | uint32 sr_data; | ||
75 | } sbsocramregs_t; | ||
76 | |||
77 | #endif | ||
78 | |||
79 | |||
80 | #define SR_COREINFO 0x00 | ||
81 | #define SR_BWALLOC 0x04 | ||
82 | #define SR_BISTSTAT 0x0c | ||
83 | #define SR_BANKINDEX 0x10 | ||
84 | #define SR_BANKSTBYCTL 0x14 | ||
85 | #define SR_PWRCTL 0x1e8 | ||
86 | |||
87 | |||
88 | #define SRCI_PT_MASK 0x00070000 | ||
89 | #define SRCI_PT_SHIFT 16 | ||
90 | |||
91 | #define SRCI_PT_OCP_OCP 0 | ||
92 | #define SRCI_PT_AXI_OCP 1 | ||
93 | #define SRCI_PT_ARM7AHB_OCP 2 | ||
94 | #define SRCI_PT_CM3AHB_OCP 3 | ||
95 | #define SRCI_PT_AXI_AXI 4 | ||
96 | #define SRCI_PT_AHB_AXI 5 | ||
97 | |||
98 | #define SRCI_LSS_MASK 0x00f00000 | ||
99 | #define SRCI_LSS_SHIFT 20 | ||
100 | #define SRCI_LRS_MASK 0x0f000000 | ||
101 | #define SRCI_LRS_SHIFT 24 | ||
102 | |||
103 | |||
104 | #define SRCI_MS0_MASK 0xf | ||
105 | #define SR_MS0_BASE 16 | ||
106 | |||
107 | |||
108 | #define SRCI_ROMNB_MASK 0xf000 | ||
109 | #define SRCI_ROMNB_SHIFT 12 | ||
110 | #define SRCI_ROMBSZ_MASK 0xf00 | ||
111 | #define SRCI_ROMBSZ_SHIFT 8 | ||
112 | #define SRCI_SRNB_MASK 0xf0 | ||
113 | #define SRCI_SRNB_SHIFT 4 | ||
114 | #define SRCI_SRBSZ_MASK 0xf | ||
115 | #define SRCI_SRBSZ_SHIFT 0 | ||
116 | |||
117 | #define SR_BSZ_BASE 14 | ||
118 | |||
119 | |||
120 | #define SRSC_SBYOVR_MASK 0x80000000 | ||
121 | #define SRSC_SBYOVR_SHIFT 31 | ||
122 | #define SRSC_SBYOVRVAL_MASK 0x60000000 | ||
123 | #define SRSC_SBYOVRVAL_SHIFT 29 | ||
124 | #define SRSC_SBYEN_MASK 0x01000000 | ||
125 | #define SRSC_SBYEN_SHIFT 24 | ||
126 | |||
127 | |||
128 | #define SRPC_PMU_STBYDIS_MASK 0x00000010 | ||
129 | #define SRPC_PMU_STBYDIS_SHIFT 4 | ||
130 | #define SRPC_STBYOVRVAL_MASK 0x00000008 | ||
131 | #define SRPC_STBYOVRVAL_SHIFT 3 | ||
132 | #define SRPC_STBYOVR_MASK 0x00000007 | ||
133 | #define SRPC_STBYOVR_SHIFT 0 | ||
134 | |||
135 | |||
136 | #define SRECC_NUM_BANKS_MASK 0x000000F0 | ||
137 | #define SRECC_NUM_BANKS_SHIFT 4 | ||
138 | #define SRECC_BANKSIZE_MASK 0x0000000F | ||
139 | #define SRECC_BANKSIZE_SHIFT 0 | ||
140 | |||
141 | #define SRECC_BANKSIZE(value) (1 << (value)) | ||
142 | |||
143 | |||
144 | #define SRCBPC_PATCHENABLE 0x80000000 | ||
145 | |||
146 | #define SRP_ADDRESS 0x0001FFFC | ||
147 | #define SRP_VALID 0x8000 | ||
148 | |||
149 | |||
150 | #define SRCMD_WRITE 0x00020000 | ||
151 | #define SRCMD_READ 0x00010000 | ||
152 | #define SRCMD_DONE 0x80000000 | ||
153 | |||
154 | #define SRCMD_DONE_DLY 1000 | ||
155 | |||
156 | |||
157 | #define SOCRAM_BANKINFO_SZMASK 0x3f | ||
158 | #define SOCRAM_BANKIDX_ROM_MASK 0x100 | ||
159 | |||
160 | #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 | ||
161 | |||
162 | #define SOCRAM_MEMTYPE_RAM 0 | ||
163 | #define SOCRAM_MEMTYPE_R0M 1 | ||
164 | #define SOCRAM_MEMTYPE_DEVRAM 2 | ||
165 | |||
166 | #define SOCRAM_BANKINFO_REG 0x40 | ||
167 | #define SOCRAM_BANKIDX_REG 0x10 | ||
168 | #define SOCRAM_BANKINFO_STDBY_MASK 0x400 | ||
169 | #define SOCRAM_BANKINFO_STDBY_TIMER 0x800 | ||
170 | |||
171 | |||
172 | #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 | ||
173 | #define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 | ||
174 | #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 | ||
175 | #define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 | ||
176 | |||
177 | |||
178 | #define SOCRAM_DEVRAMBANK_MASK 0xF000 | ||
179 | #define SOCRAM_DEVRAMBANK_SHIFT 12 | ||
180 | |||
181 | |||
182 | #define SOCRAM_BANKINFO_SZBASE 8192 | ||
183 | #define SOCRAM_BANKSIZE_SHIFT 13 | ||
184 | |||
185 | |||
186 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sdio.h b/drivers/net/wireless/bcmdhd/include/sdio.h new file mode 100644 index 00000000000..ca932266a1b --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sdio.h | |||
@@ -0,0 +1,611 @@ | |||
1 | /* | ||
2 | * SDIO spec header file | ||
3 | * Protocol and standard (common) device definitions | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: sdio.h,v 13.27.14.1 2010-09-07 13:37:45 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _SDIO_H | ||
29 | #define _SDIO_H | ||
30 | |||
31 | |||
32 | /* CCCR structure for function 0 */ | ||
33 | typedef volatile struct { | ||
34 | uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ | ||
35 | uint8 sd_rev; /* RO, sd spec revision */ | ||
36 | uint8 io_en; /* I/O enable */ | ||
37 | uint8 io_rdy; /* I/O ready reg */ | ||
38 | uint8 intr_ctl; /* Master and per function interrupt enable control */ | ||
39 | uint8 intr_status; /* RO, interrupt pending status */ | ||
40 | uint8 io_abort; /* read/write abort or reset all functions */ | ||
41 | uint8 bus_inter; /* bus interface control */ | ||
42 | uint8 capability; /* RO, card capability */ | ||
43 | |||
44 | uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ | ||
45 | uint8 cis_base_mid; | ||
46 | uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ | ||
47 | |||
48 | /* suspend/resume registers */ | ||
49 | uint8 bus_suspend; /* 0xC */ | ||
50 | uint8 func_select; /* 0xD */ | ||
51 | uint8 exec_flag; /* 0xE */ | ||
52 | uint8 ready_flag; /* 0xF */ | ||
53 | |||
54 | uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ | ||
55 | |||
56 | uint8 power_control; /* 0x12 (SDIO version 1.10) */ | ||
57 | |||
58 | uint8 speed_control; /* 0x13 */ | ||
59 | } sdio_regs_t; | ||
60 | |||
61 | /* SDIO Device CCCR offsets */ | ||
62 | #define SDIOD_CCCR_REV 0x00 | ||
63 | #define SDIOD_CCCR_SDREV 0x01 | ||
64 | #define SDIOD_CCCR_IOEN 0x02 | ||
65 | #define SDIOD_CCCR_IORDY 0x03 | ||
66 | #define SDIOD_CCCR_INTEN 0x04 | ||
67 | #define SDIOD_CCCR_INTPEND 0x05 | ||
68 | #define SDIOD_CCCR_IOABORT 0x06 | ||
69 | #define SDIOD_CCCR_BICTRL 0x07 | ||
70 | #define SDIOD_CCCR_CAPABLITIES 0x08 | ||
71 | #define SDIOD_CCCR_CISPTR_0 0x09 | ||
72 | #define SDIOD_CCCR_CISPTR_1 0x0A | ||
73 | #define SDIOD_CCCR_CISPTR_2 0x0B | ||
74 | #define SDIOD_CCCR_BUSSUSP 0x0C | ||
75 | #define SDIOD_CCCR_FUNCSEL 0x0D | ||
76 | #define SDIOD_CCCR_EXECFLAGS 0x0E | ||
77 | #define SDIOD_CCCR_RDYFLAGS 0x0F | ||
78 | #define SDIOD_CCCR_BLKSIZE_0 0x10 | ||
79 | #define SDIOD_CCCR_BLKSIZE_1 0x11 | ||
80 | #define SDIOD_CCCR_POWER_CONTROL 0x12 | ||
81 | #define SDIOD_CCCR_SPEED_CONTROL 0x13 | ||
82 | #define SDIOD_CCCR_UHSI_SUPPORT 0x14 | ||
83 | #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 | ||
84 | #define SDIOD_CCCR_INTR_EXTN 0x16 | ||
85 | |||
86 | /* Broadcom extensions (corerev >= 1) */ | ||
87 | #define SDIOD_CCCR_BRCM_SEPINT 0xf2 | ||
88 | |||
89 | /* cccr_sdio_rev */ | ||
90 | #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ | ||
91 | #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ | ||
92 | |||
93 | /* sd_rev */ | ||
94 | #define SD_REV_PHY_MASK 0x0f /* SD format version number */ | ||
95 | |||
96 | /* io_en */ | ||
97 | #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ | ||
98 | #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ | ||
99 | |||
100 | /* io_rdys */ | ||
101 | #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ | ||
102 | #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ | ||
103 | |||
104 | /* intr_ctl */ | ||
105 | #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ | ||
106 | #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ | ||
107 | #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ | ||
108 | |||
109 | /* intr_status */ | ||
110 | #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ | ||
111 | #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ | ||
112 | |||
113 | /* io_abort */ | ||
114 | #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ | ||
115 | #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ | ||
116 | |||
117 | /* bus_inter */ | ||
118 | #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ | ||
119 | #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ | ||
120 | #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ | ||
121 | #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ | ||
122 | #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ | ||
123 | #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ | ||
124 | |||
125 | /* capability */ | ||
126 | #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ | ||
127 | #define SDIO_CAP_LSC 0x40 /* low speed card */ | ||
128 | #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ | ||
129 | #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ | ||
130 | #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ | ||
131 | #define SDIO_CAP_SRW 0x04 /* support read wait */ | ||
132 | #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ | ||
133 | #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ | ||
134 | |||
135 | /* power_control */ | ||
136 | #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ | ||
137 | #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ | ||
138 | |||
139 | /* speed_control (control device entry into high-speed clocking mode) */ | ||
140 | #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ | ||
141 | #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ | ||
142 | |||
143 | /* for setting bus speed in card: 0x13h */ | ||
144 | #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) | ||
145 | #define SDIO_BUS_SPEED_UHSISEL_S 1 | ||
146 | |||
147 | /* for getting bus speed cap in card: 0x14h */ | ||
148 | #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) | ||
149 | #define SDIO_BUS_SPEED_UHSICAP_S 0 | ||
150 | |||
151 | /* for getting driver type CAP in card: 0x15h */ | ||
152 | #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) | ||
153 | #define SDIO_BUS_DRVR_TYPE_CAP_S 0 | ||
154 | |||
155 | /* for setting driver type selection in card: 0x15h */ | ||
156 | #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) | ||
157 | #define SDIO_BUS_DRVR_TYPE_SEL_S 4 | ||
158 | |||
159 | /* for getting async int support in card: 0x16h */ | ||
160 | #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) | ||
161 | #define SDIO_BUS_ASYNCINT_CAP_S 0 | ||
162 | |||
163 | /* for setting async int selection in card: 0x16h */ | ||
164 | #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) | ||
165 | #define SDIO_BUS_ASYNCINT_SEL_S 1 | ||
166 | |||
167 | /* brcm sepint */ | ||
168 | #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ | ||
169 | #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ | ||
170 | #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ | ||
171 | |||
172 | /* FBR structure for function 1-7, FBR addresses and register offsets */ | ||
173 | typedef volatile struct { | ||
174 | uint8 devctr; /* device interface, CSA control */ | ||
175 | uint8 ext_dev; /* extended standard I/O device type code */ | ||
176 | uint8 pwr_sel; /* power selection support */ | ||
177 | uint8 PAD[6]; /* reserved */ | ||
178 | |||
179 | uint8 cis_low; /* CIS LSB */ | ||
180 | uint8 cis_mid; | ||
181 | uint8 cis_high; /* CIS MSB */ | ||
182 | uint8 csa_low; /* code storage area, LSB */ | ||
183 | uint8 csa_mid; | ||
184 | uint8 csa_high; /* code storage area, MSB */ | ||
185 | uint8 csa_dat_win; /* data access window to function */ | ||
186 | |||
187 | uint8 fnx_blk_size[2]; /* block size, little endian */ | ||
188 | } sdio_fbr_t; | ||
189 | |||
190 | /* Maximum number of I/O funcs */ | ||
191 | #define SDIOD_MAX_IOFUNCS 7 | ||
192 | |||
193 | /* SDIO Device FBR Start Address */ | ||
194 | #define SDIOD_FBR_STARTADDR 0x100 | ||
195 | |||
196 | /* SDIO Device FBR Size */ | ||
197 | #define SDIOD_FBR_SIZE 0x100 | ||
198 | |||
199 | /* Macro to calculate FBR register base */ | ||
200 | #define SDIOD_FBR_BASE(n) ((n) * 0x100) | ||
201 | |||
202 | /* Function register offsets */ | ||
203 | #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ | ||
204 | #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ | ||
205 | #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ | ||
206 | |||
207 | /* SDIO Function CIS ptr offset */ | ||
208 | #define SDIOD_FBR_CISPTR_0 0x09 | ||
209 | #define SDIOD_FBR_CISPTR_1 0x0A | ||
210 | #define SDIOD_FBR_CISPTR_2 0x0B | ||
211 | |||
212 | /* Code Storage Area pointer */ | ||
213 | #define SDIOD_FBR_CSA_ADDR_0 0x0C | ||
214 | #define SDIOD_FBR_CSA_ADDR_1 0x0D | ||
215 | #define SDIOD_FBR_CSA_ADDR_2 0x0E | ||
216 | #define SDIOD_FBR_CSA_DATA 0x0F | ||
217 | |||
218 | /* SDIO Function I/O Block Size */ | ||
219 | #define SDIOD_FBR_BLKSIZE_0 0x10 | ||
220 | #define SDIOD_FBR_BLKSIZE_1 0x11 | ||
221 | |||
222 | /* devctr */ | ||
223 | #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ | ||
224 | #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ | ||
225 | #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ | ||
226 | /* interface codes */ | ||
227 | #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ | ||
228 | #define SDIOD_DIC_UART 1 | ||
229 | #define SDIOD_DIC_BLUETOOTH_A 2 | ||
230 | #define SDIOD_DIC_BLUETOOTH_B 3 | ||
231 | #define SDIOD_DIC_GPS 4 | ||
232 | #define SDIOD_DIC_CAMERA 5 | ||
233 | #define SDIOD_DIC_PHS 6 | ||
234 | #define SDIOD_DIC_WLAN 7 | ||
235 | #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ | ||
236 | |||
237 | /* pwr_sel */ | ||
238 | #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ | ||
239 | #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ | ||
240 | |||
241 | /* misc defines */ | ||
242 | #define SDIO_FUNC_0 0 | ||
243 | #define SDIO_FUNC_1 1 | ||
244 | #define SDIO_FUNC_2 2 | ||
245 | #define SDIO_FUNC_3 3 | ||
246 | #define SDIO_FUNC_4 4 | ||
247 | #define SDIO_FUNC_5 5 | ||
248 | #define SDIO_FUNC_6 6 | ||
249 | #define SDIO_FUNC_7 7 | ||
250 | |||
251 | #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ | ||
252 | #define SD_CARD_TYPE_IO 1 /* IO only card */ | ||
253 | #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ | ||
254 | #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ | ||
255 | |||
256 | #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ | ||
257 | #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ | ||
258 | |||
259 | /* Card registers: status bit position */ | ||
260 | #define CARDREG_STATUS_BIT_OUTOFRANGE 31 | ||
261 | #define CARDREG_STATUS_BIT_COMCRCERROR 23 | ||
262 | #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 | ||
263 | #define CARDREG_STATUS_BIT_ERROR 19 | ||
264 | #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 | ||
265 | #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 | ||
266 | #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 | ||
267 | #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 | ||
268 | #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 | ||
269 | |||
270 | |||
271 | |||
272 | #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ | ||
273 | #define SD_CMD_SEND_OPCOND 1 | ||
274 | #define SD_CMD_MMC_SET_RCA 3 | ||
275 | #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ | ||
276 | #define SD_CMD_SELECT_DESELECT_CARD 7 | ||
277 | #define SD_CMD_SEND_CSD 9 | ||
278 | #define SD_CMD_SEND_CID 10 | ||
279 | #define SD_CMD_STOP_TRANSMISSION 12 | ||
280 | #define SD_CMD_SEND_STATUS 13 | ||
281 | #define SD_CMD_GO_INACTIVE_STATE 15 | ||
282 | #define SD_CMD_SET_BLOCKLEN 16 | ||
283 | #define SD_CMD_READ_SINGLE_BLOCK 17 | ||
284 | #define SD_CMD_READ_MULTIPLE_BLOCK 18 | ||
285 | #define SD_CMD_WRITE_BLOCK 24 | ||
286 | #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 | ||
287 | #define SD_CMD_PROGRAM_CSD 27 | ||
288 | #define SD_CMD_SET_WRITE_PROT 28 | ||
289 | #define SD_CMD_CLR_WRITE_PROT 29 | ||
290 | #define SD_CMD_SEND_WRITE_PROT 30 | ||
291 | #define SD_CMD_ERASE_WR_BLK_START 32 | ||
292 | #define SD_CMD_ERASE_WR_BLK_END 33 | ||
293 | #define SD_CMD_ERASE 38 | ||
294 | #define SD_CMD_LOCK_UNLOCK 42 | ||
295 | #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ | ||
296 | #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ | ||
297 | #define SD_CMD_APP_CMD 55 | ||
298 | #define SD_CMD_GEN_CMD 56 | ||
299 | #define SD_CMD_READ_OCR 58 | ||
300 | #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ | ||
301 | #define SD_ACMD_SD_STATUS 13 | ||
302 | #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 | ||
303 | #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 | ||
304 | #define SD_ACMD_SD_SEND_OP_COND 41 | ||
305 | #define SD_ACMD_SET_CLR_CARD_DETECT 42 | ||
306 | #define SD_ACMD_SEND_SCR 51 | ||
307 | |||
308 | /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ | ||
309 | #define SD_IO_OP_READ 0 /* Read_Write: Read */ | ||
310 | #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ | ||
311 | #define SD_IO_RW_NORMAL 0 /* no RAW */ | ||
312 | #define SD_IO_RW_RAW 1 /* RAW */ | ||
313 | #define SD_IO_BYTE_MODE 0 /* Byte Mode */ | ||
314 | #define SD_IO_BLOCK_MODE 1 /* BlockMode */ | ||
315 | #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ | ||
316 | #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ | ||
317 | |||
318 | /* build SD_CMD_IO_RW_DIRECT Argument */ | ||
319 | #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ | ||
320 | ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ | ||
321 | (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) | ||
322 | |||
323 | /* build SD_CMD_IO_RW_EXTENDED Argument */ | ||
324 | #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ | ||
325 | ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ | ||
326 | (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) | ||
327 | |||
328 | /* SDIO response parameters */ | ||
329 | #define SD_RSP_NO_NONE 0 | ||
330 | #define SD_RSP_NO_1 1 | ||
331 | #define SD_RSP_NO_2 2 | ||
332 | #define SD_RSP_NO_3 3 | ||
333 | #define SD_RSP_NO_4 4 | ||
334 | #define SD_RSP_NO_5 5 | ||
335 | #define SD_RSP_NO_6 6 | ||
336 | |||
337 | /* Modified R6 response (to CMD3) */ | ||
338 | #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 | ||
339 | #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 | ||
340 | #define SD_RSP_MR6_ERROR 0x2000 | ||
341 | |||
342 | /* Modified R1 in R4 Response (to CMD5) */ | ||
343 | #define SD_RSP_MR1_SBIT 0x80 | ||
344 | #define SD_RSP_MR1_PARAMETER_ERROR 0x40 | ||
345 | #define SD_RSP_MR1_RFU5 0x20 | ||
346 | #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 | ||
347 | #define SD_RSP_MR1_COM_CRC_ERROR 0x08 | ||
348 | #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 | ||
349 | #define SD_RSP_MR1_RFU1 0x02 | ||
350 | #define SD_RSP_MR1_IDLE_STATE 0x01 | ||
351 | |||
352 | /* R5 response (to CMD52 and CMD53) */ | ||
353 | #define SD_RSP_R5_COM_CRC_ERROR 0x80 | ||
354 | #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 | ||
355 | #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 | ||
356 | #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 | ||
357 | #define SD_RSP_R5_ERROR 0x08 | ||
358 | #define SD_RSP_R5_RFU 0x04 | ||
359 | #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 | ||
360 | #define SD_RSP_R5_OUT_OF_RANGE 0x01 | ||
361 | |||
362 | #define SD_RSP_R5_ERRBITS 0xCB | ||
363 | |||
364 | |||
365 | /* ------------------------------------------------ | ||
366 | * SDIO Commands and responses | ||
367 | * | ||
368 | * I/O only commands are: | ||
369 | * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 | ||
370 | * ------------------------------------------------ | ||
371 | */ | ||
372 | |||
373 | /* SDIO Commands */ | ||
374 | #define SDIOH_CMD_0 0 | ||
375 | #define SDIOH_CMD_3 3 | ||
376 | #define SDIOH_CMD_5 5 | ||
377 | #define SDIOH_CMD_7 7 | ||
378 | #define SDIOH_CMD_11 11 | ||
379 | #define SDIOH_CMD_14 14 | ||
380 | #define SDIOH_CMD_15 15 | ||
381 | #define SDIOH_CMD_19 19 | ||
382 | #define SDIOH_CMD_52 52 | ||
383 | #define SDIOH_CMD_53 53 | ||
384 | #define SDIOH_CMD_59 59 | ||
385 | |||
386 | /* SDIO Command Responses */ | ||
387 | #define SDIOH_RSP_NONE 0 | ||
388 | #define SDIOH_RSP_R1 1 | ||
389 | #define SDIOH_RSP_R2 2 | ||
390 | #define SDIOH_RSP_R3 3 | ||
391 | #define SDIOH_RSP_R4 4 | ||
392 | #define SDIOH_RSP_R5 5 | ||
393 | #define SDIOH_RSP_R6 6 | ||
394 | |||
395 | /* | ||
396 | * SDIO Response Error flags | ||
397 | */ | ||
398 | #define SDIOH_RSP5_ERROR_FLAGS 0xCB | ||
399 | |||
400 | /* ------------------------------------------------ | ||
401 | * SDIO Command structures. I/O only commands are: | ||
402 | * | ||
403 | * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 | ||
404 | * ------------------------------------------------ | ||
405 | */ | ||
406 | |||
407 | #define CMD5_OCR_M BITFIELD_MASK(24) | ||
408 | #define CMD5_OCR_S 0 | ||
409 | |||
410 | #define CMD5_S18R_M BITFIELD_MASK(1) | ||
411 | #define CMD5_S18R_S 24 | ||
412 | |||
413 | #define CMD7_RCA_M BITFIELD_MASK(16) | ||
414 | #define CMD7_RCA_S 16 | ||
415 | #define CMD14_RCA_M BITFIELD_MASK(16) | ||
416 | #define CMD14_RCA_S 16 | ||
417 | #define CMD14_SLEEP_M BITFIELD_MASK(1) | ||
418 | #define CMD14_SLEEP_S 15 | ||
419 | |||
420 | #define CMD_15_RCA_M BITFIELD_MASK(16) | ||
421 | #define CMD_15_RCA_S 16 | ||
422 | |||
423 | #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 | ||
424 | */ | ||
425 | #define CMD52_DATA_S 0 | ||
426 | #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ | ||
427 | #define CMD52_REG_ADDR_S 9 | ||
428 | #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ | ||
429 | #define CMD52_RAW_S 27 | ||
430 | #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ | ||
431 | #define CMD52_FUNCTION_S 28 | ||
432 | #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ | ||
433 | #define CMD52_RW_FLAG_S 31 | ||
434 | |||
435 | |||
436 | #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ | ||
437 | #define CMD53_BYTE_BLK_CNT_S 0 | ||
438 | #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ | ||
439 | #define CMD53_REG_ADDR_S 9 | ||
440 | #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ | ||
441 | #define CMD53_OP_CODE_S 26 | ||
442 | #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ | ||
443 | #define CMD53_BLK_MODE_S 27 | ||
444 | #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ | ||
445 | #define CMD53_FUNCTION_S 28 | ||
446 | #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ | ||
447 | #define CMD53_RW_FLAG_S 31 | ||
448 | |||
449 | /* ------------------------------------------------------ | ||
450 | * SDIO Command Response structures for SD1 and SD4 modes | ||
451 | * ----------------------------------------------------- | ||
452 | */ | ||
453 | #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ | ||
454 | #define RSP4_IO_OCR_S 0 | ||
455 | |||
456 | #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */ | ||
457 | #define RSP4_S18A_S 24 | ||
458 | |||
459 | #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ | ||
460 | #define RSP4_STUFF_S 24 | ||
461 | #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ | ||
462 | #define RSP4_MEM_PRESENT_S 27 | ||
463 | #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ | ||
464 | #define RSP4_NUM_FUNCS_S 28 | ||
465 | #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ | ||
466 | #define RSP4_CARD_READY_S 31 | ||
467 | |||
468 | #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] | ||
469 | */ | ||
470 | #define RSP6_STATUS_S 0 | ||
471 | #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ | ||
472 | #define RSP6_IO_RCA_S 16 | ||
473 | |||
474 | #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ | ||
475 | #define RSP1_AKE_SEQ_ERROR_S 3 | ||
476 | #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ | ||
477 | #define RSP1_APP_CMD_S 5 | ||
478 | #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ | ||
479 | #define RSP1_READY_FOR_DATA_S 8 | ||
480 | #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card | ||
481 | * when Cmd was received | ||
482 | */ | ||
483 | #define RSP1_CURR_STATE_S 9 | ||
484 | #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ | ||
485 | #define RSP1_EARSE_RESET_S 13 | ||
486 | #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ | ||
487 | #define RSP1_CARD_ECC_DISABLE_S 14 | ||
488 | #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ | ||
489 | #define RSP1_WP_ERASE_SKIP_S 15 | ||
490 | #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits | ||
491 | * of CSD | ||
492 | */ | ||
493 | #define RSP1_CID_CSD_OVERW_S 16 | ||
494 | #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ | ||
495 | #define RSP1_ERROR_S 19 | ||
496 | #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ | ||
497 | #define RSP1_CC_ERROR_S 20 | ||
498 | #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed | ||
499 | * to correct data | ||
500 | */ | ||
501 | #define RSP1_CARD_ECC_FAILED_S 21 | ||
502 | #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ | ||
503 | #define RSP1_ILLEGAL_CMD_S 22 | ||
504 | #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed | ||
505 | */ | ||
506 | #define RSP1_COM_CRC_ERROR_S 23 | ||
507 | #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ | ||
508 | #define RSP1_LOCK_UNLOCK_FAIL_S 24 | ||
509 | #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ | ||
510 | #define RSP1_CARD_LOCKED_S 25 | ||
511 | #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program | ||
512 | * write-protected blocks | ||
513 | */ | ||
514 | #define RSP1_WP_VIOLATION_S 26 | ||
515 | #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ | ||
516 | #define RSP1_ERASE_PARAM_S 27 | ||
517 | #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ | ||
518 | #define RSP1_ERASE_SEQ_ERR_S 28 | ||
519 | #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ | ||
520 | #define RSP1_BLK_LEN_ERR_S 29 | ||
521 | #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ | ||
522 | #define RSP1_ADDR_ERR_S 30 | ||
523 | #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ | ||
524 | #define RSP1_OUT_OF_RANGE_S 31 | ||
525 | |||
526 | |||
527 | #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ | ||
528 | #define RSP5_DATA_S 0 | ||
529 | #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ | ||
530 | #define RSP5_FLAGS_S 8 | ||
531 | #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ | ||
532 | #define RSP5_STUFF_S 16 | ||
533 | |||
534 | /* ---------------------------------------------- | ||
535 | * SDIO Command Response structures for SPI mode | ||
536 | * ---------------------------------------------- | ||
537 | */ | ||
538 | #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ | ||
539 | #define SPIRSP4_IO_OCR_S 0 | ||
540 | #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ | ||
541 | #define SPIRSP4_STUFF_S 16 | ||
542 | #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ | ||
543 | #define SPIRSP4_MEM_PRESENT_S 19 | ||
544 | #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ | ||
545 | #define SPIRSP4_NUM_FUNCS_S 20 | ||
546 | #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ | ||
547 | #define SPIRSP4_CARD_READY_S 23 | ||
548 | #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ | ||
549 | #define SPIRSP4_IDLE_STATE_S 24 | ||
550 | #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ | ||
551 | #define SPIRSP4_ILLEGAL_CMD_S 26 | ||
552 | #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ | ||
553 | #define SPIRSP4_COM_CRC_ERROR_S 27 | ||
554 | #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error | ||
555 | */ | ||
556 | #define SPIRSP4_FUNC_NUM_ERROR_S 28 | ||
557 | #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ | ||
558 | #define SPIRSP4_PARAM_ERROR_S 30 | ||
559 | #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ | ||
560 | #define SPIRSP4_START_BIT_S 31 | ||
561 | |||
562 | #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ | ||
563 | #define SPIRSP5_DATA_S 16 | ||
564 | #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ | ||
565 | #define SPIRSP5_IDLE_STATE_S 24 | ||
566 | #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ | ||
567 | #define SPIRSP5_ILLEGAL_CMD_S 26 | ||
568 | #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ | ||
569 | #define SPIRSP5_COM_CRC_ERROR_S 27 | ||
570 | #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error | ||
571 | */ | ||
572 | #define SPIRSP5_FUNC_NUM_ERROR_S 28 | ||
573 | #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ | ||
574 | #define SPIRSP5_PARAM_ERROR_S 30 | ||
575 | #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ | ||
576 | #define SPIRSP5_START_BIT_S 31 | ||
577 | |||
578 | /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ | ||
579 | #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error | ||
580 | */ | ||
581 | #define RSP6STAT_AKE_SEQ_ERROR_S 3 | ||
582 | #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ | ||
583 | #define RSP6STAT_APP_CMD_S 5 | ||
584 | #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data | ||
585 | * (buff empty) | ||
586 | */ | ||
587 | #define RSP6STAT_READY_FOR_DATA_S 8 | ||
588 | #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at | ||
589 | * Cmd reception | ||
590 | */ | ||
591 | #define RSP6STAT_CURR_STATE_S 9 | ||
592 | #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 | ||
593 | */ | ||
594 | #define RSP6STAT_ERROR_S 13 | ||
595 | #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for | ||
596 | * card state Bit 22 | ||
597 | */ | ||
598 | #define RSP6STAT_ILLEGAL_CMD_S 14 | ||
599 | #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command | ||
600 | * failed Bit 23 | ||
601 | */ | ||
602 | #define RSP6STAT_COM_CRC_ERROR_S 15 | ||
603 | |||
604 | #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ | ||
605 | #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE | ||
606 | |||
607 | /* command issue options */ | ||
608 | #define CMD_OPTION_DEFAULT 0 | ||
609 | #define CMD_OPTION_TUNING 1 | ||
610 | |||
611 | #endif /* _SDIO_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sdioh.h b/drivers/net/wireless/bcmdhd/include/sdioh.h new file mode 100644 index 00000000000..3d37c7a7e30 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sdioh.h | |||
@@ -0,0 +1,412 @@ | |||
1 | /* | ||
2 | * SDIO Host Controller Spec header file | ||
3 | * Register map and definitions for the Standard Host Controller | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: sdioh.h,v 13.17.2.3 2011-01-08 05:28:21 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _SDIOH_H | ||
29 | #define _SDIOH_H | ||
30 | |||
31 | #define SD_SysAddr 0x000 | ||
32 | #define SD_BlockSize 0x004 | ||
33 | #define SD_BlockCount 0x006 | ||
34 | #define SD_Arg0 0x008 | ||
35 | #define SD_Arg1 0x00A | ||
36 | #define SD_TransferMode 0x00C | ||
37 | #define SD_Command 0x00E | ||
38 | #define SD_Response0 0x010 | ||
39 | #define SD_Response1 0x012 | ||
40 | #define SD_Response2 0x014 | ||
41 | #define SD_Response3 0x016 | ||
42 | #define SD_Response4 0x018 | ||
43 | #define SD_Response5 0x01A | ||
44 | #define SD_Response6 0x01C | ||
45 | #define SD_Response7 0x01E | ||
46 | #define SD_BufferDataPort0 0x020 | ||
47 | #define SD_BufferDataPort1 0x022 | ||
48 | #define SD_PresentState 0x024 | ||
49 | #define SD_HostCntrl 0x028 | ||
50 | #define SD_PwrCntrl 0x029 | ||
51 | #define SD_BlockGapCntrl 0x02A | ||
52 | #define SD_WakeupCntrl 0x02B | ||
53 | #define SD_ClockCntrl 0x02C | ||
54 | #define SD_TimeoutCntrl 0x02E | ||
55 | #define SD_SoftwareReset 0x02F | ||
56 | #define SD_IntrStatus 0x030 | ||
57 | #define SD_ErrorIntrStatus 0x032 | ||
58 | #define SD_IntrStatusEnable 0x034 | ||
59 | #define SD_ErrorIntrStatusEnable 0x036 | ||
60 | #define SD_IntrSignalEnable 0x038 | ||
61 | #define SD_ErrorIntrSignalEnable 0x03A | ||
62 | #define SD_CMD12ErrorStatus 0x03C | ||
63 | #define SD_Capabilities 0x040 | ||
64 | #define SD_Capabilities3 0x044 | ||
65 | #define SD_MaxCurCap 0x048 | ||
66 | #define SD_MaxCurCap_Reserved 0x04C | ||
67 | #define SD_ADMA_ErrStatus 0x054 | ||
68 | #define SD_ADMA_SysAddr 0x58 | ||
69 | #define SD_SlotInterruptStatus 0x0FC | ||
70 | #define SD_HostControllerVersion 0x0FE | ||
71 | |||
72 | /* SD specific registers in PCI config space */ | ||
73 | #define SD_SlotInfo 0x40 | ||
74 | |||
75 | /* HC 3.0 specific registers and offsets */ | ||
76 | #define SD3_HostCntrl2 0x03E | ||
77 | /* preset regsstart and count */ | ||
78 | #define SD3_PresetValStart 0x060 | ||
79 | #define SD3_PresetValCount 8 | ||
80 | /* preset-indiv regs */ | ||
81 | #define SD3_PresetVal_init 0x060 | ||
82 | #define SD3_PresetVal_default 0x062 | ||
83 | #define SD3_PresetVal_HS 0x064 | ||
84 | #define SD3_PresetVal_SDR12 0x066 | ||
85 | #define SD3_PresetVal_SDR25 0x068 | ||
86 | #define SD3_PresetVal_SDR50 0x06a | ||
87 | #define SD3_PresetVal_SDR104 0x06c | ||
88 | #define SD3_PresetVal_DDR50 0x06e | ||
89 | |||
90 | /* preset value indices */ | ||
91 | #define SD3_PRESETVAL_INITIAL_IX 0 | ||
92 | #define SD3_PRESETVAL_DESPEED_IX 1 | ||
93 | #define SD3_PRESETVAL_HISPEED_IX 2 | ||
94 | #define SD3_PRESETVAL_SDR12_IX 3 | ||
95 | #define SD3_PRESETVAL_SDR25_IX 4 | ||
96 | #define SD3_PRESETVAL_SDR50_IX 5 | ||
97 | #define SD3_PRESETVAL_SDR104_IX 6 | ||
98 | #define SD3_PRESETVAL_DDR50_IX 7 | ||
99 | |||
100 | /* SD_Capabilities reg (0x040) */ | ||
101 | #define CAP_TO_CLKFREQ_M BITFIELD_MASK(6) | ||
102 | #define CAP_TO_CLKFREQ_S 0 | ||
103 | #define CAP_TO_CLKUNIT_M BITFIELD_MASK(1) | ||
104 | #define CAP_TO_CLKUNIT_S 7 | ||
105 | /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2 | ||
106 | bits are reserved. going ahead with 8 bits, as it is req for 3.0 | ||
107 | */ | ||
108 | #define CAP_BASECLK_M BITFIELD_MASK(8) | ||
109 | #define CAP_BASECLK_S 8 | ||
110 | #define CAP_MAXBLOCK_M BITFIELD_MASK(2) | ||
111 | #define CAP_MAXBLOCK_S 16 | ||
112 | #define CAP_ADMA2_M BITFIELD_MASK(1) | ||
113 | #define CAP_ADMA2_S 19 | ||
114 | #define CAP_ADMA1_M BITFIELD_MASK(1) | ||
115 | #define CAP_ADMA1_S 20 | ||
116 | #define CAP_HIGHSPEED_M BITFIELD_MASK(1) | ||
117 | #define CAP_HIGHSPEED_S 21 | ||
118 | #define CAP_DMA_M BITFIELD_MASK(1) | ||
119 | #define CAP_DMA_S 22 | ||
120 | #define CAP_SUSPEND_M BITFIELD_MASK(1) | ||
121 | #define CAP_SUSPEND_S 23 | ||
122 | #define CAP_VOLT_3_3_M BITFIELD_MASK(1) | ||
123 | #define CAP_VOLT_3_3_S 24 | ||
124 | #define CAP_VOLT_3_0_M BITFIELD_MASK(1) | ||
125 | #define CAP_VOLT_3_0_S 25 | ||
126 | #define CAP_VOLT_1_8_M BITFIELD_MASK(1) | ||
127 | #define CAP_VOLT_1_8_S 26 | ||
128 | #define CAP_64BIT_HOST_M BITFIELD_MASK(1) | ||
129 | #define CAP_64BIT_HOST_S 28 | ||
130 | |||
131 | #define SDIO_OCR_READ_FAIL (2) | ||
132 | |||
133 | |||
134 | #define CAP_ASYNCINT_SUP_M BITFIELD_MASK(1) | ||
135 | #define CAP_ASYNCINT_SUP_S 29 | ||
136 | |||
137 | #define CAP_SLOTTYPE_M BITFIELD_MASK(2) | ||
138 | #define CAP_SLOTTYPE_S 30 | ||
139 | |||
140 | #define CAP3_MSBits_OFFSET (32) | ||
141 | /* note: following are caps MSB32 bits. | ||
142 | So the bits start from 0, instead of 32. that is why | ||
143 | CAP3_MSBits_OFFSET is subtracted. | ||
144 | */ | ||
145 | #define CAP3_SDR50_SUP_M BITFIELD_MASK(1) | ||
146 | #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET) | ||
147 | |||
148 | #define CAP3_SDR104_SUP_M BITFIELD_MASK(1) | ||
149 | #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET) | ||
150 | |||
151 | #define CAP3_DDR50_SUP_M BITFIELD_MASK(1) | ||
152 | #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET) | ||
153 | |||
154 | /* for knowing the clk caps in a single read */ | ||
155 | #define CAP3_30CLKCAP_M BITFIELD_MASK(3) | ||
156 | #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET) | ||
157 | |||
158 | #define CAP3_DRIVTYPE_A_M BITFIELD_MASK(1) | ||
159 | #define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET) | ||
160 | |||
161 | #define CAP3_DRIVTYPE_C_M BITFIELD_MASK(1) | ||
162 | #define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET) | ||
163 | |||
164 | #define CAP3_DRIVTYPE_D_M BITFIELD_MASK(1) | ||
165 | #define CAP3_DRIVTYPE_D_S (38 - CAP3_MSBits_OFFSET) | ||
166 | |||
167 | #define CAP3_RETUNING_TC_M BITFIELD_MASK(4) | ||
168 | #define CAP3_RETUNING_TC_S (40 - CAP3_MSBits_OFFSET) | ||
169 | |||
170 | #define CAP3_TUNING_SDR50_M BITFIELD_MASK(1) | ||
171 | #define CAP3_TUNING_SDR50_S (45 - CAP3_MSBits_OFFSET) | ||
172 | |||
173 | #define CAP3_RETUNING_MODES_M BITFIELD_MASK(2) | ||
174 | #define CAP3_RETUNING_MODES_S (46 - CAP3_MSBits_OFFSET) | ||
175 | |||
176 | #define CAP3_CLK_MULT_M BITFIELD_MASK(8) | ||
177 | #define CAP3_CLK_MULT_S (48 - CAP3_MSBits_OFFSET) | ||
178 | |||
179 | #define PRESET_DRIVR_SELECT_M BITFIELD_MASK(2) | ||
180 | #define PRESET_DRIVR_SELECT_S 14 | ||
181 | |||
182 | #define PRESET_CLK_DIV_M BITFIELD_MASK(10) | ||
183 | #define PRESET_CLK_DIV_S 0 | ||
184 | |||
185 | /* SD_MaxCurCap reg (0x048) */ | ||
186 | #define CAP_CURR_3_3_M BITFIELD_MASK(8) | ||
187 | #define CAP_CURR_3_3_S 0 | ||
188 | #define CAP_CURR_3_0_M BITFIELD_MASK(8) | ||
189 | #define CAP_CURR_3_0_S 8 | ||
190 | #define CAP_CURR_1_8_M BITFIELD_MASK(8) | ||
191 | #define CAP_CURR_1_8_S 16 | ||
192 | |||
193 | /* SD_SysAddr: Offset 0x0000, Size 4 bytes */ | ||
194 | |||
195 | /* SD_BlockSize: Offset 0x004, Size 2 bytes */ | ||
196 | #define BLKSZ_BLKSZ_M BITFIELD_MASK(12) | ||
197 | #define BLKSZ_BLKSZ_S 0 | ||
198 | #define BLKSZ_BNDRY_M BITFIELD_MASK(3) | ||
199 | #define BLKSZ_BNDRY_S 12 | ||
200 | |||
201 | /* SD_BlockCount: Offset 0x006, size 2 bytes */ | ||
202 | |||
203 | /* SD_Arg0: Offset 0x008, size = 4 bytes */ | ||
204 | /* SD_TransferMode Offset 0x00C, size = 2 bytes */ | ||
205 | #define XFER_DMA_ENABLE_M BITFIELD_MASK(1) | ||
206 | #define XFER_DMA_ENABLE_S 0 | ||
207 | #define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1) | ||
208 | #define XFER_BLK_COUNT_EN_S 1 | ||
209 | #define XFER_CMD_12_EN_M BITFIELD_MASK(1) | ||
210 | #define XFER_CMD_12_EN_S 2 | ||
211 | #define XFER_DATA_DIRECTION_M BITFIELD_MASK(1) | ||
212 | #define XFER_DATA_DIRECTION_S 4 | ||
213 | #define XFER_MULTI_BLOCK_M BITFIELD_MASK(1) | ||
214 | #define XFER_MULTI_BLOCK_S 5 | ||
215 | |||
216 | /* SD_Command: Offset 0x00E, size = 2 bytes */ | ||
217 | /* resp_type field */ | ||
218 | #define RESP_TYPE_NONE 0 | ||
219 | #define RESP_TYPE_136 1 | ||
220 | #define RESP_TYPE_48 2 | ||
221 | #define RESP_TYPE_48_BUSY 3 | ||
222 | /* type field */ | ||
223 | #define CMD_TYPE_NORMAL 0 | ||
224 | #define CMD_TYPE_SUSPEND 1 | ||
225 | #define CMD_TYPE_RESUME 2 | ||
226 | #define CMD_TYPE_ABORT 3 | ||
227 | |||
228 | #define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */ | ||
229 | #define CMD_RESP_TYPE_S 0 | ||
230 | #define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */ | ||
231 | #define CMD_CRC_EN_S 3 | ||
232 | #define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */ | ||
233 | #define CMD_INDEX_EN_S 4 | ||
234 | #define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */ | ||
235 | #define CMD_DATA_EN_S 5 | ||
236 | #define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc | ||
237 | */ | ||
238 | #define CMD_TYPE_S 6 | ||
239 | #define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */ | ||
240 | #define CMD_INDEX_S 8 | ||
241 | |||
242 | /* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */ | ||
243 | /* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */ | ||
244 | /* SD_PresentState : Offset 0x024, size = 4 bytes */ | ||
245 | #define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */ | ||
246 | #define PRES_CMD_INHIBIT_S 0 | ||
247 | #define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */ | ||
248 | #define PRES_DAT_INHIBIT_S 1 | ||
249 | #define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */ | ||
250 | #define PRES_DAT_BUSY_S 2 | ||
251 | #define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */ | ||
252 | #define PRES_PRESENT_RSVD_S 3 | ||
253 | #define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */ | ||
254 | #define PRES_WRITE_ACTIVE_S 8 | ||
255 | #define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */ | ||
256 | #define PRES_READ_ACTIVE_S 9 | ||
257 | #define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */ | ||
258 | #define PRES_WRITE_DATA_RDY_S 10 | ||
259 | #define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */ | ||
260 | #define PRES_READ_DATA_RDY_S 11 | ||
261 | #define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */ | ||
262 | #define PRES_CARD_PRESENT_S 16 | ||
263 | #define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */ | ||
264 | #define PRES_CARD_STABLE_S 17 | ||
265 | #define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */ | ||
266 | #define PRES_CARD_PRESENT_RAW_S 18 | ||
267 | #define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */ | ||
268 | #define PRES_WRITE_ENABLED_S 19 | ||
269 | #define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */ | ||
270 | #define PRES_DAT_SIGNAL_S 20 | ||
271 | #define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */ | ||
272 | #define PRES_CMD_SIGNAL_S 24 | ||
273 | |||
274 | /* SD_HostCntrl: Offset 0x028, size = 1 bytes */ | ||
275 | #define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */ | ||
276 | #define HOST_LED_S 0 | ||
277 | #define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */ | ||
278 | #define HOST_DATA_WIDTH_S 1 | ||
279 | #define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */ | ||
280 | #define HOST_DMA_SEL_S 3 | ||
281 | #define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */ | ||
282 | #define HOST_HI_SPEED_EN_S 2 | ||
283 | |||
284 | /* Host Control2: */ | ||
285 | #define HOSTCtrl2_PRESVAL_EN_M BITFIELD_MASK(1) /* 1 bit */ | ||
286 | #define HOSTCtrl2_PRESVAL_EN_S 15 /* bit# */ | ||
287 | |||
288 | #define HOSTCtrl2_ASYINT_EN_M BITFIELD_MASK(1) /* 1 bit */ | ||
289 | #define HOSTCtrl2_ASYINT_EN_S 14 /* bit# */ | ||
290 | |||
291 | #define HOSTCtrl2_SAMPCLK_SEL_M BITFIELD_MASK(1) /* 1 bit */ | ||
292 | #define HOSTCtrl2_SAMPCLK_SEL_S 7 /* bit# */ | ||
293 | |||
294 | #define HOSTCtrl2_EXEC_TUNING_M BITFIELD_MASK(1) /* 1 bit */ | ||
295 | #define HOSTCtrl2_EXEC_TUNING_S 6 /* bit# */ | ||
296 | |||
297 | #define HOSTCtrl2_DRIVSTRENGTH_SEL_M BITFIELD_MASK(2) /* 2 bit */ | ||
298 | #define HOSTCtrl2_DRIVSTRENGTH_SEL_S 4 /* bit# */ | ||
299 | |||
300 | #define HOSTCtrl2_1_8SIG_EN_M BITFIELD_MASK(1) /* 1 bit */ | ||
301 | #define HOSTCtrl2_1_8SIG_EN_S 3 /* bit# */ | ||
302 | |||
303 | #define HOSTCtrl2_UHSMODE_SEL_M BITFIELD_MASK(3) /* 3 bit */ | ||
304 | #define HOSTCtrl2_UHSMODE_SEL_S 0 /* bit# */ | ||
305 | |||
306 | #define HOST_CONTR_VER_2 (1) | ||
307 | #define HOST_CONTR_VER_3 (2) | ||
308 | |||
309 | /* misc defines */ | ||
310 | #define SD1_MODE 0x1 /* SD Host Cntrlr Spec */ | ||
311 | #define SD4_MODE 0x2 /* SD Host Cntrlr Spec */ | ||
312 | |||
313 | /* SD_PwrCntrl: Offset 0x029, size = 1 bytes */ | ||
314 | #define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */ | ||
315 | #define PWR_BUS_EN_S 0 | ||
316 | #define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */ | ||
317 | #define PWR_VOLTS_S 1 | ||
318 | |||
319 | /* SD_SoftwareReset: Offset 0x02F, size = 1 byte */ | ||
320 | #define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */ | ||
321 | #define SW_RESET_ALL_S 0 | ||
322 | #define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */ | ||
323 | #define SW_RESET_CMD_S 1 | ||
324 | #define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */ | ||
325 | #define SW_RESET_DAT_S 2 | ||
326 | |||
327 | /* SD_IntrStatus: Offset 0x030, size = 2 bytes */ | ||
328 | /* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */ | ||
329 | #define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */ | ||
330 | #define INTSTAT_CMD_COMPLETE_S 0 | ||
331 | #define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1) | ||
332 | #define INTSTAT_XFER_COMPLETE_S 1 | ||
333 | #define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1) | ||
334 | #define INTSTAT_BLOCK_GAP_EVENT_S 2 | ||
335 | #define INTSTAT_DMA_INT_M BITFIELD_MASK(1) | ||
336 | #define INTSTAT_DMA_INT_S 3 | ||
337 | #define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1) | ||
338 | #define INTSTAT_BUF_WRITE_READY_S 4 | ||
339 | #define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1) | ||
340 | #define INTSTAT_BUF_READ_READY_S 5 | ||
341 | #define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1) | ||
342 | #define INTSTAT_CARD_INSERTION_S 6 | ||
343 | #define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1) | ||
344 | #define INTSTAT_CARD_REMOVAL_S 7 | ||
345 | #define INTSTAT_CARD_INT_M BITFIELD_MASK(1) | ||
346 | #define INTSTAT_CARD_INT_S 8 | ||
347 | #define INTSTAT_RETUNING_INT_M BITFIELD_MASK(1) /* Bit 12 */ | ||
348 | #define INTSTAT_RETUNING_INT_S 12 | ||
349 | #define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */ | ||
350 | #define INTSTAT_ERROR_INT_S 15 | ||
351 | |||
352 | /* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */ | ||
353 | /* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */ | ||
354 | #define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1) | ||
355 | #define ERRINT_CMD_TIMEOUT_S 0 | ||
356 | #define ERRINT_CMD_CRC_M BITFIELD_MASK(1) | ||
357 | #define ERRINT_CMD_CRC_S 1 | ||
358 | #define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1) | ||
359 | #define ERRINT_CMD_ENDBIT_S 2 | ||
360 | #define ERRINT_CMD_INDEX_M BITFIELD_MASK(1) | ||
361 | #define ERRINT_CMD_INDEX_S 3 | ||
362 | #define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1) | ||
363 | #define ERRINT_DATA_TIMEOUT_S 4 | ||
364 | #define ERRINT_DATA_CRC_M BITFIELD_MASK(1) | ||
365 | #define ERRINT_DATA_CRC_S 5 | ||
366 | #define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1) | ||
367 | #define ERRINT_DATA_ENDBIT_S 6 | ||
368 | #define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1) | ||
369 | #define ERRINT_CURRENT_LIMIT_S 7 | ||
370 | #define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1) | ||
371 | #define ERRINT_AUTO_CMD12_S 8 | ||
372 | #define ERRINT_VENDOR_M BITFIELD_MASK(4) | ||
373 | #define ERRINT_VENDOR_S 12 | ||
374 | #define ERRINT_ADMA_M BITFIELD_MASK(1) | ||
375 | #define ERRINT_ADMA_S 9 | ||
376 | |||
377 | /* Also provide definitions in "normal" form to allow combined masks */ | ||
378 | #define ERRINT_CMD_TIMEOUT_BIT 0x0001 | ||
379 | #define ERRINT_CMD_CRC_BIT 0x0002 | ||
380 | #define ERRINT_CMD_ENDBIT_BIT 0x0004 | ||
381 | #define ERRINT_CMD_INDEX_BIT 0x0008 | ||
382 | #define ERRINT_DATA_TIMEOUT_BIT 0x0010 | ||
383 | #define ERRINT_DATA_CRC_BIT 0x0020 | ||
384 | #define ERRINT_DATA_ENDBIT_BIT 0x0040 | ||
385 | #define ERRINT_CURRENT_LIMIT_BIT 0x0080 | ||
386 | #define ERRINT_AUTO_CMD12_BIT 0x0100 | ||
387 | #define ERRINT_ADMA_BIT 0x0200 | ||
388 | |||
389 | /* Masks to select CMD vs. DATA errors */ | ||
390 | #define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\ | ||
391 | ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT) | ||
392 | #define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\ | ||
393 | ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT) | ||
394 | #define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS) | ||
395 | |||
396 | /* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */ | ||
397 | /* SD_ClockCntrl : Offset 0x02C , size = bytes */ | ||
398 | /* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */ | ||
399 | /* SD_IntrStatus : Offset 0x030 , size = bytes */ | ||
400 | /* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */ | ||
401 | /* SD_IntrStatusEnable : Offset 0x034 , size = bytes */ | ||
402 | /* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */ | ||
403 | /* SD_IntrSignalEnable : Offset 0x038 , size = bytes */ | ||
404 | /* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */ | ||
405 | /* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */ | ||
406 | /* SD_Capabilities : Offset 0x040 , size = bytes */ | ||
407 | /* SD_MaxCurCap : Offset 0x048 , size = bytes */ | ||
408 | /* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */ | ||
409 | /* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */ | ||
410 | /* SD_HostControllerVersion : Offset 0x0FE , size = bytes */ | ||
411 | |||
412 | #endif /* _SDIOH_H */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/sdiovar.h b/drivers/net/wireless/bcmdhd/include/sdiovar.h new file mode 100644 index 00000000000..2c5bcf97e91 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/sdiovar.h | |||
@@ -0,0 +1,58 @@ | |||
1 | /* | ||
2 | * Structure used by apps whose drivers access SDIO drivers. | ||
3 | * Pulled out separately so dhdu and wlu can both use it. | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: sdiovar.h,v 13.9 2009-12-08 22:30:15 Exp $ | ||
26 | */ | ||
27 | |||
28 | #ifndef _sdiovar_h_ | ||
29 | #define _sdiovar_h_ | ||
30 | |||
31 | #include <typedefs.h> | ||
32 | |||
33 | /* require default structure packing */ | ||
34 | #define BWL_DEFAULT_PACKING | ||
35 | #include <packed_section_start.h> | ||
36 | |||
37 | typedef struct sdreg { | ||
38 | int func; | ||
39 | int offset; | ||
40 | int value; | ||
41 | } sdreg_t; | ||
42 | |||
43 | /* Common msglevel constants */ | ||
44 | #define SDH_ERROR_VAL 0x0001 /* Error */ | ||
45 | #define SDH_TRACE_VAL 0x0002 /* Trace */ | ||
46 | #define SDH_INFO_VAL 0x0004 /* Info */ | ||
47 | #define SDH_DEBUG_VAL 0x0008 /* Debug */ | ||
48 | #define SDH_DATA_VAL 0x0010 /* Data */ | ||
49 | #define SDH_CTRL_VAL 0x0020 /* Control Regs */ | ||
50 | #define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ | ||
51 | #define SDH_DMA_VAL 0x0080 /* DMA */ | ||
52 | |||
53 | #define NUM_PREV_TRANSACTIONS 16 | ||
54 | |||
55 | |||
56 | #include <packed_section_end.h> | ||
57 | |||
58 | #endif /* _sdiovar_h_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/siutils.h b/drivers/net/wireless/bcmdhd/include/siutils.h new file mode 100644 index 00000000000..c5a33832b58 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/siutils.h | |||
@@ -0,0 +1,247 @@ | |||
1 | /* | ||
2 | * Misc utility routines for accessing the SOC Interconnects | ||
3 | * of Broadcom HNBU chips. | ||
4 | * | ||
5 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
6 | * | ||
7 | * Unless you and Broadcom execute a separate written software license | ||
8 | * agreement governing use of this software, this software is licensed to you | ||
9 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
10 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
11 | * following added to such license: | ||
12 | * | ||
13 | * As a special exception, the copyright holders of this software give you | ||
14 | * permission to link this software with independent modules, and to copy and | ||
15 | * distribute the resulting executable under terms of your choice, provided that | ||
16 | * you also meet, for each linked independent module, the terms and conditions of | ||
17 | * the license of that module. An independent module is a module which is not | ||
18 | * derived from this software. The special exception does not apply to any | ||
19 | * modifications of the software. | ||
20 | * | ||
21 | * Notwithstanding the above, under no circumstances may you combine this | ||
22 | * software in any way with any other Broadcom software provided under a license | ||
23 | * other than the GPL, without Broadcom's express prior written consent. | ||
24 | * | ||
25 | * $Id: siutils.h,v 13.251.2.10 2011-02-04 05:06:32 Exp $ | ||
26 | */ | ||
27 | |||
28 | |||
29 | #ifndef _siutils_h_ | ||
30 | #define _siutils_h_ | ||
31 | |||
32 | |||
33 | struct si_pub { | ||
34 | uint socitype; | ||
35 | |||
36 | uint bustype; | ||
37 | uint buscoretype; | ||
38 | uint buscorerev; | ||
39 | uint buscoreidx; | ||
40 | int ccrev; | ||
41 | uint32 cccaps; | ||
42 | uint32 cccaps_ext; | ||
43 | int pmurev; | ||
44 | uint32 pmucaps; | ||
45 | uint boardtype; | ||
46 | uint boardvendor; | ||
47 | uint boardflags; | ||
48 | uint boardflags2; | ||
49 | uint chip; | ||
50 | uint chiprev; | ||
51 | uint chippkg; | ||
52 | uint32 chipst; | ||
53 | bool issim; | ||
54 | uint socirev; | ||
55 | bool pci_pr32414; | ||
56 | |||
57 | }; | ||
58 | |||
59 | |||
60 | typedef const struct si_pub si_t; | ||
61 | |||
62 | |||
63 | #define SI_OSH NULL | ||
64 | |||
65 | #define BADIDX (SI_MAXCORES + 1) | ||
66 | |||
67 | |||
68 | #define XTAL 0x1 | ||
69 | #define PLL 0x2 | ||
70 | |||
71 | |||
72 | #define CLK_FAST 0 | ||
73 | #define CLK_DYNAMIC 2 | ||
74 | |||
75 | |||
76 | #define GPIO_DRV_PRIORITY 0 | ||
77 | #define GPIO_APP_PRIORITY 1 | ||
78 | #define GPIO_HI_PRIORITY 2 | ||
79 | |||
80 | |||
81 | #define GPIO_PULLUP 0 | ||
82 | #define GPIO_PULLDN 1 | ||
83 | |||
84 | |||
85 | #define GPIO_REGEVT 0 | ||
86 | #define GPIO_REGEVT_INTMSK 1 | ||
87 | #define GPIO_REGEVT_INTPOL 2 | ||
88 | |||
89 | |||
90 | #define SI_DEVPATH_BUFSZ 16 | ||
91 | |||
92 | |||
93 | #define SI_DOATTACH 1 | ||
94 | #define SI_PCIDOWN 2 | ||
95 | #define SI_PCIUP 3 | ||
96 | |||
97 | #define ISSIM_ENAB(sih) 0 | ||
98 | |||
99 | |||
100 | #if defined(BCMPMUCTL) | ||
101 | #define PMUCTL_ENAB(sih) (BCMPMUCTL) | ||
102 | #else | ||
103 | #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) | ||
104 | #endif | ||
105 | |||
106 | |||
107 | #if defined(BCMPMUCTL) && BCMPMUCTL | ||
108 | #define CCCTL_ENAB(sih) (0) | ||
109 | #define CCPLL_ENAB(sih) (0) | ||
110 | #else | ||
111 | #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) | ||
112 | #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) | ||
113 | #endif | ||
114 | |||
115 | typedef void (*gpio_handler_t)(uint32 stat, void *arg); | ||
116 | |||
117 | |||
118 | |||
119 | extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, | ||
120 | void *sdh, char **vars, uint *varsz); | ||
121 | extern si_t *si_kattach(osl_t *osh); | ||
122 | extern void si_detach(si_t *sih); | ||
123 | extern bool si_pci_war16165(si_t *sih); | ||
124 | |||
125 | extern uint si_corelist(si_t *sih, uint coreid[]); | ||
126 | extern uint si_coreid(si_t *sih); | ||
127 | extern uint si_flag(si_t *sih); | ||
128 | extern uint si_intflag(si_t *sih); | ||
129 | extern uint si_coreidx(si_t *sih); | ||
130 | extern uint si_coreunit(si_t *sih); | ||
131 | extern uint si_corevendor(si_t *sih); | ||
132 | extern uint si_corerev(si_t *sih); | ||
133 | extern void *si_osh(si_t *sih); | ||
134 | extern void si_setosh(si_t *sih, osl_t *osh); | ||
135 | extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); | ||
136 | extern void *si_coreregs(si_t *sih); | ||
137 | extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); | ||
138 | extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); | ||
139 | extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); | ||
140 | extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); | ||
141 | extern bool si_iscoreup(si_t *sih); | ||
142 | extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); | ||
143 | extern void *si_setcoreidx(si_t *sih, uint coreidx); | ||
144 | extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); | ||
145 | extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val); | ||
146 | extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); | ||
147 | extern int si_numaddrspaces(si_t *sih); | ||
148 | extern uint32 si_addrspace(si_t *sih, uint asidx); | ||
149 | extern uint32 si_addrspacesize(si_t *sih, uint asidx); | ||
150 | extern int si_corebist(si_t *sih); | ||
151 | extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); | ||
152 | extern void si_core_disable(si_t *sih, uint32 bits); | ||
153 | extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); | ||
154 | extern bool si_read_pmu_autopll(si_t *sih); | ||
155 | extern uint32 si_clock(si_t *sih); | ||
156 | extern uint32 si_alp_clock(si_t *sih); | ||
157 | extern uint32 si_ilp_clock(si_t *sih); | ||
158 | extern void si_pci_setup(si_t *sih, uint coremask); | ||
159 | extern void si_pcmcia_init(si_t *sih); | ||
160 | extern void si_setint(si_t *sih, int siflag); | ||
161 | extern bool si_backplane64(si_t *sih); | ||
162 | extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, | ||
163 | void *intrsenabled_fn, void *intr_arg); | ||
164 | extern void si_deregister_intr_callback(si_t *sih); | ||
165 | extern void si_clkctl_init(si_t *sih); | ||
166 | extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); | ||
167 | extern bool si_clkctl_cc(si_t *sih, uint mode); | ||
168 | extern int si_clkctl_xtal(si_t *sih, uint what, bool on); | ||
169 | extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); | ||
170 | extern void si_btcgpiowar(si_t *sih); | ||
171 | extern bool si_deviceremoved(si_t *sih); | ||
172 | extern uint32 si_socram_size(si_t *sih); | ||
173 | extern uint32 si_socdevram_size(si_t *sih); | ||
174 | extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect); | ||
175 | extern bool si_socdevram_pkg(si_t *sih); | ||
176 | |||
177 | extern void si_watchdog(si_t *sih, uint ticks); | ||
178 | extern void si_watchdog_ms(si_t *sih, uint32 ms); | ||
179 | extern void *si_gpiosetcore(si_t *sih); | ||
180 | extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); | ||
181 | extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); | ||
182 | extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); | ||
183 | extern uint32 si_gpioin(si_t *sih); | ||
184 | extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); | ||
185 | extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); | ||
186 | extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); | ||
187 | extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority); | ||
188 | extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority); | ||
189 | extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); | ||
190 | extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); | ||
191 | extern uint32 si_gpio_int_enable(si_t *sih, bool enable); | ||
192 | |||
193 | |||
194 | extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg); | ||
195 | extern void si_gpio_handler_unregister(si_t *sih, void* gpioh); | ||
196 | extern void si_gpio_handler_process(si_t *sih); | ||
197 | |||
198 | |||
199 | extern bool si_pci_pmecap(si_t *sih); | ||
200 | struct osl_info; | ||
201 | extern bool si_pci_fastpmecap(struct osl_info *osh); | ||
202 | extern bool si_pci_pmestat(si_t *sih); | ||
203 | extern void si_pci_pmeclr(si_t *sih); | ||
204 | extern void si_pci_pmeen(si_t *sih); | ||
205 | extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); | ||
206 | |||
207 | extern void si_sdio_init(si_t *sih); | ||
208 | |||
209 | extern uint16 si_d11_devid(si_t *sih); | ||
210 | extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, | ||
211 | uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); | ||
212 | |||
213 | #define si_eci(sih) 0 | ||
214 | #define si_eci_init(sih) (0) | ||
215 | #define si_eci_notify_bt(sih, type, val) (0) | ||
216 | |||
217 | |||
218 | |||
219 | extern int si_devpath(si_t *sih, char *path, int size); | ||
220 | |||
221 | extern char *si_getdevpathvar(si_t *sih, const char *name); | ||
222 | extern int si_getdevpathintvar(si_t *sih, const char *name); | ||
223 | |||
224 | |||
225 | extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); | ||
226 | extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); | ||
227 | extern void si_war42780_clkreq(si_t *sih, bool clkreq); | ||
228 | extern void si_pci_sleep(si_t *sih); | ||
229 | extern void si_pci_down(si_t *sih); | ||
230 | extern void si_pci_up(si_t *sih); | ||
231 | extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm); | ||
232 | extern void si_pcie_extendL1timer(si_t *sih, bool extend); | ||
233 | extern int si_pci_fixcfg(si_t *sih); | ||
234 | extern uint si_pll_reset(si_t *sih); | ||
235 | |||
236 | |||
237 | |||
238 | extern bool si_taclear(si_t *sih, bool details); | ||
239 | |||
240 | |||
241 | |||
242 | extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); | ||
243 | extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); | ||
244 | |||
245 | char *si_getnvramflvar(si_t *sih, const char *name); | ||
246 | |||
247 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/trxhdr.h b/drivers/net/wireless/bcmdhd/include/trxhdr.h new file mode 100644 index 00000000000..397006ab005 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/trxhdr.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * TRX image file header format. | ||
3 | * | ||
4 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
5 | * | ||
6 | * Unless you and Broadcom execute a separate written software license | ||
7 | * agreement governing use of this software, this software is licensed to you | ||
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
10 | * following added to such license: | ||
11 | * | ||
12 | * As a special exception, the copyright holders of this software give you | ||
13 | * permission to link this software with independent modules, and to copy and | ||
14 | * distribute the resulting executable under terms of your choice, provided that | ||
15 | * you also meet, for each linked independent module, the terms and conditions of | ||
16 | * the license of that module. An independent module is a module which is not | ||
17 | * derived from this software. The special exception does not apply to any | ||
18 | * modifications of the software. | ||
19 | * | ||
20 | * Notwithstanding the above, under no circumstances may you combine this | ||
21 | * software in any way with any other Broadcom software provided under a license | ||
22 | * other than the GPL, without Broadcom's express prior written consent. | ||
23 | * | ||
24 | * $Id: trxhdr.h,v 13.15.108.2 2010-11-15 17:57:30 Exp $ | ||
25 | */ | ||
26 | |||
27 | #ifndef _TRX_HDR_H_ | ||
28 | #define _TRX_HDR_H_ | ||
29 | |||
30 | #include <typedefs.h> | ||
31 | |||
32 | #define TRX_MAGIC 0x30524448 /* "HDR0" */ | ||
33 | #define TRX_VERSION 1 /* Version 1 */ | ||
34 | #define TRX_MAX_LEN 0x3B0000 /* Max length */ | ||
35 | #define TRX_NO_HEADER 1 /* Do not write TRX header */ | ||
36 | #define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */ | ||
37 | #define TRX_OVERLAYS 0x4 /* Contains an overlay header after the trx header */ | ||
38 | #define TRX_MAX_OFFSET 3 /* Max number of individual files */ | ||
39 | #define TRX_UNCOMP_IMAGE 0x20 /* Trx contains uncompressed rtecdc.bin image */ | ||
40 | |||
41 | struct trx_header { | ||
42 | uint32 magic; /* "HDR0" */ | ||
43 | uint32 len; /* Length of file including header */ | ||
44 | uint32 crc32; /* 32-bit CRC from flag_version to end of file */ | ||
45 | uint32 flag_version; /* 0:15 flags, 16:31 version */ | ||
46 | uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ | ||
47 | }; | ||
48 | |||
49 | /* Compatibility */ | ||
50 | typedef struct trx_header TRXHDR, *PTRXHDR; | ||
51 | |||
52 | #endif /* _TRX_HDR_H_ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/typedefs.h b/drivers/net/wireless/bcmdhd/include/typedefs.h new file mode 100644 index 00000000000..228b5dcf11c --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/typedefs.h | |||
@@ -0,0 +1,309 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * $Id: typedefs.h,v 1.103.2.1 2010-05-11 18:19:28 Exp $ | ||
22 | */ | ||
23 | |||
24 | |||
25 | #ifndef _TYPEDEFS_H_ | ||
26 | #define _TYPEDEFS_H_ | ||
27 | |||
28 | #ifdef SITE_TYPEDEFS | ||
29 | |||
30 | |||
31 | |||
32 | #include "site_typedefs.h" | ||
33 | |||
34 | #else | ||
35 | |||
36 | |||
37 | |||
38 | #ifdef __cplusplus | ||
39 | |||
40 | #define TYPEDEF_BOOL | ||
41 | #ifndef FALSE | ||
42 | #define FALSE false | ||
43 | #endif | ||
44 | #ifndef TRUE | ||
45 | #define TRUE true | ||
46 | #endif | ||
47 | |||
48 | #else | ||
49 | |||
50 | |||
51 | #endif | ||
52 | |||
53 | #if defined(__x86_64__) | ||
54 | #define TYPEDEF_UINTPTR | ||
55 | typedef unsigned long long int uintptr; | ||
56 | #endif | ||
57 | |||
58 | |||
59 | |||
60 | |||
61 | |||
62 | #if defined(_NEED_SIZE_T_) | ||
63 | typedef long unsigned int size_t; | ||
64 | #endif | ||
65 | |||
66 | |||
67 | |||
68 | |||
69 | |||
70 | #if defined(__sparc__) | ||
71 | #define TYPEDEF_ULONG | ||
72 | #endif | ||
73 | |||
74 | |||
75 | |||
76 | #if !defined(LINUX_HYBRID) || defined(LINUX_PORT) | ||
77 | #define TYPEDEF_UINT | ||
78 | #ifndef TARGETENV_android | ||
79 | #define TYPEDEF_USHORT | ||
80 | #define TYPEDEF_ULONG | ||
81 | #endif | ||
82 | #ifdef __KERNEL__ | ||
83 | #include <linux/version.h> | ||
84 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) | ||
85 | #define TYPEDEF_BOOL | ||
86 | #endif | ||
87 | |||
88 | #if (LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 18)) | ||
89 | #include <linux/compiler.h> | ||
90 | #ifdef noinline_for_stack | ||
91 | #define TYPEDEF_BOOL | ||
92 | #endif | ||
93 | #endif | ||
94 | #endif | ||
95 | #endif | ||
96 | |||
97 | |||
98 | |||
99 | |||
100 | |||
101 | #if defined(__GNUC__) && defined(__STRICT_ANSI__) | ||
102 | #define TYPEDEF_INT64 | ||
103 | #define TYPEDEF_UINT64 | ||
104 | #endif | ||
105 | |||
106 | |||
107 | #if defined(__ICL) | ||
108 | |||
109 | #define TYPEDEF_INT64 | ||
110 | |||
111 | #if defined(__STDC__) | ||
112 | #define TYPEDEF_UINT64 | ||
113 | #endif | ||
114 | |||
115 | #endif | ||
116 | |||
117 | #if !defined(__DJGPP__) | ||
118 | |||
119 | |||
120 | #if defined(__KERNEL__) | ||
121 | |||
122 | |||
123 | #if !defined(LINUX_HYBRID) || defined(LINUX_PORT) | ||
124 | #include <linux/types.h> | ||
125 | #endif | ||
126 | |||
127 | #else | ||
128 | |||
129 | |||
130 | #include <sys/types.h> | ||
131 | |||
132 | #endif | ||
133 | |||
134 | #endif | ||
135 | |||
136 | |||
137 | |||
138 | |||
139 | #define USE_TYPEDEF_DEFAULTS | ||
140 | |||
141 | #endif | ||
142 | |||
143 | |||
144 | |||
145 | |||
146 | #ifdef USE_TYPEDEF_DEFAULTS | ||
147 | #undef USE_TYPEDEF_DEFAULTS | ||
148 | |||
149 | #ifndef TYPEDEF_BOOL | ||
150 | typedef unsigned char bool; | ||
151 | #endif | ||
152 | |||
153 | |||
154 | |||
155 | #ifndef TYPEDEF_UCHAR | ||
156 | typedef unsigned char uchar; | ||
157 | #endif | ||
158 | |||
159 | #ifndef TYPEDEF_USHORT | ||
160 | typedef unsigned short ushort; | ||
161 | #endif | ||
162 | |||
163 | #ifndef TYPEDEF_UINT | ||
164 | typedef unsigned int uint; | ||
165 | #endif | ||
166 | |||
167 | #ifndef TYPEDEF_ULONG | ||
168 | typedef unsigned long ulong; | ||
169 | #endif | ||
170 | |||
171 | |||
172 | |||
173 | #ifndef TYPEDEF_UINT8 | ||
174 | typedef unsigned char uint8; | ||
175 | #endif | ||
176 | |||
177 | #ifndef TYPEDEF_UINT16 | ||
178 | typedef unsigned short uint16; | ||
179 | #endif | ||
180 | |||
181 | #ifndef TYPEDEF_UINT32 | ||
182 | typedef unsigned int uint32; | ||
183 | #endif | ||
184 | |||
185 | #ifndef TYPEDEF_UINT64 | ||
186 | typedef unsigned long long uint64; | ||
187 | #endif | ||
188 | |||
189 | #ifndef TYPEDEF_UINTPTR | ||
190 | typedef unsigned int uintptr; | ||
191 | #endif | ||
192 | |||
193 | #ifndef TYPEDEF_INT8 | ||
194 | typedef signed char int8; | ||
195 | #endif | ||
196 | |||
197 | #ifndef TYPEDEF_INT16 | ||
198 | typedef signed short int16; | ||
199 | #endif | ||
200 | |||
201 | #ifndef TYPEDEF_INT32 | ||
202 | typedef signed int int32; | ||
203 | #endif | ||
204 | |||
205 | #ifndef TYPEDEF_INT64 | ||
206 | typedef signed long long int64; | ||
207 | #endif | ||
208 | |||
209 | |||
210 | |||
211 | #ifndef TYPEDEF_FLOAT32 | ||
212 | typedef float float32; | ||
213 | #endif | ||
214 | |||
215 | #ifndef TYPEDEF_FLOAT64 | ||
216 | typedef double float64; | ||
217 | #endif | ||
218 | |||
219 | |||
220 | |||
221 | #ifndef TYPEDEF_FLOAT_T | ||
222 | |||
223 | #if defined(FLOAT32) | ||
224 | typedef float32 float_t; | ||
225 | #else | ||
226 | typedef float64 float_t; | ||
227 | #endif | ||
228 | |||
229 | #endif | ||
230 | |||
231 | |||
232 | |||
233 | #ifndef FALSE | ||
234 | #define FALSE 0 | ||
235 | #endif | ||
236 | |||
237 | #ifndef TRUE | ||
238 | #define TRUE 1 | ||
239 | #endif | ||
240 | |||
241 | #ifndef NULL | ||
242 | #define NULL 0 | ||
243 | #endif | ||
244 | |||
245 | #ifndef OFF | ||
246 | #define OFF 0 | ||
247 | #endif | ||
248 | |||
249 | #ifndef ON | ||
250 | #define ON 1 | ||
251 | #endif | ||
252 | |||
253 | #define AUTO (-1) | ||
254 | |||
255 | |||
256 | |||
257 | #ifndef PTRSZ | ||
258 | #define PTRSZ sizeof(char*) | ||
259 | #endif | ||
260 | |||
261 | |||
262 | |||
263 | #if defined(__GNUC__) | ||
264 | #define BWL_COMPILER_GNU | ||
265 | #elif defined(__CC_ARM) && __CC_ARM | ||
266 | #define BWL_COMPILER_ARMCC | ||
267 | #else | ||
268 | #error "Unknown compiler!" | ||
269 | #endif | ||
270 | |||
271 | |||
272 | #ifndef INLINE | ||
273 | #if defined(BWL_COMPILER_MICROSOFT) | ||
274 | #define INLINE __inline | ||
275 | #elif defined(BWL_COMPILER_GNU) | ||
276 | #define INLINE __inline__ | ||
277 | #elif defined(BWL_COMPILER_ARMCC) | ||
278 | #define INLINE __inline | ||
279 | #else | ||
280 | #define INLINE | ||
281 | #endif | ||
282 | #endif | ||
283 | |||
284 | #undef TYPEDEF_BOOL | ||
285 | #undef TYPEDEF_UCHAR | ||
286 | #undef TYPEDEF_USHORT | ||
287 | #undef TYPEDEF_UINT | ||
288 | #undef TYPEDEF_ULONG | ||
289 | #undef TYPEDEF_UINT8 | ||
290 | #undef TYPEDEF_UINT16 | ||
291 | #undef TYPEDEF_UINT32 | ||
292 | #undef TYPEDEF_UINT64 | ||
293 | #undef TYPEDEF_UINTPTR | ||
294 | #undef TYPEDEF_INT8 | ||
295 | #undef TYPEDEF_INT16 | ||
296 | #undef TYPEDEF_INT32 | ||
297 | #undef TYPEDEF_INT64 | ||
298 | #undef TYPEDEF_FLOAT32 | ||
299 | #undef TYPEDEF_FLOAT64 | ||
300 | #undef TYPEDEF_FLOAT_T | ||
301 | |||
302 | #endif | ||
303 | |||
304 | |||
305 | #define UNUSED_PARAMETER(x) (void)(x) | ||
306 | |||
307 | |||
308 | #include <bcmdefs.h> | ||
309 | #endif | ||
diff --git a/drivers/net/wireless/bcmdhd/include/wlfc_proto.h b/drivers/net/wireless/bcmdhd/include/wlfc_proto.h new file mode 100644 index 00000000000..7230d3b67ab --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/wlfc_proto.h | |||
@@ -0,0 +1,198 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
3 | * | ||
4 | * Unless you and Broadcom execute a separate written software license | ||
5 | * agreement governing use of this software, this software is licensed to you | ||
6 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
7 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
8 | * following added to such license: | ||
9 | * | ||
10 | * As a special exception, the copyright holders of this software give you | ||
11 | * permission to link this software with independent modules, and to copy and | ||
12 | * distribute the resulting executable under terms of your choice, provided that | ||
13 | * you also meet, for each linked independent module, the terms and conditions of | ||
14 | * the license of that module. An independent module is a module which is not | ||
15 | * derived from this software. The special exception does not apply to any | ||
16 | * modifications of the software. | ||
17 | * | ||
18 | * Notwithstanding the above, under no circumstances may you combine this | ||
19 | * software in any way with any other Broadcom software provided under a license | ||
20 | * other than the GPL, without Broadcom's express prior written consent. | ||
21 | * $Id: wlfc_proto.h,v 1.1.6.2 2010-05-08 01:30:41 Exp $ | ||
22 | * | ||
23 | */ | ||
24 | #ifndef __wlfc_proto_definitions_h__ | ||
25 | #define __wlfc_proto_definitions_h__ | ||
26 | |||
27 | /* Use TLV to convey WLFC information. | ||
28 | --------------------------------------------------------------------------- | ||
29 | | Type | Len | value | Description | ||
30 | --------------------------------------------------------------------------- | ||
31 | | 1 | 1 | (handle) | MAC OPEN | ||
32 | --------------------------------------------------------------------------- | ||
33 | | 2 | 1 | (handle) | MAC CLOSE | ||
34 | --------------------------------------------------------------------------- | ||
35 | | 3 | 2 | (count, handle, prec_bmp)| Set the credit depth for a MAC dstn | ||
36 | --------------------------------------------------------------------------- | ||
37 | | 4 | 4 | see pkttag comments | TXSTATUS | ||
38 | --------------------------------------------------------------------------- | ||
39 | | 5 | 4 | see pkttag comments | PKKTTAG [host->firmware] | ||
40 | --------------------------------------------------------------------------- | ||
41 | | 6 | 8 | (handle, ifid, MAC) | MAC ADD | ||
42 | --------------------------------------------------------------------------- | ||
43 | | 7 | 8 | (handle, ifid, MAC) | MAC DEL | ||
44 | --------------------------------------------------------------------------- | ||
45 | | 8 | 1 | (rssi) | RSSI - RSSI value for the packet. | ||
46 | --------------------------------------------------------------------------- | ||
47 | | 9 | 1 | (interface ID) | Interface OPEN | ||
48 | --------------------------------------------------------------------------- | ||
49 | | 10 | 1 | (interface ID) | Interface CLOSE | ||
50 | --------------------------------------------------------------------------- | ||
51 | | 11 | 8 | fifo credit returns map | FIFO credits back to the host | ||
52 | | | | | | ||
53 | | | | | -------------------------------------- | ||
54 | | | | | | ac0 | ac1 | ac2 | ac3 | bcmc | atim | | ||
55 | | | | | -------------------------------------- | ||
56 | | | | | | ||
57 | --------------------------------------------------------------------------- | ||
58 | | 12 | 2 | MAC handle, | Host provides a bitmap of pending | ||
59 | | | | AC[0-3] traffic bitmap | unicast traffic for MAC-handle dstn. | ||
60 | | | | | [host->firmware] | ||
61 | --------------------------------------------------------------------------- | ||
62 | | 13 | 3 | (count, handle, prec_bmp)| One time request for packet to a specific | ||
63 | | | | | MAC destination. | ||
64 | --------------------------------------------------------------------------- | ||
65 | | 255 | N/A | N/A | FILLER - This is a special type | ||
66 | | | | | that has no length or value. | ||
67 | | | | | Typically used for padding. | ||
68 | --------------------------------------------------------------------------- | ||
69 | */ | ||
70 | |||
71 | #define WLFC_CTL_TYPE_MAC_OPEN 1 | ||
72 | #define WLFC_CTL_TYPE_MAC_CLOSE 2 | ||
73 | #define WLFC_CTL_TYPE_MAC_REQUEST_CREDIT 3 | ||
74 | #define WLFC_CTL_TYPE_TXSTATUS 4 | ||
75 | #define WLFC_CTL_TYPE_PKTTAG 5 | ||
76 | |||
77 | #define WLFC_CTL_TYPE_MACDESC_ADD 6 | ||
78 | #define WLFC_CTL_TYPE_MACDESC_DEL 7 | ||
79 | #define WLFC_CTL_TYPE_RSSI 8 | ||
80 | |||
81 | #define WLFC_CTL_TYPE_INTERFACE_OPEN 9 | ||
82 | #define WLFC_CTL_TYPE_INTERFACE_CLOSE 10 | ||
83 | |||
84 | #define WLFC_CTL_TYPE_FIFO_CREDITBACK 11 | ||
85 | |||
86 | #define WLFC_CTL_TYPE_PENDING_TRAFFIC_BMP 12 | ||
87 | #define WLFC_CTL_TYPE_MAC_REQUEST_PACKET 13 | ||
88 | |||
89 | #define WLFC_CTL_TYPE_FILLER 255 | ||
90 | |||
91 | #define WLFC_CTL_VALUE_LEN_MACDESC 8 /* handle, interface, MAC */ | ||
92 | |||
93 | #define WLFC_CTL_VALUE_LEN_MAC 1 /* MAC-handle */ | ||
94 | #define WLFC_CTL_VALUE_LEN_RSSI 1 | ||
95 | |||
96 | #define WLFC_CTL_VALUE_LEN_INTERFACE 1 | ||
97 | #define WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP 2 | ||
98 | |||
99 | #define WLFC_CTL_VALUE_LEN_TXSTATUS 4 | ||
100 | #define WLFC_CTL_VALUE_LEN_PKTTAG 4 | ||
101 | |||
102 | /* enough space to host all 4 ACs, bc/mc and atim fifo credit */ | ||
103 | #define WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK 6 | ||
104 | |||
105 | #define WLFC_CTL_VALUE_LEN_REQUEST_CREDIT 3 /* credit, MAC-handle, prec_bitmap */ | ||
106 | #define WLFC_CTL_VALUE_LEN_REQUEST_PACKET 3 /* credit, MAC-handle, prec_bitmap */ | ||
107 | |||
108 | |||
109 | |||
110 | #define WLFC_PKTID_GEN_MASK 0x80000000 | ||
111 | #define WLFC_PKTID_GEN_SHIFT 31 | ||
112 | |||
113 | #define WLFC_PKTID_GEN(x) (((x) & WLFC_PKTID_GEN_MASK) >> WLFC_PKTID_GEN_SHIFT) | ||
114 | #define WLFC_PKTID_SETGEN(x, gen) (x) = ((x) & ~WLFC_PKTID_GEN_MASK) | \ | ||
115 | (((gen) << WLFC_PKTID_GEN_SHIFT) & WLFC_PKTID_GEN_MASK) | ||
116 | |||
117 | #define WLFC_PKTFLAG_PKTFROMHOST 0x01 | ||
118 | #define WLFC_PKTFLAG_PKT_REQUESTED 0x02 | ||
119 | |||
120 | #define WL_TXSTATUS_FLAGS_MASK 0xf /* allow 4 bits only */ | ||
121 | #define WL_TXSTATUS_FLAGS_SHIFT 27 | ||
122 | |||
123 | #define WL_TXSTATUS_SET_FLAGS(x, flags) ((x) = \ | ||
124 | ((x) & ~(WL_TXSTATUS_FLAGS_MASK << WL_TXSTATUS_FLAGS_SHIFT)) | \ | ||
125 | (((flags) & WL_TXSTATUS_FLAGS_MASK) << WL_TXSTATUS_FLAGS_SHIFT)) | ||
126 | #define WL_TXSTATUS_GET_FLAGS(x) (((x) >> WL_TXSTATUS_FLAGS_SHIFT) & \ | ||
127 | WL_TXSTATUS_FLAGS_MASK) | ||
128 | |||
129 | #define WL_TXSTATUS_FIFO_MASK 0x7 /* allow 3 bits for FIFO ID */ | ||
130 | #define WL_TXSTATUS_FIFO_SHIFT 24 | ||
131 | |||
132 | #define WL_TXSTATUS_SET_FIFO(x, flags) ((x) = \ | ||
133 | ((x) & ~(WL_TXSTATUS_FIFO_MASK << WL_TXSTATUS_FIFO_SHIFT)) | \ | ||
134 | (((flags) & WL_TXSTATUS_FIFO_MASK) << WL_TXSTATUS_FIFO_SHIFT)) | ||
135 | #define WL_TXSTATUS_GET_FIFO(x) (((x) >> WL_TXSTATUS_FIFO_SHIFT) & WL_TXSTATUS_FIFO_MASK) | ||
136 | |||
137 | #define WL_TXSTATUS_PKTID_MASK 0xffffff /* allow 24 bits */ | ||
138 | #define WL_TXSTATUS_SET_PKTID(x, num) ((x) = \ | ||
139 | ((x) & ~WL_TXSTATUS_PKTID_MASK) | (num)) | ||
140 | #define WL_TXSTATUS_GET_PKTID(x) ((x) & WL_TXSTATUS_PKTID_MASK) | ||
141 | |||
142 | /* 32 STA should be enough??, 6 bits; Must be power of 2 */ | ||
143 | #define WLFC_MAC_DESC_TABLE_SIZE 32 | ||
144 | #define WLFC_MAX_IFNUM 16 | ||
145 | #define WLFC_MAC_DESC_ID_INVALID 0xff | ||
146 | |||
147 | /* b[7:5] -reuse guard, b[4:0] -value */ | ||
148 | #define WLFC_MAC_DESC_GET_LOOKUP_INDEX(x) ((x) & 0x1f) | ||
149 | |||
150 | #define WLFC_PKTFLAG_SET_PKTREQUESTED(x) (x) |= \ | ||
151 | (WLFC_PKTFLAG_PKT_REQUESTED << WL_TXSTATUS_FLAGS_SHIFT) | ||
152 | |||
153 | #define WLFC_PKTFLAG_CLR_PKTREQUESTED(x) (x) &= \ | ||
154 | ~(WLFC_PKTFLAG_PKT_REQUESTED << WL_TXSTATUS_FLAGS_SHIFT) | ||
155 | |||
156 | #define WL_TXSTATUS_GENERATION_MASK 1 | ||
157 | #define WL_TXSTATUS_GENERATION_SHIFT 31 | ||
158 | |||
159 | #define WLFC_PKTFLAG_SET_GENERATION(x, gen) ((x) = \ | ||
160 | ((x) & ~(WL_TXSTATUS_GENERATION_MASK << WL_TXSTATUS_GENERATION_SHIFT)) | \ | ||
161 | (((gen) & WL_TXSTATUS_GENERATION_MASK) << WL_TXSTATUS_GENERATION_SHIFT)) | ||
162 | |||
163 | #define WLFC_PKTFLAG_GENERATION(x) (((x) >> WL_TXSTATUS_GENERATION_SHIFT) & \ | ||
164 | WL_TXSTATUS_GENERATION_MASK) | ||
165 | |||
166 | #define WLFC_MAX_PENDING_DATALEN 120 | ||
167 | |||
168 | /* host is free to discard the packet */ | ||
169 | #define WLFC_CTL_PKTFLAG_DISCARD 0 | ||
170 | /* D11 suppressed a packet */ | ||
171 | #define WLFC_CTL_PKTFLAG_D11SUPPRESS 1 | ||
172 | /* WL firmware suppressed a packet because MAC is | ||
173 | already in PSMode (short time window) | ||
174 | */ | ||
175 | #define WLFC_CTL_PKTFLAG_WLSUPPRESS 2 | ||
176 | /* Firmware tossed this packet */ | ||
177 | #define WLFC_CTL_PKTFLAG_TOSSED_BYWLC 3 | ||
178 | |||
179 | #define WLFC_D11_STATUS_INTERPRET(txs) ((((txs)->status & TX_STATUS_SUPR_MASK) >> \ | ||
180 | TX_STATUS_SUPR_SHIFT)) ? WLFC_CTL_PKTFLAG_D11SUPPRESS : WLFC_CTL_PKTFLAG_DISCARD | ||
181 | |||
182 | #ifdef PROP_TXSTATUS_DEBUG | ||
183 | #define WLFC_DBGMESG(x) printf x | ||
184 | /* wlfc-breadcrumb */ | ||
185 | #define WLFC_BREADCRUMB(x) do {if ((x) == NULL) \ | ||
186 | {printf("WLFC: %s():%d:caller:%p\n", \ | ||
187 | __FUNCTION__, __LINE__, __builtin_return_address(0));}} while (0) | ||
188 | #define WLFC_PRINTMAC(banner, ea) do {printf("%s MAC: [%02x:%02x:%02x:%02x:%02x:%02x]\n", \ | ||
189 | banner, ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); } while (0) | ||
190 | #define WLFC_WHEREIS(s) printf("WLFC: at %s():%d, %s\n", __FUNCTION__, __LINE__, (s)) | ||
191 | #else | ||
192 | #define WLFC_DBGMESG(x) | ||
193 | #define WLFC_BREADCRUMB(x) | ||
194 | #define WLFC_PRINTMAC(banner, ea) | ||
195 | #define WLFC_WHEREIS(s) | ||
196 | #endif | ||
197 | |||
198 | #endif /* __wlfc_proto_definitions_h__ */ | ||
diff --git a/drivers/net/wireless/bcmdhd/include/wlioctl.h b/drivers/net/wireless/bcmdhd/include/wlioctl.h new file mode 100644 index 00000000000..9357552c919 --- /dev/null +++ b/drivers/net/wireless/bcmdhd/include/wlioctl.h | |||
@@ -0,0 +1,2757 @@ | |||
1 | /* | ||
2 | * Custom OID/ioctl definitions for | ||
3 | * Broadcom 802.11abg Networking Device Driver | ||
4 | * | ||
5 | * Definitions subject to change without notice. | ||
6 | * | ||
7 | * Copyright (C) 1999-2011, Broadcom Corporation | ||
8 | * | ||
9 | * Unless you and Broadcom execute a separate written software license | ||
10 | * agreement governing use of this software, this software is licensed to you | ||
11 | * under the terms of the GNU General Public License version 2 (the "GPL"), | ||
12 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | ||
13 | * following added to such license: | ||
14 | * | ||
15 | * As a special exception, the copyright holders of this software give you | ||
16 | * permission to link this software with independent modules, and to copy and | ||
17 | * distribute the resulting executable under terms of your choice, provided that | ||
18 | * you also meet, for each linked independent module, the terms and conditions of | ||
19 | * the license of that module. An independent module is a module which is not | ||
20 | * derived from this software. The special exception does not apply to any | ||
21 | * modifications of the software. | ||
22 | * | ||
23 | * Notwithstanding the above, under no circumstances may you combine this | ||
24 | * software in any way with any other Broadcom software provided under a license | ||
25 | * other than the GPL, without Broadcom's express prior written consent. | ||
26 | * | ||
27 | * $Id: wlioctl.h,v 1.767.2.38 2011-02-01 23:04:28 Exp $ | ||
28 | */ | ||
29 | |||
30 | |||
31 | #ifndef _wlioctl_h_ | ||
32 | #define _wlioctl_h_ | ||
33 | |||
34 | #include <typedefs.h> | ||
35 | #include <proto/ethernet.h> | ||
36 | #include <proto/bcmeth.h> | ||
37 | #include <proto/bcmevent.h> | ||
38 | #include <proto/802.11.h> | ||
39 | #include <bcmwifi.h> | ||
40 | |||
41 | #include <bcmcdc.h> | ||
42 | |||
43 | #ifndef INTF_NAME_SIZ | ||
44 | #define INTF_NAME_SIZ 16 | ||
45 | #endif | ||
46 | |||
47 | |||
48 | typedef struct remote_ioctl { | ||
49 | cdc_ioctl_t msg; | ||
50 | uint data_len; | ||
51 | char intf_name[INTF_NAME_SIZ]; | ||
52 | } rem_ioctl_t; | ||
53 | #define REMOTE_SIZE sizeof(rem_ioctl_t) | ||
54 | |||
55 | #define ACTION_FRAME_SIZE 1040 | ||
56 | |||
57 | typedef struct wl_action_frame { | ||
58 | struct ether_addr da; | ||
59 | uint16 len; | ||
60 | uint32 packetId; | ||
61 | uint8 data[ACTION_FRAME_SIZE]; | ||
62 | } wl_action_frame_t; | ||
63 | |||
64 | #define WL_WIFI_ACTION_FRAME_SIZE sizeof(struct wl_action_frame) | ||
65 | |||
66 | typedef struct ssid_info | ||
67 | { | ||
68 | uint8 ssid_len; | ||
69 | uint8 ssid[32]; | ||
70 | } ssid_info_t; | ||
71 | |||
72 | typedef struct wl_af_params { | ||
73 | uint32 channel; | ||
74 | int32 dwell_time; | ||
75 | struct ether_addr BSSID; | ||
76 | wl_action_frame_t action_frame; | ||
77 | } wl_af_params_t; | ||
78 | |||
79 | #define WL_WIFI_AF_PARAMS_SIZE sizeof(struct wl_af_params) | ||
80 | |||
81 | |||
82 | #define BWL_DEFAULT_PACKING | ||
83 | #include <packed_section_start.h> | ||
84 | |||
85 | |||
86 | |||
87 | |||
88 | |||
89 | #define LEGACY2_WL_BSS_INFO_VERSION 108 | ||
90 | |||
91 | |||
92 | typedef struct wl_bss_info_108 { | ||
93 | uint32 version; | ||
94 | uint32 length; | ||
95 | struct ether_addr BSSID; | ||
96 | uint16 beacon_period; | ||
97 | uint16 capability; | ||
98 | uint8 SSID_len; | ||
99 | uint8 SSID[32]; | ||
100 | struct { | ||
101 | uint count; | ||
102 | uint8 rates[16]; | ||
103 | } rateset; | ||
104 | chanspec_t chanspec; | ||
105 | uint16 atim_window; | ||
106 | uint8 dtim_period; | ||
107 | int16 RSSI; | ||
108 | int8 phy_noise; | ||
109 | |||
110 | uint8 n_cap; | ||
111 | uint32 nbss_cap; | ||
112 | uint8 ctl_ch; | ||
113 | uint32 reserved32[1]; | ||
114 | uint8 flags; | ||
115 | uint8 reserved[3]; | ||
116 | uint8 basic_mcs[MCSSET_LEN]; | ||
117 | |||
118 | uint16 ie_offset; | ||
119 | uint32 ie_length; | ||
120 | |||
121 | |||
122 | } wl_bss_info_108_t; | ||
123 | |||
124 | #define WL_BSS_INFO_VERSION 109 | ||
125 | |||
126 | |||
127 | typedef struct wl_bss_info { | ||
128 | uint32 version; | ||
129 | uint32 length; | ||
130 | struct ether_addr BSSID; | ||
131 | uint16 beacon_period; | ||
132 | uint16 capability; | ||
133 | uint8 SSID_len; | ||
134 | uint8 SSID[32]; | ||
135 | struct { | ||
136 | uint count; | ||
137 | uint8 rates[16]; | ||
138 | } rateset; | ||
139 | chanspec_t chanspec; | ||
140 | uint16 atim_window; | ||
141 | uint8 dtim_period; | ||
142 | int16 RSSI; | ||
143 | int8 phy_noise; | ||
144 | |||
145 | uint8 n_cap; | ||
146 | uint32 nbss_cap; | ||
147 | uint8 ctl_ch; | ||
148 | uint32 reserved32[1]; | ||
149 | uint8 flags; | ||
150 | uint8 reserved[3]; | ||
151 | uint8 basic_mcs[MCSSET_LEN]; | ||
152 | |||
153 | uint16 ie_offset; | ||
154 | uint32 ie_length; | ||
155 | int16 SNR; | ||
156 | |||
157 | |||
158 | } wl_bss_info_t; | ||
159 | |||
160 | typedef struct wl_bsscfg { | ||
161 | uint32 wsec; | ||
162 | uint32 WPA_auth; | ||
163 | uint32 wsec_index; | ||
164 | uint32 associated; | ||
165 | uint32 BSS; | ||
166 | uint32 phytest_on; | ||
167 | struct ether_addr prev_BSSID; | ||
168 | struct ether_addr BSSID; | ||
169 | } wl_bsscfg_t; | ||
170 | |||
171 | typedef struct wl_bss_config { | ||
172 | uint32 atim_window; | ||
173 | uint32 beacon_period; | ||
174 | uint32 chanspec; | ||
175 | } wl_bss_config_t; | ||
176 | |||
177 | |||
178 | typedef struct wlc_ssid { | ||
179 | uint32 SSID_len; | ||
180 | uchar SSID[32]; | ||
181 | } wlc_ssid_t; | ||
182 | |||
183 | |||
184 | #define WL_BSSTYPE_INFRA 1 | ||
185 | #define WL_BSSTYPE_INDEP 0 | ||
186 | #define WL_BSSTYPE_ANY 2 | ||
187 | |||
188 | |||
189 | #define WL_SCANFLAGS_PASSIVE 0x01 | ||
190 | #define WL_SCANFLAGS_RESERVED 0x02 | ||
191 | #define WL_SCANFLAGS_PROHIBITED 0x04 | ||
192 | |||
193 | #define WL_SCAN_PARAMS_SSID_MAX 10 | ||
194 | typedef struct wl_scan_params { | ||
195 | wlc_ssid_t ssid; | ||
196 | struct ether_addr bssid; | ||
197 | int8 bss_type; | ||
198 | uint8 scan_type; | ||
199 | int32 nprobes; | ||
200 | int32 active_time; | ||
201 | int32 passive_time; | ||
202 | int32 home_time; | ||
203 | int32 channel_num; | ||
204 | uint16 channel_list[1]; | ||
205 | } wl_scan_params_t; | ||
206 | |||
207 | |||
208 | #define WL_SCAN_PARAMS_FIXED_SIZE 64 | ||
209 | |||
210 | |||
211 | #define WL_SCAN_PARAMS_COUNT_MASK 0x0000ffff | ||
212 | #define WL_SCAN_PARAMS_NSSID_SHIFT 16 | ||
213 | |||
214 | #define WL_SCAN_ACTION_START 1 | ||
215 | #define WL_SCAN_ACTION_CONTINUE 2 | ||
216 | #define WL_SCAN_ACTION_ABORT 3 | ||
217 | |||
218 | #define ISCAN_REQ_VERSION 1 | ||
219 | |||
220 | |||
221 | typedef struct wl_iscan_params { | ||
222 | uint32 version; | ||
223 | uint16 action; | ||
224 | uint16 scan_duration; | ||
225 | wl_scan_params_t params; | ||
226 | } wl_iscan_params_t; | ||
227 | |||
228 | |||
229 | #define WL_ISCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_iscan_params_t, params) + sizeof(wlc_ssid_t)) | ||
230 | |||
231 | typedef struct wl_scan_results { | ||
232 | uint32 buflen; | ||
233 | uint32 version; | ||
234 | uint32 count; | ||
235 | wl_bss_info_t bss_info[1]; | ||
236 | } wl_scan_results_t; | ||
237 | |||
238 | |||
239 | #define WL_SCAN_RESULTS_FIXED_SIZE (sizeof(wl_scan_results_t) - sizeof(wl_bss_info_t)) | ||
240 | |||
241 | |||
242 | #define WL_SCAN_RESULTS_SUCCESS 0 | ||
243 | #define WL_SCAN_RESULTS_PARTIAL 1 | ||
244 | #define WL_SCAN_RESULTS_PENDING 2 | ||
245 | #define WL_SCAN_RESULTS_ABORTED 3 | ||
246 | #define WL_SCAN_RESULTS_NO_MEM 4 | ||
247 | |||
248 | |||
249 | #define DNGL_RXCTXT_SIZE 45 | ||
250 | |||
251 | #if defined(SIMPLE_ISCAN) | ||
252 | #define ISCAN_RETRY_CNT 5 | ||
253 | #define ISCAN_STATE_IDLE 0 | ||
254 | #define ISCAN_STATE_SCANING 1 | ||
255 | #define ISCAN_STATE_PENDING 2 | ||
256 | |||
257 | |||
258 | #define WLC_IW_ISCAN_MAXLEN 2048 | ||
259 | typedef struct iscan_buf { | ||
260 | struct iscan_buf * next; | ||
261 | char iscan_buf[WLC_IW_ISCAN_MAXLEN]; | ||
262 | } iscan_buf_t; | ||
263 | #endif | ||
264 | |||
265 | #define ESCAN_REQ_VERSION 1 | ||
266 | |||
267 | typedef struct wl_escan_params { | ||
268 | uint32 version; | ||
269 | uint16 action; | ||
270 | uint16 sync_id; | ||
271 | wl_scan_params_t params; | ||
272 | } wl_escan_params_t; | ||
273 | |||
274 | #define WL_ESCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_escan_params_t, params) + sizeof(wlc_ssid_t)) | ||
275 | |||
276 | typedef struct wl_escan_result { | ||
277 | uint32 buflen; | ||
278 | uint32 version; | ||
279 | uint16 sync_id; | ||
280 | uint16 bss_count; | ||
281 | wl_bss_info_t bss_info[1]; | ||
282 | } wl_escan_result_t; | ||
283 | |||
284 | #define WL_ESCAN_RESULTS_FIXED_SIZE (sizeof(wl_escan_result_t) - sizeof(wl_bss_info_t)) | ||
285 | |||
286 | |||
287 | typedef struct wl_iscan_results { | ||
288 | uint32 status; | ||
289 | wl_scan_results_t results; | ||
290 | } wl_iscan_results_t; | ||
291 | |||
292 | |||
293 | #define WL_ISCAN_RESULTS_FIXED_SIZE \ | ||
294 | (WL_SCAN_RESULTS_FIXED_SIZE + OFFSETOF(wl_iscan_results_t, results)) | ||
295 | |||
296 | typedef struct wl_probe_params { | ||
297 | wlc_ssid_t ssid; | ||
298 | struct ether_addr bssid; | ||
299 | struct ether_addr mac; | ||
300 | } wl_probe_params_t; | ||
301 | |||
302 | #define WL_NUMRATES 16 | ||
303 | typedef struct wl_rateset { | ||
304 | uint32 count; | ||
305 | uint8 rates[WL_NUMRATES]; | ||
306 | } wl_rateset_t; | ||
307 | |||
308 | typedef struct wl_rateset_args { | ||
309 | uint32 count; | ||
310 | uint8 rates[WL_NUMRATES]; | ||
311 | uint8 mcs[MCSSET_LEN]; | ||
312 | } wl_rateset_args_t; | ||
313 | |||
314 | |||
315 | typedef struct wl_uint32_list { | ||
316 | |||
317 | uint32 count; | ||
318 | |||
319 | uint32 element[1]; | ||
320 | } wl_uint32_list_t; | ||
321 | |||
322 | |||
323 | typedef struct wl_assoc_params { | ||
324 | struct ether_addr bssid; | ||
325 | uint16 bssid_cnt; | ||
326 | int32 chanspec_num; | ||
327 | chanspec_t chanspec_list[1]; | ||
328 | } wl_assoc_params_t; | ||
329 | #define WL_ASSOC_PARAMS_FIXED_SIZE (sizeof(wl_assoc_params_t) - sizeof(chanspec_t)) | ||
330 | |||
331 | |||
332 | typedef wl_assoc_params_t wl_reassoc_params_t; | ||
333 | #define WL_REASSOC_PARAMS_FIXED_SIZE WL_ASSOC_PARAMS_FIXED_SIZE | ||
334 | |||
335 | |||
336 | typedef wl_assoc_params_t wl_join_assoc_params_t; | ||
337 | #define WL_JOIN_ASSOC_PARAMS_FIXED_SIZE WL_ASSOC_PARAMS_FIXED_SIZE | ||
338 | |||
339 | |||
340 | typedef struct wl_join_params { | ||
341 | wlc_ssid_t ssid; | ||
342 | wl_assoc_params_t params; | ||
343 | } wl_join_params_t; | ||
344 | #define WL_JOIN_PARAMS_FIXED_SIZE (sizeof(wl_join_params_t) - sizeof(chanspec_t)) | ||
345 | |||
346 | |||
347 | typedef struct wl_join_scan_params { | ||
348 | uint8 scan_type; | ||
349 | int32 nprobes; | ||
350 | int32 active_time; | ||
351 | int32 passive_time; | ||
352 | int32 home_time; | ||
353 | } wl_join_scan_params_t; | ||
354 | |||
355 | |||
356 | typedef struct wl_extjoin_params { | ||
357 | wlc_ssid_t ssid; | ||
358 | wl_join_scan_params_t scan; | ||
359 | wl_join_assoc_params_t assoc; | ||
360 | } wl_extjoin_params_t; | ||
361 | #define WL_EXTJOIN_PARAMS_FIXED_SIZE (sizeof(wl_extjoin_params_t) - sizeof(chanspec_t)) | ||
362 | |||
363 | typedef struct { | ||
364 | uint32 num; | ||
365 | chanspec_t list[1]; | ||
366 | } chanspec_list_t; | ||
367 | |||
368 | |||
369 | #define NRATE_MCS_INUSE 0x00000080 | ||
370 | #define NRATE_RATE_MASK 0x0000007f | ||
371 | #define NRATE_STF_MASK 0x0000ff00 | ||
372 | #define NRATE_STF_SHIFT 8 | ||
373 | #define NRATE_OVERRIDE 0x80000000 | ||
374 | #define NRATE_OVERRIDE_MCS_ONLY 0x40000000 | ||
375 | #define NRATE_SGI_MASK 0x00800000 | ||
376 | #define NRATE_SGI_SHIFT 23 | ||
377 | #define NRATE_LDPC_CODING 0x00400000 | ||
378 | #define NRATE_LDPC_SHIFT 22 | ||
379 | |||
380 | #define NRATE_STF_SISO 0 | ||
381 | #define NRATE_STF_CDD 1 | ||
382 | #define NRATE_STF_STBC 2 | ||
383 | #define NRATE_STF_SDM 3 | ||
384 | |||
385 | #define ANTENNA_NUM_1 1 | ||
386 | #define ANTENNA_NUM_2 2 | ||
387 | #define ANTENNA_NUM_3 3 | ||
388 | #define ANTENNA_NUM_4 4 | ||
389 | |||
390 | #define ANT_SELCFG_AUTO 0x80 | ||
391 | #define ANT_SELCFG_MASK 0x33 | ||
392 | #define ANT_SELCFG_MAX 4 | ||
393 | #define ANT_SELCFG_TX_UNICAST 0 | ||
394 | #define ANT_SELCFG_RX_UNICAST 1 | ||
395 | #define ANT_SELCFG_TX_DEF 2 | ||
396 | #define ANT_SELCFG_RX_DEF 3 | ||
397 | |||
398 | #define MAX_STREAMS_SUPPORTED 4 | ||
399 | |||
400 | typedef struct { | ||
401 | uint8 ant_config[ANT_SELCFG_MAX]; | ||
402 | uint8 num_antcfg; | ||
403 | } wlc_antselcfg_t; | ||
404 | |||
405 | #define HIGHEST_SINGLE_STREAM_MCS 7 | ||
406 | |||
407 | #define MAX_CCA_CHANNELS 38 | ||
408 | #define MAX_CCA_SECS 60 | ||
409 | |||
410 | #define IBSS_MED 15 | ||
411 | #define IBSS_HI 25 | ||
412 | #define OBSS_MED 12 | ||
413 | #define OBSS_HI 25 | ||
414 | #define INTERFER_MED 5 | ||
415 | #define INTERFER_HI 10 | ||
416 | |||
417 | #define CCA_FLAG_2G_ONLY 0x01 | ||
418 | #define CCA_FLAG_5G_ONLY 0x02 | ||
419 | #define CCA_FLAG_IGNORE_DURATION 0x04 | ||
420 | #define CCA_FLAGS_PREFER_1_6_11 0x10 | ||
421 | #define CCA_FLAG_IGNORE_INTERFER 0x20 | ||
422 | |||
423 | #define CCA_ERRNO_BAND 1 | ||
424 | #define CCA_ERRNO_DURATION 2 | ||
425 | #define CCA_ERRNO_PREF_CHAN 3 | ||
426 | #define CCA_ERRNO_INTERFER 4 | ||
427 | #define CCA_ERRNO_TOO_FEW 5 | ||
428 | |||
429 | typedef struct { | ||
430 | uint32 duration; | ||
431 | uint32 congest_ibss; | ||
432 | |||
433 | uint32 congest_obss; | ||
434 | uint32 interference; | ||
435 | uint32 timestamp; | ||
436 | } cca_congest_t; | ||
437 | |||
438 | typedef struct { | ||
439 | chanspec_t chanspec; | ||
440 | uint8 num_secs; | ||
441 | cca_congest_t secs[1]; | ||
442 | } cca_congest_channel_req_t; | ||
443 | |||
444 | #define WLC_CNTRY_BUF_SZ 4 | ||
445 | |||
446 | typedef struct wl_country { | ||
447 | char country_abbrev[WLC_CNTRY_BUF_SZ]; | ||
448 | int32 rev; | ||
449 | char ccode[WLC_CNTRY_BUF_SZ]; | ||
450 | } wl_country_t; | ||
451 | |||
452 | typedef struct wl_channels_in_country { | ||
453 | uint32 buflen; | ||
454 | uint32 band; | ||
455 | char country_abbrev[WLC_CNTRY_BUF_SZ]; | ||
456 | uint32 count; | ||
457 | uint32 channel[1]; | ||
458 | } wl_channels_in_country_t; | ||
459 | |||
460 | typedef struct wl_country_list { | ||
461 | uint32 buflen; | ||
462 | uint32 band_set; | ||
463 | uint32 band; | ||
464 | uint32 count; | ||
465 | char country_abbrev[1]; | ||
466 | } wl_country_list_t; | ||
467 | |||
468 | #define WL_NUM_RPI_BINS 8 | ||
469 | #define WL_RM_TYPE_BASIC 1 | ||
470 | #define WL_RM_TYPE_CCA 2 | ||
471 | #define WL_RM_TYPE_RPI 3 | ||
472 | |||
473 | #define WL_RM_FLAG_PARALLEL (1<<0) | ||
474 | |||
475 | #define WL_RM_FLAG_LATE (1<<1) | ||
476 | #define WL_RM_FLAG_INCAPABLE (1<<2) | ||
477 | #define WL_RM_FLAG_REFUSED (1<<3) | ||
478 | |||
479 | typedef struct wl_rm_req_elt { | ||
480 | int8 type; | ||
481 | int8 flags; | ||
482 | chanspec_t chanspec; | ||
483 | uint32 token; | ||
484 | uint32 tsf_h; | ||
485 | uint32 tsf_l; | ||
486 | uint32 dur; | ||
487 | } wl_rm_req_elt_t; | ||
488 | |||
489 | typedef struct wl_rm_req { | ||
490 | uint32 token; | ||
491 | uint32 count; | ||
492 | void *cb; | ||
493 | void *cb_arg; | ||
494 | wl_rm_req_elt_t req[1]; | ||
495 | } wl_rm_req_t; | ||
496 | #define WL_RM_REQ_FIXED_LEN OFFSETOF(wl_rm_req_t, req) | ||
497 | |||
498 | typedef struct wl_rm_rep_elt { | ||
499 | int8 type; | ||
500 | int8 flags; | ||
501 | chanspec_t chanspec; | ||
502 | uint32 token; | ||
503 | uint32 tsf_h; | ||
504 | uint32 tsf_l; | ||
505 | uint32 dur; | ||
506 | uint32 len; | ||
507 | uint8 data[1]; | ||
508 | } wl_rm_rep_elt_t; | ||
509 | #define WL_RM_REP_ELT_FIXED_LEN 24 | ||
510 | |||
511 | #define WL_RPI_REP_BIN_NUM 8 | ||
512 | typedef struct wl_rm_rpi_rep { | ||
513 | uint8 rpi[WL_RPI_REP_BIN_NUM]; | ||
514 | int8 rpi_max[WL_RPI_REP_BIN_NUM]; | ||
515 | } wl_rm_rpi_rep_t; | ||
516 | |||
517 | typedef struct wl_rm_rep { | ||
518 | uint32 token; | ||
519 | uint32 len; | ||
520 | wl_rm_rep_elt_t rep[1]; | ||
521 | } wl_rm_rep_t; | ||
522 | #define WL_RM_REP_FIXED_LEN 8 | ||
523 | |||
524 | |||
525 | typedef enum sup_auth_status { | ||
526 | |||
527 | WLC_SUP_DISCONNECTED = 0, | ||
528 | WLC_SUP_CONNECTING, | ||
529 | WLC_SUP_IDREQUIRED, | ||
530 | WLC_SUP_AUTHENTICATING, | ||
531 | WLC_SUP_AUTHENTICATED, | ||
532 | WLC_SUP_KEYXCHANGE, | ||
533 | WLC_SUP_KEYED, | ||
534 | WLC_SUP_TIMEOUT, | ||
535 | WLC_SUP_LAST_BASIC_STATE, | ||
536 | |||
537 | |||
538 | |||
539 | WLC_SUP_KEYXCHANGE_WAIT_M1 = WLC_SUP_AUTHENTICATED, | ||
540 | |||
541 | WLC_SUP_KEYXCHANGE_PREP_M2 = WLC_SUP_KEYXCHANGE, | ||
542 | |||
543 | WLC_SUP_KEYXCHANGE_WAIT_M3 = WLC_SUP_LAST_BASIC_STATE, | ||
544 | WLC_SUP_KEYXCHANGE_PREP_M4, | ||
545 | WLC_SUP_KEYXCHANGE_WAIT_G1, | ||
546 | WLC_SUP_KEYXCHANGE_PREP_G2 | ||
547 | } sup_auth_status_t; | ||
548 | |||
549 | |||
550 | #define CRYPTO_ALGO_OFF 0 | ||
551 | #define CRYPTO_ALGO_WEP1 1 | ||
552 | #define CRYPTO_ALGO_TKIP 2 | ||
553 | #define CRYPTO_ALGO_WEP128 3 | ||
554 | #define CRYPTO_ALGO_AES_CCM 4 | ||
555 | #define CRYPTO_ALGO_AES_OCB_MSDU 5 | ||
556 | #define CRYPTO_ALGO_AES_OCB_MPDU 6 | ||
557 | #define CRYPTO_ALGO_NALG 7 | ||
558 | #define CRYPTO_ALGO_PMK 12 | ||
559 | |||
560 | #define WSEC_GEN_MIC_ERROR 0x0001 | ||
561 | #define WSEC_GEN_REPLAY 0x0002 | ||
562 | #define WSEC_GEN_ICV_ERROR 0x0004 | ||
563 | |||
564 | #define WL_SOFT_KEY (1 << 0) | ||
565 | #define WL_PRIMARY_KEY (1 << 1) | ||
566 | #define WL_KF_RES_4 (1 << 4) | ||
567 | #define WL_KF_RES_5 (1 << 5) | ||
568 | #define WL_IBSS_PEER_GROUP_KEY (1 << 6) | ||
569 | |||
570 | typedef struct wl_wsec_key { | ||
571 | uint32 index; | ||
572 | uint32 len; | ||
573 | uint8 data[DOT11_MAX_KEY_SIZE]; | ||
574 | uint32 pad_1[18]; | ||
575 | uint32 algo; | ||
576 | uint32 flags; | ||
577 | uint32 pad_2[2]; | ||
578 | int pad_3; | ||
579 | int iv_initialized; | ||
580 | int pad_4; | ||
581 | |||
582 | struct { | ||
583 | uint32 hi; | ||
584 | uint16 lo; | ||
585 | } rxiv; | ||
586 | uint32 pad_5[2]; | ||
587 | struct ether_addr ea; | ||
588 | } wl_wsec_key_t; | ||
589 | |||
590 | #define WSEC_MIN_PSK_LEN 8 | ||
591 | #define WSEC_MAX_PSK_LEN 64 | ||
592 | |||
593 | |||
594 | #define WSEC_PASSPHRASE (1<<0) | ||
595 | |||
596 | |||
597 | typedef struct { | ||
598 | ushort key_len; | ||
599 | ushort flags; | ||
600 | uint8 key[WSEC_MAX_PSK_LEN]; | ||
601 | } wsec_pmk_t; | ||
602 | |||
603 | |||
604 | #define WEP_ENABLED 0x0001 | ||
605 | #define TKIP_ENABLED 0x0002 | ||
606 | #define AES_ENABLED 0x0004 | ||
607 | #define WSEC_SWFLAG 0x0008 | ||
608 | #define SES_OW_ENABLED 0x0040 | ||
609 | |||
610 | |||
611 | #define WPA_AUTH_DISABLED 0x0000 | ||
612 | #define WPA_AUTH_NONE 0x0001 | ||
613 | #define WPA_AUTH_UNSPECIFIED 0x0002 | ||
614 | #define WPA_AUTH_PSK 0x0004 | ||
615 | |||
616 | #define WPA2_AUTH_UNSPECIFIED 0x0040 | ||
617 | #define WPA2_AUTH_PSK 0x0080 | ||
618 | #define BRCM_AUTH_PSK 0x0100 | ||
619 | #define BRCM_AUTH_DPT 0x0200 | ||
620 | #define WPA2_AUTH_MFP 0x1000 | ||
621 | #define WPA2_AUTH_TPK 0x2000 | ||
622 | #define WPA2_AUTH_FT 0x4000 | ||
623 | |||
624 | |||
625 | #define MAXPMKID 16 | ||
626 | |||
627 | typedef struct _pmkid { | ||
628 | struct ether_addr BSSID; | ||
629 | uint8 PMKID[WPA2_PMKID_LEN]; | ||
630 | } pmkid_t; | ||
631 | |||
632 | typedef struct _pmkid_list { | ||
633 | uint32 npmkid; | ||
634 | pmkid_t pmkid[1]; | ||
635 | } pmkid_list_t; | ||
636 | |||
637 | typedef struct _pmkid_cand { | ||
638 | struct ether_addr BSSID; | ||
639 | uint8 preauth; | ||
640 | } pmkid_cand_t; | ||
641 | |||
642 | typedef struct _pmkid_cand_list { | ||
643 | uint32 npmkid_cand; | ||
644 | pmkid_cand_t pmkid_cand[1]; | ||
645 | } pmkid_cand_list_t; | ||
646 | |||
647 | typedef struct wl_assoc_info { | ||
648 | uint32 req_len; | ||
649 | uint32 resp_len; | ||
650 | uint32 flags; | ||
651 | struct dot11_assoc_req req; | ||
652 | struct ether_addr reassoc_bssid; | ||
653 | struct dot11_assoc_resp resp; | ||
654 | } wl_assoc_info_t; | ||
655 | |||
656 | |||
657 | #define WLC_ASSOC_REQ_IS_REASSOC 0x01 | ||
658 | |||
659 | |||
660 | typedef struct { | ||
661 | uint16 ver; | ||
662 | uint16 len; | ||
663 | uint16 cap; | ||
664 | uint32 flags; | ||
665 | uint32 idle; | ||
666 | struct ether_addr ea; | ||
667 | wl_rateset_t rateset; | ||
668 | uint32 in; | ||
669 | uint32 listen_interval_inms; | ||
670 | uint32 tx_pkts; | ||
671 | uint32 tx_failures; | ||
672 | uint32 rx_ucast_pkts; | ||
673 | uint32 rx_mcast_pkts; | ||
674 | uint32 tx_rate; | ||
675 | uint32 rx_rate; | ||
676 | uint32 rx_decrypt_succeeds; | ||
677 | uint32 rx_decrypt_failures; | ||
678 | } sta_info_t; | ||
679 | |||
680 | #define WL_OLD_STAINFO_SIZE OFFSETOF(sta_info_t, tx_pkts) | ||
681 | |||
682 | #define WL_STA_VER 3 | ||
683 | |||
684 | |||
685 | #define WL_STA_BRCM 0x1 | ||
686 | #define WL_STA_WME 0x2 | ||
687 | #define WL_STA_ABCAP 0x4 | ||
688 | #define WL_STA_AUTHE 0x8 | ||
689 | #define WL_STA_ASSOC 0x10 | ||
690 | #define WL_STA_AUTHO 0x20 | ||
691 | #define WL_STA_WDS 0x40 | ||
692 | #define WL_STA_WDS_LINKUP 0x80 | ||
693 | #define WL_STA_PS 0x100 | ||
694 | #define WL_STA_APSD_BE 0x200 | ||
695 | #define WL_STA_APSD_BK 0x400 | ||
696 | #define WL_STA_APSD_VI 0x800 | ||
697 | #define WL_STA_APSD_VO 0x1000 | ||
698 | #define WL_STA_N_CAP 0x2000 | ||
699 | #define WL_STA_SCBSTATS 0x4000 | ||
700 | |||
701 | #define WL_WDS_LINKUP WL_STA_WDS_LINKUP | ||
702 | |||
703 | |||
704 | #define WLC_TXFILTER_OVERRIDE_DISABLED 0 | ||
705 | #define WLC_TXFILTER_OVERRIDE_ENABLED 1 | ||
706 | |||
707 | |||
708 | typedef struct { | ||
709 | uint32 val; | ||
710 | struct ether_addr ea; | ||
711 | } scb_val_t; | ||
712 | |||
713 | |||
714 | typedef struct { | ||
715 | uint32 code; | ||
716 | scb_val_t ioctl_args; | ||
717 | } authops_t; | ||
718 | |||
719 | |||
720 | typedef struct channel_info { | ||
721 | int hw_channel; | ||
722 | int target_channel; | ||
723 | int scan_channel; | ||
724 | } channel_info_t; | ||
725 | |||
726 | |||
727 | struct maclist { | ||
728 | uint count; | ||
729 | struct ether_addr ea[1]; | ||
730 | }; | ||
731 | |||
732 | |||
733 | typedef struct get_pktcnt { | ||
734 | uint rx_good_pkt; | ||
735 | uint rx_bad_pkt; | ||
736 | uint tx_good_pkt; | ||
737 | uint tx_bad_pkt; | ||
738 | uint rx_ocast_good_pkt; | ||
739 | } get_pktcnt_t; | ||
740 | |||
741 | #define WL_IOCTL_ACTION_GET 0x0 | ||
742 | #define WL_IOCTL_ACTION_SET 0x1 | ||
743 | #define WL_IOCTL_ACTION_OVL_IDX_MASK 0x1e | ||
744 | #define WL_IOCTL_ACTION_OVL_RSV 0x20 | ||
745 | #define WL_IOCTL_ACTION_OVL 0x40 | ||
746 | #define WL_IOCTL_ACTION_MASK 0x7e | ||
747 | #define WL_IOCTL_ACTION_OVL_SHIFT 1 | ||
748 | |||
749 | |||
750 | typedef struct wl_ioctl { | ||
751 | uint cmd; | ||
752 | void *buf; | ||
753 | uint len; | ||
754 | uint8 set; | ||
755 | uint used; | ||
756 | uint needed; | ||
757 | } wl_ioctl_t; | ||
758 | |||
759 | |||
760 | #define ioctl_subtype set | ||
761 | #define ioctl_pid used | ||
762 | #define ioctl_status needed | ||
763 | |||
764 | |||
765 | typedef struct wlc_rev_info { | ||
766 | uint vendorid; | ||
767 | uint deviceid; | ||
768 | uint radiorev; | ||
769 | uint chiprev; | ||
770 | uint corerev; | ||
771 | uint boardid; | ||
772 | uint boardvendor; | ||
773 | uint boardrev; | ||
774 | uint driverrev; | ||
775 | uint ucoderev; | ||
776 | uint bus; | ||
777 | uint chipnum; | ||
778 | uint phytype; | ||
779 | uint phyrev; | ||
780 | uint anarev; | ||
781 | uint chippkg; | ||
782 | } wlc_rev_info_t; | ||
783 | |||
784 | #define WL_REV_INFO_LEGACY_LENGTH 48 | ||
785 | |||
786 | #define WL_BRAND_MAX 10 | ||
787 | typedef struct wl_instance_info { | ||
788 | uint instance; | ||
789 | char brand[WL_BRAND_MAX]; | ||
790 | } wl_instance_info_t; | ||
791 | |||
792 | |||
793 | typedef struct wl_txfifo_sz { | ||
794 | uint16 magic; | ||
795 | uint16 fifo; | ||
796 | uint16 size; | ||
797 | } wl_txfifo_sz_t; | ||
798 | |||
799 | #define WL_TXFIFO_SZ_MAGIC 0xa5a5 | ||
800 | |||
801 | |||
802 | |||
803 | #define WLC_IOV_NAME_LEN 30 | ||
804 | typedef struct wlc_iov_trx_s { | ||
805 | uint8 module; | ||
806 | uint8 type; | ||
807 | char name[WLC_IOV_NAME_LEN]; | ||
808 | } wlc_iov_trx_t; | ||
809 | |||
810 | |||
811 | #define WLC_IOCTL_MAGIC 0x14e46c77 | ||
812 | |||
813 | |||
814 | #define WLC_IOCTL_VERSION 1 | ||
815 | |||
816 | #define WLC_IOCTL_MAXLEN 8192 | ||
817 | #define WLC_IOCTL_SMLEN 256 | ||
818 | #define WLC_IOCTL_MEDLEN 1536 | ||
819 | #ifdef WLC_HIGH_ONLY | ||
820 | #define WLC_SAMPLECOLLECT_MAXLEN 1024 | ||
821 | #else | ||
822 | #define WLC_SAMPLECOLLECT_MAXLEN 10240 | ||
823 | #endif | ||
824 | |||
825 | |||
826 | #define WLC_GET_MAGIC 0 | ||
827 | #define WLC_GET_VERSION 1 | ||
828 | #define WLC_UP 2 | ||
829 | #define WLC_DOWN 3 | ||
830 | #define WLC_GET_LOOP 4 | ||
831 | #define WLC_SET_LOOP 5 | ||
832 | #define WLC_DUMP 6 | ||
833 | #define WLC_GET_MSGLEVEL 7 | ||
834 | #define WLC_SET_MSGLEVEL 8 | ||
835 | #define WLC_GET_PROMISC 9 | ||
836 | #define WLC_SET_PROMISC 10 | ||
837 | #define WLC_OVERLAY_IOCTL 11 | ||
838 | #define WLC_GET_RATE 12 | ||
839 | |||
840 | #define WLC_GET_INSTANCE 14 | ||
841 | |||
842 | |||
843 | |||
844 | |||
845 | #define WLC_GET_INFRA 19 | ||
846 | #define WLC_SET_INFRA 20 | ||
847 | #define WLC_GET_AUTH 21 | ||
848 | #define WLC_SET_AUTH 22 | ||
849 | #define WLC_GET_BSSID 23 | ||
850 | #define WLC_SET_BSSID 24 | ||
851 | #define WLC_GET_SSID 25 | ||
852 | #define WLC_SET_SSID 26 | ||
853 | #define WLC_RESTART 27 | ||
854 | |||
855 | #define WLC_GET_CHANNEL 29 | ||
856 | #define WLC_SET_CHANNEL 30 | ||
857 | #define WLC_GET_SRL 31 | ||
858 | #define WLC_SET_SRL 32 | ||
859 | #define WLC_GET_LRL 33 | ||
860 | #define WLC_SET_LRL 34 | ||
861 | #define WLC_GET_PLCPHDR 35 | ||
862 | #define WLC_SET_PLCPHDR 36 | ||
863 | #define WLC_GET_RADIO 37 | ||
864 | #define WLC_SET_RADIO 38 | ||
865 | #define WLC_GET_PHYTYPE 39 | ||
866 | #define WLC_DUMP_RATE 40 | ||
867 | #define WLC_SET_RATE_PARAMS 41 | ||
868 | #define WLC_GET_FIXRATE 42 | ||
869 | #define WLC_SET_FIXRATE 43 | ||
870 | |||
871 | |||
872 | #define WLC_GET_KEY 44 | ||
873 | #define WLC_SET_KEY 45 | ||
874 | #define WLC_GET_REGULATORY 46 | ||
875 | #define WLC_SET_REGULATORY 47 | ||
876 | #define WLC_GET_PASSIVE_SCAN 48 | ||
877 | #define WLC_SET_PASSIVE_SCAN 49 | ||
878 | #define WLC_SCAN 50 | ||
879 | #define WLC_SCAN_RESULTS 51 | ||
880 | #define WLC_DISASSOC 52 | ||
881 | #define WLC_REASSOC 53 | ||
882 | #define WLC_GET_ROAM_TRIGGER 54 | ||
883 | #define WLC_SET_ROAM_TRIGGER 55 | ||
884 | #define WLC_GET_ROAM_DELTA 56 | ||
885 | #define WLC_SET_ROAM_DELTA 57 | ||
886 | #define WLC_GET_ROAM_SCAN_PERIOD 58 | ||
887 | #define WLC_SET_ROAM_SCAN_PERIOD 59 | ||
888 | #define WLC_EVM 60 | ||
889 | #define WLC_GET_TXANT 61 | ||
890 | #define WLC_SET_TXANT 62 | ||
891 | #define WLC_GET_ANTDIV 63 | ||
892 | #define WLC_SET_ANTDIV 64 | ||
893 | |||
894 | |||
895 | #define WLC_GET_CLOSED 67 | ||
896 | #define WLC_SET_CLOSED 68 | ||
897 | #define WLC_GET_MACLIST 69 | ||
898 | #define WLC_SET_MACLIST 70 | ||
899 | #define WLC_GET_RATESET 71 | ||
900 | #define WLC_SET_RATESET 72 | ||
901 | |||
902 | #define WLC_LONGTRAIN 74 | ||
903 | #define WLC_GET_BCNPRD 75 | ||
904 | #define WLC_SET_BCNPRD 76 | ||
905 | #define WLC_GET_DTIMPRD 77 | ||
906 | #define WLC_SET_DTIMPRD 78 | ||
907 | #define WLC_GET_SROM 79 | ||
908 | #define WLC_SET_SROM 80 | ||
909 | #define WLC_GET_WEP_RESTRICT 81 | ||
910 | #define WLC_SET_WEP_RESTRICT 82 | ||
911 | #define WLC_GET_COUNTRY 83 | ||
912 | #define WLC_SET_COUNTRY 84 | ||
913 | #define WLC_GET_PM 85 | ||
914 | #define WLC_SET_PM 86 | ||
915 | #define WLC_GET_WAKE 87 | ||
916 | #define WLC_SET_WAKE 88 | ||
917 | |||
918 | #define WLC_GET_FORCELINK 90 | ||
919 | #define WLC_SET_FORCELINK 91 | ||
920 | #define WLC_FREQ_ACCURACY 92 | ||
921 | #define WLC_CARRIER_SUPPRESS 93 | ||
922 | #define WLC_GET_PHYREG 94 | ||
923 | #define WLC_SET_PHYREG 95 | ||
924 | #define WLC_GET_RADIOREG 96 | ||
925 | #define WLC_SET_RADIOREG 97 | ||
926 | #define WLC_GET_REVINFO 98 | ||
927 | #define WLC_GET_UCANTDIV 99 | ||
928 | #define WLC_SET_UCANTDIV 100 | ||
929 | #define WLC_R_REG 101 | ||
930 | #define WLC_W_REG 102 | ||
931 | |||
932 | |||
933 | #define WLC_GET_MACMODE 105 | ||
934 | #define WLC_SET_MACMODE 106 | ||
935 | #define WLC_GET_MONITOR 107 | ||
936 | #define WLC_SET_MONITOR 108 | ||
937 | #define WLC_GET_GMODE 109 | ||
938 | #define WLC_SET_GMODE 110 | ||
939 | #define WLC_GET_LEGACY_ERP 111 | ||
940 | #define WLC_SET_LEGACY_ERP 112 | ||
941 | #define WLC_GET_RX_ANT 113 | ||
942 | #define WLC_GET_CURR_RATESET 114 | ||
943 | #define WLC_GET_SCANSUPPRESS 115 | ||
944 | #define WLC_SET_SCANSUPPRESS 116 | ||
945 | #define WLC_GET_AP 117 | ||
946 | #define WLC_SET_AP 118 | ||
947 | #define WLC_GET_EAP_RESTRICT 119 | ||
948 | #define WLC_SET_EAP_RESTRICT 120 | ||
949 | #define WLC_SCB_AUTHORIZE 121 | ||
950 | #define WLC_SCB_DEAUTHORIZE 122 | ||
951 | #define WLC_GET_WDSLIST 123 | ||
952 | #define WLC_SET_WDSLIST 124 | ||
953 | #define WLC_GET_ATIM 125 | ||
954 | #define WLC_SET_ATIM 126 | ||
955 | #define WLC_GET_RSSI 127 | ||
956 | #define WLC_GET_PHYANTDIV 128 | ||
957 | #define WLC_SET_PHYANTDIV 129 | ||
958 | #define WLC_AP_RX_ONLY 130 | ||
959 | #define WLC_GET_TX_PATH_PWR 131 | ||
960 | #define WLC_SET_TX_PATH_PWR 132 | ||
961 | #define WLC_GET_WSEC 133 | ||
962 | #define WLC_SET_WSEC 134 | ||
963 | #define WLC_GET_PHY_NOISE 135 | ||
964 | #define WLC_GET_BSS_INFO 136 | ||
965 | #define WLC_GET_PKTCNTS 137 | ||
966 | #define WLC_GET_LAZYWDS 138 | ||
967 | #define WLC_SET_LAZYWDS 139 | ||
968 | #define WLC_GET_BANDLIST 140 | ||
969 | #define WLC_GET_BAND 141 | ||
970 | #define WLC_SET_BAND 142 | ||
971 | #define WLC_SCB_DEAUTHENTICATE 143 | ||
972 | #define WLC_GET_SHORTSLOT 144 | ||
973 | #define WLC_GET_SHORTSLOT_OVERRIDE 145 | ||
974 | #define WLC_SET_SHORTSLOT_OVERRIDE 146 | ||
975 | #define WLC_GET_SHORTSLOT_RESTRICT 147 | ||
976 | #define WLC_SET_SHORTSLOT_RESTRICT 148 | ||
977 | #define WLC_GET_GMODE_PROTECTION 149 | ||
978 | #define WLC_GET_GMODE_PROTECTION_OVERRIDE 150 | ||
979 | #define WLC_SET_GMODE_PROTECTION_OVERRIDE 151 | ||
980 | #define WLC_UPGRADE 152 | ||
981 | |||
982 | |||
983 | #define WLC_GET_IGNORE_BCNS 155 | ||
984 | #define WLC_SET_IGNORE_BCNS 156 | ||
985 | #define WLC_GET_SCB_TIMEOUT 157 | ||
986 | #define WLC_SET_SCB_TIMEOUT 158 | ||
987 | #define WLC_GET_ASSOCLIST 159 | ||
988 | #define WLC_GET_CLK 160 | ||
989 | #define WLC_SET_CLK 161 | ||
990 | #define WLC_GET_UP 162 | ||
991 | #define WLC_OUT 163 | ||
992 | #define WLC_GET_WPA_AUTH 164 | ||
993 | #define WLC_SET_WPA_AUTH 165 | ||
994 | #define WLC_GET_UCFLAGS 166 | ||
995 | #define WLC_SET_UCFLAGS 167 | ||
996 | #define WLC_GET_PWRIDX 168 | ||
997 | #define WLC_SET_PWRIDX 169 | ||
998 | #define WLC_GET_TSSI 170 | ||
999 | #define WLC_GET_SUP_RATESET_OVERRIDE 171 | ||
1000 | #define WLC_SET_SUP_RATESET_OVERRIDE 172 | ||
1001 | |||
1002 | |||
1003 | |||
1004 | |||
1005 | |||
1006 | #define WLC_GET_PROTECTION_CONTROL 178 | ||
1007 | #define WLC_SET_PROTECTION_CONTROL 179 | ||
1008 | #define WLC_GET_PHYLIST 180 | ||
1009 | #define WLC_ENCRYPT_STRENGTH 181 | ||
1010 | #define WLC_DECRYPT_STATUS 182 | ||
1011 | #define WLC_GET_KEY_SEQ 183 | ||
1012 | #define WLC_GET_SCAN_CHANNEL_TIME 184 | ||
1013 | #define WLC_SET_SCAN_CHANNEL_TIME 185 | ||
1014 | #define WLC_GET_SCAN_UNASSOC_TIME 186 | ||
1015 | #define WLC_SET_SCAN_UNASSOC_TIME 187 | ||
1016 | #define WLC_GET_SCAN_HOME_TIME 188 | ||
1017 | #define WLC_SET_SCAN_HOME_TIME 189 | ||
1018 | #define WLC_GET_SCAN_NPROBES 190 | ||
1019 | #define WLC_SET_SCAN_NPROBES 191 | ||
1020 | #define WLC_GET_PRB_RESP_TIMEOUT 192 | ||
1021 | #define WLC_SET_PRB_RESP_TIMEOUT 193 | ||
1022 | #define WLC_GET_ATTEN 194 | ||
1023 | #define WLC_SET_ATTEN 195 | ||
1024 | #define WLC_GET_SHMEM 196 | ||
1025 | #define WLC_SET_SHMEM 197 | ||
1026 | |||
1027 | |||
1028 | #define WLC_SET_WSEC_TEST 200 | ||
1029 | #define WLC_SCB_DEAUTHENTICATE_FOR_REASON 201 | ||
1030 | #define WLC_TKIP_COUNTERMEASURES 202 | ||
1031 | #define WLC_GET_PIOMODE 203 | ||
1032 | #define WLC_SET_PIOMODE 204 | ||
1033 | #define WLC_SET_ASSOC_PREFER 205 | ||
1034 | #define WLC_GET_ASSOC_PREFER 206 | ||
1035 | #define WLC_SET_ROAM_PREFER 207 | ||
1036 | #define WLC_GET_ROAM_PREFER 208 | ||
1037 | #define WLC_SET_LED 209 | ||
1038 | #define WLC_GET_LED 210 | ||
1039 | #define WLC_GET_INTERFERENCE_MODE 211 | ||
1040 | #define WLC_SET_INTERFERENCE_MODE 212 | ||
1041 | #define WLC_GET_CHANNEL_QA 213 | ||
1042 | #define WLC_START_CHANNEL_QA 214 | ||
1043 | #define WLC_GET_CHANNEL_SEL 215 | ||
1044 | #define WLC_START_CHANNEL_SEL 216 | ||
1045 | #define WLC_GET_VALID_CHANNELS 217 | ||
1046 | #define WLC_GET_FAKEFRAG 218 | ||
1047 | #define WLC_SET_FAKEFRAG 219 | ||
1048 | #define WLC_GET_PWROUT_PERCENTAGE 220 | ||
1049 | #define WLC_SET_PWROUT_PERCENTAGE 221 | ||
1050 | #define WLC_SET_BAD_FRAME_PREEMPT 222 | ||
1051 | #define WLC_GET_BAD_FRAME_PREEMPT 223 | ||
1052 | #define WLC_SET_LEAP_LIST 224 | ||
1053 | #define WLC_GET_LEAP_LIST 225 | ||
1054 | #define WLC_GET_CWMIN 226 | ||
1055 | #define WLC_SET_CWMIN 227 | ||
1056 | #define WLC_GET_CWMAX 228 | ||
1057 | #define WLC_SET_CWMAX 229 | ||
1058 | #define WLC_GET_WET 230 | ||
1059 | #define WLC_SET_WET 231 | ||
1060 | #define WLC_GET_PUB 232 | ||
1061 | |||
1062 | |||
1063 | #define WLC_GET_KEY_PRIMARY 235 | ||
1064 | #define WLC_SET_KEY_PRIMARY 236 | ||
1065 | |||
1066 | #define WLC_GET_ACI_ARGS 238 | ||
1067 | #define WLC_SET_ACI_ARGS 239 | ||
1068 | #define WLC_UNSET_CALLBACK 240 | ||
1069 | #define WLC_SET_CALLBACK 241 | ||
1070 | #define WLC_GET_RADAR 242 | ||
1071 | #define WLC_SET_RADAR 243 | ||
1072 | #define WLC_SET_SPECT_MANAGMENT 244 | ||
1073 | #define WLC_GET_SPECT_MANAGMENT 245 | ||
1074 | #define WLC_WDS_GET_REMOTE_HWADDR 246 | ||
1075 | #define WLC_WDS_GET_WPA_SUP 247 | ||
1076 | #define WLC_SET_CS_SCAN_TIMER 248 | ||
1077 | #define WLC_GET_CS_SCAN_TIMER 249 | ||
1078 | #define WLC_MEASURE_REQUEST 250 | ||
1079 | #define WLC_INIT 251 | ||
1080 | #define WLC_SEND_QUIET 252 | ||
1081 | #define WLC_KEEPALIVE 253 | ||
1082 | #define WLC_SEND_PWR_CONSTRAINT 254 | ||
1083 | #define WLC_UPGRADE_STATUS 255 | ||
1084 | #define WLC_CURRENT_PWR 256 | ||
1085 | #define WLC_GET_SCAN_PASSIVE_TIME 257 | ||
1086 | #define WLC_SET_SCAN_PASSIVE_TIME 258 | ||
1087 | #define WLC_LEGACY_LINK_BEHAVIOR 259 | ||
1088 | #define WLC_GET_CHANNELS_IN_COUNTRY 260 | ||
1089 | #define WLC_GET_COUNTRY_LIST 261 | ||
1090 | #define WLC_GET_VAR 262 | ||
1091 | #define WLC_SET_VAR 263 | ||
1092 | #define WLC_NVRAM_GET 264 | ||
1093 | #define WLC_NVRAM_SET 265 | ||
1094 | #define WLC_NVRAM_DUMP 266 | ||
1095 | #define WLC_REBOOT 267 | ||
1096 | #define WLC_SET_WSEC_PMK 268 | ||
1097 | #define WLC_GET_AUTH_MODE 269 | ||
1098 | #define WLC_SET_AUTH_MODE 270 | ||
1099 | #define WLC_GET_WAKEENTRY 271 | ||
1100 | #define WLC_SET_WAKEENTRY 272 | ||
1101 | #define WLC_NDCONFIG_ITEM 273 | ||
1102 | #define WLC_NVOTPW 274 | ||
1103 | #define WLC_OTPW 275 | ||
1104 | #define WLC_IOV_BLOCK_GET 276 | ||
1105 | #define WLC_IOV_MODULES_GET 277 | ||
1106 | #define WLC_SOFT_RESET 278 | ||
1107 | #define WLC_GET_ALLOW_MODE 279 | ||
1108 | #define WLC_SET_ALLOW_MODE 280 | ||
1109 | #define WLC_GET_DESIRED_BSSID 281 | ||
1110 | #define WLC_SET_DESIRED_BSSID 282 | ||
1111 | #define WLC_DISASSOC_MYAP 283 | ||
1112 | #define WLC_GET_NBANDS 284 | ||
1113 | #define WLC_GET_BANDSTATES 285 | ||
1114 | #define WLC_GET_WLC_BSS_INFO 286 | ||
1115 | #define WLC_GET_ASSOC_INFO 287 | ||
1116 | #define WLC_GET_OID_PHY 288 | ||
1117 | #define WLC_SET_OID_PHY 289 | ||
1118 | #define WLC_SET_ASSOC_TIME 290 | ||
1119 | #define WLC_GET_DESIRED_SSID 291 | ||
1120 | #define WLC_GET_CHANSPEC 292 | ||
1121 | #define WLC_GET_ASSOC_STATE 293 | ||
1122 | #define WLC_SET_PHY_STATE 294 | ||
1123 | #define WLC_GET_SCAN_PENDING 295 | ||
1124 | #define WLC_GET_SCANREQ_PENDING 296 | ||
1125 | #define WLC_GET_PREV_ROAM_REASON 297 | ||
1126 | #define WLC_SET_PREV_ROAM_REASON 298 | ||
1127 | #define WLC_GET_BANDSTATES_PI 299 | ||
1128 | #define WLC_GET_PHY_STATE 300 | ||
1129 | #define WLC_GET_BSS_WPA_RSN 301 | ||
1130 | #define WLC_GET_BSS_WPA2_RSN 302 | ||
1131 | #define WLC_GET_BSS_BCN_TS 303 | ||
1132 | #define WLC_GET_INT_DISASSOC 304 | ||
1133 | #define WLC_SET_NUM_PEERS 305 | ||
1134 | #define WLC_GET_NUM_BSS 306 | ||
1135 | #define WLC_NPHY_SAMPLE_COLLECT 307 | ||
1136 | #define WLC_UM_PRIV 308 | ||
1137 | #define WLC_GET_CMD 309 | ||
1138 | |||
1139 | #define WLC_SET_INTERFERENCE_OVERRIDE_MODE 311 | ||
1140 | #define WLC_GET_INTERFERENCE_OVERRIDE_MODE 312 | ||
1141 | #define WLC_GET_WAI_RESTRICT 313 | ||
1142 | #define WLC_SET_WAI_RESTRICT 314 | ||
1143 | #define WLC_SET_WAI_REKEY 315 | ||
1144 | #define WLC_SET_PEAKRATE 316 | ||
1145 | #define WLC_GET_PEAKRATE 317 | ||
1146 | #define WLC_LAST 318 | ||
1147 | |||
1148 | #ifndef EPICTRL_COOKIE | ||
1149 | #define EPICTRL_COOKIE 0xABADCEDE | ||
1150 | #endif | ||
1151 | |||
1152 | |||
1153 | #define CMN_IOCTL_OFF 0x180 | ||
1154 | |||
1155 | |||
1156 | |||
1157 | |||
1158 | #define WL_OID_BASE 0xFFE41420 | ||
1159 | |||
1160 | |||
1161 | #define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE) | ||
1162 | #define OID_WL_GET_FORCELINK (WL_OID_BASE + WLC_GET_FORCELINK) | ||
1163 | #define OID_WL_SET_FORCELINK (WL_OID_BASE + WLC_SET_FORCELINK) | ||
1164 | #define OID_WL_ENCRYPT_STRENGTH (WL_OID_BASE + WLC_ENCRYPT_STRENGTH) | ||
1165 | #define OID_WL_DECRYPT_STATUS (WL_OID_BASE + WLC_DECRYPT_STATUS) | ||
1166 | #define OID_LEGACY_LINK_BEHAVIOR (WL_OID_BASE + WLC_LEGACY_LINK_BEHAVIOR) | ||
1167 | #define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM) | ||
1168 | |||
1169 | |||
1170 | #define OID_STA_CHANSPEC (WL_OID_BASE + WLC_GET_CHANSPEC) | ||
1171 | #define OID_STA_NBANDS (WL_OID_BASE + WLC_GET_NBANDS) | ||
1172 | #define OID_STA_GET_PHY (WL_OID_BASE + WLC_GET_OID_PHY) | ||
1173 | #define OID_STA_SET_PHY (WL_OID_BASE + WLC_SET_OID_PHY) | ||
1174 | #define OID_STA_ASSOC_TIME (WL_OID_BASE + WLC_SET_ASSOC_TIME) | ||
1175 | #define OID_STA_DESIRED_SSID (WL_OID_BASE + WLC_GET_DESIRED_SSID) | ||
1176 | #define OID_STA_SET_PHY_STATE (WL_OID_BASE + WLC_SET_PHY_STATE) | ||
1177 | #define OID_STA_SCAN_PENDING (WL_OID_BASE + WLC_GET_SCAN_PENDING) | ||
1178 | #define OID_STA_SCANREQ_PENDING (WL_OID_BASE + WLC_GET_SCANREQ_PENDING) | ||
1179 | #define OID_STA_GET_ROAM_REASON (WL_OID_BASE + WLC_GET_PREV_ROAM_REASON) | ||
1180 | #define OID_STA_SET_ROAM_REASON (WL_OID_BASE + WLC_SET_PREV_ROAM_REASON) | ||
1181 | #define OID_STA_GET_PHY_STATE (WL_OID_BASE + WLC_GET_PHY_STATE) | ||
1182 | #define OID_STA_INT_DISASSOC (WL_OID_BASE + WLC_GET_INT_DISASSOC) | ||
1183 | #define OID_STA_SET_NUM_PEERS (WL_OID_BASE + WLC_SET_NUM_PEERS) | ||
1184 | #define OID_STA_GET_NUM_BSS (WL_OID_BASE + WLC_GET_NUM_BSS) | ||
1185 | |||
1186 | #define WL_DECRYPT_STATUS_SUCCESS 1 | ||
1187 | #define WL_DECRYPT_STATUS_FAILURE 2 | ||
1188 | #define WL_DECRYPT_STATUS_UNKNOWN 3 | ||
1189 | |||
1190 | |||
1191 | #define WLC_UPGRADE_SUCCESS 0 | ||
1192 | #define WLC_UPGRADE_PENDING 1 | ||
1193 | |||
1194 | #ifdef CONFIG_USBRNDIS_RETAIL | ||
1195 | |||
1196 | typedef struct { | ||
1197 | char *name; | ||
1198 | void *param; | ||
1199 | } ndconfig_item_t; | ||
1200 | #endif | ||
1201 | |||
1202 | |||
1203 | |||
1204 | #define WL_AUTH_OPEN_SYSTEM 0 | ||
1205 | #define WL_AUTH_SHARED_KEY 1 | ||
1206 | #define WL_AUTH_OPEN_SHARED 2 | ||
1207 | |||
1208 | |||
1209 | #define WL_RADIO_SW_DISABLE (1<<0) | ||
1210 | #define WL_RADIO_HW_DISABLE (1<<1) | ||
1211 | #define WL_RADIO_MPC_DISABLE (1<<2) | ||
1212 | #define WL_RADIO_COUNTRY_DISABLE (1<<3) | ||
1213 | |||
1214 | #define WL_SPURAVOID_OFF 0 | ||
1215 | #define WL_SPURAVOID_ON1 1 | ||
1216 | #define WL_SPURAVOID_ON2 2 | ||
1217 | |||
1218 | |||
1219 | #define WL_TXPWR_OVERRIDE (1U<<31) | ||
1220 | #define WL_TXPWR_NEG (1U<<30) | ||
1221 | |||
1222 | #define WL_PHY_PAVARS_LEN 6 | ||
1223 | |||
1224 | #define WL_PHY_PAVARS2_NUM 3 | ||
1225 | #define WL_PHY_PAVAR_VER 1 | ||
1226 | typedef struct wl_pavars2 { | ||
1227 | uint16 ver; | ||
1228 | uint16 len; | ||
1229 | uint16 inuse; | ||
1230 | uint16 phy_type; | ||
1231 | uint16 bandrange; | ||
1232 | uint16 chain; | ||
1233 | uint16 inpa[WL_PHY_PAVARS2_NUM]; | ||
1234 | } wl_pavars2_t; | ||
1235 | |||
1236 | typedef struct wl_po { | ||
1237 | uint16 phy_type; | ||
1238 | uint16 band; | ||
1239 | uint16 cckpo; | ||
1240 | uint32 ofdmpo; | ||
1241 | uint16 mcspo[8]; | ||
1242 | } wl_po_t; | ||
1243 | |||
1244 | |||
1245 | #define WLC_TXPWR_MAX (127) | ||
1246 | |||
1247 | |||
1248 | #define WL_DIAG_INTERRUPT 1 | ||
1249 | #define WL_DIAG_LOOPBACK 2 | ||
1250 | #define WL_DIAG_MEMORY 3 | ||
1251 | #define WL_DIAG_LED 4 | ||
1252 | #define WL_DIAG_REG 5 | ||
1253 | #define WL_DIAG_SROM 6 | ||
1254 | #define WL_DIAG_DMA 7 | ||
1255 | |||
1256 | #define WL_DIAGERR_SUCCESS 0 | ||
1257 | #define WL_DIAGERR_FAIL_TO_RUN 1 | ||
1258 | #define WL_DIAGERR_NOT_SUPPORTED 2 | ||
1259 | #define WL_DIAGERR_INTERRUPT_FAIL 3 | ||
1260 | #define WL_DIAGERR_LOOPBACK_FAIL 4 | ||
1261 | #define WL_DIAGERR_SROM_FAIL 5 | ||
1262 | #define WL_DIAGERR_SROM_BADCRC 6 | ||
1263 | #define WL_DIAGERR_REG_FAIL 7 | ||
1264 | #define WL_DIAGERR_MEMORY_FAIL 8 | ||
1265 | #define WL_DIAGERR_NOMEM 9 | ||
1266 | #define WL_DIAGERR_DMA_FAIL 10 | ||
1267 | |||
1268 | #define WL_DIAGERR_MEMORY_TIMEOUT 11 | ||
1269 | #define WL_DIAGERR_MEMORY_BADPATTERN 12 | ||
1270 | |||
1271 | |||
1272 | #define WLC_BAND_AUTO 0 | ||
1273 | #define WLC_BAND_5G 1 | ||
1274 | #define WLC_BAND_2G 2 | ||
1275 | #define WLC_BAND_ALL 3 | ||
1276 | |||
1277 | |||
1278 | #define WL_CHAN_FREQ_RANGE_2G 0 | ||
1279 | #define WL_CHAN_FREQ_RANGE_5GL 1 | ||
1280 | #define WL_CHAN_FREQ_RANGE_5GM 2 | ||
1281 | #define WL_CHAN_FREQ_RANGE_5GH 3 | ||
1282 | |||
1283 | #define WL_CHAN_FREQ_RANGE_5GLL_VER2 4 | ||
1284 | #define WL_CHAN_FREQ_RANGE_5GLH_VER2 5 | ||
1285 | #define WL_CHAN_FREQ_RANGE_5GML_VER2 6 | ||
1286 | #define WL_CHAN_FREQ_RANGE_5GMH_VER2 7 | ||
1287 | #define WL_CHAN_FREQ_RANGE_5GH_VER2 8 | ||
1288 | |||
1289 | #define WL_CHAN_FREQ_RANGE_5GLL_5BAND 4 | ||
1290 | #define WL_CHAN_FREQ_RANGE_5GLH_5BAND 5 | ||
1291 | #define WL_CHAN_FREQ_RANGE_5GML_5BAND 6 | ||
1292 | #define WL_CHAN_FREQ_RANGE_5GMH_5BAND 7 | ||
1293 | #define WL_CHAN_FREQ_RANGE_5GH_5BAND 8 | ||
1294 | |||
1295 | |||
1296 | #define WLC_PHY_TYPE_A 0 | ||
1297 | #define WLC_PHY_TYPE_B 1 | ||
1298 | #define WLC_PHY_TYPE_G 2 | ||
1299 | #define WLC_PHY_TYPE_N 4 | ||
1300 | #define WLC_PHY_TYPE_LP 5 | ||
1301 | #define WLC_PHY_TYPE_SSN 6 | ||
1302 | #define WLC_PHY_TYPE_HT 7 | ||
1303 | #define WLC_PHY_TYPE_LCN 8 | ||
1304 | #define WLC_PHY_TYPE_NULL 0xf | ||
1305 | |||
1306 | |||
1307 | #define WLC_MACMODE_DISABLED 0 | ||
1308 | #define WLC_MACMODE_DENY 1 | ||
1309 | #define WLC_MACMODE_ALLOW 2 | ||
1310 | |||
1311 | |||
1312 | #define GMODE_LEGACY_B 0 | ||
1313 | #define GMODE_AUTO 1 | ||
1314 | #define GMODE_ONLY 2 | ||
1315 | #define GMODE_B_DEFERRED 3 | ||
1316 | #define GMODE_PERFORMANCE 4 | ||
1317 | #define GMODE_LRS 5 | ||
1318 | #define GMODE_MAX 6 | ||
1319 | |||
1320 | |||
1321 | #define WLC_PLCP_AUTO -1 | ||
1322 | #define WLC_PLCP_SHORT 0 | ||
1323 | #define WLC_PLCP_LONG 1 | ||
1324 | |||
1325 | |||
1326 | #define WLC_PROTECTION_AUTO -1 | ||
1327 | #define WLC_PROTECTION_OFF 0 | ||
1328 | #define WLC_PROTECTION_ON 1 | ||
1329 | #define WLC_PROTECTION_MMHDR_ONLY 2 | ||
1330 | #define WLC_PROTECTION_CTS_ONLY 3 | ||
1331 | |||
1332 | |||
1333 | #define WLC_PROTECTION_CTL_OFF 0 | ||
1334 | #define WLC_PROTECTION_CTL_LOCAL 1 | ||
1335 | #define WLC_PROTECTION_CTL_OVERLAP 2 | ||
1336 | |||
1337 | |||
1338 | #define WLC_N_PROTECTION_OFF 0 | ||
1339 | #define WLC_N_PROTECTION_OPTIONAL 1 | ||
1340 | #define WLC_N_PROTECTION_20IN40 2 | ||
1341 | #define WLC_N_PROTECTION_MIXEDMODE 3 | ||
1342 | |||
1343 | |||
1344 | #define WLC_N_PREAMBLE_MIXEDMODE 0 | ||
1345 | #define WLC_N_PREAMBLE_GF 1 | ||
1346 | #define WLC_N_PREAMBLE_GF_BRCM 2 | ||
1347 | |||
1348 | |||
1349 | #define WLC_N_BW_20ALL 0 | ||
1350 | #define WLC_N_BW_40ALL 1 | ||
1351 | #define WLC_N_BW_20IN2G_40IN5G 2 | ||
1352 | |||
1353 | |||
1354 | #define WLC_N_TXRX_CHAIN0 0 | ||
1355 | #define WLC_N_TXRX_CHAIN1 1 | ||
1356 | |||
1357 | |||
1358 | #define WLC_N_SGI_20 0x01 | ||
1359 | #define WLC_N_SGI_40 0x02 | ||
1360 | |||
1361 | |||
1362 | #define PM_OFF 0 | ||
1363 | #define PM_MAX 1 | ||
1364 | #define PM_FAST 2 | ||
1365 | |||
1366 | #define LISTEN_INTERVAL 10 | ||
1367 | |||
1368 | #define INTERFERE_OVRRIDE_OFF -1 | ||
1369 | #define INTERFERE_NONE 0 | ||
1370 | #define NON_WLAN 1 | ||
1371 | #define WLAN_MANUAL 2 | ||
1372 | #define WLAN_AUTO 3 | ||
1373 | #define WLAN_AUTO_W_NOISE 4 | ||
1374 | #define AUTO_ACTIVE (1 << 7) | ||
1375 | |||
1376 | typedef struct wl_aci_args { | ||
1377 | int enter_aci_thresh; | ||
1378 | int exit_aci_thresh; | ||
1379 | int usec_spin; | ||
1380 | int glitch_delay; | ||
1381 | uint16 nphy_adcpwr_enter_thresh; | ||
1382 | uint16 nphy_adcpwr_exit_thresh; | ||
1383 | uint16 nphy_repeat_ctr; | ||
1384 | uint16 nphy_num_samples; | ||
1385 | uint16 nphy_undetect_window_sz; | ||
1386 | uint16 nphy_b_energy_lo_aci; | ||
1387 | uint16 nphy_b_energy_md_aci; | ||
1388 | uint16 nphy_b_energy_hi_aci; | ||
1389 | uint16 nphy_noise_noassoc_glitch_th_up; | ||
1390 | uint16 nphy_noise_noassoc_glitch_th_dn; | ||
1391 | uint16 nphy_noise_assoc_glitch_th_up; | ||
1392 | uint16 nphy_noise_assoc_glitch_th_dn; | ||
1393 | uint16 nphy_noise_assoc_aci_glitch_th_up; | ||
1394 | uint16 nphy_noise_assoc_aci_glitch_th_dn; | ||
1395 | uint16 nphy_noise_assoc_enter_th; | ||
1396 | uint16 nphy_noise_noassoc_enter_th; | ||
1397 | uint16 nphy_noise_assoc_rx_glitch_badplcp_enter_th; | ||
1398 | uint16 nphy_noise_noassoc_crsidx_incr; | ||
1399 | uint16 nphy_noise_assoc_crsidx_incr; | ||
1400 | uint16 nphy_noise_crsidx_decr; | ||
1401 | } wl_aci_args_t; | ||
1402 | |||
1403 | #define TRIGGER_NOW 0 | ||
1404 | #define TRIGGER_CRS 0x01 | ||
1405 | #define TRIGGER_CRSDEASSERT 0x02 | ||
1406 | #define TRIGGER_GOODFCS 0x04 | ||
1407 | #define TRIGGER_BADFCS 0x08 | ||
1408 | #define TRIGGER_BADPLCP 0x10 | ||
1409 | #define TRIGGER_CRSGLITCH 0x20 | ||
1410 | #define WL_ACI_ARGS_LEGACY_LENGTH 16 | ||
1411 | #define WL_SAMPLECOLLECT_T_VERSION 1 | ||
1412 | typedef struct wl_samplecollect_args { | ||
1413 | |||
1414 | uint8 coll_us; | ||
1415 | int cores; | ||
1416 | |||
1417 | uint16 version; | ||
1418 | uint16 length; | ||
1419 | uint8 trigger; | ||
1420 | uint16 timeout; | ||
1421 | uint16 mode; | ||
1422 | uint32 pre_dur; | ||
1423 | uint32 post_dur; | ||
1424 | uint8 gpio_sel; | ||
1425 | bool downsamp; | ||
1426 | bool be_deaf; | ||
1427 | bool agc; | ||
1428 | bool filter; | ||
1429 | } wl_samplecollect_args_t; | ||
1430 | |||
1431 | #define WL_SAMPLEDATA_HEADER_TYPE 1 | ||
1432 | #define WL_SAMPLEDATA_HEADER_SIZE 80 | ||
1433 | #define WL_SAMPLEDATA_TYPE 2 | ||
1434 | #define WL_SAMPLEDATA_SEQ 0xff | ||
1435 | #define WL_SAMPLEDATA_MORE_DATA 0x100 | ||
1436 | #define WL_SAMPLEDATA_T_VERSION 1 | ||
1437 | |||
1438 | #define WL_SAMPLEDATA_T_VERSION_SPEC_AN 2 | ||
1439 | |||
1440 | typedef struct wl_sampledata { | ||
1441 | uint16 version; | ||
1442 | uint16 size; | ||
1443 | uint16 tag; | ||
1444 | uint16 length; | ||
1445 | uint32 flag; | ||
1446 | } wl_sampledata_t; | ||
1447 | |||
1448 | |||
1449 | |||
1450 | #define WL_ERROR_VAL 0x00000001 | ||
1451 | #define WL_TRACE_VAL 0x00000002 | ||
1452 | #define WL_PRHDRS_VAL 0x00000004 | ||
1453 | #define WL_PRPKT_VAL 0x00000008 | ||
1454 | #define WL_INFORM_VAL 0x00000010 | ||
1455 | #define WL_TMP_VAL 0x00000020 | ||
1456 | #define WL_OID_VAL 0x00000040 | ||
1457 | #define WL_RATE_VAL 0x00000080 | ||
1458 | #define WL_ASSOC_VAL 0x00000100 | ||
1459 | #define WL_PRUSR_VAL 0x00000200 | ||
1460 | #define WL_PS_VAL 0x00000400 | ||
1461 | #define WL_TXPWR_VAL 0x00000800 | ||
1462 | #define WL_PORT_VAL 0x00001000 | ||
1463 | #define WL_DUAL_VAL 0x00002000 | ||
1464 | #define WL_WSEC_VAL 0x00004000 | ||
1465 | #define WL_WSEC_DUMP_VAL 0x00008000 | ||
1466 | #define WL_LOG_VAL 0x00010000 | ||
1467 | #define WL_NRSSI_VAL 0x00020000 | ||
1468 | #define WL_LOFT_VAL 0x00040000 | ||
1469 | #define WL_REGULATORY_VAL 0x00080000 | ||
1470 | #define WL_PHYCAL_VAL 0x00100000 | ||
1471 | #define WL_RADAR_VAL 0x00200000 | ||
1472 | #define WL_MPC_VAL 0x00400000 | ||
1473 | #define WL_APSTA_VAL 0x00800000 | ||
1474 | #define WL_DFS_VAL 0x01000000 | ||
1475 | #define WL_BA_VAL 0x02000000 | ||
1476 | #define WL_ACI_VAL 0x04000000 | ||
1477 | #define WL_MBSS_VAL 0x04000000 | ||
1478 | #define WL_CAC_VAL 0x08000000 | ||
1479 | #define WL_AMSDU_VAL 0x10000000 | ||
1480 | #define WL_AMPDU_VAL 0x20000000 | ||
1481 | #define WL_FFPLD_VAL 0x40000000 | ||
1482 | |||
1483 | |||
1484 | #define WL_DPT_VAL 0x00000001 | ||
1485 | #define WL_SCAN_VAL 0x00000002 | ||
1486 | #define WL_WOWL_VAL 0x00000004 | ||
1487 | #define WL_COEX_VAL 0x00000008 | ||
1488 | #define WL_RTDC_VAL 0x00000010 | ||
1489 | #define WL_PROTO_VAL 0x00000020 | ||
1490 | #define WL_BTA_VAL 0x00000040 | ||
1491 | #define WL_CHANINT_VAL 0x00000080 | ||
1492 | #define WL_THERMAL_VAL 0x00000100 | ||
1493 | #define WL_P2P_VAL 0x00000200 | ||
1494 | #define WL_TXRX_VAL 0x00000400 | ||
1495 | #define WL_MCHAN_VAL 0x00000800 | ||
1496 | |||
1497 | |||
1498 | #define WL_LED_NUMGPIO 16 | ||
1499 | |||
1500 | |||
1501 | #define WL_LED_OFF 0 | ||
1502 | #define WL_LED_ON 1 | ||
1503 | #define WL_LED_ACTIVITY 2 | ||
1504 | #define WL_LED_RADIO 3 | ||
1505 | #define WL_LED_ARADIO 4 | ||
1506 | #define WL_LED_BRADIO 5 | ||
1507 | #define WL_LED_BGMODE 6 | ||
1508 | #define WL_LED_WI1 7 | ||
1509 | #define WL_LED_WI2 8 | ||
1510 | #define WL_LED_WI3 9 | ||
1511 | #define WL_LED_ASSOC 10 | ||
1512 | #define WL_LED_INACTIVE 11 | ||
1513 | #define WL_LED_ASSOCACT 12 | ||
1514 | #define WL_LED_WI4 13 | ||
1515 | #define WL_LED_WI5 14 | ||
1516 | #define WL_LED_BLINKSLOW 15 | ||
1517 | #define WL_LED_BLINKMED 16 | ||
1518 | #define WL_LED_BLINKFAST 17 | ||
1519 | #define WL_LED_BLINKCUSTOM 18 | ||
1520 | #define WL_LED_BLINKPERIODIC 19 | ||
1521 | #define WL_LED_ASSOC_WITH_SEC 20 | ||
1522 | |||
1523 | #define WL_LED_START_OFF 21 | ||
1524 | #define WL_LED_NUMBEHAVIOR 22 | ||
1525 | |||
1526 | |||
1527 | #define WL_LED_BEH_MASK 0x7f | ||
1528 | #define WL_LED_AL_MASK 0x80 | ||
1529 | |||
1530 | |||
1531 | #define WL_NUMCHANNELS 64 | ||
1532 | #define WL_NUMCHANSPECS 100 | ||
1533 | |||
1534 | |||
1535 | #define WL_WDS_WPA_ROLE_AUTH 0 | ||
1536 | #define WL_WDS_WPA_ROLE_SUP 1 | ||
1537 | #define WL_WDS_WPA_ROLE_AUTO 255 | ||
1538 | |||
1539 | |||
1540 | #define WL_EVENTING_MASK_LEN 16 | ||
1541 | |||
1542 | |||
1543 | |||
1544 | |||
1545 | #define WL_JOIN_PREF_RSSI 1 | ||
1546 | #define WL_JOIN_PREF_WPA 2 | ||
1547 | #define WL_JOIN_PREF_BAND 3 | ||
1548 | #define WL_JOIN_PREF_RSSI_DELTA 4 | ||
1549 | #define WL_JOIN_PREF_TRANS_PREF 5 | ||
1550 | |||
1551 | |||
1552 | #define WLJP_BAND_ASSOC_PREF 255 | ||
1553 | |||
1554 | |||
1555 | #define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00" | ||
1556 | |||
1557 | struct tsinfo_arg { | ||
1558 | uint8 octets[3]; | ||
1559 | }; | ||
1560 | |||
1561 | #define NFIFO 6 | ||
1562 | |||
1563 | #define WL_CNT_T_VERSION 6 | ||
1564 | |||
1565 | typedef struct { | ||
1566 | uint16 version; | ||
1567 | uint16 length; | ||
1568 | |||
1569 | |||
1570 | uint32 txframe; | ||
1571 | uint32 txbyte; | ||
1572 | uint32 txretrans; | ||
1573 | uint32 txerror; | ||
1574 | uint32 txctl; | ||
1575 | uint32 txprshort; | ||
1576 | uint32 txserr; | ||
1577 | uint32 txnobuf; | ||
1578 | uint32 txnoassoc; | ||
1579 | uint32 txrunt; | ||
1580 | uint32 txchit; | ||
1581 | uint32 txcmiss; | ||
1582 | |||
1583 | |||
1584 | uint32 txuflo; | ||
1585 | uint32 txphyerr; | ||
1586 | uint32 txphycrs; | ||
1587 | |||
1588 | |||
1589 | uint32 rxframe; | ||
1590 | uint32 rxbyte; | ||
1591 | uint32 rxerror; | ||
1592 | uint32 rxctl; | ||
1593 | uint32 rxnobuf; | ||
1594 | uint32 rxnondata; | ||
1595 | uint32 rxbadds; | ||
1596 | uint32 rxbadcm; | ||
1597 | uint32 rxfragerr; | ||
1598 | uint32 rxrunt; | ||
1599 | uint32 rxgiant; | ||
1600 | uint32 rxnoscb; | ||
1601 | uint32 rxbadproto; | ||
1602 | uint32 rxbadsrcmac; | ||
1603 | uint32 rxbadda; | ||
1604 | uint32 rxfilter; | ||
1605 | |||
1606 | |||
1607 | uint32 rxoflo; | ||
1608 | uint32 rxuflo[NFIFO]; | ||
1609 | |||
1610 | uint32 d11cnt_txrts_off; | ||
1611 | uint32 d11cnt_rxcrc_off; | ||
1612 | uint32 d11cnt_txnocts_off; | ||
1613 | |||
1614 | |||
1615 | uint32 dmade; | ||
1616 | uint32 dmada; | ||
1617 | uint32 dmape; | ||
1618 | uint32 reset; | ||
1619 | uint32 tbtt; | ||
1620 | uint32 txdmawar; | ||
1621 | uint32 pkt_callback_reg_fail; | ||
1622 | |||
1623 | |||
1624 | uint32 txallfrm; | ||
1625 | uint32 txrtsfrm; | ||
1626 | uint32 txctsfrm; | ||
1627 | uint32 txackfrm; | ||
1628 | uint32 txdnlfrm; | ||
1629 | uint32 txbcnfrm; | ||
1630 | uint32 txfunfl[8]; | ||
1631 | uint32 txtplunfl; | ||
1632 | uint32 txphyerror; | ||
1633 | uint32 rxfrmtoolong; | ||
1634 | uint32 rxfrmtooshrt; | ||
1635 | uint32 rxinvmachdr; | ||
1636 | uint32 rxbadfcs; | ||
1637 | uint32 rxbadplcp; | ||
1638 | uint32 rxcrsglitch; | ||
1639 | uint32 rxstrt; | ||
1640 | uint32 rxdfrmucastmbss; | ||
1641 | uint32 rxmfrmucastmbss; | ||
1642 | uint32 rxcfrmucast; | ||
1643 | uint32 rxrtsucast; | ||
1644 | uint32 rxctsucast; | ||
1645 | uint32 rxackucast; | ||
1646 | uint32 rxdfrmocast; | ||
1647 | uint32 rxmfrmocast; | ||
1648 | uint32 rxcfrmocast; | ||
1649 | uint32 rxrtsocast; | ||
1650 | uint32 rxctsocast; | ||
1651 | uint32 rxdfrmmcast; | ||
1652 | uint32 rxmfrmmcast; | ||
1653 | uint32 rxcfrmmcast; | ||
1654 | uint32 rxbeaconmbss; | ||
1655 | uint32 rxdfrmucastobss; | ||
1656 | uint32 rxbeaconobss; | ||
1657 | uint32 rxrsptmout; | ||
1658 | uint32 bcntxcancl; | ||
1659 | uint32 rxf0ovfl; | ||
1660 | uint32 rxf1ovfl; | ||
1661 | uint32 rxf2ovfl; | ||
1662 | uint32 txsfovfl; | ||
1663 | uint32 pmqovfl; | ||
1664 | uint32 rxcgprqfrm; | ||
1665 | uint32 rxcgprsqovfl; | ||
1666 | uint32 txcgprsfail; | ||
1667 | uint32 txcgprssuc; | ||
1668 | uint32 prs_timeout; | ||
1669 | uint32 rxnack; | ||
1670 | uint32 frmscons; | ||
1671 | uint32 txnack; | ||
1672 | uint32 txglitch_nack; | ||
1673 | uint32 txburst; | ||
1674 | |||
1675 | |||
1676 | uint32 txfrag; | ||
1677 | uint32 txmulti; | ||
1678 | uint32 txfail; | ||
1679 | uint32 txretry; | ||
1680 | uint32 txretrie; | ||
1681 | uint32 rxdup; | ||
1682 | uint32 txrts; | ||
1683 | uint32 txnocts; | ||
1684 | uint32 txnoack; | ||
1685 | uint32 rxfrag; | ||
1686 | uint32 rxmulti; | ||
1687 | uint32 rxcrc; | ||
1688 | uint32 txfrmsnt; | ||
1689 | uint32 rxundec; | ||
1690 | |||
1691 | |||
1692 | uint32 tkipmicfaill; | ||
1693 | uint32 tkipcntrmsr; | ||
1694 | uint32 tkipreplay; | ||
1695 | uint32 ccmpfmterr; | ||
1696 | uint32 ccmpreplay; | ||
1697 | uint32 ccmpundec; | ||
1698 | uint32 fourwayfail; | ||
1699 | uint32 wepundec; | ||
1700 | uint32 wepicverr; | ||
1701 | uint32 decsuccess; | ||
1702 | uint32 tkipicverr; | ||
1703 | uint32 wepexcluded; | ||
1704 | |||
1705 | uint32 rxundec_mcst; | ||
1706 | |||
1707 | |||
1708 | uint32 tkipmicfaill_mcst; | ||
1709 | uint32 tkipcntrmsr_mcst; | ||
1710 | uint32 tkipreplay_mcst; | ||
1711 | uint32 ccmpfmterr_mcst; | ||
1712 | uint32 ccmpreplay_mcst; | ||
1713 | uint32 ccmpundec_mcst; | ||
1714 | uint32 fourwayfail_mcst; | ||
1715 | uint32 wepundec_mcst; | ||
1716 | uint32 wepicverr_mcst; | ||
1717 | uint32 decsuccess_mcst; | ||
1718 | uint32 tkipicverr_mcst; | ||
1719 | uint32 wepexcluded_mcst; | ||
1720 | |||
1721 | uint32 txchanrej; | ||
1722 | uint32 txexptime; | ||
1723 | uint32 psmwds; | ||
1724 | uint32 phywatchdog; | ||
1725 | |||
1726 | |||
1727 | uint32 prq_entries_handled; | ||
1728 | uint32 prq_undirected_entries; | ||
1729 | uint32 prq_bad_entries; | ||
1730 | uint32 atim_suppress_count; | ||
1731 | uint32 bcn_template_not_ready; | ||
1732 | uint32 bcn_template_not_ready_done; | ||
1733 | uint32 late_tbtt_dpc; | ||
1734 | |||
1735 | |||
1736 | uint32 rx1mbps; | ||
1737 | uint32 rx2mbps; | ||
1738 | uint32 rx5mbps5; | ||
1739 | uint32 rx6mbps; | ||
1740 | uint32 rx9mbps; | ||
1741 | uint32 rx11mbps; | ||
1742 | uint32 rx12mbps; | ||
1743 | uint32 rx18mbps; | ||
1744 | uint32 rx24mbps; | ||
1745 | uint32 rx36mbps; | ||
1746 | uint32 rx48mbps; | ||
1747 | uint32 rx54mbps; | ||
1748 | uint32 rx108mbps; | ||
1749 | uint32 rx162mbps; | ||
1750 | uint32 rx216mbps; | ||
1751 | uint32 rx270mbps; | ||
1752 | uint32 rx324mbps; | ||
1753 | uint32 rx378mbps; | ||
1754 | uint32 rx432mbps; | ||
1755 | uint32 rx486mbps; | ||
1756 | uint32 rx540mbps; | ||
1757 | |||
1758 | |||
1759 | uint32 pktengrxducast; | ||
1760 | uint32 pktengrxdmcast; | ||
1761 | |||
1762 | uint32 rfdisable; | ||
1763 | uint32 bphy_rxcrsglitch; | ||
1764 | |||
1765 | uint32 txmpdu_sgi; | ||
1766 | uint32 rxmpdu_sgi; | ||
1767 | uint32 txmpdu_stbc; | ||
1768 | uint32 rxmpdu_stbc; | ||
1769 | } wl_cnt_t; | ||
1770 | |||
1771 | |||
1772 | #define WL_WME_CNT_VERSION 1 | ||
1773 | |||
1774 | typedef struct { | ||
1775 | uint32 packets; | ||
1776 | uint32 bytes; | ||
1777 | } wl_traffic_stats_t; | ||
1778 | |||
1779 | typedef struct { | ||
1780 | uint16 version; | ||
1781 | uint16 length; | ||
1782 | |||
1783 | wl_traffic_stats_t tx[AC_COUNT]; | ||
1784 | wl_traffic_stats_t tx_failed[AC_COUNT]; | ||
1785 | wl_traffic_stats_t rx[AC_COUNT]; | ||
1786 | wl_traffic_stats_t rx_failed[AC_COUNT]; | ||
1787 | |||
1788 | wl_traffic_stats_t forward[AC_COUNT]; | ||
1789 | |||
1790 | wl_traffic_stats_t tx_expired[AC_COUNT]; | ||
1791 | |||
1792 | } wl_wme_cnt_t; | ||
1793 | |||
1794 | struct wl_msglevel2 { | ||
1795 | uint32 low; | ||
1796 | uint32 high; | ||
1797 | }; | ||
1798 | |||
1799 | typedef struct wl_mkeep_alive_pkt { | ||
1800 | uint16 version; | ||
1801 | uint16 length; | ||
1802 | uint32 period_msec; | ||
1803 | uint16 len_bytes; | ||
1804 | uint8 keep_alive_id; | ||
1805 | uint8 data[1]; | ||
1806 | } wl_mkeep_alive_pkt_t; | ||
1807 | |||
1808 | #define WL_MKEEP_ALIVE_VERSION 1 | ||
1809 | #define WL_MKEEP_ALIVE_FIXED_LEN OFFSETOF(wl_mkeep_alive_pkt_t, data) | ||
1810 | #define WL_MKEEP_ALIVE_PRECISION 500 | ||
1811 | |||
1812 | #define WLC_ROAM_TRIGGER_DEFAULT 0 | ||
1813 | #define WLC_ROAM_TRIGGER_BANDWIDTH 1 | ||
1814 | #define WLC_ROAM_TRIGGER_DISTANCE 2 | ||
1815 | #define WLC_ROAM_TRIGGER_AUTO 3 | ||
1816 | #define WLC_ROAM_TRIGGER_MAX_VALUE 3 | ||
1817 | |||
1818 | |||
1819 | #define WPA_AUTH_PFN_ANY 0xffffffff | ||
1820 | |||
1821 | enum { | ||
1822 | PFN_LIST_ORDER, | ||
1823 | PFN_RSSI | ||
1824 | }; | ||
1825 | |||
1826 | enum { | ||
1827 | DISABLE, | ||
1828 | ENABLE | ||
1829 | }; | ||
1830 | |||
1831 | enum { | ||
1832 | OFF_ADAPT, | ||
1833 | SMART_ADAPT, | ||
1834 | STRICT_ADAPT, | ||
1835 | SLOW_ADAPT | ||
1836 | }; | ||
1837 | |||
1838 | #define SORT_CRITERIA_BIT 0 | ||
1839 | #define AUTO_NET_SWITCH_BIT 1 | ||
1840 | #define ENABLE_BKGRD_SCAN_BIT 2 | ||
1841 | #define IMMEDIATE_SCAN_BIT 3 | ||
1842 | #define AUTO_CONNECT_BIT 4 | ||
1843 | #define ENABLE_BD_SCAN_BIT 5 | ||
1844 | #define ENABLE_ADAPTSCAN_BIT 6 | ||
1845 | #define IMMEDIATE_EVENT_BIT 8 | ||
1846 | |||
1847 | #define SORT_CRITERIA_MASK 0x0001 | ||
1848 | #define AUTO_NET_SWITCH_MASK 0x0002 | ||
1849 | #define ENABLE_BKGRD_SCAN_MASK 0x0004 | ||
1850 | #define IMMEDIATE_SCAN_MASK 0x0008 | ||
1851 | #define AUTO_CONNECT_MASK 0x0010 | ||
1852 | #define ENABLE_BD_SCAN_MASK 0x0020 | ||
1853 | #define ENABLE_ADAPTSCAN_MASK 0x00c0 | ||
1854 | #define IMMEDIATE_EVENT_MASK 0x0100 | ||
1855 | |||
1856 | #define PFN_VERSION 2 | ||
1857 | #define PFN_SCANRESULT_VERSION 1 | ||
1858 | #define MAX_PFN_LIST_COUNT 16 | ||
1859 | |||
1860 | #define PFN_COMPLETE 1 | ||
1861 | #define PFN_INCOMPLETE 0 | ||
1862 | |||
1863 | #define DEFAULT_BESTN 2 | ||
1864 | #define DEFAULT_MSCAN 0 | ||
1865 | #define DEFAULT_REPEAT 10 | ||
1866 | #define DEFAULT_EXP 2 | ||
1867 | |||
1868 | |||
1869 | typedef struct wl_pfn_subnet_info { | ||
1870 | struct ether_addr BSSID; | ||
1871 | uint8 channel; | ||
1872 | uint8 SSID_len; | ||
1873 | uint8 SSID[32]; | ||
1874 | } wl_pfn_subnet_info_t; | ||
1875 | |||
1876 | typedef struct wl_pfn_net_info { | ||
1877 | wl_pfn_subnet_info_t pfnsubnet; | ||
1878 | int16 RSSI; | ||
1879 | uint16 timestamp; | ||
1880 | } wl_pfn_net_info_t; | ||
1881 | |||
1882 | typedef struct wl_pfn_scanresults { | ||
1883 | uint32 version; | ||
1884 | uint32 status; | ||
1885 | uint32 count; | ||
1886 | wl_pfn_net_info_t netinfo[1]; | ||
1887 | } wl_pfn_scanresults_t; | ||
1888 | |||
1889 | |||
1890 | typedef struct wl_pfn_param { | ||
1891 | int32 version; | ||
1892 | int32 scan_freq; | ||
1893 | int32 lost_network_timeout; | ||
1894 | int16 flags; | ||
1895 | int16 rssi_margin; | ||
1896 | uint8 bestn; | ||
1897 | uint8 mscan; | ||
1898 | uint8 repeat; | ||
1899 | uint8 exp; | ||
1900 | int32 slow_freq; | ||
1901 | } wl_pfn_param_t; | ||
1902 | |||
1903 | typedef struct wl_pfn_bssid { | ||
1904 | struct ether_addr macaddr; | ||
1905 | |||
1906 | uint16 flags; | ||
1907 | } wl_pfn_bssid_t; | ||
1908 | #define WL_PFN_SUPPRESSFOUND_MASK 0x08 | ||
1909 | #define WL_PFN_SUPPRESSLOST_MASK 0x10 | ||
1910 | |||
1911 | typedef struct wl_pfn_cfg { | ||
1912 | uint32 reporttype; | ||
1913 | int32 channel_num; | ||
1914 | uint16 channel_list[WL_NUMCHANNELS]; | ||
1915 | } wl_pfn_cfg_t; | ||
1916 | #define WL_PFN_REPORT_ALLNET 0 | ||
1917 | #define WL_PFN_REPORT_SSIDNET 1 | ||
1918 | #define WL_PFN_REPORT_BSSIDNET 2 | ||
1919 | |||
1920 | typedef struct wl_pfn { | ||
1921 | wlc_ssid_t ssid; | ||
1922 | int32 flags; | ||
1923 | int32 infra; | ||
1924 | int32 auth; | ||
1925 | int32 wpa_auth; | ||
1926 | int32 wsec; | ||
1927 | } wl_pfn_t; | ||
1928 | #define WL_PFN_HIDDEN_BIT 2 | ||
1929 | #define PNO_SCAN_MAX_FW 508*1000 | ||
1930 | #define PNO_SCAN_MAX_FW_SEC PNO_SCAN_MAX_FW/1000 | ||
1931 | #define PNO_SCAN_MIN_FW_SEC 10 | ||
1932 | #define WL_PFN_HIDDEN_MASK 0x4 | ||
1933 | |||
1934 | |||
1935 | #define TOE_TX_CSUM_OL 0x00000001 | ||
1936 | #define TOE_RX_CSUM_OL 0x00000002 | ||
1937 | |||
1938 | |||
1939 | #define TOE_ERRTEST_TX_CSUM 0x00000001 | ||
1940 | #define TOE_ERRTEST_RX_CSUM 0x00000002 | ||
1941 | #define TOE_ERRTEST_RX_CSUM2 0x00000004 | ||
1942 | |||
1943 | struct toe_ol_stats_t { | ||
1944 | |||
1945 | uint32 tx_summed; | ||
1946 | |||
1947 | |||
1948 | uint32 tx_iph_fill; | ||
1949 | uint32 tx_tcp_fill; | ||
1950 | uint32 tx_udp_fill; | ||
1951 | uint32 tx_icmp_fill; | ||
1952 | |||
1953 | |||
1954 | uint32 rx_iph_good; | ||
1955 | uint32 rx_iph_bad; | ||
1956 | uint32 rx_tcp_good; | ||
1957 | uint32 rx_tcp_bad; | ||
1958 | uint32 rx_udp_good; | ||
1959 | uint32 rx_udp_bad; | ||
1960 | uint32 rx_icmp_good; | ||
1961 | uint32 rx_icmp_bad; | ||
1962 | |||
1963 | |||
1964 | uint32 tx_tcp_errinj; | ||
1965 | uint32 tx_udp_errinj; | ||
1966 | uint32 tx_icmp_errinj; | ||
1967 | |||
1968 | |||
1969 | uint32 rx_tcp_errinj; | ||
1970 | uint32 rx_udp_errinj; | ||
1971 | uint32 rx_icmp_errinj; | ||
1972 | }; | ||
1973 | |||
1974 | |||
1975 | #define ARP_OL_AGENT 0x00000001 | ||
1976 | #define ARP_OL_SNOOP 0x00000002 | ||
1977 | #define ARP_OL_HOST_AUTO_REPLY 0x00000004 | ||
1978 | #define ARP_OL_PEER_AUTO_REPLY 0x00000008 | ||
1979 | |||
1980 | |||
1981 | #define ARP_ERRTEST_REPLY_PEER 0x1 | ||
1982 | #define ARP_ERRTEST_REPLY_HOST 0x2 | ||
1983 | |||
1984 | #define ARP_MULTIHOMING_MAX 8 | ||
1985 | |||
1986 | |||
1987 | struct arp_ol_stats_t { | ||
1988 | uint32 host_ip_entries; | ||
1989 | uint32 host_ip_overflow; | ||
1990 | |||
1991 | uint32 arp_table_entries; | ||
1992 | uint32 arp_table_overflow; | ||
1993 | |||
1994 | uint32 host_request; | ||
1995 | uint32 host_reply; | ||
1996 | uint32 host_service; | ||
1997 | |||
1998 | uint32 peer_request; | ||
1999 | uint32 peer_request_drop; | ||
2000 | uint32 peer_reply; | ||
2001 | uint32 peer_reply_drop; | ||
2002 | uint32 peer_service; | ||
2003 | }; | ||
2004 | |||
2005 | |||
2006 | |||
2007 | |||
2008 | typedef struct wl_keep_alive_pkt { | ||
2009 | uint32 period_msec; | ||
2010 | uint16 len_bytes; | ||
2011 | uint8 data[1]; | ||
2012 | } wl_keep_alive_pkt_t; | ||
2013 | |||
2014 | #define WL_KEEP_ALIVE_FIXED_LEN OFFSETOF(wl_keep_alive_pkt_t, data) | ||
2015 | |||
2016 | |||
2017 | |||
2018 | |||
2019 | typedef enum wl_pkt_filter_type { | ||
2020 | WL_PKT_FILTER_TYPE_PATTERN_MATCH | ||
2021 | } wl_pkt_filter_type_t; | ||
2022 | |||
2023 | #define WL_PKT_FILTER_TYPE wl_pkt_filter_type_t | ||
2024 | |||
2025 | |||
2026 | typedef struct wl_pkt_filter_pattern { | ||
2027 | uint32 offset; | ||
2028 | uint32 size_bytes; | ||
2029 | uint8 mask_and_pattern[1]; | ||
2030 | } wl_pkt_filter_pattern_t; | ||
2031 | |||
2032 | |||
2033 | typedef struct wl_pkt_filter { | ||
2034 | uint32 id; | ||
2035 | uint32 type; | ||
2036 | uint32 negate_match; | ||
2037 | union { | ||
2038 | wl_pkt_filter_pattern_t pattern; | ||
2039 | } u; | ||
2040 | } wl_pkt_filter_t; | ||
2041 | |||
2042 | #define WL_PKT_FILTER_FIXED_LEN OFFSETOF(wl_pkt_filter_t, u) | ||
2043 | #define WL_PKT_FILTER_PATTERN_FIXED_LEN OFFSETOF(wl_pkt_filter_pattern_t, mask_and_pattern) | ||
2044 | |||
2045 | |||
2046 | typedef struct wl_pkt_filter_enable { | ||
2047 | uint32 id; | ||
2048 | uint32 enable; | ||
2049 | } wl_pkt_filter_enable_t; | ||
2050 | |||
2051 | |||
2052 | typedef struct wl_pkt_filter_list { | ||
2053 | uint32 num; | ||
2054 | wl_pkt_filter_t filter[1]; | ||
2055 | } wl_pkt_filter_list_t; | ||
2056 | |||
2057 | #define WL_PKT_FILTER_LIST_FIXED_LEN OFFSETOF(wl_pkt_filter_list_t, filter) | ||
2058 | |||
2059 | |||
2060 | typedef struct wl_pkt_filter_stats { | ||
2061 | uint32 num_pkts_matched; | ||
2062 | uint32 num_pkts_forwarded; | ||
2063 | uint32 num_pkts_discarded; | ||
2064 | } wl_pkt_filter_stats_t; | ||
2065 | |||
2066 | |||
2067 | typedef struct wl_seq_cmd_ioctl { | ||
2068 | uint32 cmd; | ||
2069 | uint32 len; | ||
2070 | } wl_seq_cmd_ioctl_t; | ||
2071 | |||
2072 | #define WL_SEQ_CMD_ALIGN_BYTES 4 | ||
2073 | |||
2074 | |||
2075 | #define WL_SEQ_CMDS_GET_IOCTL_FILTER(cmd) \ | ||
2076 | (((cmd) == WLC_GET_MAGIC) || \ | ||
2077 | ((cmd) == WLC_GET_VERSION) || \ | ||
2078 | ((cmd) == WLC_GET_AP) || \ | ||
2079 | ((cmd) == WLC_GET_INSTANCE)) | ||
2080 | |||
2081 | |||
2082 | |||
2083 | #define WL_PKTENG_PER_TX_START 0x01 | ||
2084 | #define WL_PKTENG_PER_TX_STOP 0x02 | ||
2085 | #define WL_PKTENG_PER_RX_START 0x04 | ||
2086 | #define WL_PKTENG_PER_RX_WITH_ACK_START 0x05 | ||
2087 | #define WL_PKTENG_PER_TX_WITH_ACK_START 0x06 | ||
2088 | #define WL_PKTENG_PER_RX_STOP 0x08 | ||
2089 | #define WL_PKTENG_PER_MASK 0xff | ||
2090 | |||
2091 | #define WL_PKTENG_SYNCHRONOUS 0x100 | ||
2092 | |||
2093 | typedef struct wl_pkteng { | ||
2094 | uint32 flags; | ||
2095 | uint32 delay; | ||
2096 | uint32 nframes; | ||
2097 | uint32 length; | ||
2098 | uint8 seqno; | ||
2099 | struct ether_addr dest; | ||
2100 | struct ether_addr src; | ||
2101 | } wl_pkteng_t; | ||
2102 | |||
2103 | #define NUM_80211b_RATES 4 | ||
2104 | #define NUM_80211ag_RATES 8 | ||
2105 | #define NUM_80211n_RATES 32 | ||
2106 | #define NUM_80211_RATES (NUM_80211b_RATES+NUM_80211ag_RATES+NUM_80211n_RATES) | ||
2107 | typedef struct wl_pkteng_stats { | ||
2108 | uint32 lostfrmcnt; | ||
2109 | int32 rssi; | ||
2110 | int32 snr; | ||
2111 | uint16 rxpktcnt[NUM_80211_RATES+1]; | ||
2112 | } wl_pkteng_stats_t; | ||
2113 | |||
2114 | |||
2115 | #define WL_WOWL_MAGIC (1 << 0) | ||
2116 | #define WL_WOWL_NET (1 << 1) | ||
2117 | #define WL_WOWL_DIS (1 << 2) | ||
2118 | #define WL_WOWL_RETR (1 << 3) | ||
2119 | #define WL_WOWL_BCN (1 << 4) | ||
2120 | #define WL_WOWL_TST (1 << 5) | ||
2121 | #define WL_WOWL_M1 (1 << 6) | ||
2122 | #define WL_WOWL_EAPID (1 << 7) | ||
2123 | #define WL_WOWL_KEYROT (1 << 14) | ||
2124 | #define WL_WOWL_BCAST (1 << 15) | ||
2125 | |||
2126 | #define MAGIC_PKT_MINLEN 102 | ||
2127 | |||
2128 | typedef struct { | ||
2129 | uint masksize; | ||
2130 | uint offset; | ||
2131 | uint patternoffset; | ||
2132 | uint patternsize; | ||
2133 | ulong id; | ||
2134 | |||
2135 | |||
2136 | } wl_wowl_pattern_t; | ||
2137 | |||
2138 | typedef struct { | ||
2139 | uint count; | ||
2140 | wl_wowl_pattern_t pattern[1]; | ||
2141 | } wl_wowl_pattern_list_t; | ||
2142 | |||
2143 | typedef struct { | ||
2144 | uint8 pci_wakeind; | ||
2145 | uint16 ucode_wakeind; | ||
2146 | } wl_wowl_wakeind_t; | ||
2147 | |||
2148 | |||
2149 | typedef struct wl_txrate_class { | ||
2150 | uint8 init_rate; | ||
2151 | uint8 min_rate; | ||
2152 | uint8 max_rate; | ||
2153 | } wl_txrate_class_t; | ||
2154 | |||
2155 | |||
2156 | |||
2157 | |||
2158 | #define WLC_OBSS_SCAN_PASSIVE_DWELL_DEFAULT 20 | ||
2159 | #define WLC_OBSS_SCAN_PASSIVE_DWELL_MIN 5 | ||
2160 | #define WLC_OBSS_SCAN_PASSIVE_DWELL_MAX 1000 | ||
2161 | #define WLC_OBSS_SCAN_ACTIVE_DWELL_DEFAULT 10 | ||
2162 | #define WLC_OBSS_SCAN_ACTIVE_DWELL_MIN 10 | ||
2163 | #define WLC_OBSS_SCAN_ACTIVE_DWELL_MAX 1000 | ||
2164 | #define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_DEFAULT 300 | ||
2165 | #define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_MIN 10 | ||
2166 | #define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_MAX 900 | ||
2167 | #define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_DEFAULT 5 | ||
2168 | #define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_MIN 5 | ||
2169 | #define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_MAX 100 | ||
2170 | #define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_DEFAULT 200 | ||
2171 | #define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_MIN 200 | ||
2172 | #define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_MAX 10000 | ||
2173 | #define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_DEFAULT 20 | ||
2174 | #define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_MIN 20 | ||
2175 | #define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_MAX 10000 | ||
2176 | #define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_DEFAULT 25 | ||
2177 | #define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_MIN 0 | ||
2178 | #define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_MAX 100 | ||
2179 | |||
2180 | |||
2181 | typedef struct wl_obss_scan_arg { | ||
2182 | int16 passive_dwell; | ||
2183 | int16 active_dwell; | ||
2184 | int16 bss_widthscan_interval; | ||
2185 | int16 passive_total; | ||
2186 | int16 active_total; | ||
2187 | int16 chanwidth_transition_delay; | ||
2188 | int16 activity_threshold; | ||
2189 | } wl_obss_scan_arg_t; | ||
2190 | |||
2191 | #define WL_OBSS_SCAN_PARAM_LEN sizeof(wl_obss_scan_arg_t) | ||
2192 | #define WL_MIN_NUM_OBSS_SCAN_ARG 7 | ||
2193 | |||
2194 | #define WL_COEX_INFO_MASK 0x07 | ||
2195 | #define WL_COEX_INFO_REQ 0x01 | ||
2196 | #define WL_COEX_40MHZ_INTOLERANT 0x02 | ||
2197 | #define WL_COEX_WIDTH20 0x04 | ||
2198 | |||
2199 | #define WLC_RSSI_INVALID 0 | ||
2200 | |||
2201 | #define MAX_RSSI_LEVELS 8 | ||
2202 | |||
2203 | |||
2204 | typedef struct wl_rssi_event { | ||
2205 | uint32 rate_limit_msec; | ||
2206 | uint8 num_rssi_levels; | ||
2207 | int8 rssi_levels[MAX_RSSI_LEVELS]; | ||
2208 | } wl_rssi_event_t; | ||
2209 | |||
2210 | typedef struct wl_action_obss_coex_req { | ||
2211 | uint8 info; | ||
2212 | uint8 num; | ||
2213 | uint8 ch_list[1]; | ||
2214 | } wl_action_obss_coex_req_t; | ||
2215 | |||
2216 | |||
2217 | #define EXTLOG_CUR_VER 0x0100 | ||
2218 | |||
2219 | #define MAX_ARGSTR_LEN 18 | ||
2220 | |||
2221 | |||
2222 | #define LOG_MODULE_COMMON 0x0001 | ||
2223 | #define LOG_MODULE_ASSOC 0x0002 | ||
2224 | #define LOG_MODULE_EVENT 0x0004 | ||
2225 | #define LOG_MODULE_MAX 3 | ||
2226 | |||
2227 | |||
2228 | #define WL_LOG_LEVEL_DISABLE 0 | ||
2229 | #define WL_LOG_LEVEL_ERR 1 | ||
2230 | #define WL_LOG_LEVEL_WARN 2 | ||
2231 | #define WL_LOG_LEVEL_INFO 3 | ||
2232 | #define WL_LOG_LEVEL_MAX WL_LOG_LEVEL_INFO | ||
2233 | |||
2234 | |||
2235 | #define LOG_FLAG_EVENT 1 | ||
2236 | |||
2237 | |||
2238 | #define LOG_ARGTYPE_NULL 0 | ||
2239 | #define LOG_ARGTYPE_STR 1 | ||
2240 | #define LOG_ARGTYPE_INT 2 | ||
2241 | #define LOG_ARGTYPE_INT_STR 3 | ||
2242 | #define LOG_ARGTYPE_STR_INT 4 | ||
2243 | |||
2244 | typedef struct wlc_extlog_cfg { | ||
2245 | int max_number; | ||
2246 | uint16 module; | ||
2247 | uint8 level; | ||
2248 | uint8 flag; | ||
2249 | uint16 version; | ||
2250 | } wlc_extlog_cfg_t; | ||
2251 | |||
2252 | typedef struct log_record { | ||
2253 | uint32 time; | ||
2254 | uint16 module; | ||
2255 | uint16 id; | ||
2256 | uint8 level; | ||
2257 | uint8 sub_unit; | ||
2258 | uint8 seq_num; | ||
2259 | int32 arg; | ||
2260 | char str[MAX_ARGSTR_LEN]; | ||
2261 | } log_record_t; | ||
2262 | |||
2263 | typedef struct wlc_extlog_req { | ||
2264 | uint32 from_last; | ||
2265 | uint32 num; | ||
2266 | } wlc_extlog_req_t; | ||
2267 | |||
2268 | typedef struct wlc_extlog_results { | ||
2269 | uint16 version; | ||
2270 | uint16 record_len; | ||
2271 | uint32 num; | ||
2272 | log_record_t logs[1]; | ||
2273 | } wlc_extlog_results_t; | ||
2274 | |||
2275 | typedef struct log_idstr { | ||
2276 | uint16 id; | ||
2277 | uint16 flag; | ||
2278 | uint8 arg_type; | ||
2279 | const char *fmt_str; | ||
2280 | } log_idstr_t; | ||
2281 | |||
2282 | #define FMTSTRF_USER 1 | ||
2283 | |||
2284 | |||
2285 | typedef enum { | ||
2286 | FMTSTR_DRIVER_UP_ID = 0, | ||
2287 | FMTSTR_DRIVER_DOWN_ID = 1, | ||
2288 | FMTSTR_SUSPEND_MAC_FAIL_ID = 2, | ||
2289 | FMTSTR_NO_PROGRESS_ID = 3, | ||
2290 | FMTSTR_RFDISABLE_ID = 4, | ||
2291 | FMTSTR_REG_PRINT_ID = 5, | ||
2292 | FMTSTR_EXPTIME_ID = 6, | ||
2293 | FMTSTR_JOIN_START_ID = 7, | ||
2294 | FMTSTR_JOIN_COMPLETE_ID = 8, | ||
2295 | FMTSTR_NO_NETWORKS_ID = 9, | ||
2296 | FMTSTR_SECURITY_MISMATCH_ID = 10, | ||
2297 | FMTSTR_RATE_MISMATCH_ID = 11, | ||
2298 | FMTSTR_AP_PRUNED_ID = 12, | ||
2299 | FMTSTR_KEY_INSERTED_ID = 13, | ||
2300 | FMTSTR_DEAUTH_ID = 14, | ||
2301 | FMTSTR_DISASSOC_ID = 15, | ||
2302 | FMTSTR_LINK_UP_ID = 16, | ||
2303 | FMTSTR_LINK_DOWN_ID = 17, | ||
2304 | FMTSTR_RADIO_HW_OFF_ID = 18, | ||
2305 | FMTSTR_RADIO_HW_ON_ID = 19, | ||
2306 | FMTSTR_EVENT_DESC_ID = 20, | ||
2307 | FMTSTR_PNP_SET_POWER_ID = 21, | ||
2308 | FMTSTR_RADIO_SW_OFF_ID = 22, | ||
2309 | FMTSTR_RADIO_SW_ON_ID = 23, | ||
2310 | FMTSTR_PWD_MISMATCH_ID = 24, | ||
2311 | FMTSTR_FATAL_ERROR_ID = 25, | ||
2312 | FMTSTR_AUTH_FAIL_ID = 26, | ||
2313 | FMTSTR_ASSOC_FAIL_ID = 27, | ||
2314 | FMTSTR_IBSS_FAIL_ID = 28, | ||
2315 | FMTSTR_EXTAP_FAIL_ID = 29, | ||
2316 | FMTSTR_MAX_ID | ||
2317 | } log_fmtstr_id_t; | ||
2318 | |||
2319 | #ifdef DONGLEOVERLAYS | ||
2320 | typedef struct { | ||
2321 | uint32 flags_idx; | ||
2322 | uint32 offset; | ||
2323 | uint32 len; | ||
2324 | |||
2325 | } wl_ioctl_overlay_t; | ||
2326 | |||
2327 | #define OVERLAY_IDX_MASK 0x000000ff | ||
2328 | #define OVERLAY_IDX_SHIFT 0 | ||
2329 | #define OVERLAY_FLAGS_MASK 0xffffff00 | ||
2330 | #define OVERLAY_FLAGS_SHIFT 8 | ||
2331 | |||
2332 | #define OVERLAY_FLAG_POSTLOAD 0x100 | ||
2333 | |||
2334 | #define OVERLAY_FLAG_DEFER_DL 0x200 | ||
2335 | |||
2336 | #define OVERLAY_FLAG_PRESLEEP 0x400 | ||
2337 | |||
2338 | #define OVERLAY_DOWNLOAD_CHUNKSIZE 1024 | ||
2339 | #endif | ||
2340 | |||
2341 | |||
2342 | #include <packed_section_end.h> | ||
2343 | |||
2344 | |||
2345 | #include <packed_section_start.h> | ||
2346 | |||
2347 | #define VNDR_IE_CMD_LEN 4 | ||
2348 | |||
2349 | |||
2350 | #define VNDR_IE_BEACON_FLAG 0x1 | ||
2351 | #define VNDR_IE_PRBRSP_FLAG 0x2 | ||
2352 | #define VNDR_IE_ASSOCRSP_FLAG 0x4 | ||
2353 | #define VNDR_IE_AUTHRSP_FLAG 0x8 | ||
2354 | #define VNDR_IE_PRBREQ_FLAG 0x10 | ||
2355 | #define VNDR_IE_ASSOCREQ_FLAG 0x20 | ||
2356 | #define VNDR_IE_CUSTOM_FLAG 0x100 | ||
2357 | |||
2358 | #define VNDR_IE_INFO_HDR_LEN (sizeof(uint32)) | ||
2359 | |||
2360 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
2361 | uint32 pktflag; | ||
2362 | vndr_ie_t vndr_ie_data; | ||
2363 | } BWL_POST_PACKED_STRUCT vndr_ie_info_t; | ||
2364 | |||
2365 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
2366 | int iecount; | ||
2367 | vndr_ie_info_t vndr_ie_list[1]; | ||
2368 | } BWL_POST_PACKED_STRUCT vndr_ie_buf_t; | ||
2369 | |||
2370 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
2371 | char cmd[VNDR_IE_CMD_LEN]; | ||
2372 | vndr_ie_buf_t vndr_ie_buffer; | ||
2373 | } BWL_POST_PACKED_STRUCT vndr_ie_setbuf_t; | ||
2374 | |||
2375 | |||
2376 | |||
2377 | typedef BWL_PRE_PACKED_STRUCT struct sta_prbreq_wps_ie_hdr { | ||
2378 | struct ether_addr staAddr; | ||
2379 | uint16 ieLen; | ||
2380 | } BWL_POST_PACKED_STRUCT sta_prbreq_wps_ie_hdr_t; | ||
2381 | |||
2382 | typedef BWL_PRE_PACKED_STRUCT struct sta_prbreq_wps_ie_data { | ||
2383 | sta_prbreq_wps_ie_hdr_t hdr; | ||
2384 | uint8 ieData[1]; | ||
2385 | } BWL_POST_PACKED_STRUCT sta_prbreq_wps_ie_data_t; | ||
2386 | |||
2387 | typedef BWL_PRE_PACKED_STRUCT struct sta_prbreq_wps_ie_list { | ||
2388 | uint32 totLen; | ||
2389 | uint8 ieDataList[1]; | ||
2390 | } BWL_POST_PACKED_STRUCT sta_prbreq_wps_ie_list_t; | ||
2391 | |||
2392 | |||
2393 | #ifdef WLMEDIA_TXFAILEVENT | ||
2394 | typedef BWL_PRE_PACKED_STRUCT struct { | ||
2395 | char dest[ETHER_ADDR_LEN]; | ||
2396 | uint8 prio; | ||
2397 | uint8 flags; | ||
2398 | uint32 tsf_l; | ||
2399 | uint32 tsf_h; | ||
2400 | uint16 rates; | ||
2401 | uint16 txstatus; | ||
2402 | } BWL_POST_PACKED_STRUCT txfailinfo_t; | ||
2403 | #endif | ||
2404 | |||
2405 | #include <packed_section_end.h> | ||
2406 | |||
2407 | |||
2408 | #define ASSERTLOG_CUR_VER 0x0100 | ||
2409 | #define MAX_ASSRTSTR_LEN 64 | ||
2410 | |||
2411 | typedef struct assert_record { | ||
2412 | uint32 time; | ||
2413 | uint8 seq_num; | ||
2414 | char str[MAX_ASSRTSTR_LEN]; | ||
2415 | } assert_record_t; | ||
2416 | |||
2417 | typedef struct assertlog_results { | ||
2418 | uint16 version; | ||
2419 | uint16 record_len; | ||
2420 | uint32 num; | ||
2421 | assert_record_t logs[1]; | ||
2422 | } assertlog_results_t; | ||
2423 | |||
2424 | #define LOGRRC_FIX_LEN 8 | ||
2425 | #define IOBUF_ALLOWED_NUM_OF_LOGREC(type, len) ((len - LOGRRC_FIX_LEN)/sizeof(type)) | ||
2426 | |||
2427 | |||
2428 | |||
2429 | |||
2430 | |||
2431 | #define CHANIM_DISABLE 0 | ||
2432 | #define CHANIM_DETECT 1 | ||
2433 | #define CHANIM_ACT 2 | ||
2434 | #define CHANIM_MODE_MAX 2 | ||
2435 | |||
2436 | |||
2437 | #define APCS_IOCTL 1 | ||
2438 | #define APCS_CHANIM 2 | ||
2439 | #define APCS_CSTIMER 3 | ||
2440 | #define APCS_BTA 4 | ||
2441 | |||
2442 | |||
2443 | #define CHANIM_ACS_RECORD 10 | ||
2444 | |||
2445 | |||
2446 | typedef struct { | ||
2447 | bool valid; | ||
2448 | uint8 trigger; | ||
2449 | chanspec_t selected_chspc; | ||
2450 | uint32 glitch_cnt; | ||
2451 | uint8 ccastats; | ||
2452 | uint timestamp; | ||
2453 | } chanim_acs_record_t; | ||
2454 | |||
2455 | typedef struct { | ||
2456 | chanim_acs_record_t acs_record[CHANIM_ACS_RECORD]; | ||
2457 | uint8 count; | ||
2458 | uint timestamp; | ||
2459 | } wl_acs_record_t; | ||
2460 | |||
2461 | |||
2462 | |||
2463 | #define SMFS_VERSION 1 | ||
2464 | |||
2465 | typedef struct wl_smfs_elem { | ||
2466 | uint32 count; | ||
2467 | uint16 code; | ||
2468 | } wl_smfs_elem_t; | ||
2469 | |||
2470 | typedef struct wl_smf_stats { | ||
2471 | uint32 version; | ||
2472 | uint16 length; | ||
2473 | uint8 type; | ||
2474 | uint8 codetype; | ||
2475 | uint32 ignored_cnt; | ||
2476 | uint32 malformed_cnt; | ||
2477 | uint32 count_total; | ||
2478 | wl_smfs_elem_t elem[1]; | ||
2479 | } wl_smf_stats_t; | ||
2480 | |||
2481 | #define WL_SMFSTATS_FIXED_LEN OFFSETOF(wl_smf_stats_t, elem); | ||
2482 | |||
2483 | enum { | ||
2484 | SMFS_CODETYPE_SC, | ||
2485 | SMFS_CODETYPE_RC | ||
2486 | }; | ||
2487 | |||
2488 | |||
2489 | #define SMFS_CODE_MALFORMED 0xFFFE | ||
2490 | #define SMFS_CODE_IGNORED 0xFFFD | ||
2491 | |||
2492 | typedef enum smfs_type { | ||
2493 | SMFS_TYPE_AUTH, | ||
2494 | SMFS_TYPE_ASSOC, | ||
2495 | SMFS_TYPE_REASSOC, | ||
2496 | SMFS_TYPE_DISASSOC_TX, | ||
2497 | SMFS_TYPE_DISASSOC_RX, | ||
2498 | SMFS_TYPE_DEAUTH_TX, | ||
2499 | SMFS_TYPE_DEAUTH_RX, | ||
2500 | SMFS_TYPE_MAX | ||
2501 | } smfs_type_t; | ||
2502 | |||
2503 | #ifdef PHYMON | ||
2504 | |||
2505 | #define PHYMON_VERSION 1 | ||
2506 | |||
2507 | typedef struct wl_phycal_core_state { | ||
2508 | |||
2509 | int16 tx_iqlocal_a; | ||
2510 | int16 tx_iqlocal_b; | ||
2511 | int8 tx_iqlocal_ci; | ||
2512 | int8 tx_iqlocal_cq; | ||
2513 | int8 tx_iqlocal_di; | ||
2514 | int8 tx_iqlocal_dq; | ||
2515 | int8 tx_iqlocal_ei; | ||
2516 | int8 tx_iqlocal_eq; | ||
2517 | int8 tx_iqlocal_fi; | ||
2518 | int8 tx_iqlocal_fq; | ||
2519 | |||
2520 | |||
2521 | int16 rx_iqcal_a; | ||
2522 | int16 rx_iqcal_b; | ||
2523 | |||
2524 | uint8 tx_iqlocal_pwridx; | ||
2525 | uint32 papd_epsilon_table[64]; | ||
2526 | int16 papd_epsilon_offset; | ||
2527 | uint8 curr_tx_pwrindex; | ||
2528 | int8 idle_tssi; | ||
2529 | int8 est_tx_pwr; | ||
2530 | int8 est_rx_pwr; | ||
2531 | uint16 rx_gaininfo; | ||
2532 | uint16 init_gaincode; | ||
2533 | int8 estirr_tx; | ||
2534 | int8 estirr_rx; | ||
2535 | |||
2536 | } wl_phycal_core_state_t; | ||
2537 | |||
2538 | typedef struct wl_phycal_state { | ||
2539 | int version; | ||
2540 | int8 num_phy_cores; | ||
2541 | int8 curr_temperature; | ||
2542 | chanspec_t chspec; | ||
2543 | bool aci_state; | ||
2544 | uint16 crsminpower; | ||
2545 | uint16 crsminpowerl; | ||
2546 | uint16 crsminpoweru; | ||
2547 | wl_phycal_core_state_t phycal_core[1]; | ||
2548 | } wl_phycal_state_t; | ||
2549 | |||
2550 | #define WL_PHYCAL_STAT_FIXED_LEN OFFSETOF(wl_phycal_state_t, phycal_core) | ||
2551 | #endif | ||
2552 | |||
2553 | #ifdef WLP2P | ||
2554 | |||
2555 | typedef struct wl_p2p_disc_st { | ||
2556 | uint8 state; | ||
2557 | chanspec_t chspec; | ||
2558 | uint16 dwell; | ||
2559 | } wl_p2p_disc_st_t; | ||
2560 | |||
2561 | |||
2562 | #define WL_P2P_DISC_ST_SCAN 0 | ||
2563 | #define WL_P2P_DISC_ST_LISTEN 1 | ||
2564 | #define WL_P2P_DISC_ST_SEARCH 2 | ||
2565 | |||
2566 | |||
2567 | typedef struct wl_p2p_scan { | ||
2568 | uint8 type; | ||
2569 | uint8 reserved[3]; | ||
2570 | |||
2571 | } wl_p2p_scan_t; | ||
2572 | |||
2573 | |||
2574 | typedef struct wl_p2p_if { | ||
2575 | struct ether_addr addr; | ||
2576 | uint8 type; | ||
2577 | chanspec_t chspec; | ||
2578 | } wl_p2p_if_t; | ||
2579 | |||
2580 | |||
2581 | #define WL_P2P_IF_CLIENT 0 | ||
2582 | #define WL_P2P_IF_GO 1 | ||
2583 | #define WL_P2P_IF_DYNBCN_GO 2 | ||
2584 | #define WL_P2P_IF_DEV 3 | ||
2585 | |||
2586 | |||
2587 | typedef struct wl_p2p_ifq { | ||
2588 | uint bsscfgidx; | ||
2589 | char ifname[BCM_MSG_IFNAME_MAX]; | ||
2590 | } wl_p2p_ifq_t; | ||
2591 | |||
2592 | |||
2593 | typedef struct wl_p2p_ops { | ||
2594 | uint8 ops; | ||
2595 | uint8 ctw; | ||
2596 | } wl_p2p_ops_t; | ||
2597 | |||
2598 | |||
2599 | typedef struct wl_p2p_sched_desc { | ||
2600 | uint32 start; | ||
2601 | uint32 interval; | ||
2602 | uint32 duration; | ||
2603 | uint32 count; | ||
2604 | } wl_p2p_sched_desc_t; | ||
2605 | |||
2606 | |||
2607 | #define WL_P2P_SCHED_RSVD 0 | ||
2608 | #define WL_P2P_SCHED_REPEAT 255 | ||
2609 | |||
2610 | typedef struct wl_p2p_sched { | ||
2611 | uint8 type; | ||
2612 | uint8 action; | ||
2613 | uint8 option; | ||
2614 | wl_p2p_sched_desc_t desc[1]; | ||
2615 | } wl_p2p_sched_t; | ||
2616 | #define WL_P2P_SCHED_FIXED_LEN 3 | ||
2617 | |||
2618 | |||
2619 | #define WL_P2P_SCHED_TYPE_ABS 0 | ||
2620 | #define WL_P2P_SCHED_TYPE_REQ_ABS 1 | ||
2621 | |||
2622 | |||
2623 | #define WL_P2P_SCHED_ACTION_NONE 0 | ||
2624 | #define WL_P2P_SCHED_ACTION_DOZE 1 | ||
2625 | |||
2626 | #define WL_P2P_SCHED_ACTION_GOOFF 2 | ||
2627 | |||
2628 | #define WL_P2P_SCHED_ACTION_RESET 255 | ||
2629 | |||
2630 | |||
2631 | #define WL_P2P_SCHED_OPTION_NORMAL 0 | ||
2632 | #define WL_P2P_SCHED_OPTION_BCNPCT 1 | ||
2633 | |||
2634 | #define WL_P2P_SCHED_OPTION_TSFOFS 2 | ||
2635 | |||
2636 | |||
2637 | #define WL_P2P_FEAT_GO_CSA (1 << 0) | ||
2638 | #define WL_P2P_FEAT_GO_NOLEGACY (1 << 1) | ||
2639 | #define WL_P2P_FEAT_RESTRICT_DEV_RESP (1 << 2) | ||
2640 | #endif | ||
2641 | |||
2642 | |||
2643 | #define BCM_ACTION_RFAWARE 0x77 | ||
2644 | #define BCM_ACTION_RFAWARE_DCS 0x01 | ||
2645 | |||
2646 | |||
2647 | |||
2648 | #define WL_11N_2x2 1 | ||
2649 | #define WL_11N_3x3 3 | ||
2650 | #define WL_11N_4x4 4 | ||
2651 | |||
2652 | |||
2653 | #define WLFEATURE_DISABLE_11N 0x00000001 | ||
2654 | #define WLFEATURE_DISABLE_11N_STBC_TX 0x00000002 | ||
2655 | #define WLFEATURE_DISABLE_11N_STBC_RX 0x00000004 | ||
2656 | #define WLFEATURE_DISABLE_11N_SGI_TX 0x00000008 | ||
2657 | #define WLFEATURE_DISABLE_11N_SGI_RX 0x00000010 | ||
2658 | #define WLFEATURE_DISABLE_11N_AMPDU_TX 0x00000020 | ||
2659 | #define WLFEATURE_DISABLE_11N_AMPDU_RX 0x00000040 | ||
2660 | #define WLFEATURE_DISABLE_11N_GF 0x00000080 | ||
2661 | |||
2662 | |||
2663 | #define LQ_IDX_LAST 3 | ||
2664 | #define MCS_INDEX_SIZE 33 | ||
2665 | |||
2666 | #define LQ_IDX_MIN 0 | ||
2667 | #define LQ_IDX_MAX 1 | ||
2668 | #define LQ_IDX_AVG 2 | ||
2669 | #define LQ_IDX_SUM 2 | ||
2670 | #define LQ_IDX_LAST 3 | ||
2671 | #define LQ_STOP_MONITOR 0 | ||
2672 | #define LQ_START_MONITOR 1 | ||
2673 | |||
2674 | #define LINKQUAL_V1 0x01 | ||
2675 | |||
2676 | struct wl_lq { | ||
2677 | int32 enable; | ||
2678 | int32 rssi[LQ_IDX_LAST]; | ||
2679 | int32 rssicnt; | ||
2680 | int32 snr[LQ_IDX_LAST]; | ||
2681 | uint32 nsamples; | ||
2682 | uint8 isvalid; | ||
2683 | uint8 version; | ||
2684 | }; | ||
2685 | |||
2686 | typedef struct wl_lq wl_lq_t; | ||
2687 | typedef struct wl_lq wl_lq_stats_t; | ||
2688 | |||
2689 | typedef struct { | ||
2690 | struct ether_addr ea; | ||
2691 | uint8 ac_cat; | ||
2692 | uint8 num_pkts; | ||
2693 | } wl_mac_ratehisto_cmd_t; | ||
2694 | |||
2695 | |||
2696 | typedef struct { | ||
2697 | uint32 rate[WLC_MAXRATE + 1]; | ||
2698 | uint32 mcs_index[MCS_INDEX_SIZE]; | ||
2699 | uint32 tsf_timer[2][2]; | ||
2700 | } wl_mac_ratehisto_res_t; | ||
2701 | |||
2702 | #ifdef PROP_TXSTATUS | ||
2703 | |||
2704 | |||
2705 | #define WLFC_FLAGS_RSSI_SIGNALS 1 | ||
2706 | |||
2707 | |||
2708 | #define WLFC_FLAGS_XONXOFF_SIGNALS 2 | ||
2709 | |||
2710 | |||
2711 | #define WLFC_FLAGS_CREDIT_STATUS_SIGNALS 4 | ||
2712 | |||
2713 | #define WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE 8 | ||
2714 | #define WLFC_FLAGS_PSQ_GENERATIONFSM_ENABLE 16 | ||
2715 | #define WLFC_FLAGS_PSQ_ZERO_BUFFER_ENABLE 32 | ||
2716 | #endif | ||
2717 | |||
2718 | #define BTA_STATE_LOG_SZ 64 | ||
2719 | |||
2720 | |||
2721 | enum { | ||
2722 | HCIReset = 1, | ||
2723 | HCIReadLocalAMPInfo, | ||
2724 | HCIReadLocalAMPASSOC, | ||
2725 | HCIWriteRemoteAMPASSOC, | ||
2726 | HCICreatePhysicalLink, | ||
2727 | HCIAcceptPhysicalLinkRequest, | ||
2728 | HCIDisconnectPhysicalLink, | ||
2729 | HCICreateLogicalLink, | ||
2730 | HCIAcceptLogicalLink, | ||
2731 | HCIDisconnectLogicalLink, | ||
2732 | HCILogicalLinkCancel, | ||
2733 | HCIAmpStateChange, | ||
2734 | HCIWriteLogicalLinkAcceptTimeout | ||
2735 | }; | ||
2736 | |||
2737 | typedef struct flush_txfifo { | ||
2738 | uint32 txfifobmp; | ||
2739 | uint32 hwtxfifoflush; | ||
2740 | struct ether_addr ea; | ||
2741 | } flush_txfifo_t; | ||
2742 | |||
2743 | #define CHANNEL_5G_LOW_START 36 | ||
2744 | #define CHANNEL_5G_MID_START 52 | ||
2745 | #define CHANNEL_5G_HIGH_START 100 | ||
2746 | #define CHANNEL_5G_UPPER_START 149 | ||
2747 | |||
2748 | enum { | ||
2749 | SPATIAL_MODE_2G_IDX = 0, | ||
2750 | SPATIAL_MODE_5G_LOW_IDX, | ||
2751 | SPATIAL_MODE_5G_MID_IDX, | ||
2752 | SPATIAL_MODE_5G_HIGH_IDX, | ||
2753 | SPATIAL_MODE_5G_UPPER_IDX, | ||
2754 | SPATIAL_MODE_MAX_IDX | ||
2755 | }; | ||
2756 | |||
2757 | #endif | ||