diff options
Diffstat (limited to 'drivers/net/wireless/ath5k/base.c')
-rw-r--r-- | drivers/net/wireless/ath5k/base.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index bcec74e839e..7989ab5c2bb 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c | |||
@@ -707,7 +707,7 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) | |||
707 | * return false w/o doing anything. MAC's that do | 707 | * return false w/o doing anything. MAC's that do |
708 | * support it will return true w/o doing anything. | 708 | * support it will return true w/o doing anything. |
709 | */ | 709 | */ |
710 | ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); | 710 | ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); |
711 | if (ret < 0) | 711 | if (ret < 0) |
712 | goto err; | 712 | goto err; |
713 | if (ret > 0) | 713 | if (ret > 0) |
@@ -1137,7 +1137,7 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) | |||
1137 | ds = bf->desc; | 1137 | ds = bf->desc; |
1138 | ds->ds_link = bf->daddr; /* link to self */ | 1138 | ds->ds_link = bf->daddr; /* link to self */ |
1139 | ds->ds_data = bf->skbaddr; | 1139 | ds->ds_data = bf->skbaddr; |
1140 | ath5k_hw_setup_rx_desc(ah, ds, | 1140 | ah->ah_setup_rx_desc(ah, ds, |
1141 | skb_tailroom(skb), /* buffer size */ | 1141 | skb_tailroom(skb), /* buffer size */ |
1142 | 0); | 1142 | 0); |
1143 | 1143 | ||
@@ -1188,12 +1188,12 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) | |||
1188 | list_add_tail(&bf->list, &txq->q); | 1188 | list_add_tail(&bf->list, &txq->q); |
1189 | sc->tx_stats[txq->qnum].len++; | 1189 | sc->tx_stats[txq->qnum].len++; |
1190 | if (txq->link == NULL) /* is this first packet? */ | 1190 | if (txq->link == NULL) /* is this first packet? */ |
1191 | ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); | 1191 | ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); |
1192 | else /* no, so only link it */ | 1192 | else /* no, so only link it */ |
1193 | *txq->link = bf->daddr; | 1193 | *txq->link = bf->daddr; |
1194 | 1194 | ||
1195 | txq->link = &ds->ds_link; | 1195 | txq->link = &ds->ds_link; |
1196 | ath5k_hw_tx_start(ah, txq->qnum); | 1196 | ath5k_hw_start_tx_dma(ah, txq->qnum); |
1197 | mmiowb(); | 1197 | mmiowb(); |
1198 | spin_unlock_bh(&txq->lock); | 1198 | spin_unlock_bh(&txq->lock); |
1199 | 1199 | ||
@@ -1393,7 +1393,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc) | |||
1393 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", | 1393 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", |
1394 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | 1394 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); |
1395 | 1395 | ||
1396 | ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi); | 1396 | ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); |
1397 | if (ret) { | 1397 | if (ret) { |
1398 | ATH5K_ERR(sc, "%s: unable to update parameters for beacon " | 1398 | ATH5K_ERR(sc, "%s: unable to update parameters for beacon " |
1399 | "hardware queue!\n", __func__); | 1399 | "hardware queue!\n", __func__); |
@@ -1442,14 +1442,14 @@ ath5k_txq_cleanup(struct ath5k_softc *sc) | |||
1442 | /* don't touch the hardware if marked invalid */ | 1442 | /* don't touch the hardware if marked invalid */ |
1443 | ath5k_hw_stop_tx_dma(ah, sc->bhalq); | 1443 | ath5k_hw_stop_tx_dma(ah, sc->bhalq); |
1444 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", | 1444 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", |
1445 | ath5k_hw_get_tx_buf(ah, sc->bhalq)); | 1445 | ath5k_hw_get_txdp(ah, sc->bhalq)); |
1446 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) | 1446 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) |
1447 | if (sc->txqs[i].setup) { | 1447 | if (sc->txqs[i].setup) { |
1448 | ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); | 1448 | ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); |
1449 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " | 1449 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " |
1450 | "link %p\n", | 1450 | "link %p\n", |
1451 | sc->txqs[i].qnum, | 1451 | sc->txqs[i].qnum, |
1452 | ath5k_hw_get_tx_buf(ah, | 1452 | ath5k_hw_get_txdp(ah, |
1453 | sc->txqs[i].qnum), | 1453 | sc->txqs[i].qnum), |
1454 | sc->txqs[i].link); | 1454 | sc->txqs[i].link); |
1455 | } | 1455 | } |
@@ -1509,8 +1509,8 @@ ath5k_rx_start(struct ath5k_softc *sc) | |||
1509 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); | 1509 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); |
1510 | spin_unlock_bh(&sc->rxbuflock); | 1510 | spin_unlock_bh(&sc->rxbuflock); |
1511 | 1511 | ||
1512 | ath5k_hw_put_rx_buf(ah, bf->daddr); | 1512 | ath5k_hw_set_rxdp(ah, bf->daddr); |
1513 | ath5k_hw_start_rx(ah); /* enable recv descriptors */ | 1513 | ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ |
1514 | ath5k_mode_setup(sc); /* set filters, etc. */ | 1514 | ath5k_mode_setup(sc); /* set filters, etc. */ |
1515 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ | 1515 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ |
1516 | 1516 | ||
@@ -1527,7 +1527,7 @@ ath5k_rx_stop(struct ath5k_softc *sc) | |||
1527 | { | 1527 | { |
1528 | struct ath5k_hw *ah = sc->ah; | 1528 | struct ath5k_hw *ah = sc->ah; |
1529 | 1529 | ||
1530 | ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ | 1530 | ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ |
1531 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ | 1531 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ |
1532 | ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ | 1532 | ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ |
1533 | 1533 | ||
@@ -1976,8 +1976,8 @@ ath5k_beacon_send(struct ath5k_softc *sc) | |||
1976 | /* NB: hw still stops DMA, so proceed */ | 1976 | /* NB: hw still stops DMA, so proceed */ |
1977 | } | 1977 | } |
1978 | 1978 | ||
1979 | ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr); | 1979 | ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); |
1980 | ath5k_hw_tx_start(ah, sc->bhalq); | 1980 | ath5k_hw_start_tx_dma(ah, sc->bhalq); |
1981 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", | 1981 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", |
1982 | sc->bhalq, (unsigned long long)bf->daddr, bf->desc); | 1982 | sc->bhalq, (unsigned long long)bf->daddr, bf->desc); |
1983 | 1983 | ||
@@ -2106,7 +2106,7 @@ ath5k_beacon_config(struct ath5k_softc *sc) | |||
2106 | { | 2106 | { |
2107 | struct ath5k_hw *ah = sc->ah; | 2107 | struct ath5k_hw *ah = sc->ah; |
2108 | 2108 | ||
2109 | ath5k_hw_set_intr(ah, 0); | 2109 | ath5k_hw_set_imr(ah, 0); |
2110 | sc->bmisscount = 0; | 2110 | sc->bmisscount = 0; |
2111 | sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); | 2111 | sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); |
2112 | 2112 | ||
@@ -2132,7 +2132,7 @@ ath5k_beacon_config(struct ath5k_softc *sc) | |||
2132 | } | 2132 | } |
2133 | /* TODO else AP */ | 2133 | /* TODO else AP */ |
2134 | 2134 | ||
2135 | ath5k_hw_set_intr(ah, sc->imask); | 2135 | ath5k_hw_set_imr(ah, sc->imask); |
2136 | } | 2136 | } |
2137 | 2137 | ||
2138 | 2138 | ||
@@ -2211,7 +2211,7 @@ ath5k_stop_locked(struct ath5k_softc *sc) | |||
2211 | 2211 | ||
2212 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { | 2212 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { |
2213 | ath5k_led_off(sc); | 2213 | ath5k_led_off(sc); |
2214 | ath5k_hw_set_intr(ah, 0); | 2214 | ath5k_hw_set_imr(ah, 0); |
2215 | synchronize_irq(sc->pdev->irq); | 2215 | synchronize_irq(sc->pdev->irq); |
2216 | } | 2216 | } |
2217 | ath5k_txq_cleanup(sc); | 2217 | ath5k_txq_cleanup(sc); |
@@ -2604,7 +2604,7 @@ ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel) | |||
2604 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); | 2604 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); |
2605 | 2605 | ||
2606 | if (stop) { | 2606 | if (stop) { |
2607 | ath5k_hw_set_intr(ah, 0); | 2607 | ath5k_hw_set_imr(ah, 0); |
2608 | ath5k_txq_cleanup(sc); | 2608 | ath5k_txq_cleanup(sc); |
2609 | ath5k_rx_stop(sc); | 2609 | ath5k_rx_stop(sc); |
2610 | } | 2610 | } |