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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_mac.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c176
1 files changed, 0 insertions, 176 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index cb86c957708..f7d8e516a2a 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -270,35 +270,6 @@ ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
270 | SM(i->rtscts_rate, AR_RTSCTSRate); 270 | SM(i->rtscts_rate, AR_RTSCTSRate);
271} 271}
272 272
273static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
274 bool is_firstseg, bool is_lastseg,
275 const void *ds0, dma_addr_t buf_addr,
276 unsigned int qcu)
277{
278 struct ar5416_desc *ads = AR5416DESC(ds);
279
280 ads->ds_data = buf_addr;
281
282 if (is_firstseg) {
283 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
284 } else if (is_lastseg) {
285 ads->ds_ctl0 = 0;
286 ads->ds_ctl1 = seglen;
287 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
288 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
289 } else {
290 ads->ds_ctl0 = 0;
291 ads->ds_ctl1 = seglen | AR_TxMore;
292 ads->ds_ctl2 = 0;
293 ads->ds_ctl3 = 0;
294 }
295 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
296 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
297 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
298 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
299 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
300}
301
302static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, 273static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
303 struct ath_tx_status *ts) 274 struct ath_tx_status *ts)
304{ 275{
@@ -371,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
371 return 0; 342 return 0;
372} 343}
373 344
374static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
375 u32 pktLen, enum ath9k_pkt_type type,
376 u32 txPower, u8 keyIx,
377 enum ath9k_key_type keyType, u32 flags)
378{
379 struct ar5416_desc *ads = AR5416DESC(ds);
380
381 if (txPower > 63)
382 txPower = 63;
383
384 ads->ds_ctl0 = (pktLen & AR_FrameLen)
385 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
386 | SM(txPower, AR_XmitPower)
387 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
388 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
389 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
390
391 ads->ds_ctl1 =
392 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
393 | SM(type, AR_FrameType)
394 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
395 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
396 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
397
398 ads->ds_ctl6 = SM(keyType, AR_EncrType);
399
400 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
401 ads->ds_ctl8 = 0;
402 ads->ds_ctl9 = 0;
403 ads->ds_ctl10 = 0;
404 ads->ds_ctl11 = 0;
405 }
406}
407
408static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
409{
410 struct ar5416_desc *ads = AR5416DESC(ds);
411
412 if (val)
413 ads->ds_ctl0 |= AR_ClrDestMask;
414 else
415 ads->ds_ctl0 &= ~AR_ClrDestMask;
416}
417
418static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
419 void *lastds,
420 u32 durUpdateEn, u32 rtsctsRate,
421 u32 rtsctsDuration,
422 struct ath9k_11n_rate_series series[],
423 u32 nseries, u32 flags)
424{
425 struct ar5416_desc *ads = AR5416DESC(ds);
426 struct ar5416_desc *last_ads = AR5416DESC(lastds);
427 u32 ds_ctl0;
428
429 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
430 ds_ctl0 = ads->ds_ctl0;
431
432 if (flags & ATH9K_TXDESC_RTSENA) {
433 ds_ctl0 &= ~AR_CTSEnable;
434 ds_ctl0 |= AR_RTSEnable;
435 } else {
436 ds_ctl0 &= ~AR_RTSEnable;
437 ds_ctl0 |= AR_CTSEnable;
438 }
439
440 ads->ds_ctl0 = ds_ctl0;
441 } else {
442 ads->ds_ctl0 =
443 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
444 }
445
446 ads->ds_ctl2 = set11nTries(series, 0)
447 | set11nTries(series, 1)
448 | set11nTries(series, 2)
449 | set11nTries(series, 3)
450 | (durUpdateEn ? AR_DurUpdateEna : 0)
451 | SM(0, AR_BurstDur);
452
453 ads->ds_ctl3 = set11nRate(series, 0)
454 | set11nRate(series, 1)
455 | set11nRate(series, 2)
456 | set11nRate(series, 3);
457
458 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
459 | set11nPktDurRTSCTS(series, 1);
460
461 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
462 | set11nPktDurRTSCTS(series, 3);
463
464 ads->ds_ctl7 = set11nRateFlags(series, 0)
465 | set11nRateFlags(series, 1)
466 | set11nRateFlags(series, 2)
467 | set11nRateFlags(series, 3)
468 | SM(rtsctsRate, AR_RTSCTSRate);
469 last_ads->ds_ctl2 = ads->ds_ctl2;
470 last_ads->ds_ctl3 = ads->ds_ctl3;
471}
472
473static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
474 u32 aggrLen)
475{
476 struct ar5416_desc *ads = AR5416DESC(ds);
477
478 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
479 ads->ds_ctl6 &= ~AR_AggrLen;
480 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
481}
482
483static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
484 u32 numDelims)
485{
486 struct ar5416_desc *ads = AR5416DESC(ds);
487 unsigned int ctl6;
488
489 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
490
491 ctl6 = ads->ds_ctl6;
492 ctl6 &= ~AR_PadDelim;
493 ctl6 |= SM(numDelims, AR_PadDelim);
494 ads->ds_ctl6 = ctl6;
495}
496
497static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
498{
499 struct ar5416_desc *ads = AR5416DESC(ds);
500
501 ads->ds_ctl1 |= AR_IsAggr;
502 ads->ds_ctl1 &= ~AR_MoreAggr;
503 ads->ds_ctl6 &= ~AR_PadDelim;
504}
505
506static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
507{
508 struct ar5416_desc *ads = AR5416DESC(ds);
509
510 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
511}
512
513void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 345void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
514 u32 size, u32 flags) 346 u32 size, u32 flags)
515{ 347{
@@ -534,13 +366,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
534 ops->set_desc_link = ar9002_hw_set_desc_link; 366 ops->set_desc_link = ar9002_hw_set_desc_link;
535 ops->get_isr = ar9002_hw_get_isr; 367 ops->get_isr = ar9002_hw_get_isr;
536 ops->set_txdesc = ar9002_set_txdesc; 368 ops->set_txdesc = ar9002_set_txdesc;
537 ops->fill_txdesc = ar9002_hw_fill_txdesc;
538 ops->proc_txdesc = ar9002_hw_proc_txdesc; 369 ops->proc_txdesc = ar9002_hw_proc_txdesc;
539 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
540 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
541 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
542 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
543 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
544 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
545 ops->set_clrdmask = ar9002_hw_set_clrdmask;
546} 370}