diff options
Diffstat (limited to 'drivers/net/igb/e1000_phy.h')
-rw-r--r-- | drivers/net/igb/e1000_phy.h | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_phy.h b/drivers/net/igb/e1000_phy.h new file mode 100644 index 00000000000..8510797b9d8 --- /dev/null +++ b/drivers/net/igb/e1000_phy.h | |||
@@ -0,0 +1,136 @@ | |||
1 | /******************************************************************************* | ||
2 | |||
3 | Intel(R) Gigabit Ethernet Linux driver | ||
4 | Copyright(c) 2007-2011 Intel Corporation. | ||
5 | |||
6 | This program is free software; you can redistribute it and/or modify it | ||
7 | under the terms and conditions of the GNU General Public License, | ||
8 | version 2, as published by the Free Software Foundation. | ||
9 | |||
10 | This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | more details. | ||
14 | |||
15 | You should have received a copy of the GNU General Public License along with | ||
16 | this program; if not, write to the Free Software Foundation, Inc., | ||
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | |||
19 | The full GNU General Public License is included in this distribution in | ||
20 | the file called "COPYING". | ||
21 | |||
22 | Contact Information: | ||
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | ||
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | ||
25 | |||
26 | *******************************************************************************/ | ||
27 | |||
28 | #ifndef _E1000_PHY_H_ | ||
29 | #define _E1000_PHY_H_ | ||
30 | |||
31 | enum e1000_ms_type { | ||
32 | e1000_ms_hw_default = 0, | ||
33 | e1000_ms_force_master, | ||
34 | e1000_ms_force_slave, | ||
35 | e1000_ms_auto | ||
36 | }; | ||
37 | |||
38 | enum e1000_smart_speed { | ||
39 | e1000_smart_speed_default = 0, | ||
40 | e1000_smart_speed_on, | ||
41 | e1000_smart_speed_off | ||
42 | }; | ||
43 | |||
44 | s32 igb_check_downshift(struct e1000_hw *hw); | ||
45 | s32 igb_check_reset_block(struct e1000_hw *hw); | ||
46 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw); | ||
47 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw); | ||
48 | s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw); | ||
49 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); | ||
50 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); | ||
51 | s32 igb_get_cable_length_m88(struct e1000_hw *hw); | ||
52 | s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw); | ||
53 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); | ||
54 | s32 igb_get_phy_id(struct e1000_hw *hw); | ||
55 | s32 igb_get_phy_info_igp(struct e1000_hw *hw); | ||
56 | s32 igb_get_phy_info_m88(struct e1000_hw *hw); | ||
57 | s32 igb_phy_sw_reset(struct e1000_hw *hw); | ||
58 | s32 igb_phy_hw_reset(struct e1000_hw *hw); | ||
59 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); | ||
60 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); | ||
61 | s32 igb_setup_copper_link(struct e1000_hw *hw); | ||
62 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); | ||
63 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, | ||
64 | u32 usec_interval, bool *success); | ||
65 | void igb_power_up_phy_copper(struct e1000_hw *hw); | ||
66 | void igb_power_down_phy_copper(struct e1000_hw *hw); | ||
67 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw); | ||
68 | s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); | ||
69 | s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); | ||
70 | s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); | ||
71 | s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); | ||
72 | s32 igb_copper_link_setup_82580(struct e1000_hw *hw); | ||
73 | s32 igb_get_phy_info_82580(struct e1000_hw *hw); | ||
74 | s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); | ||
75 | s32 igb_get_cable_length_82580(struct e1000_hw *hw); | ||
76 | |||
77 | /* IGP01E1000 Specific Registers */ | ||
78 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ | ||
79 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ | ||
80 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ | ||
81 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ | ||
82 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ | ||
83 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ | ||
84 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 | ||
85 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 | ||
86 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 | ||
87 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ | ||
88 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 | ||
89 | |||
90 | #define I82580_ADDR_REG 16 | ||
91 | #define I82580_CFG_REG 22 | ||
92 | #define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15) | ||
93 | #define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | ||
94 | #define I82580_CTRL_REG 23 | ||
95 | #define I82580_CTRL_DOWNSHIFT_MASK (7 << 10) | ||
96 | |||
97 | /* 82580 specific PHY registers */ | ||
98 | #define I82580_PHY_CTRL_2 18 | ||
99 | #define I82580_PHY_LBK_CTRL 19 | ||
100 | #define I82580_PHY_STATUS_2 26 | ||
101 | #define I82580_PHY_DIAG_STATUS 31 | ||
102 | |||
103 | /* I82580 PHY Status 2 */ | ||
104 | #define I82580_PHY_STATUS2_REV_POLARITY 0x0400 | ||
105 | #define I82580_PHY_STATUS2_MDIX 0x0800 | ||
106 | #define I82580_PHY_STATUS2_SPEED_MASK 0x0300 | ||
107 | #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200 | ||
108 | #define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100 | ||
109 | |||
110 | /* I82580 PHY Control 2 */ | ||
111 | #define I82580_PHY_CTRL2_AUTO_MDIX 0x0400 | ||
112 | #define I82580_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | ||
113 | |||
114 | /* I82580 PHY Diagnostics Status */ | ||
115 | #define I82580_DSTATUS_CABLE_LENGTH 0x03FC | ||
116 | #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2 | ||
117 | /* Enable flexible speed on link-up */ | ||
118 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ | ||
119 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ | ||
120 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 | ||
121 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 | ||
122 | #define IGP01E1000_PSSR_MDIX 0x0800 | ||
123 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 | ||
124 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 | ||
125 | #define IGP02E1000_PHY_CHANNEL_NUM 4 | ||
126 | #define IGP02E1000_PHY_AGC_A 0x11B1 | ||
127 | #define IGP02E1000_PHY_AGC_B 0x12B1 | ||
128 | #define IGP02E1000_PHY_AGC_C 0x14B1 | ||
129 | #define IGP02E1000_PHY_AGC_D 0x18B1 | ||
130 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ | ||
131 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F | ||
132 | #define IGP02E1000_AGC_RANGE 15 | ||
133 | |||
134 | #define E1000_CABLE_LENGTH_UNDEFINED 0xFF | ||
135 | |||
136 | #endif | ||