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path: root/drivers/media/video/cx25821/cx25821-medusa-video.c
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Diffstat (limited to 'drivers/media/video/cx25821/cx25821-medusa-video.c')
-rw-r--r--drivers/media/video/cx25821/cx25821-medusa-video.c410
1 files changed, 164 insertions, 246 deletions
diff --git a/drivers/media/video/cx25821/cx25821-medusa-video.c b/drivers/media/video/cx25821/cx25821-medusa-video.c
index fc780d0908d..298a68d98c2 100644
--- a/drivers/media/video/cx25821/cx25821-medusa-video.c
+++ b/drivers/media/video/cx25821/cx25821-medusa-video.c
@@ -99,82 +99,67 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
99 99
100 for (i = 0; i < MAX_DECODERS; i++) { 100 for (i = 0; i < MAX_DECODERS; i++) {
101 /* set video format NTSC-M */ 101 /* set video format NTSC-M */
102 value = 102 value = cx25821_i2c_read(&dev->i2c_bus[0],
103 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 103 MODE_CTRL + (0x200 * i), &tmp);
104 &tmp);
105 value &= 0xFFFFFFF0; 104 value &= 0xFFFFFFF0;
106 /* enable the fast locking mode bit[16] */ 105 /* enable the fast locking mode bit[16] */
107 value |= 0x10001; 106 value |= 0x10001;
108 ret_val = 107 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
109 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 108 MODE_CTRL + (0x200 * i), value);
110 value);
111 109
112 /* resolution NTSC 720x480 */ 110 /* resolution NTSC 720x480 */
113 value = 111 value = cx25821_i2c_read(&dev->i2c_bus[0],
114 cx25821_i2c_read(&dev->i2c_bus[0], 112 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
115 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
116 value &= 0x00C00C00; 113 value &= 0x00C00C00;
117 value |= 0x612D0074; 114 value |= 0x612D0074;
118 ret_val = 115 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
119 cx25821_i2c_write(&dev->i2c_bus[0], 116 HORIZ_TIM_CTRL + (0x200 * i), value);
120 HORIZ_TIM_CTRL + (0x200 * i), value);
121 117
122 value = 118 value = cx25821_i2c_read(&dev->i2c_bus[0],
123 cx25821_i2c_read(&dev->i2c_bus[0], 119 VERT_TIM_CTRL + (0x200 * i), &tmp);
124 VERT_TIM_CTRL + (0x200 * i), &tmp);
125 value &= 0x00C00C00; 120 value &= 0x00C00C00;
126 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */ 121 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
127 ret_val = 122 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
128 cx25821_i2c_write(&dev->i2c_bus[0], 123 VERT_TIM_CTRL + (0x200 * i), value);
129 VERT_TIM_CTRL + (0x200 * i), value);
130 124
131 /* chroma subcarrier step size */ 125 /* chroma subcarrier step size */
132 ret_val = 126 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
133 cx25821_i2c_write(&dev->i2c_bus[0], 127 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
134 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
135 128
136 /* enable VIP optional active */ 129 /* enable VIP optional active */
137 value = 130 value = cx25821_i2c_read(&dev->i2c_bus[0],
138 cx25821_i2c_read(&dev->i2c_bus[0], 131 OUT_CTRL_NS + (0x200 * i), &tmp);
139 OUT_CTRL_NS + (0x200 * i), &tmp);
140 value &= 0xFFFBFFFF; 132 value &= 0xFFFBFFFF;
141 value |= 0x00040000; 133 value |= 0x00040000;
142 ret_val = 134 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
143 cx25821_i2c_write(&dev->i2c_bus[0], 135 OUT_CTRL_NS + (0x200 * i), value);
144 OUT_CTRL_NS + (0x200 * i), value);
145 136
146 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 137 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
147 value = 138 value = cx25821_i2c_read(&dev->i2c_bus[0],
148 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 139 OUT_CTRL1 + (0x200 * i), &tmp);
149 &tmp);
150 value &= 0xFFFBFFFF; 140 value &= 0xFFFBFFFF;
151 value |= 0x00040000; 141 value |= 0x00040000;
152 ret_val = 142 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
153 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 143 OUT_CTRL1 + (0x200 * i), value);
154 value);
155 144
156 /* 145 /*
157 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 146 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
158 * when the input switching rate < 16 fields 147 * when the input switching rate < 16 fields
159 */ 148 */
160 value = 149 value = cx25821_i2c_read(&dev->i2c_bus[0],
161 cx25821_i2c_read(&dev->i2c_bus[0], 150 MISC_TIM_CTRL + (0x200 * i), &tmp);
162 MISC_TIM_CTRL + (0x200 * i), &tmp);
163 /* disable special play detection */ 151 /* disable special play detection */
164 value = setBitAtPos(value, 14); 152 value = setBitAtPos(value, 14);
165 value = clearBitAtPos(value, 15); 153 value = clearBitAtPos(value, 15);
166 ret_val = 154 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
167 cx25821_i2c_write(&dev->i2c_bus[0], 155 MISC_TIM_CTRL + (0x200 * i), value);
168 MISC_TIM_CTRL + (0x200 * i), value);
169 156
170 /* set vbi_gate_en to 0 */ 157 /* set vbi_gate_en to 0 */
171 value = 158 value = cx25821_i2c_read(&dev->i2c_bus[0],
172 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 159 DFE_CTRL1 + (0x200 * i), &tmp);
173 &tmp);
174 value = clearBitAtPos(value, 29); 160 value = clearBitAtPos(value, 29);
175 ret_val = 161 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
176 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 162 DFE_CTRL1 + (0x200 * i), value);
177 value);
178 163
179 /* Enable the generation of blue field output if no video */ 164 /* Enable the generation of blue field output if no video */
180 medusa_enable_bluefield_output(dev, i, 1); 165 medusa_enable_bluefield_output(dev, i, 1);
@@ -182,61 +167,49 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
182 167
183 for (i = 0; i < MAX_ENCODERS; i++) { 168 for (i = 0; i < MAX_ENCODERS; i++) {
184 /* NTSC hclock */ 169 /* NTSC hclock */
185 value = 170 value = cx25821_i2c_read(&dev->i2c_bus[0],
186 cx25821_i2c_read(&dev->i2c_bus[0], 171 DENC_A_REG_1 + (0x100 * i), &tmp);
187 DENC_A_REG_1 + (0x100 * i), &tmp);
188 value &= 0xF000FC00; 172 value &= 0xF000FC00;
189 value |= 0x06B402D0; 173 value |= 0x06B402D0;
190 ret_val = 174 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
191 cx25821_i2c_write(&dev->i2c_bus[0], 175 DENC_A_REG_1 + (0x100 * i), value);
192 DENC_A_REG_1 + (0x100 * i), value);
193 176
194 /* burst begin and burst end */ 177 /* burst begin and burst end */
195 value = 178 value = cx25821_i2c_read(&dev->i2c_bus[0],
196 cx25821_i2c_read(&dev->i2c_bus[0], 179 DENC_A_REG_2 + (0x100 * i), &tmp);
197 DENC_A_REG_2 + (0x100 * i), &tmp);
198 value &= 0xFF000000; 180 value &= 0xFF000000;
199 value |= 0x007E9054; 181 value |= 0x007E9054;
200 ret_val = 182 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
201 cx25821_i2c_write(&dev->i2c_bus[0], 183 DENC_A_REG_2 + (0x100 * i), value);
202 DENC_A_REG_2 + (0x100 * i), value);
203 184
204 value = 185 value = cx25821_i2c_read(&dev->i2c_bus[0],
205 cx25821_i2c_read(&dev->i2c_bus[0], 186 DENC_A_REG_3 + (0x100 * i), &tmp);
206 DENC_A_REG_3 + (0x100 * i), &tmp);
207 value &= 0xFC00FE00; 187 value &= 0xFC00FE00;
208 value |= 0x00EC00F0; 188 value |= 0x00EC00F0;
209 ret_val = 189 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
210 cx25821_i2c_write(&dev->i2c_bus[0], 190 DENC_A_REG_3 + (0x100 * i), value);
211 DENC_A_REG_3 + (0x100 * i), value);
212 191
213 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */ 192 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
214 value = 193 value = cx25821_i2c_read(&dev->i2c_bus[0],
215 cx25821_i2c_read(&dev->i2c_bus[0], 194 DENC_A_REG_4 + (0x100 * i), &tmp);
216 DENC_A_REG_4 + (0x100 * i), &tmp);
217 value &= 0x00FCFFFF; 195 value &= 0x00FCFFFF;
218 value |= 0x13020000; 196 value |= 0x13020000;
219 ret_val = 197 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
220 cx25821_i2c_write(&dev->i2c_bus[0], 198 DENC_A_REG_4 + (0x100 * i), value);
221 DENC_A_REG_4 + (0x100 * i), value);
222 199
223 value = 200 value = cx25821_i2c_read(&dev->i2c_bus[0],
224 cx25821_i2c_read(&dev->i2c_bus[0], 201 DENC_A_REG_5 + (0x100 * i), &tmp);
225 DENC_A_REG_5 + (0x100 * i), &tmp);
226 value &= 0xFFFF0000; 202 value &= 0xFFFF0000;
227 value |= 0x0000E575; 203 value |= 0x0000E575;
228 ret_val = 204 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
229 cx25821_i2c_write(&dev->i2c_bus[0], 205 DENC_A_REG_5 + (0x100 * i), value);
230 DENC_A_REG_5 + (0x100 * i), value);
231 206
232 ret_val = 207 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
233 cx25821_i2c_write(&dev->i2c_bus[0], 208 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
234 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
235 209
236 /* Subcarrier Increment */ 210 /* Subcarrier Increment */
237 ret_val = 211 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
238 cx25821_i2c_write(&dev->i2c_bus[0], 212 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
239 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
240 } 213 }
241 214
242 /* set picture resolutions */ 215 /* set picture resolutions */
@@ -261,34 +234,27 @@ static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
261 u32 value = 0, tmp = 0; 234 u32 value = 0, tmp = 0;
262 235
263 /* Setup for 2D threshold */ 236 /* Setup for 2D threshold */
264 ret_val = 237 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
265 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec), 238 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
266 0x20002861); 239 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
267 ret_val = 240 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
268 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec), 241 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
269 0x20002861); 242 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
270 ret_val =
271 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
272 0x200A1023);
273 243
274 /* Setup flat chroma and luma thresholds */ 244 /* Setup flat chroma and luma thresholds */
275 value = 245 value = cx25821_i2c_read(&dev->i2c_bus[0],
276 cx25821_i2c_read(&dev->i2c_bus[0], 246 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
277 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
278 value &= 0x06230000; 247 value &= 0x06230000;
279 ret_val = 248 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
280 cx25821_i2c_write(&dev->i2c_bus[0], 249 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
281 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
282 250
283 /* set comb 2D blend */ 251 /* set comb 2D blend */
284 ret_val = 252 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
285 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec), 253 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
286 0x210F0F0F);
287 254
288 /* COMB MISC CONTROL */ 255 /* COMB MISC CONTROL */
289 ret_val = 256 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
290 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec), 257 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
291 0x41120A7F);
292 258
293 return ret_val; 259 return ret_val;
294} 260}
@@ -304,83 +270,68 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
304 270
305 for (i = 0; i < MAX_DECODERS; i++) { 271 for (i = 0; i < MAX_DECODERS; i++) {
306 /* set video format PAL-BDGHI */ 272 /* set video format PAL-BDGHI */
307 value = 273 value = cx25821_i2c_read(&dev->i2c_bus[0],
308 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 274 MODE_CTRL + (0x200 * i), &tmp);
309 &tmp);
310 value &= 0xFFFFFFF0; 275 value &= 0xFFFFFFF0;
311 /* enable the fast locking mode bit[16] */ 276 /* enable the fast locking mode bit[16] */
312 value |= 0x10004; 277 value |= 0x10004;
313 ret_val = 278 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
314 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 279 MODE_CTRL + (0x200 * i), value);
315 value);
316 280
317 /* resolution PAL 720x576 */ 281 /* resolution PAL 720x576 */
318 value = 282 value = cx25821_i2c_read(&dev->i2c_bus[0],
319 cx25821_i2c_read(&dev->i2c_bus[0], 283 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
320 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
321 value &= 0x00C00C00; 284 value &= 0x00C00C00;
322 value |= 0x632D007D; 285 value |= 0x632D007D;
323 ret_val = 286 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
324 cx25821_i2c_write(&dev->i2c_bus[0], 287 HORIZ_TIM_CTRL + (0x200 * i), value);
325 HORIZ_TIM_CTRL + (0x200 * i), value);
326 288
327 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */ 289 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
328 value = 290 value = cx25821_i2c_read(&dev->i2c_bus[0],
329 cx25821_i2c_read(&dev->i2c_bus[0], 291 VERT_TIM_CTRL + (0x200 * i), &tmp);
330 VERT_TIM_CTRL + (0x200 * i), &tmp);
331 value &= 0x00C00C00; 292 value &= 0x00C00C00;
332 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */ 293 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
333 ret_val = 294 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
334 cx25821_i2c_write(&dev->i2c_bus[0], 295 VERT_TIM_CTRL + (0x200 * i), value);
335 VERT_TIM_CTRL + (0x200 * i), value);
336 296
337 /* chroma subcarrier step size */ 297 /* chroma subcarrier step size */
338 ret_val = 298 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
339 cx25821_i2c_write(&dev->i2c_bus[0], 299 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
340 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
341 300
342 /* enable VIP optional active */ 301 /* enable VIP optional active */
343 value = 302 value = cx25821_i2c_read(&dev->i2c_bus[0],
344 cx25821_i2c_read(&dev->i2c_bus[0], 303 OUT_CTRL_NS + (0x200 * i), &tmp);
345 OUT_CTRL_NS + (0x200 * i), &tmp);
346 value &= 0xFFFBFFFF; 304 value &= 0xFFFBFFFF;
347 value |= 0x00040000; 305 value |= 0x00040000;
348 ret_val = 306 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
349 cx25821_i2c_write(&dev->i2c_bus[0], 307 OUT_CTRL_NS + (0x200 * i), value);
350 OUT_CTRL_NS + (0x200 * i), value);
351 308
352 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 309 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
353 value = 310 value = cx25821_i2c_read(&dev->i2c_bus[0],
354 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 311 OUT_CTRL1 + (0x200 * i), &tmp);
355 &tmp);
356 value &= 0xFFFBFFFF; 312 value &= 0xFFFBFFFF;
357 value |= 0x00040000; 313 value |= 0x00040000;
358 ret_val = 314 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
359 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 315 OUT_CTRL1 + (0x200 * i), value);
360 value);
361 316
362 /* 317 /*
363 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 318 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
364 * when the input switching rate < 16 fields 319 * when the input switching rate < 16 fields
365 */ 320 */
366 value = 321 value = cx25821_i2c_read(&dev->i2c_bus[0],
367 cx25821_i2c_read(&dev->i2c_bus[0], 322 MISC_TIM_CTRL + (0x200 * i), &tmp);
368 MISC_TIM_CTRL + (0x200 * i), &tmp);
369 /* disable special play detection */ 323 /* disable special play detection */
370 value = setBitAtPos(value, 14); 324 value = setBitAtPos(value, 14);
371 value = clearBitAtPos(value, 15); 325 value = clearBitAtPos(value, 15);
372 ret_val = 326 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
373 cx25821_i2c_write(&dev->i2c_bus[0], 327 MISC_TIM_CTRL + (0x200 * i), value);
374 MISC_TIM_CTRL + (0x200 * i), value);
375 328
376 /* set vbi_gate_en to 0 */ 329 /* set vbi_gate_en to 0 */
377 value = 330 value = cx25821_i2c_read(&dev->i2c_bus[0],
378 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 331 DFE_CTRL1 + (0x200 * i), &tmp);
379 &tmp);
380 value = clearBitAtPos(value, 29); 332 value = clearBitAtPos(value, 29);
381 ret_val = 333 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
382 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 334 DFE_CTRL1 + (0x200 * i), value);
383 value);
384 335
385 medusa_PALCombInit(dev, i); 336 medusa_PALCombInit(dev, i);
386 337
@@ -390,62 +341,50 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
390 341
391 for (i = 0; i < MAX_ENCODERS; i++) { 342 for (i = 0; i < MAX_ENCODERS; i++) {
392 /* PAL hclock */ 343 /* PAL hclock */
393 value = 344 value = cx25821_i2c_read(&dev->i2c_bus[0],
394 cx25821_i2c_read(&dev->i2c_bus[0], 345 DENC_A_REG_1 + (0x100 * i), &tmp);
395 DENC_A_REG_1 + (0x100 * i), &tmp);
396 value &= 0xF000FC00; 346 value &= 0xF000FC00;
397 value |= 0x06C002D0; 347 value |= 0x06C002D0;
398 ret_val = 348 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
399 cx25821_i2c_write(&dev->i2c_bus[0], 349 DENC_A_REG_1 + (0x100 * i), value);
400 DENC_A_REG_1 + (0x100 * i), value);
401 350
402 /* burst begin and burst end */ 351 /* burst begin and burst end */
403 value = 352 value = cx25821_i2c_read(&dev->i2c_bus[0],
404 cx25821_i2c_read(&dev->i2c_bus[0], 353 DENC_A_REG_2 + (0x100 * i), &tmp);
405 DENC_A_REG_2 + (0x100 * i), &tmp);
406 value &= 0xFF000000; 354 value &= 0xFF000000;
407 value |= 0x007E9754; 355 value |= 0x007E9754;
408 ret_val = 356 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
409 cx25821_i2c_write(&dev->i2c_bus[0], 357 DENC_A_REG_2 + (0x100 * i), value);
410 DENC_A_REG_2 + (0x100 * i), value);
411 358
412 /* hblank and vactive */ 359 /* hblank and vactive */
413 value = 360 value = cx25821_i2c_read(&dev->i2c_bus[0],
414 cx25821_i2c_read(&dev->i2c_bus[0], 361 DENC_A_REG_3 + (0x100 * i), &tmp);
415 DENC_A_REG_3 + (0x100 * i), &tmp);
416 value &= 0xFC00FE00; 362 value &= 0xFC00FE00;
417 value |= 0x00FC0120; 363 value |= 0x00FC0120;
418 ret_val = 364 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
419 cx25821_i2c_write(&dev->i2c_bus[0], 365 DENC_A_REG_3 + (0x100 * i), value);
420 DENC_A_REG_3 + (0x100 * i), value);
421 366
422 /* set PAL vblank, phase alternation, 0 IRE pedestal */ 367 /* set PAL vblank, phase alternation, 0 IRE pedestal */
423 value = 368 value = cx25821_i2c_read(&dev->i2c_bus[0],
424 cx25821_i2c_read(&dev->i2c_bus[0], 369 DENC_A_REG_4 + (0x100 * i), &tmp);
425 DENC_A_REG_4 + (0x100 * i), &tmp);
426 value &= 0x00FCFFFF; 370 value &= 0x00FCFFFF;
427 value |= 0x14010000; 371 value |= 0x14010000;
428 ret_val = 372 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
429 cx25821_i2c_write(&dev->i2c_bus[0], 373 DENC_A_REG_4 + (0x100 * i), value);
430 DENC_A_REG_4 + (0x100 * i), value);
431 374
432 value = 375 value = cx25821_i2c_read(&dev->i2c_bus[0],
433 cx25821_i2c_read(&dev->i2c_bus[0], 376 DENC_A_REG_5 + (0x100 * i), &tmp);
434 DENC_A_REG_5 + (0x100 * i), &tmp);
435 value &= 0xFFFF0000; 377 value &= 0xFFFF0000;
436 value |= 0x0000F078; 378 value |= 0x0000F078;
437 ret_val = 379 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
438 cx25821_i2c_write(&dev->i2c_bus[0], 380 DENC_A_REG_5 + (0x100 * i), value);
439 DENC_A_REG_5 + (0x100 * i), value);
440 381
441 ret_val = 382 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
442 cx25821_i2c_write(&dev->i2c_bus[0], 383 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
443 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
444 384
445 /* Subcarrier Increment */ 385 /* Subcarrier Increment */
446 ret_val = 386 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
447 cx25821_i2c_write(&dev->i2c_bus[0], 387 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
448 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
449 } 388 }
450 389
451 /* set picture resolutions */ 390 /* set picture resolutions */
@@ -499,7 +438,7 @@ void medusa_set_resolution(struct cx25821_dev *dev, int width,
499 438
500 mutex_lock(&dev->lock); 439 mutex_lock(&dev->lock);
501 440
502 /* validate the width - cannot be negative */ 441 /* validate the width */
503 if (width > MAX_WIDTH) { 442 if (width > MAX_WIDTH) {
504 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n", 443 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
505 __func__, width, MAX_WIDTH); 444 __func__, width, MAX_WIDTH);
@@ -543,12 +482,10 @@ void medusa_set_resolution(struct cx25821_dev *dev, int width,
543 482
544 for (; decoder < decoder_count; decoder++) { 483 for (; decoder < decoder_count; decoder++) {
545 /* write scaling values for each decoder */ 484 /* write scaling values for each decoder */
546 ret_val = 485 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
547 cx25821_i2c_write(&dev->i2c_bus[0], 486 HSCALE_CTRL + (0x200 * decoder), hscale);
548 HSCALE_CTRL + (0x200 * decoder), hscale); 487 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
549 ret_val = 488 VSCALE_CTRL + (0x200 * decoder), vscale);
550 cx25821_i2c_write(&dev->i2c_bus[0],
551 VSCALE_CTRL + (0x200 * decoder), vscale);
552 } 489 }
553 490
554 mutex_unlock(&dev->lock); 491 mutex_unlock(&dev->lock);
@@ -606,8 +543,8 @@ static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
606} 543}
607 544
608/* Map to Medusa register setting */ 545/* Map to Medusa register setting */
609static int mapM(int srcMin, 546static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
610 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal) 547 int *dstVal)
611{ 548{
612 int numerator; 549 int numerator;
613 int denominator; 550 int denominator;
@@ -654,23 +591,19 @@ int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
654 u32 val = 0, tmp = 0; 591 u32 val = 0, tmp = 0;
655 592
656 mutex_lock(&dev->lock); 593 mutex_lock(&dev->lock);
657 if ((brightness > VIDEO_PROCAMP_MAX) 594 if ((brightness > VIDEO_PROCAMP_MAX) ||
658 || (brightness < VIDEO_PROCAMP_MIN)) { 595 (brightness < VIDEO_PROCAMP_MIN)) {
659 mutex_unlock(&dev->lock); 596 mutex_unlock(&dev->lock);
660 return -1; 597 return -1;
661 } 598 }
662 ret_val = 599 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
663 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness, 600 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
664 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
665 value = convert_to_twos(value, 8); 601 value = convert_to_twos(value, 8);
666 val = 602 val = cx25821_i2c_read(&dev->i2c_bus[0],
667 cx25821_i2c_read(&dev->i2c_bus[0], 603 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
668 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
669 val &= 0xFFFFFF00; 604 val &= 0xFFFFFF00;
670 ret_val |= 605 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
671 cx25821_i2c_write(&dev->i2c_bus[0], 606 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
672 VDEC_A_BRITE_CTRL + (0x200 * decoder),
673 val | value);
674 mutex_unlock(&dev->lock); 607 mutex_unlock(&dev->lock);
675 return ret_val; 608 return ret_val;
676} 609}
@@ -688,17 +621,13 @@ int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
688 return -1; 621 return -1;
689 } 622 }
690 623
691 ret_val = 624 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
692 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast, 625 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
693 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); 626 val = cx25821_i2c_read(&dev->i2c_bus[0],
694 val = 627 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
695 cx25821_i2c_read(&dev->i2c_bus[0],
696 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
697 val &= 0xFFFFFF00; 628 val &= 0xFFFFFF00;
698 ret_val |= 629 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
699 cx25821_i2c_write(&dev->i2c_bus[0], 630 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
700 VDEC_A_CNTRST_CTRL + (0x200 * decoder),
701 val | value);
702 631
703 mutex_unlock(&dev->lock); 632 mutex_unlock(&dev->lock);
704 return ret_val; 633 return ret_val;
@@ -717,19 +646,16 @@ int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
717 return -1; 646 return -1;
718 } 647 }
719 648
720 ret_val = 649 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
721 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN, 650 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
722 SIGNED_BYTE_MAX, &value);
723 651
724 value = convert_to_twos(value, 8); 652 value = convert_to_twos(value, 8);
725 val = 653 val = cx25821_i2c_read(&dev->i2c_bus[0],
726 cx25821_i2c_read(&dev->i2c_bus[0], 654 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
727 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
728 val &= 0xFFFFFF00; 655 val &= 0xFFFFFF00;
729 656
730 ret_val |= 657 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
731 cx25821_i2c_write(&dev->i2c_bus[0], 658 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
732 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
733 659
734 mutex_unlock(&dev->lock); 660 mutex_unlock(&dev->lock);
735 return ret_val; 661 return ret_val;
@@ -743,33 +669,26 @@ int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
743 669
744 mutex_lock(&dev->lock); 670 mutex_lock(&dev->lock);
745 671
746 if ((saturation > VIDEO_PROCAMP_MAX) 672 if ((saturation > VIDEO_PROCAMP_MAX) ||
747 || (saturation < VIDEO_PROCAMP_MIN)) { 673 (saturation < VIDEO_PROCAMP_MIN)) {
748 mutex_unlock(&dev->lock); 674 mutex_unlock(&dev->lock);
749 return -1; 675 return -1;
750 } 676 }
751 677
752 ret_val = 678 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
753 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation, 679 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
754 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
755 680
756 val = 681 val = cx25821_i2c_read(&dev->i2c_bus[0],
757 cx25821_i2c_read(&dev->i2c_bus[0], 682 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
758 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
759 val &= 0xFFFFFF00; 683 val &= 0xFFFFFF00;
760 ret_val |= 684 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
761 cx25821_i2c_write(&dev->i2c_bus[0], 685 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
762 VDEC_A_USAT_CTRL + (0x200 * decoder), 686
763 val | value); 687 val = cx25821_i2c_read(&dev->i2c_bus[0],
764 688 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
765 val =
766 cx25821_i2c_read(&dev->i2c_bus[0],
767 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
768 val &= 0xFFFFFF00; 689 val &= 0xFFFFFF00;
769 ret_val |= 690 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
770 cx25821_i2c_write(&dev->i2c_bus[0], 691 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
771 VDEC_A_VSAT_CTRL + (0x200 * decoder),
772 val | value);
773 692
774 mutex_unlock(&dev->lock); 693 mutex_unlock(&dev->lock);
775 return ret_val; 694 return ret_val;
@@ -830,9 +749,8 @@ int medusa_video_init(struct cx25821_dev *dev)
830 /* select AFE clock to output mode */ 749 /* select AFE clock to output mode */
831 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 750 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
832 value &= 0x83FFFFFF; 751 value &= 0x83FFFFFF;
833 ret_val = 752 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
834 cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, 753 value | 0x10000000);
835 value | 0x10000000);
836 754
837 if (ret_val < 0) 755 if (ret_val < 0)
838 goto error; 756 goto error;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 21:39:10 -0400