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Diffstat (limited to 'drivers/media/dvb/frontends/dib7000p.c')
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c456
1 files changed, 246 insertions, 210 deletions
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index ce8534ff142..5ceadc285b3 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -70,6 +70,8 @@ struct dib7000p_state {
70 u8 i2c_write_buffer[4]; 70 u8 i2c_write_buffer[4];
71 u8 i2c_read_buffer[2]; 71 u8 i2c_read_buffer[2];
72 struct mutex i2c_buffer_lock; 72 struct mutex i2c_buffer_lock;
73
74 u8 input_mode_mpeg;
73}; 75};
74 76
75enum dib7000p_power_mode { 77enum dib7000p_power_mode {
@@ -78,8 +80,11 @@ enum dib7000p_power_mode {
78 DIB7000P_POWER_INTERFACE_ONLY, 80 DIB7000P_POWER_INTERFACE_ONLY,
79}; 81};
80 82
83/* dib7090 specific fonctions */
81static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode); 84static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
82static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff); 85static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
86static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
87static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
83 88
84static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) 89static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
85{ 90{
@@ -276,17 +281,23 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
276 dib7000p_write_word(state, 774, reg_774); 281 dib7000p_write_word(state, 774, reg_774);
277 dib7000p_write_word(state, 775, reg_775); 282 dib7000p_write_word(state, 775, reg_775);
278 dib7000p_write_word(state, 776, reg_776); 283 dib7000p_write_word(state, 776, reg_776);
279 dib7000p_write_word(state, 899, reg_899);
280 dib7000p_write_word(state, 1280, reg_1280); 284 dib7000p_write_word(state, 1280, reg_1280);
285 if (state->version != SOC7090)
286 dib7000p_write_word(state, 899, reg_899);
281 287
282 return 0; 288 return 0;
283} 289}
284 290
285static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) 291static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
286{ 292{
287 u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909); 293 u16 reg_908 = 0, reg_909 = 0;
288 u16 reg; 294 u16 reg;
289 295
296 if (state->version != SOC7090) {
297 reg_908 = dib7000p_read_word(state, 908);
298 reg_909 = dib7000p_read_word(state, 909);
299 }
300
290 switch (no) { 301 switch (no) {
291 case DIBX000_SLOW_ADC_ON: 302 case DIBX000_SLOW_ADC_ON:
292 if (state->version == SOC7090) { 303 if (state->version == SOC7090) {
@@ -342,8 +353,10 @@ static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_ad
342 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4; 353 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
343 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7; 354 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
344 355
345 dib7000p_write_word(state, 908, reg_908); 356 if (state->version != SOC7090) {
346 dib7000p_write_word(state, 909, reg_909); 357 dib7000p_write_word(state, 908, reg_908);
358 dib7000p_write_word(state, 909, reg_909);
359 }
347} 360}
348 361
349static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) 362static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
@@ -398,6 +411,24 @@ int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
398} 411}
399EXPORT_SYMBOL(dib7000p_set_wbd_ref); 412EXPORT_SYMBOL(dib7000p_set_wbd_ref);
400 413
414int dib7000p_get_agc_values(struct dvb_frontend *fe,
415 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
416{
417 struct dib7000p_state *state = fe->demodulator_priv;
418
419 if (agc_global != NULL)
420 *agc_global = dib7000p_read_word(state, 394);
421 if (agc1 != NULL)
422 *agc1 = dib7000p_read_word(state, 392);
423 if (agc2 != NULL)
424 *agc2 = dib7000p_read_word(state, 393);
425 if (wbd != NULL)
426 *wbd = dib7000p_read_word(state, 397);
427
428 return 0;
429}
430EXPORT_SYMBOL(dib7000p_get_agc_values);
431
401static void dib7000p_reset_pll(struct dib7000p_state *state) 432static void dib7000p_reset_pll(struct dib7000p_state *state)
402{ 433{
403 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 434 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
@@ -519,7 +550,7 @@ static u16 dib7000p_defaults[] = {
519 // auto search configuration 550 // auto search configuration
520 3, 2, 551 3, 2,
521 0x0004, 552 0x0004,
522 0x1000, 553 (1<<3)|(1<<11)|(1<<12)|(1<<13),
523 0x0814, /* Equal Lock */ 554 0x0814, /* Equal Lock */
524 555
525 12, 6, 556 12, 6,
@@ -595,13 +626,6 @@ static u16 dib7000p_defaults[] = {
595 1, 235, 626 1, 235,
596 0x0062, 627 0x0062,
597 628
598 2, 901,
599 0x0006,
600 (3 << 10) | (1 << 6),
601
602 1, 905,
603 0x2c8e,
604
605 0, 629 0,
606}; 630};
607 631
@@ -618,15 +642,18 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
618 dib7000p_write_word(state, 770, 0xffff); 642 dib7000p_write_word(state, 770, 0xffff);
619 dib7000p_write_word(state, 771, 0xffff); 643 dib7000p_write_word(state, 771, 0xffff);
620 dib7000p_write_word(state, 772, 0x001f); 644 dib7000p_write_word(state, 772, 0x001f);
621 dib7000p_write_word(state, 898, 0x0003);
622 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3))); 645 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
623 646
624 dib7000p_write_word(state, 770, 0); 647 dib7000p_write_word(state, 770, 0);
625 dib7000p_write_word(state, 771, 0); 648 dib7000p_write_word(state, 771, 0);
626 dib7000p_write_word(state, 772, 0); 649 dib7000p_write_word(state, 772, 0);
627 dib7000p_write_word(state, 898, 0);
628 dib7000p_write_word(state, 1280, 0); 650 dib7000p_write_word(state, 1280, 0);
629 651
652 if (state->version != SOC7090) {
653 dib7000p_write_word(state, 898, 0x0003);
654 dib7000p_write_word(state, 898, 0);
655 }
656
630 /* default */ 657 /* default */
631 dib7000p_reset_pll(state); 658 dib7000p_reset_pll(state);
632 659
@@ -640,7 +667,7 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
640 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */ 667 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
641 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */ 668 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
642 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */ 669 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
643 dib7000p_write_word(state, 273, (1<<6) | 30); 670 dib7000p_write_word(state, 273, (0<<6) | 30);
644 } 671 }
645 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 672 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
646 dprintk("OUTPUT_MODE could not be reset."); 673 dprintk("OUTPUT_MODE could not be reset.");
@@ -655,7 +682,7 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
655 dib7000p_set_bandwidth(state, 8000); 682 dib7000p_set_bandwidth(state, 8000);
656 683
657 if (state->version == SOC7090) { 684 if (state->version == SOC7090) {
658 dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */ 685 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
659 } else { 686 } else {
660 if (state->cfg.tuner_is_baseband) 687 if (state->cfg.tuner_is_baseband)
661 dib7000p_write_word(state, 36, 0x0755); 688 dib7000p_write_word(state, 36, 0x0755);
@@ -664,6 +691,11 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
664 } 691 }
665 692
666 dib7000p_write_tab(state, dib7000p_defaults); 693 dib7000p_write_tab(state, dib7000p_defaults);
694 if (state->version != SOC7090) {
695 dib7000p_write_word(state, 901, 0x0006);
696 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
697 dib7000p_write_word(state, 905, 0x2c8e);
698 }
667 699
668 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 700 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
669 701
@@ -780,8 +812,9 @@ static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
780 } 812 }
781} 813}
782 814
783static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 815static int dib7000p_agc_startup(struct dvb_frontend *demod)
784{ 816{
817 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
785 struct dib7000p_state *state = demod->demodulator_priv; 818 struct dib7000p_state *state = demod->demodulator_priv;
786 int ret = -1; 819 int ret = -1;
787 u8 *agc_state = &state->agc_state; 820 u8 *agc_state = &state->agc_state;
@@ -904,15 +937,16 @@ u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
904} 937}
905EXPORT_SYMBOL(dib7000p_ctrl_timf); 938EXPORT_SYMBOL(dib7000p_ctrl_timf);
906 939
907static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq) 940static void dib7000p_set_channel(struct dib7000p_state *state,
941 struct dtv_frontend_properties *ch, u8 seq)
908{ 942{
909 u16 value, est[4]; 943 u16 value, est[4];
910 944
911 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 945 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
912 946
913 /* nfft, guard, qam, alpha */ 947 /* nfft, guard, qam, alpha */
914 value = 0; 948 value = 0;
915 switch (ch->u.ofdm.transmission_mode) { 949 switch (ch->transmission_mode) {
916 case TRANSMISSION_MODE_2K: 950 case TRANSMISSION_MODE_2K:
917 value |= (0 << 7); 951 value |= (0 << 7);
918 break; 952 break;
@@ -924,7 +958,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
924 value |= (1 << 7); 958 value |= (1 << 7);
925 break; 959 break;
926 } 960 }
927 switch (ch->u.ofdm.guard_interval) { 961 switch (ch->guard_interval) {
928 case GUARD_INTERVAL_1_32: 962 case GUARD_INTERVAL_1_32:
929 value |= (0 << 5); 963 value |= (0 << 5);
930 break; 964 break;
@@ -939,7 +973,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
939 value |= (2 << 5); 973 value |= (2 << 5);
940 break; 974 break;
941 } 975 }
942 switch (ch->u.ofdm.constellation) { 976 switch (ch->modulation) {
943 case QPSK: 977 case QPSK:
944 value |= (0 << 3); 978 value |= (0 << 3);
945 break; 979 break;
@@ -970,11 +1004,11 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
970 value = 0; 1004 value = 0;
971 if (1 != 0) 1005 if (1 != 0)
972 value |= (1 << 6); 1006 value |= (1 << 6);
973 if (ch->u.ofdm.hierarchy_information == 1) 1007 if (ch->hierarchy == 1)
974 value |= (1 << 4); 1008 value |= (1 << 4);
975 if (1 == 1) 1009 if (1 == 1)
976 value |= 1; 1010 value |= 1;
977 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 1011 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
978 case FEC_2_3: 1012 case FEC_2_3:
979 value |= (2 << 1); 1013 value |= (2 << 1);
980 break; 1014 break;
@@ -1001,7 +1035,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1001 dib7000p_write_word(state, 33, 0x0005); 1035 dib7000p_write_word(state, 33, 0x0005);
1002 1036
1003 /* P_dvsy_sync_wait */ 1037 /* P_dvsy_sync_wait */
1004 switch (ch->u.ofdm.transmission_mode) { 1038 switch (ch->transmission_mode) {
1005 case TRANSMISSION_MODE_8K: 1039 case TRANSMISSION_MODE_8K:
1006 value = 256; 1040 value = 256;
1007 break; 1041 break;
@@ -1013,7 +1047,7 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1013 value = 64; 1047 value = 64;
1014 break; 1048 break;
1015 } 1049 }
1016 switch (ch->u.ofdm.guard_interval) { 1050 switch (ch->guard_interval) {
1017 case GUARD_INTERVAL_1_16: 1051 case GUARD_INTERVAL_1_16:
1018 value *= 2; 1052 value *= 2;
1019 break; 1053 break;
@@ -1034,11 +1068,11 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1034 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; 1068 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
1035 1069
1036 /* deactive the possibility of diversity reception if extended interleaver */ 1070 /* deactive the possibility of diversity reception if extended interleaver */
1037 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K; 1071 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
1038 dib7000p_set_diversity_in(&state->demod, state->div_state); 1072 dib7000p_set_diversity_in(&state->demod, state->div_state);
1039 1073
1040 /* channel estimation fine configuration */ 1074 /* channel estimation fine configuration */
1041 switch (ch->u.ofdm.constellation) { 1075 switch (ch->modulation) {
1042 case QAM_64: 1076 case QAM_64:
1043 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 1077 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
1044 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 1078 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
@@ -1062,27 +1096,31 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
1062 dib7000p_write_word(state, 187 + value, est[value]); 1096 dib7000p_write_word(state, 187 + value, est[value]);
1063} 1097}
1064 1098
1065static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1099static int dib7000p_autosearch_start(struct dvb_frontend *demod)
1066{ 1100{
1101 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1067 struct dib7000p_state *state = demod->demodulator_priv; 1102 struct dib7000p_state *state = demod->demodulator_priv;
1068 struct dvb_frontend_parameters schan; 1103 struct dtv_frontend_properties schan;
1069 u32 value, factor; 1104 u32 value, factor;
1070 u32 internal = dib7000p_get_internal_freq(state); 1105 u32 internal = dib7000p_get_internal_freq(state);
1071 1106
1072 schan = *ch; 1107 schan = *ch;
1073 schan.u.ofdm.constellation = QAM_64; 1108 schan.modulation = QAM_64;
1074 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1109 schan.guard_interval = GUARD_INTERVAL_1_32;
1075 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1110 schan.transmission_mode = TRANSMISSION_MODE_8K;
1076 schan.u.ofdm.code_rate_HP = FEC_2_3; 1111 schan.code_rate_HP = FEC_2_3;
1077 schan.u.ofdm.code_rate_LP = FEC_3_4; 1112 schan.code_rate_LP = FEC_3_4;
1078 schan.u.ofdm.hierarchy_information = 0; 1113 schan.hierarchy = 0;
1079 1114
1080 dib7000p_set_channel(state, &schan, 7); 1115 dib7000p_set_channel(state, &schan, 7);
1081 1116
1082 factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth); 1117 factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
1083 if (factor >= 5000) 1118 if (factor >= 5000) {
1084 factor = 1; 1119 if (state->version == SOC7090)
1085 else 1120 factor = 2;
1121 else
1122 factor = 1;
1123 } else
1086 factor = 6; 1124 factor = 6;
1087 1125
1088 value = 30 * internal * factor; 1126 value = 30 * internal * factor;
@@ -1205,8 +1243,9 @@ static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32
1205 dib7000p_write_word(state, 143, 0); 1243 dib7000p_write_word(state, 143, 0);
1206} 1244}
1207 1245
1208static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1246static int dib7000p_tune(struct dvb_frontend *demod)
1209{ 1247{
1248 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1210 struct dib7000p_state *state = demod->demodulator_priv; 1249 struct dib7000p_state *state = demod->demodulator_priv;
1211 u16 tmp = 0; 1250 u16 tmp = 0;
1212 1251
@@ -1239,7 +1278,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1239 1278
1240 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1279 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1241 tmp = (6 << 8) | 0x80; 1280 tmp = (6 << 8) | 0x80;
1242 switch (ch->u.ofdm.transmission_mode) { 1281 switch (ch->transmission_mode) {
1243 case TRANSMISSION_MODE_2K: 1282 case TRANSMISSION_MODE_2K:
1244 tmp |= (2 << 12); 1283 tmp |= (2 << 12);
1245 break; 1284 break;
@@ -1255,7 +1294,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1255 1294
1256 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1295 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1257 tmp = (0 << 4); 1296 tmp = (0 << 4);
1258 switch (ch->u.ofdm.transmission_mode) { 1297 switch (ch->transmission_mode) {
1259 case TRANSMISSION_MODE_2K: 1298 case TRANSMISSION_MODE_2K:
1260 tmp |= 0x6; 1299 tmp |= 0x6;
1261 break; 1300 break;
@@ -1271,7 +1310,7 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1271 1310
1272 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1311 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1273 tmp = (0 << 4); 1312 tmp = (0 << 4);
1274 switch (ch->u.ofdm.transmission_mode) { 1313 switch (ch->transmission_mode) {
1275 case TRANSMISSION_MODE_2K: 1314 case TRANSMISSION_MODE_2K:
1276 tmp |= 0x6; 1315 tmp |= 0x6;
1277 break; 1316 break;
@@ -1303,9 +1342,9 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
1303 } 1342 }
1304 1343
1305 if (state->cfg.spur_protect) 1344 if (state->cfg.spur_protect)
1306 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1345 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1307 1346
1308 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1347 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1309 return 0; 1348 return 0;
1310} 1349}
1311 1350
@@ -1323,7 +1362,7 @@ static int dib7000p_sleep(struct dvb_frontend *demod)
1323{ 1362{
1324 struct dib7000p_state *state = demod->demodulator_priv; 1363 struct dib7000p_state *state = demod->demodulator_priv;
1325 if (state->version == SOC7090) 1364 if (state->version == SOC7090)
1326 return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1365 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1327 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1366 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1328} 1367}
1329 1368
@@ -1345,93 +1384,94 @@ static int dib7000p_identify(struct dib7000p_state *st)
1345 return 0; 1384 return 0;
1346} 1385}
1347 1386
1348static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1387static int dib7000p_get_frontend(struct dvb_frontend *fe)
1349{ 1388{
1389 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1350 struct dib7000p_state *state = fe->demodulator_priv; 1390 struct dib7000p_state *state = fe->demodulator_priv;
1351 u16 tps = dib7000p_read_word(state, 463); 1391 u16 tps = dib7000p_read_word(state, 463);
1352 1392
1353 fep->inversion = INVERSION_AUTO; 1393 fep->inversion = INVERSION_AUTO;
1354 1394
1355 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth); 1395 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1356 1396
1357 switch ((tps >> 8) & 0x3) { 1397 switch ((tps >> 8) & 0x3) {
1358 case 0: 1398 case 0:
1359 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 1399 fep->transmission_mode = TRANSMISSION_MODE_2K;
1360 break; 1400 break;
1361 case 1: 1401 case 1:
1362 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1402 fep->transmission_mode = TRANSMISSION_MODE_8K;
1363 break; 1403 break;
1364 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */ 1404 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1365 } 1405 }
1366 1406
1367 switch (tps & 0x3) { 1407 switch (tps & 0x3) {
1368 case 0: 1408 case 0:
1369 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1409 fep->guard_interval = GUARD_INTERVAL_1_32;
1370 break; 1410 break;
1371 case 1: 1411 case 1:
1372 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 1412 fep->guard_interval = GUARD_INTERVAL_1_16;
1373 break; 1413 break;
1374 case 2: 1414 case 2:
1375 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 1415 fep->guard_interval = GUARD_INTERVAL_1_8;
1376 break; 1416 break;
1377 case 3: 1417 case 3:
1378 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 1418 fep->guard_interval = GUARD_INTERVAL_1_4;
1379 break; 1419 break;
1380 } 1420 }
1381 1421
1382 switch ((tps >> 14) & 0x3) { 1422 switch ((tps >> 14) & 0x3) {
1383 case 0: 1423 case 0:
1384 fep->u.ofdm.constellation = QPSK; 1424 fep->modulation = QPSK;
1385 break; 1425 break;
1386 case 1: 1426 case 1:
1387 fep->u.ofdm.constellation = QAM_16; 1427 fep->modulation = QAM_16;
1388 break; 1428 break;
1389 case 2: 1429 case 2:
1390 default: 1430 default:
1391 fep->u.ofdm.constellation = QAM_64; 1431 fep->modulation = QAM_64;
1392 break; 1432 break;
1393 } 1433 }
1394 1434
1395 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1435 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1396 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ 1436 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1397 1437
1398 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 1438 fep->hierarchy = HIERARCHY_NONE;
1399 switch ((tps >> 5) & 0x7) { 1439 switch ((tps >> 5) & 0x7) {
1400 case 1: 1440 case 1:
1401 fep->u.ofdm.code_rate_HP = FEC_1_2; 1441 fep->code_rate_HP = FEC_1_2;
1402 break; 1442 break;
1403 case 2: 1443 case 2:
1404 fep->u.ofdm.code_rate_HP = FEC_2_3; 1444 fep->code_rate_HP = FEC_2_3;
1405 break; 1445 break;
1406 case 3: 1446 case 3:
1407 fep->u.ofdm.code_rate_HP = FEC_3_4; 1447 fep->code_rate_HP = FEC_3_4;
1408 break; 1448 break;
1409 case 5: 1449 case 5:
1410 fep->u.ofdm.code_rate_HP = FEC_5_6; 1450 fep->code_rate_HP = FEC_5_6;
1411 break; 1451 break;
1412 case 7: 1452 case 7:
1413 default: 1453 default:
1414 fep->u.ofdm.code_rate_HP = FEC_7_8; 1454 fep->code_rate_HP = FEC_7_8;
1415 break; 1455 break;
1416 1456
1417 } 1457 }
1418 1458
1419 switch ((tps >> 2) & 0x7) { 1459 switch ((tps >> 2) & 0x7) {
1420 case 1: 1460 case 1:
1421 fep->u.ofdm.code_rate_LP = FEC_1_2; 1461 fep->code_rate_LP = FEC_1_2;
1422 break; 1462 break;
1423 case 2: 1463 case 2:
1424 fep->u.ofdm.code_rate_LP = FEC_2_3; 1464 fep->code_rate_LP = FEC_2_3;
1425 break; 1465 break;
1426 case 3: 1466 case 3:
1427 fep->u.ofdm.code_rate_LP = FEC_3_4; 1467 fep->code_rate_LP = FEC_3_4;
1428 break; 1468 break;
1429 case 5: 1469 case 5:
1430 fep->u.ofdm.code_rate_LP = FEC_5_6; 1470 fep->code_rate_LP = FEC_5_6;
1431 break; 1471 break;
1432 case 7: 1472 case 7:
1433 default: 1473 default:
1434 fep->u.ofdm.code_rate_LP = FEC_7_8; 1474 fep->code_rate_LP = FEC_7_8;
1435 break; 1475 break;
1436 } 1476 }
1437 1477
@@ -1440,36 +1480,36 @@ static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_pa
1440 return 0; 1480 return 0;
1441} 1481}
1442 1482
1443static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1483static int dib7000p_set_frontend(struct dvb_frontend *fe)
1444{ 1484{
1485 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1445 struct dib7000p_state *state = fe->demodulator_priv; 1486 struct dib7000p_state *state = fe->demodulator_priv;
1446 int time, ret; 1487 int time, ret;
1447 1488
1448 if (state->version == SOC7090) { 1489 if (state->version == SOC7090)
1449 dib7090_set_diversity_in(fe, 0); 1490 dib7090_set_diversity_in(fe, 0);
1450 dib7090_set_output_mode(fe, OUTMODE_HIGH_Z); 1491 else
1451 } else
1452 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); 1492 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1453 1493
1454 /* maybe the parameter has been changed */ 1494 /* maybe the parameter has been changed */
1455 state->sfn_workaround_active = buggy_sfn_workaround; 1495 state->sfn_workaround_active = buggy_sfn_workaround;
1456 1496
1457 if (fe->ops.tuner_ops.set_params) 1497 if (fe->ops.tuner_ops.set_params)
1458 fe->ops.tuner_ops.set_params(fe, fep); 1498 fe->ops.tuner_ops.set_params(fe);
1459 1499
1460 /* start up the AGC */ 1500 /* start up the AGC */
1461 state->agc_state = 0; 1501 state->agc_state = 0;
1462 do { 1502 do {
1463 time = dib7000p_agc_startup(fe, fep); 1503 time = dib7000p_agc_startup(fe);
1464 if (time != -1) 1504 if (time != -1)
1465 msleep(time); 1505 msleep(time);
1466 } while (time != -1); 1506 } while (time != -1);
1467 1507
1468 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1508 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1469 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1509 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
1470 int i = 800, found; 1510 int i = 800, found;
1471 1511
1472 dib7000p_autosearch_start(fe, fep); 1512 dib7000p_autosearch_start(fe);
1473 do { 1513 do {
1474 msleep(1); 1514 msleep(1);
1475 found = dib7000p_autosearch_is_irq(fe); 1515 found = dib7000p_autosearch_is_irq(fe);
@@ -1479,15 +1519,19 @@ static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_pa
1479 if (found == 0 || found == 1) 1519 if (found == 0 || found == 1)
1480 return 0; 1520 return 0;
1481 1521
1482 dib7000p_get_frontend(fe, fep); 1522 dib7000p_get_frontend(fe);
1483 } 1523 }
1484 1524
1485 ret = dib7000p_tune(fe, fep); 1525 ret = dib7000p_tune(fe);
1486 1526
1487 /* make this a config parameter */ 1527 /* make this a config parameter */
1488 if (state->version == SOC7090) 1528 if (state->version == SOC7090) {
1489 dib7090_set_output_mode(fe, state->cfg.output_mode); 1529 dib7090_set_output_mode(fe, state->cfg.output_mode);
1490 else 1530 if (state->cfg.enMpegOutput == 0) {
1531 dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
1532 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1533 }
1534 } else
1491 dib7000p_set_output_mode(state, state->cfg.output_mode); 1535 dib7000p_set_output_mode(state, state->cfg.output_mode);
1492 1536
1493 return ret; 1537 return ret;
@@ -1831,7 +1875,8 @@ static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg m
1831 return num; 1875 return num;
1832} 1876}
1833 1877
1834int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address) 1878static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
1879 struct i2c_msg msg[], int num, u16 apb_address)
1835{ 1880{
1836 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 1881 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1837 u16 word; 1882 u16 word;
@@ -1933,10 +1978,10 @@ static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[]
1933 apb_address = 915; 1978 apb_address = 915;
1934 break; 1979 break;
1935 case 0x27: 1980 case 0x27:
1936 apb_address = 916; 1981 apb_address = 917;
1937 break; 1982 break;
1938 case 0x28: 1983 case 0x28:
1939 apb_address = 917; 1984 apb_address = 916;
1940 break; 1985 break;
1941 case 0x1d: 1986 case 0x1d:
1942 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3); 1987 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
@@ -2031,12 +2076,7 @@ static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32
2031 2076
2032static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize) 2077static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
2033{ 2078{
2034 u8 index_buf;
2035 u16 rx_copy_buf[22];
2036
2037 dprintk("Configure DibStream Tx"); 2079 dprintk("Configure DibStream Tx");
2038 for (index_buf = 0; index_buf < 22; index_buf++)
2039 rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
2040 2080
2041 dib7000p_write_word(state, 1615, 1); 2081 dib7000p_write_word(state, 1615, 1);
2042 dib7000p_write_word(state, 1603, P_Kin); 2082 dib7000p_write_word(state, 1603, P_Kin);
@@ -2048,9 +2088,6 @@ static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout
2048 dib7000p_write_word(state, 1612, syncSize); 2088 dib7000p_write_word(state, 1612, syncSize);
2049 dib7000p_write_word(state, 1615, 0); 2089 dib7000p_write_word(state, 1615, 0);
2050 2090
2051 for (index_buf = 0; index_buf < 22; index_buf++)
2052 dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
2053
2054 return 0; 2091 return 0;
2055} 2092}
2056 2093
@@ -2077,109 +2114,121 @@ static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout
2077 return 0; 2114 return 0;
2078} 2115}
2079 2116
2080static int dib7090_enDivOnHostBus(struct dib7000p_state *state) 2117static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
2081{
2082 u16 reg;
2083
2084 dprintk("Enable Diversity on host bus");
2085 reg = (1 << 8) | (1 << 5);
2086 dib7000p_write_word(state, 1288, reg);
2087
2088 return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2089}
2090
2091static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
2092{
2093 u16 reg;
2094
2095 dprintk("Enable ADC on host bus");
2096 reg = (1 << 7) | (1 << 5);
2097 dib7000p_write_word(state, 1288, reg);
2098
2099 return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2100}
2101
2102static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
2103{ 2118{
2104 u16 reg; 2119 u16 reg_1287 = dib7000p_read_word(state, 1287);
2105
2106 dprintk("Enable Mpeg on host bus");
2107 reg = (1 << 9) | (1 << 5);
2108 dib7000p_write_word(state, 1288, reg);
2109 2120
2110 return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); 2121 switch (onoff) {
2111} 2122 case 1:
2123 reg_1287 &= ~(1<<7);
2124 break;
2125 case 0:
2126 reg_1287 |= (1<<7);
2127 break;
2128 }
2112 2129
2113static int dib7090_enMpegInput(struct dib7000p_state *state) 2130 dib7000p_write_word(state, 1287, reg_1287);
2114{
2115 dprintk("Enable Mpeg input");
2116 return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2117} 2131}
2118 2132
2119static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2) 2133static void dib7090_configMpegMux(struct dib7000p_state *state,
2134 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2120{ 2135{
2121 u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
2122
2123 dprintk("Enable Mpeg mux"); 2136 dprintk("Enable Mpeg mux");
2124 dib7000p_write_word(state, 1287, reg);
2125 2137
2126 reg &= ~(1 << 7); 2138 dib7090_enMpegMux(state, 0);
2127 dib7000p_write_word(state, 1287, reg);
2128 2139
2129 reg = (1 << 4); 2140 /* If the input mode is MPEG do not divide the serial clock */
2130 dib7000p_write_word(state, 1288, reg); 2141 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
2142 enSerialClkDiv2 = 0;
2131 2143
2132 return 0; 2144 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
2145 | ((enSerialMode & 0x1) << 1)
2146 | (enSerialClkDiv2 & 0x1));
2147
2148 dib7090_enMpegMux(state, 1);
2133} 2149}
2134 2150
2135static int dib7090_disableMpegMux(struct dib7000p_state *state) 2151static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
2136{ 2152{
2137 u16 reg; 2153 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
2138
2139 dprintk("Disable Mpeg mux");
2140 dib7000p_write_word(state, 1288, 0);
2141
2142 reg = dib7000p_read_word(state, 1287);
2143 reg &= ~(1 << 7);
2144 dib7000p_write_word(state, 1287, reg);
2145 2154
2146 return 0; 2155 switch (mode) {
2156 case MPEG_ON_DIBTX:
2157 dprintk("SET MPEG ON DIBSTREAM TX");
2158 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2159 reg_1288 |= (1<<9);
2160 break;
2161 case DIV_ON_DIBTX:
2162 dprintk("SET DIV_OUT ON DIBSTREAM TX");
2163 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2164 reg_1288 |= (1<<8);
2165 break;
2166 case ADC_ON_DIBTX:
2167 dprintk("SET ADC_OUT ON DIBSTREAM TX");
2168 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2169 reg_1288 |= (1<<7);
2170 break;
2171 default:
2172 break;
2173 }
2174 dib7000p_write_word(state, 1288, reg_1288);
2147} 2175}
2148 2176
2149static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode) 2177static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
2150{ 2178{
2151 struct dib7000p_state *state = fe->demodulator_priv; 2179 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
2152 2180
2153 switch (mode) { 2181 switch (mode) {
2154 case INPUT_MODE_DIVERSITY: 2182 case DEMOUT_ON_HOSTBUS:
2155 dprintk("Enable diversity INPUT"); 2183 dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
2156 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); 2184 dib7090_enMpegMux(state, 0);
2185 reg_1288 |= (1<<6);
2186 break;
2187 case DIBTX_ON_HOSTBUS:
2188 dprintk("SET DIBSTREAM TX ON HOST BUS");
2189 dib7090_enMpegMux(state, 0);
2190 reg_1288 |= (1<<5);
2157 break; 2191 break;
2158 case INPUT_MODE_MPEG: 2192 case MPEG_ON_HOSTBUS:
2159 dprintk("Enable Mpeg INPUT"); 2193 dprintk("SET MPEG MUX ON HOST BUS");
2160 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */ 2194 reg_1288 |= (1<<4);
2161 break; 2195 break;
2162 case INPUT_MODE_OFF:
2163 default: 2196 default:
2164 dprintk("Disable INPUT");
2165 dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
2166 break; 2197 break;
2167 } 2198 }
2168 return 0; 2199 dib7000p_write_word(state, 1288, reg_1288);
2169} 2200}
2170 2201
2171static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff) 2202int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2172{ 2203{
2204 struct dib7000p_state *state = fe->demodulator_priv;
2205 u16 reg_1287;
2206
2173 switch (onoff) { 2207 switch (onoff) {
2174 case 0: /* only use the internal way - not the diversity input */ 2208 case 0: /* only use the internal way - not the diversity input */
2175 dib7090_set_input_mode(fe, INPUT_MODE_MPEG); 2209 dprintk("%s mode OFF : by default Enable Mpeg INPUT", __func__);
2176 break; 2210 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
2177 case 1: /* both ways */ 2211
2178 case 2: /* only the diversity input */ 2212 /* Do not divide the serial clock of MPEG MUX */
2179 dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY); 2213 /* in SERIAL MODE in case input mode MPEG is used */
2180 break; 2214 reg_1287 = dib7000p_read_word(state, 1287);
2215 /* enSerialClkDiv2 == 1 ? */
2216 if ((reg_1287 & 0x1) == 1) {
2217 /* force enSerialClkDiv2 = 0 */
2218 reg_1287 &= ~0x1;
2219 dib7000p_write_word(state, 1287, reg_1287);
2220 }
2221 state->input_mode_mpeg = 1;
2222 break;
2223 case 1: /* both ways */
2224 case 2: /* only the diversity input */
2225 dprintk("%s ON : Enable diversity INPUT", __func__);
2226 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2227 state->input_mode_mpeg = 0;
2228 break;
2181 } 2229 }
2182 2230
2231 dib7000p_set_diversity_in(&state->demod, onoff);
2183 return 0; 2232 return 0;
2184} 2233}
2185 2234
@@ -2204,69 +2253,63 @@ static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2204 2253
2205 case OUTMODE_MPEG2_SERIAL: 2254 case OUTMODE_MPEG2_SERIAL:
2206 if (prefer_mpeg_mux_use) { 2255 if (prefer_mpeg_mux_use) {
2207 dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux"); 2256 dprintk("setting output mode TS_SERIAL using Mpeg Mux");
2208 dib7090_enMpegOnHostBus(state); 2257 dib7090_configMpegMux(state, 3, 1, 1);
2209 dib7090_enMpegInput(state); 2258 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2210 if (state->cfg.enMpegOutput == 1) 2259 } else {/* Use Smooth block */
2211 dib7090_enMpegMux(state, 3, 1, 1); 2260 dprintk("setting output mode TS_SERIAL using Smooth bloc");
2212 2261 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2213 } else { /* Use Smooth block */ 2262 outreg |= (2<<6) | (0 << 1);
2214 dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
2215 dib7090_disableMpegMux(state);
2216 dib7000p_write_word(state, 1288, (1 << 6));
2217 outreg |= (2 << 6) | (0 << 1);
2218 } 2263 }
2219 break; 2264 break;
2220 2265
2221 case OUTMODE_MPEG2_PAR_GATED_CLK: 2266 case OUTMODE_MPEG2_PAR_GATED_CLK:
2222 if (prefer_mpeg_mux_use) { 2267 if (prefer_mpeg_mux_use) {
2223 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux"); 2268 dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2224 dib7090_enMpegOnHostBus(state); 2269 dib7090_configMpegMux(state, 2, 0, 0);
2225 dib7090_enMpegInput(state); 2270 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2226 if (state->cfg.enMpegOutput == 1) 2271 } else { /* Use Smooth block */
2227 dib7090_enMpegMux(state, 2, 0, 0); 2272 dprintk("setting output mode TS_PARALLEL_GATED using Smooth block");
2228 } else { /* Use Smooth block */ 2273 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2229 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block"); 2274 outreg |= (0<<6);
2230 dib7090_disableMpegMux(state);
2231 dib7000p_write_word(state, 1288, (1 << 6));
2232 outreg |= (0 << 6);
2233 } 2275 }
2234 break; 2276 break;
2235 2277
2236 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */ 2278 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
2237 dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block"); 2279 dprintk("setting output mode TS_PARALLEL_CONT using Smooth block");
2238 dib7090_disableMpegMux(state); 2280 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2239 dib7000p_write_word(state, 1288, (1 << 6)); 2281 outreg |= (1<<6);
2240 outreg |= (1 << 6);
2241 break; 2282 break;
2242 2283
2243 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */ 2284 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
2244 dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block"); 2285 dprintk("setting output mode TS_FIFO using Smooth block");
2245 dib7090_disableMpegMux(state); 2286 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2246 dib7000p_write_word(state, 1288, (1 << 6)); 2287 outreg |= (5<<6);
2247 outreg |= (5 << 6);
2248 smo_mode |= (3 << 1); 2288 smo_mode |= (3 << 1);
2249 fifo_threshold = 512; 2289 fifo_threshold = 512;
2250 break; 2290 break;
2251 2291
2252 case OUTMODE_DIVERSITY: 2292 case OUTMODE_DIVERSITY:
2253 dprintk("Sip 7090P setting output mode MODE_DIVERSITY"); 2293 dprintk("setting output mode MODE_DIVERSITY");
2254 dib7090_disableMpegMux(state); 2294 dib7090_setDibTxMux(state, DIV_ON_DIBTX);
2255 dib7090_enDivOnHostBus(state); 2295 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2256 break; 2296 break;
2257 2297
2258 case OUTMODE_ANALOG_ADC: 2298 case OUTMODE_ANALOG_ADC:
2259 dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC"); 2299 dprintk("setting output mode MODE_ANALOG_ADC");
2260 dib7090_enAdcOnHostBus(state); 2300 dib7090_setDibTxMux(state, ADC_ON_DIBTX);
2301 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2261 break; 2302 break;
2262 } 2303 }
2304 if (mode != OUTMODE_HIGH_Z)
2305 outreg |= (1 << 10);
2263 2306
2264 if (state->cfg.output_mpeg2_in_188_bytes) 2307 if (state->cfg.output_mpeg2_in_188_bytes)
2265 smo_mode |= (1 << 5); 2308 smo_mode |= (1 << 5);
2266 2309
2267 ret |= dib7000p_write_word(state, 235, smo_mode); 2310 ret |= dib7000p_write_word(state, 235, smo_mode);
2268 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 2311 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2269 ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */ 2312 ret |= dib7000p_write_word(state, 1286, outreg);
2270 2313
2271 return ret; 2314 return ret;
2272} 2315}
@@ -2296,13 +2339,6 @@ int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2296} 2339}
2297EXPORT_SYMBOL(dib7090_tuner_sleep); 2340EXPORT_SYMBOL(dib7090_tuner_sleep);
2298 2341
2299int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2300{
2301 dprintk("AGC restart callback: %d", restart);
2302 return 0;
2303}
2304EXPORT_SYMBOL(dib7090_agc_restart);
2305
2306int dib7090_get_adc_power(struct dvb_frontend *fe) 2342int dib7090_get_adc_power(struct dvb_frontend *fe)
2307{ 2343{
2308 return dib7000p_get_adc_power(fe); 2344 return dib7000p_get_adc_power(fe);
@@ -2391,9 +2427,9 @@ error:
2391EXPORT_SYMBOL(dib7000p_attach); 2427EXPORT_SYMBOL(dib7000p_attach);
2392 2428
2393static struct dvb_frontend_ops dib7000p_ops = { 2429static struct dvb_frontend_ops dib7000p_ops = {
2430 .delsys = { SYS_DVBT },
2394 .info = { 2431 .info = {
2395 .name = "DiBcom 7000PC", 2432 .name = "DiBcom 7000PC",
2396 .type = FE_OFDM,
2397 .frequency_min = 44250000, 2433 .frequency_min = 44250000,
2398 .frequency_max = 867250000, 2434 .frequency_max = 867250000,
2399 .frequency_stepsize = 62500, 2435 .frequency_stepsize = 62500,