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path: root/drivers/gpu/drm/radeon
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-rw-r--r--drivers/gpu/drm/radeon/atombios.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c197
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/nid.h2
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h8
-rw-r--r--drivers/gpu/drm/radeon/r600.c21
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c31
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c44
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c71
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c123
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c51
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c10
21 files changed, 438 insertions, 162 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 49611e2365d..1b50ad8919d 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -1200,6 +1200,7 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1200#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1200#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1201#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1201#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1202#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1202#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1203#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1203 1204
1204// ucConfig 1205// ucConfig
1205#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1206#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 84a69e7fa11..9541995e4b2 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -671,6 +671,13 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
671 DISPPLL_CONFIG_DUAL_LINK; 671 DISPPLL_CONFIG_DUAL_LINK;
672 } 672 }
673 } 673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
674 atom_execute_table(rdev->mode_info.atom_context, 681 atom_execute_table(rdev->mode_info.atom_context,
675 index, (uint32_t *)&args); 682 index, (uint32_t *)&args);
676 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 98ea597bc76..660f96401a0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -88,7 +88,8 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
88/* get temperature in millidegrees */ 88/* get temperature in millidegrees */
89int evergreen_get_temp(struct radeon_device *rdev) 89int evergreen_get_temp(struct radeon_device *rdev)
90{ 90{
91 u32 temp, toffset, actual_temp = 0; 91 u32 temp, toffset;
92 int actual_temp = 0;
92 93
93 if (rdev->family == CHIP_JUNIPER) { 94 if (rdev->family == CHIP_JUNIPER) {
94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 95 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
@@ -139,11 +140,17 @@ void evergreen_pm_misc(struct radeon_device *rdev)
139 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
140 141
141 if (voltage->type == VOLTAGE_SW) { 142 if (voltage->type == VOLTAGE_SW) {
143 /* 0xff01 is a flag rather then an actual voltage */
144 if (voltage->voltage == 0xff01)
145 return;
142 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 146 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
143 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 147 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
144 rdev->pm.current_vddc = voltage->voltage; 148 rdev->pm.current_vddc = voltage->voltage;
145 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 149 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
146 } 150 }
151 /* 0xff01 is a flag rather then an actual voltage */
152 if (voltage->vddci == 0xff01)
153 return;
147 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 154 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
148 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 155 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
149 rdev->pm.current_vddci = voltage->vddci; 156 rdev->pm.current_vddci = voltage->vddci;
@@ -978,17 +985,19 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
978{ 985{
979 save->vga_control[0] = RREG32(D1VGA_CONTROL); 986 save->vga_control[0] = RREG32(D1VGA_CONTROL);
980 save->vga_control[1] = RREG32(D2VGA_CONTROL); 987 save->vga_control[1] = RREG32(D2VGA_CONTROL);
981 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
982 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
983 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
984 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
985 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
986 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
987 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
988 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
989 if (!(rdev->flags & RADEON_IS_IGP)) { 992 if (rdev->num_crtc >= 4) {
993 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
994 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
990 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
991 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
997 }
998 if (rdev->num_crtc >= 6) {
999 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1000 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
992 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
993 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
994 } 1003 }
@@ -997,35 +1006,45 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
997 WREG32(VGA_RENDER_CONTROL, 0); 1006 WREG32(VGA_RENDER_CONTROL, 0);
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1000 if (!(rdev->flags & RADEON_IS_IGP)) { 1009 if (rdev->num_crtc >= 4) {
1001 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1002 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1012 }
1013 if (rdev->num_crtc >= 6) {
1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1005 } 1016 }
1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1007 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1008 if (!(rdev->flags & RADEON_IS_IGP)) { 1019 if (rdev->num_crtc >= 4) {
1009 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1010 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1021 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1022 }
1023 if (rdev->num_crtc >= 6) {
1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013 } 1026 }
1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1016 if (!(rdev->flags & RADEON_IS_IGP)) { 1029 if (rdev->num_crtc >= 4) {
1017 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1018 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1032 }
1033 if (rdev->num_crtc >= 6) {
1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1021 } 1036 }
1022 1037
1023 WREG32(D1VGA_CONTROL, 0); 1038 WREG32(D1VGA_CONTROL, 0);
1024 WREG32(D2VGA_CONTROL, 0); 1039 WREG32(D2VGA_CONTROL, 0);
1025 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1040 if (rdev->num_crtc >= 4) {
1026 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1041 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1027 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1042 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1028 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1043 }
1044 if (rdev->num_crtc >= 6) {
1045 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1046 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1047 }
1029} 1048}
1030 1049
1031void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1050void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1048,7 +1067,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start); 1068 (u32)rdev->mc.vram_start);
1050 1069
1051 if (!(rdev->flags & RADEON_IS_IGP)) { 1070 if (rdev->num_crtc >= 4) {
1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1053 upper_32_bits(rdev->mc.vram_start)); 1072 upper_32_bits(rdev->mc.vram_start));
1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
@@ -1066,7 +1085,8 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1066 (u32)rdev->mc.vram_start); 1085 (u32)rdev->mc.vram_start);
1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1068 (u32)rdev->mc.vram_start); 1087 (u32)rdev->mc.vram_start);
1069 1088 }
1089 if (rdev->num_crtc >= 6) {
1070 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1071 upper_32_bits(rdev->mc.vram_start)); 1091 upper_32_bits(rdev->mc.vram_start));
1072 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
@@ -1094,31 +1114,41 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1094 /* Restore video state */ 1114 /* Restore video state */
1095 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1115 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1096 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1116 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1097 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1117 if (rdev->num_crtc >= 4) {
1098 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1118 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1099 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1119 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1100 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1120 }
1121 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1123 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1124 }
1101 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1103 if (!(rdev->flags & RADEON_IS_IGP)) { 1127 if (rdev->num_crtc >= 4) {
1104 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1105 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1130 }
1131 if (rdev->num_crtc >= 6) {
1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1108 } 1134 }
1109 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1110 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1111 if (!(rdev->flags & RADEON_IS_IGP)) { 1137 if (rdev->num_crtc >= 4) {
1112 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1113 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1140 }
1141 if (rdev->num_crtc >= 6) {
1114 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1115 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1116 } 1144 }
1117 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1119 if (!(rdev->flags & RADEON_IS_IGP)) { 1147 if (rdev->num_crtc >= 4) {
1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1150 }
1151 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1123 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1124 } 1154 }
@@ -2006,9 +2036,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2006 rdev->config.evergreen.tile_config |= (3 << 0); 2036 rdev->config.evergreen.tile_config |= (3 << 0);
2007 break; 2037 break;
2008 } 2038 }
2009 /* num banks is 8 on all fusion asics */ 2039 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2010 if (rdev->flags & RADEON_IS_IGP) 2040 if (rdev->flags & RADEON_IS_IGP)
2011 rdev->config.evergreen.tile_config |= 8 << 4; 2041 rdev->config.evergreen.tile_config |= 1 << 4;
2012 else 2042 else
2013 rdev->config.evergreen.tile_config |= 2043 rdev->config.evergreen.tile_config |=
2014 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 2044 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
@@ -2241,7 +2271,10 @@ int evergreen_mc_init(struct radeon_device *rdev)
2241 2271
2242 /* Get VRAM informations */ 2272 /* Get VRAM informations */
2243 rdev->mc.vram_is_ddr = true; 2273 rdev->mc.vram_is_ddr = true;
2244 tmp = RREG32(MC_ARB_RAMCFG); 2274 if (rdev->flags & RADEON_IS_IGP)
2275 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2276 else
2277 tmp = RREG32(MC_ARB_RAMCFG);
2245 if (tmp & CHANSIZE_OVERRIDE) { 2278 if (tmp & CHANSIZE_OVERRIDE) {
2246 chansize = 16; 2279 chansize = 16;
2247 } else if (tmp & CHANSIZE_MASK) { 2280 } else if (tmp & CHANSIZE_MASK) {
@@ -2407,18 +2440,22 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2407 WREG32(GRBM_INT_CNTL, 0); 2440 WREG32(GRBM_INT_CNTL, 0);
2408 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2409 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2410 if (!(rdev->flags & RADEON_IS_IGP)) { 2443 if (rdev->num_crtc >= 4) {
2411 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2412 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2446 }
2447 if (rdev->num_crtc >= 6) {
2413 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2448 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2414 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2449 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2415 } 2450 }
2416 2451
2417 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2418 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2419 if (!(rdev->flags & RADEON_IS_IGP)) { 2454 if (rdev->num_crtc >= 4) {
2420 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2421 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2456 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2457 }
2458 if (rdev->num_crtc >= 6) {
2422 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2459 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2423 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2460 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2424 } 2461 }
@@ -2537,19 +2574,25 @@ int evergreen_irq_set(struct radeon_device *rdev)
2537 2574
2538 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2575 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2539 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2576 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2540 if (!(rdev->flags & RADEON_IS_IGP)) { 2577 if (rdev->num_crtc >= 4) {
2541 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2578 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2542 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2579 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2580 }
2581 if (rdev->num_crtc >= 6) {
2543 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2582 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2544 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2583 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2545 } 2584 }
2546 2585
2547 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2586 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2549 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2588 if (rdev->num_crtc >= 4) {
2550 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2589 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2551 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2590 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2591 }
2592 if (rdev->num_crtc >= 6) {
2593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2595 }
2553 2596
2554 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2597 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2555 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2598 WREG32(DC_HPD2_INT_CONTROL, hpd2);
@@ -2573,53 +2616,57 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
2573 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2616 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2574 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2617 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2575 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2618 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2576 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2619 if (rdev->num_crtc >= 4) {
2577 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2620 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2578 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2621 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2579 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2622 }
2623 if (rdev->num_crtc >= 6) {
2624 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2625 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2626 }
2580 2627
2581 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2628 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2582 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2583 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2630 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2584 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2585 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2586 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2587 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2588 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2589 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2590 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2591 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2592 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2593
2594 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2632 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2595 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2596 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2634 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2597 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2598
2599 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2600 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2601 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2602 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2603 2640
2604 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2641 if (rdev->num_crtc >= 4) {
2605 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2642 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2643 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2607 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2644 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2608 2645 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2609 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2610 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2647 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2611 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2612 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2649 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2613 2650 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2614 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2651 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2615 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2616 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2653 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2617 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2654 }
2618 2655
2619 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2656 if (rdev->num_crtc >= 6) {
2620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2657 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2621 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2622 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2659 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2661 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2669 }
2623 2670
2624 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2671 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2625 tmp = RREG32(DC_HPD1_INT_CONTROL); 2672 tmp = RREG32(DC_HPD1_INT_CONTROL);
@@ -2694,28 +2741,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2694 2741
2695int evergreen_irq_process(struct radeon_device *rdev) 2742int evergreen_irq_process(struct radeon_device *rdev)
2696{ 2743{
2697 u32 wptr = evergreen_get_ih_wptr(rdev); 2744 u32 wptr;
2698 u32 rptr = rdev->ih.rptr; 2745 u32 rptr;
2699 u32 src_id, src_data; 2746 u32 src_id, src_data;
2700 u32 ring_index; 2747 u32 ring_index;
2701 unsigned long flags; 2748 unsigned long flags;
2702 bool queue_hotplug = false; 2749 bool queue_hotplug = false;
2703 2750
2704 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2751 if (!rdev->ih.enabled || rdev->shutdown)
2705 if (!rdev->ih.enabled)
2706 return IRQ_NONE; 2752 return IRQ_NONE;
2707 2753
2708 spin_lock_irqsave(&rdev->ih.lock, flags); 2754 wptr = evergreen_get_ih_wptr(rdev);
2755 rptr = rdev->ih.rptr;
2756 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2709 2757
2758 spin_lock_irqsave(&rdev->ih.lock, flags);
2710 if (rptr == wptr) { 2759 if (rptr == wptr) {
2711 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2760 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2712 return IRQ_NONE; 2761 return IRQ_NONE;
2713 } 2762 }
2714 if (rdev->shutdown) {
2715 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2716 return IRQ_NONE;
2717 }
2718
2719restart_ih: 2763restart_ih:
2720 /* display interrupts */ 2764 /* display interrupts */
2721 evergreen_irq_ack(rdev); 2765 evergreen_irq_ack(rdev);
@@ -2944,7 +2988,7 @@ restart_ih:
2944 radeon_fence_process(rdev); 2988 radeon_fence_process(rdev);
2945 break; 2989 break;
2946 case 233: /* GUI IDLE */ 2990 case 233: /* GUI IDLE */
2947 DRM_DEBUG("IH: CP EOP\n"); 2991 DRM_DEBUG("IH: GUI idle\n");
2948 rdev->pm.gui_idle = true; 2992 rdev->pm.gui_idle = true;
2949 wake_up(&rdev->irq.idle_queue); 2993 wake_up(&rdev->irq.idle_queue);
2950 break; 2994 break;
@@ -3230,6 +3274,7 @@ void evergreen_fini(struct radeon_device *rdev)
3230 r700_cp_fini(rdev); 3274 r700_cp_fini(rdev);
3231 r600_irq_fini(rdev); 3275 r600_irq_fini(rdev);
3232 radeon_wb_fini(rdev); 3276 radeon_wb_fini(rdev);
3277 radeon_ib_pool_fini(rdev);
3233 radeon_irq_kms_fini(rdev); 3278 radeon_irq_kms_fini(rdev);
3234 evergreen_pcie_gart_fini(rdev); 3279 evergreen_pcie_gart_fini(rdev);
3235 radeon_gem_fini(rdev); 3280 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 1636e344982..b7b2714f0b3 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -466,7 +466,7 @@
466#define IH_RB_WPTR_ADDR_LO 0x3e14 466#define IH_RB_WPTR_ADDR_LO 0x3e14
467#define IH_CNTL 0x3e18 467#define IH_CNTL 0x3e18
468# define ENABLE_INTR (1 << 0) 468# define ENABLE_INTR (1 << 0)
469# define IH_MC_SWAP(x) ((x) << 2) 469# define IH_MC_SWAP(x) ((x) << 1)
470# define IH_MC_SWAP_NONE 0 470# define IH_MC_SWAP_NONE 0
471# define IH_MC_SWAP_16BIT 1 471# define IH_MC_SWAP_16BIT 1
472# define IH_MC_SWAP_32BIT 2 472# define IH_MC_SWAP_32BIT 2
@@ -547,7 +547,7 @@
547# define LB_D5_VBLANK_INTERRUPT (1 << 3) 547# define LB_D5_VBLANK_INTERRUPT (1 << 3)
548# define DC_HPD5_INTERRUPT (1 << 17) 548# define DC_HPD5_INTERRUPT (1 << 17)
549# define DC_HPD5_RX_INTERRUPT (1 << 18) 549# define DC_HPD5_RX_INTERRUPT (1 << 18)
550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
551# define LB_D6_VLINE_INTERRUPT (1 << 2) 551# define LB_D6_VLINE_INTERRUPT (1 << 2)
552# define LB_D6_VBLANK_INTERRUPT (1 << 3) 552# define LB_D6_VBLANK_INTERRUPT (1 << 3)
553# define DC_HPD6_INTERRUPT (1 << 17) 553# define DC_HPD6_INTERRUPT (1 << 17)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 16caafeadf5..559dbd41290 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1581,6 +1581,7 @@ void cayman_fini(struct radeon_device *rdev)
1581 cayman_cp_fini(rdev); 1581 cayman_cp_fini(rdev);
1582 r600_irq_fini(rdev); 1582 r600_irq_fini(rdev);
1583 radeon_wb_fini(rdev); 1583 radeon_wb_fini(rdev);
1584 radeon_ib_pool_fini(rdev);
1584 radeon_irq_kms_fini(rdev); 1585 radeon_irq_kms_fini(rdev);
1585 cayman_pcie_gart_fini(rdev); 1586 cayman_pcie_gart_fini(rdev);
1586 radeon_gem_fini(rdev); 1587 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 9736746da2d..4672869cdb2 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -320,7 +320,7 @@
320#define CGTS_USER_TCC_DISABLE 0x914C 320#define CGTS_USER_TCC_DISABLE 0x914C
321#define TCC_DISABLE_MASK 0xFFFF0000 321#define TCC_DISABLE_MASK 0xFFFF0000
322#define TCC_DISABLE_SHIFT 16 322#define TCC_DISABLE_SHIFT 16
323#define CGTS_SM_CTRL_REG 0x915C 323#define CGTS_SM_CTRL_REG 0x9150
324#define OVERRIDE (1 << 21) 324#define OVERRIDE (1 << 21)
325 325
326#define TA_CNTL_AUX 0x9508 326#define TA_CNTL_AUX 0x9508
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 2fef9de7f36..686f9dc5d4b 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -63,7 +63,7 @@ struct r100_cs_track {
63 unsigned num_arrays; 63 unsigned num_arrays;
64 unsigned max_indx; 64 unsigned max_indx;
65 unsigned color_channel_mask; 65 unsigned color_channel_mask;
66 struct r100_cs_track_array arrays[11]; 66 struct r100_cs_track_array arrays[16];
67 struct r100_cs_track_cb cb[R300_MAX_CB]; 67 struct r100_cs_track_cb cb[R300_MAX_CB];
68 struct r100_cs_track_cb zb; 68 struct r100_cs_track_cb zb;
69 struct r100_cs_track_cb aa; 69 struct r100_cs_track_cb aa;
@@ -146,6 +146,12 @@ static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
146 ib = p->ib->ptr; 146 ib = p->ib->ptr;
147 track = (struct r100_cs_track *)p->track; 147 track = (struct r100_cs_track *)p->track;
148 c = radeon_get_ib_value(p, idx++) & 0x1F; 148 c = radeon_get_ib_value(p, idx++) & 0x1F;
149 if (c > 16) {
150 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
151 pkt->opcode);
152 r100_cs_dump_packet(p, pkt);
153 return -EINVAL;
154 }
149 track->num_arrays = c; 155 track->num_arrays = c;
150 for (i = 0; i < (c - 1); i+=2, idx+=3) { 156 for (i = 0; i < (c - 1); i+=2, idx+=3) {
151 r = r100_cs_packet_next_reloc(p, &reloc); 157 r = r100_cs_packet_next_reloc(p, &reloc);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d74d4d71437..bc54b26cb32 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -590,6 +590,9 @@ void r600_pm_misc(struct radeon_device *rdev)
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591 591
592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
593 if (voltage->voltage != rdev->pm.current_vddc) { 596 if (voltage->voltage != rdev->pm.current_vddc) {
594 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
595 rdev->pm.current_vddc = voltage->voltage; 598 rdev->pm.current_vddc = voltage->voltage;
@@ -2625,6 +2628,7 @@ void r600_fini(struct radeon_device *rdev)
2625 r600_cp_fini(rdev); 2628 r600_cp_fini(rdev);
2626 r600_irq_fini(rdev); 2629 r600_irq_fini(rdev);
2627 radeon_wb_fini(rdev); 2630 radeon_wb_fini(rdev);
2631 radeon_ib_pool_fini(rdev);
2628 radeon_irq_kms_fini(rdev); 2632 radeon_irq_kms_fini(rdev);
2629 r600_pcie_gart_fini(rdev); 2633 r600_pcie_gart_fini(rdev);
2630 radeon_agp_fini(rdev); 2634 radeon_agp_fini(rdev);
@@ -3294,27 +3298,26 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3294 3298
3295int r600_irq_process(struct radeon_device *rdev) 3299int r600_irq_process(struct radeon_device *rdev)
3296{ 3300{
3297 u32 wptr = r600_get_ih_wptr(rdev); 3301 u32 wptr;
3298 u32 rptr = rdev->ih.rptr; 3302 u32 rptr;
3299 u32 src_id, src_data; 3303 u32 src_id, src_data;
3300 u32 ring_index; 3304 u32 ring_index;
3301 unsigned long flags; 3305 unsigned long flags;
3302 bool queue_hotplug = false; 3306 bool queue_hotplug = false;
3303 3307
3304 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3308 if (!rdev->ih.enabled || rdev->shutdown)
3305 if (!rdev->ih.enabled)
3306 return IRQ_NONE; 3309 return IRQ_NONE;
3307 3310
3311 wptr = r600_get_ih_wptr(rdev);
3312 rptr = rdev->ih.rptr;
3313 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3314
3308 spin_lock_irqsave(&rdev->ih.lock, flags); 3315 spin_lock_irqsave(&rdev->ih.lock, flags);
3309 3316
3310 if (rptr == wptr) { 3317 if (rptr == wptr) {
3311 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3318 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3312 return IRQ_NONE; 3319 return IRQ_NONE;
3313 } 3320 }
3314 if (rdev->shutdown) {
3315 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3316 return IRQ_NONE;
3317 }
3318 3321
3319restart_ih: 3322restart_ih:
3320 /* display interrupts */ 3323 /* display interrupts */
@@ -3444,7 +3447,7 @@ restart_ih:
3444 radeon_fence_process(rdev); 3447 radeon_fence_process(rdev);
3445 break; 3448 break;
3446 case 233: /* GUI IDLE */ 3449 case 233: /* GUI IDLE */
3447 DRM_DEBUG("IH: CP EOP\n"); 3450 DRM_DEBUG("IH: GUI idle\n");
3448 rdev->pm.gui_idle = true; 3451 rdev->pm.gui_idle = true;
3449 wake_up(&rdev->irq.idle_queue); 3452 wake_up(&rdev->irq.idle_queue);
3450 break; 3453 break;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index f140a0d5cb5..0245ae6c204 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -536,7 +536,7 @@
536#define IH_RB_WPTR_ADDR_LO 0x3e14 536#define IH_RB_WPTR_ADDR_LO 0x3e14
537#define IH_CNTL 0x3e18 537#define IH_CNTL 0x3e18
538# define ENABLE_INTR (1 << 0) 538# define ENABLE_INTR (1 << 0)
539# define IH_MC_SWAP(x) ((x) << 2) 539# define IH_MC_SWAP(x) ((x) << 1)
540# define IH_MC_SWAP_NONE 0 540# define IH_MC_SWAP_NONE 0
541# define IH_MC_SWAP_16BIT 1 541# define IH_MC_SWAP_16BIT 1
542# define IH_MC_SWAP_32BIT 2 542# define IH_MC_SWAP_32BIT 2
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ba643b57605..ef0e0e01691 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -165,6 +165,7 @@ struct radeon_clock {
165 uint32_t default_sclk; 165 uint32_t default_sclk;
166 uint32_t default_dispclk; 166 uint32_t default_dispclk;
167 uint32_t dp_extclk; 167 uint32_t dp_extclk;
168 uint32_t max_pixel_clock;
168}; 169};
169 170
170/* 171/*
@@ -178,6 +179,7 @@ void radeon_pm_resume(struct radeon_device *rdev);
178void radeon_combios_get_power_modes(struct radeon_device *rdev); 179void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev); 180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
181void rs690_pm_info(struct radeon_device *rdev); 183void rs690_pm_info(struct radeon_device *rdev);
182extern int rv6xx_get_temp(struct radeon_device *rdev); 184extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev); 185extern int rv770_get_temp(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 9bd162fc9b0..b2449629537 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -938,6 +938,13 @@ static struct radeon_asic cayman_asic = {
938int radeon_asic_init(struct radeon_device *rdev) 938int radeon_asic_init(struct radeon_device *rdev)
939{ 939{
940 radeon_register_accessor_init(rdev); 940 radeon_register_accessor_init(rdev);
941
942 /* set the number of crtcs */
943 if (rdev->flags & RADEON_SINGLE_CRTC)
944 rdev->num_crtc = 1;
945 else
946 rdev->num_crtc = 2;
947
941 switch (rdev->family) { 948 switch (rdev->family) {
942 case CHIP_R100: 949 case CHIP_R100:
943 case CHIP_RV100: 950 case CHIP_RV100:
@@ -1017,6 +1024,11 @@ int radeon_asic_init(struct radeon_device *rdev)
1017 case CHIP_JUNIPER: 1024 case CHIP_JUNIPER:
1018 case CHIP_CYPRESS: 1025 case CHIP_CYPRESS:
1019 case CHIP_HEMLOCK: 1026 case CHIP_HEMLOCK:
1027 /* set num crtcs */
1028 if (rdev->family == CHIP_CEDAR)
1029 rdev->num_crtc = 4;
1030 else
1031 rdev->num_crtc = 6;
1020 rdev->asic = &evergreen_asic; 1032 rdev->asic = &evergreen_asic;
1021 break; 1033 break;
1022 case CHIP_PALM: 1034 case CHIP_PALM:
@@ -1027,10 +1039,17 @@ int radeon_asic_init(struct radeon_device *rdev)
1027 case CHIP_BARTS: 1039 case CHIP_BARTS:
1028 case CHIP_TURKS: 1040 case CHIP_TURKS:
1029 case CHIP_CAICOS: 1041 case CHIP_CAICOS:
1042 /* set num crtcs */
1043 if (rdev->family == CHIP_CAICOS)
1044 rdev->num_crtc = 4;
1045 else
1046 rdev->num_crtc = 6;
1030 rdev->asic = &btc_asic; 1047 rdev->asic = &btc_asic;
1031 break; 1048 break;
1032 case CHIP_CAYMAN: 1049 case CHIP_CAYMAN:
1033 rdev->asic = &cayman_asic; 1050 rdev->asic = &cayman_asic;
1051 /* set num crtcs */
1052 rdev->num_crtc = 6;
1034 break; 1053 break;
1035 default: 1054 default:
1036 /* FIXME: not supported yet */ 1055 /* FIXME: not supported yet */
@@ -1042,18 +1061,6 @@ int radeon_asic_init(struct radeon_device *rdev)
1042 rdev->asic->set_memory_clock = NULL; 1061 rdev->asic->set_memory_clock = NULL;
1043 } 1062 }
1044 1063
1045 /* set the number of crtcs */
1046 if (rdev->flags & RADEON_SINGLE_CRTC)
1047 rdev->num_crtc = 1;
1048 else {
1049 if (ASIC_IS_DCE41(rdev))
1050 rdev->num_crtc = 2;
1051 else if (ASIC_IS_DCE4(rdev))
1052 rdev->num_crtc = 6;
1053 else
1054 rdev->num_crtc = 2;
1055 }
1056
1057 return 0; 1064 return 0;
1058} 1065}
1059 1066
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 90dfb2b8cf0..bf2b61584cd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1246,6 +1246,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1246 } 1246 }
1247 *dcpll = *p1pll; 1247 *dcpll = *p1pll;
1248 1248
1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
1249 return true; 1253 return true;
1250 } 1254 }
1251 1255
@@ -2316,6 +2320,14 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2316 le16_to_cpu(clock_info->r600.usVDDC); 2320 le16_to_cpu(clock_info->r600.usVDDC);
2317 } 2321 }
2318 2322
2323 /* patch up vddc if necessary */
2324 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2325 u16 vddc;
2326
2327 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2329 }
2330
2319 if (rdev->flags & RADEON_IS_IGP) { 2331 if (rdev->flags & RADEON_IS_IGP) {
2320 /* skip invalid modes */ 2332 /* skip invalid modes */
2321 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2333 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
@@ -2603,6 +2615,10 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2603 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2615 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2604 return; 2616 return;
2605 2617
2618 /* 0xff01 is a flag rather then an actual voltage */
2619 if (voltage_level == 0xff01)
2620 return;
2621
2606 switch (crev) { 2622 switch (crev) {
2607 case 1: 2623 case 1:
2608 args.v1.ucVoltageType = voltage_type; 2624 args.v1.ucVoltageType = voltage_type;
@@ -2622,7 +2638,35 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2623} 2639}
2624 2640
2641int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2642 u16 *voltage)
2643{
2644 union set_voltage args;
2645 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2646 u8 frev, crev;
2647
2648 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2649 return -EINVAL;
2625 2650
2651 switch (crev) {
2652 case 1:
2653 return -EINVAL;
2654 case 2:
2655 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2656 args.v2.ucVoltageMode = 0;
2657 args.v2.usVoltageLevel = 0;
2658
2659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2660
2661 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2662 break;
2663 default:
2664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669}
2626 2670
2627void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 2671void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2628{ 2672{
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 1aba85cad1a..3fc5fa1aefd 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -104,7 +104,7 @@ static bool radeon_read_bios(struct radeon_device *rdev)
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 105{
106 int ret; 106 int ret;
107 int size = 64 * 1024; 107 int size = 256 * 1024;
108 int i; 108 int i;
109 109
110 if (!radeon_atrm_supported(rdev->pdev)) 110 if (!radeon_atrm_supported(rdev->pdev))
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 5249af8931e..2d48e7a1474 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -117,7 +117,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2) 118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12; 119 p1pll->reference_div = 12;
120 p2pll->reference_div = p1pll->reference_div; 120 p2pll->reference_div = p1pll->reference_div;
121 121
122 /* These aren't in the device-tree */ 122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) { 123 if (rdev->family >= CHIP_R420) {
@@ -139,6 +139,8 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
139 p2pll->pll_out_min = 12500; 139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000; 140 p2pll->pll_out_max = 35000;
141 } 141 }
142 /* not sure what the max should be in all cases */
143 rdev->clock.max_pixel_clock = 35000;
142 144
143 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; 145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
144 spll->reference_div = mpll->reference_div = 146 spll->reference_div = mpll->reference_div =
@@ -151,7 +153,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
151 else 153 else
152 rdev->clock.default_sclk = 154 rdev->clock.default_sclk =
153 radeon_legacy_get_engine_clock(rdev); 155 radeon_legacy_get_engine_clock(rdev);
154 156
155 val = of_get_property(dp, "ATY,MCLK", NULL); 157 val = of_get_property(dp, "ATY,MCLK", NULL);
156 if (val && *val) 158 if (val && *val)
157 rdev->clock.default_mclk = (*val) / 10; 159 rdev->clock.default_mclk = (*val) / 10;
@@ -160,7 +162,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
160 radeon_legacy_get_memory_clock(rdev); 162 radeon_legacy_get_memory_clock(rdev);
161 163
162 DRM_INFO("Using device-tree clock info\n"); 164 DRM_INFO("Using device-tree clock info\n");
163 165
164 return true; 166 return true;
165} 167}
166#else 168#else
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 5b991f7c6e2..e4594676a07 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -866,6 +866,11 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
866 rdev->clock.default_sclk = sclk; 866 rdev->clock.default_sclk = sclk;
867 rdev->clock.default_mclk = mclk; 867 rdev->clock.default_mclk = mclk;
868 868
869 if (RBIOS32(pll_info + 0x16))
870 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
871 else
872 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
873
869 return true; 874 return true;
870 } 875 }
871 return false; 876 return false;
@@ -1548,10 +1553,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1548 (rdev->pdev->subsystem_device == 0x4a48)) { 1553 (rdev->pdev->subsystem_device == 0x4a48)) {
1549 /* Mac X800 */ 1554 /* Mac X800 */
1550 rdev->mode_info.connector_table = CT_MAC_X800; 1555 rdev->mode_info.connector_table = CT_MAC_X800;
1551 } else if ((rdev->pdev->device == 0x4150) && 1556 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1557 of_machine_is_compatible("PowerMac7,3")) &&
1558 (rdev->pdev->device == 0x4150) &&
1552 (rdev->pdev->subsystem_vendor == 0x1002) && 1559 (rdev->pdev->subsystem_vendor == 0x1002) &&
1553 (rdev->pdev->subsystem_device == 0x4150)) { 1560 (rdev->pdev->subsystem_device == 0x4150)) {
1554 /* Mac G5 9600 */ 1561 /* Mac G5 tower 9600 */
1555 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1562 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1556 } else 1563 } else
1557#endif /* CONFIG_PPC_PMAC */ 1564#endif /* CONFIG_PPC_PMAC */
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index ee1dccb3fec..cbfca3a24fd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -44,6 +44,8 @@ extern void
44radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 44radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
45 struct drm_connector *drm_connector); 45 struct drm_connector *drm_connector);
46 46
47bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
48
47void radeon_connector_hotplug(struct drm_connector *connector) 49void radeon_connector_hotplug(struct drm_connector *connector)
48{ 50{
49 struct drm_device *dev = connector->dev; 51 struct drm_device *dev = connector->dev;
@@ -626,8 +628,14 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
626static int radeon_vga_mode_valid(struct drm_connector *connector, 628static int radeon_vga_mode_valid(struct drm_connector *connector,
627 struct drm_display_mode *mode) 629 struct drm_display_mode *mode)
628{ 630{
631 struct drm_device *dev = connector->dev;
632 struct radeon_device *rdev = dev->dev_private;
633
629 /* XXX check mode bandwidth */ 634 /* XXX check mode bandwidth */
630 /* XXX verify against max DAC output frequency */ 635
636 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
637 return MODE_CLOCK_HIGH;
638
631 return MODE_OK; 639 return MODE_OK;
632} 640}
633 641
@@ -830,6 +838,13 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
830 if (!radeon_connector->edid) { 838 if (!radeon_connector->edid) {
831 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 839 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
832 drm_get_connector_name(connector)); 840 drm_get_connector_name(connector));
841 /* rs690 seems to have a problem with connectors not existing and always
842 * return a block of 0's. If we see this just stop polling on this output */
843 if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) && radeon_connector->base.null_edid_counter) {
844 ret = connector_status_disconnected;
845 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector));
846 radeon_connector->ddc_bus = NULL;
847 }
833 } else { 848 } else {
834 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 849 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
835 850
@@ -1015,6 +1030,11 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
1015 } else 1030 } else
1016 return MODE_CLOCK_HIGH; 1031 return MODE_CLOCK_HIGH;
1017 } 1032 }
1033
1034 /* check against the max pixel clock */
1035 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1036 return MODE_CLOCK_HIGH;
1037
1018 return MODE_OK; 1038 return MODE_OK;
1019} 1039}
1020 1040
@@ -1052,10 +1072,11 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1052{ 1072{
1053 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1073 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1054 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1074 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1075 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1055 int ret; 1076 int ret;
1056 1077
1057 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1078 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1058 struct drm_encoder *encoder; 1079 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1059 struct drm_display_mode *mode; 1080 struct drm_display_mode *mode;
1060 1081
1061 if (!radeon_dig_connector->edp_on) 1082 if (!radeon_dig_connector->edp_on)
@@ -1067,7 +1088,6 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1067 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1088 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1068 1089
1069 if (ret > 0) { 1090 if (ret > 0) {
1070 encoder = radeon_best_single_encoder(connector);
1071 if (encoder) { 1091 if (encoder) {
1072 radeon_fixup_lvds_native_mode(encoder, connector); 1092 radeon_fixup_lvds_native_mode(encoder, connector);
1073 /* add scaled modes */ 1093 /* add scaled modes */
@@ -1091,8 +1111,14 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1091 /* add scaled modes */ 1111 /* add scaled modes */
1092 radeon_add_common_modes(encoder, connector); 1112 radeon_add_common_modes(encoder, connector);
1093 } 1113 }
1094 } else 1114 } else {
1115 /* need to setup ddc on the bridge */
1116 if (radeon_connector_encoder_is_dp_bridge(connector)) {
1117 if (encoder)
1118 radeon_atom_ext_encoder_setup_ddc(encoder);
1119 }
1095 ret = radeon_ddc_get_modes(radeon_connector); 1120 ret = radeon_ddc_get_modes(radeon_connector);
1121 }
1096 1122
1097 return ret; 1123 return ret;
1098} 1124}
@@ -1176,14 +1202,15 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1176 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1202 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1177 enum drm_connector_status ret = connector_status_disconnected; 1203 enum drm_connector_status ret = connector_status_disconnected;
1178 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1204 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1205 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1179 1206
1180 if (radeon_connector->edid) { 1207 if (radeon_connector->edid) {
1181 kfree(radeon_connector->edid); 1208 kfree(radeon_connector->edid);
1182 radeon_connector->edid = NULL; 1209 radeon_connector->edid = NULL;
1183 } 1210 }
1184 1211
1185 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1212 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1186 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 1213 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1187 if (encoder) { 1214 if (encoder) {
1188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1189 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 1216 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
@@ -1203,6 +1230,11 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1203 atombios_set_edp_panel_power(connector, 1230 atombios_set_edp_panel_power(connector,
1204 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1231 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1205 } else { 1232 } else {
1233 /* need to setup ddc on the bridge */
1234 if (radeon_connector_encoder_is_dp_bridge(connector)) {
1235 if (encoder)
1236 radeon_atom_ext_encoder_setup_ddc(encoder);
1237 }
1206 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); 1238 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1207 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { 1239 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1208 ret = connector_status_connected; 1240 ret = connector_status_connected;
@@ -1217,6 +1249,16 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1217 ret = connector_status_connected; 1249 ret = connector_status_connected;
1218 } 1250 }
1219 } 1251 }
1252
1253 if ((ret == connector_status_disconnected) &&
1254 radeon_connector->dac_load_detect) {
1255 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1256 struct drm_encoder_helper_funcs *encoder_funcs;
1257 if (encoder) {
1258 encoder_funcs = encoder->helper_private;
1259 ret = encoder_funcs->detect(encoder, connector);
1260 }
1261 }
1220 } 1262 }
1221 1263
1222 radeon_connector_update_scratch_regs(connector, ret); 1264 radeon_connector_update_scratch_regs(connector, ret);
@@ -1231,7 +1273,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1231 1273
1232 /* XXX check mode bandwidth */ 1274 /* XXX check mode bandwidth */
1233 1275
1234 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1276 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1277 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1235 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 1278 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1236 1279
1237 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1280 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
@@ -1241,7 +1284,7 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1242 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 1285 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1243 1286
1244 /* AVIVO hardware supports downscaling modes larger than the panel 1287 /* AVIVO hardware supports downscaling modes larger than the panel
1245 * to the panel size, but I'm not sure this is desirable. 1288 * to the panel size, but I'm not sure this is desirable.
1246 */ 1289 */
1247 if ((mode->hdisplay > native_mode->hdisplay) || 1290 if ((mode->hdisplay > native_mode->hdisplay) ||
@@ -1390,6 +1433,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1390 default: 1433 default:
1391 connector->interlace_allowed = true; 1434 connector->interlace_allowed = true;
1392 connector->doublescan_allowed = true; 1435 connector->doublescan_allowed = true;
1436 radeon_connector->dac_load_detect = true;
1437 drm_connector_attach_property(&radeon_connector->base,
1438 rdev->mode_info.load_detect_property,
1439 1);
1393 break; 1440 break;
1394 case DRM_MODE_CONNECTOR_DVII: 1441 case DRM_MODE_CONNECTOR_DVII:
1395 case DRM_MODE_CONNECTOR_DVID: 1442 case DRM_MODE_CONNECTOR_DVID:
@@ -1411,6 +1458,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1411 connector->doublescan_allowed = true; 1458 connector->doublescan_allowed = true;
1412 else 1459 else
1413 connector->doublescan_allowed = false; 1460 connector->doublescan_allowed = false;
1461 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1462 radeon_connector->dac_load_detect = true;
1463 drm_connector_attach_property(&radeon_connector->base,
1464 rdev->mode_info.load_detect_property,
1465 1);
1466 }
1414 break; 1467 break;
1415 case DRM_MODE_CONNECTOR_LVDS: 1468 case DRM_MODE_CONNECTOR_LVDS:
1416 case DRM_MODE_CONNECTOR_eDP: 1469 case DRM_MODE_CONNECTOR_eDP:
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e680501c78e..7cfaa7e2f3b 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -215,6 +215,8 @@ int radeon_wb_init(struct radeon_device *rdev)
215 return r; 215 return r;
216 } 216 }
217 217
218 /* clear wb memory */
219 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
218 /* disable event_write fences */ 220 /* disable event_write fences */
219 rdev->wb.use_event = false; 221 rdev->wb.use_event = false;
220 /* disabled via module param */ 222 /* disabled via module param */
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 03f124d626c..b293487e5aa 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -367,7 +367,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
367 } 367 }
368 368
369 if (ASIC_IS_DCE3(rdev) && 369 if (ASIC_IS_DCE3(rdev) &&
370 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { 370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 radeon_encoder_is_dp_bridge(encoder))) {
371 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
372 radeon_dp_set_link_config(connector, mode); 373 radeon_dp_set_link_config(connector, mode);
373 } 374 }
@@ -660,21 +661,16 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
660 if (radeon_encoder_is_dp_bridge(encoder)) 661 if (radeon_encoder_is_dp_bridge(encoder))
661 return ATOM_ENCODER_MODE_DP; 662 return ATOM_ENCODER_MODE_DP;
662 663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
663 connector = radeon_get_connector_for_encoder(encoder); 668 connector = radeon_get_connector_for_encoder(encoder);
664 if (!connector) { 669 /* if we don't have an active device yet, just use one of
665 switch (radeon_encoder->encoder_id) { 670 * the connectors tied to the encoder.
666 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 671 */
667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 672 if (!connector)
668 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 673 connector = radeon_get_connector_for_encoder_init(encoder);
669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
670 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
671 return ATOM_ENCODER_MODE_DVI;
672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
674 default:
675 return ATOM_ENCODER_MODE_CRT;
676 }
677 }
678 radeon_connector = to_radeon_connector(connector); 674 radeon_connector = to_radeon_connector(connector);
679 675
680 switch (connector->connector_type) { 676 switch (connector->connector_type) {
@@ -1094,9 +1090,10 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1094 break; 1090 break;
1095 } 1091 }
1096 1092
1097 if (is_dp) 1093 if (is_dp) {
1098 args.v2.acConfig.fCoherentMode = 1; 1094 args.v2.acConfig.fCoherentMode = 1;
1099 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1100 if (dig->coherent_mode) 1097 if (dig->coherent_mode)
1101 args.v2.acConfig.fCoherentMode = 1; 1098 args.v2.acConfig.fCoherentMode = 1;
1102 if (radeon_encoder->pixel_clock > 165000) 1099 if (radeon_encoder->pixel_clock > 165000)
@@ -1435,7 +1432,11 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1435 if (is_dig) { 1432 if (is_dig) {
1436 switch (mode) { 1433 switch (mode) {
1437 case DRM_MODE_DPMS_ON: 1434 case DRM_MODE_DPMS_ON:
1438 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1438 else
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1439 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1440 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1441 1442
@@ -1526,26 +1527,29 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1526 } 1527 }
1527 1528
1528 if (ext_encoder) { 1529 if (ext_encoder) {
1529 int action;
1530
1531 switch (mode) { 1530 switch (mode) {
1532 case DRM_MODE_DPMS_ON: 1531 case DRM_MODE_DPMS_ON:
1533 default: 1532 default:
1534 if (ASIC_IS_DCE41(rdev)) 1533 if (ASIC_IS_DCE41(rdev)) {
1535 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; 1534 atombios_external_encoder_setup(encoder, ext_encoder,
1536 else 1535 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1537 action = ATOM_ENABLE; 1536 atombios_external_encoder_setup(encoder, ext_encoder,
1537 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1538 } else
1539 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1538 break; 1540 break;
1539 case DRM_MODE_DPMS_STANDBY: 1541 case DRM_MODE_DPMS_STANDBY:
1540 case DRM_MODE_DPMS_SUSPEND: 1542 case DRM_MODE_DPMS_SUSPEND:
1541 case DRM_MODE_DPMS_OFF: 1543 case DRM_MODE_DPMS_OFF:
1542 if (ASIC_IS_DCE41(rdev)) 1544 if (ASIC_IS_DCE41(rdev)) {
1543 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; 1545 atombios_external_encoder_setup(encoder, ext_encoder,
1544 else 1546 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1545 action = ATOM_DISABLE; 1547 atombios_external_encoder_setup(encoder, ext_encoder,
1548 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1549 } else
1550 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1546 break; 1551 break;
1547 } 1552 }
1548 atombios_external_encoder_setup(encoder, ext_encoder, action);
1549 } 1553 }
1550 1554
1551 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1555 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
@@ -2004,6 +2008,65 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
2004 return connector_status_disconnected; 2008 return connector_status_disconnected;
2005} 2009}
2006 2010
2011static enum drm_connector_status
2012radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2013{
2014 struct drm_device *dev = encoder->dev;
2015 struct radeon_device *rdev = dev->dev_private;
2016 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2017 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2018 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2019 u32 bios_0_scratch;
2020
2021 if (!ASIC_IS_DCE4(rdev))
2022 return connector_status_unknown;
2023
2024 if (!ext_encoder)
2025 return connector_status_unknown;
2026
2027 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2028 return connector_status_unknown;
2029
2030 /* load detect on the dp bridge */
2031 atombios_external_encoder_setup(encoder, ext_encoder,
2032 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2033
2034 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2035
2036 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2037 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2038 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2039 return connector_status_connected;
2040 }
2041 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2042 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2043 return connector_status_connected;
2044 }
2045 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2046 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2047 return connector_status_connected;
2048 }
2049 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2050 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2051 return connector_status_connected; /* CTV */
2052 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2053 return connector_status_connected; /* STV */
2054 }
2055 return connector_status_disconnected;
2056}
2057
2058void
2059radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2060{
2061 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2062
2063 if (ext_encoder)
2064 /* ddc_setup on the dp bridge */
2065 atombios_external_encoder_setup(encoder, ext_encoder,
2066 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2067
2068}
2069
2007static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2070static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2008{ 2071{
2009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2072 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -2167,7 +2230,7 @@ static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2167 .mode_set = radeon_atom_encoder_mode_set, 2230 .mode_set = radeon_atom_encoder_mode_set,
2168 .commit = radeon_atom_encoder_commit, 2231 .commit = radeon_atom_encoder_commit,
2169 .disable = radeon_atom_encoder_disable, 2232 .disable = radeon_atom_encoder_disable,
2170 /* no detect for TMDS/LVDS yet */ 2233 .detect = radeon_atom_dig_detect,
2171}; 2234};
2172 2235
2173static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2236static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 1f822943657..021d2b6b556 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -40,6 +40,35 @@
40#include "radeon.h" 40#include "radeon.h"
41#include "radeon_trace.h" 41#include "radeon_trace.h"
42 42
43static void radeon_fence_write(struct radeon_device *rdev, u32 seq)
44{
45 if (rdev->wb.enabled) {
46 u32 scratch_index;
47 if (rdev->wb.use_event)
48 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
49 else
50 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
51 rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);;
52 } else
53 WREG32(rdev->fence_drv.scratch_reg, seq);
54}
55
56static u32 radeon_fence_read(struct radeon_device *rdev)
57{
58 u32 seq;
59
60 if (rdev->wb.enabled) {
61 u32 scratch_index;
62 if (rdev->wb.use_event)
63 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
64 else
65 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
66 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
67 } else
68 seq = RREG32(rdev->fence_drv.scratch_reg);
69 return seq;
70}
71
43int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) 72int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
44{ 73{
45 unsigned long irq_flags; 74 unsigned long irq_flags;
@@ -50,12 +79,12 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
50 return 0; 79 return 0;
51 } 80 }
52 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); 81 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
53 if (!rdev->cp.ready) { 82 if (!rdev->cp.ready)
54 /* FIXME: cp is not running assume everythings is done right 83 /* FIXME: cp is not running assume everythings is done right
55 * away 84 * away
56 */ 85 */
57 WREG32(rdev->fence_drv.scratch_reg, fence->seq); 86 radeon_fence_write(rdev, fence->seq);
58 } else 87 else
59 radeon_fence_ring_emit(rdev, fence); 88 radeon_fence_ring_emit(rdev, fence);
60 89
61 trace_radeon_fence_emit(rdev->ddev, fence->seq); 90 trace_radeon_fence_emit(rdev->ddev, fence->seq);
@@ -73,15 +102,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
73 bool wake = false; 102 bool wake = false;
74 unsigned long cjiffies; 103 unsigned long cjiffies;
75 104
76 if (rdev->wb.enabled) { 105 seq = radeon_fence_read(rdev);
77 u32 scratch_index;
78 if (rdev->wb.use_event)
79 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
80 else
81 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
82 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
83 } else
84 seq = RREG32(rdev->fence_drv.scratch_reg);
85 if (seq != rdev->fence_drv.last_seq) { 106 if (seq != rdev->fence_drv.last_seq) {
86 rdev->fence_drv.last_seq = seq; 107 rdev->fence_drv.last_seq = seq;
87 rdev->fence_drv.last_jiffies = jiffies; 108 rdev->fence_drv.last_jiffies = jiffies;
@@ -251,7 +272,7 @@ retry:
251 r = radeon_gpu_reset(rdev); 272 r = radeon_gpu_reset(rdev);
252 if (r) 273 if (r)
253 return r; 274 return r;
254 WREG32(rdev->fence_drv.scratch_reg, fence->seq); 275 radeon_fence_write(rdev, fence->seq);
255 rdev->gpu_lockup = false; 276 rdev->gpu_lockup = false;
256 } 277 }
257 timeout = RADEON_FENCE_JIFFIES_TIMEOUT; 278 timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
@@ -351,7 +372,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
351 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 372 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
352 return r; 373 return r;
353 } 374 }
354 WREG32(rdev->fence_drv.scratch_reg, 0); 375 radeon_fence_write(rdev, 0);
355 atomic_set(&rdev->fence_drv.seq, 0); 376 atomic_set(&rdev->fence_drv.seq, 0);
356 INIT_LIST_HEAD(&rdev->fence_drv.created); 377 INIT_LIST_HEAD(&rdev->fence_drv.created);
357 INIT_LIST_HEAD(&rdev->fence_drv.emited); 378 INIT_LIST_HEAD(&rdev->fence_drv.emited);
@@ -391,7 +412,7 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
391 struct radeon_fence *fence; 412 struct radeon_fence *fence;
392 413
393 seq_printf(m, "Last signaled fence 0x%08X\n", 414 seq_printf(m, "Last signaled fence 0x%08X\n",
394 RREG32(rdev->fence_drv.scratch_reg)); 415 radeon_fence_read(rdev));
395 if (!list_empty(&rdev->fence_drv.emited)) { 416 if (!list_empty(&rdev->fence_drv.emited)) {
396 fence = list_entry(rdev->fence_drv.emited.prev, 417 fence = list_entry(rdev->fence_drv.emited.prev,
397 struct radeon_fence, list); 418 struct radeon_fence, list);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 977a341266b..6df4e3cec0c 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -483,6 +483,8 @@ extern void radeon_atom_encoder_init(struct radeon_device *rdev);
483extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 483extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
484 int action, uint8_t lane_num, 484 int action, uint8_t lane_num,
485 uint8_t lane_set); 485 uint8_t lane_set);
486extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
487extern struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder);
486extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 488extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
487 u8 write_byte, u8 *read_byte); 489 u8 write_byte, u8 *read_byte);
488 490
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index ef8a5babe9f..4de51891aa6 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -105,6 +105,9 @@ void rv770_pm_misc(struct radeon_device *rdev)
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106 106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
108 if (voltage->voltage != rdev->pm.current_vddc) { 111 if (voltage->voltage != rdev->pm.current_vddc) {
109 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
110 rdev->pm.current_vddc = voltage->voltage; 113 rdev->pm.current_vddc = voltage->voltage;
@@ -572,6 +575,12 @@ static void rv770_program_channel_remap(struct radeon_device *rdev)
572 else 575 else
573 tcp_chan_steer = 0x00fac688; 576 tcp_chan_steer = 0x00fac688;
574 577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
575 WREG32(TCP_CHAN_STEER, tcp_chan_steer); 584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
576 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
577} 586}
@@ -1359,6 +1368,7 @@ void rv770_fini(struct radeon_device *rdev)
1359 r700_cp_fini(rdev); 1368 r700_cp_fini(rdev);
1360 r600_irq_fini(rdev); 1369 r600_irq_fini(rdev);
1361 radeon_wb_fini(rdev); 1370 radeon_wb_fini(rdev);
1371 radeon_ib_pool_fini(rdev);
1362 radeon_irq_kms_fini(rdev); 1372 radeon_irq_kms_fini(rdev);
1363 rv770_pcie_gart_fini(rdev); 1373 rv770_pcie_gart_fini(rdev);
1364 rv770_vram_scratch_fini(rdev); 1374 rv770_vram_scratch_fini(rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 07:52:41 -0500