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-rw-r--r--drivers/gpu/drm/drm_bufs.c17
-rw-r--r--drivers/gpu/drm/drm_crtc.c5
-rw-r--r--drivers/gpu/drm/drm_edid.c19
-rw-r--r--drivers/gpu/drm/drm_gem.c1
-rw-r--r--drivers/gpu/drm/drm_ioc32.c9
-rw-r--r--drivers/gpu/drm/drm_pci.c3
-rw-r--r--drivers/gpu/drm/drm_vm.c2
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c16
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c34
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c11
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h35
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c58
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c89
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c16
-rw-r--r--drivers/gpu/drm/i915/intel_display.c308
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c3
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c12
-rw-r--r--drivers/gpu/drm/mga/mga_drv.h19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c59
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_perf.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c17
-rw-r--r--drivers/gpu/drm/radeon/atombios.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c197
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/nid.h2
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h8
-rw-r--r--drivers/gpu/drm/radeon/r600.c21
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c31
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c44
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c71
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c123
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c51
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c10
-rw-r--r--drivers/gpu/drm/savage/savage_bci.c3
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c5
48 files changed, 886 insertions, 472 deletions
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 3e257a50bf5..61e1ef90d4e 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -46,10 +46,11 @@ static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
46 list_for_each_entry(entry, &dev->maplist, head) { 46 list_for_each_entry(entry, &dev->maplist, head) {
47 /* 47 /*
48 * Because the kernel-userspace ABI is fixed at a 32-bit offset 48 * Because the kernel-userspace ABI is fixed at a 32-bit offset
49 * while PCI resources may live above that, we ignore the map 49 * while PCI resources may live above that, we only compare the
50 * offset for maps of type _DRM_FRAMEBUFFER or _DRM_REGISTERS. 50 * lower 32 bits of the map offset for maps of type
51 * It is assumed that each driver will have only one resource of 51 * _DRM_FRAMEBUFFER or _DRM_REGISTERS.
52 * each type. 52 * It is assumed that if a driver have more than one resource
53 * of each type, the lower 32 bits are different.
53 */ 54 */
54 if (!entry->map || 55 if (!entry->map ||
55 map->type != entry->map->type || 56 map->type != entry->map->type ||
@@ -59,9 +60,12 @@ static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
59 case _DRM_SHM: 60 case _DRM_SHM:
60 if (map->flags != _DRM_CONTAINS_LOCK) 61 if (map->flags != _DRM_CONTAINS_LOCK)
61 break; 62 break;
63 return entry;
62 case _DRM_REGISTERS: 64 case _DRM_REGISTERS:
63 case _DRM_FRAME_BUFFER: 65 case _DRM_FRAME_BUFFER:
64 return entry; 66 if ((entry->map->offset & 0xffffffff) ==
67 (map->offset & 0xffffffff))
68 return entry;
65 default: /* Make gcc happy */ 69 default: /* Make gcc happy */
66 ; 70 ;
67 } 71 }
@@ -183,9 +187,6 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
183 return -EINVAL; 187 return -EINVAL;
184 } 188 }
185#endif 189#endif
186#ifdef __alpha__
187 map->offset += dev->hose->mem_space->start;
188#endif
189 /* Some drivers preinitialize some maps, without the X Server 190 /* Some drivers preinitialize some maps, without the X Server
190 * needing to be aware of it. Therefore, we just return success 191 * needing to be aware of it. Therefore, we just return success
191 * when the server tries to create a duplicate map. 192 * when the server tries to create a duplicate map.
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 872747c5a54..82db1850666 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -886,9 +886,6 @@ int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
886 total_objects += dev->mode_config.num_connector; 886 total_objects += dev->mode_config.num_connector;
887 total_objects += dev->mode_config.num_encoder; 887 total_objects += dev->mode_config.num_encoder;
888 888
889 if (total_objects == 0)
890 return -EINVAL;
891
892 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL); 889 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL);
893 if (!group->id_list) 890 if (!group->id_list)
894 return -ENOMEM; 891 return -ENOMEM;
@@ -1113,7 +1110,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
1113 if (card_res->count_fbs >= fb_count) { 1110 if (card_res->count_fbs >= fb_count) {
1114 copied = 0; 1111 copied = 0;
1115 fb_id = (uint32_t __user *)(unsigned long)card_res->fb_id_ptr; 1112 fb_id = (uint32_t __user *)(unsigned long)card_res->fb_id_ptr;
1116 list_for_each_entry(fb, &file_priv->fbs, head) { 1113 list_for_each_entry(fb, &file_priv->fbs, filp_head) {
1117 if (put_user(fb->base.id, fb_id + copied)) { 1114 if (put_user(fb->base.id, fb_id + copied)) {
1118 ret = -EFAULT; 1115 ret = -EFAULT;
1119 goto out; 1116 goto out;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0a9357c66ff..09292193daf 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -184,9 +184,9 @@ drm_edid_block_valid(u8 *raw_edid)
184 184
185bad: 185bad:
186 if (raw_edid) { 186 if (raw_edid) {
187 DRM_ERROR("Raw EDID:\n"); 187 printk(KERN_ERR "Raw EDID:\n");
188 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH); 188 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
189 printk("\n"); 189 printk(KERN_ERR "\n");
190 } 190 }
191 return 0; 191 return 0;
192} 192}
@@ -258,6 +258,17 @@ drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
258 return ret == 2 ? 0 : -1; 258 return ret == 2 ? 0 : -1;
259} 259}
260 260
261static bool drm_edid_is_zero(u8 *in_edid, int length)
262{
263 int i;
264 u32 *raw_edid = (u32 *)in_edid;
265
266 for (i = 0; i < length / 4; i++)
267 if (*(raw_edid + i) != 0)
268 return false;
269 return true;
270}
271
261static u8 * 272static u8 *
262drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 273drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
263{ 274{
@@ -273,6 +284,10 @@ drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
273 goto out; 284 goto out;
274 if (drm_edid_block_valid(block)) 285 if (drm_edid_block_valid(block))
275 break; 286 break;
287 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
288 connector->null_edid_counter++;
289 goto carp;
290 }
276 } 291 }
277 if (i == 4) 292 if (i == 4)
278 goto carp; 293 goto carp;
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 74e4ff57801..4012fe42346 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -34,6 +34,7 @@
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/mman.h> 35#include <linux/mman.h>
36#include <linux/pagemap.h> 36#include <linux/pagemap.h>
37#include <linux/shmem_fs.h>
37#include "drmP.h" 38#include "drmP.h"
38 39
39/** @file drm_gem.c 40/** @file drm_gem.c
diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c
index d61d185cf04..4a058c7af6c 100644
--- a/drivers/gpu/drm/drm_ioc32.c
+++ b/drivers/gpu/drm/drm_ioc32.c
@@ -28,6 +28,7 @@
28 * IN THE SOFTWARE. 28 * IN THE SOFTWARE.
29 */ 29 */
30#include <linux/compat.h> 30#include <linux/compat.h>
31#include <linux/ratelimit.h>
31 32
32#include "drmP.h" 33#include "drmP.h"
33#include "drm_core.h" 34#include "drm_core.h"
@@ -253,10 +254,10 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
253 return -EFAULT; 254 return -EFAULT;
254 255
255 m32.handle = (unsigned long)handle; 256 m32.handle = (unsigned long)handle;
256 if (m32.handle != (unsigned long)handle && printk_ratelimit()) 257 if (m32.handle != (unsigned long)handle)
257 printk(KERN_ERR "compat_drm_addmap truncated handle" 258 printk_ratelimited(KERN_ERR "compat_drm_addmap truncated handle"
258 " %p for type %d offset %x\n", 259 " %p for type %d offset %x\n",
259 handle, m32.type, m32.offset); 260 handle, m32.type, m32.offset);
260 261
261 if (copy_to_user(argp, &m32, sizeof(m32))) 262 if (copy_to_user(argp, &m32, sizeof(m32)))
262 return -EFAULT; 263 return -EFAULT;
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index e1aee4f6a7c..b6a19cb07ca 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -251,7 +251,7 @@ err:
251} 251}
252 252
253 253
254int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p) 254static int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p)
255{ 255{
256 if ((p->busnum >> 8) != drm_get_pci_domain(dev) || 256 if ((p->busnum >> 8) != drm_get_pci_domain(dev) ||
257 (p->busnum & 0xff) != dev->pdev->bus->number || 257 (p->busnum & 0xff) != dev->pdev->bus->number ||
@@ -292,6 +292,7 @@ static struct drm_bus drm_pci_bus = {
292 .get_name = drm_pci_get_name, 292 .get_name = drm_pci_get_name,
293 .set_busid = drm_pci_set_busid, 293 .set_busid = drm_pci_set_busid,
294 .set_unique = drm_pci_set_unique, 294 .set_unique = drm_pci_set_unique,
295 .irq_by_busid = drm_pci_irq_by_busid,
295 .agp_init = drm_pci_agp_init, 296 .agp_init = drm_pci_agp_init,
296}; 297};
297 298
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index 2c3fcbdfd8f..5db96d45fc7 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -526,7 +526,7 @@ static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma)
526static resource_size_t drm_core_get_reg_ofs(struct drm_device *dev) 526static resource_size_t drm_core_get_reg_ofs(struct drm_device *dev)
527{ 527{
528#ifdef __alpha__ 528#ifdef __alpha__
529 return dev->hose->dense_mem_base - dev->hose->mem_space->start; 529 return dev->hose->dense_mem_base;
530#else 530#else
531 return 0; 531 return 0;
532#endif 532#endif
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4d46441cbe2..0a893f7400f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1207,13 +1207,17 @@ static int i915_context_status(struct seq_file *m, void *unused)
1207 if (ret) 1207 if (ret)
1208 return ret; 1208 return ret;
1209 1209
1210 seq_printf(m, "power context "); 1210 if (dev_priv->pwrctx) {
1211 describe_obj(m, dev_priv->pwrctx); 1211 seq_printf(m, "power context ");
1212 seq_printf(m, "\n"); 1212 describe_obj(m, dev_priv->pwrctx);
1213 seq_printf(m, "\n");
1214 }
1213 1215
1214 seq_printf(m, "render context "); 1216 if (dev_priv->renderctx) {
1215 describe_obj(m, dev_priv->renderctx); 1217 seq_printf(m, "render context ");
1216 seq_printf(m, "\n"); 1218 describe_obj(m, dev_priv->renderctx);
1219 seq_printf(m, "\n");
1220 }
1217 1221
1218 mutex_unlock(&dev->mode_config.mutex); 1222 mutex_unlock(&dev->mode_config.mutex);
1219 1223
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0239e9974bf..e1787022d6c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1266,30 +1266,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
1266 1266
1267 intel_modeset_gem_init(dev); 1267 intel_modeset_gem_init(dev);
1268 1268
1269 if (IS_IVYBRIDGE(dev)) {
1270 /* Share pre & uninstall handlers with ILK/SNB */
1271 dev->driver->irq_handler = ivybridge_irq_handler;
1272 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1273 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1274 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1275 dev->driver->enable_vblank = ivybridge_enable_vblank;
1276 dev->driver->disable_vblank = ivybridge_disable_vblank;
1277 } else if (HAS_PCH_SPLIT(dev)) {
1278 dev->driver->irq_handler = ironlake_irq_handler;
1279 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1280 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1281 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1282 dev->driver->enable_vblank = ironlake_enable_vblank;
1283 dev->driver->disable_vblank = ironlake_disable_vblank;
1284 } else {
1285 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1286 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1287 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1288 dev->driver->irq_handler = i915_driver_irq_handler;
1289 dev->driver->enable_vblank = i915_enable_vblank;
1290 dev->driver->disable_vblank = i915_disable_vblank;
1291 }
1292
1293 ret = drm_irq_install(dev); 1269 ret = drm_irq_install(dev);
1294 if (ret) 1270 if (ret)
1295 goto cleanup_gem; 1271 goto cleanup_gem;
@@ -2017,12 +1993,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2017 /* enable GEM by default */ 1993 /* enable GEM by default */
2018 dev_priv->has_gem = 1; 1994 dev_priv->has_gem = 1;
2019 1995
2020 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1996 intel_irq_init(dev);
2021 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2022 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2025 }
2026 1997
2027 /* Try to make sure MCHBAR is enabled before poking at it */ 1998 /* Try to make sure MCHBAR is enabled before poking at it */
2028 intel_setup_mchbar(dev); 1999 intel_setup_mchbar(dev);
@@ -2182,9 +2153,8 @@ int i915_driver_unload(struct drm_device *dev)
2182 /* Flush any outstanding unpin_work. */ 2153 /* Flush any outstanding unpin_work. */
2183 flush_workqueue(dev_priv->wq); 2154 flush_workqueue(dev_priv->wq);
2184 2155
2185 i915_gem_free_all_phys_object(dev);
2186
2187 mutex_lock(&dev->struct_mutex); 2156 mutex_lock(&dev->struct_mutex);
2157 i915_gem_free_all_phys_object(dev);
2188 i915_gem_cleanup_ringbuffer(dev); 2158 i915_gem_cleanup_ringbuffer(dev);
2189 mutex_unlock(&dev->struct_mutex); 2159 mutex_unlock(&dev->struct_mutex);
2190 if (I915_HAS_FBC(dev) && i915_powersave) 2160 if (I915_HAS_FBC(dev) && i915_powersave)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0defd427059..013d304455b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -579,6 +579,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
579 } else switch (INTEL_INFO(dev)->gen) { 579 } else switch (INTEL_INFO(dev)->gen) {
580 case 6: 580 case 6:
581 ret = gen6_do_reset(dev, flags); 581 ret = gen6_do_reset(dev, flags);
582 /* If reset with a user forcewake, try to restore */
583 if (atomic_read(&dev_priv->forcewake_count))
584 __gen6_gt_force_wake_get(dev_priv);
582 break; 585 break;
583 case 5: 586 case 5:
584 ret = ironlake_do_reset(dev, flags); 587 ret = ironlake_do_reset(dev, flags);
@@ -762,14 +765,6 @@ static struct drm_driver driver = {
762 .resume = i915_resume, 765 .resume = i915_resume,
763 766
764 .device_is_agp = i915_driver_device_is_agp, 767 .device_is_agp = i915_driver_device_is_agp,
765 .enable_vblank = i915_enable_vblank,
766 .disable_vblank = i915_disable_vblank,
767 .get_vblank_timestamp = i915_get_vblank_timestamp,
768 .get_scanout_position = i915_get_crtc_scanoutpos,
769 .irq_preinstall = i915_driver_irq_preinstall,
770 .irq_postinstall = i915_driver_irq_postinstall,
771 .irq_uninstall = i915_driver_irq_uninstall,
772 .irq_handler = i915_driver_irq_handler,
773 .reclaim_buffers = drm_core_reclaim_buffers, 768 .reclaim_buffers = drm_core_reclaim_buffers,
774 .master_create = i915_master_create, 769 .master_create = i915_master_create,
775 .master_destroy = i915_master_destroy, 770 .master_destroy = i915_master_destroy,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f63ee162f12..f245c588ae9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -211,6 +211,9 @@ struct drm_i915_display_funcs {
211 void (*fdi_link_train)(struct drm_crtc *crtc); 211 void (*fdi_link_train)(struct drm_crtc *crtc);
212 void (*init_clock_gating)(struct drm_device *dev); 212 void (*init_clock_gating)(struct drm_device *dev);
213 void (*init_pch_clock_gating)(struct drm_device *dev); 213 void (*init_pch_clock_gating)(struct drm_device *dev);
214 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
215 struct drm_framebuffer *fb,
216 struct drm_i915_gem_object *obj);
214 /* clock updates for mode set */ 217 /* clock updates for mode set */
215 /* cursor updates */ 218 /* cursor updates */
216 /* render clock increase/decrease */ 219 /* render clock increase/decrease */
@@ -994,8 +997,6 @@ extern unsigned int i915_enable_fbc;
994 997
995extern int i915_suspend(struct drm_device *dev, pm_message_t state); 998extern int i915_suspend(struct drm_device *dev, pm_message_t state);
996extern int i915_resume(struct drm_device *dev); 999extern int i915_resume(struct drm_device *dev);
997extern void i915_save_display(struct drm_device *dev);
998extern void i915_restore_display(struct drm_device *dev);
999extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1000extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1000extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1001extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1001 1002
@@ -1030,33 +1031,12 @@ extern int i915_irq_emit(struct drm_device *dev, void *data,
1030extern int i915_irq_wait(struct drm_device *dev, void *data, 1031extern int i915_irq_wait(struct drm_device *dev, void *data,
1031 struct drm_file *file_priv); 1032 struct drm_file *file_priv);
1032 1033
1033extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 1034extern void intel_irq_init(struct drm_device *dev);
1034extern void i915_driver_irq_preinstall(struct drm_device * dev);
1035extern int i915_driver_irq_postinstall(struct drm_device *dev);
1036extern void i915_driver_irq_uninstall(struct drm_device * dev);
1037
1038extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1039extern void ironlake_irq_preinstall(struct drm_device *dev);
1040extern int ironlake_irq_postinstall(struct drm_device *dev);
1041extern void ironlake_irq_uninstall(struct drm_device *dev);
1042
1043extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1044extern void ivybridge_irq_preinstall(struct drm_device *dev);
1045extern int ivybridge_irq_postinstall(struct drm_device *dev);
1046extern void ivybridge_irq_uninstall(struct drm_device *dev);
1047 1035
1048extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1036extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv); 1037 struct drm_file *file_priv);
1050extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1038extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv); 1039 struct drm_file *file_priv);
1052extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1053extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1054extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1055extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1056extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1057extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1058extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1059extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1060extern int i915_vblank_swap(struct drm_device *dev, void *data, 1040extern int i915_vblank_swap(struct drm_device *dev, void *data,
1061 struct drm_file *file_priv); 1041 struct drm_file *file_priv);
1062 1042
@@ -1067,13 +1047,6 @@ void
1067i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1047i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1068 1048
1069void intel_enable_asle (struct drm_device *dev); 1049void intel_enable_asle (struct drm_device *dev);
1070int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1071 int *max_error,
1072 struct timeval *vblank_time,
1073 unsigned flags);
1074
1075int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1076 int *vpos, int *hpos);
1077 1050
1078#ifdef CONFIG_DEBUG_FS 1051#ifdef CONFIG_DEBUG_FS
1079extern void i915_destroy_error_state(struct drm_device *dev); 1052extern void i915_destroy_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 12d32579b95..5c0d1247f45 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -31,6 +31,7 @@
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "i915_trace.h" 32#include "i915_trace.h"
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/swap.h> 36#include <linux/swap.h>
36#include <linux/pci.h> 37#include <linux/pci.h>
@@ -359,8 +360,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev,
359 if ((page_offset + remain) > PAGE_SIZE) 360 if ((page_offset + remain) > PAGE_SIZE)
360 page_length = PAGE_SIZE - page_offset; 361 page_length = PAGE_SIZE - page_offset;
361 362
362 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
363 GFP_HIGHUSER | __GFP_RECLAIMABLE);
364 if (IS_ERR(page)) 364 if (IS_ERR(page))
365 return PTR_ERR(page); 365 return PTR_ERR(page);
366 366
@@ -463,10 +463,11 @@ i915_gem_shmem_pread_slow(struct drm_device *dev,
463 if ((data_page_offset + page_length) > PAGE_SIZE) 463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset; 464 page_length = PAGE_SIZE - data_page_offset;
465 465
466 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
467 GFP_HIGHUSER | __GFP_RECLAIMABLE); 467 if (IS_ERR(page)) {
468 if (IS_ERR(page)) 468 ret = PTR_ERR(page);
469 return PTR_ERR(page); 469 goto out;
470 }
470 471
471 if (do_bit17_swizzling) { 472 if (do_bit17_swizzling) {
472 slow_shmem_bit17_copy(page, 473 slow_shmem_bit17_copy(page,
@@ -795,8 +796,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev,
795 if ((page_offset + remain) > PAGE_SIZE) 796 if ((page_offset + remain) > PAGE_SIZE)
796 page_length = PAGE_SIZE - page_offset; 797 page_length = PAGE_SIZE - page_offset;
797 798
798 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
799 GFP_HIGHUSER | __GFP_RECLAIMABLE);
800 if (IS_ERR(page)) 800 if (IS_ERR(page))
801 return PTR_ERR(page); 801 return PTR_ERR(page);
802 802
@@ -905,8 +905,7 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev,
905 if ((data_page_offset + page_length) > PAGE_SIZE) 905 if ((data_page_offset + page_length) > PAGE_SIZE)
906 page_length = PAGE_SIZE - data_page_offset; 906 page_length = PAGE_SIZE - data_page_offset;
907 907
908 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
909 GFP_HIGHUSER | __GFP_RECLAIMABLE);
910 if (IS_ERR(page)) { 909 if (IS_ERR(page)) {
911 ret = PTR_ERR(page); 910 ret = PTR_ERR(page);
912 goto out; 911 goto out;
@@ -1217,11 +1216,11 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1217 ret = i915_gem_object_bind_to_gtt(obj, 0, true); 1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1218 if (ret) 1217 if (ret)
1219 goto unlock; 1218 goto unlock;
1220 }
1221 1219
1222 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1223 if (ret) 1221 if (ret)
1224 goto unlock; 1222 goto unlock;
1223 }
1225 1224
1226 if (obj->tiling_mode == I915_TILING_NONE) 1225 if (obj->tiling_mode == I915_TILING_NONE)
1227 ret = i915_gem_object_put_fence(obj); 1226 ret = i915_gem_object_put_fence(obj);
@@ -1556,12 +1555,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1556 1555
1557 inode = obj->base.filp->f_path.dentry->d_inode; 1556 inode = obj->base.filp->f_path.dentry->d_inode;
1558 mapping = inode->i_mapping; 1557 mapping = inode->i_mapping;
1558 gfpmask |= mapping_gfp_mask(mapping);
1559
1559 for (i = 0; i < page_count; i++) { 1560 for (i = 0; i < page_count; i++) {
1560 page = read_cache_page_gfp(mapping, i, 1561 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1561 GFP_HIGHUSER |
1562 __GFP_COLD |
1563 __GFP_RECLAIMABLE |
1564 gfpmask);
1565 if (IS_ERR(page)) 1562 if (IS_ERR(page))
1566 goto err_pages; 1563 goto err_pages;
1567 1564
@@ -1699,13 +1696,10 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1699 /* Our goal here is to return as much of the memory as 1696 /* Our goal here is to return as much of the memory as
1700 * is possible back to the system as we are called from OOM. 1697 * is possible back to the system as we are called from OOM.
1701 * To do this we must instruct the shmfs to drop all of its 1698 * To do this we must instruct the shmfs to drop all of its
1702 * backing pages, *now*. Here we mirror the actions taken 1699 * backing pages, *now*.
1703 * when by shmem_delete_inode() to release the backing store.
1704 */ 1700 */
1705 inode = obj->base.filp->f_path.dentry->d_inode; 1701 inode = obj->base.filp->f_path.dentry->d_inode;
1706 truncate_inode_pages(inode->i_mapping, 0); 1702 shmem_truncate_range(inode, 0, (loff_t)-1);
1707 if (inode->i_op->truncate_range)
1708 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1709 1703
1710 obj->madv = __I915_MADV_PURGED; 1704 obj->madv = __I915_MADV_PURGED;
1711} 1705}
@@ -2078,8 +2072,8 @@ i915_wait_request(struct intel_ring_buffer *ring,
2078 if (!ier) { 2072 if (!ier) {
2079 DRM_ERROR("something (likely vbetool) disabled " 2073 DRM_ERROR("something (likely vbetool) disabled "
2080 "interrupts, re-enabling\n"); 2074 "interrupts, re-enabling\n");
2081 i915_driver_irq_preinstall(ring->dev); 2075 ring->dev->driver->irq_preinstall(ring->dev);
2082 i915_driver_irq_postinstall(ring->dev); 2076 ring->dev->driver->irq_postinstall(ring->dev);
2083 } 2077 }
2084 2078
2085 trace_i915_gem_request_wait_begin(ring, seqno); 2079 trace_i915_gem_request_wait_begin(ring, seqno);
@@ -2924,8 +2918,6 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2924 */ 2918 */
2925 wmb(); 2919 wmb();
2926 2920
2927 i915_gem_release_mmap(obj);
2928
2929 old_write_domain = obj->base.write_domain; 2921 old_write_domain = obj->base.write_domain;
2930 obj->base.write_domain = 0; 2922 obj->base.write_domain = 0;
2931 2923
@@ -3565,6 +3557,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3565{ 3557{
3566 struct drm_i915_private *dev_priv = dev->dev_private; 3558 struct drm_i915_private *dev_priv = dev->dev_private;
3567 struct drm_i915_gem_object *obj; 3559 struct drm_i915_gem_object *obj;
3560 struct address_space *mapping;
3568 3561
3569 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 3562 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3570 if (obj == NULL) 3563 if (obj == NULL)
@@ -3575,6 +3568,9 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3575 return NULL; 3568 return NULL;
3576 } 3569 }
3577 3570
3571 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3572 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3573
3578 i915_gem_info_add_obj(dev_priv, size); 3574 i915_gem_info_add_obj(dev_priv, size);
3579 3575
3580 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 3576 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
@@ -3950,8 +3946,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
3950 3946
3951 page_count = obj->base.size / PAGE_SIZE; 3947 page_count = obj->base.size / PAGE_SIZE;
3952 for (i = 0; i < page_count; i++) { 3948 for (i = 0; i < page_count; i++) {
3953 struct page *page = read_cache_page_gfp(mapping, i, 3949 struct page *page = shmem_read_mapping_page(mapping, i);
3954 GFP_HIGHUSER | __GFP_RECLAIMABLE);
3955 if (!IS_ERR(page)) { 3950 if (!IS_ERR(page)) {
3956 char *dst = kmap_atomic(page); 3951 char *dst = kmap_atomic(page);
3957 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); 3952 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
@@ -4012,8 +4007,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
4012 struct page *page; 4007 struct page *page;
4013 char *dst, *src; 4008 char *dst, *src;
4014 4009
4015 page = read_cache_page_gfp(mapping, i, 4010 page = shmem_read_mapping_page(mapping, i);
4016 GFP_HIGHUSER | __GFP_RECLAIMABLE);
4017 if (IS_ERR(page)) 4011 if (IS_ERR(page))
4018 return PTR_ERR(page); 4012 return PTR_ERR(page);
4019 4013
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 20a4cc5b818..4934cf84c32 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -187,10 +187,6 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) 187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
188 i915_gem_clflush_object(obj); 188 i915_gem_clflush_object(obj);
189 189
190 /* blow away mappings if mapped through GTT */
191 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
192 i915_gem_release_mmap(obj);
193
194 if (obj->base.pending_write_domain) 190 if (obj->base.pending_write_domain)
195 cd->flips |= atomic_read(&obj->pending_flip); 191 cd->flips |= atomic_read(&obj->pending_flip);
196 192
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b9fafe3b045..3b03f85ea62 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -152,7 +152,7 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
152/* Called from drm generic code, passed a 'crtc', which 152/* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index 153 * we use as a pipe index
154 */ 154 */
155u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 155static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
156{ 156{
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame; 158 unsigned long high_frame;
@@ -184,7 +184,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
184 return (high1 << 8) | low; 184 return (high1 << 8) | low;
185} 185}
186 186
187u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 187static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
188{ 188{
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe); 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
@@ -198,7 +198,7 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 return I915_READ(reg); 198 return I915_READ(reg);
199} 199}
200 200
201int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 201static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos) 202 int *vpos, int *hpos)
203{ 203{
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -264,7 +264,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
264 return ret; 264 return ret;
265} 265}
266 266
267int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 267static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
268 int *max_error, 268 int *max_error,
269 struct timeval *vblank_time, 269 struct timeval *vblank_time,
270 unsigned flags) 270 unsigned flags)
@@ -462,7 +462,7 @@ static void pch_irq_handler(struct drm_device *dev)
462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
463} 463}
464 464
465irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 465static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
466{ 466{
467 struct drm_device *dev = (struct drm_device *) arg; 467 struct drm_device *dev = (struct drm_device *) arg;
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -550,7 +550,7 @@ done:
550 return ret; 550 return ret;
551} 551}
552 552
553irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 553static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
554{ 554{
555 struct drm_device *dev = (struct drm_device *) arg; 555 struct drm_device *dev = (struct drm_device *) arg;
556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1209,7 +1209,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1209 } 1209 }
1210} 1210}
1211 1211
1212irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1212static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1213{ 1213{
1214 struct drm_device *dev = (struct drm_device *) arg; 1214 struct drm_device *dev = (struct drm_device *) arg;
1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1454,7 +1454,7 @@ int i915_irq_wait(struct drm_device *dev, void *data,
1454/* Called from drm generic code, passed 'crtc' which 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index 1455 * we use as a pipe index
1456 */ 1456 */
1457int i915_enable_vblank(struct drm_device *dev, int pipe) 1457static int i915_enable_vblank(struct drm_device *dev, int pipe)
1458{ 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1460 unsigned long irqflags; 1460 unsigned long irqflags;
@@ -1478,7 +1478,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1478 return 0; 1478 return 0;
1479} 1479}
1480 1480
1481int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1481static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1482{ 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags; 1484 unsigned long irqflags;
@@ -1494,7 +1494,7 @@ int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1494 return 0; 1494 return 0;
1495} 1495}
1496 1496
1497int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1497static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1498{ 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags; 1500 unsigned long irqflags;
@@ -1513,7 +1513,7 @@ int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1513/* Called from drm generic code, passed 'crtc' which 1513/* Called from drm generic code, passed 'crtc' which
1514 * we use as a pipe index 1514 * we use as a pipe index
1515 */ 1515 */
1516void i915_disable_vblank(struct drm_device *dev, int pipe) 1516static void i915_disable_vblank(struct drm_device *dev, int pipe)
1517{ 1517{
1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1519 unsigned long irqflags; 1519 unsigned long irqflags;
@@ -1529,7 +1529,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1530} 1530}
1531 1531
1532void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1532static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1533{ 1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags; 1535 unsigned long irqflags;
@@ -1540,7 +1540,7 @@ void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541} 1541}
1542 1542
1543void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1543static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1544{ 1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags; 1546 unsigned long irqflags;
@@ -1728,7 +1728,7 @@ repeat:
1728 1728
1729/* drm_dma.h hooks 1729/* drm_dma.h hooks
1730*/ 1730*/
1731void ironlake_irq_preinstall(struct drm_device *dev) 1731static void ironlake_irq_preinstall(struct drm_device *dev)
1732{ 1732{
1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1734 1734
@@ -1740,6 +1740,17 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1741 1741
1742 I915_WRITE(HWSTAM, 0xeffe); 1742 I915_WRITE(HWSTAM, 0xeffe);
1743 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1744 /* Workaround stalls observed on Sandy Bridge GPUs by
1745 * making the blitter command streamer generate a
1746 * write to the Hardware Status Page for
1747 * MI_USER_INTERRUPT. This appears to serialize the
1748 * previous seqno write out before the interrupt
1749 * happens.
1750 */
1751 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1752 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1753 }
1743 1754
1744 /* XXX hotplug from PCH */ 1755 /* XXX hotplug from PCH */
1745 1756
@@ -1758,7 +1769,7 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1758 POSTING_READ(SDEIER); 1769 POSTING_READ(SDEIER);
1759} 1770}
1760 1771
1761int ironlake_irq_postinstall(struct drm_device *dev) 1772static int ironlake_irq_postinstall(struct drm_device *dev)
1762{ 1773{
1763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1764 /* enable kind of interrupts always enabled */ 1775 /* enable kind of interrupts always enabled */
@@ -1830,7 +1841,7 @@ int ironlake_irq_postinstall(struct drm_device *dev)
1830 return 0; 1841 return 0;
1831} 1842}
1832 1843
1833int ivybridge_irq_postinstall(struct drm_device *dev) 1844static int ivybridge_irq_postinstall(struct drm_device *dev)
1834{ 1845{
1835 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1836 /* enable kind of interrupts always enabled */ 1847 /* enable kind of interrupts always enabled */
@@ -1880,7 +1891,7 @@ int ivybridge_irq_postinstall(struct drm_device *dev)
1880 return 0; 1891 return 0;
1881} 1892}
1882 1893
1883void i915_driver_irq_preinstall(struct drm_device * dev) 1894static void i915_driver_irq_preinstall(struct drm_device * dev)
1884{ 1895{
1885 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1886 int pipe; 1897 int pipe;
@@ -1907,7 +1918,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1907 * Must be called after intel_modeset_init or hotplug interrupts won't be 1918 * Must be called after intel_modeset_init or hotplug interrupts won't be
1908 * enabled correctly. 1919 * enabled correctly.
1909 */ 1920 */
1910int i915_driver_irq_postinstall(struct drm_device *dev) 1921static int i915_driver_irq_postinstall(struct drm_device *dev)
1911{ 1922{
1912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1913 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
@@ -1983,7 +1994,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1983 return 0; 1994 return 0;
1984} 1995}
1985 1996
1986void ironlake_irq_uninstall(struct drm_device *dev) 1997static void ironlake_irq_uninstall(struct drm_device *dev)
1987{ 1998{
1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1989 2000
@@ -2003,7 +2014,7 @@ void ironlake_irq_uninstall(struct drm_device *dev)
2003 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2014 I915_WRITE(GTIIR, I915_READ(GTIIR));
2004} 2015}
2005 2016
2006void i915_driver_irq_uninstall(struct drm_device * dev) 2017static void i915_driver_irq_uninstall(struct drm_device * dev)
2007{ 2018{
2008 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2009 int pipe; 2020 int pipe;
@@ -2029,3 +2040,41 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
2029 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2030 I915_WRITE(IIR, I915_READ(IIR)); 2041 I915_WRITE(IIR, I915_READ(IIR));
2031} 2042}
2043
2044void intel_irq_init(struct drm_device *dev)
2045{
2046 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2047 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2048 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2049 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2050 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2051 }
2052
2053
2054 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2055 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2056
2057 if (IS_IVYBRIDGE(dev)) {
2058 /* Share pre & uninstall handlers with ILK/SNB */
2059 dev->driver->irq_handler = ivybridge_irq_handler;
2060 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2061 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2062 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2063 dev->driver->enable_vblank = ivybridge_enable_vblank;
2064 dev->driver->disable_vblank = ivybridge_disable_vblank;
2065 } else if (HAS_PCH_SPLIT(dev)) {
2066 dev->driver->irq_handler = ironlake_irq_handler;
2067 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2068 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2069 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2070 dev->driver->enable_vblank = ironlake_enable_vblank;
2071 dev->driver->disable_vblank = ironlake_disable_vblank;
2072 } else {
2073 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2074 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2075 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2076 dev->driver->irq_handler = i915_driver_irq_handler;
2077 dev->driver->enable_vblank = i915_enable_vblank;
2078 dev->driver->disable_vblank = i915_disable_vblank;
2079 }
2080}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f967af8e62..5d5def756c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -531,6 +531,7 @@
531#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 531#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
532#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 532#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
533 533
534#define GEN6_BSD_HWSTAM 0x12098
534#define GEN6_BSD_IMR 0x120a8 535#define GEN6_BSD_IMR 0x120a8
535#define GEN6_BSD_USER_INTERRUPT (1 << 12) 536#define GEN6_BSD_USER_INTERRUPT (1 << 12)
536 537
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 60a94d2b526..5257cfc34c3 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -597,7 +597,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
597 return; 597 return;
598} 598}
599 599
600void i915_save_display(struct drm_device *dev) 600static void i915_save_display(struct drm_device *dev)
601{ 601{
602 struct drm_i915_private *dev_priv = dev->dev_private; 602 struct drm_i915_private *dev_priv = dev->dev_private;
603 603
@@ -689,7 +689,7 @@ void i915_save_display(struct drm_device *dev)
689 i915_save_vga(dev); 689 i915_save_vga(dev);
690} 690}
691 691
692void i915_restore_display(struct drm_device *dev) 692static void i915_restore_display(struct drm_device *dev)
693{ 693{
694 struct drm_i915_private *dev_priv = dev->dev_private; 694 struct drm_i915_private *dev_priv = dev->dev_private;
695 695
@@ -780,6 +780,7 @@ void i915_restore_display(struct drm_device *dev)
780 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 780 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
781 else 781 else
782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
783
783 I915_WRITE(VGA0, dev_priv->saveVGA0); 784 I915_WRITE(VGA0, dev_priv->saveVGA0);
784 I915_WRITE(VGA1, dev_priv->saveVGA1); 785 I915_WRITE(VGA1, dev_priv->saveVGA1);
785 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 786 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -796,6 +797,8 @@ int i915_save_state(struct drm_device *dev)
796 797
797 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 798 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
798 799
800 mutex_lock(&dev->struct_mutex);
801
799 /* Hardware status page */ 802 /* Hardware status page */
800 dev_priv->saveHWS = I915_READ(HWS_PGA); 803 dev_priv->saveHWS = I915_READ(HWS_PGA);
801 804
@@ -835,6 +838,8 @@ int i915_save_state(struct drm_device *dev)
835 for (i = 0; i < 3; i++) 838 for (i = 0; i < 3; i++)
836 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 839 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
837 840
841 mutex_unlock(&dev->struct_mutex);
842
838 return 0; 843 return 0;
839} 844}
840 845
@@ -845,6 +850,8 @@ int i915_restore_state(struct drm_device *dev)
845 850
846 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 851 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
847 852
853 mutex_lock(&dev->struct_mutex);
854
848 /* Hardware status page */ 855 /* Hardware status page */
849 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 856 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
850 857
@@ -862,6 +869,7 @@ int i915_restore_state(struct drm_device *dev)
862 I915_WRITE(IER, dev_priv->saveIER); 869 I915_WRITE(IER, dev_priv->saveIER);
863 I915_WRITE(IMR, dev_priv->saveIMR); 870 I915_WRITE(IMR, dev_priv->saveIMR);
864 } 871 }
872 mutex_unlock(&dev->struct_mutex);
865 873
866 intel_init_clock_gating(dev); 874 intel_init_clock_gating(dev);
867 875
@@ -873,6 +881,8 @@ int i915_restore_state(struct drm_device *dev)
873 if (IS_GEN6(dev)) 881 if (IS_GEN6(dev))
874 gen6_enable_rps(dev_priv); 882 gen6_enable_rps(dev_priv);
875 883
884 mutex_lock(&dev->struct_mutex);
885
876 /* Cache mode state */ 886 /* Cache mode state */
877 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 887 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
878 888
@@ -886,6 +896,8 @@ int i915_restore_state(struct drm_device *dev)
886 for (i = 0; i < 3; i++) 896 for (i = 0; i < 3; i++)
887 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 897 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
888 898
899 mutex_unlock(&dev->struct_mutex);
900
889 intel_i2c_reset(dev); 901 intel_i2c_reset(dev);
890 902
891 return 0; 903 return 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 81a9059b6a9..21b6f93fe91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4687,6 +4687,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4687 4687
4688 I915_WRITE(DSPCNTR(plane), dspcntr); 4688 I915_WRITE(DSPCNTR(plane), dspcntr);
4689 POSTING_READ(DSPCNTR(plane)); 4689 POSTING_READ(DSPCNTR(plane));
4690 intel_enable_plane(dev_priv, plane, pipe);
4690 4691
4691 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4692 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4692 4693
@@ -5217,8 +5218,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5217 5218
5218 I915_WRITE(DSPCNTR(plane), dspcntr); 5219 I915_WRITE(DSPCNTR(plane), dspcntr);
5219 POSTING_READ(DSPCNTR(plane)); 5220 POSTING_READ(DSPCNTR(plane));
5220 if (!HAS_PCH_SPLIT(dev))
5221 intel_enable_plane(dev_priv, plane, pipe);
5222 5221
5223 ret = intel_pipe_set_base(crtc, x, y, old_fb); 5222 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5224 5223
@@ -6262,6 +6261,197 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
6262 spin_unlock_irqrestore(&dev->event_lock, flags); 6261 spin_unlock_irqrestore(&dev->event_lock, flags);
6263} 6262}
6264 6263
6264static int intel_gen2_queue_flip(struct drm_device *dev,
6265 struct drm_crtc *crtc,
6266 struct drm_framebuffer *fb,
6267 struct drm_i915_gem_object *obj)
6268{
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6271 unsigned long offset;
6272 u32 flip_mask;
6273 int ret;
6274
6275 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6276 if (ret)
6277 goto out;
6278
6279 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6280 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6281
6282 ret = BEGIN_LP_RING(6);
6283 if (ret)
6284 goto out;
6285
6286 /* Can't queue multiple flips, so wait for the previous
6287 * one to finish before executing the next.
6288 */
6289 if (intel_crtc->plane)
6290 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6291 else
6292 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6293 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6294 OUT_RING(MI_NOOP);
6295 OUT_RING(MI_DISPLAY_FLIP |
6296 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6297 OUT_RING(fb->pitch);
6298 OUT_RING(obj->gtt_offset + offset);
6299 OUT_RING(MI_NOOP);
6300 ADVANCE_LP_RING();
6301out:
6302 return ret;
6303}
6304
6305static int intel_gen3_queue_flip(struct drm_device *dev,
6306 struct drm_crtc *crtc,
6307 struct drm_framebuffer *fb,
6308 struct drm_i915_gem_object *obj)
6309{
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 unsigned long offset;
6313 u32 flip_mask;
6314 int ret;
6315
6316 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6317 if (ret)
6318 goto out;
6319
6320 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6321 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6322
6323 ret = BEGIN_LP_RING(6);
6324 if (ret)
6325 goto out;
6326
6327 if (intel_crtc->plane)
6328 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6329 else
6330 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6331 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6332 OUT_RING(MI_NOOP);
6333 OUT_RING(MI_DISPLAY_FLIP_I915 |
6334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6335 OUT_RING(fb->pitch);
6336 OUT_RING(obj->gtt_offset + offset);
6337 OUT_RING(MI_NOOP);
6338
6339 ADVANCE_LP_RING();
6340out:
6341 return ret;
6342}
6343
6344static int intel_gen4_queue_flip(struct drm_device *dev,
6345 struct drm_crtc *crtc,
6346 struct drm_framebuffer *fb,
6347 struct drm_i915_gem_object *obj)
6348{
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6351 uint32_t pf, pipesrc;
6352 int ret;
6353
6354 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6355 if (ret)
6356 goto out;
6357
6358 ret = BEGIN_LP_RING(4);
6359 if (ret)
6360 goto out;
6361
6362 /* i965+ uses the linear or tiled offsets from the
6363 * Display Registers (which do not change across a page-flip)
6364 * so we need only reprogram the base address.
6365 */
6366 OUT_RING(MI_DISPLAY_FLIP |
6367 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6368 OUT_RING(fb->pitch);
6369 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6370
6371 /* XXX Enabling the panel-fitter across page-flip is so far
6372 * untested on non-native modes, so ignore it for now.
6373 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6374 */
6375 pf = 0;
6376 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6377 OUT_RING(pf | pipesrc);
6378 ADVANCE_LP_RING();
6379out:
6380 return ret;
6381}
6382
6383static int intel_gen6_queue_flip(struct drm_device *dev,
6384 struct drm_crtc *crtc,
6385 struct drm_framebuffer *fb,
6386 struct drm_i915_gem_object *obj)
6387{
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 uint32_t pf, pipesrc;
6391 int ret;
6392
6393 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6394 if (ret)
6395 goto out;
6396
6397 ret = BEGIN_LP_RING(4);
6398 if (ret)
6399 goto out;
6400
6401 OUT_RING(MI_DISPLAY_FLIP |
6402 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6403 OUT_RING(fb->pitch | obj->tiling_mode);
6404 OUT_RING(obj->gtt_offset);
6405
6406 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6407 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6408 OUT_RING(pf | pipesrc);
6409 ADVANCE_LP_RING();
6410out:
6411 return ret;
6412}
6413
6414/*
6415 * On gen7 we currently use the blit ring because (in early silicon at least)
6416 * the render ring doesn't give us interrpts for page flip completion, which
6417 * means clients will hang after the first flip is queued. Fortunately the
6418 * blit ring generates interrupts properly, so use it instead.
6419 */
6420static int intel_gen7_queue_flip(struct drm_device *dev,
6421 struct drm_crtc *crtc,
6422 struct drm_framebuffer *fb,
6423 struct drm_i915_gem_object *obj)
6424{
6425 struct drm_i915_private *dev_priv = dev->dev_private;
6426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6428 int ret;
6429
6430 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6431 if (ret)
6432 goto out;
6433
6434 ret = intel_ring_begin(ring, 4);
6435 if (ret)
6436 goto out;
6437
6438 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6439 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6440 intel_ring_emit(ring, (obj->gtt_offset));
6441 intel_ring_emit(ring, (MI_NOOP));
6442 intel_ring_advance(ring);
6443out:
6444 return ret;
6445}
6446
6447static int intel_default_queue_flip(struct drm_device *dev,
6448 struct drm_crtc *crtc,
6449 struct drm_framebuffer *fb,
6450 struct drm_i915_gem_object *obj)
6451{
6452 return -ENODEV;
6453}
6454
6265static int intel_crtc_page_flip(struct drm_crtc *crtc, 6455static int intel_crtc_page_flip(struct drm_crtc *crtc,
6266 struct drm_framebuffer *fb, 6456 struct drm_framebuffer *fb,
6267 struct drm_pending_vblank_event *event) 6457 struct drm_pending_vblank_event *event)
@@ -6272,9 +6462,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6272 struct drm_i915_gem_object *obj; 6462 struct drm_i915_gem_object *obj;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 struct intel_unpin_work *work; 6464 struct intel_unpin_work *work;
6275 unsigned long flags, offset; 6465 unsigned long flags;
6276 int pipe = intel_crtc->pipe;
6277 u32 pf, pipesrc;
6278 int ret; 6466 int ret;
6279 6467
6280 work = kzalloc(sizeof *work, GFP_KERNEL); 6468 work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -6303,9 +6491,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6303 obj = intel_fb->obj; 6491 obj = intel_fb->obj;
6304 6492
6305 mutex_lock(&dev->struct_mutex); 6493 mutex_lock(&dev->struct_mutex);
6306 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6307 if (ret)
6308 goto cleanup_work;
6309 6494
6310 /* Reference the objects for the scheduled work. */ 6495 /* Reference the objects for the scheduled work. */
6311 drm_gem_object_reference(&work->old_fb_obj->base); 6496 drm_gem_object_reference(&work->old_fb_obj->base);
@@ -6317,91 +6502,18 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6317 if (ret) 6502 if (ret)
6318 goto cleanup_objs; 6503 goto cleanup_objs;
6319 6504
6320 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6321 u32 flip_mask;
6322
6323 /* Can't queue multiple flips, so wait for the previous
6324 * one to finish before executing the next.
6325 */
6326 ret = BEGIN_LP_RING(2);
6327 if (ret)
6328 goto cleanup_objs;
6329
6330 if (intel_crtc->plane)
6331 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6332 else
6333 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6334 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6335 OUT_RING(MI_NOOP);
6336 ADVANCE_LP_RING();
6337 }
6338
6339 work->pending_flip_obj = obj; 6505 work->pending_flip_obj = obj;
6340 6506
6341 work->enable_stall_check = true; 6507 work->enable_stall_check = true;
6342 6508
6343 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6344 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6345
6346 ret = BEGIN_LP_RING(4);
6347 if (ret)
6348 goto cleanup_objs;
6349
6350 /* Block clients from rendering to the new back buffer until 6509 /* Block clients from rendering to the new back buffer until
6351 * the flip occurs and the object is no longer visible. 6510 * the flip occurs and the object is no longer visible.
6352 */ 6511 */
6353 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 6512 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6354 6513
6355 switch (INTEL_INFO(dev)->gen) { 6514 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6356 case 2: 6515 if (ret)
6357 OUT_RING(MI_DISPLAY_FLIP | 6516 goto cleanup_pending;
6358 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6359 OUT_RING(fb->pitch);
6360 OUT_RING(obj->gtt_offset + offset);
6361 OUT_RING(MI_NOOP);
6362 break;
6363
6364 case 3:
6365 OUT_RING(MI_DISPLAY_FLIP_I915 |
6366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6367 OUT_RING(fb->pitch);
6368 OUT_RING(obj->gtt_offset + offset);
6369 OUT_RING(MI_NOOP);
6370 break;
6371
6372 case 4:
6373 case 5:
6374 /* i965+ uses the linear or tiled offsets from the
6375 * Display Registers (which do not change across a page-flip)
6376 * so we need only reprogram the base address.
6377 */
6378 OUT_RING(MI_DISPLAY_FLIP |
6379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6380 OUT_RING(fb->pitch);
6381 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6382
6383 /* XXX Enabling the panel-fitter across page-flip is so far
6384 * untested on non-native modes, so ignore it for now.
6385 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6386 */
6387 pf = 0;
6388 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6389 OUT_RING(pf | pipesrc);
6390 break;
6391
6392 case 6:
6393 case 7:
6394 OUT_RING(MI_DISPLAY_FLIP |
6395 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6396 OUT_RING(fb->pitch | obj->tiling_mode);
6397 OUT_RING(obj->gtt_offset);
6398
6399 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6400 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6401 OUT_RING(pf | pipesrc);
6402 break;
6403 }
6404 ADVANCE_LP_RING();
6405 6517
6406 mutex_unlock(&dev->struct_mutex); 6518 mutex_unlock(&dev->struct_mutex);
6407 6519
@@ -6409,10 +6521,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6409 6521
6410 return 0; 6522 return 0;
6411 6523
6524cleanup_pending:
6525 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6412cleanup_objs: 6526cleanup_objs:
6413 drm_gem_object_unreference(&work->old_fb_obj->base); 6527 drm_gem_object_unreference(&work->old_fb_obj->base);
6414 drm_gem_object_unreference(&obj->base); 6528 drm_gem_object_unreference(&obj->base);
6415cleanup_work:
6416 mutex_unlock(&dev->struct_mutex); 6529 mutex_unlock(&dev->struct_mutex);
6417 6530
6418 spin_lock_irqsave(&dev->event_lock, flags); 6531 spin_lock_irqsave(&dev->event_lock, flags);
@@ -7657,6 +7770,31 @@ static void intel_init_display(struct drm_device *dev)
7657 else 7770 else
7658 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7771 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7659 } 7772 }
7773
7774 /* Default just returns -ENODEV to indicate unsupported */
7775 dev_priv->display.queue_flip = intel_default_queue_flip;
7776
7777 switch (INTEL_INFO(dev)->gen) {
7778 case 2:
7779 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7780 break;
7781
7782 case 3:
7783 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7784 break;
7785
7786 case 4:
7787 case 5:
7788 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7789 break;
7790
7791 case 6:
7792 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7793 break;
7794 case 7:
7795 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7796 break;
7797 }
7660} 7798}
7661 7799
7662/* 7800/*
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d3b903bce7c..d98cee60b60 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -401,8 +401,7 @@ int intel_setup_gmbus(struct drm_device *dev)
401 bus->reg0 = i | GMBUS_RATE_100KHZ; 401 bus->reg0 = i | GMBUS_RATE_100KHZ;
402 402
403 /* XXX force bit banging until GMBUS is fully debugged */ 403 /* XXX force bit banging until GMBUS is fully debugged */
404 if (IS_GEN2(dev)) 404 bus->force_bit = intel_gpio_create(dev_priv, i);
405 bus->force_bit = intel_gpio_create(dev_priv, i);
406 } 405 }
407 406
408 intel_i2c_reset(dev_priv->dev); 407 intel_i2c_reset(dev_priv->dev);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index a670c006982..9e2959bc91c 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1409,6 +1409,11 @@ void intel_setup_overlay(struct drm_device *dev)
1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL); 1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1410 if (!overlay) 1410 if (!overlay)
1411 return; 1411 return;
1412
1413 mutex_lock(&dev->struct_mutex);
1414 if (WARN_ON(dev_priv->overlay))
1415 goto out_free;
1416
1412 overlay->dev = dev; 1417 overlay->dev = dev;
1413 1418
1414 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE); 1419 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
@@ -1448,7 +1453,7 @@ void intel_setup_overlay(struct drm_device *dev)
1448 1453
1449 regs = intel_overlay_map_regs(overlay); 1454 regs = intel_overlay_map_regs(overlay);
1450 if (!regs) 1455 if (!regs)
1451 goto out_free_bo; 1456 goto out_unpin_bo;
1452 1457
1453 memset(regs, 0, sizeof(struct overlay_registers)); 1458 memset(regs, 0, sizeof(struct overlay_registers));
1454 update_polyphase_filter(regs); 1459 update_polyphase_filter(regs);
@@ -1457,14 +1462,17 @@ void intel_setup_overlay(struct drm_device *dev)
1457 intel_overlay_unmap_regs(overlay, regs); 1462 intel_overlay_unmap_regs(overlay, regs);
1458 1463
1459 dev_priv->overlay = overlay; 1464 dev_priv->overlay = overlay;
1465 mutex_unlock(&dev->struct_mutex);
1460 DRM_INFO("initialized overlay support\n"); 1466 DRM_INFO("initialized overlay support\n");
1461 return; 1467 return;
1462 1468
1463out_unpin_bo: 1469out_unpin_bo:
1464 i915_gem_object_unpin(reg_bo); 1470 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1471 i915_gem_object_unpin(reg_bo);
1465out_free_bo: 1472out_free_bo:
1466 drm_gem_object_unreference(&reg_bo->base); 1473 drm_gem_object_unreference(&reg_bo->base);
1467out_free: 1474out_free:
1475 mutex_unlock(&dev->struct_mutex);
1468 kfree(overlay); 1476 kfree(overlay);
1469 return; 1477 return;
1470} 1478}
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index 1084fa4d261..54558a01969 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -195,29 +195,10 @@ extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
195 195
196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
197 197
198#if defined(__linux__) && defined(__alpha__)
199#define MGA_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
200#define MGA_ADDR(reg) (MGA_BASE(reg) + reg)
201
202#define MGA_DEREF(reg) (*(volatile u32 *)MGA_ADDR(reg))
203#define MGA_DEREF8(reg) (*(volatile u8 *)MGA_ADDR(reg))
204
205#define MGA_READ(reg) (_MGA_READ((u32 *)MGA_ADDR(reg)))
206#define MGA_READ8(reg) (_MGA_READ((u8 *)MGA_ADDR(reg)))
207#define MGA_WRITE(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF(reg) = val; } while (0)
208#define MGA_WRITE8(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8(reg) = val; } while (0)
209
210static inline u32 _MGA_READ(u32 *addr)
211{
212 DRM_MEMORYBARRIER();
213 return *(volatile u32 *)addr;
214}
215#else
216#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg)) 198#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
217#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg)) 199#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
218#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 200#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
219#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 201#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
220#endif
221 202
222#define DWGREG0 0x1c00 203#define DWGREG0 0x1c00
223#define DWGREG0_END 0x1dff 204#define DWGREG0_END 0x1dff
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index f0d459bb46e..525744d593c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -262,7 +262,6 @@ static bool nouveau_dsm_detect(void)
262 vga_count++; 262 vga_count++;
263 263
264 retval = nouveau_dsm_pci_probe(pdev); 264 retval = nouveau_dsm_pci_probe(pdev);
265 printk("ret val is %d\n", retval);
266 if (retval & NOUVEAU_DSM_HAS_MUX) 265 if (retval & NOUVEAU_DSM_HAS_MUX)
267 has_dsm |= 1; 266 has_dsm |= 1;
268 if (retval & NOUVEAU_DSM_HAS_OPT) 267 if (retval & NOUVEAU_DSM_HAS_OPT)
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 4b9f4493c9f..7347075ca5b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -339,11 +339,12 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
339 int ret; 339 int ret;
340 340
341 if (dev_priv->chipset < 0x84) { 341 if (dev_priv->chipset < 0x84) {
342 ret = RING_SPACE(chan, 3); 342 ret = RING_SPACE(chan, 4);
343 if (ret) 343 if (ret)
344 return ret; 344 return ret;
345 345
346 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 2); 346 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3);
347 OUT_RING (chan, NvSema);
347 OUT_RING (chan, sema->mem->start); 348 OUT_RING (chan, sema->mem->start);
348 OUT_RING (chan, 1); 349 OUT_RING (chan, 1);
349 } else 350 } else
@@ -351,10 +352,12 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
351 struct nouveau_vma *vma = &dev_priv->fence.bo->vma; 352 struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
352 u64 offset = vma->offset + sema->mem->start; 353 u64 offset = vma->offset + sema->mem->start;
353 354
354 ret = RING_SPACE(chan, 5); 355 ret = RING_SPACE(chan, 7);
355 if (ret) 356 if (ret)
356 return ret; 357 return ret;
357 358
359 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
360 OUT_RING (chan, chan->vram_handle);
358 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 361 BEGIN_RING(chan, NvSubSw, 0x0010, 4);
359 OUT_RING (chan, upper_32_bits(offset)); 362 OUT_RING (chan, upper_32_bits(offset));
360 OUT_RING (chan, lower_32_bits(offset)); 363 OUT_RING (chan, lower_32_bits(offset));
@@ -394,11 +397,12 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
394 int ret; 397 int ret;
395 398
396 if (dev_priv->chipset < 0x84) { 399 if (dev_priv->chipset < 0x84) {
397 ret = RING_SPACE(chan, 4); 400 ret = RING_SPACE(chan, 5);
398 if (ret) 401 if (ret)
399 return ret; 402 return ret;
400 403
401 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 1); 404 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2);
405 OUT_RING (chan, NvSema);
402 OUT_RING (chan, sema->mem->start); 406 OUT_RING (chan, sema->mem->start);
403 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1); 407 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
404 OUT_RING (chan, 1); 408 OUT_RING (chan, 1);
@@ -407,10 +411,12 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
407 struct nouveau_vma *vma = &dev_priv->fence.bo->vma; 411 struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
408 u64 offset = vma->offset + sema->mem->start; 412 u64 offset = vma->offset + sema->mem->start;
409 413
410 ret = RING_SPACE(chan, 5); 414 ret = RING_SPACE(chan, 7);
411 if (ret) 415 if (ret)
412 return ret; 416 return ret;
413 417
418 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
419 OUT_RING (chan, chan->vram_handle);
414 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 420 BEGIN_RING(chan, NvSubSw, 0x0010, 4);
415 OUT_RING (chan, upper_32_bits(offset)); 421 OUT_RING (chan, upper_32_bits(offset));
416 OUT_RING (chan, lower_32_bits(offset)); 422 OUT_RING (chan, lower_32_bits(offset));
@@ -504,22 +510,22 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
504 struct nouveau_gpuobj *obj = NULL; 510 struct nouveau_gpuobj *obj = NULL;
505 int ret; 511 int ret;
506 512
507 if (dev_priv->card_type >= NV_C0) 513 if (dev_priv->card_type < NV_C0) {
508 goto out_initialised; 514 /* Create an NV_SW object for various sync purposes */
515 ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
516 if (ret)
517 return ret;
509 518
510 /* Create an NV_SW object for various sync purposes */ 519 ret = RING_SPACE(chan, 2);
511 ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW); 520 if (ret)
512 if (ret) 521 return ret;
513 return ret;
514 522
515 /* we leave subchannel empty for nvc0 */ 523 BEGIN_RING(chan, NvSubSw, 0, 1);
516 ret = RING_SPACE(chan, 2); 524 OUT_RING (chan, NvSw);
517 if (ret) 525 FIRE_RING (chan);
518 return ret; 526 }
519 BEGIN_RING(chan, NvSubSw, 0, 1);
520 OUT_RING(chan, NvSw);
521 527
522 /* Create a DMA object for the shared cross-channel sync area. */ 528 /* Setup area of memory shared between all channels for x-chan sync */
523 if (USE_SEMA(dev) && dev_priv->chipset < 0x84) { 529 if (USE_SEMA(dev) && dev_priv->chipset < 0x84) {
524 struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem; 530 struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
525 531
@@ -534,23 +540,8 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
534 nouveau_gpuobj_ref(NULL, &obj); 540 nouveau_gpuobj_ref(NULL, &obj);
535 if (ret) 541 if (ret)
536 return ret; 542 return ret;
537
538 ret = RING_SPACE(chan, 2);
539 if (ret)
540 return ret;
541 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
542 OUT_RING(chan, NvSema);
543 } else {
544 ret = RING_SPACE(chan, 2);
545 if (ret)
546 return ret;
547 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
548 OUT_RING (chan, chan->vram_handle); /* whole VM */
549 } 543 }
550 544
551 FIRE_RING(chan);
552
553out_initialised:
554 INIT_LIST_HEAD(&chan->fence.pending); 545 INIT_LIST_HEAD(&chan->fence.pending);
555 spin_lock_init(&chan->fence.lock); 546 spin_lock_init(&chan->fence.lock);
556 atomic_set(&chan->fence.last_sequence_irq, 0); 547 atomic_set(&chan->fence.last_sequence_irq, 0);
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index 922fb6b664e..ef9dec0e6f8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -182,6 +182,11 @@ nouveau_perf_init(struct drm_device *dev)
182 entries = perf[2]; 182 entries = perf[2];
183 } 183 }
184 184
185 if (entries > NOUVEAU_PM_MAX_LEVEL) {
186 NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
187 entries = NOUVEAU_PM_MAX_LEVEL;
188 }
189
185 entry = perf + headerlen; 190 entry = perf + headerlen;
186 for (i = 0; i < entries; i++) { 191 for (i = 0; i < entries; i++) {
187 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; 192 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 80218887e0a..731acea865b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -371,7 +371,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
371 engine->vram.flags_valid = nv50_vram_flags_valid; 371 engine->vram.flags_valid = nv50_vram_flags_valid;
372 break; 372 break;
373 case 0xC0: 373 case 0xC0:
374 case 0xD0:
375 engine->instmem.init = nvc0_instmem_init; 374 engine->instmem.init = nvc0_instmem_init;
376 engine->instmem.takedown = nvc0_instmem_takedown; 375 engine->instmem.takedown = nvc0_instmem_takedown;
377 engine->instmem.suspend = nvc0_instmem_suspend; 376 engine->instmem.suspend = nvc0_instmem_suspend;
@@ -881,8 +880,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
881 880
882#ifdef __BIG_ENDIAN 881#ifdef __BIG_ENDIAN
883 /* Put the card in BE mode if it's not */ 882 /* Put the card in BE mode if it's not */
884 if (nv_rd32(dev, NV03_PMC_BOOT_1)) 883 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
885 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001); 884 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
886 885
887 DRM_MEMORYBARRIER(); 886 DRM_MEMORYBARRIER();
888#endif 887#endif
@@ -923,7 +922,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
923 dev_priv->card_type = NV_50; 922 dev_priv->card_type = NV_50;
924 break; 923 break;
925 case 0xc0: 924 case 0xc0:
926 case 0xd0:
927 dev_priv->card_type = NV_C0; 925 dev_priv->card_type = NV_C0;
928 break; 926 break;
929 default: 927 default:
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 74a3f687270..08da478ba54 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -409,7 +409,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
409 struct nouveau_channel *evo = dispc->sync; 409 struct nouveau_channel *evo = dispc->sync;
410 int ret; 410 int ret;
411 411
412 ret = RING_SPACE(evo, 24); 412 ret = RING_SPACE(evo, chan ? 25 : 27);
413 if (unlikely(ret)) 413 if (unlikely(ret))
414 return ret; 414 return ret;
415 415
@@ -458,8 +458,19 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
458 /* queue the flip on the crtc's "display sync" channel */ 458 /* queue the flip on the crtc's "display sync" channel */
459 BEGIN_RING(evo, 0, 0x0100, 1); 459 BEGIN_RING(evo, 0, 0x0100, 1);
460 OUT_RING (evo, 0xfffe0000); 460 OUT_RING (evo, 0xfffe0000);
461 BEGIN_RING(evo, 0, 0x0084, 5); 461 if (chan) {
462 OUT_RING (evo, chan ? 0x00000100 : 0x00000010); 462 BEGIN_RING(evo, 0, 0x0084, 1);
463 OUT_RING (evo, 0x00000100);
464 } else {
465 BEGIN_RING(evo, 0, 0x0084, 1);
466 OUT_RING (evo, 0x00000010);
467 /* allows gamma somehow, PDISP will bitch at you if
468 * you don't wait for vblank before changing this..
469 */
470 BEGIN_RING(evo, 0, 0x00e0, 1);
471 OUT_RING (evo, 0x40000000);
472 }
473 BEGIN_RING(evo, 0, 0x0088, 4);
463 OUT_RING (evo, dispc->sem.offset); 474 OUT_RING (evo, dispc->sem.offset);
464 OUT_RING (evo, 0xf00d0000 | dispc->sem.value); 475 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
465 OUT_RING (evo, 0x74b1e000); 476 OUT_RING (evo, 0x74b1e000);
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 49611e2365d..1b50ad8919d 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -1200,6 +1200,7 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1200#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1200#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1201#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1201#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1202#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1202#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1203#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1203 1204
1204// ucConfig 1205// ucConfig
1205#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1206#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 84a69e7fa11..9541995e4b2 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -671,6 +671,13 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
671 DISPPLL_CONFIG_DUAL_LINK; 671 DISPPLL_CONFIG_DUAL_LINK;
672 } 672 }
673 } 673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
674 atom_execute_table(rdev->mode_info.atom_context, 681 atom_execute_table(rdev->mode_info.atom_context,
675 index, (uint32_t *)&args); 682 index, (uint32_t *)&args);
676 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 98ea597bc76..660f96401a0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -88,7 +88,8 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
88/* get temperature in millidegrees */ 88/* get temperature in millidegrees */
89int evergreen_get_temp(struct radeon_device *rdev) 89int evergreen_get_temp(struct radeon_device *rdev)
90{ 90{
91 u32 temp, toffset, actual_temp = 0; 91 u32 temp, toffset;
92 int actual_temp = 0;
92 93
93 if (rdev->family == CHIP_JUNIPER) { 94 if (rdev->family == CHIP_JUNIPER) {
94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 95 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
@@ -139,11 +140,17 @@ void evergreen_pm_misc(struct radeon_device *rdev)
139 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
140 141
141 if (voltage->type == VOLTAGE_SW) { 142 if (voltage->type == VOLTAGE_SW) {
143 /* 0xff01 is a flag rather then an actual voltage */
144 if (voltage->voltage == 0xff01)
145 return;
142 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 146 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
143 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 147 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
144 rdev->pm.current_vddc = voltage->voltage; 148 rdev->pm.current_vddc = voltage->voltage;
145 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 149 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
146 } 150 }
151 /* 0xff01 is a flag rather then an actual voltage */
152 if (voltage->vddci == 0xff01)
153 return;
147 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 154 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
148 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 155 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
149 rdev->pm.current_vddci = voltage->vddci; 156 rdev->pm.current_vddci = voltage->vddci;
@@ -978,17 +985,19 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
978{ 985{
979 save->vga_control[0] = RREG32(D1VGA_CONTROL); 986 save->vga_control[0] = RREG32(D1VGA_CONTROL);
980 save->vga_control[1] = RREG32(D2VGA_CONTROL); 987 save->vga_control[1] = RREG32(D2VGA_CONTROL);
981 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
982 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
983 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
984 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
985 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
986 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
987 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
988 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
989 if (!(rdev->flags & RADEON_IS_IGP)) { 992 if (rdev->num_crtc >= 4) {
993 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
994 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
990 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
991 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
997 }
998 if (rdev->num_crtc >= 6) {
999 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1000 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
992 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
993 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
994 } 1003 }
@@ -997,35 +1006,45 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
997 WREG32(VGA_RENDER_CONTROL, 0); 1006 WREG32(VGA_RENDER_CONTROL, 0);
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1000 if (!(rdev->flags & RADEON_IS_IGP)) { 1009 if (rdev->num_crtc >= 4) {
1001 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1002 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1012 }
1013 if (rdev->num_crtc >= 6) {
1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1005 } 1016 }
1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1007 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1008 if (!(rdev->flags & RADEON_IS_IGP)) { 1019 if (rdev->num_crtc >= 4) {
1009 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1010 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1021 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1022 }
1023 if (rdev->num_crtc >= 6) {
1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013 } 1026 }
1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1016 if (!(rdev->flags & RADEON_IS_IGP)) { 1029 if (rdev->num_crtc >= 4) {
1017 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1018 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1032 }
1033 if (rdev->num_crtc >= 6) {
1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1021 } 1036 }
1022 1037
1023 WREG32(D1VGA_CONTROL, 0); 1038 WREG32(D1VGA_CONTROL, 0);
1024 WREG32(D2VGA_CONTROL, 0); 1039 WREG32(D2VGA_CONTROL, 0);
1025 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1040 if (rdev->num_crtc >= 4) {
1026 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1041 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1027 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1042 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1028 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1043 }
1044 if (rdev->num_crtc >= 6) {
1045 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1046 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1047 }
1029} 1048}
1030 1049
1031void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1050void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1048,7 +1067,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start); 1068 (u32)rdev->mc.vram_start);
1050 1069
1051 if (!(rdev->flags & RADEON_IS_IGP)) { 1070 if (rdev->num_crtc >= 4) {
1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1053 upper_32_bits(rdev->mc.vram_start)); 1072 upper_32_bits(rdev->mc.vram_start));
1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
@@ -1066,7 +1085,8 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1066 (u32)rdev->mc.vram_start); 1085 (u32)rdev->mc.vram_start);
1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1068 (u32)rdev->mc.vram_start); 1087 (u32)rdev->mc.vram_start);
1069 1088 }
1089 if (rdev->num_crtc >= 6) {
1070 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1071 upper_32_bits(rdev->mc.vram_start)); 1091 upper_32_bits(rdev->mc.vram_start));
1072 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
@@ -1094,31 +1114,41 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1094 /* Restore video state */ 1114 /* Restore video state */
1095 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1115 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1096 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1116 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1097 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1117 if (rdev->num_crtc >= 4) {
1098 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1118 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1099 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1119 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1100 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1120 }
1121 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1123 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1124 }
1101 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1103 if (!(rdev->flags & RADEON_IS_IGP)) { 1127 if (rdev->num_crtc >= 4) {
1104 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1105 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1130 }
1131 if (rdev->num_crtc >= 6) {
1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1108 } 1134 }
1109 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1110 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1111 if (!(rdev->flags & RADEON_IS_IGP)) { 1137 if (rdev->num_crtc >= 4) {
1112 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1113 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1140 }
1141 if (rdev->num_crtc >= 6) {
1114 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1115 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1116 } 1144 }
1117 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1119 if (!(rdev->flags & RADEON_IS_IGP)) { 1147 if (rdev->num_crtc >= 4) {
1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1150 }
1151 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1123 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1124 } 1154 }
@@ -2006,9 +2036,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2006 rdev->config.evergreen.tile_config |= (3 << 0); 2036 rdev->config.evergreen.tile_config |= (3 << 0);
2007 break; 2037 break;
2008 } 2038 }
2009 /* num banks is 8 on all fusion asics */ 2039 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2010 if (rdev->flags & RADEON_IS_IGP) 2040 if (rdev->flags & RADEON_IS_IGP)
2011 rdev->config.evergreen.tile_config |= 8 << 4; 2041 rdev->config.evergreen.tile_config |= 1 << 4;
2012 else 2042 else
2013 rdev->config.evergreen.tile_config |= 2043 rdev->config.evergreen.tile_config |=
2014 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 2044 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
@@ -2241,7 +2271,10 @@ int evergreen_mc_init(struct radeon_device *rdev)
2241 2271
2242 /* Get VRAM informations */ 2272 /* Get VRAM informations */
2243 rdev->mc.vram_is_ddr = true; 2273 rdev->mc.vram_is_ddr = true;
2244 tmp = RREG32(MC_ARB_RAMCFG); 2274 if (rdev->flags & RADEON_IS_IGP)
2275 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2276 else
2277 tmp = RREG32(MC_ARB_RAMCFG);
2245 if (tmp & CHANSIZE_OVERRIDE) { 2278 if (tmp & CHANSIZE_OVERRIDE) {
2246 chansize = 16; 2279 chansize = 16;
2247 } else if (tmp & CHANSIZE_MASK) { 2280 } else if (tmp & CHANSIZE_MASK) {
@@ -2407,18 +2440,22 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2407 WREG32(GRBM_INT_CNTL, 0); 2440 WREG32(GRBM_INT_CNTL, 0);
2408 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2409 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2410 if (!(rdev->flags & RADEON_IS_IGP)) { 2443 if (rdev->num_crtc >= 4) {
2411 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2412 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2446 }
2447 if (rdev->num_crtc >= 6) {
2413 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2448 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2414 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2449 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2415 } 2450 }
2416 2451
2417 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2418 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2419 if (!(rdev->flags & RADEON_IS_IGP)) { 2454 if (rdev->num_crtc >= 4) {
2420 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2421 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2456 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2457 }
2458 if (rdev->num_crtc >= 6) {
2422 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2459 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2423 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2460 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2424 } 2461 }
@@ -2537,19 +2574,25 @@ int evergreen_irq_set(struct radeon_device *rdev)
2537 2574
2538 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2575 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2539 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2576 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2540 if (!(rdev->flags & RADEON_IS_IGP)) { 2577 if (rdev->num_crtc >= 4) {
2541 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2578 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2542 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2579 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2580 }
2581 if (rdev->num_crtc >= 6) {
2543 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2582 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2544 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2583 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2545 } 2584 }
2546 2585
2547 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2586 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2549 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2588 if (rdev->num_crtc >= 4) {
2550 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2589 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2551 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2590 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2591 }
2592 if (rdev->num_crtc >= 6) {
2593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2595 }
2553 2596
2554 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2597 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2555 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2598 WREG32(DC_HPD2_INT_CONTROL, hpd2);
@@ -2573,53 +2616,57 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
2573 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2616 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2574 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2617 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2575 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2618 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2576 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2619 if (rdev->num_crtc >= 4) {
2577 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2620 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2578 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2621 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2579 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2622 }
2623 if (rdev->num_crtc >= 6) {
2624 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2625 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2626 }
2580 2627
2581 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2628 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2582 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2583 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2630 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2584 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2585 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2586 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2587 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2588 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2589 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2590 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2591 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2592 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2593
2594 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2632 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2595 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2596 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2634 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2597 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2598
2599 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2600 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2601 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2602 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2603 2640
2604 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2641 if (rdev->num_crtc >= 4) {
2605 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2642 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2643 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2607 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2644 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2608 2645 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2609 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2610 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2647 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2611 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2612 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2649 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2613 2650 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2614 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2651 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2615 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2616 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2653 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2617 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2654 }
2618 2655
2619 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2656 if (rdev->num_crtc >= 6) {
2620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2657 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2621 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2622 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2659 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2661 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2669 }
2623 2670
2624 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2671 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2625 tmp = RREG32(DC_HPD1_INT_CONTROL); 2672 tmp = RREG32(DC_HPD1_INT_CONTROL);
@@ -2694,28 +2741,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2694 2741
2695int evergreen_irq_process(struct radeon_device *rdev) 2742int evergreen_irq_process(struct radeon_device *rdev)
2696{ 2743{
2697 u32 wptr = evergreen_get_ih_wptr(rdev); 2744 u32 wptr;
2698 u32 rptr = rdev->ih.rptr; 2745 u32 rptr;
2699 u32 src_id, src_data; 2746 u32 src_id, src_data;
2700 u32 ring_index; 2747 u32 ring_index;
2701 unsigned long flags; 2748 unsigned long flags;
2702 bool queue_hotplug = false; 2749 bool queue_hotplug = false;
2703 2750
2704 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2751 if (!rdev->ih.enabled || rdev->shutdown)
2705 if (!rdev->ih.enabled)
2706 return IRQ_NONE; 2752 return IRQ_NONE;
2707 2753
2708 spin_lock_irqsave(&rdev->ih.lock, flags); 2754 wptr = evergreen_get_ih_wptr(rdev);
2755 rptr = rdev->ih.rptr;
2756 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2709 2757
2758 spin_lock_irqsave(&rdev->ih.lock, flags);
2710 if (rptr == wptr) { 2759 if (rptr == wptr) {
2711 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2760 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2712 return IRQ_NONE; 2761 return IRQ_NONE;
2713 } 2762 }
2714 if (rdev->shutdown) {
2715 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2716 return IRQ_NONE;
2717 }
2718
2719restart_ih: 2763restart_ih:
2720 /* display interrupts */ 2764 /* display interrupts */
2721 evergreen_irq_ack(rdev); 2765 evergreen_irq_ack(rdev);
@@ -2944,7 +2988,7 @@ restart_ih:
2944 radeon_fence_process(rdev); 2988 radeon_fence_process(rdev);
2945 break; 2989 break;
2946 case 233: /* GUI IDLE */ 2990 case 233: /* GUI IDLE */
2947 DRM_DEBUG("IH: CP EOP\n"); 2991 DRM_DEBUG("IH: GUI idle\n");
2948 rdev->pm.gui_idle = true; 2992 rdev->pm.gui_idle = true;
2949 wake_up(&rdev->irq.idle_queue); 2993 wake_up(&rdev->irq.idle_queue);
2950 break; 2994 break;
@@ -3230,6 +3274,7 @@ void evergreen_fini(struct radeon_device *rdev)
3230 r700_cp_fini(rdev); 3274 r700_cp_fini(rdev);
3231 r600_irq_fini(rdev); 3275 r600_irq_fini(rdev);
3232 radeon_wb_fini(rdev); 3276 radeon_wb_fini(rdev);
3277 radeon_ib_pool_fini(rdev);
3233 radeon_irq_kms_fini(rdev); 3278 radeon_irq_kms_fini(rdev);
3234 evergreen_pcie_gart_fini(rdev); 3279 evergreen_pcie_gart_fini(rdev);
3235 radeon_gem_fini(rdev); 3280 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 1636e344982..b7b2714f0b3 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -466,7 +466,7 @@
466#define IH_RB_WPTR_ADDR_LO 0x3e14 466#define IH_RB_WPTR_ADDR_LO 0x3e14
467#define IH_CNTL 0x3e18 467#define IH_CNTL 0x3e18
468# define ENABLE_INTR (1 << 0) 468# define ENABLE_INTR (1 << 0)
469# define IH_MC_SWAP(x) ((x) << 2) 469# define IH_MC_SWAP(x) ((x) << 1)
470# define IH_MC_SWAP_NONE 0 470# define IH_MC_SWAP_NONE 0
471# define IH_MC_SWAP_16BIT 1 471# define IH_MC_SWAP_16BIT 1
472# define IH_MC_SWAP_32BIT 2 472# define IH_MC_SWAP_32BIT 2
@@ -547,7 +547,7 @@
547# define LB_D5_VBLANK_INTERRUPT (1 << 3) 547# define LB_D5_VBLANK_INTERRUPT (1 << 3)
548# define DC_HPD5_INTERRUPT (1 << 17) 548# define DC_HPD5_INTERRUPT (1 << 17)
549# define DC_HPD5_RX_INTERRUPT (1 << 18) 549# define DC_HPD5_RX_INTERRUPT (1 << 18)
550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
551# define LB_D6_VLINE_INTERRUPT (1 << 2) 551# define LB_D6_VLINE_INTERRUPT (1 << 2)
552# define LB_D6_VBLANK_INTERRUPT (1 << 3) 552# define LB_D6_VBLANK_INTERRUPT (1 << 3)
553# define DC_HPD6_INTERRUPT (1 << 17) 553# define DC_HPD6_INTERRUPT (1 << 17)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 16caafeadf5..559dbd41290 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1581,6 +1581,7 @@ void cayman_fini(struct radeon_device *rdev)
1581 cayman_cp_fini(rdev); 1581 cayman_cp_fini(rdev);
1582 r600_irq_fini(rdev); 1582 r600_irq_fini(rdev);
1583 radeon_wb_fini(rdev); 1583 radeon_wb_fini(rdev);
1584 radeon_ib_pool_fini(rdev);
1584 radeon_irq_kms_fini(rdev); 1585 radeon_irq_kms_fini(rdev);
1585 cayman_pcie_gart_fini(rdev); 1586 cayman_pcie_gart_fini(rdev);
1586 radeon_gem_fini(rdev); 1587 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 9736746da2d..4672869cdb2 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -320,7 +320,7 @@
320#define CGTS_USER_TCC_DISABLE 0x914C 320#define CGTS_USER_TCC_DISABLE 0x914C
321#define TCC_DISABLE_MASK 0xFFFF0000 321#define TCC_DISABLE_MASK 0xFFFF0000
322#define TCC_DISABLE_SHIFT 16 322#define TCC_DISABLE_SHIFT 16
323#define CGTS_SM_CTRL_REG 0x915C 323#define CGTS_SM_CTRL_REG 0x9150
324#define OVERRIDE (1 << 21) 324#define OVERRIDE (1 << 21)
325 325
326#define TA_CNTL_AUX 0x9508 326#define TA_CNTL_AUX 0x9508
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 2fef9de7f36..686f9dc5d4b 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -63,7 +63,7 @@ struct r100_cs_track {
63 unsigned num_arrays; 63 unsigned num_arrays;
64 unsigned max_indx; 64 unsigned max_indx;
65 unsigned color_channel_mask; 65 unsigned color_channel_mask;
66 struct r100_cs_track_array arrays[11]; 66 struct r100_cs_track_array arrays[16];
67 struct r100_cs_track_cb cb[R300_MAX_CB]; 67 struct r100_cs_track_cb cb[R300_MAX_CB];
68 struct r100_cs_track_cb zb; 68 struct r100_cs_track_cb zb;
69 struct r100_cs_track_cb aa; 69 struct r100_cs_track_cb aa;
@@ -146,6 +146,12 @@ static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
146 ib = p->ib->ptr; 146 ib = p->ib->ptr;
147 track = (struct r100_cs_track *)p->track; 147 track = (struct r100_cs_track *)p->track;
148 c = radeon_get_ib_value(p, idx++) & 0x1F; 148 c = radeon_get_ib_value(p, idx++) & 0x1F;
149 if (c > 16) {
150 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
151 pkt->opcode);
152 r100_cs_dump_packet(p, pkt);
153 return -EINVAL;
154 }
149 track->num_arrays = c; 155 track->num_arrays = c;
150 for (i = 0; i < (c - 1); i+=2, idx+=3) { 156 for (i = 0; i < (c - 1); i+=2, idx+=3) {
151 r = r100_cs_packet_next_reloc(p, &reloc); 157 r = r100_cs_packet_next_reloc(p, &reloc);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d74d4d71437..bc54b26cb32 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -590,6 +590,9 @@ void r600_pm_misc(struct radeon_device *rdev)
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591 591
592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
593 if (voltage->voltage != rdev->pm.current_vddc) { 596 if (voltage->voltage != rdev->pm.current_vddc) {
594 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
595 rdev->pm.current_vddc = voltage->voltage; 598 rdev->pm.current_vddc = voltage->voltage;
@@ -2625,6 +2628,7 @@ void r600_fini(struct radeon_device *rdev)
2625 r600_cp_fini(rdev); 2628 r600_cp_fini(rdev);
2626 r600_irq_fini(rdev); 2629 r600_irq_fini(rdev);
2627 radeon_wb_fini(rdev); 2630 radeon_wb_fini(rdev);
2631 radeon_ib_pool_fini(rdev);
2628 radeon_irq_kms_fini(rdev); 2632 radeon_irq_kms_fini(rdev);
2629 r600_pcie_gart_fini(rdev); 2633 r600_pcie_gart_fini(rdev);
2630 radeon_agp_fini(rdev); 2634 radeon_agp_fini(rdev);
@@ -3294,27 +3298,26 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3294 3298
3295int r600_irq_process(struct radeon_device *rdev) 3299int r600_irq_process(struct radeon_device *rdev)
3296{ 3300{
3297 u32 wptr = r600_get_ih_wptr(rdev); 3301 u32 wptr;
3298 u32 rptr = rdev->ih.rptr; 3302 u32 rptr;
3299 u32 src_id, src_data; 3303 u32 src_id, src_data;
3300 u32 ring_index; 3304 u32 ring_index;
3301 unsigned long flags; 3305 unsigned long flags;
3302 bool queue_hotplug = false; 3306 bool queue_hotplug = false;
3303 3307
3304 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3308 if (!rdev->ih.enabled || rdev->shutdown)
3305 if (!rdev->ih.enabled)
3306 return IRQ_NONE; 3309 return IRQ_NONE;
3307 3310
3311 wptr = r600_get_ih_wptr(rdev);
3312 rptr = rdev->ih.rptr;
3313 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3314
3308 spin_lock_irqsave(&rdev->ih.lock, flags); 3315 spin_lock_irqsave(&rdev->ih.lock, flags);
3309 3316
3310 if (rptr == wptr) { 3317 if (rptr == wptr) {
3311 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3318 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3312 return IRQ_NONE; 3319 return IRQ_NONE;
3313 } 3320 }
3314 if (rdev->shutdown) {
3315 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3316 return IRQ_NONE;
3317 }
3318 3321
3319restart_ih: 3322restart_ih:
3320 /* display interrupts */ 3323 /* display interrupts */
@@ -3444,7 +3447,7 @@ restart_ih:
3444 radeon_fence_process(rdev); 3447 radeon_fence_process(rdev);
3445 break; 3448 break;
3446 case 233: /* GUI IDLE */ 3449 case 233: /* GUI IDLE */
3447 DRM_DEBUG("IH: CP EOP\n"); 3450 DRM_DEBUG("IH: GUI idle\n");
3448 rdev->pm.gui_idle = true; 3451 rdev->pm.gui_idle = true;
3449 wake_up(&rdev->irq.idle_queue); 3452 wake_up(&rdev->irq.idle_queue);
3450 break; 3453 break;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index f140a0d5cb5..0245ae6c204 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -536,7 +536,7 @@
536#define IH_RB_WPTR_ADDR_LO 0x3e14 536#define IH_RB_WPTR_ADDR_LO 0x3e14
537#define IH_CNTL 0x3e18 537#define IH_CNTL 0x3e18
538# define ENABLE_INTR (1 << 0) 538# define ENABLE_INTR (1 << 0)
539# define IH_MC_SWAP(x) ((x) << 2) 539# define IH_MC_SWAP(x) ((x) << 1)
540# define IH_MC_SWAP_NONE 0 540# define IH_MC_SWAP_NONE 0
541# define IH_MC_SWAP_16BIT 1 541# define IH_MC_SWAP_16BIT 1
542# define IH_MC_SWAP_32BIT 2 542# define IH_MC_SWAP_32BIT 2
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ba643b57605..ef0e0e01691 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -165,6 +165,7 @@ struct radeon_clock {
165 uint32_t default_sclk; 165 uint32_t default_sclk;
166 uint32_t default_dispclk; 166 uint32_t default_dispclk;
167 uint32_t dp_extclk; 167 uint32_t dp_extclk;
168 uint32_t max_pixel_clock;
168}; 169};
169 170
170/* 171/*
@@ -178,6 +179,7 @@ void radeon_pm_resume(struct radeon_device *rdev);
178void radeon_combios_get_power_modes(struct radeon_device *rdev); 179void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev); 180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
181void rs690_pm_info(struct radeon_device *rdev); 183void rs690_pm_info(struct radeon_device *rdev);
182extern int rv6xx_get_temp(struct radeon_device *rdev); 184extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev); 185extern int rv770_get_temp(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 9bd162fc9b0..b2449629537 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -938,6 +938,13 @@ static struct radeon_asic cayman_asic = {
938int radeon_asic_init(struct radeon_device *rdev) 938int radeon_asic_init(struct radeon_device *rdev)
939{ 939{
940 radeon_register_accessor_init(rdev); 940 radeon_register_accessor_init(rdev);
941
942 /* set the number of crtcs */
943 if (rdev->flags & RADEON_SINGLE_CRTC)
944 rdev->num_crtc = 1;
945 else
946 rdev->num_crtc = 2;
947
941 switch (rdev->family) { 948 switch (rdev->family) {
942 case CHIP_R100: 949 case CHIP_R100:
943 case CHIP_RV100: 950 case CHIP_RV100:
@@ -1017,6 +1024,11 @@ int radeon_asic_init(struct radeon_device *rdev)
1017 case CHIP_JUNIPER: 1024 case CHIP_JUNIPER:
1018 case CHIP_CYPRESS: 1025 case CHIP_CYPRESS:
1019 case CHIP_HEMLOCK: 1026 case CHIP_HEMLOCK:
1027 /* set num crtcs */
1028 if (rdev->family == CHIP_CEDAR)
1029 rdev->num_crtc = 4;
1030 else
1031 rdev->num_crtc = 6;
1020 rdev->asic = &evergreen_asic; 1032 rdev->asic = &evergreen_asic;
1021 break; 1033 break;
1022 case CHIP_PALM: 1034 case CHIP_PALM:
@@ -1027,10 +1039,17 @@ int radeon_asic_init(struct radeon_device *rdev)
1027 case CHIP_BARTS: 1039 case CHIP_BARTS:
1028 case CHIP_TURKS: 1040 case CHIP_TURKS:
1029 case CHIP_CAICOS: 1041 case CHIP_CAICOS:
1042 /* set num crtcs */
1043 if (rdev->family == CHIP_CAICOS)
1044 rdev->num_crtc = 4;
1045 else
1046 rdev->num_crtc = 6;
1030 rdev->asic = &btc_asic; 1047 rdev->asic = &btc_asic;
1031 break; 1048 break;
1032 case CHIP_CAYMAN: 1049 case CHIP_CAYMAN:
1033 rdev->asic = &cayman_asic; 1050 rdev->asic = &cayman_asic;
1051 /* set num crtcs */
1052 rdev->num_crtc = 6;
1034 break; 1053 break;
1035 default: 1054 default:
1036 /* FIXME: not supported yet */ 1055 /* FIXME: not supported yet */
@@ -1042,18 +1061,6 @@ int radeon_asic_init(struct radeon_device *rdev)
1042 rdev->asic->set_memory_clock = NULL; 1061 rdev->asic->set_memory_clock = NULL;
1043 } 1062 }
1044 1063
1045 /* set the number of crtcs */
1046 if (rdev->flags & RADEON_SINGLE_CRTC)
1047 rdev->num_crtc = 1;
1048 else {
1049 if (ASIC_IS_DCE41(rdev))
1050 rdev->num_crtc = 2;
1051 else if (ASIC_IS_DCE4(rdev))
1052 rdev->num_crtc = 6;
1053 else
1054 rdev->num_crtc = 2;
1055 }
1056
1057 return 0; 1064 return 0;
1058} 1065}
1059 1066
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 90dfb2b8cf0..bf2b61584cd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1246,6 +1246,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1246 } 1246 }
1247 *dcpll = *p1pll; 1247 *dcpll = *p1pll;
1248 1248
1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
1249 return true; 1253 return true;
1250 } 1254 }
1251 1255
@@ -2316,6 +2320,14 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2316 le16_to_cpu(clock_info->r600.usVDDC); 2320 le16_to_cpu(clock_info->r600.usVDDC);
2317 } 2321 }
2318 2322
2323 /* patch up vddc if necessary */
2324 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2325 u16 vddc;
2326
2327 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2329 }
2330
2319 if (rdev->flags & RADEON_IS_IGP) { 2331 if (rdev->flags & RADEON_IS_IGP) {
2320 /* skip invalid modes */ 2332 /* skip invalid modes */
2321 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2333 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
@@ -2603,6 +2615,10 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2603 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2615 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2604 return; 2616 return;
2605 2617
2618 /* 0xff01 is a flag rather then an actual voltage */
2619 if (voltage_level == 0xff01)
2620 return;
2621
2606 switch (crev) { 2622 switch (crev) {
2607 case 1: 2623 case 1:
2608 args.v1.ucVoltageType = voltage_type; 2624 args.v1.ucVoltageType = voltage_type;
@@ -2622,7 +2638,35 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2623} 2639}
2624 2640
2641int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2642 u16 *voltage)
2643{
2644 union set_voltage args;
2645 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2646 u8 frev, crev;
2647
2648 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2649 return -EINVAL;
2625 2650
2651 switch (crev) {
2652 case 1:
2653 return -EINVAL;
2654 case 2:
2655 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2656 args.v2.ucVoltageMode = 0;
2657 args.v2.usVoltageLevel = 0;
2658
2659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2660
2661 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2662 break;
2663 default:
2664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669}
2626 2670
2627void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 2671void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2628{ 2672{
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 1aba85cad1a..3fc5fa1aefd 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -104,7 +104,7 @@ static bool radeon_read_bios(struct radeon_device *rdev)
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 105{
106 int ret; 106 int ret;
107 int size = 64 * 1024; 107 int size = 256 * 1024;
108 int i; 108 int i;
109 109
110 if (!radeon_atrm_supported(rdev->pdev)) 110 if (!radeon_atrm_supported(rdev->pdev))
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 5249af8931e..2d48e7a1474 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -117,7 +117,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2) 118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12; 119 p1pll->reference_div = 12;
120 p2pll->reference_div = p1pll->reference_div; 120 p2pll->reference_div = p1pll->reference_div;
121 121
122 /* These aren't in the device-tree */ 122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) { 123 if (rdev->family >= CHIP_R420) {
@@ -139,6 +139,8 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
139 p2pll->pll_out_min = 12500; 139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000; 140 p2pll->pll_out_max = 35000;
141 } 141 }
142 /* not sure what the max should be in all cases */
143 rdev->clock.max_pixel_clock = 35000;
142 144
143 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; 145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
144 spll->reference_div = mpll->reference_div = 146 spll->reference_div = mpll->reference_div =
@@ -151,7 +153,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
151 else 153 else
152 rdev->clock.default_sclk = 154 rdev->clock.default_sclk =
153 radeon_legacy_get_engine_clock(rdev); 155 radeon_legacy_get_engine_clock(rdev);
154 156
155 val = of_get_property(dp, "ATY,MCLK", NULL); 157 val = of_get_property(dp, "ATY,MCLK", NULL);
156 if (val && *val) 158 if (val && *val)
157 rdev->clock.default_mclk = (*val) / 10; 159 rdev->clock.default_mclk = (*val) / 10;
@@ -160,7 +162,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
160 radeon_legacy_get_memory_clock(rdev); 162 radeon_legacy_get_memory_clock(rdev);
161 163
162 DRM_INFO("Using device-tree clock info\n"); 164 DRM_INFO("Using device-tree clock info\n");
163 165
164 return true; 166 return true;
165} 167}
166#else 168#else
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 5b991f7c6e2..e4594676a07 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -866,6 +866,11 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
866 rdev->clock.default_sclk = sclk; 866 rdev->clock.default_sclk = sclk;
867 rdev->clock.default_mclk = mclk; 867 rdev->clock.default_mclk = mclk;
868 868
869 if (RBIOS32(pll_info + 0x16))
870 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
871 else
872 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
873
869 return true; 874 return true;
870 } 875 }
871 return false; 876 return false;
@@ -1548,10 +1553,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1548 (rdev->pdev->subsystem_device == 0x4a48)) { 1553 (rdev->pdev->subsystem_device == 0x4a48)) {
1549 /* Mac X800 */ 1554 /* Mac X800 */
1550 rdev->mode_info.connector_table = CT_MAC_X800; 1555 rdev->mode_info.connector_table = CT_MAC_X800;
1551 } else if ((rdev->pdev->device == 0x4150) && 1556 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1557 of_machine_is_compatible("PowerMac7,3")) &&
1558 (rdev->pdev->device == 0x4150) &&
1552 (rdev->pdev->subsystem_vendor == 0x1002) && 1559 (rdev->pdev->subsystem_vendor == 0x1002) &&
1553 (rdev->pdev->subsystem_device == 0x4150)) { 1560 (rdev->pdev->subsystem_device == 0x4150)) {
1554 /* Mac G5 9600 */ 1561 /* Mac G5 tower 9600 */
1555 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1562 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1556 } else 1563 } else
1557#endif /* CONFIG_PPC_PMAC */ 1564#endif /* CONFIG_PPC_PMAC */
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index ee1dccb3fec..cbfca3a24fd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -44,6 +44,8 @@ extern void
44radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 44radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
45 struct drm_connector *drm_connector); 45 struct drm_connector *drm_connector);
46 46
47bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
48
47void radeon_connector_hotplug(struct drm_connector *connector) 49void radeon_connector_hotplug(struct drm_connector *connector)
48{ 50{
49 struct drm_device *dev = connector->dev; 51 struct drm_device *dev = connector->dev;
@@ -626,8 +628,14 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
626static int radeon_vga_mode_valid(struct drm_connector *connector, 628static int radeon_vga_mode_valid(struct drm_connector *connector,
627 struct drm_display_mode *mode) 629 struct drm_display_mode *mode)
628{ 630{
631 struct drm_device *dev = connector->dev;
632 struct radeon_device *rdev = dev->dev_private;
633
629 /* XXX check mode bandwidth */ 634 /* XXX check mode bandwidth */
630 /* XXX verify against max DAC output frequency */ 635
636 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
637 return MODE_CLOCK_HIGH;
638
631 return MODE_OK; 639 return MODE_OK;
632} 640}
633 641
@@ -830,6 +838,13 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
830 if (!radeon_connector->edid) { 838 if (!radeon_connector->edid) {
831 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 839 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
832 drm_get_connector_name(connector)); 840 drm_get_connector_name(connector));
841 /* rs690 seems to have a problem with connectors not existing and always
842 * return a block of 0's. If we see this just stop polling on this output */
843 if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) && radeon_connector->base.null_edid_counter) {
844 ret = connector_status_disconnected;
845 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector));
846 radeon_connector->ddc_bus = NULL;
847 }
833 } else { 848 } else {
834 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 849 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
835 850
@@ -1015,6 +1030,11 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
1015 } else 1030 } else
1016 return MODE_CLOCK_HIGH; 1031 return MODE_CLOCK_HIGH;
1017 } 1032 }
1033
1034 /* check against the max pixel clock */
1035 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1036 return MODE_CLOCK_HIGH;
1037
1018 return MODE_OK; 1038 return MODE_OK;
1019} 1039}
1020 1040
@@ -1052,10 +1072,11 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1052{ 1072{
1053 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1073 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1054 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1074 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1075 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1055 int ret; 1076 int ret;
1056 1077
1057 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1078 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1058 struct drm_encoder *encoder; 1079 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1059 struct drm_display_mode *mode; 1080 struct drm_display_mode *mode;
1060 1081
1061 if (!radeon_dig_connector->edp_on) 1082 if (!radeon_dig_connector->edp_on)
@@ -1067,7 +1088,6 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1067 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1088 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1068 1089
1069 if (ret > 0) { 1090 if (ret > 0) {
1070 encoder = radeon_best_single_encoder(connector);
1071 if (encoder) { 1091 if (encoder) {
1072 radeon_fixup_lvds_native_mode(encoder, connector); 1092 radeon_fixup_lvds_native_mode(encoder, connector);
1073 /* add scaled modes */ 1093 /* add scaled modes */
@@ -1091,8 +1111,14 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1091 /* add scaled modes */ 1111 /* add scaled modes */
1092 radeon_add_common_modes(encoder, connector); 1112 radeon_add_common_modes(encoder, connector);
1093 } 1113 }
1094 } else 1114 } else {
1115 /* need to setup ddc on the bridge */
1116 if (radeon_connector_encoder_is_dp_bridge(connector)) {
1117 if (encoder)
1118 radeon_atom_ext_encoder_setup_ddc(encoder);
1119 }
1095 ret = radeon_ddc_get_modes(radeon_connector); 1120 ret = radeon_ddc_get_modes(radeon_connector);
1121 }
1096 1122
1097 return ret; 1123 return ret;
1098} 1124}
@@ -1176,14 +1202,15 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1176 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1202 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1177 enum drm_connector_status ret = connector_status_disconnected; 1203 enum drm_connector_status ret = connector_status_disconnected;
1178 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1204 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1205 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1179 1206
1180 if (radeon_connector->edid) { 1207 if (radeon_connector->edid) {
1181 kfree(radeon_connector->edid); 1208 kfree(radeon_connector->edid);
1182 radeon_connector->edid = NULL; 1209 radeon_connector->edid = NULL;
1183 } 1210 }
1184 1211
1185 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1212 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1186 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 1213 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1187 if (encoder) { 1214 if (encoder) {
1188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1189 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 1216 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
@@ -1203,6 +1230,11 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1203 atombios_set_edp_panel_power(connector, 1230 atombios_set_edp_panel_power(connector,
1204 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1231 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1205 } else { 1232 } else {
1233 /* need to setup ddc on the bridge */
1234 if (radeon_connector_encoder_is_dp_bridge(connector)) {
1235 if (encoder)
1236 radeon_atom_ext_encoder_setup_ddc(encoder);
1237 }
1206 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); 1238 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1207 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { 1239 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1208 ret = connector_status_connected; 1240 ret = connector_status_connected;
@@ -1217,6 +1249,16 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1217 ret = connector_status_connected; 1249 ret = connector_status_connected;
1218 } 1250 }
1219 } 1251 }
1252
1253 if ((ret == connector_status_disconnected) &&
1254 radeon_connector->dac_load_detect) {
1255 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1256 struct drm_encoder_helper_funcs *encoder_funcs;
1257 if (encoder) {
1258 encoder_funcs = encoder->helper_private;
1259 ret = encoder_funcs->detect(encoder, connector);
1260 }
1261 }
1220 } 1262 }
1221 1263
1222 radeon_connector_update_scratch_regs(connector, ret); 1264 radeon_connector_update_scratch_regs(connector, ret);
@@ -1231,7 +1273,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1231 1273
1232 /* XXX check mode bandwidth */ 1274 /* XXX check mode bandwidth */
1233 1275
1234 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1276 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1277 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1235 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 1278 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1236 1279
1237 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1280 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
@@ -1241,7 +1284,7 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1242 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 1285 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1243 1286
1244 /* AVIVO hardware supports downscaling modes larger than the panel 1287 /* AVIVO hardware supports downscaling modes larger than the panel
1245 * to the panel size, but I'm not sure this is desirable. 1288 * to the panel size, but I'm not sure this is desirable.
1246 */ 1289 */
1247 if ((mode->hdisplay > native_mode->hdisplay) || 1290 if ((mode->hdisplay > native_mode->hdisplay) ||
@@ -1390,6 +1433,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1390 default: 1433 default:
1391 connector->interlace_allowed = true; 1434 connector->interlace_allowed = true;
1392 connector->doublescan_allowed = true; 1435 connector->doublescan_allowed = true;
1436 radeon_connector->dac_load_detect = true;
1437 drm_connector_attach_property(&radeon_connector->base,
1438 rdev->mode_info.load_detect_property,
1439 1);
1393 break; 1440 break;
1394 case DRM_MODE_CONNECTOR_DVII: 1441 case DRM_MODE_CONNECTOR_DVII:
1395 case DRM_MODE_CONNECTOR_DVID: 1442 case DRM_MODE_CONNECTOR_DVID:
@@ -1411,6 +1458,12 @@ radeon_add_atom_connector(struct drm_device *dev,
1411 connector->doublescan_allowed = true; 1458 connector->doublescan_allowed = true;
1412 else 1459 else
1413 connector->doublescan_allowed = false; 1460 connector->doublescan_allowed = false;
1461 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1462 radeon_connector->dac_load_detect = true;
1463 drm_connector_attach_property(&radeon_connector->base,
1464 rdev->mode_info.load_detect_property,
1465 1);
1466 }
1414 break; 1467 break;
1415 case DRM_MODE_CONNECTOR_LVDS: 1468 case DRM_MODE_CONNECTOR_LVDS:
1416 case DRM_MODE_CONNECTOR_eDP: 1469 case DRM_MODE_CONNECTOR_eDP:
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e680501c78e..7cfaa7e2f3b 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -215,6 +215,8 @@ int radeon_wb_init(struct radeon_device *rdev)
215 return r; 215 return r;
216 } 216 }
217 217
218 /* clear wb memory */
219 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
218 /* disable event_write fences */ 220 /* disable event_write fences */
219 rdev->wb.use_event = false; 221 rdev->wb.use_event = false;
220 /* disabled via module param */ 222 /* disabled via module param */
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 03f124d626c..b293487e5aa 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -367,7 +367,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
367 } 367 }
368 368
369 if (ASIC_IS_DCE3(rdev) && 369 if (ASIC_IS_DCE3(rdev) &&
370 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { 370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 radeon_encoder_is_dp_bridge(encoder))) {
371 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
372 radeon_dp_set_link_config(connector, mode); 373 radeon_dp_set_link_config(connector, mode);
373 } 374 }
@@ -660,21 +661,16 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
660 if (radeon_encoder_is_dp_bridge(encoder)) 661 if (radeon_encoder_is_dp_bridge(encoder))
661 return ATOM_ENCODER_MODE_DP; 662 return ATOM_ENCODER_MODE_DP;
662 663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
663 connector = radeon_get_connector_for_encoder(encoder); 668 connector = radeon_get_connector_for_encoder(encoder);
664 if (!connector) { 669 /* if we don't have an active device yet, just use one of
665 switch (radeon_encoder->encoder_id) { 670 * the connectors tied to the encoder.
666 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 671 */
667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 672 if (!connector)
668 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 673 connector = radeon_get_connector_for_encoder_init(encoder);
669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
670 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
671 return ATOM_ENCODER_MODE_DVI;
672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
674 default:
675 return ATOM_ENCODER_MODE_CRT;
676 }
677 }
678 radeon_connector = to_radeon_connector(connector); 674 radeon_connector = to_radeon_connector(connector);
679 675
680 switch (connector->connector_type) { 676 switch (connector->connector_type) {
@@ -1094,9 +1090,10 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1094 break; 1090 break;
1095 } 1091 }
1096 1092
1097 if (is_dp) 1093 if (is_dp) {
1098 args.v2.acConfig.fCoherentMode = 1; 1094 args.v2.acConfig.fCoherentMode = 1;
1099 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1100 if (dig->coherent_mode) 1097 if (dig->coherent_mode)
1101 args.v2.acConfig.fCoherentMode = 1; 1098 args.v2.acConfig.fCoherentMode = 1;
1102 if (radeon_encoder->pixel_clock > 165000) 1099 if (radeon_encoder->pixel_clock > 165000)
@@ -1435,7 +1432,11 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1435 if (is_dig) { 1432 if (is_dig) {
1436 switch (mode) { 1433 switch (mode) {
1437 case DRM_MODE_DPMS_ON: 1434 case DRM_MODE_DPMS_ON:
1438 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1438 else
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1439 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1440 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1441 1442
@@ -1526,26 +1527,29 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1526 } 1527 }
1527 1528
1528 if (ext_encoder) { 1529 if (ext_encoder) {
1529 int action;
1530
1531 switch (mode) { 1530 switch (mode) {
1532 case DRM_MODE_DPMS_ON: 1531 case DRM_MODE_DPMS_ON:
1533 default: 1532 default:
1534 if (ASIC_IS_DCE41(rdev)) 1533 if (ASIC_IS_DCE41(rdev)) {
1535 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; 1534 atombios_external_encoder_setup(encoder, ext_encoder,
1536 else 1535 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1537 action = ATOM_ENABLE; 1536 atombios_external_encoder_setup(encoder, ext_encoder,
1537 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1538 } else
1539 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1538 break; 1540 break;
1539 case DRM_MODE_DPMS_STANDBY: 1541 case DRM_MODE_DPMS_STANDBY:
1540 case DRM_MODE_DPMS_SUSPEND: 1542 case DRM_MODE_DPMS_SUSPEND:
1541 case DRM_MODE_DPMS_OFF: 1543 case DRM_MODE_DPMS_OFF:
1542 if (ASIC_IS_DCE41(rdev)) 1544 if (ASIC_IS_DCE41(rdev)) {
1543 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; 1545 atombios_external_encoder_setup(encoder, ext_encoder,
1544 else 1546 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1545 action = ATOM_DISABLE; 1547 atombios_external_encoder_setup(encoder, ext_encoder,
1548 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1549 } else
1550 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1546 break; 1551 break;
1547 } 1552 }
1548 atombios_external_encoder_setup(encoder, ext_encoder, action);
1549 } 1553 }
1550 1554
1551 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1555 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
@@ -2004,6 +2008,65 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
2004 return connector_status_disconnected; 2008 return connector_status_disconnected;
2005} 2009}
2006 2010
2011static enum drm_connector_status
2012radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2013{
2014 struct drm_device *dev = encoder->dev;
2015 struct radeon_device *rdev = dev->dev_private;
2016 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2017 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2018 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2019 u32 bios_0_scratch;
2020
2021 if (!ASIC_IS_DCE4(rdev))
2022 return connector_status_unknown;
2023
2024 if (!ext_encoder)
2025 return connector_status_unknown;
2026
2027 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2028 return connector_status_unknown;
2029
2030 /* load detect on the dp bridge */
2031 atombios_external_encoder_setup(encoder, ext_encoder,
2032 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2033
2034 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2035
2036 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2037 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2038 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2039 return connector_status_connected;
2040 }
2041 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2042 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2043 return connector_status_connected;
2044 }
2045 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2046 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2047 return connector_status_connected;
2048 }
2049 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2050 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2051 return connector_status_connected; /* CTV */
2052 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2053 return connector_status_connected; /* STV */
2054 }
2055 return connector_status_disconnected;
2056}
2057
2058void
2059radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2060{
2061 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2062
2063 if (ext_encoder)
2064 /* ddc_setup on the dp bridge */
2065 atombios_external_encoder_setup(encoder, ext_encoder,
2066 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2067
2068}
2069
2007static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2070static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2008{ 2071{
2009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2072 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -2167,7 +2230,7 @@ static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2167 .mode_set = radeon_atom_encoder_mode_set, 2230 .mode_set = radeon_atom_encoder_mode_set,
2168 .commit = radeon_atom_encoder_commit, 2231 .commit = radeon_atom_encoder_commit,
2169 .disable = radeon_atom_encoder_disable, 2232 .disable = radeon_atom_encoder_disable,
2170 /* no detect for TMDS/LVDS yet */ 2233 .detect = radeon_atom_dig_detect,
2171}; 2234};
2172 2235
2173static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2236static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 1f822943657..021d2b6b556 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -40,6 +40,35 @@
40#include "radeon.h" 40#include "radeon.h"
41#include "radeon_trace.h" 41#include "radeon_trace.h"
42 42
43static void radeon_fence_write(struct radeon_device *rdev, u32 seq)
44{
45 if (rdev->wb.enabled) {
46 u32 scratch_index;
47 if (rdev->wb.use_event)
48 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
49 else
50 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
51 rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);;
52 } else
53 WREG32(rdev->fence_drv.scratch_reg, seq);
54}
55
56static u32 radeon_fence_read(struct radeon_device *rdev)
57{
58 u32 seq;
59
60 if (rdev->wb.enabled) {
61 u32 scratch_index;
62 if (rdev->wb.use_event)
63 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
64 else
65 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
66 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
67 } else
68 seq = RREG32(rdev->fence_drv.scratch_reg);
69 return seq;
70}
71
43int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) 72int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
44{ 73{
45 unsigned long irq_flags; 74 unsigned long irq_flags;
@@ -50,12 +79,12 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
50 return 0; 79 return 0;
51 } 80 }
52 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); 81 fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
53 if (!rdev->cp.ready) { 82 if (!rdev->cp.ready)
54 /* FIXME: cp is not running assume everythings is done right 83 /* FIXME: cp is not running assume everythings is done right
55 * away 84 * away
56 */ 85 */
57 WREG32(rdev->fence_drv.scratch_reg, fence->seq); 86 radeon_fence_write(rdev, fence->seq);
58 } else 87 else
59 radeon_fence_ring_emit(rdev, fence); 88 radeon_fence_ring_emit(rdev, fence);
60 89
61 trace_radeon_fence_emit(rdev->ddev, fence->seq); 90 trace_radeon_fence_emit(rdev->ddev, fence->seq);
@@ -73,15 +102,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
73 bool wake = false; 102 bool wake = false;
74 unsigned long cjiffies; 103 unsigned long cjiffies;
75 104
76 if (rdev->wb.enabled) { 105 seq = radeon_fence_read(rdev);
77 u32 scratch_index;
78 if (rdev->wb.use_event)
79 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
80 else
81 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
82 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
83 } else
84 seq = RREG32(rdev->fence_drv.scratch_reg);
85 if (seq != rdev->fence_drv.last_seq) { 106 if (seq != rdev->fence_drv.last_seq) {
86 rdev->fence_drv.last_seq = seq; 107 rdev->fence_drv.last_seq = seq;
87 rdev->fence_drv.last_jiffies = jiffies; 108 rdev->fence_drv.last_jiffies = jiffies;
@@ -251,7 +272,7 @@ retry:
251 r = radeon_gpu_reset(rdev); 272 r = radeon_gpu_reset(rdev);
252 if (r) 273 if (r)
253 return r; 274 return r;
254 WREG32(rdev->fence_drv.scratch_reg, fence->seq); 275 radeon_fence_write(rdev, fence->seq);
255 rdev->gpu_lockup = false; 276 rdev->gpu_lockup = false;
256 } 277 }
257 timeout = RADEON_FENCE_JIFFIES_TIMEOUT; 278 timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
@@ -351,7 +372,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
351 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 372 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
352 return r; 373 return r;
353 } 374 }
354 WREG32(rdev->fence_drv.scratch_reg, 0); 375 radeon_fence_write(rdev, 0);
355 atomic_set(&rdev->fence_drv.seq, 0); 376 atomic_set(&rdev->fence_drv.seq, 0);
356 INIT_LIST_HEAD(&rdev->fence_drv.created); 377 INIT_LIST_HEAD(&rdev->fence_drv.created);
357 INIT_LIST_HEAD(&rdev->fence_drv.emited); 378 INIT_LIST_HEAD(&rdev->fence_drv.emited);
@@ -391,7 +412,7 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
391 struct radeon_fence *fence; 412 struct radeon_fence *fence;
392 413
393 seq_printf(m, "Last signaled fence 0x%08X\n", 414 seq_printf(m, "Last signaled fence 0x%08X\n",
394 RREG32(rdev->fence_drv.scratch_reg)); 415 radeon_fence_read(rdev));
395 if (!list_empty(&rdev->fence_drv.emited)) { 416 if (!list_empty(&rdev->fence_drv.emited)) {
396 fence = list_entry(rdev->fence_drv.emited.prev, 417 fence = list_entry(rdev->fence_drv.emited.prev,
397 struct radeon_fence, list); 418 struct radeon_fence, list);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 977a341266b..6df4e3cec0c 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -483,6 +483,8 @@ extern void radeon_atom_encoder_init(struct radeon_device *rdev);
483extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 483extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
484 int action, uint8_t lane_num, 484 int action, uint8_t lane_num,
485 uint8_t lane_set); 485 uint8_t lane_set);
486extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
487extern struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder);
486extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 488extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
487 u8 write_byte, u8 *read_byte); 489 u8 write_byte, u8 *read_byte);
488 490
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index ef8a5babe9f..4de51891aa6 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -105,6 +105,9 @@ void rv770_pm_misc(struct radeon_device *rdev)
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106 106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
108 if (voltage->voltage != rdev->pm.current_vddc) { 111 if (voltage->voltage != rdev->pm.current_vddc) {
109 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
110 rdev->pm.current_vddc = voltage->voltage; 113 rdev->pm.current_vddc = voltage->voltage;
@@ -572,6 +575,12 @@ static void rv770_program_channel_remap(struct radeon_device *rdev)
572 else 575 else
573 tcp_chan_steer = 0x00fac688; 576 tcp_chan_steer = 0x00fac688;
574 577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
575 WREG32(TCP_CHAN_STEER, tcp_chan_steer); 584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
576 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
577} 586}
@@ -1359,6 +1368,7 @@ void rv770_fini(struct radeon_device *rdev)
1359 r700_cp_fini(rdev); 1368 r700_cp_fini(rdev);
1360 r600_irq_fini(rdev); 1369 r600_irq_fini(rdev);
1361 radeon_wb_fini(rdev); 1370 radeon_wb_fini(rdev);
1371 radeon_ib_pool_fini(rdev);
1362 radeon_irq_kms_fini(rdev); 1372 radeon_irq_kms_fini(rdev);
1363 rv770_pcie_gart_fini(rdev); 1373 rv770_pcie_gart_fini(rdev);
1364 rv770_vram_scratch_fini(rdev); 1374 rv770_vram_scratch_fini(rdev);
diff --git a/drivers/gpu/drm/savage/savage_bci.c b/drivers/gpu/drm/savage/savage_bci.c
index bf5f83ea14f..cb1ee4e0050 100644
--- a/drivers/gpu/drm/savage/savage_bci.c
+++ b/drivers/gpu/drm/savage/savage_bci.c
@@ -647,9 +647,6 @@ int savage_driver_firstopen(struct drm_device *dev)
647 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 647 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
648 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, 648 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
649 &dev_priv->aperture); 649 &dev_priv->aperture);
650 if (ret)
651 return ret;
652
653 return ret; 650 return ret;
654} 651}
655 652
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 90e23e0bfad..58c271ebc0f 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -31,6 +31,7 @@
31#include <linux/sched.h> 31#include <linux/sched.h>
32#include <linux/highmem.h> 32#include <linux/highmem.h>
33#include <linux/pagemap.h> 33#include <linux/pagemap.h>
34#include <linux/shmem_fs.h>
34#include <linux/file.h> 35#include <linux/file.h>
35#include <linux/swap.h> 36#include <linux/swap.h>
36#include <linux/slab.h> 37#include <linux/slab.h>
@@ -484,7 +485,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm)
484 swap_space = swap_storage->f_path.dentry->d_inode->i_mapping; 485 swap_space = swap_storage->f_path.dentry->d_inode->i_mapping;
485 486
486 for (i = 0; i < ttm->num_pages; ++i) { 487 for (i = 0; i < ttm->num_pages; ++i) {
487 from_page = read_mapping_page(swap_space, i, NULL); 488 from_page = shmem_read_mapping_page(swap_space, i);
488 if (IS_ERR(from_page)) { 489 if (IS_ERR(from_page)) {
489 ret = PTR_ERR(from_page); 490 ret = PTR_ERR(from_page);
490 goto out_err; 491 goto out_err;
@@ -557,7 +558,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage)
557 from_page = ttm->pages[i]; 558 from_page = ttm->pages[i];
558 if (unlikely(from_page == NULL)) 559 if (unlikely(from_page == NULL))
559 continue; 560 continue;
560 to_page = read_mapping_page(swap_space, i, NULL); 561 to_page = shmem_read_mapping_page(swap_space, i);
561 if (unlikely(IS_ERR(to_page))) { 562 if (unlikely(IS_ERR(to_page))) {
562 ret = PTR_ERR(to_page); 563 ret = PTR_ERR(to_page);
563 goto out_err; 564 goto out_err;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 07:45:06 -0500