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-rw-r--r--arch/powerpc/kernel/entry_64.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 952eba6701f..fbbd3f6f006 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -385,15 +385,15 @@ BEGIN_FTR_SECTION
385 oris r0,r6,(SLB_ESID_V)@h 385 oris r0,r6,(SLB_ESID_V)@h
386 ori r0,r0,(SLB_NUM_BOLTED-1)@l 386 ori r0,r0,(SLB_NUM_BOLTED-1)@l
387 387
388 /* Update the last bolted SLB */ 388 /* Update the last bolted SLB. No write barriers are needed
389 * here, provided we only update the current CPU's SLB shadow
390 * buffer.
391 */
389 ld r9,PACA_SLBSHADOWPTR(r13) 392 ld r9,PACA_SLBSHADOWPTR(r13)
390 li r12,0 393 li r12,0
391 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ 394 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
392 eieio
393 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ 395 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
394 eieio
395 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ 396 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
396 eieio
397 397
398 slbie r6 398 slbie r6
399 slbie r6 /* Workaround POWER5 < DD2.1 issue */ 399 slbie r6 /* Workaround POWER5 < DD2.1 issue */