[POWERPC] Remove barriers from the SLB shadow buffer update

After talking to an IBM POWER hypervisor (PHYP) design and development
guy, there seems to be no need for memory barriers when updating the SLB
shadow buffer provided we only update it from the current CPU, which we
do.

Also, these guys see no need in the future for these barriers.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 952eba6701f..fbbd3f6f006 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -385,15 +385,15 @@ BEGIN_FTR_SECTION
         oris    r0,r6,(SLB_ESID_V)@h
         ori     r0,r0,(SLB_NUM_BOLTED-1)@l
 
-        /* Update the last bolted SLB */
+        /* Update the last bolted SLB.  No write barriers are needed
+         * here, provided we only update the current CPU's SLB shadow
+         * buffer.
+         */
         ld      r9,PACA_SLBSHADOWPTR(r13)
         li      r12,0
         std     r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
-        eieio
         std     r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */
-        eieio
         std     r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */
-        eieio
 
         slbie   r6
         slbie   r6              /* Workaround POWER5 < DD2.1 issue */