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-rw-r--r--arch/m68k/platform/5307/Makefile20
-rw-r--r--arch/m68k/platform/5307/config.c147
-rw-r--r--arch/m68k/platform/5307/gpio.c49
-rw-r--r--arch/m68k/platform/5307/nettel.c153
4 files changed, 369 insertions, 0 deletions
diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile
new file mode 100644
index 00000000000..d4293b791f2
--- /dev/null
+++ b/arch/m68k/platform/5307/Makefile
@@ -0,0 +1,20 @@
1#
2# Makefile for the m68knommu kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y += config.o gpio.o
18obj-$(CONFIG_NETtel) += nettel.o
19obj-$(CONFIG_CLEOPATRA) += nettel.o
20
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
new file mode 100644
index 00000000000..00900ac06a9
--- /dev/null
+++ b/arch/m68k/platform/5307/config.c
@@ -0,0 +1,147 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5307/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20#include <asm/mcfwdebug.h>
21
22/***************************************************************************/
23
24/*
25 * Some platforms need software versions of the GPIO data registers.
26 */
27unsigned short ppdata;
28unsigned char ledbank = 0xff;
29
30/***************************************************************************/
31
32static struct mcf_platform_uart m5307_uart_platform[] = {
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE1,
35 .irq = 73,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE2,
39 .irq = 74,
40 },
41 { },
42};
43
44static struct platform_device m5307_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m5307_uart_platform,
48};
49
50static struct platform_device *m5307_devices[] __initdata = {
51 &m5307_uart,
52};
53
54/***************************************************************************/
55
56static void __init m5307_uart_init_line(int line, int irq)
57{
58 if (line == 0) {
59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
61 mcf_mapirq2imr(irq, MCFINTC_UART0);
62 } else if (line == 1) {
63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
65 mcf_mapirq2imr(irq, MCFINTC_UART1);
66 }
67}
68
69static void __init m5307_uarts_init(void)
70{
71 const int nrlines = ARRAY_SIZE(m5307_uart_platform);
72 int line;
73
74 for (line = 0; (line < nrlines); line++)
75 m5307_uart_init_line(line, m5307_uart_platform[line].irq);
76}
77
78/***************************************************************************/
79
80static void __init m5307_timers_init(void)
81{
82 /* Timer1 is always used as system timer */
83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
84 MCF_MBAR + MCFSIM_TIMER1ICR);
85 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
86
87#ifdef CONFIG_HIGHPROFILE
88 /* Timer2 is to be used as a high speed profile timer */
89 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
90 MCF_MBAR + MCFSIM_TIMER2ICR);
91 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
92#endif
93}
94
95/***************************************************************************/
96
97void m5307_cpu_reset(void)
98{
99 local_irq_disable();
100 /* Set watchdog to soft reset, and enabled */
101 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
102 for (;;)
103 /* wait for watchdog to timeout */;
104}
105
106/***************************************************************************/
107
108void __init config_BSP(char *commandp, int size)
109{
110#if defined(CONFIG_NETtel) || \
111 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
112 /* Copy command line from FLASH to local buffer... */
113 memcpy(commandp, (char *) 0xf0004000, size);
114 commandp[size-1] = 0;
115#endif
116
117 mach_reset = m5307_cpu_reset;
118 m5307_timers_init();
119 m5307_uarts_init();
120
121 /* Only support the external interrupts on their primary level */
122 mcf_mapirq2imr(25, MCFINTC_EINT1);
123 mcf_mapirq2imr(27, MCFINTC_EINT3);
124 mcf_mapirq2imr(29, MCFINTC_EINT5);
125 mcf_mapirq2imr(31, MCFINTC_EINT7);
126
127#ifdef CONFIG_BDM_DISABLE
128 /*
129 * Disable the BDM clocking. This also turns off most of the rest of
130 * the BDM device. This is good for EMC reasons. This option is not
131 * incompatible with the memory protection option.
132 */
133 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
134#endif
135}
136
137/***************************************************************************/
138
139static int __init init_BSP(void)
140{
141 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
142 return 0;
143}
144
145arch_initcall(init_BSP);
146
147/***************************************************************************/
diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5307/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/5307/nettel.c
new file mode 100644
index 00000000000..e925ea4602f
--- /dev/null
+++ b/arch/m68k/platform/5307/nettel.c
@@ -0,0 +1,153 @@
1/***************************************************************************/
2
3/*
4 * nettel.c -- startup code support for the NETtel boards
5 *
6 * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/coldfire.h>
17#include <asm/mcfsim.h>
18#include <asm/nettel.h>
19
20/***************************************************************************/
21
22/*
23 * Define the IO and interrupt resources of the 2 SMC9196 interfaces.
24 */
25#define NETTEL_SMC0_ADDR 0x30600300
26#define NETTEL_SMC0_IRQ 29
27
28#define NETTEL_SMC1_ADDR 0x30600000
29#define NETTEL_SMC1_IRQ 27
30
31/*
32 * We need some access into the SMC9196 registers. Define those registers
33 * we will need here (including the smc91x.h doesn't seem to give us these
34 * in a simple form).
35 */
36#define SMC91xx_BANKSELECT 14
37#define SMC91xx_BASEADDR 2
38#define SMC91xx_BASEMAC 4
39
40/***************************************************************************/
41
42static struct resource nettel_smc91x_0_resources[] = {
43 {
44 .start = NETTEL_SMC0_ADDR,
45 .end = NETTEL_SMC0_ADDR + 0x20,
46 .flags = IORESOURCE_MEM,
47 },
48 {
49 .start = NETTEL_SMC0_IRQ,
50 .end = NETTEL_SMC0_IRQ,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct resource nettel_smc91x_1_resources[] = {
56 {
57 .start = NETTEL_SMC1_ADDR,
58 .end = NETTEL_SMC1_ADDR + 0x20,
59 .flags = IORESOURCE_MEM,
60 },
61 {
62 .start = NETTEL_SMC1_IRQ,
63 .end = NETTEL_SMC1_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct platform_device nettel_smc91x[] = {
69 {
70 .name = "smc91x",
71 .id = 0,
72 .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources),
73 .resource = nettel_smc91x_0_resources,
74 },
75 {
76 .name = "smc91x",
77 .id = 1,
78 .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources),
79 .resource = nettel_smc91x_1_resources,
80 },
81};
82
83static struct platform_device *nettel_devices[] __initdata = {
84 &nettel_smc91x[0],
85 &nettel_smc91x[1],
86};
87
88/***************************************************************************/
89
90static u8 nettel_macdefault[] __initdata = {
91 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
92};
93
94/*
95 * Set flash contained MAC address into SMC9196 core. Make sure the flash
96 * MAC address is sane, and not an empty flash. If no good use the Moreton
97 * Bay default MAC address instead.
98 */
99
100static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
101{
102 u16 *macp;
103
104 macp = (u16 *) flashaddr;
105 if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
106 macp = (u16 *) &nettel_macdefault[0];
107
108 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
109 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
110 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
111 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
112}
113
114/***************************************************************************/
115
116/*
117 * Re-map the address space of at least one of the SMC ethernet
118 * parts. Both parts power up decoding the same address, so we
119 * need to move one of them first, before doing anything else.
120 */
121
122static void __init nettel_smc91x_init(void)
123{
124 writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
125 mcf_setppdata(0, 0x0080);
126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
128 mcf_setppdata(0x0080, 0);
129
130 /* Set correct chip select timing for SMC9196 accesses */
131 writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
132
133 /* Set the SMC interrupts to be auto-vectored */
134 mcf_autovector(NETTEL_SMC0_IRQ);
135 mcf_autovector(NETTEL_SMC1_IRQ);
136
137 /* Set MAC addresses from flash for both interfaces */
138 nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
139 nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
140}
141
142/***************************************************************************/
143
144static int __init init_nettel(void)
145{
146 nettel_smc91x_init();
147 platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
148 return 0;
149}
150
151arch_initcall(init_nettel);
152
153/***************************************************************************/
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-20 23:59:20 -0400