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diff --git a/arch/m68k/Kconfig.mmu b/arch/m68k/Kconfig.mmu
new file mode 100644
index 00000000000..13e20bbc407
--- /dev/null
+++ b/arch/m68k/Kconfig.mmu
@@ -0,0 +1,411 @@
+config GENERIC_IOMAP
+        bool
+        default y
+
+config ARCH_MAY_HAVE_PC_FDC
+        bool
+        depends on BROKEN && (Q40 || SUN3X)
+        default y
+
+config ARCH_USES_GETTIMEOFFSET
+        def_bool y
+
+config EISA
+        bool
+        ---help---
+          The Extended Industry Standard Architecture (EISA) bus was
+          developed as an open alternative to the IBM MicroChannel bus.
+
+          The EISA bus provided some of the features of the IBM MicroChannel
+          bus while maintaining backward compatibility with cards made for
+          the older ISA bus.  The EISA bus saw limited use between 1988 and
+          1995 when it was made obsolete by the PCI bus.
+
+          Say Y here if you are building a kernel for an EISA-based machine.
+
+          Otherwise, say N.
+
+config MCA
+        bool
+        help
+          MicroChannel Architecture is found in some IBM PS/2 machines and
+          laptops.  It is a bus system similar to PCI or ISA. See
+          <file:Documentation/mca.txt> (and especially the web page given
+          there) before attempting to build an MCA bus kernel.
+
+config PCMCIA
+        tristate
+        ---help---
+          Say Y here if you want to attach PCMCIA- or PC-cards to your Linux
+          computer.  These are credit-card size devices such as network cards,
+          modems or hard drives often used with laptops computers.  There are
+          actually two varieties of these cards: the older 16 bit PCMCIA cards
+          and the newer 32 bit CardBus cards.  If you want to use CardBus
+          cards, you need to say Y here and also to "CardBus support" below.
+
+          To use your PC-cards, you will need supporting software from David
+          Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
+          for location).  Please also read the PCMCIA-HOWTO, available from
+          <http://www.tldp.org/docs.html#howto>.
+
+          To compile this driver as modules, choose M here: the
+          modules will be called pcmcia_core and ds.
+
+config AMIGA
+        bool "Amiga support"
+        select MMU_MOTOROLA if MMU
+        help
+          This option enables support for the Amiga series of computers. If
+          you plan to use this kernel on an Amiga, say Y here and browse the
+          material available in <file:Documentation/m68k>; otherwise say N.
+
+config ATARI
+        bool "Atari support"
+        select MMU_MOTOROLA if MMU
+        help
+          This option enables support for the 68000-based Atari series of
+          computers (including the TT, Falcon and Medusa). If you plan to use
+          this kernel on an Atari, say Y here and browse the material
+          available in <file:Documentation/m68k>; otherwise say N.
+
+config MAC
+        bool "Macintosh support"
+        select MMU_MOTOROLA if MMU
+        help
+          This option enables support for the Apple Macintosh series of
+          computers (yes, there is experimental support now, at least for part
+          of the series).
+
+          Say N unless you're willing to code the remaining necessary support.
+          ;)
+
+config NUBUS
+        bool
+        depends on MAC
+        default y
+
+config M68K_L2_CACHE
+        bool
+        depends on MAC
+        default y
+
+config APOLLO
+        bool "Apollo support"
+        select MMU_MOTOROLA if MMU
+        help
+          Say Y here if you want to run Linux on an MC680x0-based Apollo
+          Domain workstation such as the DN3500.
+
+config VME
+        bool "VME (Motorola and BVM) support"
+        select MMU_MOTOROLA if MMU
+        help
+          Say Y here if you want to build a kernel for a 680x0 based VME
+          board.  Boards currently supported include Motorola boards MVME147,
+          MVME162, MVME166, MVME167, MVME172, and MVME177.  BVME4000 and
+          BVME6000 boards from BVM Ltd are also supported.
+
+config MVME147
+        bool "MVME147 support"
+        depends on VME
+        help
+          Say Y to include support for early Motorola VME boards.  This will
+          build a kernel which can run on MVME147 single-board computers.  If
+          you select this option you will have to select the appropriate
+          drivers for SCSI, Ethernet and serial ports later on.
+
+config MVME16x
+        bool "MVME162, 166 and 167 support"
+        depends on VME
+        help
+          Say Y to include support for Motorola VME boards.  This will build a
+          kernel which can run on MVME162, MVME166, MVME167, MVME172, and
+          MVME177 boards.  If you select this option you will have to select
+          the appropriate drivers for SCSI, Ethernet and serial ports later
+          on.
+
+config BVME6000
+        bool "BVME4000 and BVME6000 support"
+        depends on VME
+        help
+          Say Y to include support for VME boards from BVM Ltd.  This will
+          build a kernel which can run on BVME4000 and BVME6000 boards.  If
+          you select this option you will have to select the appropriate
+          drivers for SCSI, Ethernet and serial ports later on.
+
+config HP300
+        bool "HP9000/300 and HP9000/400 support"
+        select MMU_MOTOROLA if MMU
+        help
+          This option enables support for the HP9000/300 and HP9000/400 series
+          of workstations. Support for these machines is still somewhat
+          experimental. If you plan to try to use the kernel on such a machine
+          say Y here.
+          Everybody else says N.
+
+config DIO
+        bool "DIO bus support"
+        depends on HP300
+        default y
+        help
+          Say Y here to enable support for the "DIO" expansion bus used in
+          HP300 machines. If you are using such a system you almost certainly
+          want this.
+
+config SUN3X
+        bool "Sun3x support"
+        select MMU_MOTOROLA if MMU
+        select M68030
+        help
+          This option enables support for the Sun 3x series of workstations.
+          Be warned that this support is very experimental.
+          Note that Sun 3x kernels are not compatible with Sun 3 hardware.
+          General Linux information on the Sun 3x series (now discontinued)
+          is at <http://www.angelfire.com/ca2/tech68k/sun3.html>.
+
+          If you don't want to compile a kernel for a Sun 3x, say N.
+
+config Q40
+        bool "Q40/Q60 support"
+        select MMU_MOTOROLA if MMU
+        help
+          The Q40 is a Motorola 68040-based successor to the Sinclair QL
+          manufactured in Germany.  There is an official Q40 home page at
+          <http://www.q40.de/>.  This option enables support for the Q40 and
+          Q60. Select your CPU below.  For 68LC060 don't forget to enable FPU
+          emulation.
+
+config SUN3
+        bool "Sun3 support"
+        depends on !MMU_MOTOROLA
+        select MMU_SUN3 if MMU
+        select M68020
+        help
+          This option enables support for the Sun 3 series of workstations
+          (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires
+          that all other hardware types must be disabled, as Sun 3 kernels
+          are incompatible with all other m68k targets (including Sun 3x!).
+
+          If you don't want to compile a kernel exclusively for a Sun 3, say N.
+
+config NATFEAT
+        bool "ARAnyM emulator support"
+        depends on ATARI
+        help
+          This option enables support for ARAnyM native features, such as
+          access to a disk image as /dev/hda.
+
+config NFBLOCK
+        tristate "NatFeat block device support"
+        depends on BLOCK && NATFEAT
+        help
+          Say Y to include support for the ARAnyM NatFeat block device
+          which allows direct access to the hard drives without using
+          the hardware emulation.
+
+config NFCON
+        tristate "NatFeat console driver"
+        depends on NATFEAT
+        help
+          Say Y to include support for the ARAnyM NatFeat console driver
+          which allows the console output to be redirected to the stderr
+          output of ARAnyM.
+
+config NFETH
+        tristate "NatFeat Ethernet support"
+        depends on NET_ETHERNET && NATFEAT
+        help
+          Say Y to include support for the ARAnyM NatFeat network device
+          which will emulate a regular ethernet device while presenting an
+          ethertap device to the host system.
+
+comment "Processor type"
+
+config M68020
+        bool "68020 support"
+        help
+          If you anticipate running this kernel on a computer with a MC68020
+          processor, say Y. Otherwise, say N. Note that the 68020 requires a
+          68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
+          Sun 3, which provides its own version.
+
+config M68030
+        bool "68030 support"
+        depends on !MMU_SUN3
+        help
+          If you anticipate running this kernel on a computer with a MC68030
+          processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
+          work, as it does not include an MMU (Memory Management Unit).
+
+config M68040
+        bool "68040 support"
+        depends on !MMU_SUN3
+        help
+          If you anticipate running this kernel on a computer with a MC68LC040
+          or MC68040 processor, say Y. Otherwise, say N. Note that an
+          MC68EC040 will not work, as it does not include an MMU (Memory
+          Management Unit).
+
+config M68060
+        bool "68060 support"
+        depends on !MMU_SUN3
+        help
+          If you anticipate running this kernel on a computer with a MC68060
+          processor, say Y. Otherwise, say N.
+
+config MMU_MOTOROLA
+        bool
+
+config MMU_SUN3
+        bool
+        depends on MMU && !MMU_MOTOROLA
+
+config M68KFPU_EMU
+        bool "Math emulation support (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        help
+          At some point in the future, this will cause floating-point math
+          instructions to be emulated by the kernel on machines that lack a
+          floating-point math coprocessor.  Thrill-seekers and chronically
+          sleep-deprived psychotic hacker types can say Y now, everyone else
+          should probably wait a while.
+
+config M68KFPU_EMU_EXTRAPREC
+        bool "Math emulation extra precision"
+        depends on M68KFPU_EMU
+        help
+          The fpu uses normally a few bit more during calculations for
+          correct rounding, the emulator can (often) do the same but this
+          extra calculation can cost quite some time, so you can disable
+          it here. The emulator will then "only" calculate with a 64 bit
+          mantissa and round slightly incorrect, what is more than enough
+          for normal usage.
+
+config M68KFPU_EMU_ONLY
+        bool "Math emulation only kernel"
+        depends on M68KFPU_EMU
+        help
+          This option prevents any floating-point instructions from being
+          compiled into the kernel, thereby the kernel doesn't save any
+          floating point context anymore during task switches, so this
+          kernel will only be usable on machines without a floating-point
+          math coprocessor. This makes the kernel a bit faster as no tests
+          needs to be executed whether a floating-point instruction in the
+          kernel should be executed or not.
+
+config ADVANCED
+        bool "Advanced configuration options"
+        ---help---
+          This gives you access to some advanced options for the CPU. The
+          defaults should be fine for most users, but these options may make
+          it possible for you to improve performance somewhat if you know what
+          you are doing.
+
+          Note that the answer to this question won't directly affect the
+          kernel: saying N will just cause the configurator to skip all
+          the questions about these options.
+
+          Most users should say N to this question.
+
+config RMW_INSNS
+        bool "Use read-modify-write instructions"
+        depends on ADVANCED
+        ---help---
+          This allows to use certain instructions that work with indivisible
+          read-modify-write bus cycles. While this is faster than the
+          workaround of disabling interrupts, it can conflict with DMA
+          ( = direct memory access) on many Amiga systems, and it is also said
+          to destabilize other machines. It is very likely that this will
+          cause serious problems on any Amiga or Atari Medusa if set. The only
+          configuration where it should work are 68030-based Ataris, where it
+          apparently improves performance. But you've been warned! Unless you
+          really know what you are doing, say N. Try Y only if you're quite
+          adventurous.
+
+config SINGLE_MEMORY_CHUNK
+        bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
+        default y if SUN3
+        select NEED_MULTIPLE_NODES
+        help
+          Ignore all but the first contiguous chunk of physical memory for VM
+          purposes.  This will save a few bytes kernel size and may speed up
+          some operations.  Say N if not sure.
+
+config 060_WRITETHROUGH
+        bool "Use write-through caching for 68060 supervisor accesses"
+        depends on ADVANCED && M68060
+        ---help---
+          The 68060 generally uses copyback caching of recently accessed data.
+          Copyback caching means that memory writes will be held in an on-chip
+          cache and only written back to memory some time later.  Saying Y
+          here will force supervisor (kernel) accesses to use writethrough
+          caching.  Writethrough caching means that data is written to memory
+          straight away, so that cache and memory data always agree.
+          Writethrough caching is less efficient, but is needed for some
+          drivers on 68060 based systems where the 68060 bus snooping signal
+          is hardwired on.  The 53c710 SCSI driver is known to suffer from
+          this problem.
+
+config ARCH_DISCONTIGMEM_ENABLE
+        def_bool !SINGLE_MEMORY_CHUNK
+
+config NODES_SHIFT
+        int
+        default "3"
+        depends on !SINGLE_MEMORY_CHUNK
+
+config ZORRO
+        bool "Amiga Zorro (AutoConfig) bus support"
+        depends on AMIGA
+        help
+          This enables support for the Zorro bus in the Amiga. If you have
+          expansion cards in your Amiga that conform to the Amiga
+          AutoConfig(tm) specification, say Y, otherwise N. Note that even
+          expansion cards that do not fit in the Zorro slots but fit in e.g.
+          the CPU slot may fall in this category, so you have to say Y to let
+          Linux use these.
+
+config AMIGA_PCMCIA
+        bool "Amiga 1200/600 PCMCIA support (EXPERIMENTAL)"
+        depends on AMIGA && EXPERIMENTAL
+        help
+          Include support in the kernel for pcmcia on Amiga 1200 and Amiga
+          600. If you intend to use pcmcia cards say Y; otherwise say N.
+
+config HEARTBEAT
+        bool "Use power LED as a heartbeat" if AMIGA || APOLLO || ATARI || MAC ||Q40
+        default y if !AMIGA && !APOLLO && !ATARI && !MAC && !Q40 && HP300
+        help
+          Use the power-on LED on your machine as a load meter.  The exact
+          behavior is platform-dependent, but normally the flash frequency is
+          a hyperbolic function of the 5-minute load average.
+
+# We have a dedicated heartbeat LED. :-)
+config PROC_HARDWARE
+        bool "/proc/hardware support"
+        help
+          Say Y here to support the /proc/hardware file, which gives you
+          access to information about the machine you're running on,
+          including the model, CPU, MMU, clock speed, BogoMIPS rating,
+          and memory size.
+
+config ISA
+        bool
+        depends on Q40 || AMIGA_PCMCIA
+        default y
+        help
+          Find out whether you have ISA slots on your motherboard.  ISA is the
+          name of a bus system, i.e. the way the CPU talks to the other stuff
+          inside your box.  Other bus systems are PCI, EISA, MicroChannel
+          (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
+          newer boards don't support it.  If you have ISA, say Y, otherwise N.
+
+config GENERIC_ISA_DMA
+        bool
+        depends on Q40 || AMIGA_PCMCIA
+        default y
+
+source "drivers/pci/Kconfig"
+
+source "drivers/zorro/Kconfig"
+
diff --git a/arch/m68k/Kconfig.nommu b/arch/m68k/Kconfig.nommu
new file mode 100644
index 00000000000..ff46383112a
--- /dev/null
+++ b/arch/m68k/Kconfig.nommu
@@ -0,0 +1,787 @@
+config FPU
+        bool
+        default n
+
+config GENERIC_GPIO
+        bool
+        default n
+
+config GENERIC_CMOS_UPDATE
+        bool
+        default y
+
+config GENERIC_CLOCKEVENTS
+        bool
+        default n
+
+config M68000
+        bool
+        select CPU_HAS_NO_BITFIELDS
+        help
+          The Freescale (was Motorola) 68000 CPU is the first generation of
+          the well known M68K family of processors. The CPU core as well as
+          being available as a stand alone CPU was also used in many
+          System-On-Chip devices (eg 68328, 68302, etc). It does not contain
+          a paging MMU.
+
+config MCPU32
+        bool
+        select CPU_HAS_NO_BITFIELDS
+        help
+          The Freescale (was then Motorola) CPU32 is a CPU core that is
+          based on the 68020 processor. For the most part it is used in
+          System-On-Chip parts, and does not contain a paging MMU.
+
+config COLDFIRE
+        bool
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select CPU_HAS_NO_BITFIELDS
+        help
+          The Freescale ColdFire family of processors is a modern derivitive
+          of the 68000 processor family. They are mainly targeted at embedded
+          applications, and are all System-On-Chip (SOC) devices, as opposed
+          to stand alone CPUs. They implement a subset of the original 68000
+          processor instruction set.
+
+config COLDFIRE_SW_A7
+        bool
+        default n
+
+config HAVE_CACHE_SPLIT
+        bool
+
+config HAVE_CACHE_CB
+        bool
+
+config HAVE_MBAR
+        bool
+
+config HAVE_IPSBAR
+        bool
+
+choice
+        prompt "CPU"
+        default M68EZ328
+
+config M68328
+        bool "MC68328"
+        select M68000
+        help
+          Motorola 68328 processor support.
+
+config M68EZ328
+        bool "MC68EZ328"
+        select M68000
+        help
+          Motorola 68EX328 processor support.
+
+config M68VZ328
+        bool "MC68VZ328"
+        select M68000
+        help
+          Motorola 68VZ328 processor support.
+
+config M68360
+        bool "MC68360"
+        select MCPU32
+        help
+          Motorola 68360 processor support.
+
+config M5206
+        bool "MCF5206"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5206 processor support.
+
+config M5206e
+        bool "MCF5206e"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5206e processor support.
+
+config M520x
+        bool "MCF520x"
+        select COLDFIRE
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CACHE_SPLIT
+        help
+           Freescale Coldfire 5207/5208 processor support.
+
+config M523x
+        bool "MCF523x"
+        select COLDFIRE
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CACHE_SPLIT
+        select HAVE_IPSBAR
+        help
+          Freescale Coldfire 5230/1/2/4/5 processor support
+
+config M5249
+        bool "MCF5249"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5249 processor support.
+
+config M5271
+        bool "MCF5271"
+        select COLDFIRE
+        select HAVE_CACHE_SPLIT
+        select HAVE_IPSBAR
+        help
+          Freescale (Motorola) ColdFire 5270/5271 processor support.
+
+config M5272
+        bool "MCF5272"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5272 processor support.
+
+config M5275
+        bool "MCF5275"
+        select COLDFIRE
+        select HAVE_CACHE_SPLIT
+        select HAVE_IPSBAR
+        help
+          Freescale (Motorola) ColdFire 5274/5275 processor support.
+
+config M528x
+        bool "MCF528x"
+        select COLDFIRE
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CACHE_SPLIT
+        select HAVE_IPSBAR
+        help
+          Motorola ColdFire 5280/5282 processor support.
+
+config M5307
+        bool "MCF5307"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_CACHE_CB
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5307 processor support.
+
+config M532x
+        bool "MCF532x"
+        select COLDFIRE
+        select HAVE_CACHE_CB
+        help
+          Freescale (Motorola) ColdFire 532x processor support.
+
+config M5407
+        bool "MCF5407"
+        select COLDFIRE
+        select COLDFIRE_SW_A7
+        select HAVE_CACHE_CB
+        select HAVE_MBAR
+        help
+          Motorola ColdFire 5407 processor support.
+
+config M547x
+        bool "MCF547x"
+        select COLDFIRE
+        select HAVE_CACHE_CB
+        select HAVE_MBAR
+        help
+          Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
+
+config M548x
+        bool "MCF548x"
+        select COLDFIRE
+        select HAVE_CACHE_CB
+        select HAVE_MBAR
+        help
+          Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
+
+endchoice
+
+config M527x
+        bool
+        depends on (M5271 || M5275)
+        select GENERIC_CLOCKEVENTS
+        default y
+
+config M54xx
+        bool
+        depends on (M548x || M547x)
+        default y
+
+config CLOCK_SET
+        bool "Enable setting the CPU clock frequency"
+        default n
+        help
+          On some CPU's you do not need to know what the core CPU clock
+          frequency is. On these you can disable clock setting. On some
+          traditional 68K parts, and on all ColdFire parts you need to set
+          the appropriate CPU clock frequency. On these devices many of the
+          onboard peripherals derive their timing from the master CPU clock
+          frequency.
+
+config CLOCK_FREQ
+        int "Set the core clock frequency"
+        default "66666666"
+        depends on CLOCK_SET
+        help
+          Define the CPU clock frequency in use. This is the core clock
+          frequency, it may or may not be the same as the external clock
+          crystal fitted to your board. Some processors have an internal
+          PLL and can have their frequency programmed at run time, others
+          use internal dividers. In general the kernel won't setup a PLL
+          if it is fitted (there are some exceptions). This value will be
+          specific to the exact CPU that you are using.
+
+config OLDMASK
+        bool "Old mask 5307 (1H55J) silicon"
+        depends on M5307
+        help
+          Build support for the older revision ColdFire 5307 silicon.
+          Specifically this is the 1H55J mask revision.
+
+if HAVE_CACHE_SPLIT
+choice
+        prompt "Split Cache Configuration"
+        default CACHE_I
+
+config CACHE_I
+        bool "Instruction"
+        help
+          Use all of the ColdFire CPU cache memory as an instruction cache.
+
+config CACHE_D
+        bool "Data"
+        help
+          Use all of the ColdFire CPU cache memory as a data cache.
+
+config CACHE_BOTH
+        bool "Both"
+        help
+          Split the ColdFire CPU cache, and use half as an instruction cache
+          and half as a data cache.
+endchoice
+endif
+
+if HAVE_CACHE_CB
+choice
+        prompt "Data cache mode"
+        default CACHE_WRITETHRU
+
+config CACHE_WRITETHRU
+        bool "Write-through"
+        help
+          The ColdFire CPU cache is set into Write-through mode.
+
+config CACHE_COPYBACK
+        bool "Copy-back"
+        help
+          The ColdFire CPU cache is set into Copy-back mode.
+endchoice
+endif
+
+comment "Platform"
+
+config PILOT3
+        bool "Pilot 1000/5000, PalmPilot Personal/Pro, or PalmIII support"
+        depends on M68328
+        help
+          Support for the Palm Pilot 1000/5000, Personal/Pro and PalmIII.
+
+config XCOPILOT_BUGS
+        bool "(X)Copilot support"
+        depends on PILOT3
+        help
+          Support the bugs of Xcopilot.
+
+config UC5272
+        bool 'Arcturus Networks uC5272 dimm board support'
+        depends on M5272
+        help
+          Support for the Arcturus Networks uC5272 dimm board.
+
+config UC5282
+        bool "Arcturus Networks uC5282 board support"
+        depends on M528x
+        help
+          Support for the Arcturus Networks uC5282 dimm board.
+
+config UCSIMM
+        bool "uCsimm module support"
+        depends on M68EZ328
+        help
+          Support for the Arcturus Networks uCsimm module.
+
+config UCDIMM
+        bool "uDsimm module support"
+        depends on M68VZ328
+        help
+          Support for the Arcturus Networks uDsimm module.
+
+config DRAGEN2
+        bool "DragenEngine II board support"
+        depends on M68VZ328
+        help
+          Support for the DragenEngine II board.
+
+config DIRECT_IO_ACCESS
+        bool "Allow user to access IO directly"
+        depends on (UCSIMM || UCDIMM || DRAGEN2)
+        help
+          Disable the CPU internal registers protection in user mode,
+          to allow a user application to read/write them.
+
+config INIT_LCD
+        bool "Initialize LCD"
+        depends on (UCSIMM || UCDIMM || DRAGEN2)
+        help
+          Initialize the LCD controller of the 68x328 processor.
+
+config MEMORY_RESERVE
+        int "Memory reservation (MiB)"
+        depends on (UCSIMM || UCDIMM)
+        help
+          Reserve certain memory regions on 68x328 based boards.
+
+config UCQUICC
+        bool "Lineo uCquicc board support"
+        depends on M68360
+        help
+          Support for the Lineo uCquicc board.
+
+config ARN5206
+        bool "Arnewsh 5206 board support"
+        depends on M5206
+        help
+          Support for the Arnewsh 5206 board.
+
+config M5206eC3
+        bool "Motorola M5206eC3 board support"
+        depends on M5206e
+        help
+          Support for the Motorola M5206eC3 board.
+
+config ELITE
+        bool "Motorola M5206eLITE board support"
+        depends on M5206e
+        help
+          Support for the Motorola M5206eLITE board.
+
+config M5208EVB
+        bool "Freescale M5208EVB board support"
+        depends on M520x
+        help
+          Support for the Freescale Coldfire M5208EVB.
+
+config M5235EVB
+        bool "Freescale M5235EVB support"
+        depends on M523x
+        help
+          Support for the Freescale M5235EVB board.
+
+config M5249C3
+        bool "Motorola M5249C3 board support"
+        depends on M5249
+        help
+          Support for the Motorola M5249C3 board.
+
+config M5271EVB
+        bool "Freescale (Motorola) M5271EVB board support"
+        depends on M5271
+        help
+          Support for the Freescale (Motorola) M5271EVB board.
+
+config M5275EVB
+        bool "Freescale (Motorola) M5275EVB board support"
+        depends on M5275
+        help
+          Support for the Freescale (Motorola) M5275EVB board.
+
+config M5272C3
+        bool "Motorola M5272C3 board support"
+        depends on M5272
+        help
+          Support for the Motorola M5272C3 board.
+
+config COBRA5272
+        bool "senTec COBRA5272 board support"
+        depends on M5272
+        help
+          Support for the senTec COBRA5272 board.
+
+config AVNET5282
+        bool "Avnet 5282 board support"
+        depends on M528x
+        help
+          Support for the Avnet 5282 board.  
+          
+config M5282EVB
+        bool "Motorola M5282EVB board support"
+        depends on M528x
+        help
+          Support for the Motorola M5282EVB board.
+
+config COBRA5282
+        bool "senTec COBRA5282 board support"
+        depends on M528x
+        help
+          Support for the senTec COBRA5282 board.
+          
+config SOM5282EM
+        bool "EMAC.Inc SOM5282EM board support"
+        depends on M528x
+        help
+          Support for the EMAC.Inc SOM5282EM module.  
+          
+config WILDFIRE
+        bool "Intec Automation Inc. WildFire board support"
+        depends on M528x
+        help
+          Support for the Intec Automation Inc. WildFire.
+          
+config WILDFIREMOD
+        bool "Intec Automation Inc. WildFire module support"
+        depends on M528x
+        help
+          Support for the Intec Automation Inc. WildFire module.
+
+config ARN5307
+        bool "Arnewsh 5307 board support"
+        depends on M5307
+        help
+          Support for the Arnewsh 5307 board.
+
+config M5307C3
+        bool "Motorola M5307C3 board support"
+        depends on M5307
+        help
+          Support for the Motorola M5307C3 board.
+
+config SECUREEDGEMP3
+        bool "SnapGear SecureEdge/MP3 platform support"
+        depends on M5307
+        help
+          Support for the SnapGear SecureEdge/MP3 platform.
+
+config M5329EVB
+        bool "Freescale (Motorola) M5329EVB board support"
+        depends on M532x
+        help
+          Support for the Freescale (Motorola) M5329EVB board.
+
+config COBRA5329
+        bool "senTec COBRA5329 board support"
+        depends on M532x
+        help
+          Support for the senTec COBRA5329 board.
+
+config M5407C3
+        bool "Motorola M5407C3 board support"
+        depends on M5407
+        help
+          Support for the Motorola M5407C3 board.
+
+config FIREBEE
+        bool "FireBee board support"
+        depends on M547x
+        help
+          Support for the FireBee ColdFire 5475 based board.
+
+config CLEOPATRA
+        bool "Feith CLEOPATRA board support"
+        depends on (M5307 || M5407)
+        help
+          Support for the Feith Cleopatra boards.
+
+config CANCam
+        bool "Feith CANCam board support"
+        depends on M5272
+        help
+          Support for the Feith CANCam board.
+
+config SCALES
+        bool "Feith SCALES board support"
+        depends on M5272
+        help
+          Support for the Feith SCALES board.
+
+config NETtel
+        bool "SecureEdge/NETtel board support"
+        depends on (M5206e || M5272 || M5307)
+        help
+          Support for the SnapGear NETtel/SecureEdge/SnapGear boards.
+
+config SNAPGEAR
+        bool "SnapGear router board support"
+        depends on NETtel
+        help
+          Special additional support for SnapGear router boards.
+
+config CPU16B
+        bool "Sneha Technologies S.L. Sarasvati board support"
+        depends on M5272
+        help
+          Support for the SNEHA CPU16B board.
+
+config MOD5272
+        bool "Netburner MOD-5272 board support"
+        depends on M5272
+        help
+          Support for the Netburner MOD-5272 board.
+
+config SAVANTrosie1
+        bool "Savant Rosie1 board support"
+        depends on M523x
+        help
+          Support for the Savant Rosie1 board.
+
+config ROMFS_FROM_ROM
+        bool "ROMFS image not RAM resident"
+        depends on (NETtel || SNAPGEAR)
+        help
+          The ROMfs filesystem will stay resident in the FLASH/ROM, not be
+          moved into RAM.
+
+config PILOT
+        bool
+        default y
+        depends on (PILOT3 || PILOT5)
+
+config ARNEWSH
+        bool
+        default y
+        depends on (ARN5206 || ARN5307)
+
+config FREESCALE
+        bool
+        default y
+        depends on (M5206eC3 || M5208EVB || M5235EVB || M5249C3 || M5271EVB || M5272C3 || M5275EVB || M5282EVB || M5307C3 || M5329EVB || M5407C3)
+
+config HW_FEITH
+        bool
+        default y
+        depends on (CLEOPATRA || CANCam || SCALES)
+
+config senTec
+        bool
+        default y
+        depends on (COBRA5272 || COBRA5282)
+        
+config EMAC_INC
+        bool
+        default y
+        depends on (SOM5282EM)
+
+config SNEHA
+        bool
+        default y
+        depends on CPU16B
+
+config SAVANT
+        bool
+        default y
+        depends on SAVANTrosie1
+
+config AVNET
+        bool
+        default y
+        depends on (AVNET5282)
+
+config UBOOT
+        bool "Support for U-Boot command line parameters"
+        help
+          If you say Y here kernel will try to collect command
+          line parameters from the initial u-boot stack.
+        default n
+
+config 4KSTACKS
+        bool "Use 4Kb for kernel stacks instead of 8Kb"
+        default y
+        help
+          If you say Y here the kernel will use a 4Kb stacksize for the
+          kernel stack attached to each process/thread. This facilitates
+          running more threads on a system and also reduces the pressure
+          on the VM subsystem for higher order allocations.
+
+comment "RAM configuration"
+
+config RAMBASE
+        hex "Address of the base of RAM"
+        default "0"
+        help
+          Define the address that RAM starts at. On many platforms this is
+          0, the base of the address space. And this is the default. Some
+          platforms choose to setup their RAM at other addresses within the
+          processor address space.
+
+config RAMSIZE
+        hex "Size of RAM (in bytes), or 0 for automatic"
+        default "0x400000"
+        help
+          Define the size of the system RAM. If you select 0 then the
+          kernel will try to probe the RAM size at runtime. This is not
+          supported on all CPU types.
+
+config VECTORBASE
+        hex "Address of the base of system vectors"
+        default "0"
+        help
+          Define the address of the system vectors. Commonly this is
+          put at the start of RAM, but it doesn't have to be. On ColdFire
+          platforms this address is programmed into the VBR register, thus
+          actually setting the address to use.
+
+config MBAR
+        hex "Address of the MBAR (internal peripherals)"
+        default "0x10000000"
+        depends on HAVE_MBAR
+        help
+          Define the address of the internal system peripherals. This value
+          is set in the processors MBAR register. This is generally setup by
+          the boot loader, and will not be written by the kernel. By far most
+          ColdFire boards use the default 0x10000000 value, so if unsure then
+          use this.
+
+config IPSBAR
+        hex "Address of the IPSBAR (internal peripherals)"
+        default "0x40000000"
+        depends on HAVE_IPSBAR
+        help
+          Define the address of the internal system peripherals. This value
+          is set in the processors IPSBAR register. This is generally setup by
+          the boot loader, and will not be written by the kernel. By far most
+          ColdFire boards use the default 0x40000000 value, so if unsure then
+          use this.
+
+config KERNELBASE
+        hex "Address of the base of kernel code"
+        default "0x400"
+        help
+          Typically on m68k systems the kernel will not start at the base
+          of RAM, but usually some small offset from it. Define the start
+          address of the kernel here. The most common setup will have the
+          processor vectors at the base of RAM and then the start of the
+          kernel. On some platforms some RAM is reserved for boot loaders
+          and the kernel starts after that. The 0x400 default was based on
+          a system with the RAM based at address 0, and leaving enough room
+          for the theoretical maximum number of 256 vectors.
+
+choice
+        prompt "RAM bus width"
+        default RAMAUTOBIT
+
+config RAMAUTOBIT
+        bool "AUTO"
+        help
+          Select the physical RAM data bus size. Not needed on most platforms,
+          so you can generally choose AUTO.
+
+config RAM8BIT
+        bool "8bit"
+        help
+          Configure RAM bus to be 8 bits wide.
+
+config RAM16BIT
+        bool "16bit"
+        help
+          Configure RAM bus to be 16 bits wide.
+
+config RAM32BIT
+        bool "32bit"
+        help
+          Configure RAM bus to be 32 bits wide.
+
+endchoice
+
+comment "ROM configuration"
+
+config ROM
+        bool "Specify ROM linker regions"
+        default n
+        help
+          Define a ROM region for the linker script. This creates a kernel
+          that can be stored in flash, with possibly the text, and data
+          regions being copied out to RAM at startup.
+
+config ROMBASE
+        hex "Address of the base of ROM device"
+        default "0"
+        depends on ROM
+        help
+          Define the address that the ROM region starts at. Some platforms
+          use this to set their chip select region accordingly for the boot
+          device.
+
+config ROMVEC
+        hex "Address of the base of the ROM vectors"
+        default "0"
+        depends on ROM
+        help
+          This is almost always the same as the base of the ROM. Since on all
+          68000 type variants the vectors are at the base of the boot device
+          on system startup.
+
+config ROMVECSIZE
+        hex "Size of ROM vector region (in bytes)"
+        default "0x400"
+        depends on ROM
+        help
+          Define the size of the vector region in ROM. For most 68000
+          variants this would be 0x400 bytes in size. Set to 0 if you do
+          not want a vector region at the start of the ROM.
+
+config ROMSTART
+        hex "Address of the base of system image in ROM"
+        default "0x400"
+        depends on ROM
+        help
+          Define the start address of the system image in ROM. Commonly this
+          is strait after the ROM vectors.
+
+config ROMSIZE
+        hex "Size of the ROM device"
+        default "0x100000"
+        depends on ROM
+        help
+          Size of the ROM device. On some platforms this is used to setup
+          the chip select that controls the boot ROM device.
+
+choice
+        prompt "Kernel executes from"
+        ---help---
+          Choose the memory type that the kernel will be running in.
+
+config RAMKERNEL
+        bool "RAM"
+        help
+          The kernel will be resident in RAM when running.
+
+config ROMKERNEL
+        bool "ROM"
+        help
+          The kernel will be resident in FLASH/ROM when running. This is
+          often referred to as Execute-in-Place (XIP), since the kernel
+          code executes from the position it is stored in the FLASH/ROM.
+
+endchoice
+
+if COLDFIRE
+source "kernel/Kconfig.preempt"
+endif
+
+source "kernel/time/Kconfig"
+
+config ISA_DMA_API
+        bool
+        depends on !M5272
+        default y
+
+source "drivers/pcmcia/Kconfig"
+
diff --git a/arch/m68k/Makefile_mm b/arch/m68k/Makefile_mm
new file mode 100644
index 00000000000..d449b6d5aec
--- /dev/null
+++ b/arch/m68k/Makefile_mm
@@ -0,0 +1,121 @@
+#
+# m68k/Makefile
+#
+# This file is included by the global makefile so that you can add your own
+# architecture-specific flags and dependencies. Remember to do have actions
+# for "archclean" and "archdep" for cleaning up and making dependencies for
+# this architecture
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1994 by Hamish Macdonald
+#
+
+# override top level makefile
+AS += -m68020
+LDFLAGS := -m m68kelf
+KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds
+ifneq ($(SUBARCH),$(ARCH))
+        ifeq ($(CROSS_COMPILE),)
+                CROSS_COMPILE := $(call cc-cross-prefix, \
+                        m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-)
+        endif
+endif
+
+ifdef CONFIG_SUN3
+LDFLAGS_vmlinux = -N
+endif
+
+CHECKFLAGS += -D__mc68000__
+
+# without -fno-strength-reduce the 53c7xx.c driver fails ;-(
+KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2
+
+# enable processor switch if compiled only for a single cpu
+ifndef CONFIG_M68020
+ifndef CONFIG_M68030
+
+ifndef CONFIG_M68060
+KBUILD_CFLAGS += -m68040
+endif
+
+ifndef CONFIG_M68040
+KBUILD_CFLAGS += -m68060
+endif
+
+endif
+endif
+
+ifdef CONFIG_KGDB
+# If configured for kgdb support, include debugging infos and keep the
+# frame pointer
+KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g
+endif
+
+ifndef CONFIG_SUN3
+head-y := arch/m68k/kernel/head.o
+else
+head-y := arch/m68k/kernel/sun3-head.o
+endif
+
+core-y                          += arch/m68k/kernel/    arch/m68k/mm/
+libs-y                          += arch/m68k/lib/
+
+core-$(CONFIG_Q40)              += arch/m68k/q40/
+core-$(CONFIG_AMIGA)            += arch/m68k/amiga/
+core-$(CONFIG_ATARI)            += arch/m68k/atari/
+core-$(CONFIG_MAC)              += arch/m68k/mac/
+core-$(CONFIG_HP300)            += arch/m68k/hp300/
+core-$(CONFIG_APOLLO)           += arch/m68k/apollo/
+core-$(CONFIG_MVME147)          += arch/m68k/mvme147/
+core-$(CONFIG_MVME16x)          += arch/m68k/mvme16x/
+core-$(CONFIG_BVME6000)         += arch/m68k/bvme6000/
+core-$(CONFIG_SUN3X)            += arch/m68k/sun3x/     arch/m68k/sun3/
+core-$(CONFIG_SUN3)             += arch/m68k/sun3/      arch/m68k/sun3/prom/
+core-$(CONFIG_NATFEAT)          += arch/m68k/emu/
+core-$(CONFIG_M68040)           += arch/m68k/fpsp040/
+core-$(CONFIG_M68060)           += arch/m68k/ifpsp060/
+core-$(CONFIG_M68KFPU_EMU)      += arch/m68k/math-emu/
+
+all:    zImage
+
+lilo:   vmlinux
+        if [ -f $(INSTALL_PATH)/vmlinux ]; then mv -f $(INSTALL_PATH)/vmlinux $(INSTALL_PATH)/vmlinux.old; fi
+        if [ -f $(INSTALL_PATH)/System.map ]; then mv -f $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi
+        cat vmlinux > $(INSTALL_PATH)/vmlinux
+        cp System.map $(INSTALL_PATH)/System.map
+        if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi
+
+zImage compressed: vmlinux.gz
+
+vmlinux.gz: vmlinux
+
+ifndef CONFIG_KGDB
+        cp vmlinux vmlinux.tmp
+        $(STRIP) vmlinux.tmp
+        gzip -9c vmlinux.tmp >vmlinux.gz
+        rm vmlinux.tmp
+else
+        gzip -9c vmlinux >vmlinux.gz
+endif
+
+bzImage: vmlinux.bz2
+
+vmlinux.bz2: vmlinux
+
+ifndef CONFIG_KGDB
+        cp vmlinux vmlinux.tmp
+        $(STRIP) vmlinux.tmp
+        bzip2 -1c vmlinux.tmp >vmlinux.bz2
+        rm vmlinux.tmp
+else
+        bzip2 -1c vmlinux >vmlinux.bz2
+endif
+
+archclean:
+        rm -f vmlinux.gz vmlinux.bz2
+
+install:
+        sh $(srctree)/arch/m68k/install.sh $(KERNELRELEASE) vmlinux.gz System.map "$(INSTALL_PATH)"
diff --git a/arch/m68k/Makefile_no b/arch/m68k/Makefile_no
new file mode 100644
index 00000000000..844d3f17226
--- /dev/null
+++ b/arch/m68k/Makefile_no
@@ -0,0 +1,124 @@
+#
+# arch/m68k/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# (C) Copyright 2002, Greg Ungerer <gerg@snapgear.com>
+#
+
+platform-$(CONFIG_M68328)       := 68328
+platform-$(CONFIG_M68EZ328)     := 68EZ328
+platform-$(CONFIG_M68VZ328)     := 68VZ328
+platform-$(CONFIG_M68360)       := 68360
+platform-$(CONFIG_M5206)        := 5206
+platform-$(CONFIG_M5206e)       := 5206
+platform-$(CONFIG_M520x)        := 520x
+platform-$(CONFIG_M523x)        := 523x
+platform-$(CONFIG_M5249)        := 5249
+platform-$(CONFIG_M527x)        := 527x
+platform-$(CONFIG_M5272)        := 5272
+platform-$(CONFIG_M528x)        := 528x
+platform-$(CONFIG_M5307)        := 5307
+platform-$(CONFIG_M532x)        := 532x
+platform-$(CONFIG_M5407)        := 5407
+platform-$(CONFIG_M54xx)        := 54xx
+PLATFORM := $(platform-y)
+
+board-$(CONFIG_PILOT)           := pilot
+board-$(CONFIG_UC5272)          := UC5272
+board-$(CONFIG_UC5282)          := UC5282
+board-$(CONFIG_UCSIMM)          := ucsimm
+board-$(CONFIG_UCDIMM)          := ucdimm
+board-$(CONFIG_UCQUICC)         := uCquicc
+board-$(CONFIG_DRAGEN2)         := de2
+board-$(CONFIG_ARNEWSH)         := ARNEWSH
+board-$(CONFIG_FREESCALE)       := FREESCALE
+board-$(CONFIG_M5235EVB)        := M5235EVB
+board-$(CONFIG_M5271EVB)        := M5271EVB
+board-$(CONFIG_M5275EVB)        := M5275EVB
+board-$(CONFIG_M5282EVB)        := M5282EVB
+board-$(CONFIG_ELITE)           := eLITE
+board-$(CONFIG_NETtel)          := NETtel
+board-$(CONFIG_SECUREEDGEMP3)   := MP3
+board-$(CONFIG_CLEOPATRA)       := CLEOPATRA
+board-$(CONFIG_senTec)          := senTec
+board-$(CONFIG_SNEHA)           := SNEHA
+board-$(CONFIG_M5208EVB)        := M5208EVB
+board-$(CONFIG_MOD5272)         := MOD5272
+board-$(CONFIG_AVNET)           := AVNET
+board-$(CONFIG_SAVANT)          := SAVANT
+BOARD := $(board-y)
+
+model-$(CONFIG_RAMKERNEL)       := ram
+model-$(CONFIG_ROMKERNEL)       := rom
+MODEL := $(model-y)
+
+#
+# Some code support is grouped together for a common cpu-subclass (for
+# example all ColdFire cpu's are very similar). Determine the sub-class
+# for the selected cpu. ONLY need to define this for the non-base member
+# of the family.
+#
+cpuclass-$(CONFIG_M5206)        := coldfire
+cpuclass-$(CONFIG_M5206e)       := coldfire
+cpuclass-$(CONFIG_M520x)        := coldfire
+cpuclass-$(CONFIG_M523x)        := coldfire
+cpuclass-$(CONFIG_M5249)        := coldfire
+cpuclass-$(CONFIG_M527x)        := coldfire
+cpuclass-$(CONFIG_M5272)        := coldfire
+cpuclass-$(CONFIG_M528x)        := coldfire
+cpuclass-$(CONFIG_M5307)        := coldfire
+cpuclass-$(CONFIG_M532x)        := coldfire
+cpuclass-$(CONFIG_M5407)        := coldfire
+cpuclass-$(CONFIG_M54xx)        := coldfire
+cpuclass-$(CONFIG_M68328)       := 68328
+cpuclass-$(CONFIG_M68EZ328)     := 68328
+cpuclass-$(CONFIG_M68VZ328)     := 68328
+cpuclass-$(CONFIG_M68360)       := 68360
+CPUCLASS := $(cpuclass-y)
+
+ifneq ($(CPUCLASS),$(PLATFORM))
+CLASSDIR := arch/m68k/platform/$(cpuclass-y)/
+endif
+
+export PLATFORM BOARD MODEL CPUCLASS
+
+#
+# Some CFLAG additions based on specific CPU type.
+#
+cflags-$(CONFIG_M5206)          := $(call cc-option,-mcpu=5206,-m5200)
+cflags-$(CONFIG_M5206e)         := $(call cc-option,-mcpu=5206e,-m5200)
+cflags-$(CONFIG_M520x)          := $(call cc-option,-mcpu=5208,-m5200)
+cflags-$(CONFIG_M523x)          := $(call cc-option,-mcpu=523x,-m5307)
+cflags-$(CONFIG_M5249)          := $(call cc-option,-mcpu=5249,-m5200)
+cflags-$(CONFIG_M5271)          := $(call cc-option,-mcpu=5271,-m5307)
+cflags-$(CONFIG_M5272)          := $(call cc-option,-mcpu=5272,-m5307)
+cflags-$(CONFIG_M5275)          := $(call cc-option,-mcpu=5275,-m5307)
+cflags-$(CONFIG_M528x)          := $(call cc-option,-mcpu=528x,-m5307)
+cflags-$(CONFIG_M5307)          := $(call cc-option,-mcpu=5307,-m5200)
+cflags-$(CONFIG_M532x)          := $(call cc-option,-mcpu=532x,-m5307)
+cflags-$(CONFIG_M5407)          := $(call cc-option,-mcpu=5407,-m5200)
+cflags-$(CONFIG_M54xx)          := $(call cc-option,-mcpu=5475,-m5200)
+cflags-$(CONFIG_M68328)         := -m68000
+cflags-$(CONFIG_M68EZ328)       := -m68000
+cflags-$(CONFIG_M68VZ328)       := -m68000
+cflags-$(CONFIG_M68360)         := -m68332
+
+KBUILD_AFLAGS += $(cflags-y)
+
+KBUILD_CFLAGS += $(cflags-y)
+KBUILD_CFLAGS += -D__linux__
+KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\"
+
+head-y := arch/m68k/platform/$(cpuclass-y)/head.o
+
+core-y  += arch/m68k/kernel/ \
+           arch/m68k/mm/ \
+           $(CLASSDIR) \
+           arch/m68k/platform/$(PLATFORM)/
+libs-y  += arch/m68k/lib/
+
+archclean:
+
diff --git a/arch/m68k/include/asm/MC68332.h b/arch/m68k/include/asm/MC68332.h
new file mode 100644
index 00000000000..6bb8f02685a
--- /dev/null
+++ b/arch/m68k/include/asm/MC68332.h
@@ -0,0 +1,152 @@
+
+/* include/asm-m68knommu/MC68332.h: '332 control registers
+ *
+ * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
+ *
+ */
+
+#ifndef _MC68332_H_
+#define _MC68332_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+
+#define PORTE_ADDR      0xfffa11
+#define PORTE   BYTE_REF(PORTE_ADDR)
+#define DDRE_ADDR       0xfffa15
+#define DDRE    BYTE_REF(DDRE_ADDR)
+#define PEPAR_ADDR      0xfffa17
+#define PEPAR   BYTE_REF(PEPAR_ADDR)
+
+#define PORTF_ADDR      0xfffa19
+#define PORTF   BYTE_REF(PORTF_ADDR)
+#define DDRF_ADDR       0xfffa1d
+#define DDRF    BYTE_REF(DDRF_ADDR)
+#define PFPAR_ADDR      0xfffa1f
+#define PFPAR   BYTE_REF(PFPAR_ADDR)
+
+#define PORTQS_ADDR     0xfffc15
+#define PORTQS  BYTE_REF(PORTQS_ADDR)
+#define DDRQS_ADDR      0xfffc17
+#define DDRQS   BYTE_REF(DDRQS_ADDR)
+#define PQSPAR_ADDR     0xfffc16
+#define PQSPAR  BYTE_REF(PQSPAR_ADDR)
+
+#define CSPAR0_ADDR 0xFFFA44
+#define CSPAR0 WORD_REF(CSPAR0_ADDR)
+#define CSPAR1_ADDR 0xFFFA46
+#define CSPAR1 WORD_REF(CSPAR1_ADDR)
+#define CSARBT_ADDR 0xFFFA48
+#define CSARBT WORD_REF(CSARBT_ADDR)
+#define CSOPBT_ADDR 0xFFFA4A
+#define CSOPBT WORD_REF(CSOPBT_ADDR)
+#define CSBAR0_ADDR 0xFFFA4C
+#define CSBAR0 WORD_REF(CSBAR0_ADDR)
+#define CSOR0_ADDR 0xFFFA4E
+#define CSOR0 WORD_REF(CSOR0_ADDR)
+#define CSBAR1_ADDR 0xFFFA50
+#define CSBAR1 WORD_REF(CSBAR1_ADDR)
+#define CSOR1_ADDR 0xFFFA52
+#define CSOR1 WORD_REF(CSOR1_ADDR)
+#define CSBAR2_ADDR 0xFFFA54
+#define CSBAR2 WORD_REF(CSBAR2_ADDR)
+#define CSOR2_ADDR 0xFFFA56
+#define CSOR2 WORD_REF(CSOR2_ADDR)
+#define CSBAR3_ADDR 0xFFFA58
+#define CSBAR3 WORD_REF(CSBAR3_ADDR)
+#define CSOR3_ADDR 0xFFFA5A
+#define CSOR3 WORD_REF(CSOR3_ADDR)
+#define CSBAR4_ADDR 0xFFFA5C
+#define CSBAR4 WORD_REF(CSBAR4_ADDR)
+#define CSOR4_ADDR 0xFFFA5E
+#define CSOR4 WORD_REF(CSOR4_ADDR)
+#define CSBAR5_ADDR 0xFFFA60
+#define CSBAR5 WORD_REF(CSBAR5_ADDR)
+#define CSOR5_ADDR 0xFFFA62
+#define CSOR5 WORD_REF(CSOR5_ADDR)
+#define CSBAR6_ADDR 0xFFFA64
+#define CSBAR6 WORD_REF(CSBAR6_ADDR)
+#define CSOR6_ADDR 0xFFFA66
+#define CSOR6 WORD_REF(CSOR6_ADDR)
+#define CSBAR7_ADDR 0xFFFA68
+#define CSBAR7 WORD_REF(CSBAR7_ADDR)
+#define CSOR7_ADDR 0xFFFA6A
+#define CSOR7 WORD_REF(CSOR7_ADDR)
+#define CSBAR8_ADDR 0xFFFA6C
+#define CSBAR8 WORD_REF(CSBAR8_ADDR)
+#define CSOR8_ADDR 0xFFFA6E
+#define CSOR8 WORD_REF(CSOR8_ADDR)
+#define CSBAR9_ADDR 0xFFFA70
+#define CSBAR9 WORD_REF(CSBAR9_ADDR)
+#define CSOR9_ADDR 0xFFFA72
+#define CSOR9 WORD_REF(CSOR9_ADDR)
+#define CSBAR10_ADDR 0xFFFA74
+#define CSBAR10 WORD_REF(CSBAR10_ADDR)
+#define CSOR10_ADDR 0xFFFA76
+#define CSOR10 WORD_REF(CSOR10_ADDR)
+
+#define CSOR_MODE_ASYNC 0x0000
+#define CSOR_MODE_SYNC  0x8000
+#define CSOR_MODE_MASK  0x8000
+#define CSOR_BYTE_DISABLE       0x0000
+#define CSOR_BYTE_UPPER         0x4000
+#define CSOR_BYTE_LOWER         0x2000
+#define CSOR_BYTE_BOTH          0x6000
+#define CSOR_BYTE_MASK          0x6000
+#define CSOR_RW_RSVD            0x0000
+#define CSOR_RW_READ            0x0800
+#define CSOR_RW_WRITE           0x1000
+#define CSOR_RW_BOTH            0x1800
+#define CSOR_RW_MASK            0x1800
+#define CSOR_STROBE_DS          0x0400
+#define CSOR_STROBE_AS          0x0000
+#define CSOR_STROBE_MASK        0x0400
+#define CSOR_DSACK_WAIT(x)      (wait << 6)
+#define CSOR_DSACK_FTERM        (14 << 6)
+#define CSOR_DSACK_EXTERNAL     (15 << 6)
+#define CSOR_DSACK_MASK         0x03c0
+#define CSOR_SPACE_CPU          0x0000
+#define CSOR_SPACE_USER         0x0010
+#define CSOR_SPACE_SU           0x0020
+#define CSOR_SPACE_BOTH         0x0030
+#define CSOR_SPACE_MASK         0x0030
+#define CSOR_IPL_ALL            0x0000
+#define CSOR_IPL_PRIORITY(x)    (x << 1)
+#define CSOR_IPL_MASK           0x000e
+#define CSOR_AVEC_ON            0x0001
+#define CSOR_AVEC_OFF           0x0000
+#define CSOR_AVEC_MASK          0x0001
+
+#define CSBAR_ADDR(x)           ((addr >> 11) << 3) 
+#define CSBAR_ADDR_MASK         0xfff8
+#define CSBAR_BLKSIZE_2K        0x0000
+#define CSBAR_BLKSIZE_8K        0x0001
+#define CSBAR_BLKSIZE_16K       0x0002
+#define CSBAR_BLKSIZE_64K       0x0003
+#define CSBAR_BLKSIZE_128K      0x0004
+#define CSBAR_BLKSIZE_256K      0x0005
+#define CSBAR_BLKSIZE_512K      0x0006
+#define CSBAR_BLKSIZE_1M        0x0007
+#define CSBAR_BLKSIZE_MASK      0x0007
+
+#define CSPAR_DISC      0
+#define CSPAR_ALT       1
+#define CSPAR_CS8       2
+#define CSPAR_CS16      3
+#define CSPAR_MASK      3
+
+#define CSPAR0_CSBOOT(x) (x << 0)
+#define CSPAR0_CS0(x)   (x << 2)
+#define CSPAR0_CS1(x)   (x << 4)
+#define CSPAR0_CS2(x)   (x << 6)
+#define CSPAR0_CS3(x)   (x << 8)
+#define CSPAR0_CS4(x)   (x << 10)
+#define CSPAR0_CS5(x)   (x << 12)
+
+#define CSPAR1_CS6(x)   (x << 0)
+#define CSPAR1_CS7(x)   (x << 2)
+#define CSPAR1_CS8(x)   (x << 4)
+#define CSPAR1_CS9(x)   (x << 6)
+#define CSPAR1_CS10(x)  (x << 8)
+
+#endif
diff --git a/arch/m68k/include/asm/a.out.h b/arch/m68k/include/asm/a.out.h
new file mode 100644
index 00000000000..3885fe43432
--- /dev/null
+++ b/arch/m68k/include/asm/a.out.h
@@ -0,0 +1,20 @@
+#ifndef __M68K_A_OUT_H__
+#define __M68K_A_OUT_H__
+
+struct exec
+{
+  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
+  unsigned a_text;              /* length of text, in bytes */
+  unsigned a_data;              /* length of data, in bytes */
+  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
+  unsigned a_syms;              /* length of symbol table data in file, in bytes */
+  unsigned a_entry;             /* start address */
+  unsigned a_trsize;            /* length of relocation info for text, in bytes */
+  unsigned a_drsize;            /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#endif /* __M68K_A_OUT_H__ */
diff --git a/arch/m68k/include/asm/anchor.h b/arch/m68k/include/asm/anchor.h
new file mode 100644
index 00000000000..871c0d5cfc3
--- /dev/null
+++ b/arch/m68k/include/asm/anchor.h
@@ -0,0 +1,112 @@
+/****************************************************************************/
+
+/*
+ *      anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
+ *
+ *      (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
+ */
+
+/****************************************************************************/
+#ifndef anchor_h
+#define anchor_h
+/****************************************************************************/
+
+/*
+ *      Define basic addressing info.
+ */
+#if defined(CONFIG_M5407C3)
+#define COMEM_BASE      0xFFFF0000      /* Base of CO-MEM address space */
+#define COMEM_IRQ       25              /* IRQ of anchor part */
+#else
+#define COMEM_BASE      0x80000000      /* Base of CO-MEM address space */
+#define COMEM_IRQ       25              /* IRQ of anchor part */
+#endif
+
+/****************************************************************************/
+
+/*
+ *      4-byte registers of CO-MEM, so adjust register addresses for
+ *      easy access. Handy macro for word access too.
+ */
+#define LREG(a)         ((a) >> 2)
+#define WREG(a)         ((a) >> 1)
+
+
+/*
+ *      Define base addresses within CO-MEM Lite register address space.
+ */
+#define COMEM_I2O       0x0000          /* I2O registers */
+#define COMEM_OPREGS    0x0400          /* Operation registers */
+#define COMEM_PCIBUS    0x2000          /* Direct access to PCI bus */
+#define COMEM_SHMEM     0x4000          /* Shared memory region */
+
+#define COMEM_SHMEMSIZE 0x4000          /* Size of shared memory */
+
+
+/*
+ *      Define CO-MEM Registers.
+ */
+#define COMEM_I2OHISR   0x0030          /* I2O host interrupt status */
+#define COMEM_I2OHIMR   0x0034          /* I2O host interrupt mask */
+#define COMEM_I2OLISR   0x0038          /* I2O local interrupt status */
+#define COMEM_I2OLIMR   0x003c          /* I2O local interrupt mask */
+#define COMEM_IBFPFIFO  0x0040          /* I2O inbound free/post FIFO */
+#define COMEM_OBPFFIFO  0x0044          /* I2O outbound post/free FIFO */
+#define COMEM_IBPFFIFO  0x0048          /* I2O inbound post/free FIFO */
+#define COMEM_OBFPFIFO  0x004c          /* I2O outbound free/post FIFO */
+
+#define COMEM_DAHBASE   0x0460          /* Direct access base address */
+
+#define COMEM_NVCMD     0x04a0          /* I2C serial command */
+#define COMEM_NVREAD    0x04a4          /* I2C serial read */
+#define COMEM_NVSTAT    0x04a8          /* I2C status */
+
+#define COMEM_DMALBASE  0x04b0          /* DMA local base address */
+#define COMEM_DMAHBASE  0x04b4          /* DMA host base address */
+#define COMEM_DMASIZE   0x04b8          /* DMA size */
+#define COMEM_DMACTL    0x04bc          /* DMA control */
+
+#define COMEM_HCTL      0x04e0          /* Host control */
+#define COMEM_HINT      0x04e4          /* Host interrupt control/status */
+#define COMEM_HLDATA    0x04e8          /* Host to local data mailbox */
+#define COMEM_LINT      0x04f4          /* Local interrupt contole status */
+#define COMEM_LHDATA    0x04f8          /* Local to host data mailbox */
+
+#define COMEM_LBUSCFG   0x04fc          /* Local bus configuration */
+
+
+/*
+ *      Commands and flags for use with Direct Access Register.
+ */
+#define COMEM_DA_IACK   0x00000000      /* Interrupt acknowledge (read) */
+#define COMEM_DA_SPCL   0x00000010      /* Special cycle (write) */
+#define COMEM_DA_MEMRD  0x00000004      /* Memory read cycle */
+#define COMEM_DA_MEMWR  0x00000004      /* Memory write cycle */
+#define COMEM_DA_IORD   0x00000002      /* I/O read cycle */
+#define COMEM_DA_IOWR   0x00000002      /* I/O write cycle */
+#define COMEM_DA_CFGRD  0x00000006      /* Configuration read cycle */
+#define COMEM_DA_CFGWR  0x00000006      /* Configuration write cycle */
+
+#define COMEM_DA_ADDR(a)        ((a) & 0xffffe000)
+
+#define COMEM_DA_OFFSET(a)      ((a) & 0x00001fff)
+
+
+/*
+ *      The PCI bus will be limited in what slots will actually be used.
+ *      Define valid device numbers for different boards.
+ */
+#if defined(CONFIG_M5407C3)
+#define COMEM_MINDEV    14              /* Minimum valid DEVICE */
+#define COMEM_MAXDEV    14              /* Maximum valid DEVICE */
+#define COMEM_BRIDGEDEV 15              /* Slot bridge is in */
+#else
+#define COMEM_MINDEV    0               /* Minimum valid DEVICE */
+#define COMEM_MAXDEV    3               /* Maximum valid DEVICE */
+#endif
+
+#define COMEM_MAXPCI    (COMEM_MAXDEV+1)        /* Maximum PCI devices */
+
+
+/****************************************************************************/
+#endif  /* anchor_h */
diff --git a/arch/m68k/include/asm/apollodma.h b/arch/m68k/include/asm/apollodma.h
new file mode 100644
index 00000000000..954adc851ad
--- /dev/null
+++ b/arch/m68k/include/asm/apollodma.h
@@ -0,0 +1,248 @@
+/*
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ */
+
+#ifndef _ASM_APOLLO_DMA_H
+#define _ASM_APOLLO_DMA_H
+
+#include <asm/apollohw.h>               /* need byte IO */
+#include <linux/spinlock.h>             /* And spinlocks */
+#include <linux/delay.h>
+
+
+#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
+#define dma_inb(addr)      (*((volatile unsigned char *)(addr+IO_BASE)))
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+#define MAX_DMA_CHANNELS        8
+
+/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x1000000)
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x10C00 /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            (IO_DMA1_BASE+0x08) /* command register (w) */
+#define DMA1_STAT_REG           (IO_DMA1_BASE+0x08) /* status register (r) */
+#define DMA1_REQ_REG            (IO_DMA1_BASE+0x09) /* request register (w) */
+#define DMA1_MASK_REG           (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
+#define DMA1_MODE_REG           (IO_DMA1_BASE+0x0B) /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
+#define DMA1_RESET_REG          (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       (IO_DMA1_BASE+0x0E) /* Clear Mask */
+#define DMA1_MASK_ALL_REG       (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            (IO_DMA2_BASE+0x10) /* command register (w) */
+#define DMA2_STAT_REG           (IO_DMA2_BASE+0x10) /* status register (r) */
+#define DMA2_REQ_REG            (IO_DMA2_BASE+0x12) /* request register (w) */
+#define DMA2_MASK_REG           (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
+#define DMA2_MODE_REG           (IO_DMA2_BASE+0x16) /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
+#define DMA2_RESET_REG          (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       (IO_DMA2_BASE+0x1C) /* Clear Mask */
+#define DMA2_MASK_ALL_REG       (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
+
+#define DMA_ADDR_0              (IO_DMA1_BASE+0x00) /* DMA address registers */
+#define DMA_ADDR_1              (IO_DMA1_BASE+0x02)
+#define DMA_ADDR_2              (IO_DMA1_BASE+0x04)
+#define DMA_ADDR_3              (IO_DMA1_BASE+0x06)
+#define DMA_ADDR_4              (IO_DMA2_BASE+0x00)
+#define DMA_ADDR_5              (IO_DMA2_BASE+0x04)
+#define DMA_ADDR_6              (IO_DMA2_BASE+0x08)
+#define DMA_ADDR_7              (IO_DMA2_BASE+0x0C)
+
+#define DMA_CNT_0               (IO_DMA1_BASE+0x01)   /* DMA count registers */
+#define DMA_CNT_1               (IO_DMA1_BASE+0x03)
+#define DMA_CNT_2               (IO_DMA1_BASE+0x05)
+#define DMA_CNT_3               (IO_DMA1_BASE+0x07)
+#define DMA_CNT_4               (IO_DMA2_BASE+0x02)
+#define DMA_CNT_5               (IO_DMA2_BASE+0x06)
+#define DMA_CNT_6               (IO_DMA2_BASE+0x0A)
+#define DMA_CNT_7               (IO_DMA2_BASE+0x0E)
+
+#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT    0x10
+
+#define DMA_8BIT 0
+#define DMA_16BIT 1
+#define DMA_BUSMASTER 2
+
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr,  DMA1_MASK_REG);
+        else
+                dma_outb(dmanr & 3,  DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr | 4,  DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(0,  DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0,  DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr<=3)
+                dma_outb(mode | dmanr,  DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
+}
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+        if (dmanr <= 3)  {
+            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+        }  else  {
+            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+        }
+}
+
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3)  {
+            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+        } else {
+            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr);       /* release it again */
+
+/* These are in arch/m68k/apollo/dma.c: */
+extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
+extern void dma_unmap_page(unsigned short dma_addr);
+
+#endif /* _ASM_APOLLO_DMA_H */
diff --git a/arch/m68k/include/asm/auxvec.h b/arch/m68k/include/asm/auxvec.h
new file mode 100644
index 00000000000..844d6d52204
--- /dev/null
+++ b/arch/m68k/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMm68k_AUXVEC_H
+#define __ASMm68k_AUXVEC_H
+
+#endif
diff --git a/arch/m68k/include/asm/bitsperlong.h b/arch/m68k/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..6dc0bb0c13b
--- /dev/null
+++ b/arch/m68k/include/asm/bitsperlong.h
@@ -0,0 +1 @@
+#include <asm-generic/bitsperlong.h>
diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h
new file mode 100644
index 00000000000..31b260a8880
--- /dev/null
+++ b/arch/m68k/include/asm/byteorder.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _M68K_BYTEORDER_H */
diff --git a/arch/m68k/include/asm/cachectl.h b/arch/m68k/include/asm/cachectl.h
new file mode 100644
index 00000000000..525978e959e
--- /dev/null
+++ b/arch/m68k/include/asm/cachectl.h
@@ -0,0 +1,14 @@
+#ifndef _M68K_CACHECTL_H
+#define _M68K_CACHECTL_H
+
+/* Definitions for the cacheflush system call.  */
+
+#define FLUSH_SCOPE_LINE    1   /* Flush a cache line */
+#define FLUSH_SCOPE_PAGE    2   /* Flush a page */
+#define FLUSH_SCOPE_ALL     3   /* Flush the whole cache -- superuser only */
+
+#define FLUSH_CACHE_DATA    1   /* Writeback and flush data cache */
+#define FLUSH_CACHE_INSN    2   /* Flush instruction cache */
+#define FLUSH_CACHE_BOTH    3   /* Flush both caches */
+
+#endif /* _M68K_CACHECTL_H */
diff --git a/arch/m68k/include/asm/cputime.h b/arch/m68k/include/asm/cputime.h
new file mode 100644
index 00000000000..c79c5e89230
--- /dev/null
+++ b/arch/m68k/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __M68K_CPUTIME_H
+#define __M68K_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __M68K_CPUTIME_H */
diff --git a/arch/m68k/include/asm/device.h b/arch/m68k/include/asm/device.h
new file mode 100644
index 00000000000..d8f9872b0e2
--- /dev/null
+++ b/arch/m68k/include/asm/device.h
@@ -0,0 +1,7 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
diff --git a/arch/m68k/include/asm/emergency-restart.h b/arch/m68k/include/asm/emergency-restart.h
new file mode 100644
index 00000000000..108d8c48e42
--- /dev/null
+++ b/arch/m68k/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m68k/include/asm/entry_mm.h b/arch/m68k/include/asm/entry_mm.h
new file mode 100644
index 00000000000..73b8c8fbed9
--- /dev/null
+++ b/arch/m68k/include/asm/entry_mm.h
@@ -0,0 +1,128 @@
+#ifndef __M68K_ENTRY_H
+#define __M68K_ENTRY_H
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>
+#endif
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ *      This allows access to the syscall arguments in registers d1-d5
+ *
+ *       0(sp) - d1
+ *       4(sp) - d2
+ *       8(sp) - d3
+ *       C(sp) - d4
+ *      10(sp) - d5
+ *      14(sp) - a0
+ *      18(sp) - a1
+ *      1C(sp) - a2
+ *      20(sp) - d0
+ *      24(sp) - orig_d0
+ *      28(sp) - stack adjustment
+ *      2C(sp) - sr
+ *      2E(sp) - pc
+ *      32(sp) - format & vector
+ */
+
+/*
+ * 97/05/14 Andreas: Register %a2 is now set to the current task throughout
+ *                   the whole kernel.
+ */
+
+/* the following macro is used when enabling interrupts */
+#if defined(MACH_ATARI_ONLY)
+        /* block out HSYNC on the atari */
+#define ALLOWINT        (~0x400)
+#define MAX_NOINT_IPL   3
+#else
+        /* portable version */
+#define ALLOWINT        (~0x700)
+#define MAX_NOINT_IPL   0
+#endif /* machine compilation types */
+
+#ifdef __ASSEMBLY__
+
+#define curptr a2
+
+LFLUSH_I_AND_D = 0x00000808
+
+#define SAVE_ALL_INT save_all_int
+#define SAVE_ALL_SYS save_all_sys
+#define RESTORE_ALL restore_all
+/*
+ * This defines the normal kernel pt-regs layout.
+ *
+ * regs a3-a6 and d6-d7 are preserved by C code
+ * the kernel doesn't mess with usp unless it needs to
+ */
+
+/*
+ * a -1 in the orig_d0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro  save_all_int
+        clrl    %sp@-           | stk_adj
+        pea     -1:w            | orig d0
+        movel   %d0,%sp@-       | d0
+        moveml  %d1-%d5/%a0-%a1/%curptr,%sp@-
+.endm
+
+.macro  save_all_sys
+        clrl    %sp@-           | stk_adj
+        movel   %d0,%sp@-       | orig d0
+        movel   %d0,%sp@-       | d0
+        moveml  %d1-%d5/%a0-%a1/%curptr,%sp@-
+.endm
+
+.macro  restore_all
+        moveml  %sp@+,%a0-%a1/%curptr/%d1-%d5
+        movel   %sp@+,%d0
+        addql   #4,%sp          | orig d0
+        addl    %sp@+,%sp       | stk adj
+        rte
+.endm
+
+#define SWITCH_STACK_SIZE (6*4+4)       /* includes return address */
+
+#define SAVE_SWITCH_STACK save_switch_stack
+#define RESTORE_SWITCH_STACK restore_switch_stack
+#define GET_CURRENT(tmp) get_current tmp
+
+.macro  save_switch_stack
+        moveml  %a3-%a6/%d6-%d7,%sp@-
+.endm
+
+.macro  restore_switch_stack
+        moveml  %sp@+,%a3-%a6/%d6-%d7
+.endm
+
+.macro  get_current reg=%d0
+        movel   %sp,\reg
+        andw    #-THREAD_SIZE,\reg
+        movel   \reg,%curptr
+        movel   %curptr@,%curptr
+.endm
+
+#else /* C source */
+
+#define STR(X) STR1(X)
+#define STR1(X) #X
+
+#define SAVE_ALL_INT                            \
+        "clrl   %%sp@-;"    /* stk_adj */       \
+        "pea    -1:w;"      /* orig d0 = -1 */  \
+        "movel  %%d0,%%sp@-;" /* d0 */          \
+        "moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
+#define GET_CURRENT(tmp) \
+        "movel  %%sp,"#tmp"\n\t" \
+        "andw   #-"STR(THREAD_SIZE)","#tmp"\n\t" \
+        "movel  "#tmp",%%a2\n\t" \
+        "movel  %%a2@,%%a2"
+
+#endif
+
+#endif /* __M68K_ENTRY_H */
diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h
new file mode 100644
index 00000000000..68611e3dbb1
--- /dev/null
+++ b/arch/m68k/include/asm/entry_no.h
@@ -0,0 +1,181 @@
+#ifndef __M68KNOMMU_ENTRY_H
+#define __M68KNOMMU_ENTRY_H
+
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ * This allows access to the syscall arguments in registers d1-d5
+ *
+ *       0(sp) - d1
+ *       4(sp) - d2
+ *       8(sp) - d3
+ *       C(sp) - d4
+ *      10(sp) - d5
+ *      14(sp) - a0
+ *      18(sp) - a1
+ *      1C(sp) - a2
+ *      20(sp) - d0
+ *      24(sp) - orig_d0
+ *      28(sp) - stack adjustment
+ *      2C(sp) - [ sr              ] [ format & vector ]
+ *      2E(sp) - [ pc-hiword       ] [ sr              ]
+ *      30(sp) - [ pc-loword       ] [ pc-hiword       ]
+ *      32(sp) - [ format & vector ] [ pc-loword       ]
+ *                ^^^^^^^^^^^^^^^^^   ^^^^^^^^^^^^^^^^^
+ *                      M68K              COLDFIRE
+ */
+
+#define ALLOWINT (~0x700)
+
+#ifdef __ASSEMBLY__
+
+#define SWITCH_STACK_SIZE (6*4+4)       /* Includes return address */
+
+/*
+ * This defines the normal kernel pt-regs layout.
+ *
+ * regs are a2-a6 and d6-d7 preserved by C code
+ * the kernel doesn't mess with usp unless it needs to
+ */
+
+#ifdef CONFIG_COLDFIRE
+#ifdef CONFIG_COLDFIRE_SW_A7
+/*
+ * This is made a little more tricky on older ColdFires. There is no
+ * separate supervisor and user stack pointers. Need to artificially
+ * construct a usp in software... When doing this we need to disable
+ * interrupts, otherwise bad things will happen.
+ */
+.globl sw_usp
+.globl sw_ksp
+
+.macro SAVE_ALL
+        move    #0x2700,%sr             /* disable intrs */
+        btst    #5,%sp@(2)              /* from user? */
+        bnes    6f                      /* no, skip */
+        movel   %sp,sw_usp              /* save user sp */
+        addql   #8,sw_usp               /* remove exception */
+        movel   sw_ksp,%sp              /* kernel sp */
+        subql   #8,%sp                  /* room for exception */
+        clrl    %sp@-                   /* stkadj */
+        movel   %d0,%sp@-               /* orig d0 */
+        movel   %d0,%sp@-               /* d0 */
+        lea     %sp@(-32),%sp           /* space for 8 regs */
+        moveml  %d1-%d5/%a0-%a2,%sp@
+        movel   sw_usp,%a0              /* get usp */
+        movel   %a0@-,%sp@(PT_OFF_PC)   /* copy exception program counter */
+        movel   %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
+        bra     7f
+        6:
+        clrl    %sp@-                   /* stkadj */
+        movel   %d0,%sp@-               /* orig d0 */
+        movel   %d0,%sp@-               /* d0 */
+        lea     %sp@(-32),%sp           /* space for 8 regs */
+        moveml  %d1-%d5/%a0-%a2,%sp@
+        7:
+.endm
+
+.macro RESTORE_USER
+        move    #0x2700,%sr             /* disable intrs */
+        movel   sw_usp,%a0              /* get usp */
+        movel   %sp@(PT_OFF_PC),%a0@-   /* copy exception program counter */
+        movel   %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
+        moveml  %sp@,%d1-%d5/%a0-%a2
+        lea     %sp@(32),%sp            /* space for 8 regs */
+        movel   %sp@+,%d0
+        addql   #4,%sp                  /* orig d0 */
+        addl    %sp@+,%sp               /* stkadj */
+        addql   #8,%sp                  /* remove exception */
+        movel   %sp,sw_ksp              /* save ksp */
+        subql   #8,sw_usp               /* set exception */
+        movel   sw_usp,%sp              /* restore usp */
+        rte
+.endm
+
+.macro RDUSP
+        movel   sw_usp,%a3
+.endm
+
+.macro WRUSP
+        movel   %a3,sw_usp
+.endm
+
+#else /* !CONFIG_COLDFIRE_SW_A7 */
+/*
+ * Modern ColdFire parts have separate supervisor and user stack
+ * pointers. Simple load and restore macros for this case.
+ */
+.macro SAVE_ALL
+        move    #0x2700,%sr             /* disable intrs */
+        clrl    %sp@-                   /* stkadj */
+        movel   %d0,%sp@-               /* orig d0 */
+        movel   %d0,%sp@-               /* d0 */
+        lea     %sp@(-32),%sp           /* space for 8 regs */
+        moveml  %d1-%d5/%a0-%a2,%sp@
+.endm
+
+.macro RESTORE_USER
+        moveml  %sp@,%d1-%d5/%a0-%a2
+        lea     %sp@(32),%sp            /* space for 8 regs */
+        movel   %sp@+,%d0
+        addql   #4,%sp                  /* orig d0 */
+        addl    %sp@+,%sp               /* stkadj */
+        rte
+.endm
+
+.macro RDUSP
+        /*move  %usp,%a3*/
+        .word   0x4e6b
+.endm
+
+.macro WRUSP
+        /*move  %a3,%usp*/
+        .word   0x4e63
+.endm
+
+#endif /* !CONFIG_COLDFIRE_SW_A7 */
+
+.macro SAVE_SWITCH_STACK
+        lea     %sp@(-24),%sp           /* 6 regs */
+        moveml  %a3-%a6/%d6-%d7,%sp@
+.endm
+
+.macro RESTORE_SWITCH_STACK
+        moveml  %sp@,%a3-%a6/%d6-%d7
+        lea     %sp@(24),%sp            /* 6 regs */
+.endm
+
+#else /* !CONFIG_COLDFIRE */
+
+/*
+ * Standard 68k interrupt entry and exit macros.
+ */
+.macro SAVE_ALL
+        clrl    %sp@-                   /* stkadj */
+        movel   %d0,%sp@-               /* orig d0 */
+        movel   %d0,%sp@-               /* d0 */
+        moveml  %d1-%d5/%a0-%a2,%sp@-
+.endm
+
+.macro RESTORE_ALL
+        moveml  %sp@+,%a0-%a2/%d1-%d5
+        movel   %sp@+,%d0
+        addql   #4,%sp                  /* orig d0 */
+        addl    %sp@+,%sp               /* stkadj */
+        rte
+.endm
+
+.macro SAVE_SWITCH_STACK
+        moveml  %a3-%a6/%d6-%d7,%sp@-
+.endm
+
+.macro RESTORE_SWITCH_STACK
+        moveml  %sp@+,%a3-%a6/%d6-%d7
+.endm
+
+#endif /* !COLDFIRE_SW_A7 */
+#endif /* __ASSEMBLY__ */
+#endif /* __M68KNOMMU_ENTRY_H */
diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h
new file mode 100644
index 00000000000..0d4e188d6ef
--- /dev/null
+++ b/arch/m68k/include/asm/errno.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_ERRNO_H
+#define _M68K_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif /* _M68K_ERRNO_H */
diff --git a/arch/m68k/include/asm/fcntl.h b/arch/m68k/include/asm/fcntl.h
new file mode 100644
index 00000000000..1c369b20dc4
--- /dev/null
+++ b/arch/m68k/include/asm/fcntl.h
@@ -0,0 +1,11 @@
+#ifndef _M68K_FCNTL_H
+#define _M68K_FCNTL_H
+
+#define O_DIRECTORY     040000  /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
+#define O_LARGEFILE     0400000
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _M68K_FCNTL_H */
diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h
new file mode 100644
index 00000000000..6a332a9f099
--- /dev/null
+++ b/arch/m68k/include/asm/futex.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <asm-generic/futex.h>
+
+#endif
diff --git a/arch/m68k/include/asm/hw_irq.h b/arch/m68k/include/asm/hw_irq.h
new file mode 100644
index 00000000000..eacef0951fb
--- /dev/null
+++ b/arch/m68k/include/asm/hw_irq.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_M68K_HW_IRQ_H
+#define __ASM_M68K_HW_IRQ_H
+
+/* Dummy include. */
+
+#endif
diff --git a/arch/m68k/include/asm/ioctl.h b/arch/m68k/include/asm/ioctl.h
new file mode 100644
index 00000000000..b279fe06dfe
--- /dev/null
+++ b/arch/m68k/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/m68k/include/asm/ioctls.h b/arch/m68k/include/asm/ioctls.h
new file mode 100644
index 00000000000..1332bb4ca5b
--- /dev/null
+++ b/arch/m68k/include/asm/ioctls.h
@@ -0,0 +1,8 @@
+#ifndef __ARCH_M68K_IOCTLS_H__
+#define __ARCH_M68K_IOCTLS_H__
+
+#define FIOQSIZE        0x545E
+
+#include <asm-generic/ioctls.h>
+
+#endif /* __ARCH_M68K_IOCTLS_H__ */
diff --git a/arch/m68k/include/asm/ipcbuf.h b/arch/m68k/include/asm/ipcbuf.h
new file mode 100644
index 00000000000..a623ea3f095
--- /dev/null
+++ b/arch/m68k/include/asm/ipcbuf.h
@@ -0,0 +1,29 @@
+#ifndef __m68k_IPCBUF_H__
+#define __m68k_IPCBUF_H__
+
+/*
+ * The user_ipc_perm structure for m68k architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned short          __pad1;
+        unsigned short          seq;
+        unsigned short          __pad2;
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* __m68k_IPCBUF_H__ */
diff --git a/arch/m68k/include/asm/irq_regs.h b/arch/m68k/include/asm/irq_regs.h
new file mode 100644
index 00000000000..3dd9c0b7027
--- /dev/null
+++ b/arch/m68k/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/m68k/include/asm/kdebug.h b/arch/m68k/include/asm/kdebug.h
new file mode 100644
index 00000000000..6ece1b03766
--- /dev/null
+++ b/arch/m68k/include/asm/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h
new file mode 100644
index 00000000000..3413cc1390e
--- /dev/null
+++ b/arch/m68k/include/asm/kmap_types.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_M68K_KMAP_TYPES_H
+#define __ASM_M68K_KMAP_TYPES_H
+
+#include <asm-generic/kmap_types.h>
+
+#endif  /* __ASM_M68K_KMAP_TYPES_H */
diff --git a/arch/m68k/include/asm/local.h b/arch/m68k/include/asm/local.h
new file mode 100644
index 00000000000..6c259263e1f
--- /dev/null
+++ b/arch/m68k/include/asm/local.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_M68K_LOCAL_H
+#define _ASM_M68K_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* _ASM_M68K_LOCAL_H */
diff --git a/arch/m68k/include/asm/local64.h b/arch/m68k/include/asm/local64.h
new file mode 100644
index 00000000000..36c93b5cc23
--- /dev/null
+++ b/arch/m68k/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
new file mode 100644
index 00000000000..805714ca8d7
--- /dev/null
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -0,0 +1,255 @@
+/****************************************************************************/
+
+/*
+ *      m5249sim.h -- ColdFire 5249 System Integration Module support.
+ *
+ *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m5249sim_h
+#define m5249sim_h
+/****************************************************************************/
+
+#define CPU_NAME                "COLDFIRE(m5249)"
+#define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ *      The 5249 has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2               0x80000000
+
+/*
+ *      Define the 5249 SIM register set addresses.
+ */
+#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
+#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
+#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
+#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
+#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
+#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
+
+/*
+ *      Timer module.
+ */
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
+
+/*
+ *      UART module.
+ */
+#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
+#define MCFUART_BASE2           0x200           /* Base address of UART2 */
+
+/*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
+#define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
+#define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
+
+/*
+ *      Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
+#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
+#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
+#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
+#define MCFSIM_QSPIICR          MCFSIM_ICR10    /* QSPI ICR */
+
+/*
+ *      Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_QSPI            28              /* QSPI, Level 4 */
+#define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
+
+/*
+ *      General purpose IO registers (in MBAR2).
+ */
+#define MCFSIM2_GPIOREAD        (MCF_MBAR2 + 0x000)     /* GPIO read values */
+#define MCFSIM2_GPIOWRITE       (MCF_MBAR2 + 0x004)     /* GPIO write values */
+#define MCFSIM2_GPIOENABLE      (MCF_MBAR2 + 0x008)     /* GPIO enabled */
+#define MCFSIM2_GPIOFUNC        (MCF_MBAR2 + 0x00C)     /* GPIO function */
+#define MCFSIM2_GPIO1READ       (MCF_MBAR2 + 0x0B0)     /* GPIO1 read values */
+#define MCFSIM2_GPIO1WRITE      (MCF_MBAR2 + 0x0B4)     /* GPIO1 write values */
+#define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
+#define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
+
+#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
+#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
+#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
+
+#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
+#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
+#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
+#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
+#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
+#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
+#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
+#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
+
+#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
+
+#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
+
+/*
+ * Define the base interrupt for the second interrupt controller.
+ * We set it to 128, out of the way of the base interrupts, and plenty
+ * of room for its 64 interrupts.
+ */
+#define MCFINTC2_VECBASE        128
+
+#define MCFINTC2_GPIOIRQ0       (MCFINTC2_VECBASE + 32)
+#define MCFINTC2_GPIOIRQ1       (MCFINTC2_VECBASE + 33)
+#define MCFINTC2_GPIOIRQ2       (MCFINTC2_VECBASE + 34)
+#define MCFINTC2_GPIOIRQ3       (MCFINTC2_VECBASE + 35)
+#define MCFINTC2_GPIOIRQ4       (MCFINTC2_VECBASE + 36)
+#define MCFINTC2_GPIOIRQ5       (MCFINTC2_VECBASE + 37)
+#define MCFINTC2_GPIOIRQ6       (MCFINTC2_VECBASE + 38)
+#define MCFINTC2_GPIOIRQ7       (MCFINTC2_VECBASE + 39)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX         64
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
+
+/****************************************************************************/
+
+#ifdef __ASSEMBLER__
+
+/*
+ *      The M5249C3 board needs a little help getting all its SIM devices
+ *      initialized at kernel start time. dBUG doesn't set much up, so
+ *      we need to do it manually.
+ */
+.macro m5249c3_setup
+        /*
+         *      Set MBAR1 and MBAR2, just incase they are not set.
+         */
+        movel   #0x10000001,%a0
+        movec   %a0,%MBAR                       /* map MBAR region */
+        subql   #1,%a0                          /* get MBAR address in a0 */
+
+        movel   #0x80000001,%a1
+        movec   %a1,#3086                       /* map MBAR2 region */
+        subql   #1,%a1                          /* get MBAR2 address in a1 */
+
+        /*
+         *      Move secondary interrupts to their base (128).
+         */
+        moveb   #MCFINTC2_VECBASE,%d0
+        moveb   %d0,0x16b(%a1)                  /* interrupt base register */
+
+        /*
+         *      Work around broken CSMR0/DRAM vector problem.
+         */
+        movel   #0x001F0021,%d0                 /* disable C/I bit */
+        movel   %d0,0x84(%a0)                   /* set CSMR0 */
+
+        /*
+         *      Disable the PLL firstly. (Who knows what state it is
+         *      in here!).
+         */
+        movel   0x180(%a1),%d0                  /* get current PLL value */
+        andl    #0xfffffffe,%d0                 /* PLL bypass first */
+        movel   %d0,0x180(%a1)                  /* set PLL register */
+        nop
+
+#if CONFIG_CLOCK_FREQ == 140000000
+        /*
+         *      Set initial clock frequency. This assumes M5249C3 board
+         *      is fitted with 11.2896MHz crystal. It will program the
+         *      PLL for 140MHz. Lets go fast :-)
+         */
+        movel   #0x125a40f0,%d0                 /* set for 140MHz */
+        movel   %d0,0x180(%a1)                  /* set PLL register */
+        orl     #0x1,%d0
+        movel   %d0,0x180(%a1)                  /* set PLL register */
+#endif
+
+        /*
+         *      Setup CS1 for ethernet controller.
+         *      (Setup as per M5249C3 doco).
+         */
+        movel  #0xe0000000,%d0                  /* CS1 mapped at 0xe0000000 */
+        movel  %d0,0x8c(%a0)
+        movel  #0x001f0021,%d0                  /* CS1 size of 1Mb */
+        movel  %d0,0x90(%a0)
+        movew  #0x0080,%d0                      /* CS1 = 16bit port, AA */
+        movew  %d0,0x96(%a0)
+
+        /*
+         *      Setup CS2 for IDE interface.
+         */
+        movel   #0x50000000,%d0                 /* CS2 mapped at 0x50000000 */
+        movel   %d0,0x98(%a0)
+        movel   #0x001f0001,%d0                 /* CS2 size of 1MB */
+        movel   %d0,0x9c(%a0)
+        movew   #0x0080,%d0                     /* CS2 = 16bit, TA */
+        movew   %d0,0xa2(%a0)
+
+        movel   #0x00107000,%d0                 /* IDEconfig1 */
+        movel   %d0,0x18c(%a1)
+        movel   #0x000c0400,%d0                 /* IDEconfig2 */
+        movel   %d0,0x190(%a1)
+
+        movel   #0x00080000,%d0                 /* GPIO19, IDE reset bit */
+        orl     %d0,0xc(%a1)                    /* function GPIO19 */
+        orl     %d0,0x8(%a1)                    /* enable GPIO19 as output */
+        orl     %d0,0x4(%a1)                    /* de-assert IDE reset */
+.endm
+
+#define PLATFORM_SETUP  m5249c3_setup
+
+#endif /* __ASSEMBLER__ */
+
+/****************************************************************************/
+#endif  /* m5249sim_h */
diff --git a/arch/m68k/include/asm/mac_mouse.h b/arch/m68k/include/asm/mac_mouse.h
new file mode 100644
index 00000000000..39a5c292eae
--- /dev/null
+++ b/arch/m68k/include/asm/mac_mouse.h
@@ -0,0 +1,23 @@
+#ifndef _ASM_MAC_MOUSE_H
+#define _ASM_MAC_MOUSE_H
+
+/*
+ * linux/include/asm-m68k/mac_mouse.h
+ * header file for Macintosh ADB mouse driver
+ * 27-10-97 Michael Schmitz
+ * copied from:
+ * header file for Atari Mouse driver
+ * by Robert de Vries (robert@and.nl) on 19Jul93
+ */
+
+struct mouse_status {
+        char            buttons;
+        short           dx;
+        short           dy;
+        int             ready;
+        int             active;
+        wait_queue_head_t wait;
+        struct fasync_struct *fasyncptr;
+};
+
+#endif
diff --git a/arch/m68k/include/asm/mcfmbus.h b/arch/m68k/include/asm/mcfmbus.h
new file mode 100644
index 00000000000..319899c47a2
--- /dev/null
+++ b/arch/m68k/include/asm/mcfmbus.h
@@ -0,0 +1,77 @@
+/****************************************************************************/
+
+/*
+ *      mcfmbus.h -- Coldfire MBUS support defines.
+ *
+ *      (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) 
+ */
+
+/****************************************************************************/
+
+
+#ifndef mcfmbus_h
+#define mcfmbus_h
+
+
+#define MCFMBUS_BASE            0x280
+#define MCFMBUS_IRQ_VECTOR      0x19
+#define MCFMBUS_IRQ             0x1
+#define MCFMBUS_CLK             0x3f
+#define MCFMBUS_IRQ_LEVEL       0x07    /*IRQ Level 1*/
+#define MCFMBUS_ADDRESS         0x01
+
+
+/*
+*       Define the 5307 MBUS register set addresses
+*/
+
+#define MCFMBUS_MADR    0x00
+#define MCFMBUS_MFDR    0x04
+#define MCFMBUS_MBCR    0x08
+#define MCFMBUS_MBSR    0x0C
+#define MCFMBUS_MBDR    0x10
+
+
+#define MCFMBUS_MADR_ADDR(a)    (((a)&0x7F)<<0x01) /*Slave Address*/
+
+#define MCFMBUS_MFDR_MBC(a)     ((a)&0x3F)         /*M-Bus Clock*/
+
+/*
+*       Define bit flags in Control Register
+*/
+
+#define MCFMBUS_MBCR_MEN           (0x80)  /* M-Bus Enable                 */
+#define MCFMBUS_MBCR_MIEN          (0x40)  /* M-Bus Interrupt Enable       */
+#define MCFMBUS_MBCR_MSTA          (0x20)  /* Master/Slave Mode Select Bit */
+#define MCFMBUS_MBCR_MTX           (0x10)  /* Transmit/Rcv Mode Select Bit */
+#define MCFMBUS_MBCR_TXAK          (0x08)  /* Transmit Acknowledge Enable  */
+#define MCFMBUS_MBCR_RSTA          (0x04)  /* Repeat Start                 */
+
+/*
+*       Define bit flags in Status Register
+*/
+
+#define MCFMBUS_MBSR_MCF           (0x80)  /* Data Transfer Complete       */
+#define MCFMBUS_MBSR_MAAS          (0x40)  /* Addressed as a Slave         */
+#define MCFMBUS_MBSR_MBB           (0x20)  /* Bus Busy                     */
+#define MCFMBUS_MBSR_MAL           (0x10)  /* Arbitration Lost             */
+#define MCFMBUS_MBSR_SRW           (0x04)  /* Slave Transmit               */
+#define MCFMBUS_MBSR_MIF           (0x02)  /* M-Bus Interrupt              */
+#define MCFMBUS_MBSR_RXAK          (0x01)  /* No Acknowledge Received      */
+
+/*
+*       Define bit flags in DATA I/O Register
+*/
+
+#define MCFMBUS_MBDR_READ          (0x01)  /* 1=read 0=write MBUS */
+
+#define MBUSIOCSCLOCK           1
+#define MBUSIOCGCLOCK           2
+#define MBUSIOCSADDR                    3
+#define MBUSIOCGADDR                    4
+#define MBUSIOCSSLADDR                  5
+#define MBUSIOCGSLADDR                  6
+#define MBUSIOCSSUBADDR                 7
+#define MBUSIOCGSUBADDR                 8
+
+#endif
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcfne.h
new file mode 100644
index 00000000000..bf638be0958
--- /dev/null
+++ b/arch/m68k/include/asm/mcfne.h
@@ -0,0 +1,242 @@
+/****************************************************************************/
+
+/*
+ *      mcfne.h -- NE2000 in ColdFire eval boards.
+ *
+ *      (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000,      Lineo (www.lineo.com)
+ *      (C) Copyright 2001,      SnapGear (www.snapgear.com)
+ *
+ *      19990409 David W. Miller  Converted from m5206ne.h for 5307 eval board
+ *
+ *      Hacked support for m5206e Cadre III evaluation board
+ *      Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
+ */
+
+/****************************************************************************/
+#ifndef mcfne_h
+#define mcfne_h
+/****************************************************************************/
+
+
+/*
+ *      Support for NE2000 clones devices in ColdFire based boards.
+ *      Not all boards address these parts the same way, some use a
+ *      direct addressing method, others use a side-band address space
+ *      to access odd address registers, some require byte swapping
+ *      others do not.
+ */
+#define BSWAP(w)        (((w) << 8) | ((w) >> 8))
+#define RSWAP(w)        (w)
+
+
+/*
+ *      Define the basic hardware resources of NE2000 boards.
+ */
+
+#if defined(CONFIG_ARN5206)
+#define NE2000_ADDR             0x40000300
+#define NE2000_ODDOFFSET        0x00010000
+#define NE2000_IRQ_VECTOR       0xf0
+#define NE2000_IRQ_PRIORITY     2
+#define NE2000_IRQ_LEVEL        4
+#define NE2000_BYTE             volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5206eC3)
+#define NE2000_ADDR             0x40000300
+#define NE2000_ODDOFFSET        0x00010000
+#define NE2000_IRQ_VECTOR       0x1c
+#define NE2000_IRQ_PRIORITY     2
+#define NE2000_IRQ_LEVEL        4
+#define NE2000_BYTE             volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
+#define NE2000_ADDR             0x30000300
+#define NE2000_IRQ_VECTOR       25
+#define NE2000_IRQ_PRIORITY     1
+#define NE2000_IRQ_LEVEL        3
+#define NE2000_BYTE             volatile unsigned char
+#endif
+
+#if defined(CONFIG_M5307C3)
+#define NE2000_ADDR             0x40000300
+#define NE2000_ODDOFFSET        0x00010000
+#define NE2000_IRQ_VECTOR       0x1b
+#define NE2000_BYTE             volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
+#define NE2000_ADDR             0x30600300
+#define NE2000_ODDOFFSET        0x00008000
+#define NE2000_IRQ_VECTOR       67
+#undef  BSWAP
+#define BSWAP(w)                (w)
+#define NE2000_BYTE             volatile unsigned short
+#undef  RSWAP
+#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_M5307) && defined(CONFIG_NETtel)
+#define NE2000_ADDR0            0x30600300
+#define NE2000_ADDR1            0x30800300
+#define NE2000_ODDOFFSET        0x00008000
+#define NE2000_IRQ_VECTOR0      27
+#define NE2000_IRQ_VECTOR1      29
+#undef  BSWAP
+#define BSWAP(w)                (w)
+#define NE2000_BYTE             volatile unsigned short
+#undef  RSWAP
+#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
+#define NE2000_ADDR             0x30600300
+#define NE2000_ODDOFFSET        0x00008000
+#define NE2000_IRQ_VECTOR       27
+#undef  BSWAP
+#define BSWAP(w)                (w)
+#define NE2000_BYTE             volatile unsigned short
+#undef  RSWAP
+#define RSWAP(w)                (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_ARN5307)
+#define NE2000_ADDR             0xfe600300
+#define NE2000_ODDOFFSET        0x00010000
+#define NE2000_IRQ_VECTOR       0x1b
+#define NE2000_IRQ_PRIORITY     2
+#define NE2000_IRQ_LEVEL        3
+#define NE2000_BYTE             volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5407C3)
+#define NE2000_ADDR             0x40000300
+#define NE2000_ODDOFFSET        0x00010000
+#define NE2000_IRQ_VECTOR       0x1b
+#define NE2000_BYTE             volatile unsigned short
+#endif
+
+/****************************************************************************/
+
+/*
+ *      Side-band address space for odd address requires re-mapping
+ *      many of the standard ISA access functions.
+ */
+#ifdef NE2000_ODDOFFSET
+
+#undef outb
+#undef outb_p
+#undef inb
+#undef inb_p
+#undef outsb
+#undef outsw
+#undef insb
+#undef insw
+
+#define outb    ne2000_outb
+#define inb     ne2000_inb
+#define outb_p  ne2000_outb
+#define inb_p   ne2000_inb
+#define outsb   ne2000_outsb
+#define outsw   ne2000_outsw
+#define insb    ne2000_insb
+#define insw    ne2000_insw
+
+
+#ifndef COLDFIRE_NE2000_FUNCS
+
+void ne2000_outb(unsigned int val, unsigned int addr);
+int  ne2000_inb(unsigned int addr);
+void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
+void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
+void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
+void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
+
+#else
+
+/*
+ *      This macro converts a conventional register address into the
+ *      real memory pointer of the mapped NE2000 device.
+ *      On most NE2000 implementations on ColdFire boards the chip is
+ *      mapped in kinda funny, due to its ISA heritage.
+ */
+#define NE2000_PTR(addr)        ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
+#define NE2000_DATA_PTR(addr)   (addr)
+
+
+void ne2000_outb(unsigned int val, unsigned int addr)
+{
+        NE2000_BYTE     *rp;
+
+        rp = (NE2000_BYTE *) NE2000_PTR(addr);
+        *rp = RSWAP(val);
+}
+
+int ne2000_inb(unsigned int addr)
+{
+        NE2000_BYTE     *rp, val;
+
+        rp = (NE2000_BYTE *) NE2000_PTR(addr);
+        val = *rp;
+        return((int) ((NE2000_BYTE) RSWAP(val)));
+}
+
+void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
+{
+        NE2000_BYTE     *rp, val;
+        unsigned char   *buf;
+
+        buf = (unsigned char *) vbuf;
+        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
+        for (; (len > 0); len--) {
+                val = *rp;
+                *buf++ = RSWAP(val);
+        }
+}
+
+void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
+{
+        volatile unsigned short *rp;
+        unsigned short          w, *buf;
+
+        buf = (unsigned short *) vbuf;
+        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
+        for (; (len > 0); len--) {
+                w = *rp;
+                *buf++ = BSWAP(w);
+        }
+}
+
+void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
+{
+        NE2000_BYTE     *rp, val;
+        unsigned char   *buf;
+
+        buf = (unsigned char *) vbuf;
+        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
+        for (; (len > 0); len--) {
+                val = *buf++;
+                *rp = RSWAP(val);
+        }
+}
+
+void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
+{
+        volatile unsigned short *rp;
+        unsigned short          w, *buf;
+
+        buf = (unsigned short *) vbuf;
+        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
+        for (; (len > 0); len--) {
+                w = *buf++;
+                *rp = BSWAP(w);
+        }
+}
+
+#endif /* COLDFIRE_NE2000_FUNCS */
+#endif /* NE2000_OFFOFFSET */
+
+/****************************************************************************/
+#endif  /* mcfne_h */
diff --git a/arch/m68k/include/asm/mman.h b/arch/m68k/include/asm/mman.h
new file mode 100644
index 00000000000..8eebf89f5ab
--- /dev/null
+++ b/arch/m68k/include/asm/mman.h
@@ -0,0 +1 @@
+#include <asm-generic/mman.h>
diff --git a/arch/m68k/include/asm/msgbuf.h b/arch/m68k/include/asm/msgbuf.h
new file mode 100644
index 00000000000..243cb798de8
--- /dev/null
+++ b/arch/m68k/include/asm/msgbuf.h
@@ -0,0 +1,31 @@
+#ifndef _M68K_MSGBUF_H
+#define _M68K_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for m68k architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned long   __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned long   __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long   __unused3;
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _M68K_MSGBUF_H */
diff --git a/arch/m68k/include/asm/mutex.h b/arch/m68k/include/asm/mutex.h
new file mode 100644
index 00000000000..458c1f7fbc1
--- /dev/null
+++ b/arch/m68k/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/m68k/include/asm/param.h b/arch/m68k/include/asm/param.h
new file mode 100644
index 00000000000..36265ccf5c7
--- /dev/null
+++ b/arch/m68k/include/asm/param.h
@@ -0,0 +1,12 @@
+#ifndef _M68K_PARAM_H
+#define _M68K_PARAM_H
+
+#ifdef __uClinux__
+#define EXEC_PAGESIZE   4096
+#else
+#define EXEC_PAGESIZE   8192
+#endif
+
+#include <asm-generic/param.h>
+
+#endif /* _M68K_PARAM_H */
diff --git a/arch/m68k/include/asm/percpu.h b/arch/m68k/include/asm/percpu.h
new file mode 100644
index 00000000000..0859d048faf
--- /dev/null
+++ b/arch/m68k/include/asm/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_M68K_PERCPU_H
+#define __ASM_M68K_PERCPU_H
+
+#include <asm-generic/percpu.h>
+
+#endif  /* __ASM_M68K_PERCPU_H */
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
new file mode 100644
index 00000000000..119ee686dbd
--- /dev/null
+++ b/arch/m68k/include/asm/pinmux.h
@@ -0,0 +1,30 @@
+/*
+ * Coldfire generic GPIO pinmux support.
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef pinmux_h
+#define pinmux_h
+
+#define MCFPINMUX_NONE          -1
+
+extern int mcf_pinmux_request(unsigned, unsigned);
+extern void mcf_pinmux_release(unsigned, unsigned);
+
+static inline int mcf_pinmux_is_valid(unsigned pinmux)
+{
+        return pinmux != MCFPINMUX_NONE;
+}
+
+#endif
+
diff --git a/arch/m68k/include/asm/poll.h b/arch/m68k/include/asm/poll.h
new file mode 100644
index 00000000000..f080fcdb61b
--- /dev/null
+++ b/arch/m68k/include/asm/poll.h
@@ -0,0 +1,9 @@
+#ifndef __m68k_POLL_H
+#define __m68k_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      256
+
+#include <asm-generic/poll.h>
+
+#endif
diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h
new file mode 100644
index 00000000000..98d0970d9ba
--- /dev/null
+++ b/arch/m68k/include/asm/posix_types.h
@@ -0,0 +1,61 @@
+#ifndef __ARCH_M68K_POSIX_TYPES_H
+#define __ARCH_M68K_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef  __FD_SET
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef  __FD_CLR
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef  __FD_ISSET
+#define __FD_ISSET(d, set)      (!!((set)->fds_bits[__FDELT(d)] & __FDMASK(d)))
+
+#undef  __FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) */
+
+#endif
diff --git a/arch/m68k/include/asm/resource.h b/arch/m68k/include/asm/resource.h
new file mode 100644
index 00000000000..e7d35019f33
--- /dev/null
+++ b/arch/m68k/include/asm/resource.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_RESOURCE_H
+#define _M68K_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif /* _M68K_RESOURCE_H */
diff --git a/arch/m68k/include/asm/sbus.h b/arch/m68k/include/asm/sbus.h
new file mode 100644
index 00000000000..bfe3ba147f2
--- /dev/null
+++ b/arch/m68k/include/asm/sbus.h
@@ -0,0 +1,45 @@
+/*
+ * some sbus structures and macros to make usage of sbus drivers possible
+ */
+
+#ifndef __M68K_SBUS_H
+#define __M68K_SBUS_H
+
+struct sbus_dev {
+        struct {
+                unsigned int which_io;
+                unsigned int phys_addr;
+        } reg_addrs[1];
+};
+
+/* sbus IO functions stolen from include/asm-sparc/io.h for the serial driver */
+/* No SBUS on the Sun3, kludge -- sam */
+
+static inline void _sbus_writeb(unsigned char val, unsigned long addr)
+{
+        *(volatile unsigned char *)addr = val;
+}
+
+static inline unsigned char _sbus_readb(unsigned long addr)
+{
+        return *(volatile unsigned char *)addr;
+}
+
+static inline void _sbus_writel(unsigned long val, unsigned long addr)
+{
+        *(volatile unsigned long *)addr = val;
+
+}
+
+extern inline unsigned long _sbus_readl(unsigned long addr)
+{
+        return *(volatile unsigned long *)addr;
+}
+
+
+#define sbus_readb(a) _sbus_readb((unsigned long)a)
+#define sbus_writeb(v, a) _sbus_writeb(v, (unsigned long)a)
+#define sbus_readl(a) _sbus_readl((unsigned long)a)
+#define sbus_writel(v, a) _sbus_writel(v, (unsigned long)a)
+
+#endif
diff --git a/arch/m68k/include/asm/scatterlist.h b/arch/m68k/include/asm/scatterlist.h
new file mode 100644
index 00000000000..312505452a1
--- /dev/null
+++ b/arch/m68k/include/asm/scatterlist.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_SCATTERLIST_H
+#define _M68K_SCATTERLIST_H
+
+#include <asm-generic/scatterlist.h>
+
+#endif /* !(_M68K_SCATTERLIST_H) */
diff --git a/arch/m68k/include/asm/sections.h b/arch/m68k/include/asm/sections.h
new file mode 100644
index 00000000000..d64967ecfec
--- /dev/null
+++ b/arch/m68k/include/asm/sections.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_M68K_SECTIONS_H
+#define _ASM_M68K_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif /* _ASM_M68K_SECTIONS_H */
diff --git a/arch/m68k/include/asm/sembuf.h b/arch/m68k/include/asm/sembuf.h
new file mode 100644
index 00000000000..2308052a8c2
--- /dev/null
+++ b/arch/m68k/include/asm/sembuf.h
@@ -0,0 +1,25 @@
+#ifndef _M68K_SEMBUF_H
+#define _M68K_SEMBUF_H
+
+/*
+ * The semid64_ds structure for m68k architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused1;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   __unused2;
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _M68K_SEMBUF_H */
diff --git a/arch/m68k/include/asm/shm.h b/arch/m68k/include/asm/shm.h
new file mode 100644
index 00000000000..fa56ec84a12
--- /dev/null
+++ b/arch/m68k/include/asm/shm.h
@@ -0,0 +1,31 @@
+#ifndef _M68K_SHM_H
+#define _M68K_SHM_H
+
+
+/* format of page table entries that correspond to shared memory pages
+   currently out in swap space (see also mm/swap.c):
+   bits 0-1 (PAGE_PRESENT) is  = 0
+   bits 8..2 (SWP_TYPE) are = SHM_SWP_TYPE
+   bits 31..9 are used like this:
+   bits 15..9 (SHM_ID) the id of the shared memory segment
+   bits 30..16 (SHM_IDX) the index of the page within the shared memory segment
+                    (actually only bits 25..16 get used since SHMMAX is so low)
+   bit 31 (SHM_READ_ONLY) flag whether the page belongs to a read-only attach
+*/
+/* on the m68k both bits 0 and 1 must be zero */
+/* format on the sun3 is similar, but bits 30, 31 are set to zero and all
+   others are reduced by 2. --m */
+
+#ifndef CONFIG_SUN3
+#define SHM_ID_SHIFT    9
+#else
+#define SHM_ID_SHIFT    7
+#endif
+#define _SHM_ID_BITS    7
+#define SHM_ID_MASK     ((1<<_SHM_ID_BITS)-1)
+
+#define SHM_IDX_SHIFT   (SHM_ID_SHIFT+_SHM_ID_BITS)
+#define _SHM_IDX_BITS   15
+#define SHM_IDX_MASK    ((1<<_SHM_IDX_BITS)-1)
+
+#endif /* _M68K_SHM_H */
diff --git a/arch/m68k/include/asm/shmbuf.h b/arch/m68k/include/asm/shmbuf.h
new file mode 100644
index 00000000000..f8928d62f1b
--- /dev/null
+++ b/arch/m68k/include/asm/shmbuf.h
@@ -0,0 +1,42 @@
+#ifndef _M68K_SHMBUF_H
+#define _M68K_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for m68k architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned long           __unused1;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned long           __unused2;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned long           __unused3;
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _M68K_SHMBUF_H */
diff --git a/arch/m68k/include/asm/shmparam.h b/arch/m68k/include/asm/shmparam.h
new file mode 100644
index 00000000000..558892a2efb
--- /dev/null
+++ b/arch/m68k/include/asm/shmparam.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_SHMPARAM_H
+#define _M68K_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
+
+#endif /* _M68K_SHMPARAM_H */
diff --git a/arch/m68k/include/asm/sigcontext.h b/arch/m68k/include/asm/sigcontext.h
new file mode 100644
index 00000000000..a29dd74a17c
--- /dev/null
+++ b/arch/m68k/include/asm/sigcontext.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_M68k_SIGCONTEXT_H
+#define _ASM_M68k_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long  sc_mask;         /* old sigmask */
+        unsigned long  sc_usp;          /* old user stack pointer */
+        unsigned long  sc_d0;
+        unsigned long  sc_d1;
+        unsigned long  sc_a0;
+        unsigned long  sc_a1;
+#ifdef __uClinux__
+        unsigned long  sc_a5;
+#endif
+        unsigned short sc_sr;
+        unsigned long  sc_pc;
+        unsigned short sc_formatvec;
+#ifndef __uClinux__
+# ifdef __mcoldfire__
+        unsigned long  sc_fpregs[2][2]; /* room for two fp registers */
+# else
+        unsigned long  sc_fpregs[2*3];  /* room for two fp registers */
+# endif
+        unsigned long  sc_fpcntl[3];
+        unsigned char  sc_fpstate[216];
+#endif
+};
+
+#endif
diff --git a/arch/m68k/include/asm/siginfo.h b/arch/m68k/include/asm/siginfo.h
new file mode 100644
index 00000000000..851d3d784b5
--- /dev/null
+++ b/arch/m68k/include/asm/siginfo.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_SIGINFO_H
+#define _M68K_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif
diff --git a/arch/m68k/include/asm/socket.h b/arch/m68k/include/asm/socket.h
new file mode 100644
index 00000000000..9bf49c87d95
--- /dev/null
+++ b/arch/m68k/include/asm/socket.h
@@ -0,0 +1,65 @@
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC             31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#define SO_TIMESTAMPING         37
+#define SCM_TIMESTAMPING        SO_TIMESTAMPING
+
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
+
+#define SO_RXQ_OVFL             40
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/m68k/include/asm/sockios.h b/arch/m68k/include/asm/sockios.h
new file mode 100644
index 00000000000..c04a23943cb
--- /dev/null
+++ b/arch/m68k/include/asm/sockios.h
@@ -0,0 +1,13 @@
+#ifndef __ARCH_M68K_SOCKIOS__
+#define __ARCH_M68K_SOCKIOS__
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* __ARCH_M68K_SOCKIOS__ */
diff --git a/arch/m68k/include/asm/spinlock.h b/arch/m68k/include/asm/spinlock.h
new file mode 100644
index 00000000000..20f46e27b53
--- /dev/null
+++ b/arch/m68k/include/asm/spinlock.h
@@ -0,0 +1,6 @@
+#ifndef __M68K_SPINLOCK_H
+#define __M68K_SPINLOCK_H
+
+#error "m68k doesn't do SMP yet"
+
+#endif
diff --git a/arch/m68k/include/asm/stat.h b/arch/m68k/include/asm/stat.h
new file mode 100644
index 00000000000..dd38bc2e9f9
--- /dev/null
+++ b/arch/m68k/include/asm/stat.h
@@ -0,0 +1,77 @@
+#ifndef _M68K_STAT_H
+#define _M68K_STAT_H
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long  st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  __unused1;
+        unsigned long  st_mtime;
+        unsigned long  __unused2;
+        unsigned long  st_ctime;
+        unsigned long  __unused3;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned long long      st_dev;
+        unsigned char   __pad1[2];
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned long long      st_rdev;
+        unsigned char   __pad3[2];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+        unsigned long long      st_blocks;      /* Number 512-byte blocks allocated. */
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+
+        unsigned long long      st_ino;
+};
+
+#endif /* _M68K_STAT_H */
diff --git a/arch/m68k/include/asm/statfs.h b/arch/m68k/include/asm/statfs.h
new file mode 100644
index 00000000000..08d93f14e06
--- /dev/null
+++ b/arch/m68k/include/asm/statfs.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_STATFS_H
+#define _M68K_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif /* _M68K_STATFS_H */
diff --git a/arch/m68k/include/asm/swab.h b/arch/m68k/include/asm/swab.h
new file mode 100644
index 00000000000..b7b37a40def
--- /dev/null
+++ b/arch/m68k/include/asm/swab.h
@@ -0,0 +1,27 @@
+#ifndef _M68K_SWAB_H
+#define _M68K_SWAB_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#define __SWAB_64_THRU_32__
+
+#if defined (__mcfisaaplus__) || defined (__mcfisac__)
+static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
+{
+        __asm__("byterev %0" : "=d" (val) : "0" (val));
+        return val;
+}
+
+#define __arch_swab32 __arch_swab32
+#elif !defined(__mcoldfire__)
+
+static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
+{
+        __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val));
+        return val;
+}
+#define __arch_swab32 __arch_swab32
+#endif
+
+#endif /* _M68K_SWAB_H */
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h
new file mode 100644
index 00000000000..47b01f4726b
--- /dev/null
+++ b/arch/m68k/include/asm/system.h
@@ -0,0 +1,193 @@
+#ifndef _M68K_SYSTEM_H
+#define _M68K_SYSTEM_H
+
+#include <linux/linkage.h>
+#include <linux/kernel.h>
+#include <linux/irqflags.h>
+#include <asm/segment.h>
+#include <asm/entry.h>
+
+#ifdef __KERNEL__
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.  This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ */
+/*
+ * switch_to() saves the extra registers, that are not saved
+ * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
+ * a0-a1. Some of these are used by schedule() and its predecessors
+ * and so we might get see unexpected behaviors when a task returns
+ * with unexpected register values.
+ *
+ * syscall stores these registers itself and none of them are used
+ * by syscall after the function in the syscall has been called.
+ *
+ * Beware that resume now expects *next to be in d1 and the offset of
+ * tss to be in a1. This saves a few instructions as we no longer have
+ * to push them onto the stack and read them back right after.
+ *
+ * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
+ *
+ * Changed 96/09/19 by Andreas Schwab
+ * pass prev in a0, next in a1
+ */
+asmlinkage void resume(void);
+#define switch_to(prev,next,last) do { \
+  register void *_prev __asm__ ("a0") = (prev); \
+  register void *_next __asm__ ("a1") = (next); \
+  register void *_last __asm__ ("d1"); \
+  __asm__ __volatile__("jbsr resume" \
+                       : "=a" (_prev), "=a" (_next), "=d" (_last) \
+                       : "0" (_prev), "1" (_next) \
+                       : "d0", "d2", "d3", "d4", "d5"); \
+  (last) = _last; \
+} while (0)
+
+
+/*
+ * Force strict CPU ordering.
+ * Not really required on m68k...
+ */
+#define nop()           do { asm volatile ("nop"); barrier(); } while (0)
+#define mb()            barrier()
+#define rmb()           barrier()
+#define wmb()           barrier()
+#define read_barrier_depends()  ((void)0)
+#define set_mb(var, value)      ({ (var) = (value); wmb(); })
+
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      ((void)0)
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+#ifndef CONFIG_RMW_INSNS
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        unsigned long flags, tmp;
+
+        local_irq_save(flags);
+
+        switch (size) {
+        case 1:
+                tmp = *(u8 *)ptr;
+                *(u8 *)ptr = x;
+                x = tmp;
+                break;
+        case 2:
+                tmp = *(u16 *)ptr;
+                *(u16 *)ptr = x;
+                x = tmp;
+                break;
+        case 4:
+                tmp = *(u32 *)ptr;
+                *(u32 *)ptr = x;
+                x = tmp;
+                break;
+        default:
+                BUG();
+        }
+
+        local_irq_restore(flags);
+        return x;
+}
+#else
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+            case 1:
+                __asm__ __volatile__
+                        ("moveb %2,%0\n\t"
+                         "1:\n\t"
+                         "casb %0,%1,%2\n\t"
+                         "jne 1b"
+                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+            case 2:
+                __asm__ __volatile__
+                        ("movew %2,%0\n\t"
+                         "1:\n\t"
+                         "casw %0,%1,%2\n\t"
+                         "jne 1b"
+                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+            case 4:
+                __asm__ __volatile__
+                        ("movel %2,%0\n\t"
+                         "1:\n\t"
+                         "casl %0,%1,%2\n\t"
+                         "jne 1b"
+                         : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        }
+        return x;
+}
+#endif
+
+#include <asm-generic/cmpxchg-local.h>
+
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+#ifdef CONFIG_RMW_INSNS
+#define __HAVE_ARCH_CMPXCHG     1
+
+static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
+                                      unsigned long new, int size)
+{
+        switch (size) {
+        case 1:
+                __asm__ __volatile__ ("casb %0,%2,%1"
+                                      : "=d" (old), "=m" (*(char *)p)
+                                      : "d" (new), "0" (old), "m" (*(char *)p));
+                break;
+        case 2:
+                __asm__ __volatile__ ("casw %0,%2,%1"
+                                      : "=d" (old), "=m" (*(short *)p)
+                                      : "d" (new), "0" (old), "m" (*(short *)p));
+                break;
+        case 4:
+                __asm__ __volatile__ ("casl %0,%2,%1"
+                                      : "=d" (old), "=m" (*(int *)p)
+                                      : "d" (new), "0" (old), "m" (*(int *)p));
+                break;
+        }
+        return old;
+}
+
+#define cmpxchg(ptr, o, n)                                                  \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),           \
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg_local(ptr, o, n)                                            \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),           \
+                        (unsigned long)(n), sizeof(*(ptr))))
+#else
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                               \
+        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+                        (unsigned long)(n), sizeof(*(ptr))))
+
+#include <asm-generic/cmpxchg.h>
+
+#endif
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif /* _M68K_SYSTEM_H */
diff --git a/arch/m68k/include/asm/termbits.h b/arch/m68k/include/asm/termbits.h
new file mode 100644
index 00000000000..aea1e37b765
--- /dev/null
+++ b/arch/m68k/include/asm/termbits.h
@@ -0,0 +1,201 @@
+#ifndef __ARCH_M68K_TERMBITS_H__
+#define __ARCH_M68K_TERMBITS_H__
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000          /* input baud rate */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+#define IBSHIFT 16                      /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+#define EXTPROC 0200000
+
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* __ARCH_M68K_TERMBITS_H__ */
diff --git a/arch/m68k/include/asm/termios.h b/arch/m68k/include/asm/termios.h
new file mode 100644
index 00000000000..0823032e404
--- /dev/null
+++ b/arch/m68k/include/asm/termios.h
@@ -0,0 +1,92 @@
+#ifndef _M68K_TERMIOS_H
+#define _M68K_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+#ifdef __KERNEL__
+/*      intr=^C         quit=^|         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+#ifdef __KERNEL__
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        unsigned short tmp; \
+        get_user(tmp, &(termio)->c_iflag); \
+        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
+        get_user(tmp, &(termio)->c_oflag); \
+        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
+        get_user(tmp, &(termio)->c_cflag); \
+        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
+        get_user(tmp, &(termio)->c_lflag); \
+        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
+        get_user((termios)->c_line, &(termio)->c_line); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif /* _M68K_TERMIOS_H */
diff --git a/arch/m68k/include/asm/topology.h b/arch/m68k/include/asm/topology.h
new file mode 100644
index 00000000000..ca173e9f26f
--- /dev/null
+++ b/arch/m68k/include/asm/topology.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_M68K_TOPOLOGY_H
+#define _ASM_M68K_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_M68K_TOPOLOGY_H */
diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h
new file mode 100644
index 00000000000..b17fd115a4e
--- /dev/null
+++ b/arch/m68k/include/asm/types.h
@@ -0,0 +1,28 @@
+#ifndef _M68K_TYPES_H
+#define _M68K_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#endif /* __KERNEL__ */
+
+#endif /* _M68K_TYPES_H */
diff --git a/arch/m68k/include/asm/xor.h b/arch/m68k/include/asm/xor.h
new file mode 100644
index 00000000000..c82eb12a5b1
--- /dev/null
+++ b/arch/m68k/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/m68k/kernel/Makefile_mm b/arch/m68k/kernel/Makefile_mm
new file mode 100644
index 00000000000..aced6780457
--- /dev/null
+++ b/arch/m68k/kernel/Makefile_mm
@@ -0,0 +1,17 @@
+#
+# Makefile for the linux kernel.
+#
+
+ifndef CONFIG_SUN3
+  extra-y := head.o
+else
+  extra-y := sun3-head.o
+endif
+extra-y += vmlinux.lds
+
+obj-y   := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \
+           sys_m68k.o time.o setup.o m68k_ksyms.o devres.o syscalltable.o
+
+devres-y = ../../../kernel/irq/devres.o
+
+obj-y$(CONFIG_MMU_SUN3) += dma.o        # no, it's not a typo
diff --git a/arch/m68k/kernel/Makefile_no b/arch/m68k/kernel/Makefile_no
new file mode 100644
index 00000000000..37c3fc074c0
--- /dev/null
+++ b/arch/m68k/kernel/Makefile_no
@@ -0,0 +1,10 @@
+#
+# Makefile for arch/m68knommu/kernel.
+#
+
+extra-y := vmlinux.lds
+
+obj-y += dma.o entry.o init_task.o irq.o m68k_ksyms.o process.o ptrace.o \
+         setup.o signal.o syscalltable.o sys_m68k.o time.o traps.o
+
+obj-$(CONFIG_MODULES)   += module.o
diff --git a/arch/m68k/kernel/dma_mm.c b/arch/m68k/kernel/dma_mm.c
new file mode 100644
index 00000000000..4bbb3c2a888
--- /dev/null
+++ b/arch/m68k/kernel/dma_mm.c
@@ -0,0 +1,130 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#undef DEBUG
+
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#include <asm/pgalloc.h>
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *handle, gfp_t flag)
+{
+        struct page *page, **map;
+        pgprot_t pgprot;
+        void *addr;
+        int i, order;
+
+        pr_debug("dma_alloc_coherent: %d,%x\n", size, flag);
+
+        size = PAGE_ALIGN(size);
+        order = get_order(size);
+
+        page = alloc_pages(flag, order);
+        if (!page)
+                return NULL;
+
+        *handle = page_to_phys(page);
+        map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA);
+        if (!map) {
+                __free_pages(page, order);
+                return NULL;
+        }
+        split_page(page, order);
+
+        order = 1 << order;
+        size >>= PAGE_SHIFT;
+        map[0] = page;
+        for (i = 1; i < size; i++)
+                map[i] = page + i;
+        for (; i < order; i++)
+                __free_page(page + i);
+        pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+        if (CPU_IS_040_OR_060)
+                pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S;
+        else
+                pgprot_val(pgprot) |= _PAGE_NOCACHE030;
+        addr = vmap(map, size, VM_MAP, pgprot);
+        kfree(map);
+
+        return addr;
+}
+EXPORT_SYMBOL(dma_alloc_coherent);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                       void *addr, dma_addr_t handle)
+{
+        pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
+        vfree(addr);
+}
+EXPORT_SYMBOL(dma_free_coherent);
+
+void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+                                size_t size, enum dma_data_direction dir)
+{
+        switch (dir) {
+        case DMA_TO_DEVICE:
+                cache_push(handle, size);
+                break;
+        case DMA_FROM_DEVICE:
+                cache_clear(handle, size);
+                break;
+        default:
+                if (printk_ratelimit())
+                        printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
+                break;
+        }
+}
+EXPORT_SYMBOL(dma_sync_single_for_device);
+
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
+                            enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; sg++, i++)
+                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_device);
+
+dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
+                          enum dma_data_direction dir)
+{
+        dma_addr_t handle = virt_to_bus(addr);
+
+        dma_sync_single_for_device(dev, handle, size, dir);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_single);
+
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                        unsigned long offset, size_t size,
+                        enum dma_data_direction dir)
+{
+        dma_addr_t handle = page_to_phys(page) + offset;
+
+        dma_sync_single_for_device(dev, handle, size, dir);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_page);
+
+int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+               enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; sg++, i++) {
+                sg->dma_address = sg_phys(sg);
+                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
+        }
+        return nents;
+}
+EXPORT_SYMBOL(dma_map_sg);
diff --git a/arch/m68k/kernel/dma_no.c b/arch/m68k/kernel/dma_no.c
new file mode 100644
index 00000000000..fc61541aeb7
--- /dev/null
+++ b/arch/m68k/kernel/dma_no.c
@@ -0,0 +1,74 @@
+/*
+ * Dynamic DMA mapping support.
+ *
+ * We never have any address translations to worry about, so this
+ * is just alloc/free.
+ */
+
+#include <linux/types.h>
+#include <linux/gfp.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+
+        if (dev == NULL || (*dev->dma_mask < 0xffffffff))
+                gfp |= GFP_DMA;
+        ret = (void *)__get_free_pages(gfp, get_order(size));
+
+        if (ret != NULL) {
+                memset(ret, 0, size);
+                *dma_handle = virt_to_phys(ret);
+        }
+        return ret;
+}
+
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle)
+{
+        free_pages((unsigned long)vaddr, get_order(size));
+}
+
+void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+                                size_t size, enum dma_data_direction dir)
+{
+        switch (dir) {
+        case DMA_TO_DEVICE:
+                flush_dcache_range(handle, size);
+                break;
+        case DMA_FROM_DEVICE:
+                /* Should be clear already */
+                break;
+        default:
+                if (printk_ratelimit())
+                        printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
+                break;
+        }
+}
+
+EXPORT_SYMBOL(dma_sync_single_for_device);
+dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
+                          enum dma_data_direction dir)
+{
+        dma_addr_t handle = virt_to_phys(addr);
+        flush_dcache_range(handle, size);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_single);
+
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                        unsigned long offset, size_t size,
+                        enum dma_data_direction dir)
+{
+        dma_addr_t handle = page_to_phys(page) + offset;
+        dma_sync_single_for_device(dev, handle, size, dir);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_page);
diff --git a/arch/m68k/kernel/entry_mm.S b/arch/m68k/kernel/entry_mm.S
new file mode 100644
index 00000000000..bd0ec05263b
--- /dev/null
+++ b/arch/m68k/kernel/entry_mm.S
@@ -0,0 +1,409 @@
+/* -*- mode: asm -*-
+ *
+ *  linux/arch/m68k/kernel/entry.S
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file README.legal in the main directory of this archive
+ * for more details.
+ *
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ *
+ */
+
+/*
+ * entry.S  contains the system-call and fault low-level handling routines.
+ * This also contains the timer-interrupt handler, as well as all interrupts
+ * and faults that can result in a task-switch.
+ *
+ * NOTE: This code handles signal-recognition, which happens every time
+ * after a timer-interrupt and after each system call.
+ *
+ */
+
+/*
+ * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so
+ *               all pointers that used to be 'current' are now entry
+ *               number 0 in the 'current_set' list.
+ *
+ *  6/05/00 RZ:  addedd writeback completion after return from sighandler
+ *               for 68040
+ */
+
+#include <linux/linkage.h>
+#include <asm/entry.h>
+#include <asm/errno.h>
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/traps.h>
+#include <asm/unistd.h>
+
+#include <asm/asm-offsets.h>
+
+.globl system_call, buserr, trap, resume
+.globl sys_call_table
+.globl sys_fork, sys_clone, sys_vfork
+.globl ret_from_interrupt, bad_interrupt
+.globl auto_irqhandler_fixup
+.globl user_irqvec_fixup, user_irqhandler_fixup
+
+.text
+ENTRY(buserr)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %sp,%sp@-               | stack frame pointer argument
+        bsrl    buserr_c
+        addql   #4,%sp
+        jra     .Lret_from_exception
+
+ENTRY(trap)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %sp,%sp@-               | stack frame pointer argument
+        bsrl    trap_c
+        addql   #4,%sp
+        jra     .Lret_from_exception
+
+        | After a fork we jump here directly from resume,
+        | so that %d1 contains the previous task
+        | schedule_tail now used regardless of CONFIG_SMP
+ENTRY(ret_from_fork)
+        movel   %d1,%sp@-
+        jsr     schedule_tail
+        addql   #4,%sp
+        jra     .Lret_from_exception
+
+do_trace_entry:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
+        subql   #4,%sp
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        movel   %sp@(PT_OFF_ORIG_D0),%d0
+        cmpl    #NR_syscalls,%d0
+        jcs     syscall
+badsys:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
+        jra     ret_from_syscall
+
+do_trace_exit:
+        subql   #4,%sp
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jra     .Lret_from_exception
+
+ENTRY(ret_from_signal)
+        tstb    %curptr@(TASK_INFO+TINFO_FLAGS+2)
+        jge     1f
+        jbsr    syscall_trace
+1:      RESTORE_SWITCH_STACK
+        addql   #4,%sp
+/* on 68040 complete pending writebacks if any */
+#ifdef CONFIG_M68040
+        bfextu  %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
+        subql   #7,%d0                          | bus error frame ?
+        jbne    1f
+        movel   %sp,%sp@-
+        jbsr    berr_040cleanup
+        addql   #4,%sp
+1:
+#endif
+        jra     .Lret_from_exception
+
+ENTRY(system_call)
+        SAVE_ALL_SYS
+
+        GET_CURRENT(%d1)
+        | save top of frame
+        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
+
+        | syscall trace?
+        tstb    %curptr@(TASK_INFO+TINFO_FLAGS+2)
+        jmi     do_trace_entry
+        cmpl    #NR_syscalls,%d0
+        jcc     badsys
+syscall:
+        jbsr    @(sys_call_table,%d0:l:4)@(0)
+        movel   %d0,%sp@(PT_OFF_D0)     | save the return value
+ret_from_syscall:
+        |oriw   #0x0700,%sr
+        movew   %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0
+        jne     syscall_exit_work
+1:      RESTORE_ALL
+
+syscall_exit_work:
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
+        bnes    1b                      | if so, skip resched, signals
+        lslw    #1,%d0
+        jcs     do_trace_exit
+        jmi     do_delayed_trace
+        lslw    #8,%d0
+        jmi     do_signal_return
+        pea     resume_userspace
+        jra     schedule
+
+
+ENTRY(ret_from_exception)
+.Lret_from_exception:
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
+        bnes    1f                      | if so, skip resched, signals
+        | only allow interrupts when we are really the last one on the
+        | kernel stack, otherwise stack overflow can occur during
+        | heavy interrupt load
+        andw    #ALLOWINT,%sr
+
+resume_userspace:
+        moveb   %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0
+        jne     exit_work
+1:      RESTORE_ALL
+
+exit_work:
+        | save top of frame
+        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
+        lslb    #1,%d0
+        jmi     do_signal_return
+        pea     resume_userspace
+        jra     schedule
+
+
+do_signal_return:
+        |andw   #ALLOWINT,%sr
+        subql   #4,%sp                  | dummy return address
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        bsrl    do_signal
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jbra    resume_userspace
+
+do_delayed_trace:
+        bclr    #7,%sp@(PT_OFF_SR)      | clear trace bit in SR
+        pea     1                       | send SIGTRAP
+        movel   %curptr,%sp@-
+        pea     LSIGTRAP
+        jbsr    send_sig
+        addql   #8,%sp
+        addql   #4,%sp
+        jbra    resume_userspace
+
+
+/* This is the main interrupt handler for autovector interrupts */
+
+ENTRY(auto_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        addqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+                                        |  put exception # in d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
+        subw    #VEC_SPUR,%d0
+
+        movel   %sp,%sp@-
+        movel   %d0,%sp@-               |  put vector # on stack
+auto_irqhandler_fixup = . + 2
+        jsr     __m68k_handle_int       |  process the IRQ
+        addql   #8,%sp                  |  pop parameters off stack
+
+ret_from_interrupt:
+        subqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+2:      RESTORE_ALL
+
+        ALIGN
+ret_from_last_interrupt:
+        moveq   #(~ALLOWINT>>8)&0xff,%d0
+        andb    %sp@(PT_OFF_SR),%d0
+        jne     2b
+
+        /* check if we need to do software interrupts */
+        tstl    irq_stat+CPUSTAT_SOFTIRQ_PENDING
+        jeq     .Lret_from_exception
+        pea     ret_from_exception
+        jra     do_softirq
+
+/* Handler for user defined interrupt vectors */
+
+ENTRY(user_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        addqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+                                        |  put exception # in d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
+user_irqvec_fixup = . + 2
+        subw    #VEC_USER,%d0
+
+        movel   %sp,%sp@-
+        movel   %d0,%sp@-               |  put vector # on stack
+user_irqhandler_fixup = . + 2
+        jsr     __m68k_handle_int       |  process the IRQ
+        addql   #8,%sp                  |  pop parameters off stack
+
+        subqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+        RESTORE_ALL
+
+/* Handler for uninitialized and spurious interrupts */
+
+ENTRY(bad_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        addqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+
+        movel   %sp,%sp@-
+        jsr     handle_badint
+        addql   #4,%sp
+
+        subqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+        RESTORE_ALL
+
+
+ENTRY(sys_fork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_fork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_clone)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_clone
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_vfork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_vfork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_rt_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_rt_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+resume:
+        /*
+         * Beware - when entering resume, prev (the current task) is
+         * in a0, next (the new task) is in a1,so don't change these
+         * registers until their contents are no longer needed.
+         */
+
+        /* save sr */
+        movew   %sr,%a0@(TASK_THREAD+THREAD_SR)
+
+        /* save fs (sfc,%dfc) (may be pointing to kernel memory) */
+        movec   %sfc,%d0
+        movew   %d0,%a0@(TASK_THREAD+THREAD_FS)
+
+        /* save usp */
+        /* it is better to use a movel here instead of a movew 8*) */
+        movec   %usp,%d0
+        movel   %d0,%a0@(TASK_THREAD+THREAD_USP)
+
+        /* save non-scratch registers on stack */
+        SAVE_SWITCH_STACK
+
+        /* save current kernel stack pointer */
+        movel   %sp,%a0@(TASK_THREAD+THREAD_KSP)
+
+        /* save floating point context */
+#ifndef CONFIG_M68KFPU_EMU_ONLY
+#ifdef CONFIG_M68KFPU_EMU
+        tstl    m68k_fputype
+        jeq     3f
+#endif
+        fsave   %a0@(TASK_THREAD+THREAD_FPSTATE)
+
+#if defined(CONFIG_M68060)
+#if !defined(CPU_M68060_ONLY)
+        btst    #3,m68k_cputype+3
+        beqs    1f
+#endif
+        /* The 060 FPU keeps status in bits 15-8 of the first longword */
+        tstb    %a0@(TASK_THREAD+THREAD_FPSTATE+2)
+        jeq     3f
+#if !defined(CPU_M68060_ONLY)
+        jra     2f
+#endif
+#endif /* CONFIG_M68060 */
+#if !defined(CPU_M68060_ONLY)
+1:      tstb    %a0@(TASK_THREAD+THREAD_FPSTATE)
+        jeq     3f
+#endif
+2:      fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
+        fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL)
+3:
+#endif  /* CONFIG_M68KFPU_EMU_ONLY */
+        /* Return previous task in %d1 */
+        movel   %curptr,%d1
+
+        /* switch to new task (a1 contains new task) */
+        movel   %a1,%curptr
+
+        /* restore floating point context */
+#ifndef CONFIG_M68KFPU_EMU_ONLY
+#ifdef CONFIG_M68KFPU_EMU
+        tstl    m68k_fputype
+        jeq     4f
+#endif
+#if defined(CONFIG_M68060)
+#if !defined(CPU_M68060_ONLY)
+        btst    #3,m68k_cputype+3
+        beqs    1f
+#endif
+        /* The 060 FPU keeps status in bits 15-8 of the first longword */
+        tstb    %a1@(TASK_THREAD+THREAD_FPSTATE+2)
+        jeq     3f
+#if !defined(CPU_M68060_ONLY)
+        jra     2f
+#endif
+#endif /* CONFIG_M68060 */
+#if !defined(CPU_M68060_ONLY)
+1:      tstb    %a1@(TASK_THREAD+THREAD_FPSTATE)
+        jeq     3f
+#endif
+2:      fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
+        fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
+3:      frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
+4:
+#endif  /* CONFIG_M68KFPU_EMU_ONLY */
+
+        /* restore the kernel stack pointer */
+        movel   %a1@(TASK_THREAD+THREAD_KSP),%sp
+
+        /* restore non-scratch registers */
+        RESTORE_SWITCH_STACK
+
+        /* restore user stack pointer */
+        movel   %a1@(TASK_THREAD+THREAD_USP),%a0
+        movel   %a0,%usp
+
+        /* restore fs (sfc,%dfc) */
+        movew   %a1@(TASK_THREAD+THREAD_FS),%a0
+        movec   %a0,%sfc
+        movec   %a0,%dfc
+
+        /* restore status register */
+        movew   %a1@(TASK_THREAD+THREAD_SR),%sr
+
+        rts
+
diff --git a/arch/m68k/kernel/entry_no.S b/arch/m68k/kernel/entry_no.S
new file mode 100644
index 00000000000..5f0f6b598b5
--- /dev/null
+++ b/arch/m68k/kernel/entry_no.S
@@ -0,0 +1,133 @@
+/*
+ *  linux/arch/m68knommu/kernel/entry.S
+ *
+ *  Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *  Copyright (C) 1998  D. Jeff Dionne <jeff@lineo.ca>,
+ *                      Kenneth Albanowski <kjahds@kjahds.com>,
+ *  Copyright (C) 2000  Lineo Inc. (www.lineo.com) 
+ *
+ * Based on:
+ *
+ *  linux/arch/m68k/kernel/entry.S
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file README.legal in the main directory of this archive
+ * for more details.
+ *
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ * ColdFire support by Greg Ungerer (gerg@snapgear.com)
+ * 5307 fixes by David W. Miller
+ * linux 2.4 support David McCullough <davidm@snapgear.com>
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/asm-offsets.h>
+#include <asm/entry.h>
+#include <asm/unistd.h>
+
+.text
+
+.globl buserr
+.globl trap
+.globl ret_from_exception
+.globl ret_from_signal
+.globl sys_fork
+.globl sys_clone
+.globl sys_vfork
+
+ENTRY(buserr)
+        SAVE_ALL
+        moveq   #-1,%d0
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
+        movel   %sp,%sp@-               /* stack frame pointer argument */
+        jsr     buserr_c
+        addql   #4,%sp
+        jra     ret_from_exception
+
+ENTRY(trap)
+        SAVE_ALL
+        moveq   #-1,%d0
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
+        movel   %sp,%sp@-               /* stack frame pointer argument */
+        jsr     trap_c
+        addql   #4,%sp
+        jra     ret_from_exception
+
+#ifdef TRAP_DBG_INTERRUPT
+
+.globl dbginterrupt
+ENTRY(dbginterrupt)
+        SAVE_ALL
+        moveq   #-1,%d0
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
+        movel   %sp,%sp@-               /* stack frame pointer argument */
+        jsr     dbginterrupt_c
+        addql   #4,%sp
+        jra     ret_from_exception
+#endif
+
+ENTRY(reschedule)
+        /* save top of frame */
+        pea     %sp@
+        jbsr    set_esp0
+        addql   #4,%sp
+        pea     ret_from_exception
+        jmp     schedule
+
+ENTRY(ret_from_fork)
+        movel   %d1,%sp@-
+        jsr     schedule_tail
+        addql   #4,%sp
+        jra     ret_from_exception
+
+ENTRY(sys_fork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_fork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_vfork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_vfork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_clone)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_clone
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_rt_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_rt_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(ret_from_user_signal)
+        moveq #__NR_sigreturn,%d0
+        trap #0
+
+ENTRY(ret_from_user_rt_signal)
+        movel #__NR_rt_sigreturn,%d0
+        trap #0
+
diff --git a/arch/m68k/kernel/init_task.c b/arch/m68k/kernel/init_task.c
new file mode 100644
index 00000000000..cbf9dc3cc51
--- /dev/null
+++ b/arch/m68k/kernel/init_task.c
@@ -0,0 +1,36 @@
+/*
+ *  linux/arch/m68knommu/kernel/init_task.c
+ */
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/init_task.h>
+#include <linux/fs.h>
+#include <linux/mqueue.h>
+
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+/*
+ * Initial task structure.
+ *
+ * All other task structs will be allocated on slabs in fork.c
+ */
+__asm__(".align 4");
+struct task_struct init_task = INIT_TASK(init_task);
+
+EXPORT_SYMBOL(init_task);
+
+/*
+ * Initial thread structure.
+ *
+ * We need to make sure that this is 8192-byte aligned due to the
+ * way process stacks are handled. This is done by having a special
+ * "init_task" linker map entry..
+ */
+union thread_union init_thread_union __init_task_data =
+        { INIT_THREAD_INFO(init_task) };
+
diff --git a/arch/m68k/kernel/process_mm.c b/arch/m68k/kernel/process_mm.c
new file mode 100644
index 00000000000..1bc223aa07e
--- /dev/null
+++ b/arch/m68k/kernel/process_mm.c
@@ -0,0 +1,354 @@
+/*
+ *  linux/arch/m68k/kernel/process.c
+ *
+ *  Copyright (C) 1995  Hamish Macdonald
+ *
+ *  68060 fixes by Jesper Skov
+ */
+
+/*
+ * This file handles the architecture-dependent parts of process handling..
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/smp.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/reboot.h>
+#include <linux/init_task.h>
+#include <linux/mqueue.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/pgtable.h>
+
+/*
+ * Initial task/thread structure. Make this a per-architecture thing,
+ * because different architectures tend to have different
+ * alignment requirements and potentially different initial
+ * setup.
+ */
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+union thread_union init_thread_union __init_task_data
+        __attribute__((aligned(THREAD_SIZE))) =
+                { INIT_THREAD_INFO(init_task) };
+
+/* initial task structure */
+struct task_struct init_task = INIT_TASK(init_task);
+
+EXPORT_SYMBOL(init_task);
+
+asmlinkage void ret_from_fork(void);
+
+
+/*
+ * Return saved PC from a blocked thread
+ */
+unsigned long thread_saved_pc(struct task_struct *tsk)
+{
+        struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
+        /* Check whether the thread is blocked in resume() */
+        if (in_sched_functions(sw->retpc))
+                return ((unsigned long *)sw->a6)[1];
+        else
+                return sw->retpc;
+}
+
+/*
+ * The idle loop on an m68k..
+ */
+static void default_idle(void)
+{
+        if (!need_resched())
+#if defined(MACH_ATARI_ONLY)
+                /* block out HSYNC on the atari (falcon) */
+                __asm__("stop #0x2200" : : : "cc");
+#else
+                __asm__("stop #0x2000" : : : "cc");
+#endif
+}
+
+void (*idle)(void) = default_idle;
+
+/*
+ * The idle thread. There's no useful work to be
+ * done, so just try to conserve power and have a
+ * low exit latency (ie sit in a loop waiting for
+ * somebody to say that they'd like to reschedule)
+ */
+void cpu_idle(void)
+{
+        /* endless idle loop with no priority at all */
+        while (1) {
+                while (!need_resched())
+                        idle();
+                preempt_enable_no_resched();
+                schedule();
+                preempt_disable();
+        }
+}
+
+void machine_restart(char * __unused)
+{
+        if (mach_reset)
+                mach_reset();
+        for (;;);
+}
+
+void machine_halt(void)
+{
+        if (mach_halt)
+                mach_halt();
+        for (;;);
+}
+
+void machine_power_off(void)
+{
+        if (mach_power_off)
+                mach_power_off();
+        for (;;);
+}
+
+void (*pm_power_off)(void) = machine_power_off;
+EXPORT_SYMBOL(pm_power_off);
+
+void show_regs(struct pt_regs * regs)
+{
+        printk("\n");
+        printk("Format %02x  Vector: %04x  PC: %08lx  Status: %04x    %s\n",
+               regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
+        printk("ORIG_D0: %08lx  D0: %08lx  A2: %08lx  A1: %08lx\n",
+               regs->orig_d0, regs->d0, regs->a2, regs->a1);
+        printk("A0: %08lx  D5: %08lx  D4: %08lx\n",
+               regs->a0, regs->d5, regs->d4);
+        printk("D3: %08lx  D2: %08lx  D1: %08lx\n",
+               regs->d3, regs->d2, regs->d1);
+        if (!(regs->sr & PS_S))
+                printk("USP: %08lx\n", rdusp());
+}
+
+/*
+ * Create a kernel thread
+ */
+int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+        int pid;
+        mm_segment_t fs;
+
+        fs = get_fs();
+        set_fs (KERNEL_DS);
+
+        {
+        register long retval __asm__ ("d0");
+        register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED;
+
+        retval = __NR_clone;
+        __asm__ __volatile__
+          ("clrl %%d2\n\t"
+           "trap #0\n\t"                /* Linux/m68k system call */
+           "tstl %0\n\t"                /* child or parent */
+           "jne 1f\n\t"                 /* parent - jump */
+           "lea %%sp@(%c7),%6\n\t"      /* reload current */
+           "movel %6@,%6\n\t"
+           "movel %3,%%sp@-\n\t"        /* push argument */
+           "jsr %4@\n\t"                /* call fn */
+           "movel %0,%%d1\n\t"          /* pass exit value */
+           "movel %2,%%d0\n\t"          /* exit */
+           "trap #0\n"
+           "1:"
+           : "+d" (retval)
+           : "i" (__NR_clone), "i" (__NR_exit),
+             "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
+             "i" (-THREAD_SIZE)
+           : "d2");
+
+        pid = retval;
+        }
+
+        set_fs (fs);
+        return pid;
+}
+EXPORT_SYMBOL(kernel_thread);
+
+void flush_thread(void)
+{
+        unsigned long zero = 0;
+
+        current->thread.fs = __USER_DS;
+        if (!FPU_IS_EMU)
+                asm volatile (".chip 68k/68881\n\t"
+                              "frestore %0@\n\t"
+                              ".chip 68k" : : "a" (&zero));
+}
+
+/*
+ * "m68k_fork()".. By the time we get here, the
+ * non-volatile registers have also been saved on the
+ * stack. We do some ugly pointer stuff here.. (see
+ * also copy_thread)
+ */
+
+asmlinkage int m68k_fork(struct pt_regs *regs)
+{
+        return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
+}
+
+asmlinkage int m68k_vfork(struct pt_regs *regs)
+{
+        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0,
+                       NULL, NULL);
+}
+
+asmlinkage int m68k_clone(struct pt_regs *regs)
+{
+        unsigned long clone_flags;
+        unsigned long newsp;
+        int __user *parent_tidptr, *child_tidptr;
+
+        /* syscall2 puts clone_flags in d1 and usp in d2 */
+        clone_flags = regs->d1;
+        newsp = regs->d2;
+        parent_tidptr = (int __user *)regs->d3;
+        child_tidptr = (int __user *)regs->d4;
+        if (!newsp)
+                newsp = rdusp();
+        return do_fork(clone_flags, newsp, regs, 0,
+                       parent_tidptr, child_tidptr);
+}
+
+int copy_thread(unsigned long clone_flags, unsigned long usp,
+                 unsigned long unused,
+                 struct task_struct * p, struct pt_regs * regs)
+{
+        struct pt_regs * childregs;
+        struct switch_stack * childstack, *stack;
+        unsigned long *retp;
+
+        childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
+
+        *childregs = *regs;
+        childregs->d0 = 0;
+
+        retp = ((unsigned long *) regs);
+        stack = ((struct switch_stack *) retp) - 1;
+
+        childstack = ((struct switch_stack *) childregs) - 1;
+        *childstack = *stack;
+        childstack->retpc = (unsigned long)ret_from_fork;
+
+        p->thread.usp = usp;
+        p->thread.ksp = (unsigned long)childstack;
+
+        if (clone_flags & CLONE_SETTLS)
+                task_thread_info(p)->tp_value = regs->d5;
+
+        /*
+         * Must save the current SFC/DFC value, NOT the value when
+         * the parent was last descheduled - RGH  10-08-96
+         */
+        p->thread.fs = get_fs().seg;
+
+        if (!FPU_IS_EMU) {
+                /* Copy the current fpu state */
+                asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
+
+                if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2])
+                  asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
+                                "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
+                                : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0])
+                                : "memory");
+                /* Restore the state in case the fpu was busy */
+                asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
+        }
+
+        return 0;
+}
+
+/* Fill in the fpu structure for a core dump.  */
+
+int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
+{
+        char fpustate[216];
+
+        if (FPU_IS_EMU) {
+                int i;
+
+                memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
+                memcpy(fpu->fpregs, current->thread.fp, 96);
+                /* Convert internal fpu reg representation
+                 * into long double format
+                 */
+                for (i = 0; i < 24; i += 3)
+                        fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
+                                         ((fpu->fpregs[i] & 0x0000ffff) << 16);
+                return 1;
+        }
+
+        /* First dump the fpu context to avoid protocol violation.  */
+        asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
+        if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
+                return 0;
+
+        asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
+                :: "m" (fpu->fpcntl[0])
+                : "memory");
+        asm volatile ("fmovemx %/fp0-%/fp7,%0"
+                :: "m" (fpu->fpregs[0])
+                : "memory");
+        return 1;
+}
+EXPORT_SYMBOL(dump_fpu);
+
+/*
+ * sys_execve() executes a new program.
+ */
+asmlinkage int sys_execve(const char __user *name,
+                          const char __user *const __user *argv,
+                          const char __user *const __user *envp)
+{
+        int error;
+        char * filename;
+        struct pt_regs *regs = (struct pt_regs *) &name;
+
+        filename = getname(name);
+        error = PTR_ERR(filename);
+        if (IS_ERR(filename))
+                return error;
+        error = do_execve(filename, argv, envp, regs);
+        putname(filename);
+        return error;
+}
+
+unsigned long get_wchan(struct task_struct *p)
+{
+        unsigned long fp, pc;
+        unsigned long stack_page;
+        int count = 0;
+        if (!p || p == current || p->state == TASK_RUNNING)
+                return 0;
+
+        stack_page = (unsigned long)task_stack_page(p);
+        fp = ((struct switch_stack *)p->thread.ksp)->a6;
+        do {
+                if (fp < stack_page+sizeof(struct thread_info) ||
+                    fp >= 8184+stack_page)
+                        return 0;
+                pc = ((unsigned long *)fp)[1];
+                if (!in_sched_functions(pc))
+                        return pc;
+                fp = *(unsigned long *) fp;
+        } while (count++ < 16);
+        return 0;
+}
diff --git a/arch/m68k/kernel/process_no.c b/arch/m68k/kernel/process_no.c
new file mode 100644
index 00000000000..69c1803fcf1
--- /dev/null
+++ b/arch/m68k/kernel/process_no.c
@@ -0,0 +1,406 @@
+/*
+ *  linux/arch/m68knommu/kernel/process.c
+ *
+ *  Copyright (C) 1995  Hamish Macdonald
+ *
+ *  68060 fixes by Jesper Skov
+ *
+ *  uClinux changes
+ *  Copyright (C) 2000-2002, David McCullough <davidm@snapgear.com>
+ */
+
+/*
+ * This file handles the architecture-dependent parts of process handling..
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/pgtable.h>
+
+asmlinkage void ret_from_fork(void);
+
+/*
+ * The following aren't currently used.
+ */
+void (*pm_idle)(void);
+EXPORT_SYMBOL(pm_idle);
+
+void (*pm_power_off)(void);
+EXPORT_SYMBOL(pm_power_off);
+
+/*
+ * The idle loop on an m68knommu..
+ */
+static void default_idle(void)
+{
+        local_irq_disable();
+        while (!need_resched()) {
+                /* This stop will re-enable interrupts */
+                __asm__("stop #0x2000" : : : "cc");
+                local_irq_disable();
+        }
+        local_irq_enable();
+}
+
+void (*idle)(void) = default_idle;
+
+/*
+ * The idle thread. There's no useful work to be
+ * done, so just try to conserve power and have a
+ * low exit latency (ie sit in a loop waiting for
+ * somebody to say that they'd like to reschedule)
+ */
+void cpu_idle(void)
+{
+        /* endless idle loop with no priority at all */
+        while (1) {
+                idle();
+                preempt_enable_no_resched();
+                schedule();
+                preempt_disable();
+        }
+}
+
+void machine_restart(char * __unused)
+{
+        if (mach_reset)
+                mach_reset();
+        for (;;);
+}
+
+void machine_halt(void)
+{
+        if (mach_halt)
+                mach_halt();
+        for (;;);
+}
+
+void machine_power_off(void)
+{
+        if (mach_power_off)
+                mach_power_off();
+        for (;;);
+}
+
+void show_regs(struct pt_regs * regs)
+{
+        printk(KERN_NOTICE "\n");
+        printk(KERN_NOTICE "Format %02x  Vector: %04x  PC: %08lx  Status: %04x    %s\n",
+               regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
+        printk(KERN_NOTICE "ORIG_D0: %08lx  D0: %08lx  A2: %08lx  A1: %08lx\n",
+               regs->orig_d0, regs->d0, regs->a2, regs->a1);
+        printk(KERN_NOTICE "A0: %08lx  D5: %08lx  D4: %08lx\n",
+               regs->a0, regs->d5, regs->d4);
+        printk(KERN_NOTICE "D3: %08lx  D2: %08lx  D1: %08lx\n",
+               regs->d3, regs->d2, regs->d1);
+        if (!(regs->sr & PS_S))
+                printk(KERN_NOTICE "USP: %08lx\n", rdusp());
+}
+
+/*
+ * Create a kernel thread
+ */
+int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+        int retval;
+        long clone_arg = flags | CLONE_VM;
+        mm_segment_t fs;
+
+        fs = get_fs();
+        set_fs(KERNEL_DS);
+
+        __asm__ __volatile__ (
+                        "movel  %%sp, %%d2\n\t"
+                        "movel  %5, %%d1\n\t"
+                        "movel  %1, %%d0\n\t"
+                        "trap   #0\n\t"
+                        "cmpl   %%sp, %%d2\n\t"
+                        "jeq    1f\n\t"
+                        "movel  %3, %%sp@-\n\t"
+                        "jsr    %4@\n\t"
+                        "movel  %2, %%d0\n\t"
+                        "trap   #0\n"
+                        "1:\n\t"
+                        "movel  %%d0, %0\n"
+                : "=d" (retval)
+                : "i" (__NR_clone),
+                  "i" (__NR_exit),
+                  "a" (arg),
+                  "a" (fn),
+                  "a" (clone_arg)
+                : "cc", "%d0", "%d1", "%d2");
+
+        set_fs(fs);
+        return retval;
+}
+EXPORT_SYMBOL(kernel_thread);
+
+void flush_thread(void)
+{
+#ifdef CONFIG_FPU
+        unsigned long zero = 0;
+#endif
+
+        current->thread.fs = __USER_DS;
+#ifdef CONFIG_FPU
+        if (!FPU_IS_EMU)
+                asm volatile (".chip 68k/68881\n\t"
+                              "frestore %0@\n\t"
+                              ".chip 68k" : : "a" (&zero));
+#endif
+}
+
+/*
+ * "m68k_fork()".. By the time we get here, the
+ * non-volatile registers have also been saved on the
+ * stack. We do some ugly pointer stuff here.. (see
+ * also copy_thread)
+ */
+
+asmlinkage int m68k_fork(struct pt_regs *regs)
+{
+        /* fork almost works, enough to trick you into looking elsewhere :-( */
+        return(-EINVAL);
+}
+
+asmlinkage int m68k_vfork(struct pt_regs *regs)
+{
+        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL, NULL);
+}
+
+asmlinkage int m68k_clone(struct pt_regs *regs)
+{
+        unsigned long clone_flags;
+        unsigned long newsp;
+
+        /* syscall2 puts clone_flags in d1 and usp in d2 */
+        clone_flags = regs->d1;
+        newsp = regs->d2;
+        if (!newsp)
+                newsp = rdusp();
+        return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
+}
+
+int copy_thread(unsigned long clone_flags,
+                unsigned long usp, unsigned long topstk,
+                struct task_struct * p, struct pt_regs * regs)
+{
+        struct pt_regs * childregs;
+        struct switch_stack * childstack, *stack;
+        unsigned long *retp;
+
+        childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
+
+        *childregs = *regs;
+        childregs->d0 = 0;
+
+        retp = ((unsigned long *) regs);
+        stack = ((struct switch_stack *) retp) - 1;
+
+        childstack = ((struct switch_stack *) childregs) - 1;
+        *childstack = *stack;
+        childstack->retpc = (unsigned long)ret_from_fork;
+
+        p->thread.usp = usp;
+        p->thread.ksp = (unsigned long)childstack;
+
+        if (clone_flags & CLONE_SETTLS)
+                task_thread_info(p)->tp_value = regs->d5;
+
+        /*
+         * Must save the current SFC/DFC value, NOT the value when
+         * the parent was last descheduled - RGH  10-08-96
+         */
+        p->thread.fs = get_fs().seg;
+
+#ifdef CONFIG_FPU
+        if (!FPU_IS_EMU) {
+                /* Copy the current fpu state */
+                asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
+
+                if (p->thread.fpstate[0])
+                  asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
+                                "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
+                                : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0])
+                                : "memory");
+                /* Restore the state in case the fpu was busy */
+                asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
+        }
+#endif
+
+        return 0;
+}
+
+/* Fill in the fpu structure for a core dump.  */
+
+int dump_fpu(struct pt_regs *regs, struct user_m68kfp_struct *fpu)
+{
+#ifdef CONFIG_FPU
+        char fpustate[216];
+
+        if (FPU_IS_EMU) {
+                int i;
+
+                memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
+                memcpy(fpu->fpregs, current->thread.fp, 96);
+                /* Convert internal fpu reg representation
+                 * into long double format
+                 */
+                for (i = 0; i < 24; i += 3)
+                        fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
+                                         ((fpu->fpregs[i] & 0x0000ffff) << 16);
+                return 1;
+        }
+
+        /* First dump the fpu context to avoid protocol violation.  */
+        asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
+        if (!fpustate[0])
+                return 0;
+
+        asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
+                :: "m" (fpu->fpcntl[0])
+                : "memory");
+        asm volatile ("fmovemx %/fp0-%/fp7,%0"
+                :: "m" (fpu->fpregs[0])
+                : "memory");
+#endif
+        return 1;
+}
+EXPORT_SYMBOL(dump_fpu);
+
+/*
+ *      Generic dumping code. Used for panic and debug.
+ */
+void dump(struct pt_regs *fp)
+{
+        unsigned long   *sp;
+        unsigned char   *tp;
+        int             i;
+
+        printk(KERN_EMERG "\nCURRENT PROCESS:\n\n");
+        printk(KERN_EMERG "COMM=%s PID=%d\n", current->comm, current->pid);
+
+        if (current->mm) {
+                printk(KERN_EMERG "TEXT=%08x-%08x DATA=%08x-%08x BSS=%08x-%08x\n",
+                        (int) current->mm->start_code,
+                        (int) current->mm->end_code,
+                        (int) current->mm->start_data,
+                        (int) current->mm->end_data,
+                        (int) current->mm->end_data,
+                        (int) current->mm->brk);
+                printk(KERN_EMERG "USER-STACK=%08x KERNEL-STACK=%08x\n\n",
+                        (int) current->mm->start_stack,
+                        (int)(((unsigned long) current) + THREAD_SIZE));
+        }
+
+        printk(KERN_EMERG "PC: %08lx\n", fp->pc);
+        printk(KERN_EMERG "SR: %08lx    SP: %08lx\n", (long) fp->sr, (long) fp);
+        printk(KERN_EMERG "d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
+                fp->d0, fp->d1, fp->d2, fp->d3);
+        printk(KERN_EMERG "d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
+                fp->d4, fp->d5, fp->a0, fp->a1);
+        printk(KERN_EMERG "\nUSP: %08x   TRAPFRAME: %p\n",
+                (unsigned int) rdusp(), fp);
+
+        printk(KERN_EMERG "\nCODE:");
+        tp = ((unsigned char *) fp->pc) - 0x20;
+        for (sp = (unsigned long *) tp, i = 0; (i < 0x40);  i += 4) {
+                if ((i % 0x10) == 0)
+                        printk(KERN_EMERG "%p: ", tp + i);
+                printk("%08x ", (int) *sp++);
+        }
+        printk(KERN_EMERG "\n");
+
+        printk(KERN_EMERG "KERNEL STACK:");
+        tp = ((unsigned char *) fp) - 0x40;
+        for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) {
+                if ((i % 0x10) == 0)
+                        printk(KERN_EMERG "%p: ", tp + i);
+                printk("%08x ", (int) *sp++);
+        }
+        printk(KERN_EMERG "\n");
+
+        printk(KERN_EMERG "USER STACK:");
+        tp = (unsigned char *) (rdusp() - 0x10);
+        for (sp = (unsigned long *) tp, i = 0; (i < 0x80); i += 4) {
+                if ((i % 0x10) == 0)
+                        printk(KERN_EMERG "%p: ", tp + i);
+                printk("%08x ", (int) *sp++);
+        }
+        printk(KERN_EMERG "\n");
+}
+
+/*
+ * sys_execve() executes a new program.
+ */
+asmlinkage int sys_execve(const char *name,
+                          const char *const *argv,
+                          const char *const *envp)
+{
+        int error;
+        char * filename;
+        struct pt_regs *regs = (struct pt_regs *) &name;
+
+        filename = getname(name);
+        error = PTR_ERR(filename);
+        if (IS_ERR(filename))
+                return error;
+        error = do_execve(filename, argv, envp, regs);
+        putname(filename);
+        return error;
+}
+
+unsigned long get_wchan(struct task_struct *p)
+{
+        unsigned long fp, pc;
+        unsigned long stack_page;
+        int count = 0;
+        if (!p || p == current || p->state == TASK_RUNNING)
+                return 0;
+
+        stack_page = (unsigned long)p;
+        fp = ((struct switch_stack *)p->thread.ksp)->a6;
+        do {
+                if (fp < stack_page+sizeof(struct thread_info) ||
+                    fp >= THREAD_SIZE-8+stack_page)
+                        return 0;
+                pc = ((unsigned long *)fp)[1];
+                if (!in_sched_functions(pc))
+                        return pc;
+                fp = *(unsigned long *) fp;
+        } while (count++ < 16);
+        return 0;
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+unsigned long thread_saved_pc(struct task_struct *tsk)
+{
+        struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
+
+        /* Check whether the thread is blocked in resume() */
+        if (in_sched_functions(sw->retpc))
+                return ((unsigned long *)sw->a6)[1];
+        else
+                return sw->retpc;
+}
+
diff --git a/arch/m68k/kernel/ptrace_mm.c b/arch/m68k/kernel/ptrace_mm.c
new file mode 100644
index 00000000000..0b252683cef
--- /dev/null
+++ b/arch/m68k/kernel/ptrace_mm.c
@@ -0,0 +1,277 @@
+/*
+ *  linux/arch/m68k/kernel/ptrace.c
+ *
+ *  Copyright (C) 1994 by Hamish Macdonald
+ *  Taken from linux/kernel/ptrace.c and modified for M680x0.
+ *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of
+ * this archive for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/signal.h>
+
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+
+/*
+ * does not yet catch signals sent when the child dies.
+ * in exit.c or in signal.c.
+ */
+
+/* determines which bits in the SR the user has access to. */
+/* 1 = access 0 = no access */
+#define SR_MASK 0x001f
+
+/* sets the trace bits. */
+#define TRACE_BITS 0xC000
+#define T1_BIT 0x8000
+#define T0_BIT 0x4000
+
+/* Find the stack offset for a register, relative to thread.esp0. */
+#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
+#define SW_REG(reg)     ((long)&((struct switch_stack *)0)->reg \
+                         - sizeof(struct switch_stack))
+/* Mapping from PT_xxx to the stack offset at which the register is
+   saved.  Notice that usp has no stack-slot and needs to be treated
+   specially (see get_reg/put_reg below). */
+static const int regoff[] = {
+        [0]     = PT_REG(d1),
+        [1]     = PT_REG(d2),
+        [2]     = PT_REG(d3),
+        [3]     = PT_REG(d4),
+        [4]     = PT_REG(d5),
+        [5]     = SW_REG(d6),
+        [6]     = SW_REG(d7),
+        [7]     = PT_REG(a0),
+        [8]     = PT_REG(a1),
+        [9]     = PT_REG(a2),
+        [10]    = SW_REG(a3),
+        [11]    = SW_REG(a4),
+        [12]    = SW_REG(a5),
+        [13]    = SW_REG(a6),
+        [14]    = PT_REG(d0),
+        [15]    = -1,
+        [16]    = PT_REG(orig_d0),
+        [17]    = PT_REG(sr),
+        [18]    = PT_REG(pc),
+};
+
+/*
+ * Get contents of register REGNO in task TASK.
+ */
+static inline long get_reg(struct task_struct *task, int regno)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
+        else
+                return 0;
+        /* Need to take stkadj into account. */
+        if (regno == PT_SR || regno == PT_PC) {
+                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
+                addr = (unsigned long *) ((unsigned long)addr + stkadj);
+                /* The sr is actually a 16 bit register.  */
+                if (regno == PT_SR)
+                        return *(unsigned short *)addr;
+        }
+        return *addr;
+}
+
+/*
+ * Write contents of register REGNO in task TASK.
+ */
+static inline int put_reg(struct task_struct *task, int regno,
+                          unsigned long data)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
+        else
+                return -1;
+        /* Need to take stkadj into account. */
+        if (regno == PT_SR || regno == PT_PC) {
+                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
+                addr = (unsigned long *) ((unsigned long)addr + stkadj);
+                /* The sr is actually a 16 bit register.  */
+                if (regno == PT_SR) {
+                        *(unsigned short *)addr = data;
+                        return 0;
+                }
+        }
+        *addr = data;
+        return 0;
+}
+
+/*
+ * Make sure the single step bit is not set.
+ */
+static inline void singlestep_disable(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp);
+        clear_tsk_thread_flag(child, TIF_DELAYED_TRACE);
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ */
+void ptrace_disable(struct task_struct *child)
+{
+        singlestep_disable(child);
+}
+
+void user_enable_single_step(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp | T1_BIT);
+        set_tsk_thread_flag(child, TIF_DELAYED_TRACE);
+}
+
+void user_enable_block_step(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp | T0_BIT);
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+        singlestep_disable(child);
+}
+
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
+{
+        unsigned long tmp;
+        int i, ret = 0;
+        int regno = addr >> 2; /* temporary hack. */
+        unsigned long __user *datap = (unsigned long __user *) data;
+
+        switch (request) {
+        /* read the word at location addr in the USER area. */
+        case PTRACE_PEEKUSR:
+                if (addr & 3)
+                        goto out_eio;
+
+                if (regno >= 0 && regno < 19) {
+                        tmp = get_reg(child, regno);
+                } else if (regno >= 21 && regno < 49) {
+                        tmp = child->thread.fp[regno - 21];
+                        /* Convert internal fpu reg representation
+                         * into long double format
+                         */
+                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3))
+                                tmp = ((tmp & 0xffff0000) << 15) |
+                                      ((tmp & 0x0000ffff) << 16);
+                } else
+                        goto out_eio;
+                ret = put_user(tmp, datap);
+                break;
+
+        case PTRACE_POKEUSR:
+        /* write the word at location addr in the USER area */
+                if (addr & 3)
+                        goto out_eio;
+
+                if (regno == PT_SR) {
+                        data &= SR_MASK;
+                        data |= get_reg(child, PT_SR) & ~SR_MASK;
+                }
+                if (regno >= 0 && regno < 19) {
+                        if (put_reg(child, regno, data))
+                                goto out_eio;
+                } else if (regno >= 21 && regno < 48) {
+                        /* Convert long double format
+                         * into internal fpu reg representation
+                         */
+                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) {
+                                data <<= 15;
+                                data = (data & 0xffff0000) |
+                                       ((data & 0x0000ffff) >> 1);
+                        }
+                        child->thread.fp[regno - 21] = data;
+                } else
+                        goto out_eio;
+                break;
+
+        case PTRACE_GETREGS:    /* Get all gp regs from the child. */
+                for (i = 0; i < 19; i++) {
+                        tmp = get_reg(child, i);
+                        ret = put_user(tmp, datap);
+                        if (ret)
+                                break;
+                        datap++;
+                }
+                break;
+
+        case PTRACE_SETREGS:    /* Set all gp regs in the child. */
+                for (i = 0; i < 19; i++) {
+                        ret = get_user(tmp, datap);
+                        if (ret)
+                                break;
+                        if (i == PT_SR) {
+                                tmp &= SR_MASK;
+                                tmp |= get_reg(child, PT_SR) & ~SR_MASK;
+                        }
+                        put_reg(child, i, tmp);
+                        datap++;
+                }
+                break;
+
+        case PTRACE_GETFPREGS:  /* Get the child FPU state. */
+                if (copy_to_user(datap, &child->thread.fp,
+                                 sizeof(struct user_m68kfp_struct)))
+                        ret = -EFAULT;
+                break;
+
+        case PTRACE_SETFPREGS:  /* Set the child FPU state. */
+                if (copy_from_user(&child->thread.fp, datap,
+                                   sizeof(struct user_m68kfp_struct)))
+                        ret = -EFAULT;
+                break;
+
+        case PTRACE_GET_THREAD_AREA:
+                ret = put_user(task_thread_info(child)->tp_value, datap);
+                break;
+
+        default:
+                ret = ptrace_request(child, request, addr, data);
+                break;
+        }
+
+        return ret;
+out_eio:
+        return -EIO;
+}
+
+asmlinkage void syscall_trace(void)
+{
+        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
+                                 ? 0x80 : 0));
+        /*
+         * this isn't the same as continuing with a signal, but it will do
+         * for normal use.  strace only continues with a signal if the
+         * stopping signal is not SIGTRAP.  -brl
+         */
+        if (current->exit_code) {
+                send_sig(current->exit_code, current, 1);
+                current->exit_code = 0;
+        }
+}
diff --git a/arch/m68k/kernel/ptrace_no.c b/arch/m68k/kernel/ptrace_no.c
new file mode 100644
index 00000000000..6709fb70733
--- /dev/null
+++ b/arch/m68k/kernel/ptrace_no.c
@@ -0,0 +1,255 @@
+/*
+ *  linux/arch/m68knommu/kernel/ptrace.c
+ *
+ *  Copyright (C) 1994 by Hamish Macdonald
+ *  Taken from linux/kernel/ptrace.c and modified for M680x0.
+ *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of
+ * this archive for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/signal.h>
+#include <linux/tracehook.h>
+
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+
+/*
+ * does not yet catch signals sent when the child dies.
+ * in exit.c or in signal.c.
+ */
+
+/* determines which bits in the SR the user has access to. */
+/* 1 = access 0 = no access */
+#define SR_MASK 0x001f
+
+/* sets the trace bits. */
+#define TRACE_BITS 0x8000
+
+/* Find the stack offset for a register, relative to thread.esp0. */
+#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
+#define SW_REG(reg)     ((long)&((struct switch_stack *)0)->reg \
+                         - sizeof(struct switch_stack))
+/* Mapping from PT_xxx to the stack offset at which the register is
+   saved.  Notice that usp has no stack-slot and needs to be treated
+   specially (see get_reg/put_reg below). */
+static int regoff[] = {
+        PT_REG(d1), PT_REG(d2), PT_REG(d3), PT_REG(d4),
+        PT_REG(d5), SW_REG(d6), SW_REG(d7), PT_REG(a0),
+        PT_REG(a1), PT_REG(a2), SW_REG(a3), SW_REG(a4),
+        SW_REG(a5), SW_REG(a6), PT_REG(d0), -1,
+        PT_REG(orig_d0), PT_REG(sr), PT_REG(pc),
+};
+
+/*
+ * Get contents of register REGNO in task TASK.
+ */
+static inline long get_reg(struct task_struct *task, int regno)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
+        else
+                return 0;
+        return *addr;
+}
+
+/*
+ * Write contents of register REGNO in task TASK.
+ */
+static inline int put_reg(struct task_struct *task, int regno,
+                          unsigned long data)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *) (task->thread.esp0 + regoff[regno]);
+        else
+                return -1;
+        *addr = data;
+        return 0;
+}
+
+void user_enable_single_step(struct task_struct *task)
+{
+        unsigned long srflags;
+        srflags = get_reg(task, PT_SR) | (TRACE_BITS << 16);
+        put_reg(task, PT_SR, srflags);
+}
+
+void user_disable_single_step(struct task_struct *task)
+{
+        unsigned long srflags;
+        srflags = get_reg(task, PT_SR) & ~(TRACE_BITS << 16);
+        put_reg(task, PT_SR, srflags);
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure the single step bit is not set.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+        /* make sure the single step bit is not set. */
+        user_disable_single_step(child);
+}
+
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
+{
+        int ret;
+        int regno = addr >> 2;
+        unsigned long __user *datap = (unsigned long __user *) data;
+
+        switch (request) {
+                /* read the word at location addr in the USER area. */
+                case PTRACE_PEEKUSR: {
+                        unsigned long tmp;
+                        
+                        ret = -EIO;
+                        if ((addr & 3) || addr > sizeof(struct user) - 3)
+                                break;
+                        
+                        tmp = 0;  /* Default return condition */
+                        ret = -EIO;
+                        if (regno < 19) {
+                                tmp = get_reg(child, regno);
+                                if (regno == PT_SR)
+                                        tmp >>= 16;
+                        } else if (regno >= 21 && regno < 49) {
+                                tmp = child->thread.fp[regno - 21];
+                        } else if (regno == 49) {
+                                tmp = child->mm->start_code;
+                        } else if (regno == 50) {
+                                tmp = child->mm->start_data;
+                        } else if (regno == 51) {
+                                tmp = child->mm->end_code;
+                        } else
+                                break;
+                        ret = put_user(tmp, datap);
+                        break;
+                }
+
+                case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
+                        ret = -EIO;
+                        if ((addr & 3) || addr > sizeof(struct user) - 3)
+                                break;
+
+                        if (regno == PT_SR) {
+                                data &= SR_MASK;
+                                data <<= 16;
+                                data |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
+                        }
+                        if (regno < 19) {
+                                if (put_reg(child, regno, data))
+                                        break;
+                                ret = 0;
+                                break;
+                        }
+                        if (regno >= 21 && regno < 48)
+                        {
+                                child->thread.fp[regno - 21] = data;
+                                ret = 0;
+                        }
+                        break;
+
+                case PTRACE_GETREGS: { /* Get all gp regs from the child. */
+                        int i;
+                        unsigned long tmp;
+                        for (i = 0; i < 19; i++) {
+                            tmp = get_reg(child, i);
+                            if (i == PT_SR)
+                                tmp >>= 16;
+                            if (put_user(tmp, datap)) {
+                                ret = -EFAULT;
+                                break;
+                            }
+                            datap++;
+                        }
+                        ret = 0;
+                        break;
+                }
+
+                case PTRACE_SETREGS: { /* Set all gp regs in the child. */
+                        int i;
+                        unsigned long tmp;
+                        for (i = 0; i < 19; i++) {
+                            if (get_user(tmp, datap)) {
+                                ret = -EFAULT;
+                                break;
+                            }
+                            if (i == PT_SR) {
+                                tmp &= SR_MASK;
+                                tmp <<= 16;
+                                tmp |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
+                            }
+                            put_reg(child, i, tmp);
+                            datap++;
+                        }
+                        ret = 0;
+                        break;
+                }
+
+#ifdef PTRACE_GETFPREGS
+                case PTRACE_GETFPREGS: { /* Get the child FPU state. */
+                        ret = 0;
+                        if (copy_to_user(datap, &child->thread.fp,
+                                         sizeof(struct user_m68kfp_struct)))
+                                ret = -EFAULT;
+                        break;
+                }
+#endif
+
+#ifdef PTRACE_SETFPREGS
+                case PTRACE_SETFPREGS: { /* Set the child FPU state. */
+                        ret = 0;
+                        if (copy_from_user(&child->thread.fp, datap,
+                                           sizeof(struct user_m68kfp_struct)))
+                                ret = -EFAULT;
+                        break;
+                }
+#endif
+
+        case PTRACE_GET_THREAD_AREA:
+                ret = put_user(task_thread_info(child)->tp_value, datap);
+                break;
+
+                default:
+                        ret = ptrace_request(child, request, addr, data);
+                        break;
+        }
+        return ret;
+}
+
+asmlinkage int syscall_trace_enter(void)
+{
+        int ret = 0;
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                ret = tracehook_report_syscall_entry(task_pt_regs(current));
+        return ret;
+}
+
+asmlinkage void syscall_trace_leave(void)
+{
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(task_pt_regs(current), 0);
+}
diff --git a/arch/m68k/kernel/signal_mm.c b/arch/m68k/kernel/signal_mm.c
new file mode 100644
index 00000000000..a0afc239304
--- /dev/null
+++ b/arch/m68k/kernel/signal_mm.c
@@ -0,0 +1,1017 @@
+/*
+ *  linux/arch/m68k/kernel/signal.c
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ *
+ * 1997-12-01  Modified for POSIX.1b signals by Andreas Schwab
+ *
+ * mathemu support by Roman Zippel
+ *  (Note: fpstate in the signal context is completely ignored for the emulator
+ *         and the internal floating point format is put on stack)
+ */
+
+/*
+ * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
+ * Atari :-) Current limitation: Only one sigstack can be active at one time.
+ * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
+ * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
+ * signal handlers!
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/syscalls.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/highuid.h>
+#include <linux/personality.h>
+#include <linux/tty.h>
+#include <linux/binfmts.h>
+#include <linux/module.h>
+
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/traps.h>
+#include <asm/ucontext.h>
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+static const int frame_extra_sizes[16] = {
+  [1]   = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
+  [2]   = sizeof(((struct frame *)0)->un.fmt2),
+  [3]   = sizeof(((struct frame *)0)->un.fmt3),
+  [4]   = sizeof(((struct frame *)0)->un.fmt4),
+  [5]   = -1, /* sizeof(((struct frame *)0)->un.fmt5), */
+  [6]   = -1, /* sizeof(((struct frame *)0)->un.fmt6), */
+  [7]   = sizeof(((struct frame *)0)->un.fmt7),
+  [8]   = -1, /* sizeof(((struct frame *)0)->un.fmt8), */
+  [9]   = sizeof(((struct frame *)0)->un.fmt9),
+  [10]  = sizeof(((struct frame *)0)->un.fmta),
+  [11]  = sizeof(((struct frame *)0)->un.fmtb),
+  [12]  = -1, /* sizeof(((struct frame *)0)->un.fmtc), */
+  [13]  = -1, /* sizeof(((struct frame *)0)->un.fmtd), */
+  [14]  = -1, /* sizeof(((struct frame *)0)->un.fmte), */
+  [15]  = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
+};
+
+int handle_kernel_fault(struct pt_regs *regs)
+{
+        const struct exception_table_entry *fixup;
+        struct pt_regs *tregs;
+
+        /* Are we prepared to handle this kernel fault? */
+        fixup = search_exception_tables(regs->pc);
+        if (!fixup)
+                return 0;
+
+        /* Create a new four word stack frame, discarding the old one. */
+        regs->stkadj = frame_extra_sizes[regs->format];
+        tregs = (struct pt_regs *)((long)regs + regs->stkadj);
+        tregs->vector = regs->vector;
+        tregs->format = 0;
+        tregs->pc = fixup->fixup;
+        tregs->sr = regs->sr;
+
+        return 1;
+}
+
+/*
+ * Atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage int
+sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
+{
+        mask &= _BLOCKABLE;
+        spin_lock_irq(&current->sighand->siglock);
+        current->saved_sigmask = current->blocked;
+        siginitset(&current->blocked, mask);
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
+
+        return -ERESTARTNOHAND;
+}
+
+asmlinkage int
+sys_sigaction(int sig, const struct old_sigaction __user *act,
+              struct old_sigaction __user *oact)
+{
+        struct k_sigaction new_ka, old_ka;
+        int ret;
+
+        if (act) {
+                old_sigset_t mask;
+                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
+                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
+                        return -EFAULT;
+                siginitset(&new_ka.sa.sa_mask, mask);
+        }
+
+        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+
+        if (!ret && oact) {
+                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
+                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
+                        return -EFAULT;
+        }
+
+        return ret;
+}
+
+asmlinkage int
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
+{
+        return do_sigaltstack(uss, uoss, rdusp());
+}
+
+
+/*
+ * Do a signal return; undo the signal stack.
+ *
+ * Keep the return code on the stack quadword aligned!
+ * That makes the cache flush below easier.
+ */
+
+struct sigframe
+{
+        char __user *pretcode;
+        int sig;
+        int code;
+        struct sigcontext __user *psc;
+        char retcode[8];
+        unsigned long extramask[_NSIG_WORDS-1];
+        struct sigcontext sc;
+};
+
+struct rt_sigframe
+{
+        char __user *pretcode;
+        int sig;
+        struct siginfo __user *pinfo;
+        void __user *puc;
+        char retcode[8];
+        struct siginfo info;
+        struct ucontext uc;
+};
+
+
+static unsigned char fpu_version;       /* version number of fpu, set by setup_frame */
+
+static inline int restore_fpu_state(struct sigcontext *sc)
+{
+        int err = 1;
+
+        if (FPU_IS_EMU) {
+            /* restore registers */
+            memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
+            memcpy(current->thread.fp, sc->sc_fpregs, 24);
+            return 0;
+        }
+
+        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
+            /* Verify the frame format.  */
+            if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version))
+                goto out;
+            if (CPU_IS_020_OR_030) {
+                if (m68k_fputype & FPU_68881 &&
+                    !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
+                    goto out;
+                if (m68k_fputype & FPU_68882 &&
+                    !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
+                    goto out;
+            } else if (CPU_IS_040) {
+                if (!(sc->sc_fpstate[1] == 0x00 ||
+                      sc->sc_fpstate[1] == 0x28 ||
+                      sc->sc_fpstate[1] == 0x60))
+                    goto out;
+            } else if (CPU_IS_060) {
+                if (!(sc->sc_fpstate[3] == 0x00 ||
+                      sc->sc_fpstate[3] == 0x60 ||
+                      sc->sc_fpstate[3] == 0xe0))
+                    goto out;
+            } else
+                goto out;
+
+            __asm__ volatile (".chip 68k/68881\n\t"
+                              "fmovemx %0,%%fp0-%%fp1\n\t"
+                              "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                              ".chip 68k"
+                              : /* no outputs */
+                              : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl));
+        }
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "frestore %0\n\t"
+                          ".chip 68k" : : "m" (*sc->sc_fpstate));
+        err = 0;
+
+out:
+        return err;
+}
+
+#define FPCONTEXT_SIZE  216
+#define uc_fpstate      uc_filler[0]
+#define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
+#define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
+
+static inline int rt_restore_fpu_state(struct ucontext __user *uc)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = CPU_IS_060 ? 8 : 0;
+        fpregset_t fpregs;
+        int err = 1;
+
+        if (FPU_IS_EMU) {
+                /* restore fpu control register */
+                if (__copy_from_user(current->thread.fpcntl,
+                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
+                        goto out;
+                /* restore all other fpu register */
+                if (__copy_from_user(current->thread.fp,
+                                uc->uc_mcontext.fpregs.f_fpregs, 96))
+                        goto out;
+                return 0;
+        }
+
+        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
+                goto out;
+        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
+                if (!CPU_IS_060)
+                        context_size = fpstate[1];
+                /* Verify the frame format.  */
+                if (!CPU_IS_060 && (fpstate[0] != fpu_version))
+                        goto out;
+                if (CPU_IS_020_OR_030) {
+                        if (m68k_fputype & FPU_68881 &&
+                            !(context_size == 0x18 || context_size == 0xb4))
+                                goto out;
+                        if (m68k_fputype & FPU_68882 &&
+                            !(context_size == 0x38 || context_size == 0xd4))
+                                goto out;
+                } else if (CPU_IS_040) {
+                        if (!(context_size == 0x00 ||
+                              context_size == 0x28 ||
+                              context_size == 0x60))
+                                goto out;
+                } else if (CPU_IS_060) {
+                        if (!(fpstate[3] == 0x00 ||
+                              fpstate[3] == 0x60 ||
+                              fpstate[3] == 0xe0))
+                                goto out;
+                } else
+                        goto out;
+                if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
+                                     sizeof(fpregs)))
+                        goto out;
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %0,%%fp0-%%fp7\n\t"
+                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                                  ".chip 68k"
+                                  : /* no outputs */
+                                  : "m" (*fpregs.f_fpregs),
+                                    "m" (*fpregs.f_fpcntl));
+        }
+        if (context_size &&
+            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
+                             context_size))
+                goto out;
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "frestore %0\n\t"
+                          ".chip 68k" : : "m" (*fpstate));
+        err = 0;
+
+out:
+        return err;
+}
+
+static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
+                               void __user *fp)
+{
+        int fsize = frame_extra_sizes[formatvec >> 12];
+        if (fsize < 0) {
+                /*
+                 * user process trying to return with weird frame format
+                 */
+#ifdef DEBUG
+                printk("user process returning with weird frame format\n");
+#endif
+                return 1;
+        }
+        if (!fsize) {
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
+        } else {
+                struct switch_stack *sw = (struct switch_stack *)regs - 1;
+                unsigned long buf[fsize / 2]; /* yes, twice as much */
+
+                /* that'll make sure that expansion won't crap over data */
+                if (copy_from_user(buf + fsize / 4, fp, fsize))
+                        return 1;
+
+                /* point of no return */
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
+#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
+                __asm__ __volatile__
+                        ("   movel %0,%/a0\n\t"
+                         "   subl %1,%/a0\n\t"     /* make room on stack */
+                         "   movel %/a0,%/sp\n\t"  /* set stack pointer */
+                         /* move switch_stack and pt_regs */
+                         "1: movel %0@+,%/a0@+\n\t"
+                         "   dbra %2,1b\n\t"
+                         "   lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
+                         "   lsrl  #2,%1\n\t"
+                         "   subql #1,%1\n\t"
+                         /* copy to the gap we'd made */
+                         "2: movel %4@+,%/a0@+\n\t"
+                         "   dbra %1,2b\n\t"
+                         "   bral ret_from_signal\n"
+                         : /* no outputs, it doesn't ever return */
+                         : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
+                           "n" (frame_offset), "a" (buf + fsize/4)
+                         : "a0");
+#undef frame_offset
+        }
+        return 0;
+}
+
+static inline int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
+{
+        int formatvec;
+        struct sigcontext context;
+        int err;
+
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+        /* get previous context */
+        if (copy_from_user(&context, usc, sizeof(context)))
+                goto badframe;
+
+        /* restore passed registers */
+        regs->d0 = context.sc_d0;
+        regs->d1 = context.sc_d1;
+        regs->a0 = context.sc_a0;
+        regs->a1 = context.sc_a1;
+        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
+        regs->pc = context.sc_pc;
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        wrusp(context.sc_usp);
+        formatvec = context.sc_formatvec;
+
+        err = restore_fpu_state(&context);
+
+        if (err || mangle_kernel_stack(regs, formatvec, fp))
+                goto badframe;
+
+        return 0;
+
+badframe:
+        return 1;
+}
+
+static inline int
+rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
+                    struct ucontext __user *uc)
+{
+        int temp;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        unsigned long usp;
+        int err;
+
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+        err = __get_user(temp, &uc->uc_mcontext.version);
+        if (temp != MCONTEXT_VERSION)
+                goto badframe;
+        /* restore passed registers */
+        err |= __get_user(regs->d0, &gregs[0]);
+        err |= __get_user(regs->d1, &gregs[1]);
+        err |= __get_user(regs->d2, &gregs[2]);
+        err |= __get_user(regs->d3, &gregs[3]);
+        err |= __get_user(regs->d4, &gregs[4]);
+        err |= __get_user(regs->d5, &gregs[5]);
+        err |= __get_user(sw->d6, &gregs[6]);
+        err |= __get_user(sw->d7, &gregs[7]);
+        err |= __get_user(regs->a0, &gregs[8]);
+        err |= __get_user(regs->a1, &gregs[9]);
+        err |= __get_user(regs->a2, &gregs[10]);
+        err |= __get_user(sw->a3, &gregs[11]);
+        err |= __get_user(sw->a4, &gregs[12]);
+        err |= __get_user(sw->a5, &gregs[13]);
+        err |= __get_user(sw->a6, &gregs[14]);
+        err |= __get_user(usp, &gregs[15]);
+        wrusp(usp);
+        err |= __get_user(regs->pc, &gregs[16]);
+        err |= __get_user(temp, &gregs[17]);
+        regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        err |= __get_user(temp, &uc->uc_formatvec);
+
+        err |= rt_restore_fpu_state(uc);
+
+        if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
+                goto badframe;
+
+        if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
+                goto badframe;
+
+        return 0;
+
+badframe:
+        return 1;
+}
+
+asmlinkage int do_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
+        sigset_t set;
+
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
+            (_NSIG_WORDS > 1 &&
+             __copy_from_user(&set.sig[1], &frame->extramask,
+                              sizeof(frame->extramask))))
+                goto badframe;
+
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        current->blocked = set;
+        recalc_sigpending();
+
+        if (restore_sigcontext(regs, &frame->sc, frame + 1))
+                goto badframe;
+        return regs->d0;
+
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+
+asmlinkage int do_rt_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
+        sigset_t set;
+
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+                goto badframe;
+
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        current->blocked = set;
+        recalc_sigpending();
+
+        if (rt_restore_ucontext(regs, sw, &frame->uc))
+                goto badframe;
+        return regs->d0;
+
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+
+/*
+ * Set up a signal frame.
+ */
+
+static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+        if (FPU_IS_EMU) {
+                /* save registers */
+                memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
+                memcpy(sc->sc_fpregs, current->thread.fp, 24);
+                return;
+        }
+
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "fsave %0\n\t"
+                          ".chip 68k"
+                          : : "m" (*sc->sc_fpstate) : "memory");
+
+        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
+                fpu_version = sc->sc_fpstate[0];
+                if (CPU_IS_020_OR_030 &&
+                    regs->vector >= (VEC_FPBRUC * 4) &&
+                    regs->vector <= (VEC_FPNAN * 4)) {
+                        /* Clear pending exception in 68882 idle frame */
+                        if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
+                                sc->sc_fpstate[0x38] |= 1 << 3;
+                }
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %%fp0-%%fp1,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                  ".chip 68k"
+                                  : "=m" (*sc->sc_fpregs),
+                                    "=m" (*sc->sc_fpcntl)
+                                  : /* no inputs */
+                                  : "memory");
+        }
+}
+
+static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = CPU_IS_060 ? 8 : 0;
+        int err = 0;
+
+        if (FPU_IS_EMU) {
+                /* save fpu control register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
+                                current->thread.fpcntl, 12);
+                /* save all other fpu register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
+                                current->thread.fp, 96);
+                return err;
+        }
+
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "fsave %0\n\t"
+                          ".chip 68k"
+                          : : "m" (*fpstate) : "memory");
+
+        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
+        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
+                fpregset_t fpregs;
+                if (!CPU_IS_060)
+                        context_size = fpstate[1];
+                fpu_version = fpstate[0];
+                if (CPU_IS_020_OR_030 &&
+                    regs->vector >= (VEC_FPBRUC * 4) &&
+                    regs->vector <= (VEC_FPNAN * 4)) {
+                        /* Clear pending exception in 68882 idle frame */
+                        if (*(unsigned short *) fpstate == 0x1f38)
+                                fpstate[0x38] |= 1 << 3;
+                }
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %%fp0-%%fp7,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                  ".chip 68k"
+                                  : "=m" (*fpregs.f_fpregs),
+                                    "=m" (*fpregs.f_fpcntl)
+                                  : /* no inputs */
+                                  : "memory");
+                err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
+                                    sizeof(fpregs));
+        }
+        if (context_size)
+                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
+                                    context_size);
+        return err;
+}
+
+static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
+                             unsigned long mask)
+{
+        sc->sc_mask = mask;
+        sc->sc_usp = rdusp();
+        sc->sc_d0 = regs->d0;
+        sc->sc_d1 = regs->d1;
+        sc->sc_a0 = regs->a0;
+        sc->sc_a1 = regs->a1;
+        sc->sc_sr = regs->sr;
+        sc->sc_pc = regs->pc;
+        sc->sc_formatvec = regs->format << 12 | regs->vector;
+        save_fpu_state(sc, regs);
+}
+
+static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        int err = 0;
+
+        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
+        err |= __put_user(regs->d0, &gregs[0]);
+        err |= __put_user(regs->d1, &gregs[1]);
+        err |= __put_user(regs->d2, &gregs[2]);
+        err |= __put_user(regs->d3, &gregs[3]);
+        err |= __put_user(regs->d4, &gregs[4]);
+        err |= __put_user(regs->d5, &gregs[5]);
+        err |= __put_user(sw->d6, &gregs[6]);
+        err |= __put_user(sw->d7, &gregs[7]);
+        err |= __put_user(regs->a0, &gregs[8]);
+        err |= __put_user(regs->a1, &gregs[9]);
+        err |= __put_user(regs->a2, &gregs[10]);
+        err |= __put_user(sw->a3, &gregs[11]);
+        err |= __put_user(sw->a4, &gregs[12]);
+        err |= __put_user(sw->a5, &gregs[13]);
+        err |= __put_user(sw->a6, &gregs[14]);
+        err |= __put_user(rdusp(), &gregs[15]);
+        err |= __put_user(regs->pc, &gregs[16]);
+        err |= __put_user(regs->sr, &gregs[17]);
+        err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
+        err |= rt_save_fpu_state(uc, regs);
+        return err;
+}
+
+static inline void push_cache (unsigned long vaddr)
+{
+        /*
+         * Using the old cache_push_v() was really a big waste.
+         *
+         * What we are trying to do is to flush 8 bytes to ram.
+         * Flushing 2 cache lines of 16 bytes is much cheaper than
+         * flushing 1 or 2 pages, as previously done in
+         * cache_push_v().
+         *                                                     Jes
+         */
+        if (CPU_IS_040) {
+                unsigned long temp;
+
+                __asm__ __volatile__ (".chip 68040\n\t"
+                                      "nop\n\t"
+                                      "ptestr (%1)\n\t"
+                                      "movec %%mmusr,%0\n\t"
+                                      ".chip 68k"
+                                      : "=r" (temp)
+                                      : "a" (vaddr));
+
+                temp &= PAGE_MASK;
+                temp |= vaddr & ~PAGE_MASK;
+
+                __asm__ __volatile__ (".chip 68040\n\t"
+                                      "nop\n\t"
+                                      "cpushl %%bc,(%0)\n\t"
+                                      ".chip 68k"
+                                      : : "a" (temp));
+        }
+        else if (CPU_IS_060) {
+                unsigned long temp;
+                __asm__ __volatile__ (".chip 68060\n\t"
+                                      "plpar (%0)\n\t"
+                                      ".chip 68k"
+                                      : "=a" (temp)
+                                      : "0" (vaddr));
+                __asm__ __volatile__ (".chip 68060\n\t"
+                                      "cpushl %%bc,(%0)\n\t"
+                                      ".chip 68k"
+                                      : : "a" (temp));
+        }
+        else {
+                /*
+                 * 68030/68020 have no writeback cache;
+                 * still need to clear icache.
+                 * Note that vaddr is guaranteed to be long word aligned.
+                 */
+                unsigned long temp;
+                asm volatile ("movec %%cacr,%0" : "=r" (temp));
+                temp += 4;
+                asm volatile ("movec %0,%%caar\n\t"
+                              "movec %1,%%cacr"
+                              : : "r" (vaddr), "r" (temp));
+                asm volatile ("movec %0,%%caar\n\t"
+                              "movec %1,%%cacr"
+                              : : "r" (vaddr + 4), "r" (temp));
+        }
+}
+
+static inline void __user *
+get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
+{
+        unsigned long usp;
+
+        /* Default to using normal stack.  */
+        usp = rdusp();
+
+        /* This is the X/Open sanctioned signal stack switching.  */
+        if (ka->sa.sa_flags & SA_ONSTACK) {
+                if (!sas_ss_flags(usp))
+                        usp = current->sas_ss_sp + current->sas_ss_size;
+        }
+        return (void __user *)((usp - frame_size) & -8UL);
+}
+
+static int setup_frame (int sig, struct k_sigaction *ka,
+                         sigset_t *set, struct pt_regs *regs)
+{
+        struct sigframe __user *frame;
+        int fsize = frame_extra_sizes[regs->format];
+        struct sigcontext context;
+        int err = 0;
+
+        if (fsize < 0) {
+#ifdef DEBUG
+                printk ("setup_frame: Unknown frame format %#x\n",
+                        regs->format);
+#endif
+                goto give_sigsegv;
+        }
+
+        frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
+
+        if (fsize)
+                err |= copy_to_user (frame + 1, regs + 1, fsize);
+
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+
+        err |= __put_user(regs->vector, &frame->code);
+        err |= __put_user(&frame->sc, &frame->psc);
+
+        if (_NSIG_WORDS > 1)
+                err |= copy_to_user(frame->extramask, &set->sig[1],
+                                    sizeof(frame->extramask));
+
+        setup_sigcontext(&context, regs, set->sig[0]);
+        err |= copy_to_user (&frame->sc, &context, sizeof(context));
+
+        /* Set up to return from userspace.  */
+        err |= __put_user(frame->retcode, &frame->pretcode);
+        /* moveq #,d0; trap #0 */
+        err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
+                          (long __user *)(frame->retcode));
+
+        if (err)
+                goto give_sigsegv;
+
+        push_cache ((unsigned long) &frame->retcode);
+
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#ifdef DEBUG
+                printk("Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return 0;
+
+give_sigsegv:
+        force_sigsegv(sig, current);
+        return err;
+}
+
+static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
+                            sigset_t *set, struct pt_regs *regs)
+{
+        struct rt_sigframe __user *frame;
+        int fsize = frame_extra_sizes[regs->format];
+        int err = 0;
+
+        if (fsize < 0) {
+#ifdef DEBUG
+                printk ("setup_frame: Unknown frame format %#x\n",
+                        regs->format);
+#endif
+                goto give_sigsegv;
+        }
+
+        frame = get_sigframe(ka, regs, sizeof(*frame));
+
+        if (fsize)
+                err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
+
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+        err |= __put_user(&frame->info, &frame->pinfo);
+        err |= __put_user(&frame->uc, &frame->puc);
+        err |= copy_siginfo_to_user(&frame->info, info);
+
+        /* Create the ucontext.  */
+        err |= __put_user(0, &frame->uc.uc_flags);
+        err |= __put_user(NULL, &frame->uc.uc_link);
+        err |= __put_user((void __user *)current->sas_ss_sp,
+                          &frame->uc.uc_stack.ss_sp);
+        err |= __put_user(sas_ss_flags(rdusp()),
+                          &frame->uc.uc_stack.ss_flags);
+        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
+        err |= rt_setup_ucontext(&frame->uc, regs);
+        err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
+
+        /* Set up to return from userspace.  */
+        err |= __put_user(frame->retcode, &frame->pretcode);
+#ifdef __mcoldfire__
+        /* movel #__NR_rt_sigreturn,d0; trap #0 */
+        err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
+        err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
+                          (long __user *)(frame->retcode + 4));
+#else
+        /* moveq #,d0; notb d0; trap #0 */
+        err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
+                          (long __user *)(frame->retcode + 0));
+        err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
+#endif
+
+        if (err)
+                goto give_sigsegv;
+
+        push_cache ((unsigned long) &frame->retcode);
+
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#ifdef DEBUG
+                printk("Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return 0;
+
+give_sigsegv:
+        force_sigsegv(sig, current);
+        return err;
+}
+
+static inline void
+handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
+{
+        switch (regs->d0) {
+        case -ERESTARTNOHAND:
+                if (!has_handler)
+                        goto do_restart;
+                regs->d0 = -EINTR;
+                break;
+
+        case -ERESTART_RESTARTBLOCK:
+                if (!has_handler) {
+                        regs->d0 = __NR_restart_syscall;
+                        regs->pc -= 2;
+                        break;
+                }
+                regs->d0 = -EINTR;
+                break;
+
+        case -ERESTARTSYS:
+                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
+                        regs->d0 = -EINTR;
+                        break;
+                }
+        /* fallthrough */
+        case -ERESTARTNOINTR:
+        do_restart:
+                regs->d0 = regs->orig_d0;
+                regs->pc -= 2;
+                break;
+        }
+}
+
+void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
+{
+        if (regs->orig_d0 < 0)
+                return;
+        switch (regs->d0) {
+        case -ERESTARTNOHAND:
+        case -ERESTARTSYS:
+        case -ERESTARTNOINTR:
+                regs->d0 = regs->orig_d0;
+                regs->orig_d0 = -1;
+                regs->pc -= 2;
+                break;
+        }
+}
+
+/*
+ * OK, we're invoking a handler
+ */
+static void
+handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
+              sigset_t *oldset, struct pt_regs *regs)
+{
+        int err;
+        /* are we from a system call? */
+        if (regs->orig_d0 >= 0)
+                /* If so, check system call restarting.. */
+                handle_restart(regs, ka, 1);
+
+        /* set up the stack frame */
+        if (ka->sa.sa_flags & SA_SIGINFO)
+                err = setup_rt_frame(sig, ka, info, oldset, regs);
+        else
+                err = setup_frame(sig, ka, oldset, regs);
+
+        if (err)
+                return;
+
+        sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
+        if (!(ka->sa.sa_flags & SA_NODEFER))
+                sigaddset(&current->blocked,sig);
+        recalc_sigpending();
+
+        if (test_thread_flag(TIF_DELAYED_TRACE)) {
+                regs->sr &= ~0x8000;
+                send_sig(SIGTRAP, current, 1);
+        }
+
+        clear_thread_flag(TIF_RESTORE_SIGMASK);
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ */
+asmlinkage void do_signal(struct pt_regs *regs)
+{
+        siginfo_t info;
+        struct k_sigaction ka;
+        int signr;
+        sigset_t *oldset;
+
+        current->thread.esp0 = (unsigned long) regs;
+
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
+                oldset = &current->blocked;
+
+        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        if (signr > 0) {
+                /* Whee!  Actually deliver the signal.  */
+                handle_signal(signr, &ka, &info, oldset, regs);
+                return;
+        }
+
+        /* Did we come from a system call? */
+        if (regs->orig_d0 >= 0)
+                /* Restart the system call - no handlers present */
+                handle_restart(regs, NULL, 0);
+
+        /* If there's no signal to deliver, we just restore the saved mask.  */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
+}
diff --git a/arch/m68k/kernel/signal_no.c b/arch/m68k/kernel/signal_no.c
new file mode 100644
index 00000000000..36a81bb6835
--- /dev/null
+++ b/arch/m68k/kernel/signal_no.c
@@ -0,0 +1,765 @@
+/*
+ *  linux/arch/m68knommu/kernel/signal.c
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ *
+ * 1997-12-01  Modified for POSIX.1b signals by Andreas Schwab
+ *
+ * mathemu support by Roman Zippel
+ *  (Note: fpstate in the signal context is completely ignored for the emulator
+ *         and the internal floating point format is put on stack)
+ */
+
+/*
+ * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
+ * Atari :-) Current limitation: Only one sigstack can be active at one time.
+ * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
+ * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
+ * signal handlers!
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/syscalls.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/highuid.h>
+#include <linux/tty.h>
+#include <linux/personality.h>
+#include <linux/binfmts.h>
+
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/traps.h>
+#include <asm/ucontext.h>
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+void ret_from_user_signal(void);
+void ret_from_user_rt_signal(void);
+
+/*
+ * Atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage int
+sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
+{
+        mask &= _BLOCKABLE;
+        spin_lock_irq(&current->sighand->siglock);
+        current->saved_sigmask = current->blocked;
+        siginitset(&current->blocked, mask);
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
+
+        return -ERESTARTNOHAND;
+}
+
+asmlinkage int
+sys_sigaction(int sig, const struct old_sigaction __user *act,
+              struct old_sigaction __user *oact)
+{
+        struct k_sigaction new_ka, old_ka;
+        int ret;
+
+        if (act) {
+                old_sigset_t mask;
+                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
+                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
+                        return -EFAULT;
+                siginitset(&new_ka.sa.sa_mask, mask);
+        }
+
+        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+
+        if (!ret && oact) {
+                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
+                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
+                        return -EFAULT;
+        }
+
+        return ret;
+}
+
+asmlinkage int
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
+{
+        return do_sigaltstack(uss, uoss, rdusp());
+}
+
+
+/*
+ * Do a signal return; undo the signal stack.
+ *
+ * Keep the return code on the stack quadword aligned!
+ * That makes the cache flush below easier.
+ */
+
+struct sigframe
+{
+        char __user *pretcode;
+        int sig;
+        int code;
+        struct sigcontext __user *psc;
+        char retcode[8];
+        unsigned long extramask[_NSIG_WORDS-1];
+        struct sigcontext sc;
+};
+
+struct rt_sigframe
+{
+        char __user *pretcode;
+        int sig;
+        struct siginfo __user *pinfo;
+        void __user *puc;
+        char retcode[8];
+        struct siginfo info;
+        struct ucontext uc;
+};
+
+#ifdef CONFIG_FPU
+
+static unsigned char fpu_version = 0;   /* version number of fpu, set by setup_frame */
+
+static inline int restore_fpu_state(struct sigcontext *sc)
+{
+        int err = 1;
+
+        if (FPU_IS_EMU) {
+            /* restore registers */
+            memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
+            memcpy(current->thread.fp, sc->sc_fpregs, 24);
+            return 0;
+        }
+
+        if (sc->sc_fpstate[0]) {
+            /* Verify the frame format.  */
+            if (sc->sc_fpstate[0] != fpu_version)
+                goto out;
+
+            __asm__ volatile (".chip 68k/68881\n\t"
+                              "fmovemx %0,%%fp0-%%fp1\n\t"
+                              "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                              ".chip 68k"
+                              : /* no outputs */
+                              : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl));
+        }
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "frestore %0\n\t"
+                          ".chip 68k" : : "m" (*sc->sc_fpstate));
+        err = 0;
+
+out:
+        return err;
+}
+
+#define FPCONTEXT_SIZE  216
+#define uc_fpstate      uc_filler[0]
+#define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
+#define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
+
+static inline int rt_restore_fpu_state(struct ucontext __user *uc)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = 0;
+        fpregset_t fpregs;
+        int err = 1;
+
+        if (FPU_IS_EMU) {
+                /* restore fpu control register */
+                if (__copy_from_user(current->thread.fpcntl,
+                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
+                        goto out;
+                /* restore all other fpu register */
+                if (__copy_from_user(current->thread.fp,
+                                uc->uc_mcontext.fpregs.f_fpregs, 96))
+                        goto out;
+                return 0;
+        }
+
+        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
+                goto out;
+        if (fpstate[0]) {
+                context_size = fpstate[1];
+
+                /* Verify the frame format.  */
+                if (fpstate[0] != fpu_version)
+                        goto out;
+                if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
+                     sizeof(fpregs)))
+                        goto out;
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %0,%%fp0-%%fp7\n\t"
+                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                                  ".chip 68k"
+                                  : /* no outputs */
+                                  : "m" (*fpregs.f_fpregs),
+                                    "m" (*fpregs.f_fpcntl));
+        }
+        if (context_size &&
+            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
+                             context_size))
+                goto out;
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "frestore %0\n\t"
+                          ".chip 68k" : : "m" (*fpstate));
+        err = 0;
+
+out:
+        return err;
+}
+
+#endif
+
+static inline int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp,
+                   int *pd0)
+{
+        int formatvec;
+        struct sigcontext context;
+        int err = 0;
+
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+        /* get previous context */
+        if (copy_from_user(&context, usc, sizeof(context)))
+                goto badframe;
+        
+        /* restore passed registers */
+        regs->d1 = context.sc_d1;
+        regs->a0 = context.sc_a0;
+        regs->a1 = context.sc_a1;
+        ((struct switch_stack *)regs - 1)->a5 = context.sc_a5;
+        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
+        regs->pc = context.sc_pc;
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        wrusp(context.sc_usp);
+        formatvec = context.sc_formatvec;
+        regs->format = formatvec >> 12;
+        regs->vector = formatvec & 0xfff;
+
+#ifdef CONFIG_FPU
+        err = restore_fpu_state(&context);
+#endif
+
+        *pd0 = context.sc_d0;
+        return err;
+
+badframe:
+        return 1;
+}
+
+static inline int
+rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
+                    struct ucontext __user *uc, int *pd0)
+{
+        int temp;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        unsigned long usp;
+        int err;
+
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+        err = __get_user(temp, &uc->uc_mcontext.version);
+        if (temp != MCONTEXT_VERSION)
+                goto badframe;
+        /* restore passed registers */
+        err |= __get_user(regs->d0, &gregs[0]);
+        err |= __get_user(regs->d1, &gregs[1]);
+        err |= __get_user(regs->d2, &gregs[2]);
+        err |= __get_user(regs->d3, &gregs[3]);
+        err |= __get_user(regs->d4, &gregs[4]);
+        err |= __get_user(regs->d5, &gregs[5]);
+        err |= __get_user(sw->d6, &gregs[6]);
+        err |= __get_user(sw->d7, &gregs[7]);
+        err |= __get_user(regs->a0, &gregs[8]);
+        err |= __get_user(regs->a1, &gregs[9]);
+        err |= __get_user(regs->a2, &gregs[10]);
+        err |= __get_user(sw->a3, &gregs[11]);
+        err |= __get_user(sw->a4, &gregs[12]);
+        err |= __get_user(sw->a5, &gregs[13]);
+        err |= __get_user(sw->a6, &gregs[14]);
+        err |= __get_user(usp, &gregs[15]);
+        wrusp(usp);
+        err |= __get_user(regs->pc, &gregs[16]);
+        err |= __get_user(temp, &gregs[17]);
+        regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        regs->format = temp >> 12;
+        regs->vector = temp & 0xfff;
+
+        if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
+                goto badframe;
+
+        *pd0 = regs->d0;
+        return err;
+
+badframe:
+        return 1;
+}
+
+asmlinkage int do_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
+        sigset_t set;
+        int d0;
+
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
+            (_NSIG_WORDS > 1 &&
+             __copy_from_user(&set.sig[1], &frame->extramask,
+                              sizeof(frame->extramask))))
+                goto badframe;
+
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        spin_lock_irq(&current->sighand->siglock);
+        current->blocked = set;
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+        
+        if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
+                goto badframe;
+        return d0;
+
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+
+asmlinkage int do_rt_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
+        sigset_t set;
+        int d0;
+
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+                goto badframe;
+
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        spin_lock_irq(&current->sighand->siglock);
+        current->blocked = set;
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+        
+        if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
+                goto badframe;
+        return d0;
+
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+
+#ifdef CONFIG_FPU
+/*
+ * Set up a signal frame.
+ */
+
+static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+        if (FPU_IS_EMU) {
+                /* save registers */
+                memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
+                memcpy(sc->sc_fpregs, current->thread.fp, 24);
+                return;
+        }
+
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "fsave %0\n\t"
+                          ".chip 68k"
+                          : : "m" (*sc->sc_fpstate) : "memory");
+
+        if (sc->sc_fpstate[0]) {
+                fpu_version = sc->sc_fpstate[0];
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %%fp0-%%fp1,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                  ".chip 68k"
+                                  : "=m" (*sc->sc_fpregs),
+                                    "=m" (*sc->sc_fpcntl)
+                                  : /* no inputs */
+                                  : "memory");
+        }
+}
+
+static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = 0;
+        int err = 0;
+
+        if (FPU_IS_EMU) {
+                /* save fpu control register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl,
+                                current->thread.fpcntl, 12);
+                /* save all other fpu register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
+                                current->thread.fp, 96);
+                return err;
+        }
+
+        __asm__ volatile (".chip 68k/68881\n\t"
+                          "fsave %0\n\t"
+                          ".chip 68k"
+                          : : "m" (*fpstate) : "memory");
+
+        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
+        if (fpstate[0]) {
+                fpregset_t fpregs;
+                context_size = fpstate[1];
+                fpu_version = fpstate[0];
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %%fp0-%%fp7,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                  ".chip 68k"
+                                  : "=m" (*fpregs.f_fpregs),
+                                    "=m" (*fpregs.f_fpcntl)
+                                  : /* no inputs */
+                                  : "memory");
+                err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
+                                    sizeof(fpregs));
+        }
+        if (context_size)
+                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
+                                    context_size);
+        return err;
+}
+
+#endif
+
+static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
+                             unsigned long mask)
+{
+        sc->sc_mask = mask;
+        sc->sc_usp = rdusp();
+        sc->sc_d0 = regs->d0;
+        sc->sc_d1 = regs->d1;
+        sc->sc_a0 = regs->a0;
+        sc->sc_a1 = regs->a1;
+        sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5;
+        sc->sc_sr = regs->sr;
+        sc->sc_pc = regs->pc;
+        sc->sc_formatvec = regs->format << 12 | regs->vector;
+#ifdef CONFIG_FPU
+        save_fpu_state(sc, regs);
+#endif
+}
+
+static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        int err = 0;
+
+        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
+        err |= __put_user(regs->d0, &gregs[0]);
+        err |= __put_user(regs->d1, &gregs[1]);
+        err |= __put_user(regs->d2, &gregs[2]);
+        err |= __put_user(regs->d3, &gregs[3]);
+        err |= __put_user(regs->d4, &gregs[4]);
+        err |= __put_user(regs->d5, &gregs[5]);
+        err |= __put_user(sw->d6, &gregs[6]);
+        err |= __put_user(sw->d7, &gregs[7]);
+        err |= __put_user(regs->a0, &gregs[8]);
+        err |= __put_user(regs->a1, &gregs[9]);
+        err |= __put_user(regs->a2, &gregs[10]);
+        err |= __put_user(sw->a3, &gregs[11]);
+        err |= __put_user(sw->a4, &gregs[12]);
+        err |= __put_user(sw->a5, &gregs[13]);
+        err |= __put_user(sw->a6, &gregs[14]);
+        err |= __put_user(rdusp(), &gregs[15]);
+        err |= __put_user(regs->pc, &gregs[16]);
+        err |= __put_user(regs->sr, &gregs[17]);
+#ifdef CONFIG_FPU
+        err |= rt_save_fpu_state(uc, regs);
+#endif
+        return err;
+}
+
+static inline void __user *
+get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
+{
+        unsigned long usp;
+
+        /* Default to using normal stack.  */
+        usp = rdusp();
+
+        /* This is the X/Open sanctioned signal stack switching.  */
+        if (ka->sa.sa_flags & SA_ONSTACK) {
+                if (!sas_ss_flags(usp))
+                        usp = current->sas_ss_sp + current->sas_ss_size;
+        }
+        return (void __user *)((usp - frame_size) & -8UL);
+}
+
+static int setup_frame (int sig, struct k_sigaction *ka,
+                         sigset_t *set, struct pt_regs *regs)
+{
+        struct sigframe __user *frame;
+        struct sigcontext context;
+        int err = 0;
+
+        frame = get_sigframe(ka, regs, sizeof(*frame));
+
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+
+        err |= __put_user(regs->vector, &frame->code);
+        err |= __put_user(&frame->sc, &frame->psc);
+
+        if (_NSIG_WORDS > 1)
+                err |= copy_to_user(frame->extramask, &set->sig[1],
+                                    sizeof(frame->extramask));
+
+        setup_sigcontext(&context, regs, set->sig[0]);
+        err |= copy_to_user (&frame->sc, &context, sizeof(context));
+
+        /* Set up to return from userspace.  */
+        err |= __put_user((void *) ret_from_user_signal, &frame->pretcode);
+
+        if (err)
+                goto give_sigsegv;
+
+        /* Set up registers for signal handler */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+        ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
+        regs->format = 0x4; /*set format byte to make stack appear modulo 4 
+                                                which it will be when doing the rte */
+
+adjust_stack:
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#if defined(DEBUG)
+                printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return err;
+
+give_sigsegv:
+        force_sigsegv(sig, current);
+        goto adjust_stack;
+}
+
+static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
+                            sigset_t *set, struct pt_regs *regs)
+{
+        struct rt_sigframe __user *frame;
+        int err = 0;
+
+        frame = get_sigframe(ka, regs, sizeof(*frame));
+
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+        err |= __put_user(&frame->info, &frame->pinfo);
+        err |= __put_user(&frame->uc, &frame->puc);
+        err |= copy_siginfo_to_user(&frame->info, info);
+
+        /* Create the ucontext.  */
+        err |= __put_user(0, &frame->uc.uc_flags);
+        err |= __put_user(NULL, &frame->uc.uc_link);
+        err |= __put_user((void __user *)current->sas_ss_sp,
+                          &frame->uc.uc_stack.ss_sp);
+        err |= __put_user(sas_ss_flags(rdusp()),
+                          &frame->uc.uc_stack.ss_flags);
+        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
+        err |= rt_setup_ucontext(&frame->uc, regs);
+        err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
+
+        /* Set up to return from userspace.  */
+        err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode);
+
+        if (err)
+                goto give_sigsegv;
+
+        /* Set up registers for signal handler */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+        ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
+        regs->format = 0x4; /*set format byte to make stack appear modulo 4 
+                                                which it will be when doing the rte */
+
+adjust_stack:
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#if defined(DEBUG)
+                printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return err;
+
+give_sigsegv:
+        force_sigsegv(sig, current);
+        goto adjust_stack;
+}
+
+static inline void
+handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
+{
+        switch (regs->d0) {
+        case -ERESTARTNOHAND:
+                if (!has_handler)
+                        goto do_restart;
+                regs->d0 = -EINTR;
+                break;
+
+        case -ERESTART_RESTARTBLOCK:
+                if (!has_handler) {
+                        regs->d0 = __NR_restart_syscall;
+                        regs->pc -= 2;
+                        break;
+                }
+                regs->d0 = -EINTR;
+                break;
+
+        case -ERESTARTSYS:
+                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
+                        regs->d0 = -EINTR;
+                        break;
+                }
+        /* fallthrough */
+        case -ERESTARTNOINTR:
+        do_restart:
+                regs->d0 = regs->orig_d0;
+                regs->pc -= 2;
+                break;
+        }
+}
+
+/*
+ * OK, we're invoking a handler
+ */
+static void
+handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
+              sigset_t *oldset, struct pt_regs *regs)
+{
+        int err;
+        /* are we from a system call? */
+        if (regs->orig_d0 >= 0)
+                /* If so, check system call restarting.. */
+                handle_restart(regs, ka, 1);
+
+        /* set up the stack frame */
+        if (ka->sa.sa_flags & SA_SIGINFO)
+                err = setup_rt_frame(sig, ka, info, oldset, regs);
+        else
+                err = setup_frame(sig, ka, oldset, regs);
+
+        if (err)
+                return;
+
+        spin_lock_irq(&current->sighand->siglock);
+        sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
+        if (!(ka->sa.sa_flags & SA_NODEFER))
+                sigaddset(&current->blocked,sig);
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+
+        clear_thread_flag(TIF_RESTORE_SIGMASK);
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ */
+asmlinkage void do_signal(struct pt_regs *regs)
+{
+        struct k_sigaction ka;
+        siginfo_t info;
+        int signr;
+        sigset_t *oldset;
+
+        /*
+         * We want the common case to go fast, which
+         * is why we may in certain cases get here from
+         * kernel mode. Just return without doing anything
+         * if so.
+         */
+        if (!user_mode(regs))
+                return;
+
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
+                oldset = &current->blocked;
+
+        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        if (signr > 0) {
+                /* Whee!  Actually deliver the signal.  */
+                handle_signal(signr, &ka, &info, oldset, regs);
+                return;
+        }
+
+        /* Did we come from a system call? */
+        if (regs->orig_d0 >= 0) {
+                /* Restart the system call - no handlers present */
+                handle_restart(regs, NULL, 0);
+        }
+
+        /* If there's no signal to deliver, we just restore the saved mask.  */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
+}
diff --git a/arch/m68k/kernel/time_mm.c b/arch/m68k/kernel/time_mm.c
new file mode 100644
index 00000000000..18b34ee5db3
--- /dev/null
+++ b/arch/m68k/kernel/time_mm.c
@@ -0,0 +1,114 @@
+/*
+ *  linux/arch/m68k/kernel/time.c
+ *
+ *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
+ *
+ * This file contains the m68k-specific time handling details.
+ * Most of the stuff is located in the machine specific files.
+ *
+ * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
+ *              "A Kernel Model for Precision Timekeeping" by Dave Mills
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/irq_regs.h>
+
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/profile.h>
+
+static inline int set_rtc_mmss(unsigned long nowtime)
+{
+  if (mach_set_clock_mmss)
+    return mach_set_clock_mmss (nowtime);
+  return -1;
+}
+
+/*
+ * timer_interrupt() needs to keep up the real-time clock,
+ * as well as call the "xtime_update()" routine every clocktick
+ */
+static irqreturn_t timer_interrupt(int irq, void *dummy)
+{
+        xtime_update(1);
+        update_process_times(user_mode(get_irq_regs()));
+        profile_tick(CPU_PROFILING);
+
+#ifdef CONFIG_HEARTBEAT
+        /* use power LED as a heartbeat instead -- much more useful
+           for debugging -- based on the version for PReP by Cort */
+        /* acts like an actual heart beat -- ie thump-thump-pause... */
+        if (mach_heartbeat) {
+            static unsigned cnt = 0, period = 0, dist = 0;
+
+            if (cnt == 0 || cnt == dist)
+                mach_heartbeat( 1 );
+            else if (cnt == 7 || cnt == dist+7)
+                mach_heartbeat( 0 );
+
+            if (++cnt > period) {
+                cnt = 0;
+                /* The hyperbolic function below modifies the heartbeat period
+                 * length in dependency of the current (5min) load. It goes
+                 * through the points f(0)=126, f(1)=86, f(5)=51,
+                 * f(inf)->30. */
+                period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
+                dist = period / 4;
+            }
+        }
+#endif /* CONFIG_HEARTBEAT */
+        return IRQ_HANDLED;
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+        struct rtc_time time;
+        ts->tv_sec = 0;
+        ts->tv_nsec = 0;
+
+        if (mach_hwclk) {
+                mach_hwclk(0, &time);
+
+                if ((time.tm_year += 1900) < 1970)
+                        time.tm_year += 100;
+                ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
+                                      time.tm_hour, time.tm_min, time.tm_sec);
+        }
+}
+
+void __init time_init(void)
+{
+        mach_sched_init(timer_interrupt);
+}
+
+u32 arch_gettimeoffset(void)
+{
+        return mach_gettimeoffset() * 1000;
+}
+
+static int __init rtc_init(void)
+{
+        struct platform_device *pdev;
+
+        if (!mach_hwclk)
+                return -ENODEV;
+
+        pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
+}
+
+module_init(rtc_init);
diff --git a/arch/m68k/kernel/time_no.c b/arch/m68k/kernel/time_no.c
new file mode 100644
index 00000000000..6623909f70e
--- /dev/null
+++ b/arch/m68k/kernel/time_no.c
@@ -0,0 +1,87 @@
+/*
+ *  linux/arch/m68knommu/kernel/time.c
+ *
+ *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
+ *
+ * This file contains the m68k-specific time handling details.
+ * Most of the stuff is located in the machine specific files.
+ *
+ * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
+ *              "A Kernel Model for Precision Timekeeping" by Dave Mills
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/profile.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+
+#include <asm/machdep.h>
+#include <asm/irq_regs.h>
+
+#define TICK_SIZE (tick_nsec / 1000)
+
+static inline int set_rtc_mmss(unsigned long nowtime)
+{
+        if (mach_set_clock_mmss)
+                return mach_set_clock_mmss (nowtime);
+        return -1;
+}
+
+#ifndef CONFIG_GENERIC_CLOCKEVENTS
+/*
+ * timer_interrupt() needs to keep up the real-time clock,
+ * as well as call the "xtime_update()" routine every clocktick
+ */
+irqreturn_t arch_timer_interrupt(int irq, void *dummy)
+{
+
+        if (current->pid)
+                profile_tick(CPU_PROFILING);
+
+        xtime_update(1);
+
+        update_process_times(user_mode(get_irq_regs()));
+
+        return(IRQ_HANDLED);
+}
+#endif
+
+static unsigned long read_rtc_mmss(void)
+{
+        unsigned int year, mon, day, hour, min, sec;
+
+        if (mach_gettod) {
+                mach_gettod(&year, &mon, &day, &hour, &min, &sec);
+                if ((year += 1900) < 1970)
+                        year += 100;
+        } else {
+                year = 1970;
+                mon = day = 1;
+                hour = min = sec = 0;
+        }
+
+
+        return  mktime(year, mon, day, hour, min, sec);
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+        ts->tv_sec = read_rtc_mmss();
+        ts->tv_nsec = 0;
+}
+
+int update_persistent_clock(struct timespec now)
+{
+        return set_rtc_mmss(now.tv_sec);
+}
+
+void time_init(void)
+{
+        hw_timer_init();
+}
diff --git a/arch/m68k/kernel/traps_mm.c b/arch/m68k/kernel/traps_mm.c
new file mode 100644
index 00000000000..4022bbc2887
--- /dev/null
+++ b/arch/m68k/kernel/traps_mm.c
@@ -0,0 +1,1207 @@
+/*
+ *  linux/arch/m68k/kernel/traps.c
+ *
+ *  Copyright (C) 1993, 1994 by Hamish Macdonald
+ *
+ *  68040 fixes by Michael Rausch
+ *  68040 fixes by Martin Apel
+ *  68040 fixes and writeback by Richard Zidlicky
+ *  68060 fixes by Roman Hodek
+ *  68060 fixes by Jesper Skov
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * Sets up all exception vectors
+ */
+
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/user.h>
+#include <linux/string.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <linux/ptrace.h>
+#include <linux/kallsyms.h>
+
+#include <asm/setup.h>
+#include <asm/fpu.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/traps.h>
+#include <asm/pgalloc.h>
+#include <asm/machdep.h>
+#include <asm/siginfo.h>
+
+/* assembler routines */
+asmlinkage void system_call(void);
+asmlinkage void buserr(void);
+asmlinkage void trap(void);
+asmlinkage void nmihandler(void);
+#ifdef CONFIG_M68KFPU_EMU
+asmlinkage void fpu_emu(void);
+#endif
+
+e_vector vectors[256];
+
+/* nmi handler for the Amiga */
+asm(".text\n"
+    __ALIGN_STR "\n"
+    "nmihandler: rte");
+
+/*
+ * this must be called very early as the kernel might
+ * use some instruction that are emulated on the 060
+ * and so we're prepared for early probe attempts (e.g. nf_init).
+ */
+void __init base_trap_init(void)
+{
+        if (MACH_IS_SUN3X) {
+                extern e_vector *sun3x_prom_vbr;
+
+                __asm__ volatile ("movec %%vbr, %0" : "=r" (sun3x_prom_vbr));
+        }
+
+        /* setup the exception vector table */
+        __asm__ volatile ("movec %0,%%vbr" : : "r" ((void*)vectors));
+
+        if (CPU_IS_060) {
+                /* set up ISP entry points */
+                asmlinkage void unimp_vec(void) asm ("_060_isp_unimp");
+
+                vectors[VEC_UNIMPII] = unimp_vec;
+        }
+
+        vectors[VEC_BUSERR] = buserr;
+        vectors[VEC_ILLEGAL] = trap;
+        vectors[VEC_SYS] = system_call;
+}
+
+void __init trap_init (void)
+{
+        int i;
+
+        for (i = VEC_SPUR; i <= VEC_INT7; i++)
+                vectors[i] = bad_inthandler;
+
+        for (i = 0; i < VEC_USER; i++)
+                if (!vectors[i])
+                        vectors[i] = trap;
+
+        for (i = VEC_USER; i < 256; i++)
+                vectors[i] = bad_inthandler;
+
+#ifdef CONFIG_M68KFPU_EMU
+        if (FPU_IS_EMU)
+                vectors[VEC_LINE11] = fpu_emu;
+#endif
+
+        if (CPU_IS_040 && !FPU_IS_EMU) {
+                /* set up FPSP entry points */
+                asmlinkage void dz_vec(void) asm ("dz");
+                asmlinkage void inex_vec(void) asm ("inex");
+                asmlinkage void ovfl_vec(void) asm ("ovfl");
+                asmlinkage void unfl_vec(void) asm ("unfl");
+                asmlinkage void snan_vec(void) asm ("snan");
+                asmlinkage void operr_vec(void) asm ("operr");
+                asmlinkage void bsun_vec(void) asm ("bsun");
+                asmlinkage void fline_vec(void) asm ("fline");
+                asmlinkage void unsupp_vec(void) asm ("unsupp");
+
+                vectors[VEC_FPDIVZ] = dz_vec;
+                vectors[VEC_FPIR] = inex_vec;
+                vectors[VEC_FPOVER] = ovfl_vec;
+                vectors[VEC_FPUNDER] = unfl_vec;
+                vectors[VEC_FPNAN] = snan_vec;
+                vectors[VEC_FPOE] = operr_vec;
+                vectors[VEC_FPBRUC] = bsun_vec;
+                vectors[VEC_LINE11] = fline_vec;
+                vectors[VEC_FPUNSUP] = unsupp_vec;
+        }
+
+        if (CPU_IS_060 && !FPU_IS_EMU) {
+                /* set up IFPSP entry points */
+                asmlinkage void snan_vec6(void) asm ("_060_fpsp_snan");
+                asmlinkage void operr_vec6(void) asm ("_060_fpsp_operr");
+                asmlinkage void ovfl_vec6(void) asm ("_060_fpsp_ovfl");
+                asmlinkage void unfl_vec6(void) asm ("_060_fpsp_unfl");
+                asmlinkage void dz_vec6(void) asm ("_060_fpsp_dz");
+                asmlinkage void inex_vec6(void) asm ("_060_fpsp_inex");
+                asmlinkage void fline_vec6(void) asm ("_060_fpsp_fline");
+                asmlinkage void unsupp_vec6(void) asm ("_060_fpsp_unsupp");
+                asmlinkage void effadd_vec6(void) asm ("_060_fpsp_effadd");
+
+                vectors[VEC_FPNAN] = snan_vec6;
+                vectors[VEC_FPOE] = operr_vec6;
+                vectors[VEC_FPOVER] = ovfl_vec6;
+                vectors[VEC_FPUNDER] = unfl_vec6;
+                vectors[VEC_FPDIVZ] = dz_vec6;
+                vectors[VEC_FPIR] = inex_vec6;
+                vectors[VEC_LINE11] = fline_vec6;
+                vectors[VEC_FPUNSUP] = unsupp_vec6;
+                vectors[VEC_UNIMPEA] = effadd_vec6;
+        }
+
+        /* if running on an amiga, make the NMI interrupt do nothing */
+        if (MACH_IS_AMIGA) {
+                vectors[VEC_INT7] = nmihandler;
+        }
+}
+
+
+static const char *vec_names[] = {
+        [VEC_RESETSP]   = "RESET SP",
+        [VEC_RESETPC]   = "RESET PC",
+        [VEC_BUSERR]    = "BUS ERROR",
+        [VEC_ADDRERR]   = "ADDRESS ERROR",
+        [VEC_ILLEGAL]   = "ILLEGAL INSTRUCTION",
+        [VEC_ZERODIV]   = "ZERO DIVIDE",
+        [VEC_CHK]       = "CHK",
+        [VEC_TRAP]      = "TRAPcc",
+        [VEC_PRIV]      = "PRIVILEGE VIOLATION",
+        [VEC_TRACE]     = "TRACE",
+        [VEC_LINE10]    = "LINE 1010",
+        [VEC_LINE11]    = "LINE 1111",
+        [VEC_RESV12]    = "UNASSIGNED RESERVED 12",
+        [VEC_COPROC]    = "COPROCESSOR PROTOCOL VIOLATION",
+        [VEC_FORMAT]    = "FORMAT ERROR",
+        [VEC_UNINT]     = "UNINITIALIZED INTERRUPT",
+        [VEC_RESV16]    = "UNASSIGNED RESERVED 16",
+        [VEC_RESV17]    = "UNASSIGNED RESERVED 17",
+        [VEC_RESV18]    = "UNASSIGNED RESERVED 18",
+        [VEC_RESV19]    = "UNASSIGNED RESERVED 19",
+        [VEC_RESV20]    = "UNASSIGNED RESERVED 20",
+        [VEC_RESV21]    = "UNASSIGNED RESERVED 21",
+        [VEC_RESV22]    = "UNASSIGNED RESERVED 22",
+        [VEC_RESV23]    = "UNASSIGNED RESERVED 23",
+        [VEC_SPUR]      = "SPURIOUS INTERRUPT",
+        [VEC_INT1]      = "LEVEL 1 INT",
+        [VEC_INT2]      = "LEVEL 2 INT",
+        [VEC_INT3]      = "LEVEL 3 INT",
+        [VEC_INT4]      = "LEVEL 4 INT",
+        [VEC_INT5]      = "LEVEL 5 INT",
+        [VEC_INT6]      = "LEVEL 6 INT",
+        [VEC_INT7]      = "LEVEL 7 INT",
+        [VEC_SYS]       = "SYSCALL",
+        [VEC_TRAP1]     = "TRAP #1",
+        [VEC_TRAP2]     = "TRAP #2",
+        [VEC_TRAP3]     = "TRAP #3",
+        [VEC_TRAP4]     = "TRAP #4",
+        [VEC_TRAP5]     = "TRAP #5",
+        [VEC_TRAP6]     = "TRAP #6",
+        [VEC_TRAP7]     = "TRAP #7",
+        [VEC_TRAP8]     = "TRAP #8",
+        [VEC_TRAP9]     = "TRAP #9",
+        [VEC_TRAP10]    = "TRAP #10",
+        [VEC_TRAP11]    = "TRAP #11",
+        [VEC_TRAP12]    = "TRAP #12",
+        [VEC_TRAP13]    = "TRAP #13",
+        [VEC_TRAP14]    = "TRAP #14",
+        [VEC_TRAP15]    = "TRAP #15",
+        [VEC_FPBRUC]    = "FPCP BSUN",
+        [VEC_FPIR]      = "FPCP INEXACT",
+        [VEC_FPDIVZ]    = "FPCP DIV BY 0",
+        [VEC_FPUNDER]   = "FPCP UNDERFLOW",
+        [VEC_FPOE]      = "FPCP OPERAND ERROR",
+        [VEC_FPOVER]    = "FPCP OVERFLOW",
+        [VEC_FPNAN]     = "FPCP SNAN",
+        [VEC_FPUNSUP]   = "FPCP UNSUPPORTED OPERATION",
+        [VEC_MMUCFG]    = "MMU CONFIGURATION ERROR",
+        [VEC_MMUILL]    = "MMU ILLEGAL OPERATION ERROR",
+        [VEC_MMUACC]    = "MMU ACCESS LEVEL VIOLATION ERROR",
+        [VEC_RESV59]    = "UNASSIGNED RESERVED 59",
+        [VEC_UNIMPEA]   = "UNASSIGNED RESERVED 60",
+        [VEC_UNIMPII]   = "UNASSIGNED RESERVED 61",
+        [VEC_RESV62]    = "UNASSIGNED RESERVED 62",
+        [VEC_RESV63]    = "UNASSIGNED RESERVED 63",
+};
+
+static const char *space_names[] = {
+        [0]             = "Space 0",
+        [USER_DATA]     = "User Data",
+        [USER_PROGRAM]  = "User Program",
+#ifndef CONFIG_SUN3
+        [3]             = "Space 3",
+#else
+        [FC_CONTROL]    = "Control",
+#endif
+        [4]             = "Space 4",
+        [SUPER_DATA]    = "Super Data",
+        [SUPER_PROGRAM] = "Super Program",
+        [CPU_SPACE]     = "CPU"
+};
+
+void die_if_kernel(char *,struct pt_regs *,int);
+asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
+                             unsigned long error_code);
+int send_fault_sig(struct pt_regs *regs);
+
+asmlinkage void trap_c(struct frame *fp);
+
+#if defined (CONFIG_M68060)
+static inline void access_error060 (struct frame *fp)
+{
+        unsigned long fslw = fp->un.fmt4.pc; /* is really FSLW for access error */
+
+#ifdef DEBUG
+        printk("fslw=%#lx, fa=%#lx\n", fslw, fp->un.fmt4.effaddr);
+#endif
+
+        if (fslw & MMU060_BPE) {
+                /* branch prediction error -> clear branch cache */
+                __asm__ __volatile__ ("movec %/cacr,%/d0\n\t"
+                                      "orl   #0x00400000,%/d0\n\t"
+                                      "movec %/d0,%/cacr"
+                                      : : : "d0" );
+                /* return if there's no other error */
+                if (!(fslw & MMU060_ERR_BITS) && !(fslw & MMU060_SEE))
+                        return;
+        }
+
+        if (fslw & (MMU060_DESC_ERR | MMU060_WP | MMU060_SP)) {
+                unsigned long errorcode;
+                unsigned long addr = fp->un.fmt4.effaddr;
+
+                if (fslw & MMU060_MA)
+                        addr = (addr + PAGE_SIZE - 1) & PAGE_MASK;
+
+                errorcode = 1;
+                if (fslw & MMU060_DESC_ERR) {
+                        __flush_tlb040_one(addr);
+                        errorcode = 0;
+                }
+                if (fslw & MMU060_W)
+                        errorcode |= 2;
+#ifdef DEBUG
+                printk("errorcode = %d\n", errorcode );
+#endif
+                do_page_fault(&fp->ptregs, addr, errorcode);
+        } else if (fslw & (MMU060_SEE)){
+                /* Software Emulation Error.
+                 * fault during mem_read/mem_write in ifpsp060/os.S
+                 */
+                send_fault_sig(&fp->ptregs);
+        } else if (!(fslw & (MMU060_RE|MMU060_WE)) ||
+                   send_fault_sig(&fp->ptregs) > 0) {
+                printk("pc=%#lx, fa=%#lx\n", fp->ptregs.pc, fp->un.fmt4.effaddr);
+                printk( "68060 access error, fslw=%lx\n", fslw );
+                trap_c( fp );
+        }
+}
+#endif /* CONFIG_M68060 */
+
+#if defined (CONFIG_M68040)
+static inline unsigned long probe040(int iswrite, unsigned long addr, int wbs)
+{
+        unsigned long mmusr;
+        mm_segment_t old_fs = get_fs();
+
+        set_fs(MAKE_MM_SEG(wbs));
+
+        if (iswrite)
+                asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr));
+        else
+                asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr));
+
+        asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr));
+
+        set_fs(old_fs);
+
+        return mmusr;
+}
+
+static inline int do_040writeback1(unsigned short wbs, unsigned long wba,
+                                   unsigned long wbd)
+{
+        int res = 0;
+        mm_segment_t old_fs = get_fs();
+
+        /* set_fs can not be moved, otherwise put_user() may oops */
+        set_fs(MAKE_MM_SEG(wbs));
+
+        switch (wbs & WBSIZ_040) {
+        case BA_SIZE_BYTE:
+                res = put_user(wbd & 0xff, (char __user *)wba);
+                break;
+        case BA_SIZE_WORD:
+                res = put_user(wbd & 0xffff, (short __user *)wba);
+                break;
+        case BA_SIZE_LONG:
+                res = put_user(wbd, (int __user *)wba);
+                break;
+        }
+
+        /* set_fs can not be moved, otherwise put_user() may oops */
+        set_fs(old_fs);
+
+
+#ifdef DEBUG
+        printk("do_040writeback1, res=%d\n",res);
+#endif
+
+        return res;
+}
+
+/* after an exception in a writeback the stack frame corresponding
+ * to that exception is discarded, set a few bits in the old frame
+ * to simulate what it should look like
+ */
+static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs)
+{
+        fp->un.fmt7.faddr = wba;
+        fp->un.fmt7.ssw = wbs & 0xff;
+        if (wba != current->thread.faddr)
+            fp->un.fmt7.ssw |= MA_040;
+}
+
+static inline void do_040writebacks(struct frame *fp)
+{
+        int res = 0;
+#if 0
+        if (fp->un.fmt7.wb1s & WBV_040)
+                printk("access_error040: cannot handle 1st writeback. oops.\n");
+#endif
+
+        if ((fp->un.fmt7.wb2s & WBV_040) &&
+            !(fp->un.fmt7.wb2s & WBTT_040)) {
+                res = do_040writeback1(fp->un.fmt7.wb2s, fp->un.fmt7.wb2a,
+                                       fp->un.fmt7.wb2d);
+                if (res)
+                        fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s);
+                else
+                        fp->un.fmt7.wb2s = 0;
+        }
+
+        /* do the 2nd wb only if the first one was successful (except for a kernel wb) */
+        if (fp->un.fmt7.wb3s & WBV_040 && (!res || fp->un.fmt7.wb3s & 4)) {
+                res = do_040writeback1(fp->un.fmt7.wb3s, fp->un.fmt7.wb3a,
+                                       fp->un.fmt7.wb3d);
+                if (res)
+                    {
+                        fix_xframe040(fp, fp->un.fmt7.wb3a, fp->un.fmt7.wb3s);
+
+                        fp->un.fmt7.wb2s = fp->un.fmt7.wb3s;
+                        fp->un.fmt7.wb3s &= (~WBV_040);
+                        fp->un.fmt7.wb2a = fp->un.fmt7.wb3a;
+                        fp->un.fmt7.wb2d = fp->un.fmt7.wb3d;
+                    }
+                else
+                        fp->un.fmt7.wb3s = 0;
+        }
+
+        if (res)
+                send_fault_sig(&fp->ptregs);
+}
+
+/*
+ * called from sigreturn(), must ensure userspace code didn't
+ * manipulate exception frame to circumvent protection, then complete
+ * pending writebacks
+ * we just clear TM2 to turn it into a userspace access
+ */
+asmlinkage void berr_040cleanup(struct frame *fp)
+{
+        fp->un.fmt7.wb2s &= ~4;
+        fp->un.fmt7.wb3s &= ~4;
+
+        do_040writebacks(fp);
+}
+
+static inline void access_error040(struct frame *fp)
+{
+        unsigned short ssw = fp->un.fmt7.ssw;
+        unsigned long mmusr;
+
+#ifdef DEBUG
+        printk("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr);
+        printk("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s,
+                fp->un.fmt7.wb2s, fp->un.fmt7.wb3s);
+        printk ("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n",
+                fp->un.fmt7.wb2a, fp->un.fmt7.wb3a,
+                fp->un.fmt7.wb2d, fp->un.fmt7.wb3d);
+#endif
+
+        if (ssw & ATC_040) {
+                unsigned long addr = fp->un.fmt7.faddr;
+                unsigned long errorcode;
+
+                /*
+                 * The MMU status has to be determined AFTER the address
+                 * has been corrected if there was a misaligned access (MA).
+                 */
+                if (ssw & MA_040)
+                        addr = (addr + 7) & -8;
+
+                /* MMU error, get the MMUSR info for this access */
+                mmusr = probe040(!(ssw & RW_040), addr, ssw);
+#ifdef DEBUG
+                printk("mmusr = %lx\n", mmusr);
+#endif
+                errorcode = 1;
+                if (!(mmusr & MMU_R_040)) {
+                        /* clear the invalid atc entry */
+                        __flush_tlb040_one(addr);
+                        errorcode = 0;
+                }
+
+                /* despite what documentation seems to say, RMW
+                 * accesses have always both the LK and RW bits set */
+                if (!(ssw & RW_040) || (ssw & LK_040))
+                        errorcode |= 2;
+
+                if (do_page_fault(&fp->ptregs, addr, errorcode)) {
+#ifdef DEBUG
+                        printk("do_page_fault() !=0\n");
+#endif
+                        if (user_mode(&fp->ptregs)){
+                                /* delay writebacks after signal delivery */
+#ifdef DEBUG
+                                printk(".. was usermode - return\n");
+#endif
+                                return;
+                        }
+                        /* disable writeback into user space from kernel
+                         * (if do_page_fault didn't fix the mapping,
+                         * the writeback won't do good)
+                         */
+disable_wb:
+#ifdef DEBUG
+                        printk(".. disabling wb2\n");
+#endif
+                        if (fp->un.fmt7.wb2a == fp->un.fmt7.faddr)
+                                fp->un.fmt7.wb2s &= ~WBV_040;
+                        if (fp->un.fmt7.wb3a == fp->un.fmt7.faddr)
+                                fp->un.fmt7.wb3s &= ~WBV_040;
+                }
+        } else {
+                /* In case of a bus error we either kill the process or expect
+                 * the kernel to catch the fault, which then is also responsible
+                 * for cleaning up the mess.
+                 */
+                current->thread.signo = SIGBUS;
+                current->thread.faddr = fp->un.fmt7.faddr;
+                if (send_fault_sig(&fp->ptregs) >= 0)
+                        printk("68040 bus error (ssw=%x, faddr=%lx)\n", ssw,
+                               fp->un.fmt7.faddr);
+                goto disable_wb;
+        }
+
+        do_040writebacks(fp);
+}
+#endif /* CONFIG_M68040 */
+
+#if defined(CONFIG_SUN3)
+#include <asm/sun3mmu.h>
+
+extern int mmu_emu_handle_fault (unsigned long, int, int);
+
+/* sun3 version of bus_error030 */
+
+static inline void bus_error030 (struct frame *fp)
+{
+        unsigned char buserr_type = sun3_get_buserr ();
+        unsigned long addr, errorcode;
+        unsigned short ssw = fp->un.fmtb.ssw;
+        extern unsigned long _sun3_map_test_start, _sun3_map_test_end;
+
+#ifdef DEBUG
+        if (ssw & (FC | FB))
+                printk ("Instruction fault at %#010lx\n",
+                        ssw & FC ?
+                        fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
+                        :
+                        fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
+        if (ssw & DF)
+                printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n",
+                        ssw & RW ? "read" : "write",
+                        fp->un.fmtb.daddr,
+                        space_names[ssw & DFC], fp->ptregs.pc);
+#endif
+
+        /*
+         * Check if this page should be demand-mapped. This needs to go before
+         * the testing for a bad kernel-space access (demand-mapping applies
+         * to kernel accesses too).
+         */
+
+        if ((ssw & DF)
+            && (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) {
+                if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0))
+                        return;
+        }
+
+        /* Check for kernel-space pagefault (BAD). */
+        if (fp->ptregs.sr & PS_S) {
+                /* kernel fault must be a data fault to user space */
+                if (! ((ssw & DF) && ((ssw & DFC) == USER_DATA))) {
+                     // try checking the kernel mappings before surrender
+                     if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 1))
+                          return;
+                        /* instruction fault or kernel data fault! */
+                        if (ssw & (FC | FB))
+                                printk ("Instruction fault at %#010lx\n",
+                                        fp->ptregs.pc);
+                        if (ssw & DF) {
+                                /* was this fault incurred testing bus mappings? */
+                                if((fp->ptregs.pc >= (unsigned long)&_sun3_map_test_start) &&
+                                   (fp->ptregs.pc <= (unsigned long)&_sun3_map_test_end)) {
+                                        send_fault_sig(&fp->ptregs);
+                                        return;
+                                }
+
+                                printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n",
+                                        ssw & RW ? "read" : "write",
+                                        fp->un.fmtb.daddr,
+                                        space_names[ssw & DFC], fp->ptregs.pc);
+                        }
+                        printk ("BAD KERNEL BUSERR\n");
+
+                        die_if_kernel("Oops", &fp->ptregs,0);
+                        force_sig(SIGKILL, current);
+                        return;
+                }
+        } else {
+                /* user fault */
+                if (!(ssw & (FC | FB)) && !(ssw & DF))
+                        /* not an instruction fault or data fault! BAD */
+                        panic ("USER BUSERR w/o instruction or data fault");
+        }
+
+
+        /* First handle the data fault, if any.  */
+        if (ssw & DF) {
+                addr = fp->un.fmtb.daddr;
+
+// errorcode bit 0:     0 -> no page            1 -> protection fault
+// errorcode bit 1:     0 -> read fault         1 -> write fault
+
+// (buserr_type & SUN3_BUSERR_PROTERR)  -> protection fault
+// (buserr_type & SUN3_BUSERR_INVALID)  -> invalid page fault
+
+                if (buserr_type & SUN3_BUSERR_PROTERR)
+                        errorcode = 0x01;
+                else if (buserr_type & SUN3_BUSERR_INVALID)
+                        errorcode = 0x00;
+                else {
+#ifdef DEBUG
+                        printk ("*** unexpected busfault type=%#04x\n", buserr_type);
+                        printk ("invalid %s access at %#lx from pc %#lx\n",
+                                !(ssw & RW) ? "write" : "read", addr,
+                                fp->ptregs.pc);
+#endif
+                        die_if_kernel ("Oops", &fp->ptregs, buserr_type);
+                        force_sig (SIGBUS, current);
+                        return;
+                }
+
+//todo: wtf is RM bit? --m
+                if (!(ssw & RW) || ssw & RM)
+                        errorcode |= 0x02;
+
+                /* Handle page fault. */
+                do_page_fault (&fp->ptregs, addr, errorcode);
+
+                /* Retry the data fault now. */
+                return;
+        }
+
+        /* Now handle the instruction fault. */
+
+        /* Get the fault address. */
+        if (fp->ptregs.format == 0xA)
+                addr = fp->ptregs.pc + 4;
+        else
+                addr = fp->un.fmtb.baddr;
+        if (ssw & FC)
+                addr -= 2;
+
+        if (buserr_type & SUN3_BUSERR_INVALID) {
+                if (!mmu_emu_handle_fault (fp->un.fmtb.daddr, 1, 0))
+                        do_page_fault (&fp->ptregs, addr, 0);
+       } else {
+#ifdef DEBUG
+                printk ("protection fault on insn access (segv).\n");
+#endif
+                force_sig (SIGSEGV, current);
+       }
+}
+#else
+#if defined(CPU_M68020_OR_M68030)
+static inline void bus_error030 (struct frame *fp)
+{
+        volatile unsigned short temp;
+        unsigned short mmusr;
+        unsigned long addr, errorcode;
+        unsigned short ssw = fp->un.fmtb.ssw;
+#ifdef DEBUG
+        unsigned long desc;
+
+        printk ("pid = %x  ", current->pid);
+        printk ("SSW=%#06x  ", ssw);
+
+        if (ssw & (FC | FB))
+                printk ("Instruction fault at %#010lx\n",
+                        ssw & FC ?
+                        fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
+                        :
+                        fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
+        if (ssw & DF)
+                printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n",
+                        ssw & RW ? "read" : "write",
+                        fp->un.fmtb.daddr,
+                        space_names[ssw & DFC], fp->ptregs.pc);
+#endif
+
+        /* ++andreas: If a data fault and an instruction fault happen
+           at the same time map in both pages.  */
+
+        /* First handle the data fault, if any.  */
+        if (ssw & DF) {
+                addr = fp->un.fmtb.daddr;
+
+#ifdef DEBUG
+                asm volatile ("ptestr %3,%2@,#7,%0\n\t"
+                              "pmove %%psr,%1@"
+                              : "=a&" (desc)
+                              : "a" (&temp), "a" (addr), "d" (ssw));
+#else
+                asm volatile ("ptestr %2,%1@,#7\n\t"
+                              "pmove %%psr,%0@"
+                              : : "a" (&temp), "a" (addr), "d" (ssw));
+#endif
+                mmusr = temp;
+
+#ifdef DEBUG
+                printk("mmusr is %#x for addr %#lx in task %p\n",
+                       mmusr, addr, current);
+                printk("descriptor address is %#lx, contents %#lx\n",
+                       __va(desc), *(unsigned long *)__va(desc));
+#endif
+
+                errorcode = (mmusr & MMU_I) ? 0 : 1;
+                if (!(ssw & RW) || (ssw & RM))
+                        errorcode |= 2;
+
+                if (mmusr & (MMU_I | MMU_WP)) {
+                        if (ssw & 4) {
+                                printk("Data %s fault at %#010lx in %s (pc=%#lx)\n",
+                                       ssw & RW ? "read" : "write",
+                                       fp->un.fmtb.daddr,
+                                       space_names[ssw & DFC], fp->ptregs.pc);
+                                goto buserr;
+                        }
+                        /* Don't try to do anything further if an exception was
+                           handled. */
+                        if (do_page_fault (&fp->ptregs, addr, errorcode) < 0)
+                                return;
+                } else if (!(mmusr & MMU_I)) {
+                        /* probably a 020 cas fault */
+                        if (!(ssw & RM) && send_fault_sig(&fp->ptregs) > 0)
+                                printk("unexpected bus error (%#x,%#x)\n", ssw, mmusr);
+                } else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
+                        printk("invalid %s access at %#lx from pc %#lx\n",
+                               !(ssw & RW) ? "write" : "read", addr,
+                               fp->ptregs.pc);
+                        die_if_kernel("Oops",&fp->ptregs,mmusr);
+                        force_sig(SIGSEGV, current);
+                        return;
+                } else {
+#if 0
+                        static volatile long tlong;
+#endif
+
+                        printk("weird %s access at %#lx from pc %#lx (ssw is %#x)\n",
+                               !(ssw & RW) ? "write" : "read", addr,
+                               fp->ptregs.pc, ssw);
+                        asm volatile ("ptestr #1,%1@,#0\n\t"
+                                      "pmove %%psr,%0@"
+                                      : /* no outputs */
+                                      : "a" (&temp), "a" (addr));
+                        mmusr = temp;
+
+                        printk ("level 0 mmusr is %#x\n", mmusr);
+#if 0
+                        asm volatile ("pmove %%tt0,%0@"
+                                      : /* no outputs */
+                                      : "a" (&tlong));
+                        printk("tt0 is %#lx, ", tlong);
+                        asm volatile ("pmove %%tt1,%0@"
+                                      : /* no outputs */
+                                      : "a" (&tlong));
+                        printk("tt1 is %#lx\n", tlong);
+#endif
+#ifdef DEBUG
+                        printk("Unknown SIGSEGV - 1\n");
+#endif
+                        die_if_kernel("Oops",&fp->ptregs,mmusr);
+                        force_sig(SIGSEGV, current);
+                        return;
+                }
+
+                /* setup an ATC entry for the access about to be retried */
+                if (!(ssw & RW) || (ssw & RM))
+                        asm volatile ("ploadw %1,%0@" : /* no outputs */
+                                      : "a" (addr), "d" (ssw));
+                else
+                        asm volatile ("ploadr %1,%0@" : /* no outputs */
+                                      : "a" (addr), "d" (ssw));
+        }
+
+        /* Now handle the instruction fault. */
+
+        if (!(ssw & (FC|FB)))
+                return;
+
+        if (fp->ptregs.sr & PS_S) {
+                printk("Instruction fault at %#010lx\n",
+                        fp->ptregs.pc);
+        buserr:
+                printk ("BAD KERNEL BUSERR\n");
+                die_if_kernel("Oops",&fp->ptregs,0);
+                force_sig(SIGKILL, current);
+                return;
+        }
+
+        /* get the fault address */
+        if (fp->ptregs.format == 10)
+                addr = fp->ptregs.pc + 4;
+        else
+                addr = fp->un.fmtb.baddr;
+        if (ssw & FC)
+                addr -= 2;
+
+        if ((ssw & DF) && ((addr ^ fp->un.fmtb.daddr) & PAGE_MASK) == 0)
+                /* Insn fault on same page as data fault.  But we
+                   should still create the ATC entry.  */
+                goto create_atc_entry;
+
+#ifdef DEBUG
+        asm volatile ("ptestr #1,%2@,#7,%0\n\t"
+                      "pmove %%psr,%1@"
+                      : "=a&" (desc)
+                      : "a" (&temp), "a" (addr));
+#else
+        asm volatile ("ptestr #1,%1@,#7\n\t"
+                      "pmove %%psr,%0@"
+                      : : "a" (&temp), "a" (addr));
+#endif
+        mmusr = temp;
+
+#ifdef DEBUG
+        printk ("mmusr is %#x for addr %#lx in task %p\n",
+                mmusr, addr, current);
+        printk ("descriptor address is %#lx, contents %#lx\n",
+                __va(desc), *(unsigned long *)__va(desc));
+#endif
+
+        if (mmusr & MMU_I)
+                do_page_fault (&fp->ptregs, addr, 0);
+        else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
+                printk ("invalid insn access at %#lx from pc %#lx\n",
+                        addr, fp->ptregs.pc);
+#ifdef DEBUG
+                printk("Unknown SIGSEGV - 2\n");
+#endif
+                die_if_kernel("Oops",&fp->ptregs,mmusr);
+                force_sig(SIGSEGV, current);
+                return;
+        }
+
+create_atc_entry:
+        /* setup an ATC entry for the access about to be retried */
+        asm volatile ("ploadr #2,%0@" : /* no outputs */
+                      : "a" (addr));
+}
+#endif /* CPU_M68020_OR_M68030 */
+#endif /* !CONFIG_SUN3 */
+
+asmlinkage void buserr_c(struct frame *fp)
+{
+        /* Only set esp0 if coming from user mode */
+        if (user_mode(&fp->ptregs))
+                current->thread.esp0 = (unsigned long) fp;
+
+#ifdef DEBUG
+        printk ("*** Bus Error *** Format is %x\n", fp->ptregs.format);
+#endif
+
+        switch (fp->ptregs.format) {
+#if defined (CONFIG_M68060)
+        case 4:                         /* 68060 access error */
+          access_error060 (fp);
+          break;
+#endif
+#if defined (CONFIG_M68040)
+        case 0x7:                       /* 68040 access error */
+          access_error040 (fp);
+          break;
+#endif
+#if defined (CPU_M68020_OR_M68030)
+        case 0xa:
+        case 0xb:
+          bus_error030 (fp);
+          break;
+#endif
+        default:
+          die_if_kernel("bad frame format",&fp->ptregs,0);
+#ifdef DEBUG
+          printk("Unknown SIGSEGV - 4\n");
+#endif
+          force_sig(SIGSEGV, current);
+        }
+}
+
+
+static int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+        unsigned long *endstack;
+        unsigned long addr;
+        int i;
+
+        printk("Call Trace:");
+        addr = (unsigned long)stack + THREAD_SIZE - 1;
+        endstack = (unsigned long *)(addr & -THREAD_SIZE);
+        i = 0;
+        while (stack + 1 <= endstack) {
+                addr = *stack++;
+                /*
+                 * If the address is either in the text segment of the
+                 * kernel, or in the region which contains vmalloc'ed
+                 * memory, it *may* be the address of a calling
+                 * routine; if so, print it so that someone tracing
+                 * down the cause of the crash will be able to figure
+                 * out the call path that was taken.
+                 */
+                if (__kernel_text_address(addr)) {
+#ifndef CONFIG_KALLSYMS
+                        if (i % 5 == 0)
+                                printk("\n       ");
+#endif
+                        printk(" [<%08lx>] %pS\n", addr, (void *)addr);
+                        i++;
+                }
+        }
+        printk("\n");
+}
+
+void show_registers(struct pt_regs *regs)
+{
+        struct frame *fp = (struct frame *)regs;
+        mm_segment_t old_fs = get_fs();
+        u16 c, *cp;
+        unsigned long addr;
+        int i;
+
+        print_modules();
+        printk("PC: [<%08lx>] %pS\n", regs->pc, (void *)regs->pc);
+        printk("SR: %04x  SP: %p  a2: %08lx\n", regs->sr, regs, regs->a2);
+        printk("d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
+               regs->d0, regs->d1, regs->d2, regs->d3);
+        printk("d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
+               regs->d4, regs->d5, regs->a0, regs->a1);
+
+        printk("Process %s (pid: %d, task=%p)\n",
+                current->comm, task_pid_nr(current), current);
+        addr = (unsigned long)&fp->un;
+        printk("Frame format=%X ", regs->format);
+        switch (regs->format) {
+        case 0x2:
+                printk("instr addr=%08lx\n", fp->un.fmt2.iaddr);
+                addr += sizeof(fp->un.fmt2);
+                break;
+        case 0x3:
+                printk("eff addr=%08lx\n", fp->un.fmt3.effaddr);
+                addr += sizeof(fp->un.fmt3);
+                break;
+        case 0x4:
+                printk((CPU_IS_060 ? "fault addr=%08lx fslw=%08lx\n"
+                        : "eff addr=%08lx pc=%08lx\n"),
+                        fp->un.fmt4.effaddr, fp->un.fmt4.pc);
+                addr += sizeof(fp->un.fmt4);
+                break;
+        case 0x7:
+                printk("eff addr=%08lx ssw=%04x faddr=%08lx\n",
+                        fp->un.fmt7.effaddr, fp->un.fmt7.ssw, fp->un.fmt7.faddr);
+                printk("wb 1 stat/addr/data: %04x %08lx %08lx\n",
+                        fp->un.fmt7.wb1s, fp->un.fmt7.wb1a, fp->un.fmt7.wb1dpd0);
+                printk("wb 2 stat/addr/data: %04x %08lx %08lx\n",
+                        fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, fp->un.fmt7.wb2d);
+                printk("wb 3 stat/addr/data: %04x %08lx %08lx\n",
+                        fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, fp->un.fmt7.wb3d);
+                printk("push data: %08lx %08lx %08lx %08lx\n",
+                        fp->un.fmt7.wb1dpd0, fp->un.fmt7.pd1, fp->un.fmt7.pd2,
+                        fp->un.fmt7.pd3);
+                addr += sizeof(fp->un.fmt7);
+                break;
+        case 0x9:
+                printk("instr addr=%08lx\n", fp->un.fmt9.iaddr);
+                addr += sizeof(fp->un.fmt9);
+                break;
+        case 0xa:
+                printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
+                        fp->un.fmta.ssw, fp->un.fmta.isc, fp->un.fmta.isb,
+                        fp->un.fmta.daddr, fp->un.fmta.dobuf);
+                addr += sizeof(fp->un.fmta);
+                break;
+        case 0xb:
+                printk("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
+                        fp->un.fmtb.ssw, fp->un.fmtb.isc, fp->un.fmtb.isb,
+                        fp->un.fmtb.daddr, fp->un.fmtb.dobuf);
+                printk("baddr=%08lx dibuf=%08lx ver=%x\n",
+                        fp->un.fmtb.baddr, fp->un.fmtb.dibuf, fp->un.fmtb.ver);
+                addr += sizeof(fp->un.fmtb);
+                break;
+        default:
+                printk("\n");
+        }
+        show_stack(NULL, (unsigned long *)addr);
+
+        printk("Code:");
+        set_fs(KERNEL_DS);
+        cp = (u16 *)regs->pc;
+        for (i = -8; i < 16; i++) {
+                if (get_user(c, cp + i) && i >= 0) {
+                        printk(" Bad PC value.");
+                        break;
+                }
+                printk(i ? " %04x" : " <%04x>", c);
+        }
+        set_fs(old_fs);
+        printk ("\n");
+}
+
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+        unsigned long *p;
+        unsigned long *endstack;
+        int i;
+
+        if (!stack) {
+                if (task)
+                        stack = (unsigned long *)task->thread.esp0;
+                else
+                        stack = (unsigned long *)&stack;
+        }
+        endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE);
+
+        printk("Stack from %08lx:", (unsigned long)stack);
+        p = stack;
+        for (i = 0; i < kstack_depth_to_print; i++) {
+                if (p + 1 > endstack)
+                        break;
+                if (i % 8 == 0)
+                        printk("\n       ");
+                printk(" %08lx", *p++);
+        }
+        printk("\n");
+        show_trace(stack);
+}
+
+/*
+ * The architecture-independent backtrace generator
+ */
+void dump_stack(void)
+{
+        unsigned long stack;
+
+        show_trace(&stack);
+}
+
+EXPORT_SYMBOL(dump_stack);
+
+void bad_super_trap (struct frame *fp)
+{
+        console_verbose();
+        if (fp->ptregs.vector < 4 * ARRAY_SIZE(vec_names))
+                printk ("*** %s ***   FORMAT=%X\n",
+                        vec_names[(fp->ptregs.vector) >> 2],
+                        fp->ptregs.format);
+        else
+                printk ("*** Exception %d ***   FORMAT=%X\n",
+                        (fp->ptregs.vector) >> 2,
+                        fp->ptregs.format);
+        if (fp->ptregs.vector >> 2 == VEC_ADDRERR && CPU_IS_020_OR_030) {
+                unsigned short ssw = fp->un.fmtb.ssw;
+
+                printk ("SSW=%#06x  ", ssw);
+
+                if (ssw & RC)
+                        printk ("Pipe stage C instruction fault at %#010lx\n",
+                                (fp->ptregs.format) == 0xA ?
+                                fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2);
+                if (ssw & RB)
+                        printk ("Pipe stage B instruction fault at %#010lx\n",
+                                (fp->ptregs.format) == 0xA ?
+                                fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
+                if (ssw & DF)
+                        printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n",
+                                ssw & RW ? "read" : "write",
+                                fp->un.fmtb.daddr, space_names[ssw & DFC],
+                                fp->ptregs.pc);
+        }
+        printk ("Current process id is %d\n", task_pid_nr(current));
+        die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
+}
+
+asmlinkage void trap_c(struct frame *fp)
+{
+        int sig;
+        siginfo_t info;
+
+        if (fp->ptregs.sr & PS_S) {
+                if (fp->ptregs.vector == VEC_TRACE << 2) {
+                        /* traced a trapping instruction on a 68020/30,
+                         * real exception will be executed afterwards.
+                         */
+                } else if (!handle_kernel_fault(&fp->ptregs))
+                        bad_super_trap(fp);
+                return;
+        }
+
+        /* send the appropriate signal to the user program */
+        switch ((fp->ptregs.vector) >> 2) {
+            case VEC_ADDRERR:
+                info.si_code = BUS_ADRALN;
+                sig = SIGBUS;
+                break;
+            case VEC_ILLEGAL:
+            case VEC_LINE10:
+            case VEC_LINE11:
+                info.si_code = ILL_ILLOPC;
+                sig = SIGILL;
+                break;
+            case VEC_PRIV:
+                info.si_code = ILL_PRVOPC;
+                sig = SIGILL;
+                break;
+            case VEC_COPROC:
+                info.si_code = ILL_COPROC;
+                sig = SIGILL;
+                break;
+            case VEC_TRAP1:
+            case VEC_TRAP2:
+            case VEC_TRAP3:
+            case VEC_TRAP4:
+            case VEC_TRAP5:
+            case VEC_TRAP6:
+            case VEC_TRAP7:
+            case VEC_TRAP8:
+            case VEC_TRAP9:
+            case VEC_TRAP10:
+            case VEC_TRAP11:
+            case VEC_TRAP12:
+            case VEC_TRAP13:
+            case VEC_TRAP14:
+                info.si_code = ILL_ILLTRP;
+                sig = SIGILL;
+                break;
+            case VEC_FPBRUC:
+            case VEC_FPOE:
+            case VEC_FPNAN:
+                info.si_code = FPE_FLTINV;
+                sig = SIGFPE;
+                break;
+            case VEC_FPIR:
+                info.si_code = FPE_FLTRES;
+                sig = SIGFPE;
+                break;
+            case VEC_FPDIVZ:
+                info.si_code = FPE_FLTDIV;
+                sig = SIGFPE;
+                break;
+            case VEC_FPUNDER:
+                info.si_code = FPE_FLTUND;
+                sig = SIGFPE;
+                break;
+            case VEC_FPOVER:
+                info.si_code = FPE_FLTOVF;
+                sig = SIGFPE;
+                break;
+            case VEC_ZERODIV:
+                info.si_code = FPE_INTDIV;
+                sig = SIGFPE;
+                break;
+            case VEC_CHK:
+            case VEC_TRAP:
+                info.si_code = FPE_INTOVF;
+                sig = SIGFPE;
+                break;
+            case VEC_TRACE:             /* ptrace single step */
+                info.si_code = TRAP_TRACE;
+                sig = SIGTRAP;
+                break;
+            case VEC_TRAP15:            /* breakpoint */
+                info.si_code = TRAP_BRKPT;
+                sig = SIGTRAP;
+                break;
+            default:
+                info.si_code = ILL_ILLOPC;
+                sig = SIGILL;
+                break;
+        }
+        info.si_signo = sig;
+        info.si_errno = 0;
+        switch (fp->ptregs.format) {
+            default:
+                info.si_addr = (void *) fp->ptregs.pc;
+                break;
+            case 2:
+                info.si_addr = (void *) fp->un.fmt2.iaddr;
+                break;
+            case 7:
+                info.si_addr = (void *) fp->un.fmt7.effaddr;
+                break;
+            case 9:
+                info.si_addr = (void *) fp->un.fmt9.iaddr;
+                break;
+            case 10:
+                info.si_addr = (void *) fp->un.fmta.daddr;
+                break;
+            case 11:
+                info.si_addr = (void *) fp->un.fmtb.daddr;
+                break;
+        }
+        force_sig_info (sig, &info, current);
+}
+
+void die_if_kernel (char *str, struct pt_regs *fp, int nr)
+{
+        if (!(fp->sr & PS_S))
+                return;
+
+        console_verbose();
+        printk("%s: %08x\n",str,nr);
+        show_registers(fp);
+        add_taint(TAINT_DIE);
+        do_exit(SIGSEGV);
+}
+
+/*
+ * This function is called if an error occur while accessing
+ * user-space from the fpsp040 code.
+ */
+asmlinkage void fpsp040_die(void)
+{
+        do_exit(SIGSEGV);
+}
+
+#ifdef CONFIG_M68KFPU_EMU
+asmlinkage void fpemu_signal(int signal, int code, void *addr)
+{
+        siginfo_t info;
+
+        info.si_signo = signal;
+        info.si_errno = 0;
+        info.si_code = code;
+        info.si_addr = addr;
+        force_sig_info(signal, &info, current);
+}
+#endif
diff --git a/arch/m68k/kernel/traps_no.c b/arch/m68k/kernel/traps_no.c
new file mode 100644
index 00000000000..e67b8c80695
--- /dev/null
+++ b/arch/m68k/kernel/traps_no.c
@@ -0,0 +1,361 @@
+/*
+ *  linux/arch/m68knommu/kernel/traps.c
+ *
+ *  Copyright (C) 1993, 1994 by Hamish Macdonald
+ *
+ *  68040 fixes by Michael Rausch
+ *  68040 fixes by Martin Apel
+ *  68060 fixes by Roman Hodek
+ *  68060 fixes by Jesper Skov
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * Sets up all exception vectors
+ */
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/user.h>
+#include <linux/string.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <linux/ptrace.h>
+#include <linux/kallsyms.h>
+
+#include <asm/setup.h>
+#include <asm/fpu.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/traps.h>
+#include <asm/pgtable.h>
+#include <asm/machdep.h>
+#include <asm/siginfo.h>
+
+static char const * const vec_names[] = {
+        "RESET SP", "RESET PC", "BUS ERROR", "ADDRESS ERROR",
+        "ILLEGAL INSTRUCTION", "ZERO DIVIDE", "CHK", "TRAPcc",
+        "PRIVILEGE VIOLATION", "TRACE", "LINE 1010", "LINE 1111",
+        "UNASSIGNED RESERVED 12", "COPROCESSOR PROTOCOL VIOLATION",
+        "FORMAT ERROR", "UNINITIALIZED INTERRUPT",
+        "UNASSIGNED RESERVED 16", "UNASSIGNED RESERVED 17",
+        "UNASSIGNED RESERVED 18", "UNASSIGNED RESERVED 19",
+        "UNASSIGNED RESERVED 20", "UNASSIGNED RESERVED 21",
+        "UNASSIGNED RESERVED 22", "UNASSIGNED RESERVED 23",
+        "SPURIOUS INTERRUPT", "LEVEL 1 INT", "LEVEL 2 INT", "LEVEL 3 INT",
+        "LEVEL 4 INT", "LEVEL 5 INT", "LEVEL 6 INT", "LEVEL 7 INT",
+        "SYSCALL", "TRAP #1", "TRAP #2", "TRAP #3",
+        "TRAP #4", "TRAP #5", "TRAP #6", "TRAP #7",
+        "TRAP #8", "TRAP #9", "TRAP #10", "TRAP #11",
+        "TRAP #12", "TRAP #13", "TRAP #14", "TRAP #15",
+        "FPCP BSUN", "FPCP INEXACT", "FPCP DIV BY 0", "FPCP UNDERFLOW",
+        "FPCP OPERAND ERROR", "FPCP OVERFLOW", "FPCP SNAN",
+        "FPCP UNSUPPORTED OPERATION",
+        "MMU CONFIGURATION ERROR"
+};
+
+void die_if_kernel(char *str, struct pt_regs *fp, int nr)
+{
+        if (!(fp->sr & PS_S))
+                return;
+
+        console_verbose();
+        printk(KERN_EMERG "%s: %08x\n",str,nr);
+        printk(KERN_EMERG "PC: [<%08lx>]\nSR: %04x  SP: %p  a2: %08lx\n",
+               fp->pc, fp->sr, fp, fp->a2);
+        printk(KERN_EMERG "d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
+               fp->d0, fp->d1, fp->d2, fp->d3);
+        printk(KERN_EMERG "d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
+               fp->d4, fp->d5, fp->a0, fp->a1);
+
+        printk(KERN_EMERG "Process %s (pid: %d, stackpage=%08lx)\n",
+                current->comm, current->pid, PAGE_SIZE+(unsigned long)current);
+        show_stack(NULL, (unsigned long *)(fp + 1));
+        add_taint(TAINT_DIE);
+        do_exit(SIGSEGV);
+}
+
+asmlinkage void buserr_c(struct frame *fp)
+{
+        /* Only set esp0 if coming from user mode */
+        if (user_mode(&fp->ptregs))
+                current->thread.esp0 = (unsigned long) fp;
+
+#if defined(DEBUG)
+        printk (KERN_DEBUG "*** Bus Error *** Format is %x\n", fp->ptregs.format);
+#endif
+
+        die_if_kernel("bad frame format",&fp->ptregs,0);
+#if defined(DEBUG)
+        printk(KERN_DEBUG "Unknown SIGSEGV - 4\n");
+#endif
+        force_sig(SIGSEGV, current);
+}
+
+static void print_this_address(unsigned long addr, int i)
+{
+#ifdef CONFIG_KALLSYMS
+        printk(KERN_EMERG " [%08lx] ", addr);
+        print_symbol(KERN_CONT "%s\n", addr);
+#else
+        if (i % 5)
+                printk(KERN_CONT " [%08lx] ", addr);
+        else
+                printk(KERN_EMERG " [%08lx] ", addr);
+        i++;
+#endif
+}
+
+int kstack_depth_to_print = 48;
+
+static void __show_stack(struct task_struct *task, unsigned long *stack)
+{
+        unsigned long *endstack, addr;
+#ifdef CONFIG_FRAME_POINTER
+        unsigned long *last_stack;
+#endif
+        int i;
+
+        if (!stack)
+                stack = (unsigned long *)task->thread.ksp;
+
+        addr = (unsigned long) stack;
+        endstack = (unsigned long *) PAGE_ALIGN(addr);
+
+        printk(KERN_EMERG "Stack from %08lx:", (unsigned long)stack);
+        for (i = 0; i < kstack_depth_to_print; i++) {
+                if (stack + 1 + i > endstack)
+                        break;
+                if (i % 8 == 0)
+                        printk(KERN_EMERG "       ");
+                printk(KERN_CONT " %08lx", *(stack + i));
+        }
+        printk("\n");
+        i = 0;
+
+#ifdef CONFIG_FRAME_POINTER
+        printk(KERN_EMERG "Call Trace:\n");
+
+        last_stack = stack - 1;
+        while (stack <= endstack && stack > last_stack) {
+
+                addr = *(stack + 1);
+                print_this_address(addr, i);
+                i++;
+
+                last_stack = stack;
+                stack = (unsigned long *)*stack;
+        }
+        printk("\n");
+#else
+        printk(KERN_EMERG "Call Trace with CONFIG_FRAME_POINTER disabled:\n");
+        while (stack <= endstack) {
+                addr = *stack++;
+                /*
+                 * If the address is either in the text segment of the kernel,
+                 * or in a region which is occupied by a module then it *may*
+                 * be the address of a calling routine; if so, print it so that
+                 * someone tracing down the cause of the crash will be able to
+                 * figure out the call path that was taken.
+                 */
+                if (__kernel_text_address(addr)) {
+                        print_this_address(addr, i);
+                        i++;
+                }
+        }
+        printk(KERN_CONT "\n");
+#endif
+}
+
+void bad_super_trap(struct frame *fp)
+{
+        int vector = (fp->ptregs.vector >> 2) & 0xff;
+
+        console_verbose();
+        if (vector < ARRAY_SIZE(vec_names))
+                printk (KERN_WARNING "*** %s ***   FORMAT=%X\n",
+                        vec_names[vector],
+                        fp->ptregs.format);
+        else
+                printk (KERN_WARNING "*** Exception %d ***   FORMAT=%X\n",
+                        vector,
+                        fp->ptregs.format);
+        printk (KERN_WARNING "Current process id is %d\n", current->pid);
+        die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
+}
+
+asmlinkage void trap_c(struct frame *fp)
+{
+        int sig;
+        int vector = (fp->ptregs.vector >> 2) & 0xff;
+        siginfo_t info;
+
+        if (fp->ptregs.sr & PS_S) {
+                if (vector == VEC_TRACE) {
+                        /* traced a trapping instruction */
+                } else
+                        bad_super_trap(fp);
+                return;
+        }
+
+        /* send the appropriate signal to the user program */
+        switch (vector) {
+            case VEC_ADDRERR:
+                info.si_code = BUS_ADRALN;
+                sig = SIGBUS;
+                break;
+            case VEC_ILLEGAL:
+            case VEC_LINE10:
+            case VEC_LINE11:
+                info.si_code = ILL_ILLOPC;
+                sig = SIGILL;
+                break;
+            case VEC_PRIV:
+                info.si_code = ILL_PRVOPC;
+                sig = SIGILL;
+                break;
+            case VEC_COPROC:
+                info.si_code = ILL_COPROC;
+                sig = SIGILL;
+                break;
+            case VEC_TRAP1: /* gdbserver breakpoint */
+                fp->ptregs.pc -= 2;
+                info.si_code = TRAP_TRACE;
+                sig = SIGTRAP;
+                break;
+            case VEC_TRAP2:
+            case VEC_TRAP3:
+            case VEC_TRAP4:
+            case VEC_TRAP5:
+            case VEC_TRAP6:
+            case VEC_TRAP7:
+            case VEC_TRAP8:
+            case VEC_TRAP9:
+            case VEC_TRAP10:
+            case VEC_TRAP11:
+            case VEC_TRAP12:
+            case VEC_TRAP13:
+            case VEC_TRAP14:
+                info.si_code = ILL_ILLTRP;
+                sig = SIGILL;
+                break;
+            case VEC_FPBRUC:
+            case VEC_FPOE:
+            case VEC_FPNAN:
+                info.si_code = FPE_FLTINV;
+                sig = SIGFPE;
+                break;
+            case VEC_FPIR:
+                info.si_code = FPE_FLTRES;
+                sig = SIGFPE;
+                break;
+            case VEC_FPDIVZ:
+                info.si_code = FPE_FLTDIV;
+                sig = SIGFPE;
+                break;
+            case VEC_FPUNDER:
+                info.si_code = FPE_FLTUND;
+                sig = SIGFPE;
+                break;
+            case VEC_FPOVER:
+                info.si_code = FPE_FLTOVF;
+                sig = SIGFPE;
+                break;
+            case VEC_ZERODIV:
+                info.si_code = FPE_INTDIV;
+                sig = SIGFPE;
+                break;
+            case VEC_CHK:
+            case VEC_TRAP:
+                info.si_code = FPE_INTOVF;
+                sig = SIGFPE;
+                break;
+            case VEC_TRACE:             /* ptrace single step */
+                info.si_code = TRAP_TRACE;
+                sig = SIGTRAP;
+                break;
+            case VEC_TRAP15:            /* breakpoint */
+                info.si_code = TRAP_BRKPT;
+                sig = SIGTRAP;
+                break;
+            default:
+                info.si_code = ILL_ILLOPC;
+                sig = SIGILL;
+                break;
+        }
+        info.si_signo = sig;
+        info.si_errno = 0;
+        switch (fp->ptregs.format) {
+            default:
+                info.si_addr = (void *) fp->ptregs.pc;
+                break;
+            case 2:
+                info.si_addr = (void *) fp->un.fmt2.iaddr;
+                break;
+            case 7:
+                info.si_addr = (void *) fp->un.fmt7.effaddr;
+                break;
+            case 9:
+                info.si_addr = (void *) fp->un.fmt9.iaddr;
+                break;
+            case 10:
+                info.si_addr = (void *) fp->un.fmta.daddr;
+                break;
+            case 11:
+                info.si_addr = (void *) fp->un.fmtb.daddr;
+                break;
+        }
+        force_sig_info (sig, &info, current);
+}
+
+asmlinkage void set_esp0(unsigned long ssp)
+{
+        current->thread.esp0 = ssp;
+}
+
+/*
+ * The architecture-independent backtrace generator
+ */
+void dump_stack(void)
+{
+        /*
+         * We need frame pointers for this little trick, which works as follows:
+         *
+         * +------------+ 0x00
+         * | Next SP    |       -> 0x0c
+         * +------------+ 0x04
+         * | Caller     |
+         * +------------+ 0x08
+         * | Local vars |       -> our stack var
+         * +------------+ 0x0c
+         * | Next SP    |       -> 0x18, that is what we pass to show_stack()
+         * +------------+ 0x10
+         * | Caller     |
+         * +------------+ 0x14
+         * | Local vars |
+         * +------------+ 0x18
+         * | ...        |
+         * +------------+
+         */
+
+        unsigned long *stack;
+
+        stack = (unsigned long *)&stack;
+        stack++;
+        __show_stack(current, stack);
+}
+EXPORT_SYMBOL(dump_stack);
+
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+        if (!stack && !task)
+                dump_stack();
+        else
+                __show_stack(task, stack);
+}
diff --git a/arch/m68k/kernel/vmlinux.lds_mm.S b/arch/m68k/kernel/vmlinux.lds_mm.S
new file mode 100644
index 00000000000..99ba315bd0a
--- /dev/null
+++ b/arch/m68k/kernel/vmlinux.lds_mm.S
@@ -0,0 +1,10 @@
+PHDRS
+{
+  text PT_LOAD FILEHDR PHDRS FLAGS (7);
+  data PT_LOAD FLAGS (7);
+}
+#ifdef CONFIG_SUN3
+#include "vmlinux-sun3.lds"
+#else
+#include "vmlinux-std.lds"
+#endif
diff --git a/arch/m68k/kernel/vmlinux.lds_no.S b/arch/m68k/kernel/vmlinux.lds_no.S
new file mode 100644
index 00000000000..7dc4087a954
--- /dev/null
+++ b/arch/m68k/kernel/vmlinux.lds_no.S
@@ -0,0 +1,188 @@
+/*
+ *      vmlinux.lds.S -- master linker script for m68knommu arch
+ *
+ *      (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com>
+ *
+ *      This linker script is equipped to build either ROM loaded or RAM
+ *      run kernels.
+ */
+
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/page.h>
+#include <asm/thread_info.h>
+
+#if defined(CONFIG_RAMKERNEL)
+#define RAM_START       CONFIG_KERNELBASE
+#define RAM_LENGTH      (CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE)
+#define TEXT            ram
+#define DATA            ram
+#define INIT            ram
+#define BSSS            ram
+#endif
+#if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL)
+#define RAM_START       CONFIG_RAMBASE
+#define RAM_LENGTH      CONFIG_RAMSIZE
+#define ROMVEC_START    CONFIG_ROMVEC
+#define ROMVEC_LENGTH   CONFIG_ROMVECSIZE
+#define ROM_START       CONFIG_ROMSTART
+#define ROM_LENGTH      CONFIG_ROMSIZE
+#define TEXT            rom
+#define DATA            ram
+#define INIT            ram
+#define BSSS            ram
+#endif
+
+#ifndef DATA_ADDR
+#define DATA_ADDR
+#endif
+
+
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+
+MEMORY {
+        ram     : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+#ifdef ROM_START
+        romvec  : ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH
+        rom     : ORIGIN = ROM_START, LENGTH = ROM_LENGTH
+#endif
+}
+
+jiffies = jiffies_64 + 4;
+
+SECTIONS {
+
+#ifdef ROMVEC_START
+        . = ROMVEC_START ;
+        .romvec : {
+                __rom_start = . ;
+                _romvec = .;
+                *(.data..initvect)
+        } > romvec
+#endif
+
+        .text : {
+                _text = .;
+                _stext = . ;
+                HEAD_TEXT
+                TEXT_TEXT
+                SCHED_TEXT
+                LOCK_TEXT
+                *(.text..lock)
+
+                . = ALIGN(16);          /* Exception table              */
+                __start___ex_table = .;
+                *(__ex_table)
+                __stop___ex_table = .;
+
+                *(.rodata) *(.rodata.*)
+                *(__vermagic)           /* Kernel version magic */
+                *(__markers_strings)
+                *(.rodata1)
+                *(.rodata.str1.1)
+
+                /* Kernel symbol table: Normal symbols */
+                . = ALIGN(4);
+                __start___ksymtab = .;
+                *(SORT(___ksymtab+*))
+                __stop___ksymtab = .;
+
+                /* Kernel symbol table: GPL-only symbols */
+                __start___ksymtab_gpl = .;
+                *(SORT(___ksymtab_gpl+*))
+                __stop___ksymtab_gpl = .;
+
+                /* Kernel symbol table: Normal unused symbols */
+                __start___ksymtab_unused = .;
+                *(SORT(___ksymtab_unused+*))
+                __stop___ksymtab_unused = .;
+
+                /* Kernel symbol table: GPL-only unused symbols */
+                __start___ksymtab_unused_gpl = .;
+                *(SORT(___ksymtab_unused_gpl+*))
+                __stop___ksymtab_unused_gpl = .;
+
+                /* Kernel symbol table: GPL-future symbols */
+                __start___ksymtab_gpl_future = .;
+                *(SORT(___ksymtab_gpl_future+*))
+                __stop___ksymtab_gpl_future = .;
+
+                /* Kernel symbol table: Normal symbols */
+                __start___kcrctab = .;
+                *(SORT(___kcrctab+*))
+                __stop___kcrctab = .;
+
+                /* Kernel symbol table: GPL-only symbols */
+                __start___kcrctab_gpl = .;
+                *(SORT(___kcrctab_gpl+*))
+                __stop___kcrctab_gpl = .;
+
+                /* Kernel symbol table: Normal unused symbols */
+                __start___kcrctab_unused = .;
+                *(SORT(___kcrctab_unused+*))
+                __stop___kcrctab_unused = .;
+
+                /* Kernel symbol table: GPL-only unused symbols */
+                __start___kcrctab_unused_gpl = .;
+                *(SORT(___kcrctab_unused_gpl+*))
+                __stop___kcrctab_unused_gpl = .;
+
+                /* Kernel symbol table: GPL-future symbols */
+                __start___kcrctab_gpl_future = .;
+                *(SORT(___kcrctab_gpl_future+*))
+                __stop___kcrctab_gpl_future = .;
+
+                /* Kernel symbol table: strings */
+                *(__ksymtab_strings)
+
+                /* Built-in module parameters */
+                . = ALIGN(4) ;
+                __start___param = .;
+                *(__param)
+                __stop___param = .;
+
+                /* Built-in module versions */
+                . = ALIGN(4) ;
+                __start___modver = .;
+                *(__modver)
+                __stop___modver = .;
+
+                . = ALIGN(4) ;
+                _etext = . ;
+        } > TEXT
+
+        .data DATA_ADDR : {
+                . = ALIGN(4);
+                _sdata = . ;
+                DATA_DATA
+                CACHELINE_ALIGNED_DATA(32)
+                PAGE_ALIGNED_DATA(PAGE_SIZE)
+                *(.data..shared_aligned)
+                INIT_TASK_DATA(THREAD_SIZE)
+                _edata = . ;
+        } > DATA
+
+        .init.text : {
+                . = ALIGN(PAGE_SIZE);
+                __init_begin = .;
+        } > INIT
+        INIT_TEXT_SECTION(PAGE_SIZE) > INIT
+        INIT_DATA_SECTION(16) > INIT
+        .init.data : {
+                . = ALIGN(PAGE_SIZE);
+                __init_end = .;
+        } > INIT
+
+        .bss : {
+                . = ALIGN(4);
+                _sbss = . ;
+                *(.bss)
+                *(COMMON)
+                . = ALIGN(4) ;
+                _ebss = . ;
+                _end = . ;
+        } > BSSS
+
+        DISCARDS
+}
+
diff --git a/arch/m68k/lib/checksum_mm.c b/arch/m68k/lib/checksum_mm.c
new file mode 100644
index 00000000000..6216f12a756
--- /dev/null
+++ b/arch/m68k/lib/checksum_mm.c
@@ -0,0 +1,425 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the  BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ *              IP/TCP/UDP checksumming routines
+ *
+ * Authors:     Jorge Cwik, <jorge@laser.satlink.net>
+ *              Arnt Gulbrandsen, <agulbra@nvg.unit.no>
+ *              Tom May, <ftom@netcom.com>
+ *              Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
+ *              Lots of code moved from tcp.c and ip.c; see those files
+ *              for more names.
+ *
+ * 03/02/96     Jes Sorensen, Andreas Schwab, Roman Hodek:
+ *              Fixed some nasty bugs, causing some horrible crashes.
+ *              A: At some points, the sum (%0) was used as
+ *              length-counter instead of the length counter
+ *              (%1). Thanks to Roman Hodek for pointing this out.
+ *              B: GCC seems to mess up if one uses too many
+ *              data-registers to hold input values and one tries to
+ *              specify d0 and d1 as scratch registers. Letting gcc
+ *              choose these registers itself solves the problem.
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ *
+ * 1998/8/31    Andreas Schwab:
+ *              Zero out rest of buffer on exception in
+ *              csum_partial_copy_from_user.
+ */
+
+#include <linux/module.h>
+#include <net/checksum.h>
+
+/*
+ * computes a partial checksum, e.g. for TCP/UDP fragments
+ */
+
+__wsum csum_partial(const void *buff, int len, __wsum sum)
+{
+        unsigned long tmp1, tmp2;
+          /*
+           * Experiments with ethernet and slip connections show that buff
+           * is aligned on either a 2-byte or 4-byte boundary.
+           */
+        __asm__("movel %2,%3\n\t"
+                "btst #1,%3\n\t"        /* Check alignment */
+                "jeq 2f\n\t"
+                "subql #2,%1\n\t"       /* buff%4==2: treat first word */
+                "jgt 1f\n\t"
+                "addql #2,%1\n\t"       /* len was == 2, treat only rest */
+                "jra 4f\n"
+             "1:\t"
+                "addw %2@+,%0\n\t"      /* add first word to sum */
+                "clrl %3\n\t"
+                "addxl %3,%0\n"         /* add X bit */
+             "2:\t"
+                /* unrolled loop for the main part: do 8 longs at once */
+                "movel %1,%3\n\t"       /* save len in tmp1 */
+                "lsrl #5,%1\n\t"        /* len/32 */
+                "jeq 2f\n\t"            /* not enough... */
+                "subql #1,%1\n"
+             "1:\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "dbra %1,1b\n\t"
+                "clrl %4\n\t"
+                "addxl %4,%0\n\t"       /* add X bit */
+                "clrw %1\n\t"
+                "subql #1,%1\n\t"
+                "jcc 1b\n"
+             "2:\t"
+                "movel %3,%1\n\t"       /* restore len from tmp1 */
+                "andw #0x1c,%3\n\t"     /* number of rest longs */
+                "jeq 4f\n\t"
+                "lsrw #2,%3\n\t"
+                "subqw #1,%3\n"
+             "3:\t"
+                /* loop for rest longs */
+                "movel %2@+,%4\n\t"
+                "addxl %4,%0\n\t"
+                "dbra %3,3b\n\t"
+                "clrl %4\n\t"
+                "addxl %4,%0\n"         /* add X bit */
+             "4:\t"
+                /* now check for rest bytes that do not fit into longs */
+                "andw #3,%1\n\t"
+                "jeq 7f\n\t"
+                "clrl %4\n\t"           /* clear tmp2 for rest bytes */
+                "subqw #2,%1\n\t"
+                "jlt 5f\n\t"
+                "movew %2@+,%4\n\t"     /* have rest >= 2: get word */
+                "swap %4\n\t"           /* into bits 16..31 */
+                "tstw %1\n\t"           /* another byte? */
+                "jeq 6f\n"
+             "5:\t"
+                "moveb %2@,%4\n\t"      /* have odd rest: get byte */
+                "lslw #8,%4\n\t"        /* into bits 8..15; 16..31 untouched */
+             "6:\t"
+                "addl %4,%0\n\t"        /* now add rest long to sum */
+                "clrl %4\n\t"
+                "addxl %4,%0\n"         /* add X bit */
+             "7:\t"
+                : "=d" (sum), "=d" (len), "=a" (buff),
+                  "=&d" (tmp1), "=&d" (tmp2)
+                : "0" (sum), "1" (len), "2" (buff)
+            );
+        return(sum);
+}
+
+EXPORT_SYMBOL(csum_partial);
+
+
+/*
+ * copy from user space while checksumming, with exception handling.
+ */
+
+__wsum
+csum_partial_copy_from_user(const void __user *src, void *dst,
+                            int len, __wsum sum, int *csum_err)
+{
+        /*
+         * GCC doesn't like more than 10 operands for the asm
+         * statements so we have to use tmp2 for the error
+         * code.
+         */
+        unsigned long tmp1, tmp2;
+
+        __asm__("movel %2,%4\n\t"
+                "btst #1,%4\n\t"        /* Check alignment */
+                "jeq 2f\n\t"
+                "subql #2,%1\n\t"       /* buff%4==2: treat first word */
+                "jgt 1f\n\t"
+                "addql #2,%1\n\t"       /* len was == 2, treat only rest */
+                "jra 4f\n"
+             "1:\n"
+             "10:\t"
+                "movesw %2@+,%4\n\t"    /* add first word to sum */
+                "addw %4,%0\n\t"
+                "movew %4,%3@+\n\t"
+                "clrl %4\n\t"
+                "addxl %4,%0\n"         /* add X bit */
+             "2:\t"
+                /* unrolled loop for the main part: do 8 longs at once */
+                "movel %1,%4\n\t"       /* save len in tmp1 */
+                "lsrl #5,%1\n\t"        /* len/32 */
+                "jeq 2f\n\t"            /* not enough... */
+                "subql #1,%1\n"
+             "1:\n"
+             "11:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "12:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "13:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "14:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "15:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "16:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "17:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+             "18:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "dbra %1,1b\n\t"
+                "clrl %5\n\t"
+                "addxl %5,%0\n\t"       /* add X bit */
+                "clrw %1\n\t"
+                "subql #1,%1\n\t"
+                "jcc 1b\n"
+             "2:\t"
+                "movel %4,%1\n\t"       /* restore len from tmp1 */
+                "andw #0x1c,%4\n\t"     /* number of rest longs */
+                "jeq 4f\n\t"
+                "lsrw #2,%4\n\t"
+                "subqw #1,%4\n"
+             "3:\n"
+                /* loop for rest longs */
+             "19:\t"
+                "movesl %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "dbra %4,3b\n\t"
+                "clrl %5\n\t"
+                "addxl %5,%0\n"         /* add X bit */
+             "4:\t"
+                /* now check for rest bytes that do not fit into longs */
+                "andw #3,%1\n\t"
+                "jeq 7f\n\t"
+                "clrl %5\n\t"           /* clear tmp2 for rest bytes */
+                "subqw #2,%1\n\t"
+                "jlt 5f\n\t"
+             "20:\t"
+                "movesw %2@+,%5\n\t"    /* have rest >= 2: get word */
+                "movew %5,%3@+\n\t"
+                "swap %5\n\t"           /* into bits 16..31 */
+                "tstw %1\n\t"           /* another byte? */
+                "jeq 6f\n"
+             "5:\n"
+             "21:\t"
+                "movesb %2@,%5\n\t"     /* have odd rest: get byte */
+                "moveb %5,%3@+\n\t"
+                "lslw #8,%5\n\t"        /* into bits 8..15; 16..31 untouched */
+             "6:\t"
+                "addl %5,%0\n\t"        /* now add rest long to sum */
+                "clrl %5\n\t"
+                "addxl %5,%0\n\t"       /* add X bit */
+             "7:\t"
+                "clrl %5\n"             /* no error - clear return value */
+             "8:\n"
+                ".section .fixup,\"ax\"\n"
+                ".even\n"
+                /* If any exception occurs zero out the rest.
+                   Similarities with the code above are intentional :-) */
+             "90:\t"
+                "clrw %3@+\n\t"
+                "movel %1,%4\n\t"
+                "lsrl #5,%1\n\t"
+                "jeq 1f\n\t"
+                "subql #1,%1\n"
+             "91:\t"
+                "clrl %3@+\n"
+             "92:\t"
+                "clrl %3@+\n"
+             "93:\t"
+                "clrl %3@+\n"
+             "94:\t"
+                "clrl %3@+\n"
+             "95:\t"
+                "clrl %3@+\n"
+             "96:\t"
+                "clrl %3@+\n"
+             "97:\t"
+                "clrl %3@+\n"
+             "98:\t"
+                "clrl %3@+\n\t"
+                "dbra %1,91b\n\t"
+                "clrw %1\n\t"
+                "subql #1,%1\n\t"
+                "jcc 91b\n"
+             "1:\t"
+                "movel %4,%1\n\t"
+                "andw #0x1c,%4\n\t"
+                "jeq 1f\n\t"
+                "lsrw #2,%4\n\t"
+                "subqw #1,%4\n"
+             "99:\t"
+                "clrl %3@+\n\t"
+                "dbra %4,99b\n\t"
+             "1:\t"
+                "andw #3,%1\n\t"
+                "jeq 9f\n"
+             "100:\t"
+                "clrw %3@+\n\t"
+                "tstw %1\n\t"
+                "jeq 9f\n"
+             "101:\t"
+                "clrb %3@+\n"
+             "9:\t"
+#define STR(X) STR1(X)
+#define STR1(X) #X
+                "moveq #-" STR(EFAULT) ",%5\n\t"
+                "jra 8b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                ".long 10b,90b\n"
+                ".long 11b,91b\n"
+                ".long 12b,92b\n"
+                ".long 13b,93b\n"
+                ".long 14b,94b\n"
+                ".long 15b,95b\n"
+                ".long 16b,96b\n"
+                ".long 17b,97b\n"
+                ".long 18b,98b\n"
+                ".long 19b,99b\n"
+                ".long 20b,100b\n"
+                ".long 21b,101b\n"
+                ".previous"
+                : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst),
+                  "=&d" (tmp1), "=d" (tmp2)
+                : "0" (sum), "1" (len), "2" (src), "3" (dst)
+            );
+
+        *csum_err = tmp2;
+
+        return(sum);
+}
+
+EXPORT_SYMBOL(csum_partial_copy_from_user);
+
+
+/*
+ * copy from kernel space while checksumming, otherwise like csum_partial
+ */
+
+__wsum
+csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
+{
+        unsigned long tmp1, tmp2;
+        __asm__("movel %2,%4\n\t"
+                "btst #1,%4\n\t"        /* Check alignment */
+                "jeq 2f\n\t"
+                "subql #2,%1\n\t"       /* buff%4==2: treat first word */
+                "jgt 1f\n\t"
+                "addql #2,%1\n\t"       /* len was == 2, treat only rest */
+                "jra 4f\n"
+             "1:\t"
+                "movew %2@+,%4\n\t"     /* add first word to sum */
+                "addw %4,%0\n\t"
+                "movew %4,%3@+\n\t"
+                "clrl %4\n\t"
+                "addxl %4,%0\n"         /* add X bit */
+             "2:\t"
+                /* unrolled loop for the main part: do 8 longs at once */
+                "movel %1,%4\n\t"       /* save len in tmp1 */
+                "lsrl #5,%1\n\t"        /* len/32 */
+                "jeq 2f\n\t"            /* not enough... */
+                "subql #1,%1\n"
+             "1:\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "dbra %1,1b\n\t"
+                "clrl %5\n\t"
+                "addxl %5,%0\n\t"       /* add X bit */
+                "clrw %1\n\t"
+                "subql #1,%1\n\t"
+                "jcc 1b\n"
+             "2:\t"
+                "movel %4,%1\n\t"       /* restore len from tmp1 */
+                "andw #0x1c,%4\n\t"     /* number of rest longs */
+                "jeq 4f\n\t"
+                "lsrw #2,%4\n\t"
+                "subqw #1,%4\n"
+             "3:\t"
+                /* loop for rest longs */
+                "movel %2@+,%5\n\t"
+                "addxl %5,%0\n\t"
+                "movel %5,%3@+\n\t"
+                "dbra %4,3b\n\t"
+                "clrl %5\n\t"
+                "addxl %5,%0\n"         /* add X bit */
+             "4:\t"
+                /* now check for rest bytes that do not fit into longs */
+                "andw #3,%1\n\t"
+                "jeq 7f\n\t"
+                "clrl %5\n\t"           /* clear tmp2 for rest bytes */
+                "subqw #2,%1\n\t"
+                "jlt 5f\n\t"
+                "movew %2@+,%5\n\t"     /* have rest >= 2: get word */
+                "movew %5,%3@+\n\t"
+                "swap %5\n\t"           /* into bits 16..31 */
+                "tstw %1\n\t"           /* another byte? */
+                "jeq 6f\n"
+             "5:\t"
+                "moveb %2@,%5\n\t"      /* have odd rest: get byte */
+                "moveb %5,%3@+\n\t"
+                "lslw #8,%5\n"          /* into bits 8..15; 16..31 untouched */
+             "6:\t"
+                "addl %5,%0\n\t"        /* now add rest long to sum */
+                "clrl %5\n\t"
+                "addxl %5,%0\n"         /* add X bit */
+             "7:\t"
+                : "=d" (sum), "=d" (len), "=a" (src), "=a" (dst),
+                  "=&d" (tmp1), "=&d" (tmp2)
+                : "0" (sum), "1" (len), "2" (src), "3" (dst)
+            );
+    return(sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/m68k/lib/checksum_no.c b/arch/m68k/lib/checksum_no.c
new file mode 100644
index 00000000000..e4c6354da76
--- /dev/null
+++ b/arch/m68k/lib/checksum_no.c
@@ -0,0 +1,156 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the  BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ *              IP/TCP/UDP checksumming routines
+ *
+ * Authors:     Jorge Cwik, <jorge@laser.satlink.net>
+ *              Arnt Gulbrandsen, <agulbra@nvg.unit.no>
+ *              Tom May, <ftom@netcom.com>
+ *              Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
+ *              Lots of code moved from tcp.c and ip.c; see those files
+ *              for more names.
+ *
+ * 03/02/96     Jes Sorensen, Andreas Schwab, Roman Hodek:
+ *              Fixed some nasty bugs, causing some horrible crashes.
+ *              A: At some points, the sum (%0) was used as
+ *              length-counter instead of the length counter
+ *              (%1). Thanks to Roman Hodek for pointing this out.
+ *              B: GCC seems to mess up if one uses too many
+ *              data-registers to hold input values and one tries to
+ *              specify d0 and d1 as scratch registers. Letting gcc choose these
+ *      registers itself solves the problem.
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+ 
+/* Revised by Kenneth Albanowski for m68knommu. Basic problem: unaligned access kills, so most
+   of the assembly has to go. */
+
+#include <linux/module.h>
+#include <net/checksum.h>
+
+static inline unsigned short from32to16(unsigned long x)
+{
+        /* add up 16-bit and 16-bit for 16+c bit */
+        x = (x & 0xffff) + (x >> 16);
+        /* add up carry.. */
+        x = (x & 0xffff) + (x >> 16);
+        return x;
+}
+
+static unsigned long do_csum(const unsigned char * buff, int len)
+{
+        int odd, count;
+        unsigned long result = 0;
+
+        if (len <= 0)
+                goto out;
+        odd = 1 & (unsigned long) buff;
+        if (odd) {
+                result = *buff;
+                len--;
+                buff++;
+        }
+        count = len >> 1;               /* nr of 16-bit words.. */
+        if (count) {
+                if (2 & (unsigned long) buff) {
+                        result += *(unsigned short *) buff;
+                        count--;
+                        len -= 2;
+                        buff += 2;
+                }
+                count >>= 1;            /* nr of 32-bit words.. */
+                if (count) {
+                        unsigned long carry = 0;
+                        do {
+                                unsigned long w = *(unsigned long *) buff;
+                                count--;
+                                buff += 4;
+                                result += carry;
+                                result += w;
+                                carry = (w > result);
+                        } while (count);
+                        result += carry;
+                        result = (result & 0xffff) + (result >> 16);
+                }
+                if (len & 2) {
+                        result += *(unsigned short *) buff;
+                        buff += 2;
+                }
+        }
+        if (len & 1)
+                result += (*buff << 8);
+        result = from32to16(result);
+        if (odd)
+                result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
+out:
+        return result;
+}
+
+#ifdef CONFIG_COLDFIRE
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ */
+__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        return (__force __sum16)~do_csum(iph,ihl*4);
+}
+EXPORT_SYMBOL(ip_fast_csum);
+#endif
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+__wsum csum_partial(const void *buff, int len, __wsum sum)
+{
+        unsigned int result = do_csum(buff, len);
+
+        /* add in old sum, and carry.. */
+        result += (__force u32)sum;
+        if ((__force u32)sum > result)
+                result += 1;
+        return (__force __wsum)result;
+}
+
+EXPORT_SYMBOL(csum_partial);
+
+/*
+ * copy from fs while checksumming, otherwise like csum_partial
+ */
+
+__wsum
+csum_partial_copy_from_user(const void __user *src, void *dst,
+                            int len, __wsum sum, int *csum_err)
+{
+        if (csum_err) *csum_err = 0;
+        memcpy(dst, (__force const void *)src, len);
+        return csum_partial(dst, len, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_from_user);
+
+/*
+ * copy from ds while checksumming, otherwise like csum_partial
+ */
+
+__wsum
+csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
+{
+        memcpy(dst, src, len);
+        return csum_partial(dst, len, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/m68k/mm/init_mm.c b/arch/m68k/mm/init_mm.c
new file mode 100644
index 00000000000..bbe525434cc
--- /dev/null
+++ b/arch/m68k/mm/init_mm.c
@@ -0,0 +1,143 @@
+/*
+ *  linux/arch/m68k/mm/init.c
+ *
+ *  Copyright (C) 1995  Hamish Macdonald
+ *
+ *  Contains common initialization routines, specific init code moved
+ *  to motorola.c and sun3mmu.c
+ */
+
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/gfp.h>
+
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/system.h>
+#include <asm/machdep.h>
+#include <asm/io.h>
+#ifdef CONFIG_ATARI
+#include <asm/atari_stram.h>
+#endif
+#include <asm/sections.h>
+#include <asm/tlb.h>
+
+pg_data_t pg_data_map[MAX_NUMNODES];
+EXPORT_SYMBOL(pg_data_map);
+
+int m68k_virt_to_node_shift;
+
+#ifndef CONFIG_SINGLE_MEMORY_CHUNK
+pg_data_t *pg_data_table[65];
+EXPORT_SYMBOL(pg_data_table);
+#endif
+
+void __init m68k_setup_node(int node)
+{
+#ifndef CONFIG_SINGLE_MEMORY_CHUNK
+        struct mem_info *info = m68k_memory + node;
+        int i, end;
+
+        i = (unsigned long)phys_to_virt(info->addr) >> __virt_to_node_shift();
+        end = (unsigned long)phys_to_virt(info->addr + info->size - 1) >> __virt_to_node_shift();
+        for (; i <= end; i++) {
+                if (pg_data_table[i])
+                        printk("overlap at %u for chunk %u\n", i, node);
+                pg_data_table[i] = pg_data_map + node;
+        }
+#endif
+        pg_data_map[node].bdata = bootmem_node_data + node;
+        node_set_online(node);
+}
+
+
+/*
+ * ZERO_PAGE is a special page that is used for zero-initialized
+ * data and COW.
+ */
+
+void *empty_zero_page;
+EXPORT_SYMBOL(empty_zero_page);
+
+extern void init_pointer_table(unsigned long ptable);
+
+/* References to section boundaries */
+
+extern pmd_t *zero_pgtable;
+
+void __init mem_init(void)
+{
+        pg_data_t *pgdat;
+        int codepages = 0;
+        int datapages = 0;
+        int initpages = 0;
+        int i;
+
+        /* this will put all memory onto the freelists */
+        totalram_pages = num_physpages = 0;
+        for_each_online_pgdat(pgdat) {
+                num_physpages += pgdat->node_present_pages;
+
+                totalram_pages += free_all_bootmem_node(pgdat);
+                for (i = 0; i < pgdat->node_spanned_pages; i++) {
+                        struct page *page = pgdat->node_mem_map + i;
+                        char *addr = page_to_virt(page);
+
+                        if (!PageReserved(page))
+                                continue;
+                        if (addr >= _text &&
+                            addr < _etext)
+                                codepages++;
+                        else if (addr >= __init_begin &&
+                                 addr < __init_end)
+                                initpages++;
+                        else
+                                datapages++;
+                }
+        }
+
+#ifndef CONFIG_SUN3
+        /* insert pointer tables allocated so far into the tablelist */
+        init_pointer_table((unsigned long)kernel_pg_dir);
+        for (i = 0; i < PTRS_PER_PGD; i++) {
+                if (pgd_present(kernel_pg_dir[i]))
+                        init_pointer_table(__pgd_page(kernel_pg_dir[i]));
+        }
+
+        /* insert also pointer table that we used to unmap the zero page */
+        if (zero_pgtable)
+                init_pointer_table((unsigned long)zero_pgtable);
+#endif
+
+        printk("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init)\n",
+               nr_free_pages() << (PAGE_SHIFT-10),
+               totalram_pages << (PAGE_SHIFT-10),
+               codepages << (PAGE_SHIFT-10),
+               datapages << (PAGE_SHIFT-10),
+               initpages << (PAGE_SHIFT-10));
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+        int pages = 0;
+        for (; start < end; start += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(start));
+                init_page_count(virt_to_page(start));
+                free_page(start);
+                totalram_pages++;
+                pages++;
+        }
+        printk ("Freeing initrd memory: %dk freed\n", pages);
+}
+#endif
diff --git a/arch/m68k/mm/init_no.c b/arch/m68k/mm/init_no.c
new file mode 100644
index 00000000000..50cd12cf28d
--- /dev/null
+++ b/arch/m68k/mm/init_no.c
@@ -0,0 +1,151 @@
+/*
+ *  linux/arch/m68knommu/mm/init.c
+ *
+ *  Copyright (C) 1998  D. Jeff Dionne <jeff@lineo.ca>,
+ *                      Kenneth Albanowski <kjahds@kjahds.com>,
+ *  Copyright (C) 2000  Lineo, Inc.  (www.lineo.com) 
+ *
+ *  Based on:
+ *
+ *  linux/arch/m68k/mm/init.c
+ *
+ *  Copyright (C) 1995  Hamish Macdonald
+ *
+ *  JAN/1999 -- hacked to support ColdFire (gerg@snapgear.com)
+ *  DEC/2000 -- linux 2.4 support <davidm@snapgear.com>
+ */
+
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/init.h>
+#include <linux/highmem.h>
+#include <linux/pagemap.h>
+#include <linux/bootmem.h>
+#include <linux/gfp.h>
+
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/machdep.h>
+
+/*
+ * ZERO_PAGE is a special page that is used for zero-initialized
+ * data and COW.
+ */
+void *empty_zero_page;
+
+extern unsigned long memory_start;
+extern unsigned long memory_end;
+
+/*
+ * paging_init() continues the virtual memory environment setup which
+ * was begun by the code in arch/head.S.
+ * The parameters are pointers to where to stick the starting and ending
+ * addresses of available kernel virtual memory.
+ */
+void __init paging_init(void)
+{
+        /*
+         * Make sure start_mem is page aligned, otherwise bootmem and
+         * page_alloc get different views of the world.
+         */
+        unsigned long end_mem   = memory_end & PAGE_MASK;
+        unsigned long zones_size[MAX_NR_ZONES] = {0, };
+
+        empty_zero_page = alloc_bootmem_pages(PAGE_SIZE);
+        memset(empty_zero_page, 0, PAGE_SIZE);
+
+        /*
+         * Set up SFC/DFC registers (user data space).
+         */
+        set_fs (USER_DS);
+
+        zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
+        free_area_init(zones_size);
+}
+
+void __init mem_init(void)
+{
+        int codek = 0, datak = 0, initk = 0;
+        unsigned long tmp;
+        extern char _etext, _stext, _sdata, _ebss, __init_begin, __init_end;
+        extern unsigned int _ramend, _rambase;
+        unsigned long len = _ramend - _rambase;
+        unsigned long start_mem = memory_start; /* DAVIDM - these must start at end of kernel */
+        unsigned long end_mem   = memory_end; /* DAVIDM - this must not include kernel stack at top */
+
+        pr_debug("Mem_init: start=%lx, end=%lx\n", start_mem, end_mem);
+
+        end_mem &= PAGE_MASK;
+        high_memory = (void *) end_mem;
+
+        start_mem = PAGE_ALIGN(start_mem);
+        max_mapnr = num_physpages = (((unsigned long) high_memory) - PAGE_OFFSET) >> PAGE_SHIFT;
+
+        /* this will put all memory onto the freelists */
+        totalram_pages = free_all_bootmem();
+
+        codek = (&_etext - &_stext) >> 10;
+        datak = (&_ebss - &_sdata) >> 10;
+        initk = (&__init_begin - &__init_end) >> 10;
+
+        tmp = nr_free_pages() << PAGE_SHIFT;
+        printk(KERN_INFO "Memory available: %luk/%luk RAM, (%dk kernel code, %dk data)\n",
+               tmp >> 10,
+               len >> 10,
+               codek,
+               datak
+               );
+}
+
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+        int pages = 0;
+        for (; start < end; start += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(start));
+                init_page_count(virt_to_page(start));
+                free_page(start);
+                totalram_pages++;
+                pages++;
+        }
+        pr_notice("Freeing initrd memory: %luk freed\n",
+                  pages * (PAGE_SIZE / 1024));
+}
+#endif
+
+void free_initmem(void)
+{
+#ifdef CONFIG_RAMKERNEL
+        unsigned long addr;
+        extern char __init_begin, __init_end;
+        /*
+         * The following code should be cool even if these sections
+         * are not page aligned.
+         */
+        addr = PAGE_ALIGN((unsigned long)(&__init_begin));
+        /* next to check that the page we free is not a partial page */
+        for (; addr + PAGE_SIZE < (unsigned long)(&__init_end); addr +=PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(addr));
+                init_page_count(virt_to_page(addr));
+                free_page(addr);
+                totalram_pages++;
+        }
+        pr_notice("Freeing unused kernel memory: %luk freed (0x%x - 0x%x)\n",
+                        (addr - PAGE_ALIGN((long) &__init_begin)) >> 10,
+                        (int)(PAGE_ALIGN((unsigned long)(&__init_begin))),
+                        (int)(addr - PAGE_SIZE));
+#endif
+}
+
diff --git a/arch/m68k/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile
new file mode 100644
index 00000000000..b5db05625cf
--- /dev/null
+++ b/arch/m68k/platform/5206/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
+
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/5206/config.c
new file mode 100644
index 00000000000..6fa3f800277
--- /dev/null
+++ b/arch/m68k/platform/5206/config.c
@@ -0,0 +1,127 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5206/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com) 
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5206_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 73,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 74,
+        },
+        { },
+};
+
+static struct platform_device m5206_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5206_uart_platform,
+};
+
+static struct platform_device *m5206_devices[] __initdata = {
+        &m5206_uart,
+};
+
+/***************************************************************************/
+
+static void __init m5206_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+                writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
+        } else if (line == 1) {
+                writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+                writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
+        }
+}
+
+static void __init m5206_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5206_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5206_uart_init_line(line, m5206_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m5206_timers_init(void)
+{
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+}
+
+/***************************************************************************/
+
+void m5206_cpu_reset(void)
+{
+        local_irq_disable();
+        /* Set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if defined(CONFIG_NETtel)
+        /* Copy command line from FLASH to local buffer... */
+        memcpy(commandp, (char *) 0xf0004000, size);
+        commandp[size-1] = 0;
+#endif /* CONFIG_NETtel */
+
+        mach_reset = m5206_cpu_reset;
+        m5206_timers_init();
+        m5206_uarts_init();
+
+        /* Only support the external interrupts on their primary level */
+        mcf_mapirq2imr(25, MCFINTC_EINT1);
+        mcf_mapirq2imr(28, MCFINTC_EINT4);
+        mcf_mapirq2imr(31, MCFINTC_EINT7);
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c
new file mode 100644
index 00000000000..b9ab4a120f2
--- /dev/null
+++ b/arch/m68k/platform/5206/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PP",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PADDR,
+                .podr                           = (void __iomem *) MCFSIM_PADAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
new file mode 100644
index 00000000000..ad3f4e5a57c
--- /dev/null
+++ b/arch/m68k/platform/520x/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile for the M5208 specific file.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
new file mode 100644
index 00000000000..621238f1a21
--- /dev/null
+++ b/arch/m68k/platform/520x/config.c
@@ -0,0 +1,311 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/520x/config.c
+ *
+ *  Copyright (C) 2005,      Freescale (www.freescale.com)
+ *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
+ *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
+ *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m520x_uart_platform[] = {
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCFINT_VECBASE + MCFINT_UART1,
+        },
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCFINT_VECBASE + MCFINT_UART2,
+        },
+        { },
+};
+
+static struct platform_device m520x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m520x_uart_platform,
+};
+
+static struct resource m520x_fec_resources[] = {
+        {
+                .start          = MCFFEC_BASE,
+                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 36,
+                .end            = 64 + 36,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 40,
+                .end            = 64 + 40,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 42,
+                .end            = 64 + 42,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m520x_fec = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m520x_fec_resources),
+        .resource               = m520x_fec_resources,
+};
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m520x_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINT_VECBASE + MCFINT_QSPI,
+                .end            = MCFINT_VECBASE + MCFINT_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#define MCFQSPI_CS0    62
+#define MCFQSPI_CS1    63
+#define MCFQSPI_CS2    44
+
+static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        return 0;
+
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, cs_high);
+                break;
+        }
+}
+
+static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, !cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, !cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, !cs_high);
+                break;
+        }
+}
+
+static struct mcfqspi_cs_control m520x_cs_control = {
+        .setup                  = m520x_cs_setup,
+        .teardown               = m520x_cs_teardown,
+        .select                 = m520x_cs_select,
+        .deselect               = m520x_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m520x_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 3,
+        .cs_control             = &m520x_cs_control,
+};
+
+static struct platform_device m520x_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m520x_qspi_resources),
+        .resource               = m520x_qspi_resources,
+        .dev.platform_data      = &m520x_qspi_data,
+};
+
+static void __init m520x_qspi_init(void)
+{
+        u16 par;
+        /* setup Port QS for QSPI with gpio CS control */
+        writeb(0x3f, MCF_GPIO_PAR_QSPI);
+        /* make U1CTS and U2RTS gpio for cs_control */
+        par = readw(MCF_GPIO_PAR_UART);
+        par &= 0x00ff;
+        writew(par, MCF_GPIO_PAR_UART);
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+
+static struct platform_device *m520x_devices[] __initdata = {
+        &m520x_uart,
+        &m520x_fec,
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m520x_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m520x_uart_init_line(int line, int irq)
+{
+        u16 par;
+        u8 par2;
+
+        switch (line) {
+        case 0:
+                par = readw(MCF_GPIO_PAR_UART);
+                par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
+                       MCF_GPIO_PAR_UART_PAR_URXD0;
+                writew(par, MCF_GPIO_PAR_UART);
+                break;
+        case 1:
+                par = readw(MCF_GPIO_PAR_UART);
+                par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
+                       MCF_GPIO_PAR_UART_PAR_URXD1;
+                writew(par, MCF_GPIO_PAR_UART);
+                break;
+        case 2:
+                par2 = readb(MCF_GPIO_PAR_FECI2C);
+                par2 &= ~0x0F;
+                par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
+                        MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
+                writeb(par2, MCF_GPIO_PAR_FECI2C);
+                break;
+        }
+}
+
+static void __init m520x_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m520x_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m520x_uart_init_line(line, m520x_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m520x_fec_init(void)
+{
+        u8 v;
+
+        /* Set multi-function pins to ethernet mode */
+        v = readb(MCF_GPIO_PAR_FEC);
+        writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
+
+        v = readb(MCF_GPIO_PAR_FECI2C);
+        writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
+static void m520x_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m520x_cpu_reset;
+        m520x_uarts_init();
+        m520x_fec_init();
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m520x_qspi_init();
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
new file mode 100644
index 00000000000..d757328563d
--- /dev/null
+++ b/arch/m68k/platform/520x/gpio.c
@@ -0,0 +1,211 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PIRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *) MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BUSCTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 8,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BE",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 16,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BE,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BE,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BE,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "CS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 25,
+                        .ngpio                  = 3,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECI2C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QSPI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMER",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 48,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UART",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 56,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UART,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UART,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UART,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECL,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile
new file mode 100644
index 00000000000..c04b8f71c88
--- /dev/null
+++ b/arch/m68k/platform/523x/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c
new file mode 100644
index 00000000000..71f4436ec80
--- /dev/null
+++ b/arch/m68k/platform/523x/config.c
@@ -0,0 +1,293 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/523x/config.c
+ *
+ *      Sub-architcture dependent initialization code for the Freescale
+ *      523x CPUs.
+ *
+ *      Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m523x_uart_platform[] = {
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 1,
+        },
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 2,
+        },
+        { },
+};
+
+static struct platform_device m523x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m523x_uart_platform,
+};
+
+static struct resource m523x_fec_resources[] = {
+        {
+                .start          = MCFFEC_BASE,
+                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 23,
+                .end            = 64 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 27,
+                .end            = 64 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 29,
+                .end            = 64 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m523x_fec = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m523x_fec_resources),
+        .resource               = m523x_fec_resources,
+};
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m523x_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINT_VECBASE + MCFINT_QSPI,
+                .end            = MCFINT_VECBASE + MCFINT_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#define MCFQSPI_CS0    91
+#define MCFQSPI_CS1    92
+#define MCFQSPI_CS2    103
+#define MCFQSPI_CS3    99
+
+static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
+                goto fail3;
+        }
+        status = gpio_direction_output(MCFQSPI_CS3, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
+                goto fail4;
+        }
+
+        return 0;
+
+fail4:
+        gpio_free(MCFQSPI_CS3);
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS3);
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m523x_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, cs_high);
+                break;
+        }
+}
+
+static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, !cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, !cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, !cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, !cs_high);
+                break;
+        }
+}
+
+static struct mcfqspi_cs_control m523x_cs_control = {
+        .setup                  = m523x_cs_setup,
+        .teardown               = m523x_cs_teardown,
+        .select                 = m523x_cs_select,
+        .deselect               = m523x_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m523x_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 4,
+        .cs_control             = &m523x_cs_control,
+};
+
+static struct platform_device m523x_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m523x_qspi_resources),
+        .resource               = m523x_qspi_resources,
+        .dev.platform_data      = &m523x_qspi_data,
+};
+
+static void __init m523x_qspi_init(void)
+{
+        u16 par;
+
+        /* setup QSPS pins for QSPI with gpio CS control */
+        writeb(0x1f, MCFGPIO_PAR_QSPI);
+        /* and CS2 & CS3 as gpio */
+        par = readw(MCFGPIO_PAR_TIMER);
+        par &= 0x3f3f;
+        writew(par, MCFGPIO_PAR_TIMER);
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+static struct platform_device *m523x_devices[] __initdata = {
+        &m523x_uart,
+        &m523x_fec,
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m523x_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m523x_fec_init(void)
+{
+        u16 par;
+        u8 v;
+
+        /* Set multi-function pins to ethernet use */
+        par = readw(MCF_IPSBAR + 0x100082);
+        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
+        v = readb(MCF_IPSBAR + 0x100078);
+        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+}
+
+/***************************************************************************/
+
+static void m523x_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m523x_cpu_reset;
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        m523x_fec_init();
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m523x_qspi_init();
+#endif
+        platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c
new file mode 100644
index 00000000000..327ebf142c8
--- /dev/null
+++ b/arch/m68k/platform/523x/gpio.c
@@ -0,0 +1,284 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PIRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 1,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *) MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "ADDR",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 13,
+                        .ngpio                  = 3,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "DATAH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 16,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "DATAL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 24,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BUSCTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "CS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 49,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "SDRAM",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 56,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECI2C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 2,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 80,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QSPI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 88,
+                        .ngpio                  = 5,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMER",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 96,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "ETPU",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 104,
+                        .ngpio                  = 3,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ETPU,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_ETPU,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ETPU,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile
new file mode 100644
index 00000000000..4bed30fd007
--- /dev/null
+++ b/arch/m68k/platform/5249/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o intc2.o
+
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c
new file mode 100644
index 00000000000..ceb31e5744a
--- /dev/null
+++ b/arch/m68k/platform/5249/config.c
@@ -0,0 +1,330 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5249/config.c
+ *
+ *      Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5249_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 73,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 74,
+        },
+        { },
+};
+
+static struct platform_device m5249_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5249_uart_platform,
+};
+
+#ifdef CONFIG_M5249C3
+
+static struct resource m5249_smc91x_resources[] = {
+        {
+                .start          = 0xe0000300,
+                .end            = 0xe0000300 + 0x100,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINTC2_GPIOIRQ6,
+                .end            = MCFINTC2_GPIOIRQ6,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m5249_smc91x = {
+        .name                   = "smc91x",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m5249_smc91x_resources),
+        .resource               = m5249_smc91x_resources,
+};
+
+#endif /* CONFIG_M5249C3 */
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m5249_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_QSPI,
+                .end            = MCF_IRQ_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#define MCFQSPI_CS0    29
+#define MCFQSPI_CS1    24
+#define MCFQSPI_CS2    21
+#define MCFQSPI_CS3    22
+
+static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
+                goto fail3;
+        }
+        status = gpio_direction_output(MCFQSPI_CS3, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
+                goto fail4;
+        }
+
+        return 0;
+
+fail4:
+        gpio_free(MCFQSPI_CS3);
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS3);
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, cs_high);
+                break;
+        }
+}
+
+static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, !cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, !cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, !cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, !cs_high);
+                break;
+        }
+}
+
+static struct mcfqspi_cs_control m5249_cs_control = {
+        .setup                  = m5249_cs_setup,
+        .teardown               = m5249_cs_teardown,
+        .select                 = m5249_cs_select,
+        .deselect               = m5249_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m5249_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 4,
+        .cs_control             = &m5249_cs_control,
+};
+
+static struct platform_device m5249_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m5249_qspi_resources),
+        .resource               = m5249_qspi_resources,
+        .dev.platform_data      = &m5249_qspi_data,
+};
+
+static void __init m5249_qspi_init(void)
+{
+        /* QSPI irq setup */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
+               MCF_MBAR + MCFSIM_QSPIICR);
+        mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+
+static struct platform_device *m5249_devices[] __initdata = {
+        &m5249_uart,
+#ifdef CONFIG_M5249C3
+        &m5249_smc91x,
+#endif
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m5249_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m5249_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
+        } else if (line == 1) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
+        }
+}
+
+static void __init m5249_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5249_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5249_uart_init_line(line, m5249_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+#ifdef CONFIG_M5249C3
+
+static void __init m5249_smc91x_init(void)
+{
+        u32  gpio;
+
+        /* Set the GPIO line as interrupt source for smc91x device */
+        gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+
+        gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
+        writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
+}
+
+#endif /* CONFIG_M5249C3 */
+
+/***************************************************************************/
+
+static void __init m5249_timers_init(void)
+{
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+}
+
+/***************************************************************************/
+
+void m5249_cpu_reset(void)
+{
+        local_irq_disable();
+        /* Set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m5249_cpu_reset;
+        m5249_timers_init();
+        m5249_uarts_init();
+#ifdef CONFIG_M5249C3
+        m5249_smc91x_init();
+#endif
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m5249_qspi_init();
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c
new file mode 100644
index 00000000000..2b56c6ef65b
--- /dev/null
+++ b/arch/m68k/platform/5249/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "GPIO0",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 32,
+                },
+                .pddr                           = (void __iomem *) MCFSIM2_GPIOENABLE,
+                .podr                           = (void __iomem *) MCFSIM2_GPIOWRITE,
+                .ppdr                           = (void __iomem *) MCFSIM2_GPIOREAD,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "GPIO1",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 32,
+                        .ngpio                  = 32,
+                },
+                .pddr                           = (void __iomem *) MCFSIM2_GPIO1ENABLE,
+                .podr                           = (void __iomem *) MCFSIM2_GPIO1WRITE,
+                .ppdr                           = (void __iomem *) MCFSIM2_GPIO1READ,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c
new file mode 100644
index 00000000000..f343bf7bf5b
--- /dev/null
+++ b/arch/m68k/platform/5249/intc2.c
@@ -0,0 +1,61 @@
+/*
+ * intc2.c  -- support for the 2nd INTC controller of the 5249
+ *
+ * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+static void intc2_irq_gpio_mask(struct irq_data *d)
+{
+        u32 imr;
+        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
+        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+}
+
+static void intc2_irq_gpio_unmask(struct irq_data *d)
+{
+        u32 imr;
+        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
+        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+}
+
+static void intc2_irq_gpio_ack(struct irq_data *d)
+{
+        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
+}
+
+static struct irq_chip intc2_irq_gpio_chip = {
+        .name           = "CF-INTC2",
+        .irq_mask       = intc2_irq_gpio_mask,
+        .irq_unmask     = intc2_irq_gpio_unmask,
+        .irq_ack        = intc2_irq_gpio_ack,
+};
+
+static int __init mcf_intc2_init(void)
+{
+        int irq;
+
+        /* GPIO interrupt sources */
+        for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
+                irq_set_chip(irq, &intc2_irq_gpio_chip);
+                irq_set_handler(irq, handle_edge_irq);
+        }
+
+        return 0;
+}
+
+arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile
new file mode 100644
index 00000000000..34110fc1430
--- /dev/null
+++ b/arch/m68k/platform/5272/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o intc.o
+
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/5272/config.c
new file mode 100644
index 00000000000..65bb582734e
--- /dev/null
+++ b/arch/m68k/platform/5272/config.c
@@ -0,0 +1,176 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5272/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+/*
+ *      Some platforms need software versions of the GPIO data registers.
+ */
+unsigned short ppdata;
+unsigned char ledbank = 0xff;
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5272_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = MCF_IRQ_UART1,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = MCF_IRQ_UART2,
+        },
+        { },
+};
+
+static struct platform_device m5272_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5272_uart_platform,
+};
+
+static struct resource m5272_fec_resources[] = {
+        {
+                .start          = MCF_MBAR + 0x840,
+                .end            = MCF_MBAR + 0x840 + 0x1cf,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_ERX,
+                .end            = MCF_IRQ_ERX,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_ETX,
+                .end            = MCF_IRQ_ETX,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_ENTC,
+                .end            = MCF_IRQ_ENTC,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m5272_fec = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m5272_fec_resources),
+        .resource               = m5272_fec_resources,
+};
+
+static struct platform_device *m5272_devices[] __initdata = {
+        &m5272_uart,
+        &m5272_fec,
+};
+
+/***************************************************************************/
+
+static void __init m5272_uart_init_line(int line, int irq)
+{
+        u32 v;
+
+        if ((line >= 0) && (line < 2)) {
+                /* Enable the output lines for the serial ports */
+                v = readl(MCF_MBAR + MCFSIM_PBCNT);
+                v = (v & ~0x000000ff) | 0x00000055;
+                writel(v, MCF_MBAR + MCFSIM_PBCNT);
+
+                v = readl(MCF_MBAR + MCFSIM_PDCNT);
+                v = (v & ~0x000003fc) | 0x000002a8;
+                writel(v, MCF_MBAR + MCFSIM_PDCNT);
+        }
+}
+
+static void __init m5272_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5272_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5272_uart_init_line(line, m5272_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void m5272_cpu_reset(void)
+{
+        local_irq_disable();
+        /* Set watchdog to reset, and enabled */
+        __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
+        __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
+        __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if defined (CONFIG_MOD5272)
+        volatile unsigned char  *pivrp;
+
+        /* Set base of device vectors to be 64 */
+        pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
+        *pivrp = 0x40;
+#endif
+
+#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
+        /* Copy command line from FLASH to local buffer... */
+        memcpy(commandp, (char *) 0xf0004000, size);
+        commandp[size-1] = 0;
+#elif defined(CONFIG_CANCam)
+        /* Copy command line from FLASH to local buffer... */
+        memcpy(commandp, (char *) 0xf0010000, size);
+        commandp[size-1] = 0;
+#endif
+
+        mach_reset = m5272_cpu_reset;
+}
+
+/***************************************************************************/
+
+/*
+ * Some 5272 based boards have the FEC ethernet diectly connected to
+ * an ethernet switch. In this case we need to use the fixed phy type,
+ * and we need to declare it early in boot.
+ */
+static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
+        .link   = 1,
+        .speed  = 100,
+        .duplex = 0,
+};
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        m5272_uarts_init();
+        fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
+        platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c
new file mode 100644
index 00000000000..57ac10a5d7f
--- /dev/null
+++ b/arch/m68k/platform/5272/gpio.c
@@ -0,0 +1,81 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PA",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PADDR,
+                .podr                           = (void __iomem *) MCFSIM_PADAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "PB",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 16,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PBDDR,
+                .podr                           = (void __iomem *) MCFSIM_PBDAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PBDAT,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "PC",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 32,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PCDDR,
+                .podr                           = (void __iomem *) MCFSIM_PCDAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PCDAT,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c
new file mode 100644
index 00000000000..7160e618b0a
--- /dev/null
+++ b/arch/m68k/platform/5272/intc.c
@@ -0,0 +1,185 @@
+/*
+ * intc.c  --  interrupt controller or ColdFire 5272 SoC
+ *
+ * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/traps.h>
+
+/*
+ * The 5272 ColdFire interrupt controller is nothing like any other
+ * ColdFire interrupt controller - it truly is completely different.
+ * Given its age it is unlikely to be used on any other ColdFire CPU.
+ */
+
+/*
+ * The masking and priproty setting of interrupts on the 5272 is done
+ * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
+ * loose mapping of vector number to register and internal bits, but
+ * a table is the easiest and quickest way to map them.
+ *
+ * Note that the external interrupts are edge triggered (unlike the
+ * internal interrupt sources which are level triggered). Which means
+ * they also need acknowledging via acknowledge bits.
+ */
+struct irqmap {
+        unsigned char   icr;
+        unsigned char   index;
+        unsigned char   ack;
+};
+
+static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
+        /*MCF_IRQ_SPURIOUS*/    { .icr = 0,           .index = 0,  .ack = 0, },
+        /*MCF_IRQ_EINT1*/       { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
+        /*MCF_IRQ_EINT2*/       { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
+        /*MCF_IRQ_EINT3*/       { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
+        /*MCF_IRQ_EINT4*/       { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
+        /*MCF_IRQ_TIMER1*/      { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
+        /*MCF_IRQ_TIMER2*/      { .icr = MCFSIM_ICR1, .index = 8,  .ack = 0, },
+        /*MCF_IRQ_TIMER3*/      { .icr = MCFSIM_ICR1, .index = 4,  .ack = 0, },
+        /*MCF_IRQ_TIMER4*/      { .icr = MCFSIM_ICR1, .index = 0,  .ack = 0, },
+        /*MCF_IRQ_UART1*/       { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
+        /*MCF_IRQ_UART2*/       { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
+        /*MCF_IRQ_PLIP*/        { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
+        /*MCF_IRQ_PLIA*/        { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
+        /*MCF_IRQ_USB0*/        { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
+        /*MCF_IRQ_USB1*/        { .icr = MCFSIM_ICR2, .index = 8,  .ack = 0, },
+        /*MCF_IRQ_USB2*/        { .icr = MCFSIM_ICR2, .index = 4,  .ack = 0, },
+        /*MCF_IRQ_USB3*/        { .icr = MCFSIM_ICR2, .index = 0,  .ack = 0, },
+        /*MCF_IRQ_USB4*/        { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
+        /*MCF_IRQ_USB5*/        { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
+        /*MCF_IRQ_USB6*/        { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
+        /*MCF_IRQ_USB7*/        { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
+        /*MCF_IRQ_DMA*/         { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
+        /*MCF_IRQ_ERX*/         { .icr = MCFSIM_ICR3, .index = 8,  .ack = 0, },
+        /*MCF_IRQ_ETX*/         { .icr = MCFSIM_ICR3, .index = 4,  .ack = 0, },
+        /*MCF_IRQ_ENTC*/        { .icr = MCFSIM_ICR3, .index = 0,  .ack = 0, },
+        /*MCF_IRQ_QSPI*/        { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
+        /*MCF_IRQ_EINT5*/       { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
+        /*MCF_IRQ_EINT6*/       { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
+        /*MCF_IRQ_SWTO*/        { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
+};
+
+/*
+ * The act of masking the interrupt also has a side effect of 'ack'ing
+ * an interrupt on this irq (for the external irqs). So this mask function
+ * is also an ack_mask function.
+ */
+static void intc_irq_mask(struct irq_data *d)
+{
+        unsigned int irq = d->irq;
+
+        if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+                u32 v;
+                irq -= MCFINT_VECBASE;
+                v = 0x8 << intc_irqmap[irq].index;
+                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+        }
+}
+
+static void intc_irq_unmask(struct irq_data *d)
+{
+        unsigned int irq = d->irq;
+
+        if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+                u32 v;
+                irq -= MCFINT_VECBASE;
+                v = 0xd << intc_irqmap[irq].index;
+                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+        }
+}
+
+static void intc_irq_ack(struct irq_data *d)
+{
+        unsigned int irq = d->irq;
+
+        /* Only external interrupts are acked */
+        if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+                irq -= MCFINT_VECBASE;
+                if (intc_irqmap[irq].ack) {
+                        u32 v;
+                        v = readl(MCF_MBAR + intc_irqmap[irq].icr);
+                        v &= (0x7 << intc_irqmap[irq].index);
+                        v |= (0x8 << intc_irqmap[irq].index);
+                        writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                }
+        }
+}
+
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        unsigned int irq = d->irq;
+
+        if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
+                irq -= MCFINT_VECBASE;
+                if (intc_irqmap[irq].ack) {
+                        u32 v;
+                        v = readl(MCF_MBAR + MCFSIM_PITR);
+                        if (type == IRQ_TYPE_EDGE_FALLING)
+                                v &= ~(0x1 << (32 - irq));
+                        else
+                                v |= (0x1 << (32 - irq));
+                        writel(v, MCF_MBAR + MCFSIM_PITR);
+                }
+        }
+        return 0;
+}
+
+/*
+ * Simple flow handler to deal with the external edge triggered interrupts.
+ * We need to be careful with the masking/acking due to the side effects
+ * of masking an interrupt.
+ */
+static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
+{
+        irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
+        handle_simple_irq(irq, desc);
+}
+
+static struct irq_chip intc_irq_chip = {
+        .name           = "CF-INTC",
+        .irq_mask       = intc_irq_mask,
+        .irq_unmask     = intc_irq_unmask,
+        .irq_mask_ack   = intc_irq_mask,
+        .irq_ack        = intc_irq_ack,
+        .irq_set_type   = intc_irq_set_type,
+};
+
+void __init init_IRQ(void)
+{
+        int irq, edge;
+
+        /* Mask all interrupt sources */
+        writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
+        writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
+        writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
+        writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
+
+        for (irq = 0; (irq < NR_IRQS); irq++) {
+                irq_set_chip(irq, &intc_irq_chip);
+                edge = 0;
+                if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
+                        edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
+                if (edge) {
+                        irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
+                        irq_set_handler(irq, intc_external_irq);
+                } else {
+                        irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+                        irq_set_handler(irq, handle_level_irq);
+                }
+        }
+}
+
diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile
new file mode 100644
index 00000000000..6ac4b57370e
--- /dev/null
+++ b/arch/m68k/platform/527x/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
+
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
new file mode 100644
index 00000000000..3ebc769cefd
--- /dev/null
+++ b/arch/m68k/platform/527x/config.c
@@ -0,0 +1,384 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/527x/config.c
+ *
+ *      Sub-architcture dependent initialization code for the Freescale
+ *      5270/5271 CPUs.
+ *
+ *      Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m527x_uart_platform[] = {
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCFINT_VECBASE + MCFINT_UART1,
+        },
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCFINT_VECBASE + MCFINT_UART2,
+        },
+        { },
+};
+
+static struct platform_device m527x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m527x_uart_platform,
+};
+
+static struct resource m527x_fec0_resources[] = {
+        {
+                .start          = MCFFEC_BASE0,
+                .end            = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 23,
+                .end            = 64 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 27,
+                .end            = 64 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 29,
+                .end            = 64 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource m527x_fec1_resources[] = {
+        {
+                .start          = MCFFEC_BASE1,
+                .end            = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 128 + 23,
+                .end            = 128 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 128 + 27,
+                .end            = 128 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 128 + 29,
+                .end            = 128 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m527x_fec[] = {
+        {
+                .name           = "fec",
+                .id             = 0,
+                .num_resources  = ARRAY_SIZE(m527x_fec0_resources),
+                .resource       = m527x_fec0_resources,
+        },
+        {
+                .name           = "fec",
+                .id             = 1,
+                .num_resources  = ARRAY_SIZE(m527x_fec1_resources),
+                .resource       = m527x_fec1_resources,
+        },
+};
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m527x_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINT_VECBASE + MCFINT_QSPI,
+                .end            = MCFINT_VECBASE + MCFINT_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#if defined(CONFIG_M5271)
+#define MCFQSPI_CS0    91
+#define MCFQSPI_CS1    92
+#define MCFQSPI_CS2    99
+#define MCFQSPI_CS3    103
+#elif defined(CONFIG_M5275)
+#define MCFQSPI_CS0    59
+#define MCFQSPI_CS1    60
+#define MCFQSPI_CS2    61
+#define MCFQSPI_CS3    62
+#endif
+
+static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
+                goto fail3;
+        }
+        status = gpio_direction_output(MCFQSPI_CS3, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
+                goto fail4;
+        }
+
+        return 0;
+
+fail4:
+        gpio_free(MCFQSPI_CS3);
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS3);
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, cs_high);
+                break;
+        }
+}
+
+static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, !cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, !cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, !cs_high);
+                break;
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, !cs_high);
+                break;
+        }
+}
+
+static struct mcfqspi_cs_control m527x_cs_control = {
+        .setup                  = m527x_cs_setup,
+        .teardown               = m527x_cs_teardown,
+        .select                 = m527x_cs_select,
+        .deselect               = m527x_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m527x_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 4,
+        .cs_control             = &m527x_cs_control,
+};
+
+static struct platform_device m527x_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m527x_qspi_resources),
+        .resource               = m527x_qspi_resources,
+        .dev.platform_data      = &m527x_qspi_data,
+};
+
+static void __init m527x_qspi_init(void)
+{
+#if defined(CONFIG_M5271)
+        u16 par;
+
+        /* setup QSPS pins for QSPI with gpio CS control */
+        writeb(0x1f, MCFGPIO_PAR_QSPI);
+        /* and CS2 & CS3 as gpio */
+        par = readw(MCFGPIO_PAR_TIMER);
+        par &= 0x3f3f;
+        writew(par, MCFGPIO_PAR_TIMER);
+#elif defined(CONFIG_M5275)
+        /* setup QSPS pins for QSPI with gpio CS control */
+        writew(0x003e, MCFGPIO_PAR_QSPI);
+#endif
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+static struct platform_device *m527x_devices[] __initdata = {
+        &m527x_uart,
+        &m527x_fec[0],
+#ifdef CONFIG_FEC2
+        &m527x_fec[1],
+#endif
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m527x_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m527x_uart_init_line(int line, int irq)
+{
+        u16 sepmask;
+
+        if ((line < 0) || (line > 2))
+                return;
+
+        /*
+         * External Pin Mask Setting & Enable External Pin for Interface
+         */
+        sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        if (line == 0)
+                sepmask |= UART0_ENABLE_MASK;
+        else if (line == 1)
+                sepmask |= UART1_ENABLE_MASK;
+        else if (line == 2)
+                sepmask |= UART2_ENABLE_MASK;
+        writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+}
+
+static void __init m527x_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m527x_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m527x_uart_init_line(line, m527x_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m527x_fec_init(void)
+{
+        u16 par;
+        u8 v;
+
+        /* Set multi-function pins to ethernet mode for fec0 */
+#if defined(CONFIG_M5271)
+        v = readb(MCF_IPSBAR + 0x100047);
+        writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+#else
+        par = readw(MCF_IPSBAR + 0x100082);
+        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
+        v = readb(MCF_IPSBAR + 0x100078);
+        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+#endif
+
+#ifdef CONFIG_FEC2
+        /* Set multi-function pins to ethernet mode for fec1 */
+        par = readw(MCF_IPSBAR + 0x100082);
+        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
+        v = readb(MCF_IPSBAR + 0x100079);
+        writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+#endif
+}
+
+/***************************************************************************/
+
+static void m527x_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m527x_cpu_reset;
+        m527x_uarts_init();
+        m527x_fec_init();
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m527x_qspi_init();
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c
new file mode 100644
index 00000000000..205da0aa0f2
--- /dev/null
+++ b/arch/m68k/platform/527x/gpio.c
@@ -0,0 +1,609 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+#if defined(CONFIG_M5271)
+        {
+                .gpio_chip                      = {
+                        .label                  = "PIRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 1,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *) MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "ADDR",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 13,
+                        .ngpio                  = 3,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "DATAH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 16,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "DATAL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 24,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BUSCTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "CS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 49,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "SDRAM",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 56,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECI2C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 2,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 80,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QSPI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 88,
+                        .ngpio                  = 5,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMER",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 96,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
+        },
+#elif defined(CONFIG_M5275)
+        {
+                .gpio_chip                      = {
+                        .label                  = "PIRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 1,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *) MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BUSCTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 8,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "ADDR",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 21,
+                        .ngpio                  = 3,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "CS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 25,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FEC0H",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC0H,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC0H,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FEC0L",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC0L,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC0L,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECI2C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 48,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QSPI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 56,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "SDRAM",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMERH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMERH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMERH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMERL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 80,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMERL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMERL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 88,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FEC1H",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 96,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC1H,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC1H,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FEC1L",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 104,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC1L,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC1L,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 114,
+                        .ngpio                  = 2,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "IRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 121,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_IRQ,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_IRQ,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_IRQ,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "USBH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 128,
+                        .ngpio                  = 1,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_USBH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_USBH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_USBH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_USBH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_USBH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "USBL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 136,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_USBL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_USBL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_USBL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_USBL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_USBL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UARTH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 144,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
+        },
+#endif
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile
new file mode 100644
index 00000000000..6ac4b57370e
--- /dev/null
+++ b/arch/m68k/platform/528x/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs.  You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
+
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c
new file mode 100644
index 00000000000..7abe77a2f3e
--- /dev/null
+++ b/arch/m68k/platform/528x/config.c
@@ -0,0 +1,320 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/528x/config.c
+ *
+ *      Sub-architcture dependent initialization code for the Freescale
+ *      5280, 5281 and 5282 CPUs.
+ *
+ *      Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m528x_uart_platform[] = {
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 1,
+        },
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 2,
+        },
+        { },
+};
+
+static struct platform_device m528x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m528x_uart_platform,
+};
+
+static struct resource m528x_fec_resources[] = {
+        {
+                .start          = MCFFEC_BASE,
+                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 23,
+                .end            = 64 + 23,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 27,
+                .end            = 64 + 27,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 29,
+                .end            = 64 + 29,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m528x_fec = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m528x_fec_resources),
+        .resource               = m528x_fec_resources,
+};
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m528x_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINT_VECBASE + MCFINT_QSPI,
+                .end            = MCFINT_VECBASE + MCFINT_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#define MCFQSPI_CS0    147
+#define MCFQSPI_CS1    148
+#define MCFQSPI_CS2    149
+#define MCFQSPI_CS3    150
+
+static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
+                goto fail3;
+        }
+        status = gpio_direction_output(MCFQSPI_CS3, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
+                goto fail4;
+        }
+
+        return 0;
+
+fail4:
+        gpio_free(MCFQSPI_CS3);
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS3);
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
+}
+
+static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
+}
+
+static struct mcfqspi_cs_control m528x_cs_control = {
+        .setup                  = m528x_cs_setup,
+        .teardown               = m528x_cs_teardown,
+        .select                 = m528x_cs_select,
+        .deselect               = m528x_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m528x_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 4,
+        .cs_control             = &m528x_cs_control,
+};
+
+static struct platform_device m528x_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m528x_qspi_resources),
+        .resource               = m528x_qspi_resources,
+        .dev.platform_data      = &m528x_qspi_data,
+};
+
+static void __init m528x_qspi_init(void)
+{
+        /* setup Port QS for QSPI with gpio CS control */
+        __raw_writeb(0x07, MCFGPIO_PQSPAR);
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+static struct platform_device *m528x_devices[] __initdata = {
+        &m528x_uart,
+        &m528x_fec,
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m528x_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m528x_uart_init_line(int line, int irq)
+{
+        u8 port;
+
+        if ((line < 0) || (line > 2))
+                return;
+
+        /* make sure PUAPAR is set for UART0 and UART1 */
+        if (line < 2) {
+                port = readb(MCF5282_GPIO_PUAPAR);
+                port |= (0x03 << (line * 2));
+                writeb(port, MCF5282_GPIO_PUAPAR);
+        }
+}
+
+static void __init m528x_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m528x_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m528x_uart_init_line(line, m528x_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m528x_fec_init(void)
+{
+        u16 v16;
+
+        /* Set multi-function pins to ethernet mode for fec0 */
+        v16 = readw(MCF_IPSBAR + 0x100056);
+        writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
+        writeb(0xc0, MCF_IPSBAR + 0x100058);
+}
+
+/***************************************************************************/
+
+static void m528x_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
+}
+
+/***************************************************************************/
+
+#ifdef CONFIG_WILDFIRE
+void wildfire_halt(void)
+{
+        writeb(0, 0x30000007);
+        writeb(0x2, 0x30000007);
+}
+#endif
+
+#ifdef CONFIG_WILDFIREMOD
+void wildfiremod_halt(void)
+{
+        printk(KERN_INFO "WildFireMod hibernating...\n");
+
+        /* Set portE.5 to Digital IO */
+        MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
+
+        /* Make portE.5 an output */
+        MCF5282_GPIO_DDRE |= (1 << 5);
+
+        /* Now toggle portE.5 from low to high */
+        MCF5282_GPIO_PORTE &= ~(1 << 5);
+        MCF5282_GPIO_PORTE |= (1 << 5);
+
+        printk(KERN_EMERG "Failed to hibernate. Halting!\n");
+}
+#endif
+
+void __init config_BSP(char *commandp, int size)
+{
+#ifdef CONFIG_WILDFIRE
+        mach_halt = wildfire_halt;
+#endif
+#ifdef CONFIG_WILDFIREMOD
+        mach_halt = wildfiremod_halt;
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        mach_reset = m528x_cpu_reset;
+        m528x_uarts_init();
+        m528x_fec_init();
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m528x_qspi_init();
+#endif
+        platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c
new file mode 100644
index 00000000000..526db665d87
--- /dev/null
+++ b/arch/m68k/platform/528x/gpio.c
@@ -0,0 +1,438 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "NQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .base                   = 1,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *)MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *)MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *)MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TA",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 8,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFGPTA_GPTDDR,
+                .podr                           = (void __iomem *)MCFGPTA_GPTPORT,
+                .ppdr                           = (void __iomem *)MCFGPTB_GPTPORT,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TB",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 16,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFGPTB_GPTDDR,
+                .podr                           = (void __iomem *)MCFGPTB_GPTPORT,
+                .ppdr                           = (void __iomem *)MCFGPTB_GPTPORT,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QA",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 24,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFQADC_DDRQA,
+                .podr                           = (void __iomem *)MCFQADC_PORTQA,
+                .ppdr                           = (void __iomem *)MCFQADC_PORTQA,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QB",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFQADC_DDRQB,
+                .podr                           = (void __iomem *)MCFQADC_PORTQB,
+                .ppdr                           = (void __iomem *)MCFQADC_PORTQB,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "A",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRA,
+                .podr                           = (void __iomem *)MCFGPIO_PORTA,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTAP,
+                .setr                           = (void __iomem *)MCFGPIO_SETA,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRA,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "B",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 48,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRB,
+                .podr                           = (void __iomem *)MCFGPIO_PORTB,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTBP,
+                .setr                           = (void __iomem *)MCFGPIO_SETB,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRB,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 56,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRC,
+                .podr                           = (void __iomem *)MCFGPIO_PORTC,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTCP,
+                .setr                           = (void __iomem *)MCFGPIO_SETC,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRC,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "D",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRD,
+                .podr                           = (void __iomem *)MCFGPIO_PORTD,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTDP,
+                .setr                           = (void __iomem *)MCFGPIO_SETD,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRD,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "E",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRE,
+                .podr                           = (void __iomem *)MCFGPIO_PORTE,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTEP,
+                .setr                           = (void __iomem *)MCFGPIO_SETE,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRE,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "F",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 80,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRF,
+                .podr                           = (void __iomem *)MCFGPIO_PORTF,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTFP,
+                .setr                           = (void __iomem *)MCFGPIO_SETF,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRF,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "G",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 88,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRG,
+                .podr                           = (void __iomem *)MCFGPIO_PORTG,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTGP,
+                .setr                           = (void __iomem *)MCFGPIO_SETG,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRG,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "H",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 96,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRH,
+                .podr                           = (void __iomem *)MCFGPIO_PORTH,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTHP,
+                .setr                           = (void __iomem *)MCFGPIO_SETH,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "J",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 104,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRJ,
+                .podr                           = (void __iomem *)MCFGPIO_PORTJ,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTJP,
+                .setr                           = (void __iomem *)MCFGPIO_SETJ,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRJ,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "DD",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 112,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRDD,
+                .podr                           = (void __iomem *)MCFGPIO_PORTDD,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTDDP,
+                .setr                           = (void __iomem *)MCFGPIO_SETDD,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRDD,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "EH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 120,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDREH,
+                .podr                           = (void __iomem *)MCFGPIO_PORTEH,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTEHP,
+                .setr                           = (void __iomem *)MCFGPIO_SETEH,
+                .clrr                           = (void __iomem *)MCFGPIO_CLREH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "EL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 128,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDREL,
+                .podr                           = (void __iomem *)MCFGPIO_PORTEL,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTELP,
+                .setr                           = (void __iomem *)MCFGPIO_SETEL,
+                .clrr                           = (void __iomem *)MCFGPIO_CLREL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "AS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 136,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRAS,
+                .podr                           = (void __iomem *)MCFGPIO_PORTAS,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTASP,
+                .setr                           = (void __iomem *)MCFGPIO_SETAS,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRAS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 144,
+                        .ngpio                  = 7,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRQS,
+                .podr                           = (void __iomem *)MCFGPIO_PORTQS,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTQSP,
+                .setr                           = (void __iomem *)MCFGPIO_SETQS,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRQS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "SD",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 152,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRSD,
+                .podr                           = (void __iomem *)MCFGPIO_PORTSD,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTSDP,
+                .setr                           = (void __iomem *)MCFGPIO_SETSD,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRSD,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TC",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 160,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRTC,
+                .podr                           = (void __iomem *)MCFGPIO_PORTTC,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTTCP,
+                .setr                           = (void __iomem *)MCFGPIO_SETTC,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRTC,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TD",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 168,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRTD,
+                .podr                           = (void __iomem *)MCFGPIO_PORTTD,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTTDP,
+                .setr                           = (void __iomem *)MCFGPIO_SETTD,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRTD,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UA",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 176,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *)MCFGPIO_DDRUA,
+                .podr                           = (void __iomem *)MCFGPIO_PORTUA,
+                .ppdr                           = (void __iomem *)MCFGPIO_PORTUAP,
+                .setr                           = (void __iomem *)MCFGPIO_SETUA,
+                .clrr                           = (void __iomem *)MCFGPIO_CLRUA,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile
new file mode 100644
index 00000000000..d4293b791f2
--- /dev/null
+++ b/arch/m68k/platform/5307/Makefile
@@ -0,0 +1,20 @@
+#
+# Makefile for the m68knommu kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y                   += config.o gpio.o
+obj-$(CONFIG_NETtel)    += nettel.o
+obj-$(CONFIG_CLEOPATRA) += nettel.o
+
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
new file mode 100644
index 00000000000..00900ac06a9
--- /dev/null
+++ b/arch/m68k/platform/5307/config.c
@@ -0,0 +1,147 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5307/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2000, Lineo (www.lineo.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfwdebug.h>
+
+/***************************************************************************/
+
+/*
+ *      Some platforms need software versions of the GPIO data registers.
+ */
+unsigned short ppdata;
+unsigned char ledbank = 0xff;
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5307_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 73,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 74,
+        },
+        { },
+};
+
+static struct platform_device m5307_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5307_uart_platform,
+};
+
+static struct platform_device *m5307_devices[] __initdata = {
+        &m5307_uart,
+};
+
+/***************************************************************************/
+
+static void __init m5307_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
+        } else if (line == 1) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
+        }
+}
+
+static void __init m5307_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5307_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5307_uart_init_line(line, m5307_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m5307_timers_init(void)
+{
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+}
+
+/***************************************************************************/
+
+void m5307_cpu_reset(void)
+{
+        local_irq_disable();
+        /* Set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if defined(CONFIG_NETtel) || \
+    defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
+        /* Copy command line from FLASH to local buffer... */
+        memcpy(commandp, (char *) 0xf0004000, size);
+        commandp[size-1] = 0;
+#endif
+
+        mach_reset = m5307_cpu_reset;
+        m5307_timers_init();
+        m5307_uarts_init();
+
+        /* Only support the external interrupts on their primary level */
+        mcf_mapirq2imr(25, MCFINTC_EINT1);
+        mcf_mapirq2imr(27, MCFINTC_EINT3);
+        mcf_mapirq2imr(29, MCFINTC_EINT5);
+        mcf_mapirq2imr(31, MCFINTC_EINT7);
+
+#ifdef CONFIG_BDM_DISABLE
+        /*
+         * Disable the BDM clocking.  This also turns off most of the rest of
+         * the BDM device.  This is good for EMC reasons. This option is not
+         * incompatible with the memory protection option.
+         */
+        wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5307/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PP",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PADDR,
+                .podr                           = (void __iomem *) MCFSIM_PADAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/5307/nettel.c
new file mode 100644
index 00000000000..e925ea4602f
--- /dev/null
+++ b/arch/m68k/platform/5307/nettel.c
@@ -0,0 +1,153 @@
+/***************************************************************************/
+
+/*
+ *      nettel.c -- startup code support for the NETtel boards
+ *
+ *      Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/nettel.h>
+
+/***************************************************************************/
+
+/*
+ * Define the IO and interrupt resources of the 2 SMC9196 interfaces.
+ */
+#define NETTEL_SMC0_ADDR        0x30600300
+#define NETTEL_SMC0_IRQ         29
+
+#define NETTEL_SMC1_ADDR        0x30600000
+#define NETTEL_SMC1_IRQ         27
+
+/*
+ * We need some access into the SMC9196 registers. Define those registers
+ * we will need here (including the smc91x.h doesn't seem to give us these
+ * in a simple form).
+ */
+#define SMC91xx_BANKSELECT      14
+#define SMC91xx_BASEADDR        2
+#define SMC91xx_BASEMAC         4
+
+/***************************************************************************/
+
+static struct resource nettel_smc91x_0_resources[] = {
+        {
+                .start          = NETTEL_SMC0_ADDR,
+                .end            = NETTEL_SMC0_ADDR + 0x20,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = NETTEL_SMC0_IRQ,
+                .end            = NETTEL_SMC0_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource nettel_smc91x_1_resources[] = {
+        {
+                .start          = NETTEL_SMC1_ADDR,
+                .end            = NETTEL_SMC1_ADDR + 0x20,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = NETTEL_SMC1_IRQ,
+                .end            = NETTEL_SMC1_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device nettel_smc91x[] = {
+        {
+                .name                   = "smc91x",
+                .id                     = 0,
+                .num_resources          = ARRAY_SIZE(nettel_smc91x_0_resources),
+                .resource               = nettel_smc91x_0_resources,
+        },
+        {
+                .name                   = "smc91x",
+                .id                     = 1,
+                .num_resources          = ARRAY_SIZE(nettel_smc91x_1_resources),
+                .resource               = nettel_smc91x_1_resources,
+        },
+};
+
+static struct platform_device *nettel_devices[] __initdata = {
+        &nettel_smc91x[0],
+        &nettel_smc91x[1],
+};
+
+/***************************************************************************/
+
+static u8 nettel_macdefault[] __initdata = {
+        0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
+};
+
+/*
+ * Set flash contained MAC address into SMC9196 core. Make sure the flash
+ * MAC address is sane, and not an empty flash. If no good use the Moreton
+ * Bay default MAC address instead.
+ */
+
+static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
+{
+        u16 *macp;
+
+        macp = (u16 *) flashaddr;
+        if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
+                macp = (u16 *) &nettel_macdefault[0];
+
+        writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
+        writew(macp[0], ioaddr + SMC91xx_BASEMAC);
+        writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
+        writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
+}
+
+/***************************************************************************/
+
+/*
+ * Re-map the address space of at least one of the SMC ethernet
+ * parts. Both parts power up decoding the same address, so we
+ * need to move one of them first, before doing anything else.
+ */
+
+static void __init nettel_smc91x_init(void)
+{
+        writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
+        mcf_setppdata(0, 0x0080);
+        writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
+        writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
+        mcf_setppdata(0x0080, 0);
+
+        /* Set correct chip select timing for SMC9196 accesses */
+        writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
+
+        /* Set the SMC interrupts to be auto-vectored */
+        mcf_autovector(NETTEL_SMC0_IRQ);
+        mcf_autovector(NETTEL_SMC1_IRQ);
+
+        /* Set MAC addresses from flash for both interfaces */
+        nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
+        nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
+}
+
+/***************************************************************************/
+
+static int __init init_nettel(void)
+{
+        nettel_smc91x_init();
+        platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
+        return 0;
+}
+
+arch_initcall(init_nettel);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile
new file mode 100644
index 00000000000..ce01669399c
--- /dev/null
+++ b/arch/m68k/platform/532x/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
+obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c
new file mode 100644
index 00000000000..ca51323f957
--- /dev/null
+++ b/arch/m68k/platform/532x/config.c
@@ -0,0 +1,648 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/532x/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2000, Lineo (www.lineo.com)
+ *      Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
+ *      Copyright Freescale Semiconductor, Inc 2006
+ *      Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfdma.h>
+#include <asm/mcfwdebug.h>
+#include <asm/mcfqspi.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m532x_uart_platform[] = {
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCFINT_VECBASE + MCFINT_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCFINT_VECBASE + MCFINT_UART1,
+        },
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCFINT_VECBASE + MCFINT_UART2,
+        },
+        { },
+};
+
+static struct platform_device m532x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m532x_uart_platform,
+};
+
+static struct resource m532x_fec_resources[] = {
+        {
+                .start          = 0xfc030000,
+                .end            = 0xfc0307ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64 + 36,
+                .end            = 64 + 36,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 40,
+                .end            = 64 + 40,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 64 + 42,
+                .end            = 64 + 42,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m532x_fec = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m532x_fec_resources),
+        .resource               = m532x_fec_resources,
+};
+
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+static struct resource m532x_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_IOBASE,
+                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCFINT_VECBASE + MCFINT_QSPI,
+                .end            = MCFINT_VECBASE + MCFINT_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+#define MCFQSPI_CS0    84
+#define MCFQSPI_CS1    85
+#define MCFQSPI_CS2    86
+
+static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+        return 0;
+
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
+}
+
+static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                              u8 chip_select, bool cs_high)
+{
+        gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
+}
+
+static struct mcfqspi_cs_control m532x_cs_control = {
+        .setup                  = m532x_cs_setup,
+        .teardown               = m532x_cs_teardown,
+        .select                 = m532x_cs_select,
+        .deselect               = m532x_cs_deselect,
+};
+
+static struct mcfqspi_platform_data m532x_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 3,
+        .cs_control             = &m532x_cs_control,
+};
+
+static struct platform_device m532x_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(m532x_qspi_resources),
+        .resource               = m532x_qspi_resources,
+        .dev.platform_data      = &m532x_qspi_data,
+};
+
+static void __init m532x_qspi_init(void)
+{
+        /* setup QSPS pins for QSPI with gpio CS control */
+        writew(0x01f0, MCF_GPIO_PAR_QSPI);
+}
+#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
+
+
+static struct platform_device *m532x_devices[] __initdata = {
+        &m532x_uart,
+        &m532x_fec,
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        &m532x_qspi,
+#endif
+};
+
+/***************************************************************************/
+
+static void __init m532x_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                /* GPIO initialization */
+                MCF_GPIO_PAR_UART |= 0x000F;
+        } else if (line == 1) {
+                /* GPIO initialization */
+                MCF_GPIO_PAR_UART |= 0x0FF0;
+        }
+}
+
+static void __init m532x_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m532x_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m532x_uart_init_line(line, m532x_uart_platform[line].irq);
+}
+/***************************************************************************/
+
+static void __init m532x_fec_init(void)
+{
+        /* Set multi-function pins to ethernet mode for fec0 */
+        MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
+        MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
+                MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+}
+
+/***************************************************************************/
+
+static void m532x_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if !defined(CONFIG_BOOTPARAM)
+        /* Copy command line from FLASH to local buffer... */
+        memcpy(commandp, (char *) 0x4000, 4);
+        if(strncmp(commandp, "kcl ", 4) == 0){
+                memcpy(commandp, (char *) 0x4004, size);
+                commandp[size-1] = 0;
+        } else {
+                memset(commandp, 0, size);
+        }
+#endif
+
+#ifdef CONFIG_BDM_DISABLE
+        /*
+         * Disable the BDM clocking.  This also turns off most of the rest of
+         * the BDM device.  This is good for EMC reasons. This option is not
+         * incompatible with the memory protection option.
+         */
+        wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
+#endif
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        m532x_uarts_init();
+        m532x_fec_init();
+#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+        m532x_qspi_init();
+#endif
+        platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
+/* Board initialization */
+/***************************************************************************/
+/* 
+ * PLL min/max specifications
+ */
+#define MAX_FVCO        500000  /* KHz */
+#define MAX_FSYS        80000   /* KHz */
+#define MIN_FSYS        58333   /* KHz */
+#define FREF            16000   /* KHz */
+
+
+#define MAX_MFD         135     /* Multiplier */
+#define MIN_MFD         88      /* Multiplier */
+#define BUSDIV          6       /* Divider */
+
+/*
+ * Low Power Divider specifications
+ */
+#define MIN_LPD         (1 << 0)    /* Divider (not encoded) */
+#define MAX_LPD         (1 << 15)   /* Divider (not encoded) */
+#define DEFAULT_LPD     (1 << 1)        /* Divider (not encoded) */
+
+#define SYS_CLK_KHZ     80000
+#define SYSTEM_PERIOD   12.5
+/*
+ *  SDRAM Timing Parameters
+ */  
+#define SDRAM_BL        8       /* # of beats in a burst */
+#define SDRAM_TWR       2       /* in clocks */
+#define SDRAM_CASL      2.5     /* CASL in clocks */
+#define SDRAM_TRCD      2       /* in clocks */
+#define SDRAM_TRP       2       /* in clocks */
+#define SDRAM_TRFC      7       /* in clocks */
+#define SDRAM_TREFI     7800    /* in ns */
+
+#define EXT_SRAM_ADDRESS        (0xC0000000)
+#define FLASH_ADDRESS           (0x00000000)
+#define SDRAM_ADDRESS           (0x40000000)
+
+#define NAND_FLASH_ADDRESS      (0xD0000000)
+
+int sys_clk_khz = 0;
+int sys_clk_mhz = 0;
+
+void wtm_init(void);
+void scm_init(void);
+void gpio_init(void);
+void fbcs_init(void);
+void sdramc_init(void);
+int  clock_pll (int fsys, int flags);
+int  clock_limp (int);
+int  clock_exit_limp (void);
+int  get_sys_clock (void);
+
+asmlinkage void __init sysinit(void)
+{
+        sys_clk_khz = clock_pll(0, 0);
+        sys_clk_mhz = sys_clk_khz/1000;
+        
+        wtm_init();
+        scm_init();
+        gpio_init();
+        fbcs_init();
+        sdramc_init();
+}
+
+void wtm_init(void)
+{
+        /* Disable watchdog timer */
+        MCF_WTM_WCR = 0;
+}
+
+#define MCF_SCM_BCR_GBW         (0x00000100)
+#define MCF_SCM_BCR_GBR         (0x00000200)
+
+void scm_init(void)
+{
+        /* All masters are trusted */
+        MCF_SCM_MPR = 0x77777777;
+    
+        /* Allow supervisor/user, read/write, and trusted/untrusted
+           access to all slaves */
+        MCF_SCM_PACRA = 0;
+        MCF_SCM_PACRB = 0;
+        MCF_SCM_PACRC = 0;
+        MCF_SCM_PACRD = 0;
+        MCF_SCM_PACRE = 0;
+        MCF_SCM_PACRF = 0;
+
+        /* Enable bursts */
+        MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
+}
+
+
+void fbcs_init(void)
+{
+        MCF_GPIO_PAR_CS = 0x0000003E;
+
+        /* Latch chip select */
+        MCF_FBCS1_CSAR = 0x10080000;
+
+        MCF_FBCS1_CSCR = 0x002A3780;
+        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
+
+        /* Initialize latch to drive signals to inactive states */
+        *((u16 *)(0x10080000)) = 0xFFFF;
+
+        /* External SRAM */
+        MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
+        MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
+                        | MCF_FBCS_CSCR_AA
+                        | MCF_FBCS_CSCR_SBM
+                        | MCF_FBCS_CSCR_WS(1));
+        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
+                        | MCF_FBCS_CSMR_V);
+
+        /* Boot Flash connected to FBCS0 */
+        MCF_FBCS0_CSAR = FLASH_ADDRESS;
+        MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
+                        | MCF_FBCS_CSCR_BEM
+                        | MCF_FBCS_CSCR_AA
+                        | MCF_FBCS_CSCR_SBM
+                        | MCF_FBCS_CSCR_WS(7));
+        MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
+                        | MCF_FBCS_CSMR_V);
+}
+
+void sdramc_init(void)
+{
+        /*
+         * Check to see if the SDRAM has already been initialized
+         * by a run control tool
+         */
+        if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
+                /* SDRAM chip select initialization */
+                
+                /* Initialize SDRAM chip select */
+                MCF_SDRAMC_SDCS0 = (0
+                        | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
+                        | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
+
+        /*
+         * Basic configuration and initialization
+         */
+        MCF_SDRAMC_SDCFG1 = (0
+                | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
+                | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
+                | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
+                | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
+                | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
+                | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
+                | MCF_SDRAMC_SDCFG1_WTLAT(3));
+        MCF_SDRAMC_SDCFG2 = (0
+                | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
+                | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
+                | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
+                | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
+
+            
+        /*
+         * Precharge and enable write to SDMR
+         */
+        MCF_SDRAMC_SDCR = (0
+                | MCF_SDRAMC_SDCR_MODE_EN
+                | MCF_SDRAMC_SDCR_CKE
+                | MCF_SDRAMC_SDCR_DDR
+                | MCF_SDRAMC_SDCR_MUX(1)
+                | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
+                | MCF_SDRAMC_SDCR_PS_16
+                | MCF_SDRAMC_SDCR_IPALL);            
+
+        /*
+         * Write extended mode register
+         */
+        MCF_SDRAMC_SDMR = (0
+                | MCF_SDRAMC_SDMR_BNKAD_LEMR
+                | MCF_SDRAMC_SDMR_AD(0x0)
+                | MCF_SDRAMC_SDMR_CMD);
+
+        /*
+         * Write mode register and reset DLL
+         */
+        MCF_SDRAMC_SDMR = (0
+                | MCF_SDRAMC_SDMR_BNKAD_LMR
+                | MCF_SDRAMC_SDMR_AD(0x163)
+                | MCF_SDRAMC_SDMR_CMD);
+
+        /*
+         * Execute a PALL command
+         */
+        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+
+        /*
+         * Perform two REF cycles
+         */
+        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+
+        /*
+         * Write mode register and clear reset DLL
+         */
+        MCF_SDRAMC_SDMR = (0
+                | MCF_SDRAMC_SDMR_BNKAD_LMR
+                | MCF_SDRAMC_SDMR_AD(0x063)
+                | MCF_SDRAMC_SDMR_CMD);
+                                
+        /*
+         * Enable auto refresh and lock SDMR
+         */
+        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
+        MCF_SDRAMC_SDCR |= (0
+                | MCF_SDRAMC_SDCR_REF
+                | MCF_SDRAMC_SDCR_DQS_OE(0xC));
+        }
+}
+
+void gpio_init(void)
+{
+        /* Enable UART0 pins */
+        MCF_GPIO_PAR_UART = ( 0
+                | MCF_GPIO_PAR_UART_PAR_URXD0
+                | MCF_GPIO_PAR_UART_PAR_UTXD0);
+
+        /* Initialize TIN3 as a GPIO output to enable the write
+           half of the latch */
+        MCF_GPIO_PAR_TIMER = 0x00;
+        __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
+        __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
+
+}
+
+int clock_pll(int fsys, int flags)
+{
+        int fref, temp, fout, mfd;
+        u32 i;
+
+        fref = FREF;
+        
+        if (fsys == 0) {
+                /* Return current PLL output */
+                mfd = MCF_PLL_PFDR;
+
+                return (fref * mfd / (BUSDIV * 4));
+        }
+
+        /* Check bounds of requested system clock */
+        if (fsys > MAX_FSYS)
+                fsys = MAX_FSYS;
+        if (fsys < MIN_FSYS)
+                fsys = MIN_FSYS;
+
+        /* Multiplying by 100 when calculating the temp value,
+           and then dividing by 100 to calculate the mfd allows
+           for exact values without needing to include floating
+           point libraries. */
+        temp = 100 * fsys / fref;
+        mfd = 4 * BUSDIV * temp / 100;
+                        
+        /* Determine the output frequency for selected values */
+        fout = (fref * mfd / (BUSDIV * 4));
+
+        /*
+         * Check to see if the SDRAM has already been initialized.
+         * If it has then the SDRAM needs to be put into self refresh
+         * mode before reprogramming the PLL.
+         */
+        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+                /* Put SDRAM into self refresh mode */
+                MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
+
+        /*
+         * Initialize the PLL to generate the new system clock frequency.
+         * The device must be put into LIMP mode to reprogram the PLL.
+         */
+
+        /* Enter LIMP mode */
+        clock_limp(DEFAULT_LPD);
+                                        
+        /* Reprogram PLL for desired fsys */
+        MCF_PLL_PODR = (0
+                | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
+                | MCF_PLL_PODR_BUSDIV(BUSDIV));
+                                                
+        MCF_PLL_PFDR = mfd;
+                
+        /* Exit LIMP mode */
+        clock_exit_limp();
+        
+        /*
+         * Return the SDRAM to normal operation if it is in use.
+         */
+        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+                /* Exit self refresh mode */
+                MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
+
+        /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
+        MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
+
+        /* wait for DQS logic to relock */
+        for (i = 0; i < 0x200; i++)
+                ;
+
+        return fout;
+}
+
+int clock_limp(int div)
+{
+        u32 temp;
+
+        /* Check bounds of divider */
+        if (div < MIN_LPD)
+                div = MIN_LPD;
+        if (div > MAX_LPD)
+                div = MAX_LPD;
+    
+        /* Save of the current value of the SSIDIV so we don't
+           overwrite the value*/
+        temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
+      
+        /* Apply the divider to the system clock */
+        MCF_CCM_CDR = ( 0
+                | MCF_CCM_CDR_LPDIV(div)
+                | MCF_CCM_CDR_SSIDIV(temp));
+    
+        MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
+    
+        return (FREF/(3*(1 << div)));
+}
+
+int clock_exit_limp(void)
+{
+        int fout;
+        
+        /* Exit LIMP mode */
+        MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
+
+        /* Wait for PLL to lock */
+        while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
+                ;
+        
+        fout = get_sys_clock();
+
+        return fout;
+}
+
+int get_sys_clock(void)
+{
+        int divider;
+        
+        /* Test to see if device is in LIMP mode */
+        if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
+                divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
+                return (FREF/(2 << divider));
+        }
+        else
+                return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
+}
diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c
new file mode 100644
index 00000000000..212a85deac9
--- /dev/null
+++ b/arch/m68k/platform/532x/gpio.c
@@ -0,0 +1,337 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PIRQ",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
+                .podr                           = (void __iomem *) MCFEPORT_EPDR,
+                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 8,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 16,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "SSI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 24,
+                        .ngpio                  = 5,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SSI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_SSI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SSI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SSI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SSI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BUSCTL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 32,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "BE",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 40,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BE,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_BE,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BE,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "CS",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 49,
+                        .ngpio                  = 5,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "PWM",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 58,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_PWM,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_PWM,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_PWM,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_PWM,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_PWM,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "FECI2C",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 64,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "UART",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 72,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UART,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_UART,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UART,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "QSPI",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 80,
+                        .ngpio                  = 6,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "TIMER",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 88,
+                        .ngpio                  = 4,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "LCDDATAH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 96,
+                        .ngpio                  = 2,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "LCDDATAM",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 104,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "LCDDATAL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 112,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "LCDCTLH",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 120,
+                        .ngpio                  = 1,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
+        },
+        {
+                .gpio_chip                      = {
+                        .label                  = "LCDCTLL",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value_fast,
+                        .base                   = 128,
+                        .ngpio                  = 8,
+                },
+                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
+                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
+                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
+                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
+                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile
new file mode 100644
index 00000000000..e83fe148edd
--- /dev/null
+++ b/arch/m68k/platform/5407/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
+
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/5407/config.c
new file mode 100644
index 00000000000..70ea789a400
--- /dev/null
+++ b/arch/m68k/platform/5407/config.c
@@ -0,0 +1,122 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/5407/config.c
+ *
+ *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      Copyright (C) 2000, Lineo (www.lineo.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m5407_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 73,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 74,
+        },
+        { },
+};
+
+static struct platform_device m5407_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m5407_uart_platform,
+};
+
+static struct platform_device *m5407_devices[] __initdata = {
+        &m5407_uart,
+};
+
+/***************************************************************************/
+
+static void __init m5407_uart_init_line(int line, int irq)
+{
+        if (line == 0) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART0);
+        } else if (line == 1) {
+                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
+                mcf_mapirq2imr(irq, MCFINTC_UART1);
+        }
+}
+
+static void __init m5407_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m5407_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m5407_uart_init_line(line, m5407_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void __init m5407_timers_init(void)
+{
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+}
+
+/***************************************************************************/
+
+void m5407_cpu_reset(void)
+{
+        local_irq_disable();
+        /* set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = m5407_cpu_reset;
+        m5407_timers_init();
+        m5407_uarts_init();
+
+        /* Only support the external interrupts on their primary level */
+        mcf_mapirq2imr(25, MCFINTC_EINT1);
+        mcf_mapirq2imr(27, MCFINTC_EINT3);
+        mcf_mapirq2imr(29, MCFINTC_EINT5);
+        mcf_mapirq2imr(31, MCFINTC_EINT7);
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5407/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+        {
+                .gpio_chip                      = {
+                        .label                  = "PP",
+                        .request                = mcf_gpio_request,
+                        .free                   = mcf_gpio_free,
+                        .direction_input        = mcf_gpio_direction_input,
+                        .direction_output       = mcf_gpio_direction_output,
+                        .get                    = mcf_gpio_get_value,
+                        .set                    = mcf_gpio_set_value,
+                        .ngpio                  = 16,
+                },
+                .pddr                           = (void __iomem *) MCFSIM_PADDR,
+                .podr                           = (void __iomem *) MCFSIM_PADAT,
+                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
+        },
+};
+
+static int __init mcf_gpio_init(void)
+{
+        unsigned i = 0;
+        while (i < ARRAY_SIZE(mcf_gpio_chips))
+                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+        return 0;
+}
+
+core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile
new file mode 100644
index 00000000000..6cfd090ec3c
--- /dev/null
+++ b/arch/m68k/platform/54xx/Makefile
@@ -0,0 +1,19 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
+# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o
+obj-$(CONFIG_FIREBEE) += firebee.o
+
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c
new file mode 100644
index 00000000000..78130984db9
--- /dev/null
+++ b/arch/m68k/platform/54xx/config.c
@@ -0,0 +1,115 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/54xx/config.c
+ *
+ *      Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/m54xxsim.h>
+#include <asm/mcfuart.h>
+#include <asm/m54xxgpt.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m54xx_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 64 + 35,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 64 + 34,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE3,
+                .irq            = 64 + 33,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE4,
+                .irq            = 64 + 32,
+        },
+};
+
+static struct platform_device m54xx_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m54xx_uart_platform,
+};
+
+static struct platform_device *m54xx_devices[] __initdata = {
+        &m54xx_uart,
+};
+
+
+/***************************************************************************/
+
+static void __init m54xx_uart_init_line(int line, int irq)
+{
+        int rts_cts;
+
+        /* enable io pins */
+        switch (line) {
+        case 0:
+                rts_cts = 0; break;
+        case 1:
+                rts_cts = MCF_PAR_PSC_RTS_RTS; break;
+        case 2:
+                rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
+        case 3:
+                rts_cts = 0; break;
+        }
+        __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
+                                                MCF_MBAR + MCF_PAR_PSC(line));
+}
+
+static void __init m54xx_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void mcf54xx_reset(void)
+{
+        /* disable interrupts and enable the watchdog */
+        asm("movew #0x2700, %sr\n");
+        __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+        __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
+                                                MCF_MBAR + MCF_GPT_GMS0);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = mcf54xx_reset;
+        m54xx_uarts_init();
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+
+        platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/54xx/firebee.c b/arch/m68k/platform/54xx/firebee.c
new file mode 100644
index 00000000000..46d50534f98
--- /dev/null
+++ b/arch/m68k/platform/54xx/firebee.c
@@ -0,0 +1,86 @@
+/***************************************************************************/
+
+/*
+ *      firebee.c -- extra startup code support for the FireBee boards
+ *
+ *      Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+/***************************************************************************/
+
+/*
+ *      8MB of NOR flash fitted to the FireBee board.
+ */
+#define FLASH_PHYS_ADDR         0xe0000000      /* Physical address of flash */
+#define FLASH_PHYS_SIZE         0x00800000      /* Size of flash */
+
+#define PART_BOOT_START         0x00000000      /* Start at bottom of flash */
+#define PART_BOOT_SIZE          0x00040000      /* 256k in size */
+#define PART_IMAGE_START        0x00040000      /* Start after boot loader */
+#define PART_IMAGE_SIZE         0x006c0000      /* Most of flash */
+#define PART_FPGA_START         0x00700000      /* Start at offset 7MB */
+#define PART_FPGA_SIZE          0x00100000      /* 1MB in size */
+
+static struct mtd_partition firebee_flash_parts[] = {
+        {
+                .name   = "dBUG",
+                .offset = PART_BOOT_START,
+                .size   = PART_BOOT_SIZE,
+        },
+        {
+                .name   = "FPGA",
+                .offset = PART_FPGA_START,
+                .size   = PART_FPGA_SIZE,
+        },
+        {
+                .name   = "image",
+                .offset = PART_IMAGE_START,
+                .size   = PART_IMAGE_SIZE,
+        },
+};
+
+static struct physmap_flash_data firebee_flash_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(firebee_flash_parts),
+        .parts          = firebee_flash_parts,
+};
+
+static struct resource firebee_flash_resource = {
+        .start          = FLASH_PHYS_ADDR,
+        .end            = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device firebee_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &firebee_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &firebee_flash_resource,
+};
+
+/***************************************************************************/
+
+static int __init init_firebee(void)
+{
+        platform_device_register(&firebee_flash);
+        return 0;
+}
+
+arch_initcall(init_firebee);
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/68328/Makefile b/arch/m68k/platform/68328/Makefile
new file mode 100644
index 00000000000..5e5435552d5
--- /dev/null
+++ b/arch/m68k/platform/68328/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for arch/m68knommu/platform/68328.
+#
+
+head-y                  = head-$(MODEL).o
+head-$(CONFIG_PILOT)    = head-pilot.o
+head-$(CONFIG_DRAGEN2)  = head-de2.o
+
+obj-y                   += entry.o ints.o timers.o
+obj-$(CONFIG_M68328)    += config.o
+obj-$(CONFIG_ROM)       += romvec.o
+
+extra-y                 := head.o
+extra-$(CONFIG_M68328)  += bootlogo.rh head.o
+
+$(obj)/bootlogo.rh: $(src)/bootlogo.h
+        perl $(src)/bootlogo.pl < $(src)/bootlogo.h > $(obj)/bootlogo.rh
+
+$(obj)/head.o: $(obj)/$(head-y)
+        ln -sf $(head-y) $(obj)/head.o
+
+clean-files := $(obj)/bootlogo.rh $(obj)/head.o $(head-y)
diff --git a/arch/m68k/platform/68328/bootlogo.h b/arch/m68k/platform/68328/bootlogo.h
new file mode 100644
index 00000000000..67bc2c17386
--- /dev/null
+++ b/arch/m68k/platform/68328/bootlogo.h
@@ -0,0 +1,270 @@
+#define bootlogo_width 160
+#define bootlogo_height 160
+static unsigned char bootlogo_bits[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x01, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x40, 0x55, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x80, 0x08, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x08, 0x00, 0x00,
+  0x00, 0xff, 0x80, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0xf8, 0x80, 0x0f,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x04, 0x00, 0x00, 0x00, 0x78, 0x80, 0x0f, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00,
+  0x00, 0x78, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40,
+  0xa8, 0x02, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x70, 0x28, 0x01, 0x00, 0x00,
+  0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x20, 0x00, 0x00, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x70,
+  0x54, 0x01, 0x00, 0x00, 0x00, 0x3e, 0x80, 0x01, 0x3a, 0x78, 0x80, 0x0e,
+  0x50, 0xc0, 0x03, 0x0e, 0x00, 0x20, 0x00, 0x00, 0xaa, 0x00, 0x00, 0x00,
+  0x00, 0x3e, 0xf0, 0x83, 0x1f, 0xfc, 0xe0, 0x0f, 0x78, 0xf8, 0x87, 0x1f,
+  0x00, 0x18, 0x00, 0x30, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x1e, 0xf8, 0xc3,
+  0x1f, 0xfc, 0xe0, 0x0f, 0x78, 0xf8, 0x87, 0x0f, 0x00, 0x20, 0x00, 0x10,
+  0x55, 0x00, 0x00, 0x00, 0x00, 0x1e, 0xc0, 0x03, 0x9f, 0xf3, 0x80, 0x0f,
+  0x78, 0x80, 0xc7, 0x0e, 0x00, 0x18, 0x00, 0x20, 0xaa, 0x00, 0x00, 0x00,
+  0x00, 0x1e, 0xe0, 0x03, 0x9f, 0xf1, 0x80, 0x07, 0x78, 0x80, 0x67, 0x00,
+  0x00, 0x24, 0x00, 0x18, 0x55, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe0, 0x01,
+  0x5e, 0xf0, 0x80, 0x07, 0x3c, 0x00, 0x2f, 0x00, 0x00, 0x14, 0x00, 0x20,
+  0xaa, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe0, 0x01, 0x7f, 0xf0, 0x80, 0x07,
+  0x3c, 0x00, 0x3f, 0x00, 0x00, 0x08, 0x00, 0x18, 0x55, 0x00, 0x00, 0x00,
+  0x00, 0x0f, 0xe0, 0x00, 0x3f, 0xf0, 0xc0, 0x03, 0x1e, 0x00, 0x1f, 0x00,
+  0x00, 0x14, 0x00, 0x28, 0xaa, 0x00, 0x00, 0x00, 0x80, 0x0f, 0xf0, 0x00,
+  0x1f, 0xf0, 0xc0, 0x03, 0x1f, 0x00, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x0c,
+  0x54, 0x00, 0x00, 0x00, 0x80, 0x07, 0x78, 0x00, 0x1f, 0x78, 0xc0, 0x03,
+  0x1f, 0x00, 0x1e, 0x00, 0x00, 0x0a, 0x00, 0x12, 0xa8, 0x00, 0x00, 0x00,
+  0x80, 0x07, 0x78, 0x00, 0x1f, 0x78, 0xe0, 0x03, 0x1f, 0x00, 0x1f, 0x00,
+  0x00, 0x04, 0x00, 0x0a, 0x54, 0x00, 0x00, 0x00, 0x80, 0x07, 0x78, 0x80,
+  0x0f, 0x78, 0xe0, 0x03, 0x1f, 0x00, 0x1e, 0x00, 0x00, 0x0a, 0x00, 0x08,
+  0x50, 0x01, 0x00, 0x00, 0x84, 0x03, 0x78, 0x80, 0x07, 0x3c, 0xe0, 0xc1,
+  0x0f, 0x00, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x06, 0xa8, 0x00, 0x00, 0x00,
+  0xc0, 0x03, 0x78, 0xc0, 0x07, 0x3c, 0xe0, 0xc1, 0x0f, 0x00, 0x1f, 0x00,
+  0x00, 0x0a, 0x00, 0x08, 0x50, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x38, 0xc0,
+  0x07, 0x3c, 0xe0, 0x60, 0x0f, 0x80, 0x1e, 0x00, 0x00, 0x05, 0x00, 0x07,
+  0xa0, 0x00, 0x00, 0x80, 0xe0, 0x01, 0x3c, 0xc0, 0x07, 0x3c, 0xf0, 0xa0,
+  0x07, 0xc0, 0x1c, 0x00, 0x00, 0x0a, 0x80, 0x08, 0xa0, 0x02, 0x00, 0xa0,
+  0xe0, 0x21, 0x1c, 0xc0, 0x03, 0x1c, 0x71, 0x90, 0x47, 0x40, 0x3c, 0x04,
+  0x00, 0x05, 0x80, 0x06, 0xa0, 0x02, 0x00, 0x20, 0xe0, 0x31, 0x1e, 0xc3,
+  0x03, 0x1e, 0x79, 0x98, 0x47, 0x60, 0x38, 0x04, 0x00, 0x15, 0x40, 0x0a,
+  0xa0, 0x0a, 0x00, 0x1a, 0xe0, 0x19, 0x9e, 0xe1, 0x01, 0x9e, 0x78, 0xcc,
+  0xa7, 0x32, 0x78, 0x02, 0x80, 0x2a, 0x40, 0x05, 0x80, 0x2a, 0x00, 0x05,
+  0xe0, 0x0d, 0x9e, 0xe0, 0x01, 0xde, 0x78, 0xc6, 0x97, 0x1b, 0x78, 0x03,
+  0x80, 0x52, 0x30, 0x0a, 0x00, 0x95, 0xd2, 0x0a, 0xe0, 0x0f, 0xfe, 0xe0,
+  0x00, 0x7e, 0xf8, 0x87, 0x9f, 0x0f, 0xf8, 0x01, 0x00, 0xa1, 0x0e, 0x15,
+  0x80, 0x55, 0x55, 0x01, 0xe0, 0x01, 0x3c, 0xf0, 0x00, 0x3c, 0xf0, 0x80,
+  0x8f, 0x0f, 0x70, 0x00, 0x00, 0x81, 0x02, 0x14, 0x00, 0x54, 0x55, 0x00,
+  0xc0, 0x01, 0x3c, 0x00, 0x00, 0x0c, 0x60, 0x00, 0x07, 0x03, 0x70, 0x00,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x40, 0x01, 0x00, 0x11, 0x09, 0x00, 0x04, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
+  0x00, 0x20, 0x01, 0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x49, 0x32, 0x49, 0x49, 0x91,
+  0x24, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x20, 0x49, 0x0a, 0x09, 0xc9, 0x92, 0x14, 0x81, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x49,
+  0x18, 0x01, 0x49, 0x92, 0x0c, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x49, 0x30, 0x01, 0x49, 0x92,
+  0x14, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x08, 0x69, 0x22, 0x09, 0x49, 0xd2, 0x24, 0x24, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x51,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x05, 0xf0, 0x3f, 0x09, 0x00,
+  0x00, 0x10, 0x24, 0x48, 0x10, 0x12, 0x41, 0x52, 0x24, 0x09, 0x46, 0x71,
+  0x90, 0x20, 0x02, 0xfc, 0xff, 0x1f, 0x80, 0x22, 0x00, 0x90, 0x24, 0x49,
+  0x12, 0x92, 0x40, 0xb2, 0x24, 0x09, 0xc9, 0x49, 0x04, 0x80, 0x90, 0xfc,
+  0xff, 0xbf, 0x24, 0x00, 0x00, 0x90, 0x24, 0x49, 0x12, 0x92, 0x40, 0x92,
+  0x24, 0x06, 0x49, 0x48, 0x50, 0x0a, 0x02, 0xfe, 0xff, 0x3f, 0x00, 0x05,
+  0x00, 0x50, 0xa5, 0x4a, 0x15, 0x92, 0x40, 0x92, 0x24, 0x06, 0x49, 0x48,
+  0x80, 0x40, 0x48, 0xfe, 0xff, 0x3f, 0x49, 0x00, 0x00, 0x20, 0x42, 0x84,
+  0x88, 0x1a, 0x41, 0x92, 0x34, 0x49, 0x49, 0x68, 0x00, 0x38, 0x10, 0x07,
+  0x00, 0x60, 0x80, 0x00, 0x00, 0x20, 0x42, 0x84, 0x88, 0x14, 0x4e, 0x92,
+  0x28, 0x49, 0x46, 0x50, 0x00, 0x80, 0x83, 0x01, 0x00, 0xa0, 0x6a, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+  0x00, 0x00, 0xfc, 0x00, 0x00, 0xc0, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, };
diff --git a/arch/m68k/platform/68328/bootlogo.pl b/arch/m68k/platform/68328/bootlogo.pl
new file mode 100644
index 00000000000..b04ae3f50da
--- /dev/null
+++ b/arch/m68k/platform/68328/bootlogo.pl
@@ -0,0 +1,10 @@
+
+$_ = join("", <>);
+
+s/(0x[0-9a-f]{2})/sprintf("0x%.2x",ord(pack("b8",unpack("B8",chr(hex($1))))))/gei;
+
+s/^ /   .byte /gm;
+s/[,};]+$//gm;
+s/^static.*//gm;
+
+print $_;
diff --git a/arch/m68k/platform/68328/config.c b/arch/m68k/platform/68328/config.c
new file mode 100644
index 00000000000..a7bd21deb00
--- /dev/null
+++ b/arch/m68k/platform/68328/config.c
@@ -0,0 +1,52 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/68328/config.c
+ *
+ *  Copyright (C) 1993 Hamish Macdonald
+ *  Copyright (C) 1999 D. Jeff Dionne
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * VZ Support/Fixes             Evan Stawnyczy <e@lineo.ca>
+ */
+
+/***************************************************************************/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/system.h>
+#include <asm/machdep.h>
+#include <asm/MC68328.h>
+
+/***************************************************************************/
+
+void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+
+/***************************************************************************/
+
+void m68328_reset (void)
+{
+  local_irq_disable();
+  asm volatile ("moveal #0x10c00000, %a0;\n\t"
+                "moveb #0, 0xFFFFF300;\n\t"
+                "moveal 0(%a0), %sp;\n\t"
+                "moveal 4(%a0), %a0;\n\t"
+                "jmp (%a0);");
+}
+
+/***************************************************************************/
+
+void config_BSP(char *command, int len)
+{
+  printk(KERN_INFO "\n68328 support D. Jeff Dionne <jeff@uclinux.org>\n");
+  printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n");
+  printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n");
+
+  mach_gettod = m68328_timer_gettod;
+  mach_reset = m68328_reset;
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S
new file mode 100644
index 00000000000..293e1eba9ac
--- /dev/null
+++ b/arch/m68k/platform/68328/entry.S
@@ -0,0 +1,261 @@
+/*
+ *  linux/arch/m68knommu/platform/68328/entry.S
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file README.legal in the main directory of this archive
+ * for more details.
+ *
+ * Linux/m68k support by Hamish Macdonald
+ */
+
+#include <linux/linkage.h>
+#include <asm/thread_info.h>
+#include <asm/unistd.h>
+#include <asm/errno.h>
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/traps.h>
+#include <asm/asm-offsets.h>
+#include <asm/entry.h>
+
+.text
+
+.globl system_call
+.globl resume
+.globl ret_from_exception
+.globl ret_from_signal
+.globl sys_call_table
+.globl ret_from_interrupt
+.globl bad_interrupt
+.globl inthandler1
+.globl inthandler2
+.globl inthandler3
+.globl inthandler4
+.globl inthandler5
+.globl inthandler6
+.globl inthandler7
+
+badsys:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
+        jra     ret_from_exception
+
+do_trace:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
+        subql   #4,%sp
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace_enter
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        movel   %sp@(PT_OFF_ORIG_D0),%d1
+        movel   #-ENOSYS,%d0
+        cmpl    #NR_syscalls,%d1
+        jcc     1f
+        lsl     #2,%d1
+        lea     sys_call_table, %a0
+        jbsr    %a0@(%d1)
+
+1:      movel   %d0,%sp@(PT_OFF_D0)     /* save the return value */
+        subql   #4,%sp                  /* dummy return address */
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace_leave
+
+ret_from_signal:
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jra     ret_from_exception
+
+ENTRY(system_call)
+        SAVE_ALL
+
+        /* save top of frame*/
+        pea     %sp@
+        jbsr    set_esp0
+        addql   #4,%sp
+
+        movel   %sp@(PT_OFF_ORIG_D0),%d0
+
+        movel   %sp,%d1                 /* get thread_info pointer */
+        andl    #-THREAD_SIZE,%d1
+        movel   %d1,%a2
+        btst    #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+        jne     do_trace
+        cmpl    #NR_syscalls,%d0
+        jcc     badsys
+        lsl     #2,%d0
+        lea     sys_call_table,%a0
+        movel   %a0@(%d0), %a0
+        jbsr    %a0@
+        movel   %d0,%sp@(PT_OFF_D0)     /* save the return value*/
+
+ret_from_exception:
+        btst    #5,%sp@(PT_OFF_SR)      /* check if returning to kernel*/
+        jeq     Luser_return            /* if so, skip resched, signals*/
+
+Lkernel_return:
+        RESTORE_ALL
+
+Luser_return:
+        /* only allow interrupts when we are really the last one on the*/
+        /* kernel stack, otherwise stack overflow can occur during*/
+        /* heavy interrupt load*/
+        andw    #ALLOWINT,%sr
+
+        movel   %sp,%d1                 /* get thread_info pointer */
+        andl    #-THREAD_SIZE,%d1
+        movel   %d1,%a2
+1:
+        move    %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
+        jne     Lwork_to_do
+        RESTORE_ALL
+
+Lwork_to_do:
+        movel   %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
+        btst    #TIF_NEED_RESCHED,%d1
+        jne     reschedule
+
+Lsignal_return:
+        subql   #4,%sp                  /* dummy return address*/
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        bsrw    do_signal
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jra     1b
+
+/*
+ * This is the main interrupt handler, responsible for calling process_int()
+ */
+inthandler1:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #65,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler2:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #66,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler3:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #67,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler4:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #68,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler5:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #69,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler6:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #70,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler7:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   #71,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+inthandler:
+        SAVE_ALL
+        movew   %sp@(PT_OFF_FORMATVEC), %d0
+        and     #0x3ff, %d0
+
+        movel   %sp,%sp@-
+        movel   %d0,%sp@-               /*  put vector # on stack*/
+        jbsr    process_int             /*  process the IRQ*/
+3:      addql   #8,%sp                  /*  pop parameters off stack*/
+        bra     ret_from_interrupt
+
+ret_from_interrupt:
+        jeq     1f
+2:
+        RESTORE_ALL
+1:
+        moveb   %sp@(PT_OFF_SR), %d0
+        and     #7, %d0
+        jhi     2b
+
+        /* check if we need to do software interrupts */
+        jeq     ret_from_exception
+
+        pea     ret_from_exception
+        jra     do_softirq
+
+
+/*
+ * Handler for uninitialized and spurious interrupts.
+ */
+ENTRY(bad_interrupt)
+        addql   #1,irq_err_count
+        rte
+
+/*
+ * Beware - when entering resume, prev (the current task) is
+ * in a0, next (the new task) is in a1, so don't change these
+ * registers until their contents are no longer needed.
+ */
+ENTRY(resume)
+        movel   %a0,%d1                         /* save prev thread in d1 */
+        movew   %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */
+        SAVE_SWITCH_STACK
+        movel   %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */
+        movel   %usp,%a3                        /* save usp */
+        movel   %a3,%a0@(TASK_THREAD+THREAD_USP)
+
+        movel   %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */
+        movel   %a3,%usp
+        movel   %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */
+        RESTORE_SWITCH_STACK
+        movew   %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */
+        rts
+
diff --git a/arch/m68k/platform/68328/head-de2.S b/arch/m68k/platform/68328/head-de2.S
new file mode 100644
index 00000000000..f632fdcb93e
--- /dev/null
+++ b/arch/m68k/platform/68328/head-de2.S
@@ -0,0 +1,128 @@
+
+#define MEM_END 0x00800000      /* Memory size 8Mb */
+
+#undef CRT_DEBUG
+
+.macro  PUTC CHAR
+#ifdef CRT_DEBUG
+        moveq   #\CHAR, %d7
+        jsr     putc
+#endif
+.endm
+
+        .global _start
+        .global _rambase
+        .global _ramvec
+        .global _ramstart
+        .global _ramend
+        
+        .data
+
+/*
+ *      Set up the usable of RAM stuff
+ */
+_rambase:
+        .long   0
+_ramvec:
+        .long   0
+_ramstart:
+        .long   0
+_ramend:
+        .long   0
+
+        .text
+
+_start:
+
+/*
+ * Setup initial stack
+ */
+        /* disable all interrupts */
+        movew   #0x2700, %sr
+        movel   #-1, 0xfffff304
+        movel   #MEM_END-4, %sp
+
+        PUTC    '\r'
+        PUTC    '\n'
+        PUTC    'A'
+        PUTC    'B'
+
+/*
+ *      Determine end of RAM
+ */
+
+        movel   #MEM_END, %a0
+        movel   %a0, _ramend
+
+        PUTC    'C'
+
+/*
+ *      Move ROM filesystem above bss :-)
+ */
+
+        moveal  #_sbss, %a0                     /* romfs at the start of bss */
+        moveal  #_ebss, %a1                     /* Set up destination  */
+        movel   %a0, %a2                        /* Copy of bss start */
+
+        movel   8(%a0), %d1                     /* Get size of ROMFS */
+        addql   #8, %d1                         /* Allow for rounding */
+        andl    #0xfffffffc, %d1        /* Whole words */
+
+        addl    %d1, %a0                        /* Copy from end */
+        addl    %d1, %a1                        /* Copy from end */
+        movel   %a1, _ramstart          /* Set start of ram */
+
+1:
+        movel   -(%a0), %d0                     /* Copy dword */
+        movel   %d0, -(%a1)
+        cmpl    %a0, %a2                        /* Check if at end */
+        bne     1b
+
+        PUTC    'D'
+
+/*
+ * Initialize BSS segment to 0
+ */
+
+        lea     _sbss, %a0
+        lea     _ebss, %a1
+
+        /* Copy 0 to %a0 until %a0 == %a1 */
+2:      cmpal   %a0, %a1
+        beq     1f
+        clrl    (%a0)+
+        bra     2b
+1:
+
+        PUTC    'E'
+
+/*
+ * Load the current task pointer and stack
+ */
+
+        lea     init_thread_union, %a0
+        lea     0x2000(%a0), %sp
+
+        PUTC    'F'
+        PUTC    '\r'
+        PUTC    '\n'
+
+/*
+ * Go
+ */
+
+        jmp     start_kernel
+
+/*
+ * Local functions
+ */
+ 
+#ifdef CRT_DEBUG
+putc:
+        moveb   %d7, 0xfffff907
+1:
+        movew   0xfffff906, %d7
+        andw    #0x2000, %d7
+        beq     1b
+        rts
+#endif
diff --git a/arch/m68k/platform/68328/head-pilot.S b/arch/m68k/platform/68328/head-pilot.S
new file mode 100644
index 00000000000..aecff532b34
--- /dev/null
+++ b/arch/m68k/platform/68328/head-pilot.S
@@ -0,0 +1,222 @@
+/*
+ * linux/arch/m68knommu/platform/68328/head-pilot.S
+ * - A startup file for the MC68328
+ *
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ */
+
+#define ASSEMBLY
+
+#define IMMED #
+#define DBG_PUTC(x)     moveb IMMED x, 0xfffff907
+
+
+.global _stext
+.global _start
+
+.global _rambase
+.global _ramvec
+.global _ramstart
+.global _ramend
+
+.global penguin_bits
+
+#ifdef CONFIG_PILOT
+
+#define IMR 0xFFFFF304
+
+        .data
+        .align 16
+
+penguin_bits:   
+#include "bootlogo.rh"
+
+#endif
+
+/*****************************************************************************/
+
+.data
+
+/*
+ *      Set up the usable of RAM stuff. Size of RAM is determined then
+ *      an initial stack set up at the end.
+ */
+.align 4
+_ramvec:
+.long   0
+_rambase:
+.long   0
+_ramstart:
+.long   0
+_ramend:
+.long   0
+
+.text
+        
+_start:
+_stext:
+
+
+#ifdef CONFIG_M68328
+
+#ifdef CONFIG_PILOT
+        .byte 0x4e, 0xfa, 0x00, 0x0a /* Jmp +X bytes */
+        .byte 'b', 'o', 'o', 't'
+        .word 10000
+
+        nop
+#endif
+
+        moveq   #0, %d0
+        movew   %d0, 0xfffff618 /* Watchdog off */
+        movel   #0x00011f07, 0xfffff114 /* CS A1 Mask */
+
+        movew   #0x0800, 0xfffff906 /* Ignore CTS */
+        movew   #0x010b, 0xfffff902 /* BAUD to 9600 */
+
+        movew   #0x2410, 0xfffff200 /* PLLCR */
+        movew   #0x123, 0xfffff202 /* PLLFSR */
+
+#ifdef CONFIG_PILOT
+        moveb   #0, 0xfffffA27 /* LCKCON */
+        movel   #_start, 0xfffffA00 /* LSSA */
+        moveb   #0xa, 0xfffffA05 /* LVPW */
+        movew   #0x9f, 0xFFFFFa08 /* LXMAX */
+        movew   #0x9f, 0xFFFFFa0a /* LYMAX */
+        moveb   #9, 0xfffffa29 /* LBAR */
+        moveb   #0, 0xfffffa25 /* LPXCD */
+        moveb   #0x04, 0xFFFFFa20 /* LPICF */
+        moveb   #0x58, 0xfffffA27 /* LCKCON */
+        moveb   #0x85, 0xfffff429 /* PFDATA */
+        moveb   #0xd8, 0xfffffA27 /* LCKCON */
+        moveb   #0xc5, 0xfffff429 /* PFDATA */
+        moveb   #0xd5, 0xfffff429 /* PFDATA */
+
+        moveal  #0x00100000, %a3
+        moveal  #0x100ffc00, %a4
+#endif /* CONFIG_PILOT */
+
+#endif /* CONFIG_M68328 */
+
+        movew   #0x2700, %sr
+        lea     %a4@(-4), %sp
+
+        DBG_PUTC('\r')
+        DBG_PUTC('\n')
+        DBG_PUTC('A')
+
+        moveq   #0,%d0
+        movew   #16384, %d0  /* PLL settle wait loop */
+L0:
+        subw    #1, %d0
+        bne     L0
+
+        DBG_PUTC('B')
+
+        /* Copy command line from beginning of RAM (+16) to end of bss */
+        movel   #CONFIG_VECTORBASE, %d7
+        addl    #16, %d7
+        moveal  %d7, %a0
+        moveal  #_ebss, %a1
+        lea     %a1@(512), %a2
+
+        DBG_PUTC('C')
+
+        /* Copy %a0 to %a1 until %a1 == %a2 */
+L2:
+        movel   %a0@+, %d0
+        movel   %d0, %a1@+
+        cmpal   %a1, %a2
+        bhi     L2
+
+        /* Copy data+init segment from ROM to RAM */
+        moveal  #_etext, %a0
+        moveal  #_sdata, %a1
+        moveal  #__init_end, %a2
+
+        DBG_PUTC('D')
+
+        /* Copy %a0 to %a1 until %a1 == %a2 */
+LD1:
+        movel   %a0@+, %d0
+        movel   %d0, %a1@+
+        cmpal   %a1, %a2
+        bhi     LD1
+
+        DBG_PUTC('E')
+
+        moveal  #_sbss, %a0
+        moveal  #_ebss, %a1
+
+        /* Copy 0 to %a0 until %a0 == %a1 */
+L1:
+        movel   #0, %a0@+
+        cmpal   %a0, %a1
+        bhi     L1
+
+        DBG_PUTC('F')
+
+        /* Copy command line from end of bss to command line */
+        moveal  #_ebss, %a0
+        moveal  #command_line, %a1
+        lea     %a1@(512), %a2
+
+        DBG_PUTC('G')
+
+        /* Copy %a0 to %a1 until %a1 == %a2 */
+L3:
+        movel   %a0@+, %d0
+        movel   %d0, %a1@+
+        cmpal   %a1, %a2
+        bhi     L3
+
+        movel   #_sdata, %d0    
+        movel   %d0, _rambase   
+        movel   #_ebss, %d0
+        movel   %d0, _ramstart
+
+        movel   %a4, %d0
+        subl    #4096, %d0      /* Reserve 4K of stack */
+        moveq   #79, %d7
+        movel   %d0, _ramend
+
+        movel   %a3, %d0
+        movel   %d0, rom_length
+
+        pea     0
+        pea     env
+        pea     %sp@(4)
+        pea     0
+
+        DBG_PUTC('H')
+
+#ifdef CONFIG_PILOT
+        movel   #penguin_bits, 0xFFFFFA00
+        moveb   #10, 0xFFFFFA05
+        movew   #160, 0xFFFFFA08
+        movew   #160, 0xFFFFFA0A
+#endif /* CONFIG_PILOT */
+
+        DBG_PUTC('I')
+
+        lea     init_thread_union, %a0
+        lea     0x2000(%a0), %sp
+
+        DBG_PUTC('J')
+        DBG_PUTC('\r')
+        DBG_PUTC('\n')
+
+        jsr     start_kernel
+_exit:
+
+        jmp     _exit
+
+
+        .data
+env:
+        .long   0
diff --git a/arch/m68k/platform/68328/head-ram.S b/arch/m68k/platform/68328/head-ram.S
new file mode 100644
index 00000000000..7f1aeeacb21
--- /dev/null
+++ b/arch/m68k/platform/68328/head-ram.S
@@ -0,0 +1,141 @@
+
+        .global __main
+        .global __rom_start
+
+        .global _rambase
+        .global _ramstart
+        
+        .global splash_bits
+        .global _start
+        .global _stext
+        .global _edata
+
+#define DEBUG
+#define ROM_OFFSET 0x10C00000
+#define STACK_GAURD 0x10
+
+        .text
+        
+_start:
+_stext:
+        movew   #0x2700, %sr            /* Exceptions off! */
+
+#if 0
+        /* Init chip registers.  uCsimm specific */
+        moveb   #0x00,   0xfffffb0b     /* Watchdog off */
+        moveb   #0x10,   0xfffff000     /* SCR */
+
+        movew   #0x2400, 0xfffff200     /* PLLCR */
+        movew   #0x0123, 0xfffff202     /* PLLFSR */
+
+        moveb   #0x00,   0xfffff40b     /* enable chip select */
+        moveb   #0x00,   0xfffff423     /* enable /DWE */
+        moveb   #0x08,   0xfffffd0d     /* disable hardmap */
+        moveb   #0x07,   0xfffffd0e     /* level 7 interrupt clear */
+
+        movew   #0x8600, 0xfffff100     /* FLASH at 0x10c00000 */
+        movew   #0x018b, 0xfffff110     /* 2Meg, enable, 0ws */
+
+        movew   #0x8f00, 0xfffffc00     /* DRAM configuration */
+        movew   #0x9667, 0xfffffc02     /* DRAM control */
+        movew   #0x0000, 0xfffff106     /* DRAM at 0x00000000 */
+        movew   #0x068f, 0xfffff116     /* 8Meg, enable, 0ws */
+
+        moveb   #0x40,   0xfffff300     /* IVR */
+        movel   #0x007FFFFF, %d0        /* IMR */
+        movel   %d0,     0xfffff304
+
+        moveb   0xfffff42b, %d0
+        andb    #0xe0,   %d0
+        moveb   %d0,     0xfffff42b
+
+        moveb   #0x08,   0xfffff907     /* Ignore CTS */
+        movew   #0x010b, 0xfffff902     /* BAUD to 9600 */
+        movew   #0xe100, 0xfffff900     /* enable */
+#endif
+
+        movew   #16384, %d0  /* PLL settle wait loop */
+L0:
+        subw    #1, %d0
+        bne     L0
+#ifdef DEBUG
+        moveq   #70, %d7                /* 'F' */
+        moveb   %d7,0xfffff907          /* No absolute addresses */
+pclp1:
+        movew   0xfffff906, %d7
+        andw    #0x2000, %d7
+        beq     pclp1
+#endif /* DEBUG */
+
+#ifdef DEBUG
+        moveq   #82, %d7                /* 'R' */
+        moveb   %d7,0xfffff907          /* No absolute addresses */
+pclp3:
+        movew   0xfffff906, %d7
+        andw    #0x2000, %d7
+        beq     pclp3
+#endif /* DEBUG */
+        moveal  #0x007ffff0, %ssp
+        moveal  #_sbss, %a0
+        moveal  #_ebss, %a1
+
+        /* Copy 0 to %a0 until %a0 >= %a1 */
+L1:
+        movel   #0, %a0@+
+        cmpal   %a0, %a1
+        bhi     L1
+
+#ifdef DEBUG
+        moveq   #67, %d7                /* 'C' */
+        jsr     putc
+#endif /* DEBUG */
+
+        pea     0
+        pea     env
+        pea     %sp@(4)
+        pea     0
+
+#ifdef DEBUG
+        moveq   #70, %d7                /* 'F' */
+        jsr     putc
+#endif /* DEBUG */
+
+lp:
+        jsr     start_kernel
+        jmp lp
+_exit:
+
+        jmp     _exit
+
+__main:
+        /* nothing */
+        rts
+
+#ifdef DEBUG
+putc:
+        moveb   %d7,0xfffff907
+pclp:
+        movew   0xfffff906, %d7
+        andw    #0x2000, %d7
+        beq     pclp
+        rts
+#endif /* DEBUG */
+
+        .data
+
+/*
+ *      Set up the usable of RAM stuff. Size of RAM is determined then
+ *      an initial stack set up at the end.
+ */
+.align 4
+_ramvec:
+.long   0
+_rambase:
+.long   0
+_ramstart:
+.long   0
+_ramend:
+.long   0
+
+env:
+        .long   0
diff --git a/arch/m68k/platform/68328/head-rom.S b/arch/m68k/platform/68328/head-rom.S
new file mode 100644
index 00000000000..6ec77d3ea0b
--- /dev/null
+++ b/arch/m68k/platform/68328/head-rom.S
@@ -0,0 +1,110 @@
+        
+        .global _start
+        .global _stext
+
+        .global _rambase
+        .global _ramvec
+        .global _ramstart
+        .global _ramend
+
+#ifdef CONFIG_INIT_LCD
+        .global splash_bits
+#endif
+
+        .data
+
+/*
+ *      Set up the usable of RAM stuff. Size of RAM is determined then
+ *      an initial stack set up at the end.
+ */
+.align 4
+_ramvec:
+.long   0
+_rambase:
+.long   0
+_ramstart:
+.long   0
+_ramend:
+.long   0
+
+#define RAMEND  (CONFIG_RAMBASE + CONFIG_RAMSIZE)
+
+#ifdef CONFIG_INIT_LCD
+splash_bits:
+#include "bootlogo.rh"
+#endif
+        
+        .text
+_start:
+_stext: movew   #0x2700,%sr
+#ifdef CONFIG_INIT_LCD
+        movel   #splash_bits, 0xfffffA00 /* LSSA */
+        moveb   #0x28,   0xfffffA05     /* LVPW */
+        movew   #0x280,  0xFFFFFa08     /* LXMAX */
+        movew   #0x1df,  0xFFFFFa0a     /* LYMAX */
+        moveb   #0,      0xfffffa29     /* LBAR */
+        moveb   #0,      0xfffffa25     /* LPXCD */
+        moveb   #0x08,   0xFFFFFa20     /* LPICF */
+        moveb   #0x01,   0xFFFFFA21     /* -ve pol */
+        moveb   #0x81,   0xfffffA27     /* LCKCON */
+        movew   #0xff00, 0xfffff412     /* LCD pins */
+#endif
+        moveal  #RAMEND-CONFIG_MEMORY_RESERVE*0x100000 - 0x10, %sp
+        movew   #32767, %d0  /* PLL settle wait loop */
+1:      subq    #1, %d0
+        bne     1b
+
+        /* Copy data segment from ROM to RAM */
+        moveal  #_etext, %a0
+        moveal  #_sdata, %a1
+        moveal  #_edata, %a2
+
+        /* Copy %a0 to %a1 until %a1 == %a2 */
+1:      movel   %a0@+, %a1@+
+        cmpal   %a1, %a2
+        bhi     1b
+
+        moveal  #_sbss, %a0
+        moveal  #_ebss, %a1
+        /* Copy 0 to %a0 until %a0 == %a1 */
+        
+1:
+        clrl    %a0@+
+        cmpal   %a0, %a1
+        bhi     1b
+
+        movel   #_sdata, %d0    
+        movel   %d0, _rambase        
+        movel   #_ebss, %d0
+        movel   %d0, _ramstart
+        movel   #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0
+        movel   %d0, _ramend
+        movel   #CONFIG_VECTORBASE,     %d0
+        movel   %d0, _ramvec
+        
+/*
+ * load the current task pointer and stack
+ */
+        lea     init_thread_union, %a0
+        lea     0x2000(%a0), %sp
+
+1:      jsr     start_kernel
+        bra 1b
+_exit:
+
+        jmp     _exit
+
+
+putc:
+        moveb   %d7,0xfffff907
+1:
+        movew   0xfffff906, %d7
+        andw    #0x2000, %d7
+        beq     1b
+        rts
+
+        .data
+env:
+        .long   0
+        .text
+
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c
new file mode 100644
index 00000000000..4bd456531f9
--- /dev/null
+++ b/arch/m68k/platform/68328/ints.c
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/m68knommu/platform/68328/ints.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com>
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+
+#if defined(CONFIG_M68328)
+#include <asm/MC68328.h>
+#elif defined(CONFIG_M68EZ328)
+#include <asm/MC68EZ328.h>
+#elif defined(CONFIG_M68VZ328)
+#include <asm/MC68VZ328.h>
+#endif
+
+/* assembler routines */
+asmlinkage void system_call(void);
+asmlinkage void buserr(void);
+asmlinkage void trap(void);
+asmlinkage void trap3(void);
+asmlinkage void trap4(void);
+asmlinkage void trap5(void);
+asmlinkage void trap6(void);
+asmlinkage void trap7(void);
+asmlinkage void trap8(void);
+asmlinkage void trap9(void);
+asmlinkage void trap10(void);
+asmlinkage void trap11(void);
+asmlinkage void trap12(void);
+asmlinkage void trap13(void);
+asmlinkage void trap14(void);
+asmlinkage void trap15(void);
+asmlinkage void trap33(void);
+asmlinkage void trap34(void);
+asmlinkage void trap35(void);
+asmlinkage void trap36(void);
+asmlinkage void trap37(void);
+asmlinkage void trap38(void);
+asmlinkage void trap39(void);
+asmlinkage void trap40(void);
+asmlinkage void trap41(void);
+asmlinkage void trap42(void);
+asmlinkage void trap43(void);
+asmlinkage void trap44(void);
+asmlinkage void trap45(void);
+asmlinkage void trap46(void);
+asmlinkage void trap47(void);
+asmlinkage irqreturn_t bad_interrupt(int, void *);
+asmlinkage irqreturn_t inthandler(void);
+asmlinkage irqreturn_t inthandler1(void);
+asmlinkage irqreturn_t inthandler2(void);
+asmlinkage irqreturn_t inthandler3(void);
+asmlinkage irqreturn_t inthandler4(void);
+asmlinkage irqreturn_t inthandler5(void);
+asmlinkage irqreturn_t inthandler6(void);
+asmlinkage irqreturn_t inthandler7(void);
+
+extern e_vector *_ramvec;
+
+/* The 68k family did not have a good way to determine the source
+ * of interrupts until later in the family.  The EC000 core does
+ * not provide the vector number on the stack, we vector everything
+ * into one vector and look in the blasted mask register...
+ * This code is designed to be fast, almost constant time, not clean!
+ */
+void process_int(int vec, struct pt_regs *fp)
+{
+        int irq;
+        int mask;
+
+        unsigned long pend = ISR;
+
+        while (pend) {
+                if (pend & 0x0000ffff) {
+                        if (pend & 0x000000ff) {
+                                if (pend & 0x0000000f) {
+                                        mask = 0x00000001;
+                                        irq = 0;
+                                } else {
+                                        mask = 0x00000010;
+                                        irq = 4;
+                                }
+                        } else {
+                                if (pend & 0x00000f00) {
+                                        mask = 0x00000100;
+                                        irq = 8;
+                                } else {
+                                        mask = 0x00001000;
+                                        irq = 12;
+                                }
+                        }
+                } else {
+                        if (pend & 0x00ff0000) {
+                                if (pend & 0x000f0000) {
+                                        mask = 0x00010000;
+                                        irq = 16;
+                                } else {
+                                        mask = 0x00100000;
+                                        irq = 20;
+                                }
+                        } else {
+                                if (pend & 0x0f000000) {
+                                        mask = 0x01000000;
+                                        irq = 24;
+                                } else {
+                                        mask = 0x10000000;
+                                        irq = 28;
+                                }
+                        }
+                }
+
+                while (! (mask & pend)) {
+                        mask <<=1;
+                        irq++;
+                }
+
+                do_IRQ(irq, fp);
+                pend &= ~mask;
+        }
+}
+
+static void intc_irq_unmask(struct irq_data *d)
+{
+        IMR &= ~(1 << d->irq);
+}
+
+static void intc_irq_mask(struct irq_data *d)
+{
+        IMR |= (1 << d->irq);
+}
+
+static struct irq_chip intc_irq_chip = {
+        .name           = "M68K-INTC",
+        .irq_mask       = intc_irq_mask,
+        .irq_unmask     = intc_irq_unmask,
+};
+
+/*
+ * This function should be called during kernel startup to initialize
+ * the machine vector table.
+ */
+void __init trap_init(void)
+{
+        int i;
+
+        /* set up the vectors */
+        for (i = 72; i < 256; ++i)
+                _ramvec[i] = (e_vector) bad_interrupt;
+
+        _ramvec[32] = system_call;
+
+        _ramvec[65] = (e_vector) inthandler1;
+        _ramvec[66] = (e_vector) inthandler2;
+        _ramvec[67] = (e_vector) inthandler3;
+        _ramvec[68] = (e_vector) inthandler4;
+        _ramvec[69] = (e_vector) inthandler5;
+        _ramvec[70] = (e_vector) inthandler6;
+        _ramvec[71] = (e_vector) inthandler7;
+}
+
+void __init init_IRQ(void)
+{
+        int i;
+
+        IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
+
+        /* turn off all interrupts */
+        IMR = ~0;
+
+        for (i = 0; (i < NR_IRQS); i++) {
+                irq_set_chip(i, &intc_irq_chip);
+                irq_set_handler(i, handle_level_irq);
+        }
+}
+
diff --git a/arch/m68k/platform/68328/romvec.S b/arch/m68k/platform/68328/romvec.S
new file mode 100644
index 00000000000..31084466eae
--- /dev/null
+++ b/arch/m68k/platform/68328/romvec.S
@@ -0,0 +1,35 @@
+/*
+ * linux/arch/m68knommu/platform/68328/romvec.S
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com>
+ * Copyright 2006 Greg Ungerer <gerg@snapgear.com>
+ */
+
+.global _start
+.global _buserr
+.global trap
+.global system_call
+
+.section .romvec
+
+e_vectors:
+.long CONFIG_RAMBASE+CONFIG_RAMSIZE-4, _start, buserr, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+/* TRAP #0-15 */
+.long system_call, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long trap, trap, trap, trap
+.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c
new file mode 100644
index 00000000000..309f725995b
--- /dev/null
+++ b/arch/m68k/platform/68328/timers.c
@@ -0,0 +1,134 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/68328/timers.c
+ *
+ *  Copyright (C) 1993 Hamish Macdonald
+ *  Copyright (C) 1999 D. Jeff Dionne
+ *  Copyright (C) 2001 Georges Menie, Ken Desmet
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/***************************************************************************/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <asm/setup.h>
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/machdep.h>
+#include <asm/MC68VZ328.h>
+
+/***************************************************************************/
+
+#if defined(CONFIG_DRAGEN2)
+/* with a 33.16 MHz clock, this will give usec resolution to the time functions */
+#define CLOCK_SOURCE    TCTL_CLKSOURCE_SYSCLK
+#define CLOCK_PRE       7
+#define TICKS_PER_JIFFY 41450
+
+#elif defined(CONFIG_XCOPILOT_BUGS)
+/*
+ * The only thing I know is that CLK32 is not available on Xcopilot
+ * I have little idea about what frequency SYSCLK has on Xcopilot.
+ * The values for prescaler and compare registers were simply
+ * taken from the original source
+ */
+#define CLOCK_SOURCE    TCTL_CLKSOURCE_SYSCLK
+#define CLOCK_PRE       2
+#define TICKS_PER_JIFFY 0xd7e4
+
+#else
+/* default to using the 32Khz clock */
+#define CLOCK_SOURCE    TCTL_CLKSOURCE_32KHZ
+#define CLOCK_PRE       31
+#define TICKS_PER_JIFFY 10
+#endif
+
+static u32 m68328_tick_cnt;
+
+/***************************************************************************/
+
+static irqreturn_t hw_tick(int irq, void *dummy)
+{
+        /* Reset Timer1 */
+        TSTAT &= 0;
+
+        m68328_tick_cnt += TICKS_PER_JIFFY;
+        return arch_timer_interrupt(irq, dummy);
+}
+
+/***************************************************************************/
+
+static struct irqaction m68328_timer_irq = {
+        .name    = "timer",
+        .flags   = IRQF_DISABLED | IRQF_TIMER,
+        .handler = hw_tick,
+};
+
+/***************************************************************************/
+
+static cycle_t m68328_read_clk(struct clocksource *cs)
+{
+        unsigned long flags;
+        u32 cycles;
+
+        local_irq_save(flags);
+        cycles = m68328_tick_cnt + TCN;
+        local_irq_restore(flags);
+
+        return cycles;
+}
+
+/***************************************************************************/
+
+static struct clocksource m68328_clk = {
+        .name   = "timer",
+        .rating = 250,
+        .read   = m68328_read_clk,
+        .shift  = 20,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/***************************************************************************/
+
+void hw_timer_init(void)
+{
+        /* disable timer 1 */
+        TCTL = 0;
+
+        /* set ISR */
+        setup_irq(TMR_IRQ_NUM, &m68328_timer_irq);
+
+        /* Restart mode, Enable int, Set clock source */
+        TCTL = TCTL_OM | TCTL_IRQEN | CLOCK_SOURCE;
+        TPRER = CLOCK_PRE;
+        TCMP = TICKS_PER_JIFFY;
+
+        /* Enable timer 1 */
+        TCTL |= TCTL_TEN;
+        m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift);
+        clocksource_register(&m68328_clk);
+}
+
+/***************************************************************************/
+
+void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec)
+{
+        long now = RTCTIME;
+
+        *year = *mon = *day = 1;
+        *hour = (now >> 24) % 24;
+        *min = (now >> 16) % 60;
+        *sec = now % 60;
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile
new file mode 100644
index 00000000000..ee97735a242
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for arch/m68knommu/platform/68EZ328.
+#
+
+obj-y := config.o
+
+extra-y := bootlogo.rh
+
+$(obj)/bootlogo.rh: $(src)/bootlogo.h
+        perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \
+                > $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68EZ328/bootlogo.h
new file mode 100644
index 00000000000..e842bdae583
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/bootlogo.h
@@ -0,0 +1,3204 @@
+#define splash_width 640
+#define splash_height 480
+static unsigned char splash_bits[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  };
diff --git a/arch/m68k/platform/68EZ328/config.c b/arch/m68k/platform/68EZ328/config.c
new file mode 100644
index 00000000000..1be1a16f689
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/config.c
@@ -0,0 +1,76 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/68EZ328/config.c
+ *
+ *  Copyright (C) 1993 Hamish Macdonald
+ *  Copyright (C) 1999 D. Jeff Dionne
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/***************************************************************************/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/machdep.h>
+#include <asm/MC68EZ328.h>
+#ifdef CONFIG_UCSIMM
+#include <asm/bootstd.h>
+#endif
+
+/***************************************************************************/
+
+void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+
+/***************************************************************************/
+
+void m68ez328_reset(void)
+{
+  local_irq_disable();
+  asm volatile (
+    "moveal #0x10c00000, %a0;\n"
+    "moveb #0, 0xFFFFF300;\n"
+    "moveal 0(%a0), %sp;\n"
+    "moveal 4(%a0), %a0;\n"
+    "jmp (%a0);\n"
+    );
+}
+
+/***************************************************************************/
+
+unsigned char *cs8900a_hwaddr;
+static int errno;
+
+#ifdef CONFIG_UCSIMM
+_bsc0(char *, getserialnum)
+_bsc1(unsigned char *, gethwaddr, int, a)
+_bsc1(char *, getbenv, char *, a)
+#endif
+
+void config_BSP(char *command, int len)
+{
+  unsigned char *p;
+
+  printk(KERN_INFO "\n68EZ328 DragonBallEZ support (C) 1999 Rt-Control, Inc\n");
+
+#ifdef CONFIG_UCSIMM
+  printk(KERN_INFO "uCsimm serial string [%s]\n",getserialnum());
+  p = cs8900a_hwaddr = gethwaddr(0);
+  printk(KERN_INFO "uCsimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+         p[0], p[1], p[2], p[3], p[4], p[5]);
+
+  p = getbenv("APPEND");
+  if (p) strcpy(p,command);
+  else command[0] = 0;
+#endif
+ 
+  mach_gettod = m68328_timer_gettod;
+  mach_reset = m68ez328_reset;
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
new file mode 100644
index 00000000000..447ffa0fd7c
--- /dev/null
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -0,0 +1,16 @@
+#
+# Makefile for arch/m68knommu/platform/68VZ328.
+#
+
+obj-y           := config.o
+logo-$(UCDIMM)  := bootlogo.rh
+logo-$(DRAGEN2) := screen.h
+extra-y         := $(logo-y)
+
+$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
+        perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh
+
+$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
+        perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
+
+clean-files := $(obj)/screen.h $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68VZ328/config.c b/arch/m68k/platform/68VZ328/config.c
new file mode 100644
index 00000000000..eabaabe8af3
--- /dev/null
+++ b/arch/m68k/platform/68VZ328/config.c
@@ -0,0 +1,188 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/68VZ328/config.c
+ *
+ *  Copyright (C) 1993 Hamish Macdonald
+ *  Copyright (C) 1999 D. Jeff Dionne
+ *  Copyright (C) 2001 Georges Menie, Ken Desmet
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/***************************************************************************/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/kd.h>
+#include <linux/netdevice.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/machdep.h>
+#include <asm/MC68VZ328.h>
+#include <asm/bootstd.h>
+
+#ifdef CONFIG_INIT_LCD
+#include "bootlogo.h"
+#endif
+
+/***************************************************************************/
+
+void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+
+/***************************************************************************/
+/*                        Init Drangon Engine hardware                     */
+/***************************************************************************/
+#if defined(CONFIG_DRAGEN2)
+
+static void m68vz328_reset(void)
+{
+        local_irq_disable();
+
+#ifdef CONFIG_INIT_LCD
+        PBDATA |= 0x20;                         /* disable CCFL light */
+        PKDATA |= 0x4;                          /* disable LCD controller */
+        LCKCON = 0;
+#endif
+
+        __asm__ __volatile__(
+                "reset\n\t"
+                "moveal #0x04000000, %a0\n\t"
+                "moveal 0(%a0), %sp\n\t"
+                "moveal 4(%a0), %a0\n\t"
+                "jmp (%a0)"
+        );
+}
+
+static void init_hardware(char *command, int size)
+{
+#ifdef CONFIG_DIRECT_IO_ACCESS
+        SCR = 0x10;                                     /* allow user access to internal registers */
+#endif
+
+        /* CSGB Init */
+        CSGBB = 0x4000;
+        CSB = 0x1a1;
+
+        /* CS8900 init */
+        /* PK3: hardware sleep function pin, active low */
+        PKSEL |= PK(3);                         /* select pin as I/O */
+        PKDIR |= PK(3);                         /* select pin as output */
+        PKDATA |= PK(3);                        /* set pin high */
+
+        /* PF5: hardware reset function pin, active high */
+        PFSEL |= PF(5);                         /* select pin as I/O */
+        PFDIR |= PF(5);                         /* select pin as output */
+        PFDATA &= ~PF(5);                       /* set pin low */
+
+        /* cs8900 hardware reset */
+        PFDATA |= PF(5);
+        { int i; for (i = 0; i < 32000; ++i); }
+        PFDATA &= ~PF(5);
+
+        /* INT1 enable (cs8900 IRQ) */
+        PDPOL &= ~PD(1);                        /* active high signal */
+        PDIQEG &= ~PD(1);
+        PDIRQEN |= PD(1);                       /* IRQ enabled */
+
+#ifdef CONFIG_INIT_LCD
+        /* initialize LCD controller */
+        LSSA = (long) screen_bits;
+        LVPW = 0x14;
+        LXMAX = 0x140;
+        LYMAX = 0xef;
+        LRRA = 0;
+        LPXCD = 3;
+        LPICF = 0x08;
+        LPOLCF = 0;
+        LCKCON = 0x80;
+        PCPDEN = 0xff;
+        PCSEL = 0;
+
+        /* Enable LCD controller */
+        PKDIR |= 0x4;
+        PKSEL |= 0x4;
+        PKDATA &= ~0x4;
+
+        /* Enable CCFL backlighting circuit */
+        PBDIR |= 0x20;
+        PBSEL |= 0x20;
+        PBDATA &= ~0x20;
+
+        /* contrast control register */
+        PFDIR |= 0x1;
+        PFSEL &= ~0x1;
+        PWMR = 0x037F;
+#endif
+}
+
+/***************************************************************************/
+/*                      Init RT-Control uCdimm hardware                    */
+/***************************************************************************/
+#elif defined(CONFIG_UCDIMM)
+
+static void m68vz328_reset(void)
+{
+        local_irq_disable();
+        asm volatile (
+                "moveal #0x10c00000, %a0;\n\t"
+                "moveb #0, 0xFFFFF300;\n\t"
+                "moveal 0(%a0), %sp;\n\t"
+                "moveal 4(%a0), %a0;\n\t"
+                "jmp (%a0);\n"
+        );
+}
+
+unsigned char *cs8900a_hwaddr;
+static int errno;
+
+_bsc0(char *, getserialnum)
+_bsc1(unsigned char *, gethwaddr, int, a)
+_bsc1(char *, getbenv, char *, a)
+
+static void init_hardware(char *command, int size)
+{
+        char *p;
+
+        printk(KERN_INFO "uCdimm serial string [%s]\n", getserialnum());
+        p = cs8900a_hwaddr = gethwaddr(0);
+        printk(KERN_INFO "uCdimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+                p[0], p[1], p[2], p[3], p[4], p[5]);
+        p = getbenv("APPEND");
+        if (p)
+                strcpy(p, command);
+        else
+                command[0] = 0;
+}
+
+/***************************************************************************/
+#else
+
+static void m68vz328_reset(void)
+{
+}
+
+static void init_hardware(char *command, int size)
+{
+}
+
+/***************************************************************************/
+#endif
+/***************************************************************************/
+
+void config_BSP(char *command, int size)
+{
+        printk(KERN_INFO "68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n");
+
+        init_hardware(command, size);
+
+        mach_gettod = m68328_timer_gettod;
+        mach_reset = m68vz328_reset;
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c
new file mode 100644
index 00000000000..8c62b825939
--- /dev/null
+++ b/arch/m68k/platform/coldfire/pinmux.c
@@ -0,0 +1,28 @@
+/*
+ * Coldfire generic GPIO pinmux support.
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/pinmux.h>
+
+int mcf_pinmux_request(unsigned pinmux, unsigned func)
+{
+        return 0;
+}
+
+void mcf_pinmux_release(unsigned pinmux, unsigned func)
+{
+}