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-rw-r--r--arch/m68k/platform/527x/Makefile18
-rw-r--r--arch/m68k/platform/527x/config.c384
-rw-r--r--arch/m68k/platform/527x/gpio.c609
3 files changed, 1011 insertions, 0 deletions
diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile
new file mode 100644
index 00000000000..6ac4b57370e
--- /dev/null
+++ b/arch/m68k/platform/527x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
new file mode 100644
index 00000000000..3ebc769cefd
--- /dev/null
+++ b/arch/m68k/platform/527x/config.c
@@ -0,0 +1,384 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/527x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5270/5271 CPUs.
8 *
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
21#include <asm/machdep.h>
22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m527x_uart_platform[] = {
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 },
34 {
35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART1,
37 },
38 {
39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART2,
41 },
42 { },
43};
44
45static struct platform_device m527x_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m527x_uart_platform,
49};
50
51static struct resource m527x_fec0_resources[] = {
52 {
53 .start = MCFFEC_BASE0,
54 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = 64 + 23,
59 .end = 64 + 23,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = 64 + 27,
64 .end = 64 + 27,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = 64 + 29,
69 .end = 64 + 29,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct resource m527x_fec1_resources[] = {
75 {
76 .start = MCFFEC_BASE1,
77 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = 128 + 23,
82 .end = 128 + 23,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .start = 128 + 27,
87 .end = 128 + 27,
88 .flags = IORESOURCE_IRQ,
89 },
90 {
91 .start = 128 + 29,
92 .end = 128 + 29,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device m527x_fec[] = {
98 {
99 .name = "fec",
100 .id = 0,
101 .num_resources = ARRAY_SIZE(m527x_fec0_resources),
102 .resource = m527x_fec0_resources,
103 },
104 {
105 .name = "fec",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(m527x_fec1_resources),
108 .resource = m527x_fec1_resources,
109 },
110};
111
112#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
113static struct resource m527x_qspi_resources[] = {
114 {
115 .start = MCFQSPI_IOBASE,
116 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = MCFINT_VECBASE + MCFINT_QSPI,
121 .end = MCFINT_VECBASE + MCFINT_QSPI,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126#if defined(CONFIG_M5271)
127#define MCFQSPI_CS0 91
128#define MCFQSPI_CS1 92
129#define MCFQSPI_CS2 99
130#define MCFQSPI_CS3 103
131#elif defined(CONFIG_M5275)
132#define MCFQSPI_CS0 59
133#define MCFQSPI_CS1 60
134#define MCFQSPI_CS2 61
135#define MCFQSPI_CS3 62
136#endif
137
138static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
139{
140 int status;
141
142 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
143 if (status) {
144 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
145 goto fail0;
146 }
147 status = gpio_direction_output(MCFQSPI_CS0, 1);
148 if (status) {
149 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
150 goto fail1;
151 }
152
153 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
154 if (status) {
155 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
156 goto fail1;
157 }
158 status = gpio_direction_output(MCFQSPI_CS1, 1);
159 if (status) {
160 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
161 goto fail2;
162 }
163
164 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
165 if (status) {
166 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
167 goto fail2;
168 }
169 status = gpio_direction_output(MCFQSPI_CS2, 1);
170 if (status) {
171 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
172 goto fail3;
173 }
174
175 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
176 if (status) {
177 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
178 goto fail3;
179 }
180 status = gpio_direction_output(MCFQSPI_CS3, 1);
181 if (status) {
182 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
183 goto fail4;
184 }
185
186 return 0;
187
188fail4:
189 gpio_free(MCFQSPI_CS3);
190fail3:
191 gpio_free(MCFQSPI_CS2);
192fail2:
193 gpio_free(MCFQSPI_CS1);
194fail1:
195 gpio_free(MCFQSPI_CS0);
196fail0:
197 return status;
198}
199
200static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
201{
202 gpio_free(MCFQSPI_CS3);
203 gpio_free(MCFQSPI_CS2);
204 gpio_free(MCFQSPI_CS1);
205 gpio_free(MCFQSPI_CS0);
206}
207
208static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
209 u8 chip_select, bool cs_high)
210{
211 switch (chip_select) {
212 case 0:
213 gpio_set_value(MCFQSPI_CS0, cs_high);
214 break;
215 case 1:
216 gpio_set_value(MCFQSPI_CS1, cs_high);
217 break;
218 case 2:
219 gpio_set_value(MCFQSPI_CS2, cs_high);
220 break;
221 case 3:
222 gpio_set_value(MCFQSPI_CS3, cs_high);
223 break;
224 }
225}
226
227static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
228 u8 chip_select, bool cs_high)
229{
230 switch (chip_select) {
231 case 0:
232 gpio_set_value(MCFQSPI_CS0, !cs_high);
233 break;
234 case 1:
235 gpio_set_value(MCFQSPI_CS1, !cs_high);
236 break;
237 case 2:
238 gpio_set_value(MCFQSPI_CS2, !cs_high);
239 break;
240 case 3:
241 gpio_set_value(MCFQSPI_CS3, !cs_high);
242 break;
243 }
244}
245
246static struct mcfqspi_cs_control m527x_cs_control = {
247 .setup = m527x_cs_setup,
248 .teardown = m527x_cs_teardown,
249 .select = m527x_cs_select,
250 .deselect = m527x_cs_deselect,
251};
252
253static struct mcfqspi_platform_data m527x_qspi_data = {
254 .bus_num = 0,
255 .num_chipselect = 4,
256 .cs_control = &m527x_cs_control,
257};
258
259static struct platform_device m527x_qspi = {
260 .name = "mcfqspi",
261 .id = 0,
262 .num_resources = ARRAY_SIZE(m527x_qspi_resources),
263 .resource = m527x_qspi_resources,
264 .dev.platform_data = &m527x_qspi_data,
265};
266
267static void __init m527x_qspi_init(void)
268{
269#if defined(CONFIG_M5271)
270 u16 par;
271
272 /* setup QSPS pins for QSPI with gpio CS control */
273 writeb(0x1f, MCFGPIO_PAR_QSPI);
274 /* and CS2 & CS3 as gpio */
275 par = readw(MCFGPIO_PAR_TIMER);
276 par &= 0x3f3f;
277 writew(par, MCFGPIO_PAR_TIMER);
278#elif defined(CONFIG_M5275)
279 /* setup QSPS pins for QSPI with gpio CS control */
280 writew(0x003e, MCFGPIO_PAR_QSPI);
281#endif
282}
283#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
284
285static struct platform_device *m527x_devices[] __initdata = {
286 &m527x_uart,
287 &m527x_fec[0],
288#ifdef CONFIG_FEC2
289 &m527x_fec[1],
290#endif
291#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
292 &m527x_qspi,
293#endif
294};
295
296/***************************************************************************/
297
298static void __init m527x_uart_init_line(int line, int irq)
299{
300 u16 sepmask;
301
302 if ((line < 0) || (line > 2))
303 return;
304
305 /*
306 * External Pin Mask Setting & Enable External Pin for Interface
307 */
308 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
309 if (line == 0)
310 sepmask |= UART0_ENABLE_MASK;
311 else if (line == 1)
312 sepmask |= UART1_ENABLE_MASK;
313 else if (line == 2)
314 sepmask |= UART2_ENABLE_MASK;
315 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
316}
317
318static void __init m527x_uarts_init(void)
319{
320 const int nrlines = ARRAY_SIZE(m527x_uart_platform);
321 int line;
322
323 for (line = 0; (line < nrlines); line++)
324 m527x_uart_init_line(line, m527x_uart_platform[line].irq);
325}
326
327/***************************************************************************/
328
329static void __init m527x_fec_init(void)
330{
331 u16 par;
332 u8 v;
333
334 /* Set multi-function pins to ethernet mode for fec0 */
335#if defined(CONFIG_M5271)
336 v = readb(MCF_IPSBAR + 0x100047);
337 writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
338#else
339 par = readw(MCF_IPSBAR + 0x100082);
340 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
341 v = readb(MCF_IPSBAR + 0x100078);
342 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
343#endif
344
345#ifdef CONFIG_FEC2
346 /* Set multi-function pins to ethernet mode for fec1 */
347 par = readw(MCF_IPSBAR + 0x100082);
348 writew(par | 0xa0, MCF_IPSBAR + 0x100082);
349 v = readb(MCF_IPSBAR + 0x100079);
350 writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
351#endif
352}
353
354/***************************************************************************/
355
356static void m527x_cpu_reset(void)
357{
358 local_irq_disable();
359 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
360}
361
362/***************************************************************************/
363
364void __init config_BSP(char *commandp, int size)
365{
366 mach_reset = m527x_cpu_reset;
367 m527x_uarts_init();
368 m527x_fec_init();
369#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
370 m527x_qspi_init();
371#endif
372}
373
374/***************************************************************************/
375
376static int __init init_BSP(void)
377{
378 platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
379 return 0;
380}
381
382arch_initcall(init_BSP);
383
384/***************************************************************************/
diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c
new file mode 100644
index 00000000000..205da0aa0f2
--- /dev/null
+++ b/arch/m68k/platform/527x/gpio.c
@@ -0,0 +1,609 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24#if defined(CONFIG_M5271)
25 {
26 .gpio_chip = {
27 .label = "PIRQ",
28 .request = mcf_gpio_request,
29 .free = mcf_gpio_free,
30 .direction_input = mcf_gpio_direction_input,
31 .direction_output = mcf_gpio_direction_output,
32 .get = mcf_gpio_get_value,
33 .set = mcf_gpio_set_value,
34 .base = 1,
35 .ngpio = 7,
36 },
37 .pddr = (void __iomem *) MCFEPORT_EPDDR,
38 .podr = (void __iomem *) MCFEPORT_EPDR,
39 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
40 },
41 {
42 .gpio_chip = {
43 .label = "ADDR",
44 .request = mcf_gpio_request,
45 .free = mcf_gpio_free,
46 .direction_input = mcf_gpio_direction_input,
47 .direction_output = mcf_gpio_direction_output,
48 .get = mcf_gpio_get_value,
49 .set = mcf_gpio_set_value_fast,
50 .base = 13,
51 .ngpio = 3,
52 },
53 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
54 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
55 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
57 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
58 },
59 {
60 .gpio_chip = {
61 .label = "DATAH",
62 .request = mcf_gpio_request,
63 .free = mcf_gpio_free,
64 .direction_input = mcf_gpio_direction_input,
65 .direction_output = mcf_gpio_direction_output,
66 .get = mcf_gpio_get_value,
67 .set = mcf_gpio_set_value_fast,
68 .base = 16,
69 .ngpio = 8,
70 },
71 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
72 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
73 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
75 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
76 },
77 {
78 .gpio_chip = {
79 .label = "DATAL",
80 .request = mcf_gpio_request,
81 .free = mcf_gpio_free,
82 .direction_input = mcf_gpio_direction_input,
83 .direction_output = mcf_gpio_direction_output,
84 .get = mcf_gpio_get_value,
85 .set = mcf_gpio_set_value_fast,
86 .base = 24,
87 .ngpio = 8,
88 },
89 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
90 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
91 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
93 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
94 },
95 {
96 .gpio_chip = {
97 .label = "BUSCTL",
98 .request = mcf_gpio_request,
99 .free = mcf_gpio_free,
100 .direction_input = mcf_gpio_direction_input,
101 .direction_output = mcf_gpio_direction_output,
102 .get = mcf_gpio_get_value,
103 .set = mcf_gpio_set_value_fast,
104 .base = 32,
105 .ngpio = 8,
106 },
107 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
108 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
109 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
111 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
112 },
113 {
114 .gpio_chip = {
115 .label = "BS",
116 .request = mcf_gpio_request,
117 .free = mcf_gpio_free,
118 .direction_input = mcf_gpio_direction_input,
119 .direction_output = mcf_gpio_direction_output,
120 .get = mcf_gpio_get_value,
121 .set = mcf_gpio_set_value_fast,
122 .base = 40,
123 .ngpio = 4,
124 },
125 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
126 .podr = (void __iomem *) MCFGPIO_PODR_BS,
127 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
129 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
130 },
131 {
132 .gpio_chip = {
133 .label = "CS",
134 .request = mcf_gpio_request,
135 .free = mcf_gpio_free,
136 .direction_input = mcf_gpio_direction_input,
137 .direction_output = mcf_gpio_direction_output,
138 .get = mcf_gpio_get_value,
139 .set = mcf_gpio_set_value_fast,
140 .base = 49,
141 .ngpio = 7,
142 },
143 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
144 .podr = (void __iomem *) MCFGPIO_PODR_CS,
145 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
147 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
148 },
149 {
150 .gpio_chip = {
151 .label = "SDRAM",
152 .request = mcf_gpio_request,
153 .free = mcf_gpio_free,
154 .direction_input = mcf_gpio_direction_input,
155 .direction_output = mcf_gpio_direction_output,
156 .get = mcf_gpio_get_value,
157 .set = mcf_gpio_set_value_fast,
158 .base = 56,
159 .ngpio = 6,
160 },
161 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
162 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
163 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
165 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
166 },
167 {
168 .gpio_chip = {
169 .label = "FECI2C",
170 .request = mcf_gpio_request,
171 .free = mcf_gpio_free,
172 .direction_input = mcf_gpio_direction_input,
173 .direction_output = mcf_gpio_direction_output,
174 .get = mcf_gpio_get_value,
175 .set = mcf_gpio_set_value_fast,
176 .base = 64,
177 .ngpio = 4,
178 },
179 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
180 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
181 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
183 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
184 },
185 {
186 .gpio_chip = {
187 .label = "UARTH",
188 .request = mcf_gpio_request,
189 .free = mcf_gpio_free,
190 .direction_input = mcf_gpio_direction_input,
191 .direction_output = mcf_gpio_direction_output,
192 .get = mcf_gpio_get_value,
193 .set = mcf_gpio_set_value_fast,
194 .base = 72,
195 .ngpio = 2,
196 },
197 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
198 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
199 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
201 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
202 },
203 {
204 .gpio_chip = {
205 .label = "UARTL",
206 .request = mcf_gpio_request,
207 .free = mcf_gpio_free,
208 .direction_input = mcf_gpio_direction_input,
209 .direction_output = mcf_gpio_direction_output,
210 .get = mcf_gpio_get_value,
211 .set = mcf_gpio_set_value_fast,
212 .base = 80,
213 .ngpio = 8,
214 },
215 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
216 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
217 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
219 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
220 },
221 {
222 .gpio_chip = {
223 .label = "QSPI",
224 .request = mcf_gpio_request,
225 .free = mcf_gpio_free,
226 .direction_input = mcf_gpio_direction_input,
227 .direction_output = mcf_gpio_direction_output,
228 .get = mcf_gpio_get_value,
229 .set = mcf_gpio_set_value_fast,
230 .base = 88,
231 .ngpio = 5,
232 },
233 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
234 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
235 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
237 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
238 },
239 {
240 .gpio_chip = {
241 .label = "TIMER",
242 .request = mcf_gpio_request,
243 .free = mcf_gpio_free,
244 .direction_input = mcf_gpio_direction_input,
245 .direction_output = mcf_gpio_direction_output,
246 .get = mcf_gpio_get_value,
247 .set = mcf_gpio_set_value_fast,
248 .base = 96,
249 .ngpio = 8,
250 },
251 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
252 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
253 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
255 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
256 },
257#elif defined(CONFIG_M5275)
258 {
259 .gpio_chip = {
260 .label = "PIRQ",
261 .request = mcf_gpio_request,
262 .free = mcf_gpio_free,
263 .direction_input = mcf_gpio_direction_input,
264 .direction_output = mcf_gpio_direction_output,
265 .get = mcf_gpio_get_value,
266 .set = mcf_gpio_set_value,
267 .base = 1,
268 .ngpio = 7,
269 },
270 .pddr = (void __iomem *) MCFEPORT_EPDDR,
271 .podr = (void __iomem *) MCFEPORT_EPDR,
272 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
273 },
274 {
275 .gpio_chip = {
276 .label = "BUSCTL",
277 .request = mcf_gpio_request,
278 .free = mcf_gpio_free,
279 .direction_input = mcf_gpio_direction_input,
280 .direction_output = mcf_gpio_direction_output,
281 .get = mcf_gpio_get_value,
282 .set = mcf_gpio_set_value_fast,
283 .base = 8,
284 .ngpio = 8,
285 },
286 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
287 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
288 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
289 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
290 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
291 },
292 {
293 .gpio_chip = {
294 .label = "ADDR",
295 .request = mcf_gpio_request,
296 .free = mcf_gpio_free,
297 .direction_input = mcf_gpio_direction_input,
298 .direction_output = mcf_gpio_direction_output,
299 .get = mcf_gpio_get_value,
300 .set = mcf_gpio_set_value_fast,
301 .base = 21,
302 .ngpio = 3,
303 },
304 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
305 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
306 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
307 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
308 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
309 },
310 {
311 .gpio_chip = {
312 .label = "CS",
313 .request = mcf_gpio_request,
314 .free = mcf_gpio_free,
315 .direction_input = mcf_gpio_direction_input,
316 .direction_output = mcf_gpio_direction_output,
317 .get = mcf_gpio_get_value,
318 .set = mcf_gpio_set_value_fast,
319 .base = 25,
320 .ngpio = 7,
321 },
322 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
323 .podr = (void __iomem *) MCFGPIO_PODR_CS,
324 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
325 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
326 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
327 },
328 {
329 .gpio_chip = {
330 .label = "FEC0H",
331 .request = mcf_gpio_request,
332 .free = mcf_gpio_free,
333 .direction_input = mcf_gpio_direction_input,
334 .direction_output = mcf_gpio_direction_output,
335 .get = mcf_gpio_get_value,
336 .set = mcf_gpio_set_value_fast,
337 .base = 32,
338 .ngpio = 8,
339 },
340 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H,
341 .podr = (void __iomem *) MCFGPIO_PODR_FEC0H,
342 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
343 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
344 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
345 },
346 {
347 .gpio_chip = {
348 .label = "FEC0L",
349 .request = mcf_gpio_request,
350 .free = mcf_gpio_free,
351 .direction_input = mcf_gpio_direction_input,
352 .direction_output = mcf_gpio_direction_output,
353 .get = mcf_gpio_get_value,
354 .set = mcf_gpio_set_value_fast,
355 .base = 40,
356 .ngpio = 8,
357 },
358 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L,
359 .podr = (void __iomem *) MCFGPIO_PODR_FEC0L,
360 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
361 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
362 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
363 },
364 {
365 .gpio_chip = {
366 .label = "FECI2C",
367 .request = mcf_gpio_request,
368 .free = mcf_gpio_free,
369 .direction_input = mcf_gpio_direction_input,
370 .direction_output = mcf_gpio_direction_output,
371 .get = mcf_gpio_get_value,
372 .set = mcf_gpio_set_value_fast,
373 .base = 48,
374 .ngpio = 6,
375 },
376 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
377 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
378 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
379 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
380 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
381 },
382 {
383 .gpio_chip = {
384 .label = "QSPI",
385 .request = mcf_gpio_request,
386 .free = mcf_gpio_free,
387 .direction_input = mcf_gpio_direction_input,
388 .direction_output = mcf_gpio_direction_output,
389 .get = mcf_gpio_get_value,
390 .set = mcf_gpio_set_value_fast,
391 .base = 56,
392 .ngpio = 7,
393 },
394 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
395 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
396 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
397 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
398 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
399 },
400 {
401 .gpio_chip = {
402 .label = "SDRAM",
403 .request = mcf_gpio_request,
404 .free = mcf_gpio_free,
405 .direction_input = mcf_gpio_direction_input,
406 .direction_output = mcf_gpio_direction_output,
407 .get = mcf_gpio_get_value,
408 .set = mcf_gpio_set_value_fast,
409 .base = 64,
410 .ngpio = 8,
411 },
412 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
413 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
414 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
415 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
416 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
417 },
418 {
419 .gpio_chip = {
420 .label = "TIMERH",
421 .request = mcf_gpio_request,
422 .free = mcf_gpio_free,
423 .direction_input = mcf_gpio_direction_input,
424 .direction_output = mcf_gpio_direction_output,
425 .get = mcf_gpio_get_value,
426 .set = mcf_gpio_set_value_fast,
427 .base = 72,
428 .ngpio = 4,
429 },
430 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH,
431 .podr = (void __iomem *) MCFGPIO_PODR_TIMERH,
432 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
433 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
434 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
435 },
436 {
437 .gpio_chip = {
438 .label = "TIMERL",
439 .request = mcf_gpio_request,
440 .free = mcf_gpio_free,
441 .direction_input = mcf_gpio_direction_input,
442 .direction_output = mcf_gpio_direction_output,
443 .get = mcf_gpio_get_value,
444 .set = mcf_gpio_set_value_fast,
445 .base = 80,
446 .ngpio = 4,
447 },
448 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL,
449 .podr = (void __iomem *) MCFGPIO_PODR_TIMERL,
450 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
451 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
452 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
453 },
454 {
455 .gpio_chip = {
456 .label = "UARTL",
457 .request = mcf_gpio_request,
458 .free = mcf_gpio_free,
459 .direction_input = mcf_gpio_direction_input,
460 .direction_output = mcf_gpio_direction_output,
461 .get = mcf_gpio_get_value,
462 .set = mcf_gpio_set_value_fast,
463 .base = 88,
464 .ngpio = 8,
465 },
466 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
467 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
468 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
469 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
470 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
471 },
472 {
473 .gpio_chip = {
474 .label = "FEC1H",
475 .request = mcf_gpio_request,
476 .free = mcf_gpio_free,
477 .direction_input = mcf_gpio_direction_input,
478 .direction_output = mcf_gpio_direction_output,
479 .get = mcf_gpio_get_value,
480 .set = mcf_gpio_set_value_fast,
481 .base = 96,
482 .ngpio = 8,
483 },
484 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H,
485 .podr = (void __iomem *) MCFGPIO_PODR_FEC1H,
486 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
487 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
488 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
489 },
490 {
491 .gpio_chip = {
492 .label = "FEC1L",
493 .request = mcf_gpio_request,
494 .free = mcf_gpio_free,
495 .direction_input = mcf_gpio_direction_input,
496 .direction_output = mcf_gpio_direction_output,
497 .get = mcf_gpio_get_value,
498 .set = mcf_gpio_set_value_fast,
499 .base = 104,
500 .ngpio = 8,
501 },
502 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L,
503 .podr = (void __iomem *) MCFGPIO_PODR_FEC1L,
504 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
505 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
506 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
507 },
508 {
509 .gpio_chip = {
510 .label = "BS",
511 .request = mcf_gpio_request,
512 .free = mcf_gpio_free,
513 .direction_input = mcf_gpio_direction_input,
514 .direction_output = mcf_gpio_direction_output,
515 .get = mcf_gpio_get_value,
516 .set = mcf_gpio_set_value_fast,
517 .base = 114,
518 .ngpio = 2,
519 },
520 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
521 .podr = (void __iomem *) MCFGPIO_PODR_BS,
522 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
523 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
524 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
525 },
526 {
527 .gpio_chip = {
528 .label = "IRQ",
529 .request = mcf_gpio_request,
530 .free = mcf_gpio_free,
531 .direction_input = mcf_gpio_direction_input,
532 .direction_output = mcf_gpio_direction_output,
533 .get = mcf_gpio_get_value,
534 .set = mcf_gpio_set_value_fast,
535 .base = 121,
536 .ngpio = 7,
537 },
538 .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ,
539 .podr = (void __iomem *) MCFGPIO_PODR_IRQ,
540 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
541 .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
542 .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ,
543 },
544 {
545 .gpio_chip = {
546 .label = "USBH",
547 .request = mcf_gpio_request,
548 .free = mcf_gpio_free,
549 .direction_input = mcf_gpio_direction_input,
550 .direction_output = mcf_gpio_direction_output,
551 .get = mcf_gpio_get_value,
552 .set = mcf_gpio_set_value_fast,
553 .base = 128,
554 .ngpio = 1,
555 },
556 .pddr = (void __iomem *) MCFGPIO_PDDR_USBH,
557 .podr = (void __iomem *) MCFGPIO_PODR_USBH,
558 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
559 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
560 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH,
561 },
562 {
563 .gpio_chip = {
564 .label = "USBL",
565 .request = mcf_gpio_request,
566 .free = mcf_gpio_free,
567 .direction_input = mcf_gpio_direction_input,
568 .direction_output = mcf_gpio_direction_output,
569 .get = mcf_gpio_get_value,
570 .set = mcf_gpio_set_value_fast,
571 .base = 136,
572 .ngpio = 8,
573 },
574 .pddr = (void __iomem *) MCFGPIO_PDDR_USBL,
575 .podr = (void __iomem *) MCFGPIO_PODR_USBL,
576 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
577 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
578 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL,
579 },
580 {
581 .gpio_chip = {
582 .label = "UARTH",
583 .request = mcf_gpio_request,
584 .free = mcf_gpio_free,
585 .direction_input = mcf_gpio_direction_input,
586 .direction_output = mcf_gpio_direction_output,
587 .get = mcf_gpio_get_value,
588 .set = mcf_gpio_set_value_fast,
589 .base = 144,
590 .ngpio = 4,
591 },
592 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
593 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
594 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
595 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
596 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
597 },
598#endif
599};
600
601static int __init mcf_gpio_init(void)
602{
603 unsigned i = 0;
604 while (i < ARRAY_SIZE(mcf_gpio_chips))
605 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
606 return 0;
607}
608
609core_initcall(mcf_gpio_init);
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-22 13:02:54 -0400