15 files changed, 499 insertions, 1562 deletions

diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7cafb537d03..d2b3935ae14 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
 {
 #ifdef CACHE_INVALIDATE
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATE) : "d0" );
+                : : "r" (CACHE_INVALIDATE) );
 #endif
 }
 
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
 {
 #ifdef CACHE_INVALIDATEI
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATEI) : "d0" );
+                : : "r" (CACHE_INVALIDATEI) );
 #endif
 }
 
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
 #endif
 #ifdef CACHE_INVALIDATED
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATED) : "d0" );
+                : : "r" (CACHE_INVALIDATED) );
 #else
-        /* Flush the wrtite buffer */
+        /* Flush the write buffer */
         __asm__ __volatile__ ( "nop" );
 #endif
 }
 
 /*
  * Push cache entries at supplied address. We want to write back any dirty
- * data and the invalidate the cache lines associated with this address.
+ * data and then invalidate the cache lines associated with this address.
  */
 static inline void cache_push(unsigned long paddr, int len)
 {
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b08..4cf864f5ea7 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
 /*
  *      Define the 5206 SIM register set addresses.
  */
-#define MCFSIM_SIMR             0x03            /* SIM Config reg (r/w) */
-#define MCFSIM_ICR1             0x14            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x15            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x16            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x17            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x18            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x19            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x1a            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x1b            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x1c            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x1d            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x1e            /* Intr Ctrl reg 11 (r/w) */
-#define MCFSIM_ICR12            0x1f            /* Intr Ctrl reg 12 (r/w) */
-#define MCFSIM_ICR13            0x20            /* Intr Ctrl reg 13 (r/w) */
+#define MCFSIM_SIMR             (MCF_MBAR + 0x03)       /* SIM Config reg */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x14)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x15)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x16)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x17)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x18)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x19)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x1a)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x1b)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x1c)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x1d)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x1e)       /* Intr Ctrl reg 11 */
+#define MCFSIM_ICR12            (MCF_MBAR + 0x1f)       /* Intr Ctrl reg 12 */
+#define MCFSIM_ICR13            (MCF_MBAR + 0x20)       /* Intr Ctrl reg 13 */
 #ifdef CONFIG_M5206e
-#define MCFSIM_ICR14            0x21            /* Intr Ctrl reg 14 (r/w) */
-#define MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
+#define MCFSIM_ICR14            (MCF_MBAR + 0x21)       /* Intr Ctrl reg 14 */
+#define MCFSIM_ICR15            (MCF_MBAR + 0x22)       /* Intr Ctrl reg 15 */
 #endif
 
-#define MCFSIM_IMR              0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR              0x3a            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
+#define MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
-#define MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
+#define MCFSIM_RSR              (MCF_MBAR + 0x40)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x41)       /* System Protection */
 
-#define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x42)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x43)       /* SW Watchdog srv */
 
 #define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
 #define MCFSIM_DCTR             (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@
 #define MCFSIM_DMR1             (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
 #define MCFSIM_DCR1             (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 
-#define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x6e            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x70            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x74            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x7a            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x7c            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x80            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0x86            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0x88            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0x8c            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0x92            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0x94            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0x98            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0x9e            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xa0            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xa4            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xaa            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xac            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xb0            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xb6            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xb8            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xbc            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xc2            /* CS 7 Control reg (r/w) */
-#define MCFSIM_DMCR             0xc6            /* Default control */
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x64)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x68)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x6e)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x70)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x74)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x7a)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x7c)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x80)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0x86)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0x88)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0x8c)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0x92)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0x94)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0x98)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0x9e)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xa0)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xa4)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xaa)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xac)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xb0)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xb6)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xb8)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xbc)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xc2)       /* CS 7 Control reg */
+#define MCFSIM_DMCR             (MCF_MBAR + 0xc6)       /* Default control */
 
 #ifdef CONFIG_M5206e
-#define MCFSIM_PAR              0xca            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xca)       /* Pin Assignment */
 #else
-#define MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
+#define MCFSIM_PAR              (MCF_MBAR + 0xcb)       /* Pin Assignment */
 #endif
 
 #define MCFTIMER_BASE1          (MCF_MBAR + 0x100)      /* Base of TIMER1 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 91d3abc3f2a..5e06b4eb57f 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -176,21 +176,29 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 107
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         107
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
 /*
  * Pin Assignment
 */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PAR_ETPU        (MCF_IPSBAR + 0x10004E)
 
 /*
  * DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7f0c2c3660f..fdf45e6807c 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -25,41 +25,41 @@
 /*
  *      Define the 5249 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -134,23 +134,23 @@
 #define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
 #define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
 
-#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
-#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
-#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
+#define MCFSIM2_GPIOINTSTAT     (MCF_MBAR2 + 0xc0)      /* GPIO intr status */
+#define MCFSIM2_GPIOINTCLEAR    (MCF_MBAR2 + 0xc0)      /* GPIO intr clear */
+#define MCFSIM2_GPIOINTENABLE   (MCF_MBAR2 + 0xc4)      /* GPIO intr enable */
 
-#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
-#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
-#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
-#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
-#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
-#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
-#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
-#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
+#define MCFSIM2_INTLEVEL1       (MCF_MBAR2 + 0x140)     /* Intr level reg 1 */
+#define MCFSIM2_INTLEVEL2       (MCF_MBAR2 + 0x144)     /* Intr level reg 2 */
+#define MCFSIM2_INTLEVEL3       (MCF_MBAR2 + 0x148)     /* Intr level reg 3 */
+#define MCFSIM2_INTLEVEL4       (MCF_MBAR2 + 0x14c)     /* Intr level reg 4 */
+#define MCFSIM2_INTLEVEL5       (MCF_MBAR2 + 0x150)     /* Intr level reg 5 */
+#define MCFSIM2_INTLEVEL6       (MCF_MBAR2 + 0x154)     /* Intr level reg 6 */
+#define MCFSIM2_INTLEVEL7       (MCF_MBAR2 + 0x158)     /* Intr level reg 7 */
+#define MCFSIM2_INTLEVEL8       (MCF_MBAR2 + 0x15c)     /* Intr level reg 8 */
 
-#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
+#define MCFSIM2_DMAROUTE        (MCF_MBAR2 + 0x188)     /* DMA routing */
 
-#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
-#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
+#define MCFSIM2_IDECONFIG1      (MCF_MBAR2 + 0x18c)     /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2      (MCF_MBAR2 + 0x190)     /* IDEconfig2 */
 
 /*
  * Define the base interrupt for the second interrupt controller.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 6da24f65390..acab61cb91e 100644
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -26,41 +26,41 @@
 /*
  *      Define the 525x SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index a58f1760d85..1fb01bb05d6 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -21,52 +21,52 @@
 /*
  *      Define the 5272 SIM register set addresses.
  */
-#define MCFSIM_SCR              0x04            /* SIM Config reg (r/w) */
-#define MCFSIM_SPR              0x06            /* System Protection reg (r/w)*/
-#define MCFSIM_PMR              0x08            /* Power Management reg (r/w) */
-#define MCFSIM_APMR             0x0e            /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR              0x10            /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1             0x20            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x24            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x28            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x2c            /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR              0x30            /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR             0x34            /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR             0x38            /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR             0x3f            /* Interrupt Vector reg (r/w( */
-
-#define MCFSIM_WRRR             0x280           /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR             0x284           /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR              0x288           /* Watchdog counter (r/w) */
-#define MCFSIM_WER              0x28c           /* Watchdog event (r/w) */
-
-#define MCFSIM_CSBR0            0x40            /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0            0x44            /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1            0x48            /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1            0x4c            /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2            0x50            /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2            0x54            /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3            0x58            /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3            0x5c            /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4            0x60            /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4            0x64            /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5            0x68            /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5            0x6c            /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6            0x70            /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6            0x74            /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7            0x78            /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7            0x7c            /* CS7 Option (r/w) */
-
-#define MCFSIM_SDCR             0x180           /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR             0x184           /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0            0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0            0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0            0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1            0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_SCR              (MCF_MBAR + 0x04)       /* SIM Config reg */
+#define MCFSIM_SPR              (MCF_MBAR + 0x06)       /* System Protection */
+#define MCFSIM_PMR              (MCF_MBAR + 0x08)       /* Power Management */
+#define MCFSIM_APMR             (MCF_MBAR + 0x0e)       /* Active Low Power */
+#define MCFSIM_DIR              (MCF_MBAR + 0x10)       /* Device Identity */
+
+#define MCFSIM_ICR1             (MCF_MBAR + 0x20)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x24)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x28)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x2c)       /* Intr Ctrl reg 4 */
+
+#define MCFSIM_ISR              (MCF_MBAR + 0x30)       /* Intr Source */
+#define MCFSIM_PITR             (MCF_MBAR + 0x34)       /* Intr Transition */
+#define MCFSIM_PIWR             (MCF_MBAR + 0x38)       /* Intr Wakeup */
+#define MCFSIM_PIVR             (MCF_MBAR + 0x3f)       /* Intr Vector */
+
+#define MCFSIM_WRRR             (MCF_MBAR + 0x280)      /* Watchdog reference */
+#define MCFSIM_WIRR             (MCF_MBAR + 0x284)      /* Watchdog interrupt */
+#define MCFSIM_WCR              (MCF_MBAR + 0x288)      /* Watchdog counter */
+#define MCFSIM_WER              (MCF_MBAR + 0x28c)      /* Watchdog event */
+
+#define MCFSIM_CSBR0            (MCF_MBAR + 0x40)       /* CS0 Base Address */
+#define MCFSIM_CSOR0            (MCF_MBAR + 0x44)       /* CS0 Option */
+#define MCFSIM_CSBR1            (MCF_MBAR + 0x48)       /* CS1 Base Address */
+#define MCFSIM_CSOR1            (MCF_MBAR + 0x4c)       /* CS1 Option */
+#define MCFSIM_CSBR2            (MCF_MBAR + 0x50)       /* CS2 Base Address */
+#define MCFSIM_CSOR2            (MCF_MBAR + 0x54)       /* CS2 Option */
+#define MCFSIM_CSBR3            (MCF_MBAR + 0x58)       /* CS3 Base Address */
+#define MCFSIM_CSOR3            (MCF_MBAR + 0x5c)       /* CS3 Option */
+#define MCFSIM_CSBR4            (MCF_MBAR + 0x60)       /* CS4 Base Address */
+#define MCFSIM_CSOR4            (MCF_MBAR + 0x64)       /* CS4 Option */
+#define MCFSIM_CSBR5            (MCF_MBAR + 0x68)       /* CS5 Base Address */
+#define MCFSIM_CSOR5            (MCF_MBAR + 0x6c)       /* CS5 Option */
+#define MCFSIM_CSBR6            (MCF_MBAR + 0x70)       /* CS6 Base Address */
+#define MCFSIM_CSOR6            (MCF_MBAR + 0x74)       /* CS6 Option */
+#define MCFSIM_CSBR7            (MCF_MBAR + 0x78)       /* CS7 Base Address */
+#define MCFSIM_CSOR7            (MCF_MBAR + 0x7c)       /* CS7 Option */
+
+#define MCFSIM_SDCR             (MCF_MBAR + 0x180)      /* SDRAM Config */
+#define MCFSIM_SDTR             (MCF_MBAR + 0x184)      /* SDRAM Timing */
+#define MCFSIM_DCAR0            (MCF_MBAR + 0x4c)       /* DRAM 0 Address */
+#define MCFSIM_DCMR0            (MCF_MBAR + 0x50)       /* DRAM 0 Mask */
+#define MCFSIM_DCCR0            (MCF_MBAR + 0x57)       /* DRAM 0 Control */
+#define MCFSIM_DCAR1            (MCF_MBAR + 0x58)       /* DRAM 1 Address */
+#define MCFSIM_DCMR1            (MCF_MBAR + 0x5c)       /* DRAM 1 Mask reg */
+#define MCFSIM_DCCR1            (MCF_MBAR + 0x63)       /* DRAM 1 Control */
 
 #define MCFUART_BASE0           (MCF_MBAR + 0x100) /* Base address UART0 */
 #define MCFUART_BASE1           (MCF_MBAR + 0x140) /* Base address UART1 */
@@ -132,8 +132,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 48
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         48
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
+
 /****************************************************************************/
 #endif  /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa5104d3d..1bebbe78055 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,19 +184,33 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_ADDR
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_ADDR
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_ADDR
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_ADDR
+#define MCFGPIO_PODR            MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_ADDR
 
-#define MCFGPIO_PIN_MAX                 100
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         100
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x0ff0
+#define UART2_ENABLE_MASK       0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL     (MCF_IPSBAR + 0x100004)
@@ -279,18 +293,36 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PODR                    MCFGPIO_PODR_BUSCTL
-#define MCFGPIO_PDDR                    MCFGPIO_PDDR_BUSCTL
-#define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_SETR                    MCFGPIO_PPDSDR_BUSCTL
-#define MCFGPIO_CLRR                    MCFGPIO_PCLRR_BUSCTL
+#define MCFGPIO_PODR            MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_BUSCTL
 
-#define MCFGPIO_PIN_MAX                 148
-#define MCFGPIO_IRQ_MAX                 8
-#define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX         148
+#define MCFGPIO_IRQ_MAX         8
+#define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD          (MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS          (MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL      (MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB         (MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL      (MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL      (MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART        (MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM       (MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C      (MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS          (MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK       0x000f
+#define UART1_ENABLE_MASK       0x00f0
+#define UART2_ENABLE_MASK       0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -311,22 +343,6 @@
 #define MCFEPORT_EPFR           (MCF_IPSBAR + 0x130006)
 
 /*
- *      GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART       0x100048        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x0ff0
-#define UART2_ENABLE_MASK       0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART       0x10007c        /* PAR UART address */
-#define UART0_ENABLE_MASK       0x000f
-#define UART1_ENABLE_MASK       0x00f0
-#define UART2_ENABLE_MASK       0x3f00 
-#endif
-
-/*
  *  Reset Control Unit (relative to IPSBAR).
  */
 #define MCF_RCR                 (MCF_IPSBAR + 0x110000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4acb3c0a642..cf68ca0ac3a 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -233,23 +233,6 @@
 #define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
 #define MCFGPIO_PIN_MAX         180
 
-
-/*
- *      Derek Cheung - 6 Feb 2005
- *              add I2C and QSPI register definition using Freescale's MCF5282
- */
-/* set Port AS pin for I2C or UART */
-#define MCF5282_GPIO_PASPAR     (volatile u16 *) (MCF_IPSBAR + 0x00100056)
-
-/* Port UA Pin Assignment Register (8 Bit) */
-#define MCF5282_GPIO_PUAPAR     0x10005C
-
-/* Interrupt Mask Register Register Low */ 
-#define MCF5282_INTC0_IMRL      (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
-/* Interrupt Control Register 7 */
-#define MCF5282_INTC0_ICR17     (volatile u8 *) (MCF_IPSBAR + 0x0C51)
-
-
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
@@ -259,37 +242,5 @@
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 
-/*********************************************************************
-*
-* Inter-IC (I2C) Module
-*
-*********************************************************************/
-/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR       (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address 
-#define MCF5282_I2C_I2FDR       (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
-#define MCF5282_I2C_I2CR        (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
-#define MCF5282_I2C_I2SR        (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR        (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF5282_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF5282_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF5282_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF5282_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF5282_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF5282_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF5282_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-
+/****************************************************************************/
 #endif  /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 3bc3adaa7ee..5d0bb7ec31f 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,71 +23,71 @@
 /*
  *      Define the 5307 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status reg */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Itr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl Reg */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pend */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
 
 #ifdef CONFIG_OLDMASK
-#define MCFSIM_CSBAR            0x98            /* CS Base Address reg (r/w) */
-#define MCFSIM_CSBAMR           0x9c            /* CS Base Mask reg (r/w) */
-#define MCFSIM_CSMR2            0x9e            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSMR3            0xaa            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSMR4            0xb6            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSMR5            0xc2            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSMR6            0xce            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSMR7            0xda            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSBAR            (MCF_MBAR + 0x98)       /* CS Base Address */
+#define MCFSIM_CSBAMR           (MCF_MBAR + 0x9c)       /* CS Base Mask */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9e)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xaa)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb6)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc2)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xce)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xda)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #else
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 #endif /* CONFIG_OLDMASK */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
@@ -127,9 +127,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 
 /* Definition offset address for CS2-7  -- old mask 5307 */
@@ -167,9 +167,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b298c6e..8668e47ced0 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,10 +15,6 @@
 
 #include <asm/m53xxacr.h>
 
-#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
-#define MCF_REG16(x) (*(volatile unsigned short *)(x))
-#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
-
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
@@ -38,7 +34,7 @@
 
 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
 
-#define MCF_WTM_WCR     MCF_REG16(0xFC098000)
+#define MCF_WTM_WCR             0xFC098000
 
 /*
  *      Define the 532x SIM register set addresses.
@@ -152,42 +148,6 @@
 #define MCFPM_PPMHR1            0xfc040038
 #define MCFPM_LPCR              0xec090007
 
-/*********************************************************************
- *
- * Inter-IC (I2C) Module
- *
- *********************************************************************/
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address 
-#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN    (0x80)  // I2C enable
-#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
-#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
-#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-#define MCF532x_PAR_FECI2C      (volatile u8 *) (0xFC0A4053)
-
-
 /*
  *      The M5329EVB board needs a help getting its devices initialized 
  *      at kernel start time if dBUG doesn't set it up (for example 
@@ -217,13 +177,13 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
-#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
-#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
-#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
-#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
-#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
-#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)
+#define MCF_CCM_CCR               0xFC0A0004
+#define MCF_CCM_RCON              0xFC0A0008
+#define MCF_CCM_CIR               0xFC0A000A
+#define MCF_CCM_MISCCR            0xFC0A0010
+#define MCF_CCM_CDR               0xFC0A0012
+#define MCF_CCM_UHCSR             0xFC0A0014
+#define MCF_CCM_UOCSR             0xFC0A0016
 
 /* Bit definitions and macros for MCF_CCM_CCR */
 #define MCF_CCM_CCR_RESERVED      (0x0001)
@@ -287,104 +247,29 @@
 
 /*********************************************************************
  *
- * DMA Timers (DTIM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
-#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER           MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR           MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR           MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN           MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR           MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR          MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER           MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR           MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR           MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN           MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR           MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR          MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER           MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR           MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR           MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN           MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x)         MCF_REG16(0xFC070000+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x)        MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x)         MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x)         MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x)         MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x)         MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST        (0x0001)
-#define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR        (0x0008)
-#define MCF_DTIM_DTMR_ORRI       (0x0010)
-#define MCF_DTIM_DTMR_OM         (0x0020)
-#define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL    (0x0080)
-#define MCF_DTIM_DTMR_CE_RISE    (0x0040)
-#define MCF_DTIM_DTMR_CE_NONE    (0x0000)
-#define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
-#define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
-#define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
-#define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
-
-/* Bit definitions and macros for MCF_DTIM_DTXMR */
-#define MCF_DTIM_DTXMR_MODE16    (0x01)
-#define MCF_DTIM_DTXMR_DMAEN     (0x80)
-
-/* Bit definitions and macros for MCF_DTIM_DTER */
-#define MCF_DTIM_DTER_CAP        (0x01)
-#define MCF_DTIM_DTER_REF        (0x02)
-
-/* Bit definitions and macros for MCF_DTIM_DTRR */
-#define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCR */
-#define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCN */
-#define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
  * FlexBus Chip Selects (FBCS)
  *
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_FBCS0_CSAR          MCF_REG32(0xFC008000)
-#define MCF_FBCS0_CSMR          MCF_REG32(0xFC008004)
-#define MCF_FBCS0_CSCR          MCF_REG32(0xFC008008)
-#define MCF_FBCS1_CSAR          MCF_REG32(0xFC00800C)
-#define MCF_FBCS1_CSMR          MCF_REG32(0xFC008010)
-#define MCF_FBCS1_CSCR          MCF_REG32(0xFC008014)
-#define MCF_FBCS2_CSAR          MCF_REG32(0xFC008018)
-#define MCF_FBCS2_CSMR          MCF_REG32(0xFC00801C)
-#define MCF_FBCS2_CSCR          MCF_REG32(0xFC008020)
-#define MCF_FBCS3_CSAR          MCF_REG32(0xFC008024)
-#define MCF_FBCS3_CSMR          MCF_REG32(0xFC008028)
-#define MCF_FBCS3_CSCR          MCF_REG32(0xFC00802C)
-#define MCF_FBCS4_CSAR          MCF_REG32(0xFC008030)
-#define MCF_FBCS4_CSMR          MCF_REG32(0xFC008034)
-#define MCF_FBCS4_CSCR          MCF_REG32(0xFC008038)
-#define MCF_FBCS5_CSAR          MCF_REG32(0xFC00803C)
-#define MCF_FBCS5_CSMR          MCF_REG32(0xFC008040)
-#define MCF_FBCS5_CSCR          MCF_REG32(0xFC008044)
-#define MCF_FBCS_CSAR(x)        MCF_REG32(0xFC008000+((x)*0x00C))
-#define MCF_FBCS_CSMR(x)        MCF_REG32(0xFC008004+((x)*0x00C))
-#define MCF_FBCS_CSCR(x)        MCF_REG32(0xFC008008+((x)*0x00C))
+#define MCF_FBCS0_CSAR          0xFC008000
+#define MCF_FBCS0_CSMR          0xFC008004
+#define MCF_FBCS0_CSCR          0xFC008008
+#define MCF_FBCS1_CSAR          0xFC00800C
+#define MCF_FBCS1_CSMR          0xFC008010
+#define MCF_FBCS1_CSCR          0xFC008014
+#define MCF_FBCS2_CSAR          0xFC008018
+#define MCF_FBCS2_CSMR          0xFC00801C
+#define MCF_FBCS2_CSCR          0xFC008020
+#define MCF_FBCS3_CSAR          0xFC008024
+#define MCF_FBCS3_CSMR          0xFC008028
+#define MCF_FBCS3_CSCR          0xFC00802C
+#define MCF_FBCS4_CSAR          0xFC008030
+#define MCF_FBCS4_CSMR          0xFC008034
+#define MCF_FBCS4_CSCR          0xFC008038
+#define MCF_FBCS5_CSAR          0xFC00803C
+#define MCF_FBCS5_CSMR          0xFC008040
+#define MCF_FBCS5_CSCR          0xFC008044
 
 /* Bit definitions and macros for MCF_FBCS_CSAR */
 #define MCF_FBCS_CSAR_BA(x)     ((x)&0xFFFF0000)
@@ -501,32 +386,32 @@
 #define MCFGPIO_PCLRR_LCDDATAL          (0xFC0A404B)
 #define MCFGPIO_PCLRR_LCDCTLH           (0xFC0A404C)
 #define MCFGPIO_PCLRR_LCDCTLL           (0xFC0A404D)
-#define MCF_GPIO_PAR_FEC                MCF_REG08(0xFC0A4050)
-#define MCF_GPIO_PAR_PWM                MCF_REG08(0xFC0A4051)
-#define MCF_GPIO_PAR_BUSCTL             MCF_REG08(0xFC0A4052)
-#define MCF_GPIO_PAR_FECI2C             MCF_REG08(0xFC0A4053)
-#define MCF_GPIO_PAR_BE                 MCF_REG08(0xFC0A4054)
-#define MCF_GPIO_PAR_CS                 MCF_REG08(0xFC0A4055)
-#define MCF_GPIO_PAR_SSI                MCF_REG16(0xFC0A4056)
-#define MCF_GPIO_PAR_UART               MCF_REG16(0xFC0A4058)
-#define MCF_GPIO_PAR_QSPI               MCF_REG16(0xFC0A405A)
-#define MCF_GPIO_PAR_TIMER              MCF_REG08(0xFC0A405C)
-#define MCF_GPIO_PAR_LCDDATA            MCF_REG08(0xFC0A405D)
-#define MCF_GPIO_PAR_LCDCTL             MCF_REG16(0xFC0A405E)
-#define MCF_GPIO_PAR_IRQ                MCF_REG16(0xFC0A4060)
-#define MCF_GPIO_MSCR_FLEXBUS           MCF_REG08(0xFC0A4064)
-#define MCF_GPIO_MSCR_SDRAM             MCF_REG08(0xFC0A4065)
-#define MCF_GPIO_DSCR_I2C               MCF_REG08(0xFC0A4068)
-#define MCF_GPIO_DSCR_PWM               MCF_REG08(0xFC0A4069)
-#define MCF_GPIO_DSCR_FEC               MCF_REG08(0xFC0A406A)
-#define MCF_GPIO_DSCR_UART              MCF_REG08(0xFC0A406B)
-#define MCF_GPIO_DSCR_QSPI              MCF_REG08(0xFC0A406C)
-#define MCF_GPIO_DSCR_TIMER             MCF_REG08(0xFC0A406D)
-#define MCF_GPIO_DSCR_SSI               MCF_REG08(0xFC0A406E)
-#define MCF_GPIO_DSCR_LCD               MCF_REG08(0xFC0A406F)
-#define MCF_GPIO_DSCR_DEBUG             MCF_REG08(0xFC0A4070)
-#define MCF_GPIO_DSCR_CLKRST            MCF_REG08(0xFC0A4071)
-#define MCF_GPIO_DSCR_IRQ               MCF_REG08(0xFC0A4072)
+#define MCFGPIO_PAR_FEC                 (0xFC0A4050)
+#define MCFGPIO_PAR_PWM                 (0xFC0A4051)
+#define MCFGPIO_PAR_BUSCTL              (0xFC0A4052)
+#define MCFGPIO_PAR_FECI2C              (0xFC0A4053)
+#define MCFGPIO_PAR_BE                  (0xFC0A4054)
+#define MCFGPIO_PAR_CS                  (0xFC0A4055)
+#define MCFGPIO_PAR_SSI                 (0xFC0A4056)
+#define MCFGPIO_PAR_UART                (0xFC0A4058)
+#define MCFGPIO_PAR_QSPI                (0xFC0A405A)
+#define MCFGPIO_PAR_TIMER               (0xFC0A405C)
+#define MCFGPIO_PAR_LCDDATA             (0xFC0A405D)
+#define MCFGPIO_PAR_LCDCTL              (0xFC0A405E)
+#define MCFGPIO_PAR_IRQ                 (0xFC0A4060)
+#define MCFGPIO_MSCR_FLEXBUS            (0xFC0A4064)
+#define MCFGPIO_MSCR_SDRAM              (0xFC0A4065)
+#define MCFGPIO_DSCR_I2C                (0xFC0A4068)
+#define MCFGPIO_DSCR_PWM                (0xFC0A4069)
+#define MCFGPIO_DSCR_FEC                (0xFC0A406A)
+#define MCFGPIO_DSCR_UART               (0xFC0A406B)
+#define MCFGPIO_DSCR_QSPI               (0xFC0A406C)
+#define MCFGPIO_DSCR_TIMER              (0xFC0A406D)
+#define MCFGPIO_DSCR_SSI                (0xFC0A406E)
+#define MCFGPIO_DSCR_LCD                (0xFC0A406F)
+#define MCFGPIO_DSCR_DEBUG              (0xFC0A4070)
+#define MCFGPIO_DSCR_CLKRST             (0xFC0A4071)
+#define MCFGPIO_DSCR_IRQ                (0xFC0A4072)
 
 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
 #define MCF_GPIO_PODR_FECH_PODR_FECH0              (0x01)
@@ -1215,709 +1100,6 @@
 #define MCFGPIO_IRQ_MAX                 8
 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
 
-
-/*********************************************************************
- *
- * Interrupt Controller (INTC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH             MCF_REG32(0xFC048000)
-#define MCF_INTC0_IPRL             MCF_REG32(0xFC048004)
-#define MCF_INTC0_IMRH             MCF_REG32(0xFC048008)
-#define MCF_INTC0_IMRL             MCF_REG32(0xFC04800C)
-#define MCF_INTC0_INTFRCH          MCF_REG32(0xFC048010)
-#define MCF_INTC0_INTFRCL          MCF_REG32(0xFC048014)
-#define MCF_INTC0_ICONFIG          MCF_REG16(0xFC04801A)
-#define MCF_INTC0_SIMR             MCF_REG08(0xFC04801C)
-#define MCF_INTC0_CIMR             MCF_REG08(0xFC04801D)
-#define MCF_INTC0_CLMASK           MCF_REG08(0xFC04801E)
-#define MCF_INTC0_SLMASK           MCF_REG08(0xFC04801F)
-#define MCF_INTC0_ICR0             MCF_REG08(0xFC048040)
-#define MCF_INTC0_ICR1             MCF_REG08(0xFC048041)
-#define MCF_INTC0_ICR2             MCF_REG08(0xFC048042)
-#define MCF_INTC0_ICR3             MCF_REG08(0xFC048043)
-#define MCF_INTC0_ICR4             MCF_REG08(0xFC048044)
-#define MCF_INTC0_ICR5             MCF_REG08(0xFC048045)
-#define MCF_INTC0_ICR6             MCF_REG08(0xFC048046)
-#define MCF_INTC0_ICR7             MCF_REG08(0xFC048047)
-#define MCF_INTC0_ICR8             MCF_REG08(0xFC048048)
-#define MCF_INTC0_ICR9             MCF_REG08(0xFC048049)
-#define MCF_INTC0_ICR10            MCF_REG08(0xFC04804A)
-#define MCF_INTC0_ICR11            MCF_REG08(0xFC04804B)
-#define MCF_INTC0_ICR12            MCF_REG08(0xFC04804C)
-#define MCF_INTC0_ICR13            MCF_REG08(0xFC04804D)
-#define MCF_INTC0_ICR14            MCF_REG08(0xFC04804E)
-#define MCF_INTC0_ICR15            MCF_REG08(0xFC04804F)
-#define MCF_INTC0_ICR16            MCF_REG08(0xFC048050)
-#define MCF_INTC0_ICR17            MCF_REG08(0xFC048051)
-#define MCF_INTC0_ICR18            MCF_REG08(0xFC048052)
-#define MCF_INTC0_ICR19            MCF_REG08(0xFC048053)
-#define MCF_INTC0_ICR20            MCF_REG08(0xFC048054)
-#define MCF_INTC0_ICR21            MCF_REG08(0xFC048055)
-#define MCF_INTC0_ICR22            MCF_REG08(0xFC048056)
-#define MCF_INTC0_ICR23            MCF_REG08(0xFC048057)
-#define MCF_INTC0_ICR24            MCF_REG08(0xFC048058)
-#define MCF_INTC0_ICR25            MCF_REG08(0xFC048059)
-#define MCF_INTC0_ICR26            MCF_REG08(0xFC04805A)
-#define MCF_INTC0_ICR27            MCF_REG08(0xFC04805B)
-#define MCF_INTC0_ICR28            MCF_REG08(0xFC04805C)
-#define MCF_INTC0_ICR29            MCF_REG08(0xFC04805D)
-#define MCF_INTC0_ICR30            MCF_REG08(0xFC04805E)
-#define MCF_INTC0_ICR31            MCF_REG08(0xFC04805F)
-#define MCF_INTC0_ICR32            MCF_REG08(0xFC048060)
-#define MCF_INTC0_ICR33            MCF_REG08(0xFC048061)
-#define MCF_INTC0_ICR34            MCF_REG08(0xFC048062)
-#define MCF_INTC0_ICR35            MCF_REG08(0xFC048063)
-#define MCF_INTC0_ICR36            MCF_REG08(0xFC048064)
-#define MCF_INTC0_ICR37            MCF_REG08(0xFC048065)
-#define MCF_INTC0_ICR38            MCF_REG08(0xFC048066)
-#define MCF_INTC0_ICR39            MCF_REG08(0xFC048067)
-#define MCF_INTC0_ICR40            MCF_REG08(0xFC048068)
-#define MCF_INTC0_ICR41            MCF_REG08(0xFC048069)
-#define MCF_INTC0_ICR42            MCF_REG08(0xFC04806A)
-#define MCF_INTC0_ICR43            MCF_REG08(0xFC04806B)
-#define MCF_INTC0_ICR44            MCF_REG08(0xFC04806C)
-#define MCF_INTC0_ICR45            MCF_REG08(0xFC04806D)
-#define MCF_INTC0_ICR46            MCF_REG08(0xFC04806E)
-#define MCF_INTC0_ICR47            MCF_REG08(0xFC04806F)
-#define MCF_INTC0_ICR48            MCF_REG08(0xFC048070)
-#define MCF_INTC0_ICR49            MCF_REG08(0xFC048071)
-#define MCF_INTC0_ICR50            MCF_REG08(0xFC048072)
-#define MCF_INTC0_ICR51            MCF_REG08(0xFC048073)
-#define MCF_INTC0_ICR52            MCF_REG08(0xFC048074)
-#define MCF_INTC0_ICR53            MCF_REG08(0xFC048075)
-#define MCF_INTC0_ICR54            MCF_REG08(0xFC048076)
-#define MCF_INTC0_ICR55            MCF_REG08(0xFC048077)
-#define MCF_INTC0_ICR56            MCF_REG08(0xFC048078)
-#define MCF_INTC0_ICR57            MCF_REG08(0xFC048079)
-#define MCF_INTC0_ICR58            MCF_REG08(0xFC04807A)
-#define MCF_INTC0_ICR59            MCF_REG08(0xFC04807B)
-#define MCF_INTC0_ICR60            MCF_REG08(0xFC04807C)
-#define MCF_INTC0_ICR61            MCF_REG08(0xFC04807D)
-#define MCF_INTC0_ICR62            MCF_REG08(0xFC04807E)
-#define MCF_INTC0_ICR63            MCF_REG08(0xFC04807F)
-#define MCF_INTC0_ICR(x)           MCF_REG08(0xFC048040+((x)*0x001))
-#define MCF_INTC0_SWIACK           MCF_REG08(0xFC0480E0)
-#define MCF_INTC0_L1IACK           MCF_REG08(0xFC0480E4)
-#define MCF_INTC0_L2IACK           MCF_REG08(0xFC0480E8)
-#define MCF_INTC0_L3IACK           MCF_REG08(0xFC0480EC)
-#define MCF_INTC0_L4IACK           MCF_REG08(0xFC0480F0)
-#define MCF_INTC0_L5IACK           MCF_REG08(0xFC0480F4)
-#define MCF_INTC0_L6IACK           MCF_REG08(0xFC0480F8)
-#define MCF_INTC0_L7IACK           MCF_REG08(0xFC0480FC)
-#define MCF_INTC0_LIACK(x)         MCF_REG08(0xFC0480E4+((x)*0x004))
-#define MCF_INTC1_IPRH             MCF_REG32(0xFC04C000)
-#define MCF_INTC1_IPRL             MCF_REG32(0xFC04C004)
-#define MCF_INTC1_IMRH             MCF_REG32(0xFC04C008)
-#define MCF_INTC1_IMRL             MCF_REG32(0xFC04C00C)
-#define MCF_INTC1_INTFRCH          MCF_REG32(0xFC04C010)
-#define MCF_INTC1_INTFRCL          MCF_REG32(0xFC04C014)
-#define MCF_INTC1_ICONFIG          MCF_REG16(0xFC04C01A)
-#define MCF_INTC1_SIMR             MCF_REG08(0xFC04C01C)
-#define MCF_INTC1_CIMR             MCF_REG08(0xFC04C01D)
-#define MCF_INTC1_CLMASK           MCF_REG08(0xFC04C01E)
-#define MCF_INTC1_SLMASK           MCF_REG08(0xFC04C01F)
-#define MCF_INTC1_ICR0             MCF_REG08(0xFC04C040)
-#define MCF_INTC1_ICR1             MCF_REG08(0xFC04C041)
-#define MCF_INTC1_ICR2             MCF_REG08(0xFC04C042)
-#define MCF_INTC1_ICR3             MCF_REG08(0xFC04C043)
-#define MCF_INTC1_ICR4             MCF_REG08(0xFC04C044)
-#define MCF_INTC1_ICR5             MCF_REG08(0xFC04C045)
-#define MCF_INTC1_ICR6             MCF_REG08(0xFC04C046)
-#define MCF_INTC1_ICR7             MCF_REG08(0xFC04C047)
-#define MCF_INTC1_ICR8             MCF_REG08(0xFC04C048)
-#define MCF_INTC1_ICR9             MCF_REG08(0xFC04C049)
-#define MCF_INTC1_ICR10            MCF_REG08(0xFC04C04A)
-#define MCF_INTC1_ICR11            MCF_REG08(0xFC04C04B)
-#define MCF_INTC1_ICR12            MCF_REG08(0xFC04C04C)
-#define MCF_INTC1_ICR13            MCF_REG08(0xFC04C04D)
-#define MCF_INTC1_ICR14            MCF_REG08(0xFC04C04E)
-#define MCF_INTC1_ICR15            MCF_REG08(0xFC04C04F)
-#define MCF_INTC1_ICR16            MCF_REG08(0xFC04C050)
-#define MCF_INTC1_ICR17            MCF_REG08(0xFC04C051)
-#define MCF_INTC1_ICR18            MCF_REG08(0xFC04C052)
-#define MCF_INTC1_ICR19            MCF_REG08(0xFC04C053)
-#define MCF_INTC1_ICR20            MCF_REG08(0xFC04C054)
-#define MCF_INTC1_ICR21            MCF_REG08(0xFC04C055)
-#define MCF_INTC1_ICR22            MCF_REG08(0xFC04C056)
-#define MCF_INTC1_ICR23            MCF_REG08(0xFC04C057)
-#define MCF_INTC1_ICR24            MCF_REG08(0xFC04C058)
-#define MCF_INTC1_ICR25            MCF_REG08(0xFC04C059)
-#define MCF_INTC1_ICR26            MCF_REG08(0xFC04C05A)
-#define MCF_INTC1_ICR27            MCF_REG08(0xFC04C05B)
-#define MCF_INTC1_ICR28            MCF_REG08(0xFC04C05C)
-#define MCF_INTC1_ICR29            MCF_REG08(0xFC04C05D)
-#define MCF_INTC1_ICR30            MCF_REG08(0xFC04C05E)
-#define MCF_INTC1_ICR31            MCF_REG08(0xFC04C05F)
-#define MCF_INTC1_ICR32            MCF_REG08(0xFC04C060)
-#define MCF_INTC1_ICR33            MCF_REG08(0xFC04C061)
-#define MCF_INTC1_ICR34            MCF_REG08(0xFC04C062)
-#define MCF_INTC1_ICR35            MCF_REG08(0xFC04C063)
-#define MCF_INTC1_ICR36            MCF_REG08(0xFC04C064)
-#define MCF_INTC1_ICR37            MCF_REG08(0xFC04C065)
-#define MCF_INTC1_ICR38            MCF_REG08(0xFC04C066)
-#define MCF_INTC1_ICR39            MCF_REG08(0xFC04C067)
-#define MCF_INTC1_ICR40            MCF_REG08(0xFC04C068)
-#define MCF_INTC1_ICR41            MCF_REG08(0xFC04C069)
-#define MCF_INTC1_ICR42            MCF_REG08(0xFC04C06A)
-#define MCF_INTC1_ICR43            MCF_REG08(0xFC04C06B)
-#define MCF_INTC1_ICR44            MCF_REG08(0xFC04C06C)
-#define MCF_INTC1_ICR45            MCF_REG08(0xFC04C06D)
-#define MCF_INTC1_ICR46            MCF_REG08(0xFC04C06E)
-#define MCF_INTC1_ICR47            MCF_REG08(0xFC04C06F)
-#define MCF_INTC1_ICR48            MCF_REG08(0xFC04C070)
-#define MCF_INTC1_ICR49            MCF_REG08(0xFC04C071)
-#define MCF_INTC1_ICR50            MCF_REG08(0xFC04C072)
-#define MCF_INTC1_ICR51            MCF_REG08(0xFC04C073)
-#define MCF_INTC1_ICR52            MCF_REG08(0xFC04C074)
-#define MCF_INTC1_ICR53            MCF_REG08(0xFC04C075)
-#define MCF_INTC1_ICR54            MCF_REG08(0xFC04C076)
-#define MCF_INTC1_ICR55            MCF_REG08(0xFC04C077)
-#define MCF_INTC1_ICR56            MCF_REG08(0xFC04C078)
-#define MCF_INTC1_ICR57            MCF_REG08(0xFC04C079)
-#define MCF_INTC1_ICR58            MCF_REG08(0xFC04C07A)
-#define MCF_INTC1_ICR59            MCF_REG08(0xFC04C07B)
-#define MCF_INTC1_ICR60            MCF_REG08(0xFC04C07C)
-#define MCF_INTC1_ICR61            MCF_REG08(0xFC04C07D)
-#define MCF_INTC1_ICR62            MCF_REG08(0xFC04C07E)
-#define MCF_INTC1_ICR63            MCF_REG08(0xFC04C07F)
-#define MCF_INTC1_ICR(x)           MCF_REG08(0xFC04C040+((x)*0x001))
-#define MCF_INTC1_SWIACK           MCF_REG08(0xFC04C0E0)
-#define MCF_INTC1_L1IACK           MCF_REG08(0xFC04C0E4)
-#define MCF_INTC1_L2IACK           MCF_REG08(0xFC04C0E8)
-#define MCF_INTC1_L3IACK           MCF_REG08(0xFC04C0EC)
-#define MCF_INTC1_L4IACK           MCF_REG08(0xFC04C0F0)
-#define MCF_INTC1_L5IACK           MCF_REG08(0xFC04C0F4)
-#define MCF_INTC1_L6IACK           MCF_REG08(0xFC04C0F8)
-#define MCF_INTC1_L7IACK           MCF_REG08(0xFC04C0FC)
-#define MCF_INTC1_LIACK(x)         MCF_REG08(0xFC04C0E4+((x)*0x004))
-#define MCF_INTC_IPRH(x)           MCF_REG32(0xFC048000+((x)*0x4000))
-#define MCF_INTC_IPRL(x)           MCF_REG32(0xFC048004+((x)*0x4000))
-#define MCF_INTC_IMRH(x)           MCF_REG32(0xFC048008+((x)*0x4000))
-#define MCF_INTC_IMRL(x)           MCF_REG32(0xFC04800C+((x)*0x4000))
-#define MCF_INTC_INTFRCH(x)        MCF_REG32(0xFC048010+((x)*0x4000))
-#define MCF_INTC_INTFRCL(x)        MCF_REG32(0xFC048014+((x)*0x4000))
-#define MCF_INTC_ICONFIG(x)        MCF_REG16(0xFC04801A+((x)*0x4000))
-#define MCF_INTC_SIMR(x)           MCF_REG08(0xFC04801C+((x)*0x4000))
-#define MCF_INTC_CIMR(x)           MCF_REG08(0xFC04801D+((x)*0x4000))
-#define MCF_INTC_CLMASK(x)         MCF_REG08(0xFC04801E+((x)*0x4000))
-#define MCF_INTC_SLMASK(x)         MCF_REG08(0xFC04801F+((x)*0x4000))
-#define MCF_INTC_ICR0(x)           MCF_REG08(0xFC048040+((x)*0x4000))
-#define MCF_INTC_ICR1(x)           MCF_REG08(0xFC048041+((x)*0x4000))
-#define MCF_INTC_ICR2(x)           MCF_REG08(0xFC048042+((x)*0x4000))
-#define MCF_INTC_ICR3(x)           MCF_REG08(0xFC048043+((x)*0x4000))
-#define MCF_INTC_ICR4(x)           MCF_REG08(0xFC048044+((x)*0x4000))
-#define MCF_INTC_ICR5(x)           MCF_REG08(0xFC048045+((x)*0x4000))
-#define MCF_INTC_ICR6(x)           MCF_REG08(0xFC048046+((x)*0x4000))
-#define MCF_INTC_ICR7(x)           MCF_REG08(0xFC048047+((x)*0x4000))
-#define MCF_INTC_ICR8(x)           MCF_REG08(0xFC048048+((x)*0x4000))
-#define MCF_INTC_ICR9(x)           MCF_REG08(0xFC048049+((x)*0x4000))
-#define MCF_INTC_ICR10(x)          MCF_REG08(0xFC04804A+((x)*0x4000))
-#define MCF_INTC_ICR11(x)          MCF_REG08(0xFC04804B+((x)*0x4000))
-#define MCF_INTC_ICR12(x)          MCF_REG08(0xFC04804C+((x)*0x4000))
-#define MCF_INTC_ICR13(x)          MCF_REG08(0xFC04804D+((x)*0x4000))
-#define MCF_INTC_ICR14(x)          MCF_REG08(0xFC04804E+((x)*0x4000))
-#define MCF_INTC_ICR15(x)          MCF_REG08(0xFC04804F+((x)*0x4000))
-#define MCF_INTC_ICR16(x)          MCF_REG08(0xFC048050+((x)*0x4000))
-#define MCF_INTC_ICR17(x)          MCF_REG08(0xFC048051+((x)*0x4000))
-#define MCF_INTC_ICR18(x)          MCF_REG08(0xFC048052+((x)*0x4000))
-#define MCF_INTC_ICR19(x)          MCF_REG08(0xFC048053+((x)*0x4000))
-#define MCF_INTC_ICR20(x)          MCF_REG08(0xFC048054+((x)*0x4000))
-#define MCF_INTC_ICR21(x)          MCF_REG08(0xFC048055+((x)*0x4000))
-#define MCF_INTC_ICR22(x)          MCF_REG08(0xFC048056+((x)*0x4000))
-#define MCF_INTC_ICR23(x)          MCF_REG08(0xFC048057+((x)*0x4000))
-#define MCF_INTC_ICR24(x)          MCF_REG08(0xFC048058+((x)*0x4000))
-#define MCF_INTC_ICR25(x)          MCF_REG08(0xFC048059+((x)*0x4000))
-#define MCF_INTC_ICR26(x)          MCF_REG08(0xFC04805A+((x)*0x4000))
-#define MCF_INTC_ICR27(x)          MCF_REG08(0xFC04805B+((x)*0x4000))
-#define MCF_INTC_ICR28(x)          MCF_REG08(0xFC04805C+((x)*0x4000))
-#define MCF_INTC_ICR29(x)          MCF_REG08(0xFC04805D+((x)*0x4000))
-#define MCF_INTC_ICR30(x)          MCF_REG08(0xFC04805E+((x)*0x4000))
-#define MCF_INTC_ICR31(x)          MCF_REG08(0xFC04805F+((x)*0x4000))
-#define MCF_INTC_ICR32(x)          MCF_REG08(0xFC048060+((x)*0x4000))
-#define MCF_INTC_ICR33(x)          MCF_REG08(0xFC048061+((x)*0x4000))
-#define MCF_INTC_ICR34(x)          MCF_REG08(0xFC048062+((x)*0x4000))
-#define MCF_INTC_ICR35(x)          MCF_REG08(0xFC048063+((x)*0x4000))
-#define MCF_INTC_ICR36(x)          MCF_REG08(0xFC048064+((x)*0x4000))
-#define MCF_INTC_ICR37(x)          MCF_REG08(0xFC048065+((x)*0x4000))
-#define MCF_INTC_ICR38(x)          MCF_REG08(0xFC048066+((x)*0x4000))
-#define MCF_INTC_ICR39(x)          MCF_REG08(0xFC048067+((x)*0x4000))
-#define MCF_INTC_ICR40(x)          MCF_REG08(0xFC048068+((x)*0x4000))
-#define MCF_INTC_ICR41(x)          MCF_REG08(0xFC048069+((x)*0x4000))
-#define MCF_INTC_ICR42(x)          MCF_REG08(0xFC04806A+((x)*0x4000))
-#define MCF_INTC_ICR43(x)          MCF_REG08(0xFC04806B+((x)*0x4000))
-#define MCF_INTC_ICR44(x)          MCF_REG08(0xFC04806C+((x)*0x4000))
-#define MCF_INTC_ICR45(x)          MCF_REG08(0xFC04806D+((x)*0x4000))
-#define MCF_INTC_ICR46(x)          MCF_REG08(0xFC04806E+((x)*0x4000))
-#define MCF_INTC_ICR47(x)          MCF_REG08(0xFC04806F+((x)*0x4000))
-#define MCF_INTC_ICR48(x)          MCF_REG08(0xFC048070+((x)*0x4000))
-#define MCF_INTC_ICR49(x)          MCF_REG08(0xFC048071+((x)*0x4000))
-#define MCF_INTC_ICR50(x)          MCF_REG08(0xFC048072+((x)*0x4000))
-#define MCF_INTC_ICR51(x)          MCF_REG08(0xFC048073+((x)*0x4000))
-#define MCF_INTC_ICR52(x)          MCF_REG08(0xFC048074+((x)*0x4000))
-#define MCF_INTC_ICR53(x)          MCF_REG08(0xFC048075+((x)*0x4000))
-#define MCF_INTC_ICR54(x)          MCF_REG08(0xFC048076+((x)*0x4000))
-#define MCF_INTC_ICR55(x)          MCF_REG08(0xFC048077+((x)*0x4000))
-#define MCF_INTC_ICR56(x)          MCF_REG08(0xFC048078+((x)*0x4000))
-#define MCF_INTC_ICR57(x)          MCF_REG08(0xFC048079+((x)*0x4000))
-#define MCF_INTC_ICR58(x)          MCF_REG08(0xFC04807A+((x)*0x4000))
-#define MCF_INTC_ICR59(x)          MCF_REG08(0xFC04807B+((x)*0x4000))
-#define MCF_INTC_ICR60(x)          MCF_REG08(0xFC04807C+((x)*0x4000))
-#define MCF_INTC_ICR61(x)          MCF_REG08(0xFC04807D+((x)*0x4000))
-#define MCF_INTC_ICR62(x)          MCF_REG08(0xFC04807E+((x)*0x4000))
-#define MCF_INTC_ICR63(x)          MCF_REG08(0xFC04807F+((x)*0x4000))
-#define MCF_INTC_SWIACK(x)         MCF_REG08(0xFC0480E0+((x)*0x4000))
-#define MCF_INTC_L1IACK(x)         MCF_REG08(0xFC0480E4+((x)*0x4000))
-#define MCF_INTC_L2IACK(x)         MCF_REG08(0xFC0480E8+((x)*0x4000))
-#define MCF_INTC_L3IACK(x)         MCF_REG08(0xFC0480EC+((x)*0x4000))
-#define MCF_INTC_L4IACK(x)         MCF_REG08(0xFC0480F0+((x)*0x4000))
-#define MCF_INTC_L5IACK(x)         MCF_REG08(0xFC0480F4+((x)*0x4000))
-#define MCF_INTC_L6IACK(x)         MCF_REG08(0xFC0480F8+((x)*0x4000))
-#define MCF_INTC_L7IACK(x)         MCF_REG08(0xFC0480FC+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_INTC_IPRH */
-#define MCF_INTC_IPRH_INT32        (0x00000001)
-#define MCF_INTC_IPRH_INT33        (0x00000002)
-#define MCF_INTC_IPRH_INT34        (0x00000004)
-#define MCF_INTC_IPRH_INT35        (0x00000008)
-#define MCF_INTC_IPRH_INT36        (0x00000010)
-#define MCF_INTC_IPRH_INT37        (0x00000020)
-#define MCF_INTC_IPRH_INT38        (0x00000040)
-#define MCF_INTC_IPRH_INT39        (0x00000080)
-#define MCF_INTC_IPRH_INT40        (0x00000100)
-#define MCF_INTC_IPRH_INT41        (0x00000200)
-#define MCF_INTC_IPRH_INT42        (0x00000400)
-#define MCF_INTC_IPRH_INT43        (0x00000800)
-#define MCF_INTC_IPRH_INT44        (0x00001000)
-#define MCF_INTC_IPRH_INT45        (0x00002000)
-#define MCF_INTC_IPRH_INT46        (0x00004000)
-#define MCF_INTC_IPRH_INT47        (0x00008000)
-#define MCF_INTC_IPRH_INT48        (0x00010000)
-#define MCF_INTC_IPRH_INT49        (0x00020000)
-#define MCF_INTC_IPRH_INT50        (0x00040000)
-#define MCF_INTC_IPRH_INT51        (0x00080000)
-#define MCF_INTC_IPRH_INT52        (0x00100000)
-#define MCF_INTC_IPRH_INT53        (0x00200000)
-#define MCF_INTC_IPRH_INT54        (0x00400000)
-#define MCF_INTC_IPRH_INT55        (0x00800000)
-#define MCF_INTC_IPRH_INT56        (0x01000000)
-#define MCF_INTC_IPRH_INT57        (0x02000000)
-#define MCF_INTC_IPRH_INT58        (0x04000000)
-#define MCF_INTC_IPRH_INT59        (0x08000000)
-#define MCF_INTC_IPRH_INT60        (0x10000000)
-#define MCF_INTC_IPRH_INT61        (0x20000000)
-#define MCF_INTC_IPRH_INT62        (0x40000000)
-#define MCF_INTC_IPRH_INT63        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IPRL */
-#define MCF_INTC_IPRL_INT0         (0x00000001)
-#define MCF_INTC_IPRL_INT1         (0x00000002)
-#define MCF_INTC_IPRL_INT2         (0x00000004)
-#define MCF_INTC_IPRL_INT3         (0x00000008)
-#define MCF_INTC_IPRL_INT4         (0x00000010)
-#define MCF_INTC_IPRL_INT5         (0x00000020)
-#define MCF_INTC_IPRL_INT6         (0x00000040)
-#define MCF_INTC_IPRL_INT7         (0x00000080)
-#define MCF_INTC_IPRL_INT8         (0x00000100)
-#define MCF_INTC_IPRL_INT9         (0x00000200)
-#define MCF_INTC_IPRL_INT10        (0x00000400)
-#define MCF_INTC_IPRL_INT11        (0x00000800)
-#define MCF_INTC_IPRL_INT12        (0x00001000)
-#define MCF_INTC_IPRL_INT13        (0x00002000)
-#define MCF_INTC_IPRL_INT14        (0x00004000)
-#define MCF_INTC_IPRL_INT15        (0x00008000)
-#define MCF_INTC_IPRL_INT16        (0x00010000)
-#define MCF_INTC_IPRL_INT17        (0x00020000)
-#define MCF_INTC_IPRL_INT18        (0x00040000)
-#define MCF_INTC_IPRL_INT19        (0x00080000)
-#define MCF_INTC_IPRL_INT20        (0x00100000)
-#define MCF_INTC_IPRL_INT21        (0x00200000)
-#define MCF_INTC_IPRL_INT22        (0x00400000)
-#define MCF_INTC_IPRL_INT23        (0x00800000)
-#define MCF_INTC_IPRL_INT24        (0x01000000)
-#define MCF_INTC_IPRL_INT25        (0x02000000)
-#define MCF_INTC_IPRL_INT26        (0x04000000)
-#define MCF_INTC_IPRL_INT27        (0x08000000)
-#define MCF_INTC_IPRL_INT28        (0x10000000)
-#define MCF_INTC_IPRL_INT29        (0x20000000)
-#define MCF_INTC_IPRL_INT30        (0x40000000)
-#define MCF_INTC_IPRL_INT31        (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRH */
-#define MCF_INTC_IMRH_INT_MASK32   (0x00000001)
-#define MCF_INTC_IMRH_INT_MASK33   (0x00000002)
-#define MCF_INTC_IMRH_INT_MASK34   (0x00000004)
-#define MCF_INTC_IMRH_INT_MASK35   (0x00000008)
-#define MCF_INTC_IMRH_INT_MASK36   (0x00000010)
-#define MCF_INTC_IMRH_INT_MASK37   (0x00000020)
-#define MCF_INTC_IMRH_INT_MASK38   (0x00000040)
-#define MCF_INTC_IMRH_INT_MASK39   (0x00000080)
-#define MCF_INTC_IMRH_INT_MASK40   (0x00000100)
-#define MCF_INTC_IMRH_INT_MASK41   (0x00000200)
-#define MCF_INTC_IMRH_INT_MASK42   (0x00000400)
-#define MCF_INTC_IMRH_INT_MASK43   (0x00000800)
-#define MCF_INTC_IMRH_INT_MASK44   (0x00001000)
-#define MCF_INTC_IMRH_INT_MASK45   (0x00002000)
-#define MCF_INTC_IMRH_INT_MASK46   (0x00004000)
-#define MCF_INTC_IMRH_INT_MASK47   (0x00008000)
-#define MCF_INTC_IMRH_INT_MASK48   (0x00010000)
-#define MCF_INTC_IMRH_INT_MASK49   (0x00020000)
-#define MCF_INTC_IMRH_INT_MASK50   (0x00040000)
-#define MCF_INTC_IMRH_INT_MASK51   (0x00080000)
-#define MCF_INTC_IMRH_INT_MASK52   (0x00100000)
-#define MCF_INTC_IMRH_INT_MASK53   (0x00200000)
-#define MCF_INTC_IMRH_INT_MASK54   (0x00400000)
-#define MCF_INTC_IMRH_INT_MASK55   (0x00800000)
-#define MCF_INTC_IMRH_INT_MASK56   (0x01000000)
-#define MCF_INTC_IMRH_INT_MASK57   (0x02000000)
-#define MCF_INTC_IMRH_INT_MASK58   (0x04000000)
-#define MCF_INTC_IMRH_INT_MASK59   (0x08000000)
-#define MCF_INTC_IMRH_INT_MASK60   (0x10000000)
-#define MCF_INTC_IMRH_INT_MASK61   (0x20000000)
-#define MCF_INTC_IMRH_INT_MASK62   (0x40000000)
-#define MCF_INTC_IMRH_INT_MASK63   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRL */
-#define MCF_INTC_IMRL_INT_MASK0    (0x00000001)
-#define MCF_INTC_IMRL_INT_MASK1    (0x00000002)
-#define MCF_INTC_IMRL_INT_MASK2    (0x00000004)
-#define MCF_INTC_IMRL_INT_MASK3    (0x00000008)
-#define MCF_INTC_IMRL_INT_MASK4    (0x00000010)
-#define MCF_INTC_IMRL_INT_MASK5    (0x00000020)
-#define MCF_INTC_IMRL_INT_MASK6    (0x00000040)
-#define MCF_INTC_IMRL_INT_MASK7    (0x00000080)
-#define MCF_INTC_IMRL_INT_MASK8    (0x00000100)
-#define MCF_INTC_IMRL_INT_MASK9    (0x00000200)
-#define MCF_INTC_IMRL_INT_MASK10   (0x00000400)
-#define MCF_INTC_IMRL_INT_MASK11   (0x00000800)
-#define MCF_INTC_IMRL_INT_MASK12   (0x00001000)
-#define MCF_INTC_IMRL_INT_MASK13   (0x00002000)
-#define MCF_INTC_IMRL_INT_MASK14   (0x00004000)
-#define MCF_INTC_IMRL_INT_MASK15   (0x00008000)
-#define MCF_INTC_IMRL_INT_MASK16   (0x00010000)
-#define MCF_INTC_IMRL_INT_MASK17   (0x00020000)
-#define MCF_INTC_IMRL_INT_MASK18   (0x00040000)
-#define MCF_INTC_IMRL_INT_MASK19   (0x00080000)
-#define MCF_INTC_IMRL_INT_MASK20   (0x00100000)
-#define MCF_INTC_IMRL_INT_MASK21   (0x00200000)
-#define MCF_INTC_IMRL_INT_MASK22   (0x00400000)
-#define MCF_INTC_IMRL_INT_MASK23   (0x00800000)
-#define MCF_INTC_IMRL_INT_MASK24   (0x01000000)
-#define MCF_INTC_IMRL_INT_MASK25   (0x02000000)
-#define MCF_INTC_IMRL_INT_MASK26   (0x04000000)
-#define MCF_INTC_IMRL_INT_MASK27   (0x08000000)
-#define MCF_INTC_IMRL_INT_MASK28   (0x10000000)
-#define MCF_INTC_IMRL_INT_MASK29   (0x20000000)
-#define MCF_INTC_IMRL_INT_MASK30   (0x40000000)
-#define MCF_INTC_IMRL_INT_MASK31   (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCH */
-#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
-#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
-#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
-#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
-#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
-#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
-#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
-#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
-#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
-#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
-#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
-#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
-#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
-#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
-#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
-#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
-#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
-#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
-#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
-#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
-#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
-#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
-#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
-#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
-#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
-#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
-#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
-#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
-#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
-#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
-#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
-#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCL */
-#define MCF_INTC_INTFRCL_INTFRC0   (0x00000001)
-#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
-#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
-#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
-#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
-#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
-#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
-#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
-#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
-#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
-#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
-#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
-#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
-#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
-#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
-#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
-#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
-#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
-#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
-#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
-#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
-#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
-#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
-#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
-#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
-#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
-#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
-#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
-#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
-#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
-#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
-#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_ICONFIG */
-#define MCF_INTC_ICONFIG_EMASK     (0x0020)
-#define MCF_INTC_ICONFIG_ELVLPRI1  (0x0200)
-#define MCF_INTC_ICONFIG_ELVLPRI2  (0x0400)
-#define MCF_INTC_ICONFIG_ELVLPRI3  (0x0800)
-#define MCF_INTC_ICONFIG_ELVLPRI4  (0x1000)
-#define MCF_INTC_ICONFIG_ELVLPRI5  (0x2000)
-#define MCF_INTC_ICONFIG_ELVLPRI6  (0x4000)
-#define MCF_INTC_ICONFIG_ELVLPRI7  (0x8000)
-
-/* Bit definitions and macros for MCF_INTC_SIMR */
-#define MCF_INTC_SIMR_SIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CIMR */
-#define MCF_INTC_CIMR_CIMR(x)      (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CLMASK */
-#define MCF_INTC_CLMASK_CLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SLMASK */
-#define MCF_INTC_SLMASK_SLMASK(x)  (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_ICR */
-#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SWIACK */
-#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_INTC_LIACK */
-#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
-
-/********************************************************************/
-/*********************************************************************
-*
-* LCD Controller (LCDC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_LCDC_LSSAR                  MCF_REG32(0xFC0AC000)
-#define MCF_LCDC_LSR                    MCF_REG32(0xFC0AC004)
-#define MCF_LCDC_LVPWR                  MCF_REG32(0xFC0AC008)
-#define MCF_LCDC_LCPR                   MCF_REG32(0xFC0AC00C)
-#define MCF_LCDC_LCWHBR                 MCF_REG32(0xFC0AC010)
-#define MCF_LCDC_LCCMR                  MCF_REG32(0xFC0AC014)
-#define MCF_LCDC_LPCR                   MCF_REG32(0xFC0AC018)
-#define MCF_LCDC_LHCR                   MCF_REG32(0xFC0AC01C)
-#define MCF_LCDC_LVCR                   MCF_REG32(0xFC0AC020)
-#define MCF_LCDC_LPOR                   MCF_REG32(0xFC0AC024)
-#define MCF_LCDC_LSCR                   MCF_REG32(0xFC0AC028)
-#define MCF_LCDC_LPCCR                  MCF_REG32(0xFC0AC02C)
-#define MCF_LCDC_LDCR                   MCF_REG32(0xFC0AC030)
-#define MCF_LCDC_LRMCR                  MCF_REG32(0xFC0AC034)
-#define MCF_LCDC_LICR                   MCF_REG32(0xFC0AC038)
-#define MCF_LCDC_LIER                   MCF_REG32(0xFC0AC03C)
-#define MCF_LCDC_LISR                   MCF_REG32(0xFC0AC040)
-#define MCF_LCDC_LGWSAR                 MCF_REG32(0xFC0AC050)
-#define MCF_LCDC_LGWSR                  MCF_REG32(0xFC0AC054)
-#define MCF_LCDC_LGWVPWR                MCF_REG32(0xFC0AC058)
-#define MCF_LCDC_LGWPOR                 MCF_REG32(0xFC0AC05C)
-#define MCF_LCDC_LGWPR                  MCF_REG32(0xFC0AC060)
-#define MCF_LCDC_LGWCR                  MCF_REG32(0xFC0AC064)
-#define MCF_LCDC_LGWDCR                 MCF_REG32(0xFC0AC068)
-#define MCF_LCDC_BPLUT_BASE             MCF_REG32(0xFC0AC800)
-#define MCF_LCDC_GWLUT_BASE             MCF_REG32(0xFC0ACC00)
-
-/* Bit definitions and macros for MCF_LCDC_LSSAR */
-#define MCF_LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LSR */
-#define MCF_LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LVPWR */
-#define MCF_LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LCPR */
-#define MCF_LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
-#define MCF_LCDC_LCPR_OP                (0x10000000)
-#define MCF_LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
-#define MCF_LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
-#define MCF_LCDC_LCPR_CC_OR             (0x40000000)
-#define MCF_LCDC_LCPR_CC_XOR            (0x80000000)
-#define MCF_LCDC_LCPR_CC_AND            (0xC0000000)
-#define MCF_LCDC_LCPR_OP_ON             (0x10000000)
-#define MCF_LCDC_LCPR_OP_OFF            (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCWHBR */
-#define MCF_LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
-#define MCF_LCDC_LCWHBR_BK_EN           (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_ON        (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCCMR */
-#define MCF_LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for MCF_LCDC_LPCR */
-#define MCF_LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LPCR_SHARP             (0x00000040)
-#define MCF_LCDC_LPCR_SCLKSEL           (0x00000080)
-#define MCF_LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
-#define MCF_LCDC_LPCR_ACDSEL            (0x00008000)
-#define MCF_LCDC_LPCR_REV_VS            (0x00010000)
-#define MCF_LCDC_LPCR_SWAP_SEL          (0x00020000)
-#define MCF_LCDC_LPCR_ENDSEL            (0x00040000)
-#define MCF_LCDC_LPCR_SCLKIDLE          (0x00080000)
-#define MCF_LCDC_LPCR_OEPOL             (0x00100000)
-#define MCF_LCDC_LPCR_CLKPOL            (0x00200000)
-#define MCF_LCDC_LPCR_LPPOL             (0x00400000)
-#define MCF_LCDC_LPCR_FLM               (0x00800000)
-#define MCF_LCDC_LPCR_PIXPOL            (0x01000000)
-#define MCF_LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
-#define MCF_LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
-#define MCF_LCDC_LPCR_COLOR             (0x40000000)
-#define MCF_LCDC_LPCR_TFT               (0x80000000)
-#define MCF_LCDC_LPCR_MODE_MONOCGROME   (0x00000000)
-#define MCF_LCDC_LPCR_MODE_CSTN         (0x40000000)
-#define MCF_LCDC_LPCR_MODE_TFT          (0xC0000000)
-#define MCF_LCDC_LPCR_PBSIZ_1           (0x00000000)
-#define MCF_LCDC_LPCR_PBSIZ_2           (0x10000000)
-#define MCF_LCDC_LPCR_PBSIZ_4           (0x20000000)
-#define MCF_LCDC_LPCR_PBSIZ_8           (0x30000000)
-#define MCF_LCDC_LPCR_BPIX_1bpp         (0x00000000)
-#define MCF_LCDC_LPCR_BPIX_2bpp         (0x02000000)
-#define MCF_LCDC_LPCR_BPIX_4bpp         (0x04000000)
-#define MCF_LCDC_LPCR_BPIX_8bpp         (0x06000000)
-#define MCF_LCDC_LPCR_BPIX_12bpp        (0x08000000)
-#define MCF_LCDC_LPCR_BPIX_16bpp        (0x0A000000)
-#define MCF_LCDC_LPCR_BPIX_18bpp        (0x0C000000)
-
-#define MCF_LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30) 
-
-/* Bit definitions and macros for MCF_LCDC_LHCR */
-#define MCF_LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LVCR */
-#define MCF_LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LPOR */
-#define MCF_LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LPCCR */
-#define MCF_LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LPCCR_CC_EN            (0x00000100)
-#define MCF_LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
-#define MCF_LCDC_LPCCR_LDMSK            (0x00008000)
-#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
-#define MCF_LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
-#define MCF_LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
-#define MCF_LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
-
-/* Bit definitions and macros for MCF_LCDC_LDCR */
-#define MCF_LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LDCR_BURST             (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LRMCR */
-#define MCF_LCDC_LRMCR_SEL_REF          (0x00000001)
-
-/* Bit definitions and macros for MCF_LCDC_LICR */
-#define MCF_LCDC_LICR_INTCON            (0x00000001)
-#define MCF_LCDC_LICR_INTSYN            (0x00000004)
-#define MCF_LCDC_LICR_GW_INT_CON        (0x00000010)
-
-/* Bit definitions and macros for MCF_LCDC_LIER */
-#define MCF_LCDC_LIER_BOF_EN            (0x00000001)
-#define MCF_LCDC_LIER_EOF_EN            (0x00000002)
-#define MCF_LCDC_LIER_ERR_RES_EN        (0x00000004)
-#define MCF_LCDC_LIER_UDR_ERR_EN        (0x00000008)
-#define MCF_LCDC_LIER_GW_BOF_EN         (0x00000010)
-#define MCF_LCDC_LIER_GW_EOF_EN         (0x00000020)
-#define MCF_LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
-#define MCF_LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LISR */
-#define MCF_LCDC_LISR_BOF               (0x00000001)
-#define MCF_LCDC_LISR_EOF               (0x00000002)
-#define MCF_LCDC_LISR_ERR_RES           (0x00000004)
-#define MCF_LCDC_LISR_UDR_ERR           (0x00000008)
-#define MCF_LCDC_LISR_GW_BOF            (0x00000010)
-#define MCF_LCDC_LISR_GW_EOF            (0x00000020)
-#define MCF_LCDC_LISR_GW_ERR_RES        (0x00000040)
-#define MCF_LCDC_LISR_GW_UDR_ERR        (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSAR */
-#define MCF_LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSR */
-#define MCF_LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
-#define MCF_LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPOR */
-#define MCF_LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPR */
-#define MCF_LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for MCF_LCDC_LGWCR */
-#define MCF_LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
-#define MCF_LCDC_LGWCR_GW_RVS           (0x00200000)
-#define MCF_LCDC_LGWCR_GWE              (0x00400000)
-#define MCF_LCDC_LGWCR_GWCKE            (0x00800000)
-#define MCF_LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_LCDC_LGWDCR */
-#define MCF_LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LGWDCR_GWBT            (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LSCR */
-#define MCF_LCDC_LSCR_PS_RISE_DELAY(x)    (((x)&0x0000003F)<<26)
-#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x)   (((x)&0x000000FF)<<16)
-#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
-#define MCF_LCDC_LSCR_GRAY_2(x)                   (((x)&0x0000000F)<<4)
-#define MCF_LCDC_LSCR_GRAY_1(x)                   (((x)&0x0000000F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
-#define MCF_LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
-#define MCF_LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
-
 /*********************************************************************
  *
  * Phase Locked Loop (PLL)
@@ -1925,10 +1107,10 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_PLL_PODR              MCF_REG08(0xFC0C0000)
-#define MCF_PLL_PLLCR             MCF_REG08(0xFC0C0004)
-#define MCF_PLL_PMDR              MCF_REG08(0xFC0C0008)
-#define MCF_PLL_PFDR              MCF_REG08(0xFC0C000C)
+#define MCF_PLL_PODR              0xFC0C0000
+#define MCF_PLL_PLLCR             0xFC0C0004
+#define MCF_PLL_PMDR              0xFC0C0008
+#define MCF_PLL_PFDR              0xFC0C000C
 
 /* Bit definitions and macros for MCF_PLL_PODR */
 #define MCF_PLL_PODR_BUSDIV(x)    (((x)&0x0F)<<0)
@@ -1951,15 +1133,15 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SCM_MPR                     MCF_REG32(0xFC000000)
-#define MCF_SCM_PACRA                   MCF_REG32(0xFC000020)
-#define MCF_SCM_PACRB                   MCF_REG32(0xFC000024)
-#define MCF_SCM_PACRC                   MCF_REG32(0xFC000028)
-#define MCF_SCM_PACRD                   MCF_REG32(0xFC00002C)
-#define MCF_SCM_PACRE                   MCF_REG32(0xFC000040)
-#define MCF_SCM_PACRF                   MCF_REG32(0xFC000044)
+#define MCF_SCM_MPR                     0xFC000000
+#define MCF_SCM_PACRA                   0xFC000020
+#define MCF_SCM_PACRB                   0xFC000024
+#define MCF_SCM_PACRC                   0xFC000028
+#define MCF_SCM_PACRD                   0xFC00002C
+#define MCF_SCM_PACRE                   0xFC000040
+#define MCF_SCM_PACRF                   0xFC000044
 
-#define MCF_SCM_BCR                     MCF_REG32(0xFC040024)
+#define MCF_SCM_BCR                     0xFC040024
 
 /*********************************************************************
  *
@@ -1968,17 +1150,16 @@
  *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SDRAMC_SDMR                 MCF_REG32(0xFC0B8000)
-#define MCF_SDRAMC_SDCR                 MCF_REG32(0xFC0B8004)
-#define MCF_SDRAMC_SDCFG1               MCF_REG32(0xFC0B8008)
-#define MCF_SDRAMC_SDCFG2               MCF_REG32(0xFC0B800C)
-#define MCF_SDRAMC_LIMP_FIX             MCF_REG32(0xFC0B8080)
-#define MCF_SDRAMC_SDDS                 MCF_REG32(0xFC0B8100)
-#define MCF_SDRAMC_SDCS0                MCF_REG32(0xFC0B8110)
-#define MCF_SDRAMC_SDCS1                MCF_REG32(0xFC0B8114)
-#define MCF_SDRAMC_SDCS2                MCF_REG32(0xFC0B8118)
-#define MCF_SDRAMC_SDCS3                MCF_REG32(0xFC0B811C)
-#define MCF_SDRAMC_SDCS(x)              MCF_REG32(0xFC0B8110+((x)*0x004))
+#define MCF_SDRAMC_SDMR                 0xFC0B8000
+#define MCF_SDRAMC_SDCR                 0xFC0B8004
+#define MCF_SDRAMC_SDCFG1               0xFC0B8008
+#define MCF_SDRAMC_SDCFG2               0xFC0B800C
+#define MCF_SDRAMC_LIMP_FIX             0xFC0B8080
+#define MCF_SDRAMC_SDDS                 0xFC0B8100
+#define MCF_SDRAMC_SDCS0                0xFC0B8110
+#define MCF_SDRAMC_SDCS1                0xFC0B8114
+#define MCF_SDRAMC_SDCS2                0xFC0B8118
+#define MCF_SDRAMC_SDCS3                0xFC0B811C
 
 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
 #define MCF_SDRAMC_SDMR_CMD             (0x00010000)
@@ -2046,143 +1227,9 @@
 #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE     (0x0000001E)
 #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE     (0x0000001F)
 
-/*********************************************************************
- *
- *      FlexCAN module registers
- *
- *********************************************************************/
-#define MCF_FLEXCAN_BASEADDR(x)         (0xFC020000+(x)*0x0800)
-#define MCF_FLEXCAN_CANMCR(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x00)
-#define MCF_FLEXCAN_CANCTRL(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x04)
-#define MCF_FLEXCAN_TIMER(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x08)
-#define MCF_FLEXCAN_RXGMASK(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x10)
-#define MCF_FLEXCAN_RX14MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x14)
-#define MCF_FLEXCAN_RX15MASK(x)         MCF_REG32(0xFC020000+(x)*0x0800+0x18)
-#define MCF_FLEXCAN_ERRCNT(x)           MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
-#define MCF_FLEXCAN_ERRSTAT(x)          MCF_REG32(0xFC020000+(x)*0x0800+0x20)
-#define MCF_FLEXCAN_IMASK(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x28)
-#define MCF_FLEXCAN_IFLAG(x)            MCF_REG32(0xFC020000+(x)*0x0800+0x30)
-
-#define MCF_FLEXCAN_MB_CNT(x,y)         MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
-#define MCF_FLEXCAN_MB_ID(x,y)          MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
-#define MCF_FLEXCAN_MB_DB(x,y,z)        MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
-
-/*
- *      FlexCAN Module Configuration Register
- */
-#define CANMCR_MDIS             (0x80000000)
-#define CANMCR_FRZ              (0x40000000)
-#define CANMCR_HALT             (0x10000000)
-#define CANMCR_SOFTRST          (0x02000000)
-#define CANMCR_FRZACK           (0x01000000)
-#define CANMCR_SUPV             (0x00800000)
-#define CANMCR_MAXMB(x)         ((x)&0x0F)
-
-/*
- *      FlexCAN Control Register
- */
-#define CANCTRL_PRESDIV(x)      (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)          (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)        (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)        (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK         (0x00008000)
-#define CANCTRL_ERRMSK          (0x00004000)
-#define CANCTRL_CLKSRC          (0x00002000)
-#define CANCTRL_LPB             (0x00001000)
-#define CANCTRL_SAMP            (0x00000080)
-#define CANCTRL_BOFFREC         (0x00000040)
-#define CANCTRL_TSYNC           (0x00000020)
-#define CANCTRL_LBUF            (0x00000010)
-#define CANCTRL_LOM             (0x00000008)
-#define CANCTRL_PROPSEG(x)      ((x)&0x07)
-
-/*
- *      FlexCAN Error Counter Register
- */
-#define ERRCNT_RXECTR(x)        (((x)&0xFF)<<8)
-#define ERRCNT_TXECTR(x)        ((x)&0xFF)
-
-/*
- *      FlexCAN Error and Status Register
- */
-#define ERRSTAT_BITERR(x)       (((x)&0x03)<<14)
-#define ERRSTAT_ACKERR           (0x00002000)
-#define ERRSTAT_CRCERR           (0x00001000)
-#define ERRSTAT_FRMERR           (0x00000800)
-#define ERRSTAT_STFERR           (0x00000400)
-#define ERRSTAT_TXWRN            (0x00000200)
-#define ERRSTAT_RXWRN            (0x00000100)
-#define ERRSTAT_IDLE             (0x00000080)
-#define ERRSTAT_TXRX             (0x00000040)
-#define ERRSTAT_FLTCONF(x)       (((x)&0x03)<<4)
-#define ERRSTAT_BOFFINT          (0x00000004)
-#define ERRSTAT_ERRINT           (0x00000002)
-
 /*
- *      Interrupt Mask Register
- */
-#define IMASK_BUF15M            (0x8000)
-#define IMASK_BUF14M            (0x4000)
-#define IMASK_BUF13M            (0x2000)
-#define IMASK_BUF12M            (0x1000)
-#define IMASK_BUF11M            (0x0800)
-#define IMASK_BUF10M            (0x0400)
-#define IMASK_BUF9M             (0x0200)
-#define IMASK_BUF8M             (0x0100)
-#define IMASK_BUF7M             (0x0080)
-#define IMASK_BUF6M             (0x0040)
-#define IMASK_BUF5M             (0x0020)
-#define IMASK_BUF4M             (0x0010)
-#define IMASK_BUF3M             (0x0008)
-#define IMASK_BUF2M             (0x0004)
-#define IMASK_BUF1M             (0x0002)
-#define IMASK_BUF0M             (0x0001)
-#define IMASK_BUFnM(x)          (0x1<<(x))
-#define IMASK_BUFF_ENABLE_ALL   (0x1111)
-#define IMASK_BUFF_DISABLE_ALL  (0x0000)
-
-/*
- *      Interrupt Flag Register
- */
-#define IFLAG_BUF15M            (0x8000)
-#define IFLAG_BUF14M            (0x4000)
-#define IFLAG_BUF13M            (0x2000)
-#define IFLAG_BUF12M            (0x1000)
-#define IFLAG_BUF11M            (0x0800)
-#define IFLAG_BUF10M            (0x0400)
-#define IFLAG_BUF9M             (0x0200)
-#define IFLAG_BUF8M             (0x0100)
-#define IFLAG_BUF7M             (0x0080)
-#define IFLAG_BUF6M             (0x0040)
-#define IFLAG_BUF5M             (0x0020)
-#define IFLAG_BUF4M             (0x0010)
-#define IFLAG_BUF3M             (0x0008)
-#define IFLAG_BUF2M             (0x0004)
-#define IFLAG_BUF1M             (0x0002)
-#define IFLAG_BUF0M             (0x0001)
-#define IFLAG_BUFF_SET_ALL      (0xFFFF)
-#define IFLAG_BUFF_CLEAR_ALL    (0x0000)
-#define IFLAG_BUFnM(x)          (0x1<<(x))
-
-/*
- *      Message Buffers
- */
-#define MB_CNT_CODE(x)          (((x)&0x0F)<<24)
-#define MB_CNT_SRR              (0x00400000)
-#define MB_CNT_IDE              (0x00200000)
-#define MB_CNT_RTR              (0x00100000)
-#define MB_CNT_LENGTH(x)        (((x)&0x0F)<<16)
-#define MB_CNT_TIMESTAMP(x)     ((x)&0xFFFF)
-#define MB_ID_STD(x)            (((x)&0x07FF)<<18)
-#define MB_ID_EXT(x)            ((x)&0x3FFFF)
-
-/*********************************************************************
- *
  * Edge Port Module (EPORT)
- *
- *********************************************************************/
-
-/* Register read/write macros */
+ */
 #define MCFEPORT_EPPAR                (0xFC094000)
 #define MCFEPORT_EPDDR                (0xFC094002)
 #define MCFEPORT_EPIER                (0xFC094003)
@@ -2190,91 +1237,5 @@
 #define MCFEPORT_EPPDR                (0xFC094005)
 #define MCFEPORT_EPFR                 (0xFC094006)
 
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x)       (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x)       (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x)       (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x)       (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x)       (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x)       (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x)       (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_LEVEL          (0)
-#define MCF_EPORT_EPPAR_RISING         (1)
-#define MCF_EPORT_EPPAR_FALLING        (2)
-#define MCF_EPORT_EPPAR_BOTH           (3)
-#define MCF_EPORT_EPPAR_EPPA7_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA7_RISING   (0x4000)
-#define MCF_EPORT_EPPAR_EPPA7_FALLING  (0x8000)
-#define MCF_EPORT_EPPAR_EPPA7_BOTH     (0xC000)
-#define MCF_EPORT_EPPAR_EPPA6_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA6_RISING   (0x1000)
-#define MCF_EPORT_EPPAR_EPPA6_FALLING  (0x2000)
-#define MCF_EPORT_EPPAR_EPPA6_BOTH     (0x3000)
-#define MCF_EPORT_EPPAR_EPPA5_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA5_RISING   (0x0400)
-#define MCF_EPORT_EPPAR_EPPA5_FALLING  (0x0800)
-#define MCF_EPORT_EPPAR_EPPA5_BOTH     (0x0C00)
-#define MCF_EPORT_EPPAR_EPPA4_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA4_RISING   (0x0100)
-#define MCF_EPORT_EPPAR_EPPA4_FALLING  (0x0200)
-#define MCF_EPORT_EPPAR_EPPA4_BOTH     (0x0300)
-#define MCF_EPORT_EPPAR_EPPA3_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA3_RISING   (0x0040)
-#define MCF_EPORT_EPPAR_EPPA3_FALLING  (0x0080)
-#define MCF_EPORT_EPPAR_EPPA3_BOTH     (0x00C0)
-#define MCF_EPORT_EPPAR_EPPA2_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA2_RISING   (0x0010)
-#define MCF_EPORT_EPPAR_EPPA2_FALLING  (0x0020)
-#define MCF_EPORT_EPPAR_EPPA2_BOTH     (0x0030)
-#define MCF_EPORT_EPPAR_EPPA1_LEVEL    (0x0000)
-#define MCF_EPORT_EPPAR_EPPA1_RISING   (0x0004)
-#define MCF_EPORT_EPPAR_EPPA1_FALLING  (0x0008)
-#define MCF_EPORT_EPPAR_EPPA1_BOTH     (0x000C)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1          (0x02)
-#define MCF_EPORT_EPDDR_EPDD2          (0x04)
-#define MCF_EPORT_EPDDR_EPDD3          (0x08)
-#define MCF_EPORT_EPDDR_EPDD4          (0x10)
-#define MCF_EPORT_EPDDR_EPDD5          (0x20)
-#define MCF_EPORT_EPDDR_EPDD6          (0x40)
-#define MCF_EPORT_EPDDR_EPDD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1          (0x02)
-#define MCF_EPORT_EPIER_EPIE2          (0x04)
-#define MCF_EPORT_EPIER_EPIE3          (0x08)
-#define MCF_EPORT_EPIER_EPIE4          (0x10)
-#define MCF_EPORT_EPIER_EPIE5          (0x20)
-#define MCF_EPORT_EPIER_EPIE6          (0x40)
-#define MCF_EPORT_EPIER_EPIE7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1            (0x02)
-#define MCF_EPORT_EPDR_EPD2            (0x04)
-#define MCF_EPORT_EPDR_EPD3            (0x08)
-#define MCF_EPORT_EPDR_EPD4            (0x10)
-#define MCF_EPORT_EPDR_EPD5            (0x20)
-#define MCF_EPORT_EPDR_EPD6            (0x40)
-#define MCF_EPORT_EPDR_EPD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1          (0x02)
-#define MCF_EPORT_EPPDR_EPPD2          (0x04)
-#define MCF_EPORT_EPPDR_EPPD3          (0x08)
-#define MCF_EPORT_EPPDR_EPPD4          (0x10)
-#define MCF_EPORT_EPPDR_EPPD5          (0x20)
-#define MCF_EPORT_EPPDR_EPPD6          (0x40)
-#define MCF_EPORT_EPPDR_EPPD7          (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1            (0x02)
-#define MCF_EPORT_EPFR_EPF2            (0x04)
-#define MCF_EPORT_EPFR_EPF3            (0x08)
-#define MCF_EPORT_EPFR_EPF4            (0x10)
-#define MCF_EPORT_EPFR_EPF5            (0x20)
-#define MCF_EPORT_EPFR_EPF6            (0x40)
-#define MCF_EPORT_EPFR_EPF7            (0x80)
-
 /********************************************************************/
 #endif  /* m532xsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 79f58dd6a83..a7550bc5cd1 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,55 +23,55 @@
 /*
  *      Define the 5407 SIM register set addresses.
  */
-#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
-#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
-#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
-#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
-
-#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
-#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
-#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
-#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
-#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
-#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
-#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
-#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
-#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
-#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
-#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
-#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
+#define MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
+#define MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl */
+#define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
+#define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
+#define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
+#define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
+#define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
+#define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
+#define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
+#define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
+
+#define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
+#define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
+#define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
+#define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
+#define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
+#define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
+#define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
+#define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
+#define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
+#define MCFSIM_CSAR5            (MCF_MBAR + 0xbc)       /* CS 5 Address reg */
+#define MCFSIM_CSMR5            (MCF_MBAR + 0xc0)       /* CS 5 Mask reg */
+#define MCFSIM_CSCR5            (MCF_MBAR + 0xc6)       /* CS 5 Control reg */
+#define MCFSIM_CSAR6            (MCF_MBAR + 0xc8)       /* CS 6 Address reg */
+#define MCFSIM_CSMR6            (MCF_MBAR + 0xcc)       /* CS 6 Mask reg */
+#define MCFSIM_CSCR6            (MCF_MBAR + 0xd2)       /* CS 6 Control reg */
+#define MCFSIM_CSAR7            (MCF_MBAR + 0xd4)       /* CS 7 Address reg */
+#define MCFSIM_CSMR7            (MCF_MBAR + 0xd8)       /* CS 7 Mask reg */
+#define MCFSIM_CSCR7            (MCF_MBAR + 0xde)       /* CS 7 Control reg */
 
 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
@@ -102,9 +102,9 @@
 /*
  * Generic GPIO support
  */
-#define MCFGPIO_PIN_MAX                 16
-#define MCFGPIO_IRQ_MAX                 -1
-#define MCFGPIO_IRQ_VECBASE             -1
+#define MCFGPIO_PIN_MAX         16
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
 
 /*
  *      Some symbol defines for the above...
@@ -130,9 +130,9 @@
 /*
  *       Defines for the IRQPAR Register
  */
-#define IRQ5_LEVEL4     0x80
-#define IRQ3_LEVEL6     0x40
-#define IRQ1_LEVEL2     0x20
+#define IRQ5_LEVEL4             0x80
+#define IRQ3_LEVEL6             0x40
+#define IRQ1_LEVEL2             0x20
 
 /*
  *      Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd87ae7..0b69cd1ed0e 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_GPT_GMS0       0x000800
-#define MCF_GPT_GCIR0      0x000804
-#define MCF_GPT_GPWM0      0x000808
-#define MCF_GPT_GSR0       0x00080C
-#define MCF_GPT_GMS1       0x000810
-#define MCF_GPT_GCIR1      0x000814
-#define MCF_GPT_GPWM1      0x000818
-#define MCF_GPT_GSR1       0x00081C
-#define MCF_GPT_GMS2       0x000820
-#define MCF_GPT_GCIR2      0x000824
-#define MCF_GPT_GPWM2      0x000828
-#define MCF_GPT_GSR2       0x00082C
-#define MCF_GPT_GMS3       0x000830
-#define MCF_GPT_GCIR3      0x000834
-#define MCF_GPT_GPWM3      0x000838
-#define MCF_GPT_GSR3       0x00083C
-#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0       (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0      (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0      (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0       (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1       (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1      (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1      (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1       (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2       (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2      (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2      (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2       (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3       (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3      (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3      (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3       (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x)     (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x)    (MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x)    (MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x)     (MCF_MBAR + 0x00080C + ((x) * 0x010))
 
 /* Bit definitions and macros for MCF_GPT_GMS */
 #define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3c5e0dbdad..d3bd8388742 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -47,6 +47,12 @@
 #define MCF_IRQ_UART3           (MCFINT_VECBASE + 32)
 
 /*
+ *      Slice Timer support.
+ */
+#define MCFSLT_TIMER0           (MCF_MBAR + 0x900)      /* Base addr TIMER0 */
+#define MCFSLT_TIMER1           (MCF_MBAR + 0x910)      /* Base addr TIMER1 */
+
+/*
  *      Generic GPIO support
  */
 #define MCFGPIO_PIN_MAX         0       /* I am too lazy to count */
@@ -64,15 +70,25 @@
 #define MCFEPORT_EPFR           (MCF_MBAR + 0xf0c)      /* Flags */
 
 /*
- *      Some PSC related definitions
+ *      Pin Assignment register definitions
  */
-#define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
+#define MCFGPIO_PAR_FBCTL       (MCF_MBAR + 0xA40)
+#define MCFGPIO_PAR_FBCS        (MCF_MBAR + 0xA42)
+#define MCFGPIO_PAR_DMA         (MCF_MBAR + 0xA43)
+#define MCFGPIO_PAR_FECI2CIRQ   (MCF_MBAR + 0xA44)
+#define MCFGPIO_PAR_PCIBG       (MCF_MBAR + 0xA48)      /* PCI bus grant */
+#define MCFGPIO_PAR_PCIBR       (MCF_MBAR + 0xA4A)      /* PCI */
+#define MCFGPIO_PAR_PSC0        (MCF_MBAR + 0xA4F)
+#define MCFGPIO_PAR_PSC1        (MCF_MBAR + 0xA4E)
+#define MCFGPIO_PAR_PSC2        (MCF_MBAR + 0xA4D)
+#define MCFGPIO_PAR_PSC3        (MCF_MBAR + 0xA4C)
+#define MCFGPIO_PAR_DSPI        (MCF_MBAR + 0xA50)
+#define MCFGPIO_PAR_TIMER       (MCF_MBAR + 0xA52)
+
 #define MCF_PAR_SDA             (0x0008)
 #define MCF_PAR_SCL             (0x0004)
 #define MCF_PAR_PSC_TXD         (0x04)
 #define MCF_PAR_PSC_RXD         (0x08)
-#define MCF_PAR_PSC_RTS(x)      (((x)&0x03)<<4)
-#define MCF_PAR_PSC_CTS(x)      (((x)&0x03)<<6)
 #define MCF_PAR_PSC_CTS_GPIO    (0x00)
 #define MCF_PAR_PSC_CTS_BCLK    (0x80)
 #define MCF_PAR_PSC_CTS_CTS     (0xC0)
@@ -81,7 +97,4 @@
 #define MCF_PAR_PSC_RTS_RTS     (0x30)
 #define MCF_PAR_PSC_CANRX       (0x40)
 
-#define MCF_PAR_PCIBG           (CONFIG_MBAR + 0xa48)   /* PCI bus grant */
-#define MCF_PAR_PCIBR           (CONFIG_MBAR + 0xa4a)   /* PCI */
-
 #endif  /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index d0d0ecba533..c2314b6f8ca 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,13 +13,6 @@
 /****************************************************************************/
 
 /*
- *      Get address specific defines for the 547x.
- */
-#define MCFSLT_TIMER0           0x900   /* Base address of TIMER0 */
-#define MCFSLT_TIMER1           0x910   /* Base address of TIMER1 */
-
-
-/*
  *      Define the SLT timer register set addresses.
  */
 #define MCFSLT_STCNT            0x00    /* Terminal count */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 4dec2d9fb99..2a7a7667d80 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,6 +21,7 @@
 #ifdef CONFIG_COLDFIRE
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/io.h>
 #endif
 
 /*---------------------------------------------------------------------------*/
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
  */
 static __inline__ unsigned int mcf_getppdata(void)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        return((unsigned int) *pp);
+        return readw(MCFSIM_PBDAT);
 }
 
 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
 {
-        volatile unsigned short *pp;
-        pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-        *pp = (*pp & ~mask) | bits;
+        write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
 }
 #endif