diff options
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 7f0c2c3660f..fdf45e6807c 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h | |||
| @@ -25,41 +25,41 @@ | |||
| 25 | /* | 25 | /* |
| 26 | * Define the 5249 SIM register set addresses. | 26 | * Define the 5249 SIM register set addresses. |
| 27 | */ | 27 | */ |
| 28 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | 28 | #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ |
| 29 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | 29 | #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ |
| 30 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | 30 | #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ |
| 31 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | 31 | #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ |
| 32 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | 32 | #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ |
| 33 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | 33 | #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ |
| 34 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | 34 | #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ |
| 35 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | 35 | #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ |
| 36 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | 36 | #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ |
| 37 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | 37 | #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ |
| 38 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | 38 | #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ |
| 39 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | 39 | #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ |
| 40 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | 40 | #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ |
| 41 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | 41 | #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ |
| 42 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | 42 | #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ |
| 43 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | 43 | #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ |
| 44 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | 44 | #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ |
| 45 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | 45 | #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ |
| 46 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | 46 | #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ |
| 47 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | 47 | #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ |
| 48 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | 48 | #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ |
| 49 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | 49 | #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ |
| 50 | 50 | ||
| 51 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | 51 | #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ |
| 52 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | 52 | #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ |
| 53 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | 53 | #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ |
| 54 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | 54 | #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ |
| 55 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | 55 | #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ |
| 56 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | 56 | #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ |
| 57 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ | 57 | #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ |
| 58 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | 58 | #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ |
| 59 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | 59 | #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ |
| 60 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ | 60 | #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ |
| 61 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | 61 | #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ |
| 62 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | 62 | #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ |
| 63 | 63 | ||
| 64 | #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ | 64 | #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ |
| 65 | #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ | 65 | #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ |
| @@ -134,23 +134,23 @@ | |||
| 134 | #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ | 134 | #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ |
| 135 | #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ | 135 | #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ |
| 136 | 136 | ||
| 137 | #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ | 137 | #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ |
| 138 | #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ | 138 | #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ |
| 139 | #define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ | 139 | #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ |
| 140 | 140 | ||
| 141 | #define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ | 141 | #define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */ |
| 142 | #define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ | 142 | #define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */ |
| 143 | #define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ | 143 | #define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */ |
| 144 | #define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ | 144 | #define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */ |
| 145 | #define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ | 145 | #define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */ |
| 146 | #define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ | 146 | #define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */ |
| 147 | #define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ | 147 | #define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */ |
| 148 | #define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ | 148 | #define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */ |
| 149 | 149 | ||
| 150 | #define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ | 150 | #define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */ |
| 151 | 151 | ||
| 152 | #define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ | 152 | #define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */ |
| 153 | #define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ | 153 | #define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */ |
| 154 | 154 | ||
| 155 | /* | 155 | /* |
| 156 | * Define the base interrupt for the second interrupt controller. | 156 | * Define the base interrupt for the second interrupt controller. |