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-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c9
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c5
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c9
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c1
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c5
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c5
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c5
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/include/mach/at91_matrix.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h36
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h74
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h84
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h42
-rw-r--r--arch/arm/mach-at91/setup.c9
25 files changed, 194 insertions, 150 deletions
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index e9653328092..5c15d144dce 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -327,6 +327,7 @@ static void __init at91sam9260_ioremap_registers(void)
327 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); 327 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
328 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 328 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
329 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 329 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
330 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
330} 331}
331 332
332static void __init at91sam9260_initialize(void) 333static void __init at91sam9260_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b..b93a3376e7b 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22#include <mach/at91sam9260.h> 22#include <mach/at91sam9260.h>
23#include <mach/at91sam9260_matrix.h> 23#include <mach/at91sam9260_matrix.h>
24#include <mach/at91_matrix.h>
24#include <mach/at91sam9_smc.h> 25#include <mach/at91sam9_smc.h>
25 26
26#include "generic.h" 27#include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
422 if (!data) 423 if (!data)
423 return; 424 return;
424 425
425 csa = at91_sys_read(AT91_MATRIX_EBICSA); 426 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
426 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 427 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
427 428
428 /* enable pin */ 429 /* enable pin */
429 if (gpio_is_valid(data->enable_pin)) 430 if (gpio_is_valid(data->enable_pin))
@@ -1265,7 +1266,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1265 if (!data) 1266 if (!data)
1266 return; 1267 return;
1267 1268
1268 csa = at91_sys_read(AT91_MATRIX_EBICSA); 1269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
1269 1270
1270 switch (data->chipselect) { 1271 switch (data->chipselect) {
1271 case 4: 1272 case 4:
@@ -1288,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1288 return; 1289 return;
1289 } 1290 }
1290 1291
1291 at91_sys_write(AT91_MATRIX_EBICSA, csa); 1292 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
1292 1293
1293 if (gpio_is_valid(data->rst_pin)) { 1294 if (gpio_is_valid(data->rst_pin)) {
1294 at91_set_multi_drive(data->rst_pin, 0); 1295 at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index d7f51d6f957..50971e6dd55 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -285,6 +285,7 @@ static void __init at91sam9261_ioremap_registers(void)
285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); 285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
286 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 286 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
287 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 287 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
288 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
288} 289}
289 290
290static void __init at91sam9261_initialize(void) 291static void __init at91sam9261_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3..52c1f1a3819 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
24#include <mach/board.h> 24#include <mach/board.h>
25#include <mach/at91sam9261.h> 25#include <mach/at91sam9261.h>
26#include <mach/at91sam9261_matrix.h> 26#include <mach/at91sam9261_matrix.h>
27#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h> 28#include <mach/at91sam9_smc.h>
28 29
29#include "generic.h" 30#include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
236 if (!data) 237 if (!data)
237 return; 238 return;
238 239
239 csa = at91_sys_read(AT91_MATRIX_EBICSA); 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
240 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
241 242
242 /* enable pin */ 243 /* enable pin */
243 if (gpio_is_valid(data->enable_pin)) 244 if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 8bdba2a04b1..5fd6fe86719 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -306,6 +306,7 @@ static void __init at91sam9263_ioremap_registers(void)
306 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 306 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
307 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 307 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
308 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 308 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
309 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
309} 310}
310 311
311static void __init at91sam9263_initialize(void) 312static void __init at91sam9263_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 49aa6a9f432..545826b16a8 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/at91sam9263.h> 24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h> 25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h> 27#include <mach/at91sam9_smc.h>
27 28
28#include "generic.h" 29#include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
409 * we assume SMC timings are configured by board code, 410 * we assume SMC timings are configured by board code,
410 * except True IDE where timings are controlled by driver 411 * except True IDE where timings are controlled by driver
411 */ 412 */
412 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 413 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
413 switch (data->chipselect) { 414 switch (data->chipselect) {
414 case 4: 415 case 4:
415 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */ 416 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
428 data->chipselect); 429 data->chipselect);
429 return; 430 return;
430 } 431 }
431 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); 432 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
432 433
433 if (gpio_is_valid(data->det_pin)) { 434 if (gpio_is_valid(data->det_pin)) {
434 at91_set_gpio_input(data->det_pin, 1); 435 at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
496 if (!data) 497 if (!data)
497 return; 498 return;
498 499
499 csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 500 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
500 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); 501 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
501 502
502 /* enable pin */ 503 /* enable pin */
503 if (gpio_is_valid(data->enable_pin)) 504 if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 5d2ff90ca85..3726160b6aa 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -333,6 +333,7 @@ static void __init at91sam9g45_ioremap_registers(void)
333 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); 333 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
334 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 334 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
335 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 335 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
336 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
336} 337}
337 338
338static void __init at91sam9g45_initialize(void) 339static void __init at91sam9g45_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index bd4e68cd3e2..8c036ff10bb 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,6 +25,7 @@
25#include <mach/board.h> 25#include <mach/board.h>
26#include <mach/at91sam9g45.h> 26#include <mach/at91sam9g45.h>
27#include <mach/at91sam9g45_matrix.h> 27#include <mach/at91sam9g45_matrix.h>
28#include <mach/at91_matrix.h>
28#include <mach/at91sam9_smc.h> 29#include <mach/at91sam9_smc.h>
29#include <mach/at_hdmac.h> 30#include <mach/at_hdmac.h>
30#include <mach/atmel-mci.h> 31#include <mach/atmel-mci.h>
@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
557 if (!data) 558 if (!data)
558 return; 559 return;
559 560
560 csa = at91_sys_read(AT91_MATRIX_EBICSA); 561 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
561 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 562 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
562 563
563 /* enable pin */ 564 /* enable pin */
564 if (gpio_is_valid(data->enable_pin)) 565 if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index e86c50b19d6..d95ff978921 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -290,6 +290,7 @@ static void __init at91sam9rl_ioremap_registers(void)
290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); 290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
291 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 291 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
292 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 292 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
293 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
293} 294}
294 295
295static void __init at91sam9rl_initialize(void) 296static void __init at91sam9rl_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9be71c11d0f..936cf20bc54 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
20#include <mach/board.h> 20#include <mach/board.h>
21#include <mach/at91sam9rl.h> 21#include <mach/at91sam9rl.h>
22#include <mach/at91sam9rl_matrix.h> 22#include <mach/at91sam9rl_matrix.h>
23#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h> 24#include <mach/at91sam9_smc.h>
24#include <mach/at_hdmac.h> 25#include <mach/at_hdmac.h>
25 26
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
265 if (!data) 266 if (!data)
266 return; 267 return;
267 268
268 csa = at91_sys_read(AT91_MATRIX_EBICSA); 269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
269 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 270 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
270 271
271 /* enable pin */ 272 /* enable pin */
272 if (gpio_is_valid(data->enable_pin)) 273 if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326..989e1c5a9ca 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
43#include <mach/board.h> 43#include <mach/board.h>
44#include <mach/at91sam9_smc.h> 44#include <mach/at91sam9_smc.h>
45#include <mach/at91sam9260_matrix.h> 45#include <mach/at91sam9260_matrix.h>
46#include <mach/at91_matrix.h>
46 47
47#include "sam9_smc.h" 48#include "sam9_smc.h"
48#include "generic.h" 49#include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
238{ 239{
239 unsigned long csa; 240 unsigned long csa;
240 241
241 csa = at91_sys_read(AT91_MATRIX_EBICSA); 242 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
242 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); 243 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
243 244
244 /* configure chip-select 0 (NOR) */ 245 /* configure chip-select 0 (NOR) */
245 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); 246 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 4e322f3492b..dc74ec04357 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -67,6 +67,9 @@ extern void at91sam9g45_restart(char, const char *);
67/* shutdown */ 67/* shutdown */
68extern void at91_ioremap_shdwc(u32 base_addr); 68extern void at91_ioremap_shdwc(u32 base_addr);
69 69
70/* Matrix */
71extern void at91_ioremap_matrix(u32 base_addr);
72
70 /* GPIO */ 73 /* GPIO */
71#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ 74#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
72#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ 75#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 00000000000..02fae9de746
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
3 *
4 * Under GPLv2
5 */
6
7#ifndef __MACH_AT91_MATRIX_H__
8#define __MACH_AT91_MATRIX_H__
9
10#ifndef __ASSEMBLY__
11extern void __iomem *at91_matrix_base;
12
13#define at91_matrix_read(field) \
14 __raw_readl(at91_matrix_base + field)
15
16#define at91_matrix_write(field, value) \
17 __raw_writel(value, at91_matrix_base + field);
18
19#else
20.extern at91_matrix_base
21#endif
22
23#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb5114181..fbde3064b62 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -95,8 +95,6 @@
95#define AT91_USART2 AT91RM9200_BASE_US2 95#define AT91_USART2 AT91RM9200_BASE_US2
96#define AT91_USART3 AT91RM9200_BASE_US3 96#define AT91_USART3 AT91RM9200_BASE_US3
97 97
98#define AT91_MATRIX 0 /* not supported */
99
100/* 98/*
101 * Internal Memory. 99 * Internal Memory.
102 */ 100 */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278ade..2bde6496cd4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -81,12 +81,12 @@
81 * System Peripherals (offset from AT91_BASE_SYS) 81 * System Peripherals (offset from AT91_BASE_SYS)
82 */ 82 */
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 84#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
87 86
88#define AT91SAM9260_BASE_ECC 0xffffe800 87#define AT91SAM9260_BASE_ECC 0xffffe800
89#define AT91SAM9260_BASE_SMC 0xffffec00 88#define AT91SAM9260_BASE_SMC 0xffffec00
89#define AT91SAM9260_BASE_MATRIX 0xffffee00
90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
91#define AT91SAM9260_BASE_PIOA 0xfffff400 91#define AT91SAM9260_BASE_PIOA 0xfffff400
92#define AT91SAM9260_BASE_PIOB 0xfffff600 92#define AT91SAM9260_BASE_PIOB 0xfffff600
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921..f459df42062 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
15#ifndef AT91SAM9260_MATRIX_H 15#ifndef AT91SAM9260_MATRIX_H
16#define AT91SAM9260_MATRIX_H 16#define AT91SAM9260_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
25#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 25#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
26#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 26#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -28,11 +28,11 @@
28#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 28#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
30 30
31#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 31#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
32#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 32#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
33#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 33#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
34#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 34#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
35#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 35#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,11 +43,11 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -55,11 +55,11 @@
55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
57 57
58#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 58#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
61 61
62#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ 62#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
64#define AT91_MATRIX_CS1A_SMC (0 << 1) 64#define AT91_MATRIX_CS1A_SMC (0 << 1)
65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570..6dcff277c02 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -66,11 +66,11 @@
66 * System Peripherals (offset from AT91_BASE_SYS) 66 * System Peripherals (offset from AT91_BASE_SYS)
67 */ 67 */
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 69#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 70#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
72 71
73#define AT91SAM9261_BASE_SMC 0xffffec00 72#define AT91SAM9261_BASE_SMC 0xffffec00
73#define AT91SAM9261_BASE_MATRIX 0xffffee00
74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
75#define AT91SAM9261_BASE_PIOA 0xfffff400 75#define AT91SAM9261_BASE_PIOA 0xfffff400
76#define AT91SAM9261_BASE_PIOB 0xfffff600 76#define AT91SAM9261_BASE_PIOB 0xfffff600
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d..a50cdf8b8ca 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9261_MATRIX_H 15#ifndef AT91SAM9261_MATRIX_H
16#define AT91SAM9261_MATRIX_H 16#define AT91SAM9261_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ 18#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
21 21
22#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ 22#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
23#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ 23#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
24#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ 24#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
25#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ 25#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
26#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ 26#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -31,7 +31,7 @@
31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
33 33
34#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ 34#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
36#define AT91_MATRIX_ITCM_0 (0 << 0) 36#define AT91_MATRIX_ITCM_0 (0 << 0)
37#define AT91_MATRIX_ITCM_16 (5 << 0) 37#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -43,7 +43,7 @@
43#define AT91_MATRIX_DTCM_32 (6 << 4) 43#define AT91_MATRIX_DTCM_32 (6 << 4)
44#define AT91_MATRIX_DTCM_64 (7 << 4) 44#define AT91_MATRIX_DTCM_64 (7 << 4)
45 45
46#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ 46#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
48#define AT91_MATRIX_CS1A_SMC (0 << 1) 48#define AT91_MATRIX_CS1A_SMC (0 << 1)
49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
@@ -58,7 +58,7 @@
58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
60 60
61#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ 61#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ 62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
63 63
64#endif 64#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962..fe73bfa265e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -76,7 +76,6 @@
76 */ 76 */
77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) 77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 79#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 80#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
82 81
@@ -84,6 +83,7 @@
84#define AT91SAM9263_BASE_SMC0 0xffffe400 83#define AT91SAM9263_BASE_SMC0 0xffffe400
85#define AT91SAM9263_BASE_ECC1 0xffffe600 84#define AT91SAM9263_BASE_ECC1 0xffffe600
86#define AT91SAM9263_BASE_SMC1 0xffffea00 85#define AT91SAM9263_BASE_SMC1 0xffffea00
86#define AT91SAM9263_BASE_MATRIX 0xffffec00
87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
88#define AT91SAM9263_BASE_PIOA 0xfffff200 88#define AT91SAM9263_BASE_PIOA 0xfffff200
89#define AT91SAM9263_BASE_PIOB 0xfffff400 89#define AT91SAM9263_BASE_PIOB 0xfffff400
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f..ebb5fdb565e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9263_MATRIX_H 15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H 16#define AT91SAM9263_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -31,14 +31,14 @@
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33 33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 34#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 35#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 36#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 37#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 38#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 39#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 40#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 41#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -49,22 +49,22 @@
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51 51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 52#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 53#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 54#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 55#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 56#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 57#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 58#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 59#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 60#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 61#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 62#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 63#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 64#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 65#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 66#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 67#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -75,7 +75,7 @@
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ 75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ 76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77 77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 78#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2) 81#define AT91_MATRIX_RCB2 (1 << 2)
@@ -86,7 +86,7 @@
86#define AT91_MATRIX_RCB7 (1 << 7) 86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8) 87#define AT91_MATRIX_RCB8 (1 << 8)
88 88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 89#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0) 91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0) 92#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -96,7 +96,7 @@
96#define AT91_MATRIX_DTCM_16 (5 << 4) 96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4) 97#define AT91_MATRIX_DTCM_32 (6 << 4)
98 98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 99#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ 100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) 101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) 102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
@@ -114,7 +114,7 @@
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) 114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) 115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116 116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ 117#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ 118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) 119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) 120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea086..c8fe455f631 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -88,13 +88,13 @@
88 */ 88 */
89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) 89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 91#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 92#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
94 93
95#define AT91SAM9G45_BASE_ECC 0xffffe200 94#define AT91SAM9G45_BASE_ECC 0xffffe200
96#define AT91SAM9G45_BASE_DMA 0xffffec00 95#define AT91SAM9G45_BASE_DMA 0xffffec00
97#define AT91SAM9G45_BASE_SMC 0xffffe800 96#define AT91SAM9G45_BASE_SMC 0xffffe800
97#define AT91SAM9G45_BASE_MATRIX 0xffffea00
98#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 98#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
99#define AT91SAM9G45_BASE_PIOA 0xfffff200 99#define AT91SAM9G45_BASE_PIOA 0xfffff200
100#define AT91SAM9G45_BASE_PIOB 0xfffff400 100#define AT91SAM9G45_BASE_PIOB 0xfffff400
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0ae..b76e2ed2fbc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
15#ifndef AT91SAM9G45_MATRIX_H 15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H 16#define AT91SAM9G45_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ 27#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ 28#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ 29#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -37,14 +37,14 @@
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0) 38#define AT91_MATRIX_ULBT_128 (7 << 0)
39 39
40#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 40#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 41#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 42#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 43#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 44#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 45#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 46#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 47#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -52,22 +52,22 @@
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ 53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54 54
55#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 55#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 56#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 57#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 58#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 59#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 60#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 61#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 62#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 63#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 64#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 65#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 66#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 67#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 68#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 69#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 70#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -81,7 +81,7 @@
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ 81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ 82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83 83
84#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 84#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2) 87#define AT91_MATRIX_RCB2 (1 << 2)
@@ -95,7 +95,7 @@
95#define AT91_MATRIX_RCB10 (1 << 10) 95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11) 96#define AT91_MATRIX_RCB11 (1 << 11)
97 97
98#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ 98#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0) 100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0) 101#define AT91_MATRIX_ITCM_32 (6 << 0)
@@ -107,12 +107,12 @@
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) 107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) 108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109 109
110#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ 110#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ 111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0) 112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0) 113#define AT91C_VDEC_SEL_ON (1 << 0)
114 114
115#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ 115#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
@@ -138,13 +138,13 @@
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140 140
141#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ 141#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ 142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) 143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) 144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ 145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146 146
147#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ 147#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ 148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) 149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0) 150#define AT91_MATRIX_WPSR_WPV (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118d..51edc25b466 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -70,7 +70,6 @@
70 * System Peripherals (offset from AT91_BASE_SYS) 70 * System Peripherals (offset from AT91_BASE_SYS)
71 */ 71 */
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 73#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 74#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 75#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
@@ -78,6 +77,7 @@
78#define AT91SAM9RL_BASE_DMA 0xffffe600 77#define AT91SAM9RL_BASE_DMA 0xffffe600
79#define AT91SAM9RL_BASE_ECC 0xffffe800 78#define AT91SAM9RL_BASE_ECC 0xffffe800
80#define AT91SAM9RL_BASE_SMC 0xffffec00 79#define AT91SAM9RL_BASE_SMC 0xffffec00
80#define AT91SAM9RL_BASE_MATRIX 0xffffee00
81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
82#define AT91SAM9RL_BASE_PIOA 0xfffff400 82#define AT91SAM9RL_BASE_PIOA 0xfffff400
83#define AT91SAM9RL_BASE_PIOB 0xfffff600 83#define AT91SAM9RL_BASE_PIOB 0xfffff600
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe..6d160adadaf 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
14#ifndef AT91SAM9RL_MATRIX_H 14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H 15#define AT91SAM9RL_MATRIX_H
16 16
17#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 17#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 18#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 19#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 20#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 21#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 22#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -27,12 +27,12 @@
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29 29
30#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 30#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 31#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 32#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 33#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 34#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 35#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,12 +43,12 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 51#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -56,7 +56,7 @@
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58 58
59#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 59#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2) 62#define AT91_MATRIX_RCB2 (1 << 2)
@@ -64,7 +64,7 @@
64#define AT91_MATRIX_RCB4 (1 << 4) 64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5) 65#define AT91_MATRIX_RCB5 (1 << 5)
66 66
67#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 67#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0) 69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0) 70#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -74,7 +74,7 @@
74#define AT91_MATRIX_DTCM_16 (5 << 4) 74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4) 75#define AT91_MATRIX_DTCM_32 (6 << 4)
76 76
77#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 77#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1) 79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 620c67e8f81..372396c2ecb 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -276,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
276 panic("Impossible to ioremap at91_rstc_base\n"); 276 panic("Impossible to ioremap at91_rstc_base\n");
277} 277}
278 278
279void __iomem *at91_matrix_base;
280
281void __init at91_ioremap_matrix(u32 base_addr)
282{
283 at91_matrix_base = ioremap(base_addr, 512);
284 if (!at91_matrix_base)
285 panic("Impossible to ioremap at91_matrix_base\n");
286}
287
279void __init at91_initialize(unsigned long main_clock) 288void __init at91_initialize(unsigned long main_clock)
280{ 289{
281 at91_boot_soc.ioremap_registers(); 290 at91_boot_soc.ioremap_registers();
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 02:45:02 -0400