diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h index 5f9149071fe..6d160adadaf 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h | |||
| @@ -14,12 +14,12 @@ | |||
| 14 | #ifndef AT91SAM9RL_MATRIX_H | 14 | #ifndef AT91SAM9RL_MATRIX_H |
| 15 | #define AT91SAM9RL_MATRIX_H | 15 | #define AT91SAM9RL_MATRIX_H |
| 16 | 16 | ||
| 17 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | 17 | #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ |
| 18 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | 18 | #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ |
| 19 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | 19 | #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ |
| 20 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | 20 | #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ |
| 21 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | 21 | #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ |
| 22 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | 22 | #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ |
| 23 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | 23 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
| 24 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | 24 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
| 25 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | 25 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
| @@ -27,12 +27,12 @@ | |||
| 27 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | 27 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
| 28 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | 28 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
| 29 | 29 | ||
| 30 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | 30 | #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ |
| 31 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | 31 | #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ |
| 32 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | 32 | #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ |
| 33 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | 33 | #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ |
| 34 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | 34 | #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ |
| 35 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | 35 | #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ |
| 36 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | 36 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | 37 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | 38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
| @@ -43,12 +43,12 @@ | |||
| 43 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | 43 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
| 44 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | 44 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
| 45 | 45 | ||
| 46 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | 46 | #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ |
| 47 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | 47 | #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ |
| 48 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | 48 | #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ |
| 49 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | 49 | #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ |
| 50 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | 50 | #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ |
| 51 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | 51 | #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ |
| 52 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | 52 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
| 53 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | 53 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
| 54 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | 54 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
| @@ -56,7 +56,7 @@ | |||
| 56 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | 56 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
| 57 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | 57 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
| 58 | 58 | ||
| 59 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | 59 | #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ |
| 60 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | 60 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
| 61 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | 61 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
| 62 | #define AT91_MATRIX_RCB2 (1 << 2) | 62 | #define AT91_MATRIX_RCB2 (1 << 2) |
| @@ -64,7 +64,7 @@ | |||
| 64 | #define AT91_MATRIX_RCB4 (1 << 4) | 64 | #define AT91_MATRIX_RCB4 (1 << 4) |
| 65 | #define AT91_MATRIX_RCB5 (1 << 5) | 65 | #define AT91_MATRIX_RCB5 (1 << 5) |
| 66 | 66 | ||
| 67 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | 67 | #define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ |
| 68 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | 68 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
| 69 | #define AT91_MATRIX_ITCM_0 (0 << 0) | 69 | #define AT91_MATRIX_ITCM_0 (0 << 0) |
| 70 | #define AT91_MATRIX_ITCM_16 (5 << 0) | 70 | #define AT91_MATRIX_ITCM_16 (5 << 0) |
| @@ -74,7 +74,7 @@ | |||
| 74 | #define AT91_MATRIX_DTCM_16 (5 << 4) | 74 | #define AT91_MATRIX_DTCM_16 (5 << 4) |
| 75 | #define AT91_MATRIX_DTCM_32 (6 << 4) | 75 | #define AT91_MATRIX_DTCM_32 (6 << 4) |
| 76 | 76 | ||
| 77 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | 77 | #define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */ |
| 78 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | 78 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
| 79 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | 79 | #define AT91_MATRIX_CS1A_SMC (0 << 1) |
| 80 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | 80 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |