5 files changed, 89 insertions, 39 deletions

diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index c5eaad529de..0670f37aaae 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -82,6 +82,22 @@ enum dma_ch {
         DMACH_SLIMBUS4_TX,
         DMACH_SLIMBUS5_RX,
         DMACH_SLIMBUS5_TX,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI1,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI3,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI5,
+        DMACH_MIPI_HSI6,
+        DMACH_MIPI_HSI7,
+        DMACH_MTOM_0,
+        DMACH_MTOM_1,
+        DMACH_MTOM_2,
+        DMACH_MTOM_3,
+        DMACH_MTOM_4,
+        DMACH_MTOM_5,
+        DMACH_MTOM_6,
+        DMACH_MTOM_7,
         /* END Marker, also used to denote a reserved channel */
         DMACH_MAX,
 };
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
index 30b7cc14cef..0f8263e93ee 100644
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -18,51 +18,54 @@
 #define S3C2410_INTP_ALM        (1 << 1)
 #define S3C2410_INTP_TIC        (1 << 0)
 
-#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN  (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-#define S3C64XX_RTCCON_TICEN  (1<<8)
+#define S3C2410_RTCCON          S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN    (1 << 0)
+#define S3C2410_RTCCON_CNTSEL   (1 << 2)
+#define S3C2410_RTCCON_CLKRST   (1 << 3)
+#define S3C2443_RTCCON_TICSEL   (1 << 4)
+#define S3C64XX_RTCCON_TICEN    (1 << 8)
 
-#define S3C64XX_RTCCON_TICMSK (0xF<<7)
-#define S3C64XX_RTCCON_TICSHT (7)
+#define S3C2410_TICNT           S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE    (1 << 7)
 
-#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE  (1<<7)
+/* S3C2443: tick count is 15 bit wide
+ * TICNT[6:0] contains upper 7 bits
+ * TICNT1[7:0] contains lower 8 bits
+ */
+#define S3C2443_TICNT_PART(x)   ((x & 0x7f00) >> 8)
+#define S3C2443_TICNT1          S3C2410_RTCREG(0x4C)
+#define S3C2443_TICNT1_PART(x)  (x & 0xff)
 
-#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN  (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN  (1<<4)
-#define S3C2410_RTCALM_DAYEN  (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN  (1<<1)
-#define S3C2410_RTCALM_SECEN  (1<<0)
+/* S3C2416: tick count is 32 bit wide
+ * TICNT[6:0] contains bits [14:8]
+ * TICNT1[7:0] contains lower 8 bits
+ * TICNT2[16:0] contains upper 17 bits
+ */
+#define S3C2416_TICNT2          S3C2410_RTCREG(0x48)
+#define S3C2416_TICNT2_PART(x)  ((x & 0xffff8000) >> 15)
 
-#define S3C2410_RTCALM_ALL \
-  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
-  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
-  S3C2410_RTCALM_SECEN
+#define S3C2410_RTCALM          S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN    (1 << 6)
+#define S3C2410_RTCALM_YEAREN   (1 << 5)
+#define S3C2410_RTCALM_MONEN    (1 << 4)
+#define S3C2410_RTCALM_DAYEN    (1 << 3)
+#define S3C2410_RTCALM_HOUREN   (1 << 2)
+#define S3C2410_RTCALM_MINEN    (1 << 1)
+#define S3C2410_RTCALM_SECEN    (1 << 0)
 
+#define S3C2410_ALMSEC          S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN          S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR         S3C2410_RTCREG(0x5c)
 
-#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+#define S3C2410_ALMDATE         S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON          S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR         S3C2410_RTCREG(0x68)
 
+#define S3C2410_RTCSEC          S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN          S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR         S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE         S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCMON          S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR         S3C2410_RTCREG(0x88)
 
 #endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h
new file mode 100644
index 00000000000..21d8594d37c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/rtc-core.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h
+ *
+ * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
+ *
+ * Samsung RTC Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_RTC_CORE_H
+#define __ASM_PLAT_RTC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_rtc_setname(char *name)
+{
+#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
+        s3c_device_rtc.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_RTC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f82f888b91a..317e246ffc5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -40,6 +40,7 @@ enum clk_types {
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
+ * @host_caps2: The second standard MMC host capabilities bit field.
  * @cd_type: Type of Card Detection method (see cd_types enum above)
  * @clk_type: Type of clock divider method (see clk_types enum above)
  * @ext_cd_init: Initialize external card detect subsystem. Called on
@@ -63,6 +64,7 @@ enum clk_types {
 struct s3c_sdhci_platdata {
         unsigned int    max_width;
         unsigned int    host_caps;
+        unsigned int    host_caps2;
         unsigned int    pm_caps;
         enum cd_types   cd_type;
         enum clk_types  clk_type;
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 0f707184eae..fa78aa710ed 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -53,6 +53,8 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->host_caps)
                 set->host_caps |= pd->host_caps;
+        if (pd->host_caps2)
+                set->host_caps2 |= pd->host_caps2;
         if (pd->pm_caps)
                 set->pm_caps |= pd->pm_caps;
         if (pd->clk_type)