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-rw-r--r--arch/arm/plat-pxa/include/plat/gpio.h64
-rw-r--r--arch/arm/plat-pxa/include/plat/pxa27x_keypad.h69
-rw-r--r--arch/arm/plat-pxa/include/plat/pxa3xx_nand.h63
3 files changed, 196 insertions, 0 deletions
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
new file mode 100644
index 00000000000..1ddd2b97a72
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -0,0 +1,64 @@
1#ifndef __PLAT_GPIO_H
2#define __PLAT_GPIO_H
3
4struct irq_data;
5
6/*
7 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
8 * one set of registers. The register offsets are organized below:
9 *
10 * GPLR GPDR GPSR GPCR GRER GFER GEDR
11 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
12 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
13 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
14 *
15 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
16 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
17 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
18 *
19 * NOTE:
20 * BANK 3 is only available on PXA27x and later processors.
21 * BANK 4 and 5 are only available on PXA935
22 */
23
24#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
25
26#define GPLR_OFFSET 0x00
27#define GPDR_OFFSET 0x0C
28#define GPSR_OFFSET 0x18
29#define GPCR_OFFSET 0x24
30#define GRER_OFFSET 0x30
31#define GFER_OFFSET 0x3C
32#define GEDR_OFFSET 0x48
33
34static inline int gpio_get_value(unsigned gpio)
35{
36 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
37 return GPLR(gpio) & GPIO_bit(gpio);
38 else
39 return __gpio_get_value(gpio);
40}
41
42static inline void gpio_set_value(unsigned gpio, int value)
43{
44 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
45 if (value)
46 GPSR(gpio) = GPIO_bit(gpio);
47 else
48 GPCR(gpio) = GPIO_bit(gpio);
49 } else
50 __gpio_set_value(gpio, value);
51}
52
53#define gpio_cansleep __gpio_cansleep
54
55/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
56 * Those cases currently cause holes in the GPIO number space, the
57 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
58 */
59extern int pxa_last_gpio;
60
61typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
62
63extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
64#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
new file mode 100644
index 00000000000..abcc36eb124
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -0,0 +1,69 @@
1#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
2#define __ASM_ARCH_PXA27x_KEYPAD_H
3
4#include <linux/input.h>
5#include <linux/input/matrix_keypad.h>
6
7#define MAX_MATRIX_KEY_ROWS (8)
8#define MAX_MATRIX_KEY_COLS (8)
9#define MATRIX_ROW_SHIFT (3)
10#define MAX_DIRECT_KEY_NUM (8)
11
12/* pxa3xx keypad platform specific parameters
13 *
14 * NOTE:
15 * 1. direct_key_num indicates the number of keys in the direct keypad
16 * _plus_ the number of rotary-encoder sensor inputs, this can be
17 * left as 0 if only rotary encoders are enabled, the driver will
18 * automatically calculate this
19 *
20 * 2. direct_key_map is the key code map for the direct keys, if rotary
21 * encoder(s) are enabled, direct key 0/1(2/3) will be ignored
22 *
23 * 3. rotary can be either interpreted as a relative input event (e.g.
24 * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
25 *
26 * 4. matrix key and direct key will use the same debounce_interval by
27 * default, which should be sufficient in most cases
28 *
29 * pxa168 keypad platform specific parameter
30 *
31 * NOTE:
32 * clear_wakeup_event callback is a workaround required to clear the
33 * keypad interrupt. The keypad wake must be cleared in addition to
34 * reading the MI/DI bits in the KPC register.
35 */
36struct pxa27x_keypad_platform_data {
37
38 /* code map for the matrix keys */
39 unsigned int matrix_key_rows;
40 unsigned int matrix_key_cols;
41 unsigned int *matrix_key_map;
42 int matrix_key_map_size;
43
44 /* direct keys */
45 int direct_key_num;
46 unsigned int direct_key_map[MAX_DIRECT_KEY_NUM];
47
48 /* rotary encoders 0 */
49 int enable_rotary0;
50 int rotary0_rel_code;
51 int rotary0_up_key;
52 int rotary0_down_key;
53
54 /* rotary encoders 1 */
55 int enable_rotary1;
56 int rotary1_rel_code;
57 int rotary1_up_key;
58 int rotary1_down_key;
59
60 /* key debounce interval */
61 unsigned int debounce_interval;
62
63 /* clear wakeup event requirement for pxa168 */
64 void (*clear_wakeup_event)(void);
65};
66
67extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
68
69#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
new file mode 100644
index 00000000000..442301fe48b
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -0,0 +1,63 @@
1#ifndef __ASM_ARCH_PXA3XX_NAND_H
2#define __ASM_ARCH_PXA3XX_NAND_H
3
4#include <linux/mtd/mtd.h>
5#include <linux/mtd/partitions.h>
6
7struct pxa3xx_nand_timing {
8 unsigned int tCH; /* Enable signal hold time */
9 unsigned int tCS; /* Enable signal setup time */
10 unsigned int tWH; /* ND_nWE high duration */
11 unsigned int tWP; /* ND_nWE pulse time */
12 unsigned int tRH; /* ND_nRE high duration */
13 unsigned int tRP; /* ND_nRE pulse width */
14 unsigned int tR; /* ND_nWE high to ND_nRE low for read */
15 unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
16 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
17};
18
19struct pxa3xx_nand_cmdset {
20 uint16_t read1;
21 uint16_t read2;
22 uint16_t program;
23 uint16_t read_status;
24 uint16_t read_id;
25 uint16_t erase;
26 uint16_t reset;
27 uint16_t lock;
28 uint16_t unlock;
29 uint16_t lock_status;
30};
31
32struct pxa3xx_nand_flash {
33 char *name;
34 uint32_t chip_id;
35 unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
36 unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
37 unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
38 unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
39 unsigned int num_blocks; /* Number of physical blocks in Flash */
40
41 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
42};
43
44struct pxa3xx_nand_platform_data {
45
46 /* the data flash bus is shared between the Static Memory
47 * Controller and the Data Flash Controller, the arbiter
48 * controls the ownership of the bus
49 */
50 int enable_arbiter;
51
52 /* allow platform code to keep OBM/bootloader defined NFC config */
53 int keep_config;
54
55 const struct mtd_partition *parts;
56 unsigned int nr_parts;
57
58 const struct pxa3xx_nand_flash * flash;
59 size_t num_flash;
60};
61
62extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
63#endif /* __ASM_ARCH_PXA3XX_NAND_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-13 12:28:10 -0500