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-rw-r--r--arch/arm/plat-pxa/gpio.c338
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio.h64
-rw-r--r--arch/arm/plat-pxa/include/plat/pxa27x_keypad.h69
-rw-r--r--arch/arm/plat-pxa/include/plat/pxa3xx_nand.h63
-rw-r--r--arch/arm/plat-pxa/pwm.c304
5 files changed, 838 insertions, 0 deletions
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
new file mode 100644
index 00000000000..a11dc367050
--- /dev/null
+++ b/arch/arm/plat-pxa/gpio.c
@@ -0,0 +1,338 @@
1/*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19#include <linux/slab.h>
20
21#include <mach/gpio.h>
22
23int pxa_last_gpio;
24
25struct pxa_gpio_chip {
26 struct gpio_chip chip;
27 void __iomem *regbase;
28 char label[10];
29
30 unsigned long irq_mask;
31 unsigned long irq_edge_rise;
32 unsigned long irq_edge_fall;
33
34#ifdef CONFIG_PM
35 unsigned long saved_gplr;
36 unsigned long saved_gpdr;
37 unsigned long saved_grer;
38 unsigned long saved_gfer;
39#endif
40};
41
42static DEFINE_SPINLOCK(gpio_lock);
43static struct pxa_gpio_chip *pxa_gpio_chips;
44
45#define for_each_gpio_chip(i, c) \
46 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
47
48static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
49{
50 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
51}
52
53static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
54{
55 return &pxa_gpio_chips[gpio_to_bank(gpio)];
56}
57
58static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
59{
60 void __iomem *base = gpio_chip_base(chip);
61 uint32_t value, mask = 1 << offset;
62 unsigned long flags;
63
64 spin_lock_irqsave(&gpio_lock, flags);
65
66 value = __raw_readl(base + GPDR_OFFSET);
67 if (__gpio_is_inverted(chip->base + offset))
68 value |= mask;
69 else
70 value &= ~mask;
71 __raw_writel(value, base + GPDR_OFFSET);
72
73 spin_unlock_irqrestore(&gpio_lock, flags);
74 return 0;
75}
76
77static int pxa_gpio_direction_output(struct gpio_chip *chip,
78 unsigned offset, int value)
79{
80 void __iomem *base = gpio_chip_base(chip);
81 uint32_t tmp, mask = 1 << offset;
82 unsigned long flags;
83
84 __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
85
86 spin_lock_irqsave(&gpio_lock, flags);
87
88 tmp = __raw_readl(base + GPDR_OFFSET);
89 if (__gpio_is_inverted(chip->base + offset))
90 tmp &= ~mask;
91 else
92 tmp |= mask;
93 __raw_writel(tmp, base + GPDR_OFFSET);
94
95 spin_unlock_irqrestore(&gpio_lock, flags);
96 return 0;
97}
98
99static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
100{
101 return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
102}
103
104static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
105{
106 __raw_writel(1 << offset, gpio_chip_base(chip) +
107 (value ? GPSR_OFFSET : GPCR_OFFSET));
108}
109
110static int __init pxa_init_gpio_chip(int gpio_end)
111{
112 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
113 struct pxa_gpio_chip *chips;
114
115 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
116 if (chips == NULL) {
117 pr_err("%s: failed to allocate GPIO chips\n", __func__);
118 return -ENOMEM;
119 }
120
121 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
122 struct gpio_chip *c = &chips[i].chip;
123
124 sprintf(chips[i].label, "gpio-%d", i);
125 chips[i].regbase = (void __iomem *)GPIO_BANK(i);
126
127 c->base = gpio;
128 c->label = chips[i].label;
129
130 c->direction_input = pxa_gpio_direction_input;
131 c->direction_output = pxa_gpio_direction_output;
132 c->get = pxa_gpio_get;
133 c->set = pxa_gpio_set;
134
135 /* number of GPIOs on last bank may be less than 32 */
136 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
137 gpiochip_add(c);
138 }
139 pxa_gpio_chips = chips;
140 return 0;
141}
142
143/* Update only those GRERx and GFERx edge detection register bits if those
144 * bits are set in c->irq_mask
145 */
146static inline void update_edge_detect(struct pxa_gpio_chip *c)
147{
148 uint32_t grer, gfer;
149
150 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
151 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
152 grer |= c->irq_edge_rise & c->irq_mask;
153 gfer |= c->irq_edge_fall & c->irq_mask;
154 __raw_writel(grer, c->regbase + GRER_OFFSET);
155 __raw_writel(gfer, c->regbase + GFER_OFFSET);
156}
157
158static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
159{
160 struct pxa_gpio_chip *c;
161 int gpio = irq_to_gpio(d->irq);
162 unsigned long gpdr, mask = GPIO_bit(gpio);
163
164 c = gpio_to_pxachip(gpio);
165
166 if (type == IRQ_TYPE_PROBE) {
167 /* Don't mess with enabled GPIOs using preconfigured edges or
168 * GPIOs set to alternate function or to output during probe
169 */
170 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
171 return 0;
172
173 if (__gpio_is_occupied(gpio))
174 return 0;
175
176 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
177 }
178
179 gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
180
181 if (__gpio_is_inverted(gpio))
182 __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
183 else
184 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
185
186 if (type & IRQ_TYPE_EDGE_RISING)
187 c->irq_edge_rise |= mask;
188 else
189 c->irq_edge_rise &= ~mask;
190
191 if (type & IRQ_TYPE_EDGE_FALLING)
192 c->irq_edge_fall |= mask;
193 else
194 c->irq_edge_fall &= ~mask;
195
196 update_edge_detect(c);
197
198 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
199 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
200 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
201 return 0;
202}
203
204static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
205{
206 struct pxa_gpio_chip *c;
207 int loop, gpio, gpio_base, n;
208 unsigned long gedr;
209
210 do {
211 loop = 0;
212 for_each_gpio_chip(gpio, c) {
213 gpio_base = c->chip.base;
214
215 gedr = __raw_readl(c->regbase + GEDR_OFFSET);
216 gedr = gedr & c->irq_mask;
217 __raw_writel(gedr, c->regbase + GEDR_OFFSET);
218
219 n = find_first_bit(&gedr, BITS_PER_LONG);
220 while (n < BITS_PER_LONG) {
221 loop = 1;
222
223 generic_handle_irq(gpio_to_irq(gpio_base + n));
224 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
225 }
226 }
227 } while (loop);
228}
229
230static void pxa_ack_muxed_gpio(struct irq_data *d)
231{
232 int gpio = irq_to_gpio(d->irq);
233 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
234
235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
236}
237
238static void pxa_mask_muxed_gpio(struct irq_data *d)
239{
240 int gpio = irq_to_gpio(d->irq);
241 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
242 uint32_t grer, gfer;
243
244 c->irq_mask &= ~GPIO_bit(gpio);
245
246 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
247 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
248 __raw_writel(grer, c->regbase + GRER_OFFSET);
249 __raw_writel(gfer, c->regbase + GFER_OFFSET);
250}
251
252static void pxa_unmask_muxed_gpio(struct irq_data *d)
253{
254 int gpio = irq_to_gpio(d->irq);
255 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
256
257 c->irq_mask |= GPIO_bit(gpio);
258 update_edge_detect(c);
259}
260
261static struct irq_chip pxa_muxed_gpio_chip = {
262 .name = "GPIO",
263 .irq_ack = pxa_ack_muxed_gpio,
264 .irq_mask = pxa_mask_muxed_gpio,
265 .irq_unmask = pxa_unmask_muxed_gpio,
266 .irq_set_type = pxa_gpio_irq_type,
267};
268
269void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
270{
271 struct pxa_gpio_chip *c;
272 int gpio, irq;
273
274 pxa_last_gpio = end;
275
276 /* Initialize GPIO chips */
277 pxa_init_gpio_chip(end);
278
279 /* clear all GPIO edge detects */
280 for_each_gpio_chip(gpio, c) {
281 __raw_writel(0, c->regbase + GFER_OFFSET);
282 __raw_writel(0, c->regbase + GRER_OFFSET);
283 __raw_writel(~0,c->regbase + GEDR_OFFSET);
284 }
285
286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 handle_edge_irq);
289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 }
291
292 /* Install handler for GPIO>=2 edge detect interrupts */
293 irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
294 pxa_muxed_gpio_chip.irq_set_wake = fn;
295}
296
297#ifdef CONFIG_PM
298static int pxa_gpio_suspend(void)
299{
300 struct pxa_gpio_chip *c;
301 int gpio;
302
303 for_each_gpio_chip(gpio, c) {
304 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
305 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
306 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
307 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
308
309 /* Clear GPIO transition detect bits */
310 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
311 }
312 return 0;
313}
314
315static void pxa_gpio_resume(void)
316{
317 struct pxa_gpio_chip *c;
318 int gpio;
319
320 for_each_gpio_chip(gpio, c) {
321 /* restore level with set/clear */
322 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
323 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
324
325 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
326 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
327 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
328 }
329}
330#else
331#define pxa_gpio_suspend NULL
332#define pxa_gpio_resume NULL
333#endif
334
335struct syscore_ops pxa_gpio_syscore_ops = {
336 .suspend = pxa_gpio_suspend,
337 .resume = pxa_gpio_resume,
338};
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
new file mode 100644
index 00000000000..1ddd2b97a72
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -0,0 +1,64 @@
1#ifndef __PLAT_GPIO_H
2#define __PLAT_GPIO_H
3
4struct irq_data;
5
6/*
7 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
8 * one set of registers. The register offsets are organized below:
9 *
10 * GPLR GPDR GPSR GPCR GRER GFER GEDR
11 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
12 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
13 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
14 *
15 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
16 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
17 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
18 *
19 * NOTE:
20 * BANK 3 is only available on PXA27x and later processors.
21 * BANK 4 and 5 are only available on PXA935
22 */
23
24#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
25
26#define GPLR_OFFSET 0x00
27#define GPDR_OFFSET 0x0C
28#define GPSR_OFFSET 0x18
29#define GPCR_OFFSET 0x24
30#define GRER_OFFSET 0x30
31#define GFER_OFFSET 0x3C
32#define GEDR_OFFSET 0x48
33
34static inline int gpio_get_value(unsigned gpio)
35{
36 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
37 return GPLR(gpio) & GPIO_bit(gpio);
38 else
39 return __gpio_get_value(gpio);
40}
41
42static inline void gpio_set_value(unsigned gpio, int value)
43{
44 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
45 if (value)
46 GPSR(gpio) = GPIO_bit(gpio);
47 else
48 GPCR(gpio) = GPIO_bit(gpio);
49 } else
50 __gpio_set_value(gpio, value);
51}
52
53#define gpio_cansleep __gpio_cansleep
54
55/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
56 * Those cases currently cause holes in the GPIO number space, the
57 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
58 */
59extern int pxa_last_gpio;
60
61typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
62
63extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
64#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
new file mode 100644
index 00000000000..abcc36eb124
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -0,0 +1,69 @@
1#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
2#define __ASM_ARCH_PXA27x_KEYPAD_H
3
4#include <linux/input.h>
5#include <linux/input/matrix_keypad.h>
6
7#define MAX_MATRIX_KEY_ROWS (8)
8#define MAX_MATRIX_KEY_COLS (8)
9#define MATRIX_ROW_SHIFT (3)
10#define MAX_DIRECT_KEY_NUM (8)
11
12/* pxa3xx keypad platform specific parameters
13 *
14 * NOTE:
15 * 1. direct_key_num indicates the number of keys in the direct keypad
16 * _plus_ the number of rotary-encoder sensor inputs, this can be
17 * left as 0 if only rotary encoders are enabled, the driver will
18 * automatically calculate this
19 *
20 * 2. direct_key_map is the key code map for the direct keys, if rotary
21 * encoder(s) are enabled, direct key 0/1(2/3) will be ignored
22 *
23 * 3. rotary can be either interpreted as a relative input event (e.g.
24 * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
25 *
26 * 4. matrix key and direct key will use the same debounce_interval by
27 * default, which should be sufficient in most cases
28 *
29 * pxa168 keypad platform specific parameter
30 *
31 * NOTE:
32 * clear_wakeup_event callback is a workaround required to clear the
33 * keypad interrupt. The keypad wake must be cleared in addition to
34 * reading the MI/DI bits in the KPC register.
35 */
36struct pxa27x_keypad_platform_data {
37
38 /* code map for the matrix keys */
39 unsigned int matrix_key_rows;
40 unsigned int matrix_key_cols;
41 unsigned int *matrix_key_map;
42 int matrix_key_map_size;
43
44 /* direct keys */
45 int direct_key_num;
46 unsigned int direct_key_map[MAX_DIRECT_KEY_NUM];
47
48 /* rotary encoders 0 */
49 int enable_rotary0;
50 int rotary0_rel_code;
51 int rotary0_up_key;
52 int rotary0_down_key;
53
54 /* rotary encoders 1 */
55 int enable_rotary1;
56 int rotary1_rel_code;
57 int rotary1_up_key;
58 int rotary1_down_key;
59
60 /* key debounce interval */
61 unsigned int debounce_interval;
62
63 /* clear wakeup event requirement for pxa168 */
64 void (*clear_wakeup_event)(void);
65};
66
67extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
68
69#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
new file mode 100644
index 00000000000..442301fe48b
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -0,0 +1,63 @@
1#ifndef __ASM_ARCH_PXA3XX_NAND_H
2#define __ASM_ARCH_PXA3XX_NAND_H
3
4#include <linux/mtd/mtd.h>
5#include <linux/mtd/partitions.h>
6
7struct pxa3xx_nand_timing {
8 unsigned int tCH; /* Enable signal hold time */
9 unsigned int tCS; /* Enable signal setup time */
10 unsigned int tWH; /* ND_nWE high duration */
11 unsigned int tWP; /* ND_nWE pulse time */
12 unsigned int tRH; /* ND_nRE high duration */
13 unsigned int tRP; /* ND_nRE pulse width */
14 unsigned int tR; /* ND_nWE high to ND_nRE low for read */
15 unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
16 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
17};
18
19struct pxa3xx_nand_cmdset {
20 uint16_t read1;
21 uint16_t read2;
22 uint16_t program;
23 uint16_t read_status;
24 uint16_t read_id;
25 uint16_t erase;
26 uint16_t reset;
27 uint16_t lock;
28 uint16_t unlock;
29 uint16_t lock_status;
30};
31
32struct pxa3xx_nand_flash {
33 char *name;
34 uint32_t chip_id;
35 unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
36 unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
37 unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
38 unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
39 unsigned int num_blocks; /* Number of physical blocks in Flash */
40
41 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
42};
43
44struct pxa3xx_nand_platform_data {
45
46 /* the data flash bus is shared between the Static Memory
47 * Controller and the Data Flash Controller, the arbiter
48 * controls the ownership of the bus
49 */
50 int enable_arbiter;
51
52 /* allow platform code to keep OBM/bootloader defined NFC config */
53 int keep_config;
54
55 const struct mtd_partition *parts;
56 unsigned int nr_parts;
57
58 const struct pxa3xx_nand_flash * flash;
59 size_t num_flash;
60};
61
62extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
63#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
new file mode 100644
index 00000000000..ef32686feef
--- /dev/null
+++ b/arch/arm/plat-pxa/pwm.c
@@ -0,0 +1,304 @@
1/*
2 * linux/arch/arm/mach-pxa/pwm.c
3 *
4 * simple driver for PWM (Pulse Width Modulator) controller
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * 2008-02-13 initial version
11 * eric miao <eric.miao@marvell.com>
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/pwm.h>
22
23#include <asm/div64.h>
24
25#define HAS_SECONDARY_PWM 0x10
26#define PWM_ID_BASE(d) ((d) & 0xf)
27
28static const struct platform_device_id pwm_id_table[] = {
29 /* PWM has_secondary_pwm? */
30 { "pxa25x-pwm", 0 },
31 { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
32 { "pxa168-pwm", 1 },
33 { "pxa910-pwm", 1 },
34 { },
35};
36MODULE_DEVICE_TABLE(platform, pwm_id_table);
37
38/* PWM registers and bits definitions */
39#define PWMCR (0x00)
40#define PWMDCR (0x04)
41#define PWMPCR (0x08)
42
43#define PWMCR_SD (1 << 6)
44#define PWMDCR_FD (1 << 10)
45
46struct pwm_device {
47 struct list_head node;
48 struct pwm_device *secondary;
49 struct platform_device *pdev;
50
51 const char *label;
52 struct clk *clk;
53 int clk_enabled;
54 void __iomem *mmio_base;
55
56 unsigned int use_count;
57 unsigned int pwm_id;
58};
59
60/*
61 * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
62 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
63 */
64int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
65{
66 unsigned long long c;
67 unsigned long period_cycles, prescale, pv, dc;
68
69 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
70 return -EINVAL;
71
72 c = clk_get_rate(pwm->clk);
73 c = c * period_ns;
74 do_div(c, 1000000000);
75 period_cycles = c;
76
77 if (period_cycles < 1)
78 period_cycles = 1;
79 prescale = (period_cycles - 1) / 1024;
80 pv = period_cycles / (prescale + 1) - 1;
81
82 if (prescale > 63)
83 return -EINVAL;
84
85 if (duty_ns == period_ns)
86 dc = PWMDCR_FD;
87 else
88 dc = (pv + 1) * duty_ns / period_ns;
89
90 /* NOTE: the clock to PWM has to be enabled first
91 * before writing to the registers
92 */
93 clk_enable(pwm->clk);
94 __raw_writel(prescale, pwm->mmio_base + PWMCR);
95 __raw_writel(dc, pwm->mmio_base + PWMDCR);
96 __raw_writel(pv, pwm->mmio_base + PWMPCR);
97 clk_disable(pwm->clk);
98
99 return 0;
100}
101EXPORT_SYMBOL(pwm_config);
102
103int pwm_enable(struct pwm_device *pwm)
104{
105 int rc = 0;
106
107 if (!pwm->clk_enabled) {
108 rc = clk_enable(pwm->clk);
109 if (!rc)
110 pwm->clk_enabled = 1;
111 }
112 return rc;
113}
114EXPORT_SYMBOL(pwm_enable);
115
116void pwm_disable(struct pwm_device *pwm)
117{
118 if (pwm->clk_enabled) {
119 clk_disable(pwm->clk);
120 pwm->clk_enabled = 0;
121 }
122}
123EXPORT_SYMBOL(pwm_disable);
124
125static DEFINE_MUTEX(pwm_lock);
126static LIST_HEAD(pwm_list);
127
128struct pwm_device *pwm_request(int pwm_id, const char *label)
129{
130 struct pwm_device *pwm;
131 int found = 0;
132
133 mutex_lock(&pwm_lock);
134
135 list_for_each_entry(pwm, &pwm_list, node) {
136 if (pwm->pwm_id == pwm_id) {
137 found = 1;
138 break;
139 }
140 }
141
142 if (found) {
143 if (pwm->use_count == 0) {
144 pwm->use_count++;
145 pwm->label = label;
146 } else
147 pwm = ERR_PTR(-EBUSY);
148 } else
149 pwm = ERR_PTR(-ENOENT);
150
151 mutex_unlock(&pwm_lock);
152 return pwm;
153}
154EXPORT_SYMBOL(pwm_request);
155
156void pwm_free(struct pwm_device *pwm)
157{
158 mutex_lock(&pwm_lock);
159
160 if (pwm->use_count) {
161 pwm->use_count--;
162 pwm->label = NULL;
163 } else
164 pr_warning("PWM device already freed\n");
165
166 mutex_unlock(&pwm_lock);
167}
168EXPORT_SYMBOL(pwm_free);
169
170static inline void __add_pwm(struct pwm_device *pwm)
171{
172 mutex_lock(&pwm_lock);
173 list_add_tail(&pwm->node, &pwm_list);
174 mutex_unlock(&pwm_lock);
175}
176
177static int __devinit pwm_probe(struct platform_device *pdev)
178{
179 const struct platform_device_id *id = platform_get_device_id(pdev);
180 struct pwm_device *pwm, *secondary = NULL;
181 struct resource *r;
182 int ret = 0;
183
184 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
185 if (pwm == NULL) {
186 dev_err(&pdev->dev, "failed to allocate memory\n");
187 return -ENOMEM;
188 }
189
190 pwm->clk = clk_get(&pdev->dev, NULL);
191 if (IS_ERR(pwm->clk)) {
192 ret = PTR_ERR(pwm->clk);
193 goto err_free;
194 }
195 pwm->clk_enabled = 0;
196
197 pwm->use_count = 0;
198 pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
199 pwm->pdev = pdev;
200
201 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 if (r == NULL) {
203 dev_err(&pdev->dev, "no memory resource defined\n");
204 ret = -ENODEV;
205 goto err_free_clk;
206 }
207
208 r = request_mem_region(r->start, resource_size(r), pdev->name);
209 if (r == NULL) {
210 dev_err(&pdev->dev, "failed to request memory resource\n");
211 ret = -EBUSY;
212 goto err_free_clk;
213 }
214
215 pwm->mmio_base = ioremap(r->start, resource_size(r));
216 if (pwm->mmio_base == NULL) {
217 dev_err(&pdev->dev, "failed to ioremap() registers\n");
218 ret = -ENODEV;
219 goto err_free_mem;
220 }
221
222 if (id->driver_data & HAS_SECONDARY_PWM) {
223 secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
224 if (secondary == NULL) {
225 ret = -ENOMEM;
226 goto err_free_mem;
227 }
228
229 *secondary = *pwm;
230 pwm->secondary = secondary;
231
232 /* registers for the second PWM has offset of 0x10 */
233 secondary->mmio_base = pwm->mmio_base + 0x10;
234 secondary->pwm_id = pdev->id + 2;
235 }
236
237 __add_pwm(pwm);
238 if (secondary)
239 __add_pwm(secondary);
240
241 platform_set_drvdata(pdev, pwm);
242 return 0;
243
244err_free_mem:
245 release_mem_region(r->start, resource_size(r));
246err_free_clk:
247 clk_put(pwm->clk);
248err_free:
249 kfree(pwm);
250 return ret;
251}
252
253static int __devexit pwm_remove(struct platform_device *pdev)
254{
255 struct pwm_device *pwm;
256 struct resource *r;
257
258 pwm = platform_get_drvdata(pdev);
259 if (pwm == NULL)
260 return -ENODEV;
261
262 mutex_lock(&pwm_lock);
263
264 if (pwm->secondary) {
265 list_del(&pwm->secondary->node);
266 kfree(pwm->secondary);
267 }
268
269 list_del(&pwm->node);
270 mutex_unlock(&pwm_lock);
271
272 iounmap(pwm->mmio_base);
273
274 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
275 release_mem_region(r->start, resource_size(r));
276
277 clk_put(pwm->clk);
278 kfree(pwm);
279 return 0;
280}
281
282static struct platform_driver pwm_driver = {
283 .driver = {
284 .name = "pxa25x-pwm",
285 .owner = THIS_MODULE,
286 },
287 .probe = pwm_probe,
288 .remove = __devexit_p(pwm_remove),
289 .id_table = pwm_id_table,
290};
291
292static int __init pwm_init(void)
293{
294 return platform_driver_register(&pwm_driver);
295}
296arch_initcall(pwm_init);
297
298static void __exit pwm_exit(void)
299{
300 platform_driver_unregister(&pwm_driver);
301}
302module_exit(pwm_exit);
303
304MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-19 20:27:15 -0400