Added missing tegra files.HEADmaster

5 files changed, 838 insertions, 0 deletions

diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
new file mode 100644
index 00000000000..a11dc367050
--- /dev/null
+++ b/arch/arm/plat-pxa/gpio.c
@@ -0,0 +1,338 @@
+/*
+ *  linux/arch/arm/plat-pxa/gpio.c
+ *
+ *  Generic PXA GPIO handling
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+#include <linux/slab.h>
+
+#include <mach/gpio.h>
+
+int pxa_last_gpio;
+
+struct pxa_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem    *regbase;
+        char label[10];
+
+        unsigned long   irq_mask;
+        unsigned long   irq_edge_rise;
+        unsigned long   irq_edge_fall;
+
+#ifdef CONFIG_PM
+        unsigned long   saved_gplr;
+        unsigned long   saved_gpdr;
+        unsigned long   saved_grer;
+        unsigned long   saved_gfer;
+#endif
+};
+
+static DEFINE_SPINLOCK(gpio_lock);
+static struct pxa_gpio_chip *pxa_gpio_chips;
+
+#define for_each_gpio_chip(i, c)                        \
+        for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
+
+static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
+{
+        return container_of(c, struct pxa_gpio_chip, chip)->regbase;
+}
+
+static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
+{
+        return &pxa_gpio_chips[gpio_to_bank(gpio)];
+}
+
+static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        void __iomem *base = gpio_chip_base(chip);
+        uint32_t value, mask = 1 << offset;
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        value = __raw_readl(base + GPDR_OFFSET);
+        if (__gpio_is_inverted(chip->base + offset))
+                value |= mask;
+        else
+                value &= ~mask;
+        __raw_writel(value, base + GPDR_OFFSET);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        return 0;
+}
+
+static int pxa_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        void __iomem *base = gpio_chip_base(chip);
+        uint32_t tmp, mask = 1 << offset;
+        unsigned long flags;
+
+        __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        tmp = __raw_readl(base + GPDR_OFFSET);
+        if (__gpio_is_inverted(chip->base + offset))
+                tmp &= ~mask;
+        else
+                tmp |= mask;
+        __raw_writel(tmp, base + GPDR_OFFSET);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        return 0;
+}
+
+static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
+}
+
+static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        __raw_writel(1 << offset, gpio_chip_base(chip) +
+                                (value ? GPSR_OFFSET : GPCR_OFFSET));
+}
+
+static int __init pxa_init_gpio_chip(int gpio_end)
+{
+        int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
+        struct pxa_gpio_chip *chips;
+
+        chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
+        if (chips == NULL) {
+                pr_err("%s: failed to allocate GPIO chips\n", __func__);
+                return -ENOMEM;
+        }
+
+        for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
+                struct gpio_chip *c = &chips[i].chip;
+
+                sprintf(chips[i].label, "gpio-%d", i);
+                chips[i].regbase = (void __iomem *)GPIO_BANK(i);
+
+                c->base  = gpio;
+                c->label = chips[i].label;
+
+                c->direction_input  = pxa_gpio_direction_input;
+                c->direction_output = pxa_gpio_direction_output;
+                c->get = pxa_gpio_get;
+                c->set = pxa_gpio_set;
+
+                /* number of GPIOs on last bank may be less than 32 */
+                c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
+                gpiochip_add(c);
+        }
+        pxa_gpio_chips = chips;
+        return 0;
+}
+
+/* Update only those GRERx and GFERx edge detection register bits if those
+ * bits are set in c->irq_mask
+ */
+static inline void update_edge_detect(struct pxa_gpio_chip *c)
+{
+        uint32_t grer, gfer;
+
+        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
+        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
+        grer |= c->irq_edge_rise & c->irq_mask;
+        gfer |= c->irq_edge_fall & c->irq_mask;
+        __raw_writel(grer, c->regbase + GRER_OFFSET);
+        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+}
+
+static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
+        struct pxa_gpio_chip *c;
+        int gpio = irq_to_gpio(d->irq);
+        unsigned long gpdr, mask = GPIO_bit(gpio);
+
+        c = gpio_to_pxachip(gpio);
+
+        if (type == IRQ_TYPE_PROBE) {
+                /* Don't mess with enabled GPIOs using preconfigured edges or
+                 * GPIOs set to alternate function or to output during probe
+                 */
+                if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
+                        return 0;
+
+                if (__gpio_is_occupied(gpio))
+                        return 0;
+
+                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        }
+
+        gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+
+        if (__gpio_is_inverted(gpio))
+                __raw_writel(gpdr | mask,  c->regbase + GPDR_OFFSET);
+        else
+                __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                c->irq_edge_rise |= mask;
+        else
+                c->irq_edge_rise &= ~mask;
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                c->irq_edge_fall |= mask;
+        else
+                c->irq_edge_fall &= ~mask;
+
+        update_edge_detect(c);
+
+        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
+                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
+                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
+        return 0;
+}
+
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct pxa_gpio_chip *c;
+        int loop, gpio, gpio_base, n;
+        unsigned long gedr;
+
+        do {
+                loop = 0;
+                for_each_gpio_chip(gpio, c) {
+                        gpio_base = c->chip.base;
+
+                        gedr = __raw_readl(c->regbase + GEDR_OFFSET);
+                        gedr = gedr & c->irq_mask;
+                        __raw_writel(gedr, c->regbase + GEDR_OFFSET);
+
+                        n = find_first_bit(&gedr, BITS_PER_LONG);
+                        while (n < BITS_PER_LONG) {
+                                loop = 1;
+
+                                generic_handle_irq(gpio_to_irq(gpio_base + n));
+                                n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
+                        }
+                }
+        } while (loop);
+}
+
+static void pxa_ack_muxed_gpio(struct irq_data *d)
+{
+        int gpio = irq_to_gpio(d->irq);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
+
+        __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
+}
+
+static void pxa_mask_muxed_gpio(struct irq_data *d)
+{
+        int gpio = irq_to_gpio(d->irq);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
+        uint32_t grer, gfer;
+
+        c->irq_mask &= ~GPIO_bit(gpio);
+
+        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
+        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
+        __raw_writel(grer, c->regbase + GRER_OFFSET);
+        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+}
+
+static void pxa_unmask_muxed_gpio(struct irq_data *d)
+{
+        int gpio = irq_to_gpio(d->irq);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
+
+        c->irq_mask |= GPIO_bit(gpio);
+        update_edge_detect(c);
+}
+
+static struct irq_chip pxa_muxed_gpio_chip = {
+        .name           = "GPIO",
+        .irq_ack        = pxa_ack_muxed_gpio,
+        .irq_mask       = pxa_mask_muxed_gpio,
+        .irq_unmask     = pxa_unmask_muxed_gpio,
+        .irq_set_type   = pxa_gpio_irq_type,
+};
+
+void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
+{
+        struct pxa_gpio_chip *c;
+        int gpio, irq;
+
+        pxa_last_gpio = end;
+
+        /* Initialize GPIO chips */
+        pxa_init_gpio_chip(end);
+
+        /* clear all GPIO edge detects */
+        for_each_gpio_chip(gpio, c) {
+                __raw_writel(0, c->regbase + GFER_OFFSET);
+                __raw_writel(0, c->regbase + GRER_OFFSET);
+                __raw_writel(~0,c->regbase + GEDR_OFFSET);
+        }
+
+        for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
+                irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                         handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        /* Install handler for GPIO>=2 edge detect interrupts */
+        irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
+        pxa_muxed_gpio_chip.irq_set_wake = fn;
+}
+
+#ifdef CONFIG_PM
+static int pxa_gpio_suspend(void)
+{
+        struct pxa_gpio_chip *c;
+        int gpio;
+
+        for_each_gpio_chip(gpio, c) {
+                c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
+                c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+                c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
+                c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
+
+                /* Clear GPIO transition detect bits */
+                __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
+        }
+        return 0;
+}
+
+static void pxa_gpio_resume(void)
+{
+        struct pxa_gpio_chip *c;
+        int gpio;
+
+        for_each_gpio_chip(gpio, c) {
+                /* restore level with set/clear */
+                __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
+                __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
+
+                __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
+                __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
+                __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
+        }
+}
+#else
+#define pxa_gpio_suspend        NULL
+#define pxa_gpio_resume         NULL
+#endif
+
+struct syscore_ops pxa_gpio_syscore_ops = {
+        .suspend        = pxa_gpio_suspend,
+        .resume         = pxa_gpio_resume,
+};
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
new file mode 100644
index 00000000000..1ddd2b97a72
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -0,0 +1,64 @@
+#ifndef __PLAT_GPIO_H
+#define __PLAT_GPIO_H
+
+struct irq_data;
+
+/*
+ * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
+ * one set of registers. The register offsets are organized below:
+ *
+ *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
+ * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
+ * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
+ * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
+ *
+ * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
+ * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
+ * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
+ *
+ * NOTE:
+ *   BANK 3 is only available on PXA27x and later processors.
+ *   BANK 4 and 5 are only available on PXA935
+ */
+
+#define GPIO_BANK(n)    (GPIO_REGS_VIRT + BANK_OFF(n))
+
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
+                return GPLR(gpio) & GPIO_bit(gpio);
+        else
+                return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
+                if (value)
+                        GPSR(gpio) = GPIO_bit(gpio);
+                else
+                        GPCR(gpio) = GPIO_bit(gpio);
+        } else
+                __gpio_set_value(gpio, value);
+}
+
+#define gpio_cansleep           __gpio_cansleep
+
+/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
+ * Those cases currently cause holes in the GPIO number space, the
+ * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
+ */
+extern int pxa_last_gpio;
+
+typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
+
+extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
+#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
new file mode 100644
index 00000000000..abcc36eb124
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -0,0 +1,69 @@
+#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
+#define __ASM_ARCH_PXA27x_KEYPAD_H
+
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+
+#define MAX_MATRIX_KEY_ROWS     (8)
+#define MAX_MATRIX_KEY_COLS     (8)
+#define MATRIX_ROW_SHIFT        (3)
+#define MAX_DIRECT_KEY_NUM      (8)
+
+/* pxa3xx keypad platform specific parameters
+ *
+ * NOTE:
+ * 1. direct_key_num indicates the number of keys in the direct keypad
+ *    _plus_ the number of rotary-encoder sensor inputs,  this can be
+ *    left as 0 if only rotary encoders are enabled,  the driver will
+ *    automatically calculate this
+ *
+ * 2. direct_key_map is the key code map for the direct keys, if rotary
+ *    encoder(s) are enabled, direct key 0/1(2/3) will be ignored
+ *
+ * 3. rotary can be either interpreted as a relative input event (e.g.
+ *    REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
+ *
+ * 4. matrix key and direct key will use the same debounce_interval by
+ *    default, which should be sufficient in most cases
+ *
+ * pxa168 keypad platform specific parameter
+ *
+ * NOTE:
+ * clear_wakeup_event callback is a workaround required to clear the
+ * keypad interrupt. The keypad wake must be cleared in addition to
+ * reading the MI/DI bits in the KPC register.
+ */
+struct pxa27x_keypad_platform_data {
+
+        /* code map for the matrix keys */
+        unsigned int    matrix_key_rows;
+        unsigned int    matrix_key_cols;
+        unsigned int    *matrix_key_map;
+        int             matrix_key_map_size;
+
+        /* direct keys */
+        int             direct_key_num;
+        unsigned int    direct_key_map[MAX_DIRECT_KEY_NUM];
+
+        /* rotary encoders 0 */
+        int             enable_rotary0;
+        int             rotary0_rel_code;
+        int             rotary0_up_key;
+        int             rotary0_down_key;
+
+        /* rotary encoders 1 */
+        int             enable_rotary1;
+        int             rotary1_rel_code;
+        int             rotary1_up_key;
+        int             rotary1_down_key;
+
+        /* key debounce interval */
+        unsigned int    debounce_interval;
+
+        /* clear wakeup event requirement for pxa168 */
+        void            (*clear_wakeup_event)(void);
+};
+
+extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
+
+#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
new file mode 100644
index 00000000000..442301fe48b
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -0,0 +1,63 @@
+#ifndef __ASM_ARCH_PXA3XX_NAND_H
+#define __ASM_ARCH_PXA3XX_NAND_H
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+struct pxa3xx_nand_timing {
+        unsigned int    tCH;  /* Enable signal hold time */
+        unsigned int    tCS;  /* Enable signal setup time */
+        unsigned int    tWH;  /* ND_nWE high duration */
+        unsigned int    tWP;  /* ND_nWE pulse time */
+        unsigned int    tRH;  /* ND_nRE high duration */
+        unsigned int    tRP;  /* ND_nRE pulse width */
+        unsigned int    tR;   /* ND_nWE high to ND_nRE low for read */
+        unsigned int    tWHR; /* ND_nWE high to ND_nRE low for status read */
+        unsigned int    tAR;  /* ND_ALE low to ND_nRE low delay */
+};
+
+struct pxa3xx_nand_cmdset {
+        uint16_t        read1;
+        uint16_t        read2;
+        uint16_t        program;
+        uint16_t        read_status;
+        uint16_t        read_id;
+        uint16_t        erase;
+        uint16_t        reset;
+        uint16_t        lock;
+        uint16_t        unlock;
+        uint16_t        lock_status;
+};
+
+struct pxa3xx_nand_flash {
+        char            *name;
+        uint32_t        chip_id;
+        unsigned int    page_per_block; /* Pages per block (PG_PER_BLK) */
+        unsigned int    page_size;      /* Page size in bytes (PAGE_SZ) */
+        unsigned int    flash_width;    /* Width of Flash memory (DWIDTH_M) */
+        unsigned int    dfc_width;      /* Width of flash controller(DWIDTH_C) */
+        unsigned int    num_blocks;     /* Number of physical blocks in Flash */
+
+        struct pxa3xx_nand_timing *timing;      /* NAND Flash timing */
+};
+
+struct pxa3xx_nand_platform_data {
+
+        /* the data flash bus is shared between the Static Memory
+         * Controller and the Data Flash Controller,  the arbiter
+         * controls the ownership of the bus
+         */
+        int     enable_arbiter;
+
+        /* allow platform code to keep OBM/bootloader defined NFC config */
+        int     keep_config;
+
+        const struct mtd_partition              *parts;
+        unsigned int                            nr_parts;
+
+        const struct pxa3xx_nand_flash *        flash;
+        size_t                                  num_flash;
+};
+
+extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
+#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
new file mode 100644
index 00000000000..ef32686feef
--- /dev/null
+++ b/arch/arm/plat-pxa/pwm.c
@@ -0,0 +1,304 @@
+/*
+ * linux/arch/arm/mach-pxa/pwm.c
+ *
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 2008-02-13   initial version
+ *              eric miao <eric.miao@marvell.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/div64.h>
+
+#define HAS_SECONDARY_PWM       0x10
+#define PWM_ID_BASE(d)          ((d) & 0xf)
+
+static const struct platform_device_id pwm_id_table[] = {
+        /*   PWM    has_secondary_pwm? */
+        { "pxa25x-pwm", 0 },
+        { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
+        { "pxa168-pwm", 1 },
+        { "pxa910-pwm", 1 },
+        { },
+};
+MODULE_DEVICE_TABLE(platform, pwm_id_table);
+
+/* PWM registers and bits definitions */
+#define PWMCR           (0x00)
+#define PWMDCR          (0x04)
+#define PWMPCR          (0x08)
+
+#define PWMCR_SD        (1 << 6)
+#define PWMDCR_FD       (1 << 10)
+
+struct pwm_device {
+        struct list_head        node;
+        struct pwm_device       *secondary;
+        struct platform_device  *pdev;
+
+        const char      *label;
+        struct clk      *clk;
+        int             clk_enabled;
+        void __iomem    *mmio_base;
+
+        unsigned int    use_count;
+        unsigned int    pwm_id;
+};
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
+ * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long c;
+        unsigned long period_cycles, prescale, pv, dc;
+
+        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        c = clk_get_rate(pwm->clk);
+        c = c * period_ns;
+        do_div(c, 1000000000);
+        period_cycles = c;
+
+        if (period_cycles < 1)
+                period_cycles = 1;
+        prescale = (period_cycles - 1) / 1024;
+        pv = period_cycles / (prescale + 1) - 1;
+
+        if (prescale > 63)
+                return -EINVAL;
+
+        if (duty_ns == period_ns)
+                dc = PWMDCR_FD;
+        else
+                dc = (pv + 1) * duty_ns / period_ns;
+
+        /* NOTE: the clock to PWM has to be enabled first
+         * before writing to the registers
+         */
+        clk_enable(pwm->clk);
+        __raw_writel(prescale, pwm->mmio_base + PWMCR);
+        __raw_writel(dc, pwm->mmio_base + PWMDCR);
+        __raw_writel(pv, pwm->mmio_base + PWMPCR);
+        clk_disable(pwm->clk);
+
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        int rc = 0;
+
+        if (!pwm->clk_enabled) {
+                rc = clk_enable(pwm->clk);
+                if (!rc)
+                        pwm->clk_enabled = 1;
+        }
+        return rc;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        if (pwm->clk_enabled) {
+                clk_disable(pwm->clk);
+                pwm->clk_enabled = 0;
+        }
+}
+EXPORT_SYMBOL(pwm_disable);
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, node) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count++;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                pr_warning("PWM device already freed\n");
+
+        mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+static inline void __add_pwm(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->node, &pwm_list);
+        mutex_unlock(&pwm_lock);
+}
+
+static int __devinit pwm_probe(struct platform_device *pdev)
+{
+        const struct platform_device_id *id = platform_get_device_id(pdev);
+        struct pwm_device *pwm, *secondary = NULL;
+        struct resource *r;
+        int ret = 0;
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+
+        pwm->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(pwm->clk)) {
+                ret = PTR_ERR(pwm->clk);
+                goto err_free;
+        }
+        pwm->clk_enabled = 0;
+
+        pwm->use_count = 0;
+        pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
+        pwm->pdev = pdev;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        pwm->mmio_base = ioremap(r->start, resource_size(r));
+        if (pwm->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        if (id->driver_data & HAS_SECONDARY_PWM) {
+                secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+                if (secondary == NULL) {
+                        ret = -ENOMEM;
+                        goto err_free_mem;
+                }
+
+                *secondary = *pwm;
+                pwm->secondary = secondary;
+
+                /* registers for the second PWM has offset of 0x10 */
+                secondary->mmio_base = pwm->mmio_base + 0x10;
+                secondary->pwm_id = pdev->id + 2;
+        }
+
+        __add_pwm(pwm);
+        if (secondary)
+                __add_pwm(secondary);
+
+        platform_set_drvdata(pdev, pwm);
+        return 0;
+
+err_free_mem:
+        release_mem_region(r->start, resource_size(r));
+err_free_clk:
+        clk_put(pwm->clk);
+err_free:
+        kfree(pwm);
+        return ret;
+}
+
+static int __devexit pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+
+        pwm = platform_get_drvdata(pdev);
+        if (pwm == NULL)
+                return -ENODEV;
+
+        mutex_lock(&pwm_lock);
+
+        if (pwm->secondary) {
+                list_del(&pwm->secondary->node);
+                kfree(pwm->secondary);
+        }
+
+        list_del(&pwm->node);
+        mutex_unlock(&pwm_lock);
+
+        iounmap(pwm->mmio_base);
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, resource_size(r));
+
+        clk_put(pwm->clk);
+        kfree(pwm);
+        return 0;
+}
+
+static struct platform_driver pwm_driver = {
+        .driver         = {
+                .name   = "pxa25x-pwm",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = pwm_probe,
+        .remove         = __devexit_p(pwm_remove),
+        .id_table       = pwm_id_table,
+};
+
+static int __init pwm_init(void)
+{
+        return platform_driver_register(&pwm_driver);
+}
+arch_initcall(pwm_init);
+
+static void __exit pwm_exit(void)
+{
+        platform_driver_unregister(&pwm_driver);
+}
+module_exit(pwm_exit);
+
+MODULE_LICENSE("GPL v2");