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-rw-r--r--Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt141
-rw-r--r--Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt74
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt984
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt787
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt1202
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt1630
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt918
-rw-r--r--Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt83
-rw-r--r--Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt97
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt100
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt72
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt318
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt46
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt128
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt128
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt47
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt155
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt265
22 files changed, 0 insertions, 7629 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
deleted file mode 100644
index 3a268127b05..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ /dev/null
@@ -1,141 +0,0 @@
1* Atmel AT91 Pinmux Controller
2
3The AT91 Pinmux Controler, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
68 muxing options (called periph modes). Since different modules require
7different PAD settings (like pull up, keeper, etc) the contoller controls
8also the PAD settings parameters.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14Atmel AT91 pin configuration node is a node of a group of pins which can be
15used for a specific device or function. This node represents both mux and config
16of the pins in that group. The 'pins' selects the function mode(also named pin
17mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, multi drive, etc.
19
20Required properties for iomux controller:
21- compatible: "atmel,at91rm9200-pinctrl"
22- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
23 configured in this periph mode. All the periph and bank need to be describe.
24
25How to create such array:
26
27Each column will represent the possible peripheral of the pinctrl
28Each line will represent a pio bank
29
30Take an example on the 9260
31Peripheral: 2 ( A and B)
32Bank: 3 (A, B and C)
33=>
34
35 /* A B */
36 0xffffffff 0xffc00c3b /* pioA */
37 0xffffffff 0x7fff3ccf /* pioB */
38 0xffffffff 0x007fffff /* pioC */
39
40For each peripheral/bank we will descibe in a u32 if a pin can can be
41configured in it by putting 1 to the pin bit (1 << pin)
42
43Let's take the pioA on peripheral B
44From the datasheet Table 10-2.
45Peripheral B
46PA0 MCDB0
47PA1 MCCDB
48PA2
49PA3 MCDB3
50PA4 MCDB2
51PA5 MCDB1
52PA6
53PA7
54PA8
55PA9
56PA10 ETX2
57PA11 ETX3
58PA12
59PA13
60PA14
61PA15
62PA16
63PA17
64PA18
65PA19
66PA20
67PA21
68PA22 ETXER
69PA23 ETX2
70PA24 ETX3
71PA25 ERX2
72PA26 ERX3
73PA27 ERXCK
74PA28 ECRS
75PA29 ECOL
76PA30 RXD4
77PA31 TXD4
78
79=> 0xffc00c3b
80
81Required properties for pin configuration node:
82- atmel,pins: 4 integers array, represents a group of pins mux and config
83 setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
84 The PERIPH 0 means gpio.
85
86Bits used for CONFIG:
87PULL_UP (1 << 0): indicate this pin need a pull up.
88MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive.
89DEGLITCH (1 << 2): indicate this pin need deglitch.
90PULL_DOWN (1 << 3): indicate this pin need a pull down.
91DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger.
92DEBOUNCE (1 << 16): indicate this pin need debounce.
93DEBOUNCE_VAL (0x3fff << 17): debounce val.
94
95NOTE:
96Some requirements for using atmel,at91rm9200-pinctrl binding:
971. We have pin function node defined under at91 controller node to represent
98 what pinmux functions this SoC supports.
992. The driver can use the function node's name and pin configuration node's
100 name describe the pin function and group hierarchy.
101 For example, Linux at91 pinctrl driver takes the function node's name
102 as the function name and pin configuration node's name as group name to
103 create the map table.
1043. Each pin configuration node should have a phandle, devices can set pins
105 configurations by referring to the phandle of that pin configuration node.
1064. The gpio controller must be describe in the pinctrl simple-bus.
107
108Examples:
109
110pinctrl@fffff400 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 ranges;
114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 reg = <0xfffff400 0x600>;
116
117 atmel,mux-mask = <
118 /* A B */
119 0xffffffff 0xffc00c3b /* pioA */
120 0xffffffff 0x7fff3ccf /* pioB */
121 0xffffffff 0x007fffff /* pioC */
122 >;
123
124 /* shared pinctrl settings */
125 dbgu {
126 pinctrl_dbgu: dbgu-0 {
127 atmel,pins =
128 <1 14 0x1 0x0 /* PB14 periph A */
129 1 15 0x1 0x1>; /* PB15 periph with pullup */
130 };
131 };
132};
133
134dbgu: serial@fffff200 {
135 compatible = "atmel,at91sam9260-usart";
136 reg = <0xfffff200 0x200>;
137 interrupts = <1 4 7>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_dbgu>;
140 status = "disabled";
141};
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
deleted file mode 100644
index 8edc20e1b09..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
+++ /dev/null
@@ -1,74 +0,0 @@
1Broadcom BCM2835 GPIO (and pinmux) controller
2
3The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
4controller, and pinmux/control device.
5
6Required properties:
7- compatible: "brcm,bcm2835-gpio"
8- reg: Should contain the physical address of the GPIO module's registes.
9- gpio-controller: Marks the device node as a GPIO controller.
10- #gpio-cells : Should be two. The first cell is the pin number and the
11 second cell is used to specify optional parameters:
12 - bit 0 specifies polarity (0 for normal, 1 for inverted)
13- interrupts : The interrupt outputs from the controller. One interrupt per
14 individual bank followed by the "all banks" interrupt.
15- interrupt-controller: Marks the device node as an interrupt controller.
16- #interrupt-cells : Should be 2.
17 The first cell is the GPIO number.
18 The second cell is used to specify flags:
19 bits[3:0] trigger type and level flags:
20 1 = low-to-high edge triggered.
21 2 = high-to-low edge triggered.
22 4 = active high level-sensitive.
23 8 = active low level-sensitive.
24 Valid combinations are 1, 2, 3, 4, 8.
25
26Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
27
28Please refer to pinctrl-bindings.txt in this directory for details of the
29common pinctrl bindings used by client devices, including the meaning of the
30phrase "pin configuration node".
31
32Each pin configuration node lists the pin(s) to which it applies, and one or
33more of the mux function to select on those pin(s), and pull-up/down
34configuration. Each subnode only affects those parameters that are explicitly
35listed. In other words, a subnode that lists only a mux function implies no
36information about any pull configuration. Similarly, a subnode that lists only
37a pul parameter implies no information about the mux function.
38
39Required subnode-properties:
40- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
41 are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
42
43Optional subnode-properties:
44- brcm,function: Integer, containing the function to mux to the pin(s):
45 0: GPIO in
46 1: GPIO out
47 2: alt5
48 3: alt4
49 4: alt0
50 5: alt1
51 6: alt2
52 7: alt3
53- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
54 0: none
55 1: down
56 2: up
57
58Each of brcm,function and brcm,pull may contain either a single value which
59will be applied to all pins in brcm,pins, or 1 value for each entry in
60brcm,pins.
61
62Example:
63
64 gpio: gpio {
65 compatible = "brcm,bcm2835-gpio";
66 reg = <0x2200000 0xb4>;
67 interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
68
69 gpio-controller;
70 #gpio-cells = <2>;
71
72 interrupt-controller;
73 #interrupt-cells = <2>;
74 };
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
deleted file mode 100644
index ab19e6bc7d3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ /dev/null
@@ -1,95 +0,0 @@
1* Freescale IOMUX Controller (IOMUXC) for i.MX
2
3The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
68 muxing options (called ALT modes). Since different modules require
7different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8also the PAD settings parameters.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14Freescale IMX pin configuration node is a node of a group of pins which can be
15used for a specific device or function. This node represents both mux and config
16of the pins in that group. The 'mux' selects the function mode(also named mux
17mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, open drain, drive strength, etc.
19
20Required properties for iomux controller:
21- compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
23
24Required properties for pin configuration node:
25- fsl,pins: two integers array, represents a group of pins mux and config
26 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
27 pin working on a specific function, CONFIG is the pad setting value like
28 pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
29 pins and functions of each SoC.
30
31Bits used for CONFIG:
32NO_PAD_CTL(1 << 31): indicate this pin does not need config.
33
34SION(1 << 30): Software Input On Field.
35Force the selected mux mode input path no matter of MUX_MODE functionality.
36By default the input path is determined by functionality of the selected
37mux mode (regular).
38
39Other bits are used for PAD setting.
40Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
41of bits definitions.
42
43NOTE:
44Some requirements for using fsl,imx-pinctrl binding:
451. We have pin function node defined under iomux controller node to represent
46 what pinmux functions this SoC supports.
472. The pin configuration node intends to work on a specific function should
48 to be defined under that specific function node.
49 The function node's name should represent well about what function
50 this group of pins in this pin configuration node are working on.
513. The driver can use the function node's name and pin configuration node's
52 name describe the pin function and group hierarchy.
53 For example, Linux IMX pinctrl driver takes the function node's name
54 as the function name and pin configuration node's name as group name to
55 create the map table.
564. Each pin configuration node should have a phandle, devices can set pins
57 configurations by referring to the phandle of that pin configuration node.
58
59Examples:
60usdhc@0219c000 { /* uSDHC4 */
61 fsl,card-wired;
62 vmmc-supply = <&reg_3p3v>;
63 status = "okay";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_usdhc4_1>;
66};
67
68iomuxc@020e0000 {
69 compatible = "fsl,imx6q-iomuxc";
70 reg = <0x020e0000 0x4000>;
71
72 /* shared pinctrl settings */
73 usdhc4 {
74 pinctrl_usdhc4_1: usdhc4grp-1 {
75 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
76 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
77 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
78 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
79 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
80 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
81 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
82 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
83 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
84 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
85 };
86 };
87 ....
88};
89Refer to the IOMUXC controller chapter in imx6q datasheet,
900x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
9180Ohm driver strength and Fast Slew Rate.
92User should refer to each SoC spec to set the correct value.
93
94TODO: when dtc macro support is available, we can change above raw data
95to dt macro which can get better readability in dts file.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
deleted file mode 100644
index 1183f1a3be3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
+++ /dev/null
@@ -1,984 +0,0 @@
1* Freescale IMX35 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx35-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
16PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
17PAD_CTL_HYS (1 << 8)
18PAD_CTL_PKE (1 << 7)
19PAD_CTL_PUE (1 << 6)
20PAD_CTL_PUS_100K_DOWN (0 << 4)
21PAD_CTL_PUS_47K_UP (1 << 4)
22PAD_CTL_PUS_100K_UP (2 << 4)
23PAD_CTL_PUS_22K_UP (3 << 4)
24PAD_CTL_ODE_CMOS (0 << 3)
25PAD_CTL_ODE_OPENDRAIN (1 << 3)
26PAD_CTL_DSE_NOMINAL (0 << 1)
27PAD_CTL_DSE_HIGH (1 << 1)
28PAD_CTL_DSE_MAX (2 << 1)
29PAD_CTL_SRE_FAST (1 << 0)
30PAD_CTL_SRE_SLOW (0 << 0)
31
32See below for available PIN_FUNC_ID for imx35:
330 MX35_PAD_CAPTURE__GPT_CAPIN1
341 MX35_PAD_CAPTURE__GPT_CMPOUT2
352 MX35_PAD_CAPTURE__CSPI2_SS1
363 MX35_PAD_CAPTURE__EPIT1_EPITO
374 MX35_PAD_CAPTURE__CCM_CLK32K
385 MX35_PAD_CAPTURE__GPIO1_4
396 MX35_PAD_COMPARE__GPT_CMPOUT1
407 MX35_PAD_COMPARE__GPT_CAPIN2
418 MX35_PAD_COMPARE__GPT_CMPOUT3
429 MX35_PAD_COMPARE__EPIT2_EPITO
4310 MX35_PAD_COMPARE__GPIO1_5
4411 MX35_PAD_COMPARE__SDMA_EXTDMA_2
4512 MX35_PAD_WDOG_RST__WDOG_WDOG_B
4613 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
4714 MX35_PAD_WDOG_RST__GPIO1_6
4815 MX35_PAD_GPIO1_0__GPIO1_0
4916 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
5017 MX35_PAD_GPIO1_0__OWIRE_LINE
5118 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
5219 MX35_PAD_GPIO1_1__GPIO1_1
5320 MX35_PAD_GPIO1_1__PWM_PWMO
5421 MX35_PAD_GPIO1_1__CSPI1_SS2
5522 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
5623 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
5724 MX35_PAD_GPIO2_0__GPIO2_0
5825 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
5926 MX35_PAD_GPIO3_0__GPIO3_0
6027 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
6128 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
6229 MX35_PAD_POR_B__CCM_POR_B
6330 MX35_PAD_CLKO__CCM_CLKO
6431 MX35_PAD_CLKO__GPIO1_8
6532 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
6633 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
6734 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
6835 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
6936 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
7037 MX35_PAD_VSTBY__CCM_VSTBY
7138 MX35_PAD_VSTBY__GPIO1_7
7239 MX35_PAD_A0__EMI_EIM_DA_L_0
7340 MX35_PAD_A1__EMI_EIM_DA_L_1
7441 MX35_PAD_A2__EMI_EIM_DA_L_2
7542 MX35_PAD_A3__EMI_EIM_DA_L_3
7643 MX35_PAD_A4__EMI_EIM_DA_L_4
7744 MX35_PAD_A5__EMI_EIM_DA_L_5
7845 MX35_PAD_A6__EMI_EIM_DA_L_6
7946 MX35_PAD_A7__EMI_EIM_DA_L_7
8047 MX35_PAD_A8__EMI_EIM_DA_H_8
8148 MX35_PAD_A9__EMI_EIM_DA_H_9
8249 MX35_PAD_A10__EMI_EIM_DA_H_10
8350 MX35_PAD_MA10__EMI_MA10
8451 MX35_PAD_A11__EMI_EIM_DA_H_11
8552 MX35_PAD_A12__EMI_EIM_DA_H_12
8653 MX35_PAD_A13__EMI_EIM_DA_H_13
8754 MX35_PAD_A14__EMI_EIM_DA_H2_14
8855 MX35_PAD_A15__EMI_EIM_DA_H2_15
8956 MX35_PAD_A16__EMI_EIM_A_16
9057 MX35_PAD_A17__EMI_EIM_A_17
9158 MX35_PAD_A18__EMI_EIM_A_18
9259 MX35_PAD_A19__EMI_EIM_A_19
9360 MX35_PAD_A20__EMI_EIM_A_20
9461 MX35_PAD_A21__EMI_EIM_A_21
9562 MX35_PAD_A22__EMI_EIM_A_22
9663 MX35_PAD_A23__EMI_EIM_A_23
9764 MX35_PAD_A24__EMI_EIM_A_24
9865 MX35_PAD_A25__EMI_EIM_A_25
9966 MX35_PAD_SDBA1__EMI_EIM_SDBA1
10067 MX35_PAD_SDBA0__EMI_EIM_SDBA0
10168 MX35_PAD_SD0__EMI_DRAM_D_0
10269 MX35_PAD_SD1__EMI_DRAM_D_1
10370 MX35_PAD_SD2__EMI_DRAM_D_2
10471 MX35_PAD_SD3__EMI_DRAM_D_3
10572 MX35_PAD_SD4__EMI_DRAM_D_4
10673 MX35_PAD_SD5__EMI_DRAM_D_5
10774 MX35_PAD_SD6__EMI_DRAM_D_6
10875 MX35_PAD_SD7__EMI_DRAM_D_7
10976 MX35_PAD_SD8__EMI_DRAM_D_8
11077 MX35_PAD_SD9__EMI_DRAM_D_9
11178 MX35_PAD_SD10__EMI_DRAM_D_10
11279 MX35_PAD_SD11__EMI_DRAM_D_11
11380 MX35_PAD_SD12__EMI_DRAM_D_12
11481 MX35_PAD_SD13__EMI_DRAM_D_13
11582 MX35_PAD_SD14__EMI_DRAM_D_14
11683 MX35_PAD_SD15__EMI_DRAM_D_15
11784 MX35_PAD_SD16__EMI_DRAM_D_16
11885 MX35_PAD_SD17__EMI_DRAM_D_17
11986 MX35_PAD_SD18__EMI_DRAM_D_18
12087 MX35_PAD_SD19__EMI_DRAM_D_19
12188 MX35_PAD_SD20__EMI_DRAM_D_20
12289 MX35_PAD_SD21__EMI_DRAM_D_21
12390 MX35_PAD_SD22__EMI_DRAM_D_22
12491 MX35_PAD_SD23__EMI_DRAM_D_23
12592 MX35_PAD_SD24__EMI_DRAM_D_24
12693 MX35_PAD_SD25__EMI_DRAM_D_25
12794 MX35_PAD_SD26__EMI_DRAM_D_26
12895 MX35_PAD_SD27__EMI_DRAM_D_27
12996 MX35_PAD_SD28__EMI_DRAM_D_28
13097 MX35_PAD_SD29__EMI_DRAM_D_29
13198 MX35_PAD_SD30__EMI_DRAM_D_30
13299 MX35_PAD_SD31__EMI_DRAM_D_31
133100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
134101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
135102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
136103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
137104 MX35_PAD_EB0__EMI_EIM_EB0_B
138105 MX35_PAD_EB1__EMI_EIM_EB1_B
139106 MX35_PAD_OE__EMI_EIM_OE
140107 MX35_PAD_CS0__EMI_EIM_CS0
141108 MX35_PAD_CS1__EMI_EIM_CS1
142109 MX35_PAD_CS1__EMI_NANDF_CE3
143110 MX35_PAD_CS2__EMI_EIM_CS2
144111 MX35_PAD_CS3__EMI_EIM_CS3
145112 MX35_PAD_CS4__EMI_EIM_CS4
146113 MX35_PAD_CS4__EMI_DTACK_B
147114 MX35_PAD_CS4__EMI_NANDF_CE1
148115 MX35_PAD_CS4__GPIO1_20
149116 MX35_PAD_CS5__EMI_EIM_CS5
150117 MX35_PAD_CS5__CSPI2_SS2
151118 MX35_PAD_CS5__CSPI1_SS2
152119 MX35_PAD_CS5__EMI_NANDF_CE2
153120 MX35_PAD_CS5__GPIO1_21
154121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
155122 MX35_PAD_NF_CE0__GPIO1_22
156123 MX35_PAD_ECB__EMI_EIM_ECB
157124 MX35_PAD_LBA__EMI_EIM_LBA
158125 MX35_PAD_BCLK__EMI_EIM_BCLK
159126 MX35_PAD_RW__EMI_EIM_RW
160127 MX35_PAD_RAS__EMI_DRAM_RAS
161128 MX35_PAD_CAS__EMI_DRAM_CAS
162129 MX35_PAD_SDWE__EMI_DRAM_SDWE
163130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
164131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
165132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
166133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
167134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
168135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
169136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
170137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
171138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
172139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
173140 MX35_PAD_NFWE_B__GPIO2_18
174141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
175142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
176143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
177144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
178145 MX35_PAD_NFRE_B__GPIO2_19
179146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
180147 MX35_PAD_NFALE__EMI_NANDF_ALE
181148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
182149 MX35_PAD_NFALE__IPU_DISPB_CS0
183150 MX35_PAD_NFALE__GPIO2_20
184151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
185152 MX35_PAD_NFCLE__EMI_NANDF_CLE
186153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
187154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
188155 MX35_PAD_NFCLE__GPIO2_21
189156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
190157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
191158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
192159 MX35_PAD_NFWP_B__IPU_DISPB_WR
193160 MX35_PAD_NFWP_B__GPIO2_22
194161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
195162 MX35_PAD_NFRB__EMI_NANDF_RB
196163 MX35_PAD_NFRB__IPU_DISPB_RD
197164 MX35_PAD_NFRB__GPIO2_23
198165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
199166 MX35_PAD_D15__EMI_EIM_D_15
200167 MX35_PAD_D14__EMI_EIM_D_14
201168 MX35_PAD_D13__EMI_EIM_D_13
202169 MX35_PAD_D12__EMI_EIM_D_12
203170 MX35_PAD_D11__EMI_EIM_D_11
204171 MX35_PAD_D10__EMI_EIM_D_10
205172 MX35_PAD_D9__EMI_EIM_D_9
206173 MX35_PAD_D8__EMI_EIM_D_8
207174 MX35_PAD_D7__EMI_EIM_D_7
208175 MX35_PAD_D6__EMI_EIM_D_6
209176 MX35_PAD_D5__EMI_EIM_D_5
210177 MX35_PAD_D4__EMI_EIM_D_4
211178 MX35_PAD_D3__EMI_EIM_D_3
212179 MX35_PAD_D2__EMI_EIM_D_2
213180 MX35_PAD_D1__EMI_EIM_D_1
214181 MX35_PAD_D0__EMI_EIM_D_0
215182 MX35_PAD_CSI_D8__IPU_CSI_D_8
216183 MX35_PAD_CSI_D8__KPP_COL_0
217184 MX35_PAD_CSI_D8__GPIO1_20
218185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
219186 MX35_PAD_CSI_D9__IPU_CSI_D_9
220187 MX35_PAD_CSI_D9__KPP_COL_1
221188 MX35_PAD_CSI_D9__GPIO1_21
222189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
223190 MX35_PAD_CSI_D10__IPU_CSI_D_10
224191 MX35_PAD_CSI_D10__KPP_COL_2
225192 MX35_PAD_CSI_D10__GPIO1_22
226193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
227194 MX35_PAD_CSI_D11__IPU_CSI_D_11
228195 MX35_PAD_CSI_D11__KPP_COL_3
229196 MX35_PAD_CSI_D11__GPIO1_23
230197 MX35_PAD_CSI_D12__IPU_CSI_D_12
231198 MX35_PAD_CSI_D12__KPP_ROW_0
232199 MX35_PAD_CSI_D12__GPIO1_24
233200 MX35_PAD_CSI_D13__IPU_CSI_D_13
234201 MX35_PAD_CSI_D13__KPP_ROW_1
235202 MX35_PAD_CSI_D13__GPIO1_25
236203 MX35_PAD_CSI_D14__IPU_CSI_D_14
237204 MX35_PAD_CSI_D14__KPP_ROW_2
238205 MX35_PAD_CSI_D14__GPIO1_26
239206 MX35_PAD_CSI_D15__IPU_CSI_D_15
240207 MX35_PAD_CSI_D15__KPP_ROW_3
241208 MX35_PAD_CSI_D15__GPIO1_27
242209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
243210 MX35_PAD_CSI_MCLK__GPIO1_28
244211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
245212 MX35_PAD_CSI_VSYNC__GPIO1_29
246213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
247214 MX35_PAD_CSI_HSYNC__GPIO1_30
248215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
249216 MX35_PAD_CSI_PIXCLK__GPIO1_31
250217 MX35_PAD_I2C1_CLK__I2C1_SCL
251218 MX35_PAD_I2C1_CLK__GPIO2_24
252219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
253220 MX35_PAD_I2C1_DAT__I2C1_SDA
254221 MX35_PAD_I2C1_DAT__GPIO2_25
255222 MX35_PAD_I2C2_CLK__I2C2_SCL
256223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
257224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
258225 MX35_PAD_I2C2_CLK__GPIO2_26
259226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
260227 MX35_PAD_I2C2_DAT__I2C2_SDA
261228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
262229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
263230 MX35_PAD_I2C2_DAT__GPIO2_27
264231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
265232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
266233 MX35_PAD_STXD4__GPIO2_28
267234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
268235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
269236 MX35_PAD_SRXD4__GPIO2_29
270237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
271238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
272239 MX35_PAD_SCK4__GPIO2_30
273240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
274241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
275242 MX35_PAD_STXFS4__GPIO2_31
276243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
277244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
278245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
279246 MX35_PAD_STXD5__CSPI2_MOSI
280247 MX35_PAD_STXD5__GPIO1_0
281248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
282249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
283250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
284251 MX35_PAD_SRXD5__CSPI2_MISO
285252 MX35_PAD_SRXD5__GPIO1_1
286253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
287254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
288255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
289256 MX35_PAD_SCK5__CSPI2_SCLK
290257 MX35_PAD_SCK5__GPIO1_2
291258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
292259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
293260 MX35_PAD_STXFS5__CSPI2_RDY
294261 MX35_PAD_STXFS5__GPIO1_3
295262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
296263 MX35_PAD_SCKR__ESAI_SCKR
297264 MX35_PAD_SCKR__GPIO1_4
298265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
299266 MX35_PAD_FSR__ESAI_FSR
300267 MX35_PAD_FSR__GPIO1_5
301268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
302269 MX35_PAD_HCKR__ESAI_HCKR
303270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
304271 MX35_PAD_HCKR__CSPI2_SS0
305272 MX35_PAD_HCKR__IPU_FLASH_STROBE
306273 MX35_PAD_HCKR__GPIO1_6
307274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
308275 MX35_PAD_SCKT__ESAI_SCKT
309276 MX35_PAD_SCKT__GPIO1_7
310277 MX35_PAD_SCKT__IPU_CSI_D_0
311278 MX35_PAD_SCKT__KPP_ROW_2
312279 MX35_PAD_FST__ESAI_FST
313280 MX35_PAD_FST__GPIO1_8
314281 MX35_PAD_FST__IPU_CSI_D_1
315282 MX35_PAD_FST__KPP_ROW_3
316283 MX35_PAD_HCKT__ESAI_HCKT
317284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
318285 MX35_PAD_HCKT__GPIO1_9
319286 MX35_PAD_HCKT__IPU_CSI_D_2
320287 MX35_PAD_HCKT__KPP_COL_3
321288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
322289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
323290 MX35_PAD_TX5_RX0__CSPI2_SS2
324291 MX35_PAD_TX5_RX0__CAN2_TXCAN
325292 MX35_PAD_TX5_RX0__UART2_DTR
326293 MX35_PAD_TX5_RX0__GPIO1_10
327294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
328295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
329296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
330297 MX35_PAD_TX4_RX1__CSPI2_SS3
331298 MX35_PAD_TX4_RX1__CAN2_RXCAN
332299 MX35_PAD_TX4_RX1__UART2_DSR
333300 MX35_PAD_TX4_RX1__GPIO1_11
334301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
335302 MX35_PAD_TX4_RX1__KPP_ROW_0
336303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
337304 MX35_PAD_TX3_RX2__I2C3_SCL
338305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
339306 MX35_PAD_TX3_RX2__GPIO1_12
340307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
341308 MX35_PAD_TX3_RX2__KPP_ROW_1
342309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
343310 MX35_PAD_TX2_RX3__I2C3_SDA
344311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
345312 MX35_PAD_TX2_RX3__GPIO1_13
346313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
347314 MX35_PAD_TX2_RX3__KPP_COL_0
348315 MX35_PAD_TX1__ESAI_TX1
349316 MX35_PAD_TX1__CCM_PMIC_RDY
350317 MX35_PAD_TX1__CSPI1_SS2
351318 MX35_PAD_TX1__EMI_NANDF_CE3
352319 MX35_PAD_TX1__UART2_RI
353320 MX35_PAD_TX1__GPIO1_14
354321 MX35_PAD_TX1__IPU_CSI_D_6
355322 MX35_PAD_TX1__KPP_COL_1
356323 MX35_PAD_TX0__ESAI_TX0
357324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
358325 MX35_PAD_TX0__CSPI1_SS3
359326 MX35_PAD_TX0__EMI_DTACK_B
360327 MX35_PAD_TX0__UART2_DCD
361328 MX35_PAD_TX0__GPIO1_15
362329 MX35_PAD_TX0__IPU_CSI_D_7
363330 MX35_PAD_TX0__KPP_COL_2
364331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
365332 MX35_PAD_CSPI1_MOSI__GPIO1_16
366333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
367334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
368335 MX35_PAD_CSPI1_MISO__GPIO1_17
369336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
370337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
371338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
372339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
373340 MX35_PAD_CSPI1_SS0__GPIO1_18
374341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
375342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
376343 MX35_PAD_CSPI1_SS1__PWM_PWMO
377344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
378345 MX35_PAD_CSPI1_SS1__GPIO1_19
379346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
380347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
381348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
382349 MX35_PAD_CSPI1_SCLK__GPIO3_4
383350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
384351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
385352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
386353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
387354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
388355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
389356 MX35_PAD_RXD1__UART1_RXD_MUX
390357 MX35_PAD_RXD1__CSPI2_MOSI
391358 MX35_PAD_RXD1__KPP_COL_4
392359 MX35_PAD_RXD1__GPIO3_6
393360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
394361 MX35_PAD_TXD1__UART1_TXD_MUX
395362 MX35_PAD_TXD1__CSPI2_MISO
396363 MX35_PAD_TXD1__KPP_COL_5
397364 MX35_PAD_TXD1__GPIO3_7
398365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
399366 MX35_PAD_RTS1__UART1_RTS
400367 MX35_PAD_RTS1__CSPI2_SCLK
401368 MX35_PAD_RTS1__I2C3_SCL
402369 MX35_PAD_RTS1__IPU_CSI_D_0
403370 MX35_PAD_RTS1__KPP_COL_6
404371 MX35_PAD_RTS1__GPIO3_8
405372 MX35_PAD_RTS1__EMI_NANDF_CE1
406373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
407374 MX35_PAD_CTS1__UART1_CTS
408375 MX35_PAD_CTS1__CSPI2_RDY
409376 MX35_PAD_CTS1__I2C3_SDA
410377 MX35_PAD_CTS1__IPU_CSI_D_1
411378 MX35_PAD_CTS1__KPP_COL_7
412379 MX35_PAD_CTS1__GPIO3_9
413380 MX35_PAD_CTS1__EMI_NANDF_CE2
414381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
415382 MX35_PAD_RXD2__UART2_RXD_MUX
416383 MX35_PAD_RXD2__KPP_ROW_4
417384 MX35_PAD_RXD2__GPIO3_10
418385 MX35_PAD_TXD2__UART2_TXD_MUX
419386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
420387 MX35_PAD_TXD2__KPP_ROW_5
421388 MX35_PAD_TXD2__GPIO3_11
422389 MX35_PAD_RTS2__UART2_RTS
423390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
424391 MX35_PAD_RTS2__CAN2_RXCAN
425392 MX35_PAD_RTS2__IPU_CSI_D_2
426393 MX35_PAD_RTS2__KPP_ROW_6
427394 MX35_PAD_RTS2__GPIO3_12
428395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
429396 MX35_PAD_RTS2__UART3_RXD_MUX
430397 MX35_PAD_CTS2__UART2_CTS
431398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
432399 MX35_PAD_CTS2__CAN2_TXCAN
433400 MX35_PAD_CTS2__IPU_CSI_D_3
434401 MX35_PAD_CTS2__KPP_ROW_7
435402 MX35_PAD_CTS2__GPIO3_13
436403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
437404 MX35_PAD_CTS2__UART3_TXD_MUX
438405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
439406 MX35_PAD_TCK__SJC_TCK
440407 MX35_PAD_TMS__SJC_TMS
441408 MX35_PAD_TDI__SJC_TDI
442409 MX35_PAD_TDO__SJC_TDO
443410 MX35_PAD_TRSTB__SJC_TRSTB
444411 MX35_PAD_DE_B__SJC_DE_B
445412 MX35_PAD_SJC_MOD__SJC_MOD
446413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
447414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
448415 MX35_PAD_USBOTG_PWR__GPIO3_14
449416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
450417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
451418 MX35_PAD_USBOTG_OC__GPIO3_15
452419 MX35_PAD_LD0__IPU_DISPB_DAT_0
453420 MX35_PAD_LD0__GPIO2_0
454421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
455422 MX35_PAD_LD1__IPU_DISPB_DAT_1
456423 MX35_PAD_LD1__GPIO2_1
457424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
458425 MX35_PAD_LD2__IPU_DISPB_DAT_2
459426 MX35_PAD_LD2__GPIO2_2
460427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
461428 MX35_PAD_LD3__IPU_DISPB_DAT_3
462429 MX35_PAD_LD3__GPIO2_3
463430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
464431 MX35_PAD_LD4__IPU_DISPB_DAT_4
465432 MX35_PAD_LD4__GPIO2_4
466433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
467434 MX35_PAD_LD5__IPU_DISPB_DAT_5
468435 MX35_PAD_LD5__GPIO2_5
469436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
470437 MX35_PAD_LD6__IPU_DISPB_DAT_6
471438 MX35_PAD_LD6__GPIO2_6
472439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
473440 MX35_PAD_LD7__IPU_DISPB_DAT_7
474441 MX35_PAD_LD7__GPIO2_7
475442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
476443 MX35_PAD_LD8__IPU_DISPB_DAT_8
477444 MX35_PAD_LD8__GPIO2_8
478445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
479446 MX35_PAD_LD9__IPU_DISPB_DAT_9
480447 MX35_PAD_LD9__GPIO2_9
481448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
482449 MX35_PAD_LD10__IPU_DISPB_DAT_10
483450 MX35_PAD_LD10__GPIO2_10
484451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
485452 MX35_PAD_LD11__IPU_DISPB_DAT_11
486453 MX35_PAD_LD11__GPIO2_11
487454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
488455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
489456 MX35_PAD_LD12__IPU_DISPB_DAT_12
490457 MX35_PAD_LD12__GPIO2_12
491458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
492459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
493460 MX35_PAD_LD13__IPU_DISPB_DAT_13
494461 MX35_PAD_LD13__GPIO2_13
495462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
496463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
497464 MX35_PAD_LD14__IPU_DISPB_DAT_14
498465 MX35_PAD_LD14__GPIO2_14
499466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
500467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
501468 MX35_PAD_LD15__IPU_DISPB_DAT_15
502469 MX35_PAD_LD15__GPIO2_15
503470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
504471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
505472 MX35_PAD_LD16__IPU_DISPB_DAT_16
506473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
507474 MX35_PAD_LD16__GPIO2_16
508475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
509476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
510477 MX35_PAD_LD17__IPU_DISPB_DAT_17
511478 MX35_PAD_LD17__IPU_DISPB_CS2
512479 MX35_PAD_LD17__GPIO2_17
513480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
514481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
515482 MX35_PAD_LD18__IPU_DISPB_DAT_18
516483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
517484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
518485 MX35_PAD_LD18__ESDHC3_CMD
519486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
520487 MX35_PAD_LD18__GPIO3_24
521488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
522489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
523490 MX35_PAD_LD19__IPU_DISPB_DAT_19
524491 MX35_PAD_LD19__IPU_DISPB_BCLK
525492 MX35_PAD_LD19__IPU_DISPB_CS1
526493 MX35_PAD_LD19__ESDHC3_CLK
527494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
528495 MX35_PAD_LD19__GPIO3_25
529496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
530497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
531498 MX35_PAD_LD20__IPU_DISPB_DAT_20
532499 MX35_PAD_LD20__IPU_DISPB_CS0
533500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
534501 MX35_PAD_LD20__ESDHC3_DAT0
535502 MX35_PAD_LD20__GPIO3_26
536503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
537504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
538505 MX35_PAD_LD21__IPU_DISPB_DAT_21
539506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
540507 MX35_PAD_LD21__IPU_DISPB_SER_RS
541508 MX35_PAD_LD21__ESDHC3_DAT1
542509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
543510 MX35_PAD_LD21__GPIO3_27
544511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
545512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
546513 MX35_PAD_LD22__IPU_DISPB_DAT_22
547514 MX35_PAD_LD22__IPU_DISPB_WR
548515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
549516 MX35_PAD_LD22__ESDHC3_DAT2
550517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
551518 MX35_PAD_LD22__GPIO3_28
552519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
553520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
554521 MX35_PAD_LD23__IPU_DISPB_DAT_23
555522 MX35_PAD_LD23__IPU_DISPB_RD
556523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
557524 MX35_PAD_LD23__ESDHC3_DAT3
558525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
559526 MX35_PAD_LD23__GPIO3_29
560527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
561528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
562529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
563530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
564531 MX35_PAD_D3_HSYNC__GPIO3_30
565532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
566533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
567534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
568535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
569536 MX35_PAD_D3_FPSHIFT__GPIO3_31
570537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
571538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
572539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
573540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
574541 MX35_PAD_D3_DRDY__GPIO1_0
575542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
576543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
577544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
578545 MX35_PAD_CONTRAST__GPIO1_1
579546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
580547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
581548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
582549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
583550 MX35_PAD_D3_VSYNC__GPIO1_2
584551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
585552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
586553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
587554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
588555 MX35_PAD_D3_REV__GPIO1_3
589556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
590557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
591558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
592559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
593560 MX35_PAD_D3_CLS__GPIO1_4
594561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
595562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
596563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
597564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
598565 MX35_PAD_D3_SPL__GPIO1_5
599566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
600567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
601568 MX35_PAD_SD1_CMD__ESDHC1_CMD
602569 MX35_PAD_SD1_CMD__MSHC_SCLK
603570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
604571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
605572 MX35_PAD_SD1_CMD__GPIO1_6
606573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
607574 MX35_PAD_SD1_CLK__ESDHC1_CLK
608575 MX35_PAD_SD1_CLK__MSHC_BS
609576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
610577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
611578 MX35_PAD_SD1_CLK__GPIO1_7
612579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
613580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
614581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
615582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
616583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
617584 MX35_PAD_SD1_DATA0__GPIO1_8
618585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
619586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
620587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
621588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
622589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
623590 MX35_PAD_SD1_DATA1__GPIO1_9
624591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
625592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
626593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
627594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
628595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
629596 MX35_PAD_SD1_DATA2__GPIO1_10
630597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
631598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
632599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
633600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
634601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
635602 MX35_PAD_SD1_DATA3__GPIO1_11
636603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
637604 MX35_PAD_SD2_CMD__ESDHC2_CMD
638605 MX35_PAD_SD2_CMD__I2C3_SCL
639606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
640607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
641608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
642609 MX35_PAD_SD2_CMD__GPIO2_0
643610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
644611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
645612 MX35_PAD_SD2_CLK__ESDHC2_CLK
646613 MX35_PAD_SD2_CLK__I2C3_SDA
647614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
648615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
649616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
650617 MX35_PAD_SD2_CLK__GPIO2_1
651618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
652619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
653620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
654621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
655622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
656623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
657624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
658625 MX35_PAD_SD2_DATA0__GPIO2_2
659626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
660627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
661628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
662629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
663630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
664631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
665632 MX35_PAD_SD2_DATA1__GPIO2_3
666633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
667634 MX35_PAD_SD2_DATA2__UART3_RTS
668635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
669636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
670637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
671638 MX35_PAD_SD2_DATA2__GPIO2_4
672639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
673640 MX35_PAD_SD2_DATA3__UART3_CTS
674641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
675642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
676643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
677644 MX35_PAD_SD2_DATA3__GPIO2_5
678645 MX35_PAD_ATA_CS0__ATA_CS0
679646 MX35_PAD_ATA_CS0__CSPI1_SS3
680647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
681648 MX35_PAD_ATA_CS0__GPIO2_6
682649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
683650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
684651 MX35_PAD_ATA_CS1__ATA_CS1
685652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
686653 MX35_PAD_ATA_CS1__CSPI2_SS0
687654 MX35_PAD_ATA_CS1__GPIO2_7
688655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
689656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
690657 MX35_PAD_ATA_DIOR__ATA_DIOR
691658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
692659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
693660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
694661 MX35_PAD_ATA_DIOR__CSPI2_SS1
695662 MX35_PAD_ATA_DIOR__GPIO2_8
696663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
697664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
698665 MX35_PAD_ATA_DIOW__ATA_DIOW
699666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
700667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
701668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
702669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
703670 MX35_PAD_ATA_DIOW__GPIO2_9
704671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
705672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
706673 MX35_PAD_ATA_DMACK__ATA_DMACK
707674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
708675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
709676 MX35_PAD_ATA_DMACK__CSPI2_MISO
710677 MX35_PAD_ATA_DMACK__GPIO2_10
711678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
712679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
713680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
714681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
715682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
716683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
717684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
718685 MX35_PAD_ATA_RESET_B__GPIO2_11
719686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
720687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
721688 MX35_PAD_ATA_IORDY__ATA_IORDY
722689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
723690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
724691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
725692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
726693 MX35_PAD_ATA_IORDY__GPIO2_12
727694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
728695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
729696 MX35_PAD_ATA_DATA0__ATA_DATA_0
730697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
731698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
732699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
733700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
734701 MX35_PAD_ATA_DATA0__GPIO2_13
735702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
736703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
737704 MX35_PAD_ATA_DATA1__ATA_DATA_1
738705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
739706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
740707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
741708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
742709 MX35_PAD_ATA_DATA1__GPIO2_14
743710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
744711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
745712 MX35_PAD_ATA_DATA2__ATA_DATA_2
746713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
747714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
748715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
749716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
750717 MX35_PAD_ATA_DATA2__GPIO2_15
751718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
752719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
753720 MX35_PAD_ATA_DATA3__ATA_DATA_3
754721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
755722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
756723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
757724 MX35_PAD_ATA_DATA3__GPIO2_16
758725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
759726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
760727 MX35_PAD_ATA_DATA4__ATA_DATA_4
761728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
762729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
763730 MX35_PAD_ATA_DATA4__GPIO2_17
764731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
765732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
766733 MX35_PAD_ATA_DATA5__ATA_DATA_5
767734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
768735 MX35_PAD_ATA_DATA5__GPIO2_18
769736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
770737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
771738 MX35_PAD_ATA_DATA6__ATA_DATA_6
772739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
773740 MX35_PAD_ATA_DATA6__UART1_DTR
774741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
775742 MX35_PAD_ATA_DATA6__GPIO2_19
776743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
777744 MX35_PAD_ATA_DATA7__ATA_DATA_7
778745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
779746 MX35_PAD_ATA_DATA7__UART1_DSR
780747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
781748 MX35_PAD_ATA_DATA7__GPIO2_20
782749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
783750 MX35_PAD_ATA_DATA8__ATA_DATA_8
784751 MX35_PAD_ATA_DATA8__UART3_RTS
785752 MX35_PAD_ATA_DATA8__UART1_RI
786753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
787754 MX35_PAD_ATA_DATA8__GPIO2_21
788755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
789756 MX35_PAD_ATA_DATA9__ATA_DATA_9
790757 MX35_PAD_ATA_DATA9__UART3_CTS
791758 MX35_PAD_ATA_DATA9__UART1_DCD
792759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
793760 MX35_PAD_ATA_DATA9__GPIO2_22
794761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
795762 MX35_PAD_ATA_DATA10__ATA_DATA_10
796763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
797764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
798765 MX35_PAD_ATA_DATA10__GPIO2_23
799766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
800767 MX35_PAD_ATA_DATA11__ATA_DATA_11
801768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
802769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
803770 MX35_PAD_ATA_DATA11__GPIO2_24
804771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
805772 MX35_PAD_ATA_DATA12__ATA_DATA_12
806773 MX35_PAD_ATA_DATA12__I2C3_SCL
807774 MX35_PAD_ATA_DATA12__GPIO2_25
808775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
809776 MX35_PAD_ATA_DATA13__ATA_DATA_13
810777 MX35_PAD_ATA_DATA13__I2C3_SDA
811778 MX35_PAD_ATA_DATA13__GPIO2_26
812779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
813780 MX35_PAD_ATA_DATA14__ATA_DATA_14
814781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
815782 MX35_PAD_ATA_DATA14__KPP_ROW_0
816783 MX35_PAD_ATA_DATA14__GPIO2_27
817784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
818785 MX35_PAD_ATA_DATA15__ATA_DATA_15
819786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
820787 MX35_PAD_ATA_DATA15__KPP_ROW_1
821788 MX35_PAD_ATA_DATA15__GPIO2_28
822789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
823790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
824791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
825792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
826793 MX35_PAD_ATA_INTRQ__GPIO2_29
827794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
828795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
829796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
830797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
831798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
832799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
833800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
834801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
835802 MX35_PAD_ATA_DMARQ__KPP_COL_0
836803 MX35_PAD_ATA_DMARQ__GPIO2_31
837804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
838805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
839806 MX35_PAD_ATA_DA0__ATA_DA_0
840807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
841808 MX35_PAD_ATA_DA0__KPP_COL_1
842809 MX35_PAD_ATA_DA0__GPIO3_0
843810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
844811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
845812 MX35_PAD_ATA_DA1__ATA_DA_1
846813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
847814 MX35_PAD_ATA_DA1__KPP_COL_2
848815 MX35_PAD_ATA_DA1__GPIO3_1
849816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
850817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
851818 MX35_PAD_ATA_DA2__ATA_DA_2
852819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
853820 MX35_PAD_ATA_DA2__KPP_COL_3
854821 MX35_PAD_ATA_DA2__GPIO3_2
855822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
856823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
857824 MX35_PAD_MLB_CLK__MLB_MLBCLK
858825 MX35_PAD_MLB_CLK__GPIO3_3
859826 MX35_PAD_MLB_DAT__MLB_MLBDAT
860827 MX35_PAD_MLB_DAT__GPIO3_4
861828 MX35_PAD_MLB_SIG__MLB_MLBSIG
862829 MX35_PAD_MLB_SIG__GPIO3_5
863830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
864831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
865832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
866833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
867834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
868835 MX35_PAD_FEC_TX_CLK__GPIO3_6
869836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
870837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
871838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
872839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
873840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
874841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
875842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
876843 MX35_PAD_FEC_RX_CLK__GPIO3_7
877844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
878845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
879846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
880847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
881848 MX35_PAD_FEC_RX_DV__UART3_RTS
882849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
883850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
884851 MX35_PAD_FEC_RX_DV__GPIO3_8
885852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
886853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
887854 MX35_PAD_FEC_COL__FEC_COL
888855 MX35_PAD_FEC_COL__ESDHC1_DAT7
889856 MX35_PAD_FEC_COL__UART3_CTS
890857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
891858 MX35_PAD_FEC_COL__CSPI2_RDY
892859 MX35_PAD_FEC_COL__GPIO3_9
893860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
894861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
895862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
896863 MX35_PAD_FEC_RDATA0__PWM_PWMO
897864 MX35_PAD_FEC_RDATA0__UART3_DTR
898865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
899866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
900867 MX35_PAD_FEC_RDATA0__GPIO3_10
901868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
902869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
903870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
904871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
905872 MX35_PAD_FEC_TDATA0__UART3_DSR
906873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
907874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
908875 MX35_PAD_FEC_TDATA0__GPIO3_11
909876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
910877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
911878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
912879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
913880 MX35_PAD_FEC_TX_EN__UART3_RI
914881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
915882 MX35_PAD_FEC_TX_EN__GPIO3_12
916883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
917884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
918885 MX35_PAD_FEC_MDC__FEC_MDC
919886 MX35_PAD_FEC_MDC__CAN2_TXCAN
920887 MX35_PAD_FEC_MDC__UART3_DCD
921888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
922889 MX35_PAD_FEC_MDC__GPIO3_13
923890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
924891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
925892 MX35_PAD_FEC_MDIO__FEC_MDIO
926893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
927894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
928895 MX35_PAD_FEC_MDIO__GPIO3_14
929896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
930897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
931898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
932899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
933900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
934901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
935902 MX35_PAD_FEC_TX_ERR__GPIO3_15
936903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
937904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
938905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
939906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
940907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
941908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
942909 MX35_PAD_FEC_RX_ERR__GPIO3_16
943910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
944911 MX35_PAD_FEC_CRS__FEC_CRS
945912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
946913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
947914 MX35_PAD_FEC_CRS__KPP_COL_5
948915 MX35_PAD_FEC_CRS__GPIO3_17
949916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
950917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
951918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
952919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
953920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
954921 MX35_PAD_FEC_RDATA1__KPP_COL_6
955922 MX35_PAD_FEC_RDATA1__GPIO3_18
956923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
957924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
958925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
959926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
960927 MX35_PAD_FEC_TDATA1__KPP_COL_7
961928 MX35_PAD_FEC_TDATA1__GPIO3_19
962929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
963930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
964931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
965932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
966933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
967934 MX35_PAD_FEC_RDATA2__GPIO3_20
968935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
969936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
970937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
971938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
972939 MX35_PAD_FEC_TDATA2__GPIO3_21
973940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
974941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
975942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
976943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
977944 MX35_PAD_FEC_RDATA3__GPIO3_22
978945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
979946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
980947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
981948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
982949 MX35_PAD_FEC_TDATA3__GPIO3_23
983950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
984951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
deleted file mode 100644
index b96fa4c3174..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
+++ /dev/null
@@ -1,787 +0,0 @@
1* Freescale IMX51 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx51-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HVE (1 << 13)
16PAD_CTL_HYS (1 << 8)
17PAD_CTL_PKE (1 << 7)
18PAD_CTL_PUE (1 << 6)
19PAD_CTL_PUS_100K_DOWN (0 << 4)
20PAD_CTL_PUS_47K_UP (1 << 4)
21PAD_CTL_PUS_100K_UP (2 << 4)
22PAD_CTL_PUS_22K_UP (3 << 4)
23PAD_CTL_ODE (1 << 3)
24PAD_CTL_DSE_LOW (0 << 1)
25PAD_CTL_DSE_MED (1 << 1)
26PAD_CTL_DSE_HIGH (2 << 1)
27PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0)
30
31See below for available PIN_FUNC_ID for imx51:
32MX51_PAD_EIM_D16__AUD4_RXFS 0
33MX51_PAD_EIM_D16__AUD5_TXD 1
34MX51_PAD_EIM_D16__EIM_D16 2
35MX51_PAD_EIM_D16__GPIO2_0 3
36MX51_PAD_EIM_D16__I2C1_SDA 4
37MX51_PAD_EIM_D16__UART2_CTS 5
38MX51_PAD_EIM_D16__USBH2_DATA0 6
39MX51_PAD_EIM_D17__AUD5_RXD 7
40MX51_PAD_EIM_D17__EIM_D17 8
41MX51_PAD_EIM_D17__GPIO2_1 9
42MX51_PAD_EIM_D17__UART2_RXD 10
43MX51_PAD_EIM_D17__UART3_CTS 11
44MX51_PAD_EIM_D17__USBH2_DATA1 12
45MX51_PAD_EIM_D18__AUD5_TXC 13
46MX51_PAD_EIM_D18__EIM_D18 14
47MX51_PAD_EIM_D18__GPIO2_2 15
48MX51_PAD_EIM_D18__UART2_TXD 16
49MX51_PAD_EIM_D18__UART3_RTS 17
50MX51_PAD_EIM_D18__USBH2_DATA2 18
51MX51_PAD_EIM_D19__AUD4_RXC 19
52MX51_PAD_EIM_D19__AUD5_TXFS 20
53MX51_PAD_EIM_D19__EIM_D19 21
54MX51_PAD_EIM_D19__GPIO2_3 22
55MX51_PAD_EIM_D19__I2C1_SCL 23
56MX51_PAD_EIM_D19__UART2_RTS 24
57MX51_PAD_EIM_D19__USBH2_DATA3 25
58MX51_PAD_EIM_D20__AUD4_TXD 26
59MX51_PAD_EIM_D20__EIM_D20 27
60MX51_PAD_EIM_D20__GPIO2_4 28
61MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
62MX51_PAD_EIM_D20__USBH2_DATA4 30
63MX51_PAD_EIM_D21__AUD4_RXD 31
64MX51_PAD_EIM_D21__EIM_D21 32
65MX51_PAD_EIM_D21__GPIO2_5 33
66MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
67MX51_PAD_EIM_D21__USBH2_DATA5 35
68MX51_PAD_EIM_D22__AUD4_TXC 36
69MX51_PAD_EIM_D22__EIM_D22 37
70MX51_PAD_EIM_D22__GPIO2_6 38
71MX51_PAD_EIM_D22__USBH2_DATA6 39
72MX51_PAD_EIM_D23__AUD4_TXFS 40
73MX51_PAD_EIM_D23__EIM_D23 41
74MX51_PAD_EIM_D23__GPIO2_7 42
75MX51_PAD_EIM_D23__SPDIF_OUT1 43
76MX51_PAD_EIM_D23__USBH2_DATA7 44
77MX51_PAD_EIM_D24__AUD6_RXFS 45
78MX51_PAD_EIM_D24__EIM_D24 46
79MX51_PAD_EIM_D24__GPIO2_8 47
80MX51_PAD_EIM_D24__I2C2_SDA 48
81MX51_PAD_EIM_D24__UART3_CTS 49
82MX51_PAD_EIM_D24__USBOTG_DATA0 50
83MX51_PAD_EIM_D25__EIM_D25 51
84MX51_PAD_EIM_D25__KEY_COL6 52
85MX51_PAD_EIM_D25__UART2_CTS 53
86MX51_PAD_EIM_D25__UART3_RXD 54
87MX51_PAD_EIM_D25__USBOTG_DATA1 55
88MX51_PAD_EIM_D26__EIM_D26 56
89MX51_PAD_EIM_D26__KEY_COL7 57
90MX51_PAD_EIM_D26__UART2_RTS 58
91MX51_PAD_EIM_D26__UART3_TXD 59
92MX51_PAD_EIM_D26__USBOTG_DATA2 60
93MX51_PAD_EIM_D27__AUD6_RXC 61
94MX51_PAD_EIM_D27__EIM_D27 62
95MX51_PAD_EIM_D27__GPIO2_9 63
96MX51_PAD_EIM_D27__I2C2_SCL 64
97MX51_PAD_EIM_D27__UART3_RTS 65
98MX51_PAD_EIM_D27__USBOTG_DATA3 66
99MX51_PAD_EIM_D28__AUD6_TXD 67
100MX51_PAD_EIM_D28__EIM_D28 68
101MX51_PAD_EIM_D28__KEY_ROW4 69
102MX51_PAD_EIM_D28__USBOTG_DATA4 70
103MX51_PAD_EIM_D29__AUD6_RXD 71
104MX51_PAD_EIM_D29__EIM_D29 72
105MX51_PAD_EIM_D29__KEY_ROW5 73
106MX51_PAD_EIM_D29__USBOTG_DATA5 74
107MX51_PAD_EIM_D30__AUD6_TXC 75
108MX51_PAD_EIM_D30__EIM_D30 76
109MX51_PAD_EIM_D30__KEY_ROW6 77
110MX51_PAD_EIM_D30__USBOTG_DATA6 78
111MX51_PAD_EIM_D31__AUD6_TXFS 79
112MX51_PAD_EIM_D31__EIM_D31 80
113MX51_PAD_EIM_D31__KEY_ROW7 81
114MX51_PAD_EIM_D31__USBOTG_DATA7 82
115MX51_PAD_EIM_A16__EIM_A16 83
116MX51_PAD_EIM_A16__GPIO2_10 84
117MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
118MX51_PAD_EIM_A17__EIM_A17 86
119MX51_PAD_EIM_A17__GPIO2_11 87
120MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
121MX51_PAD_EIM_A18__BOOT_LPB0 89
122MX51_PAD_EIM_A18__EIM_A18 90
123MX51_PAD_EIM_A18__GPIO2_12 91
124MX51_PAD_EIM_A19__BOOT_LPB1 92
125MX51_PAD_EIM_A19__EIM_A19 93
126MX51_PAD_EIM_A19__GPIO2_13 94
127MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
128MX51_PAD_EIM_A20__EIM_A20 96
129MX51_PAD_EIM_A20__GPIO2_14 97
130MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
131MX51_PAD_EIM_A21__EIM_A21 99
132MX51_PAD_EIM_A21__GPIO2_15 100
133MX51_PAD_EIM_A22__EIM_A22 101
134MX51_PAD_EIM_A22__GPIO2_16 102
135MX51_PAD_EIM_A23__BOOT_HPN_EN 103
136MX51_PAD_EIM_A23__EIM_A23 104
137MX51_PAD_EIM_A23__GPIO2_17 105
138MX51_PAD_EIM_A24__EIM_A24 106
139MX51_PAD_EIM_A24__GPIO2_18 107
140MX51_PAD_EIM_A24__USBH2_CLK 108
141MX51_PAD_EIM_A25__DISP1_PIN4 109
142MX51_PAD_EIM_A25__EIM_A25 110
143MX51_PAD_EIM_A25__GPIO2_19 111
144MX51_PAD_EIM_A25__USBH2_DIR 112
145MX51_PAD_EIM_A26__CSI1_DATA_EN 113
146MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
147MX51_PAD_EIM_A26__EIM_A26 115
148MX51_PAD_EIM_A26__GPIO2_20 116
149MX51_PAD_EIM_A26__USBH2_STP 117
150MX51_PAD_EIM_A27__CSI2_DATA_EN 118
151MX51_PAD_EIM_A27__DISP1_PIN1 119
152MX51_PAD_EIM_A27__EIM_A27 120
153MX51_PAD_EIM_A27__GPIO2_21 121
154MX51_PAD_EIM_A27__USBH2_NXT 122
155MX51_PAD_EIM_EB0__EIM_EB0 123
156MX51_PAD_EIM_EB1__EIM_EB1 124
157MX51_PAD_EIM_EB2__AUD5_RXFS 125
158MX51_PAD_EIM_EB2__CSI1_D2 126
159MX51_PAD_EIM_EB2__EIM_EB2 127
160MX51_PAD_EIM_EB2__FEC_MDIO 128
161MX51_PAD_EIM_EB2__GPIO2_22 129
162MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
163MX51_PAD_EIM_EB3__AUD5_RXC 131
164MX51_PAD_EIM_EB3__CSI1_D3 132
165MX51_PAD_EIM_EB3__EIM_EB3 133
166MX51_PAD_EIM_EB3__FEC_RDATA1 134
167MX51_PAD_EIM_EB3__GPIO2_23 135
168MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
169MX51_PAD_EIM_OE__EIM_OE 137
170MX51_PAD_EIM_OE__GPIO2_24 138
171MX51_PAD_EIM_CS0__EIM_CS0 139
172MX51_PAD_EIM_CS0__GPIO2_25 140
173MX51_PAD_EIM_CS1__EIM_CS1 141
174MX51_PAD_EIM_CS1__GPIO2_26 142
175MX51_PAD_EIM_CS2__AUD5_TXD 143
176MX51_PAD_EIM_CS2__CSI1_D4 144
177MX51_PAD_EIM_CS2__EIM_CS2 145
178MX51_PAD_EIM_CS2__FEC_RDATA2 146
179MX51_PAD_EIM_CS2__GPIO2_27 147
180MX51_PAD_EIM_CS2__USBOTG_STP 148
181MX51_PAD_EIM_CS3__AUD5_RXD 149
182MX51_PAD_EIM_CS3__CSI1_D5 150
183MX51_PAD_EIM_CS3__EIM_CS3 151
184MX51_PAD_EIM_CS3__FEC_RDATA3 152
185MX51_PAD_EIM_CS3__GPIO2_28 153
186MX51_PAD_EIM_CS3__USBOTG_NXT 154
187MX51_PAD_EIM_CS4__AUD5_TXC 155
188MX51_PAD_EIM_CS4__CSI1_D6 156
189MX51_PAD_EIM_CS4__EIM_CS4 157
190MX51_PAD_EIM_CS4__FEC_RX_ER 158
191MX51_PAD_EIM_CS4__GPIO2_29 159
192MX51_PAD_EIM_CS4__USBOTG_CLK 160
193MX51_PAD_EIM_CS5__AUD5_TXFS 161
194MX51_PAD_EIM_CS5__CSI1_D7 162
195MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
196MX51_PAD_EIM_CS5__EIM_CS5 164
197MX51_PAD_EIM_CS5__FEC_CRS 165
198MX51_PAD_EIM_CS5__GPIO2_30 166
199MX51_PAD_EIM_CS5__USBOTG_DIR 167
200MX51_PAD_EIM_DTACK__EIM_DTACK 168
201MX51_PAD_EIM_DTACK__GPIO2_31 169
202MX51_PAD_EIM_LBA__EIM_LBA 170
203MX51_PAD_EIM_LBA__GPIO3_1 171
204MX51_PAD_EIM_CRE__EIM_CRE 172
205MX51_PAD_EIM_CRE__GPIO3_2 173
206MX51_PAD_DRAM_CS1__DRAM_CS1 174
207MX51_PAD_NANDF_WE_B__GPIO3_3 175
208MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
209MX51_PAD_NANDF_WE_B__PATA_DIOW 177
210MX51_PAD_NANDF_WE_B__SD3_DATA0 178
211MX51_PAD_NANDF_RE_B__GPIO3_4 179
212MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
213MX51_PAD_NANDF_RE_B__PATA_DIOR 181
214MX51_PAD_NANDF_RE_B__SD3_DATA1 182
215MX51_PAD_NANDF_ALE__GPIO3_5 183
216MX51_PAD_NANDF_ALE__NANDF_ALE 184
217MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
218MX51_PAD_NANDF_CLE__GPIO3_6 186
219MX51_PAD_NANDF_CLE__NANDF_CLE 187
220MX51_PAD_NANDF_CLE__PATA_RESET_B 188
221MX51_PAD_NANDF_WP_B__GPIO3_7 189
222MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
223MX51_PAD_NANDF_WP_B__PATA_DMACK 191
224MX51_PAD_NANDF_WP_B__SD3_DATA2 192
225MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
226MX51_PAD_NANDF_RB0__GPIO3_8 194
227MX51_PAD_NANDF_RB0__NANDF_RB0 195
228MX51_PAD_NANDF_RB0__PATA_DMARQ 196
229MX51_PAD_NANDF_RB0__SD3_DATA3 197
230MX51_PAD_NANDF_RB1__CSPI_MOSI 198
231MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
232MX51_PAD_NANDF_RB1__GPIO3_9 200
233MX51_PAD_NANDF_RB1__NANDF_RB1 201
234MX51_PAD_NANDF_RB1__PATA_IORDY 202
235MX51_PAD_NANDF_RB1__SD4_CMD 203
236MX51_PAD_NANDF_RB2__DISP2_WAIT 204
237MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
238MX51_PAD_NANDF_RB2__FEC_COL 206
239MX51_PAD_NANDF_RB2__GPIO3_10 207
240MX51_PAD_NANDF_RB2__NANDF_RB2 208
241MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
242MX51_PAD_NANDF_RB2__USBH3_NXT 210
243MX51_PAD_NANDF_RB3__DISP1_WAIT 211
244MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
245MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
246MX51_PAD_NANDF_RB3__GPIO3_11 214
247MX51_PAD_NANDF_RB3__NANDF_RB3 215
248MX51_PAD_NANDF_RB3__USBH3_CLK 216
249MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
250MX51_PAD_GPIO_NAND__GPIO_NAND 218
251MX51_PAD_GPIO_NAND__PATA_INTRQ 219
252MX51_PAD_NANDF_CS0__GPIO3_16 220
253MX51_PAD_NANDF_CS0__NANDF_CS0 221
254MX51_PAD_NANDF_CS1__GPIO3_17 222
255MX51_PAD_NANDF_CS1__NANDF_CS1 223
256MX51_PAD_NANDF_CS2__CSPI_SCLK 224
257MX51_PAD_NANDF_CS2__FEC_TX_ER 225
258MX51_PAD_NANDF_CS2__GPIO3_18 226
259MX51_PAD_NANDF_CS2__NANDF_CS2 227
260MX51_PAD_NANDF_CS2__PATA_CS_0 228
261MX51_PAD_NANDF_CS2__SD4_CLK 229
262MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
263MX51_PAD_NANDF_CS3__FEC_MDC 231
264MX51_PAD_NANDF_CS3__GPIO3_19 232
265MX51_PAD_NANDF_CS3__NANDF_CS3 233
266MX51_PAD_NANDF_CS3__PATA_CS_1 234
267MX51_PAD_NANDF_CS3__SD4_DAT0 235
268MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
269MX51_PAD_NANDF_CS4__FEC_TDATA1 237
270MX51_PAD_NANDF_CS4__GPIO3_20 238
271MX51_PAD_NANDF_CS4__NANDF_CS4 239
272MX51_PAD_NANDF_CS4__PATA_DA_0 240
273MX51_PAD_NANDF_CS4__SD4_DAT1 241
274MX51_PAD_NANDF_CS4__USBH3_STP 242
275MX51_PAD_NANDF_CS5__FEC_TDATA2 243
276MX51_PAD_NANDF_CS5__GPIO3_21 244
277MX51_PAD_NANDF_CS5__NANDF_CS5 245
278MX51_PAD_NANDF_CS5__PATA_DA_1 246
279MX51_PAD_NANDF_CS5__SD4_DAT2 247
280MX51_PAD_NANDF_CS5__USBH3_DIR 248
281MX51_PAD_NANDF_CS6__CSPI_SS3 249
282MX51_PAD_NANDF_CS6__FEC_TDATA3 250
283MX51_PAD_NANDF_CS6__GPIO3_22 251
284MX51_PAD_NANDF_CS6__NANDF_CS6 252
285MX51_PAD_NANDF_CS6__PATA_DA_2 253
286MX51_PAD_NANDF_CS6__SD4_DAT3 254
287MX51_PAD_NANDF_CS7__FEC_TX_EN 255
288MX51_PAD_NANDF_CS7__GPIO3_23 256
289MX51_PAD_NANDF_CS7__NANDF_CS7 257
290MX51_PAD_NANDF_CS7__SD3_CLK 258
291MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
292MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
293MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
294MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
295MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
296MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
297MX51_PAD_NANDF_D15__GPIO3_25 265
298MX51_PAD_NANDF_D15__NANDF_D15 266
299MX51_PAD_NANDF_D15__PATA_DATA15 267
300MX51_PAD_NANDF_D15__SD3_DAT7 268
301MX51_PAD_NANDF_D14__ECSPI2_SS3 269
302MX51_PAD_NANDF_D14__GPIO3_26 270
303MX51_PAD_NANDF_D14__NANDF_D14 271
304MX51_PAD_NANDF_D14__PATA_DATA14 272
305MX51_PAD_NANDF_D14__SD3_DAT6 273
306MX51_PAD_NANDF_D13__ECSPI2_SS2 274
307MX51_PAD_NANDF_D13__GPIO3_27 275
308MX51_PAD_NANDF_D13__NANDF_D13 276
309MX51_PAD_NANDF_D13__PATA_DATA13 277
310MX51_PAD_NANDF_D13__SD3_DAT5 278
311MX51_PAD_NANDF_D12__ECSPI2_SS1 279
312MX51_PAD_NANDF_D12__GPIO3_28 280
313MX51_PAD_NANDF_D12__NANDF_D12 281
314MX51_PAD_NANDF_D12__PATA_DATA12 282
315MX51_PAD_NANDF_D12__SD3_DAT4 283
316MX51_PAD_NANDF_D11__FEC_RX_DV 284
317MX51_PAD_NANDF_D11__GPIO3_29 285
318MX51_PAD_NANDF_D11__NANDF_D11 286
319MX51_PAD_NANDF_D11__PATA_DATA11 287
320MX51_PAD_NANDF_D11__SD3_DATA3 288
321MX51_PAD_NANDF_D10__GPIO3_30 289
322MX51_PAD_NANDF_D10__NANDF_D10 290
323MX51_PAD_NANDF_D10__PATA_DATA10 291
324MX51_PAD_NANDF_D10__SD3_DATA2 292
325MX51_PAD_NANDF_D9__FEC_RDATA0 293
326MX51_PAD_NANDF_D9__GPIO3_31 294
327MX51_PAD_NANDF_D9__NANDF_D9 295
328MX51_PAD_NANDF_D9__PATA_DATA9 296
329MX51_PAD_NANDF_D9__SD3_DATA1 297
330MX51_PAD_NANDF_D8__FEC_TDATA0 298
331MX51_PAD_NANDF_D8__GPIO4_0 299
332MX51_PAD_NANDF_D8__NANDF_D8 300
333MX51_PAD_NANDF_D8__PATA_DATA8 301
334MX51_PAD_NANDF_D8__SD3_DATA0 302
335MX51_PAD_NANDF_D7__GPIO4_1 303
336MX51_PAD_NANDF_D7__NANDF_D7 304
337MX51_PAD_NANDF_D7__PATA_DATA7 305
338MX51_PAD_NANDF_D7__USBH3_DATA0 306
339MX51_PAD_NANDF_D6__GPIO4_2 307
340MX51_PAD_NANDF_D6__NANDF_D6 308
341MX51_PAD_NANDF_D6__PATA_DATA6 309
342MX51_PAD_NANDF_D6__SD4_LCTL 310
343MX51_PAD_NANDF_D6__USBH3_DATA1 311
344MX51_PAD_NANDF_D5__GPIO4_3 312
345MX51_PAD_NANDF_D5__NANDF_D5 313
346MX51_PAD_NANDF_D5__PATA_DATA5 314
347MX51_PAD_NANDF_D5__SD4_WP 315
348MX51_PAD_NANDF_D5__USBH3_DATA2 316
349MX51_PAD_NANDF_D4__GPIO4_4 317
350MX51_PAD_NANDF_D4__NANDF_D4 318
351MX51_PAD_NANDF_D4__PATA_DATA4 319
352MX51_PAD_NANDF_D4__SD4_CD 320
353MX51_PAD_NANDF_D4__USBH3_DATA3 321
354MX51_PAD_NANDF_D3__GPIO4_5 322
355MX51_PAD_NANDF_D3__NANDF_D3 323
356MX51_PAD_NANDF_D3__PATA_DATA3 324
357MX51_PAD_NANDF_D3__SD4_DAT4 325
358MX51_PAD_NANDF_D3__USBH3_DATA4 326
359MX51_PAD_NANDF_D2__GPIO4_6 327
360MX51_PAD_NANDF_D2__NANDF_D2 328
361MX51_PAD_NANDF_D2__PATA_DATA2 329
362MX51_PAD_NANDF_D2__SD4_DAT5 330
363MX51_PAD_NANDF_D2__USBH3_DATA5 331
364MX51_PAD_NANDF_D1__GPIO4_7 332
365MX51_PAD_NANDF_D1__NANDF_D1 333
366MX51_PAD_NANDF_D1__PATA_DATA1 334
367MX51_PAD_NANDF_D1__SD4_DAT6 335
368MX51_PAD_NANDF_D1__USBH3_DATA6 336
369MX51_PAD_NANDF_D0__GPIO4_8 337
370MX51_PAD_NANDF_D0__NANDF_D0 338
371MX51_PAD_NANDF_D0__PATA_DATA0 339
372MX51_PAD_NANDF_D0__SD4_DAT7 340
373MX51_PAD_NANDF_D0__USBH3_DATA7 341
374MX51_PAD_CSI1_D8__CSI1_D8 342
375MX51_PAD_CSI1_D8__GPIO3_12 343
376MX51_PAD_CSI1_D9__CSI1_D9 344
377MX51_PAD_CSI1_D9__GPIO3_13 345
378MX51_PAD_CSI1_D10__CSI1_D10 346
379MX51_PAD_CSI1_D11__CSI1_D11 347
380MX51_PAD_CSI1_D12__CSI1_D12 348
381MX51_PAD_CSI1_D13__CSI1_D13 349
382MX51_PAD_CSI1_D14__CSI1_D14 350
383MX51_PAD_CSI1_D15__CSI1_D15 351
384MX51_PAD_CSI1_D16__CSI1_D16 352
385MX51_PAD_CSI1_D17__CSI1_D17 353
386MX51_PAD_CSI1_D18__CSI1_D18 354
387MX51_PAD_CSI1_D19__CSI1_D19 355
388MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
389MX51_PAD_CSI1_VSYNC__GPIO3_14 357
390MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
391MX51_PAD_CSI1_HSYNC__GPIO3_15 359
392MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
393MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
394MX51_PAD_CSI2_D12__CSI2_D12 362
395MX51_PAD_CSI2_D12__GPIO4_9 363
396MX51_PAD_CSI2_D13__CSI2_D13 364
397MX51_PAD_CSI2_D13__GPIO4_10 365
398MX51_PAD_CSI2_D14__CSI2_D14 366
399MX51_PAD_CSI2_D15__CSI2_D15 367
400MX51_PAD_CSI2_D16__CSI2_D16 368
401MX51_PAD_CSI2_D17__CSI2_D17 369
402MX51_PAD_CSI2_D18__CSI2_D18 370
403MX51_PAD_CSI2_D18__GPIO4_11 371
404MX51_PAD_CSI2_D19__CSI2_D19 372
405MX51_PAD_CSI2_D19__GPIO4_12 373
406MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
407MX51_PAD_CSI2_VSYNC__GPIO4_13 375
408MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
409MX51_PAD_CSI2_HSYNC__GPIO4_14 377
410MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
411MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
412MX51_PAD_I2C1_CLK__GPIO4_16 380
413MX51_PAD_I2C1_CLK__I2C1_CLK 381
414MX51_PAD_I2C1_DAT__GPIO4_17 382
415MX51_PAD_I2C1_DAT__I2C1_DAT 383
416MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
417MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
418MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
419MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
420MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
421MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
422MX51_PAD_AUD3_BB_CK__GPIO4_20 390
423MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
424MX51_PAD_AUD3_BB_FS__GPIO4_21 392
425MX51_PAD_AUD3_BB_FS__UART3_TXD 393
426MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
427MX51_PAD_CSPI1_MOSI__GPIO4_22 395
428MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
429MX51_PAD_CSPI1_MISO__AUD4_RXD 397
430MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
431MX51_PAD_CSPI1_MISO__GPIO4_23 399
432MX51_PAD_CSPI1_SS0__AUD4_TXC 400
433MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
434MX51_PAD_CSPI1_SS0__GPIO4_24 402
435MX51_PAD_CSPI1_SS1__AUD4_TXD 403
436MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
437MX51_PAD_CSPI1_SS1__GPIO4_25 405
438MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
439MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
440MX51_PAD_CSPI1_RDY__GPIO4_26 408
441MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
442MX51_PAD_CSPI1_SCLK__GPIO4_27 410
443MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
444MX51_PAD_UART1_RXD__GPIO4_28 412
445MX51_PAD_UART1_RXD__UART1_RXD 413
446MX51_PAD_UART1_TXD__GPIO4_29 414
447MX51_PAD_UART1_TXD__PWM2_PWMO 415
448MX51_PAD_UART1_TXD__UART1_TXD 416
449MX51_PAD_UART1_RTS__GPIO4_30 417
450MX51_PAD_UART1_RTS__UART1_RTS 418
451MX51_PAD_UART1_CTS__GPIO4_31 419
452MX51_PAD_UART1_CTS__UART1_CTS 420
453MX51_PAD_UART2_RXD__FIRI_TXD 421
454MX51_PAD_UART2_RXD__GPIO1_20 422
455MX51_PAD_UART2_RXD__UART2_RXD 423
456MX51_PAD_UART2_TXD__FIRI_RXD 424
457MX51_PAD_UART2_TXD__GPIO1_21 425
458MX51_PAD_UART2_TXD__UART2_TXD 426
459MX51_PAD_UART3_RXD__CSI1_D0 427
460MX51_PAD_UART3_RXD__GPIO1_22 428
461MX51_PAD_UART3_RXD__UART1_DTR 429
462MX51_PAD_UART3_RXD__UART3_RXD 430
463MX51_PAD_UART3_TXD__CSI1_D1 431
464MX51_PAD_UART3_TXD__GPIO1_23 432
465MX51_PAD_UART3_TXD__UART1_DSR 433
466MX51_PAD_UART3_TXD__UART3_TXD 434
467MX51_PAD_OWIRE_LINE__GPIO1_24 435
468MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
469MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
470MX51_PAD_KEY_ROW0__KEY_ROW0 438
471MX51_PAD_KEY_ROW1__KEY_ROW1 439
472MX51_PAD_KEY_ROW2__KEY_ROW2 440
473MX51_PAD_KEY_ROW3__KEY_ROW3 441
474MX51_PAD_KEY_COL0__KEY_COL0 442
475MX51_PAD_KEY_COL0__PLL1_BYP 443
476MX51_PAD_KEY_COL1__KEY_COL1 444
477MX51_PAD_KEY_COL1__PLL2_BYP 445
478MX51_PAD_KEY_COL2__KEY_COL2 446
479MX51_PAD_KEY_COL2__PLL3_BYP 447
480MX51_PAD_KEY_COL3__KEY_COL3 448
481MX51_PAD_KEY_COL4__I2C2_SCL 449
482MX51_PAD_KEY_COL4__KEY_COL4 450
483MX51_PAD_KEY_COL4__SPDIF_OUT1 451
484MX51_PAD_KEY_COL4__UART1_RI 452
485MX51_PAD_KEY_COL4__UART3_RTS 453
486MX51_PAD_KEY_COL5__I2C2_SDA 454
487MX51_PAD_KEY_COL5__KEY_COL5 455
488MX51_PAD_KEY_COL5__UART1_DCD 456
489MX51_PAD_KEY_COL5__UART3_CTS 457
490MX51_PAD_USBH1_CLK__CSPI_SCLK 458
491MX51_PAD_USBH1_CLK__GPIO1_25 459
492MX51_PAD_USBH1_CLK__I2C2_SCL 460
493MX51_PAD_USBH1_CLK__USBH1_CLK 461
494MX51_PAD_USBH1_DIR__CSPI_MOSI 462
495MX51_PAD_USBH1_DIR__GPIO1_26 463
496MX51_PAD_USBH1_DIR__I2C2_SDA 464
497MX51_PAD_USBH1_DIR__USBH1_DIR 465
498MX51_PAD_USBH1_STP__CSPI_RDY 466
499MX51_PAD_USBH1_STP__GPIO1_27 467
500MX51_PAD_USBH1_STP__UART3_RXD 468
501MX51_PAD_USBH1_STP__USBH1_STP 469
502MX51_PAD_USBH1_NXT__CSPI_MISO 470
503MX51_PAD_USBH1_NXT__GPIO1_28 471
504MX51_PAD_USBH1_NXT__UART3_TXD 472
505MX51_PAD_USBH1_NXT__USBH1_NXT 473
506MX51_PAD_USBH1_DATA0__GPIO1_11 474
507MX51_PAD_USBH1_DATA0__UART2_CTS 475
508MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
509MX51_PAD_USBH1_DATA1__GPIO1_12 477
510MX51_PAD_USBH1_DATA1__UART2_RXD 478
511MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
512MX51_PAD_USBH1_DATA2__GPIO1_13 480
513MX51_PAD_USBH1_DATA2__UART2_TXD 481
514MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
515MX51_PAD_USBH1_DATA3__GPIO1_14 483
516MX51_PAD_USBH1_DATA3__UART2_RTS 484
517MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
518MX51_PAD_USBH1_DATA4__CSPI_SS0 486
519MX51_PAD_USBH1_DATA4__GPIO1_15 487
520MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
521MX51_PAD_USBH1_DATA5__CSPI_SS1 489
522MX51_PAD_USBH1_DATA5__GPIO1_16 490
523MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
524MX51_PAD_USBH1_DATA6__CSPI_SS3 492
525MX51_PAD_USBH1_DATA6__GPIO1_17 493
526MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
527MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
528MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
529MX51_PAD_USBH1_DATA7__GPIO1_18 497
530MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
531MX51_PAD_DI1_PIN11__DI1_PIN11 499
532MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
533MX51_PAD_DI1_PIN11__GPIO3_0 501
534MX51_PAD_DI1_PIN12__DI1_PIN12 502
535MX51_PAD_DI1_PIN12__GPIO3_1 503
536MX51_PAD_DI1_PIN13__DI1_PIN13 504
537MX51_PAD_DI1_PIN13__GPIO3_2 505
538MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
539MX51_PAD_DI1_D0_CS__GPIO3_3 507
540MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
541MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
542MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
543MX51_PAD_DI1_D1_CS__GPIO3_4 511
544MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
545MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
546MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
547MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
548MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
549MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
550MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
551MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
552MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
553MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
554MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
555MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
556MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
557MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
558MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
559MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
560MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
561MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
562MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
563MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
564MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
565MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
566MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
567MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
568MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
569MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
570MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
571MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
572MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
573MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
574MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
575MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
576MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
577MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
578MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
579MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
580MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
581MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
582MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
583MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
584MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
585MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
586MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
587MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
588MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
589MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
590MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
591MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
592MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
593MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
594MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
595MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
596MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
597MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
598MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
599MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
600MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
601MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
602MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
603MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
604MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
605MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
606MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
607MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
608MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
609MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
610MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
611MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
612MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
613MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
614MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
615MX51_PAD_DI1_PIN3__DI1_PIN3 583
616MX51_PAD_DI1_PIN2__DI1_PIN2 584
617MX51_PAD_DI_GP2__DISP1_SER_CLK 585
618MX51_PAD_DI_GP2__DISP2_WAIT 586
619MX51_PAD_DI_GP3__CSI1_DATA_EN 587
620MX51_PAD_DI_GP3__DISP1_SER_DIO 588
621MX51_PAD_DI_GP3__FEC_TX_ER 589
622MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
623MX51_PAD_DI2_PIN4__DI2_PIN4 591
624MX51_PAD_DI2_PIN4__FEC_CRS 592
625MX51_PAD_DI2_PIN2__DI2_PIN2 593
626MX51_PAD_DI2_PIN2__FEC_MDC 594
627MX51_PAD_DI2_PIN3__DI2_PIN3 595
628MX51_PAD_DI2_PIN3__FEC_MDIO 596
629MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
630MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
631MX51_PAD_DI_GP4__DI2_PIN15 599
632MX51_PAD_DI_GP4__DISP1_SER_DIN 600
633MX51_PAD_DI_GP4__DISP2_PIN1 601
634MX51_PAD_DI_GP4__FEC_RDATA2 602
635MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
636MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
637MX51_PAD_DISP2_DAT0__KEY_COL6 605
638MX51_PAD_DISP2_DAT0__UART3_RXD 606
639MX51_PAD_DISP2_DAT0__USBH3_CLK 607
640MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
641MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
642MX51_PAD_DISP2_DAT1__KEY_COL7 610
643MX51_PAD_DISP2_DAT1__UART3_TXD 611
644MX51_PAD_DISP2_DAT1__USBH3_DIR 612
645MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
646MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
647MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
648MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
649MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
650MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
651MX51_PAD_DISP2_DAT6__GPIO1_19 619
652MX51_PAD_DISP2_DAT6__KEY_ROW4 620
653MX51_PAD_DISP2_DAT6__USBH3_STP 621
654MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
655MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
656MX51_PAD_DISP2_DAT7__GPIO1_29 624
657MX51_PAD_DISP2_DAT7__KEY_ROW5 625
658MX51_PAD_DISP2_DAT7__USBH3_NXT 626
659MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
660MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
661MX51_PAD_DISP2_DAT8__GPIO1_30 629
662MX51_PAD_DISP2_DAT8__KEY_ROW6 630
663MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
664MX51_PAD_DISP2_DAT9__AUD6_RXC 632
665MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
666MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
667MX51_PAD_DISP2_DAT9__GPIO1_31 635
668MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
669MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
670MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
671MX51_PAD_DISP2_DAT10__FEC_COL 639
672MX51_PAD_DISP2_DAT10__KEY_ROW7 640
673MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
674MX51_PAD_DISP2_DAT11__AUD6_TXD 642
675MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
676MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
677MX51_PAD_DISP2_DAT11__GPIO1_10 645
678MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
679MX51_PAD_DISP2_DAT12__AUD6_RXD 647
680MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
681MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
682MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
683MX51_PAD_DISP2_DAT13__AUD6_TXC 651
684MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
685MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
686MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
687MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
688MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
689MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
690MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
691MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
692MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
693MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
694MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
695MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
696MX51_PAD_SD1_CMD__AUD5_RXFS 664
697MX51_PAD_SD1_CMD__CSPI_MOSI 665
698MX51_PAD_SD1_CMD__SD1_CMD 666
699MX51_PAD_SD1_CLK__AUD5_RXC 667
700MX51_PAD_SD1_CLK__CSPI_SCLK 668
701MX51_PAD_SD1_CLK__SD1_CLK 669
702MX51_PAD_SD1_DATA0__AUD5_TXD 670
703MX51_PAD_SD1_DATA0__CSPI_MISO 671
704MX51_PAD_SD1_DATA0__SD1_DATA0 672
705MX51_PAD_EIM_DA0__EIM_DA0 673
706MX51_PAD_EIM_DA1__EIM_DA1 674
707MX51_PAD_EIM_DA2__EIM_DA2 675
708MX51_PAD_EIM_DA3__EIM_DA3 676
709MX51_PAD_SD1_DATA1__AUD5_RXD 677
710MX51_PAD_SD1_DATA1__SD1_DATA1 678
711MX51_PAD_EIM_DA4__EIM_DA4 679
712MX51_PAD_EIM_DA5__EIM_DA5 680
713MX51_PAD_EIM_DA6__EIM_DA6 681
714MX51_PAD_EIM_DA7__EIM_DA7 682
715MX51_PAD_SD1_DATA2__AUD5_TXC 683
716MX51_PAD_SD1_DATA2__SD1_DATA2 684
717MX51_PAD_EIM_DA10__EIM_DA10 685
718MX51_PAD_EIM_DA11__EIM_DA11 686
719MX51_PAD_EIM_DA8__EIM_DA8 687
720MX51_PAD_EIM_DA9__EIM_DA9 688
721MX51_PAD_SD1_DATA3__AUD5_TXFS 689
722MX51_PAD_SD1_DATA3__CSPI_SS1 690
723MX51_PAD_SD1_DATA3__SD1_DATA3 691
724MX51_PAD_GPIO1_0__CSPI_SS2 692
725MX51_PAD_GPIO1_0__GPIO1_0 693
726MX51_PAD_GPIO1_0__SD1_CD 694
727MX51_PAD_GPIO1_1__CSPI_MISO 695
728MX51_PAD_GPIO1_1__GPIO1_1 696
729MX51_PAD_GPIO1_1__SD1_WP 697
730MX51_PAD_EIM_DA12__EIM_DA12 698
731MX51_PAD_EIM_DA13__EIM_DA13 699
732MX51_PAD_EIM_DA14__EIM_DA14 700
733MX51_PAD_EIM_DA15__EIM_DA15 701
734MX51_PAD_SD2_CMD__CSPI_MOSI 702
735MX51_PAD_SD2_CMD__I2C1_SCL 703
736MX51_PAD_SD2_CMD__SD2_CMD 704
737MX51_PAD_SD2_CLK__CSPI_SCLK 705
738MX51_PAD_SD2_CLK__I2C1_SDA 706
739MX51_PAD_SD2_CLK__SD2_CLK 707
740MX51_PAD_SD2_DATA0__CSPI_MISO 708
741MX51_PAD_SD2_DATA0__SD1_DAT4 709
742MX51_PAD_SD2_DATA0__SD2_DATA0 710
743MX51_PAD_SD2_DATA1__SD1_DAT5 711
744MX51_PAD_SD2_DATA1__SD2_DATA1 712
745MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
746MX51_PAD_SD2_DATA2__SD1_DAT6 714
747MX51_PAD_SD2_DATA2__SD2_DATA2 715
748MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
749MX51_PAD_SD2_DATA3__CSPI_SS2 717
750MX51_PAD_SD2_DATA3__SD1_DAT7 718
751MX51_PAD_SD2_DATA3__SD2_DATA3 719
752MX51_PAD_GPIO1_2__CCM_OUT_2 720
753MX51_PAD_GPIO1_2__GPIO1_2 721
754MX51_PAD_GPIO1_2__I2C2_SCL 722
755MX51_PAD_GPIO1_2__PLL1_BYP 723
756MX51_PAD_GPIO1_2__PWM1_PWMO 724
757MX51_PAD_GPIO1_3__GPIO1_3 725
758MX51_PAD_GPIO1_3__I2C2_SDA 726
759MX51_PAD_GPIO1_3__PLL2_BYP 727
760MX51_PAD_GPIO1_3__PWM2_PWMO 728
761MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
762MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
763MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
764MX51_PAD_GPIO1_4__EIM_RDY 732
765MX51_PAD_GPIO1_4__GPIO1_4 733
766MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
767MX51_PAD_GPIO1_5__CSI2_MCLK 735
768MX51_PAD_GPIO1_5__DISP2_PIN16 736
769MX51_PAD_GPIO1_5__GPIO1_5 737
770MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
771MX51_PAD_GPIO1_6__DISP2_PIN17 739
772MX51_PAD_GPIO1_6__GPIO1_6 740
773MX51_PAD_GPIO1_6__REF_EN_B 741
774MX51_PAD_GPIO1_7__CCM_OUT_0 742
775MX51_PAD_GPIO1_7__GPIO1_7 743
776MX51_PAD_GPIO1_7__SD2_WP 744
777MX51_PAD_GPIO1_7__SPDIF_OUT1 745
778MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
779MX51_PAD_GPIO1_8__GPIO1_8 747
780MX51_PAD_GPIO1_8__SD2_CD 748
781MX51_PAD_GPIO1_8__USBH3_PWR 749
782MX51_PAD_GPIO1_9__CCM_OUT_1 750
783MX51_PAD_GPIO1_9__DISP2_D1_CS 751
784MX51_PAD_GPIO1_9__DISP2_SER_CS 752
785MX51_PAD_GPIO1_9__GPIO1_9 753
786MX51_PAD_GPIO1_9__SD2_LCTL 754
787MX51_PAD_GPIO1_9__USBH3_OC 755
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
deleted file mode 100644
index ca85ca432ef..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
+++ /dev/null
@@ -1,1202 +0,0 @@
1* Freescale IMX53 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx53-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HVE (1 << 13)
16PAD_CTL_HYS (1 << 8)
17PAD_CTL_PKE (1 << 7)
18PAD_CTL_PUE (1 << 6)
19PAD_CTL_PUS_100K_DOWN (0 << 4)
20PAD_CTL_PUS_47K_UP (1 << 4)
21PAD_CTL_PUS_100K_UP (2 << 4)
22PAD_CTL_PUS_22K_UP (3 << 4)
23PAD_CTL_ODE (1 << 3)
24PAD_CTL_DSE_LOW (0 << 1)
25PAD_CTL_DSE_MED (1 << 1)
26PAD_CTL_DSE_HIGH (2 << 1)
27PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0)
30
31See below for available PIN_FUNC_ID for imx53:
32MX53_PAD_GPIO_19__KPP_COL_5 0
33MX53_PAD_GPIO_19__GPIO4_5 1
34MX53_PAD_GPIO_19__CCM_CLKO 2
35MX53_PAD_GPIO_19__SPDIF_OUT1 3
36MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4
37MX53_PAD_GPIO_19__ECSPI1_RDY 5
38MX53_PAD_GPIO_19__FEC_TDATA_3 6
39MX53_PAD_GPIO_19__SRC_INT_BOOT 7
40MX53_PAD_KEY_COL0__KPP_COL_0 8
41MX53_PAD_KEY_COL0__GPIO4_6 9
42MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10
43MX53_PAD_KEY_COL0__UART4_TXD_MUX 11
44MX53_PAD_KEY_COL0__ECSPI1_SCLK 12
45MX53_PAD_KEY_COL0__FEC_RDATA_3 13
46MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14
47MX53_PAD_KEY_ROW0__KPP_ROW_0 15
48MX53_PAD_KEY_ROW0__GPIO4_7 16
49MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17
50MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18
51MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19
52MX53_PAD_KEY_ROW0__FEC_TX_ER 20
53MX53_PAD_KEY_COL1__KPP_COL_1 21
54MX53_PAD_KEY_COL1__GPIO4_8 22
55MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23
56MX53_PAD_KEY_COL1__UART5_TXD_MUX 24
57MX53_PAD_KEY_COL1__ECSPI1_MISO 25
58MX53_PAD_KEY_COL1__FEC_RX_CLK 26
59MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27
60MX53_PAD_KEY_ROW1__KPP_ROW_1 28
61MX53_PAD_KEY_ROW1__GPIO4_9 29
62MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30
63MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31
64MX53_PAD_KEY_ROW1__ECSPI1_SS0 32
65MX53_PAD_KEY_ROW1__FEC_COL 33
66MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34
67MX53_PAD_KEY_COL2__KPP_COL_2 35
68MX53_PAD_KEY_COL2__GPIO4_10 36
69MX53_PAD_KEY_COL2__CAN1_TXCAN 37
70MX53_PAD_KEY_COL2__FEC_MDIO 38
71MX53_PAD_KEY_COL2__ECSPI1_SS1 39
72MX53_PAD_KEY_COL2__FEC_RDATA_2 40
73MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41
74MX53_PAD_KEY_ROW2__KPP_ROW_2 42
75MX53_PAD_KEY_ROW2__GPIO4_11 43
76MX53_PAD_KEY_ROW2__CAN1_RXCAN 44
77MX53_PAD_KEY_ROW2__FEC_MDC 45
78MX53_PAD_KEY_ROW2__ECSPI1_SS2 46
79MX53_PAD_KEY_ROW2__FEC_TDATA_2 47
80MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48
81MX53_PAD_KEY_COL3__KPP_COL_3 49
82MX53_PAD_KEY_COL3__GPIO4_12 50
83MX53_PAD_KEY_COL3__USBOH3_H2_DP 51
84MX53_PAD_KEY_COL3__SPDIF_IN1 52
85MX53_PAD_KEY_COL3__I2C2_SCL 53
86MX53_PAD_KEY_COL3__ECSPI1_SS3 54
87MX53_PAD_KEY_COL3__FEC_CRS 55
88MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56
89MX53_PAD_KEY_ROW3__KPP_ROW_3 57
90MX53_PAD_KEY_ROW3__GPIO4_13 58
91MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59
92MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60
93MX53_PAD_KEY_ROW3__I2C2_SDA 61
94MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62
95MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63
96MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64
97MX53_PAD_KEY_COL4__KPP_COL_4 65
98MX53_PAD_KEY_COL4__GPIO4_14 66
99MX53_PAD_KEY_COL4__CAN2_TXCAN 67
100MX53_PAD_KEY_COL4__IPU_SISG_4 68
101MX53_PAD_KEY_COL4__UART5_RTS 69
102MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70
103MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71
104MX53_PAD_KEY_ROW4__KPP_ROW_4 72
105MX53_PAD_KEY_ROW4__GPIO4_15 73
106MX53_PAD_KEY_ROW4__CAN2_RXCAN 74
107MX53_PAD_KEY_ROW4__IPU_SISG_5 75
108MX53_PAD_KEY_ROW4__UART5_CTS 76
109MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77
110MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78
111MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79
112MX53_PAD_DI0_DISP_CLK__GPIO4_16 80
113MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81
114MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82
115MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83
116MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84
117MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85
118MX53_PAD_DI0_PIN15__GPIO4_17 86
119MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87
120MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88
121MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89
122MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90
123MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91
124MX53_PAD_DI0_PIN2__GPIO4_18 92
125MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93
126MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94
127MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95
128MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96
129MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97
130MX53_PAD_DI0_PIN3__GPIO4_19 98
131MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99
132MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100
133MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101
134MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102
135MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103
136MX53_PAD_DI0_PIN4__GPIO4_20 104
137MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105
138MX53_PAD_DI0_PIN4__ESDHC1_WP 106
139MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107
140MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108
141MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109
142MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110
143MX53_PAD_DISP0_DAT0__GPIO4_21 111
144MX53_PAD_DISP0_DAT0__CSPI_SCLK 112
145MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113
146MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114
147MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115
148MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116
149MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117
150MX53_PAD_DISP0_DAT1__GPIO4_22 118
151MX53_PAD_DISP0_DAT1__CSPI_MOSI 119
152MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120
153MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121
154MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122
155MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123
156MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124
157MX53_PAD_DISP0_DAT2__GPIO4_23 125
158MX53_PAD_DISP0_DAT2__CSPI_MISO 126
159MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127
160MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128
161MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129
162MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130
163MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131
164MX53_PAD_DISP0_DAT3__GPIO4_24 132
165MX53_PAD_DISP0_DAT3__CSPI_SS0 133
166MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134
167MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135
168MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136
169MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137
170MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138
171MX53_PAD_DISP0_DAT4__GPIO4_25 139
172MX53_PAD_DISP0_DAT4__CSPI_SS1 140
173MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141
174MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142
175MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143
176MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144
177MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145
178MX53_PAD_DISP0_DAT5__GPIO4_26 146
179MX53_PAD_DISP0_DAT5__CSPI_SS2 147
180MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148
181MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149
182MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150
183MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151
184MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152
185MX53_PAD_DISP0_DAT6__GPIO4_27 153
186MX53_PAD_DISP0_DAT6__CSPI_SS3 154
187MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155
188MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156
189MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157
190MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158
191MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159
192MX53_PAD_DISP0_DAT7__GPIO4_28 160
193MX53_PAD_DISP0_DAT7__CSPI_RDY 161
194MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162
195MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163
196MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164
197MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165
198MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166
199MX53_PAD_DISP0_DAT8__GPIO4_29 167
200MX53_PAD_DISP0_DAT8__PWM1_PWMO 168
201MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169
202MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170
203MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171
204MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172
205MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173
206MX53_PAD_DISP0_DAT9__GPIO4_30 174
207MX53_PAD_DISP0_DAT9__PWM2_PWMO 175
208MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176
209MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177
210MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178
211MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179
212MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180
213MX53_PAD_DISP0_DAT10__GPIO4_31 181
214MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182
215MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183
216MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184
217MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185
218MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186
219MX53_PAD_DISP0_DAT11__GPIO5_5 187
220MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188
221MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189
222MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190
223MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191
224MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192
225MX53_PAD_DISP0_DAT12__GPIO5_6 193
226MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194
227MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195
228MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196
229MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197
230MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198
231MX53_PAD_DISP0_DAT13__GPIO5_7 199
232MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200
233MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201
234MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202
235MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203
236MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204
237MX53_PAD_DISP0_DAT14__GPIO5_8 205
238MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206
239MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207
240MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208
241MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209
242MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210
243MX53_PAD_DISP0_DAT15__GPIO5_9 211
244MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212
245MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213
246MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214
247MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215
248MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216
249MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217
250MX53_PAD_DISP0_DAT16__GPIO5_10 218
251MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219
252MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220
253MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221
254MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222
255MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223
256MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224
257MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225
258MX53_PAD_DISP0_DAT17__GPIO5_11 226
259MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227
260MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228
261MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229
262MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230
263MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231
264MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232
265MX53_PAD_DISP0_DAT18__GPIO5_12 233
266MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234
267MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235
268MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236
269MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237
270MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238
271MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239
272MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240
273MX53_PAD_DISP0_DAT19__GPIO5_13 241
274MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242
275MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243
276MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244
277MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245
278MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246
279MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247
280MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248
281MX53_PAD_DISP0_DAT20__GPIO5_14 249
282MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250
283MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251
284MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252
285MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253
286MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254
287MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255
288MX53_PAD_DISP0_DAT21__GPIO5_15 256
289MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257
290MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258
291MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259
292MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260
293MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261
294MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262
295MX53_PAD_DISP0_DAT22__GPIO5_16 263
296MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264
297MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265
298MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266
299MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267
300MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268
301MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269
302MX53_PAD_DISP0_DAT23__GPIO5_17 270
303MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271
304MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272
305MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273
306MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274
307MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275
308MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276
309MX53_PAD_CSI0_PIXCLK__GPIO5_18 277
310MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278
311MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279
312MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280
313MX53_PAD_CSI0_MCLK__GPIO5_19 281
314MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282
315MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283
316MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284
317MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285
318MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286
319MX53_PAD_CSI0_DATA_EN__GPIO5_20 287
320MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288
321MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289
322MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290
323MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291
324MX53_PAD_CSI0_VSYNC__GPIO5_21 292
325MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293
326MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294
327MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295
328MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296
329MX53_PAD_CSI0_DAT4__GPIO5_22 297
330MX53_PAD_CSI0_DAT4__KPP_COL_5 298
331MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299
332MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300
333MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301
334MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302
335MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303
336MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304
337MX53_PAD_CSI0_DAT5__GPIO5_23 305
338MX53_PAD_CSI0_DAT5__KPP_ROW_5 306
339MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307
340MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308
341MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309
342MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310
343MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311
344MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312
345MX53_PAD_CSI0_DAT6__GPIO5_24 313
346MX53_PAD_CSI0_DAT6__KPP_COL_6 314
347MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315
348MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316
349MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317
350MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318
351MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319
352MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320
353MX53_PAD_CSI0_DAT7__GPIO5_25 321
354MX53_PAD_CSI0_DAT7__KPP_ROW_6 322
355MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323
356MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324
357MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325
358MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326
359MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327
360MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328
361MX53_PAD_CSI0_DAT8__GPIO5_26 329
362MX53_PAD_CSI0_DAT8__KPP_COL_7 330
363MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331
364MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332
365MX53_PAD_CSI0_DAT8__I2C1_SDA 333
366MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334
367MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335
368MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336
369MX53_PAD_CSI0_DAT9__GPIO5_27 337
370MX53_PAD_CSI0_DAT9__KPP_ROW_7 338
371MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339
372MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340
373MX53_PAD_CSI0_DAT9__I2C1_SCL 341
374MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342
375MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343
376MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344
377MX53_PAD_CSI0_DAT10__GPIO5_28 345
378MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346
379MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347
380MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348
381MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349
382MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350
383MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351
384MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352
385MX53_PAD_CSI0_DAT11__GPIO5_29 353
386MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354
387MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355
388MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356
389MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357
390MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358
391MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359
392MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360
393MX53_PAD_CSI0_DAT12__GPIO5_30 361
394MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362
395MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363
396MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364
397MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365
398MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366
399MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367
400MX53_PAD_CSI0_DAT13__GPIO5_31 368
401MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369
402MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370
403MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371
404MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372
405MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373
406MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374
407MX53_PAD_CSI0_DAT14__GPIO6_0 375
408MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376
409MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377
410MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378
411MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379
412MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380
413MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381
414MX53_PAD_CSI0_DAT15__GPIO6_1 382
415MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383
416MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384
417MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385
418MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386
419MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387
420MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388
421MX53_PAD_CSI0_DAT16__GPIO6_2 389
422MX53_PAD_CSI0_DAT16__UART4_RTS 390
423MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391
424MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392
425MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393
426MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394
427MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395
428MX53_PAD_CSI0_DAT17__GPIO6_3 396
429MX53_PAD_CSI0_DAT17__UART4_CTS 397
430MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398
431MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399
432MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400
433MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401
434MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402
435MX53_PAD_CSI0_DAT18__GPIO6_4 403
436MX53_PAD_CSI0_DAT18__UART5_RTS 404
437MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405
438MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406
439MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407
440MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408
441MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409
442MX53_PAD_CSI0_DAT19__GPIO6_5 410
443MX53_PAD_CSI0_DAT19__UART5_CTS 411
444MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412
445MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413
446MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414
447MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415
448MX53_PAD_EIM_A25__EMI_WEIM_A_25 416
449MX53_PAD_EIM_A25__GPIO5_2 417
450MX53_PAD_EIM_A25__ECSPI2_RDY 418
451MX53_PAD_EIM_A25__IPU_DI1_PIN12 419
452MX53_PAD_EIM_A25__CSPI_SS1 420
453MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421
454MX53_PAD_EIM_A25__USBPHY1_BISTOK 422
455MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423
456MX53_PAD_EIM_EB2__GPIO2_30 424
457MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425
458MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426
459MX53_PAD_EIM_EB2__ECSPI1_SS0 427
460MX53_PAD_EIM_EB2__I2C2_SCL 428
461MX53_PAD_EIM_D16__EMI_WEIM_D_16 429
462MX53_PAD_EIM_D16__GPIO3_16 430
463MX53_PAD_EIM_D16__IPU_DI0_PIN5 431
464MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432
465MX53_PAD_EIM_D16__ECSPI1_SCLK 433
466MX53_PAD_EIM_D16__I2C2_SDA 434
467MX53_PAD_EIM_D17__EMI_WEIM_D_17 435
468MX53_PAD_EIM_D17__GPIO3_17 436
469MX53_PAD_EIM_D17__IPU_DI0_PIN6 437
470MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438
471MX53_PAD_EIM_D17__ECSPI1_MISO 439
472MX53_PAD_EIM_D17__I2C3_SCL 440
473MX53_PAD_EIM_D18__EMI_WEIM_D_18 441
474MX53_PAD_EIM_D18__GPIO3_18 442
475MX53_PAD_EIM_D18__IPU_DI0_PIN7 443
476MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444
477MX53_PAD_EIM_D18__ECSPI1_MOSI 445
478MX53_PAD_EIM_D18__I2C3_SDA 446
479MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447
480MX53_PAD_EIM_D19__EMI_WEIM_D_19 448
481MX53_PAD_EIM_D19__GPIO3_19 449
482MX53_PAD_EIM_D19__IPU_DI0_PIN8 450
483MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451
484MX53_PAD_EIM_D19__ECSPI1_SS1 452
485MX53_PAD_EIM_D19__EPIT1_EPITO 453
486MX53_PAD_EIM_D19__UART1_CTS 454
487MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455
488MX53_PAD_EIM_D20__EMI_WEIM_D_20 456
489MX53_PAD_EIM_D20__GPIO3_20 457
490MX53_PAD_EIM_D20__IPU_DI0_PIN16 458
491MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459
492MX53_PAD_EIM_D20__CSPI_SS0 460
493MX53_PAD_EIM_D20__EPIT2_EPITO 461
494MX53_PAD_EIM_D20__UART1_RTS 462
495MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463
496MX53_PAD_EIM_D21__EMI_WEIM_D_21 464
497MX53_PAD_EIM_D21__GPIO3_21 465
498MX53_PAD_EIM_D21__IPU_DI0_PIN17 466
499MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467
500MX53_PAD_EIM_D21__CSPI_SCLK 468
501MX53_PAD_EIM_D21__I2C1_SCL 469
502MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470
503MX53_PAD_EIM_D22__EMI_WEIM_D_22 471
504MX53_PAD_EIM_D22__GPIO3_22 472
505MX53_PAD_EIM_D22__IPU_DI0_PIN1 473
506MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474
507MX53_PAD_EIM_D22__CSPI_MISO 475
508MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476
509MX53_PAD_EIM_D23__EMI_WEIM_D_23 477
510MX53_PAD_EIM_D23__GPIO3_23 478
511MX53_PAD_EIM_D23__UART3_CTS 479
512MX53_PAD_EIM_D23__UART1_DCD 480
513MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481
514MX53_PAD_EIM_D23__IPU_DI1_PIN2 482
515MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483
516MX53_PAD_EIM_D23__IPU_DI1_PIN14 484
517MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485
518MX53_PAD_EIM_EB3__GPIO2_31 486
519MX53_PAD_EIM_EB3__UART3_RTS 487
520MX53_PAD_EIM_EB3__UART1_RI 488
521MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489
522MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490
523MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491
524MX53_PAD_EIM_D24__EMI_WEIM_D_24 492
525MX53_PAD_EIM_D24__GPIO3_24 493
526MX53_PAD_EIM_D24__UART3_TXD_MUX 494
527MX53_PAD_EIM_D24__ECSPI1_SS2 495
528MX53_PAD_EIM_D24__CSPI_SS2 496
529MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497
530MX53_PAD_EIM_D24__ECSPI2_SS2 498
531MX53_PAD_EIM_D24__UART1_DTR 499
532MX53_PAD_EIM_D25__EMI_WEIM_D_25 500
533MX53_PAD_EIM_D25__GPIO3_25 501
534MX53_PAD_EIM_D25__UART3_RXD_MUX 502
535MX53_PAD_EIM_D25__ECSPI1_SS3 503
536MX53_PAD_EIM_D25__CSPI_SS3 504
537MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505
538MX53_PAD_EIM_D25__ECSPI2_SS3 506
539MX53_PAD_EIM_D25__UART1_DSR 507
540MX53_PAD_EIM_D26__EMI_WEIM_D_26 508
541MX53_PAD_EIM_D26__GPIO3_26 509
542MX53_PAD_EIM_D26__UART2_TXD_MUX 510
543MX53_PAD_EIM_D26__FIRI_RXD 511
544MX53_PAD_EIM_D26__IPU_CSI0_D_1 512
545MX53_PAD_EIM_D26__IPU_DI1_PIN11 513
546MX53_PAD_EIM_D26__IPU_SISG_2 514
547MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515
548MX53_PAD_EIM_D27__EMI_WEIM_D_27 516
549MX53_PAD_EIM_D27__GPIO3_27 517
550MX53_PAD_EIM_D27__UART2_RXD_MUX 518
551MX53_PAD_EIM_D27__FIRI_TXD 519
552MX53_PAD_EIM_D27__IPU_CSI0_D_0 520
553MX53_PAD_EIM_D27__IPU_DI1_PIN13 521
554MX53_PAD_EIM_D27__IPU_SISG_3 522
555MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523
556MX53_PAD_EIM_D28__EMI_WEIM_D_28 524
557MX53_PAD_EIM_D28__GPIO3_28 525
558MX53_PAD_EIM_D28__UART2_CTS 526
559MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527
560MX53_PAD_EIM_D28__CSPI_MOSI 528
561MX53_PAD_EIM_D28__I2C1_SDA 529
562MX53_PAD_EIM_D28__IPU_EXT_TRIG 530
563MX53_PAD_EIM_D28__IPU_DI0_PIN13 531
564MX53_PAD_EIM_D29__EMI_WEIM_D_29 532
565MX53_PAD_EIM_D29__GPIO3_29 533
566MX53_PAD_EIM_D29__UART2_RTS 534
567MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535
568MX53_PAD_EIM_D29__CSPI_SS0 536
569MX53_PAD_EIM_D29__IPU_DI1_PIN15 537
570MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538
571MX53_PAD_EIM_D29__IPU_DI0_PIN14 539
572MX53_PAD_EIM_D30__EMI_WEIM_D_30 540
573MX53_PAD_EIM_D30__GPIO3_30 541
574MX53_PAD_EIM_D30__UART3_CTS 542
575MX53_PAD_EIM_D30__IPU_CSI0_D_3 543
576MX53_PAD_EIM_D30__IPU_DI0_PIN11 544
577MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545
578MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546
579MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547
580MX53_PAD_EIM_D31__EMI_WEIM_D_31 548
581MX53_PAD_EIM_D31__GPIO3_31 549
582MX53_PAD_EIM_D31__UART3_RTS 550
583MX53_PAD_EIM_D31__IPU_CSI0_D_2 551
584MX53_PAD_EIM_D31__IPU_DI0_PIN12 552
585MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553
586MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554
587MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555
588MX53_PAD_EIM_A24__EMI_WEIM_A_24 556
589MX53_PAD_EIM_A24__GPIO5_4 557
590MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558
591MX53_PAD_EIM_A24__IPU_CSI1_D_19 559
592MX53_PAD_EIM_A24__IPU_SISG_2 560
593MX53_PAD_EIM_A24__USBPHY2_BVALID 561
594MX53_PAD_EIM_A23__EMI_WEIM_A_23 562
595MX53_PAD_EIM_A23__GPIO6_6 563
596MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564
597MX53_PAD_EIM_A23__IPU_CSI1_D_18 565
598MX53_PAD_EIM_A23__IPU_SISG_3 566
599MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567
600MX53_PAD_EIM_A22__EMI_WEIM_A_22 568
601MX53_PAD_EIM_A22__GPIO2_16 569
602MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570
603MX53_PAD_EIM_A22__IPU_CSI1_D_17 571
604MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572
605MX53_PAD_EIM_A21__EMI_WEIM_A_21 573
606MX53_PAD_EIM_A21__GPIO2_17 574
607MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575
608MX53_PAD_EIM_A21__IPU_CSI1_D_16 576
609MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577
610MX53_PAD_EIM_A20__EMI_WEIM_A_20 578
611MX53_PAD_EIM_A20__GPIO2_18 579
612MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580
613MX53_PAD_EIM_A20__IPU_CSI1_D_15 581
614MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582
615MX53_PAD_EIM_A19__EMI_WEIM_A_19 583
616MX53_PAD_EIM_A19__GPIO2_19 584
617MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585
618MX53_PAD_EIM_A19__IPU_CSI1_D_14 586
619MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587
620MX53_PAD_EIM_A18__EMI_WEIM_A_18 588
621MX53_PAD_EIM_A18__GPIO2_20 589
622MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590
623MX53_PAD_EIM_A18__IPU_CSI1_D_13 591
624MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592
625MX53_PAD_EIM_A17__EMI_WEIM_A_17 593
626MX53_PAD_EIM_A17__GPIO2_21 594
627MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595
628MX53_PAD_EIM_A17__IPU_CSI1_D_12 596
629MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597
630MX53_PAD_EIM_A16__EMI_WEIM_A_16 598
631MX53_PAD_EIM_A16__GPIO2_22 599
632MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600
633MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601
634MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602
635MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603
636MX53_PAD_EIM_CS0__GPIO2_23 604
637MX53_PAD_EIM_CS0__ECSPI2_SCLK 605
638MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606
639MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607
640MX53_PAD_EIM_CS1__GPIO2_24 608
641MX53_PAD_EIM_CS1__ECSPI2_MOSI 609
642MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610
643MX53_PAD_EIM_OE__EMI_WEIM_OE 611
644MX53_PAD_EIM_OE__GPIO2_25 612
645MX53_PAD_EIM_OE__ECSPI2_MISO 613
646MX53_PAD_EIM_OE__IPU_DI1_PIN7 614
647MX53_PAD_EIM_OE__USBPHY2_IDDIG 615
648MX53_PAD_EIM_RW__EMI_WEIM_RW 616
649MX53_PAD_EIM_RW__GPIO2_26 617
650MX53_PAD_EIM_RW__ECSPI2_SS0 618
651MX53_PAD_EIM_RW__IPU_DI1_PIN8 619
652MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620
653MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621
654MX53_PAD_EIM_LBA__GPIO2_27 622
655MX53_PAD_EIM_LBA__ECSPI2_SS1 623
656MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624
657MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625
658MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626
659MX53_PAD_EIM_EB0__GPIO2_28 627
660MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628
661MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629
662MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630
663MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631
664MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632
665MX53_PAD_EIM_EB1__GPIO2_29 633
666MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634
667MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635
668MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636
669MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637
670MX53_PAD_EIM_DA0__GPIO3_0 638
671MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639
672MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640
673MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641
674MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642
675MX53_PAD_EIM_DA1__GPIO3_1 643
676MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644
677MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645
678MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646
679MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647
680MX53_PAD_EIM_DA2__GPIO3_2 648
681MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649
682MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650
683MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651
684MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652
685MX53_PAD_EIM_DA3__GPIO3_3 653
686MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654
687MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655
688MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656
689MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657
690MX53_PAD_EIM_DA4__GPIO3_4 658
691MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659
692MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660
693MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661
694MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662
695MX53_PAD_EIM_DA5__GPIO3_5 663
696MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664
697MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665
698MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666
699MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667
700MX53_PAD_EIM_DA6__GPIO3_6 668
701MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669
702MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670
703MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671
704MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672
705MX53_PAD_EIM_DA7__GPIO3_7 673
706MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674
707MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675
708MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676
709MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677
710MX53_PAD_EIM_DA8__GPIO3_8 678
711MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679
712MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680
713MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681
714MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682
715MX53_PAD_EIM_DA9__GPIO3_9 683
716MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684
717MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685
718MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686
719MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687
720MX53_PAD_EIM_DA10__GPIO3_10 688
721MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689
722MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690
723MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691
724MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692
725MX53_PAD_EIM_DA11__GPIO3_11 693
726MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694
727MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695
728MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696
729MX53_PAD_EIM_DA12__GPIO3_12 697
730MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698
731MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699
732MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700
733MX53_PAD_EIM_DA13__GPIO3_13 701
734MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702
735MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703
736MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704
737MX53_PAD_EIM_DA14__GPIO3_14 705
738MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706
739MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707
740MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708
741MX53_PAD_EIM_DA15__GPIO3_15 709
742MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710
743MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711
744MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712
745MX53_PAD_NANDF_WE_B__GPIO6_12 713
746MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714
747MX53_PAD_NANDF_RE_B__GPIO6_13 715
748MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716
749MX53_PAD_EIM_WAIT__GPIO5_0 717
750MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718
751MX53_PAD_LVDS1_TX3_P__GPIO6_22 719
752MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720
753MX53_PAD_LVDS1_TX2_P__GPIO6_24 721
754MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722
755MX53_PAD_LVDS1_CLK_P__GPIO6_26 723
756MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724
757MX53_PAD_LVDS1_TX1_P__GPIO6_28 725
758MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726
759MX53_PAD_LVDS1_TX0_P__GPIO6_30 727
760MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728
761MX53_PAD_LVDS0_TX3_P__GPIO7_22 729
762MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730
763MX53_PAD_LVDS0_CLK_P__GPIO7_24 731
764MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732
765MX53_PAD_LVDS0_TX2_P__GPIO7_26 733
766MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734
767MX53_PAD_LVDS0_TX1_P__GPIO7_28 735
768MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736
769MX53_PAD_LVDS0_TX0_P__GPIO7_30 737
770MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738
771MX53_PAD_GPIO_10__GPIO4_0 739
772MX53_PAD_GPIO_10__OSC32k_32K_OUT 740
773MX53_PAD_GPIO_11__GPIO4_1 741
774MX53_PAD_GPIO_12__GPIO4_2 742
775MX53_PAD_GPIO_13__GPIO4_3 743
776MX53_PAD_GPIO_14__GPIO4_4 744
777MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745
778MX53_PAD_NANDF_CLE__GPIO6_7 746
779MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747
780MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748
781MX53_PAD_NANDF_ALE__GPIO6_8 749
782MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750
783MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751
784MX53_PAD_NANDF_WP_B__GPIO6_9 752
785MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753
786MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754
787MX53_PAD_NANDF_RB0__GPIO6_10 755
788MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756
789MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757
790MX53_PAD_NANDF_CS0__GPIO6_11 758
791MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759
792MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760
793MX53_PAD_NANDF_CS1__GPIO6_14 761
794MX53_PAD_NANDF_CS1__MLB_MLBCLK 762
795MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763
796MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764
797MX53_PAD_NANDF_CS2__GPIO6_15 765
798MX53_PAD_NANDF_CS2__IPU_SISG_0 766
799MX53_PAD_NANDF_CS2__ESAI1_TX0 767
800MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768
801MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769
802MX53_PAD_NANDF_CS2__MLB_MLBSIG 770
803MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771
804MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772
805MX53_PAD_NANDF_CS3__GPIO6_16 773
806MX53_PAD_NANDF_CS3__IPU_SISG_1 774
807MX53_PAD_NANDF_CS3__ESAI1_TX1 775
808MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776
809MX53_PAD_NANDF_CS3__MLB_MLBDAT 777
810MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778
811MX53_PAD_FEC_MDIO__FEC_MDIO 779
812MX53_PAD_FEC_MDIO__GPIO1_22 780
813MX53_PAD_FEC_MDIO__ESAI1_SCKR 781
814MX53_PAD_FEC_MDIO__FEC_COL 782
815MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783
816MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784
817MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785
818MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786
819MX53_PAD_FEC_REF_CLK__GPIO1_23 787
820MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788
821MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789
822MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790
823MX53_PAD_FEC_RX_ER__FEC_RX_ER 791
824MX53_PAD_FEC_RX_ER__GPIO1_24 792
825MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793
826MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794
827MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795
828MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796
829MX53_PAD_FEC_CRS_DV__GPIO1_25 797
830MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798
831MX53_PAD_FEC_RXD1__FEC_RDATA_1 799
832MX53_PAD_FEC_RXD1__GPIO1_26 800
833MX53_PAD_FEC_RXD1__ESAI1_FST 801
834MX53_PAD_FEC_RXD1__MLB_MLBSIG 802
835MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803
836MX53_PAD_FEC_RXD0__FEC_RDATA_0 804
837MX53_PAD_FEC_RXD0__GPIO1_27 805
838MX53_PAD_FEC_RXD0__ESAI1_HCKT 806
839MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807
840MX53_PAD_FEC_TX_EN__FEC_TX_EN 808
841MX53_PAD_FEC_TX_EN__GPIO1_28 809
842MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810
843MX53_PAD_FEC_TXD1__FEC_TDATA_1 811
844MX53_PAD_FEC_TXD1__GPIO1_29 812
845MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813
846MX53_PAD_FEC_TXD1__MLB_MLBCLK 814
847MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815
848MX53_PAD_FEC_TXD0__FEC_TDATA_0 816
849MX53_PAD_FEC_TXD0__GPIO1_30 817
850MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818
851MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819
852MX53_PAD_FEC_MDC__FEC_MDC 820
853MX53_PAD_FEC_MDC__GPIO1_31 821
854MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822
855MX53_PAD_FEC_MDC__MLB_MLBDAT 823
856MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824
857MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825
858MX53_PAD_PATA_DIOW__PATA_DIOW 826
859MX53_PAD_PATA_DIOW__GPIO6_17 827
860MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828
861MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829
862MX53_PAD_PATA_DMACK__PATA_DMACK 830
863MX53_PAD_PATA_DMACK__GPIO6_18 831
864MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832
865MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833
866MX53_PAD_PATA_DMARQ__PATA_DMARQ 834
867MX53_PAD_PATA_DMARQ__GPIO7_0 835
868MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836
869MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837
870MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838
871MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839
872MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840
873MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841
874MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842
875MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843
876MX53_PAD_PATA_INTRQ__PATA_INTRQ 844
877MX53_PAD_PATA_INTRQ__GPIO7_2 845
878MX53_PAD_PATA_INTRQ__UART2_CTS 846
879MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847
880MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848
881MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849
882MX53_PAD_PATA_DIOR__PATA_DIOR 850
883MX53_PAD_PATA_DIOR__GPIO7_3 851
884MX53_PAD_PATA_DIOR__UART2_RTS 852
885MX53_PAD_PATA_DIOR__CAN1_RXCAN 853
886MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854
887MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855
888MX53_PAD_PATA_RESET_B__GPIO7_4 856
889MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857
890MX53_PAD_PATA_RESET_B__UART1_CTS 858
891MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859
892MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860
893MX53_PAD_PATA_IORDY__PATA_IORDY 861
894MX53_PAD_PATA_IORDY__GPIO7_5 862
895MX53_PAD_PATA_IORDY__ESDHC3_CLK 863
896MX53_PAD_PATA_IORDY__UART1_RTS 864
897MX53_PAD_PATA_IORDY__CAN2_RXCAN 865
898MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866
899MX53_PAD_PATA_DA_0__PATA_DA_0 867
900MX53_PAD_PATA_DA_0__GPIO7_6 868
901MX53_PAD_PATA_DA_0__ESDHC3_RST 869
902MX53_PAD_PATA_DA_0__OWIRE_LINE 870
903MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871
904MX53_PAD_PATA_DA_1__PATA_DA_1 872
905MX53_PAD_PATA_DA_1__GPIO7_7 873
906MX53_PAD_PATA_DA_1__ESDHC4_CMD 874
907MX53_PAD_PATA_DA_1__UART3_CTS 875
908MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876
909MX53_PAD_PATA_DA_2__PATA_DA_2 877
910MX53_PAD_PATA_DA_2__GPIO7_8 878
911MX53_PAD_PATA_DA_2__ESDHC4_CLK 879
912MX53_PAD_PATA_DA_2__UART3_RTS 880
913MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881
914MX53_PAD_PATA_CS_0__PATA_CS_0 882
915MX53_PAD_PATA_CS_0__GPIO7_9 883
916MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884
917MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885
918MX53_PAD_PATA_CS_1__PATA_CS_1 886
919MX53_PAD_PATA_CS_1__GPIO7_10 887
920MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888
921MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889
922MX53_PAD_PATA_DATA0__PATA_DATA_0 890
923MX53_PAD_PATA_DATA0__GPIO2_0 891
924MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892
925MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893
926MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894
927MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895
928MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896
929MX53_PAD_PATA_DATA1__PATA_DATA_1 897
930MX53_PAD_PATA_DATA1__GPIO2_1 898
931MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899
932MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900
933MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901
934MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902
935MX53_PAD_PATA_DATA2__PATA_DATA_2 903
936MX53_PAD_PATA_DATA2__GPIO2_2 904
937MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905
938MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906
939MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907
940MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908
941MX53_PAD_PATA_DATA3__PATA_DATA_3 909
942MX53_PAD_PATA_DATA3__GPIO2_3 910
943MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911
944MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912
945MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913
946MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914
947MX53_PAD_PATA_DATA4__PATA_DATA_4 915
948MX53_PAD_PATA_DATA4__GPIO2_4 916
949MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917
950MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918
951MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919
952MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920
953MX53_PAD_PATA_DATA5__PATA_DATA_5 921
954MX53_PAD_PATA_DATA5__GPIO2_5 922
955MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923
956MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924
957MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925
958MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926
959MX53_PAD_PATA_DATA6__PATA_DATA_6 927
960MX53_PAD_PATA_DATA6__GPIO2_6 928
961MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929
962MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930
963MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931
964MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932
965MX53_PAD_PATA_DATA7__PATA_DATA_7 933
966MX53_PAD_PATA_DATA7__GPIO2_7 934
967MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935
968MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936
969MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937
970MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938
971MX53_PAD_PATA_DATA8__PATA_DATA_8 939
972MX53_PAD_PATA_DATA8__GPIO2_8 940
973MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941
974MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942
975MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943
976MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944
977MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945
978MX53_PAD_PATA_DATA9__PATA_DATA_9 946
979MX53_PAD_PATA_DATA9__GPIO2_9 947
980MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948
981MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949
982MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950
983MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951
984MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952
985MX53_PAD_PATA_DATA10__PATA_DATA_10 953
986MX53_PAD_PATA_DATA10__GPIO2_10 954
987MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955
988MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956
989MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957
990MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958
991MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959
992MX53_PAD_PATA_DATA11__PATA_DATA_11 960
993MX53_PAD_PATA_DATA11__GPIO2_11 961
994MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962
995MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963
996MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964
997MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965
998MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966
999MX53_PAD_PATA_DATA12__PATA_DATA_12 967
1000MX53_PAD_PATA_DATA12__GPIO2_12 968
1001MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969
1002MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970
1003MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971
1004MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972
1005MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973
1006MX53_PAD_PATA_DATA13__PATA_DATA_13 974
1007MX53_PAD_PATA_DATA13__GPIO2_13 975
1008MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976
1009MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977
1010MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978
1011MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979
1012MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980
1013MX53_PAD_PATA_DATA14__PATA_DATA_14 981
1014MX53_PAD_PATA_DATA14__GPIO2_14 982
1015MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983
1016MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984
1017MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985
1018MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986
1019MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987
1020MX53_PAD_PATA_DATA15__PATA_DATA_15 988
1021MX53_PAD_PATA_DATA15__GPIO2_15 989
1022MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990
1023MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991
1024MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992
1025MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993
1026MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994
1027MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995
1028MX53_PAD_SD1_DATA0__GPIO1_16 996
1029MX53_PAD_SD1_DATA0__GPT_CAPIN1 997
1030MX53_PAD_SD1_DATA0__CSPI_MISO 998
1031MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999
1032MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000
1033MX53_PAD_SD1_DATA1__GPIO1_17 1001
1034MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002
1035MX53_PAD_SD1_DATA1__CSPI_SS0 1003
1036MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004
1037MX53_PAD_SD1_CMD__ESDHC1_CMD 1005
1038MX53_PAD_SD1_CMD__GPIO1_18 1006
1039MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007
1040MX53_PAD_SD1_CMD__CSPI_MOSI 1008
1041MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009
1042MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010
1043MX53_PAD_SD1_DATA2__GPIO1_19 1011
1044MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012
1045MX53_PAD_SD1_DATA2__PWM2_PWMO 1013
1046MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014
1047MX53_PAD_SD1_DATA2__CSPI_SS1 1015
1048MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016
1049MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017
1050MX53_PAD_SD1_CLK__ESDHC1_CLK 1018
1051MX53_PAD_SD1_CLK__GPIO1_20 1019
1052MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020
1053MX53_PAD_SD1_CLK__GPT_CLKIN 1021
1054MX53_PAD_SD1_CLK__CSPI_SCLK 1022
1055MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023
1056MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024
1057MX53_PAD_SD1_DATA3__GPIO1_21 1025
1058MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026
1059MX53_PAD_SD1_DATA3__PWM1_PWMO 1027
1060MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028
1061MX53_PAD_SD1_DATA3__CSPI_SS2 1029
1062MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030
1063MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031
1064MX53_PAD_SD2_CLK__ESDHC2_CLK 1032
1065MX53_PAD_SD2_CLK__GPIO1_10 1033
1066MX53_PAD_SD2_CLK__KPP_COL_5 1034
1067MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035
1068MX53_PAD_SD2_CLK__CSPI_SCLK 1036
1069MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037
1070MX53_PAD_SD2_CMD__ESDHC2_CMD 1038
1071MX53_PAD_SD2_CMD__GPIO1_11 1039
1072MX53_PAD_SD2_CMD__KPP_ROW_5 1040
1073MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041
1074MX53_PAD_SD2_CMD__CSPI_MOSI 1042
1075MX53_PAD_SD2_CMD__SCC_RANDOM 1043
1076MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044
1077MX53_PAD_SD2_DATA3__GPIO1_12 1045
1078MX53_PAD_SD2_DATA3__KPP_COL_6 1046
1079MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047
1080MX53_PAD_SD2_DATA3__CSPI_SS2 1048
1081MX53_PAD_SD2_DATA3__SJC_DONE 1049
1082MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050
1083MX53_PAD_SD2_DATA2__GPIO1_13 1051
1084MX53_PAD_SD2_DATA2__KPP_ROW_6 1052
1085MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053
1086MX53_PAD_SD2_DATA2__CSPI_SS1 1054
1087MX53_PAD_SD2_DATA2__SJC_FAIL 1055
1088MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056
1089MX53_PAD_SD2_DATA1__GPIO1_14 1057
1090MX53_PAD_SD2_DATA1__KPP_COL_7 1058
1091MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059
1092MX53_PAD_SD2_DATA1__CSPI_SS0 1060
1093MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061
1094MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062
1095MX53_PAD_SD2_DATA0__GPIO1_15 1063
1096MX53_PAD_SD2_DATA0__KPP_ROW_7 1064
1097MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065
1098MX53_PAD_SD2_DATA0__CSPI_MISO 1066
1099MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067
1100MX53_PAD_GPIO_0__CCM_CLKO 1068
1101MX53_PAD_GPIO_0__GPIO1_0 1069
1102MX53_PAD_GPIO_0__KPP_COL_5 1070
1103MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071
1104MX53_PAD_GPIO_0__EPIT1_EPITO 1072
1105MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073
1106MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074
1107MX53_PAD_GPIO_0__CSU_TD 1075
1108MX53_PAD_GPIO_1__ESAI1_SCKR 1076
1109MX53_PAD_GPIO_1__GPIO1_1 1077
1110MX53_PAD_GPIO_1__KPP_ROW_5 1078
1111MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079
1112MX53_PAD_GPIO_1__PWM2_PWMO 1080
1113MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081
1114MX53_PAD_GPIO_1__ESDHC1_CD 1082
1115MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083
1116MX53_PAD_GPIO_9__ESAI1_FSR 1084
1117MX53_PAD_GPIO_9__GPIO1_9 1085
1118MX53_PAD_GPIO_9__KPP_COL_6 1086
1119MX53_PAD_GPIO_9__CCM_REF_EN_B 1087
1120MX53_PAD_GPIO_9__PWM1_PWMO 1088
1121MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089
1122MX53_PAD_GPIO_9__ESDHC1_WP 1090
1123MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091
1124MX53_PAD_GPIO_3__ESAI1_HCKR 1092
1125MX53_PAD_GPIO_3__GPIO1_3 1093
1126MX53_PAD_GPIO_3__I2C3_SCL 1094
1127MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095
1128MX53_PAD_GPIO_3__CCM_CLKO2 1096
1129MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097
1130MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098
1131MX53_PAD_GPIO_3__MLB_MLBCLK 1099
1132MX53_PAD_GPIO_6__ESAI1_SCKT 1100
1133MX53_PAD_GPIO_6__GPIO1_6 1101
1134MX53_PAD_GPIO_6__I2C3_SDA 1102
1135MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103
1136MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104
1137MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105
1138MX53_PAD_GPIO_6__ESDHC2_LCTL 1106
1139MX53_PAD_GPIO_6__MLB_MLBSIG 1107
1140MX53_PAD_GPIO_2__ESAI1_FST 1108
1141MX53_PAD_GPIO_2__GPIO1_2 1109
1142MX53_PAD_GPIO_2__KPP_ROW_6 1110
1143MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111
1144MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112
1145MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113
1146MX53_PAD_GPIO_2__ESDHC2_WP 1114
1147MX53_PAD_GPIO_2__MLB_MLBDAT 1115
1148MX53_PAD_GPIO_4__ESAI1_HCKT 1116
1149MX53_PAD_GPIO_4__GPIO1_4 1117
1150MX53_PAD_GPIO_4__KPP_COL_7 1118
1151MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119
1152MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120
1153MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121
1154MX53_PAD_GPIO_4__ESDHC2_CD 1122
1155MX53_PAD_GPIO_4__SCC_SEC_STATE 1123
1156MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124
1157MX53_PAD_GPIO_5__GPIO1_5 1125
1158MX53_PAD_GPIO_5__KPP_ROW_7 1126
1159MX53_PAD_GPIO_5__CCM_CLKO 1127
1160MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128
1161MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129
1162MX53_PAD_GPIO_5__I2C3_SCL 1130
1163MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131
1164MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132
1165MX53_PAD_GPIO_7__GPIO1_7 1133
1166MX53_PAD_GPIO_7__EPIT1_EPITO 1134
1167MX53_PAD_GPIO_7__CAN1_TXCAN 1135
1168MX53_PAD_GPIO_7__UART2_TXD_MUX 1136
1169MX53_PAD_GPIO_7__FIRI_RXD 1137
1170MX53_PAD_GPIO_7__SPDIF_PLOCK 1138
1171MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139
1172MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140
1173MX53_PAD_GPIO_8__GPIO1_8 1141
1174MX53_PAD_GPIO_8__EPIT2_EPITO 1142
1175MX53_PAD_GPIO_8__CAN1_RXCAN 1143
1176MX53_PAD_GPIO_8__UART2_RXD_MUX 1144
1177MX53_PAD_GPIO_8__FIRI_TXD 1145
1178MX53_PAD_GPIO_8__SPDIF_SRCLK 1146
1179MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147
1180MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148
1181MX53_PAD_GPIO_16__GPIO7_11 1149
1182MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150
1183MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151
1184MX53_PAD_GPIO_16__SPDIF_IN1 1152
1185MX53_PAD_GPIO_16__I2C3_SDA 1153
1186MX53_PAD_GPIO_16__SJC_DE_B 1154
1187MX53_PAD_GPIO_17__ESAI1_TX0 1155
1188MX53_PAD_GPIO_17__GPIO7_12 1156
1189MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157
1190MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158
1191MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159
1192MX53_PAD_GPIO_17__SPDIF_OUT1 1160
1193MX53_PAD_GPIO_17__IPU_SNOOP2 1161
1194MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162
1195MX53_PAD_GPIO_18__ESAI1_TX1 1163
1196MX53_PAD_GPIO_18__GPIO7_13 1164
1197MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165
1198MX53_PAD_GPIO_18__OWIRE_LINE 1166
1199MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167
1200MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168
1201MX53_PAD_GPIO_18__ESDHC1_LCTL 1169
1202MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
deleted file mode 100644
index a4119f6422d..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+++ /dev/null
@@ -1,1630 +0,0 @@
1* Freescale IMX6Q IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6q-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HYS (1 << 16)
16PAD_CTL_PUS_100K_DOWN (0 << 14)
17PAD_CTL_PUS_47K_UP (1 << 14)
18PAD_CTL_PUS_100K_UP (2 << 14)
19PAD_CTL_PUS_22K_UP (3 << 14)
20PAD_CTL_PUE (1 << 13)
21PAD_CTL_PKE (1 << 12)
22PAD_CTL_ODE (1 << 11)
23PAD_CTL_SPEED_LOW (1 << 6)
24PAD_CTL_SPEED_MED (2 << 6)
25PAD_CTL_SPEED_HIGH (3 << 6)
26PAD_CTL_DSE_DISABLE (0 << 3)
27PAD_CTL_DSE_240ohm (1 << 3)
28PAD_CTL_DSE_120ohm (2 << 3)
29PAD_CTL_DSE_80ohm (3 << 3)
30PAD_CTL_DSE_60ohm (4 << 3)
31PAD_CTL_DSE_48ohm (5 << 3)
32PAD_CTL_DSE_40ohm (6 << 3)
33PAD_CTL_DSE_34ohm (7 << 3)
34PAD_CTL_SRE_FAST (1 << 0)
35PAD_CTL_SRE_SLOW (0 << 0)
36
37See below for available PIN_FUNC_ID for imx6q:
38MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
39MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
40MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
41MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
42MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
43MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
44MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
45MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
46MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
47MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
48MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
49MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
50MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
51MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
52MX6Q_PAD_SD2_DAT2__CCM_STOP 14
53MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
54MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
55MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
56MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
57MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
58MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
59MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
60MX6Q_PAD_SD2_DAT0__TESTO_2 22
61MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
62MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
63MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
64MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
65MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
66MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
67MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
68MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
69MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
70MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
71MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
72MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
73MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
74MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
75MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
76MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
77MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
78MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
79MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
80MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
81MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
82MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
83MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
84MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
85MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
86MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
87MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
88MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
89MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
90MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
91MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
92MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
93MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
94MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
95MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
96MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
97MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
98MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
99MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
100MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
101MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
102MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
103MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
104MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
105MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
106MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
107MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
108MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
109MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
110MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
111MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
112MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
113MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
114MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
115MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
116MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
117MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
118MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
119MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
120MX6Q_PAD_EIM_A25__GPIO_5_2 82
121MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
122MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
123MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
124MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
125MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
126MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
127MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
128MX6Q_PAD_EIM_EB2__GPIO_2_30 90
129MX6Q_PAD_EIM_EB2__I2C2_SCL 91
130MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
131MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
132MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
133MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
134MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
135MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
136MX6Q_PAD_EIM_D16__GPIO_3_16 98
137MX6Q_PAD_EIM_D16__I2C2_SDA 99
138MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
139MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
140MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
141MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
142MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
143MX6Q_PAD_EIM_D17__GPIO_3_17 105
144MX6Q_PAD_EIM_D17__I2C3_SCL 106
145MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
146MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
147MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
148MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
149MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
150MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
151MX6Q_PAD_EIM_D18__GPIO_3_18 113
152MX6Q_PAD_EIM_D18__I2C3_SDA 114
153MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
154MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
155MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
156MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
157MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
158MX6Q_PAD_EIM_D19__UART1_CTS 120
159MX6Q_PAD_EIM_D19__GPIO_3_19 121
160MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
161MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
162MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
163MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
164MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
165MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
166MX6Q_PAD_EIM_D20__UART1_RTS 128
167MX6Q_PAD_EIM_D20__GPIO_3_20 129
168MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
169MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
170MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
171MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
172MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
173MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
174MX6Q_PAD_EIM_D21__GPIO_3_21 136
175MX6Q_PAD_EIM_D21__I2C1_SCL 137
176MX6Q_PAD_EIM_D21__SPDIF_IN1 138
177MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
178MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
179MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
180MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
181MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
182MX6Q_PAD_EIM_D22__GPIO_3_22 144
183MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
184MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
185MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
186MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
187MX6Q_PAD_EIM_D23__UART3_CTS 149
188MX6Q_PAD_EIM_D23__UART1_DCD 150
189MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
190MX6Q_PAD_EIM_D23__GPIO_3_23 152
191MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
192MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
193MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
194MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
195MX6Q_PAD_EIM_EB3__UART3_RTS 157
196MX6Q_PAD_EIM_EB3__UART1_RI 158
197MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
198MX6Q_PAD_EIM_EB3__GPIO_2_31 160
199MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
200MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
201MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
202MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
203MX6Q_PAD_EIM_D24__UART3_TXD 165
204MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
205MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
206MX6Q_PAD_EIM_D24__GPIO_3_24 168
207MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
208MX6Q_PAD_EIM_D24__UART1_DTR 170
209MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
210MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
211MX6Q_PAD_EIM_D25__UART3_RXD 173
212MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
213MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
214MX6Q_PAD_EIM_D25__GPIO_3_25 176
215MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
216MX6Q_PAD_EIM_D25__UART1_DSR 178
217MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
218MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
219MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
220MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
221MX6Q_PAD_EIM_D26__UART2_TXD 183
222MX6Q_PAD_EIM_D26__GPIO_3_26 184
223MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
224MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
225MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
226MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
227MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
228MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
229MX6Q_PAD_EIM_D27__UART2_RXD 191
230MX6Q_PAD_EIM_D27__GPIO_3_27 192
231MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
232MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
233MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
234MX6Q_PAD_EIM_D28__I2C1_SDA 196
235MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
236MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
237MX6Q_PAD_EIM_D28__UART2_CTS 199
238MX6Q_PAD_EIM_D28__GPIO_3_28 200
239MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
240MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
241MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
242MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
243MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
244MX6Q_PAD_EIM_D29__UART2_RTS 206
245MX6Q_PAD_EIM_D29__GPIO_3_29 207
246MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
247MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
248MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
249MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
250MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
251MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
252MX6Q_PAD_EIM_D30__UART3_CTS 214
253MX6Q_PAD_EIM_D30__GPIO_3_30 215
254MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
255MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
256MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
257MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
258MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
259MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
260MX6Q_PAD_EIM_D31__UART3_RTS 222
261MX6Q_PAD_EIM_D31__GPIO_3_31 223
262MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
263MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
264MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
265MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
266MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
267MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
268MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
269MX6Q_PAD_EIM_A24__GPIO_5_4 231
270MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
271MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
272MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
273MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
274MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
275MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
276MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
277MX6Q_PAD_EIM_A23__GPIO_6_6 239
278MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
279MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
280MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
281MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
282MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
283MX6Q_PAD_EIM_A22__GPIO_2_16 245
284MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
285MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
286MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
287MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
288MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
289MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
290MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
291MX6Q_PAD_EIM_A21__GPIO_2_17 253
292MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
293MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
294MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
295MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
296MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
297MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
298MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
299MX6Q_PAD_EIM_A20__GPIO_2_18 261
300MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
301MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
302MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
303MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
304MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
305MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
306MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
307MX6Q_PAD_EIM_A19__GPIO_2_19 269
308MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
309MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
310MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
311MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
312MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
313MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
314MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
315MX6Q_PAD_EIM_A18__GPIO_2_20 277
316MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
317MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
318MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
319MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
320MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
321MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
322MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
323MX6Q_PAD_EIM_A17__GPIO_2_21 285
324MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
325MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
326MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
327MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
328MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
329MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
330MX6Q_PAD_EIM_A16__GPIO_2_22 292
331MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
332MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
333MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
334MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
335MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
336MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
337MX6Q_PAD_EIM_CS0__GPIO_2_23 299
338MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
339MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
340MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
341MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
342MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
343MX6Q_PAD_EIM_CS1__GPIO_2_24 305
344MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
345MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
346MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
347MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
348MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
349MX6Q_PAD_EIM_OE__GPIO_2_25 311
350MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
351MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
352MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
353MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
354MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
355MX6Q_PAD_EIM_RW__GPIO_2_26 317
356MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
357MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
358MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
359MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
360MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
361MX6Q_PAD_EIM_LBA__GPIO_2_27 323
362MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
363MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
364MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
365MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
366MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
367MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
368MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
369MX6Q_PAD_EIM_EB0__GPIO_2_28 331
370MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
371MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
372MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
373MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
374MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
375MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
376MX6Q_PAD_EIM_EB1__GPIO_2_29 338
377MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
378MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
379MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
380MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
381MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
382MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
383MX6Q_PAD_EIM_DA0__GPIO_3_0 345
384MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
385MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
386MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
387MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
388MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
389MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
390MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
391MX6Q_PAD_EIM_DA1__GPIO_3_1 353
392MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
393MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
394MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
395MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
396MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
397MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
398MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
399MX6Q_PAD_EIM_DA2__GPIO_3_2 361
400MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
401MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
402MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
403MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
404MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
405MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
406MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
407MX6Q_PAD_EIM_DA3__GPIO_3_3 369
408MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
409MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
410MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
411MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
412MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
413MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
414MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
415MX6Q_PAD_EIM_DA4__GPIO_3_4 377
416MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
417MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
418MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
419MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
420MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
421MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
422MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
423MX6Q_PAD_EIM_DA5__GPIO_3_5 385
424MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
425MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
426MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
427MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
428MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
429MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
430MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
431MX6Q_PAD_EIM_DA6__GPIO_3_6 393
432MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
433MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
434MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
435MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
436MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
437MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
438MX6Q_PAD_EIM_DA7__GPIO_3_7 400
439MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
440MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
441MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
442MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
443MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
444MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
445MX6Q_PAD_EIM_DA8__GPIO_3_8 407
446MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
447MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
448MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
449MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
450MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
451MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
452MX6Q_PAD_EIM_DA9__GPIO_3_9 414
453MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
454MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
455MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
456MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
457MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
458MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
459MX6Q_PAD_EIM_DA10__GPIO_3_10 421
460MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
461MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
462MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
463MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
464MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
465MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
466MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
467MX6Q_PAD_EIM_DA11__GPIO_3_11 429
468MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
469MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
470MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
471MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
472MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
473MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
474MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
475MX6Q_PAD_EIM_DA12__GPIO_3_12 437
476MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
477MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
478MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
479MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
480MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
481MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
482MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
483MX6Q_PAD_EIM_DA13__GPIO_3_13 445
484MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
485MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
486MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
487MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
488MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
489MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
490MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
491MX6Q_PAD_EIM_DA14__GPIO_3_14 453
492MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
493MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
494MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
495MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
496MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
497MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
498MX6Q_PAD_EIM_DA15__GPIO_3_15 460
499MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
500MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
501MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
502MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
503MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
504MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
505MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
506MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
507MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
508MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
509MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
510MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
511MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
512MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
513MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
514MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
515MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
516MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
517MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
518MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
519MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
520MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
521MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
522MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
523MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
524MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
525MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
526MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
527MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
528MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
529MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
530MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
531MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
532MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
533MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
534MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
535MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
536MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
537MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
538MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
539MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
540MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
541MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
542MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
543MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
544MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
545MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
546MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
547MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
548MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
549MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
550MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
551MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
552MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
553MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
554MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
555MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
556MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
557MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
558MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
559MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
560MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
561MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
562MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
563MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
564MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
565MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
566MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
567MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
568MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
569MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
570MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
571MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
572MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
573MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
574MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
575MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
576MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
577MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
578MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
579MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
580MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
581MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
582MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
583MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
584MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
585MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
586MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
587MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
588MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
589MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
590MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
591MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
592MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
593MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
594MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
595MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
596MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
597MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
598MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
599MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
600MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
601MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
602MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
603MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
604MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
605MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
606MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
607MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
608MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
609MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
610MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
611MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
612MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
613MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
614MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
615MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
616MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
617MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
618MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
619MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
620MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
621MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
622MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
623MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
624MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
625MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
626MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
627MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
628MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
629MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
630MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
631MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
632MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
633MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
634MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
635MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
636MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
637MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
638MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
639MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
640MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
641MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
642MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
643MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
644MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
645MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
646MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
647MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
648MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
649MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
650MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
651MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
652MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
653MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
654MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
655MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
656MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
657MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
658MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
659MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
660MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
661MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
662MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
663MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
664MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
665MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
666MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
667MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
668MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
669MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
670MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
671MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
672MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
673MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
674MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
675MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
676MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
677MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
678MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
679MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
680MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
681MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
682MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
683MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
684MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
685MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
686MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
687MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
688MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
689MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
690MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
691MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
692MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
693MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
694MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
695MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
696MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
697MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
698MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
699MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
700MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
701MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
702MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
703MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
704MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
705MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
706MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
707MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
708MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
709MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
710MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
711MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
712MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
713MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
714MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
715MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
716MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
717MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
718MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
719MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
720MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
721MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
722MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
723MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
724MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
725MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
726MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
727MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
728MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
729MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
730MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
731MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
732MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
733MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
734MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
735MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
736MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
737MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
738MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
739MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
740MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
741MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
742MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
743MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
744MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
745MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
746MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
747MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
748MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
749MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
750MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
751MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
752MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
753MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
754MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
755MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
756MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
757MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
758MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
759MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
760MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
761MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
762MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
763MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
764MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
765MX6Q_PAD_ENET_RXD1__PHY_TCK 727
766MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
767MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
768MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
769MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
770MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
771MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
772MX6Q_PAD_ENET_RXD0__PHY_TMS 734
773MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
774MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
775MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
776MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
777MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
778MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
779MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
780MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
781MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
782MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
783MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
784MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
785MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
786MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
787MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
788MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
789MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
790MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
791MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
792MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
793MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
794MX6Q_PAD_ENET_MDC__ENET_MDC 756
795MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
796MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
797MX6Q_PAD_ENET_MDC__GPIO_1_31 759
798MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
799MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
800MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
801MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
802MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
803MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
804MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
805MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
806MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
807MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
808MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
809MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
810MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
811MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
812MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
813MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
814MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
815MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
816MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
817MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
818MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
819MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
820MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
821MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
822MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
823MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
824MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
825MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
826MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
827MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
828MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
829MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
830MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
831MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
832MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
833MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
834MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
835MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
836MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
837MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
838MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
839MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
840MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
841MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
842MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
843MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
844MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
845MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
846MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
847MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
848MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
849MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
850MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
851MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
852MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
853MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
854MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
855MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
856MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
857MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
858MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
859MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
860MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
861MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
862MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
863MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
864MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
865MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
866MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
867MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
868MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
869MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
870MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
871MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
872MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
873MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
874MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
875MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
876MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
877MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
878MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
879MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
880MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
881MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
882MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
883MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
884MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
885MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
886MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
887MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
888MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
889MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
890MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
891MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
892MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
893MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
894MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
895MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
896MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
897MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
898MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
899MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
900MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
901MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
902MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
903MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
904MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
905MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
906MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
907MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
908MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
909MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
910MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
911MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
912MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
913MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
914MX6Q_PAD_KEY_COL0__KPP_COL_0 876
915MX6Q_PAD_KEY_COL0__UART4_TXD 877
916MX6Q_PAD_KEY_COL0__GPIO_4_6 878
917MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
918MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
919MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
920MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
921MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
922MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
923MX6Q_PAD_KEY_ROW0__UART4_RXD 885
924MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
925MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
926MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
927MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
928MX6Q_PAD_KEY_COL1__ENET_MDIO 890
929MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
930MX6Q_PAD_KEY_COL1__KPP_COL_1 892
931MX6Q_PAD_KEY_COL1__UART5_TXD 893
932MX6Q_PAD_KEY_COL1__GPIO_4_8 894
933MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
934MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
935MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
936MX6Q_PAD_KEY_ROW1__ENET_COL 898
937MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
938MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
939MX6Q_PAD_KEY_ROW1__UART5_RXD 901
940MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
941MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
942MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
943MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
944MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
945MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
946MX6Q_PAD_KEY_COL2__KPP_COL_2 908
947MX6Q_PAD_KEY_COL2__ENET_MDC 909
948MX6Q_PAD_KEY_COL2__GPIO_4_10 910
949MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
950MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
951MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
952MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
953MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
954MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
955MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
956MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
957MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
958MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
959MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
960MX6Q_PAD_KEY_COL3__ENET_CRS 922
961MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
962MX6Q_PAD_KEY_COL3__KPP_COL_3 924
963MX6Q_PAD_KEY_COL3__I2C2_SCL 925
964MX6Q_PAD_KEY_COL3__GPIO_4_12 926
965MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
966MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
967MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
968MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
969MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
970MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
971MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
972MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
973MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
974MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
975MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
976MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
977MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
978MX6Q_PAD_KEY_COL4__KPP_COL_4 940
979MX6Q_PAD_KEY_COL4__UART5_RTS 941
980MX6Q_PAD_KEY_COL4__GPIO_4_14 942
981MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
982MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
983MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
984MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
985MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
986MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
987MX6Q_PAD_KEY_ROW4__UART5_CTS 949
988MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
989MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
990MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
991MX6Q_PAD_GPIO_0__CCM_CLKO 953
992MX6Q_PAD_GPIO_0__KPP_COL_5 954
993MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
994MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
995MX6Q_PAD_GPIO_0__GPIO_1_0 957
996MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
997MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
998MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
999MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
1000MX6Q_PAD_GPIO_1__KPP_ROW_5 962
1001MX6Q_PAD_GPIO_1__PWM2_PWMO 963
1002MX6Q_PAD_GPIO_1__GPIO_1_1 964
1003MX6Q_PAD_GPIO_1__USDHC1_CD 965
1004MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
1005MX6Q_PAD_GPIO_9__ESAI1_FSR 967
1006MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
1007MX6Q_PAD_GPIO_9__KPP_COL_6 969
1008MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
1009MX6Q_PAD_GPIO_9__PWM1_PWMO 971
1010MX6Q_PAD_GPIO_9__GPIO_1_9 972
1011MX6Q_PAD_GPIO_9__USDHC1_WP 973
1012MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
1013MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
1014MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
1015MX6Q_PAD_GPIO_3__I2C3_SCL 977
1016MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
1017MX6Q_PAD_GPIO_3__CCM_CLKO2 979
1018MX6Q_PAD_GPIO_3__GPIO_1_3 980
1019MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
1020MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
1021MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
1022MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
1023MX6Q_PAD_GPIO_6__I2C3_SDA 985
1024MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
1025MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
1026MX6Q_PAD_GPIO_6__GPIO_1_6 988
1027MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
1028MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
1029MX6Q_PAD_GPIO_2__ESAI1_FST 991
1030MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
1031MX6Q_PAD_GPIO_2__KPP_ROW_6 993
1032MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
1033MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
1034MX6Q_PAD_GPIO_2__GPIO_1_2 996
1035MX6Q_PAD_GPIO_2__USDHC2_WP 997
1036MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
1037MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
1038MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
1039MX6Q_PAD_GPIO_4__KPP_COL_7 1001
1040MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
1041MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
1042MX6Q_PAD_GPIO_4__GPIO_1_4 1004
1043MX6Q_PAD_GPIO_4__USDHC2_CD 1005
1044MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
1045MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
1046MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
1047MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
1048MX6Q_PAD_GPIO_5__CCM_CLKO 1010
1049MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
1050MX6Q_PAD_GPIO_5__GPIO_1_5 1012
1051MX6Q_PAD_GPIO_5__I2C3_SCL 1013
1052MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
1053MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
1054MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
1055MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
1056MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
1057MX6Q_PAD_GPIO_7__UART2_TXD 1019
1058MX6Q_PAD_GPIO_7__GPIO_1_7 1020
1059MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
1060MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
1061MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
1062MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
1063MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
1064MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
1065MX6Q_PAD_GPIO_8__UART2_RXD 1027
1066MX6Q_PAD_GPIO_8__GPIO_1_8 1028
1067MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
1068MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
1069MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
1070MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
1071MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
1072MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
1073MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
1074MX6Q_PAD_GPIO_16__GPIO_7_11 1036
1075MX6Q_PAD_GPIO_16__I2C3_SDA 1037
1076MX6Q_PAD_GPIO_16__SJC_DE_B 1038
1077MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
1078MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
1079MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
1080MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
1081MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
1082MX6Q_PAD_GPIO_17__GPIO_7_12 1044
1083MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
1084MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
1085MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
1086MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
1087MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
1088MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
1089MX6Q_PAD_GPIO_18__GPIO_7_13 1051
1090MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
1091MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
1092MX6Q_PAD_GPIO_19__KPP_COL_5 1054
1093MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
1094MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
1095MX6Q_PAD_GPIO_19__CCM_CLKO 1057
1096MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
1097MX6Q_PAD_GPIO_19__GPIO_4_5 1059
1098MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
1099MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
1100MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
1101MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
1102MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
1103MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
1104MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
1105MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
1106MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
1107MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
1108MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
1109MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
1110MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
1111MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
1112MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
1113MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
1114MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
1115MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
1116MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
1117MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
1118MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
1119MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
1120MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
1121MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
1122MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
1123MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
1124MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
1125MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
1126MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
1127MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
1128MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
1129MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
1130MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
1131MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
1132MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
1133MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
1134MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
1135MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
1136MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
1137MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
1138MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
1139MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
1140MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
1141MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
1142MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
1143MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
1144MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
1145MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
1146MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
1147MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
1148MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
1149MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
1150MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
1151MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
1152MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
1153MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
1154MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
1155MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
1156MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
1157MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
1158MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
1159MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
1160MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
1161MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
1162MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
1163MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
1164MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
1165MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
1166MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
1167MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
1168MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
1169MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
1170MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
1171MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
1172MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
1173MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
1174MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
1175MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
1176MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
1177MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
1178MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
1179MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
1180MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
1181MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
1182MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
1183MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
1184MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
1185MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
1186MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
1187MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
1188MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
1189MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
1190MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
1191MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
1192MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
1193MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
1194MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
1195MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
1196MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
1197MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
1198MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
1199MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
1200MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
1201MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
1202MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
1203MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
1204MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
1205MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
1206MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
1207MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
1208MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
1209MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
1210MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
1211MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
1212MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
1213MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
1214MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
1215MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
1216MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
1217MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
1218MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
1219MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
1220MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
1221MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
1222MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
1223MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
1224MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
1225MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
1226MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
1227MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
1228MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
1229MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
1230MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
1231MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
1232MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
1233MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
1234MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
1235MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
1236MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
1237MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
1238MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
1239MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
1240MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
1241MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
1242MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
1243MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
1244MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
1245MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
1246MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
1247MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
1248MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
1249MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
1250MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
1251MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
1252MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
1253MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
1254MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
1255MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
1256MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
1257MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
1258MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
1259MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
1260MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
1261MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
1262MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
1263MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
1264MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
1265MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
1266MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
1267MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
1268MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
1269MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
1270MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
1271MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
1272MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
1273MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
1274MX6Q_PAD_POR_B__SRC_POR_B 1236
1275MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
1276MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
1277MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
1278MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
1279MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
1280MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
1281MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
1282MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
1283MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
1284MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
1285MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
1286MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
1287MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
1288MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
1289MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
1290MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
1291MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
1292MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
1293MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
1294MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
1295MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
1296MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
1297MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
1298MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
1299MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
1300MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
1301MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
1302MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
1303MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
1304MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
1305MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
1306MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
1307MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
1308MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
1309MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
1310MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
1311MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
1312MX6Q_PAD_SD3_CMD__UART2_CTS 1274
1313MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
1314MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
1315MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
1316MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
1317MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
1318MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
1319MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
1320MX6Q_PAD_SD3_CLK__UART2_RTS 1282
1321MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
1322MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
1323MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
1324MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
1325MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
1326MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
1327MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
1328MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
1329MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
1330MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
1331MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
1332MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
1333MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
1334MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
1335MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
1336MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
1337MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
1338MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
1339MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
1340MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
1341MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
1342MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
1343MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
1344MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
1345MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
1346MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
1347MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
1348MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
1349MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
1350MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
1351MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
1352MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
1353MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
1354MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
1355MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
1356MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
1357MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
1358MX6Q_PAD_SD3_RST__USDHC3_RST 1320
1359MX6Q_PAD_SD3_RST__UART3_RTS 1321
1360MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
1361MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
1362MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
1363MX6Q_PAD_SD3_RST__GPIO_7_8 1325
1364MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
1365MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
1366MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
1367MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
1368MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
1369MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
1370MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
1371MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
1372MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
1373MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
1374MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
1375MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
1376MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
1377MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
1378MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
1379MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
1380MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
1381MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
1382MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
1383MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
1384MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
1385MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
1386MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
1387MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
1388MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
1389MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
1390MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
1391MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
1392MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
1393MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
1394MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
1395MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
1396MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
1397MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
1398MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
1399MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
1400MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
1401MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
1402MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
1403MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
1404MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
1405MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
1406MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
1407MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
1408MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
1409MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
1410MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
1411MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
1412MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
1413MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
1414MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
1415MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
1416MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
1417MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
1418MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
1419MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
1420MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
1421MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
1422MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
1423MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
1424MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
1425MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
1426MX6Q_PAD_SD4_CMD__UART3_TXD 1388
1427MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
1428MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
1429MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
1430MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
1431MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
1432MX6Q_PAD_SD4_CLK__UART3_RXD 1394
1433MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
1434MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
1435MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
1436MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
1437MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
1438MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
1439MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
1440MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
1441MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
1442MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
1443MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
1444MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
1445MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
1446MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
1447MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
1448MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
1449MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
1450MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
1451MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
1452MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
1453MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
1454MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
1455MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
1456MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
1457MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
1458MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
1459MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
1460MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
1461MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
1462MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
1463MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
1464MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
1465MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
1466MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
1467MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
1468MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
1469MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
1470MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
1471MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
1472MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
1473MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
1474MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
1475MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
1476MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
1477MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
1478MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
1479MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
1480MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
1481MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
1482MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
1483MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
1484MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
1485MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
1486MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
1487MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
1488MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
1489MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
1490MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
1491MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
1492MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
1493MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
1494MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
1495MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
1496MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
1497MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
1498MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
1499MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
1500MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
1501MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
1502MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
1503MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
1504MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
1505MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
1506MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
1507MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
1508MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
1509MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
1510MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
1511MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
1512MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
1513MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
1514MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
1515MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
1516MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
1517MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
1518MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
1519MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
1520MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
1521MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
1522MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
1523MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
1524MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
1525MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
1526MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
1527MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
1528MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
1529MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
1530MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
1531MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
1532MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
1533MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
1534MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
1535MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
1536MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
1537MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
1538MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
1539MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
1540MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
1541MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
1542MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
1543MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
1544MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
1545MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
1546MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
1547MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
1548MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
1549MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
1550MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
1551MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
1552MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
1553MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
1554MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
1555MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
1556MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
1557MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
1558MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
1559MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
1560MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
1561MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
1562MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
1563MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
1564MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
1565MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
1566MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
1567MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
1568MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
1569MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
1570MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
1571MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
1572MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
1573MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
1574MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
1575MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
1576MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
1577MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
1578MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
1579MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
1580MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
1581MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
1582MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
1583MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
1584MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
1585MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
1586MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
1587MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
1588MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
1589MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
1590MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
1591MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
1592MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
1593MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
1594MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
1595MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
1596MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
1597MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
1598MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
1599MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
1600MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
1601MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
1602MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
1603MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
1604MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
1605MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
1606MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
1607MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
1608MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
1609MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
1610MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
1611MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
1612MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
1613MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
1614MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
1615MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
1616MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
1617MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
1618MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
1619MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
1620MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
1621MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
1622MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
1623MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
1624MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
1625MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
1629MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591
1630MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
deleted file mode 100644
index f7e8e8f4d9a..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
+++ /dev/null
@@ -1,918 +0,0 @@
1* Freescale MXS Pin Controller
2
3The pins controlled by mxs pin controller are organized in banks, each bank
4has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5function is GPIO. The configuration on the pins includes drive strength,
6voltage and pull-up.
7
8Required properties:
9- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10- reg: Should contain the register physical address and length for the
11 pin controller.
12
13Please refer to pinctrl-bindings.txt in this directory for details of the
14common pinctrl bindings used by client devices.
15
16The node of mxs pin controller acts as a container for an arbitrary number of
17subnodes. Each of these subnodes represents some desired configuration for
18a group of pins, and only affects those parameters that are explicitly listed.
19In other words, a subnode that describes a drive strength parameter implies no
20information about pull-up. For this reason, even seemingly boolean values are
21actually tristates in this binding: unspecified, off, or on. Unspecified is
22represented as an absent property, and off/on are represented as integer
23values 0 and 1.
24
25Those subnodes under mxs pin controller node will fall into two categories.
26One is to set up a group of pins for a function, both mux selection and pin
27configurations, and it's called group node in the binding document. The other
28one is to adjust the pin configuration for some particular pins that need a
29different configuration than what is defined in group node. The binding
30document calls this type of node config node.
31
32On mxs, there is no hardware pin group. The pin group in this binding only
33means a group of pins put together for particular peripheral to work in
34particular function, like SSP0 functioning as mmc0-8bit. That said, the
35group node should include all the pins needed for one function rather than
36having these pins defined in several group nodes. It also means each of
37"pinctrl-*" phandle in client device node should only have one group node
38pointed in there, while the phandle can have multiple config node referenced
39there to adjust configurations for some pins in the group.
40
41Required subnode-properties:
42- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
43 with given mux function, with bank, pin and mux packed as below.
44
45 [15..12] : bank number
46 [11..4] : pin number
47 [3..0] : mux selection
48
49 This integer with mux selection packed is used as an entity by both group
50 and config nodes to identify a pin. The mux selection in the integer takes
51 effects only on group node, and will get ignored by driver with config node,
52 since config node is only meant to set up pin configurations.
53
54 Valid values for these integers are listed below.
55
56- reg: Should be the index of the group nodes for same function. This property
57 is required only for group nodes, and should not be present in any config
58 nodes.
59
60Optional subnode-properties:
61- fsl,drive-strength: Integer.
62 0: 4 mA
63 1: 8 mA
64 2: 12 mA
65 3: 16 mA
66- fsl,voltage: Integer.
67 0: 1.8 V
68 1: 3.3 V
69- fsl,pull-up: Integer.
70 0: Disable the internal pull-up
71 1: Enable the internal pull-up
72
73Examples:
74
75pinctrl@80018000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "fsl,imx28-pinctrl";
79 reg = <0x80018000 2000>;
80
81 mmc0_8bit_pins_a: mmc0-8bit@0 {
82 reg = <0>;
83 fsl,pinmux-ids = <
84 0x2000 0x2010 0x2020 0x2030
85 0x2040 0x2050 0x2060 0x2070
86 0x2080 0x2090 0x20a0>;
87 fsl,drive-strength = <1>;
88 fsl,voltage = <1>;
89 fsl,pull-up = <1>;
90 };
91
92 mmc_cd_cfg: mmc-cd-cfg {
93 fsl,pinmux-ids = <0x2090>;
94 fsl,pull-up = <0>;
95 };
96
97 mmc_sck_cfg: mmc-sck-cfg {
98 fsl,pinmux-ids = <0x20a0>;
99 fsl,drive-strength = <2>;
100 fsl,pull-up = <0>;
101 };
102};
103
104In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
105to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
106applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
107adjusting the configuration for pins card-detection and clock from what group
108node mmc0-8bit defines. Only the configuration properties to be adjusted need
109to be listed in the config nodes.
110
111Valid values for i.MX28 pinmux-id:
112
113pinmux id
114------ --
115MX28_PAD_GPMI_D00__GPMI_D0 0x0000
116MX28_PAD_GPMI_D01__GPMI_D1 0x0010
117MX28_PAD_GPMI_D02__GPMI_D2 0x0020
118MX28_PAD_GPMI_D03__GPMI_D3 0x0030
119MX28_PAD_GPMI_D04__GPMI_D4 0x0040
120MX28_PAD_GPMI_D05__GPMI_D5 0x0050
121MX28_PAD_GPMI_D06__GPMI_D6 0x0060
122MX28_PAD_GPMI_D07__GPMI_D7 0x0070
123MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
124MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
125MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
126MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
127MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
128MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
129MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
130MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
131MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
132MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
133MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
134MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
135MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
136MX28_PAD_LCD_D00__LCD_D0 0x1000
137MX28_PAD_LCD_D01__LCD_D1 0x1010
138MX28_PAD_LCD_D02__LCD_D2 0x1020
139MX28_PAD_LCD_D03__LCD_D3 0x1030
140MX28_PAD_LCD_D04__LCD_D4 0x1040
141MX28_PAD_LCD_D05__LCD_D5 0x1050
142MX28_PAD_LCD_D06__LCD_D6 0x1060
143MX28_PAD_LCD_D07__LCD_D7 0x1070
144MX28_PAD_LCD_D08__LCD_D8 0x1080
145MX28_PAD_LCD_D09__LCD_D9 0x1090
146MX28_PAD_LCD_D10__LCD_D10 0x10a0
147MX28_PAD_LCD_D11__LCD_D11 0x10b0
148MX28_PAD_LCD_D12__LCD_D12 0x10c0
149MX28_PAD_LCD_D13__LCD_D13 0x10d0
150MX28_PAD_LCD_D14__LCD_D14 0x10e0
151MX28_PAD_LCD_D15__LCD_D15 0x10f0
152MX28_PAD_LCD_D16__LCD_D16 0x1100
153MX28_PAD_LCD_D17__LCD_D17 0x1110
154MX28_PAD_LCD_D18__LCD_D18 0x1120
155MX28_PAD_LCD_D19__LCD_D19 0x1130
156MX28_PAD_LCD_D20__LCD_D20 0x1140
157MX28_PAD_LCD_D21__LCD_D21 0x1150
158MX28_PAD_LCD_D22__LCD_D22 0x1160
159MX28_PAD_LCD_D23__LCD_D23 0x1170
160MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
161MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
162MX28_PAD_LCD_RS__LCD_RS 0x11a0
163MX28_PAD_LCD_CS__LCD_CS 0x11b0
164MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
165MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
166MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
167MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
168MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
169MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
170MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
171MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
172MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
173MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
174MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
175MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
176MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
177MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
178MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
179MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
180MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
181MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
182MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
183MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
184MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
185MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
186MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
187MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
188MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
189MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
190MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
191MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
192MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
193MX28_PAD_AUART0_RX__AUART0_RX 0x3000
194MX28_PAD_AUART0_TX__AUART0_TX 0x3010
195MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
196MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
197MX28_PAD_AUART1_RX__AUART1_RX 0x3040
198MX28_PAD_AUART1_TX__AUART1_TX 0x3050
199MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
200MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
201MX28_PAD_AUART2_RX__AUART2_RX 0x3080
202MX28_PAD_AUART2_TX__AUART2_TX 0x3090
203MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
204MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
205MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
206MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
207MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
208MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
209MX28_PAD_PWM0__PWM_0 0x3100
210MX28_PAD_PWM1__PWM_1 0x3110
211MX28_PAD_PWM2__PWM_2 0x3120
212MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
213MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
214MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
215MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
216MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
217MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
218MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
219MX28_PAD_SPDIF__SPDIF_TX 0x31b0
220MX28_PAD_PWM3__PWM_3 0x31c0
221MX28_PAD_PWM4__PWM_4 0x31d0
222MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
223MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
224MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
225MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
226MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
227MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
228MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
229MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
230MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
231MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
232MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
233MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
234MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
235MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
236MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
237MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
238MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
239MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
240MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
241MX28_PAD_EMI_D00__EMI_DATA0 0x5000
242MX28_PAD_EMI_D01__EMI_DATA1 0x5010
243MX28_PAD_EMI_D02__EMI_DATA2 0x5020
244MX28_PAD_EMI_D03__EMI_DATA3 0x5030
245MX28_PAD_EMI_D04__EMI_DATA4 0x5040
246MX28_PAD_EMI_D05__EMI_DATA5 0x5050
247MX28_PAD_EMI_D06__EMI_DATA6 0x5060
248MX28_PAD_EMI_D07__EMI_DATA7 0x5070
249MX28_PAD_EMI_D08__EMI_DATA8 0x5080
250MX28_PAD_EMI_D09__EMI_DATA9 0x5090
251MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
252MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
253MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
254MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
255MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
256MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
257MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
258MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
259MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
260MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
261MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
262MX28_PAD_EMI_CLK__EMI_CLK 0x5150
263MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
264MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
265MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
266MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
267MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
268MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
269MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
270MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
271MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
272MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
273MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
274MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
275MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
276MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
277MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
278MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
279MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
280MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
281MX28_PAD_EMI_BA0__EMI_BA0 0x6100
282MX28_PAD_EMI_BA1__EMI_BA1 0x6110
283MX28_PAD_EMI_BA2__EMI_BA2 0x6120
284MX28_PAD_EMI_CASN__EMI_CASN 0x6130
285MX28_PAD_EMI_RASN__EMI_RASN 0x6140
286MX28_PAD_EMI_WEN__EMI_WEN 0x6150
287MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
288MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
289MX28_PAD_EMI_CKE__EMI_CKE 0x6180
290MX28_PAD_GPMI_D00__SSP1_D0 0x0001
291MX28_PAD_GPMI_D01__SSP1_D1 0x0011
292MX28_PAD_GPMI_D02__SSP1_D2 0x0021
293MX28_PAD_GPMI_D03__SSP1_D3 0x0031
294MX28_PAD_GPMI_D04__SSP1_D4 0x0041
295MX28_PAD_GPMI_D05__SSP1_D5 0x0051
296MX28_PAD_GPMI_D06__SSP1_D6 0x0061
297MX28_PAD_GPMI_D07__SSP1_D7 0x0071
298MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
299MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
300MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
301MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
302MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
303MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
304MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
305MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
306MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
307MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
308MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
309MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
310MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
311MX28_PAD_LCD_D03__ETM_DA8 0x1031
312MX28_PAD_LCD_D04__ETM_DA9 0x1041
313MX28_PAD_LCD_D08__ETM_DA3 0x1081
314MX28_PAD_LCD_D09__ETM_DA4 0x1091
315MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
316MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
317MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
318MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
319MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
320MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
321MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
322MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
323MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
324MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
325MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
326MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
327MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
328MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
329MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
330MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
331MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
332MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
333MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
334MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
335MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
336MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
337MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
338MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
339MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
340MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
341MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
342MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
343MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
344MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
345MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
346MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
347MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
348MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
349MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
350MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
351MX28_PAD_AUART1_RTS__USB0_ID 0x3071
352MX28_PAD_AUART2_RX__SSP3_D1 0x3081
353MX28_PAD_AUART2_TX__SSP3_D2 0x3091
354MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
355MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
356MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
357MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
358MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
359MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
360MX28_PAD_PWM0__I2C1_SCL 0x3101
361MX28_PAD_PWM1__I2C1_SDA 0x3111
362MX28_PAD_PWM2__USB0_ID 0x3121
363MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
364MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
365MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
366MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
367MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
368MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
369MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
370MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
371MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
372MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
373MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
374MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
375MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
376MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
377MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
378MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
379MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
380MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
381MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
382MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
383MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
384MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
385MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
386MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
387MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
388MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
389MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
390MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
391MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
392MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
393MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
394MX28_PAD_LCD_D00__ETM_DA0 0x1002
395MX28_PAD_LCD_D01__ETM_DA1 0x1012
396MX28_PAD_LCD_D02__ETM_DA2 0x1022
397MX28_PAD_LCD_D03__ETM_DA3 0x1032
398MX28_PAD_LCD_D04__ETM_DA4 0x1042
399MX28_PAD_LCD_D05__ETM_DA5 0x1052
400MX28_PAD_LCD_D06__ETM_DA6 0x1062
401MX28_PAD_LCD_D07__ETM_DA7 0x1072
402MX28_PAD_LCD_D08__ETM_DA8 0x1082
403MX28_PAD_LCD_D09__ETM_DA9 0x1092
404MX28_PAD_LCD_D10__ETM_DA10 0x10a2
405MX28_PAD_LCD_D11__ETM_DA11 0x10b2
406MX28_PAD_LCD_D12__ETM_DA12 0x10c2
407MX28_PAD_LCD_D13__ETM_DA13 0x10d2
408MX28_PAD_LCD_D14__ETM_DA14 0x10e2
409MX28_PAD_LCD_D15__ETM_DA15 0x10f2
410MX28_PAD_LCD_D16__ETM_DA7 0x1102
411MX28_PAD_LCD_D17__ETM_DA6 0x1112
412MX28_PAD_LCD_D18__ETM_DA5 0x1122
413MX28_PAD_LCD_D19__ETM_DA4 0x1132
414MX28_PAD_LCD_D20__ETM_DA3 0x1142
415MX28_PAD_LCD_D21__ETM_DA2 0x1152
416MX28_PAD_LCD_D22__ETM_DA1 0x1162
417MX28_PAD_LCD_D23__ETM_DA0 0x1172
418MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
419MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
420MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
421MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
422MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
423MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
424MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
425MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
426MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
427MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
428MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
429MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
430MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
431MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
432MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
433MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
434MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
435MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
436MX28_PAD_AUART0_RX__DUART_CTS 0x3002
437MX28_PAD_AUART0_TX__DUART_RTS 0x3012
438MX28_PAD_AUART0_CTS__DUART_RX 0x3022
439MX28_PAD_AUART0_RTS__DUART_TX 0x3032
440MX28_PAD_AUART1_RX__PWM_0 0x3042
441MX28_PAD_AUART1_TX__PWM_1 0x3052
442MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
443MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
444MX28_PAD_AUART2_RX__SSP3_D4 0x3082
445MX28_PAD_AUART2_TX__SSP3_D5 0x3092
446MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
447MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
448MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
449MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
450MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
451MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
452MX28_PAD_PWM0__DUART_RX 0x3102
453MX28_PAD_PWM1__DUART_TX 0x3112
454MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
455MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
456MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
457MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
458MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
459MX28_PAD_I2C0_SCL__DUART_RX 0x3182
460MX28_PAD_I2C0_SDA__DUART_TX 0x3192
461MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
462MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
463MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
464MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
465MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
466MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
467MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
468MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
469MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
470MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
471MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
472MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
473MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
474MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
475MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
476MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
477MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
478MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
479MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
480MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
481MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
482MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
483MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
484MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
485MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
486MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
487MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
488MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
489MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
490MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
491MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
492MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
493MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
494MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
495MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
496MX28_PAD_LCD_D00__GPIO_1_0 0x1003
497MX28_PAD_LCD_D01__GPIO_1_1 0x1013
498MX28_PAD_LCD_D02__GPIO_1_2 0x1023
499MX28_PAD_LCD_D03__GPIO_1_3 0x1033
500MX28_PAD_LCD_D04__GPIO_1_4 0x1043
501MX28_PAD_LCD_D05__GPIO_1_5 0x1053
502MX28_PAD_LCD_D06__GPIO_1_6 0x1063
503MX28_PAD_LCD_D07__GPIO_1_7 0x1073
504MX28_PAD_LCD_D08__GPIO_1_8 0x1083
505MX28_PAD_LCD_D09__GPIO_1_9 0x1093
506MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
507MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
508MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
509MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
510MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
511MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
512MX28_PAD_LCD_D16__GPIO_1_16 0x1103
513MX28_PAD_LCD_D17__GPIO_1_17 0x1113
514MX28_PAD_LCD_D18__GPIO_1_18 0x1123
515MX28_PAD_LCD_D19__GPIO_1_19 0x1133
516MX28_PAD_LCD_D20__GPIO_1_20 0x1143
517MX28_PAD_LCD_D21__GPIO_1_21 0x1153
518MX28_PAD_LCD_D22__GPIO_1_22 0x1163
519MX28_PAD_LCD_D23__GPIO_1_23 0x1173
520MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
521MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
522MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
523MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
524MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
525MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
526MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
527MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
528MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
529MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
530MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
531MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
532MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
533MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
534MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
535MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
536MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
537MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
538MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
539MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
540MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
541MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
542MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
543MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
544MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
545MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
546MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
547MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
548MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
549MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
550MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
551MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
552MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
553MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
554MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
555MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
556MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
557MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
558MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
559MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
560MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
561MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
562MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
563MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
564MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
565MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
566MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
567MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
568MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
569MX28_PAD_PWM0__GPIO_3_16 0x3103
570MX28_PAD_PWM1__GPIO_3_17 0x3113
571MX28_PAD_PWM2__GPIO_3_18 0x3123
572MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
573MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
574MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
575MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
576MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
577MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
578MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
579MX28_PAD_SPDIF__GPIO_3_27 0x31b3
580MX28_PAD_PWM3__GPIO_3_28 0x31c3
581MX28_PAD_PWM4__GPIO_3_29 0x31d3
582MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
583MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
584MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
585MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
586MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
587MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
588MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
589MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
590MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
591MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
592MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
593MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
594MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
595MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
596MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
597MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
598MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
599MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
600MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
601
602Valid values for i.MX23 pinmux-id:
603
604pinmux id
605------ --
606MX23_PAD_GPMI_D00__GPMI_D00 0x0000
607MX23_PAD_GPMI_D01__GPMI_D01 0x0010
608MX23_PAD_GPMI_D02__GPMI_D02 0x0020
609MX23_PAD_GPMI_D03__GPMI_D03 0x0030
610MX23_PAD_GPMI_D04__GPMI_D04 0x0040
611MX23_PAD_GPMI_D05__GPMI_D05 0x0050
612MX23_PAD_GPMI_D06__GPMI_D06 0x0060
613MX23_PAD_GPMI_D07__GPMI_D07 0x0070
614MX23_PAD_GPMI_D08__GPMI_D08 0x0080
615MX23_PAD_GPMI_D09__GPMI_D09 0x0090
616MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
617MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
618MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
619MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
620MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
621MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
622MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
623MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
624MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
625MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
626MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
627MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
628MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
629MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
630MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
631MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
632MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
633MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
634MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
635MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
636MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
637MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
638MX23_PAD_LCD_D00__LCD_D00 0x1000
639MX23_PAD_LCD_D01__LCD_D01 0x1010
640MX23_PAD_LCD_D02__LCD_D02 0x1020
641MX23_PAD_LCD_D03__LCD_D03 0x1030
642MX23_PAD_LCD_D04__LCD_D04 0x1040
643MX23_PAD_LCD_D05__LCD_D05 0x1050
644MX23_PAD_LCD_D06__LCD_D06 0x1060
645MX23_PAD_LCD_D07__LCD_D07 0x1070
646MX23_PAD_LCD_D08__LCD_D08 0x1080
647MX23_PAD_LCD_D09__LCD_D09 0x1090
648MX23_PAD_LCD_D10__LCD_D10 0x10a0
649MX23_PAD_LCD_D11__LCD_D11 0x10b0
650MX23_PAD_LCD_D12__LCD_D12 0x10c0
651MX23_PAD_LCD_D13__LCD_D13 0x10d0
652MX23_PAD_LCD_D14__LCD_D14 0x10e0
653MX23_PAD_LCD_D15__LCD_D15 0x10f0
654MX23_PAD_LCD_D16__LCD_D16 0x1100
655MX23_PAD_LCD_D17__LCD_D17 0x1110
656MX23_PAD_LCD_RESET__LCD_RESET 0x1120
657MX23_PAD_LCD_RS__LCD_RS 0x1130
658MX23_PAD_LCD_WR__LCD_WR 0x1140
659MX23_PAD_LCD_CS__LCD_CS 0x1150
660MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
661MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
662MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
663MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
664MX23_PAD_PWM0__PWM0 0x11a0
665MX23_PAD_PWM1__PWM1 0x11b0
666MX23_PAD_PWM2__PWM2 0x11c0
667MX23_PAD_PWM3__PWM3 0x11d0
668MX23_PAD_PWM4__PWM4 0x11e0
669MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
670MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
671MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
672MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
673MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
674MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
675MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
676MX23_PAD_ROTARYA__ROTARYA 0x2070
677MX23_PAD_ROTARYB__ROTARYB 0x2080
678MX23_PAD_EMI_A00__EMI_A00 0x2090
679MX23_PAD_EMI_A01__EMI_A01 0x20a0
680MX23_PAD_EMI_A02__EMI_A02 0x20b0
681MX23_PAD_EMI_A03__EMI_A03 0x20c0
682MX23_PAD_EMI_A04__EMI_A04 0x20d0
683MX23_PAD_EMI_A05__EMI_A05 0x20e0
684MX23_PAD_EMI_A06__EMI_A06 0x20f0
685MX23_PAD_EMI_A07__EMI_A07 0x2100
686MX23_PAD_EMI_A08__EMI_A08 0x2110
687MX23_PAD_EMI_A09__EMI_A09 0x2120
688MX23_PAD_EMI_A10__EMI_A10 0x2130
689MX23_PAD_EMI_A11__EMI_A11 0x2140
690MX23_PAD_EMI_A12__EMI_A12 0x2150
691MX23_PAD_EMI_BA0__EMI_BA0 0x2160
692MX23_PAD_EMI_BA1__EMI_BA1 0x2170
693MX23_PAD_EMI_CASN__EMI_CASN 0x2180
694MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
695MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
696MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
697MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
698MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
699MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
700MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
701MX23_PAD_EMI_D00__EMI_D00 0x3000
702MX23_PAD_EMI_D01__EMI_D01 0x3010
703MX23_PAD_EMI_D02__EMI_D02 0x3020
704MX23_PAD_EMI_D03__EMI_D03 0x3030
705MX23_PAD_EMI_D04__EMI_D04 0x3040
706MX23_PAD_EMI_D05__EMI_D05 0x3050
707MX23_PAD_EMI_D06__EMI_D06 0x3060
708MX23_PAD_EMI_D07__EMI_D07 0x3070
709MX23_PAD_EMI_D08__EMI_D08 0x3080
710MX23_PAD_EMI_D09__EMI_D09 0x3090
711MX23_PAD_EMI_D10__EMI_D10 0x30a0
712MX23_PAD_EMI_D11__EMI_D11 0x30b0
713MX23_PAD_EMI_D12__EMI_D12 0x30c0
714MX23_PAD_EMI_D13__EMI_D13 0x30d0
715MX23_PAD_EMI_D14__EMI_D14 0x30e0
716MX23_PAD_EMI_D15__EMI_D15 0x30f0
717MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
718MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
719MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
720MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
721MX23_PAD_EMI_CLK__EMI_CLK 0x3140
722MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
723MX23_PAD_GPMI_D00__LCD_D8 0x0001
724MX23_PAD_GPMI_D01__LCD_D9 0x0011
725MX23_PAD_GPMI_D02__LCD_D10 0x0021
726MX23_PAD_GPMI_D03__LCD_D11 0x0031
727MX23_PAD_GPMI_D04__LCD_D12 0x0041
728MX23_PAD_GPMI_D05__LCD_D13 0x0051
729MX23_PAD_GPMI_D06__LCD_D14 0x0061
730MX23_PAD_GPMI_D07__LCD_D15 0x0071
731MX23_PAD_GPMI_D08__LCD_D18 0x0081
732MX23_PAD_GPMI_D09__LCD_D19 0x0091
733MX23_PAD_GPMI_D10__LCD_D20 0x00a1
734MX23_PAD_GPMI_D11__LCD_D21 0x00b1
735MX23_PAD_GPMI_D12__LCD_D22 0x00c1
736MX23_PAD_GPMI_D13__LCD_D23 0x00d1
737MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
738MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
739MX23_PAD_GPMI_CLE__LCD_D16 0x0101
740MX23_PAD_GPMI_ALE__LCD_D17 0x0111
741MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
742MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
743MX23_PAD_AUART1_RX__IR_RX 0x01c1
744MX23_PAD_AUART1_TX__IR_TX 0x01d1
745MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
746MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
747MX23_PAD_LCD_D00__ETM_DA8 0x1001
748MX23_PAD_LCD_D01__ETM_DA9 0x1011
749MX23_PAD_LCD_D02__ETM_DA10 0x1021
750MX23_PAD_LCD_D03__ETM_DA11 0x1031
751MX23_PAD_LCD_D04__ETM_DA12 0x1041
752MX23_PAD_LCD_D05__ETM_DA13 0x1051
753MX23_PAD_LCD_D06__ETM_DA14 0x1061
754MX23_PAD_LCD_D07__ETM_DA15 0x1071
755MX23_PAD_LCD_D08__ETM_DA0 0x1081
756MX23_PAD_LCD_D09__ETM_DA1 0x1091
757MX23_PAD_LCD_D10__ETM_DA2 0x10a1
758MX23_PAD_LCD_D11__ETM_DA3 0x10b1
759MX23_PAD_LCD_D12__ETM_DA4 0x10c1
760MX23_PAD_LCD_D13__ETM_DA5 0x10d1
761MX23_PAD_LCD_D14__ETM_DA6 0x10e1
762MX23_PAD_LCD_D15__ETM_DA7 0x10f1
763MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
764MX23_PAD_LCD_RS__ETM_TCLK 0x1131
765MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
766MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
767MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
768MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
769MX23_PAD_PWM0__ROTARYA 0x11a1
770MX23_PAD_PWM1__ROTARYB 0x11b1
771MX23_PAD_PWM2__GPMI_RDY3 0x11c1
772MX23_PAD_PWM3__ETM_TCTL 0x11d1
773MX23_PAD_PWM4__ETM_TCLK 0x11e1
774MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
775MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
776MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
777MX23_PAD_ROTARYA__AUART2_RTS 0x2071
778MX23_PAD_ROTARYB__AUART2_CTS 0x2081
779MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
780MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
781MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
782MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
783MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
784MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
785MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
786MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
787MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
788MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
789MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
790MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
791MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
792MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
793MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
794MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
795MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
796MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
797MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
798MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
799MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
800MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
801MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
802MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
803MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
804MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
805MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
806MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
807MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
808MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
809MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
810MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
811MX23_PAD_PWM0__DUART_RX 0x11a2
812MX23_PAD_PWM1__DUART_TX 0x11b2
813MX23_PAD_PWM3__AUART1_CTS 0x11d2
814MX23_PAD_PWM4__AUART1_RTS 0x11e2
815MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
816MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
817MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
818MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
819MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
820MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
821MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
822MX23_PAD_ROTARYA__SPDIF 0x2072
823MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
824MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
825MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
826MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
827MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
828MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
829MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
830MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
831MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
832MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
833MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
834MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
835MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
836MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
837MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
838MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
839MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
840MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
841MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
842MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
843MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
844MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
845MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
846MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
847MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
848MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
849MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
850MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
851MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
852MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
853MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
854MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
855MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
856MX23_PAD_LCD_D00__GPIO_1_0 0x1003
857MX23_PAD_LCD_D01__GPIO_1_1 0x1013
858MX23_PAD_LCD_D02__GPIO_1_2 0x1023
859MX23_PAD_LCD_D03__GPIO_1_3 0x1033
860MX23_PAD_LCD_D04__GPIO_1_4 0x1043
861MX23_PAD_LCD_D05__GPIO_1_5 0x1053
862MX23_PAD_LCD_D06__GPIO_1_6 0x1063
863MX23_PAD_LCD_D07__GPIO_1_7 0x1073
864MX23_PAD_LCD_D08__GPIO_1_8 0x1083
865MX23_PAD_LCD_D09__GPIO_1_9 0x1093
866MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
867MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
868MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
869MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
870MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
871MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
872MX23_PAD_LCD_D16__GPIO_1_16 0x1103
873MX23_PAD_LCD_D17__GPIO_1_17 0x1113
874MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
875MX23_PAD_LCD_RS__GPIO_1_19 0x1133
876MX23_PAD_LCD_WR__GPIO_1_20 0x1143
877MX23_PAD_LCD_CS__GPIO_1_21 0x1153
878MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
879MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
880MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
881MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
882MX23_PAD_PWM0__GPIO_1_26 0x11a3
883MX23_PAD_PWM1__GPIO_1_27 0x11b3
884MX23_PAD_PWM2__GPIO_1_28 0x11c3
885MX23_PAD_PWM3__GPIO_1_29 0x11d3
886MX23_PAD_PWM4__GPIO_1_30 0x11e3
887MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
888MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
889MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
890MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
891MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
892MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
893MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
894MX23_PAD_ROTARYA__GPIO_2_7 0x2073
895MX23_PAD_ROTARYB__GPIO_2_8 0x2083
896MX23_PAD_EMI_A00__GPIO_2_9 0x2093
897MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
898MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
899MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
900MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
901MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
902MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
903MX23_PAD_EMI_A07__GPIO_2_16 0x2103
904MX23_PAD_EMI_A08__GPIO_2_17 0x2113
905MX23_PAD_EMI_A09__GPIO_2_18 0x2123
906MX23_PAD_EMI_A10__GPIO_2_19 0x2133
907MX23_PAD_EMI_A11__GPIO_2_20 0x2143
908MX23_PAD_EMI_A12__GPIO_2_21 0x2153
909MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
910MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
911MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
912MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
913MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
914MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
915MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
916MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
917MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
918MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
deleted file mode 100644
index daa76895606..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
+++ /dev/null
@@ -1,83 +0,0 @@
1Lantiq FALCON pinmux controller
2
3Required properties:
4- compatible: "lantiq,pinctrl-falcon"
5- reg: Should contain the physical address and length of the gpio/pinmux
6 register range
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12Lantiq's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those group(s), and two pin configuration parameters:
16pull-up and open-drain
17
18The name of each subnode is not important as long as it is unique; all subnodes
19should be enumerated and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function.
26
27We support 2 types of nodes.
28
29Definition of mux function groups:
30
31Required subnode-properties:
32- lantiq,groups : An array of strings. Each string contains the name of a group.
33 Valid values for these names are listed below.
34- lantiq,function: A string containing the name of the function to mux to the
35 group. Valid values for function names are listed below.
36
37Valid values for group and function names:
38
39 mux groups:
40 por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
41 jtag, slic, pcm, asc1
42
43 functions:
44 rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
45
46
47Definition of pin configurations:
48
49Required subnode-properties:
50- lantiq,pins : An array of strings. Each string contains the name of a pin.
51 Valid values for these names are listed below.
52
53Optional subnode-properties:
54- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
55 0: none, 1: down
56- lantiq,drive-current: Boolean, enables drive-current
57- lantiq,slew-rate: Boolean, enables slew-rate
58
59Example:
60 pinmux0 {
61 compatible = "lantiq,pinctrl-falcon";
62 pinctrl-names = "default";
63 pinctrl-0 = <&state_default>;
64
65 state_default: pinmux {
66 asc0 {
67 lantiq,groups = "asc0";
68 lantiq,function = "asc";
69 };
70 ntr {
71 lantiq,groups = "ntr8k";
72 lantiq,function = "ntr";
73 };
74 i2c {
75 lantiq,groups = "i2c";
76 lantiq,function = "i2c";
77 };
78 hrst {
79 lantiq,groups = "hrst";
80 lantiq,function = "rst";
81 };
82 };
83 };
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
deleted file mode 100644
index b5469db1d7a..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
+++ /dev/null
@@ -1,97 +0,0 @@
1Lantiq XWAY pinmux controller
2
3Required properties:
4- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
5- reg: Should contain the physical address and length of the gpio/pinmux
6 register range
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12Lantiq's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those group(s), and two pin configuration parameters:
16pull-up and open-drain
17
18The name of each subnode is not important as long as it is unique; all subnodes
19should be enumerated and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function.
26
27We support 2 types of nodes.
28
29Definition of mux function groups:
30
31Required subnode-properties:
32- lantiq,groups : An array of strings. Each string contains the name of a group.
33 Valid values for these names are listed below.
34- lantiq,function: A string containing the name of the function to mux to the
35 group. Valid values for function names are listed below.
36
37Valid values for group and function names:
38
39 mux groups:
40 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
41 ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
42 spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
43 gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
44 req3
45
46 additional mux groups (XR9 only):
47 mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
48
49 functions:
50 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
51
52
53
54Definition of pin configurations:
55
56Required subnode-properties:
57- lantiq,pins : An array of strings. Each string contains the name of a pin.
58 Valid values for these names are listed below.
59
60Optional subnode-properties:
61- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
62 0: none, 1: down, 2: up.
63- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
64
65Valid values for XWAY pin names:
66 Pinconf pins can be referenced via the names io0-io31.
67
68Valid values for XR9 pin names:
69 Pinconf pins can be referenced via the names io0-io55.
70
71Example:
72 gpio: pinmux@E100B10 {
73 compatible = "lantiq,pinctrl-xway";
74 pinctrl-names = "default";
75 pinctrl-0 = <&state_default>;
76
77 #gpio-cells = <2>;
78 gpio-controller;
79 reg = <0xE100B10 0xA0>;
80
81 state_default: pinmux {
82 stp {
83 lantiq,groups = "stp";
84 lantiq,function = "stp";
85 };
86 pci {
87 lantiq,groups = "gnt1";
88 lantiq,function = "pci";
89 };
90 conf_out {
91 lantiq,pins = "io4", "io5", "io6"; /* stp */
92 lantiq,open-drain;
93 lantiq,pull = <0>;
94 };
95 };
96 };
97
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
deleted file mode 100644
index 01ef408e205..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ /dev/null
@@ -1,95 +0,0 @@
1* Marvell Armada 370 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6710-pinctrl"
8
9Available mpp pins/groups and functions:
10Note: brackets (x) are not part of the mpp name for marvell,function and given
11only for more detailed description in this document.
12
13name pins functions
14================================================================================
15mpp0 0 gpio, uart0(rxd)
16mpp1 1 gpo, uart0(txd)
17mpp2 2 gpio, i2c0(sck), uart0(txd)
18mpp3 3 gpio, i2c0(sda), uart0(rxd)
19mpp4 4 gpio, cpu_pd(vdd)
20mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
21mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
22mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
23mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
24mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
25mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
26mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
27 sata1(prsnt), spi1(cs1)
28mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
29 audio(spdifi)
30mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
31 audio(rmclk)
32mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
33 spi0(cs2)
34mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
35 spi0(cs3)
36mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
37mpp17 17 gpo, ge(mdc)
38mpp18 18 gpio, ge(mdio)
39mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
40mpp20 20 gpo, ge0(txd4), ge1(txd0)
41mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
42mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
43mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
44mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
45mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
46mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
47mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
48mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
49mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
50mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
51mpp31 31 gpio, tclk, ge0(txerr)
52mpp32 32 gpio, spi0(cs0)
53mpp33 33 gpio, dev(bootcs), spi0(cs0)
54mpp34 34 gpo, dev(wen0), spi0(mosi)
55mpp35 35 gpo, dev(oen), spi0(sck)
56mpp36 36 gpo, dev(a1), spi0(miso)
57mpp37 37 gpo, dev(a0), sata0(prsnt)
58mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
59mpp39 39 gpo, dev(ad0), audio(spdifo)
60mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
61mpp41 41 gpio, dev(ad2), uart1(rxd)
62mpp42 42 gpo, dev(ad3), uart1(txd)
63mpp43 43 gpo, dev(ad4), audio(bclk)
64mpp44 44 gpo, dev(ad5), audio(mclk)
65mpp45 45 gpo, dev(ad6), audio(lrclk)
66mpp46 46 gpo, dev(ad7), audio(sdo)
67mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
68mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
69 spi0(cs1)
70mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
71 audio(spdifi)
72mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
73 audio(rmclk)
74mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
75mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
76mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
77 pcie(clkreq1)
78mpp54 54 gpo, dev(ad15), tdm(dtx)
79mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
80 sata0(prsnt)
81mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
82 pcie(clkreq0), spi1(cs1)
83mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
84 audio(sdo)
85mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
86 uart0(rts)
87mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
88mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
89 audio(sdi)
90mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
91mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
92 audio(mclk), uart0(cts)
93mpp63 63 gpo, spi0(sck), tclk
94mpp64 64 gpio, spi0(miso), spi0-1(cs1)
95mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
deleted file mode 100644
index bfa0a2e5e0c..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ /dev/null
@@ -1,100 +0,0 @@
1* Marvell Armada XP SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9
10This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
11
12Available mpp pins/groups and functions:
13Note: brackets (x) are not part of the mpp name for marvell,function and given
14only for more detailed description in this document.
15
16* Marvell Armada XP (all variants)
17
18name pins functions
19================================================================================
20mpp0 0 gpio, ge0(txclko), lcd(d0)
21mpp1 1 gpio, ge0(txd0), lcd(d1)
22mpp2 2 gpio, ge0(txd1), lcd(d2)
23mpp3 3 gpio, ge0(txd2), lcd(d3)
24mpp4 4 gpio, ge0(txd3), lcd(d4)
25mpp5 5 gpio, ge0(txctl), lcd(d5)
26mpp6 6 gpio, ge0(rxd0), lcd(d6)
27mpp7 7 gpio, ge0(rxd1), lcd(d7)
28mpp8 8 gpio, ge0(rxd2), lcd(d8)
29mpp9 9 gpio, ge0(rxd3), lcd(d9)
30mpp10 10 gpio, ge0(rxctl), lcd(d10)
31mpp11 11 gpio, ge0(rxclk), lcd(d11)
32mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
33mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
34mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
35mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
36mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
37mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
38mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
39mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
40mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
41mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
42mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
43mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
44mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
45mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
46mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
47mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
48mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
49mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
50mpp30 30 gpio, tdm(int1), sd0(clk)
51mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
52mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
53mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
54mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
55mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
56mpp36 36 gpio, spi(mosi)
57mpp37 37 gpio, spi(miso)
58mpp38 38 gpio, spi(sck)
59mpp39 39 gpio, spi(cs0)
60mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
61 pcie(clkreq0)
62mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
63 pcie(clkreq1)
64mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
65 vdd(cpu0-pd)
66mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
67 vdd(cpu2-3-pd){1}
68mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
69 mem(bat)
70mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
71mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
72mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
73 ref(clkout)
74mpp48 48 gpio, tclk, dev(burst/last)
75
76* Marvell Armada XP (mv78260 and mv78460 only)
77
78name pins functions
79================================================================================
80mpp49 49 gpio, dev(we3)
81mpp50 50 gpio, dev(we2)
82mpp51 51 gpio, dev(ad16)
83mpp52 52 gpio, dev(ad17)
84mpp53 53 gpio, dev(ad18)
85mpp54 54 gpio, dev(ad19)
86mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
87mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
88mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
89mpp58 58 gpio, dev(ad23)
90mpp59 59 gpio, dev(ad24)
91mpp60 60 gpio, dev(ad25)
92mpp61 61 gpio, dev(ad26)
93mpp62 62 gpio, dev(ad27)
94mpp63 63 gpio, dev(ad28)
95mpp64 64 gpio, dev(ad29)
96mpp65 65 gpio, dev(ad30)
97mpp66 66 gpio, dev(ad31)
98
99Notes:
100* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
deleted file mode 100644
index a648aaad611..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ /dev/null
@@ -1,72 +0,0 @@
1* Marvell Dove SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,dove-pinctrl"
8- clocks: (optional) phandle of pdma clock
9
10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document.
13
14name pins functions
15================================================================================
16mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
17mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
18mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
19 uart1(rts)
20mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
21 uart1(cts), lcd-spi(cs1)
22mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
23mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
24mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
25mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
26mpp8 8 gpio, pmu, watchdog(rstout)
27mpp9 9 gpio, pmu, pex1(clkreq)
28mpp10 10 gpio, pmu, ssp(sclk)
29mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
30 sdio1(ledctrl), pex0(clkreq)
31mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
32mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
33 ssp(extclk)
34mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
35mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
36mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
37mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
38 ac97-1(sysclko)
39mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
40mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
41mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
42 ac97(sysclko)
43mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
44 uart1(cts), ssp(sfrm)
45mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
46 lcd-spi(mosi), uart1(cts), ssp(txd)
47mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
48 lcd-spi(sck), ssp(sclk)
49mpp_camera 24-39 gpio, camera
50mpp_sdio0 40-45 gpio, sdio0
51mpp_sdio1 46-51 gpio, sdio1
52mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
53 ssp/twsi
54mpp_spi0 58-61 gpio, spi0
55mpp_uart1 62-63 gpio, uart1
56mpp_nand 64-71 gpo, nand
57audio0 - i2s, ac97
58twsi - none, opt1, opt2, opt3
59
60Notes:
61* group "mpp_audio1" allows the following functions and gpio pins:
62 - gpio : gpio on pins 52-57
63 - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
64 - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
65 - spdifo : spdifo on pin 57, gpio on pins 52-55
66 - twsi : twsi on pins 56,57, gpio on pins 52-55
67 - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
68 - ssp : ssp on pins 52-55, gpio on pins 56,57
69 - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
70* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
71 audio0 pins.
72* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
deleted file mode 100644
index 95daf6335c3..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ /dev/null
@@ -1,318 +0,0 @@
1* Marvell Kirkwood SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10 "marvell,98dx4122-pinctrl"
11
12This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
14
15Available mpp pins/groups and functions:
16Note: brackets (x) are not part of the mpp name for marvell,function and given
17only for more detailed description in this document.
18
19* Marvell Kirkwood 88f6180
20
21name pins functions
22================================================================================
23mpp0 0 gpio, nand(io2), spi(cs)
24mpp1 1 gpo, nand(io3), spi(mosi)
25mpp2 2 gpo, nand(io4), spi(sck)
26mpp3 3 gpo, nand(io5), spi(miso)
27mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
28mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
29mpp6 6 sysrst(out), spi(mosi), ptp(trig)
30mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
31mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
32 mii(col)
33mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
34 mii(crs)
35mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
36mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
37 ptp-2(trig)
38mpp12 12 gpo, sdio(clk)
39mpp13 13 gpio, sdio(cmd), uart1(txd)
40mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
41mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
42mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
43mpp17 17 gpio, sdio(d3)
44mpp18 18 gpo, nand(io0)
45mpp19 19 gpo, nand(io1)
46mpp20 20 gpio, mii(rxerr)
47mpp21 21 gpio, audio(spdifi)
48mpp22 22 gpio, audio(spdifo)
49mpp23 23 gpio, audio(rmclk)
50mpp24 24 gpio, audio(bclk)
51mpp25 25 gpio, audio(sdo)
52mpp26 26 gpio, audio(lrclk)
53mpp27 27 gpio, audio(mclk)
54mpp28 28 gpio, audio(sdi)
55mpp29 29 gpio, audio(extclk)
56
57* Marvell Kirkwood 88f6190
58
59name pins functions
60================================================================================
61mpp0 0 gpio, nand(io2), spi(cs)
62mpp1 1 gpo, nand(io3), spi(mosi)
63mpp2 2 gpo, nand(io4), spi(sck)
64mpp3 3 gpo, nand(io5), spi(miso)
65mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
66mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
67mpp6 6 sysrst(out), spi(mosi), ptp(trig)
68mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
69mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
70 mii(col), mii-1(rxerr)
71mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
72 mii(crs), sata0(prsnt)
73mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
74mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
75 ptp-2(trig), sata0(act)
76mpp12 12 gpo, sdio(clk)
77mpp13 13 gpio, sdio(cmd), uart1(txd)
78mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
79mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
80mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
81mpp17 17 gpio, sdio(d3), sata0(prsnt)
82mpp18 18 gpo, nand(io0)
83mpp19 19 gpo, nand(io1)
84mpp20 20 gpio, ge1(txd0)
85mpp21 21 gpio, ge1(txd1), sata0(act)
86mpp22 22 gpio, ge1(txd2)
87mpp23 23 gpio, ge1(txd3), sata0(prsnt)
88mpp24 24 gpio, ge1(rxd0)
89mpp25 25 gpio, ge1(rxd1)
90mpp26 26 gpio, ge1(rxd2)
91mpp27 27 gpio, ge1(rxd3)
92mpp28 28 gpio, ge1(col)
93mpp29 29 gpio, ge1(txclk)
94mpp30 30 gpio, ge1(rxclk)
95mpp31 31 gpio, ge1(rxclk)
96mpp32 32 gpio, ge1(txclko)
97mpp33 33 gpo, ge1(txclk)
98mpp34 34 gpio, ge1(txen)
99mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
100
101* Marvell Kirkwood 88f6192
102
103name pins functions
104================================================================================
105mpp0 0 gpio, nand(io2), spi(cs)
106mpp1 1 gpo, nand(io3), spi(mosi)
107mpp2 2 gpo, nand(io4), spi(sck)
108mpp3 3 gpo, nand(io5), spi(miso)
109mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
110mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
111mpp6 6 sysrst(out), spi(mosi), ptp(trig)
112mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
113mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
114 mii(col), mii-1(rxerr), sata1(prsnt)
115mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
116 mii(crs), sata0(prsnt)
117mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
118mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
119 ptp-2(trig), sata0(act)
120mpp12 12 gpo, sdio(clk)
121mpp13 13 gpio, sdio(cmd), uart1(txd)
122mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
123mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
124mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
125 sata1(act)
126mpp17 17 gpio, sdio(d3), sata0(prsnt)
127mpp18 18 gpo, nand(io0)
128mpp19 19 gpo, nand(io1)
129mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
130 sata1(act)
131mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
132 audio(spdifo)
133mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
134 sata1(prsnt)
135mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
136 audio(bclk)
137mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
138mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
139mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
140mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
141mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
142mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
143mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
144mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
145mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
146mpp33 33 gpo, ge1(txclk), tdm(drx)
147mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
148mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
149
150* Marvell Kirkwood 88f6281
151
152name pins functions
153================================================================================
154mpp0 0 gpio, nand(io2), spi(cs)
155mpp1 1 gpo, nand(io3), spi(mosi)
156mpp2 2 gpo, nand(io4), spi(sck)
157mpp3 3 gpo, nand(io5), spi(miso)
158mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
159mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
160mpp6 6 sysrst(out), spi(mosi), ptp(trig)
161mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
162mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
163 mii(col), mii-1(rxerr), sata1(prsnt)
164mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
165 mii(crs), sata0(prsnt)
166mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
167mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
168 ptp-2(trig), sata0(act)
169mpp12 12 gpio, sdio(clk)
170mpp13 13 gpio, sdio(cmd), uart1(txd)
171mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
172mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
173mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
174 sata1(act)
175mpp17 17 gpio, sdio(d3), sata0(prsnt)
176mpp18 18 gpo, nand(io0)
177mpp19 19 gpo, nand(io1)
178mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
179 sata1(act)
180mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
181 audio(spdifo)
182mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
183 sata1(prsnt)
184mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
185 audio(bclk)
186mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
187mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
188mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
189mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
190mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
191mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
192mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
193mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
194mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
195mpp33 33 gpo, ge1(txclk), tdm(drx)
196mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
197mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
198mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
199mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
200mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
201mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
202mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
203mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
204mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
205mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
206mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
207mpp45 45 gpio, ts(mp9), tdm(pclk)
208mpp46 46 gpio, ts(mp10), tdm(fs)
209mpp47 47 gpio, ts(mp11), tdm(drx)
210mpp48 48 gpio, ts(mp12), tdm(dtx)
211mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
212
213* Marvell Kirkwood 88f6282
214
215name pins functions
216================================================================================
217mpp0 0 gpio, nand(io2), spi(cs)
218mpp1 1 gpo, nand(io3), spi(mosi)
219mpp2 2 gpo, nand(io4), spi(sck)
220mpp3 3 gpo, nand(io5), spi(miso)
221mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
222mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
223mpp6 6 sysrst(out), spi(mosi)
224mpp7 7 gpo, spi(cs), lcd(pwm)
225mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
226 mii-1(rxerr), sata1(prsnt)
227mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
228 sata0(prsnt)
229mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
230mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
231mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
232mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
233mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
234 audio(spdifi), audio-1(sdi)
235mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
236 spi(cs)
237mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
238 sata1(act), lcd(extclk)
239mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
240mpp18 18 gpo, nand(io0), pex(clkreq)
241mpp19 19 gpo, nand(io1)
242mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
243 sata1(act), lcd(d0)
244mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
245 audio(spdifo), lcd(d1)
246mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
247 sata1(prsnt), lcd(d2)
248mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
249 audio(bclk), lcd(d3)
250mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
251 lcd(d4)
252mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
253 lcd(d5)
254mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
255 lcd(d6)
256mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
257 lcd(d7)
258mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
259 lcd(d8)
260mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
261mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
262mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
263mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
264mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
265mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
266mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
267 lcd(d15)
268mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
269mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
270mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
271mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
272mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
273mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
274mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
275mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
276mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
277mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
278mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
279mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
280mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
281mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
282
283* Marvell Bobcat 98dx4122
284
285name pins functions
286================================================================================
287mpp0 0 gpio, nand(io2), spi(cs)
288mpp1 1 gpo, nand(io3), spi(mosi)
289mpp2 2 gpo, nand(io4), spi(sck)
290mpp3 3 gpo, nand(io5), spi(miso)
291mpp4 4 gpio, nand(io6), uart0(rxd)
292mpp5 5 gpo, nand(io7), uart0(txd)
293mpp6 6 sysrst(out), spi(mosi)
294mpp7 7 gpo, pex(rsto), spi(cs)
295mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts)
296mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts)
297mpp10 10 gpo, spi(sck), uart0(txd)
298mpp11 11 gpio, spi(miso), uart0(rxd)
299mpp13 13 gpio, uart1(txd)
300mpp14 14 gpio, uart1(rxd)
301mpp15 15 gpio, uart0(rts)
302mpp16 16 gpio, uart0(cts)
303mpp18 18 gpo, nand(io0)
304mpp19 19 gpo, nand(io1)
305mpp34 34 gpio
306mpp35 35 gpio
307mpp36 36 gpio
308mpp37 37 gpio
309mpp38 38 gpio
310mpp39 39 gpio
311mpp40 40 gpio
312mpp41 41 gpio
313mpp42 42 gpio
314mpp43 43 gpio
315mpp44 44 gpio
316mpp45 45 gpio
317mpp49 49 gpio
318
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
deleted file mode 100644
index 0a26c3aa4e6..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ /dev/null
@@ -1,46 +0,0 @@
1* Marvell SoC pinctrl core driver for mpp
2
3The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4(mpp) to a specific function. For each SoC family there is a SoC specific
5driver using this core driver.
6
7Please refer to pinctrl-bindings.txt in this directory for details of the
8common pinctrl bindings used by client devices, including the meaning of the
9phrase "pin configuration node".
10
11A Marvell SoC pin configuration node is a node of a group of pins which can
12be used for a specific device or function. Each node requires one or more
13mpp pins or group of pins and a mpp function common to all pins.
14
15Required properties for pinctrl driver:
16- compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
18
19Required properties for pin configuration node:
20- marvell,pins: string array of mpp pins or group of pins to be muxed.
21- marvell,function: string representing a function to mux to for all
22 marvell,pins given in this pin configuration node. The function has to be
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
24 valid pin/pin group names and available function names for each SoC.
25
26Examples:
27
28uart1: serial@12100 {
29 compatible = "ns16550a";
30 reg = <0x12100 0x100>;
31 reg-shift = <2>;
32 interrupts = <7>;
33
34 pinctrl-0 = <&pmx_uart1_sw>;
35 pinctrl-names = "default";
36};
37
38pinctrl: pinctrl@d0200 {
39 compatible = "marvell,dove-pinctrl";
40 reg = <0xd0200 0x20>;
41
42 pmx_uart1_sw: pmx-uart1-sw {
43 marvell,pins = "mpp_uart1";
44 marvell,function = "uart1";
45 };
46};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
deleted file mode 100644
index 683fde93c4f..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
+++ /dev/null
@@ -1,132 +0,0 @@
1NVIDIA Tegra20 pinmux controller
2
3Required properties:
4- compatible: "nvidia,tegra20-pinmux"
5- reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12Tegra's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, tristate, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function or tristate parameter. For this
26reason, even seemingly boolean values are actually tristates in this binding:
27unspecified, off, or on. Unspecified is represented as an absent property,
28and off/on are represented as integer values 0 and 1.
29
30Required subnode-properties:
31- nvidia,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- nvidia,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below. See the Tegra
37 TRM to determine which are valid for each pin or group.
38- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
39 0: none, 1: down, 2: up.
40- nvidia,tristate: Integer.
41 0: drive, 1: tristate.
42- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
43 0: no, 1: yes.
44- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
45 0: no, 1: yes.
46- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
47 most power. Controls the drive power or current. See "Low Power Mode"
48 or "LPMD1" and "LPMD0" in the Tegra TRM.
49- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
50 The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
51 Tegra TRM.
52- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
53 The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
54 Tegra TRM.
55- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
56 fastest. The range of valid values depends on the pingroup. See
57 "DRVDN_SLWR" in the Tegra TRM.
58- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
59 fastest. The range of valid values depends on the pingroup. See
60 "DRVUP_SLWF" in the Tegra TRM.
61
62Note that many of these properties are only valid for certain specific pins
63or groups. See the Tegra TRM and various pinmux spreadsheets for complete
64details regarding which groups support which functionality. The Linux pinctrl
65driver may also be a useful reference, since it consolidates, disambiguates,
66and corrects data from all those sources.
67
68Valid values for pin and group names are:
69
70 mux groups:
71
72 These all support nvidia,function, nvidia,tristate, and many support
73 nvidia,pull.
74
75 ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
76 ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
77 gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
78 ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
79 ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
80 lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
81 owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
82 spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
83 uca, ucb, uda.
84
85 tristate groups:
86
87 These only support nvidia,pull.
88
89 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
90 ld19_18, ld21_20, ld23_22.
91
92 drive groups:
93
94 With some exceptions, these support nvidia,high-speed-mode,
95 nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
96 nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
97
98 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
99 drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
100 drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
101 drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
102 drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
103 drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
104 drive_uda.
105
106Example:
107
108 pinctrl@70000000 {
109 compatible = "nvidia,tegra20-pinmux";
110 reg = < 0x70000014 0x10 /* Tri-state registers */
111 0x70000080 0x20 /* Mux registers */
112 0x700000a0 0x14 /* Pull-up/down registers */
113 0x70000868 0xa8 >; /* Pad control registers */
114 };
115
116Example board file extract:
117
118 pinctrl@70000000 {
119 sdio4_default: sdio4_default {
120 atb {
121 nvidia,pins = "atb", "gma", "gme";
122 nvidia,function = "sdio4";
123 nvidia,pull = <0>;
124 nvidia,tristate = <0>;
125 };
126 };
127 };
128
129 sdhci@c8000600 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&sdio4_default>;
132 };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
deleted file mode 100644
index 6f426ed7009..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
+++ /dev/null
@@ -1,132 +0,0 @@
1NVIDIA Tegra30 pinmux controller
2
3The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
4as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
5that binding as a baseline, and only documents the differences between the
6two bindings.
7
8Required properties:
9- compatible: "nvidia,tegra30-pinmux"
10- reg: Should contain the register physical address and length for each of
11 the pad control and mux registers.
12
13Tegra30 adds the following optional properties for pin configuration subnodes:
14- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16- nvidia,lock: Integer. Lock the pin configuration against further changes
17 until reset. 0: no, 1: yes.
18- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
19
20As with Tegra20, see the Tegra TRM for complete details regarding which groups
21support which functionality.
22
23Valid values for pin and group names are:
24
25 per-pin mux groups:
26
27 These all support nvidia,function, nvidia,tristate, nvidia,pull,
28 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
29 nvidia,io-reset.
30
31 clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
32 dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
33 gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
34 sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
35 uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
36 lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
37 sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
38 lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
39 lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
40 lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
41 gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
42 gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
43 gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
44 gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
45 gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
46 gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
47 uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
48 gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
49 vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
50 vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
51 lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
52 dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
53 lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
54 ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
55 ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
56 dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
57 kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
58 kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
59 kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
60 kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
61 kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
62 vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
63 sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
64 pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
65 lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
66 clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
67 spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
68 spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
69 sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
70 sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
71 sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
72 sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
73 sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
74 cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
75 cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
76 clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
77 pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
78 pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
79 pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
80 clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
81 pwr_int_n.
82
83 drive groups:
84
85 These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
86 nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
87 support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
88
89 ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
90 dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
91 gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
92 uart3, uda, vi1.
93
94Example:
95
96 pinctrl@70000000 {
97 compatible = "nvidia,tegra30-pinmux";
98 reg = < 0x70000868 0xd0 /* Pad control registers */
99 0x70003000 0x3e0 >; /* Mux registers */
100 };
101
102Example board file extract:
103
104 pinctrl@70000000 {
105 sdmmc4_default: pinmux {
106 sdmmc4_clk_pcc4 {
107 nvidia,pins = "sdmmc4_clk_pcc4",
108 "sdmmc4_rst_n_pcc3";
109 nvidia,function = "sdmmc4";
110 nvidia,pull = <0>;
111 nvidia,tristate = <0>;
112 };
113 sdmmc4_dat0_paa0 {
114 nvidia,pins = "sdmmc4_dat0_paa0",
115 "sdmmc4_dat1_paa1",
116 "sdmmc4_dat2_paa2",
117 "sdmmc4_dat3_paa3",
118 "sdmmc4_dat4_paa4",
119 "sdmmc4_dat5_paa5",
120 "sdmmc4_dat6_paa6",
121 "sdmmc4_dat7_paa7";
122 nvidia,function = "sdmmc4";
123 nvidia,pull = <2>;
124 nvidia,tristate = <0>;
125 };
126 };
127 };
128
129 sdhci@78000400 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&sdmmc4_default>;
132 };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
deleted file mode 100644
index c95ea8278f8..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ /dev/null
@@ -1,128 +0,0 @@
1== Introduction ==
2
3Hardware modules that control pin multiplexing or configuration parameters
4such as pull-up/down, tri-state, drive-strength etc are designated as pin
5controllers. Each pin controller must be represented as a node in device tree,
6just like any other hardware module.
7
8Hardware modules whose signals are affected by pin configuration are
9designated client devices. Again, each client device must be represented as a
10node in device tree, just like any other hardware module.
11
12For a client device to operate correctly, certain pin controllers must
13set up certain specific pin configurations. Some client devices need a
14single static pin configuration, e.g. set up during initialization. Others
15need to reconfigure pins at run-time, for example to tri-state pins when the
16device is inactive. Hence, each client device can define a set of named
17states. The number and names of those states is defined by the client device's
18own binding.
19
20The common pinctrl bindings defined in this file provide an infrastructure
21for client device device tree nodes to map those state names to the pin
22configuration used by those states.
23
24Note that pin controllers themselves may also be client devices of themselves.
25For example, a pin controller may set up its own "active" state when the
26driver loads. This would allow representing a board's static pin configuration
27in a single place, rather than splitting it across multiple client device
28nodes. The decision to do this or not somewhat rests with the author of
29individual board device tree files, and any requirements imposed by the
30bindings for the individual client devices in use by that board, i.e. whether
31they require certain specific named states for dynamic pin configuration.
32
33== Pinctrl client devices ==
34
35For each client device individually, every pin state is assigned an integer
36ID. These numbers start at 0, and are contiguous. For each state ID, a unique
37property exists to define the pin configuration. Each state may also be
38assigned a name. When names are used, another property exists to map from
39those names to the integer IDs.
40
41Each client device's own binding determines the set of states the must be
42defined in its device tree node, and whether to define the set of state
43IDs that must be provided, or whether to define the set of state names that
44must be provided.
45
46Required properties:
47pinctrl-0: List of phandles, each pointing at a pin configuration
48 node. These referenced pin configuration nodes must be child
49 nodes of the pin controller that they configure. Multiple
50 entries may exist in this list so that multiple pin
51 controllers may be configured, or so that a state may be built
52 from multiple nodes for a single pin controller, each
53 contributing part of the overall configuration. See the next
54 section of this document for details of the format of these
55 pin configuration nodes.
56
57 In some cases, it may be useful to define a state, but for it
58 to be empty. This may be required when a common IP block is
59 used in an SoC either without a pin controller, or where the
60 pin controller does not affect the HW module in question. If
61 the binding for that IP block requires certain pin states to
62 exist, they must still be defined, but may be left empty.
63
64Optional properties:
65pinctrl-1: List of phandles, each pointing at a pin configuration
66 node within a pin controller.
67...
68pinctrl-n: List of phandles, each pointing at a pin configuration
69 node within a pin controller.
70pinctrl-names: The list of names to assign states. List entry 0 defines the
71 name for integer state ID 0, list entry 1 for state ID 1, and
72 so on.
73
74For example:
75
76 /* For a client device requiring named states */
77 device {
78 pinctrl-names = "active", "idle";
79 pinctrl-0 = <&state_0_node_a>;
80 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
81 };
82
83 /* For the same device if using state IDs */
84 device {
85 pinctrl-0 = <&state_0_node_a>;
86 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
87 };
88
89 /*
90 * For an IP block whose binding supports pin configuration,
91 * but in use on an SoC that doesn't have any pin control hardware
92 */
93 device {
94 pinctrl-names = "active", "idle";
95 pinctrl-0 = <>;
96 pinctrl-1 = <>;
97 };
98
99== Pin controller devices ==
100
101Pin controller devices should contain the pin configuration nodes that client
102devices reference.
103
104For example:
105
106 pincontroller {
107 ... /* Standard DT properties for the device itself elided */
108
109 state_0_node_a {
110 ...
111 };
112 state_1_node_a {
113 ...
114 };
115 state_1_node_b {
116 ...
117 };
118 }
119
120The contents of each of those pin configuration child nodes is defined
121entirely by the binding for the individual pin controller device. There
122exists no common standard for this content.
123
124The pin configuration nodes need not be direct children of the pin controller
125device; they may be grandchildren, for example. Whether this is legal, and
126whether there is any interaction between the child and intermediate parent
127nodes, is again defined entirely by the binding for the individual pin
128controller device.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
deleted file mode 100644
index 2c81e45f137..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ /dev/null
@@ -1,128 +0,0 @@
1One-register-per-pin type device tree based pinctrl driver
2
3Required properties:
4- compatible : "pinctrl-single"
5
6- reg : offset and length of the register set for the mux registers
7
8- pinctrl-single,register-width : pinmux register access width in bits
9
10- pinctrl-single,function-mask : mask of allowed pinmux function bits
11 in the pinmux register
12
13Optional properties:
14- pinctrl-single,function-off : function off mode for disabled state if
15 available and same for all registers; if not specified, disabling of
16 pin functions is ignored
17- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
18 more than one pin
19
20This driver assumes that there is only one register for each pin (unless the
21pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
22specified in the pinctrl-bindings.txt document in this directory.
23
24The pin configuration nodes for pinctrl-single are specified as pinctrl
25register offset and value pairs using pinctrl-single,pins. Only the bits
26specified in pinctrl-single,function-mask are updated. For example, setting
27a pin for a device could be done with:
28
29 pinctrl-single,pins = <0xdc 0x118>;
30
31Where 0xdc is the offset from the pinctrl register base address for the
32device pinctrl register, and 0x118 contains the desired value of the
33pinctrl register. See the device example and static board pins example
34below for more information.
35
36In case when one register changes more than one pin's mux the
37pinctrl-single,bits need to be used which takes three parameters:
38
39 pinctrl-single,bits = <0xdc 0x18, 0xff>;
40
41Where 0xdc is the offset from the pinctrl register base address for the
42device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
43be used when applying this change to the register.
44
45Example:
46
47/* SoC common file */
48
49/* first controller instance for pins in core domain */
50pmx_core: pinmux@4a100040 {
51 compatible = "pinctrl-single";
52 reg = <0x4a100040 0x0196>;
53 #address-cells = <1>;
54 #size-cells = <0>;
55 pinctrl-single,register-width = <16>;
56 pinctrl-single,function-mask = <0xffff>;
57};
58
59/* second controller instance for pins in wkup domain */
60pmx_wkup: pinmux@4a31e040 {
61 compatible = "pinctrl-single;
62 reg = <0x4a31e040 0x0038>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 pinctrl-single,register-width = <16>;
66 pinctrl-single,function-mask = <0xffff>;
67};
68
69control_devconf0: pinmux@48002274 {
70 compatible = "pinctrl-single";
71 reg = <0x48002274 4>; /* Single register */
72 #address-cells = <1>;
73 #size-cells = <0>;
74 pinctrl-single,bit-per-mux;
75 pinctrl-single,register-width = <32>;
76 pinctrl-single,function-mask = <0x5F>;
77};
78
79/* board specific .dts file */
80
81&pmx_core {
82
83 /*
84 * map all board specific static pins enabled by the pinctrl driver
85 * itself during the boot (or just set them up in the bootloader)
86 */
87 pinctrl-names = "default";
88 pinctrl-0 = <&board_pins>;
89
90 board_pins: pinmux_board_pins {
91 pinctrl-single,pins = <
92 0x6c 0xf
93 0x6e 0xf
94 0x70 0xf
95 0x72 0xf
96 >;
97 };
98
99 /* map uart2 pins */
100 uart2_pins: pinmux_uart2_pins {
101 pinctrl-single,pins = <
102 0xd8 0x118
103 0xda 0
104 0xdc 0x118
105 0xde 0
106 >;
107 };
108};
109
110&control_devconf0 {
111 mcbsp1_pins: pinmux_mcbsp1_pins {
112 pinctrl-single,bits = <
113 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
114 >;
115 };
116
117 mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
118 pinctrl-single,bits = <
119 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
120 >;
121 };
122
123};
124
125&uart2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&uart2_pins>;
128};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
deleted file mode 100644
index c596a6ad328..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
+++ /dev/null
@@ -1,47 +0,0 @@
1CSR SiRFprimaII pinmux controller
2
3Required properties:
4- compatible : "sirf,prima2-pinctrl"
5- reg : Address range of the pinctrl registers
6- interrupts : Interrupts used by every GPIO group
7- gpio-controller : Indicates this device is a GPIO controller
8- interrupt-controller : Marks the device node as an interrupt controller
9Optional properties:
10- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
12
13Please refer to pinctrl-bindings.txt in this directory for details of the common
14pinctrl bindings used by client devices.
15
16SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes.
17Each of these subnodes represents some desired configuration for a group of pins.
18
19Required subnode-properties:
20- sirf,pins : An array of strings. Each string contains the name of a group.
21- sirf,function: A string containing the name of the function to mux to the
22 group.
23
24 Valid values for group and function names can be found from looking at the
25 group and function arrays in driver files:
26 drivers/pinctrl/pinctrl-sirf.c
27
28For example, pinctrl might have subnodes like the following:
29 uart2_pins_a: uart2@0 {
30 uart {
31 sirf,pins = "uart2grp";
32 sirf,function = "uart2";
33 };
34 };
35 uart2_noflow_pins_a: uart2@1 {
36 uart {
37 sirf,pins = "uart2_nostreamctrlgrp";
38 sirf,function = "uart2_nostreamctrl";
39 };
40 };
41
42For a specific board, if it wants to use uart2 without hardware flow control,
43it can add the following to its board-specific .dts file.
44uart2: uart@0xb0070000 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&uart2_noflow_pins_a>;
47}
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
deleted file mode 100644
index b4480d5c3ac..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
+++ /dev/null
@@ -1,155 +0,0 @@
1ST Microelectronics, SPEAr pinmux controller
2
3Required properties:
4- compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9- reg : Address range of the pinctrl registers
10- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
14 - PHOTO_FRAME_MODE : <2>
15 - LEND_IP_PHONE_MODE : <3>
16 - HEND_IP_PHONE_MODE : <4>
17 - LEND_WIFI_PHONE_MODE : <5>
18 - HEND_WIFI_PHONE_MODE : <6>
19 - ATA_PABX_WI2S_MODE : <7>
20 - ATA_PABX_I2S_MODE : <8>
21 - CAML_LCDW_MODE : <9>
22 - CAMU_LCD_MODE : <10>
23 - CAMU_WLCD_MODE : <11>
24 - CAML_LCD_MODE : <12>
25 - Its values for SPEAr320:
26 - AUTO_NET_SMII_MODE : <0>
27 - AUTO_NET_MII_MODE : <1>
28 - AUTO_EXP_MODE : <2>
29 - SMALL_PRINTERS_MODE : <3>
30 - EXTENDED_MODE : <4>
31
32Please refer to pinctrl-bindings.txt in this directory for details of the common
33pinctrl bindings used by client devices.
34
35SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
36of these subnodes represents muxing for a pin, a group, or a list of pins or
37groups.
38
39The name of each subnode is not important; all subnodes should be enumerated
40and processed purely based on their content.
41
42Required subnode-properties:
43- st,pins : An array of strings. Each string contains the name of a pin or
44 group.
45- st,function: A string containing the name of the function to mux to the pin or
46 group. See the SPEAr's TRM to determine which are valid for each pin or group.
47
48 Valid values for group and function names can be found from looking at the
49 group and function arrays in driver files:
50 drivers/pinctrl/spear/pinctrl-spear3*0.c
51
52Valid values for group names are:
53For All SPEAr3xx machines:
54 "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
55 "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
56 "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
57 "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
58
59For SPEAr300 machines:
60 "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
61 "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
62 "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
63 "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
64
65For SPEAr310 machines:
66 "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
67 "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
68
69For SPEAr320 machines:
70 "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
71 "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
72 "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
73 "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
74 "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
75 "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
76 "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
77 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
78 "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
79 "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
80 "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
81 "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
82 "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
83 "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
84 "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
85 "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
86 "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
87 "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
88 "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
89 "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
90 "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
91 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
92 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
93
94For SPEAr1310 machines:
95 "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
96 "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
97 "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
98 "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
99 "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
100 "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
101 "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
102 "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
103 "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
104 "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
105 "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
106 "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
107 "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
108 "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
109 "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
110 "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
111
112For SPEAr1340 machines:
113 "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
114 "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
115 "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
116 "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
117 "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
118 "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
119 "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
120 "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
121 "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
122 "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
123 "miphy_dbg_grp", "pcie_grp", "sata_grp"
124
125Valid values for function names are:
126For All SPEAr3xx machines:
127 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
128 "uart0", "timer_0_1", "timer_2_3"
129
130For SPEAr300 machines:
131 "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
132
133For SPEAr310 machines:
134 "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
135 "rs485_1", "tdm"
136
137For SPEAr320 machines:
138 "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
139 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
140 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
141 "mii0_1", "i2c1", "i2c2"
142
143
144For SPEAr1310 machines:
145 "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
146 "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
147 "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
148 "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
149 "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
150
151For SPEAr1340 machines:
152 "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
153 "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
154 "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
155 "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
deleted file mode 100644
index e97a27856b2..00000000000
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ /dev/null
@@ -1,265 +0,0 @@
1Samsung GPIO and Pin Mux/Config controller
2
3Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
4controller. It controls the input/output settings on the available pads/pins
5and also provides ability to multiplex and configure the output of various
6on-chip controllers onto these pads.
7
8Required Properties:
9- compatible: should be one of the following.
10 - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
11 - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
12 - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
13
14- reg: Base address of the pin controller hardware module and length of
15 the address space it occupies.
16
17- Pin banks as child nodes: Pin banks of the controller are represented by child
18 nodes of the controller node. Bank name is taken from name of the node. Each
19 bank node must contain following properties:
20
21 - gpio-controller: identifies the node as a gpio controller and pin bank.
22 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
23 binding is used, the amount of cells must be specified as 2. See generic
24 GPIO binding documentation for description of particular cells.
25
26- Pin mux/config groups as child nodes: The pin mux (selecting pin function
27 mode) and pin config (pull up/down, driver strength) settings are represented
28 as child nodes of the pin-controller node. There should be atleast one
29 child node and there is no limit on the count of these child nodes.
30
31 The child node should contain a list of pin(s) on which a particular pin
32 function selection or pin configuration (or both) have to applied. This
33 list of pins is specified using the property name "samsung,pins". There
34 should be atleast one pin specfied for this property and there is no upper
35 limit on the count of pins that can be specified. The pins are specified
36 using pin names which are derived from the hardware manual of the SoC. As
37 an example, the pins in GPA0 bank of the pin controller can be represented
38 as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
39 The format of the pin names should be (as per the hardware manual)
40 "[pin bank name]-[pin number within the bank]".
41
42 The pin function selection that should be applied on the pins listed in the
43 child node is specified using the "samsung,pin-function" property. The value
44 of this property that should be applied to each of the pins listed in the
45 "samsung,pins" property should be picked from the hardware manual of the SoC
46 for the specified pin group. This property is optional in the child node if
47 no specific function selection is desired for the pins listed in the child
48 node. The value of this property is used as-is to program the pin-controller
49 function selector register of the pin-bank.
50
51 The child node can also optionally specify one or more of the pin
52 configuration that should be applied on all the pins listed in the
53 "samsung,pins" property of the child node. The following pin configuration
54 properties are supported.
55
56 - samsung,pin-pud: Pull up/down configuration.
57 - samsung,pin-drv: Drive strength configuration.
58 - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
59 - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
60
61 The values specified by these config properties should be derived from the
62 hardware manual and these values are programmed as-is into the pin
63 pull up/down and driver strength register of the pin-controller.
64
65 Note: A child should include atleast a pin function selection property or
66 pin configuration property (one or more) or both.
67
68 The client nodes that require a particular pin function selection and/or
69 pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
70 file.
71
72External GPIO and Wakeup Interrupts:
73
74The controller supports two types of external interrupts over gpio. The first
75is the external gpio interrupt and second is the external wakeup interrupts.
76The difference between the two is that the external wakeup interrupts can be
77used as system wakeup events.
78
79A. External GPIO Interrupts: For supporting external gpio interrupts, the
80 following properties should be specified in the pin-controller device node.
81
82 - interrupt-parent: phandle of the interrupt parent to which the external
83 GPIO interrupts are forwarded to.
84 - interrupts: interrupt specifier for the controller. The format and value of
85 the interrupt specifier depends on the interrupt parent for the controller.
86
87 In addition, following properties must be present in node of every bank
88 of pins supporting GPIO interrupts:
89
90 - interrupt-controller: identifies the controller node as interrupt-parent.
91 - #interrupt-cells: the value of this property should be 2.
92 - First Cell: represents the external gpio interrupt number local to the
93 external gpio interrupt space of the controller.
94 - Second Cell: flags to identify the type of the interrupt
95 - 1 = rising edge triggered
96 - 2 = falling edge triggered
97 - 3 = rising and falling edge triggered
98 - 4 = high level triggered
99 - 8 = low level triggered
100
101B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
102 child node representing the external wakeup interrupt controller should be
103 included in the pin-controller device node. This child node should include
104 the following properties.
105
106 - compatible: identifies the type of the external wakeup interrupt controller
107 The possible values are:
108 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
109 found on Samsung Exynos4210 SoC.
110 - interrupt-parent: phandle of the interrupt parent to which the external
111 wakeup interrupts are forwarded to.
112 - interrupts: interrupt used by multiplexed wakeup interrupts.
113
114 In addition, following properties must be present in node of every bank
115 of pins supporting wake-up interrupts:
116
117 - interrupt-controller: identifies the node as interrupt-parent.
118 - #interrupt-cells: the value of this property should be 2
119 - First Cell: represents the external wakeup interrupt number local to
120 the external wakeup interrupt space of the controller.
121 - Second Cell: flags to identify the type of the interrupt
122 - 1 = rising edge triggered
123 - 2 = falling edge triggered
124 - 3 = rising and falling edge triggered
125 - 4 = high level triggered
126 - 8 = low level triggered
127
128 Node of every bank of pins supporting direct wake-up interrupts (without
129 multiplexing) must contain following properties:
130
131 - interrupt-parent: phandle of the interrupt parent to which the external
132 wakeup interrupts are forwarded to.
133 - interrupts: interrupts of the interrupt parent which are used for external
134 wakeup interrupts from pins of the bank, must contain interrupts for all
135 pins of the bank.
136
137Aliases:
138
139All the pin controller nodes should be represented in the aliases node using
140the following format 'pinctrl{n}' where n is a unique number for the alias.
141
142Example: A pin-controller node with pin banks:
143
144 pinctrl_0: pinctrl@11400000 {
145 compatible = "samsung,pinctrl-exynos4210";
146 reg = <0x11400000 0x1000>;
147 interrupts = <0 47 0>;
148
149 /* ... */
150
151 /* Pin bank without external interrupts */
152 gpy0: gpy0 {
153 gpio-controller;
154 #gpio-cells = <2>;
155 };
156
157 /* ... */
158
159 /* Pin bank with external GPIO or muxed wake-up interrupts */
160 gpj0: gpj0 {
161 gpio-controller;
162 #gpio-cells = <2>;
163
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
167
168 /* ... */
169
170 /* Pin bank with external direct wake-up interrupts */
171 gpx0: gpx0 {
172 gpio-controller;
173 #gpio-cells = <2>;
174
175 interrupt-controller;
176 interrupt-parent = <&gic>;
177 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
178 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
179 #interrupt-cells = <2>;
180 };
181
182 /* ... */
183 };
184
185Example 1: A pin-controller node with pin groups.
186
187 pinctrl_0: pinctrl@11400000 {
188 compatible = "samsung,pinctrl-exynos4210";
189 reg = <0x11400000 0x1000>;
190 interrupts = <0 47 0>;
191
192 /* ... */
193
194 uart0_data: uart0-data {
195 samsung,pins = "gpa0-0", "gpa0-1";
196 samsung,pin-function = <2>;
197 samsung,pin-pud = <0>;
198 samsung,pin-drv = <0>;
199 };
200
201 uart0_fctl: uart0-fctl {
202 samsung,pins = "gpa0-2", "gpa0-3";
203 samsung,pin-function = <2>;
204 samsung,pin-pud = <0>;
205 samsung,pin-drv = <0>;
206 };
207
208 uart1_data: uart1-data {
209 samsung,pins = "gpa0-4", "gpa0-5";
210 samsung,pin-function = <2>;
211 samsung,pin-pud = <0>;
212 samsung,pin-drv = <0>;
213 };
214
215 uart1_fctl: uart1-fctl {
216 samsung,pins = "gpa0-6", "gpa0-7";
217 samsung,pin-function = <2>;
218 samsung,pin-pud = <0>;
219 samsung,pin-drv = <0>;
220 };
221
222 i2c2_bus: i2c2-bus {
223 samsung,pins = "gpa0-6", "gpa0-7";
224 samsung,pin-function = <3>;
225 samsung,pin-pud = <3>;
226 samsung,pin-drv = <0>;
227 };
228 };
229
230Example 2: A pin-controller node with external wakeup interrupt controller node.
231
232 pinctrl_1: pinctrl@11000000 {
233 compatible = "samsung,pinctrl-exynos4210";
234 reg = <0x11000000 0x1000>;
235 interrupts = <0 46 0>
236
237 /* ... */
238
239 wakeup-interrupt-controller {
240 compatible = "samsung,exynos4210-wakeup-eint";
241 interrupt-parent = <&gic>;
242 interrupts = <0 32 0>;
243 };
244 };
245
246Example 3: A uart client node that supports 'default' and 'flow-control' states.
247
248 uart@13800000 {
249 compatible = "samsung,exynos4210-uart";
250 reg = <0x13800000 0x100>;
251 interrupts = <0 52 0>;
252 pinctrl-names = "default", "flow-control;
253 pinctrl-0 = <&uart0_data>;
254 pinctrl-1 = <&uart0_data &uart0_fctl>;
255 };
256
257Example 4: Set up the default pin state for uart controller.
258
259 static int s3c24xx_serial_probe(struct platform_device *pdev) {
260 struct pinctrl *pinctrl;
261
262 /* ... */
263
264 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
265 }
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