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-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt163
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/srio.txt103
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/powerpc/Kconfig54
-rw-r--r--arch/powerpc/Kconfig.debug12
-rw-r--r--arch/powerpc/Makefile11
-rw-r--r--arch/powerpc/boot/Makefile12
-rw-r--r--arch/powerpc/boot/dcr.h6
-rw-r--r--arch/powerpc/boot/div64.S52
-rw-r--r--arch/powerpc/boot/dts/asp834x-redboot.dts4
-rw-r--r--arch/powerpc/boot/dts/currituck.dts237
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi248
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi63
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi191
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi63
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi143
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi62
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi270
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi65
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi304
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi64
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi196
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi70
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-post.dtsi198
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi64
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi174
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi225
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi235
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi224
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi76
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-post.dtsi194
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi69
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi325
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi111
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi352
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi112
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-post.dtsi296
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi125
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi350
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi143
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi355
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi96
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi60
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi60
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi59
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi65
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi106
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi100
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi109
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi109
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts4
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts4
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts4
-rw-r--r--arch/powerpc/boot/dts/klondike.dts227
-rw-r--r--arch/powerpc/boot/dts/kmeter1.dts2
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts4
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8308_p1m.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_wlan.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts456
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi141
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts410
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts473
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dtsi161
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts505
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts482
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts414
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts757
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi397
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_36b.dts746
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts487
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts245
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts73
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts4
-rw-r--r--arch/powerpc/boot/dts/obs600.dts314
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts228
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi234
-rw-r--r--arch/powerpc/boot/dts/p1010rdb_36b.dts89
-rw-r--r--arch/powerpc/boot/dts/p1010si.dtsi374
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts262
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dtsi247
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_36b.dts66
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core0.dts154
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core1.dts11
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi377
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts425
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts459
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts380
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts353
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dtsi316
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts71
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts141
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts107
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi382
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts22
-rw-r--r--arch/powerpc/boot/dts/p2041si.dtsi692
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts23
-rw-r--r--arch/powerpc/boot/dts/p3041si.dtsi729
-rw-r--r--arch/powerpc/boot/dts/p3060qds.dts12
-rw-r--r--arch/powerpc/boot/dts/p3060si.dtsi719
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts24
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi755
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts24
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi716
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts4
-rw-r--r--arch/powerpc/boot/dts/socrates.dts4
-rw-r--r--arch/powerpc/boot/dts/storcenter.dts4
-rw-r--r--arch/powerpc/boot/dts/stxssa8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts4
-rw-r--r--arch/powerpc/boot/dts/xcalibur1501.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5200.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5200_xmon.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5301.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5330.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5370.dts4
-rw-r--r--arch/powerpc/boot/treeboot-currituck.c119
-rwxr-xr-xarch/powerpc/boot/wrapper45
-rw-r--r--arch/powerpc/configs/40x/klondike_defconfig55
-rw-r--r--arch/powerpc/configs/40x/obs600_defconfig83
-rw-r--r--arch/powerpc/configs/44x/currituck_defconfig110
-rw-r--r--arch/powerpc/configs/44x/iss476-smp_defconfig3
-rw-r--r--arch/powerpc/configs/chroma_defconfig307
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig11
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig4
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig17
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig18
-rw-r--r--arch/powerpc/configs/ppc64_defconfig5
-rw-r--r--arch/powerpc/configs/ps3_defconfig39
-rw-r--r--arch/powerpc/configs/pseries_defconfig5
-rw-r--r--arch/powerpc/include/asm/Kbuild2
-rw-r--r--arch/powerpc/include/asm/cputable.h5
-rw-r--r--arch/powerpc/include/asm/cputime.h6
-rw-r--r--arch/powerpc/include/asm/fsl_ifc.h834
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h7
-rw-r--r--arch/powerpc/include/asm/hugetlb.h38
-rw-r--r--arch/powerpc/include/asm/kdump.h4
-rw-r--r--arch/powerpc/include/asm/kexec.h7
-rw-r--r--arch/powerpc/include/asm/lv1call.h10
-rw-r--r--arch/powerpc/include/asm/machdep.h3
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h11
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h7
-rw-r--r--arch/powerpc/include/asm/mpic.h14
-rw-r--r--arch/powerpc/include/asm/opal.h131
-rw-r--r--arch/powerpc/include/asm/paca.h1
-rw-r--r--arch/powerpc/include/asm/page.h90
-rw-r--r--arch/powerpc/include/asm/page_64.h2
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h6
-rw-r--r--arch/powerpc/include/asm/pci.h2
-rw-r--r--arch/powerpc/include/asm/pgtable.h3
-rw-r--r--arch/powerpc/include/asm/processor.h3
-rw-r--r--arch/powerpc/include/asm/reg.h1
-rw-r--r--arch/powerpc/include/asm/reg_booke.h4
-rw-r--r--arch/powerpc/include/asm/rtas.h18
-rw-r--r--arch/powerpc/include/asm/rwsem.h132
-rw-r--r--arch/powerpc/include/asm/system.h11
-rw-r--r--arch/powerpc/include/asm/tce.h10
-rw-r--r--arch/powerpc/include/asm/time.h2
-rw-r--r--arch/powerpc/include/asm/types.h5
-rw-r--r--arch/powerpc/kernel/Makefile2
-rw-r--r--arch/powerpc/kernel/asm-offsets.c1
-rw-r--r--arch/powerpc/kernel/cpu_setup_a2.S10
-rw-r--r--arch/powerpc/kernel/cputable.c27
-rw-r--r--arch/powerpc/kernel/crash.c220
-rw-r--r--arch/powerpc/kernel/crash_dump.c4
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S2
-rw-r--r--arch/powerpc/kernel/head_44x.S107
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S2
-rw-r--r--arch/powerpc/kernel/idle.c27
-rw-r--r--arch/powerpc/kernel/idle_power7.S4
-rw-r--r--arch/powerpc/kernel/irq.c28
-rw-r--r--arch/powerpc/kernel/machine_kexec.c2
-rw-r--r--arch/powerpc/kernel/pci-common.c78
-rw-r--r--arch/powerpc/kernel/pci_dn.c3
-rw-r--r--arch/powerpc/kernel/process.c22
-rw-r--r--arch/powerpc/kernel/prom_init.c37
-rw-r--r--arch/powerpc/kernel/reloc_32.S208
-rw-r--r--arch/powerpc/kernel/rtas_flash.c6
-rw-r--r--arch/powerpc/kernel/rtasd.c7
-rw-r--r--arch/powerpc/kernel/setup_64.c10
-rw-r--r--arch/powerpc/kernel/smp.c3
-rw-r--r--arch/powerpc/kernel/sysfs.c10
-rw-r--r--arch/powerpc/kernel/time.c105
-rw-r--r--arch/powerpc/kernel/traps.c173
-rw-r--r--arch/powerpc/kernel/vmlinux.lds.S8
-rw-r--r--arch/powerpc/kvm/book3s_hv_rmhandlers.S3
-rw-r--r--arch/powerpc/lib/Makefile4
-rw-r--r--arch/powerpc/lib/copyuser_64.S6
-rw-r--r--arch/powerpc/lib/copyuser_power7.S683
-rw-r--r--arch/powerpc/lib/copyuser_power7_vmx.c50
-rw-r--r--arch/powerpc/mm/44x_mmu.c6
-rw-r--r--arch/powerpc/mm/Makefile2
-rw-r--r--arch/powerpc/mm/fault.c17
-rw-r--r--arch/powerpc/mm/hugetlbpage-book3e.c21
-rw-r--r--arch/powerpc/mm/hugetlbpage.c116
-rw-r--r--arch/powerpc/mm/icswx.c273
-rw-r--r--arch/powerpc/mm/icswx.h62
-rw-r--r--arch/powerpc/mm/icswx_pid.c87
-rw-r--r--arch/powerpc/mm/init_32.c7
-rw-r--r--arch/powerpc/mm/mem.c23
-rw-r--r--arch/powerpc/mm/mmap_64.c14
-rw-r--r--arch/powerpc/mm/mmu_context_hash64.c195
-rw-r--r--arch/powerpc/mm/numa.c4
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S36
-rw-r--r--arch/powerpc/mm/tlb_nohash.c2
-rw-r--r--arch/powerpc/platforms/40x/Kconfig21
-rw-r--r--arch/powerpc/platforms/40x/ppc40x_simple.c4
-rw-r--r--arch/powerpc/platforms/44x/Kconfig14
-rw-r--r--arch/powerpc/platforms/44x/Makefile1
-rw-r--r--arch/powerpc/platforms/44x/currituck.c204
-rw-r--r--arch/powerpc/platforms/44x/iss4xx.c2
-rw-r--r--arch/powerpc/platforms/83xx/asp834x.c35
-rw-r--r--arch/powerpc/platforms/83xx/km83xx.c58
-rw-r--r--arch/powerpc/platforms/83xx/misc.c77
-rw-r--r--arch/powerpc/platforms/83xx/mpc830x_rdb.c40
-rw-r--r--arch/powerpc/platforms/83xx/mpc831x_rdb.c43
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_mds.c53
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_rdb.c56
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_itx.c30
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_mds.c42
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_mds.c53
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_rdk.c48
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_mds.c46
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_rdb.c47
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h16
-rw-r--r--arch/powerpc/platforms/83xx/sbc834x.c49
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/common.c66
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c28
-rw-r--r--arch/powerpc/platforms/85xx/ksi8560.c69
-rw-r--r--arch/powerpc/platforms/85xx/mpc8536_ds.c38
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.h11
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c74
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c42
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c50
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c73
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c49
-rw-r--r--arch/powerpc/platforms/85xx/p1010rdb.c38
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c37
-rw-r--r--arch/powerpc/platforms/85xx/p1023_rds.c47
-rw-r--r--arch/powerpc/platforms/85xx/sbc8548.c43
-rw-r--r--arch/powerpc/platforms/85xx/sbc8560.c74
-rw-r--r--arch/powerpc/platforms/85xx/smp.c1
-rw-r--r--arch/powerpc/platforms/85xx/smp.h15
-rw-r--r--arch/powerpc/platforms/85xx/socrates.c33
-rw-r--r--arch/powerpc/platforms/85xx/stx_gp3.c73
-rw-r--r--arch/powerpc/platforms/85xx/tqm85xx.c73
-rw-r--r--arch/powerpc/platforms/85xx/xes_mpc85xx.c48
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c2
-rw-r--r--arch/powerpc/platforms/86xx/pic.c18
-rw-r--r--arch/powerpc/platforms/Kconfig6
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype25
-rw-r--r--arch/powerpc/platforms/cell/iommu.c2
-rw-r--r--arch/powerpc/platforms/cell/setup.c25
-rw-r--r--arch/powerpc/platforms/chrp/setup.c3
-rw-r--r--arch/powerpc/platforms/embedded6xx/holly.c23
-rw-r--r--arch/powerpc/platforms/embedded6xx/linkstation.c20
-rw-r--r--arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c24
-rw-r--r--arch/powerpc/platforms/embedded6xx/storcenter.c26
-rw-r--r--arch/powerpc/platforms/maple/pci.c55
-rw-r--r--arch/powerpc/platforms/maple/setup.c2
-rw-r--r--arch/powerpc/platforms/pasemi/setup.c4
-rw-r--r--arch/powerpc/platforms/powermac/pic.c80
-rw-r--r--arch/powerpc/platforms/powermac/setup.c8
-rw-r--r--arch/powerpc/platforms/powermac/smp.c6
-rw-r--r--arch/powerpc/platforms/powernv/Makefile2
-rw-r--r--arch/powerpc/platforms/powernv/opal-wrappers.S8
-rw-r--r--arch/powerpc/platforms/powernv/pci-ioda.c1330
-rw-r--r--arch/powerpc/platforms/powernv/pci-p5ioc2.c1
-rw-r--r--arch/powerpc/platforms/powernv/pci.c228
-rw-r--r--arch/powerpc/platforms/powernv/pci.h100
-rw-r--r--arch/powerpc/platforms/powernv/smp.c2
-rw-r--r--arch/powerpc/platforms/ps3/interrupt.c103
-rw-r--r--arch/powerpc/platforms/ps3/repository.c137
-rw-r--r--arch/powerpc/platforms/ps3/setup.c4
-rw-r--r--arch/powerpc/platforms/ps3/smp.c2
-rw-r--r--arch/powerpc/platforms/ps3/spu.c2
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig9
-rw-r--r--arch/powerpc/platforms/pseries/Makefile1
-rw-r--r--arch/powerpc/platforms/pseries/hvCall_inst.c4
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c61
-rw-r--r--arch/powerpc/platforms/pseries/lpar.c2
-rw-r--r--arch/powerpc/platforms/pseries/nvram.c7
-rw-r--r--arch/powerpc/platforms/pseries/processor_idle.c329
-rw-r--r--arch/powerpc/platforms/pseries/pseries.h3
-rw-r--r--arch/powerpc/platforms/pseries/setup.c109
-rw-r--r--arch/powerpc/platforms/pseries/smp.c1
-rw-r--r--arch/powerpc/platforms/wsp/Kconfig12
-rw-r--r--arch/powerpc/platforms/wsp/Makefile8
-rw-r--r--arch/powerpc/platforms/wsp/chroma.c56
-rw-r--r--arch/powerpc/platforms/wsp/h8.c134
-rw-r--r--arch/powerpc/platforms/wsp/opb_pic.c3
-rw-r--r--arch/powerpc/platforms/wsp/psr2.c56
-rw-r--r--arch/powerpc/platforms/wsp/wsp.c115
-rw-r--r--arch/powerpc/platforms/wsp/wsp.h16
-rwxr-xr-xarch/powerpc/relocs_check.pl14
-rw-r--r--arch/powerpc/sysdev/Makefile3
-rw-r--r--arch/powerpc/sysdev/fsl_ifc.c310
-rw-r--r--arch/powerpc/sysdev/fsl_lbc.c36
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c99
-rw-r--r--arch/powerpc/sysdev/fsl_msi.h10
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c84
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c1519
-rw-r--r--arch/powerpc/sysdev/fsl_rio.h135
-rw-r--r--arch/powerpc/sysdev/fsl_rmu.c1104
-rw-r--r--arch/powerpc/sysdev/mpic.c201
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c85
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h7
-rw-r--r--arch/powerpc/sysdev/xics/icp-hv.c47
-rw-r--r--arch/powerpc/sysdev/xics/xics-common.c2
-rw-r--r--arch/powerpc/xmon/xmon.c16
-rw-r--r--arch/sparc/kernel/sys_sparc_64.c6
-rw-r--r--drivers/net/ethernet/toshiba/ps3_gelic_net.c4
-rw-r--r--drivers/tty/serial/pmac_zilog.c423
-rw-r--r--drivers/tty/serial/pmac_zilog.h19
-rw-r--r--drivers/tty/serial/ucc_uart.c3
-rw-r--r--drivers/video/offb.c71
-rw-r--r--include/linux/cpuidle.h2
-rw-r--r--tools/perf/arch/powerpc/util/dwarf-regs.c3
388 files changed, 21757 insertions, 16278 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
new file mode 100644
index 00000000000..b9a8a2bcfae
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
@@ -0,0 +1,163 @@
1Message unit node:
2
3For SRIO controllers that implement the message unit as part of the controller
4this node is required. For devices with RMAN this node should NOT exist. The
5node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
7
8See srio.txt for more details about generic SRIO controller details.
9
10 - compatible
11 Usage: required
12 Value type: <string>
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
14
15 The version X.Y should match the general SRIO controller's IP Block
16 revision register's Major(X) and Minor (Y) value.
17
18 - reg
19 Usage: required
20 Value type: <prop-encoded-array>
21 Definition: A standard property. Specifies the physical address and
22 length of the SRIO configuration registers for message units
23 and doorbell units.
24
25 - fsl,liodn
26 Usage: optional-but-recommended (for devices with PAMU)
27 Value type: <prop-encoded-array>
28 Definition: The logical I/O device number for the PAMU (IOMMU) to be
29 correctly configured for SRIO accesses. The property should
30 not exist on devices that do not support PAMU.
31
32 The LIODN value is associated with all RMU transactions
33 (msg-unit, doorbell, port-write).
34
35Sub-Nodes for RMU: The RMU node is composed of multiple sub-nodes that
36correspond to the actual sub-controllers in the RMU. The manual for a given
37SoC will detail which and how many of these sub-controllers are implemented.
38
39Message Unit:
40
41 - compatible
42 Usage: required
43 Value type: <string>
44 Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit".
45
46 The version X.Y should match the general SRIO controller's IP Block
47 revision register's Major(X) and Minor (Y) value.
48
49 - reg
50 Usage: required
51 Value type: <prop-encoded-array>
52 Definition: A standard property. Specifies the physical address and
53 length of the SRIO configuration registers for message units
54 and doorbell units.
55
56 - interrupts
57 Usage: required
58 Value type: <prop_encoded-array>
59 Definition: Specifies the interrupts generated by this device. The
60 value of the interrupts property consists of one interrupt
61 specifier. The format of the specifier is defined by the
62 binding document describing the node's interrupt parent.
63
64 A pair of IRQs are specified in this property. The first
65 element is associated with the transmit (TX) interrupt and the
66 second element is associated with the receive (RX) interrupt.
67
68Doorbell Unit:
69
70 - compatible
71 Usage: required
72 Value type: <string>
73 Definition: Must include:
74 "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit"
75
76 The version X.Y should match the general SRIO controller's IP Block
77 revision register's Major(X) and Minor (Y) value.
78
79 - reg
80 Usage: required
81 Value type: <prop-encoded-array>
82 Definition: A standard property. Specifies the physical address and
83 length of the SRIO configuration registers for message units
84 and doorbell units.
85
86 - interrupts
87 Usage: required
88 Value type: <prop_encoded-array>
89 Definition: Specifies the interrupts generated by this device. The
90 value of the interrupts property consists of one interrupt
91 specifier. The format of the specifier is defined by the
92 binding document describing the node's interrupt parent.
93
94 A pair of IRQs are specified in this property. The first
95 element is associated with the transmit (TX) interrupt and the
96 second element is associated with the receive (RX) interrupt.
97
98Port-Write Unit:
99
100 - compatible
101 Usage: required
102 Value type: <string>
103 Definition: Must include:
104 "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit"
105
106 The version X.Y should match the general SRIO controller's IP Block
107 revision register's Major(X) and Minor (Y) value.
108
109 - reg
110 Usage: required
111 Value type: <prop-encoded-array>
112 Definition: A standard property. Specifies the physical address and
113 length of the SRIO configuration registers for message units
114 and doorbell units.
115
116 - interrupts
117 Usage: required
118 Value type: <prop_encoded-array>
119 Definition: Specifies the interrupts generated by this device. The
120 value of the interrupts property consists of one interrupt
121 specifier. The format of the specifier is defined by the
122 binding document describing the node's interrupt parent.
123
124 A single IRQ that handles port-write conditions is
125 specified by this property. (Typically shared with error).
126
127 Note: All other standard properties (see the ePAPR) are allowed
128 but are optional.
129
130Example:
131 rmu: rmu@d3000 {
132 compatible = "fsl,srio-rmu";
133 reg = <0xd3000 0x400>;
134 ranges = <0x0 0xd3000 0x400>;
135 fsl,liodn = <0xc8>;
136
137 message-unit@0 {
138 compatible = "fsl,srio-msg-unit";
139 reg = <0x0 0x100>;
140 interrupts = <
141 60 2 0 0 /* msg1_tx_irq */
142 61 2 0 0>;/* msg1_rx_irq */
143 };
144 message-unit@100 {
145 compatible = "fsl,srio-msg-unit";
146 reg = <0x100 0x100>;
147 interrupts = <
148 62 2 0 0 /* msg2_tx_irq */
149 63 2 0 0>;/* msg2_rx_irq */
150 };
151 doorbell-unit@400 {
152 compatible = "fsl,srio-dbell-unit";
153 reg = <0x400 0x80>;
154 interrupts = <
155 56 2 0 0 /* bell_outb_irq */
156 57 2 0 0>;/* bell_inb_irq */
157 };
158 port-write-unit@4e0 {
159 compatible = "fsl,srio-port-write-unit";
160 reg = <0x4e0 0x20>;
161 interrupts = <16 2 1 11>;
162 };
163 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
new file mode 100644
index 00000000000..b039bcbee13
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
@@ -0,0 +1,103 @@
1* Freescale Serial RapidIO (SRIO) Controller
2
3RapidIO port node:
4Properties:
5 - compatible
6 Usage: required
7 Value type: <string>
8 Definition: Must include "fsl,srio" for IP blocks with IP Block
9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
10
11 Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
12 version in IP Block Revision Register and Y is Minor version. If this
13 compatiable is provided it should be ordered before "fsl,srio".
14
15 - reg
16 Usage: required
17 Value type: <prop-encoded-array>
18 Definition: A standard property. Specifies the physical address and
19 length of the SRIO configuration registers. The size should
20 be set to 0x11000.
21
22 - interrupts
23 Usage: required
24 Value type: <prop_encoded-array>
25 Definition: Specifies the interrupts generated by this device. The
26 value of the interrupts property consists of one interrupt
27 specifier. The format of the specifier is defined by the
28 binding document describing the node's interrupt parent.
29
30 A single IRQ that handles error conditions is specified by this
31 property. (Typically shared with port-write).
32
33 - fsl,srio-rmu-handle:
34 Usage: required if rmu node is defined
35 Value type: <phandle>
36 Definition: A single <phandle> value that points to the RMU.
37 (See srio-rmu.txt for more details on RMU node binding)
38
39Port Child Nodes: There should a port child node for each port that exists in
40the controller. The ports are numbered starting at one (1) and should have
41the following properties:
42
43 - cell-index
44 Usage: required
45 Value type: <u32>
46 Definition: A standard property. Matches the port id.
47
48 - ranges
49 Usage: required if local access windows preset
50 Value type: <prop-encoded-array>
51 Definition: A standard property. Utilized to describe the memory mapped
52 IO space utilized by the controller. This corresponds to the
53 setting of the local access windows that are targeted to this
54 SRIO port.
55
56 - fsl,liodn
57 Usage: optional-but-recommended (for devices with PAMU)
58 Value type: <prop-encoded-array>
59 Definition: The logical I/O device number for the PAMU (IOMMU) to be
60 correctly configured for SRIO accesses. The property should
61 not exist on devices that do not support PAMU.
62
63 For HW (ie, the P4080) that only supports a LIODN for both
64 memory and maintenance transactions then a single LIODN is
65 represented in the property for both transactions.
66
67 For HW (ie, the P304x/P5020, etc) that supports an LIODN for
68 memory transactions and a unique LIODN for maintenance
69 transactions then a pair of LIODNs are represented in the
70 property. Within the pair, the first element represents the
71 LIODN associated with memory transactions and the second element
72 represents the LIODN associated with maintenance transactions
73 for the port.
74
75Note: All other standard properties (see ePAPR) are allowed but are optional.
76
77Example:
78
79 rapidio: rapidio@ffe0c0000 {
80 #address-cells = <2>;
81 #size-cells = <2>;
82 reg = <0xf 0xfe0c0000 0 0x11000>;
83 compatible = "fsl,srio";
84 interrupts = <16 2 1 11>; /* err_irq */
85 fsl,srio-rmu-handle = <&rmu>;
86 ranges;
87
88 port1 {
89 cell-index = <1>;
90 #address-cells = <2>;
91 #size-cells = <2>;
92 fsl,liodn = <34>;
93 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
94 };
95
96 port2 {
97 cell-index = <2>;
98 #address-cells = <2>;
99 #size-cells = <2>;
100 fsl,liodn = <48>;
101 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
102 };
103 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0cc83fc1d8b..2747a7e9e7b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4011,7 +4011,7 @@ M: Josh Boyer <jwboyer@gmail.com>
4011M: Matt Porter <mporter@kernel.crashing.org> 4011M: Matt Porter <mporter@kernel.crashing.org>
4012W: http://www.penguinppc.org/ 4012W: http://www.penguinppc.org/
4013L: linuxppc-dev@lists.ozlabs.org 4013L: linuxppc-dev@lists.ozlabs.org
4014T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git 4014T: git git://git.infradead.org/users/jwboyer/powerpc-4xx.git
4015S: Maintained 4015S: Maintained
4016F: arch/powerpc/platforms/40x/ 4016F: arch/powerpc/platforms/40x/
4017F: arch/powerpc/platforms/44x/ 4017F: arch/powerpc/platforms/44x/
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index ead0bc68439..692ac7588e2 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -87,6 +87,10 @@ config ARCH_HAS_ILOG2_U64
87 bool 87 bool
88 default y if 64BIT 88 default y if 64BIT
89 89
90config ARCH_HAS_CPU_IDLE_WAIT
91 bool
92 default y
93
90config GENERIC_HWEIGHT 94config GENERIC_HWEIGHT
91 bool 95 bool
92 default y 96 default y
@@ -133,6 +137,7 @@ config PPC
133 select IRQ_PER_CPU 137 select IRQ_PER_CPU
134 select GENERIC_IRQ_SHOW 138 select GENERIC_IRQ_SHOW
135 select GENERIC_IRQ_SHOW_LEVEL 139 select GENERIC_IRQ_SHOW_LEVEL
140 select IRQ_FORCED_THREADING
136 select HAVE_RCU_TABLE_FREE if SMP 141 select HAVE_RCU_TABLE_FREE if SMP
137 select HAVE_SYSCALL_TRACEPOINTS 142 select HAVE_SYSCALL_TRACEPOINTS
138 select HAVE_BPF_JIT if (PPC64 && NET) 143 select HAVE_BPF_JIT if (PPC64 && NET)
@@ -363,8 +368,9 @@ config KEXEC
363 368
364config CRASH_DUMP 369config CRASH_DUMP
365 bool "Build a kdump crash kernel" 370 bool "Build a kdump crash kernel"
366 depends on PPC64 || 6xx || FSL_BOOKE 371 depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP && !PPC_47x)
367 select RELOCATABLE if PPC64 || FSL_BOOKE 372 select RELOCATABLE if PPC64 || 44x
373 select DYNAMIC_MEMSTART if FSL_BOOKE
368 help 374 help
369 Build a kernel suitable for use as a kdump capture kernel. 375 Build a kernel suitable for use as a kdump capture kernel.
370 The same kernel binary can be used as production kernel and dump 376 The same kernel binary can be used as production kernel and dump
@@ -685,6 +691,10 @@ config FSL_LBC
685 controller. Also contains some common code used by 691 controller. Also contains some common code used by
686 drivers for specific local bus peripherals. 692 drivers for specific local bus peripherals.
687 693
694config FSL_IFC
695 bool
696 depends on FSL_SOC
697
688config FSL_GTM 698config FSL_GTM
689 bool 699 bool
690 depends on PPC_83xx || QUICC_ENGINE || CPM2 700 depends on PPC_83xx || QUICC_ENGINE || CPM2
@@ -770,6 +780,10 @@ source "drivers/rapidio/Kconfig"
770 780
771endmenu 781endmenu
772 782
783config NONSTATIC_KERNEL
784 bool
785 default n
786
773menu "Advanced setup" 787menu "Advanced setup"
774 depends on PPC32 788 depends on PPC32
775 789
@@ -819,13 +833,32 @@ config LOWMEM_CAM_NUM
819 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL 833 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
820 default 3 834 default 3
821 835
836config DYNAMIC_MEMSTART
837 bool "Enable page aligned dynamic load address for kernel (EXPERIMENTAL)"
838 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || 44x)
839 select NONSTATIC_KERNEL
840 help
841 This option enables the kernel to be loaded at any page aligned
842 physical address. The kernel creates a mapping from KERNELBASE to
843 the address where the kernel is loaded. The page size here implies
844 the TLB page size of the mapping for kernel on the particular platform.
845 Please refer to the init code for finding the TLB page size.
846
847 DYNAMIC_MEMSTART is an easy way of implementing pseudo-RELOCATABLE
848 kernel image, where the only restriction is the page aligned kernel
849 load address. When this option is enabled, the compile time physical
850 address CONFIG_PHYSICAL_START is ignored.
851
852 This option is overridden by CONFIG_RELOCATABLE
853
822config RELOCATABLE 854config RELOCATABLE
823 bool "Build a relocatable kernel (EXPERIMENTAL)" 855 bool "Build a relocatable kernel (EXPERIMENTAL)"
824 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x) 856 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && 44x
857 select NONSTATIC_KERNEL
825 help 858 help
826 This builds a kernel image that is capable of running at the 859 This builds a kernel image that is capable of running at the
827 location the kernel is loaded at (some alignment restrictions may 860 location the kernel is loaded at, without any alignment restrictions.
828 exist). 861 This feature is a superset of DYNAMIC_MEMSTART and hence overrides it.
829 862
830 One use is for the kexec on panic case where the recovery kernel 863 One use is for the kexec on panic case where the recovery kernel
831 must live at a different physical address than the primary 864 must live at a different physical address than the primary
@@ -835,7 +868,11 @@ config RELOCATABLE
835 it has been loaded at and the compile time physical addresses 868 it has been loaded at and the compile time physical addresses
836 CONFIG_PHYSICAL_START is ignored. However CONFIG_PHYSICAL_START 869 CONFIG_PHYSICAL_START is ignored. However CONFIG_PHYSICAL_START
837 setting can still be useful to bootwrappers that need to know the 870 setting can still be useful to bootwrappers that need to know the
838 load location of the kernel (eg. u-boot/mkimage). 871 load address of the kernel (eg. u-boot/mkimage).
872
873config RELOCATABLE_PPC32
874 def_bool y
875 depends on PPC32 && RELOCATABLE
839 876
840config PAGE_OFFSET_BOOL 877config PAGE_OFFSET_BOOL
841 bool "Set custom page offset address" 878 bool "Set custom page offset address"
@@ -865,7 +902,7 @@ config KERNEL_START_BOOL
865config KERNEL_START 902config KERNEL_START
866 hex "Virtual address of kernel base" if KERNEL_START_BOOL 903 hex "Virtual address of kernel base" if KERNEL_START_BOOL
867 default PAGE_OFFSET if PAGE_OFFSET_BOOL 904 default PAGE_OFFSET if PAGE_OFFSET_BOOL
868 default "0xc2000000" if CRASH_DUMP && !RELOCATABLE 905 default "0xc2000000" if CRASH_DUMP && !NONSTATIC_KERNEL
869 default "0xc0000000" 906 default "0xc0000000"
870 907
871config PHYSICAL_START_BOOL 908config PHYSICAL_START_BOOL
@@ -878,7 +915,7 @@ config PHYSICAL_START_BOOL
878 915
879config PHYSICAL_START 916config PHYSICAL_START
880 hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL 917 hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
881 default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !RELOCATABLE 918 default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !NONSTATIC_KERNEL
882 default "0x00000000" 919 default "0x00000000"
883 920
884config PHYSICAL_ALIGN 921config PHYSICAL_ALIGN
@@ -924,6 +961,7 @@ endmenu
924if PPC64 961if PPC64
925config RELOCATABLE 962config RELOCATABLE
926 bool "Build a relocatable kernel" 963 bool "Build a relocatable kernel"
964 select NONSTATIC_KERNEL
927 help 965 help
928 This builds a kernel image that is capable of running anywhere 966 This builds a kernel image that is capable of running anywhere
929 in the RMA (real memory area) at any 16k-aligned base address. 967 in the RMA (real memory area) at any 16k-aligned base address.
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 1b8a9c905cf..4ccb2a009f7 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -336,4 +336,16 @@ config PPC_EARLY_DEBUG_CPM_ADDR
336 platform probing is done, all platforms selected must 336 platform probing is done, all platforms selected must
337 share the same address. 337 share the same address.
338 338
339config STRICT_DEVMEM
340 def_bool y
341 prompt "Filter access to /dev/mem"
342 help
343 This option restricts access to /dev/mem. If this option is
344 disabled, you allow userspace access to all memory, including
345 kernel and userspace memory. Accidental memory access is likely
346 to be disastrous.
347 Memory access is required for experts who want to debug the kernel.
348
349 If you are unsure, say Y.
350
339endmenu 351endmenu
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 70ba0c0a122..b8b105c01c6 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -63,9 +63,9 @@ override CC += -m$(CONFIG_WORD_SIZE)
63override AR := GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR) 63override AR := GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR)
64endif 64endif
65 65
66LDFLAGS_vmlinux-yy := -Bstatic 66LDFLAGS_vmlinux-y := -Bstatic
67LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie 67LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) := -pie
68LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-yy) 68LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y)
69 69
70CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=no -mcall-aixdesc 70CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=no -mcall-aixdesc
71CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple 71CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
@@ -131,8 +131,7 @@ KBUILD_CFLAGS += -mno-sched-epilog
131endif 131endif
132 132
133cpu-as-$(CONFIG_4xx) += -Wa,-m405 133cpu-as-$(CONFIG_4xx) += -Wa,-m405
134cpu-as-$(CONFIG_6xx) += -Wa,-maltivec 134cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec
135cpu-as-$(CONFIG_POWER4) += -Wa,-maltivec
136cpu-as-$(CONFIG_E500) += -Wa,-me500 135cpu-as-$(CONFIG_E500) += -Wa,-me500
137cpu-as-$(CONFIG_E200) += -Wa,-me200 136cpu-as-$(CONFIG_E200) += -Wa,-me200
138 137
@@ -166,7 +165,7 @@ all: zImage
166 165
167# With make 3.82 we cannot mix normal and wildcard targets 166# With make 3.82 we cannot mix normal and wildcard targets
168BOOT_TARGETS1 := zImage zImage.initrd uImage 167BOOT_TARGETS1 := zImage zImage.initrd uImage
169BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% 168BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
170 169
171PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2) 170PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
172 171
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 72ee8c1fba4..15986e70799 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,7 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
47$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 47$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
48$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
48$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 49$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
49 50
50 51
@@ -79,7 +80,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
79 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 80 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
80 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 81 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
81 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ 82 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
82 gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c 83 gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
84 treeboot-currituck.c
83src-boot := $(src-wlib) $(src-plat) empty.c 85src-boot := $(src-wlib) $(src-plat) empty.c
84 86
85src-boot := $(addprefix $(obj)/, $(src-boot)) 87src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -199,6 +201,7 @@ image-$(CONFIG_EP405) += dtbImage.ep405
199image-$(CONFIG_HOTFOOT) += cuImage.hotfoot 201image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
200image-$(CONFIG_WALNUT) += treeImage.walnut 202image-$(CONFIG_WALNUT) += treeImage.walnut
201image-$(CONFIG_ACADIA) += cuImage.acadia 203image-$(CONFIG_ACADIA) += cuImage.acadia
204image-$(CONFIG_OBS600) += uImage.obs600
202 205
203# Board ports in arch/powerpc/platform/44x/Kconfig 206# Board ports in arch/powerpc/platform/44x/Kconfig
204image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony 207image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
@@ -212,6 +215,7 @@ image-$(CONFIG_WARP) += cuImage.warp
212image-$(CONFIG_YOSEMITE) += cuImage.yosemite 215image-$(CONFIG_YOSEMITE) += cuImage.yosemite
213image-$(CONFIG_ISS4xx) += treeImage.iss4xx \ 216image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
214 treeImage.iss4xx-mpic 217 treeImage.iss4xx-mpic
218image-$(CONFIG_CURRITUCK) += treeImage.currituck
215 219
216# Board ports in arch/powerpc/platform/8xx/Kconfig 220# Board ports in arch/powerpc/platform/8xx/Kconfig
217image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads 221image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
@@ -316,6 +320,12 @@ $(obj)/zImage.iseries: vmlinux
316$(obj)/uImage: vmlinux $(wrapperbits) 320$(obj)/uImage: vmlinux $(wrapperbits)
317 $(call if_changed,wrap,uboot) 321 $(call if_changed,wrap,uboot)
318 322
323$(obj)/uImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
324 $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
325
326$(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
327 $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
328
319$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) 329$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
320 $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) 330 $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
321 331
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 645a7c964e5..cc73f7a95e2 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -9,6 +9,12 @@
9 }) 9 })
10#define mtdcr(rn, val) \ 10#define mtdcr(rn, val) \
11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val)) 11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
12#define mfdcrx(rn) \
13 ({ \
14 unsigned long rval; \
15 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
16 rval; \
17 })
12 18
13/* 440GP/440GX SDRAM controller DCRs */ 19/* 440GP/440GX SDRAM controller DCRs */
14#define DCRN_SDRAM0_CFGADDR 0x010 20#define DCRN_SDRAM0_CFGADDR 0x010
diff --git a/arch/powerpc/boot/div64.S b/arch/powerpc/boot/div64.S
index d271ab54267..bbcb8a4cc12 100644
--- a/arch/powerpc/boot/div64.S
+++ b/arch/powerpc/boot/div64.S
@@ -57,3 +57,55 @@ __div64_32:
57 stw r8,4(r3) 57 stw r8,4(r3)
58 mr r3,r6 # return the remainder in r3 58 mr r3,r6 # return the remainder in r3
59 blr 59 blr
60
61/*
62 * Extended precision shifts.
63 *
64 * Updated to be valid for shift counts from 0 to 63 inclusive.
65 * -- Gabriel
66 *
67 * R3/R4 has 64 bit value
68 * R5 has shift count
69 * result in R3/R4
70 *
71 * ashrdi3: arithmetic right shift (sign propagation)
72 * lshrdi3: logical right shift
73 * ashldi3: left shift
74 */
75 .globl __ashrdi3
76__ashrdi3:
77 subfic r6,r5,32
78 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
79 addi r7,r5,32 # could be xori, or addi with -32
80 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
81 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
82 sraw r7,r3,r7 # t2 = MSW >> (count-32)
83 or r4,r4,r6 # LSW |= t1
84 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
85 sraw r3,r3,r5 # MSW = MSW >> count
86 or r4,r4,r7 # LSW |= t2
87 blr
88
89 .globl __ashldi3
90__ashldi3:
91 subfic r6,r5,32
92 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
93 addi r7,r5,32 # could be xori, or addi with -32
94 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
95 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
96 or r3,r3,r6 # MSW |= t1
97 slw r4,r4,r5 # LSW = LSW << count
98 or r3,r3,r7 # MSW |= t2
99 blr
100
101 .globl __lshrdi3
102__lshrdi3:
103 subfic r6,r5,32
104 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
105 addi r7,r5,32 # could be xori, or addi with -32
106 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
107 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
108 or r4,r4,r6 # LSW |= t1
109 srw r3,r3,r5 # MSW = MSW >> count
110 or r4,r4,r7 # LSW |= t2
111 blr
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 261d10c4534..227290db866 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -256,7 +256,7 @@
256 serial0: serial@4500 { 256 serial0: serial@4500 {
257 cell-index = <0>; 257 cell-index = <0>;
258 device_type = "serial"; 258 device_type = "serial";
259 compatible = "ns16550"; 259 compatible = "fsl,ns16550", "ns16550";
260 reg = <0x4500 0x100>; 260 reg = <0x4500 0x100>;
261 clock-frequency = <400000000>; 261 clock-frequency = <400000000>;
262 interrupts = <9 0x8>; 262 interrupts = <9 0x8>;
@@ -266,7 +266,7 @@
266 serial1: serial@4600 { 266 serial1: serial@4600 {
267 cell-index = <1>; 267 cell-index = <1>;
268 device_type = "serial"; 268 device_type = "serial";
269 compatible = "ns16550"; 269 compatible = "fsl,ns16550", "ns16550";
270 reg = <0x4600 0x100>; 270 reg = <0x4600 0x100>;
271 clock-frequency = <400000000>; 271 clock-frequency = <400000000>;
272 interrupts = <10 0x8>; 272 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
new file mode 100644
index 00000000000..b801dd06e57
--- /dev/null
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -0,0 +1,237 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2011 Tony Breeds IBM Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/memreserve/ 0x01f00000 0x00100000; // spin table
14
15/ {
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "ibm,currituck";
19 compatible = "ibm,currituck";
20 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 serial0 = &UART0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 model = "PowerPC,476";
33 reg = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
38 i-cache-size = <32768>;
39 d-cache-size = <32768>;
40 dcr-controller;
41 dcr-access-method = "native";
42 status = "ok";
43 };
44 cpu@1 {
45 device_type = "cpu";
46 model = "PowerPC,476";
47 reg = <1>;
48 clock-frequency = <1600000000>; // 1.6 GHz
49 timebase-frequency = <100000000>; // 100Mhz
50 i-cache-line-size = <32>;
51 d-cache-line-size = <32>;
52 i-cache-size = <32768>;
53 d-cache-size = <32768>;
54 dcr-controller;
55 dcr-access-method = "native";
56 status = "disabled";
57 enable-method = "spin-table";
58 cpu-release-addr = <0x0 0x01f00000>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
65 };
66
67 MPIC: interrupt-controller {
68 compatible = "chrp,open-pic";
69 interrupt-controller;
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
74
75 };
76
77 plb {
78 compatible = "ibm,plb6";
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82 clock-frequency = <200000000>; // 200Mhz
83
84 POB0: opb {
85 compatible = "ibm,opb-4xx", "ibm,opb";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 /* Wish there was a nicer way of specifying a full
89 * 32-bit range
90 */
91 ranges = <0x00000000 0x00000200 0x00000000 0x80000000
92 0x80000000 0x00000200 0x80000000 0x80000000>;
93 clock-frequency = <100000000>;
94
95 UART0: serial@10000000 {
96 device_type = "serial";
97 compatible = "ns16750", "ns16550";
98 reg = <0x10000000 0x00000008>;
99 virtual-reg = <0xe1000000>;
100 clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
101 current-speed = <115200>;
102 interrupt-parent = <&MPIC>;
103 interrupts = <34 2>;
104 };
105
106 IIC0: i2c@00000000 {
107 compatible = "ibm,iic-currituck", "ibm,iic";
108 reg = <0x0 0x00000014>;
109 interrupt-parent = <&MPIC>;
110 interrupts = <79 2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 rtc@68 {
114 compatible = "stm,m41t80", "m41st85";
115 reg = <0x68>;
116 };
117 };
118 };
119
120 PCIE0: pciex@10100000000 { // 4xGBIF1
121 device_type = "pci";
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
126 primary;
127 port = <0x0>; /* port number */
128 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
129 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
130 dcr-reg = <0x80 0x20>;
131
132// pci_space < pci_addr > < cpu_addr > < size >
133 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
134 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
135
136 /* Inbound starting at 0 to memsize filled in by zImage */
137 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
138
139 /* This drives busses 0 to 0xf */
140 bus-range = <0x0 0xf>;
141
142 /* Legacy interrupts (note the weird polarity, the bridge seems
143 * to invert PCIe legacy interrupts).
144 * We are de-swizzling here because the numbers are actually for
145 * port of the root complex virtual P2P bridge. But I want
146 * to avoid putting a node for it in the tree, so the numbers
147 * below are basically de-swizzled numbers.
148 * The real slot is on idsel 0, so the swizzling is 1:1
149 */
150 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151 interrupt-map = <
152 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
153 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
154 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
155 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
156 };
157
158 PCIE1: pciex@30100000000 { // 4xGBIF0
159 device_type = "pci";
160 #interrupt-cells = <1>;
161 #size-cells = <2>;
162 #address-cells = <3>;
163 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
164 primary;
165 port = <0x1>; /* port number */
166 reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
167 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
168 dcr-reg = <0x60 0x20>;
169
170 ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
171 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
172
173 /* Inbound starting at 0 to memsize filled in by zImage */
174 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
175
176 /* This drives busses 0 to 0xf */
177 bus-range = <0x0 0xf>;
178
179 /* Legacy interrupts (note the weird polarity, the bridge seems
180 * to invert PCIe legacy interrupts).
181 * We are de-swizzling here because the numbers are actually for
182 * port of the root complex virtual P2P bridge. But I want
183 * to avoid putting a node for it in the tree, so the numbers
184 * below are basically de-swizzled numbers.
185 * The real slot is on idsel 0, so the swizzling is 1:1
186 */
187 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
188 interrupt-map = <
189 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
190 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
191 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
192 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
193 };
194
195 PCIE2: pciex@38100000000 { // 2xGBIF0
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
201 primary;
202 port = <0x2>; /* port number */
203 reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
204 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
205 dcr-reg = <0xA0 0x20>;
206
207 ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
208 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
209
210 /* Inbound starting at 0 to memsize filled in by zImage */
211 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
212
213 /* This drives busses 0 to 0xf */
214 bus-range = <0x0 0xf>;
215
216 /* Legacy interrupts (note the weird polarity, the bridge seems
217 * to invert PCIe legacy interrupts).
218 * We are de-swizzling here because the numbers are actually for
219 * port of the root complex virtual P2P bridge. But I want
220 * to avoid putting a node for it in the tree, so the numbers
221 * below are basically de-swizzled numbers.
222 * The real slot is on idsel 0, so the swizzling is 1:1
223 */
224 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
225 interrupt-map = <
226 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
227 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
228 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
229 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
230 };
231
232 };
233
234 chosen {
235 linux,stdout-path = &UART0;
236 };
237};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
new file mode 100644
index 00000000000..89af6263770
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -0,0 +1,248 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8548-pcie";
56 device_type = "pci";
57 #size-cells = <2>;
58 #address-cells = <3>;
59 bus-range = <0 255>;
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
62
63 pcie@0 {
64 reg = <0 0 0 0 0>;
65 #interrupt-cells = <1>;
66 #size-cells = <2>;
67 #address-cells = <3>;
68 device_type = "pci";
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
71
72 interrupt-map = <
73 /* IDSEL 0x0 */
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
78 >;
79 };
80};
81
82/* controller at 0xa000 */
83&pci2 {
84 compatible = "fsl,mpc8548-pcie";
85 device_type = "pci";
86 #size-cells = <2>;
87 #address-cells = <3>;
88 bus-range = <0 255>;
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
91
92 pcie@0 {
93 reg = <0 0 0 0 0>;
94 #interrupt-cells = <1>;
95 #size-cells = <2>;
96 #address-cells = <3>;
97 device_type = "pci";
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
100 interrupt-map = <
101 /* IDSEL 0x0 */
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
106 >;
107 };
108};
109
110/* controller at 0xb000 */
111&pci3 {
112 compatible = "fsl,mpc8548-pcie";
113 device_type = "pci";
114 #size-cells = <2>;
115 #address-cells = <3>;
116 bus-range = <0 255>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
119
120 pcie@0 {
121 reg = <0 0 0 0 0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 device_type = "pci";
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
128 interrupt-map = <
129 /* IDSEL 0x0 */
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
134 >;
135 };
136};
137&soc {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 device_type = "soc";
141 compatible = "fsl,mpc8536-immr", "simple-bus";
142 bus-frequency = <0>; // Filled out by uboot.
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <12>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2 0 0>;
154 };
155
156 memory-controller@2000 {
157 compatible = "fsl,mpc8536-memory-controller";
158 reg = <0x2000 0x1000>;
159 interrupts = <18 2 0 0>;
160 };
161
162/include/ "pq3-i2c-0.dtsi"
163/include/ "pq3-i2c-1.dtsi"
164/include/ "pq3-duart-0.dtsi"
165
166/include/ "pq3-espi-0.dtsi"
167 spi@7000 {
168 fsl,espi-num-chipselects = <4>;
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 /* mark compat w/8572 to get some erratum treatment */
174 gpio-controller@f000 {
175 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
176 };
177
178 sata@18000 {
179 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
180 reg = <0x18000 0x1000>;
181 cell-index = <1>;
182 interrupts = <74 0x2 0 0>;
183 };
184
185 sata@19000 {
186 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
187 reg = <0x19000 0x1000>;
188 cell-index = <2>;
189 interrupts = <41 0x2 0 0>;
190 };
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8536-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x80000>; // L2, 512K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-etsec1-0.dtsi"
202/include/ "pq3-etsec1-timer-0.dtsi"
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupts = <28 0x2 0 0>;
210 };
211
212 usb@23000 {
213 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 interrupts = <46 0x2 0 0>;
218 };
219
220 ptp_clock@24e00 {
221 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
222 };
223
224/include/ "pq3-etsec1-2.dtsi"
225
226 ethernet@26000 {
227 cell-index = <1>;
228 };
229
230 usb@2b000 {
231 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
232 reg = <0x2b000 0x1000>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 interrupts = <60 0x2 0 0>;
236 };
237
238/include/ "pq3-esdhc-0.dtsi"
239/include/ "pq3-sec3.0-0.dtsi"
240/include/ "pq3-mpic.dtsi"
241/include/ "pq3-mpic-timer-B.dtsi"
242
243 global-utilities@e0000 {
244 compatible = "fsl,mpc8536-guts";
245 reg = <0xe0000 0x1000>;
246 fsl,has-rstcr;
247 };
248};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
new file mode 100644
index 00000000000..7de45a784df
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -0,0 +1,63 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8536";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 pci3 = &pci3;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8536@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
new file mode 100644
index 00000000000..b68eb119fae
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
@@ -0,0 +1,191 @@
1/*
2 * MPC8544 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8548-pcie";
56 device_type = "pci";
57 #size-cells = <2>;
58 #address-cells = <3>;
59 bus-range = <0 255>;
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
62
63 pcie@0 {
64 reg = <0 0 0 0 0>;
65 #interrupt-cells = <1>;
66 #size-cells = <2>;
67 #address-cells = <3>;
68 device_type = "pci";
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
71
72 interrupt-map = <
73 /* IDSEL 0x0 */
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
78 >;
79 };
80};
81
82/* controller at 0xa000 */
83&pci2 {
84 compatible = "fsl,mpc8548-pcie";
85 device_type = "pci";
86 #size-cells = <2>;
87 #address-cells = <3>;
88 bus-range = <0 255>;
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
91
92 pcie@0 {
93 reg = <0 0 0 0 0>;
94 #interrupt-cells = <1>;
95 #size-cells = <2>;
96 #address-cells = <3>;
97 device_type = "pci";
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
100 interrupt-map = <
101 /* IDSEL 0x0 */
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
106 >;
107 };
108};
109
110/* controller at 0xb000 */
111&pci3 {
112 compatible = "fsl,mpc8548-pcie";
113 device_type = "pci";
114 #size-cells = <2>;
115 #address-cells = <3>;
116 bus-range = <0 255>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
119
120 pcie@0 {
121 reg = <0 0 0 0 0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 device_type = "pci";
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
128 interrupt-map = <
129 /* IDSEL 0x0 */
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
134 >;
135 };
136};
137
138&soc {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 device_type = "soc";
142 compatible = "fsl,mpc8544-immr", "simple-bus";
143 bus-frequency = <0>; // Filled out by uboot.
144
145 ecm-law@0 {
146 compatible = "fsl,ecm-law";
147 reg = <0x0 0x1000>;
148 fsl,num-laws = <10>;
149 };
150
151 ecm@1000 {
152 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
153 reg = <0x1000 0x1000>;
154 interrupts = <17 2 0 0>;
155 };
156
157 memory-controller@2000 {
158 compatible = "fsl,mpc8544-memory-controller";
159 reg = <0x2000 0x1000>;
160 interrupts = <18 2 0 0>;
161 };
162
163/include/ "pq3-i2c-0.dtsi"
164/include/ "pq3-i2c-1.dtsi"
165/include/ "pq3-duart-0.dtsi"
166
167 L2: l2-cache-controller@20000 {
168 compatible = "fsl,mpc8544-l2-cache-controller";
169 reg = <0x20000 0x1000>;
170 cache-line-size = <32>; // 32 bytes
171 cache-size = <0x40000>; // L2, 256K
172 interrupts = <16 2 0 0>;
173 };
174
175/include/ "pq3-dma-0.dtsi"
176/include/ "pq3-etsec1-0.dtsi"
177/include/ "pq3-etsec1-2.dtsi"
178
179 ethernet@26000 {
180 cell-index = <1>;
181 };
182
183/include/ "pq3-sec2.1-0.dtsi"
184/include/ "pq3-mpic.dtsi"
185
186 global-utilities@e0000 {
187 compatible = "fsl,mpc8544-guts";
188 reg = <0xe0000 0x1000>;
189 fsl,has-rstcr;
190 };
191};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
new file mode 100644
index 00000000000..8777f9239d9
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
@@ -0,0 +1,63 @@
1/*
2 * MPC8544 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8544";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 pci3 = &pci3;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8544@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
new file mode 100644
index 00000000000..9d8023a69d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -0,0 +1,143 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8540-pci";
56 device_type = "pci";
57 interrupts = <25 0x2 0 0>;
58 bus-range = <0 0xff>;
59 #interrupt-cells = <1>;
60 #size-cells = <2>;
61 #address-cells = <3>;
62};
63
64/* controller at 0xa000 */
65&pci2 {
66 compatible = "fsl,mpc8548-pcie";
67 device_type = "pci";
68 #size-cells = <2>;
69 #address-cells = <3>;
70 bus-range = <0 255>;
71 clock-frequency = <33333333>;
72 interrupts = <26 2 0 0>;
73
74 pcie@0 {
75 reg = <0 0 0 0 0>;
76 #interrupt-cells = <1>;
77 #size-cells = <2>;
78 #address-cells = <3>;
79 device_type = "pci";
80 interrupts = <26 2 0 0>;
81 interrupt-map-mask = <0xf800 0 0 7>;
82 interrupt-map = <
83 /* IDSEL 0x0 */
84 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
85 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
86 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
87 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
88 >;
89 };
90};
91
92&soc {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 device_type = "soc";
96 compatible = "fsl,mpc8548-immr", "simple-bus";
97 bus-frequency = <0>; // Filled out by uboot.
98
99 ecm-law@0 {
100 compatible = "fsl,ecm-law";
101 reg = <0x0 0x1000>;
102 fsl,num-laws = <10>;
103 };
104
105 ecm@1000 {
106 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
107 reg = <0x1000 0x1000>;
108 interrupts = <17 2 0 0>;
109 };
110
111 memory-controller@2000 {
112 compatible = "fsl,mpc8548-memory-controller";
113 reg = <0x2000 0x1000>;
114 interrupts = <18 2 0 0>;
115 };
116
117/include/ "pq3-i2c-0.dtsi"
118/include/ "pq3-i2c-1.dtsi"
119/include/ "pq3-duart-0.dtsi"
120
121 L2: l2-cache-controller@20000 {
122 compatible = "fsl,mpc8548-l2-cache-controller";
123 reg = <0x20000 0x1000>;
124 cache-line-size = <32>; // 32 bytes
125 cache-size = <0x80000>; // L2, 512K
126 interrupts = <16 2 0 0>;
127 };
128
129/include/ "pq3-dma-0.dtsi"
130/include/ "pq3-etsec1-0.dtsi"
131/include/ "pq3-etsec1-1.dtsi"
132/include/ "pq3-etsec1-2.dtsi"
133/include/ "pq3-etsec1-3.dtsi"
134
135/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi"
137
138 global-utilities@e0000 {
139 compatible = "fsl,mpc8548-guts";
140 reg = <0xe0000 0x1000>;
141 fsl,has-rstcr;
142 };
143};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
new file mode 100644
index 00000000000..289f1218d75
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -0,0 +1,62 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8548";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8548@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61 };
62};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
new file mode 100644
index 00000000000..64e7075a9cd
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
@@ -0,0 +1,270 @@
1/*
2 * MPC8568 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0x8000 */
44&pci0 {
45 compatible = "fsl,mpc8540-pci";
46 device_type = "pci";
47 interrupts = <24 0x2 0 0>;
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
52 sleep = <&pmc 0x80000000>;
53};
54
55/* controller at 0xa000 */
56&pci1 {
57 compatible = "fsl,mpc8548-pcie";
58 device_type = "pci";
59 #size-cells = <2>;
60 #address-cells = <3>;
61 bus-range = <0 255>;
62 clock-frequency = <33333333>;
63 interrupts = <26 2 0 0>;
64 sleep = <&pmc 0x20000000>;
65
66 pcie@0 {
67 reg = <0 0 0 0 0>;
68 #interrupt-cells = <1>;
69 #size-cells = <2>;
70 #address-cells = <3>;
71 device_type = "pci";
72 interrupts = <26 2 0 0>;
73 interrupt-map-mask = <0xf800 0 0 7>;
74 interrupt-map = <
75 /* IDSEL 0x0 */
76 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
77 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
78 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
79 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
80 >;
81 };
82};
83
84&rio {
85 compatible = "fsl,srio";
86 interrupts = <48 2 0 0>;
87 #address-cells = <2>;
88 #size-cells = <2>;
89 fsl,srio-rmu-handle = <&rmu>;
90 sleep = <&pmc 0x00080000>;
91 ranges;
92
93 port1 {
94 #address-cells = <2>;
95 #size-cells = <2>;
96 cell-index = <1>;
97 };
98};
99
100&soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,mpc8568-immr", "simple-bus";
105 bus-frequency = <0>; // Filled out by uboot.
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <10>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
116 interrupts = <17 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,mpc8568-memory-controller";
121 reg = <0x2000 0x1000>;
122 interrupts = <18 2 0 0>;
123 };
124
125 i2c-sleep-nexus {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 sleep = <&pmc 0x00000004>;
130 ranges;
131
132/include/ "pq3-i2c-0.dtsi"
133/include/ "pq3-i2c-1.dtsi"
134
135 };
136
137 duart-sleep-nexus {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "simple-bus";
141 sleep = <&pmc 0x00000002>;
142 ranges;
143
144/include/ "pq3-duart-0.dtsi"
145
146 };
147
148 L2: l2-cache-controller@20000 {
149 compatible = "fsl,mpc8568-l2-cache-controller";
150 reg = <0x20000 0x1000>;
151 cache-line-size = <32>; // 32 bytes
152 cache-size = <0x80000>; // L2, 512K
153 interrupts = <16 2 0 0>;
154 };
155
156/include/ "pq3-dma-0.dtsi"
157 dma@21300 {
158 sleep = <&pmc 0x00000400>;
159 };
160
161/include/ "pq3-etsec1-0.dtsi"
162 ethernet@24000 {
163 sleep = <&pmc 0x00000080>;
164 };
165
166/include/ "pq3-etsec1-1.dtsi"
167 ethernet@25000 {
168 sleep = <&pmc 0x00000040>;
169 };
170
171 par_io@e0100 {
172 reg = <0xe0100 0x100>;
173 device_type = "par_io";
174 };
175
176/include/ "pq3-sec2.1-0.dtsi"
177 crypto@30000 {
178 sleep = <&pmc 0x01000000>;
179 };
180
181/include/ "pq3-mpic.dtsi"
182/include/ "pq3-rmu-0.dtsi"
183 rmu@d3000 {
184 sleep = <&pmc 0x00040000>;
185 };
186
187 global-utilities@e0000 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
191 reg = <0xe0000 0x1000>;
192 ranges = <0 0xe0000 0x1000>;
193 fsl,has-rstcr;
194
195 pmc: power@70 {
196 compatible = "fsl,mpc8568-pmc",
197 "fsl,mpc8548-pmc";
198 reg = <0x70 0x20>;
199 };
200 };
201};
202
203&qe {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 device_type = "qe";
207 compatible = "fsl,qe";
208 sleep = <&pmc 0x00000800>;
209 brg-frequency = <0>;
210 bus-frequency = <396000000>;
211 fsl,qe-num-riscs = <2>;
212 fsl,qe-num-snums = <28>;
213
214 qeic: interrupt-controller@80 {
215 interrupt-controller;
216 compatible = "fsl,qe-ic";
217 #address-cells = <0>;
218 #interrupt-cells = <1>;
219 reg = <0x80 0x80>;
220 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
221 interrupt-parent = <&mpic>;
222 };
223
224 spi@4c0 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "fsl,spi";
228 reg = <0x4c0 0x40>;
229 cell-index = <0>;
230 interrupts = <2>;
231 interrupt-parent = <&qeic>;
232 };
233
234 spi@500 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl,spi";
239 reg = <0x500 0x40>;
240 interrupts = <1>;
241 interrupt-parent = <&qeic>;
242 };
243
244 ucc@2000 {
245 cell-index = <1>;
246 reg = <0x2000 0x200>;
247 interrupts = <32>;
248 interrupt-parent = <&qeic>;
249 };
250
251 ucc@3000 {
252 cell-index = <2>;
253 reg = <0x3000 0x200>;
254 interrupts = <33>;
255 interrupt-parent = <&qeic>;
256 };
257
258 muram@10000 {
259 #address-cells = <1>;
260 #size-cells = <1>;
261 compatible = "fsl,qe-muram", "fsl,cpm-muram";
262 ranges = <0x0 0x10000 0x10000>;
263
264 data-only@0 {
265 compatible = "fsl,qe-muram-data",
266 "fsl,cpm-muram-data";
267 reg = <0x0 0x10000>;
268 };
269 };
270};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
new file mode 100644
index 00000000000..eacd62c5fe6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
@@ -0,0 +1,65 @@
1/*
2 * MPC8568 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8568";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci0 = &pci0;
50 pci1 = &pci1;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8568@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 sleep = <&pmc 0x00008000 // core
62 &pmc 0x00004000>; // timebase
63 };
64 };
65};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
new file mode 100644
index 00000000000..3e6346a4a18
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
@@ -0,0 +1,304 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0xa000 */
44&pci1 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
53
54 pcie@0 {
55 reg = <0 0 0 0 0>;
56 #interrupt-cells = <1>;
57 #size-cells = <2>;
58 #address-cells = <3>;
59 device_type = "pci";
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
62 interrupt-map = <
63 /* IDSEL 0x0 */
64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
68 >;
69 };
70};
71
72&rio {
73 compatible = "fsl,srio";
74 interrupts = <48 2 0 0>;
75 #address-cells = <2>;
76 #size-cells = <2>;
77 fsl,srio-rmu-handle = <&rmu>;
78 sleep = <&pmc 0x00080000>;
79 ranges;
80
81 port1 {
82 #address-cells = <2>;
83 #size-cells = <2>;
84 cell-index = <1>;
85 };
86
87 port2 {
88 #address-cells = <2>;
89 #size-cells = <2>;
90 cell-index = <2>;
91 };
92};
93
94&soc {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 device_type = "soc";
98 compatible = "fsl,mpc8569-immr", "simple-bus";
99 bus-frequency = <0>; // Filled out by uboot.
100
101 ecm-law@0 {
102 compatible = "fsl,ecm-law";
103 reg = <0x0 0x1000>;
104 fsl,num-laws = <10>;
105 };
106
107 ecm@1000 {
108 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
109 reg = <0x1000 0x1000>;
110 interrupts = <17 2 0 0>;
111 };
112
113 memory-controller@2000 {
114 compatible = "fsl,mpc8569-memory-controller";
115 reg = <0x2000 0x1000>;
116 interrupts = <18 2 0 0>;
117 };
118
119 i2c-sleep-nexus {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 sleep = <&pmc 0x00000004>;
124 ranges;
125
126/include/ "pq3-i2c-0.dtsi"
127/include/ "pq3-i2c-1.dtsi"
128
129 };
130
131 duart-sleep-nexus {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
135 sleep = <&pmc 0x00000002>;
136 ranges;
137
138/include/ "pq3-duart-0.dtsi"
139
140 };
141
142 L2: l2-cache-controller@20000 {
143 compatible = "fsl,mpc8569-l2-cache-controller";
144 reg = <0x20000 0x1000>;
145 cache-line-size = <32>; // 32 bytes
146 cache-size = <0x80000>; // L2, 512K
147 interrupts = <16 2 0 0>;
148 };
149
150/include/ "pq3-dma-0.dtsi"
151/include/ "pq3-esdhc-0.dtsi"
152 sdhc@2e000 {
153 sleep = <&pmc 0x00200000>;
154 };
155
156 par_io@e0100 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0xe0100 0x100>;
160 ranges = <0x0 0xe0100 0x100>;
161 device_type = "par_io";
162 };
163
164/include/ "pq3-sec3.1-0.dtsi"
165 crypto@30000 {
166 sleep = <&pmc 0x01000000>;
167 };
168
169/include/ "pq3-mpic.dtsi"
170/include/ "pq3-rmu-0.dtsi"
171 rmu@d3000 {
172 sleep = <&pmc 0x00040000>;
173 };
174
175 global-utilities@e0000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
179 reg = <0xe0000 0x1000>;
180 ranges = <0 0xe0000 0x1000>;
181 fsl,has-rstcr;
182
183 pmc: power@70 {
184 compatible = "fsl,mpc8569-pmc",
185 "fsl,mpc8548-pmc";
186 reg = <0x70 0x20>;
187 };
188 };
189};
190
191&qe {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 device_type = "qe";
195 compatible = "fsl,qe";
196 sleep = <&pmc 0x00000800>;
197 brg-frequency = <0>;
198 bus-frequency = <0>;
199 fsl,qe-num-riscs = <4>;
200 fsl,qe-num-snums = <46>;
201
202 qeic: interrupt-controller@80 {
203 interrupt-controller;
204 compatible = "fsl,qe-ic";
205 #address-cells = <0>;
206 #interrupt-cells = <1>;
207 reg = <0x80 0x80>;
208 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
209 interrupt-parent = <&mpic>;
210 };
211
212 timer@440 {
213 compatible = "fsl,mpc8569-qe-gtm",
214 "fsl,qe-gtm", "fsl,gtm";
215 reg = <0x440 0x40>;
216 interrupts = <12 13 14 15>;
217 interrupt-parent = <&qeic>;
218 /* Filled in by U-Boot */
219 clock-frequency = <0>;
220 };
221
222 spi@4c0 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
226 reg = <0x4c0 0x40>;
227 cell-index = <0>;
228 interrupts = <2>;
229 interrupt-parent = <&qeic>;
230 };
231
232 spi@500 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 cell-index = <1>;
236 compatible = "fsl,spi";
237 reg = <0x500 0x40>;
238 interrupts = <1>;
239 interrupt-parent = <&qeic>;
240 };
241
242 usb@6c0 {
243 compatible = "fsl,mpc8569-qe-usb",
244 "fsl,mpc8323-qe-usb";
245 reg = <0x6c0 0x40 0x8b00 0x100>;
246 interrupts = <11>;
247 interrupt-parent = <&qeic>;
248 };
249
250 ucc@2000 {
251 cell-index = <1>;
252 reg = <0x2000 0x200>;
253 interrupts = <32>;
254 interrupt-parent = <&qeic>;
255 };
256
257 ucc@2200 {
258 cell-index = <3>;
259 reg = <0x2200 0x200>;
260 interrupts = <34>;
261 interrupt-parent = <&qeic>;
262 };
263
264 ucc@3000 {
265 cell-index = <2>;
266 reg = <0x3000 0x200>;
267 interrupts = <33>;
268 interrupt-parent = <&qeic>;
269 };
270
271 ucc@3200 {
272 cell-index = <4>;
273 reg = <0x3200 0x200>;
274 interrupts = <35>;
275 interrupt-parent = <&qeic>;
276 };
277
278 ucc@3400 {
279 cell-index = <6>;
280 reg = <0x3400 0x200>;
281 interrupts = <41>;
282 interrupt-parent = <&qeic>;
283 };
284
285 ucc@3600 {
286 cell-index = <8>;
287 reg = <0x3600 0x200>;
288 interrupts = <43>;
289 interrupt-parent = <&qeic>;
290 };
291
292 muram@10000 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,qe-muram", "fsl,cpm-muram";
296 ranges = <0x0 0x10000 0x20000>;
297
298 data-only@0 {
299 compatible = "fsl,qe-muram-data",
300 "fsl,cpm-muram-data";
301 reg = <0x0 0x20000>;
302 };
303 };
304};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
new file mode 100644
index 00000000000..b07064d1193
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -0,0 +1,64 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8569";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8569@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 sleep = <&pmc 0x00008000 // core
61 &pmc 0x00004000>; // timebase
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
new file mode 100644
index 00000000000..d44e25a4873
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
@@ -0,0 +1,196 @@
1/*
2 * MPC8572 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <24 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <24 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60
61 interrupt-map = <
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
67 >;
68 };
69};
70
71/* controller at 0x9000 */
72&pci1 {
73 compatible = "fsl,mpc8548-pcie";
74 device_type = "pci";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
79 interrupts = <25 2 0 0>;
80
81 pcie@0 {
82 reg = <0 0 0 0 0>;
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
86 device_type = "pci";
87 interrupts = <25 2 0 0>;
88 interrupt-map-mask = <0xf800 0 0 7>;
89
90 interrupt-map = <
91 /* IDSEL 0x0 */
92 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
93 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
94 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
95 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
96 >;
97 };
98};
99
100/* controller at 0xa000 */
101&pci2 {
102 compatible = "fsl,mpc8548-pcie";
103 device_type = "pci";
104 #size-cells = <2>;
105 #address-cells = <3>;
106 bus-range = <0 255>;
107 clock-frequency = <33333333>;
108 interrupts = <26 2 0 0>;
109
110 pcie@0 {
111 reg = <0 0 0 0 0>;
112 #interrupt-cells = <1>;
113 #size-cells = <2>;
114 #address-cells = <3>;
115 device_type = "pci";
116 interrupts = <26 2 0 0>;
117 interrupt-map-mask = <0xf800 0 0 7>;
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,mpc8572-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <17 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,mpc8572-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <18 2 0 0>;
151 };
152
153 memory-controller@6000 {
154 compatible = "fsl,mpc8572-memory-controller";
155 reg = <0x6000 0x1000>;
156 interrupts = <18 2 0 0>;
157 };
158
159/include/ "pq3-i2c-0.dtsi"
160/include/ "pq3-i2c-1.dtsi"
161/include/ "pq3-duart-0.dtsi"
162/include/ "pq3-dma-1.dtsi"
163/include/ "pq3-gpio-0.dtsi"
164 gpio-controller@f000 {
165 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
166 };
167
168 L2: l2-cache-controller@20000 {
169 compatible = "fsl,mpc8572-l2-cache-controller";
170 reg = <0x20000 0x1000>;
171 cache-line-size = <32>; // 32 bytes
172 cache-size = <0x100000>; // L2,1M
173 interrupts = <16 2 0 0>;
174 };
175
176/include/ "pq3-dma-0.dtsi"
177/include/ "pq3-etsec1-0.dtsi"
178/include/ "pq3-etsec1-timer-0.dtsi"
179
180 ptp_clock@24e00 {
181 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
182 };
183
184/include/ "pq3-etsec1-1.dtsi"
185/include/ "pq3-etsec1-2.dtsi"
186/include/ "pq3-etsec1-3.dtsi"
187/include/ "pq3-sec3.0-0.dtsi"
188/include/ "pq3-mpic.dtsi"
189/include/ "pq3-mpic-timer-B.dtsi"
190
191 global-utilities@e0000 {
192 compatible = "fsl,mpc8572-guts";
193 reg = <0xe0000 0x1000>;
194 fsl,has-rstcr;
195 };
196};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
new file mode 100644
index 00000000000..ca188326c2c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
@@ -0,0 +1,70 @@
1/*
2 * MPC8572 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8572";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci0 = &pci0;
50 pci1 = &pci1;
51 pci2 = &pci2;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 PowerPC,8572@0 {
59 device_type = "cpu";
60 reg = <0x0>;
61 next-level-cache = <&L2>;
62 };
63
64 PowerPC,8572@1 {
65 device_type = "cpu";
66 reg = <0x1>;
67 next-level-cache = <&L2>;
68 };
69 };
70};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
new file mode 100644
index 00000000000..bd9e163c764
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -0,0 +1,198 @@
1/*
2 * P1010/P1014 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <16 2 0 0 19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1010-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1010-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1010-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127/include/ "pq3-espi-0.dtsi"
128 spi0: spi@7000 {
129 fsl,espi-num-chipselects = <1>;
130 };
131
132/include/ "pq3-gpio-0.dtsi"
133/include/ "pq3-sata2-0.dtsi"
134/include/ "pq3-sata2-1.dtsi"
135
136 can0: can@1c000 {
137 compatible = "fsl,p1010-flexcan";
138 reg = <0x1c000 0x1000>;
139 interrupts = <48 0x2 0 0>;
140 };
141
142 can1: can@1d000 {
143 compatible = "fsl,p1010-flexcan";
144 reg = <0x1d000 0x1000>;
145 interrupts = <61 0x2 0 0>;
146 };
147
148 L2: l2-cache-controller@20000 {
149 compatible = "fsl,p1010-l2-cache-controller",
150 "fsl,p1014-l2-cache-controller";
151 reg = <0x20000 0x1000>;
152 cache-line-size = <32>; // 32 bytes
153 cache-size = <0x40000>; // L2,256K
154 interrupts = <16 2 0 0>;
155 };
156
157/include/ "pq3-dma-0.dtsi"
158/include/ "pq3-usb2-dr-0.dtsi"
159/include/ "pq3-esdhc-0.dtsi"
160 sdhc@2e000 {
161 fsl,sdhci-auto-cmd12;
162 };
163
164/include/ "pq3-sec4.4-0.dtsi"
165/include/ "pq3-mpic.dtsi"
166/include/ "pq3-mpic-timer-B.dtsi"
167
168/include/ "pq3-etsec2-0.dtsi"
169 enet0: ethernet@b0000 {
170 queue-group@b0000 {
171 fsl,rx-bit-map = <0xff>;
172 fsl,tx-bit-map = <0xff>;
173 };
174 };
175
176/include/ "pq3-etsec2-1.dtsi"
177 enet1: ethernet@b1000 {
178 queue-group@b1000 {
179 fsl,rx-bit-map = <0xff>;
180 fsl,tx-bit-map = <0xff>;
181 };
182 };
183
184/include/ "pq3-etsec2-2.dtsi"
185 enet2: ethernet@b2000 {
186 queue-group@b2000 {
187 fsl,rx-bit-map = <0xff>;
188 fsl,tx-bit-map = <0xff>;
189 };
190
191 };
192
193 global-utilities@e0000 {
194 compatible = "fsl,p1010-guts";
195 reg = <0xe0000 0x1000>;
196 fsl,has-rstcr;
197 };
198};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
new file mode 100644
index 00000000000..7354a8f90ea
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
@@ -0,0 +1,64 @@
1/*
2 * P1010/P1014 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1010";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 can0 = &can0;
51 can1 = &can1;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 PowerPC,P1010@0 {
59 device_type = "cpu";
60 reg = <0x0>;
61 next-level-cache = <&L2>;
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
new file mode 100644
index 00000000000..fc924c5ffeb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -0,0 +1,174 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1020-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1020-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1020-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1020-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145/include/ "pq3-usb2-dr-1.dtsi"
146
147/include/ "pq3-esdhc-0.dtsi"
148/include/ "pq3-sec3.3-0.dtsi"
149
150/include/ "pq3-mpic.dtsi"
151/include/ "pq3-mpic-timer-B.dtsi"
152
153/include/ "pq3-etsec2-0.dtsi"
154 enet0: enet0_grp2: ethernet@b0000 {
155 };
156
157/include/ "pq3-etsec2-1.dtsi"
158 enet1: enet1_grp2: ethernet@b1000 {
159 };
160
161/include/ "pq3-etsec2-2.dtsi"
162 enet2: enet2_grp2: ethernet@b2000 {
163 };
164
165 global-utilities@e0000 {
166 compatible = "fsl,p1020-guts";
167 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr;
169 };
170};
171
172/include/ "pq3-etsec2-grp2-0.dtsi"
173/include/ "pq3-etsec2-grp2-1.dtsi"
174/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
new file mode 100644
index 00000000000..6f0376e554e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1020@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1020@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
new file mode 100644
index 00000000000..38ba54d1e32
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -0,0 +1,225 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1021-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1021-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1021-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1021-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146/include/ "pq3-esdhc-0.dtsi"
147/include/ "pq3-sec3.3-0.dtsi"
148
149/include/ "pq3-mpic.dtsi"
150/include/ "pq3-mpic-timer-B.dtsi"
151
152/include/ "pq3-etsec2-0.dtsi"
153 enet0: enet0_grp2: ethernet@b0000 {
154 };
155
156/include/ "pq3-etsec2-1.dtsi"
157 enet1: enet1_grp2: ethernet@b1000 {
158 };
159
160/include/ "pq3-etsec2-2.dtsi"
161 enet2: enet2_grp2: ethernet@b2000 {
162 };
163
164 global-utilities@e0000 {
165 compatible = "fsl,p1021-guts";
166 reg = <0xe0000 0x1000>;
167 fsl,has-rstcr;
168 };
169};
170
171&qe {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 device_type = "qe";
175 compatible = "fsl,qe";
176 fsl,qe-num-riscs = <1>;
177 fsl,qe-num-snums = <28>;
178
179 qeic: interrupt-controller@80 {
180 interrupt-controller;
181 compatible = "fsl,qe-ic";
182 #address-cells = <0>;
183 #interrupt-cells = <1>;
184 reg = <0x80 0x80>;
185 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
186 };
187
188 ucc@2000 {
189 cell-index = <1>;
190 reg = <0x2000 0x200>;
191 interrupts = <32>;
192 interrupt-parent = <&qeic>;
193 };
194
195 mdio@2120 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0x2120 0x18>;
199 compatible = "fsl,ucc-mdio";
200 };
201
202 ucc@2400 {
203 cell-index = <5>;
204 reg = <0x2400 0x200>;
205 interrupts = <40>;
206 interrupt-parent = <&qeic>;
207 };
208
209 muram@10000 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,qe-muram", "fsl,cpm-muram";
213 ranges = <0x0 0x10000 0x6000>;
214
215 data-only@0 {
216 compatible = "fsl,qe-muram-data",
217 "fsl,cpm-muram-data";
218 reg = <0x0 0x6000>;
219 };
220 };
221};
222
223/include/ "pq3-etsec2-grp2-0.dtsi"
224/include/ "pq3-etsec2-grp2-1.dtsi"
225/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
new file mode 100644
index 00000000000..4abd54bc330
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1021";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1021@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1021@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
new file mode 100644
index 00000000000..16239b199d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -0,0 +1,235 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,p1022-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,p1022-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0xb000 */
100&pci2 {
101 compatible = "fsl,p1022-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <16 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <16 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p1022-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p1022-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <16 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p1022-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <16 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162 dma@c300 {
163 dma00: dma-channel@0 {
164 compatible = "fsl,ssi-dma-channel";
165 };
166 dma01: dma-channel@80 {
167 compatible = "fsl,ssi-dma-channel";
168 };
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 display@10000 {
174 compatible = "fsl,diu", "fsl,p1022-diu";
175 reg = <0x10000 1000>;
176 interrupts = <64 2 0 0>;
177 };
178
179 ssi@15000 {
180 compatible = "fsl,mpc8610-ssi";
181 cell-index = <0>;
182 reg = <0x15000 0x100>;
183 interrupts = <75 2 0 0>;
184 fsl,playback-dma = <&dma00>;
185 fsl,capture-dma = <&dma01>;
186 fsl,fifo-depth = <15>;
187 };
188
189/include/ "pq3-sata2-0.dtsi"
190/include/ "pq3-sata2-1.dtsi"
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,p1022-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x40000>; // L2,256K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-usb2-dr-0.dtsi"
202/include/ "pq3-usb2-dr-1.dtsi"
203
204/include/ "pq3-esdhc-0.dtsi"
205 sdhc@2e000 {
206 fsl,sdhci-auto-cmd12;
207 };
208
209/include/ "pq3-sec3.3-0.dtsi"
210/include/ "pq3-mpic.dtsi"
211/include/ "pq3-mpic-timer-B.dtsi"
212
213/include/ "pq3-etsec2-0.dtsi"
214 enet0: enet0_grp2: ethernet@b0000 {
215 };
216
217/include/ "pq3-etsec2-1.dtsi"
218 enet1: enet1_grp2: ethernet@b1000 {
219 };
220
221 global-utilities@e0000 {
222 compatible = "fsl,p1022-guts";
223 reg = <0xe0000 0x1000>;
224 fsl,has-rstcr;
225 };
226
227 power@e0070{
228 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
229 reg = <0xe0070 0x20>;
230 };
231
232};
233
234/include/ "pq3-etsec2-grp2-0.dtsi"
235/include/ "pq3-etsec2-grp2-1.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
new file mode 100644
index 00000000000..e930f4f7ca8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1022";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1022@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1022@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
new file mode 100644
index 00000000000..b06bb4cc1fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -0,0 +1,224 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 0 0>;
58 };
59};
60
61/* controller at 0x9000 */
62&pci1 {
63 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
64 device_type = "pci";
65 #size-cells = <2>;
66 #address-cells = <3>;
67 bus-range = <0 0xff>;
68 clock-frequency = <33333333>;
69 interrupts = <16 2 0 0>;
70 pcie@0 {
71 reg = <0 0 0 0 0>;
72 #interrupt-cells = <1>;
73 #size-cells = <2>;
74 #address-cells = <3>;
75 device_type = "pci";
76 interrupts = <16 2 0 0>;
77 };
78};
79
80/* controller at 0xb000 */
81&pci2 {
82 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
83 device_type = "pci";
84 #size-cells = <2>;
85 #address-cells = <3>;
86 bus-range = <0x0 0xff>;
87 clock-frequency = <33333333>;
88 interrupts = <16 2 0 0>;
89 pcie@0 {
90 reg = <0 0 0 0 0>;
91 #interrupt-cells = <1>;
92 #size-cells = <2>;
93 #address-cells = <3>;
94 device_type = "pci";
95 interrupts = <16 2 0 0>;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1023-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1023-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1023-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1023-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146 crypto: crypto@300000 {
147 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <0x30000 0x10000>;
151 ranges = <0 0x30000 0x10000>;
152 interrupts = <58 2 0 0>;
153
154 sec_jr0: jr@1000 {
155 compatible = "fsl,sec-v4.2-job-ring",
156 "fsl,sec-v4.0-job-ring";
157 reg = <0x1000 0x1000>;
158 interrupts = <45 2 0 0>;
159 };
160
161 sec_jr1: jr@2000 {
162 compatible = "fsl,sec-v4.2-job-ring",
163 "fsl,sec-v4.0-job-ring";
164 reg = <0x2000 0x1000>;
165 interrupts = <45 2 0 0>;
166 };
167
168 sec_jr2: jr@3000 {
169 compatible = "fsl,sec-v4.2-job-ring",
170 "fsl,sec-v4.0-job-ring";
171 reg = <0x3000 0x1000>;
172 interrupts = <57 2 0 0>;
173 };
174
175 sec_jr3: jr@4000 {
176 compatible = "fsl,sec-v4.2-job-ring",
177 "fsl,sec-v4.0-job-ring";
178 reg = <0x4000 0x1000>;
179 interrupts = <57 2 0 0>;
180 };
181
182 rtic@6000 {
183 compatible = "fsl,sec-v4.2-rtic",
184 "fsl,sec-v4.0-rtic";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = <0x6000 0x100>;
188 ranges = <0x0 0x6100 0xe00>;
189
190 rtic_a: rtic-a@0 {
191 compatible = "fsl,sec-v4.2-rtic-memory",
192 "fsl,sec-v4.0-rtic-memory";
193 reg = <0x00 0x20 0x100 0x80>;
194 };
195
196 rtic_b: rtic-b@20 {
197 compatible = "fsl,sec-v4.2-rtic-memory",
198 "fsl,sec-v4.0-rtic-memory";
199 reg = <0x20 0x20 0x200 0x80>;
200 };
201
202 rtic_c: rtic-c@40 {
203 compatible = "fsl,sec-v4.2-rtic-memory",
204 "fsl,sec-v4.0-rtic-memory";
205 reg = <0x40 0x20 0x300 0x80>;
206 };
207
208 rtic_d: rtic-d@60 {
209 compatible = "fsl,sec-v4.2-rtic-memory",
210 "fsl,sec-v4.0-rtic-memory";
211 reg = <0x60 0x20 0x500 0x80>;
212 };
213 };
214 };
215
216/include/ "pq3-mpic.dtsi"
217/include/ "pq3-mpic-timer-B.dtsi"
218
219 global-utilities@e0000 {
220 compatible = "fsl,p1023-guts";
221 reg = <0xe0000 0x1000>;
222 fsl,has-rstcr;
223 };
224};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
new file mode 100644
index 00000000000..ac45f6d9338
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -0,0 +1,76 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1023";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 pci0 = &pci0;
46 pci1 = &pci1;
47 pci2 = &pci2;
48
49 crypto = &crypto;
50 sec_jr0 = &sec_jr0;
51 sec_jr1 = &sec_jr1;
52 sec_jr2 = &sec_jr2;
53 sec_jr3 = &sec_jr3;
54 rtic_a = &rtic_a;
55 rtic_b = &rtic_b;
56 rtic_c = &rtic_c;
57 rtic_d = &rtic_d;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 PowerPC,P1023@0 {
65 device_type = "cpu";
66 reg = <0x0>;
67 next-level-cache = <&L2>;
68 };
69
70 PowerPC,P1023@1 {
71 device_type = "cpu";
72 reg = <0x1>;
73 next-level-cache = <&L2>;
74 };
75 };
76};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
new file mode 100644
index 00000000000..c041050561a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -0,0 +1,194 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <26 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <26 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0x9000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <25 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <25 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0x8000 */
100&pci2 {
101 compatible = "fsl,mpc8548-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <24 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <24 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p2020-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p2020-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <17 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p2020-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <18 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi0: spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162/include/ "pq3-gpio-0.dtsi"
163
164 L2: l2-cache-controller@20000 {
165 compatible = "fsl,p2020-l2-cache-controller";
166 reg = <0x20000 0x1000>;
167 cache-line-size = <32>; // 32 bytes
168 cache-size = <0x80000>; // L2,512K
169 interrupts = <16 2 0 0>;
170 };
171
172/include/ "pq3-dma-0.dtsi"
173/include/ "pq3-usb2-dr-0.dtsi"
174/include/ "pq3-etsec1-0.dtsi"
175/include/ "pq3-etsec1-timer-0.dtsi"
176
177 ptp_clock@24e00 {
178 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
179 };
180
181
182/include/ "pq3-etsec1-1.dtsi"
183/include/ "pq3-etsec1-2.dtsi"
184/include/ "pq3-esdhc-0.dtsi"
185/include/ "pq3-sec3.1-0.dtsi"
186/include/ "pq3-mpic.dtsi"
187/include/ "pq3-mpic-timer-B.dtsi"
188
189 global-utilities@e0000 {
190 compatible = "fsl,p2020-guts";
191 reg = <0xe0000 0x1000>;
192 fsl,has-rstcr;
193 };
194};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
new file mode 100644
index 00000000000..3213288641d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -0,0 +1,69 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P2020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,P2020@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62
63 PowerPC,P2020@1 {
64 device_type = "cpu";
65 reg = <0x1>;
66 next-level-cache = <&L2>;
67 };
68 };
69};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
new file mode 100644
index 00000000000..234a399ddeb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -0,0 +1,325 @@
1/*
2 * P2041/P2040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&rio {
124 compatible = "fsl,srio";
125 interrupts = <16 2 1 11>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 ranges;
129
130 port1 {
131 #address-cells = <2>;
132 #size-cells = <2>;
133 cell-index = <1>;
134 };
135
136 port2 {
137 #address-cells = <2>;
138 #size-cells = <2>;
139 cell-index = <2>;
140 };
141};
142
143&dcsr {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,dcsr", "simple-bus";
147
148 dcsr-epu@0 {
149 compatible = "fsl,dcsr-epu";
150 interrupts = <52 2 0 0
151 84 2 0 0
152 85 2 0 0>;
153 reg = <0x0 0x1000>;
154 };
155 dcsr-npc {
156 compatible = "fsl,dcsr-npc";
157 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 };
159 dcsr-nxc@2000 {
160 compatible = "fsl,dcsr-nxc";
161 reg = <0x2000 0x1000>;
162 };
163 dcsr-corenet {
164 compatible = "fsl,dcsr-corenet";
165 reg = <0x8000 0x1000 0xB0000 0x1000>;
166 };
167 dcsr-dpaa@9000 {
168 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
169 reg = <0x9000 0x1000>;
170 };
171 dcsr-ocn@11000 {
172 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
173 reg = <0x11000 0x1000>;
174 };
175 dcsr-ddr@12000 {
176 compatible = "fsl,dcsr-ddr";
177 dev-handle = <&ddr1>;
178 reg = <0x12000 0x1000>;
179 };
180 dcsr-nal@18000 {
181 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
182 reg = <0x18000 0x1000>;
183 };
184 dcsr-rcpm@22000 {
185 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
186 reg = <0x22000 0x1000>;
187 };
188 dcsr-cpu-sb-proxy@40000 {
189 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
190 cpu-handle = <&cpu0>;
191 reg = <0x40000 0x1000>;
192 };
193 dcsr-cpu-sb-proxy@41000 {
194 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
195 cpu-handle = <&cpu1>;
196 reg = <0x41000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@42000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu2>;
201 reg = <0x42000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@43000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu3>;
206 reg = <0x43000 0x1000>;
207 };
208};
209
210&soc {
211 #address-cells = <1>;
212 #size-cells = <1>;
213 device_type = "soc";
214 compatible = "simple-bus";
215
216 soc-sram-error {
217 compatible = "fsl,soc-sram-error";
218 interrupts = <16 2 1 29>;
219 };
220
221 corenet-law@0 {
222 compatible = "fsl,corenet-law";
223 reg = <0x0 0x1000>;
224 fsl,num-laws = <32>;
225 };
226
227 ddr1: memory-controller@8000 {
228 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
229 reg = <0x8000 0x1000>;
230 interrupts = <16 2 1 23>;
231 };
232
233 cpc: l3-cache-controller@10000 {
234 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
235 reg = <0x10000 0x1000>;
236 interrupts = <16 2 1 27>;
237 };
238
239 corenet-cf@18000 {
240 compatible = "fsl,corenet-cf";
241 reg = <0x18000 0x1000>;
242 interrupts = <16 2 1 31>;
243 fsl,ccf-num-csdids = <32>;
244 fsl,ccf-num-snoopids = <32>;
245 };
246
247 iommu@20000 {
248 compatible = "fsl,pamu-v1.0", "fsl,pamu";
249 reg = <0x20000 0x4000>;
250 interrupts = <
251 24 2 0 0
252 16 2 1 30>;
253 };
254
255/include/ "qoriq-mpic.dtsi"
256
257 guts: global-utilities@e0000 {
258 compatible = "fsl,qoriq-device-config-1.0";
259 reg = <0xe0000 0xe00>;
260 fsl,has-rstcr;
261 #sleep-cells = <1>;
262 fsl,liodn-bits = <12>;
263 };
264
265 pins: global-utilities@e0e00 {
266 compatible = "fsl,qoriq-pin-control-1.0";
267 reg = <0xe0e00 0x200>;
268 #sleep-cells = <2>;
269 };
270
271 clockgen: global-utilities@e1000 {
272 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
273 reg = <0xe1000 0x1000>;
274 clock-frequency = <0>;
275 };
276
277 rcpm: global-utilities@e2000 {
278 compatible = "fsl,qoriq-rcpm-1.0";
279 reg = <0xe2000 0x1000>;
280 #sleep-cells = <1>;
281 };
282
283 sfp: sfp@e8000 {
284 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
285 reg = <0xe8000 0x1000>;
286 };
287
288 serdes: serdes@ea000 {
289 compatible = "fsl,p2041-serdes";
290 reg = <0xea000 0x1000>;
291 };
292
293/include/ "qoriq-dma-0.dtsi"
294/include/ "qoriq-dma-1.dtsi"
295/include/ "qoriq-espi-0.dtsi"
296 spi@110000 {
297 fsl,espi-num-chipselects = <4>;
298 };
299
300/include/ "qoriq-esdhc-0.dtsi"
301 sdhc@114000 {
302 sdhci,auto-cmd12;
303 };
304
305/include/ "qoriq-i2c-0.dtsi"
306/include/ "qoriq-i2c-1.dtsi"
307/include/ "qoriq-duart-0.dtsi"
308/include/ "qoriq-duart-1.dtsi"
309/include/ "qoriq-gpio-0.dtsi"
310/include/ "qoriq-usb2-mph-0.dtsi"
311 usb0: usb@210000 {
312 phy_type = "utmi";
313 port0;
314 };
315
316/include/ "qoriq-usb2-dr-0.dtsi"
317 usb1: usb@211000 {
318 dr_mode = "host";
319 phy_type = "utmi";
320 };
321
322/include/ "qoriq-sata2-0.dtsi"
323/include/ "qoriq-sata2-1.dtsi"
324/include/ "qoriq-sec4.2-0.dtsi"
325};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
new file mode 100644
index 00000000000..2d0a40d6b10
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -0,0 +1,111 @@
1/*
2 * P2041 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P2041";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 };
111};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
new file mode 100644
index 00000000000..d41d08de7f7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -0,0 +1,352 @@
1/*
2 * P3041 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x203000 */
124&pci3 {
125 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <16 2 1 12>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&rio {
151 compatible = "fsl,srio";
152 interrupts = <16 2 1 11>;
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 port1 {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 cell-index = <1>;
161 };
162
163 port2 {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 cell-index = <2>;
167 };
168};
169
170&dcsr {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "fsl,dcsr", "simple-bus";
174
175 dcsr-epu@0 {
176 compatible = "fsl,dcsr-epu";
177 interrupts = <52 2 0 0
178 84 2 0 0
179 85 2 0 0>;
180 reg = <0x0 0x1000>;
181 };
182 dcsr-npc {
183 compatible = "fsl,dcsr-npc";
184 reg = <0x1000 0x1000 0x1000000 0x8000>;
185 };
186 dcsr-nxc@2000 {
187 compatible = "fsl,dcsr-nxc";
188 reg = <0x2000 0x1000>;
189 };
190 dcsr-corenet {
191 compatible = "fsl,dcsr-corenet";
192 reg = <0x8000 0x1000 0xB0000 0x1000>;
193 };
194 dcsr-dpaa@9000 {
195 compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
196 reg = <0x9000 0x1000>;
197 };
198 dcsr-ocn@11000 {
199 compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
200 reg = <0x11000 0x1000>;
201 };
202 dcsr-ddr@12000 {
203 compatible = "fsl,dcsr-ddr";
204 dev-handle = <&ddr1>;
205 reg = <0x12000 0x1000>;
206 };
207 dcsr-nal@18000 {
208 compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
209 reg = <0x18000 0x1000>;
210 };
211 dcsr-rcpm@22000 {
212 compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
213 reg = <0x22000 0x1000>;
214 };
215 dcsr-cpu-sb-proxy@40000 {
216 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217 cpu-handle = <&cpu0>;
218 reg = <0x40000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@41000 {
221 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu1>;
223 reg = <0x41000 0x1000>;
224 };
225 dcsr-cpu-sb-proxy@42000 {
226 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu2>;
228 reg = <0x42000 0x1000>;
229 };
230 dcsr-cpu-sb-proxy@43000 {
231 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
232 cpu-handle = <&cpu3>;
233 reg = <0x43000 0x1000>;
234 };
235};
236
237&soc {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 device_type = "soc";
241 compatible = "simple-bus";
242
243 soc-sram-error {
244 compatible = "fsl,soc-sram-error";
245 interrupts = <16 2 1 29>;
246 };
247
248 corenet-law@0 {
249 compatible = "fsl,corenet-law";
250 reg = <0x0 0x1000>;
251 fsl,num-laws = <32>;
252 };
253
254 ddr1: memory-controller@8000 {
255 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
256 reg = <0x8000 0x1000>;
257 interrupts = <16 2 1 23>;
258 };
259
260 cpc: l3-cache-controller@10000 {
261 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
262 reg = <0x10000 0x1000>;
263 interrupts = <16 2 1 27>;
264 };
265
266 corenet-cf@18000 {
267 compatible = "fsl,corenet-cf";
268 reg = <0x18000 0x1000>;
269 interrupts = <16 2 1 31>;
270 fsl,ccf-num-csdids = <32>;
271 fsl,ccf-num-snoopids = <32>;
272 };
273
274 iommu@20000 {
275 compatible = "fsl,pamu-v1.0", "fsl,pamu";
276 reg = <0x20000 0x4000>;
277 interrupts = <
278 24 2 0 0
279 16 2 1 30>;
280 };
281
282/include/ "qoriq-mpic.dtsi"
283
284 guts: global-utilities@e0000 {
285 compatible = "fsl,qoriq-device-config-1.0";
286 reg = <0xe0000 0xe00>;
287 fsl,has-rstcr;
288 #sleep-cells = <1>;
289 fsl,liodn-bits = <12>;
290 };
291
292 pins: global-utilities@e0e00 {
293 compatible = "fsl,qoriq-pin-control-1.0";
294 reg = <0xe0e00 0x200>;
295 #sleep-cells = <2>;
296 };
297
298 clockgen: global-utilities@e1000 {
299 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
300 reg = <0xe1000 0x1000>;
301 clock-frequency = <0>;
302 };
303
304 rcpm: global-utilities@e2000 {
305 compatible = "fsl,qoriq-rcpm-1.0";
306 reg = <0xe2000 0x1000>;
307 #sleep-cells = <1>;
308 };
309
310 sfp: sfp@e8000 {
311 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
312 reg = <0xe8000 0x1000>;
313 };
314
315 serdes: serdes@ea000 {
316 compatible = "fsl,p3041-serdes";
317 reg = <0xea000 0x1000>;
318 };
319
320/include/ "qoriq-dma-0.dtsi"
321/include/ "qoriq-dma-1.dtsi"
322/include/ "qoriq-espi-0.dtsi"
323 spi@110000 {
324 fsl,espi-num-chipselects = <4>;
325 };
326
327/include/ "qoriq-esdhc-0.dtsi"
328 sdhc@114000 {
329 sdhci,auto-cmd12;
330 };
331
332/include/ "qoriq-i2c-0.dtsi"
333/include/ "qoriq-i2c-1.dtsi"
334/include/ "qoriq-duart-0.dtsi"
335/include/ "qoriq-duart-1.dtsi"
336/include/ "qoriq-gpio-0.dtsi"
337/include/ "qoriq-usb2-mph-0.dtsi"
338 usb0: usb@210000 {
339 phy_type = "utmi";
340 port0;
341 };
342
343/include/ "qoriq-usb2-dr-0.dtsi"
344 usb1: usb@211000 {
345 dr_mode = "host";
346 phy_type = "utmi";
347 };
348
349/include/ "qoriq-sata2-0.dtsi"
350/include/ "qoriq-sata2-1.dtsi"
351/include/ "qoriq-sec4.2-0.dtsi"
352};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
new file mode 100644
index 00000000000..136def3536b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -0,0 +1,112 @@
1/*
2 * P3041 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P3041";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e500mc@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e500mc@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 cpu2: PowerPC,e500mc@2 {
96 device_type = "cpu";
97 reg = <2>;
98 next-level-cache = <&L2_2>;
99 L2_2: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 cpu3: PowerPC,e500mc@3 {
104 device_type = "cpu";
105 reg = <3>;
106 next-level-cache = <&L2_3>;
107 L2_3: l2-cache {
108 next-level-cache = <&cpc>;
109 };
110 };
111 };
112};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
new file mode 100644
index 00000000000..a63edd195ae
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -0,0 +1,296 @@
1/*
2 * P3060 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96&rio {
97 compatible = "fsl,srio";
98 interrupts = <16 2 1 11>;
99 #address-cells = <2>;
100 #size-cells = <2>;
101 fsl,srio-rmu-handle = <&rmu>;
102 ranges;
103
104 port1 {
105 #address-cells = <2>;
106 #size-cells = <2>;
107 cell-index = <1>;
108 };
109
110 port2 {
111 #address-cells = <2>;
112 #size-cells = <2>;
113 cell-index = <2>;
114 };
115};
116
117&dcsr {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,dcsr", "simple-bus";
121
122 dcsr-epu@0 {
123 compatible = "fsl,dcsr-epu";
124 interrupts = <52 2 0 0
125 84 2 0 0
126 85 2 0 0>;
127 reg = <0x0 0x1000>;
128 };
129 dcsr-npc {
130 compatible = "fsl,dcsr-npc";
131 reg = <0x1000 0x1000 0x1000000 0x8000>;
132 };
133 dcsr-nxc@2000 {
134 compatible = "fsl,dcsr-nxc";
135 reg = <0x2000 0x1000>;
136 };
137 dcsr-corenet {
138 compatible = "fsl,dcsr-corenet";
139 reg = <0x8000 0x1000 0xB0000 0x1000>;
140 };
141 dcsr-dpaa@9000 {
142 compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
143 reg = <0x9000 0x1000>;
144 };
145 dcsr-ocn@11000 {
146 compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
147 reg = <0x11000 0x1000>;
148 };
149 dcsr-ddr@12000 {
150 compatible = "fsl,dcsr-ddr";
151 dev-handle = <&ddr1>;
152 reg = <0x12000 0x1000>;
153 };
154 dcsr-nal@18000 {
155 compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
156 reg = <0x18000 0x1000>;
157 };
158 dcsr-rcpm@22000 {
159 compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
160 reg = <0x22000 0x1000>;
161 };
162 dcsr-cpu-sb-proxy@40000 {
163 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
164 cpu-handle = <&cpu0>;
165 reg = <0x40000 0x1000>;
166 };
167 dcsr-cpu-sb-proxy@41000 {
168 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
169 cpu-handle = <&cpu1>;
170 reg = <0x41000 0x1000>;
171 };
172 dcsr-cpu-sb-proxy@44000 {
173 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
174 cpu-handle = <&cpu4>;
175 reg = <0x44000 0x1000>;
176 };
177 dcsr-cpu-sb-proxy@45000 {
178 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
179 cpu-handle = <&cpu5>;
180 reg = <0x45000 0x1000>;
181 };
182 dcsr-cpu-sb-proxy@46000 {
183 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
184 cpu-handle = <&cpu6>;
185 reg = <0x46000 0x1000>;
186 };
187 dcsr-cpu-sb-proxy@47000 {
188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
189 cpu-handle = <&cpu7>;
190 reg = <0x47000 0x1000>;
191 };
192
193};
194
195&soc {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 device_type = "soc";
199 compatible = "simple-bus";
200
201 soc-sram-error {
202 compatible = "fsl,soc-sram-error";
203 interrupts = <16 2 1 29>;
204 };
205
206 corenet-law@0 {
207 compatible = "fsl,corenet-law";
208 reg = <0x0 0x1000>;
209 fsl,num-laws = <32>;
210 };
211
212 ddr1: memory-controller@8000 {
213 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
214 reg = <0x8000 0x1000>;
215 interrupts = <16 2 1 23>;
216 };
217
218 cpc: l3-cache-controller@10000 {
219 compatible = "fsl,p3060-l3-cache-controller", "cache";
220 reg = <0x10000 0x1000
221 0x11000 0x1000>;
222 interrupts = <16 2 1 27
223 16 2 1 26>;
224 };
225
226 corenet-cf@18000 {
227 compatible = "fsl,corenet-cf";
228 reg = <0x18000 0x1000>;
229 interrupts = <16 2 1 31>;
230 fsl,ccf-num-csdids = <32>;
231 fsl,ccf-num-snoopids = <32>;
232 };
233
234 iommu@20000 {
235 compatible = "fsl,pamu-v1.0", "fsl,pamu";
236 reg = <0x20000 0x5000>;
237 interrupts = <
238 24 2 0 0
239 16 2 1 30>;
240 };
241
242/include/ "qoriq-rmu-0.dtsi"
243/include/ "qoriq-mpic.dtsi"
244
245 guts: global-utilities@e0000 {
246 compatible = "fsl,qoriq-device-config-1.0";
247 reg = <0xe0000 0xe00>;
248 fsl,has-rstcr;
249 #sleep-cells = <1>;
250 fsl,liodn-bits = <12>;
251 };
252
253 pins: global-utilities@e0e00 {
254 compatible = "fsl,qoriq-pin-control-1.0";
255 reg = <0xe0e00 0x200>;
256 #sleep-cells = <2>;
257 };
258
259 clockgen: global-utilities@e1000 {
260 compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
261 reg = <0xe1000 0x1000>;
262 clock-frequency = <0>;
263 };
264
265 rcpm: global-utilities@e2000 {
266 compatible = "fsl,qoriq-rcpm-1.0";
267 reg = <0xe2000 0x1000>;
268 #sleep-cells = <1>;
269 };
270
271 sfp: sfp@e8000 {
272 compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
273 reg = <0xe8000 0x1000>;
274 };
275
276 serdes: serdes@ea000 {
277 compatible = "fsl,p3060-serdes";
278 reg = <0xea000 0x1000>;
279 };
280
281/include/ "qoriq-dma-0.dtsi"
282/include/ "qoriq-dma-1.dtsi"
283/include/ "qoriq-espi-0.dtsi"
284 spi@110000 {
285 fsl,espi-num-chipselects = <4>;
286 };
287
288/include/ "qoriq-i2c-0.dtsi"
289/include/ "qoriq-i2c-1.dtsi"
290/include/ "qoriq-duart-0.dtsi"
291/include/ "qoriq-duart-1.dtsi"
292/include/ "qoriq-gpio-0.dtsi"
293/include/ "qoriq-usb2-mph-0.dtsi"
294/include/ "qoriq-usb2-dr-0.dtsi"
295/include/ "qoriq-sec4.1-0.dtsi"
296};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
new file mode 100644
index 00000000000..00c8e70e7b9
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
@@ -0,0 +1,125 @@
1/*
2 * P3060 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P3060";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 usb0 = &usb0;
53 usb1 = &usb1;
54 dma0 = &dma0;
55 dma1 = &dma1;
56 msi0 = &msi0;
57 msi1 = &msi1;
58 msi2 = &msi2;
59
60 crypto = &crypto;
61 sec_jr0 = &sec_jr0;
62 sec_jr1 = &sec_jr1;
63 sec_jr2 = &sec_jr2;
64 sec_jr3 = &sec_jr3;
65 rtic_a = &rtic_a;
66 rtic_b = &rtic_b;
67 rtic_c = &rtic_c;
68 rtic_d = &rtic_d;
69 sec_mon = &sec_mon;
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 cpu0: PowerPC,e500mc@0 {
77 device_type = "cpu";
78 reg = <0>;
79 next-level-cache = <&L2_0>;
80 L2_0: l2-cache {
81 next-level-cache = <&cpc>;
82 };
83 };
84 cpu1: PowerPC,e500mc@1 {
85 device_type = "cpu";
86 reg = <1>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu4: PowerPC,e500mc@4 {
93 device_type = "cpu";
94 reg = <4>;
95 next-level-cache = <&L2_4>;
96 L2_4: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 cpu5: PowerPC,e500mc@5 {
101 device_type = "cpu";
102 reg = <5>;
103 next-level-cache = <&L2_5>;
104 L2_5: l2-cache {
105 next-level-cache = <&cpc>;
106 };
107 };
108 cpu6: PowerPC,e500mc@6 {
109 device_type = "cpu";
110 reg = <6>;
111 next-level-cache = <&L2_6>;
112 L2_6: l2-cache {
113 next-level-cache = <&cpc>;
114 };
115 };
116 cpu7: PowerPC,e500mc@7 {
117 device_type = "cpu";
118 reg = <7>;
119 next-level-cache = <&L2_7>;
120 L2_7: l2-cache {
121 next-level-cache = <&cpc>;
122 };
123 };
124 };
125};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
new file mode 100644
index 00000000000..8d35d2c1f69
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -0,0 +1,350 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p4080-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p4080-pcie";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p4080-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&rio {
124 compatible = "fsl,srio";
125 interrupts = <16 2 1 11>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 fsl,srio-rmu-handle = <&rmu>;
129 ranges;
130
131 port1 {
132 #address-cells = <2>;
133 #size-cells = <2>;
134 cell-index = <1>;
135 };
136
137 port2 {
138 #address-cells = <2>;
139 #size-cells = <2>;
140 cell-index = <2>;
141 };
142};
143
144&dcsr {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "fsl,dcsr", "simple-bus";
148
149 dcsr-epu@0 {
150 compatible = "fsl,dcsr-epu";
151 interrupts = <52 2 0 0
152 84 2 0 0
153 85 2 0 0>;
154 reg = <0x0 0x1000>;
155 };
156 dcsr-npc {
157 compatible = "fsl,dcsr-npc";
158 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 };
160 dcsr-nxc@2000 {
161 compatible = "fsl,dcsr-nxc";
162 reg = <0x2000 0x1000>;
163 };
164 dcsr-corenet {
165 compatible = "fsl,dcsr-corenet";
166 reg = <0x8000 0x1000 0xB0000 0x1000>;
167 };
168 dcsr-dpaa@9000 {
169 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
170 reg = <0x9000 0x1000>;
171 };
172 dcsr-ocn@11000 {
173 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
174 reg = <0x11000 0x1000>;
175 };
176 dcsr-ddr@12000 {
177 compatible = "fsl,dcsr-ddr";
178 dev-handle = <&ddr1>;
179 reg = <0x12000 0x1000>;
180 };
181 dcsr-ddr@13000 {
182 compatible = "fsl,dcsr-ddr";
183 dev-handle = <&ddr2>;
184 reg = <0x13000 0x1000>;
185 };
186 dcsr-nal@18000 {
187 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
188 reg = <0x18000 0x1000>;
189 };
190 dcsr-rcpm@22000 {
191 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
192 reg = <0x22000 0x1000>;
193 };
194 dcsr-cpu-sb-proxy@40000 {
195 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
196 cpu-handle = <&cpu0>;
197 reg = <0x40000 0x1000>;
198 };
199 dcsr-cpu-sb-proxy@41000 {
200 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
201 cpu-handle = <&cpu1>;
202 reg = <0x41000 0x1000>;
203 };
204 dcsr-cpu-sb-proxy@42000 {
205 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
206 cpu-handle = <&cpu2>;
207 reg = <0x42000 0x1000>;
208 };
209 dcsr-cpu-sb-proxy@43000 {
210 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
211 cpu-handle = <&cpu3>;
212 reg = <0x43000 0x1000>;
213 };
214 dcsr-cpu-sb-proxy@44000 {
215 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
216 cpu-handle = <&cpu4>;
217 reg = <0x44000 0x1000>;
218 };
219 dcsr-cpu-sb-proxy@45000 {
220 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
221 cpu-handle = <&cpu5>;
222 reg = <0x45000 0x1000>;
223 };
224 dcsr-cpu-sb-proxy@46000 {
225 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
226 cpu-handle = <&cpu6>;
227 reg = <0x46000 0x1000>;
228 };
229 dcsr-cpu-sb-proxy@47000 {
230 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
231 cpu-handle = <&cpu7>;
232 reg = <0x47000 0x1000>;
233 };
234
235};
236
237&soc {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 device_type = "soc";
241 compatible = "simple-bus";
242
243 soc-sram-error {
244 compatible = "fsl,soc-sram-error";
245 interrupts = <16 2 1 29>;
246 };
247
248 corenet-law@0 {
249 compatible = "fsl,corenet-law";
250 reg = <0x0 0x1000>;
251 fsl,num-laws = <32>;
252 };
253
254 ddr1: memory-controller@8000 {
255 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
256 reg = <0x8000 0x1000>;
257 interrupts = <16 2 1 23>;
258 };
259
260 ddr2: memory-controller@9000 {
261 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
262 reg = <0x9000 0x1000>;
263 interrupts = <16 2 1 22>;
264 };
265
266 cpc: l3-cache-controller@10000 {
267 compatible = "fsl,p4080-l3-cache-controller", "cache";
268 reg = <0x10000 0x1000
269 0x11000 0x1000>;
270 interrupts = <16 2 1 27
271 16 2 1 26>;
272 };
273
274 corenet-cf@18000 {
275 compatible = "fsl,corenet-cf";
276 reg = <0x18000 0x1000>;
277 interrupts = <16 2 1 31>;
278 fsl,ccf-num-csdids = <32>;
279 fsl,ccf-num-snoopids = <32>;
280 };
281
282 iommu@20000 {
283 compatible = "fsl,pamu-v1.0", "fsl,pamu";
284 reg = <0x20000 0x5000>;
285 interrupts = <
286 24 2 0 0
287 16 2 1 30>;
288 };
289
290/include/ "qoriq-rmu-0.dtsi"
291/include/ "qoriq-mpic.dtsi"
292
293 guts: global-utilities@e0000 {
294 compatible = "fsl,qoriq-device-config-1.0";
295 reg = <0xe0000 0xe00>;
296 fsl,has-rstcr;
297 #sleep-cells = <1>;
298 fsl,liodn-bits = <12>;
299 };
300
301 pins: global-utilities@e0e00 {
302 compatible = "fsl,qoriq-pin-control-1.0";
303 reg = <0xe0e00 0x200>;
304 #sleep-cells = <2>;
305 };
306
307 clockgen: global-utilities@e1000 {
308 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
309 reg = <0xe1000 0x1000>;
310 clock-frequency = <0>;
311 };
312
313 rcpm: global-utilities@e2000 {
314 compatible = "fsl,qoriq-rcpm-1.0";
315 reg = <0xe2000 0x1000>;
316 #sleep-cells = <1>;
317 };
318
319 sfp: sfp@e8000 {
320 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
321 reg = <0xe8000 0x1000>;
322 };
323
324 serdes: serdes@ea000 {
325 compatible = "fsl,p4080-serdes";
326 reg = <0xea000 0x1000>;
327 };
328
329/include/ "qoriq-dma-0.dtsi"
330/include/ "qoriq-dma-1.dtsi"
331/include/ "qoriq-espi-0.dtsi"
332 spi@110000 {
333 fsl,espi-num-chipselects = <4>;
334 };
335
336/include/ "qoriq-esdhc-0.dtsi"
337 sdhc@114000 {
338 voltage-ranges = <3300 3300>;
339 sdhci,auto-cmd12;
340 };
341
342/include/ "qoriq-i2c-0.dtsi"
343/include/ "qoriq-i2c-1.dtsi"
344/include/ "qoriq-duart-0.dtsi"
345/include/ "qoriq-duart-1.dtsi"
346/include/ "qoriq-gpio-0.dtsi"
347/include/ "qoriq-usb2-mph-0.dtsi"
348/include/ "qoriq-usb2-dr-0.dtsi"
349/include/ "qoriq-sec4.0-0.dtsi"
350};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
new file mode 100644
index 00000000000..b9556ee3a63
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,143 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P4080";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 cpu4: PowerPC,e500mc@4 {
111 device_type = "cpu";
112 reg = <4>;
113 next-level-cache = <&L2_4>;
114 L2_4: l2-cache {
115 next-level-cache = <&cpc>;
116 };
117 };
118 cpu5: PowerPC,e500mc@5 {
119 device_type = "cpu";
120 reg = <5>;
121 next-level-cache = <&L2_5>;
122 L2_5: l2-cache {
123 next-level-cache = <&cpc>;
124 };
125 };
126 cpu6: PowerPC,e500mc@6 {
127 device_type = "cpu";
128 reg = <6>;
129 next-level-cache = <&L2_6>;
130 L2_6: l2-cache {
131 next-level-cache = <&cpc>;
132 };
133 };
134 cpu7: PowerPC,e500mc@7 {
135 device_type = "cpu";
136 reg = <7>;
137 next-level-cache = <&L2_7>;
138 L2_7: l2-cache {
139 next-level-cache = <&cpc>;
140 };
141 };
142 };
143};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
new file mode 100644
index 00000000000..914074b91a8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -0,0 +1,355 @@
1/*
2 * P5020/5010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x203000 */
124&pci3 {
125 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <16 2 1 12>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&rio {
151 compatible = "fsl,srio";
152 interrupts = <16 2 1 11>;
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 port1 {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 cell-index = <1>;
161 };
162
163 port2 {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 cell-index = <2>;
167 };
168};
169
170&dcsr {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "fsl,dcsr", "simple-bus";
174
175 dcsr-epu@0 {
176 compatible = "fsl,dcsr-epu";
177 interrupts = <52 2 0 0
178 84 2 0 0
179 85 2 0 0>;
180 reg = <0x0 0x1000>;
181 };
182 dcsr-npc {
183 compatible = "fsl,dcsr-npc";
184 reg = <0x1000 0x1000 0x1000000 0x8000>;
185 };
186 dcsr-nxc@2000 {
187 compatible = "fsl,dcsr-nxc";
188 reg = <0x2000 0x1000>;
189 };
190 dcsr-corenet {
191 compatible = "fsl,dcsr-corenet";
192 reg = <0x8000 0x1000 0xB0000 0x1000>;
193 };
194 dcsr-dpaa@9000 {
195 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
196 reg = <0x9000 0x1000>;
197 };
198 dcsr-ocn@11000 {
199 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
200 reg = <0x11000 0x1000>;
201 };
202 dcsr-ddr@12000 {
203 compatible = "fsl,dcsr-ddr";
204 dev-handle = <&ddr1>;
205 reg = <0x12000 0x1000>;
206 };
207 dcsr-ddr@13000 {
208 compatible = "fsl,dcsr-ddr";
209 dev-handle = <&ddr2>;
210 reg = <0x13000 0x1000>;
211 };
212 dcsr-nal@18000 {
213 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
214 reg = <0x18000 0x1000>;
215 };
216 dcsr-rcpm@22000 {
217 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
218 reg = <0x22000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@40000 {
221 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu0>;
223 reg = <0x40000 0x1000>;
224 };
225 dcsr-cpu-sb-proxy@41000 {
226 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu1>;
228 reg = <0x41000 0x1000>;
229 };
230};
231
232&soc {
233 #address-cells = <1>;
234 #size-cells = <1>;
235 device_type = "soc";
236 compatible = "simple-bus";
237
238 soc-sram-error {
239 compatible = "fsl,soc-sram-error";
240 interrupts = <16 2 1 29>;
241 };
242
243 corenet-law@0 {
244 compatible = "fsl,corenet-law";
245 reg = <0x0 0x1000>;
246 fsl,num-laws = <32>;
247 };
248
249 ddr1: memory-controller@8000 {
250 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
251 reg = <0x8000 0x1000>;
252 interrupts = <16 2 1 23>;
253 };
254
255 ddr2: memory-controller@9000 {
256 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
257 reg = <0x9000 0x1000>;
258 interrupts = <16 2 1 22>;
259 };
260
261 cpc: l3-cache-controller@10000 {
262 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
263 reg = <0x10000 0x1000
264 0x11000 0x1000>;
265 interrupts = <16 2 1 27
266 16 2 1 26>;
267 };
268
269 corenet-cf@18000 {
270 compatible = "fsl,corenet-cf";
271 reg = <0x18000 0x1000>;
272 interrupts = <16 2 1 31>;
273 fsl,ccf-num-csdids = <32>;
274 fsl,ccf-num-snoopids = <32>;
275 };
276
277 iommu@20000 {
278 compatible = "fsl,pamu-v1.0", "fsl,pamu";
279 reg = <0x20000 0x4000>;
280 interrupts = <
281 24 2 0 0
282 16 2 1 30>;
283 };
284
285/include/ "qoriq-mpic.dtsi"
286
287 guts: global-utilities@e0000 {
288 compatible = "fsl,qoriq-device-config-1.0";
289 reg = <0xe0000 0xe00>;
290 fsl,has-rstcr;
291 #sleep-cells = <1>;
292 fsl,liodn-bits = <12>;
293 };
294
295 pins: global-utilities@e0e00 {
296 compatible = "fsl,qoriq-pin-control-1.0";
297 reg = <0xe0e00 0x200>;
298 #sleep-cells = <2>;
299 };
300
301 clockgen: global-utilities@e1000 {
302 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
303 reg = <0xe1000 0x1000>;
304 clock-frequency = <0>;
305 };
306
307 rcpm: global-utilities@e2000 {
308 compatible = "fsl,qoriq-rcpm-1.0";
309 reg = <0xe2000 0x1000>;
310 #sleep-cells = <1>;
311 };
312
313 sfp: sfp@e8000 {
314 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
315 reg = <0xe8000 0x1000>;
316 };
317
318 serdes: serdes@ea000 {
319 compatible = "fsl,p5020-serdes";
320 reg = <0xea000 0x1000>;
321 };
322
323/include/ "qoriq-dma-0.dtsi"
324/include/ "qoriq-dma-1.dtsi"
325/include/ "qoriq-espi-0.dtsi"
326 spi@110000 {
327 fsl,espi-num-chipselects = <4>;
328 };
329
330/include/ "qoriq-esdhc-0.dtsi"
331 sdhc@114000 {
332 sdhci,auto-cmd12;
333 };
334
335/include/ "qoriq-i2c-0.dtsi"
336/include/ "qoriq-i2c-1.dtsi"
337/include/ "qoriq-duart-0.dtsi"
338/include/ "qoriq-duart-1.dtsi"
339/include/ "qoriq-gpio-0.dtsi"
340/include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 {
342 phy_type = "utmi";
343 port0;
344 };
345
346/include/ "qoriq-usb2-dr-0.dtsi"
347 usb1: usb@211000 {
348 dr_mode = "host";
349 phy_type = "utmi";
350 };
351
352/include/ "qoriq-sata2-0.dtsi"
353/include/ "qoriq-sata2-1.dtsi"
354/include/ "qoriq-sec4.2-0.dtsi"
355};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
new file mode 100644
index 00000000000..ae823a47584
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -0,0 +1,96 @@
1/*
2 * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P5020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e5500@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e5500@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 };
96};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
new file mode 100644
index 00000000000..b5b37ad30e7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma@21300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x21300 0x4>;
40 ranges = <0x0 0x21100 0x200>;
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <20 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <21 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <22 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <23 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
new file mode 100644
index 00000000000..28cb8a55d80
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma@c300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0xc300 0x4>;
40 ranges = <0x0 0xc100 0x200>;
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <76 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <77 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <78 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <79 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
new file mode 100644
index 00000000000..5e268fdb9d1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -0,0 +1,51 @@
1/*
2 * PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial0: serial@4500 {
36 cell-index = <0>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x4500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <42 2 0 0>;
42};
43
44serial1: serial@4600 {
45 cell-index = <1>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x4600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <42 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
new file mode 100644
index 00000000000..5743433e278
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sdhc@2e000 {
36 compatible = "fsl,esdhc";
37 reg = <0x2e000 0x1000>;
38 interrupts = <72 0x2 0 0>;
39 /* Filled in by U-Boot */
40 clock-frequency = <0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
new file mode 100644
index 00000000000..75854b2e039
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 eSPI device tree stub [ controller @ offset 0x7000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35spi@7000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,mpc8536-espi";
39 reg = <0x7000 0x1000>;
40 interrupts = <59 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
new file mode 100644
index 00000000000..a1979ae334a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@24000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x24000 0x1000>;
43 ranges = <0x0 0x24000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
46};
47
48mdio@24520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-mdio";
52 reg = <0x24520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
new file mode 100644
index 00000000000..4c4fdde1ec2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@25000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x25000 0x1000>;
43 ranges = <0x0 0x25000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
46};
47
48mdio@25520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x25520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
new file mode 100644
index 00000000000..4b8ab438668
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@26000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <2>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
46};
47
48mdio@26520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x26520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
new file mode 100644
index 00000000000..40c9137729a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@27000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <3>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x27000 0x1000>;
43 ranges = <0x0 0x27000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
46};
47
48mdio@27520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x27520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
new file mode 100644
index 00000000000..efe2ca04bce
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
@@ -0,0 +1,39 @@
1/*
2 * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ptp_clock@24e00 {
36 compatible = "fsl,etsec-ptp";
37 reg = <0x24e00 0xb0>;
38 interrupts = <68 2 0 0 69 2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
new file mode 100644
index 00000000000..1382fec9e8c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
@@ -0,0 +1,60 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36mdio@24000 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-mdio";
40 reg = <0x24000 0x1000 0xb0030 0x4>;
41};
42
43ethernet@b0000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "network";
47 model = "eTSEC";
48 compatible = "fsl,etsec2";
49 fsl,num_rx_queues = <0x8>;
50 fsl,num_tx_queues = <0x8>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
53
54 queue-group@b0000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0xb0000 0x1000>;
58 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
59 };
60};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
new file mode 100644
index 00000000000..221cd2ea5b3
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
@@ -0,0 +1,60 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36mdio@25000 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-tbi";
40 reg = <0x25000 0x1000 0xb1030 0x4>;
41};
42
43ethernet@b1000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "network";
47 model = "eTSEC";
48 compatible = "fsl,etsec2";
49 fsl,num_rx_queues = <0x8>;
50 fsl,num_tx_queues = <0x8>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
53
54 queue-group@b1000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0xb1000 0x1000>;
58 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
59 };
60};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
new file mode 100644
index 00000000000..61456c31760
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
@@ -0,0 +1,59 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mdio@26000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,etsec2-tbi";
39 reg = <0x26000 0x1000 0xb1030 0x4>;
40};
41
42ethernet@b2000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 device_type = "network";
46 model = "eTSEC";
47 compatible = "fsl,etsec2";
48 fsl,num_rx_queues = <0x8>;
49 fsl,num_tx_queues = <0x8>;
50 fsl,magic-packet;
51 local-mac-address = [ 00 00 00 00 00 00 ];
52
53 queue-group@b2000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0xb2000 0x1000>;
57 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
58 };
59};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 00000000000..034ab8fac22
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet0_grp2 {
36 queue-group@b4000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb4000 0x1000>;
40 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 00000000000..3be9ba3b374
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet1_grp2 {
36 queue-group@b5000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb5000 0x1000>;
40 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 00000000000..02a33457048
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet2_grp2 {
36 queue-group@b6000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb6000 0x1000>;
40 interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
new file mode 100644
index 00000000000..72a3ef5945c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 GPIO device tree stub [ controller @ offset 0xf000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio-controller@f000 {
36 #gpio-cells = <2>;
37 compatible = "fsl,pq3-gpio";
38 reg = <0xf000 0x100>;
39 interrupts = <47 0x2 0 0>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
new file mode 100644
index 00000000000..d1dd6fb82a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 I2C device tree stub [ controller @ offset 0x3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@3000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <0>;
39 compatible = "fsl-i2c";
40 reg = <0x3000 0x100>;
41 interrupts = <43 2 0 0>;
42 dfsrr;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
new file mode 100644
index 00000000000..a9bd803e209
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 I2C device tree stub [ controller @ offset 0x3100 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@3100 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <1>;
39 compatible = "fsl-i2c";
40 reg = <0x3100 0x100>;
41 interrupts = <43 2 0 0>;
42 dfsrr;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
new file mode 100644
index 00000000000..8734cffae1a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35timer@42100 {
36 compatible = "fsl,mpic-global-timer";
37 reg = <0x42100 0x100 0x42300 4>;
38 interrupts = <4 0 3 0
39 5 0 3 0
40 6 0 3 0
41 7 0 3 0>;
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
new file mode 100644
index 00000000000..5c804606584
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42};
43
44timer@41100 {
45 compatible = "fsl,mpic-global-timer";
46 reg = <0x41100 0x100 0x41300 4>;
47 interrupts = <0 0 3 0
48 1 0 3 0
49 2 0 3 0
50 3 0 3 0>;
51};
52
53msi@41600 {
54 compatible = "fsl,mpic-msi";
55 reg = <0x41600 0x80>;
56 msi-available-ranges = <0 0x100>;
57 interrupts = <
58 0xe0 0 0 0
59 0xe1 0 0 0
60 0xe2 0 0 0
61 0xe3 0 0 0
62 0xe4 0 0 0
63 0xe5 0 0 0
64 0xe6 0 0 0
65 0xe7 0 0 0>;
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
new file mode 100644
index 00000000000..587ca9ffad7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
@@ -0,0 +1,68 @@
1/*
2 * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35rmu: rmu@d3000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,srio-rmu";
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
41
42 message-unit@0 {
43 compatible = "fsl,srio-msg-unit";
44 reg = <0x0 0x100>;
45 interrupts = <
46 53 2 0 0 /* msg1_tx_irq */
47 54 2 0 0>;/* msg1_rx_irq */
48 };
49 message-unit@100 {
50 compatible = "fsl,srio-msg-unit";
51 reg = <0x100 0x100>;
52 interrupts = <
53 55 2 0 0 /* msg2_tx_irq */
54 56 2 0 0>;/* msg2_rx_irq */
55 };
56 doorbell-unit@400 {
57 compatible = "fsl,srio-dbell-unit";
58 reg = <0x400 0x80>;
59 interrupts = <
60 49 2 0 0 /* bell_outb_irq */
61 50 2 0 0>;/* bell_inb_irq */
62 };
63 port-write-unit@4e0 {
64 compatible = "fsl,srio-port-write-unit";
65 reg = <0x4e0 0x20>;
66 interrupts = <48 2 0 0>;
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
new file mode 100644
index 00000000000..3c28dd08d38
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
@@ -0,0 +1,40 @@
1/*
2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@18000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x18000 0x1000>;
38 cell-index = <1>;
39 interrupts = <74 0x2 0 0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
new file mode 100644
index 00000000000..eefaf2855e3
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
@@ -0,0 +1,40 @@
1/*
2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@19000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x19000 0x1000>;
38 cell-index = <2>;
39 interrupts = <41 0x2 0 0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
new file mode 100644
index 00000000000..02a5c7ae72d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec2.1", "fsl,sec2.0";
37 reg = <0x30000 0x10000>;
38 interrupts = <45 2 0 0>;
39 fsl,num-channels = <4>;
40 fsl,channel-fifo-len = <24>;
41 fsl,exec-units-mask = <0xfe>;
42 fsl,descriptor-types-mask = <0x12b0ebf>;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
new file mode 100644
index 00000000000..bba1ba44ccf
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0x9fe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
new file mode 100644
index 00000000000..8f0a5669bee
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.1", "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0xbfe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
new file mode 100644
index 00000000000..c227f2748a2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0x97c>;
44 fsl,descriptor-types-mask = <0x3a30abf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
new file mode 100644
index 00000000000..bf957a7fca2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -0,0 +1,65 @@
1/*
2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec4.4", "fsl,sec4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>;
41
42 sec_jr0: jr@1000 {
43 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
44 reg = <0x1000 0x1000>;
45 interrupts = <45 2 0 0>;
46 };
47
48 sec_jr1: jr@2000 {
49 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
50 reg = <0x2000 0x1000>;
51 interrupts = <45 2 0 0>;
52 };
53
54 sec_jr2: jr@3000 {
55 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
56 reg = <0x3000 0x1000>;
57 interrupts = <45 2 0 0>;
58 };
59
60 sec_jr3: jr@4000 {
61 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
62 reg = <0x4000 0x1000>;
63 interrupts = <45 2 0 0>;
64 };
65};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
new file mode 100644
index 00000000000..185ab9dc3ec
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 USB DR device tree stub [ controller @ offset 0x22000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@22000 {
36 compatible = "fsl-usb2-dr";
37 reg = <0x22000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <28 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
new file mode 100644
index 00000000000..fe24cd612ff
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 USB DR device tree stub [ controller @ offset 0x23000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@23000 {
36 compatible = "fsl-usb2-dr";
37 reg = <0x23000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <46 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
new file mode 100644
index 00000000000..1aebf3ea4ca
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
@@ -0,0 +1,66 @@
1/*
2 * QorIQ DMA device tree stub [ controller @ offset 0x100000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x100300 0x4>;
40 ranges = <0x0 0x100100 0x200>;
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <28 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <29 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <30 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <31 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
new file mode 100644
index 00000000000..ecf5e180fe7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
@@ -0,0 +1,66 @@
1/*
2 * QorIQ DMA device tree stub [ controller @ offset 0x101000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x101300 0x4>;
40 ranges = <0x0 0x101100 0x200>;
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <32 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <33 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <34 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <35 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
new file mode 100644
index 00000000000..225c07b4e8a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
@@ -0,0 +1,51 @@
1/*
2 * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial0: serial@11c500 {
36 cell-index = <0>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x11c500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <36 2 0 0>;
42};
43
44serial1: serial@11c600 {
45 cell-index = <1>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x11c600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <36 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
new file mode 100644
index 00000000000..d23233a56b9
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
@@ -0,0 +1,51 @@
1/*
2 * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial2: serial@11d500 {
36 cell-index = <2>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x11d500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <37 2 0 0>;
42};
43
44serial3: serial@11d600 {
45 cell-index = <3>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x11d600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <37 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
new file mode 100644
index 00000000000..20835ae216c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
@@ -0,0 +1,40 @@
1/*
2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sdhc: sdhc@114000 {
36 compatible = "fsl,esdhc";
37 reg = <0x114000 0x1000>;
38 interrupts = <48 2 0 0>;
39 clock-frequency = <0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
new file mode 100644
index 00000000000..6db06975e09
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35spi@110000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,mpc8536-espi";
39 reg = <0x110000 0x1000>;
40 interrupts = <53 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
new file mode 100644
index 00000000000..cf714f5f68b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ GPIO device tree stub [ controller @ offset 0x130000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio0: gpio@130000 {
36 compatible = "fsl,qoriq-gpio";
37 reg = <0x130000 0x1000>;
38 interrupts = <55 2 0 0>;
39 #gpio-cells = <2>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
new file mode 100644
index 00000000000..5f9bf7debe4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
@@ -0,0 +1,53 @@
1/*
2 * QorIQ I2C device tree stub [ controller @ offset 0x118000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@118000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <0>;
39 compatible = "fsl-i2c";
40 reg = <0x118000 0x100>;
41 interrupts = <38 2 0 0>;
42 dfsrr;
43};
44
45i2c@118100 {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cell-index = <1>;
49 compatible = "fsl-i2c";
50 reg = <0x118100 0x100>;
51 interrupts = <38 2 0 0>;
52 dfsrr;
53};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
new file mode 100644
index 00000000000..7989bf5eeb5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
@@ -0,0 +1,53 @@
1/*
2 * QorIQ I2C device tree stub [ controller @ offset 0x119000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@119000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <2>;
39 compatible = "fsl-i2c";
40 reg = <0x119000 0x100>;
41 interrupts = <39 2 0 0>;
42 dfsrr;
43};
44
45i2c@119100 {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cell-index = <3>;
49 compatible = "fsl-i2c";
50 reg = <0x119100 0x100>;
51 interrupts = <39 2 0 0>;
52 dfsrr;
53};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
new file mode 100644
index 00000000000..b9bada6a87d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -0,0 +1,106 @@
1/*
2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
43};
44
45timer@41100 {
46 compatible = "fsl,mpic-global-timer";
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
52};
53
54msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
56 reg = <0x41600 0x200>;
57 msi-available-ranges = <0 0x100>;
58 interrupts = <
59 0xe0 0 0 0
60 0xe1 0 0 0
61 0xe2 0 0 0
62 0xe3 0 0 0
63 0xe4 0 0 0
64 0xe5 0 0 0
65 0xe6 0 0 0
66 0xe7 0 0 0>;
67};
68
69msi1: msi@41800 {
70 compatible = "fsl,mpic-msi";
71 reg = <0x41800 0x200>;
72 msi-available-ranges = <0 0x100>;
73 interrupts = <
74 0xe8 0 0 0
75 0xe9 0 0 0
76 0xea 0 0 0
77 0xeb 0 0 0
78 0xec 0 0 0
79 0xed 0 0 0
80 0xee 0 0 0
81 0xef 0 0 0>;
82};
83
84msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi";
86 reg = <0x41a00 0x200>;
87 msi-available-ranges = <0 0x100>;
88 interrupts = <
89 0xf0 0 0 0
90 0xf1 0 0 0
91 0xf2 0 0 0
92 0xf3 0 0 0
93 0xf4 0 0 0
94 0xf5 0 0 0
95 0xf6 0 0 0
96 0xf7 0 0 0>;
97};
98
99timer@42100 {
100 compatible = "fsl,mpic-global-timer";
101 reg = <0x42100 0x100 0x42300 4>;
102 interrupts = <4 0 3 0
103 5 0 3 0
104 6 0 3 0
105 7 0 3 0>;
106};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
new file mode 100644
index 00000000000..ca7fec792e5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
@@ -0,0 +1,68 @@
1/*
2 * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35rmu: rmu@d3000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,srio-rmu";
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
41
42 message-unit@0 {
43 compatible = "fsl,srio-msg-unit";
44 reg = <0x0 0x100>;
45 interrupts = <
46 60 2 0 0 /* msg1_tx_irq */
47 61 2 0 0>;/* msg1_rx_irq */
48 };
49 message-unit@100 {
50 compatible = "fsl,srio-msg-unit";
51 reg = <0x100 0x100>;
52 interrupts = <
53 62 2 0 0 /* msg2_tx_irq */
54 63 2 0 0>;/* msg2_rx_irq */
55 };
56 doorbell-unit@400 {
57 compatible = "fsl,srio-dbell-unit";
58 reg = <0x400 0x80>;
59 interrupts = <
60 56 2 0 0 /* bell_outb_irq */
61 57 2 0 0>;/* bell_inb_irq */
62 };
63 port-write-unit@4e0 {
64 compatible = "fsl,srio-port-write-unit";
65 reg = <0x4e0 0x20>;
66 interrupts = <16 2 1 11>;
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
new file mode 100644
index 00000000000..b642047fdec
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
@@ -0,0 +1,39 @@
1/*
2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@220000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x220000 0x1000>;
38 interrupts = <68 0x2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
new file mode 100644
index 00000000000..c5737025975
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
@@ -0,0 +1,39 @@
1/*
2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@221000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x221000 0x1000>;
38 interrupts = <69 0x2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
new file mode 100644
index 00000000000..0cbbac32953
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,100 @@
1/*
2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.0-job-ring";
45 reg = <0x1000 0x1000>;
46 interrupts = <88 2 0 0>;
47 };
48
49 sec_jr1: jr@2000 {
50 compatible = "fsl,sec-v4.0-job-ring";
51 reg = <0x2000 0x1000>;
52 interrupts = <89 2 0 0>;
53 };
54
55 sec_jr2: jr@3000 {
56 compatible = "fsl,sec-v4.0-job-ring";
57 reg = <0x3000 0x1000>;
58 interrupts = <90 2 0 0>;
59 };
60
61 sec_jr3: jr@4000 {
62 compatible = "fsl,sec-v4.0-job-ring";
63 reg = <0x4000 0x1000>;
64 interrupts = <91 2 0 0>;
65 };
66
67 rtic@6000 {
68 compatible = "fsl,sec-v4.0-rtic";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 reg = <0x6000 0x100>;
72 ranges = <0x0 0x6100 0xe00>;
73
74 rtic_a: rtic-a@0 {
75 compatible = "fsl,sec-v4.0-rtic-memory";
76 reg = <0x00 0x20 0x100 0x80>;
77 };
78
79 rtic_b: rtic-b@20 {
80 compatible = "fsl,sec-v4.0-rtic-memory";
81 reg = <0x20 0x20 0x200 0x80>;
82 };
83
84 rtic_c: rtic-c@40 {
85 compatible = "fsl,sec-v4.0-rtic-memory";
86 reg = <0x40 0x20 0x300 0x80>;
87 };
88
89 rtic_d: rtic-d@60 {
90 compatible = "fsl,sec-v4.0-rtic-memory";
91 reg = <0x60 0x20 0x500 0x80>;
92 };
93 };
94};
95
96sec_mon: sec_mon@314000 {
97 compatible = "fsl,sec-v4.0-mon";
98 reg = <0x314000 0x1000>;
99 interrupts = <93 2 0 0>;
100};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
new file mode 100644
index 00000000000..3308986bba0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
@@ -0,0 +1,109 @@
1/*
2 * QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.1-job-ring",
45 "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
48 };
49
50 sec_jr1: jr@2000 {
51 compatible = "fsl,sec-v4.1-job-ring",
52 "fsl,sec-v4.0-job-ring";
53 reg = <0x2000 0x1000>;
54 interrupts = <89 2 0 0>;
55 };
56
57 sec_jr2: jr@3000 {
58 compatible = "fsl,sec-v4.1-job-ring",
59 "fsl,sec-v4.0-job-ring";
60 reg = <0x3000 0x1000>;
61 interrupts = <90 2 0 0>;
62 };
63
64 sec_jr3: jr@4000 {
65 compatible = "fsl,sec-v4.1-job-ring",
66 "fsl,sec-v4.0-job-ring";
67 reg = <0x4000 0x1000>;
68 interrupts = <91 2 0 0>;
69 };
70
71 rtic@6000 {
72 compatible = "fsl,sec-v4.1-rtic",
73 "fsl,sec-v4.0-rtic";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x6000 0x100>;
77 ranges = <0x0 0x6100 0xe00>;
78
79 rtic_a: rtic-a@0 {
80 compatible = "fsl,sec-v4.1-rtic-memory",
81 "fsl,sec-v4.0-rtic-memory";
82 reg = <0x00 0x20 0x100 0x80>;
83 };
84
85 rtic_b: rtic-b@20 {
86 compatible = "fsl,sec-v4.1-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x20 0x20 0x200 0x80>;
89 };
90
91 rtic_c: rtic-c@40 {
92 compatible = "fsl,sec-v4.1-rtic-memory",
93 "fsl,sec-v4.0-rtic-memory";
94 reg = <0x40 0x20 0x300 0x80>;
95 };
96
97 rtic_d: rtic-d@60 {
98 compatible = "fsl,sec-v4.1-rtic-memory",
99 "fsl,sec-v4.0-rtic-memory";
100 reg = <0x60 0x20 0x500 0x80>;
101 };
102 };
103};
104
105sec_mon: sec_mon@314000 {
106 compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
107 reg = <0x314000 0x1000>;
108 interrupts = <93 2 0 0>;
109};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
new file mode 100644
index 00000000000..7990e0d3d6f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,109 @@
1/*
2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.2-job-ring",
45 "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
48 };
49
50 sec_jr1: jr@2000 {
51 compatible = "fsl,sec-v4.2-job-ring",
52 "fsl,sec-v4.0-job-ring";
53 reg = <0x2000 0x1000>;
54 interrupts = <89 2 0 0>;
55 };
56
57 sec_jr2: jr@3000 {
58 compatible = "fsl,sec-v4.2-job-ring",
59 "fsl,sec-v4.0-job-ring";
60 reg = <0x3000 0x1000>;
61 interrupts = <90 2 0 0>;
62 };
63
64 sec_jr3: jr@4000 {
65 compatible = "fsl,sec-v4.2-job-ring",
66 "fsl,sec-v4.0-job-ring";
67 reg = <0x4000 0x1000>;
68 interrupts = <91 2 0 0>;
69 };
70
71 rtic@6000 {
72 compatible = "fsl,sec-v4.2-rtic",
73 "fsl,sec-v4.0-rtic";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x6000 0x100>;
77 ranges = <0x0 0x6100 0xe00>;
78
79 rtic_a: rtic-a@0 {
80 compatible = "fsl,sec-v4.2-rtic-memory",
81 "fsl,sec-v4.0-rtic-memory";
82 reg = <0x00 0x20 0x100 0x80>;
83 };
84
85 rtic_b: rtic-b@20 {
86 compatible = "fsl,sec-v4.2-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x20 0x20 0x200 0x80>;
89 };
90
91 rtic_c: rtic-c@40 {
92 compatible = "fsl,sec-v4.2-rtic-memory",
93 "fsl,sec-v4.0-rtic-memory";
94 reg = <0x40 0x20 0x300 0x80>;
95 };
96
97 rtic_d: rtic-d@60 {
98 compatible = "fsl,sec-v4.2-rtic-memory",
99 "fsl,sec-v4.0-rtic-memory";
100 reg = <0x60 0x20 0x500 0x80>;
101 };
102 };
103};
104
105sec_mon: sec_mon@314000 {
106 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
107 reg = <0x314000 0x1000>;
108 interrupts = <93 2 0 0>;
109};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
new file mode 100644
index 00000000000..4dd6f84c239
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@211000 {
36 compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
37 reg = <0x211000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <45 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
new file mode 100644
index 00000000000..f053835aa1c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@210000 {
36 compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
37 reg = <0x210000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 2266bbb303d..38dcb96c8e2 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -339,7 +339,7 @@
339 serial0: serial@4500 { 339 serial0: serial@4500 {
340 cell-index = <0>; 340 cell-index = <0>;
341 device_type = "serial"; 341 device_type = "serial";
342 compatible = "ns16550"; 342 compatible = "fsl,ns16550", "ns16550";
343 reg = <0x4500 0x100>; 343 reg = <0x4500 0x100>;
344 clock-frequency = <0>; 344 clock-frequency = <0>;
345 interrupts = <0x2a 0x2>; 345 interrupts = <0x2a 0x2>;
@@ -349,7 +349,7 @@
349 serial1: serial@4600 { 349 serial1: serial@4600 {
350 cell-index = <1>; 350 cell-index = <1>;
351 device_type = "serial"; 351 device_type = "serial";
352 compatible = "ns16550"; 352 compatible = "fsl,ns16550", "ns16550";
353 reg = <0x4600 0x100>; 353 reg = <0x4600 0x100>;
354 clock-frequency = <0>; 354 clock-frequency = <0>;
355 interrupts = <0x1c 0x2>; 355 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 429e87d9ace..5ab8932d09b 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>; 343 interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
347 serial1: serial@4600 { 347 serial1: serial@4600 {
348 cell-index = <1>; 348 cell-index = <1>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4600 0x100>; 351 reg = <0x4600 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>; 353 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index d81201ac2ca..d5341f5741a 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>; 343 interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
347 serial1: serial@4600 { 347 serial1: serial@4600 {
348 cell-index = <1>; 348 cell-index = <1>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4600 0x100>; 351 reg = <0x4600 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>; 353 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/klondike.dts b/arch/powerpc/boot/dts/klondike.dts
new file mode 100644
index 00000000000..8c942903361
--- /dev/null
+++ b/arch/powerpc/boot/dts/klondike.dts
@@ -0,0 +1,227 @@
1/*
2 * Device Tree for Klondike (APM8018X) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tanmay Inamdar <tinamdar@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 model = "apm,klondike";
30 compatible = "apm,klondike";
31 dcr-parent = <&{/cpus/cpu@0}>;
32
33 aliases {
34 ethernet0 = &EMAC0;
35 ethernet1 = &EMAC1;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 device_type = "cpu";
44 model = "PowerPC,apm8018x";
45 reg = <0x00000000>;
46 clock-frequency = <300000000>; /* Filled in by U-Boot */
47 timebase-frequency = <300000000>; /* Filled in by U-Boot */
48 i-cache-line-size = <32>;
49 d-cache-line-size = <32>;
50 i-cache-size = <16384>; /* 16 kB */
51 d-cache-size = <16384>; /* 16 kB */
52 dcr-controller;
53 dcr-access-method = "native";
54 };
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
60 };
61
62 UIC0: interrupt-controller {
63 compatible = "ibm,uic";
64 interrupt-controller;
65 cell-index = <0>;
66 dcr-reg = <0x0c0 0x010>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 };
71
72 UIC1: interrupt-controller1 {
73 compatible = "ibm,uic";
74 interrupt-controller;
75 cell-index = <1>;
76 dcr-reg = <0x0d0 0x010>;
77 #address-cells = <0>;
78 #size-cells = <0>;
79 #interrupt-cells = <2>;
80 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
81 interrupt-parent = <&UIC0>;
82 };
83
84 UIC2: interrupt-controller2 {
85 compatible = "ibm,uic";
86 interrupt-controller;
87 cell-index = <2>;
88 dcr-reg = <0x0e0 0x010>;
89 #address-cells = <0>;
90 #size-cells = <0>;
91 #interrupt-cells = <2>;
92 interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
93 interrupt-parent = <&UIC0>;
94 };
95
96 UIC3: interrupt-controller3 {
97 compatible = "ibm,uic";
98 interrupt-controller;
99 cell-index = <3>;
100 dcr-reg = <0x0f0 0x010>;
101 #address-cells = <0>;
102 #size-cells = <0>;
103 #interrupt-cells = <2>;
104 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
105 interrupt-parent = <&UIC0>;
106 };
107
108 plb {
109 compatible = "ibm,plb4";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113 clock-frequency = <0>; /* Filled in by U-Boot */
114
115 SDRAM0: memory-controller {
116 compatible = "ibm,sdram-apm8018x";
117 dcr-reg = <0x010 0x002>;
118 };
119
120 MAL0: mcmal {
121 compatible = "ibm,mcmal2";
122 dcr-reg = <0x180 0x062>;
123 num-tx-chans = <2>;
124 num-rx-chans = <16>;
125 #address-cells = <0>;
126 #size-cells = <0>;
127 interrupt-parent = <&UIC1>;
128 interrupts = </*TXEOB*/ 0x6 0x4
129 /*RXEOB*/ 0x7 0x4
130 /*SERR*/ 0x1 0x4
131 /*TXDE*/ 0x2 0x4
132 /*RXDE*/ 0x3 0x4>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0x20000000 0x20000000 0x30000000
140 0x50000000 0x50000000 0x10000000
141 0x60000000 0x60000000 0x10000000
142 0xFE000000 0xFE000000 0x00010000>;
143 dcr-reg = <0x100 0x020>;
144 clock-frequency = <300000000>; /* Filled in by U-Boot */
145
146 RGMII0: emac-rgmii@400a2000 {
147 compatible = "ibm,rgmii";
148 reg = <0x400a2000 0x00000010>;
149 has-mdio;
150 };
151
152 TAH0: emac-tah@400a3000 {
153 compatible = "ibm,tah";
154 reg = <0x400a3000 0x100>;
155 };
156
157 TAH1: emac-tah@400a4000 {
158 compatible = "ibm,tah";
159 reg = <0x400a4000 0x100>;
160 };
161
162 EMAC0: ethernet@400a0000 {
163 compatible = "ibm,emac4", "ibm-emac4sync";
164 interrupt-parent = <&EMAC0>;
165 interrupts = <0x0>;
166 #interrupt-cells = <1>;
167 #address-cells = <0>;
168 #size-cells = <0>;
169 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
170 reg = <0x400a0000 0x00000100>;
171 local-mac-address = [000000000000]; /* Filled in by U-Boot */
172 mal-device = <&MAL0>;
173 mal-tx-channel = <0x0>;
174 mal-rx-channel = <0x0>;
175 cell-index = <0>;
176 max-frame-size = <9000>;
177 rx-fifo-size = <4096>;
178 tx-fifo-size = <2048>;
179 phy-mode = "rgmii";
180 phy-address = <0x2>;
181 turbo = "no";
182 phy-map = <0x00000000>;
183 rgmii-device = <&RGMII0>;
184 rgmii-channel = <0>;
185 tah-device = <&TAH0>;
186 tah-channel = <0>;
187 has-inverted-stacr-oc;
188 has-new-stacr-staopc;
189 };
190
191 EMAC1: ethernet@400a1000 {
192 compatible = "ibm,emac4", "ibm-emac4sync";
193 status = "disabled";
194 interrupt-parent = <&EMAC1>;
195 interrupts = <0x0>;
196 #interrupt-cells = <1>;
197 #address-cells = <0>;
198 #size-cells = <0>;
199 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
200 reg = <0x400a1000 0x00000100>;
201 local-mac-address = [000000000000]; /* Filled in by U-Boot */
202 mal-device = <&MAL0>;
203 mal-tx-channel = <1>;
204 mal-rx-channel = <8>;
205 cell-index = <1>;
206 max-frame-size = <9000>;
207 rx-fifo-size = <4096>;
208 tx-fifo-size = <2048>;
209 phy-mode = "rgmii";
210 phy-address = <0x3>;
211 turbo = "no";
212 phy-map = <0x00000000>;
213 rgmii-device = <&RGMII0>;
214 rgmii-channel = <1>;
215 tah-device = <&TAH1>;
216 tah-channel = <0>;
217 has-inverted-stacr-oc;
218 has-new-stacr-staopc;
219 mdio-device = <&EMAC0>;
220 };
221 };
222 };
223
224 chosen {
225 linux,stdout-path = "/plb/opb/serial@50001000";
226 };
227};
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index d16bae1230f..983aee18579 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -80,7 +80,7 @@
80 serial0: serial@4500 { 80 serial0: serial@4500 {
81 cell-index = <0>; 81 cell-index = <0>;
82 device_type = "serial"; 82 device_type = "serial";
83 compatible = "ns16550"; 83 compatible = "fsl,ns16550", "ns16550";
84 reg = <0x4500 0x100>; 84 reg = <0x4500 0x100>;
85 clock-frequency = <264000000>; 85 clock-frequency = <264000000>;
86 interrupts = <9 0x8>; 86 interrupts = <9 0x8>;
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 8d725d10882..0a4545159e8 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
84 serial0: serial@80004500 { 84 serial0: serial@80004500 {
85 cell-index = <0>; 85 cell-index = <0>;
86 device_type = "serial"; 86 device_type = "serial";
87 compatible = "ns16550"; 87 compatible = "fsl,ns16550", "ns16550";
88 reg = <0x80004500 0x8>; 88 reg = <0x80004500 0x8>;
89 clock-frequency = <97553800>; 89 clock-frequency = <97553800>;
90 current-speed = <9600>; 90 current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
95 serial1: serial@80004600 { 95 serial1: serial@80004600 {
96 cell-index = <1>; 96 cell-index = <1>;
97 device_type = "serial"; 97 device_type = "serial";
98 compatible = "ns16550"; 98 compatible = "fsl,ns16550", "ns16550";
99 reg = <0x80004600 0x8>; 99 reg = <0x80004600 0x8>;
100 clock-frequency = <97553800>; 100 clock-frequency = <97553800>;
101 current-speed = <57600>; 101 current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index b13a11eb81b..0e758b347cd 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
84 serial0: serial@80004500 { 84 serial0: serial@80004500 {
85 cell-index = <0>; 85 cell-index = <0>;
86 device_type = "serial"; 86 device_type = "serial";
87 compatible = "ns16550"; 87 compatible = "fsl,ns16550", "ns16550";
88 reg = <0x80004500 0x8>; 88 reg = <0x80004500 0x8>;
89 clock-frequency = <130041000>; 89 clock-frequency = <130041000>;
90 current-speed = <9600>; 90 current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
95 serial1: serial@80004600 { 95 serial1: serial@80004600 {
96 cell-index = <1>; 96 cell-index = <1>;
97 device_type = "serial"; 97 device_type = "serial";
98 compatible = "ns16550"; 98 compatible = "fsl,ns16550", "ns16550";
99 reg = <0x80004600 0x8>; 99 reg = <0x80004600 0x8>;
100 clock-frequency = <130041000>; 100 clock-frequency = <130041000>;
101 current-speed = <57600>; 101 current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 697b3f6b78b..22b0832b6c3 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -233,7 +233,7 @@
233 serial0: serial@4500 { 233 serial0: serial@4500 {
234 cell-index = <0>; 234 cell-index = <0>;
235 device_type = "serial"; 235 device_type = "serial";
236 compatible = "ns16550"; 236 compatible = "fsl,ns16550", "ns16550";
237 reg = <0x4500 0x100>; 237 reg = <0x4500 0x100>;
238 clock-frequency = <133333333>; 238 clock-frequency = <133333333>;
239 interrupts = <9 0x8>; 239 interrupts = <9 0x8>;
@@ -243,7 +243,7 @@
243 serial1: serial@4600 { 243 serial1: serial@4600 {
244 cell-index = <1>; 244 cell-index = <1>;
245 device_type = "serial"; 245 device_type = "serial";
246 compatible = "ns16550"; 246 compatible = "fsl,ns16550", "ns16550";
247 reg = <0x4600 0x100>; 247 reg = <0x4600 0x100>;
248 clock-frequency = <133333333>; 248 clock-frequency = <133333333>;
249 interrupts = <10 0x8>; 249 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a0bd1881081..f66d10d95a8 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -208,7 +208,7 @@
208 serial0: serial@4500 { 208 serial0: serial@4500 {
209 cell-index = <0>; 209 cell-index = <0>;
210 device_type = "serial"; 210 device_type = "serial";
211 compatible = "ns16550"; 211 compatible = "fsl,ns16550", "ns16550";
212 reg = <0x4500 0x100>; 212 reg = <0x4500 0x100>;
213 clock-frequency = <133333333>; 213 clock-frequency = <133333333>;
214 interrupts = <9 0x8>; 214 interrupts = <9 0x8>;
@@ -218,7 +218,7 @@
218 serial1: serial@4600 { 218 serial1: serial@4600 {
219 cell-index = <1>; 219 cell-index = <1>;
220 device_type = "serial"; 220 device_type = "serial";
221 compatible = "ns16550"; 221 compatible = "fsl,ns16550", "ns16550";
222 reg = <0x4600 0x100>; 222 reg = <0x4600 0x100>;
223 clock-frequency = <133333333>; 223 clock-frequency = <133333333>;
224 interrupts = <10 0x8>; 224 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index ac1eb320c7b..1c836c6c5be 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -261,7 +261,7 @@
261 serial0: serial@4500 { 261 serial0: serial@4500 {
262 cell-index = <0>; 262 cell-index = <0>;
263 device_type = "serial"; 263 device_type = "serial";
264 compatible = "ns16550"; 264 compatible = "fsl,ns16550", "ns16550";
265 reg = <0x4500 0x100>; 265 reg = <0x4500 0x100>;
266 clock-frequency = <0>; 266 clock-frequency = <0>;
267 interrupts = <9 0x8>; 267 interrupts = <9 0x8>;
@@ -271,7 +271,7 @@
271 serial1: serial@4600 { 271 serial1: serial@4600 {
272 cell-index = <1>; 272 cell-index = <1>;
273 device_type = "serial"; 273 device_type = "serial";
274 compatible = "ns16550"; 274 compatible = "fsl,ns16550", "ns16550";
275 reg = <0x4600 0x100>; 275 reg = <0x4600 0x100>;
276 clock-frequency = <0>; 276 clock-frequency = <0>;
277 interrupts = <10 0x8>; 277 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 4dd08c32297..811848e93ae 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -265,7 +265,7 @@
265 serial0: serial@4500 { 265 serial0: serial@4500 {
266 cell-index = <0>; 266 cell-index = <0>;
267 device_type = "serial"; 267 device_type = "serial";
268 compatible = "ns16550"; 268 compatible = "fsl,ns16550", "ns16550";
269 reg = <0x4500 0x100>; 269 reg = <0x4500 0x100>;
270 clock-frequency = <133333333>; 270 clock-frequency = <133333333>;
271 interrupts = <9 0x8>; 271 interrupts = <9 0x8>;
@@ -275,7 +275,7 @@
275 serial1: serial@4600 { 275 serial1: serial@4600 {
276 cell-index = <1>; 276 cell-index = <1>;
277 device_type = "serial"; 277 device_type = "serial";
278 compatible = "ns16550"; 278 compatible = "fsl,ns16550", "ns16550";
279 reg = <0x4600 0x100>; 279 reg = <0x4600 0x100>;
280 clock-frequency = <133333333>; 280 clock-frequency = <133333333>;
281 interrupts = <10 0x8>; 281 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 05ad8c98e52..da9c72ddc34 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -105,7 +105,7 @@
105 serial0: serial@4500 { 105 serial0: serial@4500 {
106 cell-index = <0>; 106 cell-index = <0>;
107 device_type = "serial"; 107 device_type = "serial";
108 compatible = "ns16550"; 108 compatible = "fsl,ns16550", "ns16550";
109 reg = <0x4500 0x100>; 109 reg = <0x4500 0x100>;
110 clock-frequency = <0>; 110 clock-frequency = <0>;
111 interrupts = <9 0x8>; 111 interrupts = <9 0x8>;
@@ -115,7 +115,7 @@
115 serial1: serial@4600 { 115 serial1: serial@4600 {
116 cell-index = <1>; 116 cell-index = <1>;
117 device_type = "serial"; 117 device_type = "serial";
118 compatible = "ns16550"; 118 compatible = "fsl,ns16550", "ns16550";
119 reg = <0x4600 0x100>; 119 reg = <0x4600 0x100>;
120 clock-frequency = <0>; 120 clock-frequency = <0>;
121 interrupts = <10 0x8>; 121 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index f4fadb23ad6..ff7b15b340a 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -83,7 +83,7 @@
83 serial0: serial@4500 { 83 serial0: serial@4500 {
84 cell-index = <0>; 84 cell-index = <0>;
85 device_type = "serial"; 85 device_type = "serial";
86 compatible = "ns16550"; 86 compatible = "fsl,ns16550", "ns16550";
87 reg = <0x4500 0x100>; 87 reg = <0x4500 0x100>;
88 clock-frequency = <0>; 88 clock-frequency = <0>;
89 interrupts = <9 0x8>; 89 interrupts = <9 0x8>;
@@ -93,7 +93,7 @@
93 serial1: serial@4600 { 93 serial1: serial@4600 {
94 cell-index = <1>; 94 cell-index = <1>;
95 device_type = "serial"; 95 device_type = "serial";
96 compatible = "ns16550"; 96 compatible = "fsl,ns16550", "ns16550";
97 reg = <0x4600 0x100>; 97 reg = <0x4600 0x100>;
98 clock-frequency = <0>; 98 clock-frequency = <0>;
99 interrupts = <10 0x8>; 99 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 505dc842d80..2608679d0d4 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -283,7 +283,7 @@
283 serial0: serial@4500 { 283 serial0: serial@4500 {
284 cell-index = <0>; 284 cell-index = <0>;
285 device_type = "serial"; 285 device_type = "serial";
286 compatible = "ns16550"; 286 compatible = "fsl,ns16550", "ns16550";
287 reg = <0x4500 0x100>; 287 reg = <0x4500 0x100>;
288 clock-frequency = <0>; // from bootloader 288 clock-frequency = <0>; // from bootloader
289 interrupts = <9 0x8>; 289 interrupts = <9 0x8>;
@@ -293,7 +293,7 @@
293 serial1: serial@4600 { 293 serial1: serial@4600 {
294 cell-index = <1>; 294 cell-index = <1>;
295 device_type = "serial"; 295 device_type = "serial";
296 compatible = "ns16550"; 296 compatible = "fsl,ns16550", "ns16550";
297 reg = <0x4600 0x100>; 297 reg = <0x4600 0x100>;
298 clock-frequency = <0>; // from bootloader 298 clock-frequency = <0>; // from bootloader
299 interrupts = <10 0x8>; 299 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index eb732115f01..6cd044d8fb8 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -189,7 +189,7 @@
189 serial0: serial@4500 { 189 serial0: serial@4500 {
190 cell-index = <0>; 190 cell-index = <0>;
191 device_type = "serial"; 191 device_type = "serial";
192 compatible = "ns16550"; 192 compatible = "fsl,ns16550", "ns16550";
193 reg = <0x4500 0x100>; 193 reg = <0x4500 0x100>;
194 clock-frequency = <0>; // from bootloader 194 clock-frequency = <0>; // from bootloader
195 interrupts = <9 0x8>; 195 interrupts = <9 0x8>;
@@ -199,7 +199,7 @@
199 serial1: serial@4600 { 199 serial1: serial@4600 {
200 cell-index = <1>; 200 cell-index = <1>;
201 device_type = "serial"; 201 device_type = "serial";
202 compatible = "ns16550"; 202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4600 0x100>; 203 reg = <0x4600 0x100>;
204 clock-frequency = <0>; // from bootloader 204 clock-frequency = <0>; // from bootloader
205 interrupts = <10 0x8>; 205 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 230febb9b72..4552864082c 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -242,7 +242,7 @@
242 serial0: serial@4500 { 242 serial0: serial@4500 {
243 cell-index = <0>; 243 cell-index = <0>;
244 device_type = "serial"; 244 device_type = "serial";
245 compatible = "ns16550"; 245 compatible = "fsl,ns16550", "ns16550";
246 reg = <0x4500 0x100>; 246 reg = <0x4500 0x100>;
247 clock-frequency = <0>; 247 clock-frequency = <0>;
248 interrupts = <9 0x8>; 248 interrupts = <9 0x8>;
@@ -252,7 +252,7 @@
252 serial1: serial@4600 { 252 serial1: serial@4600 {
253 cell-index = <1>; 253 cell-index = <1>;
254 device_type = "serial"; 254 device_type = "serial";
255 compatible = "ns16550"; 255 compatible = "fsl,ns16550", "ns16550";
256 reg = <0x4600 0x100>; 256 reg = <0x4600 0x100>;
257 clock-frequency = <0>; 257 clock-frequency = <0>;
258 interrupts = <10 0x8>; 258 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 45cfa1c50a2..c0e450a551b 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -136,7 +136,7 @@
136 serial0: serial@4500 { 136 serial0: serial@4500 {
137 cell-index = <0>; 137 cell-index = <0>;
138 device_type = "serial"; 138 device_type = "serial";
139 compatible = "ns16550"; 139 compatible = "fsl,ns16550", "ns16550";
140 reg = <0x4500 0x100>; 140 reg = <0x4500 0x100>;
141 clock-frequency = <264000000>; 141 clock-frequency = <264000000>;
142 interrupts = <9 0x8>; 142 interrupts = <9 0x8>;
@@ -146,7 +146,7 @@
146 serial1: serial@4600 { 146 serial1: serial@4600 {
147 cell-index = <1>; 147 cell-index = <1>;
148 device_type = "serial"; 148 device_type = "serial";
149 compatible = "ns16550"; 149 compatible = "fsl,ns16550", "ns16550";
150 reg = <0x4600 0x100>; 150 reg = <0x4600 0x100>;
151 clock-frequency = <264000000>; 151 clock-frequency = <264000000>;
152 interrupts = <10 0x8>; 152 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index bdf4459677b..b6e9aec1d86 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -102,7 +102,7 @@
102 102
103 serial0: serial@4500 { 103 serial0: serial@4500 {
104 device_type = "serial"; 104 device_type = "serial";
105 compatible = "ns16550"; 105 compatible = "fsl,ns16550", "ns16550";
106 reg = <0x4500 0x100>; 106 reg = <0x4500 0x100>;
107 interrupts = <9 8>; 107 interrupts = <9 8>;
108 interrupt-parent = <&ipic>; 108 interrupt-parent = <&ipic>;
@@ -112,7 +112,7 @@
112 112
113 serial1: serial@4600 { 113 serial1: serial@4600 {
114 device_type = "serial"; 114 device_type = "serial";
115 compatible = "ns16550"; 115 compatible = "fsl,ns16550", "ns16550";
116 reg = <0x4600 0x100>; 116 reg = <0x4600 0x100>;
117 interrupts = <10 8>; 117 interrupts = <10 8>;
118 interrupt-parent = <&ipic>; 118 interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 855782c5e5e..cfccef57cd1 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -276,7 +276,7 @@
276 serial0: serial@4500 { 276 serial0: serial@4500 {
277 cell-index = <0>; 277 cell-index = <0>;
278 device_type = "serial"; 278 device_type = "serial";
279 compatible = "ns16550"; 279 compatible = "fsl,ns16550", "ns16550";
280 reg = <0x4500 0x100>; 280 reg = <0x4500 0x100>;
281 clock-frequency = <0>; 281 clock-frequency = <0>;
282 interrupts = <9 0x8>; 282 interrupts = <9 0x8>;
@@ -286,7 +286,7 @@
286 serial1: serial@4600 { 286 serial1: serial@4600 {
287 cell-index = <1>; 287 cell-index = <1>;
288 device_type = "serial"; 288 device_type = "serial";
289 compatible = "ns16550"; 289 compatible = "fsl,ns16550", "ns16550";
290 reg = <0x4600 0x100>; 290 reg = <0x4600 0x100>;
291 clock-frequency = <0>; 291 clock-frequency = <0>;
292 interrupts = <10 0x8>; 292 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index dbc1b988b29..353deff1b7f 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -321,7 +321,7 @@
321 serial0: serial@4500 { 321 serial0: serial@4500 {
322 cell-index = <0>; 322 cell-index = <0>;
323 device_type = "serial"; 323 device_type = "serial";
324 compatible = "ns16550"; 324 compatible = "fsl,ns16550", "ns16550";
325 reg = <0x4500 0x100>; 325 reg = <0x4500 0x100>;
326 clock-frequency = <0>; 326 clock-frequency = <0>;
327 interrupts = <9 0x8>; 327 interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
331 serial1: serial@4600 { 331 serial1: serial@4600 {
332 cell-index = <1>; 332 cell-index = <1>;
333 device_type = "serial"; 333 device_type = "serial";
334 compatible = "ns16550"; 334 compatible = "fsl,ns16550", "ns16550";
335 reg = <0x4600 0x100>; 335 reg = <0x4600 0x100>;
336 clock-frequency = <0>; 336 clock-frequency = <0>;
337 interrupts = <10 0x8>; 337 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
index 9ea78305696..ef4a305a0d0 100644
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -304,7 +304,7 @@
304 serial0: serial@4500 { 304 serial0: serial@4500 {
305 cell-index = <0>; 305 cell-index = <0>;
306 device_type = "serial"; 306 device_type = "serial";
307 compatible = "ns16550"; 307 compatible = "fsl,ns16550", "ns16550";
308 reg = <0x4500 0x100>; 308 reg = <0x4500 0x100>;
309 clock-frequency = <0>; 309 clock-frequency = <0>;
310 interrupts = <9 0x8>; 310 interrupts = <9 0x8>;
@@ -314,7 +314,7 @@
314 serial1: serial@4600 { 314 serial1: serial@4600 {
315 cell-index = <1>; 315 cell-index = <1>;
316 device_type = "serial"; 316 device_type = "serial";
317 compatible = "ns16550"; 317 compatible = "fsl,ns16550", "ns16550";
318 reg = <0x4600 0x100>; 318 reg = <0x4600 0x100>;
319 clock-frequency = <0>; 319 clock-frequency = <0>;
320 interrupts = <10 0x8>; 320 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index f70cf600083..538fcb92733 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -315,7 +315,7 @@
315 serial0: serial@4500 { 315 serial0: serial@4500 {
316 cell-index = <0>; 316 cell-index = <0>;
317 device_type = "serial"; 317 device_type = "serial";
318 compatible = "ns16550"; 318 compatible = "fsl,ns16550", "ns16550";
319 reg = <0x4500 0x100>; 319 reg = <0x4500 0x100>;
320 clock-frequency = <0>; 320 clock-frequency = <0>;
321 interrupts = <9 0x8>; 321 interrupts = <9 0x8>;
@@ -325,7 +325,7 @@
325 serial1: serial@4600 { 325 serial1: serial@4600 {
326 cell-index = <1>; 326 cell-index = <1>;
327 device_type = "serial"; 327 device_type = "serial";
328 compatible = "ns16550"; 328 compatible = "fsl,ns16550", "ns16550";
329 reg = <0x4600 0x100>; 329 reg = <0x4600 0x100>;
330 clock-frequency = <0>; 330 clock-frequency = <0>;
331 interrupts = <10 0x8>; 331 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 3447eb9f6e8..32333a908f3 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -321,7 +321,7 @@
321 serial0: serial@4500 { 321 serial0: serial@4500 {
322 cell-index = <0>; 322 cell-index = <0>;
323 device_type = "serial"; 323 device_type = "serial";
324 compatible = "ns16550"; 324 compatible = "fsl,ns16550", "ns16550";
325 reg = <0x4500 0x100>; 325 reg = <0x4500 0x100>;
326 clock-frequency = <0>; 326 clock-frequency = <0>;
327 interrupts = <9 0x8>; 327 interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
331 serial1: serial@4600 { 331 serial1: serial@4600 {
332 cell-index = <1>; 332 cell-index = <1>;
333 device_type = "serial"; 333 device_type = "serial";
334 compatible = "ns16550"; 334 compatible = "fsl,ns16550", "ns16550";
335 reg = <0x4600 0x100>; 335 reg = <0x4600 0x100>;
336 clock-frequency = <0>; 336 clock-frequency = <0>;
337 interrupts = <10 0x8>; 337 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 645ec51cc6e..5387092fdfb 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -313,7 +313,7 @@
313 serial0: serial@4500 { 313 serial0: serial@4500 {
314 cell-index = <0>; 314 cell-index = <0>;
315 device_type = "serial"; 315 device_type = "serial";
316 compatible = "ns16550"; 316 compatible = "fsl,ns16550", "ns16550";
317 reg = <0x4500 0x100>; 317 reg = <0x4500 0x100>;
318 clock-frequency = <0>; 318 clock-frequency = <0>;
319 interrupts = <9 0x8>; 319 interrupts = <9 0x8>;
@@ -323,7 +323,7 @@
323 serial1: serial@4600 { 323 serial1: serial@4600 {
324 cell-index = <1>; 324 cell-index = <1>;
325 device_type = "serial"; 325 device_type = "serial";
326 compatible = "ns16550"; 326 compatible = "fsl,ns16550", "ns16550";
327 reg = <0x4600 0x100>; 327 reg = <0x4600 0x100>;
328 clock-frequency = <0>; 328 clock-frequency = <0>;
329 interrupts = <10 0x8>; 329 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 15560c619b0..46224c2430f 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -319,7 +319,7 @@
319 serial0: serial@4500 { 319 serial0: serial@4500 {
320 cell-index = <0>; 320 cell-index = <0>;
321 device_type = "serial"; 321 device_type = "serial";
322 compatible = "ns16550"; 322 compatible = "fsl,ns16550", "ns16550";
323 reg = <0x4500 0x100>; 323 reg = <0x4500 0x100>;
324 clock-frequency = <0>; 324 clock-frequency = <0>;
325 interrupts = <9 0x8>; 325 interrupts = <9 0x8>;
@@ -329,7 +329,7 @@
329 serial1: serial@4600 { 329 serial1: serial@4600 {
330 cell-index = <1>; 330 cell-index = <1>;
331 device_type = "serial"; 331 device_type = "serial";
332 compatible = "ns16550"; 332 compatible = "fsl,ns16550", "ns16550";
333 reg = <0x4600 0x100>; 333 reg = <0x4600 0x100>;
334 clock-frequency = <0>; 334 clock-frequency = <0>;
335 interrupts = <10 0x8>; 335 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index a75c10eed26..c15881574fd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,403 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@ffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 spi@7000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,mpc8536-espi";
115 reg = <0x7000 0x1000>;
116 interrupts = <59 0x2>;
117 interrupt-parent = <&mpic>;
118 fsl,espi-num-chipselects = <4>;
119
120 flash@0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "spansion,s25sl12801";
124 reg = <0>;
125 spi-max-frequency = <40000000>;
126 partition@u-boot {
127 label = "u-boot";
128 reg = <0x00000000 0x00100000>;
129 read-only;
130 };
131 partition@kernel {
132 label = "kernel";
133 reg = <0x00100000 0x00500000>;
134 read-only;
135 };
136 partition@dtb {
137 label = "dtb";
138 reg = <0x00600000 0x00100000>;
139 read-only;
140 };
141 partition@fs {
142 label = "file system";
143 reg = <0x00700000 0x00900000>;
144 };
145 };
146 flash@1 {
147 compatible = "spansion,s25sl12801";
148 reg = <1>;
149 spi-max-frequency = <40000000>;
150 };
151 flash@2 {
152 compatible = "spansion,s25sl12801";
153 reg = <2>;
154 spi-max-frequency = <40000000>;
155 };
156 flash@3 {
157 compatible = "spansion,s25sl12801";
158 reg = <3>;
159 spi-max-frequency = <40000000>;
160 };
161 };
162
163 dma@21300 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
167 reg = <0x21300 4>;
168 ranges = <0 0x21100 0x200>;
169 cell-index = <0>;
170 dma-channel@0 {
171 compatible = "fsl,mpc8536-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x0 0x80>;
174 cell-index = <0>;
175 interrupt-parent = <&mpic>;
176 interrupts = <20 2>;
177 };
178 dma-channel@80 {
179 compatible = "fsl,mpc8536-dma-channel",
180 "fsl,eloplus-dma-channel";
181 reg = <0x80 0x80>;
182 cell-index = <1>;
183 interrupt-parent = <&mpic>;
184 interrupts = <21 2>;
185 };
186 dma-channel@100 {
187 compatible = "fsl,mpc8536-dma-channel",
188 "fsl,eloplus-dma-channel";
189 reg = <0x100 0x80>;
190 cell-index = <2>;
191 interrupt-parent = <&mpic>;
192 interrupts = <22 2>;
193 };
194 dma-channel@180 {
195 compatible = "fsl,mpc8536-dma-channel",
196 "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 phy_type = "ulpi";
212 };
213
214 usb@23000 {
215 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
216 reg = <0x23000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <46 0x2>;
221 phy_type = "ulpi";
222 };
223
224 enet0: ethernet@24000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@0 {
247 interrupt-parent = <&mpic>;
248 interrupts = <10 0x1>;
249 reg = <0>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <10 0x1>;
255 reg = <1>;
256 device_type = "ethernet-phy";
257 };
258 tbi0: tbi-phy@11 {
259 reg = <0x11>;
260 device_type = "tbi-phy";
261 };
262 };
263 };
264
265 enet1: ethernet@26000 {
266 #address-cells = <1>;
267 #size-cells = <1>;
268 cell-index = <1>;
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x26000 0x1000>;
273 ranges = <0x0 0x26000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <31 2 32 2 33 2>;
276 interrupt-parent = <&mpic>;
277 tbi-handle = <&tbi1>;
278 phy-handle = <&phy0>;
279 phy-connection-type = "rgmii-id";
280
281 mdio@520 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "fsl,gianfar-tbi";
285 reg = <0x520 0x20>;
286
287 tbi1: tbi-phy@11 {
288 reg = <0x11>;
289 device_type = "tbi-phy";
290 };
291 };
292 };
293
294 usb@2b000 {
295 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
296 reg = <0x2b000 0x1000>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 interrupt-parent = <&mpic>;
300 interrupts = <60 0x2>;
301 dr_mode = "peripheral";
302 phy_type = "ulpi";
303 };
304
305 sdhci@2e000 {
306 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
307 reg = <0x2e000 0x1000>;
308 interrupts = <72 0x2>;
309 interrupt-parent = <&mpic>;
310 clock-frequency = <250000000>;
311 };
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 0x2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 0x2>;
330 interrupt-parent = <&mpic>;
331 };
332
333 crypto@30000 {
334 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335 "fsl,sec2.1", "fsl,sec2.0";
336 reg = <0x30000 0x10000>;
337 interrupts = <45 2 58 2>;
338 interrupt-parent = <&mpic>;
339 fsl,num-channels = <4>;
340 fsl,channel-fifo-len = <24>;
341 fsl,exec-units-mask = <0x9fe>;
342 fsl,descriptor-types-mask = <0x3ab0ebf>;
343 };
344
345 sata@18000 {
346 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
347 reg = <0x18000 0x1000>;
348 cell-index = <1>;
349 interrupts = <74 0x2>;
350 interrupt-parent = <&mpic>;
351 };
352
353 sata@19000 {
354 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
355 reg = <0x19000 0x1000>;
356 cell-index = <2>;
357 interrupts = <41 0x2>;
358 interrupt-parent = <&mpic>;
359 };
360
361 global-utilities@e0000 { //global utilities block
362 compatible = "fsl,mpc8548-guts";
363 reg = <0xe0000 0x1000>;
364 fsl,has-rstcr;
365 };
366
367 mpic: pic@40000 {
368 clock-frequency = <0>;
369 interrupt-controller;
370 #address-cells = <0>;
371 #interrupt-cells = <2>;
372 reg = <0x40000 0x40000>;
373 compatible = "chrp,open-pic";
374 device_type = "open-pic";
375 big-endian;
376 };
377 38
378 msi@41600 { 39 board_soc: soc: soc@ffe00000 {
379 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0 0xffe00000 0x100000>;
380 reg = <0x41600 0x80>;
381 msi-available-ranges = <0 0x100>;
382 interrupts = <
383 0xe0 0
384 0xe1 0
385 0xe2 0
386 0xe3 0
387 0xe4 0
388 0xe5 0
389 0xe6 0
390 0xe7 0>;
391 interrupt-parent = <&mpic>;
392 };
393 }; 41 };
394 42
395 pci0: pci@ffe08000 { 43 pci0: pci@ffe08000 {
396 compatible = "fsl,mpc8540-pci"; 44 reg = <0 0xffe08000 0 0x1000>;
397 device_type = "pci"; 45 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
46 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
398 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 49 interrupt-map = <
400 50
401 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
402 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
403 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
404 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
405 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
406
407 interrupt-parent = <&mpic>;
408 interrupts = <24 0x2>;
409 bus-range = <0 0xff>;
410 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
411 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
412 clock-frequency = <66666666>;
413 #interrupt-cells = <1>;
414 #size-cells = <2>;
415 #address-cells = <3>;
416 reg = <0 0xffe08000 0 0x1000>;
417 }; 56 };
418 57
419 pci1: pcie@ffe09000 { 58 pci1: pcie@ffe09000 {
420 compatible = "fsl,mpc8548-pcie";
421 device_type = "pci";
422 #interrupt-cells = <1>;
423 #size-cells = <2>;
424 #address-cells = <3>;
425 reg = <0 0xffe09000 0 0x1000>; 59 reg = <0 0xffe09000 0 0x1000>;
426 bus-range = <0 0xff>;
427 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000 60 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
428 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
429 clock-frequency = <33333333>;
430 interrupt-parent = <&mpic>;
431 interrupts = <25 0x2>;
432 interrupt-map-mask = <0xf800 0 0 7>;
433 interrupt-map = <
434 /* IDSEL 0x0 */
435 0000 0 0 1 &mpic 4 1
436 0000 0 0 2 &mpic 5 1
437 0000 0 0 3 &mpic 6 1
438 0000 0 0 4 &mpic 7 1
439 >;
440 pcie@0 { 62 pcie@0 {
441 reg = <0 0 0 0 0>;
442 #size-cells = <2>;
443 #address-cells = <3>;
444 device_type = "pci";
445 ranges = <0x02000000 0 0x98000000 63 ranges = <0x02000000 0 0x98000000
446 0x02000000 0 0x98000000 64 0x02000000 0 0x98000000
447 0 0x08000000 65 0 0x08000000
@@ -453,31 +71,10 @@
453 }; 71 };
454 72
455 pci2: pcie@ffe0a000 { 73 pci2: pcie@ffe0a000 {
456 compatible = "fsl,mpc8548-pcie";
457 device_type = "pci";
458 #interrupt-cells = <1>;
459 #size-cells = <2>;
460 #address-cells = <3>;
461 reg = <0 0xffe0a000 0 0x1000>; 74 reg = <0 0xffe0a000 0 0x1000>;
462 bus-range = <0 0xff>;
463 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000 75 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
464 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
465 clock-frequency = <33333333>;
466 interrupt-parent = <&mpic>;
467 interrupts = <26 0x2>;
468 interrupt-map-mask = <0xf800 0 0 7>;
469 interrupt-map = <
470 /* IDSEL 0x0 */
471 0000 0 0 1 &mpic 0 1
472 0000 0 0 2 &mpic 1 1
473 0000 0 0 3 &mpic 2 1
474 0000 0 0 4 &mpic 3 1
475 >;
476 pcie@0 { 77 pcie@0 {
477 reg = <0 0 0 0 0>;
478 #size-cells = <2>;
479 #address-cells = <3>;
480 device_type = "pci";
481 ranges = <0x02000000 0 0x90000000 78 ranges = <0x02000000 0 0x90000000
482 0x02000000 0 0x90000000 79 0x02000000 0 0x90000000
483 0 0x08000000 80 0 0x08000000
@@ -489,32 +86,10 @@
489 }; 86 };
490 87
491 pci3: pcie@ffe0b000 { 88 pci3: pcie@ffe0b000 {
492 compatible = "fsl,mpc8548-pcie";
493 device_type = "pci";
494 #interrupt-cells = <1>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 reg = <0 0xffe0b000 0 0x1000>; 89 reg = <0 0xffe0b000 0 0x1000>;
498 bus-range = <0 0xff>;
499 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 90 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
500 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
501 clock-frequency = <33333333>;
502 interrupt-parent = <&mpic>;
503 interrupts = <27 0x2>;
504 interrupt-map-mask = <0xf800 0 0 7>;
505 interrupt-map = <
506 /* IDSEL 0x0 */
507 0000 0 0 1 &mpic 8 1
508 0000 0 0 2 &mpic 9 1
509 0000 0 0 3 &mpic 10 1
510 0000 0 0 4 &mpic 11 1
511 >;
512
513 pcie@0 { 92 pcie@0 {
514 reg = <0 0 0 0 0>;
515 #size-cells = <2>;
516 #address-cells = <3>;
517 device_type = "pci";
518 ranges = <0x02000000 0 0xa0000000 93 ranges = <0x02000000 0 0xa0000000
519 0x02000000 0 0xa0000000 94 0x02000000 0 0xa0000000
520 0 0x20000000 95 0 0x20000000
@@ -525,3 +100,6 @@
525 }; 100 };
526 }; 101 };
527}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
new file mode 100644
index 00000000000..1462e4cf49d
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -0,0 +1,141 @@
1/*
2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_soc {
36 i2c@3100 {
37 rtc@68 {
38 compatible = "dallas,ds3232";
39 reg = <0x68>;
40 interrupts = <0 0x1 0 0>;
41 };
42 };
43
44 spi@7000 {
45 flash@0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "spansion,s25sl12801";
49 reg = <0>;
50 spi-max-frequency = <40000000>;
51 partition@u-boot {
52 label = "u-boot";
53 reg = <0x00000000 0x00100000>;
54 read-only;
55 };
56 partition@kernel {
57 label = "kernel";
58 reg = <0x00100000 0x00500000>;
59 read-only;
60 };
61 partition@dtb {
62 label = "dtb";
63 reg = <0x00600000 0x00100000>;
64 read-only;
65 };
66 partition@fs {
67 label = "file system";
68 reg = <0x00700000 0x00900000>;
69 };
70 };
71 flash@1 {
72 compatible = "spansion,s25sl12801";
73 reg = <1>;
74 spi-max-frequency = <40000000>;
75 };
76 flash@2 {
77 compatible = "spansion,s25sl12801";
78 reg = <2>;
79 spi-max-frequency = <40000000>;
80 };
81 flash@3 {
82 compatible = "spansion,s25sl12801";
83 reg = <3>;
84 spi-max-frequency = <40000000>;
85 };
86 };
87
88 usb@22000 {
89 phy_type = "ulpi";
90 };
91
92 usb@23000 {
93 phy_type = "ulpi";
94 };
95
96 enet0: ethernet@24000 {
97 tbi-handle = <&tbi0>;
98 phy-handle = <&phy1>;
99 phy-connection-type = "rgmii-id";
100 };
101
102 mdio@24520 {
103 phy0: ethernet-phy@0 {
104 interrupts = <10 0x1 0 0>;
105 reg = <0>;
106 device_type = "ethernet-phy";
107 };
108 phy1: ethernet-phy@1 {
109 interrupts = <10 0x1 0 0>;
110 reg = <1>;
111 device_type = "ethernet-phy";
112 };
113 tbi0: tbi-phy@11 {
114 reg = <0x11>;
115 device_type = "tbi-phy";
116 };
117 };
118
119 enet2: ethernet@26000 {
120 tbi-handle = <&tbi1>;
121 phy-handle = <&phy0>;
122 phy-connection-type = "rgmii-id";
123 };
124
125 mdio@26520 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "fsl,gianfar-tbi";
129 reg = <0x26520 0x20>;
130
131 tbi1: tbi-phy@11 {
132 reg = <0x11>;
133 device_type = "tbi-phy";
134 };
135 };
136
137 usb@2b000 {
138 dr_mode = "peripheral";
139 phy_type = "ulpi";
140 };
141};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index d95b26021e6..8f4b929b1d1 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8536 DS Device Tree Source 2 * MPC8536DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc. 4 * Copyright 2008-2009 Freescale Semiconductor, Inc.
5 * 5 *
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,351 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@fffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
115 reg = <0x21300 4>;
116 ranges = <0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8536-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8536-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8536-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8536-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
151
152 usb@22000 {
153 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
154 reg = <0x22000 0x1000>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupt-parent = <&mpic>;
158 interrupts = <28 0x2>;
159 phy_type = "ulpi";
160 };
161
162 usb@23000 {
163 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
164 reg = <0x23000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupt-parent = <&mpic>;
168 interrupts = <46 0x2>;
169 phy_type = "ulpi";
170 };
171
172 enet0: ethernet@24000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 cell-index = <0>;
176 device_type = "network";
177 model = "eTSEC";
178 compatible = "gianfar";
179 reg = <0x24000 0x1000>;
180 ranges = <0x0 0x24000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <29 2 30 2 34 2>;
183 interrupt-parent = <&mpic>;
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy1>;
186 phy-connection-type = "rgmii-id";
187
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-mdio";
192 reg = <0x520 0x20>;
193
194 phy0: ethernet-phy@0 {
195 interrupt-parent = <&mpic>;
196 interrupts = <10 0x1>;
197 reg = <0>;
198 device_type = "ethernet-phy";
199 };
200 phy1: ethernet-phy@1 {
201 interrupt-parent = <&mpic>;
202 interrupts = <10 0x1>;
203 reg = <1>;
204 device_type = "ethernet-phy";
205 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
212
213 enet1: ethernet@26000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "eTSEC";
219 compatible = "gianfar";
220 reg = <0x26000 0x1000>;
221 ranges = <0x0 0x26000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <31 2 32 2 33 2>;
224 interrupt-parent = <&mpic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
234
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
241
242 usb@2b000 {
243 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
244 reg = <0x2b000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupt-parent = <&mpic>;
248 interrupts = <60 0x2>;
249 dr_mode = "peripheral";
250 phy_type = "ulpi";
251 };
252
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
260
261 serial0: serial@4500 {
262 cell-index = <0>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4500 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 0x2>;
268 interrupt-parent = <&mpic>;
269 };
270
271 serial1: serial@4600 {
272 cell-index = <1>;
273 device_type = "serial";
274 compatible = "ns16550";
275 reg = <0x4600 0x100>;
276 clock-frequency = <0>;
277 interrupts = <42 0x2>;
278 interrupt-parent = <&mpic>;
279 };
280
281 crypto@30000 {
282 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
283 "fsl,sec2.1", "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <45 2 58 2>;
286 interrupt-parent = <&mpic>;
287 fsl,num-channels = <4>;
288 fsl,channel-fifo-len = <24>;
289 fsl,exec-units-mask = <0x9fe>;
290 fsl,descriptor-types-mask = <0x3ab0ebf>;
291 };
292
293 sata@18000 {
294 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
295 reg = <0x18000 0x1000>;
296 cell-index = <1>;
297 interrupts = <74 0x2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 sata@19000 {
302 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
303 reg = <0x19000 0x1000>;
304 cell-index = <2>;
305 interrupts = <41 0x2>;
306 interrupt-parent = <&mpic>;
307 };
308
309 global-utilities@e0000 { //global utilities block
310 compatible = "fsl,mpc8548-guts";
311 reg = <0xe0000 0x1000>;
312 fsl,has-rstcr;
313 };
314
315 mpic: pic@40000 {
316 clock-frequency = <0>;
317 interrupt-controller;
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 reg = <0x40000 0x40000>;
321 compatible = "chrp,open-pic";
322 device_type = "open-pic";
323 big-endian;
324 };
325 38
326 msi@41600 { 39 board_soc: soc: soc@fffe00000 {
327 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0xf 0xffe00000 0x100000>;
328 reg = <0x41600 0x80>;
329 msi-available-ranges = <0 0x100>;
330 interrupts = <
331 0xe0 0
332 0xe1 0
333 0xe2 0
334 0xe3 0
335 0xe4 0
336 0xe5 0
337 0xe6 0
338 0xe7 0>;
339 interrupt-parent = <&mpic>;
340 };
341 }; 41 };
342 42
343 pci0: pci@fffe08000 { 43 pci0: pci@ffe08000 {
344 compatible = "fsl,mpc8540-pci"; 44 reg = <0xf 0xffe08000 0 0x1000>;
345 device_type = "pci"; 45 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
46 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
346 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-map = < 49 interrupt-map = <
348 50
349 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
350 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
351 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
352 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
353 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <24 0x2>;
357 bus-range = <0 0xff>;
358 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
359 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
360 clock-frequency = <66666666>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <0xf 0xffe08000 0 0x1000>;
365 }; 56 };
366 57
367 pci1: pcie@fffe09000 { 58 pci1: pcie@ffe09000 {
368 compatible = "fsl,mpc8548-pcie";
369 device_type = "pci";
370 #interrupt-cells = <1>;
371 #size-cells = <2>;
372 #address-cells = <3>;
373 reg = <0xf 0xffe09000 0 0x1000>; 59 reg = <0xf 0xffe09000 0 0x1000>;
374 bus-range = <0 0xff>;
375 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000 60 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
376 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
377 clock-frequency = <33333333>;
378 interrupt-parent = <&mpic>;
379 interrupts = <25 0x2>;
380 interrupt-map-mask = <0xf800 0 0 7>;
381 interrupt-map = <
382 /* IDSEL 0x0 */
383 0000 0 0 1 &mpic 4 1
384 0000 0 0 2 &mpic 5 1
385 0000 0 0 3 &mpic 6 1
386 0000 0 0 4 &mpic 7 1
387 >;
388 pcie@0 { 62 pcie@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 device_type = "pci";
393 ranges = <0x02000000 0 0xf8000000 63 ranges = <0x02000000 0 0xf8000000
394 0x02000000 0 0xf8000000 64 0x02000000 0 0xf8000000
395 0 0x08000000 65 0 0x08000000
@@ -401,31 +71,10 @@
401 }; 71 };
402 72
403 pci2: pcie@fffe0a000 { 73 pci2: pcie@fffe0a000 {
404 compatible = "fsl,mpc8548-pcie";
405 device_type = "pci";
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 reg = <0xf 0xffe0a000 0 0x1000>; 74 reg = <0xf 0xffe0a000 0 0x1000>;
410 bus-range = <0 0xff>;
411 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000 75 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
412 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
413 clock-frequency = <33333333>;
414 interrupt-parent = <&mpic>;
415 interrupts = <26 0x2>;
416 interrupt-map-mask = <0xf800 0 0 7>;
417 interrupt-map = <
418 /* IDSEL 0x0 */
419 0000 0 0 1 &mpic 0 1
420 0000 0 0 2 &mpic 1 1
421 0000 0 0 3 &mpic 2 1
422 0000 0 0 4 &mpic 3 1
423 >;
424 pcie@0 { 77 pcie@0 {
425 reg = <0 0 0 0 0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x02000000 0 0xf8000000 78 ranges = <0x02000000 0 0xf8000000
430 0x02000000 0 0xf8000000 79 0x02000000 0 0xf8000000
431 0 0x08000000 80 0 0x08000000
@@ -437,32 +86,10 @@
437 }; 86 };
438 87
439 pci3: pcie@fffe0b000 { 88 pci3: pcie@fffe0b000 {
440 compatible = "fsl,mpc8548-pcie";
441 device_type = "pci";
442 #interrupt-cells = <1>;
443 #size-cells = <2>;
444 #address-cells = <3>;
445 reg = <0xf 0xffe0b000 0 0x1000>; 89 reg = <0xf 0xffe0b000 0 0x1000>;
446 bus-range = <0 0xff>;
447 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000 90 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
448 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
449 clock-frequency = <33333333>;
450 interrupt-parent = <&mpic>;
451 interrupts = <27 0x2>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <
454 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 8 1
456 0000 0 0 2 &mpic 9 1
457 0000 0 0 3 &mpic 10 1
458 0000 0 0 4 &mpic 11 1
459 >;
460
461 pcie@0 { 92 pcie@0 {
462 reg = <0 0 0 0 0>;
463 #size-cells = <2>;
464 #address-cells = <3>;
465 device_type = "pci";
466 ranges = <0x02000000 0 0xe0000000 93 ranges = <0x02000000 0 0xe0000000
467 0x02000000 0 0xe0000000 94 0x02000000 0 0xe0000000
468 0 0x20000000 95 0 0x20000000
@@ -473,3 +100,6 @@
473 }; 100 };
474 }; 101 };
475}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 8d1bf0fd926..f99fb110c97 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -243,7 +243,7 @@
243 serial0: serial@4500 { 243 serial0: serial@4500 {
244 cell-index = <0>; 244 cell-index = <0>;
245 device_type = "serial"; 245 device_type = "serial";
246 compatible = "ns16550"; 246 compatible = "fsl,ns16550", "ns16550";
247 reg = <0x4500 0x100>; // reg base, size 247 reg = <0x4500 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot? 248 clock-frequency = <0>; // should we fill in in uboot?
249 interrupts = <42 2>; 249 interrupts = <42 2>;
@@ -253,7 +253,7 @@
253 serial1: serial@4600 { 253 serial1: serial@4600 {
254 cell-index = <1>; 254 cell-index = <1>;
255 device_type = "serial"; 255 device_type = "serial";
256 compatible = "ns16550"; 256 compatible = "fsl,ns16550", "ns16550";
257 reg = <0x4600 0x100>; // reg base, size 257 reg = <0x4600 0x100>; // reg base, size
258 clock-frequency = <0>; // should we fill in in uboot? 258 clock-frequency = <0>; // should we fill in in uboot?
259 interrupts = <42 2>; 259 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 87ff96549fa..0f5e9391279 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -209,7 +209,7 @@
209 serial0: serial@4500 { 209 serial0: serial@4500 {
210 cell-index = <0>; 210 cell-index = <0>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4500 0x100>; // reg base, size 213 reg = <0x4500 0x100>; // reg base, size
214 clock-frequency = <0>; // should we fill in in uboot? 214 clock-frequency = <0>; // should we fill in in uboot?
215 interrupts = <42 2>; 215 interrupts = <42 2>;
@@ -219,7 +219,7 @@
219 serial1: serial@4600 { 219 serial1: serial@4600 {
220 cell-index = <1>; 220 cell-index = <1>;
221 device_type = "serial"; 221 device_type = "serial";
222 compatible = "ns16550"; 222 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4600 0x100>; // reg base, size 223 reg = <0x4600 0x100>; // reg base, size
224 clock-frequency = <0>; // should we fill in in uboot? 224 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 225 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index d793968743c..e934987e882 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -9,339 +9,52 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8544si-pre.dtsi"
13
13/ { 14/ {
14 model = "MPC8544DS"; 15 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS"; 16 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8544@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47 17
48 memory { 18 memory {
49 device_type = "memory"; 19 device_type = "memory";
50 reg = <0x0 0x0>; // Filled by U-Boot 20 reg = <0 0 0 0>; // Filled by U-Boot
51 }; 21 };
52 22
53 soc8544@e0000000 { 23 lbc: localbus@e0005000 {
54 #address-cells = <1>; 24 reg = <0 0xe0005000 0 0x1000>;
55 #size-cells = <1>; 25 };
56 device_type = "soc";
57 compatible = "simple-bus";
58
59 ranges = <0x0 0xe0000000 0x100000>;
60 bus-frequency = <0>; // Filled out by uboot.
61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <10>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>;
80 };
81
82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
87 interrupt-parent = <&mpic>;
88 interrupts = <16 2>;
89 };
90
91 i2c@3000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <0>;
95 compatible = "fsl-i2c";
96 reg = <0x3000 0x100>;
97 interrupts = <43 2>;
98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
101
102 i2c@3100 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 cell-index = <1>;
106 compatible = "fsl-i2c";
107 reg = <0x3100 0x100>;
108 interrupts = <43 2>;
109 interrupt-parent = <&mpic>;
110 dfsrr;
111 };
112
113 dma@21300 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
117 reg = <0x21300 0x4>;
118 ranges = <0x0 0x21100 0x200>;
119 cell-index = <0>;
120 dma-channel@0 {
121 compatible = "fsl,mpc8544-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x0 0x80>;
124 cell-index = <0>;
125 interrupt-parent = <&mpic>;
126 interrupts = <20 2>;
127 };
128 dma-channel@80 {
129 compatible = "fsl,mpc8544-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x80 0x80>;
132 cell-index = <1>;
133 interrupt-parent = <&mpic>;
134 interrupts = <21 2>;
135 };
136 dma-channel@100 {
137 compatible = "fsl,mpc8544-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x100 0x80>;
140 cell-index = <2>;
141 interrupt-parent = <&mpic>;
142 interrupts = <22 2>;
143 };
144 dma-channel@180 {
145 compatible = "fsl,mpc8544-dma-channel",
146 "fsl,eloplus-dma-channel";
147 reg = <0x180 0x80>;
148 cell-index = <3>;
149 interrupt-parent = <&mpic>;
150 interrupts = <23 2>;
151 };
152 };
153
154 enet0: ethernet@24000 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 cell-index = <0>;
158 device_type = "network";
159 model = "TSEC";
160 compatible = "gianfar";
161 reg = <0x24000 0x1000>;
162 ranges = <0x0 0x24000 0x1000>;
163 local-mac-address = [ 00 00 00 00 00 00 ];
164 interrupts = <29 2 30 2 34 2>;
165 interrupt-parent = <&mpic>;
166 phy-handle = <&phy0>;
167 tbi-handle = <&tbi0>;
168 phy-connection-type = "rgmii-id";
169
170 mdio@520 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,gianfar-mdio";
174 reg = <0x520 0x20>;
175
176 phy0: ethernet-phy@0 {
177 interrupt-parent = <&mpic>;
178 interrupts = <10 1>;
179 reg = <0x0>;
180 device_type = "ethernet-phy";
181 };
182 phy1: ethernet-phy@1 {
183 interrupt-parent = <&mpic>;
184 interrupts = <10 1>;
185 reg = <0x1>;
186 device_type = "ethernet-phy";
187 };
188
189 tbi0: tbi-phy@11 {
190 reg = <0x11>;
191 device_type = "tbi-phy";
192 };
193 };
194 };
195
196 enet1: ethernet@26000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cell-index = <1>;
200 device_type = "network";
201 model = "TSEC";
202 compatible = "gianfar";
203 reg = <0x26000 0x1000>;
204 ranges = <0x0 0x26000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <31 2 32 2 33 2>;
207 interrupt-parent = <&mpic>;
208 phy-handle = <&phy1>;
209 tbi-handle = <&tbi1>;
210 phy-connection-type = "rgmii-id";
211
212 mdio@520 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,gianfar-tbi";
216 reg = <0x520 0x20>;
217
218 tbi1: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 };
223 };
224
225 serial0: serial@4500 {
226 cell-index = <0>;
227 device_type = "serial";
228 compatible = "ns16550";
229 reg = <0x4500 0x100>;
230 clock-frequency = <0>;
231 interrupts = <42 2>;
232 interrupt-parent = <&mpic>;
233 };
234
235 serial1: serial@4600 {
236 cell-index = <1>;
237 device_type = "serial";
238 compatible = "ns16550";
239 reg = <0x4600 0x100>;
240 clock-frequency = <0>;
241 interrupts = <42 2>;
242 interrupt-parent = <&mpic>;
243 };
244
245 global-utilities@e0000 { //global utilities block
246 compatible = "fsl,mpc8548-guts";
247 reg = <0xe0000 0x1000>;
248 fsl,has-rstcr;
249 };
250
251 crypto@30000 {
252 compatible = "fsl,sec2.1", "fsl,sec2.0";
253 reg = <0x30000 0x10000>;
254 interrupts = <45 2>;
255 interrupt-parent = <&mpic>;
256 fsl,num-channels = <4>;
257 fsl,channel-fifo-len = <24>;
258 fsl,exec-units-mask = <0xfe>;
259 fsl,descriptor-types-mask = <0x12b0ebf>;
260 };
261
262 mpic: pic@40000 {
263 interrupt-controller;
264 #address-cells = <0>;
265 #interrupt-cells = <2>;
266 reg = <0x40000 0x40000>;
267 compatible = "chrp,open-pic";
268 device_type = "open-pic";
269 };
270 26
271 msi@41600 { 27 board_soc: soc: soc8544@e0000000 {
272 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi"; 28 ranges = <0x0 0x0 0xe0000000 0x100000>;
273 reg = <0x41600 0x80>;
274 msi-available-ranges = <0 0x100>;
275 interrupts = <
276 0xe0 0
277 0xe1 0
278 0xe2 0
279 0xe3 0
280 0xe4 0
281 0xe5 0
282 0xe6 0
283 0xe7 0>;
284 interrupt-parent = <&mpic>;
285 };
286 }; 29 };
287 30
288 pci0: pci@e0008000 { 31 pci0: pci@e0008000 {
289 compatible = "fsl,mpc8540-pci"; 32 reg = <0 0xe0008000 0 0x1000>;
290 device_type = "pci"; 33 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
34 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
35 clock-frequency = <66666666>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 36 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = < 37 interrupt-map = <
293 38
294 /* IDSEL 0x11 J17 Slot 1 */ 39 /* IDSEL 0x11 J17 Slot 1 */
295 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 40 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
296 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 41 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
297 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 42 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
298 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 43 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
299 44
300 /* IDSEL 0x12 J16 Slot 2 */ 45 /* IDSEL 0x12 J16 Slot 2 */
301 46
302 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 47 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
303 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 48 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
304 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 49 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
305 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>; 50 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
306
307 interrupt-parent = <&mpic>;
308 interrupts = <24 2>;
309 bus-range = <0 255>;
310 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
311 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
312 clock-frequency = <66666666>;
313 #interrupt-cells = <1>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 reg = <0xe0008000 0x1000>;
317 }; 51 };
318 52
319 pci1: pcie@e0009000 { 53 pci1: pcie@e0009000 {
320 compatible = "fsl,mpc8548-pcie"; 54 reg = <0x0 0xe0009000 0x0 0x1000>;
321 device_type = "pci"; 55 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
322 #interrupt-cells = <1>; 56 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 reg = <0xe0009000 0x1000>;
326 bus-range = <0 255>;
327 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
328 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
329 clock-frequency = <33333333>;
330 interrupt-parent = <&mpic>;
331 interrupts = <25 2>;
332 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
333 interrupt-map = <
334 /* IDSEL 0x0 */
335 0000 0x0 0x0 0x1 &mpic 0x4 0x1
336 0000 0x0 0x0 0x2 &mpic 0x5 0x1
337 0000 0x0 0x0 0x3 &mpic 0x6 0x1
338 0000 0x0 0x0 0x4 &mpic 0x7 0x1
339 >;
340 pcie@0 { 57 pcie@0 {
341 reg = <0x0 0x0 0x0 0x0 0x0>;
342 #size-cells = <2>;
343 #address-cells = <3>;
344 device_type = "pci";
345 ranges = <0x2000000 0x0 0x80000000 58 ranges = <0x2000000 0x0 0x80000000
346 0x2000000 0x0 0x80000000 59 0x2000000 0x0 0x80000000
347 0x0 0x20000000 60 0x0 0x20000000
@@ -353,31 +66,10 @@
353 }; 66 };
354 67
355 pci2: pcie@e000a000 { 68 pci2: pcie@e000a000 {
356 compatible = "fsl,mpc8548-pcie"; 69 reg = <0x0 0xe000a000 0x0 0x1000>;
357 device_type = "pci"; 70 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
358 #interrupt-cells = <1>; 71 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
359 #size-cells = <2>;
360 #address-cells = <3>;
361 reg = <0xe000a000 0x1000>;
362 bus-range = <0 255>;
363 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
364 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <26 2>;
368 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
369 interrupt-map = <
370 /* IDSEL 0x0 */
371 0000 0x0 0x0 0x1 &mpic 0x0 0x1
372 0000 0x0 0x0 0x2 &mpic 0x1 0x1
373 0000 0x0 0x0 0x3 &mpic 0x2 0x1
374 0000 0x0 0x0 0x4 &mpic 0x3 0x1
375 >;
376 pcie@0 { 72 pcie@0 {
377 reg = <0x0 0x0 0x0 0x0 0x0>;
378 #size-cells = <2>;
379 #address-cells = <3>;
380 device_type = "pci";
381 ranges = <0x2000000 0x0 0xa0000000 73 ranges = <0x2000000 0x0 0xa0000000
382 0x2000000 0x0 0xa0000000 74 0x2000000 0x0 0xa0000000
383 0x0 0x10000000 75 0x0 0x10000000
@@ -388,44 +80,11 @@
388 }; 80 };
389 }; 81 };
390 82
391 pci3: pcie@e000b000 { 83 board_pci3: pci3: pcie@e000b000 {
392 compatible = "fsl,mpc8548-pcie"; 84 reg = <0x0 0xe000b000 0x0 0x1000>;
393 device_type = "pci"; 85 ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
394 #interrupt-cells = <1>; 86 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 reg = <0xe000b000 0x1000>;
398 bus-range = <0 255>;
399 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
400 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
401 clock-frequency = <33333333>;
402 interrupt-parent = <&mpic>;
403 interrupts = <27 2>;
404 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
405 interrupt-map = <
406 // IDSEL 0x1c USB
407 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
408 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
409 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
410 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
411
412 // IDSEL 0x1d Audio
413 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
414
415 // IDSEL 0x1e Legacy
416 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
417 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
418
419 // IDSEL 0x1f IDE/SATA
420 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
421 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
422 >;
423
424 pcie@0 { 87 pcie@0 {
425 reg = <0x0 0x0 0x0 0x0 0x0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x2000000 0x0 0xb0000000 88 ranges = <0x2000000 0x0 0xb0000000
430 0x2000000 0x0 0xb0000000 89 0x2000000 0x0 0xb0000000
431 0x0 0x100000 90 0x0 0x100000
@@ -433,70 +92,14 @@
433 0x1000000 0x0 0x0 92 0x1000000 0x0 0x0
434 0x1000000 0x0 0x0 93 0x1000000 0x0 0x0
435 0x0 0x100000>; 94 0x0 0x100000>;
436
437 uli1575@0 {
438 reg = <0x0 0x0 0x0 0x0 0x0>;
439 #size-cells = <2>;
440 #address-cells = <3>;
441 ranges = <0x2000000 0x0 0xb0000000
442 0x2000000 0x0 0xb0000000
443 0x0 0x100000
444
445 0x1000000 0x0 0x0
446 0x1000000 0x0 0x0
447 0x0 0x100000>;
448 isa@1e {
449 device_type = "isa";
450 #interrupt-cells = <2>;
451 #size-cells = <1>;
452 #address-cells = <2>;
453 reg = <0xf000 0x0 0x0 0x0 0x0>;
454 ranges = <0x1 0x0
455 0x1000000 0x0 0x0
456 0x1000>;
457 interrupt-parent = <&i8259>;
458
459 i8259: interrupt-controller@20 {
460 reg = <0x1 0x20 0x2
461 0x1 0xa0 0x2
462 0x1 0x4d0 0x2>;
463 interrupt-controller;
464 device_type = "interrupt-controller";
465 #address-cells = <0>;
466 #interrupt-cells = <2>;
467 compatible = "chrp,iic";
468 interrupts = <9 2>;
469 interrupt-parent = <&mpic>;
470 };
471
472 i8042@60 {
473 #size-cells = <0>;
474 #address-cells = <1>;
475 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
476 interrupts = <1 3 12 3>;
477 interrupt-parent = <&i8259>;
478
479 keyboard@0 {
480 reg = <0x0>;
481 compatible = "pnpPNP,303";
482 };
483
484 mouse@1 {
485 reg = <0x1>;
486 compatible = "pnpPNP,f03";
487 };
488 };
489
490 rtc@70 {
491 compatible = "pnpPNP,b00";
492 reg = <0x1 0x70 0x2>;
493 };
494
495 gpio@400 {
496 reg = <0x1 0x400 0x80>;
497 };
498 };
499 };
500 }; 95 };
501 }; 96 };
502}; 97};
98
99/*
100 * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
101 * for interrupt-map & interrupt-map-mask
102 */
103
104/include/ "fsl/mpc8544si-post.dtsi"
105/include/ "mpc8544ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
new file mode 100644
index 00000000000..270f64b90f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -0,0 +1,161 @@
1/*
2 * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_soc {
36 enet0: ethernet@24000 {
37 phy-handle = <&phy0>;
38 tbi-handle = <&tbi0>;
39 phy-connection-type = "rgmii-id";
40 };
41
42 mdio@24520 {
43 phy0: ethernet-phy@0 {
44 interrupts = <10 1 0 0>;
45 reg = <0x0>;
46 device_type = "ethernet-phy";
47 };
48 phy1: ethernet-phy@1 {
49 interrupts = <10 1 0 0>;
50 reg = <0x1>;
51 device_type = "ethernet-phy";
52 };
53
54 tbi0: tbi-phy@11 {
55 reg = <0x11>;
56 device_type = "tbi-phy";
57 };
58 };
59
60 enet2: ethernet@26000 {
61 phy-handle = <&phy1>;
62 tbi-handle = <&tbi1>;
63 phy-connection-type = "rgmii-id";
64 };
65
66 mdio@26520 {
67 tbi1: tbi-phy@11 {
68 reg = <0x11>;
69 device_type = "tbi-phy";
70 };
71 };
72};
73
74&board_pci3 {
75 pcie@0 {
76 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
77 interrupt-map = <
78 // IDSEL 0x1c USB
79 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
80 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
81 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
82 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
83
84 // IDSEL 0x1d Audio
85 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
86
87 // IDSEL 0x1e Legacy
88 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
89 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
90
91 // IDSEL 0x1f IDE/SATA
92 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
93 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
94 >;
95
96
97 uli1575@0 {
98 reg = <0x0 0x0 0x0 0x0 0x0>;
99 #size-cells = <2>;
100 #address-cells = <3>;
101 ranges = <0x2000000 0x0 0xb0000000
102 0x2000000 0x0 0xb0000000
103 0x0 0x100000
104
105 0x1000000 0x0 0x0
106 0x1000000 0x0 0x0
107 0x0 0x100000>;
108 isa@1e {
109 device_type = "isa";
110 #interrupt-cells = <2>;
111 #size-cells = <1>;
112 #address-cells = <2>;
113 reg = <0xf000 0x0 0x0 0x0 0x0>;
114 ranges = <0x1 0x0 0x1000000 0x0 0x0
115 0x1000>;
116 interrupt-parent = <&i8259>;
117
118 i8259: interrupt-controller@20 {
119 reg = <0x1 0x20 0x2
120 0x1 0xa0 0x2
121 0x1 0x4d0 0x2>;
122 interrupt-controller;
123 device_type = "interrupt-controller";
124 #address-cells = <0>;
125 #interrupt-cells = <2>;
126 compatible = "chrp,iic";
127 interrupts = <9 2 0 0>;
128 interrupt-parent = <&mpic>;
129 };
130
131 i8042@60 {
132 #size-cells = <0>;
133 #address-cells = <1>;
134 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
135 interrupts = <1 3 12 3>;
136 interrupt-parent =
137 <&i8259>;
138
139 keyboard@0 {
140 reg = <0x0>;
141 compatible = "pnpPNP,303";
142 };
143
144 mouse@1 {
145 reg = <0x1>;
146 compatible = "pnpPNP,f03";
147 };
148 };
149
150 rtc@70 {
151 compatible = "pnpPNP,b00";
152 reg = <0x1 0x70 0x2>;
153 };
154
155 gpio@400 {
156 reg = <0x1 0x400 0x80>;
157 };
158 };
159 };
160 };
161};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index a17a5572fb7..07b8dae0f46 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -9,13 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8548si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS"; 16 compatible = "MPC8548CDS", "MPC85xxCDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -29,76 +27,19 @@
29 pci2 = &pci2; 27 pci2 = &pci2;
30 }; 28 };
31 29
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8548@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // 33 MHz, from uboot
44 bus-frequency = <0>; // 166 MHz
45 clock-frequency = <0>; // 825 MHz, from uboot
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory { 30 memory {
51 device_type = "memory"; 31 device_type = "memory";
52 reg = <0x0 0x8000000>; // 128M at 0x0 32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
53 }; 33 };
54 34
55 soc8548@e0000000 { 35 lbc: localbus@e0005000 {
56 #address-cells = <1>; 36 reg = <0 0xe0005000 0 0x1000>;
57 #size-cells = <1>; 37 };
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xe0000000 0x100000>;
61 bus-frequency = <0>;
62
63 ecm-law@0 {
64 compatible = "fsl,ecm-law";
65 reg = <0x0 0x1000>;
66 fsl,num-laws = <10>;
67 };
68
69 ecm@1000 {
70 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
71 reg = <0x1000 0x1000>;
72 interrupts = <17 2>;
73 interrupt-parent = <&mpic>;
74 };
75
76 memory-controller@2000 {
77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>;
81 };
82 38
83 L2: l2-cache-controller@20000 { 39 soc: soc8548@e0000000 {
84 compatible = "fsl,mpc8548-l2-cache-controller"; 40 ranges = <0 0x0 0xe0000000 0x100000>;
85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K
88 interrupt-parent = <&mpic>;
89 interrupts = <16 2>;
90 };
91 41
92 i2c@3000 { 42 i2c@3000 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <0>;
96 compatible = "fsl-i2c";
97 reg = <0x3000 0x100>;
98 interrupts = <43 2>;
99 interrupt-parent = <&mpic>;
100 dfsrr;
101
102 eeprom@50 { 43 eeprom@50 {
103 compatible = "atmel,24c64"; 44 compatible = "atmel,24c64";
104 reg = <0x50>; 45 reg = <0x50>;
@@ -116,351 +57,178 @@
116 }; 57 };
117 58
118 i2c@3100 { 59 i2c@3100 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 cell-index = <1>;
122 compatible = "fsl-i2c";
123 reg = <0x3100 0x100>;
124 interrupts = <43 2>;
125 interrupt-parent = <&mpic>;
126 dfsrr;
127
128 eeprom@50 { 60 eeprom@50 {
129 compatible = "atmel,24c64"; 61 compatible = "atmel,24c64";
130 reg = <0x50>; 62 reg = <0x50>;
131 }; 63 };
132 }; 64 };
133 65
134 dma@21300 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
138 reg = <0x21300 0x4>;
139 ranges = <0x0 0x21100 0x200>;
140 cell-index = <0>;
141 dma-channel@0 {
142 compatible = "fsl,mpc8548-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x0 0x80>;
145 cell-index = <0>;
146 interrupt-parent = <&mpic>;
147 interrupts = <20 2>;
148 };
149 dma-channel@80 {
150 compatible = "fsl,mpc8548-dma-channel",
151 "fsl,eloplus-dma-channel";
152 reg = <0x80 0x80>;
153 cell-index = <1>;
154 interrupt-parent = <&mpic>;
155 interrupts = <21 2>;
156 };
157 dma-channel@100 {
158 compatible = "fsl,mpc8548-dma-channel",
159 "fsl,eloplus-dma-channel";
160 reg = <0x100 0x80>;
161 cell-index = <2>;
162 interrupt-parent = <&mpic>;
163 interrupts = <22 2>;
164 };
165 dma-channel@180 {
166 compatible = "fsl,mpc8548-dma-channel",
167 "fsl,eloplus-dma-channel";
168 reg = <0x180 0x80>;
169 cell-index = <3>;
170 interrupt-parent = <&mpic>;
171 interrupts = <23 2>;
172 };
173 };
174
175 enet0: ethernet@24000 { 66 enet0: ethernet@24000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 cell-index = <0>;
179 device_type = "network";
180 model = "eTSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 ranges = <0x0 0x24000 0x1000>;
184 local-mac-address = [ 00 00 00 00 00 00 ];
185 interrupts = <29 2 30 2 34 2>;
186 interrupt-parent = <&mpic>;
187 tbi-handle = <&tbi0>; 67 tbi-handle = <&tbi0>;
188 phy-handle = <&phy0>; 68 phy-handle = <&phy0>;
69 };
189 70
190 mdio@520 { 71 mdio@24520 {
191 #address-cells = <1>; 72 phy0: ethernet-phy@0 {
192 #size-cells = <0>; 73 interrupts = <5 1 0 0>;
193 compatible = "fsl,gianfar-mdio"; 74 reg = <0x0>;
194 reg = <0x520 0x20>; 75 device_type = "ethernet-phy";
195 76 };
196 phy0: ethernet-phy@0 { 77 phy1: ethernet-phy@1 {
197 interrupt-parent = <&mpic>; 78 interrupts = <5 1 0 0>;
198 interrupts = <5 1>; 79 reg = <0x1>;
199 reg = <0x0>; 80 device_type = "ethernet-phy";
200 device_type = "ethernet-phy"; 81 };
201 }; 82 phy2: ethernet-phy@2 {
202 phy1: ethernet-phy@1 { 83 interrupts = <5 1 0 0>;
203 interrupt-parent = <&mpic>; 84 reg = <0x2>;
204 interrupts = <5 1>; 85 device_type = "ethernet-phy";
205 reg = <0x1>; 86 };
206 device_type = "ethernet-phy"; 87 phy3: ethernet-phy@3 {
207 }; 88 interrupts = <5 1 0 0>;
208 phy2: ethernet-phy@2 { 89 reg = <0x3>;
209 interrupt-parent = <&mpic>; 90 device_type = "ethernet-phy";
210 interrupts = <5 1>; 91 };
211 reg = <0x2>; 92 tbi0: tbi-phy@11 {
212 device_type = "ethernet-phy"; 93 reg = <0x11>;
213 }; 94 device_type = "tbi-phy";
214 phy3: ethernet-phy@3 {
215 interrupt-parent = <&mpic>;
216 interrupts = <5 1>;
217 reg = <0x3>;
218 device_type = "ethernet-phy";
219 };
220 tbi0: tbi-phy@11 {
221 reg = <0x11>;
222 device_type = "tbi-phy";
223 };
224 }; 95 };
225 }; 96 };
226 97
227 enet1: ethernet@25000 { 98 enet1: ethernet@25000 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 cell-index = <1>;
231 device_type = "network";
232 model = "eTSEC";
233 compatible = "gianfar";
234 reg = <0x25000 0x1000>;
235 ranges = <0x0 0x25000 0x1000>;
236 local-mac-address = [ 00 00 00 00 00 00 ];
237 interrupts = <35 2 36 2 40 2>;
238 interrupt-parent = <&mpic>;
239 tbi-handle = <&tbi1>; 99 tbi-handle = <&tbi1>;
240 phy-handle = <&phy1>; 100 phy-handle = <&phy1>;
101 };
241 102
242 mdio@520 { 103 mdio@25520 {
243 #address-cells = <1>; 104 tbi1: tbi-phy@11 {
244 #size-cells = <0>; 105 reg = <0x11>;
245 compatible = "fsl,gianfar-tbi"; 106 device_type = "tbi-phy";
246 reg = <0x520 0x20>;
247
248 tbi1: tbi-phy@11 {
249 reg = <0x11>;
250 device_type = "tbi-phy";
251 };
252 }; 107 };
253 }; 108 };
254 109
255 enet2: ethernet@26000 { 110 enet2: ethernet@26000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 cell-index = <2>;
259 device_type = "network";
260 model = "eTSEC";
261 compatible = "gianfar";
262 reg = <0x26000 0x1000>;
263 ranges = <0x0 0x26000 0x1000>;
264 local-mac-address = [ 00 00 00 00 00 00 ];
265 interrupts = <31 2 32 2 33 2>;
266 interrupt-parent = <&mpic>;
267 tbi-handle = <&tbi2>; 111 tbi-handle = <&tbi2>;
268 phy-handle = <&phy2>; 112 phy-handle = <&phy2>;
113 };
269 114
270 mdio@520 { 115 mdio@26520 {
271 #address-cells = <1>; 116 tbi2: tbi-phy@11 {
272 #size-cells = <0>; 117 reg = <0x11>;
273 compatible = "fsl,gianfar-tbi"; 118 device_type = "tbi-phy";
274 reg = <0x520 0x20>;
275
276 tbi2: tbi-phy@11 {
277 reg = <0x11>;
278 device_type = "tbi-phy";
279 };
280 }; 119 };
281 }; 120 };
282 121
283 enet3: ethernet@27000 { 122 enet3: ethernet@27000 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 cell-index = <3>;
287 device_type = "network";
288 model = "eTSEC";
289 compatible = "gianfar";
290 reg = <0x27000 0x1000>;
291 ranges = <0x0 0x27000 0x1000>;
292 local-mac-address = [ 00 00 00 00 00 00 ];
293 interrupts = <37 2 38 2 39 2>;
294 interrupt-parent = <&mpic>;
295 tbi-handle = <&tbi3>; 123 tbi-handle = <&tbi3>;
296 phy-handle = <&phy3>; 124 phy-handle = <&phy3>;
297
298 mdio@520 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "fsl,gianfar-tbi";
302 reg = <0x520 0x20>;
303
304 tbi3: tbi-phy@11 {
305 reg = <0x11>;
306 device_type = "tbi-phy";
307 };
308 };
309 };
310
311 serial0: serial@4500 {
312 cell-index = <0>;
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>; // reg base, size
316 clock-frequency = <0>; // should we fill in in uboot?
317 interrupts = <42 2>;
318 interrupt-parent = <&mpic>;
319 };
320
321 serial1: serial@4600 {
322 cell-index = <1>;
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>; // reg base, size
326 clock-frequency = <0>; // should we fill in in uboot?
327 interrupts = <42 2>;
328 interrupt-parent = <&mpic>;
329 }; 125 };
330 126
331 global-utilities@e0000 { //global utilities reg 127 mdio@27520 {
332 compatible = "fsl,mpc8548-guts"; 128 tbi3: tbi-phy@11 {
333 reg = <0xe0000 0x1000>; 129 reg = <0x11>;
334 fsl,has-rstcr; 130 device_type = "tbi-phy";
335 }; 131 };
336
337 crypto@30000 {
338 compatible = "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000>;
340 interrupts = <45 2>;
341 interrupt-parent = <&mpic>;
342 fsl,num-channels = <4>;
343 fsl,channel-fifo-len = <24>;
344 fsl,exec-units-mask = <0xfe>;
345 fsl,descriptor-types-mask = <0x12b0ebf>;
346 };
347
348 mpic: pic@40000 {
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <0x40000 0x40000>;
353 compatible = "chrp,open-pic";
354 device_type = "open-pic";
355 }; 132 };
356 }; 133 };
357 134
358 pci0: pci@e0008000 { 135 pci0: pci@e0008000 {
136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
359 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 interrupt-map = < 141 interrupt-map = <
361 /* IDSEL 0x4 (PCIX Slot 2) */ 142 /* IDSEL 0x4 (PCIX Slot 2) */
362 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
363 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
364 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
365 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
366 147
367 /* IDSEL 0x5 (PCIX Slot 3) */ 148 /* IDSEL 0x5 (PCIX Slot 3) */
368 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
369 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
370 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
371 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
372 153
373 /* IDSEL 0x6 (PCIX Slot 4) */ 154 /* IDSEL 0x6 (PCIX Slot 4) */
374 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
375 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
376 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
377 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
378 159
379 /* IDSEL 0x8 (PCIX Slot 5) */ 160 /* IDSEL 0x8 (PCIX Slot 5) */
380 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
381 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
382 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
383 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
384 165
385 /* IDSEL 0xC (Tsi310 bridge) */ 166 /* IDSEL 0xC (Tsi310 bridge) */
386 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
387 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
388 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
389 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
390 171
391 /* IDSEL 0x14 (Slot 2) */ 172 /* IDSEL 0x14 (Slot 2) */
392 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
393 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
394 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
395 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
396 177
397 /* IDSEL 0x15 (Slot 3) */ 178 /* IDSEL 0x15 (Slot 3) */
398 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
399 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
400 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
401 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
402 183
403 /* IDSEL 0x16 (Slot 4) */ 184 /* IDSEL 0x16 (Slot 4) */
404 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
405 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
406 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
407 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
408 189
409 /* IDSEL 0x18 (Slot 5) */ 190 /* IDSEL 0x18 (Slot 5) */
410 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
411 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
412 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
413 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
414 195
415 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
416 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
417 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
418 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
419 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>; 200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
420
421 interrupt-parent = <&mpic>;
422 interrupts = <24 2>;
423 bus-range = <0 0>;
424 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
425 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <66666666>;
427 #interrupt-cells = <1>;
428 #size-cells = <2>;
429 #address-cells = <3>;
430 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
432 device_type = "pci";
433 201
434 pci_bridge@1c { 202 pci_bridge@1c {
435 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
436 interrupt-map = < 204 interrupt-map = <
437 205
438 /* IDSEL 0x00 (PrPMC Site) */ 206 /* IDSEL 0x00 (PrPMC Site) */
439 0000 0x0 0x0 0x1 &mpic 0x0 0x1 207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
440 0000 0x0 0x0 0x2 &mpic 0x1 0x1 208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
441 0000 0x0 0x0 0x3 &mpic 0x2 0x1 209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
442 0000 0x0 0x0 0x4 &mpic 0x3 0x1 210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
443 211
444 /* IDSEL 0x04 (VIA chip) */ 212 /* IDSEL 0x04 (VIA chip) */
445 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
446 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
447 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
448 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
449 217
450 /* IDSEL 0x05 (8139) */ 218 /* IDSEL 0x05 (8139) */
451 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
452 220
453 /* IDSEL 0x06 (Slot 6) */ 221 /* IDSEL 0x06 (Slot 6) */
454 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
455 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
456 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
457 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
458 226
459 /* IDESL 0x07 (Slot 7) */ 227 /* IDESL 0x07 (Slot 7) */
460 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
461 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
462 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
463 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>; 231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
464 232
465 reg = <0xe000 0x0 0x0 0x0 0x0>; 233 reg = <0xe000 0x0 0x0 0x0 0x0>;
466 #interrupt-cells = <1>; 234 #interrupt-cells = <1>;
@@ -492,7 +260,7 @@
492 #address-cells = <0>; 260 #address-cells = <0>;
493 #interrupt-cells = <2>; 261 #interrupt-cells = <2>;
494 compatible = "chrp,iic"; 262 compatible = "chrp,iic";
495 interrupts = <0 1>; 263 interrupts = <0 1 0 0>;
496 interrupt-parent = <&mpic>; 264 interrupt-parent = <&mpic>;
497 }; 265 };
498 266
@@ -505,56 +273,25 @@
505 }; 273 };
506 274
507 pci1: pci@e0009000 { 275 pci1: pci@e0009000 {
276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
508 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
509 interrupt-map = < 281 interrupt-map = <
510 282
511 /* IDSEL 0x15 */ 283 /* IDSEL 0x15 */
512 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
513 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
514 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
515 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>; 287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
516
517 interrupt-parent = <&mpic>;
518 interrupts = <25 2>;
519 bus-range = <0 0>;
520 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
521 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
522 clock-frequency = <66666666>;
523 #interrupt-cells = <1>;
524 #size-cells = <2>;
525 #address-cells = <3>;
526 reg = <0xe0009000 0x1000>;
527 compatible = "fsl,mpc8540-pci";
528 device_type = "pci";
529 }; 288 };
530 289
531 pci2: pcie@e000a000 { 290 pci2: pcie@e000a000 {
532 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 291 reg = <0 0xe000a000 0 0x1000>;
533 interrupt-map = < 292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
534 293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
535 /* IDSEL 0x0 (PEX) */
536 00000 0x0 0x0 0x1 &mpic 0x0 0x1
537 00000 0x0 0x0 0x2 &mpic 0x1 0x1
538 00000 0x0 0x0 0x3 &mpic 0x2 0x1
539 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
540
541 interrupt-parent = <&mpic>;
542 interrupts = <26 2>;
543 bus-range = <0 255>;
544 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
545 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
546 clock-frequency = <33333333>;
547 #interrupt-cells = <1>;
548 #size-cells = <2>;
549 #address-cells = <3>;
550 reg = <0xe000a000 0x1000>;
551 compatible = "fsl,mpc8548-pcie";
552 device_type = "pci";
553 pcie@0 { 294 pcie@0 {
554 reg = <0x0 0x0 0x0 0x0 0x0>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 ranges = <0x2000000 0x0 0xa0000000 295 ranges = <0x2000000 0x0 0xa0000000
559 0x2000000 0x0 0xa0000000 296 0x2000000 0x0 0xa0000000
560 0x0 0x20000000 297 0x0 0x20000000
@@ -565,3 +302,5 @@
565 }; 302 };
566 }; 303 };
567}; 304};
305
306/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 5c5614f9eb1..fe10438613d 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -209,7 +209,7 @@
209 serial0: serial@4500 { 209 serial0: serial@4500 {
210 cell-index = <0>; 210 cell-index = <0>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4500 0x100>; // reg base, size 213 reg = <0x4500 0x100>; // reg base, size
214 clock-frequency = <0>; // should we fill in in uboot? 214 clock-frequency = <0>; // should we fill in in uboot?
215 interrupts = <42 2>; 215 interrupts = <42 2>;
@@ -219,7 +219,7 @@
219 serial1: serial@4600 { 219 serial1: serial@4600 {
220 cell-index = <1>; 220 cell-index = <1>;
221 device_type = "serial"; 221 device_type = "serial";
222 compatible = "ns16550"; 222 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4600 0x100>; // reg base, size 223 reg = <0x4600 0x100>; // reg base, size
224 clock-frequency = <0>; // should we fill in in uboot? 224 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 225 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 647daf8e729..09598bb5d44 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -9,60 +9,25 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8568si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS"; 16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0; 19 pci0 = &pci0;
28 pci1 = &pci1; 20 pci1 = &pci1;
29 rapidio0 = &rio0; 21 rapidio0 = &rio;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8568@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 sleep = <&pmc 0x00008000 // core
44 &pmc 0x00004000>; // timebase
45 timebase-frequency = <0>;
46 bus-frequency = <0>;
47 clock-frequency = <0>;
48 next-level-cache = <&L2>;
49 };
50 }; 22 };
51 23
52 memory { 24 memory {
53 device_type = "memory"; 25 device_type = "memory";
54 reg = <0x0 0x10000000>; 26 reg = <0x0 0x0 0x0 0x0>;
55 }; 27 };
56 28
57 localbus@e0005000 { 29 lbc: localbus@e0005000 {
58 #address-cells = <2>; 30 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>;
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus";
62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
65
66 ranges = <0x0 0x0 0xfe000000 0x02000000 31 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000 32 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000 33 0x2 0x0 0xf0000000 0x04000000
@@ -104,288 +69,65 @@
104 }; 69 };
105 }; 70 };
106 71
107 soc8568@e0000000 { 72 soc: soc8568@e0000000 {
108 #address-cells = <1>; 73 ranges = <0x0 0x0 0xe0000000 0x100000>;
109 #size-cells = <1>;
110 device_type = "soc";
111 compatible = "simple-bus";
112 ranges = <0x0 0xe0000000 0x100000>;
113 bus-frequency = <0>;
114
115 ecm-law@0 {
116 compatible = "fsl,ecm-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <10>;
119 };
120
121 ecm@1000 {
122 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
123 reg = <0x1000 0x1000>;
124 interrupts = <17 2>;
125 interrupt-parent = <&mpic>;
126 };
127
128 memory-controller@2000 {
129 compatible = "fsl,mpc8568-memory-controller";
130 reg = <0x2000 0x1000>;
131 interrupt-parent = <&mpic>;
132 interrupts = <18 2>;
133 };
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,mpc8568-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x80000>; // L2, 512K
140 interrupt-parent = <&mpic>;
141 interrupts = <16 2>;
142 };
143 74
144 i2c-sleep-nexus { 75 i2c-sleep-nexus {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 sleep = <&pmc 0x00000004>;
149 ranges;
150
151 i2c@3000 { 76 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
160
161 rtc@68 { 77 rtc@68 {
162 compatible = "dallas,ds1374"; 78 compatible = "dallas,ds1374";
163 reg = <0x68>; 79 reg = <0x68>;
164 interrupts = <3 1>; 80 interrupts = <3 1 0 0>;
165 interrupt-parent = <&mpic>;
166 }; 81 };
167 }; 82 };
83 };
168 84
169 i2c@3100 { 85 enet0: ethernet@24000 {
170 #address-cells = <1>; 86 tbi-handle = <&tbi0>;
171 #size-cells = <0>; 87 phy-handle = <&phy2>;
172 cell-index = <1>;
173 compatible = "fsl-i2c";
174 reg = <0x3100 0x100>;
175 interrupts = <43 2>;
176 interrupt-parent = <&mpic>;
177 dfsrr;
178 };
179 }; 88 };
180 89
181 dma@21300 { 90 mdio@24520 {
182 #address-cells = <1>; 91 phy0: ethernet-phy@7 {
183 #size-cells = <1>; 92 interrupts = <1 1 0 0>;
184 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; 93 reg = <0x7>;
185 reg = <0x21300 0x4>; 94 device_type = "ethernet-phy";
186 ranges = <0x0 0x21100 0x200>;
187 cell-index = <0>;
188 sleep = <&pmc 0x00000400>;
189
190 dma-channel@0 {
191 compatible = "fsl,mpc8568-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&mpic>;
196 interrupts = <20 2>;
197 }; 95 };
198 dma-channel@80 { 96 phy1: ethernet-phy@1 {
199 compatible = "fsl,mpc8568-dma-channel", 97 interrupts = <2 1 0 0>;
200 "fsl,eloplus-dma-channel"; 98 reg = <0x1>;
201 reg = <0x80 0x80>; 99 device_type = "ethernet-phy";
202 cell-index = <1>;
203 interrupt-parent = <&mpic>;
204 interrupts = <21 2>;
205 }; 100 };
206 dma-channel@100 { 101 phy2: ethernet-phy@2 {
207 compatible = "fsl,mpc8568-dma-channel", 102 interrupts = <1 1 0 0>;
208 "fsl,eloplus-dma-channel"; 103 reg = <0x2>;
209 reg = <0x100 0x80>; 104 device_type = "ethernet-phy";
210 cell-index = <2>;
211 interrupt-parent = <&mpic>;
212 interrupts = <22 2>;
213 }; 105 };
214 dma-channel@180 { 106 phy3: ethernet-phy@3 {
215 compatible = "fsl,mpc8568-dma-channel", 107 interrupts = <2 1 0 0>;
216 "fsl,eloplus-dma-channel"; 108 reg = <0x3>;
217 reg = <0x180 0x80>; 109 device_type = "ethernet-phy";
218 cell-index = <3>;
219 interrupt-parent = <&mpic>;
220 interrupts = <23 2>;
221 }; 110 };
222 }; 111 tbi0: tbi-phy@11 {
223 112 reg = <0x11>;
224 enet0: ethernet@24000 { 113 device_type = "tbi-phy";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy2>;
238 sleep = <&pmc 0x00000080>;
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@7 {
247 interrupt-parent = <&mpic>;
248 interrupts = <1 1>;
249 reg = <0x7>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <2 1>;
255 reg = <0x1>;
256 device_type = "ethernet-phy";
257 };
258 phy2: ethernet-phy@2 {
259 interrupt-parent = <&mpic>;
260 interrupts = <1 1>;
261 reg = <0x2>;
262 device_type = "ethernet-phy";
263 };
264 phy3: ethernet-phy@3 {
265 interrupt-parent = <&mpic>;
266 interrupts = <2 1>;
267 reg = <0x3>;
268 device_type = "ethernet-phy";
269 };
270 tbi0: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 }; 114 };
275 }; 115 };
276 116
277 enet1: ethernet@25000 { 117 enet1: ethernet@25000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <1>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x25000 0x1000>;
285 ranges = <0x0 0x25000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <35 2 36 2 40 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi1>; 118 tbi-handle = <&tbi1>;
290 phy-handle = <&phy3>; 119 phy-handle = <&phy3>;
291 sleep = <&pmc 0x00000040>; 120 sleep = <&pmc 0x00000040>;
292
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
298
299 tbi1: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 }; 121 };
305 122
306 duart-sleep-nexus { 123 mdio@25520 {
307 #address-cells = <1>; 124 tbi1: tbi-phy@11 {
308 #size-cells = <1>; 125 reg = <0x11>;
309 compatible = "simple-bus"; 126 device_type = "tbi-phy";
310 sleep = <&pmc 0x00000002>;
311 ranges;
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 2>;
330 interrupt-parent = <&mpic>;
331 }; 127 };
332 }; 128 };
333 129
334 global-utilities@e0000 {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
338 reg = <0xe0000 0x1000>;
339 ranges = <0 0xe0000 0x1000>;
340 fsl,has-rstcr;
341
342 pmc: power@70 {
343 compatible = "fsl,mpc8568-pmc",
344 "fsl,mpc8548-pmc";
345 reg = <0x70 0x20>;
346 };
347 };
348
349 crypto@30000 {
350 compatible = "fsl,sec2.1", "fsl,sec2.0";
351 reg = <0x30000 0x10000>;
352 interrupts = <45 2>;
353 interrupt-parent = <&mpic>;
354 fsl,num-channels = <4>;
355 fsl,channel-fifo-len = <24>;
356 fsl,exec-units-mask = <0xfe>;
357 fsl,descriptor-types-mask = <0x12b0ebf>;
358 sleep = <&pmc 0x01000000>;
359 };
360
361 mpic: pic@40000 {
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x40000 0x40000>;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 };
369
370 msi@41600 {
371 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
372 reg = <0x41600 0x80>;
373 msi-available-ranges = <0 0x100>;
374 interrupts = <
375 0xe0 0
376 0xe1 0
377 0xe2 0
378 0xe3 0
379 0xe4 0
380 0xe5 0
381 0xe6 0
382 0xe7 0>;
383 interrupt-parent = <&mpic>;
384 };
385
386 par_io@e0100 { 130 par_io@e0100 {
387 reg = <0xe0100 0x100>;
388 device_type = "par_io";
389 num-ports = <7>; 131 num-ports = <7>;
390 132
391 pio1: ucc_pin@01 { 133 pio1: ucc_pin@01 {
@@ -448,57 +190,21 @@
448 }; 190 };
449 }; 191 };
450 192
451 qe@e0080000 { 193 qe: qe@e0080000 {
452 #address-cells = <1>; 194 ranges = <0x0 0x0 0xe0080000 0x40000>;
453 #size-cells = <1>; 195 reg = <0x0 0xe0080000 0x0 0x480>;
454 device_type = "qe";
455 compatible = "fsl,qe";
456 ranges = <0x0 0xe0080000 0x40000>;
457 reg = <0xe0080000 0x480>;
458 sleep = <&pmc 0x00000800>;
459 brg-frequency = <0>;
460 bus-frequency = <396000000>;
461 fsl,qe-num-riscs = <2>;
462 fsl,qe-num-snums = <28>;
463
464 muram@10000 {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "fsl,qe-muram", "fsl,cpm-muram";
468 ranges = <0x0 0x10000 0x10000>;
469
470 data-only@0 {
471 compatible = "fsl,qe-muram-data",
472 "fsl,cpm-muram-data";
473 reg = <0x0 0x10000>;
474 };
475 };
476 196
477 spi@4c0 { 197 spi@4c0 {
478 cell-index = <0>;
479 compatible = "fsl,spi";
480 reg = <0x4c0 0x40>;
481 interrupts = <2>;
482 interrupt-parent = <&qeic>;
483 mode = "cpu"; 198 mode = "cpu";
484 }; 199 };
485 200
486 spi@500 { 201 spi@500 {
487 cell-index = <1>;
488 compatible = "fsl,spi";
489 reg = <0x500 0x40>;
490 interrupts = <1>;
491 interrupt-parent = <&qeic>;
492 mode = "cpu"; 202 mode = "cpu";
493 }; 203 };
494 204
495 enet2: ucc@2000 { 205 enet2: ucc@2000 {
496 device_type = "network"; 206 device_type = "network";
497 compatible = "ucc_geth"; 207 compatible = "ucc_geth";
498 cell-index = <1>;
499 reg = <0x2000 0x200>;
500 interrupts = <32>;
501 interrupt-parent = <&qeic>;
502 local-mac-address = [ 00 00 00 00 00 00 ]; 208 local-mac-address = [ 00 00 00 00 00 00 ];
503 rx-clock-name = "none"; 209 rx-clock-name = "none";
504 tx-clock-name = "clk16"; 210 tx-clock-name = "clk16";
@@ -510,10 +216,6 @@
510 enet3: ucc@3000 { 216 enet3: ucc@3000 {
511 device_type = "network"; 217 device_type = "network";
512 compatible = "ucc_geth"; 218 compatible = "ucc_geth";
513 cell-index = <2>;
514 reg = <0x3000 0x200>;
515 interrupts = <33>;
516 interrupt-parent = <&qeic>;
517 local-mac-address = [ 00 00 00 00 00 00 ]; 219 local-mac-address = [ 00 00 00 00 00 00 ];
518 rx-clock-name = "none"; 220 rx-clock-name = "none";
519 tx-clock-name = "clk16"; 221 tx-clock-name = "clk16";
@@ -532,102 +234,57 @@
532 * gianfar's MDIO bus */ 234 * gianfar's MDIO bus */
533 qe_phy0: ethernet-phy@07 { 235 qe_phy0: ethernet-phy@07 {
534 interrupt-parent = <&mpic>; 236 interrupt-parent = <&mpic>;
535 interrupts = <1 1>; 237 interrupts = <1 1 0 0>;
536 reg = <0x7>; 238 reg = <0x7>;
537 device_type = "ethernet-phy"; 239 device_type = "ethernet-phy";
538 }; 240 };
539 qe_phy1: ethernet-phy@01 { 241 qe_phy1: ethernet-phy@01 {
540 interrupt-parent = <&mpic>; 242 interrupt-parent = <&mpic>;
541 interrupts = <2 1>; 243 interrupts = <2 1 0 0>;
542 reg = <0x1>; 244 reg = <0x1>;
543 device_type = "ethernet-phy"; 245 device_type = "ethernet-phy";
544 }; 246 };
545 qe_phy2: ethernet-phy@02 { 247 qe_phy2: ethernet-phy@02 {
546 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
547 interrupts = <1 1>; 249 interrupts = <1 1 0 0>;
548 reg = <0x2>; 250 reg = <0x2>;
549 device_type = "ethernet-phy"; 251 device_type = "ethernet-phy";
550 }; 252 };
551 qe_phy3: ethernet-phy@03 { 253 qe_phy3: ethernet-phy@03 {
552 interrupt-parent = <&mpic>; 254 interrupt-parent = <&mpic>;
553 interrupts = <2 1>; 255 interrupts = <2 1 0 0>;
554 reg = <0x3>; 256 reg = <0x3>;
555 device_type = "ethernet-phy"; 257 device_type = "ethernet-phy";
556 }; 258 };
557 }; 259 };
558
559 qeic: interrupt-controller@80 {
560 interrupt-controller;
561 compatible = "fsl,qe-ic";
562 #address-cells = <0>;
563 #interrupt-cells = <1>;
564 reg = <0x80 0x80>;
565 big-endian;
566 interrupts = <46 2 46 2>; //high:30 low:30
567 interrupt-parent = <&mpic>;
568 };
569
570 }; 260 };
571 261
572 pci0: pci@e0008000 { 262 pci0: pci@e0008000 {
263 reg = <0x0 0xe0008000 0x0 0x1000>;
264 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
265 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
266 clock-frequency = <66666666>;
573 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 267 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
574 interrupt-map = < 268 interrupt-map = <
575 /* IDSEL 0x12 AD18 */ 269 /* IDSEL 0x12 AD18 */
576 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 270 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
577 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 271 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
578 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 272 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
579 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 273 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
580 274
581 /* IDSEL 0x13 AD19 */ 275 /* IDSEL 0x13 AD19 */
582 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 276 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
583 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 277 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
584 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 278 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
585 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>; 279 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
586
587 interrupt-parent = <&mpic>;
588 interrupts = <24 2>;
589 bus-range = <0 255>;
590 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
591 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
592 sleep = <&pmc 0x80000000>;
593 clock-frequency = <66666666>;
594 #interrupt-cells = <1>;
595 #size-cells = <2>;
596 #address-cells = <3>;
597 reg = <0xe0008000 0x1000>;
598 compatible = "fsl,mpc8540-pci";
599 device_type = "pci";
600 }; 280 };
601 281
602 /* PCI Express */ 282 /* PCI Express */
603 pci1: pcie@e000a000 { 283 pci1: pcie@e000a000 {
604 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 284 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
605 interrupt-map = < 285 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
606 286 reg = <0x0 0xe000a000 0x0 0x1000>;
607 /* IDSEL 0x0 (PEX) */
608 00000 0x0 0x0 0x1 &mpic 0x0 0x1
609 00000 0x0 0x0 0x2 &mpic 0x1 0x1
610 00000 0x0 0x0 0x3 &mpic 0x2 0x1
611 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
612
613 interrupt-parent = <&mpic>;
614 interrupts = <26 2>;
615 bus-range = <0 255>;
616 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
617 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
618 sleep = <&pmc 0x20000000>;
619 clock-frequency = <33333333>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 reg = <0xe000a000 0x1000>;
624 compatible = "fsl,mpc8548-pcie";
625 device_type = "pci";
626 pcie@0 { 287 pcie@0 {
627 reg = <0x0 0x0 0x0 0x0 0x0>;
628 #size-cells = <2>;
629 #address-cells = <3>;
630 device_type = "pci";
631 ranges = <0x2000000 0x0 0xa0000000 288 ranges = <0x2000000 0x0 0xa0000000
632 0x2000000 0x0 0xa0000000 289 0x2000000 0x0 0xa0000000
633 0x0 0x10000000 290 0x0 0x10000000
@@ -638,22 +295,11 @@
638 }; 295 };
639 }; 296 };
640 297
641 rio0: rapidio@e00c00000 { 298 rio: rapidio@e00c00000 {
642 #address-cells = <2>; 299 reg = <0x0 0xe00c0000 0x0 0x20000>;
643 #size-cells = <2>; 300 port1 {
644 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; 301 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
645 reg = <0xe00c0000 0x20000>; 302 };
646 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
647 interrupts = <48 2 /* error */
648 49 2 /* bell_outb */
649 50 2 /* bell_inb */
650 53 2 /* msg1_tx */
651 54 2 /* msg1_rx */
652 55 2 /* msg2_tx */
653 56 2 /* msg2_rx */>;
654 interrupt-parent = <&mpic>;
655 sleep = <&pmc 0x00080000 /* controller */
656 &pmc 0x00040000>; /* message unit */
657 }; 303 };
658 304
659 leds { 305 leds {
@@ -672,3 +318,5 @@
672 }; 318 };
673 }; 319 };
674}; 320};
321
322/include/ "fsl/mpc8568si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 8b72eaff5b0..7e283c891b7 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -9,66 +9,36 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8569si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8569EMDS"; 15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS"; 16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 interrupt-parent = <&mpic>;
19 20
20 aliases { 21 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2; 22 ethernet2 = &enet2;
26 ethernet3 = &enet3; 23 ethernet3 = &enet3;
27 ethernet5 = &enet5; 24 ethernet5 = &enet5;
28 ethernet7 = &enet7; 25 ethernet7 = &enet7;
29 pci1 = &pci1; 26 rapidio0 = &rio;
30 rapidio0 = &rio0;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 sleep = <&pmc 0x00008000 // core
45 &pmc 0x00004000>; // timebase
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 next-level-cache = <&L2>;
50 };
51 }; 27 };
52 28
53 memory { 29 memory {
54 device_type = "memory"; 30 device_type = "memory";
55 }; 31 };
56 32
57 localbus@e0005000 { 33 lbc: localbus@e0005000 {
58 #address-cells = <2>; 34 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>; 35
60 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; 36 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
61 reg = <0xe0005000 0x1000>; 37 0x1 0x0 0x0 0xf8000000 0x00008000
62 interrupts = <19 2>; 38 0x2 0x0 0x0 0xf0000000 0x04000000
63 interrupt-parent = <&mpic>; 39 0x3 0x0 0x0 0xfc000000 0x00008000
64 sleep = <&pmc 0x08000000>; 40 0x4 0x0 0x0 0xf8008000 0x00008000
65 41 0x5 0x0 0x0 0xf8010000 0x00008000>;
66 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000
69 0x3 0x0 0xfc000000 0x00008000
70 0x4 0x0 0xf8008000 0x00008000
71 0x5 0x0 0xf8010000 0x00008000>;
72 42
73 nor@0,0 { 43 nor@0,0 {
74 #address-cells = <1>; 44 #address-cells = <1>;
@@ -133,220 +103,25 @@
133 }; 103 };
134 }; 104 };
135 105
136 soc@e0000000 { 106 soc: soc@e0000000 {
137 #address-cells = <1>; 107 ranges = <0x0 0x0 0xe0000000 0x100000>;
138 #size-cells = <1>;
139 device_type = "soc";
140 compatible = "fsl,mpc8569-immr", "simple-bus";
141 ranges = <0x0 0xe0000000 0x100000>;
142 bus-frequency = <0>;
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <10>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 memory-controller@2000 {
158 compatible = "fsl,mpc8569-memory-controller";
159 reg = <0x2000 0x1000>;
160 interrupt-parent = <&mpic>;
161 interrupts = <18 2>;
162 };
163 108
164 i2c-sleep-nexus { 109 i2c-sleep-nexus {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "simple-bus";
168 sleep = <&pmc 0x00000004>;
169 ranges;
170
171 i2c@3000 { 110 i2c@3000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 cell-index = <0>;
175 compatible = "fsl-i2c";
176 reg = <0x3000 0x100>;
177 interrupts = <43 2>;
178 interrupt-parent = <&mpic>;
179 dfsrr;
180
181 rtc@68 { 111 rtc@68 {
182 compatible = "dallas,ds1374"; 112 compatible = "dallas,ds1374";
183 reg = <0x68>; 113 reg = <0x68>;
184 interrupts = <3 1>; 114 interrupts = <3 1 0 0>;
185 interrupt-parent = <&mpic>;
186 }; 115 };
187 }; 116 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 interrupt-parent = <&mpic>;
197 dfsrr;
198 };
199 };
200
201 duart-sleep-nexus {
202 #address-cells = <1>;
203 #size-cells = <1>;
204 compatible = "simple-bus";
205 sleep = <&pmc 0x00000002>;
206 ranges;
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <0>;
214 interrupts = <42 2>;
215 interrupt-parent = <&mpic>;
216 };
217
218 serial1: serial@4600 {
219 cell-index = <1>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4600 0x100>;
223 clock-frequency = <0>;
224 interrupts = <42 2>;
225 interrupt-parent = <&mpic>;
226 };
227 };
228
229 L2: l2-cache-controller@20000 {
230 compatible = "fsl,mpc8569-l2-cache-controller";
231 reg = <0x20000 0x1000>;
232 cache-line-size = <32>; // 32 bytes
233 cache-size = <0x80000>; // L2, 512K
234 interrupt-parent = <&mpic>;
235 interrupts = <16 2>;
236 }; 117 };
237 118
238 dma@21300 { 119 sdhc@2e000 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
242 reg = <0x21300 0x4>;
243 ranges = <0x0 0x21100 0x200>;
244 cell-index = <0>;
245 dma-channel@0 {
246 compatible = "fsl,mpc8569-dma-channel",
247 "fsl,eloplus-dma-channel";
248 reg = <0x0 0x80>;
249 cell-index = <0>;
250 interrupt-parent = <&mpic>;
251 interrupts = <20 2>;
252 };
253 dma-channel@80 {
254 compatible = "fsl,mpc8569-dma-channel",
255 "fsl,eloplus-dma-channel";
256 reg = <0x80 0x80>;
257 cell-index = <1>;
258 interrupt-parent = <&mpic>;
259 interrupts = <21 2>;
260 };
261 dma-channel@100 {
262 compatible = "fsl,mpc8569-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x100 0x80>;
265 cell-index = <2>;
266 interrupt-parent = <&mpic>;
267 interrupts = <22 2>;
268 };
269 dma-channel@180 {
270 compatible = "fsl,mpc8569-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x180 0x80>;
273 cell-index = <3>;
274 interrupt-parent = <&mpic>;
275 interrupts = <23 2>;
276 };
277 };
278
279 sdhci@2e000 {
280 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
281 reg = <0x2e000 0x1000>;
282 interrupts = <72 0x8>;
283 interrupt-parent = <&mpic>;
284 sleep = <&pmc 0x00200000>;
285 /* Filled in by U-Boot */
286 clock-frequency = <0>;
287 status = "disabled"; 120 status = "disabled";
288 sdhci,1-bit-only; 121 sdhci,1-bit-only;
289 }; 122 };
290 123
291 crypto@30000 {
292 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
293 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
294 reg = <0x30000 0x10000>;
295 interrupts = <45 2 58 2>;
296 interrupt-parent = <&mpic>;
297 fsl,num-channels = <4>;
298 fsl,channel-fifo-len = <24>;
299 fsl,exec-units-mask = <0xbfe>;
300 fsl,descriptor-types-mask = <0x3ab0ebf>;
301 sleep = <&pmc 0x01000000>;
302 };
303
304 mpic: pic@40000 {
305 interrupt-controller;
306 #address-cells = <0>;
307 #interrupt-cells = <2>;
308 reg = <0x40000 0x40000>;
309 compatible = "chrp,open-pic";
310 device_type = "open-pic";
311 };
312
313 msi@41600 {
314 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
315 reg = <0x41600 0x80>;
316 msi-available-ranges = <0 0x100>;
317 interrupts = <
318 0xe0 0
319 0xe1 0
320 0xe2 0
321 0xe3 0
322 0xe4 0
323 0xe5 0
324 0xe6 0
325 0xe7 0>;
326 interrupt-parent = <&mpic>;
327 };
328
329 global-utilities@e0000 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
333 reg = <0xe0000 0x1000>;
334 ranges = <0 0xe0000 0x1000>;
335 fsl,has-rstcr;
336
337 pmc: power@70 {
338 compatible = "fsl,mpc8569-pmc",
339 "fsl,mpc8548-pmc";
340 reg = <0x70 0x20>;
341 };
342 };
343
344 par_io@e0100 { 124 par_io@e0100 {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 reg = <0xe0100 0x100>;
348 ranges = <0x0 0xe0100 0x100>;
349 device_type = "par_io";
350 num-ports = <7>; 125 num-ports = <7>;
351 126
352 qe_pio_e: gpio-controller@80 { 127 qe_pio_e: gpio-controller@80 {
@@ -447,47 +222,11 @@
447 }; 222 };
448 }; 223 };
449 224
450 qe@e0080000 { 225 qe: qe@e0080000 {
451 #address-cells = <1>; 226 ranges = <0x0 0x0 0xe0080000 0x40000>;
452 #size-cells = <1>; 227 reg = <0x0 0xe0080000 0x0 0x480>;
453 device_type = "qe";
454 compatible = "fsl,qe";
455 ranges = <0x0 0xe0080000 0x40000>;
456 reg = <0xe0080000 0x480>;
457 sleep = <&pmc 0x00000800>;
458 brg-frequency = <0>;
459 bus-frequency = <0>;
460 fsl,qe-num-riscs = <4>;
461 fsl,qe-num-snums = <46>;
462
463 qeic: interrupt-controller@80 {
464 interrupt-controller;
465 compatible = "fsl,qe-ic";
466 #address-cells = <0>;
467 #interrupt-cells = <1>;
468 reg = <0x80 0x80>;
469 interrupts = <46 2 46 2>; //high:30 low:30
470 interrupt-parent = <&mpic>;
471 };
472
473 timer@440 {
474 compatible = "fsl,mpc8569-qe-gtm",
475 "fsl,qe-gtm", "fsl,gtm";
476 reg = <0x440 0x40>;
477 interrupts = <12 13 14 15>;
478 interrupt-parent = <&qeic>;
479 /* Filled in by U-Boot */
480 clock-frequency = <0>;
481 };
482 228
483 spi@4c0 { 229 spi@4c0 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
487 reg = <0x4c0 0x40>;
488 cell-index = <0>;
489 interrupts = <2>;
490 interrupt-parent = <&qeic>;
491 gpios = <&qe_pio_e 30 0>; 230 gpios = <&qe_pio_e 30 0>;
492 mode = "cpu-qe"; 231 mode = "cpu-qe";
493 232
@@ -499,20 +238,10 @@
499 }; 238 };
500 239
501 spi@500 { 240 spi@500 {
502 cell-index = <1>;
503 compatible = "fsl,spi";
504 reg = <0x500 0x40>;
505 interrupts = <1>;
506 interrupt-parent = <&qeic>;
507 mode = "cpu"; 241 mode = "cpu";
508 }; 242 };
509 243
510 usb@6c0 { 244 usb@6c0 {
511 compatible = "fsl,mpc8569-qe-usb",
512 "fsl,mpc8323-qe-usb";
513 reg = <0x6c0 0x40 0x8b00 0x100>;
514 interrupts = <11>;
515 interrupt-parent = <&qeic>;
516 fsl,fullspeed-clock = "clk5"; 245 fsl,fullspeed-clock = "clk5";
517 fsl,lowspeed-clock = "brg10"; 246 fsl,lowspeed-clock = "brg10";
518 gpios = <&qe_pio_f 3 0 /* USBOE */ 247 gpios = <&qe_pio_f 3 0 /* USBOE */
@@ -527,10 +256,6 @@
527 enet0: ucc@2000 { 256 enet0: ucc@2000 {
528 device_type = "network"; 257 device_type = "network";
529 compatible = "ucc_geth"; 258 compatible = "ucc_geth";
530 cell-index = <1>;
531 reg = <0x2000 0x200>;
532 interrupts = <32>;
533 interrupt-parent = <&qeic>;
534 local-mac-address = [ 00 00 00 00 00 00 ]; 259 local-mac-address = [ 00 00 00 00 00 00 ];
535 rx-clock-name = "none"; 260 rx-clock-name = "none";
536 tx-clock-name = "clk12"; 261 tx-clock-name = "clk12";
@@ -548,35 +273,33 @@
548 273
549 qe_phy0: ethernet-phy@07 { 274 qe_phy0: ethernet-phy@07 {
550 interrupt-parent = <&mpic>; 275 interrupt-parent = <&mpic>;
551 interrupts = <1 1>; 276 interrupts = <1 1 0 0>;
552 reg = <0x7>; 277 reg = <0x7>;
553 device_type = "ethernet-phy"; 278 device_type = "ethernet-phy";
554 }; 279 };
555 qe_phy1: ethernet-phy@01 { 280 qe_phy1: ethernet-phy@01 {
556 interrupt-parent = <&mpic>; 281 interrupt-parent = <&mpic>;
557 interrupts = <2 1>; 282 interrupts = <2 1 0 0>;
558 reg = <0x1>; 283 reg = <0x1>;
559 device_type = "ethernet-phy"; 284 device_type = "ethernet-phy";
560 }; 285 };
561 qe_phy2: ethernet-phy@02 { 286 qe_phy2: ethernet-phy@02 {
562 interrupt-parent = <&mpic>; 287 interrupt-parent = <&mpic>;
563 interrupts = <3 1>; 288 interrupts = <3 1 0 0>;
564 reg = <0x2>; 289 reg = <0x2>;
565 device_type = "ethernet-phy"; 290 device_type = "ethernet-phy";
566 }; 291 };
567 qe_phy3: ethernet-phy@03 { 292 qe_phy3: ethernet-phy@03 {
568 interrupt-parent = <&mpic>; 293 interrupt-parent = <&mpic>;
569 interrupts = <4 1>; 294 interrupts = <4 1 0 0>;
570 reg = <0x3>; 295 reg = <0x3>;
571 device_type = "ethernet-phy"; 296 device_type = "ethernet-phy";
572 }; 297 };
573 qe_phy5: ethernet-phy@04 { 298 qe_phy5: ethernet-phy@04 {
574 interrupt-parent = <&mpic>;
575 reg = <0x04>; 299 reg = <0x04>;
576 device_type = "ethernet-phy"; 300 device_type = "ethernet-phy";
577 }; 301 };
578 qe_phy7: ethernet-phy@06 { 302 qe_phy7: ethernet-phy@06 {
579 interrupt-parent = <&mpic>;
580 reg = <0x6>; 303 reg = <0x6>;
581 device_type = "ethernet-phy"; 304 device_type = "ethernet-phy";
582 }; 305 };
@@ -610,10 +333,6 @@
610 enet2: ucc@2200 { 333 enet2: ucc@2200 {
611 device_type = "network"; 334 device_type = "network";
612 compatible = "ucc_geth"; 335 compatible = "ucc_geth";
613 cell-index = <3>;
614 reg = <0x2200 0x200>;
615 interrupts = <34>;
616 interrupt-parent = <&qeic>;
617 local-mac-address = [ 00 00 00 00 00 00 ]; 336 local-mac-address = [ 00 00 00 00 00 00 ];
618 rx-clock-name = "none"; 337 rx-clock-name = "none";
619 tx-clock-name = "clk12"; 338 tx-clock-name = "clk12";
@@ -637,10 +356,6 @@
637 enet1: ucc@3000 { 356 enet1: ucc@3000 {
638 device_type = "network"; 357 device_type = "network";
639 compatible = "ucc_geth"; 358 compatible = "ucc_geth";
640 cell-index = <2>;
641 reg = <0x3000 0x200>;
642 interrupts = <33>;
643 interrupt-parent = <&qeic>;
644 local-mac-address = [ 00 00 00 00 00 00 ]; 359 local-mac-address = [ 00 00 00 00 00 00 ];
645 rx-clock-name = "none"; 360 rx-clock-name = "none";
646 tx-clock-name = "clk17"; 361 tx-clock-name = "clk17";
@@ -664,10 +379,6 @@
664 enet3: ucc@3200 { 379 enet3: ucc@3200 {
665 device_type = "network"; 380 device_type = "network";
666 compatible = "ucc_geth"; 381 compatible = "ucc_geth";
667 cell-index = <4>;
668 reg = <0x3200 0x200>;
669 interrupts = <35>;
670 interrupt-parent = <&qeic>;
671 local-mac-address = [ 00 00 00 00 00 00 ]; 382 local-mac-address = [ 00 00 00 00 00 00 ];
672 rx-clock-name = "none"; 383 rx-clock-name = "none";
673 tx-clock-name = "clk17"; 384 tx-clock-name = "clk17";
@@ -691,10 +402,6 @@
691 enet5: ucc@3400 { 402 enet5: ucc@3400 {
692 device_type = "network"; 403 device_type = "network";
693 compatible = "ucc_geth"; 404 compatible = "ucc_geth";
694 cell-index = <6>;
695 reg = <0x3400 0x200>;
696 interrupts = <41>;
697 interrupt-parent = <&qeic>;
698 local-mac-address = [ 00 00 00 00 00 00 ]; 405 local-mac-address = [ 00 00 00 00 00 00 ];
699 rx-clock-name = "none"; 406 rx-clock-name = "none";
700 tx-clock-name = "none"; 407 tx-clock-name = "none";
@@ -706,10 +413,6 @@
706 enet7: ucc@3600 { 413 enet7: ucc@3600 {
707 device_type = "network"; 414 device_type = "network";
708 compatible = "ucc_geth"; 415 compatible = "ucc_geth";
709 cell-index = <8>;
710 reg = <0x3600 0x200>;
711 interrupts = <43>;
712 interrupt-parent = <&qeic>;
713 local-mac-address = [ 00 00 00 00 00 00 ]; 416 local-mac-address = [ 00 00 00 00 00 00 ];
714 rx-clock-name = "none"; 417 rx-clock-name = "none";
715 tx-clock-name = "none"; 418 tx-clock-name = "none";
@@ -717,50 +420,14 @@
717 phy-handle = <&qe_phy7>; 420 phy-handle = <&qe_phy7>;
718 phy-connection-type = "sgmii"; 421 phy-connection-type = "sgmii";
719 }; 422 };
720
721 muram@10000 {
722 #address-cells = <1>;
723 #size-cells = <1>;
724 compatible = "fsl,qe-muram", "fsl,cpm-muram";
725 ranges = <0x0 0x10000 0x20000>;
726
727 data-only@0 {
728 compatible = "fsl,qe-muram-data",
729 "fsl,cpm-muram-data";
730 reg = <0x0 0x20000>;
731 };
732 };
733
734 }; 423 };
735 424
736 /* PCI Express */ 425 /* PCI Express */
737 pci1: pcie@e000a000 { 426 pci1: pcie@e000a000 {
738 compatible = "fsl,mpc8548-pcie"; 427 reg = <0x0 0xe000a000 0x0 0x1000>;
739 device_type = "pci"; 428 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
740 #interrupt-cells = <1>; 429 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xe000a000 0x1000>;
744 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
745 interrupt-map = <
746 /* IDSEL 0x0 (PEX) */
747 00000 0x0 0x0 0x1 &mpic 0x0 0x1
748 00000 0x0 0x0 0x2 &mpic 0x1 0x1
749 00000 0x0 0x0 0x3 &mpic 0x2 0x1
750 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
751
752 interrupt-parent = <&mpic>;
753 interrupts = <26 2>;
754 bus-range = <0 255>;
755 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
756 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
757 sleep = <&pmc 0x20000000>;
758 clock-frequency = <33333333>;
759 pcie@0 { 430 pcie@0 {
760 reg = <0x0 0x0 0x0 0x0 0x0>;
761 #size-cells = <2>;
762 #address-cells = <3>;
763 device_type = "pci";
764 ranges = <0x2000000 0x0 0xa0000000 431 ranges = <0x2000000 0x0 0xa0000000
765 0x2000000 0x0 0xa0000000 432 0x2000000 0x0 0xa0000000
766 0x0 0x10000000 433 0x0 0x10000000
@@ -771,20 +438,15 @@
771 }; 438 };
772 }; 439 };
773 440
774 rio0: rapidio@e00c00000 { 441 rio: rapidio@e00c00000 {
775 #address-cells = <2>; 442 reg = <0x0 0xe00c0000 0x0 0x20000>;
776 #size-cells = <2>; 443 port1 {
777 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta"; 444 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
778 reg = <0xe00c0000 0x20000>; 445 };
779 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; 446 port2 {
780 interrupts = <48 2 /* error */ 447 status = "disabled";
781 49 2 /* bell_outb */ 448 };
782 50 2 /* bell_inb */
783 53 2 /* msg1_tx */
784 54 2 /* msg1_rx */
785 55 2 /* msg2_tx */
786 56 2 /* msg2_rx */>;
787 interrupt-parent = <&mpic>;
788 sleep = <&pmc 0x00080000>;
789 }; 449 };
790}; 450};
451
452/include/ "fsl/mpc8569si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index f6c04d25e91..0c9f2955deb 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -9,67 +9,18 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8572si-pre.dtsi"
13
13/ { 14/ {
14 model = "fsl,MPC8572DS"; 15 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS"; 16 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61 17
62 memory { 18 memory {
63 device_type = "memory"; 19 device_type = "memory";
64 }; 20 };
65 21
66 localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0 0xffe05000 0 0x1000>; 23 reg = <0 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73 24
74 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 25 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
75 0x1 0x0 0x0 0xe0000000 0x08000000 26 0x1 0x0 0x0 0xe0000000 0x08000000
@@ -78,601 +29,17 @@
78 0x4 0x0 0x0 0xffa40000 0x00040000 29 0x4 0x0 0x0 0xffa40000 0x00040000
79 0x5 0x0 0x0 0xffa80000 0x00040000 30 0x5 0x0 0x0 0xffa80000 0x00040000
80 0x6 0x0 0x0 0xffac0000 0x00040000>; 31 0x6 0x0 0x0 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 }; 32 };
178 33
179 soc8572@ffe00000 { 34 board_soc: soc: soc8572@ffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0 0xffe00000 0x100000>; 35 ranges = <0x0 0 0xffe00000 0x100000>;
185 bus-frequency = <0>; // Filled out by uboot.
186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
200 memory-controller@2000 {
201 compatible = "fsl,mpc8572-memory-controller";
202 reg = <0x2000 0x1000>;
203 interrupt-parent = <&mpic>;
204 interrupts = <18 2>;
205 };
206
207 memory-controller@6000 {
208 compatible = "fsl,mpc8572-memory-controller";
209 reg = <0x6000 0x1000>;
210 interrupt-parent = <&mpic>;
211 interrupts = <18 2>;
212 };
213
214 L2: l2-cache-controller@20000 {
215 compatible = "fsl,mpc8572-l2-cache-controller";
216 reg = <0x20000 0x1000>;
217 cache-line-size = <32>; // 32 bytes
218 cache-size = <0x100000>; // L2, 1M
219 interrupt-parent = <&mpic>;
220 interrupts = <16 2>;
221 };
222
223 i2c@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cell-index = <0>;
227 compatible = "fsl-i2c";
228 reg = <0x3000 0x100>;
229 interrupts = <43 2>;
230 interrupt-parent = <&mpic>;
231 dfsrr;
232 };
233
234 i2c@3100 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
239 reg = <0x3100 0x100>;
240 interrupts = <43 2>;
241 interrupt-parent = <&mpic>;
242 dfsrr;
243 };
244
245 dma@c300 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
249 reg = <0xc300 0x4>;
250 ranges = <0x0 0xc100 0x200>;
251 cell-index = <1>;
252 dma-channel@0 {
253 compatible = "fsl,mpc8572-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x0 0x80>;
256 cell-index = <0>;
257 interrupt-parent = <&mpic>;
258 interrupts = <76 2>;
259 };
260 dma-channel@80 {
261 compatible = "fsl,mpc8572-dma-channel",
262 "fsl,eloplus-dma-channel";
263 reg = <0x80 0x80>;
264 cell-index = <1>;
265 interrupt-parent = <&mpic>;
266 interrupts = <77 2>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,mpc8572-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupt-parent = <&mpic>;
274 interrupts = <78 2>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,mpc8572-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupt-parent = <&mpic>;
282 interrupts = <79 2>;
283 };
284 };
285
286 dma@21300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0x21300 0x4>;
291 ranges = <0x0 0x21100 0x200>;
292 cell-index = <0>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <20 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <21 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <22 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <23 2>;
324 };
325 };
326
327 ptp_clock@24E00 {
328 compatible = "fsl,etsec-ptp";
329 reg = <0x24E00 0xB0>;
330 interrupts = <68 2 69 2 70 2 71 2>;
331 interrupt-parent = < &mpic >;
332 fsl,tclk-period = <5>;
333 fsl,tmr-prsc = <200>;
334 fsl,tmr-add = <0xAAAAAAAB>;
335 fsl,tmr-fiper1 = <0x3B9AC9FB>;
336 fsl,tmr-fiper2 = <0x3B9AC9FB>;
337 fsl,max-adj = <499999999>;
338 };
339
340 enet0: ethernet@24000 {
341 #address-cells = <1>;
342 #size-cells = <1>;
343 cell-index = <0>;
344 device_type = "network";
345 model = "eTSEC";
346 compatible = "gianfar";
347 reg = <0x24000 0x1000>;
348 ranges = <0x0 0x24000 0x1000>;
349 local-mac-address = [ 00 00 00 00 00 00 ];
350 interrupts = <29 2 30 2 34 2>;
351 interrupt-parent = <&mpic>;
352 tbi-handle = <&tbi0>;
353 phy-handle = <&phy0>;
354 phy-connection-type = "rgmii-id";
355
356 mdio@520 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,gianfar-mdio";
360 reg = <0x520 0x20>;
361
362 phy0: ethernet-phy@0 {
363 interrupt-parent = <&mpic>;
364 interrupts = <10 1>;
365 reg = <0x0>;
366 };
367 phy1: ethernet-phy@1 {
368 interrupt-parent = <&mpic>;
369 interrupts = <10 1>;
370 reg = <0x1>;
371 };
372 phy2: ethernet-phy@2 {
373 interrupt-parent = <&mpic>;
374 interrupts = <10 1>;
375 reg = <0x2>;
376 };
377 phy3: ethernet-phy@3 {
378 interrupt-parent = <&mpic>;
379 interrupts = <10 1>;
380 reg = <0x3>;
381 };
382
383 tbi0: tbi-phy@11 {
384 reg = <0x11>;
385 device_type = "tbi-phy";
386 };
387 };
388 };
389
390 enet1: ethernet@25000 {
391 #address-cells = <1>;
392 #size-cells = <1>;
393 cell-index = <1>;
394 device_type = "network";
395 model = "eTSEC";
396 compatible = "gianfar";
397 reg = <0x25000 0x1000>;
398 ranges = <0x0 0x25000 0x1000>;
399 local-mac-address = [ 00 00 00 00 00 00 ];
400 interrupts = <35 2 36 2 40 2>;
401 interrupt-parent = <&mpic>;
402 tbi-handle = <&tbi1>;
403 phy-handle = <&phy1>;
404 phy-connection-type = "rgmii-id";
405
406 mdio@520 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "fsl,gianfar-tbi";
410 reg = <0x520 0x20>;
411
412 tbi1: tbi-phy@11 {
413 reg = <0x11>;
414 device_type = "tbi-phy";
415 };
416 };
417 };
418
419 enet2: ethernet@26000 {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 cell-index = <2>;
423 device_type = "network";
424 model = "eTSEC";
425 compatible = "gianfar";
426 reg = <0x26000 0x1000>;
427 ranges = <0x0 0x26000 0x1000>;
428 local-mac-address = [ 00 00 00 00 00 00 ];
429 interrupts = <31 2 32 2 33 2>;
430 interrupt-parent = <&mpic>;
431 tbi-handle = <&tbi2>;
432 phy-handle = <&phy2>;
433 phy-connection-type = "rgmii-id";
434
435 mdio@520 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "fsl,gianfar-tbi";
439 reg = <0x520 0x20>;
440
441 tbi2: tbi-phy@11 {
442 reg = <0x11>;
443 device_type = "tbi-phy";
444 };
445 };
446 };
447
448 enet3: ethernet@27000 {
449 #address-cells = <1>;
450 #size-cells = <1>;
451 cell-index = <3>;
452 device_type = "network";
453 model = "eTSEC";
454 compatible = "gianfar";
455 reg = <0x27000 0x1000>;
456 ranges = <0x0 0x27000 0x1000>;
457 local-mac-address = [ 00 00 00 00 00 00 ];
458 interrupts = <37 2 38 2 39 2>;
459 interrupt-parent = <&mpic>;
460 tbi-handle = <&tbi3>;
461 phy-handle = <&phy3>;
462 phy-connection-type = "rgmii-id";
463
464 mdio@520 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 compatible = "fsl,gianfar-tbi";
468 reg = <0x520 0x20>;
469
470 tbi3: tbi-phy@11 {
471 reg = <0x11>;
472 device_type = "tbi-phy";
473 };
474 };
475 };
476
477 serial0: serial@4500 {
478 cell-index = <0>;
479 device_type = "serial";
480 compatible = "ns16550";
481 reg = <0x4500 0x100>;
482 clock-frequency = <0>;
483 interrupts = <42 2>;
484 interrupt-parent = <&mpic>;
485 };
486
487 serial1: serial@4600 {
488 cell-index = <1>;
489 device_type = "serial";
490 compatible = "ns16550";
491 reg = <0x4600 0x100>;
492 clock-frequency = <0>;
493 interrupts = <42 2>;
494 interrupt-parent = <&mpic>;
495 };
496
497 global-utilities@e0000 { //global utilities block
498 compatible = "fsl,mpc8572-guts";
499 reg = <0xe0000 0x1000>;
500 fsl,has-rstcr;
501 };
502
503 msi@41600 {
504 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
505 reg = <0x41600 0x80>;
506 msi-available-ranges = <0 0x100>;
507 interrupts = <
508 0xe0 0
509 0xe1 0
510 0xe2 0
511 0xe3 0
512 0xe4 0
513 0xe5 0
514 0xe6 0
515 0xe7 0>;
516 interrupt-parent = <&mpic>;
517 };
518
519 crypto@30000 {
520 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
521 "fsl,sec2.1", "fsl,sec2.0";
522 reg = <0x30000 0x10000>;
523 interrupts = <45 2 58 2>;
524 interrupt-parent = <&mpic>;
525 fsl,num-channels = <4>;
526 fsl,channel-fifo-len = <24>;
527 fsl,exec-units-mask = <0x9fe>;
528 fsl,descriptor-types-mask = <0x3ab0ebf>;
529 };
530
531 mpic: pic@40000 {
532 interrupt-controller;
533 #address-cells = <0>;
534 #interrupt-cells = <2>;
535 reg = <0x40000 0x40000>;
536 compatible = "chrp,open-pic";
537 device_type = "open-pic";
538 };
539 }; 36 };
540 37
541 pci0: pcie@ffe08000 { 38 board_pci0: pci0: pcie@ffe08000 {
542 compatible = "fsl,mpc8548-pcie";
543 device_type = "pci";
544 #interrupt-cells = <1>;
545 #size-cells = <2>;
546 #address-cells = <3>;
547 reg = <0 0xffe08000 0 0x1000>; 39 reg = <0 0xffe08000 0 0x1000>;
548 bus-range = <0 255>;
549 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 40 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
550 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; 41 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
551 clock-frequency = <33333333>;
552 interrupt-parent = <&mpic>;
553 interrupts = <24 2>;
554 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
555 interrupt-map = <
556 /* IDSEL 0x11 func 0 - PCI slot 1 */
557 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
558 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
559 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
560 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
561
562 /* IDSEL 0x11 func 1 - PCI slot 1 */
563 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
564 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
565 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
566 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
567
568 /* IDSEL 0x11 func 2 - PCI slot 1 */
569 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
570 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
571 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
572 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
573
574 /* IDSEL 0x11 func 3 - PCI slot 1 */
575 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
576 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
577 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
578 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
579
580 /* IDSEL 0x11 func 4 - PCI slot 1 */
581 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
582 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
583 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
584 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
585
586 /* IDSEL 0x11 func 5 - PCI slot 1 */
587 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
588 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
589 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
590 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
591
592 /* IDSEL 0x11 func 6 - PCI slot 1 */
593 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
594 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
595 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
596 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
597
598 /* IDSEL 0x11 func 7 - PCI slot 1 */
599 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
600 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
601 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
602 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
603
604 /* IDSEL 0x12 func 0 - PCI slot 2 */
605 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
606 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
607 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
608 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
609
610 /* IDSEL 0x12 func 1 - PCI slot 2 */
611 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
612 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
613 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
614 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
615
616 /* IDSEL 0x12 func 2 - PCI slot 2 */
617 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
618 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
619 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
620 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
621
622 /* IDSEL 0x12 func 3 - PCI slot 2 */
623 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
624 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
625 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
626 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
627
628 /* IDSEL 0x12 func 4 - PCI slot 2 */
629 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
630 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
631 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
632 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
633
634 /* IDSEL 0x12 func 5 - PCI slot 2 */
635 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
636 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
637 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
638 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
639
640 /* IDSEL 0x12 func 6 - PCI slot 2 */
641 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
642 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
643 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
644 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
645
646 /* IDSEL 0x12 func 7 - PCI slot 2 */
647 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
648 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
649 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
650 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
651
652 // IDSEL 0x1c USB
653 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
654 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
655 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
656 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
657
658 // IDSEL 0x1d Audio
659 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
660
661 // IDSEL 0x1e Legacy
662 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
663 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
664
665 // IDSEL 0x1f IDE/SATA
666 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
667 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
668
669 >;
670
671 pcie@0 { 42 pcie@0 {
672 reg = <0x0 0x0 0x0 0x0 0x0>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 device_type = "pci";
676 ranges = <0x2000000 0x0 0x80000000 43 ranges = <0x2000000 0x0 0x80000000
677 0x2000000 0x0 0x80000000 44 0x2000000 0x0 0x80000000
678 0x0 0x20000000 45 0x0 0x20000000
@@ -680,99 +47,14 @@
680 0x1000000 0x0 0x0 47 0x1000000 0x0 0x0
681 0x1000000 0x0 0x0 48 0x1000000 0x0 0x0
682 0x0 0x10000>; 49 0x0 0x10000>;
683 uli1575@0 {
684 reg = <0x0 0x0 0x0 0x0 0x0>;
685 #size-cells = <2>;
686 #address-cells = <3>;
687 ranges = <0x2000000 0x0 0x80000000
688 0x2000000 0x0 0x80000000
689 0x0 0x20000000
690
691 0x1000000 0x0 0x0
692 0x1000000 0x0 0x0
693 0x0 0x10000>;
694 isa@1e {
695 device_type = "isa";
696 #interrupt-cells = <2>;
697 #size-cells = <1>;
698 #address-cells = <2>;
699 reg = <0xf000 0x0 0x0 0x0 0x0>;
700 ranges = <0x1 0x0 0x1000000 0x0 0x0
701 0x1000>;
702 interrupt-parent = <&i8259>;
703
704 i8259: interrupt-controller@20 {
705 reg = <0x1 0x20 0x2
706 0x1 0xa0 0x2
707 0x1 0x4d0 0x2>;
708 interrupt-controller;
709 device_type = "interrupt-controller";
710 #address-cells = <0>;
711 #interrupt-cells = <2>;
712 compatible = "chrp,iic";
713 interrupts = <9 2>;
714 interrupt-parent = <&mpic>;
715 };
716
717 i8042@60 {
718 #size-cells = <0>;
719 #address-cells = <1>;
720 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
721 interrupts = <1 3 12 3>;
722 interrupt-parent =
723 <&i8259>;
724
725 keyboard@0 {
726 reg = <0x0>;
727 compatible = "pnpPNP,303";
728 };
729
730 mouse@1 {
731 reg = <0x1>;
732 compatible = "pnpPNP,f03";
733 };
734 };
735
736 rtc@70 {
737 compatible = "pnpPNP,b00";
738 reg = <0x1 0x70 0x2>;
739 };
740
741 gpio@400 {
742 reg = <0x1 0x400 0x80>;
743 };
744 };
745 };
746 }; 50 };
747
748 }; 51 };
749 52
750 pci1: pcie@ffe09000 { 53 pci1: pcie@ffe09000 {
751 compatible = "fsl,mpc8548-pcie";
752 device_type = "pci";
753 #interrupt-cells = <1>;
754 #size-cells = <2>;
755 #address-cells = <3>;
756 reg = <0 0xffe09000 0 0x1000>; 54 reg = <0 0xffe09000 0 0x1000>;
757 bus-range = <0 255>;
758 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 55 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
759 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; 56 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
760 clock-frequency = <33333333>;
761 interrupt-parent = <&mpic>;
762 interrupts = <25 2>;
763 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
764 interrupt-map = <
765 /* IDSEL 0x0 */
766 0000 0x0 0x0 0x1 &mpic 0x4 0x1
767 0000 0x0 0x0 0x2 &mpic 0x5 0x1
768 0000 0x0 0x0 0x3 &mpic 0x6 0x1
769 0000 0x0 0x0 0x4 &mpic 0x7 0x1
770 >;
771 pcie@0 { 57 pcie@0 {
772 reg = <0x0 0x0 0x0 0x0 0x0>;
773 #size-cells = <2>;
774 #address-cells = <3>;
775 device_type = "pci";
776 ranges = <0x2000000 0x0 0xa0000000 58 ranges = <0x2000000 0x0 0xa0000000
777 0x2000000 0x0 0xa0000000 59 0x2000000 0x0 0xa0000000
778 0x0 0x20000000 60 0x0 0x20000000
@@ -784,31 +66,10 @@
784 }; 66 };
785 67
786 pci2: pcie@ffe0a000 { 68 pci2: pcie@ffe0a000 {
787 compatible = "fsl,mpc8548-pcie";
788 device_type = "pci";
789 #interrupt-cells = <1>;
790 #size-cells = <2>;
791 #address-cells = <3>;
792 reg = <0 0xffe0a000 0 0x1000>; 69 reg = <0 0xffe0a000 0 0x1000>;
793 bus-range = <0 255>;
794 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 70 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
795 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; 71 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
796 clock-frequency = <33333333>;
797 interrupt-parent = <&mpic>;
798 interrupts = <26 2>;
799 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
800 interrupt-map = <
801 /* IDSEL 0x0 */
802 0000 0x0 0x0 0x1 &mpic 0x0 0x1
803 0000 0x0 0x0 0x2 &mpic 0x1 0x1
804 0000 0x0 0x0 0x3 &mpic 0x2 0x1
805 0000 0x0 0x0 0x4 &mpic 0x3 0x1
806 >;
807 pcie@0 { 72 pcie@0 {
808 reg = <0x0 0x0 0x0 0x0 0x0>;
809 #size-cells = <2>;
810 #address-cells = <3>;
811 device_type = "pci";
812 ranges = <0x2000000 0x0 0xc0000000 73 ranges = <0x2000000 0x0 0xc0000000
813 0x2000000 0x0 0xc0000000 74 0x2000000 0x0 0xc0000000
814 0x0 0x20000000 75 0x0 0x20000000
@@ -819,3 +80,11 @@
819 }; 80 };
820 }; 81 };
821}; 82};
83
84/*
85 * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
86 * for interrupt-map & interrupt-map-mask
87 */
88
89/include/ "fsl/mpc8572si-post.dtsi"
90/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
new file mode 100644
index 00000000000..c3d4fac0532
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -0,0 +1,397 @@
1/*
2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
46 read-only;
47 };
48
49 diagnostic@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 read-only;
52 };
53
54 dink@3e00000 {
55 reg = <0x03e00000 0x00200000>;
56 read-only;
57 };
58
59 kernel@4000000 {
60 reg = <0x04000000 0x00400000>;
61 read-only;
62 };
63
64 jffs2@4400000 {
65 reg = <0x04400000 0x03b00000>;
66 };
67
68 dtb@7f00000 {
69 reg = <0x07f00000 0x00080000>;
70 read-only;
71 };
72
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
76 };
77 };
78
79 nand@2,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,mpc8572-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <0x2 0x0 0x40000>;
85
86 u-boot@0 {
87 reg = <0x0 0x02000000>;
88 read-only;
89 };
90
91 jffs2@2000000 {
92 reg = <0x02000000 0x10000000>;
93 };
94
95 ramdisk@12000000 {
96 reg = <0x12000000 0x08000000>;
97 read-only;
98 };
99
100 kernel@1a000000 {
101 reg = <0x1a000000 0x04000000>;
102 };
103
104 dtb@1e000000 {
105 reg = <0x1e000000 0x01000000>;
106 read-only;
107 };
108
109 empty@1f000000 {
110 reg = <0x1f000000 0x21000000>;
111 };
112 };
113
114 nand@4,0 {
115 compatible = "fsl,mpc8572-fcm-nand",
116 "fsl,elbc-fcm-nand";
117 reg = <0x4 0x0 0x40000>;
118 };
119
120 nand@5,0 {
121 compatible = "fsl,mpc8572-fcm-nand",
122 "fsl,elbc-fcm-nand";
123 reg = <0x5 0x0 0x40000>;
124 };
125
126 nand@6,0 {
127 compatible = "fsl,mpc8572-fcm-nand",
128 "fsl,elbc-fcm-nand";
129 reg = <0x6 0x0 0x40000>;
130 };
131};
132
133&board_soc {
134 enet0: ethernet@24000 {
135 tbi-handle = <&tbi0>;
136 phy-handle = <&phy0>;
137 phy-connection-type = "rgmii-id";
138 };
139
140 mdio@24520 {
141 phy0: ethernet-phy@0 {
142 interrupts = <10 1 0 0>;
143 reg = <0x0>;
144 };
145 phy1: ethernet-phy@1 {
146 interrupts = <10 1 0 0>;
147 reg = <0x1>;
148 };
149 phy2: ethernet-phy@2 {
150 interrupts = <10 1 0 0>;
151 reg = <0x2>;
152 };
153 phy3: ethernet-phy@3 {
154 interrupts = <10 1 0 0>;
155 reg = <0x3>;
156 };
157
158 tbi0: tbi-phy@11 {
159 reg = <0x11>;
160 device_type = "tbi-phy";
161 };
162 };
163
164 ptp_clock@24e00 {
165 fsl,tclk-period = <5>;
166 fsl,tmr-prsc = <200>;
167 fsl,tmr-add = <0xAAAAAAAB>;
168 fsl,tmr-fiper1 = <0x3B9AC9FB>;
169 fsl,tmr-fiper2 = <0x3B9AC9FB>;
170 fsl,max-adj = <499999999>;
171 };
172
173 enet1: ethernet@25000 {
174 tbi-handle = <&tbi1>;
175 phy-handle = <&phy1>;
176 phy-connection-type = "rgmii-id";
177
178 };
179
180 mdio@25520 {
181 tbi1: tbi-phy@11 {
182 reg = <0x11>;
183 device_type = "tbi-phy";
184 };
185 };
186
187 enet2: ethernet@26000 {
188 tbi-handle = <&tbi2>;
189 phy-handle = <&phy2>;
190 phy-connection-type = "rgmii-id";
191
192 };
193 mdio@26520 {
194 tbi2: tbi-phy@11 {
195 reg = <0x11>;
196 device_type = "tbi-phy";
197 };
198 };
199
200 enet3: ethernet@27000 {
201 tbi-handle = <&tbi3>;
202 phy-handle = <&phy3>;
203 phy-connection-type = "rgmii-id";
204 };
205
206 mdio@27520 {
207 tbi3: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
210 };
211 };
212};
213
214&board_pci0 {
215 pcie@0 {
216 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
217 interrupt-map = <
218 /* IDSEL 0x11 func 0 - PCI slot 1 */
219 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
220 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
221 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
222 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
223
224 /* IDSEL 0x11 func 1 - PCI slot 1 */
225 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
226 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
227 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
228 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
229
230 /* IDSEL 0x11 func 2 - PCI slot 1 */
231 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
232 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
233 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
234 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
235
236 /* IDSEL 0x11 func 3 - PCI slot 1 */
237 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
238 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
239 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
240 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
241
242 /* IDSEL 0x11 func 4 - PCI slot 1 */
243 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
244 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
245 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
246 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
247
248 /* IDSEL 0x11 func 5 - PCI slot 1 */
249 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
250 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
251 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
252 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
253
254 /* IDSEL 0x11 func 6 - PCI slot 1 */
255 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
256 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
257 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
258 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
259
260 /* IDSEL 0x11 func 7 - PCI slot 1 */
261 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
262 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
263 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
264 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
265
266 /* IDSEL 0x12 func 0 - PCI slot 2 */
267 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
268 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
269 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
270 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
271
272 /* IDSEL 0x12 func 1 - PCI slot 2 */
273 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
274 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
275 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
276 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
277
278 /* IDSEL 0x12 func 2 - PCI slot 2 */
279 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
280 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
281 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
282 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
283
284 /* IDSEL 0x12 func 3 - PCI slot 2 */
285 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
286 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
287 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
288 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
289
290 /* IDSEL 0x12 func 4 - PCI slot 2 */
291 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
292 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
293 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
294 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
295
296 /* IDSEL 0x12 func 5 - PCI slot 2 */
297 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
298 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
299 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
300 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
301
302 /* IDSEL 0x12 func 6 - PCI slot 2 */
303 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
304 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
305 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
306 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
307
308 /* IDSEL 0x12 func 7 - PCI slot 2 */
309 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
310 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
311 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
312 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
313
314 // IDSEL 0x1c USB
315 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
316 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
317 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
318 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
319
320 // IDSEL 0x1d Audio
321 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
322
323 // IDSEL 0x1e Legacy
324 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
325 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
326
327 // IDSEL 0x1f IDE/SATA
328 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
329 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
330 >;
331
332
333 uli1575@0 {
334 reg = <0x0 0x0 0x0 0x0 0x0>;
335 #size-cells = <2>;
336 #address-cells = <3>;
337 ranges = <0x2000000 0x0 0x80000000
338 0x2000000 0x0 0x80000000
339 0x0 0x20000000
340
341 0x1000000 0x0 0x0
342 0x1000000 0x0 0x0
343 0x0 0x10000>;
344 isa@1e {
345 device_type = "isa";
346 #interrupt-cells = <2>;
347 #size-cells = <1>;
348 #address-cells = <2>;
349 reg = <0xf000 0x0 0x0 0x0 0x0>;
350 ranges = <0x1 0x0 0x1000000 0x0 0x0
351 0x1000>;
352 interrupt-parent = <&i8259>;
353
354 i8259: interrupt-controller@20 {
355 reg = <0x1 0x20 0x2
356 0x1 0xa0 0x2
357 0x1 0x4d0 0x2>;
358 interrupt-controller;
359 device_type = "interrupt-controller";
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
362 compatible = "chrp,iic";
363 interrupts = <9 2 0 0>;
364 interrupt-parent = <&mpic>;
365 };
366
367 i8042@60 {
368 #size-cells = <0>;
369 #address-cells = <1>;
370 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
371 interrupts = <1 3 12 3>;
372 interrupt-parent =
373 <&i8259>;
374
375 keyboard@0 {
376 reg = <0x0>;
377 compatible = "pnpPNP,303";
378 };
379
380 mouse@1 {
381 reg = <0x1>;
382 compatible = "pnpPNP,f03";
383 };
384 };
385
386 rtc@70 {
387 compatible = "pnpPNP,b00";
388 reg = <0x1 0x70 0x2>;
389 };
390
391 gpio@400 {
392 reg = <0x1 0x400 0x80>;
393 };
394 };
395 };
396 };
397};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
index f6365db3b97..6c3d0b305e1 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc. 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * 5 *
@@ -9,67 +9,18 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8572si-pre.dtsi"
13
13/ { 14/ {
14 model = "fsl,MPC8572DS"; 15 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS"; 16 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61 17
62 memory { 18 memory {
63 device_type = "memory"; 19 device_type = "memory";
64 }; 20 };
65 21
66 localbus@fffe05000 { 22 board_lbc: lbc: localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>; 23 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73 24
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 25 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000 26 0x1 0x0 0xf 0xe0000000 0x08000000
@@ -78,588 +29,17 @@
78 0x4 0x0 0xf 0xffa40000 0x00040000 29 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000 30 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>; 31 0x6 0x0 0xf 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 }; 32 };
178 33
179 soc8572@fffe00000 { 34 board_soc: soc: soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>; 35 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 bus-frequency = <0>; // Filled out by uboot.
186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
200 memory-controller@2000 {
201 compatible = "fsl,mpc8572-memory-controller";
202 reg = <0x2000 0x1000>;
203 interrupt-parent = <&mpic>;
204 interrupts = <18 2>;
205 };
206
207 memory-controller@6000 {
208 compatible = "fsl,mpc8572-memory-controller";
209 reg = <0x6000 0x1000>;
210 interrupt-parent = <&mpic>;
211 interrupts = <18 2>;
212 };
213
214 L2: l2-cache-controller@20000 {
215 compatible = "fsl,mpc8572-l2-cache-controller";
216 reg = <0x20000 0x1000>;
217 cache-line-size = <32>; // 32 bytes
218 cache-size = <0x100000>; // L2, 1M
219 interrupt-parent = <&mpic>;
220 interrupts = <16 2>;
221 };
222
223 i2c@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cell-index = <0>;
227 compatible = "fsl-i2c";
228 reg = <0x3000 0x100>;
229 interrupts = <43 2>;
230 interrupt-parent = <&mpic>;
231 dfsrr;
232 };
233
234 i2c@3100 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
239 reg = <0x3100 0x100>;
240 interrupts = <43 2>;
241 interrupt-parent = <&mpic>;
242 dfsrr;
243 };
244
245 dma@c300 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
249 reg = <0xc300 0x4>;
250 ranges = <0x0 0xc100 0x200>;
251 cell-index = <1>;
252 dma-channel@0 {
253 compatible = "fsl,mpc8572-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x0 0x80>;
256 cell-index = <0>;
257 interrupt-parent = <&mpic>;
258 interrupts = <76 2>;
259 };
260 dma-channel@80 {
261 compatible = "fsl,mpc8572-dma-channel",
262 "fsl,eloplus-dma-channel";
263 reg = <0x80 0x80>;
264 cell-index = <1>;
265 interrupt-parent = <&mpic>;
266 interrupts = <77 2>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,mpc8572-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupt-parent = <&mpic>;
274 interrupts = <78 2>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,mpc8572-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupt-parent = <&mpic>;
282 interrupts = <79 2>;
283 };
284 };
285
286 dma@21300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0x21300 0x4>;
291 ranges = <0x0 0x21100 0x200>;
292 cell-index = <0>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <20 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <21 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <22 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <23 2>;
324 };
325 };
326
327 enet0: ethernet@24000 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 cell-index = <0>;
331 device_type = "network";
332 model = "eTSEC";
333 compatible = "gianfar";
334 reg = <0x24000 0x1000>;
335 ranges = <0x0 0x24000 0x1000>;
336 local-mac-address = [ 00 00 00 00 00 00 ];
337 interrupts = <29 2 30 2 34 2>;
338 interrupt-parent = <&mpic>;
339 tbi-handle = <&tbi0>;
340 phy-handle = <&phy0>;
341 phy-connection-type = "rgmii-id";
342
343 mdio@520 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,gianfar-mdio";
347 reg = <0x520 0x20>;
348
349 phy0: ethernet-phy@0 {
350 interrupt-parent = <&mpic>;
351 interrupts = <10 1>;
352 reg = <0x0>;
353 };
354 phy1: ethernet-phy@1 {
355 interrupt-parent = <&mpic>;
356 interrupts = <10 1>;
357 reg = <0x1>;
358 };
359 phy2: ethernet-phy@2 {
360 interrupt-parent = <&mpic>;
361 interrupts = <10 1>;
362 reg = <0x2>;
363 };
364 phy3: ethernet-phy@3 {
365 interrupt-parent = <&mpic>;
366 interrupts = <10 1>;
367 reg = <0x3>;
368 };
369
370 tbi0: tbi-phy@11 {
371 reg = <0x11>;
372 device_type = "tbi-phy";
373 };
374 };
375 };
376
377 enet1: ethernet@25000 {
378 #address-cells = <1>;
379 #size-cells = <1>;
380 cell-index = <1>;
381 device_type = "network";
382 model = "eTSEC";
383 compatible = "gianfar";
384 reg = <0x25000 0x1000>;
385 ranges = <0x0 0x25000 0x1000>;
386 local-mac-address = [ 00 00 00 00 00 00 ];
387 interrupts = <35 2 36 2 40 2>;
388 interrupt-parent = <&mpic>;
389 tbi-handle = <&tbi1>;
390 phy-handle = <&phy1>;
391 phy-connection-type = "rgmii-id";
392
393 mdio@520 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "fsl,gianfar-tbi";
397 reg = <0x520 0x20>;
398
399 tbi1: tbi-phy@11 {
400 reg = <0x11>;
401 device_type = "tbi-phy";
402 };
403 };
404 };
405
406 enet2: ethernet@26000 {
407 #address-cells = <1>;
408 #size-cells = <1>;
409 cell-index = <2>;
410 device_type = "network";
411 model = "eTSEC";
412 compatible = "gianfar";
413 reg = <0x26000 0x1000>;
414 ranges = <0x0 0x26000 0x1000>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 interrupts = <31 2 32 2 33 2>;
417 interrupt-parent = <&mpic>;
418 tbi-handle = <&tbi2>;
419 phy-handle = <&phy2>;
420 phy-connection-type = "rgmii-id";
421
422 mdio@520 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,gianfar-tbi";
426 reg = <0x520 0x20>;
427
428 tbi2: tbi-phy@11 {
429 reg = <0x11>;
430 device_type = "tbi-phy";
431 };
432 };
433 };
434
435 enet3: ethernet@27000 {
436 #address-cells = <1>;
437 #size-cells = <1>;
438 cell-index = <3>;
439 device_type = "network";
440 model = "eTSEC";
441 compatible = "gianfar";
442 reg = <0x27000 0x1000>;
443 ranges = <0x0 0x27000 0x1000>;
444 local-mac-address = [ 00 00 00 00 00 00 ];
445 interrupts = <37 2 38 2 39 2>;
446 interrupt-parent = <&mpic>;
447 tbi-handle = <&tbi3>;
448 phy-handle = <&phy3>;
449 phy-connection-type = "rgmii-id";
450
451 mdio@520 {
452 #address-cells = <1>;
453 #size-cells = <0>;
454 compatible = "fsl,gianfar-tbi";
455 reg = <0x520 0x20>;
456
457 tbi3: tbi-phy@11 {
458 reg = <0x11>;
459 device_type = "tbi-phy";
460 };
461 };
462 };
463
464 serial0: serial@4500 {
465 cell-index = <0>;
466 device_type = "serial";
467 compatible = "ns16550";
468 reg = <0x4500 0x100>;
469 clock-frequency = <0>;
470 interrupts = <42 2>;
471 interrupt-parent = <&mpic>;
472 };
473
474 serial1: serial@4600 {
475 cell-index = <1>;
476 device_type = "serial";
477 compatible = "ns16550";
478 reg = <0x4600 0x100>;
479 clock-frequency = <0>;
480 interrupts = <42 2>;
481 interrupt-parent = <&mpic>;
482 };
483
484 global-utilities@e0000 { //global utilities block
485 compatible = "fsl,mpc8572-guts";
486 reg = <0xe0000 0x1000>;
487 fsl,has-rstcr;
488 };
489
490 msi@41600 {
491 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
492 reg = <0x41600 0x80>;
493 msi-available-ranges = <0 0x100>;
494 interrupts = <
495 0xe0 0
496 0xe1 0
497 0xe2 0
498 0xe3 0
499 0xe4 0
500 0xe5 0
501 0xe6 0
502 0xe7 0>;
503 interrupt-parent = <&mpic>;
504 };
505
506 crypto@30000 {
507 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
508 "fsl,sec2.1", "fsl,sec2.0";
509 reg = <0x30000 0x10000>;
510 interrupts = <45 2 58 2>;
511 interrupt-parent = <&mpic>;
512 fsl,num-channels = <4>;
513 fsl,channel-fifo-len = <24>;
514 fsl,exec-units-mask = <0x9fe>;
515 fsl,descriptor-types-mask = <0x3ab0ebf>;
516 };
517
518 mpic: pic@40000 {
519 interrupt-controller;
520 #address-cells = <0>;
521 #interrupt-cells = <2>;
522 reg = <0x40000 0x40000>;
523 compatible = "chrp,open-pic";
524 device_type = "open-pic";
525 };
526 }; 36 };
527 37
528 pci0: pcie@fffe08000 { 38 board_pci0: pci0: pcie@fffe08000 {
529 compatible = "fsl,mpc8548-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xffe08000 0 0x1000>; 39 reg = <0xf 0xffe08000 0 0x1000>;
535 bus-range = <0 255>;
536 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; 41 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
538 clock-frequency = <33333333>;
539 interrupt-parent = <&mpic>;
540 interrupts = <24 2>;
541 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
542 interrupt-map = <
543 /* IDSEL 0x11 func 0 - PCI slot 1 */
544 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
545 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
546 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
547 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
548
549 /* IDSEL 0x11 func 1 - PCI slot 1 */
550 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
551 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
552 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
553 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
554
555 /* IDSEL 0x11 func 2 - PCI slot 1 */
556 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
557 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
558 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
559 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
560
561 /* IDSEL 0x11 func 3 - PCI slot 1 */
562 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
563 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
564 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
565 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
566
567 /* IDSEL 0x11 func 4 - PCI slot 1 */
568 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
569 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
570 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
571 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
572
573 /* IDSEL 0x11 func 5 - PCI slot 1 */
574 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
575 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
576 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
577 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
578
579 /* IDSEL 0x11 func 6 - PCI slot 1 */
580 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
581 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
582 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
583 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
584
585 /* IDSEL 0x11 func 7 - PCI slot 1 */
586 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
587 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
588 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
589 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
590
591 /* IDSEL 0x12 func 0 - PCI slot 2 */
592 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
593 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
594 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
595 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
596
597 /* IDSEL 0x12 func 1 - PCI slot 2 */
598 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
599 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
600 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
601 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
602
603 /* IDSEL 0x12 func 2 - PCI slot 2 */
604 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
605 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
606 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
607 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
608
609 /* IDSEL 0x12 func 3 - PCI slot 2 */
610 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
611 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
612 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
613 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
614
615 /* IDSEL 0x12 func 4 - PCI slot 2 */
616 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
617 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
618 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
619 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
620
621 /* IDSEL 0x12 func 5 - PCI slot 2 */
622 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
623 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
624 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
625 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
626
627 /* IDSEL 0x12 func 6 - PCI slot 2 */
628 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
629 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
630 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
631 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
632
633 /* IDSEL 0x12 func 7 - PCI slot 2 */
634 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
635 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
636 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
637 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
638
639 // IDSEL 0x1c USB
640 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
641 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
642 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
643 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
644
645 // IDSEL 0x1d Audio
646 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
647
648 // IDSEL 0x1e Legacy
649 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
650 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
651
652 // IDSEL 0x1f IDE/SATA
653 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
654 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
655
656 >;
657
658 pcie@0 { 42 pcie@0 {
659 reg = <0x0 0x0 0x0 0x0 0x0>;
660 #size-cells = <2>;
661 #address-cells = <3>;
662 device_type = "pci";
663 ranges = <0x2000000 0x0 0xe0000000 43 ranges = <0x2000000 0x0 0xe0000000
664 0x2000000 0x0 0xe0000000 44 0x2000000 0x0 0xe0000000
665 0x0 0x20000000 45 0x0 0x20000000
@@ -667,99 +47,14 @@
667 0x1000000 0x0 0x0 47 0x1000000 0x0 0x0
668 0x1000000 0x0 0x0 48 0x1000000 0x0 0x0
669 0x0 0x10000>; 49 0x0 0x10000>;
670 uli1575@0 {
671 reg = <0x0 0x0 0x0 0x0 0x0>;
672 #size-cells = <2>;
673 #address-cells = <3>;
674 ranges = <0x2000000 0x0 0xe0000000
675 0x2000000 0x0 0xe0000000
676 0x0 0x20000000
677
678 0x1000000 0x0 0x0
679 0x1000000 0x0 0x0
680 0x0 0x10000>;
681 isa@1e {
682 device_type = "isa";
683 #interrupt-cells = <2>;
684 #size-cells = <1>;
685 #address-cells = <2>;
686 reg = <0xf000 0x0 0x0 0x0 0x0>;
687 ranges = <0x1 0x0 0x1000000 0x0 0x0
688 0x1000>;
689 interrupt-parent = <&i8259>;
690
691 i8259: interrupt-controller@20 {
692 reg = <0x1 0x20 0x2
693 0x1 0xa0 0x2
694 0x1 0x4d0 0x2>;
695 interrupt-controller;
696 device_type = "interrupt-controller";
697 #address-cells = <0>;
698 #interrupt-cells = <2>;
699 compatible = "chrp,iic";
700 interrupts = <9 2>;
701 interrupt-parent = <&mpic>;
702 };
703
704 i8042@60 {
705 #size-cells = <0>;
706 #address-cells = <1>;
707 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
708 interrupts = <1 3 12 3>;
709 interrupt-parent =
710 <&i8259>;
711
712 keyboard@0 {
713 reg = <0x0>;
714 compatible = "pnpPNP,303";
715 };
716
717 mouse@1 {
718 reg = <0x1>;
719 compatible = "pnpPNP,f03";
720 };
721 };
722
723 rtc@70 {
724 compatible = "pnpPNP,b00";
725 reg = <0x1 0x70 0x2>;
726 };
727
728 gpio@400 {
729 reg = <0x1 0x400 0x80>;
730 };
731 };
732 };
733 }; 50 };
734
735 }; 51 };
736 52
737 pci1: pcie@fffe09000 { 53 pci1: pcie@fffe09000 {
738 compatible = "fsl,mpc8548-pcie";
739 device_type = "pci";
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xf 0xffe09000 0 0x1000>; 54 reg = <0xf 0xffe09000 0 0x1000>;
744 bus-range = <0 255>;
745 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 55 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
746 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; 56 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
747 clock-frequency = <33333333>;
748 interrupt-parent = <&mpic>;
749 interrupts = <25 2>;
750 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
751 interrupt-map = <
752 /* IDSEL 0x0 */
753 0000 0x0 0x0 0x1 &mpic 0x4 0x1
754 0000 0x0 0x0 0x2 &mpic 0x5 0x1
755 0000 0x0 0x0 0x3 &mpic 0x6 0x1
756 0000 0x0 0x0 0x4 &mpic 0x7 0x1
757 >;
758 pcie@0 { 57 pcie@0 {
759 reg = <0x0 0x0 0x0 0x0 0x0>;
760 #size-cells = <2>;
761 #address-cells = <3>;
762 device_type = "pci";
763 ranges = <0x2000000 0x0 0xe0000000 58 ranges = <0x2000000 0x0 0xe0000000
764 0x2000000 0x0 0xe0000000 59 0x2000000 0x0 0xe0000000
765 0x0 0x20000000 60 0x0 0x20000000
@@ -771,31 +66,10 @@
771 }; 66 };
772 67
773 pci2: pcie@fffe0a000 { 68 pci2: pcie@fffe0a000 {
774 compatible = "fsl,mpc8548-pcie";
775 device_type = "pci";
776 #interrupt-cells = <1>;
777 #size-cells = <2>;
778 #address-cells = <3>;
779 reg = <0xf 0xffe0a000 0 0x1000>; 69 reg = <0xf 0xffe0a000 0 0x1000>;
780 bus-range = <0 255>;
781 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 70 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
782 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; 71 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
783 clock-frequency = <33333333>;
784 interrupt-parent = <&mpic>;
785 interrupts = <26 2>;
786 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
787 interrupt-map = <
788 /* IDSEL 0x0 */
789 0000 0x0 0x0 0x1 &mpic 0x0 0x1
790 0000 0x0 0x0 0x2 &mpic 0x1 0x1
791 0000 0x0 0x0 0x3 &mpic 0x2 0x1
792 0000 0x0 0x0 0x4 &mpic 0x3 0x1
793 >;
794 pcie@0 { 72 pcie@0 {
795 reg = <0x0 0x0 0x0 0x0 0x0>;
796 #size-cells = <2>;
797 #address-cells = <3>;
798 device_type = "pci";
799 ranges = <0x2000000 0x0 0xe0000000 73 ranges = <0x2000000 0x0 0xe0000000
800 0x2000000 0x0 0xe0000000 74 0x2000000 0x0 0xe0000000
801 0x0 0x20000000 75 0x0 0x20000000
@@ -806,3 +80,11 @@
806 }; 80 };
807 }; 81 };
808}; 82};
83
84/*
85 * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
86 * for interrupt-map & interrupt-map-mask
87 */
88
89/include/ "fsl/mpc8572si-post.dtsi"
90/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 3375c2ab0c3..d34d1271212 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -14,494 +14,69 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/dts-v1/; 17/include/ "mpc8572ds.dts"
18
18/ { 19/ {
19 model = "fsl,MPC8572DS"; 20 model = "fsl,MPC8572DS";
20 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 serial0 = &serial0;
28 pci0 = &pci0;
29 pci1 = &pci1;
30 };
31 22
32 cpus { 23 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8572@0 { 24 PowerPC,8572@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 }; 25 };
48 26 PowerPC,8572@1 {
27 status = "disabled";
28 };
49 }; 29 };
50 30
51 memory { 31 localbus@ffe05000 {
52 device_type = "memory"; 32 status = "disabled";
53 reg = <0x0 0x0>; // Filled by U-Boot
54 }; 33 };
55 34
56 soc8572@ffe00000 { 35 soc8572@ffe00000 {
57 #address-cells = <1>; 36 serial@4600 {
58 #size-cells = <1>; 37 status = "disabled";
59 device_type = "soc";
60 compatible = "simple-bus";
61 ranges = <0x0 0xffe00000 0x100000>;
62 bus-frequency = <0>; // Filled out by uboot.
63
64 ecm-law@0 {
65 compatible = "fsl,ecm-law";
66 reg = <0x0 0x1000>;
67 fsl,num-laws = <12>;
68 }; 38 };
69 39 dma@c300 {
70 ecm@1000 { 40 status = "disabled";
71 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
72 reg = <0x1000 0x1000>;
73 interrupts = <17 2>;
74 interrupt-parent = <&mpic>;
75 }; 41 };
76 42 gpio-controller@f000 {
77 memory-controller@2000 {
78 compatible = "fsl,mpc8572-memory-controller";
79 reg = <0x2000 0x1000>;
80 interrupt-parent = <&mpic>;
81 interrupts = <18 2>;
82 }; 43 };
83 44 l2-cache-controller@20000 {
84 memory-controller@6000 {
85 compatible = "fsl,mpc8572-memory-controller";
86 reg = <0x6000 0x1000>;
87 interrupt-parent = <&mpic>;
88 interrupts = <18 2>;
89 };
90
91 L2: l2-cache-controller@20000 {
92 compatible = "fsl,mpc8572-l2-cache-controller";
93 reg = <0x20000 0x1000>;
94 cache-line-size = <32>; // 32 bytes
95 cache-size = <0x80000>; // L2, 512K 45 cache-size = <0x80000>; // L2, 512K
96 interrupt-parent = <&mpic>;
97 interrupts = <16 2>;
98 }; 46 };
99 47 ethernet@26000 {
100 i2c@3000 { 48 status = "disabled";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 cell-index = <0>;
104 compatible = "fsl-i2c";
105 reg = <0x3000 0x100>;
106 interrupts = <43 2>;
107 interrupt-parent = <&mpic>;
108 dfsrr;
109 }; 49 };
110 50 mdio@26520 {
111 i2c@3100 { 51 status = "disabled";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 cell-index = <1>;
115 compatible = "fsl-i2c";
116 reg = <0x3100 0x100>;
117 interrupts = <43 2>;
118 interrupt-parent = <&mpic>;
119 dfsrr;
120 }; 52 };
121 53 ethernet@27000 {
122 dma@21300 { 54 status = "disabled";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
126 reg = <0x21300 0x4>;
127 ranges = <0x0 0x21100 0x200>;
128 cell-index = <0>;
129 dma-channel@0 {
130 compatible = "fsl,mpc8572-dma-channel",
131 "fsl,eloplus-dma-channel";
132 reg = <0x0 0x80>;
133 cell-index = <0>;
134 interrupt-parent = <&mpic>;
135 interrupts = <20 2>;
136 };
137 dma-channel@80 {
138 compatible = "fsl,mpc8572-dma-channel",
139 "fsl,eloplus-dma-channel";
140 reg = <0x80 0x80>;
141 cell-index = <1>;
142 interrupt-parent = <&mpic>;
143 interrupts = <21 2>;
144 };
145 dma-channel@100 {
146 compatible = "fsl,mpc8572-dma-channel",
147 "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <22 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,mpc8572-dma-channel",
155 "fsl,eloplus-dma-channel";
156 reg = <0x180 0x80>;
157 cell-index = <3>;
158 interrupt-parent = <&mpic>;
159 interrupts = <23 2>;
160 };
161 }; 55 };
162 56 mdio@27520 {
163 enet0: ethernet@24000 { 57 status = "disabled";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 cell-index = <0>;
167 device_type = "network";
168 model = "eTSEC";
169 compatible = "gianfar";
170 reg = <0x24000 0x1000>;
171 ranges = <0x0 0x24000 0x1000>;
172 local-mac-address = [ 00 00 00 00 00 00 ];
173 interrupts = <29 2 30 2 34 2>;
174 interrupt-parent = <&mpic>;
175 phy-handle = <&phy0>;
176 phy-connection-type = "rgmii-id";
177
178 mdio@520 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,gianfar-mdio";
182 reg = <0x520 0x20>;
183
184 phy0: ethernet-phy@0 {
185 interrupt-parent = <&mpic>;
186 interrupts = <10 1>;
187 reg = <0x0>;
188 };
189 phy1: ethernet-phy@1 {
190 interrupt-parent = <&mpic>;
191 interrupts = <10 1>;
192 reg = <0x1>;
193 };
194 };
195 }; 58 };
196 59 pic@40000 {
197 enet1: ethernet@25000 { 60 protected-sources = <
198 cell-index = <1>; 61 31 32 33 37 38 39 /* enet2 enet3 */
199 device_type = "network"; 62 76 77 78 79 26 42 /* dma2 pci2 serial*/
200 model = "eTSEC"; 63 0xe4 0xe5 0xe6 0xe7 /* msi */
201 compatible = "gianfar"; 64 >;
202 reg = <0x25000 0x1000>;
203 local-mac-address = [ 00 00 00 00 00 00 ];
204 interrupts = <35 2 36 2 40 2>;
205 interrupt-parent = <&mpic>;
206 phy-handle = <&phy1>;
207 phy-connection-type = "rgmii-id";
208 };
209
210 serial0: serial@4500 {
211 cell-index = <0>;
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 }; 65 };
217 66
218 msi@41600 { 67 msi@41600 {
219 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
220 reg = <0x41600 0x80>;
221 msi-available-ranges = <0 0x80>; 68 msi-available-ranges = <0 0x80>;
222 interrupts = < 69 interrupts = <
223 0xe0 0 70 0xe0 0
224 0xe1 0 71 0xe1 0
225 0xe2 0 72 0xe2 0
226 0xe3 0>; 73 0xe3 0>;
227 interrupt-parent = <&mpic>;
228 };
229
230 global-utilities@e0000 { //global utilities block
231 compatible = "fsl,mpc8572-guts";
232 reg = <0xe0000 0x1000>;
233 fsl,has-rstcr;
234 };
235
236 crypto@30000 {
237 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
238 "fsl,sec2.1", "fsl,sec2.0";
239 reg = <0x30000 0x10000>;
240 interrupts = <45 2 58 2>;
241 interrupt-parent = <&mpic>;
242 fsl,num-channels = <4>;
243 fsl,channel-fifo-len = <24>;
244 fsl,exec-units-mask = <0x9fe>;
245 fsl,descriptor-types-mask = <0x3ab0ebf>;
246 };
247
248 mpic: pic@40000 {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <2>;
252 reg = <0x40000 0x40000>;
253 compatible = "chrp,open-pic";
254 device_type = "open-pic";
255 protected-sources = <
256 31 32 33 37 38 39 /* enet2 enet3 */
257 76 77 78 79 26 42 /* dma2 pci2 serial*/
258 0xe4 0xe5 0xe6 0xe7 /* msi */
259 >;
260 }; 74 };
261 }; 75 timer@42100 {
262 76 status = "disabled";
263 pci0: pcie@ffe08000 {
264 compatible = "fsl,mpc8548-pcie";
265 device_type = "pci";
266 #interrupt-cells = <1>;
267 #size-cells = <2>;
268 #address-cells = <3>;
269 reg = <0xffe08000 0x1000>;
270 bus-range = <0 255>;
271 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
272 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
273 clock-frequency = <33333333>;
274 interrupt-parent = <&mpic>;
275 interrupts = <24 2>;
276 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
277 interrupt-map = <
278 /* IDSEL 0x11 func 0 - PCI slot 1 */
279 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
280 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
281 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
282 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
283
284 /* IDSEL 0x11 func 1 - PCI slot 1 */
285 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
286 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
287 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
288 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
289
290 /* IDSEL 0x11 func 2 - PCI slot 1 */
291 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
292 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
293 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
294 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
295
296 /* IDSEL 0x11 func 3 - PCI slot 1 */
297 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
298 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
299 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
300 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
301
302 /* IDSEL 0x11 func 4 - PCI slot 1 */
303 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
304 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
305 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
306 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
307
308 /* IDSEL 0x11 func 5 - PCI slot 1 */
309 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
310 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
311 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
312 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
313
314 /* IDSEL 0x11 func 6 - PCI slot 1 */
315 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
316 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
317 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
318 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
319
320 /* IDSEL 0x11 func 7 - PCI slot 1 */
321 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
322 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
323 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
324 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
325
326 /* IDSEL 0x12 func 0 - PCI slot 2 */
327 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
328 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
329 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
330 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
331
332 /* IDSEL 0x12 func 1 - PCI slot 2 */
333 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
334 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
335 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
336 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
337
338 /* IDSEL 0x12 func 2 - PCI slot 2 */
339 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
340 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
341 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
342 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
343
344 /* IDSEL 0x12 func 3 - PCI slot 2 */
345 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
346 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
347 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
348 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
349
350 /* IDSEL 0x12 func 4 - PCI slot 2 */
351 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
352 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
353 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
354 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
355
356 /* IDSEL 0x12 func 5 - PCI slot 2 */
357 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
358 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
359 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
360 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
361
362 /* IDSEL 0x12 func 6 - PCI slot 2 */
363 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
364 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
365 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
366 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
367
368 /* IDSEL 0x12 func 7 - PCI slot 2 */
369 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
370 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
371 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
372 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
373
374 // IDSEL 0x1c USB
375 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
376 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
377 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
378 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
379
380 // IDSEL 0x1d Audio
381 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
382
383 // IDSEL 0x1e Legacy
384 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
385 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
386
387 // IDSEL 0x1f IDE/SATA
388 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
389 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
390
391 >;
392
393 pcie@0 {
394 reg = <0x0 0x0 0x0 0x0 0x0>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 device_type = "pci";
398 ranges = <0x2000000 0x0 0x80000000
399 0x2000000 0x0 0x80000000
400 0x0 0x20000000
401
402 0x1000000 0x0 0x0
403 0x1000000 0x0 0x0
404 0x0 0x10000>;
405 uli1575@0 {
406 reg = <0x0 0x0 0x0 0x0 0x0>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 ranges = <0x2000000 0x0 0x80000000
410 0x2000000 0x0 0x80000000
411 0x0 0x20000000
412
413 0x1000000 0x0 0x0
414 0x1000000 0x0 0x0
415 0x0 0x10000>;
416 isa@1e {
417 device_type = "isa";
418 #interrupt-cells = <2>;
419 #size-cells = <1>;
420 #address-cells = <2>;
421 reg = <0xf000 0x0 0x0 0x0 0x0>;
422 ranges = <0x1 0x0 0x1000000 0x0 0x0
423 0x1000>;
424 interrupt-parent = <&i8259>;
425
426 i8259: interrupt-controller@20 {
427 reg = <0x1 0x20 0x2
428 0x1 0xa0 0x2
429 0x1 0x4d0 0x2>;
430 interrupt-controller;
431 device_type = "interrupt-controller";
432 #address-cells = <0>;
433 #interrupt-cells = <2>;
434 compatible = "chrp,iic";
435 interrupts = <9 2>;
436 interrupt-parent = <&mpic>;
437 };
438
439 i8042@60 {
440 #size-cells = <0>;
441 #address-cells = <1>;
442 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
443 interrupts = <1 3 12 3>;
444 interrupt-parent =
445 <&i8259>;
446
447 keyboard@0 {
448 reg = <0x0>;
449 compatible = "pnpPNP,303";
450 };
451
452 mouse@1 {
453 reg = <0x1>;
454 compatible = "pnpPNP,f03";
455 };
456 };
457
458 rtc@70 {
459 compatible = "pnpPNP,b00";
460 reg = <0x1 0x70 0x2>;
461 };
462
463 gpio@400 {
464 reg = <0x1 0x400 0x80>;
465 };
466 };
467 };
468 }; 77 };
469
470 }; 78 };
471 79 pcie@ffe0a000 {
472 pci1: pcie@ffe09000 { 80 status = "disabled";
473 compatible = "fsl,mpc8548-pcie";
474 device_type = "pci";
475 #interrupt-cells = <1>;
476 #size-cells = <2>;
477 #address-cells = <3>;
478 reg = <0xffe09000 0x1000>;
479 bus-range = <0 255>;
480 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
481 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
482 clock-frequency = <33333333>;
483 interrupt-parent = <&mpic>;
484 interrupts = <25 2>;
485 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
486 interrupt-map = <
487 /* IDSEL 0x0 */
488 0000 0x0 0x0 0x1 &mpic 0x4 0x1
489 0000 0x0 0x0 0x2 &mpic 0x5 0x1
490 0000 0x0 0x0 0x3 &mpic 0x6 0x1
491 0000 0x0 0x0 0x4 &mpic 0x7 0x1
492 >;
493 pcie@0 {
494 reg = <0x0 0x0 0x0 0x0 0x0>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 device_type = "pci";
498 ranges = <0x2000000 0x0 0xa0000000
499 0x2000000 0x0 0xa0000000
500 0x0 0x20000000
501
502 0x1000000 0x0 0x0
503 0x1000000 0x0 0x0
504 0x0 0x10000>;
505 };
506 }; 81 };
507}; 82};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index e7b477f6a3f..d6a8fafc0d0 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -15,169 +15,74 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/dts-v1/; 18/include/ "mpc8572ds.dts"
19
19/ { 20/ {
20 model = "fsl,MPC8572DS"; 21 model = "fsl,MPC8572DS";
21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 22 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28 serial0 = &serial0;
29 pci2 = &pci2;
30 };
31 23
32 cpus { 24 cpus {
33 #address-cells = <1>; 25 PowerPC,8572@0 {
34 #size-cells = <0>; 26 status = "disabled";
35 27 };
36 PowerPC,8572@1 { 28 PowerPC,8572@1 {
37 device_type = "cpu";
38 reg = <0x1>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 }; 29 };
48 }; 30 };
49 31
50 memory { 32 localbus@ffe05000 {
51 device_type = "memory"; 33 status = "disabled";
52 reg = <0x0 0x0>; // Filled by U-Boot
53 }; 34 };
54 35
55 soc8572@ffe00000 { 36 soc8572@ffe00000 {
56 #address-cells = <1>; 37 ecm-law@0 {
57 #size-cells = <1>; 38 status = "disabled";
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xffe00000 0x100000>;
61 bus-frequency = <0>; // Filled out by uboot.
62
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8572-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 cache-line-size = <32>; // 32 bytes
67 cache-size = <0x80000>; // L2, 512K
68 interrupt-parent = <&mpic>;
69 }; 39 };
70 40 ecm@1000 {
71 dma@c300 { 41 status = "disabled";
72 #address-cells = <1>; 42 };
73 #size-cells = <1>; 43 memory-controller@2000 {
74 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 44 status = "disabled";
75 reg = <0xc300 0x4>; 45 };
76 ranges = <0x0 0xc100 0x200>; 46 memory-controller@6000 {
77 cell-index = <0>; 47 status = "disabled";
78 dma-channel@0 { 48 };
79 compatible = "fsl,mpc8572-dma-channel", 49 i2c@3000 {
80 "fsl,eloplus-dma-channel"; 50 status = "disabled";
81 reg = <0x0 0x80>; 51 };
82 cell-index = <0>; 52 i2c@3100 {
83 interrupt-parent = <&mpic>; 53 status = "disabled";
84 interrupts = <76 2>; 54 };
85 }; 55 serial@4500 {
86 dma-channel@80 { 56 status = "disabled";
87 compatible = "fsl,mpc8572-dma-channel", 57 };
88 "fsl,eloplus-dma-channel"; 58 gpio-controller@f000 {
89 reg = <0x80 0x80>; 59 status = "disabled";
90 cell-index = <1>; 60 };
91 interrupt-parent = <&mpic>; 61 l2-cache-controller@20000 {
92 interrupts = <77 2>; 62 cache-size = <0x80000>; // L2, 512K
93 }; 63 };
94 dma-channel@100 { 64 dma@21300 {
95 compatible = "fsl,mpc8572-dma-channel", 65 status = "disabled";
96 "fsl,eloplus-dma-channel"; 66 };
97 reg = <0x100 0x80>; 67 ethernet@24000 {
98 cell-index = <2>; 68 status = "disabled";
99 interrupt-parent = <&mpic>;
100 interrupts = <78 2>;
101 };
102 dma-channel@180 {
103 compatible = "fsl,mpc8572-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x180 0x80>;
106 cell-index = <3>;
107 interrupt-parent = <&mpic>;
108 interrupts = <79 2>;
109 };
110 }; 69 };
111
112 mdio@24520 { 70 mdio@24520 {
113 #address-cells = <1>; 71 status = "disabled";
114 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio";
116 reg = <0x24520 0x20>;
117
118 phy2: ethernet-phy@2 {
119 interrupt-parent = <&mpic>;
120 reg = <0x2>;
121 };
122 phy3: ethernet-phy@3 {
123 interrupt-parent = <&mpic>;
124 reg = <0x3>;
125 };
126 }; 72 };
127 73 ptp_clock@24e00 {
128 enet2: ethernet@26000 { 74 status = "disabled";
129 cell-index = <2>;
130 device_type = "network";
131 model = "eTSEC";
132 compatible = "gianfar";
133 reg = <0x26000 0x1000>;
134 local-mac-address = [ 00 00 00 00 00 00 ];
135 interrupts = <31 2 32 2 33 2>;
136 interrupt-parent = <&mpic>;
137 phy-handle = <&phy2>;
138 phy-connection-type = "rgmii-id";
139 }; 75 };
140 76 ethernet@25000 {
141 enet3: ethernet@27000 { 77 status = "disabled";
142 cell-index = <3>;
143 device_type = "network";
144 model = "eTSEC";
145 compatible = "gianfar";
146 reg = <0x27000 0x1000>;
147 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <37 2 38 2 39 2>;
149 interrupt-parent = <&mpic>;
150 phy-handle = <&phy3>;
151 phy-connection-type = "rgmii-id";
152 }; 78 };
153 79 mdio@25520 {
154 msi@41600 { 80 status = "disabled";
155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
156 reg = <0x41600 0x80>;
157 msi-available-ranges = <0x80 0x80>;
158 interrupts = <
159 0xe4 0
160 0xe5 0
161 0xe6 0
162 0xe7 0>;
163 interrupt-parent = <&mpic>;
164 }; 81 };
165 82 crypto@30000 {
166 serial0: serial@4600 { 83 status = "disabled";
167 cell-index = <1>;
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <0x4600 0x100>;
171 clock-frequency = <0>;
172 }; 84 };
173 85 pic@40000 {
174 mpic: pic@40000 {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>;
179 compatible = "chrp,open-pic";
180 device_type = "open-pic";
181 protected-sources = < 86 protected-sources = <
182 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */ 87 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
183 29 30 34 35 36 40 /* enet0 enet1 */ 88 29 30 34 35 36 40 /* enet0 enet1 */
@@ -189,41 +94,25 @@
189 0xe0 0xe1 0xe2 0xe3 /* msi */ 94 0xe0 0xe1 0xe2 0xe3 /* msi */
190 >; 95 >;
191 }; 96 };
192 }; 97 timer@41100 {
193 98 status = "disabled";
194 pci2: pcie@ffe0a000 {
195 compatible = "fsl,mpc8548-pcie";
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 reg = <0xffe0a000 0x1000>;
201 bus-range = <0 255>;
202 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
203 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
204 clock-frequency = <33333333>;
205 interrupt-parent = <&mpic>;
206 interrupts = <26 2>;
207 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
208 interrupt-map = <
209 /* IDSEL 0x0 */
210 0000 0x0 0x0 0x1 &mpic 0x0 0x1
211 0000 0x0 0x0 0x2 &mpic 0x1 0x1
212 0000 0x0 0x0 0x3 &mpic 0x2 0x1
213 0000 0x0 0x0 0x4 &mpic 0x3 0x1
214 >;
215 pcie@0 {
216 reg = <0x0 0x0 0x0 0x0 0x0>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219 device_type = "pci";
220 ranges = <0x2000000 0x0 0xc0000000
221 0x2000000 0x0 0xc0000000
222 0x0 0x20000000
223
224 0x1000000 0x0 0x0
225 0x1000000 0x0 0x0
226 0x0 0x10000>;
227 }; 99 };
100 msi@41600 {
101 msi-available-ranges = <0x80 0x80>;
102 interrupts = <
103 0xe4 0
104 0xe5 0
105 0xe6 0
106 0xe7 0>;
107 };
108 global-utilities@e0000 {
109 status = "disabled";
110 };
111 };
112 pcie@ffe08000 {
113 status = "disabled";
114 };
115 pcie@ffe09000 {
116 status = "disabled";
228 }; 117 };
229}; 118};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 83c3218cb4d..6a109a0ceac 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -175,7 +175,7 @@
175 serial0: serial@4500 { 175 serial0: serial@4500 {
176 cell-index = <0>; 176 cell-index = <0>;
177 device_type = "serial"; 177 device_type = "serial";
178 compatible = "ns16550"; 178 compatible = "fsl,ns16550", "ns16550";
179 reg = <0x4500 0x100>; 179 reg = <0x4500 0x100>;
180 clock-frequency = <0>; 180 clock-frequency = <0>;
181 interrupts = <42 2>; 181 interrupts = <42 2>;
@@ -186,7 +186,7 @@
186 serial1: serial@4600 { 186 serial1: serial@4600 {
187 cell-index = <1>; 187 cell-index = <1>;
188 device_type = "serial"; 188 device_type = "serial";
189 compatible = "ns16550"; 189 compatible = "fsl,ns16550", "ns16550";
190 reg = <0x4600 0x100>; 190 reg = <0x4600 0x100>;
191 clock-frequency = <0>; 191 clock-frequency = <0>;
192 interrupts = <42 2>; 192 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 848320e4d3c..1e8666ccbed 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -26,13 +26,6 @@
26 serial1 = &serial1; 26 serial1 = &serial1;
27 pci0 = &pci0; 27 pci0 = &pci0;
28 pci1 = &pci1; 28 pci1 = &pci1;
29/*
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
34 */
35 /* rapidio0 = &rapidio0; */
36 }; 29 };
37 30
38 cpus { 31 cpus {
@@ -335,7 +328,7 @@
335 serial0: serial@4500 { 328 serial0: serial@4500 {
336 cell-index = <0>; 329 cell-index = <0>;
337 device_type = "serial"; 330 device_type = "serial";
338 compatible = "ns16550"; 331 compatible = "fsl,ns16550", "ns16550";
339 reg = <0x4500 0x100>; 332 reg = <0x4500 0x100>;
340 clock-frequency = <0>; 333 clock-frequency = <0>;
341 interrupts = <42 2>; 334 interrupts = <42 2>;
@@ -345,7 +338,7 @@
345 serial1: serial@4600 { 338 serial1: serial@4600 {
346 cell-index = <1>; 339 cell-index = <1>;
347 device_type = "serial"; 340 device_type = "serial";
348 compatible = "ns16550"; 341 compatible = "fsl,ns16550", "ns16550";
349 reg = <0x4600 0x100>; 342 reg = <0x4600 0x100>;
350 clock-frequency = <0>; 343 clock-frequency = <0>;
351 interrupts = <28 2>; 344 interrupts = <28 2>;
@@ -361,6 +354,41 @@
361 device_type = "open-pic"; 354 device_type = "open-pic";
362 }; 355 };
363 356
357 rmu: rmu@d3000 {
358 #address-cells = <1>;
359 #size-cells = <1>;
360 compatible = "fsl,srio-rmu";
361 reg = <0xd3000 0x500>;
362 ranges = <0x0 0xd3000 0x500>;
363
364 message-unit@0 {
365 compatible = "fsl,srio-msg-unit";
366 reg = <0x0 0x100>;
367 interrupts = <
368 53 2 /* msg1_tx_irq */
369 54 2>;/* msg1_rx_irq */
370 };
371 message-unit@100 {
372 compatible = "fsl,srio-msg-unit";
373 reg = <0x100 0x100>;
374 interrupts = <
375 55 2 /* msg2_tx_irq */
376 56 2>;/* msg2_rx_irq */
377 };
378 doorbell-unit@400 {
379 compatible = "fsl,srio-dbell-unit";
380 reg = <0x400 0x80>;
381 interrupts = <
382 49 2 /* bell_outb_irq */
383 50 2>;/* bell_inb_irq */
384 };
385 port-write-unit@4e0 {
386 compatible = "fsl,srio-port-write-unit";
387 reg = <0x4e0 0x20>;
388 interrupts = <48 2>;
389 };
390 };
391
364 global-utilities@e0000 { 392 global-utilities@e0000 {
365 compatible = "fsl,mpc8641-guts"; 393 compatible = "fsl,mpc8641-guts";
366 reg = <0xe0000 0x1000>; 394 reg = <0xe0000 0x1000>;
@@ -612,16 +640,27 @@
612 }; 640 };
613 }; 641 };
614/* 642/*
615 rapidio0: rapidio@ffec0000 { 643 * Only one of Rapid IO or PCI can be present due to HW limitations and
644 * due to the fact that the 2 now share address space in the new memory
645 * map. The most likely case is that we have PCI, so comment out the
646 * rapidio node. Leave it here for reference.
647
648 rapidio@ffec0000 {
649 reg = <0xffec0000 0x11000>;
650 compatible = "fsl,srio";
651 interrupt-parent = <&mpic>;
652 interrupts = <48 2>;
616 #address-cells = <2>; 653 #address-cells = <2>;
617 #size-cells = <2>; 654 #size-cells = <2>;
618 compatible = "fsl,rapidio-delta"; 655 fsl,srio-rmu-handle = <&rmu>;
619 reg = <0xffec0000 0x20000>; 656 ranges;
620 ranges = <0 0 0x80000000 0 0x20000000>; 657
621 interrupt-parent = <&mpic>; 658 port1 {
622 // err_irq bell_outb_irq bell_inb_irq 659 #address-cells = <2>;
623 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq 660 #size-cells = <2>;
624 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>; 661 cell-index = <1>;
662 ranges = <0 0 0x80000000 0 0x20000000>;
663 };
625 }; 664 };
626*/ 665*/
627 666
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
index 8be8e701e1d..fd4cd4da60b 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -328,7 +328,7 @@
328 serial0: serial@4500 { 328 serial0: serial@4500 {
329 cell-index = <0>; 329 cell-index = <0>;
330 device_type = "serial"; 330 device_type = "serial";
331 compatible = "ns16550"; 331 compatible = "fsl,ns16550", "ns16550";
332 reg = <0x4500 0x100>; 332 reg = <0x4500 0x100>;
333 clock-frequency = <0>; 333 clock-frequency = <0>;
334 interrupts = <42 2>; 334 interrupts = <42 2>;
@@ -338,7 +338,7 @@
338 serial1: serial@4600 { 338 serial1: serial@4600 {
339 cell-index = <1>; 339 cell-index = <1>;
340 device_type = "serial"; 340 device_type = "serial";
341 compatible = "ns16550"; 341 compatible = "fsl,ns16550", "ns16550";
342 reg = <0x4600 0x100>; 342 reg = <0x4600 0x100>;
343 clock-frequency = <0>; 343 clock-frequency = <0>;
344 interrupts = <28 2>; 344 interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/obs600.dts b/arch/powerpc/boot/dts/obs600.dts
new file mode 100644
index 00000000000..18e7d79ee4c
--- /dev/null
+++ b/arch/powerpc/boot/dts/obs600.dts
@@ -0,0 +1,314 @@
1/*
2 * Device Tree Source for PlatHome OpenBlockS 600 (405EX)
3 *
4 * Copyright 2011 Ben Herrenschmidt, IBM Corp.
5 *
6 * Based on Kilauea by:
7 *
8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 model = "PlatHome,OpenBlockS 600";
21 compatible = "plathome,obs600";
22 dcr-parent = <&{/cpus/cpu@0}>;
23
24 aliases {
25 ethernet0 = &EMAC0;
26 ethernet1 = &EMAC1;
27 serial0 = &UART0;
28 serial1 = &UART1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 model = "PowerPC,405EX";
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
43 i-cache-size = <16384>; /* 16 kB */
44 d-cache-size = <16384>; /* 16 kB */
45 dcr-controller;
46 dcr-access-method = "native";
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
53 };
54
55 UIC0: interrupt-controller {
56 compatible = "ibm,uic-405ex", "ibm,uic";
57 interrupt-controller;
58 cell-index = <0>;
59 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 };
64
65 UIC1: interrupt-controller1 {
66 compatible = "ibm,uic-405ex","ibm,uic";
67 interrupt-controller;
68 cell-index = <1>;
69 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>;
75 };
76
77 UIC2: interrupt-controller2 {
78 compatible = "ibm,uic-405ex","ibm,uic";
79 interrupt-controller;
80 cell-index = <2>;
81 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>;
83 #size-cells = <0>;
84 #interrupt-cells = <2>;
85 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>;
87 };
88
89 CPM0: cpm {
90 compatible = "ibm,cpm";
91 dcr-access-method = "native";
92 dcr-reg = <0x0b0 0x003>;
93 unused-units = <0x00000000>;
94 idle-doze = <0x02000000>;
95 standby = <0xe3e74800>;
96 };
97
98 plb {
99 compatible = "ibm,plb-405ex", "ibm,plb4";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 clock-frequency = <0>; /* Filled in by U-Boot */
104
105 SDRAM0: memory-controller {
106 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
107 dcr-reg = <0x010 0x002>;
108 interrupt-parent = <&UIC2>;
109 interrupts = <0x5 0x4 /* ECC DED Error */
110 0x6 0x4>; /* ECC SEC Error */
111 };
112
113 CRYPTO: crypto@ef700000 {
114 compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
115 reg = <0xef700000 0x80400>;
116 interrupt-parent = <&UIC0>;
117 interrupts = <0x17 0x2>;
118 };
119
120 MAL0: mcmal {
121 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
122 dcr-reg = <0x180 0x062>;
123 num-tx-chans = <2>;
124 num-rx-chans = <2>;
125 interrupt-parent = <&MAL0>;
126 interrupts = <0x0 0x1 0x2 0x3 0x4>;
127 #interrupt-cells = <1>;
128 #address-cells = <0>;
129 #size-cells = <0>;
130 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
131 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
132 /*SERR*/ 0x2 &UIC1 0x0 0x4
133 /*TXDE*/ 0x3 &UIC1 0x1 0x4
134 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
135 interrupt-map-mask = <0xffffffff>;
136 };
137
138 POB0: opb {
139 compatible = "ibm,opb-405ex", "ibm,opb";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x80000000 0x80000000 0x10000000
143 0xef600000 0xef600000 0x00a00000
144 0xf0000000 0xf0000000 0x10000000>;
145 dcr-reg = <0x0a0 0x005>;
146 clock-frequency = <0>; /* Filled in by U-Boot */
147
148 EBC0: ebc {
149 compatible = "ibm,ebc-405ex", "ibm,ebc";
150 dcr-reg = <0x012 0x002>;
151 #address-cells = <2>;
152 #size-cells = <1>;
153 clock-frequency = <0>; /* Filled in by U-Boot */
154 /* ranges property is supplied by U-Boot */
155 interrupts = <0x5 0x1>;
156 interrupt-parent = <&UIC1>;
157
158 nor_flash@0,0 {
159 compatible = "amd,s29gl512n", "cfi-flash";
160 bank-width = <2>;
161 reg = <0x00000000 0x00000000 0x08000000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 partition@0 {
165 label = "kernel + initrd";
166 reg = <0x00000000 0x03de0000>;
167 };
168 partition@3de0000 {
169 label = "user config area";
170 reg = <0x03de0000 0x00080000>;
171 };
172 partition@3e60000 {
173 label = "user program area";
174 reg = <0x03e60000 0x04000000>;
175 };
176 partition@7e60000 {
177 label = "flat device tree";
178 reg = <0x07e60000 0x00080000>;
179 };
180 partition@7ee0000 {
181 label = "test program";
182 reg = <0x07ee0000 0x00080000>;
183 };
184 partition@7f60000 {
185 label = "u-boot env";
186 reg = <0x07f60000 0x00040000>;
187 };
188 partition@7fa0000 {
189 label = "u-boot";
190 reg = <0x07fa0000 0x00060000>;
191 };
192 };
193 };
194
195 UART0: serial@ef600200 {
196 device_type = "serial";
197 compatible = "ns16550";
198 reg = <0xef600200 0x00000008>;
199 virtual-reg = <0xef600200>;
200 clock-frequency = <0>; /* Filled in by U-Boot */
201 current-speed = <0>;
202 interrupt-parent = <&UIC0>;
203 interrupts = <0x1a 0x4>;
204 };
205
206 UART1: serial@ef600300 {
207 device_type = "serial";
208 compatible = "ns16550";
209 reg = <0xef600300 0x00000008>;
210 virtual-reg = <0xef600300>;
211 clock-frequency = <0>; /* Filled in by U-Boot */
212 current-speed = <0>;
213 interrupt-parent = <&UIC0>;
214 interrupts = <0x1 0x4>;
215 };
216
217 IIC0: i2c@ef600400 {
218 compatible = "ibm,iic-405ex", "ibm,iic";
219 reg = <0xef600400 0x00000014>;
220 interrupt-parent = <&UIC0>;
221 interrupts = <0x2 0x4>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 rtc@68 {
226 compatible = "dallas,ds1340";
227 reg = <0x68>;
228 };
229 };
230
231 IIC1: i2c@ef600500 {
232 compatible = "ibm,iic-405ex", "ibm,iic";
233 reg = <0xef600500 0x00000014>;
234 interrupt-parent = <&UIC0>;
235 interrupts = <0x7 0x4>;
236 };
237
238 RGMII0: emac-rgmii@ef600b00 {
239 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
240 reg = <0xef600b00 0x00000104>;
241 has-mdio;
242 };
243
244 EMAC0: ethernet@ef600900 {
245 linux,network-index = <0x0>;
246 device_type = "network";
247 compatible = "ibm,emac-405ex", "ibm,emac4sync";
248 interrupt-parent = <&EMAC0>;
249 interrupts = <0x0 0x1>;
250 #interrupt-cells = <1>;
251 #address-cells = <0>;
252 #size-cells = <0>;
253 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
254 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
255 reg = <0xef600900 0x000000c4>;
256 local-mac-address = [000000000000]; /* Filled in by U-Boot */
257 mal-device = <&MAL0>;
258 mal-tx-channel = <0>;
259 mal-rx-channel = <0>;
260 cell-index = <0>;
261 max-frame-size = <9000>;
262 rx-fifo-size = <4096>;
263 tx-fifo-size = <2048>;
264 rx-fifo-size-gige = <16384>;
265 tx-fifo-size-gige = <16384>;
266 phy-mode = "rgmii";
267 phy-map = <0x00000000>;
268 rgmii-device = <&RGMII0>;
269 rgmii-channel = <0>;
270 has-inverted-stacr-oc;
271 has-new-stacr-staopc;
272 };
273
274 EMAC1: ethernet@ef600a00 {
275 linux,network-index = <0x1>;
276 device_type = "network";
277 compatible = "ibm,emac-405ex", "ibm,emac4sync";
278 interrupt-parent = <&EMAC1>;
279 interrupts = <0x0 0x1>;
280 #interrupt-cells = <1>;
281 #address-cells = <0>;
282 #size-cells = <0>;
283 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
284 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
285 reg = <0xef600a00 0x000000c4>;
286 local-mac-address = [000000000000]; /* Filled in by U-Boot */
287 mal-device = <&MAL0>;
288 mal-tx-channel = <1>;
289 mal-rx-channel = <1>;
290 cell-index = <1>;
291 max-frame-size = <9000>;
292 rx-fifo-size = <4096>;
293 tx-fifo-size = <2048>;
294 rx-fifo-size-gige = <16384>;
295 tx-fifo-size-gige = <16384>;
296 phy-mode = "rgmii";
297 phy-map = <0x00000000>;
298 rgmii-device = <&RGMII0>;
299 rgmii-channel = <1>;
300 has-inverted-stacr-oc;
301 has-new-stacr-staopc;
302 };
303
304 GPIO: gpio@ef600800 {
305 device_type = "gpio";
306 compatible = "ibm,gpio-405ex", "ibm,ppc4xx-gpio";
307 reg = <0xef600800 0x50>;
308 };
309 };
310 };
311 chosen {
312 linux,stdout-path = "/plb/opb/serial@ef600200";
313 };
314};
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index d6c669c888e..b868d22984e 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -9,230 +9,33 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1010si.dtsi" 12/include/ "fsl/p1010si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P1010RDB"; 15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB"; 16 compatible = "fsl,P1010RDB";
17 17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 can0 = &can0;
27 can1 = &can1;
28 };
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 ifc@ffe1e000 { 22 board_ifc: ifc: ifc@ffe1e000 {
35 /* NOR, NAND Flashes and CPLD on board */ 23 /* NOR, NAND Flashes and CPLD on board */
36 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 24 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
37 0x1 0x0 0x0 0xff800000 0x00010000 25 0x1 0x0 0x0 0xff800000 0x00010000
38 0x3 0x0 0x0 0xffb00000 0x00000020>; 26 0x3 0x0 0x0 0xffb00000 0x00000020>;
39 27 reg = <0x0 0xffe1e000 0 0x2000>;
40 nor@0,0 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "cfi-flash";
44 reg = <0x0 0x0 0x2000000>;
45 bank-width = <2>;
46 device-width = <1>;
47
48 partition@40000 {
49 /* 256KB for DTB Image */
50 reg = <0x00040000 0x00040000>;
51 label = "NOR DTB Image";
52 };
53
54 partition@80000 {
55 /* 7 MB for Linux Kernel Image */
56 reg = <0x00080000 0x00700000>;
57 label = "NOR Linux Kernel Image";
58 };
59
60 partition@800000 {
61 /* 20MB for JFFS2 based Root file System */
62 reg = <0x00800000 0x01400000>;
63 label = "NOR JFFS2 Root File System";
64 };
65
66 partition@1f00000 {
67 /* This location must not be altered */
68 /* 512KB for u-boot Bootloader Image */
69 /* 512KB for u-boot Environment Variables */
70 reg = <0x01f00000 0x00100000>;
71 label = "NOR U-Boot Image";
72 read-only;
73 };
74 };
75
76 nand@1,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,ifc-nand";
80 reg = <0x1 0x0 0x10000>;
81
82 partition@0 {
83 /* This location must not be altered */
84 /* 1MB for u-boot Bootloader Image */
85 reg = <0x0 0x00100000>;
86 label = "NAND U-Boot Image";
87 read-only;
88 };
89
90 partition@100000 {
91 /* 1MB for DTB Image */
92 reg = <0x00100000 0x00100000>;
93 label = "NAND DTB Image";
94 };
95
96 partition@200000 {
97 /* 4MB for Linux Kernel Image */
98 reg = <0x00200000 0x00400000>;
99 label = "NAND Linux Kernel Image";
100 };
101
102 partition@600000 {
103 /* 4MB for Compressed Root file System Image */
104 reg = <0x00600000 0x00400000>;
105 label = "NAND Compressed RFS Image";
106 };
107
108 partition@a00000 {
109 /* 15MB for JFFS2 based Root file System */
110 reg = <0x00a00000 0x00f00000>;
111 label = "NAND JFFS2 Root File System";
112 };
113
114 partition@1900000 {
115 /* 7MB for User Area */
116 reg = <0x01900000 0x00700000>;
117 label = "NAND User area";
118 };
119 };
120
121 cpld@3,0 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 compatible = "fsl,p1010rdb-cpld";
125 reg = <0x3 0x0 0x0000020>;
126 bank-width = <1>;
127 device-width = <1>;
128 };
129 }; 28 };
130 29
131 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
132 spi@7000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
133 flash@0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "spansion,s25sl12801";
137 reg = <0>;
138 spi-max-frequency = <50000000>;
139
140 partition@0 {
141 /* 1MB for u-boot Bootloader Image */
142 /* 1MB for Environment */
143 reg = <0x0 0x00100000>;
144 label = "SPI Flash U-Boot Image";
145 read-only;
146 };
147
148 partition@100000 {
149 /* 512KB for DTB Image */
150 reg = <0x00100000 0x00080000>;
151 label = "SPI Flash DTB Image";
152 };
153
154 partition@180000 {
155 /* 4MB for Linux Kernel Image */
156 reg = <0x00180000 0x00400000>;
157 label = "SPI Flash Linux Kernel Image";
158 };
159
160 partition@580000 {
161 /* 4MB for Compressed RFS Image */
162 reg = <0x00580000 0x00400000>;
163 label = "SPI Flash Compressed RFSImage";
164 };
165
166 partition@980000 {
167 /* 6.5MB for JFFS2 based RFS */
168 reg = <0x00980000 0x00680000>;
169 label = "SPI Flash JFFS2 RFS";
170 };
171 };
172 };
173
174 usb@22000 {
175 phy_type = "utmi";
176 };
177
178 mdio@24000 {
179 phy0: ethernet-phy@0 {
180 interrupt-parent = <&mpic>;
181 interrupts = <3 1>;
182 reg = <0x1>;
183 };
184
185 phy1: ethernet-phy@1 {
186 interrupt-parent = <&mpic>;
187 interrupts = <2 1>;
188 reg = <0x0>;
189 };
190
191 phy2: ethernet-phy@2 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x2>;
195 };
196 };
197
198 enet0: ethernet@b0000 {
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 enet1: ethernet@b1000 {
204 phy-handle = <&phy1>;
205 tbi-handle = <&tbi0>;
206 phy-connection-type = "sgmii";
207 };
208
209 enet2: ethernet@b2000 {
210 phy-handle = <&phy2>;
211 tbi-handle = <&tbi1>;
212 phy-connection-type = "sgmii";
213 };
214 }; 32 };
215 33
216 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
35 reg = <0 0xffe09000 0 0x1000>;
217 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 36 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
218 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 37 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
219 pcie@0 { 38 pcie@0 {
220 reg = <0x0 0x0 0x0 0x0 0x0>;
221 #interrupt-cells = <1>;
222 #size-cells = <2>;
223 #address-cells = <3>;
224 device_type = "pci";
225 interrupt-parent = <&mpic>;
226 interrupts = <16 2>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x4 0x1
231 0000 0x0 0x0 0x2 &mpic 0x5 0x1
232 0000 0x0 0x0 0x3 &mpic 0x6 0x1
233 0000 0x0 0x0 0x4 &mpic 0x7 0x1
234 >;
235
236 ranges = <0x2000000 0x0 0xa0000000 39 ranges = <0x2000000 0x0 0xa0000000
237 0x2000000 0x0 0xa0000000 40 0x2000000 0x0 0xa0000000
238 0x0 0x20000000 41 0x0 0x20000000
@@ -244,24 +47,10 @@
244 }; 47 };
245 48
246 pci1: pcie@ffe0a000 { 49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
247 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
248 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
249 pcie@0 { 53 pcie@0 {
250 reg = <0x0 0x0 0x0 0x0 0x0>;
251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
254 device_type = "pci";
255 interrupt-parent = <&mpic>;
256 interrupts = <16 2>;
257 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
258 interrupt-map = <
259 /* IDSEL 0x0 */
260 0000 0x0 0x0 0x1 &mpic 0x4 0x1
261 0000 0x0 0x0 0x2 &mpic 0x5 0x1
262 0000 0x0 0x0 0x3 &mpic 0x6 0x1
263 0000 0x0 0x0 0x4 &mpic 0x7 0x1
264 >;
265 ranges = <0x2000000 0x0 0x80000000 54 ranges = <0x2000000 0x0 0x80000000
266 0x2000000 0x0 0x80000000 55 0x2000000 0x0 0x80000000
267 0x0 0x20000000 56 0x0 0x20000000
@@ -272,3 +61,6 @@
272 }; 61 };
273 }; 62 };
274}; 63};
64
65/include/ "p1010rdb.dtsi"
66/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
new file mode 100644
index 00000000000..d4c4a773028
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -0,0 +1,234 @@
1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_ifc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x2000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@40000 {
45 /* 256KB for DTB Image */
46 reg = <0x00040000 0x00040000>;
47 label = "NOR DTB Image";
48 };
49
50 partition@80000 {
51 /* 7 MB for Linux Kernel Image */
52 reg = <0x00080000 0x00700000>;
53 label = "NOR Linux Kernel Image";
54 };
55
56 partition@800000 {
57 /* 20MB for JFFS2 based Root file System */
58 reg = <0x00800000 0x01400000>;
59 label = "NOR JFFS2 Root File System";
60 };
61
62 partition@1f00000 {
63 /* This location must not be altered */
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
66 reg = <0x01f00000 0x00100000>;
67 label = "NOR U-Boot Image";
68 read-only;
69 };
70 };
71
72 nand@1,0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,ifc-nand";
76 reg = <0x1 0x0 0x10000>;
77
78 partition@0 {
79 /* This location must not be altered */
80 /* 1MB for u-boot Bootloader Image */
81 reg = <0x0 0x00100000>;
82 label = "NAND U-Boot Image";
83 read-only;
84 };
85
86 partition@100000 {
87 /* 1MB for DTB Image */
88 reg = <0x00100000 0x00100000>;
89 label = "NAND DTB Image";
90 };
91
92 partition@200000 {
93 /* 4MB for Linux Kernel Image */
94 reg = <0x00200000 0x00400000>;
95 label = "NAND Linux Kernel Image";
96 };
97
98 partition@600000 {
99 /* 4MB for Compressed Root file System Image */
100 reg = <0x00600000 0x00400000>;
101 label = "NAND Compressed RFS Image";
102 };
103
104 partition@a00000 {
105 /* 15MB for JFFS2 based Root file System */
106 reg = <0x00a00000 0x00f00000>;
107 label = "NAND JFFS2 Root File System";
108 };
109
110 partition@1900000 {
111 /* 7MB for User Area */
112 reg = <0x01900000 0x00700000>;
113 label = "NAND User area";
114 };
115 };
116
117 cpld@3,0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,p1010rdb-cpld";
121 reg = <0x3 0x0 0x0000020>;
122 bank-width = <1>;
123 device-width = <1>;
124 };
125};
126
127&board_soc {
128 i2c@3000 {
129 rtc@68 {
130 compatible = "pericom,pt7c4338";
131 reg = <0x68>;
132 };
133 };
134
135 spi@7000 {
136 flash@0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "spansion,s25sl12801";
140 reg = <0>;
141 spi-max-frequency = <50000000>;
142
143 partition@0 {
144 /* 1MB for u-boot Bootloader Image */
145 /* 1MB for Environment */
146 reg = <0x0 0x00100000>;
147 label = "SPI Flash U-Boot Image";
148 read-only;
149 };
150
151 partition@100000 {
152 /* 512KB for DTB Image */
153 reg = <0x00100000 0x00080000>;
154 label = "SPI Flash DTB Image";
155 };
156
157 partition@180000 {
158 /* 4MB for Linux Kernel Image */
159 reg = <0x00180000 0x00400000>;
160 label = "SPI Flash Linux Kernel Image";
161 };
162
163 partition@580000 {
164 /* 4MB for Compressed RFS Image */
165 reg = <0x00580000 0x00400000>;
166 label = "SPI Flash Compressed RFSImage";
167 };
168
169 partition@980000 {
170 /* 6.5MB for JFFS2 based RFS */
171 reg = <0x00980000 0x00680000>;
172 label = "SPI Flash JFFS2 RFS";
173 };
174 };
175 };
176
177 usb@22000 {
178 phy_type = "utmi";
179 dr_mode = "host";
180 };
181
182 mdio@24000 {
183 phy0: ethernet-phy@0 {
184 interrupts = <3 1 0 0>;
185 reg = <0x1>;
186 };
187
188 phy1: ethernet-phy@1 {
189 interrupts = <2 1 0 0>;
190 reg = <0x0>;
191 };
192
193 phy2: ethernet-phy@2 {
194 interrupts = <2 1 0 0>;
195 reg = <0x2>;
196 };
197
198 tbi-phy@3 {
199 device-type = "tbi-phy";
200 reg = <0x3>;
201 };
202 };
203
204 mdio@25000 {
205 tbi0: tbi-phy@11 {
206 reg = <0x11>;
207 device_type = "tbi-phy";
208 };
209 };
210
211 mdio@26000 {
212 tbi1: tbi-phy@11 {
213 reg = <0x11>;
214 device_type = "tbi-phy";
215 };
216 };
217
218 enet0: ethernet@b0000 {
219 phy-handle = <&phy0>;
220 phy-connection-type = "rgmii-id";
221 };
222
223 enet1: ethernet@b1000 {
224 phy-handle = <&phy1>;
225 tbi-handle = <&tbi0>;
226 phy-connection-type = "sgmii";
227 };
228
229 enet2: ethernet@b2000 {
230 phy-handle = <&phy2>;
231 tbi-handle = <&tbi1>;
232 phy-connection-type = "sgmii";
233 };
234};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/p1010rdb_36b.dts
new file mode 100644
index 00000000000..64776f4a465
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_36b.dts
@@ -0,0 +1,89 @@
1/*
2 * P1010 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1010si-pre.dtsi"
36
37/ {
38 model = "fsl,P1010RDB";
39 compatible = "fsl,P1010RDB";
40
41 memory {
42 device_type = "memory";
43 };
44
45 board_ifc: ifc: ifc@fffe1e000 {
46 /* NOR, NAND Flashes and CPLD on board */
47 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x3 0x0 0xf 0xffb00000 0x00000020>;
50 reg = <0xf 0xffe1e000 0 0x2000>;
51 };
52
53 board_soc: soc: soc@fffe00000 {
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@fffe09000 {
58 reg = <0xf 0xffe09000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xc0000000
63 0x2000000 0x0 0xc0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@fffe0a000 {
73 reg = <0xf 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0xc0000000
78 0x2000000 0x0 0xc0000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86};
87
88/include/ "p1010rdb.dtsi"
89/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
deleted file mode 100644
index cabe0a453ae..00000000000
--- a/arch/powerpc/boot/dts/p1010si.dtsi
+++ /dev/null
@@ -1,374 +0,0 @@
1/*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
28
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
37
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
45
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
51
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
58
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
65
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
76
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
97
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
117
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
126
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
134
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
142
143 can0: can@1c000 {
144 compatible = "fsl,p1010-flexcan";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 };
149
150 can1: can@1d000 {
151 compatible = "fsl,p1010-flexcan";
152 reg = <0x1d000 0x1000>;
153 interrupts = <61 0x2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 L2: l2-cache-controller@20000 {
158 compatible = "fsl,p1010-l2-cache-controller",
159 "fsl,p1014-l2-cache-controller";
160 reg = <0x20000 0x1000>;
161 cache-line-size = <32>; // 32 bytes
162 cache-size = <0x40000>; // L2,256K
163 interrupt-parent = <&mpic>;
164 interrupts = <16 2>;
165 };
166
167 dma@21300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
171 reg = <0x21300 0x4>;
172 ranges = <0x0 0x21100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
176 reg = <0x0 0x80>;
177 cell-index = <0>;
178 interrupt-parent = <&mpic>;
179 interrupts = <20 2>;
180 };
181 dma-channel@80 {
182 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
183 reg = <0x80 0x80>;
184 cell-index = <1>;
185 interrupt-parent = <&mpic>;
186 interrupts = <21 2>;
187 };
188 dma-channel@100 {
189 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
190 reg = <0x100 0x80>;
191 cell-index = <2>;
192 interrupt-parent = <&mpic>;
193 interrupts = <22 2>;
194 };
195 dma-channel@180 {
196 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
203
204 usb@22000 {
205 compatible = "fsl-usb2-dr";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 dr_mode = "host";
212 };
213
214 mdio@24000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,etsec2-mdio";
218 reg = <0x24000 0x1000 0xb0030 0x4>;
219 };
220
221 mdio@25000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,etsec2-tbi";
225 reg = <0x25000 0x1000 0xb1030 0x4>;
226 tbi0: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
231
232 mdio@26000 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,etsec2-tbi";
236 reg = <0x26000 0x1000 0xb1030 0x4>;
237 tbi1: tbi-phy@11 {
238 reg = <0x11>;
239 device_type = "tbi-phy";
240 };
241 };
242
243 sdhci@2e000 {
244 compatible = "fsl,esdhc";
245 reg = <0x2e000 0x1000>;
246 interrupts = <72 0x8>;
247 interrupt-parent = <&mpic>;
248 /* Filled in by U-Boot */
249 clock-frequency = <0>;
250 fsl,sdhci-auto-cmd12;
251 };
252
253 enet0: ethernet@b0000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 device_type = "network";
257 model = "eTSEC";
258 compatible = "fsl,etsec2";
259 fsl,num_rx_queues = <0x8>;
260 fsl,num_tx_queues = <0x8>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupt-parent = <&mpic>;
263
264 queue-group@0 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 reg = <0xb0000 0x1000>;
268 fsl,rx-bit-map = <0xff>;
269 fsl,tx-bit-map = <0xff>;
270 interrupts = <29 2 30 2 34 2>;
271 };
272
273 };
274
275 enet1: ethernet@b1000 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 device_type = "network";
279 model = "eTSEC";
280 compatible = "fsl,etsec2";
281 fsl,num_rx_queues = <0x8>;
282 fsl,num_tx_queues = <0x8>;
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 interrupt-parent = <&mpic>;
285
286 queue-group@0 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <0xb1000 0x1000>;
290 fsl,rx-bit-map = <0xff>;
291 fsl,tx-bit-map = <0xff>;
292 interrupts = <35 2 36 2 40 2>;
293 };
294
295 };
296
297 enet2: ethernet@b2000 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 device_type = "network";
301 model = "eTSEC";
302 compatible = "fsl,etsec2";
303 fsl,num_rx_queues = <0x8>;
304 fsl,num_tx_queues = <0x8>;
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 interrupt-parent = <&mpic>;
307
308 queue-group@0 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 reg = <0xb2000 0x1000>;
312 fsl,rx-bit-map = <0xff>;
313 fsl,tx-bit-map = <0xff>;
314 interrupts = <31 2 32 2 33 2>;
315 };
316
317 };
318
319 mpic: pic@40000 {
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <0x40000 0x40000>;
324 compatible = "chrp,open-pic";
325 device_type = "open-pic";
326 };
327
328 msi@41600 {
329 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
330 reg = <0x41600 0x80>;
331 msi-available-ranges = <0 0x100>;
332 interrupts = <
333 0xe0 0
334 0xe1 0
335 0xe2 0
336 0xe3 0
337 0xe4 0
338 0xe5 0
339 0xe6 0
340 0xe7 0>;
341 interrupt-parent = <&mpic>;
342 };
343
344 global-utilities@e0000 { //global utilities block
345 compatible = "fsl,p1010-guts";
346 reg = <0xe0000 0x1000>;
347 fsl,has-rstcr;
348 };
349 };
350
351 pci0: pcie@ffe09000 {
352 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
353 device_type = "pci";
354 #size-cells = <2>;
355 #address-cells = <3>;
356 reg = <0 0xffe09000 0 0x1000>;
357 bus-range = <0 255>;
358 clock-frequency = <33333333>;
359 interrupt-parent = <&mpic>;
360 interrupts = <16 2>;
361 };
362
363 pci1: pcie@ffe0a000 {
364 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
365 device_type = "pci";
366 #size-cells = <2>;
367 #address-cells = <3>;
368 reg = <0 0xffe0a000 0 0x1000>;
369 bus-range = <0 255>;
370 clock-frequency = <33333333>;
371 interrupt-parent = <&mpic>;
372 interrupts = <16 2>;
373 };
374};
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index d6a8ae45813..518bf99b1f5 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,267 +9,33 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1020si.dtsi" 12/include/ "fsl/p1020si-pre.dtsi"
13
14/ { 13/ {
15 model = "fsl,P1020RDB"; 14 model = "fsl,P1020RDB";
16 compatible = "fsl,P1020RDB"; 15 compatible = "fsl,P1020RDB";
17 16
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory { 17 memory {
29 device_type = "memory"; 18 device_type = "memory";
30 }; 19 };
31 20
32 localbus@ffe05000 { 21 board_lbc: lbc: localbus@ffe05000 {
22 reg = <0 0xffe05000 0 0x1000>;
33 23
34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 25 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
36 0x1 0x0 0x0 0xffa00000 0x00040000 26 0x1 0x0 0x0 0xffa00000 0x00040000
37 0x2 0x0 0x0 0xffb00000 0x00020000>; 27 0x2 0x0 0x0 0xffb00000 0x00020000>;
38
39 nor@0,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x1000000>;
44 bank-width = <2>;
45 device-width = <1>;
46
47 partition@0 {
48 /* This location must not be altered */
49 /* 256KB for Vitesse 7385 Switch firmware */
50 reg = <0x0 0x00040000>;
51 label = "NOR (RO) Vitesse-7385 Firmware";
52 read-only;
53 };
54
55 partition@40000 {
56 /* 256KB for DTB Image */
57 reg = <0x00040000 0x00040000>;
58 label = "NOR (RO) DTB Image";
59 read-only;
60 };
61
62 partition@80000 {
63 /* 3.5 MB for Linux Kernel Image */
64 reg = <0x00080000 0x00380000>;
65 label = "NOR (RO) Linux Kernel Image";
66 read-only;
67 };
68
69 partition@400000 {
70 /* 11MB for JFFS2 based Root file System */
71 reg = <0x00400000 0x00b00000>;
72 label = "NOR (RW) JFFS2 Root File System";
73 };
74
75 partition@f00000 {
76 /* This location must not be altered */
77 /* 512KB for u-boot Bootloader Image */
78 /* 512KB for u-boot Environment Variables */
79 reg = <0x00f00000 0x00100000>;
80 label = "NOR (RO) U-Boot Image";
81 read-only;
82 };
83 };
84
85 nand@1,0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "fsl,p1020-fcm-nand",
89 "fsl,elbc-fcm-nand";
90 reg = <0x1 0x0 0x40000>;
91
92 partition@0 {
93 /* This location must not be altered */
94 /* 1MB for u-boot Bootloader Image */
95 reg = <0x0 0x00100000>;
96 label = "NAND (RO) U-Boot Image";
97 read-only;
98 };
99
100 partition@100000 {
101 /* 1MB for DTB Image */
102 reg = <0x00100000 0x00100000>;
103 label = "NAND (RO) DTB Image";
104 read-only;
105 };
106
107 partition@200000 {
108 /* 4MB for Linux Kernel Image */
109 reg = <0x00200000 0x00400000>;
110 label = "NAND (RO) Linux Kernel Image";
111 read-only;
112 };
113
114 partition@600000 {
115 /* 4MB for Compressed Root file System Image */
116 reg = <0x00600000 0x00400000>;
117 label = "NAND (RO) Compressed RFS Image";
118 read-only;
119 };
120
121 partition@a00000 {
122 /* 7MB for JFFS2 based Root file System */
123 reg = <0x00a00000 0x00700000>;
124 label = "NAND (RW) JFFS2 Root File System";
125 };
126
127 partition@1100000 {
128 /* 15MB for JFFS2 based Root file System */
129 reg = <0x01100000 0x00f00000>;
130 label = "NAND (RW) Writable User area";
131 };
132 };
133
134 L2switch@2,0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "vitesse-7385";
138 reg = <0x2 0x0 0x20000>;
139 };
140
141 }; 28 };
142 29
143 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
144 i2c@3000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
145 rtc@68 {
146 compatible = "dallas,ds1339";
147 reg = <0x68>;
148 };
149 };
150
151 spi@7000 {
152
153 fsl_m25p80@0 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "fsl,espi-flash";
157 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>;
161 mode = <0>;
162
163 partition@0 {
164 /* 512KB for u-boot Bootloader Image */
165 reg = <0x0 0x00080000>;
166 label = "SPI (RO) U-Boot Image";
167 read-only;
168 };
169
170 partition@80000 {
171 /* 512KB for DTB Image */
172 reg = <0x00080000 0x00080000>;
173 label = "SPI (RO) DTB Image";
174 read-only;
175 };
176
177 partition@100000 {
178 /* 4MB for Linux Kernel Image */
179 reg = <0x00100000 0x00400000>;
180 label = "SPI (RO) Linux Kernel Image";
181 read-only;
182 };
183
184 partition@500000 {
185 /* 4MB for Compressed RFS Image */
186 reg = <0x00500000 0x00400000>;
187 label = "SPI (RO) Compressed RFS Image";
188 read-only;
189 };
190
191 partition@900000 {
192 /* 7MB for JFFS2 based RFS */
193 reg = <0x00900000 0x00700000>;
194 label = "SPI (RW) JFFS2 RFS";
195 };
196 };
197 };
198
199 mdio@24000 {
200
201 phy0: ethernet-phy@0 {
202 interrupt-parent = <&mpic>;
203 interrupts = <3 1>;
204 reg = <0x0>;
205 };
206
207 phy1: ethernet-phy@1 {
208 interrupt-parent = <&mpic>;
209 interrupts = <2 1>;
210 reg = <0x1>;
211 };
212 };
213
214 mdio@25000 {
215
216 tbi0: tbi-phy@11 {
217 reg = <0x11>;
218 device_type = "tbi-phy";
219 };
220 };
221
222 enet0: ethernet@b0000 {
223 fixed-link = <1 1 1000 0 0>;
224 phy-connection-type = "rgmii-id";
225
226 };
227
228 enet1: ethernet@b1000 {
229 phy-handle = <&phy0>;
230 tbi-handle = <&tbi0>;
231 phy-connection-type = "sgmii";
232
233 };
234
235 enet2: ethernet@b2000 {
236 phy-handle = <&phy1>;
237 phy-connection-type = "rgmii-id";
238
239 };
240
241 usb@22000 {
242 phy_type = "ulpi";
243 };
244
245 /* USB2 is shared with localbus, so it must be disabled
246 by default. We can't put 'status = "disabled";' here
247 since U-Boot doesn't clear the status property when
248 it enables USB2. OTOH, U-Boot does create a new node
249 when there isn't any. So, just comment it out.
250 usb@23000 {
251 phy_type = "ulpi";
252 };
253 */
254
255 }; 32 };
256 33
257 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
258 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 35 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
259 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 36 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 37 reg = <0 0xffe09000 0 0x1000>;
261 interrupt-map = <
262 /* IDSEL 0x0 */
263 0000 0x0 0x0 0x1 &mpic 0x4 0x1
264 0000 0x0 0x0 0x2 &mpic 0x5 0x1
265 0000 0x0 0x0 0x3 &mpic 0x6 0x1
266 0000 0x0 0x0 0x4 &mpic 0x7 0x1
267 >;
268 pcie@0 { 38 pcie@0 {
269 reg = <0x0 0x0 0x0 0x0 0x0>;
270 #size-cells = <2>;
271 #address-cells = <3>;
272 device_type = "pci";
273 ranges = <0x2000000 0x0 0xa0000000 39 ranges = <0x2000000 0x0 0xa0000000
274 0x2000000 0x0 0xa0000000 40 0x2000000 0x0 0xa0000000
275 0x0 0x20000000 41 0x0 0x20000000
@@ -281,21 +47,10 @@
281 }; 47 };
282 48
283 pci1: pcie@ffe0a000 { 49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
284 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
285 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
286 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
287 interrupt-map = <
288 /* IDSEL 0x0 */
289 0000 0x0 0x0 0x1 &mpic 0x0 0x1
290 0000 0x0 0x0 0x2 &mpic 0x1 0x1
291 0000 0x0 0x0 0x3 &mpic 0x2 0x1
292 0000 0x0 0x0 0x4 &mpic 0x3 0x1
293 >;
294 pcie@0 { 53 pcie@0 {
295 reg = <0x0 0x0 0x0 0x0 0x0>;
296 #size-cells = <2>;
297 #address-cells = <3>;
298 device_type = "pci";
299 ranges = <0x2000000 0x0 0x80000000 54 ranges = <0x2000000 0x0 0x80000000
300 0x2000000 0x0 0x80000000 55 0x2000000 0x0 0x80000000
301 0x0 0x20000000 56 0x0 0x20000000
@@ -306,3 +61,6 @@
306 }; 61 };
307 }; 62 };
308}; 63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb.dtsi b/arch/powerpc/boot/dts/p1020rdb.dtsi
new file mode 100644
index 00000000000..b5bd86f4baf
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dtsi
@@ -0,0 +1,247 @@
1/*
2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR (RO) DTB Image";
56 read-only;
57 };
58
59 partition@80000 {
60 /* 3.5 MB for Linux Kernel Image */
61 reg = <0x00080000 0x00380000>;
62 label = "NOR (RO) Linux Kernel Image";
63 read-only;
64 };
65
66 partition@400000 {
67 /* 11MB for JFFS2 based Root file System */
68 reg = <0x00400000 0x00b00000>;
69 label = "NOR (RW) JFFS2 Root File System";
70 };
71
72 partition@f00000 {
73 /* This location must not be altered */
74 /* 512KB for u-boot Bootloader Image */
75 /* 512KB for u-boot Environment Variables */
76 reg = <0x00f00000 0x00100000>;
77 label = "NOR (RO) U-Boot Image";
78 read-only;
79 };
80 };
81
82 nand@1,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "fsl,p1020-fcm-nand",
86 "fsl,elbc-fcm-nand";
87 reg = <0x1 0x0 0x40000>;
88
89 partition@0 {
90 /* This location must not be altered */
91 /* 1MB for u-boot Bootloader Image */
92 reg = <0x0 0x00100000>;
93 label = "NAND (RO) U-Boot Image";
94 read-only;
95 };
96
97 partition@100000 {
98 /* 1MB for DTB Image */
99 reg = <0x00100000 0x00100000>;
100 label = "NAND (RO) DTB Image";
101 read-only;
102 };
103
104 partition@200000 {
105 /* 4MB for Linux Kernel Image */
106 reg = <0x00200000 0x00400000>;
107 label = "NAND (RO) Linux Kernel Image";
108 read-only;
109 };
110
111 partition@600000 {
112 /* 4MB for Compressed Root file System Image */
113 reg = <0x00600000 0x00400000>;
114 label = "NAND (RO) Compressed RFS Image";
115 read-only;
116 };
117
118 partition@a00000 {
119 /* 7MB for JFFS2 based Root file System */
120 reg = <0x00a00000 0x00700000>;
121 label = "NAND (RW) JFFS2 Root File System";
122 };
123
124 partition@1100000 {
125 /* 15MB for JFFS2 based Root file System */
126 reg = <0x01100000 0x00f00000>;
127 label = "NAND (RW) Writable User area";
128 };
129 };
130
131 L2switch@2,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "vitesse-7385";
135 reg = <0x2 0x0 0x20000>;
136 };
137};
138
139&board_soc {
140 i2c@3000 {
141 rtc@68 {
142 compatible = "dallas,ds1339";
143 reg = <0x68>;
144 };
145 };
146
147 spi@7000 {
148 flash@0 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "spansion,s25sl12801";
152 reg = <0>;
153 spi-max-frequency = <40000000>; /* input clock */
154
155 partition@u-boot {
156 /* 512KB for u-boot Bootloader Image */
157 reg = <0x0 0x00080000>;
158 label = "u-boot";
159 read-only;
160 };
161
162 partition@dtb {
163 /* 512KB for DTB Image */
164 reg = <0x00080000 0x00080000>;
165 label = "dtb";
166 read-only;
167 };
168
169 partition@kernel {
170 /* 4MB for Linux Kernel Image */
171 reg = <0x00100000 0x00400000>;
172 label = "kernel";
173 read-only;
174 };
175
176 partition@fs {
177 /* 4MB for Compressed RFS Image */
178 reg = <0x00500000 0x00400000>;
179 label = "file system";
180 read-only;
181 };
182
183 partition@jffs-fs {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "file system jffs2";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 /* USB2 is shared with localbus, so it must be disabled
196 by default. We can't put 'status = "disabled";' here
197 since U-Boot doesn't clear the status property when
198 it enables USB2. OTOH, U-Boot does create a new node
199 when there isn't any. So, just comment it out.
200 usb@23000 {
201 phy_type = "ulpi";
202 };
203 */
204
205 mdio@24000 {
206 phy0: ethernet-phy@0 {
207 interrupt-parent = <&mpic>;
208 interrupts = <3 1>;
209 reg = <0x0>;
210 };
211
212 phy1: ethernet-phy@1 {
213 interrupt-parent = <&mpic>;
214 interrupts = <2 1>;
215 reg = <0x1>;
216 };
217
218 tbi-phy@2 {
219 device_type = "tbi-phy";
220 reg = <0x2>;
221 };
222 };
223
224 mdio@25000 {
225 tbi0: tbi-phy@11 {
226 reg = <0x11>;
227 device_type = "tbi-phy";
228 };
229 };
230
231 enet0: ethernet@b0000 {
232 fixed-link = <1 1 1000 0 0>;
233 phy-connection-type = "rgmii-id";
234
235 };
236
237 enet1: ethernet@b1000 {
238 phy-handle = <&phy0>;
239 tbi-handle = <&tbi0>;
240 phy-connection-type = "sgmii";
241 };
242
243 enet2: ethernet@b2000 {
244 phy-handle = <&phy1>;
245 phy-connection-type = "rgmii-id";
246 };
247};
diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts b/arch/powerpc/boot/dts/p1020rdb_36b.dts
new file mode 100644
index 00000000000..bdbdb6097e5
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_36b.dts
@@ -0,0 +1,66 @@
1/*
2 * P1020 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/p1020si-pre.dtsi"
13/ {
14 model = "fsl,P1020RDB";
15 compatible = "fsl,P1020RDB";
16
17 memory {
18 device_type = "memory";
19 };
20
21 board_lbc: lbc: localbus@fffe05000 {
22 reg = <0xf 0xffe05000 0 0x1000>;
23
24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
25 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
26 0x1 0x0 0xf 0xffa00000 0x00040000
27 0x2 0x0 0xf 0xffb00000 0x00020000>;
28 };
29
30 board_soc: soc: soc@fffe00000 {
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
32 };
33
34 pci0: pcie@fffe09000 {
35 reg = <0xf 0xffe09000 0 0x1000>;
36 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
37 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
38 pcie@0 {
39 ranges = <0x2000000 0x0 0xc0000000
40 0x2000000 0x0 0xc0000000
41 0x0 0x20000000
42
43 0x1000000 0x0 0x0
44 0x1000000 0x0 0x0
45 0x0 0x100000>;
46 };
47 };
48
49 pci1: pcie@fffe0a000 {
50 reg = <0xf 0xffe0a000 0 0x1000>;
51 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
52 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
53 pcie@0 {
54 ranges = <0x2000000 0x0 0x80000000
55 0x2000000 0x0 0x80000000
56 0x0 0x20000000
57
58 0x1000000 0x0 0x0
59 0x1000000 0x0 0x0
60 0x0 0x100000>;
61 };
62 };
63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
index f0bf7f42f09..41b4585c5da 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -16,7 +16,7 @@
16 * option) any later version. 16 * option) any later version.
17 */ 17 */
18 18
19/include/ "p1020si.dtsi" 19/include/ "p1020rdb.dts"
20 20
21/ { 21/ {
22 model = "fsl,P1020RDB"; 22 model = "fsl,P1020RDB";
@@ -32,7 +32,7 @@
32 32
33 cpus { 33 cpus {
34 PowerPC,P1020@1 { 34 PowerPC,P1020@1 {
35 status = "disabled"; 35 status = "disabled";
36 }; 36 };
37 }; 37 };
38 38
@@ -45,169 +45,19 @@
45 }; 45 };
46 46
47 soc@ffe00000 { 47 soc@ffe00000 {
48 i2c@3000 {
49 rtc@68 {
50 compatible = "dallas,ds1339";
51 reg = <0x68>;
52 };
53 };
54
55 serial1: serial@4600 { 48 serial1: serial@4600 {
56 status = "disabled"; 49 status = "disabled";
57 }; 50 };
58 51
59 spi@7000 {
60 fsl_m25p80@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,espi-flash";
64 reg = <0>;
65 linux,modalias = "fsl_m25p80";
66 spi-max-frequency = <40000000>;
67
68 partition@0 {
69 /* 512KB for u-boot Bootloader Image */
70 reg = <0x0 0x00080000>;
71 label = "SPI (RO) U-Boot Image";
72 read-only;
73 };
74
75 partition@80000 {
76 /* 512KB for DTB Image */
77 reg = <0x00080000 0x00080000>;
78 label = "SPI (RO) DTB Image";
79 read-only;
80 };
81
82 partition@100000 {
83 /* 4MB for Linux Kernel Image */
84 reg = <0x00100000 0x00400000>;
85 label = "SPI (RO) Linux Kernel Image";
86 read-only;
87 };
88
89 partition@500000 {
90 /* 4MB for Compressed RFS Image */
91 reg = <0x00500000 0x00400000>;
92 label = "SPI (RO) Compressed RFS Image";
93 read-only;
94 };
95
96 partition@900000 {
97 /* 7MB for JFFS2 based RFS */
98 reg = <0x00900000 0x00700000>;
99 label = "SPI (RW) JFFS2 RFS";
100 };
101 };
102 };
103
104 mdio@24000 {
105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
107 interrupts = <3 1>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupt-parent = <&mpic>;
112 interrupts = <2 1>;
113 reg = <0x1>;
114 };
115 };
116
117 mdio@25000 {
118 tbi0: tbi-phy@11 {
119 reg = <0x11>;
120 device_type = "tbi-phy";
121 };
122 };
123
124 enet0: ethernet@b0000 { 52 enet0: ethernet@b0000 {
125 status = "disabled"; 53 status = "disabled";
126 }; 54 };
127 55
128 enet1: ethernet@b1000 {
129 phy-handle = <&phy0>;
130 tbi-handle = <&tbi0>;
131 phy-connection-type = "sgmii";
132 };
133
134 enet2: ethernet@b2000 {
135 phy-handle = <&phy1>;
136 phy-connection-type = "rgmii-id";
137 };
138
139 usb@22000 {
140 phy_type = "ulpi";
141 };
142
143 /* USB2 is shared with localbus, so it must be disabled
144 by default. We can't put 'status = "disabled";' here
145 since U-Boot doesn't clear the status property when
146 it enables USB2. OTOH, U-Boot does create a new node
147 when there isn't any. So, just comment it out.
148 usb@23000 {
149 phy_type = "ulpi";
150 };
151 */
152
153 mpic: pic@40000 { 56 mpic: pic@40000 {
154 protected-sources = < 57 protected-sources = <
155 42 29 30 34 /* serial1, enet0-queue-group0 */ 58 42 29 30 34 /* serial1, enet0-queue-group0 */
156 17 18 24 45 /* enet0-queue-group1, crypto */ 59 17 18 24 45 /* enet0-queue-group1, crypto */
157 >; 60 >;
158 }; 61 };
159
160 };
161
162 pci0: pcie@ffe09000 {
163 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
164 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
165 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
166 interrupt-map = <
167 /* IDSEL 0x0 */
168 0000 0x0 0x0 0x1 &mpic 0x4 0x1
169 0000 0x0 0x0 0x2 &mpic 0x5 0x1
170 0000 0x0 0x0 0x3 &mpic 0x6 0x1
171 0000 0x0 0x0 0x4 &mpic 0x7 0x1
172 >;
173 pcie@0 {
174 reg = <0x0 0x0 0x0 0x0 0x0>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 device_type = "pci";
178 ranges = <0x2000000 0x0 0xa0000000
179 0x2000000 0x0 0xa0000000
180 0x0 0x20000000
181
182 0x1000000 0x0 0x0
183 0x1000000 0x0 0x0
184 0x0 0x100000>;
185 };
186 };
187
188 pci1: pcie@ffe0a000 {
189 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
190 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
191 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
192 interrupt-map = <
193 /* IDSEL 0x0 */
194 0000 0x0 0x0 0x1 &mpic 0x0 0x1
195 0000 0x0 0x0 0x2 &mpic 0x1 0x1
196 0000 0x0 0x0 0x3 &mpic 0x2 0x1
197 0000 0x0 0x0 0x4 &mpic 0x3 0x1
198 >;
199 pcie@0 {
200 reg = <0x0 0x0 0x0 0x0 0x0>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 device_type = "pci";
204 ranges = <0x2000000 0x0 0x80000000
205 0x2000000 0x0 0x80000000
206 0x0 0x20000000
207
208 0x1000000 0x0 0x0
209 0x1000000 0x0 0x0
210 0x0 0x100000>;
211 };
212 }; 62 };
213}; 63};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
index 6ec02204a44..51745382188 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
@@ -15,7 +15,7 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/include/ "p1020si.dtsi" 18/include/ "p1020rdb.dts"
19 19
20/ { 20/ {
21 model = "fsl,P1020RDB"; 21 model = "fsl,P1020RDB";
@@ -28,7 +28,7 @@
28 28
29 cpus { 29 cpus {
30 PowerPC,P1020@0 { 30 PowerPC,P1020@0 {
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
33 }; 33 };
34 34
@@ -85,12 +85,6 @@
85 status = "disabled"; 85 status = "disabled";
86 }; 86 };
87 87
88 enet0: ethernet@b0000 {
89 fixed-link = <1 1 1000 0 0>;
90 phy-connection-type = "rgmii-id";
91
92 };
93
94 enet1: ethernet@b1000 { 88 enet1: ethernet@b1000 {
95 status = "disabled"; 89 status = "disabled";
96 }; 90 };
@@ -135,7 +129,6 @@
135 global-utilities@e0000 { //global utilities block 129 global-utilities@e0000 { //global utilities block
136 status = "disabled"; 130 status = "disabled";
137 }; 131 };
138
139 }; 132 };
140 133
141 pci0: pcie@ffe09000 { 134 pci0: pcie@ffe09000 {
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
deleted file mode 100644
index 5c5acb66c3f..00000000000
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * P1020si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P1020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p1020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <16 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p1020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <16 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 gpio: gpio-controller@f000 {
126 #gpio-cells = <2>;
127 compatible = "fsl,mpc8572-gpio";
128 reg = <0xf000 0x100>;
129 interrupts = <47 0x2>;
130 interrupt-parent = <&mpic>;
131 gpio-controller;
132 };
133
134 L2: l2-cache-controller@20000 {
135 compatible = "fsl,p1020-l2-cache-controller";
136 reg = <0x20000 0x1000>;
137 cache-line-size = <32>; // 32 bytes
138 cache-size = <0x40000>; // L2,256K
139 interrupt-parent = <&mpic>;
140 interrupts = <16 2>;
141 };
142
143 dma@21300 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,eloplus-dma";
147 reg = <0x21300 0x4>;
148 ranges = <0x0 0x21100 0x200>;
149 cell-index = <0>;
150 dma-channel@0 {
151 compatible = "fsl,eloplus-dma-channel";
152 reg = <0x0 0x80>;
153 cell-index = <0>;
154 interrupt-parent = <&mpic>;
155 interrupts = <20 2>;
156 };
157 dma-channel@80 {
158 compatible = "fsl,eloplus-dma-channel";
159 reg = <0x80 0x80>;
160 cell-index = <1>;
161 interrupt-parent = <&mpic>;
162 interrupts = <21 2>;
163 };
164 dma-channel@100 {
165 compatible = "fsl,eloplus-dma-channel";
166 reg = <0x100 0x80>;
167 cell-index = <2>;
168 interrupt-parent = <&mpic>;
169 interrupts = <22 2>;
170 };
171 dma-channel@180 {
172 compatible = "fsl,eloplus-dma-channel";
173 reg = <0x180 0x80>;
174 cell-index = <3>;
175 interrupt-parent = <&mpic>;
176 interrupts = <23 2>;
177 };
178 };
179
180 mdio@24000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,etsec2-mdio";
184 reg = <0x24000 0x1000 0xb0030 0x4>;
185
186 };
187
188 mdio@25000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,etsec2-tbi";
192 reg = <0x25000 0x1000 0xb1030 0x4>;
193
194 };
195
196 enet0: ethernet@b0000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "fsl,etsec2";
202 fsl,num_rx_queues = <0x8>;
203 fsl,num_tx_queues = <0x8>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupt-parent = <&mpic>;
206
207 queue-group@0 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0xb0000 0x1000>;
211 interrupts = <29 2 30 2 34 2>;
212 };
213
214 queue-group@1 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 reg = <0xb4000 0x1000>;
218 interrupts = <17 2 18 2 24 2>;
219 };
220 };
221
222 enet1: ethernet@b1000 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 device_type = "network";
226 model = "eTSEC";
227 compatible = "fsl,etsec2";
228 fsl,num_rx_queues = <0x8>;
229 fsl,num_tx_queues = <0x8>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 interrupt-parent = <&mpic>;
232
233 queue-group@0 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 reg = <0xb1000 0x1000>;
237 interrupts = <35 2 36 2 40 2>;
238 };
239
240 queue-group@1 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 reg = <0xb5000 0x1000>;
244 interrupts = <51 2 52 2 67 2>;
245 };
246 };
247
248 enet2: ethernet@b2000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "fsl,etsec2";
254 fsl,num_rx_queues = <0x8>;
255 fsl,num_tx_queues = <0x8>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupt-parent = <&mpic>;
258
259 queue-group@0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0xb2000 0x1000>;
263 interrupts = <31 2 32 2 33 2>;
264 };
265
266 queue-group@1 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb6000 0x1000>;
270 interrupts = <25 2 26 2 27 2>;
271 };
272 };
273
274 usb@22000 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "fsl-usb2-dr";
278 reg = <0x22000 0x1000>;
279 interrupt-parent = <&mpic>;
280 interrupts = <28 0x2>;
281 };
282
283 /* USB2 is shared with localbus, so it must be disabled
284 by default. We can't put 'status = "disabled";' here
285 since U-Boot doesn't clear the status property when
286 it enables USB2. OTOH, U-Boot does create a new node
287 when there isn't any. So, just comment it out.
288 usb@23000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl-usb2-dr";
292 reg = <0x23000 0x1000>;
293 interrupt-parent = <&mpic>;
294 interrupts = <46 0x2>;
295 phy_type = "ulpi";
296 };
297 */
298
299 sdhci@2e000 {
300 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
301 reg = <0x2e000 0x1000>;
302 interrupts = <72 0x2>;
303 interrupt-parent = <&mpic>;
304 /* Filled in by U-Boot */
305 clock-frequency = <0>;
306 };
307
308 crypto@30000 {
309 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
310 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
311 reg = <0x30000 0x10000>;
312 interrupts = <45 2 58 2>;
313 interrupt-parent = <&mpic>;
314 fsl,num-channels = <4>;
315 fsl,channel-fifo-len = <24>;
316 fsl,exec-units-mask = <0xbfe>;
317 fsl,descriptor-types-mask = <0x3ab0ebf>;
318 };
319
320 mpic: pic@40000 {
321 interrupt-controller;
322 #address-cells = <0>;
323 #interrupt-cells = <2>;
324 reg = <0x40000 0x40000>;
325 compatible = "chrp,open-pic";
326 device_type = "open-pic";
327 };
328
329 msi@41600 {
330 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
331 reg = <0x41600 0x80>;
332 msi-available-ranges = <0 0x100>;
333 interrupts = <
334 0xe0 0
335 0xe1 0
336 0xe2 0
337 0xe3 0
338 0xe4 0
339 0xe5 0
340 0xe6 0
341 0xe7 0>;
342 interrupt-parent = <&mpic>;
343 };
344
345 global-utilities@e0000 { //global utilities block
346 compatible = "fsl,p1020-guts","fsl,p2020-guts";
347 reg = <0xe0000 0x1000>;
348 fsl,has-rstcr;
349 };
350 };
351
352 pci0: pcie@ffe09000 {
353 compatible = "fsl,mpc8548-pcie";
354 device_type = "pci";
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,mpc8548-pcie";
367 device_type = "pci";
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
371 reg = <0 0xffe0a000 0 0x1000>;
372 bus-range = <0 255>;
373 clock-frequency = <33333333>;
374 interrupt-parent = <&mpic>;
375 interrupts = <16 2>;
376 };
377};
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index ad5b8526900..d9540791e43 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -9,53 +9,22 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/p1021si-pre.dtsi"
13/ { 13/ {
14 model = "fsl,P1021"; 14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS"; 15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 16
19 aliases { 17 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3; 18 ethernet3 = &enet3;
26 ethernet4 = &enet4; 19 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 }; 20 };
47 21
48 memory { 22 memory {
49 device_type = "memory"; 23 device_type = "memory";
50 }; 24 };
51 25
52 localbus@ffe05000 { 26 lbc: localbus@ffe05000 {
53 #address-cells = <2>; 27 reg = <0x0 0xffe05000 0x0 0x1000>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59 28
60 /* NAND Flash, BCSR, PMC0/1*/ 29 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 30 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
@@ -138,99 +107,26 @@
138 }; 107 };
139 }; 108 };
140 109
141 soc@ffe00000 { 110 soc: soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus"; 111 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>; 112 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169 113
170 i2c@3000 { 114 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 { 115 rtc@68 {
180 compatible = "dallas,ds1374"; 116 compatible = "dallas,ds1374";
181 reg = <0x68>; 117 reg = <0x68>;
182 }; 118 };
183 }; 119 };
184 120
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 { 121 spi@7000 {
217 cell-index = <0>; 122
218 #address-cells = <1>; 123 flash@0 {
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>; 124 #address-cells = <1>;
229 #size-cells = <1>; 125 #size-cells = <1>;
230 compatible = "fsl,espi-flash"; 126 compatible = "spansion,s25sl12801";
231 reg = <0>; 127 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */ 128 spi-max-frequency = <40000000>; /* input clock */
129
234 partition@u-boot { 130 partition@u-boot {
235 label = "u-boot-spi"; 131 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>; 132 reg = <0x00000000 0x00100000>;
@@ -253,237 +149,49 @@
253 }; 149 };
254 }; 150 };
255 151
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 { 152 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi"; 153 phy_type = "ulpi";
319 }; 154 };
320 155
321 mdio@24000 { 156 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 { 157 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>; 158 interrupts = <1 1 0 0>;
329 interrupts = <1 1>;
330 reg = <0x0>; 159 reg = <0x0>;
331 }; 160 };
332 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>; 162 interrupts = <2 1 0 0>;
334 interrupts = <2 1>;
335 reg = <0x1>; 163 reg = <0x1>;
336 }; 164 };
337 phy4: ethernet-phy@4 { 165 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>; 166 reg = <0x4>;
340 }; 167 };
168 tbi-phy@5 {
169 device_type = "tbi-phy";
170 reg = <0x5>;
171 };
341 }; 172 };
342 173
343 mdio@25000 { 174 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 { 175 tbi0: tbi-phy@11 {
349 reg = <0x11>; 176 reg = <0x11>;
350 device_type = "tbi-phy"; 177 device_type = "tbi-phy";
351 }; 178 };
352 }; 179 };
353 180
354 enet0: ethernet@B0000 { 181 ethernet@b0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>; 182 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id"; 183 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 }; 184 };
380 185
381 enet1: ethernet@B1000 { 186 ethernet@b1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>; 187 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>; 188 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii"; 189 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 }; 190 };
408 191
409 enet2: ethernet@B2000 { 192 ethernet@b2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>; 193 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id"; 194 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 }; 195 };
488 196
489 par_io@e0100 { 197 par_io@e0100 {
@@ -499,8 +207,7 @@
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 207 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 208 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 209 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 210 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 211 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 212 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 213 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
@@ -535,31 +242,10 @@
535 }; 242 };
536 243
537 pci0: pcie@ffe09000 { 244 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>; 245 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 246 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 247 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 { 248 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000 249 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000 250 0x2000000 0x0 0xa0000000
565 0x0 0x20000000 251 0x0 0x20000000
@@ -571,31 +257,10 @@
571 }; 257 };
572 258
573 pci1: pcie@ffe0a000 { 259 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>; 260 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 261 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 262 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 { 263 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000 264 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000 265 0x2000000 0x0 0xc0000000
601 0x0 0x20000000 266 0x0 0x20000000
@@ -606,36 +271,16 @@
606 }; 271 };
607 }; 272 };
608 273
609 qe@ffe80000 { 274 qe: qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>; 275 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>; 276 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>; 277 brg-frequency = <0>;
617 bus-frequency = <0>; 278 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620 status = "disabled"; /* no firmware loaded */ 279 status = "disabled"; /* no firmware loaded */
621 280
622 qeic: interrupt-controller@80 {
623 interrupt-controller;
624 compatible = "fsl,qe-ic";
625 #address-cells = <0>;
626 #interrupt-cells = <1>;
627 reg = <0x80 0x80>;
628 interrupts = <63 2 60 2>; //high:47 low:44
629 interrupt-parent = <&mpic>;
630 };
631
632 enet3: ucc@2000 { 281 enet3: ucc@2000 {
633 device_type = "network"; 282 device_type = "network";
634 compatible = "ucc_geth"; 283 compatible = "ucc_geth";
635 cell-index = <1>;
636 reg = <0x2000 0x200>;
637 interrupts = <32>;
638 interrupt-parent = <&qeic>;
639 local-mac-address = [ 00 00 00 00 00 00 ]; 284 local-mac-address = [ 00 00 00 00 00 00 ];
640 rx-clock-name = "clk12"; 285 rx-clock-name = "clk12";
641 tx-clock-name = "clk9"; 286 tx-clock-name = "clk9";
@@ -645,20 +290,15 @@
645 }; 290 };
646 291
647 mdio@2120 { 292 mdio@2120 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <0x2120 0x18>;
651 compatible = "fsl,ucc-mdio";
652
653 qe_phy0: ethernet-phy@0 { 293 qe_phy0: ethernet-phy@0 {
654 interrupt-parent = <&mpic>; 294 interrupt-parent = <&mpic>;
655 interrupts = <4 1>; 295 interrupts = <4 1 0 0>;
656 reg = <0x0>; 296 reg = <0x0>;
657 device_type = "ethernet-phy"; 297 device_type = "ethernet-phy";
658 }; 298 };
659 qe_phy1: ethernet-phy@03 { 299 qe_phy1: ethernet-phy@03 {
660 interrupt-parent = <&mpic>; 300 interrupt-parent = <&mpic>;
661 interrupts = <5 1>; 301 interrupts = <5 1 0 0>;
662 reg = <0x3>; 302 reg = <0x3>;
663 device_type = "ethernet-phy"; 303 device_type = "ethernet-phy";
664 }; 304 };
@@ -671,10 +311,6 @@
671 enet4: ucc@2400 { 311 enet4: ucc@2400 {
672 device_type = "network"; 312 device_type = "network";
673 compatible = "ucc_geth"; 313 compatible = "ucc_geth";
674 cell-index = <5>;
675 reg = <0x2400 0x200>;
676 interrupts = <40>;
677 interrupt-parent = <&qeic>;
678 local-mac-address = [ 00 00 00 00 00 00 ]; 314 local-mac-address = [ 00 00 00 00 00 00 ];
679 rx-clock-name = "none"; 315 rx-clock-name = "none";
680 tx-clock-name = "clk13"; 316 tx-clock-name = "clk13";
@@ -682,18 +318,7 @@
682 phy-handle = <&qe_phy1>; 318 phy-handle = <&qe_phy1>;
683 phy-connection-type = "rmii"; 319 phy-connection-type = "rmii";
684 }; 320 };
685
686 muram@10000 {
687 #address-cells = <1>;
688 #size-cells = <1>;
689 compatible = "fsl,qe-muram", "fsl,cpm-muram";
690 ranges = <0x0 0x10000 0x6000>;
691
692 data-only@0 {
693 compatible = "fsl,qe-muram-data",
694 "fsl,cpm-muram-data";
695 reg = <0x0 0x6000>;
696 };
697 };
698 }; 321 };
699}; 322};
323
324/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index b9b8719a620..ef95717db4b 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -8,57 +8,36 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/; 11/include/ "fsl/p1022si-pre.dtsi"
12/ { 12/ {
13 model = "fsl,P1022"; 13 model = "fsl,P1022DS";
14 compatible = "fsl,P1022DS"; 14 compatible = "fsl,P1022DS";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1022@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1022@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45 15
46 memory { 16 memory {
47 device_type = "memory"; 17 device_type = "memory";
48 }; 18 };
49 19
50 localbus@fffe05000 { 20 lbc: localbus@fffe05000 {
51 #address-cells = <2>; 21 reg = <0xf 0xffe05000 0 0x1000>;
52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2 0 0>;
56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 22 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 23 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000 24 0x2 0x0 0xf 0xff800000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>; 25 0x3 0x0 0xf 0xffdf0000 0x00008000>;
61 26
27 /*
28 * This node is used to access the pixis via "indirect" mode,
29 * which is done by writing the pixis register index to chip
30 * select 0 and the value to/from chip select 1. Indirect
31 * mode is the only way to access the pixis when DIU video
32 * is enabled. Note that this assumes that the first column
33 * of the 'ranges' property above is the chip select number.
34 */
35 board-control@0,0 {
36 compatible = "fsl,p1022ds-indirect-pixis";
37 reg = <0x0 0x0 1 /* CS0 */
38 0x1 0x0 1>; /* CS1 */
39 };
40
62 nor@0,0 { 41 nor@0,0 {
63 #address-cells = <1>; 42 #address-cells = <1>;
64 #size-cells = <1>; 43 #size-cells = <1>;
@@ -161,51 +140,10 @@
161 }; 140 };
162 }; 141 };
163 142
164 soc@fffe00000 { 143 soc: soc@fffe00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 device_type = "soc";
168 compatible = "fsl,p1022-immr", "simple-bus";
169 ranges = <0x0 0xf 0xffe00000 0x100000>; 144 ranges = <0x0 0xf 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
171
172 ecm-law@0 {
173 compatible = "fsl,ecm-law";
174 reg = <0x0 0x1000>;
175 fsl,num-laws = <12>;
176 };
177
178 ecm@1000 {
179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2 0 0>;
182 };
183
184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>;
187 interrupts = <16 2 0 0>;
188 };
189
190 i2c@3000 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 cell-index = <0>;
194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>;
196 interrupts = <43 2 0 0>;
197 dfsrr;
198 };
199 145
200 i2c@3100 { 146 i2c@3100 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 cell-index = <1>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <43 2 0 0>;
207 dfsrr;
208
209 wm8776:codec@1a { 147 wm8776:codec@1a {
210 compatible = "wlf,wm8776"; 148 compatible = "wlf,wm8776";
211 reg = <0x1a>; 149 reg = <0x1a>;
@@ -216,41 +154,14 @@
216 }; 154 };
217 }; 155 };
218 156
219 serial0: serial@4500 {
220 cell-index = <0>;
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0x4500 0x100>;
224 clock-frequency = <0>;
225 interrupts = <42 2 0 0>;
226 };
227
228 serial1: serial@4600 {
229 cell-index = <1>;
230 device_type = "serial";
231 compatible = "ns16550";
232 reg = <0x4600 0x100>;
233 clock-frequency = <0>;
234 interrupts = <42 2 0 0>;
235 };
236
237 spi@7000 { 157 spi@7000 {
238 cell-index = <0>; 158 flash@0 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "fsl,espi";
242 reg = <0x7000 0x1000>;
243 interrupts = <59 0x2 0 0>;
244 espi,num-ss-bits = <4>;
245 mode = "cpu";
246
247 fsl_m25p80@0 {
248 #address-cells = <1>; 159 #address-cells = <1>;
249 #size-cells = <1>; 160 #size-cells = <1>;
250 compatible = "fsl,espi-flash"; 161 compatible = "spansion,s25sl12801";
251 reg = <0>; 162 reg = <0>;
252 linux,modalias = "fsl_m25p80";
253 spi-max-frequency = <40000000>; /* input clock */ 163 spi-max-frequency = <40000000>; /* input clock */
164
254 partition@0 { 165 partition@0 {
255 label = "u-boot-spi"; 166 label = "u-boot-spi";
256 reg = <0x00000000 0x00100000>; 167 reg = <0x00000000 0x00100000>;
@@ -274,115 +185,20 @@
274 }; 185 };
275 186
276 ssi@15000 { 187 ssi@15000 {
277 compatible = "fsl,mpc8610-ssi";
278 cell-index = <0>;
279 reg = <0x15000 0x100>;
280 interrupts = <75 2 0 0>;
281 fsl,mode = "i2s-slave"; 188 fsl,mode = "i2s-slave";
282 codec-handle = <&wm8776>; 189 codec-handle = <&wm8776>;
283 fsl,playback-dma = <&dma00>;
284 fsl,capture-dma = <&dma01>;
285 fsl,fifo-depth = <15>;
286 fsl,ssi-asynchronous; 190 fsl,ssi-asynchronous;
287 }; 191 };
288 192
289 dma@c300 {
290 #address-cells = <1>;
291 #size-cells = <1>;
292 compatible = "fsl,eloplus-dma";
293 reg = <0xc300 0x4>;
294 ranges = <0x0 0xc100 0x200>;
295 cell-index = <1>;
296 dma00: dma-channel@0 {
297 compatible = "fsl,ssi-dma-channel";
298 reg = <0x0 0x80>;
299 cell-index = <0>;
300 interrupts = <76 2 0 0>;
301 };
302 dma01: dma-channel@80 {
303 compatible = "fsl,ssi-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <77 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,eloplus-dma-channel";
310 reg = <0x100 0x80>;
311 cell-index = <2>;
312 interrupts = <78 2 0 0>;
313 };
314 dma-channel@180 {
315 compatible = "fsl,eloplus-dma-channel";
316 reg = <0x180 0x80>;
317 cell-index = <3>;
318 interrupts = <79 2 0 0>;
319 };
320 };
321
322 gpio: gpio-controller@f000 {
323 #gpio-cells = <2>;
324 compatible = "fsl,mpc8572-gpio";
325 reg = <0xf000 0x100>;
326 interrupts = <47 0x2 0 0>;
327 gpio-controller;
328 };
329
330 L2: l2-cache-controller@20000 {
331 compatible = "fsl,p1022-l2-cache-controller";
332 reg = <0x20000 0x1000>;
333 cache-line-size = <32>; // 32 bytes
334 cache-size = <0x40000>; // L2, 256K
335 interrupts = <16 2 0 0>;
336 };
337
338 dma@21300 {
339 #address-cells = <1>;
340 #size-cells = <1>;
341 compatible = "fsl,eloplus-dma";
342 reg = <0x21300 0x4>;
343 ranges = <0x0 0x21100 0x200>;
344 cell-index = <0>;
345 dma-channel@0 {
346 compatible = "fsl,eloplus-dma-channel";
347 reg = <0x0 0x80>;
348 cell-index = <0>;
349 interrupts = <20 2 0 0>;
350 };
351 dma-channel@80 {
352 compatible = "fsl,eloplus-dma-channel";
353 reg = <0x80 0x80>;
354 cell-index = <1>;
355 interrupts = <21 2 0 0>;
356 };
357 dma-channel@100 {
358 compatible = "fsl,eloplus-dma-channel";
359 reg = <0x100 0x80>;
360 cell-index = <2>;
361 interrupts = <22 2 0 0>;
362 };
363 dma-channel@180 {
364 compatible = "fsl,eloplus-dma-channel";
365 reg = <0x180 0x80>;
366 cell-index = <3>;
367 interrupts = <23 2 0 0>;
368 };
369 };
370
371 usb@22000 { 193 usb@22000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl-usb2-dr";
375 reg = <0x22000 0x1000>;
376 interrupts = <28 0x2 0 0>;
377 phy_type = "ulpi"; 194 phy_type = "ulpi";
378 }; 195 };
379 196
380 mdio@24000 { 197 usb@23000 {
381 #address-cells = <1>; 198 status = "disabled";
382 #size-cells = <0>; 199 };
383 compatible = "fsl,etsec2-mdio";
384 reg = <0x24000 0x1000 0xb0030 0x4>;
385 200
201 mdio@24000 {
386 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
387 interrupts = <3 1 0 0>; 203 interrupts = <3 1 0 0>;
388 reg = <0x1>; 204 reg = <0x1>;
@@ -391,189 +207,28 @@
391 interrupts = <9 1 0 0>; 207 interrupts = <9 1 0 0>;
392 reg = <0x2>; 208 reg = <0x2>;
393 }; 209 };
210 tbi-phy@2 {
211 device_type = "tbi-phy";
212 reg = <0x2>;
213 };
394 }; 214 };
395 215
396 mdio@25000 { 216 ethernet@b0000 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "fsl,etsec2-mdio";
400 reg = <0x25000 0x1000 0xb1030 0x4>;
401 };
402
403 enet0: ethernet@B0000 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 cell-index = <0>;
407 device_type = "network";
408 model = "eTSEC";
409 compatible = "fsl,etsec2";
410 fsl,num_rx_queues = <0x8>;
411 fsl,num_tx_queues = <0x8>;
412 fsl,magic-packet;
413 fsl,wake-on-filer;
414 local-mac-address = [ 00 00 00 00 00 00 ];
415 phy-handle = <&phy0>; 217 phy-handle = <&phy0>;
416 phy-connection-type = "rgmii-id"; 218 phy-connection-type = "rgmii-id";
417 queue-group@0{
418 #address-cells = <1>;
419 #size-cells = <1>;
420 reg = <0xB0000 0x1000>;
421 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
422 };
423 queue-group@1{
424 #address-cells = <1>;
425 #size-cells = <1>;
426 reg = <0xB4000 0x1000>;
427 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
428 };
429 }; 219 };
430 220
431 enet1: ethernet@B1000 { 221 ethernet@b1000 {
432 #address-cells = <1>;
433 #size-cells = <1>;
434 cell-index = <0>;
435 device_type = "network";
436 model = "eTSEC";
437 compatible = "fsl,etsec2";
438 fsl,num_rx_queues = <0x8>;
439 fsl,num_tx_queues = <0x8>;
440 local-mac-address = [ 00 00 00 00 00 00 ];
441 phy-handle = <&phy1>; 222 phy-handle = <&phy1>;
442 phy-connection-type = "rgmii-id"; 223 phy-connection-type = "rgmii-id";
443 queue-group@0{
444 #address-cells = <1>;
445 #size-cells = <1>;
446 reg = <0xB1000 0x1000>;
447 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
448 };
449 queue-group@1{
450 #address-cells = <1>;
451 #size-cells = <1>;
452 reg = <0xB5000 0x1000>;
453 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
454 };
455 };
456
457 sdhci@2e000 {
458 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
459 reg = <0x2e000 0x1000>;
460 interrupts = <72 0x2 0 0>;
461 fsl,sdhci-auto-cmd12;
462 /* Filled in by U-Boot */
463 clock-frequency = <0>;
464 };
465
466 crypto@30000 {
467 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
468 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
469 "fsl,sec2.0";
470 reg = <0x30000 0x10000>;
471 interrupts = <45 2 0 0 58 2 0 0>;
472 fsl,num-channels = <4>;
473 fsl,channel-fifo-len = <24>;
474 fsl,exec-units-mask = <0x97c>;
475 fsl,descriptor-types-mask = <0x3a30abf>;
476 };
477
478 sata@18000 {
479 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
480 reg = <0x18000 0x1000>;
481 cell-index = <1>;
482 interrupts = <74 0x2 0 0>;
483 };
484
485 sata@19000 {
486 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
487 reg = <0x19000 0x1000>;
488 cell-index = <2>;
489 interrupts = <41 0x2 0 0>;
490 };
491
492 power@e0070{
493 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
494 reg = <0xe0070 0x20>;
495 };
496
497 display@10000 {
498 compatible = "fsl,diu", "fsl,p1022-diu";
499 reg = <0x10000 1000>;
500 interrupts = <64 2 0 0>;
501 };
502
503 timer@41100 {
504 compatible = "fsl,mpic-global-timer";
505 reg = <0x41100 0x100 0x41300 4>;
506 interrupts = <0 0 3 0
507 1 0 3 0
508 2 0 3 0
509 3 0 3 0>;
510 };
511
512 timer@42100 {
513 compatible = "fsl,mpic-global-timer";
514 reg = <0x42100 0x100 0x42300 4>;
515 interrupts = <4 0 3 0
516 5 0 3 0
517 6 0 3 0
518 7 0 3 0>;
519 };
520
521 mpic: pic@40000 {
522 interrupt-controller;
523 #address-cells = <0>;
524 #interrupt-cells = <4>;
525 reg = <0x40000 0x40000>;
526 compatible = "fsl,mpic";
527 device_type = "open-pic";
528 };
529
530 msi@41600 {
531 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
532 reg = <0x41600 0x80>;
533 msi-available-ranges = <0 0x100>;
534 interrupts = <
535 0xe0 0 0 0
536 0xe1 0 0 0
537 0xe2 0 0 0
538 0xe3 0 0 0
539 0xe4 0 0 0
540 0xe5 0 0 0
541 0xe6 0 0 0
542 0xe7 0 0 0>;
543 };
544
545 global-utilities@e0000 { //global utilities block
546 compatible = "fsl,p1022-guts";
547 reg = <0xe0000 0x1000>;
548 fsl,has-rstcr;
549 }; 224 };
550 }; 225 };
551 226
552 pci0: pcie@fffe09000 { 227 pci0: pcie@fffe09000 {
553 compatible = "fsl,p1022-pcie";
554 device_type = "pci";
555 #interrupt-cells = <1>;
556 #size-cells = <2>;
557 #address-cells = <3>;
558 reg = <0xf 0xffe09000 0 0x1000>; 228 reg = <0xf 0xffe09000 0 0x1000>;
559 bus-range = <0 255>; 229 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
560 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
561 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 230 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
562 clock-frequency = <33333333>;
563 interrupts = <16 2 0 0>;
564 interrupt-map-mask = <0xf800 0 0 7>;
565 interrupt-map = <
566 /* IDSEL 0x0 */
567 0000 0 0 1 &mpic 4 1
568 0000 0 0 2 &mpic 5 1
569 0000 0 0 3 &mpic 6 1
570 0000 0 0 4 &mpic 7 1
571 >;
572 pcie@0 { 231 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>;
575 #address-cells = <3>;
576 device_type = "pci";
577 ranges = <0x2000000 0x0 0xe0000000 232 ranges = <0x2000000 0x0 0xe0000000
578 0x2000000 0x0 0xe0000000 233 0x2000000 0x0 0xe0000000
579 0x0 0x20000000 234 0x0 0x20000000
@@ -585,30 +240,11 @@
585 }; 240 };
586 241
587 pci1: pcie@fffe0a000 { 242 pci1: pcie@fffe0a000 {
588 compatible = "fsl,p1022-pcie";
589 device_type = "pci";
590 #interrupt-cells = <1>;
591 #size-cells = <2>;
592 #address-cells = <3>;
593 reg = <0xf 0xffe0a000 0 0x1000>; 243 reg = <0xf 0xffe0a000 0 0x1000>;
594 bus-range = <0 255>; 244 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
595 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
596 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 245 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
597 clock-frequency = <33333333>;
598 interrupts = <16 2 0 0>;
599 interrupt-map-mask = <0xf800 0 0 7>;
600 interrupt-map = <
601 /* IDSEL 0x0 */
602 0000 0 0 1 &mpic 0 1
603 0000 0 0 2 &mpic 1 1
604 0000 0 0 3 &mpic 2 1
605 0000 0 0 4 &mpic 3 1
606 >;
607 pcie@0 { 246 pcie@0 {
608 reg = <0x0 0x0 0x0 0x0 0x0>; 247 reg = <0x0 0x0 0x0 0x0 0x0>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 ranges = <0x2000000 0x0 0xe0000000 248 ranges = <0x2000000 0x0 0xe0000000
613 0x2000000 0x0 0xe0000000 249 0x2000000 0x0 0xe0000000
614 0x0 0x20000000 250 0x0 0x20000000
@@ -619,32 +255,11 @@
619 }; 255 };
620 }; 256 };
621 257
622
623 pci2: pcie@fffe0b000 { 258 pci2: pcie@fffe0b000 {
624 compatible = "fsl,p1022-pcie";
625 device_type = "pci";
626 #interrupt-cells = <1>;
627 #size-cells = <2>;
628 #address-cells = <3>;
629 reg = <0xf 0xffe0b000 0 0x1000>; 259 reg = <0xf 0xffe0b000 0 0x1000>;
630 bus-range = <0 255>; 260 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
631 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
632 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 261 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
633 clock-frequency = <33333333>;
634 interrupts = <16 2 0 0>;
635 interrupt-map-mask = <0xf800 0 0 7>;
636 interrupt-map = <
637 /* IDSEL 0x0 */
638 0000 0 0 1 &mpic 8 1
639 0000 0 0 2 &mpic 9 1
640 0000 0 0 3 &mpic 10 1
641 0000 0 0 4 &mpic 11 1
642 >;
643 pcie@0 { 262 pcie@0 {
644 reg = <0x0 0x0 0x0 0x0 0x0>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 device_type = "pci";
648 ranges = <0x2000000 0x0 0xe0000000 263 ranges = <0x2000000 0x0 0xe0000000
649 0x2000000 0x0 0xe0000000 264 0x2000000 0x0 0xe0000000
650 0x0 0x20000000 265 0x0 0x20000000
@@ -655,3 +270,5 @@
655 }; 270 };
656 }; 271 };
657}; 272};
273
274/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d3b478242ea..beb6cb12e59 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -34,137 +34,30 @@
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37/dts-v1/; 37/include/ "fsl/p1023si-pre.dtsi"
38 38
39/ { 39/ {
40 model = "fsl,P1023"; 40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS"; 41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>; 42 #address-cells = <2>;
43 #size-cells = <2>; 43 #size-cells = <2>;
44 44 interrupt-parent = <&mpic>;
45 aliases {
46 serial0 = &serial0;
47 serial1 = &serial1;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51
52 crypto = &crypto;
53 sec_jr0 = &sec_jr0;
54 sec_jr1 = &sec_jr1;
55 sec_jr2 = &sec_jr2;
56 sec_jr3 = &sec_jr3;
57 rtic_a = &rtic_a;
58 rtic_b = &rtic_b;
59 rtic_c = &rtic_c;
60 rtic_d = &rtic_d;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,P1023@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 next-level-cache = <&L2>;
71 };
72
73 cpu1: PowerPC,P1023@1 {
74 device_type = "cpu";
75 reg = <0x1>;
76 next-level-cache = <&L2>;
77 };
78 };
79 45
80 memory { 46 memory {
81 device_type = "memory"; 47 device_type = "memory";
82 }; 48 };
83 49
84 soc@ff600000 { 50 soc: soc@ff600000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 device_type = "soc";
88 compatible = "fsl,p1023-immr", "simple-bus";
89 ranges = <0x0 0x0 0xff600000 0x200000>; 51 ranges = <0x0 0x0 0xff600000 0x200000>;
90 bus-frequency = <0>; // Filled out by uboot.
91
92 ecm-law@0 {
93 compatible = "fsl,ecm-law";
94 reg = <0x0 0x1000>;
95 fsl,num-laws = <12>;
96 };
97
98 ecm@1000 {
99 compatible = "fsl,p1023-ecm", "fsl,ecm";
100 reg = <0x1000 0x1000>;
101 interrupts = <16 2>;
102 interrupt-parent = <&mpic>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,p1023-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupt-parent = <&mpic>;
109 interrupts = <16 2>;
110 };
111 52
112 i2c@3000 { 53 i2c@3000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 cell-index = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <43 2>;
119 interrupt-parent = <&mpic>;
120 dfsrr;
121 rtc@68 { 54 rtc@68 {
122 compatible = "dallas,ds1374"; 55 compatible = "dallas,ds1374";
123 reg = <0x68>; 56 reg = <0x68>;
124 }; 57 };
125 }; 58 };
126 59
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3100 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136 };
137
138 serial0: serial@4500 {
139 cell-index = <0>;
140 device_type = "serial";
141 compatible = "ns16550";
142 reg = <0x4500 0x100>;
143 clock-frequency = <0>;
144 interrupts = <42 2>;
145 interrupt-parent = <&mpic>;
146 };
147
148 serial1: serial@4600 {
149 cell-index = <1>;
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <0x4600 0x100>;
153 clock-frequency = <0>;
154 interrupts = <42 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 spi@7000 { 60 spi@7000 {
159 cell-index = <0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
163 reg = <0x7000 0x1000>;
164 interrupts = <59 0x2>;
165 interrupt-parent = <&mpic>;
166 fsl,espi-num-chipselects = <4>;
167
168 fsl_dataflash@0 { 61 fsl_dataflash@0 {
169 #address-cells = <1>; 62 #address-cells = <1>;
170 #size-cells = <1>; 63 #size-cells = <1>;
@@ -186,197 +79,14 @@
186 }; 79 };
187 }; 80 };
188 81
189 gpio: gpio-controller@f000 {
190 #gpio-cells = <2>;
191 compatible = "fsl,qoriq-gpio";
192 reg = <0xf000 0x100>;
193 interrupts = <47 0x2>;
194 interrupt-parent = <&mpic>;
195 gpio-controller;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,p1023-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x40000>; // L2,256K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,eloplus-dma-channel";
216 reg = <0x0 0x80>;
217 cell-index = <0>;
218 interrupt-parent = <&mpic>;
219 interrupts = <20 2>;
220 };
221 dma-channel@80 {
222 compatible = "fsl,eloplus-dma-channel";
223 reg = <0x80 0x80>;
224 cell-index = <1>;
225 interrupt-parent = <&mpic>;
226 interrupts = <21 2>;
227 };
228 dma-channel@100 {
229 compatible = "fsl,eloplus-dma-channel";
230 reg = <0x100 0x80>;
231 cell-index = <2>;
232 interrupt-parent = <&mpic>;
233 interrupts = <22 2>;
234 };
235 dma-channel@180 {
236 compatible = "fsl,eloplus-dma-channel";
237 reg = <0x180 0x80>;
238 cell-index = <3>;
239 interrupt-parent = <&mpic>;
240 interrupts = <23 2>;
241 };
242 };
243
244 usb@22000 { 82 usb@22000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl-usb2-dr";
248 reg = <0x22000 0x1000>;
249 interrupt-parent = <&mpic>;
250 interrupts = <28 0x2>;
251 dr_mode = "host"; 83 dr_mode = "host";
252 phy_type = "ulpi"; 84 phy_type = "ulpi";
253 }; 85 };
254
255 crypto: crypto@300000 {
256 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 reg = <0x30000 0x10000>;
260 ranges = <0 0x30000 0x10000>;
261 interrupt-parent = <&mpic>;
262 interrupts = <58 2>;
263
264 sec_jr0: jr@1000 {
265 compatible = "fsl,sec-v4.2-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x1000 0x1000>;
268 interrupts = <45 2>;
269 };
270
271 sec_jr1: jr@2000 {
272 compatible = "fsl,sec-v4.2-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x2000 0x1000>;
275 interrupts = <45 2>;
276 };
277
278 sec_jr2: jr@3000 {
279 compatible = "fsl,sec-v4.2-job-ring",
280 "fsl,sec-v4.0-job-ring";
281 reg = <0x3000 0x1000>;
282 interrupts = <57 2>;
283 };
284
285 sec_jr3: jr@4000 {
286 compatible = "fsl,sec-v4.2-job-ring",
287 "fsl,sec-v4.0-job-ring";
288 reg = <0x4000 0x1000>;
289 interrupts = <57 2>;
290 };
291
292 rtic@6000 {
293 compatible = "fsl,sec-v4.2-rtic",
294 "fsl,sec-v4.0-rtic";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x6000 0x100>;
298 ranges = <0x0 0x6100 0xe00>;
299
300 rtic_a: rtic-a@0 {
301 compatible = "fsl,sec-v4.2-rtic-memory",
302 "fsl,sec-v4.0-rtic-memory";
303 reg = <0x00 0x20 0x100 0x80>;
304 };
305
306 rtic_b: rtic-b@20 {
307 compatible = "fsl,sec-v4.2-rtic-memory",
308 "fsl,sec-v4.0-rtic-memory";
309 reg = <0x20 0x20 0x200 0x80>;
310 };
311
312 rtic_c: rtic-c@40 {
313 compatible = "fsl,sec-v4.2-rtic-memory",
314 "fsl,sec-v4.0-rtic-memory";
315 reg = <0x40 0x20 0x300 0x80>;
316 };
317
318 rtic_d: rtic-d@60 {
319 compatible = "fsl,sec-v4.2-rtic-memory",
320 "fsl,sec-v4.0-rtic-memory";
321 reg = <0x60 0x20 0x500 0x80>;
322 };
323 };
324 };
325
326 power@e0070{
327 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
328 "fsl,p1022-pmc";
329 reg = <0xe0070 0x20>;
330 etsec1_clk: soc-clk@B0{
331 fsl,pmcdr-mask = <0x00000080>;
332 };
333 etsec2_clk: soc-clk@B1{
334 fsl,pmcdr-mask = <0x00000040>;
335 };
336 etsec3_clk: soc-clk@B2{
337 fsl,pmcdr-mask = <0x00000020>;
338 };
339 };
340
341 mpic: pic@40000 {
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <2>;
345 reg = <0x40000 0x40000>;
346 compatible = "chrp,open-pic";
347 device_type = "open-pic";
348 };
349
350 msi@41600 {
351 compatible = "fsl,p1023-msi", "fsl,mpic-msi";
352 reg = <0x41600 0x80>;
353 msi-available-ranges = <0 0x100>;
354 interrupts = <
355 0xe0 0
356 0xe1 0
357 0xe2 0
358 0xe3 0
359 0xe4 0
360 0xe5 0
361 0xe6 0
362 0xe7 0>;
363 interrupt-parent = <&mpic>;
364 };
365
366 global-utilities@e0000 { //global utilities block
367 compatible = "fsl,p1023-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 }; 86 };
372 87
373 localbus@ff605000 { 88 lbc: localbus@ff605000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
377 reg = <0 0xff605000 0 0x1000>; 89 reg = <0 0xff605000 0 0x1000>;
378 interrupts = <19 2>;
379 interrupt-parent = <&mpic>;
380 90
381 /* NOR Flash, BCSR */ 91 /* NOR Flash, BCSR */
382 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 92 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
@@ -428,34 +138,18 @@
428 }; 138 };
429 139
430 pci0: pcie@ff60a000 { 140 pci0: pcie@ff60a000 {
431 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
432 cell-index = <1>;
433 device_type = "pci";
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0 0xff60a000 0 0x1000>; 141 reg = <0 0xff60a000 0 0x1000>;
437 bus-range = <0 255>;
438 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 142 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
439 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 143 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
440 clock-frequency = <33333333>;
441 interrupt-parent = <&mpic>;
442 interrupts = <16 2>;
443 pcie@0 { 144 pcie@0 {
444 reg = <0x0 0x0 0x0 0x0 0x0>;
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 device_type = "pci";
449 interrupt-parent = <&mpic>;
450 interrupts = <16 2>;
451 interrupt-map-mask = <0xf800 0 0 7>;
452 /* IRQ[0:3] are pulled up on board, set to active-low */ 145 /* IRQ[0:3] are pulled up on board, set to active-low */
146 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = < 147 interrupt-map = <
454 /* IDSEL 0x0 */ 148 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 0 1 149 0000 0 0 1 &mpic 0 1 0 0
456 0000 0 0 2 &mpic 1 1 150 0000 0 0 2 &mpic 1 1 0 0
457 0000 0 0 3 &mpic 2 1 151 0000 0 0 3 &mpic 2 1 0 0
458 0000 0 0 4 &mpic 3 1 152 0000 0 0 4 &mpic 3 1 0 0
459 >; 153 >;
460 ranges = <0x2000000 0x0 0xc0000000 154 ranges = <0x2000000 0x0 0xc0000000
461 0x2000000 0x0 0xc0000000 155 0x2000000 0x0 0xc0000000
@@ -467,38 +161,22 @@
467 }; 161 };
468 }; 162 };
469 163
470 pci1: pcie@ff609000 { 164 board_pci1: pci1: pcie@ff609000 {
471 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
472 cell-index = <2>;
473 device_type = "pci";
474 #size-cells = <2>;
475 #address-cells = <3>;
476 reg = <0 0xff609000 0 0x1000>; 165 reg = <0 0xff609000 0 0x1000>;
477 bus-range = <0 255>;
478 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 166 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
479 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 167 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
480 clock-frequency = <33333333>;
481 interrupt-parent = <&mpic>;
482 interrupts = <16 2>;
483 pcie@0 { 168 pcie@0 {
484 reg = <0x0 0x0 0x0 0x0 0x0>;
485 #interrupt-cells = <1>;
486 #size-cells = <2>;
487 #address-cells = <3>;
488 device_type = "pci";
489 interrupt-parent = <&mpic>;
490 interrupts = <16 2>;
491 interrupt-map-mask = <0xf800 0 0 7>;
492 /* 169 /*
493 * IRQ[4:6] only for PCIe, set to active-high, 170 * IRQ[4:6] only for PCIe, set to active-high,
494 * IRQ[7] is pulled up on board, set to active-low 171 * IRQ[7] is pulled up on board, set to active-low
495 */ 172 */
173 interrupt-map-mask = <0xf800 0 0 7>;
496 interrupt-map = < 174 interrupt-map = <
497 /* IDSEL 0x0 */ 175 /* IDSEL 0x0 */
498 0000 0 0 1 &mpic 4 2 176 0000 0 0 1 &mpic 4 2 0 0
499 0000 0 0 2 &mpic 5 2 177 0000 0 0 2 &mpic 5 2 0 0
500 0000 0 0 3 &mpic 6 2 178 0000 0 0 3 &mpic 6 2 0 0
501 0000 0 0 4 &mpic 7 1 179 0000 0 0 4 &mpic 7 1 0 0
502 >; 180 >;
503 ranges = <0x2000000 0x0 0xa0000000 181 ranges = <0x2000000 0x0 0xa0000000
504 0x2000000 0x0 0xa0000000 182 0x2000000 0x0 0xa0000000
@@ -511,37 +189,21 @@
511 }; 189 };
512 190
513 pci2: pcie@ff60b000 { 191 pci2: pcie@ff60b000 {
514 cell-index = <3>;
515 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
516 device_type = "pci";
517 #size-cells = <2>;
518 #address-cells = <3>;
519 reg = <0 0xff60b000 0 0x1000>; 192 reg = <0 0xff60b000 0 0x1000>;
520 bus-range = <0 255>;
521 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 193 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
522 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 194 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
523 clock-frequency = <33333333>;
524 interrupt-parent = <&mpic>;
525 interrupts = <16 2>;
526 pcie@0 { 195 pcie@0 {
527 reg = <0x0 0x0 0x0 0x0 0x0>;
528 #interrupt-cells = <1>;
529 #size-cells = <2>;
530 #address-cells = <3>;
531 device_type = "pci";
532 interrupt-parent = <&mpic>;
533 interrupts = <16 2>;
534 interrupt-map-mask = <0xf800 0 0 7>;
535 /* 196 /*
536 * IRQ[8:10] are pulled up on board, set to active-low 197 * IRQ[8:10] are pulled up on board, set to active-low
537 * IRQ[11] only for PCIe, set to active-high, 198 * IRQ[11] only for PCIe, set to active-high,
538 */ 199 */
200 interrupt-map-mask = <0xf800 0 0 7>;
539 interrupt-map = < 201 interrupt-map = <
540 /* IDSEL 0x0 */ 202 /* IDSEL 0x0 */
541 0000 0 0 1 &mpic 8 1 203 0000 0 0 1 &mpic 8 1 0 0
542 0000 0 0 2 &mpic 9 1 204 0000 0 0 2 &mpic 9 1 0 0
543 0000 0 0 3 &mpic 10 1 205 0000 0 0 3 &mpic 10 1 0 0
544 0000 0 0 4 &mpic 11 2 206 0000 0 0 4 &mpic 11 2 0 0
545 >; 207 >;
546 ranges = <0x2000000 0x0 0x80000000 208 ranges = <0x2000000 0x0 0x80000000
547 0x2000000 0x0 0x80000000 209 0x2000000 0x0 0x80000000
@@ -553,3 +215,5 @@
553 }; 215 };
554 }; 216 };
555}; 217};
218
219/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 66f03d6477b..237310cc7e6 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -9,30 +9,17 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020DS"; 15 model = "fsl,P2020DS";
16 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
17 17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
35 compatible = "fsl,elbc", "simple-bus";
36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 23 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
37 0x1 0x0 0x0 0xe0000000 0x08000000 24 0x1 0x0 0x0 0xe0000000 0x08000000
38 0x2 0x0 0x0 0xffa00000 0x00040000 25 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -40,203 +27,18 @@
40 0x4 0x0 0x0 0xffa40000 0x00040000 27 0x4 0x0 0x0 0xffa40000 0x00040000
41 0x5 0x0 0x0 0xffa80000 0x00040000 28 0x5 0x0 0x0 0xffa80000 0x00040000
42 0x6 0x0 0x0 0xffac0000 0x00040000>; 29 0x6 0x0 0x0 0xffac0000 0x00040000>;
43 30 reg = <0 0xffe05000 0 0x1000>;
44 nor@0,0 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "cfi-flash";
48 reg = <0x0 0x0 0x8000000>;
49 bank-width = <2>;
50 device-width = <1>;
51
52 ramdisk@0 {
53 reg = <0x0 0x03000000>;
54 read-only;
55 };
56
57 diagnostic@3000000 {
58 reg = <0x03000000 0x00e00000>;
59 read-only;
60 };
61
62 dink@3e00000 {
63 reg = <0x03e00000 0x00200000>;
64 read-only;
65 };
66
67 kernel@4000000 {
68 reg = <0x04000000 0x00400000>;
69 read-only;
70 };
71
72 jffs2@4400000 {
73 reg = <0x04400000 0x03b00000>;
74 };
75
76 dtb@7f00000 {
77 reg = <0x07f00000 0x00080000>;
78 read-only;
79 };
80
81 u-boot@7f80000 {
82 reg = <0x07f80000 0x00080000>;
83 read-only;
84 };
85 };
86
87 nand@2,0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,elbc-fcm-nand";
91 reg = <0x2 0x0 0x40000>;
92
93 u-boot@0 {
94 reg = <0x0 0x02000000>;
95 read-only;
96 };
97
98 jffs2@2000000 {
99 reg = <0x02000000 0x10000000>;
100 };
101
102 ramdisk@12000000 {
103 reg = <0x12000000 0x08000000>;
104 read-only;
105 };
106
107 kernel@1a000000 {
108 reg = <0x1a000000 0x04000000>;
109 };
110
111 dtb@1e000000 {
112 reg = <0x1e000000 0x01000000>;
113 read-only;
114 };
115
116 empty@1f000000 {
117 reg = <0x1f000000 0x21000000>;
118 };
119 };
120
121 board-control@3,0 {
122 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
123 reg = <0x3 0x0 0x30>;
124 };
125
126 nand@4,0 {
127 compatible = "fsl,elbc-fcm-nand";
128 reg = <0x4 0x0 0x40000>;
129 };
130
131 nand@5,0 {
132 compatible = "fsl,elbc-fcm-nand";
133 reg = <0x5 0x0 0x40000>;
134 };
135
136 nand@6,0 {
137 compatible = "fsl,elbc-fcm-nand";
138 reg = <0x6 0x0 0x40000>;
139 };
140 }; 31 };
141 32
142 soc@ffe00000 { 33 board_soc: soc: soc@ffe00000 {
143 34 ranges = <0x0 0x0 0xffe00000 0x100000>;
144 usb@22000 {
145 phy_type = "ulpi";
146 };
147
148 mdio@24520 {
149 phy0: ethernet-phy@0 {
150 interrupt-parent = <&mpic>;
151 interrupts = <3 1>;
152 reg = <0x0>;
153 };
154 phy1: ethernet-phy@1 {
155 interrupt-parent = <&mpic>;
156 interrupts = <3 1>;
157 reg = <0x1>;
158 };
159 phy2: ethernet-phy@2 {
160 interrupt-parent = <&mpic>;
161 interrupts = <3 1>;
162 reg = <0x2>;
163 };
164 tbi0: tbi-phy@11 {
165 reg = <0x11>;
166 device_type = "tbi-phy";
167 };
168
169 };
170
171 mdio@25520 {
172 tbi1: tbi-phy@11 {
173 reg = <0x11>;
174 device_type = "tbi-phy";
175 };
176 };
177
178 mdio@26520 {
179 tbi2: tbi-phy@11 {
180 reg = <0x11>;
181 device_type = "tbi-phy";
182 };
183
184 };
185
186 ptp_clock@24E00 {
187 compatible = "fsl,etsec-ptp";
188 reg = <0x24E00 0xB0>;
189 interrupts = <68 2 69 2 70 2>;
190 interrupt-parent = < &mpic >;
191 fsl,tclk-period = <5>;
192 fsl,tmr-prsc = <200>;
193 fsl,tmr-add = <0xCCCCCCCD>;
194 fsl,tmr-fiper1 = <0x3B9AC9FB>;
195 fsl,tmr-fiper2 = <0x0001869B>;
196 fsl,max-adj = <249999999>;
197 };
198
199 enet0: ethernet@24000 {
200 tbi-handle = <&tbi0>;
201 phy-handle = <&phy0>;
202 phy-connection-type = "rgmii-id";
203 };
204
205 enet1: ethernet@25000 {
206 tbi-handle = <&tbi1>;
207 phy-handle = <&phy1>;
208 phy-connection-type = "rgmii-id";
209
210 };
211
212 enet2: ethernet@26000 {
213 tbi-handle = <&tbi2>;
214 phy-handle = <&phy2>;
215 phy-connection-type = "rgmii-id";
216 };
217
218
219 msi@41600 {
220 compatible = "fsl,mpic-msi";
221 };
222 }; 35 };
223 36
224 pci0: pcie@ffe08000 { 37 pci2: pcie@ffe08000 {
225 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 38 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
226 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 39 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 40 reg = <0 0xffe08000 0 0x1000>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x8 0x1
231 0000 0x0 0x0 0x2 &mpic 0x9 0x1
232 0000 0x0 0x0 0x3 &mpic 0xa 0x1
233 0000 0x0 0x0 0x4 &mpic 0xb 0x1
234 >;
235 pcie@0 { 41 pcie@0 {
236 reg = <0x0 0x0 0x0 0x0 0x0>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 device_type = "pci";
240 ranges = <0x2000000 0x0 0x80000000 42 ranges = <0x2000000 0x0 0x80000000
241 0x2000000 0x0 0x80000000 43 0x2000000 0x0 0x80000000
242 0x0 0x20000000 44 0x0 0x20000000
@@ -247,61 +49,11 @@
247 }; 49 };
248 }; 50 };
249 51
250 pci1: pcie@ffe09000 { 52 board_pci1: pci1: pcie@ffe09000 {
251 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
252 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
253 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 55 reg = <0 0xffe09000 0 0x1000>;
254 interrupt-map = <
255
256 // IDSEL 0x11 func 0 - PCI slot 1
257 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
258 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
259
260 // IDSEL 0x11 func 1 - PCI slot 1
261 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
262 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
263
264 // IDSEL 0x11 func 2 - PCI slot 1
265 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
266 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
267
268 // IDSEL 0x11 func 3 - PCI slot 1
269 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
270 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
271
272 // IDSEL 0x11 func 4 - PCI slot 1
273 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
274 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
275
276 // IDSEL 0x11 func 5 - PCI slot 1
277 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
278 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
279
280 // IDSEL 0x11 func 6 - PCI slot 1
281 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
282 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
283
284 // IDSEL 0x11 func 7 - PCI slot 1
285 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
286 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
287
288 // IDSEL 0x1d Audio
289 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
290
291 // IDSEL 0x1e Legacy
292 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
293 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
294
295 // IDSEL 0x1f IDE/SATA
296 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
297 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
298 >;
299
300 pcie@0 { 56 pcie@0 {
301 reg = <0x0 0x0 0x0 0x0 0x0>;
302 #size-cells = <2>;
303 #address-cells = <3>;
304 device_type = "pci";
305 ranges = <0x2000000 0x0 0xa0000000 57 ranges = <0x2000000 0x0 0xa0000000
306 0x2000000 0x0 0xa0000000 58 0x2000000 0x0 0xa0000000
307 0x0 0x20000000 59 0x0 0x20000000
@@ -309,89 +61,14 @@
309 0x1000000 0x0 0x0 61 0x1000000 0x0 0x0
310 0x1000000 0x0 0x0 62 0x1000000 0x0 0x0
311 0x0 0x10000>; 63 0x0 0x10000>;
312 uli1575@0 {
313 reg = <0x0 0x0 0x0 0x0 0x0>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 ranges = <0x2000000 0x0 0xa0000000
317 0x2000000 0x0 0xa0000000
318 0x0 0x20000000
319
320 0x1000000 0x0 0x0
321 0x1000000 0x0 0x0
322 0x0 0x10000>;
323 isa@1e {
324 device_type = "isa";
325 #interrupt-cells = <2>;
326 #size-cells = <1>;
327 #address-cells = <2>;
328 reg = <0xf000 0x0 0x0 0x0 0x0>;
329 ranges = <0x1 0x0 0x1000000 0x0 0x0
330 0x1000>;
331 interrupt-parent = <&i8259>;
332
333 i8259: interrupt-controller@20 {
334 reg = <0x1 0x20 0x2
335 0x1 0xa0 0x2
336 0x1 0x4d0 0x2>;
337 interrupt-controller;
338 device_type = "interrupt-controller";
339 #address-cells = <0>;
340 #interrupt-cells = <2>;
341 compatible = "chrp,iic";
342 interrupts = <4 1>;
343 interrupt-parent = <&mpic>;
344 };
345
346 i8042@60 {
347 #size-cells = <0>;
348 #address-cells = <1>;
349 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
350 interrupts = <1 3 12 3>;
351 interrupt-parent =
352 <&i8259>;
353
354 keyboard@0 {
355 reg = <0x0>;
356 compatible = "pnpPNP,303";
357 };
358
359 mouse@1 {
360 reg = <0x1>;
361 compatible = "pnpPNP,f03";
362 };
363 };
364
365 rtc@70 {
366 compatible = "pnpPNP,b00";
367 reg = <0x1 0x70 0x2>;
368 };
369
370 gpio@400 {
371 reg = <0x1 0x400 0x80>;
372 };
373 };
374 };
375 }; 64 };
376
377 }; 65 };
378 66
379 pci2: pcie@ffe0a000 { 67 pci0: pcie@ffe0a000 {
380 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 68 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
381 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 69 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
382 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 70 reg = <0 0xffe0a000 0 0x1000>;
383 interrupt-map = <
384 /* IDSEL 0x0 */
385 0000 0x0 0x0 0x1 &mpic 0x0 0x1
386 0000 0x0 0x0 0x2 &mpic 0x1 0x1
387 0000 0x0 0x0 0x3 &mpic 0x2 0x1
388 0000 0x0 0x0 0x4 &mpic 0x3 0x1
389 >;
390 pcie@0 { 71 pcie@0 {
391 reg = <0x0 0x0 0x0 0x0 0x0>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 ranges = <0x2000000 0x0 0xc0000000 72 ranges = <0x2000000 0x0 0xc0000000
396 0x2000000 0x0 0xc0000000 73 0x2000000 0x0 0xc0000000
397 0x0 0x20000000 74 0x0 0x20000000
@@ -402,3 +79,11 @@
402 }; 79 };
403 }; 80 };
404}; 81};
82
83/*
84 * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
85 * for interrupt-map & interrupt-map-mask
86 */
87
88/include/ "fsl/p2020si-post.dtsi"
89/include/ "p2020ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
new file mode 100644
index 00000000000..c1cf6cef4dd
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -0,0 +1,316 @@
1/*
2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
46 read-only;
47 };
48
49 diagnostic@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 read-only;
52 };
53
54 dink@3e00000 {
55 reg = <0x03e00000 0x00200000>;
56 read-only;
57 };
58
59 kernel@4000000 {
60 reg = <0x04000000 0x00400000>;
61 read-only;
62 };
63
64 jffs2@4400000 {
65 reg = <0x04400000 0x03b00000>;
66 };
67
68 dtb@7f00000 {
69 reg = <0x07f00000 0x00080000>;
70 read-only;
71 };
72
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
76 };
77 };
78
79 nand@2,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,elbc-fcm-nand";
83 reg = <0x2 0x0 0x40000>;
84
85 u-boot@0 {
86 reg = <0x0 0x02000000>;
87 read-only;
88 };
89
90 jffs2@2000000 {
91 reg = <0x02000000 0x10000000>;
92 };
93
94 ramdisk@12000000 {
95 reg = <0x12000000 0x08000000>;
96 read-only;
97 };
98
99 kernel@1a000000 {
100 reg = <0x1a000000 0x04000000>;
101 };
102
103 dtb@1e000000 {
104 reg = <0x1e000000 0x01000000>;
105 read-only;
106 };
107
108 empty@1f000000 {
109 reg = <0x1f000000 0x21000000>;
110 };
111 };
112
113 board-control@3,0 {
114 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
115 reg = <0x3 0x0 0x30>;
116 };
117
118 nand@4,0 {
119 compatible = "fsl,elbc-fcm-nand";
120 reg = <0x4 0x0 0x40000>;
121 };
122
123 nand@5,0 {
124 compatible = "fsl,elbc-fcm-nand";
125 reg = <0x5 0x0 0x40000>;
126 };
127
128 nand@6,0 {
129 compatible = "fsl,elbc-fcm-nand";
130 reg = <0x6 0x0 0x40000>;
131 };
132};
133
134&board_soc {
135 usb@22000 {
136 phy_type = "ulpi";
137 };
138
139 mdio@24520 {
140 phy0: ethernet-phy@0 {
141 interrupts = <3 1 0 0>;
142 reg = <0x0>;
143 };
144 phy1: ethernet-phy@1 {
145 interrupts = <3 1 0 0>;
146 reg = <0x1>;
147 };
148 phy2: ethernet-phy@2 {
149 interrupts = <3 1 0 0>;
150 reg = <0x2>;
151 };
152 tbi0: tbi-phy@11 {
153 reg = <0x11>;
154 device_type = "tbi-phy";
155 };
156
157 };
158
159 mdio@25520 {
160 tbi1: tbi-phy@11 {
161 reg = <0x11>;
162 device_type = "tbi-phy";
163 };
164 };
165
166 mdio@26520 {
167 tbi2: tbi-phy@11 {
168 reg = <0x11>;
169 device_type = "tbi-phy";
170 };
171
172 };
173
174 ptp_clock@24e00 {
175 fsl,tclk-period = <5>;
176 fsl,tmr-prsc = <200>;
177 fsl,tmr-add = <0xCCCCCCCD>;
178 fsl,tmr-fiper1 = <0x3B9AC9FB>;
179 fsl,tmr-fiper2 = <0x0001869B>;
180 fsl,max-adj = <249999999>;
181 };
182
183 enet0: ethernet@24000 {
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy0>;
186 phy-connection-type = "rgmii-id";
187 };
188
189 enet1: ethernet@25000 {
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
193
194 };
195
196 enet2: ethernet@26000 {
197 tbi-handle = <&tbi2>;
198 phy-handle = <&phy2>;
199 phy-connection-type = "rgmii-id";
200 };
201};
202
203&board_pci1 {
204 pcie@0 {
205 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
206 interrupt-map = <
207
208 // IDSEL 0x11 func 0 - PCI slot 1
209 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
210 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
211
212 // IDSEL 0x11 func 1 - PCI slot 1
213 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
214 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
215
216 // IDSEL 0x11 func 2 - PCI slot 1
217 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
218 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
219
220 // IDSEL 0x11 func 3 - PCI slot 1
221 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
222 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
223
224 // IDSEL 0x11 func 4 - PCI slot 1
225 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
226 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
227
228 // IDSEL 0x11 func 5 - PCI slot 1
229 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
230 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
231
232 // IDSEL 0x11 func 6 - PCI slot 1
233 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
234 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
235
236 // IDSEL 0x11 func 7 - PCI slot 1
237 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
238 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
239
240 // IDSEL 0x1d Audio
241 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
242
243 // IDSEL 0x1e Legacy
244 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
245 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
246
247 // IDSEL 0x1f IDE/SATA
248 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
249 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
250 >;
251
252 uli1575@0 {
253 reg = <0x0 0x0 0x0 0x0 0x0>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 ranges = <0x2000000 0x0 0xa0000000
257 0x2000000 0x0 0xa0000000
258 0x0 0x20000000
259
260 0x1000000 0x0 0x0
261 0x1000000 0x0 0x0
262 0x0 0x10000>;
263 isa@1e {
264 device_type = "isa";
265 #interrupt-cells = <2>;
266 #size-cells = <1>;
267 #address-cells = <2>;
268 reg = <0xf000 0x0 0x0 0x0 0x0>;
269 ranges = <0x1 0x0 0x1000000 0x0 0x0
270 0x1000>;
271 interrupt-parent = <&i8259>;
272
273 i8259: interrupt-controller@20 {
274 reg = <0x1 0x20 0x2
275 0x1 0xa0 0x2
276 0x1 0x4d0 0x2>;
277 interrupt-controller;
278 device_type = "interrupt-controller";
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 compatible = "chrp,iic";
282 interrupts = <4 1 0 0>;
283 interrupt-parent = <&mpic>;
284 };
285
286 i8042@60 {
287 #size-cells = <0>;
288 #address-cells = <1>;
289 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
290 interrupts = <1 3 12 3>;
291 interrupt-parent =
292 <&i8259>;
293
294 keyboard@0 {
295 reg = <0x0>;
296 compatible = "pnpPNP,303";
297 };
298
299 mouse@1 {
300 reg = <0x1>;
301 compatible = "pnpPNP,f03";
302 };
303 };
304
305 rtc@70 {
306 compatible = "pnpPNP,b00";
307 reg = <0x1 0x70 0x2>;
308 };
309
310 gpio@400 {
311 reg = <0x1 0x400 0x80>;
312 };
313 };
314 };
315 };
316};
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f3021..26759a59171 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,7 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020RDB"; 15 model = "fsl,P2020RDB";
@@ -29,7 +29,8 @@
29 device_type = "memory"; 29 device_type = "memory";
30 }; 30 };
31 31
32 localbus@ffe05000 { 32 lbc: localbus@ffe05000 {
33 reg = <0 0xffe05000 0 0x1000>;
33 34
34 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -140,7 +141,9 @@
140 141
141 }; 142 };
142 143
143 soc@ffe00000 { 144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0x100000>;
146
144 i2c@3000 { 147 i2c@3000 {
145 rtc@68 { 148 rtc@68 {
146 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
@@ -148,17 +151,13 @@
148 }; 151 };
149 }; 152 };
150 153
151 spi@7000 { 154 spi@7000 {
152 155 flash@0 {
153 fsl_m25p80@0 {
154 #address-cells = <1>; 156 #address-cells = <1>;
155 #size-cells = <1>; 157 #size-cells = <1>;
156 compatible = "fsl,espi-flash"; 158 compatible = "spansion,s25sl12801";
157 reg = <0>; 159 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>; 160 spi-max-frequency = <50000000>;
161 mode = <0>;
162 161
163 partition@0 { 162 partition@0 {
164 /* 512KB for u-boot Bootloader Image */ 163 /* 512KB for u-boot Bootloader Image */
@@ -202,15 +201,17 @@
202 201
203 mdio@24520 { 202 mdio@24520 {
204 phy0: ethernet-phy@0 { 203 phy0: ethernet-phy@0 {
205 interrupt-parent = <&mpic>; 204 interrupts = <3 1 0 0>;
206 interrupts = <3 1>;
207 reg = <0x0>; 205 reg = <0x0>;
208 }; 206 };
209 phy1: ethernet-phy@1 { 207 phy1: ethernet-phy@1 {
210 interrupt-parent = <&mpic>; 208 interrupts = <3 1 0 0>;
211 interrupts = <3 1>;
212 reg = <0x1>; 209 reg = <0x1>;
213 }; 210 };
211 tbi-phy@2 {
212 device_type = "tbi-phy";
213 reg = <0x2>;
214 };
214 }; 215 };
215 216
216 mdio@25520 { 217 mdio@25520 {
@@ -224,11 +225,7 @@
224 status = "disabled"; 225 status = "disabled";
225 }; 226 };
226 227
227 ptp_clock@24E00 { 228 ptp_clock@24e00 {
228 compatible = "fsl,etsec-ptp";
229 reg = <0x24E00 0xB0>;
230 interrupts = <68 2 69 2 70 2>;
231 interrupt-parent = < &mpic >;
232 fsl,tclk-period = <5>; 229 fsl,tclk-period = <5>;
233 fsl,tmr-prsc = <200>; 230 fsl,tmr-prsc = <200>;
234 fsl,tmr-add = <0xCCCCCCCD>; 231 fsl,tmr-add = <0xCCCCCCCD>;
@@ -252,29 +249,18 @@
252 phy-handle = <&phy1>; 249 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id"; 250 phy-connection-type = "rgmii-id";
254 }; 251 };
255
256 }; 252 };
257 253
258 pci0: pcie@ffe08000 { 254 pci0: pcie@ffe08000 {
255 reg = <0 0xffe08000 0 0x1000>;
259 status = "disabled"; 256 status = "disabled";
260 }; 257 };
261 258
262 pci1: pcie@ffe09000 { 259 pci1: pcie@ffe09000 {
260 reg = <0 0xffe09000 0 0x1000>;
263 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 261 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
264 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 262 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
265 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 263 pcie@0 {
266 interrupt-map = <
267 /* IDSEL 0x0 */
268 0000 0x0 0x0 0x1 &mpic 0x4 0x1
269 0000 0x0 0x0 0x2 &mpic 0x5 0x1
270 0000 0x0 0x0 0x3 &mpic 0x6 0x1
271 0000 0x0 0x0 0x4 &mpic 0x7 0x1
272 >;
273 pcie@0 {
274 reg = <0x0 0x0 0x0 0x0 0x0>;
275 #size-cells = <2>;
276 #address-cells = <3>;
277 device_type = "pci";
278 ranges = <0x2000000 0x0 0xa0000000 264 ranges = <0x2000000 0x0 0xa0000000
279 0x2000000 0x0 0xa0000000 265 0x2000000 0x0 0xa0000000
280 0x0 0x20000000 266 0x0 0x20000000
@@ -286,21 +272,10 @@
286 }; 272 };
287 273
288 pci2: pcie@ffe0a000 { 274 pci2: pcie@ffe0a000 {
275 reg = <0 0xffe0a000 0 0x1000>;
289 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 276 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
290 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 277 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = <
293 /* IDSEL 0x0 */
294 0000 0x0 0x0 0x1 &mpic 0x0 0x1
295 0000 0x0 0x0 0x2 &mpic 0x1 0x1
296 0000 0x0 0x0 0x3 &mpic 0x2 0x1
297 0000 0x0 0x0 0x4 &mpic 0x3 0x1
298 >;
299 pcie@0 { 278 pcie@0 {
300 reg = <0x0 0x0 0x0 0x0 0x0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x2000000 0x0 0x80000000 279 ranges = <0x2000000 0x0 0x80000000
305 0x2000000 0x0 0x80000000 280 0x2000000 0x0 0x80000000
306 0x0 0x20000000 281 0x0 0x20000000
@@ -311,3 +286,5 @@
311 }; 286 };
312 }; 287 };
313}; 288};
289
290/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8ddddfccb..66aac864c4c 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,28 +14,16 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/include/ "p2020si.dtsi" 17/include/ "p2020rdb.dts"
18 18
19/ { 19/ {
20 model = "fsl,P2020RDB"; 20 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 22
23 aliases {
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 serial0 = &serial0;
27 pci0 = &pci0;
28 };
29
30 cpus { 23 cpus {
31 PowerPC,P2020@1 { 24 PowerPC,P2020@1 {
32 status = "disabled"; 25 status = "disabled";
33 }; 26 };
34
35 };
36
37 memory {
38 device_type = "memory";
39 }; 27 };
40 28
41 localbus@ffe05000 { 29 localbus@ffe05000 {
@@ -43,115 +31,18 @@
43 }; 31 };
44 32
45 soc@ffe00000 { 33 soc@ffe00000 {
46 i2c@3000 {
47 rtc@68 {
48 compatible = "dallas,ds1339";
49 reg = <0x68>;
50 };
51 };
52
53 serial1: serial@4600 { 34 serial1: serial@4600 {
54 status = "disabled"; 35 status = "disabled";
55 }; 36 };
56 37
57 spi@7000 {
58
59 fsl_m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "fsl,espi-flash";
63 reg = <0>;
64 linux,modalias = "fsl_m25p80";
65 modal = "s25sl128b";
66 spi-max-frequency = <50000000>;
67 mode = <0>;
68
69 partition@0 {
70 /* 512KB for u-boot Bootloader Image */
71 reg = <0x0 0x00080000>;
72 label = "SPI (RO) U-Boot Image";
73 read-only;
74 };
75
76 partition@80000 {
77 /* 512KB for DTB Image */
78 reg = <0x00080000 0x00080000>;
79 label = "SPI (RO) DTB Image";
80 read-only;
81 };
82
83 partition@100000 {
84 /* 4MB for Linux Kernel Image */
85 reg = <0x00100000 0x00400000>;
86 label = "SPI (RO) Linux Kernel Image";
87 read-only;
88 };
89
90 partition@500000 {
91 /* 4MB for Compressed RFS Image */
92 reg = <0x00500000 0x00400000>;
93 label = "SPI (RO) Compressed RFS Image";
94 read-only;
95 };
96
97 partition@900000 {
98 /* 7MB for JFFS2 based RFS */
99 reg = <0x00900000 0x00700000>;
100 label = "SPI (RW) JFFS2 RFS";
101 };
102 };
103 };
104
105 dma@c300 { 38 dma@c300 {
106 status = "disabled"; 39 status = "disabled";
107 }; 40 };
108 41
109 usb@22000 {
110 phy_type = "ulpi";
111 };
112
113 mdio@24520 {
114
115 phy0: ethernet-phy@0 {
116 interrupt-parent = <&mpic>;
117 interrupts = <3 1>;
118 reg = <0x0>;
119 };
120 phy1: ethernet-phy@1 {
121 interrupt-parent = <&mpic>;
122 interrupts = <3 1>;
123 reg = <0x1>;
124 };
125 };
126
127 mdio@25520 {
128 tbi0: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 { 42 enet0: ethernet@24000 {
139 status = "disabled"; 43 status = "disabled";
140 }; 44 };
141 45
142 enet1: ethernet@25000 {
143 tbi-handle = <&tbi0>;
144 phy-handle = <&phy0>;
145 phy-connection-type = "sgmii";
146
147 };
148
149 enet2: ethernet@26000 {
150 phy-handle = <&phy1>;
151 phy-connection-type = "rgmii-id";
152 };
153
154
155 mpic: pic@40000 { 46 mpic: pic@40000 {
156 protected-sources = < 47 protected-sources = <
157 42 76 77 78 79 /* serial1 , dma2 */ 48 42 76 77 78 79 /* serial1 , dma2 */
@@ -164,40 +55,12 @@
164 msi@41600 { 55 msi@41600 {
165 status = "disabled"; 56 status = "disabled";
166 }; 57 };
167
168
169 }; 58 };
170 59
171 pci0: pcie@ffe08000 { 60 pci0: pcie@ffe08000 {
172 status = "disabled"; 61 status = "disabled";
173 }; 62 };
174 63
175 pci1: pcie@ffe09000 {
176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
179 interrupt-map = <
180 /* IDSEL 0x0 */
181 0000 0x0 0x0 0x1 &mpic 0x4 0x1
182 0000 0x0 0x0 0x2 &mpic 0x5 0x1
183 0000 0x0 0x0 0x3 &mpic 0x6 0x1
184 0000 0x0 0x0 0x4 &mpic 0x7 0x1
185 >;
186 pcie@0 {
187 reg = <0x0 0x0 0x0 0x0 0x0>;
188 #size-cells = <2>;
189 #address-cells = <3>;
190 device_type = "pci";
191 ranges = <0x2000000 0x0 0xa0000000
192 0x2000000 0x0 0xa0000000
193 0x0 0x20000000
194
195 0x1000000 0x0 0x0
196 0x1000000 0x0 0x0
197 0x0 0x100000>;
198 };
199 };
200
201 pci2: pcie@ffe0a000 { 64 pci2: pcie@ffe0a000 {
202 status = "disabled"; 65 status = "disabled";
203 }; 66 };
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 261c34ba45e..9bd8ef493dd 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,28 +15,18 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/include/ "p2020si.dtsi" 18/include/ "p2020rdb.dts"
19 19
20/ { 20/ {
21 model = "fsl,P2020RDB"; 21 model = "fsl,P2020RDB";
22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
23 23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 pci1 = &pci1;
28 };
29
30 cpus { 24 cpus {
31 PowerPC,P2020@0 { 25 PowerPC,P2020@0 {
32 status = "disabled"; 26 status = "disabled";
33 }; 27 };
34 }; 28 };
35 29
36 memory {
37 device_type = "memory";
38 };
39
40 localbus@ffe05000 { 30 localbus@ffe05000 {
41 status = "disabled"; 31 status = "disabled";
42 }; 32 };
@@ -70,55 +60,10 @@
70 status = "disabled"; 60 status = "disabled";
71 }; 61 };
72 62
73 dma@c300 {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 compatible = "fsl,eloplus-dma";
77 reg = <0xc300 0x4>;
78 ranges = <0x0 0xc100 0x200>;
79 cell-index = <1>;
80 dma-channel@0 {
81 compatible = "fsl,eloplus-dma-channel";
82 reg = <0x0 0x80>;
83 cell-index = <0>;
84 interrupt-parent = <&mpic>;
85 interrupts = <76 2>;
86 };
87 dma-channel@80 {
88 compatible = "fsl,eloplus-dma-channel";
89 reg = <0x80 0x80>;
90 cell-index = <1>;
91 interrupt-parent = <&mpic>;
92 interrupts = <77 2>;
93 };
94 dma-channel@100 {
95 compatible = "fsl,eloplus-dma-channel";
96 reg = <0x100 0x80>;
97 cell-index = <2>;
98 interrupt-parent = <&mpic>;
99 interrupts = <78 2>;
100 };
101 dma-channel@180 {
102 compatible = "fsl,eloplus-dma-channel";
103 reg = <0x180 0x80>;
104 cell-index = <3>;
105 interrupt-parent = <&mpic>;
106 interrupts = <79 2>;
107 };
108 };
109
110 gpio: gpio-controller@f000 { 63 gpio: gpio-controller@f000 {
111 status = "disabled"; 64 status = "disabled";
112 }; 65 };
113 66
114 L2: l2-cache-controller@20000 {
115 compatible = "fsl,p2020-l2-cache-controller";
116 reg = <0x20000 0x1000>;
117 cache-line-size = <32>; // 32 bytes
118 cache-size = <0x80000>; // L2,512K
119 interrupt-parent = <&mpic>;
120 };
121
122 dma@21300 { 67 dma@21300 {
123 status = "disabled"; 68 status = "disabled";
124 }; 69 };
@@ -139,12 +84,6 @@
139 status = "disabled"; 84 status = "disabled";
140 }; 85 };
141 86
142 enet0: ethernet@24000 {
143 fixed-link = <1 1 1000 0 0>;
144 phy-connection-type = "rgmii-id";
145
146 };
147
148 enet1: ethernet@25000 { 87 enet1: ethernet@25000 {
149 status = "disabled"; 88 status = "disabled";
150 }; 89 };
@@ -170,22 +109,6 @@
170 >; 109 >;
171 }; 110 };
172 111
173 msi@41600 {
174 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
175 reg = <0x41600 0x80>;
176 msi-available-ranges = <0 0x100>;
177 interrupts = <
178 0xe0 0
179 0xe1 0
180 0xe2 0
181 0xe3 0
182 0xe4 0
183 0xe5 0
184 0xe6 0
185 0xe7 0>;
186 interrupt-parent = <&mpic>;
187 };
188
189 global-utilities@e0000 { //global utilities block 112 global-utilities@e0000 { //global utilities block
190 status = "disabled"; 113 status = "disabled";
191 }; 114 };
@@ -199,30 +122,4 @@
199 pci1: pcie@ffe09000 { 122 pci1: pcie@ffe09000 {
200 status = "disabled"; 123 status = "disabled";
201 }; 124 };
202
203 pci2: pcie@ffe0a000 {
204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
206 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
207 interrupt-map = <
208 /* IDSEL 0x0 */
209 0000 0x0 0x0 0x1 &mpic 0x0 0x1
210 0000 0x0 0x0 0x2 &mpic 0x1 0x1
211 0000 0x0 0x0 0x3 &mpic 0x2 0x1
212 0000 0x0 0x0 0x4 &mpic 0x3 0x1
213 >;
214 pcie@0 {
215 reg = <0x0 0x0 0x0 0x0 0x0>;
216 #size-cells = <2>;
217 #address-cells = <3>;
218 device_type = "pci";
219 ranges = <0x2000000 0x0 0x80000000
220 0x2000000 0x0 0x80000000
221 0x0 0x20000000
222
223 0x1000000 0x0 0x0
224 0x1000000 0x0 0x0
225 0x0 0x100000>;
226 };
227 };
228}; 125};
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
deleted file mode 100644
index 6def17f265d..00000000000
--- a/arch/powerpc/boot/dts/p2020si.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P2020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P2020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 dma@c300 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,eloplus-dma";
129 reg = <0xc300 0x4>;
130 ranges = <0x0 0xc100 0x200>;
131 cell-index = <1>;
132 dma-channel@0 {
133 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <76 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>;
142 cell-index = <1>;
143 interrupt-parent = <&mpic>;
144 interrupts = <77 2>;
145 };
146 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <78 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>;
156 cell-index = <3>;
157 interrupt-parent = <&mpic>;
158 interrupts = <79 2>;
159 };
160 };
161
162 gpio: gpio-controller@f000 {
163 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>;
167 interrupt-parent = <&mpic>;
168 gpio-controller;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,p2020-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 dma@21300 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "fsl,eloplus-dma";
184 reg = <0x21300 0x4>;
185 ranges = <0x0 0x21100 0x200>;
186 cell-index = <0>;
187 dma-channel@0 {
188 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>;
190 cell-index = <0>;
191 interrupt-parent = <&mpic>;
192 interrupts = <20 2>;
193 };
194 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>;
197 cell-index = <1>;
198 interrupt-parent = <&mpic>;
199 interrupts = <21 2>;
200 };
201 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>;
204 cell-index = <2>;
205 interrupt-parent = <&mpic>;
206 interrupts = <22 2>;
207 };
208 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 usb@22000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>;
223 interrupts = <28 0x2>;
224 };
225
226 mdio@24520 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,gianfar-mdio";
230 reg = <0x24520 0x20>;
231 };
232
233 mdio@25520 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,gianfar-tbi";
237 reg = <0x26520 0x20>;
238 };
239
240 mdio@26520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-tbi";
244 reg = <0x520 0x20>;
245 };
246
247 enet0: ethernet@24000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <0>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>;
258 interrupt-parent = <&mpic>;
259 };
260
261 enet1: ethernet@25000 {
262 #address-cells = <1>;
263 #size-cells = <1>;
264 cell-index = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>;
272 interrupt-parent = <&mpic>;
273
274 };
275
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288
289 };
290
291 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */
297 clock-frequency = <0>;
298 };
299
300 crypto@30000 {
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>;
309 fsl,descriptor-types-mask = <0x3ab0ebf>;
310 };
311
312 mpic: pic@40000 {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <0x40000 0x40000>;
317 compatible = "chrp,open-pic";
318 device_type = "open-pic";
319 };
320
321 msi@41600 {
322 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
323 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>;
325 interrupts = <
326 0xe0 0
327 0xe1 0
328 0xe2 0
329 0xe3 0
330 0xe4 0
331 0xe5 0
332 0xe6 0
333 0xe7 0>;
334 interrupt-parent = <&mpic>;
335 };
336
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,p2020-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
343
344 pci0: pcie@ffe08000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
354 interrupts = <24 2>;
355 };
356
357 pci1: pcie@ffe09000 {
358 compatible = "fsl,mpc8548-pcie";
359 device_type = "pci";
360 #interrupt-cells = <1>;
361 #size-cells = <2>;
362 #address-cells = <3>;
363 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <25 2>;
368 };
369
370 pci2: pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>;
378 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>;
380 interrupts = <26 2>;
381 };
382};
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 79b6895027c..4f957db0123 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p2041si.dtsi" 35/include/ "fsl/p2041si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P2041RDB"; 38 model = "fsl,P2041RDB";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -106,7 +108,18 @@
106 }; 108 };
107 }; 109 };
108 110
109 localbus@ffe124000 { 111 rio: rapidio@ffe0c0000 {
112 reg = <0xf 0xfe0c0000 0 0x11000>;
113
114 port1 {
115 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
116 };
117 port2 {
118 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
119 };
120 };
121
122 lbc: localbus@ffe124000 {
110 reg = <0xf 0xfe124000 0 0x1000>; 123 reg = <0xf 0xfe124000 0 0x1000>;
111 ranges = <0 0 0xf 0xe8000000 0x08000000>; 124 ranges = <0 0 0xf 0xe8000000 0x08000000>;
112 125
@@ -122,6 +135,7 @@
122 reg = <0xf 0xfe200000 0 0x1000>; 135 reg = <0xf 0xfe200000 0 0x1000>;
123 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 136 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
124 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 137 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
138 fsl,msi = <&msi0>;
125 pcie@0 { 139 pcie@0 {
126 ranges = <0x02000000 0 0xe0000000 140 ranges = <0x02000000 0 0xe0000000
127 0x02000000 0 0xe0000000 141 0x02000000 0 0xe0000000
@@ -137,6 +151,7 @@
137 reg = <0xf 0xfe201000 0 0x1000>; 151 reg = <0xf 0xfe201000 0 0x1000>;
138 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 152 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
139 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 153 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
154 fsl,msi = <&msi1>;
140 pcie@0 { 155 pcie@0 {
141 ranges = <0x02000000 0 0xe0000000 156 ranges = <0x02000000 0 0xe0000000
142 0x02000000 0 0xe0000000 157 0x02000000 0 0xe0000000
@@ -152,6 +167,7 @@
152 reg = <0xf 0xfe202000 0 0x1000>; 167 reg = <0xf 0xfe202000 0 0x1000>;
153 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 168 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
154 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 169 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
170 fsl,msi = <&msi2>;
155 pcie@0 { 171 pcie@0 {
156 ranges = <0x02000000 0 0xe0000000 172 ranges = <0x02000000 0 0xe0000000
157 0x02000000 0 0xe0000000 173 0x02000000 0 0xe0000000
@@ -163,3 +179,5 @@
163 }; 179 };
164 }; 180 };
165}; 181};
182
183/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2041si.dtsi b/arch/powerpc/boot/dts/p2041si.dtsi
deleted file mode 100644
index f7492edd0df..00000000000
--- a/arch/powerpc/boot/dts/p2041si.dtsi
+++ /dev/null
@@ -1,692 +0,0 @@
1/*
2 * P2041 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P2041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e500mc@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e500mc@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 cpu2: PowerPC,e500mc@2 {
96 device_type = "cpu";
97 reg = <2>;
98 next-level-cache = <&L2_2>;
99 L2_2: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 cpu3: PowerPC,e500mc@3 {
104 device_type = "cpu";
105 reg = <3>;
106 next-level-cache = <&L2_3>;
107 L2_3: l2-cache {
108 next-level-cache = <&cpc>;
109 };
110 };
111 };
112
113 dcsr: dcsr@f00000000 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,dcsr", "simple-bus";
117
118 dcsr-epu@0 {
119 compatible = "fsl,dcsr-epu";
120 interrupts = <52 2 0 0
121 84 2 0 0
122 85 2 0 0>;
123 interrupt-parent = <&mpic>;
124 reg = <0x0 0x1000>;
125 };
126 dcsr-npc {
127 compatible = "fsl,dcsr-npc";
128 reg = <0x1000 0x1000 0x1000000 0x8000>;
129 };
130 dcsr-nxc@2000 {
131 compatible = "fsl,dcsr-nxc";
132 reg = <0x2000 0x1000>;
133 };
134 dcsr-corenet {
135 compatible = "fsl,dcsr-corenet";
136 reg = <0x8000 0x1000 0xB0000 0x1000>;
137 };
138 dcsr-dpaa@9000 {
139 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
140 reg = <0x9000 0x1000>;
141 };
142 dcsr-ocn@11000 {
143 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
144 reg = <0x11000 0x1000>;
145 };
146 dcsr-ddr@12000 {
147 compatible = "fsl,dcsr-ddr";
148 dev-handle = <&ddr>;
149 reg = <0x12000 0x1000>;
150 };
151 dcsr-nal@18000 {
152 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
153 reg = <0x18000 0x1000>;
154 };
155 dcsr-rcpm@22000 {
156 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
157 reg = <0x22000 0x1000>;
158 };
159 dcsr-cpu-sb-proxy@40000 {
160 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
161 cpu-handle = <&cpu0>;
162 reg = <0x40000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@41000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu1>;
167 reg = <0x41000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@42000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu2>;
172 reg = <0x42000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@43000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu3>;
177 reg = <0x43000 0x1000>;
178 };
179 };
180
181 soc: soc@ffe000000 {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 device_type = "soc";
185 compatible = "simple-bus";
186 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
187 reg = <0xf 0xfe000000 0 0x00001000>;
188
189 soc-sram-error {
190 compatible = "fsl,soc-sram-error";
191 interrupts = <16 2 1 29>;
192 };
193
194 corenet-law@0 {
195 compatible = "fsl,corenet-law";
196 reg = <0x0 0x1000>;
197 fsl,num-laws = <32>;
198 };
199
200 ddr: memory-controller@8000 {
201 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
202 reg = <0x8000 0x1000>;
203 interrupts = <16 2 1 23>;
204 };
205
206 cpc: l3-cache-controller@10000 {
207 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
208 reg = <0x10000 0x1000>;
209 interrupts = <16 2 1 27>;
210 };
211
212 corenet-cf@18000 {
213 compatible = "fsl,corenet-cf";
214 reg = <0x18000 0x1000>;
215 interrupts = <16 2 1 31>;
216 fsl,ccf-num-csdids = <32>;
217 fsl,ccf-num-snoopids = <32>;
218 };
219
220 iommu@20000 {
221 compatible = "fsl,pamu-v1.0", "fsl,pamu";
222 reg = <0x20000 0x4000>;
223 interrupts = <
224 24 2 0 0
225 16 2 1 30>;
226 };
227
228 mpic: pic@40000 {
229 clock-frequency = <0>;
230 interrupt-controller;
231 #address-cells = <0>;
232 #interrupt-cells = <4>;
233 reg = <0x40000 0x40000>;
234 compatible = "fsl,mpic", "chrp,open-pic";
235 device_type = "open-pic";
236 };
237
238 msi0: msi@41600 {
239 compatible = "fsl,mpic-msi";
240 reg = <0x41600 0x200>;
241 msi-available-ranges = <0 0x100>;
242 interrupts = <
243 0xe0 0 0 0
244 0xe1 0 0 0
245 0xe2 0 0 0
246 0xe3 0 0 0
247 0xe4 0 0 0
248 0xe5 0 0 0
249 0xe6 0 0 0
250 0xe7 0 0 0>;
251 };
252
253 msi1: msi@41800 {
254 compatible = "fsl,mpic-msi";
255 reg = <0x41800 0x200>;
256 msi-available-ranges = <0 0x100>;
257 interrupts = <
258 0xe8 0 0 0
259 0xe9 0 0 0
260 0xea 0 0 0
261 0xeb 0 0 0
262 0xec 0 0 0
263 0xed 0 0 0
264 0xee 0 0 0
265 0xef 0 0 0>;
266 };
267
268 msi2: msi@41a00 {
269 compatible = "fsl,mpic-msi";
270 reg = <0x41a00 0x200>;
271 msi-available-ranges = <0 0x100>;
272 interrupts = <
273 0xf0 0 0 0
274 0xf1 0 0 0
275 0xf2 0 0 0
276 0xf3 0 0 0
277 0xf4 0 0 0
278 0xf5 0 0 0
279 0xf6 0 0 0
280 0xf7 0 0 0>;
281 };
282
283 guts: global-utilities@e0000 {
284 compatible = "fsl,qoriq-device-config-1.0";
285 reg = <0xe0000 0xe00>;
286 fsl,has-rstcr;
287 #sleep-cells = <1>;
288 fsl,liodn-bits = <12>;
289 };
290
291 pins: global-utilities@e0e00 {
292 compatible = "fsl,qoriq-pin-control-1.0";
293 reg = <0xe0e00 0x200>;
294 #sleep-cells = <2>;
295 };
296
297 clockgen: global-utilities@e1000 {
298 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
299 reg = <0xe1000 0x1000>;
300 clock-frequency = <0>;
301 };
302
303 rcpm: global-utilities@e2000 {
304 compatible = "fsl,qoriq-rcpm-1.0";
305 reg = <0xe2000 0x1000>;
306 #sleep-cells = <1>;
307 };
308
309 sfp: sfp@e8000 {
310 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
311 reg = <0xe8000 0x1000>;
312 };
313
314 serdes: serdes@ea000 {
315 compatible = "fsl,p2041-serdes";
316 reg = <0xea000 0x1000>;
317 };
318
319 dma0: dma@100300 {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
323 reg = <0x100300 0x4>;
324 ranges = <0x0 0x100100 0x200>;
325 cell-index = <0>;
326 dma-channel@0 {
327 compatible = "fsl,p2041-dma-channel",
328 "fsl,eloplus-dma-channel";
329 reg = <0x0 0x80>;
330 cell-index = <0>;
331 interrupts = <28 2 0 0>;
332 };
333 dma-channel@80 {
334 compatible = "fsl,p2041-dma-channel",
335 "fsl,eloplus-dma-channel";
336 reg = <0x80 0x80>;
337 cell-index = <1>;
338 interrupts = <29 2 0 0>;
339 };
340 dma-channel@100 {
341 compatible = "fsl,p2041-dma-channel",
342 "fsl,eloplus-dma-channel";
343 reg = <0x100 0x80>;
344 cell-index = <2>;
345 interrupts = <30 2 0 0>;
346 };
347 dma-channel@180 {
348 compatible = "fsl,p2041-dma-channel",
349 "fsl,eloplus-dma-channel";
350 reg = <0x180 0x80>;
351 cell-index = <3>;
352 interrupts = <31 2 0 0>;
353 };
354 };
355
356 dma1: dma@101300 {
357 #address-cells = <1>;
358 #size-cells = <1>;
359 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
360 reg = <0x101300 0x4>;
361 ranges = <0x0 0x101100 0x200>;
362 cell-index = <1>;
363 dma-channel@0 {
364 compatible = "fsl,p2041-dma-channel",
365 "fsl,eloplus-dma-channel";
366 reg = <0x0 0x80>;
367 cell-index = <0>;
368 interrupts = <32 2 0 0>;
369 };
370 dma-channel@80 {
371 compatible = "fsl,p2041-dma-channel",
372 "fsl,eloplus-dma-channel";
373 reg = <0x80 0x80>;
374 cell-index = <1>;
375 interrupts = <33 2 0 0>;
376 };
377 dma-channel@100 {
378 compatible = "fsl,p2041-dma-channel",
379 "fsl,eloplus-dma-channel";
380 reg = <0x100 0x80>;
381 cell-index = <2>;
382 interrupts = <34 2 0 0>;
383 };
384 dma-channel@180 {
385 compatible = "fsl,p2041-dma-channel",
386 "fsl,eloplus-dma-channel";
387 reg = <0x180 0x80>;
388 cell-index = <3>;
389 interrupts = <35 2 0 0>;
390 };
391 };
392
393 spi@110000 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
397 reg = <0x110000 0x1000>;
398 interrupts = <53 0x2 0 0>;
399 fsl,espi-num-chipselects = <4>;
400 };
401
402 sdhc: sdhc@114000 {
403 compatible = "fsl,p2041-esdhc", "fsl,esdhc";
404 reg = <0x114000 0x1000>;
405 interrupts = <48 2 0 0>;
406 sdhci,auto-cmd12;
407 clock-frequency = <0>;
408 };
409
410 i2c@118000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 cell-index = <0>;
414 compatible = "fsl-i2c";
415 reg = <0x118000 0x100>;
416 interrupts = <38 2 0 0>;
417 dfsrr;
418 };
419
420 i2c@118100 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 cell-index = <1>;
424 compatible = "fsl-i2c";
425 reg = <0x118100 0x100>;
426 interrupts = <38 2 0 0>;
427 dfsrr;
428 };
429
430 i2c@119000 {
431 #address-cells = <1>;
432 #size-cells = <0>;
433 cell-index = <2>;
434 compatible = "fsl-i2c";
435 reg = <0x119000 0x100>;
436 interrupts = <39 2 0 0>;
437 dfsrr;
438 };
439
440 i2c@119100 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 cell-index = <3>;
444 compatible = "fsl-i2c";
445 reg = <0x119100 0x100>;
446 interrupts = <39 2 0 0>;
447 dfsrr;
448 };
449
450 serial0: serial@11c500 {
451 cell-index = <0>;
452 device_type = "serial";
453 compatible = "ns16550";
454 reg = <0x11c500 0x100>;
455 clock-frequency = <0>;
456 interrupts = <36 2 0 0>;
457 };
458
459 serial1: serial@11c600 {
460 cell-index = <1>;
461 device_type = "serial";
462 compatible = "ns16550";
463 reg = <0x11c600 0x100>;
464 clock-frequency = <0>;
465 interrupts = <36 2 0 0>;
466 };
467
468 serial2: serial@11d500 {
469 cell-index = <2>;
470 device_type = "serial";
471 compatible = "ns16550";
472 reg = <0x11d500 0x100>;
473 clock-frequency = <0>;
474 interrupts = <37 2 0 0>;
475 };
476
477 serial3: serial@11d600 {
478 cell-index = <3>;
479 device_type = "serial";
480 compatible = "ns16550";
481 reg = <0x11d600 0x100>;
482 clock-frequency = <0>;
483 interrupts = <37 2 0 0>;
484 };
485
486 gpio0: gpio@130000 {
487 compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
488 reg = <0x130000 0x1000>;
489 interrupts = <55 2 0 0>;
490 #gpio-cells = <2>;
491 gpio-controller;
492 };
493
494 usb0: usb@210000 {
495 compatible = "fsl,p2041-usb2-mph",
496 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
497 reg = <0x210000 0x1000>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 interrupts = <44 0x2 0 0>;
501 phy_type = "utmi";
502 port0;
503 };
504
505 usb1: usb@211000 {
506 compatible = "fsl,p2041-usb2-dr",
507 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
508 reg = <0x211000 0x1000>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 interrupts = <45 0x2 0 0>;
512 phy_type = "utmi";
513 };
514
515 sata@220000 {
516 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
517 reg = <0x220000 0x1000>;
518 interrupts = <68 0x2 0 0>;
519 };
520
521 sata@221000 {
522 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
523 reg = <0x221000 0x1000>;
524 interrupts = <69 0x2 0 0>;
525 };
526
527 crypto: crypto@300000 {
528 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 reg = <0x300000 0x10000>;
532 ranges = <0 0x300000 0x10000>;
533 interrupts = <92 2 0 0>;
534
535 sec_jr0: jr@1000 {
536 compatible = "fsl,sec-v4.2-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x1000 0x1000>;
539 interrupts = <88 2 0 0>;
540 };
541
542 sec_jr1: jr@2000 {
543 compatible = "fsl,sec-v4.2-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x2000 0x1000>;
546 interrupts = <89 2 0 0>;
547 };
548
549 sec_jr2: jr@3000 {
550 compatible = "fsl,sec-v4.2-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x3000 0x1000>;
553 interrupts = <90 2 0 0>;
554 };
555
556 sec_jr3: jr@4000 {
557 compatible = "fsl,sec-v4.2-job-ring",
558 "fsl,sec-v4.0-job-ring";
559 reg = <0x4000 0x1000>;
560 interrupts = <91 2 0 0>;
561 };
562
563 rtic@6000 {
564 compatible = "fsl,sec-v4.2-rtic",
565 "fsl,sec-v4.0-rtic";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 reg = <0x6000 0x100>;
569 ranges = <0x0 0x6100 0xe00>;
570
571 rtic_a: rtic-a@0 {
572 compatible = "fsl,sec-v4.2-rtic-memory",
573 "fsl,sec-v4.0-rtic-memory";
574 reg = <0x00 0x20 0x100 0x80>;
575 };
576
577 rtic_b: rtic-b@20 {
578 compatible = "fsl,sec-v4.2-rtic-memory",
579 "fsl,sec-v4.0-rtic-memory";
580 reg = <0x20 0x20 0x200 0x80>;
581 };
582
583 rtic_c: rtic-c@40 {
584 compatible = "fsl,sec-v4.2-rtic-memory",
585 "fsl,sec-v4.0-rtic-memory";
586 reg = <0x40 0x20 0x300 0x80>;
587 };
588
589 rtic_d: rtic-d@60 {
590 compatible = "fsl,sec-v4.2-rtic-memory",
591 "fsl,sec-v4.0-rtic-memory";
592 reg = <0x60 0x20 0x500 0x80>;
593 };
594 };
595 };
596
597 sec_mon: sec_mon@314000 {
598 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
599 reg = <0x314000 0x1000>;
600 interrupts = <93 2 0 0>;
601 };
602
603 };
604
605 localbus@ffe124000 {
606 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
607 interrupts = <25 2 0 0>;
608 #address-cells = <2>;
609 #size-cells = <1>;
610 };
611
612 pci0: pcie@ffe200000 {
613 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
614 device_type = "pci";
615 #size-cells = <2>;
616 #address-cells = <3>;
617 bus-range = <0x0 0xff>;
618 clock-frequency = <33333333>;
619 fsl,msi = <&msi0>;
620 interrupts = <16 2 1 15>;
621 pcie@0 {
622 reg = <0 0 0 0 0>;
623 #interrupt-cells = <1>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 device_type = "pci";
627 interrupts = <16 2 1 15>;
628 interrupt-map-mask = <0xf800 0 0 7>;
629 interrupt-map = <
630 /* IDSEL 0x0 */
631 0000 0 0 1 &mpic 40 1 0 0
632 0000 0 0 2 &mpic 1 1 0 0
633 0000 0 0 3 &mpic 2 1 0 0
634 0000 0 0 4 &mpic 3 1 0 0
635 >;
636 };
637 };
638
639 pci1: pcie@ffe201000 {
640 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
641 device_type = "pci";
642 #size-cells = <2>;
643 #address-cells = <3>;
644 bus-range = <0 0xff>;
645 clock-frequency = <33333333>;
646 fsl,msi = <&msi1>;
647 interrupts = <16 2 1 14>;
648 pcie@0 {
649 reg = <0 0 0 0 0>;
650 #interrupt-cells = <1>;
651 #size-cells = <2>;
652 #address-cells = <3>;
653 device_type = "pci";
654 interrupts = <16 2 1 14>;
655 interrupt-map-mask = <0xf800 0 0 7>;
656 interrupt-map = <
657 /* IDSEL 0x0 */
658 0000 0 0 1 &mpic 41 1 0 0
659 0000 0 0 2 &mpic 5 1 0 0
660 0000 0 0 3 &mpic 6 1 0 0
661 0000 0 0 4 &mpic 7 1 0 0
662 >;
663 };
664 };
665
666 pci2: pcie@ffe202000 {
667 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
668 device_type = "pci";
669 #size-cells = <2>;
670 #address-cells = <3>;
671 bus-range = <0x0 0xff>;
672 clock-frequency = <33333333>;
673 fsl,msi = <&msi2>;
674 interrupts = <16 2 1 13>;
675 pcie@0 {
676 reg = <0 0 0 0 0>;
677 #interrupt-cells = <1>;
678 #size-cells = <2>;
679 #address-cells = <3>;
680 device_type = "pci";
681 interrupts = <16 2 1 13>;
682 interrupt-map-mask = <0xf800 0 0 7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0000 0 0 1 &mpic 42 1 0 0
686 0000 0 0 2 &mpic 9 1 0 0
687 0000 0 0 3 &mpic 10 1 0 0
688 0000 0 0 4 &mpic 11 1 0 0
689 >;
690 };
691 };
692};
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index bbd113b49a8..f469145abae 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p3041si.dtsi" 35/include/ "fsl/p3041si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P3041DS"; 38 model = "fsl,P3041DS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -99,7 +101,18 @@
99 }; 101 };
100 }; 102 };
101 103
102 localbus@ffe124000 { 104 rio: rapidio@ffe0c0000 {
105 reg = <0xf 0xfe0c0000 0 0x11000>;
106
107 port1 {
108 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
109 };
110 port2 {
111 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
112 };
113 };
114
115 lbc: localbus@ffe124000 {
103 reg = <0xf 0xfe124000 0 0x1000>; 116 reg = <0xf 0xfe124000 0 0x1000>;
104 ranges = <0 0 0xf 0xe8000000 0x08000000 117 ranges = <0 0 0xf 0xe8000000 0x08000000
105 2 0 0xf 0xffa00000 0x00040000 118 2 0 0xf 0xffa00000 0x00040000
@@ -160,6 +173,7 @@
160 reg = <0xf 0xfe200000 0 0x1000>; 173 reg = <0xf 0xfe200000 0 0x1000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
176 fsl,msi = <&msi0>;
163 pcie@0 { 177 pcie@0 {
164 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
165 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -175,6 +189,7 @@
175 reg = <0xf 0xfe201000 0 0x1000>; 189 reg = <0xf 0xfe201000 0 0x1000>;
176 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 190 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
177 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 191 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
192 fsl,msi = <&msi1>;
178 pcie@0 { 193 pcie@0 {
179 ranges = <0x02000000 0 0xe0000000 194 ranges = <0x02000000 0 0xe0000000
180 0x02000000 0 0xe0000000 195 0x02000000 0 0xe0000000
@@ -190,6 +205,7 @@
190 reg = <0xf 0xfe202000 0 0x1000>; 205 reg = <0xf 0xfe202000 0 0x1000>;
191 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 206 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
192 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 207 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
208 fsl,msi = <&msi2>;
193 pcie@0 { 209 pcie@0 {
194 ranges = <0x02000000 0 0xe0000000 210 ranges = <0x02000000 0 0xe0000000
195 0x02000000 0 0xe0000000 211 0x02000000 0 0xe0000000
@@ -205,6 +221,7 @@
205 reg = <0xf 0xfe203000 0 0x1000>; 221 reg = <0xf 0xfe203000 0 0x1000>;
206 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 222 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
207 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 223 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
224 fsl,msi = <&msi2>;
208 pcie@0 { 225 pcie@0 {
209 ranges = <0x02000000 0 0xe0000000 226 ranges = <0x02000000 0 0xe0000000
210 0x02000000 0 0xe0000000 227 0x02000000 0 0xe0000000
@@ -216,3 +233,5 @@
216 }; 233 };
217 }; 234 };
218}; 235};
236
237/include/ "fsl/p3041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
deleted file mode 100644
index 87130b732bc..00000000000
--- a/arch/powerpc/boot/dts/p3041si.dtsi
+++ /dev/null
@@ -1,729 +0,0 @@
1/*
2 * P3041 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74
75/*
76 rio0 = &rapidio0;
77 */
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: PowerPC,e500mc@0 {
85 device_type = "cpu";
86 reg = <0>;
87 next-level-cache = <&L2_0>;
88 L2_0: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu1: PowerPC,e500mc@1 {
93 device_type = "cpu";
94 reg = <1>;
95 next-level-cache = <&L2_1>;
96 L2_1: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 cpu2: PowerPC,e500mc@2 {
101 device_type = "cpu";
102 reg = <2>;
103 next-level-cache = <&L2_2>;
104 L2_2: l2-cache {
105 next-level-cache = <&cpc>;
106 };
107 };
108 cpu3: PowerPC,e500mc@3 {
109 device_type = "cpu";
110 reg = <3>;
111 next-level-cache = <&L2_3>;
112 L2_3: l2-cache {
113 next-level-cache = <&cpc>;
114 };
115 };
116 };
117
118 dcsr: dcsr@f00000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,dcsr", "simple-bus";
122
123 dcsr-epu@0 {
124 compatible = "fsl,dcsr-epu";
125 interrupts = <52 2 0 0
126 84 2 0 0
127 85 2 0 0>;
128 interrupt-parent = <&mpic>;
129 reg = <0x0 0x1000>;
130 };
131 dcsr-npc {
132 compatible = "fsl,dcsr-npc";
133 reg = <0x1000 0x1000 0x1000000 0x8000>;
134 };
135 dcsr-nxc@2000 {
136 compatible = "fsl,dcsr-nxc";
137 reg = <0x2000 0x1000>;
138 };
139 dcsr-corenet {
140 compatible = "fsl,dcsr-corenet";
141 reg = <0x8000 0x1000 0xB0000 0x1000>;
142 };
143 dcsr-dpaa@9000 {
144 compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
145 reg = <0x9000 0x1000>;
146 };
147 dcsr-ocn@11000 {
148 compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
149 reg = <0x11000 0x1000>;
150 };
151 dcsr-ddr@12000 {
152 compatible = "fsl,dcsr-ddr";
153 dev-handle = <&ddr>;
154 reg = <0x12000 0x1000>;
155 };
156 dcsr-nal@18000 {
157 compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
158 reg = <0x18000 0x1000>;
159 };
160 dcsr-rcpm@22000 {
161 compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
162 reg = <0x22000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@40000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu0>;
167 reg = <0x40000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@41000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu1>;
172 reg = <0x41000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@42000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu2>;
177 reg = <0x42000 0x1000>;
178 };
179 dcsr-cpu-sb-proxy@43000 {
180 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
181 cpu-handle = <&cpu3>;
182 reg = <0x43000 0x1000>;
183 };
184 };
185
186 soc: soc@ffe000000 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 device_type = "soc";
190 compatible = "simple-bus";
191 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
192 reg = <0xf 0xfe000000 0 0x00001000>;
193
194 soc-sram-error {
195 compatible = "fsl,soc-sram-error";
196 interrupts = <16 2 1 29>;
197 };
198
199 corenet-law@0 {
200 compatible = "fsl,corenet-law";
201 reg = <0x0 0x1000>;
202 fsl,num-laws = <32>;
203 };
204
205 ddr: memory-controller@8000 {
206 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
207 reg = <0x8000 0x1000>;
208 interrupts = <16 2 1 23>;
209 };
210
211 cpc: l3-cache-controller@10000 {
212 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
213 reg = <0x10000 0x1000>;
214 interrupts = <16 2 1 27>;
215 };
216
217 corenet-cf@18000 {
218 compatible = "fsl,corenet-cf";
219 reg = <0x18000 0x1000>;
220 interrupts = <16 2 1 31>;
221 fsl,ccf-num-csdids = <32>;
222 fsl,ccf-num-snoopids = <32>;
223 };
224
225 iommu@20000 {
226 compatible = "fsl,pamu-v1.0", "fsl,pamu";
227 reg = <0x20000 0x4000>;
228 interrupts = <
229 24 2 0 0
230 16 2 1 30>;
231 };
232
233 mpic: pic@40000 {
234 clock-frequency = <0>;
235 interrupt-controller;
236 #address-cells = <0>;
237 #interrupt-cells = <4>;
238 reg = <0x40000 0x40000>;
239 compatible = "fsl,mpic", "chrp,open-pic";
240 device_type = "open-pic";
241 };
242
243 msi0: msi@41600 {
244 compatible = "fsl,mpic-msi";
245 reg = <0x41600 0x200>;
246 msi-available-ranges = <0 0x100>;
247 interrupts = <
248 0xe0 0 0 0
249 0xe1 0 0 0
250 0xe2 0 0 0
251 0xe3 0 0 0
252 0xe4 0 0 0
253 0xe5 0 0 0
254 0xe6 0 0 0
255 0xe7 0 0 0>;
256 };
257
258 msi1: msi@41800 {
259 compatible = "fsl,mpic-msi";
260 reg = <0x41800 0x200>;
261 msi-available-ranges = <0 0x100>;
262 interrupts = <
263 0xe8 0 0 0
264 0xe9 0 0 0
265 0xea 0 0 0
266 0xeb 0 0 0
267 0xec 0 0 0
268 0xed 0 0 0
269 0xee 0 0 0
270 0xef 0 0 0>;
271 };
272
273 msi2: msi@41a00 {
274 compatible = "fsl,mpic-msi";
275 reg = <0x41a00 0x200>;
276 msi-available-ranges = <0 0x100>;
277 interrupts = <
278 0xf0 0 0 0
279 0xf1 0 0 0
280 0xf2 0 0 0
281 0xf3 0 0 0
282 0xf4 0 0 0
283 0xf5 0 0 0
284 0xf6 0 0 0
285 0xf7 0 0 0>;
286 };
287
288 guts: global-utilities@e0000 {
289 compatible = "fsl,qoriq-device-config-1.0";
290 reg = <0xe0000 0xe00>;
291 fsl,has-rstcr;
292 #sleep-cells = <1>;
293 fsl,liodn-bits = <12>;
294 };
295
296 pins: global-utilities@e0e00 {
297 compatible = "fsl,qoriq-pin-control-1.0";
298 reg = <0xe0e00 0x200>;
299 #sleep-cells = <2>;
300 };
301
302 clockgen: global-utilities@e1000 {
303 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
304 reg = <0xe1000 0x1000>;
305 clock-frequency = <0>;
306 };
307
308 rcpm: global-utilities@e2000 {
309 compatible = "fsl,qoriq-rcpm-1.0";
310 reg = <0xe2000 0x1000>;
311 #sleep-cells = <1>;
312 };
313
314 sfp: sfp@e8000 {
315 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
316 reg = <0xe8000 0x1000>;
317 };
318
319 serdes: serdes@ea000 {
320 compatible = "fsl,p3041-serdes";
321 reg = <0xea000 0x1000>;
322 };
323
324 dma0: dma@100300 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
328 reg = <0x100300 0x4>;
329 ranges = <0x0 0x100100 0x200>;
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,p3041-dma-channel",
333 "fsl,eloplus-dma-channel";
334 reg = <0x0 0x80>;
335 cell-index = <0>;
336 interrupts = <28 2 0 0>;
337 };
338 dma-channel@80 {
339 compatible = "fsl,p3041-dma-channel",
340 "fsl,eloplus-dma-channel";
341 reg = <0x80 0x80>;
342 cell-index = <1>;
343 interrupts = <29 2 0 0>;
344 };
345 dma-channel@100 {
346 compatible = "fsl,p3041-dma-channel",
347 "fsl,eloplus-dma-channel";
348 reg = <0x100 0x80>;
349 cell-index = <2>;
350 interrupts = <30 2 0 0>;
351 };
352 dma-channel@180 {
353 compatible = "fsl,p3041-dma-channel",
354 "fsl,eloplus-dma-channel";
355 reg = <0x180 0x80>;
356 cell-index = <3>;
357 interrupts = <31 2 0 0>;
358 };
359 };
360
361 dma1: dma@101300 {
362 #address-cells = <1>;
363 #size-cells = <1>;
364 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
365 reg = <0x101300 0x4>;
366 ranges = <0x0 0x101100 0x200>;
367 cell-index = <1>;
368 dma-channel@0 {
369 compatible = "fsl,p3041-dma-channel",
370 "fsl,eloplus-dma-channel";
371 reg = <0x0 0x80>;
372 cell-index = <0>;
373 interrupts = <32 2 0 0>;
374 };
375 dma-channel@80 {
376 compatible = "fsl,p3041-dma-channel",
377 "fsl,eloplus-dma-channel";
378 reg = <0x80 0x80>;
379 cell-index = <1>;
380 interrupts = <33 2 0 0>;
381 };
382 dma-channel@100 {
383 compatible = "fsl,p3041-dma-channel",
384 "fsl,eloplus-dma-channel";
385 reg = <0x100 0x80>;
386 cell-index = <2>;
387 interrupts = <34 2 0 0>;
388 };
389 dma-channel@180 {
390 compatible = "fsl,p3041-dma-channel",
391 "fsl,eloplus-dma-channel";
392 reg = <0x180 0x80>;
393 cell-index = <3>;
394 interrupts = <35 2 0 0>;
395 };
396 };
397
398 spi@110000 {
399 #address-cells = <1>;
400 #size-cells = <0>;
401 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
402 reg = <0x110000 0x1000>;
403 interrupts = <53 0x2 0 0>;
404 fsl,espi-num-chipselects = <4>;
405 };
406
407 sdhc: sdhc@114000 {
408 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
409 reg = <0x114000 0x1000>;
410 interrupts = <48 2 0 0>;
411 sdhci,auto-cmd12;
412 clock-frequency = <0>;
413 };
414
415 i2c@118000 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 cell-index = <0>;
419 compatible = "fsl-i2c";
420 reg = <0x118000 0x100>;
421 interrupts = <38 2 0 0>;
422 dfsrr;
423 };
424
425 i2c@118100 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 cell-index = <1>;
429 compatible = "fsl-i2c";
430 reg = <0x118100 0x100>;
431 interrupts = <38 2 0 0>;
432 dfsrr;
433 };
434
435 i2c@119000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 cell-index = <2>;
439 compatible = "fsl-i2c";
440 reg = <0x119000 0x100>;
441 interrupts = <39 2 0 0>;
442 dfsrr;
443 };
444
445 i2c@119100 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 cell-index = <3>;
449 compatible = "fsl-i2c";
450 reg = <0x119100 0x100>;
451 interrupts = <39 2 0 0>;
452 dfsrr;
453 };
454
455 serial0: serial@11c500 {
456 cell-index = <0>;
457 device_type = "serial";
458 compatible = "ns16550";
459 reg = <0x11c500 0x100>;
460 clock-frequency = <0>;
461 interrupts = <36 2 0 0>;
462 };
463
464 serial1: serial@11c600 {
465 cell-index = <1>;
466 device_type = "serial";
467 compatible = "ns16550";
468 reg = <0x11c600 0x100>;
469 clock-frequency = <0>;
470 interrupts = <36 2 0 0>;
471 };
472
473 serial2: serial@11d500 {
474 cell-index = <2>;
475 device_type = "serial";
476 compatible = "ns16550";
477 reg = <0x11d500 0x100>;
478 clock-frequency = <0>;
479 interrupts = <37 2 0 0>;
480 };
481
482 serial3: serial@11d600 {
483 cell-index = <3>;
484 device_type = "serial";
485 compatible = "ns16550";
486 reg = <0x11d600 0x100>;
487 clock-frequency = <0>;
488 interrupts = <37 2 0 0>;
489 };
490
491 gpio0: gpio@130000 {
492 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
493 reg = <0x130000 0x1000>;
494 interrupts = <55 2 0 0>;
495 #gpio-cells = <2>;
496 gpio-controller;
497 };
498
499 usb0: usb@210000 {
500 compatible = "fsl,p3041-usb2-mph",
501 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
502 reg = <0x210000 0x1000>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 interrupts = <44 0x2 0 0>;
506 phy_type = "utmi";
507 port0;
508 };
509
510 usb1: usb@211000 {
511 compatible = "fsl,p3041-usb2-dr",
512 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
513 reg = <0x211000 0x1000>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 interrupts = <45 0x2 0 0>;
517 dr_mode = "host";
518 phy_type = "utmi";
519 };
520
521 sata@220000 {
522 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
523 reg = <0x220000 0x1000>;
524 interrupts = <68 0x2 0 0>;
525 };
526
527 sata@221000 {
528 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
529 reg = <0x221000 0x1000>;
530 interrupts = <69 0x2 0 0>;
531 };
532
533 crypto: crypto@300000 {
534 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
535 #address-cells = <1>;
536 #size-cells = <1>;
537 reg = <0x300000 0x10000>;
538 ranges = <0 0x300000 0x10000>;
539 interrupts = <92 2 0 0>;
540
541 sec_jr0: jr@1000 {
542 compatible = "fsl,sec-v4.2-job-ring",
543 "fsl,sec-v4.0-job-ring";
544 reg = <0x1000 0x1000>;
545 interrupts = <88 2 0 0>;
546 };
547
548 sec_jr1: jr@2000 {
549 compatible = "fsl,sec-v4.2-job-ring",
550 "fsl,sec-v4.0-job-ring";
551 reg = <0x2000 0x1000>;
552 interrupts = <89 2 0 0>;
553 };
554
555 sec_jr2: jr@3000 {
556 compatible = "fsl,sec-v4.2-job-ring",
557 "fsl,sec-v4.0-job-ring";
558 reg = <0x3000 0x1000>;
559 interrupts = <90 2 0 0>;
560 };
561
562 sec_jr3: jr@4000 {
563 compatible = "fsl,sec-v4.2-job-ring",
564 "fsl,sec-v4.0-job-ring";
565 reg = <0x4000 0x1000>;
566 interrupts = <91 2 0 0>;
567 };
568
569 rtic@6000 {
570 compatible = "fsl,sec-v4.2-rtic",
571 "fsl,sec-v4.0-rtic";
572 #address-cells = <1>;
573 #size-cells = <1>;
574 reg = <0x6000 0x100>;
575 ranges = <0x0 0x6100 0xe00>;
576
577 rtic_a: rtic-a@0 {
578 compatible = "fsl,sec-v4.2-rtic-memory",
579 "fsl,sec-v4.0-rtic-memory";
580 reg = <0x00 0x20 0x100 0x80>;
581 };
582
583 rtic_b: rtic-b@20 {
584 compatible = "fsl,sec-v4.2-rtic-memory",
585 "fsl,sec-v4.0-rtic-memory";
586 reg = <0x20 0x20 0x200 0x80>;
587 };
588
589 rtic_c: rtic-c@40 {
590 compatible = "fsl,sec-v4.2-rtic-memory",
591 "fsl,sec-v4.0-rtic-memory";
592 reg = <0x40 0x20 0x300 0x80>;
593 };
594
595 rtic_d: rtic-d@60 {
596 compatible = "fsl,sec-v4.2-rtic-memory",
597 "fsl,sec-v4.0-rtic-memory";
598 reg = <0x60 0x20 0x500 0x80>;
599 };
600 };
601 };
602
603 sec_mon: sec_mon@314000 {
604 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
605 reg = <0x314000 0x1000>;
606 interrupts = <93 2 0 0>;
607 };
608 };
609
610/*
611 rapidio0: rapidio@ffe0c0000
612*/
613
614 localbus@ffe124000 {
615 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
616 interrupts = <25 2 0 0>;
617 #address-cells = <2>;
618 #size-cells = <1>;
619 };
620
621 pci0: pcie@ffe200000 {
622 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
623 device_type = "pci";
624 #size-cells = <2>;
625 #address-cells = <3>;
626 bus-range = <0x0 0xff>;
627 clock-frequency = <0x1fca055>;
628 fsl,msi = <&msi0>;
629 interrupts = <16 2 1 15>;
630
631 pcie@0 {
632 reg = <0 0 0 0 0>;
633 #interrupt-cells = <1>;
634 #size-cells = <2>;
635 #address-cells = <3>;
636 device_type = "pci";
637 interrupts = <16 2 1 15>;
638 interrupt-map-mask = <0xf800 0 0 7>;
639 interrupt-map = <
640 /* IDSEL 0x0 */
641 0000 0 0 1 &mpic 40 1 0 0
642 0000 0 0 2 &mpic 1 1 0 0
643 0000 0 0 3 &mpic 2 1 0 0
644 0000 0 0 4 &mpic 3 1 0 0
645 >;
646 };
647 };
648
649 pci1: pcie@ffe201000 {
650 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
651 device_type = "pci";
652 #size-cells = <2>;
653 #address-cells = <3>;
654 bus-range = <0 0xff>;
655 clock-frequency = <0x1fca055>;
656 fsl,msi = <&msi1>;
657 interrupts = <16 2 1 14>;
658 pcie@0 {
659 reg = <0 0 0 0 0>;
660 #interrupt-cells = <1>;
661 #size-cells = <2>;
662 #address-cells = <3>;
663 device_type = "pci";
664 interrupts = <16 2 1 14>;
665 interrupt-map-mask = <0xf800 0 0 7>;
666 interrupt-map = <
667 /* IDSEL 0x0 */
668 0000 0 0 1 &mpic 41 1 0 0
669 0000 0 0 2 &mpic 5 1 0 0
670 0000 0 0 3 &mpic 6 1 0 0
671 0000 0 0 4 &mpic 7 1 0 0
672 >;
673 };
674 };
675
676 pci2: pcie@ffe202000 {
677 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
678 device_type = "pci";
679 #size-cells = <2>;
680 #address-cells = <3>;
681 bus-range = <0x0 0xff>;
682 clock-frequency = <0x1fca055>;
683 fsl,msi = <&msi2>;
684 interrupts = <16 2 1 13>;
685 pcie@0 {
686 reg = <0 0 0 0 0>;
687 #interrupt-cells = <1>;
688 #size-cells = <2>;
689 #address-cells = <3>;
690 device_type = "pci";
691 interrupts = <16 2 1 13>;
692 interrupt-map-mask = <0xf800 0 0 7>;
693 interrupt-map = <
694 /* IDSEL 0x0 */
695 0000 0 0 1 &mpic 42 1 0 0
696 0000 0 0 2 &mpic 9 1 0 0
697 0000 0 0 3 &mpic 10 1 0 0
698 0000 0 0 4 &mpic 11 1 0 0
699 >;
700 };
701 };
702
703 pci3: pcie@ffe203000 {
704 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
705 device_type = "pci";
706 #size-cells = <2>;
707 #address-cells = <3>;
708 bus-range = <0x0 0xff>;
709 clock-frequency = <0x1fca055>;
710 fsl,msi = <&msi2>;
711 interrupts = <16 2 1 12>;
712 pcie@0 {
713 reg = <0 0 0 0 0>;
714 #interrupt-cells = <1>;
715 #size-cells = <2>;
716 #address-cells = <3>;
717 device_type = "pci";
718 interrupts = <16 2 1 12>;
719 interrupt-map-mask = <0xf800 0 0 7>;
720 interrupt-map = <
721 /* IDSEL 0x0 */
722 0000 0 0 1 &mpic 43 1 0 0
723 0000 0 0 2 &mpic 0 1 0 0
724 0000 0 0 3 &mpic 4 1 0 0
725 0000 0 0 4 &mpic 8 1 0 0
726 >;
727 };
728 };
729};
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
index 08b9193213e..529042e4b9a 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p3060si.dtsi" 35/include/ "fsl/p3060si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P3060QDS"; 38 model = "fsl,P3060QDS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -138,7 +140,7 @@
138 }; 140 };
139 }; 141 };
140 142
141 rapidio@ffe0c0000 { 143 rio: rapidio@ffe0c0000 {
142 reg = <0xf 0xfe0c0000 0 0x11000>; 144 reg = <0xf 0xfe0c0000 0 0x11000>;
143 145
144 port1 { 146 port1 {
@@ -149,7 +151,7 @@
149 }; 151 };
150 }; 152 };
151 153
152 localbus@ffe124000 { 154 lbc: localbus@ffe124000 {
153 reg = <0xf 0xfe124000 0 0x1000>; 155 reg = <0xf 0xfe124000 0 0x1000>;
154 ranges = <0 0 0xf 0xe8000000 0x08000000 156 ranges = <0 0 0xf 0xe8000000 0x08000000
155 2 0 0xf 0xffa00000 0x00040000 157 2 0 0xf 0xffa00000 0x00040000
@@ -210,6 +212,7 @@
210 reg = <0xf 0xfe200000 0 0x1000>; 212 reg = <0xf 0xfe200000 0 0x1000>;
211 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 213 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
212 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 214 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
215 fsl,msi = <&msi0>;
213 pcie@0 { 216 pcie@0 {
214 ranges = <0x02000000 0 0xe0000000 217 ranges = <0x02000000 0 0xe0000000
215 0x02000000 0 0xe0000000 218 0x02000000 0 0xe0000000
@@ -225,6 +228,7 @@
225 reg = <0xf 0xfe201000 0 0x1000>; 228 reg = <0xf 0xfe201000 0 0x1000>;
226 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 229 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
227 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 230 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
231 fsl,msi = <&msi1>;
228 pcie@0 { 232 pcie@0 {
229 ranges = <0x02000000 0 0xe0000000 233 ranges = <0x02000000 0 0xe0000000
230 0x02000000 0 0xe0000000 234 0x02000000 0 0xe0000000
@@ -236,3 +240,5 @@
236 }; 240 };
237 }; 241 };
238}; 242};
243
244/include/ "fsl/p3060si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3060si.dtsi b/arch/powerpc/boot/dts/p3060si.dtsi
deleted file mode 100644
index 68947e157bb..00000000000
--- a/arch/powerpc/boot/dts/p3060si.dtsi
+++ /dev/null
@@ -1,719 +0,0 @@
1/*
2 * P3060 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3060";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 msi0 = &msi0;
58 msi1 = &msi1;
59 msi2 = &msi2;
60
61 crypto = &crypto;
62 sec_jr0 = &sec_jr0;
63 sec_jr1 = &sec_jr1;
64 sec_jr2 = &sec_jr2;
65 sec_jr3 = &sec_jr3;
66 rtic_a = &rtic_a;
67 rtic_b = &rtic_b;
68 rtic_c = &rtic_c;
69 rtic_d = &rtic_d;
70 sec_mon = &sec_mon;
71 };
72
73 cpus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 cpu0: PowerPC,e500mc@0 {
78 device_type = "cpu";
79 reg = <0>;
80 next-level-cache = <&L2_0>;
81 L2_0: l2-cache {
82 next-level-cache = <&cpc>;
83 };
84 };
85 cpu1: PowerPC,e500mc@1 {
86 device_type = "cpu";
87 reg = <1>;
88 next-level-cache = <&L2_1>;
89 L2_1: l2-cache {
90 next-level-cache = <&cpc>;
91 };
92 };
93 cpu4: PowerPC,e500mc@4 {
94 device_type = "cpu";
95 reg = <4>;
96 next-level-cache = <&L2_4>;
97 L2_4: l2-cache {
98 next-level-cache = <&cpc>;
99 };
100 };
101 cpu5: PowerPC,e500mc@5 {
102 device_type = "cpu";
103 reg = <5>;
104 next-level-cache = <&L2_5>;
105 L2_5: l2-cache {
106 next-level-cache = <&cpc>;
107 };
108 };
109 cpu6: PowerPC,e500mc@6 {
110 device_type = "cpu";
111 reg = <6>;
112 next-level-cache = <&L2_6>;
113 L2_6: l2-cache {
114 next-level-cache = <&cpc>;
115 };
116 };
117 cpu7: PowerPC,e500mc@7 {
118 device_type = "cpu";
119 reg = <7>;
120 next-level-cache = <&L2_7>;
121 L2_7: l2-cache {
122 next-level-cache = <&cpc>;
123 };
124 };
125 };
126
127 dcsr: dcsr@f00000000 {
128 #address-cells = <1>;
129 #size-cells = <1>;
130 compatible = "fsl,dcsr", "simple-bus";
131
132 dcsr-epu@0 {
133 compatible = "fsl,dcsr-epu";
134 interrupts = <52 2 0 0
135 84 2 0 0
136 85 2 0 0>;
137 interrupt-parent = <&mpic>;
138 reg = <0x0 0x1000>;
139 };
140 dcsr-npc {
141 compatible = "fsl,dcsr-npc";
142 reg = <0x1000 0x1000 0x1000000 0x8000>;
143 };
144 dcsr-nxc@2000 {
145 compatible = "fsl,dcsr-nxc";
146 reg = <0x2000 0x1000>;
147 };
148 dcsr-corenet {
149 compatible = "fsl,dcsr-corenet";
150 reg = <0x8000 0x1000 0xB0000 0x1000>;
151 };
152 dcsr-dpaa@9000 {
153 compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
154 reg = <0x9000 0x1000>;
155 };
156 dcsr-ocn@11000 {
157 compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
158 reg = <0x11000 0x1000>;
159 };
160 dcsr-ddr@12000 {
161 compatible = "fsl,dcsr-ddr";
162 dev-handle = <&ddr>;
163 reg = <0x12000 0x1000>;
164 };
165 dcsr-nal@18000 {
166 compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
167 reg = <0x18000 0x1000>;
168 };
169 dcsr-rcpm@22000 {
170 compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
171 reg = <0x22000 0x1000>;
172 };
173 dcsr-cpu-sb-proxy@40000 {
174 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
175 cpu-handle = <&cpu0>;
176 reg = <0x40000 0x1000>;
177 };
178 dcsr-cpu-sb-proxy@41000 {
179 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
180 cpu-handle = <&cpu1>;
181 reg = <0x41000 0x1000>;
182 };
183 dcsr-cpu-sb-proxy@44000 {
184 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
185 cpu-handle = <&cpu4>;
186 reg = <0x44000 0x1000>;
187 };
188 dcsr-cpu-sb-proxy@45000 {
189 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
190 cpu-handle = <&cpu5>;
191 reg = <0x45000 0x1000>;
192 };
193 dcsr-cpu-sb-proxy@46000 {
194 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
195 cpu-handle = <&cpu6>;
196 reg = <0x46000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@47000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu7>;
201 reg = <0x47000 0x1000>;
202 };
203 };
204
205 soc: soc@ffe000000 {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 device_type = "soc";
209 compatible = "simple-bus";
210 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
211 reg = <0xf 0xfe000000 0 0x00001000>;
212
213 soc-sram-error {
214 compatible = "fsl,soc-sram-error";
215 interrupts = <16 2 1 29>;
216 };
217
218 corenet-law@0 {
219 compatible = "fsl,corenet-law";
220 reg = <0x0 0x1000>;
221 fsl,num-laws = <32>;
222 };
223
224 ddr: memory-controller@8000 {
225 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
226 reg = <0x8000 0x1000>;
227 interrupts = <16 2 1 23>;
228 };
229
230 cpc: l3-cache-controller@10000 {
231 compatible = "fsl,p3060-l3-cache-controller", "cache";
232 reg = <0x10000 0x1000
233 0x11000 0x1000>;
234 interrupts = <16 2 1 27>;
235 };
236
237 corenet-cf@18000 {
238 compatible = "fsl,corenet-cf";
239 reg = <0x18000 0x1000>;
240 interrupts = <16 2 1 31>;
241 fsl,ccf-num-csdids = <32>;
242 fsl,ccf-num-snoopids = <32>;
243 };
244
245 iommu@20000 {
246 compatible = "fsl,pamu-v1.0", "fsl,pamu";
247 reg = <0x20000 0x5000>;
248 interrupts = <
249 24 2 0 0
250 16 2 1 30>;
251 };
252
253 mpic: pic@40000 {
254 clock-frequency = <0>;
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <4>;
258 reg = <0x40000 0x40000>;
259 compatible = "fsl,mpic", "chrp,open-pic";
260 device_type = "open-pic";
261 };
262
263 msi0: msi@41600 {
264 compatible = "fsl,mpic-msi";
265 reg = <0x41600 0x200>;
266 msi-available-ranges = <0 0x100>;
267 interrupts = <
268 0xe0 0 0 0
269 0xe1 0 0 0
270 0xe2 0 0 0
271 0xe3 0 0 0
272 0xe4 0 0 0
273 0xe5 0 0 0
274 0xe6 0 0 0
275 0xe7 0 0 0>;
276 };
277
278 msi1: msi@41800 {
279 compatible = "fsl,mpic-msi";
280 reg = <0x41800 0x200>;
281 msi-available-ranges = <0 0x100>;
282 interrupts = <
283 0xe8 0 0 0
284 0xe9 0 0 0
285 0xea 0 0 0
286 0xeb 0 0 0
287 0xec 0 0 0
288 0xed 0 0 0
289 0xee 0 0 0
290 0xef 0 0 0>;
291 };
292
293 msi2: msi@41a00 {
294 compatible = "fsl,mpic-msi";
295 reg = <0x41a00 0x200>;
296 msi-available-ranges = <0 0x100>;
297 interrupts = <
298 0xf0 0 0 0
299 0xf1 0 0 0
300 0xf2 0 0 0
301 0xf3 0 0 0
302 0xf4 0 0 0
303 0xf5 0 0 0
304 0xf6 0 0 0
305 0xf7 0 0 0>;
306 };
307
308 rmu: rmu@d3000 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 compatible = "fsl,srio-rmu";
312 reg = <0xd3000 0x500>;
313 ranges = <0x0 0xd3000 0x500>;
314
315 message-unit@0 {
316 compatible = "fsl,srio-msg-unit";
317 reg = <0x0 0x100>;
318 interrupts = <
319 60 2 0 0 /* msg1_tx_irq */
320 61 2 0 0>;/* msg1_rx_irq */
321 };
322 message-unit@100 {
323 compatible = "fsl,srio-msg-unit";
324 reg = <0x100 0x100>;
325 interrupts = <
326 62 2 0 0 /* msg2_tx_irq */
327 63 2 0 0>;/* msg2_rx_irq */
328 };
329 doorbell-unit@400 {
330 compatible = "fsl,srio-dbell-unit";
331 reg = <0x400 0x80>;
332 interrupts = <
333 56 2 0 0 /* bell_outb_irq */
334 57 2 0 0>;/* bell_inb_irq */
335 };
336 port-write-unit@4e0 {
337 compatible = "fsl,srio-port-write-unit";
338 reg = <0x4e0 0x20>;
339 interrupts = <16 2 1 11>;
340 };
341 };
342
343 guts: global-utilities@e0000 {
344 compatible = "fsl,qoriq-device-config-1.0";
345 reg = <0xe0000 0xe00>;
346 fsl,has-rstcr;
347 #sleep-cells = <1>;
348 fsl,liodn-bits = <12>;
349 };
350
351 pins: global-utilities@e0e00 {
352 compatible = "fsl,qoriq-pin-control-1.0";
353 reg = <0xe0e00 0x200>;
354 #sleep-cells = <2>;
355 };
356
357 clockgen: global-utilities@e1000 {
358 compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
359 reg = <0xe1000 0x1000>;
360 clock-frequency = <0>;
361 };
362
363 rcpm: global-utilities@e2000 {
364 compatible = "fsl,qoriq-rcpm-1.0";
365 reg = <0xe2000 0x1000>;
366 #sleep-cells = <1>;
367 };
368
369 sfp: sfp@e8000 {
370 compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
371 reg = <0xe8000 0x1000>;
372 };
373
374 serdes: serdes@ea000 {
375 compatible = "fsl,p3060-serdes";
376 reg = <0xea000 0x1000>;
377 };
378
379 dma0: dma@100300 {
380 #address-cells = <1>;
381 #size-cells = <1>;
382 compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
383 reg = <0x100300 0x4>;
384 ranges = <0x0 0x100100 0x200>;
385 cell-index = <0>;
386 dma-channel@0 {
387 compatible = "fsl,p3060-dma-channel",
388 "fsl,eloplus-dma-channel";
389 reg = <0x0 0x80>;
390 cell-index = <0>;
391 interrupts = <28 2 0 0>;
392 };
393 dma-channel@80 {
394 compatible = "fsl,p3060-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x80 0x80>;
397 cell-index = <1>;
398 interrupts = <29 2 0 0>;
399 };
400 dma-channel@100 {
401 compatible = "fsl,p3060-dma-channel",
402 "fsl,eloplus-dma-channel";
403 reg = <0x100 0x80>;
404 cell-index = <2>;
405 interrupts = <30 2 0 0>;
406 };
407 dma-channel@180 {
408 compatible = "fsl,p3060-dma-channel",
409 "fsl,eloplus-dma-channel";
410 reg = <0x180 0x80>;
411 cell-index = <3>;
412 interrupts = <31 2 0 0>;
413 };
414 };
415
416 dma1: dma@101300 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
420 reg = <0x101300 0x4>;
421 ranges = <0x0 0x101100 0x200>;
422 cell-index = <1>;
423 dma-channel@0 {
424 compatible = "fsl,p3060-dma-channel",
425 "fsl,eloplus-dma-channel";
426 reg = <0x0 0x80>;
427 cell-index = <0>;
428 interrupts = <32 2 0 0>;
429 };
430 dma-channel@80 {
431 compatible = "fsl,p3060-dma-channel",
432 "fsl,eloplus-dma-channel";
433 reg = <0x80 0x80>;
434 cell-index = <1>;
435 interrupts = <33 2 0 0>;
436 };
437 dma-channel@100 {
438 compatible = "fsl,p3060-dma-channel",
439 "fsl,eloplus-dma-channel";
440 reg = <0x100 0x80>;
441 cell-index = <2>;
442 interrupts = <34 2 0 0>;
443 };
444 dma-channel@180 {
445 compatible = "fsl,p3060-dma-channel",
446 "fsl,eloplus-dma-channel";
447 reg = <0x180 0x80>;
448 cell-index = <3>;
449 interrupts = <35 2 0 0>;
450 };
451 };
452
453 spi@110000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "fsl,p3060-espi", "fsl,mpc8536-espi";
457 reg = <0x110000 0x1000>;
458 interrupts = <53 0x2 0 0>;
459 fsl,espi-num-chipselects = <4>;
460 };
461
462 i2c@118000 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 cell-index = <0>;
466 compatible = "fsl-i2c";
467 reg = <0x118000 0x100>;
468 interrupts = <38 2 0 0>;
469 dfsrr;
470 };
471
472 i2c@118100 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 cell-index = <1>;
476 compatible = "fsl-i2c";
477 reg = <0x118100 0x100>;
478 interrupts = <38 2 0 0>;
479 dfsrr;
480 };
481
482 i2c@119000 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 cell-index = <2>;
486 compatible = "fsl-i2c";
487 reg = <0x119000 0x100>;
488 interrupts = <39 2 0 0>;
489 dfsrr;
490 };
491
492 i2c@119100 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 cell-index = <3>;
496 compatible = "fsl-i2c";
497 reg = <0x119100 0x100>;
498 interrupts = <39 2 0 0>;
499 dfsrr;
500 };
501
502 serial0: serial@11c500 {
503 cell-index = <0>;
504 device_type = "serial";
505 compatible = "ns16550";
506 reg = <0x11c500 0x100>;
507 clock-frequency = <0>;
508 interrupts = <36 2 0 0>;
509 };
510
511 serial1: serial@11c600 {
512 cell-index = <1>;
513 device_type = "serial";
514 compatible = "ns16550";
515 reg = <0x11c600 0x100>;
516 clock-frequency = <0>;
517 interrupts = <36 2 0 0>;
518 };
519
520 serial2: serial@11d500 {
521 cell-index = <2>;
522 device_type = "serial";
523 compatible = "ns16550";
524 reg = <0x11d500 0x100>;
525 clock-frequency = <0>;
526 interrupts = <37 2 0 0>;
527 };
528
529 serial3: serial@11d600 {
530 cell-index = <3>;
531 device_type = "serial";
532 compatible = "ns16550";
533 reg = <0x11d600 0x100>;
534 clock-frequency = <0>;
535 interrupts = <37 2 0 0>;
536 };
537
538 gpio0: gpio@130000 {
539 compatible = "fsl,p3060-gpio", "fsl,qoriq-gpio";
540 reg = <0x130000 0x1000>;
541 interrupts = <55 2 0 0>;
542 #gpio-cells = <2>;
543 gpio-controller;
544 };
545
546 usb0: usb@210000 {
547 compatible = "fsl,p3060-usb2-mph",
548 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
549 reg = <0x210000 0x1000>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 interrupts = <44 0x2 0 0>;
553 };
554
555 usb1: usb@211000 {
556 compatible = "fsl,p3060-usb2-dr",
557 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
558 reg = <0x211000 0x1000>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 interrupts = <45 0x2 0 0>;
562 };
563
564 crypto: crypto@300000 {
565 compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 reg = <0x300000 0x10000>;
569 ranges = <0 0x300000 0x10000>;
570 interrupt-parent = <&mpic>;
571 interrupts = <92 2 0 0>;
572
573 sec_jr0: jr@1000 {
574 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
575 reg = <0x1000 0x1000>;
576 interrupt-parent = <&mpic>;
577 interrupts = <88 2 0 0>;
578 };
579
580 sec_jr1: jr@2000 {
581 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
582 reg = <0x2000 0x1000>;
583 interrupt-parent = <&mpic>;
584 interrupts = <89 2 0 0>;
585 };
586
587 sec_jr2: jr@3000 {
588 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
589 reg = <0x3000 0x1000>;
590 interrupt-parent = <&mpic>;
591 interrupts = <90 2 0 0>;
592 };
593
594 sec_jr3: jr@4000 {
595 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
596 reg = <0x4000 0x1000>;
597 interrupt-parent = <&mpic>;
598 interrupts = <91 2 0 0>;
599 };
600
601 rtic@6000 {
602 compatible = "fsl,sec-v4.1-rtic", "fsl,sec-v4.0-rtic";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 reg = <0x6000 0x100>;
606 ranges = <0x0 0x6100 0xe00>;
607
608 rtic_a: rtic-a@0 {
609 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
610 reg = <0x00 0x20 0x100 0x80>;
611 };
612
613 rtic_b: rtic-b@20 {
614 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
615 reg = <0x20 0x20 0x200 0x80>;
616 };
617
618 rtic_c: rtic-c@40 {
619 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
620 reg = <0x40 0x20 0x300 0x80>;
621 };
622
623 rtic_d: rtic-d@60 {
624 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
625 reg = <0x60 0x20 0x500 0x80>;
626 };
627 };
628 };
629
630 sec_mon: sec_mon@314000 {
631 compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
632 reg = <0x314000 0x1000>;
633 interrupt-parent = <&mpic>;
634 interrupts = <93 2 0 0>;
635 };
636 };
637
638 rapidio@ffe0c0000 {
639 compatible = "fsl,srio";
640 interrupts = <16 2 1 11>;
641 #address-cells = <2>;
642 #size-cells = <2>;
643 fsl,srio-rmu-handle = <&rmu>;
644 ranges;
645
646 port1 {
647 #address-cells = <2>;
648 #size-cells = <2>;
649 cell-index = <1>;
650 };
651
652 port2 {
653 #address-cells = <2>;
654 #size-cells = <2>;
655 cell-index = <2>;
656 };
657 };
658
659 localbus@ffe124000 {
660 compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
661 interrupts = <25 2 0 0>;
662 #address-cells = <2>;
663 #size-cells = <1>;
664 };
665
666 pci0: pcie@ffe200000 {
667 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
668 device_type = "pci";
669 #size-cells = <2>;
670 #address-cells = <3>;
671 bus-range = <0x0 0xff>;
672 clock-frequency = <33333333>;
673 fsl,msi = <&msi0>;
674 interrupts = <16 2 1 15>;
675 pcie@0 {
676 reg = <0 0 0 0 0>;
677 #interrupt-cells = <1>;
678 #size-cells = <2>;
679 #address-cells = <3>;
680 device_type = "pci";
681 interrupts = <16 2 1 15>;
682 interrupt-map-mask = <0xf800 0 0 7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0000 0 0 1 &mpic 40 1 0 0
686 0000 0 0 2 &mpic 1 1 0 0
687 0000 0 0 3 &mpic 2 1 0 0
688 0000 0 0 4 &mpic 3 1 0 0
689 >;
690 };
691 };
692
693 pci1: pcie@ffe201000 {
694 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
695 device_type = "pci";
696 #size-cells = <2>;
697 #address-cells = <3>;
698 bus-range = <0 0xff>;
699 clock-frequency = <33333333>;
700 fsl,msi = <&msi1>;
701 interrupts = <16 2 1 14>;
702 pcie@0 {
703 reg = <0 0 0 0 0>;
704 #interrupt-cells = <1>;
705 #size-cells = <2>;
706 #address-cells = <3>;
707 device_type = "pci";
708 interrupts = <16 2 1 14>;
709 interrupt-map-mask = <0xf800 0 0 7>;
710 interrupt-map = <
711 /* IDSEL 0x0 */
712 0000 0 0 1 &mpic 41 1 0 0
713 0000 0 0 2 &mpic 5 1 0 0
714 0000 0 0 3 &mpic 6 1 0 0
715 0000 0 0 4 &mpic 7 1 0 0
716 >;
717 };
718 };
719};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index c7916dc2801..6d60e54e50a 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p4080si.dtsi" 35/include/ "fsl/p4080si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P4080DS"; 38 model = "fsl,P4080DS";
@@ -50,6 +50,9 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
55
53 spi@110000 { 56 spi@110000 {
54 flash@0 { 57 flash@0 {
55 #address-cells = <1>; 58 #address-cells = <1>;
@@ -105,12 +108,18 @@
105 }; 108 };
106 }; 109 };
107 110
108 rapidio0: rapidio@ffe0c0000 { 111 rio: rapidio@ffe0c0000 {
109 reg = <0xf 0xfe0c0000 0 0x20000>; 112 reg = <0xf 0xfe0c0000 0 0x11000>;
110 ranges = <0 0 0xc 0x20000000 0 0x01000000>; 113
114 port1 {
115 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
116 };
117 port2 {
118 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
119 };
111 }; 120 };
112 121
113 localbus@ffe124000 { 122 lbc: localbus@ffe124000 {
114 reg = <0xf 0xfe124000 0 0x1000>; 123 reg = <0xf 0xfe124000 0 0x1000>;
115 ranges = <0 0 0xf 0xe8000000 0x08000000 124 ranges = <0 0 0xf 0xe8000000 0x08000000
116 3 0 0xf 0xffdf0000 0x00008000>; 125 3 0 0xf 0xffdf0000 0x00008000>;
@@ -132,6 +141,7 @@
132 reg = <0xf 0xfe200000 0 0x1000>; 141 reg = <0xf 0xfe200000 0 0x1000>;
133 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 142 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
134 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 143 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
144 fsl,msi = <&msi0>;
135 pcie@0 { 145 pcie@0 {
136 ranges = <0x02000000 0 0xe0000000 146 ranges = <0x02000000 0 0xe0000000
137 0x02000000 0 0xe0000000 147 0x02000000 0 0xe0000000
@@ -147,6 +157,7 @@
147 reg = <0xf 0xfe201000 0 0x1000>; 157 reg = <0xf 0xfe201000 0 0x1000>;
148 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 158 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
149 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 159 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
160 fsl,msi = <&msi1>;
150 pcie@0 { 161 pcie@0 {
151 ranges = <0x02000000 0 0xe0000000 162 ranges = <0x02000000 0 0xe0000000
152 0x02000000 0 0xe0000000 163 0x02000000 0 0xe0000000
@@ -162,6 +173,7 @@
162 reg = <0xf 0xfe202000 0 0x1000>; 173 reg = <0xf 0xfe202000 0 0x1000>;
163 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
164 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
176 fsl,msi = <&msi2>;
165 pcie@0 { 177 pcie@0 {
166 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
167 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -174,3 +186,5 @@
174 }; 186 };
175 187
176}; 188};
189
190/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
deleted file mode 100644
index f20c01ab247..00000000000
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ /dev/null
@@ -1,755 +0,0 @@
1/*
2 * P4080 Silicon Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P4080";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74 rio0 = &rapidio0;
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu0: PowerPC,e500mc@0 {
82 device_type = "cpu";
83 reg = <0>;
84 next-level-cache = <&L2_0>;
85 L2_0: l2-cache {
86 next-level-cache = <&cpc>;
87 };
88 };
89 cpu1: PowerPC,e500mc@1 {
90 device_type = "cpu";
91 reg = <1>;
92 next-level-cache = <&L2_1>;
93 L2_1: l2-cache {
94 next-level-cache = <&cpc>;
95 };
96 };
97 cpu2: PowerPC,e500mc@2 {
98 device_type = "cpu";
99 reg = <2>;
100 next-level-cache = <&L2_2>;
101 L2_2: l2-cache {
102 next-level-cache = <&cpc>;
103 };
104 };
105 cpu3: PowerPC,e500mc@3 {
106 device_type = "cpu";
107 reg = <3>;
108 next-level-cache = <&L2_3>;
109 L2_3: l2-cache {
110 next-level-cache = <&cpc>;
111 };
112 };
113 cpu4: PowerPC,e500mc@4 {
114 device_type = "cpu";
115 reg = <4>;
116 next-level-cache = <&L2_4>;
117 L2_4: l2-cache {
118 next-level-cache = <&cpc>;
119 };
120 };
121 cpu5: PowerPC,e500mc@5 {
122 device_type = "cpu";
123 reg = <5>;
124 next-level-cache = <&L2_5>;
125 L2_5: l2-cache {
126 next-level-cache = <&cpc>;
127 };
128 };
129 cpu6: PowerPC,e500mc@6 {
130 device_type = "cpu";
131 reg = <6>;
132 next-level-cache = <&L2_6>;
133 L2_6: l2-cache {
134 next-level-cache = <&cpc>;
135 };
136 };
137 cpu7: PowerPC,e500mc@7 {
138 device_type = "cpu";
139 reg = <7>;
140 next-level-cache = <&L2_7>;
141 L2_7: l2-cache {
142 next-level-cache = <&cpc>;
143 };
144 };
145 };
146
147 dcsr: dcsr@f00000000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,dcsr", "simple-bus";
151
152 dcsr-epu@0 {
153 compatible = "fsl,dcsr-epu";
154 interrupts = <52 2 0 0
155 84 2 0 0
156 85 2 0 0>;
157 interrupt-parent = <&mpic>;
158 reg = <0x0 0x1000>;
159 };
160 dcsr-npc {
161 compatible = "fsl,dcsr-npc";
162 reg = <0x1000 0x1000 0x1000000 0x8000>;
163 };
164 dcsr-nxc@2000 {
165 compatible = "fsl,dcsr-nxc";
166 reg = <0x2000 0x1000>;
167 };
168 dcsr-corenet {
169 compatible = "fsl,dcsr-corenet";
170 reg = <0x8000 0x1000 0xB0000 0x1000>;
171 };
172 dcsr-dpaa@9000 {
173 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
174 reg = <0x9000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-ddr@13000 {
186 compatible = "fsl,dcsr-ddr";
187 dev-handle = <&ddr2>;
188 reg = <0x13000 0x1000>;
189 };
190 dcsr-nal@18000 {
191 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
192 reg = <0x18000 0x1000>;
193 };
194 dcsr-rcpm@22000 {
195 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
196 reg = <0x22000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@40000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu0>;
201 reg = <0x40000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@41000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu1>;
206 reg = <0x41000 0x1000>;
207 };
208 dcsr-cpu-sb-proxy@42000 {
209 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
210 cpu-handle = <&cpu2>;
211 reg = <0x42000 0x1000>;
212 };
213 dcsr-cpu-sb-proxy@43000 {
214 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
215 cpu-handle = <&cpu3>;
216 reg = <0x43000 0x1000>;
217 };
218 dcsr-cpu-sb-proxy@44000 {
219 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
220 cpu-handle = <&cpu4>;
221 reg = <0x44000 0x1000>;
222 };
223 dcsr-cpu-sb-proxy@45000 {
224 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
225 cpu-handle = <&cpu5>;
226 reg = <0x45000 0x1000>;
227 };
228 dcsr-cpu-sb-proxy@46000 {
229 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
230 cpu-handle = <&cpu6>;
231 reg = <0x46000 0x1000>;
232 };
233 dcsr-cpu-sb-proxy@47000 {
234 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
235 cpu-handle = <&cpu7>;
236 reg = <0x47000 0x1000>;
237 };
238 };
239
240 soc: soc@ffe000000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 device_type = "soc";
244 compatible = "simple-bus";
245 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
246 reg = <0xf 0xfe000000 0 0x00001000>;
247
248 soc-sram-error {
249 compatible = "fsl,soc-sram-error";
250 interrupts = <16 2 1 29>;
251 };
252
253 corenet-law@0 {
254 compatible = "fsl,corenet-law";
255 reg = <0x0 0x1000>;
256 fsl,num-laws = <32>;
257 };
258
259 ddr1: memory-controller@8000 {
260 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
261 reg = <0x8000 0x1000>;
262 interrupts = <16 2 1 23>;
263 };
264
265 ddr2: memory-controller@9000 {
266 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
267 reg = <0x9000 0x1000>;
268 interrupts = <16 2 1 22>;
269 };
270
271 cpc: l3-cache-controller@10000 {
272 compatible = "fsl,p4080-l3-cache-controller", "cache";
273 reg = <0x10000 0x1000
274 0x11000 0x1000>;
275 interrupts = <16 2 1 27
276 16 2 1 26>;
277 };
278
279 corenet-cf@18000 {
280 compatible = "fsl,corenet-cf";
281 reg = <0x18000 0x1000>;
282 interrupts = <16 2 1 31>;
283 fsl,ccf-num-csdids = <32>;
284 fsl,ccf-num-snoopids = <32>;
285 };
286
287 iommu@20000 {
288 compatible = "fsl,pamu-v1.0", "fsl,pamu";
289 reg = <0x20000 0x5000>;
290 interrupts = <
291 24 2 0 0
292 16 2 1 30>;
293 };
294
295 mpic: pic@40000 {
296 clock-frequency = <0>;
297 interrupt-controller;
298 #address-cells = <0>;
299 #interrupt-cells = <4>;
300 reg = <0x40000 0x40000>;
301 compatible = "fsl,mpic", "chrp,open-pic";
302 device_type = "open-pic";
303 };
304
305 msi0: msi@41600 {
306 compatible = "fsl,mpic-msi";
307 reg = <0x41600 0x200>;
308 msi-available-ranges = <0 0x100>;
309 interrupts = <
310 0xe0 0 0 0
311 0xe1 0 0 0
312 0xe2 0 0 0
313 0xe3 0 0 0
314 0xe4 0 0 0
315 0xe5 0 0 0
316 0xe6 0 0 0
317 0xe7 0 0 0>;
318 };
319
320 msi1: msi@41800 {
321 compatible = "fsl,mpic-msi";
322 reg = <0x41800 0x200>;
323 msi-available-ranges = <0 0x100>;
324 interrupts = <
325 0xe8 0 0 0
326 0xe9 0 0 0
327 0xea 0 0 0
328 0xeb 0 0 0
329 0xec 0 0 0
330 0xed 0 0 0
331 0xee 0 0 0
332 0xef 0 0 0>;
333 };
334
335 msi2: msi@41a00 {
336 compatible = "fsl,mpic-msi";
337 reg = <0x41a00 0x200>;
338 msi-available-ranges = <0 0x100>;
339 interrupts = <
340 0xf0 0 0 0
341 0xf1 0 0 0
342 0xf2 0 0 0
343 0xf3 0 0 0
344 0xf4 0 0 0
345 0xf5 0 0 0
346 0xf6 0 0 0
347 0xf7 0 0 0>;
348 };
349
350 guts: global-utilities@e0000 {
351 compatible = "fsl,qoriq-device-config-1.0";
352 reg = <0xe0000 0xe00>;
353 fsl,has-rstcr;
354 #sleep-cells = <1>;
355 fsl,liodn-bits = <12>;
356 };
357
358 pins: global-utilities@e0e00 {
359 compatible = "fsl,qoriq-pin-control-1.0";
360 reg = <0xe0e00 0x200>;
361 #sleep-cells = <2>;
362 };
363
364 clockgen: global-utilities@e1000 {
365 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
366 reg = <0xe1000 0x1000>;
367 clock-frequency = <0>;
368 };
369
370 rcpm: global-utilities@e2000 {
371 compatible = "fsl,qoriq-rcpm-1.0";
372 reg = <0xe2000 0x1000>;
373 #sleep-cells = <1>;
374 };
375
376 sfp: sfp@e8000 {
377 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
378 reg = <0xe8000 0x1000>;
379 };
380
381 serdes: serdes@ea000 {
382 compatible = "fsl,p4080-serdes";
383 reg = <0xea000 0x1000>;
384 };
385
386 dma0: dma@100300 {
387 #address-cells = <1>;
388 #size-cells = <1>;
389 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
390 reg = <0x100300 0x4>;
391 ranges = <0x0 0x100100 0x200>;
392 cell-index = <0>;
393 dma-channel@0 {
394 compatible = "fsl,p4080-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x0 0x80>;
397 cell-index = <0>;
398 interrupts = <28 2 0 0>;
399 };
400 dma-channel@80 {
401 compatible = "fsl,p4080-dma-channel",
402 "fsl,eloplus-dma-channel";
403 reg = <0x80 0x80>;
404 cell-index = <1>;
405 interrupts = <29 2 0 0>;
406 };
407 dma-channel@100 {
408 compatible = "fsl,p4080-dma-channel",
409 "fsl,eloplus-dma-channel";
410 reg = <0x100 0x80>;
411 cell-index = <2>;
412 interrupts = <30 2 0 0>;
413 };
414 dma-channel@180 {
415 compatible = "fsl,p4080-dma-channel",
416 "fsl,eloplus-dma-channel";
417 reg = <0x180 0x80>;
418 cell-index = <3>;
419 interrupts = <31 2 0 0>;
420 };
421 };
422
423 dma1: dma@101300 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
427 reg = <0x101300 0x4>;
428 ranges = <0x0 0x101100 0x200>;
429 cell-index = <1>;
430 dma-channel@0 {
431 compatible = "fsl,p4080-dma-channel",
432 "fsl,eloplus-dma-channel";
433 reg = <0x0 0x80>;
434 cell-index = <0>;
435 interrupts = <32 2 0 0>;
436 };
437 dma-channel@80 {
438 compatible = "fsl,p4080-dma-channel",
439 "fsl,eloplus-dma-channel";
440 reg = <0x80 0x80>;
441 cell-index = <1>;
442 interrupts = <33 2 0 0>;
443 };
444 dma-channel@100 {
445 compatible = "fsl,p4080-dma-channel",
446 "fsl,eloplus-dma-channel";
447 reg = <0x100 0x80>;
448 cell-index = <2>;
449 interrupts = <34 2 0 0>;
450 };
451 dma-channel@180 {
452 compatible = "fsl,p4080-dma-channel",
453 "fsl,eloplus-dma-channel";
454 reg = <0x180 0x80>;
455 cell-index = <3>;
456 interrupts = <35 2 0 0>;
457 };
458 };
459
460 spi@110000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
464 reg = <0x110000 0x1000>;
465 interrupts = <53 0x2 0 0>;
466 fsl,espi-num-chipselects = <4>;
467 };
468
469 sdhc: sdhc@114000 {
470 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
471 reg = <0x114000 0x1000>;
472 interrupts = <48 2 0 0>;
473 voltage-ranges = <3300 3300>;
474 sdhci,auto-cmd12;
475 clock-frequency = <0>;
476 };
477
478 i2c@118000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 cell-index = <0>;
482 compatible = "fsl-i2c";
483 reg = <0x118000 0x100>;
484 interrupts = <38 2 0 0>;
485 dfsrr;
486 };
487
488 i2c@118100 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 cell-index = <1>;
492 compatible = "fsl-i2c";
493 reg = <0x118100 0x100>;
494 interrupts = <38 2 0 0>;
495 dfsrr;
496 };
497
498 i2c@119000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 cell-index = <2>;
502 compatible = "fsl-i2c";
503 reg = <0x119000 0x100>;
504 interrupts = <39 2 0 0>;
505 dfsrr;
506 };
507
508 i2c@119100 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 cell-index = <3>;
512 compatible = "fsl-i2c";
513 reg = <0x119100 0x100>;
514 interrupts = <39 2 0 0>;
515 dfsrr;
516 };
517
518 serial0: serial@11c500 {
519 cell-index = <0>;
520 device_type = "serial";
521 compatible = "ns16550";
522 reg = <0x11c500 0x100>;
523 clock-frequency = <0>;
524 interrupts = <36 2 0 0>;
525 };
526
527 serial1: serial@11c600 {
528 cell-index = <1>;
529 device_type = "serial";
530 compatible = "ns16550";
531 reg = <0x11c600 0x100>;
532 clock-frequency = <0>;
533 interrupts = <36 2 0 0>;
534 };
535
536 serial2: serial@11d500 {
537 cell-index = <2>;
538 device_type = "serial";
539 compatible = "ns16550";
540 reg = <0x11d500 0x100>;
541 clock-frequency = <0>;
542 interrupts = <37 2 0 0>;
543 };
544
545 serial3: serial@11d600 {
546 cell-index = <3>;
547 device_type = "serial";
548 compatible = "ns16550";
549 reg = <0x11d600 0x100>;
550 clock-frequency = <0>;
551 interrupts = <37 2 0 0>;
552 };
553
554 gpio0: gpio@130000 {
555 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
556 reg = <0x130000 0x1000>;
557 interrupts = <55 2 0 0>;
558 #gpio-cells = <2>;
559 gpio-controller;
560 };
561
562 usb0: usb@210000 {
563 compatible = "fsl,p4080-usb2-mph",
564 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
565 reg = <0x210000 0x1000>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 interrupts = <44 0x2 0 0>;
569 };
570
571 usb1: usb@211000 {
572 compatible = "fsl,p4080-usb2-dr",
573 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
574 reg = <0x211000 0x1000>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 interrupts = <45 0x2 0 0>;
578 };
579
580 crypto: crypto@300000 {
581 compatible = "fsl,sec-v4.0";
582 #address-cells = <1>;
583 #size-cells = <1>;
584 reg = <0x300000 0x10000>;
585 ranges = <0 0x300000 0x10000>;
586 interrupt-parent = <&mpic>;
587 interrupts = <92 2 0 0>;
588
589 sec_jr0: jr@1000 {
590 compatible = "fsl,sec-v4.0-job-ring";
591 reg = <0x1000 0x1000>;
592 interrupt-parent = <&mpic>;
593 interrupts = <88 2 0 0>;
594 };
595
596 sec_jr1: jr@2000 {
597 compatible = "fsl,sec-v4.0-job-ring";
598 reg = <0x2000 0x1000>;
599 interrupt-parent = <&mpic>;
600 interrupts = <89 2 0 0>;
601 };
602
603 sec_jr2: jr@3000 {
604 compatible = "fsl,sec-v4.0-job-ring";
605 reg = <0x3000 0x1000>;
606 interrupt-parent = <&mpic>;
607 interrupts = <90 2 0 0>;
608 };
609
610 sec_jr3: jr@4000 {
611 compatible = "fsl,sec-v4.0-job-ring";
612 reg = <0x4000 0x1000>;
613 interrupt-parent = <&mpic>;
614 interrupts = <91 2 0 0>;
615 };
616
617 rtic@6000 {
618 compatible = "fsl,sec-v4.0-rtic";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 reg = <0x6000 0x100>;
622 ranges = <0x0 0x6100 0xe00>;
623
624 rtic_a: rtic-a@0 {
625 compatible = "fsl,sec-v4.0-rtic-memory";
626 reg = <0x00 0x20 0x100 0x80>;
627 };
628
629 rtic_b: rtic-b@20 {
630 compatible = "fsl,sec-v4.0-rtic-memory";
631 reg = <0x20 0x20 0x200 0x80>;
632 };
633
634 rtic_c: rtic-c@40 {
635 compatible = "fsl,sec-v4.0-rtic-memory";
636 reg = <0x40 0x20 0x300 0x80>;
637 };
638
639 rtic_d: rtic-d@60 {
640 compatible = "fsl,sec-v4.0-rtic-memory";
641 reg = <0x60 0x20 0x500 0x80>;
642 };
643 };
644 };
645
646 sec_mon: sec_mon@314000 {
647 compatible = "fsl,sec-v4.0-mon";
648 reg = <0x314000 0x1000>;
649 interrupt-parent = <&mpic>;
650 interrupts = <93 2 0 0>;
651 };
652 };
653
654 rapidio0: rapidio@ffe0c0000 {
655 #address-cells = <2>;
656 #size-cells = <2>;
657 compatible = "fsl,rapidio-delta";
658 interrupts = <
659 16 2 1 11 /* err_irq */
660 56 2 0 0 /* bell_outb_irq */
661 57 2 0 0 /* bell_inb_irq */
662 60 2 0 0 /* msg1_tx_irq */
663 61 2 0 0 /* msg1_rx_irq */
664 62 2 0 0 /* msg2_tx_irq */
665 63 2 0 0>; /* msg2_rx_irq */
666 };
667
668 localbus@ffe124000 {
669 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
670 interrupts = <25 2 0 0>;
671 #address-cells = <2>;
672 #size-cells = <1>;
673 };
674
675 pci0: pcie@ffe200000 {
676 compatible = "fsl,p4080-pcie";
677 device_type = "pci";
678 #size-cells = <2>;
679 #address-cells = <3>;
680 bus-range = <0x0 0xff>;
681 clock-frequency = <0x1fca055>;
682 fsl,msi = <&msi0>;
683 interrupts = <16 2 1 15>;
684 pcie@0 {
685 reg = <0 0 0 0 0>;
686 #interrupt-cells = <1>;
687 #size-cells = <2>;
688 #address-cells = <3>;
689 device_type = "pci";
690 interrupts = <16 2 1 15>;
691 interrupt-map-mask = <0xf800 0 0 7>;
692 interrupt-map = <
693 /* IDSEL 0x0 */
694 0000 0 0 1 &mpic 40 1 0 0
695 0000 0 0 2 &mpic 1 1 0 0
696 0000 0 0 3 &mpic 2 1 0 0
697 0000 0 0 4 &mpic 3 1 0 0
698 >;
699 };
700 };
701
702 pci1: pcie@ffe201000 {
703 compatible = "fsl,p4080-pcie";
704 device_type = "pci";
705 #size-cells = <2>;
706 #address-cells = <3>;
707 bus-range = <0 0xff>;
708 clock-frequency = <0x1fca055>;
709 fsl,msi = <&msi1>;
710 interrupts = <16 2 1 14>;
711 pcie@0 {
712 reg = <0 0 0 0 0>;
713 #interrupt-cells = <1>;
714 #size-cells = <2>;
715 #address-cells = <3>;
716 device_type = "pci";
717 interrupts = <16 2 1 14>;
718 interrupt-map-mask = <0xf800 0 0 7>;
719 interrupt-map = <
720 /* IDSEL 0x0 */
721 0000 0 0 1 &mpic 41 1 0 0
722 0000 0 0 2 &mpic 5 1 0 0
723 0000 0 0 3 &mpic 6 1 0 0
724 0000 0 0 4 &mpic 7 1 0 0
725 >;
726 };
727 };
728
729 pci2: pcie@ffe202000 {
730 compatible = "fsl,p4080-pcie";
731 device_type = "pci";
732 #size-cells = <2>;
733 #address-cells = <3>;
734 bus-range = <0x0 0xff>;
735 clock-frequency = <0x1fca055>;
736 fsl,msi = <&msi2>;
737 interrupts = <16 2 1 13>;
738 pcie@0 {
739 reg = <0 0 0 0 0>;
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 device_type = "pci";
744 interrupts = <16 2 1 13>;
745 interrupt-map-mask = <0xf800 0 0 7>;
746 interrupt-map = <
747 /* IDSEL 0x0 */
748 0000 0 0 1 &mpic 42 1 0 0
749 0000 0 0 2 &mpic 9 1 0 0
750 0000 0 0 3 &mpic 10 1 0 0
751 0000 0 0 4 &mpic 11 1 0 0
752 >;
753 };
754 };
755};
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index e6d40999ccd..1c250684c90 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p5020si.dtsi" 35/include/ "fsl/p5020si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P5020DS"; 38 model = "fsl,P5020DS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -99,7 +101,18 @@
99 }; 101 };
100 }; 102 };
101 103
102 localbus@ffe124000 { 104 rio: rapidio@ffe0c0000 {
105 reg = <0xf 0xfe0c0000 0 0x11000>;
106
107 port1 {
108 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
109 };
110 port2 {
111 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
112 };
113 };
114
115 lbc: localbus@ffe124000 {
103 reg = <0xf 0xfe124000 0 0x1000>; 116 reg = <0xf 0xfe124000 0 0x1000>;
104 ranges = <0 0 0xf 0xe8000000 0x08000000 117 ranges = <0 0 0xf 0xe8000000 0x08000000
105 2 0 0xf 0xffa00000 0x00040000 118 2 0 0xf 0xffa00000 0x00040000
@@ -160,7 +173,7 @@
160 reg = <0xf 0xfe200000 0 0x1000>; 173 reg = <0xf 0xfe200000 0 0x1000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
163 176 fsl,msi = <&msi0>;
164 pcie@0 { 177 pcie@0 {
165 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
166 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -176,6 +189,7 @@
176 reg = <0xf 0xfe201000 0 0x1000>; 189 reg = <0xf 0xfe201000 0 0x1000>;
177 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 190 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
178 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 191 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
192 fsl,msi = <&msi1>;
179 pcie@0 { 193 pcie@0 {
180 ranges = <0x02000000 0 0xe0000000 194 ranges = <0x02000000 0 0xe0000000
181 0x02000000 0 0xe0000000 195 0x02000000 0 0xe0000000
@@ -191,6 +205,7 @@
191 reg = <0xf 0xfe202000 0 0x1000>; 205 reg = <0xf 0xfe202000 0 0x1000>;
192 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 206 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
193 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 207 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
208 fsl,msi = <&msi2>;
194 pcie@0 { 209 pcie@0 {
195 ranges = <0x02000000 0 0xe0000000 210 ranges = <0x02000000 0 0xe0000000
196 0x02000000 0 0xe0000000 211 0x02000000 0 0xe0000000
@@ -206,6 +221,7 @@
206 reg = <0xf 0xfe203000 0 0x1000>; 221 reg = <0xf 0xfe203000 0 0x1000>;
207 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 222 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
208 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 223 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
224 fsl,msi = <&msi2>;
209 pcie@0 { 225 pcie@0 {
210 ranges = <0x02000000 0 0xe0000000 226 ranges = <0x02000000 0 0xe0000000
211 0x02000000 0 0xe0000000 227 0x02000000 0 0xe0000000
@@ -217,3 +233,5 @@
217 }; 233 };
218 }; 234 };
219}; 235};
236
237/include/ "fsl/p5020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
deleted file mode 100644
index e7948ad71fa..00000000000
--- a/arch/powerpc/boot/dts/p5020si.dtsi
+++ /dev/null
@@ -1,716 +0,0 @@
1/*
2 * P5020 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P5020";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74
75/*
76 rio0 = &rapidio0;
77 */
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: PowerPC,e5500@0 {
85 device_type = "cpu";
86 reg = <0>;
87 next-level-cache = <&L2_0>;
88 L2_0: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu1: PowerPC,e5500@1 {
93 device_type = "cpu";
94 reg = <1>;
95 next-level-cache = <&L2_1>;
96 L2_1: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 };
101
102 dcsr: dcsr@f00000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,dcsr", "simple-bus";
106
107 dcsr-epu@0 {
108 compatible = "fsl,dcsr-epu";
109 interrupts = <52 2 0 0
110 84 2 0 0
111 85 2 0 0>;
112 interrupt-parent = <&mpic>;
113 reg = <0x0 0x1000>;
114 };
115 dcsr-npc {
116 compatible = "fsl,dcsr-npc";
117 reg = <0x1000 0x1000 0x1000000 0x8000>;
118 };
119 dcsr-nxc@2000 {
120 compatible = "fsl,dcsr-nxc";
121 reg = <0x2000 0x1000>;
122 };
123 dcsr-corenet {
124 compatible = "fsl,dcsr-corenet";
125 reg = <0x8000 0x1000 0xB0000 0x1000>;
126 };
127 dcsr-dpaa@9000 {
128 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
129 reg = <0x9000 0x1000>;
130 };
131 dcsr-ocn@11000 {
132 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
133 reg = <0x11000 0x1000>;
134 };
135 dcsr-ddr@12000 {
136 compatible = "fsl,dcsr-ddr";
137 dev-handle = <&ddr1>;
138 reg = <0x12000 0x1000>;
139 };
140 dcsr-ddr@13000 {
141 compatible = "fsl,dcsr-ddr";
142 dev-handle = <&ddr2>;
143 reg = <0x13000 0x1000>;
144 };
145 dcsr-nal@18000 {
146 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
147 reg = <0x18000 0x1000>;
148 };
149 dcsr-rcpm@22000 {
150 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
151 reg = <0x22000 0x1000>;
152 };
153 dcsr-cpu-sb-proxy@40000 {
154 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
155 cpu-handle = <&cpu0>;
156 reg = <0x40000 0x1000>;
157 };
158 dcsr-cpu-sb-proxy@41000 {
159 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
160 cpu-handle = <&cpu1>;
161 reg = <0x41000 0x1000>;
162 };
163 };
164
165 soc: soc@ffe000000 {
166 #address-cells = <1>;
167 #size-cells = <1>;
168 device_type = "soc";
169 compatible = "simple-bus";
170 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
171 reg = <0xf 0xfe000000 0 0x00001000>;
172
173 soc-sram-error {
174 compatible = "fsl,soc-sram-error";
175 interrupts = <16 2 1 29>;
176 };
177
178 corenet-law@0 {
179 compatible = "fsl,corenet-law";
180 reg = <0x0 0x1000>;
181 fsl,num-laws = <32>;
182 };
183
184 ddr1: memory-controller@8000 {
185 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
186 reg = <0x8000 0x1000>;
187 interrupts = <16 2 1 23>;
188 };
189
190 ddr2: memory-controller@9000 {
191 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
192 reg = <0x9000 0x1000>;
193 interrupts = <16 2 1 22>;
194 };
195
196 cpc: l3-cache-controller@10000 {
197 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
198 reg = <0x10000 0x1000
199 0x11000 0x1000>;
200 interrupts = <16 2 1 27
201 16 2 1 26>;
202 };
203
204 corenet-cf@18000 {
205 compatible = "fsl,corenet-cf";
206 reg = <0x18000 0x1000>;
207 interrupts = <16 2 1 31>;
208 fsl,ccf-num-csdids = <32>;
209 fsl,ccf-num-snoopids = <32>;
210 };
211
212 iommu@20000 {
213 compatible = "fsl,pamu-v1.0", "fsl,pamu";
214 reg = <0x20000 0x4000>;
215 interrupts = <
216 24 2 0 0
217 16 2 1 30>;
218 };
219
220 mpic: pic@40000 {
221 clock-frequency = <0>;
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <4>;
225 reg = <0x40000 0x40000>;
226 compatible = "fsl,mpic", "chrp,open-pic";
227 device_type = "open-pic";
228 };
229
230 msi0: msi@41600 {
231 compatible = "fsl,mpic-msi";
232 reg = <0x41600 0x200>;
233 msi-available-ranges = <0 0x100>;
234 interrupts = <
235 0xe0 0 0 0
236 0xe1 0 0 0
237 0xe2 0 0 0
238 0xe3 0 0 0
239 0xe4 0 0 0
240 0xe5 0 0 0
241 0xe6 0 0 0
242 0xe7 0 0 0>;
243 };
244
245 msi1: msi@41800 {
246 compatible = "fsl,mpic-msi";
247 reg = <0x41800 0x200>;
248 msi-available-ranges = <0 0x100>;
249 interrupts = <
250 0xe8 0 0 0
251 0xe9 0 0 0
252 0xea 0 0 0
253 0xeb 0 0 0
254 0xec 0 0 0
255 0xed 0 0 0
256 0xee 0 0 0
257 0xef 0 0 0>;
258 };
259
260 msi2: msi@41a00 {
261 compatible = "fsl,mpic-msi";
262 reg = <0x41a00 0x200>;
263 msi-available-ranges = <0 0x100>;
264 interrupts = <
265 0xf0 0 0 0
266 0xf1 0 0 0
267 0xf2 0 0 0
268 0xf3 0 0 0
269 0xf4 0 0 0
270 0xf5 0 0 0
271 0xf6 0 0 0
272 0xf7 0 0 0>;
273 };
274
275 guts: global-utilities@e0000 {
276 compatible = "fsl,qoriq-device-config-1.0";
277 reg = <0xe0000 0xe00>;
278 fsl,has-rstcr;
279 #sleep-cells = <1>;
280 fsl,liodn-bits = <12>;
281 };
282
283 pins: global-utilities@e0e00 {
284 compatible = "fsl,qoriq-pin-control-1.0";
285 reg = <0xe0e00 0x200>;
286 #sleep-cells = <2>;
287 };
288
289 clockgen: global-utilities@e1000 {
290 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
291 reg = <0xe1000 0x1000>;
292 clock-frequency = <0>;
293 };
294
295 rcpm: global-utilities@e2000 {
296 compatible = "fsl,qoriq-rcpm-1.0";
297 reg = <0xe2000 0x1000>;
298 #sleep-cells = <1>;
299 };
300
301 sfp: sfp@e8000 {
302 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
303 reg = <0xe8000 0x1000>;
304 };
305
306 serdes: serdes@ea000 {
307 compatible = "fsl,p5020-serdes";
308 reg = <0xea000 0x1000>;
309 };
310
311 dma0: dma@100300 {
312 #address-cells = <1>;
313 #size-cells = <1>;
314 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
315 reg = <0x100300 0x4>;
316 ranges = <0x0 0x100100 0x200>;
317 cell-index = <0>;
318 dma-channel@0 {
319 compatible = "fsl,p5020-dma-channel",
320 "fsl,eloplus-dma-channel";
321 reg = <0x0 0x80>;
322 cell-index = <0>;
323 interrupts = <28 2 0 0>;
324 };
325 dma-channel@80 {
326 compatible = "fsl,p5020-dma-channel",
327 "fsl,eloplus-dma-channel";
328 reg = <0x80 0x80>;
329 cell-index = <1>;
330 interrupts = <29 2 0 0>;
331 };
332 dma-channel@100 {
333 compatible = "fsl,p5020-dma-channel",
334 "fsl,eloplus-dma-channel";
335 reg = <0x100 0x80>;
336 cell-index = <2>;
337 interrupts = <30 2 0 0>;
338 };
339 dma-channel@180 {
340 compatible = "fsl,p5020-dma-channel",
341 "fsl,eloplus-dma-channel";
342 reg = <0x180 0x80>;
343 cell-index = <3>;
344 interrupts = <31 2 0 0>;
345 };
346 };
347
348 dma1: dma@101300 {
349 #address-cells = <1>;
350 #size-cells = <1>;
351 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
352 reg = <0x101300 0x4>;
353 ranges = <0x0 0x101100 0x200>;
354 cell-index = <1>;
355 dma-channel@0 {
356 compatible = "fsl,p5020-dma-channel",
357 "fsl,eloplus-dma-channel";
358 reg = <0x0 0x80>;
359 cell-index = <0>;
360 interrupts = <32 2 0 0>;
361 };
362 dma-channel@80 {
363 compatible = "fsl,p5020-dma-channel",
364 "fsl,eloplus-dma-channel";
365 reg = <0x80 0x80>;
366 cell-index = <1>;
367 interrupts = <33 2 0 0>;
368 };
369 dma-channel@100 {
370 compatible = "fsl,p5020-dma-channel",
371 "fsl,eloplus-dma-channel";
372 reg = <0x100 0x80>;
373 cell-index = <2>;
374 interrupts = <34 2 0 0>;
375 };
376 dma-channel@180 {
377 compatible = "fsl,p5020-dma-channel",
378 "fsl,eloplus-dma-channel";
379 reg = <0x180 0x80>;
380 cell-index = <3>;
381 interrupts = <35 2 0 0>;
382 };
383 };
384
385 spi@110000 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
389 reg = <0x110000 0x1000>;
390 interrupts = <53 0x2 0 0>;
391 fsl,espi-num-chipselects = <4>;
392 };
393
394 sdhc: sdhc@114000 {
395 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
396 reg = <0x114000 0x1000>;
397 interrupts = <48 2 0 0>;
398 sdhci,auto-cmd12;
399 clock-frequency = <0>;
400 };
401
402 i2c@118000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 cell-index = <0>;
406 compatible = "fsl-i2c";
407 reg = <0x118000 0x100>;
408 interrupts = <38 2 0 0>;
409 dfsrr;
410 };
411
412 i2c@118100 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 cell-index = <1>;
416 compatible = "fsl-i2c";
417 reg = <0x118100 0x100>;
418 interrupts = <38 2 0 0>;
419 dfsrr;
420 };
421
422 i2c@119000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 cell-index = <2>;
426 compatible = "fsl-i2c";
427 reg = <0x119000 0x100>;
428 interrupts = <39 2 0 0>;
429 dfsrr;
430 };
431
432 i2c@119100 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 cell-index = <3>;
436 compatible = "fsl-i2c";
437 reg = <0x119100 0x100>;
438 interrupts = <39 2 0 0>;
439 dfsrr;
440 };
441
442 serial0: serial@11c500 {
443 cell-index = <0>;
444 device_type = "serial";
445 compatible = "ns16550";
446 reg = <0x11c500 0x100>;
447 clock-frequency = <0>;
448 interrupts = <36 2 0 0>;
449 };
450
451 serial1: serial@11c600 {
452 cell-index = <1>;
453 device_type = "serial";
454 compatible = "ns16550";
455 reg = <0x11c600 0x100>;
456 clock-frequency = <0>;
457 interrupts = <36 2 0 0>;
458 };
459
460 serial2: serial@11d500 {
461 cell-index = <2>;
462 device_type = "serial";
463 compatible = "ns16550";
464 reg = <0x11d500 0x100>;
465 clock-frequency = <0>;
466 interrupts = <37 2 0 0>;
467 };
468
469 serial3: serial@11d600 {
470 cell-index = <3>;
471 device_type = "serial";
472 compatible = "ns16550";
473 reg = <0x11d600 0x100>;
474 clock-frequency = <0>;
475 interrupts = <37 2 0 0>;
476 };
477
478 gpio0: gpio@130000 {
479 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
480 reg = <0x130000 0x1000>;
481 interrupts = <55 2 0 0>;
482 #gpio-cells = <2>;
483 gpio-controller;
484 };
485
486 usb0: usb@210000 {
487 compatible = "fsl,p5020-usb2-mph",
488 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
489 reg = <0x210000 0x1000>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 interrupts = <44 0x2 0 0>;
493 phy_type = "utmi";
494 port0;
495 };
496
497 usb1: usb@211000 {
498 compatible = "fsl,p5020-usb2-dr",
499 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
500 reg = <0x211000 0x1000>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 interrupts = <45 0x2 0 0>;
504 dr_mode = "host";
505 phy_type = "utmi";
506 };
507
508 sata@220000 {
509 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
510 reg = <0x220000 0x1000>;
511 interrupts = <68 0x2 0 0>;
512 };
513
514 sata@221000 {
515 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
516 reg = <0x221000 0x1000>;
517 interrupts = <69 0x2 0 0>;
518 };
519
520 crypto: crypto@300000 {
521 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 reg = <0x300000 0x10000>;
525 ranges = <0 0x300000 0x10000>;
526 interrupts = <92 2 0 0>;
527
528 sec_jr0: jr@1000 {
529 compatible = "fsl,sec-v4.2-job-ring",
530 "fsl,sec-v4.0-job-ring";
531 reg = <0x1000 0x1000>;
532 interrupts = <88 2 0 0>;
533 };
534
535 sec_jr1: jr@2000 {
536 compatible = "fsl,sec-v4.2-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x2000 0x1000>;
539 interrupts = <89 2 0 0>;
540 };
541
542 sec_jr2: jr@3000 {
543 compatible = "fsl,sec-v4.2-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x3000 0x1000>;
546 interrupts = <90 2 0 0>;
547 };
548
549 sec_jr3: jr@4000 {
550 compatible = "fsl,sec-v4.2-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x4000 0x1000>;
553 interrupts = <91 2 0 0>;
554 };
555
556 rtic@6000 {
557 compatible = "fsl,sec-v4.2-rtic",
558 "fsl,sec-v4.0-rtic";
559 #address-cells = <1>;
560 #size-cells = <1>;
561 reg = <0x6000 0x100>;
562 ranges = <0x0 0x6100 0xe00>;
563
564 rtic_a: rtic-a@0 {
565 compatible = "fsl,sec-v4.2-rtic-memory",
566 "fsl,sec-v4.0-rtic-memory";
567 reg = <0x00 0x20 0x100 0x80>;
568 };
569
570 rtic_b: rtic-b@20 {
571 compatible = "fsl,sec-v4.2-rtic-memory",
572 "fsl,sec-v4.0-rtic-memory";
573 reg = <0x20 0x20 0x200 0x80>;
574 };
575
576 rtic_c: rtic-c@40 {
577 compatible = "fsl,sec-v4.2-rtic-memory",
578 "fsl,sec-v4.0-rtic-memory";
579 reg = <0x40 0x20 0x300 0x80>;
580 };
581
582 rtic_d: rtic-d@60 {
583 compatible = "fsl,sec-v4.2-rtic-memory",
584 "fsl,sec-v4.0-rtic-memory";
585 reg = <0x60 0x20 0x500 0x80>;
586 };
587 };
588 };
589
590 sec_mon: sec_mon@314000 {
591 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
592 reg = <0x314000 0x1000>;
593 interrupts = <93 2 0 0>;
594 };
595 };
596
597/*
598 rapidio0: rapidio@ffe0c0000
599*/
600
601 localbus@ffe124000 {
602 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
603 interrupts = <25 2 0 0>;
604 #address-cells = <2>;
605 #size-cells = <1>;
606 };
607
608 pci0: pcie@ffe200000 {
609 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
610 device_type = "pci";
611 #size-cells = <2>;
612 #address-cells = <3>;
613 bus-range = <0x0 0xff>;
614 clock-frequency = <0x1fca055>;
615 fsl,msi = <&msi0>;
616 interrupts = <16 2 1 15>;
617
618 pcie@0 {
619 reg = <0 0 0 0 0>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 device_type = "pci";
624 interrupts = <16 2 1 15>;
625 interrupt-map-mask = <0xf800 0 0 7>;
626 interrupt-map = <
627 /* IDSEL 0x0 */
628 0000 0 0 1 &mpic 40 1 0 0
629 0000 0 0 2 &mpic 1 1 0 0
630 0000 0 0 3 &mpic 2 1 0 0
631 0000 0 0 4 &mpic 3 1 0 0
632 >;
633 };
634 };
635
636 pci1: pcie@ffe201000 {
637 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
638 device_type = "pci";
639 #size-cells = <2>;
640 #address-cells = <3>;
641 bus-range = <0 0xff>;
642 clock-frequency = <0x1fca055>;
643 fsl,msi = <&msi1>;
644 interrupts = <16 2 1 14>;
645 pcie@0 {
646 reg = <0 0 0 0 0>;
647 #interrupt-cells = <1>;
648 #size-cells = <2>;
649 #address-cells = <3>;
650 device_type = "pci";
651 interrupts = <16 2 1 14>;
652 interrupt-map-mask = <0xf800 0 0 7>;
653 interrupt-map = <
654 /* IDSEL 0x0 */
655 0000 0 0 1 &mpic 41 1 0 0
656 0000 0 0 2 &mpic 5 1 0 0
657 0000 0 0 3 &mpic 6 1 0 0
658 0000 0 0 4 &mpic 7 1 0 0
659 >;
660 };
661 };
662
663 pci2: pcie@ffe202000 {
664 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
665 device_type = "pci";
666 #size-cells = <2>;
667 #address-cells = <3>;
668 bus-range = <0x0 0xff>;
669 clock-frequency = <0x1fca055>;
670 fsl,msi = <&msi2>;
671 interrupts = <16 2 1 13>;
672 pcie@0 {
673 reg = <0 0 0 0 0>;
674 #interrupt-cells = <1>;
675 #size-cells = <2>;
676 #address-cells = <3>;
677 device_type = "pci";
678 interrupts = <16 2 1 13>;
679 interrupt-map-mask = <0xf800 0 0 7>;
680 interrupt-map = <
681 /* IDSEL 0x0 */
682 0000 0 0 1 &mpic 42 1 0 0
683 0000 0 0 2 &mpic 9 1 0 0
684 0000 0 0 3 &mpic 10 1 0 0
685 0000 0 0 4 &mpic 11 1 0 0
686 >;
687 };
688 };
689
690 pci3: pcie@ffe203000 {
691 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
692 device_type = "pci";
693 #size-cells = <2>;
694 #address-cells = <3>;
695 bus-range = <0x0 0xff>;
696 clock-frequency = <0x1fca055>;
697 fsl,msi = <&msi2>;
698 interrupts = <16 2 1 12>;
699 pcie@0 {
700 reg = <0 0 0 0 0>;
701 #interrupt-cells = <1>;
702 #size-cells = <2>;
703 #address-cells = <3>;
704 device_type = "pci";
705 interrupts = <16 2 1 12>;
706 interrupt-map-mask = <0xf800 0 0 7>;
707 interrupt-map = <
708 /* IDSEL 0x0 */
709 0000 0 0 1 &mpic 43 1 0 0
710 0000 0 0 2 &mpic 0 1 0 0
711 0000 0 0 3 &mpic 4 1 0 0
712 0000 0 0 4 &mpic 8 1 0 0
713 >;
714 };
715 };
716};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 0dc90f9bd81..b1e45a8537a 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -222,7 +222,7 @@
222 serial0: serial@4500 { 222 serial0: serial@4500 {
223 cell-index = <0>; 223 cell-index = <0>;
224 device_type = "serial"; 224 device_type = "serial";
225 compatible = "ns16550"; 225 compatible = "fsl,ns16550", "ns16550";
226 reg = <0x4500 0x100>; 226 reg = <0x4500 0x100>;
227 clock-frequency = <0>; 227 clock-frequency = <0>;
228 interrupts = <9 0x8>; 228 interrupts = <9 0x8>;
@@ -232,7 +232,7 @@
232 serial1: serial@4600 { 232 serial1: serial@4600 {
233 cell-index = <1>; 233 cell-index = <1>;
234 device_type = "serial"; 234 device_type = "serial";
235 compatible = "ns16550"; 235 compatible = "fsl,ns16550", "ns16550";
236 reg = <0x4600 0x100>; 236 reg = <0x4600 0x100>;
237 clock-frequency = <0>; 237 clock-frequency = <0>;
238 interrupts = <10 0x8>; 238 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 94a33225171..77be77116c2 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -316,7 +316,7 @@
316 serial0: serial@4500 { 316 serial0: serial@4500 {
317 cell-index = <0>; 317 cell-index = <0>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4500 0x100>; // reg base, size 320 reg = <0x4500 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 interrupts = <0x2a 0x2>; 322 interrupts = <0x2a 0x2>;
@@ -326,7 +326,7 @@
326 serial1: serial@4600 { 326 serial1: serial@4600 {
327 cell-index = <1>; 327 cell-index = <1>;
328 device_type = "serial"; 328 device_type = "serial";
329 compatible = "ns16550"; 329 compatible = "fsl,ns16550", "ns16550";
330 reg = <0x4600 0x100>; // reg base, size 330 reg = <0x4600 0x100>; // reg base, size
331 clock-frequency = <0>; // should we fill in in uboot? 331 clock-frequency = <0>; // should we fill in in uboot?
332 interrupts = <0x2a 0x2>; 332 interrupts = <0x2a 0x2>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index ee5538feb45..56bebce8784 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -347,7 +347,7 @@
347 serial0: serial@4500 { 347 serial0: serial@4500 {
348 cell-index = <0>; 348 cell-index = <0>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4500 0x100>; 351 reg = <0x4500 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <42 2>; 353 interrupts = <42 2>;
@@ -357,7 +357,7 @@
357 serial1: serial@4600 { 357 serial1: serial@4600 {
358 cell-index = <1>; 358 cell-index = <1>;
359 device_type = "serial"; 359 device_type = "serial";
360 compatible = "ns16550"; 360 compatible = "fsl,ns16550", "ns16550";
361 reg = <0x4600 0x100>; 361 reg = <0x4600 0x100>;
362 clock-frequency = <0>; 362 clock-frequency = <0>;
363 interrupts = <28 2>; 363 interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index 38c35404bdc..134a5ff917e 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -199,7 +199,7 @@
199 serial0: serial@4500 { 199 serial0: serial@4500 {
200 cell-index = <0>; 200 cell-index = <0>;
201 device_type = "serial"; 201 device_type = "serial";
202 compatible = "ns16550"; 202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4500 0x100>; 203 reg = <0x4500 0x100>;
204 clock-frequency = <0>; 204 clock-frequency = <0>;
205 interrupts = <42 2>; 205 interrupts = <42 2>;
@@ -209,7 +209,7 @@
209 serial1: serial@4600 { 209 serial1: serial@4600 {
210 cell-index = <1>; 210 cell-index = <1>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4600 0x100>; 213 reg = <0x4600 0x100>;
214 clock-frequency = <0>; 214 clock-frequency = <0>;
215 interrupts = <42 2>; 215 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index eab680ce10d..2a555738517 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -74,7 +74,7 @@
74 serial0: serial@4500 { 74 serial0: serial@4500 {
75 cell-index = <0>; 75 cell-index = <0>;
76 device_type = "serial"; 76 device_type = "serial";
77 compatible = "ns16550"; 77 compatible = "fsl,ns16550", "ns16550";
78 reg = <0x4500 0x20>; 78 reg = <0x4500 0x20>;
79 clock-frequency = <97553800>; /* Hz */ 79 clock-frequency = <97553800>; /* Hz */
80 current-speed = <115200>; 80 current-speed = <115200>;
@@ -85,7 +85,7 @@
85 serial1: serial@4600 { 85 serial1: serial@4600 {
86 cell-index = <1>; 86 cell-index = <1>;
87 device_type = "serial"; 87 device_type = "serial";
88 compatible = "ns16550"; 88 compatible = "fsl,ns16550", "ns16550";
89 reg = <0x4600 0x20>; 89 reg = <0x4600 0x20>;
90 clock-frequency = <97553800>; /* Hz */ 90 clock-frequency = <97553800>; /* Hz */
91 current-speed = <9600>; 91 current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
index 49efd44057d..4f166b01c1b 100644
--- a/arch/powerpc/boot/dts/stxssa8555.dts
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -210,7 +210,7 @@
210 serial0: serial@4500 { 210 serial0: serial@4500 {
211 cell-index = <0>; 211 cell-index = <0>;
212 device_type = "serial"; 212 device_type = "serial";
213 compatible = "ns16550"; 213 compatible = "fsl,ns16550", "ns16550";
214 reg = <0x4500 0x100>; // reg base, size 214 reg = <0x4500 0x100>; // reg base, size
215 clock-frequency = <0>; // should we fill in in uboot? 215 clock-frequency = <0>; // should we fill in in uboot?
216 interrupts = <42 2>; 216 interrupts = <42 2>;
@@ -220,7 +220,7 @@
220 serial1: serial@4600 { 220 serial1: serial@4600 {
221 cell-index = <1>; 221 cell-index = <1>;
222 device_type = "serial"; 222 device_type = "serial";
223 compatible = "ns16550"; 223 compatible = "fsl,ns16550", "ns16550";
224 reg = <0x4600 0x100>; // reg base, size 224 reg = <0x4600 0x100>; // reg base, size
225 clock-frequency = <0>; // should we fill in in uboot? 225 clock-frequency = <0>; // should we fill in in uboot?
226 interrupts = <42 2>; 226 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 0a4cedbdcb5..ed264d9ae35 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -250,7 +250,7 @@
250 serial0: serial@4500 { 250 serial0: serial@4500 {
251 cell-index = <0>; 251 cell-index = <0>;
252 device_type = "serial"; 252 device_type = "serial";
253 compatible = "ns16550"; 253 compatible = "fsl,ns16550", "ns16550";
254 reg = <0x4500 0x100>; // reg base, size 254 reg = <0x4500 0x100>; // reg base, size
255 clock-frequency = <0>; // should we fill in in uboot? 255 clock-frequency = <0>; // should we fill in in uboot?
256 interrupts = <42 2>; 256 interrupts = <42 2>;
@@ -260,7 +260,7 @@
260 serial1: serial@4600 { 260 serial1: serial@4600 {
261 cell-index = <1>; 261 cell-index = <1>;
262 device_type = "serial"; 262 device_type = "serial";
263 compatible = "ns16550"; 263 compatible = "fsl,ns16550", "ns16550";
264 reg = <0x4600 0x100>; // reg base, size 264 reg = <0x4600 0x100>; // reg base, size
265 clock-frequency = <0>; // should we fill in in uboot? 265 clock-frequency = <0>; // should we fill in in uboot?
266 interrupts = <42 2>; 266 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index f49d0918131..92524211581 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -224,7 +224,7 @@
224 serial0: serial@4500 { 224 serial0: serial@4500 {
225 cell-index = <0>; 225 cell-index = <0>;
226 device_type = "serial"; 226 device_type = "serial";
227 compatible = "ns16550"; 227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size 228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot? 229 clock-frequency = <0>; // should we fill in in uboot?
230 interrupts = <42 2>; 230 interrupts = <42 2>;
@@ -234,7 +234,7 @@
234 serial1: serial@4600 { 234 serial1: serial@4600 {
235 cell-index = <1>; 235 cell-index = <1>;
236 device_type = "serial"; 236 device_type = "serial";
237 compatible = "ns16550"; 237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size 238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot? 239 clock-frequency = <0>; // should we fill in in uboot?
240 interrupts = <42 2>; 240 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index d918752b120..6e1ac50852a 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -305,7 +305,7 @@
305 serial0: serial@4500 { 305 serial0: serial@4500 {
306 cell-index = <0>; 306 cell-index = <0>;
307 device_type = "serial"; 307 device_type = "serial";
308 compatible = "ns16550"; 308 compatible = "fsl,ns16550", "ns16550";
309 reg = <0x4500 0x100>; // reg base, size 309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot? 310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>; 311 current-speed = <115200>;
@@ -316,7 +316,7 @@
316 serial1: serial@4600 { 316 serial1: serial@4600 {
317 cell-index = <1>; 317 cell-index = <1>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4600 0x100>; // reg base, size 320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>; 322 current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 988d887c97f..161e75eac7f 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -305,7 +305,7 @@
305 serial0: serial@4500 { 305 serial0: serial@4500 {
306 cell-index = <0>; 306 cell-index = <0>;
307 device_type = "serial"; 307 device_type = "serial";
308 compatible = "ns16550"; 308 compatible = "fsl,ns16550", "ns16550";
309 reg = <0x4500 0x100>; // reg base, size 309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot? 310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>; 311 current-speed = <115200>;
@@ -316,7 +316,7 @@
316 serial1: serial@4600 { 316 serial1: serial@4600 {
317 cell-index = <1>; 317 cell-index = <1>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4600 0x100>; // reg base, size 320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>; 322 current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 81bad8cd375..aa6ff0d3dd9 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -224,7 +224,7 @@
224 serial0: serial@4500 { 224 serial0: serial@4500 {
225 cell-index = <0>; 225 cell-index = <0>;
226 device_type = "serial"; 226 device_type = "serial";
227 compatible = "ns16550"; 227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size 228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot? 229 clock-frequency = <0>; // should we fill in in uboot?
230 interrupts = <42 2>; 230 interrupts = <42 2>;
@@ -234,7 +234,7 @@
234 serial1: serial@4600 { 234 serial1: serial@4600 {
235 cell-index = <1>; 235 cell-index = <1>;
236 device_type = "serial"; 236 device_type = "serial";
237 compatible = "ns16550"; 237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size 238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot? 239 clock-frequency = <0>; // should we fill in in uboot?
240 interrupts = <42 2>; 240 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
index ac0a617b429..cc00f4ddd9a 100644
--- a/arch/powerpc/boot/dts/xcalibur1501.dts
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -531,7 +531,7 @@
531 serial0: serial@4500 { 531 serial0: serial@4500 {
532 cell-index = <0>; 532 cell-index = <0>;
533 device_type = "serial"; 533 device_type = "serial";
534 compatible = "ns16550"; 534 compatible = "fsl,ns16550", "ns16550";
535 reg = <0x4500 0x100>; 535 reg = <0x4500 0x100>;
536 clock-frequency = <0>; 536 clock-frequency = <0>;
537 interrupts = <42 2>; 537 interrupts = <42 2>;
@@ -542,7 +542,7 @@
542 serial1: serial@4600 { 542 serial1: serial@4600 {
543 cell-index = <1>; 543 cell-index = <1>;
544 device_type = "serial"; 544 device_type = "serial";
545 compatible = "ns16550"; 545 compatible = "fsl,ns16550", "ns16550";
546 reg = <0x4600 0x100>; 546 reg = <0x4600 0x100>;
547 clock-frequency = <0>; 547 clock-frequency = <0>;
548 interrupts = <42 2>; 548 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
index c41a80c55e4..8fd7b703135 100644
--- a/arch/powerpc/boot/dts/xpedite5200.dts
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -333,7 +333,7 @@
333 serial0: serial@4500 { 333 serial0: serial@4500 {
334 cell-index = <0>; 334 cell-index = <0>;
335 device_type = "serial"; 335 device_type = "serial";
336 compatible = "ns16550"; 336 compatible = "fsl,ns16550", "ns16550";
337 reg = <0x4500 0x100>; 337 reg = <0x4500 0x100>;
338 clock-frequency = <0>; 338 clock-frequency = <0>;
339 current-speed = <115200>; 339 current-speed = <115200>;
@@ -344,7 +344,7 @@
344 serial1: serial@4600 { 344 serial1: serial@4600 {
345 cell-index = <1>; 345 cell-index = <1>;
346 device_type = "serial"; 346 device_type = "serial";
347 compatible = "ns16550"; 347 compatible = "fsl,ns16550", "ns16550";
348 reg = <0x4600 0x100>; 348 reg = <0x4600 0x100>;
349 clock-frequency = <0>; 349 clock-frequency = <0>;
350 current-speed = <115200>; 350 current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
index c0efcbb4513..0baa8283d08 100644
--- a/arch/powerpc/boot/dts/xpedite5200_xmon.dts
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 current-speed = <9600>; 343 current-speed = <9600>;
@@ -348,7 +348,7 @@
348 serial1: serial@4600 { 348 serial1: serial@4600 {
349 cell-index = <1>; 349 cell-index = <1>;
350 device_type = "serial"; 350 device_type = "serial";
351 compatible = "ns16550"; 351 compatible = "fsl,ns16550", "ns16550";
352 reg = <0x4600 0x100>; 352 reg = <0x4600 0x100>;
353 clock-frequency = <0>; 353 clock-frequency = <0>;
354 current-speed = <9600>; 354 current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
index db7faf5ebb3..53c1c6a9752 100644
--- a/arch/powerpc/boot/dts/xpedite5301.dts
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -441,7 +441,7 @@
441 serial0: serial@4500 { 441 serial0: serial@4500 {
442 cell-index = <0>; 442 cell-index = <0>;
443 device_type = "serial"; 443 device_type = "serial";
444 compatible = "ns16550"; 444 compatible = "fsl,ns16550", "ns16550";
445 reg = <0x4500 0x100>; 445 reg = <0x4500 0x100>;
446 clock-frequency = <0>; 446 clock-frequency = <0>;
447 interrupts = <42 2>; 447 interrupts = <42 2>;
@@ -452,7 +452,7 @@
452 serial1: serial@4600 { 452 serial1: serial@4600 {
453 cell-index = <1>; 453 cell-index = <1>;
454 device_type = "serial"; 454 device_type = "serial";
455 compatible = "ns16550"; 455 compatible = "fsl,ns16550", "ns16550";
456 reg = <0x4600 0x100>; 456 reg = <0x4600 0x100>;
457 clock-frequency = <0>; 457 clock-frequency = <0>;
458 interrupts = <42 2>; 458 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
index c364ca6ff7d..21522598315 100644
--- a/arch/powerpc/boot/dts/xpedite5330.dts
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -477,7 +477,7 @@
477 serial0: serial@4500 { 477 serial0: serial@4500 {
478 cell-index = <0>; 478 cell-index = <0>;
479 device_type = "serial"; 479 device_type = "serial";
480 compatible = "ns16550"; 480 compatible = "fsl,ns16550", "ns16550";
481 reg = <0x4500 0x100>; 481 reg = <0x4500 0x100>;
482 clock-frequency = <0>; 482 clock-frequency = <0>;
483 interrupts = <42 2>; 483 interrupts = <42 2>;
@@ -488,7 +488,7 @@
488 serial1: serial@4600 { 488 serial1: serial@4600 {
489 cell-index = <1>; 489 cell-index = <1>;
490 device_type = "serial"; 490 device_type = "serial";
491 compatible = "ns16550"; 491 compatible = "fsl,ns16550", "ns16550";
492 reg = <0x4600 0x100>; 492 reg = <0x4600 0x100>;
493 clock-frequency = <0>; 493 clock-frequency = <0>;
494 interrupts = <42 2>; 494 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
index 7a8a4afd56c..11dbda10d75 100644
--- a/arch/powerpc/boot/dts/xpedite5370.dts
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -439,7 +439,7 @@
439 serial0: serial@4500 { 439 serial0: serial@4500 {
440 cell-index = <0>; 440 cell-index = <0>;
441 device_type = "serial"; 441 device_type = "serial";
442 compatible = "ns16550"; 442 compatible = "fsl,ns16550", "ns16550";
443 reg = <0x4500 0x100>; 443 reg = <0x4500 0x100>;
444 clock-frequency = <0>; 444 clock-frequency = <0>;
445 interrupts = <42 2>; 445 interrupts = <42 2>;
@@ -450,7 +450,7 @@
450 serial1: serial@4600 { 450 serial1: serial@4600 {
451 cell-index = <1>; 451 cell-index = <1>;
452 device_type = "serial"; 452 device_type = "serial";
453 compatible = "ns16550"; 453 compatible = "fsl,ns16550", "ns16550";
454 reg = <0x4600 0x100>; 454 reg = <0x4600 0x100>;
455 clock-frequency = <0>; 455 clock-frequency = <0>;
456 interrupts = <42 2>; 456 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/treeboot-currituck.c b/arch/powerpc/boot/treeboot-currituck.c
new file mode 100644
index 00000000000..925ae43b746
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-currituck.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright © 2011 Tony Breeds IBM Corporation
3 *
4 * Based on earlier code:
5 * Copyright (C) Paul Mackerras 1997.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * Copyright 2007 David Gibson, IBM Corporation.
14 * Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
15 * Copyright © 2011 David Kleikamp IBM Corporation
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 */
22#include <stdarg.h>
23#include <stddef.h>
24#include "types.h"
25#include "elf.h"
26#include "string.h"
27#include "stdio.h"
28#include "page.h"
29#include "ops.h"
30#include "reg.h"
31#include "io.h"
32#include "dcr.h"
33#include "4xx.h"
34#include "44x.h"
35#include "libfdt.h"
36
37BSS_STACK(4096);
38
39#define MAX_RANKS 0x4
40#define DDR3_MR0CF 0x80010011U
41
42static unsigned long long ibm_currituck_memsize;
43static unsigned long long ibm_currituck_detect_memsize(void)
44{
45 u32 reg;
46 unsigned i;
47 unsigned long long memsize = 0;
48
49 for(i = 0; i < MAX_RANKS; i++){
50 reg = mfdcrx(DDR3_MR0CF + i);
51
52 if (!(reg & 1))
53 continue;
54
55 reg &= 0x0000f000;
56 reg >>= 12;
57 memsize += (0x800000ULL << reg);
58 }
59
60 return memsize;
61}
62
63static void ibm_currituck_fixups(void)
64{
65 void *devp = finddevice("/");
66 u32 dma_ranges[7];
67
68 dt_fixup_memory(0x0ULL, ibm_currituck_memsize);
69
70 while ((devp = find_node_by_devtype(devp, "pci"))) {
71 if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) {
72 printf("%s: Failed to get dma-ranges\r\n", __func__);
73 continue;
74 }
75
76 dma_ranges[5] = ibm_currituck_memsize >> 32;
77 dma_ranges[6] = ibm_currituck_memsize & 0xffffffffUL;
78
79 setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges));
80 }
81}
82
83#define SPRN_PIR 0x11E /* Processor Indentification Register */
84void platform_init(void)
85{
86 unsigned long end_of_ram, avail_ram;
87 u32 pir_reg;
88 int node, size;
89 const u32 *timebase;
90
91 ibm_currituck_memsize = ibm_currituck_detect_memsize();
92 if (ibm_currituck_memsize >> 32)
93 end_of_ram = ~0UL;
94 else
95 end_of_ram = ibm_currituck_memsize;
96 avail_ram = end_of_ram - (unsigned long)_end;
97
98 simple_alloc_init(_end, avail_ram, 128, 64);
99 platform_ops.fixups = ibm_currituck_fixups;
100 platform_ops.exit = ibm44x_dbcr_reset;
101 pir_reg = mfspr(SPRN_PIR);
102
103 /* Make sure FDT blob is sane */
104 if (fdt_check_header(_dtb_start) != 0)
105 fatal("Invalid device tree blob\n");
106
107 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
108 "cpu", sizeof("cpu"));
109 if (!node)
110 fatal("Cannot find cpu node\n");
111 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
112 if (timebase && (size == 4))
113 timebase_period_ns = 1000000000 / *timebase;
114
115 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
116 fdt_init(_dtb_start);
117
118 serial_console_init();
119}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index c74531af72c..f090e6d2907 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -163,7 +163,7 @@ coff)
163 link_address='0x500000' 163 link_address='0x500000'
164 pie= 164 pie=
165 ;; 165 ;;
166miboot|uboot) 166miboot|uboot*)
167 # miboot and U-boot want just the bare bits, not an ELF binary 167 # miboot and U-boot want just the bare bits, not an ELF binary
168 ext=bin 168 ext=bin
169 objflags="-O binary" 169 objflags="-O binary"
@@ -244,6 +244,9 @@ gamecube|wii)
244 link_address='0x600000' 244 link_address='0x600000'
245 platformo="$object/$platform-head.o $object/$platform.o" 245 platformo="$object/$platform-head.o $object/$platform.o"
246 ;; 246 ;;
247treeboot-currituck)
248 link_address='0x1000000'
249 ;;
247treeboot-iss4xx-mpic) 250treeboot-iss4xx-mpic)
248 platformo="$object/treeboot-iss4xx.o" 251 platformo="$object/treeboot-iss4xx.o"
249 ;; 252 ;;
@@ -257,6 +260,8 @@ vmz="$tmpdir/`basename \"$kernel\"`.$ext"
257if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then 260if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
258 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$" 261 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
259 262
263 strip_size=$(stat -c %s $vmz.$$)
264
260 if [ -n "$gzip" ]; then 265 if [ -n "$gzip" ]; then
261 gzip -n -f -9 "$vmz.$$" 266 gzip -n -f -9 "$vmz.$$"
262 fi 267 fi
@@ -266,6 +271,24 @@ if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
266 else 271 else
267 vmz="$vmz.$$" 272 vmz="$vmz.$$"
268 fi 273 fi
274else
275 # Calculate the vmlinux.strip size
276 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
277 strip_size=$(stat -c %s $vmz.$$)
278 rm -f $vmz.$$
279fi
280
281# Round the size to next higher MB limit
282round_size=$(((strip_size + 0xfffff) & 0xfff00000))
283
284round_size=0x$(printf "%x" $round_size)
285link_addr=$(printf "%d" $link_address)
286
287if [ $link_addr -lt $strip_size ]; then
288 echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
289 "overlaps the address of the wrapper($link_address)"
290 echo "INFO: Fixing the link_address of wrapper to ($round_size)"
291 link_address=$round_size
269fi 292fi
270 293
271vmz="$vmz$gzip" 294vmz="$vmz$gzip"
@@ -291,6 +314,26 @@ uboot)
291 fi 314 fi
292 exit 0 315 exit 0
293 ;; 316 ;;
317uboot-obs600)
318 rm -f "$ofile"
319 # obs600 wants a multi image with an initrd, so we need to put a fake
320 # one in even when building a "normal" image.
321 if [ -n "$initrd" ]; then
322 real_rd="$initrd"
323 else
324 real_rd=`mktemp`
325 echo "\0" >>"$real_rd"
326 fi
327 ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
328 $uboot_version -d "$vmz":"$real_rd":"$dtb" "$ofile"
329 if [ -z "$initrd" ]; then
330 rm -f "$real_rd"
331 fi
332 if [ -z "$cacheit" ]; then
333 rm -f "$vmz"
334 fi
335 exit 0
336 ;;
294esac 337esac
295 338
296addsec() { 339addsec() {
diff --git a/arch/powerpc/configs/40x/klondike_defconfig b/arch/powerpc/configs/40x/klondike_defconfig
new file mode 100644
index 00000000000..c0d228dc73d
--- /dev/null
+++ b/arch/powerpc/configs/40x/klondike_defconfig
@@ -0,0 +1,55 @@
1CONFIG_40x=y
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_SYSFS_DEPRECATED=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_SYSCTL_SYSCALL=y
9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y
11CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y
13# CONFIG_WALNUT is not set
14CONFIG_APM8018X=y
15# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
16CONFIG_MATH_EMULATION=y
17# CONFIG_MIGRATION is not set
18# CONFIG_SUSPEND is not set
19CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
20CONFIG_PROC_DEVICETREE=y
21CONFIG_BLK_DEV_RAM=y
22CONFIG_BLK_DEV_RAM_SIZE=35000
23CONFIG_SCSI=y
24CONFIG_BLK_DEV_SD=y
25CONFIG_CHR_DEV_SG=y
26CONFIG_SCSI_SAS_ATTRS=y
27# CONFIG_INPUT is not set
28# CONFIG_SERIO is not set
29# CONFIG_VT is not set
30# CONFIG_UNIX98_PTYS is not set
31# CONFIG_LEGACY_PTYS is not set
32# CONFIG_DEVKMEM is not set
33# CONFIG_HW_RANDOM is not set
34# CONFIG_HWMON is not set
35# CONFIG_USB_SUPPORT is not set
36# CONFIG_IOMMU_SUPPORT is not set
37CONFIG_EXT2_FS=y
38CONFIG_EXT3_FS=y
39# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
40CONFIG_EXT4_FS=y
41CONFIG_MSDOS_FS=y
42CONFIG_VFAT_FS=y
43CONFIG_PROC_KCORE=y
44CONFIG_TMPFS=y
45CONFIG_CRAMFS=y
46CONFIG_NLS_CODEPAGE_437=y
47CONFIG_NLS_ASCII=y
48CONFIG_NLS_ISO8859_1=y
49CONFIG_NLS_UTF8=y
50CONFIG_AVERAGE=y
51CONFIG_MAGIC_SYSRQ=y
52# CONFIG_SCHED_DEBUG is not set
53# CONFIG_DEBUG_BUGVERBOSE is not set
54CONFIG_SYSCTL_SYSCALL_CHECK=y
55# CONFIG_FTRACE is not set
diff --git a/arch/powerpc/configs/40x/obs600_defconfig b/arch/powerpc/configs/40x/obs600_defconfig
new file mode 100644
index 00000000000..91c110dad2d
--- /dev/null
+++ b/arch/powerpc/configs/40x/obs600_defconfig
@@ -0,0 +1,83 @@
1CONFIG_40x=y
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_EXPERT=y
8CONFIG_KALLSYMS_ALL=y
9CONFIG_MODULES=y
10CONFIG_MODULE_UNLOAD=y
11# CONFIG_BLK_DEV_BSG is not set
12# CONFIG_WALNUT is not set
13CONFIG_OBS600=y
14CONFIG_NO_HZ=y
15CONFIG_HIGH_RES_TIMERS=y
16CONFIG_MATH_EMULATION=y
17CONFIG_NET=y
18CONFIG_PACKET=y
19CONFIG_UNIX=y
20CONFIG_INET=y
21CONFIG_IP_PNP=y
22CONFIG_IP_PNP_DHCP=y
23CONFIG_IP_PNP_BOOTP=y
24# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
25# CONFIG_INET_XFRM_MODE_TUNNEL is not set
26# CONFIG_INET_XFRM_MODE_BEET is not set
27# CONFIG_INET_LRO is not set
28# CONFIG_IPV6 is not set
29CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30CONFIG_CONNECTOR=y
31CONFIG_MTD=y
32CONFIG_MTD_CMDLINE_PARTS=y
33CONFIG_MTD_OF_PARTS=y
34CONFIG_MTD_CHAR=y
35CONFIG_MTD_BLOCK=y
36CONFIG_MTD_CFI=y
37CONFIG_MTD_JEDECPROBE=y
38CONFIG_MTD_CFI_AMDSTD=y
39CONFIG_MTD_PHYSMAP_OF=y
40CONFIG_MTD_NAND=y
41CONFIG_MTD_NAND_NDFC=y
42CONFIG_PROC_DEVICETREE=y
43CONFIG_BLK_DEV_RAM=y
44CONFIG_BLK_DEV_RAM_SIZE=35000
45CONFIG_NETDEVICES=y
46CONFIG_IBM_EMAC=y
47CONFIG_IBM_EMAC_RXB=256
48CONFIG_IBM_EMAC_TXB=256
49# CONFIG_INPUT is not set
50# CONFIG_SERIO is not set
51# CONFIG_VT is not set
52CONFIG_SERIAL_8250=y
53CONFIG_SERIAL_8250_CONSOLE=y
54CONFIG_SERIAL_8250_EXTENDED=y
55CONFIG_SERIAL_8250_SHARE_IRQ=y
56CONFIG_SERIAL_OF_PLATFORM=y
57# CONFIG_HW_RANDOM is not set
58CONFIG_I2C=y
59CONFIG_I2C_CHARDEV=y
60CONFIG_I2C_IBM_IIC=y
61CONFIG_SENSORS_LM75=y
62CONFIG_THERMAL=y
63# CONFIG_USB_SUPPORT is not set
64CONFIG_RTC_CLASS=y
65CONFIG_RTC_DRV_DS1307=y
66CONFIG_EXT2_FS=y
67CONFIG_PROC_KCORE=y
68CONFIG_TMPFS=y
69CONFIG_CRAMFS=y
70CONFIG_NFS_FS=y
71CONFIG_NFS_V3=y
72CONFIG_ROOT_NFS=y
73CONFIG_MAGIC_SYSRQ=y
74CONFIG_DEBUG_FS=y
75CONFIG_DETECT_HUNG_TASK=y
76CONFIG_SYSCTL_SYSCALL_CHECK=y
77CONFIG_CRYPTO=y
78CONFIG_CRYPTO_CBC=y
79CONFIG_CRYPTO_ECB=y
80CONFIG_CRYPTO_PCBC=y
81CONFIG_CRYPTO_MD5=y
82CONFIG_CRYPTO_DES=y
83# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/44x/currituck_defconfig b/arch/powerpc/configs/44x/currituck_defconfig
new file mode 100644
index 00000000000..4192322f8a7
--- /dev/null
+++ b/arch/powerpc/configs/44x/currituck_defconfig
@@ -0,0 +1,110 @@
1CONFIG_44x=y
2CONFIG_SMP=y
3CONFIG_EXPERIMENTAL=y
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_SPARSE_IRQ=y
7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_EXPERT=y
9CONFIG_KALLSYMS_ALL=y
10CONFIG_PROFILING=y
11CONFIG_OPROFILE=y
12CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set
15CONFIG_PPC_47x=y
16# CONFIG_EBONY is not set
17CONFIG_CURRITUCK=y
18CONFIG_HIGHMEM=y
19CONFIG_HZ_100=y
20CONFIG_MATH_EMULATION=y
21CONFIG_IRQ_ALL_CPUS=y
22CONFIG_CMDLINE_BOOL=y
23CONFIG_CMDLINE=""
24# CONFIG_SUSPEND is not set
25CONFIG_NET=y
26CONFIG_PACKET=y
27CONFIG_UNIX=y
28CONFIG_INET=y
29CONFIG_IP_PNP=y
30CONFIG_IP_PNP_DHCP=y
31CONFIG_IP_PNP_BOOTP=y
32# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
33# CONFIG_INET_XFRM_MODE_TUNNEL is not set
34# CONFIG_INET_XFRM_MODE_BEET is not set
35# CONFIG_INET_LRO is not set
36# CONFIG_IPV6 is not set
37CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
38CONFIG_DEVTMPFS=y
39CONFIG_DEVTMPFS_MOUNT=y
40CONFIG_CONNECTOR=y
41CONFIG_MTD=y
42CONFIG_MTD_CHAR=y
43CONFIG_MTD_BLOCK=y
44CONFIG_MTD_JEDECPROBE=y
45CONFIG_MTD_CFI_AMDSTD=y
46CONFIG_MTD_PHYSMAP_OF=y
47CONFIG_PROC_DEVICETREE=y
48CONFIG_BLK_DEV_RAM=y
49CONFIG_BLK_DEV_RAM_SIZE=35000
50# CONFIG_SCSI_PROC_FS is not set
51CONFIG_BLK_DEV_SD=y
52# CONFIG_SCSI_LOWLEVEL is not set
53CONFIG_ATA=y
54# CONFIG_SATA_PMP is not set
55CONFIG_SATA_SIL24=y
56# CONFIG_ATA_SFF is not set
57CONFIG_NETDEVICES=y
58CONFIG_E1000E=y
59# CONFIG_NETDEV_10000 is not set
60# CONFIG_INPUT is not set
61# CONFIG_SERIO is not set
62# CONFIG_VT is not set
63CONFIG_SERIAL_8250=y
64CONFIG_SERIAL_8250_CONSOLE=y
65CONFIG_SERIAL_8250_EXTENDED=y
66CONFIG_SERIAL_8250_SHARE_IRQ=y
67CONFIG_SERIAL_OF_PLATFORM=y
68# CONFIG_HW_RANDOM is not set
69CONFIG_I2C=y
70CONFIG_I2C_IBM_IIC=y
71# CONFIG_HWMON is not set
72CONFIG_THERMAL=y
73CONFIG_USB=y
74CONFIG_USB_DEBUG=y
75CONFIG_USB_EHCI_HCD=y
76CONFIG_USB_OHCI_HCD=y
77CONFIG_RTC_CLASS=y
78CONFIG_RTC_DRV_M41T80=y
79CONFIG_EXT2_FS=y
80CONFIG_EXT3_FS=y
81# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
82CONFIG_EXT3_FS_POSIX_ACL=y
83CONFIG_EXT3_FS_SECURITY=y
84CONFIG_PROC_KCORE=y
85CONFIG_TMPFS=y
86CONFIG_CRAMFS=y
87CONFIG_NFS_FS=y
88CONFIG_NFS_V3=y
89CONFIG_NFS_V3_ACL=y
90CONFIG_NFS_V4=y
91CONFIG_NLS_DEFAULT="n"
92CONFIG_MAGIC_SYSRQ=y
93CONFIG_DEBUG_FS=y
94CONFIG_DEBUG_KERNEL=y
95CONFIG_DETECT_HUNG_TASK=y
96CONFIG_DEBUG_INFO=y
97CONFIG_SYSCTL_SYSCALL_CHECK=y
98CONFIG_XMON=y
99CONFIG_XMON_DEFAULT=y
100CONFIG_PPC_EARLY_DEBUG=y
101CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0x10000000
102CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x200
103CONFIG_CRYPTO=y
104CONFIG_CRYPTO_CBC=y
105CONFIG_CRYPTO_ECB=y
106CONFIG_CRYPTO_PCBC=y
107CONFIG_CRYPTO_MD5=y
108CONFIG_CRYPTO_DES=y
109# CONFIG_CRYPTO_ANSI_CPRNG is not set
110# CONFIG_CRYPTO_HW is not set
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig
index a6eb6ad05b2..ca00cf750d3 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -25,7 +25,8 @@ CONFIG_CMDLINE_BOOL=y
25CONFIG_CMDLINE="root=/dev/issblk0" 25CONFIG_CMDLINE="root=/dev/issblk0"
26# CONFIG_PCI is not set 26# CONFIG_PCI is not set
27CONFIG_ADVANCED_OPTIONS=y 27CONFIG_ADVANCED_OPTIONS=y
28CONFIG_RELOCATABLE=y 28CONFIG_NONSTATIC_KERNEL=y
29CONFIG_DYNAMIC_MEMSTART=y
29CONFIG_NET=y 30CONFIG_NET=y
30CONFIG_PACKET=y 31CONFIG_PACKET=y
31CONFIG_UNIX=y 32CONFIG_UNIX=y
diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig
new file mode 100644
index 00000000000..acf7fb28046
--- /dev/null
+++ b/arch/powerpc/configs/chroma_defconfig
@@ -0,0 +1,307 @@
1CONFIG_PPC64=y
2CONFIG_PPC_BOOK3E_64=y
3# CONFIG_VIRT_CPU_ACCOUNTING is not set
4CONFIG_SMP=y
5CONFIG_NR_CPUS=256
6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y
8CONFIG_POSIX_MQUEUE=y
9CONFIG_BSD_PROCESS_ACCT=y
10CONFIG_TASKSTATS=y
11CONFIG_TASK_DELAY_ACCT=y
12CONFIG_TASK_XACCT=y
13CONFIG_TASK_IO_ACCOUNTING=y
14CONFIG_AUDIT=y
15CONFIG_AUDITSYSCALL=y
16CONFIG_IKCONFIG=y
17CONFIG_IKCONFIG_PROC=y
18CONFIG_LOG_BUF_SHIFT=19
19CONFIG_CGROUPS=y
20CONFIG_CGROUP_DEVICE=y
21CONFIG_CPUSETS=y
22CONFIG_CGROUP_CPUACCT=y
23CONFIG_RESOURCE_COUNTERS=y
24CONFIG_CGROUP_MEM_RES_CTLR=y
25CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
26CONFIG_NAMESPACES=y
27CONFIG_RELAY=y
28CONFIG_BLK_DEV_INITRD=y
29CONFIG_INITRAMFS_SOURCE=""
30CONFIG_RD_BZIP2=y
31CONFIG_RD_LZMA=y
32CONFIG_INITRAMFS_COMPRESSION_GZIP=y
33CONFIG_KALLSYMS_ALL=y
34CONFIG_EMBEDDED=y
35CONFIG_PERF_COUNTERS=y
36CONFIG_PROFILING=y
37CONFIG_OPROFILE=y
38CONFIG_KPROBES=y
39CONFIG_MODULES=y
40CONFIG_MODULE_FORCE_LOAD=y
41CONFIG_MODULE_UNLOAD=y
42CONFIG_MODULE_FORCE_UNLOAD=y
43CONFIG_MODVERSIONS=y
44CONFIG_MODULE_SRCVERSION_ALL=y
45CONFIG_SCOM_DEBUGFS=y
46CONFIG_PPC_A2_DD2=y
47CONFIG_KVM_GUEST=y
48CONFIG_NO_HZ=y
49CONFIG_HIGH_RES_TIMERS=y
50CONFIG_HZ_100=y
51# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
52CONFIG_BINFMT_MISC=y
53CONFIG_NUMA=y
54# CONFIG_MIGRATION is not set
55CONFIG_PPC_64K_PAGES=y
56CONFIG_SCHED_SMT=y
57CONFIG_CMDLINE_BOOL=y
58CONFIG_CMDLINE=""
59# CONFIG_SECCOMP is not set
60CONFIG_PCIEPORTBUS=y
61# CONFIG_PCIEASPM is not set
62CONFIG_PCI_MSI=y
63CONFIG_PACKET=y
64CONFIG_UNIX=y
65CONFIG_XFRM_USER=m
66CONFIG_XFRM_SUB_POLICY=y
67CONFIG_XFRM_STATISTICS=y
68CONFIG_NET_KEY=m
69CONFIG_NET_KEY_MIGRATE=y
70CONFIG_INET=y
71CONFIG_IP_MULTICAST=y
72CONFIG_IP_ADVANCED_ROUTER=y
73CONFIG_IP_ROUTE_MULTIPATH=y
74CONFIG_IP_ROUTE_VERBOSE=y
75CONFIG_IP_PNP=y
76CONFIG_IP_PNP_DHCP=y
77CONFIG_IP_PNP_BOOTP=y
78CONFIG_NET_IPIP=y
79CONFIG_IP_MROUTE=y
80CONFIG_IP_PIMSM_V1=y
81CONFIG_IP_PIMSM_V2=y
82CONFIG_SYN_COOKIES=y
83CONFIG_INET_AH=m
84CONFIG_INET_ESP=m
85CONFIG_INET_IPCOMP=m
86CONFIG_IPV6=y
87CONFIG_IPV6_PRIVACY=y
88CONFIG_IPV6_ROUTER_PREF=y
89CONFIG_IPV6_ROUTE_INFO=y
90CONFIG_IPV6_OPTIMISTIC_DAD=y
91CONFIG_INET6_AH=y
92CONFIG_INET6_ESP=y
93CONFIG_INET6_IPCOMP=y
94CONFIG_IPV6_MIP6=y
95CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
96CONFIG_IPV6_TUNNEL=y
97CONFIG_IPV6_MULTIPLE_TABLES=y
98CONFIG_IPV6_SUBTREES=y
99CONFIG_IPV6_MROUTE=y
100CONFIG_IPV6_PIMSM_V2=y
101CONFIG_NETFILTER=y
102CONFIG_NF_CONNTRACK=m
103CONFIG_NF_CONNTRACK_EVENTS=y
104CONFIG_NF_CT_PROTO_UDPLITE=m
105CONFIG_NF_CONNTRACK_FTP=m
106CONFIG_NF_CONNTRACK_IRC=m
107CONFIG_NF_CONNTRACK_TFTP=m
108CONFIG_NF_CT_NETLINK=m
109CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
110CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
111CONFIG_NETFILTER_XT_TARGET_MARK=m
112CONFIG_NETFILTER_XT_TARGET_NFLOG=m
113CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
114CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
115CONFIG_NETFILTER_XT_MATCH_COMMENT=m
116CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
117CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
118CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
119CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
120CONFIG_NETFILTER_XT_MATCH_DCCP=m
121CONFIG_NETFILTER_XT_MATCH_DSCP=m
122CONFIG_NETFILTER_XT_MATCH_ESP=m
123CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
124CONFIG_NETFILTER_XT_MATCH_HELPER=m
125CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
126CONFIG_NETFILTER_XT_MATCH_LENGTH=m
127CONFIG_NETFILTER_XT_MATCH_LIMIT=m
128CONFIG_NETFILTER_XT_MATCH_MAC=m
129CONFIG_NETFILTER_XT_MATCH_MARK=m
130CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
131CONFIG_NETFILTER_XT_MATCH_OWNER=m
132CONFIG_NETFILTER_XT_MATCH_POLICY=m
133CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
134CONFIG_NETFILTER_XT_MATCH_QUOTA=m
135CONFIG_NETFILTER_XT_MATCH_RATEEST=m
136CONFIG_NETFILTER_XT_MATCH_REALM=m
137CONFIG_NETFILTER_XT_MATCH_RECENT=m
138CONFIG_NETFILTER_XT_MATCH_SCTP=m
139CONFIG_NETFILTER_XT_MATCH_STATE=m
140CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
141CONFIG_NETFILTER_XT_MATCH_STRING=m
142CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
143CONFIG_NETFILTER_XT_MATCH_TIME=m
144CONFIG_NETFILTER_XT_MATCH_U32=m
145CONFIG_NF_CONNTRACK_IPV4=m
146CONFIG_IP_NF_QUEUE=m
147CONFIG_IP_NF_IPTABLES=m
148CONFIG_IP_NF_MATCH_AH=m
149CONFIG_IP_NF_MATCH_ECN=m
150CONFIG_IP_NF_MATCH_TTL=m
151CONFIG_IP_NF_FILTER=m
152CONFIG_IP_NF_TARGET_REJECT=m
153CONFIG_IP_NF_TARGET_LOG=m
154CONFIG_IP_NF_TARGET_ULOG=m
155CONFIG_NF_NAT=m
156CONFIG_IP_NF_TARGET_MASQUERADE=m
157CONFIG_IP_NF_TARGET_NETMAP=m
158CONFIG_IP_NF_TARGET_REDIRECT=m
159CONFIG_NET_TCPPROBE=y
160# CONFIG_WIRELESS is not set
161CONFIG_NET_9P=y
162CONFIG_NET_9P_DEBUG=y
163CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
164CONFIG_DEVTMPFS=y
165CONFIG_MTD=y
166CONFIG_MTD_CHAR=y
167CONFIG_MTD_BLOCK=y
168CONFIG_MTD_CFI=y
169CONFIG_MTD_CFI_ADV_OPTIONS=y
170CONFIG_MTD_CFI_LE_BYTE_SWAP=y
171CONFIG_MTD_CFI_INTELEXT=y
172CONFIG_MTD_CFI_AMDSTD=y
173CONFIG_MTD_CFI_STAA=y
174CONFIG_MTD_PHYSMAP_OF=y
175CONFIG_PROC_DEVICETREE=y
176CONFIG_BLK_DEV_LOOP=y
177CONFIG_BLK_DEV_CRYPTOLOOP=y
178CONFIG_BLK_DEV_NBD=m
179CONFIG_BLK_DEV_RAM=y
180CONFIG_BLK_DEV_RAM_SIZE=65536
181CONFIG_CDROM_PKTCDVD=y
182CONFIG_MISC_DEVICES=y
183CONFIG_BLK_DEV_SD=y
184CONFIG_BLK_DEV_SR=y
185CONFIG_BLK_DEV_SR_VENDOR=y
186CONFIG_CHR_DEV_SG=y
187CONFIG_SCSI_MULTI_LUN=y
188CONFIG_SCSI_CONSTANTS=y
189CONFIG_SCSI_SPI_ATTRS=y
190CONFIG_SCSI_FC_ATTRS=y
191CONFIG_SCSI_ISCSI_ATTRS=m
192CONFIG_SCSI_SAS_ATTRS=m
193CONFIG_SCSI_SRP_ATTRS=y
194CONFIG_ATA=y
195CONFIG_SATA_AHCI=y
196CONFIG_SATA_SIL24=y
197CONFIG_SATA_MV=y
198CONFIG_SATA_SIL=y
199CONFIG_PATA_CMD64X=y
200CONFIG_PATA_MARVELL=y
201CONFIG_PATA_SIL680=y
202CONFIG_MD=y
203CONFIG_BLK_DEV_MD=y
204CONFIG_MD_LINEAR=y
205CONFIG_BLK_DEV_DM=y
206CONFIG_DM_CRYPT=y
207CONFIG_DM_SNAPSHOT=y
208CONFIG_DM_MIRROR=y
209CONFIG_DM_ZERO=y
210CONFIG_DM_UEVENT=y
211CONFIG_NETDEVICES=y
212CONFIG_TUN=y
213CONFIG_E1000E=y
214CONFIG_TIGON3=y
215# CONFIG_WLAN is not set
216# CONFIG_INPUT is not set
217# CONFIG_SERIO is not set
218# CONFIG_VT is not set
219CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
220CONFIG_SERIAL_8250=y
221CONFIG_SERIAL_8250_CONSOLE=y
222CONFIG_HW_RANDOM=y
223CONFIG_RAW_DRIVER=y
224CONFIG_MAX_RAW_DEVS=1024
225# CONFIG_HWMON is not set
226# CONFIG_VGA_ARB is not set
227# CONFIG_USB_SUPPORT is not set
228CONFIG_EDAC=y
229CONFIG_EDAC_MM_EDAC=y
230CONFIG_RTC_CLASS=y
231CONFIG_RTC_DRV_DS1511=y
232CONFIG_RTC_DRV_DS1553=y
233CONFIG_EXT2_FS=y
234CONFIG_EXT2_FS_XATTR=y
235CONFIG_EXT2_FS_POSIX_ACL=y
236CONFIG_EXT2_FS_SECURITY=y
237CONFIG_EXT2_FS_XIP=y
238CONFIG_EXT3_FS=y
239# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
240CONFIG_EXT3_FS_POSIX_ACL=y
241CONFIG_EXT3_FS_SECURITY=y
242CONFIG_EXT4_FS=y
243# CONFIG_DNOTIFY is not set
244CONFIG_FUSE_FS=y
245CONFIG_ISO9660_FS=y
246CONFIG_JOLIET=y
247CONFIG_ZISOFS=y
248CONFIG_UDF_FS=m
249CONFIG_MSDOS_FS=y
250CONFIG_VFAT_FS=y
251CONFIG_PROC_KCORE=y
252CONFIG_TMPFS=y
253CONFIG_TMPFS_POSIX_ACL=y
254CONFIG_CONFIGFS_FS=m
255CONFIG_CRAMFS=y
256CONFIG_NFS_FS=y
257CONFIG_NFS_V3=y
258CONFIG_NFS_V3_ACL=y
259CONFIG_NFS_V4=y
260CONFIG_NFS_V4_1=y
261CONFIG_ROOT_NFS=y
262CONFIG_CIFS=y
263CONFIG_CIFS_WEAK_PW_HASH=y
264CONFIG_CIFS_XATTR=y
265CONFIG_CIFS_POSIX=y
266CONFIG_NLS_CODEPAGE_437=y
267CONFIG_NLS_ASCII=y
268CONFIG_NLS_ISO8859_1=y
269CONFIG_CRC_CCITT=m
270CONFIG_CRC_T10DIF=y
271CONFIG_LIBCRC32C=m
272CONFIG_PRINTK_TIME=y
273CONFIG_MAGIC_SYSRQ=y
274CONFIG_STRIP_ASM_SYMS=y
275CONFIG_DETECT_HUNG_TASK=y
276# CONFIG_SCHED_DEBUG is not set
277CONFIG_DEBUG_INFO=y
278CONFIG_FTRACE_SYSCALLS=y
279CONFIG_PPC_EMULATED_STATS=y
280CONFIG_XMON=y
281CONFIG_XMON_DEFAULT=y
282CONFIG_VIRQ_DEBUG=y
283CONFIG_PPC_EARLY_DEBUG=y
284CONFIG_KEYS_DEBUG_PROC_KEYS=y
285CONFIG_CRYPTO_NULL=m
286CONFIG_CRYPTO_TEST=m
287CONFIG_CRYPTO_CCM=m
288CONFIG_CRYPTO_GCM=m
289CONFIG_CRYPTO_PCBC=m
290CONFIG_CRYPTO_MICHAEL_MIC=m
291CONFIG_CRYPTO_SHA256=m
292CONFIG_CRYPTO_SHA512=m
293CONFIG_CRYPTO_TGR192=m
294CONFIG_CRYPTO_WP512=m
295CONFIG_CRYPTO_AES=m
296CONFIG_CRYPTO_ANUBIS=m
297CONFIG_CRYPTO_BLOWFISH=m
298CONFIG_CRYPTO_CAST5=m
299CONFIG_CRYPTO_CAST6=m
300CONFIG_CRYPTO_KHAZAD=m
301CONFIG_CRYPTO_SALSA20=m
302CONFIG_CRYPTO_SERPENT=m
303CONFIG_CRYPTO_TEA=m
304CONFIG_CRYPTO_TWOFISH=m
305CONFIG_CRYPTO_LZO=m
306# CONFIG_CRYPTO_ANSI_CPRNG is not set
307CONFIG_VIRTUALIZATION=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index f087de6ec03..f8aef205d22 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -37,6 +37,8 @@ CONFIG_FSL_LBC=y
37CONFIG_PCI=y 37CONFIG_PCI=y
38CONFIG_PCIEPORTBUS=y 38CONFIG_PCIEPORTBUS=y
39# CONFIG_PCIEASPM is not set 39# CONFIG_PCIEASPM is not set
40CONFIG_RAPIDIO=y
41CONFIG_FSL_RIO=y
40CONFIG_NET=y 42CONFIG_NET=y
41CONFIG_PACKET=y 43CONFIG_PACKET=y
42CONFIG_UNIX=y 44CONFIG_UNIX=y
@@ -94,17 +96,17 @@ CONFIG_SATA_SIL24=y
94CONFIG_SATA_SIL=y 96CONFIG_SATA_SIL=y
95CONFIG_PATA_SIL680=y 97CONFIG_PATA_SIL680=y
96CONFIG_NETDEVICES=y 98CONFIG_NETDEVICES=y
97CONFIG_VITESSE_PHY=y 99CONFIG_FSL_PQ_MDIO=y
98CONFIG_FIXED_PHY=y
99CONFIG_NET_ETHERNET=y
100CONFIG_E1000=y 100CONFIG_E1000=y
101CONFIG_E1000E=y 101CONFIG_E1000E=y
102CONFIG_FSL_PQ_MDIO=y 102CONFIG_VITESSE_PHY=y
103CONFIG_FIXED_PHY=y
103# CONFIG_INPUT_MOUSEDEV is not set 104# CONFIG_INPUT_MOUSEDEV is not set
104# CONFIG_INPUT_KEYBOARD is not set 105# CONFIG_INPUT_KEYBOARD is not set
105# CONFIG_INPUT_MOUSE is not set 106# CONFIG_INPUT_MOUSE is not set
106CONFIG_SERIO_LIBPS2=y 107CONFIG_SERIO_LIBPS2=y
107# CONFIG_LEGACY_PTYS is not set 108# CONFIG_LEGACY_PTYS is not set
109CONFIG_PPC_EPAPR_HV_BYTECHAN=y
108CONFIG_SERIAL_8250=y 110CONFIG_SERIAL_8250=y
109CONFIG_SERIAL_8250_CONSOLE=y 111CONFIG_SERIAL_8250_CONSOLE=y
110CONFIG_SERIAL_8250_EXTENDED=y 112CONFIG_SERIAL_8250_EXTENDED=y
@@ -155,6 +157,7 @@ CONFIG_VFAT_FS=y
155CONFIG_NTFS_FS=y 157CONFIG_NTFS_FS=y
156CONFIG_PROC_KCORE=y 158CONFIG_PROC_KCORE=y
157CONFIG_TMPFS=y 159CONFIG_TMPFS=y
160CONFIG_HUGETLBFS=y
158CONFIG_JFFS2_FS=y 161CONFIG_JFFS2_FS=y
159CONFIG_CRAMFS=y 162CONFIG_CRAMFS=y
160CONFIG_NFS_FS=y 163CONFIG_NFS_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 782822c32d1..7ed8d4cf271 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,8 @@ CONFIG_P5020_DS=y
23CONFIG_NO_HZ=y 23CONFIG_NO_HZ=y
24CONFIG_HIGH_RES_TIMERS=y 24CONFIG_HIGH_RES_TIMERS=y
25CONFIG_BINFMT_MISC=m 25CONFIG_BINFMT_MISC=m
26CONFIG_RAPIDIO=y
27CONFIG_FSL_RIO=y
26CONFIG_NET=y 28CONFIG_NET=y
27CONFIG_PACKET=y 29CONFIG_PACKET=y
28CONFIG_UNIX=y 30CONFIG_UNIX=y
@@ -57,7 +59,6 @@ CONFIG_MISC_DEVICES=y
57CONFIG_EEPROM_LEGACY=y 59CONFIG_EEPROM_LEGACY=y
58CONFIG_NETDEVICES=y 60CONFIG_NETDEVICES=y
59CONFIG_DUMMY=y 61CONFIG_DUMMY=y
60CONFIG_NET_ETHERNET=y
61CONFIG_INPUT_FF_MEMLESS=m 62CONFIG_INPUT_FF_MEMLESS=m
62# CONFIG_INPUT_MOUSEDEV is not set 63# CONFIG_INPUT_MOUSEDEV is not set
63# CONFIG_INPUT_KEYBOARD is not set 64# CONFIG_INPUT_KEYBOARD is not set
@@ -81,6 +82,7 @@ CONFIG_EXT3_FS=y
81# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 82# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
82CONFIG_PROC_KCORE=y 83CONFIG_PROC_KCORE=y
83CONFIG_TMPFS=y 84CONFIG_TMPFS=y
85CONFIG_HUGETLBFS=y
84# CONFIG_MISC_FILESYSTEMS is not set 86# CONFIG_MISC_FILESYSTEMS is not set
85CONFIG_PARTITION_ADVANCED=y 87CONFIG_PARTITION_ADVANCED=y
86CONFIG_MAC_PARTITION=y 88CONFIG_MAC_PARTITION=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index a1e5a178a4a..f37a2ab4888 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,5 +1,4 @@
1CONFIG_PPC_85xx=y 1CONFIG_PPC_85xx=y
2CONFIG_PHYS_64BIT=y
3CONFIG_EXPERIMENTAL=y 2CONFIG_EXPERIMENTAL=y
4CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y 4CONFIG_POSIX_MQUEUE=y
@@ -93,15 +92,14 @@ CONFIG_SATA_FSL=y
93CONFIG_PATA_ALI=y 92CONFIG_PATA_ALI=y
94CONFIG_NETDEVICES=y 93CONFIG_NETDEVICES=y
95CONFIG_DUMMY=y 94CONFIG_DUMMY=y
95CONFIG_FS_ENET=y
96CONFIG_UCC_GETH=y
97CONFIG_GIANFAR=y
96CONFIG_MARVELL_PHY=y 98CONFIG_MARVELL_PHY=y
97CONFIG_DAVICOM_PHY=y 99CONFIG_DAVICOM_PHY=y
98CONFIG_CICADA_PHY=y 100CONFIG_CICADA_PHY=y
99CONFIG_VITESSE_PHY=y 101CONFIG_VITESSE_PHY=y
100CONFIG_FIXED_PHY=y 102CONFIG_FIXED_PHY=y
101CONFIG_NET_ETHERNET=y
102CONFIG_FS_ENET=y
103CONFIG_GIANFAR=y
104CONFIG_UCC_GETH=y
105CONFIG_INPUT_FF_MEMLESS=m 103CONFIG_INPUT_FF_MEMLESS=m
106# CONFIG_INPUT_MOUSEDEV is not set 104# CONFIG_INPUT_MOUSEDEV is not set
107# CONFIG_INPUT_KEYBOARD is not set 105# CONFIG_INPUT_KEYBOARD is not set
@@ -120,6 +118,9 @@ CONFIG_NVRAM=y
120CONFIG_I2C=y 118CONFIG_I2C=y
121CONFIG_I2C_CPM=m 119CONFIG_I2C_CPM=m
122CONFIG_I2C_MPC=y 120CONFIG_I2C_MPC=y
121CONFIG_SPI=y
122CONFIG_SPI_FSL_SPI=y
123CONFIG_SPI_FSL_ESPI=y
123CONFIG_GPIO_MPC8XXX=y 124CONFIG_GPIO_MPC8XXX=y
124# CONFIG_HWMON is not set 125# CONFIG_HWMON is not set
125CONFIG_VIDEO_OUTPUT_CONTROL=y 126CONFIG_VIDEO_OUTPUT_CONTROL=y
@@ -163,6 +164,10 @@ CONFIG_USB_OHCI_HCD=y
163CONFIG_USB_OHCI_HCD_PPC_OF_BE=y 164CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
164CONFIG_USB_OHCI_HCD_PPC_OF_LE=y 165CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
165CONFIG_USB_STORAGE=y 166CONFIG_USB_STORAGE=y
167CONFIG_MMC=y
168CONFIG_MMC_SDHCI=y
169CONFIG_MMC_SDHCI_PLTFM=y
170CONFIG_MMC_SDHCI_OF_ESDHC=y
166CONFIG_EDAC=y 171CONFIG_EDAC=y
167CONFIG_EDAC_MM_EDAC=y 172CONFIG_EDAC_MM_EDAC=y
168CONFIG_RTC_CLASS=y 173CONFIG_RTC_CLASS=y
@@ -182,6 +187,7 @@ CONFIG_VFAT_FS=y
182CONFIG_NTFS_FS=y 187CONFIG_NTFS_FS=y
183CONFIG_PROC_KCORE=y 188CONFIG_PROC_KCORE=y
184CONFIG_TMPFS=y 189CONFIG_TMPFS=y
190CONFIG_HUGETLBFS=y
185CONFIG_ADFS_FS=m 191CONFIG_ADFS_FS=m
186CONFIG_AFFS_FS=m 192CONFIG_AFFS_FS=m
187CONFIG_HFS_FS=m 193CONFIG_HFS_FS=m
@@ -213,4 +219,5 @@ CONFIG_CRYPTO_SHA256=y
213CONFIG_CRYPTO_SHA512=y 219CONFIG_CRYPTO_SHA512=y
214CONFIG_CRYPTO_AES=y 220CONFIG_CRYPTO_AES=y
215# CONFIG_CRYPTO_ANSI_CPRNG is not set 221# CONFIG_CRYPTO_ANSI_CPRNG is not set
222CONFIG_CRYPTO_DEV_FSL_CAAM=y
216CONFIG_CRYPTO_DEV_TALITOS=y 223CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index dd1e41386c4..abdcd317cda 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -1,5 +1,4 @@
1CONFIG_PPC_85xx=y 1CONFIG_PPC_85xx=y
2CONFIG_PHYS_64BIT=y
3CONFIG_SMP=y 2CONFIG_SMP=y
4CONFIG_NR_CPUS=8 3CONFIG_NR_CPUS=8
5CONFIG_EXPERIMENTAL=y 4CONFIG_EXPERIMENTAL=y
@@ -26,6 +25,7 @@ CONFIG_MPC85xx_MDS=y
26CONFIG_MPC8536_DS=y 25CONFIG_MPC8536_DS=y
27CONFIG_MPC85xx_DS=y 26CONFIG_MPC85xx_DS=y
28CONFIG_MPC85xx_RDB=y 27CONFIG_MPC85xx_RDB=y
28CONFIG_P1010_RDB=y
29CONFIG_P1022_DS=y 29CONFIG_P1022_DS=y
30CONFIG_P1023_RDS=y 30CONFIG_P1023_RDS=y
31CONFIG_SOCRATES=y 31CONFIG_SOCRATES=y
@@ -94,15 +94,14 @@ CONFIG_SATA_FSL=y
94CONFIG_PATA_ALI=y 94CONFIG_PATA_ALI=y
95CONFIG_NETDEVICES=y 95CONFIG_NETDEVICES=y
96CONFIG_DUMMY=y 96CONFIG_DUMMY=y
97CONFIG_FS_ENET=y
98CONFIG_UCC_GETH=y
99CONFIG_GIANFAR=y
97CONFIG_MARVELL_PHY=y 100CONFIG_MARVELL_PHY=y
98CONFIG_DAVICOM_PHY=y 101CONFIG_DAVICOM_PHY=y
99CONFIG_CICADA_PHY=y 102CONFIG_CICADA_PHY=y
100CONFIG_VITESSE_PHY=y 103CONFIG_VITESSE_PHY=y
101CONFIG_FIXED_PHY=y 104CONFIG_FIXED_PHY=y
102CONFIG_NET_ETHERNET=y
103CONFIG_FS_ENET=y
104CONFIG_GIANFAR=y
105CONFIG_UCC_GETH=y
106CONFIG_INPUT_FF_MEMLESS=m 105CONFIG_INPUT_FF_MEMLESS=m
107# CONFIG_INPUT_MOUSEDEV is not set 106# CONFIG_INPUT_MOUSEDEV is not set
108# CONFIG_INPUT_KEYBOARD is not set 107# CONFIG_INPUT_KEYBOARD is not set
@@ -121,6 +120,9 @@ CONFIG_NVRAM=y
121CONFIG_I2C=y 120CONFIG_I2C=y
122CONFIG_I2C_CPM=m 121CONFIG_I2C_CPM=m
123CONFIG_I2C_MPC=y 122CONFIG_I2C_MPC=y
123CONFIG_SPI=y
124CONFIG_SPI_FSL_SPI=y
125CONFIG_SPI_FSL_ESPI=y
124CONFIG_GPIO_MPC8XXX=y 126CONFIG_GPIO_MPC8XXX=y
125# CONFIG_HWMON is not set 127# CONFIG_HWMON is not set
126CONFIG_VIDEO_OUTPUT_CONTROL=y 128CONFIG_VIDEO_OUTPUT_CONTROL=y
@@ -164,6 +166,10 @@ CONFIG_USB_OHCI_HCD=y
164CONFIG_USB_OHCI_HCD_PPC_OF_BE=y 166CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
165CONFIG_USB_OHCI_HCD_PPC_OF_LE=y 167CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
166CONFIG_USB_STORAGE=y 168CONFIG_USB_STORAGE=y
169CONFIG_MMC=y
170CONFIG_MMC_SDHCI=y
171CONFIG_MMC_SDHCI_PLTFM=y
172CONFIG_MMC_SDHCI_OF_ESDHC=y
167CONFIG_EDAC=y 173CONFIG_EDAC=y
168CONFIG_EDAC_MM_EDAC=y 174CONFIG_EDAC_MM_EDAC=y
169CONFIG_RTC_CLASS=y 175CONFIG_RTC_CLASS=y
@@ -183,6 +189,7 @@ CONFIG_VFAT_FS=y
183CONFIG_NTFS_FS=y 189CONFIG_NTFS_FS=y
184CONFIG_PROC_KCORE=y 190CONFIG_PROC_KCORE=y
185CONFIG_TMPFS=y 191CONFIG_TMPFS=y
192CONFIG_HUGETLBFS=y
186CONFIG_ADFS_FS=m 193CONFIG_ADFS_FS=m
187CONFIG_AFFS_FS=m 194CONFIG_AFFS_FS=m
188CONFIG_HFS_FS=m 195CONFIG_HFS_FS=m
@@ -214,4 +221,5 @@ CONFIG_CRYPTO_SHA256=y
214CONFIG_CRYPTO_SHA512=y 221CONFIG_CRYPTO_SHA512=y
215CONFIG_CRYPTO_AES=y 222CONFIG_CRYPTO_AES=y
216# CONFIG_CRYPTO_ANSI_CPRNG is not set 223# CONFIG_CRYPTO_ANSI_CPRNG is not set
224CONFIG_CRYPTO_DEV_FSL_CAAM=y
217CONFIG_CRYPTO_DEV_TALITOS=y 225CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 535711fcb13..2156e077859 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -390,6 +390,11 @@ CONFIG_HUGETLBFS=y
390CONFIG_HFS_FS=m 390CONFIG_HFS_FS=m
391CONFIG_HFSPLUS_FS=m 391CONFIG_HFSPLUS_FS=m
392CONFIG_CRAMFS=m 392CONFIG_CRAMFS=m
393CONFIG_SQUASHFS=m
394CONFIG_SQUASHFS_XATTR=y
395CONFIG_SQUASHFS_ZLIB=y
396CONFIG_SQUASHFS_LZO=y
397CONFIG_SQUASHFS_XZ=y
393CONFIG_NFS_FS=y 398CONFIG_NFS_FS=y
394CONFIG_NFS_V3=y 399CONFIG_NFS_V3=y
395CONFIG_NFS_V3_ACL=y 400CONFIG_NFS_V3_ACL=y
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index 185c292b0f1..ded867871e9 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -6,10 +6,10 @@ CONFIG_NR_CPUS=2
6CONFIG_EXPERIMENTAL=y 6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y 7CONFIG_SYSVIPC=y
8CONFIG_POSIX_MQUEUE=y 8CONFIG_POSIX_MQUEUE=y
9CONFIG_NAMESPACES=y 9CONFIG_SPARSE_IRQ=y
10CONFIG_BLK_DEV_INITRD=y 10CONFIG_BLK_DEV_INITRD=y
11CONFIG_EXPERT=y 11CONFIG_CC_OPTIMIZE_FOR_SIZE=y
12CONFIG_KALLSYMS_EXTRA_PASS=y 12CONFIG_EMBEDDED=y
13# CONFIG_PERF_EVENTS is not set 13# CONFIG_PERF_EVENTS is not set
14# CONFIG_COMPAT_BRK is not set 14# CONFIG_COMPAT_BRK is not set
15CONFIG_SLAB=y 15CONFIG_SLAB=y
@@ -17,6 +17,7 @@ CONFIG_PROFILING=y
17CONFIG_OPROFILE=m 17CONFIG_OPROFILE=m
18CONFIG_MODULES=y 18CONFIG_MODULES=y
19CONFIG_MODULE_UNLOAD=y 19CONFIG_MODULE_UNLOAD=y
20# CONFIG_PPC_POWERNV is not set
20# CONFIG_PPC_PSERIES is not set 21# CONFIG_PPC_PSERIES is not set
21# CONFIG_PPC_PMAC is not set 22# CONFIG_PPC_PMAC is not set
22CONFIG_PPC_PS3=y 23CONFIG_PPC_PS3=y
@@ -27,14 +28,14 @@ CONFIG_PS3_VRAM=m
27CONFIG_PS3_LPM=m 28CONFIG_PS3_LPM=m
28# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set 29# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
29CONFIG_HIGH_RES_TIMERS=y 30CONFIG_HIGH_RES_TIMERS=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
30CONFIG_BINFMT_MISC=y 32CONFIG_BINFMT_MISC=y
31CONFIG_KEXEC=y 33CONFIG_KEXEC=y
32CONFIG_SPARSE_IRQ=y
33# CONFIG_SPARSEMEM_VMEMMAP is not set 34# CONFIG_SPARSEMEM_VMEMMAP is not set
34CONFIG_SCHED_SMT=y 35CONFIG_SCHED_SMT=y
35CONFIG_CMDLINE_BOOL=y 36CONFIG_CMDLINE_BOOL=y
36CONFIG_CMDLINE="" 37CONFIG_CMDLINE=""
37CONFIG_PM=y 38CONFIG_PM_RUNTIME=y
38CONFIG_PM_DEBUG=y 39CONFIG_PM_DEBUG=y
39# CONFIG_SECCOMP is not set 40# CONFIG_SECCOMP is not set
40# CONFIG_PCI is not set 41# CONFIG_PCI is not set
@@ -81,20 +82,23 @@ CONFIG_SCSI_MULTI_LUN=y
81CONFIG_MD=y 82CONFIG_MD=y
82CONFIG_BLK_DEV_DM=m 83CONFIG_BLK_DEV_DM=m
83CONFIG_NETDEVICES=y 84CONFIG_NETDEVICES=y
84CONFIG_NET_ETHERNET=y 85# CONFIG_NET_VENDOR_BROADCOM is not set
86# CONFIG_NET_VENDOR_CHELSIO is not set
87# CONFIG_NET_VENDOR_INTEL is not set
88# CONFIG_NET_VENDOR_MARVELL is not set
89# CONFIG_NET_VENDOR_MICREL is not set
90# CONFIG_NET_VENDOR_NATSEMI is not set
91# CONFIG_NET_VENDOR_SEEQ is not set
92# CONFIG_NET_VENDOR_STMICRO is not set
85CONFIG_GELIC_NET=y 93CONFIG_GELIC_NET=y
86CONFIG_GELIC_WIRELESS=y 94CONFIG_GELIC_WIRELESS=y
87# CONFIG_NETDEV_10000 is not set 95# CONFIG_NET_VENDOR_XILINX is not set
88CONFIG_USB_USBNET=m 96CONFIG_USB_USBNET=m
89# CONFIG_USB_NET_CDCETHER is not set 97# CONFIG_USB_NET_CDCETHER is not set
98# CONFIG_USB_NET_CDC_NCM is not set
90# CONFIG_USB_NET_NET1080 is not set 99# CONFIG_USB_NET_NET1080 is not set
91# CONFIG_USB_NET_CDC_SUBSET is not set 100# CONFIG_USB_NET_CDC_SUBSET is not set
92# CONFIG_USB_NET_ZAURUS is not set 101# CONFIG_USB_NET_ZAURUS is not set
93CONFIG_PPP=m
94CONFIG_PPP_MULTILINK=y
95CONFIG_PPP_ASYNC=m
96CONFIG_PPP_DEFLATE=m
97CONFIG_PPPOE=m
98CONFIG_INPUT_FF_MEMLESS=m 102CONFIG_INPUT_FF_MEMLESS=m
99# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 103# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
100CONFIG_INPUT_JOYDEV=m 104CONFIG_INPUT_JOYDEV=m
@@ -135,22 +139,21 @@ CONFIG_USB=m
135CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 139CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
136CONFIG_USB_DEVICEFS=y 140CONFIG_USB_DEVICEFS=y
137# CONFIG_USB_DEVICE_CLASS is not set 141# CONFIG_USB_DEVICE_CLASS is not set
142CONFIG_USB_SUSPEND=y
138CONFIG_USB_MON=m 143CONFIG_USB_MON=m
139CONFIG_USB_EHCI_HCD=m 144CONFIG_USB_EHCI_HCD=m
140CONFIG_USB_EHCI_TT_NEWSCHED=y
141# CONFIG_USB_EHCI_HCD_PPC_OF is not set 145# CONFIG_USB_EHCI_HCD_PPC_OF is not set
142CONFIG_USB_OHCI_HCD=m 146CONFIG_USB_OHCI_HCD=m
143CONFIG_USB_STORAGE=m 147CONFIG_USB_STORAGE=m
144CONFIG_RTC_CLASS=y 148CONFIG_RTC_CLASS=y
145CONFIG_RTC_DRV_PS3=m 149CONFIG_RTC_DRV_PS3=y
150# CONFIG_IOMMU_SUPPORT is not set
146CONFIG_EXT2_FS=m 151CONFIG_EXT2_FS=m
147CONFIG_EXT3_FS=m 152CONFIG_EXT3_FS=m
148# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 153# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
149CONFIG_EXT4_FS=y 154CONFIG_EXT4_FS=y
150CONFIG_INOTIFY=y
151CONFIG_QUOTA=y 155CONFIG_QUOTA=y
152CONFIG_QFMT_V2=y 156CONFIG_QFMT_V2=y
153CONFIG_AUTOFS_FS=m
154CONFIG_AUTOFS4_FS=m 157CONFIG_AUTOFS4_FS=m
155CONFIG_ISO9660_FS=m 158CONFIG_ISO9660_FS=m
156CONFIG_JOLIET=y 159CONFIG_JOLIET=y
@@ -167,19 +170,17 @@ CONFIG_CIFS=m
167CONFIG_NLS=y 170CONFIG_NLS=y
168CONFIG_NLS_CODEPAGE_437=y 171CONFIG_NLS_CODEPAGE_437=y
169CONFIG_NLS_ISO8859_1=y 172CONFIG_NLS_ISO8859_1=y
173CONFIG_CRC_CCITT=m
170CONFIG_CRC_T10DIF=y 174CONFIG_CRC_T10DIF=y
171CONFIG_MAGIC_SYSRQ=y 175CONFIG_MAGIC_SYSRQ=y
172CONFIG_DEBUG_FS=y 176CONFIG_DEBUG_FS=y
173CONFIG_DEBUG_KERNEL=y
174CONFIG_DETECT_HUNG_TASK=y 177CONFIG_DETECT_HUNG_TASK=y
175CONFIG_PROVE_LOCKING=y 178CONFIG_PROVE_LOCKING=y
176CONFIG_DEBUG_LOCKDEP=y 179CONFIG_DEBUG_LOCKDEP=y
177CONFIG_DEBUG_SPINLOCK_SLEEP=y
178CONFIG_DEBUG_INFO=y 180CONFIG_DEBUG_INFO=y
179CONFIG_DEBUG_WRITECOUNT=y 181CONFIG_DEBUG_WRITECOUNT=y
180CONFIG_DEBUG_MEMORY_INIT=y 182CONFIG_DEBUG_MEMORY_INIT=y
181CONFIG_DEBUG_LIST=y 183CONFIG_DEBUG_LIST=y
182# CONFIG_RCU_CPU_STALL_DETECTOR is not set
183CONFIG_SYSCTL_SYSCALL_CHECK=y 184CONFIG_SYSCTL_SYSCALL_CHECK=y
184# CONFIG_FTRACE is not set 185# CONFIG_FTRACE is not set
185CONFIG_DEBUG_STACKOVERFLOW=y 186CONFIG_DEBUG_STACKOVERFLOW=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index a72f2415a64..30e7d0d20e4 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -304,6 +304,11 @@ CONFIG_PROC_KCORE=y
304CONFIG_TMPFS=y 304CONFIG_TMPFS=y
305CONFIG_HUGETLBFS=y 305CONFIG_HUGETLBFS=y
306CONFIG_CRAMFS=m 306CONFIG_CRAMFS=m
307CONFIG_SQUASHFS=m
308CONFIG_SQUASHFS_XATTR=y
309CONFIG_SQUASHFS_ZLIB=y
310CONFIG_SQUASHFS_LZO=y
311CONFIG_SQUASHFS_XZ=y
307CONFIG_NFS_FS=y 312CONFIG_NFS_FS=y
308CONFIG_NFS_V3=y 313CONFIG_NFS_V3=y
309CONFIG_NFS_V3_ACL=y 314CONFIG_NFS_V3_ACL=y
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d51df17c7e6..7e313f1ed18 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -34,3 +34,5 @@ header-y += termios.h
34header-y += types.h 34header-y += types.h
35header-y += ucontext.h 35header-y += ucontext.h
36header-y += unistd.h 36header-y += unistd.h
37
38generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e30442c539c..ad55a1ccb9f 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -201,6 +201,7 @@ extern const char *powerpc_base_platform;
201#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) 201#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
202#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) 202#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
203#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000) 203#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
204#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
204 205
205#ifndef __ASSEMBLY__ 206#ifndef __ASSEMBLY__
206 207
@@ -425,7 +426,7 @@ extern const char *powerpc_base_platform;
425 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 426 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
426 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 427 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
427 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 428 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
428 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE) 429 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
429#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 430#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 432 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -437,7 +438,7 @@ extern const char *powerpc_base_platform;
437#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 438#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
438 439
439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 440#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
440 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 441 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
441 442
442#ifdef __powerpc64__ 443#ifdef __powerpc64__
443#ifdef CONFIG_PPC_BOOK3E 444#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 6ec1c380a4d..487d46ff68a 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -110,11 +110,11 @@ static inline u64 cputime64_to_jiffies64(const cputime_t ct)
110/* 110/*
111 * Convert cputime <-> microseconds 111 * Convert cputime <-> microseconds
112 */ 112 */
113extern u64 __cputime_msec_factor; 113extern u64 __cputime_usec_factor;
114 114
115static inline unsigned long cputime_to_usecs(const cputime_t ct) 115static inline unsigned long cputime_to_usecs(const cputime_t ct)
116{ 116{
117 return mulhdu((__force u64) ct, __cputime_msec_factor) * USEC_PER_MSEC; 117 return mulhdu((__force u64) ct, __cputime_usec_factor);
118} 118}
119 119
120static inline cputime_t usecs_to_cputime(const unsigned long us) 120static inline cputime_t usecs_to_cputime(const unsigned long us)
@@ -127,7 +127,7 @@ static inline cputime_t usecs_to_cputime(const unsigned long us)
127 sec = us / 1000000; 127 sec = us / 1000000;
128 if (ct) { 128 if (ct) {
129 ct *= tb_ticks_per_sec; 129 ct *= tb_ticks_per_sec;
130 do_div(ct, 1000); 130 do_div(ct, 1000000);
131 } 131 }
132 if (sec) 132 if (sec)
133 ct += (cputime_t) sec * tb_ticks_per_sec; 133 ct += (cputime_t) sec * tb_ticks_per_sec;
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 00000000000..b955012939a
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
1/* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_FSL_IFC_H
23#define __ASM_FSL_IFC_H
24
25#include <linux/compiler.h>
26#include <linux/types.h>
27#include <linux/io.h>
28
29#include <linux/of_platform.h>
30#include <linux/interrupt.h>
31
32#define FSL_IFC_BANK_COUNT 4
33
34/*
35 * CSPR - Chip Select Property Register
36 */
37#define CSPR_BA 0xFFFF0000
38#define CSPR_BA_SHIFT 16
39#define CSPR_PORT_SIZE 0x00000180
40#define CSPR_PORT_SIZE_SHIFT 7
41/* Port Size 8 bit */
42#define CSPR_PORT_SIZE_8 0x00000080
43/* Port Size 16 bit */
44#define CSPR_PORT_SIZE_16 0x00000100
45/* Port Size 32 bit */
46#define CSPR_PORT_SIZE_32 0x00000180
47/* Write Protect */
48#define CSPR_WP 0x00000040
49#define CSPR_WP_SHIFT 6
50/* Machine Select */
51#define CSPR_MSEL 0x00000006
52#define CSPR_MSEL_SHIFT 1
53/* NOR */
54#define CSPR_MSEL_NOR 0x00000000
55/* NAND */
56#define CSPR_MSEL_NAND 0x00000002
57/* GPCM */
58#define CSPR_MSEL_GPCM 0x00000004
59/* Bank Valid */
60#define CSPR_V 0x00000001
61#define CSPR_V_SHIFT 0
62
63/*
64 * Address Mask Register
65 */
66#define IFC_AMASK_MASK 0xFFFF0000
67#define IFC_AMASK_SHIFT 16
68#define IFC_AMASK(n) (IFC_AMASK_MASK << \
69 (__ilog2(n) - IFC_AMASK_SHIFT))
70
71/*
72 * Chip Select Option Register IFC_NAND Machine
73 */
74/* Enable ECC Encoder */
75#define CSOR_NAND_ECC_ENC_EN 0x80000000
76#define CSOR_NAND_ECC_MODE_MASK 0x30000000
77/* 4 bit correction per 520 Byte sector */
78#define CSOR_NAND_ECC_MODE_4 0x00000000
79/* 8 bit correction per 528 Byte sector */
80#define CSOR_NAND_ECC_MODE_8 0x10000000
81/* Enable ECC Decoder */
82#define CSOR_NAND_ECC_DEC_EN 0x04000000
83/* Row Address Length */
84#define CSOR_NAND_RAL_MASK 0x01800000
85#define CSOR_NAND_RAL_SHIFT 20
86#define CSOR_NAND_RAL_1 0x00000000
87#define CSOR_NAND_RAL_2 0x00800000
88#define CSOR_NAND_RAL_3 0x01000000
89#define CSOR_NAND_RAL_4 0x01800000
90/* Page Size 512b, 2k, 4k */
91#define CSOR_NAND_PGS_MASK 0x00180000
92#define CSOR_NAND_PGS_SHIFT 16
93#define CSOR_NAND_PGS_512 0x00000000
94#define CSOR_NAND_PGS_2K 0x00080000
95#define CSOR_NAND_PGS_4K 0x00100000
96/* Spare region Size */
97#define CSOR_NAND_SPRZ_MASK 0x0000E000
98#define CSOR_NAND_SPRZ_SHIFT 13
99#define CSOR_NAND_SPRZ_16 0x00000000
100#define CSOR_NAND_SPRZ_64 0x00002000
101#define CSOR_NAND_SPRZ_128 0x00004000
102#define CSOR_NAND_SPRZ_210 0x00006000
103#define CSOR_NAND_SPRZ_218 0x00008000
104#define CSOR_NAND_SPRZ_224 0x0000A000
105/* Pages Per Block */
106#define CSOR_NAND_PB_MASK 0x00000700
107#define CSOR_NAND_PB_SHIFT 8
108#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
109/* Time for Read Enable High to Output High Impedance */
110#define CSOR_NAND_TRHZ_MASK 0x0000001C
111#define CSOR_NAND_TRHZ_SHIFT 2
112#define CSOR_NAND_TRHZ_20 0x00000000
113#define CSOR_NAND_TRHZ_40 0x00000004
114#define CSOR_NAND_TRHZ_60 0x00000008
115#define CSOR_NAND_TRHZ_80 0x0000000C
116#define CSOR_NAND_TRHZ_100 0x00000010
117/* Buffer control disable */
118#define CSOR_NAND_BCTLD 0x00000001
119
120/*
121 * Chip Select Option Register - NOR Flash Mode
122 */
123/* Enable Address shift Mode */
124#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
125/* Page Read Enable from NOR device */
126#define CSOR_NOR_PGRD_EN 0x10000000
127/* AVD Toggle Enable during Burst Program */
128#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
129/* Address Data Multiplexing Shift */
130#define CSOR_NOR_ADM_MASK 0x0003E000
131#define CSOR_NOR_ADM_SHIFT_SHIFT 13
132#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
133/* Type of the NOR device hooked */
134#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
135#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
136/* Time for Read Enable High to Output High Impedance */
137#define CSOR_NOR_TRHZ_MASK 0x0000001C
138#define CSOR_NOR_TRHZ_SHIFT 2
139#define CSOR_NOR_TRHZ_20 0x00000000
140#define CSOR_NOR_TRHZ_40 0x00000004
141#define CSOR_NOR_TRHZ_60 0x00000008
142#define CSOR_NOR_TRHZ_80 0x0000000C
143#define CSOR_NOR_TRHZ_100 0x00000010
144/* Buffer control disable */
145#define CSOR_NOR_BCTLD 0x00000001
146
147/*
148 * Chip Select Option Register - GPCM Mode
149 */
150/* GPCM Mode - Normal */
151#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
152/* GPCM Mode - GenericASIC */
153#define CSOR_GPCM_GPMODE_ASIC 0x80000000
154/* Parity Mode odd/even */
155#define CSOR_GPCM_PARITY_EVEN 0x40000000
156/* Parity Checking enable/disable */
157#define CSOR_GPCM_PAR_EN 0x20000000
158/* GPCM Timeout Count */
159#define CSOR_GPCM_GPTO_MASK 0x0F000000
160#define CSOR_GPCM_GPTO_SHIFT 24
161#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
162/* GPCM External Access Termination mode for read access */
163#define CSOR_GPCM_RGETA_EXT 0x00080000
164/* GPCM External Access Termination mode for write access */
165#define CSOR_GPCM_WGETA_EXT 0x00040000
166/* Address Data Multiplexing Shift */
167#define CSOR_GPCM_ADM_MASK 0x0003E000
168#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
169#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
170/* Generic ASIC Parity error indication delay */
171#define CSOR_GPCM_GAPERRD_MASK 0x00000180
172#define CSOR_GPCM_GAPERRD_SHIFT 7
173#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
174/* Time for Read Enable High to Output High Impedance */
175#define CSOR_GPCM_TRHZ_MASK 0x0000001C
176#define CSOR_GPCM_TRHZ_20 0x00000000
177#define CSOR_GPCM_TRHZ_40 0x00000004
178#define CSOR_GPCM_TRHZ_60 0x00000008
179#define CSOR_GPCM_TRHZ_80 0x0000000C
180#define CSOR_GPCM_TRHZ_100 0x00000010
181/* Buffer control disable */
182#define CSOR_GPCM_BCTLD 0x00000001
183
184/*
185 * Ready Busy Status Register (RB_STAT)
186 */
187/* CSn is READY */
188#define IFC_RB_STAT_READY_CS0 0x80000000
189#define IFC_RB_STAT_READY_CS1 0x40000000
190#define IFC_RB_STAT_READY_CS2 0x20000000
191#define IFC_RB_STAT_READY_CS3 0x10000000
192
193/*
194 * General Control Register (GCR)
195 */
196#define IFC_GCR_MASK 0x8000F800
197/* reset all IFC hardware */
198#define IFC_GCR_SOFT_RST_ALL 0x80000000
199/* Turnaroud Time of external buffer */
200#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
201#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
202
203/*
204 * Common Event and Error Status Register (CM_EVTER_STAT)
205 */
206/* Chip select error */
207#define IFC_CM_EVTER_STAT_CSER 0x80000000
208
209/*
210 * Common Event and Error Enable Register (CM_EVTER_EN)
211 */
212/* Chip select error checking enable */
213#define IFC_CM_EVTER_EN_CSEREN 0x80000000
214
215/*
216 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
217 */
218/* Chip select error interrupt enable */
219#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
220
221/*
222 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
223 */
224/* transaction type of error Read/Write */
225#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
226#define IFC_CM_ERATTR0_ERAID 0x0FF00000
227#define IFC_CM_ERATTR0_ERAID_SHIFT 20
228#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
229#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
230
231/*
232 * Clock Control Register (CCR)
233 */
234#define IFC_CCR_MASK 0x0F0F8800
235/* Clock division ratio */
236#define IFC_CCR_CLK_DIV_MASK 0x0F000000
237#define IFC_CCR_CLK_DIV_SHIFT 24
238#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
239/* IFC Clock Delay */
240#define IFC_CCR_CLK_DLY_MASK 0x000F0000
241#define IFC_CCR_CLK_DLY_SHIFT 16
242#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
243/* Invert IFC clock before sending out */
244#define IFC_CCR_INV_CLK_EN 0x00008000
245/* Fedback IFC Clock */
246#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
247
248/*
249 * Clock Status Register (CSR)
250 */
251/* Clk is stable */
252#define IFC_CSR_CLK_STAT_STABLE 0x80000000
253
254/*
255 * IFC_NAND Machine Specific Registers
256 */
257/*
258 * NAND Configuration Register (NCFGR)
259 */
260/* Auto Boot Mode */
261#define IFC_NAND_NCFGR_BOOT 0x80000000
262/* Addressing Mode-ROW0+n/COL0 */
263#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
264/* Addressing Mode-ROW0+n/COL0+n */
265#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
266/* Number of loop iterations of FIR sequences for multi page operations */
267#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
268#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
269#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
270/* Number of wait cycles */
271#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
272#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
273
274/*
275 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
276 */
277/* General purpose FCM flash command bytes CMD0-CMD7 */
278#define IFC_NAND_FCR0_CMD0 0xFF000000
279#define IFC_NAND_FCR0_CMD0_SHIFT 24
280#define IFC_NAND_FCR0_CMD1 0x00FF0000
281#define IFC_NAND_FCR0_CMD1_SHIFT 16
282#define IFC_NAND_FCR0_CMD2 0x0000FF00
283#define IFC_NAND_FCR0_CMD2_SHIFT 8
284#define IFC_NAND_FCR0_CMD3 0x000000FF
285#define IFC_NAND_FCR0_CMD3_SHIFT 0
286#define IFC_NAND_FCR1_CMD4 0xFF000000
287#define IFC_NAND_FCR1_CMD4_SHIFT 24
288#define IFC_NAND_FCR1_CMD5 0x00FF0000
289#define IFC_NAND_FCR1_CMD5_SHIFT 16
290#define IFC_NAND_FCR1_CMD6 0x0000FF00
291#define IFC_NAND_FCR1_CMD6_SHIFT 8
292#define IFC_NAND_FCR1_CMD7 0x000000FF
293#define IFC_NAND_FCR1_CMD7_SHIFT 0
294
295/*
296 * Flash ROW and COL Address Register (ROWn, COLn)
297 */
298/* Main/spare region locator */
299#define IFC_NAND_COL_MS 0x80000000
300/* Column Address */
301#define IFC_NAND_COL_CA_MASK 0x00000FFF
302
303/*
304 * NAND Flash Byte Count Register (NAND_BC)
305 */
306/* Byte Count for read/Write */
307#define IFC_NAND_BC 0x000001FF
308
309/*
310 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
311 */
312/* NAND Machine specific opcodes OP0-OP14*/
313#define IFC_NAND_FIR0_OP0 0xFC000000
314#define IFC_NAND_FIR0_OP0_SHIFT 26
315#define IFC_NAND_FIR0_OP1 0x03F00000
316#define IFC_NAND_FIR0_OP1_SHIFT 20
317#define IFC_NAND_FIR0_OP2 0x000FC000
318#define IFC_NAND_FIR0_OP2_SHIFT 14
319#define IFC_NAND_FIR0_OP3 0x00003F00
320#define IFC_NAND_FIR0_OP3_SHIFT 8
321#define IFC_NAND_FIR0_OP4 0x000000FC
322#define IFC_NAND_FIR0_OP4_SHIFT 2
323#define IFC_NAND_FIR1_OP5 0xFC000000
324#define IFC_NAND_FIR1_OP5_SHIFT 26
325#define IFC_NAND_FIR1_OP6 0x03F00000
326#define IFC_NAND_FIR1_OP6_SHIFT 20
327#define IFC_NAND_FIR1_OP7 0x000FC000
328#define IFC_NAND_FIR1_OP7_SHIFT 14
329#define IFC_NAND_FIR1_OP8 0x00003F00
330#define IFC_NAND_FIR1_OP8_SHIFT 8
331#define IFC_NAND_FIR1_OP9 0x000000FC
332#define IFC_NAND_FIR1_OP9_SHIFT 2
333#define IFC_NAND_FIR2_OP10 0xFC000000
334#define IFC_NAND_FIR2_OP10_SHIFT 26
335#define IFC_NAND_FIR2_OP11 0x03F00000
336#define IFC_NAND_FIR2_OP11_SHIFT 20
337#define IFC_NAND_FIR2_OP12 0x000FC000
338#define IFC_NAND_FIR2_OP12_SHIFT 14
339#define IFC_NAND_FIR2_OP13 0x00003F00
340#define IFC_NAND_FIR2_OP13_SHIFT 8
341#define IFC_NAND_FIR2_OP14 0x000000FC
342#define IFC_NAND_FIR2_OP14_SHIFT 2
343
344/*
345 * Instruction opcodes to be programmed
346 * in FIR registers- 6bits
347 */
348enum ifc_nand_fir_opcodes {
349 IFC_FIR_OP_NOP,
350 IFC_FIR_OP_CA0,
351 IFC_FIR_OP_CA1,
352 IFC_FIR_OP_CA2,
353 IFC_FIR_OP_CA3,
354 IFC_FIR_OP_RA0,
355 IFC_FIR_OP_RA1,
356 IFC_FIR_OP_RA2,
357 IFC_FIR_OP_RA3,
358 IFC_FIR_OP_CMD0,
359 IFC_FIR_OP_CMD1,
360 IFC_FIR_OP_CMD2,
361 IFC_FIR_OP_CMD3,
362 IFC_FIR_OP_CMD4,
363 IFC_FIR_OP_CMD5,
364 IFC_FIR_OP_CMD6,
365 IFC_FIR_OP_CMD7,
366 IFC_FIR_OP_CW0,
367 IFC_FIR_OP_CW1,
368 IFC_FIR_OP_CW2,
369 IFC_FIR_OP_CW3,
370 IFC_FIR_OP_CW4,
371 IFC_FIR_OP_CW5,
372 IFC_FIR_OP_CW6,
373 IFC_FIR_OP_CW7,
374 IFC_FIR_OP_WBCD,
375 IFC_FIR_OP_RBCD,
376 IFC_FIR_OP_BTRD,
377 IFC_FIR_OP_RDSTAT,
378 IFC_FIR_OP_NWAIT,
379 IFC_FIR_OP_WFR,
380 IFC_FIR_OP_SBRD,
381 IFC_FIR_OP_UA,
382 IFC_FIR_OP_RB,
383};
384
385/*
386 * NAND Chip Select Register (NAND_CSEL)
387 */
388#define IFC_NAND_CSEL 0x0C000000
389#define IFC_NAND_CSEL_SHIFT 26
390#define IFC_NAND_CSEL_CS0 0x00000000
391#define IFC_NAND_CSEL_CS1 0x04000000
392#define IFC_NAND_CSEL_CS2 0x08000000
393#define IFC_NAND_CSEL_CS3 0x0C000000
394
395/*
396 * NAND Operation Sequence Start (NANDSEQ_STRT)
397 */
398/* NAND Flash Operation Start */
399#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
400/* Automatic Erase */
401#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
402/* Automatic Program */
403#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
404/* Automatic Copyback */
405#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
406/* Automatic Read Operation */
407#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
408/* Automatic Status Read */
409#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
410
411/*
412 * NAND Event and Error Status Register (NAND_EVTER_STAT)
413 */
414/* Operation Complete */
415#define IFC_NAND_EVTER_STAT_OPC 0x80000000
416/* Flash Timeout Error */
417#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
418/* Write Protect Error */
419#define IFC_NAND_EVTER_STAT_WPER 0x04000000
420/* ECC Error */
421#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
422/* RCW Load Done */
423#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
424/* Boot Loadr Done */
425#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
426/* Bad Block Indicator search select */
427#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
428
429/*
430 * NAND Flash Page Read Completion Event Status Register
431 * (PGRDCMPL_EVT_STAT)
432 */
433#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
434/* Small Page 0-15 Done */
435#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
436/* Large Page(2K) 0-3 Done */
437#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
438/* Large Page(4K) 0-1 Done */
439#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
440
441/*
442 * NAND Event and Error Enable Register (NAND_EVTER_EN)
443 */
444/* Operation complete event enable */
445#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
446/* Page read complete event enable */
447#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
448/* Flash Timeout error enable */
449#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
450/* Write Protect error enable */
451#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
452/* ECC error logging enable */
453#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
454
455/*
456 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
457 */
458/* Enable interrupt for operation complete */
459#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
460/* Enable interrupt for Page read complete */
461#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
462/* Enable interrupt for Flash timeout error */
463#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
464/* Enable interrupt for Write protect error */
465#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
466/* Enable interrupt for ECC error*/
467#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
468
469/*
470 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
471 */
472#define IFC_NAND_ERATTR0_MASK 0x0C080000
473/* Error on CS0-3 for NAND */
474#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
475#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
476#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
477#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
478/* Transaction type of error Read/Write */
479#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
480
481/*
482 * NAND Flash Status Register (NAND_FSR)
483 */
484/* First byte of data read from read status op */
485#define IFC_NAND_NFSR_RS0 0xFF000000
486/* Second byte of data read from read status op */
487#define IFC_NAND_NFSR_RS1 0x00FF0000
488
489/*
490 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
491 */
492/* Number of ECC errors on sector n (n = 0-15) */
493#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
494#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
495#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
496#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
497#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
498#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
499#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
500#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
501#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
502#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
503#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
504#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
505#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
506#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
507#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
508#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
509#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
510#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
511#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
512#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
513#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
514#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
515#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
516#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
517#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
518#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
519#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
520#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
521#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
522#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
523#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
524#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
525
526/*
527 * NAND Control Register (NANDCR)
528 */
529#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
530#define IFC_NAND_NCR_FTOCNT_SHIFT 25
531#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
532
533/*
534 * NAND_AUTOBOOT_TRGR
535 */
536/* Trigger RCW load */
537#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
538/* Trigget Auto Boot */
539#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
540
541/*
542 * NAND_MDR
543 */
544/* 1st read data byte when opcode SBRD */
545#define IFC_NAND_MDR_RDATA0 0xFF000000
546/* 2nd read data byte when opcode SBRD */
547#define IFC_NAND_MDR_RDATA1 0x00FF0000
548
549/*
550 * NOR Machine Specific Registers
551 */
552/*
553 * NOR Event and Error Status Register (NOR_EVTER_STAT)
554 */
555/* NOR Command Sequence Operation Complete */
556#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
557/* Write Protect Error */
558#define IFC_NOR_EVTER_STAT_WPER 0x04000000
559/* Command Sequence Timeout Error */
560#define IFC_NOR_EVTER_STAT_STOER 0x01000000
561
562/*
563 * NOR Event and Error Enable Register (NOR_EVTER_EN)
564 */
565/* NOR Command Seq complete event enable */
566#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
567/* Write Protect Error Checking Enable */
568#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
569/* Timeout Error Enable */
570#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
571
572/*
573 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
574 */
575/* Enable interrupt for OPC complete */
576#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
577/* Enable interrupt for write protect error */
578#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
579/* Enable interrupt for timeout error */
580#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
581
582/*
583 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
584 */
585/* Source ID for error transaction */
586#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
587/* AXI ID for error transation */
588#define IFC_NOR_ERATTR0_ERAID 0x000FF000
589/* Chip select corresponds to NOR error */
590#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
591#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
592#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
593#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
594/* Type of transaction read/write */
595#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
596
597/*
598 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
599 */
600#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
601#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
602
603/*
604 * NOR Control Register (NORCR)
605 */
606#define IFC_NORCR_MASK 0x0F0F0000
607/* No. of Address/Data Phase */
608#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
609#define IFC_NORCR_NUM_PHASE_SHIFT 24
610#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
611/* Sequence Timeout Count */
612#define IFC_NORCR_STOCNT_MASK 0x000F0000
613#define IFC_NORCR_STOCNT_SHIFT 16
614#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
615
616/*
617 * GPCM Machine specific registers
618 */
619/*
620 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
621 */
622/* Timeout error */
623#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
624/* Parity error */
625#define IFC_GPCM_EVTER_STAT_PER 0x01000000
626
627/*
628 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
629 */
630/* Timeout error enable */
631#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
632/* Parity error enable */
633#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
634
635/*
636 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
637 */
638/* Enable Interrupt for timeout error */
639#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
640/* Enable Interrupt for Parity error */
641#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
642
643/*
644 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
645 */
646/* Source ID for error transaction */
647#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
648/* AXI ID for error transaction */
649#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
650/* Chip select corresponds to GPCM error */
651#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
652#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
653#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
654#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
655/* Type of transaction read/Write */
656#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
657
658/*
659 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
660 */
661/* On which beat of address/data parity error is observed */
662#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
663/* Parity Error on byte */
664#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
665/* Parity Error reported in addr or data phase */
666#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
667
668/*
669 * GPCM Status Register (GPCM_STAT)
670 */
671#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
672
673/*
674 * IFC Controller NAND Machine registers
675 */
676struct fsl_ifc_nand {
677 __be32 ncfgr;
678 u32 res1[0x4];
679 __be32 nand_fcr0;
680 __be32 nand_fcr1;
681 u32 res2[0x8];
682 __be32 row0;
683 u32 res3;
684 __be32 col0;
685 u32 res4;
686 __be32 row1;
687 u32 res5;
688 __be32 col1;
689 u32 res6;
690 __be32 row2;
691 u32 res7;
692 __be32 col2;
693 u32 res8;
694 __be32 row3;
695 u32 res9;
696 __be32 col3;
697 u32 res10[0x24];
698 __be32 nand_fbcr;
699 u32 res11;
700 __be32 nand_fir0;
701 __be32 nand_fir1;
702 __be32 nand_fir2;
703 u32 res12[0x10];
704 __be32 nand_csel;
705 u32 res13;
706 __be32 nandseq_strt;
707 u32 res14;
708 __be32 nand_evter_stat;
709 u32 res15;
710 __be32 pgrdcmpl_evt_stat;
711 u32 res16[0x2];
712 __be32 nand_evter_en;
713 u32 res17[0x2];
714 __be32 nand_evter_intr_en;
715 u32 res18[0x2];
716 __be32 nand_erattr0;
717 __be32 nand_erattr1;
718 u32 res19[0x10];
719 __be32 nand_fsr;
720 u32 res20;
721 __be32 nand_eccstat[4];
722 u32 res21[0x20];
723 __be32 nanndcr;
724 u32 res22[0x2];
725 __be32 nand_autoboot_trgr;
726 u32 res23;
727 __be32 nand_mdr;
728 u32 res24[0x5C];
729};
730
731/*
732 * IFC controller NOR Machine registers
733 */
734struct fsl_ifc_nor {
735 __be32 nor_evter_stat;
736 u32 res1[0x2];
737 __be32 nor_evter_en;
738 u32 res2[0x2];
739 __be32 nor_evter_intr_en;
740 u32 res3[0x2];
741 __be32 nor_erattr0;
742 __be32 nor_erattr1;
743 __be32 nor_erattr2;
744 u32 res4[0x4];
745 __be32 norcr;
746 u32 res5[0xEF];
747};
748
749/*
750 * IFC controller GPCM Machine registers
751 */
752struct fsl_ifc_gpcm {
753 __be32 gpcm_evter_stat;
754 u32 res1[0x2];
755 __be32 gpcm_evter_en;
756 u32 res2[0x2];
757 __be32 gpcm_evter_intr_en;
758 u32 res3[0x2];
759 __be32 gpcm_erattr0;
760 __be32 gpcm_erattr1;
761 __be32 gpcm_erattr2;
762 __be32 gpcm_stat;
763 u32 res4[0x1F3];
764};
765
766/*
767 * IFC Controller Registers
768 */
769struct fsl_ifc_regs {
770 __be32 ifc_rev;
771 u32 res1[0x3];
772 struct {
773 __be32 cspr;
774 u32 res2[0x2];
775 } cspr_cs[FSL_IFC_BANK_COUNT];
776 u32 res3[0x18];
777 struct {
778 __be32 amask;
779 u32 res4[0x2];
780 } amask_cs[FSL_IFC_BANK_COUNT];
781 u32 res5[0x18];
782 struct {
783 __be32 csor;
784 u32 res6[0x2];
785 } csor_cs[FSL_IFC_BANK_COUNT];
786 u32 res7[0x18];
787 struct {
788 __be32 ftim[4];
789 u32 res8[0x8];
790 } ftim_cs[FSL_IFC_BANK_COUNT];
791 u32 res9[0x60];
792 __be32 rb_stat;
793 u32 res10[0x2];
794 __be32 ifc_gcr;
795 u32 res11[0x2];
796 __be32 cm_evter_stat;
797 u32 res12[0x2];
798 __be32 cm_evter_en;
799 u32 res13[0x2];
800 __be32 cm_evter_intr_en;
801 u32 res14[0x2];
802 __be32 cm_erattr0;
803 __be32 cm_erattr1;
804 u32 res15[0x2];
805 __be32 ifc_ccr;
806 __be32 ifc_csr;
807 u32 res16[0x2EB];
808 struct fsl_ifc_nand ifc_nand;
809 struct fsl_ifc_nor ifc_nor;
810 struct fsl_ifc_gpcm ifc_gpcm;
811};
812
813extern unsigned int convert_ifc_address(phys_addr_t addr_base);
814extern int fsl_ifc_find(phys_addr_t addr_base);
815
816/* overview of the fsl ifc controller */
817
818struct fsl_ifc_ctrl {
819 /* device info */
820 struct device *dev;
821 struct fsl_ifc_regs __iomem *regs;
822 int irq;
823 int nand_irq;
824 spinlock_t lock;
825 void *nand;
826
827 u32 nand_stat;
828 wait_queue_head_t nand_wait;
829};
830
831extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
832
833
834#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8a0b5ece8f7..420b45368fc 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -238,8 +238,6 @@ struct fsl_lbc_regs {
238#define FPAR_LP_CI_SHIFT 0 238#define FPAR_LP_CI_SHIFT 0
239 __be32 fbcr; /**< Flash Byte Count Register */ 239 __be32 fbcr; /**< Flash Byte Count Register */
240#define FBCR_BC 0x00000FFF 240#define FBCR_BC 0x00000FFF
241 u8 res11[0x8];
242 u8 res8[0xF00];
243}; 241};
244 242
245/* 243/*
@@ -294,6 +292,11 @@ struct fsl_lbc_ctrl {
294 292
295 /* status read from LTESR by irq handler */ 293 /* status read from LTESR by irq handler */
296 unsigned int irq_status; 294 unsigned int irq_status;
295
296#ifdef CONFIG_SUSPEND
297 /* save regs when system go to deep-sleep */
298 struct fsl_lbc_regs *saved_regs;
299#endif
297}; 300};
298 301
299extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, 302extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 86004930a78..dfdb95bc59a 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
5#include <asm/page.h> 5#include <asm/page.h>
6 6
7extern struct kmem_cache *hugepte_cache; 7extern struct kmem_cache *hugepte_cache;
8extern void __init reserve_hugetlb_gpages(void);
9 8
10static inline pte_t *hugepd_page(hugepd_t hpd) 9static inline pte_t *hugepd_page(hugepd_t hpd)
11{ 10{
@@ -22,14 +21,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
22 unsigned pdshift) 21 unsigned pdshift)
23{ 22{
24 /* 23 /*
25 * On 32-bit, we have multiple higher-level table entries that point to 24 * On FSL BookE, we have multiple higher-level table entries that
26 * the same hugepte. Just use the first one since they're all 25 * point to the same hugepte. Just use the first one since they're all
27 * identical. So for that case, idx=0. 26 * identical. So for that case, idx=0.
28 */ 27 */
29 unsigned long idx = 0; 28 unsigned long idx = 0;
30 29
31 pte_t *dir = hugepd_page(*hpdp); 30 pte_t *dir = hugepd_page(*hpdp);
32#ifdef CONFIG_PPC64 31#ifndef CONFIG_PPC_FSL_BOOK3E
33 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp); 32 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
34#endif 33#endif
35 34
@@ -53,7 +52,8 @@ static inline int is_hugepage_only_range(struct mm_struct *mm,
53} 52}
54#endif 53#endif
55 54
56void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte); 55void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
56 pte_t pte);
57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr); 57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
58 58
59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, 59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
@@ -124,7 +124,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
124 unsigned long addr, pte_t *ptep, 124 unsigned long addr, pte_t *ptep,
125 pte_t pte, int dirty) 125 pte_t pte, int dirty)
126{ 126{
127#ifdef HUGETLB_NEED_PRELOAD
128 /*
129 * The "return 1" forces a call of update_mmu_cache, which will write a
130 * TLB entry. Without this, platforms that don't do a write of the TLB
131 * entry in the TLB miss handler asm will fault ad infinitum.
132 */
133 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
134 return 1;
135#else
127 return ptep_set_access_flags(vma, addr, ptep, pte, dirty); 136 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
137#endif
128} 138}
129 139
130static inline pte_t huge_ptep_get(pte_t *ptep) 140static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -142,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
142} 152}
143 153
144#else /* ! CONFIG_HUGETLB_PAGE */ 154#else /* ! CONFIG_HUGETLB_PAGE */
145static inline void reserve_hugetlb_gpages(void)
146{
147 pr_err("Cannot reserve gpages without hugetlb enabled\n");
148}
149static inline void flush_hugetlb_page(struct vm_area_struct *vma, 155static inline void flush_hugetlb_page(struct vm_area_struct *vma,
150 unsigned long vmaddr) 156 unsigned long vmaddr)
151{ 157{
152} 158}
159#endif /* CONFIG_HUGETLB_PAGE */
160
161
162/*
163 * FSL Book3E platforms require special gpage handling - the gpages
164 * are reserved early in the boot process by memblock instead of via
165 * the .dts as on IBM platforms.
166 */
167#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
168extern void __init reserve_hugetlb_gpages(void);
169#else
170static inline void reserve_hugetlb_gpages(void)
171{
172}
153#endif 173#endif
154 174
155#endif /* _ASM_POWERPC_HUGETLB_H */ 175#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
index bffd062adf7..c9776202d7e 100644
--- a/arch/powerpc/include/asm/kdump.h
+++ b/arch/powerpc/include/asm/kdump.h
@@ -32,11 +32,11 @@
32 32
33#ifndef __ASSEMBLY__ 33#ifndef __ASSEMBLY__
34 34
35#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_RELOCATABLE) 35#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_NONSTATIC_KERNEL)
36extern void reserve_kdump_trampoline(void); 36extern void reserve_kdump_trampoline(void);
37extern void setup_kdump_trampoline(void); 37extern void setup_kdump_trampoline(void);
38#else 38#else
39/* !CRASH_DUMP || RELOCATABLE */ 39/* !CRASH_DUMP || !NONSTATIC_KERNEL */
40static inline void reserve_kdump_trampoline(void) { ; } 40static inline void reserve_kdump_trampoline(void) { ; }
41static inline void setup_kdump_trampoline(void) { ; } 41static inline void setup_kdump_trampoline(void) { ; }
42#endif 42#endif
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index f921eb121d3..16d7e33d35e 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -49,7 +49,6 @@
49#define KEXEC_STATE_REAL_MODE 2 49#define KEXEC_STATE_REAL_MODE 2
50 50
51#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
52#include <linux/cpumask.h>
53#include <asm/reg.h> 52#include <asm/reg.h>
54 53
55typedef void (*crash_shutdown_t)(void); 54typedef void (*crash_shutdown_t)(void);
@@ -73,11 +72,6 @@ extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
73 master to copy new code to 0 */ 72 master to copy new code to 0 */
74extern int crashing_cpu; 73extern int crashing_cpu;
75extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)); 74extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
76extern cpumask_t cpus_in_sr;
77static inline int kexec_sr_activated(int cpu)
78{
79 return cpumask_test_cpu(cpu, &cpus_in_sr);
80}
81 75
82struct kimage; 76struct kimage;
83struct pt_regs; 77struct pt_regs;
@@ -94,7 +88,6 @@ extern void reserve_crashkernel(void);
94extern void machine_kexec_mask_interrupts(void); 88extern void machine_kexec_mask_interrupts(void);
95 89
96#else /* !CONFIG_KEXEC */ 90#else /* !CONFIG_KEXEC */
97static inline int kexec_sr_activated(int cpu) { return 0; }
98static inline void crash_kexec_secondary(struct pt_regs *regs) { } 91static inline void crash_kexec_secondary(struct pt_regs *regs) { }
99 92
100static inline int overlaps_crashkernel(unsigned long start, unsigned long size) 93static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
index f77c708c67a..233f9ecae76 100644
--- a/arch/powerpc/include/asm/lv1call.h
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -231,7 +231,7 @@ LV1_CALL(allocate_memory, 4, 2, 0 )
231LV1_CALL(write_htab_entry, 4, 0, 1 ) 231LV1_CALL(write_htab_entry, 4, 0, 1 )
232LV1_CALL(construct_virtual_address_space, 3, 2, 2 ) 232LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
233LV1_CALL(invalidate_htab_entries, 5, 0, 3 ) 233LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
234LV1_CALL(get_virtual_address_space_id_of_ppe, 1, 1, 4 ) 234LV1_CALL(get_virtual_address_space_id_of_ppe, 0, 1, 4 )
235LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 ) 235LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
236LV1_CALL(select_virtual_address_space, 1, 0, 7 ) 236LV1_CALL(select_virtual_address_space, 1, 0, 7 )
237LV1_CALL(pause, 1, 0, 9 ) 237LV1_CALL(pause, 1, 0, 9 )
@@ -264,7 +264,7 @@ LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
264LV1_CALL(get_spe_irq_outlet, 2, 1, 78 ) 264LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
265LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 ) 265LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
266LV1_CALL(create_repository_node, 6, 0, 90 ) 266LV1_CALL(create_repository_node, 6, 0, 90 )
267LV1_CALL(get_repository_node_value, 5, 2, 91 ) 267LV1_CALL(read_repository_node, 5, 2, 91 )
268LV1_CALL(modify_repository_node_value, 6, 0, 92 ) 268LV1_CALL(modify_repository_node_value, 6, 0, 92 )
269LV1_CALL(remove_repository_node, 4, 0, 93 ) 269LV1_CALL(remove_repository_node, 4, 0, 93 )
270LV1_CALL(read_htab_entries, 2, 5, 95 ) 270LV1_CALL(read_htab_entries, 2, 5, 95 )
@@ -276,7 +276,7 @@ LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
276LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 ) 276LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
277LV1_CALL(map_htab, 1, 1, 122 ) 277LV1_CALL(map_htab, 1, 1, 122 )
278LV1_CALL(unmap_htab, 1, 0, 123 ) 278LV1_CALL(unmap_htab, 1, 0, 123 )
279LV1_CALL(get_version_info, 0, 1, 127 ) 279LV1_CALL(get_version_info, 0, 2, 127 )
280LV1_CALL(insert_htab_entry, 6, 3, 158 ) 280LV1_CALL(insert_htab_entry, 6, 3, 158 )
281LV1_CALL(read_virtual_uart, 3, 1, 162 ) 281LV1_CALL(read_virtual_uart, 3, 1, 162 )
282LV1_CALL(write_virtual_uart, 3, 1, 163 ) 282LV1_CALL(write_virtual_uart, 3, 1, 163 )
@@ -294,9 +294,9 @@ LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
294LV1_CALL(net_add_multicast_address, 4, 0, 185 ) 294LV1_CALL(net_add_multicast_address, 4, 0, 185 )
295LV1_CALL(net_remove_multicast_address, 4, 0, 186 ) 295LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
296LV1_CALL(net_start_tx_dma, 4, 0, 187 ) 296LV1_CALL(net_start_tx_dma, 4, 0, 187 )
297LV1_CALL(net_stop_tx_dma, 3, 0, 188 ) 297LV1_CALL(net_stop_tx_dma, 2, 0, 188 )
298LV1_CALL(net_start_rx_dma, 4, 0, 189 ) 298LV1_CALL(net_start_rx_dma, 4, 0, 189 )
299LV1_CALL(net_stop_rx_dma, 3, 0, 190 ) 299LV1_CALL(net_stop_rx_dma, 2, 0, 190 )
300LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 ) 300LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
301LV1_CALL(net_set_interrupt_mask, 4, 0, 193 ) 301LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
302LV1_CALL(net_control, 6, 2, 194 ) 302LV1_CALL(net_control, 6, 2, 194 )
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index b540d6fcedd..bf37931d1ad 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -213,6 +213,9 @@ struct machdep_calls {
213 * allow assignment/enabling of the device. */ 213 * allow assignment/enabling of the device. */
214 int (*pcibios_enable_device_hook)(struct pci_dev *); 214 int (*pcibios_enable_device_hook)(struct pci_dev *);
215 215
216 /* Called after scan and before resource survey */
217 void (*pcibios_fixup_phb)(struct pci_controller *hose);
218
216 /* Called to shutdown machine specific hardware not already controlled 219 /* Called to shutdown machine specific hardware not already controlled
217 * by other drivers. 220 * by other drivers.
218 */ 221 */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 0260ea5ec3c..f5f89cafebd 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -214,6 +214,10 @@ typedef struct {
214 unsigned int id; 214 unsigned int id;
215 unsigned int active; 215 unsigned int active;
216 unsigned long vdso_base; 216 unsigned long vdso_base;
217#ifdef CONFIG_PPC_ICSWX
218 struct spinlock *cop_lockp; /* guard cop related stuff */
219 unsigned long acop; /* mask of enabled coprocessor types */
220#endif /* CONFIG_PPC_ICSWX */
217#ifdef CONFIG_PPC_MM_SLICES 221#ifdef CONFIG_PPC_MM_SLICES
218 u64 low_slices_psize; /* SLB page size encodings */ 222 u64 low_slices_psize; /* SLB page size encodings */
219 u64 high_slices_psize; /* 4 bits per slice for now */ 223 u64 high_slices_psize; /* 4 bits per slice for now */
@@ -254,6 +258,13 @@ extern int mmu_vmemmap_psize;
254 258
255#ifdef CONFIG_PPC64 259#ifdef CONFIG_PPC64
256extern unsigned long linear_map_top; 260extern unsigned long linear_map_top;
261
262/*
263 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
264 * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
265 * return 1, indicating that the tlb requires preloading.
266 */
267#define HUGETLB_NEED_PRELOAD
257#endif 268#endif
258 269
259#endif /* !__ASSEMBLY__ */ 270#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index db645ec842b..412ba493cb9 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -312,10 +312,9 @@ extern void slb_set_size(u16 size);
312 * (i.e. everything above 0xC000000000000000), except the very top 312 * (i.e. everything above 0xC000000000000000), except the very top
313 * segment, which simplifies several things. 313 * segment, which simplifies several things.
314 * 314 *
315 * - We allow for 15 significant bits of ESID and 20 bits of 315 * - We allow for 16 significant bits of ESID and 19 bits of
316 * context for user addresses. i.e. 8T (43 bits) of address space for 316 * context for user addresses. i.e. 16T (44 bits) of address space for
317 * up to 1M contexts (although the page table structure and context 317 * up to half a million contexts.
318 * allocation will need changes to take advantage of this).
319 * 318 *
320 * - The scramble function gives robust scattering in the hash 319 * - The scramble function gives robust scattering in the hash
321 * table (at least based on some initial results). The previous 320 * table (at least based on some initial results). The previous
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e6fae49e0b7..67b4d983723 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -251,6 +251,9 @@ struct mpic_irq_save {
251/* The instance data of a given MPIC */ 251/* The instance data of a given MPIC */
252struct mpic 252struct mpic
253{ 253{
254 /* The OpenFirmware dt node for this MPIC */
255 struct device_node *node;
256
254 /* The remapper for this MPIC */ 257 /* The remapper for this MPIC */
255 struct irq_host *irqhost; 258 struct irq_host *irqhost;
256 259
@@ -293,6 +296,9 @@ struct mpic
293 /* Register access method */ 296 /* Register access method */
294 enum mpic_reg_type reg_type; 297 enum mpic_reg_type reg_type;
295 298
299 /* The physical base address of the MPIC */
300 phys_addr_t paddr;
301
296 /* The various ioremap'ed bases */ 302 /* The various ioremap'ed bases */
297 struct mpic_reg_bank gregs; 303 struct mpic_reg_bank gregs;
298 struct mpic_reg_bank tmregs; 304 struct mpic_reg_bank tmregs;
@@ -331,11 +337,11 @@ struct mpic
331 * Note setting any ID (leaving those bits to 0) means standard MPIC 337 * Note setting any ID (leaving those bits to 0) means standard MPIC
332 */ 338 */
333 339
334/* This is the primary controller, only that one has IPIs and 340/*
335 * has afinity control. A non-primary MPIC always uses CPU0 341 * This is a secondary ("chained") controller; it only uses the CPU0
336 * registers only 342 * registers. Primary controllers have IPIs and affinity control.
337 */ 343 */
338#define MPIC_PRIMARY 0x00000001 344#define MPIC_SECONDARY 0x00000001
339 345
340/* Set this for a big-endian MPIC */ 346/* Set this for a big-endian MPIC */
341#define MPIC_BIG_ENDIAN 0x00000002 347#define MPIC_BIG_ENDIAN 0x00000002
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 2893e8f5406..a4b28f165b6 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -109,6 +109,14 @@ extern int opal_enter_rtas(struct rtas_args *args,
109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44 109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111#define OPAL_PCI_RESET 49 111#define OPAL_PCI_RESET 49
112#define OPAL_PCI_GET_HUB_DIAG_DATA 50
113#define OPAL_PCI_GET_PHB_DIAG_DATA 51
114#define OPAL_PCI_FENCE_PHB 52
115#define OPAL_PCI_REINIT 53
116#define OPAL_PCI_MASK_PE_ERROR 54
117#define OPAL_SET_SLOT_LED_STATUS 55
118#define OPAL_GET_EPOW_STATUS 56
119#define OPAL_SET_SYSTEM_ATTENTION_LED 57
112 120
113#ifndef __ASSEMBLY__ 121#ifndef __ASSEMBLY__
114 122
@@ -169,7 +177,11 @@ enum OpalPendingState {
169 OPAL_EVENT_NVRAM = 0x2, 177 OPAL_EVENT_NVRAM = 0x2,
170 OPAL_EVENT_RTC = 0x4, 178 OPAL_EVENT_RTC = 0x4,
171 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 179 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
172 OPAL_EVENT_CONSOLE_INPUT = 0x10 180 OPAL_EVENT_CONSOLE_INPUT = 0x10,
181 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
182 OPAL_EVENT_ERROR_LOG = 0x40,
183 OPAL_EVENT_EPOW = 0x80,
184 OPAL_EVENT_LED_STATUS = 0x100
173}; 185};
174 186
175/* Machine check related definitions */ 187/* Machine check related definitions */
@@ -258,13 +270,49 @@ enum OpalPeAction {
258 OPAL_MAP_PE = 1 270 OPAL_MAP_PE = 1
259}; 271};
260 272
273enum OpalPeltvAction {
274 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
275 OPAL_ADD_PE_TO_DOMAIN = 1
276};
277
278enum OpalMveEnableAction {
279 OPAL_DISABLE_MVE = 0,
280 OPAL_ENABLE_MVE = 1
281};
282
261enum OpalPciResetAndReinitScope { 283enum OpalPciResetAndReinitScope {
262 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 284 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
263 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 285 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
264 OPAL_PCI_IODA_RESET = 6, 286 OPAL_PCI_IODA_TABLE_RESET = 6,
287};
288
289enum OpalPciResetState {
290 OPAL_DEASSERT_RESET = 0,
291 OPAL_ASSERT_RESET = 1
265}; 292};
266 293
267enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 }; 294enum OpalPciMaskAction {
295 OPAL_UNMASK_ERROR_TYPE = 0,
296 OPAL_MASK_ERROR_TYPE = 1
297};
298
299enum OpalSlotLedType {
300 OPAL_SLOT_LED_ID_TYPE = 0,
301 OPAL_SLOT_LED_FAULT_TYPE = 1
302};
303
304enum OpalLedAction {
305 OPAL_TURN_OFF_LED = 0,
306 OPAL_TURN_ON_LED = 1,
307 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
308};
309
310enum OpalEpowStatus {
311 OPAL_EPOW_NONE = 0,
312 OPAL_EPOW_UPS = 1,
313 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
314 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
315};
268 316
269struct opal_machine_check_event { 317struct opal_machine_check_event {
270 enum OpalMCE_Version version:8; /* 0x00 */ 318 enum OpalMCE_Version version:8; /* 0x00 */
@@ -314,8 +362,74 @@ struct opal_machine_check_event {
314 } u; 362 } u;
315}; 363};
316 364
365/**
366 * This structure defines the overlay which will be used to store PHB error
367 * data upon request.
368 */
369enum {
370 OPAL_P7IOC_NUM_PEST_REGS = 128,
371};
372
373struct OpalIoP7IOCPhbErrorData {
374 uint32_t brdgCtl;
375
376 // P7IOC utl regs
377 uint32_t portStatusReg;
378 uint32_t rootCmplxStatus;
379 uint32_t busAgentStatus;
380
381 // P7IOC cfg regs
382 uint32_t deviceStatus;
383 uint32_t slotStatus;
384 uint32_t linkStatus;
385 uint32_t devCmdStatus;
386 uint32_t devSecStatus;
387
388 // cfg AER regs
389 uint32_t rootErrorStatus;
390 uint32_t uncorrErrorStatus;
391 uint32_t corrErrorStatus;
392 uint32_t tlpHdr1;
393 uint32_t tlpHdr2;
394 uint32_t tlpHdr3;
395 uint32_t tlpHdr4;
396 uint32_t sourceId;
397
398 uint32_t rsv3;
399
400 // Record data about the call to allocate a buffer.
401 uint64_t errorClass;
402 uint64_t correlator;
403
404 //P7IOC MMIO Error Regs
405 uint64_t p7iocPlssr; // n120
406 uint64_t p7iocCsr; // n110
407 uint64_t lemFir; // nC00
408 uint64_t lemErrorMask; // nC18
409 uint64_t lemWOF; // nC40
410 uint64_t phbErrorStatus; // nC80
411 uint64_t phbFirstErrorStatus; // nC88
412 uint64_t phbErrorLog0; // nCC0
413 uint64_t phbErrorLog1; // nCC8
414 uint64_t mmioErrorStatus; // nD00
415 uint64_t mmioFirstErrorStatus; // nD08
416 uint64_t mmioErrorLog0; // nD40
417 uint64_t mmioErrorLog1; // nD48
418 uint64_t dma0ErrorStatus; // nD80
419 uint64_t dma0FirstErrorStatus; // nD88
420 uint64_t dma0ErrorLog0; // nDC0
421 uint64_t dma0ErrorLog1; // nDC8
422 uint64_t dma1ErrorStatus; // nE00
423 uint64_t dma1FirstErrorStatus; // nE08
424 uint64_t dma1ErrorLog0; // nE40
425 uint64_t dma1ErrorLog1; // nE48
426 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
427 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
428};
429
317typedef struct oppanel_line { 430typedef struct oppanel_line {
318 /* XXX */ 431 const char * line;
432 uint64_t line_len;
319} oppanel_line_t; 433} oppanel_line_t;
320 434
321/* API functions */ 435/* API functions */
@@ -413,6 +527,15 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
413 uint64_t pci_mem_size); 527 uint64_t pci_mem_size);
414int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 528int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
415 529
530int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
531int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
532int64_t opal_pci_fence_phb(uint64_t phb_id);
533int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
534int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
535int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
536int64_t opal_get_epow_status(uint64_t *status);
537int64_t opal_set_system_attention_led(uint8_t led_action);
538
416/* Internal functions */ 539/* Internal functions */
417extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); 540extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
418 541
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 17722c73ba2..269c05a36d9 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -135,6 +135,7 @@ struct paca_struct {
135 u8 hard_enabled; /* set if irqs are enabled in MSR */ 135 u8 hard_enabled; /* set if irqs are enabled in MSR */
136 u8 io_sync; /* writel() needs spin_unlock sync */ 136 u8 io_sync; /* writel() needs spin_unlock sync */
137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
138 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
138 139
139#ifdef CONFIG_PPC_POWERNV 140#ifdef CONFIG_PPC_POWERNV
140 /* Pointer to OPAL machine check event structure set by the 141 /* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index dd9c4fd038e..f072e974f8a 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -92,20 +92,34 @@ extern unsigned int HPAGE_SHIFT;
92#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET) 92#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET)
93#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START)) 93#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
94 94
95#if defined(CONFIG_RELOCATABLE) 95#if defined(CONFIG_NONSTATIC_KERNEL)
96#ifndef __ASSEMBLY__ 96#ifndef __ASSEMBLY__
97 97
98extern phys_addr_t memstart_addr; 98extern phys_addr_t memstart_addr;
99extern phys_addr_t kernstart_addr; 99extern phys_addr_t kernstart_addr;
100
101#ifdef CONFIG_RELOCATABLE_PPC32
102extern long long virt_phys_offset;
100#endif 103#endif
104
105#endif /* __ASSEMBLY__ */
101#define PHYSICAL_START kernstart_addr 106#define PHYSICAL_START kernstart_addr
102#else 107
108#else /* !CONFIG_NONSTATIC_KERNEL */
103#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START) 109#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START)
104#endif 110#endif
105 111
112/* See Description below for VIRT_PHYS_OFFSET */
113#ifdef CONFIG_RELOCATABLE_PPC32
114#define VIRT_PHYS_OFFSET virt_phys_offset
115#else
116#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
117#endif
118
119
106#ifdef CONFIG_PPC64 120#ifdef CONFIG_PPC64
107#define MEMORY_START 0UL 121#define MEMORY_START 0UL
108#elif defined(CONFIG_RELOCATABLE) 122#elif defined(CONFIG_NONSTATIC_KERNEL)
109#define MEMORY_START memstart_addr 123#define MEMORY_START memstart_addr
110#else 124#else
111#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE) 125#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
@@ -125,12 +139,77 @@ extern phys_addr_t kernstart_addr;
125 * determine MEMORY_START until then. However we can determine PHYSICAL_START 139 * determine MEMORY_START until then. However we can determine PHYSICAL_START
126 * from information at hand (program counter, TLB lookup). 140 * from information at hand (program counter, TLB lookup).
127 * 141 *
142 * On BookE with RELOCATABLE (RELOCATABLE_PPC32)
143 *
144 * With RELOCATABLE_PPC32, we support loading the kernel at any physical
145 * address without any restriction on the page alignment.
146 *
147 * We find the runtime address of _stext and relocate ourselves based on
148 * the following calculation:
149 *
150 * virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
151 * MODULO(_stext.run,256M)
152 * and create the following mapping:
153 *
154 * ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
155 *
156 * When we process relocations, we cannot depend on the
157 * existing equation for the __va()/__pa() translations:
158 *
159 * __va(x) = (x) - PHYSICAL_START + KERNELBASE
160 *
161 * Where:
162 * PHYSICAL_START = kernstart_addr = Physical address of _stext
163 * KERNELBASE = Compiled virtual address of _stext.
164 *
165 * This formula holds true iff, kernel load address is TLB page aligned.
166 *
167 * In our case, we need to also account for the shift in the kernel Virtual
168 * address.
169 *
170 * E.g.,
171 *
172 * Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
173 * In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
174 *
175 * Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
176 * = 0xbc100000 , which is wrong.
177 *
178 * Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
179 * according to our mapping.
180 *
181 * Hence we use the following formula to get the translations right:
182 *
183 * __va(x) = (x) - [ PHYSICAL_START - Effective KERNELBASE ]
184 *
185 * Where :
186 * PHYSICAL_START = dynamic load address.(kernstart_addr variable)
187 * Effective KERNELBASE = virtual_base =
188 * = ALIGN_DOWN(KERNELBASE,256M) +
189 * MODULO(PHYSICAL_START,256M)
190 *
191 * To make the cost of __va() / __pa() more light weight, we introduce
192 * a new variable virt_phys_offset, which will hold :
193 *
194 * virt_phys_offset = Effective KERNELBASE - PHYSICAL_START
195 * = ALIGN_DOWN(KERNELBASE,256M) -
196 * ALIGN_DOWN(PHYSICALSTART,256M)
197 *
198 * Hence :
199 *
200 * __va(x) = x - PHYSICAL_START + Effective KERNELBASE
201 * = x + virt_phys_offset
202 *
203 * and
204 * __pa(x) = x + PHYSICAL_START - Effective KERNELBASE
205 * = x - virt_phys_offset
206 *
128 * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use 207 * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use
129 * the other definitions for __va & __pa. 208 * the other definitions for __va & __pa.
130 */ 209 */
131#ifdef CONFIG_BOOKE 210#ifdef CONFIG_BOOKE
132#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START + KERNELBASE)) 211#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))
133#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE) 212#define __pa(x) ((unsigned long)(x) - VIRT_PHYS_OFFSET)
134#else 213#else
135#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START)) 214#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START))
136#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START) 215#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
@@ -290,6 +369,7 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
290extern void copy_user_page(void *to, void *from, unsigned long vaddr, 369extern void copy_user_page(void *to, void *from, unsigned long vaddr,
291 struct page *p); 370 struct page *p);
292extern int page_is_ram(unsigned long pfn); 371extern int page_is_ram(unsigned long pfn);
372extern int devmem_is_allowed(unsigned long pfn);
293 373
294#ifdef CONFIG_PPC_SMLPAR 374#ifdef CONFIG_PPC_SMLPAR
295void arch_free_page(struct page *page, int order); 375void arch_free_page(struct page *page, int order);
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede6bc0..fed85e6290e 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do { \
130 130
131#ifdef CONFIG_HUGETLB_PAGE 131#ifdef CONFIG_HUGETLB_PAGE
132 132
133#ifdef CONFIG_PPC_MM_SLICES
133#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA 134#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
135#endif
134 136
135#endif /* !CONFIG_HUGETLB_PAGE */ 137#endif /* !CONFIG_HUGETLB_PAGE */
136 138
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 56b879ab3a4..882b6aa6c85 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -153,8 +153,8 @@ struct pci_dn {
153 153
154 int pci_ext_config_space; /* for pci devices */ 154 int pci_ext_config_space; /* for pci devices */
155 155
156#ifdef CONFIG_EEH
157 struct pci_dev *pcidev; /* back-pointer to the pci device */ 156 struct pci_dev *pcidev; /* back-pointer to the pci device */
157#ifdef CONFIG_EEH
158 int class_code; /* pci device class */ 158 int class_code; /* pci device class */
159 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 159 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
160 int eeh_config_addr; 160 int eeh_config_addr;
@@ -164,6 +164,10 @@ struct pci_dn {
164 int eeh_false_positives; /* # times this device reported #ff's */ 164 int eeh_false_positives; /* # times this device reported #ff's */
165 u32 config_space[16]; /* saved PCI config space */ 165 u32 config_space[16]; /* saved PCI config space */
166#endif 166#endif
167#define IODA_INVALID_PE (-1)
168#ifdef CONFIG_PPC_POWERNV
169 int pe_number;
170#endif
167}; 171};
168 172
169/* Get the pointer to a device_node's pci_dn */ 173/* Get the pointer to a device_node's pci_dn */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 49c3de582be..1c92013466e 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -184,8 +184,6 @@ extern void of_scan_pci_bridge(struct pci_dev *dev);
184extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 184extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
185extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); 185extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
186 186
187extern int pci_read_irq_line(struct pci_dev *dev);
188
189struct file; 187struct file;
190extern pgprot_t pci_phys_mem_access_prot(struct file *file, 188extern pgprot_t pci_phys_mem_access_prot(struct file *file,
191 unsigned long pfn, 189 unsigned long pfn,
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 88b0bd925a8..2e0e4110f7a 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,9 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
170#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 170#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
171 _PAGE_COHERENT | _PAGE_WRITETHRU)) 171 _PAGE_COHERENT | _PAGE_WRITETHRU))
172 172
173#define pgprot_cached_noncoherent(prot) \
174 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
175
173#define pgprot_writecombine pgprot_noncached_wc 176#define pgprot_writecombine pgprot_noncached_wc
174 177
175struct file; 178struct file;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index eb11a446720..b585bff1a02 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -382,6 +382,9 @@ static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
382} 382}
383#endif 383#endif
384 384
385extern unsigned long cpuidle_disable;
386enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
387
385#endif /* __KERNEL__ */ 388#endif /* __KERNEL__ */
386#endif /* __ASSEMBLY__ */ 389#endif /* __ASSEMBLY__ */
387#endif /* _ASM_POWERPC_PROCESSOR_H */ 390#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 559da199edb..7fdc2c0b7fa 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -951,6 +951,7 @@
951#define PVR_403GCX 0x00201400 951#define PVR_403GCX 0x00201400
952#define PVR_405GP 0x40110000 952#define PVR_405GP 0x40110000
953#define PVR_476 0x11a52000 953#define PVR_476 0x11a52000
954#define PVR_476FPE 0x7ff50000
954#define PVR_STB03XXX 0x40310000 955#define PVR_STB03XXX 0x40310000
955#define PVR_NP405H 0x41410000 956#define PVR_NP405H 0x41410000
956#define PVR_NP405L 0x41610000 957#define PVR_NP405L 0x41610000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 03c48e819c8..500fe1dc43e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
188#endif 188#endif
189 189
190#ifdef CONFIG_PPC_ICSWX
191#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
192#endif
193
190/* Bit definitions for CCR1. */ 194/* Bit definitions for CCR1. */
191#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 195#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
192#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 196#define CCR1_TCS 0x00000080 /* Timer Clock Select */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 41f69ae79d4..01c143bb77a 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -245,6 +245,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
245 245
246extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal); 246extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
247 247
248#ifdef CONFIG_PPC_RTAS_DAEMON
249extern void rtas_cancel_event_scan(void);
250#else
251static inline void rtas_cancel_event_scan(void) { }
252#endif
253
248/* Error types logged. */ 254/* Error types logged. */
249#define ERR_FLAG_ALREADY_LOGGED 0x0 255#define ERR_FLAG_ALREADY_LOGGED 0x0
250#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */ 256#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
@@ -307,5 +313,17 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
307extern void __cpuinit rtas_give_timebase(void); 313extern void __cpuinit rtas_give_timebase(void);
308extern void __cpuinit rtas_take_timebase(void); 314extern void __cpuinit rtas_take_timebase(void);
309 315
316#ifdef CONFIG_PPC_RTAS
317static inline int page_is_rtas_user_buf(unsigned long pfn)
318{
319 unsigned long paddr = (pfn << PAGE_SHIFT);
320 if (paddr >= rtas_rmo_buf && paddr < (rtas_rmo_buf + RTAS_RMOBUF_MAX))
321 return 1;
322 return 0;
323}
324#else
325static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;}
326#endif
327
310#endif /* __KERNEL__ */ 328#endif /* __KERNEL__ */
311#endif /* _POWERPC_RTAS_H */ 329#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
deleted file mode 100644
index bb1e2cdeb9b..00000000000
--- a/arch/powerpc/include/asm/rwsem.h
+++ /dev/null
@@ -1,132 +0,0 @@
1#ifndef _ASM_POWERPC_RWSEM_H
2#define _ASM_POWERPC_RWSEM_H
3
4#ifndef _LINUX_RWSEM_H
5#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
6#endif
7
8#ifdef __KERNEL__
9
10/*
11 * R/W semaphores for PPC using the stuff in lib/rwsem.c.
12 * Adapted largely from include/asm-i386/rwsem.h
13 * by Paul Mackerras <paulus@samba.org>.
14 */
15
16/*
17 * the semaphore definition
18 */
19#ifdef CONFIG_PPC64
20# define RWSEM_ACTIVE_MASK 0xffffffffL
21#else
22# define RWSEM_ACTIVE_MASK 0x0000ffffL
23#endif
24
25#define RWSEM_UNLOCKED_VALUE 0x00000000L
26#define RWSEM_ACTIVE_BIAS 0x00000001L
27#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
28#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
29#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
30
31/*
32 * lock for reading
33 */
34static inline void __down_read(struct rw_semaphore *sem)
35{
36 if (unlikely(atomic_long_inc_return((atomic_long_t *)&sem->count) <= 0))
37 rwsem_down_read_failed(sem);
38}
39
40static inline int __down_read_trylock(struct rw_semaphore *sem)
41{
42 long tmp;
43
44 while ((tmp = sem->count) >= 0) {
45 if (tmp == cmpxchg(&sem->count, tmp,
46 tmp + RWSEM_ACTIVE_READ_BIAS)) {
47 return 1;
48 }
49 }
50 return 0;
51}
52
53/*
54 * lock for writing
55 */
56static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
57{
58 long tmp;
59
60 tmp = atomic_long_add_return(RWSEM_ACTIVE_WRITE_BIAS,
61 (atomic_long_t *)&sem->count);
62 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
63 rwsem_down_write_failed(sem);
64}
65
66static inline void __down_write(struct rw_semaphore *sem)
67{
68 __down_write_nested(sem, 0);
69}
70
71static inline int __down_write_trylock(struct rw_semaphore *sem)
72{
73 long tmp;
74
75 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
76 RWSEM_ACTIVE_WRITE_BIAS);
77 return tmp == RWSEM_UNLOCKED_VALUE;
78}
79
80/*
81 * unlock after reading
82 */
83static inline void __up_read(struct rw_semaphore *sem)
84{
85 long tmp;
86
87 tmp = atomic_long_dec_return((atomic_long_t *)&sem->count);
88 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
89 rwsem_wake(sem);
90}
91
92/*
93 * unlock after writing
94 */
95static inline void __up_write(struct rw_semaphore *sem)
96{
97 if (unlikely(atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_long_t *)&sem->count) < 0))
99 rwsem_wake(sem);
100}
101
102/*
103 * implement atomic add functionality
104 */
105static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
106{
107 atomic_long_add(delta, (atomic_long_t *)&sem->count);
108}
109
110/*
111 * downgrade write lock to read lock
112 */
113static inline void __downgrade_write(struct rw_semaphore *sem)
114{
115 long tmp;
116
117 tmp = atomic_long_add_return(-RWSEM_WAITING_BIAS,
118 (atomic_long_t *)&sem->count);
119 if (tmp < 0)
120 rwsem_downgrade_wake(sem);
121}
122
123/*
124 * implement exchange and add functionality
125 */
126static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
127{
128 return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
129}
130
131#endif /* __KERNEL__ */
132#endif /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index e30a13d1ee7..c377457d1b8 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -193,8 +193,8 @@ extern void cacheable_memzero(void *p, unsigned int nb);
193extern void *cacheable_memcpy(void *, const void *, unsigned int); 193extern void *cacheable_memcpy(void *, const void *, unsigned int);
194extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); 194extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
195extern void bad_page_fault(struct pt_regs *, unsigned long, int); 195extern void bad_page_fault(struct pt_regs *, unsigned long, int);
196extern int die(const char *, struct pt_regs *, long);
197extern void _exception(int, struct pt_regs *, int, unsigned long); 196extern void _exception(int, struct pt_regs *, int, unsigned long);
197extern void die(const char *, struct pt_regs *, long);
198extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 198extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
199 199
200#ifdef CONFIG_BOOKE_WDT 200#ifdef CONFIG_BOOKE_WDT
@@ -221,6 +221,15 @@ extern unsigned long klimit;
221extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); 221extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
222 222
223extern int powersave_nap; /* set if nap mode can be used in idle loop */ 223extern int powersave_nap; /* set if nap mode can be used in idle loop */
224void cpu_idle_wait(void);
225
226#ifdef CONFIG_PSERIES_IDLE
227extern void update_smt_snooze_delay(int snooze);
228extern int pseries_notify_cpuidle_add_cpu(int cpu);
229#else
230static inline void update_smt_snooze_delay(int snooze) {}
231static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
232#endif
224 233
225/* 234/*
226 * Atomic exchange 235 * Atomic exchange
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index f663634cccc..743f36b38e5 100644
--- a/arch/powerpc/include/asm/tce.h
+++ b/arch/powerpc/include/asm/tce.h
@@ -26,10 +26,14 @@
26 26
27/* 27/*
28 * Tces come in two formats, one for the virtual bus and a different 28 * Tces come in two formats, one for the virtual bus and a different
29 * format for PCI 29 * format for PCI. PCI TCEs can have hardware or software maintianed
30 * coherency.
30 */ 31 */
31#define TCE_VB 0 32#define TCE_VB 0
32#define TCE_PCI 1 33#define TCE_PCI 1
34#define TCE_PCI_SWINV_CREATE 2
35#define TCE_PCI_SWINV_FREE 4
36#define TCE_PCI_SWINV_PAIR 8
33 37
34/* TCE page size is 4096 bytes (1 << 12) */ 38/* TCE page size is 4096 bytes (1 << 12) */
35 39
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index fe6f7c2c9c6..7eb10fb96cd 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -219,5 +219,7 @@ DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
219extern void secondary_cpu_time_init(void); 219extern void secondary_cpu_time_init(void);
220extern void iSeries_time_init_early(void); 220extern void iSeries_time_init_early(void);
221 221
222DECLARE_PER_CPU(u64, decrementers_next_tb);
223
222#endif /* __KERNEL__ */ 224#endif /* __KERNEL__ */
223#endif /* __POWERPC_TIME_H */ 225#endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 8947b9827bc..d82e94e6c2b 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -5,8 +5,11 @@
5 * This is here because we used to use l64 for 64bit powerpc 5 * This is here because we used to use l64 for 64bit powerpc
6 * and we don't want to impact user mode with our change to ll64 6 * and we don't want to impact user mode with our change to ll64
7 * in the kernel. 7 * in the kernel.
8 *
9 * However, some user programs are fine with this. They can
10 * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
8 */ 11 */
9#if defined(__powerpc64__) && !defined(__KERNEL__) 12#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
10# include <asm-generic/int-l64.h> 13# include <asm-generic/int-l64.h>
11#else 14#else
12# include <asm-generic/int-ll64.h> 15# include <asm-generic/int-ll64.h>
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index ce4f7f17911..ee728e433aa 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -85,6 +85,8 @@ extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
85extra-$(CONFIG_8xx) := head_8xx.o 85extra-$(CONFIG_8xx) := head_8xx.o
86extra-y += vmlinux.lds 86extra-y += vmlinux.lds
87 87
88obj-$(CONFIG_RELOCATABLE_PPC32) += reloc_32.o
89
88obj-$(CONFIG_PPC32) += entry_32.o setup_32.o 90obj-$(CONFIG_PPC32) += entry_32.o setup_32.o
89obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o 91obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o
90obj-$(CONFIG_KGDB) += kgdb.o 92obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 7c5324f1ec9..04caee7d9bc 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -208,6 +208,7 @@ int main(void)
208 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time)); 208 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
209 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); 209 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
210 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); 210 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
211 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
211#endif /* CONFIG_PPC64 */ 212#endif /* CONFIG_PPC64 */
212 213
213 /* RTAS */ 214 /* RTAS */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818feaa7a..ebc62f42a23 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
41 * core local but doing it always won't hurt 41 * core local but doing it always won't hurt
42 */ 42 */
43 43
44#ifdef CONFIG_PPC_WSP_COPRO 44#ifdef CONFIG_PPC_ICSWX
45 /* Make sure ACOP starts out as zero */ 45 /* Make sure ACOP starts out as zero */
46 li r3,0 46 li r3,0
47 mtspr SPRN_ACOP,r3 47 mtspr SPRN_ACOP,r3
48 48
49 /* Skip the following if we are in Guest mode */
50 mfmsr r3
51 andis. r0,r3,MSR_GS@h
52 bne _icswx_skip_guest
53
49 /* Enable icswx instruction */ 54 /* Enable icswx instruction */
50 mfspr r3,SPRN_A2_CCR2 55 mfspr r3,SPRN_A2_CCR2
51 ori r3,r3,A2_CCR2_ENABLE_ICSWX 56 ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
54 /* Unmask all CTs in HACOP */ 59 /* Unmask all CTs in HACOP */
55 li r3,-1 60 li r3,-1
56 mtspr SPRN_HACOP,r3 61 mtspr SPRN_HACOP,r3
57#endif /* CONFIG_PPC_WSP_COPRO */ 62_icswx_skip_guest:
63#endif /* CONFIG_PPC_ICSWX */
58 64
59 /* Enable doorbell */ 65 /* Enable doorbell */
60 mfspr r3,SPRN_A2_CCR2 66 mfspr r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index edae5bb06f1..81db9e2a8a2 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1505,6 +1505,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
1505 .machine_check = machine_check_4xx, 1505 .machine_check = machine_check_4xx,
1506 .platform = "ppc405", 1506 .platform = "ppc405",
1507 }, 1507 },
1508 { /* APM8018X */
1509 .pvr_mask = 0xffff0000,
1510 .pvr_value = 0x7ff11432,
1511 .cpu_name = "APM8018X",
1512 .cpu_features = CPU_FTRS_40X,
1513 .cpu_user_features = PPC_FEATURE_32 |
1514 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
1515 .mmu_features = MMU_FTR_TYPE_40x,
1516 .icache_bsize = 32,
1517 .dcache_bsize = 32,
1518 .machine_check = machine_check_4xx,
1519 .platform = "ppc405",
1520 },
1508 { /* default match */ 1521 { /* default match */
1509 .pvr_mask = 0x00000000, 1522 .pvr_mask = 0x00000000,
1510 .pvr_value = 0x00000000, 1523 .pvr_value = 0x00000000,
@@ -1830,6 +1843,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
1830 .machine_check = machine_check_47x, 1843 .machine_check = machine_check_47x,
1831 .platform = "ppc470", 1844 .platform = "ppc470",
1832 }, 1845 },
1846 { /* 476fpe */
1847 .pvr_mask = 0xffff0000,
1848 .pvr_value = 0x7ff50000,
1849 .cpu_name = "476fpe",
1850 .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
1851 .cpu_user_features = COMMON_USER_BOOKE |
1852 PPC_FEATURE_HAS_FPU,
1853 .mmu_features = MMU_FTR_TYPE_47x |
1854 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
1855 .icache_bsize = 32,
1856 .dcache_bsize = 128,
1857 .machine_check = machine_check_47x,
1858 .platform = "ppc470",
1859 },
1833 { /* 476 iss */ 1860 { /* 476 iss */
1834 .pvr_mask = 0xffff0000, 1861 .pvr_mask = 0xffff0000,
1835 .pvr_value = 0x00050000, 1862 .pvr_value = 0x00050000,
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index d879809d5c4..28be3452e67 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -10,85 +10,85 @@
10 * 10 *
11 */ 11 */
12 12
13#undef DEBUG
14
15#include <linux/kernel.h> 13#include <linux/kernel.h>
16#include <linux/smp.h> 14#include <linux/smp.h>
17#include <linux/reboot.h> 15#include <linux/reboot.h>
18#include <linux/kexec.h> 16#include <linux/kexec.h>
19#include <linux/bootmem.h>
20#include <linux/export.h> 17#include <linux/export.h>
21#include <linux/crash_dump.h> 18#include <linux/crash_dump.h>
22#include <linux/delay.h> 19#include <linux/delay.h>
23#include <linux/elf.h>
24#include <linux/elfcore.h>
25#include <linux/init.h> 20#include <linux/init.h>
26#include <linux/irq.h> 21#include <linux/irq.h>
27#include <linux/types.h> 22#include <linux/types.h>
28#include <linux/memblock.h>
29 23
30#include <asm/processor.h> 24#include <asm/processor.h>
31#include <asm/machdep.h> 25#include <asm/machdep.h>
32#include <asm/kexec.h> 26#include <asm/kexec.h>
33#include <asm/kdump.h> 27#include <asm/kdump.h>
34#include <asm/prom.h> 28#include <asm/prom.h>
35#include <asm/firmware.h>
36#include <asm/smp.h> 29#include <asm/smp.h>
37#include <asm/system.h> 30#include <asm/system.h>
38#include <asm/setjmp.h> 31#include <asm/setjmp.h>
39 32
40#ifdef DEBUG 33/*
41#include <asm/udbg.h> 34 * The primary CPU waits a while for all secondary CPUs to enter. This is to
42#define DBG(fmt...) udbg_printf(fmt) 35 * avoid sending an IPI if the secondary CPUs are entering
43#else 36 * crash_kexec_secondary on their own (eg via a system reset).
44#define DBG(fmt...) 37 *
45#endif 38 * The secondary timeout has to be longer than the primary. Both timeouts are
39 * in milliseconds.
40 */
41#define PRIMARY_TIMEOUT 500
42#define SECONDARY_TIMEOUT 1000
46 43
47/* This keeps a track of which one is crashing cpu. */ 44#define IPI_TIMEOUT 10000
45#define REAL_MODE_TIMEOUT 10000
46
47/* This keeps a track of which one is the crashing cpu. */
48int crashing_cpu = -1; 48int crashing_cpu = -1;
49static cpumask_t cpus_in_crash = CPU_MASK_NONE; 49static atomic_t cpus_in_crash;
50cpumask_t cpus_in_sr = CPU_MASK_NONE; 50static int time_to_dump;
51 51
52#define CRASH_HANDLER_MAX 3 52#define CRASH_HANDLER_MAX 3
53/* NULL terminated list of shutdown handles */ 53/* NULL terminated list of shutdown handles */
54static crash_shutdown_t crash_shutdown_handles[CRASH_HANDLER_MAX+1]; 54static crash_shutdown_t crash_shutdown_handles[CRASH_HANDLER_MAX+1];
55static DEFINE_SPINLOCK(crash_handlers_lock); 55static DEFINE_SPINLOCK(crash_handlers_lock);
56 56
57static unsigned long crash_shutdown_buf[JMP_BUF_LEN];
58static int crash_shutdown_cpu = -1;
59
60static int handle_fault(struct pt_regs *regs)
61{
62 if (crash_shutdown_cpu == smp_processor_id())
63 longjmp(crash_shutdown_buf, 1);
64 return 0;
65}
66
57#ifdef CONFIG_SMP 67#ifdef CONFIG_SMP
58static atomic_t enter_on_soft_reset = ATOMIC_INIT(0);
59 68
60void crash_ipi_callback(struct pt_regs *regs) 69void crash_ipi_callback(struct pt_regs *regs)
61{ 70{
71 static cpumask_t cpus_state_saved = CPU_MASK_NONE;
72
62 int cpu = smp_processor_id(); 73 int cpu = smp_processor_id();
63 74
64 if (!cpu_online(cpu)) 75 if (!cpu_online(cpu))
65 return; 76 return;
66 77
67 hard_irq_disable(); 78 hard_irq_disable();
68 if (!cpumask_test_cpu(cpu, &cpus_in_crash)) 79 if (!cpumask_test_cpu(cpu, &cpus_state_saved)) {
69 crash_save_cpu(regs, cpu); 80 crash_save_cpu(regs, cpu);
70 cpumask_set_cpu(cpu, &cpus_in_crash); 81 cpumask_set_cpu(cpu, &cpus_state_saved);
71
72 /*
73 * Entered via soft-reset - could be the kdump
74 * process is invoked using soft-reset or user activated
75 * it if some CPU did not respond to an IPI.
76 * For soft-reset, the secondary CPU can enter this func
77 * twice. 1 - using IPI, and 2. soft-reset.
78 * Tell the kexec CPU that entered via soft-reset and ready
79 * to go down.
80 */
81 if (cpumask_test_cpu(cpu, &cpus_in_sr)) {
82 cpumask_clear_cpu(cpu, &cpus_in_sr);
83 atomic_inc(&enter_on_soft_reset);
84 } 82 }
85 83
84 atomic_inc(&cpus_in_crash);
85 smp_mb__after_atomic_inc();
86
86 /* 87 /*
87 * Starting the kdump boot. 88 * Starting the kdump boot.
88 * This barrier is needed to make sure that all CPUs are stopped. 89 * This barrier is needed to make sure that all CPUs are stopped.
89 * If not, soft-reset will be invoked to bring other CPUs.
90 */ 90 */
91 while (!cpumask_test_cpu(crashing_cpu, &cpus_in_crash)) 91 while (!time_to_dump)
92 cpu_relax(); 92 cpu_relax();
93 93
94 if (ppc_md.kexec_cpu_down) 94 if (ppc_md.kexec_cpu_down)
@@ -103,106 +103,99 @@ void crash_ipi_callback(struct pt_regs *regs)
103 /* NOTREACHED */ 103 /* NOTREACHED */
104} 104}
105 105
106/*
107 * Wait until all CPUs are entered via soft-reset.
108 */
109static void crash_soft_reset_check(int cpu)
110{
111 unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
112
113 cpumask_clear_cpu(cpu, &cpus_in_sr);
114 while (atomic_read(&enter_on_soft_reset) != ncpus)
115 cpu_relax();
116}
117
118
119static void crash_kexec_prepare_cpus(int cpu) 106static void crash_kexec_prepare_cpus(int cpu)
120{ 107{
121 unsigned int msecs; 108 unsigned int msecs;
122
123 unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */ 109 unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
110 int tries = 0;
111 int (*old_handler)(struct pt_regs *regs);
112
113 printk(KERN_EMERG "Sending IPI to other CPUs\n");
124 114
125 crash_send_ipi(crash_ipi_callback); 115 crash_send_ipi(crash_ipi_callback);
126 smp_wmb(); 116 smp_wmb();
127 117
118again:
128 /* 119 /*
129 * FIXME: Until we will have the way to stop other CPUs reliably, 120 * FIXME: Until we will have the way to stop other CPUs reliably,
130 * the crash CPU will send an IPI and wait for other CPUs to 121 * the crash CPU will send an IPI and wait for other CPUs to
131 * respond. 122 * respond.
132 * Delay of at least 10 seconds.
133 */ 123 */
134 printk(KERN_EMERG "Sending IPI to other cpus...\n"); 124 msecs = IPI_TIMEOUT;
135 msecs = 10000; 125 while ((atomic_read(&cpus_in_crash) < ncpus) && (--msecs > 0))
136 while ((cpumask_weight(&cpus_in_crash) < ncpus) && (--msecs > 0)) {
137 cpu_relax();
138 mdelay(1); 126 mdelay(1);
139 }
140 127
141 /* Would it be better to replace the trap vector here? */ 128 /* Would it be better to replace the trap vector here? */
142 129
130 if (atomic_read(&cpus_in_crash) >= ncpus) {
131 printk(KERN_EMERG "IPI complete\n");
132 return;
133 }
134
135 printk(KERN_EMERG "ERROR: %d cpu(s) not responding\n",
136 ncpus - atomic_read(&cpus_in_crash));
137
143 /* 138 /*
144 * FIXME: In case if we do not get all CPUs, one possibility: ask the 139 * If we have a panic timeout set then we can't wait indefinitely
145 * user to do soft reset such that we get all. 140 * for someone to activate system reset. We also give up on the
146 * Soft-reset will be used until better mechanism is implemented. 141 * second time through if system reset fail to work.
147 */ 142 */
148 if (cpumask_weight(&cpus_in_crash) < ncpus) { 143 if ((panic_timeout > 0) || (tries > 0))
149 printk(KERN_EMERG "done waiting: %d cpu(s) not responding\n", 144 return;
150 ncpus - cpumask_weight(&cpus_in_crash)); 145
151 printk(KERN_EMERG "Activate soft-reset to stop other cpu(s)\n");
152 cpumask_clear(&cpus_in_sr);
153 atomic_set(&enter_on_soft_reset, 0);
154 while (cpumask_weight(&cpus_in_crash) < ncpus)
155 cpu_relax();
156 }
157 /* 146 /*
158 * Make sure all CPUs are entered via soft-reset if the kdump is 147 * A system reset will cause all CPUs to take an 0x100 exception.
159 * invoked using soft-reset. 148 * The primary CPU returns here via setjmp, and the secondary
149 * CPUs reexecute the crash_kexec_secondary path.
160 */ 150 */
161 if (cpumask_test_cpu(cpu, &cpus_in_sr)) 151 old_handler = __debugger;
162 crash_soft_reset_check(cpu); 152 __debugger = handle_fault;
163 /* Leave the IPI callback set */ 153 crash_shutdown_cpu = smp_processor_id();
154
155 if (setjmp(crash_shutdown_buf) == 0) {
156 printk(KERN_EMERG "Activate system reset (dumprestart) "
157 "to stop other cpu(s)\n");
158
159 /*
160 * A system reset will force all CPUs to execute the
161 * crash code again. We need to reset cpus_in_crash so we
162 * wait for everyone to do this.
163 */
164 atomic_set(&cpus_in_crash, 0);
165 smp_mb();
166
167 while (atomic_read(&cpus_in_crash) < ncpus)
168 cpu_relax();
169 }
170
171 crash_shutdown_cpu = -1;
172 __debugger = old_handler;
173
174 tries++;
175 goto again;
164} 176}
165 177
166/* 178/*
167 * This function will be called by secondary cpus or by kexec cpu 179 * This function will be called by secondary cpus.
168 * if soft-reset is activated to stop some CPUs.
169 */ 180 */
170void crash_kexec_secondary(struct pt_regs *regs) 181void crash_kexec_secondary(struct pt_regs *regs)
171{ 182{
172 int cpu = smp_processor_id();
173 unsigned long flags; 183 unsigned long flags;
174 int msecs = 5; 184 int msecs = SECONDARY_TIMEOUT;
175 185
176 local_irq_save(flags); 186 local_irq_save(flags);
177 /* Wait 5ms if the kexec CPU is not entered yet. */ 187
188 /* Wait for the primary crash CPU to signal its progress */
178 while (crashing_cpu < 0) { 189 while (crashing_cpu < 0) {
179 if (--msecs < 0) { 190 if (--msecs < 0) {
180 /* 191 /* No response, kdump image may not have been loaded */
181 * Either kdump image is not loaded or
182 * kdump process is not started - Probably xmon
183 * exited using 'x'(exit and recover) or
184 * kexec_should_crash() failed for all running tasks.
185 */
186 cpumask_clear_cpu(cpu, &cpus_in_sr);
187 local_irq_restore(flags); 192 local_irq_restore(flags);
188 return; 193 return;
189 } 194 }
195
190 mdelay(1); 196 mdelay(1);
191 cpu_relax();
192 }
193 if (cpu == crashing_cpu) {
194 /*
195 * Panic CPU will enter this func only via soft-reset.
196 * Wait until all secondary CPUs entered and
197 * then start kexec boot.
198 */
199 crash_soft_reset_check(cpu);
200 cpumask_set_cpu(crashing_cpu, &cpus_in_crash);
201 if (ppc_md.kexec_cpu_down)
202 ppc_md.kexec_cpu_down(1, 0);
203 machine_kexec(kexec_crash_image);
204 /* NOTREACHED */
205 } 197 }
198
206 crash_ipi_callback(regs); 199 crash_ipi_callback(regs);
207} 200}
208 201
@@ -211,7 +204,7 @@ void crash_kexec_secondary(struct pt_regs *regs)
211static void crash_kexec_prepare_cpus(int cpu) 204static void crash_kexec_prepare_cpus(int cpu)
212{ 205{
213 /* 206 /*
214 * move the secondarys to us so that we can copy 207 * move the secondaries to us so that we can copy
215 * the new kernel 0-0x100 safely 208 * the new kernel 0-0x100 safely
216 * 209 *
217 * do this if kexec in setup.c ? 210 * do this if kexec in setup.c ?
@@ -225,7 +218,6 @@ static void crash_kexec_prepare_cpus(int cpu)
225 218
226void crash_kexec_secondary(struct pt_regs *regs) 219void crash_kexec_secondary(struct pt_regs *regs)
227{ 220{
228 cpumask_clear(&cpus_in_sr);
229} 221}
230#endif /* CONFIG_SMP */ 222#endif /* CONFIG_SMP */
231 223
@@ -236,7 +228,7 @@ static void crash_kexec_wait_realmode(int cpu)
236 unsigned int msecs; 228 unsigned int msecs;
237 int i; 229 int i;
238 230
239 msecs = 10000; 231 msecs = REAL_MODE_TIMEOUT;
240 for (i=0; i < nr_cpu_ids && msecs > 0; i++) { 232 for (i=0; i < nr_cpu_ids && msecs > 0; i++) {
241 if (i == cpu) 233 if (i == cpu)
242 continue; 234 continue;
@@ -308,22 +300,11 @@ int crash_shutdown_unregister(crash_shutdown_t handler)
308} 300}
309EXPORT_SYMBOL(crash_shutdown_unregister); 301EXPORT_SYMBOL(crash_shutdown_unregister);
310 302
311static unsigned long crash_shutdown_buf[JMP_BUF_LEN];
312static int crash_shutdown_cpu = -1;
313
314static int handle_fault(struct pt_regs *regs)
315{
316 if (crash_shutdown_cpu == smp_processor_id())
317 longjmp(crash_shutdown_buf, 1);
318 return 0;
319}
320
321void default_machine_crash_shutdown(struct pt_regs *regs) 303void default_machine_crash_shutdown(struct pt_regs *regs)
322{ 304{
323 unsigned int i; 305 unsigned int i;
324 int (*old_handler)(struct pt_regs *regs); 306 int (*old_handler)(struct pt_regs *regs);
325 307
326
327 /* 308 /*
328 * This function is only called after the system 309 * This function is only called after the system
329 * has panicked or is otherwise in a critical state. 310 * has panicked or is otherwise in a critical state.
@@ -341,15 +322,26 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
341 * such that another IPI will not be sent. 322 * such that another IPI will not be sent.
342 */ 323 */
343 crashing_cpu = smp_processor_id(); 324 crashing_cpu = smp_processor_id();
344 crash_save_cpu(regs, crashing_cpu); 325
326 /*
327 * If we came in via system reset, wait a while for the secondary
328 * CPUs to enter.
329 */
330 if (TRAP(regs) == 0x100)
331 mdelay(PRIMARY_TIMEOUT);
332
345 crash_kexec_prepare_cpus(crashing_cpu); 333 crash_kexec_prepare_cpus(crashing_cpu);
346 cpumask_set_cpu(crashing_cpu, &cpus_in_crash); 334
335 crash_save_cpu(regs, crashing_cpu);
336
337 time_to_dump = 1;
338
347 crash_kexec_wait_realmode(crashing_cpu); 339 crash_kexec_wait_realmode(crashing_cpu);
348 340
349 machine_kexec_mask_interrupts(); 341 machine_kexec_mask_interrupts();
350 342
351 /* 343 /*
352 * Call registered shutdown routines savely. Swap out 344 * Call registered shutdown routines safely. Swap out
353 * __debugger_fault_handler, and replace on exit. 345 * __debugger_fault_handler, and replace on exit.
354 */ 346 */
355 old_handler = __debugger_fault_handler; 347 old_handler = __debugger_fault_handler;
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 424afb6b8fb..b3ba5163eae 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -28,7 +28,7 @@
28#define DBG(fmt...) 28#define DBG(fmt...)
29#endif 29#endif
30 30
31#ifndef CONFIG_RELOCATABLE 31#ifndef CONFIG_NONSTATIC_KERNEL
32void __init reserve_kdump_trampoline(void) 32void __init reserve_kdump_trampoline(void)
33{ 33{
34 memblock_reserve(0, KDUMP_RESERVE_LIMIT); 34 memblock_reserve(0, KDUMP_RESERVE_LIMIT);
@@ -67,7 +67,7 @@ void __init setup_kdump_trampoline(void)
67 67
68 DBG(" <- setup_kdump_trampoline()\n"); 68 DBG(" <- setup_kdump_trampoline()\n");
69} 69}
70#endif /* CONFIG_RELOCATABLE */ 70#endif /* CONFIG_NONSTATIC_KERNEL */
71 71
72static int __init parse_savemaxmem(char *p) 72static int __init parse_savemaxmem(char *p)
73{ 73{
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index cf9c69b9189..d4be7bb3dbd 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -65,7 +65,7 @@ BEGIN_FTR_SECTION
65 lbz r0,PACAPROCSTART(r13) 65 lbz r0,PACAPROCSTART(r13)
66 cmpwi r0,0x80 66 cmpwi r0,0x80
67 bne 1f 67 bne 1f
68 li r0,0 68 li r0,1
69 stb r0,PACAPROCSTART(r13) 69 stb r0,PACAPROCSTART(r13)
70 b kvm_start_guest 70 b kvm_start_guest
711: 711:
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index b725dab0f88..7dd2981bcc5 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -64,6 +64,35 @@ _ENTRY(_start);
64 mr r31,r3 /* save device tree ptr */ 64 mr r31,r3 /* save device tree ptr */
65 li r24,0 /* CPU number */ 65 li r24,0 /* CPU number */
66 66
67#ifdef CONFIG_RELOCATABLE
68/*
69 * Relocate ourselves to the current runtime address.
70 * This is called only by the Boot CPU.
71 * "relocate" is called with our current runtime virutal
72 * address.
73 * r21 will be loaded with the physical runtime address of _stext
74 */
75 bl 0f /* Get our runtime address */
760: mflr r21 /* Make it accessible */
77 addis r21,r21,(_stext - 0b)@ha
78 addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */
79
80 /*
81 * We have the runtime (virutal) address of our base.
82 * We calculate our shift of offset from a 256M page.
83 * We could map the 256M page we belong to at PAGE_OFFSET and
84 * get going from there.
85 */
86 lis r4,KERNELBASE@h
87 ori r4,r4,KERNELBASE@l
88 rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */
89 rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */
90 subf r3,r5,r6 /* r3 = r6 - r5 */
91 add r3,r4,r3 /* Required Virutal Address */
92
93 bl relocate
94#endif
95
67 bl init_cpu_state 96 bl init_cpu_state
68 97
69 /* 98 /*
@@ -88,6 +117,65 @@ _ENTRY(_start);
88 117
89#ifdef CONFIG_RELOCATABLE 118#ifdef CONFIG_RELOCATABLE
90 /* 119 /*
120 * Relocatable kernel support based on processing of dynamic
121 * relocation entries.
122 *
123 * r25 will contain RPN/ERPN for the start address of memory
124 * r21 will contain the current offset of _stext
125 */
126 lis r3,kernstart_addr@ha
127 la r3,kernstart_addr@l(r3)
128
129 /*
130 * Compute the kernstart_addr.
131 * kernstart_addr => (r6,r8)
132 * kernstart_addr & ~0xfffffff => (r6,r7)
133 */
134 rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */
135 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
136 rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */
137 or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */
138
139 /* Store kernstart_addr */
140 stw r6,0(r3) /* higher 32bit */
141 stw r8,4(r3) /* lower 32bit */
142
143 /*
144 * Compute the virt_phys_offset :
145 * virt_phys_offset = stext.run - kernstart_addr
146 *
147 * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff)
148 * When we relocate, we have :
149 *
150 * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff)
151 *
152 * hence:
153 * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
154 *
155 */
156
157 /* KERNELBASE&~0xfffffff => (r4,r5) */
158 li r4, 0 /* higer 32bit */
159 lis r5,KERNELBASE@h
160 rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */
161
162 /*
163 * 64bit subtraction.
164 */
165 subfc r5,r7,r5
166 subfe r4,r6,r4
167
168 /* Store virt_phys_offset */
169 lis r3,virt_phys_offset@ha
170 la r3,virt_phys_offset@l(r3)
171
172 stw r4,0(r3)
173 stw r5,4(r3)
174
175#elif defined(CONFIG_DYNAMIC_MEMSTART)
176 /*
177 * Mapping based, page aligned dynamic kernel loading.
178 *
91 * r25 will contain RPN/ERPN for the start address of memory 179 * r25 will contain RPN/ERPN for the start address of memory
92 * 180 *
93 * Add the difference between KERNELBASE and PAGE_OFFSET to the 181 * Add the difference between KERNELBASE and PAGE_OFFSET to the
@@ -732,6 +820,8 @@ _GLOBAL(init_cpu_state)
732 /* We use the PVR to differenciate 44x cores from 476 */ 820 /* We use the PVR to differenciate 44x cores from 476 */
733 mfspr r3,SPRN_PVR 821 mfspr r3,SPRN_PVR
734 srwi r3,r3,16 822 srwi r3,r3,16
823 cmplwi cr0,r3,PVR_476FPE@h
824 beq head_start_47x
735 cmplwi cr0,r3,PVR_476@h 825 cmplwi cr0,r3,PVR_476@h
736 beq head_start_47x 826 beq head_start_47x
737 cmplwi cr0,r3,PVR_476_ISS@h 827 cmplwi cr0,r3,PVR_476_ISS@h
@@ -800,12 +890,29 @@ skpinv: addi r4,r4,1 /* Increment */
800/* 890/*
801 * Configure and load pinned entry into TLB slot 63. 891 * Configure and load pinned entry into TLB slot 63.
802 */ 892 */
893#ifdef CONFIG_NONSTATIC_KERNEL
894 /*
895 * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT
896 * entries of the initial mapping set by the boot loader.
897 * The XLAT entry is stored in r25
898 */
899
900 /* Read the XLAT entry for our current mapping */
901 tlbre r25,r23,PPC44x_TLB_XLAT
902
903 lis r3,KERNELBASE@h
904 ori r3,r3,KERNELBASE@l
905
906 /* Use our current RPN entry */
907 mr r4,r25
908#else
803 909
804 lis r3,PAGE_OFFSET@h 910 lis r3,PAGE_OFFSET@h
805 ori r3,r3,PAGE_OFFSET@l 911 ori r3,r3,PAGE_OFFSET@l
806 912
807 /* Kernel is at the base of RAM */ 913 /* Kernel is at the base of RAM */
808 li r4, 0 /* Load the kernel physical address */ 914 li r4, 0 /* Load the kernel physical address */
915#endif
809 916
810 /* Load the kernel PID = 0 */ 917 /* Load the kernel PID = 0 */
811 li r0,0 918 li r0,0
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 9f5d210ddf3..d5d78c4ceef 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -197,7 +197,7 @@ _ENTRY(__early_start)
197 197
198 bl early_init 198 bl early_init
199 199
200#ifdef CONFIG_RELOCATABLE 200#ifdef CONFIG_DYNAMIC_MEMSTART
201 lis r3,kernstart_addr@ha 201 lis r3,kernstart_addr@ha
202 la r3,kernstart_addr@l(r3) 202 la r3,kernstart_addr@l(r3)
203#ifdef CONFIG_PHYS_64BIT 203#ifdef CONFIG_PHYS_64BIT
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 9c3cd490b1b..7c66ce13da8 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -39,9 +39,13 @@
39#define cpu_should_die() 0 39#define cpu_should_die() 0
40#endif 40#endif
41 41
42unsigned long cpuidle_disable = IDLE_NO_OVERRIDE;
43EXPORT_SYMBOL(cpuidle_disable);
44
42static int __init powersave_off(char *arg) 45static int __init powersave_off(char *arg)
43{ 46{
44 ppc_md.power_save = NULL; 47 ppc_md.power_save = NULL;
48 cpuidle_disable = IDLE_POWERSAVE_OFF;
45 return 0; 49 return 0;
46} 50}
47__setup("powersave=off", powersave_off); 51__setup("powersave=off", powersave_off);
@@ -113,6 +117,29 @@ void cpu_idle(void)
113 } 117 }
114} 118}
115 119
120
121/*
122 * cpu_idle_wait - Used to ensure that all the CPUs come out of the old
123 * idle loop and start using the new idle loop.
124 * Required while changing idle handler on SMP systems.
125 * Caller must have changed idle handler to the new value before the call.
126 * This window may be larger on shared systems.
127 */
128void cpu_idle_wait(void)
129{
130 int cpu;
131 smp_mb();
132
133 /* kick all the CPUs so that they exit out of old idle routine */
134 get_online_cpus();
135 for_each_online_cpu(cpu) {
136 if (cpu != smp_processor_id())
137 smp_send_reschedule(cpu);
138 }
139 put_online_cpus();
140}
141EXPORT_SYMBOL_GPL(cpu_idle_wait);
142
116int powersave_nap; 143int powersave_nap;
117 144
118#ifdef CONFIG_SYSCTL 145#ifdef CONFIG_SYSCTL
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 3a70845a51c..fcdff198da4 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -54,6 +54,7 @@ _GLOBAL(power7_idle)
54 li r0,0 54 li r0,0
55 stb r0,PACASOFTIRQEN(r13) /* we'll hard-enable shortly */ 55 stb r0,PACASOFTIRQEN(r13) /* we'll hard-enable shortly */
56 stb r0,PACAHARDIRQEN(r13) 56 stb r0,PACAHARDIRQEN(r13)
57 stb r0,PACA_NAPSTATELOST(r13)
57 58
58 /* Continue saving state */ 59 /* Continue saving state */
59 SAVE_GPR(2, r1) 60 SAVE_GPR(2, r1)
@@ -86,6 +87,9 @@ _GLOBAL(power7_wakeup_loss)
86 rfid 87 rfid
87 88
88_GLOBAL(power7_wakeup_noloss) 89_GLOBAL(power7_wakeup_noloss)
90 lbz r0,PACA_NAPSTATELOST(r13)
91 cmpwi r0,0
92 bne .power7_wakeup_loss
89 ld r1,PACAR1(r13) 93 ld r1,PACAR1(r13)
90 ld r4,_MSR(r1) 94 ld r4,_MSR(r1)
91 ld r5,_NIP(r1) 95 ld r5,_NIP(r1)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5c3c46948d9..701d4aceb4f 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -115,6 +115,15 @@ static inline notrace void set_soft_enabled(unsigned long enable)
115 : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); 115 : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
116} 116}
117 117
118static inline notrace void decrementer_check_overflow(void)
119{
120 u64 now = get_tb_or_rtc();
121 u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
122
123 if (now >= *next_tb)
124 set_dec(1);
125}
126
118notrace void arch_local_irq_restore(unsigned long en) 127notrace void arch_local_irq_restore(unsigned long en)
119{ 128{
120 /* 129 /*
@@ -164,24 +173,21 @@ notrace void arch_local_irq_restore(unsigned long en)
164 */ 173 */
165 local_paca->hard_enabled = en; 174 local_paca->hard_enabled = en;
166 175
167#ifndef CONFIG_BOOKE 176 /*
168 /* On server, re-trigger the decrementer if it went negative since 177 * Trigger the decrementer if we have a pending event. Some processors
169 * some processors only trigger on edge transitions of the sign bit. 178 * only trigger on edge transitions of the sign bit. We might also
170 * 179 * have disabled interrupts long enough that the decrementer wrapped
171 * BookE has a level sensitive decrementer (latches in TSR) so we 180 * to positive.
172 * don't need that
173 */ 181 */
174 if ((int)mfspr(SPRN_DEC) < 0) 182 decrementer_check_overflow();
175 mtspr(SPRN_DEC, 1);
176#endif /* CONFIG_BOOKE */
177 183
178 /* 184 /*
179 * Force the delivery of pending soft-disabled interrupts on PS3. 185 * Force the delivery of pending soft-disabled interrupts on PS3.
180 * Any HV call will have this side effect. 186 * Any HV call will have this side effect.
181 */ 187 */
182 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { 188 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
183 u64 tmp; 189 u64 tmp, tmp2;
184 lv1_get_version_info(&tmp); 190 lv1_get_version_info(&tmp, &tmp2);
185 } 191 }
186 192
187 __hard_irq_enable(); 193 __hard_irq_enable();
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index a2158a395d9..c957b1202bd 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -125,7 +125,7 @@ void __init reserve_crashkernel(void)
125 125
126 crash_size = resource_size(&crashk_res); 126 crash_size = resource_size(&crashk_res);
127 127
128#ifndef CONFIG_RELOCATABLE 128#ifndef CONFIG_NONSTATIC_KERNEL
129 if (crashk_res.start != KDUMP_KERNELBASE) 129 if (crashk_res.start != KDUMP_KERNELBASE)
130 printk("Crash kernel location must be 0x%x\n", 130 printk("Crash kernel location must be 0x%x\n",
131 KDUMP_KERNELBASE); 131 KDUMP_KERNELBASE);
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 458ed3bee66..fa4a573d671 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -214,7 +214,7 @@ char __devinit *pcibios_setup(char *str)
214 * If the interrupt is used, then gets the interrupt line from the 214 * If the interrupt is used, then gets the interrupt line from the
215 * openfirmware and sets it in the pci_dev and pci_config line. 215 * openfirmware and sets it in the pci_dev and pci_config line.
216 */ 216 */
217int pci_read_irq_line(struct pci_dev *pci_dev) 217static int pci_read_irq_line(struct pci_dev *pci_dev)
218{ 218{
219 struct of_irq oirq; 219 struct of_irq oirq;
220 unsigned int virq; 220 unsigned int virq;
@@ -283,7 +283,6 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
283 283
284 return 0; 284 return 0;
285} 285}
286EXPORT_SYMBOL(pci_read_irq_line);
287 286
288/* 287/*
289 * Platform support for /proc/bus/pci/X/Y mmap()s, 288 * Platform support for /proc/bus/pci/X/Y mmap()s,
@@ -921,18 +920,22 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
921 struct resource *res = dev->resource + i; 920 struct resource *res = dev->resource + i;
922 if (!res->flags) 921 if (!res->flags)
923 continue; 922 continue;
924 /* On platforms that have PCI_PROBE_ONLY set, we don't 923
925 * consider 0 as an unassigned BAR value. It's technically 924 /* If we're going to re-assign everything, we mark all resources
926 * a valid value, but linux doesn't like it... so when we can 925 * as unset (and 0-base them). In addition, we mark BARs starting
927 * re-assign things, we do so, but if we can't, we keep it 926 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
928 * around and hope for the best... 927 * since in that case, we don't want to re-assign anything
929 */ 928 */
930 if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) { 929 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
931 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 930 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
932 pci_name(dev), i, 931 /* Only print message if not re-assigning */
933 (unsigned long long)res->start, 932 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
934 (unsigned long long)res->end, 933 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
935 (unsigned int)res->flags); 934 "is unassigned\n",
935 pci_name(dev), i,
936 (unsigned long long)res->start,
937 (unsigned long long)res->end,
938 (unsigned int)res->flags);
936 res->end -= res->start; 939 res->end -= res->start;
937 res->start = 0; 940 res->start = 0;
938 res->flags |= IORESOURCE_UNSET; 941 res->flags |= IORESOURCE_UNSET;
@@ -1042,6 +1045,16 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1042 if (i >= 3 && bus->self->transparent) 1045 if (i >= 3 && bus->self->transparent)
1043 continue; 1046 continue;
1044 1047
1048 /* If we are going to re-assign everything, mark the resource
1049 * as unset and move it down to 0
1050 */
1051 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1052 res->flags |= IORESOURCE_UNSET;
1053 res->end -= res->start;
1054 res->start = 0;
1055 continue;
1056 }
1057
1045 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", 1058 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1046 pci_name(dev), i, 1059 pci_name(dev), i,
1047 (unsigned long long)res->start,\ 1060 (unsigned long long)res->start,\
@@ -1262,18 +1275,15 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
1262 pci_bus_for_each_resource(bus, res, i) { 1275 pci_bus_for_each_resource(bus, res, i) {
1263 if (!res || !res->flags || res->start > res->end || res->parent) 1276 if (!res || !res->flags || res->start > res->end || res->parent)
1264 continue; 1277 continue;
1278
1279 /* If the resource was left unset at this point, we clear it */
1280 if (res->flags & IORESOURCE_UNSET)
1281 goto clear_resource;
1282
1265 if (bus->parent == NULL) 1283 if (bus->parent == NULL)
1266 pr = (res->flags & IORESOURCE_IO) ? 1284 pr = (res->flags & IORESOURCE_IO) ?
1267 &ioport_resource : &iomem_resource; 1285 &ioport_resource : &iomem_resource;
1268 else { 1286 else {
1269 /* Don't bother with non-root busses when
1270 * re-assigning all resources. We clear the
1271 * resource flags as if they were colliding
1272 * and as such ensure proper re-allocation
1273 * later.
1274 */
1275 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC))
1276 goto clear_resource;
1277 pr = pci_find_parent_resource(bus->self, res); 1287 pr = pci_find_parent_resource(bus->self, res);
1278 if (pr == res) { 1288 if (pr == res) {
1279 /* this happens when the generic PCI 1289 /* this happens when the generic PCI
@@ -1304,9 +1314,9 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
1304 if (reparent_resources(pr, res) == 0) 1314 if (reparent_resources(pr, res) == 0)
1305 continue; 1315 continue;
1306 } 1316 }
1307 printk(KERN_WARNING "PCI: Cannot allocate resource region " 1317 pr_warning("PCI: Cannot allocate resource region "
1308 "%d of PCI bridge %d, will remap\n", i, bus->number); 1318 "%d of PCI bridge %d, will remap\n", i, bus->number);
1309clear_resource: 1319 clear_resource:
1310 res->start = res->end = 0; 1320 res->start = res->end = 0;
1311 res->flags = 0; 1321 res->flags = 0;
1312 } 1322 }
@@ -1451,16 +1461,11 @@ void __init pcibios_resource_survey(void)
1451{ 1461{
1452 struct pci_bus *b; 1462 struct pci_bus *b;
1453 1463
1454 /* Allocate and assign resources. If we re-assign everything, then 1464 /* Allocate and assign resources */
1455 * we skip the allocate phase
1456 */
1457 list_for_each_entry(b, &pci_root_buses, node) 1465 list_for_each_entry(b, &pci_root_buses, node)
1458 pcibios_allocate_bus_resources(b); 1466 pcibios_allocate_bus_resources(b);
1459 1467 pcibios_allocate_resources(0);
1460 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1468 pcibios_allocate_resources(1);
1461 pcibios_allocate_resources(0);
1462 pcibios_allocate_resources(1);
1463 }
1464 1469
1465 /* Before we start assigning unassigned resource, we try to reserve 1470 /* Before we start assigning unassigned resource, we try to reserve
1466 * the low IO area and the VGA memory area if they intersect the 1471 * the low IO area and the VGA memory area if they intersect the
@@ -1732,6 +1737,12 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1732 if (mode == PCI_PROBE_NORMAL) 1737 if (mode == PCI_PROBE_NORMAL)
1733 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1738 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1734 1739
1740 /* Platform gets a chance to do some global fixups before
1741 * we proceed to resource allocation
1742 */
1743 if (ppc_md.pcibios_fixup_phb)
1744 ppc_md.pcibios_fixup_phb(hose);
1745
1735 /* Configure PCI Express settings */ 1746 /* Configure PCI Express settings */
1736 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1747 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1737 struct pci_bus *child; 1748 struct pci_bus *child;
@@ -1747,10 +1758,13 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1747static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1758static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1748{ 1759{
1749 int i, class = dev->class >> 8; 1760 int i, class = dev->class >> 8;
1761 /* When configured as agent, programing interface = 1 */
1762 int prog_if = dev->class & 0xf;
1750 1763
1751 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1764 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1752 class == PCI_CLASS_BRIDGE_OTHER) && 1765 class == PCI_CLASS_BRIDGE_OTHER) &&
1753 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1766 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1767 (prog_if == 0) &&
1754 (dev->bus->parent == NULL)) { 1768 (dev->bus->parent == NULL)) {
1755 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1769 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1756 dev->resource[i].start = 0; 1770 dev->resource[i].start = 0;
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 4e69deb89b3..dd9e4a04bf7 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -50,6 +50,9 @@ void * __devinit update_dn_pci_info(struct device_node *dn, void *data)
50 dn->data = pdn; 50 dn->data = pdn;
51 pdn->node = dn; 51 pdn->node = dn;
52 pdn->phb = phb; 52 pdn->phb = phb;
53#ifdef CONFIG_PPC_POWERNV
54 pdn->pe_number = IODA_INVALID_PE;
55#endif
53 regs = of_get_property(dn, "reg", NULL); 56 regs = of_get_property(dn, "reg", NULL);
54 if (regs) { 57 if (regs) {
55 /* First register entry is addr (00BBSS00) */ 58 /* First register entry is addr (00BBSS00) */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 6457574c0b2..ebe5766781a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -584,16 +584,32 @@ static struct regbit {
584 unsigned long bit; 584 unsigned long bit;
585 const char *name; 585 const char *name;
586} msr_bits[] = { 586} msr_bits[] = {
587#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
588 {MSR_SF, "SF"},
589 {MSR_HV, "HV"},
590#endif
591 {MSR_VEC, "VEC"},
592 {MSR_VSX, "VSX"},
593#ifdef CONFIG_BOOKE
594 {MSR_CE, "CE"},
595#endif
587 {MSR_EE, "EE"}, 596 {MSR_EE, "EE"},
588 {MSR_PR, "PR"}, 597 {MSR_PR, "PR"},
589 {MSR_FP, "FP"}, 598 {MSR_FP, "FP"},
590 {MSR_VEC, "VEC"},
591 {MSR_VSX, "VSX"},
592 {MSR_ME, "ME"}, 599 {MSR_ME, "ME"},
593 {MSR_CE, "CE"}, 600#ifdef CONFIG_BOOKE
594 {MSR_DE, "DE"}, 601 {MSR_DE, "DE"},
602#else
603 {MSR_SE, "SE"},
604 {MSR_BE, "BE"},
605#endif
595 {MSR_IR, "IR"}, 606 {MSR_IR, "IR"},
596 {MSR_DR, "DR"}, 607 {MSR_DR, "DR"},
608 {MSR_PMM, "PMM"},
609#ifndef CONFIG_BOOKE
610 {MSR_RI, "RI"},
611 {MSR_LE, "LE"},
612#endif
597 {0, NULL} 613 {0, NULL}
598}; 614};
599 615
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index cc584865b3d..eca626ea3f2 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -742,7 +742,7 @@ static unsigned char ibm_architecture_vec[] = {
742 W(0xffffffff), /* virt_base */ 742 W(0xffffffff), /* virt_base */
743 W(0xffffffff), /* virt_size */ 743 W(0xffffffff), /* virt_size */
744 W(0xffffffff), /* load_base */ 744 W(0xffffffff), /* load_base */
745 W(64), /* 64MB min RMA */ 745 W(256), /* 256MB min RMA */
746 W(0xffffffff), /* full client load */ 746 W(0xffffffff), /* full client load */
747 0, /* min RMA percentage of total RAM */ 747 0, /* min RMA percentage of total RAM */
748 48, /* max log_2(hash table size) */ 748 48, /* max log_2(hash table size) */
@@ -1224,14 +1224,6 @@ static void __init prom_init_mem(void)
1224 1224
1225 RELOC(alloc_bottom) = PAGE_ALIGN((unsigned long)&RELOC(_end) + 0x4000); 1225 RELOC(alloc_bottom) = PAGE_ALIGN((unsigned long)&RELOC(_end) + 0x4000);
1226 1226
1227 /* Check if we have an initrd after the kernel, if we do move our bottom
1228 * point to after it
1229 */
1230 if (RELOC(prom_initrd_start)) {
1231 if (RELOC(prom_initrd_end) > RELOC(alloc_bottom))
1232 RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(prom_initrd_end));
1233 }
1234
1235 /* 1227 /*
1236 * If prom_memory_limit is set we reduce the upper limits *except* for 1228 * If prom_memory_limit is set we reduce the upper limits *except* for
1237 * alloc_top_high. This must be the real top of RAM so we can put 1229 * alloc_top_high. This must be the real top of RAM so we can put
@@ -1269,6 +1261,15 @@ static void __init prom_init_mem(void)
1269 RELOC(alloc_top) = RELOC(rmo_top); 1261 RELOC(alloc_top) = RELOC(rmo_top);
1270 RELOC(alloc_top_high) = RELOC(ram_top); 1262 RELOC(alloc_top_high) = RELOC(ram_top);
1271 1263
1264 /*
1265 * Check if we have an initrd after the kernel but still inside
1266 * the RMO. If we do move our bottom point to after it.
1267 */
1268 if (RELOC(prom_initrd_start) &&
1269 RELOC(prom_initrd_start) < RELOC(rmo_top) &&
1270 RELOC(prom_initrd_end) > RELOC(alloc_bottom))
1271 RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(prom_initrd_end));
1272
1272 prom_printf("memory layout at init:\n"); 1273 prom_printf("memory layout at init:\n");
1273 prom_printf(" memory_limit : %x (16 MB aligned)\n", RELOC(prom_memory_limit)); 1274 prom_printf(" memory_limit : %x (16 MB aligned)\n", RELOC(prom_memory_limit));
1274 prom_printf(" alloc_bottom : %x\n", RELOC(alloc_bottom)); 1275 prom_printf(" alloc_bottom : %x\n", RELOC(alloc_bottom));
@@ -2079,7 +2080,7 @@ static void __init prom_check_displays(void)
2079 /* Setup a usable color table when the appropriate 2080 /* Setup a usable color table when the appropriate
2080 * method is available. Should update this to set-colors */ 2081 * method is available. Should update this to set-colors */
2081 clut = RELOC(default_colors); 2082 clut = RELOC(default_colors);
2082 for (i = 0; i < 32; i++, clut += 3) 2083 for (i = 0; i < 16; i++, clut += 3)
2083 if (prom_set_color(ih, i, clut[0], clut[1], 2084 if (prom_set_color(ih, i, clut[0], clut[1],
2084 clut[2]) != 0) 2085 clut[2]) != 0)
2085 break; 2086 break;
@@ -2844,7 +2845,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
2844 RELOC(of_platform) = prom_find_machine_type(); 2845 RELOC(of_platform) = prom_find_machine_type();
2845 prom_printf("Detected machine type: %x\n", RELOC(of_platform)); 2846 prom_printf("Detected machine type: %x\n", RELOC(of_platform));
2846 2847
2847#ifndef CONFIG_RELOCATABLE 2848#ifndef CONFIG_NONSTATIC_KERNEL
2848 /* Bail if this is a kdump kernel. */ 2849 /* Bail if this is a kdump kernel. */
2849 if (PHYSICAL_START > 0) 2850 if (PHYSICAL_START > 0)
2850 prom_panic("Error: You can't boot a kdump kernel from OF!\n"); 2851 prom_panic("Error: You can't boot a kdump kernel from OF!\n");
@@ -2969,9 +2970,11 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
2969 /* 2970 /*
2970 * in case stdin is USB and still active on IBM machines... 2971 * in case stdin is USB and still active on IBM machines...
2971 * Unfortunately quiesce crashes on some powermacs if we have 2972 * Unfortunately quiesce crashes on some powermacs if we have
2972 * closed stdin already (in particular the powerbook 101). 2973 * closed stdin already (in particular the powerbook 101). It
2974 * appears that the OPAL version of OFW doesn't like it either.
2973 */ 2975 */
2974 if (RELOC(of_platform) != PLATFORM_POWERMAC) 2976 if (RELOC(of_platform) != PLATFORM_POWERMAC &&
2977 RELOC(of_platform) != PLATFORM_OPAL)
2975 prom_close_stdin(); 2978 prom_close_stdin();
2976 2979
2977 /* 2980 /*
@@ -2987,8 +2990,12 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
2987 * is common to us and kexec 2990 * is common to us and kexec
2988 */ 2991 */
2989 hdr = RELOC(dt_header_start); 2992 hdr = RELOC(dt_header_start);
2990 prom_printf("returning from prom_init\n"); 2993
2991 prom_debug("->dt_header_start=0x%x\n", hdr); 2994 /* Don't print anything after quiesce under OPAL, it crashes OFW */
2995 if (RELOC(of_platform) != PLATFORM_OPAL) {
2996 prom_printf("returning from prom_init\n");
2997 prom_debug("->dt_header_start=0x%x\n", hdr);
2998 }
2992 2999
2993#ifdef CONFIG_PPC32 3000#ifdef CONFIG_PPC32
2994 reloc_got2(-offset); 3001 reloc_got2(-offset);
diff --git a/arch/powerpc/kernel/reloc_32.S b/arch/powerpc/kernel/reloc_32.S
new file mode 100644
index 00000000000..ef46ba6e094
--- /dev/null
+++ b/arch/powerpc/kernel/reloc_32.S
@@ -0,0 +1,208 @@
1/*
2 * Code to process dynamic relocations for PPC32.
3 *
4 * Copyrights (C) IBM Corporation, 2011.
5 * Author: Suzuki Poulose <suzuki@in.ibm.com>
6 *
7 * - Based on ppc64 code - reloc_64.S
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/ppc_asm.h>
16
17/* Dynamic section table entry tags */
18DT_RELA = 7 /* Tag for Elf32_Rela section */
19DT_RELASZ = 8 /* Size of the Rela relocs */
20DT_RELAENT = 9 /* Size of one Rela reloc entry */
21
22STN_UNDEF = 0 /* Undefined symbol index */
23STB_LOCAL = 0 /* Local binding for the symbol */
24
25R_PPC_ADDR16_LO = 4 /* Lower half of (S+A) */
26R_PPC_ADDR16_HI = 5 /* Upper half of (S+A) */
27R_PPC_ADDR16_HA = 6 /* High Adjusted (S+A) */
28R_PPC_RELATIVE = 22
29
30/*
31 * r3 = desired final address
32 */
33
34_GLOBAL(relocate)
35
36 mflr r0 /* Save our LR */
37 bl 0f /* Find our current runtime address */
380: mflr r12 /* Make it accessible */
39 mtlr r0
40
41 lwz r11, (p_dyn - 0b)(r12)
42 add r11, r11, r12 /* runtime address of .dynamic section */
43 lwz r9, (p_rela - 0b)(r12)
44 add r9, r9, r12 /* runtime address of .rela.dyn section */
45 lwz r10, (p_st - 0b)(r12)
46 add r10, r10, r12 /* runtime address of _stext section */
47 lwz r13, (p_sym - 0b)(r12)
48 add r13, r13, r12 /* runtime address of .dynsym section */
49
50 /*
51 * Scan the dynamic section for RELA, RELASZ entries
52 */
53 li r6, 0
54 li r7, 0
55 li r8, 0
561: lwz r5, 0(r11) /* ELF_Dyn.d_tag */
57 cmpwi r5, 0 /* End of ELF_Dyn[] */
58 beq eodyn
59 cmpwi r5, DT_RELA
60 bne relasz
61 lwz r7, 4(r11) /* r7 = rela.link */
62 b skip
63relasz:
64 cmpwi r5, DT_RELASZ
65 bne relaent
66 lwz r8, 4(r11) /* r8 = Total Rela relocs size */
67 b skip
68relaent:
69 cmpwi r5, DT_RELAENT
70 bne skip
71 lwz r6, 4(r11) /* r6 = Size of one Rela reloc */
72skip:
73 addi r11, r11, 8
74 b 1b
75eodyn: /* End of Dyn Table scan */
76
77 /* Check if we have found all the entries */
78 cmpwi r7, 0
79 beq done
80 cmpwi r8, 0
81 beq done
82 cmpwi r6, 0
83 beq done
84
85
86 /*
87 * Work out the current offset from the link time address of .rela
88 * section.
89 * cur_offset[r7] = rela.run[r9] - rela.link [r7]
90 * _stext.link[r12] = _stext.run[r10] - cur_offset[r7]
91 * final_offset[r3] = _stext.final[r3] - _stext.link[r12]
92 */
93 subf r7, r7, r9 /* cur_offset */
94 subf r12, r7, r10
95 subf r3, r12, r3 /* final_offset */
96
97 subf r8, r6, r8 /* relaz -= relaent */
98 /*
99 * Scan through the .rela table and process each entry
100 * r9 - points to the current .rela table entry
101 * r13 - points to the symbol table
102 */
103
104 /*
105 * Check if we have a relocation based on symbol
106 * r5 will hold the value of the symbol.
107 */
108applyrela:
109 lwz r4, 4(r9) /* r4 = rela.r_info */
110 srwi r5, r4, 8 /* ELF32_R_SYM(r_info) */
111 cmpwi r5, STN_UNDEF /* sym == STN_UNDEF ? */
112 beq get_type /* value = 0 */
113 /* Find the value of the symbol at index(r5) */
114 slwi r5, r5, 4 /* r5 = r5 * sizeof(Elf32_Sym) */
115 add r12, r13, r5 /* r12 = &__dyn_sym[Index] */
116
117 /*
118 * GNU ld has a bug, where dynamic relocs based on
119 * STB_LOCAL symbols, the value should be assumed
120 * to be zero. - Alan Modra
121 */
122 /* XXX: Do we need to check if we are using GNU ld ? */
123 lbz r5, 12(r12) /* r5 = dyn_sym[Index].st_info */
124 extrwi r5, r5, 4, 24 /* r5 = ELF32_ST_BIND(r5) */
125 cmpwi r5, STB_LOCAL /* st_value = 0, ld bug */
126 beq get_type /* We have r5 = 0 */
127 lwz r5, 4(r12) /* r5 = __dyn_sym[Index].st_value */
128
129get_type:
130 /* Load the relocation type to r4 */
131 extrwi r4, r4, 8, 24 /* r4 = ELF32_R_TYPE(r_info) = ((char*)r4)[3] */
132
133 /* R_PPC_RELATIVE */
134 cmpwi r4, R_PPC_RELATIVE
135 bne hi16
136 lwz r4, 0(r9) /* r_offset */
137 lwz r0, 8(r9) /* r_addend */
138 add r0, r0, r3 /* final addend */
139 stwx r0, r4, r7 /* memory[r4+r7]) = (u32)r0 */
140 b nxtrela /* continue */
141
142 /* R_PPC_ADDR16_HI */
143hi16:
144 cmpwi r4, R_PPC_ADDR16_HI
145 bne ha16
146 lwz r4, 0(r9) /* r_offset */
147 lwz r0, 8(r9) /* r_addend */
148 add r0, r0, r3
149 add r0, r0, r5 /* r0 = (S+A+Offset) */
150 extrwi r0, r0, 16, 0 /* r0 = (r0 >> 16) */
151 b store_half
152
153 /* R_PPC_ADDR16_HA */
154ha16:
155 cmpwi r4, R_PPC_ADDR16_HA
156 bne lo16
157 lwz r4, 0(r9) /* r_offset */
158 lwz r0, 8(r9) /* r_addend */
159 add r0, r0, r3
160 add r0, r0, r5 /* r0 = (S+A+Offset) */
161 extrwi r5, r0, 1, 16 /* Extract bit 16 */
162 extrwi r0, r0, 16, 0 /* r0 = (r0 >> 16) */
163 add r0, r0, r5 /* Add it to r0 */
164 b store_half
165
166 /* R_PPC_ADDR16_LO */
167lo16:
168 cmpwi r4, R_PPC_ADDR16_LO
169 bne nxtrela
170 lwz r4, 0(r9) /* r_offset */
171 lwz r0, 8(r9) /* r_addend */
172 add r0, r0, r3
173 add r0, r0, r5 /* r0 = (S+A+Offset) */
174 extrwi r0, r0, 16, 16 /* r0 &= 0xffff */
175 /* Fall through to */
176
177 /* Store half word */
178store_half:
179 sthx r0, r4, r7 /* memory[r4+r7] = (u16)r0 */
180
181nxtrela:
182 /*
183 * We have to flush the modified instructions to the
184 * main storage from the d-cache. And also, invalidate the
185 * cached instructions in i-cache which has been modified.
186 *
187 * We delay the sync / isync operation till the end, since
188 * we won't be executing the modified instructions until
189 * we return from here.
190 */
191 dcbst r4,r7
192 sync /* Ensure the data is flushed before icbi */
193 icbi r4,r7
194 cmpwi r8, 0 /* relasz = 0 ? */
195 ble done
196 add r9, r9, r6 /* move to next entry in the .rela table */
197 subf r8, r6, r8 /* relasz -= relaent */
198 b applyrela
199
200done:
201 sync /* Wait for the flush to finish */
202 isync /* Discard prefetched instructions */
203 blr
204
205p_dyn: .long __dynamic_start - 0b
206p_rela: .long __rela_dyn_start - 0b
207p_sym: .long __dynamic_symtab - 0b
208p_st: .long _stext - 0b
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index e037c7494fd..4174b4b2324 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -568,6 +568,12 @@ static void rtas_flash_firmware(int reboot_type)
568 } 568 }
569 569
570 /* 570 /*
571 * Just before starting the firmware flash, cancel the event scan work
572 * to avoid any soft lockup issues.
573 */
574 rtas_cancel_event_scan();
575
576 /*
571 * NOTE: the "first" block must be under 4GB, so we create 577 * NOTE: the "first" block must be under 4GB, so we create
572 * an entry with no data blocks in the reserved buffer in 578 * an entry with no data blocks in the reserved buffer in
573 * the kernel data segment. 579 * the kernel data segment.
diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c
index 481ef064c8f..1045ff49cc6 100644
--- a/arch/powerpc/kernel/rtasd.c
+++ b/arch/powerpc/kernel/rtasd.c
@@ -472,6 +472,13 @@ static void start_event_scan(void)
472 &event_scan_work, event_scan_delay); 472 &event_scan_work, event_scan_delay);
473} 473}
474 474
475/* Cancel the rtas event scan work */
476void rtas_cancel_event_scan(void)
477{
478 cancel_delayed_work_sync(&event_scan_work);
479}
480EXPORT_SYMBOL_GPL(rtas_cancel_event_scan);
481
475static int __init rtas_init(void) 482static int __init rtas_init(void)
476{ 483{
477 struct proc_dir_entry *entry; 484 struct proc_dir_entry *entry;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index fb9bb46e7e8..4cb8f1e9d04 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -35,6 +35,8 @@
35#include <linux/pci.h> 35#include <linux/pci.h>
36#include <linux/lockdep.h> 36#include <linux/lockdep.h>
37#include <linux/memblock.h> 37#include <linux/memblock.h>
38#include <linux/hugetlb.h>
39
38#include <asm/io.h> 40#include <asm/io.h>
39#include <asm/kdump.h> 41#include <asm/kdump.h>
40#include <asm/prom.h> 42#include <asm/prom.h>
@@ -64,6 +66,7 @@
64#include <asm/mmu_context.h> 66#include <asm/mmu_context.h>
65#include <asm/code-patching.h> 67#include <asm/code-patching.h>
66#include <asm/kvm_ppc.h> 68#include <asm/kvm_ppc.h>
69#include <asm/hugetlb.h>
67 70
68#include "setup.h" 71#include "setup.h"
69 72
@@ -217,6 +220,13 @@ void __init early_setup(unsigned long dt_ptr)
217 /* Initialize the hash table or TLB handling */ 220 /* Initialize the hash table or TLB handling */
218 early_init_mmu(); 221 early_init_mmu();
219 222
223 /*
224 * Reserve any gigantic pages requested on the command line.
225 * memblock needs to have been initialized by the time this is
226 * called since this will reserve memory.
227 */
228 reserve_hugetlb_gpages();
229
220 DBG(" <- early_setup()\n"); 230 DBG(" <- early_setup()\n");
221} 231}
222 232
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 6df70907d60..f0abe92f63f 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -187,7 +187,8 @@ int smp_request_message_ipi(int virq, int msg)
187 return 1; 187 return 1;
188 } 188 }
189#endif 189#endif
190 err = request_irq(virq, smp_ipi_action[msg], IRQF_PERCPU, 190 err = request_irq(virq, smp_ipi_action[msg],
191 IRQF_PERCPU | IRQF_NO_THREAD,
191 smp_ipi_name[msg], 0); 192 smp_ipi_name[msg], 0);
192 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", 193 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
193 virq, smp_ipi_name[msg], err); 194 virq, smp_ipi_name[msg], err);
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index ce035c1905f..6fdf5ffe8c4 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -18,6 +18,7 @@
18#include <asm/machdep.h> 18#include <asm/machdep.h>
19#include <asm/smp.h> 19#include <asm/smp.h>
20#include <asm/pmc.h> 20#include <asm/pmc.h>
21#include <asm/system.h>
21 22
22#include "cacheinfo.h" 23#include "cacheinfo.h"
23 24
@@ -51,6 +52,7 @@ static ssize_t store_smt_snooze_delay(struct sys_device *dev,
51 return -EINVAL; 52 return -EINVAL;
52 53
53 per_cpu(smt_snooze_delay, cpu->sysdev.id) = snooze; 54 per_cpu(smt_snooze_delay, cpu->sysdev.id) = snooze;
55 update_smt_snooze_delay(snooze);
54 56
55 return count; 57 return count;
56} 58}
@@ -177,11 +179,13 @@ SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
177SYSFS_PMCSETUP(purr, SPRN_PURR); 179SYSFS_PMCSETUP(purr, SPRN_PURR);
178SYSFS_PMCSETUP(spurr, SPRN_SPURR); 180SYSFS_PMCSETUP(spurr, SPRN_SPURR);
179SYSFS_PMCSETUP(dscr, SPRN_DSCR); 181SYSFS_PMCSETUP(dscr, SPRN_DSCR);
182SYSFS_PMCSETUP(pir, SPRN_PIR);
180 183
181static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra); 184static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
182static SYSDEV_ATTR(spurr, 0600, show_spurr, NULL); 185static SYSDEV_ATTR(spurr, 0600, show_spurr, NULL);
183static SYSDEV_ATTR(dscr, 0600, show_dscr, store_dscr); 186static SYSDEV_ATTR(dscr, 0600, show_dscr, store_dscr);
184static SYSDEV_ATTR(purr, 0600, show_purr, store_purr); 187static SYSDEV_ATTR(purr, 0600, show_purr, store_purr);
188static SYSDEV_ATTR(pir, 0400, show_pir, NULL);
185 189
186unsigned long dscr_default = 0; 190unsigned long dscr_default = 0;
187EXPORT_SYMBOL(dscr_default); 191EXPORT_SYMBOL(dscr_default);
@@ -392,6 +396,9 @@ static void __cpuinit register_cpu_online(unsigned int cpu)
392 396
393 if (cpu_has_feature(CPU_FTR_DSCR)) 397 if (cpu_has_feature(CPU_FTR_DSCR))
394 sysdev_create_file(s, &attr_dscr); 398 sysdev_create_file(s, &attr_dscr);
399
400 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
401 sysdev_create_file(s, &attr_pir);
395#endif /* CONFIG_PPC64 */ 402#endif /* CONFIG_PPC64 */
396 403
397 cacheinfo_cpu_online(cpu); 404 cacheinfo_cpu_online(cpu);
@@ -462,6 +469,9 @@ static void unregister_cpu_online(unsigned int cpu)
462 469
463 if (cpu_has_feature(CPU_FTR_DSCR)) 470 if (cpu_has_feature(CPU_FTR_DSCR))
464 sysdev_remove_file(s, &attr_dscr); 471 sysdev_remove_file(s, &attr_dscr);
472
473 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
474 sysdev_remove_file(s, &attr_pir);
465#endif /* CONFIG_PPC64 */ 475#endif /* CONFIG_PPC64 */
466 476
467 cacheinfo_cpu_offline(cpu); 477 cacheinfo_cpu_offline(cpu);
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 522bb1dfc35..567dd7c3ac2 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -86,8 +86,6 @@ static struct clocksource clocksource_rtc = {
86 .rating = 400, 86 .rating = 400,
87 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 87 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
88 .mask = CLOCKSOURCE_MASK(64), 88 .mask = CLOCKSOURCE_MASK(64),
89 .shift = 22,
90 .mult = 0, /* To be filled in */
91 .read = rtc_read, 89 .read = rtc_read,
92}; 90};
93 91
@@ -97,8 +95,6 @@ static struct clocksource clocksource_timebase = {
97 .rating = 400, 95 .rating = 400,
98 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
99 .mask = CLOCKSOURCE_MASK(64), 97 .mask = CLOCKSOURCE_MASK(64),
100 .shift = 22,
101 .mult = 0, /* To be filled in */
102 .read = timebase_read, 98 .read = timebase_read,
103}; 99};
104 100
@@ -110,22 +106,16 @@ static void decrementer_set_mode(enum clock_event_mode mode,
110 struct clock_event_device *dev); 106 struct clock_event_device *dev);
111 107
112static struct clock_event_device decrementer_clockevent = { 108static struct clock_event_device decrementer_clockevent = {
113 .name = "decrementer", 109 .name = "decrementer",
114 .rating = 200, 110 .rating = 200,
115 .shift = 0, /* To be filled in */ 111 .irq = 0,
116 .mult = 0, /* To be filled in */ 112 .set_next_event = decrementer_set_next_event,
117 .irq = 0, 113 .set_mode = decrementer_set_mode,
118 .set_next_event = decrementer_set_next_event, 114 .features = CLOCK_EVT_FEAT_ONESHOT,
119 .set_mode = decrementer_set_mode,
120 .features = CLOCK_EVT_FEAT_ONESHOT,
121}; 115};
122 116
123struct decrementer_clock { 117DEFINE_PER_CPU(u64, decrementers_next_tb);
124 struct clock_event_device event; 118static DEFINE_PER_CPU(struct clock_event_device, decrementers);
125 u64 next_tb;
126};
127
128static DEFINE_PER_CPU(struct decrementer_clock, decrementers);
129 119
130#ifdef CONFIG_PPC_ISERIES 120#ifdef CONFIG_PPC_ISERIES
131static unsigned long __initdata iSeries_recal_titan; 121static unsigned long __initdata iSeries_recal_titan;
@@ -168,13 +158,13 @@ EXPORT_SYMBOL_GPL(ppc_tb_freq);
168#ifdef CONFIG_VIRT_CPU_ACCOUNTING 158#ifdef CONFIG_VIRT_CPU_ACCOUNTING
169/* 159/*
170 * Factors for converting from cputime_t (timebase ticks) to 160 * Factors for converting from cputime_t (timebase ticks) to
171 * jiffies, milliseconds, seconds, and clock_t (1/USER_HZ seconds). 161 * jiffies, microseconds, seconds, and clock_t (1/USER_HZ seconds).
172 * These are all stored as 0.64 fixed-point binary fractions. 162 * These are all stored as 0.64 fixed-point binary fractions.
173 */ 163 */
174u64 __cputime_jiffies_factor; 164u64 __cputime_jiffies_factor;
175EXPORT_SYMBOL(__cputime_jiffies_factor); 165EXPORT_SYMBOL(__cputime_jiffies_factor);
176u64 __cputime_msec_factor; 166u64 __cputime_usec_factor;
177EXPORT_SYMBOL(__cputime_msec_factor); 167EXPORT_SYMBOL(__cputime_usec_factor);
178u64 __cputime_sec_factor; 168u64 __cputime_sec_factor;
179EXPORT_SYMBOL(__cputime_sec_factor); 169EXPORT_SYMBOL(__cputime_sec_factor);
180u64 __cputime_clockt_factor; 170u64 __cputime_clockt_factor;
@@ -192,8 +182,8 @@ static void calc_cputime_factors(void)
192 182
193 div128_by_32(HZ, 0, tb_ticks_per_sec, &res); 183 div128_by_32(HZ, 0, tb_ticks_per_sec, &res);
194 __cputime_jiffies_factor = res.result_low; 184 __cputime_jiffies_factor = res.result_low;
195 div128_by_32(1000, 0, tb_ticks_per_sec, &res); 185 div128_by_32(1000000, 0, tb_ticks_per_sec, &res);
196 __cputime_msec_factor = res.result_low; 186 __cputime_usec_factor = res.result_low;
197 div128_by_32(1, 0, tb_ticks_per_sec, &res); 187 div128_by_32(1, 0, tb_ticks_per_sec, &res);
198 __cputime_sec_factor = res.result_low; 188 __cputime_sec_factor = res.result_low;
199 div128_by_32(USER_HZ, 0, tb_ticks_per_sec, &res); 189 div128_by_32(USER_HZ, 0, tb_ticks_per_sec, &res);
@@ -441,7 +431,7 @@ EXPORT_SYMBOL(profile_pc);
441/* 431/*
442 * This function recalibrates the timebase based on the 49-bit time-of-day 432 * This function recalibrates the timebase based on the 49-bit time-of-day
443 * value in the Titan chip. The Titan is much more accurate than the value 433 * value in the Titan chip. The Titan is much more accurate than the value
444 * returned by the service processor for the timebase frequency. 434 * returned by the service processor for the timebase frequency.
445 */ 435 */
446 436
447static int __init iSeries_tb_recal(void) 437static int __init iSeries_tb_recal(void)
@@ -576,9 +566,8 @@ void arch_irq_work_raise(void)
576void timer_interrupt(struct pt_regs * regs) 566void timer_interrupt(struct pt_regs * regs)
577{ 567{
578 struct pt_regs *old_regs; 568 struct pt_regs *old_regs;
579 struct decrementer_clock *decrementer = &__get_cpu_var(decrementers); 569 u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
580 struct clock_event_device *evt = &decrementer->event; 570 struct clock_event_device *evt = &__get_cpu_var(decrementers);
581 u64 now;
582 571
583 /* Ensure a positive value is written to the decrementer, or else 572 /* Ensure a positive value is written to the decrementer, or else
584 * some CPUs will continue to take decrementer exceptions. 573 * some CPUs will continue to take decrementer exceptions.
@@ -613,16 +602,9 @@ void timer_interrupt(struct pt_regs * regs)
613 get_lppaca()->int_dword.fields.decr_int = 0; 602 get_lppaca()->int_dword.fields.decr_int = 0;
614#endif 603#endif
615 604
616 now = get_tb_or_rtc(); 605 *next_tb = ~(u64)0;
617 if (now >= decrementer->next_tb) { 606 if (evt->event_handler)
618 decrementer->next_tb = ~(u64)0; 607 evt->event_handler(evt);
619 if (evt->event_handler)
620 evt->event_handler(evt);
621 } else {
622 now = decrementer->next_tb - now;
623 if (now <= DECREMENTER_MAX)
624 set_dec((int)now);
625 }
626 608
627#ifdef CONFIG_PPC_ISERIES 609#ifdef CONFIG_PPC_ISERIES
628 if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending()) 610 if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending())
@@ -650,9 +632,9 @@ static void generic_suspend_disable_irqs(void)
650 * with suspending. 632 * with suspending.
651 */ 633 */
652 634
653 set_dec(0x7fffffff); 635 set_dec(DECREMENTER_MAX);
654 local_irq_disable(); 636 local_irq_disable();
655 set_dec(0x7fffffff); 637 set_dec(DECREMENTER_MAX);
656} 638}
657 639
658static void generic_suspend_enable_irqs(void) 640static void generic_suspend_enable_irqs(void)
@@ -824,9 +806,8 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
824 ++vdso_data->tb_update_count; 806 ++vdso_data->tb_update_count;
825 smp_mb(); 807 smp_mb();
826 808
827 /* XXX this assumes clock->shift == 22 */ 809 /* 19342813113834067 ~= 2^(20+64) / 1e9 */
828 /* 4611686018 ~= 2^(20+64-22) / 1e9 */ 810 new_tb_to_xs = (u64) mult * (19342813113834067ULL >> clock->shift);
829 new_tb_to_xs = (u64) mult * 4611686018ULL;
830 new_stamp_xsec = (u64) wall_time->tv_nsec * XSEC_PER_SEC; 811 new_stamp_xsec = (u64) wall_time->tv_nsec * XSEC_PER_SEC;
831 do_div(new_stamp_xsec, 1000000000); 812 do_div(new_stamp_xsec, 1000000000);
832 new_stamp_xsec += (u64) wall_time->tv_sec * XSEC_PER_SEC; 813 new_stamp_xsec += (u64) wall_time->tv_sec * XSEC_PER_SEC;
@@ -877,9 +858,7 @@ static void __init clocksource_init(void)
877 else 858 else
878 clock = &clocksource_timebase; 859 clock = &clocksource_timebase;
879 860
880 clock->mult = clocksource_hz2mult(tb_ticks_per_sec, clock->shift); 861 if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
881
882 if (clocksource_register(clock)) {
883 printk(KERN_ERR "clocksource: %s is already registered\n", 862 printk(KERN_ERR "clocksource: %s is already registered\n",
884 clock->name); 863 clock->name);
885 return; 864 return;
@@ -892,7 +871,7 @@ static void __init clocksource_init(void)
892static int decrementer_set_next_event(unsigned long evt, 871static int decrementer_set_next_event(unsigned long evt,
893 struct clock_event_device *dev) 872 struct clock_event_device *dev)
894{ 873{
895 __get_cpu_var(decrementers).next_tb = get_tb_or_rtc() + evt; 874 __get_cpu_var(decrementers_next_tb) = get_tb_or_rtc() + evt;
896 set_dec(evt); 875 set_dec(evt);
897 return 0; 876 return 0;
898} 877}
@@ -904,34 +883,9 @@ static void decrementer_set_mode(enum clock_event_mode mode,
904 decrementer_set_next_event(DECREMENTER_MAX, dev); 883 decrementer_set_next_event(DECREMENTER_MAX, dev);
905} 884}
906 885
907static inline uint64_t div_sc64(unsigned long ticks, unsigned long nsec,
908 int shift)
909{
910 uint64_t tmp = ((uint64_t)ticks) << shift;
911
912 do_div(tmp, nsec);
913 return tmp;
914}
915
916static void __init setup_clockevent_multiplier(unsigned long hz)
917{
918 u64 mult, shift = 32;
919
920 while (1) {
921 mult = div_sc64(hz, NSEC_PER_SEC, shift);
922 if (mult && (mult >> 32UL) == 0UL)
923 break;
924
925 shift--;
926 }
927
928 decrementer_clockevent.shift = shift;
929 decrementer_clockevent.mult = mult;
930}
931
932static void register_decrementer_clockevent(int cpu) 886static void register_decrementer_clockevent(int cpu)
933{ 887{
934 struct clock_event_device *dec = &per_cpu(decrementers, cpu).event; 888 struct clock_event_device *dec = &per_cpu(decrementers, cpu);
935 889
936 *dec = decrementer_clockevent; 890 *dec = decrementer_clockevent;
937 dec->cpumask = cpumask_of(cpu); 891 dec->cpumask = cpumask_of(cpu);
@@ -946,7 +900,8 @@ static void __init init_decrementer_clockevent(void)
946{ 900{
947 int cpu = smp_processor_id(); 901 int cpu = smp_processor_id();
948 902
949 setup_clockevent_multiplier(ppc_tb_freq); 903 clockevents_calc_mult_shift(&decrementer_clockevent, ppc_tb_freq, 4);
904
950 decrementer_clockevent.max_delta_ns = 905 decrementer_clockevent.max_delta_ns =
951 clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent); 906 clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent);
952 decrementer_clockevent.min_delta_ns = 907 decrementer_clockevent.min_delta_ns =
@@ -1014,10 +969,10 @@ void __init time_init(void)
1014 boot_tb = get_tb_or_rtc(); 969 boot_tb = get_tb_or_rtc();
1015 970
1016 /* If platform provided a timezone (pmac), we correct the time */ 971 /* If platform provided a timezone (pmac), we correct the time */
1017 if (timezone_offset) { 972 if (timezone_offset) {
1018 sys_tz.tz_minuteswest = -timezone_offset / 60; 973 sys_tz.tz_minuteswest = -timezone_offset / 60;
1019 sys_tz.tz_dsttime = 0; 974 sys_tz.tz_dsttime = 0;
1020 } 975 }
1021 976
1022 vdso_data->tb_update_count = 0; 977 vdso_data->tb_update_count = 0;
1023 vdso_data->tb_ticks_per_sec = tb_ticks_per_sec; 978 vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5459d148a0f..c091527efd8 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -98,18 +98,14 @@ static void pmac_backlight_unblank(void)
98static inline void pmac_backlight_unblank(void) { } 98static inline void pmac_backlight_unblank(void) { }
99#endif 99#endif
100 100
101int die(const char *str, struct pt_regs *regs, long err) 101static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
102static int die_owner = -1;
103static unsigned int die_nest_count;
104static int die_counter;
105
106static unsigned __kprobes long oops_begin(struct pt_regs *regs)
102{ 107{
103 static struct { 108 int cpu;
104 raw_spinlock_t lock;
105 u32 lock_owner;
106 int lock_owner_depth;
107 } die = {
108 .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock),
109 .lock_owner = -1,
110 .lock_owner_depth = 0
111 };
112 static int die_counter;
113 unsigned long flags; 109 unsigned long flags;
114 110
115 if (debugger(regs)) 111 if (debugger(regs))
@@ -117,66 +113,109 @@ int die(const char *str, struct pt_regs *regs, long err)
117 113
118 oops_enter(); 114 oops_enter();
119 115
120 if (die.lock_owner != raw_smp_processor_id()) { 116 /* racy, but better than risking deadlock. */
121 console_verbose(); 117 raw_local_irq_save(flags);
122 raw_spin_lock_irqsave(&die.lock, flags); 118 cpu = smp_processor_id();
123 die.lock_owner = smp_processor_id(); 119 if (!arch_spin_trylock(&die_lock)) {
124 die.lock_owner_depth = 0; 120 if (cpu == die_owner)
125 bust_spinlocks(1); 121 /* nested oops. should stop eventually */;
126 if (machine_is(powermac)) 122 else
127 pmac_backlight_unblank(); 123 arch_spin_lock(&die_lock);
128 } else {
129 local_save_flags(flags);
130 } 124 }
125 die_nest_count++;
126 die_owner = cpu;
127 console_verbose();
128 bust_spinlocks(1);
129 if (machine_is(powermac))
130 pmac_backlight_unblank();
131 return flags;
132}
131 133
132 if (++die.lock_owner_depth < 3) { 134static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
133 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 135 int signr)
134#ifdef CONFIG_PREEMPT 136{
135 printk("PREEMPT "); 137 bust_spinlocks(0);
136#endif 138 die_owner = -1;
137#ifdef CONFIG_SMP 139 add_taint(TAINT_DIE);
138 printk("SMP NR_CPUS=%d ", NR_CPUS); 140 die_nest_count--;
139#endif 141 oops_exit();
140#ifdef CONFIG_DEBUG_PAGEALLOC 142 printk("\n");
141 printk("DEBUG_PAGEALLOC "); 143 if (!die_nest_count)
142#endif 144 /* Nest count reaches zero, release the lock. */
143#ifdef CONFIG_NUMA 145 arch_spin_unlock(&die_lock);
144 printk("NUMA "); 146 raw_local_irq_restore(flags);
145#endif
146 printk("%s\n", ppc_md.name ? ppc_md.name : "");
147 147
148 if (notify_die(DIE_OOPS, str, regs, err, 255, 148 /*
149 SIGSEGV) == NOTIFY_STOP) 149 * A system reset (0x100) is a request to dump, so we always send
150 return 1; 150 * it through the crashdump code.
151 */
152 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
153 crash_kexec(regs);
151 154
152 print_modules(); 155 /*
153 show_regs(regs); 156 * We aren't the primary crash CPU. We need to send it
154 } else { 157 * to a holding pattern to avoid it ending up in the panic
155 printk("Recursive die() failure, output suppressed\n"); 158 * code.
159 */
160 crash_kexec_secondary(regs);
156 } 161 }
157 162
158 bust_spinlocks(0); 163 if (!signr)
159 die.lock_owner = -1; 164 return;
160 add_taint(TAINT_DIE);
161 raw_spin_unlock_irqrestore(&die.lock, flags);
162 165
163 if (kexec_should_crash(current) || 166 /*
164 kexec_sr_activated(smp_processor_id())) 167 * While our oops output is serialised by a spinlock, output
165 crash_kexec(regs); 168 * from panic() called below can race and corrupt it. If we
166 crash_kexec_secondary(regs); 169 * know we are going to panic, delay for 1 second so we have a
170 * chance to get clean backtraces from all CPUs that are oopsing.
171 */
172 if (in_interrupt() || panic_on_oops || !current->pid ||
173 is_global_init(current)) {
174 mdelay(MSEC_PER_SEC);
175 }
167 176
168 if (in_interrupt()) 177 if (in_interrupt())
169 panic("Fatal exception in interrupt"); 178 panic("Fatal exception in interrupt");
170
171 if (panic_on_oops) 179 if (panic_on_oops)
172 panic("Fatal exception"); 180 panic("Fatal exception");
181 do_exit(signr);
182}
173 183
174 oops_exit(); 184static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
175 do_exit(err); 185{
186 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
187#ifdef CONFIG_PREEMPT
188 printk("PREEMPT ");
189#endif
190#ifdef CONFIG_SMP
191 printk("SMP NR_CPUS=%d ", NR_CPUS);
192#endif
193#ifdef CONFIG_DEBUG_PAGEALLOC
194 printk("DEBUG_PAGEALLOC ");
195#endif
196#ifdef CONFIG_NUMA
197 printk("NUMA ");
198#endif
199 printk("%s\n", ppc_md.name ? ppc_md.name : "");
200
201 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
202 return 1;
203
204 print_modules();
205 show_regs(regs);
176 206
177 return 0; 207 return 0;
178} 208}
179 209
210void die(const char *str, struct pt_regs *regs, long err)
211{
212 unsigned long flags = oops_begin(regs);
213
214 if (__die(str, regs, err))
215 err = 0;
216 oops_end(flags, regs, err);
217}
218
180void user_single_step_siginfo(struct task_struct *tsk, 219void user_single_step_siginfo(struct task_struct *tsk,
181 struct pt_regs *regs, siginfo_t *info) 220 struct pt_regs *regs, siginfo_t *info)
182{ 221{
@@ -195,10 +234,11 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
195 "at %016lx nip %016lx lr %016lx code %x\n"; 234 "at %016lx nip %016lx lr %016lx code %x\n";
196 235
197 if (!user_mode(regs)) { 236 if (!user_mode(regs)) {
198 if (die("Exception in kernel mode", regs, signr)) 237 die("Exception in kernel mode", regs, signr);
199 return; 238 return;
200 } else if (show_unhandled_signals && 239 }
201 unhandled_signal(current, signr)) { 240
241 if (show_unhandled_signals && unhandled_signal(current, signr)) {
202 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 242 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
203 current->comm, current->pid, signr, 243 current->comm, current->pid, signr,
204 addr, regs->nip, regs->link, code); 244 addr, regs->nip, regs->link, code);
@@ -220,25 +260,8 @@ void system_reset_exception(struct pt_regs *regs)
220 return; 260 return;
221 } 261 }
222 262
223#ifdef CONFIG_KEXEC
224 cpumask_set_cpu(smp_processor_id(), &cpus_in_sr);
225#endif
226
227 die("System Reset", regs, SIGABRT); 263 die("System Reset", regs, SIGABRT);
228 264
229 /*
230 * Some CPUs when released from the debugger will execute this path.
231 * These CPUs entered the debugger via a soft-reset. If the CPU was
232 * hung before entering the debugger it will return to the hung
233 * state when exiting this function. This causes a problem in
234 * kdump since the hung CPU(s) will not respond to the IPI sent
235 * from kdump. To prevent the problem we call crash_kexec_secondary()
236 * here. If a kdump had not been initiated or we exit the debugger
237 * with the "exit and recover" command (x) crash_kexec_secondary()
238 * will return after 5ms and the CPU returns to its previous state.
239 */
240 crash_kexec_secondary(regs);
241
242 /* Must die if the interrupt is not recoverable */ 265 /* Must die if the interrupt is not recoverable */
243 if (!(regs->msr & MSR_RI)) 266 if (!(regs->msr & MSR_RI))
244 panic("Unrecoverable System Reset"); 267 panic("Unrecoverable System Reset");
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 920276c0f6a..710a54005df 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -170,7 +170,13 @@ SECTIONS
170 } 170 }
171#ifdef CONFIG_RELOCATABLE 171#ifdef CONFIG_RELOCATABLE
172 . = ALIGN(8); 172 . = ALIGN(8);
173 .dynsym : AT(ADDR(.dynsym) - LOAD_OFFSET) { *(.dynsym) } 173 .dynsym : AT(ADDR(.dynsym) - LOAD_OFFSET)
174 {
175#ifdef CONFIG_RELOCATABLE_PPC32
176 __dynamic_symtab = .;
177#endif
178 *(.dynsym)
179 }
174 .dynstr : AT(ADDR(.dynstr) - LOAD_OFFSET) { *(.dynstr) } 180 .dynstr : AT(ADDR(.dynstr) - LOAD_OFFSET) { *(.dynstr) }
175 .dynamic : AT(ADDR(.dynamic) - LOAD_OFFSET) 181 .dynamic : AT(ADDR(.dynamic) - LOAD_OFFSET)
176 { 182 {
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 44d8829334a..5c8b26183f5 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -112,6 +112,9 @@ kvm_start_guest:
112 stbcix r0, r5, r6 /* clear it */ 112 stbcix r0, r5, r6 /* clear it */
113 stwcix r8, r5, r7 /* EOI it */ 113 stwcix r8, r5, r7 /* EOI it */
114 114
115 /* NV GPR values from power7_idle() will no longer be valid */
116 stb r0, PACA_NAPSTATELOST(r13)
117
115.global kvmppc_hv_entry 118.global kvmppc_hv_entry
116kvmppc_hv_entry: 119kvmppc_hv_entry:
117 120
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 166a6a0ad54..7735a2c2e6d 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -16,13 +16,15 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o
16 16
17obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \ 17obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
18 memcpy_64.o usercopy_64.o mem_64.o string.o \ 18 memcpy_64.o usercopy_64.o mem_64.o string.o \
19 checksum_wrappers_64.o hweight_64.o 19 checksum_wrappers_64.o hweight_64.o \
20 copyuser_power7.o
20obj-$(CONFIG_XMON) += sstep.o ldstfp.o 21obj-$(CONFIG_XMON) += sstep.o ldstfp.o
21obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o 22obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o
22obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o 23obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o
23 24
24ifeq ($(CONFIG_PPC64),y) 25ifeq ($(CONFIG_PPC64),y)
25obj-$(CONFIG_SMP) += locks.o 26obj-$(CONFIG_SMP) += locks.o
27obj-$(CONFIG_ALTIVEC) += copyuser_power7_vmx.o
26endif 28endif
27 29
28obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o 30obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 578b625d6a3..773d38f90aa 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -11,6 +11,12 @@
11 11
12 .align 7 12 .align 7
13_GLOBAL(__copy_tofrom_user) 13_GLOBAL(__copy_tofrom_user)
14BEGIN_FTR_SECTION
15 nop
16FTR_SECTION_ELSE
17 b __copy_tofrom_user_power7
18ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
19_GLOBAL(__copy_tofrom_user_base)
14 /* first check for a whole page copy on a page boundary */ 20 /* first check for a whole page copy on a page boundary */
15 cmpldi cr1,r5,16 21 cmpldi cr1,r5,16
16 cmpdi cr6,r5,4096 22 cmpdi cr6,r5,4096
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
new file mode 100644
index 00000000000..497db7b23bb
--- /dev/null
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -0,0 +1,683 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) IBM Corporation, 2011
17 *
18 * Author: Anton Blanchard <anton@au.ibm.com>
19 */
20#include <asm/ppc_asm.h>
21
22#define STACKFRAMESIZE 256
23#define STK_REG(i) (112 + ((i)-14)*8)
24
25 .macro err1
26100:
27 .section __ex_table,"a"
28 .align 3
29 .llong 100b,.Ldo_err1
30 .previous
31 .endm
32
33 .macro err2
34200:
35 .section __ex_table,"a"
36 .align 3
37 .llong 200b,.Ldo_err2
38 .previous
39 .endm
40
41#ifdef CONFIG_ALTIVEC
42 .macro err3
43300:
44 .section __ex_table,"a"
45 .align 3
46 .llong 300b,.Ldo_err3
47 .previous
48 .endm
49
50 .macro err4
51400:
52 .section __ex_table,"a"
53 .align 3
54 .llong 400b,.Ldo_err4
55 .previous
56 .endm
57
58
59.Ldo_err4:
60 ld r16,STK_REG(r16)(r1)
61 ld r15,STK_REG(r15)(r1)
62 ld r14,STK_REG(r14)(r1)
63.Ldo_err3:
64 bl .exit_vmx_copy
65 ld r0,STACKFRAMESIZE+16(r1)
66 mtlr r0
67 b .Lexit
68#endif /* CONFIG_ALTIVEC */
69
70.Ldo_err2:
71 ld r22,STK_REG(r22)(r1)
72 ld r21,STK_REG(r21)(r1)
73 ld r20,STK_REG(r20)(r1)
74 ld r19,STK_REG(r19)(r1)
75 ld r18,STK_REG(r18)(r1)
76 ld r17,STK_REG(r17)(r1)
77 ld r16,STK_REG(r16)(r1)
78 ld r15,STK_REG(r15)(r1)
79 ld r14,STK_REG(r14)(r1)
80.Lexit:
81 addi r1,r1,STACKFRAMESIZE
82.Ldo_err1:
83 ld r3,48(r1)
84 ld r4,56(r1)
85 ld r5,64(r1)
86 b __copy_tofrom_user_base
87
88
89_GLOBAL(__copy_tofrom_user_power7)
90#ifdef CONFIG_ALTIVEC
91 cmpldi r5,16
92 cmpldi cr1,r5,4096
93
94 std r3,48(r1)
95 std r4,56(r1)
96 std r5,64(r1)
97
98 blt .Lshort_copy
99 bgt cr1,.Lvmx_copy
100#else
101 cmpldi r5,16
102
103 std r3,48(r1)
104 std r4,56(r1)
105 std r5,64(r1)
106
107 blt .Lshort_copy
108#endif
109
110.Lnonvmx_copy:
111 /* Get the source 8B aligned */
112 neg r6,r4
113 mtocrf 0x01,r6
114 clrldi r6,r6,(64-3)
115
116 bf cr7*4+3,1f
117err1; lbz r0,0(r4)
118 addi r4,r4,1
119err1; stb r0,0(r3)
120 addi r3,r3,1
121
1221: bf cr7*4+2,2f
123err1; lhz r0,0(r4)
124 addi r4,r4,2
125err1; sth r0,0(r3)
126 addi r3,r3,2
127
1282: bf cr7*4+1,3f
129err1; lwz r0,0(r4)
130 addi r4,r4,4
131err1; stw r0,0(r3)
132 addi r3,r3,4
133
1343: sub r5,r5,r6
135 cmpldi r5,128
136 blt 5f
137
138 mflr r0
139 stdu r1,-STACKFRAMESIZE(r1)
140 std r14,STK_REG(r14)(r1)
141 std r15,STK_REG(r15)(r1)
142 std r16,STK_REG(r16)(r1)
143 std r17,STK_REG(r17)(r1)
144 std r18,STK_REG(r18)(r1)
145 std r19,STK_REG(r19)(r1)
146 std r20,STK_REG(r20)(r1)
147 std r21,STK_REG(r21)(r1)
148 std r22,STK_REG(r22)(r1)
149 std r0,STACKFRAMESIZE+16(r1)
150
151 srdi r6,r5,7
152 mtctr r6
153
154 /* Now do cacheline (128B) sized loads and stores. */
155 .align 5
1564:
157err2; ld r0,0(r4)
158err2; ld r6,8(r4)
159err2; ld r7,16(r4)
160err2; ld r8,24(r4)
161err2; ld r9,32(r4)
162err2; ld r10,40(r4)
163err2; ld r11,48(r4)
164err2; ld r12,56(r4)
165err2; ld r14,64(r4)
166err2; ld r15,72(r4)
167err2; ld r16,80(r4)
168err2; ld r17,88(r4)
169err2; ld r18,96(r4)
170err2; ld r19,104(r4)
171err2; ld r20,112(r4)
172err2; ld r21,120(r4)
173 addi r4,r4,128
174err2; std r0,0(r3)
175err2; std r6,8(r3)
176err2; std r7,16(r3)
177err2; std r8,24(r3)
178err2; std r9,32(r3)
179err2; std r10,40(r3)
180err2; std r11,48(r3)
181err2; std r12,56(r3)
182err2; std r14,64(r3)
183err2; std r15,72(r3)
184err2; std r16,80(r3)
185err2; std r17,88(r3)
186err2; std r18,96(r3)
187err2; std r19,104(r3)
188err2; std r20,112(r3)
189err2; std r21,120(r3)
190 addi r3,r3,128
191 bdnz 4b
192
193 clrldi r5,r5,(64-7)
194
195 ld r14,STK_REG(r14)(r1)
196 ld r15,STK_REG(r15)(r1)
197 ld r16,STK_REG(r16)(r1)
198 ld r17,STK_REG(r17)(r1)
199 ld r18,STK_REG(r18)(r1)
200 ld r19,STK_REG(r19)(r1)
201 ld r20,STK_REG(r20)(r1)
202 ld r21,STK_REG(r21)(r1)
203 ld r22,STK_REG(r22)(r1)
204 addi r1,r1,STACKFRAMESIZE
205
206 /* Up to 127B to go */
2075: srdi r6,r5,4
208 mtocrf 0x01,r6
209
2106: bf cr7*4+1,7f
211err1; ld r0,0(r4)
212err1; ld r6,8(r4)
213err1; ld r7,16(r4)
214err1; ld r8,24(r4)
215err1; ld r9,32(r4)
216err1; ld r10,40(r4)
217err1; ld r11,48(r4)
218err1; ld r12,56(r4)
219 addi r4,r4,64
220err1; std r0,0(r3)
221err1; std r6,8(r3)
222err1; std r7,16(r3)
223err1; std r8,24(r3)
224err1; std r9,32(r3)
225err1; std r10,40(r3)
226err1; std r11,48(r3)
227err1; std r12,56(r3)
228 addi r3,r3,64
229
230 /* Up to 63B to go */
2317: bf cr7*4+2,8f
232err1; ld r0,0(r4)
233err1; ld r6,8(r4)
234err1; ld r7,16(r4)
235err1; ld r8,24(r4)
236 addi r4,r4,32
237err1; std r0,0(r3)
238err1; std r6,8(r3)
239err1; std r7,16(r3)
240err1; std r8,24(r3)
241 addi r3,r3,32
242
243 /* Up to 31B to go */
2448: bf cr7*4+3,9f
245err1; ld r0,0(r4)
246err1; ld r6,8(r4)
247 addi r4,r4,16
248err1; std r0,0(r3)
249err1; std r6,8(r3)
250 addi r3,r3,16
251
2529: clrldi r5,r5,(64-4)
253
254 /* Up to 15B to go */
255.Lshort_copy:
256 mtocrf 0x01,r5
257 bf cr7*4+0,12f
258err1; lwz r0,0(r4) /* Less chance of a reject with word ops */
259err1; lwz r6,4(r4)
260 addi r4,r4,8
261err1; stw r0,0(r3)
262err1; stw r6,4(r3)
263 addi r3,r3,8
264
26512: bf cr7*4+1,13f
266err1; lwz r0,0(r4)
267 addi r4,r4,4
268err1; stw r0,0(r3)
269 addi r3,r3,4
270
27113: bf cr7*4+2,14f
272err1; lhz r0,0(r4)
273 addi r4,r4,2
274err1; sth r0,0(r3)
275 addi r3,r3,2
276
27714: bf cr7*4+3,15f
278err1; lbz r0,0(r4)
279err1; stb r0,0(r3)
280
28115: li r3,0
282 blr
283
284.Lunwind_stack_nonvmx_copy:
285 addi r1,r1,STACKFRAMESIZE
286 b .Lnonvmx_copy
287
288#ifdef CONFIG_ALTIVEC
289.Lvmx_copy:
290 mflr r0
291 std r0,16(r1)
292 stdu r1,-STACKFRAMESIZE(r1)
293 bl .enter_vmx_copy
294 cmpwi r3,0
295 ld r0,STACKFRAMESIZE+16(r1)
296 ld r3,STACKFRAMESIZE+48(r1)
297 ld r4,STACKFRAMESIZE+56(r1)
298 ld r5,STACKFRAMESIZE+64(r1)
299 mtlr r0
300
301 beq .Lunwind_stack_nonvmx_copy
302
303 /*
304 * If source and destination are not relatively aligned we use a
305 * slower permute loop.
306 */
307 xor r6,r4,r3
308 rldicl. r6,r6,0,(64-4)
309 bne .Lvmx_unaligned_copy
310
311 /* Get the destination 16B aligned */
312 neg r6,r3
313 mtocrf 0x01,r6
314 clrldi r6,r6,(64-4)
315
316 bf cr7*4+3,1f
317err3; lbz r0,0(r4)
318 addi r4,r4,1
319err3; stb r0,0(r3)
320 addi r3,r3,1
321
3221: bf cr7*4+2,2f
323err3; lhz r0,0(r4)
324 addi r4,r4,2
325err3; sth r0,0(r3)
326 addi r3,r3,2
327
3282: bf cr7*4+1,3f
329err3; lwz r0,0(r4)
330 addi r4,r4,4
331err3; stw r0,0(r3)
332 addi r3,r3,4
333
3343: bf cr7*4+0,4f
335err3; ld r0,0(r4)
336 addi r4,r4,8
337err3; std r0,0(r3)
338 addi r3,r3,8
339
3404: sub r5,r5,r6
341
342 /* Get the desination 128B aligned */
343 neg r6,r3
344 srdi r7,r6,4
345 mtocrf 0x01,r7
346 clrldi r6,r6,(64-7)
347
348 li r9,16
349 li r10,32
350 li r11,48
351
352 bf cr7*4+3,5f
353err3; lvx vr1,r0,r4
354 addi r4,r4,16
355err3; stvx vr1,r0,r3
356 addi r3,r3,16
357
3585: bf cr7*4+2,6f
359err3; lvx vr1,r0,r4
360err3; lvx vr0,r4,r9
361 addi r4,r4,32
362err3; stvx vr1,r0,r3
363err3; stvx vr0,r3,r9
364 addi r3,r3,32
365
3666: bf cr7*4+1,7f
367err3; lvx vr3,r0,r4
368err3; lvx vr2,r4,r9
369err3; lvx vr1,r4,r10
370err3; lvx vr0,r4,r11
371 addi r4,r4,64
372err3; stvx vr3,r0,r3
373err3; stvx vr2,r3,r9
374err3; stvx vr1,r3,r10
375err3; stvx vr0,r3,r11
376 addi r3,r3,64
377
3787: sub r5,r5,r6
379 srdi r6,r5,7
380
381 std r14,STK_REG(r14)(r1)
382 std r15,STK_REG(r15)(r1)
383 std r16,STK_REG(r16)(r1)
384
385 li r12,64
386 li r14,80
387 li r15,96
388 li r16,112
389
390 mtctr r6
391
392 /*
393 * Now do cacheline sized loads and stores. By this stage the
394 * cacheline stores are also cacheline aligned.
395 */
396 .align 5
3978:
398err4; lvx vr7,r0,r4
399err4; lvx vr6,r4,r9
400err4; lvx vr5,r4,r10
401err4; lvx vr4,r4,r11
402err4; lvx vr3,r4,r12
403err4; lvx vr2,r4,r14
404err4; lvx vr1,r4,r15
405err4; lvx vr0,r4,r16
406 addi r4,r4,128
407err4; stvx vr7,r0,r3
408err4; stvx vr6,r3,r9
409err4; stvx vr5,r3,r10
410err4; stvx vr4,r3,r11
411err4; stvx vr3,r3,r12
412err4; stvx vr2,r3,r14
413err4; stvx vr1,r3,r15
414err4; stvx vr0,r3,r16
415 addi r3,r3,128
416 bdnz 8b
417
418 ld r14,STK_REG(r14)(r1)
419 ld r15,STK_REG(r15)(r1)
420 ld r16,STK_REG(r16)(r1)
421
422 /* Up to 127B to go */
423 clrldi r5,r5,(64-7)
424 srdi r6,r5,4
425 mtocrf 0x01,r6
426
427 bf cr7*4+1,9f
428err3; lvx vr3,r0,r4
429err3; lvx vr2,r4,r9
430err3; lvx vr1,r4,r10
431err3; lvx vr0,r4,r11
432 addi r4,r4,64
433err3; stvx vr3,r0,r3
434err3; stvx vr2,r3,r9
435err3; stvx vr1,r3,r10
436err3; stvx vr0,r3,r11
437 addi r3,r3,64
438
4399: bf cr7*4+2,10f
440err3; lvx vr1,r0,r4
441err3; lvx vr0,r4,r9
442 addi r4,r4,32
443err3; stvx vr1,r0,r3
444err3; stvx vr0,r3,r9
445 addi r3,r3,32
446
44710: bf cr7*4+3,11f
448err3; lvx vr1,r0,r4
449 addi r4,r4,16
450err3; stvx vr1,r0,r3
451 addi r3,r3,16
452
453 /* Up to 15B to go */
45411: clrldi r5,r5,(64-4)
455 mtocrf 0x01,r5
456 bf cr7*4+0,12f
457err3; ld r0,0(r4)
458 addi r4,r4,8
459err3; std r0,0(r3)
460 addi r3,r3,8
461
46212: bf cr7*4+1,13f
463err3; lwz r0,0(r4)
464 addi r4,r4,4
465err3; stw r0,0(r3)
466 addi r3,r3,4
467
46813: bf cr7*4+2,14f
469err3; lhz r0,0(r4)
470 addi r4,r4,2
471err3; sth r0,0(r3)
472 addi r3,r3,2
473
47414: bf cr7*4+3,15f
475err3; lbz r0,0(r4)
476err3; stb r0,0(r3)
477
47815: addi r1,r1,STACKFRAMESIZE
479 b .exit_vmx_copy /* tail call optimise */
480
481.Lvmx_unaligned_copy:
482 /* Get the destination 16B aligned */
483 neg r6,r3
484 mtocrf 0x01,r6
485 clrldi r6,r6,(64-4)
486
487 bf cr7*4+3,1f
488err3; lbz r0,0(r4)
489 addi r4,r4,1
490err3; stb r0,0(r3)
491 addi r3,r3,1
492
4931: bf cr7*4+2,2f
494err3; lhz r0,0(r4)
495 addi r4,r4,2
496err3; sth r0,0(r3)
497 addi r3,r3,2
498
4992: bf cr7*4+1,3f
500err3; lwz r0,0(r4)
501 addi r4,r4,4
502err3; stw r0,0(r3)
503 addi r3,r3,4
504
5053: bf cr7*4+0,4f
506err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
507err3; lwz r7,4(r4)
508 addi r4,r4,8
509err3; stw r0,0(r3)
510err3; stw r7,4(r3)
511 addi r3,r3,8
512
5134: sub r5,r5,r6
514
515 /* Get the desination 128B aligned */
516 neg r6,r3
517 srdi r7,r6,4
518 mtocrf 0x01,r7
519 clrldi r6,r6,(64-7)
520
521 li r9,16
522 li r10,32
523 li r11,48
524
525 lvsl vr16,0,r4 /* Setup permute control vector */
526err3; lvx vr0,0,r4
527 addi r4,r4,16
528
529 bf cr7*4+3,5f
530err3; lvx vr1,r0,r4
531 vperm vr8,vr0,vr1,vr16
532 addi r4,r4,16
533err3; stvx vr8,r0,r3
534 addi r3,r3,16
535 vor vr0,vr1,vr1
536
5375: bf cr7*4+2,6f
538err3; lvx vr1,r0,r4
539 vperm vr8,vr0,vr1,vr16
540err3; lvx vr0,r4,r9
541 vperm vr9,vr1,vr0,vr16
542 addi r4,r4,32
543err3; stvx vr8,r0,r3
544err3; stvx vr9,r3,r9
545 addi r3,r3,32
546
5476: bf cr7*4+1,7f
548err3; lvx vr3,r0,r4
549 vperm vr8,vr0,vr3,vr16
550err3; lvx vr2,r4,r9
551 vperm vr9,vr3,vr2,vr16
552err3; lvx vr1,r4,r10
553 vperm vr10,vr2,vr1,vr16
554err3; lvx vr0,r4,r11
555 vperm vr11,vr1,vr0,vr16
556 addi r4,r4,64
557err3; stvx vr8,r0,r3
558err3; stvx vr9,r3,r9
559err3; stvx vr10,r3,r10
560err3; stvx vr11,r3,r11
561 addi r3,r3,64
562
5637: sub r5,r5,r6
564 srdi r6,r5,7
565
566 std r14,STK_REG(r14)(r1)
567 std r15,STK_REG(r15)(r1)
568 std r16,STK_REG(r16)(r1)
569
570 li r12,64
571 li r14,80
572 li r15,96
573 li r16,112
574
575 mtctr r6
576
577 /*
578 * Now do cacheline sized loads and stores. By this stage the
579 * cacheline stores are also cacheline aligned.
580 */
581 .align 5
5828:
583err4; lvx vr7,r0,r4
584 vperm vr8,vr0,vr7,vr16
585err4; lvx vr6,r4,r9
586 vperm vr9,vr7,vr6,vr16
587err4; lvx vr5,r4,r10
588 vperm vr10,vr6,vr5,vr16
589err4; lvx vr4,r4,r11
590 vperm vr11,vr5,vr4,vr16
591err4; lvx vr3,r4,r12
592 vperm vr12,vr4,vr3,vr16
593err4; lvx vr2,r4,r14
594 vperm vr13,vr3,vr2,vr16
595err4; lvx vr1,r4,r15
596 vperm vr14,vr2,vr1,vr16
597err4; lvx vr0,r4,r16
598 vperm vr15,vr1,vr0,vr16
599 addi r4,r4,128
600err4; stvx vr8,r0,r3
601err4; stvx vr9,r3,r9
602err4; stvx vr10,r3,r10
603err4; stvx vr11,r3,r11
604err4; stvx vr12,r3,r12
605err4; stvx vr13,r3,r14
606err4; stvx vr14,r3,r15
607err4; stvx vr15,r3,r16
608 addi r3,r3,128
609 bdnz 8b
610
611 ld r14,STK_REG(r14)(r1)
612 ld r15,STK_REG(r15)(r1)
613 ld r16,STK_REG(r16)(r1)
614
615 /* Up to 127B to go */
616 clrldi r5,r5,(64-7)
617 srdi r6,r5,4
618 mtocrf 0x01,r6
619
620 bf cr7*4+1,9f
621err3; lvx vr3,r0,r4
622 vperm vr8,vr0,vr3,vr16
623err3; lvx vr2,r4,r9
624 vperm vr9,vr3,vr2,vr16
625err3; lvx vr1,r4,r10
626 vperm vr10,vr2,vr1,vr16
627err3; lvx vr0,r4,r11
628 vperm vr11,vr1,vr0,vr16
629 addi r4,r4,64
630err3; stvx vr8,r0,r3
631err3; stvx vr9,r3,r9
632err3; stvx vr10,r3,r10
633err3; stvx vr11,r3,r11
634 addi r3,r3,64
635
6369: bf cr7*4+2,10f
637err3; lvx vr1,r0,r4
638 vperm vr8,vr0,vr1,vr16
639err3; lvx vr0,r4,r9
640 vperm vr9,vr1,vr0,vr16
641 addi r4,r4,32
642err3; stvx vr8,r0,r3
643err3; stvx vr9,r3,r9
644 addi r3,r3,32
645
64610: bf cr7*4+3,11f
647err3; lvx vr1,r0,r4
648 vperm vr8,vr0,vr1,vr16
649 addi r4,r4,16
650err3; stvx vr8,r0,r3
651 addi r3,r3,16
652
653 /* Up to 15B to go */
65411: clrldi r5,r5,(64-4)
655 addi r4,r4,-16 /* Unwind the +16 load offset */
656 mtocrf 0x01,r5
657 bf cr7*4+0,12f
658err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
659err3; lwz r6,4(r4)
660 addi r4,r4,8
661err3; stw r0,0(r3)
662err3; stw r6,4(r3)
663 addi r3,r3,8
664
66512: bf cr7*4+1,13f
666err3; lwz r0,0(r4)
667 addi r4,r4,4
668err3; stw r0,0(r3)
669 addi r3,r3,4
670
67113: bf cr7*4+2,14f
672err3; lhz r0,0(r4)
673 addi r4,r4,2
674err3; sth r0,0(r3)
675 addi r3,r3,2
676
67714: bf cr7*4+3,15f
678err3; lbz r0,0(r4)
679err3; stb r0,0(r3)
680
68115: addi r1,r1,STACKFRAMESIZE
682 b .exit_vmx_copy /* tail call optimise */
683#endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/copyuser_power7_vmx.c b/arch/powerpc/lib/copyuser_power7_vmx.c
new file mode 100644
index 00000000000..6e1efadac48
--- /dev/null
+++ b/arch/powerpc/lib/copyuser_power7_vmx.c
@@ -0,0 +1,50 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) IBM Corporation, 2011
17 *
18 * Authors: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
19 * Anton Blanchard <anton@au.ibm.com>
20 */
21#include <linux/uaccess.h>
22#include <linux/hardirq.h>
23
24int enter_vmx_copy(void)
25{
26 if (in_interrupt())
27 return 0;
28
29 /* This acts as preempt_disable() as well and will make
30 * enable_kernel_altivec(). We need to disable page faults
31 * as they can call schedule and thus make us lose the VMX
32 * context. So on page faults, we just fail which will cause
33 * a fallback to the normal non-vmx copy.
34 */
35 pagefault_disable();
36
37 enable_kernel_altivec();
38
39 return 1;
40}
41
42/*
43 * This function must return 0 because we tail call optimise when calling
44 * from __copy_tofrom_user_power7 which returns 0 on success.
45 */
46int exit_vmx_copy(void)
47{
48 pagefault_enable();
49 return 0;
50}
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index f60e006d90c..388b95e1a00 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -78,11 +78,7 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
78 "tlbwe %1,%3,%5\n" 78 "tlbwe %1,%3,%5\n"
79 "tlbwe %0,%3,%6\n" 79 "tlbwe %0,%3,%6\n"
80 : 80 :
81#ifdef CONFIG_PPC47x
82 : "r" (PPC47x_TLB2_S_RWX),
83#else
84 : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), 81 : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
85#endif
86 "r" (phys), 82 "r" (phys),
87 "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M), 83 "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
88 "r" (entry), 84 "r" (entry),
@@ -221,7 +217,7 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
221{ 217{
222 u64 size; 218 u64 size;
223 219
224#ifndef CONFIG_RELOCATABLE 220#ifndef CONFIG_NONSTATIC_KERNEL
225 /* We don't currently support the first MEMBLOCK not mapping 0 221 /* We don't currently support the first MEMBLOCK not mapping 0
226 * physical on those processors 222 * physical on those processors
227 */ 223 */
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 991ee813d2a..3787b61f7d2 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
21obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ 21obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
22 tlb_hash$(CONFIG_WORD_SIZE).o \ 22 tlb_hash$(CONFIG_WORD_SIZE).o \
23 mmu_context_hash$(CONFIG_WORD_SIZE).o 23 mmu_context_hash$(CONFIG_WORD_SIZE).o
24obj-$(CONFIG_PPC_ICSWX) += icswx.o
25obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o
24obj-$(CONFIG_40x) += 40x_mmu.o 26obj-$(CONFIG_40x) += 40x_mmu.o
25obj-$(CONFIG_44x) += 44x_mmu.o 27obj-$(CONFIG_44x) += 44x_mmu.o
26obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o 28obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c96d37..2f0d1b032a8 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -44,6 +44,8 @@
44#include <asm/siginfo.h> 44#include <asm/siginfo.h>
45#include <mm/mmu_decl.h> 45#include <mm/mmu_decl.h>
46 46
47#include "icswx.h"
48
47#ifdef CONFIG_KPROBES 49#ifdef CONFIG_KPROBES
48static inline int notify_page_fault(struct pt_regs *regs) 50static inline int notify_page_fault(struct pt_regs *regs)
49{ 51{
@@ -143,6 +145,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
143 is_write = error_code & ESR_DST; 145 is_write = error_code & ESR_DST;
144#endif /* CONFIG_4xx || CONFIG_BOOKE */ 146#endif /* CONFIG_4xx || CONFIG_BOOKE */
145 147
148#ifdef CONFIG_PPC_ICSWX
149 /*
150 * we need to do this early because this "data storage
151 * interrupt" does not update the DAR/DEAR so we don't want to
152 * look at it
153 */
154 if (error_code & ICSWX_DSI_UCT) {
155 int ret;
156
157 ret = acop_handle_fault(regs, address, error_code);
158 if (ret)
159 return ret;
160 }
161#endif
162
146 if (notify_page_fault(regs)) 163 if (notify_page_fault(regs))
147 return 0; 164 return 0;
148 165
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 343ad0b8726..3bc700655fc 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -37,31 +37,32 @@ static inline int book3e_tlb_exists(unsigned long ea, unsigned long pid)
37 return found; 37 return found;
38} 38}
39 39
40void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte) 40void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
41 pte_t pte)
41{ 42{
42 unsigned long mas1, mas2; 43 unsigned long mas1, mas2;
43 u64 mas7_3; 44 u64 mas7_3;
44 unsigned long psize, tsize, shift; 45 unsigned long psize, tsize, shift;
45 unsigned long flags; 46 unsigned long flags;
47 struct mm_struct *mm;
46 48
47#ifdef CONFIG_PPC_FSL_BOOK3E 49#ifdef CONFIG_PPC_FSL_BOOK3E
48 int index, lz, ncams; 50 int index, ncams;
49 struct vm_area_struct *vma;
50#endif 51#endif
51 52
52 if (unlikely(is_kernel_addr(ea))) 53 if (unlikely(is_kernel_addr(ea)))
53 return; 54 return;
54 55
56 mm = vma->vm_mm;
57
55#ifdef CONFIG_PPC_MM_SLICES 58#ifdef CONFIG_PPC_MM_SLICES
56 psize = mmu_get_tsize(get_slice_psize(mm, ea)); 59 psize = get_slice_psize(mm, ea);
57 tsize = mmu_get_psize(psize); 60 tsize = mmu_get_tsize(psize);
58 shift = mmu_psize_defs[psize].shift; 61 shift = mmu_psize_defs[psize].shift;
59#else 62#else
60 vma = find_vma(mm, ea); 63 psize = vma_mmu_pagesize(vma);
61 psize = vma_mmu_pagesize(vma); /* returns actual size in bytes */ 64 shift = __ilog2(psize);
62 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize)); 65 tsize = shift - 10;
63 shift = 31 - lz;
64 tsize = 21 - lz;
65#endif 66#endif
66 67
67 /* 68 /*
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 8558b572e55..a8b3cc7d90f 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -29,22 +29,22 @@ unsigned int HPAGE_SHIFT;
29 29
30/* 30/*
31 * Tracks gpages after the device tree is scanned and before the 31 * Tracks gpages after the device tree is scanned and before the
32 * huge_boot_pages list is ready. On 64-bit implementations, this is 32 * huge_boot_pages list is ready. On non-Freescale implementations, this is
33 * just used to track 16G pages and so is a single array. 32-bit 33 * just used to track 16G pages and so is a single array. FSL-based
34 * implementations may have more than one gpage size due to limitations 34 * implementations may have more than one gpage size, so we need multiple
35 * of the memory allocators, so we need multiple arrays 35 * arrays
36 */ 36 */
37#ifdef CONFIG_PPC64 37#ifdef CONFIG_PPC_FSL_BOOK3E
38#define MAX_NUMBER_GPAGES 1024
39static u64 gpage_freearray[MAX_NUMBER_GPAGES];
40static unsigned nr_gpages;
41#else
42#define MAX_NUMBER_GPAGES 128 38#define MAX_NUMBER_GPAGES 128
43struct psize_gpages { 39struct psize_gpages {
44 u64 gpage_list[MAX_NUMBER_GPAGES]; 40 u64 gpage_list[MAX_NUMBER_GPAGES];
45 unsigned int nr_gpages; 41 unsigned int nr_gpages;
46}; 42};
47static struct psize_gpages gpage_freearray[MMU_PAGE_COUNT]; 43static struct psize_gpages gpage_freearray[MMU_PAGE_COUNT];
44#else
45#define MAX_NUMBER_GPAGES 1024
46static u64 gpage_freearray[MAX_NUMBER_GPAGES];
47static unsigned nr_gpages;
48#endif 48#endif
49 49
50static inline int shift_to_mmu_psize(unsigned int shift) 50static inline int shift_to_mmu_psize(unsigned int shift)
@@ -115,12 +115,12 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
115 struct kmem_cache *cachep; 115 struct kmem_cache *cachep;
116 pte_t *new; 116 pte_t *new;
117 117
118#ifdef CONFIG_PPC64 118#ifdef CONFIG_PPC_FSL_BOOK3E
119 cachep = PGT_CACHE(pdshift - pshift);
120#else
121 int i; 119 int i;
122 int num_hugepd = 1 << (pshift - pdshift); 120 int num_hugepd = 1 << (pshift - pdshift);
123 cachep = hugepte_cache; 121 cachep = hugepte_cache;
122#else
123 cachep = PGT_CACHE(pdshift - pshift);
124#endif 124#endif
125 125
126 new = kmem_cache_zalloc(cachep, GFP_KERNEL|__GFP_REPEAT); 126 new = kmem_cache_zalloc(cachep, GFP_KERNEL|__GFP_REPEAT);
@@ -132,12 +132,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
132 return -ENOMEM; 132 return -ENOMEM;
133 133
134 spin_lock(&mm->page_table_lock); 134 spin_lock(&mm->page_table_lock);
135#ifdef CONFIG_PPC64 135#ifdef CONFIG_PPC_FSL_BOOK3E
136 if (!hugepd_none(*hpdp))
137 kmem_cache_free(cachep, new);
138 else
139 hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
140#else
141 /* 136 /*
142 * We have multiple higher-level entries that point to the same 137 * We have multiple higher-level entries that point to the same
143 * actual pte location. Fill in each as we go and backtrack on error. 138 * actual pte location. Fill in each as we go and backtrack on error.
@@ -156,11 +151,28 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
156 hpdp->pd = 0; 151 hpdp->pd = 0;
157 kmem_cache_free(cachep, new); 152 kmem_cache_free(cachep, new);
158 } 153 }
154#else
155 if (!hugepd_none(*hpdp))
156 kmem_cache_free(cachep, new);
157 else
158 hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
159#endif 159#endif
160 spin_unlock(&mm->page_table_lock); 160 spin_unlock(&mm->page_table_lock);
161 return 0; 161 return 0;
162} 162}
163 163
164/*
165 * These macros define how to determine which level of the page table holds
166 * the hpdp.
167 */
168#ifdef CONFIG_PPC_FSL_BOOK3E
169#define HUGEPD_PGD_SHIFT PGDIR_SHIFT
170#define HUGEPD_PUD_SHIFT PUD_SHIFT
171#else
172#define HUGEPD_PGD_SHIFT PUD_SHIFT
173#define HUGEPD_PUD_SHIFT PMD_SHIFT
174#endif
175
164pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz) 176pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
165{ 177{
166 pgd_t *pg; 178 pgd_t *pg;
@@ -173,12 +185,13 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
173 addr &= ~(sz-1); 185 addr &= ~(sz-1);
174 186
175 pg = pgd_offset(mm, addr); 187 pg = pgd_offset(mm, addr);
176 if (pshift >= PUD_SHIFT) { 188
189 if (pshift >= HUGEPD_PGD_SHIFT) {
177 hpdp = (hugepd_t *)pg; 190 hpdp = (hugepd_t *)pg;
178 } else { 191 } else {
179 pdshift = PUD_SHIFT; 192 pdshift = PUD_SHIFT;
180 pu = pud_alloc(mm, pg, addr); 193 pu = pud_alloc(mm, pg, addr);
181 if (pshift >= PMD_SHIFT) { 194 if (pshift >= HUGEPD_PUD_SHIFT) {
182 hpdp = (hugepd_t *)pu; 195 hpdp = (hugepd_t *)pu;
183 } else { 196 } else {
184 pdshift = PMD_SHIFT; 197 pdshift = PMD_SHIFT;
@@ -198,7 +211,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
198 return hugepte_offset(hpdp, addr, pdshift); 211 return hugepte_offset(hpdp, addr, pdshift);
199} 212}
200 213
201#ifdef CONFIG_PPC32 214#ifdef CONFIG_PPC_FSL_BOOK3E
202/* Build list of addresses of gigantic pages. This function is used in early 215/* Build list of addresses of gigantic pages. This function is used in early
203 * boot before the buddy or bootmem allocator is setup. 216 * boot before the buddy or bootmem allocator is setup.
204 */ 217 */
@@ -318,7 +331,7 @@ void __init reserve_hugetlb_gpages(void)
318 } 331 }
319} 332}
320 333
321#else /* PPC64 */ 334#else /* !PPC_FSL_BOOK3E */
322 335
323/* Build list of addresses of gigantic pages. This function is used in early 336/* Build list of addresses of gigantic pages. This function is used in early
324 * boot before the buddy or bootmem allocator is setup. 337 * boot before the buddy or bootmem allocator is setup.
@@ -356,7 +369,7 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
356 return 0; 369 return 0;
357} 370}
358 371
359#ifdef CONFIG_PPC32 372#ifdef CONFIG_PPC_FSL_BOOK3E
360#define HUGEPD_FREELIST_SIZE \ 373#define HUGEPD_FREELIST_SIZE \
361 ((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t)) 374 ((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t))
362 375
@@ -416,11 +429,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
416 unsigned long pdmask = ~((1UL << pdshift) - 1); 429 unsigned long pdmask = ~((1UL << pdshift) - 1);
417 unsigned int num_hugepd = 1; 430 unsigned int num_hugepd = 1;
418 431
419#ifdef CONFIG_PPC64 432#ifdef CONFIG_PPC_FSL_BOOK3E
420 unsigned int shift = hugepd_shift(*hpdp); 433 /* Note: On fsl the hpdp may be the first of several */
421#else
422 /* Note: On 32-bit the hpdp may be the first of several */
423 num_hugepd = (1 << (hugepd_shift(*hpdp) - pdshift)); 434 num_hugepd = (1 << (hugepd_shift(*hpdp) - pdshift));
435#else
436 unsigned int shift = hugepd_shift(*hpdp);
424#endif 437#endif
425 438
426 start &= pdmask; 439 start &= pdmask;
@@ -438,10 +451,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
438 hpdp->pd = 0; 451 hpdp->pd = 0;
439 452
440 tlb->need_flush = 1; 453 tlb->need_flush = 1;
441#ifdef CONFIG_PPC64 454
442 pgtable_free_tlb(tlb, hugepte, pdshift - shift); 455#ifdef CONFIG_PPC_FSL_BOOK3E
443#else
444 hugepd_free(tlb, hugepte); 456 hugepd_free(tlb, hugepte);
457#else
458 pgtable_free_tlb(tlb, hugepte, pdshift - shift);
445#endif 459#endif
446} 460}
447 461
@@ -454,14 +468,23 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
454 unsigned long start; 468 unsigned long start;
455 469
456 start = addr; 470 start = addr;
457 pmd = pmd_offset(pud, addr);
458 do { 471 do {
472 pmd = pmd_offset(pud, addr);
459 next = pmd_addr_end(addr, end); 473 next = pmd_addr_end(addr, end);
460 if (pmd_none(*pmd)) 474 if (pmd_none(*pmd))
461 continue; 475 continue;
476#ifdef CONFIG_PPC_FSL_BOOK3E
477 /*
478 * Increment next by the size of the huge mapping since
479 * there may be more than one entry at this level for a
480 * single hugepage, but all of them point to
481 * the same kmem cache that holds the hugepte.
482 */
483 next = addr + (1 << hugepd_shift(*(hugepd_t *)pmd));
484#endif
462 free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT, 485 free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT,
463 addr, next, floor, ceiling); 486 addr, next, floor, ceiling);
464 } while (pmd++, addr = next, addr != end); 487 } while (addr = next, addr != end);
465 488
466 start &= PUD_MASK; 489 start &= PUD_MASK;
467 if (start < floor) 490 if (start < floor)
@@ -488,8 +511,8 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
488 unsigned long start; 511 unsigned long start;
489 512
490 start = addr; 513 start = addr;
491 pud = pud_offset(pgd, addr);
492 do { 514 do {
515 pud = pud_offset(pgd, addr);
493 next = pud_addr_end(addr, end); 516 next = pud_addr_end(addr, end);
494 if (!is_hugepd(pud)) { 517 if (!is_hugepd(pud)) {
495 if (pud_none_or_clear_bad(pud)) 518 if (pud_none_or_clear_bad(pud))
@@ -497,10 +520,19 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
497 hugetlb_free_pmd_range(tlb, pud, addr, next, floor, 520 hugetlb_free_pmd_range(tlb, pud, addr, next, floor,
498 ceiling); 521 ceiling);
499 } else { 522 } else {
523#ifdef CONFIG_PPC_FSL_BOOK3E
524 /*
525 * Increment next by the size of the huge mapping since
526 * there may be more than one entry at this level for a
527 * single hugepage, but all of them point to
528 * the same kmem cache that holds the hugepte.
529 */
530 next = addr + (1 << hugepd_shift(*(hugepd_t *)pud));
531#endif
500 free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT, 532 free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT,
501 addr, next, floor, ceiling); 533 addr, next, floor, ceiling);
502 } 534 }
503 } while (pud++, addr = next, addr != end); 535 } while (addr = next, addr != end);
504 536
505 start &= PGDIR_MASK; 537 start &= PGDIR_MASK;
506 if (start < floor) 538 if (start < floor)
@@ -555,12 +587,12 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
555 continue; 587 continue;
556 hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling); 588 hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
557 } else { 589 } else {
558#ifdef CONFIG_PPC32 590#ifdef CONFIG_PPC_FSL_BOOK3E
559 /* 591 /*
560 * Increment next by the size of the huge mapping since 592 * Increment next by the size of the huge mapping since
561 * on 32-bit there may be more than one entry at the pgd 593 * there may be more than one entry at the pgd level
562 * level for a single hugepage, but all of them point to 594 * for a single hugepage, but all of them point to the
563 * the same kmem cache that holds the hugepte. 595 * same kmem cache that holds the hugepte.
564 */ 596 */
565 next = addr + (1 << hugepd_shift(*(hugepd_t *)pgd)); 597 next = addr + (1 << hugepd_shift(*(hugepd_t *)pgd));
566#endif 598#endif
@@ -698,19 +730,17 @@ int gup_hugepd(hugepd_t *hugepd, unsigned pdshift,
698 return 1; 730 return 1;
699} 731}
700 732
733#ifdef CONFIG_PPC_MM_SLICES
701unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, 734unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
702 unsigned long len, unsigned long pgoff, 735 unsigned long len, unsigned long pgoff,
703 unsigned long flags) 736 unsigned long flags)
704{ 737{
705#ifdef CONFIG_PPC_MM_SLICES
706 struct hstate *hstate = hstate_file(file); 738 struct hstate *hstate = hstate_file(file);
707 int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate)); 739 int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
708 740
709 return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0); 741 return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
710#else
711 return get_unmapped_area(file, addr, len, pgoff, flags);
712#endif
713} 742}
743#endif
714 744
715unsigned long vma_mmu_pagesize(struct vm_area_struct *vma) 745unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
716{ 746{
@@ -784,7 +814,7 @@ static int __init hugepage_setup_sz(char *str)
784} 814}
785__setup("hugepagesz=", hugepage_setup_sz); 815__setup("hugepagesz=", hugepage_setup_sz);
786 816
787#ifdef CONFIG_FSL_BOOKE 817#ifdef CONFIG_PPC_FSL_BOOK3E
788struct kmem_cache *hugepte_cache; 818struct kmem_cache *hugepte_cache;
789static int __init hugetlbpage_init(void) 819static int __init hugetlbpage_init(void)
790{ 820{
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 00000000000..5d9a59eaad9
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,273 @@
1/*
2 * ICSWX and ACOP Management
3 *
4 * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/types.h>
17#include <linux/mm.h>
18#include <linux/spinlock.h>
19#include <linux/module.h>
20#include <linux/uaccess.h>
21
22#include "icswx.h"
23
24/*
25 * The processor and its L2 cache cause the icswx instruction to
26 * generate a COP_REQ transaction on PowerBus. The transaction has no
27 * address, and the processor does not perform an MMU access to
28 * authenticate the transaction. The command portion of the PowerBus
29 * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
30 * Process ID (PID), which the coprocessor compares to the authorized
31 * LPID and PID held in the coprocessor, to determine if the process
32 * is authorized to generate the transaction. The data of the COP_REQ
33 * transaction is 128-byte or less in size and is placed in cacheable
34 * memory on a 128-byte cache line boundary.
35 *
36 * The task to use a coprocessor should use use_cop() to mark the use
37 * of the Coprocessor Type (CT) and context switching. On a server
38 * class processor, the PID register is used only for coprocessor
39 * management + * and so a coprocessor PID is allocated before
40 * executing icswx + * instruction. Drop_cop() is used to free the
41 * coprocessor PID.
42 *
43 * Example:
44 * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
45 * Each HFI have multiple windows. Each HFI window serves as a
46 * network device sending to and receiving from HFI network.
47 * HFI immediate send function uses icswx instruction. The immediate
48 * send function allows small (single cache-line) packets be sent
49 * without using the regular HFI send FIFO and doorbell, which are
50 * much slower than immediate send.
51 *
52 * For each task intending to use HFI immediate send, the HFI driver
53 * calls use_cop() to obtain a coprocessor PID for the task.
54 * The HFI driver then allocate a free HFI window and save the
55 * coprocessor PID to the HFI window to allow the task to use the
56 * HFI window.
57 *
58 * The HFI driver repeatedly creates immediate send packets and
59 * issues icswx instruction to send data through the HFI window.
60 * The HFI compares the coprocessor PID in the CPU PID register
61 * to the PID held in the HFI window to determine if the transaction
62 * is allowed.
63 *
64 * When the task to release the HFI window, the HFI driver calls
65 * drop_cop() to release the coprocessor PID.
66 */
67
68void switch_cop(struct mm_struct *next)
69{
70#ifdef CONFIG_ICSWX_PID
71 mtspr(SPRN_PID, next->context.cop_pid);
72#endif
73 mtspr(SPRN_ACOP, next->context.acop);
74}
75
76/**
77 * Start using a coprocessor.
78 * @acop: mask of coprocessor to be used.
79 * @mm: The mm the coprocessor to associate with. Most likely current mm.
80 *
81 * Return a positive PID if successful. Negative errno otherwise.
82 * The returned PID will be fed to the coprocessor to determine if an
83 * icswx transaction is authenticated.
84 */
85int use_cop(unsigned long acop, struct mm_struct *mm)
86{
87 int ret;
88
89 if (!cpu_has_feature(CPU_FTR_ICSWX))
90 return -ENODEV;
91
92 if (!mm || !acop)
93 return -EINVAL;
94
95 /* The page_table_lock ensures mm_users won't change under us */
96 spin_lock(&mm->page_table_lock);
97 spin_lock(mm->context.cop_lockp);
98
99 ret = get_cop_pid(mm);
100 if (ret < 0)
101 goto out;
102
103 /* update acop */
104 mm->context.acop |= acop;
105
106 sync_cop(mm);
107
108 /*
109 * If this is a threaded process then there might be other threads
110 * running. We need to send an IPI to force them to pick up any
111 * change in PID and ACOP.
112 */
113 if (atomic_read(&mm->mm_users) > 1)
114 smp_call_function(sync_cop, mm, 1);
115
116out:
117 spin_unlock(mm->context.cop_lockp);
118 spin_unlock(&mm->page_table_lock);
119
120 return ret;
121}
122EXPORT_SYMBOL_GPL(use_cop);
123
124/**
125 * Stop using a coprocessor.
126 * @acop: mask of coprocessor to be stopped.
127 * @mm: The mm the coprocessor associated with.
128 */
129void drop_cop(unsigned long acop, struct mm_struct *mm)
130{
131 int free_pid;
132
133 if (!cpu_has_feature(CPU_FTR_ICSWX))
134 return;
135
136 if (WARN_ON_ONCE(!mm))
137 return;
138
139 /* The page_table_lock ensures mm_users won't change under us */
140 spin_lock(&mm->page_table_lock);
141 spin_lock(mm->context.cop_lockp);
142
143 mm->context.acop &= ~acop;
144
145 free_pid = disable_cop_pid(mm);
146 sync_cop(mm);
147
148 /*
149 * If this is a threaded process then there might be other threads
150 * running. We need to send an IPI to force them to pick up any
151 * change in PID and ACOP.
152 */
153 if (atomic_read(&mm->mm_users) > 1)
154 smp_call_function(sync_cop, mm, 1);
155
156 if (free_pid != COP_PID_NONE)
157 free_cop_pid(free_pid);
158
159 spin_unlock(mm->context.cop_lockp);
160 spin_unlock(&mm->page_table_lock);
161}
162EXPORT_SYMBOL_GPL(drop_cop);
163
164static int acop_use_cop(int ct)
165{
166 /* todo */
167 return -1;
168}
169
170/*
171 * Get the instruction word at the NIP
172 */
173static u32 acop_get_inst(struct pt_regs *regs)
174{
175 u32 inst;
176 u32 __user *p;
177
178 p = (u32 __user *)regs->nip;
179 if (!access_ok(VERIFY_READ, p, sizeof(*p)))
180 return 0;
181
182 if (__get_user(inst, p))
183 return 0;
184
185 return inst;
186}
187
188/**
189 * @regs: regsiters at time of interrupt
190 * @address: storage address
191 * @error_code: Fault code, usually the DSISR or ESR depending on
192 * processor type
193 *
194 * Return 0 if we are able to resolve the data storage fault that
195 * results from a CT miss in the ACOP register.
196 */
197int acop_handle_fault(struct pt_regs *regs, unsigned long address,
198 unsigned long error_code)
199{
200 int ct;
201 u32 inst = 0;
202
203 if (!cpu_has_feature(CPU_FTR_ICSWX)) {
204 pr_info("No coprocessors available");
205 _exception(SIGILL, regs, ILL_ILLOPN, address);
206 }
207
208 if (!user_mode(regs)) {
209 /* this could happen if the HV denies the
210 * kernel access, for now we just die */
211 die("ICSWX from kernel failed", regs, SIGSEGV);
212 }
213
214 /* Some implementations leave us a hint for the CT */
215 ct = ICSWX_GET_CT_HINT(error_code);
216 if (ct < 0) {
217 /* we have to peek at the instruction word to figure out CT */
218 u32 ccw;
219 u32 rs;
220
221 inst = acop_get_inst(regs);
222 if (inst == 0)
223 return -1;
224
225 rs = (inst >> (31 - 10)) & 0x1f;
226 ccw = regs->gpr[rs];
227 ct = (ccw >> 16) & 0x3f;
228 }
229
230 if (!acop_use_cop(ct))
231 return 0;
232
233 /* at this point the CT is unknown to the system */
234 pr_warn("%s[%d]: Coprocessor %d is unavailable",
235 current->comm, current->pid, ct);
236
237 /* get inst if we don't already have it */
238 if (inst == 0) {
239 inst = acop_get_inst(regs);
240 if (inst == 0)
241 return -1;
242 }
243
244 /* Check if the instruction is the "record form" */
245 if (inst & 1) {
246 /*
247 * the instruction is "record" form so we can reject
248 * using CR0
249 */
250 regs->ccr &= ~(0xful << 28);
251 regs->ccr |= ICSWX_RC_NOT_FOUND << 28;
252
253 /* Move on to the next instruction */
254 regs->nip += 4;
255 } else {
256 /*
257 * There is no architected mechanism to report a bad
258 * CT so we could either SIGILL or report nothing.
259 * Since the non-record version should only bu used
260 * for "hints" or "don't care" we should probably do
261 * nothing. However, I could see how some people
262 * might want an SIGILL so it here if you want it.
263 */
264#ifdef CONFIG_PPC_ICSWX_USE_SIGILL
265 _exception(SIGILL, regs, ILL_ILLOPN, address);
266#else
267 regs->nip += 4;
268#endif
269 }
270
271 return 0;
272}
273EXPORT_SYMBOL_GPL(acop_handle_fault);
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
new file mode 100644
index 00000000000..42176bd0884
--- /dev/null
+++ b/arch/powerpc/mm/icswx.h
@@ -0,0 +1,62 @@
1#ifndef _ARCH_POWERPC_MM_ICSWX_H_
2#define _ARCH_POWERPC_MM_ICSWX_H_
3
4/*
5 * ICSWX and ACOP Management
6 *
7 * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 */
15
16#include <asm/mmu_context.h>
17
18/* also used to denote that PIDs are not used */
19#define COP_PID_NONE 0
20
21static inline void sync_cop(void *arg)
22{
23 struct mm_struct *mm = arg;
24
25 if (mm == current->active_mm)
26 switch_cop(current->active_mm);
27}
28
29#ifdef CONFIG_PPC_ICSWX_PID
30extern int get_cop_pid(struct mm_struct *mm);
31extern int disable_cop_pid(struct mm_struct *mm);
32extern void free_cop_pid(int free_pid);
33#else
34#define get_cop_pid(m) (COP_PID_NONE)
35#define disable_cop_pid(m) (COP_PID_NONE)
36#define free_cop_pid(p)
37#endif
38
39/*
40 * These are implementation bits for architected registers. If this
41 * ever becomes architecture the should be moved to reg.h et. al.
42 */
43/* UCT is the same bit for Server and Embedded */
44#define ICSWX_DSI_UCT 0x00004000 /* Unavailable Coprocessor Type */
45
46#ifdef CONFIG_PPC_BOOK3E
47/* Embedded implementation gives us no hints as to what the CT is */
48#define ICSWX_GET_CT_HINT(x) (-1)
49#else
50/* Server implementation contains the CT value in the DSISR */
51#define ICSWX_DSISR_CTMASK 0x00003f00
52#define ICSWX_GET_CT_HINT(x) (((x) & ICSWX_DSISR_CTMASK) >> 8)
53#endif
54
55#define ICSWX_RC_STARTED 0x8 /* The request has been started */
56#define ICSWX_RC_NOT_IDLE 0x4 /* No coprocessor found idle */
57#define ICSWX_RC_NOT_FOUND 0x2 /* No coprocessor found */
58#define ICSWX_RC_UNDEFINED 0x1 /* Reserved */
59
60extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
61 unsigned long error_code);
62#endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
diff --git a/arch/powerpc/mm/icswx_pid.c b/arch/powerpc/mm/icswx_pid.c
new file mode 100644
index 00000000000..91e30eb7d05
--- /dev/null
+++ b/arch/powerpc/mm/icswx_pid.c
@@ -0,0 +1,87 @@
1/*
2 * ICSWX and ACOP/PID Management
3 *
4 * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/types.h>
17#include <linux/mm.h>
18#include <linux/spinlock.h>
19#include <linux/idr.h>
20#include <linux/module.h>
21#include "icswx.h"
22
23#define COP_PID_MIN (COP_PID_NONE + 1)
24#define COP_PID_MAX (0xFFFF)
25
26static DEFINE_SPINLOCK(mmu_context_acop_lock);
27static DEFINE_IDA(cop_ida);
28
29static int new_cop_pid(struct ida *ida, int min_id, int max_id,
30 spinlock_t *lock)
31{
32 int index;
33 int err;
34
35again:
36 if (!ida_pre_get(ida, GFP_KERNEL))
37 return -ENOMEM;
38
39 spin_lock(lock);
40 err = ida_get_new_above(ida, min_id, &index);
41 spin_unlock(lock);
42
43 if (err == -EAGAIN)
44 goto again;
45 else if (err)
46 return err;
47
48 if (index > max_id) {
49 spin_lock(lock);
50 ida_remove(ida, index);
51 spin_unlock(lock);
52 return -ENOMEM;
53 }
54
55 return index;
56}
57
58int get_cop_pid(struct mm_struct *mm)
59{
60 int pid;
61
62 if (mm->context.cop_pid == COP_PID_NONE) {
63 pid = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
64 &mmu_context_acop_lock);
65 if (pid >= 0)
66 mm->context.cop_pid = pid;
67 }
68 return mm->context.cop_pid;
69}
70
71int disable_cop_pid(struct mm_struct *mm)
72{
73 int free_pid = COP_PID_NONE;
74
75 if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
76 free_pid = mm->context.cop_pid;
77 mm->context.cop_pid = COP_PID_NONE;
78 }
79 return free_pid;
80}
81
82void free_cop_pid(int free_pid)
83{
84 spin_lock(&mmu_context_acop_lock);
85 ida_remove(&cop_ida, free_pid);
86 spin_unlock(&mmu_context_acop_lock);
87}
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 58861fa1220..6157be2a704 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -65,6 +65,13 @@ phys_addr_t memstart_addr = (phys_addr_t)~0ull;
65EXPORT_SYMBOL(memstart_addr); 65EXPORT_SYMBOL(memstart_addr);
66phys_addr_t kernstart_addr; 66phys_addr_t kernstart_addr;
67EXPORT_SYMBOL(kernstart_addr); 67EXPORT_SYMBOL(kernstart_addr);
68
69#ifdef CONFIG_RELOCATABLE_PPC32
70/* Used in __va()/__pa() */
71long long virt_phys_offset;
72EXPORT_SYMBOL(virt_phys_offset);
73#endif
74
68phys_addr_t lowmem_end_addr; 75phys_addr_t lowmem_end_addr;
69 76
70int boot_mapsize; 77int boot_mapsize;
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 8e2eb6611b0..d974b79a306 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -51,6 +51,7 @@
51#include <asm/vdso.h> 51#include <asm/vdso.h>
52#include <asm/fixmap.h> 52#include <asm/fixmap.h>
53#include <asm/swiotlb.h> 53#include <asm/swiotlb.h>
54#include <asm/rtas.h>
54 55
55#include "mmu_decl.h" 56#include "mmu_decl.h"
56 57
@@ -553,7 +554,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
553#if (defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_PPC_FSL_BOOK3E)) \ 554#if (defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_PPC_FSL_BOOK3E)) \
554 && defined(CONFIG_HUGETLB_PAGE) 555 && defined(CONFIG_HUGETLB_PAGE)
555 if (is_vm_hugetlb_page(vma)) 556 if (is_vm_hugetlb_page(vma))
556 book3e_hugetlb_preload(vma->vm_mm, address, *ptep); 557 book3e_hugetlb_preload(vma, address, *ptep);
557#endif 558#endif
558} 559}
559 560
@@ -585,3 +586,23 @@ static int add_system_ram_resources(void)
585 return 0; 586 return 0;
586} 587}
587subsys_initcall(add_system_ram_resources); 588subsys_initcall(add_system_ram_resources);
589
590#ifdef CONFIG_STRICT_DEVMEM
591/*
592 * devmem_is_allowed(): check to see if /dev/mem access to a certain address
593 * is valid. The argument is a physical page number.
594 *
595 * Access has to be given to non-kernel-ram areas as well, these contain the
596 * PCI mmio resources as well as potential bios/acpi data regions.
597 */
598int devmem_is_allowed(unsigned long pfn)
599{
600 if (iomem_is_exclusive(pfn << PAGE_SHIFT))
601 return 0;
602 if (!page_is_ram(pfn))
603 return 1;
604 if (page_is_rtas_user_buf(pfn))
605 return 1;
606 return 0;
607}
608#endif /* CONFIG_STRICT_DEVMEM */
diff --git a/arch/powerpc/mm/mmap_64.c b/arch/powerpc/mm/mmap_64.c
index 5a783d8e8e8..67a42ed0d2f 100644
--- a/arch/powerpc/mm/mmap_64.c
+++ b/arch/powerpc/mm/mmap_64.c
@@ -53,14 +53,6 @@ static inline int mmap_is_legacy(void)
53 return sysctl_legacy_va_layout; 53 return sysctl_legacy_va_layout;
54} 54}
55 55
56/*
57 * Since get_random_int() returns the same value within a 1 jiffy window,
58 * we will almost always get the same randomisation for the stack and mmap
59 * region. This will mean the relative distance between stack and mmap will
60 * be the same.
61 *
62 * To avoid this we can shift the randomness by 1 bit.
63 */
64static unsigned long mmap_rnd(void) 56static unsigned long mmap_rnd(void)
65{ 57{
66 unsigned long rnd = 0; 58 unsigned long rnd = 0;
@@ -68,11 +60,11 @@ static unsigned long mmap_rnd(void)
68 if (current->flags & PF_RANDOMIZE) { 60 if (current->flags & PF_RANDOMIZE) {
69 /* 8MB for 32bit, 1GB for 64bit */ 61 /* 8MB for 32bit, 1GB for 64bit */
70 if (is_32bit_task()) 62 if (is_32bit_task())
71 rnd = (long)(get_random_int() % (1<<(22-PAGE_SHIFT))); 63 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
72 else 64 else
73 rnd = (long)(get_random_int() % (1<<(29-PAGE_SHIFT))); 65 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
74 } 66 }
75 return (rnd << PAGE_SHIFT) * 2; 67 return rnd << PAGE_SHIFT;
76} 68}
77 69
78static inline unsigned long mmap_base(void) 70static inline unsigned long mmap_base(void)
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index ca988a3d5fb..40677aa0190 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -24,200 +24,7 @@
24 24
25#include <asm/mmu_context.h> 25#include <asm/mmu_context.h>
26 26
27#ifdef CONFIG_PPC_ICSWX 27#include "icswx.h"
28/*
29 * The processor and its L2 cache cause the icswx instruction to
30 * generate a COP_REQ transaction on PowerBus. The transaction has
31 * no address, and the processor does not perform an MMU access
32 * to authenticate the transaction. The command portion of the
33 * PowerBus COP_REQ transaction includes the LPAR_ID (LPID) and
34 * the coprocessor Process ID (PID), which the coprocessor compares
35 * to the authorized LPID and PID held in the coprocessor, to determine
36 * if the process is authorized to generate the transaction.
37 * The data of the COP_REQ transaction is 128-byte or less and is
38 * placed in cacheable memory on a 128-byte cache line boundary.
39 *
40 * The task to use a coprocessor should use use_cop() to allocate
41 * a coprocessor PID before executing icswx instruction. use_cop()
42 * also enables the coprocessor context switching. Drop_cop() is
43 * used to free the coprocessor PID.
44 *
45 * Example:
46 * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
47 * Each HFI have multiple windows. Each HFI window serves as a
48 * network device sending to and receiving from HFI network.
49 * HFI immediate send function uses icswx instruction. The immediate
50 * send function allows small (single cache-line) packets be sent
51 * without using the regular HFI send FIFO and doorbell, which are
52 * much slower than immediate send.
53 *
54 * For each task intending to use HFI immediate send, the HFI driver
55 * calls use_cop() to obtain a coprocessor PID for the task.
56 * The HFI driver then allocate a free HFI window and save the
57 * coprocessor PID to the HFI window to allow the task to use the
58 * HFI window.
59 *
60 * The HFI driver repeatedly creates immediate send packets and
61 * issues icswx instruction to send data through the HFI window.
62 * The HFI compares the coprocessor PID in the CPU PID register
63 * to the PID held in the HFI window to determine if the transaction
64 * is allowed.
65 *
66 * When the task to release the HFI window, the HFI driver calls
67 * drop_cop() to release the coprocessor PID.
68 */
69
70#define COP_PID_NONE 0
71#define COP_PID_MIN (COP_PID_NONE + 1)
72#define COP_PID_MAX (0xFFFF)
73
74static DEFINE_SPINLOCK(mmu_context_acop_lock);
75static DEFINE_IDA(cop_ida);
76
77void switch_cop(struct mm_struct *next)
78{
79 mtspr(SPRN_PID, next->context.cop_pid);
80 mtspr(SPRN_ACOP, next->context.acop);
81}
82
83static int new_cop_pid(struct ida *ida, int min_id, int max_id,
84 spinlock_t *lock)
85{
86 int index;
87 int err;
88
89again:
90 if (!ida_pre_get(ida, GFP_KERNEL))
91 return -ENOMEM;
92
93 spin_lock(lock);
94 err = ida_get_new_above(ida, min_id, &index);
95 spin_unlock(lock);
96
97 if (err == -EAGAIN)
98 goto again;
99 else if (err)
100 return err;
101
102 if (index > max_id) {
103 spin_lock(lock);
104 ida_remove(ida, index);
105 spin_unlock(lock);
106 return -ENOMEM;
107 }
108
109 return index;
110}
111
112static void sync_cop(void *arg)
113{
114 struct mm_struct *mm = arg;
115
116 if (mm == current->active_mm)
117 switch_cop(current->active_mm);
118}
119
120/**
121 * Start using a coprocessor.
122 * @acop: mask of coprocessor to be used.
123 * @mm: The mm the coprocessor to associate with. Most likely current mm.
124 *
125 * Return a positive PID if successful. Negative errno otherwise.
126 * The returned PID will be fed to the coprocessor to determine if an
127 * icswx transaction is authenticated.
128 */
129int use_cop(unsigned long acop, struct mm_struct *mm)
130{
131 int ret;
132
133 if (!cpu_has_feature(CPU_FTR_ICSWX))
134 return -ENODEV;
135
136 if (!mm || !acop)
137 return -EINVAL;
138
139 /* The page_table_lock ensures mm_users won't change under us */
140 spin_lock(&mm->page_table_lock);
141 spin_lock(mm->context.cop_lockp);
142
143 if (mm->context.cop_pid == COP_PID_NONE) {
144 ret = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
145 &mmu_context_acop_lock);
146 if (ret < 0)
147 goto out;
148
149 mm->context.cop_pid = ret;
150 }
151 mm->context.acop |= acop;
152
153 sync_cop(mm);
154
155 /*
156 * If this is a threaded process then there might be other threads
157 * running. We need to send an IPI to force them to pick up any
158 * change in PID and ACOP.
159 */
160 if (atomic_read(&mm->mm_users) > 1)
161 smp_call_function(sync_cop, mm, 1);
162
163 ret = mm->context.cop_pid;
164
165out:
166 spin_unlock(mm->context.cop_lockp);
167 spin_unlock(&mm->page_table_lock);
168
169 return ret;
170}
171EXPORT_SYMBOL_GPL(use_cop);
172
173/**
174 * Stop using a coprocessor.
175 * @acop: mask of coprocessor to be stopped.
176 * @mm: The mm the coprocessor associated with.
177 */
178void drop_cop(unsigned long acop, struct mm_struct *mm)
179{
180 int free_pid = COP_PID_NONE;
181
182 if (!cpu_has_feature(CPU_FTR_ICSWX))
183 return;
184
185 if (WARN_ON_ONCE(!mm))
186 return;
187
188 /* The page_table_lock ensures mm_users won't change under us */
189 spin_lock(&mm->page_table_lock);
190 spin_lock(mm->context.cop_lockp);
191
192 mm->context.acop &= ~acop;
193
194 if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
195 free_pid = mm->context.cop_pid;
196 mm->context.cop_pid = COP_PID_NONE;
197 }
198
199 sync_cop(mm);
200
201 /*
202 * If this is a threaded process then there might be other threads
203 * running. We need to send an IPI to force them to pick up any
204 * change in PID and ACOP.
205 */
206 if (atomic_read(&mm->mm_users) > 1)
207 smp_call_function(sync_cop, mm, 1);
208
209 if (free_pid != COP_PID_NONE) {
210 spin_lock(&mmu_context_acop_lock);
211 ida_remove(&cop_ida, free_pid);
212 spin_unlock(&mmu_context_acop_lock);
213 }
214
215 spin_unlock(mm->context.cop_lockp);
216 spin_unlock(&mm->page_table_lock);
217}
218EXPORT_SYMBOL_GPL(drop_cop);
219
220#endif /* CONFIG_PPC_ICSWX */
221 28
222static DEFINE_SPINLOCK(mmu_context_lock); 29static DEFINE_SPINLOCK(mmu_context_lock);
223static DEFINE_IDA(mmu_context_ida); 30static DEFINE_IDA(mmu_context_ida);
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index e6eea0ac80c..c0189c169bb 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -386,7 +386,7 @@ static void __init get_n_mem_cells(int *n_addr_cells, int *n_size_cells)
386 of_node_put(memory); 386 of_node_put(memory);
387} 387}
388 388
389static unsigned long __devinit read_n_cells(int n, const unsigned int **buf) 389static unsigned long read_n_cells(int n, const unsigned int **buf)
390{ 390{
391 unsigned long result = 0; 391 unsigned long result = 0;
392 392
@@ -947,7 +947,7 @@ static struct notifier_block __cpuinitdata ppc64_numa_nb = {
947 .priority = 1 /* Must run before sched domains notifier. */ 947 .priority = 1 /* Must run before sched domains notifier. */
948}; 948};
949 949
950static void mark_reserved_regions_for_nid(int nid) 950static void __init mark_reserved_regions_for_nid(int nid)
951{ 951{
952 struct pglist_data *node = NODE_DATA(nid); 952 struct pglist_data *node = NODE_DATA(nid);
953 struct memblock_region *reg; 953 struct memblock_region *reg;
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index dc4a5f385e4..ff672bd8fea 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -94,11 +94,11 @@
94 94
95 srdi r15,r16,60 /* get region */ 95 srdi r15,r16,60 /* get region */
96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
97 bne- dtlb_miss_fault_bolted 97 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
98 98
99 rlwinm r10,r11,32-19,27,27 99 rlwinm r10,r11,32-19,27,27
100 rlwimi r10,r11,32-16,19,19 100 rlwimi r10,r11,32-16,19,19
101 cmpwi r15,0 101 cmpwi r15,0 /* user vs kernel check */
102 ori r10,r10,_PAGE_PRESENT 102 ori r10,r10,_PAGE_PRESENT
103 oris r11,r10,_PAGE_ACCESSED@h 103 oris r11,r10,_PAGE_ACCESSED@h
104 104
@@ -120,44 +120,38 @@ tlb_miss_common_bolted:
120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
121 cmpldi cr0,r14,0 121 cmpldi cr0,r14,0
122 clrrdi r15,r15,3 122 clrrdi r15,r15,3
123 beq tlb_miss_fault_bolted 123 beq tlb_miss_fault_bolted /* No PGDIR, bail */
124 124
125BEGIN_MMU_FTR_SECTION 125BEGIN_MMU_FTR_SECTION
126 /* Set the TLB reservation and search for existing entry. Then load 126 /* Set the TLB reservation and search for existing entry. Then load
127 * the entry. 127 * the entry.
128 */ 128 */
129 PPC_TLBSRX_DOT(0,r16) 129 PPC_TLBSRX_DOT(0,r16)
130 ldx r14,r14,r15 130 ldx r14,r14,r15 /* grab pgd entry */
131 beq normal_tlb_miss_done 131 beq normal_tlb_miss_done /* tlb exists already, bail */
132MMU_FTR_SECTION_ELSE 132MMU_FTR_SECTION_ELSE
133 ldx r14,r14,r15 133 ldx r14,r14,r15 /* grab pgd entry */
134ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) 134ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
135 135
136#ifndef CONFIG_PPC_64K_PAGES 136#ifndef CONFIG_PPC_64K_PAGES
137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
138 clrrdi r15,r15,3 138 clrrdi r15,r15,3
139 139 cmpdi cr0,r14,0
140 cmpldi cr0,r14,0 140 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
141 beq tlb_miss_fault_bolted 141 ldx r14,r14,r15 /* grab pud entry */
142
143 ldx r14,r14,r15
144#endif /* CONFIG_PPC_64K_PAGES */ 142#endif /* CONFIG_PPC_64K_PAGES */
145 143
146 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 144 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
147 clrrdi r15,r15,3 145 clrrdi r15,r15,3
148 146 cmpdi cr0,r14,0
149 cmpldi cr0,r14,0 147 bge tlb_miss_fault_bolted
150 beq tlb_miss_fault_bolted 148 ldx r14,r14,r15 /* Grab pmd entry */
151
152 ldx r14,r14,r15
153 149
154 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3 150 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
155 clrrdi r15,r15,3 151 clrrdi r15,r15,3
156 152 cmpdi cr0,r14,0
157 cmpldi cr0,r14,0 153 bge tlb_miss_fault_bolted
158 beq tlb_miss_fault_bolted 154 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
159
160 ldx r14,r14,r15
161 155
162 /* Check if required permissions are met */ 156 /* Check if required permissions are met */
163 andc. r15,r11,r14 157 andc. r15,r11,r14
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 573ba3b69d1..df32a838dcf 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -52,7 +52,7 @@
52 * indirect page table entries. 52 * indirect page table entries.
53 */ 53 */
54#ifdef CONFIG_PPC_BOOK3E_MMU 54#ifdef CONFIG_PPC_BOOK3E_MMU
55#ifdef CONFIG_FSL_BOOKE 55#ifdef CONFIG_PPC_FSL_BOOK3E
56struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 56struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
57 [MMU_PAGE_4K] = { 57 [MMU_PAGE_4K] = {
58 .shift = 12, 58 .shift = 12,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 153022971da..baae85584b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -100,6 +100,16 @@ config XILINX_VIRTEX_GENERIC_BOARD
100 Most Virtex designs should use this unless it needs to do some 100 Most Virtex designs should use this unless it needs to do some
101 special configuration at board probe time. 101 special configuration at board probe time.
102 102
103config OBS600
104 bool "OpenBlockS 600"
105 depends on 40x
106 default n
107 select 405EX
108 select PPC40x_SIMPLE
109 help
110 This option enables support for PlatHome OpenBlockS 600 server
111
112
103config PPC40x_SIMPLE 113config PPC40x_SIMPLE
104 bool "Simple PowerPC 40x board support" 114 bool "Simple PowerPC 40x board support"
105 depends on 40x 115 depends on 40x
@@ -186,3 +196,14 @@ config IBM405_ERR51
186# bool 196# bool
187# depends on !STB03xxx && PPC4xx_DMA 197# depends on !STB03xxx && PPC4xx_DMA
188# default y 198# default y
199#
200
201config APM8018X
202 bool "APM8018X"
203 depends on 40x
204 default n
205 select PPC40x_SIMPLE
206 help
207 This option enables support for the AppliedMicro APM8018X evaluation
208 board.
209
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index e8dd5c5df7d..97612068fae 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -55,7 +55,9 @@ static const char *board[] __initdata = {
55 "amcc,haleakala", 55 "amcc,haleakala",
56 "amcc,kilauea", 56 "amcc,kilauea",
57 "amcc,makalu", 57 "amcc,makalu",
58 "est,hotfoot" 58 "apm,klondike",
59 "est,hotfoot",
60 "plathome,obs600"
59}; 61};
60 62
61static int __init ppc40x_probe(void) 63static int __init ppc40x_probe(void)
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 762322ce24a..5d5aaf6c91a 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -186,6 +186,16 @@ config ISS4xx
186 help 186 help
187 This option enables support for the IBM ISS simulation environment 187 This option enables support for the IBM ISS simulation environment
188 188
189config CURRITUCK
190 bool "IBM Currituck (476fpe) Support"
191 depends on PPC_47x
192 default n
193 select SWIOTLB
194 select 476FPE
195 select PPC4xx_PCI_EXPRESS
196 help
197 This option enables support for the IBM Currituck (476fpe) evaluation board
198
189config ICON 199config ICON
190 bool "Icon" 200 bool "Icon"
191 depends on 44x 201 depends on 44x
@@ -308,6 +318,10 @@ config 460SX
308 select IBM_EMAC_ZMII 318 select IBM_EMAC_ZMII
309 select IBM_EMAC_TAH 319 select IBM_EMAC_TAH
310 320
321config 476FPE
322 bool
323 select PPC_FPU
324
311config APM821xx 325config APM821xx
312 bool 326 bool
313 select PPC_FPU 327 select PPC_FPU
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 553db600721..d03833abec0 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
10obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o 10obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
11obj-$(CONFIG_ISS4xx) += iss4xx.o 11obj-$(CONFIG_ISS4xx) += iss4xx.o
12obj-$(CONFIG_CANYONLANDS)+= canyonlands.o 12obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
13obj-$(CONFIG_CURRITUCK) += currituck.o
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
new file mode 100644
index 00000000000..3f6229b5dee
--- /dev/null
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -0,0 +1,204 @@
1/*
2 * Currituck board specific routines
3 *
4 * Copyright © 2011 Tony Breeds IBM Corporation
5 *
6 * Based on earlier code:
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003-2005 Zultys Technologies
12 *
13 * Rewritten and ported to the merged powerpc tree:
14 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
15 * Copyright © 2011 David Kliekamp IBM Corporation
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 */
22
23#include <linux/init.h>
24#include <linux/memblock.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/rtc.h>
28
29#include <asm/machdep.h>
30#include <asm/prom.h>
31#include <asm/udbg.h>
32#include <asm/time.h>
33#include <asm/uic.h>
34#include <asm/ppc4xx.h>
35#include <asm/mpic.h>
36#include <asm/mmu.h>
37
38#include <linux/pci.h>
39
40static __initdata struct of_device_id ppc47x_of_bus[] = {
41 { .compatible = "ibm,plb4", },
42 { .compatible = "ibm,plb6", },
43 { .compatible = "ibm,opb", },
44 { .compatible = "ibm,ebc", },
45 {},
46};
47
48/* The EEPROM is missing and the default values are bogus. This forces USB in
49 * to EHCI mode */
50static void __devinit quirk_ppc_currituck_usb_fixup(struct pci_dev *dev)
51{
52 if (of_machine_is_compatible("ibm,currituck")) {
53 pci_write_config_dword(dev, 0xe0, 0x0114231f);
54 pci_write_config_dword(dev, 0xe4, 0x00006c40);
55 }
56}
57DECLARE_PCI_FIXUP_HEADER(0x1033, 0x0035, quirk_ppc_currituck_usb_fixup);
58
59static int __init ppc47x_device_probe(void)
60{
61 of_platform_bus_probe(NULL, ppc47x_of_bus, NULL);
62
63 return 0;
64}
65machine_device_initcall(ppc47x, ppc47x_device_probe);
66
67/* We can have either UICs or MPICs */
68static void __init ppc47x_init_irq(void)
69{
70 struct device_node *np;
71
72 /* Find top level interrupt controller */
73 for_each_node_with_property(np, "interrupt-controller") {
74 if (of_get_property(np, "interrupts", NULL) == NULL)
75 break;
76 }
77 if (np == NULL)
78 panic("Can't find top level interrupt controller");
79
80 /* Check type and do appropriate initialization */
81 if (of_device_is_compatible(np, "chrp,open-pic")) {
82 /* The MPIC driver will get everything it needs from the
83 * device-tree, just pass 0 to all arguments
84 */
85 struct mpic *mpic =
86 mpic_alloc(np, 0, 0, 0, 0, " MPIC ");
87 BUG_ON(mpic == NULL);
88 mpic_init(mpic);
89 ppc_md.get_irq = mpic_get_irq;
90 } else
91 panic("Unrecognized top level interrupt controller");
92}
93
94#ifdef CONFIG_SMP
95static void __cpuinit smp_ppc47x_setup_cpu(int cpu)
96{
97 mpic_setup_this_cpu();
98}
99
100static int __cpuinit smp_ppc47x_kick_cpu(int cpu)
101{
102 struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
103 const u64 *spin_table_addr_prop;
104 u32 *spin_table;
105 extern void start_secondary_47x(void);
106
107 BUG_ON(cpunode == NULL);
108
109 /* Assume spin table. We could test for the enable-method in
110 * the device-tree but currently there's little point as it's
111 * our only supported method
112 */
113 spin_table_addr_prop =
114 of_get_property(cpunode, "cpu-release-addr", NULL);
115
116 if (spin_table_addr_prop == NULL) {
117 pr_err("CPU%d: Can't start, missing cpu-release-addr !\n",
118 cpu);
119 return 1;
120 }
121
122 /* Assume it's mapped as part of the linear mapping. This is a bit
123 * fishy but will work fine for now
124 *
125 * XXX: Is there any reason to assume differently?
126 */
127 spin_table = (u32 *)__va(*spin_table_addr_prop);
128 pr_debug("CPU%d: Spin table mapped at %p\n", cpu, spin_table);
129
130 spin_table[3] = cpu;
131 smp_wmb();
132 spin_table[1] = __pa(start_secondary_47x);
133 mb();
134
135 return 0;
136}
137
138static struct smp_ops_t ppc47x_smp_ops = {
139 .probe = smp_mpic_probe,
140 .message_pass = smp_mpic_message_pass,
141 .setup_cpu = smp_ppc47x_setup_cpu,
142 .kick_cpu = smp_ppc47x_kick_cpu,
143 .give_timebase = smp_generic_give_timebase,
144 .take_timebase = smp_generic_take_timebase,
145};
146
147static void __init ppc47x_smp_init(void)
148{
149 if (mmu_has_feature(MMU_FTR_TYPE_47x))
150 smp_ops = &ppc47x_smp_ops;
151}
152
153#else /* CONFIG_SMP */
154static void __init ppc47x_smp_init(void) { }
155#endif /* CONFIG_SMP */
156
157static void __init ppc47x_setup_arch(void)
158{
159
160 /* No need to check the DMA config as we /know/ our windows are all of
161 * RAM. Lets hope that doesn't change */
162#ifdef CONFIG_SWIOTLB
163 if (memblock_end_of_DRAM() > 0xffffffff) {
164 ppc_swiotlb_enable = 1;
165 set_pci_dma_ops(&swiotlb_dma_ops);
166 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
167 }
168#endif
169 ppc47x_smp_init();
170}
171
172/*
173 * Called very early, MMU is off, device-tree isn't unflattened
174 */
175static int __init ppc47x_probe(void)
176{
177 unsigned long root = of_get_flat_dt_root();
178
179 if (!of_flat_dt_is_compatible(root, "ibm,currituck"))
180 return 0;
181
182 return 1;
183}
184
185/* Use USB controller should have been hardware swizzled but it wasn't :( */
186static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
187{
188 if (dev->vendor == 0x1033 && (dev->device == 0x0035 ||
189 dev->device == 0x00e0)) {
190 dev->irq = irq_create_mapping(NULL, 47);
191 pr_info("%s: Mapping irq 47 %d\n", __func__, dev->irq);
192 }
193}
194
195define_machine(ppc47x) {
196 .name = "PowerPC 47x",
197 .probe = ppc47x_probe,
198 .progress = udbg_progress,
199 .init_IRQ = ppc47x_init_irq,
200 .setup_arch = ppc47x_setup_arch,
201 .pci_irq_fixup = ppc47x_pci_irq_fixup,
202 .restart = ppc4xx_reset_system,
203 .calibrate_decr = generic_calibrate_decr,
204};
diff --git a/arch/powerpc/platforms/44x/iss4xx.c b/arch/powerpc/platforms/44x/iss4xx.c
index 19395f18b1d..5b8cdbb82f8 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -71,7 +71,7 @@ static void __init iss4xx_init_irq(void)
71 /* The MPIC driver will get everything it needs from the 71 /* The MPIC driver will get everything it needs from the
72 * device-tree, just pass 0 to all arguments 72 * device-tree, just pass 0 to all arguments
73 */ 73 */
74 struct mpic *mpic = mpic_alloc(np, 0, MPIC_PRIMARY, 0, 0, 74 struct mpic *mpic = mpic_alloc(np, 0, 0, 0, 0,
75 " MPIC "); 75 " MPIC ");
76 BUG_ON(mpic == NULL); 76 BUG_ON(mpic == NULL);
77 mpic_init(mpic); 77 mpic_init(mpic);
diff --git a/arch/powerpc/platforms/83xx/asp834x.c b/arch/powerpc/platforms/83xx/asp834x.c
index aa0d84d2258..464ea8e0292 100644
--- a/arch/powerpc/platforms/83xx/asp834x.c
+++ b/arch/powerpc/platforms/83xx/asp834x.c
@@ -36,38 +36,7 @@ static void __init asp834x_setup_arch(void)
36 mpc834x_usb_cfg(); 36 mpc834x_usb_cfg();
37} 37}
38 38
39static void __init asp834x_init_IRQ(void) 39machine_device_initcall(asp834x, mpc83xx_declare_of_platform_devices);
40{
41 struct device_node *np;
42
43 np = of_find_node_by_type(NULL, "ipic");
44 if (!np)
45 return;
46
47 ipic_init(np, 0);
48
49 of_node_put(np);
50
51 /* Initialize the default interrupt mapping priorities,
52 * in case the boot rom changed something on us.
53 */
54 ipic_set_default_priority();
55}
56
57static struct __initdata of_device_id asp8347_ids[] = {
58 { .type = "soc", },
59 { .compatible = "soc", },
60 { .compatible = "simple-bus", },
61 { .compatible = "gianfar", },
62 {},
63};
64
65static int __init asp8347_declare_of_platform_devices(void)
66{
67 of_platform_bus_probe(NULL, asp8347_ids, NULL);
68 return 0;
69}
70machine_device_initcall(asp834x, asp8347_declare_of_platform_devices);
71 40
72/* 41/*
73 * Called very early, MMU is off, device-tree isn't unflattened 42 * Called very early, MMU is off, device-tree isn't unflattened
@@ -82,7 +51,7 @@ define_machine(asp834x) {
82 .name = "ASP8347E", 51 .name = "ASP8347E",
83 .probe = asp834x_probe, 52 .probe = asp834x_probe,
84 .setup_arch = asp834x_setup_arch, 53 .setup_arch = asp834x_setup_arch,
85 .init_IRQ = asp834x_init_IRQ, 54 .init_IRQ = mpc83xx_ipic_init_IRQ,
86 .get_irq = ipic_get_irq, 55 .get_irq = ipic_get_irq,
87 .restart = mpc83xx_restart, 56 .restart = mpc83xx_restart,
88 .time_init = mpc83xx_time_init, 57 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index c55129f5760..65eb792a0d0 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -51,15 +51,14 @@
51 */ 51 */
52static void __init mpc83xx_km_setup_arch(void) 52static void __init mpc83xx_km_setup_arch(void)
53{ 53{
54#ifdef CONFIG_QUICC_ENGINE
54 struct device_node *np; 55 struct device_node *np;
56#endif
55 57
56 if (ppc_md.progress) 58 if (ppc_md.progress)
57 ppc_md.progress("kmpbec83xx_setup_arch()", 0); 59 ppc_md.progress("kmpbec83xx_setup_arch()", 0);
58 60
59#ifdef CONFIG_PCI 61 mpc83xx_setup_pci();
60 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
61 mpc83xx_add_bridge(np);
62#endif
63 62
64#ifdef CONFIG_QUICC_ENGINE 63#ifdef CONFIG_QUICC_ENGINE
65 qe_reset(); 64 qe_reset();
@@ -122,54 +121,7 @@ static void __init mpc83xx_km_setup_arch(void)
122#endif /* CONFIG_QUICC_ENGINE */ 121#endif /* CONFIG_QUICC_ENGINE */
123} 122}
124 123
125static struct of_device_id kmpbec83xx_ids[] = { 124machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
126 { .type = "soc", },
127 { .compatible = "soc", },
128 { .compatible = "simple-bus", },
129 { .type = "qe", },
130 { .compatible = "fsl,qe", },
131 {},
132};
133
134static int __init kmeter_declare_of_platform_devices(void)
135{
136 /* Publish the QE devices */
137 of_platform_bus_probe(NULL, kmpbec83xx_ids, NULL);
138
139 return 0;
140}
141machine_device_initcall(mpc83xx_km, kmeter_declare_of_platform_devices);
142
143static void __init mpc83xx_km_init_IRQ(void)
144{
145 struct device_node *np;
146
147 np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic");
148 if (!np) {
149 np = of_find_node_by_type(NULL, "ipic");
150 if (!np)
151 return;
152 }
153
154 ipic_init(np, 0);
155
156 /* Initialize the default interrupt mapping priorities,
157 * in case the boot rom changed something on us.
158 */
159 ipic_set_default_priority();
160 of_node_put(np);
161
162#ifdef CONFIG_QUICC_ENGINE
163 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
164 if (!np) {
165 np = of_find_node_by_type(NULL, "qeic");
166 if (!np)
167 return;
168 }
169 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
170 of_node_put(np);
171#endif /* CONFIG_QUICC_ENGINE */
172}
173 125
174/* list of the supported boards */ 126/* list of the supported boards */
175static char *board[] __initdata = { 127static char *board[] __initdata = {
@@ -198,7 +150,7 @@ define_machine(mpc83xx_km) {
198 .name = "mpc83xx-km-platform", 150 .name = "mpc83xx-km-platform",
199 .probe = mpc83xx_km_probe, 151 .probe = mpc83xx_km_probe,
200 .setup_arch = mpc83xx_km_setup_arch, 152 .setup_arch = mpc83xx_km_setup_arch,
201 .init_IRQ = mpc83xx_km_init_IRQ, 153 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
202 .get_irq = ipic_get_irq, 154 .get_irq = ipic_get_irq,
203 .restart = mpc83xx_restart, 155 .restart = mpc83xx_restart,
204 .time_init = mpc83xx_time_init, 156 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index f01806c940e..125336f750c 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -11,10 +11,15 @@
11 11
12#include <linux/stddef.h> 12#include <linux/stddef.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/of_platform.h>
15#include <linux/pci.h>
14 16
15#include <asm/io.h> 17#include <asm/io.h>
16#include <asm/hw_irq.h> 18#include <asm/hw_irq.h>
19#include <asm/ipic.h>
20#include <asm/qe_ic.h>
17#include <sysdev/fsl_soc.h> 21#include <sysdev/fsl_soc.h>
22#include <sysdev/fsl_pci.h>
18 23
19#include "mpc83xx.h" 24#include "mpc83xx.h"
20 25
@@ -65,3 +70,75 @@ long __init mpc83xx_time_init(void)
65 70
66 return 0; 71 return 0;
67} 72}
73
74void __init mpc83xx_ipic_init_IRQ(void)
75{
76 struct device_node *np;
77
78 /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
79 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
80 if (!np)
81 np = of_find_node_by_type(NULL, "ipic");
82 if (!np)
83 return;
84
85 ipic_init(np, 0);
86
87 of_node_put(np);
88
89 /* Initialize the default interrupt mapping priorities,
90 * in case the boot rom changed something on us.
91 */
92 ipic_set_default_priority();
93}
94
95#ifdef CONFIG_QUICC_ENGINE
96void __init mpc83xx_qe_init_IRQ(void)
97{
98 struct device_node *np;
99
100 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
101 if (!np) {
102 np = of_find_node_by_type(NULL, "qeic");
103 if (!np)
104 return;
105 }
106 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
107 of_node_put(np);
108}
109
110void __init mpc83xx_ipic_and_qe_init_IRQ(void)
111{
112 mpc83xx_ipic_init_IRQ();
113 mpc83xx_qe_init_IRQ();
114}
115#endif /* CONFIG_QUICC_ENGINE */
116
117static struct of_device_id __initdata of_bus_ids[] = {
118 { .type = "soc", },
119 { .compatible = "soc", },
120 { .compatible = "simple-bus" },
121 { .compatible = "gianfar" },
122 { .compatible = "gpio-leds", },
123 { .type = "qe", },
124 { .compatible = "fsl,qe", },
125 {},
126};
127
128int __init mpc83xx_declare_of_platform_devices(void)
129{
130 of_platform_bus_probe(NULL, of_bus_ids, NULL);
131 return 0;
132}
133
134#ifdef CONFIG_PCI
135void __init mpc83xx_setup_pci(void)
136{
137 struct device_node *np;
138
139 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
140 mpc83xx_add_bridge(np);
141 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
142 mpc83xx_add_bridge(np);
143}
144#endif
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
index d0c4e15b779..4f2d9fea77b 100644
--- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -27,36 +27,13 @@
27 */ 27 */
28static void __init mpc830x_rdb_setup_arch(void) 28static void __init mpc830x_rdb_setup_arch(void)
29{ 29{
30#ifdef CONFIG_PCI
31 struct device_node *np;
32#endif
33
34 if (ppc_md.progress) 30 if (ppc_md.progress)
35 ppc_md.progress("mpc830x_rdb_setup_arch()", 0); 31 ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
36 32
37#ifdef CONFIG_PCI 33 mpc83xx_setup_pci();
38 for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
39 mpc83xx_add_bridge(np);
40#endif
41 mpc831x_usb_cfg(); 34 mpc831x_usb_cfg();
42} 35}
43 36
44static void __init mpc830x_rdb_init_IRQ(void)
45{
46 struct device_node *np;
47
48 np = of_find_node_by_type(NULL, "ipic");
49 if (!np)
50 return;
51
52 ipic_init(np, 0);
53
54 /* Initialize the default interrupt mapping priorities,
55 * in case the boot rom changed something on us.
56 */
57 ipic_set_default_priority();
58}
59
60static const char *board[] __initdata = { 37static const char *board[] __initdata = {
61 "MPC8308RDB", 38 "MPC8308RDB",
62 "fsl,mpc8308rdb", 39 "fsl,mpc8308rdb",
@@ -72,24 +49,13 @@ static int __init mpc830x_rdb_probe(void)
72 return of_flat_dt_match(of_get_flat_dt_root(), board); 49 return of_flat_dt_match(of_get_flat_dt_root(), board);
73} 50}
74 51
75static struct of_device_id __initdata of_bus_ids[] = { 52machine_device_initcall(mpc830x_rdb, mpc83xx_declare_of_platform_devices);
76 { .compatible = "simple-bus" },
77 { .compatible = "gianfar" },
78 {},
79};
80
81static int __init declare_of_platform_devices(void)
82{
83 of_platform_bus_probe(NULL, of_bus_ids, NULL);
84 return 0;
85}
86machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
87 53
88define_machine(mpc830x_rdb) { 54define_machine(mpc830x_rdb) {
89 .name = "MPC830x RDB", 55 .name = "MPC830x RDB",
90 .probe = mpc830x_rdb_probe, 56 .probe = mpc830x_rdb_probe,
91 .setup_arch = mpc830x_rdb_setup_arch, 57 .setup_arch = mpc830x_rdb_setup_arch,
92 .init_IRQ = mpc830x_rdb_init_IRQ, 58 .init_IRQ = mpc83xx_ipic_init_IRQ,
93 .get_irq = ipic_get_irq, 59 .get_irq = ipic_get_irq,
94 .restart = mpc83xx_restart, 60 .restart = mpc83xx_restart,
95 .time_init = mpc83xx_time_init, 61 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index f859ead49a8..fa25977c52d 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -28,38 +28,13 @@
28 */ 28 */
29static void __init mpc831x_rdb_setup_arch(void) 29static void __init mpc831x_rdb_setup_arch(void)
30{ 30{
31#ifdef CONFIG_PCI
32 struct device_node *np;
33#endif
34
35 if (ppc_md.progress) 31 if (ppc_md.progress)
36 ppc_md.progress("mpc831x_rdb_setup_arch()", 0); 32 ppc_md.progress("mpc831x_rdb_setup_arch()", 0);
37 33
38#ifdef CONFIG_PCI 34 mpc83xx_setup_pci();
39 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
40 mpc83xx_add_bridge(np);
41 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
42 mpc83xx_add_bridge(np);
43#endif
44 mpc831x_usb_cfg(); 35 mpc831x_usb_cfg();
45} 36}
46 37
47static void __init mpc831x_rdb_init_IRQ(void)
48{
49 struct device_node *np;
50
51 np = of_find_node_by_type(NULL, "ipic");
52 if (!np)
53 return;
54
55 ipic_init(np, 0);
56
57 /* Initialize the default interrupt mapping priorities,
58 * in case the boot rom changed something on us.
59 */
60 ipic_set_default_priority();
61}
62
63static const char *board[] __initdata = { 38static const char *board[] __initdata = {
64 "MPC8313ERDB", 39 "MPC8313ERDB",
65 "fsl,mpc8315erdb", 40 "fsl,mpc8315erdb",
@@ -74,25 +49,13 @@ static int __init mpc831x_rdb_probe(void)
74 return of_flat_dt_match(of_get_flat_dt_root(), board); 49 return of_flat_dt_match(of_get_flat_dt_root(), board);
75} 50}
76 51
77static struct of_device_id __initdata of_bus_ids[] = { 52machine_device_initcall(mpc831x_rdb, mpc83xx_declare_of_platform_devices);
78 { .compatible = "simple-bus" },
79 { .compatible = "gianfar" },
80 { .compatible = "gpio-leds", },
81 {},
82};
83
84static int __init declare_of_platform_devices(void)
85{
86 of_platform_bus_probe(NULL, of_bus_ids, NULL);
87 return 0;
88}
89machine_device_initcall(mpc831x_rdb, declare_of_platform_devices);
90 53
91define_machine(mpc831x_rdb) { 54define_machine(mpc831x_rdb) {
92 .name = "MPC831x RDB", 55 .name = "MPC831x RDB",
93 .probe = mpc831x_rdb_probe, 56 .probe = mpc831x_rdb_probe,
94 .setup_arch = mpc831x_rdb_setup_arch, 57 .setup_arch = mpc831x_rdb_setup_arch,
95 .init_IRQ = mpc831x_rdb_init_IRQ, 58 .init_IRQ = mpc83xx_ipic_init_IRQ,
96 .get_irq = ipic_get_irq, 59 .get_irq = ipic_get_irq,
97 .restart = mpc83xx_restart, 60 .restart = mpc83xx_restart,
98 .time_init = mpc83xx_time_init, 61 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 32a52896822..e36bc611dd6 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -72,10 +72,7 @@ static void __init mpc832x_sys_setup_arch(void)
72 of_node_put(np); 72 of_node_put(np);
73 } 73 }
74 74
75#ifdef CONFIG_PCI 75 mpc83xx_setup_pci();
76 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
77 mpc83xx_add_bridge(np);
78#endif
79 76
80#ifdef CONFIG_QUICC_ENGINE 77#ifdef CONFIG_QUICC_ENGINE
81 qe_reset(); 78 qe_reset();
@@ -101,51 +98,7 @@ static void __init mpc832x_sys_setup_arch(void)
101#endif /* CONFIG_QUICC_ENGINE */ 98#endif /* CONFIG_QUICC_ENGINE */
102} 99}
103 100
104static struct of_device_id mpc832x_ids[] = { 101machine_device_initcall(mpc832x_mds, mpc83xx_declare_of_platform_devices);
105 { .type = "soc", },
106 { .compatible = "soc", },
107 { .compatible = "simple-bus", },
108 { .type = "qe", },
109 { .compatible = "fsl,qe", },
110 {},
111};
112
113static int __init mpc832x_declare_of_platform_devices(void)
114{
115 /* Publish the QE devices */
116 of_platform_bus_probe(NULL, mpc832x_ids, NULL);
117
118 return 0;
119}
120machine_device_initcall(mpc832x_mds, mpc832x_declare_of_platform_devices);
121
122static void __init mpc832x_sys_init_IRQ(void)
123{
124 struct device_node *np;
125
126 np = of_find_node_by_type(NULL, "ipic");
127 if (!np)
128 return;
129
130 ipic_init(np, 0);
131
132 /* Initialize the default interrupt mapping priorities,
133 * in case the boot rom changed something on us.
134 */
135 ipic_set_default_priority();
136 of_node_put(np);
137
138#ifdef CONFIG_QUICC_ENGINE
139 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
140 if (!np) {
141 np = of_find_node_by_type(NULL, "qeic");
142 if (!np)
143 return;
144 }
145 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
146 of_node_put(np);
147#endif /* CONFIG_QUICC_ENGINE */
148}
149 102
150/* 103/*
151 * Called very early, MMU is off, device-tree isn't unflattened 104 * Called very early, MMU is off, device-tree isn't unflattened
@@ -161,7 +114,7 @@ define_machine(mpc832x_mds) {
161 .name = "MPC832x MDS", 114 .name = "MPC832x MDS",
162 .probe = mpc832x_sys_probe, 115 .probe = mpc832x_sys_probe,
163 .setup_arch = mpc832x_sys_setup_arch, 116 .setup_arch = mpc832x_sys_setup_arch,
164 .init_IRQ = mpc832x_sys_init_IRQ, 117 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
165 .get_irq = ipic_get_irq, 118 .get_irq = ipic_get_irq,
166 .restart = mpc83xx_restart, 119 .restart = mpc83xx_restart,
167 .time_init = mpc83xx_time_init, 120 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 17f99745f0e..eff5baabc3f 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -193,17 +193,14 @@ machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
193 */ 193 */
194static void __init mpc832x_rdb_setup_arch(void) 194static void __init mpc832x_rdb_setup_arch(void)
195{ 195{
196#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE) 196#if defined(CONFIG_QUICC_ENGINE)
197 struct device_node *np; 197 struct device_node *np;
198#endif 198#endif
199 199
200 if (ppc_md.progress) 200 if (ppc_md.progress)
201 ppc_md.progress("mpc832x_rdb_setup_arch()", 0); 201 ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
202 202
203#ifdef CONFIG_PCI 203 mpc83xx_setup_pci();
204 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
205 mpc83xx_add_bridge(np);
206#endif
207 204
208#ifdef CONFIG_QUICC_ENGINE 205#ifdef CONFIG_QUICC_ENGINE
209 qe_reset(); 206 qe_reset();
@@ -218,52 +215,7 @@ static void __init mpc832x_rdb_setup_arch(void)
218#endif /* CONFIG_QUICC_ENGINE */ 215#endif /* CONFIG_QUICC_ENGINE */
219} 216}
220 217
221static struct of_device_id mpc832x_ids[] = { 218machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
222 { .type = "soc", },
223 { .compatible = "soc", },
224 { .compatible = "simple-bus", },
225 { .type = "qe", },
226 { .compatible = "fsl,qe", },
227 {},
228};
229
230static int __init mpc832x_declare_of_platform_devices(void)
231{
232 /* Publish the QE devices */
233 of_platform_bus_probe(NULL, mpc832x_ids, NULL);
234
235 return 0;
236}
237machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
238
239static void __init mpc832x_rdb_init_IRQ(void)
240{
241
242 struct device_node *np;
243
244 np = of_find_node_by_type(NULL, "ipic");
245 if (!np)
246 return;
247
248 ipic_init(np, 0);
249
250 /* Initialize the default interrupt mapping priorities,
251 * in case the boot rom changed something on us.
252 */
253 ipic_set_default_priority();
254 of_node_put(np);
255
256#ifdef CONFIG_QUICC_ENGINE
257 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
258 if (!np) {
259 np = of_find_node_by_type(NULL, "qeic");
260 if (!np)
261 return;
262 }
263 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
264 of_node_put(np);
265#endif /* CONFIG_QUICC_ENGINE */
266}
267 219
268/* 220/*
269 * Called very early, MMU is off, device-tree isn't unflattened 221 * Called very early, MMU is off, device-tree isn't unflattened
@@ -279,7 +231,7 @@ define_machine(mpc832x_rdb) {
279 .name = "MPC832x RDB", 231 .name = "MPC832x RDB",
280 .probe = mpc832x_rdb_probe, 232 .probe = mpc832x_rdb_probe,
281 .setup_arch = mpc832x_rdb_setup_arch, 233 .setup_arch = mpc832x_rdb_setup_arch,
282 .init_IRQ = mpc832x_rdb_init_IRQ, 234 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
283 .get_irq = ipic_get_irq, 235 .get_irq = ipic_get_irq,
284 .restart = mpc83xx_restart, 236 .restart = mpc83xx_restart,
285 .time_init = mpc83xx_time_init, 237 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index 6b45969567d..39849dd1b5b 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -41,13 +41,12 @@
41 41
42static struct of_device_id __initdata mpc834x_itx_ids[] = { 42static struct of_device_id __initdata mpc834x_itx_ids[] = {
43 { .compatible = "fsl,pq2pro-localbus", }, 43 { .compatible = "fsl,pq2pro-localbus", },
44 { .compatible = "simple-bus", },
45 { .compatible = "gianfar", },
46 {}, 44 {},
47}; 45};
48 46
49static int __init mpc834x_itx_declare_of_platform_devices(void) 47static int __init mpc834x_itx_declare_of_platform_devices(void)
50{ 48{
49 mpc83xx_declare_of_platform_devices();
51 return of_platform_bus_probe(NULL, mpc834x_itx_ids, NULL); 50 return of_platform_bus_probe(NULL, mpc834x_itx_ids, NULL);
52} 51}
53machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices); 52machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices);
@@ -59,37 +58,14 @@ machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices);
59 */ 58 */
60static void __init mpc834x_itx_setup_arch(void) 59static void __init mpc834x_itx_setup_arch(void)
61{ 60{
62#ifdef CONFIG_PCI
63 struct device_node *np;
64#endif
65
66 if (ppc_md.progress) 61 if (ppc_md.progress)
67 ppc_md.progress("mpc834x_itx_setup_arch()", 0); 62 ppc_md.progress("mpc834x_itx_setup_arch()", 0);
68 63
69#ifdef CONFIG_PCI 64 mpc83xx_setup_pci();
70 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
71 mpc83xx_add_bridge(np);
72#endif
73 65
74 mpc834x_usb_cfg(); 66 mpc834x_usb_cfg();
75} 67}
76 68
77static void __init mpc834x_itx_init_IRQ(void)
78{
79 struct device_node *np;
80
81 np = of_find_node_by_type(NULL, "ipic");
82 if (!np)
83 return;
84
85 ipic_init(np, 0);
86
87 /* Initialize the default interrupt mapping priorities,
88 * in case the boot rom changed something on us.
89 */
90 ipic_set_default_priority();
91}
92
93/* 69/*
94 * Called very early, MMU is off, device-tree isn't unflattened 70 * Called very early, MMU is off, device-tree isn't unflattened
95 */ 71 */
@@ -104,7 +80,7 @@ define_machine(mpc834x_itx) {
104 .name = "MPC834x ITX", 80 .name = "MPC834x ITX",
105 .probe = mpc834x_itx_probe, 81 .probe = mpc834x_itx_probe,
106 .setup_arch = mpc834x_itx_setup_arch, 82 .setup_arch = mpc834x_itx_setup_arch,
107 .init_IRQ = mpc834x_itx_init_IRQ, 83 .init_IRQ = mpc83xx_ipic_init_IRQ,
108 .get_irq = ipic_get_irq, 84 .get_irq = ipic_get_irq,
109 .restart = mpc83xx_restart, 85 .restart = mpc83xx_restart,
110 .time_init = mpc83xx_time_init, 86 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc834x_mds.c b/arch/powerpc/platforms/83xx/mpc834x_mds.c
index 041c5177e73..5828d8e97c3 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_mds.c
@@ -77,51 +77,15 @@ static int mpc834xemds_usb_cfg(void)
77 */ 77 */
78static void __init mpc834x_mds_setup_arch(void) 78static void __init mpc834x_mds_setup_arch(void)
79{ 79{
80#ifdef CONFIG_PCI
81 struct device_node *np;
82#endif
83
84 if (ppc_md.progress) 80 if (ppc_md.progress)
85 ppc_md.progress("mpc834x_mds_setup_arch()", 0); 81 ppc_md.progress("mpc834x_mds_setup_arch()", 0);
86 82
87#ifdef CONFIG_PCI 83 mpc83xx_setup_pci();
88 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
89 mpc83xx_add_bridge(np);
90#endif
91 84
92 mpc834xemds_usb_cfg(); 85 mpc834xemds_usb_cfg();
93} 86}
94 87
95static void __init mpc834x_mds_init_IRQ(void) 88machine_device_initcall(mpc834x_mds, mpc83xx_declare_of_platform_devices);
96{
97 struct device_node *np;
98
99 np = of_find_node_by_type(NULL, "ipic");
100 if (!np)
101 return;
102
103 ipic_init(np, 0);
104
105 /* Initialize the default interrupt mapping priorities,
106 * in case the boot rom changed something on us.
107 */
108 ipic_set_default_priority();
109}
110
111static struct of_device_id mpc834x_ids[] = {
112 { .type = "soc", },
113 { .compatible = "soc", },
114 { .compatible = "simple-bus", },
115 { .compatible = "gianfar", },
116 {},
117};
118
119static int __init mpc834x_declare_of_platform_devices(void)
120{
121 of_platform_bus_probe(NULL, mpc834x_ids, NULL);
122 return 0;
123}
124machine_device_initcall(mpc834x_mds, mpc834x_declare_of_platform_devices);
125 89
126/* 90/*
127 * Called very early, MMU is off, device-tree isn't unflattened 91 * Called very early, MMU is off, device-tree isn't unflattened
@@ -137,7 +101,7 @@ define_machine(mpc834x_mds) {
137 .name = "MPC834x MDS", 101 .name = "MPC834x MDS",
138 .probe = mpc834x_mds_probe, 102 .probe = mpc834x_mds_probe,
139 .setup_arch = mpc834x_mds_setup_arch, 103 .setup_arch = mpc834x_mds_setup_arch,
140 .init_IRQ = mpc834x_mds_init_IRQ, 104 .init_IRQ = mpc83xx_ipic_init_IRQ,
141 .get_irq = ipic_get_irq, 105 .get_irq = ipic_get_irq,
142 .restart = mpc83xx_restart, 106 .restart = mpc83xx_restart,
143 .time_init = mpc83xx_time_init, 107 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 934cc8c46bb..ad8e4bcd7d5 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -80,10 +80,7 @@ static void __init mpc836x_mds_setup_arch(void)
80 of_node_put(np); 80 of_node_put(np);
81 } 81 }
82 82
83#ifdef CONFIG_PCI 83 mpc83xx_setup_pci();
84 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
85 mpc83xx_add_bridge(np);
86#endif
87 84
88#ifdef CONFIG_QUICC_ENGINE 85#ifdef CONFIG_QUICC_ENGINE
89 qe_reset(); 86 qe_reset();
@@ -144,23 +141,7 @@ static void __init mpc836x_mds_setup_arch(void)
144#endif /* CONFIG_QUICC_ENGINE */ 141#endif /* CONFIG_QUICC_ENGINE */
145} 142}
146 143
147static struct of_device_id mpc836x_ids[] = { 144machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
148 { .type = "soc", },
149 { .compatible = "soc", },
150 { .compatible = "simple-bus", },
151 { .type = "qe", },
152 { .compatible = "fsl,qe", },
153 {},
154};
155
156static int __init mpc836x_declare_of_platform_devices(void)
157{
158 /* Publish the QE devices */
159 of_platform_bus_probe(NULL, mpc836x_ids, NULL);
160
161 return 0;
162}
163machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
164 145
165#ifdef CONFIG_QE_USB 146#ifdef CONFIG_QE_USB
166static int __init mpc836x_usb_cfg(void) 147static int __init mpc836x_usb_cfg(void)
@@ -226,34 +207,6 @@ err:
226machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg); 207machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
227#endif /* CONFIG_QE_USB */ 208#endif /* CONFIG_QE_USB */
228 209
229static void __init mpc836x_mds_init_IRQ(void)
230{
231 struct device_node *np;
232
233 np = of_find_node_by_type(NULL, "ipic");
234 if (!np)
235 return;
236
237 ipic_init(np, 0);
238
239 /* Initialize the default interrupt mapping priorities,
240 * in case the boot rom changed something on us.
241 */
242 ipic_set_default_priority();
243 of_node_put(np);
244
245#ifdef CONFIG_QUICC_ENGINE
246 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
247 if (!np) {
248 np = of_find_node_by_type(NULL, "qeic");
249 if (!np)
250 return;
251 }
252 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
253 of_node_put(np);
254#endif /* CONFIG_QUICC_ENGINE */
255}
256
257/* 210/*
258 * Called very early, MMU is off, device-tree isn't unflattened 211 * Called very early, MMU is off, device-tree isn't unflattened
259 */ 212 */
@@ -268,7 +221,7 @@ define_machine(mpc836x_mds) {
268 .name = "MPC836x MDS", 221 .name = "MPC836x MDS",
269 .probe = mpc836x_mds_probe, 222 .probe = mpc836x_mds_probe,
270 .setup_arch = mpc836x_mds_setup_arch, 223 .setup_arch = mpc836x_mds_setup_arch,
271 .init_IRQ = mpc836x_mds_init_IRQ, 224 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
272 .get_irq = ipic_get_irq, 225 .get_irq = ipic_get_irq,
273 .restart = mpc83xx_restart, 226 .restart = mpc83xx_restart,
274 .time_init = mpc83xx_time_init, 227 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index b0090aac964..f8769d713d6 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -27,61 +27,19 @@
27 27
28#include "mpc83xx.h" 28#include "mpc83xx.h"
29 29
30static struct of_device_id __initdata mpc836x_rdk_ids[] = { 30machine_device_initcall(mpc836x_rdk, mpc83xx_declare_of_platform_devices);
31 { .compatible = "simple-bus", },
32 {},
33};
34
35static int __init mpc836x_rdk_declare_of_platform_devices(void)
36{
37 return of_platform_bus_probe(NULL, mpc836x_rdk_ids, NULL);
38}
39machine_device_initcall(mpc836x_rdk, mpc836x_rdk_declare_of_platform_devices);
40 31
41static void __init mpc836x_rdk_setup_arch(void) 32static void __init mpc836x_rdk_setup_arch(void)
42{ 33{
43#ifdef CONFIG_PCI
44 struct device_node *np;
45#endif
46
47 if (ppc_md.progress) 34 if (ppc_md.progress)
48 ppc_md.progress("mpc836x_rdk_setup_arch()", 0); 35 ppc_md.progress("mpc836x_rdk_setup_arch()", 0);
49 36
50#ifdef CONFIG_PCI 37 mpc83xx_setup_pci();
51 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
52 mpc83xx_add_bridge(np);
53#endif
54#ifdef CONFIG_QUICC_ENGINE 38#ifdef CONFIG_QUICC_ENGINE
55 qe_reset(); 39 qe_reset();
56#endif 40#endif
57} 41}
58 42
59static void __init mpc836x_rdk_init_IRQ(void)
60{
61 struct device_node *np;
62
63 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
64 if (!np)
65 return;
66
67 ipic_init(np, 0);
68
69 /*
70 * Initialize the default interrupt mapping priorities,
71 * in case the boot rom changed something on us.
72 */
73 ipic_set_default_priority();
74 of_node_put(np);
75#ifdef CONFIG_QUICC_ENGINE
76 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
77 if (!np)
78 return;
79
80 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
81 of_node_put(np);
82#endif
83}
84
85/* 43/*
86 * Called very early, MMU is off, device-tree isn't unflattened. 44 * Called very early, MMU is off, device-tree isn't unflattened.
87 */ 45 */
@@ -96,7 +54,7 @@ define_machine(mpc836x_rdk) {
96 .name = "MPC836x RDK", 54 .name = "MPC836x RDK",
97 .probe = mpc836x_rdk_probe, 55 .probe = mpc836x_rdk_probe,
98 .setup_arch = mpc836x_rdk_setup_arch, 56 .setup_arch = mpc836x_rdk_setup_arch,
99 .init_IRQ = mpc836x_rdk_init_IRQ, 57 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
100 .get_irq = ipic_get_irq, 58 .get_irq = ipic_get_irq,
101 .restart = mpc83xx_restart, 59 .restart = mpc83xx_restart,
102 .time_init = mpc83xx_time_init, 60 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 83068322abd..e53a60b6c86 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -79,54 +79,14 @@ out:
79 */ 79 */
80static void __init mpc837x_mds_setup_arch(void) 80static void __init mpc837x_mds_setup_arch(void)
81{ 81{
82#ifdef CONFIG_PCI
83 struct device_node *np;
84#endif
85
86 if (ppc_md.progress) 82 if (ppc_md.progress)
87 ppc_md.progress("mpc837x_mds_setup_arch()", 0); 83 ppc_md.progress("mpc837x_mds_setup_arch()", 0);
88 84
89#ifdef CONFIG_PCI 85 mpc83xx_setup_pci();
90 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
91 mpc83xx_add_bridge(np);
92 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
93 mpc83xx_add_bridge(np);
94#endif
95 mpc837xmds_usb_cfg(); 86 mpc837xmds_usb_cfg();
96} 87}
97 88
98static struct of_device_id mpc837x_ids[] = { 89machine_device_initcall(mpc837x_mds, mpc83xx_declare_of_platform_devices);
99 { .type = "soc", },
100 { .compatible = "soc", },
101 { .compatible = "simple-bus", },
102 { .compatible = "gianfar", },
103 {},
104};
105
106static int __init mpc837x_declare_of_platform_devices(void)
107{
108 /* Publish platform_device */
109 of_platform_bus_probe(NULL, mpc837x_ids, NULL);
110
111 return 0;
112}
113machine_device_initcall(mpc837x_mds, mpc837x_declare_of_platform_devices);
114
115static void __init mpc837x_mds_init_IRQ(void)
116{
117 struct device_node *np;
118
119 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
120 if (!np)
121 return;
122
123 ipic_init(np, 0);
124
125 /* Initialize the default interrupt mapping priorities,
126 * in case the boot rom changed something on us.
127 */
128 ipic_set_default_priority();
129}
130 90
131/* 91/*
132 * Called very early, MMU is off, device-tree isn't unflattened 92 * Called very early, MMU is off, device-tree isn't unflattened
@@ -142,7 +102,7 @@ define_machine(mpc837x_mds) {
142 .name = "MPC837x MDS", 102 .name = "MPC837x MDS",
143 .probe = mpc837x_mds_probe, 103 .probe = mpc837x_mds_probe,
144 .setup_arch = mpc837x_mds_setup_arch, 104 .setup_arch = mpc837x_mds_setup_arch,
145 .init_IRQ = mpc837x_mds_init_IRQ, 105 .init_IRQ = mpc83xx_ipic_init_IRQ,
146 .get_irq = ipic_get_irq, 106 .get_irq = ipic_get_irq,
147 .restart = mpc83xx_restart, 107 .restart = mpc83xx_restart,
148 .time_init = mpc83xx_time_init, 108 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 7bafbf2ec0f..16c9c9cbbb7 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -50,56 +50,15 @@ static void mpc837x_rdb_sd_cfg(void)
50 */ 50 */
51static void __init mpc837x_rdb_setup_arch(void) 51static void __init mpc837x_rdb_setup_arch(void)
52{ 52{
53#ifdef CONFIG_PCI
54 struct device_node *np;
55#endif
56
57 if (ppc_md.progress) 53 if (ppc_md.progress)
58 ppc_md.progress("mpc837x_rdb_setup_arch()", 0); 54 ppc_md.progress("mpc837x_rdb_setup_arch()", 0);
59 55
60#ifdef CONFIG_PCI 56 mpc83xx_setup_pci();
61 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
62 mpc83xx_add_bridge(np);
63 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
64 mpc83xx_add_bridge(np);
65#endif
66 mpc837x_usb_cfg(); 57 mpc837x_usb_cfg();
67 mpc837x_rdb_sd_cfg(); 58 mpc837x_rdb_sd_cfg();
68} 59}
69 60
70static struct of_device_id mpc837x_ids[] = { 61machine_device_initcall(mpc837x_rdb, mpc83xx_declare_of_platform_devices);
71 { .type = "soc", },
72 { .compatible = "soc", },
73 { .compatible = "simple-bus", },
74 { .compatible = "gianfar", },
75 { .compatible = "gpio-leds", },
76 {},
77};
78
79static int __init mpc837x_declare_of_platform_devices(void)
80{
81 /* Publish platform_device */
82 of_platform_bus_probe(NULL, mpc837x_ids, NULL);
83
84 return 0;
85}
86machine_device_initcall(mpc837x_rdb, mpc837x_declare_of_platform_devices);
87
88static void __init mpc837x_rdb_init_IRQ(void)
89{
90 struct device_node *np;
91
92 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
93 if (!np)
94 return;
95
96 ipic_init(np, 0);
97
98 /* Initialize the default interrupt mapping priorities,
99 * in case the boot rom changed something on us.
100 */
101 ipic_set_default_priority();
102}
103 62
104static const char *board[] __initdata = { 63static const char *board[] __initdata = {
105 "fsl,mpc8377rdb", 64 "fsl,mpc8377rdb",
@@ -121,7 +80,7 @@ define_machine(mpc837x_rdb) {
121 .name = "MPC837x RDB/WLAN", 80 .name = "MPC837x RDB/WLAN",
122 .probe = mpc837x_rdb_probe, 81 .probe = mpc837x_rdb_probe,
123 .setup_arch = mpc837x_rdb_setup_arch, 82 .setup_arch = mpc837x_rdb_setup_arch,
124 .init_IRQ = mpc837x_rdb_init_IRQ, 83 .init_IRQ = mpc83xx_ipic_init_IRQ,
125 .get_irq = ipic_get_irq, 84 .get_irq = ipic_get_irq,
126 .restart = mpc83xx_restart, 85 .restart = mpc83xx_restart,
127 .time_init = mpc83xx_time_init, 86 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 82a434510d8..0cf74d7ea1c 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -70,5 +70,21 @@ extern long mpc83xx_time_init(void);
70extern int mpc837x_usb_cfg(void); 70extern int mpc837x_usb_cfg(void);
71extern int mpc834x_usb_cfg(void); 71extern int mpc834x_usb_cfg(void);
72extern int mpc831x_usb_cfg(void); 72extern int mpc831x_usb_cfg(void);
73extern void mpc83xx_ipic_init_IRQ(void);
74#ifdef CONFIG_QUICC_ENGINE
75extern void mpc83xx_qe_init_IRQ(void);
76extern void mpc83xx_ipic_and_qe_init_IRQ(void);
77#else
78static inline void __init mpc83xx_qe_init_IRQ(void) {}
79#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
80#endif /* CONFIG_QUICC_ENGINE */
81
82#ifdef CONFIG_PCI
83extern void mpc83xx_setup_pci(void);
84#else
85#define mpc83xx_setup_pci() do {} while (0)
86#endif
87
88extern int mpc83xx_declare_of_platform_devices(void);
73 89
74#endif /* __MPC83XX_H__ */ 90#endif /* __MPC83XX_H__ */
diff --git a/arch/powerpc/platforms/83xx/sbc834x.c b/arch/powerpc/platforms/83xx/sbc834x.c
index af41d8c810a..8a81d7640b1 100644
--- a/arch/powerpc/platforms/83xx/sbc834x.c
+++ b/arch/powerpc/platforms/83xx/sbc834x.c
@@ -48,52 +48,13 @@
48 */ 48 */
49static void __init sbc834x_setup_arch(void) 49static void __init sbc834x_setup_arch(void)
50{ 50{
51#ifdef CONFIG_PCI
52 struct device_node *np;
53#endif
54
55 if (ppc_md.progress) 51 if (ppc_md.progress)
56 ppc_md.progress("sbc834x_setup_arch()", 0); 52 ppc_md.progress("sbc834x_setup_arch()", 0);
57 53
58#ifdef CONFIG_PCI 54 mpc83xx_setup_pci();
59 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
60 mpc83xx_add_bridge(np);
61#endif
62
63} 55}
64 56
65static void __init sbc834x_init_IRQ(void) 57machine_device_initcall(sbc834x, mpc83xx_declare_of_platform_devices);
66{
67 struct device_node *np;
68
69 np = of_find_node_by_type(NULL, "ipic");
70 if (!np)
71 return;
72
73 ipic_init(np, 0);
74
75 /* Initialize the default interrupt mapping priorities,
76 * in case the boot rom changed something on us.
77 */
78 ipic_set_default_priority();
79
80 of_node_put(np);
81}
82
83static struct __initdata of_device_id sbc834x_ids[] = {
84 { .type = "soc", },
85 { .compatible = "soc", },
86 { .compatible = "simple-bus", },
87 { .compatible = "gianfar", },
88 {},
89};
90
91static int __init sbc834x_declare_of_platform_devices(void)
92{
93 of_platform_bus_probe(NULL, sbc834x_ids, NULL);
94 return 0;
95}
96machine_device_initcall(sbc834x, sbc834x_declare_of_platform_devices);
97 58
98/* 59/*
99 * Called very early, MMU is off, device-tree isn't unflattened 60 * Called very early, MMU is off, device-tree isn't unflattened
@@ -102,14 +63,14 @@ static int __init sbc834x_probe(void)
102{ 63{
103 unsigned long root = of_get_flat_dt_root(); 64 unsigned long root = of_get_flat_dt_root();
104 65
105 return of_flat_dt_is_compatible(root, "SBC834x"); 66 return of_flat_dt_is_compatible(root, "SBC834xE");
106} 67}
107 68
108define_machine(sbc834x) { 69define_machine(sbc834x) {
109 .name = "SBC834x", 70 .name = "SBC834xE",
110 .probe = sbc834x_probe, 71 .probe = sbc834x_probe,
111 .setup_arch = sbc834x_setup_arch, 72 .setup_arch = sbc834x_setup_arch,
112 .init_IRQ = sbc834x_init_IRQ, 73 .init_IRQ = mpc83xx_ipic_init_IRQ,
113 .get_irq = ipic_get_irq, 74 .get_irq = ipic_get_irq,
114 .restart = mpc83xx_restart, 75 .restart = mpc83xx_restart,
115 .time_init = mpc83xx_time_init, 76 .time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index bc5acb95917..9cb2d4320dc 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -3,6 +3,8 @@
3# 3#
4obj-$(CONFIG_SMP) += smp.o 4obj-$(CONFIG_SMP) += smp.o
5 5
6obj-y += common.o
7
6obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o 8obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
7obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o 9obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
8obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o 10obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
new file mode 100644
index 00000000000..9fef5302adc
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -0,0 +1,66 @@
1/*
2 * Routines common to most mpc85xx-based boards.
3 *
4 * This is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/of_platform.h>
9
10#include <sysdev/cpm2_pic.h>
11
12#include "mpc85xx.h"
13
14static struct of_device_id __initdata mpc85xx_common_ids[] = {
15 { .type = "soc", },
16 { .compatible = "soc", },
17 { .compatible = "simple-bus", },
18 { .name = "cpm", },
19 { .name = "localbus", },
20 { .compatible = "gianfar", },
21 { .compatible = "fsl,qe", },
22 { .compatible = "fsl,cpm2", },
23 { .compatible = "fsl,srio", },
24 {},
25};
26
27int __init mpc85xx_common_publish_devices(void)
28{
29 return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
30}
31#ifdef CONFIG_CPM2
32static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
33{
34 struct irq_chip *chip = irq_desc_get_chip(desc);
35 int cascade_irq;
36
37 while ((cascade_irq = cpm2_get_irq()) >= 0)
38 generic_handle_irq(cascade_irq);
39
40 chip->irq_eoi(&desc->irq_data);
41}
42
43
44void __init mpc85xx_cpm2_pic_init(void)
45{
46 struct device_node *np;
47 int irq;
48
49 /* Setup CPM2 PIC */
50 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
51 if (np == NULL) {
52 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
53 return;
54 }
55 irq = irq_of_parse_and_map(np, 0);
56 if (irq == NO_IRQ) {
57 of_node_put(np);
58 printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
59 return;
60 }
61
62 cpm2_pic_init(np);
63 of_node_put(np);
64 irq_set_chained_handler(irq, cpm2_cascade);
65}
66#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 802ad110b75..07e3e6c4737 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -31,32 +31,18 @@
31#include <linux/of_platform.h> 31#include <linux/of_platform.h>
32#include <sysdev/fsl_soc.h> 32#include <sysdev/fsl_soc.h>
33#include <sysdev/fsl_pci.h> 33#include <sysdev/fsl_pci.h>
34#include "smp.h"
34 35
35void __init corenet_ds_pic_init(void) 36void __init corenet_ds_pic_init(void)
36{ 37{
37 struct mpic *mpic; 38 struct mpic *mpic;
38 struct resource r; 39 unsigned int flags = MPIC_BIG_ENDIAN |
39 struct device_node *np = NULL;
40 unsigned int flags = MPIC_PRIMARY | MPIC_BIG_ENDIAN |
41 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU; 40 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
42 41
43 np = of_find_node_by_type(np, "open-pic");
44
45 if (np == NULL) {
46 printk(KERN_ERR "Could not find open-pic node\n");
47 return;
48 }
49
50 if (of_address_to_resource(np, 0, &r)) {
51 printk(KERN_ERR "Failed to map mpic register space\n");
52 of_node_put(np);
53 return;
54 }
55
56 if (ppc_md.get_irq == mpic_get_coreint_irq) 42 if (ppc_md.get_irq == mpic_get_coreint_irq)
57 flags |= MPIC_ENABLE_COREINT; 43 flags |= MPIC_ENABLE_COREINT;
58 44
59 mpic = mpic_alloc(np, r.start, flags, 0, 256, " OpenPIC "); 45 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
60 BUG_ON(mpic == NULL); 46 BUG_ON(mpic == NULL);
61 47
62 mpic_init(mpic); 48 mpic_init(mpic);
@@ -65,10 +51,6 @@ void __init corenet_ds_pic_init(void)
65/* 51/*
66 * Setup the architecture 52 * Setup the architecture
67 */ 53 */
68#ifdef CONFIG_SMP
69void __init mpc85xx_smp_init(void);
70#endif
71
72void __init corenet_ds_setup_arch(void) 54void __init corenet_ds_setup_arch(void)
73{ 55{
74#ifdef CONFIG_PCI 56#ifdef CONFIG_PCI
@@ -77,9 +59,7 @@ void __init corenet_ds_setup_arch(void)
77#endif 59#endif
78 dma_addr_t max = 0xffffffff; 60 dma_addr_t max = 0xffffffff;
79 61
80#ifdef CONFIG_SMP
81 mpc85xx_smp_init(); 62 mpc85xx_smp_init();
82#endif
83 63
84#ifdef CONFIG_PCI 64#ifdef CONFIG_PCI
85 for_each_node_by_type(np, "pci") { 65 for_each_node_by_type(np, "pci") {
@@ -112,7 +92,7 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
112 .compatible = "simple-bus" 92 .compatible = "simple-bus"
113 }, 93 },
114 { 94 {
115 .compatible = "fsl,rapidio-delta", 95 .compatible = "fsl,srio",
116 }, 96 },
117 { 97 {
118 .compatible = "fsl,p4080-pcie", 98 .compatible = "fsl,p4080-pcie",
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index c46f9359be1..20f75d7819c 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -35,6 +35,7 @@
35#include <asm/cpm2.h> 35#include <asm/cpm2.h>
36#include <sysdev/cpm2_pic.h> 36#include <sysdev/cpm2_pic.h>
37 37
38#include "mpc85xx.h"
38 39
39#define KSI8560_CPLD_HVR 0x04 /* Hardware Version Register */ 40#define KSI8560_CPLD_HVR 0x04 /* Hardware Version Register */
40#define KSI8560_CPLD_PVR 0x08 /* PLD Version Register */ 41#define KSI8560_CPLD_PVR 0x08 /* PLD Version Register */
@@ -54,60 +55,15 @@ static void machine_restart(char *cmd)
54 for (;;); 55 for (;;);
55} 56}
56 57
57static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
58{
59 struct irq_chip *chip = irq_desc_get_chip(desc);
60 int cascade_irq;
61
62 while ((cascade_irq = cpm2_get_irq()) >= 0)
63 generic_handle_irq(cascade_irq);
64
65 chip->irq_eoi(&desc->irq_data);
66}
67
68static void __init ksi8560_pic_init(void) 58static void __init ksi8560_pic_init(void)
69{ 59{
70 struct mpic *mpic; 60 struct mpic *mpic = mpic_alloc(NULL, 0,
71 struct resource r; 61 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
72 struct device_node *np;
73#ifdef CONFIG_CPM2
74 int irq;
75#endif
76
77 np = of_find_node_by_type(NULL, "open-pic");
78
79 if (np == NULL) {
80 printk(KERN_ERR "Could not find open-pic node\n");
81 return;
82 }
83
84 if (of_address_to_resource(np, 0, &r)) {
85 printk(KERN_ERR "Could not map mpic register space\n");
86 of_node_put(np);
87 return;
88 }
89
90 mpic = mpic_alloc(np, r.start,
91 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
92 0, 256, " OpenPIC "); 62 0, 256, " OpenPIC ");
93 BUG_ON(mpic == NULL); 63 BUG_ON(mpic == NULL);
94 of_node_put(np);
95
96 mpic_init(mpic); 64 mpic_init(mpic);
97 65
98#ifdef CONFIG_CPM2 66 mpc85xx_cpm2_pic_init();
99 /* Setup CPM2 PIC */
100 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
101 if (np == NULL) {
102 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
103 return;
104 }
105 irq = irq_of_parse_and_map(np, 0);
106
107 cpm2_pic_init(np);
108 of_node_put(np);
109 irq_set_chained_handler(irq, cpm2_cascade);
110#endif
111} 67}
112 68
113#ifdef CONFIG_CPM2 69#ifdef CONFIG_CPM2
@@ -215,22 +171,7 @@ static void ksi8560_show_cpuinfo(struct seq_file *m)
215 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 171 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
216} 172}
217 173
218static struct of_device_id __initdata of_bus_ids[] = { 174machine_device_initcall(ksi8560, mpc85xx_common_publish_devices);
219 { .type = "soc", },
220 { .type = "simple-bus", },
221 { .name = "cpm", },
222 { .name = "localbus", },
223 { .compatible = "gianfar", },
224 {},
225};
226
227static int __init declare_of_platform_devices(void)
228{
229 of_platform_bus_probe(NULL, of_bus_ids, NULL);
230
231 return 0;
232}
233machine_device_initcall(ksi8560, declare_of_platform_devices);
234 175
235/* 176/*
236 * Called very early, device-tree isn't unflattened 177 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index f79f2f10214..cf266826682 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -32,31 +32,15 @@
32#include <sysdev/fsl_soc.h> 32#include <sysdev/fsl_soc.h>
33#include <sysdev/fsl_pci.h> 33#include <sysdev/fsl_pci.h>
34 34
35#include "mpc85xx.h"
36
35void __init mpc8536_ds_pic_init(void) 37void __init mpc8536_ds_pic_init(void)
36{ 38{
37 struct mpic *mpic; 39 struct mpic *mpic = mpic_alloc(NULL, 0,
38 struct resource r; 40 MPIC_WANTS_RESET |
39 struct device_node *np;
40
41 np = of_find_node_by_type(NULL, "open-pic");
42 if (np == NULL) {
43 printk(KERN_ERR "Could not find open-pic node\n");
44 return;
45 }
46
47 if (of_address_to_resource(np, 0, &r)) {
48 printk(KERN_ERR "Failed to map mpic register space\n");
49 of_node_put(np);
50 return;
51 }
52
53 mpic = mpic_alloc(np, r.start,
54 MPIC_PRIMARY | MPIC_WANTS_RESET |
55 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, 41 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
56 0, 256, " OpenPIC "); 42 0, 256, " OpenPIC ");
57 BUG_ON(mpic == NULL); 43 BUG_ON(mpic == NULL);
58 of_node_put(np);
59
60 mpic_init(mpic); 44 mpic_init(mpic);
61} 45}
62 46
@@ -104,19 +88,7 @@ static void __init mpc8536_ds_setup_arch(void)
104 printk("MPC8536 DS board from Freescale Semiconductor\n"); 88 printk("MPC8536 DS board from Freescale Semiconductor\n");
105} 89}
106 90
107static struct of_device_id __initdata mpc8536_ds_ids[] = { 91machine_device_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
108 { .type = "soc", },
109 { .compatible = "soc", },
110 { .compatible = "simple-bus", },
111 { .compatible = "gianfar", },
112 {},
113};
114
115static int __init mpc8536_ds_publish_devices(void)
116{
117 return of_platform_bus_probe(NULL, mpc8536_ds_ids, NULL);
118}
119machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices);
120 92
121machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier); 93machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
122 94
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
new file mode 100644
index 00000000000..2aa7c5dc2c7
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -0,0 +1,11 @@
1#ifndef MPC85xx_H
2#define MPC85xx_H
3extern int mpc85xx_common_publish_devices(void);
4
5#ifdef CONFIG_CPM2
6extern void mpc85xx_cpm2_pic_init(void);
7#else
8static inline void __init mpc85xx_cpm2_pic_init(void) {}
9#endif /* CONFIG_CPM2 */
10
11#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 3b2c9bb6619..3bebb5173bf 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -35,6 +35,8 @@
35#include <sysdev/cpm2_pic.h> 35#include <sysdev/cpm2_pic.h>
36#endif 36#endif
37 37
38#include "mpc85xx.h"
39
38#ifdef CONFIG_PCI 40#ifdef CONFIG_PCI
39static int mpc85xx_exclude_device(struct pci_controller *hose, 41static int mpc85xx_exclude_device(struct pci_controller *hose,
40 u_char bus, u_char devfn) 42 u_char bus, u_char devfn)
@@ -46,63 +48,15 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
46} 48}
47#endif /* CONFIG_PCI */ 49#endif /* CONFIG_PCI */
48 50
49#ifdef CONFIG_CPM2
50
51static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
52{
53 struct irq_chip *chip = irq_desc_get_chip(desc);
54 int cascade_irq;
55
56 while ((cascade_irq = cpm2_get_irq()) >= 0)
57 generic_handle_irq(cascade_irq);
58
59 chip->irq_eoi(&desc->irq_data);
60}
61
62#endif /* CONFIG_CPM2 */
63
64static void __init mpc85xx_ads_pic_init(void) 51static void __init mpc85xx_ads_pic_init(void)
65{ 52{
66 struct mpic *mpic; 53 struct mpic *mpic = mpic_alloc(NULL, 0,
67 struct resource r; 54 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
68 struct device_node *np = NULL;
69#ifdef CONFIG_CPM2
70 int irq;
71#endif
72
73 np = of_find_node_by_type(np, "open-pic");
74 if (!np) {
75 printk(KERN_ERR "Could not find open-pic node\n");
76 return;
77 }
78
79 if (of_address_to_resource(np, 0, &r)) {
80 printk(KERN_ERR "Could not map mpic register space\n");
81 of_node_put(np);
82 return;
83 }
84
85 mpic = mpic_alloc(np, r.start,
86 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
87 0, 256, " OpenPIC "); 55 0, 256, " OpenPIC ");
88 BUG_ON(mpic == NULL); 56 BUG_ON(mpic == NULL);
89 of_node_put(np);
90
91 mpic_init(mpic); 57 mpic_init(mpic);
92 58
93#ifdef CONFIG_CPM2 59 mpc85xx_cpm2_pic_init();
94 /* Setup CPM2 PIC */
95 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
96 if (np == NULL) {
97 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
98 return;
99 }
100 irq = irq_of_parse_and_map(np, 0);
101
102 cpm2_pic_init(np);
103 of_node_put(np);
104 irq_set_chained_handler(irq, cpm2_cascade);
105#endif
106} 60}
107 61
108/* 62/*
@@ -221,23 +175,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
221 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 175 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
222} 176}
223 177
224static struct of_device_id __initdata of_bus_ids[] = { 178machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
225 { .name = "soc", },
226 { .type = "soc", },
227 { .name = "cpm", },
228 { .name = "localbus", },
229 { .compatible = "simple-bus", },
230 { .compatible = "gianfar", },
231 {},
232};
233
234static int __init declare_of_platform_devices(void)
235{
236 of_platform_bus_probe(NULL, of_bus_ids, NULL);
237
238 return 0;
239}
240machine_device_initcall(mpc85xx_ads, declare_of_platform_devices);
241 179
242/* 180/*
243 * Called very early, device-tree isn't unflattened 181 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 66cb8d64079..40f03da616a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -46,6 +46,8 @@
46#include <sysdev/fsl_soc.h> 46#include <sysdev/fsl_soc.h>
47#include <sysdev/fsl_pci.h> 47#include <sysdev/fsl_pci.h>
48 48
49#include "mpc85xx.h"
50
49/* CADMUS info */ 51/* CADMUS info */
50/* xxx - galak, move into device tree */ 52/* xxx - galak, move into device tree */
51#define CADMUS_BASE (0xf8004000) 53#define CADMUS_BASE (0xf8004000)
@@ -177,7 +179,7 @@ static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
177 179
178static struct irqaction mpc85xxcds_8259_irqaction = { 180static struct irqaction mpc85xxcds_8259_irqaction = {
179 .handler = mpc85xx_8259_cascade_action, 181 .handler = mpc85xx_8259_cascade_action,
180 .flags = IRQF_SHARED, 182 .flags = IRQF_SHARED | IRQF_NO_THREAD,
181 .name = "8259 cascade", 183 .name = "8259 cascade",
182}; 184};
183#endif /* PPC_I8259 */ 185#endif /* PPC_I8259 */
@@ -186,30 +188,10 @@ static struct irqaction mpc85xxcds_8259_irqaction = {
186static void __init mpc85xx_cds_pic_init(void) 188static void __init mpc85xx_cds_pic_init(void)
187{ 189{
188 struct mpic *mpic; 190 struct mpic *mpic;
189 struct resource r; 191 mpic = mpic_alloc(NULL, 0,
190 struct device_node *np = NULL; 192 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
191
192 np = of_find_node_by_type(np, "open-pic");
193
194 if (np == NULL) {
195 printk(KERN_ERR "Could not find open-pic node\n");
196 return;
197 }
198
199 if (of_address_to_resource(np, 0, &r)) {
200 printk(KERN_ERR "Failed to map mpic register space\n");
201 of_node_put(np);
202 return;
203 }
204
205 mpic = mpic_alloc(np, r.start,
206 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
207 0, 256, " OpenPIC "); 193 0, 256, " OpenPIC ");
208 BUG_ON(mpic == NULL); 194 BUG_ON(mpic == NULL);
209
210 /* Return the mpic node */
211 of_node_put(np);
212
213 mpic_init(mpic); 195 mpic_init(mpic);
214} 196}
215 197
@@ -330,19 +312,7 @@ static int __init mpc85xx_cds_probe(void)
330 return of_flat_dt_is_compatible(root, "MPC85xxCDS"); 312 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
331} 313}
332 314
333static struct of_device_id __initdata of_bus_ids[] = { 315machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
334 { .type = "soc", },
335 { .compatible = "soc", },
336 { .compatible = "simple-bus", },
337 { .compatible = "gianfar", },
338 {},
339};
340
341static int __init declare_of_platform_devices(void)
342{
343 return of_platform_bus_probe(NULL, of_bus_ids, NULL);
344}
345machine_device_initcall(mpc85xx_cds, declare_of_platform_devices);
346 316
347define_machine(mpc85xx_cds) { 317define_machine(mpc85xx_cds) {
348 .name = "MPC85xx CDS", 318 .name = "MPC85xx CDS",
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 1b9a8cf1873..eefbb91e1d6 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -35,6 +35,9 @@
35 35
36#include <sysdev/fsl_soc.h> 36#include <sysdev/fsl_soc.h>
37#include <sysdev/fsl_pci.h> 37#include <sysdev/fsl_pci.h>
38#include "smp.h"
39
40#include "mpc85xx.h"
38 41
39#undef DEBUG 42#undef DEBUG
40 43
@@ -60,43 +63,27 @@ static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
60void __init mpc85xx_ds_pic_init(void) 63void __init mpc85xx_ds_pic_init(void)
61{ 64{
62 struct mpic *mpic; 65 struct mpic *mpic;
63 struct resource r;
64 struct device_node *np;
65#ifdef CONFIG_PPC_I8259 66#ifdef CONFIG_PPC_I8259
67 struct device_node *np;
66 struct device_node *cascade_node = NULL; 68 struct device_node *cascade_node = NULL;
67 int cascade_irq; 69 int cascade_irq;
68#endif 70#endif
69 unsigned long root = of_get_flat_dt_root(); 71 unsigned long root = of_get_flat_dt_root();
70 72
71 np = of_find_node_by_type(NULL, "open-pic");
72 if (np == NULL) {
73 printk(KERN_ERR "Could not find open-pic node\n");
74 return;
75 }
76
77 if (of_address_to_resource(np, 0, &r)) {
78 printk(KERN_ERR "Failed to map mpic register space\n");
79 of_node_put(np);
80 return;
81 }
82
83 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) { 73 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
84 mpic = mpic_alloc(np, r.start, 74 mpic = mpic_alloc(NULL, 0,
85 MPIC_PRIMARY |
86 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 75 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
87 MPIC_SINGLE_DEST_CPU, 76 MPIC_SINGLE_DEST_CPU,
88 0, 256, " OpenPIC "); 77 0, 256, " OpenPIC ");
89 } else { 78 } else {
90 mpic = mpic_alloc(np, r.start, 79 mpic = mpic_alloc(NULL, 0,
91 MPIC_PRIMARY | MPIC_WANTS_RESET | 80 MPIC_WANTS_RESET |
92 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 81 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
93 MPIC_SINGLE_DEST_CPU, 82 MPIC_SINGLE_DEST_CPU,
94 0, 256, " OpenPIC "); 83 0, 256, " OpenPIC ");
95 } 84 }
96 85
97 BUG_ON(mpic == NULL); 86 BUG_ON(mpic == NULL);
98 of_node_put(np);
99
100 mpic_init(mpic); 87 mpic_init(mpic);
101 88
102#ifdef CONFIG_PPC_I8259 89#ifdef CONFIG_PPC_I8259
@@ -152,9 +139,6 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
152/* 139/*
153 * Setup the architecture 140 * Setup the architecture
154 */ 141 */
155#ifdef CONFIG_SMP
156extern void __init mpc85xx_smp_init(void);
157#endif
158static void __init mpc85xx_ds_setup_arch(void) 142static void __init mpc85xx_ds_setup_arch(void)
159{ 143{
160#ifdef CONFIG_PCI 144#ifdef CONFIG_PCI
@@ -187,9 +171,7 @@ static void __init mpc85xx_ds_setup_arch(void)
187 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 171 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
188#endif 172#endif
189 173
190#ifdef CONFIG_SMP
191 mpc85xx_smp_init(); 174 mpc85xx_smp_init();
192#endif
193 175
194#ifdef CONFIG_SWIOTLB 176#ifdef CONFIG_SWIOTLB
195 if (memblock_end_of_DRAM() > max) { 177 if (memblock_end_of_DRAM() > max) {
@@ -219,21 +201,9 @@ static int __init mpc8544_ds_probe(void)
219 return 0; 201 return 0;
220} 202}
221 203
222static struct of_device_id __initdata mpc85xxds_ids[] = { 204machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
223 { .type = "soc", }, 205machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
224 { .compatible = "soc", }, 206machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices);
225 { .compatible = "simple-bus", },
226 { .compatible = "gianfar", },
227 {},
228};
229
230static int __init mpc85xxds_publish_devices(void)
231{
232 return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
233}
234machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
235machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
236machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
237 207
238machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); 208machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
239machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); 209machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a23a3ff634c..1d15a0cd2c8 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,9 @@
51#include <asm/qe_ic.h> 51#include <asm/qe_ic.h>
52#include <asm/mpic.h> 52#include <asm/mpic.h>
53#include <asm/swiotlb.h> 53#include <asm/swiotlb.h>
54#include "smp.h"
55
56#include "mpc85xx.h"
54 57
55#undef DEBUG 58#undef DEBUG
56#ifdef DEBUG 59#ifdef DEBUG
@@ -153,30 +156,7 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
153 * Setup the architecture 156 * Setup the architecture
154 * 157 *
155 */ 158 */
156#ifdef CONFIG_SMP
157extern void __init mpc85xx_smp_init(void);
158#endif
159
160#ifdef CONFIG_QUICC_ENGINE 159#ifdef CONFIG_QUICC_ENGINE
161static struct of_device_id mpc85xx_qe_ids[] __initdata = {
162 { .type = "qe", },
163 { .compatible = "fsl,qe", },
164 { },
165};
166
167static void __init mpc85xx_publish_qe_devices(void)
168{
169 struct device_node *np;
170
171 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
172 if (!of_device_is_available(np)) {
173 of_node_put(np);
174 return;
175 }
176
177 of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
178}
179
180static void __init mpc85xx_mds_reset_ucc_phys(void) 160static void __init mpc85xx_mds_reset_ucc_phys(void)
181{ 161{
182 struct device_node *np; 162 struct device_node *np;
@@ -347,7 +327,6 @@ static void __init mpc85xx_mds_qeic_init(void)
347 of_node_put(np); 327 of_node_put(np);
348} 328}
349#else 329#else
350static void __init mpc85xx_publish_qe_devices(void) { }
351static void __init mpc85xx_mds_qe_init(void) { } 330static void __init mpc85xx_mds_qe_init(void) { }
352static void __init mpc85xx_mds_qeic_init(void) { } 331static void __init mpc85xx_mds_qeic_init(void) { }
353#endif /* CONFIG_QUICC_ENGINE */ 332#endif /* CONFIG_QUICC_ENGINE */
@@ -381,9 +360,7 @@ static void __init mpc85xx_mds_setup_arch(void)
381 } 360 }
382#endif 361#endif
383 362
384#ifdef CONFIG_SMP
385 mpc85xx_smp_init(); 363 mpc85xx_smp_init();
386#endif
387 364
388 mpc85xx_mds_qe_init(); 365 mpc85xx_mds_qe_init();
389 366
@@ -429,24 +406,11 @@ machine_arch_initcall(mpc8568_mds, board_fixups);
429machine_arch_initcall(mpc8569_mds, board_fixups); 406machine_arch_initcall(mpc8569_mds, board_fixups);
430 407
431static struct of_device_id mpc85xx_ids[] = { 408static struct of_device_id mpc85xx_ids[] = {
432 { .type = "soc", },
433 { .compatible = "soc", },
434 { .compatible = "simple-bus", },
435 { .compatible = "gianfar", },
436 { .compatible = "fsl,rapidio-delta", },
437 { .compatible = "fsl,mpc8548-guts", }, 409 { .compatible = "fsl,mpc8548-guts", },
438 { .compatible = "gpio-leds", }, 410 { .compatible = "gpio-leds", },
439 {}, 411 {},
440}; 412};
441 413
442static struct of_device_id p1021_ids[] = {
443 { .type = "soc", },
444 { .compatible = "soc", },
445 { .compatible = "simple-bus", },
446 { .compatible = "gianfar", },
447 {},
448};
449
450static int __init mpc85xx_publish_devices(void) 414static int __init mpc85xx_publish_devices(void)
451{ 415{
452 if (machine_is(mpc8568_mds)) 416 if (machine_is(mpc8568_mds))
@@ -454,23 +418,15 @@ static int __init mpc85xx_publish_devices(void)
454 if (machine_is(mpc8569_mds)) 418 if (machine_is(mpc8569_mds))
455 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); 419 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
456 420
421 mpc85xx_common_publish_devices();
457 of_platform_bus_probe(NULL, mpc85xx_ids, NULL); 422 of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
458 mpc85xx_publish_qe_devices();
459
460 return 0;
461}
462
463static int __init p1021_publish_devices(void)
464{
465 of_platform_bus_probe(NULL, p1021_ids, NULL);
466 mpc85xx_publish_qe_devices();
467 423
468 return 0; 424 return 0;
469} 425}
470 426
471machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 427machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
472machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 428machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
473machine_device_initcall(p1021_mds, p1021_publish_devices); 429machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices);
474 430
475machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 431machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
476machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 432machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
@@ -478,26 +434,11 @@ machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
478 434
479static void __init mpc85xx_mds_pic_init(void) 435static void __init mpc85xx_mds_pic_init(void)
480{ 436{
481 struct mpic *mpic; 437 struct mpic *mpic = mpic_alloc(NULL, 0,
482 struct resource r; 438 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
483 struct device_node *np = NULL;
484
485 np = of_find_node_by_type(NULL, "open-pic");
486 if (!np)
487 return;
488
489 if (of_address_to_resource(np, 0, &r)) {
490 printk(KERN_ERR "Failed to map mpic register space\n");
491 of_node_put(np);
492 return;
493 }
494
495 mpic = mpic_alloc(np, r.start,
496 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
497 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 439 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
498 0, 256, " OpenPIC "); 440 0, 256, " OpenPIC ");
499 BUG_ON(mpic == NULL); 441 BUG_ON(mpic == NULL);
500 of_node_put(np);
501 442
502 mpic_init(mpic); 443 mpic_init(mpic);
503 mpc85xx_mds_qeic_init(); 444 mpc85xx_mds_qeic_init();
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index f5ff9110c97..ccf520e890b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -29,6 +29,9 @@
29 29
30#include <sysdev/fsl_soc.h> 30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h> 31#include <sysdev/fsl_pci.h>
32#include "smp.h"
33
34#include "mpc85xx.h"
32 35
33#undef DEBUG 36#undef DEBUG
34 37
@@ -42,49 +45,28 @@
42void __init mpc85xx_rdb_pic_init(void) 45void __init mpc85xx_rdb_pic_init(void)
43{ 46{
44 struct mpic *mpic; 47 struct mpic *mpic;
45 struct resource r;
46 struct device_node *np;
47 unsigned long root = of_get_flat_dt_root(); 48 unsigned long root = of_get_flat_dt_root();
48 49
49 np = of_find_node_by_type(NULL, "open-pic");
50 if (np == NULL) {
51 printk(KERN_ERR "Could not find open-pic node\n");
52 return;
53 }
54
55 if (of_address_to_resource(np, 0, &r)) {
56 printk(KERN_ERR "Failed to map mpic register space\n");
57 of_node_put(np);
58 return;
59 }
60
61 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { 50 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
62 mpic = mpic_alloc(np, r.start, 51 mpic = mpic_alloc(NULL, 0,
63 MPIC_PRIMARY |
64 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 52 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
65 MPIC_SINGLE_DEST_CPU, 53 MPIC_SINGLE_DEST_CPU,
66 0, 256, " OpenPIC "); 54 0, 256, " OpenPIC ");
67 } else { 55 } else {
68 mpic = mpic_alloc(np, r.start, 56 mpic = mpic_alloc(NULL, 0,
69 MPIC_PRIMARY | MPIC_WANTS_RESET | 57 MPIC_WANTS_RESET |
70 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 58 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
71 MPIC_SINGLE_DEST_CPU, 59 MPIC_SINGLE_DEST_CPU,
72 0, 256, " OpenPIC "); 60 0, 256, " OpenPIC ");
73 } 61 }
74 62
75 BUG_ON(mpic == NULL); 63 BUG_ON(mpic == NULL);
76 of_node_put(np);
77
78 mpic_init(mpic); 64 mpic_init(mpic);
79
80} 65}
81 66
82/* 67/*
83 * Setup the architecture 68 * Setup the architecture
84 */ 69 */
85#ifdef CONFIG_SMP
86extern void __init mpc85xx_smp_init(void);
87#endif
88static void __init mpc85xx_rdb_setup_arch(void) 70static void __init mpc85xx_rdb_setup_arch(void)
89{ 71{
90#ifdef CONFIG_PCI 72#ifdef CONFIG_PCI
@@ -102,27 +84,12 @@ static void __init mpc85xx_rdb_setup_arch(void)
102 84
103#endif 85#endif
104 86
105#ifdef CONFIG_SMP
106 mpc85xx_smp_init(); 87 mpc85xx_smp_init();
107#endif
108
109 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 88 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
110} 89}
111 90
112static struct of_device_id __initdata mpc85xxrdb_ids[] = { 91machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
113 { .type = "soc", }, 92machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
114 { .compatible = "soc", },
115 { .compatible = "simple-bus", },
116 { .compatible = "gianfar", },
117 {},
118};
119
120static int __init mpc85xxrdb_publish_devices(void)
121{
122 return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
123}
124machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
125machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);
126 93
127/* 94/*
128 * Called very early, device-tree isn't unflattened 95 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index d7387fa7f53..538bc3f57e9 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -28,33 +28,18 @@
28#include <sysdev/fsl_soc.h> 28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h> 29#include <sysdev/fsl_pci.h>
30 30
31#include "mpc85xx.h"
32
31void __init p1010_rdb_pic_init(void) 33void __init p1010_rdb_pic_init(void)
32{ 34{
33 struct mpic *mpic; 35 struct mpic *mpic = mpic_alloc(NULL, 0,
34 struct resource r; 36 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
35 struct device_node *np; 37 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
36
37 np = of_find_node_by_type(NULL, "open-pic");
38 if (np == NULL) {
39 printk(KERN_ERR "Could not find open-pic node\n");
40 return;
41 }
42
43 if (of_address_to_resource(np, 0, &r)) {
44 printk(KERN_ERR "Failed to map mpic register space\n");
45 of_node_put(np);
46 return;
47 }
48
49 mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET |
50 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
51 0, 256, " OpenPIC "); 38 0, 256, " OpenPIC ");
52 39
53 BUG_ON(mpic == NULL); 40 BUG_ON(mpic == NULL);
54 of_node_put(np);
55 41
56 mpic_init(mpic); 42 mpic_init(mpic);
57
58} 43}
59 44
60 45
@@ -81,18 +66,7 @@ static void __init p1010_rdb_setup_arch(void)
81 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n"); 66 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
82} 67}
83 68
84static struct of_device_id __initdata p1010rdb_ids[] = { 69machine_device_initcall(p1010_rdb, mpc85xx_common_publish_devices);
85 { .type = "soc", },
86 { .compatible = "soc", },
87 { .compatible = "simple-bus", },
88 {},
89};
90
91static int __init p1010rdb_publish_devices(void)
92{
93 return of_platform_bus_probe(NULL, p1010rdb_ids, NULL);
94}
95machine_device_initcall(p1010_rdb, p1010rdb_publish_devices);
96machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier); 70machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
97 71
98/* 72/*
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index fda15716fad..bb3d84f4046 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -26,6 +26,9 @@
26#include <sysdev/fsl_soc.h> 26#include <sysdev/fsl_soc.h>
27#include <sysdev/fsl_pci.h> 27#include <sysdev/fsl_pci.h>
28#include <asm/fsl_guts.h> 28#include <asm/fsl_guts.h>
29#include "smp.h"
30
31#include "mpc85xx.h"
29 32
30#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 33#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
31 34
@@ -238,38 +241,15 @@ p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
238 241
239void __init p1022_ds_pic_init(void) 242void __init p1022_ds_pic_init(void)
240{ 243{
241 struct mpic *mpic; 244 struct mpic *mpic = mpic_alloc(NULL, 0,
242 struct resource r; 245 MPIC_WANTS_RESET |
243 struct device_node *np;
244
245 np = of_find_node_by_type(NULL, "open-pic");
246 if (!np) {
247 pr_err("Could not find open-pic node\n");
248 return;
249 }
250
251 if (of_address_to_resource(np, 0, &r)) {
252 pr_err("Failed to map mpic register space\n");
253 of_node_put(np);
254 return;
255 }
256
257 mpic = mpic_alloc(np, r.start,
258 MPIC_PRIMARY | MPIC_WANTS_RESET |
259 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 246 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
260 MPIC_SINGLE_DEST_CPU, 247 MPIC_SINGLE_DEST_CPU,
261 0, 256, " OpenPIC "); 248 0, 256, " OpenPIC ");
262
263 BUG_ON(mpic == NULL); 249 BUG_ON(mpic == NULL);
264 of_node_put(np);
265
266 mpic_init(mpic); 250 mpic_init(mpic);
267} 251}
268 252
269#ifdef CONFIG_SMP
270void __init mpc85xx_smp_init(void);
271#endif
272
273/* 253/*
274 * Setup the architecture 254 * Setup the architecture
275 */ 255 */
@@ -309,9 +289,7 @@ static void __init p1022_ds_setup_arch(void)
309 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 289 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
310#endif 290#endif
311 291
312#ifdef CONFIG_SMP
313 mpc85xx_smp_init(); 292 mpc85xx_smp_init();
314#endif
315 293
316#ifdef CONFIG_SWIOTLB 294#ifdef CONFIG_SWIOTLB
317 if (memblock_end_of_DRAM() > max) { 295 if (memblock_end_of_DRAM() > max) {
@@ -325,10 +303,6 @@ static void __init p1022_ds_setup_arch(void)
325} 303}
326 304
327static struct of_device_id __initdata p1022_ds_ids[] = { 305static struct of_device_id __initdata p1022_ds_ids[] = {
328 { .type = "soc", },
329 { .compatible = "soc", },
330 { .compatible = "simple-bus", },
331 { .compatible = "gianfar", },
332 /* So that the DMA channel nodes can be probed individually: */ 306 /* So that the DMA channel nodes can be probed individually: */
333 { .compatible = "fsl,eloplus-dma", }, 307 { .compatible = "fsl,eloplus-dma", },
334 {}, 308 {},
@@ -336,6 +310,7 @@ static struct of_device_id __initdata p1022_ds_ids[] = {
336 310
337static int __init p1022_ds_publish_devices(void) 311static int __init p1022_ds_publish_devices(void)
338{ 312{
313 mpc85xx_common_publish_devices();
339 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); 314 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
340} 315}
341machine_device_initcall(p1022_ds, p1022_ds_publish_devices); 316machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 835e0b335bf..d951e7027bb 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -30,19 +30,18 @@
30#include <asm/prom.h> 30#include <asm/prom.h>
31#include <asm/udbg.h> 31#include <asm/udbg.h>
32#include <asm/mpic.h> 32#include <asm/mpic.h>
33#include "smp.h"
33 34
34#include <sysdev/fsl_soc.h> 35#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h> 36#include <sysdev/fsl_pci.h>
36 37
38#include "mpc85xx.h"
39
37/* ************************************************************************ 40/* ************************************************************************
38 * 41 *
39 * Setup the architecture 42 * Setup the architecture
40 * 43 *
41 */ 44 */
42#ifdef CONFIG_SMP
43void __init mpc85xx_smp_init(void);
44#endif
45
46static void __init mpc85xx_rds_setup_arch(void) 45static void __init mpc85xx_rds_setup_arch(void)
47{ 46{
48 struct device_node *np; 47 struct device_node *np;
@@ -87,53 +86,19 @@ static void __init mpc85xx_rds_setup_arch(void)
87 fsl_add_bridge(np, 0); 86 fsl_add_bridge(np, 0);
88#endif 87#endif
89 88
90#ifdef CONFIG_SMP
91 mpc85xx_smp_init(); 89 mpc85xx_smp_init();
92#endif
93}
94
95static struct of_device_id p1023_ids[] = {
96 { .type = "soc", },
97 { .compatible = "soc", },
98 { .compatible = "simple-bus", },
99 {},
100};
101
102
103static int __init p1023_publish_devices(void)
104{
105 of_platform_bus_probe(NULL, p1023_ids, NULL);
106
107 return 0;
108} 90}
109 91
110machine_device_initcall(p1023_rds, p1023_publish_devices); 92machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices);
111 93
112static void __init mpc85xx_rds_pic_init(void) 94static void __init mpc85xx_rds_pic_init(void)
113{ 95{
114 struct mpic *mpic; 96 struct mpic *mpic = mpic_alloc(NULL, 0,
115 struct resource r; 97 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
116 struct device_node *np = NULL;
117
118 np = of_find_node_by_type(NULL, "open-pic");
119 if (!np) {
120 printk(KERN_ERR "Could not find open-pic node\n");
121 return;
122 }
123
124 if (of_address_to_resource(np, 0, &r)) {
125 printk(KERN_ERR "Failed to map mpic register space\n");
126 of_node_put(np);
127 return;
128 }
129
130 mpic = mpic_alloc(np, r.start,
131 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
132 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 98 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
133 0, 256, " OpenPIC "); 99 0, 256, " OpenPIC ");
134 100
135 BUG_ON(mpic == NULL); 101 BUG_ON(mpic == NULL);
136 of_node_put(np);
137 102
138 mpic_init(mpic); 103 mpic_init(mpic);
139} 104}
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index 14632a97122..184a5078461 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -48,35 +48,16 @@
48#include <sysdev/fsl_soc.h> 48#include <sysdev/fsl_soc.h>
49#include <sysdev/fsl_pci.h> 49#include <sysdev/fsl_pci.h>
50 50
51#include "mpc85xx.h"
52
51static int sbc_rev; 53static int sbc_rev;
52 54
53static void __init sbc8548_pic_init(void) 55static void __init sbc8548_pic_init(void)
54{ 56{
55 struct mpic *mpic; 57 struct mpic *mpic = mpic_alloc(NULL, 0,
56 struct resource r; 58 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
57 struct device_node *np = NULL;
58
59 np = of_find_node_by_type(np, "open-pic");
60
61 if (np == NULL) {
62 printk(KERN_ERR "Could not find open-pic node\n");
63 return;
64 }
65
66 if (of_address_to_resource(np, 0, &r)) {
67 printk(KERN_ERR "Failed to map mpic register space\n");
68 of_node_put(np);
69 return;
70 }
71
72 mpic = mpic_alloc(np, r.start,
73 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
74 0, 256, " OpenPIC "); 59 0, 256, " OpenPIC ");
75 BUG_ON(mpic == NULL); 60 BUG_ON(mpic == NULL);
76
77 /* Return the mpic node */
78 of_node_put(np);
79
80 mpic_init(mpic); 61 mpic_init(mpic);
81} 62}
82 63
@@ -149,21 +130,7 @@ static void sbc8548_show_cpuinfo(struct seq_file *m)
149 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 130 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
150} 131}
151 132
152static struct of_device_id __initdata of_bus_ids[] = { 133machine_device_initcall(sbc8548, mpc85xx_common_publish_devices);
153 { .name = "soc", },
154 { .type = "soc", },
155 { .compatible = "simple-bus", },
156 { .compatible = "gianfar", },
157 {},
158};
159
160static int __init declare_of_platform_devices(void)
161{
162 of_platform_bus_probe(NULL, of_bus_ids, NULL);
163
164 return 0;
165}
166machine_device_initcall(sbc8548, declare_of_platform_devices);
167 134
168/* 135/*
169 * Called very early, device-tree isn't unflattened 136 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index cebd786dc33..940752e9305 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -32,68 +32,22 @@
32#include <sysdev/fsl_soc.h> 32#include <sysdev/fsl_soc.h>
33#include <sysdev/fsl_pci.h> 33#include <sysdev/fsl_pci.h>
34 34
35#include "mpc85xx.h"
36
35#ifdef CONFIG_CPM2 37#ifdef CONFIG_CPM2
36#include <asm/cpm2.h> 38#include <asm/cpm2.h>
37#include <sysdev/cpm2_pic.h> 39#include <sysdev/cpm2_pic.h>
38#endif 40#endif
39 41
40#ifdef CONFIG_CPM2
41
42static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
43{
44 struct irq_chip *chip = irq_desc_get_chip(desc);
45 int cascade_irq;
46
47 while ((cascade_irq = cpm2_get_irq()) >= 0)
48 generic_handle_irq(cascade_irq);
49
50 chip->irq_eoi(&desc->irq_data);
51}
52
53#endif /* CONFIG_CPM2 */
54
55static void __init sbc8560_pic_init(void) 42static void __init sbc8560_pic_init(void)
56{ 43{
57 struct mpic *mpic; 44 struct mpic *mpic = mpic_alloc(NULL, 0,
58 struct resource r; 45 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
59 struct device_node *np = NULL;
60#ifdef CONFIG_CPM2
61 int irq;
62#endif
63
64 np = of_find_node_by_type(np, "open-pic");
65 if (!np) {
66 printk(KERN_ERR "Could not find open-pic node\n");
67 return;
68 }
69
70 if (of_address_to_resource(np, 0, &r)) {
71 printk(KERN_ERR "Could not map mpic register space\n");
72 of_node_put(np);
73 return;
74 }
75
76 mpic = mpic_alloc(np, r.start,
77 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
78 0, 256, " OpenPIC "); 46 0, 256, " OpenPIC ");
79 BUG_ON(mpic == NULL); 47 BUG_ON(mpic == NULL);
80 of_node_put(np);
81
82 mpic_init(mpic); 48 mpic_init(mpic);
83 49
84#ifdef CONFIG_CPM2 50 mpc85xx_cpm2_pic_init();
85 /* Setup CPM2 PIC */
86 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
87 if (np == NULL) {
88 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
89 return;
90 }
91 irq = irq_of_parse_and_map(np, 0);
92
93 cpm2_pic_init(np);
94 of_node_put(np);
95 irq_set_chained_handler(irq, cpm2_cascade);
96#endif
97} 51}
98 52
99/* 53/*
@@ -208,23 +162,7 @@ static void sbc8560_show_cpuinfo(struct seq_file *m)
208 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 162 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
209} 163}
210 164
211static struct of_device_id __initdata of_bus_ids[] = { 165machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
212 { .name = "soc", },
213 { .type = "soc", },
214 { .name = "cpm", },
215 { .name = "localbus", },
216 { .compatible = "simple-bus", },
217 { .compatible = "gianfar", },
218 {},
219};
220
221static int __init declare_of_platform_devices(void)
222{
223 of_platform_bus_probe(NULL, of_bus_ids, NULL);
224
225 return 0;
226}
227machine_device_initcall(sbc8560, declare_of_platform_devices);
228 166
229/* 167/*
230 * Called very early, device-tree isn't unflattened 168 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 2df4785ffd4..ff4249044a3 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -27,6 +27,7 @@
27 27
28#include <sysdev/fsl_soc.h> 28#include <sysdev/fsl_soc.h>
29#include <sysdev/mpic.h> 29#include <sysdev/mpic.h>
30#include "smp.h"
30 31
31extern void __early_start(void); 32extern void __early_start(void);
32 33
diff --git a/arch/powerpc/platforms/85xx/smp.h b/arch/powerpc/platforms/85xx/smp.h
new file mode 100644
index 00000000000..e2b44933ff1
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/smp.h
@@ -0,0 +1,15 @@
1#ifndef POWERPC_85XX_SMP_H_
2#define POWERPC_85XX_SMP_H_ 1
3
4#include <linux/init.h>
5
6#ifdef CONFIG_SMP
7void __init mpc85xx_smp_init(void);
8#else
9static inline void mpc85xx_smp_init(void)
10{
11 /* Nothing to do */
12}
13#endif
14
15#endif /* not POWERPC_85XX_SMP_H_ */
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index 747d8fb3ab8..18f635906b2 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -41,32 +41,17 @@
41#include <sysdev/fsl_soc.h> 41#include <sysdev/fsl_soc.h>
42#include <sysdev/fsl_pci.h> 42#include <sysdev/fsl_pci.h>
43 43
44#include "mpc85xx.h"
44#include "socrates_fpga_pic.h" 45#include "socrates_fpga_pic.h"
45 46
46static void __init socrates_pic_init(void) 47static void __init socrates_pic_init(void)
47{ 48{
48 struct mpic *mpic;
49 struct resource r;
50 struct device_node *np; 49 struct device_node *np;
51 50
52 np = of_find_node_by_type(NULL, "open-pic"); 51 struct mpic *mpic = mpic_alloc(NULL, 0,
53 if (!np) { 52 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
54 printk(KERN_ERR "Could not find open-pic node\n");
55 return;
56 }
57
58 if (of_address_to_resource(np, 0, &r)) {
59 printk(KERN_ERR "Could not map mpic register space\n");
60 of_node_put(np);
61 return;
62 }
63
64 mpic = mpic_alloc(np, r.start,
65 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
66 0, 256, " OpenPIC "); 53 0, 256, " OpenPIC ");
67 BUG_ON(mpic == NULL); 54 BUG_ON(mpic == NULL);
68 of_node_put(np);
69
70 mpic_init(mpic); 55 mpic_init(mpic);
71 56
72 np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic"); 57 np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic");
@@ -96,17 +81,7 @@ static void __init socrates_setup_arch(void)
96#endif 81#endif
97} 82}
98 83
99static struct of_device_id __initdata socrates_of_bus_ids[] = { 84machine_device_initcall(socrates, mpc85xx_common_publish_devices);
100 { .compatible = "simple-bus", },
101 { .compatible = "gianfar", },
102 {},
103};
104
105static int __init socrates_publish_devices(void)
106{
107 return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL);
108}
109machine_device_initcall(socrates, socrates_publish_devices);
110 85
111/* 86/*
112 * Called very early, device-tree isn't unflattened 87 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index 5387e9f06bd..e9e5234b4e7 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -40,70 +40,21 @@
40#include <sysdev/fsl_soc.h> 40#include <sysdev/fsl_soc.h>
41#include <sysdev/fsl_pci.h> 41#include <sysdev/fsl_pci.h>
42 42
43#include "mpc85xx.h"
44
43#ifdef CONFIG_CPM2 45#ifdef CONFIG_CPM2
44#include <asm/cpm2.h> 46#include <asm/cpm2.h>
45#include <sysdev/cpm2_pic.h>
46
47static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
48{
49 struct irq_chip *chip = irq_desc_get_chip(desc);
50 int cascade_irq;
51
52 while ((cascade_irq = cpm2_get_irq()) >= 0)
53 generic_handle_irq(cascade_irq);
54
55 chip->irq_eoi(&desc->irq_data);
56}
57#endif /* CONFIG_CPM2 */ 47#endif /* CONFIG_CPM2 */
58 48
59static void __init stx_gp3_pic_init(void) 49static void __init stx_gp3_pic_init(void)
60{ 50{
61 struct mpic *mpic; 51 struct mpic *mpic = mpic_alloc(NULL, 0,
62 struct resource r; 52 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
63 struct device_node *np;
64#ifdef CONFIG_CPM2
65 int irq;
66#endif
67
68 np = of_find_node_by_type(NULL, "open-pic");
69 if (!np) {
70 printk(KERN_ERR "Could not find open-pic node\n");
71 return;
72 }
73
74 if (of_address_to_resource(np, 0, &r)) {
75 printk(KERN_ERR "Could not map mpic register space\n");
76 of_node_put(np);
77 return;
78 }
79
80 mpic = mpic_alloc(np, r.start,
81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
82 0, 256, " OpenPIC "); 53 0, 256, " OpenPIC ");
83 BUG_ON(mpic == NULL); 54 BUG_ON(mpic == NULL);
84 of_node_put(np);
85
86 mpic_init(mpic); 55 mpic_init(mpic);
87 56
88#ifdef CONFIG_CPM2 57 mpc85xx_cpm2_pic_init();
89 /* Setup CPM2 PIC */
90 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
91 if (np == NULL) {
92 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
93 return;
94 }
95 irq = irq_of_parse_and_map(np, 0);
96
97 if (irq == NO_IRQ) {
98 of_node_put(np);
99 printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
100 return;
101 }
102
103 cpm2_pic_init(np);
104 of_node_put(np);
105 irq_set_chained_handler(irq, cpm2_cascade);
106#endif
107} 58}
108 59
109/* 60/*
@@ -144,19 +95,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
144 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 95 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
145} 96}
146 97
147static struct of_device_id __initdata of_bus_ids[] = { 98machine_device_initcall(stx_gp3, mpc85xx_common_publish_devices);
148 { .compatible = "simple-bus", },
149 { .compatible = "gianfar", },
150 {},
151};
152
153static int __init declare_of_platform_devices(void)
154{
155 of_platform_bus_probe(NULL, of_bus_ids, NULL);
156
157 return 0;
158}
159machine_device_initcall(stx_gp3, declare_of_platform_devices);
160 99
161/* 100/*
162 * Called very early, device-tree isn't unflattened 101 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 325de772725..bf7c89fb75b 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -38,70 +38,21 @@
38#include <sysdev/fsl_soc.h> 38#include <sysdev/fsl_soc.h>
39#include <sysdev/fsl_pci.h> 39#include <sysdev/fsl_pci.h>
40 40
41#include "mpc85xx.h"
42
41#ifdef CONFIG_CPM2 43#ifdef CONFIG_CPM2
42#include <asm/cpm2.h> 44#include <asm/cpm2.h>
43#include <sysdev/cpm2_pic.h>
44
45static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
46{
47 struct irq_chip *chip = irq_desc_get_chip(desc);
48 int cascade_irq;
49
50 while ((cascade_irq = cpm2_get_irq()) >= 0)
51 generic_handle_irq(cascade_irq);
52
53 chip->irq_eoi(&desc->irq_data);
54}
55#endif /* CONFIG_CPM2 */ 45#endif /* CONFIG_CPM2 */
56 46
57static void __init tqm85xx_pic_init(void) 47static void __init tqm85xx_pic_init(void)
58{ 48{
59 struct mpic *mpic; 49 struct mpic *mpic = mpic_alloc(NULL, 0,
60 struct resource r; 50 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
61 struct device_node *np;
62#ifdef CONFIG_CPM2
63 int irq;
64#endif
65
66 np = of_find_node_by_type(NULL, "open-pic");
67 if (!np) {
68 printk(KERN_ERR "Could not find open-pic node\n");
69 return;
70 }
71
72 if (of_address_to_resource(np, 0, &r)) {
73 printk(KERN_ERR "Could not map mpic register space\n");
74 of_node_put(np);
75 return;
76 }
77
78 mpic = mpic_alloc(np, r.start,
79 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
80 0, 256, " OpenPIC "); 51 0, 256, " OpenPIC ");
81 BUG_ON(mpic == NULL); 52 BUG_ON(mpic == NULL);
82 of_node_put(np);
83
84 mpic_init(mpic); 53 mpic_init(mpic);
85 54
86#ifdef CONFIG_CPM2 55 mpc85xx_cpm2_pic_init();
87 /* Setup CPM2 PIC */
88 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
89 if (np == NULL) {
90 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
91 return;
92 }
93 irq = irq_of_parse_and_map(np, 0);
94
95 if (irq == NO_IRQ) {
96 of_node_put(np);
97 printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
98 return;
99 }
100
101 cpm2_pic_init(np);
102 of_node_put(np);
103 irq_set_chained_handler(irq, cpm2_cascade);
104#endif
105} 56}
106 57
107/* 58/*
@@ -173,19 +124,7 @@ static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520, 124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
174 tqm85xx_ti1520_fixup); 125 tqm85xx_ti1520_fixup);
175 126
176static struct of_device_id __initdata of_bus_ids[] = { 127machine_device_initcall(tqm85xx, mpc85xx_common_publish_devices);
177 { .compatible = "simple-bus", },
178 { .compatible = "gianfar", },
179 {},
180};
181
182static int __init declare_of_platform_devices(void)
183{
184 of_platform_bus_probe(NULL, of_bus_ids, NULL);
185
186 return 0;
187}
188machine_device_initcall(tqm85xx, declare_of_platform_devices);
189 128
190static const char *board[] __initdata = { 129static const char *board[] __initdata = {
191 "tqc,tqm8540", 130 "tqc,tqm8540",
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index a9dc5e79512..3a69f8b77de 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -32,6 +32,9 @@
32 32
33#include <sysdev/fsl_soc.h> 33#include <sysdev/fsl_soc.h>
34#include <sysdev/fsl_pci.h> 34#include <sysdev/fsl_pci.h>
35#include "smp.h"
36
37#include "mpc85xx.h"
35 38
36/* A few bit definitions needed for fixups on some boards */ 39/* A few bit definitions needed for fixups on some boards */
37#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ 40#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
@@ -40,29 +43,11 @@
40 43
41void __init xes_mpc85xx_pic_init(void) 44void __init xes_mpc85xx_pic_init(void)
42{ 45{
43 struct mpic *mpic; 46 struct mpic *mpic = mpic_alloc(NULL, 0,
44 struct resource r; 47 MPIC_WANTS_RESET |
45 struct device_node *np;
46
47 np = of_find_node_by_type(NULL, "open-pic");
48 if (np == NULL) {
49 printk(KERN_ERR "Could not find open-pic node\n");
50 return;
51 }
52
53 if (of_address_to_resource(np, 0, &r)) {
54 printk(KERN_ERR "Failed to map mpic register space\n");
55 of_node_put(np);
56 return;
57 }
58
59 mpic = mpic_alloc(np, r.start,
60 MPIC_PRIMARY | MPIC_WANTS_RESET |
61 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, 48 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
62 0, 256, " OpenPIC "); 49 0, 256, " OpenPIC ");
63 BUG_ON(mpic == NULL); 50 BUG_ON(mpic == NULL);
64 of_node_put(np);
65
66 mpic_init(mpic); 51 mpic_init(mpic);
67} 52}
68 53
@@ -136,9 +121,6 @@ static int primary_phb_addr;
136/* 121/*
137 * Setup the architecture 122 * Setup the architecture
138 */ 123 */
139#ifdef CONFIG_SMP
140extern void __init mpc85xx_smp_init(void);
141#endif
142static void __init xes_mpc85xx_setup_arch(void) 124static void __init xes_mpc85xx_setup_arch(void)
143{ 125{
144#ifdef CONFIG_PCI 126#ifdef CONFIG_PCI
@@ -172,26 +154,12 @@ static void __init xes_mpc85xx_setup_arch(void)
172 } 154 }
173#endif 155#endif
174 156
175#ifdef CONFIG_SMP
176 mpc85xx_smp_init(); 157 mpc85xx_smp_init();
177#endif
178} 158}
179 159
180static struct of_device_id __initdata xes_mpc85xx_ids[] = { 160machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
181 { .type = "soc", }, 161machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
182 { .compatible = "soc", }, 162machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
183 { .compatible = "simple-bus", },
184 { .compatible = "gianfar", },
185 {},
186};
187
188static int __init xes_mpc85xx_publish_devices(void)
189{
190 return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
191}
192machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
193machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
194machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
195 163
196/* 164/*
197 * Called very early, device-tree isn't unflattened 165 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index b11c3535f35..569262ca499 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -161,7 +161,7 @@ mpc86xx_time_init(void)
161 161
162static __initdata struct of_device_id of_bus_ids[] = { 162static __initdata struct of_device_id of_bus_ids[] = {
163 { .compatible = "simple-bus", }, 163 { .compatible = "simple-bus", },
164 { .compatible = "fsl,rapidio-delta", }, 164 { .compatible = "fsl,srio", },
165 { .compatible = "gianfar", }, 165 { .compatible = "gianfar", },
166 {}, 166 {},
167}; 167};
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c
index 8ef8960abda..52bbfa03153 100644
--- a/arch/powerpc/platforms/86xx/pic.c
+++ b/arch/powerpc/platforms/86xx/pic.c
@@ -31,26 +31,16 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
31 31
32void __init mpc86xx_init_irq(void) 32void __init mpc86xx_init_irq(void)
33{ 33{
34 struct mpic *mpic;
35 struct device_node *np;
36 struct resource res;
37#ifdef CONFIG_PPC_I8259 34#ifdef CONFIG_PPC_I8259
35 struct device_node *np;
38 struct device_node *cascade_node = NULL; 36 struct device_node *cascade_node = NULL;
39 int cascade_irq; 37 int cascade_irq;
40#endif 38#endif
41 39
42 /* Determine PIC address. */ 40 struct mpic *mpic = mpic_alloc(NULL, 0,
43 np = of_find_node_by_type(NULL, "open-pic"); 41 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
44 if (np == NULL) 42 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
45 return;
46 of_address_to_resource(np, 0, &res);
47
48 mpic = mpic_alloc(np, res.start,
49 MPIC_PRIMARY | MPIC_WANTS_RESET |
50 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
51 MPIC_SINGLE_DEST_CPU,
52 0, 256, " MPIC "); 43 0, 256, " MPIC ");
53 of_node_put(np);
54 BUG_ON(mpic == NULL); 44 BUG_ON(mpic == NULL);
55 45
56 mpic_init(mpic); 46 mpic_init(mpic);
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 3fe6d927ad7..31e1adeaa92 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -211,6 +211,12 @@ config PPC_PASEMI_CPUFREQ
211 211
212endmenu 212endmenu
213 213
214menu "CPUIdle driver"
215
216source "drivers/cpuidle/Kconfig"
217
218endmenu
219
214config PPC601_SYNC_FIX 220config PPC601_SYNC_FIX
215 bool "Workarounds for PPC601 bugs" 221 bool "Workarounds for PPC601 bugs"
216 depends on 6xx && (PPC_PREP || PPC_PMAC) 222 depends on 6xx && (PPC_PREP || PPC_PMAC)
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index fbecae0fbb4..425db18580a 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -174,7 +174,6 @@ config BOOKE
174config FSL_BOOKE 174config FSL_BOOKE
175 bool 175 bool
176 depends on (E200 || E500) && PPC32 176 depends on (E200 || E500) && PPC32
177 select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT
178 default y 177 default y
179 178
180# this is for common code between PPC32 & PPC64 FSL BOOKE 179# this is for common code between PPC32 & PPC64 FSL BOOKE
@@ -182,6 +181,7 @@ config PPC_FSL_BOOK3E
182 bool 181 bool
183 select FSL_EMB_PERFMON 182 select FSL_EMB_PERFMON
184 select PPC_SMP_MUXED_IPI 183 select PPC_SMP_MUXED_IPI
184 select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
185 default y if FSL_BOOKE 185 default y if FSL_BOOKE
186 186
187config PTE_64BIT 187config PTE_64BIT
@@ -236,7 +236,7 @@ config VSX
236 236
237config PPC_ICSWX 237config PPC_ICSWX
238 bool "Support for PowerPC icswx coprocessor instruction" 238 bool "Support for PowerPC icswx coprocessor instruction"
239 depends on POWER4 239 depends on POWER4 || PPC_A2
240 default n 240 default n
241 ---help--- 241 ---help---
242 242
@@ -252,6 +252,25 @@ config PPC_ICSWX
252 252
253 If in doubt, say N here. 253 If in doubt, say N here.
254 254
255config PPC_ICSWX_PID
256 bool "icswx requires direct PID management"
257 depends on PPC_ICSWX && POWER4
258 default y
259 ---help---
260 The PID register in server is used explicitly for ICSWX. In
261 embedded systems PID managment is done by the system.
262
263config PPC_ICSWX_USE_SIGILL
264 bool "Should a bad CT cause a SIGILL?"
265 depends on PPC_ICSWX
266 default n
267 ---help---
268 Should a bad CT used for "non-record form ICSWX" cause an
269 illegal intruction signal or should it be silent as
270 architected.
271
272 If in doubt, say N here.
273
255config SPE 274config SPE
256 bool "SPE Support" 275 bool "SPE Support"
257 depends on E200 || (E500 && !PPC_E500MC) 276 depends on E200 || (E500 && !PPC_E500MC)
@@ -290,7 +309,7 @@ config PPC_BOOK3E_MMU
290 309
291config PPC_MM_SLICES 310config PPC_MM_SLICES
292 bool 311 bool
293 default y if (PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES) 312 default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
294 default n 313 default n
295 314
296config VIRT_CPU_ACCOUNTING 315config VIRT_CPU_ACCOUNTING
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 592c3d51b81..ae9fc7bc17d 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -1037,6 +1037,8 @@ static int __init cell_iommu_fixed_mapping_init(void)
1037 1037
1038 /* The fixed mapping is only supported on axon machines */ 1038 /* The fixed mapping is only supported on axon machines */
1039 np = of_find_node_by_name(NULL, "axon"); 1039 np = of_find_node_by_name(NULL, "axon");
1040 of_node_put(np);
1041
1040 if (!np) { 1042 if (!np) {
1041 pr_debug("iommu: fixed mapping disabled, no axons found\n"); 1043 pr_debug("iommu: fixed mapping disabled, no axons found\n");
1042 return -1; 1044 return -1;
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 0fc9b725612..62002a7edfe 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -184,24 +184,10 @@ static int __init cell_publish_devices(void)
184} 184}
185machine_subsys_initcall(cell, cell_publish_devices); 185machine_subsys_initcall(cell, cell_publish_devices);
186 186
187static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
188{
189 struct irq_chip *chip = irq_desc_get_chip(desc);
190 struct mpic *mpic = irq_desc_get_handler_data(desc);
191 unsigned int virq;
192
193 virq = mpic_get_one_irq(mpic);
194 if (virq != NO_IRQ)
195 generic_handle_irq(virq);
196
197 chip->irq_eoi(&desc->irq_data);
198}
199
200static void __init mpic_init_IRQ(void) 187static void __init mpic_init_IRQ(void)
201{ 188{
202 struct device_node *dn; 189 struct device_node *dn;
203 struct mpic *mpic; 190 struct mpic *mpic;
204 unsigned int virq;
205 191
206 for (dn = NULL; 192 for (dn = NULL;
207 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { 193 (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
@@ -211,19 +197,10 @@ static void __init mpic_init_IRQ(void)
211 /* The MPIC driver will get everything it needs from the 197 /* The MPIC driver will get everything it needs from the
212 * device-tree, just pass 0 to all arguments 198 * device-tree, just pass 0 to all arguments
213 */ 199 */
214 mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC "); 200 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY, 0, 0, " MPIC ");
215 if (mpic == NULL) 201 if (mpic == NULL)
216 continue; 202 continue;
217 mpic_init(mpic); 203 mpic_init(mpic);
218
219 virq = irq_of_parse_and_map(dn, 0);
220 if (virq == NO_IRQ)
221 continue;
222
223 printk(KERN_INFO "%s : hooking up to IRQ %d\n",
224 dn->full_name, virq);
225 irq_set_handler_data(virq, mpic);
226 irq_set_chained_handler(virq, cell_mpic_cascade);
227 } 204 }
228} 205}
229 206
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 12278649841..f1f17bb2c33 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -435,8 +435,7 @@ static void __init chrp_find_openpic(void)
435 if (len > 1) 435 if (len > 1)
436 isu_size = iranges[3]; 436 isu_size = iranges[3];
437 437
438 chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, 438 chrp_mpic = mpic_alloc(np, opaddr, 0, isu_size, 0, " MPIC ");
439 isu_size, 0, " MPIC ");
440 if (chrp_mpic == NULL) { 439 if (chrp_mpic == NULL) {
441 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 440 printk(KERN_ERR "Failed to allocate MPIC structure\n");
442 goto bail; 441 goto bail;
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index 2e9bcf6444c..9cfcf20c056 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -148,30 +148,14 @@ static void __init holly_setup_arch(void)
148static void __init holly_init_IRQ(void) 148static void __init holly_init_IRQ(void)
149{ 149{
150 struct mpic *mpic; 150 struct mpic *mpic;
151 phys_addr_t mpic_paddr = 0;
152 struct device_node *tsi_pic;
153#ifdef CONFIG_PCI 151#ifdef CONFIG_PCI
154 unsigned int cascade_pci_irq; 152 unsigned int cascade_pci_irq;
155 struct device_node *tsi_pci; 153 struct device_node *tsi_pci;
156 struct device_node *cascade_node = NULL; 154 struct device_node *cascade_node = NULL;
157#endif 155#endif
158 156
159 tsi_pic = of_find_node_by_type(NULL, "open-pic"); 157 mpic = mpic_alloc(NULL, 0,
160 if (tsi_pic) { 158 MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
161 unsigned int size;
162 const void *prop = of_get_property(tsi_pic, "reg", &size);
163 mpic_paddr = of_translate_address(tsi_pic, prop);
164 }
165
166 if (mpic_paddr == 0) {
167 printk(KERN_ERR "%s: No tsi108 PIC found !\n", __func__);
168 return;
169 }
170
171 pr_debug("%s: tsi108 pic phys_addr = 0x%x\n", __func__, (u32) mpic_paddr);
172
173 mpic = mpic_alloc(tsi_pic, mpic_paddr,
174 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
175 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, 159 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
176 24, 160 24,
177 NR_IRQS-4, /* num_sources used */ 161 NR_IRQS-4, /* num_sources used */
@@ -179,7 +163,7 @@ static void __init holly_init_IRQ(void)
179 163
180 BUG_ON(mpic == NULL); 164 BUG_ON(mpic == NULL);
181 165
182 mpic_assign_isu(mpic, 0, mpic_paddr + 0x100); 166 mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
183 167
184 mpic_init(mpic); 168 mpic_init(mpic);
185 169
@@ -204,7 +188,6 @@ static void __init holly_init_IRQ(void)
204#endif 188#endif
205 /* Configure MPIC outputs to CPU0 */ 189 /* Configure MPIC outputs to CPU0 */
206 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); 190 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
207 of_node_put(tsi_pic);
208} 191}
209 192
210void holly_show_cpuinfo(struct seq_file *m) 193void holly_show_cpuinfo(struct seq_file *m)
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index 244f997de79..bcfad92c9ce 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -81,29 +81,19 @@ static void __init linkstation_setup_arch(void)
81static void __init linkstation_init_IRQ(void) 81static void __init linkstation_init_IRQ(void)
82{ 82{
83 struct mpic *mpic; 83 struct mpic *mpic;
84 struct device_node *dnp;
85 const u32 *prop;
86 int size;
87 phys_addr_t paddr;
88 84
89 dnp = of_find_node_by_type(NULL, "open-pic"); 85 mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
90 if (dnp == NULL) 86 4, 32, " EPIC ");
91 return;
92
93 prop = of_get_property(dnp, "reg", &size);
94 paddr = (phys_addr_t)of_translate_address(dnp, prop);
95
96 mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, 4, 32, " EPIC ");
97 BUG_ON(mpic == NULL); 87 BUG_ON(mpic == NULL);
98 88
99 /* PCI IRQs */ 89 /* PCI IRQs */
100 mpic_assign_isu(mpic, 0, paddr + 0x10200); 90 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200);
101 91
102 /* I2C */ 92 /* I2C */
103 mpic_assign_isu(mpic, 1, paddr + 0x11000); 93 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000);
104 94
105 /* ttyS0, ttyS1 */ 95 /* ttyS0, ttyS1 */
106 mpic_assign_isu(mpic, 2, paddr + 0x11100); 96 mpic_assign_isu(mpic, 2, mpic->paddr + 0x11100);
107 97
108 mpic_init(mpic); 98 mpic_init(mpic);
109} 99}
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index f8f33e16c6b..f3350d786f5 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -102,31 +102,14 @@ static void __init mpc7448_hpc2_setup_arch(void)
102static void __init mpc7448_hpc2_init_IRQ(void) 102static void __init mpc7448_hpc2_init_IRQ(void)
103{ 103{
104 struct mpic *mpic; 104 struct mpic *mpic;
105 phys_addr_t mpic_paddr = 0;
106 struct device_node *tsi_pic;
107#ifdef CONFIG_PCI 105#ifdef CONFIG_PCI
108 unsigned int cascade_pci_irq; 106 unsigned int cascade_pci_irq;
109 struct device_node *tsi_pci; 107 struct device_node *tsi_pci;
110 struct device_node *cascade_node = NULL; 108 struct device_node *cascade_node = NULL;
111#endif 109#endif
112 110
113 tsi_pic = of_find_node_by_type(NULL, "open-pic"); 111 mpic = mpic_alloc(NULL, 0,
114 if (tsi_pic) { 112 MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
115 unsigned int size;
116 const void *prop = of_get_property(tsi_pic, "reg", &size);
117 mpic_paddr = of_translate_address(tsi_pic, prop);
118 }
119
120 if (mpic_paddr == 0) {
121 printk("%s: No tsi108 PIC found !\n", __func__);
122 return;
123 }
124
125 DBG("%s: tsi108 pic phys_addr = 0x%x\n", __func__,
126 (u32) mpic_paddr);
127
128 mpic = mpic_alloc(tsi_pic, mpic_paddr,
129 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
130 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, 113 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
131 24, 114 24,
132 NR_IRQS-4, /* num_sources used */ 115 NR_IRQS-4, /* num_sources used */
@@ -134,7 +117,7 @@ static void __init mpc7448_hpc2_init_IRQ(void)
134 117
135 BUG_ON(mpic == NULL); 118 BUG_ON(mpic == NULL);
136 119
137 mpic_assign_isu(mpic, 0, mpic_paddr + 0x100); 120 mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
138 121
139 mpic_init(mpic); 122 mpic_init(mpic);
140 123
@@ -159,7 +142,6 @@ static void __init mpc7448_hpc2_init_IRQ(void)
159#endif 142#endif
160 /* Configure MPIC outputs to CPU0 */ 143 /* Configure MPIC outputs to CPU0 */
161 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); 144 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
162 of_node_put(tsi_pic);
163} 145}
164 146
165void mpc7448_hpc2_show_cpuinfo(struct seq_file *m) 147void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index f1eebcae9bf..afa63883496 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -83,35 +83,17 @@ static void __init storcenter_setup_arch(void)
83static void __init storcenter_init_IRQ(void) 83static void __init storcenter_init_IRQ(void)
84{ 84{
85 struct mpic *mpic; 85 struct mpic *mpic;
86 struct device_node *dnp;
87 const void *prop;
88 int size;
89 phys_addr_t paddr;
90
91 dnp = of_find_node_by_type(NULL, "open-pic");
92 if (dnp == NULL)
93 return;
94
95 prop = of_get_property(dnp, "reg", &size);
96 if (prop == NULL) {
97 of_node_put(dnp);
98 return;
99 }
100
101 paddr = (phys_addr_t)of_translate_address(dnp, prop);
102 mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET,
103 16, 32, " OpenPIC ");
104
105 of_node_put(dnp);
106 86
87 mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
88 16, 32, " OpenPIC ");
107 BUG_ON(mpic == NULL); 89 BUG_ON(mpic == NULL);
108 90
109 /* 91 /*
110 * 16 Serial Interrupts followed by 16 Internal Interrupts. 92 * 16 Serial Interrupts followed by 16 Internal Interrupts.
111 * I2C is the second internal, so it is at 17, 0x11020. 93 * I2C is the second internal, so it is at 17, 0x11020.
112 */ 94 */
113 mpic_assign_isu(mpic, 0, paddr + 0x10200); 95 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200);
114 mpic_assign_isu(mpic, 1, paddr + 0x11000); 96 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000);
115 97
116 mpic_init(mpic); 98 mpic_init(mpic);
117} 99}
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index dd2e48b2850..401e3f3f74c 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -207,6 +207,54 @@ static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
207 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset); 207 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
208} 208}
209 209
210static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
211 int len, u32 *val)
212{
213 volatile void __iomem *addr;
214
215 addr = hose->cfg_addr;
216 addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
217
218 switch (len) {
219 case 1:
220 *val = in_8(addr);
221 break;
222 case 2:
223 *val = in_be16(addr);
224 break;
225 default:
226 *val = in_be32(addr);
227 break;
228 }
229
230 return PCIBIOS_SUCCESSFUL;
231}
232
233static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
234 int len, u32 val)
235{
236 volatile void __iomem *addr;
237
238 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
239
240 if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
241 return PCIBIOS_SUCCESSFUL;
242
243 switch (len) {
244 case 1:
245 out_8(addr, val);
246 break;
247 case 2:
248 out_be16(addr, val);
249 break;
250 default:
251 out_be32(addr, val);
252 break;
253 }
254
255 return PCIBIOS_SUCCESSFUL;
256}
257
210static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 258static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
211 int offset, int len, u32 *val) 259 int offset, int len, u32 *val)
212{ 260{
@@ -217,6 +265,9 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
217 if (hose == NULL) 265 if (hose == NULL)
218 return PCIBIOS_DEVICE_NOT_FOUND; 266 return PCIBIOS_DEVICE_NOT_FOUND;
219 267
268 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
269 return u3_ht_root_read_config(hose, offset, len, val);
270
220 if (offset > 0xff) 271 if (offset > 0xff)
221 return PCIBIOS_BAD_REGISTER_NUMBER; 272 return PCIBIOS_BAD_REGISTER_NUMBER;
222 273
@@ -252,6 +303,9 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
252 if (hose == NULL) 303 if (hose == NULL)
253 return PCIBIOS_DEVICE_NOT_FOUND; 304 return PCIBIOS_DEVICE_NOT_FOUND;
254 305
306 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
307 return u3_ht_root_write_config(hose, offset, len, val);
308
255 if (offset > 0xff) 309 if (offset > 0xff)
256 return PCIBIOS_BAD_REGISTER_NUMBER; 310 return PCIBIOS_BAD_REGISTER_NUMBER;
257 311
@@ -428,6 +482,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
428 * reg_property and using some accessor functions instead 482 * reg_property and using some accessor functions instead
429 */ 483 */
430 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 484 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
485 hose->cfg_addr = ioremap(0xf8070000, 0x1000);
431 486
432 hose->first_busno = 0; 487 hose->first_busno = 0;
433 hose->last_busno = 0xef; 488 hose->last_busno = 0xef;
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index 4c372047c94..0bcbfe7b2c5 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -221,7 +221,7 @@ static void __init maple_init_IRQ(void)
221 unsigned long openpic_addr = 0; 221 unsigned long openpic_addr = 0;
222 int naddr, n, i, opplen, has_isus = 0; 222 int naddr, n, i, opplen, has_isus = 0;
223 struct mpic *mpic; 223 struct mpic *mpic;
224 unsigned int flags = MPIC_PRIMARY; 224 unsigned int flags = 0;
225 225
226 /* Locate MPIC in the device-tree. Note that there is a bug 226 /* Locate MPIC in the device-tree. Note that there is a bug
227 * in Maple device-tree where the type of the controller is 227 * in Maple device-tree where the type of the controller is
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index 6f355821055..98b7a7c1317 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -224,7 +224,7 @@ static __init void pas_init_IRQ(void)
224 openpic_addr = of_read_number(opprop, naddr); 224 openpic_addr = of_read_number(opprop, naddr);
225 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); 225 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
226 226
227 mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS; 227 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
228 228
229 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 229 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
230 if (nmiprop) 230 if (nmiprop)
@@ -234,7 +234,7 @@ static __init void pas_init_IRQ(void)
234 mpic_flags, 0, 0, "PASEMI-OPIC"); 234 mpic_flags, 0, 0, "PASEMI-OPIC");
235 BUG_ON(!mpic); 235 BUG_ON(!mpic);
236 236
237 mpic_assign_isu(mpic, 0, openpic_addr + 0x10000); 237 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
238 mpic_init(mpic); 238 mpic_init(mpic);
239 /* The NMI/MCK source needs to be prio 15 */ 239 /* The NMI/MCK source needs to be prio 15 */
240 if (nmiprop) { 240 if (nmiprop) {
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 901bfbddc3d..7761aabfc29 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -52,13 +52,8 @@ struct device_node *of_irq_dflt_pic;
52/* Default addresses */ 52/* Default addresses */
53static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; 53static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
54 54
55#define GC_LEVEL_MASK 0x3ff00000
56#define OHARE_LEVEL_MASK 0x1ff00000
57#define HEATHROW_LEVEL_MASK 0x1ff00000
58
59static int max_irqs; 55static int max_irqs;
60static int max_real_irqs; 56static int max_real_irqs;
61static u32 level_mask[4];
62 57
63static DEFINE_RAW_SPINLOCK(pmac_pic_lock); 58static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
64 59
@@ -217,8 +212,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
217 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { 212 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
218 int i = irq >> 5; 213 int i = irq >> 5;
219 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 214 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
220 /* We must read level interrupts from the level register */ 215 bits |= in_le32(&pmac_irq_hw[i]->level);
221 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
222 bits &= ppc_cached_irq_mask[i]; 216 bits &= ppc_cached_irq_mask[i];
223 if (bits == 0) 217 if (bits == 0)
224 continue; 218 continue;
@@ -248,8 +242,7 @@ static unsigned int pmac_pic_get_irq(void)
248 for (irq = max_real_irqs; (irq -= 32) >= 0; ) { 242 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
249 int i = irq >> 5; 243 int i = irq >> 5;
250 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 244 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
251 /* We must read level interrupts from the level register */ 245 bits |= in_le32(&pmac_irq_hw[i]->level);
252 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
253 bits &= ppc_cached_irq_mask[i]; 246 bits &= ppc_cached_irq_mask[i];
254 if (bits == 0) 247 if (bits == 0)
255 continue; 248 continue;
@@ -284,19 +277,14 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
284static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, 277static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
285 irq_hw_number_t hw) 278 irq_hw_number_t hw)
286{ 279{
287 int level;
288
289 if (hw >= max_irqs) 280 if (hw >= max_irqs)
290 return -EINVAL; 281 return -EINVAL;
291 282
292 /* Mark level interrupts, set delayed disable for edge ones and set 283 /* Mark level interrupts, set delayed disable for edge ones and set
293 * handlers 284 * handlers
294 */ 285 */
295 level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); 286 irq_set_status_flags(virq, IRQ_LEVEL);
296 if (level) 287 irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
297 irq_set_status_flags(virq, IRQ_LEVEL);
298 irq_set_chip_and_handler(virq, &pmac_pic,
299 level ? handle_level_irq : handle_edge_irq);
300 return 0; 288 return 0;
301} 289}
302 290
@@ -334,21 +322,14 @@ static void __init pmac_pic_probe_oldstyle(void)
334 322
335 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { 323 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
336 max_irqs = max_real_irqs = 32; 324 max_irqs = max_real_irqs = 32;
337 level_mask[0] = GC_LEVEL_MASK;
338 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { 325 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
339 max_irqs = max_real_irqs = 32; 326 max_irqs = max_real_irqs = 32;
340 level_mask[0] = OHARE_LEVEL_MASK;
341
342 /* We might have a second cascaded ohare */ 327 /* We might have a second cascaded ohare */
343 slave = of_find_node_by_name(NULL, "pci106b,7"); 328 slave = of_find_node_by_name(NULL, "pci106b,7");
344 if (slave) { 329 if (slave)
345 max_irqs = 64; 330 max_irqs = 64;
346 level_mask[1] = OHARE_LEVEL_MASK;
347 }
348 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { 331 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
349 max_irqs = max_real_irqs = 64; 332 max_irqs = max_real_irqs = 64;
350 level_mask[0] = HEATHROW_LEVEL_MASK;
351 level_mask[1] = 0;
352 333
353 /* We might have a second cascaded heathrow */ 334 /* We might have a second cascaded heathrow */
354 slave = of_find_node_by_name(master, "mac-io"); 335 slave = of_find_node_by_name(master, "mac-io");
@@ -363,11 +344,8 @@ static void __init pmac_pic_probe_oldstyle(void)
363 } 344 }
364 345
365 /* We found a slave */ 346 /* We found a slave */
366 if (slave) { 347 if (slave)
367 max_irqs = 128; 348 max_irqs = 128;
368 level_mask[2] = HEATHROW_LEVEL_MASK;
369 level_mask[3] = 0;
370 }
371 } 349 }
372 BUG_ON(master == NULL); 350 BUG_ON(master == NULL);
373 351
@@ -464,18 +442,6 @@ int of_irq_map_oldworld(struct device_node *device, int index,
464} 442}
465#endif /* CONFIG_PPC32 */ 443#endif /* CONFIG_PPC32 */
466 444
467static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
468{
469 struct irq_chip *chip = irq_desc_get_chip(desc);
470 struct mpic *mpic = irq_desc_get_handler_data(desc);
471 unsigned int cascade_irq = mpic_get_one_irq(mpic);
472
473 if (cascade_irq != NO_IRQ)
474 generic_handle_irq(cascade_irq);
475
476 chip->irq_eoi(&desc->irq_data);
477}
478
479static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) 445static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
480{ 446{
481#if defined(CONFIG_XMON) && defined(CONFIG_PPC32) 447#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
@@ -498,14 +464,8 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
498 int master) 464 int master)
499{ 465{
500 const char *name = master ? " MPIC 1 " : " MPIC 2 "; 466 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
501 struct resource r;
502 struct mpic *mpic; 467 struct mpic *mpic;
503 unsigned int flags = master ? MPIC_PRIMARY : 0; 468 unsigned int flags = master ? 0 : MPIC_SECONDARY;
504 int rc;
505
506 rc = of_address_to_resource(np, 0, &r);
507 if (rc)
508 return NULL;
509 469
510 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); 470 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
511 471
@@ -519,7 +479,7 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
519 if (master && (flags & MPIC_BIG_ENDIAN)) 479 if (master && (flags & MPIC_BIG_ENDIAN))
520 flags |= MPIC_U3_HT_IRQS; 480 flags |= MPIC_U3_HT_IRQS;
521 481
522 mpic = mpic_alloc(np, r.start, flags, 0, 0, name); 482 mpic = mpic_alloc(np, 0, flags, 0, 0, name);
523 if (mpic == NULL) 483 if (mpic == NULL)
524 return NULL; 484 return NULL;
525 485
@@ -532,7 +492,6 @@ static int __init pmac_pic_probe_mpic(void)
532{ 492{
533 struct mpic *mpic1, *mpic2; 493 struct mpic *mpic1, *mpic2;
534 struct device_node *np, *master = NULL, *slave = NULL; 494 struct device_node *np, *master = NULL, *slave = NULL;
535 unsigned int cascade;
536 495
537 /* We can have up to 2 MPICs cascaded */ 496 /* We can have up to 2 MPICs cascaded */
538 for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) 497 for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
@@ -568,27 +527,14 @@ static int __init pmac_pic_probe_mpic(void)
568 527
569 of_node_put(master); 528 of_node_put(master);
570 529
571 /* No slave, let's go out */ 530 /* Set up a cascaded controller, if present */
572 if (slave == NULL) 531 if (slave) {
573 return 0; 532 mpic2 = pmac_setup_one_mpic(slave, 0);
574 533 if (mpic2 == NULL)
575 /* Get/Map slave interrupt */ 534 printk(KERN_ERR "Failed to setup slave MPIC\n");
576 cascade = irq_of_parse_and_map(slave, 0);
577 if (cascade == NO_IRQ) {
578 printk(KERN_ERR "Failed to map cascade IRQ\n");
579 return 0;
580 }
581
582 mpic2 = pmac_setup_one_mpic(slave, 0);
583 if (mpic2 == NULL) {
584 printk(KERN_ERR "Failed to setup slave MPIC\n");
585 of_node_put(slave); 535 of_node_put(slave);
586 return 0;
587 } 536 }
588 irq_set_handler_data(cascade, mpic2);
589 irq_set_chained_handler(cascade, pmac_u3_cascade);
590 537
591 of_node_put(slave);
592 return 0; 538 return 0;
593} 539}
594 540
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 96580b189ec..970ea1de429 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -494,11 +494,15 @@ static int __init pmac_declare_of_platform_devices(void)
494 return -1; 494 return -1;
495 495
496 np = of_find_node_by_name(NULL, "valkyrie"); 496 np = of_find_node_by_name(NULL, "valkyrie");
497 if (np) 497 if (np) {
498 of_platform_device_create(np, "valkyrie", NULL); 498 of_platform_device_create(np, "valkyrie", NULL);
499 of_node_put(np);
500 }
499 np = of_find_node_by_name(NULL, "platinum"); 501 np = of_find_node_by_name(NULL, "platinum");
500 if (np) 502 if (np) {
501 of_platform_device_create(np, "platinum", NULL); 503 of_platform_device_create(np, "platinum", NULL);
504 of_node_put(np);
505 }
502 np = of_find_node_by_type(NULL, "smu"); 506 np = of_find_node_by_type(NULL, "smu");
503 if (np) { 507 if (np) {
504 of_platform_device_create(np, "smu", NULL); 508 of_platform_device_create(np, "smu", NULL);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 9b6a820bdd7..44d769258eb 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -200,7 +200,7 @@ static int psurge_secondary_ipi_init(void)
200 200
201 if (psurge_secondary_virq) 201 if (psurge_secondary_virq)
202 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 202 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
203 IRQF_PERCPU, "IPI", NULL); 203 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
204 204
205 if (rc) 205 if (rc)
206 pr_err("Failed to setup secondary cpu IPI\n"); 206 pr_err("Failed to setup secondary cpu IPI\n");
@@ -408,13 +408,13 @@ static int __init smp_psurge_kick_cpu(int nr)
408 408
409static struct irqaction psurge_irqaction = { 409static struct irqaction psurge_irqaction = {
410 .handler = psurge_ipi_intr, 410 .handler = psurge_ipi_intr,
411 .flags = IRQF_PERCPU, 411 .flags = IRQF_PERCPU | IRQF_NO_THREAD,
412 .name = "primary IPI", 412 .name = "primary IPI",
413}; 413};
414 414
415static void __init smp_psurge_setup_cpu(int cpu_nr) 415static void __init smp_psurge_setup_cpu(int cpu_nr)
416{ 416{
417 if (cpu_nr != 0) 417 if (cpu_nr != 0 || !psurge_start)
418 return; 418 return;
419 419
420 /* reset the entry point so if we get another intr we won't 420 /* reset the entry point so if we get another intr we won't
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 31853008b41..bcc3cb48a44 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -2,4 +2,4 @@ obj-y += setup.o opal-takeover.o opal-wrappers.o opal.o
2obj-y += opal-rtc.o opal-nvram.o 2obj-y += opal-rtc.o opal-nvram.o
3 3
4obj-$(CONFIG_SMP) += smp.o 4obj-$(CONFIG_SMP) += smp.o
5obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o 5obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o pci-ioda.o
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 4a3f46d8533..3bb07e5e43c 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -99,3 +99,11 @@ OPAL_CALL(opal_write_oppanel, OPAL_WRITE_OPPANEL);
99OPAL_CALL(opal_pci_map_pe_dma_window, OPAL_PCI_MAP_PE_DMA_WINDOW); 99OPAL_CALL(opal_pci_map_pe_dma_window, OPAL_PCI_MAP_PE_DMA_WINDOW);
100OPAL_CALL(opal_pci_map_pe_dma_window_real, OPAL_PCI_MAP_PE_DMA_WINDOW_REAL); 100OPAL_CALL(opal_pci_map_pe_dma_window_real, OPAL_PCI_MAP_PE_DMA_WINDOW_REAL);
101OPAL_CALL(opal_pci_reset, OPAL_PCI_RESET); 101OPAL_CALL(opal_pci_reset, OPAL_PCI_RESET);
102OPAL_CALL(opal_pci_get_hub_diag_data, OPAL_PCI_GET_HUB_DIAG_DATA);
103OPAL_CALL(opal_pci_get_phb_diag_data, OPAL_PCI_GET_PHB_DIAG_DATA);
104OPAL_CALL(opal_pci_fence_phb, OPAL_PCI_FENCE_PHB);
105OPAL_CALL(opal_pci_reinit, OPAL_PCI_REINIT);
106OPAL_CALL(opal_pci_mask_pe_error, OPAL_PCI_MASK_PE_ERROR);
107OPAL_CALL(opal_set_slot_led_status, OPAL_SET_SLOT_LED_STATUS);
108OPAL_CALL(opal_get_epow_status, OPAL_GET_EPOW_STATUS);
109OPAL_CALL(opal_set_system_attention_led, OPAL_SET_SYSTEM_ATTENTION_LED);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
new file mode 100644
index 00000000000..f31162cfdaa
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -0,0 +1,1330 @@
1/*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#undef DEBUG
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/bootmem.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/msi.h>
23
24#include <asm/sections.h>
25#include <asm/io.h>
26#include <asm/prom.h>
27#include <asm/pci-bridge.h>
28#include <asm/machdep.h>
29#include <asm/ppc-pci.h>
30#include <asm/opal.h>
31#include <asm/iommu.h>
32#include <asm/tce.h>
33#include <asm/abs_addr.h>
34
35#include "powernv.h"
36#include "pci.h"
37
38struct resource_wrap {
39 struct list_head link;
40 resource_size_t size;
41 resource_size_t align;
42 struct pci_dev *dev; /* Set if it's a device */
43 struct pci_bus *bus; /* Set if it's a bridge */
44};
45
46static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe,
47 struct va_format *vaf)
48{
49 char pfix[32];
50
51 if (pe->pdev)
52 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
53 else
54 sprintf(pfix, "%04x:%02x ",
55 pci_domain_nr(pe->pbus), pe->pbus->number);
56 return printk("pci %s%s: [PE# %.3d] %pV", level, pfix, pe->pe_number, vaf);
57}
58
59#define define_pe_printk_level(func, kern_level) \
60static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \
61{ \
62 struct va_format vaf; \
63 va_list args; \
64 int r; \
65 \
66 va_start(args, fmt); \
67 \
68 vaf.fmt = fmt; \
69 vaf.va = &args; \
70 \
71 r = __pe_printk(kern_level, pe, &vaf); \
72 va_end(args); \
73 \
74 return r; \
75} \
76
77define_pe_printk_level(pe_err, KERN_ERR);
78define_pe_printk_level(pe_warn, KERN_WARNING);
79define_pe_printk_level(pe_info, KERN_INFO);
80
81
82/* Calculate resource usage & alignment requirement of a single
83 * device. This will also assign all resources within the device
84 * for a given type starting at 0 for the biggest one and then
85 * assigning in decreasing order of size.
86 */
87static void __devinit pnv_ioda_calc_dev(struct pci_dev *dev, unsigned int flags,
88 resource_size_t *size,
89 resource_size_t *align)
90{
91 resource_size_t start;
92 struct resource *r;
93 int i;
94
95 pr_devel(" -> CDR %s\n", pci_name(dev));
96
97 *size = *align = 0;
98
99 /* Clear the resources out and mark them all unset */
100 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
101 r = &dev->resource[i];
102 if (!(r->flags & flags))
103 continue;
104 if (r->start) {
105 r->end -= r->start;
106 r->start = 0;
107 }
108 r->flags |= IORESOURCE_UNSET;
109 }
110
111 /* We currently keep all memory resources together, we
112 * will handle prefetch & 64-bit separately in the future
113 * but for now we stick everybody in M32
114 */
115 start = 0;
116 for (;;) {
117 resource_size_t max_size = 0;
118 int max_no = -1;
119
120 /* Find next biggest resource */
121 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
122 r = &dev->resource[i];
123 if (!(r->flags & IORESOURCE_UNSET) ||
124 !(r->flags & flags))
125 continue;
126 if (resource_size(r) > max_size) {
127 max_size = resource_size(r);
128 max_no = i;
129 }
130 }
131 if (max_no < 0)
132 break;
133 r = &dev->resource[max_no];
134 if (max_size > *align)
135 *align = max_size;
136 *size += max_size;
137 r->start = start;
138 start += max_size;
139 r->end = r->start + max_size - 1;
140 r->flags &= ~IORESOURCE_UNSET;
141 pr_devel(" -> R%d %016llx..%016llx\n",
142 max_no, r->start, r->end);
143 }
144 pr_devel(" <- CDR %s size=%llx align=%llx\n",
145 pci_name(dev), *size, *align);
146}
147
148/* Allocate a resource "wrap" for a given device or bridge and
149 * insert it at the right position in the sorted list
150 */
151static void __devinit pnv_ioda_add_wrap(struct list_head *list,
152 struct pci_bus *bus,
153 struct pci_dev *dev,
154 resource_size_t size,
155 resource_size_t align)
156{
157 struct resource_wrap *w1, *w = kzalloc(sizeof(*w), GFP_KERNEL);
158
159 w->size = size;
160 w->align = align;
161 w->dev = dev;
162 w->bus = bus;
163
164 list_for_each_entry(w1, list, link) {
165 if (w1->align < align) {
166 list_add_tail(&w->link, &w1->link);
167 return;
168 }
169 }
170 list_add_tail(&w->link, list);
171}
172
173/* Offset device resources of a given type */
174static void __devinit pnv_ioda_offset_dev(struct pci_dev *dev,
175 unsigned int flags,
176 resource_size_t offset)
177{
178 struct resource *r;
179 int i;
180
181 pr_devel(" -> ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
182
183 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
184 r = &dev->resource[i];
185 if (r->flags & flags) {
186 dev->resource[i].start += offset;
187 dev->resource[i].end += offset;
188 }
189 }
190
191 pr_devel(" <- ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
192}
193
194/* Offset bus resources (& all children) of a given type */
195static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
196 unsigned int flags,
197 resource_size_t offset)
198{
199 struct resource *r;
200 struct pci_dev *dev;
201 struct pci_bus *cbus;
202 int i;
203
204 pr_devel(" -> OBR %s [%x] +%016llx\n",
205 bus->self ? pci_name(bus->self) : "root", flags, offset);
206
207 for (i = 0; i < 2; i++) {
208 r = bus->resource[i];
209 if (r && (r->flags & flags)) {
210 bus->resource[i]->start += offset;
211 bus->resource[i]->end += offset;
212 }
213 }
214 list_for_each_entry(dev, &bus->devices, bus_list)
215 pnv_ioda_offset_dev(dev, flags, offset);
216 list_for_each_entry(cbus, &bus->children, node)
217 pnv_ioda_offset_bus(cbus, flags, offset);
218
219 pr_devel(" <- OBR %s [%x]\n",
220 bus->self ? pci_name(bus->self) : "root", flags);
221}
222
223/* This is the guts of our IODA resource allocation. This is called
224 * recursively for each bus in the system. It calculates all the
225 * necessary size and requirements for children and assign them
226 * resources such that:
227 *
228 * - Each function fits in it's own contiguous set of IO/M32
229 * segment
230 *
231 * - All segments behind a P2P bridge are contiguous and obey
232 * alignment constraints of those bridges
233 */
234static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
235 resource_size_t *size,
236 resource_size_t *align)
237{
238 struct pci_controller *hose = pci_bus_to_host(bus);
239 struct pnv_phb *phb = hose->private_data;
240 resource_size_t dev_size, dev_align, start;
241 resource_size_t min_align, min_balign;
242 struct pci_dev *cdev;
243 struct pci_bus *cbus;
244 struct list_head head;
245 struct resource_wrap *w;
246 unsigned int bres;
247
248 *size = *align = 0;
249
250 pr_devel("-> CBR %s [%x]\n",
251 bus->self ? pci_name(bus->self) : "root", flags);
252
253 /* Calculate alignment requirements based on the type
254 * of resource we are working on
255 */
256 if (flags & IORESOURCE_IO) {
257 bres = 0;
258 min_align = phb->ioda.io_segsize;
259 min_balign = 0x1000;
260 } else {
261 bres = 1;
262 min_align = phb->ioda.m32_segsize;
263 min_balign = 0x100000;
264 }
265
266 /* Gather all our children resources ordered by alignment */
267 INIT_LIST_HEAD(&head);
268
269 /* - Busses */
270 list_for_each_entry(cbus, &bus->children, node) {
271 pnv_ioda_calc_bus(cbus, flags, &dev_size, &dev_align);
272 pnv_ioda_add_wrap(&head, cbus, NULL, dev_size, dev_align);
273 }
274
275 /* - Devices */
276 list_for_each_entry(cdev, &bus->devices, bus_list) {
277 pnv_ioda_calc_dev(cdev, flags, &dev_size, &dev_align);
278 /* Align them to segment size */
279 if (dev_align < min_align)
280 dev_align = min_align;
281 pnv_ioda_add_wrap(&head, NULL, cdev, dev_size, dev_align);
282 }
283 if (list_empty(&head))
284 goto empty;
285
286 /* Now we can do two things: assign offsets to them within that
287 * level and get our total alignment & size requirements. The
288 * assignment algorithm is going to be uber-trivial for now, we
289 * can try to be smarter later at filling out holes.
290 */
291 start = bus->self ? 0 : bus->resource[bres]->start;
292
293 /* Don't hand out IO 0 */
294 if ((flags & IORESOURCE_IO) && !bus->self)
295 start += 0x1000;
296
297 while(!list_empty(&head)) {
298 w = list_first_entry(&head, struct resource_wrap, link);
299 list_del(&w->link);
300 if (w->size) {
301 if (start) {
302 start = ALIGN(start, w->align);
303 if (w->dev)
304 pnv_ioda_offset_dev(w->dev,flags,start);
305 else if (w->bus)
306 pnv_ioda_offset_bus(w->bus,flags,start);
307 }
308 if (w->align > *align)
309 *align = w->align;
310 }
311 start += w->size;
312 kfree(w);
313 }
314 *size = start;
315
316 /* Align and setup bridge resources */
317 *align = max_t(resource_size_t, *align,
318 max_t(resource_size_t, min_align, min_balign));
319 *size = ALIGN(*size,
320 max_t(resource_size_t, min_align, min_balign));
321 empty:
322 /* Only setup P2P's, not the PHB itself */
323 if (bus->self) {
324 WARN_ON(bus->resource[bres] == NULL);
325 bus->resource[bres]->start = 0;
326 bus->resource[bres]->flags = (*size) ? flags : 0;
327 bus->resource[bres]->end = (*size) ? (*size - 1) : 0;
328
329 /* Clear prefetch bus resources for now */
330 bus->resource[2]->flags = 0;
331 }
332
333 pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
334 bus->self ? pci_name(bus->self) : "root", flags,*size,*align);
335}
336
337static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
338{
339 struct device_node *np;
340
341 np = pci_device_to_OF_node(dev);
342 if (!np)
343 return NULL;
344 return PCI_DN(np);
345}
346
347static void __devinit pnv_ioda_setup_pe_segments(struct pci_dev *dev)
348{
349 struct pci_controller *hose = pci_bus_to_host(dev->bus);
350 struct pnv_phb *phb = hose->private_data;
351 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
352 unsigned int pe, i;
353 resource_size_t pos;
354 struct resource io_res;
355 struct resource m32_res;
356 struct pci_bus_region region;
357 int rc;
358
359 /* Anything not referenced in the device-tree gets PE#0 */
360 pe = pdn ? pdn->pe_number : 0;
361
362 /* Calculate the device min/max */
363 io_res.start = m32_res.start = (resource_size_t)-1;
364 io_res.end = m32_res.end = 0;
365 io_res.flags = IORESOURCE_IO;
366 m32_res.flags = IORESOURCE_MEM;
367
368 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
369 struct resource *r = NULL;
370 if (dev->resource[i].flags & IORESOURCE_IO)
371 r = &io_res;
372 if (dev->resource[i].flags & IORESOURCE_MEM)
373 r = &m32_res;
374 if (!r)
375 continue;
376 if (dev->resource[i].start < r->start)
377 r->start = dev->resource[i].start;
378 if (dev->resource[i].end > r->end)
379 r->end = dev->resource[i].end;
380 }
381
382 /* Setup IO segments */
383 if (io_res.start < io_res.end) {
384 pcibios_resource_to_bus(dev, &region, &io_res);
385 pos = region.start;
386 i = pos / phb->ioda.io_segsize;
387 while(i < phb->ioda.total_pe && pos <= region.end) {
388 if (phb->ioda.io_segmap[i]) {
389 pr_err("%s: Trying to use IO seg #%d which is"
390 " already used by PE# %d\n",
391 pci_name(dev), i,
392 phb->ioda.io_segmap[i]);
393 /* XXX DO SOMETHING TO DISABLE DEVICE ? */
394 break;
395 }
396 phb->ioda.io_segmap[i] = pe;
397 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
398 OPAL_IO_WINDOW_TYPE,
399 0, i);
400 if (rc != OPAL_SUCCESS) {
401 pr_err("%s: OPAL error %d setting up mapping"
402 " for IO seg# %d\n",
403 pci_name(dev), rc, i);
404 /* XXX DO SOMETHING TO DISABLE DEVICE ? */
405 break;
406 }
407 pos += phb->ioda.io_segsize;
408 i++;
409 };
410 }
411
412 /* Setup M32 segments */
413 if (m32_res.start < m32_res.end) {
414 pcibios_resource_to_bus(dev, &region, &m32_res);
415 pos = region.start;
416 i = pos / phb->ioda.m32_segsize;
417 while(i < phb->ioda.total_pe && pos <= region.end) {
418 if (phb->ioda.m32_segmap[i]) {
419 pr_err("%s: Trying to use M32 seg #%d which is"
420 " already used by PE# %d\n",
421 pci_name(dev), i,
422 phb->ioda.m32_segmap[i]);
423 /* XXX DO SOMETHING TO DISABLE DEVICE ? */
424 break;
425 }
426 phb->ioda.m32_segmap[i] = pe;
427 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
428 OPAL_M32_WINDOW_TYPE,
429 0, i);
430 if (rc != OPAL_SUCCESS) {
431 pr_err("%s: OPAL error %d setting up mapping"
432 " for M32 seg# %d\n",
433 pci_name(dev), rc, i);
434 /* XXX DO SOMETHING TO DISABLE DEVICE ? */
435 break;
436 }
437 pos += phb->ioda.m32_segsize;
438 i++;
439 }
440 }
441}
442
443/* Check if a resource still fits in the total IO or M32 range
444 * for a given PHB
445 */
446static int __devinit pnv_ioda_resource_fit(struct pci_controller *hose,
447 struct resource *r)
448{
449 struct resource *bounds;
450
451 if (r->flags & IORESOURCE_IO)
452 bounds = &hose->io_resource;
453 else if (r->flags & IORESOURCE_MEM)
454 bounds = &hose->mem_resources[0];
455 else
456 return 1;
457
458 if (r->start >= bounds->start && r->end <= bounds->end)
459 return 1;
460 r->flags = 0;
461 return 0;
462}
463
464static void __devinit pnv_ioda_update_resources(struct pci_bus *bus)
465{
466 struct pci_controller *hose = pci_bus_to_host(bus);
467 struct pci_bus *cbus;
468 struct pci_dev *cdev;
469 unsigned int i;
470
471 /* We used to clear all device enables here. However it looks like
472 * clearing MEM enable causes Obsidian (IPR SCS) to go bonkers,
473 * and shoot fatal errors to the PHB which in turns fences itself
474 * and we can't recover from that ... yet. So for now, let's leave
475 * the enables as-is and hope for the best.
476 */
477
478 /* Check if bus resources fit in our IO or M32 range */
479 for (i = 0; bus->self && (i < 2); i++) {
480 struct resource *r = bus->resource[i];
481 if (r && !pnv_ioda_resource_fit(hose, r))
482 pr_err("%s: Bus %d resource %d disabled, no room\n",
483 pci_name(bus->self), bus->number, i);
484 }
485
486 /* Update self if it's not a PHB */
487 if (bus->self)
488 pci_setup_bridge(bus);
489
490 /* Update child devices */
491 list_for_each_entry(cdev, &bus->devices, bus_list) {
492 /* Check if resource fits, if not, disabled it */
493 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
494 struct resource *r = &cdev->resource[i];
495 if (!pnv_ioda_resource_fit(hose, r))
496 pr_err("%s: Resource %d disabled, no room\n",
497 pci_name(cdev), i);
498 }
499
500 /* Assign segments */
501 pnv_ioda_setup_pe_segments(cdev);
502
503 /* Update HW BARs */
504 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
505 pci_update_resource(cdev, i);
506 }
507
508 /* Update child busses */
509 list_for_each_entry(cbus, &bus->children, node)
510 pnv_ioda_update_resources(cbus);
511}
512
513static int __devinit pnv_ioda_alloc_pe(struct pnv_phb *phb)
514{
515 unsigned long pe;
516
517 do {
518 pe = find_next_zero_bit(phb->ioda.pe_alloc,
519 phb->ioda.total_pe, 0);
520 if (pe >= phb->ioda.total_pe)
521 return IODA_INVALID_PE;
522 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
523
524 phb->ioda.pe_array[pe].pe_number = pe;
525 return pe;
526}
527
528static void __devinit pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
529{
530 WARN_ON(phb->ioda.pe_array[pe].pdev);
531
532 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
533 clear_bit(pe, phb->ioda.pe_alloc);
534}
535
536/* Currently those 2 are only used when MSIs are enabled, this will change
537 * but in the meantime, we need to protect them to avoid warnings
538 */
539#ifdef CONFIG_PCI_MSI
540static struct pnv_ioda_pe * __devinit __pnv_ioda_get_one_pe(struct pci_dev *dev)
541{
542 struct pci_controller *hose = pci_bus_to_host(dev->bus);
543 struct pnv_phb *phb = hose->private_data;
544 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
545
546 if (!pdn)
547 return NULL;
548 if (pdn->pe_number == IODA_INVALID_PE)
549 return NULL;
550 return &phb->ioda.pe_array[pdn->pe_number];
551}
552
553static struct pnv_ioda_pe * __devinit pnv_ioda_get_pe(struct pci_dev *dev)
554{
555 struct pnv_ioda_pe *pe = __pnv_ioda_get_one_pe(dev);
556
557 while (!pe && dev->bus->self) {
558 dev = dev->bus->self;
559 pe = __pnv_ioda_get_one_pe(dev);
560 if (pe)
561 pe = pe->bus_pe;
562 }
563 return pe;
564}
565#endif /* CONFIG_PCI_MSI */
566
567static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
568 struct pnv_ioda_pe *pe)
569{
570 struct pci_dev *parent;
571 uint8_t bcomp, dcomp, fcomp;
572 long rc, rid_end, rid;
573
574 /* Bus validation ? */
575 if (pe->pbus) {
576 int count;
577
578 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
579 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
580 parent = pe->pbus->self;
581 count = pe->pbus->subordinate - pe->pbus->secondary + 1;
582 switch(count) {
583 case 1: bcomp = OpalPciBusAll; break;
584 case 2: bcomp = OpalPciBus7Bits; break;
585 case 4: bcomp = OpalPciBus6Bits; break;
586 case 8: bcomp = OpalPciBus5Bits; break;
587 case 16: bcomp = OpalPciBus4Bits; break;
588 case 32: bcomp = OpalPciBus3Bits; break;
589 default:
590 pr_err("%s: Number of subordinate busses %d"
591 " unsupported\n",
592 pci_name(pe->pbus->self), count);
593 /* Do an exact match only */
594 bcomp = OpalPciBusAll;
595 }
596 rid_end = pe->rid + (count << 8);
597 } else {
598 parent = pe->pdev->bus->self;
599 bcomp = OpalPciBusAll;
600 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
601 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
602 rid_end = pe->rid + 1;
603 }
604
605 /* Associate PE in PELT */
606 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
607 bcomp, dcomp, fcomp, OPAL_MAP_PE);
608 if (rc) {
609 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
610 return -ENXIO;
611 }
612 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
613 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
614
615 /* Add to all parents PELT-V */
616 while (parent) {
617 struct pci_dn *pdn = pnv_ioda_get_pdn(parent);
618 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
619 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
620 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
621 /* XXX What to do in case of error ? */
622 }
623 parent = parent->bus->self;
624 }
625 /* Setup reverse map */
626 for (rid = pe->rid; rid < rid_end; rid++)
627 phb->ioda.pe_rmap[rid] = pe->pe_number;
628
629 /* Setup one MVTs on IODA1 */
630 if (phb->type == PNV_PHB_IODA1) {
631 pe->mve_number = pe->pe_number;
632 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
633 pe->pe_number);
634 if (rc) {
635 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
636 rc, pe->mve_number);
637 pe->mve_number = -1;
638 } else {
639 rc = opal_pci_set_mve_enable(phb->opal_id,
640 pe->mve_number, OPAL_ENABLE_MVE);
641 if (rc) {
642 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
643 rc, pe->mve_number);
644 pe->mve_number = -1;
645 }
646 }
647 } else if (phb->type == PNV_PHB_IODA2)
648 pe->mve_number = 0;
649
650 return 0;
651}
652
653static void __devinit pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
654 struct pnv_ioda_pe *pe)
655{
656 struct pnv_ioda_pe *lpe;
657
658 list_for_each_entry(lpe, &phb->ioda.pe_list, link) {
659 if (lpe->dma_weight < pe->dma_weight) {
660 list_add_tail(&pe->link, &lpe->link);
661 return;
662 }
663 }
664 list_add_tail(&pe->link, &phb->ioda.pe_list);
665}
666
667static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
668{
669 /* This is quite simplistic. The "base" weight of a device
670 * is 10. 0 means no DMA is to be accounted for it.
671 */
672
673 /* If it's a bridge, no DMA */
674 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
675 return 0;
676
677 /* Reduce the weight of slow USB controllers */
678 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
679 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
680 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
681 return 3;
682
683 /* Increase the weight of RAID (includes Obsidian) */
684 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
685 return 15;
686
687 /* Default */
688 return 10;
689}
690
691static struct pnv_ioda_pe * __devinit pnv_ioda_setup_dev_PE(struct pci_dev *dev)
692{
693 struct pci_controller *hose = pci_bus_to_host(dev->bus);
694 struct pnv_phb *phb = hose->private_data;
695 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
696 struct pnv_ioda_pe *pe;
697 int pe_num;
698
699 if (!pdn) {
700 pr_err("%s: Device tree node not associated properly\n",
701 pci_name(dev));
702 return NULL;
703 }
704 if (pdn->pe_number != IODA_INVALID_PE)
705 return NULL;
706
707 /* PE#0 has been pre-set */
708 if (dev->bus->number == 0)
709 pe_num = 0;
710 else
711 pe_num = pnv_ioda_alloc_pe(phb);
712 if (pe_num == IODA_INVALID_PE) {
713 pr_warning("%s: Not enough PE# available, disabling device\n",
714 pci_name(dev));
715 return NULL;
716 }
717
718 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
719 * pointer in the PE data structure, both should be destroyed at the
720 * same time. However, this needs to be looked at more closely again
721 * once we actually start removing things (Hotplug, SR-IOV, ...)
722 *
723 * At some point we want to remove the PDN completely anyways
724 */
725 pe = &phb->ioda.pe_array[pe_num];
726 pci_dev_get(dev);
727 pdn->pcidev = dev;
728 pdn->pe_number = pe_num;
729 pe->pdev = dev;
730 pe->pbus = NULL;
731 pe->tce32_seg = -1;
732 pe->mve_number = -1;
733 pe->rid = dev->bus->number << 8 | pdn->devfn;
734
735 pe_info(pe, "Associated device to PE\n");
736
737 if (pnv_ioda_configure_pe(phb, pe)) {
738 /* XXX What do we do here ? */
739 if (pe_num)
740 pnv_ioda_free_pe(phb, pe_num);
741 pdn->pe_number = IODA_INVALID_PE;
742 pe->pdev = NULL;
743 pci_dev_put(dev);
744 return NULL;
745 }
746
747 /* Assign a DMA weight to the device */
748 pe->dma_weight = pnv_ioda_dma_weight(dev);
749 if (pe->dma_weight != 0) {
750 phb->ioda.dma_weight += pe->dma_weight;
751 phb->ioda.dma_pe_count++;
752 }
753
754 /* Link the PE */
755 pnv_ioda_link_pe_by_weight(phb, pe);
756
757 return pe;
758}
759
760static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
761{
762 struct pci_dev *dev;
763
764 list_for_each_entry(dev, &bus->devices, bus_list) {
765 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
766
767 if (pdn == NULL) {
768 pr_warn("%s: No device node associated with device !\n",
769 pci_name(dev));
770 continue;
771 }
772 pci_dev_get(dev);
773 pdn->pcidev = dev;
774 pdn->pe_number = pe->pe_number;
775 pe->dma_weight += pnv_ioda_dma_weight(dev);
776 if (dev->subordinate)
777 pnv_ioda_setup_same_PE(dev->subordinate, pe);
778 }
779}
780
781static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
782 struct pnv_ioda_pe *ppe)
783{
784 struct pci_controller *hose = pci_bus_to_host(dev->bus);
785 struct pnv_phb *phb = hose->private_data;
786 struct pci_bus *bus = dev->subordinate;
787 struct pnv_ioda_pe *pe;
788 int pe_num;
789
790 if (!bus) {
791 pr_warning("%s: Bridge without a subordinate bus !\n",
792 pci_name(dev));
793 return;
794 }
795 pe_num = pnv_ioda_alloc_pe(phb);
796 if (pe_num == IODA_INVALID_PE) {
797 pr_warning("%s: Not enough PE# available, disabling bus\n",
798 pci_name(dev));
799 return;
800 }
801
802 pe = &phb->ioda.pe_array[pe_num];
803 ppe->bus_pe = pe;
804 pe->pbus = bus;
805 pe->pdev = NULL;
806 pe->tce32_seg = -1;
807 pe->mve_number = -1;
808 pe->rid = bus->secondary << 8;
809 pe->dma_weight = 0;
810
811 pe_info(pe, "Secondary busses %d..%d associated with PE\n",
812 bus->secondary, bus->subordinate);
813
814 if (pnv_ioda_configure_pe(phb, pe)) {
815 /* XXX What do we do here ? */
816 if (pe_num)
817 pnv_ioda_free_pe(phb, pe_num);
818 pe->pbus = NULL;
819 return;
820 }
821
822 /* Associate it with all child devices */
823 pnv_ioda_setup_same_PE(bus, pe);
824
825 /* Account for one DMA PE if at least one DMA capable device exist
826 * below the bridge
827 */
828 if (pe->dma_weight != 0) {
829 phb->ioda.dma_weight += pe->dma_weight;
830 phb->ioda.dma_pe_count++;
831 }
832
833 /* Link the PE */
834 pnv_ioda_link_pe_by_weight(phb, pe);
835}
836
837static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
838{
839 struct pci_dev *dev;
840 struct pnv_ioda_pe *pe;
841
842 list_for_each_entry(dev, &bus->devices, bus_list) {
843 pe = pnv_ioda_setup_dev_PE(dev);
844 if (pe == NULL)
845 continue;
846 /* Leaving the PCIe domain ... single PE# */
847 if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
848 pnv_ioda_setup_bus_PE(dev, pe);
849 else if (dev->subordinate)
850 pnv_ioda_setup_PEs(dev->subordinate);
851 }
852}
853
854static void __devinit pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb,
855 struct pci_dev *dev)
856{
857 /* We delay DMA setup after we have assigned all PE# */
858}
859
860static void __devinit pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
861 struct pci_bus *bus)
862{
863 struct pci_dev *dev;
864
865 list_for_each_entry(dev, &bus->devices, bus_list) {
866 set_iommu_table_base(&dev->dev, &pe->tce32_table);
867 if (dev->subordinate)
868 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
869 }
870}
871
872static void __devinit pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
873 struct pnv_ioda_pe *pe,
874 unsigned int base,
875 unsigned int segs)
876{
877
878 struct page *tce_mem = NULL;
879 const __be64 *swinvp;
880 struct iommu_table *tbl;
881 unsigned int i;
882 int64_t rc;
883 void *addr;
884
885 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
886#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
887
888 /* XXX FIXME: Handle 64-bit only DMA devices */
889 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
890 /* XXX FIXME: Allocate multi-level tables on PHB3 */
891
892 /* We shouldn't already have a 32-bit DMA associated */
893 if (WARN_ON(pe->tce32_seg >= 0))
894 return;
895
896 /* Grab a 32-bit TCE table */
897 pe->tce32_seg = base;
898 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
899 (base << 28), ((base + segs) << 28) - 1);
900
901 /* XXX Currently, we allocate one big contiguous table for the
902 * TCEs. We only really need one chunk per 256M of TCE space
903 * (ie per segment) but that's an optimization for later, it
904 * requires some added smarts with our get/put_tce implementation
905 */
906 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
907 get_order(TCE32_TABLE_SIZE * segs));
908 if (!tce_mem) {
909 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
910 goto fail;
911 }
912 addr = page_address(tce_mem);
913 memset(addr, 0, TCE32_TABLE_SIZE * segs);
914
915 /* Configure HW */
916 for (i = 0; i < segs; i++) {
917 rc = opal_pci_map_pe_dma_window(phb->opal_id,
918 pe->pe_number,
919 base + i, 1,
920 __pa(addr) + TCE32_TABLE_SIZE * i,
921 TCE32_TABLE_SIZE, 0x1000);
922 if (rc) {
923 pe_err(pe, " Failed to configure 32-bit TCE table,"
924 " err %ld\n", rc);
925 goto fail;
926 }
927 }
928
929 /* Setup linux iommu table */
930 tbl = &pe->tce32_table;
931 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
932 base << 28);
933
934 /* OPAL variant of P7IOC SW invalidated TCEs */
935 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
936 if (swinvp) {
937 /* We need a couple more fields -- an address and a data
938 * to or. Since the bus is only printed out on table free
939 * errors, and on the first pass the data will be a relative
940 * bus number, print that out instead.
941 */
942 tbl->it_busno = 0;
943 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
944 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE
945 | TCE_PCI_SWINV_PAIR;
946 }
947 iommu_init_table(tbl, phb->hose->node);
948
949 if (pe->pdev)
950 set_iommu_table_base(&pe->pdev->dev, tbl);
951 else
952 pnv_ioda_setup_bus_dma(pe, pe->pbus);
953
954 return;
955 fail:
956 /* XXX Failure: Try to fallback to 64-bit only ? */
957 if (pe->tce32_seg >= 0)
958 pe->tce32_seg = -1;
959 if (tce_mem)
960 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
961}
962
963static void __devinit pnv_ioda_setup_dma(struct pnv_phb *phb)
964{
965 struct pci_controller *hose = phb->hose;
966 unsigned int residual, remaining, segs, tw, base;
967 struct pnv_ioda_pe *pe;
968
969 /* If we have more PE# than segments available, hand out one
970 * per PE until we run out and let the rest fail. If not,
971 * then we assign at least one segment per PE, plus more based
972 * on the amount of devices under that PE
973 */
974 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
975 residual = 0;
976 else
977 residual = phb->ioda.tce32_count -
978 phb->ioda.dma_pe_count;
979
980 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
981 hose->global_number, phb->ioda.tce32_count);
982 pr_info("PCI: %d PE# for a total weight of %d\n",
983 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
984
985 /* Walk our PE list and configure their DMA segments, hand them
986 * out one base segment plus any residual segments based on
987 * weight
988 */
989 remaining = phb->ioda.tce32_count;
990 tw = phb->ioda.dma_weight;
991 base = 0;
992 list_for_each_entry(pe, &phb->ioda.pe_list, link) {
993 if (!pe->dma_weight)
994 continue;
995 if (!remaining) {
996 pe_warn(pe, "No DMA32 resources available\n");
997 continue;
998 }
999 segs = 1;
1000 if (residual) {
1001 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
1002 if (segs > remaining)
1003 segs = remaining;
1004 }
1005 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
1006 pe->dma_weight, segs);
1007 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
1008 remaining -= segs;
1009 base += segs;
1010 }
1011}
1012
1013#ifdef CONFIG_PCI_MSI
1014static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
1015 unsigned int hwirq, unsigned int is_64,
1016 struct msi_msg *msg)
1017{
1018 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
1019 unsigned int xive_num = hwirq - phb->msi_base;
1020 uint64_t addr64;
1021 uint32_t addr32, data;
1022 int rc;
1023
1024 /* No PE assigned ? bail out ... no MSI for you ! */
1025 if (pe == NULL)
1026 return -ENXIO;
1027
1028 /* Check if we have an MVE */
1029 if (pe->mve_number < 0)
1030 return -ENXIO;
1031
1032 /* Assign XIVE to PE */
1033 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
1034 if (rc) {
1035 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
1036 pci_name(dev), rc, xive_num);
1037 return -EIO;
1038 }
1039
1040 if (is_64) {
1041 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
1042 &addr64, &data);
1043 if (rc) {
1044 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
1045 pci_name(dev), rc);
1046 return -EIO;
1047 }
1048 msg->address_hi = addr64 >> 32;
1049 msg->address_lo = addr64 & 0xfffffffful;
1050 } else {
1051 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
1052 &addr32, &data);
1053 if (rc) {
1054 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
1055 pci_name(dev), rc);
1056 return -EIO;
1057 }
1058 msg->address_hi = 0;
1059 msg->address_lo = addr32;
1060 }
1061 msg->data = data;
1062
1063 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
1064 " address=%x_%08x data=%x PE# %d\n",
1065 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
1066 msg->address_hi, msg->address_lo, data, pe->pe_number);
1067
1068 return 0;
1069}
1070
1071static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
1072{
1073 unsigned int bmap_size;
1074 const __be32 *prop = of_get_property(phb->hose->dn,
1075 "ibm,opal-msi-ranges", NULL);
1076 if (!prop) {
1077 /* BML Fallback */
1078 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
1079 }
1080 if (!prop)
1081 return;
1082
1083 phb->msi_base = be32_to_cpup(prop);
1084 phb->msi_count = be32_to_cpup(prop + 1);
1085 bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
1086 phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
1087 if (!phb->msi_map) {
1088 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
1089 phb->hose->global_number);
1090 return;
1091 }
1092 phb->msi_setup = pnv_pci_ioda_msi_setup;
1093 phb->msi32_support = 1;
1094 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
1095 phb->msi_count, phb->msi_base);
1096}
1097#else
1098static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
1099#endif /* CONFIG_PCI_MSI */
1100
1101/* This is the starting point of our IODA specific resource
1102 * allocation process
1103 */
1104static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
1105{
1106 resource_size_t size, align;
1107 struct pci_bus *child;
1108
1109 /* Associate PEs per functions */
1110 pnv_ioda_setup_PEs(hose->bus);
1111
1112 /* Calculate all resources */
1113 pnv_ioda_calc_bus(hose->bus, IORESOURCE_IO, &size, &align);
1114 pnv_ioda_calc_bus(hose->bus, IORESOURCE_MEM, &size, &align);
1115
1116 /* Apply then to HW */
1117 pnv_ioda_update_resources(hose->bus);
1118
1119 /* Setup DMA */
1120 pnv_ioda_setup_dma(hose->private_data);
1121
1122 /* Configure PCI Express settings */
1123 list_for_each_entry(child, &hose->bus->children, node) {
1124 struct pci_dev *self = child->self;
1125 if (!self)
1126 continue;
1127 pcie_bus_configure_settings(child, self->pcie_mpss);
1128 }
1129}
1130
1131/* Prevent enabling devices for which we couldn't properly
1132 * assign a PE
1133 */
1134static int __devinit pnv_pci_enable_device_hook(struct pci_dev *dev)
1135{
1136 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
1137
1138 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1139 return -EINVAL;
1140 return 0;
1141}
1142
1143static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1144 u32 devfn)
1145{
1146 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1147}
1148
1149void __init pnv_pci_init_ioda1_phb(struct device_node *np)
1150{
1151 struct pci_controller *hose;
1152 static int primary = 1;
1153 struct pnv_phb *phb;
1154 unsigned long size, m32map_off, iomap_off, pemap_off;
1155 const u64 *prop64;
1156 u64 phb_id;
1157 void *aux;
1158 long rc;
1159
1160 pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name);
1161
1162 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1163 if (!prop64) {
1164 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
1165 return;
1166 }
1167 phb_id = be64_to_cpup(prop64);
1168 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
1169
1170 phb = alloc_bootmem(sizeof(struct pnv_phb));
1171 if (phb) {
1172 memset(phb, 0, sizeof(struct pnv_phb));
1173 phb->hose = hose = pcibios_alloc_controller(np);
1174 }
1175 if (!phb || !phb->hose) {
1176 pr_err("PCI: Failed to allocate PCI controller for %s\n",
1177 np->full_name);
1178 return;
1179 }
1180
1181 spin_lock_init(&phb->lock);
1182 /* XXX Use device-tree */
1183 hose->first_busno = 0;
1184 hose->last_busno = 0xff;
1185 hose->private_data = phb;
1186 phb->opal_id = phb_id;
1187 phb->type = PNV_PHB_IODA1;
1188
1189 /* Detect specific models for error handling */
1190 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1191 phb->model = PNV_PHB_MODEL_P7IOC;
1192 else
1193 phb->model = PNV_PHB_MODEL_UNKNOWN;
1194
1195 /* We parse "ranges" now since we need to deduce the register base
1196 * from the IO base
1197 */
1198 pci_process_bridge_OF_ranges(phb->hose, np, primary);
1199 primary = 0;
1200
1201 /* Magic formula from Milton */
1202 phb->regs = of_iomap(np, 0);
1203 if (phb->regs == NULL)
1204 pr_err(" Failed to map registers !\n");
1205
1206
1207 /* XXX This is hack-a-thon. This needs to be changed so that:
1208 * - we obtain stuff like PE# etc... from device-tree
1209 * - we properly re-allocate M32 ourselves
1210 * (the OFW one isn't very good)
1211 */
1212
1213 /* Initialize more IODA stuff */
1214 phb->ioda.total_pe = 128;
1215
1216 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1217 /* OFW Has already off top 64k of M32 space (MSI space) */
1218 phb->ioda.m32_size += 0x10000;
1219
1220 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1221 phb->ioda.m32_pci_base = hose->mem_resources[0].start -
1222 hose->pci_mem_offset;
1223 phb->ioda.io_size = hose->pci_io_size;
1224 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1225 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1226
1227 /* Allocate aux data & arrays */
1228 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1229 m32map_off = size;
1230 size += phb->ioda.total_pe;
1231 iomap_off = size;
1232 size += phb->ioda.total_pe;
1233 pemap_off = size;
1234 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1235 aux = alloc_bootmem(size);
1236 memset(aux, 0, size);
1237 phb->ioda.pe_alloc = aux;
1238 phb->ioda.m32_segmap = aux + m32map_off;
1239 phb->ioda.io_segmap = aux + iomap_off;
1240 phb->ioda.pe_array = aux + pemap_off;
1241 set_bit(0, phb->ioda.pe_alloc);
1242
1243 INIT_LIST_HEAD(&phb->ioda.pe_list);
1244
1245 /* Calculate how many 32-bit TCE segments we have */
1246 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1247
1248 /* Clear unusable m64 */
1249 hose->mem_resources[1].flags = 0;
1250 hose->mem_resources[1].start = 0;
1251 hose->mem_resources[1].end = 0;
1252 hose->mem_resources[2].flags = 0;
1253 hose->mem_resources[2].start = 0;
1254 hose->mem_resources[2].end = 0;
1255
1256#if 0
1257 rc = opal_pci_set_phb_mem_window(opal->phb_id,
1258 window_type,
1259 window_num,
1260 starting_real_address,
1261 starting_pci_address,
1262 segment_size);
1263#endif
1264
1265 pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
1266 phb->ioda.total_pe,
1267 phb->ioda.m32_size, phb->ioda.m32_segsize,
1268 phb->ioda.io_size, phb->ioda.io_segsize);
1269
1270 if (phb->regs) {
1271 pr_devel(" BUID = 0x%016llx\n", in_be64(phb->regs + 0x100));
1272 pr_devel(" PHB2_CR = 0x%016llx\n", in_be64(phb->regs + 0x160));
1273 pr_devel(" IO_BAR = 0x%016llx\n", in_be64(phb->regs + 0x170));
1274 pr_devel(" IO_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x178));
1275 pr_devel(" IO_SAR = 0x%016llx\n", in_be64(phb->regs + 0x180));
1276 pr_devel(" M32_BAR = 0x%016llx\n", in_be64(phb->regs + 0x190));
1277 pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198));
1278 pr_devel(" M32_SAR = 0x%016llx\n", in_be64(phb->regs + 0x1a0));
1279 }
1280 phb->hose->ops = &pnv_pci_ops;
1281
1282 /* Setup RID -> PE mapping function */
1283 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1284
1285 /* Setup TCEs */
1286 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1287
1288 /* Setup MSI support */
1289 pnv_pci_init_ioda_msis(phb);
1290
1291 /* We set both probe_only and PCI_REASSIGN_ALL_RSRC. This is an
1292 * odd combination which essentially means that we skip all resource
1293 * fixups and assignments in the generic code, and do it all
1294 * ourselves here
1295 */
1296 pci_probe_only = 1;
1297 ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
1298 ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1299 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1300
1301 /* Reset IODA tables to a clean state */
1302 rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1303 if (rc)
1304 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
1305 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1306}
1307
1308void __init pnv_pci_init_ioda_hub(struct device_node *np)
1309{
1310 struct device_node *phbn;
1311 const u64 *prop64;
1312 u64 hub_id;
1313
1314 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1315
1316 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1317 if (!prop64) {
1318 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1319 return;
1320 }
1321 hub_id = be64_to_cpup(prop64);
1322 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1323
1324 /* Count child PHBs */
1325 for_each_child_of_node(np, phbn) {
1326 /* Look for IODA1 PHBs */
1327 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1328 pnv_pci_init_ioda1_phb(phbn);
1329 }
1330}
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 4c80f7c77d5..264967770c3 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -137,6 +137,7 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
137 phb->hose->private_data = phb; 137 phb->hose->private_data = phb;
138 phb->opal_id = phb_id; 138 phb->opal_id = phb_id;
139 phb->type = PNV_PHB_P5IOC2; 139 phb->type = PNV_PHB_P5IOC2;
140 phb->model = PNV_PHB_MODEL_P5IOC2;
140 141
141 phb->regs = of_iomap(np, 0); 142 phb->regs = of_iomap(np, 0);
142 143
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 85bb66d7f93..a70bc1e385e 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -144,6 +144,112 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
144} 144}
145#endif /* CONFIG_PCI_MSI */ 145#endif /* CONFIG_PCI_MSI */
146 146
147static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
148{
149 struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
150 int i;
151
152 pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
153
154 pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
155
156 pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
157 pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
158 pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
159
160 pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
161 pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
162 pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
163 pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
164 pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
165
166 pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
167 pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
168 pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
169 pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
170 pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
171 pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
172 pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
173 pr_info(" sourceId = 0x%08x\n", data->sourceId);
174
175 pr_info(" errorClass = 0x%016llx\n", data->errorClass);
176 pr_info(" correlator = 0x%016llx\n", data->correlator);
177
178 pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
179 pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
180 pr_info(" lemFir = 0x%016llx\n", data->lemFir);
181 pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
182 pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
183 pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
184 pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
185 pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
186 pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
187 pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
188 pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
189 pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
190 pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
191 pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
192 pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
193 pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
194 pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
195 pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
196 pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
197 pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
198 pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
199
200 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
201 if ((data->pestA[i] >> 63) == 0 &&
202 (data->pestB[i] >> 63) == 0)
203 continue;
204 pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
205 pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
206 }
207}
208
209static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
210{
211 switch(phb->model) {
212 case PNV_PHB_MODEL_P7IOC:
213 pnv_pci_dump_p7ioc_diag_data(phb);
214 break;
215 default:
216 pr_warning("PCI %d: Can't decode this PHB diag data\n",
217 phb->hose->global_number);
218 }
219}
220
221static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
222{
223 unsigned long flags, rc;
224 int has_diag;
225
226 spin_lock_irqsave(&phb->lock, flags);
227
228 rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
229 has_diag = (rc == OPAL_SUCCESS);
230
231 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
232 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
233 if (rc) {
234 pr_warning("PCI %d: Failed to clear EEH freeze state"
235 " for PE#%d, err %ld\n",
236 phb->hose->global_number, pe_no, rc);
237
238 /* For now, let's only display the diag buffer when we fail to clear
239 * the EEH status. We'll do more sensible things later when we have
240 * proper EEH support. We need to make sure we don't pollute ourselves
241 * with the normal errors generated when probing empty slots
242 */
243 if (has_diag)
244 pnv_pci_dump_phb_diag_data(phb);
245 else
246 pr_warning("PCI %d: No diag data available\n",
247 phb->hose->global_number);
248 }
249
250 spin_unlock_irqrestore(&phb->lock, flags);
251}
252
147static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus, 253static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
148 u32 bdfn) 254 u32 bdfn)
149{ 255{
@@ -165,15 +271,8 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
165 } 271 }
166 cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n", 272 cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
167 bdfn, pe_no, fstate); 273 bdfn, pe_no, fstate);
168 if (fstate != 0) { 274 if (fstate != 0)
169 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 275 pnv_pci_handle_eeh_config(phb, pe_no);
170 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
171 if (rc) {
172 pr_warning("PCI %d: Failed to clear EEH freeze state"
173 " for PE#%d, err %lld\n",
174 phb->hose->global_number, pe_no, rc);
175 }
176 }
177} 276}
178 277
179static int pnv_pci_read_config(struct pci_bus *bus, 278static int pnv_pci_read_config(struct pci_bus *bus,
@@ -257,12 +356,54 @@ struct pci_ops pnv_pci_ops = {
257 .write = pnv_pci_write_config, 356 .write = pnv_pci_write_config,
258}; 357};
259 358
359
360static void pnv_tce_invalidate(struct iommu_table *tbl,
361 u64 *startp, u64 *endp)
362{
363 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
364 unsigned long start, end, inc;
365
366 start = __pa(startp);
367 end = __pa(endp);
368
369
370 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
371 if (tbl->it_busno) {
372 start <<= 12;
373 end <<= 12;
374 inc = 128 << 12;
375 start |= tbl->it_busno;
376 end |= tbl->it_busno;
377 }
378 /* p7ioc-style invalidation, 2 TCEs per write */
379 else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
380 start |= (1ull << 63);
381 end |= (1ull << 63);
382 inc = 16;
383 }
384 /* Default (older HW) */
385 else
386 inc = 128;
387
388 end |= inc - 1; /* round up end to be different than start */
389
390 mb(); /* Ensure above stores are visible */
391 while (start <= end) {
392 __raw_writeq(start, invalidate);
393 start += inc;
394 }
395 /* The iommu layer will do another mb() for us on build() and
396 * we don't care on free()
397 */
398}
399
400
260static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 401static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
261 unsigned long uaddr, enum dma_data_direction direction, 402 unsigned long uaddr, enum dma_data_direction direction,
262 struct dma_attrs *attrs) 403 struct dma_attrs *attrs)
263{ 404{
264 u64 proto_tce; 405 u64 proto_tce;
265 u64 *tcep; 406 u64 *tcep, *tces;
266 u64 rpn; 407 u64 rpn;
267 408
268 proto_tce = TCE_PCI_READ; // Read allowed 409 proto_tce = TCE_PCI_READ; // Read allowed
@@ -270,25 +411,33 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
270 if (direction != DMA_TO_DEVICE) 411 if (direction != DMA_TO_DEVICE)
271 proto_tce |= TCE_PCI_WRITE; 412 proto_tce |= TCE_PCI_WRITE;
272 413
273 tcep = ((u64 *)tbl->it_base) + index; 414 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
415 rpn = __pa(uaddr) >> TCE_SHIFT;
274 416
275 while (npages--) { 417 while (npages--)
276 /* can't move this out since we might cross LMB boundary */ 418 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
277 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 419
278 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 420 /* Some implementations won't cache invalid TCEs and thus may not
421 * need that flush. We'll probably turn it_type into a bit mask
422 * of flags if that becomes the case
423 */
424 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
425 pnv_tce_invalidate(tbl, tces, tcep - 1);
279 426
280 uaddr += TCE_PAGE_SIZE;
281 tcep++;
282 }
283 return 0; 427 return 0;
284} 428}
285 429
286static void pnv_tce_free(struct iommu_table *tbl, long index, long npages) 430static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
287{ 431{
288 u64 *tcep = ((u64 *)tbl->it_base) + index; 432 u64 *tcep, *tces;
433
434 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
289 435
290 while (npages--) 436 while (npages--)
291 *(tcep++) = 0; 437 *(tcep++) = 0;
438
439 if (tbl->it_type & TCE_PCI_SWINV_FREE)
440 pnv_tce_invalidate(tbl, tces, tcep - 1);
292} 441}
293 442
294void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 443void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
@@ -308,13 +457,14 @@ static struct iommu_table * __devinit
308pnv_pci_setup_bml_iommu(struct pci_controller *hose) 457pnv_pci_setup_bml_iommu(struct pci_controller *hose)
309{ 458{
310 struct iommu_table *tbl; 459 struct iommu_table *tbl;
311 const __be64 *basep; 460 const __be64 *basep, *swinvp;
312 const __be32 *sizep; 461 const __be32 *sizep;
313 462
314 basep = of_get_property(hose->dn, "linux,tce-base", NULL); 463 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
315 sizep = of_get_property(hose->dn, "linux,tce-size", NULL); 464 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
316 if (basep == NULL || sizep == NULL) { 465 if (basep == NULL || sizep == NULL) {
317 pr_err("PCI: %s has missing tce entries !\n", hose->dn->full_name); 466 pr_err("PCI: %s has missing tce entries !\n",
467 hose->dn->full_name);
318 return NULL; 468 return NULL;
319 } 469 }
320 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); 470 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
@@ -323,6 +473,15 @@ pnv_pci_setup_bml_iommu(struct pci_controller *hose)
323 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), 473 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
324 be32_to_cpup(sizep), 0); 474 be32_to_cpup(sizep), 0);
325 iommu_init_table(tbl, hose->node); 475 iommu_init_table(tbl, hose->node);
476
477 /* Deal with SW invalidated TCEs when needed (BML way) */
478 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
479 NULL);
480 if (swinvp) {
481 tbl->it_busno = swinvp[1];
482 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
483 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
484 }
326 return tbl; 485 return tbl;
327} 486}
328 487
@@ -356,6 +515,13 @@ static void __devinit pnv_pci_dma_dev_setup(struct pci_dev *pdev)
356 pnv_pci_dma_fallback_setup(hose, pdev); 515 pnv_pci_dma_fallback_setup(hose, pdev);
357} 516}
358 517
518/* Fixup wrong class code in p7ioc root complex */
519static void __devinit pnv_p7ioc_rc_quirk(struct pci_dev *dev)
520{
521 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
522}
523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
524
359static int pnv_pci_probe_mode(struct pci_bus *bus) 525static int pnv_pci_probe_mode(struct pci_bus *bus)
360{ 526{
361 struct pci_controller *hose = pci_bus_to_host(bus); 527 struct pci_controller *hose = pci_bus_to_host(bus);
@@ -400,12 +566,24 @@ void __init pnv_pci_init(void)
400 init_pci_config_tokens(); 566 init_pci_config_tokens();
401 find_and_init_phbs(); 567 find_and_init_phbs();
402#endif /* CONFIG_PPC_POWERNV_RTAS */ 568#endif /* CONFIG_PPC_POWERNV_RTAS */
403 } else { 569 }
404 /* OPAL is here, do our normal stuff */ 570 /* OPAL is here, do our normal stuff */
571 else {
572 int found_ioda = 0;
573
574 /* Look for IODA IO-Hubs. We don't support mixing IODA
575 * and p5ioc2 due to the need to change some global
576 * probing flags
577 */
578 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
579 pnv_pci_init_ioda_hub(np);
580 found_ioda = 1;
581 }
405 582
406 /* Look for p5ioc2 IO-Hubs */ 583 /* Look for p5ioc2 IO-Hubs */
407 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 584 if (!found_ioda)
408 pnv_pci_init_p5ioc2_hub(np); 585 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
586 pnv_pci_init_p5ioc2_hub(np);
409 } 587 }
410 588
411 /* Setup the linkage between OF nodes and PHBs */ 589 /* Setup the linkage between OF nodes and PHBs */
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index d4dbc495093..8bc47963464 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -9,9 +9,63 @@ enum pnv_phb_type {
9 PNV_PHB_IODA2, 9 PNV_PHB_IODA2,
10}; 10};
11 11
12/* Precise PHB model for error management */
13enum pnv_phb_model {
14 PNV_PHB_MODEL_UNKNOWN,
15 PNV_PHB_MODEL_P5IOC2,
16 PNV_PHB_MODEL_P7IOC,
17};
18
19#define PNV_PCI_DIAG_BUF_SIZE 4096
20
21/* Data associated with a PE, including IOMMU tracking etc.. */
22struct pnv_ioda_pe {
23 /* A PE can be associated with a single device or an
24 * entire bus (& children). In the former case, pdev
25 * is populated, in the later case, pbus is.
26 */
27 struct pci_dev *pdev;
28 struct pci_bus *pbus;
29
30 /* Effective RID (device RID for a device PE and base bus
31 * RID with devfn 0 for a bus PE)
32 */
33 unsigned int rid;
34
35 /* PE number */
36 unsigned int pe_number;
37
38 /* "Weight" assigned to the PE for the sake of DMA resource
39 * allocations
40 */
41 unsigned int dma_weight;
42
43 /* This is a PCI-E -> PCI-X bridge, this points to the
44 * corresponding bus PE
45 */
46 struct pnv_ioda_pe *bus_pe;
47
48 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
49 int tce32_seg;
50 int tce32_segcount;
51 struct iommu_table tce32_table;
52
53 /* XXX TODO: Add support for additional 64-bit iommus */
54
55 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
56 * and -1 if not supported. (It's actually identical to the
57 * PE number)
58 */
59 int mve_number;
60
61 /* Link in list of PE#s */
62 struct list_head link;
63};
64
12struct pnv_phb { 65struct pnv_phb {
13 struct pci_controller *hose; 66 struct pci_controller *hose;
14 enum pnv_phb_type type; 67 enum pnv_phb_type type;
68 enum pnv_phb_model model;
15 u64 opal_id; 69 u64 opal_id;
16 void __iomem *regs; 70 void __iomem *regs;
17 spinlock_t lock; 71 spinlock_t lock;
@@ -34,7 +88,52 @@ struct pnv_phb {
34 struct { 88 struct {
35 struct iommu_table iommu_table; 89 struct iommu_table iommu_table;
36 } p5ioc2; 90 } p5ioc2;
91
92 struct {
93 /* Global bridge info */
94 unsigned int total_pe;
95 unsigned int m32_size;
96 unsigned int m32_segsize;
97 unsigned int m32_pci_base;
98 unsigned int io_size;
99 unsigned int io_segsize;
100 unsigned int io_pci_base;
101
102 /* PE allocation bitmap */
103 unsigned long *pe_alloc;
104
105 /* M32 & IO segment maps */
106 unsigned int *m32_segmap;
107 unsigned int *io_segmap;
108 struct pnv_ioda_pe *pe_array;
109
110 /* Reverse map of PEs, will have to extend if
111 * we are to support more than 256 PEs, indexed
112 * bus { bus, devfn }
113 */
114 unsigned char pe_rmap[0x10000];
115
116 /* 32-bit TCE tables allocation */
117 unsigned long tce32_count;
118
119 /* Total "weight" for the sake of DMA resources
120 * allocation
121 */
122 unsigned int dma_weight;
123 unsigned int dma_pe_count;
124
125 /* Sorted list of used PE's, sorted at
126 * boot for resource allocation purposes
127 */
128 struct list_head pe_list;
129 } ioda;
37 }; 130 };
131
132 /* PHB status structure */
133 union {
134 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
135 struct OpalIoP7IOCPhbErrorData p7ioc;
136 } diag;
38}; 137};
39 138
40extern struct pci_ops pnv_pci_ops; 139extern struct pci_ops pnv_pci_ops;
@@ -43,6 +142,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
43 void *tce_mem, u64 tce_size, 142 void *tce_mem, u64 tce_size,
44 u64 dma_offset); 143 u64 dma_offset);
45extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 144extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
145extern void pnv_pci_init_ioda_hub(struct device_node *np);
46 146
47 147
48#endif /* __POWERNV_PCI_H */ 148#endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index e8773668524..17210c526c5 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -75,7 +75,7 @@ int __devinit pnv_smp_kick_cpu(int nr)
75 /* On OPAL v2 the CPU are still spinning inside OPAL itself, 75 /* On OPAL v2 the CPU are still spinning inside OPAL itself,
76 * get them back now 76 * get them back now
77 */ 77 */
78 if (firmware_has_feature(FW_FEATURE_OPALv2)) { 78 if (!paca[nr].cpu_start && firmware_has_feature(FW_FEATURE_OPALv2)) {
79 pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu); 79 pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
80 rc = opal_start_cpu(pcpu, start_here); 80 rc = opal_start_cpu(pcpu, start_here);
81 if (rc != OPAL_SUCCESS) 81 if (rc != OPAL_SUCCESS)
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 1d6f4f478fe..617efa12a3a 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -31,18 +31,18 @@
31 31
32#if defined(DEBUG) 32#if defined(DEBUG)
33#define DBG udbg_printf 33#define DBG udbg_printf
34#define FAIL udbg_printf
34#else 35#else
35#define DBG pr_debug 36#define DBG pr_devel
37#define FAIL pr_debug
36#endif 38#endif
37 39
38/** 40/**
39 * struct ps3_bmp - a per cpu irq status and mask bitmap structure 41 * struct ps3_bmp - a per cpu irq status and mask bitmap structure
40 * @status: 256 bit status bitmap indexed by plug 42 * @status: 256 bit status bitmap indexed by plug
41 * @unused_1: 43 * @unused_1: Alignment
42 * @mask: 256 bit mask bitmap indexed by plug 44 * @mask: 256 bit mask bitmap indexed by plug
43 * @unused_2: 45 * @unused_2: Alignment
44 * @lock:
45 * @ipi_debug_brk_mask:
46 * 46 *
47 * The HV maintains per SMT thread mappings of HV outlet to HV plug on 47 * The HV maintains per SMT thread mappings of HV outlet to HV plug on
48 * behalf of the guest. These mappings are implemented as 256 bit guest 48 * behalf of the guest. These mappings are implemented as 256 bit guest
@@ -73,21 +73,24 @@ struct ps3_bmp {
73 unsigned long mask; 73 unsigned long mask;
74 u64 unused_2[3]; 74 u64 unused_2[3];
75 }; 75 };
76 u64 ipi_debug_brk_mask;
77 spinlock_t lock;
78}; 76};
79 77
80/** 78/**
81 * struct ps3_private - a per cpu data structure 79 * struct ps3_private - a per cpu data structure
82 * @bmp: ps3_bmp structure 80 * @bmp: ps3_bmp structure
81 * @bmp_lock: Syncronize access to bmp.
82 * @ipi_debug_brk_mask: Mask for debug break IPIs
83 * @ppe_id: HV logical_ppe_id 83 * @ppe_id: HV logical_ppe_id
84 * @thread_id: HV thread_id 84 * @thread_id: HV thread_id
85 * @ipi_mask: Mask of IPI virqs
85 */ 86 */
86 87
87struct ps3_private { 88struct ps3_private {
88 struct ps3_bmp bmp __attribute__ ((aligned (PS3_BMP_MINALIGN))); 89 struct ps3_bmp bmp __attribute__ ((aligned (PS3_BMP_MINALIGN)));
90 spinlock_t bmp_lock;
89 u64 ppe_id; 91 u64 ppe_id;
90 u64 thread_id; 92 u64 thread_id;
93 unsigned long ipi_debug_brk_mask;
91 unsigned long ipi_mask; 94 unsigned long ipi_mask;
92}; 95};
93 96
@@ -105,7 +108,7 @@ static void ps3_chip_mask(struct irq_data *d)
105 struct ps3_private *pd = irq_data_get_irq_chip_data(d); 108 struct ps3_private *pd = irq_data_get_irq_chip_data(d);
106 unsigned long flags; 109 unsigned long flags;
107 110
108 pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, 111 DBG("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
109 pd->thread_id, d->irq); 112 pd->thread_id, d->irq);
110 113
111 local_irq_save(flags); 114 local_irq_save(flags);
@@ -126,7 +129,7 @@ static void ps3_chip_unmask(struct irq_data *d)
126 struct ps3_private *pd = irq_data_get_irq_chip_data(d); 129 struct ps3_private *pd = irq_data_get_irq_chip_data(d);
127 unsigned long flags; 130 unsigned long flags;
128 131
129 pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, 132 DBG("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
130 pd->thread_id, d->irq); 133 pd->thread_id, d->irq);
131 134
132 local_irq_save(flags); 135 local_irq_save(flags);
@@ -190,19 +193,19 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
190 *virq = irq_create_mapping(NULL, outlet); 193 *virq = irq_create_mapping(NULL, outlet);
191 194
192 if (*virq == NO_IRQ) { 195 if (*virq == NO_IRQ) {
193 pr_debug("%s:%d: irq_create_mapping failed: outlet %lu\n", 196 FAIL("%s:%d: irq_create_mapping failed: outlet %lu\n",
194 __func__, __LINE__, outlet); 197 __func__, __LINE__, outlet);
195 result = -ENOMEM; 198 result = -ENOMEM;
196 goto fail_create; 199 goto fail_create;
197 } 200 }
198 201
199 pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, 202 DBG("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__,
200 outlet, cpu, *virq); 203 outlet, cpu, *virq);
201 204
202 result = irq_set_chip_data(*virq, pd); 205 result = irq_set_chip_data(*virq, pd);
203 206
204 if (result) { 207 if (result) {
205 pr_debug("%s:%d: irq_set_chip_data failed\n", 208 FAIL("%s:%d: irq_set_chip_data failed\n",
206 __func__, __LINE__); 209 __func__, __LINE__);
207 goto fail_set; 210 goto fail_set;
208 } 211 }
@@ -228,13 +231,13 @@ static int ps3_virq_destroy(unsigned int virq)
228{ 231{
229 const struct ps3_private *pd = irq_get_chip_data(virq); 232 const struct ps3_private *pd = irq_get_chip_data(virq);
230 233
231 pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, 234 DBG("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
232 __LINE__, pd->ppe_id, pd->thread_id, virq); 235 __LINE__, pd->ppe_id, pd->thread_id, virq);
233 236
234 irq_set_chip_data(virq, NULL); 237 irq_set_chip_data(virq, NULL);
235 irq_dispose_mapping(virq); 238 irq_dispose_mapping(virq);
236 239
237 pr_debug("%s:%d <-\n", __func__, __LINE__); 240 DBG("%s:%d <-\n", __func__, __LINE__);
238 return 0; 241 return 0;
239} 242}
240 243
@@ -257,7 +260,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
257 result = ps3_virq_setup(cpu, outlet, virq); 260 result = ps3_virq_setup(cpu, outlet, virq);
258 261
259 if (result) { 262 if (result) {
260 pr_debug("%s:%d: ps3_virq_setup failed\n", __func__, __LINE__); 263 FAIL("%s:%d: ps3_virq_setup failed\n", __func__, __LINE__);
261 goto fail_setup; 264 goto fail_setup;
262 } 265 }
263 266
@@ -269,7 +272,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
269 outlet, 0); 272 outlet, 0);
270 273
271 if (result) { 274 if (result) {
272 pr_info("%s:%d: lv1_connect_irq_plug_ext failed: %s\n", 275 FAIL("%s:%d: lv1_connect_irq_plug_ext failed: %s\n",
273 __func__, __LINE__, ps3_result(result)); 276 __func__, __LINE__, ps3_result(result));
274 result = -EPERM; 277 result = -EPERM;
275 goto fail_connect; 278 goto fail_connect;
@@ -298,7 +301,7 @@ int ps3_irq_plug_destroy(unsigned int virq)
298 int result; 301 int result;
299 const struct ps3_private *pd = irq_get_chip_data(virq); 302 const struct ps3_private *pd = irq_get_chip_data(virq);
300 303
301 pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, 304 DBG("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
302 __LINE__, pd->ppe_id, pd->thread_id, virq); 305 __LINE__, pd->ppe_id, pd->thread_id, virq);
303 306
304 ps3_chip_mask(irq_get_irq_data(virq)); 307 ps3_chip_mask(irq_get_irq_data(virq));
@@ -306,7 +309,7 @@ int ps3_irq_plug_destroy(unsigned int virq)
306 result = lv1_disconnect_irq_plug_ext(pd->ppe_id, pd->thread_id, virq); 309 result = lv1_disconnect_irq_plug_ext(pd->ppe_id, pd->thread_id, virq);
307 310
308 if (result) 311 if (result)
309 pr_info("%s:%d: lv1_disconnect_irq_plug_ext failed: %s\n", 312 FAIL("%s:%d: lv1_disconnect_irq_plug_ext failed: %s\n",
310 __func__, __LINE__, ps3_result(result)); 313 __func__, __LINE__, ps3_result(result));
311 314
312 ps3_virq_destroy(virq); 315 ps3_virq_destroy(virq);
@@ -334,7 +337,7 @@ int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq)
334 result = lv1_construct_event_receive_port(&outlet); 337 result = lv1_construct_event_receive_port(&outlet);
335 338
336 if (result) { 339 if (result) {
337 pr_debug("%s:%d: lv1_construct_event_receive_port failed: %s\n", 340 FAIL("%s:%d: lv1_construct_event_receive_port failed: %s\n",
338 __func__, __LINE__, ps3_result(result)); 341 __func__, __LINE__, ps3_result(result));
339 *virq = NO_IRQ; 342 *virq = NO_IRQ;
340 return result; 343 return result;
@@ -360,14 +363,14 @@ int ps3_event_receive_port_destroy(unsigned int virq)
360{ 363{
361 int result; 364 int result;
362 365
363 pr_debug(" -> %s:%d virq %u\n", __func__, __LINE__, virq); 366 DBG(" -> %s:%d virq %u\n", __func__, __LINE__, virq);
364 367
365 ps3_chip_mask(irq_get_irq_data(virq)); 368 ps3_chip_mask(irq_get_irq_data(virq));
366 369
367 result = lv1_destruct_event_receive_port(virq_to_hw(virq)); 370 result = lv1_destruct_event_receive_port(virq_to_hw(virq));
368 371
369 if (result) 372 if (result)
370 pr_debug("%s:%d: lv1_destruct_event_receive_port failed: %s\n", 373 FAIL("%s:%d: lv1_destruct_event_receive_port failed: %s\n",
371 __func__, __LINE__, ps3_result(result)); 374 __func__, __LINE__, ps3_result(result));
372 375
373 /* 376 /*
@@ -375,7 +378,7 @@ int ps3_event_receive_port_destroy(unsigned int virq)
375 * calls from interrupt context (smp_call_function) when kexecing. 378 * calls from interrupt context (smp_call_function) when kexecing.
376 */ 379 */
377 380
378 pr_debug(" <- %s:%d\n", __func__, __LINE__); 381 DBG(" <- %s:%d\n", __func__, __LINE__);
379 return result; 382 return result;
380} 383}
381 384
@@ -411,7 +414,7 @@ int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
411 dev->dev_id, virq_to_hw(*virq), dev->interrupt_id); 414 dev->dev_id, virq_to_hw(*virq), dev->interrupt_id);
412 415
413 if (result) { 416 if (result) {
414 pr_debug("%s:%d: lv1_connect_interrupt_event_receive_port" 417 FAIL("%s:%d: lv1_connect_interrupt_event_receive_port"
415 " failed: %s\n", __func__, __LINE__, 418 " failed: %s\n", __func__, __LINE__,
416 ps3_result(result)); 419 ps3_result(result));
417 ps3_event_receive_port_destroy(*virq); 420 ps3_event_receive_port_destroy(*virq);
@@ -419,7 +422,7 @@ int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
419 return result; 422 return result;
420 } 423 }
421 424
422 pr_debug("%s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__, 425 DBG("%s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
423 dev->interrupt_id, *virq); 426 dev->interrupt_id, *virq);
424 427
425 return 0; 428 return 0;
@@ -433,14 +436,14 @@ int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
433 436
434 int result; 437 int result;
435 438
436 pr_debug(" -> %s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__, 439 DBG(" -> %s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
437 dev->interrupt_id, virq); 440 dev->interrupt_id, virq);
438 441
439 result = lv1_disconnect_interrupt_event_receive_port(dev->bus_id, 442 result = lv1_disconnect_interrupt_event_receive_port(dev->bus_id,
440 dev->dev_id, virq_to_hw(virq), dev->interrupt_id); 443 dev->dev_id, virq_to_hw(virq), dev->interrupt_id);
441 444
442 if (result) 445 if (result)
443 pr_debug("%s:%d: lv1_disconnect_interrupt_event_receive_port" 446 FAIL("%s:%d: lv1_disconnect_interrupt_event_receive_port"
444 " failed: %s\n", __func__, __LINE__, 447 " failed: %s\n", __func__, __LINE__,
445 ps3_result(result)); 448 ps3_result(result));
446 449
@@ -455,7 +458,7 @@ int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
455 result = ps3_virq_destroy(virq); 458 result = ps3_virq_destroy(virq);
456 BUG_ON(result); 459 BUG_ON(result);
457 460
458 pr_debug(" <- %s:%d\n", __func__, __LINE__); 461 DBG(" <- %s:%d\n", __func__, __LINE__);
459 return result; 462 return result;
460} 463}
461EXPORT_SYMBOL(ps3_sb_event_receive_port_destroy); 464EXPORT_SYMBOL(ps3_sb_event_receive_port_destroy);
@@ -480,7 +483,7 @@ int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
480 result = lv1_construct_io_irq_outlet(interrupt_id, &outlet); 483 result = lv1_construct_io_irq_outlet(interrupt_id, &outlet);
481 484
482 if (result) { 485 if (result) {
483 pr_debug("%s:%d: lv1_construct_io_irq_outlet failed: %s\n", 486 FAIL("%s:%d: lv1_construct_io_irq_outlet failed: %s\n",
484 __func__, __LINE__, ps3_result(result)); 487 __func__, __LINE__, ps3_result(result));
485 return result; 488 return result;
486 } 489 }
@@ -510,7 +513,7 @@ int ps3_io_irq_destroy(unsigned int virq)
510 result = lv1_destruct_io_irq_outlet(outlet); 513 result = lv1_destruct_io_irq_outlet(outlet);
511 514
512 if (result) 515 if (result)
513 pr_debug("%s:%d: lv1_destruct_io_irq_outlet failed: %s\n", 516 FAIL("%s:%d: lv1_destruct_io_irq_outlet failed: %s\n",
514 __func__, __LINE__, ps3_result(result)); 517 __func__, __LINE__, ps3_result(result));
515 518
516 return result; 519 return result;
@@ -542,7 +545,7 @@ int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
542 result = lv1_configure_virtual_uart_irq(lpar_addr, &outlet); 545 result = lv1_configure_virtual_uart_irq(lpar_addr, &outlet);
543 546
544 if (result) { 547 if (result) {
545 pr_debug("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n", 548 FAIL("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
546 __func__, __LINE__, ps3_result(result)); 549 __func__, __LINE__, ps3_result(result));
547 return result; 550 return result;
548 } 551 }
@@ -562,7 +565,7 @@ int ps3_vuart_irq_destroy(unsigned int virq)
562 result = lv1_deconfigure_virtual_uart_irq(); 565 result = lv1_deconfigure_virtual_uart_irq();
563 566
564 if (result) { 567 if (result) {
565 pr_debug("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n", 568 FAIL("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
566 __func__, __LINE__, ps3_result(result)); 569 __func__, __LINE__, ps3_result(result));
567 return result; 570 return result;
568 } 571 }
@@ -595,7 +598,7 @@ int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
595 result = lv1_get_spe_irq_outlet(spe_id, class, &outlet); 598 result = lv1_get_spe_irq_outlet(spe_id, class, &outlet);
596 599
597 if (result) { 600 if (result) {
598 pr_debug("%s:%d: lv1_get_spe_irq_outlet failed: %s\n", 601 FAIL("%s:%d: lv1_get_spe_irq_outlet failed: %s\n",
599 __func__, __LINE__, ps3_result(result)); 602 __func__, __LINE__, ps3_result(result));
600 return result; 603 return result;
601 } 604 }
@@ -626,7 +629,7 @@ int ps3_spe_irq_destroy(unsigned int virq)
626static void _dump_64_bmp(const char *header, const u64 *p, unsigned cpu, 629static void _dump_64_bmp(const char *header, const u64 *p, unsigned cpu,
627 const char* func, int line) 630 const char* func, int line)
628{ 631{
629 pr_debug("%s:%d: %s %u {%04lx_%04lx_%04lx_%04lx}\n", 632 pr_debug("%s:%d: %s %u {%04llx_%04llx_%04llx_%04llx}\n",
630 func, line, header, cpu, 633 func, line, header, cpu,
631 *p >> 48, (*p >> 32) & 0xffff, (*p >> 16) & 0xffff, 634 *p >> 48, (*p >> 32) & 0xffff, (*p >> 16) & 0xffff,
632 *p & 0xffff); 635 *p & 0xffff);
@@ -635,7 +638,7 @@ static void _dump_64_bmp(const char *header, const u64 *p, unsigned cpu,
635static void __maybe_unused _dump_256_bmp(const char *header, 638static void __maybe_unused _dump_256_bmp(const char *header,
636 const u64 *p, unsigned cpu, const char* func, int line) 639 const u64 *p, unsigned cpu, const char* func, int line)
637{ 640{
638 pr_debug("%s:%d: %s %u {%016lx:%016lx:%016lx:%016lx}\n", 641 pr_debug("%s:%d: %s %u {%016llx:%016llx:%016llx:%016llx}\n",
639 func, line, header, cpu, p[0], p[1], p[2], p[3]); 642 func, line, header, cpu, p[0], p[1], p[2], p[3]);
640} 643}
641 644
@@ -644,10 +647,10 @@ static void _dump_bmp(struct ps3_private* pd, const char* func, int line)
644{ 647{
645 unsigned long flags; 648 unsigned long flags;
646 649
647 spin_lock_irqsave(&pd->bmp.lock, flags); 650 spin_lock_irqsave(&pd->bmp_lock, flags);
648 _dump_64_bmp("stat", &pd->bmp.status, pd->thread_id, func, line); 651 _dump_64_bmp("stat", &pd->bmp.status, pd->thread_id, func, line);
649 _dump_64_bmp("mask", &pd->bmp.mask, pd->thread_id, func, line); 652 _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line);
650 spin_unlock_irqrestore(&pd->bmp.lock, flags); 653 spin_unlock_irqrestore(&pd->bmp_lock, flags);
651} 654}
652 655
653#define dump_mask(_x) _dump_mask(_x, __func__, __LINE__) 656#define dump_mask(_x) _dump_mask(_x, __func__, __LINE__)
@@ -656,9 +659,9 @@ static void __maybe_unused _dump_mask(struct ps3_private *pd,
656{ 659{
657 unsigned long flags; 660 unsigned long flags;
658 661
659 spin_lock_irqsave(&pd->bmp.lock, flags); 662 spin_lock_irqsave(&pd->bmp_lock, flags);
660 _dump_64_bmp("mask", &pd->bmp.mask, pd->thread_id, func, line); 663 _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line);
661 spin_unlock_irqrestore(&pd->bmp.lock, flags); 664 spin_unlock_irqrestore(&pd->bmp_lock, flags);
662} 665}
663#else 666#else
664static void dump_bmp(struct ps3_private* pd) {}; 667static void dump_bmp(struct ps3_private* pd) {};
@@ -667,7 +670,7 @@ static void dump_bmp(struct ps3_private* pd) {};
667static int ps3_host_map(struct irq_host *h, unsigned int virq, 670static int ps3_host_map(struct irq_host *h, unsigned int virq,
668 irq_hw_number_t hwirq) 671 irq_hw_number_t hwirq)
669{ 672{
670 pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, 673 DBG("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq,
671 virq); 674 virq);
672 675
673 irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); 676 irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
@@ -690,10 +693,10 @@ void __init ps3_register_ipi_debug_brk(unsigned int cpu, unsigned int virq)
690{ 693{
691 struct ps3_private *pd = &per_cpu(ps3_private, cpu); 694 struct ps3_private *pd = &per_cpu(ps3_private, cpu);
692 695
693 pd->bmp.ipi_debug_brk_mask = 0x8000000000000000UL >> virq; 696 set_bit(63 - virq, &pd->ipi_debug_brk_mask);
694 697
695 pr_debug("%s:%d: cpu %u, virq %u, mask %llxh\n", __func__, __LINE__, 698 DBG("%s:%d: cpu %u, virq %u, mask %lxh\n", __func__, __LINE__,
696 cpu, virq, pd->bmp.ipi_debug_brk_mask); 699 cpu, virq, pd->ipi_debug_brk_mask);
697} 700}
698 701
699void __init ps3_register_ipi_irq(unsigned int cpu, unsigned int virq) 702void __init ps3_register_ipi_irq(unsigned int cpu, unsigned int virq)
@@ -714,14 +717,14 @@ static unsigned int ps3_get_irq(void)
714 717
715 /* check for ipi break first to stop this cpu ASAP */ 718 /* check for ipi break first to stop this cpu ASAP */
716 719
717 if (x & pd->bmp.ipi_debug_brk_mask) 720 if (x & pd->ipi_debug_brk_mask)
718 x &= pd->bmp.ipi_debug_brk_mask; 721 x &= pd->ipi_debug_brk_mask;
719 722
720 asm volatile("cntlzd %0,%1" : "=r" (plug) : "r" (x)); 723 asm volatile("cntlzd %0,%1" : "=r" (plug) : "r" (x));
721 plug &= 0x3f; 724 plug &= 0x3f;
722 725
723 if (unlikely(plug == NO_IRQ)) { 726 if (unlikely(plug == NO_IRQ)) {
724 pr_debug("%s:%d: no plug found: thread_id %llu\n", __func__, 727 DBG("%s:%d: no plug found: thread_id %llu\n", __func__,
725 __LINE__, pd->thread_id); 728 __LINE__, pd->thread_id);
726 dump_bmp(&per_cpu(ps3_private, 0)); 729 dump_bmp(&per_cpu(ps3_private, 0));
727 dump_bmp(&per_cpu(ps3_private, 1)); 730 dump_bmp(&per_cpu(ps3_private, 1));
@@ -760,9 +763,9 @@ void __init ps3_init_IRQ(void)
760 763
761 lv1_get_logical_ppe_id(&pd->ppe_id); 764 lv1_get_logical_ppe_id(&pd->ppe_id);
762 pd->thread_id = get_hard_smp_processor_id(cpu); 765 pd->thread_id = get_hard_smp_processor_id(cpu);
763 spin_lock_init(&pd->bmp.lock); 766 spin_lock_init(&pd->bmp_lock);
764 767
765 pr_debug("%s:%d: ppe_id %llu, thread_id %llu, bmp %lxh\n", 768 DBG("%s:%d: ppe_id %llu, thread_id %llu, bmp %lxh\n",
766 __func__, __LINE__, pd->ppe_id, pd->thread_id, 769 __func__, __LINE__, pd->ppe_id, pd->thread_id,
767 ps3_mm_phys_to_lpar(__pa(&pd->bmp))); 770 ps3_mm_phys_to_lpar(__pa(&pd->bmp)));
768 771
@@ -770,7 +773,7 @@ void __init ps3_init_IRQ(void)
770 pd->thread_id, ps3_mm_phys_to_lpar(__pa(&pd->bmp))); 773 pd->thread_id, ps3_mm_phys_to_lpar(__pa(&pd->bmp)));
771 774
772 if (result) 775 if (result)
773 pr_debug("%s:%d: lv1_configure_irq_state_bitmap failed:" 776 FAIL("%s:%d: lv1_configure_irq_state_bitmap failed:"
774 " %s\n", __func__, __LINE__, 777 " %s\n", __func__, __LINE__,
775 ps3_result(result)); 778 ps3_result(result));
776 } 779 }
diff --git a/arch/powerpc/platforms/ps3/repository.c b/arch/powerpc/platforms/ps3/repository.c
index ca40f6afd35..7bdfea336f5 100644
--- a/arch/powerpc/platforms/ps3/repository.c
+++ b/arch/powerpc/platforms/ps3/repository.c
@@ -44,7 +44,7 @@ static void _dump_field(const char *hdr, u64 n, const char *func, int line)
44 s[i] = (in[i] <= 126 && in[i] >= 32) ? in[i] : '.'; 44 s[i] = (in[i] <= 126 && in[i] >= 32) ? in[i] : '.';
45 s[i] = 0; 45 s[i] = 0;
46 46
47 pr_debug("%s:%d: %s%016llx : %s\n", func, line, hdr, n, s); 47 pr_devel("%s:%d: %s%016llx : %s\n", func, line, hdr, n, s);
48#endif 48#endif
49} 49}
50 50
@@ -53,7 +53,7 @@ static void _dump_field(const char *hdr, u64 n, const char *func, int line)
53static void _dump_node_name(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, 53static void _dump_node_name(unsigned int lpar_id, u64 n1, u64 n2, u64 n3,
54 u64 n4, const char *func, int line) 54 u64 n4, const char *func, int line)
55{ 55{
56 pr_debug("%s:%d: lpar: %u\n", func, line, lpar_id); 56 pr_devel("%s:%d: lpar: %u\n", func, line, lpar_id);
57 _dump_field("n1: ", n1, func, line); 57 _dump_field("n1: ", n1, func, line);
58 _dump_field("n2: ", n2, func, line); 58 _dump_field("n2: ", n2, func, line);
59 _dump_field("n3: ", n3, func, line); 59 _dump_field("n3: ", n3, func, line);
@@ -65,13 +65,13 @@ static void _dump_node_name(unsigned int lpar_id, u64 n1, u64 n2, u64 n3,
65static void _dump_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4, 65static void _dump_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
66 u64 v1, u64 v2, const char *func, int line) 66 u64 v1, u64 v2, const char *func, int line)
67{ 67{
68 pr_debug("%s:%d: lpar: %u\n", func, line, lpar_id); 68 pr_devel("%s:%d: lpar: %u\n", func, line, lpar_id);
69 _dump_field("n1: ", n1, func, line); 69 _dump_field("n1: ", n1, func, line);
70 _dump_field("n2: ", n2, func, line); 70 _dump_field("n2: ", n2, func, line);
71 _dump_field("n3: ", n3, func, line); 71 _dump_field("n3: ", n3, func, line);
72 _dump_field("n4: ", n4, func, line); 72 _dump_field("n4: ", n4, func, line);
73 pr_debug("%s:%d: v1: %016llx\n", func, line, v1); 73 pr_devel("%s:%d: v1: %016llx\n", func, line, v1);
74 pr_debug("%s:%d: v2: %016llx\n", func, line, v2); 74 pr_devel("%s:%d: v2: %016llx\n", func, line, v2);
75} 75}
76 76
77/** 77/**
@@ -131,11 +131,11 @@ static int read_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
131 lpar_id = id; 131 lpar_id = id;
132 } 132 }
133 133
134 result = lv1_get_repository_node_value(lpar_id, n1, n2, n3, n4, &v1, 134 result = lv1_read_repository_node(lpar_id, n1, n2, n3, n4, &v1,
135 &v2); 135 &v2);
136 136
137 if (result) { 137 if (result) {
138 pr_debug("%s:%d: lv1_get_repository_node_value failed: %s\n", 138 pr_warn("%s:%d: lv1_read_repository_node failed: %s\n",
139 __func__, __LINE__, ps3_result(result)); 139 __func__, __LINE__, ps3_result(result));
140 dump_node_name(lpar_id, n1, n2, n3, n4); 140 dump_node_name(lpar_id, n1, n2, n3, n4);
141 return -ENOENT; 141 return -ENOENT;
@@ -149,10 +149,10 @@ static int read_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
149 *_v2 = v2; 149 *_v2 = v2;
150 150
151 if (v1 && !_v1) 151 if (v1 && !_v1)
152 pr_debug("%s:%d: warning: discarding non-zero v1: %016llx\n", 152 pr_devel("%s:%d: warning: discarding non-zero v1: %016llx\n",
153 __func__, __LINE__, v1); 153 __func__, __LINE__, v1);
154 if (v2 && !_v2) 154 if (v2 && !_v2)
155 pr_debug("%s:%d: warning: discarding non-zero v2: %016llx\n", 155 pr_devel("%s:%d: warning: discarding non-zero v2: %016llx\n",
156 __func__, __LINE__, v2); 156 __func__, __LINE__, v2);
157 157
158 return 0; 158 return 0;
@@ -323,16 +323,16 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
323 result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev); 323 result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev);
324 324
325 if (result) { 325 if (result) {
326 pr_debug("%s:%d read_bus_num_dev failed\n", __func__, __LINE__); 326 pr_devel("%s:%d read_bus_num_dev failed\n", __func__, __LINE__);
327 return result; 327 return result;
328 } 328 }
329 329
330 pr_debug("%s:%d: bus_type %u, bus_index %u, bus_id %llu, num_dev %u\n", 330 pr_devel("%s:%d: bus_type %u, bus_index %u, bus_id %llu, num_dev %u\n",
331 __func__, __LINE__, tmp.bus_type, tmp.bus_index, tmp.bus_id, 331 __func__, __LINE__, tmp.bus_type, tmp.bus_index, tmp.bus_id,
332 num_dev); 332 num_dev);
333 333
334 if (tmp.dev_index >= num_dev) { 334 if (tmp.dev_index >= num_dev) {
335 pr_debug("%s:%d: no device found\n", __func__, __LINE__); 335 pr_devel("%s:%d: no device found\n", __func__, __LINE__);
336 return -ENODEV; 336 return -ENODEV;
337 } 337 }
338 338
@@ -340,7 +340,7 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
340 &tmp.dev_type); 340 &tmp.dev_type);
341 341
342 if (result) { 342 if (result) {
343 pr_debug("%s:%d read_dev_type failed\n", __func__, __LINE__); 343 pr_devel("%s:%d read_dev_type failed\n", __func__, __LINE__);
344 return result; 344 return result;
345 } 345 }
346 346
@@ -348,12 +348,12 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
348 &tmp.dev_id); 348 &tmp.dev_id);
349 349
350 if (result) { 350 if (result) {
351 pr_debug("%s:%d ps3_repository_read_dev_id failed\n", __func__, 351 pr_devel("%s:%d ps3_repository_read_dev_id failed\n", __func__,
352 __LINE__); 352 __LINE__);
353 return result; 353 return result;
354 } 354 }
355 355
356 pr_debug("%s:%d: found: dev_type %u, dev_index %u, dev_id %llu\n", 356 pr_devel("%s:%d: found: dev_type %u, dev_index %u, dev_id %llu\n",
357 __func__, __LINE__, tmp.dev_type, tmp.dev_index, tmp.dev_id); 357 __func__, __LINE__, tmp.dev_type, tmp.dev_index, tmp.dev_id);
358 358
359 *repo = tmp; 359 *repo = tmp;
@@ -367,14 +367,14 @@ int ps3_repository_find_device_by_id(struct ps3_repository_device *repo,
367 struct ps3_repository_device tmp; 367 struct ps3_repository_device tmp;
368 unsigned int num_dev; 368 unsigned int num_dev;
369 369
370 pr_debug(" -> %s:%u: find device by id %llu:%llu\n", __func__, __LINE__, 370 pr_devel(" -> %s:%u: find device by id %llu:%llu\n", __func__, __LINE__,
371 bus_id, dev_id); 371 bus_id, dev_id);
372 372
373 for (tmp.bus_index = 0; tmp.bus_index < 10; tmp.bus_index++) { 373 for (tmp.bus_index = 0; tmp.bus_index < 10; tmp.bus_index++) {
374 result = ps3_repository_read_bus_id(tmp.bus_index, 374 result = ps3_repository_read_bus_id(tmp.bus_index,
375 &tmp.bus_id); 375 &tmp.bus_id);
376 if (result) { 376 if (result) {
377 pr_debug("%s:%u read_bus_id(%u) failed\n", __func__, 377 pr_devel("%s:%u read_bus_id(%u) failed\n", __func__,
378 __LINE__, tmp.bus_index); 378 __LINE__, tmp.bus_index);
379 return result; 379 return result;
380 } 380 }
@@ -382,23 +382,23 @@ int ps3_repository_find_device_by_id(struct ps3_repository_device *repo,
382 if (tmp.bus_id == bus_id) 382 if (tmp.bus_id == bus_id)
383 goto found_bus; 383 goto found_bus;
384 384
385 pr_debug("%s:%u: skip, bus_id %llu\n", __func__, __LINE__, 385 pr_devel("%s:%u: skip, bus_id %llu\n", __func__, __LINE__,
386 tmp.bus_id); 386 tmp.bus_id);
387 } 387 }
388 pr_debug(" <- %s:%u: bus not found\n", __func__, __LINE__); 388 pr_devel(" <- %s:%u: bus not found\n", __func__, __LINE__);
389 return result; 389 return result;
390 390
391found_bus: 391found_bus:
392 result = ps3_repository_read_bus_type(tmp.bus_index, &tmp.bus_type); 392 result = ps3_repository_read_bus_type(tmp.bus_index, &tmp.bus_type);
393 if (result) { 393 if (result) {
394 pr_debug("%s:%u read_bus_type(%u) failed\n", __func__, 394 pr_devel("%s:%u read_bus_type(%u) failed\n", __func__,
395 __LINE__, tmp.bus_index); 395 __LINE__, tmp.bus_index);
396 return result; 396 return result;
397 } 397 }
398 398
399 result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev); 399 result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev);
400 if (result) { 400 if (result) {
401 pr_debug("%s:%u read_bus_num_dev failed\n", __func__, 401 pr_devel("%s:%u read_bus_num_dev failed\n", __func__,
402 __LINE__); 402 __LINE__);
403 return result; 403 return result;
404 } 404 }
@@ -408,7 +408,7 @@ found_bus:
408 tmp.dev_index, 408 tmp.dev_index,
409 &tmp.dev_id); 409 &tmp.dev_id);
410 if (result) { 410 if (result) {
411 pr_debug("%s:%u read_dev_id(%u:%u) failed\n", __func__, 411 pr_devel("%s:%u read_dev_id(%u:%u) failed\n", __func__,
412 __LINE__, tmp.bus_index, tmp.dev_index); 412 __LINE__, tmp.bus_index, tmp.dev_index);
413 return result; 413 return result;
414 } 414 }
@@ -416,21 +416,21 @@ found_bus:
416 if (tmp.dev_id == dev_id) 416 if (tmp.dev_id == dev_id)
417 goto found_dev; 417 goto found_dev;
418 418
419 pr_debug("%s:%u: skip, dev_id %llu\n", __func__, __LINE__, 419 pr_devel("%s:%u: skip, dev_id %llu\n", __func__, __LINE__,
420 tmp.dev_id); 420 tmp.dev_id);
421 } 421 }
422 pr_debug(" <- %s:%u: dev not found\n", __func__, __LINE__); 422 pr_devel(" <- %s:%u: dev not found\n", __func__, __LINE__);
423 return result; 423 return result;
424 424
425found_dev: 425found_dev:
426 result = ps3_repository_read_dev_type(tmp.bus_index, tmp.dev_index, 426 result = ps3_repository_read_dev_type(tmp.bus_index, tmp.dev_index,
427 &tmp.dev_type); 427 &tmp.dev_type);
428 if (result) { 428 if (result) {
429 pr_debug("%s:%u read_dev_type failed\n", __func__, __LINE__); 429 pr_devel("%s:%u read_dev_type failed\n", __func__, __LINE__);
430 return result; 430 return result;
431 } 431 }
432 432
433 pr_debug(" <- %s:%u: found: type (%u:%u) index (%u:%u) id (%llu:%llu)\n", 433 pr_devel(" <- %s:%u: found: type (%u:%u) index (%u:%u) id (%llu:%llu)\n",
434 __func__, __LINE__, tmp.bus_type, tmp.dev_type, tmp.bus_index, 434 __func__, __LINE__, tmp.bus_type, tmp.dev_type, tmp.bus_index,
435 tmp.dev_index, tmp.bus_id, tmp.dev_id); 435 tmp.dev_index, tmp.bus_id, tmp.dev_id);
436 *repo = tmp; 436 *repo = tmp;
@@ -443,18 +443,18 @@ int __devinit ps3_repository_find_devices(enum ps3_bus_type bus_type,
443 int result = 0; 443 int result = 0;
444 struct ps3_repository_device repo; 444 struct ps3_repository_device repo;
445 445
446 pr_debug(" -> %s:%d: find bus_type %u\n", __func__, __LINE__, bus_type); 446 pr_devel(" -> %s:%d: find bus_type %u\n", __func__, __LINE__, bus_type);
447 447
448 repo.bus_type = bus_type; 448 repo.bus_type = bus_type;
449 result = ps3_repository_find_bus(repo.bus_type, 0, &repo.bus_index); 449 result = ps3_repository_find_bus(repo.bus_type, 0, &repo.bus_index);
450 if (result) { 450 if (result) {
451 pr_debug(" <- %s:%u: bus not found\n", __func__, __LINE__); 451 pr_devel(" <- %s:%u: bus not found\n", __func__, __LINE__);
452 return result; 452 return result;
453 } 453 }
454 454
455 result = ps3_repository_read_bus_id(repo.bus_index, &repo.bus_id); 455 result = ps3_repository_read_bus_id(repo.bus_index, &repo.bus_id);
456 if (result) { 456 if (result) {
457 pr_debug("%s:%d read_bus_id(%u) failed\n", __func__, __LINE__, 457 pr_devel("%s:%d read_bus_id(%u) failed\n", __func__, __LINE__,
458 repo.bus_index); 458 repo.bus_index);
459 return result; 459 return result;
460 } 460 }
@@ -469,13 +469,13 @@ int __devinit ps3_repository_find_devices(enum ps3_bus_type bus_type,
469 469
470 result = callback(&repo); 470 result = callback(&repo);
471 if (result) { 471 if (result) {
472 pr_debug("%s:%d: abort at callback\n", __func__, 472 pr_devel("%s:%d: abort at callback\n", __func__,
473 __LINE__); 473 __LINE__);
474 break; 474 break;
475 } 475 }
476 } 476 }
477 477
478 pr_debug(" <- %s:%d\n", __func__, __LINE__); 478 pr_devel(" <- %s:%d\n", __func__, __LINE__);
479 return result; 479 return result;
480} 480}
481 481
@@ -489,7 +489,7 @@ int ps3_repository_find_bus(enum ps3_bus_type bus_type, unsigned int from,
489 for (i = from; i < 10; i++) { 489 for (i = from; i < 10; i++) {
490 error = ps3_repository_read_bus_type(i, &type); 490 error = ps3_repository_read_bus_type(i, &type);
491 if (error) { 491 if (error) {
492 pr_debug("%s:%d read_bus_type failed\n", 492 pr_devel("%s:%d read_bus_type failed\n",
493 __func__, __LINE__); 493 __func__, __LINE__);
494 *bus_index = UINT_MAX; 494 *bus_index = UINT_MAX;
495 return error; 495 return error;
@@ -509,7 +509,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
509 int result = 0; 509 int result = 0;
510 unsigned int res_index; 510 unsigned int res_index;
511 511
512 pr_debug("%s:%d: find intr_type %u\n", __func__, __LINE__, intr_type); 512 pr_devel("%s:%d: find intr_type %u\n", __func__, __LINE__, intr_type);
513 513
514 *interrupt_id = UINT_MAX; 514 *interrupt_id = UINT_MAX;
515 515
@@ -521,7 +521,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
521 repo->dev_index, res_index, &t, &id); 521 repo->dev_index, res_index, &t, &id);
522 522
523 if (result) { 523 if (result) {
524 pr_debug("%s:%d read_dev_intr failed\n", 524 pr_devel("%s:%d read_dev_intr failed\n",
525 __func__, __LINE__); 525 __func__, __LINE__);
526 return result; 526 return result;
527 } 527 }
@@ -535,7 +535,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
535 if (res_index == 10) 535 if (res_index == 10)
536 return -ENODEV; 536 return -ENODEV;
537 537
538 pr_debug("%s:%d: found intr_type %u at res_index %u\n", 538 pr_devel("%s:%d: found intr_type %u at res_index %u\n",
539 __func__, __LINE__, intr_type, res_index); 539 __func__, __LINE__, intr_type, res_index);
540 540
541 return result; 541 return result;
@@ -547,7 +547,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
547 int result = 0; 547 int result = 0;
548 unsigned int res_index; 548 unsigned int res_index;
549 549
550 pr_debug("%s:%d: find reg_type %u\n", __func__, __LINE__, reg_type); 550 pr_devel("%s:%d: find reg_type %u\n", __func__, __LINE__, reg_type);
551 551
552 *bus_addr = *len = 0; 552 *bus_addr = *len = 0;
553 553
@@ -560,7 +560,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
560 repo->dev_index, res_index, &t, &a, &l); 560 repo->dev_index, res_index, &t, &a, &l);
561 561
562 if (result) { 562 if (result) {
563 pr_debug("%s:%d read_dev_reg failed\n", 563 pr_devel("%s:%d read_dev_reg failed\n",
564 __func__, __LINE__); 564 __func__, __LINE__);
565 return result; 565 return result;
566 } 566 }
@@ -575,7 +575,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
575 if (res_index == 10) 575 if (res_index == 10)
576 return -ENODEV; 576 return -ENODEV;
577 577
578 pr_debug("%s:%d: found reg_type %u at res_index %u\n", 578 pr_devel("%s:%d: found reg_type %u at res_index %u\n",
579 __func__, __LINE__, reg_type, res_index); 579 __func__, __LINE__, reg_type, res_index);
580 580
581 return result; 581 return result;
@@ -1009,7 +1009,7 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
1009 int result = 0; 1009 int result = 0;
1010 unsigned int res_index; 1010 unsigned int res_index;
1011 1011
1012 pr_debug(" -> %s:%d: (%u:%u)\n", __func__, __LINE__, 1012 pr_devel(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
1013 repo->bus_index, repo->dev_index); 1013 repo->bus_index, repo->dev_index);
1014 1014
1015 for (res_index = 0; res_index < 10; res_index++) { 1015 for (res_index = 0; res_index < 10; res_index++) {
@@ -1021,13 +1021,13 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
1021 1021
1022 if (result) { 1022 if (result) {
1023 if (result != LV1_NO_ENTRY) 1023 if (result != LV1_NO_ENTRY)
1024 pr_debug("%s:%d ps3_repository_read_dev_intr" 1024 pr_devel("%s:%d ps3_repository_read_dev_intr"
1025 " (%u:%u) failed\n", __func__, __LINE__, 1025 " (%u:%u) failed\n", __func__, __LINE__,
1026 repo->bus_index, repo->dev_index); 1026 repo->bus_index, repo->dev_index);
1027 break; 1027 break;
1028 } 1028 }
1029 1029
1030 pr_debug("%s:%d (%u:%u) intr_type %u, interrupt_id %u\n", 1030 pr_devel("%s:%d (%u:%u) intr_type %u, interrupt_id %u\n",
1031 __func__, __LINE__, repo->bus_index, repo->dev_index, 1031 __func__, __LINE__, repo->bus_index, repo->dev_index,
1032 intr_type, interrupt_id); 1032 intr_type, interrupt_id);
1033 } 1033 }
@@ -1042,18 +1042,18 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
1042 1042
1043 if (result) { 1043 if (result) {
1044 if (result != LV1_NO_ENTRY) 1044 if (result != LV1_NO_ENTRY)
1045 pr_debug("%s:%d ps3_repository_read_dev_reg" 1045 pr_devel("%s:%d ps3_repository_read_dev_reg"
1046 " (%u:%u) failed\n", __func__, __LINE__, 1046 " (%u:%u) failed\n", __func__, __LINE__,
1047 repo->bus_index, repo->dev_index); 1047 repo->bus_index, repo->dev_index);
1048 break; 1048 break;
1049 } 1049 }
1050 1050
1051 pr_debug("%s:%d (%u:%u) reg_type %u, bus_addr %lxh, len %lxh\n", 1051 pr_devel("%s:%d (%u:%u) reg_type %u, bus_addr %llxh, len %llxh\n",
1052 __func__, __LINE__, repo->bus_index, repo->dev_index, 1052 __func__, __LINE__, repo->bus_index, repo->dev_index,
1053 reg_type, bus_addr, len); 1053 reg_type, bus_addr, len);
1054 } 1054 }
1055 1055
1056 pr_debug(" <- %s:%d\n", __func__, __LINE__); 1056 pr_devel(" <- %s:%d\n", __func__, __LINE__);
1057 return result; 1057 return result;
1058} 1058}
1059 1059
@@ -1063,22 +1063,22 @@ static int dump_stor_dev_info(struct ps3_repository_device *repo)
1063 unsigned int num_regions, region_index; 1063 unsigned int num_regions, region_index;
1064 u64 port, blk_size, num_blocks; 1064 u64 port, blk_size, num_blocks;
1065 1065
1066 pr_debug(" -> %s:%d: (%u:%u)\n", __func__, __LINE__, 1066 pr_devel(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
1067 repo->bus_index, repo->dev_index); 1067 repo->bus_index, repo->dev_index);
1068 1068
1069 result = ps3_repository_read_stor_dev_info(repo->bus_index, 1069 result = ps3_repository_read_stor_dev_info(repo->bus_index,
1070 repo->dev_index, &port, &blk_size, &num_blocks, &num_regions); 1070 repo->dev_index, &port, &blk_size, &num_blocks, &num_regions);
1071 if (result) { 1071 if (result) {
1072 pr_debug("%s:%d ps3_repository_read_stor_dev_info" 1072 pr_devel("%s:%d ps3_repository_read_stor_dev_info"
1073 " (%u:%u) failed\n", __func__, __LINE__, 1073 " (%u:%u) failed\n", __func__, __LINE__,
1074 repo->bus_index, repo->dev_index); 1074 repo->bus_index, repo->dev_index);
1075 goto out; 1075 goto out;
1076 } 1076 }
1077 1077
1078 pr_debug("%s:%d (%u:%u): port %lu, blk_size %lu, num_blocks " 1078 pr_devel("%s:%d (%u:%u): port %llu, blk_size %llu, num_blocks "
1079 "%lu, num_regions %u\n", 1079 "%llu, num_regions %u\n",
1080 __func__, __LINE__, repo->bus_index, repo->dev_index, port, 1080 __func__, __LINE__, repo->bus_index, repo->dev_index,
1081 blk_size, num_blocks, num_regions); 1081 port, blk_size, num_blocks, num_regions);
1082 1082
1083 for (region_index = 0; region_index < num_regions; region_index++) { 1083 for (region_index = 0; region_index < num_regions; region_index++) {
1084 unsigned int region_id; 1084 unsigned int region_id;
@@ -1088,19 +1088,20 @@ static int dump_stor_dev_info(struct ps3_repository_device *repo)
1088 repo->dev_index, region_index, &region_id, 1088 repo->dev_index, region_index, &region_id,
1089 &region_start, &region_size); 1089 &region_start, &region_size);
1090 if (result) { 1090 if (result) {
1091 pr_debug("%s:%d ps3_repository_read_stor_dev_region" 1091 pr_devel("%s:%d ps3_repository_read_stor_dev_region"
1092 " (%u:%u) failed\n", __func__, __LINE__, 1092 " (%u:%u) failed\n", __func__, __LINE__,
1093 repo->bus_index, repo->dev_index); 1093 repo->bus_index, repo->dev_index);
1094 break; 1094 break;
1095 } 1095 }
1096 1096
1097 pr_debug("%s:%d (%u:%u) region_id %u, start %lxh, size %lxh\n", 1097 pr_devel("%s:%d (%u:%u) region_id %u, start %lxh, size %lxh\n",
1098 __func__, __LINE__, repo->bus_index, repo->dev_index, 1098 __func__, __LINE__, repo->bus_index, repo->dev_index,
1099 region_id, region_start, region_size); 1099 region_id, (unsigned long)region_start,
1100 (unsigned long)region_size);
1100 } 1101 }
1101 1102
1102out: 1103out:
1103 pr_debug(" <- %s:%d\n", __func__, __LINE__); 1104 pr_devel(" <- %s:%d\n", __func__, __LINE__);
1104 return result; 1105 return result;
1105} 1106}
1106 1107
@@ -1109,7 +1110,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
1109{ 1110{
1110 int result = 0; 1111 int result = 0;
1111 1112
1112 pr_debug(" -> %s:%d: bus_%u\n", __func__, __LINE__, repo->bus_index); 1113 pr_devel(" -> %s:%d: bus_%u\n", __func__, __LINE__, repo->bus_index);
1113 1114
1114 for (repo->dev_index = 0; repo->dev_index < num_dev; 1115 for (repo->dev_index = 0; repo->dev_index < num_dev;
1115 repo->dev_index++) { 1116 repo->dev_index++) {
@@ -1118,7 +1119,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
1118 repo->dev_index, &repo->dev_type); 1119 repo->dev_index, &repo->dev_type);
1119 1120
1120 if (result) { 1121 if (result) {
1121 pr_debug("%s:%d ps3_repository_read_dev_type" 1122 pr_devel("%s:%d ps3_repository_read_dev_type"
1122 " (%u:%u) failed\n", __func__, __LINE__, 1123 " (%u:%u) failed\n", __func__, __LINE__,
1123 repo->bus_index, repo->dev_index); 1124 repo->bus_index, repo->dev_index);
1124 break; 1125 break;
@@ -1128,15 +1129,15 @@ static int dump_device_info(struct ps3_repository_device *repo,
1128 repo->dev_index, &repo->dev_id); 1129 repo->dev_index, &repo->dev_id);
1129 1130
1130 if (result) { 1131 if (result) {
1131 pr_debug("%s:%d ps3_repository_read_dev_id" 1132 pr_devel("%s:%d ps3_repository_read_dev_id"
1132 " (%u:%u) failed\n", __func__, __LINE__, 1133 " (%u:%u) failed\n", __func__, __LINE__,
1133 repo->bus_index, repo->dev_index); 1134 repo->bus_index, repo->dev_index);
1134 continue; 1135 continue;
1135 } 1136 }
1136 1137
1137 pr_debug("%s:%d (%u:%u): dev_type %u, dev_id %lu\n", __func__, 1138 pr_devel("%s:%d (%u:%u): dev_type %u, dev_id %lu\n", __func__,
1138 __LINE__, repo->bus_index, repo->dev_index, 1139 __LINE__, repo->bus_index, repo->dev_index,
1139 repo->dev_type, repo->dev_id); 1140 repo->dev_type, (unsigned long)repo->dev_id);
1140 1141
1141 ps3_repository_dump_resource_info(repo); 1142 ps3_repository_dump_resource_info(repo);
1142 1143
@@ -1144,7 +1145,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
1144 dump_stor_dev_info(repo); 1145 dump_stor_dev_info(repo);
1145 } 1146 }
1146 1147
1147 pr_debug(" <- %s:%d\n", __func__, __LINE__); 1148 pr_devel(" <- %s:%d\n", __func__, __LINE__);
1148 return result; 1149 return result;
1149} 1150}
1150 1151
@@ -1153,7 +1154,7 @@ int ps3_repository_dump_bus_info(void)
1153 int result = 0; 1154 int result = 0;
1154 struct ps3_repository_device repo; 1155 struct ps3_repository_device repo;
1155 1156
1156 pr_debug(" -> %s:%d\n", __func__, __LINE__); 1157 pr_devel(" -> %s:%d\n", __func__, __LINE__);
1157 1158
1158 memset(&repo, 0, sizeof(repo)); 1159 memset(&repo, 0, sizeof(repo));
1159 1160
@@ -1164,7 +1165,7 @@ int ps3_repository_dump_bus_info(void)
1164 &repo.bus_type); 1165 &repo.bus_type);
1165 1166
1166 if (result) { 1167 if (result) {
1167 pr_debug("%s:%d read_bus_type(%u) failed\n", 1168 pr_devel("%s:%d read_bus_type(%u) failed\n",
1168 __func__, __LINE__, repo.bus_index); 1169 __func__, __LINE__, repo.bus_index);
1169 break; 1170 break;
1170 } 1171 }
@@ -1173,32 +1174,32 @@ int ps3_repository_dump_bus_info(void)
1173 &repo.bus_id); 1174 &repo.bus_id);
1174 1175
1175 if (result) { 1176 if (result) {
1176 pr_debug("%s:%d read_bus_id(%u) failed\n", 1177 pr_devel("%s:%d read_bus_id(%u) failed\n",
1177 __func__, __LINE__, repo.bus_index); 1178 __func__, __LINE__, repo.bus_index);
1178 continue; 1179 continue;
1179 } 1180 }
1180 1181
1181 if (repo.bus_index != repo.bus_id) 1182 if (repo.bus_index != repo.bus_id)
1182 pr_debug("%s:%d bus_index != bus_id\n", 1183 pr_devel("%s:%d bus_index != bus_id\n",
1183 __func__, __LINE__); 1184 __func__, __LINE__);
1184 1185
1185 result = ps3_repository_read_bus_num_dev(repo.bus_index, 1186 result = ps3_repository_read_bus_num_dev(repo.bus_index,
1186 &num_dev); 1187 &num_dev);
1187 1188
1188 if (result) { 1189 if (result) {
1189 pr_debug("%s:%d read_bus_num_dev(%u) failed\n", 1190 pr_devel("%s:%d read_bus_num_dev(%u) failed\n",
1190 __func__, __LINE__, repo.bus_index); 1191 __func__, __LINE__, repo.bus_index);
1191 continue; 1192 continue;
1192 } 1193 }
1193 1194
1194 pr_debug("%s:%d bus_%u: bus_type %u, bus_id %lu, num_dev %u\n", 1195 pr_devel("%s:%d bus_%u: bus_type %u, bus_id %lu, num_dev %u\n",
1195 __func__, __LINE__, repo.bus_index, repo.bus_type, 1196 __func__, __LINE__, repo.bus_index, repo.bus_type,
1196 repo.bus_id, num_dev); 1197 (unsigned long)repo.bus_id, num_dev);
1197 1198
1198 dump_device_info(&repo, num_dev); 1199 dump_device_info(&repo, num_dev);
1199 } 1200 }
1200 1201
1201 pr_debug(" <- %s:%d\n", __func__, __LINE__); 1202 pr_devel(" <- %s:%d\n", __func__, __LINE__);
1202 return result; 1203 return result;
1203} 1204}
1204 1205
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index e8ec1b2bfff..2d664c5a83b 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -193,10 +193,12 @@ static int ps3_set_dabr(unsigned long dabr)
193 193
194static void __init ps3_setup_arch(void) 194static void __init ps3_setup_arch(void)
195{ 195{
196 u64 tmp;
196 197
197 DBG(" -> %s:%d\n", __func__, __LINE__); 198 DBG(" -> %s:%d\n", __func__, __LINE__);
198 199
199 lv1_get_version_info(&ps3_firmware_version.raw); 200 lv1_get_version_info(&ps3_firmware_version.raw, &tmp);
201
200 printk(KERN_INFO "PS3 firmware version %u.%u.%u\n", 202 printk(KERN_INFO "PS3 firmware version %u.%u.%u\n",
201 ps3_firmware_version.major, ps3_firmware_version.minor, 203 ps3_firmware_version.major, ps3_firmware_version.minor,
202 ps3_firmware_version.rev); 204 ps3_firmware_version.rev);
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c
index efc1cd8c034..4b35166229f 100644
--- a/arch/powerpc/platforms/ps3/smp.c
+++ b/arch/powerpc/platforms/ps3/smp.c
@@ -57,7 +57,7 @@ static void ps3_smp_message_pass(int cpu, int msg)
57 " (%d)\n", __func__, __LINE__, cpu, msg, result); 57 " (%d)\n", __func__, __LINE__, cpu, msg, result);
58} 58}
59 59
60static int ps3_smp_probe(void) 60static int __init ps3_smp_probe(void)
61{ 61{
62 int cpu; 62 int cpu;
63 63
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index 451fad1c92a..e17fa1432d8 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -154,7 +154,7 @@ static unsigned long get_vas_id(void)
154 u64 id; 154 u64 id;
155 155
156 lv1_get_logical_ppe_id(&id); 156 lv1_get_logical_ppe_id(&id);
157 lv1_get_virtual_address_space_id_of_ppe(id, &id); 157 lv1_get_virtual_address_space_id_of_ppe(&id);
158 158
159 return id; 159 return id;
160} 160}
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index c81f6bb9c10..ae7b6d41fed 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -120,3 +120,12 @@ config DTL
120 which are accessible through a debugfs file. 120 which are accessible through a debugfs file.
121 121
122 Say N if you are unsure. 122 Say N if you are unsure.
123
124config PSERIES_IDLE
125 tristate "Cpuidle driver for pSeries platforms"
126 depends on CPU_IDLE
127 depends on PPC_PSERIES
128 default y
129 help
130 Select this option to enable processor idle state management
131 through cpuidle subsystem.
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 3556e402cbf..236db46b407 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PHYP_DUMP) += phyp_dump.o
22obj-$(CONFIG_CMM) += cmm.o 22obj-$(CONFIG_CMM) += cmm.o
23obj-$(CONFIG_DTL) += dtl.o 23obj-$(CONFIG_DTL) += dtl.o
24obj-$(CONFIG_IO_EVENT_IRQ) += io_event_irq.o 24obj-$(CONFIG_IO_EVENT_IRQ) += io_event_irq.o
25obj-$(CONFIG_PSERIES_IDLE) += processor_idle.o
25 26
26ifeq ($(CONFIG_PPC_PSERIES),y) 27ifeq ($(CONFIG_PPC_PSERIES),y)
27obj-$(CONFIG_SUSPEND) += suspend.o 28obj-$(CONFIG_SUSPEND) += suspend.o
diff --git a/arch/powerpc/platforms/pseries/hvCall_inst.c b/arch/powerpc/platforms/pseries/hvCall_inst.c
index f106662f438..c9311cfdfca 100644
--- a/arch/powerpc/platforms/pseries/hvCall_inst.c
+++ b/arch/powerpc/platforms/pseries/hvCall_inst.c
@@ -109,7 +109,7 @@ static void probe_hcall_entry(void *ignored, unsigned long opcode, unsigned long
109 if (opcode > MAX_HCALL_OPCODE) 109 if (opcode > MAX_HCALL_OPCODE)
110 return; 110 return;
111 111
112 h = &get_cpu_var(hcall_stats)[opcode / 4]; 112 h = &__get_cpu_var(hcall_stats)[opcode / 4];
113 h->tb_start = mftb(); 113 h->tb_start = mftb();
114 h->purr_start = mfspr(SPRN_PURR); 114 h->purr_start = mfspr(SPRN_PURR);
115} 115}
@@ -126,8 +126,6 @@ static void probe_hcall_exit(void *ignored, unsigned long opcode, unsigned long
126 h->num_calls++; 126 h->num_calls++;
127 h->tb_total += mftb() - h->tb_start; 127 h->tb_total += mftb() - h->tb_start;
128 h->purr_total += mfspr(SPRN_PURR) - h->purr_start; 128 h->purr_total += mfspr(SPRN_PURR) - h->purr_start;
129
130 put_cpu_var(hcall_stats);
131} 129}
132 130
133static int __init hcall_inst_init(void) 131static int __init hcall_inst_init(void)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index b719d970973..c442f2b1980 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -52,13 +52,42 @@
52#include "plpar_wrappers.h" 52#include "plpar_wrappers.h"
53 53
54 54
55static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
56 u64 *startp, u64 *endp)
57{
58 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
59 unsigned long start, end, inc;
60
61 start = __pa(startp);
62 end = __pa(endp);
63 inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
64
65 /* If this is non-zero, change the format. We shift the
66 * address and or in the magic from the device tree. */
67 if (tbl->it_busno) {
68 start <<= 12;
69 end <<= 12;
70 inc <<= 12;
71 start |= tbl->it_busno;
72 end |= tbl->it_busno;
73 }
74
75 end |= inc - 1; /* round up end to be different than start */
76
77 mb(); /* Make sure TCEs in memory are written */
78 while (start <= end) {
79 out_be64(invalidate, start);
80 start += inc;
81 }
82}
83
55static int tce_build_pSeries(struct iommu_table *tbl, long index, 84static int tce_build_pSeries(struct iommu_table *tbl, long index,
56 long npages, unsigned long uaddr, 85 long npages, unsigned long uaddr,
57 enum dma_data_direction direction, 86 enum dma_data_direction direction,
58 struct dma_attrs *attrs) 87 struct dma_attrs *attrs)
59{ 88{
60 u64 proto_tce; 89 u64 proto_tce;
61 u64 *tcep; 90 u64 *tcep, *tces;
62 u64 rpn; 91 u64 rpn;
63 92
64 proto_tce = TCE_PCI_READ; // Read allowed 93 proto_tce = TCE_PCI_READ; // Read allowed
@@ -66,7 +95,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
66 if (direction != DMA_TO_DEVICE) 95 if (direction != DMA_TO_DEVICE)
67 proto_tce |= TCE_PCI_WRITE; 96 proto_tce |= TCE_PCI_WRITE;
68 97
69 tcep = ((u64 *)tbl->it_base) + index; 98 tces = tcep = ((u64 *)tbl->it_base) + index;
70 99
71 while (npages--) { 100 while (npages--) {
72 /* can't move this out since we might cross MEMBLOCK boundary */ 101 /* can't move this out since we might cross MEMBLOCK boundary */
@@ -76,18 +105,24 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
76 uaddr += TCE_PAGE_SIZE; 105 uaddr += TCE_PAGE_SIZE;
77 tcep++; 106 tcep++;
78 } 107 }
108
109 if (tbl->it_type == TCE_PCI_SWINV_CREATE)
110 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
79 return 0; 111 return 0;
80} 112}
81 113
82 114
83static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 115static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
84{ 116{
85 u64 *tcep; 117 u64 *tcep, *tces;
86 118
87 tcep = ((u64 *)tbl->it_base) + index; 119 tces = tcep = ((u64 *)tbl->it_base) + index;
88 120
89 while (npages--) 121 while (npages--)
90 *(tcep++) = 0; 122 *(tcep++) = 0;
123
124 if (tbl->it_type == TCE_PCI_SWINV_FREE)
125 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
91} 126}
92 127
93static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 128static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
@@ -425,7 +460,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
425 struct iommu_table *tbl) 460 struct iommu_table *tbl)
426{ 461{
427 struct device_node *node; 462 struct device_node *node;
428 const unsigned long *basep; 463 const unsigned long *basep, *sw_inval;
429 const u32 *sizep; 464 const u32 *sizep;
430 465
431 node = phb->dn; 466 node = phb->dn;
@@ -462,6 +497,22 @@ static void iommu_table_setparms(struct pci_controller *phb,
462 tbl->it_index = 0; 497 tbl->it_index = 0;
463 tbl->it_blocksize = 16; 498 tbl->it_blocksize = 16;
464 tbl->it_type = TCE_PCI; 499 tbl->it_type = TCE_PCI;
500
501 sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
502 if (sw_inval) {
503 /*
504 * This property contains information on how to
505 * invalidate the TCE entry. The first property is
506 * the base MMIO address used to invalidate entries.
507 * The second property tells us the format of the TCE
508 * invalidate (whether it needs to be shifted) and
509 * some magic routing info to add to our invalidate
510 * command.
511 */
512 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
513 tbl->it_busno = sw_inval[1]; /* overload this with magic */
514 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
515 }
465} 516}
466 517
467/* 518/*
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 52d429be6c7..948e0e3b354 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -554,6 +554,7 @@ void __trace_hcall_entry(unsigned long opcode, unsigned long *args)
554 goto out; 554 goto out;
555 555
556 (*depth)++; 556 (*depth)++;
557 preempt_disable();
557 trace_hcall_entry(opcode, args); 558 trace_hcall_entry(opcode, args);
558 if (opcode == H_CEDE) 559 if (opcode == H_CEDE)
559 rcu_idle_enter(); 560 rcu_idle_enter();
@@ -580,6 +581,7 @@ void __trace_hcall_exit(long opcode, unsigned long retval,
580 if (opcode == H_CEDE) 581 if (opcode == H_CEDE)
581 rcu_idle_exit(); 582 rcu_idle_exit();
582 trace_hcall_exit(opcode, retval, retbuf); 583 trace_hcall_exit(opcode, retval, retbuf);
584 preempt_enable();
583 (*depth)--; 585 (*depth)--;
584 586
585out: 587out:
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index a76b22844d1..330a57b7c17 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -625,6 +625,8 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
625{ 625{
626 static unsigned int oops_count = 0; 626 static unsigned int oops_count = 0;
627 static bool panicking = false; 627 static bool panicking = false;
628 static DEFINE_SPINLOCK(lock);
629 unsigned long flags;
628 size_t text_len; 630 size_t text_len;
629 unsigned int err_type = ERR_TYPE_KERNEL_PANIC_GZ; 631 unsigned int err_type = ERR_TYPE_KERNEL_PANIC_GZ;
630 int rc = -1; 632 int rc = -1;
@@ -655,6 +657,9 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
655 if (clobbering_unread_rtas_event()) 657 if (clobbering_unread_rtas_event())
656 return; 658 return;
657 659
660 if (!spin_trylock_irqsave(&lock, flags))
661 return;
662
658 if (big_oops_buf) { 663 if (big_oops_buf) {
659 text_len = capture_last_msgs(old_msgs, old_len, 664 text_len = capture_last_msgs(old_msgs, old_len,
660 new_msgs, new_len, big_oops_buf, big_oops_buf_sz); 665 new_msgs, new_len, big_oops_buf, big_oops_buf_sz);
@@ -670,4 +675,6 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
670 675
671 (void) nvram_write_os_partition(&oops_log_partition, oops_buf, 676 (void) nvram_write_os_partition(&oops_log_partition, oops_buf,
672 (int) (sizeof(*oops_len) + *oops_len), err_type, ++oops_count); 677 (int) (sizeof(*oops_len) + *oops_len), err_type, ++oops_count);
678
679 spin_unlock_irqrestore(&lock, flags);
673} 680}
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
new file mode 100644
index 00000000000..085fd3f45ad
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -0,0 +1,329 @@
1/*
2 * processor_idle - idle state cpuidle driver.
3 * Adapted from drivers/idle/intel_idle.c and
4 * drivers/acpi/processor_idle.c
5 *
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/moduleparam.h>
12#include <linux/cpuidle.h>
13#include <linux/cpu.h>
14
15#include <asm/paca.h>
16#include <asm/reg.h>
17#include <asm/system.h>
18#include <asm/machdep.h>
19#include <asm/firmware.h>
20
21#include "plpar_wrappers.h"
22#include "pseries.h"
23
24struct cpuidle_driver pseries_idle_driver = {
25 .name = "pseries_idle",
26 .owner = THIS_MODULE,
27};
28
29#define MAX_IDLE_STATE_COUNT 2
30
31static int max_idle_state = MAX_IDLE_STATE_COUNT - 1;
32static struct cpuidle_device __percpu *pseries_cpuidle_devices;
33static struct cpuidle_state *cpuidle_state_table;
34
35void update_smt_snooze_delay(int snooze)
36{
37 struct cpuidle_driver *drv = cpuidle_get_driver();
38 if (drv)
39 drv->states[0].target_residency = snooze;
40}
41
42static inline void idle_loop_prolog(unsigned long *in_purr, ktime_t *kt_before)
43{
44
45 *kt_before = ktime_get_real();
46 *in_purr = mfspr(SPRN_PURR);
47 /*
48 * Indicate to the HV that we are idle. Now would be
49 * a good time to find other work to dispatch.
50 */
51 get_lppaca()->idle = 1;
52}
53
54static inline s64 idle_loop_epilog(unsigned long in_purr, ktime_t kt_before)
55{
56 get_lppaca()->wait_state_cycles += mfspr(SPRN_PURR) - in_purr;
57 get_lppaca()->idle = 0;
58
59 return ktime_to_us(ktime_sub(ktime_get_real(), kt_before));
60}
61
62static int snooze_loop(struct cpuidle_device *dev,
63 struct cpuidle_driver *drv,
64 int index)
65{
66 unsigned long in_purr;
67 ktime_t kt_before;
68 unsigned long start_snooze;
69 long snooze = drv->states[0].target_residency;
70
71 idle_loop_prolog(&in_purr, &kt_before);
72
73 if (snooze) {
74 start_snooze = get_tb() + snooze * tb_ticks_per_usec;
75 local_irq_enable();
76 set_thread_flag(TIF_POLLING_NRFLAG);
77
78 while ((snooze < 0) || (get_tb() < start_snooze)) {
79 if (need_resched() || cpu_is_offline(dev->cpu))
80 goto out;
81 ppc64_runlatch_off();
82 HMT_low();
83 HMT_very_low();
84 }
85
86 HMT_medium();
87 clear_thread_flag(TIF_POLLING_NRFLAG);
88 smp_mb();
89 local_irq_disable();
90 }
91
92out:
93 HMT_medium();
94 dev->last_residency =
95 (int)idle_loop_epilog(in_purr, kt_before);
96 return index;
97}
98
99static int dedicated_cede_loop(struct cpuidle_device *dev,
100 struct cpuidle_driver *drv,
101 int index)
102{
103 unsigned long in_purr;
104 ktime_t kt_before;
105
106 idle_loop_prolog(&in_purr, &kt_before);
107 get_lppaca()->donate_dedicated_cpu = 1;
108
109 ppc64_runlatch_off();
110 HMT_medium();
111 cede_processor();
112
113 get_lppaca()->donate_dedicated_cpu = 0;
114 dev->last_residency =
115 (int)idle_loop_epilog(in_purr, kt_before);
116 return index;
117}
118
119static int shared_cede_loop(struct cpuidle_device *dev,
120 struct cpuidle_driver *drv,
121 int index)
122{
123 unsigned long in_purr;
124 ktime_t kt_before;
125
126 idle_loop_prolog(&in_purr, &kt_before);
127
128 /*
129 * Yield the processor to the hypervisor. We return if
130 * an external interrupt occurs (which are driven prior
131 * to returning here) or if a prod occurs from another
132 * processor. When returning here, external interrupts
133 * are enabled.
134 */
135 cede_processor();
136
137 dev->last_residency =
138 (int)idle_loop_epilog(in_purr, kt_before);
139 return index;
140}
141
142/*
143 * States for dedicated partition case.
144 */
145static struct cpuidle_state dedicated_states[MAX_IDLE_STATE_COUNT] = {
146 { /* Snooze */
147 .name = "snooze",
148 .desc = "snooze",
149 .flags = CPUIDLE_FLAG_TIME_VALID,
150 .exit_latency = 0,
151 .target_residency = 0,
152 .enter = &snooze_loop },
153 { /* CEDE */
154 .name = "CEDE",
155 .desc = "CEDE",
156 .flags = CPUIDLE_FLAG_TIME_VALID,
157 .exit_latency = 1,
158 .target_residency = 10,
159 .enter = &dedicated_cede_loop },
160};
161
162/*
163 * States for shared partition case.
164 */
165static struct cpuidle_state shared_states[MAX_IDLE_STATE_COUNT] = {
166 { /* Shared Cede */
167 .name = "Shared Cede",
168 .desc = "Shared Cede",
169 .flags = CPUIDLE_FLAG_TIME_VALID,
170 .exit_latency = 0,
171 .target_residency = 0,
172 .enter = &shared_cede_loop },
173};
174
175int pseries_notify_cpuidle_add_cpu(int cpu)
176{
177 struct cpuidle_device *dev =
178 per_cpu_ptr(pseries_cpuidle_devices, cpu);
179 if (dev && cpuidle_get_driver()) {
180 cpuidle_disable_device(dev);
181 cpuidle_enable_device(dev);
182 }
183 return 0;
184}
185
186/*
187 * pseries_cpuidle_driver_init()
188 */
189static int pseries_cpuidle_driver_init(void)
190{
191 int idle_state;
192 struct cpuidle_driver *drv = &pseries_idle_driver;
193
194 drv->state_count = 0;
195
196 for (idle_state = 0; idle_state < MAX_IDLE_STATE_COUNT; ++idle_state) {
197
198 if (idle_state > max_idle_state)
199 break;
200
201 /* is the state not enabled? */
202 if (cpuidle_state_table[idle_state].enter == NULL)
203 continue;
204
205 drv->states[drv->state_count] = /* structure copy */
206 cpuidle_state_table[idle_state];
207
208 if (cpuidle_state_table == dedicated_states)
209 drv->states[drv->state_count].target_residency =
210 __get_cpu_var(smt_snooze_delay);
211
212 drv->state_count += 1;
213 }
214
215 return 0;
216}
217
218/* pseries_idle_devices_uninit(void)
219 * unregister cpuidle devices and de-allocate memory
220 */
221static void pseries_idle_devices_uninit(void)
222{
223 int i;
224 struct cpuidle_device *dev;
225
226 for_each_possible_cpu(i) {
227 dev = per_cpu_ptr(pseries_cpuidle_devices, i);
228 cpuidle_unregister_device(dev);
229 }
230
231 free_percpu(pseries_cpuidle_devices);
232 return;
233}
234
235/* pseries_idle_devices_init()
236 * allocate, initialize and register cpuidle device
237 */
238static int pseries_idle_devices_init(void)
239{
240 int i;
241 struct cpuidle_driver *drv = &pseries_idle_driver;
242 struct cpuidle_device *dev;
243
244 pseries_cpuidle_devices = alloc_percpu(struct cpuidle_device);
245 if (pseries_cpuidle_devices == NULL)
246 return -ENOMEM;
247
248 for_each_possible_cpu(i) {
249 dev = per_cpu_ptr(pseries_cpuidle_devices, i);
250 dev->state_count = drv->state_count;
251 dev->cpu = i;
252 if (cpuidle_register_device(dev)) {
253 printk(KERN_DEBUG \
254 "cpuidle_register_device %d failed!\n", i);
255 return -EIO;
256 }
257 }
258
259 return 0;
260}
261
262/*
263 * pseries_idle_probe()
264 * Choose state table for shared versus dedicated partition
265 */
266static int pseries_idle_probe(void)
267{
268
269 if (!firmware_has_feature(FW_FEATURE_SPLPAR))
270 return -ENODEV;
271
272 if (cpuidle_disable != IDLE_NO_OVERRIDE)
273 return -ENODEV;
274
275 if (max_idle_state == 0) {
276 printk(KERN_DEBUG "pseries processor idle disabled.\n");
277 return -EPERM;
278 }
279
280 if (get_lppaca()->shared_proc)
281 cpuidle_state_table = shared_states;
282 else
283 cpuidle_state_table = dedicated_states;
284
285 return 0;
286}
287
288static int __init pseries_processor_idle_init(void)
289{
290 int retval;
291
292 retval = pseries_idle_probe();
293 if (retval)
294 return retval;
295
296 pseries_cpuidle_driver_init();
297 retval = cpuidle_register_driver(&pseries_idle_driver);
298 if (retval) {
299 printk(KERN_DEBUG "Registration of pseries driver failed.\n");
300 return retval;
301 }
302
303 retval = pseries_idle_devices_init();
304 if (retval) {
305 pseries_idle_devices_uninit();
306 cpuidle_unregister_driver(&pseries_idle_driver);
307 return retval;
308 }
309
310 printk(KERN_DEBUG "pseries_idle_driver registered\n");
311
312 return 0;
313}
314
315static void __exit pseries_processor_idle_exit(void)
316{
317
318 pseries_idle_devices_uninit();
319 cpuidle_unregister_driver(&pseries_idle_driver);
320
321 return;
322}
323
324module_init(pseries_processor_idle_init);
325module_exit(pseries_processor_idle_exit);
326
327MODULE_AUTHOR("Deepthi Dharwar <deepthi@linux.vnet.ibm.com>");
328MODULE_DESCRIPTION("Cpuidle driver for POWER");
329MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 24c7162f11d..9a3dda07566 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -57,4 +57,7 @@ extern struct device_node *dlpar_configure_connector(u32);
57extern int dlpar_attach_node(struct device_node *); 57extern int dlpar_attach_node(struct device_node *);
58extern int dlpar_detach_node(struct device_node *); 58extern int dlpar_detach_node(struct device_node *);
59 59
60/* Snooze Delay, pseries_idle */
61DECLARE_PER_CPU(long, smt_snooze_delay);
62
60#endif /* _PSERIES_PSERIES_H */ 63#endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index c3408ca8855..f79f1278dfc 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -39,6 +39,7 @@
39#include <linux/irq.h> 39#include <linux/irq.h>
40#include <linux/seq_file.h> 40#include <linux/seq_file.h>
41#include <linux/root_dev.h> 41#include <linux/root_dev.h>
42#include <linux/cpuidle.h>
42 43
43#include <asm/mmu.h> 44#include <asm/mmu.h>
44#include <asm/processor.h> 45#include <asm/processor.h>
@@ -74,9 +75,6 @@ EXPORT_SYMBOL(CMO_PageSize);
74 75
75int fwnmi_active; /* TRUE if an FWNMI handler is present */ 76int fwnmi_active; /* TRUE if an FWNMI handler is present */
76 77
77static void pseries_shared_idle_sleep(void);
78static void pseries_dedicated_idle_sleep(void);
79
80static struct device_node *pSeries_mpic_node; 78static struct device_node *pSeries_mpic_node;
81 79
82static void pSeries_show_cpuinfo(struct seq_file *m) 80static void pSeries_show_cpuinfo(struct seq_file *m)
@@ -192,8 +190,7 @@ static void __init pseries_mpic_init_IRQ(void)
192 BUG_ON(openpic_addr == 0); 190 BUG_ON(openpic_addr == 0);
193 191
194 /* Setup the openpic driver */ 192 /* Setup the openpic driver */
195 mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 193 mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 0,
196 MPIC_PRIMARY,
197 16, 250, /* isu size, irq count */ 194 16, 250, /* isu size, irq count */
198 " MPIC "); 195 " MPIC ");
199 BUG_ON(mpic == NULL); 196 BUG_ON(mpic == NULL);
@@ -352,8 +349,25 @@ static int alloc_dispatch_log_kmem_cache(void)
352} 349}
353early_initcall(alloc_dispatch_log_kmem_cache); 350early_initcall(alloc_dispatch_log_kmem_cache);
354 351
352static void pSeries_idle(void)
353{
354 /* This would call on the cpuidle framework, and the back-end pseries
355 * driver to go to idle states
356 */
357 if (cpuidle_idle_call()) {
358 /* On error, execute default handler
359 * to go into low thread priority and possibly
360 * low power mode.
361 */
362 HMT_low();
363 HMT_very_low();
364 }
365}
366
355static void __init pSeries_setup_arch(void) 367static void __init pSeries_setup_arch(void)
356{ 368{
369 panic_timeout = 10;
370
357 /* Discover PIC type and setup ppc_md accordingly */ 371 /* Discover PIC type and setup ppc_md accordingly */
358 pseries_discover_pic(); 372 pseries_discover_pic();
359 373
@@ -374,18 +388,9 @@ static void __init pSeries_setup_arch(void)
374 388
375 pSeries_nvram_init(); 389 pSeries_nvram_init();
376 390
377 /* Choose an idle loop */
378 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 391 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
379 vpa_init(boot_cpuid); 392 vpa_init(boot_cpuid);
380 if (get_lppaca()->shared_proc) { 393 ppc_md.power_save = pSeries_idle;
381 printk(KERN_DEBUG "Using shared processor idle loop\n");
382 ppc_md.power_save = pseries_shared_idle_sleep;
383 } else {
384 printk(KERN_DEBUG "Using dedicated idle loop\n");
385 ppc_md.power_save = pseries_dedicated_idle_sleep;
386 }
387 } else {
388 printk(KERN_DEBUG "Using default idle loop\n");
389 } 394 }
390 395
391 if (firmware_has_feature(FW_FEATURE_LPAR)) 396 if (firmware_has_feature(FW_FEATURE_LPAR))
@@ -586,80 +591,6 @@ static int __init pSeries_probe(void)
586 return 1; 591 return 1;
587} 592}
588 593
589
590DECLARE_PER_CPU(long, smt_snooze_delay);
591
592static void pseries_dedicated_idle_sleep(void)
593{
594 unsigned int cpu = smp_processor_id();
595 unsigned long start_snooze;
596 unsigned long in_purr, out_purr;
597 long snooze = __get_cpu_var(smt_snooze_delay);
598
599 /*
600 * Indicate to the HV that we are idle. Now would be
601 * a good time to find other work to dispatch.
602 */
603 get_lppaca()->idle = 1;
604 get_lppaca()->donate_dedicated_cpu = 1;
605 in_purr = mfspr(SPRN_PURR);
606
607 /*
608 * We come in with interrupts disabled, and need_resched()
609 * has been checked recently. If we should poll for a little
610 * while, do so.
611 */
612 if (snooze) {
613 start_snooze = get_tb() + snooze * tb_ticks_per_usec;
614 local_irq_enable();
615 set_thread_flag(TIF_POLLING_NRFLAG);
616
617 while ((snooze < 0) || (get_tb() < start_snooze)) {
618 if (need_resched() || cpu_is_offline(cpu))
619 goto out;
620 ppc64_runlatch_off();
621 HMT_low();
622 HMT_very_low();
623 }
624
625 HMT_medium();
626 clear_thread_flag(TIF_POLLING_NRFLAG);
627 smp_mb();
628 local_irq_disable();
629 if (need_resched() || cpu_is_offline(cpu))
630 goto out;
631 }
632
633 cede_processor();
634
635out:
636 HMT_medium();
637 out_purr = mfspr(SPRN_PURR);
638 get_lppaca()->wait_state_cycles += out_purr - in_purr;
639 get_lppaca()->donate_dedicated_cpu = 0;
640 get_lppaca()->idle = 0;
641}
642
643static void pseries_shared_idle_sleep(void)
644{
645 /*
646 * Indicate to the HV that we are idle. Now would be
647 * a good time to find other work to dispatch.
648 */
649 get_lppaca()->idle = 1;
650
651 /*
652 * Yield the processor to the hypervisor. We return if
653 * an external interrupt occurs (which are driven prior
654 * to returning here) or if a prod occurs from another
655 * processor. When returning here, external interrupts
656 * are enabled.
657 */
658 cede_processor();
659
660 get_lppaca()->idle = 0;
661}
662
663static int pSeries_pci_probe_mode(struct pci_bus *bus) 594static int pSeries_pci_probe_mode(struct pci_bus *bus)
664{ 595{
665 if (firmware_has_feature(FW_FEATURE_LPAR)) 596 if (firmware_has_feature(FW_FEATURE_LPAR))
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 26e93fd4c62..bbc3c42f673 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -148,6 +148,7 @@ static void __devinit smp_xics_setup_cpu(int cpu)
148 set_cpu_current_state(cpu, CPU_STATE_ONLINE); 148 set_cpu_current_state(cpu, CPU_STATE_ONLINE);
149 set_default_offline_state(cpu); 149 set_default_offline_state(cpu);
150#endif 150#endif
151 pseries_notify_cpuidle_add_cpu(cpu);
151} 152}
152 153
153static int __devinit smp_pSeries_kick_cpu(int nr) 154static int __devinit smp_pSeries_kick_cpu(int nr)
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index bd560c786ed..57d22a2f4ba 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,20 +1,28 @@
1config PPC_WSP 1config PPC_WSP
2 bool 2 bool
3 select PPC_A2 3 select PPC_A2
4 select GENERIC_TBSYNC
5 select PPC_ICSWX
4 select PPC_SCOM 6 select PPC_SCOM
5 select PPC_XICS 7 select PPC_XICS
6 select PPC_ICP_NATIVE 8 select PPC_ICP_NATIVE
7 select PCI 9 select PCI
8 select PPC_IO_WORKAROUNDS if PCI 10 select PPC_IO_WORKAROUNDS if PCI
9 select PPC_INDIRECT_PIO if PCI 11 select PPC_INDIRECT_PIO if PCI
12 select PPC_WSP_COPRO
10 default n 13 default n
11 14
12menu "WSP platform selection" 15menu "WSP platform selection"
13 depends on PPC_BOOK3E_64 16 depends on PPC_BOOK3E_64
14 17
15config PPC_PSR2 18config PPC_PSR2
16 bool "PSR-2 platform" 19 bool "PowerEN System Reference Platform 2"
17 select GENERIC_TBSYNC 20 select EPAPR_BOOT
21 select PPC_WSP
22 default y
23
24config PPC_CHROMA
25 bool "PowerEN PCIe Chroma Card"
18 select EPAPR_BOOT 26 select EPAPR_BOOT
19 select PPC_WSP 27 select PPC_WSP
20 default y 28 default y
diff --git a/arch/powerpc/platforms/wsp/Makefile b/arch/powerpc/platforms/wsp/Makefile
index a1486b436f0..56817ac98fc 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -1,8 +1,10 @@
1ccflags-y += -mno-minimal-toc 1ccflags-y += -mno-minimal-toc
2 2
3obj-y += setup.o ics.o 3obj-y += setup.o ics.o wsp.o
4obj-$(CONFIG_PPC_PSR2) += psr2.o opb_pic.o 4obj-$(CONFIG_PPC_PSR2) += psr2.o
5obj-$(CONFIG_PPC_CHROMA) += chroma.o h8.o
6obj-$(CONFIG_PPC_WSP) += opb_pic.o
5obj-$(CONFIG_PPC_WSP) += scom_wsp.o 7obj-$(CONFIG_PPC_WSP) += scom_wsp.o
6obj-$(CONFIG_SMP) += smp.o scom_smp.o 8obj-$(CONFIG_SMP) += smp.o scom_smp.o
7obj-$(CONFIG_PCI) += wsp_pci.o 9obj-$(CONFIG_PCI) += wsp_pci.o
8obj-$(CONFIG_PCI_MSI) += msi.o \ No newline at end of file 10obj-$(CONFIG_PCI_MSI) += msi.o
diff --git a/arch/powerpc/platforms/wsp/chroma.c b/arch/powerpc/platforms/wsp/chroma.c
new file mode 100644
index 00000000000..ca6fa26f6e6
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/chroma.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright 2008-2011, IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/mm.h>
15#include <linux/of.h>
16#include <linux/smp.h>
17#include <linux/time.h>
18
19#include <asm/machdep.h>
20#include <asm/system.h>
21#include <asm/udbg.h>
22
23#include "ics.h"
24#include "wsp.h"
25
26void __init chroma_setup_arch(void)
27{
28 wsp_setup_arch();
29 wsp_setup_h8();
30
31}
32
33static int __init chroma_probe(void)
34{
35 unsigned long root = of_get_flat_dt_root();
36
37 if (!of_flat_dt_is_compatible(root, "ibm,wsp-chroma"))
38 return 0;
39
40 return 1;
41}
42
43define_machine(chroma_md) {
44 .name = "Chroma PCIe",
45 .probe = chroma_probe,
46 .setup_arch = chroma_setup_arch,
47 .restart = wsp_h8_restart,
48 .power_off = wsp_h8_power_off,
49 .halt = wsp_halt,
50 .calibrate_decr = generic_calibrate_decr,
51 .init_IRQ = wsp_setup_irq,
52 .progress = udbg_progress,
53 .power_save = book3e_idle,
54};
55
56machine_arch_initcall(chroma_md, wsp_probe_devices);
diff --git a/arch/powerpc/platforms/wsp/h8.c b/arch/powerpc/platforms/wsp/h8.c
new file mode 100644
index 00000000000..d18e6cc19df
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/h8.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2008-2011, IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/kernel.h>
11#include <linux/of.h>
12#include <linux/io.h>
13
14#include "wsp.h"
15
16/*
17 * The UART connection to the H8 is over ttyS1 which is just a 16550.
18 * We assume that FW has it setup right and no one messes with it.
19 */
20
21
22static u8 __iomem *h8;
23
24#define RBR 0 /* Receiver Buffer Register */
25#define THR 0 /* Transmitter Holding Register */
26#define LSR 5 /* Line Status Register */
27#define LSR_DR 0x01 /* LSR value for Data-Ready */
28#define LSR_THRE 0x20 /* LSR value for Transmitter-Holding-Register-Empty */
29static void wsp_h8_putc(int c)
30{
31 u8 lsr;
32
33 do {
34 lsr = readb(h8 + LSR);
35 } while ((lsr & LSR_THRE) != LSR_THRE);
36 writeb(c, h8 + THR);
37}
38
39static int wsp_h8_getc(void)
40{
41 u8 lsr;
42
43 do {
44 lsr = readb(h8 + LSR);
45 } while ((lsr & LSR_DR) != LSR_DR);
46
47 return readb(h8 + RBR);
48}
49
50static void wsp_h8_puts(const char *s, int sz)
51{
52 int i;
53
54 for (i = 0; i < sz; i++) {
55 wsp_h8_putc(s[i]);
56
57 /* no flow control so wait for echo */
58 wsp_h8_getc();
59 }
60 wsp_h8_putc('\r');
61 wsp_h8_putc('\n');
62}
63
64static void wsp_h8_terminal_cmd(const char *cmd, int sz)
65{
66 hard_irq_disable();
67 wsp_h8_puts(cmd, sz);
68 /* should never return, but just in case */
69 for (;;)
70 continue;
71}
72
73
74void wsp_h8_restart(char *cmd)
75{
76 static const char restart[] = "warm-reset";
77
78 (void)cmd;
79 wsp_h8_terminal_cmd(restart, sizeof(restart) - 1);
80}
81
82void wsp_h8_power_off(void)
83{
84 static const char off[] = "power-off";
85
86 wsp_h8_terminal_cmd(off, sizeof(off) - 1);
87}
88
89static void __iomem *wsp_h8_getaddr(void)
90{
91 struct device_node *aliases;
92 struct device_node *uart;
93 struct property *path;
94 void __iomem *va = NULL;
95
96 /*
97 * there is nothing in the devtree to tell us which is mapped
98 * to the H8, but se know it is the second serial port.
99 */
100
101 aliases = of_find_node_by_path("/aliases");
102 if (aliases == NULL)
103 return NULL;
104
105 path = of_find_property(aliases, "serial1", NULL);
106 if (path == NULL)
107 goto out;
108
109 uart = of_find_node_by_path(path->value);
110 if (uart == NULL)
111 goto out;
112
113 va = of_iomap(uart, 0);
114
115 /* remove it so no one messes with it */
116 of_detach_node(uart);
117 of_node_put(uart);
118
119out:
120 of_node_put(aliases);
121
122 return va;
123}
124
125void __init wsp_setup_h8(void)
126{
127 h8 = wsp_h8_getaddr();
128
129 /* Devtree change? lets hard map it anyway */
130 if (h8 == NULL) {
131 pr_warn("UART to H8 could not be found");
132 h8 = ioremap(0xffc0008000ULL, 0x100);
133 }
134}
diff --git a/arch/powerpc/platforms/wsp/opb_pic.c b/arch/powerpc/platforms/wsp/opb_pic.c
index be05631a3c1..19f353dfcd0 100644
--- a/arch/powerpc/platforms/wsp/opb_pic.c
+++ b/arch/powerpc/platforms/wsp/opb_pic.c
@@ -320,7 +320,8 @@ void __init opb_pic_init(void)
320 } 320 }
321 321
322 /* Attach opb interrupt handler to new virtual IRQ */ 322 /* Attach opb interrupt handler to new virtual IRQ */
323 rc = request_irq(virq, opb_irq_handler, 0, "OPB LS Cascade", opb); 323 rc = request_irq(virq, opb_irq_handler, IRQF_NO_THREAD,
324 "OPB LS Cascade", opb);
324 if (rc) { 325 if (rc) {
325 printk("opb: request_irq failed: %d\n", rc); 326 printk("opb: request_irq failed: %d\n", rc);
326 continue; 327 continue;
diff --git a/arch/powerpc/platforms/wsp/psr2.c b/arch/powerpc/platforms/wsp/psr2.c
index 166f2e4b4be..0c1ae06d0be 100644
--- a/arch/powerpc/platforms/wsp/psr2.c
+++ b/arch/powerpc/platforms/wsp/psr2.c
@@ -14,10 +14,10 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/smp.h> 16#include <linux/smp.h>
17#include <linux/time.h>
17 18
18#include <asm/machdep.h> 19#include <asm/machdep.h>
19#include <asm/system.h> 20#include <asm/system.h>
20#include <asm/time.h>
21#include <asm/udbg.h> 21#include <asm/udbg.h>
22 22
23#include "ics.h" 23#include "ics.h"
@@ -27,7 +27,8 @@
27static void psr2_spin(void) 27static void psr2_spin(void)
28{ 28{
29 hard_irq_disable(); 29 hard_irq_disable();
30 for (;;) ; 30 for (;;)
31 continue;
31} 32}
32 33
33static void psr2_restart(char *cmd) 34static void psr2_restart(char *cmd)
@@ -35,65 +36,32 @@ static void psr2_restart(char *cmd)
35 psr2_spin(); 36 psr2_spin();
36} 37}
37 38
38static int psr2_probe_devices(void)
39{
40 struct device_node *np;
41
42 /* Our RTC is a ds1500. It seems to be programatically compatible
43 * with the ds1511 for which we have a driver so let's use that
44 */
45 np = of_find_compatible_node(NULL, NULL, "dallas,ds1500");
46 if (np != NULL) {
47 struct resource res;
48 if (of_address_to_resource(np, 0, &res) == 0)
49 platform_device_register_simple("ds1511", 0, &res, 1);
50 }
51 return 0;
52}
53machine_arch_initcall(psr2_md, psr2_probe_devices);
54
55static void __init psr2_setup_arch(void)
56{
57 /* init to some ~sane value until calibrate_delay() runs */
58 loops_per_jiffy = 50000000;
59
60 scom_init_wsp();
61
62 /* Setup SMP callback */
63#ifdef CONFIG_SMP
64 a2_setup_smp();
65#endif
66#ifdef CONFIG_PCI
67 wsp_setup_pci();
68#endif
69
70}
71
72static int __init psr2_probe(void) 39static int __init psr2_probe(void)
73{ 40{
74 unsigned long root = of_get_flat_dt_root(); 41 unsigned long root = of_get_flat_dt_root();
75 42
43 if (of_flat_dt_is_compatible(root, "ibm,wsp-chroma")) {
44 /* chroma systems also claim they are psr2s */
45 return 0;
46 }
47
76 if (!of_flat_dt_is_compatible(root, "ibm,psr2")) 48 if (!of_flat_dt_is_compatible(root, "ibm,psr2"))
77 return 0; 49 return 0;
78 50
79 return 1; 51 return 1;
80} 52}
81 53
82static void __init psr2_init_irq(void)
83{
84 wsp_init_irq();
85 opb_pic_init();
86}
87
88define_machine(psr2_md) { 54define_machine(psr2_md) {
89 .name = "PSR2 A2", 55 .name = "PSR2 A2",
90 .probe = psr2_probe, 56 .probe = psr2_probe,
91 .setup_arch = psr2_setup_arch, 57 .setup_arch = wsp_setup_arch,
92 .restart = psr2_restart, 58 .restart = psr2_restart,
93 .power_off = psr2_spin, 59 .power_off = psr2_spin,
94 .halt = psr2_spin, 60 .halt = psr2_spin,
95 .calibrate_decr = generic_calibrate_decr, 61 .calibrate_decr = generic_calibrate_decr,
96 .init_IRQ = psr2_init_irq, 62 .init_IRQ = wsp_setup_irq,
97 .progress = udbg_progress, 63 .progress = udbg_progress,
98 .power_save = book3e_idle, 64 .power_save = book3e_idle,
99}; 65};
66
67machine_arch_initcall(psr2_md, wsp_probe_devices);
diff --git a/arch/powerpc/platforms/wsp/wsp.c b/arch/powerpc/platforms/wsp/wsp.c
new file mode 100644
index 00000000000..d25cc96c21b
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/wsp.c
@@ -0,0 +1,115 @@
1/*
2 * Copyright 2008-2011, IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/kernel.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/smp.h>
14#include <linux/delay.h>
15#include <linux/time.h>
16
17#include <asm/scom.h>
18
19#include "wsp.h"
20#include "ics.h"
21
22#define WSP_SOC_COMPATIBLE "ibm,wsp-soc"
23#define PBIC_COMPATIBLE "ibm,wsp-pbic"
24#define COPRO_COMPATIBLE "ibm,wsp-coprocessor"
25
26static int __init wsp_probe_buses(void)
27{
28 static __initdata struct of_device_id bus_ids[] = {
29 /*
30 * every node in between needs to be here or you won't
31 * find it
32 */
33 { .compatible = WSP_SOC_COMPATIBLE, },
34 { .compatible = PBIC_COMPATIBLE, },
35 { .compatible = COPRO_COMPATIBLE, },
36 {},
37 };
38 of_platform_bus_probe(NULL, bus_ids, NULL);
39
40 return 0;
41}
42
43void __init wsp_setup_arch(void)
44{
45 /* init to some ~sane value until calibrate_delay() runs */
46 loops_per_jiffy = 50000000;
47
48 scom_init_wsp();
49
50 /* Setup SMP callback */
51#ifdef CONFIG_SMP
52 a2_setup_smp();
53#endif
54#ifdef CONFIG_PCI
55 wsp_setup_pci();
56#endif
57}
58
59void __init wsp_setup_irq(void)
60{
61 wsp_init_irq();
62 opb_pic_init();
63}
64
65
66int __init wsp_probe_devices(void)
67{
68 struct device_node *np;
69
70 /* Our RTC is a ds1500. It seems to be programatically compatible
71 * with the ds1511 for which we have a driver so let's use that
72 */
73 np = of_find_compatible_node(NULL, NULL, "dallas,ds1500");
74 if (np != NULL) {
75 struct resource res;
76 if (of_address_to_resource(np, 0, &res) == 0)
77 platform_device_register_simple("ds1511", 0, &res, 1);
78 }
79
80 wsp_probe_buses();
81
82 return 0;
83}
84
85void wsp_halt(void)
86{
87 u64 val;
88 scom_map_t m;
89 struct device_node *dn;
90 struct device_node *mine;
91 struct device_node *me;
92
93 me = of_get_cpu_node(smp_processor_id(), NULL);
94 mine = scom_find_parent(me);
95
96 /* This will halt all the A2s but not power off the chip */
97 for_each_node_with_property(dn, "scom-controller") {
98 if (dn == mine)
99 continue;
100 m = scom_map(dn, 0, 1);
101
102 /* read-modify-write it so the HW probe does not get
103 * confused */
104 val = scom_read(m, 0);
105 val |= 1;
106 scom_write(m, 0, val);
107 scom_unmap(m);
108 }
109 m = scom_map(mine, 0, 1);
110 val = scom_read(m, 0);
111 val |= 1;
112 scom_write(m, 0, val);
113 /* should never return */
114 scom_unmap(m);
115}
diff --git a/arch/powerpc/platforms/wsp/wsp.h b/arch/powerpc/platforms/wsp/wsp.h
index 33479818f62..10c1d1fff36 100644
--- a/arch/powerpc/platforms/wsp/wsp.h
+++ b/arch/powerpc/platforms/wsp/wsp.h
@@ -6,15 +6,25 @@
6/* Devtree compatible strings for major devices */ 6/* Devtree compatible strings for major devices */
7#define PCIE_COMPATIBLE "ibm,wsp-pciex" 7#define PCIE_COMPATIBLE "ibm,wsp-pciex"
8 8
9extern void wsp_setup_arch(void);
10extern void wsp_setup_irq(void);
11extern int wsp_probe_devices(void);
12extern void wsp_halt(void);
13
9extern void wsp_setup_pci(void); 14extern void wsp_setup_pci(void);
10extern void scom_init_wsp(void); 15extern void scom_init_wsp(void);
11 16
12extern void a2_setup_smp(void); 17extern void a2_setup_smp(void);
13extern int a2_scom_startup_cpu(unsigned int lcpu, int thr_idx, 18extern int a2_scom_startup_cpu(unsigned int lcpu, int thr_idx,
14 struct device_node *np); 19 struct device_node *np);
15int smp_a2_cpu_bootable(unsigned int nr); 20extern int smp_a2_cpu_bootable(unsigned int nr);
16int __devinit smp_a2_kick_cpu(int nr); 21extern int __devinit smp_a2_kick_cpu(int nr);
22
23extern void opb_pic_init(void);
17 24
18void opb_pic_init(void); 25/* chroma specific managment */
26extern void wsp_h8_restart(char *cmd);
27extern void wsp_h8_power_off(void);
28extern void __init wsp_setup_h8(void);
19 29
20#endif /* __WSP_H */ 30#endif /* __WSP_H */
diff --git a/arch/powerpc/relocs_check.pl b/arch/powerpc/relocs_check.pl
index d2571096c3e..7f5b8380886 100755
--- a/arch/powerpc/relocs_check.pl
+++ b/arch/powerpc/relocs_check.pl
@@ -32,8 +32,18 @@ while (<FD>) {
32 next if (!/\s+R_/); 32 next if (!/\s+R_/);
33 33
34 # These relocations are okay 34 # These relocations are okay
35 next if (/R_PPC64_RELATIVE/ or /R_PPC64_NONE/ or 35 # On PPC64:
36 /R_PPC64_ADDR64\s+mach_/); 36 # R_PPC64_RELATIVE, R_PPC64_NONE, R_PPC64_ADDR64
37 # On PPC:
38 # R_PPC_RELATIVE, R_PPC_ADDR16_HI,
39 # R_PPC_ADDR16_HA,R_PPC_ADDR16_LO,
40 # R_PPC_NONE
41
42 next if (/\bR_PPC64_RELATIVE\b/ or /\bR_PPC64_NONE\b/ or
43 /\bR_PPC64_ADDR64\s+mach_/);
44 next if (/\bR_PPC_ADDR16_LO\b/ or /\bR_PPC_ADDR16_HI\b/ or
45 /\bR_PPC_ADDR16_HA\b/ or /\bR_PPC_RELATIVE\b/ or
46 /\bR_PPC_NONE\b/);
37 47
38 # If we see this type of relcoation it's an idication that 48 # If we see this type of relcoation it's an idication that
39 # we /may/ be using an old version of binutils. 49 # we /may/ be using an old version of binutils.
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 84e13253aec..5e37b471786 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,10 +17,11 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
17obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) 17obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
18obj-$(CONFIG_FSL_PMC) += fsl_pmc.o 18obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
19obj-$(CONFIG_FSL_LBC) += fsl_lbc.o 19obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
20obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
20obj-$(CONFIG_FSL_GTM) += fsl_gtm.o 21obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o 22obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o 23obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
23obj-$(CONFIG_FSL_RIO) += fsl_rio.o 24obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 25obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
25obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 26obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
26obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ 27obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
new file mode 100644
index 00000000000..b31f19f6103
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -0,0 +1,310 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc
3 *
4 * Freescale Integrated Flash Controller
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/compiler.h>
26#include <linux/spinlock.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/io.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/platform_device.h>
33#include <asm/prom.h>
34#include <asm/fsl_ifc.h>
35
36struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
37EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
38
39/*
40 * convert_ifc_address - convert the base address
41 * @addr_base: base address of the memory bank
42 */
43unsigned int convert_ifc_address(phys_addr_t addr_base)
44{
45 return addr_base & CSPR_BA;
46}
47EXPORT_SYMBOL(convert_ifc_address);
48
49/*
50 * fsl_ifc_find - find IFC bank
51 * @addr_base: base address of the memory bank
52 *
53 * This function walks IFC banks comparing "Base address" field of the CSPR
54 * registers with the supplied addr_base argument. When bases match this
55 * function returns bank number (starting with 0), otherwise it returns
56 * appropriate errno value.
57 */
58int fsl_ifc_find(phys_addr_t addr_base)
59{
60 int i = 0;
61
62 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
63 return -ENODEV;
64
65 for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
66 __be32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
67 if (cspr & CSPR_V && (cspr & CSPR_BA) ==
68 convert_ifc_address(addr_base))
69 return i;
70 }
71
72 return -ENOENT;
73}
74EXPORT_SYMBOL(fsl_ifc_find);
75
76static int __devinit fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
77{
78 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
79
80 /*
81 * Clear all the common status and event registers
82 */
83 if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
84 out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
85
86 /* enable all error and events */
87 out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
88
89 /* enable all error and event interrupts */
90 out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
91 out_be32(&ifc->cm_erattr0, 0x0);
92 out_be32(&ifc->cm_erattr1, 0x0);
93
94 return 0;
95}
96
97static int fsl_ifc_ctrl_remove(struct platform_device *dev)
98{
99 struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
100
101 free_irq(ctrl->nand_irq, ctrl);
102 free_irq(ctrl->irq, ctrl);
103
104 irq_dispose_mapping(ctrl->nand_irq);
105 irq_dispose_mapping(ctrl->irq);
106
107 iounmap(ctrl->regs);
108
109 dev_set_drvdata(&dev->dev, NULL);
110 kfree(ctrl);
111
112 return 0;
113}
114
115/*
116 * NAND events are split between an operational interrupt which only
117 * receives OPC, and an error interrupt that receives everything else,
118 * including non-NAND errors. Whichever interrupt gets to it first
119 * records the status and wakes the wait queue.
120 */
121static DEFINE_SPINLOCK(nand_irq_lock);
122
123static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
124{
125 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
126 unsigned long flags;
127 u32 stat;
128
129 spin_lock_irqsave(&nand_irq_lock, flags);
130
131 stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
132 if (stat) {
133 out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
134 ctrl->nand_stat = stat;
135 wake_up(&ctrl->nand_wait);
136 }
137
138 spin_unlock_irqrestore(&nand_irq_lock, flags);
139
140 return stat;
141}
142
143static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
144{
145 struct fsl_ifc_ctrl *ctrl = data;
146
147 if (check_nand_stat(ctrl))
148 return IRQ_HANDLED;
149
150 return IRQ_NONE;
151}
152
153/*
154 * NOTE: This interrupt is used to report ifc events of various kinds,
155 * such as transaction errors on the chipselects.
156 */
157static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
158{
159 struct fsl_ifc_ctrl *ctrl = data;
160 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
161 u32 err_axiid, err_srcid, status, cs_err, err_addr;
162 irqreturn_t ret = IRQ_NONE;
163
164 /* read for chip select error */
165 cs_err = in_be32(&ifc->cm_evter_stat);
166 if (cs_err) {
167 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
168 "any memory bank 0x%08X\n", cs_err);
169 /* clear the chip select error */
170 out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
171
172 /* read error attribute registers print the error information */
173 status = in_be32(&ifc->cm_erattr0);
174 err_addr = in_be32(&ifc->cm_erattr1);
175
176 if (status & IFC_CM_ERATTR0_ERTYP_READ)
177 dev_err(ctrl->dev, "Read transaction error"
178 "CM_ERATTR0 0x%08X\n", status);
179 else
180 dev_err(ctrl->dev, "Write transaction error"
181 "CM_ERATTR0 0x%08X\n", status);
182
183 err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
184 IFC_CM_ERATTR0_ERAID_SHIFT;
185 dev_err(ctrl->dev, "AXI ID of the error"
186 "transaction 0x%08X\n", err_axiid);
187
188 err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
189 IFC_CM_ERATTR0_ESRCID_SHIFT;
190 dev_err(ctrl->dev, "SRC ID of the error"
191 "transaction 0x%08X\n", err_srcid);
192
193 dev_err(ctrl->dev, "Transaction Address corresponding to error"
194 "ERADDR 0x%08X\n", err_addr);
195
196 ret = IRQ_HANDLED;
197 }
198
199 if (check_nand_stat(ctrl))
200 ret = IRQ_HANDLED;
201
202 return ret;
203}
204
205/*
206 * fsl_ifc_ctrl_probe
207 *
208 * called by device layer when it finds a device matching
209 * one our driver can handled. This code allocates all of
210 * the resources needed for the controller only. The
211 * resources for the NAND banks themselves are allocated
212 * in the chip probe function.
213*/
214static int __devinit fsl_ifc_ctrl_probe(struct platform_device *dev)
215{
216 int ret = 0;
217
218
219 dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
220
221 fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
222 if (!fsl_ifc_ctrl_dev)
223 return -ENOMEM;
224
225 dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
226
227 /* IOMAP the entire IFC region */
228 fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
229 if (!fsl_ifc_ctrl_dev->regs) {
230 dev_err(&dev->dev, "failed to get memory region\n");
231 ret = -ENODEV;
232 goto err;
233 }
234
235 /* get the Controller level irq */
236 fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
237 if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
238 dev_err(&dev->dev, "failed to get irq resource "
239 "for IFC\n");
240 ret = -ENODEV;
241 goto err;
242 }
243
244 /* get the nand machine irq */
245 fsl_ifc_ctrl_dev->nand_irq =
246 irq_of_parse_and_map(dev->dev.of_node, 1);
247 if (fsl_ifc_ctrl_dev->nand_irq == NO_IRQ) {
248 dev_err(&dev->dev, "failed to get irq resource "
249 "for NAND Machine\n");
250 ret = -ENODEV;
251 goto err;
252 }
253
254 fsl_ifc_ctrl_dev->dev = &dev->dev;
255
256 ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
257 if (ret < 0)
258 goto err;
259
260 init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
261
262 ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
263 "fsl-ifc", fsl_ifc_ctrl_dev);
264 if (ret != 0) {
265 dev_err(&dev->dev, "failed to install irq (%d)\n",
266 fsl_ifc_ctrl_dev->irq);
267 goto err_irq;
268 }
269
270 ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq, 0,
271 "fsl-ifc-nand", fsl_ifc_ctrl_dev);
272 if (ret != 0) {
273 dev_err(&dev->dev, "failed to install irq (%d)\n",
274 fsl_ifc_ctrl_dev->nand_irq);
275 goto err_nandirq;
276 }
277
278 return 0;
279
280err_nandirq:
281 free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
282 irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
283err_irq:
284 free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
285 irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
286err:
287 return ret;
288}
289
290static const struct of_device_id fsl_ifc_match[] = {
291 {
292 .compatible = "fsl,ifc",
293 },
294 {},
295};
296
297static struct platform_driver fsl_ifc_ctrl_driver = {
298 .driver = {
299 .name = "fsl-ifc",
300 .of_match_table = fsl_ifc_match,
301 },
302 .probe = fsl_ifc_ctrl_probe,
303 .remove = fsl_ifc_ctrl_remove,
304};
305
306module_platform_driver(fsl_ifc_ctrl_driver);
307
308MODULE_LICENSE("GPL");
309MODULE_AUTHOR("Freescale Semiconductor");
310MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index d5c3c90ee69..483126d7b3c 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -332,6 +332,38 @@ err:
332 return ret; 332 return ret;
333} 333}
334 334
335#ifdef CONFIG_SUSPEND
336
337/* save lbc registers */
338static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
339{
340 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
341 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
342
343 ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
344 if (!ctrl->saved_regs)
345 return -ENOMEM;
346
347 _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
348 return 0;
349}
350
351/* restore lbc registers */
352static int fsl_lbc_resume(struct platform_device *pdev)
353{
354 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
355 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
356
357 if (ctrl->saved_regs) {
358 _memcpy_toio(lbc, ctrl->saved_regs,
359 sizeof(struct fsl_lbc_regs));
360 kfree(ctrl->saved_regs);
361 ctrl->saved_regs = NULL;
362 }
363 return 0;
364}
365#endif /* CONFIG_SUSPEND */
366
335static const struct of_device_id fsl_lbc_match[] = { 367static const struct of_device_id fsl_lbc_match[] = {
336 { .compatible = "fsl,elbc", }, 368 { .compatible = "fsl,elbc", },
337 { .compatible = "fsl,pq3-localbus", }, 369 { .compatible = "fsl,pq3-localbus", },
@@ -346,6 +378,10 @@ static struct platform_driver fsl_lbc_ctrl_driver = {
346 .of_match_table = fsl_lbc_match, 378 .of_match_table = fsl_lbc_match,
347 }, 379 },
348 .probe = fsl_lbc_ctrl_probe, 380 .probe = fsl_lbc_ctrl_probe,
381#ifdef CONFIG_SUSPEND
382 .suspend = fsl_lbc_suspend,
383 .resume = fsl_lbc_resume,
384#endif
349}; 385};
350 386
351static int __init fsl_lbc_init(void) 387static int __init fsl_lbc_init(void)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index e5c344d336e..ecb5c1946d2 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -23,6 +23,8 @@
23#include <asm/hw_irq.h> 23#include <asm/hw_irq.h>
24#include <asm/ppc-pci.h> 24#include <asm/ppc-pci.h>
25#include <asm/mpic.h> 25#include <asm/mpic.h>
26#include <asm/fsl_hcalls.h>
27
26#include "fsl_msi.h" 28#include "fsl_msi.h"
27#include "fsl_pci.h" 29#include "fsl_pci.h"
28 30
@@ -148,14 +150,49 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
148 150
149static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 151static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
150{ 152{
153 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
154 struct device_node *np;
155 phandle phandle = 0;
151 int rc, hwirq = -ENOMEM; 156 int rc, hwirq = -ENOMEM;
152 unsigned int virq; 157 unsigned int virq;
153 struct msi_desc *entry; 158 struct msi_desc *entry;
154 struct msi_msg msg; 159 struct msi_msg msg;
155 struct fsl_msi *msi_data; 160 struct fsl_msi *msi_data;
156 161
162 /*
163 * If the PCI node has an fsl,msi property, then we need to use it
164 * to find the specific MSI.
165 */
166 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
167 if (np) {
168 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
169 of_device_is_compatible(np, "fsl,vmpic-msi"))
170 phandle = np->phandle;
171 else {
172 dev_err(&pdev->dev,
173 "node %s has an invalid fsl,msi phandle %u\n",
174 hose->dn->full_name, np->phandle);
175 return -EINVAL;
176 }
177 }
178
157 list_for_each_entry(entry, &pdev->msi_list, list) { 179 list_for_each_entry(entry, &pdev->msi_list, list) {
180 /*
181 * Loop over all the MSI devices until we find one that has an
182 * available interrupt.
183 */
158 list_for_each_entry(msi_data, &msi_head, list) { 184 list_for_each_entry(msi_data, &msi_head, list) {
185 /*
186 * If the PCI node has an fsl,msi property, then we
187 * restrict our search to the corresponding MSI node.
188 * The simplest way is to skip over MSI nodes with the
189 * wrong phandle. Under the Freescale hypervisor, this
190 * has the additional benefit of skipping over MSI
191 * nodes that are not mapped in the PAMU.
192 */
193 if (phandle && (phandle != msi_data->phandle))
194 continue;
195
159 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); 196 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
160 if (hwirq >= 0) 197 if (hwirq >= 0)
161 break; 198 break;
@@ -163,16 +200,14 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
163 200
164 if (hwirq < 0) { 201 if (hwirq < 0) {
165 rc = hwirq; 202 rc = hwirq;
166 pr_debug("%s: fail allocating msi interrupt\n", 203 dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
167 __func__);
168 goto out_free; 204 goto out_free;
169 } 205 }
170 206
171 virq = irq_create_mapping(msi_data->irqhost, hwirq); 207 virq = irq_create_mapping(msi_data->irqhost, hwirq);
172 208
173 if (virq == NO_IRQ) { 209 if (virq == NO_IRQ) {
174 pr_debug("%s: fail mapping hwirq 0x%x\n", 210 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
175 __func__, hwirq);
176 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); 211 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
177 rc = -ENOSPC; 212 rc = -ENOSPC;
178 goto out_free; 213 goto out_free;
@@ -201,6 +236,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
201 u32 intr_index; 236 u32 intr_index;
202 u32 have_shift = 0; 237 u32 have_shift = 0;
203 struct fsl_msi_cascade_data *cascade_data; 238 struct fsl_msi_cascade_data *cascade_data;
239 unsigned int ret;
204 240
205 cascade_data = irq_get_handler_data(irq); 241 cascade_data = irq_get_handler_data(irq);
206 msi_data = cascade_data->msi_data; 242 msi_data = cascade_data->msi_data;
@@ -232,6 +268,14 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
232 case FSL_PIC_IP_IPIC: 268 case FSL_PIC_IP_IPIC:
233 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); 269 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
234 break; 270 break;
271 case FSL_PIC_IP_VMPIC:
272 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
273 if (ret) {
274 pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
275 "irq %u (ret=%u)\n", irq, ret);
276 msir_value = 0;
277 }
278 break;
235 } 279 }
236 280
237 while (msir_value) { 281 while (msir_value) {
@@ -249,6 +293,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
249 293
250 switch (msi_data->feature & FSL_PIC_IP_MASK) { 294 switch (msi_data->feature & FSL_PIC_IP_MASK) {
251 case FSL_PIC_IP_MPIC: 295 case FSL_PIC_IP_MPIC:
296 case FSL_PIC_IP_VMPIC:
252 chip->irq_eoi(idata); 297 chip->irq_eoi(idata);
253 break; 298 break;
254 case FSL_PIC_IP_IPIC: 299 case FSL_PIC_IP_IPIC:
@@ -278,7 +323,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
278 } 323 }
279 if (msi->bitmap.bitmap) 324 if (msi->bitmap.bitmap)
280 msi_bitmap_free(&msi->bitmap); 325 msi_bitmap_free(&msi->bitmap);
281 iounmap(msi->msi_regs); 326 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
327 iounmap(msi->msi_regs);
282 kfree(msi); 328 kfree(msi);
283 329
284 return 0; 330 return 0;
@@ -350,25 +396,37 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
350 goto error_out; 396 goto error_out;
351 } 397 }
352 398
353 /* Get the MSI reg base */ 399 /*
354 err = of_address_to_resource(dev->dev.of_node, 0, &res); 400 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
355 if (err) { 401 * property. Instead, we use hypercalls to access the MSI.
356 dev_err(&dev->dev, "%s resource error!\n", 402 */
403 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
404 err = of_address_to_resource(dev->dev.of_node, 0, &res);
405 if (err) {
406 dev_err(&dev->dev, "invalid resource for node %s\n",
357 dev->dev.of_node->full_name); 407 dev->dev.of_node->full_name);
358 goto error_out; 408 goto error_out;
359 } 409 }
360 410
361 msi->msi_regs = ioremap(res.start, resource_size(&res)); 411 msi->msi_regs = ioremap(res.start, resource_size(&res));
362 if (!msi->msi_regs) { 412 if (!msi->msi_regs) {
363 dev_err(&dev->dev, "ioremap problem failed\n"); 413 dev_err(&dev->dev, "could not map node %s\n",
364 goto error_out; 414 dev->dev.of_node->full_name);
415 goto error_out;
416 }
417 msi->msiir_offset =
418 features->msiir_offset + (res.start & 0xfffff);
365 } 419 }
366 420
367 msi->feature = features->fsl_pic_ip; 421 msi->feature = features->fsl_pic_ip;
368 422
369 msi->irqhost->host_data = msi; 423 msi->irqhost->host_data = msi;
370 424
371 msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff); 425 /*
426 * Remember the phandle, so that we can match with any PCI nodes
427 * that have an "fsl,msi" property.
428 */
429 msi->phandle = dev->dev.of_node->phandle;
372 430
373 rc = fsl_msi_init_allocator(msi); 431 rc = fsl_msi_init_allocator(msi);
374 if (rc) { 432 if (rc) {
@@ -437,6 +495,11 @@ static const struct fsl_msi_feature ipic_msi_feature = {
437 .msiir_offset = 0x38, 495 .msiir_offset = 0x38,
438}; 496};
439 497
498static const struct fsl_msi_feature vmpic_msi_feature = {
499 .fsl_pic_ip = FSL_PIC_IP_VMPIC,
500 .msiir_offset = 0,
501};
502
440static const struct of_device_id fsl_of_msi_ids[] = { 503static const struct of_device_id fsl_of_msi_ids[] = {
441 { 504 {
442 .compatible = "fsl,mpic-msi", 505 .compatible = "fsl,mpic-msi",
@@ -446,6 +509,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
446 .compatible = "fsl,ipic-msi", 509 .compatible = "fsl,ipic-msi",
447 .data = (void *)&ipic_msi_feature, 510 .data = (void *)&ipic_msi_feature,
448 }, 511 },
512 {
513 .compatible = "fsl,vmpic-msi",
514 .data = (void *)&vmpic_msi_feature,
515 },
449 {} 516 {}
450}; 517};
451 518
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 1313abbc520..f6c646a5254 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -13,15 +13,17 @@
13#ifndef _POWERPC_SYSDEV_FSL_MSI_H 13#ifndef _POWERPC_SYSDEV_FSL_MSI_H
14#define _POWERPC_SYSDEV_FSL_MSI_H 14#define _POWERPC_SYSDEV_FSL_MSI_H
15 15
16#include <linux/of.h>
16#include <asm/msi_bitmap.h> 17#include <asm/msi_bitmap.h>
17 18
18#define NR_MSI_REG 8 19#define NR_MSI_REG 8
19#define IRQS_PER_MSI_REG 32 20#define IRQS_PER_MSI_REG 32
20#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG) 21#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
21 22
22#define FSL_PIC_IP_MASK 0x0000000F 23#define FSL_PIC_IP_MASK 0x0000000F
23#define FSL_PIC_IP_MPIC 0x00000001 24#define FSL_PIC_IP_MPIC 0x00000001
24#define FSL_PIC_IP_IPIC 0x00000002 25#define FSL_PIC_IP_IPIC 0x00000002
26#define FSL_PIC_IP_VMPIC 0x00000003
25 27
26struct fsl_msi { 28struct fsl_msi {
27 struct irq_host *irqhost; 29 struct irq_host *irqhost;
@@ -36,6 +38,8 @@ struct fsl_msi {
36 struct msi_bitmap bitmap; 38 struct msi_bitmap bitmap;
37 39
38 struct list_head list; /* support multiple MSI banks */ 40 struct list_head list; /* support multiple MSI banks */
41
42 phandle phandle;
39}; 43};
40 44
41#endif /* _POWERPC_SYSDEV_FSL_MSI_H */ 45#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ce547e0047..3b61e8cf342 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -65,6 +65,30 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose)
65} 65}
66 66
67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
68
69#define MAX_PHYS_ADDR_BITS 40
70static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
71
72static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
73{
74 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
75 return -EIO;
76
77 /*
78 * Fixup PCI devices that are able to DMA to above the physical
79 * address width of the SoC such that we can address any internal
80 * SoC address from across PCI if needed
81 */
82 if ((dev->bus == &pci_bus_type) &&
83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
84 set_dma_ops(dev, &dma_direct_ops);
85 set_dma_offset(dev, pci64_dma_offset);
86 }
87
88 *dev->dma_mask = dma_mask;
89 return 0;
90}
91
68static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 92static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
69 unsigned int index, const struct resource *res, 93 unsigned int index, const struct resource *res,
70 resource_size_t offset) 94 resource_size_t offset)
@@ -113,6 +137,8 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
113 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
114 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
115 char *name = hose->dn->full_name; 139 char *name = hose->dn->full_name;
140 const u64 *reg;
141 int len;
116 142
117 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
118 (u64)rsrc->start, (u64)resource_size(rsrc)); 144 (u64)rsrc->start, (u64)resource_size(rsrc));
@@ -205,6 +231,33 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
205 231
206 /* Setup inbound mem window */ 232 /* Setup inbound mem window */
207 mem = memblock_end_of_DRAM(); 233 mem = memblock_end_of_DRAM();
234
235 /*
236 * The msi-address-64 property, if it exists, indicates the physical
237 * address of the MSIIR register. Normally, this register is located
238 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
239 * this property exists, then we normally need to create a new ATMU
240 * for it. For now, however, we cheat. The only entity that creates
241 * this property is the Freescale hypervisor, and the address is
242 * specified in the partition configuration. Typically, the address
243 * is located in the page immediately after the end of DDR. If so, we
244 * can avoid allocating a new ATMU by extending the DDR ATMU by one
245 * page.
246 */
247 reg = of_get_property(hose->dn, "msi-address-64", &len);
248 if (reg && (len == sizeof(u64))) {
249 u64 address = be64_to_cpup(reg);
250
251 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
252 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
253 mem += PAGE_SIZE;
254 } else {
255 /* TODO: Create a new ATMU for MSIIR */
256 pr_warn("%s: msi-address-64 address of %llx is "
257 "unsupported\n", name, address);
258 }
259 }
260
208 sz = min(mem, paddr_lo); 261 sz = min(mem, paddr_lo);
209 mem_log = __ilog2_u64(sz); 262 mem_log = __ilog2_u64(sz);
210 263
@@ -228,6 +281,37 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
228 281
229 hose->dma_window_base_cur = 0x00000000; 282 hose->dma_window_base_cur = 0x00000000;
230 hose->dma_window_size = (resource_size_t)sz; 283 hose->dma_window_size = (resource_size_t)sz;
284
285 /*
286 * if we have >4G of memory setup second PCI inbound window to
287 * let devices that are 64-bit address capable to work w/o
288 * SWIOTLB and access the full range of memory
289 */
290 if (sz != mem) {
291 mem_log = __ilog2_u64(mem);
292
293 /* Size window up if we dont fit in exact power-of-2 */
294 if ((1ull << mem_log) != mem)
295 mem_log++;
296
297 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
298
299 /* Setup inbound memory window */
300 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
301 out_be32(&pci->piw[win_idx].piwbear,
302 pci64_dma_offset >> 44);
303 out_be32(&pci->piw[win_idx].piwbar,
304 pci64_dma_offset >> 12);
305 out_be32(&pci->piw[win_idx].piwar, piwar);
306
307 /*
308 * install our own dma_set_mask handler to fixup dma_ops
309 * and dma_offset
310 */
311 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
312
313 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
314 }
231 } else { 315 } else {
232 u64 paddr = 0; 316 u64 paddr = 0;
233 317
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 22ffccd8bef..a4c4f4a932d 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
10 * - Added Port-Write message handling 10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling 11 * - Added Machine Check exception handling
12 * 12 *
13 * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com> 14 * Zhang Wei <wei.zhang@freescale.com>
15 * 15 *
16 * Copyright 2005 MontaVista Software, Inc. 16 * Copyright 2005 MontaVista Software, Inc.
@@ -28,240 +28,33 @@
28#include <linux/dma-mapping.h> 28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/rio.h>
32#include <linux/rio_drv.h>
33#include <linux/of_platform.h> 31#include <linux/of_platform.h>
34#include <linux/delay.h> 32#include <linux/delay.h>
35#include <linux/slab.h> 33#include <linux/slab.h>
36#include <linux/kfifo.h>
37 34
38#include <asm/io.h> 35#include <linux/io.h>
36#include <linux/uaccess.h>
39#include <asm/machdep.h> 37#include <asm/machdep.h>
40#include <asm/uaccess.h>
41 38
42#undef DEBUG_PW /* Port-Write debugging */ 39#include "fsl_rio.h"
43 40
44/* RapidIO definition irq, which read from OF-tree */ 41#undef DEBUG_PW /* Port-Write debugging */
45#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
49
50#define IPWSR_CLEAR 0x98
51#define OMSR_CLEAR 0x1cb3
52#define IMSR_CLEAR 0x491
53#define IDSR_CLEAR 0x91
54#define ODSR_CLEAR 0x1c00
55#define LTLEECSR_ENABLE_ALL 0xFFC000FC
56#define ESCSR_CLEAR 0x07120204
57#define IECSR_CLEAR 0x80000000
58 42
59#define RIO_PORT1_EDCSR 0x0640 43#define RIO_PORT1_EDCSR 0x0640
60#define RIO_PORT2_EDCSR 0x0680 44#define RIO_PORT2_EDCSR 0x0680
61#define RIO_PORT1_IECSR 0x10130 45#define RIO_PORT1_IECSR 0x10130
62#define RIO_PORT2_IECSR 0x101B0 46#define RIO_PORT2_IECSR 0x101B0
63#define RIO_IM0SR 0x13064 47
64#define RIO_IM1SR 0x13164
65#define RIO_OM0SR 0x13004
66#define RIO_OM1SR 0x13104
67
68#define RIO_ATMU_REGS_OFFSET 0x10c00
69#define RIO_P_MSG_REGS_OFFSET 0x11000
70#define RIO_S_MSG_REGS_OFFSET 0x13000
71#define RIO_GCCSR 0x13c 48#define RIO_GCCSR 0x13c
72#define RIO_ESCSR 0x158 49#define RIO_ESCSR 0x158
50#define ESCSR_CLEAR 0x07120204
73#define RIO_PORT2_ESCSR 0x178 51#define RIO_PORT2_ESCSR 0x178
74#define RIO_CCSR 0x15c 52#define RIO_CCSR 0x15c
75#define RIO_LTLEDCSR 0x0608
76#define RIO_LTLEDCSR_IER 0x80000000 53#define RIO_LTLEDCSR_IER 0x80000000
77#define RIO_LTLEDCSR_PRT 0x01000000 54#define RIO_LTLEDCSR_PRT 0x01000000
78#define RIO_LTLEECSR 0x060c 55#define IECSR_CLEAR 0x80000000
79#define RIO_EPWISR 0x10010
80#define RIO_ISR_AACR 0x10120 56#define RIO_ISR_AACR 0x10120
81#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 57#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
82#define RIO_MAINT_WIN_SIZE 0x400000
83#define RIO_DBELL_WIN_SIZE 0x1000
84
85#define RIO_MSG_OMR_MUI 0x00000002
86#define RIO_MSG_OSR_TE 0x00000080
87#define RIO_MSG_OSR_QOI 0x00000020
88#define RIO_MSG_OSR_QFI 0x00000010
89#define RIO_MSG_OSR_MUB 0x00000004
90#define RIO_MSG_OSR_EOMI 0x00000002
91#define RIO_MSG_OSR_QEI 0x00000001
92
93#define RIO_MSG_IMR_MI 0x00000002
94#define RIO_MSG_ISR_TE 0x00000080
95#define RIO_MSG_ISR_QFI 0x00000010
96#define RIO_MSG_ISR_DIQI 0x00000001
97
98#define RIO_IPWMR_SEN 0x00100000
99#define RIO_IPWMR_QFIE 0x00000100
100#define RIO_IPWMR_EIE 0x00000020
101#define RIO_IPWMR_CQ 0x00000002
102#define RIO_IPWMR_PWE 0x00000001
103
104#define RIO_IPWSR_QF 0x00100000
105#define RIO_IPWSR_TE 0x00000080
106#define RIO_IPWSR_QFI 0x00000010
107#define RIO_IPWSR_PWD 0x00000008
108#define RIO_IPWSR_PWB 0x00000004
109
110/* EPWISR Error match value */
111#define RIO_EPWISR_PINT1 0x80000000
112#define RIO_EPWISR_PINT2 0x40000000
113#define RIO_EPWISR_MU 0x00000002
114#define RIO_EPWISR_PW 0x00000001
115
116#define RIO_MSG_DESC_SIZE 32
117#define RIO_MSG_BUFFER_SIZE 4096
118#define RIO_MIN_TX_RING_SIZE 2
119#define RIO_MAX_TX_RING_SIZE 2048
120#define RIO_MIN_RX_RING_SIZE 2
121#define RIO_MAX_RX_RING_SIZE 2048
122
123#define DOORBELL_DMR_DI 0x00000002
124#define DOORBELL_DSR_TE 0x00000080
125#define DOORBELL_DSR_QFI 0x00000010
126#define DOORBELL_DSR_DIQI 0x00000001
127#define DOORBELL_TID_OFFSET 0x02
128#define DOORBELL_SID_OFFSET 0x04
129#define DOORBELL_INFO_OFFSET 0x06
130
131#define DOORBELL_MESSAGE_SIZE 0x08
132#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
133#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
134#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
135
136struct rio_atmu_regs {
137 u32 rowtar;
138 u32 rowtear;
139 u32 rowbar;
140 u32 pad2;
141 u32 rowar;
142 u32 pad3[3];
143};
144
145struct rio_msg_regs {
146 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
147 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
148 u32 pad1;
149 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
150 dequeue pointer address register */
151 u32 pad2;
152 u32 osar; /* 0xD_3014 - Outbound message 0 source address
153 register */
154 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
155 register */
156 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
157 Register*/
158 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
159 register */
160 u32 pad3;
161 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
162 enqueue pointer address register */
163 u32 pad4[13];
164 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
165 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
166 u32 pad5;
167 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
168 pointer address register*/
169 u32 pad6;
170 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
171 pointer address register */
172 u32 pad7[226];
173 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
174 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
175 u32 res0[4];
176 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
177 register */
178 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
179 register */
180 u32 res1[3];
181 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
182 configuration register */
183 u32 res2[12];
184 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
185 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
186 u32 pad8;
187 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
188 address register */
189 u32 pad9;
190 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
191 address register */
192 u32 pad10[26];
193 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
194 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
195 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
196 register */
197 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
198 register */
199};
200
201struct rio_tx_desc {
202 u32 res1;
203 u32 saddr;
204 u32 dport;
205 u32 dattr;
206 u32 res2;
207 u32 res3;
208 u32 dwcnt;
209 u32 res4;
210};
211
212struct rio_dbell_ring {
213 void *virt;
214 dma_addr_t phys;
215};
216
217struct rio_msg_tx_ring {
218 void *virt;
219 dma_addr_t phys;
220 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
221 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
222 int tx_slot;
223 int size;
224 void *dev_id;
225};
226
227struct rio_msg_rx_ring {
228 void *virt;
229 dma_addr_t phys;
230 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
231 int rx_slot;
232 int size;
233 void *dev_id;
234};
235
236struct rio_port_write_msg {
237 void *virt;
238 dma_addr_t phys;
239 u32 msg_count;
240 u32 err_count;
241 u32 discard_count;
242};
243
244struct rio_priv {
245 struct device *dev;
246 void __iomem *regs_win;
247 struct rio_atmu_regs __iomem *atmu_regs;
248 struct rio_atmu_regs __iomem *maint_atmu_regs;
249 struct rio_atmu_regs __iomem *dbell_atmu_regs;
250 void __iomem *dbell_win;
251 void __iomem *maint_win;
252 struct rio_msg_regs __iomem *msg_regs;
253 struct rio_dbell_ring dbell_ring;
254 struct rio_msg_tx_ring msg_tx_ring;
255 struct rio_msg_rx_ring msg_rx_ring;
256 struct rio_port_write_msg port_write_msg;
257 int bellirq;
258 int txirq;
259 int rxirq;
260 int pwirq;
261 struct work_struct pw_work;
262 struct kfifo pw_fifo;
263 spinlock_t pw_fifo_lock;
264};
265 58
266#define __fsl_read_rio_config(x, addr, err, op) \ 59#define __fsl_read_rio_config(x, addr, err, op) \
267 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
@@ -279,7 +72,12 @@ struct rio_priv {
279 : "=r" (err), "=r" (x) \ 72 : "=r" (err), "=r" (x) \
280 : "b" (addr), "i" (-EFAULT), "0" (err)) 73 : "b" (addr), "i" (-EFAULT), "0" (err))
281 74
282static void __iomem *rio_regs_win; 75void __iomem *rio_regs_win;
76void __iomem *rmu_regs_win;
77resource_size_t rio_law_start;
78
79struct fsl_rio_dbell *dbell;
80struct fsl_rio_pw *pw;
283 81
284#ifdef CONFIG_E500 82#ifdef CONFIG_E500
285int fsl_rio_mcheck_exception(struct pt_regs *regs) 83int fsl_rio_mcheck_exception(struct pt_regs *regs)
@@ -311,42 +109,6 @@ EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
311#endif 109#endif
312 110
313/** 111/**
314 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
315 * @mport: RapidIO master port info
316 * @index: ID of RapidIO interface
317 * @destid: Destination ID of target device
318 * @data: 16-bit info field of RapidIO doorbell message
319 *
320 * Sends a MPC85xx doorbell message. Returns %0 on success or
321 * %-EINVAL on failure.
322 */
323static int fsl_rio_doorbell_send(struct rio_mport *mport,
324 int index, u16 destid, u16 data)
325{
326 struct rio_priv *priv = mport->priv;
327 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
328 index, destid, data);
329 switch (mport->phy_type) {
330 case RIO_PHY_PARALLEL:
331 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
332 out_be16(priv->dbell_win, data);
333 break;
334 case RIO_PHY_SERIAL:
335 /* In the serial version silicons, such as MPC8548, MPC8641,
336 * below operations is must be.
337 */
338 out_be32(&priv->msg_regs->odmr, 0x00000000);
339 out_be32(&priv->msg_regs->odretcr, 0x00000004);
340 out_be32(&priv->msg_regs->oddpr, destid << 16);
341 out_be32(&priv->msg_regs->oddatr, data);
342 out_be32(&priv->msg_regs->odmr, 0x00000001);
343 break;
344 }
345
346 return 0;
347}
348
349/**
350 * fsl_local_config_read - Generate a MPC85xx local config space read 112 * fsl_local_config_read - Generate a MPC85xx local config space read
351 * @mport: RapidIO master port info 113 * @mport: RapidIO master port info
352 * @index: ID of RapdiIO interface 114 * @index: ID of RapdiIO interface
@@ -384,8 +146,8 @@ static int fsl_local_config_write(struct rio_mport *mport,
384{ 146{
385 struct rio_priv *priv = mport->priv; 147 struct rio_priv *priv = mport->priv;
386 pr_debug 148 pr_debug
387 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 149 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
388 index, offset, data); 150 index, offset, data);
389 out_be32(priv->regs_win + offset, data); 151 out_be32(priv->regs_win + offset, data);
390 152
391 return 0; 153 return 0;
@@ -413,8 +175,9 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
413 u32 rval, err = 0; 175 u32 rval, err = 0;
414 176
415 pr_debug 177 pr_debug
416 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 178 ("fsl_rio_config_read:"
417 index, destid, hopcount, offset, len); 179 " index %d destid %d hopcount %d offset %8.8x len %d\n",
180 index, destid, hopcount, offset, len);
418 181
419 /* 16MB maintenance window possible */ 182 /* 16MB maintenance window possible */
420 /* allow only aligned access to maintenance registers */ 183 /* allow only aligned access to maintenance registers */
@@ -423,7 +186,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
423 186
424 out_be32(&priv->maint_atmu_regs->rowtar, 187 out_be32(&priv->maint_atmu_regs->rowtar,
425 (destid << 22) | (hopcount << 12) | (offset >> 12)); 188 (destid << 22) | (hopcount << 12) | (offset >> 12));
426 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 189 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
427 190
428 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 191 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
429 switch (len) { 192 switch (len) {
@@ -470,8 +233,9 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
470 struct rio_priv *priv = mport->priv; 233 struct rio_priv *priv = mport->priv;
471 u8 *data; 234 u8 *data;
472 pr_debug 235 pr_debug
473 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 236 ("fsl_rio_config_write:"
474 index, destid, hopcount, offset, len, val); 237 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
238 index, destid, hopcount, offset, len, val);
475 239
476 /* 16MB maintenance windows possible */ 240 /* 16MB maintenance windows possible */
477 /* allow only aligned access to maintenance registers */ 241 /* allow only aligned access to maintenance registers */
@@ -480,7 +244,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
480 244
481 out_be32(&priv->maint_atmu_regs->rowtar, 245 out_be32(&priv->maint_atmu_regs->rowtar,
482 (destid << 22) | (hopcount << 12) | (offset >> 12)); 246 (destid << 22) | (hopcount << 12) | (offset >> 12));
483 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 247 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
484 248
485 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 249 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
486 switch (len) { 250 switch (len) {
@@ -500,590 +264,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
500 return 0; 264 return 0;
501} 265}
502 266
503/** 267void fsl_rio_port_error_handler(int offset)
504 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
505 * @mport: Master port with outbound message queue
506 * @rdev: Target of outbound message
507 * @mbox: Outbound mailbox
508 * @buffer: Message to add to outbound queue
509 * @len: Length of message
510 *
511 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
512 * %0 on success or %-EINVAL on failure.
513 */
514static int
515fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
516 void *buffer, size_t len)
517{
518 struct rio_priv *priv = mport->priv;
519 u32 omr;
520 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
521 + priv->msg_tx_ring.tx_slot;
522 int ret = 0;
523
524 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
525 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
526
527 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
528 ret = -EINVAL;
529 goto out;
530 }
531
532 /* Copy and clear rest of buffer */
533 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
534 len);
535 if (len < (RIO_MAX_MSG_SIZE - 4))
536 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
537 + len, 0, RIO_MAX_MSG_SIZE - len);
538
539 switch (mport->phy_type) {
540 case RIO_PHY_PARALLEL:
541 /* Set mbox field for message */
542 desc->dport = mbox & 0x3;
543
544 /* Enable EOMI interrupt, set priority, and set destid */
545 desc->dattr = 0x28000000 | (rdev->destid << 2);
546 break;
547 case RIO_PHY_SERIAL:
548 /* Set mbox field for message, and set destid */
549 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
550
551 /* Enable EOMI interrupt and priority */
552 desc->dattr = 0x28000000;
553 break;
554 }
555
556 /* Set transfer size aligned to next power of 2 (in double words) */
557 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
558
559 /* Set snooping and source buffer address */
560 desc->saddr = 0x00000004
561 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
562
563 /* Increment enqueue pointer */
564 omr = in_be32(&priv->msg_regs->omr);
565 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
566
567 /* Go to next descriptor */
568 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
569 priv->msg_tx_ring.tx_slot = 0;
570
571 out:
572 return ret;
573}
574
575/**
576 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
577 * @irq: Linux interrupt number
578 * @dev_instance: Pointer to interrupt-specific data
579 *
580 * Handles outbound message interrupts. Executes a register outbound
581 * mailbox event handler and acks the interrupt occurrence.
582 */
583static irqreturn_t
584fsl_rio_tx_handler(int irq, void *dev_instance)
585{
586 int osr;
587 struct rio_mport *port = (struct rio_mport *)dev_instance;
588 struct rio_priv *priv = port->priv;
589
590 osr = in_be32(&priv->msg_regs->osr);
591
592 if (osr & RIO_MSG_OSR_TE) {
593 pr_info("RIO: outbound message transmission error\n");
594 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
595 goto out;
596 }
597
598 if (osr & RIO_MSG_OSR_QOI) {
599 pr_info("RIO: outbound message queue overflow\n");
600 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
601 goto out;
602 }
603
604 if (osr & RIO_MSG_OSR_EOMI) {
605 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
606 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
607 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
608 slot);
609
610 /* Ack the end-of-message interrupt */
611 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
612 }
613
614 out:
615 return IRQ_HANDLED;
616}
617
618/**
619 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
620 * @mport: Master port implementing the outbound message unit
621 * @dev_id: Device specific pointer to pass on event
622 * @mbox: Mailbox to open
623 * @entries: Number of entries in the outbound mailbox ring
624 *
625 * Initializes buffer ring, request the outbound message interrupt,
626 * and enables the outbound message unit. Returns %0 on success and
627 * %-EINVAL or %-ENOMEM on failure.
628 */
629static int
630fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
631{
632 int i, j, rc = 0;
633 struct rio_priv *priv = mport->priv;
634
635 if ((entries < RIO_MIN_TX_RING_SIZE) ||
636 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
637 rc = -EINVAL;
638 goto out;
639 }
640
641 /* Initialize shadow copy ring */
642 priv->msg_tx_ring.dev_id = dev_id;
643 priv->msg_tx_ring.size = entries;
644
645 for (i = 0; i < priv->msg_tx_ring.size; i++) {
646 priv->msg_tx_ring.virt_buffer[i] =
647 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
648 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
649 if (!priv->msg_tx_ring.virt_buffer[i]) {
650 rc = -ENOMEM;
651 for (j = 0; j < priv->msg_tx_ring.size; j++)
652 if (priv->msg_tx_ring.virt_buffer[j])
653 dma_free_coherent(priv->dev,
654 RIO_MSG_BUFFER_SIZE,
655 priv->msg_tx_ring.
656 virt_buffer[j],
657 priv->msg_tx_ring.
658 phys_buffer[j]);
659 goto out;
660 }
661 }
662
663 /* Initialize outbound message descriptor ring */
664 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
665 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
666 &priv->msg_tx_ring.phys, GFP_KERNEL);
667 if (!priv->msg_tx_ring.virt) {
668 rc = -ENOMEM;
669 goto out_dma;
670 }
671 memset(priv->msg_tx_ring.virt, 0,
672 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
673 priv->msg_tx_ring.tx_slot = 0;
674
675 /* Point dequeue/enqueue pointers at first entry in ring */
676 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
677 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
678
679 /* Configure for snooping */
680 out_be32(&priv->msg_regs->osar, 0x00000004);
681
682 /* Clear interrupt status */
683 out_be32(&priv->msg_regs->osr, 0x000000b3);
684
685 /* Hook up outbound message handler */
686 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
687 "msg_tx", (void *)mport);
688 if (rc < 0)
689 goto out_irq;
690
691 /*
692 * Configure outbound message unit
693 * Snooping
694 * Interrupts (all enabled, except QEIE)
695 * Chaining mode
696 * Disable
697 */
698 out_be32(&priv->msg_regs->omr, 0x00100220);
699
700 /* Set number of entries */
701 out_be32(&priv->msg_regs->omr,
702 in_be32(&priv->msg_regs->omr) |
703 ((get_bitmask_order(entries) - 2) << 12));
704
705 /* Now enable the unit */
706 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
707
708 out:
709 return rc;
710
711 out_irq:
712 dma_free_coherent(priv->dev,
713 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
714 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
715
716 out_dma:
717 for (i = 0; i < priv->msg_tx_ring.size; i++)
718 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
719 priv->msg_tx_ring.virt_buffer[i],
720 priv->msg_tx_ring.phys_buffer[i]);
721
722 return rc;
723}
724
725/**
726 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
727 * @mport: Master port implementing the outbound message unit
728 * @mbox: Mailbox to close
729 *
730 * Disables the outbound message unit, free all buffers, and
731 * frees the outbound message interrupt.
732 */
733static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
734{
735 struct rio_priv *priv = mport->priv;
736 /* Disable inbound message unit */
737 out_be32(&priv->msg_regs->omr, 0);
738
739 /* Free ring */
740 dma_free_coherent(priv->dev,
741 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
742 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
743
744 /* Free interrupt */
745 free_irq(IRQ_RIO_TX(mport), (void *)mport);
746}
747
748/**
749 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
750 * @irq: Linux interrupt number
751 * @dev_instance: Pointer to interrupt-specific data
752 *
753 * Handles inbound message interrupts. Executes a registered inbound
754 * mailbox event handler and acks the interrupt occurrence.
755 */
756static irqreturn_t
757fsl_rio_rx_handler(int irq, void *dev_instance)
758{
759 int isr;
760 struct rio_mport *port = (struct rio_mport *)dev_instance;
761 struct rio_priv *priv = port->priv;
762
763 isr = in_be32(&priv->msg_regs->isr);
764
765 if (isr & RIO_MSG_ISR_TE) {
766 pr_info("RIO: inbound message reception error\n");
767 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
768 goto out;
769 }
770
771 /* XXX Need to check/dispatch until queue empty */
772 if (isr & RIO_MSG_ISR_DIQI) {
773 /*
774 * We implement *only* mailbox 0, but can receive messages
775 * for any mailbox/letter to that mailbox destination. So,
776 * make the callback with an unknown/invalid mailbox number
777 * argument.
778 */
779 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
780
781 /* Ack the queueing interrupt */
782 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
783 }
784
785 out:
786 return IRQ_HANDLED;
787}
788
789/**
790 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
791 * @mport: Master port implementing the inbound message unit
792 * @dev_id: Device specific pointer to pass on event
793 * @mbox: Mailbox to open
794 * @entries: Number of entries in the inbound mailbox ring
795 *
796 * Initializes buffer ring, request the inbound message interrupt,
797 * and enables the inbound message unit. Returns %0 on success
798 * and %-EINVAL or %-ENOMEM on failure.
799 */
800static int
801fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
802{
803 int i, rc = 0;
804 struct rio_priv *priv = mport->priv;
805
806 if ((entries < RIO_MIN_RX_RING_SIZE) ||
807 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
808 rc = -EINVAL;
809 goto out;
810 }
811
812 /* Initialize client buffer ring */
813 priv->msg_rx_ring.dev_id = dev_id;
814 priv->msg_rx_ring.size = entries;
815 priv->msg_rx_ring.rx_slot = 0;
816 for (i = 0; i < priv->msg_rx_ring.size; i++)
817 priv->msg_rx_ring.virt_buffer[i] = NULL;
818
819 /* Initialize inbound message ring */
820 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
821 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
822 &priv->msg_rx_ring.phys, GFP_KERNEL);
823 if (!priv->msg_rx_ring.virt) {
824 rc = -ENOMEM;
825 goto out;
826 }
827
828 /* Point dequeue/enqueue pointers at first entry in ring */
829 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
830 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
831
832 /* Clear interrupt status */
833 out_be32(&priv->msg_regs->isr, 0x00000091);
834
835 /* Hook up inbound message handler */
836 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
837 "msg_rx", (void *)mport);
838 if (rc < 0) {
839 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
840 priv->msg_tx_ring.virt_buffer[i],
841 priv->msg_tx_ring.phys_buffer[i]);
842 goto out;
843 }
844
845 /*
846 * Configure inbound message unit:
847 * Snooping
848 * 4KB max message size
849 * Unmask all interrupt sources
850 * Disable
851 */
852 out_be32(&priv->msg_regs->imr, 0x001b0060);
853
854 /* Set number of queue entries */
855 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
856
857 /* Now enable the unit */
858 setbits32(&priv->msg_regs->imr, 0x1);
859
860 out:
861 return rc;
862}
863
864/**
865 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
866 * @mport: Master port implementing the inbound message unit
867 * @mbox: Mailbox to close
868 *
869 * Disables the inbound message unit, free all buffers, and
870 * frees the inbound message interrupt.
871 */
872static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
873{
874 struct rio_priv *priv = mport->priv;
875 /* Disable inbound message unit */
876 out_be32(&priv->msg_regs->imr, 0);
877
878 /* Free ring */
879 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
880 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
881
882 /* Free interrupt */
883 free_irq(IRQ_RIO_RX(mport), (void *)mport);
884}
885
886/**
887 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
888 * @mport: Master port implementing the inbound message unit
889 * @mbox: Inbound mailbox number
890 * @buf: Buffer to add to inbound queue
891 *
892 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
893 * %0 on success or %-EINVAL on failure.
894 */
895static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
896{
897 int rc = 0;
898 struct rio_priv *priv = mport->priv;
899
900 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
901 priv->msg_rx_ring.rx_slot);
902
903 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
904 printk(KERN_ERR
905 "RIO: error adding inbound buffer %d, buffer exists\n",
906 priv->msg_rx_ring.rx_slot);
907 rc = -EINVAL;
908 goto out;
909 }
910
911 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
912 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
913 priv->msg_rx_ring.rx_slot = 0;
914
915 out:
916 return rc;
917}
918
919/**
920 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
921 * @mport: Master port implementing the inbound message unit
922 * @mbox: Inbound mailbox number
923 *
924 * Gets the next available inbound message from the inbound message queue.
925 * A pointer to the message is returned on success or NULL on failure.
926 */
927static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
928{
929 struct rio_priv *priv = mport->priv;
930 u32 phys_buf, virt_buf;
931 void *buf = NULL;
932 int buf_idx;
933
934 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
935
936 /* If no more messages, then bail out */
937 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
938 goto out2;
939
940 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
941 - priv->msg_rx_ring.phys);
942 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
943 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
944
945 if (!buf) {
946 printk(KERN_ERR
947 "RIO: inbound message copy failed, no buffers\n");
948 goto out1;
949 }
950
951 /* Copy max message size, caller is expected to allocate that big */
952 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
953
954 /* Clear the available buffer */
955 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
956
957 out1:
958 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
959
960 out2:
961 return buf;
962}
963
964/**
965 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
966 * @irq: Linux interrupt number
967 * @dev_instance: Pointer to interrupt-specific data
968 *
969 * Handles doorbell interrupts. Parses a list of registered
970 * doorbell event handlers and executes a matching event handler.
971 */
972static irqreturn_t
973fsl_rio_dbell_handler(int irq, void *dev_instance)
974{
975 int dsr;
976 struct rio_mport *port = (struct rio_mport *)dev_instance;
977 struct rio_priv *priv = port->priv;
978
979 dsr = in_be32(&priv->msg_regs->dsr);
980
981 if (dsr & DOORBELL_DSR_TE) {
982 pr_info("RIO: doorbell reception error\n");
983 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
984 goto out;
985 }
986
987 if (dsr & DOORBELL_DSR_QFI) {
988 pr_info("RIO: doorbell queue full\n");
989 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
990 }
991
992 /* XXX Need to check/dispatch until queue empty */
993 if (dsr & DOORBELL_DSR_DIQI) {
994 u32 dmsg =
995 (u32) priv->dbell_ring.virt +
996 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
997 struct rio_dbell *dbell;
998 int found = 0;
999
1000 pr_debug
1001 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1002 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1003
1004 list_for_each_entry(dbell, &port->dbells, node) {
1005 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
1006 (dbell->res->end >= DBELL_INF(dmsg))) {
1007 found = 1;
1008 break;
1009 }
1010 }
1011 if (found) {
1012 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
1013 DBELL_INF(dmsg));
1014 } else {
1015 pr_debug
1016 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1017 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1018 }
1019 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1020 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1021 }
1022
1023 out:
1024 return IRQ_HANDLED;
1025}
1026
1027/**
1028 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1029 * @mport: Master port implementing the inbound doorbell unit
1030 *
1031 * Initializes doorbell unit hardware and inbound DMA buffer
1032 * ring. Called from fsl_rio_setup(). Returns %0 on success
1033 * or %-ENOMEM on failure.
1034 */
1035static int fsl_rio_doorbell_init(struct rio_mport *mport)
1036{
1037 struct rio_priv *priv = mport->priv;
1038 int rc = 0;
1039
1040 /* Map outbound doorbell window immediately after maintenance window */
1041 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1042 RIO_DBELL_WIN_SIZE);
1043 if (!priv->dbell_win) {
1044 printk(KERN_ERR
1045 "RIO: unable to map outbound doorbell window\n");
1046 rc = -ENOMEM;
1047 goto out;
1048 }
1049
1050 /* Initialize inbound doorbells */
1051 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1052 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1053 if (!priv->dbell_ring.virt) {
1054 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1055 rc = -ENOMEM;
1056 iounmap(priv->dbell_win);
1057 goto out;
1058 }
1059
1060 /* Point dequeue/enqueue pointers at first entry in ring */
1061 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1062 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1063
1064 /* Clear interrupt status */
1065 out_be32(&priv->msg_regs->dsr, 0x00000091);
1066
1067 /* Hook up doorbell handler */
1068 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1069 "dbell_rx", (void *)mport);
1070 if (rc < 0) {
1071 iounmap(priv->dbell_win);
1072 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1073 priv->dbell_ring.virt, priv->dbell_ring.phys);
1074 printk(KERN_ERR
1075 "MPC85xx RIO: unable to request inbound doorbell irq");
1076 goto out;
1077 }
1078
1079 /* Configure doorbells for snooping, 512 entries, and enable */
1080 out_be32(&priv->msg_regs->dmr, 0x00108161);
1081
1082 out:
1083 return rc;
1084}
1085
1086static void port_error_handler(struct rio_mport *port, int offset)
1087{ 268{
1088 /*XXX: Error recovery is not implemented, we just clear errors */ 269 /*XXX: Error recovery is not implemented, we just clear errors */
1089 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 270 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
@@ -1098,263 +279,6 @@ static void port_error_handler(struct rio_mport *port, int offset)
1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 279 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
1099 } 280 }
1100} 281}
1101
1102static void msg_unit_error_handler(struct rio_mport *port)
1103{
1104 struct rio_priv *priv = port->priv;
1105
1106 /*XXX: Error recovery is not implemented, we just clear errors */
1107 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
1108
1109 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
1110 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
1111 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
1112 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
1113
1114 out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
1115 out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
1116
1117 out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
1118}
1119
1120/**
1121 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1122 * @irq: Linux interrupt number
1123 * @dev_instance: Pointer to interrupt-specific data
1124 *
1125 * Handles port write interrupts. Parses a list of registered
1126 * port write event handlers and executes a matching event handler.
1127 */
1128static irqreturn_t
1129fsl_rio_port_write_handler(int irq, void *dev_instance)
1130{
1131 u32 ipwmr, ipwsr;
1132 struct rio_mport *port = (struct rio_mport *)dev_instance;
1133 struct rio_priv *priv = port->priv;
1134 u32 epwisr, tmp;
1135
1136 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1137 if (!(epwisr & RIO_EPWISR_PW))
1138 goto pw_done;
1139
1140 ipwmr = in_be32(&priv->msg_regs->pwmr);
1141 ipwsr = in_be32(&priv->msg_regs->pwsr);
1142
1143#ifdef DEBUG_PW
1144 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1145 if (ipwsr & RIO_IPWSR_QF)
1146 pr_debug(" QF");
1147 if (ipwsr & RIO_IPWSR_TE)
1148 pr_debug(" TE");
1149 if (ipwsr & RIO_IPWSR_QFI)
1150 pr_debug(" QFI");
1151 if (ipwsr & RIO_IPWSR_PWD)
1152 pr_debug(" PWD");
1153 if (ipwsr & RIO_IPWSR_PWB)
1154 pr_debug(" PWB");
1155 pr_debug(" )\n");
1156#endif
1157 /* Schedule deferred processing if PW was received */
1158 if (ipwsr & RIO_IPWSR_QFI) {
1159 /* Save PW message (if there is room in FIFO),
1160 * otherwise discard it.
1161 */
1162 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1163 priv->port_write_msg.msg_count++;
1164 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1165 RIO_PW_MSG_SIZE);
1166 } else {
1167 priv->port_write_msg.discard_count++;
1168 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1169 priv->port_write_msg.discard_count);
1170 }
1171 /* Clear interrupt and issue Clear Queue command. This allows
1172 * another port-write to be received.
1173 */
1174 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1175 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1176
1177 schedule_work(&priv->pw_work);
1178 }
1179
1180 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1181 priv->port_write_msg.err_count++;
1182 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1183 priv->port_write_msg.err_count);
1184 /* Clear Transaction Error: port-write controller should be
1185 * disabled when clearing this error
1186 */
1187 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1188 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1189 out_be32(&priv->msg_regs->pwmr, ipwmr);
1190 }
1191
1192 if (ipwsr & RIO_IPWSR_PWD) {
1193 priv->port_write_msg.discard_count++;
1194 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1195 priv->port_write_msg.discard_count);
1196 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1197 }
1198
1199pw_done:
1200 if (epwisr & RIO_EPWISR_PINT1) {
1201 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1202 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1203 port_error_handler(port, 0);
1204 }
1205
1206 if (epwisr & RIO_EPWISR_PINT2) {
1207 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1208 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1209 port_error_handler(port, 1);
1210 }
1211
1212 if (epwisr & RIO_EPWISR_MU) {
1213 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1214 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1215 msg_unit_error_handler(port);
1216 }
1217
1218 return IRQ_HANDLED;
1219}
1220
1221static void fsl_pw_dpc(struct work_struct *work)
1222{
1223 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1224 unsigned long flags;
1225 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1226
1227 /*
1228 * Process port-write messages
1229 */
1230 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1231 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1232 RIO_PW_MSG_SIZE)) {
1233 /* Process one message */
1234 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1235#ifdef DEBUG_PW
1236 {
1237 u32 i;
1238 pr_debug("%s : Port-Write Message:", __func__);
1239 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1240 if ((i%4) == 0)
1241 pr_debug("\n0x%02x: 0x%08x", i*4,
1242 msg_buffer[i]);
1243 else
1244 pr_debug(" 0x%08x", msg_buffer[i]);
1245 }
1246 pr_debug("\n");
1247 }
1248#endif
1249 /* Pass the port-write message to RIO core for processing */
1250 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1251 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1252 }
1253 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1254}
1255
1256/**
1257 * fsl_rio_pw_enable - enable/disable port-write interface init
1258 * @mport: Master port implementing the port write unit
1259 * @enable: 1=enable; 0=disable port-write message handling
1260 */
1261static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1262{
1263 struct rio_priv *priv = mport->priv;
1264 u32 rval;
1265
1266 rval = in_be32(&priv->msg_regs->pwmr);
1267
1268 if (enable)
1269 rval |= RIO_IPWMR_PWE;
1270 else
1271 rval &= ~RIO_IPWMR_PWE;
1272
1273 out_be32(&priv->msg_regs->pwmr, rval);
1274
1275 return 0;
1276}
1277
1278/**
1279 * fsl_rio_port_write_init - MPC85xx port write interface init
1280 * @mport: Master port implementing the port write unit
1281 *
1282 * Initializes port write unit hardware and DMA buffer
1283 * ring. Called from fsl_rio_setup(). Returns %0 on success
1284 * or %-ENOMEM on failure.
1285 */
1286static int fsl_rio_port_write_init(struct rio_mport *mport)
1287{
1288 struct rio_priv *priv = mport->priv;
1289 int rc = 0;
1290
1291 /* Following configurations require a disabled port write controller */
1292 out_be32(&priv->msg_regs->pwmr,
1293 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1294
1295 /* Initialize port write */
1296 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1297 RIO_PW_MSG_SIZE,
1298 &priv->port_write_msg.phys, GFP_KERNEL);
1299 if (!priv->port_write_msg.virt) {
1300 pr_err("RIO: unable allocate port write queue\n");
1301 return -ENOMEM;
1302 }
1303
1304 priv->port_write_msg.err_count = 0;
1305 priv->port_write_msg.discard_count = 0;
1306
1307 /* Point dequeue/enqueue pointers at first entry */
1308 out_be32(&priv->msg_regs->epwqbar, 0);
1309 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1310
1311 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1312 in_be32(&priv->msg_regs->epwqbar),
1313 in_be32(&priv->msg_regs->pwqbar));
1314
1315 /* Clear interrupt status IPWSR */
1316 out_be32(&priv->msg_regs->pwsr,
1317 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1318
1319 /* Configure port write contoller for snooping enable all reporting,
1320 clear queue full */
1321 out_be32(&priv->msg_regs->pwmr,
1322 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1323
1324
1325 /* Hook up port-write handler */
1326 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
1327 IRQF_SHARED, "port-write", (void *)mport);
1328 if (rc < 0) {
1329 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1330 goto err_out;
1331 }
1332 /* Enable Error Interrupt */
1333 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
1334
1335 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1336 spin_lock_init(&priv->pw_fifo_lock);
1337 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1338 pr_err("FIFO allocation failed\n");
1339 rc = -ENOMEM;
1340 goto err_out_irq;
1341 }
1342
1343 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1344 in_be32(&priv->msg_regs->pwmr),
1345 in_be32(&priv->msg_regs->pwsr));
1346
1347 return rc;
1348
1349err_out_irq:
1350 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1351err_out:
1352 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1353 priv->port_write_msg.virt,
1354 priv->port_write_msg.phys);
1355 return rc;
1356}
1357
1358static inline void fsl_rio_info(struct device *dev, u32 ccsr) 282static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1359{ 283{
1360 const char *str; 284 const char *str;
@@ -1411,16 +335,21 @@ int fsl_rio_setup(struct platform_device *dev)
1411 struct rio_mport *port; 335 struct rio_mport *port;
1412 struct rio_priv *priv; 336 struct rio_priv *priv;
1413 int rc = 0; 337 int rc = 0;
1414 const u32 *dt_range, *cell; 338 const u32 *dt_range, *cell, *port_index;
1415 struct resource regs; 339 u32 active_ports = 0;
340 struct resource regs, rmu_regs;
341 struct device_node *np, *rmu_node;
1416 int rlen; 342 int rlen;
1417 u32 ccsr; 343 u32 ccsr;
1418 u64 law_start, law_size; 344 u64 range_start, range_size;
1419 int paw, aw, sw; 345 int paw, aw, sw;
346 u32 i;
347 static int tmp;
348 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
1420 349
1421 if (!dev->dev.of_node) { 350 if (!dev->dev.of_node) {
1422 dev_err(&dev->dev, "Device OF-Node is NULL"); 351 dev_err(&dev->dev, "Device OF-Node is NULL");
1423 return -EFAULT; 352 return -ENODEV;
1424 } 353 }
1425 354
1426 rc = of_address_to_resource(dev->dev.of_node, 0, &regs); 355 rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
@@ -1429,37 +358,17 @@ int fsl_rio_setup(struct platform_device *dev)
1429 dev->dev.of_node->full_name); 358 dev->dev.of_node->full_name);
1430 return -EFAULT; 359 return -EFAULT;
1431 } 360 }
1432 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 361 dev_info(&dev->dev, "Of-device full name %s\n",
362 dev->dev.of_node->full_name);
1433 dev_info(&dev->dev, "Regs: %pR\n", &regs); 363 dev_info(&dev->dev, "Regs: %pR\n", &regs);
1434 364
1435 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 365 rio_regs_win = ioremap(regs.start, resource_size(&regs));
1436 if (!dt_range) { 366 if (!rio_regs_win) {
1437 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 367 dev_err(&dev->dev, "Unable to map rio register window\n");
1438 dev->dev.of_node->full_name); 368 rc = -ENOMEM;
1439 return -EFAULT; 369 goto err_rio_regs;
1440 } 370 }
1441 371
1442 /* Get node address wide */
1443 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1444 if (cell)
1445 aw = *cell;
1446 else
1447 aw = of_n_addr_cells(dev->dev.of_node);
1448 /* Get node size wide */
1449 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1450 if (cell)
1451 sw = *cell;
1452 else
1453 sw = of_n_size_cells(dev->dev.of_node);
1454 /* Get parent address wide wide */
1455 paw = of_n_addr_cells(dev->dev.of_node);
1456
1457 law_start = of_read_number(dt_range + aw, paw);
1458 law_size = of_read_number(dt_range + aw + paw, sw);
1459
1460 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1461 law_start, law_size);
1462
1463 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 372 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1464 if (!ops) { 373 if (!ops) {
1465 rc = -ENOMEM; 374 rc = -ENOMEM;
@@ -1479,143 +388,257 @@ int fsl_rio_setup(struct platform_device *dev)
1479 ops->add_inb_buffer = fsl_add_inb_buffer; 388 ops->add_inb_buffer = fsl_add_inb_buffer;
1480 ops->get_inb_message = fsl_get_inb_message; 389 ops->get_inb_message = fsl_get_inb_message;
1481 390
1482 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 391 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
1483 if (!port) { 392 if (!rmu_node)
393 goto err_rmu;
394 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
395 if (rc) {
396 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
397 rmu_node->full_name);
398 goto err_rmu;
399 }
400 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
401 if (!rmu_regs_win) {
402 dev_err(&dev->dev, "Unable to map rmu register window\n");
1484 rc = -ENOMEM; 403 rc = -ENOMEM;
1485 goto err_port; 404 goto err_rmu;
405 }
406 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
407 rmu_np[tmp] = np;
408 tmp++;
1486 } 409 }
1487 port->index = 0;
1488 410
1489 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 411 /*set up doobell node*/
1490 if (!priv) { 412 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
1491 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 413 if (!np) {
414 rc = -ENODEV;
415 goto err_dbell;
416 }
417 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
418 if (!(dbell)) {
419 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
1492 rc = -ENOMEM; 420 rc = -ENOMEM;
1493 goto err_priv; 421 goto err_dbell;
1494 } 422 }
423 dbell->dev = &dev->dev;
424 dbell->bellirq = irq_of_parse_and_map(np, 1);
425 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
1495 426
1496 INIT_LIST_HEAD(&port->dbells); 427 aw = of_n_addr_cells(np);
1497 port->iores.start = law_start; 428 dt_range = of_get_property(np, "reg", &rlen);
1498 port->iores.end = law_start + law_size - 1; 429 if (!dt_range) {
1499 port->iores.flags = IORESOURCE_MEM; 430 pr_err("%s: unable to find 'reg' property\n",
1500 port->iores.name = "rio_io_win"; 431 np->full_name);
1501 432 rc = -ENOMEM;
1502 if (request_resource(&iomem_resource, &port->iores) < 0) { 433 goto err_pw;
1503 dev_err(&dev->dev, "RIO: Error requesting master port region"
1504 " 0x%016llx-0x%016llx\n",
1505 (u64)port->iores.start, (u64)port->iores.end);
1506 rc = -ENOMEM;
1507 goto err_res;
1508 } 434 }
435 range_start = of_read_number(dt_range, aw);
436 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
437 (u32)range_start);
1509 438
1510 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 439 /*set up port write node*/
1511 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 440 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
1512 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 441 if (!np) {
1513 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 442 rc = -ENODEV;
1514 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 443 goto err_pw;
1515 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 444 }
1516 445 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
1517 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 446 if (!(pw)) {
1518 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 447 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
1519 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 448 rc = -ENOMEM;
1520 strcpy(port->name, "RIO0 mport"); 449 goto err_pw;
1521 450 }
1522 priv->dev = &dev->dev; 451 pw->dev = &dev->dev;
1523 452 pw->pwirq = irq_of_parse_and_map(np, 0);
1524 port->ops = ops; 453 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
1525 port->priv = priv; 454 aw = of_n_addr_cells(np);
1526 port->phys_efptr = 0x100; 455 dt_range = of_get_property(np, "reg", &rlen);
1527 456 if (!dt_range) {
1528 priv->regs_win = ioremap(regs.start, resource_size(&regs)); 457 pr_err("%s: unable to find 'reg' property\n",
1529 rio_regs_win = priv->regs_win; 458 np->full_name);
1530 459 rc = -ENOMEM;
1531 /* Probe the master port phy type */ 460 goto err;
1532 ccsr = in_be32(priv->regs_win + RIO_CCSR); 461 }
1533 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 462 range_start = of_read_number(dt_range, aw);
1534 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 463 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
1535 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 464
1536 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 465 /*set up ports node*/
1537 "unknown")); 466 for_each_child_of_node(dev->dev.of_node, np) {
1538 /* Checking the port training status */ 467 port_index = of_get_property(np, "cell-index", NULL);
1539 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 468 if (!port_index) {
1540 dev_err(&dev->dev, "Port is not ready. " 469 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
1541 "Try to restart connection...\n"); 470 np->full_name);
1542 switch (port->phy_type) { 471 continue;
1543 case RIO_PHY_SERIAL: 472 }
473
474 dt_range = of_get_property(np, "ranges", &rlen);
475 if (!dt_range) {
476 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
477 np->full_name);
478 continue;
479 }
480
481 /* Get node address wide */
482 cell = of_get_property(np, "#address-cells", NULL);
483 if (cell)
484 aw = *cell;
485 else
486 aw = of_n_addr_cells(np);
487 /* Get node size wide */
488 cell = of_get_property(np, "#size-cells", NULL);
489 if (cell)
490 sw = *cell;
491 else
492 sw = of_n_size_cells(np);
493 /* Get parent address wide wide */
494 paw = of_n_addr_cells(np);
495 range_start = of_read_number(dt_range + aw, paw);
496 range_size = of_read_number(dt_range + aw + paw, sw);
497
498 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
499 np->full_name, range_start, range_size);
500
501 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
502 if (!port)
503 continue;
504
505 i = *port_index - 1;
506 port->index = (unsigned char)i;
507
508 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
509 if (!priv) {
510 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
511 kfree(port);
512 continue;
513 }
514
515 INIT_LIST_HEAD(&port->dbells);
516 port->iores.start = range_start;
517 port->iores.end = port->iores.start + range_size - 1;
518 port->iores.flags = IORESOURCE_MEM;
519 port->iores.name = "rio_io_win";
520
521 if (request_resource(&iomem_resource, &port->iores) < 0) {
522 dev_err(&dev->dev, "RIO: Error requesting master port region"
523 " 0x%016llx-0x%016llx\n",
524 (u64)port->iores.start, (u64)port->iores.end);
525 kfree(priv);
526 kfree(port);
527 continue;
528 }
529 sprintf(port->name, "RIO mport %d", i);
530
531 priv->dev = &dev->dev;
532 port->ops = ops;
533 port->priv = priv;
534 port->phys_efptr = 0x100;
535 priv->regs_win = rio_regs_win;
536
537 /* Probe the master port phy type */
538 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
539 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
540 if (port->phy_type == RIO_PHY_PARALLEL) {
541 dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
542 release_resource(&port->iores);
543 kfree(priv);
544 kfree(port);
545 continue;
546 }
547 dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
548 /* Checking the port training status */
549 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
550 dev_err(&dev->dev, "Port %d is not ready. "
551 "Try to restart connection...\n", i);
1544 /* Disable ports */ 552 /* Disable ports */
1545 out_be32(priv->regs_win + RIO_CCSR, 0); 553 out_be32(priv->regs_win
554 + RIO_CCSR + i*0x20, 0);
1546 /* Set 1x lane */ 555 /* Set 1x lane */
1547 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 556 setbits32(priv->regs_win
557 + RIO_CCSR + i*0x20, 0x02000000);
1548 /* Enable ports */ 558 /* Enable ports */
1549 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 559 setbits32(priv->regs_win
1550 break; 560 + RIO_CCSR + i*0x20, 0x00600000);
1551 case RIO_PHY_PARALLEL: 561 msleep(100);
1552 /* Disable ports */ 562 if (in_be32((priv->regs_win
1553 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 563 + RIO_ESCSR + i*0x20)) & 1) {
1554 /* Enable ports */ 564 dev_err(&dev->dev,
1555 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 565 "Port %d restart failed.\n", i);
1556 break; 566 release_resource(&port->iores);
1557 } 567 kfree(priv);
1558 msleep(100); 568 kfree(port);
1559 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 569 continue;
1560 dev_err(&dev->dev, "Port restart failed.\n"); 570 }
1561 rc = -ENOLINK; 571 dev_info(&dev->dev, "Port %d restart success!\n", i);
1562 goto err;
1563 } 572 }
1564 dev_info(&dev->dev, "Port restart success!\n"); 573 fsl_rio_info(&dev->dev, ccsr);
1565 }
1566 fsl_rio_info(&dev->dev, ccsr);
1567 574
1568 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 575 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1569 & RIO_PEF_CTLS) >> 4; 576 & RIO_PEF_CTLS) >> 4;
1570 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 577 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1571 port->sys_size ? 65536 : 256); 578 port->sys_size ? 65536 : 256);
579
580 if (rio_register_mport(port)) {
581 release_resource(&port->iores);
582 kfree(priv);
583 kfree(port);
584 continue;
585 }
586 if (port->host_deviceid >= 0)
587 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
588 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
589 else
590 out_be32(priv->regs_win + RIO_GCCSR,
591 RIO_PORT_GEN_MASTER);
592
593 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
594 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
595 RIO_ATMU_REGS_PORT2_OFFSET));
1572 596
1573 if (rio_register_mport(port)) 597 priv->maint_atmu_regs = priv->atmu_regs + 1;
598
599 /* Set to receive any dist ID for serial RapidIO controller. */
600 if (port->phy_type == RIO_PHY_SERIAL)
601 out_be32((priv->regs_win
602 + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
603
604 /* Configure maintenance transaction window */
605 out_be32(&priv->maint_atmu_regs->rowbar,
606 port->iores.start >> 12);
607 out_be32(&priv->maint_atmu_regs->rowar,
608 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
609
610 priv->maint_win = ioremap(port->iores.start,
611 RIO_MAINT_WIN_SIZE);
612
613 rio_law_start = range_start;
614
615 fsl_rio_setup_rmu(port, rmu_np[i]);
616
617 dbell->mport[i] = port;
618
619 active_ports++;
620 }
621
622 if (!active_ports) {
623 rc = -ENOLINK;
1574 goto err; 624 goto err;
625 }
1575 626
1576 if (port->host_deviceid >= 0) 627 fsl_rio_doorbell_init(dbell);
1577 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 628 fsl_rio_port_write_init(pw);
1578 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
1579 else
1580 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
1581
1582 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1583 + RIO_ATMU_REGS_OFFSET);
1584 priv->maint_atmu_regs = priv->atmu_regs + 1;
1585 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1586 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1587 ((port->phy_type == RIO_PHY_SERIAL) ?
1588 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1589
1590 /* Set to receive any dist ID for serial RapidIO controller. */
1591 if (port->phy_type == RIO_PHY_SERIAL)
1592 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1593
1594 /* Configure maintenance transaction window */
1595 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1596 out_be32(&priv->maint_atmu_regs->rowar,
1597 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1598
1599 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1600
1601 /* Configure outbound doorbell window */
1602 out_be32(&priv->dbell_atmu_regs->rowbar,
1603 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1604 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1605 fsl_rio_doorbell_init(port);
1606 fsl_rio_port_write_init(port);
1607 629
1608 return 0; 630 return 0;
1609err: 631err:
1610 iounmap(priv->regs_win); 632 kfree(pw);
1611 release_resource(&port->iores); 633err_pw:
1612err_res: 634 kfree(dbell);
1613 kfree(priv); 635err_dbell:
1614err_priv: 636 iounmap(rmu_regs_win);
1615 kfree(port); 637err_rmu:
1616err_port:
1617 kfree(ops); 638 kfree(ops);
1618err_ops: 639err_ops:
640 iounmap(rio_regs_win);
641err_rio_regs:
1619 return rc; 642 return rc;
1620} 643}
1621 644
@@ -1631,7 +654,7 @@ static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
1631 654
1632static const struct of_device_id fsl_of_rio_rpn_ids[] = { 655static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1633 { 656 {
1634 .compatible = "fsl,rapidio-delta", 657 .compatible = "fsl,srio",
1635 }, 658 },
1636 {}, 659 {},
1637}; 660};
diff --git a/arch/powerpc/sysdev/fsl_rio.h b/arch/powerpc/sysdev/fsl_rio.h
new file mode 100644
index 00000000000..ae8e27405a0
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rio.h
@@ -0,0 +1,135 @@
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
16 * Liu Gang <Gang.Liu@freescale.com>
17 *
18 * Copyright 2005 MontaVista Software, Inc.
19 * Matt Porter <mporter@kernel.crashing.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 */
26
27#ifndef __FSL_RIO_H
28#define __FSL_RIO_H
29
30#include <linux/rio.h>
31#include <linux/rio_drv.h>
32#include <linux/kfifo.h>
33
34#define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win)
35
36#define RIO_MAINT_WIN_SIZE 0x400000
37#define RIO_LTLEDCSR 0x0608
38
39#define DOORBELL_ROWAR_EN 0x80000000
40#define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
41#define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
42#define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
43#define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
44#define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserverd */
45#define DOORBELL_ROWAR_MAINTWD 0x00007000
46#define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
47
48#define RIO_ATMU_REGS_PORT1_OFFSET 0x10c00
49#define RIO_ATMU_REGS_PORT2_OFFSET 0x10e00
50#define RIO_S_DBELL_REGS_OFFSET 0x13400
51#define RIO_S_PW_REGS_OFFSET 0x134e0
52#define RIO_ATMU_REGS_DBELL_OFFSET 0x10C40
53
54#define MAX_MSG_UNIT_NUM 2
55#define MAX_PORT_NUM 4
56
57struct rio_atmu_regs {
58 u32 rowtar;
59 u32 rowtear;
60 u32 rowbar;
61 u32 pad1;
62 u32 rowar;
63 u32 pad2[3];
64};
65
66struct rio_dbell_ring {
67 void *virt;
68 dma_addr_t phys;
69};
70
71struct rio_port_write_msg {
72 void *virt;
73 dma_addr_t phys;
74 u32 msg_count;
75 u32 err_count;
76 u32 discard_count;
77};
78
79struct fsl_rio_dbell {
80 struct rio_mport *mport[MAX_PORT_NUM];
81 struct device *dev;
82 struct rio_dbell_regs __iomem *dbell_regs;
83 struct rio_dbell_ring dbell_ring;
84 int bellirq;
85};
86
87struct fsl_rio_pw {
88 struct device *dev;
89 struct rio_pw_regs __iomem *pw_regs;
90 struct rio_port_write_msg port_write_msg;
91 int pwirq;
92 struct work_struct pw_work;
93 struct kfifo pw_fifo;
94 spinlock_t pw_fifo_lock;
95};
96
97struct rio_priv {
98 struct device *dev;
99 void __iomem *regs_win;
100 struct rio_atmu_regs __iomem *atmu_regs;
101 struct rio_atmu_regs __iomem *maint_atmu_regs;
102 void __iomem *maint_win;
103 void *rmm_handle; /* RapidIO message manager(unit) Handle */
104};
105
106extern void __iomem *rio_regs_win;
107extern void __iomem *rmu_regs_win;
108
109extern resource_size_t rio_law_start;
110
111extern struct fsl_rio_dbell *dbell;
112extern struct fsl_rio_pw *pw;
113
114extern int fsl_rio_setup_rmu(struct rio_mport *mport,
115 struct device_node *node);
116extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
117extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
118extern void fsl_rio_port_error_handler(int offset);
119extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
120
121extern int fsl_rio_doorbell_send(struct rio_mport *mport,
122 int index, u16 destid, u16 data);
123extern int fsl_add_outb_message(struct rio_mport *mport,
124 struct rio_dev *rdev,
125 int mbox, void *buffer, size_t len);
126extern int fsl_open_outb_mbox(struct rio_mport *mport,
127 void *dev_id, int mbox, int entries);
128extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
129extern int fsl_open_inb_mbox(struct rio_mport *mport,
130 void *dev_id, int mbox, int entries);
131extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
132extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
133extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);
134
135#endif
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
new file mode 100644
index 00000000000..15485789e9d
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -0,0 +1,1104 @@
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO RMU support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
16 * Liu Gang <Gang.Liu@freescale.com>
17 *
18 * Copyright 2005 MontaVista Software, Inc.
19 * Matt Porter <mporter@kernel.crashing.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 */
26
27#include <linux/types.h>
28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h>
30#include <linux/of_platform.h>
31#include <linux/slab.h>
32
33#include "fsl_rio.h"
34
35#define GET_RMM_HANDLE(mport) \
36 (((struct rio_priv *)(mport->priv))->rmm_handle)
37
38/* RapidIO definition irq, which read from OF-tree */
39#define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
40#define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
41#define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
42#define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
43
44#define RIO_MIN_TX_RING_SIZE 2
45#define RIO_MAX_TX_RING_SIZE 2048
46#define RIO_MIN_RX_RING_SIZE 2
47#define RIO_MAX_RX_RING_SIZE 2048
48
49#define RIO_IPWMR_SEN 0x00100000
50#define RIO_IPWMR_QFIE 0x00000100
51#define RIO_IPWMR_EIE 0x00000020
52#define RIO_IPWMR_CQ 0x00000002
53#define RIO_IPWMR_PWE 0x00000001
54
55#define RIO_IPWSR_QF 0x00100000
56#define RIO_IPWSR_TE 0x00000080
57#define RIO_IPWSR_QFI 0x00000010
58#define RIO_IPWSR_PWD 0x00000008
59#define RIO_IPWSR_PWB 0x00000004
60
61#define RIO_EPWISR 0x10010
62/* EPWISR Error match value */
63#define RIO_EPWISR_PINT1 0x80000000
64#define RIO_EPWISR_PINT2 0x40000000
65#define RIO_EPWISR_MU 0x00000002
66#define RIO_EPWISR_PW 0x00000001
67
68#define IPWSR_CLEAR 0x98
69#define OMSR_CLEAR 0x1cb3
70#define IMSR_CLEAR 0x491
71#define IDSR_CLEAR 0x91
72#define ODSR_CLEAR 0x1c00
73#define LTLEECSR_ENABLE_ALL 0xFFC000FC
74#define RIO_LTLEECSR 0x060c
75
76#define RIO_IM0SR 0x64
77#define RIO_IM1SR 0x164
78#define RIO_OM0SR 0x4
79#define RIO_OM1SR 0x104
80
81#define RIO_DBELL_WIN_SIZE 0x1000
82
83#define RIO_MSG_OMR_MUI 0x00000002
84#define RIO_MSG_OSR_TE 0x00000080
85#define RIO_MSG_OSR_QOI 0x00000020
86#define RIO_MSG_OSR_QFI 0x00000010
87#define RIO_MSG_OSR_MUB 0x00000004
88#define RIO_MSG_OSR_EOMI 0x00000002
89#define RIO_MSG_OSR_QEI 0x00000001
90
91#define RIO_MSG_IMR_MI 0x00000002
92#define RIO_MSG_ISR_TE 0x00000080
93#define RIO_MSG_ISR_QFI 0x00000010
94#define RIO_MSG_ISR_DIQI 0x00000001
95
96#define RIO_MSG_DESC_SIZE 32
97#define RIO_MSG_BUFFER_SIZE 4096
98
99#define DOORBELL_DMR_DI 0x00000002
100#define DOORBELL_DSR_TE 0x00000080
101#define DOORBELL_DSR_QFI 0x00000010
102#define DOORBELL_DSR_DIQI 0x00000001
103#define DOORBELL_TID_OFFSET 0x02
104#define DOORBELL_SID_OFFSET 0x04
105#define DOORBELL_INFO_OFFSET 0x06
106
107#define DOORBELL_MESSAGE_SIZE 0x08
108#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
109#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
110#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
111
112struct rio_msg_regs {
113 u32 omr;
114 u32 osr;
115 u32 pad1;
116 u32 odqdpar;
117 u32 pad2;
118 u32 osar;
119 u32 odpr;
120 u32 odatr;
121 u32 odcr;
122 u32 pad3;
123 u32 odqepar;
124 u32 pad4[13];
125 u32 imr;
126 u32 isr;
127 u32 pad5;
128 u32 ifqdpar;
129 u32 pad6;
130 u32 ifqepar;
131};
132
133struct rio_dbell_regs {
134 u32 odmr;
135 u32 odsr;
136 u32 pad1[4];
137 u32 oddpr;
138 u32 oddatr;
139 u32 pad2[3];
140 u32 odretcr;
141 u32 pad3[12];
142 u32 dmr;
143 u32 dsr;
144 u32 pad4;
145 u32 dqdpar;
146 u32 pad5;
147 u32 dqepar;
148};
149
150struct rio_pw_regs {
151 u32 pwmr;
152 u32 pwsr;
153 u32 epwqbar;
154 u32 pwqbar;
155};
156
157
158struct rio_tx_desc {
159 u32 pad1;
160 u32 saddr;
161 u32 dport;
162 u32 dattr;
163 u32 pad2;
164 u32 pad3;
165 u32 dwcnt;
166 u32 pad4;
167};
168
169struct rio_msg_tx_ring {
170 void *virt;
171 dma_addr_t phys;
172 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
173 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
174 int tx_slot;
175 int size;
176 void *dev_id;
177};
178
179struct rio_msg_rx_ring {
180 void *virt;
181 dma_addr_t phys;
182 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
183 int rx_slot;
184 int size;
185 void *dev_id;
186};
187
188struct fsl_rmu {
189 struct rio_msg_regs __iomem *msg_regs;
190 struct rio_msg_tx_ring msg_tx_ring;
191 struct rio_msg_rx_ring msg_rx_ring;
192 int txirq;
193 int rxirq;
194};
195
196/**
197 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
198 * @irq: Linux interrupt number
199 * @dev_instance: Pointer to interrupt-specific data
200 *
201 * Handles outbound message interrupts. Executes a register outbound
202 * mailbox event handler and acks the interrupt occurrence.
203 */
204static irqreturn_t
205fsl_rio_tx_handler(int irq, void *dev_instance)
206{
207 int osr;
208 struct rio_mport *port = (struct rio_mport *)dev_instance;
209 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
210
211 osr = in_be32(&rmu->msg_regs->osr);
212
213 if (osr & RIO_MSG_OSR_TE) {
214 pr_info("RIO: outbound message transmission error\n");
215 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
216 goto out;
217 }
218
219 if (osr & RIO_MSG_OSR_QOI) {
220 pr_info("RIO: outbound message queue overflow\n");
221 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
222 goto out;
223 }
224
225 if (osr & RIO_MSG_OSR_EOMI) {
226 u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
227 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
228 if (port->outb_msg[0].mcback != NULL) {
229 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id,
230 -1,
231 slot);
232 }
233 /* Ack the end-of-message interrupt */
234 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
235 }
236
237out:
238 return IRQ_HANDLED;
239}
240
241/**
242 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
243 * @irq: Linux interrupt number
244 * @dev_instance: Pointer to interrupt-specific data
245 *
246 * Handles inbound message interrupts. Executes a registered inbound
247 * mailbox event handler and acks the interrupt occurrence.
248 */
249static irqreturn_t
250fsl_rio_rx_handler(int irq, void *dev_instance)
251{
252 int isr;
253 struct rio_mport *port = (struct rio_mport *)dev_instance;
254 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
255
256 isr = in_be32(&rmu->msg_regs->isr);
257
258 if (isr & RIO_MSG_ISR_TE) {
259 pr_info("RIO: inbound message reception error\n");
260 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
261 goto out;
262 }
263
264 /* XXX Need to check/dispatch until queue empty */
265 if (isr & RIO_MSG_ISR_DIQI) {
266 /*
267 * Can receive messages for any mailbox/letter to that
268 * mailbox destination. So, make the callback with an
269 * unknown/invalid mailbox number argument.
270 */
271 if (port->inb_msg[0].mcback != NULL)
272 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id,
273 -1,
274 -1);
275
276 /* Ack the queueing interrupt */
277 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
278 }
279
280out:
281 return IRQ_HANDLED;
282}
283
284/**
285 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
286 * @irq: Linux interrupt number
287 * @dev_instance: Pointer to interrupt-specific data
288 *
289 * Handles doorbell interrupts. Parses a list of registered
290 * doorbell event handlers and executes a matching event handler.
291 */
292static irqreturn_t
293fsl_rio_dbell_handler(int irq, void *dev_instance)
294{
295 int dsr;
296 struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance;
297 int i;
298
299 dsr = in_be32(&fsl_dbell->dbell_regs->dsr);
300
301 if (dsr & DOORBELL_DSR_TE) {
302 pr_info("RIO: doorbell reception error\n");
303 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE);
304 goto out;
305 }
306
307 if (dsr & DOORBELL_DSR_QFI) {
308 pr_info("RIO: doorbell queue full\n");
309 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI);
310 }
311
312 /* XXX Need to check/dispatch until queue empty */
313 if (dsr & DOORBELL_DSR_DIQI) {
314 u32 dmsg =
315 (u32) fsl_dbell->dbell_ring.virt +
316 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
317 struct rio_dbell *dbell;
318 int found = 0;
319
320 pr_debug
321 ("RIO: processing doorbell,"
322 " sid %2.2x tid %2.2x info %4.4x\n",
323 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
324
325 for (i = 0; i < MAX_PORT_NUM; i++) {
326 if (fsl_dbell->mport[i]) {
327 list_for_each_entry(dbell,
328 &fsl_dbell->mport[i]->dbells, node) {
329 if ((dbell->res->start
330 <= DBELL_INF(dmsg))
331 && (dbell->res->end
332 >= DBELL_INF(dmsg))) {
333 found = 1;
334 break;
335 }
336 }
337 if (found && dbell->dinb) {
338 dbell->dinb(fsl_dbell->mport[i],
339 dbell->dev_id, DBELL_SID(dmsg),
340 DBELL_TID(dmsg),
341 DBELL_INF(dmsg));
342 break;
343 }
344 }
345 }
346
347 if (!found) {
348 pr_debug
349 ("RIO: spurious doorbell,"
350 " sid %2.2x tid %2.2x info %4.4x\n",
351 DBELL_SID(dmsg), DBELL_TID(dmsg),
352 DBELL_INF(dmsg));
353 }
354 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
355 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
356 }
357
358out:
359 return IRQ_HANDLED;
360}
361
362void msg_unit_error_handler(void)
363{
364
365 /*XXX: Error recovery is not implemented, we just clear errors */
366 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
367
368 out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR);
369 out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR);
370 out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR);
371 out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR);
372
373 out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR);
374 out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR);
375
376 out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR);
377}
378
379/**
380 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
381 * @irq: Linux interrupt number
382 * @dev_instance: Pointer to interrupt-specific data
383 *
384 * Handles port write interrupts. Parses a list of registered
385 * port write event handlers and executes a matching event handler.
386 */
387static irqreturn_t
388fsl_rio_port_write_handler(int irq, void *dev_instance)
389{
390 u32 ipwmr, ipwsr;
391 struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance;
392 u32 epwisr, tmp;
393
394 epwisr = in_be32(rio_regs_win + RIO_EPWISR);
395 if (!(epwisr & RIO_EPWISR_PW))
396 goto pw_done;
397
398 ipwmr = in_be32(&pw->pw_regs->pwmr);
399 ipwsr = in_be32(&pw->pw_regs->pwsr);
400
401#ifdef DEBUG_PW
402 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
403 if (ipwsr & RIO_IPWSR_QF)
404 pr_debug(" QF");
405 if (ipwsr & RIO_IPWSR_TE)
406 pr_debug(" TE");
407 if (ipwsr & RIO_IPWSR_QFI)
408 pr_debug(" QFI");
409 if (ipwsr & RIO_IPWSR_PWD)
410 pr_debug(" PWD");
411 if (ipwsr & RIO_IPWSR_PWB)
412 pr_debug(" PWB");
413 pr_debug(" )\n");
414#endif
415 /* Schedule deferred processing if PW was received */
416 if (ipwsr & RIO_IPWSR_QFI) {
417 /* Save PW message (if there is room in FIFO),
418 * otherwise discard it.
419 */
420 if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) {
421 pw->port_write_msg.msg_count++;
422 kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt,
423 RIO_PW_MSG_SIZE);
424 } else {
425 pw->port_write_msg.discard_count++;
426 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
427 pw->port_write_msg.discard_count);
428 }
429 /* Clear interrupt and issue Clear Queue command. This allows
430 * another port-write to be received.
431 */
432 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI);
433 out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
434
435 schedule_work(&pw->pw_work);
436 }
437
438 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
439 pw->port_write_msg.err_count++;
440 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
441 pw->port_write_msg.err_count);
442 /* Clear Transaction Error: port-write controller should be
443 * disabled when clearing this error
444 */
445 out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
446 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE);
447 out_be32(&pw->pw_regs->pwmr, ipwmr);
448 }
449
450 if (ipwsr & RIO_IPWSR_PWD) {
451 pw->port_write_msg.discard_count++;
452 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
453 pw->port_write_msg.discard_count);
454 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD);
455 }
456
457pw_done:
458 if (epwisr & RIO_EPWISR_PINT1) {
459 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
460 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
461 fsl_rio_port_error_handler(0);
462 }
463
464 if (epwisr & RIO_EPWISR_PINT2) {
465 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
466 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
467 fsl_rio_port_error_handler(1);
468 }
469
470 if (epwisr & RIO_EPWISR_MU) {
471 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
472 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
473 msg_unit_error_handler();
474 }
475
476 return IRQ_HANDLED;
477}
478
479static void fsl_pw_dpc(struct work_struct *work)
480{
481 struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work);
482 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
483
484 /*
485 * Process port-write messages
486 */
487 while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)msg_buffer,
488 RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) {
489 /* Process one message */
490#ifdef DEBUG_PW
491 {
492 u32 i;
493 pr_debug("%s : Port-Write Message:", __func__);
494 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
495 if ((i%4) == 0)
496 pr_debug("\n0x%02x: 0x%08x", i*4,
497 msg_buffer[i]);
498 else
499 pr_debug(" 0x%08x", msg_buffer[i]);
500 }
501 pr_debug("\n");
502 }
503#endif
504 /* Pass the port-write message to RIO core for processing */
505 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
506 }
507}
508
509/**
510 * fsl_rio_pw_enable - enable/disable port-write interface init
511 * @mport: Master port implementing the port write unit
512 * @enable: 1=enable; 0=disable port-write message handling
513 */
514int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
515{
516 u32 rval;
517
518 rval = in_be32(&pw->pw_regs->pwmr);
519
520 if (enable)
521 rval |= RIO_IPWMR_PWE;
522 else
523 rval &= ~RIO_IPWMR_PWE;
524
525 out_be32(&pw->pw_regs->pwmr, rval);
526
527 return 0;
528}
529
530/**
531 * fsl_rio_port_write_init - MPC85xx port write interface init
532 * @mport: Master port implementing the port write unit
533 *
534 * Initializes port write unit hardware and DMA buffer
535 * ring. Called from fsl_rio_setup(). Returns %0 on success
536 * or %-ENOMEM on failure.
537 */
538
539int fsl_rio_port_write_init(struct fsl_rio_pw *pw)
540{
541 int rc = 0;
542
543 /* Following configurations require a disabled port write controller */
544 out_be32(&pw->pw_regs->pwmr,
545 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE);
546
547 /* Initialize port write */
548 pw->port_write_msg.virt = dma_alloc_coherent(pw->dev,
549 RIO_PW_MSG_SIZE,
550 &pw->port_write_msg.phys, GFP_KERNEL);
551 if (!pw->port_write_msg.virt) {
552 pr_err("RIO: unable allocate port write queue\n");
553 return -ENOMEM;
554 }
555
556 pw->port_write_msg.err_count = 0;
557 pw->port_write_msg.discard_count = 0;
558
559 /* Point dequeue/enqueue pointers at first entry */
560 out_be32(&pw->pw_regs->epwqbar, 0);
561 out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys);
562
563 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
564 in_be32(&pw->pw_regs->epwqbar),
565 in_be32(&pw->pw_regs->pwqbar));
566
567 /* Clear interrupt status IPWSR */
568 out_be32(&pw->pw_regs->pwsr,
569 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
570
571 /* Configure port write contoller for snooping enable all reporting,
572 clear queue full */
573 out_be32(&pw->pw_regs->pwmr,
574 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
575
576
577 /* Hook up port-write handler */
578 rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler,
579 IRQF_SHARED, "port-write", (void *)pw);
580 if (rc < 0) {
581 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
582 goto err_out;
583 }
584 /* Enable Error Interrupt */
585 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
586
587 INIT_WORK(&pw->pw_work, fsl_pw_dpc);
588 spin_lock_init(&pw->pw_fifo_lock);
589 if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
590 pr_err("FIFO allocation failed\n");
591 rc = -ENOMEM;
592 goto err_out_irq;
593 }
594
595 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
596 in_be32(&pw->pw_regs->pwmr),
597 in_be32(&pw->pw_regs->pwsr));
598
599 return rc;
600
601err_out_irq:
602 free_irq(IRQ_RIO_PW(pw), (void *)pw);
603err_out:
604 dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE,
605 pw->port_write_msg.virt,
606 pw->port_write_msg.phys);
607 return rc;
608}
609
610/**
611 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
612 * @mport: RapidIO master port info
613 * @index: ID of RapidIO interface
614 * @destid: Destination ID of target device
615 * @data: 16-bit info field of RapidIO doorbell message
616 *
617 * Sends a MPC85xx doorbell message. Returns %0 on success or
618 * %-EINVAL on failure.
619 */
620int fsl_rio_doorbell_send(struct rio_mport *mport,
621 int index, u16 destid, u16 data)
622{
623 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
624 index, destid, data);
625
626 /* In the serial version silicons, such as MPC8548, MPC8641,
627 * below operations is must be.
628 */
629 out_be32(&dbell->dbell_regs->odmr, 0x00000000);
630 out_be32(&dbell->dbell_regs->odretcr, 0x00000004);
631 out_be32(&dbell->dbell_regs->oddpr, destid << 16);
632 out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
633 out_be32(&dbell->dbell_regs->odmr, 0x00000001);
634
635 return 0;
636}
637
638/**
639 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
640 * @mport: Master port with outbound message queue
641 * @rdev: Target of outbound message
642 * @mbox: Outbound mailbox
643 * @buffer: Message to add to outbound queue
644 * @len: Length of message
645 *
646 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
647 * %0 on success or %-EINVAL on failure.
648 */
649int
650fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
651 void *buffer, size_t len)
652{
653 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
654 u32 omr;
655 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
656 + rmu->msg_tx_ring.tx_slot;
657 int ret = 0;
658
659 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
660 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
661 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
662 ret = -EINVAL;
663 goto out;
664 }
665
666 /* Copy and clear rest of buffer */
667 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
668 len);
669 if (len < (RIO_MAX_MSG_SIZE - 4))
670 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
671 + len, 0, RIO_MAX_MSG_SIZE - len);
672
673 /* Set mbox field for message, and set destid */
674 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
675
676 /* Enable EOMI interrupt and priority */
677 desc->dattr = 0x28000000 | ((mport->index) << 20);
678
679 /* Set transfer size aligned to next power of 2 (in double words) */
680 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
681
682 /* Set snooping and source buffer address */
683 desc->saddr = 0x00000004
684 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
685
686 /* Increment enqueue pointer */
687 omr = in_be32(&rmu->msg_regs->omr);
688 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
689
690 /* Go to next descriptor */
691 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
692 rmu->msg_tx_ring.tx_slot = 0;
693
694out:
695 return ret;
696}
697
698/**
699 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
700 * @mport: Master port implementing the outbound message unit
701 * @dev_id: Device specific pointer to pass on event
702 * @mbox: Mailbox to open
703 * @entries: Number of entries in the outbound mailbox ring
704 *
705 * Initializes buffer ring, request the outbound message interrupt,
706 * and enables the outbound message unit. Returns %0 on success and
707 * %-EINVAL or %-ENOMEM on failure.
708 */
709int
710fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
711{
712 int i, j, rc = 0;
713 struct rio_priv *priv = mport->priv;
714 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
715
716 if ((entries < RIO_MIN_TX_RING_SIZE) ||
717 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
718 rc = -EINVAL;
719 goto out;
720 }
721
722 /* Initialize shadow copy ring */
723 rmu->msg_tx_ring.dev_id = dev_id;
724 rmu->msg_tx_ring.size = entries;
725
726 for (i = 0; i < rmu->msg_tx_ring.size; i++) {
727 rmu->msg_tx_ring.virt_buffer[i] =
728 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
729 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
730 if (!rmu->msg_tx_ring.virt_buffer[i]) {
731 rc = -ENOMEM;
732 for (j = 0; j < rmu->msg_tx_ring.size; j++)
733 if (rmu->msg_tx_ring.virt_buffer[j])
734 dma_free_coherent(priv->dev,
735 RIO_MSG_BUFFER_SIZE,
736 rmu->msg_tx_ring.
737 virt_buffer[j],
738 rmu->msg_tx_ring.
739 phys_buffer[j]);
740 goto out;
741 }
742 }
743
744 /* Initialize outbound message descriptor ring */
745 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
746 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
747 &rmu->msg_tx_ring.phys, GFP_KERNEL);
748 if (!rmu->msg_tx_ring.virt) {
749 rc = -ENOMEM;
750 goto out_dma;
751 }
752 memset(rmu->msg_tx_ring.virt, 0,
753 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
754 rmu->msg_tx_ring.tx_slot = 0;
755
756 /* Point dequeue/enqueue pointers at first entry in ring */
757 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
758 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
759
760 /* Configure for snooping */
761 out_be32(&rmu->msg_regs->osar, 0x00000004);
762
763 /* Clear interrupt status */
764 out_be32(&rmu->msg_regs->osr, 0x000000b3);
765
766 /* Hook up outbound message handler */
767 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
768 "msg_tx", (void *)mport);
769 if (rc < 0)
770 goto out_irq;
771
772 /*
773 * Configure outbound message unit
774 * Snooping
775 * Interrupts (all enabled, except QEIE)
776 * Chaining mode
777 * Disable
778 */
779 out_be32(&rmu->msg_regs->omr, 0x00100220);
780
781 /* Set number of entries */
782 out_be32(&rmu->msg_regs->omr,
783 in_be32(&rmu->msg_regs->omr) |
784 ((get_bitmask_order(entries) - 2) << 12));
785
786 /* Now enable the unit */
787 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
788
789out:
790 return rc;
791
792out_irq:
793 dma_free_coherent(priv->dev,
794 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
795 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
796
797out_dma:
798 for (i = 0; i < rmu->msg_tx_ring.size; i++)
799 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
800 rmu->msg_tx_ring.virt_buffer[i],
801 rmu->msg_tx_ring.phys_buffer[i]);
802
803 return rc;
804}
805
806/**
807 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
808 * @mport: Master port implementing the outbound message unit
809 * @mbox: Mailbox to close
810 *
811 * Disables the outbound message unit, free all buffers, and
812 * frees the outbound message interrupt.
813 */
814void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
815{
816 struct rio_priv *priv = mport->priv;
817 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
818
819 /* Disable inbound message unit */
820 out_be32(&rmu->msg_regs->omr, 0);
821
822 /* Free ring */
823 dma_free_coherent(priv->dev,
824 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
825 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
826
827 /* Free interrupt */
828 free_irq(IRQ_RIO_TX(mport), (void *)mport);
829}
830
831/**
832 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
833 * @mport: Master port implementing the inbound message unit
834 * @dev_id: Device specific pointer to pass on event
835 * @mbox: Mailbox to open
836 * @entries: Number of entries in the inbound mailbox ring
837 *
838 * Initializes buffer ring, request the inbound message interrupt,
839 * and enables the inbound message unit. Returns %0 on success
840 * and %-EINVAL or %-ENOMEM on failure.
841 */
842int
843fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
844{
845 int i, rc = 0;
846 struct rio_priv *priv = mport->priv;
847 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
848
849 if ((entries < RIO_MIN_RX_RING_SIZE) ||
850 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
851 rc = -EINVAL;
852 goto out;
853 }
854
855 /* Initialize client buffer ring */
856 rmu->msg_rx_ring.dev_id = dev_id;
857 rmu->msg_rx_ring.size = entries;
858 rmu->msg_rx_ring.rx_slot = 0;
859 for (i = 0; i < rmu->msg_rx_ring.size; i++)
860 rmu->msg_rx_ring.virt_buffer[i] = NULL;
861
862 /* Initialize inbound message ring */
863 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
864 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
865 &rmu->msg_rx_ring.phys, GFP_KERNEL);
866 if (!rmu->msg_rx_ring.virt) {
867 rc = -ENOMEM;
868 goto out;
869 }
870
871 /* Point dequeue/enqueue pointers at first entry in ring */
872 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
873 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
874
875 /* Clear interrupt status */
876 out_be32(&rmu->msg_regs->isr, 0x00000091);
877
878 /* Hook up inbound message handler */
879 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
880 "msg_rx", (void *)mport);
881 if (rc < 0) {
882 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
883 rmu->msg_tx_ring.virt_buffer[i],
884 rmu->msg_tx_ring.phys_buffer[i]);
885 goto out;
886 }
887
888 /*
889 * Configure inbound message unit:
890 * Snooping
891 * 4KB max message size
892 * Unmask all interrupt sources
893 * Disable
894 */
895 out_be32(&rmu->msg_regs->imr, 0x001b0060);
896
897 /* Set number of queue entries */
898 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
899
900 /* Now enable the unit */
901 setbits32(&rmu->msg_regs->imr, 0x1);
902
903out:
904 return rc;
905}
906
907/**
908 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
909 * @mport: Master port implementing the inbound message unit
910 * @mbox: Mailbox to close
911 *
912 * Disables the inbound message unit, free all buffers, and
913 * frees the inbound message interrupt.
914 */
915void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
916{
917 struct rio_priv *priv = mport->priv;
918 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
919
920 /* Disable inbound message unit */
921 out_be32(&rmu->msg_regs->imr, 0);
922
923 /* Free ring */
924 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
925 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
926
927 /* Free interrupt */
928 free_irq(IRQ_RIO_RX(mport), (void *)mport);
929}
930
931/**
932 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
933 * @mport: Master port implementing the inbound message unit
934 * @mbox: Inbound mailbox number
935 * @buf: Buffer to add to inbound queue
936 *
937 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
938 * %0 on success or %-EINVAL on failure.
939 */
940int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
941{
942 int rc = 0;
943 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
944
945 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
946 rmu->msg_rx_ring.rx_slot);
947
948 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
949 printk(KERN_ERR
950 "RIO: error adding inbound buffer %d, buffer exists\n",
951 rmu->msg_rx_ring.rx_slot);
952 rc = -EINVAL;
953 goto out;
954 }
955
956 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
957 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
958 rmu->msg_rx_ring.rx_slot = 0;
959
960out:
961 return rc;
962}
963
964/**
965 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
966 * @mport: Master port implementing the inbound message unit
967 * @mbox: Inbound mailbox number
968 *
969 * Gets the next available inbound message from the inbound message queue.
970 * A pointer to the message is returned on success or NULL on failure.
971 */
972void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
973{
974 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
975 u32 phys_buf, virt_buf;
976 void *buf = NULL;
977 int buf_idx;
978
979 phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
980
981 /* If no more messages, then bail out */
982 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
983 goto out2;
984
985 virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf
986 - rmu->msg_rx_ring.phys);
987 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
988 buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
989
990 if (!buf) {
991 printk(KERN_ERR
992 "RIO: inbound message copy failed, no buffers\n");
993 goto out1;
994 }
995
996 /* Copy max message size, caller is expected to allocate that big */
997 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
998
999 /* Clear the available buffer */
1000 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
1001
1002out1:
1003 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
1004
1005out2:
1006 return buf;
1007}
1008
1009/**
1010 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1011 * @mport: Master port implementing the inbound doorbell unit
1012 *
1013 * Initializes doorbell unit hardware and inbound DMA buffer
1014 * ring. Called from fsl_rio_setup(). Returns %0 on success
1015 * or %-ENOMEM on failure.
1016 */
1017int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell)
1018{
1019 int rc = 0;
1020
1021 /* Initialize inbound doorbells */
1022 dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 *
1023 DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL);
1024 if (!dbell->dbell_ring.virt) {
1025 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1026 rc = -ENOMEM;
1027 goto out;
1028 }
1029
1030 /* Point dequeue/enqueue pointers at first entry in ring */
1031 out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys);
1032 out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys);
1033
1034 /* Clear interrupt status */
1035 out_be32(&dbell->dbell_regs->dsr, 0x00000091);
1036
1037 /* Hook up doorbell handler */
1038 rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0,
1039 "dbell_rx", (void *)dbell);
1040 if (rc < 0) {
1041 dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE,
1042 dbell->dbell_ring.virt, dbell->dbell_ring.phys);
1043 printk(KERN_ERR
1044 "MPC85xx RIO: unable to request inbound doorbell irq");
1045 goto out;
1046 }
1047
1048 /* Configure doorbells for snooping, 512 entries, and enable */
1049 out_be32(&dbell->dbell_regs->dmr, 0x00108161);
1050
1051out:
1052 return rc;
1053}
1054
1055int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
1056{
1057 struct rio_priv *priv;
1058 struct fsl_rmu *rmu;
1059 u64 msg_start;
1060 const u32 *msg_addr;
1061 int mlen;
1062 int aw;
1063
1064 if (!mport || !mport->priv)
1065 return -EINVAL;
1066
1067 priv = mport->priv;
1068
1069 if (!node) {
1070 dev_warn(priv->dev, "Can't get %s property 'fsl,rmu'\n",
1071 priv->dev->of_node->full_name);
1072 return -EINVAL;
1073 }
1074
1075 rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
1076 if (!rmu)
1077 return -ENOMEM;
1078
1079 aw = of_n_addr_cells(node);
1080 msg_addr = of_get_property(node, "reg", &mlen);
1081 if (!msg_addr) {
1082 pr_err("%s: unable to find 'reg' property of message-unit\n",
1083 node->full_name);
1084 kfree(rmu);
1085 return -ENOMEM;
1086 }
1087 msg_start = of_read_number(msg_addr, aw);
1088
1089 rmu->msg_regs = (struct rio_msg_regs *)
1090 (rmu_regs_win + (u32)msg_start);
1091
1092 rmu->txirq = irq_of_parse_and_map(node, 0);
1093 rmu->rxirq = irq_of_parse_and_map(node, 1);
1094 printk(KERN_INFO "%s: txirq: %d, rxirq %d\n",
1095 node->full_name, rmu->txirq, rmu->rxirq);
1096
1097 priv->rmm_handle = rmu;
1098
1099 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1100 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1101 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1102
1103 return 0;
1104}
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8c7e8528e7c..4e9ccb1015d 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -154,7 +154,7 @@ static inline unsigned int mpic_processor_id(struct mpic *mpic)
154{ 154{
155 unsigned int cpu = 0; 155 unsigned int cpu = 0;
156 156
157 if (mpic->flags & MPIC_PRIMARY) 157 if (!(mpic->flags & MPIC_SECONDARY))
158 cpu = hard_smp_processor_id(); 158 cpu = hard_smp_processor_id();
159 159
160 return cpu; 160 return cpu;
@@ -315,29 +315,25 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
315} 315}
316 316
317#ifdef CONFIG_PPC_DCR 317#ifdef CONFIG_PPC_DCR
318static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, 318static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
319 struct mpic_reg_bank *rb,
320 unsigned int offset, unsigned int size) 319 unsigned int offset, unsigned int size)
321{ 320{
322 const u32 *dbasep; 321 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
323 322 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
324 dbasep = of_get_property(node, "dcr-reg", NULL);
325
326 rb->dhost = dcr_map(node, *dbasep + offset, size);
327 BUG_ON(!DCR_MAP_OK(rb->dhost)); 323 BUG_ON(!DCR_MAP_OK(rb->dhost));
328} 324}
329 325
330static inline void mpic_map(struct mpic *mpic, struct device_node *node, 326static inline void mpic_map(struct mpic *mpic,
331 phys_addr_t phys_addr, struct mpic_reg_bank *rb, 327 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
332 unsigned int offset, unsigned int size) 328 unsigned int offset, unsigned int size)
333{ 329{
334 if (mpic->flags & MPIC_USES_DCR) 330 if (mpic->flags & MPIC_USES_DCR)
335 _mpic_map_dcr(mpic, node, rb, offset, size); 331 _mpic_map_dcr(mpic, rb, offset, size);
336 else 332 else
337 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 333 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
338} 334}
339#else /* CONFIG_PPC_DCR */ 335#else /* CONFIG_PPC_DCR */
340#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 336#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
341#endif /* !CONFIG_PPC_DCR */ 337#endif /* !CONFIG_PPC_DCR */
342 338
343 339
@@ -901,7 +897,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
901 if (vold != vnew) 897 if (vold != vnew)
902 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 898 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
903 899
904 return IRQ_SET_MASK_OK_NOCOPY;; 900 return IRQ_SET_MASK_OK_NOCOPY;
905} 901}
906 902
907void mpic_set_vector(unsigned int virq, unsigned int vector) 903void mpic_set_vector(unsigned int virq, unsigned int vector)
@@ -990,7 +986,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
990 986
991#ifdef CONFIG_SMP 987#ifdef CONFIG_SMP
992 else if (hw >= mpic->ipi_vecs[0]) { 988 else if (hw >= mpic->ipi_vecs[0]) {
993 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 989 WARN_ON(mpic->flags & MPIC_SECONDARY);
994 990
995 DBG("mpic: mapping as IPI\n"); 991 DBG("mpic: mapping as IPI\n");
996 irq_set_chip_data(virq, mpic); 992 irq_set_chip_data(virq, mpic);
@@ -1001,7 +997,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
1001#endif /* CONFIG_SMP */ 997#endif /* CONFIG_SMP */
1002 998
1003 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { 999 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1004 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 1000 WARN_ON(mpic->flags & MPIC_SECONDARY);
1005 1001
1006 DBG("mpic: mapping as timer\n"); 1002 DBG("mpic: mapping as timer\n");
1007 irq_set_chip_data(virq, mpic); 1003 irq_set_chip_data(virq, mpic);
@@ -1115,17 +1111,28 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1115 return 0; 1111 return 0;
1116} 1112}
1117 1113
1114/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1115static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1116{
1117 struct irq_chip *chip = irq_desc_get_chip(desc);
1118 struct mpic *mpic = irq_desc_get_handler_data(desc);
1119 unsigned int virq;
1120
1121 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1122
1123 virq = mpic_get_one_irq(mpic);
1124 if (virq != NO_IRQ)
1125 generic_handle_irq(virq);
1126
1127 chip->irq_eoi(&desc->irq_data);
1128}
1129
1118static struct irq_host_ops mpic_host_ops = { 1130static struct irq_host_ops mpic_host_ops = {
1119 .match = mpic_host_match, 1131 .match = mpic_host_match,
1120 .map = mpic_host_map, 1132 .map = mpic_host_map,
1121 .xlate = mpic_host_xlate, 1133 .xlate = mpic_host_xlate,
1122}; 1134};
1123 1135
1124static int mpic_reset_prohibited(struct device_node *node)
1125{
1126 return node && of_get_property(node, "pic-no-reset", NULL);
1127}
1128
1129/* 1136/*
1130 * Exported functions 1137 * Exported functions
1131 */ 1138 */
@@ -1137,27 +1144,60 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1137 unsigned int irq_count, 1144 unsigned int irq_count,
1138 const char *name) 1145 const char *name)
1139{ 1146{
1140 struct mpic *mpic; 1147 int i, psize, intvec_top;
1141 u32 greg_feature; 1148 struct mpic *mpic;
1142 const char *vers; 1149 u32 greg_feature;
1143 int i; 1150 const char *vers;
1144 int intvec_top; 1151 const u32 *psrc;
1145 u64 paddr = phys_addr; 1152
1153 /* Default MPIC search parameters */
1154 static const struct of_device_id __initconst mpic_device_id[] = {
1155 { .type = "open-pic", },
1156 { .compatible = "open-pic", },
1157 {},
1158 };
1159
1160 /*
1161 * If we were not passed a device-tree node, then perform the default
1162 * search for standardized a standardized OpenPIC.
1163 */
1164 if (node) {
1165 node = of_node_get(node);
1166 } else {
1167 node = of_find_matching_node(NULL, mpic_device_id);
1168 if (!node)
1169 return NULL;
1170 }
1171
1172 /* Pick the physical address from the device tree if unspecified */
1173 if (!phys_addr) {
1174 /* Check if it is DCR-based */
1175 if (of_get_property(node, "dcr-reg", NULL)) {
1176 flags |= MPIC_USES_DCR;
1177 } else {
1178 struct resource r;
1179 if (of_address_to_resource(node, 0, &r))
1180 goto err_of_node_put;
1181 phys_addr = r.start;
1182 }
1183 }
1146 1184
1147 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1185 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1148 if (mpic == NULL) 1186 if (mpic == NULL)
1149 return NULL; 1187 goto err_of_node_put;
1150 1188
1151 mpic->name = name; 1189 mpic->name = name;
1190 mpic->node = node;
1191 mpic->paddr = phys_addr;
1152 1192
1153 mpic->hc_irq = mpic_irq_chip; 1193 mpic->hc_irq = mpic_irq_chip;
1154 mpic->hc_irq.name = name; 1194 mpic->hc_irq.name = name;
1155 if (flags & MPIC_PRIMARY) 1195 if (!(flags & MPIC_SECONDARY))
1156 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; 1196 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1157#ifdef CONFIG_MPIC_U3_HT_IRQS 1197#ifdef CONFIG_MPIC_U3_HT_IRQS
1158 mpic->hc_ht_irq = mpic_irq_ht_chip; 1198 mpic->hc_ht_irq = mpic_irq_ht_chip;
1159 mpic->hc_ht_irq.name = name; 1199 mpic->hc_ht_irq.name = name;
1160 if (flags & MPIC_PRIMARY) 1200 if (!(flags & MPIC_SECONDARY))
1161 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; 1201 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1162#endif /* CONFIG_MPIC_U3_HT_IRQS */ 1202#endif /* CONFIG_MPIC_U3_HT_IRQS */
1163 1203
@@ -1194,28 +1234,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1194 mpic->spurious_vec = intvec_top; 1234 mpic->spurious_vec = intvec_top;
1195 1235
1196 /* Check for "big-endian" in device-tree */ 1236 /* Check for "big-endian" in device-tree */
1197 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1237 if (of_get_property(mpic->node, "big-endian", NULL) != NULL)
1198 mpic->flags |= MPIC_BIG_ENDIAN; 1238 mpic->flags |= MPIC_BIG_ENDIAN;
1199 if (node && of_device_is_compatible(node, "fsl,mpic")) 1239 if (of_device_is_compatible(mpic->node, "fsl,mpic"))
1200 mpic->flags |= MPIC_FSL; 1240 mpic->flags |= MPIC_FSL;
1201 1241
1202 /* Look for protected sources */ 1242 /* Look for protected sources */
1203 if (node) { 1243 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1204 int psize; 1244 if (psrc) {
1205 unsigned int bits, mapsize; 1245 /* Allocate a bitmap with one bit per interrupt */
1206 const u32 *psrc = 1246 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1207 of_get_property(node, "protected-sources", &psize); 1247 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1208 if (psrc) { 1248 BUG_ON(mpic->protected == NULL);
1209 psize /= 4; 1249 for (i = 0; i < psize/sizeof(u32); i++) {
1210 bits = intvec_top + 1; 1250 if (psrc[i] > intvec_top)
1211 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1251 continue;
1212 mpic->protected = kzalloc(mapsize, GFP_KERNEL); 1252 __set_bit(psrc[i], mpic->protected);
1213 BUG_ON(mpic->protected == NULL);
1214 for (i = 0; i < psize; i++) {
1215 if (psrc[i] > intvec_top)
1216 continue;
1217 __set_bit(psrc[i], mpic->protected);
1218 }
1219 } 1253 }
1220 } 1254 }
1221 1255
@@ -1224,42 +1258,32 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1224#endif 1258#endif
1225 1259
1226 /* default register type */ 1260 /* default register type */
1227 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1261 if (flags & MPIC_BIG_ENDIAN)
1228 mpic_access_mmio_be : mpic_access_mmio_le; 1262 mpic->reg_type = mpic_access_mmio_be;
1229 1263 else
1230 /* If no physical address is passed in, a device-node is mandatory */ 1264 mpic->reg_type = mpic_access_mmio_le;
1231 BUG_ON(paddr == 0 && node == NULL);
1232 1265
1233 /* If no physical address passed in, check if it's dcr based */ 1266 /*
1234 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1267 * An MPIC with a "dcr-reg" property must be accessed that way, but
1268 * only if the kernel includes DCR support.
1269 */
1235#ifdef CONFIG_PPC_DCR 1270#ifdef CONFIG_PPC_DCR
1236 mpic->flags |= MPIC_USES_DCR; 1271 if (flags & MPIC_USES_DCR)
1237 mpic->reg_type = mpic_access_dcr; 1272 mpic->reg_type = mpic_access_dcr;
1238#else 1273#else
1239 BUG(); 1274 BUG_ON(flags & MPIC_USES_DCR);
1240#endif /* CONFIG_PPC_DCR */ 1275#endif
1241 }
1242
1243 /* If the MPIC is not DCR based, and no physical address was passed
1244 * in, try to obtain one
1245 */
1246 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1247 const u32 *reg = of_get_property(node, "reg", NULL);
1248 BUG_ON(reg == NULL);
1249 paddr = of_translate_address(node, reg);
1250 BUG_ON(paddr == OF_BAD_ADDR);
1251 }
1252 1276
1253 /* Map the global registers */ 1277 /* Map the global registers */
1254 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1278 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1255 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1279 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1256 1280
1257 /* Reset */ 1281 /* Reset */
1258 1282
1259 /* When using a device-node, reset requests are only honored if the MPIC 1283 /* When using a device-node, reset requests are only honored if the MPIC
1260 * is allowed to reset. 1284 * is allowed to reset.
1261 */ 1285 */
1262 if (mpic_reset_prohibited(node)) 1286 if (of_get_property(mpic->node, "pic-no-reset", NULL))
1263 mpic->flags |= MPIC_NO_RESET; 1287 mpic->flags |= MPIC_NO_RESET;
1264 1288
1265 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { 1289 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
@@ -1307,7 +1331,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1307 for_each_possible_cpu(i) { 1331 for_each_possible_cpu(i) {
1308 unsigned int cpu = get_hard_smp_processor_id(i); 1332 unsigned int cpu = get_hard_smp_processor_id(i);
1309 1333
1310 mpic_map(mpic, node, paddr, &mpic->cpuregs[cpu], 1334 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1311 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), 1335 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1312 0x1000); 1336 0x1000);
1313 } 1337 }
@@ -1315,16 +1339,21 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1315 /* Initialize main ISU if none provided */ 1339 /* Initialize main ISU if none provided */
1316 if (mpic->isu_size == 0) { 1340 if (mpic->isu_size == 0) {
1317 mpic->isu_size = mpic->num_sources; 1341 mpic->isu_size = mpic->num_sources;
1318 mpic_map(mpic, node, paddr, &mpic->isus[0], 1342 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1319 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1343 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1320 } 1344 }
1321 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1345 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1322 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1346 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1323 1347
1324 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1348 mpic->irqhost = irq_alloc_host(mpic->node, IRQ_HOST_MAP_LINEAR,
1325 isu_size ? isu_size : mpic->num_sources, 1349 isu_size ? isu_size : mpic->num_sources,
1326 &mpic_host_ops, 1350 &mpic_host_ops,
1327 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1351 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1352
1353 /*
1354 * FIXME: The code leaks the MPIC object and mappings here; this
1355 * is very unlikely to fail but it ought to be fixed anyways.
1356 */
1328 if (mpic->irqhost == NULL) 1357 if (mpic->irqhost == NULL)
1329 return NULL; 1358 return NULL;
1330 1359
@@ -1347,19 +1376,23 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1347 } 1376 }
1348 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1377 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1349 " max %d CPUs\n", 1378 " max %d CPUs\n",
1350 name, vers, (unsigned long long)paddr, num_possible_cpus()); 1379 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1351 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1380 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1352 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1381 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1353 1382
1354 mpic->next = mpics; 1383 mpic->next = mpics;
1355 mpics = mpic; 1384 mpics = mpic;
1356 1385
1357 if (flags & MPIC_PRIMARY) { 1386 if (!(flags & MPIC_SECONDARY)) {
1358 mpic_primary = mpic; 1387 mpic_primary = mpic;
1359 irq_set_default_host(mpic->irqhost); 1388 irq_set_default_host(mpic->irqhost);
1360 } 1389 }
1361 1390
1362 return mpic; 1391 return mpic;
1392
1393err_of_node_put:
1394 of_node_put(node);
1395 return NULL;
1363} 1396}
1364 1397
1365void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1398void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
@@ -1369,7 +1402,7 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1369 1402
1370 BUG_ON(isu_num >= MPIC_MAX_ISU); 1403 BUG_ON(isu_num >= MPIC_MAX_ISU);
1371 1404
1372 mpic_map(mpic, mpic->irqhost->of_node, 1405 mpic_map(mpic,
1373 paddr, &mpic->isus[isu_num], 0, 1406 paddr, &mpic->isus[isu_num], 0,
1374 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1407 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1375 1408
@@ -1385,8 +1418,7 @@ void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1385 1418
1386void __init mpic_init(struct mpic *mpic) 1419void __init mpic_init(struct mpic *mpic)
1387{ 1420{
1388 int i; 1421 int i, cpu;
1389 int cpu;
1390 1422
1391 BUG_ON(mpic->num_sources == 0); 1423 BUG_ON(mpic->num_sources == 0);
1392 1424
@@ -1424,7 +1456,7 @@ void __init mpic_init(struct mpic *mpic)
1424 1456
1425 /* Do the HT PIC fixups on U3 broken mpic */ 1457 /* Do the HT PIC fixups on U3 broken mpic */
1426 DBG("MPIC flags: %x\n", mpic->flags); 1458 DBG("MPIC flags: %x\n", mpic->flags);
1427 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1459 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1428 mpic_scan_ht_pics(mpic); 1460 mpic_scan_ht_pics(mpic);
1429 mpic_u3msi_init(mpic); 1461 mpic_u3msi_init(mpic);
1430 } 1462 }
@@ -1471,6 +1503,17 @@ void __init mpic_init(struct mpic *mpic)
1471 GFP_KERNEL); 1503 GFP_KERNEL);
1472 BUG_ON(mpic->save_data == NULL); 1504 BUG_ON(mpic->save_data == NULL);
1473#endif 1505#endif
1506
1507 /* Check if this MPIC is chained from a parent interrupt controller */
1508 if (mpic->flags & MPIC_SECONDARY) {
1509 int virq = irq_of_parse_and_map(mpic->node, 0);
1510 if (virq != NO_IRQ) {
1511 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1512 mpic->node->full_name, virq);
1513 irq_set_handler_data(virq, mpic);
1514 irq_set_chained_handler(virq, &mpic_cascade);
1515 }
1516 }
1474} 1517}
1475 1518
1476void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1519void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 862f11b3821..4f05f754234 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -185,9 +185,15 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
185 out: 185 out:
186 dma_offset_set = 1; 186 dma_offset_set = 1;
187 pci_dram_offset = res->start; 187 pci_dram_offset = res->start;
188 hose->dma_window_base_cur = res->start;
189 hose->dma_window_size = resource_size(res);
188 190
189 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", 191 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
190 pci_dram_offset); 192 pci_dram_offset);
193 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
194 (unsigned long long)hose->dma_window_base_cur);
195 printk(KERN_INFO "DMA window size 0x%016llx\n",
196 (unsigned long long)hose->dma_window_size);
191 return 0; 197 return 0;
192} 198}
193 199
@@ -647,6 +653,7 @@ static unsigned int ppc4xx_pciex_port_count;
647 653
648struct ppc4xx_pciex_hwops 654struct ppc4xx_pciex_hwops
649{ 655{
656 bool want_sdr;
650 int (*core_init)(struct device_node *np); 657 int (*core_init)(struct device_node *np);
651 int (*port_init_hw)(struct ppc4xx_pciex_port *port); 658 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
652 int (*setup_utl)(struct ppc4xx_pciex_port *port); 659 int (*setup_utl)(struct ppc4xx_pciex_port *port);
@@ -916,6 +923,7 @@ static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
916 923
917static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = 924static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
918{ 925{
926 .want_sdr = true,
919 .core_init = ppc440spe_pciex_core_init, 927 .core_init = ppc440spe_pciex_core_init,
920 .port_init_hw = ppc440speA_pciex_init_port_hw, 928 .port_init_hw = ppc440speA_pciex_init_port_hw,
921 .setup_utl = ppc440speA_pciex_init_utl, 929 .setup_utl = ppc440speA_pciex_init_utl,
@@ -924,6 +932,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
924 932
925static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 933static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
926{ 934{
935 .want_sdr = true,
927 .core_init = ppc440spe_pciex_core_init, 936 .core_init = ppc440spe_pciex_core_init,
928 .port_init_hw = ppc440speB_pciex_init_port_hw, 937 .port_init_hw = ppc440speB_pciex_init_port_hw,
929 .setup_utl = ppc440speB_pciex_init_utl, 938 .setup_utl = ppc440speB_pciex_init_utl,
@@ -1034,6 +1043,7 @@ static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1034 1043
1035static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = 1044static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1036{ 1045{
1046 .want_sdr = true,
1037 .core_init = ppc460ex_pciex_core_init, 1047 .core_init = ppc460ex_pciex_core_init,
1038 .port_init_hw = ppc460ex_pciex_init_port_hw, 1048 .port_init_hw = ppc460ex_pciex_init_port_hw,
1039 .setup_utl = ppc460ex_pciex_init_utl, 1049 .setup_utl = ppc460ex_pciex_init_utl,
@@ -1181,6 +1191,7 @@ done:
1181} 1191}
1182 1192
1183static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { 1193static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1194 .want_sdr = true,
1184 .core_init = ppc460sx_pciex_core_init, 1195 .core_init = ppc460sx_pciex_core_init,
1185 .port_init_hw = ppc460sx_pciex_init_port_hw, 1196 .port_init_hw = ppc460sx_pciex_init_port_hw,
1186 .setup_utl = ppc460sx_pciex_init_utl, 1197 .setup_utl = ppc460sx_pciex_init_utl,
@@ -1276,6 +1287,7 @@ static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1276 1287
1277static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = 1288static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1278{ 1289{
1290 .want_sdr = true,
1279 .core_init = ppc405ex_pciex_core_init, 1291 .core_init = ppc405ex_pciex_core_init,
1280 .port_init_hw = ppc405ex_pciex_init_port_hw, 1292 .port_init_hw = ppc405ex_pciex_init_port_hw,
1281 .setup_utl = ppc405ex_pciex_init_utl, 1293 .setup_utl = ppc405ex_pciex_init_utl,
@@ -1284,6 +1296,52 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1284 1296
1285#endif /* CONFIG_40x */ 1297#endif /* CONFIG_40x */
1286 1298
1299#ifdef CONFIG_476FPE
1300static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
1301{
1302 return 4;
1303}
1304
1305static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1306{
1307 u32 timeout_ms = 20;
1308 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
1309 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1310 0x1000);
1311
1312 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1313
1314 if (mbase == NULL) {
1315 printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
1316 port->index);
1317 return;
1318 }
1319
1320 while (timeout_ms--) {
1321 val = in_le32(mbase + PECFG_TLDLP);
1322
1323 if ((val & mask) == mask)
1324 break;
1325 msleep(10);
1326 }
1327
1328 if (val & PECFG_TLDLP_PRESENT) {
1329 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1330 port->link = 1;
1331 } else
1332 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1333
1334 iounmap(mbase);
1335 return;
1336}
1337
1338static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
1339{
1340 .core_init = ppc_476fpe_pciex_core_init,
1341 .check_link = ppc_476fpe_pciex_check_link,
1342};
1343#endif /* CONFIG_476FPE */
1344
1287/* Check that the core has been initied and if not, do it */ 1345/* Check that the core has been initied and if not, do it */
1288static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 1346static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1289{ 1347{
@@ -1309,6 +1367,10 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1309 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1367 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1310 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; 1368 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1311#endif 1369#endif
1370#ifdef CONFIG_476FPE
1371 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
1372 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
1373#endif
1312 if (ppc4xx_pciex_hwops == NULL) { 1374 if (ppc4xx_pciex_hwops == NULL) {
1313 printk(KERN_WARNING "PCIE: unknown host type %s\n", 1375 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1314 np->full_name); 1376 np->full_name);
@@ -1617,6 +1679,10 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1617 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 1679 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1618 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT 1680 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
1619 | DCRO_PEGPL_OMRxMSKL_VAL); 1681 | DCRO_PEGPL_OMRxMSKL_VAL);
1682 else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1683 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1684 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
1685 | DCRO_PEGPL_OMRxMSKL_VAL);
1620 else 1686 else
1621 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 1687 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1622 sa | DCRO_PEGPL_OMR1MSKL_UOT 1688 sa | DCRO_PEGPL_OMR1MSKL_UOT
@@ -1739,9 +1805,10 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1739 /* Calculate window size */ 1805 /* Calculate window size */
1740 sa = (0xffffffffffffffffull << ilog2(size)); 1806 sa = (0xffffffffffffffffull << ilog2(size));
1741 if (res->flags & IORESOURCE_PREFETCH) 1807 if (res->flags & IORESOURCE_PREFETCH)
1742 sa |= 0x8; 1808 sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1743 1809
1744 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) 1810 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1811 of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1745 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64; 1812 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
1746 1813
1747 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); 1814 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
@@ -1972,13 +2039,15 @@ static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1972 } 2039 }
1973 2040
1974 port->node = of_node_get(np); 2041 port->node = of_node_get(np);
1975 pval = of_get_property(np, "sdr-base", NULL); 2042 if (ppc4xx_pciex_hwops->want_sdr) {
1976 if (pval == NULL) { 2043 pval = of_get_property(np, "sdr-base", NULL);
1977 printk(KERN_ERR "PCIE: missing sdr-base for %s\n", 2044 if (pval == NULL) {
1978 np->full_name); 2045 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1979 return; 2046 np->full_name);
2047 return;
2048 }
2049 port->sdr_base = *pval;
1980 } 2050 }
1981 port->sdr_base = *pval;
1982 2051
1983 /* Check if device_type property is set to "pci" or "pci-endpoint". 2052 /* Check if device_type property is set to "pci" or "pci-endpoint".
1984 * Resulting from this setup this PCIe port will be configured 2053 * Resulting from this setup this PCIe port will be configured
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 32ce763a375..bb4821938ab 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -476,6 +476,13 @@
476#define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002 476#define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002
477#define DCRO_PEGPL_OMR3MSKL_IO 0x00000002 477#define DCRO_PEGPL_OMR3MSKL_IO 0x00000002
478 478
479/* 476FPE */
480#define PCCFG_LCPA 0x270
481#define PECFG_TLDLP 0x3F8
482#define PECFG_TLDLP_LNKUP 0x00000008
483#define PECFG_TLDLP_PRESENT 0x00000010
484#define DCRO_PEGPL_476FPE_OMR1MSKL_UOT 0x00000004
485
479/* SDR Bit Mappings */ 486/* SDR Bit Mappings */
480#define PESDRx_RCSSET_HLDPLB 0x10000000 487#define PESDRx_RCSSET_HLDPLB 0x10000000
481#define PESDRx_RCSSET_RSTGU 0x01000000 488#define PESDRx_RCSSET_RSTGU 0x01000000
diff --git a/arch/powerpc/sysdev/xics/icp-hv.c b/arch/powerpc/sysdev/xics/icp-hv.c
index 9518d367a64..253dce98c16 100644
--- a/arch/powerpc/sysdev/xics/icp-hv.c
+++ b/arch/powerpc/sysdev/xics/icp-hv.c
@@ -27,33 +27,50 @@ static inline unsigned int icp_hv_get_xirr(unsigned char cppr)
27{ 27{
28 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 28 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
29 long rc; 29 long rc;
30 unsigned int ret = XICS_IRQ_SPURIOUS;
30 31
31 rc = plpar_hcall(H_XIRR, retbuf, cppr); 32 rc = plpar_hcall(H_XIRR, retbuf, cppr);
32 if (rc != H_SUCCESS) 33 if (rc == H_SUCCESS) {
33 panic(" bad return code xirr - rc = %lx\n", rc); 34 ret = (unsigned int)retbuf[0];
34 return (unsigned int)retbuf[0]; 35 } else {
35} 36 pr_err("%s: bad return code xirr cppr=0x%x returned %ld\n",
37 __func__, cppr, rc);
38 WARN_ON_ONCE(1);
39 }
36 40
37static inline void icp_hv_set_xirr(unsigned int value) 41 return ret;
38{
39 long rc = plpar_hcall_norets(H_EOI, value);
40 if (rc != H_SUCCESS)
41 panic("bad return code EOI - rc = %ld, value=%x\n", rc, value);
42} 42}
43 43
44static inline void icp_hv_set_cppr(u8 value) 44static inline void icp_hv_set_cppr(u8 value)
45{ 45{
46 long rc = plpar_hcall_norets(H_CPPR, value); 46 long rc = plpar_hcall_norets(H_CPPR, value);
47 if (rc != H_SUCCESS) 47 if (rc != H_SUCCESS) {
48 panic("bad return code cppr - rc = %lx\n", rc); 48 pr_err("%s: bad return code cppr cppr=0x%x returned %ld\n",
49 __func__, value, rc);
50 WARN_ON_ONCE(1);
51 }
52}
53
54static inline void icp_hv_set_xirr(unsigned int value)
55{
56 long rc = plpar_hcall_norets(H_EOI, value);
57 if (rc != H_SUCCESS) {
58 pr_err("%s: bad return code eoi xirr=0x%x returned %ld\n",
59 __func__, value, rc);
60 WARN_ON_ONCE(1);
61 icp_hv_set_cppr(value >> 24);
62 }
49} 63}
50 64
51static inline void icp_hv_set_qirr(int n_cpu , u8 value) 65static inline void icp_hv_set_qirr(int n_cpu , u8 value)
52{ 66{
53 long rc = plpar_hcall_norets(H_IPI, get_hard_smp_processor_id(n_cpu), 67 int hw_cpu = get_hard_smp_processor_id(n_cpu);
54 value); 68 long rc = plpar_hcall_norets(H_IPI, hw_cpu, value);
55 if (rc != H_SUCCESS) 69 if (rc != H_SUCCESS) {
56 panic("bad return code qirr - rc = %lx\n", rc); 70 pr_err("%s: bad return code qirr cpu=%d hw_cpu=%d mfrr=0x%x "
71 "returned %ld\n", __func__, n_cpu, hw_cpu, value, rc);
72 WARN_ON_ONCE(1);
73 }
57} 74}
58 75
59static void icp_hv_eoi(struct irq_data *d) 76static void icp_hv_eoi(struct irq_data *d)
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index 63762c672a0..d72eda6a4c0 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -137,7 +137,7 @@ static void xics_request_ipi(void)
137 * IPIs are marked IRQF_PERCPU. The handler was set in map. 137 * IPIs are marked IRQF_PERCPU. The handler was set in map.
138 */ 138 */
139 BUG_ON(request_irq(ipi, icp_ops->ipi_action, 139 BUG_ON(request_irq(ipi, icp_ops->ipi_action,
140 IRQF_PERCPU, "IPI", NULL)); 140 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
141} 141}
142 142
143int __init xics_smp_probe(void) 143int __init xics_smp_probe(void)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 03a217ae3be..cb95eea74d3 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -228,13 +228,11 @@ Commands:\n\
228 t print backtrace\n\ 228 t print backtrace\n\
229 x exit monitor and recover\n\ 229 x exit monitor and recover\n\
230 X exit monitor and dont recover\n" 230 X exit monitor and dont recover\n"
231#ifdef CONFIG_PPC64 231#if defined(CONFIG_PPC64) && !defined(CONFIG_PPC_BOOK3E)
232" u dump segment table or SLB\n" 232" u dump segment table or SLB\n"
233#endif 233#elif defined(CONFIG_PPC_STD_MMU_32)
234#ifdef CONFIG_PPC_STD_MMU_32
235" u dump segment registers\n" 234" u dump segment registers\n"
236#endif 235#elif defined(CONFIG_44x) || defined(CONFIG_PPC_BOOK3E)
237#ifdef CONFIG_44x
238" u dump TLB\n" 236" u dump TLB\n"
239#endif 237#endif
240" ? help\n" 238" ? help\n"
@@ -340,7 +338,7 @@ int cpus_are_in_xmon(void)
340 338
341static inline int unrecoverable_excp(struct pt_regs *regs) 339static inline int unrecoverable_excp(struct pt_regs *regs)
342{ 340{
343#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E) 341#if defined(CONFIG_4xx) || defined(CONFIG_PPC_BOOK3E)
344 /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */ 342 /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
345 return 0; 343 return 0;
346#else 344#else
@@ -885,13 +883,11 @@ cmds(struct pt_regs *excp)
885 case 'u': 883 case 'u':
886 dump_segments(); 884 dump_segments();
887 break; 885 break;
888#endif 886#elif defined(CONFIG_4xx)
889#ifdef CONFIG_4xx
890 case 'u': 887 case 'u':
891 dump_tlb_44x(); 888 dump_tlb_44x();
892 break; 889 break;
893#endif 890#elif defined(CONFIG_PPC_BOOK3E)
894#ifdef CONFIG_PPC_BOOK3E
895 case 'u': 891 case 'u':
896 dump_tlb_book3e(); 892 dump_tlb_book3e();
897 break; 893 break;
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 441521ad8a3..232df994953 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -368,11 +368,11 @@ static unsigned long mmap_rnd(void)
368 if (current->flags & PF_RANDOMIZE) { 368 if (current->flags & PF_RANDOMIZE) {
369 unsigned long val = get_random_int(); 369 unsigned long val = get_random_int();
370 if (test_thread_flag(TIF_32BIT)) 370 if (test_thread_flag(TIF_32BIT))
371 rnd = (val % (1UL << (22UL-PAGE_SHIFT))); 371 rnd = (val % (1UL << (23UL-PAGE_SHIFT)));
372 else 372 else
373 rnd = (val % (1UL << (29UL-PAGE_SHIFT))); 373 rnd = (val % (1UL << (30UL-PAGE_SHIFT)));
374 } 374 }
375 return (rnd << PAGE_SHIFT) * 2; 375 return rnd << PAGE_SHIFT;
376} 376}
377 377
378void arch_pick_mmap_layout(struct mm_struct *mm) 378void arch_pick_mmap_layout(struct mm_struct *mm)
diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c
index 7bf1e201578..5ee82a77723 100644
--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c
+++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c
@@ -640,7 +640,7 @@ static inline void gelic_card_disable_rxdmac(struct gelic_card *card)
640 int status; 640 int status;
641 641
642 /* this hvc blocks until the DMA in progress really stopped */ 642 /* this hvc blocks until the DMA in progress really stopped */
643 status = lv1_net_stop_rx_dma(bus_id(card), dev_id(card), 0); 643 status = lv1_net_stop_rx_dma(bus_id(card), dev_id(card));
644 if (status) 644 if (status)
645 dev_err(ctodev(card), 645 dev_err(ctodev(card),
646 "lv1_net_stop_rx_dma failed, %d\n", status); 646 "lv1_net_stop_rx_dma failed, %d\n", status);
@@ -658,7 +658,7 @@ static inline void gelic_card_disable_txdmac(struct gelic_card *card)
658 int status; 658 int status;
659 659
660 /* this hvc blocks until the DMA in progress really stopped */ 660 /* this hvc blocks until the DMA in progress really stopped */
661 status = lv1_net_stop_tx_dma(bus_id(card), dev_id(card), 0); 661 status = lv1_net_stop_tx_dma(bus_id(card), dev_id(card));
662 if (status) 662 if (status)
663 dev_err(ctodev(card), 663 dev_err(ctodev(card),
664 "lv1_net_stop_tx_dma failed, status=%d\n", status); 664 "lv1_net_stop_tx_dma failed, status=%d\n", status);
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
index 5acd24a27d0..e9c2dfe471a 100644
--- a/drivers/tty/serial/pmac_zilog.c
+++ b/drivers/tty/serial/pmac_zilog.c
@@ -99,6 +99,9 @@ MODULE_LICENSE("GPL");
99#define PMACZILOG_NAME "ttyPZ" 99#define PMACZILOG_NAME "ttyPZ"
100#endif 100#endif
101 101
102#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
103#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
104#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
102 105
103/* 106/*
104 * For the sake of early serial console, we can do a pre-probe 107 * For the sake of early serial console, we can do a pre-probe
@@ -106,7 +109,6 @@ MODULE_LICENSE("GPL");
106 */ 109 */
107static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 110static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
108static int pmz_ports_count; 111static int pmz_ports_count;
109static DEFINE_MUTEX(pmz_irq_mutex);
110 112
111static struct uart_driver pmz_uart_reg = { 113static struct uart_driver pmz_uart_reg = {
112 .owner = THIS_MODULE, 114 .owner = THIS_MODULE,
@@ -126,9 +128,6 @@ static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
126{ 128{
127 int i; 129 int i;
128 130
129 if (ZS_IS_ASLEEP(uap))
130 return;
131
132 /* Let pending transmits finish. */ 131 /* Let pending transmits finish. */
133 for (i = 0; i < 1000; i++) { 132 for (i = 0; i < 1000; i++) {
134 unsigned char stat = read_zsreg(uap, R1); 133 unsigned char stat = read_zsreg(uap, R1);
@@ -216,32 +215,24 @@ static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
216 } 215 }
217} 216}
218 217
218static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
219{
220 if (enable) {
221 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
222 if (!ZS_IS_EXTCLK(uap))
223 uap->curregs[1] |= EXT_INT_ENAB;
224 } else {
225 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
226 }
227 write_zsreg(uap, R1, uap->curregs[1]);
228}
229
219static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) 230static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
220{ 231{
221 struct tty_struct *tty = NULL; 232 struct tty_struct *tty = NULL;
222 unsigned char ch, r1, drop, error, flag; 233 unsigned char ch, r1, drop, error, flag;
223 int loops = 0; 234 int loops = 0;
224 235
225 /* The interrupt can be enabled when the port isn't open, typically
226 * that happens when using one port is open and the other closed (stale
227 * interrupt) or when one port is used as a console.
228 */
229 if (!ZS_IS_OPEN(uap)) {
230 pmz_debug("pmz: draining input\n");
231 /* Port is closed, drain input data */
232 for (;;) {
233 if ((++loops) > 1000)
234 goto flood;
235 (void)read_zsreg(uap, R1);
236 write_zsreg(uap, R0, ERR_RES);
237 (void)read_zsdata(uap);
238 ch = read_zsreg(uap, R0);
239 if (!(ch & Rx_CH_AV))
240 break;
241 }
242 return NULL;
243 }
244
245 /* Sanity check, make sure the old bug is no longer happening */ 236 /* Sanity check, make sure the old bug is no longer happening */
246 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) { 237 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
247 WARN_ON(1); 238 WARN_ON(1);
@@ -339,9 +330,7 @@ static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
339 330
340 return tty; 331 return tty;
341 flood: 332 flood:
342 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 333 pmz_interrupt_control(uap, 0);
343 write_zsreg(uap, R1, uap->curregs[R1]);
344 zssync(uap);
345 pmz_error("pmz: rx irq flood !\n"); 334 pmz_error("pmz: rx irq flood !\n");
346 return tty; 335 return tty;
347} 336}
@@ -383,8 +372,6 @@ static void pmz_transmit_chars(struct uart_pmac_port *uap)
383{ 372{
384 struct circ_buf *xmit; 373 struct circ_buf *xmit;
385 374
386 if (ZS_IS_ASLEEP(uap))
387 return;
388 if (ZS_IS_CONS(uap)) { 375 if (ZS_IS_CONS(uap)) {
389 unsigned char status = read_zsreg(uap, R0); 376 unsigned char status = read_zsreg(uap, R0);
390 377
@@ -481,6 +468,10 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
481 /* Channel A */ 468 /* Channel A */
482 tty = NULL; 469 tty = NULL;
483 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 470 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
471 if (!ZS_IS_OPEN(uap_a)) {
472 pmz_debug("ChanA interrupt while open !\n");
473 goto skip_a;
474 }
484 write_zsreg(uap_a, R0, RES_H_IUS); 475 write_zsreg(uap_a, R0, RES_H_IUS);
485 zssync(uap_a); 476 zssync(uap_a);
486 if (r3 & CHAEXT) 477 if (r3 & CHAEXT)
@@ -491,16 +482,21 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
491 pmz_transmit_chars(uap_a); 482 pmz_transmit_chars(uap_a);
492 rc = IRQ_HANDLED; 483 rc = IRQ_HANDLED;
493 } 484 }
485 skip_a:
494 spin_unlock(&uap_a->port.lock); 486 spin_unlock(&uap_a->port.lock);
495 if (tty != NULL) 487 if (tty != NULL)
496 tty_flip_buffer_push(tty); 488 tty_flip_buffer_push(tty);
497 489
498 if (uap_b->node == NULL) 490 if (!uap_b)
499 goto out; 491 goto out;
500 492
501 spin_lock(&uap_b->port.lock); 493 spin_lock(&uap_b->port.lock);
502 tty = NULL; 494 tty = NULL;
503 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 495 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
496 if (!ZS_IS_OPEN(uap_a)) {
497 pmz_debug("ChanB interrupt while open !\n");
498 goto skip_b;
499 }
504 write_zsreg(uap_b, R0, RES_H_IUS); 500 write_zsreg(uap_b, R0, RES_H_IUS);
505 zssync(uap_b); 501 zssync(uap_b);
506 if (r3 & CHBEXT) 502 if (r3 & CHBEXT)
@@ -511,14 +507,12 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
511 pmz_transmit_chars(uap_b); 507 pmz_transmit_chars(uap_b);
512 rc = IRQ_HANDLED; 508 rc = IRQ_HANDLED;
513 } 509 }
510 skip_b:
514 spin_unlock(&uap_b->port.lock); 511 spin_unlock(&uap_b->port.lock);
515 if (tty != NULL) 512 if (tty != NULL)
516 tty_flip_buffer_push(tty); 513 tty_flip_buffer_push(tty);
517 514
518 out: 515 out:
519#ifdef DEBUG_HARD
520 pmz_debug("irq done.\n");
521#endif
522 return rc; 516 return rc;
523} 517}
524 518
@@ -543,12 +537,8 @@ static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
543 */ 537 */
544static unsigned int pmz_tx_empty(struct uart_port *port) 538static unsigned int pmz_tx_empty(struct uart_port *port)
545{ 539{
546 struct uart_pmac_port *uap = to_pmz(port);
547 unsigned char status; 540 unsigned char status;
548 541
549 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
550 return TIOCSER_TEMT;
551
552 status = pmz_peek_status(to_pmz(port)); 542 status = pmz_peek_status(to_pmz(port));
553 if (status & Tx_BUF_EMP) 543 if (status & Tx_BUF_EMP)
554 return TIOCSER_TEMT; 544 return TIOCSER_TEMT;
@@ -570,8 +560,7 @@ static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
570 if (ZS_IS_IRDA(uap)) 560 if (ZS_IS_IRDA(uap))
571 return; 561 return;
572 /* We get called during boot with a port not up yet */ 562 /* We get called during boot with a port not up yet */
573 if (ZS_IS_ASLEEP(uap) || 563 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
574 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
575 return; 564 return;
576 565
577 set_bits = clear_bits = 0; 566 set_bits = clear_bits = 0;
@@ -590,8 +579,7 @@ static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
590 /* NOTE: Not subject to 'transmitter active' rule. */ 579 /* NOTE: Not subject to 'transmitter active' rule. */
591 uap->curregs[R5] |= set_bits; 580 uap->curregs[R5] |= set_bits;
592 uap->curregs[R5] &= ~clear_bits; 581 uap->curregs[R5] &= ~clear_bits;
593 if (ZS_IS_ASLEEP(uap)) 582
594 return;
595 write_zsreg(uap, R5, uap->curregs[R5]); 583 write_zsreg(uap, R5, uap->curregs[R5]);
596 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 584 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
597 set_bits, clear_bits, uap->curregs[R5]); 585 set_bits, clear_bits, uap->curregs[R5]);
@@ -609,9 +597,6 @@ static unsigned int pmz_get_mctrl(struct uart_port *port)
609 unsigned char status; 597 unsigned char status;
610 unsigned int ret; 598 unsigned int ret;
611 599
612 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
613 return 0;
614
615 status = read_zsreg(uap, R0); 600 status = read_zsreg(uap, R0);
616 601
617 ret = 0; 602 ret = 0;
@@ -649,9 +634,6 @@ static void pmz_start_tx(struct uart_port *port)
649 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 634 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
650 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 635 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
651 636
652 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
653 return;
654
655 status = read_zsreg(uap, R0); 637 status = read_zsreg(uap, R0);
656 638
657 /* TX busy? Just wait for the TX done interrupt. */ 639 /* TX busy? Just wait for the TX done interrupt. */
@@ -690,9 +672,6 @@ static void pmz_stop_rx(struct uart_port *port)
690{ 672{
691 struct uart_pmac_port *uap = to_pmz(port); 673 struct uart_pmac_port *uap = to_pmz(port);
692 674
693 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
694 return;
695
696 pmz_debug("pmz: stop_rx()()\n"); 675 pmz_debug("pmz: stop_rx()()\n");
697 676
698 /* Disable all RX interrupts. */ 677 /* Disable all RX interrupts. */
@@ -711,14 +690,12 @@ static void pmz_enable_ms(struct uart_port *port)
711 struct uart_pmac_port *uap = to_pmz(port); 690 struct uart_pmac_port *uap = to_pmz(port);
712 unsigned char new_reg; 691 unsigned char new_reg;
713 692
714 if (ZS_IS_IRDA(uap) || uap->node == NULL) 693 if (ZS_IS_IRDA(uap))
715 return; 694 return;
716 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 695 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
717 if (new_reg != uap->curregs[R15]) { 696 if (new_reg != uap->curregs[R15]) {
718 uap->curregs[R15] = new_reg; 697 uap->curregs[R15] = new_reg;
719 698
720 if (ZS_IS_ASLEEP(uap))
721 return;
722 /* NOTE: Not subject to 'transmitter active' rule. */ 699 /* NOTE: Not subject to 'transmitter active' rule. */
723 write_zsreg(uap, R15, uap->curregs[R15]); 700 write_zsreg(uap, R15, uap->curregs[R15]);
724 } 701 }
@@ -734,8 +711,6 @@ static void pmz_break_ctl(struct uart_port *port, int break_state)
734 unsigned char set_bits, clear_bits, new_reg; 711 unsigned char set_bits, clear_bits, new_reg;
735 unsigned long flags; 712 unsigned long flags;
736 713
737 if (uap->node == NULL)
738 return;
739 set_bits = clear_bits = 0; 714 set_bits = clear_bits = 0;
740 715
741 if (break_state) 716 if (break_state)
@@ -748,12 +723,6 @@ static void pmz_break_ctl(struct uart_port *port, int break_state)
748 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 723 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
749 if (new_reg != uap->curregs[R5]) { 724 if (new_reg != uap->curregs[R5]) {
750 uap->curregs[R5] = new_reg; 725 uap->curregs[R5] = new_reg;
751
752 /* NOTE: Not subject to 'transmitter active' rule. */
753 if (ZS_IS_ASLEEP(uap)) {
754 spin_unlock_irqrestore(&port->lock, flags);
755 return;
756 }
757 write_zsreg(uap, R5, uap->curregs[R5]); 726 write_zsreg(uap, R5, uap->curregs[R5]);
758 } 727 }
759 728
@@ -927,14 +896,21 @@ static int __pmz_startup(struct uart_pmac_port *uap)
927 896
928static void pmz_irda_reset(struct uart_pmac_port *uap) 897static void pmz_irda_reset(struct uart_pmac_port *uap)
929{ 898{
899 unsigned long flags;
900
901 spin_lock_irqsave(&uap->port.lock, flags);
930 uap->curregs[R5] |= DTR; 902 uap->curregs[R5] |= DTR;
931 write_zsreg(uap, R5, uap->curregs[R5]); 903 write_zsreg(uap, R5, uap->curregs[R5]);
932 zssync(uap); 904 zssync(uap);
933 mdelay(110); 905 spin_unlock_irqrestore(&uap->port.lock, flags);
906 msleep(110);
907
908 spin_lock_irqsave(&uap->port.lock, flags);
934 uap->curregs[R5] &= ~DTR; 909 uap->curregs[R5] &= ~DTR;
935 write_zsreg(uap, R5, uap->curregs[R5]); 910 write_zsreg(uap, R5, uap->curregs[R5]);
936 zssync(uap); 911 zssync(uap);
937 mdelay(10); 912 spin_unlock_irqrestore(&uap->port.lock, flags);
913 msleep(10);
938} 914}
939 915
940/* 916/*
@@ -949,13 +925,6 @@ static int pmz_startup(struct uart_port *port)
949 925
950 pmz_debug("pmz: startup()\n"); 926 pmz_debug("pmz: startup()\n");
951 927
952 if (ZS_IS_ASLEEP(uap))
953 return -EAGAIN;
954 if (uap->node == NULL)
955 return -ENODEV;
956
957 mutex_lock(&pmz_irq_mutex);
958
959 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 928 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
960 929
961 /* A console is never powered down. Else, power up and 930 /* A console is never powered down. Else, power up and
@@ -966,18 +935,14 @@ static int pmz_startup(struct uart_port *port)
966 pwr_delay = __pmz_startup(uap); 935 pwr_delay = __pmz_startup(uap);
967 spin_unlock_irqrestore(&port->lock, flags); 936 spin_unlock_irqrestore(&port->lock, flags);
968 } 937 }
969 938 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
970 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
971 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 939 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
972 "SCC", uap)) { 940 uap->irq_name, uap)) {
973 pmz_error("Unable to register zs interrupt handler.\n"); 941 pmz_error("Unable to register zs interrupt handler.\n");
974 pmz_set_scc_power(uap, 0); 942 pmz_set_scc_power(uap, 0);
975 mutex_unlock(&pmz_irq_mutex);
976 return -ENXIO; 943 return -ENXIO;
977 } 944 }
978 945
979 mutex_unlock(&pmz_irq_mutex);
980
981 /* Right now, we deal with delay by blocking here, I'll be 946 /* Right now, we deal with delay by blocking here, I'll be
982 * smarter later on 947 * smarter later on
983 */ 948 */
@@ -990,12 +955,9 @@ static int pmz_startup(struct uart_port *port)
990 if (ZS_IS_IRDA(uap)) 955 if (ZS_IS_IRDA(uap))
991 pmz_irda_reset(uap); 956 pmz_irda_reset(uap);
992 957
993 /* Enable interrupts emission from the chip */ 958 /* Enable interrupt requests for the channel */
994 spin_lock_irqsave(&port->lock, flags); 959 spin_lock_irqsave(&port->lock, flags);
995 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 960 pmz_interrupt_control(uap, 1);
996 if (!ZS_IS_EXTCLK(uap))
997 uap->curregs[R1] |= EXT_INT_ENAB;
998 write_zsreg(uap, R1, uap->curregs[R1]);
999 spin_unlock_irqrestore(&port->lock, flags); 961 spin_unlock_irqrestore(&port->lock, flags);
1000 962
1001 pmz_debug("pmz: startup() done.\n"); 963 pmz_debug("pmz: startup() done.\n");
@@ -1010,49 +972,35 @@ static void pmz_shutdown(struct uart_port *port)
1010 972
1011 pmz_debug("pmz: shutdown()\n"); 973 pmz_debug("pmz: shutdown()\n");
1012 974
1013 if (uap->node == NULL)
1014 return;
1015
1016 mutex_lock(&pmz_irq_mutex);
1017
1018 /* Release interrupt handler */
1019 free_irq(uap->port.irq, uap);
1020
1021 spin_lock_irqsave(&port->lock, flags); 975 spin_lock_irqsave(&port->lock, flags);
1022 976
1023 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 977 /* Disable interrupt requests for the channel */
978 pmz_interrupt_control(uap, 0);
1024 979
1025 if (!ZS_IS_OPEN(uap->mate)) 980 if (!ZS_IS_CONS(uap)) {
1026 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 981 /* Disable receiver and transmitter */
982 uap->curregs[R3] &= ~RxENABLE;
983 uap->curregs[R5] &= ~TxENABLE;
1027 984
1028 /* Disable interrupts */ 985 /* Disable break assertion */
1029 if (!ZS_IS_ASLEEP(uap)) { 986 uap->curregs[R5] &= ~SND_BRK;
1030 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 987 pmz_maybe_update_regs(uap);
1031 write_zsreg(uap, R1, uap->curregs[R1]);
1032 zssync(uap);
1033 } 988 }
1034 989
1035 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { 990 spin_unlock_irqrestore(&port->lock, flags);
1036 spin_unlock_irqrestore(&port->lock, flags); 991
1037 mutex_unlock(&pmz_irq_mutex); 992 /* Release interrupt handler */
1038 return; 993 free_irq(uap->port.irq, uap);
1039 }
1040 994
1041 /* Disable receiver and transmitter. */ 995 spin_lock_irqsave(&port->lock, flags);
1042 uap->curregs[R3] &= ~RxENABLE;
1043 uap->curregs[R5] &= ~TxENABLE;
1044 996
1045 /* Disable all interrupts and BRK assertion. */ 997 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1046 uap->curregs[R5] &= ~SND_BRK;
1047 pmz_maybe_update_regs(uap);
1048 998
1049 /* Shut the chip down */ 999 if (!ZS_IS_CONS(uap))
1050 pmz_set_scc_power(uap, 0); 1000 pmz_set_scc_power(uap, 0); /* Shut the chip down */
1051 1001
1052 spin_unlock_irqrestore(&port->lock, flags); 1002 spin_unlock_irqrestore(&port->lock, flags);
1053 1003
1054 mutex_unlock(&pmz_irq_mutex);
1055
1056 pmz_debug("pmz: shutdown() done.\n"); 1004 pmz_debug("pmz: shutdown() done.\n");
1057} 1005}
1058 1006
@@ -1300,9 +1248,6 @@ static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1300 1248
1301 pmz_debug("pmz: set_termios()\n"); 1249 pmz_debug("pmz: set_termios()\n");
1302 1250
1303 if (ZS_IS_ASLEEP(uap))
1304 return;
1305
1306 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1251 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1307 1252
1308 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds 1253 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
@@ -1352,19 +1297,15 @@ static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1352 spin_lock_irqsave(&port->lock, flags); 1297 spin_lock_irqsave(&port->lock, flags);
1353 1298
1354 /* Disable IRQs on the port */ 1299 /* Disable IRQs on the port */
1355 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1300 pmz_interrupt_control(uap, 0);
1356 write_zsreg(uap, R1, uap->curregs[R1]);
1357 1301
1358 /* Setup new port configuration */ 1302 /* Setup new port configuration */
1359 __pmz_set_termios(port, termios, old); 1303 __pmz_set_termios(port, termios, old);
1360 1304
1361 /* Re-enable IRQs on the port */ 1305 /* Re-enable IRQs on the port */
1362 if (ZS_IS_OPEN(uap)) { 1306 if (ZS_IS_OPEN(uap))
1363 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1307 pmz_interrupt_control(uap, 1);
1364 if (!ZS_IS_EXTCLK(uap)) 1308
1365 uap->curregs[R1] |= EXT_INT_ENAB;
1366 write_zsreg(uap, R1, uap->curregs[R1]);
1367 }
1368 spin_unlock_irqrestore(&port->lock, flags); 1309 spin_unlock_irqrestore(&port->lock, flags);
1369} 1310}
1370 1311
@@ -1604,25 +1545,34 @@ static void pmz_dispose_port(struct uart_pmac_port *uap)
1604 */ 1545 */
1605static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1546static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1606{ 1547{
1548 struct uart_pmac_port *uap;
1607 int i; 1549 int i;
1608 1550
1609 /* Iterate the pmz_ports array to find a matching entry 1551 /* Iterate the pmz_ports array to find a matching entry
1610 */ 1552 */
1611 for (i = 0; i < MAX_ZS_PORTS; i++) 1553 for (i = 0; i < MAX_ZS_PORTS; i++)
1612 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) { 1554 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1613 struct uart_pmac_port *uap = &pmz_ports[i]; 1555 break;
1614 1556 if (i >= MAX_ZS_PORTS)
1615 uap->dev = mdev; 1557 return -ENODEV;
1616 dev_set_drvdata(&mdev->ofdev.dev, uap); 1558
1617 if (macio_request_resources(uap->dev, "pmac_zilog")) 1559
1618 printk(KERN_WARNING "%s: Failed to request resource" 1560 uap = &pmz_ports[i];
1619 ", port still active\n", 1561 uap->dev = mdev;
1620 uap->node->name); 1562 uap->port.dev = &mdev->ofdev.dev;
1621 else 1563 dev_set_drvdata(&mdev->ofdev.dev, uap);
1622 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1564
1623 return 0; 1565 /* We still activate the port even when failing to request resources
1624 } 1566 * to work around bugs in ancient Apple device-trees
1625 return -ENODEV; 1567 */
1568 if (macio_request_resources(uap->dev, "pmac_zilog"))
1569 printk(KERN_WARNING "%s: Failed to request resource"
1570 ", port still active\n",
1571 uap->node->name);
1572 else
1573 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1574
1575 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1626} 1576}
1627 1577
1628/* 1578/*
@@ -1636,12 +1586,15 @@ static int pmz_detach(struct macio_dev *mdev)
1636 if (!uap) 1586 if (!uap)
1637 return -ENODEV; 1587 return -ENODEV;
1638 1588
1589 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1590
1639 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1591 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1640 macio_release_resources(uap->dev); 1592 macio_release_resources(uap->dev);
1641 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1593 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1642 } 1594 }
1643 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1595 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1644 uap->dev = NULL; 1596 uap->dev = NULL;
1597 uap->port.dev = NULL;
1645 1598
1646 return 0; 1599 return 0;
1647} 1600}
@@ -1650,59 +1603,13 @@ static int pmz_detach(struct macio_dev *mdev)
1650static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1603static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1651{ 1604{
1652 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1605 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1653 struct uart_state *state;
1654 unsigned long flags;
1655 1606
1656 if (uap == NULL) { 1607 if (uap == NULL) {
1657 printk("HRM... pmz_suspend with NULL uap\n"); 1608 printk("HRM... pmz_suspend with NULL uap\n");
1658 return 0; 1609 return 0;
1659 } 1610 }
1660 1611
1661 if (pm_state.event == mdev->ofdev.dev.power.power_state.event) 1612 uart_suspend_port(&pmz_uart_reg, &uap->port);
1662 return 0;
1663
1664 pmz_debug("suspend, switching to state %d\n", pm_state.event);
1665
1666 state = pmz_uart_reg.state + uap->port.line;
1667
1668 mutex_lock(&pmz_irq_mutex);
1669 mutex_lock(&state->port.mutex);
1670
1671 spin_lock_irqsave(&uap->port.lock, flags);
1672
1673 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1674 /* Disable receiver and transmitter. */
1675 uap->curregs[R3] &= ~RxENABLE;
1676 uap->curregs[R5] &= ~TxENABLE;
1677
1678 /* Disable all interrupts and BRK assertion. */
1679 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1680 uap->curregs[R5] &= ~SND_BRK;
1681 pmz_load_zsregs(uap, uap->curregs);
1682 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1683 mb();
1684 }
1685
1686 spin_unlock_irqrestore(&uap->port.lock, flags);
1687
1688 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1689 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1690 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1691 disable_irq(uap->port.irq);
1692 }
1693
1694 if (ZS_IS_CONS(uap))
1695 uap->port.cons->flags &= ~CON_ENABLED;
1696
1697 /* Shut the chip down */
1698 pmz_set_scc_power(uap, 0);
1699
1700 mutex_unlock(&state->port.mutex);
1701 mutex_unlock(&pmz_irq_mutex);
1702
1703 pmz_debug("suspend, switching complete\n");
1704
1705 mdev->ofdev.dev.power.power_state = pm_state;
1706 1613
1707 return 0; 1614 return 0;
1708} 1615}
@@ -1711,76 +1618,20 @@ static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1711static int pmz_resume(struct macio_dev *mdev) 1618static int pmz_resume(struct macio_dev *mdev)
1712{ 1619{
1713 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1620 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1714 struct uart_state *state;
1715 unsigned long flags;
1716 int pwr_delay = 0;
1717 1621
1718 if (uap == NULL) 1622 if (uap == NULL)
1719 return 0; 1623 return 0;
1720 1624
1721 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) 1625 uart_resume_port(&pmz_uart_reg, &uap->port);
1722 return 0;
1723
1724 pmz_debug("resume, switching to state 0\n");
1725
1726 state = pmz_uart_reg.state + uap->port.line;
1727
1728 mutex_lock(&pmz_irq_mutex);
1729 mutex_lock(&state->port.mutex);
1730
1731 spin_lock_irqsave(&uap->port.lock, flags);
1732 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1733 spin_unlock_irqrestore(&uap->port.lock, flags);
1734 goto bail;
1735 }
1736 pwr_delay = __pmz_startup(uap);
1737
1738 /* Take care of config that may have changed while asleep */
1739 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1740
1741 if (ZS_IS_OPEN(uap)) {
1742 /* Enable interrupts */
1743 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1744 if (!ZS_IS_EXTCLK(uap))
1745 uap->curregs[R1] |= EXT_INT_ENAB;
1746 write_zsreg(uap, R1, uap->curregs[R1]);
1747 }
1748
1749 spin_unlock_irqrestore(&uap->port.lock, flags);
1750
1751 if (ZS_IS_CONS(uap))
1752 uap->port.cons->flags |= CON_ENABLED;
1753
1754 /* Re-enable IRQ on the controller */
1755 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1756 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1757 enable_irq(uap->port.irq);
1758 }
1759
1760 bail:
1761 mutex_unlock(&state->port.mutex);
1762 mutex_unlock(&pmz_irq_mutex);
1763
1764 /* Right now, we deal with delay by blocking here, I'll be
1765 * smarter later on
1766 */
1767 if (pwr_delay != 0) {
1768 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1769 msleep(pwr_delay);
1770 }
1771
1772 pmz_debug("resume, switching complete\n");
1773
1774 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1775 1626
1776 return 0; 1627 return 0;
1777} 1628}
1778 1629
1779/* 1630/*
1780 * Probe all ports in the system and build the ports array, we register 1631 * Probe all ports in the system and build the ports array, we register
1781 * with the serial layer at this point, the macio-type probing is only 1632 * with the serial layer later, so we get a proper struct device which
1782 * used later to "attach" to the sysfs tree so we get power management 1633 * allows the tty to attach properly. This is later than it used to be
1783 * events 1634 * but the tty layer really wants it that way.
1784 */ 1635 */
1785static int __init pmz_probe(void) 1636static int __init pmz_probe(void)
1786{ 1637{
@@ -1816,8 +1667,10 @@ static int __init pmz_probe(void)
1816 /* 1667 /*
1817 * Fill basic fields in the port structures 1668 * Fill basic fields in the port structures
1818 */ 1669 */
1819 pmz_ports[count].mate = &pmz_ports[count+1]; 1670 if (node_b != NULL) {
1820 pmz_ports[count+1].mate = &pmz_ports[count]; 1671 pmz_ports[count].mate = &pmz_ports[count+1];
1672 pmz_ports[count+1].mate = &pmz_ports[count];
1673 }
1821 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1674 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1822 pmz_ports[count].node = node_a; 1675 pmz_ports[count].node = node_a;
1823 pmz_ports[count+1].node = node_b; 1676 pmz_ports[count+1].node = node_b;
@@ -1855,8 +1708,8 @@ static int __init pmz_init_port(struct uart_pmac_port *uap)
1855 struct resource *r_ports; 1708 struct resource *r_ports;
1856 int irq; 1709 int irq;
1857 1710
1858 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0); 1711 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1859 irq = platform_get_irq(uap->node, 0); 1712 irq = platform_get_irq(uap->pdev, 0);
1860 if (!r_ports || !irq) 1713 if (!r_ports || !irq)
1861 return -ENODEV; 1714 return -ENODEV;
1862 1715
@@ -1885,19 +1738,19 @@ static int __init pmz_probe(void)
1885 1738
1886 pmz_ports_count = 0; 1739 pmz_ports_count = 0;
1887 1740
1888 pmz_ports[0].mate = &pmz_ports[1];
1889 pmz_ports[0].port.line = 0; 1741 pmz_ports[0].port.line = 0;
1890 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1742 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1891 pmz_ports[0].node = &scc_a_pdev; 1743 pmz_ports[0].pdev = &scc_a_pdev;
1892 err = pmz_init_port(&pmz_ports[0]); 1744 err = pmz_init_port(&pmz_ports[0]);
1893 if (err) 1745 if (err)
1894 return err; 1746 return err;
1895 pmz_ports_count++; 1747 pmz_ports_count++;
1896 1748
1749 pmz_ports[0].mate = &pmz_ports[1];
1897 pmz_ports[1].mate = &pmz_ports[0]; 1750 pmz_ports[1].mate = &pmz_ports[0];
1898 pmz_ports[1].port.line = 1; 1751 pmz_ports[1].port.line = 1;
1899 pmz_ports[1].flags = 0; 1752 pmz_ports[1].flags = 0;
1900 pmz_ports[1].node = &scc_b_pdev; 1753 pmz_ports[1].pdev = &scc_b_pdev;
1901 err = pmz_init_port(&pmz_ports[1]); 1754 err = pmz_init_port(&pmz_ports[1]);
1902 if (err) 1755 if (err)
1903 return err; 1756 return err;
@@ -1913,16 +1766,35 @@ static void pmz_dispose_port(struct uart_pmac_port *uap)
1913 1766
1914static int __init pmz_attach(struct platform_device *pdev) 1767static int __init pmz_attach(struct platform_device *pdev)
1915{ 1768{
1769 struct uart_pmac_port *uap;
1916 int i; 1770 int i;
1917 1771
1772 /* Iterate the pmz_ports array to find a matching entry */
1918 for (i = 0; i < pmz_ports_count; i++) 1773 for (i = 0; i < pmz_ports_count; i++)
1919 if (pmz_ports[i].node == pdev) 1774 if (pmz_ports[i].pdev == pdev)
1920 return 0; 1775 break;
1921 return -ENODEV; 1776 if (i >= pmz_ports_count)
1777 return -ENODEV;
1778
1779 uap = &pmz_ports[i];
1780 uap->port.dev = &pdev->dev;
1781 platform_set_drvdata(pdev, uap);
1782
1783 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1922} 1784}
1923 1785
1924static int __exit pmz_detach(struct platform_device *pdev) 1786static int __exit pmz_detach(struct platform_device *pdev)
1925{ 1787{
1788 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1789
1790 if (!uap)
1791 return -ENODEV;
1792
1793 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1794
1795 platform_set_drvdata(pdev, NULL);
1796 uap->port.dev = NULL;
1797
1926 return 0; 1798 return 0;
1927} 1799}
1928 1800
@@ -1954,38 +1826,13 @@ static struct console pmz_console = {
1954 */ 1826 */
1955static int __init pmz_register(void) 1827static int __init pmz_register(void)
1956{ 1828{
1957 int i, rc;
1958
1959 pmz_uart_reg.nr = pmz_ports_count; 1829 pmz_uart_reg.nr = pmz_ports_count;
1960 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1830 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1961 1831
1962 /* 1832 /*
1963 * Register this driver with the serial core 1833 * Register this driver with the serial core
1964 */ 1834 */
1965 rc = uart_register_driver(&pmz_uart_reg); 1835 return uart_register_driver(&pmz_uart_reg);
1966 if (rc)
1967 return rc;
1968
1969 /*
1970 * Register each port with the serial core
1971 */
1972 for (i = 0; i < pmz_ports_count; i++) {
1973 struct uart_pmac_port *uport = &pmz_ports[i];
1974 /* NULL node may happen on wallstreet */
1975 if (uport->node != NULL)
1976 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1977 if (rc)
1978 goto err_out;
1979 }
1980
1981 return 0;
1982err_out:
1983 while (i-- > 0) {
1984 struct uart_pmac_port *uport = &pmz_ports[i];
1985 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1986 }
1987 uart_unregister_driver(&pmz_uart_reg);
1988 return rc;
1989} 1836}
1990 1837
1991#ifdef CONFIG_PPC_PMAC 1838#ifdef CONFIG_PPC_PMAC
@@ -2084,10 +1931,13 @@ static void __exit exit_pmz(void)
2084 1931
2085 for (i = 0; i < pmz_ports_count; i++) { 1932 for (i = 0; i < pmz_ports_count; i++) {
2086 struct uart_pmac_port *uport = &pmz_ports[i]; 1933 struct uart_pmac_port *uport = &pmz_ports[i];
2087 if (uport->node != NULL) { 1934#ifdef CONFIG_PPC_PMAC
2088 uart_remove_one_port(&pmz_uart_reg, &uport->port); 1935 if (uport->node != NULL)
2089 pmz_dispose_port(uport); 1936 pmz_dispose_port(uport);
2090 } 1937#else
1938 if (uport->pdev != NULL)
1939 pmz_dispose_port(uport);
1940#endif
2091 } 1941 }
2092 /* Unregister UART driver */ 1942 /* Unregister UART driver */
2093 uart_unregister_driver(&pmz_uart_reg); 1943 uart_unregister_driver(&pmz_uart_reg);
@@ -2114,8 +1964,6 @@ static void pmz_console_write(struct console *con, const char *s, unsigned int c
2114 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1964 struct uart_pmac_port *uap = &pmz_ports[con->index];
2115 unsigned long flags; 1965 unsigned long flags;
2116 1966
2117 if (ZS_IS_ASLEEP(uap))
2118 return;
2119 spin_lock_irqsave(&uap->port.lock, flags); 1967 spin_lock_irqsave(&uap->port.lock, flags);
2120 1968
2121 /* Turn of interrupts and enable the transmitter. */ 1969 /* Turn of interrupts and enable the transmitter. */
@@ -2160,8 +2008,13 @@ static int __init pmz_console_setup(struct console *co, char *options)
2160 if (co->index >= pmz_ports_count) 2008 if (co->index >= pmz_ports_count)
2161 co->index = 0; 2009 co->index = 0;
2162 uap = &pmz_ports[co->index]; 2010 uap = &pmz_ports[co->index];
2011#ifdef CONFIG_PPC_PMAC
2163 if (uap->node == NULL) 2012 if (uap->node == NULL)
2164 return -ENODEV; 2013 return -ENODEV;
2014#else
2015 if (uap->pdev == NULL)
2016 return -ENODEV;
2017#endif
2165 port = &uap->port; 2018 port = &uap->port;
2166 2019
2167 /* 2020 /*
diff --git a/drivers/tty/serial/pmac_zilog.h b/drivers/tty/serial/pmac_zilog.h
index cbc34fbb1b2..3483242ee3e 100644
--- a/drivers/tty/serial/pmac_zilog.h
+++ b/drivers/tty/serial/pmac_zilog.h
@@ -1,16 +1,6 @@
1#ifndef __PMAC_ZILOG_H__ 1#ifndef __PMAC_ZILOG_H__
2#define __PMAC_ZILOG_H__ 2#define __PMAC_ZILOG_H__
3 3
4#ifdef CONFIG_PPC_PMAC
5#define pmz_debug(fmt, arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg)
6#define pmz_error(fmt, arg...) dev_err(&uap->dev->ofdev.dev, fmt, ## arg)
7#define pmz_info(fmt, arg...) dev_info(&uap->dev->ofdev.dev, fmt, ## arg)
8#else
9#define pmz_debug(fmt, arg...) dev_dbg(&uap->node->dev, fmt, ## arg)
10#define pmz_error(fmt, arg...) dev_err(&uap->node->dev, fmt, ## arg)
11#define pmz_info(fmt, arg...) dev_info(&uap->node->dev, fmt, ## arg)
12#endif
13
14/* 4/*
15 * At most 2 ESCCs with 2 ports each 5 * At most 2 ESCCs with 2 ports each
16 */ 6 */
@@ -35,7 +25,7 @@ struct uart_pmac_port {
35 */ 25 */
36 struct device_node *node; 26 struct device_node *node;
37#else 27#else
38 struct platform_device *node; 28 struct platform_device *pdev;
39#endif 29#endif
40 30
41 /* Port type as obtained from device tree (IRDA, modem, ...) */ 31 /* Port type as obtained from device tree (IRDA, modem, ...) */
@@ -50,14 +40,11 @@ struct uart_pmac_port {
50#define PMACZILOG_FLAG_REGS_HELD 0x00000010 40#define PMACZILOG_FLAG_REGS_HELD 0x00000010
51#define PMACZILOG_FLAG_TX_STOPPED 0x00000020 41#define PMACZILOG_FLAG_TX_STOPPED 0x00000020
52#define PMACZILOG_FLAG_TX_ACTIVE 0x00000040 42#define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
53#define PMACZILOG_FLAG_ENABLED 0x00000080
54#define PMACZILOG_FLAG_IS_IRDA 0x00000100 43#define PMACZILOG_FLAG_IS_IRDA 0x00000100
55#define PMACZILOG_FLAG_IS_INTMODEM 0x00000200 44#define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
56#define PMACZILOG_FLAG_HAS_DMA 0x00000400 45#define PMACZILOG_FLAG_HAS_DMA 0x00000400
57#define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800 46#define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
58#define PMACZILOG_FLAG_IS_ASLEEP 0x00001000
59#define PMACZILOG_FLAG_IS_OPEN 0x00002000 47#define PMACZILOG_FLAG_IS_OPEN 0x00002000
60#define PMACZILOG_FLAG_IS_IRQ_ON 0x00004000
61#define PMACZILOG_FLAG_IS_EXTCLK 0x00008000 48#define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
62#define PMACZILOG_FLAG_BREAK 0x00010000 49#define PMACZILOG_FLAG_BREAK 0x00010000
63 50
@@ -74,6 +61,8 @@ struct uart_pmac_port {
74 volatile struct dbdma_regs __iomem *rx_dma_regs; 61 volatile struct dbdma_regs __iomem *rx_dma_regs;
75#endif 62#endif
76 63
64 unsigned char irq_name[8];
65
77 struct ktermios termios_cache; 66 struct ktermios termios_cache;
78}; 67};
79 68
@@ -388,9 +377,7 @@ static inline void zssync(struct uart_pmac_port *port)
388#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) 377#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
389#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) 378#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
390#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) 379#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
391#define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP)
392#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) 380#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
393#define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON)
394#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) 381#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
395 382
396#endif /* __PMAC_ZILOG_H__ */ 383#endif /* __PMAC_ZILOG_H__ */
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index cea8918b823..2ebe606a2db 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -963,6 +963,9 @@ static void qe_uart_set_termios(struct uart_port *port,
963 /* Do we really need a spinlock here? */ 963 /* Do we really need a spinlock here? */
964 spin_lock_irqsave(&port->lock, flags); 964 spin_lock_irqsave(&port->lock, flags);
965 965
966 /* Update the per-port timeout. */
967 uart_update_timeout(port, termios->c_cflag, baud);
968
966 out_be16(&uccp->upsmr, upsmr); 969 out_be16(&uccp->upsmr, upsmr);
967 if (soft_uart) { 970 if (soft_uart) {
968 out_be16(&uccup->supsmr, supsmr); 971 out_be16(&uccup->supsmr, supsmr);
diff --git a/drivers/video/offb.c b/drivers/video/offb.c
index cb163a5397b..0c4f34311ed 100644
--- a/drivers/video/offb.c
+++ b/drivers/video/offb.c
@@ -41,13 +41,14 @@
41/* Supported palette hacks */ 41/* Supported palette hacks */
42enum { 42enum {
43 cmap_unknown, 43 cmap_unknown,
44 cmap_m64, /* ATI Mach64 */ 44 cmap_simple, /* ATI Mach64 */
45 cmap_r128, /* ATI Rage128 */ 45 cmap_r128, /* ATI Rage128 */
46 cmap_M3A, /* ATI Rage Mobility M3 Head A */ 46 cmap_M3A, /* ATI Rage Mobility M3 Head A */
47 cmap_M3B, /* ATI Rage Mobility M3 Head B */ 47 cmap_M3B, /* ATI Rage Mobility M3 Head B */
48 cmap_radeon, /* ATI Radeon */ 48 cmap_radeon, /* ATI Radeon */
49 cmap_gxt2000, /* IBM GXT2000 */ 49 cmap_gxt2000, /* IBM GXT2000 */
50 cmap_avivo, /* ATI R5xx */ 50 cmap_avivo, /* ATI R5xx */
51 cmap_qemu, /* qemu vga */
51}; 52};
52 53
53struct offb_par { 54struct offb_par {
@@ -100,36 +101,32 @@ static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
100 u_int transp, struct fb_info *info) 101 u_int transp, struct fb_info *info)
101{ 102{
102 struct offb_par *par = (struct offb_par *) info->par; 103 struct offb_par *par = (struct offb_par *) info->par;
103 int i, depth; 104
104 u32 *pal = info->pseudo_palette; 105 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
105 106 u32 *pal = info->pseudo_palette;
106 depth = info->var.bits_per_pixel; 107 u32 cr = red >> (16 - info->var.red.length);
107 if (depth == 16) 108 u32 cg = green >> (16 - info->var.green.length);
108 depth = (info->var.green.length == 5) ? 15 : 16; 109 u32 cb = blue >> (16 - info->var.blue.length);
109 110 u32 value;
110 if (regno > 255 || 111
111 (depth == 16 && regno > 63) || 112 if (regno >= 16)
112 (depth == 15 && regno > 31)) 113 return -EINVAL;
113 return 1; 114
114 115 value = (cr << info->var.red.offset) |
115 if (regno < 16) { 116 (cg << info->var.green.offset) |
116 switch (depth) { 117 (cb << info->var.blue.offset);
117 case 15: 118 if (info->var.transp.length > 0) {
118 pal[regno] = (regno << 10) | (regno << 5) | regno; 119 u32 mask = (1 << info->var.transp.length) - 1;
119 break; 120 mask <<= info->var.transp.offset;
120 case 16: 121 value |= mask;
121 pal[regno] = (regno << 11) | (regno << 5) | regno;
122 break;
123 case 24:
124 pal[regno] = (regno << 16) | (regno << 8) | regno;
125 break;
126 case 32:
127 i = (regno << 8) | regno;
128 pal[regno] = (i << 16) | i;
129 break;
130 } 122 }
123 pal[regno] = value;
124 return 0;
131 } 125 }
132 126
127 if (regno > 255)
128 return -EINVAL;
129
133 red >>= 8; 130 red >>= 8;
134 green >>= 8; 131 green >>= 8;
135 blue >>= 8; 132 blue >>= 8;
@@ -138,7 +135,7 @@ static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
138 return 0; 135 return 0;
139 136
140 switch (par->cmap_type) { 137 switch (par->cmap_type) {
141 case cmap_m64: 138 case cmap_simple:
142 writeb(regno, par->cmap_adr); 139 writeb(regno, par->cmap_adr);
143 writeb(red, par->cmap_data); 140 writeb(red, par->cmap_data);
144 writeb(green, par->cmap_data); 141 writeb(green, par->cmap_data);
@@ -208,7 +205,7 @@ static int offb_blank(int blank, struct fb_info *info)
208 if (blank) 205 if (blank)
209 for (i = 0; i < 256; i++) { 206 for (i = 0; i < 256; i++) {
210 switch (par->cmap_type) { 207 switch (par->cmap_type) {
211 case cmap_m64: 208 case cmap_simple:
212 writeb(i, par->cmap_adr); 209 writeb(i, par->cmap_adr);
213 for (j = 0; j < 3; j++) 210 for (j = 0; j < 3; j++)
214 writeb(0, par->cmap_data); 211 writeb(0, par->cmap_data);
@@ -350,7 +347,7 @@ static void offb_init_palette_hacks(struct fb_info *info, struct device_node *dp
350 par->cmap_adr = 347 par->cmap_adr =
351 ioremap(base + 0x7ff000, 0x1000) + 0xcc0; 348 ioremap(base + 0x7ff000, 0x1000) + 0xcc0;
352 par->cmap_data = par->cmap_adr + 1; 349 par->cmap_data = par->cmap_adr + 1;
353 par->cmap_type = cmap_m64; 350 par->cmap_type = cmap_simple;
354 } else if (dp && (of_device_is_compatible(dp, "pci1014,b7") || 351 } else if (dp && (of_device_is_compatible(dp, "pci1014,b7") ||
355 of_device_is_compatible(dp, "pci1014,21c"))) { 352 of_device_is_compatible(dp, "pci1014,21c"))) {
356 par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000); 353 par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000);
@@ -371,6 +368,16 @@ static void offb_init_palette_hacks(struct fb_info *info, struct device_node *dp
371 par->cmap_type = cmap_avivo; 368 par->cmap_type = cmap_avivo;
372 } 369 }
373 of_node_put(pciparent); 370 of_node_put(pciparent);
371 } else if (dp && of_device_is_compatible(dp, "qemu,std-vga")) {
372 const u32 io_of_addr[3] = { 0x01000000, 0x0, 0x0 };
373 u64 io_addr = of_translate_address(dp, io_of_addr);
374 if (io_addr != OF_BAD_ADDR) {
375 par->cmap_adr = ioremap(io_addr + 0x3c8, 2);
376 if (par->cmap_adr) {
377 par->cmap_type = cmap_simple;
378 par->cmap_data = par->cmap_adr + 1;
379 }
380 }
374 } 381 }
375 info->fix.visual = (par->cmap_type != cmap_unknown) ? 382 info->fix.visual = (par->cmap_type != cmap_unknown) ?
376 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR; 383 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR;
@@ -381,7 +388,7 @@ static void __init offb_init_fb(const char *name, const char *full_name,
381 int pitch, unsigned long address, 388 int pitch, unsigned long address,
382 int foreign_endian, struct device_node *dp) 389 int foreign_endian, struct device_node *dp)
383{ 390{
384 unsigned long res_size = pitch * height * (depth + 7) / 8; 391 unsigned long res_size = pitch * height;
385 struct offb_par *par = &default_par; 392 struct offb_par *par = &default_par;
386 unsigned long res_start = address; 393 unsigned long res_start = address;
387 struct fb_fix_screeninfo *fix; 394 struct fb_fix_screeninfo *fix;
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 7408af843b8..23f81de5182 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -130,7 +130,6 @@ struct cpuidle_driver {
130#ifdef CONFIG_CPU_IDLE 130#ifdef CONFIG_CPU_IDLE
131extern void disable_cpuidle(void); 131extern void disable_cpuidle(void);
132extern int cpuidle_idle_call(void); 132extern int cpuidle_idle_call(void);
133
134extern int cpuidle_register_driver(struct cpuidle_driver *drv); 133extern int cpuidle_register_driver(struct cpuidle_driver *drv);
135struct cpuidle_driver *cpuidle_get_driver(void); 134struct cpuidle_driver *cpuidle_get_driver(void);
136extern void cpuidle_unregister_driver(struct cpuidle_driver *drv); 135extern void cpuidle_unregister_driver(struct cpuidle_driver *drv);
@@ -145,7 +144,6 @@ extern void cpuidle_disable_device(struct cpuidle_device *dev);
145#else 144#else
146static inline void disable_cpuidle(void) { } 145static inline void disable_cpuidle(void) { }
147static inline int cpuidle_idle_call(void) { return -ENODEV; } 146static inline int cpuidle_idle_call(void) { return -ENODEV; }
148
149static inline int cpuidle_register_driver(struct cpuidle_driver *drv) 147static inline int cpuidle_register_driver(struct cpuidle_driver *drv)
150{return -ENODEV; } 148{return -ENODEV; }
151static inline struct cpuidle_driver *cpuidle_get_driver(void) {return NULL; } 149static inline struct cpuidle_driver *cpuidle_get_driver(void) {return NULL; }
diff --git a/tools/perf/arch/powerpc/util/dwarf-regs.c b/tools/perf/arch/powerpc/util/dwarf-regs.c
index 48ae0c5e3f7..7cdd61d0e27 100644
--- a/tools/perf/arch/powerpc/util/dwarf-regs.c
+++ b/tools/perf/arch/powerpc/util/dwarf-regs.c
@@ -9,7 +9,10 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12#include <stdlib.h>
13#ifndef __UCLIBC__
12#include <libio.h> 14#include <libio.h>
15#endif
13#include <dwarf-regs.h> 16#include <dwarf-regs.h>
14 17
15 18
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 06:53:05 -0400