diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /sound/soc/codecs/tlv320aic326x.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'sound/soc/codecs/tlv320aic326x.h')
-rw-r--r-- | sound/soc/codecs/tlv320aic326x.h | 684 |
1 files changed, 684 insertions, 0 deletions
diff --git a/sound/soc/codecs/tlv320aic326x.h b/sound/soc/codecs/tlv320aic326x.h new file mode 100644 index 00000000000..a31cc9eca5c --- /dev/null +++ b/sound/soc/codecs/tlv320aic326x.h | |||
@@ -0,0 +1,684 @@ | |||
1 | /* | ||
2 | * linux/sound/soc/codecs/tlv320aic3262.h | ||
3 | * | ||
4 | * | ||
5 | * Copyright (C) 2012 Texas Instruments, Inc. | ||
6 | * | ||
7 | * This package is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | ||
12 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | ||
13 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
14 | * | ||
15 | * History: | ||
16 | * Rev 0.1 ASoC driver support 20-01-2011 | ||
17 | * | ||
18 | * The AIC3262 ASoC driver is ported for the codec AIC3262. | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #ifndef _TLV320AIC3262_H | ||
23 | #define _TLV320AIC3262_H | ||
24 | #include <linux/input.h> | ||
25 | #define AUDIO_NAME "aic3262" | ||
26 | #define AIC3262_VERSION "1.1" | ||
27 | |||
28 | //#define AIC3262_ASI2_MASTER 1 | ||
29 | |||
30 | /* Enable this macro allow for different ASI formats */ | ||
31 | /*#define ASI_MULTI_FMT*/ | ||
32 | #undef ASI_MULTI_FMT | ||
33 | |||
34 | #define INT_FLAG2_BUTTN_PRESSBIT 0x20 | ||
35 | |||
36 | /* Enable register caching on write */ | ||
37 | #define EN_REG_CACHE 1 | ||
38 | |||
39 | #define MULTIBYTE_CONFIG_SUPPORT | ||
40 | |||
41 | /*Setting all codec reg/write locally*/ | ||
42 | /* This definition is added as the snd_ direct call are | ||
43 | result some issue with cache. Common code doesnot support | ||
44 | page, so fix that before commenting this line*/ | ||
45 | #define LOCAL_REG_ACCESS 1 | ||
46 | |||
47 | /* Macro to enable the inclusion of tiload kernel driver */ | ||
48 | #define AIC3262_TiLoad | ||
49 | |||
50 | |||
51 | /* Macro enables or disables support for miniDSP in the driver */ | ||
52 | /* Enable the AIC3262_TiLoad macro first before enabling these macros */ | ||
53 | #define CONFIG_MINI_DSP | ||
54 | /*#undef CONFIG_MINI_DSP*/ | ||
55 | |||
56 | /* Enable or disable controls to have Input routing*/ | ||
57 | /*#define FULL_IN_CNTL */ | ||
58 | #undef FULL_IN_CNTL | ||
59 | /* AIC3262 supported sample rate are 8k to 192k */ | ||
60 | #define AIC3262_RATES SNDRV_PCM_RATE_8000_192000 | ||
61 | |||
62 | /* AIC3262 supports the word formats 16bits, 20bits, 24bits and 32 bits */ | ||
63 | #define AIC3262_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | ||
64 | | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | ||
65 | |||
66 | #define AIC3262_FREQ_12000000 12000000 | ||
67 | #define AIC3262_FREQ_12288000 12288000 | ||
68 | #define AIC3262_FREQ_24000000 24000000 | ||
69 | |||
70 | /* Macro for enabling the Multi_I2S Support in Driver */ | ||
71 | #define AIC3262_MULTI_I2S 1 | ||
72 | |||
73 | /* Driver Debug Messages Enabled */ | ||
74 | //#define DEBUG | ||
75 | |||
76 | #ifdef DEBUG | ||
77 | #define DBG(x...) printk(x) | ||
78 | #else | ||
79 | #define DBG(x...) | ||
80 | #endif | ||
81 | |||
82 | /*Select the below macro to decide on the DAC master volume controls. | ||
83 | *2 independent or one combined | ||
84 | */ | ||
85 | /*#define DAC_INDEPENDENT_VOL*/ | ||
86 | #undef DAC_INDEPENDENT_VOL | ||
87 | |||
88 | /* Audio data word length = 16-bits (default setting) */ | ||
89 | #define AIC3262_WORD_LEN_16BITS 0x00 | ||
90 | #define AIC3262_WORD_LEN_20BITS 0x01 | ||
91 | #define AIC3262_WORD_LEN_24BITS 0x02 | ||
92 | #define AIC3262_WORD_LEN_32BITS 0x03 | ||
93 | |||
94 | /* sink: name of target widget */ | ||
95 | #define AIC3262_WIDGET_NAME 0 | ||
96 | /* control: mixer control name */ | ||
97 | #define AIC3262_CONTROL_NAME | ||
98 | /* source: name of source name */ | ||
99 | #define AIC3262_SOURCE_NAME 2 | ||
100 | |||
101 | /* D15..D8 aic3262 register offset */ | ||
102 | #define AIC3262_REG_OFFSET_INDEX 0 | ||
103 | /* D7...D0 register data */ | ||
104 | #define AIC3262_REG_DATA_INDEX 1 | ||
105 | |||
106 | /* Serial data bus uses I2S mode (Default mode) */ | ||
107 | #define AIC3262_I2S_MODE 0x00 | ||
108 | #define AIC3262_DSP_MODE 0x01 | ||
109 | #define AIC3262_RIGHT_JUSTIFIED_MODE 0x02 | ||
110 | #define AIC3262_LEFT_JUSTIFIED_MODE 0x03 | ||
111 | |||
112 | /* 8 bit mask value */ | ||
113 | #define AIC3262_8BITS_MASK 0xFF | ||
114 | |||
115 | /* shift value for CLK_REG_3 register */ | ||
116 | #define CLK_REG_3_SHIFT 6 | ||
117 | /* shift value for DAC_OSR_MSB register */ | ||
118 | #define DAC_OSR_MSB_SHIFT 4 | ||
119 | |||
120 | /* number of codec specific register for configuration */ | ||
121 | #define NO_FEATURE_REGS 2 | ||
122 | |||
123 | /* Total number of ASI Ports */ | ||
124 | #define MAX_ASI_COUNT 3 | ||
125 | |||
126 | |||
127 | /* AIC3262 register space */ | ||
128 | /* Updated from 256 to support Page 3 registers */ | ||
129 | #define AIC3262_CACHEREGNUM 1024 | ||
130 | #define BIT7 (0x01 << 7) | ||
131 | #define BIT6 (0x01 << 6) | ||
132 | #define BIT5 (0x01 << 5) | ||
133 | #define BIT4 (0x01 << 4) | ||
134 | #define BIT3 (0x01 << 3) | ||
135 | #define BIT2 (0x01 << 2) | ||
136 | #define BIT1 (0x01 << 1) | ||
137 | #define BIT0 (0x01 << 0) | ||
138 | |||
139 | #define DAC_FLAG_MIC_MASKBITS 0x30 | ||
140 | #define DAC_FLAG_HS_MASKBITS 0x03 | ||
141 | #define DAC_FLAG_R1_NOJACK 0 | ||
142 | #define DAC_FLAG_R1_NOMIC (0x1 << 4) | ||
143 | #define DAC_FLAG_R1_MIC (0x3 << 4) | ||
144 | #define DAC_FLAG_R1_NOHS 0 | ||
145 | #define DAC_FLAG_R1_MONOHS 1 | ||
146 | #define DAC_FLAG_R1_STEREOHS 2 | ||
147 | |||
148 | /*mask patterns for DAC and ADC polling logic*/ | ||
149 | #define LDAC_POW_FLAG_MASK 0x80 | ||
150 | #define RDAC_POW_FLAG_MASK 0x08 | ||
151 | #define LADC_POW_FLAG_MASK 0x40 | ||
152 | #define RADC_POW_FLAG_MASK 0x04 | ||
153 | |||
154 | /* ****************** Book 0 Registers **************************************/ | ||
155 | |||
156 | /* ****************** Page 0 Registers **************************************/ | ||
157 | |||
158 | #define PAGE_SEL_REG 0 | ||
159 | #define RESET_REG 1 | ||
160 | #define DAC_ADC_CLKIN_REG 4 | ||
161 | #define PLL_CLKIN_REG 5 | ||
162 | #define PLL_CLK_RANGE_REG 5 | ||
163 | #define PLL_PR_POW_REG 6 | ||
164 | #define PLL_J_REG 7 | ||
165 | #define PLL_D_MSB 8 | ||
166 | #define PLL_D_LSB 9 | ||
167 | #define PLL_CKIN_DIV 10 | ||
168 | |||
169 | #define NDAC_DIV_POW_REG 11 | ||
170 | #define MDAC_DIV_POW_REG 12 | ||
171 | #define DOSR_MSB_REG 13 | ||
172 | #define DOSR_LSB_REG 14 | ||
173 | |||
174 | #define NADC_DIV_POW_REG 18 | ||
175 | #define MADC_DIV_POW_REG 19 | ||
176 | #define AOSR_REG 20 | ||
177 | #define CLKOUT_MUX 21 | ||
178 | #define CLKOUT_MDIV_VAL 22 | ||
179 | #define TIMER_REG 23 | ||
180 | |||
181 | #define LF_CLK_CNTL 24 | ||
182 | #define HF_CLK_CNTL_R1 25 | ||
183 | #define HF_CLK_CNTL_R2 26 | ||
184 | #define HF_CLK_CNTL_R3 27 | ||
185 | #define HF_CLK_CNTL_R4 28 | ||
186 | #define HF_CLK_TRIM_R1 29 | ||
187 | #define HF_CLK_TRIM_R2 30 | ||
188 | #define HF_CLK_TRIM_R3 31 | ||
189 | #define HF_CLK_TRIM_R4 32 | ||
190 | #define ADC_FLAG_R1 36 | ||
191 | #define DAC_FLAG_R1 37 | ||
192 | #define DAC_FLAG_R2 38 | ||
193 | |||
194 | #define STICKY_FLAG1 42 | ||
195 | #define INT_FLAG1 43 | ||
196 | #define STICKY_FLAG2 44 | ||
197 | #define STICKY_FLAG3 45 | ||
198 | #define INT_FLAG2 46 | ||
199 | #define INT1_CNTL 48 | ||
200 | #define INT2_CNTL 49 | ||
201 | #define INT_FMT 51 | ||
202 | |||
203 | #define DAC_PRB 60 | ||
204 | #define ADC_PRB 61 | ||
205 | #define PASI_DAC_DP_SETUP 63 | ||
206 | #define DAC_MVOL_CONF 64 | ||
207 | #define DAC_LVOL 65 | ||
208 | #define DAC_RVOL 66 | ||
209 | #define HP_DETECT 67 | ||
210 | #define DRC_CNTL_R1 68 | ||
211 | #define DRC_CNTL_R2 69 | ||
212 | #define DRC_CNTL_R3 70 | ||
213 | #define BEEP_CNTL_R1 71 | ||
214 | #define BEEP_CNTL_R2 72 | ||
215 | |||
216 | #define ADC_CHANNEL_POW 81 | ||
217 | #define ADC_FINE_GAIN 82 | ||
218 | #define LADC_VOL 83 | ||
219 | #define RADC_VOL 84 | ||
220 | #define ADC_PHASE 85 | ||
221 | |||
222 | #define LAGC_CNTL 86 | ||
223 | #define LAGC_CNTL_R2 87 | ||
224 | #define LAGC_CNTL_R3 88 | ||
225 | #define LAGC_CNTL_R4 89 | ||
226 | #define LAGC_CNTL_R5 90 | ||
227 | #define LAGC_CNTL_R6 91 | ||
228 | #define LAGC_CNTL_R7 92 | ||
229 | #define LAGC_CNTL_R8 93 | ||
230 | |||
231 | #define RAGC_CNTL 94 | ||
232 | #define RAGC_CNTL_R2 95 | ||
233 | #define RAGC_CNTL_R3 96 | ||
234 | #define RAGC_CNTL_R4 97 | ||
235 | #define RAGC_CNTL_R5 98 | ||
236 | #define RAGC_CNTL_R6 99 | ||
237 | #define RAGC_CNTL_R7 100 | ||
238 | #define RAGC_CNTL_R8 101 | ||
239 | #define MINIDSP_ACCESS_CTRL 121 | ||
240 | /* ****************** Page 1 Registers **************************************/ | ||
241 | #define PAGE_1 128 | ||
242 | |||
243 | #define POWER_CONF (PAGE_1 + 1) | ||
244 | #define LDAC_PTM (PAGE_1 + 3) | ||
245 | #define RDAC_PTM (PAGE_1 + 4) | ||
246 | #define CM_REG (PAGE_1 + 8) | ||
247 | #define HP_CTL (PAGE_1 + 9) | ||
248 | #define HP_DEPOP (PAGE_1 + 11) | ||
249 | #define RECV_DEPOP (PAGE_1 + 12) | ||
250 | #define MA_CNTL (PAGE_1 + 17) | ||
251 | #define LADC_PGA_MAL_VOL (PAGE_1 + 18) | ||
252 | #define RADC_PGA_MAR_VOL (PAGE_1 + 19) | ||
253 | |||
254 | |||
255 | #define LINE_AMP_CNTL_R1 (PAGE_1 + 22) | ||
256 | #define LINE_AMP_CNTL_R2 (PAGE_1 + 23) | ||
257 | |||
258 | #define HP_AMP_CNTL_R1 (PAGE_1 + 27) | ||
259 | #define HP_AMP_CNTL_R2 (PAGE_1 + 28) | ||
260 | #define HP_AMP_CNTL_R3 (PAGE_1 + 29) | ||
261 | |||
262 | #define HPL_VOL (PAGE_1 + 31) | ||
263 | #define HPR_VOL (PAGE_1 + 32) | ||
264 | #define INT1_SEL_L (PAGE_1 + 34) | ||
265 | #define RAMP_CNTL_R1 (PAGE_1 + 36) | ||
266 | #define RAMP_CNTL_R2 (PAGE_1 + 37) | ||
267 | //#define INT1_SEL_RM (PAGE_1 + 39) | ||
268 | #define IN1L_SEL_RM (PAGE_1 + 39) | ||
269 | #define IN1R_SEL_RM (PAGE_1 + 39) | ||
270 | |||
271 | #define REC_AMP_CNTL_R5 (PAGE_1 + 40) | ||
272 | #define RAMPR_VOL (PAGE_1 + 41) | ||
273 | #define RAMP_TIME_CNTL (PAGE_1 + 42) | ||
274 | #define SPK_AMP_CNTL_R1 (PAGE_1 + 45) | ||
275 | #define SPK_AMP_CNTL_R2 (PAGE_1 + 46) | ||
276 | #define SPK_AMP_CNTL_R3 (PAGE_1 + 47) | ||
277 | #define SPK_AMP_CNTL_R4 (PAGE_1 + 48) | ||
278 | #define MIC_BIAS_CNTL (PAGE_1 + 51) | ||
279 | |||
280 | #define LMIC_PGA_PIN (PAGE_1 + 52) | ||
281 | #define LMIC_PGA_PM_IN4 (PAGE_1 + 53) | ||
282 | #define LMIC_PGA_MIN (PAGE_1 + 54) | ||
283 | #define RMIC_PGA_PIN (PAGE_1 + 55) | ||
284 | #define RMIC_PGA_PM_IN4 (PAGE_1 + 56) | ||
285 | #define RMIC_PGA_MIN (PAGE_1 + 57) | ||
286 | /* MIC PGA Gain Registers */ | ||
287 | #define MICL_PGA (PAGE_1 + 59) | ||
288 | #define MICR_PGA (PAGE_1 + 60) | ||
289 | #define HEADSET_TUNING1_REG (PAGE_1 + 119) | ||
290 | #define HEADSET_TUNING2_REG (PAGE_1 + 120) | ||
291 | #define MIC_PWR_DLY (PAGE_1 + 121) | ||
292 | #define REF_PWR_DLY (PAGE_1 + 122) | ||
293 | |||
294 | /* ****************** Page 4 Registers **************************************/ | ||
295 | #define PAGE_4 512 | ||
296 | #define ASI1_BUS_FMT (PAGE_4 + 1) | ||
297 | #define ASI1_LCH_OFFSET (PAGE_4 + 2) | ||
298 | #define ASI1_RCH_OFFSET (PAGE_4 + 3) | ||
299 | #define ASI1_CHNL_SETUP (PAGE_4 + 4) | ||
300 | #define ASI1_MULTI_CH_SETUP_R1 (PAGE_4 + 5) | ||
301 | #define ASI1_MULTI_CH_SETUP_R2 (PAGE_4 + 6) | ||
302 | #define ASI1_ADC_INPUT_CNTL (PAGE_4 + 7) | ||
303 | #define ASI1_DAC_OUT_CNTL (PAGE_4 + 8) | ||
304 | #define ASI1_ADC_OUT_TRISTATE (PAGE_4 + 9) | ||
305 | #define ASI1_BWCLK_CNTL_REG (PAGE_4 + 10) | ||
306 | #define ASI1_BCLK_N_CNTL (PAGE_4 + 11) | ||
307 | #define ASI1_BCLK_N (PAGE_4 + 12) | ||
308 | #define ASI1_WCLK_N (PAGE_4 + 13) | ||
309 | #define ASI1_BWCLK_OUT_CNTL (PAGE_4 + 14) | ||
310 | #define ASI1_DATA_OUT (PAGE_4 + 15) | ||
311 | #define ASI2_BUS_FMT (PAGE_4 + 17) | ||
312 | #define ASI2_LCH_OFFSET (PAGE_4 + 18) | ||
313 | #define ASI2_RCH_OFFSET (PAGE_4 + 19) | ||
314 | #define ASI2_ADC_INPUT_CNTL (PAGE_4 + 23) | ||
315 | #define ASI2_DAC_OUT_CNTL (PAGE_4 + 24) | ||
316 | #define ASI2_BWCLK_CNTL_REG (PAGE_4 + 26) | ||
317 | #define ASI2_BCLK_N_CNTL (PAGE_4 + 27) | ||
318 | #define ASI2_BCLK_N (PAGE_4 + 28) | ||
319 | #define ASI2_WCLK_N (PAGE_4 + 29) | ||
320 | #define ASI2_BWCLK_OUT_CNTL (PAGE_4 + 30) | ||
321 | #define ASI2_DATA_OUT (PAGE_4 + 31) | ||
322 | #define ASI3_BUS_FMT (PAGE_4 + 33) | ||
323 | #define ASI3_LCH_OFFSET (PAGE_4 + 34) | ||
324 | #define ASI3_RCH_OFFSET (PAGE_4 + 35) | ||
325 | #define ASI3_ADC_INPUT_CNTL (PAGE_4 + 39) | ||
326 | #define ASI3_DAC_OUT_CNTL (PAGE_4 + 40) | ||
327 | #define ASI3_BWCLK_CNTL_REG (PAGE_4 + 42) | ||
328 | #define ASI3_BCLK_N_CNTL (PAGE_4 + 43) | ||
329 | #define ASI3_BCLK_N (PAGE_4 + 44) | ||
330 | #define ASI3_WCLK_N (PAGE_4 + 45) | ||
331 | #define ASI3_BWCLK_OUT_CNTL (PAGE_4 + 46) | ||
332 | #define ASI3_DATA_OUT (PAGE_4 + 47) | ||
333 | #define WCLK1_PIN_CNTL_REG (PAGE_4 + 65) | ||
334 | #define DOUT1_PIN_CNTL_REG (PAGE_4 + 67) | ||
335 | #define DIN1_PIN_CNTL_REG (PAGE_4 + 68) | ||
336 | #define WCLK2_PIN_CNTL_REG (PAGE_4 + 69) | ||
337 | #define BCLK2_PIN_CNTL_REG (PAGE_4 + 70) | ||
338 | #define DOUT2_PIN_CNTL_REG (PAGE_4 + 71) | ||
339 | #define DIN2_PIN_CNTL_REG (PAGE_4 + 72) | ||
340 | #define WCLK3_PIN_CNTL_REG (PAGE_4 + 73) | ||
341 | #define BCLK3_PIN_CNTL_REG (PAGE_4 + 74) | ||
342 | #define DOUT3_PIN_CNTL_REG (PAGE_4 + 75) | ||
343 | #define DIN3_PIN_CNTL_REG (PAGE_4 + 76) | ||
344 | #define MCLK2_PIN_CNTL_REG (PAGE_4 + 82) | ||
345 | #define GPIO1_IO_CNTL (PAGE_4 + 86) | ||
346 | #define GPIO2_IO_CNTL (PAGE_4 + 87) | ||
347 | #define GPI1_EN (PAGE_4 + 91) | ||
348 | #define GPO2_EN (PAGE_4 + 92) | ||
349 | #define GPO1_PIN_CNTL (PAGE_4 + 96) | ||
350 | #define MINIDSP_PORT_CNTL_REG (PAGE_4 + 118) | ||
351 | |||
352 | /**************************************************************************** | ||
353 | * Mixer control related #defines | ||
354 | *************************************************************************** | ||
355 | */ | ||
356 | #define WCLK1_ENUM 0 | ||
357 | #define DOUT1_ENUM 1 | ||
358 | #define DIN1_ENUM 2 | ||
359 | #define WCLK2_ENUM 3 | ||
360 | #define BCLK2_ENUM 4 | ||
361 | #define DOUT2_ENUM 5 | ||
362 | #define DIN2_ENUM 6 | ||
363 | #define WCLK3_ENUM 7 | ||
364 | #define BCLK3_ENUM 8 | ||
365 | #define DOUT3_ENUM 9 | ||
366 | #define DIN3_ENUM 10 | ||
367 | #define CLKIN_ENUM 11 | ||
368 | /* | ||
369 | ***************************************************************************** | ||
370 | * Enumeration Definitions | ||
371 | ***************************************************************************** | ||
372 | */ | ||
373 | /* The below enumeration lists down all the possible inputs to the | ||
374 | * the PLL of the AIC3262. The Private structure will hold a member | ||
375 | * of this Enumeration Type. | ||
376 | */ | ||
377 | enum AIC3262_PLL_OPTION { | ||
378 | PLL_CLKIN_MCLK1 = 0, /* 0000: (Device Pin) */ | ||
379 | PLL_CLKIN_BLKC1, /* 0001: (Device Pin) */ | ||
380 | PLL_CLKIN_GPIO1, /* 0010: (Device Pin)*/ | ||
381 | PLL_CLKIN_DIN1, /* 0011: (Device Pin)*/ | ||
382 | PLL_CLKIN_BCLK2, /* 0100: (Device Pin)*/ | ||
383 | PLL_CLKIN_GPI1, /* 0101: (Device Pin)*/ | ||
384 | PLL_CLKIN_HF_REF_CLK, /* 0110: (Device Pin)*/ | ||
385 | PLL_CLKIN_GPIO2, /* 0111: (Device Pin)*/ | ||
386 | PLL_CLKIN_GPI2, /* 1000: (Device Pin)*/ | ||
387 | PLL_CLKIN_MCLK2 /* 1001: (Device Pin)*/ | ||
388 | }; | ||
389 | |||
390 | /* ASI Specific Bit Clock Divider Input Options. | ||
391 | * Please refer to Page 4 Reg 11, Reg 27 and Reg 43 | ||
392 | */ | ||
393 | enum ASI_BDIV_CLKIN_OPTION { | ||
394 | BDIV_CLKIN_DAC_CLK = 0, /* 00 DAC_CLK */ | ||
395 | BDIV_CLKIN_DAC_MOD_CLK, /* 01 DAC_MOD_CLK */ | ||
396 | BDIV_CLKIN_ADC_CLK, /* 02 ADC_CLK */ | ||
397 | BDIV_CLKIN_ADC_MOD_CLK /* 03 ADC_MOD_CLK */ | ||
398 | }; | ||
399 | |||
400 | /* ASI Specific Bit Clock Output Mux Options. | ||
401 | * Please refer to Page 4 Reg 14, Reg 30 and Reg 46 | ||
402 | * Please note that we are not handling the Reserved | ||
403 | * cases here. | ||
404 | */ | ||
405 | enum ASI_BCLK_OPTION { | ||
406 | ASI1_BCLK_DIVIDER_OUTPUT = 0, /* 00 ASI1 Bit Clock Divider Output */ | ||
407 | ASI1_BCLK_INPUT, /* 01 ASI1 Bit Clock Input */ | ||
408 | ASI2_BCLK_DIVIDER_OUTPUT, /* 02 ASI2 Bit Clock Divider Output */ | ||
409 | ASI2_BCLK_INPUT, /* 03 ASI2 Bit Clock Input */ | ||
410 | ASI3_BCLK_DIVIDER_OUTPUT, /* 04 ASI3 Bit Clock Divider Output */ | ||
411 | ASI3_BBCLK_INPUT /* 05 ASi3 Bit Clock Input */ | ||
412 | }; | ||
413 | |||
414 | /* Above bits are to be configured after Shifting 4 bits */ | ||
415 | #define AIC3262_ASI_BCLK_MUX_SHIFT 4 | ||
416 | #define AIC3262_ASI_BCLK_MUX_MASK (BIT6 | BIT5 | BIT4) | ||
417 | #define AIC3262_ASI_WCLK_MUX_MASK (BIT2 | BIT1 | BIT0) | ||
418 | |||
419 | /* ASI Specific Word Clock Output Mux Options */ | ||
420 | enum ASI_WCLK_OPTION { | ||
421 | GENERATED_DAC_FS = 0, /* 00 WCLK = DAC_FS */ | ||
422 | GENERATED_ADC_FS = 1, /* 01 WCLK = ADC_FS */ | ||
423 | ASI1_WCLK_DIV_OUTPUT = 2, /* 02 WCLK = ASI1 WCLK_DIV_OUT */ | ||
424 | ASI1_WCLK_INPUT = 3, /* 03 WCLK = ASI1 WCLK Input */ | ||
425 | ASI2_WCLK_DIV_OUTPUT = 4, /* 04 WCLK = ASI2 WCLK_DIV_OUT */ | ||
426 | ASI2_WCLK_INPUT = 5, /* 05 WCLK = ASI2 WCLK Input */ | ||
427 | ASI3_WCLK_DIV_OUTPUT = 6, /* 06 WCLK = ASI3 WCLK_DIV_OUT */ | ||
428 | ASI3_WCLK_INPUT = 7 /* 07 WCLK = ASI3 WCLK Input */ | ||
429 | }; | ||
430 | |||
431 | /* ASI DAC Output Control Options */ | ||
432 | enum ASI_DAC_OUTPUT_OPTION { | ||
433 | DAC_PATH_OFF = 0, /* 00 DAC Datapath Off */ | ||
434 | DAC_PATH_LEFT, /* 01 DAC Datapath left Data */ | ||
435 | DAC_PATH_RIGHT, /* 02 DAC Datapath Right Data */ | ||
436 | }; | ||
437 | |||
438 | #define AIC3262_READ_COMMAND_WORD(addr) ((1 << 15) | (addr << 5)) | ||
439 | #define AIC3262_WRITE_COMMAND_WORD(addr) ((0 << 15) | (addr << 5)) | ||
440 | |||
441 | /* Shift the above options by so many bits */ | ||
442 | #define AIC3262_ASI_LDAC_PATH_SHIFT 6 | ||
443 | #define AIC3262_ASI_LDAC_PATH_MASK (BIT5 | BIT4) | ||
444 | #define AIC3262_ASI_RDAC_PATH_SHIFT 4 | ||
445 | #define AIC3262_ASI_RDAC_PATH_MASK (BIT7 | BIT6) | ||
446 | |||
447 | |||
448 | #define DAC_LR_MUTE_MASK 0xc | ||
449 | #define DAC_LR_MUTE 0xc | ||
450 | #define ENABLE_CLK_MASK 0x80 | ||
451 | #define ENABLE_CLK 0x80 | ||
452 | |||
453 | /* ASI specific ADC Input Control Options */ | ||
454 | enum ASI_ADC_INPUT_OPTION { | ||
455 | ADC_PATH_OFF = 0, /* 00 ASI Digital Output Disabled */ | ||
456 | ADC_PATH_MINIDSP_1, /* 01 ASI Digital O/P from miniDSP_A(L1,R1) */ | ||
457 | ADC_PATH_ASI1, /* 02 ASI Digital Output from ASI1 */ | ||
458 | ADC_PATH_ASI2, /* 03 ASI Digital Output from ASI2 */ | ||
459 | ADC_PATH_ASI3, /* 04 ASI Digital Output from ASI3 */ | ||
460 | ADC_PATH_MINIDSP_2, /* 05 ASI Digital O/P from miniDSP_A(L2,R2) */ | ||
461 | ADC_PATH_MINIDSP_3 /* 05 ASI Digital O/P from miniDSP_A(L3,R3) */ | ||
462 | }; | ||
463 | |||
464 | /* ASI Specific DOUT Pin Options */ | ||
465 | enum ASI_DOUT_OPTION { | ||
466 | ASI_OUTPUT = 0, /* 00 Default ASI Output */ | ||
467 | ASI1_INPUT, /* 01 ASI1 Data Input */ | ||
468 | ASI2_INPUT, /* 02 ASI2 Data Input */ | ||
469 | ASI3_INPUT /* 03 ASI3 Data Input */ | ||
470 | }; | ||
471 | |||
472 | #define AIC3262_ASI_DOUT_MASK (BIT1 | BIT0) | ||
473 | |||
474 | /* | ||
475 | ***************************************************************************** | ||
476 | * Structures Definitions | ||
477 | ***************************************************************************** | ||
478 | */ | ||
479 | #define AIC3262_MULTI_ASI_ACTIVE(x) (((x)->asiCtxt[0].asi_active) || \ | ||
480 | ((x)->asiCtxt[1].asi_active) || \ | ||
481 | ((x)->asiCtxt[2].asi_active)) | ||
482 | |||
483 | /* | ||
484 | *---------------------------------------------------------------------------- | ||
485 | * @struct aic3262_setup_data | | ||
486 | * i2c specific data setup for AIC3262. | ||
487 | * @field unsigned short |i2c_address | | ||
488 | * Unsigned short for i2c address. | ||
489 | *---------------------------------------------------------------------------- | ||
490 | */ | ||
491 | struct aic3262_setup_data { | ||
492 | unsigned short i2c_address; | ||
493 | }; | ||
494 | |||
495 | /* | ||
496 | *---------------------------------------------------------------------------- | ||
497 | * @struct aic3262_asi_data | ||
498 | * ASI specific data stored for each ASI Interface | ||
499 | * | ||
500 | * | ||
501 | *--------------------------------------------------------------------------- | ||
502 | */ | ||
503 | struct aic3262_asi_data { | ||
504 | u8 asi_active; /* ASI Active Flag */ | ||
505 | u8 master; /* Frame Master */ | ||
506 | u32 sampling_rate; /* Sampling Rate */ | ||
507 | enum ASI_BDIV_CLKIN_OPTION bclk_div_option; /* BCLK DIV Mux Option*/ | ||
508 | enum ASI_BCLK_OPTION bclk_output; /* BCLK Output Option*/ | ||
509 | enum ASI_WCLK_OPTION wclk_output; /* WCLK Output Option*/ | ||
510 | u8 bclk_div; /* BCLK Divider */ | ||
511 | u8 wclk_div; /* WCLK Divider */ | ||
512 | enum ASI_DAC_OUTPUT_OPTION left_dac_output; /* LDAC Path */ | ||
513 | enum ASI_DAC_OUTPUT_OPTION right_dac_output; /* RDAC Path */ | ||
514 | enum ASI_ADC_INPUT_OPTION adc_input; /* ADC Input Control */ | ||
515 | enum ASI_DOUT_OPTION dout_option; /* DOUT Option */ | ||
516 | u8 playback_mode; /* Playback Selected */ | ||
517 | u8 capture_mode; /* Record Selected */ | ||
518 | u8 port_muted; /* ASI Muted */ | ||
519 | u8 pcm_format; /* PCM Format */ | ||
520 | u8 word_len; /* Word Length */ | ||
521 | u8 offset1; /* Left Ch offset */ | ||
522 | u8 offset2; /* Right Ch Offset */ | ||
523 | }; | ||
524 | |||
525 | /* | ||
526 | *---------------------------------------------------------------------------- | ||
527 | * @struct aic3262_priv | | ||
528 | * AIC3262 priviate data structure to set the system clock, mode and | ||
529 | * page number. | ||
530 | * @field u32 | sysclk | | ||
531 | * system clock | ||
532 | * @field s32 | master | | ||
533 | * master/slave mode setting for AIC3262 | ||
534 | * @field u8 | book_no | | ||
535 | * book number. | ||
536 | * @field u8 | page_no | | ||
537 | * page number. Here, page 0 and page 1 are used. | ||
538 | *---------------------------------------------------------------------------- | ||
539 | */ | ||
540 | struct aic3262_priv { | ||
541 | enum snd_soc_control_type control_type; | ||
542 | struct aic326x_pdata *pdata; | ||
543 | struct snd_soc_codec codec; | ||
544 | u32 sysclk; | ||
545 | s32 master; | ||
546 | u8 book_no; | ||
547 | u8 page_no; | ||
548 | u8 process_flow; | ||
549 | u8 mute_codec; | ||
550 | u8 stream_status; | ||
551 | u32 active_count; | ||
552 | int current_dac_config[MAX_ASI_COUNT]; | ||
553 | int current_adc_config[MAX_ASI_COUNT]; | ||
554 | int current_config; | ||
555 | struct aic3262_asi_data asiCtxt[MAX_ASI_COUNT]; | ||
556 | enum AIC3262_PLL_OPTION aic3262_pllclkin_option; | ||
557 | u8 dac_clkin_option; | ||
558 | u8 adc_clkin_option; | ||
559 | int irq; | ||
560 | u8 dac_reg; | ||
561 | u8 adc_gain; | ||
562 | u8 hpl; | ||
563 | u8 hpr; | ||
564 | u8 rec_amp; | ||
565 | u8 rampr; | ||
566 | u8 spk_amp; | ||
567 | struct spi_device *spi; | ||
568 | struct snd_soc_jack *headset_jack; | ||
569 | struct input_dev *button_dev; | ||
570 | int codec_audio_mode; | ||
571 | #if defined(LOCAL_REG_ACCESS) | ||
572 | void *control_data; | ||
573 | #endif | ||
574 | }; | ||
575 | |||
576 | /* | ||
577 | *---------------------------------------------------------------------------- | ||
578 | * @struct aic3262_configs | | ||
579 | * AIC3262 initialization data which has register offset and register | ||
580 | * value. | ||
581 | * @field u8 | book_no | | ||
582 | * AIC3262 Book Number Offsets required for initialization.. | ||
583 | * @field u16 | reg_offset | | ||
584 | * AIC3262 Register offsets required for initialization.. | ||
585 | * @field u8 | reg_val | | ||
586 | * value to set the AIC3262 register to initialize the AIC3262. | ||
587 | *---------------------------------------------------------------------------- | ||
588 | */ | ||
589 | struct aic3262_configs { | ||
590 | u8 book_no; | ||
591 | u16 reg_offset; | ||
592 | u8 reg_val; | ||
593 | }; | ||
594 | |||
595 | /* | ||
596 | *---------------------------------------------------------------------------- | ||
597 | * @struct aic3262_rate_divs | | ||
598 | * Setting up the values to get different freqencies | ||
599 | * @field u32 | mclk | | ||
600 | * Master clock | ||
601 | * @field u32 | rate | | ||
602 | * sample rate | ||
603 | * @field u8 | p_val | | ||
604 | * value of p in PLL | ||
605 | * @field u32 | pll_j | | ||
606 | * value for pll_j | ||
607 | * @field u32 | pll_d | | ||
608 | * value for pll_d | ||
609 | * @field u32 | dosr | | ||
610 | * value to store dosr | ||
611 | * @field u32 | ndac | | ||
612 | * value for ndac | ||
613 | * @field u32 | mdac | | ||
614 | * value for mdac | ||
615 | * @field u32 | aosr | | ||
616 | * value for aosr | ||
617 | * @field u32 | nadc | | ||
618 | * value for nadc | ||
619 | * @field u32 | madc | | ||
620 | * value for madc | ||
621 | * @field u32 | blck_N | | ||
622 | * value for block N | ||
623 | * @field u32 | aic3262_configs | | ||
624 | * configurations for aic3262 register value | ||
625 | *---------------------------------------------------------------------------- | ||
626 | */ | ||
627 | struct aic3262_rate_divs { | ||
628 | u32 mclk; | ||
629 | u32 rate; | ||
630 | u8 p_val; | ||
631 | u8 pll_j; | ||
632 | u16 pll_d; | ||
633 | u16 dosr; | ||
634 | u8 ndac; | ||
635 | u8 mdac; | ||
636 | u8 aosr; | ||
637 | u8 nadc; | ||
638 | u8 madc; | ||
639 | u8 blck_N; | ||
640 | struct aic3262_configs codec_specific_regs[NO_FEATURE_REGS]; | ||
641 | }; | ||
642 | |||
643 | /* | ||
644 | ***************************************************************************** | ||
645 | * EXTERN DECLARATIONS | ||
646 | ***************************************************************************** | ||
647 | */ | ||
648 | /* | ||
649 | *---------------------------------------------------------------------------- | ||
650 | * @func aic326x_headset_detect | ||
651 | * This function help to setup the needed registers to | ||
652 | * enable the headset detection | ||
653 | * | ||
654 | */ | ||
655 | extern int aic326x_headset_detect(struct snd_soc_codec *codec, | ||
656 | struct snd_soc_jack *jack, int jack_type); | ||
657 | extern int aic326x_headset_button_init(struct snd_soc_codec *codec, | ||
658 | struct snd_soc_jack *jack, int jack_type); | ||
659 | |||
660 | extern u8 aic3262_read(struct snd_soc_codec *codec, u16 reg); | ||
661 | extern u16 aic3262_read_2byte(struct snd_soc_codec *codec, u16 reg); | ||
662 | extern int aic3262_reset_cache(struct snd_soc_codec *codec); | ||
663 | extern int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page); | ||
664 | extern int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value); | ||
665 | extern void aic3262_write_reg_cache(struct snd_soc_codec *codec, | ||
666 | u16 reg, u8 value); | ||
667 | extern int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book); | ||
668 | extern int reg_def_conf(struct snd_soc_codec *codec); | ||
669 | extern int i2c_verify_book0(struct snd_soc_codec *codec); | ||
670 | extern int poll_dac(struct snd_soc_codec *codec, int left_right, int on_off); | ||
671 | extern int poll_adc(struct snd_soc_codec *codec, int left_right, int on_off); | ||
672 | |||
673 | #ifdef CONFIG_MINI_DSP | ||
674 | extern int aic3262_minidsp_program(struct snd_soc_codec *codec); | ||
675 | extern int aic3262_add_minidsp_controls(struct snd_soc_codec *codec); | ||
676 | #endif | ||
677 | |||
678 | |||
679 | #ifdef MULTIBYTE_CONFIG_SUPPORT | ||
680 | extern int aic3262_add_multiconfig_controls(struct snd_soc_codec *codec); | ||
681 | #endif | ||
682 | |||
683 | #endif /* _TLV320AIC3262_H */ | ||
684 | |||