aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs
diff options
context:
space:
mode:
authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /sound/soc/codecs
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h96
-rw-r--r--sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h96
-rw-r--r--sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h96
-rw-r--r--sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h96
-rw-r--r--sound/soc/codecs/ads117x.h13
-rw-r--r--sound/soc/codecs/aic326x_tiload.c312
-rw-r--r--sound/soc/codecs/aic326x_tiload.h36
-rw-r--r--sound/soc/codecs/base_main_Rate48_pps_driver.h5979
-rw-r--r--sound/soc/codecs/first_rate_pps_driver.h5959
-rw-r--r--sound/soc/codecs/rt5639.c2444
-rw-r--r--sound/soc/codecs/rt5639.h2104
-rw-r--r--sound/soc/codecs/rt5640.c2546
-rw-r--r--sound/soc/codecs/rt5640.h2098
-rw-r--r--sound/soc/codecs/second_rate_pps_driver.h3626
-rw-r--r--sound/soc/codecs/tlv320aic326x.c4528
-rw-r--r--sound/soc/codecs/tlv320aic326x.h684
-rw-r--r--sound/soc/codecs/tlv320aic326x_mini-dsp.c1796
-rw-r--r--sound/soc/codecs/tlv320aic326x_mini-dsp.h128
-rw-r--r--sound/soc/codecs/tlv320aic326x_minidsp_config.c495
-rw-r--r--sound/soc/codecs/wm8994-tables.c3147
20 files changed, 36279 insertions, 0 deletions
diff --git a/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
new file mode 100644
index 00000000000..bbea174e3d2
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
1/*
2 * linux/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
3 *
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 *
15*/
16
17reg_value jazz_A_reg_values[] = {
18};
19#define miniDSP_A_reg_values_COEFF_START 0
20#define miniDSP_A_reg_values_COEFF_SIZE 0
21#define miniDSP_A_reg_values_INST_START 0
22#define miniDSP_A_reg_values_INST_SIZE 0
23
24reg_value jazz_D_reg_values[] = {
25 {0, 0x0},
26 {0x7F, 0x50},
27 { 0, 0x01},
28 { 36, 0xB0},
29 { 37, 0x00},
30 { 38, 0x00},
31 { 39, 0x00},
32 { 40, 0xE0},
33 { 41, 0x00},
34 { 42, 0x00},
35 { 43, 0x00},
36 { 44, 0x08},
37 { 45, 0x00},
38 { 46, 0x00},
39 { 47, 0x00},
40 { 48, 0x40},
41 { 49, 0x00},
42 { 50, 0x00},
43 { 51, 0x00},
44 { 52, 0x58},
45 { 53, 0x00},
46 { 54, 0x00},
47 { 55, 0x00},
48 { 0, 0x09},
49 {100, 0xB0},
50 {101, 0x00},
51 {102, 0x00},
52 {103, 0x00},
53 {104, 0xE0},
54 {105, 0x00},
55 {106, 0x00},
56 {107, 0x00},
57 {108, 0x08},
58 {109, 0x00},
59 {110, 0x00},
60 {111, 0x00},
61 {112, 0x40},
62 {113, 0x00},
63 {114, 0x00},
64 {115, 0x00},
65 {116, 0x58},
66 {117, 0x00},
67 {118, 0x00},
68 {119, 0x00},
69 { 0, 0x0},
70 { 0x7F, 0x3C},
71 { 0, 0x01},
72 { 24, 0xB0},
73 { 25, 0x00},
74 { 26, 0x00},
75 { 27, 0x00},
76 { 28, 0xE0},
77 { 29, 0x00},
78 { 30, 0x00},
79 { 31, 0x00},
80 { 32, 0x08},
81 { 33, 0x00},
82 { 34, 0x00},
83 { 35, 0x00},
84 { 36, 0x40},
85 { 37, 0x00},
86 { 38, 0x00},
87 { 39, 0x00},
88 { 40, 0x58},
89 { 41, 0x00},
90 { 42, 0x00},
91 { 43, 0x00},
92};
93#define miniDSP_D_reg_values_COEFF_START 0
94#define miniDSP_D_reg_values_COEFF_SIZE 67
95#define miniDSP_D_reg_values_INST_START 67
96#define miniDSP_D_reg_values_INST_SIZE 0
diff --git a/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
new file mode 100644
index 00000000000..80cc3416c34
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
1/*
2 * linux/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
3 *
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 *
15*/
16
17reg_value main_A_reg_values[] = {
18};
19#define miniDSP_A_reg_values_COEFF_START 0
20#define miniDSP_A_reg_values_COEFF_SIZE 0
21#define miniDSP_A_reg_values_INST_START 0
22#define miniDSP_A_reg_values_INST_SIZE 0
23
24reg_value main_D_reg_values[] = {
25 { 0, 0x0},
26 { 0x7F, 0x50},
27 { 0, 0x01},
28 { 36, 0x00},
29 { 37, 0x00},
30 { 38, 0x00},
31 { 39, 0x00},
32 { 40, 0x00},
33 { 41, 0x00},
34 { 42, 0x00},
35 { 43, 0x00},
36 { 44, 0x00},
37 { 45, 0x00},
38 { 46, 0x00},
39 { 47, 0x00},
40 { 48, 0x00},
41 { 49, 0x00},
42 { 50, 0x00},
43 { 51, 0x00},
44 { 52, 0x00},
45 { 53, 0x00},
46 { 54, 0x00},
47 { 55, 0x00},
48 { 0, 0x09},
49 {100, 0x00},
50 {101, 0x00},
51 {102, 0x00},
52 {103, 0x00},
53 {104, 0x00},
54 {105, 0x00},
55 {106, 0x00},
56 {107, 0x00},
57 {108, 0x00},
58 {109, 0x00},
59 {110, 0x00},
60 {111, 0x00},
61 {112, 0x00},
62 {113, 0x00},
63 {114, 0x00},
64 {115, 0x00},
65 {116, 0x00},
66 {117, 0x00},
67 {118, 0x00},
68 {119, 0x00},
69 { 0, 0x0},
70 { 0x7F, 0x3C},
71 { 0, 0x01},
72 { 24, 0x00},
73 { 25, 0x00},
74 { 26, 0x00},
75 { 27, 0x00},
76 { 28, 0x00},
77 { 29, 0x00},
78 { 30, 0x00},
79 { 31, 0x00},
80 { 32, 0x00},
81 { 33, 0x00},
82 { 34, 0x00},
83 { 35, 0x00},
84 { 36, 0x00},
85 { 37, 0x00},
86 { 38, 0x00},
87 { 39, 0x00},
88 { 40, 0x00},
89 { 41, 0x00},
90 { 42, 0x00},
91 { 43, 0x00},
92};
93#define miniDSP_D_reg_values_COEFF_START 0
94#define miniDSP_D_reg_values_COEFF_SIZE 67
95#define miniDSP_D_reg_values_INST_START 67
96#define miniDSP_D_reg_values_INST_SIZE 0
diff --git a/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
new file mode 100644
index 00000000000..c2c3d0a1df8
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
1/*
2 * linux/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
3 *
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 *
15*/
16
17reg_value pop_A_reg_values[] = {
18};
19#define miniDSP_A_reg_values_COEFF_START 0
20#define miniDSP_A_reg_values_COEFF_SIZE 0
21#define miniDSP_A_reg_values_INST_START 0
22#define miniDSP_A_reg_values_INST_SIZE 0
23
24reg_value pop_D_reg_values[] = {
25 { 0, 0x0},
26 { 0x7F, 0x50},
27 { 0, 0x01},
28 { 36, 0x40},
29 { 37, 0x00},
30 { 38, 0x00},
31 { 39, 0x00},
32 { 40, 0x20},
33 { 41, 0x00},
34 { 42, 0x00},
35 { 43, 0x00},
36 { 44, 0x00},
37 { 45, 0x00},
38 { 46, 0x00},
39 { 47, 0x00},
40 { 48, 0xD8},
41 { 49, 0x00},
42 { 50, 0x00},
43 { 51, 0x00},
44 { 52, 0xB0},
45 { 53, 0x00},
46 { 54, 0x00},
47 { 55, 0x00},
48 { 0, 0x09},
49 {100, 0x40},
50 {101, 0x00},
51 {102, 0x00},
52 {103, 0x00},
53 {104, 0x20},
54 {105, 0x00},
55 {106, 0x00},
56 {107, 0x00},
57 {108, 0x00},
58 {109, 0x00},
59 {110, 0x00},
60 {111, 0x00},
61 {112, 0xD8},
62 {113, 0x00},
63 {114, 0x00},
64 {115, 0x00},
65 {116, 0xB0},
66 {117, 0x00},
67 {118, 0x00},
68 {119, 0x00},
69 { 0, 0x0},
70 { 0x7F, 0x3C},
71 { 0, 0x01},
72 { 24, 0x40},
73 { 25, 0x00},
74 { 26, 0x00},
75 { 27, 0x00},
76 { 28, 0x20},
77 { 29, 0x00},
78 { 30, 0x00},
79 { 31, 0x00},
80 { 32, 0x00},
81 { 33, 0x00},
82 { 34, 0x00},
83 { 35, 0x00},
84 { 36, 0xD8},
85 { 37, 0x00},
86 { 38, 0x00},
87 { 39, 0x00},
88 { 40, 0xB0},
89 { 41, 0x00},
90 { 42, 0x00},
91 { 43, 0x00},
92};
93#define miniDSP_D_reg_values_COEFF_START 0
94#define miniDSP_D_reg_values_COEFF_SIZE 67
95#define miniDSP_D_reg_values_INST_START 67
96#define miniDSP_D_reg_values_INST_SIZE 0
diff --git a/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
new file mode 100644
index 00000000000..954c7c37478
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
1/*
2 * linux/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
3 *
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 *
15*/
16
17reg_value rock_A_reg_values[] = {
18};
19#define miniDSP_A_reg_values_COEFF_START 0
20#define miniDSP_A_reg_values_COEFF_SIZE 0
21#define miniDSP_A_reg_values_INST_START 0
22#define miniDSP_A_reg_values_INST_SIZE 0
23
24reg_value rock_D_reg_values[] = {
25 { 0, 0x0},
26 { 0x7F, 0x50},
27 { 0, 0x01},
28 { 36, 0x58},
29 { 37, 0x00},
30 { 38, 0x00},
31 { 39, 0x00},
32 { 40, 0x30},
33 { 41, 0x00},
34 { 42, 0x00},
35 { 43, 0x00},
36 { 44, 0xD8},
37 { 45, 0x00},
38 { 46, 0x00},
39 { 47, 0x00},
40 { 48, 0xF0},
41 { 49, 0x00},
42 { 50, 0x00},
43 { 51, 0x00},
44 { 52, 0x60},
45 { 53, 0x00},
46 { 54, 0x00},
47 { 55, 0x00},
48 { 0, 0x09},
49 {100, 0x58},
50 {101, 0x00},
51 {102, 0x00},
52 {103, 0x00},
53 {104, 0x30},
54 {105, 0x00},
55 {106, 0x00},
56 {107, 0x00},
57 {108, 0xD8},
58 {109, 0x00},
59 {110, 0x00},
60 {111, 0x00},
61 {112, 0xF0},
62 {113, 0x00},
63 {114, 0x00},
64 {115, 0x00},
65 {116, 0x60},
66 {117, 0x00},
67 {118, 0x00},
68 {119, 0x00},
69 { 0, 0x0},
70 { 0x7F, 0x3C},
71 { 0, 0x01},
72 { 24, 0x58},
73 { 25, 0x00},
74 { 26, 0x00},
75 { 27, 0x00},
76 { 28, 0x30},
77 { 29, 0x00},
78 { 30, 0x00},
79 { 31, 0x00},
80 { 32, 0xD8},
81 { 33, 0x00},
82 { 34, 0x00},
83 { 35, 0x00},
84 { 36, 0xF0},
85 { 37, 0x00},
86 { 38, 0x00},
87 { 39, 0x00},
88 { 40, 0x60},
89 { 41, 0x00},
90 { 42, 0x00},
91 { 43, 0x00},
92};
93#define miniDSP_D_reg_values_COEFF_START 0
94#define miniDSP_D_reg_values_COEFF_SIZE 67
95#define miniDSP_D_reg_values_INST_START 67
96#define miniDSP_D_reg_values_INST_SIZE 0
diff --git a/sound/soc/codecs/ads117x.h b/sound/soc/codecs/ads117x.h
new file mode 100644
index 00000000000..3ce02861400
--- /dev/null
+++ b/sound/soc/codecs/ads117x.h
@@ -0,0 +1,13 @@
1/*
2 * ads117x.h -- Driver for ads1174/8 ADC chips
3 *
4 * Copyright 2009 ShotSpotter Inc.
5 * Author: Graeme Gregory <gg@slimlogic.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12extern struct snd_soc_dai_driver ads117x_dai;
13extern struct snd_soc_codec_driver soc_codec_dev_ads117x;
diff --git a/sound/soc/codecs/aic326x_tiload.c b/sound/soc/codecs/aic326x_tiload.c
new file mode 100644
index 00000000000..00aa4d4ce7d
--- /dev/null
+++ b/sound/soc/codecs/aic326x_tiload.c
@@ -0,0 +1,312 @@
1/*
2 * linux/sound/soc/codecs/AIC3262_tiload.c
3 *
4 *
5 * Copyright (C) 2010 Texas Instruments, Inc.
6 *
7 *
8 *
9 * This package is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 * History:
18 *
19 * Rev 0.1 Tiload support 16-09-2010
20 *
21 * The Tiload programming support is added to AIC3262.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/fs.h>
30#include <linux/types.h>
31#include <linux/kdev_t.h>
32#include <linux/cdev.h>
33#include <linux/device.h>
34#include <asm/io.h>
35#include <linux/delay.h>
36#include <linux/i2c.h>
37#include <linux/platform_device.h>
38#include <sound/soc.h>
39#include <sound/control.h>
40
41#include "tlv320aic326x.h"
42#include "aic326x_tiload.h"
43
44/* enable debug prints in the driver */
45#define DEBUG
46//#undef DEBUG
47
48#ifdef DEBUG
49#define dprintk(x...) printk(x)
50#else
51#define dprintk(x...)
52#endif
53
54#ifdef AIC3262_TiLoad
55
56/* Function prototypes */
57#ifdef REG_DUMP_aic3262
58static void aic3262_dump_page(struct i2c_client *i2c, u8 page);
59#endif
60
61/* externs */
62extern int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page);
63extern int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book);
64extern int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value);
65int aic3262_driver_init(struct snd_soc_codec *codec);
66/************** Dynamic aic3262 driver, TI LOAD support ***************/
67
68static struct cdev *aic3262_cdev;
69static int aic3262_major = 0; /* Dynamic allocation of Mjr No. */
70static int aic3262_opened = 0; /* Dynamic allocation of Mjr No. */
71static struct snd_soc_codec *aic3262_codec;
72struct class *tiload_class;
73static unsigned int magic_num = 0xE0;
74
75/******************************** Debug section *****************************/
76
77#ifdef REG_DUMP_aic3262
78/*
79 *----------------------------------------------------------------------------
80 * Function : aic3262_dump_page
81 * Purpose : Read and display one codec register page, for debugging purpose
82 *----------------------------------------------------------------------------
83 */
84static void aic3262_dump_page(struct i2c_client *i2c, u8 page)
85{
86 int i;
87 u8 data;
88 u8 test_page_array[8];
89
90 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
91 aic3262_change_page(codec, page);
92
93 data = 0x0;
94
95 i2c_master_send(i2c, data, 1);
96 i2c_master_recv(i2c, test_page_array, 8);
97
98 printk("\n------- aic3262 PAGE %d DUMP --------\n", page);
99 for (i = 0; i < 8; i++) {
100 printk(" [ %d ] = 0x%x\n", i, test_page_array[i]);
101 }
102}
103#endif
104
105/*
106 *----------------------------------------------------------------------------
107 * Function : tiload_open
108 *
109 * Purpose : open method for aic3262-tiload programming interface
110 *----------------------------------------------------------------------------
111 */
112static int tiload_open(struct inode *in, struct file *filp)
113{
114 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
115 if (aic3262_opened) {
116 printk("%s device is already opened\n", "aic3262");
117 printk("%s: only one instance of driver is allowed\n",
118 "aic3262");
119 return -1;
120 }
121 aic3262_opened++;
122 return 0;
123}
124
125/*
126 *----------------------------------------------------------------------------
127 * Function : tiload_release
128 *
129 * Purpose : close method for aic3262_tilaod programming interface
130 *----------------------------------------------------------------------------
131 */
132static int tiload_release(struct inode *in, struct file *filp)
133{
134 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
135 aic3262_opened--;
136 return 0;
137}
138
139/*
140 *----------------------------------------------------------------------------
141 * Function : tiload_read
142 *
143 * Purpose : read method for mini dsp programming interface
144 *----------------------------------------------------------------------------
145 */
146static ssize_t tiload_read(struct file *file, char __user * buf,
147 size_t count, loff_t * offset)
148{
149 static char rd_data[8];
150 char reg_addr;
151 size_t size;
152 #ifdef DEBUG
153 int i;
154 #endif
155 struct i2c_client *i2c = aic3262_codec->control_data;
156
157 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
158 if (count > 128) {
159 printk("Max 128 bytes can be read\n");
160 count = 128;
161 }
162
163 /* copy register address from user space */
164 size = copy_from_user(&reg_addr, buf, 1);
165 if (size != 0) {
166 printk("read: copy_from_user failure\n");
167 return -1;
168 }
169 /* Send the address to device thats is to be read */
170
171 if (i2c_master_send(i2c, &reg_addr, 1) != 1) {
172 dprintk("Can not write register address\n");
173 return -1;
174 }
175 /* read the codec device registers */
176 size = i2c_master_recv(i2c, rd_data, count);
177#ifdef DEBUG
178 printk(KERN_ERR "read size = %d, reg_addr= %x , count = %d\n",
179 (int)size, reg_addr, (int)count);
180 for (i = 0; i < (int)size; i++) {
181 printk(KERN_ERR "rd_data[%d]=%x\n", i, rd_data[i]);
182 }
183#endif
184 if (size != count) {
185 printk("read %d registers from the codec\n", size);
186 }
187
188 if (copy_to_user(buf, rd_data, size) != 0) {
189 dprintk("copy_to_user failed\n");
190 return -1;
191 }
192
193 return size;
194}
195
196/*
197 *----------------------------------------------------------------------------
198 * Function : tiload_write
199 *
200 * Purpose : write method for aic3262_tiload programming interface
201 *----------------------------------------------------------------------------
202 */
203static ssize_t tiload_write(struct file *file, const char __user * buf,
204 size_t count, loff_t * offset)
205{
206 static char wr_data[8];
207 u8 pg_no;
208 #ifdef DEBUG
209 int i;
210 #endif
211 struct i2c_client *i2c = aic3262_codec->control_data;
212 struct aic3262_priv *aic3262_private = snd_soc_codec_get_drvdata(aic3262_codec);
213
214 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
215 /* copy buffer from user space */
216 if (copy_from_user(wr_data, buf, count)) {
217 printk("copy_from_user failure\n");
218 return -1;
219 }
220#ifdef DEBUG
221 printk(KERN_ERR "write size = %d\n", (int)count);
222 for (i = 0; i < (int)count; i++) {
223 printk(KERN_INFO "\nwr_data[%d]=%x\n", i, wr_data[i]);
224 }
225#endif
226 if (wr_data[0] == 0) {
227 aic3262_change_page(aic3262_codec, wr_data[1]);
228 return count;
229 }
230 pg_no = aic3262_private->page_no;
231
232 if ((wr_data[0] == 127) && (pg_no == 0)) {
233 aic3262_change_book(aic3262_codec, wr_data[1]);
234 return count;
235 }
236 return i2c_master_send(i2c, wr_data, count);
237}
238
239static int tiload_ioctl( struct file *filp,
240 unsigned int cmd, unsigned long arg)
241{
242 int num = 0;
243 void __user *argp = (void __user *)arg;
244 if (_IOC_TYPE(cmd) != aic3262_IOC_MAGIC)
245 return -ENOTTY;
246
247 dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
248 switch (cmd) {
249 case aic3262_IOMAGICNUM_GET:
250 num = copy_to_user(argp, &magic_num, sizeof(int));
251 break;
252 case aic3262_IOMAGICNUM_SET:
253 num = copy_from_user(&magic_num, argp, sizeof(int));
254 break;
255 }
256 return num;
257}
258
259/*********** File operations structure for aic3262-tiload programming *************/
260static struct file_operations aic3262_fops = {
261 .owner = THIS_MODULE,
262 .open = tiload_open,
263 .release = tiload_release,
264 .read = tiload_read,
265 .write = tiload_write,
266 .unlocked_ioctl = tiload_ioctl,
267};
268
269/*
270 *----------------------------------------------------------------------------
271 * Function : aic3262_driver_init
272 *
273 * Purpose : Register a char driver for dynamic aic3262-tiload programming
274 *----------------------------------------------------------------------------
275 */
276int aic3262_driver_init(struct snd_soc_codec *codec)
277{
278 int result;
279
280 dev_t dev = MKDEV(aic3262_major, 0);
281 printk("TiLoad DRIVER : %s\n", __FUNCTION__);
282 aic3262_codec = codec;
283
284 printk("allocating dynamic major number\n");
285
286 result = alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME);
287 if (result < 0) {
288 printk("cannot allocate major number %d\n", aic3262_major);
289 return result;
290 }
291 tiload_class = class_create(THIS_MODULE, DEVICE_NAME);
292 aic3262_major = MAJOR(dev);
293 printk("allocated Major Number: %d\n", aic3262_major);
294
295 aic3262_cdev = cdev_alloc();
296 cdev_init(aic3262_cdev, &aic3262_fops);
297 aic3262_cdev->owner = THIS_MODULE;
298 aic3262_cdev->ops = &aic3262_fops;
299
300 if (cdev_add(aic3262_cdev, dev, 1) < 0) {
301 dprintk("aic3262_driver: cdev_add failed \n");
302 unregister_chrdev_region(dev, 1);
303 aic3262_cdev = NULL;
304 return 1;
305 }
306 printk("Registered aic3262 TiLoad driver, Major number: %d \n",
307 aic3262_major);
308 //class_device_create(tiload_class, NULL, dev, NULL, DEVICE_NAME, 0);
309 return 0;
310}
311
312#endif
diff --git a/sound/soc/codecs/aic326x_tiload.h b/sound/soc/codecs/aic326x_tiload.h
new file mode 100644
index 00000000000..6621a4127b1
--- /dev/null
+++ b/sound/soc/codecs/aic326x_tiload.h
@@ -0,0 +1,36 @@
1/*
2 * linux/sound/soc/codecs/aic3262_tiload.h
3 *
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 *
8 *
9 * This package is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 * History:
18 *
19 *
20 *
21 *
22 */
23
24#ifndef _AIC3262_TILOAD_H
25#define _AIC3262_TILOAD_H
26
27/* typedefs required for the included header files */
28typedef char *string;
29
30/* defines */
31#define DEVICE_NAME "tiload_node"
32#define aic3262_IOC_MAGIC 0xE0
33#define aic3262_IOMAGICNUM_GET _IOR(aic3262_IOC_MAGIC, 1, int)
34#define aic3262_IOMAGICNUM_SET _IOW(aic3262_IOC_MAGIC, 2, int)
35
36#endif
diff --git a/sound/soc/codecs/base_main_Rate48_pps_driver.h b/sound/soc/codecs/base_main_Rate48_pps_driver.h
new file mode 100644
index 00000000000..4d6f227cc42
--- /dev/null
+++ b/sound/soc/codecs/base_main_Rate48_pps_driver.h
@@ -0,0 +1,5979 @@
1static control base_speaker_SRS_MUX_controls[] = {
2/*{4,28,1,0},
3{4,36,1,1},
4{4,112,1,2}*/
5};
6
7static char * base_speaker_SRS_MUX_control_names[] = {
8/*"Stereo_Mux_1",
9"Stereo_Mux_3",
10"Stereo_Mux_4"*/
11};
12
13static control base_speaker_SRS_VOLUME_controls[] = {
14};
15
16static char * base_speaker_SRS_VOLUME_control_names[] = {
17};
18
19/*//INSTRUCTIONS & COEFFICIENTS
20typedef struct {
21 u8 reg_off;
22 u8 reg_val;
23} reg_value;*/
24
25static char * base_speaker_SRS_REG_Section_names[] = {
26 "miniDSP_A_reg_values",
27 "miniDSP_D_reg_values",
28};
29
30reg_value base_speaker_SRS_REG_init_Section_program[] = {
31 { 0,0x0},
32 { 0x7F,0x00},
33// # Set AutoINC
34 {121,0x01},
35 { 0x7F,0x78},
36// # reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled
37 { 50,0x88},
38 { 0x7F,0x64},
39// # reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled
40 { 50,0xA4},
41 { 0x7F,0x78},
42// # reg[120][0][24]=0x80
43 { 24,0x80},
44};
45
46reg_value base_speaker_SRS_REG_post_Section_program[] = {
47 { 0,0x0},
48 { 0x7F,0x28},
49// # reg[40][0][1] = 0x04 ; adaptive mode for ADC
50 { 1,0x04},
51 { 0x7F,0x50},
52// # reg[80][0][1] = 0x04 ; adaptive mode for DAC
53 { 1,0x04},
54 { 0x7F,0x64},
55// # reg[100][0][48] = 4
56 { 48,0x04},
57// # reg[100][0][49] = 0
58 { 49,0x00},
59 { 0x7F,0x78},
60// # reg[120][0][48] = 4
61 { 48,0x04},
62// # reg[120][0][49] = 0
63 { 49,0x00},
64 { 0x7F,0x64},
65// # reg[100][0][20] = 0x00 ; Disable ADC double buffer mode
66 { 20,0x00},
67 { 0x7F,0x78},
68// # reg[120][0][20] = 0x00 ; Disable DAC double buffer mode
69 { 20,0x00},
70
71};
72
73reg_value base_speaker_SRS_miniDSP_A_reg_values[] = {
74 { 0,0x0},
75 { 0x7F,0x28},
76 { 0,0x01},
77 { 8,0x00},
78 { 9,0xA7},
79 { 10,0xF8},
80 { 11,0x00},
81 { 12,0x7E},
82 { 13,0xB0},
83 { 14,0x10},
84 { 15,0x00},
85 { 16,0x7F},
86 { 17,0xFF},
87 { 18,0xFF},
88 { 19,0x00},
89 { 20,0x00},
90 { 21,0x00},
91 { 22,0x00},
92 { 23,0x00},
93 { 24,0x00},
94 { 25,0x00},
95 { 26,0x00},
96 { 27,0x00},
97 { 28,0xFF},
98 { 29,0xFF},
99 { 30,0xFF},
100 { 31,0x00},
101 { 32,0x80},
102 { 33,0x00},
103 { 34,0x00},
104 { 35,0x00},
105 { 36,0x7F},
106 { 37,0xFF},
107 { 38,0xFF},
108 { 39,0x00},
109 { 40,0x40},
110 { 41,0x00},
111 { 42,0x00},
112 { 43,0x00},
113 { 44,0x00},
114 { 45,0x00},
115 { 46,0x00},
116 { 47,0x00},
117 { 48,0xFF},
118 { 49,0x9E},
119 { 50,0x00},
120 { 51,0x00},
121 { 52,0xF7},
122 { 53,0x10},
123 { 54,0x00},
124 { 55,0x00},
125 { 56,0x26},
126 { 57,0xF0},
127 { 58,0x00},
128 { 59,0x00},
129 { 60,0x02},
130 { 61,0x61},
131 { 62,0x00},
132 { 63,0x00},
133 { 64,0x40},
134 { 65,0x02},
135 { 66,0x00},
136 { 67,0x00},
137 { 68,0xFF},
138 { 69,0xFC},
139 { 70,0x00},
140 { 71,0x00},
141 { 72,0xFF},
142 { 73,0xFD},
143 { 74,0x00},
144 { 75,0x00},
145 { 76,0xFF},
146 { 77,0xE5},
147 { 78,0x00},
148 { 79,0x00},
149 { 80,0xFF},
150 { 81,0xA7},
151 { 82,0x00},
152 { 83,0x00},
153 { 84,0xFF},
154 { 85,0xC7},
155 { 86,0x00},
156 { 87,0x00},
157 { 88,0xFF},
158 { 89,0xCE},
159 { 90,0x00},
160 { 91,0x00},
161 { 92,0xFF},
162 { 93,0xFE},
163 { 94,0x00},
164 { 95,0x00},
165 { 96,0xFE},
166 { 97,0xF7},
167 { 98,0x00},
168 { 99,0x00},
169 {100,0xFF},
170 {101,0x46},
171 {102,0x00},
172 {103,0x00},
173 {104,0xFF},
174 {105,0x22},
175 {106,0x00},
176 {107,0x00},
177 {108,0x7F},
178 {109,0xFF},
179 {110,0xFF},
180 {111,0x00},
181 {112,0x00},
182 {113,0x00},
183 {114,0x00},
184 {115,0x00},
185 {116,0x00},
186 {117,0x00},
187 {118,0x00},
188 {119,0x00},
189 {120,0x00},
190 {121,0x00},
191 {122,0x00},
192 {123,0x00},
193 {124,0x00},
194 {125,0x00},
195 {126,0x00},
196 {127,0x00},
197 { 0,0x02},
198 { 8,0xFF},
199 { 9,0x0F},
200 { 10,0x00},
201 { 11,0x00},
202 { 12,0xFA},
203 { 13,0x8C},
204 { 14,0x00},
205 { 15,0x00},
206 { 16,0xF5},
207 { 17,0x08},
208 { 18,0x00},
209 { 19,0x00},
210 { 20,0xFD},
211 { 21,0x92},
212 { 22,0x00},
213 { 23,0x00},
214 { 24,0xF3},
215 { 25,0xA3},
216 { 26,0x00},
217 { 27,0x00},
218 { 28,0x03},
219 { 29,0xB3},
220 { 30,0x00},
221 { 31,0x00},
222 { 32,0x00},
223 { 33,0x33},
224 { 34,0x00},
225 { 35,0x00},
226 { 36,0x00},
227 { 37,0x71},
228 { 38,0x00},
229 { 39,0x00},
230 { 40,0x40},
231 { 41,0x60},
232 { 42,0x00},
233 { 43,0x00},
234 { 44,0x00},
235 { 45,0xE2},
236 { 46,0x00},
237 { 47,0x00},
238 { 48,0x00},
239 { 49,0xC6},
240 { 50,0x00},
241 { 51,0x00},
242 { 52,0x00},
243 { 53,0x87},
244 { 54,0x00},
245 { 55,0x00},
246 { 56,0x00},
247 { 57,0x0F},
248 { 58,0x00},
249 { 59,0x00},
250 { 60,0x00},
251 { 61,0x0A},
252 { 62,0x00},
253 { 63,0x00},
254 { 64,0x00},
255 { 65,0x02},
256 { 66,0x00},
257 { 67,0x00},
258 { 68,0x01},
259 { 69,0x81},
260 { 70,0x00},
261 { 71,0x00},
262 { 72,0x18},
263 { 73,0x89},
264 { 74,0x00},
265 { 75,0x00},
266 { 76,0x07},
267 { 77,0xFB},
268 { 78,0x00},
269 { 79,0x00},
270 { 80,0x03},
271 { 81,0xBE},
272 { 82,0x00},
273 { 83,0x00},
274 { 0,0x09},
275 { 72,0x00},
276 { 73,0xA7},
277 { 74,0xF8},
278 { 75,0x00},
279 { 76,0x7E},
280 { 77,0xB0},
281 { 78,0x10},
282 { 79,0x00},
283 { 80,0x7F},
284 { 81,0xFF},
285 { 82,0xFF},
286 { 83,0x00},
287 { 84,0x00},
288 { 85,0x00},
289 { 86,0x00},
290 { 87,0x00},
291 { 88,0x00},
292 { 89,0x00},
293 { 90,0x00},
294 { 91,0x00},
295 { 92,0xFF},
296 { 93,0xFF},
297 { 94,0xFF},
298 { 95,0x00},
299 { 96,0x80},
300 { 97,0x00},
301 { 98,0x00},
302 { 99,0x00},
303 {100,0x7F},
304 {101,0xFF},
305 {102,0xFF},
306 {103,0x00},
307 {104,0x40},
308 {105,0x00},
309 {106,0x00},
310 {107,0x00},
311 {108,0x00},
312 {109,0x00},
313 {110,0x00},
314 {111,0x00},
315 {112,0xFF},
316 {113,0x9E},
317 {114,0x00},
318 {115,0x00},
319 {116,0xF7},
320 {117,0x10},
321 {118,0x00},
322 {119,0x00},
323 {120,0x26},
324 {121,0xF0},
325 {122,0x00},
326 {123,0x00},
327 {124,0x02},
328 {125,0x61},
329 {126,0x00},
330 {127,0x00},
331 { 0,0x0A},
332 { 8,0x40},
333 { 9,0x02},
334 { 10,0x00},
335 { 11,0x00},
336 { 12,0xFF},
337 { 13,0xFC},
338 { 14,0x00},
339 { 15,0x00},
340 { 16,0xFF},
341 { 17,0xFD},
342 { 18,0x00},
343 { 19,0x00},
344 { 20,0xFF},
345 { 21,0xE5},
346 { 22,0x00},
347 { 23,0x00},
348 { 24,0xFF},
349 { 25,0xA7},
350 { 26,0x00},
351 { 27,0x00},
352 { 28,0xFF},
353 { 29,0xC7},
354 { 30,0x00},
355 { 31,0x00},
356 { 32,0xFF},
357 { 33,0xCE},
358 { 34,0x00},
359 { 35,0x00},
360 { 36,0xFF},
361 { 37,0xFE},
362 { 38,0x00},
363 { 39,0x00},
364 { 40,0xFE},
365 { 41,0xF7},
366 { 42,0x00},
367 { 43,0x00},
368 { 44,0xFF},
369 { 45,0x46},
370 { 46,0x00},
371 { 47,0x00},
372 { 48,0xFF},
373 { 49,0x22},
374 { 50,0x00},
375 { 51,0x00},
376 { 52,0x7F},
377 { 53,0xFF},
378 { 54,0xFF},
379 { 55,0x00},
380 { 56,0x00},
381 { 57,0x00},
382 { 58,0x00},
383 { 59,0x00},
384 { 60,0x00},
385 { 61,0x00},
386 { 62,0x00},
387 { 63,0x00},
388 { 64,0x00},
389 { 65,0x00},
390 { 66,0x00},
391 { 67,0x00},
392 { 68,0x00},
393 { 69,0x00},
394 { 70,0x00},
395 { 71,0x00},
396 { 72,0xFF},
397 { 73,0x0F},
398 { 74,0x00},
399 { 75,0x00},
400 { 76,0xFA},
401 { 77,0x8C},
402 { 78,0x00},
403 { 79,0x00},
404 { 80,0xF5},
405 { 81,0x08},
406 { 82,0x00},
407 { 83,0x00},
408 { 84,0xFD},
409 { 85,0x92},
410 { 86,0x00},
411 { 87,0x00},
412 { 88,0xF3},
413 { 89,0xA3},
414 { 90,0x00},
415 { 91,0x00},
416 { 92,0x03},
417 { 93,0xB3},
418 { 94,0x00},
419 { 95,0x00},
420 { 96,0x00},
421 { 97,0x33},
422 { 98,0x00},
423 { 99,0x00},
424 {100,0x00},
425 {101,0x71},
426 {102,0x00},
427 {103,0x00},
428 {104,0x40},
429 {105,0x60},
430 {106,0x00},
431 {107,0x00},
432 {108,0x00},
433 {109,0xE2},
434 {110,0x00},
435 {111,0x00},
436 {112,0x00},
437 {113,0xC6},
438 {114,0x00},
439 {115,0x00},
440 {116,0x00},
441 {117,0x87},
442 {118,0x00},
443 {119,0x00},
444 {120,0x00},
445 {121,0x0F},
446 {122,0x00},
447 {123,0x00},
448 {124,0x00},
449 {125,0x0A},
450 {126,0x00},
451 {127,0x00},
452 { 0,0x0B},
453 { 8,0x00},
454 { 9,0x02},
455 { 10,0x00},
456 { 11,0x00},
457 { 12,0x01},
458 { 13,0x81},
459 { 14,0x00},
460 { 15,0x00},
461 { 16,0x18},
462 { 17,0x89},
463 { 18,0x00},
464 { 19,0x00},
465 { 20,0x07},
466 { 21,0xFB},
467 { 22,0x00},
468 { 23,0x00},
469 { 24,0x03},
470 { 25,0xBE},
471 { 26,0x00},
472 { 27,0x00},
473 { 0,0x0},
474 { 0x7F,0x14},
475 { 0,0x01},
476 { 8,0xC0},
477 { 9,0x00},
478 { 10,0x00},
479 { 11,0x00},
480 { 12,0xC0},
481 { 13,0x00},
482 { 14,0x00},
483 { 15,0x00},
484 { 0,0x0},
485 { 0x7F,0x64},
486 { 0,0x01},
487 { 8,0x58},
488 { 9,0x60},
489 { 10,0x08},
490 { 11,0x01},
491 { 12,0x60},
492 { 13,0x60},
493 { 14,0x00},
494 { 15,0x00},
495 { 16,0x58},
496 { 17,0x60},
497 { 18,0x00},
498 { 19,0x09},
499 { 20,0x00},
500 { 21,0x00},
501 { 22,0x00},
502 { 23,0x00},
503 { 24,0x44},
504 { 25,0x00},
505 { 26,0xC0},
506 { 27,0x07},
507 { 28,0x04},
508 { 29,0x00},
509 { 30,0x00},
510 { 31,0x00},
511 { 32,0x04},
512 { 33,0x00},
513 { 34,0x00},
514 { 35,0x0D},
515 { 36,0x04},
516 { 37,0x00},
517 { 38,0x00},
518 { 39,0x08},
519 { 40,0x04},
520 { 41,0x00},
521 { 42,0x00},
522 { 43,0x04},
523 { 44,0x00},
524 { 45,0x00},
525 { 46,0x00},
526 { 47,0x00},
527 { 48,0x00},
528 { 49,0x00},
529 { 50,0x00},
530 { 51,0x00},
531 { 52,0x44},
532 { 53,0x00},
533 { 54,0x00},
534 { 55,0x07},
535 { 56,0x21},
536 { 57,0x00},
537 { 58,0x20},
538 { 59,0x00},
539 { 60,0x4B},
540 { 61,0x00},
541 { 62,0xC0},
542 { 63,0x00},
543 { 64,0x4B},
544 { 65,0x00},
545 { 66,0xE0},
546 { 67,0x00},
547 { 68,0x10},
548 { 69,0x00},
549 { 70,0x00},
550 { 71,0x00},
551 { 72,0x10},
552 { 73,0x00},
553 { 74,0x00},
554 { 75,0x0D},
555 { 76,0x10},
556 { 77,0x00},
557 { 78,0x00},
558 { 79,0x08},
559 { 80,0x10},
560 { 81,0x00},
561 { 82,0x00},
562 { 83,0x04},
563 { 84,0x18},
564 { 85,0x01},
565 { 86,0xC0},
566 { 87,0x0F},
567 { 88,0x1C},
568 { 89,0x01},
569 { 90,0xA0},
570 { 91,0x09},
571 { 92,0x1C},
572 { 93,0x01},
573 { 94,0xA0},
574 { 95,0x03},
575 { 96,0x1C},
576 { 97,0x01},
577 { 98,0x80},
578 { 99,0x0A},
579 {100,0x1C},
580 {101,0x01},
581 {102,0x80},
582 {103,0x02},
583 {104,0x1C},
584 {105,0x01},
585 {106,0x40},
586 {107,0x0C},
587 {108,0x1C},
588 {109,0x01},
589 {110,0x40},
590 {111,0x00},
591 {112,0x1C},
592 {113,0x01},
593 {114,0x60},
594 {115,0x01},
595 {116,0x1C},
596 {117,0x01},
597 {118,0x60},
598 {119,0x0B},
599 {120,0x18},
600 {121,0x01},
601 {122,0x40},
602 {123,0x03},
603 {124,0x1C},
604 {125,0x01},
605 {126,0x40},
606 {127,0x08},
607 { 0,0x02},
608 { 8,0x1C},
609 { 9,0x01},
610 { 10,0x60},
611 { 11,0x09},
612 { 12,0x10},
613 { 13,0x00},
614 { 14,0x00},
615 { 15,0x2D},
616 { 16,0x1C},
617 { 17,0x01},
618 { 18,0x60},
619 { 19,0x02},
620 { 20,0x1C},
621 { 21,0x01},
622 { 22,0x80},
623 { 23,0x01},
624 { 24,0x1C},
625 { 25,0x01},
626 { 26,0x80},
627 { 27,0x0A},
628 { 28,0x1C},
629 { 29,0x01},
630 { 30,0xA0},
631 { 31,0x00},
632 { 32,0x1C},
633 { 33,0x01},
634 { 34,0xA0},
635 { 35,0x0B},
636 { 36,0x1C},
637 { 37,0x01},
638 { 38,0xC0},
639 { 39,0x06},
640 { 40,0x00},
641 { 41,0x00},
642 { 42,0x00},
643 { 43,0x00},
644 { 44,0x00},
645 { 45,0x00},
646 { 46,0x00},
647 { 47,0x00},
648 { 48,0x00},
649 { 49,0x00},
650 { 50,0x00},
651 { 51,0x00},
652 { 52,0x10},
653 { 53,0x00},
654 { 54,0x00},
655 { 55,0x0F},
656 { 56,0x18},
657 { 57,0x01},
658 { 58,0xE0},
659 { 59,0x2C},
660 { 60,0x1C},
661 { 61,0x02},
662 { 62,0x00},
663 { 63,0x11},
664 { 64,0x1C},
665 { 65,0x02},
666 { 66,0x00},
667 { 67,0x48},
668 { 68,0x1C},
669 { 69,0x01},
670 { 70,0xE0},
671 { 71,0x2D},
672 { 72,0x1C},
673 { 73,0x02},
674 { 74,0x20},
675 { 75,0x2F},
676 { 76,0x1C},
677 { 77,0x02},
678 { 78,0x20},
679 { 79,0x2A},
680 { 80,0x1C},
681 { 81,0x02},
682 { 82,0x40},
683 { 83,0x31},
684 { 84,0x1C},
685 { 85,0x02},
686 { 86,0x40},
687 { 87,0x28},
688 { 88,0x1C},
689 { 89,0x02},
690 { 90,0x60},
691 { 91,0x37},
692 { 92,0x1C},
693 { 93,0x02},
694 { 94,0x60},
695 { 95,0x22},
696 { 96,0x1C},
697 { 97,0x02},
698 { 98,0x80},
699 { 99,0x14},
700 {100,0x1C},
701 {101,0x02},
702 {102,0x80},
703 {103,0x45},
704 {104,0x1C},
705 {105,0x02},
706 {106,0xA0},
707 {107,0x12},
708 {108,0x1C},
709 {109,0x02},
710 {110,0xA0},
711 {111,0x47},
712 {112,0x1C},
713 {113,0x02},
714 {114,0xC0},
715 {115,0x38},
716 {116,0x1C},
717 {117,0x02},
718 {118,0xC0},
719 {119,0x21},
720 {120,0x1C},
721 {121,0x02},
722 {122,0xE0},
723 {123,0x33},
724 {124,0x1C},
725 {125,0x02},
726 {126,0xE0},
727 {127,0x26},
728 { 0,0x03},
729 { 8,0x1C},
730 { 9,0x03},
731 { 10,0x00},
732 { 11,0x16},
733 { 12,0x1C},
734 { 13,0x03},
735 { 14,0x00},
736 { 15,0x43},
737 { 16,0x1C},
738 { 17,0x03},
739 { 18,0xC0},
740 { 19,0x35},
741 { 20,0x1C},
742 { 21,0x03},
743 { 22,0xC0},
744 { 23,0x24},
745 { 24,0x1C},
746 { 25,0x03},
747 { 26,0xE0},
748 { 27,0x1A},
749 { 28,0x1C},
750 { 29,0x03},
751 { 30,0xE0},
752 { 31,0x3F},
753 { 32,0x1C},
754 { 33,0x04},
755 { 34,0x00},
756 { 35,0x3A},
757 { 36,0x1C},
758 { 37,0x04},
759 { 38,0x00},
760 { 39,0x1F},
761 { 40,0x1C},
762 { 41,0x04},
763 { 42,0x20},
764 { 43,0x18},
765 { 44,0x1C},
766 { 45,0x04},
767 { 46,0x20},
768 { 47,0x41},
769 { 48,0x1C},
770 { 49,0x04},
771 { 50,0x40},
772 { 51,0x1C},
773 { 52,0x1C},
774 { 53,0x04},
775 { 54,0x40},
776 { 55,0x3D},
777 { 56,0x1C},
778 { 57,0x04},
779 { 58,0x60},
780 { 59,0x19},
781 { 60,0x1C},
782 { 61,0x04},
783 { 62,0x60},
784 { 63,0x40},
785 { 64,0x1C},
786 { 65,0x04},
787 { 66,0x80},
788 { 67,0x30},
789 { 68,0x1C},
790 { 69,0x04},
791 { 70,0x80},
792 { 71,0x29},
793 { 72,0x1C},
794 { 73,0x04},
795 { 74,0xA0},
796 { 75,0x15},
797 { 76,0x1C},
798 { 77,0x04},
799 { 78,0xA0},
800 { 79,0x44},
801 { 80,0x1C},
802 { 81,0x04},
803 { 82,0xC0},
804 { 83,0x3B},
805 { 84,0x1C},
806 { 85,0x04},
807 { 86,0xC0},
808 { 87,0x1E},
809 { 88,0x1C},
810 { 89,0x04},
811 { 90,0xE0},
812 { 91,0x34},
813 { 92,0x1C},
814 { 93,0x04},
815 { 94,0xE0},
816 { 95,0x25},
817 { 96,0x1C},
818 { 97,0x05},
819 { 98,0x00},
820 { 99,0x36},
821 {100,0x1C},
822 {101,0x05},
823 {102,0x00},
824 {103,0x23},
825 {104,0x1C},
826 {105,0x05},
827 {106,0x20},
828 {107,0x32},
829 {108,0x1C},
830 {109,0x05},
831 {110,0x20},
832 {111,0x27},
833 {112,0x1C},
834 {113,0x05},
835 {114,0x40},
836 {115,0x13},
837 {116,0x1C},
838 {117,0x05},
839 {118,0x40},
840 {119,0x46},
841 {120,0x1C},
842 {121,0x05},
843 {122,0x60},
844 {123,0x2E},
845 {124,0x1C},
846 {125,0x05},
847 {126,0x60},
848 {127,0x2B},
849 { 0,0x04},
850 { 8,0x1C},
851 { 9,0x05},
852 { 10,0x80},
853 { 11,0x10},
854 { 12,0x1C},
855 { 13,0x05},
856 { 14,0x80},
857 { 15,0x49},
858 { 16,0x1C},
859 { 17,0x05},
860 { 18,0xA0},
861 { 19,0x17},
862 { 20,0x1C},
863 { 21,0x05},
864 { 22,0xA0},
865 { 23,0x42},
866 { 24,0x1C},
867 { 25,0x05},
868 { 26,0xC0},
869 { 27,0x1D},
870 { 28,0x1C},
871 { 29,0x05},
872 { 30,0xC0},
873 { 31,0x3C},
874 { 32,0x1C},
875 { 33,0x05},
876 { 34,0xE0},
877 { 35,0x1B},
878 { 36,0x1C},
879 { 37,0x05},
880 { 38,0xE0},
881 { 39,0x3E},
882 { 40,0x1C},
883 { 41,0x06},
884 { 42,0x00},
885 { 43,0x39},
886 { 44,0x1C},
887 { 45,0x06},
888 { 46,0x00},
889 { 47,0x20},
890 { 48,0x00},
891 { 49,0x00},
892 { 50,0x00},
893 { 51,0x00},
894 { 52,0x5C},
895 { 53,0x90},
896 { 54,0x40},
897 { 55,0x00},
898 { 56,0x00},
899 { 57,0x00},
900 { 58,0x00},
901 { 59,0x00},
902 { 60,0x5C},
903 { 61,0x90},
904 { 62,0x20},
905 { 63,0x00},
906 { 64,0x00},
907 { 65,0x00},
908 { 66,0x00},
909 { 67,0x00},
910 { 68,0x00},
911 { 69,0x00},
912 { 70,0x00},
913 { 71,0x00},
914 { 72,0x00},
915 { 73,0x00},
916 { 74,0x00},
917 { 75,0x00},
918 { 76,0x10},
919 { 77,0x00},
920 { 78,0x00},
921 { 79,0x49},
922 { 80,0x18},
923 { 81,0x00},
924 { 82,0x60},
925 { 83,0x4A},
926 { 84,0x1C},
927 { 85,0x00},
928 { 86,0x80},
929 { 87,0x4C},
930 { 88,0x1C},
931 { 89,0x00},
932 { 90,0x40},
933 { 91,0x49},
934 { 92,0x30},
935 { 93,0x00},
936 { 94,0x00},
937 { 95,0x4C},
938 { 96,0x1C},
939 { 97,0x00},
940 { 98,0x20},
941 { 99,0x4E},
942 {100,0x00},
943 {101,0x00},
944 {102,0x00},
945 {103,0x00},
946 {104,0x10},
947 {105,0x30},
948 {106,0x00},
949 {107,0x4B},
950 {108,0x34},
951 {109,0x00},
952 {110,0x00},
953 {111,0x4B},
954 {112,0x5C},
955 {113,0x60},
956 {114,0xA0},
957 {115,0x4B},
958 {116,0x0C},
959 {117,0x00},
960 {118,0x40},
961 {119,0x00},
962 {120,0x00},
963 {121,0x00},
964 {122,0x00},
965 {123,0x00},
966 {124,0x10},
967 {125,0x30},
968 {126,0x00},
969 {127,0x4D},
970 { 0,0x05},
971 { 8,0x10},
972 { 9,0x13},
973 { 10,0xE0},
974 { 11,0x50},
975 { 12,0x18},
976 { 13,0x01},
977 { 14,0x00},
978 { 15,0x50},
979 { 16,0x18},
980 { 17,0x03},
981 { 18,0x60},
982 { 19,0x53},
983 { 20,0x6C},
984 { 21,0x03},
985 { 22,0x40},
986 { 23,0x52},
987 { 24,0x6C},
988 { 25,0x03},
989 { 26,0x80},
990 { 27,0x55},
991 { 28,0x10},
992 { 29,0x00},
993 { 30,0x20},
994 { 31,0x51},
995 { 32,0x1C},
996 { 33,0x03},
997 { 34,0x20},
998 { 35,0x51},
999 { 36,0x1C},
1000 { 37,0x03},
1001 { 38,0xA0},
1002 { 39,0x56},
1003 { 40,0x00},
1004 { 41,0x00},
1005 { 42,0x00},
1006 { 43,0x00},
1007 { 44,0x00},
1008 { 45,0x00},
1009 { 46,0x00},
1010 { 47,0x00},
1011 { 48,0x00},
1012 { 49,0x00},
1013 { 50,0x00},
1014 { 51,0x00},
1015 { 52,0x10},
1016 { 53,0x00},
1017 { 54,0x00},
1018 { 55,0x54},
1019 { 56,0x18},
1020 { 57,0x01},
1021 { 58,0x00},
1022 { 59,0x54},
1023 { 60,0x00},
1024 { 61,0x00},
1025 { 62,0x00},
1026 { 63,0x00},
1027 { 64,0x0C},
1028 { 65,0x00},
1029 { 66,0x00},
1030 { 67,0x03},
1031 { 68,0x00},
1032 { 69,0x00},
1033 { 70,0x00},
1034 { 71,0x00},
1035 { 72,0x00},
1036 { 73,0x00},
1037 { 74,0x00},
1038 { 75,0x00},
1039 { 76,0x00},
1040 { 77,0x00},
1041 { 78,0x00},
1042 { 79,0x00},
1043 { 80,0x02},
1044 { 81,0x00},
1045 { 82,0x00},
1046 { 83,0x00},
1047 { 84,0x00},
1048 { 85,0x00},
1049 { 86,0x00},
1050 { 87,0x00},
1051};
1052
1053
1054reg_value base_speaker_SRS_miniDSP_D_reg_values[] = {
1055 { 0,0x0},
1056 { 0x7F,0x50},
1057 { 0,0x01},
1058 { 8,0xFF},
1059 { 9,0xFF},
1060 { 10,0xFF},
1061 { 11,0x00},
1062 { 12,0x80},
1063 { 13,0x00},
1064 { 14,0x00},
1065 { 15,0x00},
1066 { 16,0x7F},
1067 { 17,0xF7},
1068 { 18,0x00},
1069 { 19,0x00},
1070 { 20,0x80},
1071 { 21,0x09},
1072 { 22,0x00},
1073 { 23,0x00},
1074 { 24,0x7F},
1075 { 25,0xEF},
1076 { 26,0x00},
1077 { 27,0x00},
1078 { 28,0x66},
1079 { 29,0x66},
1080 { 30,0x60},
1081 { 31,0x00},
1082 { 32,0x1B},
1083 { 33,0x33},
1084 { 34,0x20},
1085 { 35,0x00},
1086 { 36,0x66},
1087 { 37,0x66},
1088 { 38,0x60},
1089 { 39,0x00},
1090 { 40,0x33},
1091 { 41,0x33},
1092 { 42,0x30},
1093 { 43,0x00},
1094 { 44,0x4C},
1095 { 45,0xCC},
1096 { 46,0xCD},
1097 { 47,0x00},
1098 { 48,0x00},
1099 { 49,0x00},
1100 { 50,0x01},
1101 { 51,0x00},
1102 { 52,0x33},
1103 { 53,0x33},
1104 { 54,0x30},
1105 { 55,0x00},
1106 { 56,0x33},
1107 { 57,0x33},
1108 { 58,0x30},
1109 { 59,0x00},
1110 { 60,0x7F},
1111 { 61,0xFF},
1112 { 62,0xAC},
1113 { 63,0x00},
1114 { 64,0x80},
1115 { 65,0x00},
1116 { 66,0x00},
1117 { 67,0x00},
1118 { 68,0x40},
1119 { 69,0x00},
1120 { 70,0x00},
1121 { 71,0x00},
1122 { 72,0x40},
1123 { 73,0x00},
1124 { 74,0x00},
1125 { 75,0x00},
1126 { 76,0xC0},
1127 { 77,0x00},
1128 { 78,0x00},
1129 { 79,0x00},
1130 { 80,0x50},
1131 { 81,0xC3},
1132 { 82,0x36},
1133 { 83,0x00},
1134 { 84,0x02},
1135 { 85,0x8F},
1136 { 86,0x5C},
1137 { 87,0x00},
1138 { 88,0x02},
1139 { 89,0xD7},
1140 { 90,0x0A},
1141 { 91,0x00},
1142 { 92,0x00},
1143 { 93,0x00},
1144 { 94,0x00},
1145 { 95,0x00},
1146 { 96,0x00},
1147 { 97,0x00},
1148 { 98,0x00},
1149 { 99,0x00},
1150 {100,0x00},
1151 {101,0x00},
1152 {102,0x00},
1153 {103,0x00},
1154 {104,0x00},
1155 {105,0x00},
1156 {106,0x00},
1157 {107,0x00},
1158 {108,0x00},
1159 {109,0x00},
1160 {110,0x00},
1161 {111,0x00},
1162 {112,0x40},
1163 {113,0x00},
1164 {114,0x00},
1165 {115,0x00},
1166 {116,0xFF},
1167 {117,0xFF},
1168 {118,0xFF},
1169 {119,0x00},
1170 {120,0xFF},
1171 {121,0xFF},
1172 {122,0xFE},
1173 {123,0x00},
1174 {124,0xFF},
1175 {125,0xFF},
1176 {126,0xFD},
1177 {127,0x00},
1178 { 0,0x02},
1179 { 8,0xFF},
1180 { 9,0xFF},
1181 { 10,0xFC},
1182 { 11,0x00},
1183 { 12,0x00},
1184 { 13,0x00},
1185 { 14,0x00},
1186 { 15,0x00},
1187 { 16,0x73},
1188 { 17,0x56},
1189 { 18,0x6E},
1190 { 19,0x00},
1191 { 20,0x7F},
1192 { 21,0xF4},
1193 { 22,0xA0},
1194 { 23,0x00},
1195 { 24,0x00},
1196 { 25,0x80},
1197 { 26,0x2D},
1198 { 27,0x00},
1199 { 28,0x7E},
1200 { 29,0xFF},
1201 { 30,0xA5},
1202 { 31,0x00},
1203 { 32,0x00},
1204 { 33,0x2E},
1205 { 34,0x73},
1206 { 35,0x00},
1207 { 36,0xFF},
1208 { 37,0xD1},
1209 { 38,0x8D},
1210 { 39,0x00},
1211 { 40,0x7F},
1212 { 41,0xC1},
1213 { 42,0x2F},
1214 { 43,0x00},
1215 { 44,0x80},
1216 { 45,0x7B},
1217 { 46,0x94},
1218 { 47,0x00},
1219 { 48,0x01},
1220 { 49,0x50},
1221 { 50,0xC1},
1222 { 51,0x00},
1223 { 52,0xFE},
1224 { 53,0xAF},
1225 { 54,0x3F},
1226 { 55,0x00},
1227 { 56,0x7F},
1228 { 57,0x55},
1229 { 58,0xC1},
1230 { 59,0x00},
1231 { 60,0x81},
1232 { 61,0x4E},
1233 { 62,0x4E},
1234 { 63,0x00},
1235 { 64,0x7F},
1236 { 65,0xFF},
1237 { 66,0xFF},
1238 { 67,0x00},
1239 { 68,0x00},
1240 { 69,0x00},
1241 { 70,0x00},
1242 { 71,0x00},
1243 { 72,0xC7},
1244 { 73,0x2E},
1245 { 74,0x8D},
1246 { 75,0x00},
1247 { 76,0x31},
1248 { 77,0x91},
1249 { 78,0x54},
1250 { 79,0x00},
1251 { 80,0xD1},
1252 { 81,0xFC},
1253 { 82,0xF4},
1254 { 83,0x00},
1255 { 84,0x2A},
1256 { 85,0x09},
1257 { 86,0x1A},
1258 { 87,0x00},
1259 { 88,0xEA},
1260 { 89,0xD6},
1261 { 90,0x1C},
1262 { 91,0x00},
1263 { 92,0xC5},
1264 { 93,0x28},
1265 { 94,0xA2},
1266 { 95,0x00},
1267 { 96,0x32},
1268 { 97,0xD7},
1269 { 98,0x53},
1270 { 99,0x00},
1271 {100,0xD3},
1272 {101,0x74},
1273 {102,0x4B},
1274 {103,0x00},
1275 {104,0x15},
1276 {105,0x04},
1277 {106,0x8D},
1278 {107,0x00},
1279 {108,0xF5},
1280 {109,0x6B},
1281 {110,0x0E},
1282 {111,0x00},
1283 {112,0xC0},
1284 {113,0x0C},
1285 {114,0x47},
1286 {115,0x00},
1287 {116,0x3F},
1288 {117,0x99},
1289 {118,0x61},
1290 {119,0x00},
1291 {120,0x3E},
1292 {121,0xE2},
1293 {122,0x1D},
1294 {123,0x00},
1295 {124,0x3E},
1296 {125,0xE2},
1297 {126,0x1D},
1298 {127,0x00},
1299 { 0,0x03},
1300 { 8,0x0A},
1301 { 9,0x57},
1302 { 10,0x0D},
1303 { 11,0x00},
1304 { 12,0xF5},
1305 { 13,0xA8},
1306 { 14,0xF3},
1307 { 15,0x00},
1308 { 16,0x6E},
1309 { 17,0x1B},
1310 { 18,0xC0},
1311 { 19,0x00},
1312 { 20,0x89},
1313 { 21,0x90},
1314 { 22,0x65},
1315 { 23,0x00},
1316 { 24,0x1B},
1317 { 25,0x6E},
1318 { 26,0xFE},
1319 { 27,0x00},
1320 { 28,0xE4},
1321 { 29,0x91},
1322 { 30,0x02},
1323 { 31,0x00},
1324 { 32,0x5B},
1325 { 33,0x45},
1326 { 34,0x9C},
1327 { 35,0x00},
1328 { 36,0x99},
1329 { 37,0x5F},
1330 { 38,0xEC},
1331 { 39,0x00},
1332 { 40,0x15},
1333 { 41,0x3D},
1334 { 42,0xC9},
1335 { 43,0x00},
1336 { 44,0xEA},
1337 { 45,0xC2},
1338 { 46,0x37},
1339 { 47,0x00},
1340 { 48,0x40},
1341 { 49,0x53},
1342 { 50,0x16},
1343 { 51,0x00},
1344 { 52,0x93},
1345 { 53,0xA5},
1346 { 54,0xAE},
1347 { 55,0x00},
1348 { 56,0x9B},
1349 { 57,0x77},
1350 { 58,0x00},
1351 { 59,0x00},
1352 { 60,0x64},
1353 { 61,0x88},
1354 { 62,0xF0},
1355 { 63,0x00},
1356 { 64,0x45},
1357 { 65,0x84},
1358 { 66,0x40},
1359 { 67,0x00},
1360 { 68,0xBA},
1361 { 69,0x7B},
1362 { 70,0xB0},
1363 { 71,0x00},
1364 { 72,0xC3},
1365 { 73,0xE0},
1366 { 74,0x00},
1367 { 75,0x00},
1368 { 76,0x3C},
1369 { 77,0x1F},
1370 { 78,0xF0},
1371 { 79,0x00},
1372 { 80,0x68},
1373 { 81,0x76},
1374 { 82,0x1D},
1375 { 83,0x00},
1376 { 84,0x97},
1377 { 85,0x89},
1378 { 86,0xE3},
1379 { 87,0x00},
1380 { 88,0x67},
1381 { 89,0xEA},
1382 { 90,0x3A},
1383 { 91,0x00},
1384 { 92,0xAD},
1385 { 93,0xFC},
1386 { 94,0x02},
1387 { 95,0x00},
1388 { 96,0x79},
1389 { 97,0xEC},
1390 { 98,0x4D},
1391 { 99,0x00},
1392 {100,0x86},
1393 {101,0x13},
1394 {102,0xB3},
1395 {103,0x00},
1396 {104,0x3A},
1397 {105,0x36},
1398 {106,0x6A},
1399 {107,0x00},
1400 {108,0x7F},
1401 {109,0xFF},
1402 {110,0xFF},
1403 {111,0x00},
1404 {112,0x00},
1405 {113,0x00},
1406 {114,0x00},
1407 {115,0x00},
1408 {116,0x00},
1409 {117,0x00},
1410 {118,0x00},
1411 {119,0x00},
1412 {120,0x00},
1413 {121,0x00},
1414 {122,0x00},
1415 {123,0x00},
1416 {124,0x00},
1417 {125,0x00},
1418 {126,0x00},
1419 {127,0x00},
1420 { 0,0x04},
1421 { 8,0x7F},
1422 { 9,0xFF},
1423 { 10,0xFF},
1424 { 11,0x00},
1425 { 12,0x00},
1426 { 13,0x00},
1427 { 14,0x00},
1428 { 15,0x00},
1429 { 16,0x00},
1430 { 17,0x00},
1431 { 18,0x00},
1432 { 19,0x00},
1433 { 20,0x00},
1434 { 21,0x00},
1435 { 22,0x00},
1436 { 23,0x00},
1437 { 24,0x00},
1438 { 25,0x00},
1439 { 26,0x00},
1440 { 27,0x00},
1441 { 28,0x00},
1442 { 29,0x00},
1443 { 30,0x01},
1444 { 31,0x00},
1445 { 32,0xC0},
1446 { 33,0x00},
1447 { 34,0x00},
1448 { 35,0x00},
1449 { 36,0x00},
1450 { 37,0x00},
1451 { 38,0x01},
1452 { 39,0x00},
1453 { 40,0x00},
1454 { 41,0x00},
1455 { 42,0xAF},
1456 { 43,0x00},
1457 { 44,0x7F},
1458 { 45,0xFF},
1459 { 46,0x51},
1460 { 47,0x00},
1461 { 48,0x00},
1462 { 49,0x00},
1463 { 50,0x00},
1464 { 51,0x00},
1465 { 52,0xF0},
1466 { 53,0x00},
1467 { 54,0x00},
1468 { 55,0x00},
1469 { 56,0xE4},
1470 { 57,0x00},
1471 { 58,0x00},
1472 { 59,0x00},
1473 { 60,0x32},
1474 { 61,0x00},
1475 { 62,0x00},
1476 { 63,0x00},
1477 { 64,0x14},
1478 { 65,0x00},
1479 { 66,0x00},
1480 { 67,0x00},
1481 { 68,0xFF},
1482 { 69,0x00},
1483 { 70,0x00},
1484 { 71,0x00},
1485 { 72,0xF0},
1486 { 73,0x00},
1487 { 74,0x00},
1488 { 75,0x00},
1489 { 76,0x00},
1490 { 77,0x02},
1491 { 78,0xBB},
1492 { 79,0x00},
1493 { 80,0x7F},
1494 { 81,0xFD},
1495 { 82,0x45},
1496 { 83,0x00},
1497 { 84,0x00},
1498 { 85,0x00},
1499 { 86,0x57},
1500 { 87,0x00},
1501 { 88,0x7F},
1502 { 89,0xFF},
1503 { 90,0xA9},
1504 { 91,0x00},
1505 { 92,0x20},
1506 { 93,0x00},
1507 { 94,0x00},
1508 { 95,0x00},
1509 { 96,0x00},
1510 { 97,0x00},
1511 { 98,0x00},
1512 { 99,0x00},
1513 {100,0xD7},
1514 {101,0x41},
1515 {102,0xA0},
1516 {103,0x00},
1517 {104,0xFF},
1518 {105,0xF0},
1519 {106,0x00},
1520 {107,0x00},
1521 {108,0x88},
1522 {109,0x00},
1523 {110,0x00},
1524 {111,0x00},
1525 {112,0x18},
1526 {113,0x00},
1527 {114,0x00},
1528 {115,0x00},
1529 {116,0x00},
1530 {117,0x00},
1531 {118,0x00},
1532 {119,0x00},
1533 {120,0x0C},
1534 {121,0x00},
1535 {122,0x00},
1536 {123,0x00},
1537 {124,0xF4},
1538 {125,0x00},
1539 {126,0x00},
1540 {127,0x00},
1541 { 0,0x05},
1542 { 8,0x15},
1543 { 9,0x42},
1544 { 10,0xA6},
1545 { 11,0x00},
1546 { 12,0x7F},
1547 { 13,0xFF},
1548 { 14,0xFF},
1549 { 15,0x00},
1550 { 16,0x0B},
1551 { 17,0xF9},
1552 { 18,0x13},
1553 { 19,0x00},
1554 { 20,0x18},
1555 { 21,0xEC},
1556 { 22,0xF7},
1557 { 23,0x00},
1558 { 24,0x5B},
1559 { 25,0x9E},
1560 { 26,0xC4},
1561 { 27,0x00},
1562 { 28,0x7F},
1563 { 29,0x7B},
1564 { 30,0x30},
1565 { 31,0x00},
1566 { 32,0x00},
1567 { 33,0x00},
1568 { 34,0x00},
1569 { 35,0x00},
1570 { 36,0x00},
1571 { 37,0x00},
1572 { 38,0x00},
1573 { 39,0x00},
1574 { 40,0x00},
1575 { 41,0x00},
1576 { 42,0x00},
1577 { 43,0x00},
1578 { 44,0x00},
1579 { 45,0x0D},
1580 { 46,0x00},
1581 { 47,0x00},
1582 { 48,0x00},
1583 { 49,0x1C},
1584 { 50,0x00},
1585 { 51,0x00},
1586 { 52,0x00},
1587 { 53,0x3E},
1588 { 54,0x00},
1589 { 55,0x00},
1590 { 56,0x00},
1591 { 57,0x78},
1592 { 58,0x00},
1593 { 59,0x00},
1594 { 60,0x02},
1595 { 61,0x4C},
1596 { 62,0x00},
1597 { 63,0x00},
1598 { 64,0x00},
1599 { 65,0xD5},
1600 { 66,0x00},
1601 { 67,0x00},
1602 { 68,0x01},
1603 { 69,0x65},
1604 { 70,0x00},
1605 { 71,0x00},
1606 { 72,0x03},
1607 { 73,0xE9},
1608 { 74,0x00},
1609 { 75,0x00},
1610 { 76,0x07},
1611 { 77,0xCA},
1612 { 78,0x00},
1613 { 79,0x00},
1614 { 80,0xFF},
1615 { 81,0xEF},
1616 { 82,0x00},
1617 { 83,0x00},
1618 { 84,0xFE},
1619 { 85,0xEB},
1620 { 86,0x00},
1621 { 87,0x00},
1622 { 88,0xFF},
1623 { 89,0xA8},
1624 { 90,0x00},
1625 { 91,0x00},
1626 { 92,0xFD},
1627 { 93,0x08},
1628 { 94,0x00},
1629 { 95,0x00},
1630 { 96,0xFF},
1631 { 97,0x5E},
1632 { 98,0x00},
1633 { 99,0x00},
1634 {100,0xFF},
1635 {101,0xD5},
1636 {102,0x00},
1637 {103,0x00},
1638 {104,0xFE},
1639 {105,0x36},
1640 {106,0x00},
1641 {107,0x00},
1642 {108,0xFA},
1643 {109,0xAC},
1644 {110,0x00},
1645 {111,0x00},
1646 {112,0xF2},
1647 {113,0xA3},
1648 {114,0x00},
1649 {115,0x00},
1650 {116,0x28},
1651 {117,0xAB},
1652 {118,0x00},
1653 {119,0x00},
1654 {120,0x3F},
1655 {121,0xFF},
1656 {122,0x00},
1657 {123,0x00},
1658 {124,0xFF},
1659 {125,0x98},
1660 {126,0x00},
1661 {127,0x00},
1662 { 0,0x06},
1663 { 8,0xF6},
1664 { 9,0xF9},
1665 { 10,0x00},
1666 { 11,0x00},
1667 { 12,0x26},
1668 { 13,0xFB},
1669 { 14,0x00},
1670 { 15,0x00},
1671 { 16,0x02},
1672 { 17,0x72},
1673 { 18,0x00},
1674 { 19,0x00},
1675 { 20,0x40},
1676 { 21,0x02},
1677 { 22,0x00},
1678 { 23,0x00},
1679 { 24,0xFB},
1680 { 25,0xCB},
1681 { 26,0x00},
1682 { 27,0x00},
1683 { 28,0x20},
1684 { 29,0xA7},
1685 { 30,0x00},
1686 { 31,0x00},
1687 { 32,0xFF},
1688 { 33,0x6A},
1689 { 34,0x00},
1690 { 35,0x00},
1691 { 36,0x3A},
1692 { 37,0x0F},
1693 { 38,0x00},
1694 { 39,0x00},
1695 { 0,0x09},
1696 { 72,0xFF},
1697 { 73,0xFF},
1698 { 74,0xFF},
1699 { 75,0x00},
1700 { 76,0x80},
1701 { 77,0x00},
1702 { 78,0x00},
1703 { 79,0x00},
1704 { 80,0x7F},
1705 { 81,0xF7},
1706 { 82,0x00},
1707 { 83,0x00},
1708 { 84,0x80},
1709 { 85,0x09},
1710 { 86,0x00},
1711 { 87,0x00},
1712 { 88,0x7F},
1713 { 89,0xEF},
1714 { 90,0x00},
1715 { 91,0x00},
1716 { 92,0x66},
1717 { 93,0x66},
1718 { 94,0x60},
1719 { 95,0x00},
1720 { 96,0x1B},
1721 { 97,0x33},
1722 { 98,0x20},
1723 { 99,0x00},
1724 {100,0x66},
1725 {101,0x66},
1726 {102,0x60},
1727 {103,0x00},
1728 {104,0x33},
1729 {105,0x33},
1730 {106,0x30},
1731 {107,0x00},
1732 {108,0x4C},
1733 {109,0xCC},
1734 {110,0xCD},
1735 {111,0x00},
1736 {112,0x00},
1737 {113,0x00},
1738 {114,0x01},
1739 {115,0x00},
1740 {116,0x33},
1741 {117,0x33},
1742 {118,0x30},
1743 {119,0x00},
1744 {120,0x33},
1745 {121,0x33},
1746 {122,0x30},
1747 {123,0x00},
1748 {124,0x7F},
1749 {125,0xFF},
1750 {126,0xAC},
1751 {127,0x00},
1752 { 0,0x0A},
1753 { 8,0x80},
1754 { 9,0x00},
1755 { 10,0x00},
1756 { 11,0x00},
1757 { 12,0x40},
1758 { 13,0x00},
1759 { 14,0x00},
1760 { 15,0x00},
1761 { 16,0x40},
1762 { 17,0x00},
1763 { 18,0x00},
1764 { 19,0x00},
1765 { 20,0xC0},
1766 { 21,0x00},
1767 { 22,0x00},
1768 { 23,0x00},
1769 { 24,0x50},
1770 { 25,0xC3},
1771 { 26,0x36},
1772 { 27,0x00},
1773 { 28,0x02},
1774 { 29,0x8F},
1775 { 30,0x5C},
1776 { 31,0x00},
1777 { 32,0x02},
1778 { 33,0xD7},
1779 { 34,0x0A},
1780 { 35,0x00},
1781 { 36,0x00},
1782 { 37,0x00},
1783 { 38,0x00},
1784 { 39,0x00},
1785 { 40,0x00},
1786 { 41,0x00},
1787 { 42,0x00},
1788 { 43,0x00},
1789 { 44,0x00},
1790 { 45,0x00},
1791 { 46,0x00},
1792 { 47,0x00},
1793 { 48,0x00},
1794 { 49,0x00},
1795 { 50,0x00},
1796 { 51,0x00},
1797 { 52,0x00},
1798 { 53,0x00},
1799 { 54,0x00},
1800 { 55,0x00},
1801 { 56,0x40},
1802 { 57,0x00},
1803 { 58,0x00},
1804 { 59,0x00},
1805 { 60,0xFF},
1806 { 61,0xFF},
1807 { 62,0xFF},
1808 { 63,0x00},
1809 { 64,0xFF},
1810 { 65,0xFF},
1811 { 66,0xFE},
1812 { 67,0x00},
1813 { 68,0xFF},
1814 { 69,0xFF},
1815 { 70,0xFD},
1816 { 71,0x00},
1817 { 72,0xFF},
1818 { 73,0xFF},
1819 { 74,0xFC},
1820 { 75,0x00},
1821 { 76,0x00},
1822 { 77,0x00},
1823 { 78,0x00},
1824 { 79,0x00},
1825 { 80,0x73},
1826 { 81,0x56},
1827 { 82,0x6E},
1828 { 83,0x00},
1829 { 84,0x7F},
1830 { 85,0xF4},
1831 { 86,0xA0},
1832 { 87,0x00},
1833 { 88,0x00},
1834 { 89,0x80},
1835 { 90,0x2D},
1836 { 91,0x00},
1837 { 92,0x7E},
1838 { 93,0xFF},
1839 { 94,0xA5},
1840 { 95,0x00},
1841 { 96,0x00},
1842 { 97,0x2E},
1843 { 98,0x73},
1844 { 99,0x00},
1845 {100,0xFF},
1846 {101,0xD1},
1847 {102,0x8D},
1848 {103,0x00},
1849 {104,0x7F},
1850 {105,0xC1},
1851 {106,0x2F},
1852 {107,0x00},
1853 {108,0x80},
1854 {109,0x7B},
1855 {110,0x94},
1856 {111,0x00},
1857 {112,0x01},
1858 {113,0x50},
1859 {114,0xC1},
1860 {115,0x00},
1861 {116,0xFE},
1862 {117,0xAF},
1863 {118,0x3F},
1864 {119,0x00},
1865 {120,0x7F},
1866 {121,0x55},
1867 {122,0xC1},
1868 {123,0x00},
1869 {124,0x81},
1870 {125,0x4E},
1871 {126,0x4E},
1872 {127,0x00},
1873 { 0,0x0B},
1874 { 8,0x7F},
1875 { 9,0xFF},
1876 { 10,0xFF},
1877 { 11,0x00},
1878 { 12,0x00},
1879 { 13,0x00},
1880 { 14,0x00},
1881 { 15,0x00},
1882 { 16,0xC7},
1883 { 17,0x2E},
1884 { 18,0x8D},
1885 { 19,0x00},
1886 { 20,0x31},
1887 { 21,0x91},
1888 { 22,0x54},
1889 { 23,0x00},
1890 { 24,0xD1},
1891 { 25,0xFC},
1892 { 26,0xF4},
1893
1894 { 27,0x00},
1895 { 28,0x2A},
1896 { 29,0x09},
1897 { 30,0x1A},
1898 { 31,0x00},
1899 { 32,0xEA},
1900 { 33,0xD6},
1901 { 34,0x1C},
1902 { 35,0x00},
1903 { 36,0xC5},
1904 { 37,0x28},
1905 { 38,0xA2},
1906 { 39,0x00},
1907 { 40,0x32},
1908 { 41,0xD7},
1909 { 42,0x53},
1910 { 43,0x00},
1911 { 44,0xD3},
1912 { 45,0x74},
1913 { 46,0x4B},
1914 { 47,0x00},
1915 { 48,0x15},
1916 { 49,0x04},
1917 { 50,0x8D},
1918 { 51,0x00},
1919 { 52,0xF5},
1920 { 53,0x6B},
1921 { 54,0x0E},
1922 { 55,0x00},
1923 { 56,0xC0},
1924 { 57,0x0C},
1925 { 58,0x47},
1926 { 59,0x00},
1927 { 60,0x3F},
1928 { 61,0x99},
1929 { 62,0x61},
1930 { 63,0x00},
1931 { 64,0x3E},
1932 { 65,0xE2},
1933 { 66,0x1D},
1934 { 67,0x00},
1935 { 68,0x3E},
1936 { 69,0xE2},
1937 { 70,0x1D},
1938 { 71,0x00},
1939 { 72,0x0A},
1940 { 73,0x57},
1941 { 74,0x0D},
1942 { 75,0x00},
1943 { 76,0xF5},
1944 { 77,0xA8},
1945 { 78,0xF3},
1946 { 79,0x00},
1947 { 80,0x6E},
1948 { 81,0x1B},
1949 { 82,0xC0},
1950 { 83,0x00},
1951 { 84,0x89},
1952 { 85,0x90},
1953 { 86,0x65},
1954 { 87,0x00},
1955 { 88,0x1B},
1956 { 89,0x6E},
1957 { 90,0xFE},
1958 { 91,0x00},
1959 { 92,0xE4},
1960 { 93,0x91},
1961 { 94,0x02},
1962 { 95,0x00},
1963 { 96,0x5B},
1964 { 97,0x45},
1965 { 98,0x9C},
1966 { 99,0x00},
1967 {100,0x99},
1968 {101,0x5F},
1969 {102,0xEC},
1970 {103,0x00},
1971 {104,0x15},
1972 {105,0x3D},
1973 {106,0xC9},
1974 {107,0x00},
1975 {108,0xEA},
1976 {109,0xC2},
1977 {110,0x37},
1978 {111,0x00},
1979 {112,0x40},
1980 {113,0x53},
1981 {114,0x16},
1982 {115,0x00},
1983 {116,0x93},
1984 {117,0xA5},
1985 {118,0xAE},
1986 {119,0x00},
1987 {120,0x9B},
1988 {121,0x77},
1989 {122,0x00},
1990 {123,0x00},
1991 {124,0x64},
1992 {125,0x88},
1993 {126,0xF0},
1994 {127,0x00},
1995 { 0,0x0C},
1996 { 8,0x45},
1997 { 9,0x84},
1998 { 10,0x40},
1999 { 11,0x00},
2000 { 12,0xBA},
2001 { 13,0x7B},
2002 { 14,0xB0},
2003 { 15,0x00},
2004 { 16,0xC3},
2005 { 17,0xE0},
2006 { 18,0x00},
2007 { 19,0x00},
2008 { 20,0x3C},
2009 { 21,0x1F},
2010 { 22,0xF0},
2011 { 23,0x00},
2012 { 24,0x68},
2013 { 25,0x76},
2014 { 26,0x1D},
2015 { 27,0x00},
2016 { 28,0x97},
2017 { 29,0x89},
2018 { 30,0xE3},
2019 { 31,0x00},
2020 { 32,0x67},
2021 { 33,0xEA},
2022 { 34,0x3A},
2023 { 35,0x00},
2024 { 36,0xAD},
2025 { 37,0xFC},
2026 { 38,0x02},
2027 { 39,0x00},
2028 { 40,0x79},
2029 { 41,0xEC},
2030 { 42,0x4D},
2031 { 43,0x00},
2032 { 44,0x86},
2033 { 45,0x13},
2034 { 46,0xB3},
2035 { 47,0x00},
2036 { 48,0x3A},
2037 { 49,0x36},
2038 { 50,0x6A},
2039 { 51,0x00},
2040 { 52,0x7F},
2041 { 53,0xFF},
2042 { 54,0xFF},
2043 { 55,0x00},
2044 { 56,0x00},
2045 { 57,0x00},
2046 { 58,0x00},
2047 { 59,0x00},
2048 { 60,0x00},
2049 { 61,0x00},
2050 { 62,0x00},
2051 { 63,0x00},
2052 { 64,0x00},
2053 { 65,0x00},
2054 { 66,0x00},
2055 { 67,0x00},
2056 { 68,0x00},
2057 { 69,0x00},
2058 { 70,0x00},
2059 { 71,0x00},
2060 { 72,0x7F},
2061 { 73,0xFF},
2062 { 74,0xFF},
2063 { 75,0x00},
2064 { 76,0x00},
2065 { 77,0x00},
2066 { 78,0x00},
2067 { 79,0x00},
2068 { 80,0x00},
2069 { 81,0x00},
2070 { 82,0x00},
2071 { 83,0x00},
2072 { 84,0x00},
2073 { 85,0x00},
2074 { 86,0x00},
2075 { 87,0x00},
2076 { 88,0x00},
2077 { 89,0x00},
2078 { 90,0x00},
2079 { 91,0x00},
2080 { 92,0x00},
2081 { 93,0x00},
2082 { 94,0x01},
2083 { 95,0x00},
2084 { 96,0xC0},
2085 { 97,0x00},
2086 { 98,0x00},
2087 { 99,0x00},
2088 {100,0x00},
2089 {101,0x00},
2090 {102,0x01},
2091 {103,0x00},
2092 {104,0x00},
2093 {105,0x00},
2094 {106,0xAF},
2095 {107,0x00},
2096 {108,0x7F},
2097 {109,0xFF},
2098 {110,0x51},
2099 {111,0x00},
2100 {112,0x00},
2101 {113,0x00},
2102 {114,0x00},
2103 {115,0x00},
2104 {116,0xF0},
2105 {117,0x00},
2106 {118,0x00},
2107 {119,0x00},
2108 {120,0xE4},
2109 {121,0x00},
2110 {122,0x00},
2111 {123,0x00},
2112 {124,0x32},
2113 {125,0x00},
2114 {126,0x00},
2115 {127,0x00},
2116 { 0,0x0D},
2117 { 8,0x14},
2118 { 9,0x00},
2119 { 10,0x00},
2120 { 11,0x00},
2121 { 12,0xFF},
2122 { 13,0x00},
2123 { 14,0x00},
2124 { 15,0x00},
2125 { 16,0xF0},
2126 { 17,0x00},
2127 { 18,0x00},
2128 { 19,0x00},
2129 { 20,0x00},
2130 { 21,0x02},
2131 { 22,0xBB},
2132 { 23,0x00},
2133 { 24,0x7F},
2134 { 25,0xFD},
2135 { 26,0x45},
2136 { 27,0x00},
2137 { 28,0x00},
2138 { 29,0x00},
2139 { 30,0x57},
2140 { 31,0x00},
2141 { 32,0x7F},
2142 { 33,0xFF},
2143 { 34,0xA9},
2144 { 35,0x00},
2145 { 36,0x20},
2146 { 37,0x00},
2147 { 38,0x00},
2148 { 39,0x00},
2149 { 40,0x00},
2150 { 41,0x00},
2151 { 42,0x00},
2152 { 43,0x00},
2153 { 44,0xD7},
2154 { 45,0x41},
2155 { 46,0xA0},
2156 { 47,0x00},
2157 { 48,0xFF},
2158 { 49,0xF0},
2159 { 50,0x00},
2160 { 51,0x00},
2161 { 52,0x88},
2162 { 53,0x00},
2163 { 54,0x00},
2164 { 55,0x00},
2165 { 56,0x18},
2166 { 57,0x00},
2167 { 58,0x00},
2168 { 59,0x00},
2169 { 60,0x00},
2170 { 61,0x00},
2171 { 62,0x00},
2172 { 63,0x00},
2173 { 64,0x0C},
2174 { 65,0x00},
2175 { 66,0x00},
2176 { 67,0x00},
2177 { 68,0xF4},
2178 { 69,0x00},
2179 { 70,0x00},
2180 { 71,0x00},
2181 { 72,0x15},
2182 { 73,0x42},
2183 { 74,0xA6},
2184 { 75,0x00},
2185 { 76,0x7F},
2186 { 77,0xFF},
2187 { 78,0xFF},
2188 { 79,0x00},
2189 { 80,0x0B},
2190 { 81,0xF9},
2191 { 82,0x13},
2192 { 83,0x00},
2193 { 84,0x18},
2194 { 85,0xEC},
2195 { 86,0xF7},
2196 { 87,0x00},
2197 { 88,0x5B},
2198 { 89,0x9E},
2199 { 90,0xC4},
2200 { 91,0x00},
2201 { 92,0x7F},
2202 { 93,0x7B},
2203 { 94,0x30},
2204 { 95,0x00},
2205 { 96,0x00},
2206 { 97,0x00},
2207 { 98,0x00},
2208 { 99,0x00},
2209 {100,0x00},
2210 {101,0x00},
2211 {102,0x00},
2212 {103,0x00},
2213 {104,0x00},
2214 {105,0x00},
2215 {106,0x00},
2216 {107,0x00},
2217 {108,0x00},
2218 {109,0x0D},
2219 {110,0x00},
2220 {111,0x00},
2221 {112,0x00},
2222 {113,0x1C},
2223 {114,0x00},
2224 {115,0x00},
2225 {116,0x00},
2226 {117,0x3E},
2227 {118,0x00},
2228 {119,0x00},
2229 {120,0x00},
2230 {121,0x78},
2231 {122,0x00},
2232 {123,0x00},
2233 {124,0x02},
2234 {125,0x4C},
2235 {126,0x00},
2236 {127,0x00},
2237 { 0,0x0E},
2238 { 8,0x00},
2239 { 9,0xD5},
2240 { 10,0x00},
2241 { 11,0x00},
2242 { 12,0x01},
2243 { 13,0x65},
2244 { 14,0x00},
2245 { 15,0x00},
2246 { 16,0x03},
2247 { 17,0xE9},
2248 { 18,0x00},
2249 { 19,0x00},
2250 { 20,0x07},
2251 { 21,0xCA},
2252 { 22,0x00},
2253 { 23,0x00},
2254 { 24,0xFF},
2255 { 25,0xEF},
2256 { 26,0x00},
2257 { 27,0x00},
2258 { 28,0xFE},
2259 { 29,0xEB},
2260 { 30,0x00},
2261 { 31,0x00},
2262 { 32,0xFF},
2263 { 33,0xA8},
2264 { 34,0x00},
2265 { 35,0x00},
2266 { 36,0xFD},
2267 { 37,0x08},
2268 { 38,0x00},
2269 { 39,0x00},
2270 { 40,0xFF},
2271 { 41,0x5E},
2272 { 42,0x00},
2273 { 43,0x00},
2274 { 44,0xFF},
2275 { 45,0xD5},
2276 { 46,0x00},
2277 { 47,0x00},
2278 { 48,0xFE},
2279 { 49,0x36},
2280 { 50,0x00},
2281 { 51,0x00},
2282 { 52,0xFA},
2283 { 53,0xAC},
2284 { 54,0x00},
2285 { 55,0x00},
2286 { 56,0xF2},
2287 { 57,0xA3},
2288 { 58,0x00},
2289 { 59,0x00},
2290 { 60,0x28},
2291 { 61,0xAB},
2292 { 62,0x00},
2293 { 63,0x00},
2294 { 64,0x3F},
2295 { 65,0xFF},
2296 { 66,0x00},
2297 { 67,0x00},
2298 { 68,0xFF},
2299 { 69,0x98},
2300 { 70,0x00},
2301 { 71,0x00},
2302 { 72,0xF6},
2303 { 73,0xF9},
2304 { 74,0x00},
2305 { 75,0x00},
2306 { 76,0x26},
2307 { 77,0xFB},
2308 { 78,0x00},
2309 { 79,0x00},
2310 { 80,0x02},
2311 { 81,0x72},
2312 { 82,0x00},
2313 { 83,0x00},
2314 { 84,0x40},
2315 { 85,0x02},
2316 { 86,0x00},
2317 { 87,0x00},
2318 { 88,0xFB},
2319 { 89,0xCB},
2320 { 90,0x00},
2321 { 91,0x00},
2322 { 92,0x20},
2323 { 93,0xA7},
2324 { 94,0x00},
2325 { 95,0x00},
2326 { 96,0xFF},
2327 { 97,0x6A},
2328 { 98,0x00},
2329 { 99,0x00},
2330 {100,0x3A},
2331 {101,0x0F},
2332 {102,0x00},
2333 {103,0x00},
2334 { 0,0x0},
2335 { 0x7F,0x3C},
2336 { 0,0x01},
2337 { 8,0xC0},
2338 { 9,0x00},
2339 { 10,0x00},
2340 { 11,0x00},
2341 { 12,0xC0},
2342 { 13,0x00},
2343 { 14,0x00},
2344 { 15,0x00},
2345 { 0,0x0},
2346 { 0x7F,0x78},
2347 { 0,0x01},
2348 { 8,0x04},
2349 { 9,0x00},
2350 { 10,0x00},
2351 { 11,0x00},
2352 { 12,0x04},
2353 { 13,0x00},
2354 { 14,0x20},
2355 { 15,0x01},
2356 { 16,0x58},
2357 { 17,0x60},
2358 { 18,0x08},
2359 { 19,0x01},
2360 { 20,0x60},
2361 { 21,0x60},
2362 { 22,0x00},
2363 { 23,0x00},
2364 { 24,0x58},
2365 { 25,0x60},
2366 { 26,0x00},
2367 { 27,0x2D},
2368 { 28,0x00},
2369 { 29,0x00},
2370 { 30,0x00},
2371 { 31,0x00},
2372 { 32,0x44},
2373 { 33,0x00},
2374 { 34,0xC0},
2375 { 35,0x16},
2376 { 36,0x08},
2377 { 37,0x00},
2378 { 38,0x00},
2379 { 39,0xBE},
2380 { 40,0x08},
2381 { 41,0x00},
2382 { 42,0x20},
2383 { 43,0xFE},
2384 { 44,0x08},
2385 { 45,0x00},
2386 { 46,0x00},
2387 { 47,0xBD},
2388 { 48,0x08},
2389 { 49,0x00},
2390 { 50,0x20},
2391 { 51,0xFD},
2392 { 52,0x08},
2393 { 53,0x00},
2394 { 54,0x00},
2395 { 55,0xBC},
2396 { 56,0x08},
2397 { 57,0x00},
2398 { 58,0x20},
2399 { 59,0xFC},
2400 { 60,0x08},
2401 { 61,0x00},
2402 { 62,0x00},
2403 { 63,0xBB},
2404 { 64,0x08},
2405 { 65,0x00},
2406 { 66,0x20},
2407 { 67,0xFB},
2408 { 68,0x08},
2409 { 69,0x00},
2410 { 70,0x00},
2411 { 71,0xBA},
2412 { 72,0x08},
2413 { 73,0x00},
2414 { 74,0x20},
2415 { 75,0xFA},
2416 { 76,0x08},
2417 { 77,0x00},
2418 { 78,0x00},
2419 { 79,0xB9},
2420 { 80,0x08},
2421 { 81,0x00},
2422 { 82,0x20},
2423 { 83,0xF9},
2424 { 84,0x08},
2425 { 85,0x00},
2426 { 86,0x00},
2427 { 87,0xB8},
2428 { 88,0x08},
2429 { 89,0x00},
2430 { 90,0x20},
2431 { 91,0xF8},
2432 { 92,0x08},
2433 { 93,0x00},
2434 { 94,0x00},
2435 { 95,0xB7},
2436 { 96,0x08},
2437 { 97,0x00},
2438 { 98,0x20},
2439 { 99,0xF7},
2440 {100,0x00},
2441 {101,0x00},
2442 {102,0x00},
2443 {103,0x00},
2444 {104,0x00},
2445 {105,0x00},
2446 {106,0x00},
2447 {107,0x00},
2448 {108,0x00},
2449 {109,0x00},
2450 {110,0x00},
2451 {111,0x00},
2452 {112,0x00},
2453 {113,0x00},
2454 {114,0x00},
2455 {115,0x00},
2456 {116,0x00},
2457 {117,0x00},
2458 {118,0x00},
2459 {119,0x00},
2460 {120,0x44},
2461 {121,0x00},
2462 {122,0x00},
2463 {123,0x06},
2464 {124,0x21},
2465 {125,0x00},
2466 {126,0x20},
2467 {127,0x00},
2468 { 0,0x02},
2469 { 8,0x4B},
2470 { 9,0x00},
2471 { 10,0xC0},
2472 { 11,0x00},
2473 { 12,0x4B},
2474 { 13,0x00},
2475 { 14,0xE0},
2476 { 15,0x00},
2477 { 16,0x00},
2478 { 17,0x00},
2479 { 18,0x40},
2480 { 19,0x48},
2481 { 20,0x0C},
2482 { 21,0x00},
2483 { 22,0x00},
2484 { 23,0x00},
2485 { 24,0x0C},
2486 { 25,0x00},
2487 { 26,0x20},
2488 { 27,0x00},
2489 { 28,0x18},
2490 { 29,0x01},
2491 { 30,0xA0},
2492 { 31,0x00},
2493 { 32,0x18},
2494 { 33,0x01},
2495 { 34,0xA0},
2496 { 35,0x01},
2497 { 36,0x00},
2498 { 37,0x00},
2499 { 38,0x00},
2500 { 39,0x00},
2501 { 40,0x00},
2502 { 41,0x00},
2503 { 42,0x00},
2504 { 43,0x00},
2505 { 44,0x10},
2506 { 45,0x13},
2507 { 46,0xE0},
2508 { 47,0x04},
2509 { 48,0x10},
2510 { 49,0x13},
2511 { 50,0xE0},
2512 { 51,0x05},
2513 { 52,0x18},
2514 { 53,0x01},
2515 { 54,0xA0},
2516 { 55,0x04},
2517 { 56,0x1C},
2518 { 57,0x01},
2519 { 58,0xA0},
2520 { 59,0x05},
2521 { 60,0x00},
2522 { 61,0x00},
2523 { 62,0x00},
2524 { 63,0x00},
2525 { 64,0x00},
2526 { 65,0x00},
2527 { 66,0x00},
2528 { 67,0x00},
2529 { 68,0x00},
2530 { 69,0x00},
2531 { 70,0x00},
2532 { 71,0x00},
2533 { 72,0x10},
2534 { 73,0x00},
2535 { 74,0x00},
2536 { 75,0x08},
2537 { 76,0x18},
2538 { 77,0x04},
2539 { 78,0x40},
2540 { 79,0x08},
2541 { 80,0x1C},
2542 { 81,0x04},
2543 { 82,0x40},
2544 { 83,0x09},
2545 { 84,0x1C},
2546 { 85,0x04},
2547 { 86,0x60},
2548 { 87,0x0B},
2549 { 88,0x00},
2550 { 89,0x00},
2551 { 90,0x00},
2552 { 91,0x00},
2553 { 92,0x00},
2554 { 93,0x00},
2555 { 94,0x00},
2556 { 95,0x00},
2557 { 96,0x00},
2558 { 97,0x00},
2559 { 98,0x00},
2560 { 99,0x00},
2561 {100,0x10},
2562 {101,0x00},
2563 {102,0x00},
2564 {103,0x0A},
2565 {104,0x18},
2566 {105,0x01},
2567 {106,0xA0},
2568 {107,0x04},
2569 {108,0x1C},
2570 {109,0x01},
2571 {110,0xC0},
2572 {111,0x0A},
2573 {112,0x18},
2574 {113,0x01},
2575 {114,0xA0},
2576 {115,0x05},
2577 {116,0x1C},
2578 {117,0x01},
2579 {118,0xC0},
2580 {119,0x0A},
2581 {120,0x00},
2582 {121,0x00},
2583 {122,0x00},
2584 {123,0x00},
2585 {124,0x10},
2586 {125,0x00},
2587 {126,0x00},
2588 {127,0x04},
2589 { 0,0x03},
2590 { 8,0x00},
2591 { 9,0x00},
2592 { 10,0x00},
2593 { 11,0x00},
2594 { 12,0x10},
2595 { 13,0x00},
2596 { 14,0x00},
2597 { 15,0x05},
2598 { 16,0x18},
2599 { 17,0x04},
2600 { 18,0x40},
2601 { 19,0x0A},
2602 { 20,0x1C},
2603 { 21,0x04},
2604 { 22,0x40},
2605 { 23,0x0B},
2606 { 24,0x1C},
2607 { 25,0x04},
2608 { 26,0x60},
2609 { 27,0x0D},
2610 { 28,0x00},
2611 { 29,0x00},
2612 { 30,0x00},
2613 { 31,0x00},
2614 { 32,0x00},
2615 { 33,0x00},
2616 { 34,0x00},
2617 { 35,0x00},
2618 { 36,0x00},
2619 { 37,0x00},
2620 { 38,0x00},
2621 { 39,0x00},
2622 { 40,0x10},
2623 { 41,0x00},
2624 { 42,0x00},
2625 { 43,0x0C},
2626 { 44,0x18},
2627 { 45,0x04},
2628 { 46,0x80},
2629 { 47,0x0C},
2630 { 48,0x1C},
2631 { 49,0x04},
2632 { 50,0xA0},
2633 { 51,0x0E},
2634 { 52,0x6C},
2635 { 53,0x04},
2636 { 54,0xC0},
2637 { 55,0x10},
2638 { 56,0x1C},
2639 { 57,0x04},
2640 { 58,0xE0},
2641 { 59,0x11},
2642 { 60,0x00},
2643 { 61,0x00},
2644 { 62,0x00},
2645 { 63,0x00},
2646 { 64,0x00},
2647 { 65,0x00},
2648 { 66,0x00},
2649 { 67,0x00},
2650 { 68,0x00},
2651 { 69,0x00},
2652 { 70,0x00},
2653 { 71,0x00},
2654 { 72,0x10},
2655 { 73,0x00},
2656 { 74,0x00},
2657 { 75,0x0F},
2658 { 76,0x18},
2659 { 77,0x05},
2660 { 78,0x20},
2661 { 79,0x0E},
2662 { 80,0x1C},
2663 { 81,0x05},
2664 { 82,0x00},
2665 { 83,0x0C},
2666 { 84,0x6C},
2667 { 85,0x05},
2668 { 86,0x40},
2669 { 87,0x13},
2670 { 88,0x1C},
2671 { 89,0x05},
2672 { 90,0x60},
2673 { 91,0x14},
2674 { 92,0x00},
2675 { 93,0x00},
2676 { 94,0x00},
2677 { 95,0x00},
2678 { 96,0x00},
2679 { 97,0x00},
2680 { 98,0x00},
2681 { 99,0x00},
2682 {100,0x00},
2683 {101,0x00},
2684 {102,0x00},
2685 {103,0x00},
2686 {104,0x10},
2687 {105,0x00},
2688 {106,0x00},
2689 {107,0x12},
2690 {108,0x18},
2691 {109,0x01},
2692 {110,0xC0},
2693 {111,0x0F},
2694 {112,0x1C},
2695 {113,0x01},
2696 {114,0xC0},
2697 {115,0x12},
2698 {116,0x00},
2699 {117,0x00},
2700 {118,0x00},
2701 {119,0x00},
2702 {120,0x00},
2703 {121,0x00},
2704 {122,0x00},
2705 {123,0x00},
2706 {124,0x00},
2707 {125,0x00},
2708 {126,0x00},
2709 {127,0x00},
2710 { 0,0x04},
2711 { 8,0x10},
2712 { 9,0x00},
2713 { 10,0x00},
2714 { 11,0x16},
2715 { 12,0x30},
2716 { 13,0x01},
2717 { 14,0xA0},
2718 { 15,0x16},
2719 { 16,0x58},
2720 { 17,0x60},
2721 { 18,0x00},
2722 { 19,0x0E},
2723 { 20,0x00},
2724 { 21,0x00},
2725 { 22,0x00},
2726 { 23,0x00},
2727 { 24,0x00},
2728 { 25,0x00},
2729 { 26,0x00},
2730 { 27,0x00},
2731 { 28,0x20},
2732 { 29,0x02},
2733 { 30,0xE0},
2734 { 31,0x00},
2735 { 32,0x10},
2736 { 33,0x00},
2737 { 34,0x00},
2738 { 35,0x18},
2739 { 36,0x58},
2740 { 37,0x60},
2741 { 38,0x00},
2742 { 39,0x17},
2743 { 40,0x40},
2744 { 41,0x02},
2745 { 42,0xC0},
2746 { 43,0x18},
2747 { 44,0x00},
2748 { 45,0x00},
2749 { 46,0x00},
2750 { 47,0x00},
2751 { 48,0x00},
2752 { 49,0x00},
2753 { 50,0x00},
2754 { 51,0x00},
2755 { 52,0x00},
2756 { 53,0x00},
2757 { 54,0x00},
2758 { 55,0x00},
2759 { 56,0x44},
2760 { 57,0x00},
2761 { 58,0x40},
2762 { 59,0x10},
2763 { 60,0x44},
2764 { 61,0x00},
2765 { 62,0x80},
2766 { 63,0x10},
2767 { 64,0x58},
2768 { 65,0x60},
2769 { 66,0x00},
2770 { 67,0x17},
2771 { 68,0x1C},
2772 { 69,0x02},
2773 { 70,0xC0},
2774 { 71,0x18},
2775 { 72,0x00},
2776 { 73,0x00},
2777 { 74,0x00},
2778 { 75,0x00},
2779 { 76,0x24},
2780 { 77,0x04},
2781 { 78,0x00},
2782 { 79,0x02},
2783 { 80,0x00},
2784 { 81,0x00},
2785 { 82,0x00},
2786 { 83,0x00},
2787 { 84,0x00},
2788 { 85,0x00},
2789 { 86,0x00},
2790 { 87,0x00},
2791 { 88,0x00},
2792 { 89,0x00},
2793 { 90,0x00},
2794 { 91,0x00},
2795 { 92,0x20},
2796 { 93,0x03},
2797 { 94,0x20},
2798 { 95,0x00},
2799 { 96,0x58},
2800 { 97,0x60},
2801 { 98,0x00},
2802 { 99,0x17},
2803 {100,0x1C},
2804 {101,0x03},
2805 {102,0x20},
2806 {103,0x18},
2807 {104,0x00},
2808 {105,0x00},
2809 {106,0x00},
2810 {107,0x00},
2811 {108,0x00},
2812 {109,0x00},
2813 {110,0x00},
2814 {111,0x00},
2815 {112,0x00},
2816 {113,0x00},
2817 {114,0x00},
2818 {115,0x00},
2819 {116,0x20},
2820 {117,0x02},
2821 {118,0xC0},
2822 {119,0x02},
2823 {120,0x44},
2824 {121,0x00},
2825 {122,0x00},
2826 {123,0x10},
2827 {124,0x00},
2828 {125,0x00},
2829 {126,0x00},
2830 {127,0x00},
2831 { 0,0x05},
2832 { 8,0x00},
2833 { 9,0x00},
2834 { 10,0x00},
2835 { 11,0x00},
2836 { 12,0x58},
2837 { 13,0x60},
2838 { 14,0x00},
2839 { 15,0x16},
2840 { 16,0x1C},
2841 { 17,0x02},
2842 { 18,0xE0},
2843 { 19,0x18},
2844 { 20,0x00},
2845 { 21,0x00},
2846 { 22,0x00},
2847 { 23,0x00},
2848 { 24,0x24},
2849 { 25,0x04},
2850 { 26,0x20},
2851 { 27,0x02},
2852 { 28,0x00},
2853 { 29,0x00},
2854 { 30,0x00},
2855 { 31,0x00},
2856 { 32,0x00},
2857 { 33,0x00},
2858 { 34,0x00},
2859 { 35,0x00},
2860 { 36,0x00},
2861 { 37,0x00},
2862 { 38,0x00},
2863 { 39,0x00},
2864 { 40,0x20},
2865 { 41,0x03},
2866 { 42,0x20},
2867 { 43,0x00},
2868 { 44,0x58},
2869 { 45,0x60},
2870 { 46,0x00},
2871 { 47,0x17},
2872 { 48,0x58},
2873 { 49,0x70},
2874 { 50,0x00},
2875 { 51,0x19},
2876 { 52,0x00},
2877 { 53,0x00},
2878 { 54,0x00},
2879 { 55,0x00},
2880 { 56,0x00},
2881 { 57,0x00},
2882 { 58,0x00},
2883 { 59,0x00},
2884 { 60,0x00},
2885 { 61,0x00},
2886 { 62,0x00},
2887 { 63,0x00},
2888 { 64,0x20},
2889 { 65,0x02},
2890 { 66,0xC0},
2891 { 67,0x02},
2892 { 68,0x58},
2893 { 69,0x60},
2894 { 70,0x00},
2895 { 71,0x15},
2896 { 72,0x00},
2897 { 73,0x00},
2898 { 74,0x00},
2899 { 75,0x00},
2900 { 76,0x24},
2901 { 77,0x02},
2902 { 78,0xC0},
2903 { 79,0x02},
2904 { 80,0x00},
2905 { 81,0x00},
2906 { 82,0x00},
2907 { 83,0x00},
2908 { 84,0x00},
2909 { 85,0x00},
2910 { 86,0x00},
2911 { 87,0x00},
2912 { 88,0x00},
2913 { 89,0x00},
2914 { 90,0x00},
2915 { 91,0x00},
2916 { 92,0x20},
2917 { 93,0x03},
2918 { 94,0x00},
2919 { 95,0x00},
2920 { 96,0x24},
2921 { 97,0x03},
2922 { 98,0x00},
2923 { 99,0x00},
2924 {100,0x00},
2925 {101,0x00},
2926 {102,0x00},
2927 {103,0x00},
2928 {104,0x00},
2929 {105,0x00},
2930 {106,0x00},
2931 {107,0x00},
2932 {108,0x00},
2933 {109,0x00},
2934 {110,0x00},
2935 {111,0x00},
2936 {112,0x20},
2937 {113,0x03},
2938 {114,0x00},
2939 {115,0x05},
2940 {116,0x58},
2941 {117,0x60},
2942 {118,0x00},
2943 {119,0x15},
2944 {120,0x00},
2945 {121,0x00},
2946 {122,0x00},
2947 {123,0x00},
2948 {124,0x24},
2949 {125,0x03},
2950 {126,0x00},
2951 {127,0x02},
2952 { 0,0x06},
2953 { 8,0x00},
2954 { 9,0x00},
2955 { 10,0x00},
2956 { 11,0x00},
2957 { 12,0x00},
2958 { 13,0x00},
2959 { 14,0x00},
2960 { 15,0x00},
2961 { 16,0x00},
2962 { 17,0x00},
2963 { 18,0x00},
2964 { 19,0x00},
2965 { 20,0x20},
2966 { 21,0x03},
2967 { 22,0x00},
2968 { 23,0x05},
2969 { 24,0x58},
2970 { 25,0x60},
2971 { 26,0x00},
2972 { 27,0x14},
2973 { 28,0x1C},
2974 { 29,0x03},
2975 { 30,0x00},
2976 { 31,0x18},
2977 { 32,0x00},
2978 { 33,0x00},
2979 { 34,0x00},
2980 { 35,0x00},
2981 { 36,0x24},
2982 { 37,0x02},
2983 { 38,0x60},
2984 { 39,0x00},
2985 { 40,0x58},
2986 { 41,0x70},
2987 { 42,0x00},
2988 { 43,0x15},
2989 { 44,0x00},
2990 { 45,0x00},
2991 { 46,0x00},
2992 { 47,0x00},
2993 { 48,0x00},
2994 { 49,0x00},
2995 { 50,0x00},
2996 { 51,0x00},
2997 { 52,0x00},
2998 { 53,0x00},
2999 { 54,0x00},
3000 { 55,0x00},
3001 { 56,0x20},
3002 { 57,0x02},
3003 { 58,0xA0},
3004 { 59,0x02},
3005 { 60,0x58},
3006 { 61,0x60},
3007 { 62,0x00},
3008 { 63,0x15},
3009 { 64,0x40},
3010 { 65,0x00},
3011 { 66,0xC0},
3012 { 67,0x18},
3013 { 68,0x58},
3014 { 69,0x60},
3015 { 70,0x00},
3016 { 71,0x06},
3017 { 72,0x00},
3018 { 73,0x00},
3019 { 74,0x00},
3020 { 75,0x00},
3021 { 76,0x00},
3022 { 77,0x00},
3023 { 78,0x00},
3024 { 79,0x00},
3025 { 80,0x44},
3026 { 81,0x00},
3027 { 82,0x80},
3028 { 83,0x02},
3029 { 84,0x20},
3030 { 85,0x02},
3031 { 86,0xA0},
3032 { 87,0x02},
3033 { 88,0x44},
3034 { 89,0x00},
3035 { 90,0x00},
3036 { 91,0x02},
3037 { 92,0x00},
3038 { 93,0x00},
3039 { 94,0x00},
3040 { 95,0x00},
3041 { 96,0x00},
3042 { 97,0x00},
3043 { 98,0x00},
3044 { 99,0x00},
3045 {100,0x18},
3046 {101,0x02},
3047 {102,0xA0},
3048 {103,0x16},
3049 {104,0x18},
3050 {105,0x01},
3051 {106,0xE0},
3052 {107,0x0C},
3053 {108,0x00},
3054 {109,0x00},
3055 {110,0x00},
3056 {111,0x00},
3057 {112,0x00},
3058 {113,0x00},
3059 {114,0x00},
3060 {115,0x00},
3061 {116,0x10},
3062 {117,0x00},
3063 {118,0xA0},
3064 {119,0x15},
3065 {120,0x10},
3066 {121,0x00},
3067 {122,0x00},
3068 {123,0x17},
3069 {124,0x18},
3070 {125,0x01},
3071 {126,0xA0},
3072 {127,0x15},
3073 { 0,0x07},
3074 { 8,0x1C},
3075 { 9,0x01},
3076 { 10,0xA0},
3077 { 11,0x17},
3078 { 12,0x00},
3079 { 13,0x00},
3080 { 14,0x00},
3081 { 15,0x00},
3082 { 16,0x24},
3083 { 17,0x00},
3084 { 18,0xA0},
3085 { 19,0x00},
3086 { 20,0x00},
3087 { 21,0x00},
3088 { 22,0x00},
3089 { 23,0x00},
3090 { 24,0x00},
3091 { 25,0x00},
3092 { 26,0x00},
3093 { 27,0x00},
3094 { 28,0x00},
3095 { 29,0x00},
3096 { 30,0x00},
3097 { 31,0x00},
3098 { 32,0x10},
3099 { 33,0x00},
3100 { 34,0x00},
3101 { 35,0x19},
3102 { 36,0x58},
3103 { 37,0x60},
3104 { 38,0x00},
3105 { 39,0x0A},
3106 { 40,0x59},
3107 { 41,0x00},
3108 { 42,0x00},
3109 { 43,0x1E},
3110 { 44,0x58},
3111 { 45,0x60},
3112 { 46,0x00},
3113 { 47,0x0A},
3114 { 48,0x59},
3115 { 49,0x00},
3116 { 50,0x00},
3117 { 51,0x1B},
3118 { 52,0x00},
3119 { 53,0x00},
3120 { 54,0x00},
3121 { 55,0x00},
3122 { 56,0x44},
3123 { 57,0x00},
3124 { 58,0x40},
3125 { 59,0x3A},
3126 { 60,0x00},
3127 { 61,0x00},
3128 { 62,0x00},
3129 { 63,0x00},
3130 { 64,0x44},
3131 { 65,0x00},
3132 { 66,0x40},
3133 { 67,0x68},
3134 { 68,0x18},
3135 { 69,0x02},
3136 { 70,0x00},
3137 { 71,0x04},
3138 { 72,0x1C},
3139 { 73,0x02},
3140 { 74,0x20},
3141 { 75,0x05},
3142 { 76,0x00},
3143 { 77,0x00},
3144 { 78,0x00},
3145 { 79,0x00},
3146 { 80,0x58},
3147 { 81,0x60},
3148 { 82,0x00},
3149 { 83,0x0A},
3150 { 84,0x00},
3151 { 85,0x00},
3152 { 86,0x00},
3153 { 87,0x00},
3154 { 88,0x10},
3155 { 89,0x00},
3156 { 90,0x20},
3157 { 91,0x1A},
3158 { 92,0x10},
3159 { 93,0x00},
3160 { 94,0x20},
3161 { 95,0x1B},
3162 { 96,0x59},
3163 { 97,0x00},
3164 { 98,0x00},
3165 { 99,0x1C},
3166 {100,0x00},
3167 {101,0x00},
3168 {102,0x00},
3169 {103,0x00},
3170 {104,0x00},
3171 {105,0x00},
3172 {106,0x00},
3173 {107,0x00},
3174 {108,0x00},
3175 {109,0x00},
3176 {110,0x00},
3177 {111,0x00},
3178 {112,0x44},
3179 {113,0x00},
3180 {114,0x40},
3181 {115,0x0A},
3182 {116,0x18},
3183 {117,0x05},
3184 {118,0xC0},
3185 {119,0x1B},
3186 {120,0x6C},
3187 {121,0x05},
3188 {122,0xE0},
3189 {123,0x1C},
3190 {124,0x1C},
3191 {125,0x06},
3192 {126,0x00},
3193 {127,0x1D},
3194 { 0,0x08},
3195 { 8,0x6C},
3196 { 9,0x06},
3197 { 10,0x20},
3198 { 11,0x1F},
3199 { 12,0x1C},
3200 { 13,0x06},
3201 { 14,0x40},
3202 { 15,0x20},
3203 { 16,0x00},
3204 { 17,0x00},
3205 { 18,0x00},
3206 { 19,0x00},
3207 { 20,0x00},
3208 { 21,0x00},
3209 { 22,0x00},
3210 { 23,0x00},
3211 { 24,0x00},
3212 { 25,0x00},
3213 { 26,0x00},
3214 { 27,0x00},
3215 { 28,0x10},
3216 { 29,0x00},
3217 { 30,0x20},
3218 { 31,0x1E},
3219 { 32,0x44},
3220 { 33,0x00},
3221 { 34,0x00},
3222 { 35,0x0A},
3223 { 36,0x18},
3224 { 37,0x06},
3225 { 38,0x60},
3226 { 39,0x1B},
3227 { 40,0x6C},
3228 { 41,0x06},
3229 { 42,0x80},
3230 { 43,0x1C},
3231 { 44,0x1C},
3232 { 45,0x06},
3233 { 46,0xA0},
3234 { 47,0x1D},
3235 { 48,0x6C},
3236 { 49,0x06},
3237 { 50,0xC0},
3238 { 51,0x1F},
3239 { 52,0x1C},
3240 { 53,0x06},
3241 { 54,0xE0},
3242 { 55,0x20},
3243 { 56,0x00},
3244 { 57,0x00},
3245 { 58,0x00},
3246 { 59,0x00},
3247 { 60,0x00},
3248 { 61,0x00},
3249 { 62,0x00},
3250 { 63,0x00},
3251 { 64,0x00},
3252 { 65,0x00},
3253 { 66,0x00},
3254 { 67,0x00},
3255 { 68,0x10},
3256 { 69,0x00},
3257 { 70,0x40},
3258 { 71,0x1E},
3259 { 72,0x00},
3260 { 73,0x00},
3261 { 74,0x00},
3262 { 75,0x00},
3263 { 76,0x18},
3264 { 77,0x02},
3265 { 78,0x00},
3266 { 79,0x1F},
3267 { 80,0x1C},
3268 { 81,0x07},
3269 { 82,0x00},
3270 { 83,0x1E},
3271 { 84,0x1C},
3272 { 85,0x07},
3273 { 86,0x20},
3274 { 87,0x22},
3275 { 88,0x18},
3276 { 89,0x02},
3277 { 90,0x00},
3278 { 91,0x04},
3279 { 92,0x1C},
3280 { 93,0x02},
3281 { 94,0x00},
3282 { 95,0x05},
3283 { 96,0x00},
3284 { 97,0x00},
3285 { 98,0x00},
3286 { 99,0x00},
3287 {100,0x10},
3288 {101,0x00},
3289 {102,0x20},
3290 {103,0x21},
3291 {104,0x00},
3292 {105,0x00},
3293 {106,0x00},
3294 {107,0x00},
3295 {108,0x10},
3296 {109,0x00},
3297 {110,0x20},
3298 {111,0x23},
3299 {112,0x18},
3300 {113,0x00},
3301 {114,0xE0},
3302 {115,0x21},
3303 {116,0x1C},
3304 {117,0x01},
3305 {118,0x00},
3306 {119,0x23},
3307 {120,0x00},
3308 {121,0x00},
3309 {122,0x00},
3310 {123,0x00},
3311 {124,0x18},
3312 {125,0x00},
3313 {126,0xE0},
3314 {127,0x21},
3315 { 0,0x09},
3316 { 8,0x00},
3317 { 9,0x00},
3318 { 10,0x00},
3319 { 11,0x00},
3320 { 12,0x10},
3321 { 13,0x00},
3322 { 14,0x00},
3323 { 15,0x47},
3324 { 16,0x24},
3325 { 17,0x01},
3326 { 18,0xC0},
3327 { 19,0x00},
3328 { 20,0x00},
3329 { 21,0x00},
3330 { 22,0x00},
3331 { 23,0x00},
3332 { 24,0x1C},
3333 { 25,0x01},
3334 { 26,0x00},
3335 { 27,0x23},
3336 { 28,0x00},
3337 { 29,0x00},
3338 { 30,0x00},
3339 { 31,0x00},
3340 { 32,0x00},
3341 { 33,0x00},
3342 { 34,0x00},
3343 { 35,0x00},
3344 { 36,0x00},
3345 { 37,0x00},
3346 { 38,0x00},
3347 { 39,0x00},
3348 { 40,0x10},
3349 { 41,0x00},
3350 { 42,0x00},
3351 { 43,0x4D},
3352 { 44,0x00},
3353 { 45,0x00},
3354 { 46,0x00},
3355 { 47,0x00},
3356 { 48,0x44},
3357 { 49,0x00},
3358 { 50,0x00},
3359 { 51,0x5E},
3360 { 52,0x18},
3361 { 53,0x02},
3362 { 54,0x00},
3363 { 55,0x04},
3364 { 56,0x18},
3365 { 57,0x02},
3366 { 58,0x00},
3367 { 59,0x05},
3368 { 60,0x00},
3369 { 61,0x00},
3370 { 62,0x00},
3371 { 63,0x00},
3372 { 64,0x00},
3373 { 65,0x00},
3374 { 66,0x00},
3375 { 67,0x00},
3376 { 68,0x10},
3377 { 69,0x00},
3378 { 70,0x20},
3379 { 71,0x24},
3380 { 72,0x10},
3381 { 73,0x00},
3382 { 74,0x20},
3383 { 75,0x2A},
3384 { 76,0x18},
3385 { 77,0x09},
3386 { 78,0x00},
3387 { 79,0x24},
3388 { 80,0x1C},
3389 { 81,0x01},
3390 { 82,0xA0},
3391 { 83,0x25},
3392 { 84,0x1C},
3393 { 85,0x09},
3394 { 86,0x20},
3395 { 87,0x27},
3396 { 88,0x00},
3397 { 89,0x00},
3398 { 90,0x00},
3399 { 91,0x00},
3400 { 92,0x18},
3401 { 93,0x01},
3402 { 94,0xA0},
3403 { 95,0x27},
3404 { 96,0x00},
3405 { 97,0x00},
3406 { 98,0x00},
3407 { 99,0x00},
3408 {100,0x4C},
3409 {101,0x09},
3410 {102,0x40},
3411 {103,0x26},
3412 {104,0x1C},
3413 {105,0x09},
3414 {106,0x60},
3415 {107,0x29},
3416 {108,0x18},
3417 {109,0x09},
3418 {110,0x80},
3419 {111,0x2A},
3420 {112,0x1C},
3421 {113,0x01},
3422 {114,0xA0},
3423 {115,0x2B},
3424 {116,0x00},
3425 {117,0x00},
3426 {118,0x00},
3427 {119,0x00},
3428 {120,0x10},
3429 {121,0x00},
3430 {122,0x00},
3431 {123,0x28},
3432 {124,0x1C},
3433 {125,0x09},
3434 {126,0xA0},
3435 {127,0x2D},
3436 { 0,0x0A},
3437 { 8,0x00},
3438 { 9,0x00},
3439 { 10,0x00},
3440 { 11,0x00},
3441 { 12,0x18},
3442 { 13,0x01},
3443 { 14,0x20},
3444 { 15,0x28},
3445 { 16,0x00},
3446 { 17,0x00},
3447 { 18,0x00},
3448 { 19,0x00},
3449 { 20,0x10},
3450 { 21,0x00},
3451 { 22,0x00},
3452 { 23,0x2C},
3453 { 24,0x18},
3454 { 25,0x01},
3455 { 26,0x20},
3456 { 27,0x2C},
3457 { 28,0x10},
3458 { 29,0x00},
3459 { 30,0x00},
3460 { 31,0x44},
3461 { 32,0x00},
3462 { 33,0x00},
3463 { 34,0x00},
3464 { 35,0x00},
3465 { 36,0x00},
3466 { 37,0x00},
3467 { 38,0x00},
3468 { 39,0x00},
3469 { 40,0x10},
3470 { 41,0x00},
3471 { 42,0x00},
3472 { 43,0x45},
3473 { 44,0x18},
3474 { 45,0x02},
3475 { 46,0x00},
3476 { 47,0x44},
3477 { 48,0x1C},
3478 { 49,0x02},
3479 { 50,0x20},
3480 { 51,0x45},
3481 { 52,0x00},
3482 { 53,0x00},
3483 { 54,0x00},
3484 { 55,0x00},
3485 { 56,0x24},
3486 { 57,0x00},
3487 { 58,0xE0},
3488 { 59,0x01},
3489 { 60,0x00},
3490 { 61,0x00},
3491 { 62,0x00},
3492 { 63,0x00},
3493 { 64,0x24},
3494 { 65,0x02},
3495 { 66,0x40},
3496 { 67,0x00},
3497 { 68,0x00},
3498 { 69,0x00},
3499 { 70,0x00},
3500 { 71,0x00},
3501 { 72,0x00},
3502 { 73,0x00},
3503 { 74,0x00},
3504 { 75,0x00},
3505 { 76,0x00},
3506 { 77,0x00},
3507 { 78,0x00},
3508 { 79,0x00},
3509 { 80,0x10},
3510 { 81,0x00},
3511 { 82,0x40},
3512 { 83,0x46},
3513 { 84,0x18},
3514 { 85,0x02},
3515 { 86,0x00},
3516 { 87,0x44},
3517 { 88,0x1C},
3518 { 89,0x02},
3519 { 90,0x00},
3520 { 91,0x46},
3521 { 92,0x18},
3522 { 93,0x02},
3523 { 94,0x00},
3524 { 95,0x45},
3525 { 96,0x1C},
3526 { 97,0x02},
3527 { 98,0x20},
3528 { 99,0x46},
3529 {100,0x00},
3530 {101,0x00},
3531 {102,0x00},
3532 {103,0x00},
3533 {104,0x10},
3534 {105,0x00},
3535 {106,0x20},
3536 {107,0x47},
3537 {108,0x00},
3538 {109,0x00},
3539 {110,0x00},
3540 {111,0x00},
3541 {112,0x10},
3542 {113,0x00},
3543 {114,0x20},
3544 {115,0x4D},
3545 {116,0x00},
3546 {117,0x00},
3547 {118,0x00},
3548 {119,0x00},
3549 {120,0x44},
3550 {121,0x00},
3551 {122,0x00},
3552 {123,0x2E},
3553 {124,0x18},
3554 {125,0x02},
3555 {126,0x00},
3556 {127,0x04},
3557 { 0,0x0B},
3558 { 8,0x1C},
3559 { 9,0x02},
3560 { 10,0x00},
3561 { 11,0x05},
3562 { 12,0x18},
3563 { 13,0x02},
3564 { 14,0x00},
3565 { 15,0x04},
3566 { 16,0x1C},
3567 { 17,0x02},
3568 { 18,0x20},
3569 { 19,0x05},
3570 { 20,0x00},
3571 { 21,0x00},
3572 { 22,0x00},
3573 { 23,0x00},
3574 { 24,0x10},
3575 { 25,0x00},
3576 { 26,0x20},
3577 { 27,0x2E},
3578 { 28,0x00},
3579 { 29,0x00},
3580 { 30,0x00},
3581 { 31,0x00},
3582 { 32,0x10},
3583 { 33,0x00},
3584 { 34,0x20},
3585 { 35,0x32},
3586 { 36,0x00},
3587 { 37,0x00},
3588 { 38,0x00},
3589 { 39,0x00},
3590 { 40,0x10},
3591 { 41,0x00},
3592 { 42,0x20},
3593 { 43,0x38},
3594 { 44,0x10},
3595 { 45,0x00},
3596 { 46,0x20},
3597 { 47,0x3E},
3598 { 48,0x18},
3599 { 49,0x07},
3600 { 50,0x40},
3601 { 51,0x2E},
3602 { 52,0x1C},
3603 { 53,0x01},
3604 { 54,0xC0},
3605 { 55,0x2F},
3606 { 56,0x1C},
3607 { 57,0x07},
3608 { 58,0x60},
3609 { 59,0x31},
3610 { 60,0x18},
3611 { 61,0x07},
3612 { 62,0x80},
3613 { 63,0x32},
3614 { 64,0x1C},
3615 { 65,0x07},
3616 { 66,0xA0},
3617 { 67,0x34},
3618 { 68,0x00},
3619 { 69,0x00},
3620 { 70,0x00},
3621 { 71,0x00},
3622 { 72,0x10},
3623 { 73,0x00},
3624 { 74,0x00},
3625 { 75,0x30},
3626 { 76,0x6C},
3627 { 77,0x07},
3628 { 78,0xC0},
3629 { 79,0x36},
3630 { 80,0x1C},
3631 { 81,0x07},
3632 { 82,0xE0},
3633 { 83,0x37},
3634 { 84,0x18},
3635 { 85,0x08},
3636 { 86,0x00},
3637 { 87,0x38},
3638 { 88,0x1C},
3639 { 89,0x08},
3640 { 90,0x20},
3641 { 91,0x3A},
3642 { 92,0x00},
3643 { 93,0x00},
3644 { 94,0x00},
3645 { 95,0x00},
3646 { 96,0x10},
3647 { 97,0x00},
3648 { 98,0x00},
3649 { 99,0x35},
3650 {100,0x6C},
3651 {101,0x08},
3652 {102,0x40},
3653 {103,0x3C},
3654 {104,0x1C},
3655 {105,0x08},
3656 {106,0x60},
3657 {107,0x3D},
3658 {108,0x18},
3659 {109,0x08},
3660 {110,0x80},
3661 {111,0x3E},
3662 {112,0x1C},
3663 {113,0x08},
3664 {114,0xA0},
3665 {115,0x40},
3666 {116,0x00},
3667 {117,0x00},
3668 {118,0x00},
3669 {119,0x00},
3670 {120,0x10},
3671 {121,0x00},
3672 {122,0x00},
3673 {123,0x3B},
3674 {124,0x6C},
3675 {125,0x08},
3676 {126,0xC0},
3677 {127,0x42},
3678 { 0,0x0C},
3679 { 8,0x1C},
3680 { 9,0x08},
3681 { 10,0xE0},
3682 { 11,0x43},
3683 { 12,0x18},
3684 { 13,0x02},
3685 { 14,0x00},
3686 { 15,0x35},
3687 { 16,0x1C},
3688 { 17,0x02},
3689 { 18,0x00},
3690 { 19,0x3B},
3691 { 20,0x00},
3692 { 21,0x00},
3693 { 22,0x00},
3694 { 23,0x00},
3695 { 24,0x10},
3696 { 25,0x00},
3697 { 26,0x00},
3698 { 27,0x41},
3699 { 28,0x1C},
3700 { 29,0x02},
3701 { 30,0x00},
3702 { 31,0x41},
3703 { 32,0x00},
3704 { 33,0x00},
3705 { 34,0x00},
3706 { 35,0x00},
3707 { 36,0x24},
3708 { 37,0x00},
3709 { 38,0xE0},
3710 { 39,0x00},
3711 { 40,0x00},
3712 { 41,0x00},
3713 { 42,0x00},
3714 { 43,0x00},
3715 { 44,0x1C},
3716 { 45,0x02},
3717 { 46,0x00},
3718 { 47,0x30},
3719 { 48,0x00},
3720 { 49,0x00},
3721 { 50,0x00},
3722 { 51,0x00},
3723 { 52,0x00},
3724 { 53,0x00},
3725 { 54,0x00},
3726 { 55,0x00},
3727 { 56,0x00},
3728 { 57,0x00},
3729 { 58,0x00},
3730 { 59,0x00},
3731 { 60,0x10},
3732 { 61,0x00},
3733 { 62,0x20},
3734 { 63,0x47},
3735 { 64,0x10},
3736 { 65,0x00},
3737 { 66,0x20},
3738 { 67,0x4D},
3739 { 68,0x18},
3740 { 69,0x02},
3741 { 70,0x00},
3742 { 71,0x47},
3743 { 72,0x18},
3744 { 73,0x02},
3745 { 74,0x00},
3746 { 75,0x4D},
3747 { 76,0x00},
3748 { 77,0x00},
3749 { 78,0x00},
3750 { 79,0x00},
3751 { 80,0x00},
3752 { 81,0x00},
3753 { 82,0x00},
3754 { 83,0x00},
3755 { 84,0x10},
3756 { 85,0x00},
3757 { 86,0x20},
3758 { 87,0x55},
3759 { 88,0x10},
3760 { 89,0x00},
3761 { 90,0x20},
3762 { 91,0x59},
3763 { 92,0x58},
3764 { 93,0x60},
3765 { 94,0x00},
3766 { 95,0x0A},
3767 { 96,0x59},
3768 { 97,0x00},
3769 { 98,0x00},
3770 { 99,0x1B},
3771 {100,0x00},
3772 {101,0x00},
3773 {102,0x00},
3774 {103,0x00},
3775 {104,0x00},
3776 {105,0x00},
3777 {106,0x00},
3778 {107,0x00},
3779 {108,0x00},
3780 {109,0x00},
3781 {110,0x00},
3782 {111,0x00},
3783 {112,0x44},
3784 {113,0x00},
3785 {114,0x40},
3786 {115,0x07},
3787 {116,0x18},
3788 {117,0x02},
3789 {118,0x00},
3790 {119,0x47},
3791 {120,0x1C},
3792 {121,0x02},
3793 {122,0x00},
3794 {123,0x19},
3795 {124,0x18},
3796 {125,0x02},
3797 {126,0x00},
3798 {127,0x4D},
3799 { 0,0x0D},
3800 { 8,0x1C},
3801 { 9,0x02},
3802 { 10,0x00},
3803 { 11,0x19},
3804 { 12,0x00},
3805 { 13,0x00},
3806 { 14,0x00},
3807 { 15,0x00},
3808 { 16,0x10},
3809 { 17,0x00},
3810 { 18,0x20},
3811 { 19,0x02},
3812 { 20,0x44},
3813 { 21,0x00},
3814 { 22,0x00},
3815 { 23,0x07},
3816 { 24,0x18},
3817 { 25,0x02},
3818 { 26,0x00},
3819 { 27,0x19},
3820 { 28,0x1C},
3821 { 29,0x02},
3822 { 30,0x20},
3823 { 31,0x47},
3824 { 32,0x18},
3825 { 33,0x02},
3826 { 34,0x00},
3827 { 35,0x19},
3828 { 36,0x1C},
3829 { 37,0x02},
3830 { 38,0x20},
3831 { 39,0x4D},
3832 { 40,0x00},
3833 { 41,0x00},
3834 { 42,0x00},
3835 { 43,0x00},
3836 { 44,0x10},
3837 { 45,0x00},
3838 { 46,0x20},
3839 { 47,0x02},
3840 { 48,0x00},
3841 { 49,0x00},
3842 { 50,0x00},
3843 { 51,0x00},
3844 { 52,0x10},
3845 { 53,0x00},
3846 { 54,0x20},
3847 { 55,0x03},
3848 { 56,0x18},
3849 { 57,0x09},
3850 { 58,0xC0},
3851 { 59,0x47},
3852 { 60,0x6C},
3853 { 61,0x09},
3854 { 62,0xE0},
3855 { 63,0x48},
3856 { 64,0x1C},
3857 { 65,0x09},
3858 { 66,0xC0},
3859 { 67,0x49},
3860 { 68,0x6C},
3861 { 69,0x0A},
3862 { 70,0x00},
3863 { 71,0x4B},
3864 { 72,0x1C},
3865 { 73,0x0A},
3866 { 74,0x20},
3867 { 75,0x4C},
3868 { 76,0x18},
3869 { 77,0x09},
3870 { 78,0xC0},
3871 { 79,0x4D},
3872 { 80,0x6C},
3873 { 81,0x09},
3874 { 82,0xE0},
3875 { 83,0x4E},
3876 { 84,0x00},
3877 { 85,0x00},
3878 { 86,0x00},
3879 { 87,0x00},
3880 { 88,0x10},
3881 { 89,0x00},
3882 { 90,0x00},
3883 { 91,0x4A},
3884 { 92,0x1C},
3885 { 93,0x09},
3886 { 94,0xC0},
3887 { 95,0x4F},
3888 { 96,0x6C},
3889 { 97,0x0A},
3890 { 98,0x00},
3891 { 99,0x51},
3892 {100,0x1C},
3893 {101,0x0A},
3894 {102,0x20},
3895 {103,0x52},
3896 {104,0x58},
3897 {105,0x60},
3898 {106,0x00},
3899 {107,0x0B},
3900 {108,0x00},
3901 {109,0x00},
3902 {110,0x00},
3903 {111,0x00},
3904 {112,0x00},
3905 {113,0x00},
3906 {114,0x00},
3907 {115,0x00},
3908 {116,0x10},
3909 {117,0x00},
3910 {118,0x00},
3911 {119,0x50},
3912 {120,0x20},
3913 {121,0x03},
3914 {122,0xE0},
3915 {123,0x02},
3916 {124,0x00},
3917 {125,0x00},
3918 {126,0x00},
3919 {127,0x00},
3920 { 0,0x0E},
3921 { 8,0x18},
3922 { 9,0x03},
3923 { 10,0xE0},
3924 { 11,0x4A},
3925 { 12,0x18},
3926 { 13,0x03},
3927 { 14,0xE0},
3928 { 15,0x50},
3929 { 16,0x00},
3930 { 17,0x00},
3931 { 18,0x00},
3932 { 19,0x00},
3933 { 20,0x00},
3934 { 21,0x00},
3935 { 22,0x00},
3936 { 23,0x00},
3937 { 24,0x10},
3938 { 25,0x00},
3939 { 26,0x40},
3940 { 27,0x53},
3941 { 28,0x10},
3942 { 29,0x00},
3943 { 30,0x40},
3944 { 31,0x54},
3945 { 32,0x18},
3946 { 33,0x02},
3947 { 34,0x00},
3948 { 35,0x02},
3949 { 36,0x1C},
3950 { 37,0x02},
3951 { 38,0x00},
3952 { 39,0x53},
3953 { 40,0x18},
3954 { 41,0x02},
3955 { 42,0x00},
3956 { 43,0x03},
3957 { 44,0x1C},
3958 { 45,0x02},
3959 { 46,0x00},
3960 { 47,0x54},
3961 { 48,0x00},
3962 { 49,0x00},
3963 { 50,0x00},
3964 { 51,0x00},
3965 { 52,0x10},
3966 { 53,0x00},
3967 { 54,0x20},
3968 { 55,0x02},
3969 { 56,0x00},
3970 { 57,0x00},
3971 { 58,0x00},
3972 { 59,0x00},
3973 { 60,0x10},
3974 { 61,0x00},
3975 { 62,0x20},
3976 { 63,0x03},
3977 { 64,0x18},
3978 { 65,0x0A},
3979 { 66,0x40},
3980 { 67,0x55},
3981 { 68,0x1C},
3982 { 69,0x0A},
3983 { 70,0x60},
3984 { 71,0x56},
3985 { 72,0x1C},
3986 { 73,0x0A},
3987 { 74,0x80},
3988 { 75,0x58},
3989 { 76,0x18},
3990 { 77,0x0A},
3991 { 78,0x40},
3992 { 79,0x59},
3993 { 80,0x1C},
3994 { 81,0x0A},
3995 { 82,0x60},
3996 { 83,0x5A},
3997 { 84,0x00},
3998 { 85,0x00},
3999 { 86,0x00},
4000 { 87,0x00},
4001 { 88,0x10},
4002 { 89,0x00},
4003 { 90,0x20},
4004 { 91,0x57},
4005 { 92,0x1C},
4006 { 93,0x0A},
4007 { 94,0x80},
4008 { 95,0x5C},
4009 { 96,0x00},
4010 { 97,0x00},
4011 { 98,0x00},
4012 { 99,0x00},
4013 {100,0x00},
4014 {101,0x00},
4015 {102,0x00},
4016 {103,0x00},
4017 {104,0x00},
4018 {105,0x00},
4019 {106,0x00},
4020 {107,0x00},
4021 {108,0x10},
4022 {109,0x00},
4023 {110,0x20},
4024 {111,0x5B},
4025 {112,0x18},
4026 {113,0x01},
4027 {114,0x80},
4028 {115,0x57},
4029 {116,0x18},
4030 {117,0x01},
4031 {118,0x80},
4032 {119,0x5B},
4033 {120,0x00},
4034 {121,0x00},
4035 {122,0x00},
4036 {123,0x00},
4037 {124,0x00},
4038 {125,0x00},
4039 {126,0x00},
4040 {127,0x00},
4041 { 0,0x0F},
4042 { 8,0x10},
4043 { 9,0x00},
4044 { 10,0x00},
4045 { 11,0x5D},
4046 { 12,0x10},
4047 { 13,0x00},
4048 { 14,0x00},
4049 { 15,0x5E},
4050 { 16,0x18},
4051 { 17,0x02},
4052 { 18,0x00},
4053 { 19,0x02},
4054 { 20,0x1C},
4055 { 21,0x02},
4056 { 22,0x00},
4057 { 23,0x5D},
4058 { 24,0x18},
4059 { 25,0x02},
4060 { 26,0x00},
4061 { 27,0x03},
4062 { 28,0x1C},
4063 { 29,0x02},
4064 { 30,0x00},
4065 { 31,0x5E},
4066 { 32,0x00},
4067 { 33,0x00},
4068 { 34,0x00},
4069 { 35,0x00},
4070 { 36,0x10},
4071 { 37,0x00},
4072 { 38,0x20},
4073 { 39,0x02},
4074 { 40,0x00},
4075 { 41,0x00},
4076 { 42,0x00},
4077 { 43,0x00},
4078 { 44,0x10},
4079 { 45,0x00},
4080 { 46,0x20},
4081 { 47,0x03},
4082 { 48,0x58},
4083 { 49,0x60},
4084 { 50,0x00},
4085 { 51,0x00},
4086 { 52,0x59},
4087 { 53,0x00},
4088 { 54,0x00},
4089 { 55,0x61},
4090 { 56,0x58},
4091 { 57,0x70},
4092 { 58,0x00},
4093 { 59,0x00},
4094 { 60,0x59},
4095 { 61,0x00},
4096 { 62,0x00},
4097 { 63,0x61},
4098 { 64,0x00},
4099 { 65,0x00},
4100 { 66,0x00},
4101 { 67,0x00},
4102 { 68,0x44},
4103 { 69,0x00},
4104 { 70,0x40},
4105 { 71,0x05},
4106 { 72,0x00},
4107 { 73,0x00},
4108 { 74,0x00},
4109 { 75,0x00},
4110 { 76,0x44},
4111 { 77,0x00},
4112 { 78,0x40},
4113 { 79,0x08},
4114 { 80,0x58},
4115 { 81,0x60},
4116 { 82,0x00},
4117 { 83,0x2D},
4118 { 84,0x00},
4119 { 85,0x00},
4120 { 86,0x00},
4121 { 87,0x00},
4122 { 88,0x44},
4123 { 89,0x00},
4124 { 90,0x00},
4125 { 91,0x08},
4126 { 92,0x00},
4127 { 93,0x00},
4128 { 94,0x00},
4129 { 95,0x00},
4130 { 96,0x00},
4131 { 97,0x00},
4132 { 98,0x00},
4133 { 99,0x00},
4134 {100,0x18},
4135 {101,0x03},
4136 {102,0x40},
4137 {103,0x00},
4138 {104,0x18},
4139 {105,0x03},
4140 {106,0x40},
4141 {107,0x01},
4142 {108,0x44},
4143 {109,0x00},
4144 {110,0x00},
4145 {111,0x03},
4146 {112,0x18},
4147 {113,0x03},
4148 {114,0x40},
4149 {115,0x02},
4150 {116,0x18},
4151 {117,0x03},
4152 {118,0x40},
4153 {119,0x03},
4154 {120,0x44},
4155 {121,0x00},
4156 {122,0x00},
4157 {123,0x00},
4158 {124,0x00},
4159 {125,0x00},
4160 {126,0x00},
4161 {127,0x00},
4162 { 0,0x10},
4163 { 8,0x10},
4164 { 9,0x00},
4165 { 10,0x20},
4166 { 11,0x5F},
4167 { 12,0x10},
4168 { 13,0x00},
4169 { 14,0x20},
4170 { 15,0x60},
4171 { 16,0x18},
4172 { 17,0x03},
4173 { 18,0x40},
4174 { 19,0x5F},
4175 { 20,0x18},
4176 { 21,0x0A},
4177 { 22,0xE0},
4178 { 23,0x63},
4179 { 24,0x6C},
4180 { 25,0x0A},
4181 { 26,0xC0},
4182 { 27,0x62},
4183 { 28,0x6C},
4184 { 29,0x0B},
4185 { 30,0x00},
4186 { 31,0x65},
4187 { 32,0x10},
4188 { 33,0x00},
4189 { 34,0x20},
4190 { 35,0x61},
4191 { 36,0x1C},
4192 { 37,0x0A},
4193 { 38,0xA0},
4194 { 39,0x61},
4195 { 40,0x1C},
4196 { 41,0x0B},
4197 { 42,0x20},
4198 { 43,0x66},
4199 { 44,0x00},
4200 { 45,0x00},
4201 { 46,0x00},
4202 { 47,0x00},
4203 { 48,0x00},
4204 { 49,0x00},
4205 { 50,0x00},
4206 { 51,0x00},
4207 { 52,0x00},
4208 { 53,0x00},
4209 { 54,0x00},
4210 { 55,0x00},
4211 { 56,0x10},
4212 { 57,0x00},
4213 { 58,0x00},
4214 { 59,0x64},
4215 { 60,0x18},
4216 { 61,0x03},
4217 { 62,0x40},
4218 { 63,0x60},
4219 { 64,0x18},
4220 { 65,0x0B},
4221 { 66,0x80},
4222 { 67,0x69},
4223 { 68,0x6C},
4224 { 69,0x0B},
4225 { 70,0x60},
4226 { 71,0x68},
4227 { 72,0x6C},
4228 { 73,0x0B},
4229 { 74,0xA0},
4230 { 75,0x6B},
4231 { 76,0x10},
4232 { 77,0x00},
4233 { 78,0x20},
4234 { 79,0x67},
4235 { 80,0x1C},
4236 { 81,0x0B},
4237 { 82,0x40},
4238 { 83,0x67},
4239 { 84,0x1C},
4240 { 85,0x0B},
4241 { 86,0xC0},
4242 { 87,0x6C},
4243 { 88,0x00},
4244 { 89,0x00},
4245 { 90,0x00},
4246 { 91,0x00},
4247 { 92,0x00},
4248 { 93,0x00},
4249 { 94,0x00},
4250 { 95,0x00},
4251 { 96,0x00},
4252 { 97,0x00},
4253 { 98,0x00},
4254 { 99,0x00},
4255 {100,0x10},
4256 {101,0x00},
4257 {102,0x00},
4258 {103,0x6A},
4259 {104,0x30},
4260 {105,0x0C},
4261 {106,0x40},
4262 {107,0x64},
4263 {108,0x1C},
4264 {109,0x0C},
4265 {110,0x60},
4266 {111,0x70},
4267 {112,0x30},
4268 {113,0x0C},
4269 {114,0x40},
4270 {115,0x6A},
4271 {116,0x1C},
4272 {117,0x0C},
4273 {118,0x60},
4274 {119,0x72},
4275 {120,0x00},
4276 {121,0x00},
4277 {122,0x00},
4278 {123,0x00},
4279 {124,0x10},
4280 {125,0x00},
4281 {126,0x00},
4282 {127,0x6F},
4283 { 0,0x11},
4284 { 8,0x40},
4285 { 9,0x00},
4286 { 10,0x20},
4287 { 11,0x6F},
4288 { 12,0x10},
4289 { 13,0x00},
4290 { 14,0x00},
4291 { 15,0x71},
4292 { 16,0x00},
4293 { 17,0x00},
4294 { 18,0x00},
4295 { 19,0x00},
4296 { 20,0x18},
4297 { 21,0x03},
4298 { 22,0x40},
4299 { 23,0x6F},
4300 { 24,0x44},
4301 { 25,0x00},
4302 { 26,0x80},
4303 { 27,0x02},
4304 { 28,0x18},
4305 { 29,0x03},
4306 { 30,0x40},
4307 { 31,0x71},
4308 { 32,0x44},
4309 { 33,0x00},
4310 { 34,0x00},
4311 { 35,0x02},
4312 { 36,0x00},
4313 { 37,0x00},
4314 { 38,0x00},
4315 { 39,0x00},
4316 { 40,0x00},
4317 { 41,0x00},
4318 { 42,0x00},
4319 { 43,0x00},
4320 { 44,0x59},
4321 { 45,0x00},
4322 { 46,0x00},
4323 { 47,0x71},
4324 { 48,0x59},
4325 { 49,0x00},
4326 { 50,0x00},
4327 { 51,0x72},
4328 { 52,0x00},
4329 { 53,0x00},
4330 { 54,0x00},
4331 { 55,0x00},
4332 { 56,0x00},
4333 { 57,0x00},
4334 { 58,0x00},
4335 { 59,0x00},
4336 { 60,0x44},
4337 { 61,0x00},
4338 { 62,0x60},
4339 { 63,0x0B},
4340 { 64,0x44},
4341 { 65,0x00},
4342 { 66,0x80},
4343 { 67,0x05},
4344 { 68,0x0C},
4345 { 69,0x00},
4346 { 70,0x80},
4347 { 71,0x03},
4348 { 72,0x58},
4349 { 73,0x60},
4350 { 74,0x00},
4351 { 75,0x2D},
4352 { 76,0x06},
4353 { 77,0x00},
4354 { 78,0x80},
4355 { 79,0x70},
4356 { 80,0x58},
4357 { 81,0x70},
4358 { 82,0x00},
4359 { 83,0x70},
4360 { 84,0x44},
4361 { 85,0x00},
4362 { 86,0x00},
4363 { 87,0x0B},
4364 { 88,0x0C},
4365 { 89,0x00},
4366 { 90,0x80},
4367 { 91,0x0D},
4368 { 92,0x58},
4369 { 93,0x60},
4370 { 94,0x00},
4371 { 95,0x73},
4372 { 96,0x06},
4373 { 97,0x00},
4374 { 98,0x80},
4375 { 99,0x70},
4376 {100,0x58},
4377 {101,0x70},
4378 {102,0x00},
4379 {103,0x70},
4380 {104,0x44},
4381 {105,0x00},
4382 {106,0x00},
4383 {107,0x06},
4384 {108,0x00},
4385 {109,0x00},
4386 {110,0x00},
4387 {111,0x00},
4388 {112,0x0C},
4389 {113,0x00},
4390 {114,0x80},
4391 {115,0x01},
4392 {116,0x58},
4393 {117,0x60},
4394 {118,0x00},
4395 {119,0x74},
4396 {120,0x06},
4397 {121,0x00},
4398 {122,0x80},
4399 {123,0x70},
4400 {124,0x58},
4401 {125,0x70},
4402 {126,0x00},
4403 {127,0x70},
4404 { 0,0x12},
4405 { 8,0x00},
4406 { 9,0x00},
4407 { 10,0x00},
4408 { 11,0x00},
4409 { 12,0x00},
4410 { 13,0x00},
4411 { 14,0x00},
4412 { 15,0x00},
4413 { 16,0x00},
4414 { 17,0x00},
4415 { 18,0x00},
4416 { 19,0x00},
4417 { 20,0x20},
4418 { 21,0x0E},
4419 { 22,0x00},
4420 { 23,0x01},
4421 { 24,0x58},
4422 { 25,0x60},
4423 { 26,0x00},
4424 { 27,0x70},
4425 { 28,0x59},
4426 { 29,0x00},
4427 { 30,0x00},
4428 { 31,0x67},
4429 { 32,0x59},
4430 { 33,0x00},
4431 { 34,0x00},
4432 { 35,0x68},
4433 { 36,0x58},
4434 { 37,0x70},
4435 { 38,0x00},
4436 { 39,0x68},
4437 { 40,0x00},
4438 { 41,0x00},
4439 { 42,0x00},
4440 { 43,0x00},
4441 { 44,0x44},
4442 { 45,0x00},
4443 { 46,0x80},
4444 { 47,0x0B},
4445 { 48,0x44},
4446 { 49,0x00},
4447 { 50,0x80},
4448 { 51,0x05},
4449 { 52,0x20},
4450 { 53,0x0E},
4451 { 54,0xA0},
4452 { 55,0x02},
4453 { 56,0x58},
4454 { 57,0x60},
4455 { 58,0x00},
4456 { 59,0x6A},
4457 { 60,0x58},
4458 { 61,0x60},
4459 { 62,0x00},
4460 { 63,0x66},
4461 { 64,0x58},
4462 { 65,0x60},
4463 { 66,0x00},
4464 { 67,0x2D},
4465 { 68,0x44},
4466 { 69,0x00},
4467 { 70,0x00},
4468 { 71,0x0B},
4469 { 72,0x20},
4470 { 73,0x0E},
4471 { 74,0xA0},
4472 { 75,0x02},
4473 { 76,0x58},
4474 { 77,0x60},
4475 { 78,0x00},
4476 { 79,0x6A},
4477 { 80,0x58},
4478 { 81,0x60},
4479 { 82,0x00},
4480 { 83,0x65},
4481 { 84,0x58},
4482 { 85,0x60},
4483 { 86,0x00},
4484 { 87,0x2D},
4485 { 88,0x44},
4486 { 89,0x00},
4487 { 90,0x00},
4488 { 91,0x06},
4489 { 92,0x58},
4490 { 93,0x60},
4491 { 94,0x00},
4492 { 95,0x70},
4493 { 96,0x58},
4494 { 97,0x70},
4495 { 98,0x00},
4496 { 99,0x67},
4497 {100,0x58},
4498 {101,0x60},
4499 {102,0x00},
4500 {103,0x69},
4501 {104,0x58},
4502 {105,0x60},
4503 {106,0x00},
4504 {107,0x64},
4505 {108,0x58},
4506 {109,0x60},
4507 {110,0x00},
4508 {111,0x2D},
4509 {112,0x20},
4510 {113,0x0E},
4511 {114,0xA0},
4512 {115,0x02},
4513 {116,0x4C},
4514 {117,0x0D},
4515 {118,0xE0},
4516 {119,0x76},
4517 {120,0x4C},
4518 {121,0x0E},
4519 {122,0xA0},
4520 {123,0x73},
4521 {124,0x59},
4522 {125,0x00},
4523 {126,0x00},
4524 {127,0x77},
4525 { 0,0x13},
4526 { 8,0x59},
4527 { 9,0x00},
4528 { 10,0x00},
4529 { 11,0x76},
4530 { 12,0x58},
4531 { 13,0x60},
4532 { 14,0x00},
4533 { 15,0x77},
4534 { 16,0x10},
4535 { 17,0x00},
4536 { 18,0xA0},
4537 { 19,0x75},
4538 { 20,0x44},
4539 { 21,0x00},
4540 { 22,0x60},
4541 { 23,0x05},
4542 { 24,0x44},
4543 { 25,0x00},
4544 { 26,0x80},
4545 { 27,0x06},
4546 { 28,0x00},
4547 { 29,0x00},
4548 { 30,0x00},
4549 { 31,0x00},
4550 { 32,0x00},
4551 { 33,0x00},
4552 { 34,0x00},
4553 { 35,0x00},
4554 { 36,0x00},
4555 { 37,0x00},
4556 { 38,0x00},
4557 { 39,0x00},
4558 { 40,0x44},
4559 { 41,0x00},
4560 { 42,0x00},
4561 { 43,0x06},
4562 { 44,0x58},
4563 { 45,0x60},
4564 { 46,0x00},
4565 { 47,0x76},
4566 { 48,0x44},
4567 { 49,0x00},
4568 { 50,0x00},
4569 { 51,0x01},
4570 { 52,0x00},
4571 { 53,0x00},
4572 { 54,0x00},
4573 { 55,0x00},
4574 { 56,0x00},
4575 { 57,0x00},
4576 { 58,0x00},
4577 { 59,0x00},
4578 { 60,0x00},
4579 { 61,0x00},
4580 { 62,0x00},
4581 { 63,0x00},
4582 { 64,0x10},
4583 { 65,0x00},
4584 { 66,0xA0},
4585 { 67,0x75},
4586 { 68,0x18},
4587 { 69,0x0F},
4588 { 70,0x00},
4589 { 71,0x75},
4590 { 72,0x64},
4591 { 73,0x00},
4592 { 74,0xC0},
4593 { 75,0x00},
4594 { 76,0x0C},
4595 { 77,0x07},
4596 { 78,0x40},
4597 { 79,0x02},
4598 { 80,0x64},
4599 { 81,0x30},
4600 { 82,0x20},
4601 { 83,0x79},
4602 { 84,0x00},
4603 { 85,0x00},
4604 { 86,0x00},
4605 { 87,0x00},
4606 { 88,0x00},
4607 { 89,0x00},
4608 { 90,0x00},
4609 { 91,0x00},
4610 { 92,0x58},
4611 { 93,0x60},
4612 { 94,0x00},
4613 { 95,0x7A},
4614 { 96,0x20},
4615 { 97,0x0F},
4616 { 98,0xC0},
4617 { 99,0x00},
4618 {100,0x58},
4619 {101,0x60},
4620 {102,0x00},
4621 {103,0x7B},
4622 {104,0x38},
4623 {105,0x0F},
4624 {106,0xC0},
4625 {107,0x76},
4626 {108,0x58},
4627 {109,0x60},
4628 {110,0x00},
4629 {111,0x7C},
4630 {112,0x38},
4631 {113,0x0F},
4632 {114,0xC0},
4633 {115,0x76},
4634 {116,0x58},
4635 {117,0x60},
4636 {118,0x00},
4637 {119,0x7D},
4638 {120,0x38},
4639 {121,0x0F},
4640 {122,0xC0},
4641 {123,0x76},
4642 {124,0x64},
4643 {125,0x03},
4644 {126,0x40},
4645 {127,0x00},
4646 { 0,0x14},
4647 { 8,0x64},
4648 { 9,0x20},
4649 { 10,0x60},
4650 { 11,0x00},
4651 { 12,0x00},
4652 { 13,0x00},
4653 { 14,0x00},
4654 { 15,0x00},
4655 { 16,0x00},
4656 { 17,0x00},
4657 { 18,0x00},
4658 { 19,0x00},
4659 { 20,0x00},
4660 { 21,0x00},
4661 { 22,0x00},
4662 { 23,0x00},
4663 { 24,0x10},
4664 { 25,0x00},
4665 { 26,0x00},
4666 { 27,0x76},
4667 { 28,0x18},
4668 { 29,0x03},
4669 { 30,0x40},
4670 { 31,0x73},
4671 { 32,0x18},
4672 { 33,0x03},
4673 { 34,0x40},
4674 { 35,0x76},
4675 { 36,0x58},
4676 { 37,0x60},
4677 { 38,0x00},
4678 { 39,0x1A},
4679 { 40,0x18},
4680 { 41,0x0C},
4681 { 42,0x00},
4682 { 43,0x7A},
4683 { 44,0x44},
4684 { 45,0x00},
4685 { 46,0xC0},
4686 { 47,0x03},
4687 { 48,0x10},
4688 { 49,0x00},
4689 { 50,0x20},
4690 { 51,0x78},
4691 { 52,0x10},
4692 { 53,0x13},
4693 { 54,0x60},
4694 { 55,0x77},
4695 { 56,0x44},
4696 { 57,0x00},
4697 { 58,0x00},
4698 { 59,0x03},
4699 { 60,0x10},
4700 { 61,0x00},
4701 { 62,0x20},
4702 { 63,0x77},
4703 { 64,0x10},
4704 { 65,0x13},
4705 { 66,0x60},
4706 { 67,0x78},
4707 { 68,0x00},
4708 { 69,0x00},
4709 { 70,0x00},
4710 { 71,0x00},
4711 { 72,0x40},
4712 { 73,0x03},
4713 { 74,0x40},
4714 { 75,0x77},
4715 { 76,0x18},
4716 { 77,0x0D},
4717 { 78,0x80},
4718 { 79,0x7A},
4719 { 80,0x1C},
4720 { 81,0x0D},
4721 { 82,0x60},
4722 { 83,0x77},
4723 { 84,0x18},
4724 { 85,0x0D},
4725 { 86,0xC0},
4726 { 87,0x7A},
4727 { 88,0x1C},
4728 { 89,0x0D},
4729 { 90,0xA0},
4730 { 91,0x77},
4731 { 92,0x44},
4732 { 93,0x00},
4733 { 94,0x60},
4734 { 95,0x03},
4735 { 96,0x10},
4736 { 97,0x00},
4737 { 98,0x00},
4738 { 99,0x79},
4739 {100,0x18},
4740 {101,0x0C},
4741 {102,0x00},
4742 {103,0x7C},
4743 {104,0x44},
4744 {105,0x00},
4745 {106,0x00},
4746 {107,0x03},
4747 {108,0x00},
4748 {109,0x00},
4749 {110,0x00},
4750 {111,0x00},
4751 {112,0x18},
4752 {113,0x0C},
4753 {114,0x00},
4754 {115,0x7C},
4755 {116,0x10},
4756 {117,0x00},
4757 {118,0x00},
4758 {119,0x79},
4759 {120,0x40},
4760 {121,0x03},
4761 {122,0x40},
4762 {123,0x78},
4763 {124,0x64},
4764 {125,0x50},
4765 {126,0x00},
4766 {127,0x79},
4767 { 0,0x15},
4768 { 8,0x00},
4769 { 9,0x00},
4770 { 10,0x00},
4771 { 11,0x00},
4772 { 12,0x00},
4773 { 13,0x00},
4774 { 14,0x00},
4775 { 15,0x00},
4776 { 16,0x44},
4777 { 17,0x00},
4778 { 18,0x60},
4779 { 19,0x03},
4780 { 20,0x18},
4781 { 21,0x0D},
4782 { 22,0xC0},
4783 { 23,0x7C},
4784 { 24,0x1C},
4785 { 25,0x0D},
4786 { 26,0xA0},
4787 { 27,0x78},
4788 { 28,0x44},
4789 { 29,0x00},
4790 { 30,0x00},
4791 { 31,0x03},
4792 { 32,0x18},
4793 { 33,0x0D},
4794 { 34,0x80},
4795 { 35,0x7C},
4796 { 36,0x1C},
4797 { 37,0x0D},
4798 { 38,0x60},
4799 { 39,0x78},
4800 { 40,0x00},
4801 { 41,0x00},
4802 { 42,0x00},
4803 { 43,0x00},
4804 { 44,0x00},
4805 { 45,0x00},
4806 { 46,0x00},
4807 { 47,0x00},
4808 { 48,0x00},
4809 { 49,0x00},
4810 { 50,0x00},
4811 { 51,0x00},
4812 { 52,0x10},
4813 { 53,0x00},
4814 { 54,0x00},
4815 { 55,0x7B},
4816 { 56,0x20},
4817 { 57,0x10},
4818 { 58,0x00},
4819 { 59,0x00},
4820 { 60,0x64},
4821 { 61,0x40},
4822 { 62,0x80},
4823 { 63,0x64},
4824 { 64,0x64},
4825 { 65,0x40},
4826 { 66,0x80},
4827 { 67,0x6A},
4828 { 68,0x24},
4829 { 69,0x10},
4830 { 70,0x00},
4831 { 71,0x08},
4832 { 72,0x24},
4833 { 73,0x10},
4834 { 74,0x00},
4835 { 75,0x08},
4836 { 76,0x00},
4837 { 77,0x00},
4838 { 78,0x00},
4839 { 79,0x00},
4840 { 80,0x00},
4841 { 81,0x00},
4842 { 82,0x00},
4843 { 83,0x00},
4844 { 84,0x10},
4845 { 85,0x01},
4846 { 86,0x00},
4847 { 87,0x6D},
4848 { 88,0x10},
4849 { 89,0x01},
4850 { 90,0x00},
4851 { 91,0x6E},
4852 { 92,0x58},
4853 { 93,0x60},
4854 { 94,0x00},
4855 { 95,0x00},
4856 { 96,0x59},
4857 { 97,0x00},
4858 { 98,0x00},
4859 { 99,0x5F},
4860 {100,0x58},
4861 {101,0x70},
4862 {102,0x00},
4863 {103,0x00},
4864 {104,0x59},
4865 {105,0x00},
4866 {106,0x00},
4867 {107,0x5F},
4868 {108,0x00},
4869 {109,0x00},
4870 {110,0x00},
4871 {111,0x00},
4872 {112,0x44},
4873 {113,0x00},
4874 {114,0x40},
4875 {115,0x05},
4876 {116,0x00},
4877 {117,0x00},
4878 {118,0x00},
4879 {119,0x00},
4880 {120,0x44},
4881 {121,0x00},
4882 {122,0x40},
4883 {123,0x08},
4884 {124,0x58},
4885 {125,0x60},
4886 {126,0x00},
4887 {127,0x2D},
4888 { 0,0x16},
4889 { 8,0x00},
4890 { 9,0x00},
4891 { 10,0x00},
4892 { 11,0x00},
4893 { 12,0x44},
4894 { 13,0x00},
4895 { 14,0x00},
4896 { 15,0x08},
4897 { 16,0x00},
4898 { 17,0x00},
4899 { 18,0x00},
4900 { 19,0x00},
4901 { 20,0x00},
4902 { 21,0x00},
4903 { 22,0x00},
4904 { 23,0x00},
4905 { 24,0x18},
4906 { 25,0x03},
4907 { 26,0x40},
4908 { 27,0x5F},
4909 { 28,0x18},
4910 { 29,0x03},
4911 { 30,0x40},
4912 { 31,0x60},
4913 { 32,0x44},
4914 { 33,0x00},
4915 { 34,0x00},
4916 { 35,0x03},
4917 { 36,0x18},
4918 { 37,0x03},
4919 { 38,0x40},
4920 { 39,0x6D},
4921 { 40,0x18},
4922 { 41,0x03},
4923 { 42,0x40},
4924 { 43,0x6E},
4925 { 44,0x44},
4926 { 45,0x00},
4927 { 46,0x00},
4928 { 47,0x00},
4929 { 48,0x00},
4930 { 49,0x00},
4931 { 50,0x00},
4932 { 51,0x00},
4933 { 52,0x10},
4934 { 53,0x00},
4935 { 54,0x20},
4936 { 55,0x7D},
4937 { 56,0x10},
4938 { 57,0x00},
4939 { 58,0x20},
4940 { 59,0x7E},
4941 { 60,0x18},
4942 { 61,0x03},
4943 { 62,0x40},
4944 { 63,0x7D},
4945 { 64,0x18},
4946 { 65,0x03},
4947 { 66,0x40},
4948 { 67,0x7E},
4949 { 68,0x18},
4950 { 69,0x00},
4951 { 70,0x60},
4952 { 71,0x82},
4953 { 72,0x1C},
4954 { 73,0x00},
4955 { 74,0x80},
4956 { 75,0x84},
4957 { 76,0x10},
4958 { 77,0x00},
4959 { 78,0x20},
4960 { 79,0x81},
4961 { 80,0x10},
4962 { 81,0x00},
4963 { 82,0x20},
4964 { 83,0xBF},
4965 { 84,0x1C},
4966 { 85,0x00},
4967 { 86,0x40},
4968 { 87,0x81},
4969 { 88,0x18},
4970 { 89,0x00},
4971 { 90,0x60},
4972 { 91,0xC0},
4973 { 92,0x1C},
4974 { 93,0x00},
4975 { 94,0x80},
4976 { 95,0xC4},
4977 { 96,0x1C},
4978 { 97,0x00},
4979 { 98,0x40},
4980 { 99,0xBF},
4981 {100,0x10},
4982 {101,0x30},
4983 {102,0x00},
4984 {103,0x83},
4985 {104,0x00},
4986 {105,0x00},
4987 {106,0x00},
4988 {107,0x00},
4989 {108,0x00},
4990 {109,0x00},
4991 {110,0x00},
4992 {111,0x00},
4993 {112,0x10},
4994 {113,0x30},
4995 {114,0x00},
4996 {115,0xC3},
4997 {116,0x18},
4998 {117,0x10},
4999 {118,0x20},
5000 {119,0xA8},
5001 {120,0x1C},
5002 {121,0x10},
5003 {122,0x40},
5004 {123,0x85},
5005 {124,0x1C},
5006 {125,0x10},
5007 {126,0x20},
5008 {127,0x83},
5009 { 0,0x17},
5010 { 8,0x1C},
5011 { 9,0x10},
5012 { 10,0x40},
5013 { 11,0xA6},
5014 { 12,0x1C},
5015 { 13,0x10},
5016 { 14,0x60},
5017 { 15,0x87},
5018 { 16,0x1C},
5019 { 17,0x10},
5020 { 18,0x60},
5021 { 19,0xA4},
5022 { 20,0x1C},
5023 { 21,0x10},
5024 { 22,0x80},
5025 { 23,0x89},
5026 { 24,0x1C},
5027 { 25,0x10},
5028 { 26,0x80},
5029 { 27,0xA2},
5030 { 28,0x1C},
5031 { 29,0x10},
5032 { 30,0xA0},
5033 { 31,0x8F},
5034 { 32,0x1C},
5035 { 33,0x10},
5036 { 34,0xA0},
5037 { 35,0x9C},
5038 { 36,0x1C},
5039 { 37,0x10},
5040 { 38,0xC0},
5041 { 39,0x8B},
5042 { 40,0x1C},
5043 { 41,0x10},
5044 { 42,0xC0},
5045 { 43,0xA0},
5046 { 44,0x1C},
5047 { 45,0x10},
5048 { 46,0xE0},
5049 { 47,0x8D},
5050 { 48,0x1C},
5051 { 49,0x10},
5052 { 50,0xE0},
5053 { 51,0x9E},
5054 { 52,0x1C},
5055 { 53,0x11},
5056 { 54,0x00},
5057 { 55,0x91},
5058 { 56,0x1C},
5059 { 57,0x11},
5060 { 58,0x00},
5061 { 59,0x9A},
5062 { 60,0x1C},
5063 { 61,0x11},
5064 { 62,0x20},
5065 { 63,0x93},
5066 { 64,0x1C},
5067 { 65,0x11},
5068 { 66,0x20},
5069 { 67,0x98},
5070 { 68,0x1C},
5071 { 69,0x11},
5072 { 70,0x40},
5073 { 71,0x84},
5074 { 72,0x1C},
5075 { 73,0x11},
5076 { 74,0x40},
5077 { 75,0xA7},
5078 { 76,0x1C},
5079 { 77,0x11},
5080 { 78,0x60},
5081 { 79,0x8C},
5082 { 80,0x1C},
5083 { 81,0x11},
5084 { 82,0x60},
5085 { 83,0x9F},
5086 { 84,0x1C},
5087 { 85,0x11},
5088 { 86,0x80},
5089 { 87,0x88},
5090 { 88,0x1C},
5091 { 89,0x11},
5092 { 90,0x80},
5093 { 91,0xA3},
5094 { 92,0x1C},
5095 { 93,0x11},
5096 { 94,0xA0},
5097 { 95,0x90},
5098 { 96,0x1C},
5099 { 97,0x11},
5100 { 98,0xA0},
5101 { 99,0x9B},
5102 {100,0x1C},
5103 {101,0x11},
5104 {102,0xC0},
5105 {103,0x8A},
5106 {104,0x1C},
5107 {105,0x11},
5108 {106,0xC0},
5109 {107,0xA1},
5110 {108,0x1C},
5111 {109,0x11},
5112 {110,0xE0},
5113 {111,0x86},
5114 {112,0x1C},
5115 {113,0x11},
5116 {114,0xE0},
5117 {115,0xA5},
5118 {116,0x1C},
5119 {117,0x12},
5120 {118,0x00},
5121 {119,0x8E},
5122 {120,0x1C},
5123 {121,0x12},
5124 {122,0x00},
5125 {123,0x9D},
5126 {124,0x1C},
5127 {125,0x12},
5128 {126,0x20},
5129 {127,0x92},
5130 { 0,0x18},
5131 { 8,0x1C},
5132 { 9,0x12},
5133 { 10,0x20},
5134 { 11,0x99},
5135 { 12,0x1C},
5136 { 13,0x12},
5137 { 14,0x40},
5138 { 15,0x94},
5139 { 16,0x1C},
5140 { 17,0x12},
5141 { 18,0x40},
5142 { 19,0x97},
5143 { 20,0x1C},
5144 { 21,0x12},
5145 { 22,0x60},
5146 { 23,0x95},
5147 { 24,0x1C},
5148 { 25,0x12},
5149 { 26,0x60},
5150 { 27,0x96},
5151 { 28,0x00},
5152 { 29,0x00},
5153 { 30,0x00},
5154 { 31,0x00},
5155 { 32,0x00},
5156 { 33,0x00},
5157 { 34,0x00},
5158 { 35,0x00},
5159 { 36,0x00},
5160 { 37,0x00},
5161 { 38,0x00},
5162 { 39,0x00},
5163 { 40,0x10},
5164 { 41,0x00},
5165 { 42,0x00},
5166 { 43,0xAD},
5167 { 44,0x18},
5168 { 45,0x10},
5169 { 46,0x20},
5170 { 47,0xE8},
5171 { 48,0x1C},
5172 { 49,0x10},
5173 { 50,0x40},
5174 { 51,0xC5},
5175 { 52,0x1C},
5176 { 53,0x10},
5177 { 54,0x20},
5178 { 55,0xC3},
5179 { 56,0x1C},
5180 { 57,0x10},
5181 { 58,0x40},
5182 { 59,0xE6},
5183 { 60,0x1C},
5184 { 61,0x10},
5185 { 62,0x60},
5186 { 63,0xC7},
5187 { 64,0x1C},
5188 { 65,0x10},
5189 { 66,0x60},
5190 { 67,0xE4},
5191 { 68,0x1C},
5192 { 69,0x10},
5193 { 70,0x80},
5194 { 71,0xC9},
5195 { 72,0x1C},
5196 { 73,0x10},
5197 { 74,0x80},
5198 { 75,0xE2},
5199 { 76,0x1C},
5200 { 77,0x10},
5201 { 78,0xA0},
5202 { 79,0xCF},
5203 { 80,0x1C},
5204 { 81,0x10},
5205 { 82,0xA0},
5206 { 83,0xDC},
5207 { 84,0x1C},
5208 { 85,0x10},
5209 { 86,0xC0},
5210 { 87,0xCB},
5211 { 88,0x1C},
5212 { 89,0x10},
5213 { 90,0xC0},
5214 { 91,0xE0},
5215 { 92,0x1C},
5216 { 93,0x10},
5217 { 94,0xE0},
5218 { 95,0xCD},
5219 { 96,0x1C},
5220 { 97,0x10},
5221 { 98,0xE0},
5222 { 99,0xDE},
5223 {100,0x1C},
5224 {101,0x11},
5225 {102,0x00},
5226 {103,0xD1},
5227 {104,0x1C},
5228 {105,0x11},
5229 {106,0x00},
5230 {107,0xDA},
5231 {108,0x1C},
5232 {109,0x11},
5233 {110,0x20},
5234 {111,0xD3},
5235 {112,0x1C},
5236 {113,0x11},
5237 {114,0x20},
5238 {115,0xD8},
5239 {116,0x1C},
5240 {117,0x11},
5241 {118,0x40},
5242 {119,0xC4},
5243 {120,0x1C},
5244 {121,0x11},
5245 {122,0x40},
5246 {123,0xE7},
5247 {124,0x1C},
5248 {125,0x11},
5249 {126,0x60},
5250 {127,0xCC},
5251 { 0,0x19},
5252 { 8,0x1C},
5253 { 9,0x11},
5254 { 10,0x60},
5255 { 11,0xDF},
5256 { 12,0x1C},
5257 { 13,0x11},
5258 { 14,0x80},
5259 { 15,0xC8},
5260 { 16,0x1C},
5261 { 17,0x11},
5262 { 18,0x80},
5263 { 19,0xE3},
5264 { 20,0x1C},
5265 { 21,0x11},
5266 { 22,0xA0},
5267 { 23,0xD0},
5268 { 24,0x1C},
5269 { 25,0x11},
5270 { 26,0xA0},
5271 { 27,0xDB},
5272 { 28,0x1C},
5273 { 29,0x11},
5274 { 30,0xC0},
5275 { 31,0xCA},
5276 { 32,0x1C},
5277 { 33,0x11},
5278 { 34,0xC0},
5279 { 35,0xE1},
5280 { 36,0x1C},
5281 { 37,0x11},
5282 { 38,0xE0},
5283 { 39,0xC6},
5284 { 40,0x1C},
5285 { 41,0x11},
5286 { 42,0xE0},
5287 { 43,0xE5},
5288 { 44,0x1C},
5289 { 45,0x12},
5290 { 46,0x00},
5291 { 47,0xCE},
5292 { 48,0x1C},
5293 { 49,0x12},
5294 { 50,0x00},
5295 { 51,0xDD},
5296 { 52,0x1C},
5297 { 53,0x12},
5298 { 54,0x20},
5299 { 55,0xD2},
5300 { 56,0x1C},
5301 { 57,0x12},
5302 { 58,0x20},
5303 { 59,0xD9},
5304 { 60,0x1C},
5305 { 61,0x12},
5306 { 62,0x40},
5307 { 63,0xD4},
5308 { 64,0x1C},
5309 { 65,0x12},
5310 { 66,0x40},
5311 { 67,0xD7},
5312 { 68,0x1C},
5313 { 69,0x12},
5314 { 70,0x60},
5315 { 71,0xD5},
5316 { 72,0x1C},
5317 { 73,0x12},
5318 { 74,0x60},
5319 { 75,0xD6},
5320 { 76,0x00},
5321 { 77,0x00},
5322 { 78,0x00},
5323 { 79,0x00},
5324 { 80,0x00},
5325 { 81,0x00},
5326 { 82,0x00},
5327 { 83,0x00},
5328 { 84,0x00},
5329 { 85,0x00},
5330 { 86,0x00},
5331 { 87,0x00},
5332 { 88,0x10},
5333 { 89,0x00},
5334 { 90,0x00},
5335 { 91,0xED},
5336 { 92,0x18},
5337 { 93,0x12},
5338 { 94,0xA0},
5339 { 95,0xEC},
5340 { 96,0x1C},
5341 { 97,0x12},
5342 { 98,0xC0},
5343 { 99,0xEE},
5344 {100,0x1C},
5345 {101,0x12},
5346 {102,0xC0},
5347 {103,0xEB},
5348 {104,0x1C},
5349 {105,0x12},
5350 {106,0xA0},
5351 {107,0xED},
5352 {108,0x1C},
5353 {109,0x12},
5354 {110,0xE0},
5355 {111,0xEA},
5356 {112,0x1C},
5357 {113,0x12},
5358 {114,0xE0},
5359 {115,0xEF},
5360 {116,0x1C},
5361 {117,0x13},
5362 {118,0x00},
5363 {119,0xE9},
5364 {120,0x1C},
5365 {121,0x13},
5366 {122,0x00},
5367 {123,0xF0},
5368 {124,0x18},
5369 {125,0x13},
5370 {126,0x60},
5371 {127,0xF1},
5372 { 0,0x1A},
5373 { 8,0x1C},
5374 { 9,0x13},
5375 { 10,0x60},
5376 { 11,0xF3},
5377 { 12,0x1C},
5378 { 13,0x13},
5379 { 14,0x40},
5380 { 15,0xF6},
5381 { 16,0x4C},
5382 { 17,0x13},
5383 { 18,0x40},
5384 { 19,0xF4},
5385 { 20,0x00},
5386 { 21,0x00},
5387 { 22,0x00},
5388 { 23,0x00},
5389 { 24,0x5C},
5390 { 25,0x90},
5391 { 26,0x60},
5392 { 27,0x03},
5393 { 28,0x18},
5394 { 29,0x12},
5395 { 30,0xA0},
5396 { 31,0xAC},
5397 { 32,0x1C},
5398 { 33,0x12},
5399 { 34,0xA0},
5400 { 35,0xAD},
5401 { 36,0x1C},
5402 { 37,0x12},
5403 { 38,0xC0},
5404 { 39,0xAE},
5405 { 40,0x10},
5406 { 41,0x00},
5407 { 42,0x40},
5408 { 43,0xFD},
5409 { 44,0x1C},
5410 { 45,0x12},
5411 { 46,0xC0},
5412 { 47,0xAB},
5413 { 48,0x1C},
5414 { 49,0x12},
5415 { 50,0xE0},
5416 { 51,0xAA},
5417 { 52,0x1C},
5418 { 53,0x12},
5419 { 54,0xE0},
5420 { 55,0xAF},
5421 { 56,0x1C},
5422 { 57,0x13},
5423 { 58,0x00},
5424 { 59,0xA9},
5425 { 60,0x1C},
5426 { 61,0x13},
5427 { 62,0x00},
5428 { 63,0xB0},
5429 { 64,0x18},
5430 { 65,0x13},
5431 { 66,0x60},
5432 { 67,0xB1},
5433 { 68,0x1C},
5434 { 69,0x13},
5435 { 70,0x60},
5436 { 71,0xB3},
5437 { 72,0x1C},
5438 { 73,0x13},
5439 { 74,0x40},
5440 { 75,0xB6},
5441 { 76,0x4C},
5442 { 77,0x13},
5443 { 78,0x40},
5444 { 79,0xB4},
5445 { 80,0x00},
5446 { 81,0x00},
5447 { 82,0x00},
5448 { 83,0x00},
5449 { 84,0x5C},
5450 { 85,0x90},
5451 { 86,0x40},
5452 { 87,0x03},
5453 { 88,0x00},
5454 { 89,0x00},
5455 { 90,0x00},
5456 { 91,0x00},
5457 { 92,0x00},
5458 { 93,0x00},
5459 { 94,0x00},
5460 { 95,0x00},
5461 { 96,0x00},
5462 { 97,0x00},
5463 { 98,0x00},
5464 { 99,0x00},
5465 {100,0x10},
5466 {101,0x00},
5467 {102,0x40},
5468 {103,0xBD},
5469 {104,0x18},
5470 {105,0x13},
5471 {106,0x80},
5472 {107,0xF4},
5473 {108,0x1C},
5474 {109,0x13},
5475 {110,0x80},
5476 {111,0xF3},
5477 {112,0x1C},
5478 {113,0x13},
5479 {114,0xA0},
5480 {115,0xF1},
5481 {116,0x00},
5482 {117,0x00},
5483 {118,0x00},
5484 {119,0x00},
5485 {120,0x5C},
5486 {121,0x90},
5487 {122,0x60},
5488 {123,0x03},
5489 {124,0x18},
5490 {125,0x13},
5491 {126,0x80},
5492 {127,0xB4},
5493 { 0,0x1B},
5494 { 8,0x1C},
5495 { 9,0x13},
5496 { 10,0x80},
5497 { 11,0xB3},
5498 { 12,0x1C},
5499 { 13,0x13},
5500 { 14,0xA0},
5501 { 15,0xB1},
5502 { 16,0x10},
5503 { 17,0x00},
5504 { 18,0x40},
5505 { 19,0xFC},
5506 { 20,0x18},
5507 { 21,0x13},
5508 { 22,0x20},
5509 { 23,0xEA},
5510 { 24,0x5C},
5511 { 25,0x90},
5512 { 26,0x40},
5513 { 27,0x03},
5514 { 28,0x18},
5515 { 29,0x13},
5516 { 30,0x40},
5517 { 31,0xF3},
5518 { 32,0x1C},
5519 { 33,0x13},
5520 { 34,0x60},
5521 { 35,0xF4},
5522 { 36,0x4C},
5523 { 37,0x13},
5524 { 38,0x40},
5525 { 39,0xF5},
5526 { 40,0x10},
5527 { 41,0x00},
5528 { 42,0x40},
5529 { 43,0xBC},
5530 { 44,0x1C},
5531 { 45,0x13},
5532 { 46,0x60},
5533 { 47,0xF1},
5534 { 48,0x18},
5535 { 49,0x13},
5536 { 50,0x20},
5537 { 51,0xAA},
5538 { 52,0x5C},
5539 { 53,0x90},
5540 { 54,0x60},
5541 { 55,0x03},
5542 { 56,0x18},
5543 { 57,0x13},
5544 { 58,0x40},
5545 { 59,0xB3},
5546 { 60,0x1C},
5547 { 61,0x13},
5548 { 62,0x60},
5549 { 63,0xB4},
5550 { 64,0x4C},
5551 { 65,0x13},
5552 { 66,0x40},
5553 { 67,0xB5},
5554 { 68,0x10},
5555 { 69,0x00},
5556 { 70,0x40},
5557 { 71,0xFB},
5558 { 72,0x1C},
5559 { 73,0x13},
5560 { 74,0x60},
5561 { 75,0xB1},
5562 { 76,0x00},
5563 { 77,0x00},
5564 { 78,0x00},
5565 { 79,0x00},
5566 { 80,0x5C},
5567 { 81,0x90},
5568 { 82,0x40},
5569 { 83,0x03},
5570 { 84,0x18},
5571 { 85,0x13},
5572 { 86,0x80},
5573 { 87,0xF5},
5574 { 88,0x1C},
5575 { 89,0x13},
5576 { 90,0x80},
5577 { 91,0xF1},
5578 { 92,0x1C},
5579 { 93,0x13},
5580 { 94,0xA0},
5581 { 95,0xF4},
5582 { 96,0x10},
5583 { 97,0x00},
5584 { 98,0x40},
5585 { 99,0xBB},
5586 {100,0x5C},
5587 {101,0x90},
5588 {102,0x60},
5589 {103,0x03},
5590 {104,0x00},
5591 {105,0x00},
5592 {106,0x00},
5593 {107,0x00},
5594 {108,0x00},
5595 {109,0x00},
5596 {110,0x00},
5597 {111,0x00},
5598 {112,0x00},
5599 {113,0x00},
5600 {114,0x00},
5601 {115,0x00},
5602 {116,0x10},
5603 {117,0x00},
5604 {118,0x40},
5605 {119,0xFA},
5606 {120,0x18},
5607 {121,0x13},
5608 {122,0x80},
5609 {123,0xB5},
5610 {124,0x1C},
5611 {125,0x13},
5612 {126,0x80},
5613 {127,0xB1},
5614 { 0,0x1C},
5615 { 8,0x1C},
5616 { 9,0x13},
5617 { 10,0xA0},
5618 { 11,0xB4},
5619 { 12,0x18},
5620 { 13,0x12},
5621 { 14,0x80},
5622 { 15,0xD5},
5623 { 16,0x5C},
5624 { 17,0x90},
5625 { 18,0x40},
5626 { 19,0x03},
5627 { 20,0x18},
5628 { 21,0x12},
5629 { 22,0xA0},
5630 { 23,0xF0},
5631 { 24,0x1C},
5632 { 25,0x12},
5633 { 26,0xC0},
5634 { 27,0xE9},
5635 { 28,0x4C},
5636 { 29,0x12},
5637 { 30,0xA0},
5638 { 31,0xE8},
5639 { 32,0x10},
5640 { 33,0x00},
5641 { 34,0x40},
5642 { 35,0xBA},
5643 { 36,0x1C},
5644 { 37,0x12},
5645 { 38,0xC0},
5646 { 39,0xEF},
5647 { 40,0x1C},
5648 { 41,0x12},
5649 { 42,0xE0},
5650 { 43,0xEE},
5651 { 44,0x1C},
5652 { 45,0x12},
5653 { 46,0xE0},
5654 { 47,0xEA},
5655 { 48,0x1C},
5656 { 49,0x13},
5657 { 50,0x00},
5658 { 51,0xED},
5659 { 52,0x1C},
5660 { 53,0x13},
5661 { 54,0x00},
5662 { 55,0xEB},
5663 { 56,0x18},
5664 { 57,0x13},
5665 { 58,0x60},
5666 { 59,0xF5},
5667 { 60,0x1C},
5668 { 61,0x13},
5669 { 62,0x60},
5670 { 63,0xF4},
5671 { 64,0x1C},
5672 { 65,0x13},
5673 { 66,0x40},
5674 { 67,0xF1},
5675 { 68,0x4C},
5676 { 69,0x13},
5677 { 70,0x40},
5678 { 71,0xF2},
5679 { 72,0x18},
5680 { 73,0x12},
5681 { 74,0x80},
5682 { 75,0x95},
5683 { 76,0x5C},
5684 { 77,0x90},
5685 { 78,0x60},
5686 { 79,0x03},
5687 { 80,0x18},
5688 { 81,0x12},
5689 { 82,0xA0},
5690 { 83,0xB0},
5691 { 84,0x1C},
5692 { 85,0x12},
5693 { 86,0xC0},
5694 { 87,0xA9},
5695 { 88,0x4C},
5696 { 89,0x12},
5697 { 90,0xA0},
5698 { 91,0xA8},
5699 { 92,0x10},
5700 { 93,0x00},
5701 { 94,0x40},
5702 { 95,0xF9},
5703 { 96,0x1C},
5704 { 97,0x12},
5705 { 98,0xC0},
5706 { 99,0xAF},
5707 {100,0x1C},
5708 {101,0x12},
5709 {102,0xE0},
5710 {103,0xAE},
5711 {104,0x1C},
5712 {105,0x12},
5713 {106,0xE0},
5714 {107,0xAA},
5715 {108,0x1C},
5716 {109,0x13},
5717 {110,0x00},
5718 {111,0xAD},
5719 {112,0x1C},
5720 {113,0x13},
5721 {114,0x00},
5722 {115,0xAB},
5723 {116,0x18},
5724 {117,0x13},
5725 {118,0x60},
5726 {119,0xB5},
5727 {120,0x1C},
5728 {121,0x13},
5729 {122,0x60},
5730 {123,0xB4},
5731 {124,0x1C},
5732 {125,0x13},
5733 {126,0x40},
5734 {127,0xB1},
5735 { 0,0x1D},
5736 { 8,0x4C},
5737 { 9,0x13},
5738 { 10,0x40},
5739 { 11,0xB2},
5740 { 12,0x00},
5741 { 13,0x00},
5742 { 14,0x00},
5743 { 15,0x00},
5744 { 16,0x5C},
5745 { 17,0x90},
5746 { 18,0x40},
5747 { 19,0x03},
5748 { 20,0x00},
5749 { 21,0x00},
5750 { 22,0x00},
5751 { 23,0x00},
5752 { 24,0x00},
5753 { 25,0x00},
5754 { 26,0x00},
5755 { 27,0x00},
5756 { 28,0x00},
5757 { 29,0x00},
5758 { 30,0x00},
5759 { 31,0x00},
5760 { 32,0x10},
5761 { 33,0x00},
5762 { 34,0x40},
5763 { 35,0xB8},
5764 { 36,0x18},
5765 { 37,0x13},
5766 { 38,0x80},
5767 { 39,0xF2},
5768 { 40,0x1C},
5769 { 41,0x13},
5770 { 42,0x80},
5771 { 43,0xF4},
5772 { 44,0x1C},
5773 { 45,0x13},
5774 { 46,0xA0},
5775 { 47,0xF5},
5776 { 48,0x10},
5777 { 49,0x00},
5778 { 50,0x40},
5779 { 51,0xB9},
5780 { 52,0x00},
5781 { 53,0x00},
5782 { 54,0x00},
5783 { 55,0x00},
5784 { 56,0x5C},
5785 { 57,0x90},
5786 { 58,0x60},
5787 { 59,0x03},
5788 { 60,0x18},
5789 { 61,0x13},
5790 { 62,0x80},
5791 { 63,0xB2},
5792 { 64,0x1C},
5793 { 65,0x13},
5794 { 66,0x80},
5795 { 67,0xB4},
5796 { 68,0x1C},
5797 { 69,0x13},
5798 { 70,0xA0},
5799 { 71,0xB5},
5800 { 72,0x10},
5801 { 73,0x00},
5802 { 74,0x40},
5803 { 75,0xF8},
5804 { 76,0x18},
5805 { 77,0x13},
5806 { 78,0x20},
5807 { 79,0xEE},
5808 { 80,0x5C},
5809 { 81,0x90},
5810 { 82,0x40},
5811 { 83,0x03},
5812 { 84,0x18},
5813 { 85,0x13},
5814 { 86,0x40},
5815 { 87,0xF4},
5816 { 88,0x1C},
5817 { 89,0x13},
5818 { 90,0x60},
5819 { 91,0xF2},
5820 { 92,0x4C},
5821 { 93,0x13},
5822 { 94,0x40},
5823 { 95,0xF0},
5824 { 96,0x10},
5825 { 97,0x00},
5826 { 98,0x40},
5827 { 99,0xB8},
5828 {100,0x1C},
5829 {101,0x13},
5830 {102,0x60},
5831 {103,0xF5},
5832 {104,0x18},
5833 {105,0x13},
5834 {106,0x20},
5835 {107,0xAE},
5836 {108,0x5C},
5837 {109,0x90},
5838 {110,0x60},
5839 {111,0x03},
5840 {112,0x18},
5841 {113,0x13},
5842 {114,0x40},
5843 {115,0xB4},
5844 {116,0x1C},
5845 {117,0x13},
5846 {118,0x60},
5847 {119,0xB2},
5848 {120,0x4C},
5849 {121,0x13},
5850 {122,0x40},
5851 {123,0xB0},
5852 {124,0x10},
5853 {125,0x00},
5854 {126,0x40},
5855 {127,0xF7},
5856 { 0,0x1E},
5857 { 8,0x1C},
5858 { 9,0x13},
5859 { 10,0x60},
5860 { 11,0xB5},
5861 { 12,0x00},
5862 { 13,0x00},
5863 { 14,0x00},
5864 { 15,0x00},
5865 { 16,0x5C},
5866 { 17,0x90},
5867 { 18,0x40},
5868 { 19,0x03},
5869 { 20,0x18},
5870 { 21,0x13},
5871 { 22,0x80},
5872 { 23,0xF0},
5873 { 24,0x1C},
5874 { 25,0x13},
5875 { 26,0x80},
5876 { 27,0xF5},
5877 { 28,0x1C},
5878 { 29,0x13},
5879 { 30,0xA0},
5880 { 31,0xF2},
5881 { 32,0x10},
5882 { 33,0x00},
5883 { 34,0x40},
5884 { 35,0xB7},
5885 { 36,0x00},
5886 { 37,0x00},
5887 { 38,0x00},
5888 { 39,0x00},
5889 { 40,0x5C},
5890 { 41,0x90},
5891 { 42,0x60},
5892 { 43,0x03},
5893 { 44,0x18},
5894 { 45,0x13},
5895 { 46,0x80},
5896 { 47,0xB0},
5897 { 48,0x1C},
5898 { 49,0x13},
5899 { 50,0x80},
5900 { 51,0xB5},
5901 { 52,0x1C},
5902 { 53,0x13},
5903 { 54,0xA0},
5904 { 55,0xB2},
5905 { 56,0x10},
5906 { 57,0x00},
5907 { 58,0x40},
5908 { 59,0xF6},
5909 { 60,0x5C},
5910 { 61,0x90},
5911 { 62,0x40},
5912 { 63,0x03},
5913 { 64,0x00},
5914 { 65,0x00},
5915 { 66,0x00},
5916 { 67,0x00},
5917 { 68,0x00},
5918 { 69,0x00},
5919 { 70,0x00},
5920 { 71,0x00},
5921 { 72,0x00},
5922 { 73,0x00},
5923 { 74,0x00},
5924 { 75,0x00},
5925 { 76,0x10},
5926 { 77,0x00},
5927 { 78,0x40},
5928 { 79,0xB6},
5929 { 80,0x00},
5930 { 81,0x00},
5931 { 82,0x00},
5932 { 83,0x00},
5933 { 84,0x00},
5934 { 85,0x00},
5935 { 86,0x00},
5936 { 87,0x00},
5937 { 88,0x00},
5938 { 89,0x00},
5939 { 90,0x00},
5940 { 91,0x00},
5941 { 92,0x02},
5942 { 93,0x00},
5943 { 94,0x00},
5944 { 95,0x00},
5945 { 96,0x00},
5946 { 97,0x00},
5947 { 98,0x00},
5948 { 99,0x00},
5949};
5950
5951reg_value SRS_OFF_miniDSP_D_reg_values[] = {
5952 { 0,0x0},
5953 { 0x7F,0x50},
5954 { 0,0x04},
5955 { 36,0x00},
5956 { 37,0x00},
5957 { 38,0x01},
5958 { 39,0x00},
5959 { 0,0x0C},
5960 {100,0x00},
5961 {101,0x00},
5962 {102,0x01},
5963 {103,0x00},
5964};
5965
5966reg_value SRS_ON_miniDSP_D_reg_values[] = {
5967 { 0,0x0},
5968 { 0x7F,0x50},
5969 { 0,0x04},
5970 { 36,0x00},
5971 { 37,0x00},
5972 { 38,0x02},
5973 { 39,0x00},
5974 { 0,0x0C},
5975 {100,0x00},
5976 {101,0x00},
5977 {102,0x02},
5978 {103,0x00},
5979};
diff --git a/sound/soc/codecs/first_rate_pps_driver.h b/sound/soc/codecs/first_rate_pps_driver.h
new file mode 100644
index 00000000000..95d1996b742
--- /dev/null
+++ b/sound/soc/codecs/first_rate_pps_driver.h
@@ -0,0 +1,5959 @@
1static control main44_MUX_controls[] = {
2/*{4,28,1,0},
3{4,36,1,1},
4{4,112,1,2}*/
5};
6
7static char * main44_MUX_control_names[] = {
8/*"Stereo_Mux_1",
9"Stereo_Mux_3",
10"Stereo_Mux_4"*/
11};
12
13static control main44_VOLUME_controls[] = {
14};
15
16static char * main44_VOLUME_control_names[] = {
17};
18
19/*//INSTRUCTIONS & COEFFICIENTS
20typedef struct {
21 u8 reg_off;
22 u8 reg_val;
23} reg_value;*/
24
25static char * main44_REG_Section_names[] = {
26 "main44_miniDSP_A_reg_values",
27 "main44_miniDSP_D_reg_values",
28};
29
30reg_value main44_REG_Section_init_program[] = {
31 { 0,0x0},
32 { 0x7F,0x00},
33// # Set AutoINC
34 {121,0x01},
35 { 0x7F,0x78},
36// # reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled
37 { 50,0x88},
38 { 0x7F,0x64},
39// # reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled
40 { 50,0xA4},
41 { 0x7F,0x78},
42// # reg[120][0][24]=0x80
43 { 24,0x80},
44};
45
46reg_value main44_REG_Section_post_program[] = {
47 { 0,0x0},
48 { 0x7F,0x28},
49// # reg[40][0][1] = 0x04 ; adaptive mode for ADC
50 { 1,0x04},
51 { 0x7F,0x50},
52// # reg[80][0][1] = 0x04 ; adaptive mode for DAC
53 { 1,0x04},
54 { 0x7F,0x64},
55// # reg[100][0][48] = 4
56 { 48,0x04},
57// # reg[100][0][49] = 0
58 { 49,0x00},
59 { 0x7F,0x78},
60// # reg[120][0][48] = 4
61 { 48,0x04},
62// # reg[120][0][49] = 0
63 { 49,0x00},
64 { 0x7F,0x64},
65// # reg[100][0][20] = 0x00 ; Disable ADC double buffer mode
66 { 20,0x00},
67 { 0x7F,0x78},
68// # reg[120][0][20] = 0x00 ; Disable DAC double buffer mode
69 { 20,0x00},
70
71};
72
73reg_value main44_miniDSP_A_reg_values[] = {
74 { 0,0x0},
75 { 0x7F,0x28},
76 { 0,0x01},
77 { 8,0x00},
78 { 9,0xA7},
79 { 10,0xF8},
80 { 11,0x00},
81 { 12,0x7E},
82 { 13,0xB0},
83 { 14,0x10},
84 { 15,0x00},
85 { 16,0x7F},
86 { 17,0xFF},
87 { 18,0xFF},
88 { 19,0x00},
89 { 20,0x00},
90 { 21,0x00},
91 { 22,0x00},
92 { 23,0x00},
93 { 24,0x00},
94 { 25,0x00},
95 { 26,0x00},
96 { 27,0x00},
97 { 28,0xFF},
98 { 29,0xFF},
99 { 30,0xFF},
100 { 31,0x00},
101 { 32,0x80},
102 { 33,0x00},
103 { 34,0x00},
104 { 35,0x00},
105 { 36,0x7F},
106 { 37,0xFF},
107 { 38,0xFF},
108 { 39,0x00},
109 { 40,0x40},
110 { 41,0x00},
111 { 42,0x00},
112 { 43,0x00},
113 { 44,0x00},
114 { 45,0x00},
115 { 46,0x00},
116 { 47,0x00},
117 { 48,0xFF},
118 { 49,0x9E},
119 { 50,0x00},
120 { 51,0x00},
121 { 52,0xF7},
122 { 53,0x10},
123 { 54,0x00},
124 { 55,0x00},
125 { 56,0x26},
126 { 57,0xF0},
127 { 58,0x00},
128 { 59,0x00},
129 { 60,0x02},
130 { 61,0x61},
131 { 62,0x00},
132 { 63,0x00},
133 { 64,0x40},
134 { 65,0x02},
135 { 66,0x00},
136 { 67,0x00},
137 { 68,0xFF},
138 { 69,0xFC},
139 { 70,0x00},
140 { 71,0x00},
141 { 72,0xFF},
142 { 73,0xFD},
143 { 74,0x00},
144 { 75,0x00},
145 { 76,0xFF},
146 { 77,0xE5},
147 { 78,0x00},
148 { 79,0x00},
149 { 80,0xFF},
150 { 81,0xA7},
151 { 82,0x00},
152 { 83,0x00},
153 { 84,0xFF},
154 { 85,0xC7},
155 { 86,0x00},
156 { 87,0x00},
157 { 88,0xFF},
158 { 89,0xCE},
159 { 90,0x00},
160 { 91,0x00},
161 { 92,0xFF},
162 { 93,0xFE},
163 { 94,0x00},
164 { 95,0x00},
165 { 96,0xFE},
166 { 97,0xF7},
167 { 98,0x00},
168 { 99,0x00},
169 {100,0xFF},
170 {101,0x46},
171 {102,0x00},
172 {103,0x00},
173 {104,0xFF},
174 {105,0x22},
175 {106,0x00},
176 {107,0x00},
177 {108,0x7F},
178 {109,0xFF},
179 {110,0xFF},
180 {111,0x00},
181 {112,0x00},
182 {113,0x00},
183 {114,0x00},
184 {115,0x00},
185 {116,0x00},
186 {117,0x00},
187 {118,0x00},
188 {119,0x00},
189 {120,0x00},
190 {121,0x00},
191 {122,0x00},
192 {123,0x00},
193 {124,0x00},
194 {125,0x00},
195 {126,0x00},
196 {127,0x00},
197 { 0,0x02},
198 { 8,0xFF},
199 { 9,0x0F},
200 { 10,0x00},
201 { 11,0x00},
202 { 12,0xFA},
203 { 13,0x8C},
204 { 14,0x00},
205 { 15,0x00},
206 { 16,0xF5},
207 { 17,0x08},
208 { 18,0x00},
209 { 19,0x00},
210 { 20,0xFD},
211 { 21,0x92},
212 { 22,0x00},
213 { 23,0x00},
214 { 24,0xF3},
215 { 25,0xA3},
216 { 26,0x00},
217 { 27,0x00},
218 { 28,0x03},
219 { 29,0xB3},
220 { 30,0x00},
221 { 31,0x00},
222 { 32,0x00},
223 { 33,0x33},
224 { 34,0x00},
225 { 35,0x00},
226 { 36,0x00},
227 { 37,0x71},
228 { 38,0x00},
229 { 39,0x00},
230 { 40,0x40},
231 { 41,0x60},
232 { 42,0x00},
233 { 43,0x00},
234 { 44,0x00},
235 { 45,0xE2},
236 { 46,0x00},
237 { 47,0x00},
238 { 48,0x00},
239 { 49,0xC6},
240 { 50,0x00},
241 { 51,0x00},
242 { 52,0x00},
243 { 53,0x87},
244 { 54,0x00},
245 { 55,0x00},
246 { 56,0x00},
247 { 57,0x0F},
248 { 58,0x00},
249 { 59,0x00},
250 { 60,0x00},
251 { 61,0x0A},
252 { 62,0x00},
253 { 63,0x00},
254 { 64,0x00},
255 { 65,0x02},
256 { 66,0x00},
257 { 67,0x00},
258 { 68,0x01},
259 { 69,0x81},
260 { 70,0x00},
261 { 71,0x00},
262 { 72,0x18},
263 { 73,0x89},
264 { 74,0x00},
265 { 75,0x00},
266 { 76,0x07},
267 { 77,0xFB},
268 { 78,0x00},
269 { 79,0x00},
270 { 80,0x03},
271 { 81,0xBE},
272 { 82,0x00},
273 { 83,0x00},
274 { 0,0x09},
275 { 72,0x00},
276 { 73,0xA7},
277 { 74,0xF8},
278 { 75,0x00},
279 { 76,0x7E},
280 { 77,0xB0},
281 { 78,0x10},
282 { 79,0x00},
283 { 80,0x7F},
284 { 81,0xFF},
285 { 82,0xFF},
286 { 83,0x00},
287 { 84,0x00},
288 { 85,0x00},
289 { 86,0x00},
290 { 87,0x00},
291 { 88,0x00},
292 { 89,0x00},
293 { 90,0x00},
294 { 91,0x00},
295 { 92,0xFF},
296 { 93,0xFF},
297 { 94,0xFF},
298 { 95,0x00},
299 { 96,0x80},
300 { 97,0x00},
301 { 98,0x00},
302 { 99,0x00},
303 {100,0x7F},
304 {101,0xFF},
305 {102,0xFF},
306 {103,0x00},
307 {104,0x40},
308 {105,0x00},
309 {106,0x00},
310 {107,0x00},
311 {108,0x00},
312 {109,0x00},
313 {110,0x00},
314 {111,0x00},
315 {112,0xFF},
316 {113,0x9E},
317 {114,0x00},
318 {115,0x00},
319 {116,0xF7},
320 {117,0x10},
321 {118,0x00},
322 {119,0x00},
323 {120,0x26},
324 {121,0xF0},
325 {122,0x00},
326 {123,0x00},
327 {124,0x02},
328 {125,0x61},
329 {126,0x00},
330 {127,0x00},
331 { 0,0x0A},
332 { 8,0x40},
333 { 9,0x02},
334 { 10,0x00},
335 { 11,0x00},
336 { 12,0xFF},
337 { 13,0xFC},
338 { 14,0x00},
339 { 15,0x00},
340 { 16,0xFF},
341 { 17,0xFD},
342 { 18,0x00},
343 { 19,0x00},
344 { 20,0xFF},
345 { 21,0xE5},
346 { 22,0x00},
347 { 23,0x00},
348 { 24,0xFF},
349 { 25,0xA7},
350 { 26,0x00},
351 { 27,0x00},
352 { 28,0xFF},
353 { 29,0xC7},
354 { 30,0x00},
355 { 31,0x00},
356 { 32,0xFF},
357 { 33,0xCE},
358 { 34,0x00},
359 { 35,0x00},
360 { 36,0xFF},
361 { 37,0xFE},
362 { 38,0x00},
363 { 39,0x00},
364 { 40,0xFE},
365 { 41,0xF7},
366 { 42,0x00},
367 { 43,0x00},
368 { 44,0xFF},
369 { 45,0x46},
370 { 46,0x00},
371 { 47,0x00},
372 { 48,0xFF},
373 { 49,0x22},
374 { 50,0x00},
375 { 51,0x00},
376 { 52,0x7F},
377 { 53,0xFF},
378 { 54,0xFF},
379 { 55,0x00},
380 { 56,0x00},
381 { 57,0x00},
382 { 58,0x00},
383 { 59,0x00},
384 { 60,0x00},
385 { 61,0x00},
386 { 62,0x00},
387 { 63,0x00},
388 { 64,0x00},
389 { 65,0x00},
390 { 66,0x00},
391 { 67,0x00},
392 { 68,0x00},
393 { 69,0x00},
394 { 70,0x00},
395 { 71,0x00},
396 { 72,0xFF},
397 { 73,0x0F},
398 { 74,0x00},
399 { 75,0x00},
400 { 76,0xFA},
401 { 77,0x8C},
402 { 78,0x00},
403 { 79,0x00},
404 { 80,0xF5},
405 { 81,0x08},
406 { 82,0x00},
407 { 83,0x00},
408 { 84,0xFD},
409 { 85,0x92},
410 { 86,0x00},
411 { 87,0x00},
412 { 88,0xF3},
413 { 89,0xA3},
414 { 90,0x00},
415 { 91,0x00},
416 { 92,0x03},
417 { 93,0xB3},
418 { 94,0x00},
419 { 95,0x00},
420 { 96,0x00},
421 { 97,0x33},
422 { 98,0x00},
423 { 99,0x00},
424 {100,0x00},
425 {101,0x71},
426 {102,0x00},
427 {103,0x00},
428 {104,0x40},
429 {105,0x60},
430 {106,0x00},
431 {107,0x00},
432 {108,0x00},
433 {109,0xE2},
434 {110,0x00},
435 {111,0x00},
436 {112,0x00},
437 {113,0xC6},
438 {114,0x00},
439 {115,0x00},
440 {116,0x00},
441 {117,0x87},
442 {118,0x00},
443 {119,0x00},
444 {120,0x00},
445 {121,0x0F},
446 {122,0x00},
447 {123,0x00},
448 {124,0x00},
449 {125,0x0A},
450 {126,0x00},
451 {127,0x00},
452 { 0,0x0B},
453 { 8,0x00},
454 { 9,0x02},
455 { 10,0x00},
456 { 11,0x00},
457 { 12,0x01},
458 { 13,0x81},
459 { 14,0x00},
460 { 15,0x00},
461 { 16,0x18},
462 { 17,0x89},
463 { 18,0x00},
464 { 19,0x00},
465 { 20,0x07},
466 { 21,0xFB},
467 { 22,0x00},
468 { 23,0x00},
469 { 24,0x03},
470 { 25,0xBE},
471 { 26,0x00},
472 { 27,0x00},
473 { 0,0x0},
474 { 0x7F,0x14},
475 { 0,0x01},
476 { 8,0xC0},
477 { 9,0x00},
478 { 10,0x00},
479 { 11,0x00},
480 { 12,0xC0},
481 { 13,0x00},
482 { 14,0x00},
483 { 15,0x00},
484 { 0,0x0},
485 { 0x7F,0x64},
486 { 0,0x01},
487 { 8,0x58},
488 { 9,0x60},
489 { 10,0x08},
490 { 11,0x01},
491 { 12,0x60},
492 { 13,0x60},
493 { 14,0x00},
494 { 15,0x00},
495 { 16,0x58},
496 { 17,0x60},
497 { 18,0x00},
498 { 19,0x09},
499 { 20,0x00},
500 { 21,0x00},
501 { 22,0x00},
502 { 23,0x00},
503 { 24,0x44},
504 { 25,0x00},
505 { 26,0xC0},
506 { 27,0x07},
507 { 28,0x04},
508 { 29,0x00},
509 { 30,0x00},
510 { 31,0x00},
511 { 32,0x04},
512 { 33,0x00},
513 { 34,0x00},
514 { 35,0x0D},
515 { 36,0x04},
516 { 37,0x00},
517 { 38,0x00},
518 { 39,0x08},
519 { 40,0x04},
520 { 41,0x00},
521 { 42,0x00},
522 { 43,0x04},
523 { 44,0x00},
524 { 45,0x00},
525 { 46,0x00},
526 { 47,0x00},
527 { 48,0x00},
528 { 49,0x00},
529 { 50,0x00},
530 { 51,0x00},
531 { 52,0x44},
532 { 53,0x00},
533 { 54,0x00},
534 { 55,0x07},
535 { 56,0x21},
536 { 57,0x00},
537 { 58,0x20},
538 { 59,0x00},
539 { 60,0x4B},
540 { 61,0x00},
541 { 62,0xC0},
542 { 63,0x00},
543 { 64,0x4B},
544 { 65,0x00},
545 { 66,0xE0},
546 { 67,0x00},
547 { 68,0x10},
548 { 69,0x00},
549 { 70,0x00},
550 { 71,0x00},
551 { 72,0x10},
552 { 73,0x00},
553 { 74,0x00},
554 { 75,0x0D},
555 { 76,0x10},
556 { 77,0x00},
557 { 78,0x00},
558 { 79,0x08},
559 { 80,0x10},
560 { 81,0x00},
561 { 82,0x00},
562 { 83,0x04},
563 { 84,0x18},
564 { 85,0x01},
565 { 86,0xC0},
566 { 87,0x0F},
567 { 88,0x1C},
568 { 89,0x01},
569 { 90,0xA0},
570 { 91,0x09},
571 { 92,0x1C},
572 { 93,0x01},
573 { 94,0xA0},
574 { 95,0x03},
575 { 96,0x1C},
576 { 97,0x01},
577 { 98,0x80},
578 { 99,0x0A},
579 {100,0x1C},
580 {101,0x01},
581 {102,0x80},
582 {103,0x02},
583 {104,0x1C},
584 {105,0x01},
585 {106,0x40},
586 {107,0x0C},
587 {108,0x1C},
588 {109,0x01},
589 {110,0x40},
590 {111,0x00},
591 {112,0x1C},
592 {113,0x01},
593 {114,0x60},
594 {115,0x01},
595 {116,0x1C},
596 {117,0x01},
597 {118,0x60},
598 {119,0x0B},
599 {120,0x18},
600 {121,0x01},
601 {122,0x40},
602 {123,0x03},
603 {124,0x1C},
604 {125,0x01},
605 {126,0x40},
606 {127,0x08},
607 { 0,0x02},
608 { 8,0x1C},
609 { 9,0x01},
610 { 10,0x60},
611 { 11,0x09},
612 { 12,0x10},
613 { 13,0x00},
614 { 14,0x00},
615 { 15,0x2D},
616 { 16,0x1C},
617 { 17,0x01},
618 { 18,0x60},
619 { 19,0x02},
620 { 20,0x1C},
621 { 21,0x01},
622 { 22,0x80},
623 { 23,0x01},
624 { 24,0x1C},
625 { 25,0x01},
626 { 26,0x80},
627 { 27,0x0A},
628 { 28,0x1C},
629 { 29,0x01},
630 { 30,0xA0},
631 { 31,0x00},
632 { 32,0x1C},
633 { 33,0x01},
634 { 34,0xA0},
635 { 35,0x0B},
636 { 36,0x1C},
637 { 37,0x01},
638 { 38,0xC0},
639 { 39,0x06},
640 { 40,0x00},
641 { 41,0x00},
642 { 42,0x00},
643 { 43,0x00},
644 { 44,0x00},
645 { 45,0x00},
646 { 46,0x00},
647 { 47,0x00},
648 { 48,0x00},
649 { 49,0x00},
650 { 50,0x00},
651 { 51,0x00},
652 { 52,0x10},
653 { 53,0x00},
654 { 54,0x00},
655 { 55,0x0F},
656 { 56,0x18},
657 { 57,0x01},
658 { 58,0xE0},
659 { 59,0x2C},
660 { 60,0x1C},
661 { 61,0x02},
662 { 62,0x00},
663 { 63,0x11},
664 { 64,0x1C},
665 { 65,0x02},
666 { 66,0x00},
667 { 67,0x48},
668 { 68,0x1C},
669 { 69,0x01},
670 { 70,0xE0},
671 { 71,0x2D},
672 { 72,0x1C},
673 { 73,0x02},
674 { 74,0x20},
675 { 75,0x2F},
676 { 76,0x1C},
677 { 77,0x02},
678 { 78,0x20},
679 { 79,0x2A},
680 { 80,0x1C},
681 { 81,0x02},
682 { 82,0x40},
683 { 83,0x31},
684 { 84,0x1C},
685 { 85,0x02},
686 { 86,0x40},
687 { 87,0x28},
688 { 88,0x1C},
689 { 89,0x02},
690 { 90,0x60},
691 { 91,0x37},
692 { 92,0x1C},
693 { 93,0x02},
694 { 94,0x60},
695 { 95,0x22},
696 { 96,0x1C},
697 { 97,0x02},
698 { 98,0x80},
699 { 99,0x14},
700 {100,0x1C},
701 {101,0x02},
702 {102,0x80},
703 {103,0x45},
704 {104,0x1C},
705 {105,0x02},
706 {106,0xA0},
707 {107,0x12},
708 {108,0x1C},
709 {109,0x02},
710 {110,0xA0},
711 {111,0x47},
712 {112,0x1C},
713 {113,0x02},
714 {114,0xC0},
715 {115,0x38},
716 {116,0x1C},
717 {117,0x02},
718 {118,0xC0},
719 {119,0x21},
720 {120,0x1C},
721 {121,0x02},
722 {122,0xE0},
723 {123,0x33},
724 {124,0x1C},
725 {125,0x02},
726 {126,0xE0},
727 {127,0x26},
728 { 0,0x03},
729 { 8,0x1C},
730 { 9,0x03},
731 { 10,0x00},
732 { 11,0x16},
733 { 12,0x1C},
734 { 13,0x03},
735 { 14,0x00},
736 { 15,0x43},
737 { 16,0x1C},
738 { 17,0x03},
739 { 18,0xC0},
740 { 19,0x35},
741 { 20,0x1C},
742 { 21,0x03},
743 { 22,0xC0},
744 { 23,0x24},
745 { 24,0x1C},
746 { 25,0x03},
747 { 26,0xE0},
748 { 27,0x1A},
749 { 28,0x1C},
750 { 29,0x03},
751 { 30,0xE0},
752 { 31,0x3F},
753 { 32,0x1C},
754 { 33,0x04},
755 { 34,0x00},
756 { 35,0x3A},
757 { 36,0x1C},
758 { 37,0x04},
759 { 38,0x00},
760 { 39,0x1F},
761 { 40,0x1C},
762 { 41,0x04},
763 { 42,0x20},
764 { 43,0x18},
765 { 44,0x1C},
766 { 45,0x04},
767 { 46,0x20},
768 { 47,0x41},
769 { 48,0x1C},
770 { 49,0x04},
771 { 50,0x40},
772 { 51,0x1C},
773 { 52,0x1C},
774 { 53,0x04},
775 { 54,0x40},
776 { 55,0x3D},
777 { 56,0x1C},
778 { 57,0x04},
779 { 58,0x60},
780 { 59,0x19},
781 { 60,0x1C},
782 { 61,0x04},
783 { 62,0x60},
784 { 63,0x40},
785 { 64,0x1C},
786 { 65,0x04},
787 { 66,0x80},
788 { 67,0x30},
789 { 68,0x1C},
790 { 69,0x04},
791 { 70,0x80},
792 { 71,0x29},
793 { 72,0x1C},
794 { 73,0x04},
795 { 74,0xA0},
796 { 75,0x15},
797 { 76,0x1C},
798 { 77,0x04},
799 { 78,0xA0},
800 { 79,0x44},
801 { 80,0x1C},
802 { 81,0x04},
803 { 82,0xC0},
804 { 83,0x3B},
805 { 84,0x1C},
806 { 85,0x04},
807 { 86,0xC0},
808 { 87,0x1E},
809 { 88,0x1C},
810 { 89,0x04},
811 { 90,0xE0},
812 { 91,0x34},
813 { 92,0x1C},
814 { 93,0x04},
815 { 94,0xE0},
816 { 95,0x25},
817 { 96,0x1C},
818 { 97,0x05},
819 { 98,0x00},
820 { 99,0x36},
821 {100,0x1C},
822 {101,0x05},
823 {102,0x00},
824 {103,0x23},
825 {104,0x1C},
826 {105,0x05},
827 {106,0x20},
828 {107,0x32},
829 {108,0x1C},
830 {109,0x05},
831 {110,0x20},
832 {111,0x27},
833 {112,0x1C},
834 {113,0x05},
835 {114,0x40},
836 {115,0x13},
837 {116,0x1C},
838 {117,0x05},
839 {118,0x40},
840 {119,0x46},
841 {120,0x1C},
842 {121,0x05},
843 {122,0x60},
844 {123,0x2E},
845 {124,0x1C},
846 {125,0x05},
847 {126,0x60},
848 {127,0x2B},
849 { 0,0x04},
850 { 8,0x1C},
851 { 9,0x05},
852 { 10,0x80},
853 { 11,0x10},
854 { 12,0x1C},
855 { 13,0x05},
856 { 14,0x80},
857 { 15,0x49},
858 { 16,0x1C},
859 { 17,0x05},
860 { 18,0xA0},
861 { 19,0x17},
862 { 20,0x1C},
863 { 21,0x05},
864 { 22,0xA0},
865 { 23,0x42},
866 { 24,0x1C},
867 { 25,0x05},
868 { 26,0xC0},
869 { 27,0x1D},
870 { 28,0x1C},
871 { 29,0x05},
872 { 30,0xC0},
873 { 31,0x3C},
874 { 32,0x1C},
875 { 33,0x05},
876 { 34,0xE0},
877 { 35,0x1B},
878 { 36,0x1C},
879 { 37,0x05},
880 { 38,0xE0},
881 { 39,0x3E},
882 { 40,0x1C},
883 { 41,0x06},
884 { 42,0x00},
885 { 43,0x39},
886 { 44,0x1C},
887 { 45,0x06},
888 { 46,0x00},
889 { 47,0x20},
890 { 48,0x00},
891 { 49,0x00},
892 { 50,0x00},
893 { 51,0x00},
894 { 52,0x5C},
895 { 53,0x90},
896 { 54,0x40},
897 { 55,0x00},
898 { 56,0x00},
899 { 57,0x00},
900 { 58,0x00},
901 { 59,0x00},
902 { 60,0x5C},
903 { 61,0x90},
904 { 62,0x20},
905 { 63,0x00},
906 { 64,0x00},
907 { 65,0x00},
908 { 66,0x00},
909 { 67,0x00},
910 { 68,0x00},
911 { 69,0x00},
912 { 70,0x00},
913 { 71,0x00},
914 { 72,0x00},
915 { 73,0x00},
916 { 74,0x00},
917 { 75,0x00},
918 { 76,0x10},
919 { 77,0x00},
920 { 78,0x00},
921 { 79,0x49},
922 { 80,0x18},
923 { 81,0x00},
924 { 82,0x60},
925 { 83,0x4A},
926 { 84,0x1C},
927 { 85,0x00},
928 { 86,0x80},
929 { 87,0x4C},
930 { 88,0x1C},
931 { 89,0x00},
932 { 90,0x40},
933 { 91,0x49},
934 { 92,0x30},
935 { 93,0x00},
936 { 94,0x00},
937 { 95,0x4C},
938 { 96,0x1C},
939 { 97,0x00},
940 { 98,0x20},
941 { 99,0x4E},
942 {100,0x00},
943 {101,0x00},
944 {102,0x00},
945 {103,0x00},
946 {104,0x10},
947 {105,0x30},
948 {106,0x00},
949 {107,0x4B},
950 {108,0x34},
951 {109,0x00},
952 {110,0x00},
953 {111,0x4B},
954 {112,0x5C},
955 {113,0x60},
956 {114,0xA0},
957 {115,0x4B},
958 {116,0x0C},
959 {117,0x00},
960 {118,0x40},
961 {119,0x00},
962 {120,0x00},
963 {121,0x00},
964 {122,0x00},
965 {123,0x00},
966 {124,0x10},
967 {125,0x30},
968 {126,0x00},
969 {127,0x4D},
970 { 0,0x05},
971 { 8,0x10},
972 { 9,0x13},
973 { 10,0xE0},
974 { 11,0x50},
975 { 12,0x18},
976 { 13,0x01},
977 { 14,0x00},
978 { 15,0x50},
979 { 16,0x18},
980 { 17,0x03},
981 { 18,0x60},
982 { 19,0x53},
983 { 20,0x6C},
984 { 21,0x03},
985 { 22,0x40},
986 { 23,0x52},
987 { 24,0x6C},
988 { 25,0x03},
989 { 26,0x80},
990 { 27,0x55},
991 { 28,0x10},
992 { 29,0x00},
993 { 30,0x20},
994 { 31,0x51},
995 { 32,0x1C},
996 { 33,0x03},
997 { 34,0x20},
998 { 35,0x51},
999 { 36,0x1C},
1000 { 37,0x03},
1001 { 38,0xA0},
1002 { 39,0x56},
1003 { 40,0x00},
1004 { 41,0x00},
1005 { 42,0x00},
1006 { 43,0x00},
1007 { 44,0x00},
1008 { 45,0x00},
1009 { 46,0x00},
1010 { 47,0x00},
1011 { 48,0x00},
1012 { 49,0x00},
1013 { 50,0x00},
1014 { 51,0x00},
1015 { 52,0x10},
1016 { 53,0x00},
1017 { 54,0x00},
1018 { 55,0x54},
1019 { 56,0x18},
1020 { 57,0x01},
1021 { 58,0x00},
1022 { 59,0x54},
1023 { 60,0x00},
1024 { 61,0x00},
1025 { 62,0x00},
1026 { 63,0x00},
1027 { 64,0x0C},
1028 { 65,0x00},
1029 { 66,0x00},
1030 { 67,0x03},
1031 { 68,0x00},
1032 { 69,0x00},
1033 { 70,0x00},
1034 { 71,0x00},
1035 { 72,0x00},
1036 { 73,0x00},
1037 { 74,0x00},
1038 { 75,0x00},
1039 { 76,0x00},
1040 { 77,0x00},
1041 { 78,0x00},
1042 { 79,0x00},
1043 { 80,0x02},
1044 { 81,0x00},
1045 { 82,0x00},
1046 { 83,0x00},
1047 { 84,0x00},
1048 { 85,0x00},
1049 { 86,0x00},
1050 { 87,0x00},
1051};
1052
1053
1054#define main44_miniDSP_A_reg_values_COEFF_START 0
1055#define main44_miniDSP_A_reg_values_COEFF_SIZE 958
1056#define main44_miniDSP_A_reg_values_INST_START 958
1057#define main44_miniDSP_A_reg_values_INST_SIZE 2160
1058
1059reg_value main44_miniDSP_D_reg_values[] = {
1060 { 0,0x0},
1061 { 0x7F,0x50},
1062 { 0,0x01},
1063 { 8,0xFF},
1064 { 9,0xFF},
1065 { 10,0xFF},
1066 { 11,0x00},
1067 { 12,0x80},
1068 { 13,0x00},
1069 { 14,0x00},
1070 { 15,0x00},
1071 { 16,0x7F},
1072 { 17,0xF7},
1073 { 18,0x00},
1074 { 19,0x00},
1075 { 20,0x80},
1076 { 21,0x09},
1077 { 22,0x00},
1078 { 23,0x00},
1079 { 24,0x7F},
1080 { 25,0xEF},
1081 { 26,0x00},
1082 { 27,0x00},
1083 { 28,0x66},
1084 { 29,0x66},
1085 { 30,0x60},
1086 { 31,0x00},
1087 { 32,0x1B},
1088 { 33,0x33},
1089 { 34,0x20},
1090 { 35,0x00},
1091 { 36,0x66},
1092 { 37,0x66},
1093 { 38,0x60},
1094 { 39,0x00},
1095 { 40,0x33},
1096 { 41,0x33},
1097 { 42,0x30},
1098 { 43,0x00},
1099 { 44,0x4C},
1100 { 45,0xCC},
1101 { 46,0xCD},
1102 { 47,0x00},
1103 { 48,0x00},
1104 { 49,0x00},
1105 { 50,0x01},
1106 { 51,0x00},
1107 { 52,0x33},
1108 { 53,0x33},
1109 { 54,0x30},
1110 { 55,0x00},
1111 { 56,0x33},
1112 { 57,0x33},
1113 { 58,0x30},
1114 { 59,0x00},
1115 { 60,0x7F},
1116 { 61,0xFF},
1117 { 62,0xAC},
1118 { 63,0x00},
1119 { 64,0x80},
1120 { 65,0x00},
1121 { 66,0x00},
1122 { 67,0x00},
1123 { 68,0x40},
1124 { 69,0x00},
1125 { 70,0x00},
1126 { 71,0x00},
1127 { 72,0x40},
1128 { 73,0x00},
1129 { 74,0x00},
1130 { 75,0x00},
1131 { 76,0xC0},
1132 { 77,0x00},
1133 { 78,0x00},
1134 { 79,0x00},
1135 { 80,0x50},
1136 { 81,0xC3},
1137 { 82,0x36},
1138 { 83,0x00},
1139 { 84,0x02},
1140 { 85,0x8F},
1141 { 86,0x5C},
1142 { 87,0x00},
1143 { 88,0x02},
1144 { 89,0xD7},
1145 { 90,0x0A},
1146 { 91,0x00},
1147 { 92,0x00},
1148 { 93,0x00},
1149 { 94,0x00},
1150 { 95,0x00},
1151 { 96,0x00},
1152 { 97,0x00},
1153 { 98,0x00},
1154 { 99,0x00},
1155 {100,0x00},
1156 {101,0x00},
1157 {102,0x00},
1158 {103,0x00},
1159 {104,0x00},
1160 {105,0x00},
1161 {106,0x00},
1162 {107,0x00},
1163 {108,0x00},
1164 {109,0x00},
1165 {110,0x00},
1166 {111,0x00},
1167 {112,0x40},
1168 {113,0x00},
1169 {114,0x00},
1170 {115,0x00},
1171 {116,0xFF},
1172 {117,0xFF},
1173 {118,0xFF},
1174 {119,0x00},
1175 {120,0xFF},
1176 {121,0xFF},
1177 {122,0xFE},
1178 {123,0x00},
1179 {124,0xFF},
1180 {125,0xFF},
1181 {126,0xFD},
1182 {127,0x00},
1183 { 0,0x02},
1184 { 8,0xFF},
1185 { 9,0xFF},
1186 { 10,0xFC},
1187 { 11,0x00},
1188 { 12,0x00},
1189 { 13,0x00},
1190 { 14,0x00},
1191 { 15,0x00},
1192 { 16,0x73},
1193 { 17,0x56},
1194 { 18,0x6E},
1195 { 19,0x00},
1196 { 20,0x7F},
1197 { 21,0xF4},
1198 { 22,0xA0},
1199 { 23,0x00},
1200 { 24,0x00},
1201 { 25,0x80},
1202 { 26,0x2D},
1203 { 27,0x00},
1204 { 28,0x7E},
1205 { 29,0xFF},
1206 { 30,0xA5},
1207 { 31,0x00},
1208 { 32,0x00},
1209 { 33,0x2E},
1210 { 34,0x73},
1211 { 35,0x00},
1212 { 36,0xFF},
1213 { 37,0xD1},
1214 { 38,0x8D},
1215 { 39,0x00},
1216 { 40,0x7F},
1217 { 41,0xC1},
1218 { 42,0x2F},
1219 { 43,0x00},
1220 { 44,0x80},
1221 { 45,0x7B},
1222 { 46,0x94},
1223 { 47,0x00},
1224 { 48,0x01},
1225 { 49,0x50},
1226 { 50,0xC1},
1227 { 51,0x00},
1228 { 52,0xFE},
1229 { 53,0xAF},
1230 { 54,0x3F},
1231 { 55,0x00},
1232 { 56,0x7F},
1233 { 57,0x55},
1234 { 58,0xC1},
1235 { 59,0x00},
1236 { 60,0x81},
1237 { 61,0x4E},
1238 { 62,0x4E},
1239 { 63,0x00},
1240 { 64,0x7F},
1241 { 65,0xFF},
1242 { 66,0xFF},
1243 { 67,0x00},
1244 { 68,0x00},
1245 { 69,0x00},
1246 { 70,0x00},
1247 { 71,0x00},
1248 { 72,0xC7},
1249 { 73,0x2E},
1250 { 74,0x8D},
1251 { 75,0x00},
1252 { 76,0x31},
1253 { 77,0x91},
1254 { 78,0x54},
1255 { 79,0x00},
1256 { 80,0xD1},
1257 { 81,0xFC},
1258 { 82,0xF4},
1259 { 83,0x00},
1260 { 84,0x2A},
1261 { 85,0x09},
1262 { 86,0x1A},
1263 { 87,0x00},
1264 { 88,0xEA},
1265 { 89,0xD6},
1266 { 90,0x1C},
1267 { 91,0x00},
1268 { 92,0xC5},
1269 { 93,0x28},
1270 { 94,0xA2},
1271 { 95,0x00},
1272 { 96,0x32},
1273 { 97,0xD7},
1274 { 98,0x53},
1275 { 99,0x00},
1276 {100,0xD3},
1277 {101,0x74},
1278 {102,0x4B},
1279 {103,0x00},
1280 {104,0x15},
1281 {105,0x04},
1282 {106,0x8D},
1283 {107,0x00},
1284 {108,0xF5},
1285 {109,0x6B},
1286 {110,0x0E},
1287 {111,0x00},
1288 {112,0xC0},
1289 {113,0x0C},
1290 {114,0x47},
1291 {115,0x00},
1292 {116,0x3F},
1293 {117,0x99},
1294 {118,0x61},
1295 {119,0x00},
1296 {120,0x3E},
1297 {121,0xE2},
1298 {122,0x1D},
1299 {123,0x00},
1300 {124,0x3E},
1301 {125,0xE2},
1302 {126,0x1D},
1303 {127,0x00},
1304 { 0,0x03},
1305 { 8,0x0A},
1306 { 9,0x57},
1307 { 10,0x0D},
1308 { 11,0x00},
1309 { 12,0xF5},
1310 { 13,0xA8},
1311 { 14,0xF3},
1312 { 15,0x00},
1313 { 16,0x6E},
1314 { 17,0x1B},
1315 { 18,0xC0},
1316 { 19,0x00},
1317 { 20,0x89},
1318 { 21,0x90},
1319 { 22,0x65},
1320 { 23,0x00},
1321 { 24,0x1B},
1322 { 25,0x6E},
1323 { 26,0xFE},
1324 { 27,0x00},
1325 { 28,0xE4},
1326 { 29,0x91},
1327 { 30,0x02},
1328 { 31,0x00},
1329 { 32,0x5B},
1330 { 33,0x45},
1331 { 34,0x9C},
1332 { 35,0x00},
1333 { 36,0x99},
1334 { 37,0x5F},
1335 { 38,0xEC},
1336 { 39,0x00},
1337 { 40,0x15},
1338 { 41,0x3D},
1339 { 42,0xC9},
1340 { 43,0x00},
1341 { 44,0xEA},
1342 { 45,0xC2},
1343 { 46,0x37},
1344 { 47,0x00},
1345 { 48,0x40},
1346 { 49,0x53},
1347 { 50,0x16},
1348 { 51,0x00},
1349 { 52,0x93},
1350 { 53,0xA5},
1351 { 54,0xAE},
1352 { 55,0x00},
1353 { 56,0x9B},
1354 { 57,0x77},
1355 { 58,0x00},
1356 { 59,0x00},
1357 { 60,0x64},
1358 { 61,0x88},
1359 { 62,0xF0},
1360 { 63,0x00},
1361 { 64,0x45},
1362 { 65,0x84},
1363 { 66,0x40},
1364 { 67,0x00},
1365 { 68,0xBA},
1366 { 69,0x7B},
1367 { 70,0xB0},
1368 { 71,0x00},
1369 { 72,0xC3},
1370 { 73,0xE0},
1371 { 74,0x00},
1372 { 75,0x00},
1373 { 76,0x3C},
1374 { 77,0x1F},
1375 { 78,0xF0},
1376 { 79,0x00},
1377 { 80,0x68},
1378 { 81,0x76},
1379 { 82,0x1D},
1380 { 83,0x00},
1381 { 84,0x97},
1382 { 85,0x89},
1383 { 86,0xE3},
1384 { 87,0x00},
1385 { 88,0x67},
1386 { 89,0xEA},
1387 { 90,0x3A},
1388 { 91,0x00},
1389 { 92,0xAD},
1390 { 93,0xFC},
1391 { 94,0x02},
1392 { 95,0x00},
1393 { 96,0x79},
1394 { 97,0xEC},
1395 { 98,0x4D},
1396 { 99,0x00},
1397 {100,0x86},
1398 {101,0x13},
1399 {102,0xB3},
1400 {103,0x00},
1401 {104,0x3A},
1402 {105,0x36},
1403 {106,0x6A},
1404 {107,0x00},
1405 {108,0x7F},
1406 {109,0xFF},
1407 {110,0xFF},
1408 {111,0x00},
1409 {112,0x00},
1410 {113,0x00},
1411 {114,0x00},
1412 {115,0x00},
1413 {116,0x00},
1414 {117,0x00},
1415 {118,0x00},
1416 {119,0x00},
1417 {120,0x00},
1418 {121,0x00},
1419 {122,0x00},
1420 {123,0x00},
1421 {124,0x00},
1422 {125,0x00},
1423 {126,0x00},
1424 {127,0x00},
1425 { 0,0x04},
1426 { 8,0x7F},
1427 { 9,0xFF},
1428 { 10,0xFF},
1429 { 11,0x00},
1430 { 12,0x00},
1431 { 13,0x00},
1432 { 14,0x00},
1433 { 15,0x00},
1434 { 16,0x00},
1435 { 17,0x00},
1436 { 18,0x00},
1437 { 19,0x00},
1438 { 20,0x00},
1439 { 21,0x00},
1440 { 22,0x00},
1441 { 23,0x00},
1442 { 24,0x00},
1443 { 25,0x00},
1444 { 26,0x00},
1445 { 27,0x00},
1446 { 28,0x00},
1447 { 29,0x00},
1448 { 30,0x01},
1449 { 31,0x00},
1450 { 32,0xC0},
1451 { 33,0x00},
1452 { 34,0x00},
1453 { 35,0x00},
1454 { 36,0x00},
1455 { 37,0x00},
1456 { 38,0x01},
1457 { 39,0x00},
1458 { 40,0x00},
1459 { 41,0x00},
1460 { 42,0xAF},
1461 { 43,0x00},
1462 { 44,0x7F},
1463 { 45,0xFF},
1464 { 46,0x51},
1465 { 47,0x00},
1466 { 48,0x00},
1467 { 49,0x00},
1468 { 50,0x00},
1469 { 51,0x00},
1470 { 52,0xF0},
1471 { 53,0x00},
1472 { 54,0x00},
1473 { 55,0x00},
1474 { 56,0xE4},
1475 { 57,0x00},
1476 { 58,0x00},
1477 { 59,0x00},
1478 { 60,0x32},
1479 { 61,0x00},
1480 { 62,0x00},
1481 { 63,0x00},
1482 { 64,0x14},
1483 { 65,0x00},
1484 { 66,0x00},
1485 { 67,0x00},
1486 { 68,0xFF},
1487 { 69,0x00},
1488 { 70,0x00},
1489 { 71,0x00},
1490 { 72,0xF0},
1491 { 73,0x00},
1492 { 74,0x00},
1493 { 75,0x00},
1494 { 76,0x00},
1495 { 77,0x02},
1496 { 78,0xBB},
1497 { 79,0x00},
1498 { 80,0x7F},
1499 { 81,0xFD},
1500 { 82,0x45},
1501 { 83,0x00},
1502 { 84,0x00},
1503 { 85,0x00},
1504 { 86,0x57},
1505 { 87,0x00},
1506 { 88,0x7F},
1507 { 89,0xFF},
1508 { 90,0xA9},
1509 { 91,0x00},
1510 { 92,0x20},
1511 { 93,0x00},
1512 { 94,0x00},
1513 { 95,0x00},
1514 { 96,0x00},
1515 { 97,0x00},
1516 { 98,0x00},
1517 { 99,0x00},
1518 {100,0xD7},
1519 {101,0x41},
1520 {102,0xA0},
1521 {103,0x00},
1522 {104,0xFF},
1523 {105,0xF0},
1524 {106,0x00},
1525 {107,0x00},
1526 {108,0x88},
1527 {109,0x00},
1528 {110,0x00},
1529 {111,0x00},
1530 {112,0x18},
1531 {113,0x00},
1532 {114,0x00},
1533 {115,0x00},
1534 {116,0x00},
1535 {117,0x00},
1536 {118,0x00},
1537 {119,0x00},
1538 {120,0x0C},
1539 {121,0x00},
1540 {122,0x00},
1541 {123,0x00},
1542 {124,0xF4},
1543 {125,0x00},
1544 {126,0x00},
1545 {127,0x00},
1546 { 0,0x05},
1547 { 8,0x15},
1548 { 9,0x42},
1549 { 10,0xA6},
1550 { 11,0x00},
1551 { 12,0x7F},
1552 { 13,0xFF},
1553 { 14,0xFF},
1554 { 15,0x00},
1555 { 16,0x0B},
1556 { 17,0xF9},
1557 { 18,0x13},
1558 { 19,0x00},
1559 { 20,0x18},
1560 { 21,0xEC},
1561 { 22,0xF7},
1562 { 23,0x00},
1563 { 24,0x5B},
1564 { 25,0x9E},
1565 { 26,0xC4},
1566 { 27,0x00},
1567 { 28,0x7F},
1568 { 29,0x7B},
1569 { 30,0x30},
1570 { 31,0x00},
1571 { 32,0x00},
1572 { 33,0x00},
1573 { 34,0x00},
1574 { 35,0x00},
1575 { 36,0x00},
1576 { 37,0x00},
1577 { 38,0x00},
1578 { 39,0x00},
1579 { 40,0x00},
1580 { 41,0x00},
1581 { 42,0x00},
1582 { 43,0x00},
1583 { 44,0x00},
1584 { 45,0x0D},
1585 { 46,0x00},
1586 { 47,0x00},
1587 { 48,0x00},
1588 { 49,0x1C},
1589 { 50,0x00},
1590 { 51,0x00},
1591 { 52,0x00},
1592 { 53,0x3E},
1593 { 54,0x00},
1594 { 55,0x00},
1595 { 56,0x00},
1596 { 57,0x78},
1597 { 58,0x00},
1598 { 59,0x00},
1599 { 60,0x02},
1600 { 61,0x4C},
1601 { 62,0x00},
1602 { 63,0x00},
1603 { 64,0x00},
1604 { 65,0xD5},
1605 { 66,0x00},
1606 { 67,0x00},
1607 { 68,0x01},
1608 { 69,0x65},
1609 { 70,0x00},
1610 { 71,0x00},
1611 { 72,0x03},
1612 { 73,0xE9},
1613 { 74,0x00},
1614 { 75,0x00},
1615 { 76,0x07},
1616 { 77,0xCA},
1617 { 78,0x00},
1618 { 79,0x00},
1619 { 80,0xFF},
1620 { 81,0xEF},
1621 { 82,0x00},
1622 { 83,0x00},
1623 { 84,0xFE},
1624 { 85,0xEB},
1625 { 86,0x00},
1626 { 87,0x00},
1627 { 88,0xFF},
1628 { 89,0xA8},
1629 { 90,0x00},
1630 { 91,0x00},
1631 { 92,0xFD},
1632 { 93,0x08},
1633 { 94,0x00},
1634 { 95,0x00},
1635 { 96,0xFF},
1636 { 97,0x5E},
1637 { 98,0x00},
1638 { 99,0x00},
1639 {100,0xFF},
1640 {101,0xD5},
1641 {102,0x00},
1642 {103,0x00},
1643 {104,0xFE},
1644 {105,0x36},
1645 {106,0x00},
1646 {107,0x00},
1647 {108,0xFA},
1648 {109,0xAC},
1649 {110,0x00},
1650 {111,0x00},
1651 {112,0xF2},
1652 {113,0xA3},
1653 {114,0x00},
1654 {115,0x00},
1655 {116,0x28},
1656 {117,0xAB},
1657 {118,0x00},
1658 {119,0x00},
1659 {120,0x3F},
1660 {121,0xFF},
1661 {122,0x00},
1662 {123,0x00},
1663 {124,0xFF},
1664 {125,0x98},
1665 {126,0x00},
1666 {127,0x00},
1667 { 0,0x06},
1668 { 8,0xF6},
1669 { 9,0xF9},
1670 { 10,0x00},
1671 { 11,0x00},
1672 { 12,0x26},
1673 { 13,0xFB},
1674 { 14,0x00},
1675 { 15,0x00},
1676 { 16,0x02},
1677 { 17,0x72},
1678 { 18,0x00},
1679 { 19,0x00},
1680 { 20,0x40},
1681 { 21,0x02},
1682 { 22,0x00},
1683 { 23,0x00},
1684 { 24,0xFB},
1685 { 25,0xCB},
1686 { 26,0x00},
1687 { 27,0x00},
1688 { 28,0x20},
1689 { 29,0xA7},
1690 { 30,0x00},
1691 { 31,0x00},
1692 { 32,0xFF},
1693 { 33,0x6A},
1694 { 34,0x00},
1695 { 35,0x00},
1696 { 36,0x3A},
1697 { 37,0x0F},
1698 { 38,0x00},
1699 { 39,0x00},
1700 { 0,0x09},
1701 { 72,0xFF},
1702 { 73,0xFF},
1703 { 74,0xFF},
1704 { 75,0x00},
1705 { 76,0x80},
1706 { 77,0x00},
1707 { 78,0x00},
1708 { 79,0x00},
1709 { 80,0x7F},
1710 { 81,0xF7},
1711 { 82,0x00},
1712 { 83,0x00},
1713 { 84,0x80},
1714 { 85,0x09},
1715 { 86,0x00},
1716 { 87,0x00},
1717 { 88,0x7F},
1718 { 89,0xEF},
1719 { 90,0x00},
1720 { 91,0x00},
1721 { 92,0x66},
1722 { 93,0x66},
1723 { 94,0x60},
1724 { 95,0x00},
1725 { 96,0x1B},
1726 { 97,0x33},
1727 { 98,0x20},
1728 { 99,0x00},
1729 {100,0x66},
1730 {101,0x66},
1731 {102,0x60},
1732 {103,0x00},
1733 {104,0x33},
1734 {105,0x33},
1735 {106,0x30},
1736 {107,0x00},
1737 {108,0x4C},
1738 {109,0xCC},
1739 {110,0xCD},
1740 {111,0x00},
1741 {112,0x00},
1742 {113,0x00},
1743 {114,0x01},
1744 {115,0x00},
1745 {116,0x33},
1746 {117,0x33},
1747 {118,0x30},
1748 {119,0x00},
1749 {120,0x33},
1750 {121,0x33},
1751 {122,0x30},
1752 {123,0x00},
1753 {124,0x7F},
1754 {125,0xFF},
1755 {126,0xAC},
1756 {127,0x00},
1757 { 0,0x0A},
1758 { 8,0x80},
1759 { 9,0x00},
1760 { 10,0x00},
1761 { 11,0x00},
1762 { 12,0x40},
1763 { 13,0x00},
1764 { 14,0x00},
1765 { 15,0x00},
1766 { 16,0x40},
1767 { 17,0x00},
1768 { 18,0x00},
1769 { 19,0x00},
1770 { 20,0xC0},
1771 { 21,0x00},
1772 { 22,0x00},
1773 { 23,0x00},
1774 { 24,0x50},
1775 { 25,0xC3},
1776 { 26,0x36},
1777 { 27,0x00},
1778 { 28,0x02},
1779 { 29,0x8F},
1780 { 30,0x5C},
1781 { 31,0x00},
1782 { 32,0x02},
1783 { 33,0xD7},
1784 { 34,0x0A},
1785 { 35,0x00},
1786 { 36,0x00},
1787 { 37,0x00},
1788 { 38,0x00},
1789 { 39,0x00},
1790 { 40,0x00},
1791 { 41,0x00},
1792 { 42,0x00},
1793 { 43,0x00},
1794 { 44,0x00},
1795 { 45,0x00},
1796 { 46,0x00},
1797 { 47,0x00},
1798 { 48,0x00},
1799 { 49,0x00},
1800 { 50,0x00},
1801 { 51,0x00},
1802 { 52,0x00},
1803 { 53,0x00},
1804 { 54,0x00},
1805 { 55,0x00},
1806 { 56,0x40},
1807 { 57,0x00},
1808 { 58,0x00},
1809 { 59,0x00},
1810 { 60,0xFF},
1811 { 61,0xFF},
1812 { 62,0xFF},
1813 { 63,0x00},
1814 { 64,0xFF},
1815 { 65,0xFF},
1816 { 66,0xFE},
1817 { 67,0x00},
1818 { 68,0xFF},
1819 { 69,0xFF},
1820 { 70,0xFD},
1821 { 71,0x00},
1822 { 72,0xFF},
1823 { 73,0xFF},
1824 { 74,0xFC},
1825 { 75,0x00},
1826 { 76,0x00},
1827 { 77,0x00},
1828 { 78,0x00},
1829 { 79,0x00},
1830 { 80,0x73},
1831 { 81,0x56},
1832 { 82,0x6E},
1833 { 83,0x00},
1834 { 84,0x7F},
1835 { 85,0xF4},
1836 { 86,0xA0},
1837 { 87,0x00},
1838 { 88,0x00},
1839 { 89,0x80},
1840 { 90,0x2D},
1841 { 91,0x00},
1842 { 92,0x7E},
1843 { 93,0xFF},
1844 { 94,0xA5},
1845 { 95,0x00},
1846 { 96,0x00},
1847 { 97,0x2E},
1848 { 98,0x73},
1849 { 99,0x00},
1850 {100,0xFF},
1851 {101,0xD1},
1852 {102,0x8D},
1853 {103,0x00},
1854 {104,0x7F},
1855 {105,0xC1},
1856 {106,0x2F},
1857 {107,0x00},
1858 {108,0x80},
1859 {109,0x7B},
1860 {110,0x94},
1861 {111,0x00},
1862 {112,0x01},
1863 {113,0x50},
1864 {114,0xC1},
1865 {115,0x00},
1866 {116,0xFE},
1867 {117,0xAF},
1868 {118,0x3F},
1869 {119,0x00},
1870 {120,0x7F},
1871 {121,0x55},
1872 {122,0xC1},
1873 {123,0x00},
1874 {124,0x81},
1875 {125,0x4E},
1876 {126,0x4E},
1877 {127,0x00},
1878 { 0,0x0B},
1879 { 8,0x7F},
1880 { 9,0xFF},
1881 { 10,0xFF},
1882 { 11,0x00},
1883 { 12,0x00},
1884 { 13,0x00},
1885 { 14,0x00},
1886 { 15,0x00},
1887 { 16,0xC7},
1888 { 17,0x2E},
1889 { 18,0x8D},
1890 { 19,0x00},
1891 { 20,0x31},
1892 { 21,0x91},
1893 { 22,0x54},
1894 { 23,0x00},
1895 { 24,0xD1},
1896 { 25,0xFC},
1897 { 26,0xF4},
1898 { 27,0x00},
1899 { 28,0x2A},
1900 { 29,0x09},
1901 { 30,0x1A},
1902 { 31,0x00},
1903 { 32,0xEA},
1904 { 33,0xD6},
1905 { 34,0x1C},
1906 { 35,0x00},
1907 { 36,0xC5},
1908 { 37,0x28},
1909 { 38,0xA2},
1910 { 39,0x00},
1911 { 40,0x32},
1912 { 41,0xD7},
1913 { 42,0x53},
1914 { 43,0x00},
1915 { 44,0xD3},
1916 { 45,0x74},
1917 { 46,0x4B},
1918 { 47,0x00},
1919 { 48,0x15},
1920 { 49,0x04},
1921 { 50,0x8D},
1922 { 51,0x00},
1923 { 52,0xF5},
1924 { 53,0x6B},
1925 { 54,0x0E},
1926 { 55,0x00},
1927 { 56,0xC0},
1928 { 57,0x0C},
1929 { 58,0x47},
1930 { 59,0x00},
1931 { 60,0x3F},
1932 { 61,0x99},
1933 { 62,0x61},
1934 { 63,0x00},
1935 { 64,0x3E},
1936 { 65,0xE2},
1937 { 66,0x1D},
1938 { 67,0x00},
1939 { 68,0x3E},
1940 { 69,0xE2},
1941 { 70,0x1D},
1942 { 71,0x00},
1943 { 72,0x0A},
1944 { 73,0x57},
1945 { 74,0x0D},
1946 { 75,0x00},
1947 { 76,0xF5},
1948 { 77,0xA8},
1949 { 78,0xF3},
1950 { 79,0x00},
1951 { 80,0x6E},
1952 { 81,0x1B},
1953 { 82,0xC0},
1954 { 83,0x00},
1955 { 84,0x89},
1956 { 85,0x90},
1957 { 86,0x65},
1958 { 87,0x00},
1959 { 88,0x1B},
1960 { 89,0x6E},
1961 { 90,0xFE},
1962 { 91,0x00},
1963 { 92,0xE4},
1964 { 93,0x91},
1965 { 94,0x02},
1966 { 95,0x00},
1967 { 96,0x5B},
1968 { 97,0x45},
1969 { 98,0x9C},
1970 { 99,0x00},
1971 {100,0x99},
1972 {101,0x5F},
1973 {102,0xEC},
1974 {103,0x00},
1975 {104,0x15},
1976 {105,0x3D},
1977 {106,0xC9},
1978 {107,0x00},
1979 {108,0xEA},
1980 {109,0xC2},
1981 {110,0x37},
1982 {111,0x00},
1983 {112,0x40},
1984 {113,0x53},
1985 {114,0x16},
1986 {115,0x00},
1987 {116,0x93},
1988 {117,0xA5},
1989 {118,0xAE},
1990 {119,0x00},
1991 {120,0x9B},
1992 {121,0x77},
1993 {122,0x00},
1994 {123,0x00},
1995 {124,0x64},
1996 {125,0x88},
1997 {126,0xF0},
1998 {127,0x00},
1999 { 0,0x0C},
2000 { 8,0x45},
2001 { 9,0x84},
2002 { 10,0x40},
2003 { 11,0x00},
2004 { 12,0xBA},
2005 { 13,0x7B},
2006 { 14,0xB0},
2007 { 15,0x00},
2008 { 16,0xC3},
2009 { 17,0xE0},
2010 { 18,0x00},
2011 { 19,0x00},
2012 { 20,0x3C},
2013 { 21,0x1F},
2014 { 22,0xF0},
2015 { 23,0x00},
2016 { 24,0x68},
2017 { 25,0x76},
2018 { 26,0x1D},
2019 { 27,0x00},
2020 { 28,0x97},
2021 { 29,0x89},
2022 { 30,0xE3},
2023 { 31,0x00},
2024 { 32,0x67},
2025 { 33,0xEA},
2026 { 34,0x3A},
2027 { 35,0x00},
2028 { 36,0xAD},
2029 { 37,0xFC},
2030 { 38,0x02},
2031 { 39,0x00},
2032 { 40,0x79},
2033 { 41,0xEC},
2034 { 42,0x4D},
2035 { 43,0x00},
2036 { 44,0x86},
2037 { 45,0x13},
2038 { 46,0xB3},
2039 { 47,0x00},
2040 { 48,0x3A},
2041 { 49,0x36},
2042 { 50,0x6A},
2043 { 51,0x00},
2044 { 52,0x7F},
2045 { 53,0xFF},
2046 { 54,0xFF},
2047 { 55,0x00},
2048 { 56,0x00},
2049 { 57,0x00},
2050 { 58,0x00},
2051 { 59,0x00},
2052 { 60,0x00},
2053 { 61,0x00},
2054 { 62,0x00},
2055 { 63,0x00},
2056 { 64,0x00},
2057 { 65,0x00},
2058 { 66,0x00},
2059 { 67,0x00},
2060 { 68,0x00},
2061 { 69,0x00},
2062 { 70,0x00},
2063 { 71,0x00},
2064 { 72,0x7F},
2065 { 73,0xFF},
2066 { 74,0xFF},
2067 { 75,0x00},
2068 { 76,0x00},
2069 { 77,0x00},
2070 { 78,0x00},
2071 { 79,0x00},
2072 { 80,0x00},
2073 { 81,0x00},
2074 { 82,0x00},
2075 { 83,0x00},
2076 { 84,0x00},
2077 { 85,0x00},
2078 { 86,0x00},
2079 { 87,0x00},
2080 { 88,0x00},
2081 { 89,0x00},
2082 { 90,0x00},
2083 { 91,0x00},
2084 { 92,0x00},
2085 { 93,0x00},
2086 { 94,0x01},
2087 { 95,0x00},
2088 { 96,0xC0},
2089 { 97,0x00},
2090 { 98,0x00},
2091 { 99,0x00},
2092 {100,0x00},
2093 {101,0x00},
2094 {102,0x01},
2095 {103,0x00},
2096 {104,0x00},
2097 {105,0x00},
2098 {106,0xAF},
2099 {107,0x00},
2100 {108,0x7F},
2101 {109,0xFF},
2102 {110,0x51},
2103 {111,0x00},
2104 {112,0x00},
2105 {113,0x00},
2106 {114,0x00},
2107 {115,0x00},
2108 {116,0xF0},
2109 {117,0x00},
2110 {118,0x00},
2111 {119,0x00},
2112 {120,0xE4},
2113 {121,0x00},
2114 {122,0x00},
2115 {123,0x00},
2116 {124,0x32},
2117 {125,0x00},
2118 {126,0x00},
2119 {127,0x00},
2120 { 0,0x0D},
2121 { 8,0x14},
2122 { 9,0x00},
2123 { 10,0x00},
2124 { 11,0x00},
2125 { 12,0xFF},
2126 { 13,0x00},
2127 { 14,0x00},
2128 { 15,0x00},
2129 { 16,0xF0},
2130 { 17,0x00},
2131 { 18,0x00},
2132 { 19,0x00},
2133 { 20,0x00},
2134 { 21,0x02},
2135 { 22,0xBB},
2136 { 23,0x00},
2137 { 24,0x7F},
2138 { 25,0xFD},
2139 { 26,0x45},
2140 { 27,0x00},
2141 { 28,0x00},
2142 { 29,0x00},
2143 { 30,0x57},
2144 { 31,0x00},
2145 { 32,0x7F},
2146 { 33,0xFF},
2147 { 34,0xA9},
2148 { 35,0x00},
2149 { 36,0x20},
2150 { 37,0x00},
2151 { 38,0x00},
2152 { 39,0x00},
2153 { 40,0x00},
2154 { 41,0x00},
2155 { 42,0x00},
2156 { 43,0x00},
2157 { 44,0xD7},
2158 { 45,0x41},
2159 { 46,0xA0},
2160 { 47,0x00},
2161 { 48,0xFF},
2162 { 49,0xF0},
2163 { 50,0x00},
2164 { 51,0x00},
2165 { 52,0x88},
2166 { 53,0x00},
2167 { 54,0x00},
2168 { 55,0x00},
2169 { 56,0x18},
2170 { 57,0x00},
2171 { 58,0x00},
2172 { 59,0x00},
2173 { 60,0x00},
2174 { 61,0x00},
2175 { 62,0x00},
2176 { 63,0x00},
2177 { 64,0x0C},
2178 { 65,0x00},
2179 { 66,0x00},
2180 { 67,0x00},
2181 { 68,0xF4},
2182 { 69,0x00},
2183 { 70,0x00},
2184 { 71,0x00},
2185 { 72,0x15},
2186 { 73,0x42},
2187 { 74,0xA6},
2188 { 75,0x00},
2189 { 76,0x7F},
2190 { 77,0xFF},
2191 { 78,0xFF},
2192 { 79,0x00},
2193 { 80,0x0B},
2194 { 81,0xF9},
2195 { 82,0x13},
2196 { 83,0x00},
2197 { 84,0x18},
2198 { 85,0xEC},
2199 { 86,0xF7},
2200 { 87,0x00},
2201 { 88,0x5B},
2202 { 89,0x9E},
2203 { 90,0xC4},
2204 { 91,0x00},
2205 { 92,0x7F},
2206 { 93,0x7B},
2207 { 94,0x30},
2208 { 95,0x00},
2209 { 96,0x00},
2210 { 97,0x00},
2211 { 98,0x00},
2212 { 99,0x00},
2213 {100,0x00},
2214 {101,0x00},
2215 {102,0x00},
2216 {103,0x00},
2217 {104,0x00},
2218 {105,0x00},
2219 {106,0x00},
2220 {107,0x00},
2221 {108,0x00},
2222 {109,0x0D},
2223 {110,0x00},
2224 {111,0x00},
2225 {112,0x00},
2226 {113,0x1C},
2227 {114,0x00},
2228 {115,0x00},
2229 {116,0x00},
2230 {117,0x3E},
2231 {118,0x00},
2232 {119,0x00},
2233 {120,0x00},
2234 {121,0x78},
2235 {122,0x00},
2236 {123,0x00},
2237 {124,0x02},
2238 {125,0x4C},
2239 {126,0x00},
2240 {127,0x00},
2241 { 0,0x0E},
2242 { 8,0x00},
2243 { 9,0xD5},
2244 { 10,0x00},
2245 { 11,0x00},
2246 { 12,0x01},
2247 { 13,0x65},
2248 { 14,0x00},
2249 { 15,0x00},
2250 { 16,0x03},
2251 { 17,0xE9},
2252 { 18,0x00},
2253 { 19,0x00},
2254 { 20,0x07},
2255 { 21,0xCA},
2256 { 22,0x00},
2257 { 23,0x00},
2258 { 24,0xFF},
2259 { 25,0xEF},
2260 { 26,0x00},
2261 { 27,0x00},
2262 { 28,0xFE},
2263 { 29,0xEB},
2264 { 30,0x00},
2265 { 31,0x00},
2266 { 32,0xFF},
2267 { 33,0xA8},
2268 { 34,0x00},
2269 { 35,0x00},
2270 { 36,0xFD},
2271 { 37,0x08},
2272 { 38,0x00},
2273 { 39,0x00},
2274 { 40,0xFF},
2275 { 41,0x5E},
2276 { 42,0x00},
2277 { 43,0x00},
2278 { 44,0xFF},
2279 { 45,0xD5},
2280 { 46,0x00},
2281 { 47,0x00},
2282 { 48,0xFE},
2283 { 49,0x36},
2284 { 50,0x00},
2285 { 51,0x00},
2286 { 52,0xFA},
2287 { 53,0xAC},
2288 { 54,0x00},
2289 { 55,0x00},
2290 { 56,0xF2},
2291 { 57,0xA3},
2292 { 58,0x00},
2293 { 59,0x00},
2294 { 60,0x28},
2295 { 61,0xAB},
2296 { 62,0x00},
2297 { 63,0x00},
2298 { 64,0x3F},
2299 { 65,0xFF},
2300 { 66,0x00},
2301 { 67,0x00},
2302 { 68,0xFF},
2303 { 69,0x98},
2304 { 70,0x00},
2305 { 71,0x00},
2306 { 72,0xF6},
2307 { 73,0xF9},
2308 { 74,0x00},
2309 { 75,0x00},
2310 { 76,0x26},
2311 { 77,0xFB},
2312 { 78,0x00},
2313 { 79,0x00},
2314 { 80,0x02},
2315 { 81,0x72},
2316 { 82,0x00},
2317 { 83,0x00},
2318 { 84,0x40},
2319 { 85,0x02},
2320 { 86,0x00},
2321 { 87,0x00},
2322 { 88,0xFB},
2323 { 89,0xCB},
2324 { 90,0x00},
2325 { 91,0x00},
2326 { 92,0x20},
2327 { 93,0xA7},
2328 { 94,0x00},
2329 { 95,0x00},
2330 { 96,0xFF},
2331 { 97,0x6A},
2332 { 98,0x00},
2333 { 99,0x00},
2334 {100,0x3A},
2335 {101,0x0F},
2336 {102,0x00},
2337 {103,0x00},
2338 { 0,0x0},
2339 { 0x7F,0x3C},
2340 { 0,0x01},
2341 { 8,0xC0},
2342 { 9,0x00},
2343 { 10,0x00},
2344 { 11,0x00},
2345 { 12,0xC0},
2346 { 13,0x00},
2347 { 14,0x00},
2348 { 15,0x00},
2349 { 0,0x0},
2350 { 0x7F,0x78},
2351 { 0,0x01},
2352 { 8,0x04},
2353 { 9,0x00},
2354 { 10,0x00},
2355 { 11,0x00},
2356 { 12,0x04},
2357 { 13,0x00},
2358 { 14,0x20},
2359 { 15,0x01},
2360 { 16,0x58},
2361 { 17,0x60},
2362 { 18,0x08},
2363 { 19,0x01},
2364 { 20,0x60},
2365 { 21,0x60},
2366 { 22,0x00},
2367 { 23,0x00},
2368 { 24,0x58},
2369 { 25,0x60},
2370 { 26,0x00},
2371 { 27,0x2D},
2372 { 28,0x00},
2373 { 29,0x00},
2374 { 30,0x00},
2375 { 31,0x00},
2376 { 32,0x44},
2377 { 33,0x00},
2378 { 34,0xC0},
2379 { 35,0x16},
2380 { 36,0x08},
2381 { 37,0x00},
2382 { 38,0x00},
2383 { 39,0xBE},
2384 { 40,0x08},
2385 { 41,0x00},
2386 { 42,0x20},
2387 { 43,0xFE},
2388 { 44,0x08},
2389 { 45,0x00},
2390 { 46,0x00},
2391 { 47,0xBD},
2392 { 48,0x08},
2393 { 49,0x00},
2394 { 50,0x20},
2395 { 51,0xFD},
2396 { 52,0x08},
2397 { 53,0x00},
2398 { 54,0x00},
2399 { 55,0xBC},
2400 { 56,0x08},
2401 { 57,0x00},
2402 { 58,0x20},
2403 { 59,0xFC},
2404 { 60,0x08},
2405 { 61,0x00},
2406 { 62,0x00},
2407 { 63,0xBB},
2408 { 64,0x08},
2409 { 65,0x00},
2410 { 66,0x20},
2411 { 67,0xFB},
2412 { 68,0x08},
2413 { 69,0x00},
2414 { 70,0x00},
2415 { 71,0xBA},
2416 { 72,0x08},
2417 { 73,0x00},
2418 { 74,0x20},
2419 { 75,0xFA},
2420 { 76,0x08},
2421 { 77,0x00},
2422 { 78,0x00},
2423 { 79,0xB9},
2424 { 80,0x08},
2425 { 81,0x00},
2426 { 82,0x20},
2427 { 83,0xF9},
2428 { 84,0x08},
2429 { 85,0x00},
2430 { 86,0x00},
2431 { 87,0xB8},
2432 { 88,0x08},
2433 { 89,0x00},
2434 { 90,0x20},
2435 { 91,0xF8},
2436 { 92,0x08},
2437 { 93,0x00},
2438 { 94,0x00},
2439 { 95,0xB7},
2440 { 96,0x08},
2441 { 97,0x00},
2442 { 98,0x20},
2443 { 99,0xF7},
2444 {100,0x00},
2445 {101,0x00},
2446 {102,0x00},
2447 {103,0x00},
2448 {104,0x00},
2449 {105,0x00},
2450 {106,0x00},
2451 {107,0x00},
2452 {108,0x00},
2453 {109,0x00},
2454 {110,0x00},
2455 {111,0x00},
2456 {112,0x00},
2457 {113,0x00},
2458 {114,0x00},
2459 {115,0x00},
2460 {116,0x00},
2461 {117,0x00},
2462 {118,0x00},
2463 {119,0x00},
2464 {120,0x44},
2465 {121,0x00},
2466 {122,0x00},
2467 {123,0x06},
2468 {124,0x21},
2469 {125,0x00},
2470 {126,0x20},
2471 {127,0x00},
2472 { 0,0x02},
2473 { 8,0x4B},
2474 { 9,0x00},
2475 { 10,0xC0},
2476 { 11,0x00},
2477 { 12,0x4B},
2478 { 13,0x00},
2479 { 14,0xE0},
2480 { 15,0x00},
2481 { 16,0x00},
2482 { 17,0x00},
2483 { 18,0x40},
2484 { 19,0x48},
2485 { 20,0x0C},
2486 { 21,0x00},
2487 { 22,0x00},
2488 { 23,0x00},
2489 { 24,0x0C},
2490 { 25,0x00},
2491 { 26,0x20},
2492 { 27,0x00},
2493 { 28,0x18},
2494 { 29,0x01},
2495 { 30,0xA0},
2496 { 31,0x00},
2497 { 32,0x18},
2498 { 33,0x01},
2499 { 34,0xA0},
2500 { 35,0x01},
2501 { 36,0x00},
2502 { 37,0x00},
2503 { 38,0x00},
2504 { 39,0x00},
2505 { 40,0x00},
2506 { 41,0x00},
2507 { 42,0x00},
2508 { 43,0x00},
2509 { 44,0x10},
2510 { 45,0x13},
2511 { 46,0xE0},
2512 { 47,0x04},
2513 { 48,0x10},
2514 { 49,0x13},
2515 { 50,0xE0},
2516 { 51,0x05},
2517 { 52,0x18},
2518 { 53,0x01},
2519 { 54,0xA0},
2520 { 55,0x04},
2521 { 56,0x1C},
2522 { 57,0x01},
2523 { 58,0xA0},
2524 { 59,0x05},
2525 { 60,0x00},
2526 { 61,0x00},
2527 { 62,0x00},
2528 { 63,0x00},
2529 { 64,0x00},
2530 { 65,0x00},
2531 { 66,0x00},
2532 { 67,0x00},
2533 { 68,0x00},
2534 { 69,0x00},
2535 { 70,0x00},
2536 { 71,0x00},
2537 { 72,0x10},
2538 { 73,0x00},
2539 { 74,0x00},
2540 { 75,0x08},
2541 { 76,0x18},
2542 { 77,0x04},
2543 { 78,0x40},
2544 { 79,0x08},
2545 { 80,0x1C},
2546 { 81,0x04},
2547 { 82,0x40},
2548 { 83,0x09},
2549 { 84,0x1C},
2550 { 85,0x04},
2551 { 86,0x60},
2552 { 87,0x0B},
2553 { 88,0x00},
2554 { 89,0x00},
2555 { 90,0x00},
2556 { 91,0x00},
2557 { 92,0x00},
2558 { 93,0x00},
2559 { 94,0x00},
2560 { 95,0x00},
2561 { 96,0x00},
2562 { 97,0x00},
2563 { 98,0x00},
2564 { 99,0x00},
2565 {100,0x10},
2566 {101,0x00},
2567 {102,0x00},
2568 {103,0x0A},
2569 {104,0x18},
2570 {105,0x01},
2571 {106,0xA0},
2572 {107,0x04},
2573 {108,0x1C},
2574 {109,0x01},
2575 {110,0xC0},
2576 {111,0x0A},
2577 {112,0x18},
2578 {113,0x01},
2579 {114,0xA0},
2580 {115,0x05},
2581 {116,0x1C},
2582 {117,0x01},
2583 {118,0xC0},
2584 {119,0x0A},
2585 {120,0x00},
2586 {121,0x00},
2587 {122,0x00},
2588 {123,0x00},
2589 {124,0x10},
2590 {125,0x00},
2591 {126,0x00},
2592 {127,0x04},
2593 { 0,0x03},
2594 { 8,0x00},
2595 { 9,0x00},
2596 { 10,0x00},
2597 { 11,0x00},
2598 { 12,0x10},
2599 { 13,0x00},
2600 { 14,0x00},
2601 { 15,0x05},
2602 { 16,0x18},
2603 { 17,0x04},
2604 { 18,0x40},
2605 { 19,0x0A},
2606 { 20,0x1C},
2607 { 21,0x04},
2608 { 22,0x40},
2609 { 23,0x0B},
2610 { 24,0x1C},
2611 { 25,0x04},
2612 { 26,0x60},
2613 { 27,0x0D},
2614 { 28,0x00},
2615 { 29,0x00},
2616 { 30,0x00},
2617 { 31,0x00},
2618 { 32,0x00},
2619 { 33,0x00},
2620 { 34,0x00},
2621 { 35,0x00},
2622 { 36,0x00},
2623 { 37,0x00},
2624 { 38,0x00},
2625 { 39,0x00},
2626 { 40,0x10},
2627 { 41,0x00},
2628 { 42,0x00},
2629 { 43,0x0C},
2630 { 44,0x18},
2631 { 45,0x04},
2632 { 46,0x80},
2633 { 47,0x0C},
2634 { 48,0x1C},
2635 { 49,0x04},
2636 { 50,0xA0},
2637 { 51,0x0E},
2638 { 52,0x6C},
2639 { 53,0x04},
2640 { 54,0xC0},
2641 { 55,0x10},
2642 { 56,0x1C},
2643 { 57,0x04},
2644 { 58,0xE0},
2645 { 59,0x11},
2646 { 60,0x00},
2647 { 61,0x00},
2648 { 62,0x00},
2649 { 63,0x00},
2650 { 64,0x00},
2651 { 65,0x00},
2652 { 66,0x00},
2653 { 67,0x00},
2654 { 68,0x00},
2655 { 69,0x00},
2656 { 70,0x00},
2657 { 71,0x00},
2658 { 72,0x10},
2659 { 73,0x00},
2660 { 74,0x00},
2661 { 75,0x0F},
2662 { 76,0x18},
2663 { 77,0x05},
2664 { 78,0x20},
2665 { 79,0x0E},
2666 { 80,0x1C},
2667 { 81,0x05},
2668 { 82,0x00},
2669 { 83,0x0C},
2670 { 84,0x6C},
2671 { 85,0x05},
2672 { 86,0x40},
2673 { 87,0x13},
2674 { 88,0x1C},
2675 { 89,0x05},
2676 { 90,0x60},
2677 { 91,0x14},
2678 { 92,0x00},
2679 { 93,0x00},
2680 { 94,0x00},
2681 { 95,0x00},
2682 { 96,0x00},
2683 { 97,0x00},
2684 { 98,0x00},
2685 { 99,0x00},
2686 {100,0x00},
2687 {101,0x00},
2688 {102,0x00},
2689 {103,0x00},
2690 {104,0x10},
2691 {105,0x00},
2692 {106,0x00},
2693 {107,0x12},
2694 {108,0x18},
2695 {109,0x01},
2696 {110,0xC0},
2697 {111,0x0F},
2698 {112,0x1C},
2699 {113,0x01},
2700 {114,0xC0},
2701 {115,0x12},
2702 {116,0x00},
2703 {117,0x00},
2704 {118,0x00},
2705 {119,0x00},
2706 {120,0x00},
2707 {121,0x00},
2708 {122,0x00},
2709 {123,0x00},
2710 {124,0x00},
2711 {125,0x00},
2712 {126,0x00},
2713 {127,0x00},
2714 { 0,0x04},
2715 { 8,0x10},
2716 { 9,0x00},
2717 { 10,0x00},
2718 { 11,0x16},
2719 { 12,0x30},
2720 { 13,0x01},
2721 { 14,0xA0},
2722 { 15,0x16},
2723 { 16,0x58},
2724 { 17,0x60},
2725 { 18,0x00},
2726 { 19,0x0E},
2727 { 20,0x00},
2728 { 21,0x00},
2729 { 22,0x00},
2730 { 23,0x00},
2731 { 24,0x00},
2732 { 25,0x00},
2733 { 26,0x00},
2734 { 27,0x00},
2735 { 28,0x20},
2736 { 29,0x02},
2737 { 30,0xE0},
2738 { 31,0x00},
2739 { 32,0x10},
2740 { 33,0x00},
2741 { 34,0x00},
2742 { 35,0x18},
2743 { 36,0x58},
2744 { 37,0x60},
2745 { 38,0x00},
2746 { 39,0x17},
2747 { 40,0x40},
2748 { 41,0x02},
2749 { 42,0xC0},
2750 { 43,0x18},
2751 { 44,0x00},
2752 { 45,0x00},
2753 { 46,0x00},
2754 { 47,0x00},
2755 { 48,0x00},
2756 { 49,0x00},
2757 { 50,0x00},
2758 { 51,0x00},
2759 { 52,0x00},
2760 { 53,0x00},
2761 { 54,0x00},
2762 { 55,0x00},
2763 { 56,0x44},
2764 { 57,0x00},
2765 { 58,0x40},
2766 { 59,0x10},
2767 { 60,0x44},
2768 { 61,0x00},
2769 { 62,0x80},
2770 { 63,0x10},
2771 { 64,0x58},
2772 { 65,0x60},
2773 { 66,0x00},
2774 { 67,0x17},
2775 { 68,0x1C},
2776 { 69,0x02},
2777 { 70,0xC0},
2778 { 71,0x18},
2779 { 72,0x00},
2780 { 73,0x00},
2781 { 74,0x00},
2782 { 75,0x00},
2783 { 76,0x24},
2784 { 77,0x04},
2785 { 78,0x00},
2786 { 79,0x02},
2787 { 80,0x00},
2788 { 81,0x00},
2789 { 82,0x00},
2790 { 83,0x00},
2791 { 84,0x00},
2792 { 85,0x00},
2793 { 86,0x00},
2794 { 87,0x00},
2795 { 88,0x00},
2796 { 89,0x00},
2797 { 90,0x00},
2798 { 91,0x00},
2799 { 92,0x20},
2800 { 93,0x03},
2801 { 94,0x20},
2802 { 95,0x00},
2803 { 96,0x58},
2804 { 97,0x60},
2805 { 98,0x00},
2806 { 99,0x17},
2807 {100,0x1C},
2808 {101,0x03},
2809 {102,0x20},
2810 {103,0x18},
2811 {104,0x00},
2812 {105,0x00},
2813 {106,0x00},
2814 {107,0x00},
2815 {108,0x00},
2816 {109,0x00},
2817 {110,0x00},
2818 {111,0x00},
2819 {112,0x00},
2820 {113,0x00},
2821 {114,0x00},
2822 {115,0x00},
2823 {116,0x20},
2824 {117,0x02},
2825 {118,0xC0},
2826 {119,0x02},
2827 {120,0x44},
2828 {121,0x00},
2829 {122,0x00},
2830 {123,0x10},
2831 {124,0x00},
2832 {125,0x00},
2833 {126,0x00},
2834 {127,0x00},
2835 { 0,0x05},
2836 { 8,0x00},
2837 { 9,0x00},
2838 { 10,0x00},
2839 { 11,0x00},
2840 { 12,0x58},
2841 { 13,0x60},
2842 { 14,0x00},
2843 { 15,0x16},
2844 { 16,0x1C},
2845 { 17,0x02},
2846 { 18,0xE0},
2847 { 19,0x18},
2848 { 20,0x00},
2849 { 21,0x00},
2850 { 22,0x00},
2851 { 23,0x00},
2852 { 24,0x24},
2853 { 25,0x04},
2854 { 26,0x20},
2855 { 27,0x02},
2856 { 28,0x00},
2857 { 29,0x00},
2858 { 30,0x00},
2859 { 31,0x00},
2860 { 32,0x00},
2861 { 33,0x00},
2862 { 34,0x00},
2863 { 35,0x00},
2864 { 36,0x00},
2865 { 37,0x00},
2866 { 38,0x00},
2867 { 39,0x00},
2868 { 40,0x20},
2869 { 41,0x03},
2870 { 42,0x20},
2871 { 43,0x00},
2872 { 44,0x58},
2873 { 45,0x60},
2874 { 46,0x00},
2875 { 47,0x17},
2876 { 48,0x58},
2877 { 49,0x70},
2878 { 50,0x00},
2879 { 51,0x19},
2880 { 52,0x00},
2881 { 53,0x00},
2882 { 54,0x00},
2883 { 55,0x00},
2884 { 56,0x00},
2885 { 57,0x00},
2886 { 58,0x00},
2887 { 59,0x00},
2888 { 60,0x00},
2889 { 61,0x00},
2890 { 62,0x00},
2891 { 63,0x00},
2892 { 64,0x20},
2893 { 65,0x02},
2894 { 66,0xC0},
2895 { 67,0x02},
2896 { 68,0x58},
2897 { 69,0x60},
2898 { 70,0x00},
2899 { 71,0x15},
2900 { 72,0x00},
2901 { 73,0x00},
2902 { 74,0x00},
2903 { 75,0x00},
2904 { 76,0x24},
2905 { 77,0x02},
2906 { 78,0xC0},
2907 { 79,0x02},
2908 { 80,0x00},
2909 { 81,0x00},
2910 { 82,0x00},
2911 { 83,0x00},
2912 { 84,0x00},
2913 { 85,0x00},
2914 { 86,0x00},
2915 { 87,0x00},
2916 { 88,0x00},
2917 { 89,0x00},
2918 { 90,0x00},
2919 { 91,0x00},
2920 { 92,0x20},
2921 { 93,0x03},
2922 { 94,0x00},
2923 { 95,0x00},
2924 { 96,0x24},
2925 { 97,0x03},
2926 { 98,0x00},
2927 { 99,0x00},
2928 {100,0x00},
2929 {101,0x00},
2930 {102,0x00},
2931 {103,0x00},
2932 {104,0x00},
2933 {105,0x00},
2934 {106,0x00},
2935 {107,0x00},
2936 {108,0x00},
2937 {109,0x00},
2938 {110,0x00},
2939 {111,0x00},
2940 {112,0x20},
2941 {113,0x03},
2942 {114,0x00},
2943 {115,0x05},
2944 {116,0x58},
2945 {117,0x60},
2946 {118,0x00},
2947 {119,0x15},
2948 {120,0x00},
2949 {121,0x00},
2950 {122,0x00},
2951 {123,0x00},
2952 {124,0x24},
2953 {125,0x03},
2954 {126,0x00},
2955 {127,0x02},
2956 { 0,0x06},
2957 { 8,0x00},
2958 { 9,0x00},
2959 { 10,0x00},
2960 { 11,0x00},
2961 { 12,0x00},
2962 { 13,0x00},
2963 { 14,0x00},
2964 { 15,0x00},
2965 { 16,0x00},
2966 { 17,0x00},
2967 { 18,0x00},
2968 { 19,0x00},
2969 { 20,0x20},
2970 { 21,0x03},
2971 { 22,0x00},
2972 { 23,0x05},
2973 { 24,0x58},
2974 { 25,0x60},
2975 { 26,0x00},
2976 { 27,0x14},
2977 { 28,0x1C},
2978 { 29,0x03},
2979 { 30,0x00},
2980 { 31,0x18},
2981 { 32,0x00},
2982 { 33,0x00},
2983 { 34,0x00},
2984 { 35,0x00},
2985 { 36,0x24},
2986 { 37,0x02},
2987 { 38,0x60},
2988 { 39,0x00},
2989 { 40,0x58},
2990 { 41,0x70},
2991 { 42,0x00},
2992 { 43,0x15},
2993 { 44,0x00},
2994 { 45,0x00},
2995 { 46,0x00},
2996 { 47,0x00},
2997 { 48,0x00},
2998 { 49,0x00},
2999 { 50,0x00},
3000 { 51,0x00},
3001 { 52,0x00},
3002 { 53,0x00},
3003 { 54,0x00},
3004 { 55,0x00},
3005 { 56,0x20},
3006 { 57,0x02},
3007 { 58,0xA0},
3008 { 59,0x02},
3009 { 60,0x58},
3010 { 61,0x60},
3011 { 62,0x00},
3012 { 63,0x15},
3013 { 64,0x40},
3014 { 65,0x00},
3015 { 66,0xC0},
3016 { 67,0x18},
3017 { 68,0x58},
3018 { 69,0x60},
3019 { 70,0x00},
3020 { 71,0x06},
3021 { 72,0x00},
3022 { 73,0x00},
3023 { 74,0x00},
3024 { 75,0x00},
3025 { 76,0x00},
3026 { 77,0x00},
3027 { 78,0x00},
3028 { 79,0x00},
3029 { 80,0x44},
3030 { 81,0x00},
3031 { 82,0x80},
3032 { 83,0x02},
3033 { 84,0x20},
3034 { 85,0x02},
3035 { 86,0xA0},
3036 { 87,0x02},
3037 { 88,0x44},
3038 { 89,0x00},
3039 { 90,0x00},
3040 { 91,0x02},
3041 { 92,0x00},
3042 { 93,0x00},
3043 { 94,0x00},
3044 { 95,0x00},
3045 { 96,0x00},
3046 { 97,0x00},
3047 { 98,0x00},
3048 { 99,0x00},
3049 {100,0x18},
3050 {101,0x02},
3051 {102,0xA0},
3052 {103,0x16},
3053 {104,0x18},
3054 {105,0x01},
3055 {106,0xE0},
3056 {107,0x0C},
3057 {108,0x00},
3058 {109,0x00},
3059 {110,0x00},
3060 {111,0x00},
3061 {112,0x00},
3062 {113,0x00},
3063 {114,0x00},
3064 {115,0x00},
3065 {116,0x10},
3066 {117,0x00},
3067 {118,0xA0},
3068 {119,0x15},
3069 {120,0x10},
3070 {121,0x00},
3071 {122,0x00},
3072 {123,0x17},
3073 {124,0x18},
3074 {125,0x01},
3075 {126,0xA0},
3076 {127,0x15},
3077 { 0,0x07},
3078 { 8,0x1C},
3079 { 9,0x01},
3080 { 10,0xA0},
3081 { 11,0x17},
3082 { 12,0x00},
3083 { 13,0x00},
3084 { 14,0x00},
3085 { 15,0x00},
3086 { 16,0x24},
3087 { 17,0x00},
3088 { 18,0xA0},
3089 { 19,0x00},
3090 { 20,0x00},
3091 { 21,0x00},
3092 { 22,0x00},
3093 { 23,0x00},
3094 { 24,0x00},
3095 { 25,0x00},
3096 { 26,0x00},
3097 { 27,0x00},
3098 { 28,0x00},
3099 { 29,0x00},
3100 { 30,0x00},
3101 { 31,0x00},
3102 { 32,0x10},
3103 { 33,0x00},
3104 { 34,0x00},
3105 { 35,0x19},
3106 { 36,0x58},
3107 { 37,0x60},
3108 { 38,0x00},
3109 { 39,0x0A},
3110 { 40,0x59},
3111 { 41,0x00},
3112 { 42,0x00},
3113 { 43,0x1E},
3114 { 44,0x58},
3115 { 45,0x60},
3116 { 46,0x00},
3117 { 47,0x0A},
3118 { 48,0x59},
3119 { 49,0x00},
3120 { 50,0x00},
3121 { 51,0x1B},
3122 { 52,0x00},
3123 { 53,0x00},
3124 { 54,0x00},
3125 { 55,0x00},
3126 { 56,0x44},
3127 { 57,0x00},
3128 { 58,0x40},
3129 { 59,0x3A},
3130 { 60,0x00},
3131 { 61,0x00},
3132 { 62,0x00},
3133 { 63,0x00},
3134 { 64,0x44},
3135 { 65,0x00},
3136 { 66,0x40},
3137 { 67,0x68},
3138 { 68,0x18},
3139 { 69,0x02},
3140 { 70,0x00},
3141 { 71,0x04},
3142 { 72,0x1C},
3143 { 73,0x02},
3144 { 74,0x20},
3145 { 75,0x05},
3146 { 76,0x00},
3147 { 77,0x00},
3148 { 78,0x00},
3149 { 79,0x00},
3150 { 80,0x58},
3151 { 81,0x60},
3152 { 82,0x00},
3153 { 83,0x0A},
3154 { 84,0x00},
3155 { 85,0x00},
3156 { 86,0x00},
3157 { 87,0x00},
3158 { 88,0x10},
3159 { 89,0x00},
3160 { 90,0x20},
3161 { 91,0x1A},
3162 { 92,0x10},
3163 { 93,0x00},
3164 { 94,0x20},
3165 { 95,0x1B},
3166 { 96,0x59},
3167 { 97,0x00},
3168 { 98,0x00},
3169 { 99,0x1C},
3170 {100,0x00},
3171 {101,0x00},
3172 {102,0x00},
3173 {103,0x00},
3174 {104,0x00},
3175 {105,0x00},
3176 {106,0x00},
3177 {107,0x00},
3178 {108,0x00},
3179 {109,0x00},
3180 {110,0x00},
3181 {111,0x00},
3182 {112,0x44},
3183 {113,0x00},
3184 {114,0x40},
3185 {115,0x0A},
3186 {116,0x18},
3187 {117,0x05},
3188 {118,0xC0},
3189 {119,0x1B},
3190 {120,0x6C},
3191 {121,0x05},
3192 {122,0xE0},
3193 {123,0x1C},
3194 {124,0x1C},
3195 {125,0x06},
3196 {126,0x00},
3197 {127,0x1D},
3198 { 0,0x08},
3199 { 8,0x6C},
3200 { 9,0x06},
3201 { 10,0x20},
3202 { 11,0x1F},
3203 { 12,0x1C},
3204 { 13,0x06},
3205 { 14,0x40},
3206 { 15,0x20},
3207 { 16,0x00},
3208 { 17,0x00},
3209 { 18,0x00},
3210 { 19,0x00},
3211 { 20,0x00},
3212 { 21,0x00},
3213 { 22,0x00},
3214 { 23,0x00},
3215 { 24,0x00},
3216 { 25,0x00},
3217 { 26,0x00},
3218 { 27,0x00},
3219 { 28,0x10},
3220 { 29,0x00},
3221 { 30,0x20},
3222 { 31,0x1E},
3223 { 32,0x44},
3224 { 33,0x00},
3225 { 34,0x00},
3226 { 35,0x0A},
3227 { 36,0x18},
3228 { 37,0x06},
3229 { 38,0x60},
3230 { 39,0x1B},
3231 { 40,0x6C},
3232 { 41,0x06},
3233 { 42,0x80},
3234 { 43,0x1C},
3235 { 44,0x1C},
3236 { 45,0x06},
3237 { 46,0xA0},
3238 { 47,0x1D},
3239 { 48,0x6C},
3240 { 49,0x06},
3241 { 50,0xC0},
3242 { 51,0x1F},
3243 { 52,0x1C},
3244 { 53,0x06},
3245 { 54,0xE0},
3246 { 55,0x20},
3247 { 56,0x00},
3248 { 57,0x00},
3249 { 58,0x00},
3250 { 59,0x00},
3251 { 60,0x00},
3252 { 61,0x00},
3253 { 62,0x00},
3254 { 63,0x00},
3255 { 64,0x00},
3256 { 65,0x00},
3257 { 66,0x00},
3258 { 67,0x00},
3259 { 68,0x10},
3260 { 69,0x00},
3261 { 70,0x40},
3262 { 71,0x1E},
3263 { 72,0x00},
3264 { 73,0x00},
3265 { 74,0x00},
3266 { 75,0x00},
3267 { 76,0x18},
3268 { 77,0x02},
3269 { 78,0x00},
3270 { 79,0x1F},
3271 { 80,0x1C},
3272 { 81,0x07},
3273 { 82,0x00},
3274 { 83,0x1E},
3275 { 84,0x1C},
3276 { 85,0x07},
3277 { 86,0x20},
3278 { 87,0x22},
3279 { 88,0x18},
3280 { 89,0x02},
3281 { 90,0x00},
3282 { 91,0x04},
3283 { 92,0x1C},
3284 { 93,0x02},
3285 { 94,0x00},
3286 { 95,0x05},
3287 { 96,0x00},
3288 { 97,0x00},
3289 { 98,0x00},
3290 { 99,0x00},
3291 {100,0x10},
3292 {101,0x00},
3293 {102,0x20},
3294 {103,0x21},
3295 {104,0x00},
3296 {105,0x00},
3297 {106,0x00},
3298 {107,0x00},
3299 {108,0x10},
3300 {109,0x00},
3301 {110,0x20},
3302 {111,0x23},
3303 {112,0x18},
3304 {113,0x00},
3305 {114,0xE0},
3306 {115,0x21},
3307 {116,0x1C},
3308 {117,0x01},
3309 {118,0x00},
3310 {119,0x23},
3311 {120,0x00},
3312 {121,0x00},
3313 {122,0x00},
3314 {123,0x00},
3315 {124,0x18},
3316 {125,0x00},
3317 {126,0xE0},
3318 {127,0x21},
3319 { 0,0x09},
3320 { 8,0x00},
3321 { 9,0x00},
3322 { 10,0x00},
3323 { 11,0x00},
3324 { 12,0x10},
3325 { 13,0x00},
3326 { 14,0x00},
3327 { 15,0x47},
3328 { 16,0x24},
3329 { 17,0x01},
3330 { 18,0xC0},
3331 { 19,0x00},
3332 { 20,0x00},
3333 { 21,0x00},
3334 { 22,0x00},
3335 { 23,0x00},
3336 { 24,0x1C},
3337 { 25,0x01},
3338 { 26,0x00},
3339 { 27,0x23},
3340 { 28,0x00},
3341 { 29,0x00},
3342 { 30,0x00},
3343 { 31,0x00},
3344 { 32,0x00},
3345 { 33,0x00},
3346 { 34,0x00},
3347 { 35,0x00},
3348 { 36,0x00},
3349 { 37,0x00},
3350 { 38,0x00},
3351 { 39,0x00},
3352 { 40,0x10},
3353 { 41,0x00},
3354 { 42,0x00},
3355 { 43,0x4D},
3356 { 44,0x00},
3357 { 45,0x00},
3358 { 46,0x00},
3359 { 47,0x00},
3360 { 48,0x44},
3361 { 49,0x00},
3362 { 50,0x00},
3363 { 51,0x5E},
3364 { 52,0x18},
3365 { 53,0x02},
3366 { 54,0x00},
3367 { 55,0x04},
3368 { 56,0x18},
3369 { 57,0x02},
3370 { 58,0x00},
3371 { 59,0x05},
3372 { 60,0x00},
3373 { 61,0x00},
3374 { 62,0x00},
3375 { 63,0x00},
3376 { 64,0x00},
3377 { 65,0x00},
3378 { 66,0x00},
3379 { 67,0x00},
3380 { 68,0x10},
3381 { 69,0x00},
3382 { 70,0x20},
3383 { 71,0x24},
3384 { 72,0x10},
3385 { 73,0x00},
3386 { 74,0x20},
3387 { 75,0x2A},
3388 { 76,0x18},
3389 { 77,0x09},
3390 { 78,0x00},
3391 { 79,0x24},
3392 { 80,0x1C},
3393 { 81,0x01},
3394 { 82,0xA0},
3395 { 83,0x25},
3396 { 84,0x1C},
3397 { 85,0x09},
3398 { 86,0x20},
3399 { 87,0x27},
3400 { 88,0x00},
3401 { 89,0x00},
3402 { 90,0x00},
3403 { 91,0x00},
3404 { 92,0x18},
3405 { 93,0x01},
3406 { 94,0xA0},
3407 { 95,0x27},
3408 { 96,0x00},
3409 { 97,0x00},
3410 { 98,0x00},
3411 { 99,0x00},
3412 {100,0x4C},
3413 {101,0x09},
3414 {102,0x40},
3415 {103,0x26},
3416 {104,0x1C},
3417 {105,0x09},
3418 {106,0x60},
3419 {107,0x29},
3420 {108,0x18},
3421 {109,0x09},
3422 {110,0x80},
3423 {111,0x2A},
3424 {112,0x1C},
3425 {113,0x01},
3426 {114,0xA0},
3427 {115,0x2B},
3428 {116,0x00},
3429 {117,0x00},
3430 {118,0x00},
3431 {119,0x00},
3432 {120,0x10},
3433 {121,0x00},
3434 {122,0x00},
3435 {123,0x28},
3436 {124,0x1C},
3437 {125,0x09},
3438 {126,0xA0},
3439 {127,0x2D},
3440 { 0,0x0A},
3441 { 8,0x00},
3442 { 9,0x00},
3443 { 10,0x00},
3444 { 11,0x00},
3445 { 12,0x18},
3446 { 13,0x01},
3447 { 14,0x20},
3448 { 15,0x28},
3449 { 16,0x00},
3450 { 17,0x00},
3451 { 18,0x00},
3452 { 19,0x00},
3453 { 20,0x10},
3454 { 21,0x00},
3455 { 22,0x00},
3456 { 23,0x2C},
3457 { 24,0x18},
3458 { 25,0x01},
3459 { 26,0x20},
3460 { 27,0x2C},
3461 { 28,0x10},
3462 { 29,0x00},
3463 { 30,0x00},
3464 { 31,0x44},
3465 { 32,0x00},
3466 { 33,0x00},
3467 { 34,0x00},
3468 { 35,0x00},
3469 { 36,0x00},
3470 { 37,0x00},
3471 { 38,0x00},
3472 { 39,0x00},
3473 { 40,0x10},
3474 { 41,0x00},
3475 { 42,0x00},
3476 { 43,0x45},
3477 { 44,0x18},
3478 { 45,0x02},
3479 { 46,0x00},
3480 { 47,0x44},
3481 { 48,0x1C},
3482 { 49,0x02},
3483 { 50,0x20},
3484 { 51,0x45},
3485 { 52,0x00},
3486 { 53,0x00},
3487 { 54,0x00},
3488 { 55,0x00},
3489 { 56,0x24},
3490 { 57,0x00},
3491 { 58,0xE0},
3492 { 59,0x01},
3493 { 60,0x00},
3494 { 61,0x00},
3495 { 62,0x00},
3496 { 63,0x00},
3497 { 64,0x24},
3498 { 65,0x02},
3499 { 66,0x40},
3500 { 67,0x00},
3501 { 68,0x00},
3502 { 69,0x00},
3503 { 70,0x00},
3504 { 71,0x00},
3505 { 72,0x00},
3506 { 73,0x00},
3507 { 74,0x00},
3508 { 75,0x00},
3509 { 76,0x00},
3510 { 77,0x00},
3511 { 78,0x00},
3512 { 79,0x00},
3513 { 80,0x10},
3514 { 81,0x00},
3515 { 82,0x40},
3516 { 83,0x46},
3517 { 84,0x18},
3518 { 85,0x02},
3519 { 86,0x00},
3520 { 87,0x44},
3521 { 88,0x1C},
3522 { 89,0x02},
3523 { 90,0x00},
3524 { 91,0x46},
3525 { 92,0x18},
3526 { 93,0x02},
3527 { 94,0x00},
3528 { 95,0x45},
3529 { 96,0x1C},
3530 { 97,0x02},
3531 { 98,0x20},
3532 { 99,0x46},
3533 {100,0x00},
3534 {101,0x00},
3535 {102,0x00},
3536 {103,0x00},
3537 {104,0x10},
3538 {105,0x00},
3539 {106,0x20},
3540 {107,0x47},
3541 {108,0x00},
3542 {109,0x00},
3543 {110,0x00},
3544 {111,0x00},
3545 {112,0x10},
3546 {113,0x00},
3547 {114,0x20},
3548 {115,0x4D},
3549 {116,0x00},
3550 {117,0x00},
3551 {118,0x00},
3552 {119,0x00},
3553 {120,0x44},
3554 {121,0x00},
3555 {122,0x00},
3556 {123,0x2E},
3557 {124,0x18},
3558 {125,0x02},
3559 {126,0x00},
3560 {127,0x04},
3561 { 0,0x0B},
3562 { 8,0x1C},
3563 { 9,0x02},
3564 { 10,0x00},
3565 { 11,0x05},
3566 { 12,0x18},
3567 { 13,0x02},
3568 { 14,0x00},
3569 { 15,0x04},
3570 { 16,0x1C},
3571 { 17,0x02},
3572 { 18,0x20},
3573 { 19,0x05},
3574 { 20,0x00},
3575 { 21,0x00},
3576 { 22,0x00},
3577 { 23,0x00},
3578 { 24,0x10},
3579 { 25,0x00},
3580 { 26,0x20},
3581 { 27,0x2E},
3582 { 28,0x00},
3583 { 29,0x00},
3584 { 30,0x00},
3585 { 31,0x00},
3586 { 32,0x10},
3587 { 33,0x00},
3588 { 34,0x20},
3589 { 35,0x32},
3590 { 36,0x00},
3591 { 37,0x00},
3592 { 38,0x00},
3593 { 39,0x00},
3594 { 40,0x10},
3595 { 41,0x00},
3596 { 42,0x20},
3597 { 43,0x38},
3598 { 44,0x10},
3599 { 45,0x00},
3600 { 46,0x20},
3601 { 47,0x3E},
3602 { 48,0x18},
3603 { 49,0x07},
3604 { 50,0x40},
3605 { 51,0x2E},
3606 { 52,0x1C},
3607 { 53,0x01},
3608 { 54,0xC0},
3609 { 55,0x2F},
3610 { 56,0x1C},
3611 { 57,0x07},
3612 { 58,0x60},
3613 { 59,0x31},
3614 { 60,0x18},
3615 { 61,0x07},
3616 { 62,0x80},
3617 { 63,0x32},
3618 { 64,0x1C},
3619 { 65,0x07},
3620 { 66,0xA0},
3621 { 67,0x34},
3622 { 68,0x00},
3623 { 69,0x00},
3624 { 70,0x00},
3625 { 71,0x00},
3626 { 72,0x10},
3627 { 73,0x00},
3628 { 74,0x00},
3629 { 75,0x30},
3630 { 76,0x6C},
3631 { 77,0x07},
3632 { 78,0xC0},
3633 { 79,0x36},
3634 { 80,0x1C},
3635 { 81,0x07},
3636 { 82,0xE0},
3637 { 83,0x37},
3638 { 84,0x18},
3639 { 85,0x08},
3640 { 86,0x00},
3641 { 87,0x38},
3642 { 88,0x1C},
3643 { 89,0x08},
3644 { 90,0x20},
3645 { 91,0x3A},
3646 { 92,0x00},
3647 { 93,0x00},
3648 { 94,0x00},
3649 { 95,0x00},
3650 { 96,0x10},
3651 { 97,0x00},
3652 { 98,0x00},
3653 { 99,0x35},
3654 {100,0x6C},
3655 {101,0x08},
3656 {102,0x40},
3657 {103,0x3C},
3658 {104,0x1C},
3659 {105,0x08},
3660 {106,0x60},
3661 {107,0x3D},
3662 {108,0x18},
3663 {109,0x08},
3664 {110,0x80},
3665 {111,0x3E},
3666 {112,0x1C},
3667 {113,0x08},
3668 {114,0xA0},
3669 {115,0x40},
3670 {116,0x00},
3671 {117,0x00},
3672 {118,0x00},
3673 {119,0x00},
3674 {120,0x10},
3675 {121,0x00},
3676 {122,0x00},
3677 {123,0x3B},
3678 {124,0x6C},
3679 {125,0x08},
3680 {126,0xC0},
3681 {127,0x42},
3682 { 0,0x0C},
3683 { 8,0x1C},
3684 { 9,0x08},
3685 { 10,0xE0},
3686 { 11,0x43},
3687 { 12,0x18},
3688 { 13,0x02},
3689 { 14,0x00},
3690 { 15,0x35},
3691 { 16,0x1C},
3692 { 17,0x02},
3693 { 18,0x00},
3694 { 19,0x3B},
3695 { 20,0x00},
3696 { 21,0x00},
3697 { 22,0x00},
3698 { 23,0x00},
3699 { 24,0x10},
3700 { 25,0x00},
3701 { 26,0x00},
3702 { 27,0x41},
3703 { 28,0x1C},
3704 { 29,0x02},
3705 { 30,0x00},
3706 { 31,0x41},
3707 { 32,0x00},
3708 { 33,0x00},
3709 { 34,0x00},
3710 { 35,0x00},
3711 { 36,0x24},
3712 { 37,0x00},
3713 { 38,0xE0},
3714 { 39,0x00},
3715 { 40,0x00},
3716 { 41,0x00},
3717 { 42,0x00},
3718 { 43,0x00},
3719 { 44,0x1C},
3720 { 45,0x02},
3721 { 46,0x00},
3722 { 47,0x30},
3723 { 48,0x00},
3724 { 49,0x00},
3725 { 50,0x00},
3726 { 51,0x00},
3727 { 52,0x00},
3728 { 53,0x00},
3729 { 54,0x00},
3730 { 55,0x00},
3731 { 56,0x00},
3732 { 57,0x00},
3733 { 58,0x00},
3734 { 59,0x00},
3735 { 60,0x10},
3736 { 61,0x00},
3737 { 62,0x20},
3738 { 63,0x47},
3739 { 64,0x10},
3740 { 65,0x00},
3741 { 66,0x20},
3742 { 67,0x4D},
3743 { 68,0x18},
3744 { 69,0x02},
3745 { 70,0x00},
3746 { 71,0x47},
3747 { 72,0x18},
3748 { 73,0x02},
3749 { 74,0x00},
3750 { 75,0x4D},
3751 { 76,0x00},
3752 { 77,0x00},
3753 { 78,0x00},
3754 { 79,0x00},
3755 { 80,0x00},
3756 { 81,0x00},
3757 { 82,0x00},
3758 { 83,0x00},
3759 { 84,0x10},
3760 { 85,0x00},
3761 { 86,0x20},
3762 { 87,0x55},
3763 { 88,0x10},
3764 { 89,0x00},
3765 { 90,0x20},
3766 { 91,0x59},
3767 { 92,0x58},
3768 { 93,0x60},
3769 { 94,0x00},
3770 { 95,0x0A},
3771 { 96,0x59},
3772 { 97,0x00},
3773 { 98,0x00},
3774 { 99,0x1B},
3775 {100,0x00},
3776 {101,0x00},
3777 {102,0x00},
3778 {103,0x00},
3779 {104,0x00},
3780 {105,0x00},
3781 {106,0x00},
3782 {107,0x00},
3783 {108,0x00},
3784 {109,0x00},
3785 {110,0x00},
3786 {111,0x00},
3787 {112,0x44},
3788 {113,0x00},
3789 {114,0x40},
3790 {115,0x07},
3791 {116,0x18},
3792 {117,0x02},
3793 {118,0x00},
3794 {119,0x47},
3795 {120,0x1C},
3796 {121,0x02},
3797 {122,0x00},
3798 {123,0x19},
3799 {124,0x18},
3800 {125,0x02},
3801 {126,0x00},
3802 {127,0x4D},
3803 { 0,0x0D},
3804 { 8,0x1C},
3805 { 9,0x02},
3806 { 10,0x00},
3807 { 11,0x19},
3808 { 12,0x00},
3809 { 13,0x00},
3810 { 14,0x00},
3811 { 15,0x00},
3812 { 16,0x10},
3813 { 17,0x00},
3814 { 18,0x20},
3815 { 19,0x02},
3816 { 20,0x44},
3817 { 21,0x00},
3818 { 22,0x00},
3819 { 23,0x07},
3820 { 24,0x18},
3821 { 25,0x02},
3822 { 26,0x00},
3823 { 27,0x19},
3824 { 28,0x1C},
3825 { 29,0x02},
3826 { 30,0x20},
3827 { 31,0x47},
3828 { 32,0x18},
3829 { 33,0x02},
3830 { 34,0x00},
3831 { 35,0x19},
3832 { 36,0x1C},
3833 { 37,0x02},
3834 { 38,0x20},
3835 { 39,0x4D},
3836 { 40,0x00},
3837 { 41,0x00},
3838 { 42,0x00},
3839 { 43,0x00},
3840 { 44,0x10},
3841 { 45,0x00},
3842 { 46,0x20},
3843 { 47,0x02},
3844 { 48,0x00},
3845 { 49,0x00},
3846 { 50,0x00},
3847 { 51,0x00},
3848 { 52,0x10},
3849 { 53,0x00},
3850 { 54,0x20},
3851 { 55,0x03},
3852 { 56,0x18},
3853 { 57,0x09},
3854 { 58,0xC0},
3855 { 59,0x47},
3856 { 60,0x6C},
3857 { 61,0x09},
3858 { 62,0xE0},
3859 { 63,0x48},
3860 { 64,0x1C},
3861 { 65,0x09},
3862 { 66,0xC0},
3863 { 67,0x49},
3864 { 68,0x6C},
3865 { 69,0x0A},
3866 { 70,0x00},
3867 { 71,0x4B},
3868 { 72,0x1C},
3869 { 73,0x0A},
3870 { 74,0x20},
3871 { 75,0x4C},
3872 { 76,0x18},
3873 { 77,0x09},
3874 { 78,0xC0},
3875 { 79,0x4D},
3876 { 80,0x6C},
3877 { 81,0x09},
3878 { 82,0xE0},
3879 { 83,0x4E},
3880 { 84,0x00},
3881 { 85,0x00},
3882 { 86,0x00},
3883 { 87,0x00},
3884 { 88,0x10},
3885 { 89,0x00},
3886 { 90,0x00},
3887 { 91,0x4A},
3888 { 92,0x1C},
3889 { 93,0x09},
3890 { 94,0xC0},
3891 { 95,0x4F},
3892 { 96,0x6C},
3893 { 97,0x0A},
3894 { 98,0x00},
3895 { 99,0x51},
3896 {100,0x1C},
3897 {101,0x0A},
3898 {102,0x20},
3899 {103,0x52},
3900 {104,0x58},
3901 {105,0x60},
3902 {106,0x00},
3903 {107,0x0B},
3904 {108,0x00},
3905 {109,0x00},
3906 {110,0x00},
3907 {111,0x00},
3908 {112,0x00},
3909 {113,0x00},
3910 {114,0x00},
3911 {115,0x00},
3912 {116,0x10},
3913 {117,0x00},
3914 {118,0x00},
3915 {119,0x50},
3916 {120,0x20},
3917 {121,0x03},
3918 {122,0xE0},
3919 {123,0x02},
3920 {124,0x00},
3921 {125,0x00},
3922 {126,0x00},
3923 {127,0x00},
3924 { 0,0x0E},
3925 { 8,0x18},
3926 { 9,0x03},
3927 { 10,0xE0},
3928 { 11,0x4A},
3929 { 12,0x18},
3930 { 13,0x03},
3931 { 14,0xE0},
3932 { 15,0x50},
3933 { 16,0x00},
3934 { 17,0x00},
3935 { 18,0x00},
3936 { 19,0x00},
3937 { 20,0x00},
3938 { 21,0x00},
3939 { 22,0x00},
3940 { 23,0x00},
3941 { 24,0x10},
3942 { 25,0x00},
3943 { 26,0x40},
3944 { 27,0x53},
3945 { 28,0x10},
3946 { 29,0x00},
3947 { 30,0x40},
3948 { 31,0x54},
3949 { 32,0x18},
3950 { 33,0x02},
3951 { 34,0x00},
3952 { 35,0x02},
3953 { 36,0x1C},
3954 { 37,0x02},
3955 { 38,0x00},
3956 { 39,0x53},
3957 { 40,0x18},
3958 { 41,0x02},
3959 { 42,0x00},
3960 { 43,0x03},
3961 { 44,0x1C},
3962 { 45,0x02},
3963 { 46,0x00},
3964 { 47,0x54},
3965 { 48,0x00},
3966 { 49,0x00},
3967 { 50,0x00},
3968 { 51,0x00},
3969 { 52,0x10},
3970 { 53,0x00},
3971 { 54,0x20},
3972 { 55,0x02},
3973 { 56,0x00},
3974 { 57,0x00},
3975 { 58,0x00},
3976 { 59,0x00},
3977 { 60,0x10},
3978 { 61,0x00},
3979 { 62,0x20},
3980 { 63,0x03},
3981 { 64,0x18},
3982 { 65,0x0A},
3983 { 66,0x40},
3984 { 67,0x55},
3985 { 68,0x1C},
3986 { 69,0x0A},
3987 { 70,0x60},
3988 { 71,0x56},
3989 { 72,0x1C},
3990 { 73,0x0A},
3991 { 74,0x80},
3992 { 75,0x58},
3993 { 76,0x18},
3994 { 77,0x0A},
3995 { 78,0x40},
3996 { 79,0x59},
3997 { 80,0x1C},
3998 { 81,0x0A},
3999 { 82,0x60},
4000 { 83,0x5A},
4001 { 84,0x00},
4002 { 85,0x00},
4003 { 86,0x00},
4004 { 87,0x00},
4005 { 88,0x10},
4006 { 89,0x00},
4007 { 90,0x20},
4008 { 91,0x57},
4009 { 92,0x1C},
4010 { 93,0x0A},
4011 { 94,0x80},
4012 { 95,0x5C},
4013 { 96,0x00},
4014 { 97,0x00},
4015 { 98,0x00},
4016 { 99,0x00},
4017 {100,0x00},
4018 {101,0x00},
4019 {102,0x00},
4020 {103,0x00},
4021 {104,0x00},
4022 {105,0x00},
4023 {106,0x00},
4024 {107,0x00},
4025 {108,0x10},
4026 {109,0x00},
4027 {110,0x20},
4028 {111,0x5B},
4029 {112,0x18},
4030 {113,0x01},
4031 {114,0x80},
4032 {115,0x57},
4033 {116,0x18},
4034 {117,0x01},
4035 {118,0x80},
4036 {119,0x5B},
4037 {120,0x00},
4038 {121,0x00},
4039 {122,0x00},
4040 {123,0x00},
4041 {124,0x00},
4042 {125,0x00},
4043 {126,0x00},
4044 {127,0x00},
4045 { 0,0x0F},
4046 { 8,0x10},
4047 { 9,0x00},
4048 { 10,0x00},
4049 { 11,0x5D},
4050 { 12,0x10},
4051 { 13,0x00},
4052 { 14,0x00},
4053 { 15,0x5E},
4054 { 16,0x18},
4055 { 17,0x02},
4056 { 18,0x00},
4057 { 19,0x02},
4058 { 20,0x1C},
4059 { 21,0x02},
4060 { 22,0x00},
4061 { 23,0x5D},
4062 { 24,0x18},
4063 { 25,0x02},
4064 { 26,0x00},
4065 { 27,0x03},
4066 { 28,0x1C},
4067 { 29,0x02},
4068 { 30,0x00},
4069 { 31,0x5E},
4070 { 32,0x00},
4071 { 33,0x00},
4072 { 34,0x00},
4073 { 35,0x00},
4074 { 36,0x10},
4075 { 37,0x00},
4076 { 38,0x20},
4077 { 39,0x02},
4078 { 40,0x00},
4079 { 41,0x00},
4080 { 42,0x00},
4081 { 43,0x00},
4082 { 44,0x10},
4083 { 45,0x00},
4084 { 46,0x20},
4085 { 47,0x03},
4086 { 48,0x58},
4087 { 49,0x60},
4088 { 50,0x00},
4089 { 51,0x00},
4090 { 52,0x59},
4091 { 53,0x00},
4092 { 54,0x00},
4093 { 55,0x61},
4094 { 56,0x58},
4095 { 57,0x70},
4096 { 58,0x00},
4097 { 59,0x00},
4098 { 60,0x59},
4099 { 61,0x00},
4100 { 62,0x00},
4101 { 63,0x61},
4102 { 64,0x00},
4103 { 65,0x00},
4104 { 66,0x00},
4105 { 67,0x00},
4106 { 68,0x44},
4107 { 69,0x00},
4108 { 70,0x40},
4109 { 71,0x05},
4110 { 72,0x00},
4111 { 73,0x00},
4112 { 74,0x00},
4113 { 75,0x00},
4114 { 76,0x44},
4115 { 77,0x00},
4116 { 78,0x40},
4117 { 79,0x08},
4118 { 80,0x58},
4119 { 81,0x60},
4120 { 82,0x00},
4121 { 83,0x2D},
4122 { 84,0x00},
4123 { 85,0x00},
4124 { 86,0x00},
4125 { 87,0x00},
4126 { 88,0x44},
4127 { 89,0x00},
4128 { 90,0x00},
4129 { 91,0x08},
4130 { 92,0x00},
4131 { 93,0x00},
4132 { 94,0x00},
4133 { 95,0x00},
4134 { 96,0x00},
4135 { 97,0x00},
4136 { 98,0x00},
4137 { 99,0x00},
4138 {100,0x18},
4139 {101,0x03},
4140 {102,0x40},
4141 {103,0x00},
4142 {104,0x18},
4143 {105,0x03},
4144 {106,0x40},
4145 {107,0x01},
4146 {108,0x44},
4147 {109,0x00},
4148 {110,0x00},
4149 {111,0x03},
4150 {112,0x18},
4151 {113,0x03},
4152 {114,0x40},
4153 {115,0x02},
4154 {116,0x18},
4155 {117,0x03},
4156 {118,0x40},
4157 {119,0x03},
4158 {120,0x44},
4159 {121,0x00},
4160 {122,0x00},
4161 {123,0x00},
4162 {124,0x00},
4163 {125,0x00},
4164 {126,0x00},
4165 {127,0x00},
4166 { 0,0x10},
4167 { 8,0x10},
4168 { 9,0x00},
4169 { 10,0x20},
4170 { 11,0x5F},
4171 { 12,0x10},
4172 { 13,0x00},
4173 { 14,0x20},
4174 { 15,0x60},
4175 { 16,0x18},
4176 { 17,0x03},
4177 { 18,0x40},
4178 { 19,0x5F},
4179 { 20,0x18},
4180 { 21,0x0A},
4181 { 22,0xE0},
4182 { 23,0x63},
4183 { 24,0x6C},
4184 { 25,0x0A},
4185 { 26,0xC0},
4186 { 27,0x62},
4187 { 28,0x6C},
4188 { 29,0x0B},
4189 { 30,0x00},
4190 { 31,0x65},
4191 { 32,0x10},
4192 { 33,0x00},
4193 { 34,0x20},
4194 { 35,0x61},
4195 { 36,0x1C},
4196 { 37,0x0A},
4197 { 38,0xA0},
4198 { 39,0x61},
4199 { 40,0x1C},
4200 { 41,0x0B},
4201 { 42,0x20},
4202 { 43,0x66},
4203 { 44,0x00},
4204 { 45,0x00},
4205 { 46,0x00},
4206 { 47,0x00},
4207 { 48,0x00},
4208 { 49,0x00},
4209 { 50,0x00},
4210 { 51,0x00},
4211 { 52,0x00},
4212 { 53,0x00},
4213 { 54,0x00},
4214 { 55,0x00},
4215 { 56,0x10},
4216 { 57,0x00},
4217 { 58,0x00},
4218 { 59,0x64},
4219 { 60,0x18},
4220 { 61,0x03},
4221 { 62,0x40},
4222 { 63,0x60},
4223 { 64,0x18},
4224 { 65,0x0B},
4225 { 66,0x80},
4226 { 67,0x69},
4227 { 68,0x6C},
4228 { 69,0x0B},
4229 { 70,0x60},
4230 { 71,0x68},
4231 { 72,0x6C},
4232 { 73,0x0B},
4233 { 74,0xA0},
4234 { 75,0x6B},
4235 { 76,0x10},
4236 { 77,0x00},
4237 { 78,0x20},
4238 { 79,0x67},
4239 { 80,0x1C},
4240 { 81,0x0B},
4241 { 82,0x40},
4242 { 83,0x67},
4243 { 84,0x1C},
4244 { 85,0x0B},
4245 { 86,0xC0},
4246 { 87,0x6C},
4247 { 88,0x00},
4248 { 89,0x00},
4249 { 90,0x00},
4250 { 91,0x00},
4251 { 92,0x00},
4252 { 93,0x00},
4253 { 94,0x00},
4254 { 95,0x00},
4255 { 96,0x00},
4256 { 97,0x00},
4257 { 98,0x00},
4258 { 99,0x00},
4259 {100,0x10},
4260 {101,0x00},
4261 {102,0x00},
4262 {103,0x6A},
4263 {104,0x30},
4264 {105,0x0C},
4265 {106,0x40},
4266 {107,0x64},
4267 {108,0x1C},
4268 {109,0x0C},
4269 {110,0x60},
4270 {111,0x70},
4271 {112,0x30},
4272 {113,0x0C},
4273 {114,0x40},
4274 {115,0x6A},
4275 {116,0x1C},
4276 {117,0x0C},
4277 {118,0x60},
4278 {119,0x72},
4279 {120,0x00},
4280 {121,0x00},
4281 {122,0x00},
4282 {123,0x00},
4283 {124,0x10},
4284 {125,0x00},
4285 {126,0x00},
4286 {127,0x6F},
4287 { 0,0x11},
4288 { 8,0x40},
4289 { 9,0x00},
4290 { 10,0x20},
4291 { 11,0x6F},
4292 { 12,0x10},
4293 { 13,0x00},
4294 { 14,0x00},
4295 { 15,0x71},
4296 { 16,0x00},
4297 { 17,0x00},
4298 { 18,0x00},
4299 { 19,0x00},
4300 { 20,0x18},
4301 { 21,0x03},
4302 { 22,0x40},
4303 { 23,0x6F},
4304 { 24,0x44},
4305 { 25,0x00},
4306 { 26,0x80},
4307 { 27,0x02},
4308 { 28,0x18},
4309 { 29,0x03},
4310 { 30,0x40},
4311 { 31,0x71},
4312 { 32,0x44},
4313 { 33,0x00},
4314 { 34,0x00},
4315 { 35,0x02},
4316 { 36,0x00},
4317 { 37,0x00},
4318 { 38,0x00},
4319 { 39,0x00},
4320 { 40,0x00},
4321 { 41,0x00},
4322 { 42,0x00},
4323 { 43,0x00},
4324 { 44,0x59},
4325 { 45,0x00},
4326 { 46,0x00},
4327 { 47,0x71},
4328 { 48,0x59},
4329 { 49,0x00},
4330 { 50,0x00},
4331 { 51,0x72},
4332 { 52,0x00},
4333 { 53,0x00},
4334 { 54,0x00},
4335 { 55,0x00},
4336 { 56,0x00},
4337 { 57,0x00},
4338 { 58,0x00},
4339 { 59,0x00},
4340 { 60,0x44},
4341 { 61,0x00},
4342 { 62,0x60},
4343 { 63,0x0B},
4344 { 64,0x44},
4345 { 65,0x00},
4346 { 66,0x80},
4347 { 67,0x05},
4348 { 68,0x0C},
4349 { 69,0x00},
4350 { 70,0x80},
4351 { 71,0x03},
4352 { 72,0x58},
4353 { 73,0x60},
4354 { 74,0x00},
4355 { 75,0x2D},
4356 { 76,0x06},
4357 { 77,0x00},
4358 { 78,0x80},
4359 { 79,0x70},
4360 { 80,0x58},
4361 { 81,0x70},
4362 { 82,0x00},
4363 { 83,0x70},
4364 { 84,0x44},
4365 { 85,0x00},
4366 { 86,0x00},
4367 { 87,0x0B},
4368 { 88,0x0C},
4369 { 89,0x00},
4370 { 90,0x80},
4371 { 91,0x0D},
4372 { 92,0x58},
4373 { 93,0x60},
4374 { 94,0x00},
4375 { 95,0x73},
4376 { 96,0x06},
4377 { 97,0x00},
4378 { 98,0x80},
4379 { 99,0x70},
4380 {100,0x58},
4381 {101,0x70},
4382 {102,0x00},
4383 {103,0x70},
4384 {104,0x44},
4385 {105,0x00},
4386 {106,0x00},
4387 {107,0x06},
4388 {108,0x00},
4389 {109,0x00},
4390 {110,0x00},
4391 {111,0x00},
4392 {112,0x0C},
4393 {113,0x00},
4394 {114,0x80},
4395 {115,0x01},
4396 {116,0x58},
4397 {117,0x60},
4398 {118,0x00},
4399 {119,0x74},
4400 {120,0x06},
4401 {121,0x00},
4402 {122,0x80},
4403 {123,0x70},
4404 {124,0x58},
4405 {125,0x70},
4406 {126,0x00},
4407 {127,0x70},
4408 { 0,0x12},
4409 { 8,0x00},
4410 { 9,0x00},
4411 { 10,0x00},
4412 { 11,0x00},
4413 { 12,0x00},
4414 { 13,0x00},
4415 { 14,0x00},
4416 { 15,0x00},
4417 { 16,0x00},
4418 { 17,0x00},
4419 { 18,0x00},
4420 { 19,0x00},
4421 { 20,0x20},
4422 { 21,0x0E},
4423 { 22,0x00},
4424 { 23,0x01},
4425 { 24,0x58},
4426 { 25,0x60},
4427 { 26,0x00},
4428 { 27,0x70},
4429 { 28,0x59},
4430 { 29,0x00},
4431 { 30,0x00},
4432 { 31,0x67},
4433 { 32,0x59},
4434 { 33,0x00},
4435 { 34,0x00},
4436 { 35,0x68},
4437 { 36,0x58},
4438 { 37,0x70},
4439 { 38,0x00},
4440 { 39,0x68},
4441 { 40,0x00},
4442 { 41,0x00},
4443 { 42,0x00},
4444 { 43,0x00},
4445 { 44,0x44},
4446 { 45,0x00},
4447 { 46,0x80},
4448 { 47,0x0B},
4449 { 48,0x44},
4450 { 49,0x00},
4451 { 50,0x80},
4452 { 51,0x05},
4453 { 52,0x20},
4454 { 53,0x0E},
4455 { 54,0xA0},
4456 { 55,0x02},
4457 { 56,0x58},
4458 { 57,0x60},
4459 { 58,0x00},
4460 { 59,0x6A},
4461 { 60,0x58},
4462 { 61,0x60},
4463 { 62,0x00},
4464 { 63,0x66},
4465 { 64,0x58},
4466 { 65,0x60},
4467 { 66,0x00},
4468 { 67,0x2D},
4469 { 68,0x44},
4470 { 69,0x00},
4471 { 70,0x00},
4472 { 71,0x0B},
4473 { 72,0x20},
4474 { 73,0x0E},
4475 { 74,0xA0},
4476 { 75,0x02},
4477 { 76,0x58},
4478 { 77,0x60},
4479 { 78,0x00},
4480 { 79,0x6A},
4481 { 80,0x58},
4482 { 81,0x60},
4483 { 82,0x00},
4484 { 83,0x65},
4485 { 84,0x58},
4486 { 85,0x60},
4487 { 86,0x00},
4488 { 87,0x2D},
4489 { 88,0x44},
4490 { 89,0x00},
4491 { 90,0x00},
4492 { 91,0x06},
4493 { 92,0x58},
4494 { 93,0x60},
4495 { 94,0x00},
4496 { 95,0x70},
4497 { 96,0x58},
4498 { 97,0x70},
4499 { 98,0x00},
4500 { 99,0x67},
4501 {100,0x58},
4502 {101,0x60},
4503 {102,0x00},
4504 {103,0x69},
4505 {104,0x58},
4506 {105,0x60},
4507 {106,0x00},
4508 {107,0x64},
4509 {108,0x58},
4510 {109,0x60},
4511 {110,0x00},
4512 {111,0x2D},
4513 {112,0x20},
4514 {113,0x0E},
4515 {114,0xA0},
4516 {115,0x02},
4517 {116,0x4C},
4518 {117,0x0D},
4519 {118,0xE0},
4520 {119,0x76},
4521 {120,0x4C},
4522 {121,0x0E},
4523 {122,0xA0},
4524 {123,0x73},
4525 {124,0x59},
4526 {125,0x00},
4527 {126,0x00},
4528 {127,0x77},
4529 { 0,0x13},
4530 { 8,0x59},
4531 { 9,0x00},
4532 { 10,0x00},
4533 { 11,0x76},
4534 { 12,0x58},
4535 { 13,0x60},
4536 { 14,0x00},
4537 { 15,0x77},
4538 { 16,0x10},
4539 { 17,0x00},
4540 { 18,0xA0},
4541 { 19,0x75},
4542 { 20,0x44},
4543 { 21,0x00},
4544 { 22,0x60},
4545 { 23,0x05},
4546 { 24,0x44},
4547 { 25,0x00},
4548 { 26,0x80},
4549 { 27,0x06},
4550 { 28,0x00},
4551 { 29,0x00},
4552 { 30,0x00},
4553 { 31,0x00},
4554 { 32,0x00},
4555 { 33,0x00},
4556 { 34,0x00},
4557 { 35,0x00},
4558 { 36,0x00},
4559 { 37,0x00},
4560 { 38,0x00},
4561 { 39,0x00},
4562 { 40,0x44},
4563 { 41,0x00},
4564 { 42,0x00},
4565 { 43,0x06},
4566 { 44,0x58},
4567 { 45,0x60},
4568 { 46,0x00},
4569 { 47,0x76},
4570 { 48,0x44},
4571 { 49,0x00},
4572 { 50,0x00},
4573 { 51,0x01},
4574 { 52,0x00},
4575 { 53,0x00},
4576 { 54,0x00},
4577 { 55,0x00},
4578 { 56,0x00},
4579 { 57,0x00},
4580 { 58,0x00},
4581 { 59,0x00},
4582 { 60,0x00},
4583 { 61,0x00},
4584 { 62,0x00},
4585 { 63,0x00},
4586 { 64,0x10},
4587 { 65,0x00},
4588 { 66,0xA0},
4589 { 67,0x75},
4590 { 68,0x18},
4591 { 69,0x0F},
4592 { 70,0x00},
4593 { 71,0x75},
4594 { 72,0x64},
4595 { 73,0x00},
4596 { 74,0xC0},
4597 { 75,0x00},
4598 { 76,0x0C},
4599 { 77,0x07},
4600 { 78,0x40},
4601 { 79,0x02},
4602 { 80,0x64},
4603 { 81,0x30},
4604 { 82,0x20},
4605 { 83,0x79},
4606 { 84,0x00},
4607 { 85,0x00},
4608 { 86,0x00},
4609 { 87,0x00},
4610 { 88,0x00},
4611 { 89,0x00},
4612 { 90,0x00},
4613 { 91,0x00},
4614 { 92,0x58},
4615 { 93,0x60},
4616 { 94,0x00},
4617 { 95,0x7A},
4618 { 96,0x20},
4619 { 97,0x0F},
4620 { 98,0xC0},
4621 { 99,0x00},
4622 {100,0x58},
4623 {101,0x60},
4624 {102,0x00},
4625 {103,0x7B},
4626 {104,0x38},
4627 {105,0x0F},
4628 {106,0xC0},
4629 {107,0x76},
4630 {108,0x58},
4631 {109,0x60},
4632 {110,0x00},
4633 {111,0x7C},
4634 {112,0x38},
4635 {113,0x0F},
4636 {114,0xC0},
4637 {115,0x76},
4638 {116,0x58},
4639 {117,0x60},
4640 {118,0x00},
4641 {119,0x7D},
4642 {120,0x38},
4643 {121,0x0F},
4644 {122,0xC0},
4645 {123,0x76},
4646 {124,0x64},
4647 {125,0x03},
4648 {126,0x40},
4649 {127,0x00},
4650 { 0,0x14},
4651 { 8,0x64},
4652 { 9,0x20},
4653 { 10,0x60},
4654 { 11,0x00},
4655 { 12,0x00},
4656 { 13,0x00},
4657 { 14,0x00},
4658 { 15,0x00},
4659 { 16,0x00},
4660 { 17,0x00},
4661 { 18,0x00},
4662 { 19,0x00},
4663 { 20,0x00},
4664 { 21,0x00},
4665 { 22,0x00},
4666 { 23,0x00},
4667 { 24,0x10},
4668 { 25,0x00},
4669 { 26,0x00},
4670 { 27,0x76},
4671 { 28,0x18},
4672 { 29,0x03},
4673 { 30,0x40},
4674 { 31,0x73},
4675 { 32,0x18},
4676 { 33,0x03},
4677 { 34,0x40},
4678 { 35,0x76},
4679 { 36,0x58},
4680 { 37,0x60},
4681 { 38,0x00},
4682 { 39,0x1A},
4683 { 40,0x18},
4684 { 41,0x0C},
4685 { 42,0x00},
4686 { 43,0x7A},
4687 { 44,0x44},
4688 { 45,0x00},
4689 { 46,0xC0},
4690 { 47,0x03},
4691 { 48,0x10},
4692 { 49,0x00},
4693 { 50,0x20},
4694 { 51,0x78},
4695 { 52,0x10},
4696 { 53,0x13},
4697 { 54,0x60},
4698 { 55,0x77},
4699 { 56,0x44},
4700 { 57,0x00},
4701 { 58,0x00},
4702 { 59,0x03},
4703 { 60,0x10},
4704 { 61,0x00},
4705 { 62,0x20},
4706 { 63,0x77},
4707 { 64,0x10},
4708 { 65,0x13},
4709 { 66,0x60},
4710 { 67,0x78},
4711 { 68,0x00},
4712 { 69,0x00},
4713 { 70,0x00},
4714 { 71,0x00},
4715 { 72,0x40},
4716 { 73,0x03},
4717 { 74,0x40},
4718 { 75,0x77},
4719 { 76,0x18},
4720 { 77,0x0D},
4721 { 78,0x80},
4722 { 79,0x7A},
4723 { 80,0x1C},
4724 { 81,0x0D},
4725 { 82,0x60},
4726 { 83,0x77},
4727 { 84,0x18},
4728 { 85,0x0D},
4729 { 86,0xC0},
4730 { 87,0x7A},
4731 { 88,0x1C},
4732 { 89,0x0D},
4733 { 90,0xA0},
4734 { 91,0x77},
4735 { 92,0x44},
4736 { 93,0x00},
4737 { 94,0x60},
4738 { 95,0x03},
4739 { 96,0x10},
4740 { 97,0x00},
4741 { 98,0x00},
4742 { 99,0x79},
4743 {100,0x18},
4744 {101,0x0C},
4745 {102,0x00},
4746 {103,0x7C},
4747 {104,0x44},
4748 {105,0x00},
4749 {106,0x00},
4750 {107,0x03},
4751 {108,0x00},
4752 {109,0x00},
4753 {110,0x00},
4754 {111,0x00},
4755 {112,0x18},
4756 {113,0x0C},
4757 {114,0x00},
4758 {115,0x7C},
4759 {116,0x10},
4760 {117,0x00},
4761 {118,0x00},
4762 {119,0x79},
4763 {120,0x40},
4764 {121,0x03},
4765 {122,0x40},
4766 {123,0x78},
4767 {124,0x64},
4768 {125,0x50},
4769 {126,0x00},
4770 {127,0x79},
4771 { 0,0x15},
4772 { 8,0x00},
4773 { 9,0x00},
4774 { 10,0x00},
4775 { 11,0x00},
4776 { 12,0x00},
4777 { 13,0x00},
4778 { 14,0x00},
4779 { 15,0x00},
4780 { 16,0x44},
4781 { 17,0x00},
4782 { 18,0x60},
4783 { 19,0x03},
4784 { 20,0x18},
4785 { 21,0x0D},
4786 { 22,0xC0},
4787 { 23,0x7C},
4788 { 24,0x1C},
4789 { 25,0x0D},
4790 { 26,0xA0},
4791 { 27,0x78},
4792 { 28,0x44},
4793 { 29,0x00},
4794 { 30,0x00},
4795 { 31,0x03},
4796 { 32,0x18},
4797 { 33,0x0D},
4798 { 34,0x80},
4799 { 35,0x7C},
4800 { 36,0x1C},
4801 { 37,0x0D},
4802 { 38,0x60},
4803 { 39,0x78},
4804 { 40,0x00},
4805 { 41,0x00},
4806 { 42,0x00},
4807 { 43,0x00},
4808 { 44,0x00},
4809 { 45,0x00},
4810 { 46,0x00},
4811 { 47,0x00},
4812 { 48,0x00},
4813 { 49,0x00},
4814 { 50,0x00},
4815 { 51,0x00},
4816 { 52,0x10},
4817 { 53,0x00},
4818 { 54,0x00},
4819 { 55,0x7B},
4820 { 56,0x20},
4821 { 57,0x10},
4822 { 58,0x00},
4823 { 59,0x00},
4824 { 60,0x64},
4825 { 61,0x40},
4826 { 62,0x80},
4827 { 63,0x64},
4828 { 64,0x64},
4829 { 65,0x40},
4830 { 66,0x80},
4831 { 67,0x6A},
4832 { 68,0x24},
4833 { 69,0x10},
4834 { 70,0x00},
4835 { 71,0x08},
4836 { 72,0x24},
4837 { 73,0x10},
4838 { 74,0x00},
4839 { 75,0x08},
4840 { 76,0x00},
4841 { 77,0x00},
4842 { 78,0x00},
4843 { 79,0x00},
4844 { 80,0x00},
4845 { 81,0x00},
4846 { 82,0x00},
4847 { 83,0x00},
4848 { 84,0x10},
4849 { 85,0x01},
4850 { 86,0x00},
4851 { 87,0x6D},
4852 { 88,0x10},
4853 { 89,0x01},
4854 { 90,0x00},
4855 { 91,0x6E},
4856 { 92,0x58},
4857 { 93,0x60},
4858 { 94,0x00},
4859 { 95,0x00},
4860 { 96,0x59},
4861 { 97,0x00},
4862 { 98,0x00},
4863 { 99,0x5F},
4864 {100,0x58},
4865 {101,0x70},
4866 {102,0x00},
4867 {103,0x00},
4868 {104,0x59},
4869 {105,0x00},
4870 {106,0x00},
4871 {107,0x5F},
4872 {108,0x00},
4873 {109,0x00},
4874 {110,0x00},
4875 {111,0x00},
4876 {112,0x44},
4877 {113,0x00},
4878 {114,0x40},
4879 {115,0x05},
4880 {116,0x00},
4881 {117,0x00},
4882 {118,0x00},
4883 {119,0x00},
4884 {120,0x44},
4885 {121,0x00},
4886 {122,0x40},
4887 {123,0x08},
4888 {124,0x58},
4889 {125,0x60},
4890 {126,0x00},
4891 {127,0x2D},
4892 { 0,0x16},
4893 { 8,0x00},
4894 { 9,0x00},
4895 { 10,0x00},
4896 { 11,0x00},
4897 { 12,0x44},
4898 { 13,0x00},
4899 { 14,0x00},
4900 { 15,0x08},
4901 { 16,0x00},
4902 { 17,0x00},
4903 { 18,0x00},
4904 { 19,0x00},
4905 { 20,0x00},
4906 { 21,0x00},
4907 { 22,0x00},
4908 { 23,0x00},
4909 { 24,0x18},
4910 { 25,0x03},
4911 { 26,0x40},
4912 { 27,0x5F},
4913 { 28,0x18},
4914 { 29,0x03},
4915 { 30,0x40},
4916 { 31,0x60},
4917 { 32,0x44},
4918 { 33,0x00},
4919 { 34,0x00},
4920 { 35,0x03},
4921 { 36,0x18},
4922 { 37,0x03},
4923 { 38,0x40},
4924 { 39,0x6D},
4925 { 40,0x18},
4926 { 41,0x03},
4927 { 42,0x40},
4928 { 43,0x6E},
4929 { 44,0x44},
4930 { 45,0x00},
4931 { 46,0x00},
4932 { 47,0x00},
4933 { 48,0x00},
4934 { 49,0x00},
4935 { 50,0x00},
4936 { 51,0x00},
4937 { 52,0x10},
4938 { 53,0x00},
4939 { 54,0x20},
4940 { 55,0x7D},
4941 { 56,0x10},
4942 { 57,0x00},
4943 { 58,0x20},
4944 { 59,0x7E},
4945 { 60,0x18},
4946 { 61,0x03},
4947 { 62,0x40},
4948 { 63,0x7D},
4949 { 64,0x18},
4950 { 65,0x03},
4951 { 66,0x40},
4952 { 67,0x7E},
4953 { 68,0x18},
4954 { 69,0x00},
4955 { 70,0x60},
4956 { 71,0x82},
4957 { 72,0x1C},
4958 { 73,0x00},
4959 { 74,0x80},
4960 { 75,0x84},
4961 { 76,0x10},
4962 { 77,0x00},
4963 { 78,0x20},
4964 { 79,0x81},
4965 { 80,0x10},
4966 { 81,0x00},
4967 { 82,0x20},
4968 { 83,0xBF},
4969 { 84,0x1C},
4970 { 85,0x00},
4971 { 86,0x40},
4972 { 87,0x81},
4973 { 88,0x18},
4974 { 89,0x00},
4975 { 90,0x60},
4976 { 91,0xC0},
4977 { 92,0x1C},
4978 { 93,0x00},
4979 { 94,0x80},
4980 { 95,0xC4},
4981 { 96,0x1C},
4982 { 97,0x00},
4983 { 98,0x40},
4984 { 99,0xBF},
4985 {100,0x10},
4986 {101,0x30},
4987 {102,0x00},
4988 {103,0x83},
4989 {104,0x00},
4990 {105,0x00},
4991 {106,0x00},
4992 {107,0x00},
4993 {108,0x00},
4994 {109,0x00},
4995 {110,0x00},
4996 {111,0x00},
4997 {112,0x10},
4998 {113,0x30},
4999 {114,0x00},
5000 {115,0xC3},
5001 {116,0x18},
5002 {117,0x10},
5003 {118,0x20},
5004 {119,0xA8},
5005 {120,0x1C},
5006 {121,0x10},
5007 {122,0x40},
5008 {123,0x85},
5009 {124,0x1C},
5010 {125,0x10},
5011 {126,0x20},
5012 {127,0x83},
5013 { 0,0x17},
5014 { 8,0x1C},
5015 { 9,0x10},
5016 { 10,0x40},
5017 { 11,0xA6},
5018 { 12,0x1C},
5019 { 13,0x10},
5020 { 14,0x60},
5021 { 15,0x87},
5022 { 16,0x1C},
5023 { 17,0x10},
5024 { 18,0x60},
5025 { 19,0xA4},
5026 { 20,0x1C},
5027 { 21,0x10},
5028 { 22,0x80},
5029 { 23,0x89},
5030 { 24,0x1C},
5031 { 25,0x10},
5032 { 26,0x80},
5033 { 27,0xA2},
5034 { 28,0x1C},
5035 { 29,0x10},
5036 { 30,0xA0},
5037 { 31,0x8F},
5038 { 32,0x1C},
5039 { 33,0x10},
5040 { 34,0xA0},
5041 { 35,0x9C},
5042 { 36,0x1C},
5043 { 37,0x10},
5044 { 38,0xC0},
5045 { 39,0x8B},
5046 { 40,0x1C},
5047 { 41,0x10},
5048 { 42,0xC0},
5049 { 43,0xA0},
5050 { 44,0x1C},
5051 { 45,0x10},
5052 { 46,0xE0},
5053 { 47,0x8D},
5054 { 48,0x1C},
5055 { 49,0x10},
5056 { 50,0xE0},
5057 { 51,0x9E},
5058 { 52,0x1C},
5059 { 53,0x11},
5060 { 54,0x00},
5061 { 55,0x91},
5062 { 56,0x1C},
5063 { 57,0x11},
5064 { 58,0x00},
5065 { 59,0x9A},
5066 { 60,0x1C},
5067 { 61,0x11},
5068 { 62,0x20},
5069 { 63,0x93},
5070 { 64,0x1C},
5071 { 65,0x11},
5072 { 66,0x20},
5073 { 67,0x98},
5074 { 68,0x1C},
5075 { 69,0x11},
5076 { 70,0x40},
5077 { 71,0x84},
5078 { 72,0x1C},
5079 { 73,0x11},
5080 { 74,0x40},
5081 { 75,0xA7},
5082 { 76,0x1C},
5083 { 77,0x11},
5084 { 78,0x60},
5085 { 79,0x8C},
5086 { 80,0x1C},
5087 { 81,0x11},
5088 { 82,0x60},
5089 { 83,0x9F},
5090 { 84,0x1C},
5091 { 85,0x11},
5092 { 86,0x80},
5093 { 87,0x88},
5094 { 88,0x1C},
5095 { 89,0x11},
5096 { 90,0x80},
5097 { 91,0xA3},
5098 { 92,0x1C},
5099 { 93,0x11},
5100 { 94,0xA0},
5101 { 95,0x90},
5102 { 96,0x1C},
5103 { 97,0x11},
5104 { 98,0xA0},
5105 { 99,0x9B},
5106 {100,0x1C},
5107 {101,0x11},
5108 {102,0xC0},
5109 {103,0x8A},
5110 {104,0x1C},
5111 {105,0x11},
5112 {106,0xC0},
5113 {107,0xA1},
5114 {108,0x1C},
5115 {109,0x11},
5116 {110,0xE0},
5117 {111,0x86},
5118 {112,0x1C},
5119 {113,0x11},
5120 {114,0xE0},
5121 {115,0xA5},
5122 {116,0x1C},
5123 {117,0x12},
5124 {118,0x00},
5125 {119,0x8E},
5126 {120,0x1C},
5127 {121,0x12},
5128 {122,0x00},
5129 {123,0x9D},
5130 {124,0x1C},
5131 {125,0x12},
5132 {126,0x20},
5133 {127,0x92},
5134 { 0,0x18},
5135 { 8,0x1C},
5136 { 9,0x12},
5137 { 10,0x20},
5138 { 11,0x99},
5139 { 12,0x1C},
5140 { 13,0x12},
5141 { 14,0x40},
5142 { 15,0x94},
5143 { 16,0x1C},
5144 { 17,0x12},
5145 { 18,0x40},
5146 { 19,0x97},
5147 { 20,0x1C},
5148 { 21,0x12},
5149 { 22,0x60},
5150 { 23,0x95},
5151 { 24,0x1C},
5152 { 25,0x12},
5153 { 26,0x60},
5154 { 27,0x96},
5155 { 28,0x00},
5156 { 29,0x00},
5157 { 30,0x00},
5158 { 31,0x00},
5159 { 32,0x00},
5160 { 33,0x00},
5161 { 34,0x00},
5162 { 35,0x00},
5163 { 36,0x00},
5164 { 37,0x00},
5165 { 38,0x00},
5166 { 39,0x00},
5167 { 40,0x10},
5168 { 41,0x00},
5169 { 42,0x00},
5170 { 43,0xAD},
5171 { 44,0x18},
5172 { 45,0x10},
5173 { 46,0x20},
5174 { 47,0xE8},
5175 { 48,0x1C},
5176 { 49,0x10},
5177 { 50,0x40},
5178 { 51,0xC5},
5179 { 52,0x1C},
5180 { 53,0x10},
5181 { 54,0x20},
5182 { 55,0xC3},
5183 { 56,0x1C},
5184 { 57,0x10},
5185 { 58,0x40},
5186 { 59,0xE6},
5187 { 60,0x1C},
5188 { 61,0x10},
5189 { 62,0x60},
5190 { 63,0xC7},
5191 { 64,0x1C},
5192 { 65,0x10},
5193 { 66,0x60},
5194 { 67,0xE4},
5195 { 68,0x1C},
5196 { 69,0x10},
5197 { 70,0x80},
5198 { 71,0xC9},
5199 { 72,0x1C},
5200 { 73,0x10},
5201 { 74,0x80},
5202 { 75,0xE2},
5203 { 76,0x1C},
5204 { 77,0x10},
5205 { 78,0xA0},
5206 { 79,0xCF},
5207 { 80,0x1C},
5208 { 81,0x10},
5209 { 82,0xA0},
5210 { 83,0xDC},
5211 { 84,0x1C},
5212 { 85,0x10},
5213 { 86,0xC0},
5214 { 87,0xCB},
5215 { 88,0x1C},
5216 { 89,0x10},
5217 { 90,0xC0},
5218 { 91,0xE0},
5219 { 92,0x1C},
5220 { 93,0x10},
5221 { 94,0xE0},
5222 { 95,0xCD},
5223 { 96,0x1C},
5224 { 97,0x10},
5225 { 98,0xE0},
5226 { 99,0xDE},
5227 {100,0x1C},
5228 {101,0x11},
5229 {102,0x00},
5230 {103,0xD1},
5231 {104,0x1C},
5232 {105,0x11},
5233 {106,0x00},
5234 {107,0xDA},
5235 {108,0x1C},
5236 {109,0x11},
5237 {110,0x20},
5238 {111,0xD3},
5239 {112,0x1C},
5240 {113,0x11},
5241 {114,0x20},
5242 {115,0xD8},
5243 {116,0x1C},
5244 {117,0x11},
5245 {118,0x40},
5246 {119,0xC4},
5247 {120,0x1C},
5248 {121,0x11},
5249 {122,0x40},
5250 {123,0xE7},
5251 {124,0x1C},
5252 {125,0x11},
5253 {126,0x60},
5254 {127,0xCC},
5255 { 0,0x19},
5256 { 8,0x1C},
5257 { 9,0x11},
5258 { 10,0x60},
5259 { 11,0xDF},
5260 { 12,0x1C},
5261 { 13,0x11},
5262 { 14,0x80},
5263 { 15,0xC8},
5264 { 16,0x1C},
5265 { 17,0x11},
5266 { 18,0x80},
5267 { 19,0xE3},
5268 { 20,0x1C},
5269 { 21,0x11},
5270 { 22,0xA0},
5271 { 23,0xD0},
5272 { 24,0x1C},
5273 { 25,0x11},
5274 { 26,0xA0},
5275 { 27,0xDB},
5276 { 28,0x1C},
5277 { 29,0x11},
5278 { 30,0xC0},
5279 { 31,0xCA},
5280 { 32,0x1C},
5281 { 33,0x11},
5282 { 34,0xC0},
5283 { 35,0xE1},
5284 { 36,0x1C},
5285 { 37,0x11},
5286 { 38,0xE0},
5287 { 39,0xC6},
5288 { 40,0x1C},
5289 { 41,0x11},
5290 { 42,0xE0},
5291 { 43,0xE5},
5292 { 44,0x1C},
5293 { 45,0x12},
5294 { 46,0x00},
5295 { 47,0xCE},
5296 { 48,0x1C},
5297 { 49,0x12},
5298 { 50,0x00},
5299 { 51,0xDD},
5300 { 52,0x1C},
5301 { 53,0x12},
5302 { 54,0x20},
5303 { 55,0xD2},
5304 { 56,0x1C},
5305 { 57,0x12},
5306 { 58,0x20},
5307 { 59,0xD9},
5308 { 60,0x1C},
5309 { 61,0x12},
5310 { 62,0x40},
5311 { 63,0xD4},
5312 { 64,0x1C},
5313 { 65,0x12},
5314 { 66,0x40},
5315 { 67,0xD7},
5316 { 68,0x1C},
5317 { 69,0x12},
5318 { 70,0x60},
5319 { 71,0xD5},
5320 { 72,0x1C},
5321 { 73,0x12},
5322 { 74,0x60},
5323 { 75,0xD6},
5324 { 76,0x00},
5325 { 77,0x00},
5326 { 78,0x00},
5327 { 79,0x00},
5328 { 80,0x00},
5329 { 81,0x00},
5330 { 82,0x00},
5331 { 83,0x00},
5332 { 84,0x00},
5333 { 85,0x00},
5334 { 86,0x00},
5335 { 87,0x00},
5336 { 88,0x10},
5337 { 89,0x00},
5338 { 90,0x00},
5339 { 91,0xED},
5340 { 92,0x18},
5341 { 93,0x12},
5342 { 94,0xA0},
5343 { 95,0xEC},
5344 { 96,0x1C},
5345 { 97,0x12},
5346 { 98,0xC0},
5347 { 99,0xEE},
5348 {100,0x1C},
5349 {101,0x12},
5350 {102,0xC0},
5351 {103,0xEB},
5352 {104,0x1C},
5353 {105,0x12},
5354 {106,0xA0},
5355 {107,0xED},
5356 {108,0x1C},
5357 {109,0x12},
5358 {110,0xE0},
5359 {111,0xEA},
5360 {112,0x1C},
5361 {113,0x12},
5362 {114,0xE0},
5363 {115,0xEF},
5364 {116,0x1C},
5365 {117,0x13},
5366 {118,0x00},
5367 {119,0xE9},
5368 {120,0x1C},
5369 {121,0x13},
5370 {122,0x00},
5371 {123,0xF0},
5372 {124,0x18},
5373 {125,0x13},
5374 {126,0x60},
5375 {127,0xF1},
5376 { 0,0x1A},
5377 { 8,0x1C},
5378 { 9,0x13},
5379 { 10,0x60},
5380 { 11,0xF3},
5381 { 12,0x1C},
5382 { 13,0x13},
5383 { 14,0x40},
5384 { 15,0xF6},
5385 { 16,0x4C},
5386 { 17,0x13},
5387 { 18,0x40},
5388 { 19,0xF4},
5389 { 20,0x00},
5390 { 21,0x00},
5391 { 22,0x00},
5392 { 23,0x00},
5393 { 24,0x5C},
5394 { 25,0x90},
5395 { 26,0x60},
5396 { 27,0x03},
5397 { 28,0x18},
5398 { 29,0x12},
5399 { 30,0xA0},
5400 { 31,0xAC},
5401 { 32,0x1C},
5402 { 33,0x12},
5403 { 34,0xA0},
5404 { 35,0xAD},
5405 { 36,0x1C},
5406 { 37,0x12},
5407 { 38,0xC0},
5408 { 39,0xAE},
5409 { 40,0x10},
5410 { 41,0x00},
5411 { 42,0x40},
5412 { 43,0xFD},
5413 { 44,0x1C},
5414 { 45,0x12},
5415 { 46,0xC0},
5416 { 47,0xAB},
5417 { 48,0x1C},
5418 { 49,0x12},
5419 { 50,0xE0},
5420 { 51,0xAA},
5421 { 52,0x1C},
5422 { 53,0x12},
5423 { 54,0xE0},
5424 { 55,0xAF},
5425 { 56,0x1C},
5426 { 57,0x13},
5427 { 58,0x00},
5428 { 59,0xA9},
5429 { 60,0x1C},
5430 { 61,0x13},
5431 { 62,0x00},
5432 { 63,0xB0},
5433 { 64,0x18},
5434 { 65,0x13},
5435 { 66,0x60},
5436 { 67,0xB1},
5437 { 68,0x1C},
5438 { 69,0x13},
5439 { 70,0x60},
5440 { 71,0xB3},
5441 { 72,0x1C},
5442 { 73,0x13},
5443 { 74,0x40},
5444 { 75,0xB6},
5445 { 76,0x4C},
5446 { 77,0x13},
5447 { 78,0x40},
5448 { 79,0xB4},
5449 { 80,0x00},
5450 { 81,0x00},
5451 { 82,0x00},
5452 { 83,0x00},
5453 { 84,0x5C},
5454 { 85,0x90},
5455 { 86,0x40},
5456 { 87,0x03},
5457 { 88,0x00},
5458 { 89,0x00},
5459 { 90,0x00},
5460 { 91,0x00},
5461 { 92,0x00},
5462 { 93,0x00},
5463 { 94,0x00},
5464 { 95,0x00},
5465 { 96,0x00},
5466 { 97,0x00},
5467 { 98,0x00},
5468 { 99,0x00},
5469 {100,0x10},
5470 {101,0x00},
5471 {102,0x40},
5472 {103,0xBD},
5473 {104,0x18},
5474 {105,0x13},
5475 {106,0x80},
5476 {107,0xF4},
5477 {108,0x1C},
5478 {109,0x13},
5479 {110,0x80},
5480 {111,0xF3},
5481 {112,0x1C},
5482 {113,0x13},
5483 {114,0xA0},
5484 {115,0xF1},
5485 {116,0x00},
5486 {117,0x00},
5487 {118,0x00},
5488 {119,0x00},
5489 {120,0x5C},
5490 {121,0x90},
5491 {122,0x60},
5492 {123,0x03},
5493 {124,0x18},
5494 {125,0x13},
5495 {126,0x80},
5496 {127,0xB4},
5497 { 0,0x1B},
5498 { 8,0x1C},
5499 { 9,0x13},
5500 { 10,0x80},
5501 { 11,0xB3},
5502 { 12,0x1C},
5503 { 13,0x13},
5504 { 14,0xA0},
5505 { 15,0xB1},
5506 { 16,0x10},
5507 { 17,0x00},
5508 { 18,0x40},
5509 { 19,0xFC},
5510 { 20,0x18},
5511 { 21,0x13},
5512 { 22,0x20},
5513 { 23,0xEA},
5514 { 24,0x5C},
5515 { 25,0x90},
5516 { 26,0x40},
5517 { 27,0x03},
5518 { 28,0x18},
5519 { 29,0x13},
5520 { 30,0x40},
5521 { 31,0xF3},
5522 { 32,0x1C},
5523 { 33,0x13},
5524 { 34,0x60},
5525 { 35,0xF4},
5526 { 36,0x4C},
5527 { 37,0x13},
5528 { 38,0x40},
5529 { 39,0xF5},
5530 { 40,0x10},
5531 { 41,0x00},
5532 { 42,0x40},
5533 { 43,0xBC},
5534 { 44,0x1C},
5535 { 45,0x13},
5536 { 46,0x60},
5537 { 47,0xF1},
5538 { 48,0x18},
5539 { 49,0x13},
5540 { 50,0x20},
5541 { 51,0xAA},
5542 { 52,0x5C},
5543 { 53,0x90},
5544 { 54,0x60},
5545 { 55,0x03},
5546 { 56,0x18},
5547 { 57,0x13},
5548 { 58,0x40},
5549 { 59,0xB3},
5550 { 60,0x1C},
5551 { 61,0x13},
5552 { 62,0x60},
5553 { 63,0xB4},
5554 { 64,0x4C},
5555 { 65,0x13},
5556 { 66,0x40},
5557 { 67,0xB5},
5558 { 68,0x10},
5559 { 69,0x00},
5560 { 70,0x40},
5561 { 71,0xFB},
5562 { 72,0x1C},
5563 { 73,0x13},
5564 { 74,0x60},
5565 { 75,0xB1},
5566 { 76,0x00},
5567 { 77,0x00},
5568 { 78,0x00},
5569 { 79,0x00},
5570 { 80,0x5C},
5571 { 81,0x90},
5572 { 82,0x40},
5573 { 83,0x03},
5574 { 84,0x18},
5575 { 85,0x13},
5576 { 86,0x80},
5577 { 87,0xF5},
5578 { 88,0x1C},
5579 { 89,0x13},
5580 { 90,0x80},
5581 { 91,0xF1},
5582 { 92,0x1C},
5583 { 93,0x13},
5584 { 94,0xA0},
5585 { 95,0xF4},
5586 { 96,0x10},
5587 { 97,0x00},
5588 { 98,0x40},
5589 { 99,0xBB},
5590 {100,0x5C},
5591 {101,0x90},
5592 {102,0x60},
5593 {103,0x03},
5594 {104,0x00},
5595 {105,0x00},
5596 {106,0x00},
5597 {107,0x00},
5598 {108,0x00},
5599 {109,0x00},
5600 {110,0x00},
5601 {111,0x00},
5602 {112,0x00},
5603 {113,0x00},
5604 {114,0x00},
5605 {115,0x00},
5606 {116,0x10},
5607 {117,0x00},
5608 {118,0x40},
5609 {119,0xFA},
5610 {120,0x18},
5611 {121,0x13},
5612 {122,0x80},
5613 {123,0xB5},
5614 {124,0x1C},
5615 {125,0x13},
5616 {126,0x80},
5617 {127,0xB1},
5618 { 0,0x1C},
5619 { 8,0x1C},
5620 { 9,0x13},
5621 { 10,0xA0},
5622 { 11,0xB4},
5623 { 12,0x18},
5624 { 13,0x12},
5625 { 14,0x80},
5626 { 15,0xD5},
5627 { 16,0x5C},
5628 { 17,0x90},
5629 { 18,0x40},
5630 { 19,0x03},
5631 { 20,0x18},
5632 { 21,0x12},
5633 { 22,0xA0},
5634 { 23,0xF0},
5635 { 24,0x1C},
5636 { 25,0x12},
5637 { 26,0xC0},
5638 { 27,0xE9},
5639 { 28,0x4C},
5640 { 29,0x12},
5641 { 30,0xA0},
5642 { 31,0xE8},
5643 { 32,0x10},
5644 { 33,0x00},
5645 { 34,0x40},
5646 { 35,0xBA},
5647 { 36,0x1C},
5648 { 37,0x12},
5649 { 38,0xC0},
5650 { 39,0xEF},
5651 { 40,0x1C},
5652 { 41,0x12},
5653 { 42,0xE0},
5654 { 43,0xEE},
5655 { 44,0x1C},
5656 { 45,0x12},
5657 { 46,0xE0},
5658 { 47,0xEA},
5659 { 48,0x1C},
5660 { 49,0x13},
5661 { 50,0x00},
5662 { 51,0xED},
5663 { 52,0x1C},
5664 { 53,0x13},
5665 { 54,0x00},
5666 { 55,0xEB},
5667 { 56,0x18},
5668 { 57,0x13},
5669 { 58,0x60},
5670 { 59,0xF5},
5671 { 60,0x1C},
5672 { 61,0x13},
5673 { 62,0x60},
5674 { 63,0xF4},
5675 { 64,0x1C},
5676 { 65,0x13},
5677 { 66,0x40},
5678 { 67,0xF1},
5679 { 68,0x4C},
5680 { 69,0x13},
5681 { 70,0x40},
5682 { 71,0xF2},
5683 { 72,0x18},
5684 { 73,0x12},
5685 { 74,0x80},
5686 { 75,0x95},
5687 { 76,0x5C},
5688 { 77,0x90},
5689 { 78,0x60},
5690 { 79,0x03},
5691 { 80,0x18},
5692 { 81,0x12},
5693 { 82,0xA0},
5694 { 83,0xB0},
5695 { 84,0x1C},
5696 { 85,0x12},
5697 { 86,0xC0},
5698 { 87,0xA9},
5699 { 88,0x4C},
5700 { 89,0x12},
5701 { 90,0xA0},
5702 { 91,0xA8},
5703 { 92,0x10},
5704 { 93,0x00},
5705 { 94,0x40},
5706 { 95,0xF9},
5707 { 96,0x1C},
5708 { 97,0x12},
5709 { 98,0xC0},
5710 { 99,0xAF},
5711 {100,0x1C},
5712 {101,0x12},
5713 {102,0xE0},
5714 {103,0xAE},
5715 {104,0x1C},
5716 {105,0x12},
5717 {106,0xE0},
5718 {107,0xAA},
5719 {108,0x1C},
5720 {109,0x13},
5721 {110,0x00},
5722 {111,0xAD},
5723 {112,0x1C},
5724 {113,0x13},
5725 {114,0x00},
5726 {115,0xAB},
5727 {116,0x18},
5728 {117,0x13},
5729 {118,0x60},
5730 {119,0xB5},
5731 {120,0x1C},
5732 {121,0x13},
5733 {122,0x60},
5734 {123,0xB4},
5735 {124,0x1C},
5736 {125,0x13},
5737 {126,0x40},
5738 {127,0xB1},
5739 { 0,0x1D},
5740 { 8,0x4C},
5741 { 9,0x13},
5742 { 10,0x40},
5743 { 11,0xB2},
5744 { 12,0x00},
5745 { 13,0x00},
5746 { 14,0x00},
5747 { 15,0x00},
5748 { 16,0x5C},
5749 { 17,0x90},
5750 { 18,0x40},
5751 { 19,0x03},
5752 { 20,0x00},
5753 { 21,0x00},
5754 { 22,0x00},
5755 { 23,0x00},
5756 { 24,0x00},
5757 { 25,0x00},
5758 { 26,0x00},
5759 { 27,0x00},
5760 { 28,0x00},
5761 { 29,0x00},
5762 { 30,0x00},
5763 { 31,0x00},
5764 { 32,0x10},
5765 { 33,0x00},
5766 { 34,0x40},
5767 { 35,0xB8},
5768 { 36,0x18},
5769 { 37,0x13},
5770 { 38,0x80},
5771 { 39,0xF2},
5772 { 40,0x1C},
5773 { 41,0x13},
5774 { 42,0x80},
5775 { 43,0xF4},
5776 { 44,0x1C},
5777 { 45,0x13},
5778 { 46,0xA0},
5779 { 47,0xF5},
5780 { 48,0x10},
5781 { 49,0x00},
5782 { 50,0x40},
5783 { 51,0xB9},
5784 { 52,0x00},
5785 { 53,0x00},
5786 { 54,0x00},
5787 { 55,0x00},
5788 { 56,0x5C},
5789 { 57,0x90},
5790 { 58,0x60},
5791 { 59,0x03},
5792 { 60,0x18},
5793 { 61,0x13},
5794 { 62,0x80},
5795 { 63,0xB2},
5796 { 64,0x1C},
5797 { 65,0x13},
5798 { 66,0x80},
5799 { 67,0xB4},
5800 { 68,0x1C},
5801 { 69,0x13},
5802 { 70,0xA0},
5803 { 71,0xB5},
5804 { 72,0x10},
5805 { 73,0x00},
5806 { 74,0x40},
5807 { 75,0xF8},
5808 { 76,0x18},
5809 { 77,0x13},
5810 { 78,0x20},
5811 { 79,0xEE},
5812 { 80,0x5C},
5813 { 81,0x90},
5814 { 82,0x40},
5815 { 83,0x03},
5816 { 84,0x18},
5817 { 85,0x13},
5818 { 86,0x40},
5819 { 87,0xF4},
5820 { 88,0x1C},
5821 { 89,0x13},
5822 { 90,0x60},
5823 { 91,0xF2},
5824 { 92,0x4C},
5825 { 93,0x13},
5826 { 94,0x40},
5827 { 95,0xF0},
5828 { 96,0x10},
5829 { 97,0x00},
5830 { 98,0x40},
5831 { 99,0xB8},
5832 {100,0x1C},
5833 {101,0x13},
5834 {102,0x60},
5835 {103,0xF5},
5836 {104,0x18},
5837 {105,0x13},
5838 {106,0x20},
5839 {107,0xAE},
5840 {108,0x5C},
5841 {109,0x90},
5842 {110,0x60},
5843 {111,0x03},
5844 {112,0x18},
5845 {113,0x13},
5846 {114,0x40},
5847 {115,0xB4},
5848 {116,0x1C},
5849 {117,0x13},
5850 {118,0x60},
5851 {119,0xB2},
5852 {120,0x4C},
5853 {121,0x13},
5854 {122,0x40},
5855 {123,0xB0},
5856 {124,0x10},
5857 {125,0x00},
5858 {126,0x40},
5859 {127,0xF7},
5860 { 0,0x1E},
5861 { 8,0x1C},
5862 { 9,0x13},
5863 { 10,0x60},
5864 { 11,0xB5},
5865 { 12,0x00},
5866 { 13,0x00},
5867 { 14,0x00},
5868 { 15,0x00},
5869 { 16,0x5C},
5870 { 17,0x90},
5871 { 18,0x40},
5872 { 19,0x03},
5873 { 20,0x18},
5874 { 21,0x13},
5875 { 22,0x80},
5876 { 23,0xF0},
5877 { 24,0x1C},
5878 { 25,0x13},
5879 { 26,0x80},
5880 { 27,0xF5},
5881 { 28,0x1C},
5882 { 29,0x13},
5883 { 30,0xA0},
5884 { 31,0xF2},
5885 { 32,0x10},
5886 { 33,0x00},
5887 { 34,0x40},
5888 { 35,0xB7},
5889 { 36,0x00},
5890 { 37,0x00},
5891 { 38,0x00},
5892 { 39,0x00},
5893 { 40,0x5C},
5894 { 41,0x90},
5895 { 42,0x60},
5896 { 43,0x03},
5897 { 44,0x18},
5898 { 45,0x13},
5899 { 46,0x80},
5900 { 47,0xB0},
5901 { 48,0x1C},
5902 { 49,0x13},
5903 { 50,0x80},
5904 { 51,0xB5},
5905 { 52,0x1C},
5906 { 53,0x13},
5907 { 54,0xA0},
5908 { 55,0xB2},
5909 { 56,0x10},
5910 { 57,0x00},
5911 { 58,0x40},
5912 { 59,0xF6},
5913 { 60,0x5C},
5914 { 61,0x90},
5915 { 62,0x40},
5916 { 63,0x03},
5917 { 64,0x00},
5918 { 65,0x00},
5919 { 66,0x00},
5920 { 67,0x00},
5921 { 68,0x00},
5922 { 69,0x00},
5923 { 70,0x00},
5924 { 71,0x00},
5925 { 72,0x00},
5926 { 73,0x00},
5927 { 74,0x00},
5928 { 75,0x00},
5929 { 76,0x10},
5930 { 77,0x00},
5931 { 78,0x40},
5932 { 79,0xB6},
5933 { 80,0x00},
5934 { 81,0x00},
5935 { 82,0x00},
5936 { 83,0x00},
5937 { 84,0x00},
5938 { 85,0x00},
5939 { 86,0x00},
5940 { 87,0x00},
5941 { 88,0x00},
5942 { 89,0x00},
5943 { 90,0x00},
5944 { 91,0x00},
5945 { 92,0x02},
5946 { 93,0x00},
5947 { 94,0x00},
5948 { 95,0x00},
5949 { 96,0x00},
5950 { 97,0x00},
5951 { 98,0x00},
5952 { 99,0x00},
5953};
5954
5955#define main44_miniDSP_D_reg_values_COEFF_START 0
5956#define main44_miniDSP_D_reg_values_COEFF_SIZE 672
5957#define main44_miniDSP_D_reg_values_INST_START 672
5958#define main44_miniDSP_D_reg_values_INST_SIZE 2124
5959
diff --git a/sound/soc/codecs/rt5639.c b/sound/soc/codecs/rt5639.c
new file mode 100644
index 00000000000..139503e0d32
--- /dev/null
+++ b/sound/soc/codecs/rt5639.c
@@ -0,0 +1,2444 @@
1/*
2 * rt5639.c -- RT5639 ALSA SoC audio codec driver
3 *
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/soc-dapm.h>
25#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "rt5639.h"
29
30#define RT5639_DEMO 1
31#define RT5639_REG_RW 1
32#define RT5639_DET_EXT_MIC 0
33
34#ifdef RT5639_DEMO
35struct rt5639_init_reg {
36 u8 reg;
37 u16 val;
38};
39
40static struct rt5639_init_reg init_list[] = {
41 {RT5639_DUMMY1 , 0x3701},//fa[12:13] = 1'b;fa[8~10]=1;fa[0]=1
42 {RT5639_DEPOP_M1 , 0x0019},//8e[4:3] = 11'b; 8e[0] = 1'b
43 {RT5639_DEPOP_M2 , 0x3100},//8f[13] = 1'b
44 {RT5639_ADDA_CLK1 , 0x1114},//73[2] = 1'b
45 {RT5639_MICBIAS , 0x3030},//93[5:4] = 11'b
46 {RT5639_PRIV_INDEX , 0x003d},//PR3d[12] = 1'b
47 {RT5639_PRIV_DATA , 0x3600},
48 {RT5639_CLS_D_OUT , 0xa000},//8d[11] = 0'b
49 {RT5639_PRIV_INDEX , 0x001c},//PR1c = 0D21'h
50 {RT5639_PRIV_DATA , 0x0D21},
51
52 {RT5639_PRIV_INDEX , 0x001b},//PR1B = 0D21'h
53 {RT5639_PRIV_DATA , 0x0000},
54 {RT5639_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
55 {RT5639_PRIV_DATA , 0x0aa8},
56 {RT5639_PRIV_INDEX , 0x0014},//PR14 = 0aaa'h
57 {RT5639_PRIV_DATA , 0x0aaa},
58 {RT5639_PRIV_INDEX , 0x0020},//PR20 = 6110'h
59 {RT5639_PRIV_DATA , 0x6110},
60 {RT5639_PRIV_INDEX , 0x0021},//PR21 = e0e0'h
61 {RT5639_PRIV_DATA , 0xe0e0},
62 {RT5639_PRIV_INDEX , 0x0023},//PR23 = 1804'h
63 {RT5639_PRIV_DATA , 0x1804},
64 /*playback*/
65 {RT5639_STO_DAC_MIXER , 0x1414},//Dig inf 1 -> Sto DAC mixer -> DACL
66 {RT5639_OUT_L3_MIXER , 0x01fe},//DACL1 -> OUTMIXL
67 {RT5639_OUT_R3_MIXER , 0x01fe},//DACR1 -> OUTMIXR
68 {RT5639_HP_VOL , 0x8888},//OUTMIX -> HPVOL
69 {RT5639_HPO_MIXER , 0xc000},//HPVOL -> HPOLMIX
70// {RT5639_HPO_MIXER , 0xa000},//DAC1 -> HPOLMIX
71 {RT5639_SPK_L_MIXER , 0x0036},//DACL1 -> SPKMIXL
72 {RT5639_SPK_R_MIXER , 0x0036},//DACR1 -> SPKMIXR
73 {RT5639_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
74 {RT5639_SPO_L_MIXER , 0xe800},//SPKVOLL -> SPOLMIX
75 {RT5639_SPO_R_MIXER , 0x2800},//SPKVOLR -> SPORMIX
76// {RT5639_SPO_L_MIXER , 0xb800},//DAC -> SPOLMIX
77// {RT5639_SPO_R_MIXER , 0x1800},//DAC -> SPORMIX
78// {RT5639_I2S1_SDP , 0xD000},//change IIS1 and IIS2
79 /*record*/
80 {RT5639_IN1_IN2 , 0x5080},//IN1 boost 40db and differential mode
81 {RT5639_IN3_IN4 , 0x0500},//IN2 boost 40db and signal ended mode
82 {RT5639_REC_L2_MIXER , 0x007d},//Mic1 -> RECMIXL
83 {RT5639_REC_R2_MIXER , 0x007d},//Mic1 -> RECMIXR
84// {RT5639_REC_L2_MIXER , 0x006f},//Mic2 -> RECMIXL
85// {RT5639_REC_R2_MIXER , 0x006f},//Mic2 -> RECMIXR
86 {RT5639_STO_ADC_MIXER , 0x3020},//ADC -> Sto ADC mixer
87
88#if RT5639_DET_EXT_MIC
89 {RT5639_MICBIAS ,0x3800},//enable MICBIAS short current
90 {RT5639_GPIO_CTRL1 ,0x8400},//set GPIO1 to IRQ
91 {RT5639_GPIO_CTRL3 ,0x0004},//set GPIO1 output
92 {RT5639_IRQ_CTRL2 ,0x8000},//set MICBIAS short current to IRQ ( if sticky set regBE : 8800 )
93#endif
94};
95#define RT5639_INIT_REG_LEN ARRAY_SIZE(init_list)
96
97static int rt5639_reg_init(struct snd_soc_codec *codec)
98{
99 int i;
100
101 for (i = 0; i < RT5639_INIT_REG_LEN; i++)
102 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
103
104 return 0;
105}
106#endif
107
108static const u16 rt5639_reg[RT5639_VENDOR_ID2 + 1] = {
109 [RT5639_RESET] = 0x0008,
110 [RT5639_SPK_VOL] = 0xc8c8,
111 [RT5639_HP_VOL] = 0xc8c8,
112 [RT5639_OUTPUT] = 0xc8c8,
113 [RT5639_MONO_OUT] = 0x8000,
114 [RT5639_INL_INR_VOL] = 0x0808,
115 [RT5639_DAC1_DIG_VOL] = 0xafaf,
116 [RT5639_DAC2_DIG_VOL] = 0xafaf,
117 [RT5639_ADC_DIG_VOL] = 0x2f2f,
118 [RT5639_ADC_DATA] = 0x2f2f,
119 [RT5639_STO_ADC_MIXER] = 0x7060,
120 [RT5639_MONO_ADC_MIXER] = 0x7070,
121 [RT5639_AD_DA_MIXER] = 0x8080,
122 [RT5639_STO_DAC_MIXER] = 0x5454,
123 [RT5639_MONO_DAC_MIXER] = 0x5454,
124 [RT5639_DIG_MIXER] = 0xaa00,
125 [RT5639_DSP_PATH2] = 0xa000,
126 [RT5639_REC_L2_MIXER] = 0x007f,
127 [RT5639_REC_R2_MIXER] = 0x007f,
128 [RT5639_HPO_MIXER] = 0xe000,
129 [RT5639_SPK_L_MIXER] = 0x003e,
130 [RT5639_SPK_R_MIXER] = 0x003e,
131 [RT5639_SPO_L_MIXER] = 0xf800,
132 [RT5639_SPO_R_MIXER] = 0x3800,
133 [RT5639_SPO_CLSD_RATIO] = 0x0004,
134 [RT5639_MONO_MIXER] = 0xfc00,
135 [RT5639_OUT_L3_MIXER] = 0x01ff,
136 [RT5639_OUT_R3_MIXER] = 0x01ff,
137 [RT5639_LOUT_MIXER] = 0xf000,
138 [RT5639_PWR_ANLG1] = 0x00c0,
139 [RT5639_I2S1_SDP] = 0x8000,
140 [RT5639_I2S2_SDP] = 0x8000,
141 [RT5639_I2S3_SDP] = 0x8000,
142 [RT5639_ADDA_CLK1] = 0x1110,
143 [RT5639_ADDA_CLK2] = 0x0c00,
144 [RT5639_DMIC] = 0x1d00,
145 [RT5639_ASRC_3] = 0x0008,
146 [RT5639_HP_OVCD] = 0x0600,
147 [RT5639_CLS_D_OVCD] = 0x0228,
148 [RT5639_CLS_D_OUT] = 0xa800,
149 [RT5639_DEPOP_M1] = 0x0004,
150 [RT5639_DEPOP_M2] = 0x1100,
151 [RT5639_DEPOP_M3] = 0x0646,
152 [RT5639_CHARGE_PUMP] = 0x0c00,
153 [RT5639_MICBIAS] = 0x3000,
154 [RT5639_EQ_CTRL1] = 0x2080,
155 [RT5639_DRC_AGC_1] = 0x2206,
156 [RT5639_DRC_AGC_2] = 0x1f00,
157 [RT5639_ANC_CTRL1] = 0x034b,
158 [RT5639_ANC_CTRL2] = 0x0066,
159 [RT5639_ANC_CTRL3] = 0x000b,
160 [RT5639_GPIO_CTRL1] = 0x0400,
161 [RT5639_DSP_CTRL3] = 0x2000,
162 [RT5639_BASE_BACK] = 0x0013,
163 [RT5639_MP3_PLUS1] = 0x0680,
164 [RT5639_MP3_PLUS2] = 0x1c17,
165 [RT5639_3D_HP] = 0x8c00,
166 [RT5639_ADJ_HPF] = 0x2a20,
167 [RT5639_HP_CALIB_AMP_DET] = 0x0400,
168 [RT5639_SV_ZCD1] = 0x0809,
169 [RT5639_VENDOR_ID1] = 0x10ec,
170 [RT5639_VENDOR_ID2] = 0x6231,
171};
172
173static int rt5639_reset(struct snd_soc_codec *codec)
174{
175 return snd_soc_write(codec, RT5639_RESET, 0);
176}
177
178/**
179 * rt5639_index_write - Write private register.
180 * @codec: SoC audio codec device.
181 * @reg: Private register index.
182 * @value: Private register Data.
183 *
184 * Modify private register for advanced setting. It can be written through
185 * private index (0x6a) and data (0x6c) register.
186 *
187 * Returns 0 for success or negative error code.
188 */
189static int rt5639_index_write(struct snd_soc_codec *codec,
190 unsigned int reg, unsigned int value)
191{
192 int ret;
193
194 ret = snd_soc_write(codec, RT5639_PRIV_INDEX, reg);
195 if (ret < 0) {
196 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
197 goto err;
198 }
199 ret = snd_soc_write(codec, RT5639_PRIV_DATA, value);
200 if (ret < 0) {
201 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
202 goto err;
203 }
204 return 0;
205
206err:
207 return ret;
208}
209
210/**
211 * rt5639_index_read - Read private register.
212 * @codec: SoC audio codec device.
213 * @reg: Private register index.
214 *
215 * Read advanced setting from private register. It can be read through
216 * private index (0x6a) and data (0x6c) register.
217 *
218 * Returns private register value or negative error code.
219 */
220static unsigned int rt5639_index_read(
221 struct snd_soc_codec *codec, unsigned int reg)
222{
223 int ret;
224
225 ret = snd_soc_write(codec, RT5639_PRIV_INDEX, reg);
226 if (ret < 0) {
227 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
228 return ret;
229 }
230 return snd_soc_read(codec, RT5639_PRIV_DATA);
231}
232
233/**
234 * rt5639_index_update_bits - update private register bits
235 * @codec: audio codec
236 * @reg: Private register index.
237 * @mask: register mask
238 * @value: new value
239 *
240 * Writes new register value.
241 *
242 * Returns 1 for change, 0 for no change, or negative error code.
243 */
244static int rt5639_index_update_bits(struct snd_soc_codec *codec,
245 unsigned int reg, unsigned int mask, unsigned int value)
246{
247 unsigned int old, new;
248 int change, ret;
249
250 ret = rt5639_index_read(codec, reg);
251 if (ret < 0) {
252 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
253 goto err;
254 }
255
256 old = ret;
257 new = (old & ~mask) | (value & mask);
258 change = old != new;
259 if (change) {
260 ret = rt5639_index_write(codec, reg, new);
261 if (ret < 0) {
262 dev_err(codec->dev,
263 "Failed to write private reg: %d\n", ret);
264 goto err;
265 }
266 }
267 return change;
268
269err:
270 return ret;
271}
272
273static int rt5639_volatile_register(
274 struct snd_soc_codec *codec, unsigned int reg)
275{
276 switch (reg) {
277 case RT5639_RESET:
278 case RT5639_PRIV_DATA:
279 case RT5639_ASRC_5:
280 case RT5639_EQ_CTRL1:
281 case RT5639_DRC_AGC_1:
282 case RT5639_ANC_CTRL1:
283 case RT5639_IRQ_CTRL2:
284 case RT5639_INT_IRQ_ST:
285 case RT5639_DSP_CTRL2:
286 case RT5639_DSP_CTRL3:
287 case RT5639_PGM_REG_ARR1:
288 case RT5639_PGM_REG_ARR3:
289 return 1;
290 default:
291 return 0;
292 }
293}
294
295static int rt5639_readable_register(
296 struct snd_soc_codec *codec, unsigned int reg)
297{
298 switch (reg) {
299 case RT5639_RESET:
300 case RT5639_SPK_VOL:
301 case RT5639_HP_VOL:
302 case RT5639_OUTPUT:
303 case RT5639_MONO_OUT:
304 case RT5639_IN1_IN2:
305 case RT5639_IN3_IN4:
306 case RT5639_INL_INR_VOL:
307 case RT5639_DAC1_DIG_VOL:
308 case RT5639_DAC2_DIG_VOL:
309 case RT5639_DAC2_CTRL:
310 case RT5639_ADC_DIG_VOL:
311 case RT5639_ADC_DATA:
312 case RT5639_ADC_BST_VOL:
313 case RT5639_STO_ADC_MIXER:
314 case RT5639_MONO_ADC_MIXER:
315 case RT5639_AD_DA_MIXER:
316 case RT5639_STO_DAC_MIXER:
317 case RT5639_MONO_DAC_MIXER:
318 case RT5639_DIG_MIXER:
319 case RT5639_DSP_PATH1:
320 case RT5639_DSP_PATH2:
321 case RT5639_DIG_INF_DATA:
322 case RT5639_REC_L1_MIXER:
323 case RT5639_REC_L2_MIXER:
324 case RT5639_REC_R1_MIXER:
325 case RT5639_REC_R2_MIXER:
326 case RT5639_HPO_MIXER:
327 case RT5639_SPK_L_MIXER:
328 case RT5639_SPK_R_MIXER:
329 case RT5639_SPO_L_MIXER:
330 case RT5639_SPO_R_MIXER:
331 case RT5639_SPO_CLSD_RATIO:
332 case RT5639_MONO_MIXER:
333 case RT5639_OUT_L1_MIXER:
334 case RT5639_OUT_L2_MIXER:
335 case RT5639_OUT_L3_MIXER:
336 case RT5639_OUT_R1_MIXER:
337 case RT5639_OUT_R2_MIXER:
338 case RT5639_OUT_R3_MIXER:
339 case RT5639_LOUT_MIXER:
340 case RT5639_PWR_DIG1:
341 case RT5639_PWR_DIG2:
342 case RT5639_PWR_ANLG1:
343 case RT5639_PWR_ANLG2:
344 case RT5639_PWR_MIXER:
345 case RT5639_PWR_VOL:
346 case RT5639_PRIV_INDEX:
347 case RT5639_PRIV_DATA:
348 case RT5639_I2S1_SDP:
349 case RT5639_I2S2_SDP:
350 case RT5639_I2S3_SDP:
351 case RT5639_ADDA_CLK1:
352 case RT5639_ADDA_CLK2:
353 case RT5639_DMIC:
354 case RT5639_GLB_CLK:
355 case RT5639_PLL_CTRL1:
356 case RT5639_PLL_CTRL2:
357 case RT5639_ASRC_1:
358 case RT5639_ASRC_2:
359 case RT5639_ASRC_3:
360 case RT5639_ASRC_4:
361 case RT5639_ASRC_5:
362 case RT5639_HP_OVCD:
363 case RT5639_CLS_D_OVCD:
364 case RT5639_CLS_D_OUT:
365 case RT5639_DEPOP_M1:
366 case RT5639_DEPOP_M2:
367 case RT5639_DEPOP_M3:
368 case RT5639_CHARGE_PUMP:
369 case RT5639_PV_DET_SPK_G:
370 case RT5639_MICBIAS:
371 case RT5639_EQ_CTRL1:
372 case RT5639_EQ_CTRL2:
373 case RT5639_WIND_FILTER:
374 case RT5639_DRC_AGC_1:
375 case RT5639_DRC_AGC_2:
376 case RT5639_DRC_AGC_3:
377 case RT5639_SVOL_ZC:
378 case RT5639_ANC_CTRL1:
379 case RT5639_ANC_CTRL2:
380 case RT5639_ANC_CTRL3:
381 case RT5639_JD_CTRL:
382 case RT5639_ANC_JD:
383 case RT5639_IRQ_CTRL1:
384 case RT5639_IRQ_CTRL2:
385 case RT5639_INT_IRQ_ST:
386 case RT5639_GPIO_CTRL1:
387 case RT5639_GPIO_CTRL2:
388 case RT5639_GPIO_CTRL3:
389 case RT5639_DSP_CTRL1:
390 case RT5639_DSP_CTRL2:
391 case RT5639_DSP_CTRL3:
392 case RT5639_DSP_CTRL4:
393 case RT5639_PGM_REG_ARR1:
394 case RT5639_PGM_REG_ARR2:
395 case RT5639_PGM_REG_ARR3:
396 case RT5639_PGM_REG_ARR4:
397 case RT5639_PGM_REG_ARR5:
398 case RT5639_SCB_FUNC:
399 case RT5639_SCB_CTRL:
400 case RT5639_BASE_BACK:
401 case RT5639_MP3_PLUS1:
402 case RT5639_MP3_PLUS2:
403 case RT5639_3D_HP:
404 case RT5639_ADJ_HPF:
405 case RT5639_HP_CALIB_AMP_DET:
406 case RT5639_HP_CALIB2:
407 case RT5639_SV_ZCD1:
408 case RT5639_SV_ZCD2:
409 case RT5639_DUMMY1:
410 case RT5639_DUMMY2:
411 case RT5639_DUMMY3:
412 case RT5639_VENDOR_ID:
413 case RT5639_VENDOR_ID1:
414 case RT5639_VENDOR_ID2:
415 return 1;
416 default:
417 return 0;
418 }
419}
420
421int rt5639_headset_detect(struct snd_soc_codec *codec, int jack_insert)
422{
423 int jack_type;
424
425 if (jack_insert) {
426 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
427 RT5639_PWR_LDO2, RT5639_PWR_LDO2);
428 snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
429 RT5639_PWR_MB1, RT5639_PWR_MB1);
430 snd_soc_update_bits(codec, RT5639_MICBIAS,
431 RT5639_MIC1_OVCD_MASK | RT5639_MIC1_OVTH_MASK |
432 RT5639_PWR_CLK25M_MASK | RT5639_PWR_MB_MASK,
433 RT5639_MIC1_OVCD_EN | RT5639_MIC1_OVTH_600UA |
434 RT5639_PWR_MB_PU | RT5639_PWR_CLK25M_PU);
435 snd_soc_update_bits(codec, RT5639_DUMMY1,
436 0x1, 0x1);
437 msleep(50);
438 if (snd_soc_read(codec, RT5639_IRQ_CTRL2) & 0x8)
439 jack_type = RT5639_HEADPHO_DET;
440 else
441 jack_type = RT5639_HEADSET_DET;
442 snd_soc_update_bits(codec, RT5639_IRQ_CTRL2,
443 RT5639_MB1_OC_CLR, 0);
444 } else {
445 snd_soc_update_bits(codec, RT5639_MICBIAS,
446 RT5639_MIC1_OVCD_MASK,
447 RT5639_MIC1_OVCD_DIS);
448
449 jack_type = RT5639_NO_JACK;
450 }
451
452 return jack_type;
453}
454EXPORT_SYMBOL(rt5639_headset_detect);
455
456static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
457static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
458static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
459static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
460static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
461
462/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
463static unsigned int bst_tlv[] = {
464 TLV_DB_RANGE_HEAD(7),
465 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
466 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
467 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
468 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
469 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
470 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
471 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
472};
473
474static int rt5639_dmic_get(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
476{
477 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
478 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
479
480 ucontrol->value.integer.value[0] = rt5639->dmic_en;
481
482 return 0;
483}
484
485static int rt5639_dmic_put(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
490
491 if (rt5639->dmic_en == ucontrol->value.integer.value[0])
492 return 0;
493
494 rt5639->dmic_en = ucontrol->value.integer.value[0];
495 switch (rt5639->dmic_en) {
496 case RT5639_DMIC_DIS:
497 snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
498 RT5639_GP2_PIN_MASK | RT5639_GP3_PIN_MASK |
499 RT5639_GP4_PIN_MASK,
500 RT5639_GP2_PIN_GPIO2 | RT5639_GP3_PIN_GPIO3 |
501 RT5639_GP4_PIN_GPIO4);
502 snd_soc_update_bits(codec, RT5639_DMIC,
503 RT5639_DMIC_1_DP_MASK | RT5639_DMIC_2_DP_MASK,
504 RT5639_DMIC_1_DP_GPIO3 | RT5639_DMIC_2_DP_GPIO4);
505 snd_soc_update_bits(codec, RT5639_DMIC,
506 RT5639_DMIC_1_EN_MASK | RT5639_DMIC_2_EN_MASK,
507 RT5639_DMIC_1_DIS | RT5639_DMIC_2_DIS);
508 break;
509
510 case RT5639_DMIC1:
511 snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
512 RT5639_GP2_PIN_MASK | RT5639_GP3_PIN_MASK,
513 RT5639_GP2_PIN_DMIC1_SCL | RT5639_GP3_PIN_DMIC1_SDA);
514 snd_soc_update_bits(codec, RT5639_DMIC,
515 RT5639_DMIC_1L_LH_MASK | RT5639_DMIC_1R_LH_MASK |
516 RT5639_DMIC_1_DP_MASK,
517 RT5639_DMIC_1L_LH_FALLING | RT5639_DMIC_1R_LH_RISING |
518 RT5639_DMIC_1_DP_IN1P);
519 snd_soc_update_bits(codec, RT5639_DMIC,
520 RT5639_DMIC_1_EN_MASK, RT5639_DMIC_1_EN);
521 break;
522
523 case RT5639_DMIC2:
524 snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
525 RT5639_GP2_PIN_MASK | RT5639_GP4_PIN_MASK,
526 RT5639_GP2_PIN_DMIC1_SCL | RT5639_GP4_PIN_DMIC2_SDA);
527 snd_soc_update_bits(codec, RT5639_DMIC,
528 RT5639_DMIC_2L_LH_MASK | RT5639_DMIC_2R_LH_MASK |
529 RT5639_DMIC_2_DP_MASK,
530 RT5639_DMIC_2L_LH_FALLING | RT5639_DMIC_2R_LH_RISING |
531 RT5639_DMIC_2_DP_IN1N);
532 snd_soc_update_bits(codec, RT5639_DMIC,
533 RT5639_DMIC_2_EN_MASK, RT5639_DMIC_2_EN);
534 break;
535
536 default:
537 return -EINVAL;
538 }
539
540 return 0;
541}
542
543
544/* IN1/IN2 Input Type */
545static const char *rt5639_input_mode[] = {
546 "Single ended", "Differential"};
547
548static const SOC_ENUM_SINGLE_DECL(
549 rt5639_in1_mode_enum, RT5639_IN1_IN2,
550 RT5639_IN_SFT1, rt5639_input_mode);
551
552static const SOC_ENUM_SINGLE_DECL(
553 rt5639_in2_mode_enum, RT5639_IN3_IN4,
554 RT5639_IN_SFT2, rt5639_input_mode);
555
556/* Interface data select */
557static const char *rt5639_data_select[] = {
558 "Normal", "left copy to right", "right copy to left", "Swap"};
559
560static const SOC_ENUM_SINGLE_DECL(rt5639_if1_dac_enum, RT5639_DIG_INF_DATA,
561 RT5639_IF1_DAC_SEL_SFT, rt5639_data_select);
562
563static const SOC_ENUM_SINGLE_DECL(rt5639_if1_adc_enum, RT5639_DIG_INF_DATA,
564 RT5639_IF1_ADC_SEL_SFT, rt5639_data_select);
565
566static const SOC_ENUM_SINGLE_DECL(rt5639_if2_dac_enum, RT5639_DIG_INF_DATA,
567 RT5639_IF2_DAC_SEL_SFT, rt5639_data_select);
568
569static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_enum, RT5639_DIG_INF_DATA,
570 RT5639_IF2_ADC_SEL_SFT, rt5639_data_select);
571
572static const SOC_ENUM_SINGLE_DECL(rt5639_if3_dac_enum, RT5639_DIG_INF_DATA,
573 RT5639_IF3_DAC_SEL_SFT, rt5639_data_select);
574
575static const SOC_ENUM_SINGLE_DECL(rt5639_if3_adc_enum, RT5639_DIG_INF_DATA,
576 RT5639_IF3_ADC_SEL_SFT, rt5639_data_select);
577
578/* Class D speaker gain ratio */
579static const char *rt5639_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
580 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
581
582static const SOC_ENUM_SINGLE_DECL(
583 rt5639_clsd_spk_ratio_enum, RT5639_CLS_D_OUT,
584 RT5639_CLSD_RATIO_SFT, rt5639_clsd_spk_ratio);
585
586/* DMIC */
587static const char *rt5639_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
588
589static const SOC_ENUM_SINGLE_DECL(rt5639_dmic_enum, 0, 0, rt5639_dmic_mode);
590
591
592
593#ifdef RT5639_REG_RW
594#define REGVAL_MAX 0xffff
595static unsigned int regctl_addr;
596static int rt5639_regctl_info(struct snd_kcontrol *kcontrol,
597 struct snd_ctl_elem_info *uinfo)
598{
599 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
600 uinfo->count = 2;
601 uinfo->value.integer.min = 0;
602 uinfo->value.integer.max = REGVAL_MAX;
603 return 0;
604}
605
606static int rt5639_regctl_get(struct snd_kcontrol *kcontrol,
607 struct snd_ctl_elem_value *ucontrol)
608{
609 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
610 ucontrol->value.integer.value[0] = regctl_addr;
611 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
612 return 0;
613}
614
615static int rt5639_regctl_put(struct snd_kcontrol *kcontrol,
616 struct snd_ctl_elem_value *ucontrol)
617{
618 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
619 regctl_addr = ucontrol->value.integer.value[0];
620 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
621 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
622 return 0;
623}
624#endif
625
626
627static int rt5639_vol_rescale_get(struct snd_kcontrol *kcontrol,
628 struct snd_ctl_elem_value *ucontrol)
629{
630 struct soc_mixer_control *mc =
631 (struct soc_mixer_control *)kcontrol->private_value;
632 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
633 unsigned int val = snd_soc_read(codec, mc->reg);
634
635 ucontrol->value.integer.value[0] = RT5639_VOL_RSCL_MAX -
636 ((val & RT5639_L_VOL_MASK) >> mc->shift);
637 ucontrol->value.integer.value[1] = RT5639_VOL_RSCL_MAX -
638 (val & RT5639_R_VOL_MASK);
639
640 return 0;
641}
642
643static int rt5639_vol_rescale_put(struct snd_kcontrol *kcontrol,
644 struct snd_ctl_elem_value *ucontrol)
645{
646 struct soc_mixer_control *mc =
647 (struct soc_mixer_control *)kcontrol->private_value;
648 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
649 unsigned int val, val2;
650
651 val = RT5639_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
652 val2 = RT5639_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
653 return snd_soc_update_bits_locked(codec, mc->reg, RT5639_L_VOL_MASK |
654 RT5639_R_VOL_MASK, val << mc->shift | val2);
655}
656
657
658static const struct snd_kcontrol_new rt5639_snd_controls[] = {
659 /* Speaker Output Volume */
660 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5639_SPK_VOL,
661 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, RT5639_VOL_RSCL_RANGE, 0,
662 rt5639_vol_rescale_get, rt5639_vol_rescale_put, out_vol_tlv),
663 /* Headphone Output Volume */
664 SOC_DOUBLE("HP Playback Switch", RT5639_HP_VOL,
665 RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
666 SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT5639_HP_VOL,
667 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, RT5639_VOL_RSCL_RANGE, 0,
668 rt5639_vol_rescale_get, rt5639_vol_rescale_put, out_vol_tlv),
669 /* OUTPUT Control */
670 SOC_DOUBLE("OUT Playback Switch", RT5639_OUTPUT,
671 RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
672 SOC_DOUBLE("OUT Channel Switch", RT5639_OUTPUT,
673 RT5639_VOL_L_SFT, RT5639_VOL_R_SFT, 1, 1),
674 SOC_DOUBLE_TLV("OUT Playback Volume", RT5639_OUTPUT,
675 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, 39, 1, out_vol_tlv),
676 /* MONO Output Control */
677 SOC_SINGLE("Mono Playback Switch", RT5639_MONO_OUT,
678 RT5639_L_MUTE_SFT, 1, 1),
679 /* DAC Digital Volume */
680 SOC_DOUBLE("DAC2 Playback Switch", RT5639_DAC2_CTRL,
681 RT5639_M_DAC_L2_VOL_SFT, RT5639_M_DAC_R2_VOL_SFT, 1, 1),
682 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5639_DAC1_DIG_VOL,
683 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
684 175, 0, dac_vol_tlv),
685 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5639_DAC2_DIG_VOL,
686 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
687 175, 0, dac_vol_tlv),
688 /* IN1/IN2 Control */
689 SOC_ENUM("IN1 Mode Control", rt5639_in1_mode_enum),
690 SOC_SINGLE_TLV("IN1 Boost", RT5639_IN1_IN2,
691 RT5639_BST_SFT1, 8, 0, bst_tlv),
692 SOC_ENUM("IN2 Mode Control", rt5639_in2_mode_enum),
693 SOC_SINGLE_TLV("IN2 Boost", RT5639_IN3_IN4,
694 RT5639_BST_SFT2, 8, 0, bst_tlv),
695 /* INL/INR Volume Control */
696 SOC_DOUBLE_TLV("IN Capture Volume", RT5639_INL_INR_VOL,
697 RT5639_INL_VOL_SFT, RT5639_INR_VOL_SFT,
698 31, 1, in_vol_tlv),
699 /* ADC Digital Volume Control */
700 SOC_DOUBLE("ADC Capture Switch", RT5639_ADC_DIG_VOL,
701 RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
702 SOC_DOUBLE_TLV("ADC Capture Volume", RT5639_ADC_DIG_VOL,
703 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
704 127, 0, adc_vol_tlv),
705 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5639_ADC_DATA,
706 RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
707 127, 0, adc_vol_tlv),
708 /* ADC Boost Volume Control */
709 SOC_DOUBLE_TLV("ADC Boost Gain", RT5639_ADC_BST_VOL,
710 RT5639_ADC_L_BST_SFT, RT5639_ADC_R_BST_SFT,
711 3, 0, adc_bst_tlv),
712 /* Class D speaker gain ratio */
713 SOC_ENUM("Class D SPK Ratio Control", rt5639_clsd_spk_ratio_enum),
714 /* DMIC */
715 SOC_ENUM_EXT("DMIC Switch", rt5639_dmic_enum,
716 rt5639_dmic_get, rt5639_dmic_put),
717
718#ifdef RT5639_REG_RW
719 {
720 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
721 .name = "Register Control",
722 .info = rt5639_regctl_info,
723 .get = rt5639_regctl_get,
724 .put = rt5639_regctl_put,
725 },
726#endif
727};
728
729/**
730 * set_dmic_clk - Set parameter of dmic.
731 *
732 * @w: DAPM widget.
733 * @kcontrol: The kcontrol of this widget.
734 * @event: Event id.
735 *
736 * Choose dmic clock between 1MHz and 3MHz.
737 * It is better for clock to approximate 3MHz.
738 */
739static int set_dmic_clk(struct snd_soc_dapm_widget *w,
740 struct snd_kcontrol *kcontrol, int event)
741{
742 struct snd_soc_codec *codec = w->codec;
743 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
744 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
745
746 rate = rt5639->lrck[rt5639->aif_pu] << 8;
747 red = 3000000 * 12;
748 for (i = 0; i < ARRAY_SIZE(div); i++) {
749 bound = div[i] * 3000000;
750 if (rate > bound)
751 continue;
752 temp = bound - rate;
753 if (temp < red) {
754 red = temp;
755 idx = i;
756 }
757 }
758 if (idx < 0)
759 dev_err(codec->dev, "Failed to set DMIC clock\n");
760 else
761 snd_soc_update_bits(codec, RT5639_DMIC, RT5639_DMIC_CLK_MASK,
762 idx << RT5639_DMIC_CLK_SFT);
763 return idx;
764}
765
766static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
767 struct snd_soc_dapm_widget *sink)
768{
769 unsigned int val;
770
771 val = snd_soc_read(source->codec, RT5639_GLB_CLK);
772 val &= RT5639_SCLK_SRC_MASK;
773 if (val == RT5639_SCLK_SRC_PLL1)
774 return 1;
775 else
776 return 0;
777}
778
779/* Digital Mixer */
780static const struct snd_kcontrol_new rt5639_sto_adc_l_mix[] = {
781 SOC_DAPM_SINGLE("ADC1 Switch", RT5639_STO_ADC_MIXER,
782 RT5639_M_ADC_L1_SFT, 1, 1),
783 SOC_DAPM_SINGLE("ADC2 Switch", RT5639_STO_ADC_MIXER,
784 RT5639_M_ADC_L2_SFT, 1, 1),
785};
786
787static const struct snd_kcontrol_new rt5639_sto_adc_r_mix[] = {
788 SOC_DAPM_SINGLE("ADC1 Switch", RT5639_STO_ADC_MIXER,
789 RT5639_M_ADC_R1_SFT, 1, 1),
790 SOC_DAPM_SINGLE("ADC2 Switch", RT5639_STO_ADC_MIXER,
791 RT5639_M_ADC_R2_SFT, 1, 1),
792};
793
794static const struct snd_kcontrol_new rt5639_mono_adc_l_mix[] = {
795 SOC_DAPM_SINGLE("ADC1 Switch", RT5639_MONO_ADC_MIXER,
796 RT5639_M_MONO_ADC_L1_SFT, 1, 1),
797 SOC_DAPM_SINGLE("ADC2 Switch", RT5639_MONO_ADC_MIXER,
798 RT5639_M_MONO_ADC_L2_SFT, 1, 1),
799};
800
801static const struct snd_kcontrol_new rt5639_mono_adc_r_mix[] = {
802 SOC_DAPM_SINGLE("ADC1 Switch", RT5639_MONO_ADC_MIXER,
803 RT5639_M_MONO_ADC_R1_SFT, 1, 1),
804 SOC_DAPM_SINGLE("ADC2 Switch", RT5639_MONO_ADC_MIXER,
805 RT5639_M_MONO_ADC_R2_SFT, 1, 1),
806};
807
808static const struct snd_kcontrol_new rt5639_dac_l_mix[] = {
809 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5639_AD_DA_MIXER,
810 RT5639_M_ADCMIX_L_SFT, 1, 1),
811 SOC_DAPM_SINGLE("INF1 Switch", RT5639_AD_DA_MIXER,
812 RT5639_M_IF1_DAC_L_SFT, 1, 1),
813};
814
815static const struct snd_kcontrol_new rt5639_dac_r_mix[] = {
816 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5639_AD_DA_MIXER,
817 RT5639_M_ADCMIX_R_SFT, 1, 1),
818 SOC_DAPM_SINGLE("INF1 Switch", RT5639_AD_DA_MIXER,
819 RT5639_M_IF1_DAC_R_SFT, 1, 1),
820};
821
822static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
823 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_STO_DAC_MIXER,
824 RT5639_M_DAC_L1_SFT, 1, 1),
825 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_STO_DAC_MIXER,
826 RT5639_M_DAC_L2_SFT, 1, 1),
827 SOC_DAPM_SINGLE("ANC Switch", RT5639_STO_DAC_MIXER,
828 RT5639_M_ANC_DAC_L_SFT, 1, 1),
829};
830
831static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
832 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_STO_DAC_MIXER,
833 RT5639_M_DAC_R1_SFT, 1, 1),
834 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_STO_DAC_MIXER,
835 RT5639_M_DAC_R2_SFT, 1, 1),
836 SOC_DAPM_SINGLE("ANC Switch", RT5639_STO_DAC_MIXER,
837 RT5639_M_ANC_DAC_R_SFT, 1, 1),
838};
839
840static const struct snd_kcontrol_new rt5639_mono_dac_l_mix[] = {
841 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_MONO_DAC_MIXER,
842 RT5639_M_DAC_L1_MONO_L_SFT, 1, 1),
843 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_DAC_MIXER,
844 RT5639_M_DAC_L2_MONO_L_SFT, 1, 1),
845 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_DAC_MIXER,
846 RT5639_M_DAC_R2_MONO_L_SFT, 1, 1),
847};
848
849static const struct snd_kcontrol_new rt5639_mono_dac_r_mix[] = {
850 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_MONO_DAC_MIXER,
851 RT5639_M_DAC_R1_MONO_R_SFT, 1, 1),
852 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_DAC_MIXER,
853 RT5639_M_DAC_R2_MONO_R_SFT, 1, 1),
854 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_DAC_MIXER,
855 RT5639_M_DAC_L2_MONO_R_SFT, 1, 1),
856};
857
858static const struct snd_kcontrol_new rt5639_dig_l_mix[] = {
859 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_DIG_MIXER,
860 RT5639_M_STO_L_DAC_L_SFT, 1, 1),
861 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_DIG_MIXER,
862 RT5639_M_DAC_L2_DAC_L_SFT, 1, 1),
863};
864
865static const struct snd_kcontrol_new rt5639_dig_r_mix[] = {
866 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_DIG_MIXER,
867 RT5639_M_STO_R_DAC_R_SFT, 1, 1),
868 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_DIG_MIXER,
869 RT5639_M_DAC_R2_DAC_R_SFT, 1, 1),
870};
871
872/* Analog Input Mixer */
873static const struct snd_kcontrol_new rt5639_rec_l_mix[] = {
874 SOC_DAPM_SINGLE("HPOL Switch", RT5639_REC_L2_MIXER,
875 RT5639_M_HP_L_RM_L_SFT, 1, 1),
876 SOC_DAPM_SINGLE("INL Switch", RT5639_REC_L2_MIXER,
877 RT5639_M_IN_L_RM_L_SFT, 1, 1),
878 SOC_DAPM_SINGLE("BST2 Switch", RT5639_REC_L2_MIXER,
879 RT5639_M_BST4_RM_L_SFT, 1, 1),
880 SOC_DAPM_SINGLE("BST1 Switch", RT5639_REC_L2_MIXER,
881 RT5639_M_BST1_RM_L_SFT, 1, 1),
882 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5639_REC_L2_MIXER,
883 RT5639_M_OM_L_RM_L_SFT, 1, 1),
884};
885
886static const struct snd_kcontrol_new rt5639_rec_r_mix[] = {
887 SOC_DAPM_SINGLE("HPOR Switch", RT5639_REC_R2_MIXER,
888 RT5639_M_HP_R_RM_R_SFT, 1, 1),
889 SOC_DAPM_SINGLE("INR Switch", RT5639_REC_R2_MIXER,
890 RT5639_M_IN_R_RM_R_SFT, 1, 1),
891 SOC_DAPM_SINGLE("BST2 Switch", RT5639_REC_R2_MIXER,
892 RT5639_M_BST4_RM_R_SFT, 1, 1),
893 SOC_DAPM_SINGLE("BST1 Switch", RT5639_REC_R2_MIXER,
894 RT5639_M_BST1_RM_R_SFT, 1, 1),
895 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5639_REC_R2_MIXER,
896 RT5639_M_OM_R_RM_R_SFT, 1, 1),
897};
898
899/* Analog Output Mixer */
900static const struct snd_kcontrol_new rt5639_spk_l_mix[] = {
901 SOC_DAPM_SINGLE("REC MIXL Switch", RT5639_SPK_L_MIXER,
902 RT5639_M_RM_L_SM_L_SFT, 1, 1),
903 SOC_DAPM_SINGLE("INL Switch", RT5639_SPK_L_MIXER,
904 RT5639_M_IN_L_SM_L_SFT, 1, 1),
905 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_SPK_L_MIXER,
906 RT5639_M_DAC_L1_SM_L_SFT, 1, 1),
907 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_SPK_L_MIXER,
908 RT5639_M_DAC_L2_SM_L_SFT, 1, 1),
909 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5639_SPK_L_MIXER,
910 RT5639_M_OM_L_SM_L_SFT, 1, 1),
911};
912
913static const struct snd_kcontrol_new rt5639_spk_r_mix[] = {
914 SOC_DAPM_SINGLE("REC MIXR Switch", RT5639_SPK_R_MIXER,
915 RT5639_M_RM_R_SM_R_SFT, 1, 1),
916 SOC_DAPM_SINGLE("INR Switch", RT5639_SPK_R_MIXER,
917 RT5639_M_IN_R_SM_R_SFT, 1, 1),
918 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPK_R_MIXER,
919 RT5639_M_DAC_R1_SM_R_SFT, 1, 1),
920 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_SPK_R_MIXER,
921 RT5639_M_DAC_R2_SM_R_SFT, 1, 1),
922 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5639_SPK_R_MIXER,
923 RT5639_M_OM_R_SM_R_SFT, 1, 1),
924};
925
926static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
927 SOC_DAPM_SINGLE("SPK MIXL Switch", RT5639_OUT_L3_MIXER,
928 RT5639_M_SM_L_OM_L_SFT, 1, 1),
929 SOC_DAPM_SINGLE("BST1 Switch", RT5639_OUT_L3_MIXER,
930 RT5639_M_BST1_OM_L_SFT, 1, 1),
931 SOC_DAPM_SINGLE("INL Switch", RT5639_OUT_L3_MIXER,
932 RT5639_M_IN_L_OM_L_SFT, 1, 1),
933 SOC_DAPM_SINGLE("REC MIXL Switch", RT5639_OUT_L3_MIXER,
934 RT5639_M_RM_L_OM_L_SFT, 1, 1),
935 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_OUT_L3_MIXER,
936 RT5639_M_DAC_R2_OM_L_SFT, 1, 1),
937 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_OUT_L3_MIXER,
938 RT5639_M_DAC_L2_OM_L_SFT, 1, 1),
939 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_OUT_L3_MIXER,
940 RT5639_M_DAC_L1_OM_L_SFT, 1, 1),
941};
942
943static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
944 SOC_DAPM_SINGLE("SPK MIXR Switch", RT5639_OUT_R3_MIXER,
945 RT5639_M_SM_L_OM_R_SFT, 1, 1),
946 SOC_DAPM_SINGLE("BST2 Switch", RT5639_OUT_R3_MIXER,
947 RT5639_M_BST4_OM_R_SFT, 1, 1),
948 SOC_DAPM_SINGLE("BST1 Switch", RT5639_OUT_R3_MIXER,
949 RT5639_M_BST1_OM_R_SFT, 1, 1),
950 SOC_DAPM_SINGLE("INR Switch", RT5639_OUT_R3_MIXER,
951 RT5639_M_IN_R_OM_R_SFT, 1, 1),
952 SOC_DAPM_SINGLE("REC MIXR Switch", RT5639_OUT_R3_MIXER,
953 RT5639_M_RM_R_OM_R_SFT, 1, 1),
954 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_OUT_R3_MIXER,
955 RT5639_M_DAC_L2_OM_R_SFT, 1, 1),
956 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_OUT_R3_MIXER,
957 RT5639_M_DAC_R2_OM_R_SFT, 1, 1),
958 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_OUT_R3_MIXER,
959 RT5639_M_DAC_R1_OM_R_SFT, 1, 1),
960};
961
962static const struct snd_kcontrol_new rt5639_spo_l_mix[] = {
963 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPO_L_MIXER,
964 RT5639_M_DAC_R1_SPM_L_SFT, 1, 1),
965 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_SPO_L_MIXER,
966 RT5639_M_DAC_L1_SPM_L_SFT, 1, 1),
967 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5639_SPO_L_MIXER,
968 RT5639_M_SV_R_SPM_L_SFT, 1, 1),
969 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5639_SPO_L_MIXER,
970 RT5639_M_SV_L_SPM_L_SFT, 1, 1),
971 SOC_DAPM_SINGLE("BST1 Switch", RT5639_SPO_L_MIXER,
972 RT5639_M_BST1_SPM_L_SFT, 1, 1),
973};
974
975static const struct snd_kcontrol_new rt5639_spo_r_mix[] = {
976 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPO_R_MIXER,
977 RT5639_M_DAC_R1_SPM_R_SFT, 1, 1),
978 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5639_SPO_R_MIXER,
979 RT5639_M_SV_R_SPM_R_SFT, 1, 1),
980 SOC_DAPM_SINGLE("BST1 Switch", RT5639_SPO_R_MIXER,
981 RT5639_M_BST1_SPM_R_SFT, 1, 1),
982};
983
984static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
985 SOC_DAPM_SINGLE("DAC2 Switch", RT5639_HPO_MIXER,
986 RT5639_M_DAC2_HM_SFT, 1, 1),
987 SOC_DAPM_SINGLE("DAC1 Switch", RT5639_HPO_MIXER,
988 RT5639_M_DAC1_HM_SFT, 1, 1),
989 SOC_DAPM_SINGLE("HPVOL Switch", RT5639_HPO_MIXER,
990 RT5639_M_HPVOL_HM_SFT, 1, 1),
991};
992
993static const struct snd_kcontrol_new rt5639_lout_mix[] = {
994 SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_LOUT_MIXER,
995 RT5639_M_DAC_L1_LM_SFT, 1, 1),
996 SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_LOUT_MIXER,
997 RT5639_M_DAC_R1_LM_SFT, 1, 1),
998 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5639_LOUT_MIXER,
999 RT5639_M_OV_L_LM_SFT, 1, 1),
1000 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5639_LOUT_MIXER,
1001 RT5639_M_OV_R_LM_SFT, 1, 1),
1002};
1003
1004static const struct snd_kcontrol_new rt5639_mono_mix[] = {
1005 SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_MIXER,
1006 RT5639_M_DAC_R2_MM_SFT, 1, 1),
1007 SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_MIXER,
1008 RT5639_M_DAC_L2_MM_SFT, 1, 1),
1009 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5639_MONO_MIXER,
1010 RT5639_M_OV_R_MM_SFT, 1, 1),
1011 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5639_MONO_MIXER,
1012 RT5639_M_OV_L_MM_SFT, 1, 1),
1013 SOC_DAPM_SINGLE("BST1 Switch", RT5639_MONO_MIXER,
1014 RT5639_M_BST1_MM_SFT, 1, 1),
1015};
1016
1017/* INL/R source */
1018static const char *rt5639_inl_src[] = {"IN2P", "MonoP"};
1019
1020static const SOC_ENUM_SINGLE_DECL(
1021 rt5639_inl_enum, RT5639_INL_INR_VOL,
1022 RT5639_INL_SEL_SFT, rt5639_inl_src);
1023
1024static const struct snd_kcontrol_new rt5639_inl_mux =
1025 SOC_DAPM_ENUM("INL source", rt5639_inl_enum);
1026
1027static const char *rt5639_inr_src[] = {"IN2N", "MonoN"};
1028
1029static const SOC_ENUM_SINGLE_DECL(
1030 rt5639_inr_enum, RT5639_INL_INR_VOL,
1031 RT5639_INR_SEL_SFT, rt5639_inr_src);
1032
1033static const struct snd_kcontrol_new rt5639_inr_mux =
1034 SOC_DAPM_ENUM("INR source", rt5639_inr_enum);
1035
1036/* Stereo ADC source */
1037static const char *rt5639_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1038
1039static const SOC_ENUM_SINGLE_DECL(
1040 rt5639_stereo_adc1_enum, RT5639_STO_ADC_MIXER,
1041 RT5639_ADC_1_SRC_SFT, rt5639_stereo_adc1_src);
1042
1043static const struct snd_kcontrol_new rt5639_sto_adc_l1_mux =
1044 SOC_DAPM_ENUM("Stereo ADC L1 source", rt5639_stereo_adc1_enum);
1045
1046static const struct snd_kcontrol_new rt5639_sto_adc_r1_mux =
1047 SOC_DAPM_ENUM("Stereo ADC R1 source", rt5639_stereo_adc1_enum);
1048
1049static const char *rt5639_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1050
1051static const SOC_ENUM_SINGLE_DECL(
1052 rt5639_stereo_adc2_enum, RT5639_STO_ADC_MIXER,
1053 RT5639_ADC_2_SRC_SFT, rt5639_stereo_adc2_src);
1054
1055static const struct snd_kcontrol_new rt5639_sto_adc_l2_mux =
1056 SOC_DAPM_ENUM("Stereo ADC L2 source", rt5639_stereo_adc2_enum);
1057
1058static const struct snd_kcontrol_new rt5639_sto_adc_r2_mux =
1059 SOC_DAPM_ENUM("Stereo ADC R2 source", rt5639_stereo_adc2_enum);
1060
1061/* Mono ADC source */
1062static const char *rt5639_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1063
1064static const SOC_ENUM_SINGLE_DECL(
1065 rt5639_mono_adc_l1_enum, RT5639_MONO_ADC_MIXER,
1066 RT5639_MONO_ADC_L1_SRC_SFT, rt5639_mono_adc_l1_src);
1067
1068static const struct snd_kcontrol_new rt5639_mono_adc_l1_mux =
1069 SOC_DAPM_ENUM("Mono ADC1 left source", rt5639_mono_adc_l1_enum);
1070
1071static const char *rt5639_mono_adc_l2_src[] =
1072 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1073
1074static const SOC_ENUM_SINGLE_DECL(
1075 rt5639_mono_adc_l2_enum, RT5639_MONO_ADC_MIXER,
1076 RT5639_MONO_ADC_L2_SRC_SFT, rt5639_mono_adc_l2_src);
1077
1078static const struct snd_kcontrol_new rt5639_mono_adc_l2_mux =
1079 SOC_DAPM_ENUM("Mono ADC2 left source", rt5639_mono_adc_l2_enum);
1080
1081static const char *rt5639_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1082
1083static const SOC_ENUM_SINGLE_DECL(
1084 rt5639_mono_adc_r1_enum, RT5639_MONO_ADC_MIXER,
1085 RT5639_MONO_ADC_R1_SRC_SFT, rt5639_mono_adc_r1_src);
1086
1087static const struct snd_kcontrol_new rt5639_mono_adc_r1_mux =
1088 SOC_DAPM_ENUM("Mono ADC1 right source", rt5639_mono_adc_r1_enum);
1089
1090static const char *rt5639_mono_adc_r2_src[] =
1091 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1092
1093static const SOC_ENUM_SINGLE_DECL(
1094 rt5639_mono_adc_r2_enum, RT5639_MONO_ADC_MIXER,
1095 RT5639_MONO_ADC_R2_SRC_SFT, rt5639_mono_adc_r2_src);
1096
1097static const struct snd_kcontrol_new rt5639_mono_adc_r2_mux =
1098 SOC_DAPM_ENUM("Mono ADC2 right source", rt5639_mono_adc_r2_enum);
1099
1100/* DAC2 channel source */
1101static const char *rt5639_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1102
1103static const SOC_ENUM_SINGLE_DECL(rt5639_dac_l2_enum, RT5639_DSP_PATH2,
1104 RT5639_DAC_L2_SEL_SFT, rt5639_dac_l2_src);
1105
1106static const struct snd_kcontrol_new rt5639_dac_l2_mux =
1107 SOC_DAPM_ENUM("DAC2 left channel source", rt5639_dac_l2_enum);
1108
1109static const char *rt5639_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1110
1111static const SOC_ENUM_SINGLE_DECL(
1112 rt5639_dac_r2_enum, RT5639_DSP_PATH2,
1113 RT5639_DAC_R2_SEL_SFT, rt5639_dac_r2_src);
1114
1115static const struct snd_kcontrol_new rt5639_dac_r2_mux =
1116 SOC_DAPM_ENUM("DAC2 right channel source", rt5639_dac_r2_enum);
1117
1118/* Interface 2 ADC channel source */
1119static const char *rt5639_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1120
1121static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_l_enum, RT5639_DSP_PATH2,
1122 RT5639_IF2_ADC_L_SEL_SFT, rt5639_if2_adc_l_src);
1123
1124static const struct snd_kcontrol_new rt5639_if2_adc_l_mux =
1125 SOC_DAPM_ENUM("IF2 ADC left channel source", rt5639_if2_adc_l_enum);
1126
1127static const char *rt5639_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1128
1129static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_r_enum, RT5639_DSP_PATH2,
1130 RT5639_IF2_ADC_R_SEL_SFT, rt5639_if2_adc_r_src);
1131
1132static const struct snd_kcontrol_new rt5639_if2_adc_r_mux =
1133 SOC_DAPM_ENUM("IF2 ADC right channel source", rt5639_if2_adc_r_enum);
1134
1135/* digital interface and iis interface map */
1136static const char *rt5639_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1137 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1138 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1139
1140static const SOC_ENUM_SINGLE_DECL(
1141 rt5639_dai_iis_map_enum, RT5639_I2S1_SDP,
1142 RT5639_I2S_IF_SFT, rt5639_dai_iis_map);
1143
1144static const struct snd_kcontrol_new rt5639_dai_mux =
1145 SOC_DAPM_ENUM("DAI select", rt5639_dai_iis_map_enum);
1146
1147/* SDI select */
1148static const char *rt5639_sdi_sel[] = {"IF1", "IF2"};
1149
1150static const SOC_ENUM_SINGLE_DECL(
1151 rt5639_sdi_sel_enum, RT5639_I2S2_SDP,
1152 RT5639_I2S2_SDI_SFT, rt5639_sdi_sel);
1153
1154static const struct snd_kcontrol_new rt5639_sdi_mux =
1155 SOC_DAPM_ENUM("SDI select", rt5639_sdi_sel_enum);
1156
1157static int spk_event(struct snd_soc_dapm_widget *w,
1158 struct snd_kcontrol *kcontrol, int event)
1159{
1160 struct snd_soc_codec *codec = w->codec;
1161
1162 switch (event) {
1163 case SND_SOC_DAPM_POST_PMU:
1164 printk("spk_event --SND_SOC_DAPM_POST_PMU\n");
1165 snd_soc_update_bits(codec, RT5639_PWR_DIG1,
1166 RT5639_PWR_CLS_D, RT5639_PWR_CLS_D);
1167 rt5639_index_update_bits(codec, 0x1c, 0xf000, 0xf000);
1168 //rt5639_index_write(codec,0x1c,0xfd21);
1169 break;
1170
1171 case SND_SOC_DAPM_PRE_PMD:
1172 printk("spk_event --SND_SOC_DAPM_POST_PMD\n");
1173 //rt5639_index_write(codec,0x1c,0xfd00);
1174 rt5639_index_update_bits(codec, 0x1c, 0xf000, 0x0000);
1175 snd_soc_update_bits(codec,RT5639_PWR_DIG1,
1176 RT5639_PWR_CLS_D, 0);
1177 break;
1178
1179 default:
1180 return 0;
1181 }
1182
1183 return 0;
1184}
1185
1186static int hp_event(struct snd_soc_dapm_widget *w,
1187 struct snd_kcontrol *kcontrol, int event)
1188{
1189 struct snd_soc_codec *codec = w->codec;
1190
1191 switch (event) {
1192 case SND_SOC_DAPM_POST_PMU:
1193 printk("hp_event --SND_SOC_DAPM_POST_PMU\n");
1194 break;
1195
1196 case SND_SOC_DAPM_PRE_PMD:
1197 printk("hp_event --SND_SOC_DAPM_POST_PMD\n");
1198 break;
1199
1200 default:
1201 return 0;
1202 }
1203
1204 return 0;
1205}
1206
1207static const struct snd_soc_dapm_widget rt5639_dapm_widgets[] = {
1208 SND_SOC_DAPM_SUPPLY("PLL1", RT5639_PWR_ANLG2,
1209 RT5639_PWR_PLL_BIT, 0, NULL, 0),
1210 /* Input Side */
1211 /* micbias */
1212 SND_SOC_DAPM_SUPPLY("LDO2", RT5639_PWR_ANLG1,
1213 RT5639_PWR_LDO2_BIT, 0, NULL, 0),
1214 SND_SOC_DAPM_MICBIAS("micbias1", RT5639_PWR_ANLG2,
1215 RT5639_PWR_MB1_BIT, 0),
1216 SND_SOC_DAPM_MICBIAS("micbias2", RT5639_PWR_ANLG2,
1217 RT5639_PWR_MB2_BIT, 0),
1218 /* Input Lines */
1219
1220 SND_SOC_DAPM_INPUT("MIC1"),
1221 SND_SOC_DAPM_INPUT("MIC2"),
1222 SND_SOC_DAPM_INPUT("DMIC1"),
1223 SND_SOC_DAPM_INPUT("DMIC2"),
1224
1225 SND_SOC_DAPM_INPUT("IN1P"),
1226 SND_SOC_DAPM_INPUT("IN1N"),
1227 SND_SOC_DAPM_INPUT("IN2P"),
1228 SND_SOC_DAPM_INPUT("IN2N"),
1229 SND_SOC_DAPM_INPUT("DMIC L1"),
1230 SND_SOC_DAPM_INPUT("DMIC R1"),
1231 SND_SOC_DAPM_INPUT("DMIC L2"),
1232 SND_SOC_DAPM_INPUT("DMIC R2"),
1233 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1234 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1235 /* Boost */
1236 SND_SOC_DAPM_PGA("BST1", RT5639_PWR_ANLG2,
1237 RT5639_PWR_BST1_BIT, 0, NULL, 0),
1238 SND_SOC_DAPM_PGA("BST2", RT5639_PWR_ANLG2,
1239 RT5639_PWR_BST4_BIT, 0, NULL, 0),
1240 /* Input Volume */
1241 SND_SOC_DAPM_PGA("INL VOL", RT5639_PWR_VOL,
1242 RT5639_PWR_IN_L_BIT, 0, NULL, 0),
1243 SND_SOC_DAPM_PGA("INR VOL", RT5639_PWR_VOL,
1244 RT5639_PWR_IN_R_BIT, 0, NULL, 0),
1245 /* IN Mux */
1246 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5639_inl_mux),
1247 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5639_inr_mux),
1248 /* REC Mixer */
1249 SND_SOC_DAPM_MIXER("RECMIXL", RT5639_PWR_MIXER, RT5639_PWR_RM_L_BIT, 0,
1250 rt5639_rec_l_mix, ARRAY_SIZE(rt5639_rec_l_mix)),
1251 SND_SOC_DAPM_MIXER("RECMIXR", RT5639_PWR_MIXER, RT5639_PWR_RM_R_BIT, 0,
1252 rt5639_rec_r_mix, ARRAY_SIZE(rt5639_rec_r_mix)),
1253 /* ADCs */
1254 SND_SOC_DAPM_ADC("ADC L", NULL, RT5639_PWR_DIG1,
1255 RT5639_PWR_ADC_L_BIT, 0),
1256 SND_SOC_DAPM_ADC("ADC R", NULL, RT5639_PWR_DIG1,
1257 RT5639_PWR_ADC_R_BIT, 0),
1258 /* ADC Mux */
1259 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1260 &rt5639_sto_adc_l2_mux),
1261 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1262 &rt5639_sto_adc_r2_mux),
1263 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1264 &rt5639_sto_adc_l1_mux),
1265 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1266 &rt5639_sto_adc_r1_mux),
1267 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1268 &rt5639_mono_adc_l2_mux),
1269 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1270 &rt5639_mono_adc_l1_mux),
1271 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1272 &rt5639_mono_adc_r1_mux),
1273 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1274 &rt5639_mono_adc_r2_mux),
1275 /* ADC Mixer */
1276 SND_SOC_DAPM_SUPPLY("stereo filter", RT5639_PWR_DIG2,
1277 RT5639_PWR_ADC_SF_BIT, 0, NULL, 0),
1278 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1279 rt5639_sto_adc_l_mix, ARRAY_SIZE(rt5639_sto_adc_l_mix)),
1280 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1281 rt5639_sto_adc_r_mix, ARRAY_SIZE(rt5639_sto_adc_r_mix)),
1282 SND_SOC_DAPM_SUPPLY("mono left filter", RT5639_PWR_DIG2,
1283 RT5639_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1284 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1285 rt5639_mono_adc_l_mix, ARRAY_SIZE(rt5639_mono_adc_l_mix)),
1286 SND_SOC_DAPM_SUPPLY("mono right filter", RT5639_PWR_DIG2,
1287 RT5639_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1288 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1289 rt5639_mono_adc_r_mix, ARRAY_SIZE(rt5639_mono_adc_r_mix)),
1290
1291 /* IF2 Mux */
1292 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
1293 &rt5639_if2_adc_l_mux),
1294 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
1295 &rt5639_if2_adc_r_mux),
1296
1297 /* Digital Interface */
1298 SND_SOC_DAPM_SUPPLY("I2S1", RT5639_PWR_DIG1,
1299 RT5639_PWR_I2S1_BIT, 0, NULL, 0),
1300 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1301 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1302 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1303 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1305 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1306 SND_SOC_DAPM_SUPPLY("I2S2", RT5639_PWR_DIG1,
1307 RT5639_PWR_I2S2_BIT, 0, NULL, 0),
1308 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1309 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1310 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1311 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1312 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1313 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1314 SND_SOC_DAPM_SUPPLY("I2S3", RT5639_PWR_DIG1,
1315 RT5639_PWR_I2S3_BIT, 0, NULL, 0),
1316 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1317 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1318 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1319 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1320 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1321 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1322
1323 /* Digital Interface Select */
1324 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1325 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1326 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1327 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1328 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_sdi_mux),
1329
1330 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1331 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1332 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1333 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1334 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_sdi_mux),
1335
1336 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1337 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
1338
1339 /* Audio Interface */
1340 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1341 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1342 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1343 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1344 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1345 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1346
1347 /* Audio DSP */
1348 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1349
1350 /* ANC */
1351 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1352
1353 /* Output Side */
1354 /* DAC mixer before sound effect */
1355 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1356 rt5639_dac_l_mix, ARRAY_SIZE(rt5639_dac_l_mix)),
1357 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1358 rt5639_dac_r_mix, ARRAY_SIZE(rt5639_dac_r_mix)),
1359
1360 /* DAC2 channel Mux */
1361 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1362 &rt5639_dac_l2_mux),
1363 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1364 &rt5639_dac_r2_mux),
1365
1366 /* DAC Mixer */
1367 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1368 rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
1369 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1370 rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
1371 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1372 rt5639_mono_dac_l_mix, ARRAY_SIZE(rt5639_mono_dac_l_mix)),
1373 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1374 rt5639_mono_dac_r_mix, ARRAY_SIZE(rt5639_mono_dac_r_mix)),
1375 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
1376 rt5639_dig_l_mix, ARRAY_SIZE(rt5639_dig_l_mix)),
1377 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
1378 rt5639_dig_r_mix, ARRAY_SIZE(rt5639_dig_r_mix)),
1379 /* DACs */
1380 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5639_PWR_DIG1,
1381 RT5639_PWR_DAC_L1_BIT, 0),
1382 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5639_PWR_DIG1,
1383 RT5639_PWR_DAC_L2_BIT, 0),
1384 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5639_PWR_DIG1,
1385 RT5639_PWR_DAC_R1_BIT, 0),
1386 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5639_PWR_DIG1,
1387 RT5639_PWR_DAC_R2_BIT, 0),
1388 /* SPK/OUT Mixer */
1389 SND_SOC_DAPM_MIXER("SPK MIXL", RT5639_PWR_MIXER, RT5639_PWR_SM_L_BIT,
1390 0, rt5639_spk_l_mix, ARRAY_SIZE(rt5639_spk_l_mix)),
1391 SND_SOC_DAPM_MIXER("SPK MIXR", RT5639_PWR_MIXER, RT5639_PWR_SM_R_BIT,
1392 0, rt5639_spk_r_mix, ARRAY_SIZE(rt5639_spk_r_mix)),
1393 SND_SOC_DAPM_MIXER("OUT MIXL", RT5639_PWR_MIXER, RT5639_PWR_OM_L_BIT,
1394 0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
1395 SND_SOC_DAPM_MIXER("OUT MIXR", RT5639_PWR_MIXER, RT5639_PWR_OM_R_BIT,
1396 0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
1397 /* Ouput Volume */
1398 SND_SOC_DAPM_PGA("SPKVOL L", RT5639_PWR_VOL,
1399 RT5639_PWR_SV_L_BIT, 0, NULL, 0),
1400 SND_SOC_DAPM_PGA("SPKVOL R", RT5639_PWR_VOL,
1401 RT5639_PWR_SV_R_BIT, 0, NULL, 0),
1402 SND_SOC_DAPM_PGA("OUTVOL L", RT5639_PWR_VOL,
1403 RT5639_PWR_OV_L_BIT, 0, NULL, 0),
1404 SND_SOC_DAPM_PGA("OUTVOL R", RT5639_PWR_VOL,
1405 RT5639_PWR_OV_R_BIT, 0, NULL, 0),
1406 SND_SOC_DAPM_PGA("HPOVOL L", RT5639_PWR_VOL,
1407 RT5639_PWR_HV_L_BIT, 0, NULL, 0),
1408 SND_SOC_DAPM_PGA("HPOVOL R", RT5639_PWR_VOL,
1409 RT5639_PWR_HV_R_BIT, 0, NULL, 0),
1410 /* SPO/HPO/LOUT/Mono Mixer */
1411 SND_SOC_DAPM_MIXER("SPOL MIX",SND_SOC_NOPM, 0,
1412 0, rt5639_spo_l_mix, ARRAY_SIZE(rt5639_spo_l_mix)),
1413 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1414 0, rt5639_spo_r_mix, ARRAY_SIZE(rt5639_spo_r_mix)),
1415 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1416 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1417 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1418 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1419 SND_SOC_DAPM_MIXER("LOUT MIX", RT5639_PWR_ANLG1, RT5639_PWR_LM_BIT, 0,
1420 rt5639_lout_mix, ARRAY_SIZE(rt5639_lout_mix)),
1421 SND_SOC_DAPM_MIXER("Mono MIX", RT5639_PWR_ANLG1, RT5639_PWR_MM_BIT, 0,
1422 rt5639_mono_mix, ARRAY_SIZE(rt5639_mono_mix)),
1423
1424 SND_SOC_DAPM_SUPPLY("Improve mono amp drv", RT5639_PWR_ANLG1,
1425 RT5639_PWR_MA_BIT, 0, NULL, 0),
1426
1427 SND_SOC_DAPM_SUPPLY("Improve HP amp drv", RT5639_PWR_ANLG1,
1428 SND_SOC_NOPM, 0, hp_event,SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1429
1430 SND_SOC_DAPM_PGA("HP L amp", RT5639_PWR_ANLG1,
1431 RT5639_PWR_HP_L_BIT, 0, NULL, 0),
1432
1433 SND_SOC_DAPM_PGA("HP R amp", RT5639_PWR_ANLG1,
1434 RT5639_PWR_HP_R_BIT, 0, NULL, 0),
1435
1436 SND_SOC_DAPM_SUPPLY("Improve SPK amp drv", SND_SOC_NOPM, 0, 0,
1437 spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1438
1439 /* Output Lines */
1440 SND_SOC_DAPM_OUTPUT("SPOLP"),
1441 SND_SOC_DAPM_OUTPUT("SPOLN"),
1442 SND_SOC_DAPM_OUTPUT("SPORP"),
1443 SND_SOC_DAPM_OUTPUT("SPORN"),
1444 SND_SOC_DAPM_OUTPUT("HPOL"),
1445 SND_SOC_DAPM_OUTPUT("HPOR"),
1446 SND_SOC_DAPM_OUTPUT("LOUTL"),
1447 SND_SOC_DAPM_OUTPUT("LOUTR"),
1448};
1449
1450static const struct snd_soc_dapm_route rt5639_dapm_routes[] = {
1451 {"IN1P", NULL, "LDO2"},
1452 {"IN2P", NULL, "LDO2"},
1453
1454 {"IN1P", NULL, "MIC1"},
1455 {"IN1N", NULL, "MIC1"},
1456 {"IN2P", NULL, "MIC2"},
1457 {"IN2N", NULL, "MIC2"},
1458
1459 {"DMIC L1", NULL, "DMIC1"},
1460 {"DMIC R1", NULL, "DMIC1"},
1461 {"DMIC L2", NULL, "DMIC2"},
1462 {"DMIC R2", NULL, "DMIC2"},
1463
1464 {"BST1", NULL, "IN1P"},
1465 {"BST1", NULL, "IN1N"},
1466 {"BST2", NULL, "IN2P"},
1467 {"BST2", NULL, "IN2N"},
1468
1469 {"INL VOL", NULL, "IN2P"},
1470 {"INR VOL", NULL, "IN2N"},
1471
1472 {"RECMIXL", "HPOL Switch", "HPOL"},
1473 {"RECMIXL", "INL Switch", "INL VOL"},
1474 {"RECMIXL", "BST2 Switch", "BST2"},
1475 {"RECMIXL", "BST1 Switch", "BST1"},
1476 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
1477
1478 {"RECMIXR", "HPOR Switch", "HPOR"},
1479 {"RECMIXR", "INR Switch", "INR VOL"},
1480 {"RECMIXR", "BST2 Switch", "BST2"},
1481 {"RECMIXR", "BST1 Switch", "BST1"},
1482 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
1483
1484 {"ADC L", NULL, "RECMIXL"},
1485 {"ADC R", NULL, "RECMIXR"},
1486
1487 {"DMIC L1", NULL, "DMIC CLK"},
1488 {"DMIC L2", NULL, "DMIC CLK"},
1489
1490 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1491 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1492 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1493 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
1494 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
1495
1496 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1497 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1498 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1499 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1500 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1501
1502 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1503 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1504 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1505 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1506 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
1507
1508 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1509 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1510 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1511 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1512 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1513
1514 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1515 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1516 {"Stereo ADC MIXL", NULL, "stereo filter"},
1517 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
1518
1519 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1520 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1521 {"Stereo ADC MIXR", NULL, "stereo filter"},
1522 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
1523
1524 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1525 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1526 {"Mono ADC MIXL", NULL, "mono left filter"},
1527 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
1528
1529 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1530 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1531 {"Mono ADC MIXR", NULL, "mono right filter"},
1532 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
1533
1534 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
1535 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
1536
1537 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
1538 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
1539 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
1540 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
1541 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
1542 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
1543
1544 {"IF1 ADC", NULL, "I2S1"},
1545 {"IF1 ADC", NULL, "IF1 ADC L"},
1546 {"IF1 ADC", NULL, "IF1 ADC R"},
1547 {"IF2 ADC", NULL, "I2S2"},
1548 {"IF2 ADC", NULL, "IF2 ADC L"},
1549 {"IF2 ADC", NULL, "IF2 ADC R"},
1550 {"IF3 ADC", NULL, "I2S3"},
1551 {"IF3 ADC", NULL, "IF3 ADC L"},
1552 {"IF3 ADC", NULL, "IF3 ADC R"},
1553
1554 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
1555 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
1556 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
1557 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
1558 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
1559 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
1560 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
1561 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
1562 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
1563 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
1564
1565 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
1566 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
1567 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
1568 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
1569 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
1570 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
1571 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
1572 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
1573 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
1574 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
1575
1576 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
1577 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
1578 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
1579 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
1580 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
1581 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
1582 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
1583 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
1584
1585 {"AIF1TX", NULL, "DAI1 TX Mux"},
1586 {"AIF1TX", NULL, "SDI1 TX Mux"},
1587 {"AIF2TX", NULL, "DAI2 TX Mux"},
1588 {"AIF2TX", NULL, "SDI2 TX Mux"},
1589 {"AIF3TX", NULL, "DAI3 TX Mux"},
1590
1591 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
1592 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
1593 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
1594 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
1595 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
1596 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
1597 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
1598 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
1599
1600 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
1601 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
1602 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
1603 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
1604 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
1605 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
1606 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
1607 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
1608
1609 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
1610 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
1611 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
1612 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
1613 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
1614 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
1615 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
1616 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
1617
1618 {"IF1 DAC", NULL, "I2S1"},
1619 {"IF1 DAC", NULL, "DAI1 RX Mux"},
1620 {"IF2 DAC", NULL, "I2S2"},
1621 {"IF2 DAC", NULL, "DAI2 RX Mux"},
1622 {"IF3 DAC", NULL, "I2S3"},
1623 {"IF3 DAC", NULL, "DAI3 RX Mux"},
1624
1625 {"IF1 DAC L", NULL, "IF1 DAC"},
1626 {"IF1 DAC R", NULL, "IF1 DAC"},
1627 {"IF2 DAC L", NULL, "IF2 DAC"},
1628 {"IF2 DAC R", NULL, "IF2 DAC"},
1629 {"IF3 DAC L", NULL, "IF3 DAC"},
1630 {"IF3 DAC R", NULL, "IF3 DAC"},
1631
1632 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
1633 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
1634 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1635 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
1636
1637 {"ANC", NULL, "Stereo ADC MIXL"},
1638 {"ANC", NULL, "Stereo ADC MIXR"},
1639
1640 {"Audio DSP", NULL, "DAC MIXL"},
1641 {"Audio DSP", NULL, "DAC MIXR"},
1642
1643 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1644 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
1645 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1646
1647 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1648 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
1649
1650 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1651 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1652 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1653 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1654 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1655 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1656
1657 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1658 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1659 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1660 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1661 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1662 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1663
1664 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
1665 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1666 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1667 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1668
1669 {"DAC L1", NULL, "Stereo DAC MIXL"},
1670 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
1671 {"DAC R1", NULL, "Stereo DAC MIXR"},
1672 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
1673
1674 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1675 {"SPK MIXL", "INL Switch", "INL VOL"},
1676 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
1677 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1678 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1679 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1680 {"SPK MIXR", "INR Switch", "INR VOL"},
1681 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1682 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1683 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1684
1685 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1686 {"OUT MIXL", "BST1 Switch", "BST1"},
1687 {"OUT MIXL", "INL Switch", "INL VOL"},
1688 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1689 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1690 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1691 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1692
1693 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1694 {"OUT MIXR", "BST2 Switch", "BST2"},
1695 {"OUT MIXR", "BST1 Switch", "BST1"},
1696 {"OUT MIXR", "INR Switch", "INR VOL"},
1697 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1698 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1699 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1700 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1701
1702 {"SPKVOL L", NULL, "SPK MIXL"},
1703 {"SPKVOL R", NULL, "SPK MIXR"},
1704 {"HPOVOL L", NULL, "OUT MIXL"},
1705 {"HPOVOL R", NULL, "OUT MIXR"},
1706 {"OUTVOL L", NULL, "OUT MIXL"},
1707 {"OUTVOL R", NULL, "OUT MIXR"},
1708
1709 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1710 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
1711 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
1712 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
1713 {"SPOL MIX", "BST1 Switch", "BST1"},
1714 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1715 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1716 {"SPOR MIX", "BST1 Switch", "BST1"},
1717
1718 {"HPOL MIX", "DAC2 Switch", "DAC L2"},
1719 {"HPOL MIX", "DAC1 Switch", "DAC L1"},
1720 {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
1721 {"HPOR MIX", "DAC2 Switch", "DAC R2"},
1722 {"HPOR MIX", "DAC1 Switch", "DAC R1"},
1723 {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
1724
1725 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1726 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1727 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1728 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1729
1730 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1731 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1732 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1733 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1734 {"Mono MIX", "BST1 Switch", "BST1"},
1735
1736 {"SPOLP", NULL, "Improve SPK amp drv"},
1737 {"SPOLN", NULL, "Improve SPK amp drv"},
1738 {"SPORP", NULL, "Improve SPK amp drv"},
1739 {"SPORN", NULL, "Improve SPK amp drv"},
1740 {"SPOLP", NULL, "SPOL MIX"},
1741 {"SPOLN", NULL, "SPOL MIX"},
1742 {"SPORP", NULL, "SPOR MIX"},
1743 {"SPORN", NULL, "SPOR MIX"},
1744
1745 {"HP L amp", NULL, "HPOL MIX"},
1746 {"HP R amp", NULL, "HPOR MIX"},
1747 {"HPOL", NULL, "Improve HP amp drv"},
1748 {"HPOR", NULL, "Improve HP amp drv"},
1749 {"HPOL", NULL, "HP L amp"},
1750 {"HPOR", NULL, "HP R amp"},
1751
1752 {"LOUTL", NULL, "LOUT MIX"},
1753 {"LOUTR", NULL, "LOUT MIX"},
1754};
1755
1756static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1757{
1758 int ret = 0, val = snd_soc_read(codec, RT5639_I2S1_SDP);
1759
1760 if(codec == NULL)
1761 return -EINVAL;
1762
1763 val = (val & RT5639_I2S_IF_MASK) >> RT5639_I2S_IF_SFT;
1764 switch (dai_id) {
1765 case RT5639_AIF1:
1766 if (val == RT5639_IF_123 || val == RT5639_IF_132 ||
1767 val == RT5639_IF_113)
1768 ret |= RT5639_U_IF1;
1769 if (val == RT5639_IF_312 || val == RT5639_IF_213 ||
1770 val == RT5639_IF_113)
1771 ret |= RT5639_U_IF2;
1772 if (val == RT5639_IF_321 || val == RT5639_IF_231)
1773 ret |= RT5639_U_IF3;
1774 break;
1775
1776 case RT5639_AIF2:
1777 if (val == RT5639_IF_231 || val == RT5639_IF_213 ||
1778 val == RT5639_IF_223)
1779 ret |= RT5639_U_IF1;
1780 if (val == RT5639_IF_123 || val == RT5639_IF_321 ||
1781 val == RT5639_IF_223)
1782 ret |= RT5639_U_IF2;
1783 if (val == RT5639_IF_132 || val == RT5639_IF_312)
1784 ret |= RT5639_U_IF3;
1785 break;
1786
1787 default:
1788 ret = -EINVAL;
1789 break;
1790 }
1791
1792 return ret;
1793}
1794
1795static int get_clk_info(int sclk, int rate)
1796{
1797 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1798
1799 if(sclk <= 0 || rate <= 0)
1800 return -EINVAL;
1801
1802 rate = rate << 8;
1803 for (i = 0; i < ARRAY_SIZE(pd); i++)
1804 if (sclk == rate * pd[i])
1805 return i;
1806
1807 return -EINVAL;
1808}
1809
1810static int rt5639_hw_params(struct snd_pcm_substream *substream,
1811 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1812{
1813 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1814 struct snd_soc_codec *codec = rtd->codec;
1815 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
1816 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
1817 int pre_div, bclk_ms, frame_size;
1818
1819 rt5639->lrck[dai->id] = params_rate(params);
1820 pre_div = get_clk_info(rt5639->sysclk, rt5639->lrck[dai->id]);
1821 if (pre_div < 0) {
1822 dev_err(codec->dev, "Unsupported clock setting\n");
1823 return -EINVAL;
1824 }
1825 frame_size = snd_soc_params_to_frame_size(params);
1826 if (frame_size < 0) {
1827 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1828 return -EINVAL;
1829 }
1830 bclk_ms = frame_size > 32 ? 1 : 0;
1831 rt5639->bclk[dai->id] = rt5639->lrck[dai->id] * (32 << bclk_ms);
1832
1833 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1834 rt5639->bclk[dai->id], rt5639->lrck[dai->id]);
1835 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1836 bclk_ms, pre_div, dai->id);
1837
1838 switch (params_format(params)) {
1839 case SNDRV_PCM_FORMAT_S16_LE:
1840 break;
1841 case SNDRV_PCM_FORMAT_S20_3LE:
1842 val_len |= RT5639_I2S_DL_20;
1843 break;
1844 case SNDRV_PCM_FORMAT_S24_LE:
1845 val_len |= RT5639_I2S_DL_24;
1846 break;
1847 case SNDRV_PCM_FORMAT_S8:
1848 val_len |= RT5639_I2S_DL_8;
1849 break;
1850 default:
1851 return -EINVAL;
1852 }
1853
1854 dai_sel = get_sdp_info(codec, dai->id);
1855 if (dai_sel < 0) {
1856 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1857 return -EINVAL;
1858 }
1859 if (dai_sel & RT5639_U_IF1) {
1860 mask_clk = RT5639_I2S_BCLK_MS1_MASK | RT5639_I2S_PD1_MASK;
1861 val_clk = bclk_ms << RT5639_I2S_BCLK_MS1_SFT |
1862 pre_div << RT5639_I2S_PD1_SFT;
1863 snd_soc_update_bits(codec, RT5639_I2S1_SDP,
1864 RT5639_I2S_DL_MASK, val_len);
1865 snd_soc_update_bits(codec, RT5639_ADDA_CLK1, mask_clk, val_clk);
1866 }
1867 if (dai_sel & RT5639_U_IF2) {
1868 mask_clk = RT5639_I2S_BCLK_MS2_MASK | RT5639_I2S_PD2_MASK;
1869 val_clk = bclk_ms << RT5639_I2S_BCLK_MS2_SFT |
1870 pre_div << RT5639_I2S_PD2_SFT;
1871 snd_soc_update_bits(codec, RT5639_I2S2_SDP,
1872 RT5639_I2S_DL_MASK, val_len);
1873 snd_soc_update_bits(codec, RT5639_ADDA_CLK1, mask_clk, val_clk);
1874 }
1875
1876 return 0;
1877}
1878
1879static int rt5639_prepare(struct snd_pcm_substream *substream,
1880 struct snd_soc_dai *dai)
1881{
1882 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1883 struct snd_soc_codec *codec = rtd->codec;
1884 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
1885
1886 rt5639->aif_pu = dai->id;
1887 return 0;
1888}
1889
1890static int rt5639_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1891{
1892 struct snd_soc_codec *codec = dai->codec;
1893 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
1894 unsigned int reg_val = 0, dai_sel;
1895
1896 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1897 case SND_SOC_DAIFMT_CBM_CFM:
1898 rt5639->master[dai->id] = 1;
1899 break;
1900 case SND_SOC_DAIFMT_CBS_CFS:
1901 reg_val |= RT5639_I2S_MS_S;
1902 rt5639->master[dai->id] = 0;
1903 break;
1904 default:
1905 return -EINVAL;
1906 }
1907
1908 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1909 case SND_SOC_DAIFMT_NB_NF:
1910 break;
1911 case SND_SOC_DAIFMT_IB_NF:
1912 reg_val |= RT5639_I2S_BP_INV;
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1919 case SND_SOC_DAIFMT_I2S:
1920 break;
1921 case SND_SOC_DAIFMT_LEFT_J:
1922 reg_val |= RT5639_I2S_DF_LEFT;
1923 break;
1924 case SND_SOC_DAIFMT_DSP_A:
1925 reg_val |= RT5639_I2S_DF_PCM_A;
1926 break;
1927 case SND_SOC_DAIFMT_DSP_B:
1928 reg_val |= RT5639_I2S_DF_PCM_B;
1929 break;
1930 default:
1931 return -EINVAL;
1932 }
1933
1934 dai_sel = get_sdp_info(codec, dai->id);
1935 if (dai_sel < 0) {
1936 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1937 return -EINVAL;
1938 }
1939 if (dai_sel & RT5639_U_IF1) {
1940 snd_soc_update_bits(codec, RT5639_I2S1_SDP,
1941 RT5639_I2S_MS_MASK | RT5639_I2S_BP_MASK |
1942 RT5639_I2S_DF_MASK, reg_val);
1943 }
1944 if (dai_sel & RT5639_U_IF2) {
1945 snd_soc_update_bits(codec, RT5639_I2S2_SDP,
1946 RT5639_I2S_MS_MASK | RT5639_I2S_BP_MASK |
1947 RT5639_I2S_DF_MASK, reg_val);
1948 }
1949
1950 return 0;
1951}
1952
1953static int rt5639_set_dai_sysclk(struct snd_soc_dai *dai,
1954 int clk_id, unsigned int freq, int dir)
1955{
1956 struct snd_soc_codec *codec = dai->codec;
1957 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
1958 unsigned int reg_val = 0;
1959
1960 if (freq == rt5639->sysclk && clk_id == rt5639->sysclk_src)
1961 return 0;
1962
1963 switch (clk_id) {
1964 case RT5639_SCLK_S_MCLK:
1965 reg_val |= RT5639_SCLK_SRC_MCLK;
1966 break;
1967 case RT5639_SCLK_S_PLL1:
1968 reg_val |= RT5639_SCLK_SRC_PLL1;
1969 break;
1970 case RT5639_SCLK_S_RCCLK:
1971 reg_val |= RT5639_SCLK_SRC_RCCLK;
1972 break;
1973 default:
1974 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1975 return -EINVAL;
1976 }
1977 snd_soc_update_bits(codec, RT5639_GLB_CLK,
1978 RT5639_SCLK_SRC_MASK, reg_val);
1979 rt5639->sysclk = freq;
1980 rt5639->sysclk_src = clk_id;
1981
1982 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1983
1984 return 0;
1985}
1986
1987/**
1988 * rt5639_pll_calc - Calcualte PLL M/N/K code.
1989 * @freq_in: external clock provided to codec.
1990 * @freq_out: target clock which codec works on.
1991 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1992 *
1993 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1994 * which make calculation more efficiently.
1995 *
1996 * Returns 0 for success or negative error code.
1997 */
1998static int rt5639_pll_calc(const unsigned int freq_in,
1999 const unsigned int freq_out, struct rt5639_pll_code *pll_code)
2000{
2001 int max_n = RT5639_PLL_N_MAX, max_m = RT5639_PLL_M_MAX;
2002 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
2003 bool bypass = false;
2004
2005 if (RT5639_PLL_INP_MAX < freq_in || RT5639_PLL_INP_MIN > freq_in)
2006 return -EINVAL;
2007
2008 for (n_t = 0; n_t <= max_n; n_t++) {
2009 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
2010 if (in_t < 0)
2011 continue;
2012 if (in_t == freq_out) {
2013 bypass = true;
2014 n = n_t;
2015 goto code_find;
2016 }
2017 for (m_t = 0; m_t <= max_m; m_t++) {
2018 out_t = in_t / (m_t + 2);
2019 red = abs(out_t - freq_out);
2020 if (red < red_t) {
2021 n = n_t;
2022 m = m_t;
2023 if(red == 0)
2024 goto code_find;
2025 red_t = red;
2026 }
2027 }
2028 }
2029 pr_debug("Only get approximation about PLL\n");
2030
2031code_find:
2032
2033 pll_code->m_bp = bypass;
2034 pll_code->m_code= m;
2035 pll_code->n_code = n;
2036 pll_code->k_code = 2;
2037 return 0;
2038}
2039
2040static int rt5639_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2041 unsigned int freq_in, unsigned int freq_out)
2042{
2043 struct snd_soc_codec *codec = dai->codec;
2044 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
2045 struct rt5639_pll_code pll_code;
2046 int ret, dai_sel;
2047
2048 if (source == rt5639->pll_src && freq_in == rt5639->pll_in &&
2049 freq_out == rt5639->pll_out)
2050 return 0;
2051
2052 if (!freq_in || !freq_out) {
2053 dev_dbg(codec->dev, "PLL disabled\n");
2054
2055 rt5639->pll_in = 0;
2056 rt5639->pll_out = 0;
2057 snd_soc_update_bits(codec, RT5639_GLB_CLK,
2058 RT5639_SCLK_SRC_MASK, RT5639_SCLK_SRC_MCLK);
2059 return 0;
2060 }
2061
2062 switch (source) {
2063 case RT5639_PLL1_S_MCLK:
2064 snd_soc_update_bits(codec, RT5639_GLB_CLK,
2065 RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_MCLK);
2066 break;
2067 case RT5639_PLL1_S_BCLK1:
2068 case RT5639_PLL1_S_BCLK2:
2069 dai_sel = get_sdp_info(codec, dai->id);
2070 if (dai_sel < 0) {
2071 dev_err(codec->dev,
2072 "Failed to get sdp info: %d\n", dai_sel);
2073 return -EINVAL;
2074 }
2075 if (dai_sel & RT5639_U_IF1) {
2076 snd_soc_update_bits(codec, RT5639_GLB_CLK,
2077 RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK1);
2078 }
2079 if (dai_sel & RT5639_U_IF2) {
2080 snd_soc_update_bits(codec, RT5639_GLB_CLK,
2081 RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK2);
2082 }
2083 if (dai_sel & RT5639_U_IF3) {
2084 snd_soc_update_bits(codec, RT5639_GLB_CLK,
2085 RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK3);
2086 }
2087 break;
2088 default:
2089 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2090 return -EINVAL;
2091 }
2092
2093 ret = rt5639_pll_calc(freq_in, freq_out, &pll_code);
2094 if (ret < 0) {
2095 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2096 return ret;
2097 }
2098
2099 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
2100 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
2101
2102 snd_soc_write(codec, RT5639_PLL_CTRL1,
2103 pll_code.n_code << RT5639_PLL_N_SFT | pll_code.k_code);
2104 snd_soc_write(codec, RT5639_PLL_CTRL2,
2105 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5639_PLL_M_SFT |
2106 pll_code.m_bp << RT5639_PLL_M_BP_SFT);
2107
2108 rt5639->pll_in = freq_in;
2109 rt5639->pll_out = freq_out;
2110 rt5639->pll_src = source;
2111
2112 return 0;
2113}
2114
2115/**
2116 * rt5639_index_show - Dump private registers.
2117 * @dev: codec device.
2118 * @attr: device attribute.
2119 * @buf: buffer for display.
2120 *
2121 * To show non-zero values of all private registers.
2122 *
2123 * Returns buffer length.
2124 */
2125static ssize_t rt5639_index_show(struct device *dev,
2126 struct device_attribute *attr, char *buf)
2127{
2128 struct i2c_client *client = to_i2c_client(dev);
2129 struct rt5639_priv *rt5639 = i2c_get_clientdata(client);
2130 struct snd_soc_codec *codec = rt5639->codec;
2131 unsigned int val;
2132 int cnt = 0, i;
2133
2134 cnt += sprintf(buf, "RT5639 index register\n");
2135 for (i = 0; i < 0xb4; i++) {
2136 if (cnt + RT5639_REG_DISP_LEN >= PAGE_SIZE)
2137 break;
2138 val = rt5639_index_read(codec, i);
2139 if (!val)
2140 continue;
2141 cnt += snprintf(buf + cnt, RT5639_REG_DISP_LEN,
2142 "%02x: %04x\n", i, val);
2143 }
2144
2145 if (cnt >= PAGE_SIZE)
2146 cnt = PAGE_SIZE - 1;
2147
2148 return cnt;
2149}
2150static DEVICE_ATTR(index_reg, 0444, rt5639_index_show, NULL);
2151
2152static int rt5639_set_bias_level(struct snd_soc_codec *codec,
2153 enum snd_soc_bias_level level)
2154{
2155 switch (level) {
2156 case SND_SOC_BIAS_ON:
2157#ifdef RT5639_DEMO
2158 snd_soc_update_bits(codec, RT5639_SPK_VOL,
2159 RT5639_L_MUTE | RT5639_R_MUTE, 0);
2160 snd_soc_update_bits(codec, RT5639_HP_VOL,
2161 RT5639_L_MUTE | RT5639_R_MUTE, 0);
2162#endif
2163 break;
2164
2165 case SND_SOC_BIAS_PREPARE:
2166#ifdef RT5639_DEMO
2167 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2168 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2169 RT5639_PWR_BG | RT5639_PWR_VREF2,
2170 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2171 RT5639_PWR_BG | RT5639_PWR_VREF2);
2172 msleep(100);
2173
2174 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2175 RT5639_PWR_FV1 | RT5639_PWR_FV2,
2176 RT5639_PWR_FV1 | RT5639_PWR_FV2);
2177
2178 snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
2179 RT5639_PWR_MB1 | RT5639_PWR_MB2,
2180 RT5639_PWR_MB1 | RT5639_PWR_MB2);
2181#endif
2182 break;
2183
2184 case SND_SOC_BIAS_STANDBY:
2185#ifdef RT5639_DEMO
2186 snd_soc_update_bits(codec, RT5639_SPK_VOL,
2187 RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
2188 snd_soc_update_bits(codec, RT5639_HP_VOL,
2189 RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
2190
2191 snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
2192 RT5639_PWR_MB1 | RT5639_PWR_MB2,
2193 0);
2194#endif
2195 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2196 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2197 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2198 RT5639_PWR_BG | RT5639_PWR_VREF2,
2199 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2200 RT5639_PWR_BG | RT5639_PWR_VREF2);
2201 msleep(10);
2202 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2203 RT5639_PWR_FV1 | RT5639_PWR_FV2,
2204 RT5639_PWR_FV1 | RT5639_PWR_FV2);
2205 codec->cache_only = false;
2206 snd_soc_cache_sync(codec);
2207 }
2208 break;
2209
2210 case SND_SOC_BIAS_OFF:
2211#ifdef RT5639_DEMO
2212 snd_soc_update_bits(codec, RT5639_SPK_VOL,
2213 RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
2214 snd_soc_update_bits(codec, RT5639_HP_VOL,
2215 RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
2216 snd_soc_update_bits(codec, RT5639_OUTPUT,
2217 RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
2218 snd_soc_update_bits(codec, RT5639_MONO_OUT,
2219 RT5639_L_MUTE, RT5639_L_MUTE);
2220#endif
2221 snd_soc_write(codec, RT5639_PWR_DIG1, 0x0000);
2222 snd_soc_write(codec, RT5639_PWR_DIG2, 0x0000);
2223 snd_soc_write(codec, RT5639_PWR_VOL, 0x0000);
2224 snd_soc_write(codec, RT5639_PWR_MIXER, 0x0000);
2225 snd_soc_write(codec, RT5639_PWR_ANLG1, 0x0000);
2226 snd_soc_write(codec, RT5639_PWR_ANLG2, 0x0000);
2227 break;
2228
2229 default:
2230 break;
2231 }
2232 codec->dapm.bias_level = level;
2233
2234 return 0;
2235}
2236
2237static int rt5639_probe(struct snd_soc_codec *codec)
2238{
2239 struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
2240 int ret;
2241
2242 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
2243 if (ret != 0) {
2244 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2245 return ret;
2246 }
2247
2248 rt5639_reset(codec);
2249 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2250 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2251 RT5639_PWR_BG | RT5639_PWR_VREF2,
2252 RT5639_PWR_VREF1 | RT5639_PWR_MB |
2253 RT5639_PWR_BG | RT5639_PWR_VREF2);
2254 msleep(100);
2255 snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
2256 RT5639_PWR_FV1 | RT5639_PWR_FV2,
2257 RT5639_PWR_FV1 | RT5639_PWR_FV2);
2258 /* DMIC */
2259 if (rt5639->dmic_en == RT5639_DMIC1) {
2260 snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
2261 RT5639_GP2_PIN_MASK, RT5639_GP2_PIN_DMIC1_SCL);
2262 snd_soc_update_bits(codec, RT5639_DMIC,
2263 RT5639_DMIC_1L_LH_MASK | RT5639_DMIC_1R_LH_MASK,
2264 RT5639_DMIC_1L_LH_FALLING | RT5639_DMIC_1R_LH_RISING);
2265 } else if (rt5639->dmic_en == RT5639_DMIC2) {
2266 snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
2267 RT5639_GP2_PIN_MASK, RT5639_GP2_PIN_DMIC1_SCL);
2268 snd_soc_update_bits(codec, RT5639_DMIC,
2269 RT5639_DMIC_2L_LH_MASK | RT5639_DMIC_2R_LH_MASK,
2270 RT5639_DMIC_2L_LH_FALLING | RT5639_DMIC_2R_LH_RISING);
2271 }
2272
2273#ifdef RT5639_DEMO
2274 rt5639_reg_init(codec);
2275#endif
2276
2277 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
2278
2279 snd_soc_add_controls(codec, rt5639_snd_controls,
2280 ARRAY_SIZE(rt5639_snd_controls));
2281
2282 rt5639->codec = codec;
2283 ret = device_create_file(codec->dev, &dev_attr_index_reg);
2284 if (ret != 0) {
2285 dev_err(codec->dev,
2286 "Failed to create index_reg sysfs files: %d\n", ret);
2287 return ret;
2288 }
2289
2290 return 0;
2291}
2292
2293static int rt5639_remove(struct snd_soc_codec *codec)
2294{
2295 rt5639_set_bias_level(codec, SND_SOC_BIAS_OFF);
2296 return 0;
2297}
2298
2299#ifdef CONFIG_PM
2300static int rt5639_suspend(struct snd_soc_codec *codec, pm_message_t state)
2301{
2302 rt5639_set_bias_level(codec, SND_SOC_BIAS_OFF);
2303 return 0;
2304}
2305
2306static int rt5639_resume(struct snd_soc_codec *codec)
2307{
2308 rt5639_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2309 return 0;
2310}
2311#else
2312#define rt5639_suspend NULL
2313#define rt5639_resume NULL
2314#endif
2315
2316#define RT5639_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2317#define RT5639_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2318 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2319
2320struct snd_soc_dai_ops rt5639_aif_dai_ops = {
2321 .hw_params = rt5639_hw_params,
2322 .prepare = rt5639_prepare,
2323 .set_fmt = rt5639_set_dai_fmt,
2324 .set_sysclk = rt5639_set_dai_sysclk,
2325 .set_pll = rt5639_set_dai_pll,
2326};
2327
2328struct snd_soc_dai_driver rt5639_dai[] = {
2329 {
2330 .name = "rt5639-aif1",
2331 .id = RT5639_AIF1,
2332 .playback = {
2333 .stream_name = "AIF1 Playback",
2334 .channels_min = 1,
2335 .channels_max = 2,
2336 .rates = RT5639_STEREO_RATES,
2337 .formats = RT5639_FORMATS,
2338 },
2339 .capture = {
2340 .stream_name = "AIF1 Capture",
2341 .channels_min = 1,
2342 .channels_max = 2,
2343 .rates = RT5639_STEREO_RATES,
2344 .formats = RT5639_FORMATS,
2345 },
2346 .ops = &rt5639_aif_dai_ops,
2347 },
2348 {
2349 .name = "rt5639-aif2",
2350 .id = RT5639_AIF2,
2351 .playback = {
2352 .stream_name = "AIF2 Playback",
2353 .channels_min = 1,
2354 .channels_max = 2,
2355 .rates = RT5639_STEREO_RATES,
2356 .formats = RT5639_FORMATS,
2357 },
2358 .capture = {
2359 .stream_name = "AIF2 Capture",
2360 .channels_min = 1,
2361 .channels_max = 2,
2362 .rates = RT5639_STEREO_RATES,
2363 .formats = RT5639_FORMATS,
2364 },
2365 .ops = &rt5639_aif_dai_ops,
2366 },
2367};
2368
2369static struct snd_soc_codec_driver soc_codec_dev_rt5639 = {
2370 .probe = rt5639_probe,
2371 .remove = rt5639_remove,
2372 .suspend = rt5639_suspend,
2373 .resume = rt5639_resume,
2374 .set_bias_level = rt5639_set_bias_level,
2375 .reg_cache_size = RT5639_VENDOR_ID2 + 1,
2376 .reg_word_size = sizeof(u16),
2377 .reg_cache_default = rt5639_reg,
2378 .volatile_register = rt5639_volatile_register,
2379 .readable_register = rt5639_readable_register,
2380 .reg_cache_step = 1,
2381 .dapm_widgets = rt5639_dapm_widgets,
2382 .num_dapm_widgets = ARRAY_SIZE(rt5639_dapm_widgets),
2383 .dapm_routes = rt5639_dapm_routes,
2384 .num_dapm_routes = ARRAY_SIZE(rt5639_dapm_routes),
2385};
2386
2387static const struct i2c_device_id rt5639_i2c_id[] = {
2388 { "rt5639", 0 },
2389 { }
2390};
2391MODULE_DEVICE_TABLE(i2c, rt5639_i2c_id);
2392
2393static int rt5639_i2c_probe(struct i2c_client *i2c,
2394 const struct i2c_device_id *id)
2395{
2396 struct rt5639_priv *rt5639;
2397 int ret;
2398
2399 rt5639 = kzalloc(sizeof(struct rt5639_priv), GFP_KERNEL);
2400 if (NULL == rt5639)
2401 return -ENOMEM;
2402
2403 i2c_set_clientdata(i2c, rt5639);
2404
2405 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5639,
2406 rt5639_dai, ARRAY_SIZE(rt5639_dai));
2407 if (ret < 0)
2408 kfree(rt5639);
2409
2410 return ret;
2411}
2412
2413static __devexit int rt5639_i2c_remove(struct i2c_client *i2c)
2414{
2415 snd_soc_unregister_codec(&i2c->dev);
2416 kfree(i2c_get_clientdata(i2c));
2417 return 0;
2418}
2419
2420struct i2c_driver rt5639_i2c_driver = {
2421 .driver = {
2422 .name = "rt5639",
2423 .owner = THIS_MODULE,
2424 },
2425 .probe = rt5639_i2c_probe,
2426 .remove = __devexit_p(rt5639_i2c_remove),
2427 .id_table = rt5639_i2c_id,
2428};
2429
2430static int __init rt5639_modinit(void)
2431{
2432 return i2c_add_driver(&rt5639_i2c_driver);
2433}
2434module_init(rt5639_modinit);
2435
2436static void __exit rt5639_modexit(void)
2437{
2438 i2c_del_driver(&rt5639_i2c_driver);
2439}
2440module_exit(rt5639_modexit);
2441
2442MODULE_DESCRIPTION("ASoC RT5639 driver");
2443MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
2444MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5639.h b/sound/soc/codecs/rt5639.h
new file mode 100644
index 00000000000..f75ddad1aa0
--- /dev/null
+++ b/sound/soc/codecs/rt5639.h
@@ -0,0 +1,2104 @@
1/*
2 * rt5639.h -- RT5639 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5639_H__
13#define __RT5639_H__
14
15/* Info */
16#define RT5639_RESET 0x00
17#define RT5639_VENDOR_ID 0xfd
18#define RT5639_VENDOR_ID1 0xfe
19#define RT5639_VENDOR_ID2 0xff
20/* I/O - Output */
21#define RT5639_SPK_VOL 0x01
22#define RT5639_HP_VOL 0x02
23#define RT5639_OUTPUT 0x03
24#define RT5639_MONO_OUT 0x04
25/* I/O - Input */
26#define RT5639_IN1_IN2 0x0d
27#define RT5639_IN3_IN4 0x0e
28#define RT5639_INL_INR_VOL 0x0f
29/* I/O - ADC/DAC/DMIC */
30#define RT5639_DAC1_DIG_VOL 0x19
31#define RT5639_DAC2_DIG_VOL 0x1a
32#define RT5639_DAC2_CTRL 0x1b
33#define RT5639_ADC_DIG_VOL 0x1c
34#define RT5639_ADC_DATA 0x1d
35#define RT5639_ADC_BST_VOL 0x1e
36/* Mixer - D-D */
37#define RT5639_STO_ADC_MIXER 0x27
38#define RT5639_MONO_ADC_MIXER 0x28
39#define RT5639_AD_DA_MIXER 0x29
40#define RT5639_STO_DAC_MIXER 0x2a
41#define RT5639_MONO_DAC_MIXER 0x2b
42#define RT5639_DIG_MIXER 0x2c
43#define RT5639_DSP_PATH1 0x2d
44#define RT5639_DSP_PATH2 0x2e
45#define RT5639_DIG_INF_DATA 0x2f
46/* Mixer - ADC */
47#define RT5639_REC_L1_MIXER 0x3b
48#define RT5639_REC_L2_MIXER 0x3c
49#define RT5639_REC_R1_MIXER 0x3d
50#define RT5639_REC_R2_MIXER 0x3e
51/* Mixer - DAC */
52#define RT5639_HPO_MIXER 0x45
53#define RT5639_SPK_L_MIXER 0x46
54#define RT5639_SPK_R_MIXER 0x47
55#define RT5639_SPO_L_MIXER 0x48
56#define RT5639_SPO_R_MIXER 0x49
57#define RT5639_SPO_CLSD_RATIO 0x4a
58#define RT5639_MONO_MIXER 0x4c
59#define RT5639_OUT_L1_MIXER 0x4d
60#define RT5639_OUT_L2_MIXER 0x4e
61#define RT5639_OUT_L3_MIXER 0x4f
62#define RT5639_OUT_R1_MIXER 0x50
63#define RT5639_OUT_R2_MIXER 0x51
64#define RT5639_OUT_R3_MIXER 0x52
65#define RT5639_LOUT_MIXER 0x53
66/* Power */
67#define RT5639_PWR_DIG1 0x61
68#define RT5639_PWR_DIG2 0x62
69#define RT5639_PWR_ANLG1 0x63
70#define RT5639_PWR_ANLG2 0x64
71#define RT5639_PWR_MIXER 0x65
72#define RT5639_PWR_VOL 0x66
73/* Private Register Control */
74#define RT5639_PRIV_INDEX 0x6a
75#define RT5639_PRIV_DATA 0x6c
76/* Format - ADC/DAC */
77#define RT5639_I2S1_SDP 0x70
78#define RT5639_I2S2_SDP 0x71
79#define RT5639_I2S3_SDP 0x72
80#define RT5639_ADDA_CLK1 0x73
81#define RT5639_ADDA_CLK2 0x74
82#define RT5639_DMIC 0x75
83/* Function - Analog */
84#define RT5639_GLB_CLK 0x80
85#define RT5639_PLL_CTRL1 0x81
86#define RT5639_PLL_CTRL2 0x82
87#define RT5639_ASRC_1 0x83
88#define RT5639_ASRC_2 0x84
89#define RT5639_ASRC_3 0x85
90#define RT5639_ASRC_4 0x89
91#define RT5639_ASRC_5 0x8a
92#define RT5639_HP_OVCD 0x8b
93#define RT5639_CLS_D_OVCD 0x8c
94#define RT5639_CLS_D_OUT 0x8d
95#define RT5639_DEPOP_M1 0x8e
96#define RT5639_DEPOP_M2 0x8f
97#define RT5639_DEPOP_M3 0x90
98#define RT5639_CHARGE_PUMP 0x91
99#define RT5639_PV_DET_SPK_G 0x92
100#define RT5639_MICBIAS 0x93
101/* Function - Digital */
102#define RT5639_EQ_CTRL1 0xb0
103#define RT5639_EQ_CTRL2 0xb1
104#define RT5639_WIND_FILTER 0xb2
105#define RT5639_DRC_AGC_1 0xb4
106#define RT5639_DRC_AGC_2 0xb5
107#define RT5639_DRC_AGC_3 0xb6
108#define RT5639_SVOL_ZC 0xb7
109#define RT5639_ANC_CTRL1 0xb8
110#define RT5639_ANC_CTRL2 0xb9
111#define RT5639_ANC_CTRL3 0xba
112#define RT5639_JD_CTRL 0xbb
113#define RT5639_ANC_JD 0xbc
114#define RT5639_IRQ_CTRL1 0xbd
115#define RT5639_IRQ_CTRL2 0xbe
116#define RT5639_INT_IRQ_ST 0xbf
117#define RT5639_GPIO_CTRL1 0xc0
118#define RT5639_GPIO_CTRL2 0xc1
119#define RT5639_GPIO_CTRL3 0xc2
120#define RT5639_DSP_CTRL1 0xc4
121#define RT5639_DSP_CTRL2 0xc5
122#define RT5639_DSP_CTRL3 0xc6
123#define RT5639_DSP_CTRL4 0xc7
124#define RT5639_PGM_REG_ARR1 0xc8
125#define RT5639_PGM_REG_ARR2 0xc9
126#define RT5639_PGM_REG_ARR3 0xca
127#define RT5639_PGM_REG_ARR4 0xcb
128#define RT5639_PGM_REG_ARR5 0xcc
129#define RT5639_SCB_FUNC 0xcd
130#define RT5639_SCB_CTRL 0xce
131#define RT5639_BASE_BACK 0xcf
132#define RT5639_MP3_PLUS1 0xd0
133#define RT5639_MP3_PLUS2 0xd1
134#define RT5639_3D_HP 0xd2
135#define RT5639_ADJ_HPF 0xd3
136#define RT5639_HP_CALIB_AMP_DET 0xd6
137#define RT5639_HP_CALIB2 0xd7
138#define RT5639_SV_ZCD1 0xd9
139#define RT5639_SV_ZCD2 0xda
140/* Dummy Register */
141#define RT5639_DUMMY1 0xfa
142#define RT5639_DUMMY2 0xfb
143#define RT5639_DUMMY3 0xfc
144
145
146/* Index of Codec Private Register definition */
147#define RT5639_3D_SPK 0x63
148#define RT5639_WND_1 0x6c
149#define RT5639_WND_2 0x6d
150#define RT5639_WND_3 0x6e
151#define RT5639_WND_4 0x6f
152#define RT5639_WND_5 0x70
153#define RT5639_WND_8 0x73
154#define RT5639_DIP_SPK_INF 0x75
155#define RT5639_EQ_BW_LOP 0xa0
156#define RT5639_EQ_GN_LOP 0xa1
157#define RT5639_EQ_FC_BP1 0xa2
158#define RT5639_EQ_BW_BP1 0xa3
159#define RT5639_EQ_GN_BP1 0xa4
160#define RT5639_EQ_FC_BP2 0xa5
161#define RT5639_EQ_BW_BP2 0xa6
162#define RT5639_EQ_GN_BP2 0xa7
163#define RT5639_EQ_FC_BP3 0xa8
164#define RT5639_EQ_BW_BP3 0xa9
165#define RT5639_EQ_GN_BP3 0xaa
166#define RT5639_EQ_FC_BP4 0xab
167#define RT5639_EQ_BW_BP4 0xac
168#define RT5639_EQ_GN_BP4 0xad
169#define RT5639_EQ_FC_HIP1 0xae
170#define RT5639_EQ_GN_HIP1 0xaf
171#define RT5639_EQ_FC_HIP2 0xb0
172#define RT5639_EQ_BW_HIP2 0xb1
173#define RT5639_EQ_GN_HIP2 0xb2
174#define RT5639_EQ_PRE_VOL 0xb3
175#define RT5639_EQ_PST_VOL 0xb4
176
177
178/* global definition */
179#define RT5639_L_MUTE (0x1 << 15)
180#define RT5639_L_MUTE_SFT 15
181#define RT5639_VOL_L_MUTE (0x1 << 14)
182#define RT5639_VOL_L_SFT 14
183#define RT5639_R_MUTE (0x1 << 7)
184#define RT5639_R_MUTE_SFT 7
185#define RT5639_VOL_R_MUTE (0x1 << 6)
186#define RT5639_VOL_R_SFT 6
187#define RT5639_L_VOL_MASK (0x3f << 8)
188#define RT5639_L_VOL_SFT 8
189#define RT5639_R_VOL_MASK (0x3f)
190#define RT5639_R_VOL_SFT 0
191
192/* IN1 and IN2 Control (0x0d) */
193/* IN3 and IN4 Control (0x0e) */
194#define RT5639_BST_SFT1 12
195#define RT5639_BST_SFT2 8
196#define RT5639_IN_DF1 (0x1 << 7)
197#define RT5639_IN_SFT1 7
198#define RT5639_IN_DF2 (0x1 << 6)
199#define RT5639_IN_SFT2 6
200
201/* INL and INR Volume Control (0x0f) */
202#define RT5639_INL_SEL_MASK (0x1 << 15)
203#define RT5639_INL_SEL_SFT 15
204#define RT5639_INL_SEL_IN4P (0x0 << 15)
205#define RT5639_INL_SEL_MONOP (0x1 << 15)
206#define RT5639_INL_VOL_MASK (0x1f << 8)
207#define RT5639_INL_VOL_SFT 8
208#define RT5639_INR_SEL_MASK (0x1 << 7)
209#define RT5639_INR_SEL_SFT 7
210#define RT5639_INR_SEL_IN4N (0x0 << 7)
211#define RT5639_INR_SEL_MONON (0x1 << 7)
212#define RT5639_INR_VOL_MASK (0x1f)
213#define RT5639_INR_VOL_SFT 0
214
215/* DAC1 Digital Volume (0x19) */
216#define RT5639_DAC_L1_VOL_MASK (0xff << 8)
217#define RT5639_DAC_L1_VOL_SFT 8
218#define RT5639_DAC_R1_VOL_MASK (0xff)
219#define RT5639_DAC_R1_VOL_SFT 0
220
221/* DAC2 Digital Volume (0x1a) */
222#define RT5639_DAC_L2_VOL_MASK (0xff << 8)
223#define RT5639_DAC_L2_VOL_SFT 8
224#define RT5639_DAC_R2_VOL_MASK (0xff)
225#define RT5639_DAC_R2_VOL_SFT 0
226
227/* DAC2 Control (0x1b) */
228#define RT5639_M_DAC_L2_VOL (0x1 << 13)
229#define RT5639_M_DAC_L2_VOL_SFT 13
230#define RT5639_M_DAC_R2_VOL (0x1 << 12)
231#define RT5639_M_DAC_R2_VOL_SFT 12
232
233/* ADC Digital Volume Control (0x1c) */
234#define RT5639_ADC_L_VOL_MASK (0x7f << 8)
235#define RT5639_ADC_L_VOL_SFT 8
236#define RT5639_ADC_R_VOL_MASK (0x7f)
237#define RT5639_ADC_R_VOL_SFT 0
238
239/* Mono ADC Digital Volume Control (0x1d) */
240#define RT5639_MONO_ADC_L_VOL_MASK (0x7f << 8)
241#define RT5639_MONO_ADC_L_VOL_SFT 8
242#define RT5639_MONO_ADC_R_VOL_MASK (0x7f)
243#define RT5639_MONO_ADC_R_VOL_SFT 0
244
245/* ADC Boost Volume Control (0x1e) */
246#define RT5639_ADC_L_BST_MASK (0x3 << 14)
247#define RT5639_ADC_L_BST_SFT 14
248#define RT5639_ADC_R_BST_MASK (0x3 << 12)
249#define RT5639_ADC_R_BST_SFT 12
250#define RT5639_ADC_COMP_MASK (0x3 << 10)
251#define RT5639_ADC_COMP_SFT 10
252
253/* Stereo ADC Mixer Control (0x27) */
254#define RT5639_M_ADC_L1 (0x1 << 14)
255#define RT5639_M_ADC_L1_SFT 14
256#define RT5639_M_ADC_L2 (0x1 << 13)
257#define RT5639_M_ADC_L2_SFT 13
258#define RT5639_ADC_1_SRC_MASK (0x1 << 12)
259#define RT5639_ADC_1_SRC_SFT 12
260#define RT5639_ADC_1_SRC_ADC (0x1 << 12)
261#define RT5639_ADC_1_SRC_DACMIX (0x0 << 12)
262#define RT5639_ADC_2_SRC_MASK (0x3 << 10)
263#define RT5639_ADC_2_SRC_SFT 10
264#define RT5639_ADC_2_SRC_DMIC1 (0x0 << 10)
265#define RT5639_ADC_2_SRC_DMIC2 (0x1 << 10)
266#define RT5639_ADC_2_SRC_DACMIX (0x2 << 10)
267#define RT5639_M_ADC_R1 (0x1 << 6)
268#define RT5639_M_ADC_R1_SFT 6
269#define RT5639_M_ADC_R2 (0x1 << 5)
270#define RT5639_M_ADC_R2_SFT 5
271
272/* Mono ADC Mixer Control (0x28) */
273#define RT5639_M_MONO_ADC_L1 (0x1 << 14)
274#define RT5639_M_MONO_ADC_L1_SFT 14
275#define RT5639_M_MONO_ADC_L2 (0x1 << 13)
276#define RT5639_M_MONO_ADC_L2_SFT 13
277#define RT5639_MONO_ADC_L1_SRC_MASK (0x1 << 12)
278#define RT5639_MONO_ADC_L1_SRC_SFT 12
279#define RT5639_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
280#define RT5639_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
281#define RT5639_MONO_ADC_L2_SRC_MASK (0x3 << 10)
282#define RT5639_MONO_ADC_L2_SRC_SFT 10
283#define RT5639_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
284#define RT5639_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
285#define RT5639_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
286#define RT5639_M_MONO_ADC_R1 (0x1 << 6)
287#define RT5639_M_MONO_ADC_R1_SFT 6
288#define RT5639_M_MONO_ADC_R2 (0x1 << 5)
289#define RT5639_M_MONO_ADC_R2_SFT 5
290#define RT5639_MONO_ADC_R1_SRC_MASK (0x1 << 4)
291#define RT5639_MONO_ADC_R1_SRC_SFT 4
292#define RT5639_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
293#define RT5639_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
294#define RT5639_MONO_ADC_R2_SRC_MASK (0x3 << 2)
295#define RT5639_MONO_ADC_R2_SRC_SFT 2
296#define RT5639_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
297#define RT5639_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
298#define RT5639_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
299
300/* ADC Mixer to DAC Mixer Control (0x29) */
301#define RT5639_M_ADCMIX_L (0x1 << 15)
302#define RT5639_M_ADCMIX_L_SFT 15
303#define RT5639_M_IF1_DAC_L (0x1 << 14)
304#define RT5639_M_IF1_DAC_L_SFT 14
305#define RT5639_M_ADCMIX_R (0x1 << 7)
306#define RT5639_M_ADCMIX_R_SFT 7
307#define RT5639_M_IF1_DAC_R (0x1 << 6)
308#define RT5639_M_IF1_DAC_R_SFT 6
309
310/* Stereo DAC Mixer Control (0x2a) */
311#define RT5639_M_DAC_L1 (0x1 << 14)
312#define RT5639_M_DAC_L1_SFT 14
313#define RT5639_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
314#define RT5639_DAC_L1_STO_L_VOL_SFT 13
315#define RT5639_M_DAC_L2 (0x1 << 12)
316#define RT5639_M_DAC_L2_SFT 12
317#define RT5639_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
318#define RT5639_DAC_L2_STO_L_VOL_SFT 11
319#define RT5639_M_ANC_DAC_L (0x1 << 10)
320#define RT5639_M_ANC_DAC_L_SFT 10
321#define RT5639_M_DAC_R1 (0x1 << 6)
322#define RT5639_M_DAC_R1_SFT 6
323#define RT5639_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
324#define RT5639_DAC_R1_STO_R_VOL_SFT 5
325#define RT5639_M_DAC_R2 (0x1 << 4)
326#define RT5639_M_DAC_R2_SFT 4
327#define RT5639_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
328#define RT5639_DAC_R2_STO_R_VOL_SFT 3
329#define RT5639_M_ANC_DAC_R (0x1 << 2)
330#define RT5639_M_ANC_DAC_R_SFT 2
331
332/* Mono DAC Mixer Control (0x2b) */
333#define RT5639_M_DAC_L1_MONO_L (0x1 << 14)
334#define RT5639_M_DAC_L1_MONO_L_SFT 14
335#define RT5639_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
336#define RT5639_DAC_L1_MONO_L_VOL_SFT 13
337#define RT5639_M_DAC_L2_MONO_L (0x1 << 12)
338#define RT5639_M_DAC_L2_MONO_L_SFT 12
339#define RT5639_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
340#define RT5639_DAC_L2_MONO_L_VOL_SFT 11
341#define RT5639_M_DAC_R2_MONO_L (0x1 << 10)
342#define RT5639_M_DAC_R2_MONO_L_SFT 10
343#define RT5639_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
344#define RT5639_DAC_R2_MONO_L_VOL_SFT 9
345#define RT5639_M_DAC_R1_MONO_R (0x1 << 6)
346#define RT5639_M_DAC_R1_MONO_R_SFT 6
347#define RT5639_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
348#define RT5639_DAC_R1_MONO_R_VOL_SFT 5
349#define RT5639_M_DAC_R2_MONO_R (0x1 << 4)
350#define RT5639_M_DAC_R2_MONO_R_SFT 4
351#define RT5639_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
352#define RT5639_DAC_R2_MONO_R_VOL_SFT 3
353#define RT5639_M_DAC_L2_MONO_R (0x1 << 2)
354#define RT5639_M_DAC_L2_MONO_R_SFT 2
355#define RT5639_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
356#define RT5639_DAC_L2_MONO_R_VOL_SFT 1
357
358/* Digital Mixer Control (0x2c) */
359#define RT5639_M_STO_L_DAC_L (0x1 << 15)
360#define RT5639_M_STO_L_DAC_L_SFT 15
361#define RT5639_STO_L_DAC_L_VOL_MASK (0x1 << 14)
362#define RT5639_STO_L_DAC_L_VOL_SFT 14
363#define RT5639_M_DAC_L2_DAC_L (0x1 << 13)
364#define RT5639_M_DAC_L2_DAC_L_SFT 13
365#define RT5639_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
366#define RT5639_DAC_L2_DAC_L_VOL_SFT 12
367#define RT5639_M_STO_R_DAC_R (0x1 << 11)
368#define RT5639_M_STO_R_DAC_R_SFT 11
369#define RT5639_STO_R_DAC_R_VOL_MASK (0x1 << 10)
370#define RT5639_STO_R_DAC_R_VOL_SFT 10
371#define RT5639_M_DAC_R2_DAC_R (0x1 << 9)
372#define RT5639_M_DAC_R2_DAC_R_SFT 9
373#define RT5639_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
374#define RT5639_DAC_R2_DAC_R_VOL_SFT 8
375
376/* DSP Path Control 1 (0x2d) */
377#define RT5639_RXDP_SRC_MASK (0x1 << 15)
378#define RT5639_RXDP_SRC_SFT 15
379#define RT5639_RXDP_SRC_NOR (0x0 << 15)
380#define RT5639_RXDP_SRC_DIV3 (0x1 << 15)
381#define RT5639_TXDP_SRC_MASK (0x1 << 14)
382#define RT5639_TXDP_SRC_SFT 14
383#define RT5639_TXDP_SRC_NOR (0x0 << 14)
384#define RT5639_TXDP_SRC_DIV3 (0x1 << 14)
385
386/* DSP Path Control 2 (0x2e) */
387#define RT5639_DAC_L2_SEL_MASK (0x3 << 14)
388#define RT5639_DAC_L2_SEL_SFT 14
389#define RT5639_DAC_L2_SEL_IF2 (0x0 << 14)
390#define RT5639_DAC_L2_SEL_IF3 (0x1 << 14)
391#define RT5639_DAC_L2_SEL_TXDC (0x2 << 14)
392#define RT5639_DAC_L2_SEL_BASS (0x3 << 14)
393#define RT5639_DAC_R2_SEL_MASK (0x3 << 12)
394#define RT5639_DAC_R2_SEL_SFT 12
395#define RT5639_DAC_R2_SEL_IF2 (0x0 << 12)
396#define RT5639_DAC_R2_SEL_IF3 (0x1 << 12)
397#define RT5639_DAC_R2_SEL_TXDC (0x2 << 12)
398#define RT5639_IF2_ADC_L_SEL_MASK (0x1 << 11)
399#define RT5639_IF2_ADC_L_SEL_SFT 11
400#define RT5639_IF2_ADC_L_SEL_TXDP (0x0 << 11)
401#define RT5639_IF2_ADC_L_SEL_PASS (0x1 << 11)
402#define RT5639_IF2_ADC_R_SEL_MASK (0x1 << 10)
403#define RT5639_IF2_ADC_R_SEL_SFT 10
404#define RT5639_IF2_ADC_R_SEL_TXDP (0x0 << 10)
405#define RT5639_IF2_ADC_R_SEL_PASS (0x1 << 10)
406#define RT5639_RXDC_SEL_MASK (0x3 << 8)
407#define RT5639_RXDC_SEL_SFT 8
408#define RT5639_RXDC_SEL_NOR (0x0 << 8)
409#define RT5639_RXDC_SEL_L2R (0x1 << 8)
410#define RT5639_RXDC_SEL_R2L (0x2 << 8)
411#define RT5639_RXDC_SEL_SWAP (0x3 << 8)
412#define RT5639_RXDP_SEL_MASK (0x3 << 6)
413#define RT5639_RXDP_SEL_SFT 6
414#define RT5639_RXDP_SEL_NOR (0x0 << 6)
415#define RT5639_RXDP_SEL_L2R (0x1 << 6)
416#define RT5639_RXDP_SEL_R2L (0x2 << 6)
417#define RT5639_RXDP_SEL_SWAP (0x3 << 6)
418#define RT5639_TXDC_SEL_MASK (0x3 << 4)
419#define RT5639_TXDC_SEL_SFT 4
420#define RT5639_TXDC_SEL_NOR (0x0 << 4)
421#define RT5639_TXDC_SEL_L2R (0x1 << 4)
422#define RT5639_TXDC_SEL_R2L (0x2 << 4)
423#define RT5639_TXDC_SEL_SWAP (0x3 << 4)
424#define RT5639_TXDP_SEL_MASK (0x3 << 2)
425#define RT5639_TXDP_SEL_SFT 2
426#define RT5639_TXDP_SEL_NOR (0x0 << 2)
427#define RT5639_TXDP_SEL_L2R (0x1 << 2)
428#define RT5639_TXDP_SEL_R2L (0x2 << 2)
429#define RT5639_TRXDP_SEL_SWAP (0x3 << 2)
430
431/* Digital Interface Data Control (0x2f) */
432#define RT5639_IF1_DAC_SEL_MASK (0x3 << 14)
433#define RT5639_IF1_DAC_SEL_SFT 14
434#define RT5639_IF1_DAC_SEL_NOR (0x0 << 14)
435#define RT5639_IF1_DAC_SEL_L2R (0x1 << 14)
436#define RT5639_IF1_DAC_SEL_R2L (0x2 << 14)
437#define RT5639_IF1_DAC_SEL_SWAP (0x3 << 14)
438#define RT5639_IF1_ADC_SEL_MASK (0x3 << 12)
439#define RT5639_IF1_ADC_SEL_SFT 12
440#define RT5639_IF1_ADC_SEL_NOR (0x0 << 12)
441#define RT5639_IF1_ADC_SEL_L2R (0x1 << 12)
442#define RT5639_IF1_ADC_SEL_R2L (0x2 << 12)
443#define RT5639_IF1_ADC_SEL_SWAP (0x3 << 12)
444#define RT5639_IF2_DAC_SEL_MASK (0x3 << 10)
445#define RT5639_IF2_DAC_SEL_SFT 10
446#define RT5639_IF2_DAC_SEL_NOR (0x0 << 10)
447#define RT5639_IF2_DAC_SEL_L2R (0x1 << 10)
448#define RT5639_IF2_DAC_SEL_R2L (0x2 << 10)
449#define RT5639_IF2_DAC_SEL_SWAP (0x3 << 10)
450#define RT5639_IF2_ADC_SEL_MASK (0x3 << 8)
451#define RT5639_IF2_ADC_SEL_SFT 8
452#define RT5639_IF2_ADC_SEL_NOR (0x0 << 8)
453#define RT5639_IF2_ADC_SEL_L2R (0x1 << 8)
454#define RT5639_IF2_ADC_SEL_R2L (0x2 << 8)
455#define RT5639_IF2_ADC_SEL_SWAP (0x3 << 8)
456#define RT5639_IF3_DAC_SEL_MASK (0x3 << 6)
457#define RT5639_IF3_DAC_SEL_SFT 6
458#define RT5639_IF3_DAC_SEL_NOR (0x0 << 6)
459#define RT5639_IF3_DAC_SEL_L2R (0x1 << 6)
460#define RT5639_IF3_DAC_SEL_R2L (0x2 << 6)
461#define RT5639_IF3_DAC_SEL_SWAP (0x3 << 6)
462#define RT5639_IF3_ADC_SEL_MASK (0x3 << 4)
463#define RT5639_IF3_ADC_SEL_SFT 4
464#define RT5639_IF3_ADC_SEL_NOR (0x0 << 4)
465#define RT5639_IF3_ADC_SEL_L2R (0x1 << 4)
466#define RT5639_IF3_ADC_SEL_R2L (0x2 << 4)
467#define RT5639_IF3_ADC_SEL_SWAP (0x3 << 4)
468
469/* REC Left Mixer Control 1 (0x3b) */
470#define RT5639_G_HP_L_RM_L_MASK (0x7 << 13)
471#define RT5639_G_HP_L_RM_L_SFT 13
472#define RT5639_G_IN_L_RM_L_MASK (0x7 << 10)
473#define RT5639_G_IN_L_RM_L_SFT 10
474#define RT5639_G_BST4_RM_L_MASK (0x7 << 7)
475#define RT5639_G_BST4_RM_L_SFT 7
476#define RT5639_G_BST3_RM_L_MASK (0x7 << 4)
477#define RT5639_G_BST3_RM_L_SFT 4
478#define RT5639_G_BST2_RM_L_MASK (0x7 << 1)
479#define RT5639_G_BST2_RM_L_SFT 1
480
481/* REC Left Mixer Control 2 (0x3c) */
482#define RT5639_G_BST1_RM_L_MASK (0x7 << 13)
483#define RT5639_G_BST1_RM_L_SFT 13
484#define RT5639_G_OM_L_RM_L_MASK (0x7 << 10)
485#define RT5639_G_OM_L_RM_L_SFT 10
486#define RT5639_M_HP_L_RM_L (0x1 << 6)
487#define RT5639_M_HP_L_RM_L_SFT 6
488#define RT5639_M_IN_L_RM_L (0x1 << 5)
489#define RT5639_M_IN_L_RM_L_SFT 5
490#define RT5639_M_BST4_RM_L (0x1 << 4)
491#define RT5639_M_BST4_RM_L_SFT 4
492#define RT5639_M_BST3_RM_L (0x1 << 3)
493#define RT5639_M_BST3_RM_L_SFT 3
494#define RT5639_M_BST2_RM_L (0x1 << 2)
495#define RT5639_M_BST2_RM_L_SFT 2
496#define RT5639_M_BST1_RM_L (0x1 << 1)
497#define RT5639_M_BST1_RM_L_SFT 1
498#define RT5639_M_OM_L_RM_L (0x1)
499#define RT5639_M_OM_L_RM_L_SFT 0
500
501/* REC Right Mixer Control 1 (0x3d) */
502#define RT5639_G_HP_R_RM_R_MASK (0x7 << 13)
503#define RT5639_G_HP_R_RM_R_SFT 13
504#define RT5639_G_IN_R_RM_R_MASK (0x7 << 10)
505#define RT5639_G_IN_R_RM_R_SFT 10
506#define RT5639_G_BST4_RM_R_MASK (0x7 << 7)
507#define RT5639_G_BST4_RM_R_SFT 7
508#define RT5639_G_BST3_RM_R_MASK (0x7 << 4)
509#define RT5639_G_BST3_RM_R_SFT 4
510#define RT5639_G_BST2_RM_R_MASK (0x7 << 1)
511#define RT5639_G_BST2_RM_R_SFT 1
512
513/* REC Right Mixer Control 2 (0x3e) */
514#define RT5639_G_BST1_RM_R_MASK (0x7 << 13)
515#define RT5639_G_BST1_RM_R_SFT 13
516#define RT5639_G_OM_R_RM_R_MASK (0x7 << 10)
517#define RT5639_G_OM_R_RM_R_SFT 10
518#define RT5639_M_HP_R_RM_R (0x1 << 6)
519#define RT5639_M_HP_R_RM_R_SFT 6
520#define RT5639_M_IN_R_RM_R (0x1 << 5)
521#define RT5639_M_IN_R_RM_R_SFT 5
522#define RT5639_M_BST4_RM_R (0x1 << 4)
523#define RT5639_M_BST4_RM_R_SFT 4
524#define RT5639_M_BST3_RM_R (0x1 << 3)
525#define RT5639_M_BST3_RM_R_SFT 3
526#define RT5639_M_BST2_RM_R (0x1 << 2)
527#define RT5639_M_BST2_RM_R_SFT 2
528#define RT5639_M_BST1_RM_R (0x1 << 1)
529#define RT5639_M_BST1_RM_R_SFT 1
530#define RT5639_M_OM_R_RM_R (0x1)
531#define RT5639_M_OM_R_RM_R_SFT 0
532
533/* HPMIX Control (0x45) */
534#define RT5639_M_DAC2_HM (0x1 << 15)
535#define RT5639_M_DAC2_HM_SFT 15
536#define RT5639_M_DAC1_HM (0x1 << 14)
537#define RT5639_M_DAC1_HM_SFT 14
538#define RT5639_M_HPVOL_HM (0x1 << 13)
539#define RT5639_M_HPVOL_HM_SFT 13
540#define RT5639_G_HPOMIX_MASK (0x1 << 12)
541#define RT5639_G_HPOMIX_SFT 12
542
543/* SPK Left Mixer Control (0x46) */
544#define RT5639_G_RM_L_SM_L_MASK (0x3 << 14)
545#define RT5639_G_RM_L_SM_L_SFT 14
546#define RT5639_G_IN_L_SM_L_MASK (0x3 << 12)
547#define RT5639_G_IN_L_SM_L_SFT 12
548#define RT5639_G_DAC_L1_SM_L_MASK (0x3 << 10)
549#define RT5639_G_DAC_L1_SM_L_SFT 10
550#define RT5639_G_DAC_L2_SM_L_MASK (0x3 << 8)
551#define RT5639_G_DAC_L2_SM_L_SFT 8
552#define RT5639_G_OM_L_SM_L_MASK (0x3 << 6)
553#define RT5639_G_OM_L_SM_L_SFT 6
554#define RT5639_M_RM_L_SM_L (0x1 << 5)
555#define RT5639_M_RM_L_SM_L_SFT 5
556#define RT5639_M_IN_L_SM_L (0x1 << 4)
557#define RT5639_M_IN_L_SM_L_SFT 4
558#define RT5639_M_DAC_L1_SM_L (0x1 << 3)
559#define RT5639_M_DAC_L1_SM_L_SFT 3
560#define RT5639_M_DAC_L2_SM_L (0x1 << 2)
561#define RT5639_M_DAC_L2_SM_L_SFT 2
562#define RT5639_M_OM_L_SM_L (0x1 << 1)
563#define RT5639_M_OM_L_SM_L_SFT 1
564
565/* SPK Right Mixer Control (0x47) */
566#define RT5639_G_RM_R_SM_R_MASK (0x3 << 14)
567#define RT5639_G_RM_R_SM_R_SFT 14
568#define RT5639_G_IN_R_SM_R_MASK (0x3 << 12)
569#define RT5639_G_IN_R_SM_R_SFT 12
570#define RT5639_G_DAC_R1_SM_R_MASK (0x3 << 10)
571#define RT5639_G_DAC_R1_SM_R_SFT 10
572#define RT5639_G_DAC_R2_SM_R_MASK (0x3 << 8)
573#define RT5639_G_DAC_R2_SM_R_SFT 8
574#define RT5639_G_OM_R_SM_R_MASK (0x3 << 6)
575#define RT5639_G_OM_R_SM_R_SFT 6
576#define RT5639_M_RM_R_SM_R (0x1 << 5)
577#define RT5639_M_RM_R_SM_R_SFT 5
578#define RT5639_M_IN_R_SM_R (0x1 << 4)
579#define RT5639_M_IN_R_SM_R_SFT 4
580#define RT5639_M_DAC_R1_SM_R (0x1 << 3)
581#define RT5639_M_DAC_R1_SM_R_SFT 3
582#define RT5639_M_DAC_R2_SM_R (0x1 << 2)
583#define RT5639_M_DAC_R2_SM_R_SFT 2
584#define RT5639_M_OM_R_SM_R (0x1 << 1)
585#define RT5639_M_OM_R_SM_R_SFT 1
586
587/* SPOLMIX Control (0x48) */
588#define RT5639_M_DAC_R1_SPM_L (0x1 << 15)
589#define RT5639_M_DAC_R1_SPM_L_SFT 15
590#define RT5639_M_DAC_L1_SPM_L (0x1 << 14)
591#define RT5639_M_DAC_L1_SPM_L_SFT 14
592#define RT5639_M_SV_R_SPM_L (0x1 << 13)
593#define RT5639_M_SV_R_SPM_L_SFT 13
594#define RT5639_M_SV_L_SPM_L (0x1 << 12)
595#define RT5639_M_SV_L_SPM_L_SFT 12
596#define RT5639_M_BST1_SPM_L (0x1 << 11)
597#define RT5639_M_BST1_SPM_L_SFT 11
598
599/* SPORMIX Control (0x49) */
600#define RT5639_M_DAC_R1_SPM_R (0x1 << 13)
601#define RT5639_M_DAC_R1_SPM_R_SFT 13
602#define RT5639_M_SV_R_SPM_R (0x1 << 12)
603#define RT5639_M_SV_R_SPM_R_SFT 12
604#define RT5639_M_BST1_SPM_R (0x1 << 11)
605#define RT5639_M_BST1_SPM_R_SFT 11
606
607/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
608#define RT5639_SPO_CLSD_RATIO_MASK (0x7)
609#define RT5639_SPO_CLSD_RATIO_SFT 0
610
611/* Mono Output Mixer Control (0x4c) */
612#define RT5639_M_DAC_R2_MM (0x1 << 15)
613#define RT5639_M_DAC_R2_MM_SFT 15
614#define RT5639_M_DAC_L2_MM (0x1 << 14)
615#define RT5639_M_DAC_L2_MM_SFT 14
616#define RT5639_M_OV_R_MM (0x1 << 13)
617#define RT5639_M_OV_R_MM_SFT 13
618#define RT5639_M_OV_L_MM (0x1 << 12)
619#define RT5639_M_OV_L_MM_SFT 12
620#define RT5639_M_BST1_MM (0x1 << 11)
621#define RT5639_M_BST1_MM_SFT 11
622#define RT5639_G_MONOMIX_MASK (0x1 << 10)
623#define RT5639_G_MONOMIX_SFT 10
624
625/* Output Left Mixer Control 1 (0x4d) */
626#define RT5639_G_BST3_OM_L_MASK (0x7 << 13)
627#define RT5639_G_BST3_OM_L_SFT 13
628#define RT5639_G_BST2_OM_L_MASK (0x7 << 10)
629#define RT5639_G_BST2_OM_L_SFT 10
630#define RT5639_G_BST1_OM_L_MASK (0x7 << 7)
631#define RT5639_G_BST1_OM_L_SFT 7
632#define RT5639_G_IN_L_OM_L_MASK (0x7 << 4)
633#define RT5639_G_IN_L_OM_L_SFT 4
634#define RT5639_G_RM_L_OM_L_MASK (0x7 << 1)
635#define RT5639_G_RM_L_OM_L_SFT 1
636
637/* Output Left Mixer Control 2 (0x4e) */
638#define RT5639_G_DAC_R2_OM_L_MASK (0x7 << 13)
639#define RT5639_G_DAC_R2_OM_L_SFT 13
640#define RT5639_G_DAC_L2_OM_L_MASK (0x7 << 10)
641#define RT5639_G_DAC_L2_OM_L_SFT 10
642#define RT5639_G_DAC_L1_OM_L_MASK (0x7 << 7)
643#define RT5639_G_DAC_L1_OM_L_SFT 7
644
645/* Output Left Mixer Control 3 (0x4f) */
646#define RT5639_M_SM_L_OM_L (0x1 << 8)
647#define RT5639_M_SM_L_OM_L_SFT 8
648#define RT5639_M_BST3_OM_L (0x1 << 7)
649#define RT5639_M_BST3_OM_L_SFT 7
650#define RT5639_M_BST2_OM_L (0x1 << 6)
651#define RT5639_M_BST2_OM_L_SFT 6
652#define RT5639_M_BST1_OM_L (0x1 << 5)
653#define RT5639_M_BST1_OM_L_SFT 5
654#define RT5639_M_IN_L_OM_L (0x1 << 4)
655#define RT5639_M_IN_L_OM_L_SFT 4
656#define RT5639_M_RM_L_OM_L (0x1 << 3)
657#define RT5639_M_RM_L_OM_L_SFT 3
658#define RT5639_M_DAC_R2_OM_L (0x1 << 2)
659#define RT5639_M_DAC_R2_OM_L_SFT 2
660#define RT5639_M_DAC_L2_OM_L (0x1 << 1)
661#define RT5639_M_DAC_L2_OM_L_SFT 1
662#define RT5639_M_DAC_L1_OM_L (0x1)
663#define RT5639_M_DAC_L1_OM_L_SFT 0
664
665/* Output Right Mixer Control 1 (0x50) */
666#define RT5639_G_BST4_OM_R_MASK (0x7 << 13)
667#define RT5639_G_BST4_OM_R_SFT 13
668#define RT5639_G_BST2_OM_R_MASK (0x7 << 10)
669#define RT5639_G_BST2_OM_R_SFT 10
670#define RT5639_G_BST1_OM_R_MASK (0x7 << 7)
671#define RT5639_G_BST1_OM_R_SFT 7
672#define RT5639_G_IN_R_OM_R_MASK (0x7 << 4)
673#define RT5639_G_IN_R_OM_R_SFT 4
674#define RT5639_G_RM_R_OM_R_MASK (0x7 << 1)
675#define RT5639_G_RM_R_OM_R_SFT 1
676
677/* Output Right Mixer Control 2 (0x51) */
678#define RT5639_G_DAC_L2_OM_R_MASK (0x7 << 13)
679#define RT5639_G_DAC_L2_OM_R_SFT 13
680#define RT5639_G_DAC_R2_OM_R_MASK (0x7 << 10)
681#define RT5639_G_DAC_R2_OM_R_SFT 10
682#define RT5639_G_DAC_R1_OM_R_MASK (0x7 << 7)
683#define RT5639_G_DAC_R1_OM_R_SFT 7
684
685/* Output Right Mixer Control 3 (0x52) */
686#define RT5639_M_SM_L_OM_R (0x1 << 8)
687#define RT5639_M_SM_L_OM_R_SFT 8
688#define RT5639_M_BST4_OM_R (0x1 << 7)
689#define RT5639_M_BST4_OM_R_SFT 7
690#define RT5639_M_BST2_OM_R (0x1 << 6)
691#define RT5639_M_BST2_OM_R_SFT 6
692#define RT5639_M_BST1_OM_R (0x1 << 5)
693#define RT5639_M_BST1_OM_R_SFT 5
694#define RT5639_M_IN_R_OM_R (0x1 << 4)
695#define RT5639_M_IN_R_OM_R_SFT 4
696#define RT5639_M_RM_R_OM_R (0x1 << 3)
697#define RT5639_M_RM_R_OM_R_SFT 3
698#define RT5639_M_DAC_L2_OM_R (0x1 << 2)
699#define RT5639_M_DAC_L2_OM_R_SFT 2
700#define RT5639_M_DAC_R2_OM_R (0x1 << 1)
701#define RT5639_M_DAC_R2_OM_R_SFT 1
702#define RT5639_M_DAC_R1_OM_R (0x1)
703#define RT5639_M_DAC_R1_OM_R_SFT 0
704
705/* LOUT Mixer Control (0x53) */
706#define RT5639_M_DAC_L1_LM (0x1 << 15)
707#define RT5639_M_DAC_L1_LM_SFT 15
708#define RT5639_M_DAC_R1_LM (0x1 << 14)
709#define RT5639_M_DAC_R1_LM_SFT 14
710#define RT5639_M_OV_L_LM (0x1 << 13)
711#define RT5639_M_OV_L_LM_SFT 13
712#define RT5639_M_OV_R_LM (0x1 << 12)
713#define RT5639_M_OV_R_LM_SFT 12
714#define RT5639_G_LOUTMIX_MASK (0x1 << 11)
715#define RT5639_G_LOUTMIX_SFT 11
716
717/* Power Management for Digital 1 (0x61) */
718#define RT5639_PWR_I2S1 (0x1 << 15)
719#define RT5639_PWR_I2S1_BIT 15
720#define RT5639_PWR_I2S2 (0x1 << 14)
721#define RT5639_PWR_I2S2_BIT 14
722#define RT5639_PWR_I2S3 (0x1 << 13)
723#define RT5639_PWR_I2S3_BIT 13
724#define RT5639_PWR_DAC_L1 (0x1 << 12)
725#define RT5639_PWR_DAC_L1_BIT 12
726#define RT5639_PWR_DAC_R1 (0x1 << 11)
727#define RT5639_PWR_DAC_R1_BIT 11
728#define RT5639_PWR_DAC_L2 (0x1 << 7)
729#define RT5639_PWR_DAC_L2_BIT 7
730#define RT5639_PWR_DAC_R2 (0x1 << 6)
731#define RT5639_PWR_DAC_R2_BIT 6
732#define RT5639_PWR_ADC_L (0x1 << 2)
733#define RT5639_PWR_ADC_L_BIT 2
734#define RT5639_PWR_ADC_R (0x1 << 1)
735#define RT5639_PWR_ADC_R_BIT 1
736#define RT5639_PWR_CLS_D (0x1)
737#define RT5639_PWR_CLS_D_BIT 0
738
739/* Power Management for Digital 2 (0x62) */
740#define RT5639_PWR_ADC_SF (0x1 << 15)
741#define RT5639_PWR_ADC_SF_BIT 15
742#define RT5639_PWR_ADC_MF_L (0x1 << 14)
743#define RT5639_PWR_ADC_MF_L_BIT 14
744#define RT5639_PWR_ADC_MF_R (0x1 << 13)
745#define RT5639_PWR_ADC_MF_R_BIT 13
746#define RT5639_PWR_I2S_DSP (0x1 << 12)
747#define RT5639_PWR_I2S_DSP_BIT 12
748
749/* Power Management for Analog 1 (0x63) */
750#define RT5639_PWR_VREF1 (0x1 << 15)
751#define RT5639_PWR_VREF1_BIT 15
752#define RT5639_PWR_FV1 (0x1 << 14)
753#define RT5639_PWR_FV1_BIT 14
754#define RT5639_PWR_MB (0x1 << 13)
755#define RT5639_PWR_MB_BIT 13
756#define RT5639_PWR_LM (0x1 << 12)
757#define RT5639_PWR_LM_BIT 12
758#define RT5639_PWR_BG (0x1 << 11)
759#define RT5639_PWR_BG_BIT 11
760#define RT5639_PWR_MM (0x1 << 10)
761#define RT5639_PWR_MM_BIT 10
762#define RT5639_PWR_MA (0x1 << 8)
763#define RT5639_PWR_MA_BIT 8
764#define RT5639_PWR_HP_L (0x1 << 7)
765#define RT5639_PWR_HP_L_BIT 7
766#define RT5639_PWR_HP_R (0x1 << 6)
767#define RT5639_PWR_HP_R_BIT 6
768#define RT5639_PWR_HA (0x1 << 5)
769#define RT5639_PWR_HA_BIT 5
770#define RT5639_PWR_VREF2 (0x1 << 4)
771#define RT5639_PWR_VREF2_BIT 4
772#define RT5639_PWR_FV2 (0x1 << 3)
773#define RT5639_PWR_FV2_BIT 3
774#define RT5639_PWR_LDO2 (0x1 << 2)
775#define RT5639_PWR_LDO2_BIT 2
776
777/* Power Management for Analog 2 (0x64) */
778#define RT5639_PWR_BST1 (0x1 << 15)
779#define RT5639_PWR_BST1_BIT 15
780#define RT5639_PWR_BST2 (0x1 << 14)
781#define RT5639_PWR_BST2_BIT 14
782#define RT5639_PWR_BST3 (0x1 << 13)
783#define RT5639_PWR_BST3_BIT 13
784#define RT5639_PWR_BST4 (0x1 << 12)
785#define RT5639_PWR_BST4_BIT 12
786#define RT5639_PWR_MB1 (0x1 << 11)
787#define RT5639_PWR_MB1_BIT 11
788#define RT5639_PWR_MB2 (0x1 << 10)
789#define RT5639_PWR_MB2_BIT 10
790#define RT5639_PWR_PLL (0x1 << 9)
791#define RT5639_PWR_PLL_BIT 9
792
793/* Power Management for Mixer (0x65) */
794#define RT5639_PWR_OM_L (0x1 << 15)
795#define RT5639_PWR_OM_L_BIT 15
796#define RT5639_PWR_OM_R (0x1 << 14)
797#define RT5639_PWR_OM_R_BIT 14
798#define RT5639_PWR_SM_L (0x1 << 13)
799#define RT5639_PWR_SM_L_BIT 13
800#define RT5639_PWR_SM_R (0x1 << 12)
801#define RT5639_PWR_SM_R_BIT 12
802#define RT5639_PWR_RM_L (0x1 << 11)
803#define RT5639_PWR_RM_L_BIT 11
804#define RT5639_PWR_RM_R (0x1 << 10)
805#define RT5639_PWR_RM_R_BIT 10
806
807/* Power Management for Volume (0x66) */
808#define RT5639_PWR_SV_L (0x1 << 15)
809#define RT5639_PWR_SV_L_BIT 15
810#define RT5639_PWR_SV_R (0x1 << 14)
811#define RT5639_PWR_SV_R_BIT 14
812#define RT5639_PWR_OV_L (0x1 << 13)
813#define RT5639_PWR_OV_L_BIT 13
814#define RT5639_PWR_OV_R (0x1 << 12)
815#define RT5639_PWR_OV_R_BIT 12
816#define RT5639_PWR_HV_L (0x1 << 11)
817#define RT5639_PWR_HV_L_BIT 11
818#define RT5639_PWR_HV_R (0x1 << 10)
819#define RT5639_PWR_HV_R_BIT 10
820#define RT5639_PWR_IN_L (0x1 << 9)
821#define RT5639_PWR_IN_L_BIT 9
822#define RT5639_PWR_IN_R (0x1 << 8)
823#define RT5639_PWR_IN_R_BIT 8
824
825/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
826#define RT5639_I2S_MS_MASK (0x1 << 15)
827#define RT5639_I2S_MS_SFT 15
828#define RT5639_I2S_MS_M (0x0 << 15)
829#define RT5639_I2S_MS_S (0x1 << 15)
830#define RT5639_I2S_IF_MASK (0x7 << 12)
831#define RT5639_I2S_IF_SFT 12
832#define RT5639_I2S_O_CP_MASK (0x3 << 10)
833#define RT5639_I2S_O_CP_SFT 10
834#define RT5639_I2S_O_CP_OFF (0x0 << 10)
835#define RT5639_I2S_O_CP_U_LAW (0x1 << 10)
836#define RT5639_I2S_O_CP_A_LAW (0x2 << 10)
837#define RT5639_I2S_I_CP_MASK (0x3 << 8)
838#define RT5639_I2S_I_CP_SFT 8
839#define RT5639_I2S_I_CP_OFF (0x0 << 8)
840#define RT5639_I2S_I_CP_U_LAW (0x1 << 8)
841#define RT5639_I2S_I_CP_A_LAW (0x2 << 8)
842#define RT5639_I2S_BP_MASK (0x1 << 7)
843#define RT5639_I2S_BP_SFT 7
844#define RT5639_I2S_BP_NOR (0x0 << 7)
845#define RT5639_I2S_BP_INV (0x1 << 7)
846#define RT5639_I2S_DL_MASK (0x3 << 2)
847#define RT5639_I2S_DL_SFT 2
848#define RT5639_I2S_DL_16 (0x0 << 2)
849#define RT5639_I2S_DL_20 (0x1 << 2)
850#define RT5639_I2S_DL_24 (0x2 << 2)
851#define RT5639_I2S_DL_8 (0x3 << 2)
852#define RT5639_I2S_DF_MASK (0x3)
853#define RT5639_I2S_DF_SFT 0
854#define RT5639_I2S_DF_I2S (0x0)
855#define RT5639_I2S_DF_LEFT (0x1)
856#define RT5639_I2S_DF_PCM_A (0x2)
857#define RT5639_I2S_DF_PCM_B (0x3)
858
859/* I2S2 Audio Serial Data Port Control (0x71) */
860#define RT5639_I2S2_SDI_MASK (0x1 << 6)
861#define RT5639_I2S2_SDI_SFT 6
862#define RT5639_I2S2_SDI_I2S1 (0x0 << 6)
863#define RT5639_I2S2_SDI_I2S2 (0x1 << 6)
864
865/* ADC/DAC Clock Control 1 (0x73) */
866#define RT5639_I2S_BCLK_MS1_MASK (0x1 << 15)
867#define RT5639_I2S_BCLK_MS1_SFT 15
868#define RT5639_I2S_BCLK_MS1_32 (0x0 << 15)
869#define RT5639_I2S_BCLK_MS1_64 (0x1 << 15)
870#define RT5639_I2S_PD1_MASK (0x7 << 12)
871#define RT5639_I2S_PD1_SFT 12
872#define RT5639_I2S_PD1_1 (0x0 << 12)
873#define RT5639_I2S_PD1_2 (0x1 << 12)
874#define RT5639_I2S_PD1_3 (0x2 << 12)
875#define RT5639_I2S_PD1_4 (0x3 << 12)
876#define RT5639_I2S_PD1_6 (0x4 << 12)
877#define RT5639_I2S_PD1_8 (0x5 << 12)
878#define RT5639_I2S_PD1_12 (0x6 << 12)
879#define RT5639_I2S_PD1_16 (0x7 << 12)
880#define RT5639_I2S_BCLK_MS2_MASK (0x1 << 11)
881#define RT5639_I2S_BCLK_MS2_SFT 11
882#define RT5639_I2S_BCLK_MS2_32 (0x0 << 11)
883#define RT5639_I2S_BCLK_MS2_64 (0x1 << 11)
884#define RT5639_I2S_PD2_MASK (0x7 << 8)
885#define RT5639_I2S_PD2_SFT 8
886#define RT5639_I2S_PD2_1 (0x0 << 8)
887#define RT5639_I2S_PD2_2 (0x1 << 8)
888#define RT5639_I2S_PD2_3 (0x2 << 8)
889#define RT5639_I2S_PD2_4 (0x3 << 8)
890#define RT5639_I2S_PD2_6 (0x4 << 8)
891#define RT5639_I2S_PD2_8 (0x5 << 8)
892#define RT5639_I2S_PD2_12 (0x6 << 8)
893#define RT5639_I2S_PD2_16 (0x7 << 8)
894#define RT5639_I2S_BCLK_MS3_MASK (0x1 << 7)
895#define RT5639_I2S_BCLK_MS3_SFT 7
896#define RT5639_I2S_BCLK_MS3_32 (0x0 << 7)
897#define RT5639_I2S_BCLK_MS3_64 (0x1 << 7)
898#define RT5639_I2S_PD3_MASK (0x7 << 4)
899#define RT5639_I2S_PD3_SFT 4
900#define RT5639_I2S_PD3_1 (0x0 << 4)
901#define RT5639_I2S_PD3_2 (0x1 << 4)
902#define RT5639_I2S_PD3_3 (0x2 << 4)
903#define RT5639_I2S_PD3_4 (0x3 << 4)
904#define RT5639_I2S_PD3_6 (0x4 << 4)
905#define RT5639_I2S_PD3_8 (0x5 << 4)
906#define RT5639_I2S_PD3_12 (0x6 << 4)
907#define RT5639_I2S_PD3_16 (0x7 << 4)
908#define RT5639_DAC_OSR_MASK (0x3 << 2)
909#define RT5639_DAC_OSR_SFT 2
910#define RT5639_DAC_OSR_128 (0x0 << 2)
911#define RT5639_DAC_OSR_64 (0x1 << 2)
912#define RT5639_DAC_OSR_32 (0x2 << 2)
913#define RT5639_DAC_OSR_16 (0x3 << 2)
914#define RT5639_ADC_OSR_MASK (0x3)
915#define RT5639_ADC_OSR_SFT 0
916#define RT5639_ADC_OSR_128 (0x0)
917#define RT5639_ADC_OSR_64 (0x1)
918#define RT5639_ADC_OSR_32 (0x2)
919#define RT5639_ADC_OSR_16 (0x3)
920
921/* ADC/DAC Clock Control 2 (0x74) */
922#define RT5639_DAC_L_OSR_MASK (0x3 << 14)
923#define RT5639_DAC_L_OSR_SFT 14
924#define RT5639_DAC_L_OSR_128 (0x0 << 14)
925#define RT5639_DAC_L_OSR_64 (0x1 << 14)
926#define RT5639_DAC_L_OSR_32 (0x2 << 14)
927#define RT5639_DAC_L_OSR_16 (0x3 << 14)
928#define RT5639_ADC_R_OSR_MASK (0x3 << 12)
929#define RT5639_ADC_R_OSR_SFT 12
930#define RT5639_ADC_R_OSR_128 (0x0 << 12)
931#define RT5639_ADC_R_OSR_64 (0x1 << 12)
932#define RT5639_ADC_R_OSR_32 (0x2 << 12)
933#define RT5639_ADC_R_OSR_16 (0x3 << 12)
934#define RT5639_DAHPF_EN (0x1 << 11)
935#define RT5639_DAHPF_EN_SFT 11
936#define RT5639_ADHPF_EN (0x1 << 10)
937#define RT5639_ADHPF_EN_SFT 10
938
939/* Digital Microphone Control (0x75) */
940#define RT5639_DMIC_1_EN_MASK (0x1 << 15)
941#define RT5639_DMIC_1_EN_SFT 15
942#define RT5639_DMIC_1_DIS (0x0 << 15)
943#define RT5639_DMIC_1_EN (0x1 << 15)
944#define RT5639_DMIC_2_EN_MASK (0x1 << 14)
945#define RT5639_DMIC_2_EN_SFT 14
946#define RT5639_DMIC_2_DIS (0x0 << 14)
947#define RT5639_DMIC_2_EN (0x1 << 14)
948#define RT5639_DMIC_1L_LH_MASK (0x1 << 13)
949#define RT5639_DMIC_1L_LH_SFT 13
950#define RT5639_DMIC_1L_LH_FALLING (0x0 << 13)
951#define RT5639_DMIC_1L_LH_RISING (0x1 << 13)
952#define RT5639_DMIC_1R_LH_MASK (0x1 << 12)
953#define RT5639_DMIC_1R_LH_SFT 12
954#define RT5639_DMIC_1R_LH_FALLING (0x0 << 12)
955#define RT5639_DMIC_1R_LH_RISING (0x1 << 12)
956#define RT5639_DMIC_1_DP_MASK (0x1 << 11)
957#define RT5639_DMIC_1_DP_SFT 11
958#define RT5639_DMIC_1_DP_GPIO3 (0x0 << 11)
959#define RT5639_DMIC_1_DP_IN1P (0x1 << 11)
960#define RT5639_DMIC_2_DP_MASK (0x1 << 10)
961#define RT5639_DMIC_2_DP_SFT 10
962#define RT5639_DMIC_2_DP_GPIO4 (0x0 << 10)
963#define RT5639_DMIC_2_DP_IN1N (0x1 << 10)
964#define RT5639_DMIC_2L_LH_MASK (0x1 << 9)
965#define RT5639_DMIC_2L_LH_SFT 9
966#define RT5639_DMIC_2L_LH_FALLING (0x0 << 9)
967#define RT5639_DMIC_2L_LH_RISING (0x1 << 9)
968#define RT5639_DMIC_2R_LH_MASK (0x1 << 8)
969#define RT5639_DMIC_2R_LH_SFT 8
970#define RT5639_DMIC_2R_LH_FALLING (0x0 << 8)
971#define RT5639_DMIC_2R_LH_RISING (0x1 << 8)
972#define RT5639_DMIC_CLK_MASK (0x7 << 5)
973#define RT5639_DMIC_CLK_SFT 5
974
975/* Global Clock Control (0x80) */
976#define RT5639_SCLK_SRC_MASK (0x3 << 14)
977#define RT5639_SCLK_SRC_SFT 14
978#define RT5639_SCLK_SRC_MCLK (0x0 << 14)
979#define RT5639_SCLK_SRC_PLL1 (0x1 << 14)
980#define RT5639_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
981#define RT5639_PLL1_SRC_MASK (0x3 << 12)
982#define RT5639_PLL1_SRC_SFT 12
983#define RT5639_PLL1_SRC_MCLK (0x0 << 12)
984#define RT5639_PLL1_SRC_BCLK1 (0x1 << 12)
985#define RT5639_PLL1_SRC_BCLK2 (0x2 << 12)
986#define RT5639_PLL1_SRC_BCLK3 (0x3 << 12)
987#define RT5639_PLL1_PD_MASK (0x1 << 3)
988#define RT5639_PLL1_PD_SFT 3
989#define RT5639_PLL1_PD_1 (0x0 << 3)
990#define RT5639_PLL1_PD_2 (0x1 << 3)
991
992#define RT5639_PLL_INP_MAX 40000000
993#define RT5639_PLL_INP_MIN 256000
994/* PLL M/N/K Code Control 1 (0x81) */
995#define RT5639_PLL_N_MAX 0x1ff
996#define RT5639_PLL_N_MASK (RT5639_PLL_N_MAX << 7)
997#define RT5639_PLL_N_SFT 7
998#define RT5639_PLL_K_MAX 0x1f
999#define RT5639_PLL_K_MASK (RT5639_PLL_K_MAX)
1000#define RT5639_PLL_K_SFT 0
1001
1002/* PLL M/N/K Code Control 2 (0x82) */
1003#define RT5639_PLL_M_MAX 0xf
1004#define RT5639_PLL_M_MASK (RT5639_PLL_M_MAX << 12)
1005#define RT5639_PLL_M_SFT 12
1006#define RT5639_PLL_M_BP (0x1 << 11)
1007#define RT5639_PLL_M_BP_SFT 11
1008
1009/* ASRC Control 1 (0x83) */
1010#define RT5639_STO_T_MASK (0x1 << 15)
1011#define RT5639_STO_T_SFT 15
1012#define RT5639_STO_T_SCLK (0x0 << 15)
1013#define RT5639_STO_T_LRCK1 (0x1 << 15)
1014#define RT5639_M1_T_MASK (0x1 << 14)
1015#define RT5639_M1_T_SFT 14
1016#define RT5639_M1_T_I2S2 (0x0 << 14)
1017#define RT5639_M1_T_I2S2_D3 (0x1 << 14)
1018#define RT5639_I2S2_F_MASK (0x1 << 12)
1019#define RT5639_I2S2_F_SFT 12
1020#define RT5639_I2S2_F_I2S2_D2 (0x0 << 12)
1021#define RT5639_I2S2_F_I2S1_TCLK (0x1 << 12)
1022#define RT5639_DMIC_1_M_MASK (0x1 << 9)
1023#define RT5639_DMIC_1_M_SFT 9
1024#define RT5639_DMIC_1_M_NOR (0x0 << 9)
1025#define RT5639_DMIC_1_M_ASYN (0x1 << 9)
1026#define RT5639_DMIC_2_M_MASK (0x1 << 8)
1027#define RT5639_DMIC_2_M_SFT 8
1028#define RT5639_DMIC_2_M_NOR (0x0 << 8)
1029#define RT5639_DMIC_2_M_ASYN (0x1 << 8)
1030
1031/* ASRC Control 2 (0x84) */
1032#define RT5639_MDA_L_M_MASK (0x1 << 15)
1033#define RT5639_MDA_L_M_SFT 15
1034#define RT5639_MDA_L_M_NOR (0x0 << 15)
1035#define RT5639_MDA_L_M_ASYN (0x1 << 15)
1036#define RT5639_MDA_R_M_MASK (0x1 << 14)
1037#define RT5639_MDA_R_M_SFT 14
1038#define RT5639_MDA_R_M_NOR (0x0 << 14)
1039#define RT5639_MDA_R_M_ASYN (0x1 << 14)
1040#define RT5639_MAD_L_M_MASK (0x1 << 13)
1041#define RT5639_MAD_L_M_SFT 13
1042#define RT5639_MAD_L_M_NOR (0x0 << 13)
1043#define RT5639_MAD_L_M_ASYN (0x1 << 13)
1044#define RT5639_MAD_R_M_MASK (0x1 << 12)
1045#define RT5639_MAD_R_M_SFT 12
1046#define RT5639_MAD_R_M_NOR (0x0 << 12)
1047#define RT5639_MAD_R_M_ASYN (0x1 << 12)
1048#define RT5639_ADC_M_MASK (0x1 << 11)
1049#define RT5639_ADC_M_SFT 11
1050#define RT5639_ADC_M_NOR (0x0 << 11)
1051#define RT5639_ADC_M_ASYN (0x1 << 11)
1052#define RT5639_STO_DAC_M_MASK (0x1 << 5)
1053#define RT5639_STO_DAC_M_SFT 5
1054#define RT5639_STO_DAC_M_NOR (0x0 << 5)
1055#define RT5639_STO_DAC_M_ASYN (0x1 << 5)
1056#define RT5639_I2S1_R_D_MASK (0x1 << 4)
1057#define RT5639_I2S1_R_D_SFT 4
1058#define RT5639_I2S1_R_D_DIS (0x0 << 4)
1059#define RT5639_I2S1_R_D_EN (0x1 << 4)
1060#define RT5639_I2S2_R_D_MASK (0x1 << 3)
1061#define RT5639_I2S2_R_D_SFT 3
1062#define RT5639_I2S2_R_D_DIS (0x0 << 3)
1063#define RT5639_I2S2_R_D_EN (0x1 << 3)
1064#define RT5639_PRE_SCLK_MASK (0x3)
1065#define RT5639_PRE_SCLK_SFT 0
1066#define RT5639_PRE_SCLK_512 (0x0)
1067#define RT5639_PRE_SCLK_1024 (0x1)
1068#define RT5639_PRE_SCLK_2048 (0x2)
1069
1070/* ASRC Control 3 (0x85) */
1071#define RT5639_I2S1_RATE_MASK (0xf << 12)
1072#define RT5639_I2S1_RATE_SFT 12
1073#define RT5639_I2S2_RATE_MASK (0xf << 8)
1074#define RT5639_I2S2_RATE_SFT 8
1075
1076/* ASRC Control 4 (0x89) */
1077#define RT5639_I2S1_PD_MASK (0x7 << 12)
1078#define RT5639_I2S1_PD_SFT 12
1079#define RT5639_I2S2_PD_MASK (0x7 << 8)
1080#define RT5639_I2S2_PD_SFT 8
1081
1082/* HPOUT Over Current Detection (0x8b) */
1083#define RT5639_HP_OVCD_MASK (0x1 << 10)
1084#define RT5639_HP_OVCD_SFT 10
1085#define RT5639_HP_OVCD_DIS (0x0 << 10)
1086#define RT5639_HP_OVCD_EN (0x1 << 10)
1087#define RT5639_HP_OC_TH_MASK (0x3 << 8)
1088#define RT5639_HP_OC_TH_SFT 8
1089#define RT5639_HP_OC_TH_90 (0x0 << 8)
1090#define RT5639_HP_OC_TH_105 (0x1 << 8)
1091#define RT5639_HP_OC_TH_120 (0x2 << 8)
1092#define RT5639_HP_OC_TH_135 (0x3 << 8)
1093
1094/* Class D Over Current Control (0x8c) */
1095#define RT5639_CLSD_OC_MASK (0x1 << 9)
1096#define RT5639_CLSD_OC_SFT 9
1097#define RT5639_CLSD_OC_PU (0x0 << 9)
1098#define RT5639_CLSD_OC_PD (0x1 << 9)
1099#define RT5639_AUTO_PD_MASK (0x1 << 8)
1100#define RT5639_AUTO_PD_SFT 8
1101#define RT5639_AUTO_PD_DIS (0x0 << 8)
1102#define RT5639_AUTO_PD_EN (0x1 << 8)
1103#define RT5639_CLSD_OC_TH_MASK (0x3f)
1104#define RT5639_CLSD_OC_TH_SFT 0
1105
1106/* Class D Output Control (0x8d) */
1107#define RT5639_CLSD_RATIO_MASK (0xf << 12)
1108#define RT5639_CLSD_RATIO_SFT 12
1109#define RT5639_CLSD_OM_MASK (0x1 << 11)
1110#define RT5639_CLSD_OM_SFT 11
1111#define RT5639_CLSD_OM_MONO (0x0 << 11)
1112#define RT5639_CLSD_OM_STO (0x1 << 11)
1113#define RT5639_CLSD_SCH_MASK (0x1 << 10)
1114#define RT5639_CLSD_SCH_SFT 10
1115#define RT5639_CLSD_SCH_L (0x0 << 10)
1116#define RT5639_CLSD_SCH_S (0x1 << 10)
1117
1118/* Depop Mode Control 1 (0x8e) */
1119#define RT5639_SMT_TRIG_MASK (0x1 << 15)
1120#define RT5639_SMT_TRIG_SFT 15
1121#define RT5639_SMT_TRIG_DIS (0x0 << 15)
1122#define RT5639_SMT_TRIG_EN (0x1 << 15)
1123#define RT5639_HP_L_SMT_MASK (0x1 << 9)
1124#define RT5639_HP_L_SMT_SFT 9
1125#define RT5639_HP_L_SMT_DIS (0x0 << 9)
1126#define RT5639_HP_L_SMT_EN (0x1 << 9)
1127#define RT5639_HP_R_SMT_MASK (0x1 << 8)
1128#define RT5639_HP_R_SMT_SFT 8
1129#define RT5639_HP_R_SMT_DIS (0x0 << 8)
1130#define RT5639_HP_R_SMT_EN (0x1 << 8)
1131#define RT5639_HP_CD_PD_MASK (0x1 << 7)
1132#define RT5639_HP_CD_PD_SFT 7
1133#define RT5639_HP_CD_PD_DIS (0x0 << 7)
1134#define RT5639_HP_CD_PD_EN (0x1 << 7)
1135#define RT5639_RSTN_MASK (0x1 << 6)
1136#define RT5639_RSTN_SFT 6
1137#define RT5639_RSTN_DIS (0x0 << 6)
1138#define RT5639_RSTN_EN (0x1 << 6)
1139#define RT5639_RSTP_MASK (0x1 << 5)
1140#define RT5639_RSTP_SFT 5
1141#define RT5639_RSTP_DIS (0x0 << 5)
1142#define RT5639_RSTP_EN (0x1 << 5)
1143#define RT5639_HP_CO_MASK (0x1 << 4)
1144#define RT5639_HP_CO_SFT 4
1145#define RT5639_HP_CO_DIS (0x0 << 4)
1146#define RT5639_HP_CO_EN (0x1 << 4)
1147#define RT5639_HP_CP_MASK (0x1 << 3)
1148#define RT5639_HP_CP_SFT 3
1149#define RT5639_HP_CP_PD (0x0 << 3)
1150#define RT5639_HP_CP_PU (0x1 << 3)
1151#define RT5639_HP_SG_MASK (0x1 << 2)
1152#define RT5639_HP_SG_SFT 2
1153#define RT5639_HP_SG_DIS (0x0 << 2)
1154#define RT5639_HP_SG_EN (0x1 << 2)
1155#define RT5639_HP_DP_MASK (0x1 << 1)
1156#define RT5639_HP_DP_SFT 1
1157#define RT5639_HP_DP_PD (0x0 << 1)
1158#define RT5639_HP_DP_PU (0x1 << 1)
1159#define RT5639_HP_CB_MASK (0x1)
1160#define RT5639_HP_CB_SFT 0
1161#define RT5639_HP_CB_PD (0x0)
1162#define RT5639_HP_CB_PU (0x1)
1163
1164/* Depop Mode Control 2 (0x8f) */
1165#define RT5639_DEPOP_MASK (0x1 << 13)
1166#define RT5639_DEPOP_SFT 13
1167#define RT5639_DEPOP_AUTO (0x0 << 13)
1168#define RT5639_DEPOP_MAN (0x1 << 13)
1169#define RT5639_RAMP_MASK (0x1 << 12)
1170#define RT5639_RAMP_SFT 12
1171#define RT5639_RAMP_DIS (0x0 << 12)
1172#define RT5639_RAMP_EN (0x1 << 12)
1173#define RT5639_BPS_MASK (0x1 << 11)
1174#define RT5639_BPS_SFT 11
1175#define RT5639_BPS_DIS (0x0 << 11)
1176#define RT5639_BPS_EN (0x1 << 11)
1177#define RT5639_FAST_UPDN_MASK (0x1 << 10)
1178#define RT5639_FAST_UPDN_SFT 10
1179#define RT5639_FAST_UPDN_DIS (0x0 << 10)
1180#define RT5639_FAST_UPDN_EN (0x1 << 10)
1181#define RT5639_MRES_MASK (0x3 << 8)
1182#define RT5639_MRES_SFT 8
1183#define RT5639_MRES_15MO (0x0 << 8)
1184#define RT5639_MRES_25MO (0x1 << 8)
1185#define RT5639_MRES_35MO (0x2 << 8)
1186#define RT5639_MRES_45MO (0x3 << 8)
1187#define RT5639_VLO_MASK (0x1 << 7)
1188#define RT5639_VLO_SFT 7
1189#define RT5639_VLO_3V (0x0 << 7)
1190#define RT5639_VLO_32V (0x1 << 7)
1191#define RT5639_DIG_DP_MASK (0x1 << 6)
1192#define RT5639_DIG_DP_SFT 6
1193#define RT5639_DIG_DP_DIS (0x0 << 6)
1194#define RT5639_DIG_DP_EN (0x1 << 6)
1195#define RT5639_DP_TH_MASK (0x3 << 4)
1196#define RT5639_DP_TH_SFT 4
1197
1198/* Depop Mode Control 3 (0x90) */
1199#define RT5639_CP_SYS_MASK (0x7 << 12)
1200#define RT5639_CP_SYS_SFT 12
1201#define RT5639_CP_FQ1_MASK (0x7 << 8)
1202#define RT5639_CP_FQ1_SFT 8
1203#define RT5639_CP_FQ2_MASK (0x7 << 4)
1204#define RT5639_CP_FQ2_SFT 4
1205#define RT5639_CP_FQ3_MASK (0x7)
1206#define RT5639_CP_FQ3_SFT 0
1207
1208/* HPOUT charge pump (0x91) */
1209#define RT5639_OSW_L_MASK (0x1 << 11)
1210#define RT5639_OSW_L_SFT 11
1211#define RT5639_OSW_L_DIS (0x0 << 11)
1212#define RT5639_OSW_L_EN (0x1 << 11)
1213#define RT5639_OSW_R_MASK (0x1 << 10)
1214#define RT5639_OSW_R_SFT 10
1215#define RT5639_OSW_R_DIS (0x0 << 10)
1216#define RT5639_OSW_R_EN (0x1 << 10)
1217#define RT5639_PM_HP_MASK (0x3 << 8)
1218#define RT5639_PM_HP_SFT 8
1219#define RT5639_PM_HP_LV (0x0 << 8)
1220#define RT5639_PM_HP_MV (0x1 << 8)
1221#define RT5639_PM_HP_HV (0x2 << 8)
1222#define RT5639_IB_HP_MASK (0x3 << 6)
1223#define RT5639_IB_HP_SFT 6
1224#define RT5639_IB_HP_125IL (0x0 << 6)
1225#define RT5639_IB_HP_25IL (0x1 << 6)
1226#define RT5639_IB_HP_5IL (0x2 << 6)
1227#define RT5639_IB_HP_1IL (0x3 << 6)
1228
1229/* PV detection and SPK gain control (0x92) */
1230#define RT5639_PVDD_DET_MASK (0x1 << 15)
1231#define RT5639_PVDD_DET_SFT 15
1232#define RT5639_PVDD_DET_DIS (0x0 << 15)
1233#define RT5639_PVDD_DET_EN (0x1 << 15)
1234#define RT5639_SPK_AG_MASK (0x1 << 14)
1235#define RT5639_SPK_AG_SFT 14
1236#define RT5639_SPK_AG_DIS (0x0 << 14)
1237#define RT5639_SPK_AG_EN (0x1 << 14)
1238
1239/* Micbias Control (0x93) */
1240#define RT5639_MIC1_BS_MASK (0x1 << 15)
1241#define RT5639_MIC1_BS_SFT 15
1242#define RT5639_MIC1_BS_9AV (0x0 << 15)
1243#define RT5639_MIC1_BS_75AV (0x1 << 15)
1244#define RT5639_MIC2_BS_MASK (0x1 << 14)
1245#define RT5639_MIC2_BS_SFT 14
1246#define RT5639_MIC2_BS_9AV (0x0 << 14)
1247#define RT5639_MIC2_BS_75AV (0x1 << 14)
1248#define RT5639_MIC1_CLK_MASK (0x1 << 13)
1249#define RT5639_MIC1_CLK_SFT 13
1250#define RT5639_MIC1_CLK_DIS (0x0 << 13)
1251#define RT5639_MIC1_CLK_EN (0x1 << 13)
1252#define RT5639_MIC2_CLK_MASK (0x1 << 12)
1253#define RT5639_MIC2_CLK_SFT 12
1254#define RT5639_MIC2_CLK_DIS (0x0 << 12)
1255#define RT5639_MIC2_CLK_EN (0x1 << 12)
1256#define RT5639_MIC1_OVCD_MASK (0x1 << 11)
1257#define RT5639_MIC1_OVCD_SFT 11
1258#define RT5639_MIC1_OVCD_DIS (0x0 << 11)
1259#define RT5639_MIC1_OVCD_EN (0x1 << 11)
1260#define RT5639_MIC1_OVTH_MASK (0x3 << 9)
1261#define RT5639_MIC1_OVTH_SFT 9
1262#define RT5639_MIC1_OVTH_600UA (0x0 << 9)
1263#define RT5639_MIC1_OVTH_1500UA (0x1 << 9)
1264#define RT5639_MIC1_OVTH_2000UA (0x2 << 9)
1265#define RT5639_MIC2_OVCD_MASK (0x1 << 8)
1266#define RT5639_MIC2_OVCD_SFT 8
1267#define RT5639_MIC2_OVCD_DIS (0x0 << 8)
1268#define RT5639_MIC2_OVCD_EN (0x1 << 8)
1269#define RT5639_MIC2_OVTH_MASK (0x3 << 6)
1270#define RT5639_MIC2_OVTH_SFT 6
1271#define RT5639_MIC2_OVTH_600UA (0x0 << 6)
1272#define RT5639_MIC2_OVTH_1500UA (0x1 << 6)
1273#define RT5639_MIC2_OVTH_2000UA (0x2 << 6)
1274#define RT5639_PWR_MB_MASK (0x1 << 5)
1275#define RT5639_PWR_MB_SFT 5
1276#define RT5639_PWR_MB_PD (0x0 << 5)
1277#define RT5639_PWR_MB_PU (0x1 << 5)
1278#define RT5639_PWR_CLK25M_MASK (0x1 << 4)
1279#define RT5639_PWR_CLK25M_SFT 4
1280#define RT5639_PWR_CLK25M_PD (0x0 << 4)
1281#define RT5639_PWR_CLK25M_PU (0x1 << 4)
1282
1283/* EQ Control 1 (0xb0) */
1284#define RT5639_EQ_SRC_MASK (0x1 << 15)
1285#define RT5639_EQ_SRC_SFT 15
1286#define RT5639_EQ_SRC_DAC (0x0 << 15)
1287#define RT5639_EQ_SRC_ADC (0x1 << 15)
1288#define RT5639_EQ_UPD (0x1 << 14)
1289#define RT5639_EQ_UPD_BIT 14
1290#define RT5639_EQ_CD_MASK (0x1 << 13)
1291#define RT5639_EQ_CD_SFT 13
1292#define RT5639_EQ_CD_DIS (0x0 << 13)
1293#define RT5639_EQ_CD_EN (0x1 << 13)
1294#define RT5639_EQ_DITH_MASK (0x3 << 8)
1295#define RT5639_EQ_DITH_SFT 8
1296#define RT5639_EQ_DITH_NOR (0x0 << 8)
1297#define RT5639_EQ_DITH_LSB (0x1 << 8)
1298#define RT5639_EQ_DITH_LSB_1 (0x2 << 8)
1299#define RT5639_EQ_DITH_LSB_2 (0x3 << 8)
1300
1301/* EQ Control 2 (0xb1) */
1302#define RT5639_EQ_HPF1_M_MASK (0x1 << 8)
1303#define RT5639_EQ_HPF1_M_SFT 8
1304#define RT5639_EQ_HPF1_M_HI (0x0 << 8)
1305#define RT5639_EQ_HPF1_M_1ST (0x1 << 8)
1306#define RT5639_EQ_LPF1_M_MASK (0x1 << 7)
1307#define RT5639_EQ_LPF1_M_SFT 7
1308#define RT5639_EQ_LPF1_M_LO (0x0 << 7)
1309#define RT5639_EQ_LPF1_M_1ST (0x1 << 7)
1310#define RT5639_EQ_HPF2_MASK (0x1 << 6)
1311#define RT5639_EQ_HPF2_SFT 6
1312#define RT5639_EQ_HPF2_DIS (0x0 << 6)
1313#define RT5639_EQ_HPF2_EN (0x1 << 6)
1314#define RT5639_EQ_HPF1_MASK (0x1 << 5)
1315#define RT5639_EQ_HPF1_SFT 5
1316#define RT5639_EQ_HPF1_DIS (0x0 << 5)
1317#define RT5639_EQ_HPF1_EN (0x1 << 5)
1318#define RT5639_EQ_BPF4_MASK (0x1 << 4)
1319#define RT5639_EQ_BPF4_SFT 4
1320#define RT5639_EQ_BPF4_DIS (0x0 << 4)
1321#define RT5639_EQ_BPF4_EN (0x1 << 4)
1322#define RT5639_EQ_BPF3_MASK (0x1 << 3)
1323#define RT5639_EQ_BPF3_SFT 3
1324#define RT5639_EQ_BPF3_DIS (0x0 << 3)
1325#define RT5639_EQ_BPF3_EN (0x1 << 3)
1326#define RT5639_EQ_BPF2_MASK (0x1 << 2)
1327#define RT5639_EQ_BPF2_SFT 2
1328#define RT5639_EQ_BPF2_DIS (0x0 << 2)
1329#define RT5639_EQ_BPF2_EN (0x1 << 2)
1330#define RT5639_EQ_BPF1_MASK (0x1 << 1)
1331#define RT5639_EQ_BPF1_SFT 1
1332#define RT5639_EQ_BPF1_DIS (0x0 << 1)
1333#define RT5639_EQ_BPF1_EN (0x1 << 1)
1334#define RT5639_EQ_LPF_MASK (0x1)
1335#define RT5639_EQ_LPF_SFT 0
1336#define RT5639_EQ_LPF_DIS (0x0)
1337#define RT5639_EQ_LPF_EN (0x1)
1338
1339/* Memory Test (0xb2) */
1340#define RT5639_MT_MASK (0x1 << 15)
1341#define RT5639_MT_SFT 15
1342#define RT5639_MT_DIS (0x0 << 15)
1343#define RT5639_MT_EN (0x1 << 15)
1344
1345/* DRC/AGC Control 1 (0xb4) */
1346#define RT5639_DRC_AGC_P_MASK (0x1 << 15)
1347#define RT5639_DRC_AGC_P_SFT 15
1348#define RT5639_DRC_AGC_P_DAC (0x0 << 15)
1349#define RT5639_DRC_AGC_P_ADC (0x1 << 15)
1350#define RT5639_DRC_AGC_MASK (0x1 << 14)
1351#define RT5639_DRC_AGC_SFT 14
1352#define RT5639_DRC_AGC_DIS (0x0 << 14)
1353#define RT5639_DRC_AGC_EN (0x1 << 14)
1354#define RT5639_DRC_AGC_UPD (0x1 << 13)
1355#define RT5639_DRC_AGC_UPD_BIT 13
1356#define RT5639_DRC_AGC_AR_MASK (0x1f << 8)
1357#define RT5639_DRC_AGC_AR_SFT 8
1358#define RT5639_DRC_AGC_R_MASK (0x7 << 5)
1359#define RT5639_DRC_AGC_R_SFT 5
1360#define RT5639_DRC_AGC_R_48K (0x1 << 5)
1361#define RT5639_DRC_AGC_R_96K (0x2 << 5)
1362#define RT5639_DRC_AGC_R_192K (0x3 << 5)
1363#define RT5639_DRC_AGC_R_441K (0x5 << 5)
1364#define RT5639_DRC_AGC_R_882K (0x6 << 5)
1365#define RT5639_DRC_AGC_R_1764K (0x7 << 5)
1366#define RT5639_DRC_AGC_RC_MASK (0x1f)
1367#define RT5639_DRC_AGC_RC_SFT 0
1368
1369/* DRC/AGC Control 2 (0xb5) */
1370#define RT5639_DRC_AGC_POB_MASK (0x3f << 8)
1371#define RT5639_DRC_AGC_POB_SFT 8
1372#define RT5639_DRC_AGC_CP_MASK (0x1 << 7)
1373#define RT5639_DRC_AGC_CP_SFT 7
1374#define RT5639_DRC_AGC_CP_DIS (0x0 << 7)
1375#define RT5639_DRC_AGC_CP_EN (0x1 << 7)
1376#define RT5639_DRC_AGC_CPR_MASK (0x3 << 5)
1377#define RT5639_DRC_AGC_CPR_SFT 5
1378#define RT5639_DRC_AGC_CPR_1_1 (0x0 << 5)
1379#define RT5639_DRC_AGC_CPR_1_2 (0x1 << 5)
1380#define RT5639_DRC_AGC_CPR_1_3 (0x2 << 5)
1381#define RT5639_DRC_AGC_CPR_1_4 (0x3 << 5)
1382#define RT5639_DRC_AGC_PRB_MASK (0x1f)
1383#define RT5639_DRC_AGC_PRB_SFT 0
1384
1385/* DRC/AGC Control 3 (0xb6) */
1386#define RT5639_DRC_AGC_NGB_MASK (0xf << 12)
1387#define RT5639_DRC_AGC_NGB_SFT 12
1388#define RT5639_DRC_AGC_TAR_MASK (0x1f << 7)
1389#define RT5639_DRC_AGC_TAR_SFT 7
1390#define RT5639_DRC_AGC_NG_MASK (0x1 << 6)
1391#define RT5639_DRC_AGC_NG_SFT 6
1392#define RT5639_DRC_AGC_NG_DIS (0x0 << 6)
1393#define RT5639_DRC_AGC_NG_EN (0x1 << 6)
1394#define RT5639_DRC_AGC_NGH_MASK (0x1 << 5)
1395#define RT5639_DRC_AGC_NGH_SFT 5
1396#define RT5639_DRC_AGC_NGH_DIS (0x0 << 5)
1397#define RT5639_DRC_AGC_NGH_EN (0x1 << 5)
1398#define RT5639_DRC_AGC_NGT_MASK (0x1f)
1399#define RT5639_DRC_AGC_NGT_SFT 0
1400
1401/* ANC Control 1 (0xb8) */
1402#define RT5639_ANC_M_MASK (0x1 << 15)
1403#define RT5639_ANC_M_SFT 15
1404#define RT5639_ANC_M_NOR (0x0 << 15)
1405#define RT5639_ANC_M_REV (0x1 << 15)
1406#define RT5639_ANC_MASK (0x1 << 14)
1407#define RT5639_ANC_SFT 14
1408#define RT5639_ANC_DIS (0x0 << 14)
1409#define RT5639_ANC_EN (0x1 << 14)
1410#define RT5639_ANC_MD_MASK (0x3 << 12)
1411#define RT5639_ANC_MD_SFT 12
1412#define RT5639_ANC_MD_DIS (0x0 << 12)
1413#define RT5639_ANC_MD_67MS (0x1 << 12)
1414#define RT5639_ANC_MD_267MS (0x2 << 12)
1415#define RT5639_ANC_MD_1067MS (0x3 << 12)
1416#define RT5639_ANC_SN_MASK (0x1 << 11)
1417#define RT5639_ANC_SN_SFT 11
1418#define RT5639_ANC_SN_DIS (0x0 << 11)
1419#define RT5639_ANC_SN_EN (0x1 << 11)
1420#define RT5639_ANC_CLK_MASK (0x1 << 10)
1421#define RT5639_ANC_CLK_SFT 10
1422#define RT5639_ANC_CLK_ANC (0x0 << 10)
1423#define RT5639_ANC_CLK_REG (0x1 << 10)
1424#define RT5639_ANC_ZCD_MASK (0x3 << 8)
1425#define RT5639_ANC_ZCD_SFT 8
1426#define RT5639_ANC_ZCD_DIS (0x0 << 8)
1427#define RT5639_ANC_ZCD_T1 (0x1 << 8)
1428#define RT5639_ANC_ZCD_T2 (0x2 << 8)
1429#define RT5639_ANC_ZCD_WT (0x3 << 8)
1430#define RT5639_ANC_CS_MASK (0x1 << 7)
1431#define RT5639_ANC_CS_SFT 7
1432#define RT5639_ANC_CS_DIS (0x0 << 7)
1433#define RT5639_ANC_CS_EN (0x1 << 7)
1434#define RT5639_ANC_SW_MASK (0x1 << 6)
1435#define RT5639_ANC_SW_SFT 6
1436#define RT5639_ANC_SW_NOR (0x0 << 6)
1437#define RT5639_ANC_SW_AUTO (0x1 << 6)
1438#define RT5639_ANC_CO_L_MASK (0x3f)
1439#define RT5639_ANC_CO_L_SFT 0
1440
1441/* ANC Control 2 (0xb6) */
1442#define RT5639_ANC_FG_R_MASK (0xf << 12)
1443#define RT5639_ANC_FG_R_SFT 12
1444#define RT5639_ANC_FG_L_MASK (0xf << 8)
1445#define RT5639_ANC_FG_L_SFT 8
1446#define RT5639_ANC_CG_R_MASK (0xf << 4)
1447#define RT5639_ANC_CG_R_SFT 4
1448#define RT5639_ANC_CG_L_MASK (0xf)
1449#define RT5639_ANC_CG_L_SFT 0
1450
1451/* ANC Control 3 (0xb6) */
1452#define RT5639_ANC_CD_MASK (0x1 << 6)
1453#define RT5639_ANC_CD_SFT 6
1454#define RT5639_ANC_CD_BOTH (0x0 << 6)
1455#define RT5639_ANC_CD_IND (0x1 << 6)
1456#define RT5639_ANC_CO_R_MASK (0x3f)
1457#define RT5639_ANC_CO_R_SFT 0
1458
1459/* Jack Detect Control (0xbb) */
1460#define RT5639_JD_MASK (0x7 << 13)
1461#define RT5639_JD_SFT 13
1462#define RT5639_JD_DIS (0x0 << 13)
1463#define RT5639_JD_GPIO1 (0x1 << 13)
1464#define RT5639_JD_JD1_IN4P (0x2 << 13)
1465#define RT5639_JD_JD2_IN4N (0x3 << 13)
1466#define RT5639_JD_GPIO2 (0x4 << 13)
1467#define RT5639_JD_GPIO3 (0x5 << 13)
1468#define RT5639_JD_GPIO4 (0x6 << 13)
1469#define RT5639_JD_HP_MASK (0x1 << 11)
1470#define RT5639_JD_HP_SFT 11
1471#define RT5639_JD_HP_DIS (0x0 << 11)
1472#define RT5639_JD_HP_EN (0x1 << 11)
1473#define RT5639_JD_HP_TRG_MASK (0x1 << 10)
1474#define RT5639_JD_HP_TRG_SFT 10
1475#define RT5639_JD_HP_TRG_LO (0x0 << 10)
1476#define RT5639_JD_HP_TRG_HI (0x1 << 10)
1477#define RT5639_JD_SPL_MASK (0x1 << 9)
1478#define RT5639_JD_SPL_SFT 9
1479#define RT5639_JD_SPL_DIS (0x0 << 9)
1480#define RT5639_JD_SPL_EN (0x1 << 9)
1481#define RT5639_JD_SPL_TRG_MASK (0x1 << 8)
1482#define RT5639_JD_SPL_TRG_SFT 8
1483#define RT5639_JD_SPL_TRG_LO (0x0 << 8)
1484#define RT5639_JD_SPL_TRG_HI (0x1 << 8)
1485#define RT5639_JD_SPR_MASK (0x1 << 7)
1486#define RT5639_JD_SPR_SFT 7
1487#define RT5639_JD_SPR_DIS (0x0 << 7)
1488#define RT5639_JD_SPR_EN (0x1 << 7)
1489#define RT5639_JD_SPR_TRG_MASK (0x1 << 6)
1490#define RT5639_JD_SPR_TRG_SFT 6
1491#define RT5639_JD_SPR_TRG_LO (0x0 << 6)
1492#define RT5639_JD_SPR_TRG_HI (0x1 << 6)
1493#define RT5639_JD_MO_MASK (0x1 << 5)
1494#define RT5639_JD_MO_SFT 5
1495#define RT5639_JD_MO_DIS (0x0 << 5)
1496#define RT5639_JD_MO_EN (0x1 << 5)
1497#define RT5639_JD_MO_TRG_MASK (0x1 << 4)
1498#define RT5639_JD_MO_TRG_SFT 4
1499#define RT5639_JD_MO_TRG_LO (0x0 << 4)
1500#define RT5639_JD_MO_TRG_HI (0x1 << 4)
1501#define RT5639_JD_LO_MASK (0x1 << 3)
1502#define RT5639_JD_LO_SFT 3
1503#define RT5639_JD_LO_DIS (0x0 << 3)
1504#define RT5639_JD_LO_EN (0x1 << 3)
1505#define RT5639_JD_LO_TRG_MASK (0x1 << 2)
1506#define RT5639_JD_LO_TRG_SFT 2
1507#define RT5639_JD_LO_TRG_LO (0x0 << 2)
1508#define RT5639_JD_LO_TRG_HI (0x1 << 2)
1509#define RT5639_JD1_IN4P_MASK (0x1 << 1)
1510#define RT5639_JD1_IN4P_SFT 1
1511#define RT5639_JD1_IN4P_DIS (0x0 << 1)
1512#define RT5639_JD1_IN4P_EN (0x1 << 1)
1513#define RT5639_JD2_IN4N_MASK (0x1)
1514#define RT5639_JD2_IN4N_SFT 0
1515#define RT5639_JD2_IN4N_DIS (0x0)
1516#define RT5639_JD2_IN4N_EN (0x1)
1517
1518/* Jack detect for ANC (0xbc) */
1519#define RT5639_ANC_DET_MASK (0x3 << 4)
1520#define RT5639_ANC_DET_SFT 4
1521#define RT5639_ANC_DET_DIS (0x0 << 4)
1522#define RT5639_ANC_DET_MB1 (0x1 << 4)
1523#define RT5639_ANC_DET_MB2 (0x2 << 4)
1524#define RT5639_ANC_DET_JD (0x3 << 4)
1525#define RT5639_AD_TRG_MASK (0x1 << 3)
1526#define RT5639_AD_TRG_SFT 3
1527#define RT5639_AD_TRG_LO (0x0 << 3)
1528#define RT5639_AD_TRG_HI (0x1 << 3)
1529#define RT5639_ANCM_DET_MASK (0x3 << 4)
1530#define RT5639_ANCM_DET_SFT 4
1531#define RT5639_ANCM_DET_DIS (0x0 << 4)
1532#define RT5639_ANCM_DET_MB1 (0x1 << 4)
1533#define RT5639_ANCM_DET_MB2 (0x2 << 4)
1534#define RT5639_ANCM_DET_JD (0x3 << 4)
1535#define RT5639_AMD_TRG_MASK (0x1 << 3)
1536#define RT5639_AMD_TRG_SFT 3
1537#define RT5639_AMD_TRG_LO (0x0 << 3)
1538#define RT5639_AMD_TRG_HI (0x1 << 3)
1539
1540/* IRQ Control 1 (0xbd) */
1541#define RT5639_IRQ_JD_MASK (0x1 << 15)
1542#define RT5639_IRQ_JD_SFT 15
1543#define RT5639_IRQ_JD_BP (0x0 << 15)
1544#define RT5639_IRQ_JD_NOR (0x1 << 15)
1545#define RT5639_IRQ_OT_MASK (0x1 << 14)
1546#define RT5639_IRQ_OT_SFT 14
1547#define RT5639_IRQ_OT_BP (0x0 << 14)
1548#define RT5639_IRQ_OT_NOR (0x1 << 14)
1549#define RT5639_JD_STKY_MASK (0x1 << 13)
1550#define RT5639_JD_STKY_SFT 13
1551#define RT5639_JD_STKY_DIS (0x0 << 13)
1552#define RT5639_JD_STKY_EN (0x1 << 13)
1553#define RT5639_OT_STKY_MASK (0x1 << 12)
1554#define RT5639_OT_STKY_SFT 12
1555#define RT5639_OT_STKY_DIS (0x0 << 12)
1556#define RT5639_OT_STKY_EN (0x1 << 12)
1557#define RT5639_JD_P_MASK (0x1 << 11)
1558#define RT5639_JD_P_SFT 11
1559#define RT5639_JD_P_NOR (0x0 << 11)
1560#define RT5639_JD_P_INV (0x1 << 11)
1561#define RT5639_OT_P_MASK (0x1 << 10)
1562#define RT5639_OT_P_SFT 10
1563#define RT5639_OT_P_NOR (0x0 << 10)
1564#define RT5639_OT_P_INV (0x1 << 10)
1565
1566/* IRQ Control 2 (0xbe) */
1567#define RT5639_IRQ_MB1_OC_MASK (0x1 << 15)
1568#define RT5639_IRQ_MB1_OC_SFT 15
1569#define RT5639_IRQ_MB1_OC_BP (0x0 << 15)
1570#define RT5639_IRQ_MB1_OC_NOR (0x1 << 15)
1571#define RT5639_IRQ_MB2_OC_MASK (0x1 << 14)
1572#define RT5639_IRQ_MB2_OC_SFT 14
1573#define RT5639_IRQ_MB2_OC_BP (0x0 << 14)
1574#define RT5639_IRQ_MB2_OC_NOR (0x1 << 14)
1575#define RT5639_MB1_OC_STKY_MASK (0x1 << 11)
1576#define RT5639_MB1_OC_STKY_SFT 11
1577#define RT5639_MB1_OC_STKY_DIS (0x0 << 11)
1578#define RT5639_MB1_OC_STKY_EN (0x1 << 11)
1579#define RT5639_MB2_OC_STKY_MASK (0x1 << 10)
1580#define RT5639_MB2_OC_STKY_SFT 10
1581#define RT5639_MB2_OC_STKY_DIS (0x0 << 10)
1582#define RT5639_MB2_OC_STKY_EN (0x1 << 10)
1583#define RT5639_MB1_OC_P_MASK (0x1 << 7)
1584#define RT5639_MB1_OC_P_SFT 7
1585#define RT5639_MB1_OC_P_NOR (0x0 << 7)
1586#define RT5639_MB1_OC_P_INV (0x1 << 7)
1587#define RT5639_MB2_OC_P_MASK (0x1 << 6)
1588#define RT5639_MB2_OC_P_SFT 6
1589#define RT5639_MB2_OC_P_NOR (0x0 << 6)
1590#define RT5639_MB2_OC_P_INV (0x1 << 6)
1591#define RT5639_MB1_OC_CLR (0x1 << 3)
1592#define RT5639_MB1_OC_CLR_SFT 3
1593#define RT5639_MB2_OC_CLR (0x1 << 2)
1594#define RT5639_MB2_OC_CLR_SFT 2
1595
1596/* GPIO Control 1 (0xc0) */
1597#define RT5639_GP1_PIN_MASK (0x1 << 15)
1598#define RT5639_GP1_PIN_SFT 15
1599#define RT5639_GP1_PIN_GPIO1 (0x0 << 15)
1600#define RT5639_GP1_PIN_IRQ (0x1 << 15)
1601#define RT5639_GP2_PIN_MASK (0x1 << 14)
1602#define RT5639_GP2_PIN_SFT 14
1603#define RT5639_GP2_PIN_GPIO2 (0x0 << 14)
1604#define RT5639_GP2_PIN_DMIC1_SCL (0x1 << 14)
1605#define RT5639_GP3_PIN_MASK (0x3 << 12)
1606#define RT5639_GP3_PIN_SFT 12
1607#define RT5639_GP3_PIN_GPIO3 (0x0 << 12)
1608#define RT5639_GP3_PIN_DMIC1_SDA (0x1 << 12)
1609#define RT5639_GP3_PIN_IRQ (0x2 << 12)
1610#define RT5639_GP4_PIN_MASK (0x1 << 11)
1611#define RT5639_GP4_PIN_SFT 11
1612#define RT5639_GP4_PIN_GPIO4 (0x0 << 11)
1613#define RT5639_GP4_PIN_DMIC2_SDA (0x1 << 11)
1614#define RT5639_DP_SIG_MASK (0x1 << 10)
1615#define RT5639_DP_SIG_SFT 10
1616#define RT5639_DP_SIG_TEST (0x0 << 10)
1617#define RT5639_DP_SIG_AP (0x1 << 10)
1618#define RT5639_GPIO_M_MASK (0x1 << 9)
1619#define RT5639_GPIO_M_SFT 9
1620#define RT5639_GPIO_M_FLT (0x0 << 9)
1621#define RT5639_GPIO_M_PH (0x1 << 9)
1622
1623/* GPIO Control 3 (0xc2) */
1624#define RT5639_GP4_PF_MASK (0x1 << 11)
1625#define RT5639_GP4_PF_SFT 11
1626#define RT5639_GP4_PF_IN (0x0 << 11)
1627#define RT5639_GP4_PF_OUT (0x1 << 11)
1628#define RT5639_GP4_OUT_MASK (0x1 << 10)
1629#define RT5639_GP4_OUT_SFT 10
1630#define RT5639_GP4_OUT_LO (0x0 << 10)
1631#define RT5639_GP4_OUT_HI (0x1 << 10)
1632#define RT5639_GP4_P_MASK (0x1 << 9)
1633#define RT5639_GP4_P_SFT 9
1634#define RT5639_GP4_P_NOR (0x0 << 9)
1635#define RT5639_GP4_P_INV (0x1 << 9)
1636#define RT5639_GP3_PF_MASK (0x1 << 8)
1637#define RT5639_GP3_PF_SFT 8
1638#define RT5639_GP3_PF_IN (0x0 << 8)
1639#define RT5639_GP3_PF_OUT (0x1 << 8)
1640#define RT5639_GP3_OUT_MASK (0x1 << 7)
1641#define RT5639_GP3_OUT_SFT 7
1642#define RT5639_GP3_OUT_LO (0x0 << 7)
1643#define RT5639_GP3_OUT_HI (0x1 << 7)
1644#define RT5639_GP3_P_MASK (0x1 << 6)
1645#define RT5639_GP3_P_SFT 6
1646#define RT5639_GP3_P_NOR (0x0 << 6)
1647#define RT5639_GP3_P_INV (0x1 << 6)
1648#define RT5639_GP2_PF_MASK (0x1 << 5)
1649#define RT5639_GP2_PF_SFT 5
1650#define RT5639_GP2_PF_IN (0x0 << 5)
1651#define RT5639_GP2_PF_OUT (0x1 << 5)
1652#define RT5639_GP2_OUT_MASK (0x1 << 4)
1653#define RT5639_GP2_OUT_SFT 4
1654#define RT5639_GP2_OUT_LO (0x0 << 4)
1655#define RT5639_GP2_OUT_HI (0x1 << 4)
1656#define RT5639_GP2_P_MASK (0x1 << 3)
1657#define RT5639_GP2_P_SFT 3
1658#define RT5639_GP2_P_NOR (0x0 << 3)
1659#define RT5639_GP2_P_INV (0x1 << 3)
1660#define RT5639_GP1_PF_MASK (0x1 << 2)
1661#define RT5639_GP1_PF_SFT 2
1662#define RT5639_GP1_PF_IN (0x0 << 2)
1663#define RT5639_GP1_PF_OUT (0x1 << 2)
1664#define RT5639_GP1_OUT_MASK (0x1 << 1)
1665#define RT5639_GP1_OUT_SFT 1
1666#define RT5639_GP1_OUT_LO (0x0 << 1)
1667#define RT5639_GP1_OUT_HI (0x1 << 1)
1668#define RT5639_GP1_P_MASK (0x1)
1669#define RT5639_GP1_P_SFT 0
1670#define RT5639_GP1_P_NOR (0x0)
1671#define RT5639_GP1_P_INV (0x1)
1672
1673/* FM34-500 Register Control 1 (0xc4) */
1674#define RT5639_DSP_ADD_SFT 0
1675
1676/* FM34-500 Register Control 2 (0xc5) */
1677#define RT5639_DSP_DAT_SFT 0
1678
1679/* FM34-500 Register Control 3 (0xc6) */
1680#define RT5639_DSP_BUSY_MASK (0x1 << 15)
1681#define RT5639_DSP_BUSY_BIT 15
1682#define RT5639_DSP_DS_MASK (0x1 << 14)
1683#define RT5639_DSP_DS_SFT 14
1684#define RT5639_DSP_DS_FM3010 (0x1 << 14)
1685#define RT5639_DSP_DS_TEMP (0x1 << 14)
1686#define RT5639_DSP_CLK_MASK (0x3 << 12)
1687#define RT5639_DSP_CLK_SFT 12
1688#define RT5639_DSP_CLK_384K (0x0 << 12)
1689#define RT5639_DSP_CLK_192K (0x1 << 12)
1690#define RT5639_DSP_CLK_96K (0x2 << 12)
1691#define RT5639_DSP_CLK_64K (0x3 << 12)
1692#define RT5639_DSP_PD_PIN_MASK (0x1 << 11)
1693#define RT5639_DSP_PD_PIN_SFT 11
1694#define RT5639_DSP_PD_PIN_LO (0x0 << 11)
1695#define RT5639_DSP_PD_PIN_HI (0x1 << 11)
1696#define RT5639_DSP_RST_PIN_MASK (0x1 << 10)
1697#define RT5639_DSP_RST_PIN_SFT 10
1698#define RT5639_DSP_RST_PIN_LO (0x0 << 10)
1699#define RT5639_DSP_RST_PIN_HI (0x1 << 10)
1700#define RT5639_DSP_R_EN (0x1 << 9)
1701#define RT5639_DSP_W_EN (0x1 << 8)
1702#define RT5639_DSP_CMD_MASK (0xff)
1703#define RT5639_DSP_CMD_MW (0x3b) /* Memory Write */
1704#define RT5639_DSP_CMD_MR (0x37) /* Memory Read */
1705#define RT5639_DSP_CMD_RR (0x60) /* Register Read */
1706#define RT5639_DSP_CMD_RW (0x68) /* Register Write */
1707#define RT5639_DSP_REG_DATHI (0x26) /* High Data Addr */
1708#define RT5639_DSP_REG_DATLO (0x25) /* Low Data Addr */
1709
1710/* Programmable Register Array Control 1 (0xc8) */
1711#define RT5639_REG_SEQ_MASK (0xf << 12)
1712#define RT5639_REG_SEQ_SFT 12
1713#define RT5639_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1714#define RT5639_SEQ1_ST_SFT 11
1715#define RT5639_SEQ1_ST_RUN (0x0 << 11)
1716#define RT5639_SEQ1_ST_FIN (0x1 << 11)
1717#define RT5639_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1718#define RT5639_SEQ2_ST_SFT 10
1719#define RT5639_SEQ2_ST_RUN (0x0 << 10)
1720#define RT5639_SEQ2_ST_FIN (0x1 << 10)
1721#define RT5639_REG_LV_MASK (0x1 << 9)
1722#define RT5639_REG_LV_SFT 9
1723#define RT5639_REG_LV_MX (0x0 << 9)
1724#define RT5639_REG_LV_PR (0x1 << 9)
1725#define RT5639_SEQ_2_PT_MASK (0x1 << 8)
1726#define RT5639_SEQ_2_PT_BIT 8
1727#define RT5639_REG_IDX_MASK (0xff)
1728#define RT5639_REG_IDX_SFT 0
1729
1730/* Programmable Register Array Control 2 (0xc9) */
1731#define RT5639_REG_DAT_MASK (0xffff)
1732#define RT5639_REG_DAT_SFT 0
1733
1734/* Programmable Register Array Control 3 (0xca) */
1735#define RT5639_SEQ_DLY_MASK (0xff << 8)
1736#define RT5639_SEQ_DLY_SFT 8
1737#define RT5639_PROG_MASK (0x1 << 7)
1738#define RT5639_PROG_SFT 7
1739#define RT5639_PROG_DIS (0x0 << 7)
1740#define RT5639_PROG_EN (0x1 << 7)
1741#define RT5639_SEQ1_PT_RUN (0x1 << 6)
1742#define RT5639_SEQ1_PT_RUN_BIT 6
1743#define RT5639_SEQ2_PT_RUN (0x1 << 5)
1744#define RT5639_SEQ2_PT_RUN_BIT 5
1745
1746/* Programmable Register Array Control 4 (0xcb) */
1747#define RT5639_SEQ1_START_MASK (0xf << 8)
1748#define RT5639_SEQ1_START_SFT 8
1749#define RT5639_SEQ1_END_MASK (0xf)
1750#define RT5639_SEQ1_END_SFT 0
1751
1752/* Programmable Register Array Control 5 (0xcc) */
1753#define RT5639_SEQ2_START_MASK (0xf << 8)
1754#define RT5639_SEQ2_START_SFT 8
1755#define RT5639_SEQ2_END_MASK (0xf)
1756#define RT5639_SEQ2_END_SFT 0
1757
1758/* Scramble Function (0xcd) */
1759#define RT5639_SCB_KEY_MASK (0xff)
1760#define RT5639_SCB_KEY_SFT 0
1761
1762/* Scramble Control (0xce) */
1763#define RT5639_SCB_SWAP_MASK (0x1 << 15)
1764#define RT5639_SCB_SWAP_SFT 15
1765#define RT5639_SCB_SWAP_DIS (0x0 << 15)
1766#define RT5639_SCB_SWAP_EN (0x1 << 15)
1767#define RT5639_SCB_MASK (0x1 << 14)
1768#define RT5639_SCB_SFT 14
1769#define RT5639_SCB_DIS (0x0 << 14)
1770#define RT5639_SCB_EN (0x1 << 14)
1771
1772/* Baseback Control (0xcf) */
1773#define RT5639_BB_MASK (0x1 << 15)
1774#define RT5639_BB_SFT 15
1775#define RT5639_BB_DIS (0x0 << 15)
1776#define RT5639_BB_EN (0x1 << 15)
1777#define RT5639_BB_CT_MASK (0x7 << 12)
1778#define RT5639_BB_CT_SFT 12
1779#define RT5639_BB_CT_A (0x0 << 12)
1780#define RT5639_BB_CT_B (0x1 << 12)
1781#define RT5639_BB_CT_C (0x2 << 12)
1782#define RT5639_BB_CT_D (0x3 << 12)
1783#define RT5639_M_BB_L_MASK (0x1 << 9)
1784#define RT5639_M_BB_L_SFT 9
1785#define RT5639_M_BB_R_MASK (0x1 << 8)
1786#define RT5639_M_BB_R_SFT 8
1787#define RT5639_M_BB_HPF_L_MASK (0x1 << 7)
1788#define RT5639_M_BB_HPF_L_SFT 7
1789#define RT5639_M_BB_HPF_R_MASK (0x1 << 6)
1790#define RT5639_M_BB_HPF_R_SFT 6
1791#define RT5639_G_BB_BST_MASK (0x3f)
1792#define RT5639_G_BB_BST_SFT 0
1793
1794/* MP3 Plus Control 1 (0xd0) */
1795#define RT5639_M_MP3_L_MASK (0x1 << 15)
1796#define RT5639_M_MP3_L_SFT 15
1797#define RT5639_M_MP3_R_MASK (0x1 << 14)
1798#define RT5639_M_MP3_R_SFT 14
1799#define RT5639_M_MP3_MASK (0x1 << 13)
1800#define RT5639_M_MP3_SFT 13
1801#define RT5639_M_MP3_DIS (0x0 << 13)
1802#define RT5639_M_MP3_EN (0x1 << 13)
1803#define RT5639_EG_MP3_MASK (0x1f << 8)
1804#define RT5639_EG_MP3_SFT 8
1805#define RT5639_MP3_HLP_MASK (0x1 << 7)
1806#define RT5639_MP3_HLP_SFT 7
1807#define RT5639_MP3_HLP_DIS (0x0 << 7)
1808#define RT5639_MP3_HLP_EN (0x1 << 7)
1809#define RT5639_M_MP3_ORG_L_MASK (0x1 << 6)
1810#define RT5639_M_MP3_ORG_L_SFT 6
1811#define RT5639_M_MP3_ORG_R_MASK (0x1 << 5)
1812#define RT5639_M_MP3_ORG_R_SFT 5
1813
1814/* MP3 Plus Control 2 (0xd1) */
1815#define RT5639_MP3_WT_MASK (0x1 << 13)
1816#define RT5639_MP3_WT_SFT 13
1817#define RT5639_MP3_WT_1_4 (0x0 << 13)
1818#define RT5639_MP3_WT_1_2 (0x1 << 13)
1819#define RT5639_OG_MP3_MASK (0x1f << 8)
1820#define RT5639_OG_MP3_SFT 8
1821#define RT5639_HG_MP3_MASK (0x3f)
1822#define RT5639_HG_MP3_SFT 0
1823
1824/* 3D HP Control 1 (0xd2) */
1825#define RT5639_3D_CF_MASK (0x1 << 15)
1826#define RT5639_3D_CF_SFT 15
1827#define RT5639_3D_CF_DIS (0x0 << 15)
1828#define RT5639_3D_CF_EN (0x1 << 15)
1829#define RT5639_3D_HP_MASK (0x1 << 14)
1830#define RT5639_3D_HP_SFT 14
1831#define RT5639_3D_HP_DIS (0x0 << 14)
1832#define RT5639_3D_HP_EN (0x1 << 14)
1833#define RT5639_3D_BT_MASK (0x1 << 13)
1834#define RT5639_3D_BT_SFT 13
1835#define RT5639_3D_BT_DIS (0x0 << 13)
1836#define RT5639_3D_BT_EN (0x1 << 13)
1837#define RT5639_3D_1F_MIX_MASK (0x3 << 11)
1838#define RT5639_3D_1F_MIX_SFT 11
1839#define RT5639_3D_HP_M_MASK (0x1 << 10)
1840#define RT5639_3D_HP_M_SFT 10
1841#define RT5639_3D_HP_M_SUR (0x0 << 10)
1842#define RT5639_3D_HP_M_FRO (0x1 << 10)
1843#define RT5639_M_3D_HRTF_MASK (0x1 << 9)
1844#define RT5639_M_3D_HRTF_SFT 9
1845#define RT5639_M_3D_D2H_MASK (0x1 << 8)
1846#define RT5639_M_3D_D2H_SFT 8
1847#define RT5639_M_3D_D2R_MASK (0x1 << 7)
1848#define RT5639_M_3D_D2R_SFT 7
1849#define RT5639_M_3D_REVB_MASK (0x1 << 6)
1850#define RT5639_M_3D_REVB_SFT 6
1851
1852/* Adjustable high pass filter control 1 (0xd3) */
1853#define RT5639_2ND_HPF_MASK (0x1 << 15)
1854#define RT5639_2ND_HPF_SFT 15
1855#define RT5639_2ND_HPF_DIS (0x0 << 15)
1856#define RT5639_2ND_HPF_EN (0x1 << 15)
1857#define RT5639_HPF_CF_L_MASK (0x7 << 12)
1858#define RT5639_HPF_CF_L_SFT 12
1859#define RT5639_1ST_HPF_MASK (0x1 << 11)
1860#define RT5639_1ST_HPF_SFT 11
1861#define RT5639_1ST_HPF_DIS (0x0 << 11)
1862#define RT5639_1ST_HPF_EN (0x1 << 11)
1863#define RT5639_HPF_CF_R_MASK (0x7 << 8)
1864#define RT5639_HPF_CF_R_SFT 8
1865#define RT5639_ZD_T_MASK (0x3 << 6)
1866#define RT5639_ZD_T_SFT 6
1867#define RT5639_ZD_F_MASK (0x3 << 4)
1868#define RT5639_ZD_F_SFT 4
1869#define RT5639_ZD_F_IM (0x0 << 4)
1870#define RT5639_ZD_F_ZC_IM (0x1 << 4)
1871#define RT5639_ZD_F_ZC_IOD (0x2 << 4)
1872#define RT5639_ZD_F_UN (0x3 << 4)
1873
1874/* HP calibration control and Amp detection (0xd6) */
1875#define RT5639_SI_DAC_MASK (0x1 << 11)
1876#define RT5639_SI_DAC_SFT 11
1877#define RT5639_SI_DAC_AUTO (0x0 << 11)
1878#define RT5639_SI_DAC_TEST (0x1 << 11)
1879#define RT5639_DC_CAL_M_MASK (0x1 << 10)
1880#define RT5639_DC_CAL_M_SFT 10
1881#define RT5639_DC_CAL_M_CAL (0x0 << 10)
1882#define RT5639_DC_CAL_M_NOR (0x1 << 10)
1883#define RT5639_DC_CAL_MASK (0x1 << 9)
1884#define RT5639_DC_CAL_SFT 9
1885#define RT5639_DC_CAL_DIS (0x0 << 9)
1886#define RT5639_DC_CAL_EN (0x1 << 9)
1887#define RT5639_HPD_RCV_MASK (0x7 << 6)
1888#define RT5639_HPD_RCV_SFT 6
1889#define RT5639_HPD_PS_MASK (0x1 << 5)
1890#define RT5639_HPD_PS_SFT 5
1891#define RT5639_HPD_PS_DIS (0x0 << 5)
1892#define RT5639_HPD_PS_EN (0x1 << 5)
1893#define RT5639_CAL_M_MASK (0x1 << 4)
1894#define RT5639_CAL_M_SFT 4
1895#define RT5639_CAL_M_DEP (0x0 << 4)
1896#define RT5639_CAL_M_CAL (0x1 << 4)
1897#define RT5639_CAL_MASK (0x1 << 3)
1898#define RT5639_CAL_SFT 3
1899#define RT5639_CAL_DIS (0x0 << 3)
1900#define RT5639_CAL_EN (0x1 << 3)
1901#define RT5639_CAL_TEST_MASK (0x1 << 2)
1902#define RT5639_CAL_TEST_SFT 2
1903#define RT5639_CAL_TEST_DIS (0x0 << 2)
1904#define RT5639_CAL_TEST_EN (0x1 << 2)
1905#define RT5639_CAL_P_MASK (0x3)
1906#define RT5639_CAL_P_SFT 0
1907#define RT5639_CAL_P_NONE (0x0)
1908#define RT5639_CAL_P_CAL (0x1)
1909#define RT5639_CAL_P_DAC_CAL (0x2)
1910
1911/* Soft volume and zero cross control 1 (0xd9) */
1912#define RT5639_SV_MASK (0x1 << 15)
1913#define RT5639_SV_SFT 15
1914#define RT5639_SV_DIS (0x0 << 15)
1915#define RT5639_SV_EN (0x1 << 15)
1916#define RT5639_SPO_SV_MASK (0x1 << 14)
1917#define RT5639_SPO_SV_SFT 14
1918#define RT5639_SPO_SV_DIS (0x0 << 14)
1919#define RT5639_SPO_SV_EN (0x1 << 14)
1920#define RT5639_OUT_SV_MASK (0x1 << 13)
1921#define RT5639_OUT_SV_SFT 13
1922#define RT5639_OUT_SV_DIS (0x0 << 13)
1923#define RT5639_OUT_SV_EN (0x1 << 13)
1924#define RT5639_HP_SV_MASK (0x1 << 12)
1925#define RT5639_HP_SV_SFT 12
1926#define RT5639_HP_SV_DIS (0x0 << 12)
1927#define RT5639_HP_SV_EN (0x1 << 12)
1928#define RT5639_ZCD_DIG_MASK (0x1 << 11)
1929#define RT5639_ZCD_DIG_SFT 11
1930#define RT5639_ZCD_DIG_DIS (0x0 << 11)
1931#define RT5639_ZCD_DIG_EN (0x1 << 11)
1932#define RT5639_ZCD_MASK (0x1 << 10)
1933#define RT5639_ZCD_SFT 10
1934#define RT5639_ZCD_PD (0x0 << 10)
1935#define RT5639_ZCD_PU (0x1 << 10)
1936#define RT5639_M_ZCD_MASK (0x3f << 4)
1937#define RT5639_M_ZCD_SFT 4
1938#define RT5639_M_ZCD_RM_L (0x1 << 9)
1939#define RT5639_M_ZCD_RM_R (0x1 << 8)
1940#define RT5639_M_ZCD_SM_L (0x1 << 7)
1941#define RT5639_M_ZCD_SM_R (0x1 << 6)
1942#define RT5639_M_ZCD_OM_L (0x1 << 5)
1943#define RT5639_M_ZCD_OM_R (0x1 << 4)
1944#define RT5639_SV_DLY_MASK (0xf)
1945#define RT5639_SV_DLY_SFT 0
1946
1947/* Soft volume and zero cross control 2 (0xda) */
1948#define RT5639_ZCD_HP_MASK (0x1 << 15)
1949#define RT5639_ZCD_HP_SFT 15
1950#define RT5639_ZCD_HP_DIS (0x0 << 15)
1951#define RT5639_ZCD_HP_EN (0x1 << 15)
1952
1953
1954/* Codec Private Register definition */
1955/* 3D Speaker Control (0x63) */
1956#define RT5639_3D_SPK_MASK (0x1 << 15)
1957#define RT5639_3D_SPK_SFT 15
1958#define RT5639_3D_SPK_DIS (0x0 << 15)
1959#define RT5639_3D_SPK_EN (0x1 << 15)
1960#define RT5639_3D_SPK_M_MASK (0x3 << 13)
1961#define RT5639_3D_SPK_M_SFT 13
1962#define RT5639_3D_SPK_CG_MASK (0x1f << 8)
1963#define RT5639_3D_SPK_CG_SFT 8
1964#define RT5639_3D_SPK_SG_MASK (0x1f)
1965#define RT5639_3D_SPK_SG_SFT 0
1966
1967/* Wind Noise Detection Control 1 (0x6c) */
1968#define RT5639_WND_MASK (0x1 << 15)
1969#define RT5639_WND_SFT 15
1970#define RT5639_WND_DIS (0x0 << 15)
1971#define RT5639_WND_EN (0x1 << 15)
1972
1973/* Wind Noise Detection Control 2 (0x6d) */
1974#define RT5639_WND_FC_NW_MASK (0x3f << 10)
1975#define RT5639_WND_FC_NW_SFT 10
1976#define RT5639_WND_FC_WK_MASK (0x3f << 4)
1977#define RT5639_WND_FC_WK_SFT 4
1978
1979/* Wind Noise Detection Control 3 (0x6e) */
1980#define RT5639_HPF_FC_MASK (0x3f << 6)
1981#define RT5639_HPF_FC_SFT 6
1982#define RT5639_WND_FC_ST_MASK (0x3f)
1983#define RT5639_WND_FC_ST_SFT 0
1984
1985/* Wind Noise Detection Control 4 (0x6f) */
1986#define RT5639_WND_TH_LO_MASK (0x3ff)
1987#define RT5639_WND_TH_LO_SFT 0
1988
1989/* Wind Noise Detection Control 5 (0x70) */
1990#define RT5639_WND_TH_HI_MASK (0x3ff)
1991#define RT5639_WND_TH_HI_SFT 0
1992
1993/* Wind Noise Detection Control 8 (0x73) */
1994#define RT5639_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1995#define RT5639_WND_WIND_SFT 13
1996#define RT5639_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1997#define RT5639_WND_STRONG_SFT 12
1998enum {
1999 RT5639_NO_WIND,
2000 RT5639_BREEZE,
2001 RT5639_STORM,
2002};
2003
2004/* Dipole Speaker Interface (0x75) */
2005#define RT5639_DP_ATT_MASK (0x3 << 14)
2006#define RT5639_DP_ATT_SFT 14
2007#define RT5639_DP_SPK_MASK (0x1 << 10)
2008#define RT5639_DP_SPK_SFT 10
2009#define RT5639_DP_SPK_DIS (0x0 << 10)
2010#define RT5639_DP_SPK_EN (0x1 << 10)
2011
2012/* EQ Pre Volume Control (0xb3) */
2013#define RT5639_EQ_PRE_VOL_MASK (0xffff)
2014#define RT5639_EQ_PRE_VOL_SFT 0
2015
2016/* EQ Post Volume Control (0xb4) */
2017#define RT5639_EQ_PST_VOL_MASK (0xffff)
2018#define RT5639_EQ_PST_VOL_SFT 0
2019
2020
2021
2022/* Volume Rescale */
2023#define RT5639_VOL_RSCL_MAX 0x27
2024#define RT5639_VOL_RSCL_RANGE 0x1F
2025/* Debug String Length */
2026#define RT5639_REG_DISP_LEN 10
2027
2028#define RT5639_NO_JACK BIT(0)
2029#define RT5639_HEADSET_DET BIT(1)
2030#define RT5639_HEADPHO_DET BIT(2)
2031
2032int rt5639_headset_detect(struct snd_soc_codec *codec, int jack_insert);
2033
2034/* System Clock Source */
2035enum {
2036 RT5639_SCLK_S_MCLK,
2037 RT5639_SCLK_S_PLL1,
2038 RT5639_SCLK_S_RCCLK,
2039};
2040
2041/* PLL1 Source */
2042enum {
2043 RT5639_PLL1_S_MCLK,
2044 RT5639_PLL1_S_BCLK1,
2045 RT5639_PLL1_S_BCLK2,
2046 RT5639_PLL1_S_BCLK3,
2047};
2048
2049enum {
2050 RT5639_AIF1,
2051 RT5639_AIF2,
2052 RT5639_AIF3,
2053 RT5639_AIFS,
2054};
2055
2056#define RT5639_U_IF1 (0x1)
2057#define RT5639_U_IF2 (0x1 << 1)
2058#define RT5639_U_IF3 (0x1 << 2)
2059
2060enum {
2061 RT5639_IF_123,
2062 RT5639_IF_132,
2063 RT5639_IF_312,
2064 RT5639_IF_321,
2065 RT5639_IF_231,
2066 RT5639_IF_213,
2067 RT5639_IF_113,
2068 RT5639_IF_223,
2069 RT5639_IF_ALL,
2070};
2071
2072enum {
2073 RT5639_DMIC_DIS,
2074 RT5639_DMIC1,
2075 RT5639_DMIC2,
2076};
2077
2078struct rt5639_pll_code {
2079 bool m_bp; /* Indicates bypass m code or not. */
2080 int m_code;
2081 int n_code;
2082 int k_code;
2083};
2084
2085struct rt5639_priv {
2086 struct snd_soc_codec *codec;
2087
2088 int aif_pu;
2089 int sysclk;
2090 int sysclk_src;
2091 int lrck[RT5639_AIFS];
2092 int bclk[RT5639_AIFS];
2093 int master[RT5639_AIFS];
2094
2095 int pll_src;
2096 int pll_in;
2097 int pll_out;
2098
2099 int dmic_en;
2100 int dsp_sw;
2101};
2102
2103
2104#endif /* __RT5639_H__ */
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
new file mode 100644
index 00000000000..e3d0af02e39
--- /dev/null
+++ b/sound/soc/codecs/rt5640.c
@@ -0,0 +1,2546 @@
1/*
2 * rt5640.c -- RT5640 ALSA SoC audio codec driver
3 *
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include <sound/initval.h>
25#include <sound/tlv.h>
26
27#include "rt5640.h"
28#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
29#include "rt5640-dsp.h"
30#endif
31
32#define RT5640_DEMO 1
33#define RT5640_REG_RW 1
34#define RT5640_DET_EXT_MIC 0
35
36#ifdef RT5640_DEMO
37struct rt5640_init_reg {
38 u8 reg;
39 u16 val;
40};
41
42static struct rt5640_init_reg init_list[] = {
43 {RT5640_DUMMY1 , 0x3701},/*fa[12:13] = 1'b;fa[8~10]=1;fa[0]=1*/
44 {RT5640_DEPOP_M1 , 0x0019},/* 8e[4:3] = 11'b; 8e[0] = 1'b */
45 {RT5640_DEPOP_M2 , 0x3100},/* 8f[13] = 1'b */
46 {RT5640_ADDA_CLK1 , 0x1114},/* 73[2] = 1'b */
47 {RT5640_MICBIAS , 0x3030},/* 93[5:4] = 11'b */
48 {RT5640_PRIV_INDEX , 0x003d},/* PR3d[12] = 1'b */
49 {RT5640_PRIV_DATA , 0x3600},
50 {RT5640_CLS_D_OUT , 0xa000},/* 8d[11] = 0'b */
51 {RT5640_PRIV_INDEX , 0x001c},/* PR1c = 0D21'h */
52 {RT5640_PRIV_DATA , 0x0D21},
53 {RT5640_PRIV_INDEX , 0x001b},/* PR1B = 0D21'h */
54 {RT5640_PRIV_DATA , 0x0000},
55 {RT5640_PRIV_INDEX , 0x0012},/* PR12 = 0aa8'h */
56 {RT5640_PRIV_DATA , 0x0aa8},
57 {RT5640_PRIV_INDEX , 0x0014},/* PR14 = 0aaa'h */
58 {RT5640_PRIV_DATA , 0x0aaa},
59 {RT5640_PRIV_INDEX , 0x0020},/* PR20 = 6110'h */
60 {RT5640_PRIV_DATA , 0x6110},
61 {RT5640_PRIV_INDEX , 0x0021},/* PR21 = e0e0'h */
62 {RT5640_PRIV_DATA , 0xe0e0},
63 {RT5640_PRIV_INDEX , 0x0023},/* PR23 = 1804'h */
64 {RT5640_PRIV_DATA , 0x1804},
65 /*playback*/
66 {RT5640_STO_DAC_MIXER , 0x1414},/*Dig inf 1 -> Sto DAC mixer -> DACL*/
67 {RT5640_OUT_L3_MIXER , 0x01fe},/*DACL1 -> OUTMIXL*/
68 {RT5640_OUT_R3_MIXER , 0x01fe},/*DACR1 -> OUTMIXR */
69 {RT5640_HP_VOL , 0x8888},/* OUTMIX -> HPVOL */
70 {RT5640_HPO_MIXER , 0xc000},/* HPVOL -> HPOLMIX */
71/* {RT5640_HPO_MIXER , 0xa000},// DAC1 -> HPOLMIX */
72 {RT5640_SPK_L_MIXER , 0x0036},/* DACL1 -> SPKMIXL */
73 {RT5640_SPK_R_MIXER , 0x0036},/* DACR1 -> SPKMIXR */
74 {RT5640_SPK_VOL , 0x8888},/* SPKMIX -> SPKVOL */
75 {RT5640_SPO_L_MIXER , 0xe800},/* SPKVOLL -> SPOLMIX */
76 {RT5640_SPO_R_MIXER , 0x2800},/* SPKVOLR -> SPORMIX */
77/* {RT5640_SPO_L_MIXER , 0xb800},//DAC -> SPOLMIX */
78/* {RT5640_SPO_R_MIXER , 0x1800},//DAC -> SPORMIX */
79/* {RT5640_I2S1_SDP , 0xD000},//change IIS1 and IIS2 */
80 /*record*/
81 {RT5640_IN1_IN2 , 0x5080},/*IN1 boost 40db & differential mode*/
82 {RT5640_IN3_IN4 , 0x0500},/*IN2 boost 40db & signal ended mode*/
83 {RT5640_REC_L2_MIXER , 0x005f},/* enable Mic1 -> RECMIXL */
84 {RT5640_REC_R2_MIXER , 0x005f},/* enable Mic1 -> RECMIXR */
85/* {RT5640_REC_L2_MIXER , 0x006f},//Mic2 -> RECMIXL */
86/* {RT5640_REC_R2_MIXER , 0x006f},//Mic2 -> RECMIXR */
87 {RT5640_STO_ADC_MIXER , 0x3020},/* ADC -> Sto ADC mixer */
88
89#if RT5640_DET_EXT_MIC
90 {RT5640_MICBIAS , 0x3800},/* enable MICBIAS short current */
91 {RT5640_GPIO_CTRL1 , 0x8400},/* set GPIO1 to IRQ */
92 {RT5640_GPIO_CTRL3 , 0x0004},/* set GPIO1 output */
93 {RT5640_IRQ_CTRL2 , 0x8000},/*set MICBIAS short current to IRQ */
94 /*( if sticky set regBE : 8800 ) */
95#endif
96
97};
98#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list)
99
100static int rt5640_reg_init(struct snd_soc_codec *codec)
101{
102 int i;
103 for (i = 0; i < RT5640_INIT_REG_LEN; i++)
104 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
105 return 0;
106}
107#endif
108
109static const u16 rt5640_reg[RT5640_VENDOR_ID2 + 1] = {
110 [RT5640_RESET] = 0x000c,
111 [RT5640_SPK_VOL] = 0xc8c8,
112 [RT5640_HP_VOL] = 0xc8c8,
113 [RT5640_OUTPUT] = 0xc8c8,
114 [RT5640_MONO_OUT] = 0x8000,
115 [RT5640_INL_INR_VOL] = 0x0808,
116 [RT5640_DAC1_DIG_VOL] = 0xafaf,
117 [RT5640_DAC2_DIG_VOL] = 0xafaf,
118 [RT5640_ADC_DIG_VOL] = 0x2f2f,
119 [RT5640_ADC_DATA] = 0x2f2f,
120 [RT5640_STO_ADC_MIXER] = 0x7060,
121 [RT5640_MONO_ADC_MIXER] = 0x7070,
122 [RT5640_AD_DA_MIXER] = 0x8080,
123 [RT5640_STO_DAC_MIXER] = 0x5454,
124 [RT5640_MONO_DAC_MIXER] = 0x5454,
125 [RT5640_DIG_MIXER] = 0xaa00,
126 [RT5640_DSP_PATH2] = 0xa000,
127 [RT5640_REC_L2_MIXER] = 0x007f,
128 [RT5640_REC_R2_MIXER] = 0x007f,
129 [RT5640_HPO_MIXER] = 0xe000,
130 [RT5640_SPK_L_MIXER] = 0x003e,
131 [RT5640_SPK_R_MIXER] = 0x003e,
132 [RT5640_SPO_L_MIXER] = 0xf800,
133 [RT5640_SPO_R_MIXER] = 0x3800,
134 [RT5640_SPO_CLSD_RATIO] = 0x0004,
135 [RT5640_MONO_MIXER] = 0xfc00,
136 [RT5640_OUT_L3_MIXER] = 0x01ff,
137 [RT5640_OUT_R3_MIXER] = 0x01ff,
138 [RT5640_LOUT_MIXER] = 0xf000,
139 [RT5640_PWR_ANLG1] = 0x00c0,
140 [RT5640_I2S1_SDP] = 0x8000,
141 [RT5640_I2S2_SDP] = 0x8000,
142 [RT5640_I2S3_SDP] = 0x8000,
143 [RT5640_ADDA_CLK1] = 0x1110,
144 [RT5640_ADDA_CLK2] = 0x0c00,
145 [RT5640_DMIC] = 0x1d00,
146 [RT5640_ASRC_3] = 0x0008,
147 [RT5640_HP_OVCD] = 0x0600,
148 [RT5640_CLS_D_OVCD] = 0x0228,
149 [RT5640_CLS_D_OUT] = 0xa800,
150 [RT5640_DEPOP_M1] = 0x0004,
151 [RT5640_DEPOP_M2] = 0x1100,
152 [RT5640_DEPOP_M3] = 0x0646,
153 [RT5640_CHARGE_PUMP] = 0x0c00,
154 [RT5640_MICBIAS] = 0x3000,
155 [RT5640_EQ_CTRL1] = 0x2080,
156 [RT5640_DRC_AGC_1] = 0x2206,
157 [RT5640_DRC_AGC_2] = 0x1f00,
158 [RT5640_ANC_CTRL1] = 0x034b,
159 [RT5640_ANC_CTRL2] = 0x0066,
160 [RT5640_ANC_CTRL3] = 0x000b,
161 [RT5640_GPIO_CTRL1] = 0x0400,
162 [RT5640_DSP_CTRL3] = 0x2000,
163 [RT5640_BASE_BACK] = 0x0013,
164 [RT5640_MP3_PLUS1] = 0x0680,
165 [RT5640_MP3_PLUS2] = 0x1c17,
166 [RT5640_3D_HP] = 0x8c00,
167 [RT5640_ADJ_HPF] = 0x2a20,
168 [RT5640_HP_CALIB_AMP_DET] = 0x0400,
169 [RT5640_SV_ZCD1] = 0x0809,
170 [RT5640_VENDOR_ID1] = 0x10ec,
171 [RT5640_VENDOR_ID2] = 0x6231,
172};
173
174static int rt5640_reset(struct snd_soc_codec *codec)
175{
176 return snd_soc_write(codec, RT5640_RESET, 0);
177}
178
179/**
180 * rt5640_index_write - Write private register.
181 * @codec: SoC audio codec device.
182 * @reg: Private register index.
183 * @value: Private register Data.
184 *
185 * Modify private register for advanced setting. It can be written through
186 * private index (0x6a) and data (0x6c) register.
187 *
188 * Returns 0 for success or negative error code.
189 */
190static int rt5640_index_write(struct snd_soc_codec *codec,
191 unsigned int reg, unsigned int value)
192{
193 int ret;
194
195 ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
196 if (ret < 0) {
197 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
198 goto err;
199 }
200 ret = snd_soc_write(codec, RT5640_PRIV_DATA, value);
201 if (ret < 0) {
202 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
203 goto err;
204 }
205 return 0;
206
207err:
208 return ret;
209}
210
211/**
212 * rt5640_index_read - Read private register.
213 * @codec: SoC audio codec device.
214 * @reg: Private register index.
215 *
216 * Read advanced setting from private register. It can be read through
217 * private index (0x6a) and data (0x6c) register.
218 *
219 * Returns private register value or negative error code.
220 */
221static unsigned int rt5640_index_read(
222 struct snd_soc_codec *codec, unsigned int reg)
223{
224 int ret;
225
226 ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
227 if (ret < 0) {
228 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
229 return ret;
230 }
231 return snd_soc_read(codec, RT5640_PRIV_DATA);
232}
233
234/**
235 * rt5640_index_update_bits - update private register bits
236 * @codec: audio codec
237 * @reg: Private register index.
238 * @mask: register mask
239 * @value: new value
240 *
241 * Writes new register value.
242 *
243 * Returns 1 for change, 0 for no change, or negative error code.
244 */
245static int rt5640_index_update_bits(struct snd_soc_codec *codec,
246 unsigned int reg, unsigned int mask, unsigned int value)
247{
248 unsigned int old, new;
249 int change, ret;
250
251 ret = rt5640_index_read(codec, reg);
252 if (ret < 0) {
253 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
254 goto err;
255 }
256
257 old = ret;
258 new = (old & ~mask) | (value & mask);
259 change = old != new;
260 if (change) {
261 ret = rt5640_index_write(codec, reg, new);
262 if (ret < 0) {
263 dev_err(codec->dev,
264 "Failed to write private reg: %d\n", ret);
265 goto err;
266 }
267 }
268 return change;
269
270err:
271 return ret;
272}
273
274static int rt5640_volatile_register(
275 struct snd_soc_codec *codec, unsigned int reg)
276{
277 switch (reg) {
278 case RT5640_RESET:
279 case RT5640_PRIV_DATA:
280 case RT5640_ASRC_5:
281 case RT5640_EQ_CTRL1:
282 case RT5640_DRC_AGC_1:
283 case RT5640_ANC_CTRL1:
284 case RT5640_IRQ_CTRL2:
285 case RT5640_INT_IRQ_ST:
286 case RT5640_DSP_CTRL2:
287 case RT5640_DSP_CTRL3:
288 case RT5640_PGM_REG_ARR1:
289 case RT5640_PGM_REG_ARR3:
290 return 1;
291 default:
292 return 0;
293 }
294}
295
296static int rt5640_readable_register(
297 struct snd_soc_codec *codec, unsigned int reg)
298{
299 switch (reg) {
300 case RT5640_RESET:
301 case RT5640_SPK_VOL:
302 case RT5640_HP_VOL:
303 case RT5640_OUTPUT:
304 case RT5640_MONO_OUT:
305 case RT5640_IN1_IN2:
306 case RT5640_IN3_IN4:
307 case RT5640_INL_INR_VOL:
308 case RT5640_DAC1_DIG_VOL:
309 case RT5640_DAC2_DIG_VOL:
310 case RT5640_DAC2_CTRL:
311 case RT5640_ADC_DIG_VOL:
312 case RT5640_ADC_DATA:
313 case RT5640_ADC_BST_VOL:
314 case RT5640_STO_ADC_MIXER:
315 case RT5640_MONO_ADC_MIXER:
316 case RT5640_AD_DA_MIXER:
317 case RT5640_STO_DAC_MIXER:
318 case RT5640_MONO_DAC_MIXER:
319 case RT5640_DIG_MIXER:
320 case RT5640_DSP_PATH1:
321 case RT5640_DSP_PATH2:
322 case RT5640_DIG_INF_DATA:
323 case RT5640_REC_L1_MIXER:
324 case RT5640_REC_L2_MIXER:
325 case RT5640_REC_R1_MIXER:
326 case RT5640_REC_R2_MIXER:
327 case RT5640_HPO_MIXER:
328 case RT5640_SPK_L_MIXER:
329 case RT5640_SPK_R_MIXER:
330 case RT5640_SPO_L_MIXER:
331 case RT5640_SPO_R_MIXER:
332 case RT5640_SPO_CLSD_RATIO:
333 case RT5640_MONO_MIXER:
334 case RT5640_OUT_L1_MIXER:
335 case RT5640_OUT_L2_MIXER:
336 case RT5640_OUT_L3_MIXER:
337 case RT5640_OUT_R1_MIXER:
338 case RT5640_OUT_R2_MIXER:
339 case RT5640_OUT_R3_MIXER:
340 case RT5640_LOUT_MIXER:
341 case RT5640_PWR_DIG1:
342 case RT5640_PWR_DIG2:
343 case RT5640_PWR_ANLG1:
344 case RT5640_PWR_ANLG2:
345 case RT5640_PWR_MIXER:
346 case RT5640_PWR_VOL:
347 case RT5640_PRIV_INDEX:
348 case RT5640_PRIV_DATA:
349 case RT5640_I2S1_SDP:
350 case RT5640_I2S2_SDP:
351 case RT5640_I2S3_SDP:
352 case RT5640_ADDA_CLK1:
353 case RT5640_ADDA_CLK2:
354 case RT5640_DMIC:
355 case RT5640_GLB_CLK:
356 case RT5640_PLL_CTRL1:
357 case RT5640_PLL_CTRL2:
358 case RT5640_ASRC_1:
359 case RT5640_ASRC_2:
360 case RT5640_ASRC_3:
361 case RT5640_ASRC_4:
362 case RT5640_ASRC_5:
363 case RT5640_HP_OVCD:
364 case RT5640_CLS_D_OVCD:
365 case RT5640_CLS_D_OUT:
366 case RT5640_DEPOP_M1:
367 case RT5640_DEPOP_M2:
368 case RT5640_DEPOP_M3:
369 case RT5640_CHARGE_PUMP:
370 case RT5640_PV_DET_SPK_G:
371 case RT5640_MICBIAS:
372 case RT5640_EQ_CTRL1:
373 case RT5640_EQ_CTRL2:
374 case RT5640_WIND_FILTER:
375 case RT5640_DRC_AGC_1:
376 case RT5640_DRC_AGC_2:
377 case RT5640_DRC_AGC_3:
378 case RT5640_SVOL_ZC:
379 case RT5640_ANC_CTRL1:
380 case RT5640_ANC_CTRL2:
381 case RT5640_ANC_CTRL3:
382 case RT5640_JD_CTRL:
383 case RT5640_ANC_JD:
384 case RT5640_IRQ_CTRL1:
385 case RT5640_IRQ_CTRL2:
386 case RT5640_INT_IRQ_ST:
387 case RT5640_GPIO_CTRL1:
388 case RT5640_GPIO_CTRL2:
389 case RT5640_GPIO_CTRL3:
390 case RT5640_DSP_CTRL1:
391 case RT5640_DSP_CTRL2:
392 case RT5640_DSP_CTRL3:
393 case RT5640_DSP_CTRL4:
394 case RT5640_PGM_REG_ARR1:
395 case RT5640_PGM_REG_ARR2:
396 case RT5640_PGM_REG_ARR3:
397 case RT5640_PGM_REG_ARR4:
398 case RT5640_PGM_REG_ARR5:
399 case RT5640_SCB_FUNC:
400 case RT5640_SCB_CTRL:
401 case RT5640_BASE_BACK:
402 case RT5640_MP3_PLUS1:
403 case RT5640_MP3_PLUS2:
404 case RT5640_3D_HP:
405 case RT5640_ADJ_HPF:
406 case RT5640_HP_CALIB_AMP_DET:
407 case RT5640_HP_CALIB2:
408 case RT5640_SV_ZCD1:
409 case RT5640_SV_ZCD2:
410 case RT5640_DUMMY1:
411 case RT5640_DUMMY2:
412 case RT5640_DUMMY3:
413 case RT5640_VENDOR_ID:
414 case RT5640_VENDOR_ID1:
415 case RT5640_VENDOR_ID2:
416 return 1;
417 default:
418 return 0;
419 }
420}
421
422int rt5640_headset_detect(struct snd_soc_codec *codec, int jack_insert)
423{
424 int jack_type;
425
426 if (jack_insert) {
427 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
428 RT5640_PWR_LDO2, RT5640_PWR_LDO2);
429 snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
430 RT5640_PWR_MB1, RT5640_PWR_MB1);
431 snd_soc_update_bits(codec, RT5640_MICBIAS,
432 RT5640_MIC1_OVCD_MASK | RT5640_MIC1_OVTH_MASK |
433 RT5640_PWR_CLK25M_MASK | RT5640_PWR_MB_MASK,
434 RT5640_MIC1_OVCD_EN | RT5640_MIC1_OVTH_600UA |
435 RT5640_PWR_MB_PU | RT5640_PWR_CLK25M_PU);
436 snd_soc_update_bits(codec, RT5640_DUMMY1,
437 0x1, 0x1);
438 msleep(50);
439 if (snd_soc_read(codec, RT5640_IRQ_CTRL2) & 0x8)
440 jack_type = RT5640_HEADPHO_DET;
441 else
442 jack_type = RT5640_HEADSET_DET;
443 snd_soc_update_bits(codec, RT5640_IRQ_CTRL2,
444 RT5640_MB1_OC_CLR, 0);
445 } else {
446 snd_soc_update_bits(codec, RT5640_MICBIAS,
447 RT5640_MIC1_OVCD_MASK,
448 RT5640_MIC1_OVCD_DIS);
449
450 jack_type = RT5640_NO_JACK;
451 }
452
453 return jack_type;
454}
455EXPORT_SYMBOL(rt5640_headset_detect);
456
457static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
458static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
459static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
460static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
461static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
462
463/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
464static unsigned int bst_tlv[] = {
465 TLV_DB_RANGE_HEAD(7),
466 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
467 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
468 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
469 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
470 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
471 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
472 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
473};
474
475static int rt5640_dmic_get(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_value *ucontrol)
477{
478 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
479 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
480
481 ucontrol->value.integer.value[0] = rt5640->dmic_en;
482
483 return 0;
484}
485
486static int rt5640_dmic_put(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
488{
489 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
490 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
491
492 if (rt5640->dmic_en == ucontrol->value.integer.value[0])
493 return 0;
494
495 rt5640->dmic_en = ucontrol->value.integer.value[0];
496 switch (rt5640->dmic_en) {
497 case RT5640_DMIC_DIS:
498 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
499 RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK |
500 RT5640_GP4_PIN_MASK,
501 RT5640_GP2_PIN_GPIO2 | RT5640_GP3_PIN_GPIO3 |
502 RT5640_GP4_PIN_GPIO4);
503 snd_soc_update_bits(codec, RT5640_DMIC,
504 RT5640_DMIC_1_DP_MASK | RT5640_DMIC_2_DP_MASK,
505 RT5640_DMIC_1_DP_GPIO3 | RT5640_DMIC_2_DP_GPIO4);
506 snd_soc_update_bits(codec, RT5640_DMIC,
507 RT5640_DMIC_1_EN_MASK | RT5640_DMIC_2_EN_MASK,
508 RT5640_DMIC_1_DIS | RT5640_DMIC_2_DIS);
509 break;
510
511 case RT5640_DMIC1:
512 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
513 RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK,
514 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP3_PIN_DMIC1_SDA);
515 snd_soc_update_bits(codec, RT5640_DMIC,
516 RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK |
517 RT5640_DMIC_1_DP_MASK,
518 RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING |
519 RT5640_DMIC_1_DP_IN1P);
520 snd_soc_update_bits(codec, RT5640_DMIC,
521 RT5640_DMIC_1_EN_MASK, RT5640_DMIC_1_EN);
522 break;
523
524 case RT5640_DMIC2:
525 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
526 RT5640_GP2_PIN_MASK | RT5640_GP4_PIN_MASK,
527 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP4_PIN_DMIC2_SDA);
528 snd_soc_update_bits(codec, RT5640_DMIC,
529 RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK |
530 RT5640_DMIC_2_DP_MASK,
531 RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING |
532 RT5640_DMIC_2_DP_IN1N);
533 snd_soc_update_bits(codec, RT5640_DMIC,
534 RT5640_DMIC_2_EN_MASK, RT5640_DMIC_2_EN);
535 break;
536
537 default:
538 return -EINVAL;
539 }
540
541 return 0;
542}
543
544
545/* IN1/IN2 Input Type */
546static const char *rt5640_input_mode[] = {
547 "Single ended", "Differential"};
548
549static const SOC_ENUM_SINGLE_DECL(
550 rt5640_in1_mode_enum, RT5640_IN1_IN2,
551 RT5640_IN_SFT1, rt5640_input_mode);
552
553static const SOC_ENUM_SINGLE_DECL(
554 rt5640_in2_mode_enum, RT5640_IN3_IN4,
555 RT5640_IN_SFT2, rt5640_input_mode);
556
557/* Interface data select */
558static const char *rt5640_data_select[] = {
559 "Normal", "left copy to right", "right copy to left", "Swap"};
560
561static const SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
562 RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
563
564static const SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
565 RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
566
567static const SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
568 RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
569
570static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
571 RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
572
573static const SOC_ENUM_SINGLE_DECL(rt5640_if3_dac_enum, RT5640_DIG_INF_DATA,
574 RT5640_IF3_DAC_SEL_SFT, rt5640_data_select);
575
576static const SOC_ENUM_SINGLE_DECL(rt5640_if3_adc_enum, RT5640_DIG_INF_DATA,
577 RT5640_IF3_ADC_SEL_SFT, rt5640_data_select);
578
579/* Class D speaker gain ratio */
580static const char *rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
581 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
582
583static const SOC_ENUM_SINGLE_DECL(
584 rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
585 RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
586
587/* DMIC */
588static const char *rt5640_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
589
590static const SOC_ENUM_SINGLE_DECL(rt5640_dmic_enum, 0, 0, rt5640_dmic_mode);
591
592
593
594#ifdef RT5640_REG_RW
595#define REGVAL_MAX 0xffff
596static unsigned int regctl_addr;
597static int rt5640_regctl_info(struct snd_kcontrol *kcontrol,
598 struct snd_ctl_elem_info *uinfo) {
599 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
600 uinfo->count = 2;
601 uinfo->value.integer.min = 0;
602 uinfo->value.integer.max = REGVAL_MAX;
603 return 0;
604}
605
606static int rt5640_regctl_get(struct snd_kcontrol *kcontrol,
607 struct snd_ctl_elem_value *ucontrol)
608{
609 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
610 ucontrol->value.integer.value[0] = regctl_addr;
611 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
612 return 0;
613}
614
615static int rt5640_regctl_put(struct snd_kcontrol *kcontrol,
616 struct snd_ctl_elem_value *ucontrol)
617{
618 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
619 regctl_addr = ucontrol->value.integer.value[0];
620 if (ucontrol->value.integer.value[1] <= REGVAL_MAX)
621 snd_soc_write(codec, regctl_addr,
622 ucontrol->value.integer.value[1]);
623 return 0;
624}
625#endif
626
627
628#define VOL_RESCALE_MAX_VOL 0x27 /* 39 */
629#define VOL_RESCALE_MIX_RANGE 0x1F /* 31 */
630
631static int rt5640_vol_rescale_get(struct snd_kcontrol *kcontrol,
632 struct snd_ctl_elem_value *ucontrol)
633{
634 struct soc_mixer_control *mc =
635 (struct soc_mixer_control *)kcontrol->private_value;
636 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
637 unsigned int val = snd_soc_read(codec, mc->reg);
638
639 ucontrol->value.integer.value[0] = VOL_RESCALE_MAX_VOL -
640 ((val & RT5640_L_VOL_MASK) >> mc->shift);
641 ucontrol->value.integer.value[1] = VOL_RESCALE_MAX_VOL -
642 (val & RT5640_R_VOL_MASK);
643
644 return 0;
645}
646
647static int rt5640_vol_rescale_put(struct snd_kcontrol *kcontrol,
648 struct snd_ctl_elem_value *ucontrol)
649{
650 struct soc_mixer_control *mc =
651 (struct soc_mixer_control *)kcontrol->private_value;
652 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
653 unsigned int val, val2;
654
655 val = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[0];
656 val2 = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[1];
657 return snd_soc_update_bits_locked(codec, mc->reg, RT5640_L_VOL_MASK |
658 RT5640_R_VOL_MASK, val << mc->shift | val2);
659}
660
661
662static const struct snd_kcontrol_new rt5640_snd_controls[] = {
663 /* Speaker Output Volume */
664 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
665 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
666 rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
667
668 /* Headphone Output Volume */
669 SOC_DOUBLE("HP Playback Switch", RT5640_HP_VOL,
670 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
671
672 SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT5640_HP_VOL,
673 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
674 rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
675
676 /* OUTPUT Control */
677 SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
678 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
679 SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
680 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
681 SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
682 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
683 /* MONO Output Control */
684 SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT,
685 RT5640_L_MUTE_SFT, 1, 1),
686 /* DAC Digital Volume */
687 SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
688 RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
689 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
690 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
691 175, 0, dac_vol_tlv),
692 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
693 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
694 175, 0, dac_vol_tlv),
695 /* IN1/IN2 Control */
696 SOC_ENUM("IN1 Mode Control", rt5640_in1_mode_enum),
697 SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
698 RT5640_BST_SFT1, 8, 0, bst_tlv),
699 SOC_ENUM("IN2 Mode Control", rt5640_in2_mode_enum),
700 SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
701 RT5640_BST_SFT2, 8, 0, bst_tlv),
702 /* INL/INR Volume Control */
703 SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
704 RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
705 31, 1, in_vol_tlv),
706 /* ADC Digital Volume Control */
707 SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
708 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
709 SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
710 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
711 127, 0, adc_vol_tlv),
712 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
713 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
714 127, 0, adc_vol_tlv),
715 /* ADC Boost Volume Control */
716 SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
717 RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
718 3, 0, adc_bst_tlv),
719 /* Class D speaker gain ratio */
720 SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
721 /* DMIC */
722 SOC_ENUM_EXT("DMIC Switch", rt5640_dmic_enum,
723 rt5640_dmic_get, rt5640_dmic_put),
724
725#ifdef RT5640_REG_RW
726 {
727 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
728 .name = "Register Control",
729 .info = rt5640_regctl_info,
730 .get = rt5640_regctl_get,
731 .put = rt5640_regctl_put,
732 },
733#endif
734};
735
736/**
737 * set_dmic_clk - Set parameter of dmic.
738 *
739 * @w: DAPM widget.
740 * @kcontrol: The kcontrol of this widget.
741 * @event: Event id.
742 *
743 * Choose dmic clock between 1MHz and 3MHz.
744 * It is better for clock to approximate 3MHz.
745 */
746static int set_dmic_clk(struct snd_soc_dapm_widget *w,
747 struct snd_kcontrol *kcontrol, int event)
748{
749 struct snd_soc_codec *codec = w->codec;
750 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
751 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
752
753 rate = rt5640->lrck[rt5640->aif_pu] << 8;
754 red = 3000000 * 12;
755 for (i = 0; i < ARRAY_SIZE(div); i++) {
756 bound = div[i] * 3000000;
757 if (rate > bound)
758 continue;
759 temp = bound - rate;
760 if (temp < red) {
761 red = temp;
762 idx = i;
763 }
764 }
765 if (idx < 0)
766 dev_err(codec->dev, "Failed to set DMIC clock\n");
767 else
768 snd_soc_update_bits(codec, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
769 idx << RT5640_DMIC_CLK_SFT);
770 return idx;
771}
772
773static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
774 struct snd_soc_dapm_widget *sink)
775{
776 unsigned int val;
777
778 val = snd_soc_read(source->codec, RT5640_GLB_CLK);
779 val &= RT5640_SCLK_SRC_MASK;
780 if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T)
781 return 1;
782 else
783 return 0;
784}
785
786/* Digital Mixer */
787static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
788 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
789 RT5640_M_ADC_L1_SFT, 1, 1),
790 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
791 RT5640_M_ADC_L2_SFT, 1, 1),
792};
793
794static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
795 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
796 RT5640_M_ADC_R1_SFT, 1, 1),
797 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
798 RT5640_M_ADC_R2_SFT, 1, 1),
799};
800
801static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
802 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
803 RT5640_M_MONO_ADC_L1_SFT, 1, 1),
804 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
805 RT5640_M_MONO_ADC_L2_SFT, 1, 1),
806};
807
808static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
809 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
810 RT5640_M_MONO_ADC_R1_SFT, 1, 1),
811 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
812 RT5640_M_MONO_ADC_R2_SFT, 1, 1),
813};
814
815static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
816 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
817 RT5640_M_ADCMIX_L_SFT, 1, 1),
818 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
819 RT5640_M_IF1_DAC_L_SFT, 1, 1),
820};
821
822static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
823 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
824 RT5640_M_ADCMIX_R_SFT, 1, 1),
825 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
826 RT5640_M_IF1_DAC_R_SFT, 1, 1),
827};
828
829static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
830 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
831 RT5640_M_DAC_L1_SFT, 1, 1),
832 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
833 RT5640_M_DAC_L2_SFT, 1, 1),
834 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
835 RT5640_M_ANC_DAC_L_SFT, 1, 1),
836};
837
838static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
839 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
840 RT5640_M_DAC_R1_SFT, 1, 1),
841 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
842 RT5640_M_DAC_R2_SFT, 1, 1),
843 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
844 RT5640_M_ANC_DAC_R_SFT, 1, 1),
845};
846
847static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
848 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
849 RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
850 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
851 RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
852 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
853 RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
854};
855
856static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
857 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
858 RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
859 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
860 RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
861 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
862 RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
863};
864
865static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
866 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
867 RT5640_M_STO_L_DAC_L_SFT, 1, 1),
868 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
869 RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
870};
871
872static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
873 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
874 RT5640_M_STO_R_DAC_R_SFT, 1, 1),
875 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
876 RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
877};
878
879/* Analog Input Mixer */
880static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
881 SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
882 RT5640_M_HP_L_RM_L_SFT, 1, 1),
883 SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
884 RT5640_M_IN_L_RM_L_SFT, 1, 1),
885 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
886 RT5640_M_BST4_RM_L_SFT, 1, 1),
887 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
888 RT5640_M_BST1_RM_L_SFT, 1, 1),
889 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
890 RT5640_M_OM_L_RM_L_SFT, 1, 1),
891};
892
893static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
894 SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
895 RT5640_M_HP_R_RM_R_SFT, 1, 1),
896 SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
897 RT5640_M_IN_R_RM_R_SFT, 1, 1),
898 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
899 RT5640_M_BST4_RM_R_SFT, 1, 1),
900 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
901 RT5640_M_BST1_RM_R_SFT, 1, 1),
902 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
903 RT5640_M_OM_R_RM_R_SFT, 1, 1),
904};
905
906/* Analog Output Mixer */
907static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
908 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
909 RT5640_M_RM_L_SM_L_SFT, 1, 1),
910 SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
911 RT5640_M_IN_L_SM_L_SFT, 1, 1),
912 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
913 RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
914 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
915 RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
916 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
917 RT5640_M_OM_L_SM_L_SFT, 1, 1),
918};
919
920static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
921 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
922 RT5640_M_RM_R_SM_R_SFT, 1, 1),
923 SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
924 RT5640_M_IN_R_SM_R_SFT, 1, 1),
925 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
926 RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
927 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
928 RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
929 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
930 RT5640_M_OM_R_SM_R_SFT, 1, 1),
931};
932
933static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
934 SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
935 RT5640_M_SM_L_OM_L_SFT, 1, 1),
936 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
937 RT5640_M_BST1_OM_L_SFT, 1, 1),
938 SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
939 RT5640_M_IN_L_OM_L_SFT, 1, 1),
940 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
941 RT5640_M_RM_L_OM_L_SFT, 1, 1),
942 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
943 RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
944 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
945 RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
946 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
947 RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
948};
949
950static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
951 SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
952 RT5640_M_SM_L_OM_R_SFT, 1, 1),
953 SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
954 RT5640_M_BST4_OM_R_SFT, 1, 1),
955 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
956 RT5640_M_BST1_OM_R_SFT, 1, 1),
957 SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
958 RT5640_M_IN_R_OM_R_SFT, 1, 1),
959 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
960 RT5640_M_RM_R_OM_R_SFT, 1, 1),
961 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
962 RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
963 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
964 RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
965 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
966 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
967};
968
969static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
970 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
971 RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
972 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
973 RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
974 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
975 RT5640_M_SV_R_SPM_L_SFT, 1, 1),
976 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
977 RT5640_M_SV_L_SPM_L_SFT, 1, 1),
978 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
979 RT5640_M_BST1_SPM_L_SFT, 1, 1),
980};
981
982static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
983 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
984 RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
985 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
986 RT5640_M_SV_R_SPM_R_SFT, 1, 1),
987 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
988 RT5640_M_BST1_SPM_R_SFT, 1, 1),
989};
990
991static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
992 SOC_DAPM_SINGLE("DAC2 Switch", RT5640_HPO_MIXER,
993 RT5640_M_DAC2_HM_SFT, 1, 1),
994 SOC_DAPM_SINGLE("DAC1 Switch", RT5640_HPO_MIXER,
995 RT5640_M_DAC1_HM_SFT, 1, 1),
996 SOC_DAPM_SINGLE("HPVOL Switch", RT5640_HPO_MIXER,
997 RT5640_M_HPVOL_HM_SFT, 1, 1),
998};
999
1000static const struct snd_kcontrol_new rt5640_lout_mix[] = {
1001 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
1002 RT5640_M_DAC_L1_LM_SFT, 1, 1),
1003 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
1004 RT5640_M_DAC_R1_LM_SFT, 1, 1),
1005 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
1006 RT5640_M_OV_L_LM_SFT, 1, 1),
1007 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
1008 RT5640_M_OV_R_LM_SFT, 1, 1),
1009};
1010
1011static const struct snd_kcontrol_new rt5640_mono_mix[] = {
1012 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
1013 RT5640_M_DAC_R2_MM_SFT, 1, 1),
1014 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
1015 RT5640_M_DAC_L2_MM_SFT, 1, 1),
1016 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
1017 RT5640_M_OV_R_MM_SFT, 1, 1),
1018 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
1019 RT5640_M_OV_L_MM_SFT, 1, 1),
1020 SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
1021 RT5640_M_BST1_MM_SFT, 1, 1),
1022};
1023
1024/* INL/R source */
1025static const char *rt5640_inl_src[] = {"IN2P", "MonoP"};
1026
1027static const SOC_ENUM_SINGLE_DECL(
1028 rt5640_inl_enum, RT5640_INL_INR_VOL,
1029 RT5640_INL_SEL_SFT, rt5640_inl_src);
1030
1031static const struct snd_kcontrol_new rt5640_inl_mux =
1032 SOC_DAPM_ENUM("INL source", rt5640_inl_enum);
1033
1034static const char *rt5640_inr_src[] = {"IN2N", "MonoN"};
1035
1036static const SOC_ENUM_SINGLE_DECL(
1037 rt5640_inr_enum, RT5640_INL_INR_VOL,
1038 RT5640_INR_SEL_SFT, rt5640_inr_src);
1039
1040static const struct snd_kcontrol_new rt5640_inr_mux =
1041 SOC_DAPM_ENUM("INR source", rt5640_inr_enum);
1042
1043/* Stereo ADC source */
1044static const char *rt5640_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1045
1046static const SOC_ENUM_SINGLE_DECL(
1047 rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
1048 RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
1049
1050static const struct snd_kcontrol_new rt5640_sto_adc_l1_mux =
1051 SOC_DAPM_ENUM("Stereo ADC L1 source", rt5640_stereo_adc1_enum);
1052
1053static const struct snd_kcontrol_new rt5640_sto_adc_r1_mux =
1054 SOC_DAPM_ENUM("Stereo ADC R1 source", rt5640_stereo_adc1_enum);
1055
1056static const char *rt5640_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1057
1058static const SOC_ENUM_SINGLE_DECL(
1059 rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
1060 RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
1061
1062static const struct snd_kcontrol_new rt5640_sto_adc_l2_mux =
1063 SOC_DAPM_ENUM("Stereo ADC L2 source", rt5640_stereo_adc2_enum);
1064
1065static const struct snd_kcontrol_new rt5640_sto_adc_r2_mux =
1066 SOC_DAPM_ENUM("Stereo ADC R2 source", rt5640_stereo_adc2_enum);
1067
1068/* Mono ADC source */
1069static const char *rt5640_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1070
1071static const SOC_ENUM_SINGLE_DECL(
1072 rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
1073 RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
1074
1075static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
1076 SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
1077
1078static const char *rt5640_mono_adc_l2_src[] = {
1079 "DMIC L1", "DMIC L2", "Mono DAC MIXL"
1080};
1081
1082static const SOC_ENUM_SINGLE_DECL(
1083 rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
1084 RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
1085
1086static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
1087 SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
1088
1089static const char *rt5640_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1090
1091static const SOC_ENUM_SINGLE_DECL(
1092 rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
1093 RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
1094
1095static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
1096 SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
1097
1098static const char *rt5640_mono_adc_r2_src[] = {
1099 "DMIC R1", "DMIC R2", "Mono DAC MIXR"
1100};
1101
1102static const SOC_ENUM_SINGLE_DECL(
1103 rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
1104 RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
1105
1106static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
1107 SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
1108
1109/* DAC2 channel source */
1110static const char *rt5640_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1111
1112static const SOC_ENUM_SINGLE_DECL(rt5640_dac_l2_enum, RT5640_DSP_PATH2,
1113 RT5640_DAC_L2_SEL_SFT, rt5640_dac_l2_src);
1114
1115static const struct snd_kcontrol_new rt5640_dac_l2_mux =
1116 SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
1117
1118static const char *rt5640_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1119
1120static const SOC_ENUM_SINGLE_DECL(
1121 rt5640_dac_r2_enum, RT5640_DSP_PATH2,
1122 RT5640_DAC_R2_SEL_SFT, rt5640_dac_r2_src);
1123
1124static const struct snd_kcontrol_new rt5640_dac_r2_mux =
1125 SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
1126
1127/* Interface 2 ADC channel source */
1128static const char *rt5640_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1129
1130static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_l_enum, RT5640_DSP_PATH2,
1131 RT5640_IF2_ADC_L_SEL_SFT, rt5640_if2_adc_l_src);
1132
1133static const struct snd_kcontrol_new rt5640_if2_adc_l_mux =
1134 SOC_DAPM_ENUM("IF2 ADC left channel source", rt5640_if2_adc_l_enum);
1135
1136static const char *rt5640_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1137
1138static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_r_enum, RT5640_DSP_PATH2,
1139 RT5640_IF2_ADC_R_SEL_SFT, rt5640_if2_adc_r_src);
1140
1141static const struct snd_kcontrol_new rt5640_if2_adc_r_mux =
1142 SOC_DAPM_ENUM("IF2 ADC right channel source", rt5640_if2_adc_r_enum);
1143
1144/* digital interface and iis interface map */
1145static const char *rt5640_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1146 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1147 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1148
1149static const SOC_ENUM_SINGLE_DECL(
1150 rt5640_dai_iis_map_enum, RT5640_I2S1_SDP,
1151 RT5640_I2S_IF_SFT, rt5640_dai_iis_map);
1152
1153static const struct snd_kcontrol_new rt5640_dai_mux =
1154 SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
1155
1156/* SDI select */
1157static const char *rt5640_sdi_sel[] = {"IF1", "IF2"};
1158
1159static const SOC_ENUM_SINGLE_DECL(
1160 rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
1161 RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
1162
1163static const struct snd_kcontrol_new rt5640_sdi_mux =
1164 SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
1165
1166static int spk_event(struct snd_soc_dapm_widget *w,
1167 struct snd_kcontrol *kcontrol, int event)
1168{
1169 struct snd_soc_codec *codec = w->codec;
1170 static unsigned int spkl_out_enable;
1171 static unsigned int spkr_out_enable;
1172
1173 switch (event) {
1174 case SND_SOC_DAPM_POST_PMU:
1175 pr_info("spk_event --SND_SOC_DAPM_POST_PMU\n");
1176 snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0001);
1177 rt5640_index_update_bits(codec, 0x1c, 0xf000, 0xf000);
1178 /* rt5640_index_write(codec, 0x1c, 0xfd21); */
1179 break;
1180
1181 case SND_SOC_DAPM_PRE_PMD:
1182 pr_info("spk_event --SND_SOC_DAPM_POST_PMD\n");
1183 /* rt5640_index_write(codec, 0x1c, 0xfd00); */
1184 rt5640_index_update_bits(codec, 0x1c, 0xf000, 0x0000);
1185 snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0000);
1186 break;
1187
1188 default:
1189 return 0;
1190 }
1191 return 0;
1192}
1193
1194static int hp_event(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
1196{
1197 struct snd_soc_codec *codec = w->codec;
1198 static unsigned int hp_out_enable;
1199
1200 switch (event) {
1201 case SND_SOC_DAPM_POST_PMU:
1202 pr_info("hp_event --SND_SOC_DAPM_POST_PMU\n");
1203 break;
1204
1205 case SND_SOC_DAPM_PRE_PMD:
1206 pr_info("hp_event --SND_SOC_DAPM_POST_PMD\n");
1207 break;
1208
1209 default:
1210 return 0;
1211 }
1212 return 0;
1213}
1214
1215static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1216 SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2,
1217 RT5640_PWR_PLL_BIT, 0, NULL, 0),
1218 /* Input Side */
1219 /* micbias */
1220 SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
1221 RT5640_PWR_LDO2_BIT, 0, NULL, 0),
1222 SND_SOC_DAPM_MICBIAS("micbias1", RT5640_PWR_ANLG2,
1223 RT5640_PWR_MB1_BIT, 0),
1224 SND_SOC_DAPM_MICBIAS("micbias2", RT5640_PWR_ANLG2,
1225 RT5640_PWR_MB2_BIT, 0),
1226 /* Input Lines */
1227
1228 SND_SOC_DAPM_INPUT("MIC1"),
1229 SND_SOC_DAPM_INPUT("MIC2"),
1230 SND_SOC_DAPM_INPUT("DMIC1"),
1231 SND_SOC_DAPM_INPUT("DMIC2"),
1232 SND_SOC_DAPM_INPUT("IN1P"),
1233 SND_SOC_DAPM_INPUT("IN1N"),
1234 SND_SOC_DAPM_INPUT("IN2P"),
1235 SND_SOC_DAPM_INPUT("IN2N"),
1236 SND_SOC_DAPM_INPUT("DMIC L1"),
1237 SND_SOC_DAPM_INPUT("DMIC R1"),
1238 SND_SOC_DAPM_INPUT("DMIC L2"),
1239 SND_SOC_DAPM_INPUT("DMIC R2"),
1240 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1241 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1242 /* Boost */
1243 SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
1244 RT5640_PWR_BST1_BIT, 0, NULL, 0),
1245 SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
1246 RT5640_PWR_BST4_BIT, 0, NULL, 0),
1247 /* Input Volume */
1248 SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
1249 RT5640_PWR_IN_L_BIT, 0, NULL, 0),
1250 SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
1251 RT5640_PWR_IN_R_BIT, 0, NULL, 0),
1252 /* IN Mux */
1253 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5640_inl_mux),
1254 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5640_inr_mux),
1255 /* REC Mixer */
1256 SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
1257 rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
1258 SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
1259 rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
1260 /* ADCs */
1261 SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
1262 RT5640_PWR_ADC_L_BIT, 0),
1263 SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
1264 RT5640_PWR_ADC_R_BIT, 0),
1265 /* ADC Mux */
1266 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1267 &rt5640_sto_adc_l2_mux),
1268 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1269 &rt5640_sto_adc_r2_mux),
1270 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1271 &rt5640_sto_adc_l1_mux),
1272 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1273 &rt5640_sto_adc_r1_mux),
1274 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1275 &rt5640_mono_adc_l2_mux),
1276 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1277 &rt5640_mono_adc_l1_mux),
1278 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1279 &rt5640_mono_adc_r1_mux),
1280 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1281 &rt5640_mono_adc_r2_mux),
1282 /* ADC Mixer */
1283 SND_SOC_DAPM_SUPPLY("stereo filter", RT5640_PWR_DIG2,
1284 RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
1285 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1286 rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
1287 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1288 rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
1289 SND_SOC_DAPM_SUPPLY("mono left filter", RT5640_PWR_DIG2,
1290 RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1291 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1292 rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
1293 SND_SOC_DAPM_SUPPLY("mono right filter", RT5640_PWR_DIG2,
1294 RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1295 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1296 rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
1297
1298 /* IF2 Mux */
1299 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
1300 &rt5640_if2_adc_l_mux),
1301 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
1302 &rt5640_if2_adc_r_mux),
1303
1304 /* Digital Interface */
1305 SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
1306 RT5640_PWR_I2S1_BIT, 0, NULL, 0),
1307 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1308 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1309 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1310 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1311 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1312 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1313 SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
1314 RT5640_PWR_I2S2_BIT, 0, NULL, 0),
1315 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1316 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1317 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1318 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1319 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1320 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1321 SND_SOC_DAPM_SUPPLY("I2S3", RT5640_PWR_DIG1,
1322 RT5640_PWR_I2S3_BIT, 0, NULL, 0),
1323 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1324 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1325 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1326 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1327 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1328 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1329
1330 /* Digital Interface Select */
1331 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1332 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1333 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1334 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1335 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1336
1337 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1338 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1339 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1340 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1341 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1342
1343 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1344 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1345
1346 /* Audio Interface */
1347 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1348 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1349 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1350 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1351 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1352 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1353
1354 /* Audio DSP */
1355 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1356
1357 /* ANC */
1358 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1359
1360 /* Output Side */
1361 /* DAC mixer before sound effect */
1362 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1363 rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
1364 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1365 rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
1366
1367 /* DAC2 channel Mux */
1368 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1369 &rt5640_dac_l2_mux),
1370 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1371 &rt5640_dac_r2_mux),
1372
1373 /* DAC Mixer */
1374 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1375 rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1376 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1377 rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1378 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1379 rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
1380 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1381 rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
1382 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
1383 rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
1384 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
1385 rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
1386 /* DACs */
1387 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1,
1388 RT5640_PWR_DAC_L1_BIT, 0),
1389 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1,
1390 RT5640_PWR_DAC_L2_BIT, 0),
1391 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
1392 RT5640_PWR_DAC_R1_BIT, 0),
1393 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1,
1394 RT5640_PWR_DAC_R2_BIT, 0),
1395 /* SPK/OUT Mixer */
1396 SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
1397 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
1398 SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
1399 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
1400 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1401 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1402 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1403 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1404 /* Ouput Volume */
1405 SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
1406 RT5640_PWR_SV_L_BIT, 0, NULL, 0),
1407 SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
1408 RT5640_PWR_SV_R_BIT, 0, NULL, 0),
1409 SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
1410 RT5640_PWR_OV_L_BIT, 0, NULL, 0),
1411 SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
1412 RT5640_PWR_OV_R_BIT, 0, NULL, 0),
1413 SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
1414 RT5640_PWR_HV_L_BIT, 0, NULL, 0),
1415 SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
1416 RT5640_PWR_HV_R_BIT, 0, NULL, 0),
1417 /* SPO/HPO/LOUT/Mono Mixer */
1418 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
1419 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
1420 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1421 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
1422
1423 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1424 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1425 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1426 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1427 SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0,
1428 rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
1429 SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1430 rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1431
1432 SND_SOC_DAPM_SUPPLY("Improve mono amp drv", RT5640_PWR_ANLG1,
1433 RT5640_PWR_MA_BIT, 0, NULL, 0),
1434
1435 SND_SOC_DAPM_SUPPLY("Improve HP amp drv", RT5640_PWR_ANLG1,
1436 SND_SOC_NOPM, 0, hp_event, SND_SOC_DAPM_PRE_PMD |
1437 SND_SOC_DAPM_POST_PMU),
1438
1439 SND_SOC_DAPM_PGA("HP L amp", RT5640_PWR_ANLG1,
1440 RT5640_PWR_HP_L_BIT, 0, NULL, 0),
1441
1442 SND_SOC_DAPM_PGA("HP R amp", RT5640_PWR_ANLG1,
1443 RT5640_PWR_HP_R_BIT, 0, NULL, 0),
1444
1445 SND_SOC_DAPM_SUPPLY("Improve SPK amp drv", RT5640_PWR_DIG1,
1446 SND_SOC_NOPM, 0, spk_event,
1447 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1448
1449 /* Output Lines */
1450 SND_SOC_DAPM_OUTPUT("SPOLP"),
1451 SND_SOC_DAPM_OUTPUT("SPOLN"),
1452 SND_SOC_DAPM_OUTPUT("SPORP"),
1453 SND_SOC_DAPM_OUTPUT("SPORN"),
1454 SND_SOC_DAPM_OUTPUT("HPOL"),
1455 SND_SOC_DAPM_OUTPUT("HPOR"),
1456 SND_SOC_DAPM_OUTPUT("LOUTL"),
1457 SND_SOC_DAPM_OUTPUT("LOUTR"),
1458 SND_SOC_DAPM_OUTPUT("MonoP"),
1459 SND_SOC_DAPM_OUTPUT("MonoN"),
1460};
1461
1462static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1463 {"IN1P", NULL, "LDO2"},
1464 {"IN2P", NULL, "LDO2"},
1465
1466 {"IN1P", NULL, "MIC1"},
1467 {"IN1N", NULL, "MIC1"},
1468 {"IN2P", NULL, "MIC2"},
1469 {"IN2N", NULL, "MIC2"},
1470
1471 {"DMIC L1", NULL, "DMIC1"},
1472 {"DMIC R1", NULL, "DMIC1"},
1473 {"DMIC L2", NULL, "DMIC2"},
1474 {"DMIC R2", NULL, "DMIC2"},
1475
1476 {"BST1", NULL, "IN1P"},
1477 {"BST1", NULL, "IN1N"},
1478 {"BST2", NULL, "IN2P"},
1479 {"BST2", NULL, "IN2N"},
1480
1481 {"INL VOL", NULL, "IN2P"},
1482 {"INR VOL", NULL, "IN2N"},
1483
1484 {"RECMIXL", "HPOL Switch", "HPOL"},
1485 {"RECMIXL", "INL Switch", "INL VOL"},
1486 {"RECMIXL", "BST2 Switch", "BST2"},
1487 {"RECMIXL", "BST1 Switch", "BST1"},
1488 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
1489
1490 {"RECMIXR", "HPOR Switch", "HPOR"},
1491 {"RECMIXR", "INR Switch", "INR VOL"},
1492 {"RECMIXR", "BST2 Switch", "BST2"},
1493 {"RECMIXR", "BST1 Switch", "BST1"},
1494 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
1495
1496 {"ADC L", NULL, "RECMIXL"},
1497 {"ADC R", NULL, "RECMIXR"},
1498
1499 {"DMIC L1", NULL, "DMIC CLK"},
1500 {"DMIC L2", NULL, "DMIC CLK"},
1501
1502 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1503 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1504 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1505 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
1506 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
1507
1508 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1509 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1510 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1511 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1512 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1513
1514 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1515 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1516 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1517 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1518 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
1519
1520 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1521 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1522 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1523 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1524 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1525
1526 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1527 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1528 {"Stereo ADC MIXL", NULL, "stereo filter"},
1529 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
1530
1531 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1532 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1533 {"Stereo ADC MIXR", NULL, "stereo filter"},
1534 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
1535
1536 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1537 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1538 {"Mono ADC MIXL", NULL, "mono left filter"},
1539 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
1540
1541 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1542 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1543 {"Mono ADC MIXR", NULL, "mono right filter"},
1544 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
1545
1546 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
1547 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
1548
1549 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
1550 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
1551 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
1552 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
1553 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
1554 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
1555
1556 {"IF1 ADC", NULL, "I2S1"},
1557 {"IF1 ADC", NULL, "IF1 ADC L"},
1558 {"IF1 ADC", NULL, "IF1 ADC R"},
1559 {"IF2 ADC", NULL, "I2S2"},
1560 {"IF2 ADC", NULL, "IF2 ADC L"},
1561 {"IF2 ADC", NULL, "IF2 ADC R"},
1562 {"IF3 ADC", NULL, "I2S3"},
1563 {"IF3 ADC", NULL, "IF3 ADC L"},
1564 {"IF3 ADC", NULL, "IF3 ADC R"},
1565
1566 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
1567 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
1568 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
1569 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
1570 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
1571 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
1572 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
1573 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
1574 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
1575 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
1576
1577 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
1578 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
1579 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
1580 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
1581 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
1582 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
1583 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
1584 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
1585 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
1586 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
1587
1588 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
1589 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
1590 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
1591 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
1592 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
1593 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
1594 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
1595 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
1596
1597 {"AIF1TX", NULL, "DAI1 TX Mux"},
1598 {"AIF1TX", NULL, "SDI1 TX Mux"},
1599 {"AIF2TX", NULL, "DAI2 TX Mux"},
1600 {"AIF2TX", NULL, "SDI2 TX Mux"},
1601 {"AIF3TX", NULL, "DAI3 TX Mux"},
1602
1603 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
1604 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
1605 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
1606 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
1607 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
1608 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
1609 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
1610 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
1611
1612 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
1613 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
1614 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
1615 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
1616 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
1617 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
1618 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
1619 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
1620
1621 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
1622 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
1623 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
1624 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
1625 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
1626 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
1627 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
1628 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
1629
1630 {"IF1 DAC", NULL, "I2S1"},
1631 {"IF1 DAC", NULL, "DAI1 RX Mux"},
1632 {"IF2 DAC", NULL, "I2S2"},
1633 {"IF2 DAC", NULL, "DAI2 RX Mux"},
1634 {"IF3 DAC", NULL, "I2S3"},
1635 {"IF3 DAC", NULL, "DAI3 RX Mux"},
1636
1637 {"IF1 DAC L", NULL, "IF1 DAC"},
1638 {"IF1 DAC R", NULL, "IF1 DAC"},
1639 {"IF2 DAC L", NULL, "IF2 DAC"},
1640 {"IF2 DAC R", NULL, "IF2 DAC"},
1641 {"IF3 DAC L", NULL, "IF3 DAC"},
1642 {"IF3 DAC R", NULL, "IF3 DAC"},
1643
1644 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
1645 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
1646 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1647 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
1648
1649 {"ANC", NULL, "Stereo ADC MIXL"},
1650 {"ANC", NULL, "Stereo ADC MIXR"},
1651
1652 {"Audio DSP", NULL, "DAC MIXL"},
1653 {"Audio DSP", NULL, "DAC MIXR"},
1654
1655 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1656 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
1657 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1658
1659 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1660 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
1661
1662 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1663 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1664 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1665 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1666 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1667 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1668
1669 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1670 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1671 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1672 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1673 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1674 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1675
1676 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
1677 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1678 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1679 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1680
1681 {"DAC L1", NULL, "Stereo DAC MIXL"},
1682 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
1683 {"DAC R1", NULL, "Stereo DAC MIXR"},
1684 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
1685 {"DAC L2", NULL, "Mono DAC MIXL"},
1686 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
1687 {"DAC R2", NULL, "Mono DAC MIXR"},
1688 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
1689
1690 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1691 {"SPK MIXL", "INL Switch", "INL VOL"},
1692 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
1693 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1694 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1695 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1696 {"SPK MIXR", "INR Switch", "INR VOL"},
1697 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1698 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1699 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1700
1701 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1702 {"OUT MIXL", "BST1 Switch", "BST1"},
1703 {"OUT MIXL", "INL Switch", "INL VOL"},
1704 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1705 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1706 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1707 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1708
1709 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1710 {"OUT MIXR", "BST2 Switch", "BST2"},
1711 {"OUT MIXR", "BST1 Switch", "BST1"},
1712 {"OUT MIXR", "INR Switch", "INR VOL"},
1713 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1714 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1715 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1716 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1717
1718 {"SPKVOL L", NULL, "SPK MIXL"},
1719 {"SPKVOL R", NULL, "SPK MIXR"},
1720 {"HPOVOL L", NULL, "OUT MIXL"},
1721 {"HPOVOL R", NULL, "OUT MIXR"},
1722 {"OUTVOL L", NULL, "OUT MIXL"},
1723 {"OUTVOL R", NULL, "OUT MIXR"},
1724
1725 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1726 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
1727 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
1728 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
1729 {"SPOL MIX", "BST1 Switch", "BST1"},
1730 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1731 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1732 {"SPOR MIX", "BST1 Switch", "BST1"},
1733
1734 {"HPOL MIX", "DAC2 Switch", "DAC L2"},
1735 {"HPOL MIX", "DAC1 Switch", "DAC L1"},
1736 {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
1737 {"HPOR MIX", "DAC2 Switch", "DAC R2"},
1738 {"HPOR MIX", "DAC1 Switch", "DAC R1"},
1739 {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
1740
1741 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1742 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1743 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1744 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1745
1746 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1747 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1748 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1749 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1750 {"Mono MIX", "BST1 Switch", "BST1"},
1751
1752 {"HP L amp", NULL, "HPOL MIX"},
1753 {"HP R amp", NULL, "HPOR MIX"},
1754
1755/* {"HP L amp", NULL, "Improve HP amp drv"},
1756 {"HP R amp", NULL, "Improve HP amp drv"}, */
1757
1758 {"SPOLP", NULL, "SPOL MIX"},
1759 {"SPOLN", NULL, "SPOL MIX"},
1760 {"SPORP", NULL, "SPOR MIX"},
1761 {"SPORN", NULL, "SPOR MIX"},
1762
1763 {"SPOLP", NULL, "Improve SPK amp drv"},
1764 {"SPOLN", NULL, "Improve SPK amp drv"},
1765 {"SPORP", NULL, "Improve SPK amp drv"},
1766 {"SPORN", NULL, "Improve SPK amp drv"},
1767
1768 {"HPOL", NULL, "Improve HP amp drv"},
1769 {"HPOR", NULL, "Improve HP amp drv"},
1770
1771 {"HPOL", NULL, "HP L amp"},
1772 {"HPOR", NULL, "HP R amp"},
1773 {"LOUTL", NULL, "LOUT MIX"},
1774 {"LOUTR", NULL, "LOUT MIX"},
1775 {"MonoP", NULL, "Mono MIX"},
1776 {"MonoN", NULL, "Mono MIX"},
1777 {"MonoP", NULL, "Improve mono amp drv"},
1778};
1779
1780static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1781{
1782 int ret = 0, val = snd_soc_read(codec, RT5640_I2S1_SDP);
1783
1784 if (codec == NULL)
1785 return -EINVAL;
1786
1787 val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
1788 switch (dai_id) {
1789 case RT5640_AIF1:
1790 if (val == RT5640_IF_123 || val == RT5640_IF_132 ||
1791 val == RT5640_IF_113)
1792 ret |= RT5640_U_IF1;
1793 if (val == RT5640_IF_312 || val == RT5640_IF_213 ||
1794 val == RT5640_IF_113)
1795 ret |= RT5640_U_IF2;
1796 if (val == RT5640_IF_321 || val == RT5640_IF_231)
1797 ret |= RT5640_U_IF3;
1798 break;
1799
1800 case RT5640_AIF2:
1801 if (val == RT5640_IF_231 || val == RT5640_IF_213 ||
1802 val == RT5640_IF_223)
1803 ret |= RT5640_U_IF1;
1804 if (val == RT5640_IF_123 || val == RT5640_IF_321 ||
1805 val == RT5640_IF_223)
1806 ret |= RT5640_U_IF2;
1807 if (val == RT5640_IF_132 || val == RT5640_IF_312)
1808 ret |= RT5640_U_IF3;
1809 break;
1810
1811#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
1812 CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
1813
1814 case RT5640_AIF3:
1815 if (val == RT5640_IF_312 || val == RT5640_IF_321)
1816 ret |= RT5640_U_IF1;
1817 if (val == RT5640_IF_132 || val == RT5640_IF_231)
1818 ret |= RT5640_U_IF2;
1819 if (val == RT5640_IF_123 || val == RT5640_IF_213 ||
1820 val == RT5640_IF_113 || val == RT5640_IF_223)
1821 ret |= RT5640_U_IF3;
1822 break;
1823#endif
1824
1825 default:
1826 ret = -EINVAL;
1827 break;
1828 }
1829
1830 return ret;
1831}
1832
1833static int get_clk_info(int sclk, int rate)
1834{
1835 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1836
1837 if (sclk <= 0 || rate <= 0)
1838 return -EINVAL;
1839
1840 rate = rate << 8;
1841 for (i = 0; i < ARRAY_SIZE(pd); i++)
1842 if (sclk == rate * pd[i])
1843 return i;
1844
1845 return -EINVAL;
1846}
1847
1848static int rt5640_hw_params(struct snd_pcm_substream *substream,
1849 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1850{
1851 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1852 struct snd_soc_codec *codec = rtd->codec;
1853 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1854 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
1855 int pre_div, bclk_ms, frame_size;
1856
1857 rt5640->lrck[dai->id] = params_rate(params);
1858 pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
1859 if (pre_div < 0) {
1860 dev_err(codec->dev, "Unsupported clock setting\n");
1861 return -EINVAL;
1862 }
1863 frame_size = snd_soc_params_to_frame_size(params);
1864 if (frame_size < 0) {
1865 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1866 return -EINVAL;
1867 }
1868 bclk_ms = frame_size > 32 ? 1 : 0;
1869 rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
1870
1871 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1872 rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
1873 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1874 bclk_ms, pre_div, dai->id);
1875
1876 switch (params_format(params)) {
1877 case SNDRV_PCM_FORMAT_S16_LE:
1878 break;
1879 case SNDRV_PCM_FORMAT_S20_3LE:
1880 val_len |= RT5640_I2S_DL_20;
1881 break;
1882 case SNDRV_PCM_FORMAT_S24_LE:
1883 val_len |= RT5640_I2S_DL_24;
1884 break;
1885 case SNDRV_PCM_FORMAT_S8:
1886 val_len |= RT5640_I2S_DL_8;
1887 break;
1888 default:
1889 return -EINVAL;
1890 }
1891
1892 dai_sel = get_sdp_info(codec, dai->id);
1893 if (dai_sel < 0) {
1894 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1895 return -EINVAL;
1896 }
1897 if (dai_sel & RT5640_U_IF1) {
1898 mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
1899 val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
1900 pre_div << RT5640_I2S_PD1_SFT;
1901 snd_soc_update_bits(codec, RT5640_I2S1_SDP,
1902 RT5640_I2S_DL_MASK, val_len);
1903 snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
1904 }
1905 if (dai_sel & RT5640_U_IF2) {
1906 mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
1907 val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
1908 pre_div << RT5640_I2S_PD2_SFT;
1909 snd_soc_update_bits(codec, RT5640_I2S2_SDP,
1910 RT5640_I2S_DL_MASK, val_len);
1911 snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
1912 }
1913#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
1914 CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
1915 if (dai_sel & RT5640_U_IF3) {
1916 mask_clk = RT5640_I2S_BCLK_MS3_MASK | RT5640_I2S_PD3_MASK;
1917 val_clk = bclk_ms << RT5640_I2S_BCLK_MS3_SFT |
1918 pre_div << RT5640_I2S_PD3_SFT;
1919 snd_soc_update_bits(codec, RT5640_I2S3_SDP,
1920 RT5640_I2S_DL_MASK, val_len);
1921 snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
1922 }
1923#endif
1924 return 0;
1925}
1926
1927static int rt5640_prepare(struct snd_pcm_substream *substream,
1928 struct snd_soc_dai *dai)
1929{
1930 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1931 struct snd_soc_codec *codec = rtd->codec;
1932 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1933
1934 rt5640->aif_pu = dai->id;
1935 return 0;
1936}
1937
1938static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1939{
1940 struct snd_soc_codec *codec = dai->codec;
1941 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1942 unsigned int reg_val = 0, dai_sel;
1943
1944 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1945 case SND_SOC_DAIFMT_CBM_CFM:
1946 rt5640->master[dai->id] = 1;
1947 break;
1948 case SND_SOC_DAIFMT_CBS_CFS:
1949 reg_val |= RT5640_I2S_MS_S;
1950 rt5640->master[dai->id] = 0;
1951 break;
1952 default:
1953 return -EINVAL;
1954 }
1955
1956 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1957 case SND_SOC_DAIFMT_NB_NF:
1958 break;
1959 case SND_SOC_DAIFMT_IB_NF:
1960 reg_val |= RT5640_I2S_BP_INV;
1961 break;
1962 default:
1963 return -EINVAL;
1964 }
1965
1966 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1967 case SND_SOC_DAIFMT_I2S:
1968 break;
1969 case SND_SOC_DAIFMT_LEFT_J:
1970 reg_val |= RT5640_I2S_DF_LEFT;
1971 break;
1972 case SND_SOC_DAIFMT_DSP_A:
1973 reg_val |= RT5640_I2S_DF_PCM_A;
1974 break;
1975 case SND_SOC_DAIFMT_DSP_B:
1976 reg_val |= RT5640_I2S_DF_PCM_B;
1977 break;
1978 default:
1979 return -EINVAL;
1980 }
1981
1982 dai_sel = get_sdp_info(codec, dai->id);
1983 if (dai_sel < 0) {
1984 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
1985 return -EINVAL;
1986 }
1987 if (dai_sel & RT5640_U_IF1) {
1988 snd_soc_update_bits(codec, RT5640_I2S1_SDP,
1989 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1990 RT5640_I2S_DF_MASK, reg_val);
1991 }
1992 if (dai_sel & RT5640_U_IF2) {
1993 snd_soc_update_bits(codec, RT5640_I2S2_SDP,
1994 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1995 RT5640_I2S_DF_MASK, reg_val);
1996 }
1997#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
1998 CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
1999 if (dai_sel & RT5640_U_IF3) {
2000 snd_soc_update_bits(codec, RT5640_I2S3_SDP,
2001 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
2002 RT5640_I2S_DF_MASK, reg_val);
2003 }
2004#endif
2005 return 0;
2006}
2007
2008static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
2009 int clk_id, unsigned int freq, int dir)
2010{
2011 struct snd_soc_codec *codec = dai->codec;
2012 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
2013 unsigned int reg_val = 0;
2014
2015 if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
2016 return 0;
2017
2018 switch (clk_id) {
2019 case RT5640_SCLK_S_MCLK:
2020 reg_val |= RT5640_SCLK_SRC_MCLK;
2021 break;
2022 case RT5640_SCLK_S_PLL1:
2023 reg_val |= RT5640_SCLK_SRC_PLL1;
2024 break;
2025 case RT5640_SCLK_S_PLL1_TK:
2026 reg_val |= RT5640_SCLK_SRC_PLL1T;
2027 break;
2028 case RT5640_SCLK_S_RCCLK:
2029 reg_val |= RT5640_SCLK_SRC_RCCLK;
2030 break;
2031 default:
2032 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2033 return -EINVAL;
2034 }
2035 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2036 RT5640_SCLK_SRC_MASK, reg_val);
2037 rt5640->sysclk = freq;
2038 rt5640->sysclk_src = clk_id;
2039
2040 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2041 return 0;
2042}
2043
2044/**
2045 * rt5640_pll_calc - Calcualte PLL M/N/K code.
2046 * @freq_in: external clock provided to codec.
2047 * @freq_out: target clock which codec works on.
2048 * @pll_code: Pointer to structure with M, N, K and bypass flag.
2049 *
2050 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
2051 * which make calculation more efficiently.
2052 *
2053 * Returns 0 for success or negative error code.
2054 */
2055static int rt5640_pll_calc(const unsigned int freq_in,
2056 const unsigned int freq_out, struct rt5640_pll_code *pll_code)
2057{
2058 int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
2059 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
2060 bool bypass = false;
2061
2062 if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
2063 return -EINVAL;
2064
2065 for (n_t = 0; n_t <= max_n; n_t++) {
2066 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
2067 if (in_t < 0)
2068 continue;
2069 if (in_t == freq_out) {
2070 bypass = true;
2071 n = n_t;
2072 goto code_find;
2073 }
2074 for (m_t = 0; m_t <= max_m; m_t++) {
2075 out_t = in_t / (m_t + 2);
2076 red = abs(out_t - freq_out);
2077 if (red < red_t) {
2078 n = n_t;
2079 m = m_t;
2080 if (red == 0)
2081 goto code_find;
2082 red_t = red;
2083 }
2084 }
2085 }
2086 pr_debug("Only get approximation about PLL\n");
2087
2088code_find:
2089
2090 pll_code->m_bp = bypass;
2091 pll_code->m_code = m;
2092 pll_code->n_code = n;
2093 pll_code->k_code = 2;
2094 return 0;
2095}
2096
2097static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2098 unsigned int freq_in, unsigned int freq_out)
2099{
2100 struct snd_soc_codec *codec = dai->codec;
2101 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
2102 struct rt5640_pll_code pll_code;
2103 int ret, dai_sel;
2104
2105 if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
2106 freq_out == rt5640->pll_out)
2107 return 0;
2108
2109 if (!freq_in || !freq_out) {
2110 dev_dbg(codec->dev, "PLL disabled\n");
2111
2112 rt5640->pll_in = 0;
2113 rt5640->pll_out = 0;
2114 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2115 RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
2116 return 0;
2117 }
2118
2119 switch (source) {
2120 case RT5640_PLL1_S_MCLK:
2121 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2122 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
2123 break;
2124 case RT5640_PLL1_S_BCLK1:
2125 case RT5640_PLL1_S_BCLK2:
2126
2127#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
2128 CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
2129
2130 case RT5640_PLL1_S_BCLK3:
2131
2132#endif
2133 dai_sel = get_sdp_info(codec, dai->id);
2134 if (dai_sel < 0) {
2135 dev_err(codec->dev,
2136 "Failed to get sdp info: %d\n", dai_sel);
2137 return -EINVAL;
2138 }
2139 if (dai_sel & RT5640_U_IF1) {
2140 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2141 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
2142 }
2143 if (dai_sel & RT5640_U_IF2) {
2144 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2145 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
2146 }
2147 if (dai_sel & RT5640_U_IF3) {
2148 snd_soc_update_bits(codec, RT5640_GLB_CLK,
2149 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK3);
2150 }
2151 break;
2152 default:
2153 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2154 return -EINVAL;
2155 }
2156
2157 ret = rt5640_pll_calc(freq_in, freq_out, &pll_code);
2158 if (ret < 0) {
2159 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2160 return ret;
2161 }
2162
2163 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
2164 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
2165
2166 snd_soc_write(codec, RT5640_PLL_CTRL1,
2167 pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
2168 snd_soc_write(codec, RT5640_PLL_CTRL2,
2169 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
2170 pll_code.m_bp << RT5640_PLL_M_BP_SFT);
2171
2172 rt5640->pll_in = freq_in;
2173 rt5640->pll_out = freq_out;
2174 rt5640->pll_src = source;
2175
2176 return 0;
2177}
2178
2179/**
2180 * rt5640_index_show - Dump private registers.
2181 * @dev: codec device.
2182 * @attr: device attribute.
2183 * @buf: buffer for display.
2184 *
2185 * To show non-zero values of all private registers.
2186 *
2187 * Returns buffer length.
2188 */
2189static ssize_t rt5640_index_show(struct device *dev,
2190 struct device_attribute *attr, char *buf)
2191{
2192 struct i2c_client *client = to_i2c_client(dev);
2193 struct rt5640_priv *rt5640 = i2c_get_clientdata(client);
2194 struct snd_soc_codec *codec = rt5640->codec;
2195 unsigned int val;
2196 int cnt = 0, i;
2197
2198 cnt += sprintf(buf, "RT5640 index register\n");
2199 for (i = 0; i < 0xb4; i++) {
2200 if (cnt + 9 >= PAGE_SIZE - 1)
2201 break;
2202 val = rt5640_index_read(codec, i);
2203 if (!val)
2204 continue;
2205 cnt += snprintf(buf + cnt, 10, "%02x: %04x\n", i, val);
2206 }
2207
2208 if (cnt >= PAGE_SIZE)
2209 cnt = PAGE_SIZE - 1;
2210
2211 return cnt;
2212}
2213static DEVICE_ATTR(index_reg, 0444, rt5640_index_show, NULL);
2214
2215static int rt5640_set_bias_level(struct snd_soc_codec *codec,
2216 enum snd_soc_bias_level level)
2217{
2218 switch (level) {
2219 case SND_SOC_BIAS_ON:
2220#ifdef RT5640_DEMO
2221 snd_soc_update_bits(codec, RT5640_SPK_VOL,
2222 RT5640_L_MUTE | RT5640_R_MUTE, 0);
2223 snd_soc_update_bits(codec, RT5640_HP_VOL,
2224 RT5640_L_MUTE | RT5640_R_MUTE, 0);
2225 break;
2226#endif
2227 case SND_SOC_BIAS_PREPARE:
2228#ifdef RT5640_DEMO
2229 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2230 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2231 RT5640_PWR_BG | RT5640_PWR_VREF2,
2232 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2233 RT5640_PWR_BG | RT5640_PWR_VREF2);
2234 msleep(100);
2235
2236 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2237 RT5640_PWR_FV1 | RT5640_PWR_FV2,
2238 RT5640_PWR_FV1 | RT5640_PWR_FV2);
2239
2240 snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
2241 RT5640_PWR_MB1 | RT5640_PWR_MB2,
2242 RT5640_PWR_MB1 | RT5640_PWR_MB2);
2243#endif
2244 break;
2245
2246 case SND_SOC_BIAS_STANDBY:
2247#ifdef RT5640_DEMO
2248 snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
2249 RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
2250 snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
2251 RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
2252
2253 snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
2254 RT5640_PWR_MB1 | RT5640_PWR_MB2,
2255 0);
2256#endif
2257 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2258 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2259 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2260 RT5640_PWR_BG | RT5640_PWR_VREF2,
2261 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2262 RT5640_PWR_BG | RT5640_PWR_VREF2);
2263 msleep(10);
2264 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2265 RT5640_PWR_FV1 | RT5640_PWR_FV2,
2266 RT5640_PWR_FV1 | RT5640_PWR_FV2);
2267 codec->cache_only = false;
2268 snd_soc_cache_sync(codec);
2269 }
2270 break;
2271
2272 case SND_SOC_BIAS_OFF:
2273#ifdef RT5640_DEMO
2274 snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
2275 RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
2276 snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
2277 RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
2278 snd_soc_update_bits(codec, RT5640_OUTPUT, RT5640_L_MUTE |
2279 RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
2280 snd_soc_update_bits(codec, RT5640_MONO_OUT,
2281 RT5640_L_MUTE, RT5640_L_MUTE);
2282#endif
2283 snd_soc_write(codec, RT5640_PWR_DIG1, 0x0000);
2284 snd_soc_write(codec, RT5640_PWR_DIG2, 0x0000);
2285 snd_soc_write(codec, RT5640_PWR_VOL, 0x0000);
2286 snd_soc_write(codec, RT5640_PWR_MIXER, 0x0000);
2287 snd_soc_write(codec, RT5640_PWR_ANLG1, 0x0000);
2288 snd_soc_write(codec, RT5640_PWR_ANLG2, 0x0000);
2289 break;
2290
2291 default:
2292 break;
2293 }
2294 codec->dapm.bias_level = level;
2295
2296 return 0;
2297}
2298
2299static int rt5640_probe(struct snd_soc_codec *codec)
2300{
2301 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
2302 int ret;
2303 u16 val;
2304
2305 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
2306 if (ret != 0) {
2307 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2308 return ret;
2309 }
2310
2311 val = snd_soc_read(codec, RT5640_RESET);
2312 if (val != rt5640_reg[RT5640_RESET]) {
2313 dev_err(codec->dev,
2314 "Device with ID register %x is not a rt5640\n", val);
2315 return -ENODEV;
2316 }
2317
2318 rt5640_reset(codec);
2319 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2320 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2321 RT5640_PWR_BG | RT5640_PWR_VREF2,
2322 RT5640_PWR_VREF1 | RT5640_PWR_MB |
2323 RT5640_PWR_BG | RT5640_PWR_VREF2);
2324 msleep(100);
2325 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
2326 RT5640_PWR_FV1 | RT5640_PWR_FV2,
2327 RT5640_PWR_FV1 | RT5640_PWR_FV2);
2328 /* DMIC */
2329 if (rt5640->dmic_en == RT5640_DMIC1) {
2330 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
2331 RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
2332 snd_soc_update_bits(codec, RT5640_DMIC,
2333 RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK,
2334 RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING);
2335 } else if (rt5640->dmic_en == RT5640_DMIC2) {
2336 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
2337 RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
2338 snd_soc_update_bits(codec, RT5640_DMIC,
2339 RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK,
2340 RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING);
2341 }
2342
2343#ifdef RT5640_DEMO
2344 rt5640_reg_init(codec);
2345#endif
2346
2347
2348#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
2349 rt5640_register_dsp(codec);
2350#endif
2351
2352 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
2353
2354 snd_soc_add_controls(codec, rt5640_snd_controls,
2355 ARRAY_SIZE(rt5640_snd_controls));
2356
2357 rt5640->codec = codec;
2358 ret = device_create_file(codec->dev, &dev_attr_index_reg);
2359 if (ret != 0) {
2360 dev_err(codec->dev,
2361 "Failed to create index_reg sysfs files: %d\n", ret);
2362 return ret;
2363 }
2364
2365 return 0;
2366}
2367
2368static int rt5640_remove(struct snd_soc_codec *codec)
2369{
2370 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
2371 rt5640_reset(codec);
2372 snd_soc_write(codec, RT5640_PWR_ANLG1, 0);
2373
2374 return 0;
2375}
2376#ifdef CONFIG_PM
2377static int rt5640_suspend(struct snd_soc_codec *codec, pm_message_t state)
2378{
2379 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
2380 snd_soc_write(codec, RT5640_PWR_ANLG1, 0);
2381
2382 return 0;
2383}
2384
2385static int rt5640_resume(struct snd_soc_codec *codec)
2386{
2387 rt5640_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2388
2389 return 0;
2390}
2391#else
2392#define rt5640_suspend NULL
2393#define rt5640_resume NULL
2394#endif
2395
2396#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2397#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2398 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2399
2400struct snd_soc_dai_ops rt5640_aif_dai_ops = {
2401 .hw_params = rt5640_hw_params,
2402 .prepare = rt5640_prepare,
2403 .set_fmt = rt5640_set_dai_fmt,
2404 .set_sysclk = rt5640_set_dai_sysclk,
2405 .set_pll = rt5640_set_dai_pll,
2406};
2407
2408struct snd_soc_dai_driver rt5640_dai[] = {
2409 {
2410 .name = "rt5640-aif1",
2411 .id = RT5640_AIF1,
2412 .playback = {
2413 .stream_name = "AIF1 Playback",
2414 .channels_min = 1,
2415 .channels_max = 2,
2416 .rates = RT5640_STEREO_RATES,
2417 .formats = RT5640_FORMATS,
2418 },
2419 .capture = {
2420 .stream_name = "AIF1 Capture",
2421 .channels_min = 1,
2422 .channels_max = 2,
2423 .rates = RT5640_STEREO_RATES,
2424 .formats = RT5640_FORMATS,
2425 },
2426 .ops = &rt5640_aif_dai_ops,
2427 },
2428 {
2429 .name = "rt5640-aif2",
2430 .id = RT5640_AIF2,
2431 .playback = {
2432 .stream_name = "AIF2 Playback",
2433 .channels_min = 1,
2434 .channels_max = 2,
2435 .rates = RT5640_STEREO_RATES,
2436 .formats = RT5640_FORMATS,
2437 },
2438 .capture = {
2439 .stream_name = "AIF2 Capture",
2440 .channels_min = 1,
2441 .channels_max = 2,
2442 .rates = RT5640_STEREO_RATES,
2443 .formats = RT5640_FORMATS,
2444 },
2445 .ops = &rt5640_aif_dai_ops,
2446 },
2447#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
2448 CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
2449 {
2450 .name = "rt5640-aif3",
2451 .id = RT5640_AIF3,
2452 .playback = {
2453 .stream_name = "AIF3 Playback",
2454 .channels_min = 1,
2455 .channels_max = 2,
2456 .rates = RT5640_STEREO_RATES,
2457 .formats = RT5640_FORMATS,
2458 },
2459 .capture = {
2460 .stream_name = "AIF3 Capture",
2461 .channels_min = 1,
2462 .channels_max = 2,
2463 .rates = RT5640_STEREO_RATES,
2464 .formats = RT5640_FORMATS,
2465 },
2466 .ops = &rt5640_aif_dai_ops,
2467 },
2468#endif
2469};
2470
2471static struct snd_soc_codec_driver soc_codec_dev_rt5640 = {
2472 .probe = rt5640_probe,
2473 .remove = rt5640_remove,
2474 .suspend = rt5640_suspend,
2475 .resume = rt5640_resume,
2476 .set_bias_level = rt5640_set_bias_level,
2477 .reg_cache_size = RT5640_VENDOR_ID2 + 1,
2478 .reg_word_size = sizeof(u16),
2479 .reg_cache_default = rt5640_reg,
2480 .volatile_register = rt5640_volatile_register,
2481 .readable_register = rt5640_readable_register,
2482 .reg_cache_step = 1,
2483 .dapm_widgets = rt5640_dapm_widgets,
2484 .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
2485 .dapm_routes = rt5640_dapm_routes,
2486 .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
2487};
2488
2489static const struct i2c_device_id rt5640_i2c_id[] = {
2490 { "rt5640", 0 },
2491 { }
2492};
2493MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
2494
2495static int rt5640_i2c_probe(struct i2c_client *i2c,
2496 const struct i2c_device_id *id)
2497{
2498 struct rt5640_priv *rt5640;
2499 int ret;
2500
2501 rt5640 = kzalloc(sizeof(struct rt5640_priv), GFP_KERNEL);
2502 if (NULL == rt5640)
2503 return -ENOMEM;
2504
2505 i2c_set_clientdata(i2c, rt5640);
2506
2507 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
2508 rt5640_dai, ARRAY_SIZE(rt5640_dai));
2509 if (ret < 0)
2510 kfree(rt5640);
2511
2512 return ret;
2513}
2514
2515static __devexit int rt5640_i2c_remove(struct i2c_client *i2c)
2516{
2517 snd_soc_unregister_codec(&i2c->dev);
2518 kfree(i2c_get_clientdata(i2c));
2519 return 0;
2520}
2521
2522struct i2c_driver rt5640_i2c_driver = {
2523 .driver = {
2524 .name = "rt5640",
2525 .owner = THIS_MODULE,
2526 },
2527 .probe = rt5640_i2c_probe,
2528 .remove = __devexit_p(rt5640_i2c_remove),
2529 .id_table = rt5640_i2c_id,
2530};
2531
2532static int __init rt5640_modinit(void)
2533{
2534 return i2c_add_driver(&rt5640_i2c_driver);
2535}
2536module_init(rt5640_modinit);
2537
2538static void __exit rt5640_modexit(void)
2539{
2540 i2c_del_driver(&rt5640_i2c_driver);
2541}
2542module_exit(rt5640_modexit);
2543
2544MODULE_DESCRIPTION("ASoC RT5640 driver");
2545MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
2546MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
new file mode 100644
index 00000000000..d6920f00e08
--- /dev/null
+++ b/sound/soc/codecs/rt5640.h
@@ -0,0 +1,2098 @@
1/*
2 * rt5640.h -- RT5640 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5640_H__
13#define __RT5640_H__
14
15/* Info */
16#define RT5640_RESET 0x00
17#define RT5640_VENDOR_ID 0xfd
18#define RT5640_VENDOR_ID1 0xfe
19#define RT5640_VENDOR_ID2 0xff
20/* I/O - Output */
21#define RT5640_SPK_VOL 0x01
22#define RT5640_HP_VOL 0x02
23#define RT5640_OUTPUT 0x03
24#define RT5640_MONO_OUT 0x04
25/* I/O - Input */
26#define RT5640_IN1_IN2 0x0d
27#define RT5640_IN3_IN4 0x0e
28#define RT5640_INL_INR_VOL 0x0f
29/* I/O - ADC/DAC/DMIC */
30#define RT5640_DAC1_DIG_VOL 0x19
31#define RT5640_DAC2_DIG_VOL 0x1a
32#define RT5640_DAC2_CTRL 0x1b
33#define RT5640_ADC_DIG_VOL 0x1c
34#define RT5640_ADC_DATA 0x1d
35#define RT5640_ADC_BST_VOL 0x1e
36/* Mixer - D-D */
37#define RT5640_STO_ADC_MIXER 0x27
38#define RT5640_MONO_ADC_MIXER 0x28
39#define RT5640_AD_DA_MIXER 0x29
40#define RT5640_STO_DAC_MIXER 0x2a
41#define RT5640_MONO_DAC_MIXER 0x2b
42#define RT5640_DIG_MIXER 0x2c
43#define RT5640_DSP_PATH1 0x2d
44#define RT5640_DSP_PATH2 0x2e
45#define RT5640_DIG_INF_DATA 0x2f
46/* Mixer - ADC */
47#define RT5640_REC_L1_MIXER 0x3b
48#define RT5640_REC_L2_MIXER 0x3c
49#define RT5640_REC_R1_MIXER 0x3d
50#define RT5640_REC_R2_MIXER 0x3e
51/* Mixer - DAC */
52#define RT5640_HPO_MIXER 0x45
53#define RT5640_SPK_L_MIXER 0x46
54#define RT5640_SPK_R_MIXER 0x47
55#define RT5640_SPO_L_MIXER 0x48
56#define RT5640_SPO_R_MIXER 0x49
57#define RT5640_SPO_CLSD_RATIO 0x4a
58#define RT5640_MONO_MIXER 0x4c
59#define RT5640_OUT_L1_MIXER 0x4d
60#define RT5640_OUT_L2_MIXER 0x4e
61#define RT5640_OUT_L3_MIXER 0x4f
62#define RT5640_OUT_R1_MIXER 0x50
63#define RT5640_OUT_R2_MIXER 0x51
64#define RT5640_OUT_R3_MIXER 0x52
65#define RT5640_LOUT_MIXER 0x53
66/* Power */
67#define RT5640_PWR_DIG1 0x61
68#define RT5640_PWR_DIG2 0x62
69#define RT5640_PWR_ANLG1 0x63
70#define RT5640_PWR_ANLG2 0x64
71#define RT5640_PWR_MIXER 0x65
72#define RT5640_PWR_VOL 0x66
73/* Private Register Control */
74#define RT5640_PRIV_INDEX 0x6a
75#define RT5640_PRIV_DATA 0x6c
76/* Format - ADC/DAC */
77#define RT5640_I2S1_SDP 0x70
78#define RT5640_I2S2_SDP 0x71
79#define RT5640_I2S3_SDP 0x72
80#define RT5640_ADDA_CLK1 0x73
81#define RT5640_ADDA_CLK2 0x74
82#define RT5640_DMIC 0x75
83/* Function - Analog */
84#define RT5640_GLB_CLK 0x80
85#define RT5640_PLL_CTRL1 0x81
86#define RT5640_PLL_CTRL2 0x82
87#define RT5640_ASRC_1 0x83
88#define RT5640_ASRC_2 0x84
89#define RT5640_ASRC_3 0x85
90#define RT5640_ASRC_4 0x89
91#define RT5640_ASRC_5 0x8a
92#define RT5640_HP_OVCD 0x8b
93#define RT5640_CLS_D_OVCD 0x8c
94#define RT5640_CLS_D_OUT 0x8d
95#define RT5640_DEPOP_M1 0x8e
96#define RT5640_DEPOP_M2 0x8f
97#define RT5640_DEPOP_M3 0x90
98#define RT5640_CHARGE_PUMP 0x91
99#define RT5640_PV_DET_SPK_G 0x92
100#define RT5640_MICBIAS 0x93
101/* Function - Digital */
102#define RT5640_EQ_CTRL1 0xb0
103#define RT5640_EQ_CTRL2 0xb1
104#define RT5640_WIND_FILTER 0xb2
105#define RT5640_DRC_AGC_1 0xb4
106#define RT5640_DRC_AGC_2 0xb5
107#define RT5640_DRC_AGC_3 0xb6
108#define RT5640_SVOL_ZC 0xb7
109#define RT5640_ANC_CTRL1 0xb8
110#define RT5640_ANC_CTRL2 0xb9
111#define RT5640_ANC_CTRL3 0xba
112#define RT5640_JD_CTRL 0xbb
113#define RT5640_ANC_JD 0xbc
114#define RT5640_IRQ_CTRL1 0xbd
115#define RT5640_IRQ_CTRL2 0xbe
116#define RT5640_INT_IRQ_ST 0xbf
117#define RT5640_GPIO_CTRL1 0xc0
118#define RT5640_GPIO_CTRL2 0xc1
119#define RT5640_GPIO_CTRL3 0xc2
120#define RT5640_DSP_CTRL1 0xc4
121#define RT5640_DSP_CTRL2 0xc5
122#define RT5640_DSP_CTRL3 0xc6
123#define RT5640_DSP_CTRL4 0xc7
124#define RT5640_PGM_REG_ARR1 0xc8
125#define RT5640_PGM_REG_ARR2 0xc9
126#define RT5640_PGM_REG_ARR3 0xca
127#define RT5640_PGM_REG_ARR4 0xcb
128#define RT5640_PGM_REG_ARR5 0xcc
129#define RT5640_SCB_FUNC 0xcd
130#define RT5640_SCB_CTRL 0xce
131#define RT5640_BASE_BACK 0xcf
132#define RT5640_MP3_PLUS1 0xd0
133#define RT5640_MP3_PLUS2 0xd1
134#define RT5640_3D_HP 0xd2
135#define RT5640_ADJ_HPF 0xd3
136#define RT5640_HP_CALIB_AMP_DET 0xd6
137#define RT5640_HP_CALIB2 0xd7
138#define RT5640_SV_ZCD1 0xd9
139#define RT5640_SV_ZCD2 0xda
140/* Dummy Register */
141#define RT5640_DUMMY1 0xfa
142#define RT5640_DUMMY2 0xfb
143#define RT5640_DUMMY3 0xfc
144
145
146/* Index of Codec Private Register definition */
147#define RT5640_3D_SPK 0x63
148#define RT5640_WND_1 0x6c
149#define RT5640_WND_2 0x6d
150#define RT5640_WND_3 0x6e
151#define RT5640_WND_4 0x6f
152#define RT5640_WND_5 0x70
153#define RT5640_WND_8 0x73
154#define RT5640_DIP_SPK_INF 0x75
155#define RT5640_EQ_BW_LOP 0xa0
156#define RT5640_EQ_GN_LOP 0xa1
157#define RT5640_EQ_FC_BP1 0xa2
158#define RT5640_EQ_BW_BP1 0xa3
159#define RT5640_EQ_GN_BP1 0xa4
160#define RT5640_EQ_FC_BP2 0xa5
161#define RT5640_EQ_BW_BP2 0xa6
162#define RT5640_EQ_GN_BP2 0xa7
163#define RT5640_EQ_FC_BP3 0xa8
164#define RT5640_EQ_BW_BP3 0xa9
165#define RT5640_EQ_GN_BP3 0xaa
166#define RT5640_EQ_FC_BP4 0xab
167#define RT5640_EQ_BW_BP4 0xac
168#define RT5640_EQ_GN_BP4 0xad
169#define RT5640_EQ_FC_HIP1 0xae
170#define RT5640_EQ_GN_HIP1 0xaf
171#define RT5640_EQ_FC_HIP2 0xb0
172#define RT5640_EQ_BW_HIP2 0xb1
173#define RT5640_EQ_GN_HIP2 0xb2
174#define RT5640_EQ_PRE_VOL 0xb3
175#define RT5640_EQ_PST_VOL 0xb4
176
177
178/* global definition */
179#define RT5640_L_MUTE (0x1 << 15)
180#define RT5640_L_MUTE_SFT 15
181#define RT5640_VOL_L_MUTE (0x1 << 14)
182#define RT5640_VOL_L_SFT 14
183#define RT5640_R_MUTE (0x1 << 7)
184#define RT5640_R_MUTE_SFT 7
185#define RT5640_VOL_R_MUTE (0x1 << 6)
186#define RT5640_VOL_R_SFT 6
187#define RT5640_L_VOL_MASK (0x3f << 8)
188#define RT5640_L_VOL_SFT 8
189#define RT5640_R_VOL_MASK (0x3f)
190#define RT5640_R_VOL_SFT 0
191
192/* IN1 and IN2 Control (0x0d) */
193/* IN3 and IN4 Control (0x0e) */
194#define RT5640_BST_SFT1 12
195#define RT5640_BST_SFT2 8
196#define RT5640_IN_DF1 (0x1 << 7)
197#define RT5640_IN_SFT1 7
198#define RT5640_IN_DF2 (0x1 << 6)
199#define RT5640_IN_SFT2 6
200
201/* INL and INR Volume Control (0x0f) */
202#define RT5640_INL_SEL_MASK (0x1 << 15)
203#define RT5640_INL_SEL_SFT 15
204#define RT5640_INL_SEL_IN4P (0x0 << 15)
205#define RT5640_INL_SEL_MONOP (0x1 << 15)
206#define RT5640_INL_VOL_MASK (0x1f << 8)
207#define RT5640_INL_VOL_SFT 8
208#define RT5640_INR_SEL_MASK (0x1 << 7)
209#define RT5640_INR_SEL_SFT 7
210#define RT5640_INR_SEL_IN4N (0x0 << 7)
211#define RT5640_INR_SEL_MONON (0x1 << 7)
212#define RT5640_INR_VOL_MASK (0x1f)
213#define RT5640_INR_VOL_SFT 0
214
215/* DAC1 Digital Volume (0x19) */
216#define RT5640_DAC_L1_VOL_MASK (0xff << 8)
217#define RT5640_DAC_L1_VOL_SFT 8
218#define RT5640_DAC_R1_VOL_MASK (0xff)
219#define RT5640_DAC_R1_VOL_SFT 0
220
221/* DAC2 Digital Volume (0x1a) */
222#define RT5640_DAC_L2_VOL_MASK (0xff << 8)
223#define RT5640_DAC_L2_VOL_SFT 8
224#define RT5640_DAC_R2_VOL_MASK (0xff)
225#define RT5640_DAC_R2_VOL_SFT 0
226
227/* DAC2 Control (0x1b) */
228#define RT5640_M_DAC_L2_VOL (0x1 << 13)
229#define RT5640_M_DAC_L2_VOL_SFT 13
230#define RT5640_M_DAC_R2_VOL (0x1 << 12)
231#define RT5640_M_DAC_R2_VOL_SFT 12
232
233/* ADC Digital Volume Control (0x1c) */
234#define RT5640_ADC_L_VOL_MASK (0x7f << 8)
235#define RT5640_ADC_L_VOL_SFT 8
236#define RT5640_ADC_R_VOL_MASK (0x7f)
237#define RT5640_ADC_R_VOL_SFT 0
238
239/* Mono ADC Digital Volume Control (0x1d) */
240#define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
241#define RT5640_MONO_ADC_L_VOL_SFT 8
242#define RT5640_MONO_ADC_R_VOL_MASK (0x7f)
243#define RT5640_MONO_ADC_R_VOL_SFT 0
244
245/* ADC Boost Volume Control (0x1e) */
246#define RT5640_ADC_L_BST_MASK (0x3 << 14)
247#define RT5640_ADC_L_BST_SFT 14
248#define RT5640_ADC_R_BST_MASK (0x3 << 12)
249#define RT5640_ADC_R_BST_SFT 12
250#define RT5640_ADC_COMP_MASK (0x3 << 10)
251#define RT5640_ADC_COMP_SFT 10
252
253/* Stereo ADC Mixer Control (0x27) */
254#define RT5640_M_ADC_L1 (0x1 << 14)
255#define RT5640_M_ADC_L1_SFT 14
256#define RT5640_M_ADC_L2 (0x1 << 13)
257#define RT5640_M_ADC_L2_SFT 13
258#define RT5640_ADC_1_SRC_MASK (0x1 << 12)
259#define RT5640_ADC_1_SRC_SFT 12
260#define RT5640_ADC_1_SRC_ADC (0x1 << 12)
261#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
262#define RT5640_ADC_2_SRC_MASK (0x3 << 10)
263#define RT5640_ADC_2_SRC_SFT 10
264#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
265#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
266#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
267#define RT5640_M_ADC_R1 (0x1 << 6)
268#define RT5640_M_ADC_R1_SFT 6
269#define RT5640_M_ADC_R2 (0x1 << 5)
270#define RT5640_M_ADC_R2_SFT 5
271
272/* Mono ADC Mixer Control (0x28) */
273#define RT5640_M_MONO_ADC_L1 (0x1 << 14)
274#define RT5640_M_MONO_ADC_L1_SFT 14
275#define RT5640_M_MONO_ADC_L2 (0x1 << 13)
276#define RT5640_M_MONO_ADC_L2_SFT 13
277#define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
278#define RT5640_MONO_ADC_L1_SRC_SFT 12
279#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
280#define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
281#define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
282#define RT5640_MONO_ADC_L2_SRC_SFT 10
283#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
284#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
285#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
286#define RT5640_M_MONO_ADC_R1 (0x1 << 6)
287#define RT5640_M_MONO_ADC_R1_SFT 6
288#define RT5640_M_MONO_ADC_R2 (0x1 << 5)
289#define RT5640_M_MONO_ADC_R2_SFT 5
290#define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
291#define RT5640_MONO_ADC_R1_SRC_SFT 4
292#define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
293#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
294#define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2)
295#define RT5640_MONO_ADC_R2_SRC_SFT 2
296#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
297#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
298#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
299
300/* ADC Mixer to DAC Mixer Control (0x29) */
301#define RT5640_M_ADCMIX_L (0x1 << 15)
302#define RT5640_M_ADCMIX_L_SFT 15
303#define RT5640_M_IF1_DAC_L (0x1 << 14)
304#define RT5640_M_IF1_DAC_L_SFT 14
305#define RT5640_M_ADCMIX_R (0x1 << 7)
306#define RT5640_M_ADCMIX_R_SFT 7
307#define RT5640_M_IF1_DAC_R (0x1 << 6)
308#define RT5640_M_IF1_DAC_R_SFT 6
309
310/* Stereo DAC Mixer Control (0x2a) */
311#define RT5640_M_DAC_L1 (0x1 << 14)
312#define RT5640_M_DAC_L1_SFT 14
313#define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
314#define RT5640_DAC_L1_STO_L_VOL_SFT 13
315#define RT5640_M_DAC_L2 (0x1 << 12)
316#define RT5640_M_DAC_L2_SFT 12
317#define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
318#define RT5640_DAC_L2_STO_L_VOL_SFT 11
319#define RT5640_M_ANC_DAC_L (0x1 << 10)
320#define RT5640_M_ANC_DAC_L_SFT 10
321#define RT5640_M_DAC_R1 (0x1 << 6)
322#define RT5640_M_DAC_R1_SFT 6
323#define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
324#define RT5640_DAC_R1_STO_R_VOL_SFT 5
325#define RT5640_M_DAC_R2 (0x1 << 4)
326#define RT5640_M_DAC_R2_SFT 4
327#define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
328#define RT5640_DAC_R2_STO_R_VOL_SFT 3
329#define RT5640_M_ANC_DAC_R (0x1 << 2)
330#define RT5640_M_ANC_DAC_R_SFT 2
331
332/* Mono DAC Mixer Control (0x2b) */
333#define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
334#define RT5640_M_DAC_L1_MONO_L_SFT 14
335#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
336#define RT5640_DAC_L1_MONO_L_VOL_SFT 13
337#define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
338#define RT5640_M_DAC_L2_MONO_L_SFT 12
339#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
340#define RT5640_DAC_L2_MONO_L_VOL_SFT 11
341#define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
342#define RT5640_M_DAC_R2_MONO_L_SFT 10
343#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
344#define RT5640_DAC_R2_MONO_L_VOL_SFT 9
345#define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
346#define RT5640_M_DAC_R1_MONO_R_SFT 6
347#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
348#define RT5640_DAC_R1_MONO_R_VOL_SFT 5
349#define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
350#define RT5640_M_DAC_R2_MONO_R_SFT 4
351#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
352#define RT5640_DAC_R2_MONO_R_VOL_SFT 3
353#define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
354#define RT5640_M_DAC_L2_MONO_R_SFT 2
355#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
356#define RT5640_DAC_L2_MONO_R_VOL_SFT 1
357
358/* Digital Mixer Control (0x2c) */
359#define RT5640_M_STO_L_DAC_L (0x1 << 15)
360#define RT5640_M_STO_L_DAC_L_SFT 15
361#define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
362#define RT5640_STO_L_DAC_L_VOL_SFT 14
363#define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
364#define RT5640_M_DAC_L2_DAC_L_SFT 13
365#define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
366#define RT5640_DAC_L2_DAC_L_VOL_SFT 12
367#define RT5640_M_STO_R_DAC_R (0x1 << 11)
368#define RT5640_M_STO_R_DAC_R_SFT 11
369#define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
370#define RT5640_STO_R_DAC_R_VOL_SFT 10
371#define RT5640_M_DAC_R2_DAC_R (0x1 << 9)
372#define RT5640_M_DAC_R2_DAC_R_SFT 9
373#define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
374#define RT5640_DAC_R2_DAC_R_VOL_SFT 8
375
376/* DSP Path Control 1 (0x2d) */
377#define RT5640_RXDP_SRC_MASK (0x1 << 15)
378#define RT5640_RXDP_SRC_SFT 15
379#define RT5640_RXDP_SRC_NOR (0x0 << 15)
380#define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
381#define RT5640_TXDP_SRC_MASK (0x1 << 14)
382#define RT5640_TXDP_SRC_SFT 14
383#define RT5640_TXDP_SRC_NOR (0x0 << 14)
384#define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
385
386/* DSP Path Control 2 (0x2e) */
387#define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
388#define RT5640_DAC_L2_SEL_SFT 14
389#define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
390#define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
391#define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
392#define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
393#define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
394#define RT5640_DAC_R2_SEL_SFT 12
395#define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
396#define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
397#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
398#define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
399#define RT5640_IF2_ADC_L_SEL_SFT 11
400#define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
401#define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
402#define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
403#define RT5640_IF2_ADC_R_SEL_SFT 10
404#define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
405#define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
406#define RT5640_RXDC_SEL_MASK (0x3 << 8)
407#define RT5640_RXDC_SEL_SFT 8
408#define RT5640_RXDC_SEL_NOR (0x0 << 8)
409#define RT5640_RXDC_SEL_L2R (0x1 << 8)
410#define RT5640_RXDC_SEL_R2L (0x2 << 8)
411#define RT5640_RXDC_SEL_SWAP (0x3 << 8)
412#define RT5640_RXDP_SEL_MASK (0x3 << 6)
413#define RT5640_RXDP_SEL_SFT 6
414#define RT5640_RXDP_SEL_NOR (0x0 << 6)
415#define RT5640_RXDP_SEL_L2R (0x1 << 6)
416#define RT5640_RXDP_SEL_R2L (0x2 << 6)
417#define RT5640_RXDP_SEL_SWAP (0x3 << 6)
418#define RT5640_TXDC_SEL_MASK (0x3 << 4)
419#define RT5640_TXDC_SEL_SFT 4
420#define RT5640_TXDC_SEL_NOR (0x0 << 4)
421#define RT5640_TXDC_SEL_L2R (0x1 << 4)
422#define RT5640_TXDC_SEL_R2L (0x2 << 4)
423#define RT5640_TXDC_SEL_SWAP (0x3 << 4)
424#define RT5640_TXDP_SEL_MASK (0x3 << 2)
425#define RT5640_TXDP_SEL_SFT 2
426#define RT5640_TXDP_SEL_NOR (0x0 << 2)
427#define RT5640_TXDP_SEL_L2R (0x1 << 2)
428#define RT5640_TXDP_SEL_R2L (0x2 << 2)
429#define RT5640_TRXDP_SEL_SWAP (0x3 << 2)
430
431/* Digital Interface Data Control (0x2f) */
432#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
433#define RT5640_IF1_DAC_SEL_SFT 14
434#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
435#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)
436#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)
437#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)
438#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
439#define RT5640_IF1_ADC_SEL_SFT 12
440#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
441#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)
442#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)
443#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)
444#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
445#define RT5640_IF2_DAC_SEL_SFT 10
446#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
447#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)
448#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)
449#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)
450#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
451#define RT5640_IF2_ADC_SEL_SFT 8
452#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
453#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)
454#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)
455#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)
456#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
457#define RT5640_IF3_DAC_SEL_SFT 6
458#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
459#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)
460#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)
461#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)
462#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
463#define RT5640_IF3_ADC_SEL_SFT 4
464#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
465#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)
466#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)
467#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)
468
469/* REC Left Mixer Control 1 (0x3b) */
470#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
471#define RT5640_G_HP_L_RM_L_SFT 13
472#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
473#define RT5640_G_IN_L_RM_L_SFT 10
474#define RT5640_G_BST4_RM_L_MASK (0x7 << 7)
475#define RT5640_G_BST4_RM_L_SFT 7
476#define RT5640_G_BST3_RM_L_MASK (0x7 << 4)
477#define RT5640_G_BST3_RM_L_SFT 4
478#define RT5640_G_BST2_RM_L_MASK (0x7 << 1)
479#define RT5640_G_BST2_RM_L_SFT 1
480
481/* REC Left Mixer Control 2 (0x3c) */
482#define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
483#define RT5640_G_BST1_RM_L_SFT 13
484#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
485#define RT5640_G_OM_L_RM_L_SFT 10
486#define RT5640_M_HP_L_RM_L (0x1 << 6)
487#define RT5640_M_HP_L_RM_L_SFT 6
488#define RT5640_M_IN_L_RM_L (0x1 << 5)
489#define RT5640_M_IN_L_RM_L_SFT 5
490#define RT5640_M_BST4_RM_L (0x1 << 4)
491#define RT5640_M_BST4_RM_L_SFT 4
492#define RT5640_M_BST3_RM_L (0x1 << 3)
493#define RT5640_M_BST3_RM_L_SFT 3
494#define RT5640_M_BST2_RM_L (0x1 << 2)
495#define RT5640_M_BST2_RM_L_SFT 2
496#define RT5640_M_BST1_RM_L (0x1 << 1)
497#define RT5640_M_BST1_RM_L_SFT 1
498#define RT5640_M_OM_L_RM_L (0x1)
499#define RT5640_M_OM_L_RM_L_SFT 0
500
501/* REC Right Mixer Control 1 (0x3d) */
502#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
503#define RT5640_G_HP_R_RM_R_SFT 13
504#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
505#define RT5640_G_IN_R_RM_R_SFT 10
506#define RT5640_G_BST4_RM_R_MASK (0x7 << 7)
507#define RT5640_G_BST4_RM_R_SFT 7
508#define RT5640_G_BST3_RM_R_MASK (0x7 << 4)
509#define RT5640_G_BST3_RM_R_SFT 4
510#define RT5640_G_BST2_RM_R_MASK (0x7 << 1)
511#define RT5640_G_BST2_RM_R_SFT 1
512
513/* REC Right Mixer Control 2 (0x3e) */
514#define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
515#define RT5640_G_BST1_RM_R_SFT 13
516#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
517#define RT5640_G_OM_R_RM_R_SFT 10
518#define RT5640_M_HP_R_RM_R (0x1 << 6)
519#define RT5640_M_HP_R_RM_R_SFT 6
520#define RT5640_M_IN_R_RM_R (0x1 << 5)
521#define RT5640_M_IN_R_RM_R_SFT 5
522#define RT5640_M_BST4_RM_R (0x1 << 4)
523#define RT5640_M_BST4_RM_R_SFT 4
524#define RT5640_M_BST3_RM_R (0x1 << 3)
525#define RT5640_M_BST3_RM_R_SFT 3
526#define RT5640_M_BST2_RM_R (0x1 << 2)
527#define RT5640_M_BST2_RM_R_SFT 2
528#define RT5640_M_BST1_RM_R (0x1 << 1)
529#define RT5640_M_BST1_RM_R_SFT 1
530#define RT5640_M_OM_R_RM_R (0x1)
531#define RT5640_M_OM_R_RM_R_SFT 0
532
533/* HPMIX Control (0x45) */
534#define RT5640_M_DAC2_HM (0x1 << 15)
535#define RT5640_M_DAC2_HM_SFT 15
536#define RT5640_M_DAC1_HM (0x1 << 14)
537#define RT5640_M_DAC1_HM_SFT 14
538#define RT5640_M_HPVOL_HM (0x1 << 13)
539#define RT5640_M_HPVOL_HM_SFT 13
540#define RT5640_G_HPOMIX_MASK (0x1 << 12)
541#define RT5640_G_HPOMIX_SFT 12
542
543/* SPK Left Mixer Control (0x46) */
544#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
545#define RT5640_G_RM_L_SM_L_SFT 14
546#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
547#define RT5640_G_IN_L_SM_L_SFT 12
548#define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
549#define RT5640_G_DAC_L1_SM_L_SFT 10
550#define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
551#define RT5640_G_DAC_L2_SM_L_SFT 8
552#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
553#define RT5640_G_OM_L_SM_L_SFT 6
554#define RT5640_M_RM_L_SM_L (0x1 << 5)
555#define RT5640_M_RM_L_SM_L_SFT 5
556#define RT5640_M_IN_L_SM_L (0x1 << 4)
557#define RT5640_M_IN_L_SM_L_SFT 4
558#define RT5640_M_DAC_L1_SM_L (0x1 << 3)
559#define RT5640_M_DAC_L1_SM_L_SFT 3
560#define RT5640_M_DAC_L2_SM_L (0x1 << 2)
561#define RT5640_M_DAC_L2_SM_L_SFT 2
562#define RT5640_M_OM_L_SM_L (0x1 << 1)
563#define RT5640_M_OM_L_SM_L_SFT 1
564
565/* SPK Right Mixer Control (0x47) */
566#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
567#define RT5640_G_RM_R_SM_R_SFT 14
568#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
569#define RT5640_G_IN_R_SM_R_SFT 12
570#define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
571#define RT5640_G_DAC_R1_SM_R_SFT 10
572#define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
573#define RT5640_G_DAC_R2_SM_R_SFT 8
574#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
575#define RT5640_G_OM_R_SM_R_SFT 6
576#define RT5640_M_RM_R_SM_R (0x1 << 5)
577#define RT5640_M_RM_R_SM_R_SFT 5
578#define RT5640_M_IN_R_SM_R (0x1 << 4)
579#define RT5640_M_IN_R_SM_R_SFT 4
580#define RT5640_M_DAC_R1_SM_R (0x1 << 3)
581#define RT5640_M_DAC_R1_SM_R_SFT 3
582#define RT5640_M_DAC_R2_SM_R (0x1 << 2)
583#define RT5640_M_DAC_R2_SM_R_SFT 2
584#define RT5640_M_OM_R_SM_R (0x1 << 1)
585#define RT5640_M_OM_R_SM_R_SFT 1
586
587/* SPOLMIX Control (0x48) */
588#define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
589#define RT5640_M_DAC_R1_SPM_L_SFT 15
590#define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
591#define RT5640_M_DAC_L1_SPM_L_SFT 14
592#define RT5640_M_SV_R_SPM_L (0x1 << 13)
593#define RT5640_M_SV_R_SPM_L_SFT 13
594#define RT5640_M_SV_L_SPM_L (0x1 << 12)
595#define RT5640_M_SV_L_SPM_L_SFT 12
596#define RT5640_M_BST1_SPM_L (0x1 << 11)
597#define RT5640_M_BST1_SPM_L_SFT 11
598
599/* SPORMIX Control (0x49) */
600#define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
601#define RT5640_M_DAC_R1_SPM_R_SFT 13
602#define RT5640_M_SV_R_SPM_R (0x1 << 12)
603#define RT5640_M_SV_R_SPM_R_SFT 12
604#define RT5640_M_BST1_SPM_R (0x1 << 11)
605#define RT5640_M_BST1_SPM_R_SFT 11
606
607/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
608#define RT5640_SPO_CLSD_RATIO_MASK (0x7)
609#define RT5640_SPO_CLSD_RATIO_SFT 0
610
611/* Mono Output Mixer Control (0x4c) */
612#define RT5640_M_DAC_R2_MM (0x1 << 15)
613#define RT5640_M_DAC_R2_MM_SFT 15
614#define RT5640_M_DAC_L2_MM (0x1 << 14)
615#define RT5640_M_DAC_L2_MM_SFT 14
616#define RT5640_M_OV_R_MM (0x1 << 13)
617#define RT5640_M_OV_R_MM_SFT 13
618#define RT5640_M_OV_L_MM (0x1 << 12)
619#define RT5640_M_OV_L_MM_SFT 12
620#define RT5640_M_BST1_MM (0x1 << 11)
621#define RT5640_M_BST1_MM_SFT 11
622#define RT5640_G_MONOMIX_MASK (0x1 << 10)
623#define RT5640_G_MONOMIX_SFT 10
624
625/* Output Left Mixer Control 1 (0x4d) */
626#define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
627#define RT5640_G_BST3_OM_L_SFT 13
628#define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
629#define RT5640_G_BST2_OM_L_SFT 10
630#define RT5640_G_BST1_OM_L_MASK (0x7 << 7)
631#define RT5640_G_BST1_OM_L_SFT 7
632#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4)
633#define RT5640_G_IN_L_OM_L_SFT 4
634#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1)
635#define RT5640_G_RM_L_OM_L_SFT 1
636
637/* Output Left Mixer Control 2 (0x4e) */
638#define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13)
639#define RT5640_G_DAC_R2_OM_L_SFT 13
640#define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
641#define RT5640_G_DAC_L2_OM_L_SFT 10
642#define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7)
643#define RT5640_G_DAC_L1_OM_L_SFT 7
644
645/* Output Left Mixer Control 3 (0x4f) */
646#define RT5640_M_SM_L_OM_L (0x1 << 8)
647#define RT5640_M_SM_L_OM_L_SFT 8
648#define RT5640_M_BST3_OM_L (0x1 << 7)
649#define RT5640_M_BST3_OM_L_SFT 7
650#define RT5640_M_BST2_OM_L (0x1 << 6)
651#define RT5640_M_BST2_OM_L_SFT 6
652#define RT5640_M_BST1_OM_L (0x1 << 5)
653#define RT5640_M_BST1_OM_L_SFT 5
654#define RT5640_M_IN_L_OM_L (0x1 << 4)
655#define RT5640_M_IN_L_OM_L_SFT 4
656#define RT5640_M_RM_L_OM_L (0x1 << 3)
657#define RT5640_M_RM_L_OM_L_SFT 3
658#define RT5640_M_DAC_R2_OM_L (0x1 << 2)
659#define RT5640_M_DAC_R2_OM_L_SFT 2
660#define RT5640_M_DAC_L2_OM_L (0x1 << 1)
661#define RT5640_M_DAC_L2_OM_L_SFT 1
662#define RT5640_M_DAC_L1_OM_L (0x1)
663#define RT5640_M_DAC_L1_OM_L_SFT 0
664
665/* Output Right Mixer Control 1 (0x50) */
666#define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
667#define RT5640_G_BST4_OM_R_SFT 13
668#define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
669#define RT5640_G_BST2_OM_R_SFT 10
670#define RT5640_G_BST1_OM_R_MASK (0x7 << 7)
671#define RT5640_G_BST1_OM_R_SFT 7
672#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4)
673#define RT5640_G_IN_R_OM_R_SFT 4
674#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1)
675#define RT5640_G_RM_R_OM_R_SFT 1
676
677/* Output Right Mixer Control 2 (0x51) */
678#define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13)
679#define RT5640_G_DAC_L2_OM_R_SFT 13
680#define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
681#define RT5640_G_DAC_R2_OM_R_SFT 10
682#define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7)
683#define RT5640_G_DAC_R1_OM_R_SFT 7
684
685/* Output Right Mixer Control 3 (0x52) */
686#define RT5640_M_SM_L_OM_R (0x1 << 8)
687#define RT5640_M_SM_L_OM_R_SFT 8
688#define RT5640_M_BST4_OM_R (0x1 << 7)
689#define RT5640_M_BST4_OM_R_SFT 7
690#define RT5640_M_BST2_OM_R (0x1 << 6)
691#define RT5640_M_BST2_OM_R_SFT 6
692#define RT5640_M_BST1_OM_R (0x1 << 5)
693#define RT5640_M_BST1_OM_R_SFT 5
694#define RT5640_M_IN_R_OM_R (0x1 << 4)
695#define RT5640_M_IN_R_OM_R_SFT 4
696#define RT5640_M_RM_R_OM_R (0x1 << 3)
697#define RT5640_M_RM_R_OM_R_SFT 3
698#define RT5640_M_DAC_L2_OM_R (0x1 << 2)
699#define RT5640_M_DAC_L2_OM_R_SFT 2
700#define RT5640_M_DAC_R2_OM_R (0x1 << 1)
701#define RT5640_M_DAC_R2_OM_R_SFT 1
702#define RT5640_M_DAC_R1_OM_R (0x1)
703#define RT5640_M_DAC_R1_OM_R_SFT 0
704
705/* LOUT Mixer Control (0x53) */
706#define RT5640_M_DAC_L1_LM (0x1 << 15)
707#define RT5640_M_DAC_L1_LM_SFT 15
708#define RT5640_M_DAC_R1_LM (0x1 << 14)
709#define RT5640_M_DAC_R1_LM_SFT 14
710#define RT5640_M_OV_L_LM (0x1 << 13)
711#define RT5640_M_OV_L_LM_SFT 13
712#define RT5640_M_OV_R_LM (0x1 << 12)
713#define RT5640_M_OV_R_LM_SFT 12
714#define RT5640_G_LOUTMIX_MASK (0x1 << 11)
715#define RT5640_G_LOUTMIX_SFT 11
716
717/* Power Management for Digital 1 (0x61) */
718#define RT5640_PWR_I2S1 (0x1 << 15)
719#define RT5640_PWR_I2S1_BIT 15
720#define RT5640_PWR_I2S2 (0x1 << 14)
721#define RT5640_PWR_I2S2_BIT 14
722#define RT5640_PWR_I2S3 (0x1 << 13)
723#define RT5640_PWR_I2S3_BIT 13
724#define RT5640_PWR_DAC_L1 (0x1 << 12)
725#define RT5640_PWR_DAC_L1_BIT 12
726#define RT5640_PWR_DAC_R1 (0x1 << 11)
727#define RT5640_PWR_DAC_R1_BIT 11
728#define RT5640_PWR_DAC_L2 (0x1 << 7)
729#define RT5640_PWR_DAC_L2_BIT 7
730#define RT5640_PWR_DAC_R2 (0x1 << 6)
731#define RT5640_PWR_DAC_R2_BIT 6
732#define RT5640_PWR_ADC_L (0x1 << 2)
733#define RT5640_PWR_ADC_L_BIT 2
734#define RT5640_PWR_ADC_R (0x1 << 1)
735#define RT5640_PWR_ADC_R_BIT 1
736#define RT5640_PWR_CLS_D (0x1)
737#define RT5640_PWR_CLS_D_BIT 0
738
739/* Power Management for Digital 2 (0x62) */
740#define RT5640_PWR_ADC_SF (0x1 << 15)
741#define RT5640_PWR_ADC_SF_BIT 15
742#define RT5640_PWR_ADC_MF_L (0x1 << 14)
743#define RT5640_PWR_ADC_MF_L_BIT 14
744#define RT5640_PWR_ADC_MF_R (0x1 << 13)
745#define RT5640_PWR_ADC_MF_R_BIT 13
746#define RT5640_PWR_I2S_DSP (0x1 << 12)
747#define RT5640_PWR_I2S_DSP_BIT 12
748
749/* Power Management for Analog 1 (0x63) */
750#define RT5640_PWR_VREF1 (0x1 << 15)
751#define RT5640_PWR_VREF1_BIT 15
752#define RT5640_PWR_FV1 (0x1 << 14)
753#define RT5640_PWR_FV1_BIT 14
754#define RT5640_PWR_MB (0x1 << 13)
755#define RT5640_PWR_MB_BIT 13
756#define RT5640_PWR_LM (0x1 << 12)
757#define RT5640_PWR_LM_BIT 12
758#define RT5640_PWR_BG (0x1 << 11)
759#define RT5640_PWR_BG_BIT 11
760#define RT5640_PWR_MM (0x1 << 10)
761#define RT5640_PWR_MM_BIT 10
762#define RT5640_PWR_MA (0x1 << 8)
763#define RT5640_PWR_MA_BIT 8
764#define RT5640_PWR_HP_L (0x1 << 7)
765#define RT5640_PWR_HP_L_BIT 7
766#define RT5640_PWR_HP_R (0x1 << 6)
767#define RT5640_PWR_HP_R_BIT 6
768#define RT5640_PWR_HA (0x1 << 5)
769#define RT5640_PWR_HA_BIT 5
770#define RT5640_PWR_VREF2 (0x1 << 4)
771#define RT5640_PWR_VREF2_BIT 4
772#define RT5640_PWR_FV2 (0x1 << 3)
773#define RT5640_PWR_FV2_BIT 3
774#define RT5640_PWR_LDO2 (0x1 << 2)
775#define RT5640_PWR_LDO2_BIT 2
776
777/* Power Management for Analog 2 (0x64) */
778#define RT5640_PWR_BST1 (0x1 << 15)
779#define RT5640_PWR_BST1_BIT 15
780#define RT5640_PWR_BST2 (0x1 << 14)
781#define RT5640_PWR_BST2_BIT 14
782#define RT5640_PWR_BST3 (0x1 << 13)
783#define RT5640_PWR_BST3_BIT 13
784#define RT5640_PWR_BST4 (0x1 << 12)
785#define RT5640_PWR_BST4_BIT 12
786#define RT5640_PWR_MB1 (0x1 << 11)
787#define RT5640_PWR_MB1_BIT 11
788#define RT5640_PWR_MB2 (0x1 << 10)
789#define RT5640_PWR_MB2_BIT 10
790#define RT5640_PWR_PLL (0x1 << 9)
791#define RT5640_PWR_PLL_BIT 9
792
793/* Power Management for Mixer (0x65) */
794#define RT5640_PWR_OM_L (0x1 << 15)
795#define RT5640_PWR_OM_L_BIT 15
796#define RT5640_PWR_OM_R (0x1 << 14)
797#define RT5640_PWR_OM_R_BIT 14
798#define RT5640_PWR_SM_L (0x1 << 13)
799#define RT5640_PWR_SM_L_BIT 13
800#define RT5640_PWR_SM_R (0x1 << 12)
801#define RT5640_PWR_SM_R_BIT 12
802#define RT5640_PWR_RM_L (0x1 << 11)
803#define RT5640_PWR_RM_L_BIT 11
804#define RT5640_PWR_RM_R (0x1 << 10)
805#define RT5640_PWR_RM_R_BIT 10
806
807/* Power Management for Volume (0x66) */
808#define RT5640_PWR_SV_L (0x1 << 15)
809#define RT5640_PWR_SV_L_BIT 15
810#define RT5640_PWR_SV_R (0x1 << 14)
811#define RT5640_PWR_SV_R_BIT 14
812#define RT5640_PWR_OV_L (0x1 << 13)
813#define RT5640_PWR_OV_L_BIT 13
814#define RT5640_PWR_OV_R (0x1 << 12)
815#define RT5640_PWR_OV_R_BIT 12
816#define RT5640_PWR_HV_L (0x1 << 11)
817#define RT5640_PWR_HV_L_BIT 11
818#define RT5640_PWR_HV_R (0x1 << 10)
819#define RT5640_PWR_HV_R_BIT 10
820#define RT5640_PWR_IN_L (0x1 << 9)
821#define RT5640_PWR_IN_L_BIT 9
822#define RT5640_PWR_IN_R (0x1 << 8)
823#define RT5640_PWR_IN_R_BIT 8
824
825/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
826#define RT5640_I2S_MS_MASK (0x1 << 15)
827#define RT5640_I2S_MS_SFT 15
828#define RT5640_I2S_MS_M (0x0 << 15)
829#define RT5640_I2S_MS_S (0x1 << 15)
830#define RT5640_I2S_IF_MASK (0x7 << 12)
831#define RT5640_I2S_IF_SFT 12
832#define RT5640_I2S_O_CP_MASK (0x3 << 10)
833#define RT5640_I2S_O_CP_SFT 10
834#define RT5640_I2S_O_CP_OFF (0x0 << 10)
835#define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
836#define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
837#define RT5640_I2S_I_CP_MASK (0x3 << 8)
838#define RT5640_I2S_I_CP_SFT 8
839#define RT5640_I2S_I_CP_OFF (0x0 << 8)
840#define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
841#define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
842#define RT5640_I2S_BP_MASK (0x1 << 7)
843#define RT5640_I2S_BP_SFT 7
844#define RT5640_I2S_BP_NOR (0x0 << 7)
845#define RT5640_I2S_BP_INV (0x1 << 7)
846#define RT5640_I2S_DL_MASK (0x3 << 2)
847#define RT5640_I2S_DL_SFT 2
848#define RT5640_I2S_DL_16 (0x0 << 2)
849#define RT5640_I2S_DL_20 (0x1 << 2)
850#define RT5640_I2S_DL_24 (0x2 << 2)
851#define RT5640_I2S_DL_8 (0x3 << 2)
852#define RT5640_I2S_DF_MASK (0x3)
853#define RT5640_I2S_DF_SFT 0
854#define RT5640_I2S_DF_I2S (0x0)
855#define RT5640_I2S_DF_LEFT (0x1)
856#define RT5640_I2S_DF_PCM_A (0x2)
857#define RT5640_I2S_DF_PCM_B (0x3)
858
859/* I2S2 Audio Serial Data Port Control (0x71) */
860#define RT5640_I2S2_SDI_MASK (0x1 << 6)
861#define RT5640_I2S2_SDI_SFT 6
862#define RT5640_I2S2_SDI_I2S1 (0x0 << 6)
863#define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
864
865/* ADC/DAC Clock Control 1 (0x73) */
866#define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
867#define RT5640_I2S_BCLK_MS1_SFT 15
868#define RT5640_I2S_BCLK_MS1_32 (0x0 << 15)
869#define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
870#define RT5640_I2S_PD1_MASK (0x7 << 12)
871#define RT5640_I2S_PD1_SFT 12
872#define RT5640_I2S_PD1_1 (0x0 << 12)
873#define RT5640_I2S_PD1_2 (0x1 << 12)
874#define RT5640_I2S_PD1_3 (0x2 << 12)
875#define RT5640_I2S_PD1_4 (0x3 << 12)
876#define RT5640_I2S_PD1_6 (0x4 << 12)
877#define RT5640_I2S_PD1_8 (0x5 << 12)
878#define RT5640_I2S_PD1_12 (0x6 << 12)
879#define RT5640_I2S_PD1_16 (0x7 << 12)
880#define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
881#define RT5640_I2S_BCLK_MS2_SFT 11
882#define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
883#define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
884#define RT5640_I2S_PD2_MASK (0x7 << 8)
885#define RT5640_I2S_PD2_SFT 8
886#define RT5640_I2S_PD2_1 (0x0 << 8)
887#define RT5640_I2S_PD2_2 (0x1 << 8)
888#define RT5640_I2S_PD2_3 (0x2 << 8)
889#define RT5640_I2S_PD2_4 (0x3 << 8)
890#define RT5640_I2S_PD2_6 (0x4 << 8)
891#define RT5640_I2S_PD2_8 (0x5 << 8)
892#define RT5640_I2S_PD2_12 (0x6 << 8)
893#define RT5640_I2S_PD2_16 (0x7 << 8)
894#define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
895#define RT5640_I2S_BCLK_MS3_SFT 7
896#define RT5640_I2S_BCLK_MS3_32 (0x0 << 7)
897#define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
898#define RT5640_I2S_PD3_MASK (0x7 << 4)
899#define RT5640_I2S_PD3_SFT 4
900#define RT5640_I2S_PD3_1 (0x0 << 4)
901#define RT5640_I2S_PD3_2 (0x1 << 4)
902#define RT5640_I2S_PD3_3 (0x2 << 4)
903#define RT5640_I2S_PD3_4 (0x3 << 4)
904#define RT5640_I2S_PD3_6 (0x4 << 4)
905#define RT5640_I2S_PD3_8 (0x5 << 4)
906#define RT5640_I2S_PD3_12 (0x6 << 4)
907#define RT5640_I2S_PD3_16 (0x7 << 4)
908#define RT5640_DAC_OSR_MASK (0x3 << 2)
909#define RT5640_DAC_OSR_SFT 2
910#define RT5640_DAC_OSR_128 (0x0 << 2)
911#define RT5640_DAC_OSR_64 (0x1 << 2)
912#define RT5640_DAC_OSR_32 (0x2 << 2)
913#define RT5640_DAC_OSR_16 (0x3 << 2)
914#define RT5640_ADC_OSR_MASK (0x3)
915#define RT5640_ADC_OSR_SFT 0
916#define RT5640_ADC_OSR_128 (0x0)
917#define RT5640_ADC_OSR_64 (0x1)
918#define RT5640_ADC_OSR_32 (0x2)
919#define RT5640_ADC_OSR_16 (0x3)
920
921/* ADC/DAC Clock Control 2 (0x74) */
922#define RT5640_DAC_L_OSR_MASK (0x3 << 14)
923#define RT5640_DAC_L_OSR_SFT 14
924#define RT5640_DAC_L_OSR_128 (0x0 << 14)
925#define RT5640_DAC_L_OSR_64 (0x1 << 14)
926#define RT5640_DAC_L_OSR_32 (0x2 << 14)
927#define RT5640_DAC_L_OSR_16 (0x3 << 14)
928#define RT5640_ADC_R_OSR_MASK (0x3 << 12)
929#define RT5640_ADC_R_OSR_SFT 12
930#define RT5640_ADC_R_OSR_128 (0x0 << 12)
931#define RT5640_ADC_R_OSR_64 (0x1 << 12)
932#define RT5640_ADC_R_OSR_32 (0x2 << 12)
933#define RT5640_ADC_R_OSR_16 (0x3 << 12)
934#define RT5640_DAHPF_EN (0x1 << 11)
935#define RT5640_DAHPF_EN_SFT 11
936#define RT5640_ADHPF_EN (0x1 << 10)
937#define RT5640_ADHPF_EN_SFT 10
938
939/* Digital Microphone Control (0x75) */
940#define RT5640_DMIC_1_EN_MASK (0x1 << 15)
941#define RT5640_DMIC_1_EN_SFT 15
942#define RT5640_DMIC_1_DIS (0x0 << 15)
943#define RT5640_DMIC_1_EN (0x1 << 15)
944#define RT5640_DMIC_2_EN_MASK (0x1 << 14)
945#define RT5640_DMIC_2_EN_SFT 14
946#define RT5640_DMIC_2_DIS (0x0 << 14)
947#define RT5640_DMIC_2_EN (0x1 << 14)
948#define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
949#define RT5640_DMIC_1L_LH_SFT 13
950#define RT5640_DMIC_1L_LH_FALLING (0x0 << 13)
951#define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
952#define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
953#define RT5640_DMIC_1R_LH_SFT 12
954#define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
955#define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
956#define RT5640_DMIC_1_DP_MASK (0x1 << 11)
957#define RT5640_DMIC_1_DP_SFT 11
958#define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
959#define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
960#define RT5640_DMIC_2_DP_MASK (0x1 << 10)
961#define RT5640_DMIC_2_DP_SFT 10
962#define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
963#define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
964#define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
965#define RT5640_DMIC_2L_LH_SFT 9
966#define RT5640_DMIC_2L_LH_FALLING (0x0 << 9)
967#define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
968#define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
969#define RT5640_DMIC_2R_LH_SFT 8
970#define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
971#define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
972#define RT5640_DMIC_CLK_MASK (0x7 << 5)
973#define RT5640_DMIC_CLK_SFT 5
974
975/* Global Clock Control (0x80) */
976#define RT5640_SCLK_SRC_MASK (0x3 << 14)
977#define RT5640_SCLK_SRC_SFT 14
978#define RT5640_SCLK_SRC_MCLK (0x0 << 14)
979#define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
980#define RT5640_SCLK_SRC_PLL1T (0x2 << 14)
981#define RT5640_SCLK_SRC_RCCLK (0x3 << 14) /* 15MHz */
982#define RT5640_PLL1_SRC_MASK (0x3 << 12)
983#define RT5640_PLL1_SRC_SFT 12
984#define RT5640_PLL1_SRC_MCLK (0x0 << 12)
985#define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
986#define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
987#define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
988#define RT5640_PLL1_PD_MASK (0x1 << 3)
989#define RT5640_PLL1_PD_SFT 3
990#define RT5640_PLL1_PD_1 (0x0 << 3)
991#define RT5640_PLL1_PD_2 (0x1 << 3)
992
993#define RT5640_PLL_INP_MAX 40000000
994#define RT5640_PLL_INP_MIN 256000
995/* PLL M/N/K Code Control 1 (0x81) */
996#define RT5640_PLL_N_MAX 0x1ff
997#define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7)
998#define RT5640_PLL_N_SFT 7
999#define RT5640_PLL_K_MAX 0x1f
1000#define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX)
1001#define RT5640_PLL_K_SFT 0
1002
1003/* PLL M/N/K Code Control 2 (0x82) */
1004#define RT5640_PLL_M_MAX 0xf
1005#define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1006#define RT5640_PLL_M_SFT 12
1007#define RT5640_PLL_M_BP (0x1 << 11)
1008#define RT5640_PLL_M_BP_SFT 11
1009
1010/* ASRC Control 1 (0x83) */
1011#define RT5640_STO_T_MASK (0x1 << 15)
1012#define RT5640_STO_T_SFT 15
1013#define RT5640_STO_T_SCLK (0x0 << 15)
1014#define RT5640_STO_T_LRCK1 (0x1 << 15)
1015#define RT5640_M1_T_MASK (0x1 << 14)
1016#define RT5640_M1_T_SFT 14
1017#define RT5640_M1_T_I2S2 (0x0 << 14)
1018#define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1019#define RT5640_I2S2_F_MASK (0x1 << 12)
1020#define RT5640_I2S2_F_SFT 12
1021#define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1022#define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1023#define RT5640_DMIC_1_M_MASK (0x1 << 9)
1024#define RT5640_DMIC_1_M_SFT 9
1025#define RT5640_DMIC_1_M_NOR (0x0 << 9)
1026#define RT5640_DMIC_1_M_ASYN (0x1 << 9)
1027#define RT5640_DMIC_2_M_MASK (0x1 << 8)
1028#define RT5640_DMIC_2_M_SFT 8
1029#define RT5640_DMIC_2_M_NOR (0x0 << 8)
1030#define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1031
1032/* ASRC Control 2 (0x84) */
1033#define RT5640_MDA_L_M_MASK (0x1 << 15)
1034#define RT5640_MDA_L_M_SFT 15
1035#define RT5640_MDA_L_M_NOR (0x0 << 15)
1036#define RT5640_MDA_L_M_ASYN (0x1 << 15)
1037#define RT5640_MDA_R_M_MASK (0x1 << 14)
1038#define RT5640_MDA_R_M_SFT 14
1039#define RT5640_MDA_R_M_NOR (0x0 << 14)
1040#define RT5640_MDA_R_M_ASYN (0x1 << 14)
1041#define RT5640_MAD_L_M_MASK (0x1 << 13)
1042#define RT5640_MAD_L_M_SFT 13
1043#define RT5640_MAD_L_M_NOR (0x0 << 13)
1044#define RT5640_MAD_L_M_ASYN (0x1 << 13)
1045#define RT5640_MAD_R_M_MASK (0x1 << 12)
1046#define RT5640_MAD_R_M_SFT 12
1047#define RT5640_MAD_R_M_NOR (0x0 << 12)
1048#define RT5640_MAD_R_M_ASYN (0x1 << 12)
1049#define RT5640_ADC_M_MASK (0x1 << 11)
1050#define RT5640_ADC_M_SFT 11
1051#define RT5640_ADC_M_NOR (0x0 << 11)
1052#define RT5640_ADC_M_ASYN (0x1 << 11)
1053#define RT5640_STO_DAC_M_MASK (0x1 << 5)
1054#define RT5640_STO_DAC_M_SFT 5
1055#define RT5640_STO_DAC_M_NOR (0x0 << 5)
1056#define RT5640_STO_DAC_M_ASYN (0x1 << 5)
1057#define RT5640_I2S1_R_D_MASK (0x1 << 4)
1058#define RT5640_I2S1_R_D_SFT 4
1059#define RT5640_I2S1_R_D_DIS (0x0 << 4)
1060#define RT5640_I2S1_R_D_EN (0x1 << 4)
1061#define RT5640_I2S2_R_D_MASK (0x1 << 3)
1062#define RT5640_I2S2_R_D_SFT 3
1063#define RT5640_I2S2_R_D_DIS (0x0 << 3)
1064#define RT5640_I2S2_R_D_EN (0x1 << 3)
1065#define RT5640_PRE_SCLK_MASK (0x3)
1066#define RT5640_PRE_SCLK_SFT 0
1067#define RT5640_PRE_SCLK_512 (0x0)
1068#define RT5640_PRE_SCLK_1024 (0x1)
1069#define RT5640_PRE_SCLK_2048 (0x2)
1070
1071/* ASRC Control 3 (0x85) */
1072#define RT5640_I2S1_RATE_MASK (0xf << 12)
1073#define RT5640_I2S1_RATE_SFT 12
1074#define RT5640_I2S2_RATE_MASK (0xf << 8)
1075#define RT5640_I2S2_RATE_SFT 8
1076
1077/* ASRC Control 4 (0x89) */
1078#define RT5640_I2S1_PD_MASK (0x7 << 12)
1079#define RT5640_I2S1_PD_SFT 12
1080#define RT5640_I2S2_PD_MASK (0x7 << 8)
1081#define RT5640_I2S2_PD_SFT 8
1082
1083/* HPOUT Over Current Detection (0x8b) */
1084#define RT5640_HP_OVCD_MASK (0x1 << 10)
1085#define RT5640_HP_OVCD_SFT 10
1086#define RT5640_HP_OVCD_DIS (0x0 << 10)
1087#define RT5640_HP_OVCD_EN (0x1 << 10)
1088#define RT5640_HP_OC_TH_MASK (0x3 << 8)
1089#define RT5640_HP_OC_TH_SFT 8
1090#define RT5640_HP_OC_TH_90 (0x0 << 8)
1091#define RT5640_HP_OC_TH_105 (0x1 << 8)
1092#define RT5640_HP_OC_TH_120 (0x2 << 8)
1093#define RT5640_HP_OC_TH_135 (0x3 << 8)
1094
1095/* Class D Over Current Control (0x8c) */
1096#define RT5640_CLSD_OC_MASK (0x1 << 9)
1097#define RT5640_CLSD_OC_SFT 9
1098#define RT5640_CLSD_OC_PU (0x0 << 9)
1099#define RT5640_CLSD_OC_PD (0x1 << 9)
1100#define RT5640_AUTO_PD_MASK (0x1 << 8)
1101#define RT5640_AUTO_PD_SFT 8
1102#define RT5640_AUTO_PD_DIS (0x0 << 8)
1103#define RT5640_AUTO_PD_EN (0x1 << 8)
1104#define RT5640_CLSD_OC_TH_MASK (0x3f)
1105#define RT5640_CLSD_OC_TH_SFT 0
1106
1107/* Class D Output Control (0x8d) */
1108#define RT5640_CLSD_RATIO_MASK (0xf << 12)
1109#define RT5640_CLSD_RATIO_SFT 12
1110#define RT5640_CLSD_OM_MASK (0x1 << 11)
1111#define RT5640_CLSD_OM_SFT 11
1112#define RT5640_CLSD_OM_MONO (0x0 << 11)
1113#define RT5640_CLSD_OM_STO (0x1 << 11)
1114#define RT5640_CLSD_SCH_MASK (0x1 << 10)
1115#define RT5640_CLSD_SCH_SFT 10
1116#define RT5640_CLSD_SCH_L (0x0 << 10)
1117#define RT5640_CLSD_SCH_S (0x1 << 10)
1118
1119/* Depop Mode Control 1 (0x8e) */
1120#define RT5640_SMT_TRIG_MASK (0x1 << 15)
1121#define RT5640_SMT_TRIG_SFT 15
1122#define RT5640_SMT_TRIG_DIS (0x0 << 15)
1123#define RT5640_SMT_TRIG_EN (0x1 << 15)
1124#define RT5640_HP_L_SMT_MASK (0x1 << 9)
1125#define RT5640_HP_L_SMT_SFT 9
1126#define RT5640_HP_L_SMT_DIS (0x0 << 9)
1127#define RT5640_HP_L_SMT_EN (0x1 << 9)
1128#define RT5640_HP_R_SMT_MASK (0x1 << 8)
1129#define RT5640_HP_R_SMT_SFT 8
1130#define RT5640_HP_R_SMT_DIS (0x0 << 8)
1131#define RT5640_HP_R_SMT_EN (0x1 << 8)
1132#define RT5640_HP_CD_PD_MASK (0x1 << 7)
1133#define RT5640_HP_CD_PD_SFT 7
1134#define RT5640_HP_CD_PD_DIS (0x0 << 7)
1135#define RT5640_HP_CD_PD_EN (0x1 << 7)
1136#define RT5640_RSTN_MASK (0x1 << 6)
1137#define RT5640_RSTN_SFT 6
1138#define RT5640_RSTN_DIS (0x0 << 6)
1139#define RT5640_RSTN_EN (0x1 << 6)
1140#define RT5640_RSTP_MASK (0x1 << 5)
1141#define RT5640_RSTP_SFT 5
1142#define RT5640_RSTP_DIS (0x0 << 5)
1143#define RT5640_RSTP_EN (0x1 << 5)
1144#define RT5640_HP_CO_MASK (0x1 << 4)
1145#define RT5640_HP_CO_SFT 4
1146#define RT5640_HP_CO_DIS (0x0 << 4)
1147#define RT5640_HP_CO_EN (0x1 << 4)
1148#define RT5640_HP_CP_MASK (0x1 << 3)
1149#define RT5640_HP_CP_SFT 3
1150#define RT5640_HP_CP_PD (0x0 << 3)
1151#define RT5640_HP_CP_PU (0x1 << 3)
1152#define RT5640_HP_SG_MASK (0x1 << 2)
1153#define RT5640_HP_SG_SFT 2
1154#define RT5640_HP_SG_DIS (0x0 << 2)
1155#define RT5640_HP_SG_EN (0x1 << 2)
1156#define RT5640_HP_DP_MASK (0x1 << 1)
1157#define RT5640_HP_DP_SFT 1
1158#define RT5640_HP_DP_PD (0x0 << 1)
1159#define RT5640_HP_DP_PU (0x1 << 1)
1160#define RT5640_HP_CB_MASK (0x1)
1161#define RT5640_HP_CB_SFT 0
1162#define RT5640_HP_CB_PD (0x0)
1163#define RT5640_HP_CB_PU (0x1)
1164
1165/* Depop Mode Control 2 (0x8f) */
1166#define RT5640_DEPOP_MASK (0x1 << 13)
1167#define RT5640_DEPOP_SFT 13
1168#define RT5640_DEPOP_AUTO (0x0 << 13)
1169#define RT5640_DEPOP_MAN (0x1 << 13)
1170#define RT5640_RAMP_MASK (0x1 << 12)
1171#define RT5640_RAMP_SFT 12
1172#define RT5640_RAMP_DIS (0x0 << 12)
1173#define RT5640_RAMP_EN (0x1 << 12)
1174#define RT5640_BPS_MASK (0x1 << 11)
1175#define RT5640_BPS_SFT 11
1176#define RT5640_BPS_DIS (0x0 << 11)
1177#define RT5640_BPS_EN (0x1 << 11)
1178#define RT5640_FAST_UPDN_MASK (0x1 << 10)
1179#define RT5640_FAST_UPDN_SFT 10
1180#define RT5640_FAST_UPDN_DIS (0x0 << 10)
1181#define RT5640_FAST_UPDN_EN (0x1 << 10)
1182#define RT5640_MRES_MASK (0x3 << 8)
1183#define RT5640_MRES_SFT 8
1184#define RT5640_MRES_15MO (0x0 << 8)
1185#define RT5640_MRES_25MO (0x1 << 8)
1186#define RT5640_MRES_35MO (0x2 << 8)
1187#define RT5640_MRES_45MO (0x3 << 8)
1188#define RT5640_VLO_MASK (0x1 << 7)
1189#define RT5640_VLO_SFT 7
1190#define RT5640_VLO_3V (0x0 << 7)
1191#define RT5640_VLO_32V (0x1 << 7)
1192#define RT5640_DIG_DP_MASK (0x1 << 6)
1193#define RT5640_DIG_DP_SFT 6
1194#define RT5640_DIG_DP_DIS (0x0 << 6)
1195#define RT5640_DIG_DP_EN (0x1 << 6)
1196#define RT5640_DP_TH_MASK (0x3 << 4)
1197#define RT5640_DP_TH_SFT 4
1198
1199/* Depop Mode Control 3 (0x90) */
1200#define RT5640_CP_SYS_MASK (0x7 << 12)
1201#define RT5640_CP_SYS_SFT 12
1202#define RT5640_CP_FQ1_MASK (0x7 << 8)
1203#define RT5640_CP_FQ1_SFT 8
1204#define RT5640_CP_FQ2_MASK (0x7 << 4)
1205#define RT5640_CP_FQ2_SFT 4
1206#define RT5640_CP_FQ3_MASK (0x7)
1207#define RT5640_CP_FQ3_SFT 0
1208
1209/* HPOUT charge pump (0x91) */
1210#define RT5640_OSW_L_MASK (0x1 << 11)
1211#define RT5640_OSW_L_SFT 11
1212#define RT5640_OSW_L_DIS (0x0 << 11)
1213#define RT5640_OSW_L_EN (0x1 << 11)
1214#define RT5640_OSW_R_MASK (0x1 << 10)
1215#define RT5640_OSW_R_SFT 10
1216#define RT5640_OSW_R_DIS (0x0 << 10)
1217#define RT5640_OSW_R_EN (0x1 << 10)
1218#define RT5640_PM_HP_MASK (0x3 << 8)
1219#define RT5640_PM_HP_SFT 8
1220#define RT5640_PM_HP_LV (0x0 << 8)
1221#define RT5640_PM_HP_MV (0x1 << 8)
1222#define RT5640_PM_HP_HV (0x2 << 8)
1223#define RT5640_IB_HP_MASK (0x3 << 6)
1224#define RT5640_IB_HP_SFT 6
1225#define RT5640_IB_HP_125IL (0x0 << 6)
1226#define RT5640_IB_HP_25IL (0x1 << 6)
1227#define RT5640_IB_HP_5IL (0x2 << 6)
1228#define RT5640_IB_HP_1IL (0x3 << 6)
1229
1230/* PV detection and SPK gain control (0x92) */
1231#define RT5640_PVDD_DET_MASK (0x1 << 15)
1232#define RT5640_PVDD_DET_SFT 15
1233#define RT5640_PVDD_DET_DIS (0x0 << 15)
1234#define RT5640_PVDD_DET_EN (0x1 << 15)
1235#define RT5640_SPK_AG_MASK (0x1 << 14)
1236#define RT5640_SPK_AG_SFT 14
1237#define RT5640_SPK_AG_DIS (0x0 << 14)
1238#define RT5640_SPK_AG_EN (0x1 << 14)
1239
1240/* Micbias Control (0x93) */
1241#define RT5640_MIC1_BS_MASK (0x1 << 15)
1242#define RT5640_MIC1_BS_SFT 15
1243#define RT5640_MIC1_BS_9AV (0x0 << 15)
1244#define RT5640_MIC1_BS_75AV (0x1 << 15)
1245#define RT5640_MIC2_BS_MASK (0x1 << 14)
1246#define RT5640_MIC2_BS_SFT 14
1247#define RT5640_MIC2_BS_9AV (0x0 << 14)
1248#define RT5640_MIC2_BS_75AV (0x1 << 14)
1249#define RT5640_MIC1_CLK_MASK (0x1 << 13)
1250#define RT5640_MIC1_CLK_SFT 13
1251#define RT5640_MIC1_CLK_DIS (0x0 << 13)
1252#define RT5640_MIC1_CLK_EN (0x1 << 13)
1253#define RT5640_MIC2_CLK_MASK (0x1 << 12)
1254#define RT5640_MIC2_CLK_SFT 12
1255#define RT5640_MIC2_CLK_DIS (0x0 << 12)
1256#define RT5640_MIC2_CLK_EN (0x1 << 12)
1257#define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1258#define RT5640_MIC1_OVCD_SFT 11
1259#define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1260#define RT5640_MIC1_OVCD_EN (0x1 << 11)
1261#define RT5640_MIC1_OVTH_MASK (0x3 << 9)
1262#define RT5640_MIC1_OVTH_SFT 9
1263#define RT5640_MIC1_OVTH_600UA (0x0 << 9)
1264#define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
1265#define RT5640_MIC1_OVTH_2000UA (0x2 << 9)
1266#define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1267#define RT5640_MIC2_OVCD_SFT 8
1268#define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1269#define RT5640_MIC2_OVCD_EN (0x1 << 8)
1270#define RT5640_MIC2_OVTH_MASK (0x3 << 6)
1271#define RT5640_MIC2_OVTH_SFT 6
1272#define RT5640_MIC2_OVTH_600UA (0x0 << 6)
1273#define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1274#define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
1275#define RT5640_PWR_MB_MASK (0x1 << 5)
1276#define RT5640_PWR_MB_SFT 5
1277#define RT5640_PWR_MB_PD (0x0 << 5)
1278#define RT5640_PWR_MB_PU (0x1 << 5)
1279#define RT5640_PWR_CLK25M_MASK (0x1 << 4)
1280#define RT5640_PWR_CLK25M_SFT 4
1281#define RT5640_PWR_CLK25M_PD (0x0 << 4)
1282#define RT5640_PWR_CLK25M_PU (0x1 << 4)
1283
1284/* EQ Control 1 (0xb0) */
1285#define RT5640_EQ_SRC_MASK (0x1 << 15)
1286#define RT5640_EQ_SRC_SFT 15
1287#define RT5640_EQ_SRC_DAC (0x0 << 15)
1288#define RT5640_EQ_SRC_ADC (0x1 << 15)
1289#define RT5640_EQ_UPD (0x1 << 14)
1290#define RT5640_EQ_UPD_BIT 14
1291#define RT5640_EQ_CD_MASK (0x1 << 13)
1292#define RT5640_EQ_CD_SFT 13
1293#define RT5640_EQ_CD_DIS (0x0 << 13)
1294#define RT5640_EQ_CD_EN (0x1 << 13)
1295#define RT5640_EQ_DITH_MASK (0x3 << 8)
1296#define RT5640_EQ_DITH_SFT 8
1297#define RT5640_EQ_DITH_NOR (0x0 << 8)
1298#define RT5640_EQ_DITH_LSB (0x1 << 8)
1299#define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1300#define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1301
1302/* EQ Control 2 (0xb1) */
1303#define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1304#define RT5640_EQ_HPF1_M_SFT 8
1305#define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1306#define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1307#define RT5640_EQ_LPF1_M_MASK (0x1 << 7)
1308#define RT5640_EQ_LPF1_M_SFT 7
1309#define RT5640_EQ_LPF1_M_LO (0x0 << 7)
1310#define RT5640_EQ_LPF1_M_1ST (0x1 << 7)
1311#define RT5640_EQ_HPF2_MASK (0x1 << 6)
1312#define RT5640_EQ_HPF2_SFT 6
1313#define RT5640_EQ_HPF2_DIS (0x0 << 6)
1314#define RT5640_EQ_HPF2_EN (0x1 << 6)
1315#define RT5640_EQ_HPF1_MASK (0x1 << 5)
1316#define RT5640_EQ_HPF1_SFT 5
1317#define RT5640_EQ_HPF1_DIS (0x0 << 5)
1318#define RT5640_EQ_HPF1_EN (0x1 << 5)
1319#define RT5640_EQ_BPF4_MASK (0x1 << 4)
1320#define RT5640_EQ_BPF4_SFT 4
1321#define RT5640_EQ_BPF4_DIS (0x0 << 4)
1322#define RT5640_EQ_BPF4_EN (0x1 << 4)
1323#define RT5640_EQ_BPF3_MASK (0x1 << 3)
1324#define RT5640_EQ_BPF3_SFT 3
1325#define RT5640_EQ_BPF3_DIS (0x0 << 3)
1326#define RT5640_EQ_BPF3_EN (0x1 << 3)
1327#define RT5640_EQ_BPF2_MASK (0x1 << 2)
1328#define RT5640_EQ_BPF2_SFT 2
1329#define RT5640_EQ_BPF2_DIS (0x0 << 2)
1330#define RT5640_EQ_BPF2_EN (0x1 << 2)
1331#define RT5640_EQ_BPF1_MASK (0x1 << 1)
1332#define RT5640_EQ_BPF1_SFT 1
1333#define RT5640_EQ_BPF1_DIS (0x0 << 1)
1334#define RT5640_EQ_BPF1_EN (0x1 << 1)
1335#define RT5640_EQ_LPF_MASK (0x1)
1336#define RT5640_EQ_LPF_SFT 0
1337#define RT5640_EQ_LPF_DIS (0x0)
1338#define RT5640_EQ_LPF_EN (0x1)
1339
1340/* Memory Test (0xb2) */
1341#define RT5640_MT_MASK (0x1 << 15)
1342#define RT5640_MT_SFT 15
1343#define RT5640_MT_DIS (0x0 << 15)
1344#define RT5640_MT_EN (0x1 << 15)
1345
1346/* DRC/AGC Control 1 (0xb4) */
1347#define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1348#define RT5640_DRC_AGC_P_SFT 15
1349#define RT5640_DRC_AGC_P_DAC (0x0 << 15)
1350#define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1351#define RT5640_DRC_AGC_MASK (0x1 << 14)
1352#define RT5640_DRC_AGC_SFT 14
1353#define RT5640_DRC_AGC_DIS (0x0 << 14)
1354#define RT5640_DRC_AGC_EN (0x1 << 14)
1355#define RT5640_DRC_AGC_UPD (0x1 << 13)
1356#define RT5640_DRC_AGC_UPD_BIT 13
1357#define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1358#define RT5640_DRC_AGC_AR_SFT 8
1359#define RT5640_DRC_AGC_R_MASK (0x7 << 5)
1360#define RT5640_DRC_AGC_R_SFT 5
1361#define RT5640_DRC_AGC_R_48K (0x1 << 5)
1362#define RT5640_DRC_AGC_R_96K (0x2 << 5)
1363#define RT5640_DRC_AGC_R_192K (0x3 << 5)
1364#define RT5640_DRC_AGC_R_441K (0x5 << 5)
1365#define RT5640_DRC_AGC_R_882K (0x6 << 5)
1366#define RT5640_DRC_AGC_R_1764K (0x7 << 5)
1367#define RT5640_DRC_AGC_RC_MASK (0x1f)
1368#define RT5640_DRC_AGC_RC_SFT 0
1369
1370/* DRC/AGC Control 2 (0xb5) */
1371#define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1372#define RT5640_DRC_AGC_POB_SFT 8
1373#define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
1374#define RT5640_DRC_AGC_CP_SFT 7
1375#define RT5640_DRC_AGC_CP_DIS (0x0 << 7)
1376#define RT5640_DRC_AGC_CP_EN (0x1 << 7)
1377#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5)
1378#define RT5640_DRC_AGC_CPR_SFT 5
1379#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5)
1380#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
1381#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5)
1382#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5)
1383#define RT5640_DRC_AGC_PRB_MASK (0x1f)
1384#define RT5640_DRC_AGC_PRB_SFT 0
1385
1386/* DRC/AGC Control 3 (0xb6) */
1387#define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1388#define RT5640_DRC_AGC_NGB_SFT 12
1389#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7)
1390#define RT5640_DRC_AGC_TAR_SFT 7
1391#define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1392#define RT5640_DRC_AGC_NG_SFT 6
1393#define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
1394#define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1395#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
1396#define RT5640_DRC_AGC_NGH_SFT 5
1397#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5)
1398#define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
1399#define RT5640_DRC_AGC_NGT_MASK (0x1f)
1400#define RT5640_DRC_AGC_NGT_SFT 0
1401
1402/* ANC Control 1 (0xb8) */
1403#define RT5640_ANC_M_MASK (0x1 << 15)
1404#define RT5640_ANC_M_SFT 15
1405#define RT5640_ANC_M_NOR (0x0 << 15)
1406#define RT5640_ANC_M_REV (0x1 << 15)
1407#define RT5640_ANC_MASK (0x1 << 14)
1408#define RT5640_ANC_SFT 14
1409#define RT5640_ANC_DIS (0x0 << 14)
1410#define RT5640_ANC_EN (0x1 << 14)
1411#define RT5640_ANC_MD_MASK (0x3 << 12)
1412#define RT5640_ANC_MD_SFT 12
1413#define RT5640_ANC_MD_DIS (0x0 << 12)
1414#define RT5640_ANC_MD_67MS (0x1 << 12)
1415#define RT5640_ANC_MD_267MS (0x2 << 12)
1416#define RT5640_ANC_MD_1067MS (0x3 << 12)
1417#define RT5640_ANC_SN_MASK (0x1 << 11)
1418#define RT5640_ANC_SN_SFT 11
1419#define RT5640_ANC_SN_DIS (0x0 << 11)
1420#define RT5640_ANC_SN_EN (0x1 << 11)
1421#define RT5640_ANC_CLK_MASK (0x1 << 10)
1422#define RT5640_ANC_CLK_SFT 10
1423#define RT5640_ANC_CLK_ANC (0x0 << 10)
1424#define RT5640_ANC_CLK_REG (0x1 << 10)
1425#define RT5640_ANC_ZCD_MASK (0x3 << 8)
1426#define RT5640_ANC_ZCD_SFT 8
1427#define RT5640_ANC_ZCD_DIS (0x0 << 8)
1428#define RT5640_ANC_ZCD_T1 (0x1 << 8)
1429#define RT5640_ANC_ZCD_T2 (0x2 << 8)
1430#define RT5640_ANC_ZCD_WT (0x3 << 8)
1431#define RT5640_ANC_CS_MASK (0x1 << 7)
1432#define RT5640_ANC_CS_SFT 7
1433#define RT5640_ANC_CS_DIS (0x0 << 7)
1434#define RT5640_ANC_CS_EN (0x1 << 7)
1435#define RT5640_ANC_SW_MASK (0x1 << 6)
1436#define RT5640_ANC_SW_SFT 6
1437#define RT5640_ANC_SW_NOR (0x0 << 6)
1438#define RT5640_ANC_SW_AUTO (0x1 << 6)
1439#define RT5640_ANC_CO_L_MASK (0x3f)
1440#define RT5640_ANC_CO_L_SFT 0
1441
1442/* ANC Control 2 (0xb6) */
1443#define RT5640_ANC_FG_R_MASK (0xf << 12)
1444#define RT5640_ANC_FG_R_SFT 12
1445#define RT5640_ANC_FG_L_MASK (0xf << 8)
1446#define RT5640_ANC_FG_L_SFT 8
1447#define RT5640_ANC_CG_R_MASK (0xf << 4)
1448#define RT5640_ANC_CG_R_SFT 4
1449#define RT5640_ANC_CG_L_MASK (0xf)
1450#define RT5640_ANC_CG_L_SFT 0
1451
1452/* ANC Control 3 (0xb6) */
1453#define RT5640_ANC_CD_MASK (0x1 << 6)
1454#define RT5640_ANC_CD_SFT 6
1455#define RT5640_ANC_CD_BOTH (0x0 << 6)
1456#define RT5640_ANC_CD_IND (0x1 << 6)
1457#define RT5640_ANC_CO_R_MASK (0x3f)
1458#define RT5640_ANC_CO_R_SFT 0
1459
1460/* Jack Detect Control (0xbb) */
1461#define RT5640_JD_MASK (0x7 << 13)
1462#define RT5640_JD_SFT 13
1463#define RT5640_JD_DIS (0x0 << 13)
1464#define RT5640_JD_GPIO1 (0x1 << 13)
1465#define RT5640_JD_JD1_IN4P (0x2 << 13)
1466#define RT5640_JD_JD2_IN4N (0x3 << 13)
1467#define RT5640_JD_GPIO2 (0x4 << 13)
1468#define RT5640_JD_GPIO3 (0x5 << 13)
1469#define RT5640_JD_GPIO4 (0x6 << 13)
1470#define RT5640_JD_HP_MASK (0x1 << 11)
1471#define RT5640_JD_HP_SFT 11
1472#define RT5640_JD_HP_DIS (0x0 << 11)
1473#define RT5640_JD_HP_EN (0x1 << 11)
1474#define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1475#define RT5640_JD_HP_TRG_SFT 10
1476#define RT5640_JD_HP_TRG_LO (0x0 << 10)
1477#define RT5640_JD_HP_TRG_HI (0x1 << 10)
1478#define RT5640_JD_SPL_MASK (0x1 << 9)
1479#define RT5640_JD_SPL_SFT 9
1480#define RT5640_JD_SPL_DIS (0x0 << 9)
1481#define RT5640_JD_SPL_EN (0x1 << 9)
1482#define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1483#define RT5640_JD_SPL_TRG_SFT 8
1484#define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1485#define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1486#define RT5640_JD_SPR_MASK (0x1 << 7)
1487#define RT5640_JD_SPR_SFT 7
1488#define RT5640_JD_SPR_DIS (0x0 << 7)
1489#define RT5640_JD_SPR_EN (0x1 << 7)
1490#define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1491#define RT5640_JD_SPR_TRG_SFT 6
1492#define RT5640_JD_SPR_TRG_LO (0x0 << 6)
1493#define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1494#define RT5640_JD_MO_MASK (0x1 << 5)
1495#define RT5640_JD_MO_SFT 5
1496#define RT5640_JD_MO_DIS (0x0 << 5)
1497#define RT5640_JD_MO_EN (0x1 << 5)
1498#define RT5640_JD_MO_TRG_MASK (0x1 << 4)
1499#define RT5640_JD_MO_TRG_SFT 4
1500#define RT5640_JD_MO_TRG_LO (0x0 << 4)
1501#define RT5640_JD_MO_TRG_HI (0x1 << 4)
1502#define RT5640_JD_LO_MASK (0x1 << 3)
1503#define RT5640_JD_LO_SFT 3
1504#define RT5640_JD_LO_DIS (0x0 << 3)
1505#define RT5640_JD_LO_EN (0x1 << 3)
1506#define RT5640_JD_LO_TRG_MASK (0x1 << 2)
1507#define RT5640_JD_LO_TRG_SFT 2
1508#define RT5640_JD_LO_TRG_LO (0x0 << 2)
1509#define RT5640_JD_LO_TRG_HI (0x1 << 2)
1510#define RT5640_JD1_IN4P_MASK (0x1 << 1)
1511#define RT5640_JD1_IN4P_SFT 1
1512#define RT5640_JD1_IN4P_DIS (0x0 << 1)
1513#define RT5640_JD1_IN4P_EN (0x1 << 1)
1514#define RT5640_JD2_IN4N_MASK (0x1)
1515#define RT5640_JD2_IN4N_SFT 0
1516#define RT5640_JD2_IN4N_DIS (0x0)
1517#define RT5640_JD2_IN4N_EN (0x1)
1518
1519/* Jack detect for ANC (0xbc) */
1520#define RT5640_ANC_DET_MASK (0x3 << 4)
1521#define RT5640_ANC_DET_SFT 4
1522#define RT5640_ANC_DET_DIS (0x0 << 4)
1523#define RT5640_ANC_DET_MB1 (0x1 << 4)
1524#define RT5640_ANC_DET_MB2 (0x2 << 4)
1525#define RT5640_ANC_DET_JD (0x3 << 4)
1526#define RT5640_AD_TRG_MASK (0x1 << 3)
1527#define RT5640_AD_TRG_SFT 3
1528#define RT5640_AD_TRG_LO (0x0 << 3)
1529#define RT5640_AD_TRG_HI (0x1 << 3)
1530#define RT5640_ANCM_DET_MASK (0x3 << 4)
1531#define RT5640_ANCM_DET_SFT 4
1532#define RT5640_ANCM_DET_DIS (0x0 << 4)
1533#define RT5640_ANCM_DET_MB1 (0x1 << 4)
1534#define RT5640_ANCM_DET_MB2 (0x2 << 4)
1535#define RT5640_ANCM_DET_JD (0x3 << 4)
1536#define RT5640_AMD_TRG_MASK (0x1 << 3)
1537#define RT5640_AMD_TRG_SFT 3
1538#define RT5640_AMD_TRG_LO (0x0 << 3)
1539#define RT5640_AMD_TRG_HI (0x1 << 3)
1540
1541/* IRQ Control 1 (0xbd) */
1542#define RT5640_IRQ_JD_MASK (0x1 << 15)
1543#define RT5640_IRQ_JD_SFT 15
1544#define RT5640_IRQ_JD_BP (0x0 << 15)
1545#define RT5640_IRQ_JD_NOR (0x1 << 15)
1546#define RT5640_IRQ_OT_MASK (0x1 << 14)
1547#define RT5640_IRQ_OT_SFT 14
1548#define RT5640_IRQ_OT_BP (0x0 << 14)
1549#define RT5640_IRQ_OT_NOR (0x1 << 14)
1550#define RT5640_JD_STKY_MASK (0x1 << 13)
1551#define RT5640_JD_STKY_SFT 13
1552#define RT5640_JD_STKY_DIS (0x0 << 13)
1553#define RT5640_JD_STKY_EN (0x1 << 13)
1554#define RT5640_OT_STKY_MASK (0x1 << 12)
1555#define RT5640_OT_STKY_SFT 12
1556#define RT5640_OT_STKY_DIS (0x0 << 12)
1557#define RT5640_OT_STKY_EN (0x1 << 12)
1558#define RT5640_JD_P_MASK (0x1 << 11)
1559#define RT5640_JD_P_SFT 11
1560#define RT5640_JD_P_NOR (0x0 << 11)
1561#define RT5640_JD_P_INV (0x1 << 11)
1562#define RT5640_OT_P_MASK (0x1 << 10)
1563#define RT5640_OT_P_SFT 10
1564#define RT5640_OT_P_NOR (0x0 << 10)
1565#define RT5640_OT_P_INV (0x1 << 10)
1566
1567/* IRQ Control 2 (0xbe) */
1568#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1569#define RT5640_IRQ_MB1_OC_SFT 15
1570#define RT5640_IRQ_MB1_OC_BP (0x0 << 15)
1571#define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1572#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1573#define RT5640_IRQ_MB2_OC_SFT 14
1574#define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
1575#define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1576#define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1577#define RT5640_MB1_OC_STKY_SFT 11
1578#define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1579#define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1580#define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1581#define RT5640_MB2_OC_STKY_SFT 10
1582#define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1583#define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1584#define RT5640_MB1_OC_P_MASK (0x1 << 7)
1585#define RT5640_MB1_OC_P_SFT 7
1586#define RT5640_MB1_OC_P_NOR (0x0 << 7)
1587#define RT5640_MB1_OC_P_INV (0x1 << 7)
1588#define RT5640_MB2_OC_P_MASK (0x1 << 6)
1589#define RT5640_MB2_OC_P_SFT 6
1590#define RT5640_MB2_OC_P_NOR (0x0 << 6)
1591#define RT5640_MB2_OC_P_INV (0x1 << 6)
1592#define RT5640_MB1_OC_CLR (0x1 << 3)
1593#define RT5640_MB1_OC_CLR_SFT 3
1594#define RT5640_MB2_OC_CLR (0x1 << 2)
1595#define RT5640_MB2_OC_CLR_SFT 2
1596
1597/* GPIO Control 1 (0xc0) */
1598#define RT5640_GP1_PIN_MASK (0x1 << 15)
1599#define RT5640_GP1_PIN_SFT 15
1600#define RT5640_GP1_PIN_GPIO1 (0x0 << 15)
1601#define RT5640_GP1_PIN_IRQ (0x1 << 15)
1602#define RT5640_GP2_PIN_MASK (0x1 << 14)
1603#define RT5640_GP2_PIN_SFT 14
1604#define RT5640_GP2_PIN_GPIO2 (0x0 << 14)
1605#define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1606#define RT5640_GP3_PIN_MASK (0x3 << 12)
1607#define RT5640_GP3_PIN_SFT 12
1608#define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1609#define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1610#define RT5640_GP3_PIN_IRQ (0x2 << 12)
1611#define RT5640_GP4_PIN_MASK (0x1 << 11)
1612#define RT5640_GP4_PIN_SFT 11
1613#define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1614#define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1615#define RT5640_DP_SIG_MASK (0x1 << 10)
1616#define RT5640_DP_SIG_SFT 10
1617#define RT5640_DP_SIG_TEST (0x0 << 10)
1618#define RT5640_DP_SIG_AP (0x1 << 10)
1619#define RT5640_GPIO_M_MASK (0x1 << 9)
1620#define RT5640_GPIO_M_SFT 9
1621#define RT5640_GPIO_M_FLT (0x0 << 9)
1622#define RT5640_GPIO_M_PH (0x1 << 9)
1623
1624/* GPIO Control 3 (0xc2) */
1625#define RT5640_GP4_PF_MASK (0x1 << 11)
1626#define RT5640_GP4_PF_SFT 11
1627#define RT5640_GP4_PF_IN (0x0 << 11)
1628#define RT5640_GP4_PF_OUT (0x1 << 11)
1629#define RT5640_GP4_OUT_MASK (0x1 << 10)
1630#define RT5640_GP4_OUT_SFT 10
1631#define RT5640_GP4_OUT_LO (0x0 << 10)
1632#define RT5640_GP4_OUT_HI (0x1 << 10)
1633#define RT5640_GP4_P_MASK (0x1 << 9)
1634#define RT5640_GP4_P_SFT 9
1635#define RT5640_GP4_P_NOR (0x0 << 9)
1636#define RT5640_GP4_P_INV (0x1 << 9)
1637#define RT5640_GP3_PF_MASK (0x1 << 8)
1638#define RT5640_GP3_PF_SFT 8
1639#define RT5640_GP3_PF_IN (0x0 << 8)
1640#define RT5640_GP3_PF_OUT (0x1 << 8)
1641#define RT5640_GP3_OUT_MASK (0x1 << 7)
1642#define RT5640_GP3_OUT_SFT 7
1643#define RT5640_GP3_OUT_LO (0x0 << 7)
1644#define RT5640_GP3_OUT_HI (0x1 << 7)
1645#define RT5640_GP3_P_MASK (0x1 << 6)
1646#define RT5640_GP3_P_SFT 6
1647#define RT5640_GP3_P_NOR (0x0 << 6)
1648#define RT5640_GP3_P_INV (0x1 << 6)
1649#define RT5640_GP2_PF_MASK (0x1 << 5)
1650#define RT5640_GP2_PF_SFT 5
1651#define RT5640_GP2_PF_IN (0x0 << 5)
1652#define RT5640_GP2_PF_OUT (0x1 << 5)
1653#define RT5640_GP2_OUT_MASK (0x1 << 4)
1654#define RT5640_GP2_OUT_SFT 4
1655#define RT5640_GP2_OUT_LO (0x0 << 4)
1656#define RT5640_GP2_OUT_HI (0x1 << 4)
1657#define RT5640_GP2_P_MASK (0x1 << 3)
1658#define RT5640_GP2_P_SFT 3
1659#define RT5640_GP2_P_NOR (0x0 << 3)
1660#define RT5640_GP2_P_INV (0x1 << 3)
1661#define RT5640_GP1_PF_MASK (0x1 << 2)
1662#define RT5640_GP1_PF_SFT 2
1663#define RT5640_GP1_PF_IN (0x0 << 2)
1664#define RT5640_GP1_PF_OUT (0x1 << 2)
1665#define RT5640_GP1_OUT_MASK (0x1 << 1)
1666#define RT5640_GP1_OUT_SFT 1
1667#define RT5640_GP1_OUT_LO (0x0 << 1)
1668#define RT5640_GP1_OUT_HI (0x1 << 1)
1669#define RT5640_GP1_P_MASK (0x1)
1670#define RT5640_GP1_P_SFT 0
1671#define RT5640_GP1_P_NOR (0x0)
1672#define RT5640_GP1_P_INV (0x1)
1673
1674/* FM34-500 Register Control 1 (0xc4) */
1675#define RT5640_DSP_ADD_SFT 0
1676
1677/* FM34-500 Register Control 2 (0xc5) */
1678#define RT5640_DSP_DAT_SFT 0
1679
1680/* FM34-500 Register Control 3 (0xc6) */
1681#define RT5640_DSP_BUSY_MASK (0x1 << 15)
1682#define RT5640_DSP_BUSY_BIT 15
1683#define RT5640_DSP_DS_MASK (0x1 << 14)
1684#define RT5640_DSP_DS_SFT 14
1685#define RT5640_DSP_DS_FM3010 (0x1 << 14)
1686#define RT5640_DSP_DS_TEMP (0x1 << 14)
1687#define RT5640_DSP_CLK_MASK (0x3 << 12)
1688#define RT5640_DSP_CLK_SFT 12
1689#define RT5640_DSP_CLK_384K (0x0 << 12)
1690#define RT5640_DSP_CLK_192K (0x1 << 12)
1691#define RT5640_DSP_CLK_96K (0x2 << 12)
1692#define RT5640_DSP_CLK_64K (0x3 << 12)
1693#define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1694#define RT5640_DSP_PD_PIN_SFT 11
1695#define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1696#define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1697#define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1698#define RT5640_DSP_RST_PIN_SFT 10
1699#define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1700#define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1701#define RT5640_DSP_R_EN (0x1 << 9)
1702#define RT5640_DSP_R_EN_BIT 9
1703#define RT5640_DSP_W_EN (0x1 << 8)
1704#define RT5640_DSP_W_EN_BIT 8
1705#define RT5640_DSP_CMD_MASK (0xff)
1706#define RT5640_DSP_CMD_SFT 0
1707#define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */
1708#define RT5640_DSP_CMD_MR (0x37) /* Memory Read */
1709#define RT5640_DSP_CMD_RR (0x60) /* Register Read */
1710#define RT5640_DSP_CMD_RW (0x68) /* Register Write */
1711
1712/* Programmable Register Array Control 1 (0xc8) */
1713#define RT5640_REG_SEQ_MASK (0xf << 12)
1714#define RT5640_REG_SEQ_SFT 12
1715#define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1716#define RT5640_SEQ1_ST_SFT 11
1717#define RT5640_SEQ1_ST_RUN (0x0 << 11)
1718#define RT5640_SEQ1_ST_FIN (0x1 << 11)
1719#define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1720#define RT5640_SEQ2_ST_SFT 10
1721#define RT5640_SEQ2_ST_RUN (0x0 << 10)
1722#define RT5640_SEQ2_ST_FIN (0x1 << 10)
1723#define RT5640_REG_LV_MASK (0x1 << 9)
1724#define RT5640_REG_LV_SFT 9
1725#define RT5640_REG_LV_MX (0x0 << 9)
1726#define RT5640_REG_LV_PR (0x1 << 9)
1727#define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1728#define RT5640_SEQ_2_PT_BIT 8
1729#define RT5640_REG_IDX_MASK (0xff)
1730#define RT5640_REG_IDX_SFT 0
1731
1732/* Programmable Register Array Control 2 (0xc9) */
1733#define RT5640_REG_DAT_MASK (0xffff)
1734#define RT5640_REG_DAT_SFT 0
1735
1736/* Programmable Register Array Control 3 (0xca) */
1737#define RT5640_SEQ_DLY_MASK (0xff << 8)
1738#define RT5640_SEQ_DLY_SFT 8
1739#define RT5640_PROG_MASK (0x1 << 7)
1740#define RT5640_PROG_SFT 7
1741#define RT5640_PROG_DIS (0x0 << 7)
1742#define RT5640_PROG_EN (0x1 << 7)
1743#define RT5640_SEQ1_PT_RUN (0x1 << 6)
1744#define RT5640_SEQ1_PT_RUN_BIT 6
1745#define RT5640_SEQ2_PT_RUN (0x1 << 5)
1746#define RT5640_SEQ2_PT_RUN_BIT 5
1747
1748/* Programmable Register Array Control 4 (0xcb) */
1749#define RT5640_SEQ1_START_MASK (0xf << 8)
1750#define RT5640_SEQ1_START_SFT 8
1751#define RT5640_SEQ1_END_MASK (0xf)
1752#define RT5640_SEQ1_END_SFT 0
1753
1754/* Programmable Register Array Control 5 (0xcc) */
1755#define RT5640_SEQ2_START_MASK (0xf << 8)
1756#define RT5640_SEQ2_START_SFT 8
1757#define RT5640_SEQ2_END_MASK (0xf)
1758#define RT5640_SEQ2_END_SFT 0
1759
1760/* Scramble Function (0xcd) */
1761#define RT5640_SCB_KEY_MASK (0xff)
1762#define RT5640_SCB_KEY_SFT 0
1763
1764/* Scramble Control (0xce) */
1765#define RT5640_SCB_SWAP_MASK (0x1 << 15)
1766#define RT5640_SCB_SWAP_SFT 15
1767#define RT5640_SCB_SWAP_DIS (0x0 << 15)
1768#define RT5640_SCB_SWAP_EN (0x1 << 15)
1769#define RT5640_SCB_MASK (0x1 << 14)
1770#define RT5640_SCB_SFT 14
1771#define RT5640_SCB_DIS (0x0 << 14)
1772#define RT5640_SCB_EN (0x1 << 14)
1773
1774/* Baseback Control (0xcf) */
1775#define RT5640_BB_MASK (0x1 << 15)
1776#define RT5640_BB_SFT 15
1777#define RT5640_BB_DIS (0x0 << 15)
1778#define RT5640_BB_EN (0x1 << 15)
1779#define RT5640_BB_CT_MASK (0x7 << 12)
1780#define RT5640_BB_CT_SFT 12
1781#define RT5640_BB_CT_A (0x0 << 12)
1782#define RT5640_BB_CT_B (0x1 << 12)
1783#define RT5640_BB_CT_C (0x2 << 12)
1784#define RT5640_BB_CT_D (0x3 << 12)
1785#define RT5640_M_BB_L_MASK (0x1 << 9)
1786#define RT5640_M_BB_L_SFT 9
1787#define RT5640_M_BB_R_MASK (0x1 << 8)
1788#define RT5640_M_BB_R_SFT 8
1789#define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
1790#define RT5640_M_BB_HPF_L_SFT 7
1791#define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1792#define RT5640_M_BB_HPF_R_SFT 6
1793#define RT5640_G_BB_BST_MASK (0x3f)
1794#define RT5640_G_BB_BST_SFT 0
1795
1796/* MP3 Plus Control 1 (0xd0) */
1797#define RT5640_M_MP3_L_MASK (0x1 << 15)
1798#define RT5640_M_MP3_L_SFT 15
1799#define RT5640_M_MP3_R_MASK (0x1 << 14)
1800#define RT5640_M_MP3_R_SFT 14
1801#define RT5640_M_MP3_MASK (0x1 << 13)
1802#define RT5640_M_MP3_SFT 13
1803#define RT5640_M_MP3_DIS (0x0 << 13)
1804#define RT5640_M_MP3_EN (0x1 << 13)
1805#define RT5640_EG_MP3_MASK (0x1f << 8)
1806#define RT5640_EG_MP3_SFT 8
1807#define RT5640_MP3_HLP_MASK (0x1 << 7)
1808#define RT5640_MP3_HLP_SFT 7
1809#define RT5640_MP3_HLP_DIS (0x0 << 7)
1810#define RT5640_MP3_HLP_EN (0x1 << 7)
1811#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1812#define RT5640_M_MP3_ORG_L_SFT 6
1813#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
1814#define RT5640_M_MP3_ORG_R_SFT 5
1815
1816/* MP3 Plus Control 2 (0xd1) */
1817#define RT5640_MP3_WT_MASK (0x1 << 13)
1818#define RT5640_MP3_WT_SFT 13
1819#define RT5640_MP3_WT_1_4 (0x0 << 13)
1820#define RT5640_MP3_WT_1_2 (0x1 << 13)
1821#define RT5640_OG_MP3_MASK (0x1f << 8)
1822#define RT5640_OG_MP3_SFT 8
1823#define RT5640_HG_MP3_MASK (0x3f)
1824#define RT5640_HG_MP3_SFT 0
1825
1826/* 3D HP Control 1 (0xd2) */
1827#define RT5640_3D_CF_MASK (0x1 << 15)
1828#define RT5640_3D_CF_SFT 15
1829#define RT5640_3D_CF_DIS (0x0 << 15)
1830#define RT5640_3D_CF_EN (0x1 << 15)
1831#define RT5640_3D_HP_MASK (0x1 << 14)
1832#define RT5640_3D_HP_SFT 14
1833#define RT5640_3D_HP_DIS (0x0 << 14)
1834#define RT5640_3D_HP_EN (0x1 << 14)
1835#define RT5640_3D_BT_MASK (0x1 << 13)
1836#define RT5640_3D_BT_SFT 13
1837#define RT5640_3D_BT_DIS (0x0 << 13)
1838#define RT5640_3D_BT_EN (0x1 << 13)
1839#define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1840#define RT5640_3D_1F_MIX_SFT 11
1841#define RT5640_3D_HP_M_MASK (0x1 << 10)
1842#define RT5640_3D_HP_M_SFT 10
1843#define RT5640_3D_HP_M_SUR (0x0 << 10)
1844#define RT5640_3D_HP_M_FRO (0x1 << 10)
1845#define RT5640_M_3D_HRTF_MASK (0x1 << 9)
1846#define RT5640_M_3D_HRTF_SFT 9
1847#define RT5640_M_3D_D2H_MASK (0x1 << 8)
1848#define RT5640_M_3D_D2H_SFT 8
1849#define RT5640_M_3D_D2R_MASK (0x1 << 7)
1850#define RT5640_M_3D_D2R_SFT 7
1851#define RT5640_M_3D_REVB_MASK (0x1 << 6)
1852#define RT5640_M_3D_REVB_SFT 6
1853
1854/* Adjustable high pass filter control 1 (0xd3) */
1855#define RT5640_2ND_HPF_MASK (0x1 << 15)
1856#define RT5640_2ND_HPF_SFT 15
1857#define RT5640_2ND_HPF_DIS (0x0 << 15)
1858#define RT5640_2ND_HPF_EN (0x1 << 15)
1859#define RT5640_HPF_CF_L_MASK (0x7 << 12)
1860#define RT5640_HPF_CF_L_SFT 12
1861#define RT5640_1ST_HPF_MASK (0x1 << 11)
1862#define RT5640_1ST_HPF_SFT 11
1863#define RT5640_1ST_HPF_DIS (0x0 << 11)
1864#define RT5640_1ST_HPF_EN (0x1 << 11)
1865#define RT5640_HPF_CF_R_MASK (0x7 << 8)
1866#define RT5640_HPF_CF_R_SFT 8
1867#define RT5640_ZD_T_MASK (0x3 << 6)
1868#define RT5640_ZD_T_SFT 6
1869#define RT5640_ZD_F_MASK (0x3 << 4)
1870#define RT5640_ZD_F_SFT 4
1871#define RT5640_ZD_F_IM (0x0 << 4)
1872#define RT5640_ZD_F_ZC_IM (0x1 << 4)
1873#define RT5640_ZD_F_ZC_IOD (0x2 << 4)
1874#define RT5640_ZD_F_UN (0x3 << 4)
1875
1876/* HP calibration control and Amp detection (0xd6) */
1877#define RT5640_SI_DAC_MASK (0x1 << 11)
1878#define RT5640_SI_DAC_SFT 11
1879#define RT5640_SI_DAC_AUTO (0x0 << 11)
1880#define RT5640_SI_DAC_TEST (0x1 << 11)
1881#define RT5640_DC_CAL_M_MASK (0x1 << 10)
1882#define RT5640_DC_CAL_M_SFT 10
1883#define RT5640_DC_CAL_M_CAL (0x0 << 10)
1884#define RT5640_DC_CAL_M_NOR (0x1 << 10)
1885#define RT5640_DC_CAL_MASK (0x1 << 9)
1886#define RT5640_DC_CAL_SFT 9
1887#define RT5640_DC_CAL_DIS (0x0 << 9)
1888#define RT5640_DC_CAL_EN (0x1 << 9)
1889#define RT5640_HPD_RCV_MASK (0x7 << 6)
1890#define RT5640_HPD_RCV_SFT 6
1891#define RT5640_HPD_PS_MASK (0x1 << 5)
1892#define RT5640_HPD_PS_SFT 5
1893#define RT5640_HPD_PS_DIS (0x0 << 5)
1894#define RT5640_HPD_PS_EN (0x1 << 5)
1895#define RT5640_CAL_M_MASK (0x1 << 4)
1896#define RT5640_CAL_M_SFT 4
1897#define RT5640_CAL_M_DEP (0x0 << 4)
1898#define RT5640_CAL_M_CAL (0x1 << 4)
1899#define RT5640_CAL_MASK (0x1 << 3)
1900#define RT5640_CAL_SFT 3
1901#define RT5640_CAL_DIS (0x0 << 3)
1902#define RT5640_CAL_EN (0x1 << 3)
1903#define RT5640_CAL_TEST_MASK (0x1 << 2)
1904#define RT5640_CAL_TEST_SFT 2
1905#define RT5640_CAL_TEST_DIS (0x0 << 2)
1906#define RT5640_CAL_TEST_EN (0x1 << 2)
1907#define RT5640_CAL_P_MASK (0x3)
1908#define RT5640_CAL_P_SFT 0
1909#define RT5640_CAL_P_NONE (0x0)
1910#define RT5640_CAL_P_CAL (0x1)
1911#define RT5640_CAL_P_DAC_CAL (0x2)
1912
1913/* Soft volume and zero cross control 1 (0xd9) */
1914#define RT5640_SV_MASK (0x1 << 15)
1915#define RT5640_SV_SFT 15
1916#define RT5640_SV_DIS (0x0 << 15)
1917#define RT5640_SV_EN (0x1 << 15)
1918#define RT5640_SPO_SV_MASK (0x1 << 14)
1919#define RT5640_SPO_SV_SFT 14
1920#define RT5640_SPO_SV_DIS (0x0 << 14)
1921#define RT5640_SPO_SV_EN (0x1 << 14)
1922#define RT5640_OUT_SV_MASK (0x1 << 13)
1923#define RT5640_OUT_SV_SFT 13
1924#define RT5640_OUT_SV_DIS (0x0 << 13)
1925#define RT5640_OUT_SV_EN (0x1 << 13)
1926#define RT5640_HP_SV_MASK (0x1 << 12)
1927#define RT5640_HP_SV_SFT 12
1928#define RT5640_HP_SV_DIS (0x0 << 12)
1929#define RT5640_HP_SV_EN (0x1 << 12)
1930#define RT5640_ZCD_DIG_MASK (0x1 << 11)
1931#define RT5640_ZCD_DIG_SFT 11
1932#define RT5640_ZCD_DIG_DIS (0x0 << 11)
1933#define RT5640_ZCD_DIG_EN (0x1 << 11)
1934#define RT5640_ZCD_MASK (0x1 << 10)
1935#define RT5640_ZCD_SFT 10
1936#define RT5640_ZCD_PD (0x0 << 10)
1937#define RT5640_ZCD_PU (0x1 << 10)
1938#define RT5640_M_ZCD_MASK (0x3f << 4)
1939#define RT5640_M_ZCD_SFT 4
1940#define RT5640_M_ZCD_RM_L (0x1 << 9)
1941#define RT5640_M_ZCD_RM_R (0x1 << 8)
1942#define RT5640_M_ZCD_SM_L (0x1 << 7)
1943#define RT5640_M_ZCD_SM_R (0x1 << 6)
1944#define RT5640_M_ZCD_OM_L (0x1 << 5)
1945#define RT5640_M_ZCD_OM_R (0x1 << 4)
1946#define RT5640_SV_DLY_MASK (0xf)
1947#define RT5640_SV_DLY_SFT 0
1948
1949/* Soft volume and zero cross control 2 (0xda) */
1950#define RT5640_ZCD_HP_MASK (0x1 << 15)
1951#define RT5640_ZCD_HP_SFT 15
1952#define RT5640_ZCD_HP_DIS (0x0 << 15)
1953#define RT5640_ZCD_HP_EN (0x1 << 15)
1954
1955
1956/* Codec Private Register definition */
1957/* 3D Speaker Control (0x63) */
1958#define RT5640_3D_SPK_MASK (0x1 << 15)
1959#define RT5640_3D_SPK_SFT 15
1960#define RT5640_3D_SPK_DIS (0x0 << 15)
1961#define RT5640_3D_SPK_EN (0x1 << 15)
1962#define RT5640_3D_SPK_M_MASK (0x3 << 13)
1963#define RT5640_3D_SPK_M_SFT 13
1964#define RT5640_3D_SPK_CG_MASK (0x1f << 8)
1965#define RT5640_3D_SPK_CG_SFT 8
1966#define RT5640_3D_SPK_SG_MASK (0x1f)
1967#define RT5640_3D_SPK_SG_SFT 0
1968
1969/* Wind Noise Detection Control 1 (0x6c) */
1970#define RT5640_WND_MASK (0x1 << 15)
1971#define RT5640_WND_SFT 15
1972#define RT5640_WND_DIS (0x0 << 15)
1973#define RT5640_WND_EN (0x1 << 15)
1974
1975/* Wind Noise Detection Control 2 (0x6d) */
1976#define RT5640_WND_FC_NW_MASK (0x3f << 10)
1977#define RT5640_WND_FC_NW_SFT 10
1978#define RT5640_WND_FC_WK_MASK (0x3f << 4)
1979#define RT5640_WND_FC_WK_SFT 4
1980
1981/* Wind Noise Detection Control 3 (0x6e) */
1982#define RT5640_HPF_FC_MASK (0x3f << 6)
1983#define RT5640_HPF_FC_SFT 6
1984#define RT5640_WND_FC_ST_MASK (0x3f)
1985#define RT5640_WND_FC_ST_SFT 0
1986
1987/* Wind Noise Detection Control 4 (0x6f) */
1988#define RT5640_WND_TH_LO_MASK (0x3ff)
1989#define RT5640_WND_TH_LO_SFT 0
1990
1991/* Wind Noise Detection Control 5 (0x70) */
1992#define RT5640_WND_TH_HI_MASK (0x3ff)
1993#define RT5640_WND_TH_HI_SFT 0
1994
1995/* Wind Noise Detection Control 8 (0x73) */
1996#define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1997#define RT5640_WND_WIND_SFT 13
1998#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1999#define RT5640_WND_STRONG_SFT 12
2000enum {
2001 RT5640_NO_WIND,
2002 RT5640_BREEZE,
2003 RT5640_STORM,
2004};
2005
2006/* Dipole Speaker Interface (0x75) */
2007#define RT5640_DP_ATT_MASK (0x3 << 14)
2008#define RT5640_DP_ATT_SFT 14
2009#define RT5640_DP_SPK_MASK (0x1 << 10)
2010#define RT5640_DP_SPK_SFT 10
2011#define RT5640_DP_SPK_DIS (0x0 << 10)
2012#define RT5640_DP_SPK_EN (0x1 << 10)
2013
2014/* EQ Pre Volume Control (0xb3) */
2015#define RT5640_EQ_PRE_VOL_MASK (0xffff)
2016#define RT5640_EQ_PRE_VOL_SFT 0
2017
2018/* EQ Post Volume Control (0xb4) */
2019#define RT5640_EQ_PST_VOL_MASK (0xffff)
2020#define RT5640_EQ_PST_VOL_SFT 0
2021
2022#define RT5640_NO_JACK BIT(0)
2023#define RT5640_HEADSET_DET BIT(1)
2024#define RT5640_HEADPHO_DET BIT(2)
2025
2026int rt5640_headset_detect(struct snd_soc_codec *codec, int jack_insert);
2027
2028/* System Clock Source */
2029#define RT5640_SCLK_S_MCLK 0
2030#define RT5640_SCLK_S_PLL1 1
2031#define RT5640_SCLK_S_PLL1_TK 2
2032#define RT5640_SCLK_S_RCCLK 3
2033
2034/* PLL1 Source */
2035#define RT5640_PLL1_S_MCLK 0
2036#define RT5640_PLL1_S_BCLK1 1
2037#define RT5640_PLL1_S_BCLK2 2
2038#define RT5640_PLL1_S_BCLK3 3
2039
2040
2041enum {
2042 RT5640_AIF1,
2043 RT5640_AIF2,
2044 RT5640_AIF3,
2045 RT5640_AIFS,
2046};
2047
2048enum {
2049 RT5640_U_IF1 = 0x1,
2050 RT5640_U_IF2 = 0x2,
2051 RT5640_U_IF3 = 0x4,
2052};
2053
2054enum {
2055 RT5640_IF_123,
2056 RT5640_IF_132,
2057 RT5640_IF_312,
2058 RT5640_IF_321,
2059 RT5640_IF_231,
2060 RT5640_IF_213,
2061 RT5640_IF_113,
2062 RT5640_IF_223,
2063 RT5640_IF_ALL,
2064};
2065
2066enum {
2067 RT5640_DMIC_DIS,
2068 RT5640_DMIC1,
2069 RT5640_DMIC2,
2070};
2071
2072struct rt5640_pll_code {
2073 bool m_bp; /* Indicates bypass m code or not. */
2074 int m_code;
2075 int n_code;
2076 int k_code;
2077};
2078
2079struct rt5640_priv {
2080 struct snd_soc_codec *codec;
2081
2082 int aif_pu;
2083 int sysclk;
2084 int sysclk_src;
2085 int lrck[RT5640_AIFS];
2086 int bclk[RT5640_AIFS];
2087 int master[RT5640_AIFS];
2088
2089 int pll_src;
2090 int pll_in;
2091 int pll_out;
2092
2093 int dmic_en;
2094 int dsp_sw;
2095};
2096
2097
2098#endif /* __RT5640_H__ */
diff --git a/sound/soc/codecs/second_rate_pps_driver.h b/sound/soc/codecs/second_rate_pps_driver.h
new file mode 100644
index 00000000000..c6c128a027d
--- /dev/null
+++ b/sound/soc/codecs/second_rate_pps_driver.h
@@ -0,0 +1,3626 @@
1//CONTROL LOCATIONS
2
3
4
5static control main44_MUX_controls[] = {
6};
7
8static char *main44_MUX_control_names[] = {
9};
10
11static control main44_VOLUME_controls[] = {
12};
13
14static char *main44_VOLUME_control_names[] = {
15};
16
17
18
19static char *main44_REG_Section_names[] = {
20 "miniDSP_A_reg_values",
21 "miniDSP_D_reg_values",
22};
23
24reg_value main44_REG_Section_init_program[] = {
25 { 0,0x0},
26 { 0x7F,0x00},
27// # Set AutoINC
28 {121,0x01},
29 { 0x7F,0x78},
30// # reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled
31 { 50,0x88},
32 { 0x7F,0x64},
33// # reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled
34 { 50,0x84},
35 { 0x7F,0x78},
36// # reg[120][0][24]=0x80
37 { 24,0x80},
38 {255,0x00},
39};
40reg_value main44_REG_Section_post_program[] = {
41 { 0,0x0},
42 { 0x7F,0x28},
43// # reg[40][0][1] = 0x04 ; adaptive mode for ADC
44 { 1,0x04},
45 { 0x7F,0x50},
46// # reg[80][0][1] = 0x04 ; adaptive mode for DAC
47 { 1,0x04},
48 { 0x7F,0x64},
49// # reg[100][0][48] = 4;IDAC = 256 ; MDAC*DOSR;IADC = 256 ; MADC*AOSR;IDAC = 512 ; MDAC*DOSR;IADC = 512 ; MADC*AOSR;IDAC = 1024 ; MDAC*DOSR;IADC = 1024 ; MADC*AOSR;IDAC = 1536 ; MDAC*DOSR;IADC = 1536 ; MADC*AOSR;IDAC = 2048 ; MDAC*DOSR;IADC = 2048 ; MADC*AOSR;IDAC = 3072 ; MDAC*DOSR;IADC = 3072 ; MADC*AOSR;IDAC = 4096 ; MDAC*DOSR;IADC = 4096 ; MADC*AOSR;IDAC = 6144 ; MDAC*DOSR;IADC = 6144 ; MADC*AOSR
50 { 48,0x04},
51// # reg[100][0][49] = 0
52 { 49,0x00},
53 { 0x7F,0x78},
54// # reg[120][0][48] = 4
55 { 48,0x04},
56// # reg[120][0][49] = 0
57 { 49,0x00},
58 { 0,0x0},
59 { 0x7F,0x64},
60// # reg[100][0][20] = 0x80 ; Disable ADC double buffer mode; Disable DAC double buffer mode; Enable ADC double buffer mode
61 { 20,0x80},
62 { 0x7F,0x78},
63// # reg[120][0][20] = 0x80 ; Enable DAC double buffer mode
64 { 20,0x80},
65};
66
67reg_value main44_miniDSP_A_reg_values[] = {
68 { 0,0x0},
69 { 0x7F,0x28},
70 { 0,0x01},
71 { 8,0x01},
72 { 9,0xF0},
73 { 10,0x18},
74 { 11,0x00},
75 { 12,0x7C},
76 { 13,0x1F},
77 { 14,0xD0},
78 { 15,0x00},
79 { 16,0x7F},
80 { 17,0xFF},
81 { 18,0xFF},
82 { 19,0x00},
83 { 20,0x00},
84 { 21,0x00},
85 { 22,0x00},
86 { 23,0x00},
87 { 24,0x00},
88 { 25,0x00},
89 { 26,0x00},
90 { 27,0x00},
91 { 28,0x60},
92 { 29,0x00},
93 { 30,0x00},
94 { 31,0x00},
95 { 32,0x60},
96 { 33,0x00},
97 { 34,0x00},
98 { 35,0x00},
99 { 36,0xFF},
100 { 37,0xFF},
101 { 38,0xFF},
102 { 39,0x00},
103 { 40,0x80},
104 { 41,0x00},
105 { 42,0x00},
106 { 43,0x00},
107 { 44,0x7F},
108 { 45,0xFF},
109 { 46,0xFF},
110 { 47,0x00},
111 { 48,0x60},
112 { 49,0x00},
113 { 50,0x00},
114 { 51,0x00},
115 { 52,0x60},
116 { 53,0x00},
117 { 54,0x00},
118 { 55,0x00},
119 { 56,0x40},
120 { 57,0x00},
121 { 58,0x00},
122 { 59,0x00},
123 { 60,0x00},
124 { 61,0x00},
125 { 62,0x00},
126 { 63,0x00},
127 { 64,0xFF},
128 { 65,0x9E},
129 { 66,0x00},
130 { 67,0x00},
131 { 68,0x00},
132 { 69,0x00},
133 { 70,0x00},
134 { 71,0x00},
135 { 72,0x7F},
136 { 73,0xFF},
137 { 74,0xFF},
138 { 75,0x00},
139 { 76,0xF7},
140 { 77,0x10},
141 { 78,0x00},
142 { 79,0x00},
143 { 80,0x26},
144 { 81,0xF0},
145 { 82,0x00},
146 { 83,0x00},
147 { 84,0x02},
148 { 85,0x61},
149 { 86,0x00},
150 { 87,0x00},
151 { 88,0x40},
152 { 89,0x02},
153 { 90,0x00},
154 { 91,0x00},
155 { 92,0xFF},
156 { 93,0xFC},
157 { 94,0x00},
158 { 95,0x00},
159 { 96,0xFF},
160 { 97,0xFD},
161 { 98,0x00},
162 { 99,0x00},
163 {100,0xFF},
164 {101,0xE5},
165 {102,0x00},
166 {103,0x00},
167 {104,0xFF},
168 {105,0xA7},
169 {106,0x00},
170 {107,0x00},
171 {108,0xFF},
172 {109,0xC7},
173 {110,0x00},
174 {111,0x00},
175 {112,0xFF},
176 {113,0xCE},
177 {114,0x00},
178 {115,0x00},
179 {116,0xFF},
180 {117,0xFE},
181 {118,0x00},
182 {119,0x00},
183 {120,0xFE},
184 {121,0xF7},
185 {122,0x00},
186 {123,0x00},
187 {124,0xFF},
188 {125,0x46},
189 {126,0x00},
190 {127,0x00},
191 { 0,0x02},
192 { 8,0xFF},
193 { 9,0x22},
194 { 10,0x00},
195 { 11,0x00},
196 { 12,0xFF},
197 { 13,0x0F},
198 { 14,0x00},
199 { 15,0x00},
200 { 16,0xFA},
201 { 17,0x8C},
202 { 18,0x00},
203 { 19,0x00},
204 { 20,0xF5},
205 { 21,0x08},
206 { 22,0x00},
207 { 23,0x00},
208 { 24,0xFD},
209 { 25,0x92},
210 { 26,0x00},
211 { 27,0x00},
212 { 28,0xF3},
213 { 29,0xA3},
214 { 30,0x00},
215 { 31,0x00},
216 { 32,0x03},
217 { 33,0xB3},
218 { 34,0x00},
219 { 35,0x00},
220 { 36,0x00},
221 { 37,0x33},
222 { 38,0x00},
223 { 39,0x00},
224 { 40,0x00},
225 { 41,0x71},
226 { 42,0x00},
227 { 43,0x00},
228 { 44,0x40},
229 { 45,0x60},
230 { 46,0x00},
231 { 47,0x00},
232 { 48,0x00},
233 { 49,0xE2},
234 { 50,0x00},
235 { 51,0x00},
236 { 52,0x00},
237 { 53,0xC6},
238 { 54,0x00},
239 { 55,0x00},
240 { 56,0x00},
241 { 57,0x87},
242 { 58,0x00},
243 { 59,0x00},
244 { 60,0x00},
245 { 61,0x0F},
246 { 62,0x00},
247 { 63,0x00},
248 { 64,0x00},
249 { 65,0x0A},
250 { 66,0x00},
251 { 67,0x00},
252 { 68,0x00},
253 { 69,0x02},
254 { 70,0x00},
255 { 71,0x00},
256 { 72,0x01},
257 { 73,0x81},
258 { 74,0x00},
259 { 75,0x00},
260 { 76,0x18},
261 { 77,0x89},
262 { 78,0x00},
263 { 79,0x00},
264 { 80,0x07},
265 { 81,0xFB},
266 { 82,0x00},
267 { 83,0x00},
268 { 84,0x03},
269 { 85,0xBE},
270 { 86,0x00},
271 { 87,0x00},
272 { 88,0x00},
273 { 89,0x49},
274 { 90,0x00},
275 { 91,0x00},
276 { 92,0xFF},
277 { 93,0xF2},
278 { 94,0x00},
279 { 95,0x00},
280 { 96,0xF9},
281 { 97,0xBA},
282 { 98,0x00},
283 { 99,0x00},
284 {100,0xF9},
285 {101,0x00},
286 {102,0x00},
287 {103,0x00},
288 {104,0xFF},
289 {105,0x68},
290 {106,0x00},
291 {107,0x00},
292 {108,0xFE},
293 {109,0x2C},
294 {110,0x00},
295 {111,0x00},
296 {112,0xEB},
297 {113,0x8D},
298 {114,0x00},
299 {115,0x00},
300 {116,0x03},
301 {117,0x83},
302 {118,0x00},
303 {119,0x00},
304 {120,0x01},
305 {121,0xC3},
306 {122,0x00},
307 {123,0x00},
308 {124,0x00},
309 {125,0xD3},
310 {126,0x00},
311 {127,0x00},
312 { 0,0x03},
313 { 8,0x00},
314 { 9,0x33},
315 { 10,0x00},
316 { 11,0x00},
317 { 12,0x00},
318 { 13,0x02},
319 { 14,0x00},
320 { 15,0x00},
321 { 16,0x32},
322 { 17,0x08},
323 { 18,0x00},
324 { 19,0x00},
325 { 20,0x0A},
326 { 21,0xFA},
327 { 22,0x00},
328 { 23,0x00},
329 { 24,0x54},
330 { 25,0x7B},
331 { 26,0x00},
332 { 27,0x00},
333 { 28,0xFF},
334 { 29,0x6B},
335 { 30,0x00},
336 { 31,0x00},
337 { 32,0xFF},
338 { 33,0x03},
339 { 34,0x00},
340 { 35,0x00},
341 { 36,0xFC},
342 { 37,0xC6},
343 { 38,0x00},
344 { 39,0x00},
345 { 40,0xF5},
346 { 41,0x54},
347 { 42,0x00},
348 { 43,0x00},
349 { 44,0xF9},
350 { 45,0x64},
351 { 46,0x00},
352 { 47,0x00},
353 { 48,0x39},
354 { 49,0x80},
355 { 50,0x00},
356 { 51,0x00},
357 { 52,0x03},
358 { 53,0x1C},
359 { 54,0x00},
360 { 55,0x00},
361 { 56,0x03},
362 { 57,0x2F},
363 { 58,0x00},
364 { 59,0x00},
365 { 60,0x00},
366 { 61,0x67},
367 { 62,0x00},
368 { 63,0x00},
369 { 64,0x0F},
370 { 65,0x73},
371 { 66,0x00},
372 { 67,0x00},
373 { 68,0x2C},
374 { 69,0x2B},
375 { 70,0x00},
376 { 71,0x00},
377 { 0,0x09},
378 { 72,0x01},
379 { 73,0xF0},
380 { 74,0x18},
381 { 75,0x00},
382 { 76,0x7C},
383 { 77,0x1F},
384 { 78,0xD0},
385 { 79,0x00},
386 { 80,0x7F},
387 { 81,0xFF},
388 { 82,0xFF},
389 { 83,0x00},
390 { 84,0x00},
391 { 85,0x00},
392 { 86,0x00},
393 { 87,0x00},
394 { 88,0x00},
395 { 89,0x00},
396 { 90,0x00},
397 { 91,0x00},
398 { 92,0x60},
399 { 93,0x00},
400 { 94,0x00},
401 { 95,0x00},
402 { 96,0x60},
403 { 97,0x00},
404 { 98,0x00},
405 { 99,0x00},
406 {100,0xFF},
407 {101,0xFF},
408 {102,0xFF},
409 {103,0x00},
410 {104,0x80},
411 {105,0x00},
412 {106,0x00},
413 {107,0x00},
414 {108,0x7F},
415 {109,0xFF},
416 {110,0xFF},
417 {111,0x00},
418 {112,0x60},
419 {113,0x00},
420 {114,0x00},
421 {115,0x00},
422 {116,0x60},
423 {117,0x00},
424 {118,0x00},
425 {119,0x00},
426 {120,0x40},
427 {121,0x00},
428 {122,0x00},
429 {123,0x00},
430 {124,0x00},
431 {125,0x00},
432 {126,0x00},
433 {127,0x00},
434 { 0,0x0A},
435 { 8,0xFF},
436 { 9,0x9E},
437 { 10,0x00},
438 { 11,0x00},
439 { 12,0x00},
440 { 13,0x00},
441 { 14,0x00},
442 { 15,0x00},
443 { 16,0x7F},
444 { 17,0xFF},
445 { 18,0xFF},
446 { 19,0x00},
447 { 20,0xF7},
448 { 21,0x10},
449 { 22,0x00},
450 { 23,0x00},
451 { 24,0x26},
452 { 25,0xF0},
453 { 26,0x00},
454 { 27,0x00},
455 { 28,0x02},
456 { 29,0x61},
457 { 30,0x00},
458 { 31,0x00},
459 { 32,0x40},
460 { 33,0x02},
461 { 34,0x00},
462 { 35,0x00},
463 { 36,0xFF},
464 { 37,0xFC},
465 { 38,0x00},
466 { 39,0x00},
467 { 40,0xFF},
468 { 41,0xFD},
469 { 42,0x00},
470 { 43,0x00},
471 { 44,0xFF},
472 { 45,0xE5},
473 { 46,0x00},
474 { 47,0x00},
475 { 48,0xFF},
476 { 49,0xA7},
477 { 50,0x00},
478 { 51,0x00},
479 { 52,0xFF},
480 { 53,0xC7},
481 { 54,0x00},
482 { 55,0x00},
483 { 56,0xFF},
484 { 57,0xCE},
485 { 58,0x00},
486 { 59,0x00},
487 { 60,0xFF},
488 { 61,0xFE},
489 { 62,0x00},
490 { 63,0x00},
491 { 64,0xFE},
492 { 65,0xF7},
493 { 66,0x00},
494 { 67,0x00},
495 { 68,0xFF},
496 { 69,0x46},
497 { 70,0x00},
498 { 71,0x00},
499 { 72,0xFF},
500 { 73,0x22},
501 { 74,0x00},
502 { 75,0x00},
503 { 76,0xFF},
504 { 77,0x0F},
505 { 78,0x00},
506 { 79,0x00},
507 { 80,0xFA},
508 { 81,0x8C},
509 { 82,0x00},
510 { 83,0x00},
511 { 84,0xF5},
512 { 85,0x08},
513 { 86,0x00},
514 { 87,0x00},
515 { 88,0xFD},
516 { 89,0x92},
517 { 90,0x00},
518 { 91,0x00},
519 { 92,0xF3},
520 { 93,0xA3},
521 { 94,0x00},
522 { 95,0x00},
523 { 96,0x03},
524 { 97,0xB3},
525 { 98,0x00},
526 { 99,0x00},
527 {100,0x00},
528 {101,0x33},
529 {102,0x00},
530 {103,0x00},
531 {104,0x00},
532 {105,0x71},
533 {106,0x00},
534 {107,0x00},
535 {108,0x40},
536 {109,0x60},
537 {110,0x00},
538 {111,0x00},
539 {112,0x00},
540 {113,0xE2},
541 {114,0x00},
542 {115,0x00},
543 {116,0x00},
544 {117,0xC6},
545 {118,0x00},
546 {119,0x00},
547 {120,0x00},
548 {121,0x87},
549 {122,0x00},
550 {123,0x00},
551 {124,0x00},
552 {125,0x0F},
553 {126,0x00},
554 {127,0x00},
555 { 0,0x0B},
556 { 8,0x00},
557 { 9,0x0A},
558 { 10,0x00},
559 { 11,0x00},
560 { 12,0x00},
561 { 13,0x02},
562 { 14,0x00},
563 { 15,0x00},
564 { 16,0x01},
565 { 17,0x81},
566 { 18,0x00},
567 { 19,0x00},
568 { 20,0x18},
569 { 21,0x89},
570 { 22,0x00},
571 { 23,0x00},
572 { 24,0x07},
573 { 25,0xFB},
574 { 26,0x00},
575 { 27,0x00},
576 { 28,0x03},
577 { 29,0xBE},
578 { 30,0x00},
579 { 31,0x00},
580 { 32,0x00},
581 { 33,0x49},
582 { 34,0x00},
583 { 35,0x00},
584 { 36,0xFF},
585 { 37,0xF2},
586 { 38,0x00},
587 { 39,0x00},
588 { 40,0xF9},
589 { 41,0xBA},
590 { 42,0x00},
591 { 43,0x00},
592 { 44,0xF9},
593 { 45,0x00},
594 { 46,0x00},
595 { 47,0x00},
596 { 48,0xFF},
597 { 49,0x68},
598 { 50,0x00},
599 { 51,0x00},
600 { 52,0xFE},
601 { 53,0x2C},
602 { 54,0x00},
603 { 55,0x00},
604 { 56,0xEB},
605 { 57,0x8D},
606 { 58,0x00},
607 { 59,0x00},
608 { 60,0x03},
609 { 61,0x83},
610 { 62,0x00},
611 { 63,0x00},
612 { 64,0x01},
613 { 65,0xC3},
614 { 66,0x00},
615 { 67,0x00},
616 { 68,0x00},
617 { 69,0xD3},
618 { 70,0x00},
619 { 71,0x00},
620 { 72,0x00},
621 { 73,0x33},
622 { 74,0x00},
623 { 75,0x00},
624 { 76,0x00},
625 { 77,0x02},
626 { 78,0x00},
627 { 79,0x00},
628 { 80,0x32},
629 { 81,0x08},
630 { 82,0x00},
631 { 83,0x00},
632 { 84,0x0A},
633 { 85,0xFA},
634 { 86,0x00},
635 { 87,0x00},
636 { 88,0x54},
637 { 89,0x7B},
638 { 90,0x00},
639 { 91,0x00},
640 { 92,0xFF},
641 { 93,0x6B},
642 { 94,0x00},
643 { 95,0x00},
644 { 96,0xFF},
645 { 97,0x03},
646 { 98,0x00},
647 { 99,0x00},
648 {100,0xFC},
649 {101,0xC6},
650 {102,0x00},
651 {103,0x00},
652 {104,0xF5},
653 {105,0x54},
654 {106,0x00},
655 {107,0x00},
656 {108,0xF9},
657 {109,0x64},
658 {110,0x00},
659 {111,0x00},
660 {112,0x39},
661 {113,0x80},
662 {114,0x00},
663 {115,0x00},
664 {116,0x03},
665 {117,0x1C},
666 {118,0x00},
667 {119,0x00},
668 {120,0x03},
669 {121,0x2F},
670 {122,0x00},
671 {123,0x00},
672 {124,0x00},
673 {125,0x67},
674 {126,0x00},
675 {127,0x00},
676 { 0,0x0C},
677 { 8,0x0F},
678 { 9,0x73},
679 { 10,0x00},
680 { 11,0x00},
681 { 12,0x2C},
682 { 13,0x2B},
683 { 14,0x00},
684 { 15,0x00},
685 { 0,0x0},
686 { 0x7F,0x14},
687 { 0,0x01},
688 { 8,0xC0},
689 { 9,0x00},
690 { 10,0x00},
691 { 11,0x00},
692 { 12,0xC0},
693 { 13,0x00},
694 { 14,0x00},
695 { 15,0x00},
696 { 0,0x0},
697 { 0x7F,0x64},
698 { 0,0x01},
699 { 8,0x00},
700 { 9,0x00},
701 { 10,0x00},
702 { 11,0x00},
703 { 12,0x00},
704 { 13,0x00},
705 { 14,0x00},
706 { 15,0x00},
707 { 16,0x48},
708 { 17,0x02},
709 { 18,0x20},
710 { 19,0x00},
711 { 20,0x48},
712 { 21,0x02},
713 { 22,0x00},
714 { 23,0x00},
715 { 24,0x58},
716 { 25,0x60},
717 { 26,0x08},
718 { 27,0x00},
719 { 28,0x60},
720 { 29,0x60},
721 { 30,0x00},
722 { 31,0x00},
723 { 32,0x00},
724 { 33,0x00},
725 { 34,0x00},
726 { 35,0x00},
727 { 36,0x00},
728 { 37,0x00},
729 { 38,0x00},
730 { 39,0x00},
731 { 40,0x44},
732 { 41,0x00},
733 { 42,0xC0},
734 { 43,0x03},
735 { 44,0x00},
736 { 45,0x00},
737 { 46,0x00},
738 { 47,0x00},
739 { 48,0x00},
740 { 49,0x00},
741 { 50,0x00},
742 { 51,0x00},
743 { 52,0x44},
744 { 53,0x00},
745 { 54,0x00},
746 { 55,0x03},
747 { 56,0x21},
748 { 57,0x00},
749 { 58,0x00},
750 { 59,0x00},
751 { 60,0x03},
752 { 61,0x80},
753 { 62,0x00},
754 { 63,0x20},
755 { 64,0x00},
756 { 65,0x00},
757 { 66,0x00},
758 { 67,0x00},
759 { 68,0x45},
760 { 69,0x02},
761 { 70,0xA0},
762 { 71,0x00},
763 { 72,0x48},
764 { 73,0x05},
765 { 74,0x00},
766 { 75,0x00},
767 { 76,0x00},
768 { 77,0x00},
769 { 78,0x00},
770 { 79,0x00},
771 { 80,0x01},
772 { 81,0x00},
773 { 82,0xA0},
774 { 83,0x10},
775 { 84,0x00},
776 { 85,0x00},
777 { 86,0x00},
778 { 87,0x00},
779 { 88,0x45},
780 { 89,0x02},
781 { 90,0x80},
782 { 91,0x00},
783 { 92,0x58},
784 { 93,0x60},
785 { 94,0x08},
786 { 95,0x01},
787 { 96,0x60},
788 { 97,0x60},
789 { 98,0x00},
790 { 99,0x00},
791 {100,0x58},
792 {101,0x60},
793 {102,0x00},
794 {103,0x0D},
795 {104,0x00},
796 {105,0x00},
797 {106,0x00},
798 {107,0x00},
799 {108,0x44},
800 {109,0x00},
801 {110,0xC0},
802 {111,0x0B},
803 {112,0x04},
804 {113,0x00},
805 {114,0x00},
806 {115,0x00},
807 {116,0x04},
808 {117,0x00},
809 {118,0x20},
810 {119,0x51},
811 {120,0x04},
812 {121,0x00},
813 {122,0x00},
814 {123,0x0D},
815 {124,0x04},
816 {125,0x00},
817 {126,0x20},
818 {127,0x5E},
819 { 0,0x02},
820 { 8,0x04},
821 { 9,0x00},
822 { 10,0x00},
823 { 11,0x08},
824 { 12,0x04},
825 { 13,0x00},
826 { 14,0x20},
827 { 15,0x59},
828 { 16,0x04},
829 { 17,0x00},
830 { 18,0x00},
831 { 19,0x04},
832 { 20,0x04},
833 { 21,0x00},
834 { 22,0x20},
835 { 23,0x55},
836 { 24,0x00},
837 { 25,0x00},
838 { 26,0x00},
839 { 27,0x00},
840 { 28,0x00},
841 { 29,0x00},
842 { 30,0x00},
843 { 31,0x00},
844 { 32,0x44},
845 { 33,0x00},
846 { 34,0x00},
847 { 35,0x0B},
848 { 36,0x21},
849 { 37,0x00},
850 { 38,0x20},
851 { 39,0x00},
852 { 40,0x4B},
853 { 41,0x00},
854 { 42,0xC0},
855 { 43,0x00},
856 { 44,0x4B},
857 { 45,0x00},
858 { 46,0xE0},
859 { 47,0x00},
860 { 48,0x10},
861 { 49,0x00},
862 { 50,0x00},
863 { 51,0x00},
864 { 52,0x10},
865 { 53,0x00},
866 { 54,0x00},
867 { 55,0x51},
868 { 56,0x10},
869 { 57,0x00},
870 { 58,0x00},
871 { 59,0x0D},
872 { 60,0x10},
873 { 61,0x00},
874 { 62,0x00},
875 { 63,0x5E},
876 { 64,0x10},
877 { 65,0x00},
878 { 66,0x00},
879 { 67,0x08},
880 { 68,0x10},
881 { 69,0x00},
882 { 70,0x00},
883 { 71,0x59},
884 { 72,0x10},
885 { 73,0x00},
886 { 74,0x00},
887 { 75,0x04},
888 { 76,0x10},
889 { 77,0x00},
890 { 78,0x00},
891 { 79,0x55},
892 { 80,0x18},
893 { 81,0x02},
894 { 82,0x80},
895 { 83,0x0F},
896 { 84,0x1C},
897 { 85,0x02},
898 { 86,0x60},
899 { 87,0x09},
900 { 88,0x1C},
901 { 89,0x02},
902 { 90,0x60},
903 { 91,0x03},
904 { 92,0x1C},
905 { 93,0x02},
906 { 94,0x40},
907 { 95,0x0A},
908 { 96,0x1C},
909 { 97,0x02},
910 { 98,0x40},
911 { 99,0x02},
912 {100,0x1C},
913 {101,0x02},
914 {102,0x20},
915 {103,0x01},
916 {104,0x1C},
917 {105,0x02},
918 {106,0x20},
919 {107,0x0B},
920 {108,0x1C},
921 {109,0x01},
922 {110,0xC0},
923 {111,0x0C},
924 {112,0x1C},
925 {113,0x01},
926 {114,0xC0},
927 {115,0x00},
928 {116,0x18},
929 {117,0x01},
930 {118,0xC0},
931 {119,0x5D},
932 {120,0x1C},
933 {121,0x01},
934 {122,0xC0},
935 {123,0x51},
936 {124,0x1C},
937 {125,0x02},
938 {126,0x20},
939 {127,0x52},
940 { 0,0x03},
941 { 8,0x10},
942 { 9,0x00},
943 { 10,0x00},
944 { 11,0x2D},
945 { 12,0x1C},
946 { 13,0x02},
947 { 14,0x20},
948 { 15,0x5C},
949 { 16,0x1C},
950 { 17,0x02},
951 { 18,0x40},
952 { 19,0x5B},
953 { 20,0x1C},
954 { 21,0x02},
955 { 22,0x40},
956 { 23,0x53},
957 { 24,0x1C},
958 { 25,0x02},
959 { 26,0x60},
960 { 27,0x5A},
961 { 28,0x1C},
962 { 29,0x02},
963 { 30,0x60},
964 { 31,0x54},
965 { 32,0x1C},
966 { 33,0x02},
967 { 34,0x80},
968 { 35,0x60},
969 { 36,0x00},
970 { 37,0x00},
971 { 38,0x00},
972 { 39,0x00},
973 { 40,0x00},
974 { 41,0x00},
975 { 42,0x00},
976 { 43,0x00},
977 { 44,0x00},
978 { 45,0x00},
979 { 46,0x00},
980 { 47,0x00},
981 { 48,0x10},
982 { 49,0x00},
983 { 50,0x00},
984 { 51,0x7E},
985 { 52,0x18},
986 { 53,0x02},
987 { 54,0xA0},
988 { 55,0x2C},
989 { 56,0x1C},
990 { 57,0x02},
991 { 58,0xA0},
992 { 59,0x2D},
993 { 60,0x1C},
994 { 61,0x02},
995 { 62,0xC0},
996 { 63,0x11},
997 { 64,0x1C},
998 { 65,0x02},
999 { 66,0xC0},
1000 { 67,0x48},
1001 { 68,0x1C},
1002 { 69,0x02},
1003 { 70,0xE0},
1004 { 71,0x2F},
1005 { 72,0x1C},
1006 { 73,0x02},
1007 { 74,0xE0},
1008 { 75,0x2A},
1009 { 76,0x1C},
1010 { 77,0x03},
1011 { 78,0x00},
1012 { 79,0x31},
1013 { 80,0x1C},
1014 { 81,0x03},
1015 { 82,0x00},
1016 { 83,0x28},
1017 { 84,0x1C},
1018 { 85,0x03},
1019 { 86,0x20},
1020 { 87,0x37},
1021 { 88,0x1C},
1022 { 89,0x03},
1023 { 90,0x20},
1024 { 91,0x22},
1025 { 92,0x1C},
1026 { 93,0x03},
1027 { 94,0x40},
1028 { 95,0x14},
1029 { 96,0x1C},
1030 { 97,0x03},
1031 { 98,0x40},
1032 { 99,0x45},
1033 {100,0x1C},
1034 {101,0x03},
1035 {102,0x60},
1036 {103,0x12},
1037 {104,0x1C},
1038 {105,0x03},
1039 {106,0x60},
1040 {107,0x47},
1041 {108,0x1C},
1042 {109,0x03},
1043 {110,0x80},
1044 {111,0x38},
1045 {112,0x1C},
1046 {113,0x03},
1047 {114,0x80},
1048 {115,0x21},
1049 {116,0x1C},
1050 {117,0x03},
1051 {118,0xA0},
1052 {119,0x33},
1053 {120,0x1C},
1054 {121,0x03},
1055 {122,0xA0},
1056 {123,0x26},
1057 {124,0x1C},
1058 {125,0x03},
1059 {126,0xC0},
1060 {127,0x16},
1061 { 0,0x04},
1062 { 8,0x1C},
1063 { 9,0x03},
1064 { 10,0xC0},
1065 { 11,0x43},
1066 { 12,0x1C},
1067 { 13,0x03},
1068 { 14,0xE0},
1069 { 15,0x35},
1070 { 16,0x1C},
1071 { 17,0x03},
1072 { 18,0xE0},
1073 { 19,0x24},
1074 { 20,0x1C},
1075 { 21,0x04},
1076 { 22,0x00},
1077 { 23,0x1A},
1078 { 24,0x1C},
1079 { 25,0x04},
1080 { 26,0x00},
1081 { 27,0x3F},
1082 { 28,0x1C},
1083 { 29,0x04},
1084 { 30,0x20},
1085 { 31,0x3A},
1086 { 32,0x1C},
1087 { 33,0x04},
1088 { 34,0x20},
1089 { 35,0x1F},
1090 { 36,0x1C},
1091 { 37,0x04},
1092 { 38,0x40},
1093 { 39,0x18},
1094 { 40,0x1C},
1095 { 41,0x04},
1096 { 42,0x40},
1097 { 43,0x41},
1098 { 44,0x1C},
1099 { 45,0x04},
1100 { 46,0x60},
1101 { 47,0x1C},
1102 { 48,0x1C},
1103 { 49,0x04},
1104 { 50,0x60},
1105 { 51,0x3D},
1106 { 52,0x1C},
1107 { 53,0x04},
1108 { 54,0x80},
1109 { 55,0x19},
1110 { 56,0x1C},
1111 { 57,0x04},
1112 { 58,0x80},
1113 { 59,0x40},
1114 { 60,0x1C},
1115 { 61,0x04},
1116 { 62,0xA0},
1117 { 63,0x30},
1118 { 64,0x1C},
1119 { 65,0x04},
1120 { 66,0xA0},
1121 { 67,0x29},
1122 { 68,0x1C},
1123 { 69,0x04},
1124 { 70,0xC0},
1125 { 71,0x15},
1126 { 72,0x1C},
1127 { 73,0x04},
1128 { 74,0xC0},
1129 { 75,0x44},
1130 { 76,0x1C},
1131 { 77,0x04},
1132 { 78,0xE0},
1133 { 79,0x3B},
1134 { 80,0x1C},
1135 { 81,0x04},
1136 { 82,0xE0},
1137 { 83,0x1E},
1138 { 84,0x1C},
1139 { 85,0x05},
1140 { 86,0x00},
1141 { 87,0x34},
1142 { 88,0x1C},
1143 { 89,0x05},
1144 { 90,0x00},
1145 { 91,0x25},
1146 { 92,0x1C},
1147 { 93,0x05},
1148 { 94,0x20},
1149 { 95,0x36},
1150 { 96,0x1C},
1151 { 97,0x05},
1152 { 98,0x20},
1153 { 99,0x23},
1154 {100,0x1C},
1155 {101,0x05},
1156 {102,0x40},
1157 {103,0x32},
1158 {104,0x1C},
1159 {105,0x05},
1160 {106,0x40},
1161 {107,0x27},
1162 {108,0x1C},
1163 {109,0x05},
1164 {110,0x60},
1165 {111,0x13},
1166 {112,0x1C},
1167 {113,0x05},
1168 {114,0x60},
1169 {115,0x46},
1170 {116,0x1C},
1171 {117,0x05},
1172 {118,0x80},
1173 {119,0x2E},
1174 {120,0x1C},
1175 {121,0x05},
1176 {122,0x80},
1177 {123,0x2B},
1178 {124,0x1C},
1179 {125,0x05},
1180 {126,0xA0},
1181 {127,0x10},
1182 { 0,0x05},
1183 { 8,0x1C},
1184 { 9,0x05},
1185 { 10,0xA0},
1186 { 11,0x49},
1187 { 12,0x1C},
1188 { 13,0x05},
1189 { 14,0xC0},
1190 { 15,0x17},
1191 { 16,0x1C},
1192 { 17,0x05},
1193 { 18,0xC0},
1194 { 19,0x42},
1195 { 20,0x1C},
1196 { 21,0x05},
1197 { 22,0xE0},
1198 { 23,0x1D},
1199 { 24,0x1C},
1200 { 25,0x05},
1201 { 26,0xE0},
1202 { 27,0x3C},
1203 { 28,0x1C},
1204 { 29,0x06},
1205 { 30,0x00},
1206 { 31,0x1B},
1207 { 32,0x1C},
1208 { 33,0x06},
1209 { 34,0x00},
1210 { 35,0x3E},
1211 { 36,0x1C},
1212 { 37,0x06},
1213 { 38,0x20},
1214 { 39,0x39},
1215 { 40,0x1C},
1216 { 41,0x06},
1217 { 42,0x20},
1218 { 43,0x20},
1219 { 44,0x00},
1220 { 45,0x00},
1221 { 46,0x00},
1222 { 47,0x00},
1223 { 48,0x5C},
1224 { 49,0x90},
1225 { 50,0x40},
1226 { 51,0x00},
1227 { 52,0x00},
1228 { 53,0x00},
1229 { 54,0x00},
1230 { 55,0x00},
1231 { 56,0x5C},
1232 { 57,0x90},
1233 { 58,0x20},
1234 { 59,0x00},
1235 { 60,0x00},
1236 { 61,0x00},
1237 { 62,0x00},
1238 { 63,0x00},
1239 { 64,0x00},
1240 { 65,0x00},
1241 { 66,0x00},
1242 { 67,0x00},
1243 { 68,0x00},
1244 { 69,0x00},
1245 { 70,0x00},
1246 { 71,0x00},
1247 { 72,0x10},
1248 { 73,0x00},
1249 { 74,0x00},
1250 { 75,0x49},
1251 { 76,0x18},
1252 { 77,0x02},
1253 { 78,0x80},
1254 { 79,0x57},
1255 { 80,0x1C},
1256 { 81,0x02},
1257 { 82,0x60},
1258 { 83,0x51},
1259 { 84,0x1C},
1260 { 85,0x02},
1261 { 86,0x60},
1262 { 87,0x5C},
1263 { 88,0x1C},
1264 { 89,0x02},
1265 { 90,0x40},
1266 { 91,0x52},
1267 { 92,0x1C},
1268 { 93,0x02},
1269 { 94,0x40},
1270 { 95,0x5B},
1271 { 96,0x1C},
1272 { 97,0x02},
1273 { 98,0x20},
1274 { 99,0x5A},
1275 {100,0x1C},
1276 {101,0x02},
1277 {102,0x20},
1278 {103,0x53},
1279 {104,0x1C},
1280 {105,0x01},
1281 {106,0xC0},
1282 {107,0x54},
1283 {108,0x1C},
1284 {109,0x01},
1285 {110,0xC0},
1286 {111,0x59},
1287 {112,0x18},
1288 {113,0x01},
1289 {114,0xC0},
1290 {115,0x03},
1291 {116,0x1C},
1292 {117,0x01},
1293 {118,0xC0},
1294 {119,0x08},
1295 {120,0x1C},
1296 {121,0x02},
1297 {122,0x20},
1298 {123,0x09},
1299 {124,0x10},
1300 {125,0x00},
1301 {126,0x00},
1302 {127,0x60},
1303 { 0,0x06},
1304 { 8,0x1C},
1305 { 9,0x02},
1306 { 10,0x20},
1307 { 11,0x02},
1308 { 12,0x1C},
1309 { 13,0x02},
1310 { 14,0x40},
1311 { 15,0x01},
1312 { 16,0x1C},
1313 { 17,0x02},
1314 { 18,0x40},
1315 { 19,0x0A},
1316 { 20,0x1C},
1317 { 21,0x02},
1318 { 22,0x60},
1319 { 23,0x00},
1320 { 24,0x1C},
1321 { 25,0x02},
1322 { 26,0x60},
1323 { 27,0x0B},
1324 { 28,0x1C},
1325 { 29,0x02},
1326 { 30,0x80},
1327 { 31,0x06},
1328 { 32,0x00},
1329 { 33,0x00},
1330 { 34,0x00},
1331 { 35,0x00},
1332 { 36,0x00},
1333 { 37,0x00},
1334 { 38,0x00},
1335 { 39,0x00},
1336 { 40,0x00},
1337 { 41,0x00},
1338 { 42,0x00},
1339 { 43,0x00},
1340 { 44,0x10},
1341 { 45,0x00},
1342 { 46,0x00},
1343 { 47,0x0F},
1344 { 48,0x18},
1345 { 49,0x02},
1346 { 50,0xA0},
1347 { 51,0x7D},
1348 { 52,0x1C},
1349 { 53,0x02},
1350 { 54,0xA0},
1351 { 55,0x7E},
1352 { 56,0x1C},
1353 { 57,0x02},
1354 { 58,0xC0},
1355 { 59,0x62},
1356 { 60,0x1C},
1357 { 61,0x02},
1358 { 62,0xC0},
1359 { 63,0x99},
1360 { 64,0x1C},
1361 { 65,0x02},
1362 { 66,0xE0},
1363 { 67,0x80},
1364 { 68,0x1C},
1365 { 69,0x02},
1366 { 70,0xE0},
1367 { 71,0x7B},
1368 { 72,0x1C},
1369 { 73,0x03},
1370 { 74,0x00},
1371 { 75,0x82},
1372 { 76,0x1C},
1373 { 77,0x03},
1374 { 78,0x00},
1375 { 79,0x79},
1376 { 80,0x1C},
1377 { 81,0x03},
1378 { 82,0x20},
1379 { 83,0x88},
1380 { 84,0x1C},
1381 { 85,0x03},
1382 { 86,0x20},
1383 { 87,0x73},
1384 { 88,0x1C},
1385 { 89,0x03},
1386 { 90,0x40},
1387 { 91,0x65},
1388 { 92,0x1C},
1389 { 93,0x03},
1390 { 94,0x40},
1391 { 95,0x96},
1392 { 96,0x1C},
1393 { 97,0x03},
1394 { 98,0x60},
1395 { 99,0x63},
1396 {100,0x1C},
1397 {101,0x03},
1398 {102,0x60},
1399 {103,0x98},
1400 {104,0x1C},
1401 {105,0x03},
1402 {106,0x80},
1403 {107,0x89},
1404 {108,0x1C},
1405 {109,0x03},
1406 {110,0x80},
1407 {111,0x72},
1408 {112,0x1C},
1409 {113,0x03},
1410 {114,0xA0},
1411 {115,0x84},
1412 {116,0x1C},
1413 {117,0x03},
1414 {118,0xA0},
1415 {119,0x77},
1416 {120,0x1C},
1417 {121,0x03},
1418 {122,0xC0},
1419 {123,0x67},
1420 {124,0x1C},
1421 {125,0x03},
1422 {126,0xC0},
1423 {127,0x94},
1424 { 0,0x07},
1425 { 8,0x1C},
1426 { 9,0x03},
1427 { 10,0xE0},
1428 { 11,0x86},
1429 { 12,0x1C},
1430 { 13,0x03},
1431 { 14,0xE0},
1432 { 15,0x75},
1433 { 16,0x1C},
1434 { 17,0x04},
1435 { 18,0x00},
1436 { 19,0x6B},
1437 { 20,0x1C},
1438 { 21,0x04},
1439 { 22,0x00},
1440 { 23,0x90},
1441 { 24,0x1C},
1442 { 25,0x04},
1443 { 26,0x20},
1444 { 27,0x8B},
1445 { 28,0x1C},
1446 { 29,0x04},
1447 { 30,0x20},
1448 { 31,0x70},
1449 { 32,0x1C},
1450 { 33,0x04},
1451 { 34,0x40},
1452 { 35,0x69},
1453 { 36,0x1C},
1454 { 37,0x04},
1455 { 38,0x40},
1456 { 39,0x92},
1457 { 40,0x1C},
1458 { 41,0x04},
1459 { 42,0x60},
1460 { 43,0x6D},
1461 { 44,0x1C},
1462 { 45,0x04},
1463 { 46,0x60},
1464 { 47,0x8E},
1465 { 48,0x1C},
1466 { 49,0x04},
1467 { 50,0x80},
1468 { 51,0x6A},
1469 { 52,0x1C},
1470 { 53,0x04},
1471 { 54,0x80},
1472 { 55,0x91},
1473 { 56,0x1C},
1474 { 57,0x04},
1475 { 58,0xA0},
1476 { 59,0x81},
1477 { 60,0x1C},
1478 { 61,0x04},
1479 { 62,0xA0},
1480 { 63,0x7A},
1481 { 64,0x1C},
1482 { 65,0x04},
1483 { 66,0xC0},
1484 { 67,0x66},
1485 { 68,0x1C},
1486 { 69,0x04},
1487 { 70,0xC0},
1488 { 71,0x95},
1489 { 72,0x1C},
1490 { 73,0x04},
1491 { 74,0xE0},
1492 { 75,0x8C},
1493 { 76,0x1C},
1494 { 77,0x04},
1495 { 78,0xE0},
1496 { 79,0x6F},
1497 { 80,0x1C},
1498 { 81,0x05},
1499 { 82,0x00},
1500 { 83,0x85},
1501 { 84,0x1C},
1502 { 85,0x05},
1503 { 86,0x00},
1504 { 87,0x76},
1505 { 88,0x1C},
1506 { 89,0x05},
1507 { 90,0x20},
1508 { 91,0x87},
1509 { 92,0x1C},
1510 { 93,0x05},
1511 { 94,0x20},
1512 { 95,0x74},
1513 { 96,0x1C},
1514 { 97,0x05},
1515 { 98,0x40},
1516 { 99,0x83},
1517 {100,0x1C},
1518 {101,0x05},
1519 {102,0x40},
1520 {103,0x78},
1521 {104,0x1C},
1522 {105,0x05},
1523 {106,0x60},
1524 {107,0x64},
1525 {108,0x1C},
1526 {109,0x05},
1527 {110,0x60},
1528 {111,0x97},
1529 {112,0x1C},
1530 {113,0x05},
1531 {114,0x80},
1532 {115,0x7F},
1533 {116,0x1C},
1534 {117,0x05},
1535 {118,0x80},
1536 {119,0x7C},
1537 {120,0x1C},
1538 {121,0x05},
1539 {122,0xA0},
1540 {123,0x61},
1541 {124,0x1C},
1542 {125,0x05},
1543 {126,0xA0},
1544 {127,0x9A},
1545 { 0,0x08},
1546 { 8,0x1C},
1547 { 9,0x05},
1548 { 10,0xC0},
1549 { 11,0x68},
1550 { 12,0x1C},
1551 { 13,0x05},
1552 { 14,0xC0},
1553 { 15,0x93},
1554 { 16,0x1C},
1555 { 17,0x05},
1556 { 18,0xE0},
1557 { 19,0x6E},
1558 { 20,0x1C},
1559 { 21,0x05},
1560 { 22,0xE0},
1561 { 23,0x8D},
1562 { 24,0x1C},
1563 { 25,0x06},
1564 { 26,0x00},
1565 { 27,0x6C},
1566 { 28,0x1C},
1567 { 29,0x06},
1568 { 30,0x00},
1569 { 31,0x8F},
1570 { 32,0x1C},
1571 { 33,0x06},
1572 { 34,0x20},
1573 { 35,0x8A},
1574 { 36,0x1C},
1575 { 37,0x06},
1576 { 38,0x20},
1577 { 39,0x71},
1578 { 40,0x00},
1579 { 41,0x00},
1580 { 42,0x00},
1581 { 43,0x00},
1582 { 44,0x5C},
1583 { 45,0x90},
1584 { 46,0x80},
1585 { 47,0x00},
1586 { 48,0x00},
1587 { 49,0x00},
1588 { 50,0x00},
1589 { 51,0x00},
1590 { 52,0x5C},
1591 { 53,0x90},
1592 { 54,0x60},
1593 { 55,0x00},
1594 { 56,0x00},
1595 { 57,0x00},
1596 { 58,0x00},
1597 { 59,0x00},
1598 { 60,0x00},
1599 { 61,0x00},
1600 { 62,0x00},
1601 { 63,0x00},
1602 { 64,0x00},
1603 { 65,0x00},
1604 { 66,0x00},
1605 { 67,0x00},
1606 { 68,0x10},
1607 { 69,0x00},
1608 { 70,0x00},
1609 { 71,0x9A},
1610 { 72,0x18},
1611 { 73,0x00},
1612 { 74,0x60},
1613 { 75,0x4A},
1614 { 76,0x1C},
1615 { 77,0x00},
1616 { 78,0x80},
1617 { 79,0x4C},
1618 { 80,0x1C},
1619 { 81,0x00},
1620 { 82,0x40},
1621 { 83,0x49},
1622 { 84,0x30},
1623 { 85,0x00},
1624 { 86,0x00},
1625 { 87,0x4C},
1626 { 88,0x1C},
1627 { 89,0x00},
1628 { 90,0x20},
1629 { 91,0x4E},
1630 { 92,0x00},
1631 { 93,0x00},
1632 { 94,0x00},
1633 { 95,0x00},
1634 { 96,0x10},
1635 { 97,0x30},
1636 { 98,0x00},
1637 { 99,0x4B},
1638 {100,0x34},
1639 {101,0x00},
1640 {102,0x00},
1641 {103,0x4B},
1642 {104,0x18},
1643 {105,0x00},
1644 {106,0x60},
1645 {107,0x9B},
1646 {108,0x0C},
1647 {109,0x00},
1648 {110,0x40},
1649 {111,0x00},
1650 {112,0x1C},
1651 {113,0x00},
1652 {114,0x80},
1653 {115,0x9D},
1654 {116,0x10},
1655 {117,0x30},
1656 {118,0x00},
1657 {119,0x4D},
1658 {120,0x1C},
1659 {121,0x00},
1660 {122,0x40},
1661 {123,0x9A},
1662 {124,0x30},
1663 {125,0x00},
1664 {126,0x00},
1665 {127,0x9D},
1666 { 0,0x09},
1667 { 8,0x1C},
1668 { 9,0x00},
1669 { 10,0x20},
1670 { 11,0x9F},
1671 { 12,0x00},
1672 { 13,0x00},
1673 { 14,0x00},
1674 { 15,0x00},
1675 { 16,0x10},
1676 { 17,0x30},
1677 { 18,0x00},
1678 { 19,0x9C},
1679 { 20,0x34},
1680 { 21,0x00},
1681 { 22,0x00},
1682 { 23,0x9C},
1683 { 24,0x5C},
1684 { 25,0x60},
1685 { 26,0xC0},
1686 { 27,0x9C},
1687 { 28,0x0C},
1688 { 29,0x00},
1689 { 30,0x60},
1690 { 31,0x00},
1691 { 32,0x5C},
1692 { 33,0x60},
1693 { 34,0xA0},
1694 { 35,0x4B},
1695 { 36,0x10},
1696 { 37,0x30},
1697 { 38,0x00},
1698 { 39,0x9E},
1699 { 40,0x10},
1700 { 41,0x13},
1701 { 42,0xE0},
1702 { 43,0xA1},
1703 { 44,0x00},
1704 { 45,0x00},
1705 { 46,0x00},
1706 { 47,0x00},
1707 { 48,0x10},
1708 { 49,0x13},
1709 { 50,0xE0},
1710 { 51,0x50},
1711 { 52,0x18},
1712 { 53,0x00},
1713 { 54,0xA0},
1714 { 55,0x50},
1715 { 56,0x1C},
1716 { 57,0x00},
1717 { 58,0xC0},
1718 { 59,0xA1},
1719 { 60,0x00},
1720 { 61,0x00},
1721 { 62,0x00},
1722 { 63,0x00},
1723 { 64,0x00},
1724 { 65,0x00},
1725 { 66,0x00},
1726 { 67,0x00},
1727 { 68,0x00},
1728 { 69,0x00},
1729 { 70,0x00},
1730 { 71,0x00},
1731 { 72,0x10},
1732 { 73,0x00},
1733 { 74,0x00},
1734 { 75,0xA2},
1735 { 76,0x05},
1736 { 77,0x00},
1737 { 78,0x00},
1738 { 79,0xA3},
1739 { 80,0x05},
1740 { 81,0x00},
1741 { 82,0x20},
1742 { 83,0xA4},
1743 { 84,0x18},
1744 { 85,0x01},
1745 { 86,0x40},
1746 { 87,0xA4},
1747 { 88,0x1C},
1748 { 89,0x01},
1749 { 90,0x60},
1750 { 91,0xA2},
1751 { 92,0x00},
1752 { 93,0x00},
1753 { 94,0x00},
1754 { 95,0x00},
1755 { 96,0x00},
1756 { 97,0x00},
1757 { 98,0x00},
1758 { 99,0x00},
1759 {100,0x00},
1760 {101,0x00},
1761 {102,0x00},
1762 {103,0x00},
1763 {104,0x10},
1764 {105,0x00},
1765 {106,0x00},
1766 {107,0xA5},
1767 {108,0x18},
1768 {109,0x01},
1769 {110,0x80},
1770 {111,0xA5},
1771 {112,0x18},
1772 {113,0x01},
1773 {114,0x80},
1774 {115,0xA5},
1775 {116,0x0C},
1776 {117,0x00},
1777 {118,0x00},
1778 {119,0x03},
1779 {120,0x0C},
1780 {121,0x00},
1781 {122,0x20},
1782 {123,0x03},
1783 {124,0x18},
1784 {125,0x01},
1785 {126,0xE0},
1786 {127,0xA3},
1787 { 0,0x0A},
1788 { 8,0x1C},
1789 { 9,0x02},
1790 { 10,0x00},
1791 { 11,0xA2},
1792 { 12,0x00},
1793 { 13,0x00},
1794 { 14,0x00},
1795 { 15,0x00},
1796 { 16,0x00},
1797 { 17,0x00},
1798 { 18,0x00},
1799 { 19,0x00},
1800 { 20,0x00},
1801 { 21,0x00},
1802 { 22,0x00},
1803 { 23,0x00},
1804 { 24,0x10},
1805 { 25,0x00},
1806 { 26,0x00},
1807 { 27,0xA6},
1808 { 28,0x18},
1809 { 29,0x01},
1810 { 30,0x80},
1811 { 31,0xA6},
1812 { 32,0x18},
1813 { 33,0x01},
1814 { 34,0x80},
1815 { 35,0xA6},
1816 { 36,0x0C},
1817 { 37,0x02},
1818 { 38,0x00},
1819 { 39,0x03},
1820 { 40,0x0C},
1821 { 41,0x02},
1822 { 42,0x20},
1823 { 43,0x03},
1824 { 44,0x00},
1825 { 45,0x00},
1826 { 46,0x00},
1827 { 47,0x00},
1828 { 48,0x00},
1829 { 49,0x00},
1830 { 50,0x00},
1831 { 51,0x00},
1832 { 52,0x00},
1833 { 53,0x00},
1834 { 54,0x00},
1835 { 55,0x00},
1836 { 56,0x02},
1837 { 57,0x00},
1838 { 58,0x00},
1839 { 59,0x00},
1840 { 60,0x00},
1841 { 61,0x00},
1842 { 62,0x00},
1843 { 63,0x00},
1844};
1845#define main44_miniDSP_A_reg_values_COEFF_START 0
1846#define main44_miniDSP_A_reg_values_COEFF_SIZE 628
1847#define main44_miniDSP_A_reg_values_INST_START 628
1848#define main44_miniDSP_A_reg_values_INST_SIZE 1148
1849
1850reg_value main44_miniDSP_D_reg_values[] = {
1851 { 0,0x0},
1852 { 0x7F,0x50},
1853 { 0,0x01},
1854 { 8,0xFF},
1855 { 9,0xFF},
1856 { 10,0xFF},
1857 { 11,0x00},
1858 { 12,0x80},
1859 { 13,0x00},
1860 { 14,0x00},
1861 { 15,0x00},
1862 { 16,0x7F},
1863 { 17,0xF7},
1864 { 18,0x00},
1865 { 19,0x00},
1866 { 20,0x80},
1867 { 21,0x09},
1868 { 22,0x00},
1869 { 23,0x00},
1870 { 24,0x7F},
1871 { 25,0xEF},
1872 { 26,0x00},
1873 { 27,0x00},
1874 { 28,0x60},
1875 { 29,0x00},
1876 { 30,0x00},
1877 { 31,0x00},
1878 { 32,0x60},
1879 { 33,0x00},
1880 { 34,0x00},
1881 { 35,0x00},
1882 { 36,0x40},
1883 { 37,0x00},
1884 { 38,0x00},
1885 { 39,0x00},
1886 { 40,0x7F},
1887 { 41,0xFF},
1888 { 42,0xFF},
1889 { 43,0x00},
1890 { 44,0x00},
1891 { 45,0x00},
1892 { 46,0x00},
1893 { 47,0x00},
1894 { 48,0x60},
1895 { 49,0x00},
1896 { 50,0x00},
1897 { 51,0x00},
1898 { 52,0x60},
1899 { 53,0x00},
1900 { 54,0x00},
1901 { 55,0x00},
1902 { 56,0x00},
1903 { 57,0x0D},
1904 { 58,0x00},
1905 { 59,0x00},
1906 { 60,0x00},
1907 { 61,0x1C},
1908 { 62,0x00},
1909 { 63,0x00},
1910 { 64,0x00},
1911 { 65,0x3E},
1912 { 66,0x00},
1913 { 67,0x00},
1914 { 68,0x40},
1915 { 69,0x00},
1916 { 70,0x00},
1917 { 71,0x00},
1918 { 72,0x60},
1919 { 73,0x00},
1920 { 74,0x00},
1921 { 75,0x00},
1922 { 76,0x00},
1923 { 77,0x78},
1924 { 78,0x00},
1925 { 79,0x00},
1926 { 80,0x02},
1927 { 81,0x4C},
1928 { 82,0x00},
1929 { 83,0x00},
1930 { 84,0x00},
1931 { 85,0xD5},
1932 { 86,0x00},
1933 { 87,0x00},
1934 { 88,0x01},
1935 { 89,0x65},
1936 { 90,0x00},
1937 { 91,0x00},
1938 { 92,0x03},
1939 { 93,0xE9},
1940 { 94,0x00},
1941 { 95,0x00},
1942 { 96,0x07},
1943 { 97,0xCA},
1944 { 98,0x00},
1945 { 99,0x00},
1946 {100,0xFF},
1947 {101,0xEF},
1948 {102,0x00},
1949 {103,0x00},
1950 {104,0xFE},
1951 {105,0xEB},
1952 {106,0x00},
1953 {107,0x00},
1954 {108,0xFF},
1955 {109,0xA8},
1956 {110,0x00},
1957 {111,0x00},
1958 {112,0xFD},
1959 {113,0x08},
1960 {114,0x00},
1961 {115,0x00},
1962 {116,0xFF},
1963 {117,0x5E},
1964 {118,0x00},
1965 {119,0x00},
1966 {120,0xFF},
1967 {121,0xD5},
1968 {122,0x00},
1969 {123,0x00},
1970 {124,0xFE},
1971 {125,0x36},
1972 {126,0x00},
1973 {127,0x00},
1974 { 0,0x02},
1975 { 8,0xFA},
1976 { 9,0xAC},
1977 { 10,0x00},
1978 { 11,0x00},
1979 { 12,0xF2},
1980 { 13,0xA3},
1981 { 14,0x00},
1982 { 15,0x00},
1983 { 16,0x28},
1984 { 17,0xAB},
1985 { 18,0x00},
1986 { 19,0x00},
1987 { 20,0x3F},
1988 { 21,0xFF},
1989 { 22,0x00},
1990 { 23,0x00},
1991 { 24,0xFF},
1992 { 25,0x98},
1993 { 26,0x00},
1994 { 27,0x00},
1995 { 28,0xF6},
1996 { 29,0xF9},
1997 { 30,0x00},
1998 { 31,0x00},
1999 { 32,0x26},
2000 { 33,0xFB},
2001 { 34,0x00},
2002 { 35,0x00},
2003 { 36,0x02},
2004 { 37,0x72},
2005 { 38,0x00},
2006 { 39,0x00},
2007 { 40,0x40},
2008 { 41,0x02},
2009 { 42,0x00},
2010 { 43,0x00},
2011 { 44,0xFB},
2012 { 45,0xCB},
2013 { 46,0x00},
2014 { 47,0x00},
2015 { 48,0x20},
2016 { 49,0xA7},
2017 { 50,0x00},
2018 { 51,0x00},
2019 { 52,0xFF},
2020 { 53,0x6A},
2021 { 54,0x00},
2022 { 55,0x00},
2023 { 56,0x3A},
2024 { 57,0x0F},
2025 { 58,0x00},
2026 { 59,0x00},
2027 { 0,0x09},
2028 { 72,0xFF},
2029 { 73,0xFF},
2030 { 74,0xFF},
2031 { 75,0x00},
2032 { 76,0x80},
2033 { 77,0x00},
2034 { 78,0x00},
2035 { 79,0x00},
2036 { 80,0x7F},
2037 { 81,0xF7},
2038 { 82,0x00},
2039 { 83,0x00},
2040 { 84,0x80},
2041 { 85,0x09},
2042 { 86,0x00},
2043 { 87,0x00},
2044 { 88,0x7F},
2045 { 89,0xEF},
2046 { 90,0x00},
2047 { 91,0x00},
2048 { 92,0x60},
2049 { 93,0x00},
2050 { 94,0x00},
2051 { 95,0x00},
2052 { 96,0x60},
2053 { 97,0x00},
2054 { 98,0x00},
2055 { 99,0x00},
2056 {100,0x40},
2057 {101,0x00},
2058 {102,0x00},
2059 {103,0x00},
2060 {104,0x7F},
2061 {105,0xFF},
2062 {106,0xFF},
2063 {107,0x00},
2064 {108,0x00},
2065 {109,0x00},
2066 {110,0x00},
2067 {111,0x00},
2068 {112,0x60},
2069 {113,0x00},
2070 {114,0x00},
2071 {115,0x00},
2072 {116,0x60},
2073 {117,0x00},
2074 {118,0x00},
2075 {119,0x00},
2076 {120,0x00},
2077 {121,0x0D},
2078 {122,0x00},
2079 {123,0x00},
2080 {124,0x00},
2081 {125,0x1C},
2082 {126,0x00},
2083 {127,0x00},
2084 { 0,0x0A},
2085 { 8,0x00},
2086 { 9,0x3E},
2087 { 10,0x00},
2088 { 11,0x00},
2089 { 12,0x40},
2090 { 13,0x00},
2091 { 14,0x00},
2092 { 15,0x00},
2093 { 16,0x60},
2094 { 17,0x00},
2095 { 18,0x00},
2096 { 19,0x00},
2097 { 20,0x00},
2098 { 21,0x78},
2099 { 22,0x00},
2100 { 23,0x00},
2101 { 24,0x02},
2102 { 25,0x4C},
2103 { 26,0x00},
2104 { 27,0x00},
2105 { 28,0x00},
2106 { 29,0xD5},
2107 { 30,0x00},
2108 { 31,0x00},
2109 { 32,0x01},
2110 { 33,0x65},
2111 { 34,0x00},
2112 { 35,0x00},
2113 { 36,0x03},
2114 { 37,0xE9},
2115 { 38,0x00},
2116 { 39,0x00},
2117 { 40,0x07},
2118 { 41,0xCA},
2119 { 42,0x00},
2120 { 43,0x00},
2121 { 44,0xFF},
2122 { 45,0xEF},
2123 { 46,0x00},
2124 { 47,0x00},
2125 { 48,0xFE},
2126 { 49,0xEB},
2127 { 50,0x00},
2128 { 51,0x00},
2129 { 52,0xFF},
2130 { 53,0xA8},
2131 { 54,0x00},
2132 { 55,0x00},
2133 { 56,0xFD},
2134 { 57,0x08},
2135 { 58,0x00},
2136 { 59,0x00},
2137 { 60,0xFF},
2138 { 61,0x5E},
2139 { 62,0x00},
2140 { 63,0x00},
2141 { 64,0xFF},
2142 { 65,0xD5},
2143 { 66,0x00},
2144 { 67,0x00},
2145 { 68,0xFE},
2146 { 69,0x36},
2147 { 70,0x00},
2148 { 71,0x00},
2149 { 72,0xFA},
2150 { 73,0xAC},
2151 { 74,0x00},
2152 { 75,0x00},
2153 { 76,0xF2},
2154 { 77,0xA3},
2155 { 78,0x00},
2156 { 79,0x00},
2157 { 80,0x28},
2158 { 81,0xAB},
2159 { 82,0x00},
2160 { 83,0x00},
2161 { 84,0x3F},
2162 { 85,0xFF},
2163 { 86,0x00},
2164 { 87,0x00},
2165 { 88,0xFF},
2166 { 89,0x98},
2167 { 90,0x00},
2168 { 91,0x00},
2169 { 92,0xF6},
2170 { 93,0xF9},
2171 { 94,0x00},
2172 { 95,0x00},
2173 { 96,0x26},
2174 { 97,0xFB},
2175 { 98,0x00},
2176 { 99,0x00},
2177 {100,0x02},
2178 {101,0x72},
2179 {102,0x00},
2180 {103,0x00},
2181 {104,0x40},
2182 {105,0x02},
2183 {106,0x00},
2184 {107,0x00},
2185 {108,0xFB},
2186 {109,0xCB},
2187 {110,0x00},
2188 {111,0x00},
2189 {112,0x20},
2190 {113,0xA7},
2191 {114,0x00},
2192 {115,0x00},
2193 {116,0xFF},
2194 {117,0x6A},
2195 {118,0x00},
2196 {119,0x00},
2197 {120,0x3A},
2198 {121,0x0F},
2199 {122,0x00},
2200 {123,0x00},
2201 { 0,0x0},
2202 { 0x7F,0x3C},
2203 { 0,0x01},
2204 { 8,0xC0},
2205 { 9,0x00},
2206 { 10,0x00},
2207 { 11,0x00},
2208 { 12,0xC0},
2209 { 13,0x00},
2210 { 14,0x00},
2211 { 15,0x00},
2212 { 0,0x0},
2213 { 0x7F,0x78},
2214 { 0,0x01},
2215 { 8,0x04},
2216 { 9,0x00},
2217 { 10,0x00},
2218 { 11,0x03},
2219 { 12,0x04},
2220 { 13,0x00},
2221 { 14,0x20},
2222 { 15,0x04},
2223 { 16,0x48},
2224 { 17,0x02},
2225 { 18,0x00},
2226 { 19,0x00},
2227 { 20,0x48},
2228 { 21,0x02},
2229 { 22,0x20},
2230 { 23,0x00},
2231 { 24,0x48},
2232 { 25,0x05},
2233 { 26,0x00},
2234 { 27,0x00},
2235 { 28,0x01},
2236 { 29,0x00},
2237 { 30,0x60},
2238 { 31,0x10},
2239 { 32,0x00},
2240 { 33,0x00},
2241 { 34,0x00},
2242 { 35,0x00},
2243 { 36,0x58},
2244 { 37,0x60},
2245 { 38,0x08},
2246 { 39,0x00},
2247 { 40,0x60},
2248 { 41,0x60},
2249 { 42,0x00},
2250 { 43,0x00},
2251 { 44,0x00},
2252 { 45,0x00},
2253 { 46,0x00},
2254 { 47,0x00},
2255 { 48,0x00},
2256 { 49,0x00},
2257 { 50,0x00},
2258 { 51,0x00},
2259 { 52,0x44},
2260 { 53,0x00},
2261 { 54,0xC0},
2262 { 55,0x03},
2263 { 56,0x00},
2264 { 57,0x00},
2265 { 58,0x00},
2266 { 59,0x00},
2267 { 60,0x00},
2268 { 61,0x00},
2269 { 62,0x00},
2270 { 63,0x00},
2271 { 64,0x44},
2272 { 65,0x00},
2273 { 66,0x00},
2274 { 67,0x03},
2275 { 68,0x21},
2276 { 69,0x00},
2277 { 70,0x00},
2278 { 71,0x00},
2279 { 72,0x03},
2280 { 73,0x80},
2281 { 74,0x00},
2282 { 75,0x10},
2283 { 76,0x00},
2284 { 77,0x00},
2285 { 78,0x00},
2286 { 79,0x00},
2287 { 80,0x45},
2288 { 81,0x02},
2289 { 82,0x80},
2290 { 83,0x00},
2291 { 84,0x45},
2292 { 85,0x02},
2293 { 86,0xA0},
2294 { 87,0x00},
2295 { 88,0x58},
2296 { 89,0x60},
2297 { 90,0x08},
2298 { 91,0x01},
2299 { 92,0x60},
2300 { 93,0x60},
2301 { 94,0x00},
2302 { 95,0x00},
2303 { 96,0x58},
2304 { 97,0x60},
2305 { 98,0x00},
2306 { 99,0x09},
2307 {100,0x00},
2308 {101,0x00},
2309 {102,0x00},
2310 {103,0x00},
2311 {104,0x44},
2312 {105,0x00},
2313 {106,0xC0},
2314 {107,0x16},
2315 {108,0x08},
2316 {109,0x00},
2317 {110,0x00},
2318 {111,0x46},
2319 {112,0x08},
2320 {113,0x00},
2321 {114,0x20},
2322 {115,0x86},
2323 {116,0x08},
2324 {117,0x00},
2325 {118,0x00},
2326 {119,0x45},
2327 {120,0x08},
2328 {121,0x00},
2329 {122,0x20},
2330 {123,0x85},
2331 {124,0x08},
2332 {125,0x00},
2333 {126,0x00},
2334 {127,0x44},
2335 { 0,0x02},
2336 { 8,0x08},
2337 { 9,0x00},
2338 { 10,0x20},
2339 { 11,0x84},
2340 { 12,0x08},
2341 { 13,0x00},
2342 { 14,0x00},
2343 { 15,0x43},
2344 { 16,0x08},
2345 { 17,0x00},
2346 { 18,0x20},
2347 { 19,0x83},
2348 { 20,0x08},
2349 { 21,0x00},
2350 { 22,0x00},
2351 { 23,0x42},
2352 { 24,0x08},
2353 { 25,0x00},
2354 { 26,0x20},
2355 { 27,0x82},
2356 { 28,0x08},
2357 { 29,0x00},
2358 { 30,0x00},
2359 { 31,0x41},
2360 { 32,0x08},
2361 { 33,0x00},
2362 { 34,0x20},
2363 { 35,0x81},
2364 { 36,0x08},
2365 { 37,0x00},
2366 { 38,0x00},
2367 { 39,0x40},
2368 { 40,0x08},
2369 { 41,0x00},
2370 { 42,0x20},
2371 { 43,0x80},
2372 { 44,0x08},
2373 { 45,0x00},
2374 { 46,0x00},
2375 { 47,0x3F},
2376 { 48,0x08},
2377 { 49,0x00},
2378 { 50,0x20},
2379 { 51,0x7F},
2380 { 52,0x00},
2381 { 53,0x00},
2382 { 54,0x00},
2383 { 55,0x00},
2384 { 56,0x00},
2385 { 57,0x00},
2386 { 58,0x00},
2387 { 59,0x00},
2388 { 60,0x00},
2389 { 61,0x00},
2390 { 62,0x00},
2391 { 63,0x00},
2392 { 64,0x00},
2393 { 65,0x00},
2394 { 66,0x00},
2395 { 67,0x00},
2396 { 68,0x00},
2397 { 69,0x00},
2398 { 70,0x00},
2399 { 71,0x00},
2400 { 72,0x44},
2401 { 73,0x00},
2402 { 74,0x00},
2403 { 75,0x06},
2404 { 76,0x21},
2405 { 77,0x00},
2406 { 78,0x20},
2407 { 79,0x00},
2408 { 80,0x4B},
2409 { 81,0x00},
2410 { 82,0xC0},
2411 { 83,0x00},
2412 { 84,0x4B},
2413 { 85,0x00},
2414 { 86,0xE0},
2415 { 87,0x00},
2416 { 88,0x00},
2417 { 89,0x00},
2418 { 90,0x40},
2419 { 91,0x48},
2420 { 92,0x0C},
2421 { 93,0x00},
2422 { 94,0x00},
2423 { 95,0x00},
2424 { 96,0x0C},
2425 { 97,0x00},
2426 { 98,0x20},
2427 { 99,0x00},
2428 {100,0x04},
2429 {101,0x02},
2430 {102,0xC0},
2431 {103,0x00},
2432 {104,0x04},
2433 {105,0x02},
2434 {106,0xE0},
2435 {107,0x01},
2436 {108,0x18},
2437 {109,0x01},
2438 {110,0x40},
2439 {111,0x00},
2440 {112,0x1C},
2441 {113,0x01},
2442 {114,0x60},
2443 {115,0x01},
2444 {116,0x00},
2445 {117,0x00},
2446 {118,0x00},
2447 {119,0x00},
2448 {120,0x00},
2449 {121,0x00},
2450 {122,0x00},
2451 {123,0x00},
2452 {124,0x00},
2453 {125,0x00},
2454 {126,0x00},
2455 {127,0x00},
2456 { 0,0x03},
2457 { 8,0x10},
2458 { 9,0x00},
2459 { 10,0x00},
2460 { 11,0x02},
2461 { 12,0x18},
2462 { 13,0x00},
2463 { 14,0xA0},
2464 { 15,0x03},
2465 { 16,0x1C},
2466 { 17,0x00},
2467 { 18,0xC0},
2468 { 19,0x04},
2469 { 20,0x00},
2470 { 21,0x00},
2471 { 22,0x00},
2472 { 23,0x00},
2473 { 24,0x00},
2474 { 25,0x00},
2475 { 26,0x00},
2476 { 27,0x00},
2477 { 28,0x00},
2478 { 29,0x00},
2479 { 30,0x00},
2480 { 31,0x00},
2481 { 32,0x10},
2482 { 33,0x00},
2483 { 34,0x00},
2484 { 35,0x05},
2485 { 36,0x18},
2486 { 37,0x01},
2487 { 38,0xE0},
2488 { 39,0x05},
2489 { 40,0x1C},
2490 { 41,0x02},
2491 { 42,0x00},
2492 { 43,0x02},
2493 { 44,0x00},
2494 { 45,0x00},
2495 { 46,0x00},
2496 { 47,0x00},
2497 { 48,0x00},
2498 { 49,0x00},
2499 { 50,0x00},
2500 { 51,0x00},
2501 { 52,0x00},
2502 { 53,0x00},
2503 { 54,0x00},
2504 { 55,0x00},
2505 { 56,0x10},
2506 { 57,0x00},
2507 { 58,0x00},
2508 { 59,0x06},
2509 { 60,0x18},
2510 { 61,0x00},
2511 { 62,0xE0},
2512 { 63,0x06},
2513 { 64,0x18},
2514 { 65,0x00},
2515 { 66,0xE0},
2516 { 67,0x06},
2517 { 68,0x18},
2518 { 69,0x00},
2519 { 70,0x60},
2520 { 71,0x0A},
2521 { 72,0x1C},
2522 { 73,0x00},
2523 { 74,0x80},
2524 { 75,0x0C},
2525 { 76,0x10},
2526 { 77,0x00},
2527 { 78,0x20},
2528 { 79,0x09},
2529 { 80,0x10},
2530 { 81,0x00},
2531 { 82,0x20},
2532 { 83,0x47},
2533 { 84,0x1C},
2534 { 85,0x00},
2535 { 86,0x40},
2536 { 87,0x09},
2537 { 88,0x18},
2538 { 89,0x00},
2539 { 90,0x60},
2540 { 91,0x48},
2541 { 92,0x1C},
2542 { 93,0x00},
2543 { 94,0x80},
2544 { 95,0x4C},
2545 { 96,0x1C},
2546 { 97,0x00},
2547 { 98,0x40},
2548 { 99,0x47},
2549 {100,0x10},
2550 {101,0x30},
2551 {102,0x00},
2552 {103,0x0B},
2553 {104,0x00},
2554 {105,0x00},
2555 {106,0x00},
2556 {107,0x00},
2557 {108,0x00},
2558 {109,0x00},
2559 {110,0x00},
2560 {111,0x00},
2561 {112,0x10},
2562 {113,0x30},
2563 {114,0x00},
2564 {115,0x4B},
2565 {116,0x18},
2566 {117,0x01},
2567 {118,0x80},
2568 {119,0x30},
2569 {120,0x1C},
2570 {121,0x01},
2571 {122,0xA0},
2572 {123,0x0D},
2573 {124,0x1C},
2574 {125,0x01},
2575 {126,0x80},
2576 {127,0x0B},
2577 { 0,0x04},
2578 { 8,0x1C},
2579 { 9,0x01},
2580 { 10,0xA0},
2581 { 11,0x2E},
2582 { 12,0x1C},
2583 { 13,0x01},
2584 { 14,0xC0},
2585 { 15,0x0F},
2586 { 16,0x1C},
2587 { 17,0x01},
2588 { 18,0xC0},
2589 { 19,0x2C},
2590 { 20,0x1C},
2591 { 21,0x02},
2592 { 22,0x20},
2593 { 23,0x11},
2594 { 24,0x1C},
2595 { 25,0x02},
2596 { 26,0x20},
2597 { 27,0x2A},
2598 { 28,0x1C},
2599 { 29,0x02},
2600 { 30,0x40},
2601 { 31,0x17},
2602 { 32,0x1C},
2603 { 33,0x02},
2604 { 34,0x40},
2605 { 35,0x24},
2606 { 36,0x1C},
2607 { 37,0x02},
2608 { 38,0x60},
2609 { 39,0x13},
2610 { 40,0x1C},
2611 { 41,0x02},
2612 { 42,0x60},
2613 { 43,0x28},
2614 { 44,0x1C},
2615 { 45,0x02},
2616 { 46,0x80},
2617 { 47,0x15},
2618 { 48,0x1C},
2619 { 49,0x02},
2620 { 50,0x80},
2621 { 51,0x26},
2622 { 52,0x1C},
2623 { 53,0x02},
2624 { 54,0xA0},
2625 { 55,0x19},
2626 { 56,0x1C},
2627 { 57,0x02},
2628 { 58,0xA0},
2629 { 59,0x22},
2630 { 60,0x1C},
2631 { 61,0x02},
2632 { 62,0xC0},
2633 { 63,0x1B},
2634 { 64,0x1C},
2635 { 65,0x02},
2636 { 66,0xC0},
2637 { 67,0x20},
2638 { 68,0x1C},
2639 { 69,0x02},
2640 { 70,0xE0},
2641 { 71,0x0C},
2642 { 72,0x1C},
2643 { 73,0x02},
2644 { 74,0xE0},
2645 { 75,0x2F},
2646 { 76,0x1C},
2647 { 77,0x03},
2648 { 78,0x00},
2649 { 79,0x14},
2650 { 80,0x1C},
2651 { 81,0x03},
2652 { 82,0x00},
2653 { 83,0x27},
2654 { 84,0x1C},
2655 { 85,0x03},
2656 { 86,0x20},
2657 { 87,0x10},
2658 { 88,0x1C},
2659 { 89,0x03},
2660 { 90,0x20},
2661 { 91,0x2B},
2662 { 92,0x1C},
2663 { 93,0x03},
2664 { 94,0x40},
2665 { 95,0x18},
2666 { 96,0x1C},
2667 { 97,0x03},
2668 { 98,0x40},
2669 { 99,0x23},
2670 {100,0x1C},
2671 {101,0x03},
2672 {102,0x60},
2673 {103,0x12},
2674 {104,0x1C},
2675 {105,0x03},
2676 {106,0x60},
2677 {107,0x29},
2678 {108,0x1C},
2679 {109,0x03},
2680 {110,0x80},
2681 {111,0x0E},
2682 {112,0x1C},
2683 {113,0x03},
2684 {114,0x80},
2685 {115,0x2D},
2686 {116,0x1C},
2687 {117,0x03},
2688 {118,0xA0},
2689 {119,0x16},
2690 {120,0x1C},
2691 {121,0x03},
2692 {122,0xA0},
2693 {123,0x25},
2694 {124,0x1C},
2695 {125,0x03},
2696 {126,0xC0},
2697 {127,0x1A},
2698 { 0,0x05},
2699 { 8,0x1C},
2700 { 9,0x03},
2701 { 10,0xC0},
2702 { 11,0x21},
2703 { 12,0x1C},
2704 { 13,0x03},
2705 { 14,0xE0},
2706 { 15,0x1C},
2707 { 16,0x1C},
2708 { 17,0x03},
2709 { 18,0xE0},
2710 { 19,0x1F},
2711 { 20,0x1C},
2712 { 21,0x04},
2713 { 22,0x00},
2714 { 23,0x1D},
2715 { 24,0x1C},
2716 { 25,0x04},
2717 { 26,0x00},
2718 { 27,0x1E},
2719 { 28,0x00},
2720 { 29,0x00},
2721 { 30,0x00},
2722 { 31,0x00},
2723 { 32,0x00},
2724 { 33,0x00},
2725 { 34,0x00},
2726 { 35,0x00},
2727 { 36,0x00},
2728 { 37,0x00},
2729 { 38,0x00},
2730 { 39,0x00},
2731 { 40,0x10},
2732 { 41,0x00},
2733 { 42,0x00},
2734 { 43,0x35},
2735 { 44,0x18},
2736 { 45,0x01},
2737 { 46,0x80},
2738 { 47,0x70},
2739 { 48,0x1C},
2740 { 49,0x01},
2741 { 50,0xA0},
2742 { 51,0x4D},
2743 { 52,0x1C},
2744 { 53,0x01},
2745 { 54,0x80},
2746 { 55,0x4B},
2747 { 56,0x1C},
2748 { 57,0x01},
2749 { 58,0xA0},
2750 { 59,0x6E},
2751 { 60,0x1C},
2752 { 61,0x01},
2753 { 62,0xC0},
2754 { 63,0x4F},
2755 { 64,0x1C},
2756 { 65,0x01},
2757 { 66,0xC0},
2758 { 67,0x6C},
2759 { 68,0x1C},
2760 { 69,0x02},
2761 { 70,0x20},
2762 { 71,0x51},
2763 { 72,0x1C},
2764 { 73,0x02},
2765 { 74,0x20},
2766 { 75,0x6A},
2767 { 76,0x1C},
2768 { 77,0x02},
2769 { 78,0x40},
2770 { 79,0x57},
2771 { 80,0x1C},
2772 { 81,0x02},
2773 { 82,0x40},
2774 { 83,0x64},
2775 { 84,0x1C},
2776 { 85,0x02},
2777 { 86,0x60},
2778 { 87,0x53},
2779 { 88,0x1C},
2780 { 89,0x02},
2781 { 90,0x60},
2782 { 91,0x68},
2783 { 92,0x1C},
2784 { 93,0x02},
2785 { 94,0x80},
2786 { 95,0x55},
2787 { 96,0x1C},
2788 { 97,0x02},
2789 { 98,0x80},
2790 { 99,0x66},
2791 {100,0x1C},
2792 {101,0x02},
2793 {102,0xA0},
2794 {103,0x59},
2795 {104,0x1C},
2796 {105,0x02},
2797 {106,0xA0},
2798 {107,0x62},
2799 {108,0x1C},
2800 {109,0x02},
2801 {110,0xC0},
2802 {111,0x5B},
2803 {112,0x1C},
2804 {113,0x02},
2805 {114,0xC0},
2806 {115,0x60},
2807 {116,0x1C},
2808 {117,0x02},
2809 {118,0xE0},
2810 {119,0x4C},
2811 {120,0x1C},
2812 {121,0x02},
2813 {122,0xE0},
2814 {123,0x6F},
2815 {124,0x1C},
2816 {125,0x03},
2817 {126,0x00},
2818 {127,0x54},
2819 { 0,0x06},
2820 { 8,0x1C},
2821 { 9,0x03},
2822 { 10,0x00},
2823 { 11,0x67},
2824 { 12,0x1C},
2825
2826 { 13,0x03},
2827 { 14,0x20},
2828 { 15,0x50},
2829 { 16,0x1C},
2830 { 17,0x03},
2831 { 18,0x20},
2832 { 19,0x6B},
2833 { 20,0x1C},
2834 { 21,0x03},
2835 { 22,0x40},
2836 { 23,0x58},
2837 { 24,0x1C},
2838 { 25,0x03},
2839 { 26,0x40},
2840 { 27,0x63},
2841 { 28,0x1C},
2842 { 29,0x03},
2843 { 30,0x60},
2844 { 31,0x52},
2845 { 32,0x1C},
2846 { 33,0x03},
2847 { 34,0x60},
2848 { 35,0x69},
2849 { 36,0x1C},
2850 { 37,0x03},
2851 { 38,0x80},
2852 { 39,0x4E},
2853 { 40,0x1C},
2854 { 41,0x03},
2855 { 42,0x80},
2856 { 43,0x6D},
2857 { 44,0x1C},
2858 { 45,0x03},
2859 { 46,0xA0},
2860 { 47,0x56},
2861 { 48,0x1C},
2862 { 49,0x03},
2863 { 50,0xA0},
2864 { 51,0x65},
2865 { 52,0x1C},
2866 { 53,0x03},
2867 { 54,0xC0},
2868 { 55,0x5A},
2869 { 56,0x1C},
2870 { 57,0x03},
2871 { 58,0xC0},
2872 { 59,0x61},
2873 { 60,0x1C},
2874 { 61,0x03},
2875 { 62,0xE0},
2876 { 63,0x5C},
2877 { 64,0x1C},
2878 { 65,0x03},
2879 { 66,0xE0},
2880 { 67,0x5F},
2881 { 68,0x1C},
2882 { 69,0x04},
2883 { 70,0x00},
2884 { 71,0x5D},
2885 { 72,0x1C},
2886 { 73,0x04},
2887 { 74,0x00},
2888 { 75,0x5E},
2889 { 76,0x00},
2890 { 77,0x00},
2891 { 78,0x00},
2892 { 79,0x00},
2893 { 80,0x00},
2894 { 81,0x00},
2895 { 82,0x00},
2896 { 83,0x00},
2897 { 84,0x00},
2898 { 85,0x00},
2899 { 86,0x00},
2900 { 87,0x00},
2901 { 88,0x10},
2902 { 89,0x00},
2903 { 90,0x00},
2904 { 91,0x75},
2905 { 92,0x18},
2906 { 93,0x04},
2907 { 94,0x40},
2908 { 95,0x74},
2909 { 96,0x1C},
2910 { 97,0x04},
2911 { 98,0x60},
2912 { 99,0x76},
2913 {100,0x1C},
2914 {101,0x04},
2915 {102,0x60},
2916 {103,0x73},
2917 {104,0x1C},
2918 {105,0x04},
2919 {106,0x40},
2920 {107,0x75},
2921 {108,0x1C},
2922 {109,0x04},
2923 {110,0x80},
2924 {111,0x72},
2925 {112,0x1C},
2926 {113,0x04},
2927 {114,0x80},
2928 {115,0x77},
2929 {116,0x1C},
2930 {117,0x04},
2931 {118,0xA0},
2932 {119,0x71},
2933 {120,0x1C},
2934 {121,0x04},
2935 {122,0xA0},
2936 {123,0x78},
2937 {124,0x18},
2938 {125,0x05},
2939 {126,0x00},
2940 {127,0x79},
2941 { 0,0x07},
2942 { 8,0x1C},
2943 { 9,0x05},
2944 { 10,0x00},
2945 { 11,0x7B},
2946 { 12,0x1C},
2947 { 13,0x04},
2948 { 14,0xE0},
2949 { 15,0x7E},
2950 { 16,0x4C},
2951 { 17,0x04},
2952 { 18,0xE0},
2953 { 19,0x7C},
2954 { 20,0x00},
2955 { 21,0x00},
2956 { 22,0x00},
2957 { 23,0x00},
2958 { 24,0x5C},
2959 { 25,0x90},
2960 { 26,0x60},
2961 { 27,0x03},
2962 { 28,0x18},
2963 { 29,0x04},
2964 { 30,0x40},
2965 { 31,0x34},
2966 { 32,0x1C},
2967 { 33,0x04},
2968 { 34,0x40},
2969 { 35,0x35},
2970 { 36,0x1C},
2971 { 37,0x04},
2972 { 38,0x60},
2973 { 39,0x36},
2974 { 40,0x10},
2975 { 41,0x00},
2976 { 42,0x40},
2977 { 43,0x85},
2978 { 44,0x1C},
2979 { 45,0x04},
2980 { 46,0x60},
2981 { 47,0x33},
2982 { 48,0x1C},
2983 { 49,0x04},
2984 { 50,0x80},
2985 { 51,0x32},
2986 { 52,0x1C},
2987 { 53,0x04},
2988 { 54,0x80},
2989 { 55,0x37},
2990 { 56,0x1C},
2991 { 57,0x04},
2992 { 58,0xA0},
2993 { 59,0x31},
2994 { 60,0x1C},
2995 { 61,0x04},
2996 { 62,0xA0},
2997 { 63,0x38},
2998 { 64,0x18},
2999 { 65,0x05},
3000 { 66,0x00},
3001 { 67,0x39},
3002 { 68,0x1C},
3003 { 69,0x05},
3004 { 70,0x00},
3005 { 71,0x3B},
3006 { 72,0x1C},
3007 { 73,0x04},
3008 { 74,0xE0},
3009 { 75,0x3E},
3010 { 76,0x4C},
3011 { 77,0x04},
3012 { 78,0xE0},
3013 { 79,0x3C},
3014 { 80,0x00},
3015 { 81,0x00},
3016 { 82,0x00},
3017 { 83,0x00},
3018 { 84,0x5C},
3019 { 85,0x90},
3020 { 86,0x40},
3021 { 87,0x03},
3022 { 88,0x00},
3023 { 89,0x00},
3024 { 90,0x00},
3025 { 91,0x00},
3026 { 92,0x00},
3027 { 93,0x00},
3028 { 94,0x00},
3029 { 95,0x00},
3030 { 96,0x00},
3031 { 97,0x00},
3032 { 98,0x00},
3033 { 99,0x00},
3034 {100,0x10},
3035 {101,0x00},
3036 {102,0x40},
3037 {103,0x45},
3038 {104,0x18},
3039 {105,0x05},
3040 {106,0x20},
3041 {107,0x7C},
3042 {108,0x1C},
3043 {109,0x05},
3044 {110,0x20},
3045 {111,0x7B},
3046 {112,0x1C},
3047 {113,0x05},
3048 {114,0x40},
3049 {115,0x79},
3050 {116,0x00},
3051 {117,0x00},
3052 {118,0x00},
3053 {119,0x00},
3054 {120,0x5C},
3055 {121,0x90},
3056 {122,0x60},
3057 {123,0x03},
3058 {124,0x18},
3059 {125,0x05},
3060 {126,0x20},
3061 {127,0x3C},
3062 { 0,0x08},
3063 { 8,0x1C},
3064 { 9,0x05},
3065 { 10,0x20},
3066 { 11,0x3B},
3067 { 12,0x1C},
3068 { 13,0x05},
3069 { 14,0x40},
3070 { 15,0x39},
3071 { 16,0x10},
3072 { 17,0x00},
3073 { 18,0x40},
3074 { 19,0x84},
3075 { 20,0x18},
3076 { 21,0x04},
3077 { 22,0xC0},
3078 { 23,0x72},
3079 { 24,0x5C},
3080 { 25,0x90},
3081 { 26,0x40},
3082 { 27,0x03},
3083 { 28,0x18},
3084 { 29,0x04},
3085 { 30,0xE0},
3086 { 31,0x7B},
3087 { 32,0x1C},
3088 { 33,0x05},
3089 { 34,0x00},
3090 { 35,0x7C},
3091 { 36,0x4C},
3092 { 37,0x04},
3093 { 38,0xE0},
3094 { 39,0x7D},
3095 { 40,0x10},
3096 { 41,0x00},
3097 { 42,0x40},
3098 { 43,0x44},
3099 { 44,0x1C},
3100 { 45,0x05},
3101 { 46,0x00},
3102 { 47,0x79},
3103 { 48,0x18},
3104 { 49,0x04},
3105 { 50,0xC0},
3106 { 51,0x32},
3107 { 52,0x5C},
3108 { 53,0x90},
3109 { 54,0x60},
3110 { 55,0x03},
3111 { 56,0x18},
3112 { 57,0x04},
3113 { 58,0xE0},
3114 { 59,0x3B},
3115 { 60,0x1C},
3116 { 61,0x05},
3117 { 62,0x00},
3118 { 63,0x3C},
3119 { 64,0x4C},
3120 { 65,0x04},
3121 { 66,0xE0},
3122 { 67,0x3D},
3123 { 68,0x10},
3124 { 69,0x00},
3125 { 70,0x40},
3126 { 71,0x83},
3127 { 72,0x1C},
3128 { 73,0x05},
3129 { 74,0x00},
3130 { 75,0x39},
3131 { 76,0x00},
3132 { 77,0x00},
3133 { 78,0x00},
3134 { 79,0x00},
3135 { 80,0x5C},
3136 { 81,0x90},
3137 { 82,0x40},
3138 { 83,0x03},
3139 { 84,0x18},
3140 { 85,0x05},
3141 { 86,0x20},
3142 { 87,0x7D},
3143 { 88,0x1C},
3144 { 89,0x05},
3145 { 90,0x20},
3146 { 91,0x79},
3147 { 92,0x1C},
3148 { 93,0x05},
3149 { 94,0x40},
3150 { 95,0x7C},
3151 { 96,0x10},
3152 { 97,0x00},
3153 { 98,0x40},
3154 { 99,0x43},
3155 {100,0x5C},
3156 {101,0x90},
3157 {102,0x60},
3158 {103,0x03},
3159 {104,0x00},
3160 {105,0x00},
3161 {106,0x00},
3162 {107,0x00},
3163 {108,0x00},
3164 {109,0x00},
3165 {110,0x00},
3166 {111,0x00},
3167 {112,0x00},
3168 {113,0x00},
3169 {114,0x00},
3170 {115,0x00},
3171 {116,0x10},
3172 {117,0x00},
3173 {118,0x40},
3174 {119,0x82},
3175 {120,0x18},
3176 {121,0x05},
3177 {122,0x20},
3178 {123,0x3D},
3179 {124,0x1C},
3180 {125,0x05},
3181 {126,0x20},
3182 {127,0x39},
3183 { 0,0x09},
3184 { 8,0x1C},
3185 { 9,0x05},
3186 { 10,0x40},
3187 { 11,0x3C},
3188 { 12,0x18},
3189 { 13,0x04},
3190 { 14,0x20},
3191 { 15,0x5D},
3192 { 16,0x5C},
3193 { 17,0x90},
3194 { 18,0x40},
3195 { 19,0x03},
3196 { 20,0x18},
3197 { 21,0x04},
3198 { 22,0x40},
3199 { 23,0x78},
3200 { 24,0x1C},
3201 { 25,0x04},
3202 { 26,0x60},
3203 { 27,0x71},
3204 { 28,0x4C},
3205 { 29,0x04},
3206 { 30,0x40},
3207 { 31,0x70},
3208 { 32,0x10},
3209 { 33,0x00},
3210 { 34,0x40},
3211 { 35,0x42},
3212 { 36,0x1C},
3213 { 37,0x04},
3214 { 38,0x60},
3215 { 39,0x77},
3216 { 40,0x1C},
3217 { 41,0x04},
3218 { 42,0x80},
3219 { 43,0x76},
3220 { 44,0x1C},
3221 { 45,0x04},
3222 { 46,0x80},
3223 { 47,0x72},
3224 { 48,0x1C},
3225 { 49,0x04},
3226 { 50,0xA0},
3227 { 51,0x75},
3228 { 52,0x1C},
3229 { 53,0x04},
3230 { 54,0xA0},
3231 { 55,0x73},
3232 { 56,0x18},
3233 { 57,0x05},
3234 { 58,0x00},
3235 { 59,0x7D},
3236 { 60,0x1C},
3237 { 61,0x05},
3238 { 62,0x00},
3239 { 63,0x7C},
3240 { 64,0x1C},
3241 { 65,0x04},
3242 { 66,0xE0},
3243 { 67,0x79},
3244 { 68,0x4C},
3245 { 69,0x04},
3246 { 70,0xE0},
3247 { 71,0x7A},
3248 { 72,0x18},
3249 { 73,0x04},
3250 { 74,0x20},
3251 { 75,0x1D},
3252 { 76,0x5C},
3253 { 77,0x90},
3254 { 78,0x60},
3255 { 79,0x03},
3256 { 80,0x18},
3257 { 81,0x04},
3258 { 82,0x40},
3259 { 83,0x38},
3260 { 84,0x1C},
3261 { 85,0x04},
3262 { 86,0x60},
3263 { 87,0x31},
3264 { 88,0x4C},
3265 { 89,0x04},
3266 { 90,0x40},
3267 { 91,0x30},
3268 { 92,0x10},
3269 { 93,0x00},
3270 { 94,0x40},
3271 { 95,0x81},
3272 { 96,0x1C},
3273 { 97,0x04},
3274 { 98,0x60},
3275 { 99,0x37},
3276 {100,0x1C},
3277 {101,0x04},
3278 {102,0x80},
3279 {103,0x36},
3280 {104,0x1C},
3281 {105,0x04},
3282 {106,0x80},
3283 {107,0x32},
3284 {108,0x1C},
3285 {109,0x04},
3286 {110,0xA0},
3287 {111,0x35},
3288 {112,0x1C},
3289 {113,0x04},
3290 {114,0xA0},
3291 {115,0x33},
3292 {116,0x18},
3293 {117,0x05},
3294 {118,0x00},
3295 {119,0x3D},
3296 {120,0x1C},
3297 {121,0x05},
3298 {122,0x00},
3299 {123,0x3C},
3300 {124,0x1C},
3301 {125,0x04},
3302 {126,0xE0},
3303 {127,0x39},
3304 { 0,0x0A},
3305 { 8,0x4C},
3306 { 9,0x04},
3307 { 10,0xE0},
3308 { 11,0x3A},
3309 { 12,0x00},
3310 { 13,0x00},
3311 { 14,0x00},
3312 { 15,0x00},
3313 { 16,0x5C},
3314 { 17,0x90},
3315 { 18,0x40},
3316 { 19,0x03},
3317 { 20,0x00},
3318 { 21,0x00},
3319 { 22,0x00},
3320 { 23,0x00},
3321 { 24,0x00},
3322 { 25,0x00},
3323 { 26,0x00},
3324 { 27,0x00},
3325 { 28,0x00},
3326 { 29,0x00},
3327 { 30,0x00},
3328 { 31,0x00},
3329 { 32,0x10},
3330 { 33,0x00},
3331 { 34,0x40},
3332 { 35,0x40},
3333 { 36,0x18},
3334 { 37,0x05},
3335 { 38,0x20},
3336 { 39,0x7A},
3337 { 40,0x1C},
3338 { 41,0x05},
3339 { 42,0x20},
3340 { 43,0x7C},
3341 { 44,0x1C},
3342 { 45,0x05},
3343 { 46,0x40},
3344 { 47,0x7D},
3345 { 48,0x10},
3346 { 49,0x00},
3347 { 50,0x40},
3348 { 51,0x41},
3349 { 52,0x00},
3350 { 53,0x00},
3351 { 54,0x00},
3352 { 55,0x00},
3353 { 56,0x5C},
3354 { 57,0x90},
3355 { 58,0x60},
3356 { 59,0x03},
3357 { 60,0x18},
3358 { 61,0x05},
3359 { 62,0x20},
3360 { 63,0x3A},
3361 { 64,0x1C},
3362 { 65,0x05},
3363 { 66,0x20},
3364 { 67,0x3C},
3365 { 68,0x1C},
3366 { 69,0x05},
3367 { 70,0x40},
3368 { 71,0x3D},
3369 { 72,0x10},
3370 { 73,0x00},
3371 { 74,0x40},
3372 { 75,0x80},
3373 { 76,0x18},
3374 { 77,0x04},
3375 { 78,0xC0},
3376 { 79,0x76},
3377 { 80,0x5C},
3378 { 81,0x90},
3379 { 82,0x40},
3380 { 83,0x03},
3381 { 84,0x18},
3382 { 85,0x04},
3383 { 86,0xE0},
3384 { 87,0x7C},
3385 { 88,0x1C},
3386 { 89,0x05},
3387 { 90,0x00},
3388 { 91,0x7A},
3389 { 92,0x4C},
3390 { 93,0x04},
3391 { 94,0xE0},
3392 { 95,0x78},
3393 { 96,0x10},
3394 { 97,0x00},
3395 { 98,0x40},
3396 { 99,0x40},
3397 {100,0x1C},
3398 {101,0x05},
3399 {102,0x00},
3400 {103,0x7D},
3401 {104,0x18},
3402 {105,0x04},
3403 {106,0xC0},
3404 {107,0x36},
3405 {108,0x5C},
3406 {109,0x90},
3407 {110,0x60},
3408 {111,0x03},
3409 {112,0x18},
3410 {113,0x04},
3411 {114,0xE0},
3412 {115,0x3C},
3413 {116,0x1C},
3414 {117,0x05},
3415 {118,0x00},
3416 {119,0x3A},
3417 {120,0x4C},
3418 {121,0x04},
3419 {122,0xE0},
3420 {123,0x38},
3421 {124,0x10},
3422 {125,0x00},
3423 {126,0x40},
3424 {127,0x7F},
3425 { 0,0x0B},
3426 { 8,0x1C},
3427 { 9,0x05},
3428 { 10,0x00},
3429 { 11,0x3D},
3430 { 12,0x00},
3431 { 13,0x00},
3432 { 14,0x00},
3433 { 15,0x00},
3434 { 16,0x5C},
3435 { 17,0x90},
3436 { 18,0x40},
3437 { 19,0x03},
3438 { 20,0x18},
3439 { 21,0x05},
3440 { 22,0x20},
3441 { 23,0x78},
3442 { 24,0x1C},
3443 { 25,0x05},
3444 { 26,0x20},
3445 { 27,0x7D},
3446 { 28,0x1C},
3447 { 29,0x05},
3448 { 30,0x40},
3449 { 31,0x7A},
3450 { 32,0x10},
3451 { 33,0x00},
3452 { 34,0x40},
3453 { 35,0x3F},
3454 { 36,0x00},
3455 { 37,0x00},
3456 { 38,0x00},
3457 { 39,0x00},
3458 { 40,0x5C},
3459 { 41,0x90},
3460 { 42,0x60},
3461 { 43,0x03},
3462 { 44,0x18},
3463 { 45,0x05},
3464 { 46,0x20},
3465 { 47,0x38},
3466 { 48,0x1C},
3467 { 49,0x05},
3468 { 50,0x20},
3469 { 51,0x3D},
3470 { 52,0x1C},
3471 { 53,0x05},
3472 { 54,0x40},
3473 { 55,0x3A},
3474 { 56,0x10},
3475 { 57,0x00},
3476 { 58,0x40},
3477 { 59,0x7E},
3478 { 60,0x5C},
3479 { 61,0x90},
3480 { 62,0x40},
3481 { 63,0x03},
3482 { 64,0x00},
3483 { 65,0x00},
3484 { 66,0x00},
3485 { 67,0x00},
3486 { 68,0x00},
3487 { 69,0x00},
3488 { 70,0x00},
3489 { 71,0x00},
3490 { 72,0x00},
3491 { 73,0x00},
3492 { 74,0x00},
3493 { 75,0x00},
3494 { 76,0x10},
3495 { 77,0x00},
3496 { 78,0x40},
3497 { 79,0x3E},
3498 { 80,0x09},
3499 { 81,0x00},
3500 { 82,0x00},
3501 { 83,0x05},
3502 { 84,0x09},
3503 { 85,0x00},
3504 { 86,0x20},
3505 { 87,0x02},
3506 { 88,0x00},
3507 { 89,0x00},
3508 { 90,0x00},
3509 { 91,0x00},
3510 { 92,0x00},
3511 { 93,0x00},
3512 { 94,0x00},
3513 { 95,0x00},
3514 { 96,0x00},
3515 { 97,0x00},
3516 { 98,0x00},
3517 { 99,0x00},
3518 {100,0x02},
3519 {101,0x00},
3520 {102,0x00},
3521 {103,0x00},
3522 {104,0x00},
3523 {105,0x00},
3524 {106,0x00},
3525 {107,0x00},
3526};
3527#define main44_miniDSP_D_reg_values_COEFF_START 0
3528#define main44_miniDSP_D_reg_values_COEFF_SIZE 361
3529#define main44_miniDSP_D_reg_values_INST_START 361
3530#define main44_miniDSP_D_reg_values_INST_SIZE 1313
3531
3532/* Dummy patches*/
3533
3534reg_value handset_miniDSP_D_reg_values[] = {
3535 { 0,0x0},
3536 { 0x7F,0x50},
3537 { 0,0x06},
3538 { 60,0xBE},
3539 { 61,0xEF},
3540 { 62,0x01},
3541 { 63,0x00},
3542 {104,0x00},
3543 {105,0x80},
3544 {106,0x00},
3545 {107,0x00},
3546 {116,0x04},
3547 {117,0x0B},
3548 {118,0x78},
3549 {119,0x00},
3550 { 0,0x0E},
3551 {124,0xBE},
3552 {125,0xEF},
3553 {126,0x01},
3554 {127,0x00},
3555 { 0,0x0F},
3556 { 48,0x00},
3557 { 49,0x80},
3558 { 50,0x00},
3559 { 51,0x00},
3560 { 60,0x04},
3561 { 61,0x0B},
3562 { 62,0x78},
3563 { 63,0x00},
3564};
3565reg_value handphone_miniDSP_D_reg_values[] = {
3566 { 0,0x0},
3567 { 0x7F,0x50},
3568 { 0,0x06},
3569 { 60,0xBE},
3570 { 61,0xEF},
3571 { 62,0x01},
3572 { 63,0x00},
3573 {104,0x00},
3574 {105,0x80},
3575 {106,0x00},
3576 {107,0x00},
3577 {116,0x04},
3578 {117,0x0B},
3579 {118,0x78},
3580 {119,0x00},
3581 { 0,0x0E},
3582 {124,0xBE},
3583 {125,0xEF},
3584 {126,0x01},
3585 {127,0x00},
3586 { 0,0x0F},
3587 { 48,0x00},
3588 { 49,0x80},
3589 { 50,0x00},
3590 { 51,0x00},
3591 { 60,0x04},
3592 { 61,0x0B},
3593 { 62,0x78},
3594 { 63,0x00},
3595};
3596reg_value speaker_miniDSP_D_reg_values[] = {
3597 { 0,0x0},
3598 { 0x7F,0x50},
3599 { 0,0x06},
3600 { 60,0xBE},
3601 { 61,0xEF},
3602 { 62,0x01},
3603 { 63,0x00},
3604 {104,0x78},
3605 {105,0x00},
3606 {106,0x00},
3607 {107,0x00},
3608 {116,0x04},
3609 {117,0x08},
3610 {118,0x31},
3611 {119,0x00},
3612 { 0,0x0E},
3613 {124,0xBE},
3614 {125,0xEF},
3615 {126,0x01},
3616 {127,0x00},
3617 { 0,0x0F},
3618 { 48,0x78},
3619 { 49,0x00},
3620 { 50,0x00},
3621 { 51,0x00},
3622 { 60,0x04},
3623 { 61,0x08},
3624 { 62,0x31},
3625 { 63,0x00},
3626};
diff --git a/sound/soc/codecs/tlv320aic326x.c b/sound/soc/codecs/tlv320aic326x.c
new file mode 100644
index 00000000000..8bbd295a332
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x.c
@@ -0,0 +1,4528 @@
1/*
2* linux/sound/soc/codecs/tlv320aic3262.c
3*
4* Copyright (C) 2012 Texas Instruments, Inc.
5*
6* Based on sound/soc/codecs/tlv320aic3262.c
7*
8* This package is free software; you can redistribute it and/or modify
9* it under the terms of the GNU General Public License version 2 as
10* published by the Free Software Foundation.
11*
12* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
13* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
14* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15*
16* The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
17* codec with digital microphone inputs and programmable outputs.
18*
19* History:
20*
21* Rev 0.1 ASoC driver support 20-01-2011
22*
23* The AIC325x ASoC driver is ported for the codec AIC3262.
24* Rev 0.2 ASoC driver support 21-03-2011
25* The AIC326x ASoC driver is updated abe changes.
26*
27* Rev 0.3 ASoC driver support 12.09.2011
28* fixed the compilation issues for Whistler support
29*
30* Rev 0.4 ASoC driver support 27.09.2011
31* The AIC326x driver ported for Nvidia cardhu.
32*
33* Rev 0.5 Modified to support Multiple ASI Ports 08-Nov-2011
34* Driver updated to support ASI Ports of AIC3262
35*
36* Modified by Nvidia 23-Nov-2011 for K39 ASoC changes.
37*/
38
39/*
40 *****************************************************************************
41 * INCLUDES
42 *****************************************************************************
43 */
44#include <linux/module.h>
45#include <linux/moduleparam.h>
46#include <linux/kernel.h>
47#include <linux/init.h>
48#include <linux/delay.h>
49#include <linux/pm.h>
50#include <linux/i2c.h>
51#include <linux/platform_device.h>
52#include <linux/slab.h>
53#include <sound/core.h>
54#include <sound/pcm.h>
55#include <sound/pcm_params.h>
56#include <sound/soc.h>
57#include <sound/soc-dapm.h>
58#include <sound/initval.h>
59#include <sound/tlv.h>
60#include <asm/div64.h>
61#include <sound/tlv320aic326x.h>
62#include <sound/jack.h>
63#include <linux/spi/spi.h>
64
65#include "tlv320aic326x.h"
66#include <linux/gpio.h>
67/*
68 *****************************************************************************
69 * Global Variable
70 *****************************************************************************
71 */
72static u8 aic3262_reg_ctl;
73
74#ifdef AIC3262_TiLoad
75 extern int aic3262_driver_init(struct snd_soc_codec *codec);
76#endif
77
78
79
80/* whenever aplay/arecord is run, aic3262_hw_params() function gets called.
81 * This function reprograms the clock dividers etc. this flag can be used to
82 * disable this when the clock dividers are programmed by pps config file
83 */
84static int soc_static_freq_config = 1;
85static struct aic3262_priv *aic3262_priv_data;
86static struct i2c_client *i2c_pdev;
87static struct snd_soc_codec *aic3262_codec;
88
89/*
90 *****************************************************************************
91 * Macros
92 *****************************************************************************
93 */
94
95/* ASoC Widget Control definition for a single Register based Control */
96#define SOC_SINGLE_AIC3262(xname) \
97{\
98 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
99 .info = __new_control_info, .get = __new_control_get,\
100 .put = __new_control_put, \
101 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
102}
103#define SOC_SINGLE_N(xname, xreg, xshift, xmax, xinvert) \
104{\
105 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
106 .info = n_control_info, .get = n_control_get,\
107 .put = n_control_put, \
108 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
109 .private_value = ((unsigned long)&(struct soc_mixer_control)) \
110 {.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \
111 .invert = xinvert} }
112
113/* ASoC Widget Control definition for a Double Register based Control */
114
115#define SOC_DOUBLE_R_N(xname, reg_left, reg_right, xshift, xmax, xinvert) \
116{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
117 .info = snd_soc_info_volsw_2r_n, \
118 .get = snd_soc_get_volsw_2r_n, .put = snd_soc_put_volsw_2r_n, \
119 .private_value = (unsigned long)&(struct soc_mixer_control) \
120 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
121 .max = xmax, .invert = xinvert} }
122
123#define SND_SOC_DAPM_SWITCH_N(wname, wreg, wshift, winvert) \
124{ .id = snd_soc_dapm_switch, .name = wname, .reg = wreg, .shift = wshift,\
125 .invert = winvert, .kcontrols = NULL, .num_kcontrols = 0}
126/*
127 *****************************************************************************
128 * Function Prototype
129 *****************************************************************************
130 */
131static int aic3262_set_bias_level(struct snd_soc_codec *codec,
132 enum snd_soc_bias_level level);
133
134static int __new_control_info(struct snd_kcontrol *kcontrol,
135 struct snd_ctl_elem_info *uinfo);
136
137static int __new_control_get(struct snd_kcontrol *kcontrol,
138 struct snd_ctl_elem_value *ucontrol);
139
140static int __new_control_put(struct snd_kcontrol *kcontrol,
141 struct snd_ctl_elem_value *ucontrol);
142
143static inline int aic3262_get_divs(int mclk, int rate);
144
145static int aic3262_multi_i2s_hw_params(struct snd_pcm_substream *substream,
146 struct snd_pcm_hw_params *params,
147 struct snd_soc_dai *dai);
148
149static int aic3262_multi_i2s_set_dai_sysclk(struct snd_soc_dai *codec_dai,
150 int clk_id, unsigned int freq, int dir);
151static int aic3262_multi_i2s_set_dai_pll(struct snd_soc_dai *codec_dai,
152 int pll_id, int source, unsigned int freq_in,
153 unsigned int freq_out);
154
155static int aic3262_multi_i2s_asi1_set_dai_fmt(struct snd_soc_dai *codec_dai,
156 unsigned int fmt);
157
158static int aic3262_multi_i2s_asi2_set_dai_fmt(struct snd_soc_dai *codec_dai,
159 unsigned int fmt);
160
161static int aic3262_multi_i2s_asi3_set_dai_fmt(struct snd_soc_dai *codec_dai,
162 unsigned int fmt);
163
164static int aic3262_multi_i2s_asi1_mute(struct snd_soc_dai *dai, int mute);
165
166static int aic3262_multi_i2s_asi2_mute(struct snd_soc_dai *dai, int mute);
167
168static int aic3262_multi_i2s_asi3_mute(struct snd_soc_dai *dai, int mute);
169
170#if 0
171static const char *wclk1_pincontrol[] = {
172 "ASI1 Word Clock Input/Output", "CLKOUT output"};
173static const char *dout1_pincontrol[] = {
174 "disabled", "ASI1 data output", "gpio", "clock out",
175 "INT1", "INT2", "SAR ADC interrupt"};
176
177static const char *din1_pincontrol[] = {"disabled", "enabled"};
178
179static const char *wclk2_pincontrol[] = {
180 "diabled", "ASI1 secondary wclk", "general purpose input",
181 "general purpose output", "clkout", "INT1 interrupt",
182 "IN2 interrupt", "output digital microphone",
183 "SAR ADC interrupt", "data output for ASI1"};
184
185static const char *bclk2_pincontrol[] = {
186 "diabled", "ASI1 secondary wclk", "general purpose input",
187 "general purpose output", "clkout", "INT1 interrupt",
188 "IN2 interrupt", "output digital microphone",
189 "SAR ADC interrupt", "data output for ASI1"};
190
191static const char *dout2_pincontrol[] = {
192 "disabled", "ASI2 Data Output", "General Purpose Output",
193 "INT1 Interrupt", "INT2 Interrupt", "SAR ADC interrupt",
194 "Output for digital microphone", "Data Output for ASI1"};
195
196static const char *din2_pincontrol[] = {"disabled", "enabled"};
197
198static const char *wclk3_pincontrol[] = {
199 "Disabled", "ASI3 WCLK", "General Purpose Input",
200 "General Purpose output", "Data Output for ASI1"};
201
202static const char *bclk3_pincontrol[] = {
203 "Disabled", "ASI3 BCLK", "General Purpose Input",
204 "General Purpose output", "Data Output for ASI1"};
205
206static const char *dout3_pincontrol[] = {
207 "disabled", "ASI3 data ooutput", "General Purpose Output",
208 "ASI1 Word Clock Output", "Data Output for ASI1"};
209
210static const char *din3_pincontrol[] = {"disabled", "enabled"};
211
212static const char *clkin[] = {
213 "mclk1", "bclk1", "gpio1", "pll_clk", "bclk2", "gpi1",
214 "hf_ref_clk", "hf_osc_clk", "mclk2", "gpio2", "gpi2"};
215
216#endif
217#ifdef DAC_INDEPENDENT_VOL
218/*
219 *----------------------------------------------------------------------------
220 * Function : n_control_info
221 * Purpose : This function is to initialize data for new control required to
222 * program the AIC3262 registers.
223 *
224 *----------------------------------------------------------------------------
225 */
226static int n_control_info(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_info *uinfo)
228{
229 struct soc_mixer_control *mc =
230 (struct soc_mixer_control *)kcontrol->private_value;
231 int max = mc->max;
232 unsigned int shift = mc->shift;
233 unsigned int rshift = mc->rshift;
234
235 if (max == 1)
236 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
237 else
238 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
239
240 uinfo->count = shift == rshift ? 1 : 2;
241 uinfo->value.integer.min = 0;
242 uinfo->value.integer.max = max;
243 return 0;
244}
245
246/*
247 *----------------------------------------------------------------------------
248 * Function : n_control_get
249 * Purpose : This function is to read data of new control for
250 * program the AIC3262 registers.
251 *
252 *----------------------------------------------------------------------------
253 */
254static int n_control_get(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
256{
257 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
258 u32 val;
259 unsigned short mask, shift;
260 struct soc_mixer_control *mc =
261 (struct soc_mixer_control *)kcontrol->private_value;
262 if (!strcmp(kcontrol->id.name, "Left DAC Volume")) {
263 mask = AIC3262_8BITS_MASK;
264 shift = 0;
265 val = snd_soc_read(codec, mc->reg);
266 ucontrol->value.integer.value[0] =
267 (val <= 48) ? (val + 127) : (val - 129);
268 }
269 if (!strcmp(kcontrol->id.name, "Right DAC Volume")) {
270 mask = AIC3262_8BITS_MASK;
271 shift = 0;
272 val = snd_soc_read(codec, mc->reg);
273 ucontrol->value.integer.value[0] =
274 (val <= 48) ? (val + 127) : (val - 129);
275 }
276
277 return 0;
278}
279
280/*
281 *----------------------------------------------------------------------------
282 * Function : __new_control_put
283 * Purpose : new_control_put is called to pass data from user/application to
284 * the driver.
285 *
286 *----------------------------------------------------------------------------
287 */
288static int n_control_put(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
290{
291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
292 struct soc_mixer_control *mc =
293 (struct soc_mixer_control *)kcontrol->private_value;
294 u8 val, val_mask;
295 int reg, err;
296 unsigned int invert = mc->invert;
297 int max = mc->max;
298 DBG("n_control_put\n");
299 reg = mc->reg;
300 val = ucontrol->value.integer.value[0];
301 if (invert)
302 val = max - val;
303 if (!strcmp(kcontrol->id.name, "Left DAC Volume")) {
304 DBG("LDAC\n");
305 val = (val >= 127) ? (val - 127) : (val + 129);
306 val_mask = AIC3262_8BITS_MASK;
307 }
308 if (!strcmp(kcontrol->id.name, "Right DAC Volume")) {
309 DBG("RDAC\n");
310 val = (val >= 127) ? (val - 127) : (val + 129);
311 val_mask = AIC3262_8BITS_MASK;
312 }
313
314 err = snd_soc_update_bits_locked(codec, reg, val_mask, val);
315 if (err < 0) {
316 printk(KERN_ERR "Error while updating bits\n");
317 return err;
318 }
319
320 return 0;
321}
322#endif /*#ifdef DAC_INDEPENDENT_VOL*/
323/*
324 *------------------------------------------------------------------------------
325 * snd_soc_info_volsw_2r_n - double mixer info callback
326 * @kcontrol: mixer control
327 * @uinfo: control element information
328 *
329 * Callback to provide information about a double mixer control that
330 * spans 2 codec registers.
331 *
332 * Returns 0 for success.
333 *------------------------------------------------------------------------------
334 */
335int snd_soc_info_volsw_2r_n(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_info *uinfo)
337{
338 struct soc_mixer_control *mc =
339 (struct soc_mixer_control *)kcontrol->private_value;
340 int max = mc->max;
341
342 if (max == 1)
343 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
344 else
345 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
346
347 uinfo->count = 2;
348 uinfo->value.integer.min = 0;
349 uinfo->value.integer.max = max;
350 return 0;
351}
352
353/*
354 *------------------------------------------------------------------------------
355 * snd_soc_get_volsw_2r_n - double mixer get callback
356 * @kcontrol: mixer control
357 * @ucontrol: control element information
358 *
359 * Callback to get the value of a double mixer control that spans 2 registers.
360 *
361 * Returns 0 for success.
362 *------------------------------------------------------------------------------
363 */
364int snd_soc_get_volsw_2r_n(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366{
367 struct soc_mixer_control *mc =
368 (struct soc_mixer_control *)kcontrol->private_value;
369 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
370 unsigned int reg = mc->reg;
371 unsigned int reg2 = mc->rreg;
372 unsigned int shift = mc->shift;
373 int max = mc->max;
374 unsigned int mask;
375 unsigned int invert = mc->invert;
376 unsigned short val, val2;
377
378 if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
379 mask = AIC3262_8BITS_MASK;
380 shift = 0;
381 } else if (!strcmp(kcontrol->id.name, "HP Driver Gain")) {
382 mask = 0x3F;
383 shift = 0;
384 } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
385 mask = 0x7F;
386 shift = 0;
387 } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
388 mask = 0x3F;
389 shift = 0;
390 } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
391 mask = 0x7F;
392 shift = 0;
393 } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
394 mask = 0x7F;
395 shift = 0;
396 } else {
397 printk(KERN_ERR "Invalid kcontrol name\n");
398 return -1;
399 }
400
401 /* Read, update the corresponding Registers */
402 val = (snd_soc_read(codec, reg) >> shift) & mask;
403 val2 = (snd_soc_read(codec, reg2) >> shift) & mask;
404
405 if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
406 ucontrol->value.integer.value[0] =
407 (val <= 48) ? (val + 127) : (val - 129);
408 ucontrol->value.integer.value[1] =
409 (val2 <= 48) ? (val2 + 127) : (val2 - 129);
410 } else if (!strcmp(kcontrol->id.name, "HP Driver Gain")) {
411 ucontrol->value.integer.value[0] =
412 (val >= 57) ? (val - 57) : (val + 7);
413 ucontrol->value.integer.value[1] =
414 (val2 >= 57) ? (val2 - 57) : (val2 + 7);
415 } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
416 ucontrol->value.integer.value[0] =
417 (val <= 40) ? (val + 24) : (val - 104);
418 ucontrol->value.integer.value[1] =
419 (val2 <= 40) ? (val2 + 24) : (val2 - 104);
420 } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
421 ucontrol->value.integer.value[0] = ((val >= 0) & (val <= 29)) ?
422 (val + 7) : (val - 57);
423 ucontrol->value.integer.value[1] = ((val2 >= 0) &
424 (val2 <= 29)) ? (val2 + 7) : (val2 - 57);
425
426 } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
427 ucontrol->value.integer.value[0] = ((val >= 0) & (val <= 116)) ?
428 (val + 1) : ((val == 127) ? (0) : (117));
429 ucontrol->value.integer.value[1] = ((val2 >= 0) & (val2 <= 116))
430 ? (val2 + 1) : ((val2 == 127) ? (0) : (117));
431
432 } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
433 ucontrol->value.integer.value[0] = (val <= 40) ?
434 (41 - val) : (val = 0);
435 ucontrol->value.integer.value[1] = (val2 <= 40) ?
436 (41 - val2) : (val2 = 0);
437 }
438
439 if (invert) {
440 ucontrol->value.integer.value[0] =
441 max - ucontrol->value.integer.value[0];
442 ucontrol->value.integer.value[1] =
443 max - ucontrol->value.integer.value[1];
444 }
445
446 return 0;
447}
448/*
449*-------------------------------------------------------------------------------
450* snd_soc_put_volsw_2r_n - double mixer set callback
451* @kcontrol: mixer control
452* @ucontrol: control element information
453*
454* Callback to set the value of a double mixer control that spans 2 registers.
455*
456* Returns 0 for success.
457*-------------------------------------------------------------------------------
458*/
459int snd_soc_put_volsw_2r_n(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
461{
462 struct soc_mixer_control *mc =
463 (struct soc_mixer_control *)kcontrol->private_value;
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
465 unsigned int reg = mc->reg;
466 unsigned int reg2 = mc->rreg;
467 unsigned int shift = mc->shift;
468 int max = mc->max;
469 unsigned int mask;
470 unsigned int invert = mc->invert;
471 int err;
472 unsigned short val, val2, val_mask;
473
474 mask = 0x00FF;
475
476 val = (ucontrol->value.integer.value[0] & mask);
477 val2 = (ucontrol->value.integer.value[1] & mask);
478 if (invert) {
479 val = max - val;
480 val2 = max - val2;
481 }
482
483 /* Check for the string name of the kcontrol */
484 if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
485 val = (val >= 127) ? (val - 127) : (val + 129);
486 val2 = (val2 >= 127) ? (val2 - 127) : (val2 + 129);
487 val_mask = AIC3262_8BITS_MASK; /* 8 bits */
488 } else if ((!strcmp(kcontrol->id.name, "HP Driver Gain")) ||
489 (!strcmp(kcontrol->id.name, "LO Driver Gain"))) {
490 val = (val <= 6) ? (val + 57) : (val - 7);
491 val2 = (val2 <= 6) ? (val2 + 57) : (val2 - 7);
492 val_mask = 0x3F; /* 6 bits */
493 DBG("val=%d, val2=%d", val, val2);
494 } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
495 val = (val >= 24) ? ((val <= 64) ?
496 (val-24) : (40)) : (val + 104);
497 val2 = (val2 >= 24) ?
498 ((val2 <= 64) ? (val2 - 24) : (40)) : (val2 + 104);
499 val_mask = 0x7F; /* 7 bits */
500 } else if (!strcmp(kcontrol->id.name, "LO to REC Volume")) {
501
502 val = (val <= 116) ?
503 (val % 116) : ((val == 117) ? (127) : (117));
504 val2 = (val2 <= 116) ?
505 (val2 % 116) : ((val2 == 117) ? (127) : (117));
506 val_mask = 0x7F;
507 } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
508
509 val = (val <= 7) ? (val + 57) : ((val < 36) ? (val - 7) : (29));
510 val2 = (val2 <= 7) ?
511 (val2 + 57) : ((val2 < 36) ? (val2 - 7) : (29));
512 val_mask = 0x3F;
513 } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
514
515 val = ((val > 0) & (val <= 117)) ?
516 (val - 1) : ((val == 0) ? (127) : (116));
517 val2 = ((val2 > 0) & (val2 <= 117)) ?
518 (val2 - 1) : ((val2 == 0) ? (127) : (116));
519 val_mask = 0x7F;
520 } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
521
522 val = ((val <= 41) & (val > 0)) ?
523 (41 - val) : ((val > 41) ? (val = 41) : (63));
524 val2 = ((val2 <= 41) & (val2 > 0)) ?
525 (41 - val2) : ((val2 > 41) ? (val2 = 41) : (63));
526 val_mask = 0x7F;
527 } else {
528 printk(KERN_ERR "Invalid control name\n");
529 return -1;
530 }
531
532 val = val << shift;
533 val2 = val2 << shift;
534
535 err = snd_soc_update_bits_locked(codec, reg, val_mask, val);
536 if (err < 0)
537 return err;
538
539 err = snd_soc_update_bits_locked(codec, reg2, val_mask, val2);
540 return err;
541}
542
543static int __new_control_info(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_info *uinfo)
545{
546 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
547 uinfo->count = 1;
548 uinfo->value.integer.min = 0;
549 uinfo->value.integer.max = 65535;
550
551 return 0;
552}
553
554/*
555 *----------------------------------------------------------------------------
556 * Function : __new_control_get
557 * Purpose : This function is to read data of new control for
558 * program the AIC3262 registers.
559 *
560 *----------------------------------------------------------------------------
561 */
562static int __new_control_get(struct snd_kcontrol *kcontrol,
563 struct snd_ctl_elem_value *ucontrol)
564{
565 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
566 u32 val;
567 val = snd_soc_read(codec, aic3262_reg_ctl);
568 ucontrol->value.integer.value[0] = val;
569 return 0;
570}
571
572/*
573 *----------------------------------------------------------------------------
574 * Function : __new_control_put
575 * Purpose : new_control_put is called to pass data from user/application to
576 * the driver.
577 *
578 *----------------------------------------------------------------------------
579 */
580static int __new_control_put(struct snd_kcontrol *kcontrol,
581 struct snd_ctl_elem_value *ucontrol)
582{
583 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
584 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
585 u8 data[2];
586 int ret = 0;
587
588 u32 data_from_user = ucontrol->value.integer.value[0];
589
590 aic3262_change_book(codec, 0);
591 aic3262_reg_ctl = data[0] = (u8) ((data_from_user & 0xFF00) >> 8);
592 data[1] = (u8) ((data_from_user & 0x00FF));
593
594 if (!data[0])
595 aic3262->page_no = data[1];
596
597 DBG("reg = %d val = %x\n", data[0], data[1]);
598#if defined(LOCAL_REG_ACCESS)
599 if (codec->hw_write(codec->control_data, data, 2) != 2)
600 ret = -EIO;
601#else
602 ret = snd_soc_write(codec, data[0], data[1]);
603#endif
604 if (ret)
605 printk(KERN_ERR "Error in i2c write\n");
606
607 return ret;
608}
609
610
611/*
612 *****************************************************************************
613 * Structure Initialization
614 *****************************************************************************
615 */
616static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
617static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1200, 50, 0);
618static const DECLARE_TLV_DB_SCALE(spk_gain_tlv, 600, 600, 0);
619static const DECLARE_TLV_DB_SCALE(output_gain_tlv, -600, 100, 0);
620static const DECLARE_TLV_DB_SCALE(micpga_gain_tlv, 0, 50, 0);
621static const DECLARE_TLV_DB_SCALE(adc_fine_gain_tlv, -40, 10, 0);
622static const DECLARE_TLV_DB_SCALE(beep_gen_volume_tlv, -6300, 100, 0);
623
624/* Chip-level Input and Output CM Mode Controls */
625static const char *input_common_mode_text[] = {
626 "0.9v", "0.75v" };
627
628static const char *output_common_mode_text[] = {
629 "Input CM", "1.25v", "1.5v", "1.65v" };
630
631static const struct soc_enum input_cm_mode =
632 SOC_ENUM_SINGLE(CM_REG, 2, 2, input_common_mode_text);
633
634static const struct soc_enum output_cm_mode =
635 SOC_ENUM_SINGLE(CM_REG, 0, 4, output_common_mode_text);
636
637/*
638 *****************************************************************************
639 * Structure Initialization
640 *****************************************************************************
641 */
642static const struct snd_kcontrol_new aic3262_snd_controls[] = {
643 /* Output */
644#ifndef DAC_INDEPENDENT_VOL
645 /* sound new kcontrol for PCM Playback volume control */
646
647 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
648 DAC_LVOL, DAC_RVOL, 8,0xffffff81, 0x30, dac_vol_tlv),
649#endif
650 /*HP Driver Gain Control*/
651 SOC_DOUBLE_R_SX_TLV("HeadPhone Driver Amplifier Volume",
652 HPL_VOL, HPR_VOL, 6, 0xfffffffa, 0xe, output_gain_tlv),
653
654 /*LO Driver Gain Control*/
655 SOC_DOUBLE_TLV("Speaker Amplifier Volume",
656 SPK_AMP_CNTL_R4, 4, 0, 5, 0, spk_gain_tlv),
657
658 SOC_DOUBLE_R_SX_TLV("Receiver Amplifier Volume",
659 REC_AMP_CNTL_R5, RAMPR_VOL, 6, 0xfffffffa, 0x1d, output_gain_tlv),
660
661 SOC_DOUBLE_R_SX_TLV("PCM Capture Volume",
662 LADC_VOL, RADC_VOL, 7,0xffffff68, 0x24, adc_vol_tlv),
663
664
665 SOC_DOUBLE_R_TLV ("MicPGA Volume Control",
666 MICL_PGA, MICR_PGA, 0, 0x5F, 0, micpga_gain_tlv),
667 SOC_DOUBLE_TLV("PCM Capture Fine Gain Volume",
668 ADC_FINE_GAIN, 4, 0, 5, 1, adc_fine_gain_tlv),
669
670 SOC_DOUBLE("ADC channel mute", ADC_FINE_GAIN, 7, 3, 1, 0),
671
672 SOC_DOUBLE("DAC MUTE", DAC_MVOL_CONF, 2, 3, 1, 1),
673
674 /* sound new kcontrol for Programming the registers from user space */
675 SOC_SINGLE_AIC3262("Program Registers"),
676
677 SOC_SINGLE("RESET", RESET_REG, 0,1,0),
678
679 SOC_SINGLE("DAC VOL SOFT STEPPING", DAC_MVOL_CONF, 0, 2, 0),
680
681#ifdef DAC_INDEPENDENT_VOL
682 /*SOC_SINGLE_N("Left DAC Volume", DAC_LVOL, 0, 0xAF, 0),
683 SOC_SINGLE_N("Right DAC Volume", DAC_RVOL, 0, 0xAF, 0),*/
684#endif
685
686 SOC_SINGLE("DAC AUTO MUTE CONTROL", DAC_MVOL_CONF, 4, 7, 0),
687 SOC_SINGLE("RIGHT MODULATOR SETUP", DAC_MVOL_CONF, 7, 1, 0),
688
689 SOC_SINGLE("ADC Volume soft stepping", ADC_CHANNEL_POW, 0, 3, 0),
690
691 SOC_DOUBLE_R("MICPGA enable/disable",MICL_PGA,MICR_PGA,7, 1, 0),
692
693 SOC_SINGLE("Mic Bias ext independent enable", MIC_BIAS_CNTL, 7, 1, 0),
694 SOC_SINGLE("MICBIAS_EXT ON", MIC_BIAS_CNTL, 6, 1, 0),
695 SOC_SINGLE("MICBIAS EXT Power Level", MIC_BIAS_CNTL, 4, 3, 0),
696
697 SOC_SINGLE("MICBIAS_INT ON", MIC_BIAS_CNTL, 2, 1, 0),
698 SOC_SINGLE("MICBIAS INT Power Level", MIC_BIAS_CNTL, 0, 3, 0),
699
700 SOC_DOUBLE("DRC_EN_CTL", DRC_CNTL_R1, 6, 5, 1, 0),
701 SOC_SINGLE("DRC_THRESHOLD_LEVEL", DRC_CNTL_R1, 2, 7, 1),
702 SOC_SINGLE("DRC_HYSTERISIS_LEVEL", DRC_CNTL_R1, 0, 7, 0),
703
704 SOC_SINGLE("DRC_HOLD_LEVEL", DRC_CNTL_R2, 3, 0x0F, 0),
705 SOC_SINGLE("DRC_GAIN_RATE", DRC_CNTL_R2, 0, 4, 0),
706 SOC_SINGLE("DRC_ATTACK_RATE", DRC_CNTL_R3, 4, 0x0F, 1),
707 SOC_SINGLE("DRC_DECAY_RATE", DRC_CNTL_R3, 0, 0x0F, 1),
708
709 SOC_SINGLE("BEEP_GEN_EN", BEEP_CNTL_R1, 7, 1, 0),
710 SOC_DOUBLE_R("BEEP_VOL_CNTL", BEEP_CNTL_R1, BEEP_CNTL_R2, 0, 0x0F, 1),
711 SOC_SINGLE("BEEP_MAS_VOL", BEEP_CNTL_R2, 6, 3, 0),
712
713 SOC_DOUBLE_R("AGC_EN", LAGC_CNTL, RAGC_CNTL, 7, 1, 0),
714 SOC_DOUBLE_R("AGC_TARGET_LEVEL", LAGC_CNTL, RAGC_CNTL, 4, 7, 1),
715
716 SOC_DOUBLE_R("AGC_GAIN_HYSTERESIS", LAGC_CNTL, RAGC_CNTL, 0, 3, 0),
717 SOC_DOUBLE_R("AGC_HYSTERESIS", LAGC_CNTL_R2, RAGC_CNTL_R2, 6, 3, 0),
718 SOC_DOUBLE_R("AGC_NOISE_THRESHOLD", LAGC_CNTL_R2,
719 RAGC_CNTL_R2, 1, 31, 1),
720
721 SOC_DOUBLE_R("AGC_MAX_GAIN", LAGC_CNTL_R3, RAGC_CNTL_R3, 0, 116, 0),
722 SOC_DOUBLE_R("AGC_ATCK_TIME", LAGC_CNTL_R4, RAGC_CNTL_R4, 3, 31, 0),
723 SOC_DOUBLE_R("AGC_ATCK_SCALE_FACTOR",
724 LAGC_CNTL_R4, RAGC_CNTL_R4, 0, 7, 0),
725
726 SOC_DOUBLE_R("AGC_DECAY_TIME", LAGC_CNTL_R5, RAGC_CNTL_R5, 3, 31, 0),
727 SOC_DOUBLE_R("AGC_DECAY_SCALE_FACTOR",
728 LAGC_CNTL_R5, RAGC_CNTL_R5, 0, 7, 0),
729 SOC_DOUBLE_R("AGC_NOISE_DEB_TIME", LAGC_CNTL_R6,
730 RAGC_CNTL_R6, 0, 31, 0),
731
732 SOC_DOUBLE_R("AGC_SGL_DEB_TIME", LAGC_CNTL_R7,
733 RAGC_CNTL_R7, 0, 0x0F, 0),
734
735 SOC_SINGLE("DAC PRB Selection",DAC_PRB, 0, 25, 0),
736 SOC_SINGLE("HP_DEPOP", HP_DEPOP, 0, 255,0),
737 SOC_DOUBLE("IN1 LO BYPASS VOLUME" , LINE_AMP_CNTL_R2, 3, 0, 3, 1),
738 SOC_ENUM("Input CM mode", input_cm_mode),
739 SOC_ENUM("Output CM mode", output_cm_mode),
740};
741
742
743/* the sturcture contains the different values for mclk */
744static const struct aic3262_rate_divs aic3262_divs[] = {
745/*
746 * mclk, rate, p_val, pll_j, pll_d, dosr, ndac, mdac, aosr, nadc, madc, blck_N,
747 * codec_speficic_initializations
748 */
749 /* 8k rate */
750#ifdef CONFIG_MINI_DSP
751 {12000000, 8000, 1, 8, 1920, 768, 8, 2, 128, 8, 12, 4,
752 {{0, 60, 0}, {0, 61, 0} } },
753#else
754 {12000000, 8000, 1, 8, 1920, 128, 12, 8, 128, 8, 6, 4,
755 {{0, 60, 1}, {0, 61, 1} } },
756 {12288000, 8000, 1, 1, 3333, 128, 12, 8, 128, 8, 6, 4,
757 {{0, 60, 1}, {0, 61, 1} } },
758 {24000000, 8000, 1, 4, 96, 128, 12, 8, 128, 12, 8, 4,
759 {{0, 60, 1}, {0, 61, 1} } },
760#endif
761 /* 11.025k rate */
762 {12000000, 11025, 1, 1, 8816, 1024, 8, 2, 128, 8, 2, 48,
763 {{0, 60, 1}, {0, 61, 1} } },
764 {12288000, 11025, 1, 1, 8375, 1024, 8, 2, 128, 8, 2, 48,
765 {{0, 60, 1}, {0, 61, 1} } },
766 {24000000, 11025, 1, 3, 7632, 128, 8, 8, 128, 8, 8, 4,
767 {{0, 60, 1}, {0, 61, 1} } },
768
769 /* 16k rate */
770#ifdef CONFIG_MINI_DSP
771 {12000000, 16000, 1, 8, 1920, 384, 4, 4, 128, 4, 12, 12,
772 {{0, 60, 0}, {0, 61, 0} } },
773 {12288000, 16000, 1, 9, 0, 216, 2, 16, 72, 2, 48, 27,
774 {{0, 60, 0}, {0, 61, 0} } },
775#else
776 {12000000, 16000, 1, 8, 1920, 128, 8, 6, 128, 8, 6, 4,
777 {{0, 60, 1}, {0, 61, 1} } },
778 {12288000, 16000, 1, 2, 6667, 128, 8, 6, 128, 8, 6, 4,
779 {{0, 60, 1}, {0, 61, 1} } },
780 {24000000, 16000, 1, 4, 96, 128, 8, 6, 128, 8, 6, 4,
781 {{0, 60, 1}, {0, 61, 1} } },
782#endif
783 /* 22.05k rate */
784 {12000000, 22050, 1, 3, 7632, 128, 8, 2, 128, 8, 2, 4,
785 {{0, 60, 1}, {0, 61, 1} } },
786 {12288000, 22050, 1, 3, 675, 128, 8, 2, 128, 8, 2, 4,
787 {{0, 60, 1}, {0, 61, 1} } },
788 {24000000, 22050, 1, 3, 7632, 128, 8, 3, 128, 8, 3, 4,
789 {{0, 60, 1}, {0, 61, 1} } },
790 /* 32k rate */
791 {12000000, 32000, 1, 5, 4613, 128, 8, 2, 128, 8, 2, 4,
792 {{0, 60, 1}, {0, 61, 1} } },
793 {12288000, 32000, 1, 5, 3333, 128, 8, 2, 128, 8, 2, 4,
794 {{0, 60, 1}, {0, 61, 1} } },
795 {24000000, 32000, 1, 4, 96, 128, 6, 4, 128, 6, 4, 4,
796 {{0, 60, 1}, {0, 61, 1} } },
797
798#ifdef CONFIG_MINI_DSP
799 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4,
800 {{0, 60, 0}, {0, 61, 0} } },
801 {12288000, 44100, 1, 7, 3548, 128, 2, 8, 128, 8, 2, 4,
802 {{0, 60, 0}, {0, 61, 0} } },
803#else
804 /* 44.1k rate */
805 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2, 4,
806 {{0, 60, 1}, {0, 61, 1} } },
807 {12288000, 44100, 1, 7, 3548, 128, 8, 2, 128, 8, 2, 4,
808 {{0, 60, 1}, {0, 61, 1} } },
809 {24000000, 44100, 1, 3, 7632, 128, 4, 4, 64, 4, 4, 4,
810 {{0, 60, 1}, {0, 61, 1} } },
811#endif
812
813#ifdef CONFIG_MINI_DSP
814 {12288000, 48000, 1, 8, 52, 128, 2, 8, 128, 2, 8, 4,
815 {{0, 60, 0}, {0, 61, 0} } },
816 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4,
817 {{0, 60, 0}, {0, 61, 0}}},
818#else
819 /* 48k rate */
820 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2, 4,
821 {{0, 60, 1}, {0, 61, 1} } },
822 {12288000, 48000, 1, 8, 52, 128, 8, 2, 128, 8, 2, 4,
823 {{0, 60, 1}, {0, 61, 1} } },
824 {24000000, 48000, 1, 4, 960, 128, 4, 4, 128, 4, 4, 4,
825 {{0, 60, 1}, {0, 61, 1} } },
826#endif
827
828 /*96k rate */
829 {12000000, 96000, 1, 16, 3840, 128, 8, 2, 128, 8, 2 , 4,
830 {{0, 60, 7}, {0, 61, 7} } },
831 {24000000, 96000, 1, 4, 960, 128, 4, 2, 128, 4, 2, 2,
832 {{0, 60, 7}, {0, 61, 7} } },
833 /*192k */
834 {12000000, 192000, 1, 32, 7680, 128, 8, 2, 128, 8, 2, 4,
835 {{0, 60, 17}, {0, 61, 13} } },
836 {24000000, 192000, 1, 4, 960, 128, 2, 2, 128, 2, 2, 4,
837 {{0, 60, 17}, {0, 61, 13} } },
838};
839
840
841
842/*
843*----------------------------------------------------------------------------
844* Function : aic3262_multi_i2s_dump_regs
845* Purpose : This function is to mute or unmute the left and right DAC
846*
847*----------------------------------------------------------------------------
848*/
849static void aic3262_multi_i2s_dump_regs(struct snd_soc_dai *dai)
850{
851 struct snd_soc_codec *codec = dai->codec;
852 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
853 unsigned int counter;
854
855 DBG(KERN_INFO "#%s: Dai Active %d ASI%d REGS DUMP\n",
856 __func__, aic3262->active_count, dai->id);
857
858 aic3262_change_page(codec, 0);
859 aic3262_change_book(codec, 0);
860
861 DBG(KERN_INFO "#Page0 REGS..\n");
862 for (counter = 0; counter < 85; counter++) {
863 DBG(KERN_INFO "#%2d -> 0x%x\n", counter,
864 snd_soc_read(codec, counter));
865 }
866
867 DBG(KERN_INFO "#Page1 REGS..\n");
868 for (counter = 128; counter < 176; counter++) {
869 DBG(KERN_INFO "#%2d -> 0x%x\n", (counter % 128),
870 snd_soc_read(codec, counter));
871 }
872
873 DBG(KERN_INFO "#Page4 REGS..\n");
874 for (counter = 512; counter < 631; counter++) {
875 DBG(KERN_INFO "#%2d -> 0x%x\n",
876 (counter % 128), snd_soc_read(codec, counter));
877 }
878
879 for (counter = 0; counter < MAX_ASI_COUNT; counter++) {
880 DBG(KERN_INFO "#ASI%d Frame %s @ %dHz Playback %d Record %d\n",
881 (counter + 1),
882 (aic3262->asiCtxt[counter].master == 1) ? "Master" : "Slave",
883 aic3262->asiCtxt[counter].sampling_rate,
884 aic3262->asiCtxt[counter].playback_mode,
885 aic3262->asiCtxt[counter].capture_mode);
886 DBG(KERN_INFO "#DAC Option [%d,%d] ADC Option %d WLEN %d\n\n",
887 aic3262->asiCtxt[counter].left_dac_output,
888 aic3262->asiCtxt[counter].right_dac_output,
889 aic3262->asiCtxt[counter].adc_input,
890 aic3262->asiCtxt[counter].word_len);
891 }
892 return;
893}
894
895/*
896 *----------------------------------------------------------------------------
897 * Function : aic3262_multi_i2s_mute
898 * Purpose : This function is to mute or unmute the left and right DAC
899 *
900 *----------------------------------------------------------------------------
901 */
902static int aic3262_multi_i2s_mute(struct snd_soc_dai *dai, int mute)
903{
904 struct snd_soc_codec *codec = dai->codec;
905 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
906
907 DBG(KERN_INFO "#%s : mute entered with %d\n", __func__, mute);
908
909 /* If we are doing both Recording and Playback on this DAI interface,
910 * do not MUTE the Codec.
911 */
912 if (mute && (aic3262->asiCtxt[dai->id - 1].asi_active > 1)) {
913 DBG("#%s Cannot Mute the ASI%d Now..\n",
914 __func__, dai->id);
915 } else {
916 switch (dai->id) {
917 case 1:
918 aic3262_multi_i2s_asi1_mute(dai, mute);
919 break;
920 case 2:
921 aic3262_multi_i2s_asi2_mute(dai, mute);
922 break;
923 case 3:
924 aic3262_multi_i2s_asi3_mute(dai, mute);
925 break;
926 default:
927 printk(KERN_ERR "#%s: Invalid DAI id\n", __func__);
928 return -EINVAL;
929 }
930 }
931 DBG(KERN_INFO "#%s : mute ended\n", __func__);
932 return 0;
933}
934
935
936/*
937*----------------------------------------------------------------------------
938* Function : aic3262_multi_i2s_asi1_mute
939* Purpose : This function is to mute or unmute the left and right DAC
940*
941*----------------------------------------------------------------------------
942*/
943static int aic3262_multi_i2s_asi1_mute(struct snd_soc_dai *dai, int mute)
944{
945 struct snd_soc_codec *codec = dai->codec;
946 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
947
948 DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
949
950 if (mute && !aic3262->asiCtxt[0].port_muted ) {
951 DBG(KERN_INFO "Mute if part\n");
952
953
954 snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
955
956 /* First check if both Playback and Recording is going on
957 * this interface.
958 */
959 if (aic3262->asiCtxt[0].asi_active > 1) {
960 DBG("#%s Cannot Mute the ASI Now..\n", __func__);
961 } else if (!(aic3262->asiCtxt[1].playback_mode) &&
962 !(aic3262->asiCtxt[2].playback_mode)) {
963 /* Before Muting, please check if any other
964 * ASI is active. if so, we cannot simply mute the
965 * DAC and ADC Registers.
966 */
967 DBG("#%s None of the ASI's are active now..\n", __func__);
968 snd_soc_write(codec, DAC_MVOL_CONF,
969 ((aic3262->dac_reg & 0xF3) | 0x0C));
970 snd_soc_write(codec, ADC_FINE_GAIN,
971 ((aic3262->adc_gain & 0x77) | 0x88));
972 snd_soc_write(codec, HPL_VOL, 0xB9);
973 snd_soc_write(codec, HPR_VOL, 0xB9);
974 snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
975 snd_soc_write(codec, RAMPR_VOL, 0x39);
976 snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
977 aic3262->asiCtxt[0].port_muted = 1;
978 }
979 } else {
980 DBG(KERN_INFO "Mute else part\n");
981 snd_soc_update_bits(codec, DAC_MVOL_CONF,
982 DAC_LR_MUTE_MASK, 0x0);
983 snd_soc_write(codec, ADC_FINE_GAIN,(0X00 & 0x77) | 0x0);
984 aic3262_multi_i2s_dump_regs(dai);
985 }
986
987 DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
988
989 return 0;
990}
991
992/*
993*----------------------------------------------------------------------------
994* Function : aic3262_multi_i2s_asi2_maic3262_asi3_clk_configute
995* Purpose : This function is to mute or unmute the left and right DAC
996*
997*----------------------------------------------------------------------------
998*/
999static int aic3262_multi_i2s_asi2_mute(struct snd_soc_dai *dai, int mute)
1000{
1001 struct snd_soc_codec *codec = dai->codec;
1002 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1003
1004 DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
1005
1006 if (mute && !aic3262->asiCtxt[1].port_muted ) {
1007 DBG(KERN_INFO "Mute if part\n");
1008 snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
1009
1010 /* First check if both Playback and Recording is going on
1011 * this interface.
1012 */
1013 if (aic3262->asiCtxt[1].asi_active > 1) {
1014 DBG("#%s Cannot Mute the ASI Now..\n", __func__);
1015 } else if (!(aic3262->asiCtxt[0].playback_mode) &&
1016 !(aic3262->asiCtxt[2].playback_mode)) {
1017 /* Before Muting, please check if any other
1018 * ASI is active. if so, we cannot simply mute the
1019 * DAC and ADC Registers.
1020 */
1021 snd_soc_write(codec, DAC_MVOL_CONF,
1022 ((aic3262->dac_reg & 0xF3) | 0x0C));
1023 snd_soc_write(codec, ADC_FINE_GAIN,
1024 ((aic3262->adc_gain & 0x77) | 0x88));
1025 snd_soc_write(codec, HPL_VOL, 0xB9);
1026 snd_soc_write(codec, HPR_VOL, 0xB9);
1027 snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
1028 snd_soc_write(codec, RAMPR_VOL, 0x39);
1029 snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
1030 aic3262->asiCtxt[1].port_muted = 1;
1031 }
1032 } else {
1033 DBG(KERN_INFO "Mute else part\n");
1034 snd_soc_update_bits(codec, DAC_MVOL_CONF,
1035 DAC_LR_MUTE_MASK, 0x0);
1036
1037 /*aic3262_multi_i2s_dump_regs(dai);*/
1038 }
1039
1040 DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
1041
1042 return 0;
1043}
1044
1045/*
1046*----------------------------------------------------------------------------
1047* Function : aic3262_multi_i2s_asi3_mute
1048* Purpose : This function is to mute or unmute the left and right DAC
1049*
1050*----------------------------------------------------------------------------
1051*/
1052static int aic3262_multi_i2s_asi3_mute(struct snd_soc_dai *dai, int mute)
1053{
1054 struct snd_soc_codec *codec = dai->codec;
1055 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1056
1057 DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
1058
1059 if (mute && !aic3262->asiCtxt[2].port_muted) {
1060 DBG("Mute if part\n");
1061 snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
1062
1063 /* First check if both Playback and Recording is going on
1064 * this interface.
1065 */
1066 if (aic3262->asiCtxt[2].asi_active > 1) {
1067 DBG("#%s Cannot Mute the ASI Now..\n", __func__);
1068 } else if (!(aic3262->asiCtxt[0].playback_mode) &&
1069 !(aic3262->asiCtxt[1].playback_mode)) {
1070 /* Before Muting, please check if any other
1071 * ASI is active. if so, we cannot simply mute the
1072 * DAC and ADC Registers.
1073 */
1074 snd_soc_write(codec, DAC_MVOL_CONF,
1075 ((aic3262->dac_reg & 0xF3) | 0x0C));
1076 snd_soc_write(codec, ADC_FINE_GAIN,
1077 ((aic3262->adc_gain & 0x77) | 0x88));
1078 snd_soc_write(codec, HPL_VOL, 0xB9);
1079 snd_soc_write(codec, HPR_VOL, 0xB9);
1080 snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
1081 snd_soc_write(codec, RAMPR_VOL, 0x39);
1082 snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
1083 aic3262->asiCtxt[2].port_muted = 1;
1084 }
1085 } else {
1086 DBG("Mute else part\n");
1087 snd_soc_update_bits(codec, DAC_MVOL_CONF,
1088 DAC_LR_MUTE_MASK, 0x0);
1089
1090 /*aic3262_multi_i2s_dump_regs(dai);*/
1091
1092 }
1093
1094 DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
1095
1096 return 0;
1097}
1098
1099/*
1100 *----------------------------------------------------------------------------
1101 * Function : aic3262_multi_i2s_set_dai_fmt
1102 * Purpose : This function is to set the DAI format
1103 *
1104 *----------------------------------------------------------------------------
1105 */
1106static int aic3262_multi_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1107 unsigned int fmt)
1108{
1109 /* Check the DAI Id and based on that switch the configuration for
1110 * the Individual ASI Port.
1111 */
1112 switch (codec_dai->id) {
1113 case 1:
1114 aic3262_multi_i2s_asi1_set_dai_fmt(codec_dai, fmt);
1115 break;
1116 case 2:
1117 aic3262_multi_i2s_asi2_set_dai_fmt(codec_dai, fmt);
1118 break;
1119 case 3:
1120 aic3262_multi_i2s_asi3_set_dai_fmt(codec_dai, fmt);
1121 break;
1122 default:
1123 printk(KERN_ERR
1124 "#%s: Invalid DAI interface format\n", __func__);
1125 return -EINVAL;
1126 }
1127 return 0;
1128}
1129
1130
1131
1132/*
1133*----------------------------------------------------------------------------
1134* Function : aic3262_multi_i2s_asi1_set_dai_fmt
1135* Purpose : This function is to set the DAI format for ASI1 Port
1136*
1137*----------------------------------------------------------------------------
1138*/
1139static int aic3262_multi_i2s_asi1_set_dai_fmt(struct snd_soc_dai *codec_dai,
1140 unsigned int fmt)
1141{
1142 struct snd_soc_codec *codec = codec_dai->codec;
1143 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1144 u8 iface_reg, clk_reg;
1145 u8 regvalue;
1146
1147 DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
1148 __func__, codec_dai->id, fmt);
1149
1150 /* Read the B0_P4_R4 and B0_P4_R10 Registers to configure the
1151 * ASI1 Bus and Clock Formats depending on the PCM Format.
1152 */
1153 iface_reg = snd_soc_read(codec, ASI1_BUS_FMT);
1154 clk_reg = snd_soc_read(codec, ASI1_BWCLK_CNTL_REG);
1155
1156 /* set master/slave audio interface */
1157 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1158 case SND_SOC_DAIFMT_CBM_CFM:
1159 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
1160 __func__, codec_dai->id);
1161 aic3262->asiCtxt[0].master = 1;
1162 clk_reg |= (BIT5 | BIT2); /* Codec Interface as Master */
1163 break;
1164 case SND_SOC_DAIFMT_CBS_CFS:
1165 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
1166 __func__, codec_dai->id);
1167 clk_reg &= ~0xFC; /* Reset bits D[7:5] and D[4:2] to zero */
1168 aic3262->asiCtxt[0].master = 0;
1169 break;
1170 case SND_SOC_DAIFMT_CBS_CFM:
1171 /* new case..just for debugging */
1172 DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
1173 aic3262->asiCtxt[0].master = 0;
1174 clk_reg |= BIT5; /* Only WCLK1 Output from Codec */
1175 clk_reg &= ~0x1C; /* BCLK1 Input to Codec */
1176 break;
1177 default:
1178 printk(KERN_ERR "#%s: Invalid DAI master/slave interface\n",
1179 __func__);
1180 return -EINVAL;
1181 }
1182 aic3262->asiCtxt[0].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1183 /* interface format */
1184 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1185 case SND_SOC_DAIFMT_I2S:
1186 DBG(KERN_INFO "#%s: Configuring ASI%d for I2s Mode..\n",
1187 __func__, codec_dai->id);
1188 iface_reg = (iface_reg & 0x1f);
1189 break;
1190 case SND_SOC_DAIFMT_DSP_A:
1191 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
1192 __func__, codec_dai->id);
1193 iface_reg = (iface_reg & 0x1f) | 0x20;
1194 break;
1195 case SND_SOC_DAIFMT_RIGHT_J:
1196 iface_reg = (iface_reg & 0x1f) | 0x40;
1197 break;
1198 case SND_SOC_DAIFMT_LEFT_J:
1199 iface_reg = (iface_reg & 0x1f) | 0x60;
1200 break;
1201 case SND_SOC_DAIFMT_DSP_B:
1202 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_B Mode..\n",
1203 __func__, codec_dai->id);
1204 iface_reg = (iface_reg & 0x1f) | 0x80;
1205 /* voice call need data offset in 1 bitclock */
1206 snd_soc_write(codec, ASI1_LCH_OFFSET, 1);
1207 break;
1208 default:
1209 printk(KERN_ERR
1210 "#%s: Invalid DAI interface format\n", __func__);
1211 return -EINVAL;
1212 }
1213 /* Also Configure the Pin Control Registers before writing into
1214 * the ASI specific Clock Control and Format Registers
1215 */
1216
1217 /* Configure B0_P4_R65_D[5:2] to 001 This configures the
1218 * WCLK1 Pin to ASI1
1219 */
1220 regvalue = snd_soc_read(codec, WCLK1_PIN_CNTL_REG);
1221 snd_soc_write(codec, WCLK1_PIN_CNTL_REG, (regvalue | BIT2));
1222
1223 /* Configure B0_P4_R68_d[6:5] = 01 and B0_P4_R67_D[4:1] to 0001
1224 * to ensure that the DIN1 and DOUT1 Pins are configured
1225 * correctly
1226 */
1227 regvalue = snd_soc_read(codec, DIN1_PIN_CNTL_REG);
1228 snd_soc_write(codec, DIN1_PIN_CNTL_REG, (regvalue | BIT5));
1229 regvalue = snd_soc_read(codec, DOUT1_PIN_CNTL_REG);
1230 snd_soc_write(codec, DOUT1_PIN_CNTL_REG, (regvalue | BIT1));
1231
1232 snd_soc_write(codec, ASI1_BWCLK_CNTL_REG, clk_reg);
1233
1234 snd_soc_write(codec, ASI1_BUS_FMT, iface_reg);
1235
1236 return 0;
1237}
1238
1239
1240/*
1241*----------------------------------------------------------------------------
1242* Function : aic3262_multi_i2s_asi2_set_dai_fmt
1243* Purpose : This function is to set the DAI format for ASI2 Port
1244*
1245*----------------------------------------------------------------------------
1246*/
1247static int aic3262_multi_i2s_asi2_set_dai_fmt(struct snd_soc_dai *codec_dai,
1248 unsigned int fmt)
1249{
1250 struct snd_soc_codec *codec = codec_dai->codec;
1251 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1252 u8 iface_reg, clk_reg;
1253 u8 regvalue;
1254
1255 DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
1256 __func__, codec_dai->id, fmt);
1257
1258 /* Read the B0_P4_R17 and B0_P4_R26 Registers to configure the
1259 * ASI1 Bus and Clock Formats depending on the PCM Format.
1260 */
1261 iface_reg = snd_soc_read(codec, ASI2_BUS_FMT);
1262 clk_reg = snd_soc_read(codec, ASI2_BWCLK_CNTL_REG);
1263
1264 /* set master/slave audio interface */
1265 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1266 case SND_SOC_DAIFMT_CBM_CFM:
1267 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
1268 __func__, codec_dai->id);
1269 aic3262->asiCtxt[1].master = 1;
1270 clk_reg |= (BIT5 | BIT2);
1271 break;
1272 case SND_SOC_DAIFMT_CBS_CFS:
1273 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
1274 __func__, codec_dai->id);
1275
1276 clk_reg &= ~0xFC;
1277 aic3262->asiCtxt[1].master = 0;
1278 break;
1279 case SND_SOC_DAIFMT_CBS_CFM:
1280 /*new case..just for debugging */
1281 DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
1282 aic3262->asiCtxt[1].master = 0;
1283 clk_reg |= BIT5;
1284 clk_reg &= ~0x1C;
1285 break;
1286 default:
1287 printk(KERN_ERR "#%s:Invalid DAI master/slave interface\n",
1288 __func__);
1289 return -EINVAL;
1290 }
1291 aic3262->asiCtxt[1].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1292 /* interface format */
1293 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1294 case SND_SOC_DAIFMT_I2S:
1295 DBG(KERN_INFO "#%s: Configuring ASI%d for I2S Mode..\n",
1296 __func__, codec_dai->id);
1297 iface_reg = (iface_reg & 0x1f);
1298 break;
1299 case SND_SOC_DAIFMT_DSP_A:
1300 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
1301 __func__, codec_dai->id);
1302 iface_reg = (iface_reg & 0x1f) | 0x20;
1303 break;
1304 case SND_SOC_DAIFMT_RIGHT_J:
1305 iface_reg = (iface_reg & 0x1f) | 0x40;
1306 break;
1307 case SND_SOC_DAIFMT_LEFT_J:
1308 iface_reg = (iface_reg & 0x1f) | 0x60;
1309 break;
1310 case SND_SOC_DAIFMT_DSP_B:
1311 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP Mode..\n",
1312 __func__, codec_dai->id);
1313 iface_reg = (iface_reg & 0x1f) | 0x80;
1314 /* voice call need data offset in 1 bitclock */
1315 snd_soc_write(codec, ASI2_LCH_OFFSET, 1);
1316 break;
1317 default:
1318 printk(KERN_ERR "#%s:Invalid DAI interface format\n", __func__);
1319 return -EINVAL;
1320 }
1321
1322 /* Also Configure the Pin Control Registers before writing into
1323 * the ASI2 specific Clock Control and Format Registers
1324 */
1325
1326 /* Configure B0_P4_R69_D[5:2] to 001 This configures the
1327 * WCLK2 Pin to ASI2
1328 */
1329
1330 regvalue = snd_soc_read(codec, WCLK2_PIN_CNTL_REG);
1331 snd_soc_write(codec, WCLK2_PIN_CNTL_REG, (regvalue | BIT2));
1332
1333 regvalue = snd_soc_read(codec, BCLK2_PIN_CNTL_REG);
1334 snd_soc_write(codec, BCLK2_PIN_CNTL_REG, (regvalue | BIT2));
1335
1336 /* Configure B0_P4_R72_d[6:5] = 01 and B0_P4_R71_D[4:1] to 0001
1337 * to ensure that the DIN2 and DOUT2 Pins are configured
1338 * correctly
1339 */
1340 regvalue = snd_soc_read(codec, DIN2_PIN_CNTL_REG);
1341 snd_soc_write(codec, DIN2_PIN_CNTL_REG, (regvalue | BIT5));
1342
1343 regvalue = snd_soc_read(codec, DOUT2_PIN_CNTL_REG);
1344 snd_soc_write(codec, DOUT2_PIN_CNTL_REG, (regvalue | BIT5 | BIT1));
1345
1346 snd_soc_write(codec, ASI2_BWCLK_CNTL_REG, clk_reg);
1347
1348 snd_soc_write(codec, ASI2_BUS_FMT, iface_reg);
1349
1350 return 0;
1351}
1352
1353/*
1354*----------------------------------------------------------------------------
1355* Function : aic3262_multi_i2s_asi3_set_dai_fmt
1356* Purpose : This function is to set the DAI format for ASI3 Port
1357*
1358*----------------------------------------------------------------------------
1359*/
1360static int aic3262_multi_i2s_asi3_set_dai_fmt(struct snd_soc_dai *codec_dai,
1361 unsigned int fmt)
1362{
1363 struct snd_soc_codec *codec = codec_dai->codec;
1364 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1365 u8 iface_reg, clk_reg;
1366 u8 regvalue;
1367
1368 DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
1369 __func__, codec_dai->id, fmt);
1370
1371 /* Read the B0_P4_R33 and B0_P4_R42 Registers to configure the
1372 * ASI1 Bus and Clock Formats depending on the PCM Format.
1373 */
1374 iface_reg = snd_soc_read(codec, ASI3_BUS_FMT);
1375 clk_reg = snd_soc_read(codec, ASI3_BWCLK_CNTL_REG);
1376
1377 /* set master/slave audio interface */
1378 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1379 case SND_SOC_DAIFMT_CBM_CFM:
1380 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
1381 __func__, codec_dai->id);
1382 aic3262->asiCtxt[2].master = 1;
1383 clk_reg |= (BIT5 | BIT2);
1384 break;
1385 case SND_SOC_DAIFMT_CBS_CFS:
1386 DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
1387 __func__, codec_dai->id);
1388 clk_reg &= ~0xFC;
1389 aic3262->asiCtxt[2].master = 0;
1390 break;
1391 case SND_SOC_DAIFMT_CBS_CFM:
1392 /* new case..just for debugging */
1393 DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
1394 aic3262->asiCtxt[2].master = 0;
1395 clk_reg |= BIT5;
1396 clk_reg &= ~0x1C;
1397 break;
1398 default:
1399 printk(KERN_ERR "Invalid DAI master/slave interface\n");
1400 return -EINVAL;
1401 }
1402 aic3262->asiCtxt[2].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1403 /* interface format */
1404 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1405 case SND_SOC_DAIFMT_I2S:
1406 DBG(KERN_INFO "#%s: Configuring ASI%d for I2S Mode..\n",
1407 __func__, codec_dai->id);
1408 iface_reg = (iface_reg & 0x1f);
1409 break;
1410 case SND_SOC_DAIFMT_DSP_A:
1411 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
1412 __func__, codec_dai->id);
1413 iface_reg = (iface_reg & 0x1f) | 0x20;
1414 break;
1415 case SND_SOC_DAIFMT_RIGHT_J:
1416 iface_reg = (iface_reg & 0x1f) | 0x40;
1417 break;
1418 case SND_SOC_DAIFMT_LEFT_J:
1419 iface_reg = (iface_reg & 0x1f) | 0x60;
1420 break;
1421 case SND_SOC_DAIFMT_DSP_B:
1422 DBG(KERN_INFO "#%s: Configuring ASI%d for DSP Mode..\n",
1423 __func__, codec_dai->id);
1424 iface_reg = (iface_reg & 0x1f) | 0x80;
1425 /* voice call need data offset in 1 bitclock */
1426 snd_soc_write(codec, ASI3_LCH_OFFSET, 1);
1427 break;
1428 default:
1429 printk(KERN_ERR
1430 "#%s: Invalid DAI interface format\n", __func__);
1431 return -EINVAL;
1432 }
1433
1434 /* Also Configure the Pin Control Registers before writing into
1435 * the ASI specific Clock Control and Format Registers
1436 */
1437 /* Configure B0_P4_R73_D[5:2] to 0001 This configures the
1438 * WCLK1 Pin to ASI1
1439 */
1440 regvalue = snd_soc_read(codec, WCLK3_PIN_CNTL_REG);
1441 snd_soc_write(codec, WCLK3_PIN_CNTL_REG, (regvalue | BIT2));
1442
1443 regvalue = snd_soc_read(codec, BCLK3_PIN_CNTL_REG);
1444 snd_soc_write(codec, BCLK3_PIN_CNTL_REG, (regvalue | BIT2));
1445
1446 /* Configure B0_P4_R76_d[6:5] = 01 and B0_P4_R75_D[4:1] to 0001
1447 * to ensure that the DIN1 and DOUT1 Pins are configured
1448 * correctly
1449 */
1450 regvalue = snd_soc_read(codec, DIN3_PIN_CNTL_REG);
1451 snd_soc_write(codec, DIN3_PIN_CNTL_REG, (regvalue | BIT5));
1452 regvalue = snd_soc_read(codec, DOUT3_PIN_CNTL_REG);
1453 snd_soc_write(codec, DOUT3_PIN_CNTL_REG, (regvalue | BIT1));
1454
1455 snd_soc_write(codec, ASI3_BWCLK_CNTL_REG, clk_reg);
1456
1457 snd_soc_write(codec, ASI3_BUS_FMT, iface_reg);
1458
1459 return 0;
1460}
1461
1462/*
1463 * Clock after PLL and dividers
1464 */
1465static int aic3262_multi_i2s_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1466 int clk_id, unsigned int freq, int dir)
1467{
1468 struct snd_soc_codec *codec = codec_dai->codec;
1469 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1470
1471 DBG(KERN_INFO "#%s: DAI ID %d Freq %d Direction %d\n",
1472 __func__, codec_dai->id, freq, dir);
1473 switch (freq) {
1474 case AIC3262_FREQ_12000000:
1475 case AIC3262_FREQ_12288000:
1476 case AIC3262_FREQ_24000000:
1477 aic3262->sysclk = freq;
1478 return 0;
1479 break;
1480 }
1481 printk(KERN_ERR "Invalid frequency to set DAI system clock\n");
1482 return -EINVAL;
1483}
1484
1485/*
1486* aic3262_multi_i2s_set_pll
1487*
1488* This function is invoked as part of the PLL call-back
1489* handler from the ALSA layer.
1490*/
1491static int aic3262_multi_i2s_set_dai_pll(struct snd_soc_dai *codec_dai,
1492 int pll_id, int source, unsigned int freq_in,
1493 unsigned int freq_out)
1494{
1495
1496 printk(KERN_INFO "%s: DAI ID %d PLL_ID %d InFreq %d OutFreq %d\n",
1497 __func__, pll_id, codec_dai->id, freq_in, freq_out);
1498
1499 return 0;
1500}
1501
1502/*
1503* aic3262_asi1_clk_config
1504*
1505* This function is used to configure the BCLK1, WCLK1 pins which
1506* are specific to ASI1 Interface. This function just enables the
1507* BCLk and WCLK along with the miniDSP Port Control Registers.
1508* However, depending on the user requirement, this function can also be
1509* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
1510*/
1511static int aic3262_asi1_clk_config(struct snd_soc_codec *codec,
1512 struct snd_pcm_hw_params *params)
1513{
1514 u8 bclk_N_value, wclk_N_value;
1515 u8 minidspD_data, minidspA_data;
1516 u8 regval;
1517
1518 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1519
1520 DBG(KERN_INFO "%s: Invoked\n", __func__);
1521
1522 /* Configure the BCLK and WCLK Output Mux Options */
1523 regval = snd_soc_read(codec, ASI1_BWCLK_OUT_CNTL);
1524 regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
1525
1526 regval |= (aic3262->asiCtxt[0].bclk_output <<
1527 AIC3262_ASI_BCLK_MUX_SHIFT);
1528 regval |= aic3262->asiCtxt[0].wclk_output;
1529 snd_soc_write(codec, ASI1_BWCLK_OUT_CNTL, regval);
1530
1531 /* Configure the corresponding miniDSP Data Ports */
1532 minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
1533 minidspD_data &= ~(BIT5 | BIT4);
1534 snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
1535
1536 minidspA_data = snd_soc_read(codec, ASI1_ADC_INPUT_CNTL);
1537 minidspA_data &= ~(BIT2 | BIT1 | BIT0);
1538 minidspA_data |= aic3262->asiCtxt[0].adc_input;
1539 snd_soc_write(codec, ASI1_ADC_INPUT_CNTL, minidspA_data);
1540
1541
1542 if (aic3262->asiCtxt[0].master == 1) {
1543 DBG(KERN_INFO
1544 "#%s: Codec Master on ASI1 Port. Enabling BCLK WCLK Divider.\n",
1545 __func__);
1546 bclk_N_value = aic3262->asiCtxt[0].bclk_div;
1547 snd_soc_write(codec, ASI1_BCLK_N, (bclk_N_value | 0x80));
1548
1549 wclk_N_value = snd_soc_read(codec, ASI1_WCLK_N);
1550 snd_soc_write(codec, ASI1_WCLK_N, (wclk_N_value | 0xA0));
1551 }
1552 return 0;
1553
1554}
1555
1556/*
1557* aic3262_asi2_clk_config
1558*
1559* This function is used to configure the BCLK2, WCLK2 pins which
1560* are specific to ASI2 Interface. This function just enables the
1561* BCLk and WCLK along with the miniDSP Port Control Registers.
1562* However, depending on the user requirement, this function can also be
1563* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
1564*/
1565static int aic3262_asi2_clk_config(struct snd_soc_codec *codec,
1566 struct snd_pcm_hw_params *params)
1567{
1568 u8 bclk_N_value, wclk_N_value, minidspD_data, minidspA_data;
1569 u8 regval;
1570
1571 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1572
1573 DBG(KERN_INFO "%s: Invoked\n", __func__);
1574
1575
1576 /* Configure the BCLK and WCLK Output Mux Options */
1577 regval = snd_soc_read(codec, ASI2_BWCLK_OUT_CNTL);
1578 regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
1579 regval |= (aic3262->asiCtxt[1].bclk_output <<
1580 AIC3262_ASI_BCLK_MUX_SHIFT);
1581 regval |= aic3262->asiCtxt[1].wclk_output;
1582
1583 snd_soc_write(codec, ASI2_BWCLK_OUT_CNTL, regval);
1584 /* Configure the corresponding miniDSP Data Ports */
1585 minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
1586 minidspD_data |= (BIT2);
1587 snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
1588
1589 minidspA_data = snd_soc_read(codec, ASI2_ADC_INPUT_CNTL);
1590 minidspA_data &= ~(BIT2 | BIT1 | BIT0);
1591 minidspA_data |= aic3262->asiCtxt[1].adc_input;
1592 snd_soc_write(codec, ASI2_ADC_INPUT_CNTL, minidspA_data);
1593
1594 /* NO Manual configuration of WCLK and BCLK for Master Mode.
1595 * DAPM Handles all the required modifications.
1596 */
1597 if (aic3262->asiCtxt[1].master == 1) {
1598 DBG(KERN_INFO
1599 "#%s: Codec Master on ASI2 Port. Enabling BCLK WCLK Divider.\n",
1600 __func__);
1601 bclk_N_value = aic3262->asiCtxt[1].bclk_div;
1602 snd_soc_write(codec, ASI2_BCLK_N, (bclk_N_value | 0x80));
1603
1604 wclk_N_value = snd_soc_read(codec, ASI2_WCLK_N);
1605 snd_soc_write(codec, ASI2_WCLK_N, (wclk_N_value | 0xA0));
1606 }
1607
1608 return 0;
1609
1610}
1611
1612/*
1613* aic3262_asi3_clk_config
1614*
1615* This function is used to configure the BCLK3, WCLK3 pins which
1616* are specific to ASI3 Interface. This function just enables the
1617* BCLk and WCLK along with the miniDSP Port Control Registers.
1618* However, depending on the user requirement, this function can also be
1619* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
1620*/
1621static int aic3262_asi3_clk_config(struct snd_soc_codec *codec,
1622 struct snd_pcm_hw_params *params)
1623{
1624 u8 bclk_N_value, wclk_N_value, minidspD_data, minidspA_data;
1625 u8 regval;
1626
1627 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1628
1629 DBG(KERN_INFO "%s:\n", __func__);
1630
1631
1632 /* Configure the BCLK and WCLK Output Mux Options */
1633 regval = snd_soc_read(codec, ASI3_BWCLK_OUT_CNTL);
1634 regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
1635 regval |= (aic3262->asiCtxt[2].bclk_output <<
1636 AIC3262_ASI_BCLK_MUX_SHIFT);
1637 regval |= aic3262->asiCtxt[2].wclk_output;
1638 snd_soc_write(codec, ASI3_BWCLK_OUT_CNTL, regval);
1639
1640 minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
1641 minidspD_data |= (BIT1);
1642 snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
1643
1644 minidspA_data = snd_soc_read(codec, ASI3_ADC_INPUT_CNTL);
1645 minidspA_data &= ~(BIT2 | BIT1 | BIT0);
1646 minidspA_data |= aic3262->asiCtxt[2].adc_input;
1647 snd_soc_write(codec, ASI3_ADC_INPUT_CNTL, minidspA_data);
1648
1649 if (aic3262->asiCtxt[2].master == 1) {
1650 DBG(KERN_INFO
1651 "#%s: Codec Master on ASI3 Port. Enabling BCLK WCLK Divider.\n",
1652 __func__);
1653 bclk_N_value = aic3262->asiCtxt[2].bclk_div;
1654 snd_soc_write(codec, ASI2_BCLK_N, (bclk_N_value | 0x80));
1655
1656 wclk_N_value = snd_soc_read(codec, ASI3_WCLK_N);
1657 snd_soc_write(codec, ASI3_WCLK_N, (wclk_N_value | 0xA0));
1658 }
1659 return 0;
1660
1661}
1662
1663/*
1664* aic3262_multi_i2s_hw_params
1665*
1666* This function is used to configure the individual ASI port registers
1667* depending on the configuration passed on by the snd_pcm_hw_params
1668* structure.
1669* This function internally configures the ASI specific pins and clock
1670* Control Registers.
1671*/
1672static int aic3262_multi_i2s_hw_params(struct snd_pcm_substream *substream,
1673 struct snd_pcm_hw_params *params,
1674 struct snd_soc_dai *dai)
1675{
1676 int i, j;
1677 u8 data;
1678 u16 regoffset = 0;
1679 u8 dacpath = 0;
1680 u8 adcpath = 0;
1681 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1682 struct snd_soc_codec *codec = rtd->codec;
1683 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1684
1685 DBG(KERN_INFO "#%s: Invoked for ASI%d Port for %s Mode\n",
1686 __func__, dai->id,
1687 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1688 ? "Playback" : "Record");
1689
1690 i = aic3262_get_divs(aic3262->sysclk, params_rate(params));
1691
1692 i2c_verify_book0(codec);
1693
1694 if (i < 0) {
1695 printk(KERN_ERR "#%s: Sampling rate %d not supported\n",
1696 __func__, params_rate(params));
1697 return i;
1698 }
1699
1700 aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1701
1702 /* Configure the PLL J, R D values only if none of the ASI
1703 * Interfaces are Active.
1704 */
1705
1706 if (1) {
1707 DBG(KERN_INFO "#%s: None of the ASIs active yet...\n",
1708 __func__);
1709 /*We will fix R value to 1 and make P & J=K.D as variable */
1710 /* Setting P & R values are set to 1 and 1 at init*/
1711
1712 /* J value */
1713 snd_soc_write(codec, PLL_J_REG, aic3262_divs[i].pll_j);
1714
1715 /* MSB & LSB for D value */
1716
1717 snd_soc_write(codec, PLL_D_MSB, (aic3262_divs[i].pll_d >> 8));
1718 snd_soc_write(codec, PLL_D_LSB,
1719 (aic3262_divs[i].pll_d & AIC3262_8BITS_MASK));
1720
1721 /* NDAC divider value */
1722 data = snd_soc_read(codec, NDAC_DIV_POW_REG);
1723 DBG(KERN_INFO "# reading NDAC = %d , NDAC_DIV_POW_REG = %x\n",
1724 aic3262_divs[i].ndac, data);
1725 snd_soc_write(codec, NDAC_DIV_POW_REG,
1726 ((data & 0x80)|(aic3262_divs[i].ndac)));
1727 DBG(KERN_INFO "# writing NDAC = %d , NDAC_DIV_POW_REG = %x\n",
1728 aic3262_divs[i].ndac,
1729 ((data & 0x80)|(aic3262_divs[i].ndac)));
1730
1731 /* MDAC divider value */
1732 data = snd_soc_read(codec, MDAC_DIV_POW_REG);
1733 DBG(KERN_INFO "# reading MDAC = %d , MDAC_DIV_POW_REG = %x\n",
1734 aic3262_divs[i].mdac, data);
1735 snd_soc_write(codec, MDAC_DIV_POW_REG,
1736 ((data & 0x80)|(aic3262_divs[i].mdac)));
1737 DBG(KERN_INFO "# writing MDAC = %d , MDAC_DIV_POW_REG = %x\n",
1738 aic3262_divs[i].mdac, ((data & 0x80)|(aic3262_divs[i].mdac)));
1739
1740 /* DOSR MSB & LSB values */
1741 snd_soc_write(codec, DOSR_MSB_REG, aic3262_divs[i].dosr >> 8);
1742 DBG(KERN_INFO "# writing DOSR_MSB_REG = %d\n",
1743 (aic3262_divs[i].dosr >> 8));
1744 snd_soc_write(codec, DOSR_LSB_REG,
1745 aic3262_divs[i].dosr & AIC3262_8BITS_MASK);
1746 DBG(KERN_INFO "# writing DOSR_LSB_REG = %d\n",
1747 (aic3262_divs[i].dosr & AIC3262_8BITS_MASK));
1748
1749 /* NADC divider value */
1750 data = snd_soc_read(codec, NADC_DIV_POW_REG);
1751 snd_soc_write(codec, NADC_DIV_POW_REG,
1752 ((data & 0x80)|(aic3262_divs[i].nadc)));
1753 DBG(KERN_INFO "# writing NADC_DIV_POW_REG = %d\n",
1754 aic3262_divs[i].nadc);
1755
1756 /* MADC divider value */
1757 data = snd_soc_read(codec, MADC_DIV_POW_REG);
1758 snd_soc_write(codec, MADC_DIV_POW_REG,
1759 ((data & 0x80)|(aic3262_divs[i].madc)));
1760 DBG(KERN_INFO "# writing MADC_DIV_POW_REG = %d\n",
1761 aic3262_divs[i].madc);
1762
1763 /* AOSR value */
1764 snd_soc_write(codec, AOSR_REG, aic3262_divs[i].aosr);
1765 DBG(KERN_INFO "# writing AOSR = %d\n", aic3262_divs[i].aosr);
1766 } else {
1767 DBG(KERN_INFO "#Atleast 1 ASI Active. Cannot Program PLL..\n");
1768 }
1769 /* Check for the DAI ID to know which ASI needs
1770 * Configuration.
1771 */
1772 switch (dai->id) {
1773 case 1:
1774 regoffset = ASI1_BUS_FMT;
1775
1776 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1777 DBG(KERN_INFO "#%s: ASI1 DAC Inputs enabled..\n",
1778 __func__);
1779 /* Read the DAC Control Register and configure it
1780 * as per the ASIContext Structure Settings.
1781 */
1782 dacpath = snd_soc_read(codec, ASI1_DAC_OUT_CNTL);
1783 dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
1784 AIC3262_ASI_RDAC_PATH_MASK);
1785 dacpath |= (aic3262->asiCtxt[0].left_dac_output
1786 << AIC3262_ASI_LDAC_PATH_SHIFT);
1787
1788 dacpath |= (aic3262->asiCtxt[0].right_dac_output
1789 << AIC3262_ASI_RDAC_PATH_SHIFT);
1790 snd_soc_write(codec, ASI1_DAC_OUT_CNTL, dacpath);
1791
1792 aic3262->asiCtxt[0].playback_mode = 1;
1793 aic3262->asiCtxt[0].bclk_div =
1794 aic3262_divs[i].blck_N;
1795 } else {
1796 /* For Recording, Configure the DOUT Pin as per
1797 * ASIContext Structure Settings.
1798 */
1799 adcpath = snd_soc_read(codec, ASI1_DATA_OUT);
1800 adcpath &= ~(AIC3262_ASI_DOUT_MASK);
1801
1802 adcpath |= aic3262->asiCtxt[0].dout_option;
1803 snd_soc_write(codec, ASI1_DATA_OUT, adcpath);
1804
1805 aic3262->asiCtxt[0].capture_mode = 1;
1806 }
1807 break;
1808 case 2:
1809 regoffset = ASI2_BUS_FMT;
1810
1811 /* Since we are configuring ASI2, please check if Playback
1812 * is expected. If so, enable ASI2 Inputs to Left and
1813 * Right DACs
1814 */
1815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1816 DBG(KERN_INFO "#%s: ASI2 DAC Inputs enabled..\n",
1817 __func__);
1818 /* Read the DAC Control Register and configure it
1819 * as per theASIContext Structure Settings.
1820 */
1821 dacpath = snd_soc_read(codec, ASI2_DAC_OUT_CNTL);
1822 dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
1823 AIC3262_ASI_RDAC_PATH_MASK);
1824 dacpath |= (aic3262->asiCtxt[1].left_dac_output
1825 << AIC3262_ASI_LDAC_PATH_SHIFT);
1826
1827 dacpath |= (aic3262->asiCtxt[1].right_dac_output
1828 << AIC3262_ASI_RDAC_PATH_SHIFT);
1829 snd_soc_write(codec, ASI2_DAC_OUT_CNTL, dacpath);
1830 aic3262->asiCtxt[1].playback_mode = 1;
1831
1832 aic3262->asiCtxt[1].bclk_div =
1833 aic3262_divs[i].blck_N;
1834 } else {
1835 /* For Recording, Configure the DOUT Pin as per
1836 * ASIContext Structure Settings.
1837 */
1838 adcpath = snd_soc_read(codec, ASI2_DATA_OUT);
1839 adcpath &= ~(AIC3262_ASI_DOUT_MASK);
1840 adcpath |= aic3262->asiCtxt[1].dout_option;
1841 snd_soc_write(codec, ASI2_DATA_OUT, adcpath);
1842
1843 aic3262->asiCtxt[1].capture_mode = 1;
1844 }
1845 break;
1846 case 3:
1847 regoffset = ASI3_BUS_FMT;
1848 /* Since we are configuring ASI3, please check if Playback
1849 * is expected. If so, enable ASI3 Inputs to Left and
1850 * Right DACs
1851 */
1852 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1853 DBG(KERN_INFO "#%s:ASI3 DAC Inputs enabled.\n",
1854 __func__);
1855 /* Read the DAC Control Register and configure
1856 * it as per the ASIContext Structure Settings.
1857 */
1858 dacpath = snd_soc_read(codec, ASI3_DAC_OUT_CNTL);
1859 dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
1860 AIC3262_ASI_RDAC_PATH_MASK);
1861 dacpath |= (aic3262->asiCtxt[2].left_dac_output
1862 << AIC3262_ASI_LDAC_PATH_SHIFT);
1863 dacpath |= (aic3262->asiCtxt[2].right_dac_output
1864 << AIC3262_ASI_RDAC_PATH_SHIFT);
1865 snd_soc_write(codec,
1866 ASI3_DAC_OUT_CNTL, dacpath);
1867
1868 aic3262->asiCtxt[2].playback_mode = 1;
1869
1870 aic3262->asiCtxt[2].bclk_div =
1871 aic3262_divs[i].blck_N;
1872 } else {
1873 /* For Recording, Configure the DOUT Pin as per
1874 * ASIContext Structure Settings.
1875 */
1876 adcpath &= ~(AIC3262_ASI_DOUT_MASK);
1877 adcpath |= aic3262->asiCtxt[2].dout_option;
1878 snd_soc_write(codec, ASI3_DATA_OUT, adcpath);
1879
1880 aic3262->asiCtxt[2].capture_mode = 1;
1881 }
1882 break;
1883 default:
1884 printk(KERN_ERR "Invalid Dai ID %d in %s",
1885 dai->id, __func__);
1886 break;
1887 }
1888 DBG(KERN_INFO "#%s: Reading Pg %d Reg %d for Bus Format Control.\n",
1889 __func__, (regoffset/128), (regoffset % 128));
1890
1891 /* Read the correspondig ASI DAI Interface Register */
1892 data = snd_soc_read(codec, regoffset);
1893
1894 data = data & 0xe7;
1895
1896 switch (params_format(params)) {
1897 case SNDRV_PCM_FORMAT_S16_LE:
1898 DBG(KERN_INFO "#%s: Configuring ASI%d S16_LE Fmt..\n",
1899 __func__, dai->id);
1900 data = data | 0x00;
1901 aic3262->asiCtxt[dai->id - 1].word_len = 16;
1902 break;
1903 case SNDRV_PCM_FORMAT_S20_3LE:
1904 data |= (0x08);
1905 aic3262->asiCtxt[dai->id - 1].word_len = 20;
1906 break;
1907 case SNDRV_PCM_FORMAT_S24_LE:
1908 DBG(KERN_INFO "#%s: Configuring ASI%d S24_LE Fmt..\n",
1909 __func__, dai->id);
1910 data |= (0x10);
1911 aic3262->asiCtxt[dai->id - 1].word_len = 24;
1912 break;
1913 case SNDRV_PCM_FORMAT_S32_LE:
1914 DBG(KERN_INFO "#%s: Configuring ASI%d S32_LE Fmt..\n",
1915 __func__, dai->id);
1916 data |= (0x18);
1917 aic3262->asiCtxt[dai->id - 1].word_len = 32;
1918 break;
1919 }
1920
1921 /* configure the respective Registers for the above configuration */
1922 snd_soc_write(codec, regoffset, data);
1923
1924 for (j = 0; j < NO_FEATURE_REGS; j++) {
1925 snd_soc_write(codec,
1926 aic3262_divs[i].codec_specific_regs[j].reg_offset,
1927 aic3262_divs[i].codec_specific_regs[j].reg_val);
1928 }
1929
1930 /* Enable the PLL, MDAC, NDAC, NADC, MADC and BCLK Dividers */
1931 aic3262_set_bias_level(codec, SND_SOC_BIAS_ON);
1932
1933 /* Based on the DAI ID we enable the corresponding pins related to the
1934 * ASI Port.
1935 */
1936 switch (dai->id) {
1937 case 1:
1938 aic3262_asi1_clk_config(codec, params);
1939 break;
1940 case 2:
1941 aic3262_asi2_clk_config(codec, params);
1942 break;
1943 case 3:
1944 aic3262_asi3_clk_config(codec, params);
1945 break;
1946 default:
1947 printk(KERN_ERR "Invalid Dai ID %d in %s",
1948 dai->id, __func__);
1949 break;
1950 }
1951 /* Depending on the DAI->ID update the local Flags */
1952 aic3262->asiCtxt[dai->id - 1].asi_active++;
1953 aic3262->asiCtxt[dai->id - 1].sampling_rate = params_rate(params);
1954 /* Update the active_count flag */
1955 aic3262->active_count++;
1956
1957 return 0;
1958}
1959
1960/*
1961*
1962* aic3262_multi_i2s_hw_free
1963*
1964* This function is used to configure the Codec after the usage is completed.
1965* We can use this function to disable the DAC and ADC specific inputs from the
1966* individual ASI Ports of the Audio Codec.
1967*/
1968static int aic3262_multi_i2s_shutdown(struct snd_pcm_substream *substream,
1969 struct snd_soc_dai *dai)
1970{
1971 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1972 struct snd_soc_codec *codec = rtd->codec;
1973 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1974
1975 u8 value;
1976 u8 dacpath;
1977 u8 adcpath;
1978 u16 dacregoffset = 0;
1979 u16 adcregoffset = 0;
1980
1981 DBG(KERN_INFO "#%s: ASI%d Port for %s Mode\n",
1982 __func__, dai->id,
1983 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
1984 "Playback" : "Record");
1985
1986 /* Check if this function was already executed earlier for the same
1987 * ASI Port
1988 */
1989 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
1990 (aic3262->asiCtxt[dai->id - 1].playback_mode == 0)) {
1991 DBG(KERN_INFO "#%s: Function Already Executed. Exiting..\n",
1992 __func__);
1993 goto err;
1994 } else if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) &&
1995 (aic3262->asiCtxt[dai->id - 1].capture_mode == 0)) {
1996 DBG(KERN_INFO "#%s: Function Already Executed. Exiting..\n",
1997 __func__);
1998 goto err;
1999 }
2000
2001 switch (dai->id) {
2002 case 1:
2003 /* In case we are Frame Master on this Interface, Switch off
2004 * the Bit Clock Divider and Word Clock Dividers
2005 */
2006 if (aic3262->asiCtxt[0].master == 1) {
2007 /* Also check if either Playback or Recording is still
2008 * going on this ASI Interface
2009 */
2010
2011 value = snd_soc_read(codec, ASI1_BCLK_N);
2012 snd_soc_write(codec, ASI1_BCLK_N, (value & 0x7f));
2013
2014 value = snd_soc_read(codec, ASI1_WCLK_N);
2015 snd_soc_write(codec, ASI1_WCLK_N, (value & 0x7f));
2016 }
2017
2018 dacregoffset = ASI1_DAC_OUT_CNTL;
2019 adcregoffset = ASI1_ADC_INPUT_CNTL;
2020 break;
2021 case 2:
2022 /* In case we are Frame Master on this Interface, Switch off
2023 * the Bit Clock Divider and Word Clock Dividers
2024 */
2025 if (aic3262->asiCtxt[1].master == 1) {
2026 value = snd_soc_read(codec, ASI2_BCLK_N);
2027 snd_soc_write(codec, ASI2_BCLK_N, (value & 0x7f));
2028
2029 value = snd_soc_read(codec, ASI2_WCLK_N);
2030 snd_soc_write(codec, ASI2_WCLK_N, (value & 0x7f));
2031 }
2032 dacregoffset = ASI2_DAC_OUT_CNTL;
2033 adcregoffset = ASI2_ADC_INPUT_CNTL;
2034 break;
2035 case 3:
2036 /* In case we are Frame Master on this Interface, Switch off
2037 * the Bit Clock Divider and Word Clock Dividers
2038 */
2039 if (aic3262->asiCtxt[2].master == 1) {
2040 value = snd_soc_read(codec, ASI3_BCLK_N);
2041 snd_soc_write(codec, ASI3_BCLK_N, (value & 0x7f));
2042
2043 value = snd_soc_read(codec, ASI3_WCLK_N);
2044 snd_soc_write(codec, ASI3_WCLK_N, (value & 0x7f));
2045 }
2046 dacregoffset = ASI3_DAC_OUT_CNTL;
2047 adcregoffset = ASI3_ADC_INPUT_CNTL;
2048 break;
2049 default:
2050 printk(KERN_ERR "#%s: Invalid dai id\n", __func__);
2051 }
2052 /* If this was a Playback Stream Stop, then only
2053 * switch off the DAC Inputs
2054 */
2055 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
2056 (dacregoffset != 0)) {
2057 DBG(KERN_INFO "#%s: Disabling Pg %d Reg %d DAC Inputs ..\n",
2058 __func__, (dacregoffset/128), (dacregoffset % 128));
2059
2060 dacpath = snd_soc_read(codec, dacregoffset);
2061 snd_soc_write(codec, dacregoffset, (dacpath & ~(BIT6 | BIT4)));
2062
2063 aic3262->asiCtxt[dai->id - 1].playback_mode = 0;
2064 } else {
2065 /* Switch off the ADC Input Control Registers here */
2066 DBG(KERN_INFO "#%s: Disabling Pg %d Reg %d for ADC Inputs..\n",
2067 __func__, (adcregoffset/128), (adcregoffset % 128));
2068
2069 adcpath = snd_soc_read(codec, adcregoffset);
2070 snd_soc_write(codec, adcregoffset,
2071 (adcpath & ~(BIT2 | BIT1 | BIT0)));
2072
2073 aic3262->asiCtxt[dai->id - 1].capture_mode = 0;
2074 }
2075
2076 /* If we were configured in mono PCM Mode earlier, then reset the
2077 * Left Channel and Right Channel offset Registers here.
2078 */
2079 switch (dai->id) {
2080 case 1:
2081 if (aic3262->asiCtxt[0].pcm_format == SND_SOC_DAIFMT_DSP_B) {
2082 snd_soc_write(codec, ASI1_LCH_OFFSET, 0x00);
2083 snd_soc_write(codec, ASI1_RCH_OFFSET, 0x00);
2084 }
2085 break;
2086 case 2:
2087 if (aic3262->asiCtxt[1].pcm_format == SND_SOC_DAIFMT_DSP_B) {
2088 snd_soc_write(codec, ASI2_LCH_OFFSET, 0x00);
2089 snd_soc_write(codec, ASI2_RCH_OFFSET, 0x00);
2090 }
2091
2092 break;
2093 case 3:
2094 if (aic3262->asiCtxt[2].pcm_format == SND_SOC_DAIFMT_DSP_B) {
2095 snd_soc_write(codec, ASI3_LCH_OFFSET, 0x00);
2096 snd_soc_write(codec, ASI3_RCH_OFFSET, 0x00);
2097 }
2098 break;
2099 }
2100 /* Depending on the DAI->ID update the asi_active Flags */
2101 if (aic3262->asiCtxt[dai->id - 1].asi_active) {
2102 aic3262->asiCtxt[dai->id - 1].asi_active--;
2103
2104 /* Update the active_count flag */
2105 if (aic3262->active_count)
2106 aic3262->active_count--;
2107 }
2108err:
2109 return 0;
2110}
2111
2112
2113/*
2114*
2115* aic3262_multi_i2s_set_clkdiv
2116*
2117*/
2118static int aic3262_multi_i2s_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
2119{
2120 int value;
2121 struct snd_soc_codec *codec = codec_dai->codec;
2122 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
2123
2124
2125 value = snd_soc_read(codec, div_id);
2126 snd_soc_write(codec, div_id, (value | div));
2127
2128 printk(KERN_INFO "#%s: DAI ID %d Page %d Register %d Divider_Val %d Final_Value 0x%x\n",
2129 __func__, codec_dai->id, (div_id /128), (div_id%128), div,
2130 (value | div));
2131
2132 /* Store the Clock Divider inside the Private Structure */
2133 switch(codec_dai->id) {
2134 case 1:
2135 if (div_id == ASI1_BCLK_N)
2136 aic3262->asiCtxt[0].bclk_div = div;
2137 if (div_id == ASI1_WCLK_N)
2138 aic3262->asiCtxt[0].wclk_div = div;
2139 break;
2140 case 2:
2141 if (div_id == ASI2_BCLK_N)
2142 aic3262->asiCtxt[1].bclk_div = div;
2143 if (div_id == ASI2_WCLK_N)
2144 aic3262->asiCtxt[1].wclk_div = div;
2145 break;
2146 case 3:
2147 if (div_id == ASI3_BCLK_N)
2148 aic3262->asiCtxt[2].bclk_div = div;
2149 if (div_id == ASI3_WCLK_N)
2150 aic3262->asiCtxt[2].wclk_div = div;
2151 break;
2152 }
2153 return 0;
2154}
2155
2156
2157/*
2158 *----------------------------------------------------------------------------
2159 * @struct snd_soc_codec_dai |
2160 * It is SoC Codec DAI structure which has DAI capabilities viz.,
2161 * playback and capture, DAI runtime information viz. state of DAI
2162 * and pop wait state, and DAI private data.
2163 * The AIC3262 rates ranges from 8k to 192k
2164 * The PCM bit format supported are 16, 20, 24 and 32 bits
2165 *----------------------------------------------------------------------------
2166 */
2167struct snd_soc_dai_ops aic3262_multi_i2s_dai_ops = {
2168 .hw_params = aic3262_multi_i2s_hw_params,
2169 .digital_mute = aic3262_multi_i2s_mute,
2170 .set_fmt = aic3262_multi_i2s_set_dai_fmt,
2171 .set_pll = aic3262_multi_i2s_set_dai_pll,
2172 .set_sysclk = aic3262_multi_i2s_set_dai_sysclk,
2173 .shutdown = aic3262_multi_i2s_shutdown,
2174 .set_clkdiv = aic3262_multi_i2s_set_clkdiv,
2175};
2176
2177
2178static struct snd_soc_dai_driver tlv320aic3262_dai[] = {
2179/* AIC3262 ASI1 DAI */
2180{
2181 .name = "aic3262-asi1",
2182 .id = 1,
2183 .playback = {
2184 .stream_name = "ASI1 Playback",
2185 .channels_min = 1,
2186 .channels_max = 2,
2187 .rates = AIC3262_RATES,
2188 .formats = AIC3262_FORMATS},
2189 .capture = { /* dummy for fast DAI switching */
2190 .stream_name = "ASI1 Capture",
2191 .channels_min = 1,
2192 .channels_max = 2,
2193 .rates = AIC3262_RATES,
2194 .formats = AIC3262_FORMATS},
2195 .ops = &aic3262_multi_i2s_dai_ops,
2196},
2197/* AIC3262 ASI2 DAI */
2198{
2199 .name = "aic3262-asi2",
2200 .id = 2,
2201 .playback = {
2202 .stream_name = "ASI2 Playback",
2203 .channels_min = 1,
2204 .channels_max = 2,
2205 .rates = AIC3262_RATES,
2206 .formats = AIC3262_FORMATS,},
2207 .capture = {
2208 .stream_name = "ASI2 Capture",
2209 .channels_min = 1,
2210 .channels_max = 2,
2211 .rates = AIC3262_RATES,
2212 .formats = AIC3262_FORMATS,},
2213 .ops = &aic3262_multi_i2s_dai_ops,
2214
2215},
2216/* AIC3262 ASI3 DAI */
2217{
2218 .name = "aic3262-asi3",
2219 .id = 3,
2220 .playback = {
2221 .stream_name = "ASI3 Playback",
2222 .channels_min = 1,
2223 .channels_max = 2,
2224 .rates = AIC3262_RATES,
2225 .formats = AIC3262_FORMATS, },
2226 .capture = {
2227 .stream_name = "ASI3 Capture",
2228 .channels_min = 1,
2229 .channels_max = 2,
2230 .rates = AIC3262_RATES,
2231 .formats = AIC3262_FORMATS, },
2232 .ops = &aic3262_multi_i2s_dai_ops,
2233
2234},
2235};
2236
2237/*
2238 *****************************************************************************
2239 * Initializations
2240 *****************************************************************************
2241 */
2242/*
2243 * AIC3262 register cache
2244 * We are caching the registers here.
2245 * There is no point in caching the reset register.
2246 *
2247 * NOTE: In AIC3262, there are 127 registers supported in both page0 and page1
2248 * The following table contains the page0 and page 1 and page 3
2249 * registers values.
2250 */
2251static const u8 aic3262_reg[AIC3262_CACHEREGNUM] = {
2252 0x00, 0x00, 0x10, 0x00, /* 0 */
2253 0x03, 0x40, 0x11, 0x08, /* 4 */
2254 0x00, 0x00, 0x00, 0x82, /* 8 */
2255 0x88, 0x00, 0x80, 0x02, /* 12 */
2256 0x00, 0x08, 0x01, 0x01, /* 16 */
2257 0x80, 0x01, 0x00, 0x04, /* 20 */
2258 0x00, 0x00, 0x01, 0x00, /* 24 */
2259 0x00, 0x00, 0x01, 0x00, /* 28 */
2260 0x00, 0x00, 0x00, 0x00, /* 32 */
2261 0x00, 0x00, 0x00, 0x00, /* 36 */
2262 0x00, 0x00, 0x00, 0x00, /* 40 */
2263 0x00, 0x00, 0x00, 0x00, /* 44 */
2264 0x00, 0x00, 0x00, 0x00, /* 48 */
2265 0x00, 0x42, 0x02, 0x02, /* 52 */
2266 0x42, 0x02, 0x02, 0x02, /* 56 */
2267 0x00, 0x00, 0x00, 0x01, /* 60 */
2268 0x01, 0x00, 0x14, 0x00, /* 64 */
2269 0x0C, 0x00, 0x00, 0x00, /* 68 */
2270 0x00, 0x00, 0x00, 0xEE, /* 72 */
2271 0x10, 0xD8, 0x10, 0xD8, /* 76 */
2272 0x00, 0x00, 0x88, 0x00, /* 80 */
2273 0x00, 0x00, 0x00, 0x00, /* 84 */
2274 0x7F, 0x00, 0x00, 0x00, /* 88 */
2275 0x00, 0x00, 0x00, 0x00, /* 92 */
2276 0x7F, 0x00, 0x00, 0x00, /* 96 */
2277 0x00, 0x00, 0x00, 0x00, /* 100 */
2278 0x00, 0x00, 0x00, 0x00, /* 104 */
2279 0x00, 0x00, 0x00, 0x00, /* 108 */
2280 0x00, 0x00, 0x00, 0x00, /* 112 */
2281 0x00, 0x00, 0x00, 0x00, /* 116 */
2282 0x00, 0x00, 0x00, 0x00, /* 120 */
2283 0x00, 0x00, 0x00, 0x00, /* 124 - PAGE0 Registers(127) ends here */
2284 0x01, 0x00, 0x08, 0x00, /* 128, PAGE1-0 */
2285 0x00, 0x00, 0x00, 0x00, /* 132, PAGE1-4 */
2286 0x00, 0x00, 0x00, 0x10, /* 136, PAGE1-8 */
2287 0x00, 0x00, 0x00, 0x00, /* 140, PAGE1-12 */
2288 0x40, 0x40, 0x40, 0x40, /* 144, PAGE1-16 */
2289 0x00, 0x00, 0x00, 0x00, /* 148, PAGE1-20 */
2290 0x00, 0x00, 0x00, 0x00, /* 152, PAGE1-24 */
2291 0x00, 0x00, 0x00, 0x00, /* 156, PAGE1-28 */
2292 0x00, 0x00, 0x00, 0x00, /* 160, PAGE1-32 */
2293 0x00, 0x00, 0x00, 0x00, /* 164, PAGE1-36 */
2294 0x00, 0x00, 0x00, 0x00, /* 168, PAGE1-40 */
2295 0x00, 0x00, 0x00, 0x00, /* 172, PAGE1-44 */
2296 0x00, 0x00, 0x00, 0x00, /* 176, PAGE1-48 */
2297 0x00, 0x00, 0x00, 0x00, /* 180, PAGE1-52 */
2298 0x00, 0x00, 0x00, 0x80, /* 184, PAGE1-56 */
2299 0x80, 0x00, 0x00, 0x00, /* 188, PAGE1-60 */
2300 0x00, 0x00, 0x00, 0x00, /* 192, PAGE1-64 */
2301 0x00, 0x00, 0x00, 0x00, /* 196, PAGE1-68 */
2302 0x00, 0x00, 0x00, 0x00, /* 200, PAGE1-72 */
2303 0x00, 0x00, 0x00, 0x00, /* 204, PAGE1-76 */
2304 0x00, 0x00, 0x00, 0x00, /* 208, PAGE1-80 */
2305 0x00, 0x00, 0x00, 0x00, /* 212, PAGE1-84 */
2306 0x00, 0x00, 0x00, 0x00, /* 216, PAGE1-88 */
2307 0x00, 0x00, 0x00, 0x00, /* 220, PAGE1-92 */
2308 0x00, 0x00, 0x00, 0x00, /* 224, PAGE1-96 */
2309 0x00, 0x00, 0x00, 0x00, /* 228, PAGE1-100 */
2310 0x00, 0x00, 0x00, 0x00, /* 232, PAGE1-104 */
2311 0x00, 0x00, 0x00, 0x00, /* 236, PAGE1-108 */
2312 0x00, 0x00, 0x00, 0x00, /* 240, PAGE1-112 */
2313 0x00, 0x00, 0x00, 0x00, /* 244, PAGE1-116 */
2314 0x00, 0x00, 0x00, 0x00, /* 248, PAGE1-120 */
2315 0x00, 0x00, 0x00, 0x00, /* 252, PAGE1-124 Page 1 Registers Ends Here */
2316 0x00, 0x00, 0x00, 0x00, /* 256, PAGE2-0 */
2317 0x00, 0x00, 0x00, 0x00, /* 260, PAGE2-4 */
2318 0x00, 0x00, 0x00, 0x00, /* 264, PAGE2-8 */
2319 0x00, 0x00, 0x00, 0x00, /* 268, PAGE2-12 */
2320 0x00, 0x00, 0x00, 0x00, /* 272, PAGE2-16 */
2321 0x00, 0x00, 0x00, 0x00, /* 276, PAGE2-20 */
2322 0x00, 0x00, 0x00, 0x00, /* 280, PAGE2-24 */
2323 0x00, 0x00, 0x00, 0x00, /* 284, PAGE2-28 */
2324 0x00, 0x00, 0x00, 0x00, /* 288, PAGE2-32 */
2325 0x00, 0x00, 0x00, 0x00, /* 292, PAGE2-36 */
2326 0x00, 0x00, 0x00, 0x00, /* 296, PAGE2-40 */
2327 0x00, 0x00, 0x00, 0x00, /* 300, PAGE2-44 */
2328 0x00, 0x00, 0x00, 0x00, /* 304, PAGE2-48 */
2329 0x00, 0x00, 0x00, 0x00, /* 308, PAGE2-52 */
2330 0x00, 0x00, 0x00, 0x00, /* 312, PAGE2-56 */
2331 0x00, 0x00, 0x00, 0x00, /* 316, PAGE2-60 */
2332 0x00, 0x00, 0x00, 0x00, /* 320, PAGE2-64 */
2333 0x00, 0x00, 0x00, 0x00, /* 324, PAGE2-68 */
2334 0x00, 0x00, 0x00, 0x00, /* 328, PAGE2-72 */
2335 0x00, 0x00, 0x00, 0x00, /* 332, PAGE2-76 */
2336 0x00, 0x00, 0x00, 0x00, /* 336, PAGE2-80 */
2337 0x00, 0x00, 0x00, 0x00, /* 340, PAGE2-84 */
2338 0x00, 0x00, 0x00, 0x00, /* 344, PAGE2-88 */
2339 0x00, 0x00, 0x00, 0x00, /* 348, PAGE2-92 */
2340 0x00, 0x00, 0x00, 0x00, /* 352, PAGE2-96 */
2341 0x00, 0x00, 0x00, 0x00, /* 356, PAGE2-100 */
2342 0x00, 0x00, 0x00, 0x00, /* 360, PAGE2-104 */
2343 0x00, 0x00, 0x00, 0x00, /* 364, PAGE2-108 */
2344 0x00, 0x00, 0x00, 0x00, /* 368, PAGE2-112*/
2345 0x00, 0x00, 0x00, 0x00, /* 372, PAGE2-116*/
2346 0x00, 0x00, 0x00, 0x00, /* 376, PAGE2-120*/
2347 0x00, 0x00, 0x00, 0x00, /* 380, PAGE2-124 Page 2 Registers Ends Here */
2348 0x00, 0x00, 0x00, 0x00, /* 384, PAGE3-0 */
2349 0x00, 0x00, 0x00, 0x00, /* 388, PAGE3-4 */
2350 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-8 */
2351 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-12 */
2352 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-16 */
2353 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-20 */
2354 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-24 */
2355 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-28 */
2356 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-32 */
2357 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-36 */
2358 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-40 */
2359 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-44 */
2360 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-48 */
2361 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-52 */
2362 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-56 */
2363 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-60 */
2364 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-64 */
2365 0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-68 */
2366 0x00, 0x00, 0x00, 0x00, /* 328, PAGE3-72 */
2367 0x00, 0x00, 0x00, 0x00, /* 332, PAGE3-76 */
2368 0x00, 0x00, 0x00, 0x00, /* 336, PAGE3-80 */
2369 0x00, 0x00, 0x00, 0x00, /* 340, PAGE3-84 */
2370 0x00, 0x00, 0x00, 0x00, /* 344, PAGE3-88 */
2371 0x00, 0x00, 0x00, 0x00, /* 348, PAGE3-92 */
2372 0x00, 0x00, 0x00, 0x00, /* 352, PAGE3-96 */
2373 0x00, 0x00, 0x00, 0x00, /* 356, PAGE3-100 */
2374 0x00, 0x00, 0x00, 0x00, /* 360, PAGE3-104 */
2375 0x00, 0x00, 0x00, 0x00, /* 364, PAGE3-108 */
2376 0x00, 0x00, 0x00, 0x00, /* 368, PAGE3-112*/
2377 0x00, 0x00, 0x00, 0x00, /* 372, PAGE3-116*/
2378 0x00, 0x00, 0x00, 0x00, /* 376, PAGE3-120*/
2379 0x00, 0x00, 0x00, 0x00, /* 380, PAGE3-124 Page 3 Registers Ends Here */
2380 0x00, 0x00, 0x00, 0x00, /* 384, PAGE4-0 */
2381 0x00, 0x00, 0x00, 0x00, /* 388, PAGE4-4 */
2382 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-8 */
2383 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-12 */
2384 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-16 */
2385 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-20 */
2386 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-24 */
2387 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-28 */
2388 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-32 */
2389 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-36 */
2390 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-40 */
2391 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-44 */
2392 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-48 */
2393 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-52 */
2394 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-56 */
2395 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-60 */
2396 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-64 */
2397 0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-68 */
2398 0x00, 0x00, 0x00, 0x00, /* 328, PAGE4-72 */
2399 0x00, 0x00, 0x00, 0x00, /* 332, PAGE4-76 */
2400 0x00, 0x00, 0x00, 0x00, /* 336, PAGE4-80 */
2401 0x00, 0x00, 0x00, 0x00, /* 340, PAGE4-84 */
2402 0x00, 0x00, 0x00, 0x00, /* 344, PAGE4-88 */
2403 0x00, 0x00, 0x00, 0x00, /* 348, PAGE4-92 */
2404 0x00, 0x00, 0x00, 0x00, /* 352, PAGE4-96 */
2405 0x00, 0x00, 0x00, 0x00, /* 356, PAGE4-100 */
2406 0x00, 0x00, 0x00, 0x00, /* 360, PAGE4-104 */
2407 0x00, 0x00, 0x00, 0x00, /* 364, PAGE4-108 */
2408 0x00, 0x00, 0x00, 0x00, /* 368, PAGE4-112*/
2409 0x00, 0x00, 0x00, 0x00, /* 372, PAGE4-116*/
2410 0x00, 0x00, 0x00, 0x00, /* 376, PAGE4-120*/
2411 0x00, 0x00, 0x00, 0x00, /* 380, PAGE4-124 Page 2 Registers Ends Here */
2412
2413};
2414
2415/*
2416 *------------------------------------------------------------------------------
2417 * aic3262 initialization data
2418 * This structure initialization contains the initialization required for
2419 * AIC326x.
2420 * These registers values (reg_val) are written into the respective AIC3262
2421 * register offset (reg_offset) to initialize AIC326x.
2422 * These values are used in aic3262_init() function only.
2423 *------------------------------------------------------------------------------
2424 */
2425static const struct aic3262_configs aic3262_reg_init[] = {
2426 /* CLOCKING */
2427
2428 {0, RESET_REG, 1},
2429 {0, RESET_REG, 0},
2430
2431 {0, PASI_DAC_DP_SETUP, 0xc0}, /*DAC */
2432 {0, DAC_MVOL_CONF, 0x00}, /*DAC un-muted*/
2433 /* set default volumes */
2434 {0, DAC_LVOL, 0x01},
2435 {0, DAC_RVOL, 0x01},
2436 {0, HPL_VOL, 0x80},
2437 {0, HPR_VOL, 0x80},
2438 {0, SPK_AMP_CNTL_R2, 0x14},
2439 {0, SPK_AMP_CNTL_R3, 0x14},
2440 {0, SPK_AMP_CNTL_R4, 0x33},
2441 {0, REC_AMP_CNTL_R5, 0x82},
2442 {0, RAMPR_VOL, 20},
2443 {0, RAMP_CNTL_R1, 70},
2444 {0, RAMP_CNTL_R2, 70},
2445
2446 /* DRC Defaults */
2447 {0, DRC_CNTL_R1, 0x6c},
2448 {0, DRC_CNTL_R2, 16},
2449
2450 /* DEPOP SETTINGS */
2451 {0, HP_DEPOP, 0x14},
2452 {0, RECV_DEPOP, 0x14},
2453
2454 {0, POWER_CONF, 0x00}, /* Disconnecting AVDD-DVD weak link*/
2455 {0, REF_PWR_DLY, 0x01},
2456 {0, CM_REG, 0x00}, /*CM - default*/
2457 {0, LDAC_PTM, 0}, /*LDAC_PTM - default*/
2458 {0, RDAC_PTM, 0}, /*RDAC_PTM - default*/
2459 {0, HP_CTL, 0x30}, /*HP output percentage - at 75%*/
2460 {0, LADC_VOL, 0x01}, /*LADC volume*/
2461 {0, RADC_VOL, 0x01}, /*RADC volume*/
2462
2463 {0, DAC_ADC_CLKIN_REG, 0x33}, /*DAC ADC CLKIN*/
2464 {0, PLL_CLKIN_REG, 0x00}, /*PLL CLKIN*/
2465 {0, PLL_PR_POW_REG, 0x11}, /*PLL Power=0-down, P=1, R=1 vals*/
2466 {0, 0x3d, 1},
2467
2468 {0, LMIC_PGA_PIN, 0x0}, /*IN1_L select - - 10k -LMICPGA_P*/
2469 {0, LMIC_PGA_MIN, 0x40}, /*CM to LMICPGA-M*/
2470 {0, RMIC_PGA_PIN, 0x0}, /*IN1_R select - - 10k -RMIC_PGA_P*/
2471 {0, RMIC_PGA_MIN, 0x0}, /*CM to RMICPGA_M*/
2472 {0, MIC_PWR_DLY , 33}, /*LMIC-PGA-POWERUP-DELAY - default*/
2473 {0, REF_PWR_DLY, 1}, /*FIXMELATER*/
2474
2475
2476 {0, ADC_CHANNEL_POW, 0x0}, /*ladc, radc ON , SOFT STEP disabled*/
2477 {0, ADC_FINE_GAIN, 0x00}, /*ladc - unmute, radc - unmute*/
2478 {0, MICL_PGA, 0x3f},
2479 {0, MICR_PGA, 0x3f},
2480 /*controls MicBias ext power based on B0_P1_R51_D6*/
2481 {0, MIC_BIAS_CNTL, 0x80},
2482 /* ASI1 Configuration */
2483 {0, ASI1_BUS_FMT, 0},
2484 {0, ASI1_BWCLK_CNTL_REG, 0x00}, /* originaly 0x24*/
2485 {0, ASI1_BCLK_N_CNTL, 1},
2486 {0, ASI1_BCLK_N, 0x04},
2487
2488 {0, MA_CNTL, 0}, /* Mixer Amp disabled */
2489 {0, LINE_AMP_CNTL_R2, 0x00}, /* Line Amp Cntl disabled */
2490
2491 /* ASI2 Configuration */
2492 {0, ASI2_BUS_FMT, 0},
2493 {0, ASI2_BCLK_N_CNTL, 0x01},
2494 {0, ASI2_BCLK_N, 0x04},
2495 {0, ASI2_BWCLK_OUT_CNTL, 0x20},
2496
2497 {0, BEEP_CNTL_R1, 0x05},
2498 {0, BEEP_CNTL_R2, 0x04},
2499
2500 /* Interrupt config for headset detection */
2501 {0,HEADSET_TUNING1_REG,0x7f},
2502 {0, INT1_CNTL, 0x40},
2503 /*{0, TIMER_REG, 0x8c},*/
2504 {0, INT_FMT, 0x40},
2505 {0, GPIO1_IO_CNTL, 0x14},
2506 {0, HP_DETECT, 0x96},
2507
2508#if defined(CONFIG_MINI_DSP)
2509 {0, 60, 0},
2510 {0, 61, 0},
2511 /* Added the below set of values after consulting the miniDSP
2512 * Program Section Array
2513 */
2514 {0, MINIDSP_ACCESS_CTRL, 0x00},
2515#endif
2516
2517
2518};
2519
2520static int reg_init_size =
2521 sizeof(aic3262_reg_init) / sizeof(struct aic3262_configs);
2522
2523static const unsigned int adc_ma_tlv[] = {
2524TLV_DB_RANGE_HEAD(4),
2525 0, 29, TLV_DB_SCALE_ITEM(-1450, 500, 0),
2526 30, 35, TLV_DB_SCALE_ITEM(-2060, 1000, 0),
2527 36, 38, TLV_DB_SCALE_ITEM(-2660, 2000, 0),
2528 39, 40, TLV_DB_SCALE_ITEM(-3610, 5000, 0),
2529};
2530static const DECLARE_TLV_DB_SCALE(lo_hp_tlv, -7830, 50, 0);
2531
2532static const struct snd_kcontrol_new mal_pga_mixer_controls[] = {
2533 SOC_DAPM_SINGLE("IN1L Switch", MA_CNTL, 5, 1, 0),
2534 SOC_DAPM_SINGLE_TLV("Left MicPGA Volume", LADC_PGA_MAL_VOL, 0,
2535 0x3f, 1, adc_ma_tlv),
2536
2537};
2538
2539static const struct snd_kcontrol_new mar_pga_mixer_controls[] = {
2540 SOC_DAPM_SINGLE("IN1R Switch", MA_CNTL, 4, 1, 0),
2541 SOC_DAPM_SINGLE_TLV("Right MicPGA Volume", RADC_PGA_MAR_VOL, 0,
2542 0x3f, 1, adc_ma_tlv),
2543};
2544
2545/* Left HPL Mixer */
2546static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
2547 SOC_DAPM_SINGLE("MAL Switch", HP_AMP_CNTL_R1, 7, 1, 0),
2548 SOC_DAPM_SINGLE("LDAC Switch", HP_AMP_CNTL_R1, 5, 1, 0),
2549 SOC_DAPM_SINGLE_TLV("LOL-B1 Volume", HP_AMP_CNTL_R2, 0,
2550 0x7f, 1, lo_hp_tlv),
2551};
2552
2553/* Right HPR Mixer */
2554static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
2555 SOC_DAPM_SINGLE_TLV("LOR-B1 Volume", HP_AMP_CNTL_R3, 0,
2556 0x7f, 1, lo_hp_tlv),
2557 SOC_DAPM_SINGLE("LDAC Switch", HP_AMP_CNTL_R1, 2, 1, 0),
2558 SOC_DAPM_SINGLE("RDAC Switch", HP_AMP_CNTL_R1, 4, 1, 0),
2559 SOC_DAPM_SINGLE("MAR Switch", HP_AMP_CNTL_R1, 6, 1, 0),
2560};
2561
2562/* Left LOL Mixer */
2563static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
2564 SOC_DAPM_SINGLE("MAL Switch", LINE_AMP_CNTL_R2, 7, 1, 0),
2565 SOC_DAPM_SINGLE("IN1L-B Switch", LINE_AMP_CNTL_R2, 3, 1,0),
2566 SOC_DAPM_SINGLE("LDAC Switch", LINE_AMP_CNTL_R1, 7, 1, 0),
2567 SOC_DAPM_SINGLE("RDAC Switch", LINE_AMP_CNTL_R1, 5, 1, 0),
2568};
2569
2570/* Right LOR Mixer */
2571static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
2572 SOC_DAPM_SINGLE("LOL Switch", LINE_AMP_CNTL_R1, 2, 1, 0),
2573 SOC_DAPM_SINGLE("RDAC Switch", LINE_AMP_CNTL_R1, 6, 1, 0),
2574 SOC_DAPM_SINGLE("MAR Switch", LINE_AMP_CNTL_R2, 6, 1, 0),
2575 SOC_DAPM_SINGLE("IN1R-B Switch", LINE_AMP_CNTL_R2, 0, 1,0),
2576};
2577
2578/* Left SPKL Mixer */
2579static const struct snd_kcontrol_new spkl_output_mixer_controls[] = {
2580 SOC_DAPM_SINGLE("MAL Switch", SPK_AMP_CNTL_R1, 7, 1, 0),
2581 SOC_DAPM_SINGLE_TLV("LOL Volume", SPK_AMP_CNTL_R2, 0, 0x7f,0,
2582 lo_hp_tlv),
2583 SOC_DAPM_SINGLE("SPR_IN Switch", SPK_AMP_CNTL_R1, 2, 1, 0),
2584};
2585
2586/* Right SPKR Mixer */
2587static const struct snd_kcontrol_new spkr_output_mixer_controls[] = {
2588 SOC_DAPM_SINGLE_TLV("LOR Volume", SPK_AMP_CNTL_R3, 0, 0x7f, 0,
2589 lo_hp_tlv),
2590 SOC_DAPM_SINGLE("MAR Switch", SPK_AMP_CNTL_R1, 6, 1, 0),
2591};
2592
2593/* REC Mixer */
2594static const struct snd_kcontrol_new rec_output_mixer_controls[] = {
2595 SOC_DAPM_SINGLE_TLV("LOL-B2 Volume", RAMP_CNTL_R1, 0, 0x7f,0,
2596 lo_hp_tlv),
2597 SOC_DAPM_SINGLE_TLV("IN1L Volume", IN1L_SEL_RM, 0, 0x7f, 1, lo_hp_tlv),
2598 SOC_DAPM_SINGLE_TLV("IN1R Volume", IN1R_SEL_RM, 0, 0x7f, 1, lo_hp_tlv),
2599 SOC_DAPM_SINGLE_TLV("LOR-B2 Volume", RAMP_CNTL_R2, 0,0x7f, 0,lo_hp_tlv),
2600};
2601
2602/* Left Input Mixer */
2603static const struct snd_kcontrol_new left_input_mixer_controls[] = {
2604 SOC_DAPM_SINGLE("IN1L Switch", LMIC_PGA_PIN, 6, 1, 0),
2605 SOC_DAPM_SINGLE("IN2L Switch", LMIC_PGA_PIN, 4, 1, 0),
2606 SOC_DAPM_SINGLE("IN3L Switch", LMIC_PGA_PIN, 2, 1, 0),
2607 SOC_DAPM_SINGLE("IN4L Switch", LMIC_PGA_PM_IN4, 5, 1, 0),
2608 SOC_DAPM_SINGLE("IN1R Switch", LMIC_PGA_PIN, 0, 1, 0),
2609 SOC_DAPM_SINGLE("IN2R Switch", LMIC_PGA_MIN, 4, 1, 0),
2610 SOC_DAPM_SINGLE("IN3R Switch", LMIC_PGA_MIN, 2, 1, 0),
2611 SOC_DAPM_SINGLE("IN4R Switch", LMIC_PGA_PM_IN4, 4, 1, 0),
2612 SOC_DAPM_SINGLE("CM2L Switch", LMIC_PGA_MIN, 0, 1, 0),
2613 SOC_DAPM_SINGLE("CM1L Switch", LMIC_PGA_MIN, 6, 1, 0),
2614};
2615
2616/* Right Input Mixer */
2617static const struct snd_kcontrol_new right_input_mixer_controls[] = {
2618 SOC_DAPM_SINGLE("IN1R Switch", RMIC_PGA_PIN, 6, 1, 0),
2619 SOC_DAPM_SINGLE("IN2R Switch", RMIC_PGA_PIN, 4, 1, 0),
2620 SOC_DAPM_SINGLE("IN3R Switch", RMIC_PGA_PIN, 2, 1, 0),
2621 SOC_DAPM_SINGLE("IN4R Switch", RMIC_PGA_PM_IN4, 5, 1, 0),
2622 SOC_DAPM_SINGLE("IN2L Switch", RMIC_PGA_PIN, 0, 1, 0),
2623 SOC_DAPM_SINGLE("IN1L Switch", RMIC_PGA_MIN, 4, 1, 0),
2624 SOC_DAPM_SINGLE("IN3L Switch", RMIC_PGA_MIN, 2, 1, 0),
2625 SOC_DAPM_SINGLE("IN4L Switch", RMIC_PGA_PM_IN4, 4, 1, 0),
2626 SOC_DAPM_SINGLE("CM1R Switch", RMIC_PGA_MIN, 6, 1, 0),
2627 SOC_DAPM_SINGLE("CM2R Switch", RMIC_PGA_MIN, 0, 1, 0),
2628};
2629
2630
2631static const char *asi1lin_text[] = {
2632 "Off", "ASI1 Left In","ASI1 Right In","ASI1 MonoMix In"
2633};
2634
2635SOC_ENUM_SINGLE_DECL(asi1lin_enum, ASI1_DAC_OUT_CNTL, 6, asi1lin_text);
2636
2637static const struct snd_kcontrol_new asi1lin_control =
2638 SOC_DAPM_ENUM("ASI1LIN Route", asi1lin_enum);
2639
2640
2641static const char *asi1rin_text[] = {
2642 "Off", "ASI1 Right In","ASI1 Left In","ASI1 MonoMix In"
2643};
2644
2645SOC_ENUM_SINGLE_DECL(asi1rin_enum, ASI1_DAC_OUT_CNTL, 4, asi1rin_text);
2646
2647static const struct snd_kcontrol_new asi1rin_control =
2648 SOC_DAPM_ENUM("ASI1RIN Route", asi1rin_enum);
2649
2650static const char *asi2lin_text[] = {
2651 "Off", "ASI2 Left In","ASI2 Right In","ASI2 MonoMix In"
2652};
2653
2654SOC_ENUM_SINGLE_DECL(asi2lin_enum, ASI2_DAC_OUT_CNTL, 6, asi2lin_text);
2655static const struct snd_kcontrol_new asi2lin_control =
2656 SOC_DAPM_ENUM("ASI2LIN Route", asi2lin_enum);
2657
2658static const char *asi2rin_text[] = {
2659 "Off", "ASI2 Right In","ASI2 Left In","ASI2 MonoMix In"
2660};
2661
2662
2663SOC_ENUM_SINGLE_DECL(asi2rin_enum, ASI2_DAC_OUT_CNTL, 4, asi2rin_text);
2664
2665static const struct snd_kcontrol_new asi2rin_control =
2666 SOC_DAPM_ENUM("ASI2RIN Route", asi2rin_enum);
2667
2668static const char *asi3lin_text[] = {
2669 "Off", "ASI3 Left In","ASI3 Right In","ASI3 MonoMix In"
2670};
2671
2672
2673SOC_ENUM_SINGLE_DECL(asi3lin_enum, ASI3_DAC_OUT_CNTL, 6, asi3lin_text);
2674static const struct snd_kcontrol_new asi3lin_control =
2675 SOC_DAPM_ENUM("ASI3LIN Route", asi3lin_enum);
2676
2677
2678static const char *asi3rin_text[] = {
2679 "Off", "ASI3 Right In","ASI3 Left In","ASI3 MonoMix In"
2680};
2681
2682
2683SOC_ENUM_SINGLE_DECL(asi3rin_enum, ASI3_DAC_OUT_CNTL, 4, asi3rin_text);
2684static const struct snd_kcontrol_new asi3rin_control =
2685 SOC_DAPM_ENUM("ASI3RIN Route", asi3rin_enum);
2686
2687
2688static const char *dacminidspin1_text[] = {
2689 "ASI1 In", "ASI2 In","ASI3 In","ADC MiniDSP Out"
2690};
2691
2692SOC_ENUM_SINGLE_DECL(dacminidspin1_enum, MINIDSP_PORT_CNTL_REG, 4, dacminidspin1_text);
2693static const struct snd_kcontrol_new dacminidspin1_control =
2694 SOC_DAPM_ENUM("DAC MiniDSP IN1 Route", dacminidspin1_enum);
2695
2696static const char *dacminidspin2_text[] = {
2697 "ASI1 In", "ASI2 In","ASI3 In"
2698};
2699
2700//static const struct soc_enum dacminidspin1_enum =
2701// SOC_ENUM_SINGLE(MINIDSP_DATA_PORT_CNTL, 5, 2, dacminidspin1_text);
2702SOC_ENUM_SINGLE_DECL(dacminidspin2_enum, MINIDSP_PORT_CNTL_REG, 2, dacminidspin2_text);
2703
2704static const struct snd_kcontrol_new dacminidspin2_control =
2705 SOC_DAPM_ENUM("DAC MiniDSP IN2 Route", dacminidspin2_enum);
2706
2707static const char *dacminidspin3_text[] = {
2708 "ASI1 In", "ASI2 In","ASI3 In"
2709};
2710
2711//static const struct soc_enum dacminidspin1_enum =
2712// SOC_ENUM_SINGLE(MINIDSP_DATA_PORT_CNTL, 5, 2, dacminidspin1_text);
2713SOC_ENUM_SINGLE_DECL(dacminidspin3_enum, MINIDSP_PORT_CNTL_REG, 0, dacminidspin3_text);
2714
2715static const struct snd_kcontrol_new dacminidspin3_control =
2716SOC_DAPM_ENUM("DAC MiniDSP IN3 Route", dacminidspin3_enum);
2717
2718static const char *asi1out_text[] = {
2719 "Off",
2720 "ASI1 Out",
2721 "ASI1In Bypass",
2722 "ASI2In Bypass",
2723 "ASI3In Bypass",
2724};
2725SOC_ENUM_SINGLE_DECL(asi1out_enum, ASI1_ADC_INPUT_CNTL, 0, asi1out_text);
2726static const struct snd_kcontrol_new asi1out_control =
2727 SOC_DAPM_ENUM("ASI1OUT Route", asi1out_enum);
2728
2729static const char *asi2out_text[] = {
2730 "Off",
2731 "ASI1 Out",
2732 "ASI1In Bypass",
2733 "ASI2In Bypass",
2734 "ASI3In Bypass",
2735 "ASI2 Out",
2736};
2737SOC_ENUM_SINGLE_DECL(asi2out_enum, ASI2_ADC_INPUT_CNTL, 0, asi2out_text);
2738static const struct snd_kcontrol_new asi2out_control =
2739 SOC_DAPM_ENUM("ASI2OUT Route", asi2out_enum);
2740static const char *asi3out_text[] = {
2741 "Off",
2742 "ASI1 Out",
2743 "ASI1In Bypass",
2744 "ASI2In Bypass",
2745 "ASI3In Bypass",
2746 "ASI3 Out",
2747};
2748SOC_ENUM_SINGLE_DECL(asi3out_enum, ASI3_ADC_INPUT_CNTL, 0, asi3out_text);
2749static const struct snd_kcontrol_new asi3out_control =
2750 SOC_DAPM_ENUM("ASI3OUT Route", asi3out_enum);
2751
2752static const char *asi1bclk_text[] = {
2753 "DAC_CLK",
2754 "DAC_MOD_CLK",
2755 "ADC_CLK",
2756 "ADC_MOD_CLK",
2757};
2758
2759SOC_ENUM_SINGLE_DECL(asi1bclk_enum, ASI1_BCLK_N_CNTL, 0, asi1bclk_text);
2760static const struct snd_kcontrol_new asi1bclk_control =
2761 SOC_DAPM_ENUM("ASI1_BCLK Route", asi1bclk_enum);
2762
2763static const char *asi2bclk_text[] = {
2764 "DAC_CLK",
2765 "DAC_MOD_CLK",
2766 "ADC_CLK",
2767 "ADC_MOD_CLK",
2768};
2769SOC_ENUM_SINGLE_DECL(asi2bclk_enum, ASI2_BCLK_N_CNTL, 0, asi2bclk_text);
2770static const struct snd_kcontrol_new asi2bclk_control =
2771 SOC_DAPM_ENUM("ASI2_BCLK Route", asi2bclk_enum);
2772static const char *asi3bclk_text[] = {
2773 "DAC_CLK",
2774 "DAC_MOD_CLK",
2775 "ADC_CLK",
2776 "ADC_MOD_CLK",
2777};
2778SOC_ENUM_SINGLE_DECL(asi3bclk_enum, ASI3_BCLK_N_CNTL, 0, asi3bclk_text);
2779static const struct snd_kcontrol_new asi3bclk_control =
2780 SOC_DAPM_ENUM("ASI3_BCLK Route", asi3bclk_enum);
2781
2782static int aic326x_hp_event(struct snd_soc_dapm_widget *w,
2783 struct snd_kcontrol *kcontrol, int event)
2784{
2785 return 0;
2786}
2787static int pll_power_on_event(struct snd_soc_dapm_widget *w,
2788 struct snd_kcontrol *kcontrol, int event)
2789{
2790 if (event == SND_SOC_DAPM_POST_PMU)
2791 {
2792 mdelay(10);
2793 }
2794 return 0;
2795}
2796
2797static int polling_loop(struct snd_soc_codec *codec, unsigned int reg,
2798 int mask, int on_off)
2799{
2800 unsigned int counter, status;
2801
2802 counter = 0;
2803 switch(on_off) {
2804 case 0: /*off*/
2805 do {
2806 status = snd_soc_read(codec, reg);
2807 counter++;
2808 } while ((counter < 500) && ((status & mask) == mask));
2809 break;
2810 case 1: /*on*/
2811 do {
2812 status = snd_soc_read(codec, reg);
2813 counter++;
2814 } while ((counter < 500) && ((status & mask) != mask));
2815 break;
2816 default:
2817 printk("%s: unknown arguement\n", __func__);
2818 break;
2819 }
2820
2821 printk("%s: exiting with count value %d \n", __func__, counter);
2822 if(counter >= 500)
2823 return -1;
2824 return 0;
2825}
2826
2827int poll_dac(struct snd_soc_codec *codec, int left_right, int on_off)
2828{
2829 int ret = 0;
2830
2831 aic3262_change_page(codec, 0);
2832 aic3262_change_book(codec, 0);
2833
2834 switch(on_off) {
2835
2836 case 0:/*power off polling*/
2837 /*DAC power polling logic*/
2838 switch(left_right) {
2839 case 0: /*left dac polling*/
2840 ret = polling_loop(codec, DAC_FLAG_R1, LDAC_POW_FLAG_MASK, 0);
2841 break;
2842 case 1:/*right dac polling*/
2843 ret = polling_loop(codec, DAC_FLAG_R1, RDAC_POW_FLAG_MASK, 0);
2844 break;
2845 }
2846 break;
2847 case 1:/*power on polling*/
2848 /*DAC power polling logic*/
2849 switch(left_right) {
2850 case 0: /*left dac polling*/
2851 ret = polling_loop(codec, DAC_FLAG_R1, LDAC_POW_FLAG_MASK, 1);
2852 break;
2853 case 1:/*right dac polling*/
2854 ret = polling_loop(codec, DAC_FLAG_R1, RDAC_POW_FLAG_MASK, 1);
2855 break;
2856 }
2857 break;
2858 default:
2859 printk("%s:unknown arguement\n", __func__);
2860 break;
2861 }
2862 if(ret)
2863 printk("%s: power %s %s failure", __func__, left_right?"right":"left", on_off?"on":"off");
2864 return ret;
2865}
2866
2867int poll_adc(struct snd_soc_codec *codec, int left_right, int on_off)
2868{
2869 int ret = 0;
2870
2871 aic3262_change_page(codec, 0);
2872 aic3262_change_book(codec, 0);
2873
2874 switch(on_off) {
2875
2876 case 0:/*power off polling*/
2877 /*DAC power polling logic*/
2878 switch(left_right) {
2879 case 0: /*left dac polling*/
2880 ret = polling_loop(codec, ADC_FLAG_R1, LADC_POW_FLAG_MASK, 0);
2881 break;
2882 case 1:/*right dac polling*/
2883 ret = polling_loop(codec, ADC_FLAG_R1, RADC_POW_FLAG_MASK, 0);
2884 break;
2885 }
2886 break;
2887 case 1:/*power on polling*/
2888 /*DAC power polling logic*/
2889 switch(left_right) {
2890 case 0: /*left dac polling*/
2891 ret = polling_loop(codec, ADC_FLAG_R1, LADC_POW_FLAG_MASK, 1);
2892 break;
2893 case 1:/*right dac polling*/
2894 ret = polling_loop(codec, ADC_FLAG_R1, RADC_POW_FLAG_MASK, 1);
2895 break;
2896 }
2897 break;
2898 default:
2899 printk("%s:unknown arguement\n", __func__);
2900 break;
2901 }
2902
2903 if(ret)
2904 printk("%s: power %s %s failure", __func__, left_right?"right":"left", on_off?"on":"off");
2905 return ret;
2906}
2907
2908static int slave_dac_event(struct snd_soc_dapm_widget *w,
2909 struct snd_kcontrol *kcontrol, int event)
2910
2911{
2912 struct snd_soc_codec *codec = w->codec;
2913
2914 if (event & SND_SOC_DAPM_POST_PMU) {
2915 /* Poll for DAC Power-up first */
2916 poll_dac(codec, 0, 1);
2917 poll_dac(codec, 1, 1);
2918 }
2919
2920 if (event & SND_SOC_DAPM_POST_PMD) {
2921 poll_dac(codec, 0, 0);
2922 poll_dac(codec, 1, 0);
2923 }
2924 return 0;
2925}
2926
2927
2928static int slave_adc_event(struct snd_soc_dapm_widget *w,
2929 struct snd_kcontrol *kcontrol, int event)
2930
2931{
2932 struct snd_soc_codec *codec = w->codec;
2933
2934 if (event & SND_SOC_DAPM_POST_PMU) {
2935
2936 /* Poll for ADC Power-up first */
2937 poll_adc(codec, 0, 1);
2938 poll_adc(codec, 1, 1);
2939 }
2940
2941
2942 if (event & SND_SOC_DAPM_POST_PMD) {
2943 poll_adc(codec, 0, 0);
2944 poll_adc(codec, 1, 0);
2945 }
2946
2947 return 0;
2948}
2949
2950static const struct snd_soc_dapm_widget aic3262_dapm_widgets[] = {
2951 /* TODO: Can we switch these off ? */
2952 SND_SOC_DAPM_AIF_IN("ASI1IN", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
2953 SND_SOC_DAPM_AIF_IN("ASI2IN", "ASI2 Playback", 0, SND_SOC_NOPM, 0, 0),
2954 SND_SOC_DAPM_AIF_IN("ASI3IN", "ASI3 Playback", 0, SND_SOC_NOPM, 0, 0),
2955
2956
2957 SND_SOC_DAPM_DAC_E("Left DAC", NULL, PASI_DAC_DP_SETUP, 7, 0,
2958 slave_dac_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
2959 SND_SOC_DAPM_PRE_PMD),
2960 SND_SOC_DAPM_DAC_E("Right DAC", NULL, PASI_DAC_DP_SETUP, 6, 0,
2961 slave_dac_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
2962 SND_SOC_DAPM_PRE_PMD),
2963
2964 /* dapm widget (path domain) for HPL Output Mixer */
2965 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
2966 &hpl_output_mixer_controls[0],
2967 ARRAY_SIZE(hpl_output_mixer_controls)),
2968
2969 /* dapm widget (path domain) for HPR Output Mixer */
2970 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
2971 &hpr_output_mixer_controls[0],
2972 ARRAY_SIZE(hpr_output_mixer_controls)),
2973
2974
2975 SND_SOC_DAPM_PGA_E("HPL Driver", HP_AMP_CNTL_R1, 1, 0, NULL, 0,
2976 aic326x_hp_event, SND_SOC_DAPM_POST_PMU),
2977 SND_SOC_DAPM_PGA_E("HPR Driver", HP_AMP_CNTL_R1, 0, 0, NULL, 0,
2978 aic326x_hp_event, SND_SOC_DAPM_POST_PMU),
2979
2980
2981 /* dapm widget (path domain) for LOL Output Mixer */
2982 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
2983 &lol_output_mixer_controls[0],
2984 ARRAY_SIZE(lol_output_mixer_controls)),
2985
2986 /* dapm widget (path domain) for LOR Output Mixer mixer */
2987 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
2988 &lor_output_mixer_controls[0],
2989 ARRAY_SIZE(lor_output_mixer_controls)),
2990
2991 SND_SOC_DAPM_PGA("LOL Driver", LINE_AMP_CNTL_R1, 1, 0, NULL, 0),
2992 SND_SOC_DAPM_PGA("LOR Driver", LINE_AMP_CNTL_R1, 0, 0, NULL, 0),
2993
2994
2995 /* dapm widget (path domain) for SPKL Output Mixer */
2996 SND_SOC_DAPM_MIXER("SPKL Output Mixer", SND_SOC_NOPM, 0, 0,
2997 &spkl_output_mixer_controls[0],
2998 ARRAY_SIZE(spkl_output_mixer_controls)),
2999
3000 /* dapm widget (path domain) for SPKR Output Mixer */
3001 SND_SOC_DAPM_MIXER("SPKR Output Mixer", SND_SOC_NOPM, 0, 0,
3002 &spkr_output_mixer_controls[0],
3003 ARRAY_SIZE(spkr_output_mixer_controls)),
3004
3005 SND_SOC_DAPM_PGA("SPKL Driver", SPK_AMP_CNTL_R1, 1, 0, NULL, 0),
3006 SND_SOC_DAPM_PGA("SPKR Driver", SPK_AMP_CNTL_R1, 0, 0, NULL, 0),
3007
3008
3009 /* dapm widget (path domain) for SPKR Output Mixer */
3010 SND_SOC_DAPM_MIXER("REC Output Mixer", SND_SOC_NOPM, 0, 0,
3011 &rec_output_mixer_controls[0],
3012 ARRAY_SIZE(rec_output_mixer_controls)),
3013
3014 SND_SOC_DAPM_PGA("RECP Driver", REC_AMP_CNTL_R5, 7, 0, NULL, 0),
3015 SND_SOC_DAPM_PGA("RECM Driver", REC_AMP_CNTL_R5, 6, 0, NULL, 0),
3016
3017
3018 SND_SOC_DAPM_MUX("ASI1LIN Route",
3019 SND_SOC_NOPM, 0, 0, &asi1lin_control),
3020 SND_SOC_DAPM_MUX("ASI1RIN Route",
3021 SND_SOC_NOPM, 0, 0, &asi1rin_control),
3022 SND_SOC_DAPM_MUX("ASI2LIN Route",
3023 SND_SOC_NOPM, 0, 0, &asi2lin_control),
3024 SND_SOC_DAPM_MUX("ASI2RIN Route",
3025 SND_SOC_NOPM, 0, 0, &asi2rin_control),
3026 SND_SOC_DAPM_MUX("ASI3LIN Route",
3027 SND_SOC_NOPM, 0, 0, &asi3lin_control),
3028 SND_SOC_DAPM_MUX("ASI3RIN Route",
3029 SND_SOC_NOPM, 0, 0, &asi3rin_control),
3030
3031 SND_SOC_DAPM_PGA("ASI1LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3032 SND_SOC_DAPM_PGA("ASI1RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3033 SND_SOC_DAPM_PGA("ASI2LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3034 SND_SOC_DAPM_PGA("ASI2RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3035 SND_SOC_DAPM_PGA("ASI3LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3036 SND_SOC_DAPM_PGA("ASI3RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3037
3038 SND_SOC_DAPM_PGA("ASI1LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3039 SND_SOC_DAPM_PGA("ASI1ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3040 SND_SOC_DAPM_PGA("ASI2LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3041 SND_SOC_DAPM_PGA("ASI2ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3042 SND_SOC_DAPM_PGA("ASI3LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3043 SND_SOC_DAPM_PGA("ASI3ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
3044
3045 SND_SOC_DAPM_PGA("ASI1MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3046 SND_SOC_DAPM_PGA("ASI2MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3047 SND_SOC_DAPM_PGA("ASI3MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
3048 /* TODO: Can we switch the ASIxIN off? */
3049 SND_SOC_DAPM_PGA("ASI1IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
3050 SND_SOC_DAPM_PGA("ASI2IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
3051 SND_SOC_DAPM_PGA("ASI3IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
3052
3053
3054 SND_SOC_DAPM_MUX("DAC MiniDSP IN1 Route",
3055 SND_SOC_NOPM, 0, 0, &dacminidspin1_control),
3056SND_SOC_DAPM_MUX("DAC MiniDSP IN2 Route",
3057 SND_SOC_NOPM, 0, 0, &dacminidspin2_control),
3058 SND_SOC_DAPM_MUX("DAC MiniDSP IN3 Route",
3059 SND_SOC_NOPM, 0, 0, &dacminidspin3_control),
3060
3061 SND_SOC_DAPM_PGA("CM", SND_SOC_NOPM, 0, 0, NULL, 0),
3062 SND_SOC_DAPM_PGA("CM1L", SND_SOC_NOPM, 0, 0, NULL, 0),
3063 SND_SOC_DAPM_PGA("CM2L", SND_SOC_NOPM, 0, 0, NULL, 0),
3064 SND_SOC_DAPM_PGA("CM1R", SND_SOC_NOPM, 0, 0, NULL, 0),
3065 SND_SOC_DAPM_PGA("CM2R", SND_SOC_NOPM, 0, 0, NULL, 0),
3066
3067 /* TODO: Can we switch these off ? */
3068 SND_SOC_DAPM_AIF_OUT("ASI1OUT","ASI1 Capture", 0, SND_SOC_NOPM, 0, 0),
3069 SND_SOC_DAPM_AIF_OUT("ASI2OUT", "ASI2 Capture",0, SND_SOC_NOPM, 0, 0),
3070 SND_SOC_DAPM_AIF_OUT("ASI3OUT", "ASI3 Capture",0, SND_SOC_NOPM, 0, 0),
3071
3072 SND_SOC_DAPM_MUX("ASI1OUT Route",
3073 SND_SOC_NOPM, 0, 0, &asi1out_control),
3074 SND_SOC_DAPM_MUX("ASI2OUT Route",
3075 SND_SOC_NOPM, 0, 0, &asi2out_control),
3076 SND_SOC_DAPM_MUX("ASI3OUT Route",
3077 SND_SOC_NOPM, 0, 0, &asi3out_control),
3078
3079 /* TODO: Will be used during MINIDSP programming */
3080 /* TODO: Can we switch them off? */
3081 SND_SOC_DAPM_PGA("ADC MiniDSP OUT1", SND_SOC_NOPM, 0, 0, NULL, 0),
3082 SND_SOC_DAPM_PGA("ADC MiniDSP OUT2", SND_SOC_NOPM, 0, 0, NULL, 0),
3083 SND_SOC_DAPM_PGA("ADC MiniDSP OUT3", SND_SOC_NOPM, 0, 0, NULL, 0),
3084
3085
3086
3087 SND_SOC_DAPM_ADC_E("Left ADC", NULL, ADC_CHANNEL_POW, 7, 0,
3088 slave_adc_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
3089 SND_SOC_DAPM_PRE_PMD),
3090 SND_SOC_DAPM_ADC_E("Right ADC", NULL, ADC_CHANNEL_POW, 6, 0,
3091 slave_adc_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
3092 SND_SOC_DAPM_PRE_PMD),
3093
3094 SND_SOC_DAPM_PGA("Left MicPGA",MICL_PGA, 7, 1, NULL, 0),
3095 SND_SOC_DAPM_PGA("Right MicPGA",MICR_PGA, 7, 1, NULL, 0),
3096
3097 SND_SOC_DAPM_PGA("MAL PGA", MA_CNTL, 3, 0, NULL, 0),
3098 SND_SOC_DAPM_PGA("MAR PGA", MA_CNTL, 2, 0, NULL, 0),
3099
3100
3101 /* dapm widget for MAL PGA Mixer*/
3102 SND_SOC_DAPM_MIXER("MAL PGA Mixer", SND_SOC_NOPM, 0, 0,
3103 &mal_pga_mixer_controls[0],
3104 ARRAY_SIZE(mal_pga_mixer_controls)),
3105
3106 /* dapm widget for MAR PGA Mixer*/
3107 SND_SOC_DAPM_MIXER("MAR PGA Mixer", SND_SOC_NOPM, 0, 0,
3108 &mar_pga_mixer_controls[0],
3109 ARRAY_SIZE(mar_pga_mixer_controls)),
3110
3111 /* dapm widget for Left Input Mixer*/
3112 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
3113 &left_input_mixer_controls[0],
3114 ARRAY_SIZE(left_input_mixer_controls)),
3115
3116 /* dapm widget for Right Input Mixer*/
3117 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
3118 &right_input_mixer_controls[0],
3119 ARRAY_SIZE(right_input_mixer_controls)),
3120
3121
3122 SND_SOC_DAPM_OUTPUT("HPL"),
3123 SND_SOC_DAPM_OUTPUT("HPR"),
3124 SND_SOC_DAPM_OUTPUT("LOL"),
3125 SND_SOC_DAPM_OUTPUT("LOR"),
3126 SND_SOC_DAPM_OUTPUT("SPKL"),
3127 SND_SOC_DAPM_OUTPUT("SPKR"),
3128 SND_SOC_DAPM_OUTPUT("RECP"),
3129 SND_SOC_DAPM_OUTPUT("RECM"),
3130
3131 SND_SOC_DAPM_INPUT("IN1L"),
3132 SND_SOC_DAPM_INPUT("IN2L"),
3133 SND_SOC_DAPM_INPUT("IN3L"),
3134 SND_SOC_DAPM_INPUT("IN4L"),
3135 SND_SOC_DAPM_INPUT("IN1R"),
3136 SND_SOC_DAPM_INPUT("IN2R"),
3137 SND_SOC_DAPM_INPUT("IN3R"),
3138 SND_SOC_DAPM_INPUT("IN4R"),
3139
3140
3141 SND_SOC_DAPM_MICBIAS("Mic Bias Ext", MIC_BIAS_CNTL, 6, 0),
3142 SND_SOC_DAPM_MICBIAS("Mic Bias Int", MIC_BIAS_CNTL, 2, 0),
3143
3144 SND_SOC_DAPM_SUPPLY("PLLCLK",PLL_PR_POW_REG,7,0,pll_power_on_event,
3145 SND_SOC_DAPM_POST_PMU),
3146 SND_SOC_DAPM_SUPPLY("DACCLK",NDAC_DIV_POW_REG,7,0, NULL, 0),
3147 SND_SOC_DAPM_SUPPLY("CODEC_CLK_IN",SND_SOC_NOPM,0,0, NULL, 0),
3148 SND_SOC_DAPM_SUPPLY("DAC_MOD_CLK",MDAC_DIV_POW_REG,7,0, NULL, 0),
3149 SND_SOC_DAPM_SUPPLY("ADCCLK",NADC_DIV_POW_REG,7,0, NULL, 0),
3150 SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK",MADC_DIV_POW_REG,7,0, NULL, 0),
3151 SND_SOC_DAPM_SUPPLY("ASI1_BCLK",ASI1_BCLK_N,7,0, NULL, 0),
3152 SND_SOC_DAPM_SUPPLY("ASI1_WCLK",ASI1_WCLK_N,7,0, NULL, 0),
3153 SND_SOC_DAPM_SUPPLY("ASI2_BCLK",ASI2_BCLK_N,7,0, NULL, 0),
3154 SND_SOC_DAPM_SUPPLY("ASI2_WCLK",ASI2_WCLK_N,7,0, NULL, 0),
3155 SND_SOC_DAPM_SUPPLY("ASI3_BCLK",ASI3_BCLK_N,7,0, NULL, 0),
3156 SND_SOC_DAPM_SUPPLY("ASI3_WCLK",ASI3_WCLK_N,7,0, NULL, 0),
3157 SND_SOC_DAPM_MUX("ASI1_BCLK Route",
3158 SND_SOC_NOPM, 0, 0, &asi1bclk_control),
3159 SND_SOC_DAPM_MUX("ASI2_BCLK Route", SND_SOC_NOPM, 0, 0, &asi2bclk_control),
3160 SND_SOC_DAPM_MUX("ASI3_BCLK Route", SND_SOC_NOPM, 0, 0, &asi3bclk_control),
3161};
3162
3163static const struct snd_soc_dapm_route aic3262_dapm_routes[] ={
3164 /* TODO: Do we need only DACCLK for ASIIN's and ADCCLK for ASIOUT??? */
3165 /* Clock portion */
3166 {"CODEC_CLK_IN", NULL, "PLLCLK"},
3167 {"DACCLK", NULL, "CODEC_CLK_IN"},
3168 {"ADCCLK", NULL, "CODEC_CLK_IN"},
3169 {"DAC_MOD_CLK", NULL, "DACCLK"},
3170#ifdef AIC3262_SYNC_MODE
3171 {"ADC_MOD_CLK", NULL,"DACCLK"},
3172#else
3173 {"ADC_MOD_CLK", NULL, "ADCCLK"},
3174#endif
3175
3176 {"ASI1_BCLK Route","DAC_CLK","DACCLK"},
3177 {"ASI1_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
3178 {"ASI1_BCLK Route","ADC_CLK","ADCCLK"},
3179 {"ASI1_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
3180
3181 {"ASI2_BCLK Route","DAC_CLK","DACCLK"},
3182 {"ASI2_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
3183 {"ASI2_BCLK Route","ADC_CLK","ADCCLK"},
3184 {"ASI2_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
3185
3186 {"ASI3_BCLK Route","DAC_CLK","DACCLK"},
3187 {"ASI3_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
3188 {"ASI3_BCLK Route","ADC_CLK","ADCCLK"},
3189 {"ASI3_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
3190
3191 {"ASI1_BCLK", NULL, "ASI1_BCLK Route"},
3192 {"ASI2_BCLK", NULL, "ASI2_BCLK Route"},
3193 {"ASI3_BCLK", NULL, "ASI3_BCLK Route"},
3194
3195
3196 {"ASI1IN", NULL , "PLLCLK"},
3197 {"ASI1IN", NULL , "DACCLK"},
3198 {"ASI1IN", NULL , "ADCCLK"},
3199 {"ASI1IN", NULL , "DAC_MOD_CLK"},
3200 {"ASI1IN", NULL , "ADC_MOD_CLK"},
3201
3202 {"ASI1OUT", NULL , "PLLCLK"},
3203 {"ASI1OUT", NULL , "DACCLK"},
3204 {"ASI1OUT", NULL , "ADCCLK"},
3205 {"ASI1OUT", NULL , "DAC_MOD_CLK"},
3206 {"ASI1OUT", NULL , "ADC_MOD_CLK"},
3207#ifdef AIC3262_ASI1_MASTER
3208 {"ASI1IN", NULL , "ASI1_BCLK"},
3209 {"ASI1OUT", NULL , "ASI1_BCLK"},
3210 {"ASI1IN", NULL , "ASI1_WCLK"},
3211 {"ASI1OUT", NULL , "ASI1_WCLK"},
3212#else
3213
3214#endif
3215
3216 {"ASI2IN", NULL , "PLLCLK"},
3217 {"ASI2IN", NULL , "DACCLK"},
3218 {"ASI2IN", NULL , "ADCCLK"},
3219 {"ASI2IN", NULL , "DAC_MOD_CLK"},
3220 {"ASI2IN", NULL , "ADC_MOD_CLK"},
3221
3222 {"ASI2OUT", NULL , "PLLCLK"},
3223 {"ASI2OUT", NULL , "DACCLK"},
3224 {"ASI2OUT", NULL , "ADCCLK"},
3225 {"ASI2OUT", NULL , "DAC_MOD_CLK"},
3226 {"ASI2OUT", NULL , "ADC_MOD_CLK"},
3227
3228#ifdef AIC3262_ASI2_MASTER
3229 {"ASI2IN", NULL , "ASI2_BCLK"},
3230 {"ASI2OUT", NULL , "ASI2_BCLK"},
3231 {"ASI2IN", NULL , "ASI2_WCLK"},
3232 {"ASI2OUT", NULL , "ASI2_WCLK"},
3233#else
3234
3235#endif
3236 {"ASI3IN", NULL , "PLLCLK"},
3237 {"ASI3IN", NULL , "DACCLK"},
3238 {"ASI3IN", NULL , "ADCCLK"},
3239 {"ASI3IN", NULL , "DAC_MOD_CLK"},
3240 {"ASI3IN", NULL , "ADC_MOD_CLK"},
3241
3242
3243 {"ASI3OUT", NULL , "PLLCLK"},
3244 {"ASI3OUT", NULL , "DACCLK"},
3245 {"ASI3OUT", NULL , "ADCCLK"},
3246 {"ASI3OUT", NULL , "DAC_MOD_CLK"},
3247 {"ASI3OUT", NULL , "ADC_MOD_CLK"},
3248
3249#ifdef AIC3262_ASI3_MASTER
3250 {"ASI3IN", NULL , "ASI3_BCLK"},
3251 {"ASI3OUT", NULL , "ASI3_BCLK"},
3252 {"ASI3IN", NULL , "ASI3_WCLK"},
3253 {"ASI3OUT", NULL , "ASI3_WCLK"},
3254#else
3255#endif
3256
3257/* Playback (DAC) Portion */
3258 {"HPL Output Mixer","LDAC Switch","Left DAC"},
3259 {"HPL Output Mixer","MAL Switch","MAL PGA"},
3260 {"HPL Output Mixer","LOL-B1 Volume","LOL"},
3261
3262 {"HPR Output Mixer","LOR-B1 Volume","LOR"},
3263 {"HPR Output Mixer","LDAC Switch","Left DAC"},
3264 {"HPR Output Mixer","RDAC Switch","Right DAC"},
3265 {"HPR Output Mixer","MAR Switch","MAR PGA"},
3266
3267 {"HPL Driver",NULL,"HPL Output Mixer"},
3268 {"HPR Driver",NULL,"HPR Output Mixer"},
3269
3270 {"HPL",NULL,"HPL Driver"},
3271 {"HPR",NULL,"HPR Driver"},
3272
3273 {"LOL Output Mixer","MAL Switch","MAL PGA"},
3274 {"LOL Output Mixer","IN1L-B Switch","IN1L"},
3275 {"LOL Output Mixer","LDAC Switch","Left DAC"},
3276 {"LOL Output Mixer","RDAC Switch","Right DAC"},
3277
3278 {"LOR Output Mixer","LOL Switch","LOL"},
3279 {"LOR Output Mixer","RDAC Switch","Right DAC"},
3280 {"LOR Output Mixer","MAR Switch","MAR PGA"},
3281 {"LOR Output Mixer","IN1R-B Switch","IN1R"},
3282
3283 {"LOL Driver",NULL,"LOL Output Mixer"},
3284 {"LOR Driver",NULL,"LOR Output Mixer"},
3285
3286 {"LOL",NULL,"LOL Driver"},
3287 {"LOR",NULL,"LOR Driver"},
3288
3289 {"REC Output Mixer","LOL-B2 Volume","LOL"},
3290 {"REC Output Mixer","IN1L Volume","IN1L"},
3291 {"REC Output Mixer","IN1R Volume","IN1R"},
3292 {"REC Output Mixer","LOR-B2 Volume","LOR"},
3293
3294 {"RECP Driver",NULL,"REC Output Mixer"},
3295 {"RECM Driver",NULL,"REC Output Mixer"},
3296
3297 {"RECP",NULL,"RECP Driver"},
3298 {"RECM",NULL,"RECM Driver"},
3299
3300 {"SPKL Output Mixer","MAL Switch","MAL PGA"},
3301 {"SPKL Output Mixer","LOL Volume","LOL"},
3302 {"SPKL Output Mixer","SPR_IN Switch","SPKR Output Mixer"},
3303
3304 {"SPKR Output Mixer", "LOR Volume","LOR"},
3305 {"SPKR Output Mixer", "MAR Switch","MAR PGA"},
3306
3307
3308 {"SPKL Driver",NULL,"SPKL Output Mixer"},
3309 {"SPKR Driver",NULL,"SPKR Output Mixer"},
3310
3311 {"SPKL",NULL,"SPKL Driver"},
3312 {"SPKR",NULL,"SPKR Driver"},
3313/* ASI Input routing */
3314 {"ASI1LIN", NULL, "ASI1IN"},
3315 {"ASI1RIN", NULL, "ASI1IN"},
3316 {"ASI2LIN", NULL, "ASI2IN"},
3317 {"ASI2RIN", NULL, "ASI2IN"},
3318 {"ASI3LIN", NULL, "ASI3IN"},
3319 {"ASI3RIN", NULL, "ASI3IN"},
3320
3321 {"ASI1MonoMixIN", NULL, "ASI1IN"},
3322 {"ASI2MonoMixIN", NULL, "ASI2IN"},
3323 {"ASI3MonoMixIN", NULL, "ASI3IN"},
3324
3325 {"ASI1LIN Route","ASI1 Left In","ASI1LIN"},
3326 {"ASI1LIN Route","ASI1 Right In","ASI1RIN"},
3327 {"ASI1LIN Route","ASI1 MonoMix In","ASI1MonoMixIN"},
3328
3329 {"ASI1RIN Route", "ASI1 Right In","ASI1RIN"},
3330 {"ASI1RIN Route","ASI1 Left In","ASI1LIN"},
3331 {"ASI1RIN Route","ASI1 MonoMix In","ASI1MonoMixIN"},
3332
3333
3334 {"ASI2LIN Route","ASI2 Left In","ASI2LIN"},
3335 {"ASI2LIN Route","ASI2 Right In","ASI2RIN"},
3336 {"ASI2LIN Route","ASI2 MonoMix In","ASI2MonoMixIN"},
3337
3338 {"ASI2RIN Route","ASI2 Right In","ASI2RIN"},
3339 {"ASI2RIN Route","ASI2 Left In","ASI2LIN"},
3340 {"ASI2RIN Route","ASI2 MonoMix In","ASI2MonoMixIN"},
3341
3342
3343 {"ASI3LIN Route","ASI3 Left In","ASI3LIN"},
3344 {"ASI3LIN Route","ASI3 Right In","ASI3RIN"},
3345 {"ASI3LIN Route","ASI3 MonoMix In","ASI3MonoMixIN"},
3346
3347 {"ASI3RIN Route","ASI3 Right In","ASI3RIN"},
3348 {"ASI3RIN Route","ASI3 Left In","ASI3LIN"},
3349 {"ASI3RIN Route","ASI3 MonoMix In","ASI3MonoMixIN"},
3350
3351 {"ASI1IN Port", NULL, "ASI1LIN Route"},
3352 {"ASI1IN Port", NULL, "ASI1RIN Route"},
3353 {"ASI2IN Port", NULL, "ASI2LIN Route"},
3354 {"ASI2IN Port", NULL, "ASI2RIN Route"},
3355 {"ASI3IN Port", NULL, "ASI3LIN Route"},
3356 {"ASI3IN Port", NULL, "ASI3RIN Route"},
3357
3358 {"DAC MiniDSP IN1 Route", "ASI1 In","ASI1IN Port"},
3359 {"DAC MiniDSP IN1 Route","ASI2 In","ASI2IN Port"},
3360 {"DAC MiniDSP IN1 Route","ASI3 In","ASI3IN Port"},
3361 {"DAC MiniDSP IN1 Route","ADC MiniDSP Out","ADC MiniDSP OUT1"},
3362
3363 {"DAC MiniDSP IN2 Route","ASI1 In","ASI1IN Port"},
3364 {"DAC MiniDSP IN2 Route","ASI2 In","ASI2IN Port"},
3365 {"DAC MiniDSP IN2 Route","ASI3 In","ASI3IN Port"},
3366
3367 {"DAC MiniDSP IN3 Route","ASI1 In","ASI1IN Port"},
3368 {"DAC MiniDSP IN3 Route","ASI2 In","ASI2IN Port"},
3369 {"DAC MiniDSP IN3 Route","ASI3 In","ASI3IN Port"},
3370
3371 {"Left DAC", "NULL", "DAC MiniDSP IN1 Route"},
3372 {"Right DAC", "NULL", "DAC MiniDSP IN1 Route"},
3373
3374 {"Left DAC", "NULL","DAC MiniDSP IN2 Route"},
3375 {"Right DAC", "NULL","DAC MiniDSP IN2 Route"},
3376
3377 {"Left DAC", "NULL","DAC MiniDSP IN3 Route"},
3378 {"Right DAC", "NULL","DAC MiniDSP IN3 Route"},
3379
3380
3381/* Mixer Amplifier */
3382
3383 {"MAL PGA Mixer", "IN1L Switch","IN1L"},
3384 {"MAL PGA Mixer", "Left MicPGA Volume","Left MicPGA"},
3385
3386 {"MAL PGA", NULL, "MAL PGA Mixer"},
3387
3388
3389 {"MAR PGA Mixer", "IN1R Switch","IN1R"},
3390 {"MAR PGA Mixer", "Right MicPGA Volume","Right MicPGA"},
3391
3392 {"MAR PGA", NULL, "MAR PGA Mixer"},
3393
3394
3395/* Capture (ADC) portions */
3396 /* Left Positive PGA input */
3397 {"Left Input Mixer","IN1L Switch","IN1L"},
3398 {"Left Input Mixer","IN2L Switch","IN2L"},
3399 {"Left Input Mixer","IN3L Switch","IN3L"},
3400 {"Left Input Mixer","IN4L Switch","IN4L"},
3401 {"Left Input Mixer","IN1R Switch","IN1R"},
3402 /* Left Negative PGA input */
3403 {"Left Input Mixer","IN2R Switch","IN2R"},
3404 {"Left Input Mixer","IN3R Switch","IN3R"},
3405 {"Left Input Mixer","IN4R Switch","IN4R"},
3406 {"Left Input Mixer","CM2L Switch","CM2L"},
3407 {"Left Input Mixer","CM1L Switch","CM1L"},
3408
3409 /* Right Positive PGA Input */
3410 {"Right Input Mixer","IN1R Switch","IN1R"},
3411 {"Right Input Mixer","IN2R Switch","IN2R"},
3412 {"Right Input Mixer","IN3R Switch","IN3R"},
3413 {"Right Input Mixer","IN4R Switch","IN4R"},
3414 {"Right Input Mixer","IN2L Switch","IN2L"},
3415
3416 /* Right Negative PGA Input */
3417 {"Right Input Mixer","IN1L Switch","IN1L"},
3418 {"Right Input Mixer","IN3L Switch","IN3L"},
3419 {"Right Input Mixer","IN4L Switch","IN4L"},
3420 {"Right Input Mixer","CM1R Switch","CM1R"},
3421 {"Right Input Mixer","CM2R Switch","CM2R"},
3422
3423 {"CM1L", NULL, "CM"},
3424 {"CM2L", NULL, "CM"},
3425 {"CM1R", NULL, "CM"},
3426 {"CM2R", NULL, "CM"},
3427
3428 {"Left MicPGA",NULL,"Left Input Mixer"},
3429 {"Right MicPGA",NULL,"Right Input Mixer"},
3430
3431 {"Left ADC", NULL, "Left MicPGA"},
3432 {"Right ADC", NULL, "Right MicPGA"},
3433
3434/* ASI Output Routing */
3435 {"ADC MiniDSP OUT1", NULL, "Left ADC"},
3436 {"ADC MiniDSP OUT1", NULL, "Right ADC"},
3437 {"ADC MiniDSP OUT2", NULL, "Left ADC"},
3438 {"ADC MiniDSP OUT2", NULL, "Right ADC"},
3439 {"ADC MiniDSP OUT3", NULL, "Left ADC"},
3440 {"ADC MiniDSP OUT3", NULL, "Right ADC"},
3441
3442 {"ASI1OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
3443 {"ASI1OUT Route", "ASI1In Bypass","ASI1IN Port"},
3444 {"ASI1OUT Route", "ASI2In Bypass","ASI2IN Port"},
3445 {"ASI1OUT Route", "ASI3In Bypass","ASI3IN Port"},
3446
3447 {"ASI2OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
3448 {"ASI2OUT Route", "ASI1In Bypass","ASI1IN Port"},
3449 {"ASI2OUT Route", "ASI2In Bypass","ASI2IN Port"},
3450 {"ASI2OUT Route", "ASI3In Bypass","ASI3IN Port"},
3451 {"ASI2OUT Route", "ASI2 Out","ADC MiniDSP OUT2"},// Port 2
3452
3453 {"ASI3OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
3454 {"ASI3OUT Route", "ASI1In Bypass","ASI1IN Port"},
3455 {"ASI3OUT Route", "ASI2In Bypass","ASI2IN Port"},
3456 {"ASI3OUT Route", "ASI3In Bypass","ASI3IN Port"},
3457 {"ASI3OUT Route", "ASI3 Out","ADC MiniDSP OUT3"},// Port 3
3458
3459 {"ASI1OUT",NULL,"ASI1OUT Route"},
3460 {"ASI2OUT",NULL,"ASI2OUT Route"},
3461 {"ASI3OUT",NULL,"ASI3OUT Route"},
3462
3463};
3464
3465
3466#define AIC3262_DAPM_ROUTE_NUM (sizeof(aic3262_dapm_routes)/sizeof(struct snd_soc_dapm_route))
3467
3468/*
3469 *****************************************************************************
3470 * Function Definitions
3471 *****************************************************************************
3472 */
3473
3474
3475/*
3476 *----------------------------------------------------------------------------
3477 * Function : aic3262_change_page
3478 * Purpose : This function is to switch between page 0 and page 1.
3479 *
3480 *----------------------------------------------------------------------------
3481 */
3482int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page)
3483{
3484 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3485 u8 data[2];
3486 int ret = 0;
3487
3488 data[0] = 0;
3489 data[1] = new_page;
3490 aic3262->page_no = new_page;
3491
3492#if defined(LOCAL_REG_ACCESS)
3493 if (codec->hw_write(codec->control_data, data, 2) != 2)
3494 ret = -EIO;
3495#else
3496 ret = snd_soc_write(codec, data[0], data[1]);
3497#endif
3498 if (ret)
3499 printk(KERN_ERR "Error in changing page to %d\n", new_page);
3500
3501 /*DBG("# Changing page to %d\r\n", new_page);*/
3502
3503 return ret;
3504}
3505/*
3506 *----------------------------------------------------------------------------
3507 * Function : aic3262_change_book
3508 * Purpose : This function is to switch between books
3509 *
3510 *----------------------------------------------------------------------------
3511 */
3512int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book)
3513{
3514 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3515 u8 data[2];
3516 int ret = 0;
3517
3518 data[0] = 0x7F;
3519 data[1] = new_book;
3520 aic3262->book_no = new_book;
3521
3522 ret = aic3262_change_page(codec, 0);
3523 if (ret)
3524 return ret;
3525
3526#if defined(LOCAL_REG_ACCESS)
3527 if (codec->hw_write(codec->control_data, data, 2) != 2)
3528 ret = -EIO;
3529#else
3530 ret = snd_soc_write(codec, data[0], data[1]);
3531#endif
3532 if (ret)
3533 printk(KERN_ERR "Error in changing Book\n");
3534
3535 /*DBG("# Changing book to %d\r\n", new_book);*/
3536
3537 return ret;
3538}
3539/*
3540 *----------------------------------------------------------------------------
3541 * Function : aic3262_write_reg_cache
3542 * Purpose : This function is to write aic3262 register cache
3543 *
3544 *----------------------------------------------------------------------------
3545 */
3546void aic3262_write_reg_cache(struct snd_soc_codec *codec,
3547 u16 reg, u8 value)
3548{
3549#if defined(EN_REG_CACHE)
3550 u8 *cache = codec->reg_cache;
3551
3552 if (reg >= AIC3262_CACHEREGNUM)
3553 return;
3554
3555 if (cache)
3556 cache[reg] = value;
3557#endif
3558}
3559
3560/*
3561 *----------------------------------------------------------------------------
3562 * Function : aic3262_read
3563 * Purpose : This function is to read the aic3262 register space.
3564 *
3565 *----------------------------------------------------------------------------
3566 */
3567
3568u8 aic3262_read(struct snd_soc_codec *codec, u16 reg)
3569{
3570 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3571 u8 value;
3572 u8 page = reg / 128;
3573 u16 *cache = codec->reg_cache;
3574 u16 cmd;
3575 u8 buffer[2];
3576 int rc;
3577 reg = reg % 128;
3578
3579 if (reg >= AIC3262_CACHEREGNUM) {
3580 return 0;
3581 }
3582
3583 if (aic3262->control_type == SND_SOC_I2C) {
3584 if (aic3262->page_no != page) {
3585 aic3262_change_page(codec, page);
3586 }
3587 i2c_master_send(codec->control_data, (char *)&reg, 1);
3588 i2c_master_recv(codec->control_data, &value, 1);
3589 /*DBG("r %2x %02x\r\n", reg, value); */
3590 } else if (aic3262->control_type == SND_SOC_SPI) {
3591 u16 value;
3592
3593 /* Do SPI transfer; first 16bits are command; remaining is
3594 * register contents */
3595 cmd = AIC3262_READ_COMMAND_WORD(reg);
3596 buffer[0] = (cmd >> 8) & 0xff;
3597 buffer[1] = cmd & 0xff;
3598 //rc = spi_write_then_read(aic3262->spi, buffer, 2, buffer, 2);
3599
3600 if (rc) {
3601 dev_err(&aic3262->spi->dev, "AIC26 reg read error\n");
3602 return -EIO;
3603 }
3604 value = (buffer[0] << 8) | buffer[1];
3605 } else {
3606 printk(KERN_ERR "Unknown Interface Type in aic3262_read\n");
3607 }
3608
3609 /* Update the cache before returning with the value */
3610 cache[reg] = value;
3611 return value;
3612
3613}
3614
3615/*
3616 *----------------------------------------------------------------------------
3617 * Function : aic3262_write
3618 * Purpose : This function is to write to the aic3262 register space.
3619 *
3620 *----------------------------------------------------------------------------
3621 */
3622int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value)
3623{
3624 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3625 u8 data[2];
3626 u8 page;
3627 int ret = 0;
3628
3629 page = reg / 128;
3630 data[AIC3262_REG_OFFSET_INDEX] = reg % 128;
3631 if (aic3262->page_no != page)
3632 aic3262_change_page(codec, page);
3633
3634 /* data is
3635 * D15..D8 aic3262 register offset
3636 * D7...D0 register data
3637 */
3638 data[AIC3262_REG_DATA_INDEX] = value & AIC3262_8BITS_MASK;
3639#if defined(EN_REG_CACHE)
3640 if ((page >= 0) & (page <= 4))
3641 aic3262_write_reg_cache(codec, reg, value);
3642
3643#endif
3644 if (!data[AIC3262_REG_OFFSET_INDEX]) {
3645 /* if the write is to reg0 update aic3262->page_no */
3646 aic3262->page_no = value;
3647 }
3648
3649 /*DBG("w %2x %02x\r\n",
3650 data[AIC3262_REG_OFFSET_INDEX], data[AIC3262_REG_DATA_INDEX]);*/
3651
3652#if defined(LOCAL_REG_ACCESS)
3653 if (codec->hw_write(codec->control_data, data, 2) != 2)
3654 ret = -EIO;
3655#else
3656 ret = snd_soc_write(codec, data[AIC3262_REG_OFFSET_INDEX],
3657 data[AIC3262_REG_DATA_INDEX]);
3658#endif
3659 if (ret)
3660 printk(KERN_ERR "Error in i2c write\n");
3661
3662 return ret;
3663}
3664
3665/*
3666 *------------------------------------------------------------------------------
3667 * Function : aic3262_write__
3668 * Purpose : This function is to write to the aic3262 register space.
3669 * (low level).
3670 *------------------------------------------------------------------------------
3671 */
3672
3673int aic3262_write__(struct i2c_client *client, const char *buf, int count)
3674{
3675 u8 data[3];
3676 int ret;
3677 data[0] = *buf;
3678 data[1] = *(buf+1);
3679 data[2] = *(buf+2);
3680 /*DBG("w %2x %02x\r\n",
3681 data[AIC3262_REG_OFFSET_INDEX], data[AIC3262_REG_DATA_INDEX]);*/
3682 ret = i2c_master_send(client, data, 2);
3683 if (ret < 2) {
3684 printk(
3685 KERN_ERR "I2C write Error : bytes written = %d\n\n", ret);
3686 return -EIO;
3687 }
3688
3689 return ret;
3690}
3691/*
3692 *----------------------------------------------------------------------------
3693 * Function : aic3262_reset_cache
3694 * Purpose : This function is to reset the cache.
3695 *----------------------------------------------------------------------------
3696 */
3697int aic3262_reset_cache(struct snd_soc_codec *codec)
3698{
3699#if defined(EN_REG_CACHE)
3700 if (codec->reg_cache) {
3701 memcpy(codec->reg_cache, aic3262_reg, sizeof(aic3262_reg));
3702 return 0;
3703 }
3704
3705 codec->reg_cache = kmemdup(aic3262_reg,
3706 sizeof(aic3262_reg), GFP_KERNEL);
3707 if (!codec->reg_cache) {
3708 printk(KERN_ERR "aic32x4: kmemdup failed\n");
3709 return -ENOMEM;
3710 }
3711#endif
3712 return 0;
3713}
3714
3715/*
3716 *----------------------------------------------------------------------------
3717 * Function : aic3262_get_divs
3718 * Purpose : This function is to get required divisor from the "aic3262_divs"
3719 * table.
3720 *
3721 *----------------------------------------------------------------------------
3722 */
3723static inline int aic3262_get_divs(int mclk, int rate)
3724{
3725 int i;
3726
3727 for (i = 0; i < ARRAY_SIZE(aic3262_divs); i++) {
3728 if ((aic3262_divs[i].rate == rate)
3729 && (aic3262_divs[i].mclk == mclk)) {
3730 DBG(KERN_INFO "#%s: Found Entry %d in Clock_Array\n",
3731 __func__, i);
3732 return i;
3733 }
3734 }
3735 printk(KERN_ERR "Master clock and sample rate is not supported\n");
3736 return -EINVAL;
3737}
3738
3739/*
3740 *----------------------------------------------------------------------------
3741 * Function : aic3262_add_widgets
3742 * Purpose : This function is to add the dapm widgets
3743 * The following are the main widgets supported
3744 * # Left DAC to Left Outputs
3745 * # Right DAC to Right Outputs
3746 * # Left Inputs to Left ADC
3747 * # Right Inputs to Right ADC
3748 *
3749 *----------------------------------------------------------------------------
3750 */
3751static int aic3262_add_widgets(struct snd_soc_codec *codec)
3752{
3753 int ret;
3754 struct snd_soc_dapm_context *dapm = &codec->dapm;
3755#ifndef AIC3262_MULTI_I2S
3756 int i;
3757 for (i = 0; i < ARRAY_SIZE(aic3262_dapm_widgets); i++)
3758 ret = snd_soc_dapm_new_control(dapm, &aic3262_dapm_widgets[i]);
3759#else
3760 ret = snd_soc_dapm_new_controls(dapm, aic3262_dapm_widgets,
3761 ARRAY_SIZE(aic3262_dapm_widgets));
3762 if (ret != 0) {
3763 printk(KERN_ERR "#%s: Unable to add DAPM Controls. Err %d\n",
3764 __func__, ret);
3765 }
3766#endif
3767 /* set up audio path interconnects */
3768 DBG("#Completed adding new dapm widget controls size=%d\n",
3769 ARRAY_SIZE(aic3262_dapm_widgets));
3770 snd_soc_dapm_add_routes(dapm, aic3262_dapm_routes,
3771 ARRAY_SIZE(aic3262_dapm_routes));
3772 DBG("#Completed adding DAPM routes\n");
3773 snd_soc_dapm_new_widgets(dapm);
3774 DBG("#Completed updating dapm\n");
3775 return 0;
3776}
3777/*
3778 *----------------------------------------------------------------------------
3779 * Function : reg_def_conf
3780 * Purpose : This function is to reset the codec book 0 registers
3781 *
3782 *----------------------------------------------------------------------------
3783 */
3784int reg_def_conf(struct snd_soc_codec *codec)
3785{
3786 int i = 0, ret;
3787 DBG(KERN_INFO "#%s: Invoked..\n", __func__);
3788
3789 ret = aic3262_change_page(codec, 0);
3790 if (ret != 0)
3791 return ret;
3792
3793 ret = aic3262_change_book(codec, 0);
3794 if (ret != 0)
3795 return ret;
3796
3797 /* Configure the Codec with the default Initialization Values */
3798 for (i = 0; i < reg_init_size; i++) {
3799 ret = snd_soc_write(codec, aic3262_reg_init[i].reg_offset,
3800 aic3262_reg_init[i].reg_val);
3801 if (ret)
3802 break;
3803 }
3804 DBG(KERN_INFO "#%s: Done..\n", __func__);
3805 return ret;
3806}
3807
3808/*
3809 * i2c_verify_book0
3810 *
3811 * This function is used to dump the values of the Book 0 Pages.
3812 */
3813int i2c_verify_book0(struct snd_soc_codec *codec)
3814{
3815 int i, j, k = 0;
3816 u8 val1;
3817
3818 DBG("starting i2c_verify\n");
3819 DBG("Resetting page to 0\n");
3820 aic3262_change_book(codec, 0);
3821 for (j = 0; j < 3; j++) {
3822 if (j == 0) {
3823 aic3262_change_page(codec, 0);
3824 k = 0;
3825 }
3826 if (j == 1) {
3827 aic3262_change_page(codec, 1);
3828 k = 1;
3829 }
3830 /*
3831 if (j == 2) {
3832 aic3262_change_page(codec, 4);
3833 k = 4;
3834 }*/
3835 for (i = 0; i <= 127; i++) {
3836#if defined(LOCAL_REG_ACCESS)
3837 val1 = i2c_smbus_read_byte_data(codec->control_data, i);
3838#else
3839 val1 = snd_soc_read(codec, i);
3840#endif
3841 /* printk("[%d][%d]=[0x%2x]\n",k,i,val1); */
3842 }
3843 }
3844 return 0;
3845}
3846
3847/*
3848 *----------------------------------------------------------------------------
3849 * Function : aic3262_set_bias_level
3850 * Purpose : This function is to get triggered when dapm events occurs.
3851 *
3852 *----------------------------------------------------------------------------
3853 */
3854
3855static int aic3262_set_bias_level(struct snd_soc_codec *codec,
3856 enum snd_soc_bias_level level)
3857{
3858 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3859 u8 value;
3860 switch (level) {
3861 /* full On */
3862 case SND_SOC_BIAS_ON:
3863
3864 /* all power is driven by DAPM system */
3865 dev_dbg(codec->dev, "set_bias_on\n");
3866 break;
3867
3868 /* partial On */
3869 case SND_SOC_BIAS_PREPARE:
3870
3871 dev_dbg(codec->dev, "set_bias_prepare\n");
3872
3873 break;
3874
3875 /* Off, with power */
3876 case SND_SOC_BIAS_STANDBY:
3877 /*
3878 * all power is driven by DAPM system,
3879 * so output power is safe if bypass was set
3880 */
3881 dev_dbg(codec->dev, "set_bias_stby\n");
3882
3883 break;
3884 /* Off, without power */
3885 case SND_SOC_BIAS_OFF:
3886 dev_dbg(codec->dev, "set_bias_off\n");
3887
3888 break;
3889 }
3890 codec->dapm.bias_level=level;
3891
3892 return 0;
3893}
3894
3895
3896/*
3897 *----------------------------------------------------------------------------
3898 * Function : aic3262_suspend
3899 * Purpose : This function is to suspend the AIC3262 driver.
3900 *
3901 *----------------------------------------------------------------------------
3902 */
3903static int aic3262_suspend(struct snd_soc_codec *codec, pm_message_t state)
3904{
3905 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3906 DBG(KERN_INFO "#%s: Invoked..\n", __func__);
3907 if (aic3262)
3908 disable_irq(aic3262->irq);
3909
3910 aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3911
3912 return 0;
3913}
3914
3915/*
3916 *----------------------------------------------------------------------------
3917 * Function : aic3262_resume
3918 * Purpose : This function is to resume the AIC3262 driver
3919 *
3920 *----------------------------------------------------------------------------
3921 */
3922static int aic3262_resume(struct snd_soc_codec *codec)
3923{
3924 int i;
3925 u8 data[2];
3926 int ret = 0;
3927 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3928 u8 *cache = codec->reg_cache;
3929 DBG(KERN_INFO "#%s: Invoked..\n", __func__);
3930
3931 ret = aic3262_change_page(codec, 0);
3932 if (ret)
3933 return ret;
3934#if defined(EN_REG_CACHE)
3935 /* Sync reg_cache with the hardware */
3936 for (i = 0; i < ARRAY_SIZE(aic3262_reg); i++) {
3937 data[0] = i % 128;
3938 data[1] = cache[i];
3939#if defined(LOCAL_REG_ACCESS)
3940 codec->hw_write(codec->control_data, data, 2);
3941#else
3942 ret = snd_soc_write(codec, data[0], data[1]);
3943 if (ret)
3944 break;
3945#endif
3946 }
3947#endif
3948 if (!ret) {
3949 aic3262_change_page(codec, 0);
3950 aic3262_set_bias_level(codec, SND_SOC_BIAS_ON);
3951
3952 if (aic3262)
3953 enable_irq(aic3262->irq);
3954 }
3955 return ret;
3956}
3957/*
3958 *----------------------------------------------------------------------------
3959 * Function : aic3262_hw_read
3960 * Purpose : This is a low level harware read function.
3961 *
3962 *----------------------------------------------------------------------------
3963 */
3964unsigned int aic3262_hw_read(struct snd_soc_codec *codec, unsigned int count)
3965{
3966 struct i2c_client *client = codec->control_data;
3967 unsigned int buf;
3968
3969 if (count > (sizeof(unsigned int)))
3970 return 0;
3971
3972 i2c_master_recv(client, (char *)&buf, count);
3973 return buf;
3974}
3975
3976/*
3977* aic3262_jack_handler
3978*
3979* This function is called from the Interrupt Handler
3980* to check the status of the AIC3262 Registers related to Headset Detection
3981*/
3982static irqreturn_t aic3262_jack_handler(int irq, void *data)
3983{
3984 struct snd_soc_codec *codec = data;
3985 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
3986 unsigned int value;
3987 unsigned int micbits, hsbits = 0;
3988 DBG(KERN_INFO "%s++\n", __func__);
3989
3990 aic3262_change_page(codec, 0);
3991
3992 /* Read the Jack Status Register*/
3993 value = snd_soc_read(codec, STICKY_FLAG2);
3994 DBG(KERN_INFO "reg44 0x%x\n", value);
3995
3996
3997 value = snd_soc_read(codec, INT_FLAG2);
3998 DBG(KERN_INFO "reg46 0x%x\n", value);
3999
4000 value = snd_soc_read(codec, DAC_FLAG_R1);
4001 DBG(KERN_INFO "reg37 0x%x\n", value);
4002
4003 micbits = value & DAC_FLAG_MIC_MASKBITS;
4004 DBG(KERN_INFO "micbits 0x%x\n", micbits);
4005
4006 hsbits = value & DAC_FLAG_HS_MASKBITS;
4007 DBG(KERN_INFO "hsbits 0x%x\n", hsbits);
4008
4009
4010 /* No Headphone or Headset*/
4011 if (!micbits && !hsbits) {
4012 DBG(KERN_INFO "no headset/headphone\n");
4013 snd_soc_jack_report(aic3262->headset_jack,
4014 0, SND_JACK_HEADSET);
4015 }
4016
4017 /* Headphone Detected */
4018 if ((micbits == DAC_FLAG_R1_NOMIC) || (hsbits)) {
4019 DBG(KERN_INFO "headphone\n");
4020 snd_soc_jack_report(aic3262->headset_jack,
4021 SND_JACK_HEADPHONE, SND_JACK_HEADSET);
4022 }
4023
4024 /* Headset Detected - only with capless */
4025 if (micbits == DAC_FLAG_R1_MIC) {
4026 DBG(KERN_INFO "headset\n");
4027 snd_soc_jack_report(aic3262->headset_jack,
4028 SND_JACK_HEADSET, SND_JACK_HEADSET);
4029 }
4030 DBG(KERN_INFO "%s--\n", __func__);
4031 return IRQ_HANDLED;
4032}
4033
4034/*
4035* aic326x_headset_detect
4036*
4037* Call-back function called to check the status of Headset Pin.
4038*/
4039int aic326x_headset_detect(struct snd_soc_codec *codec,
4040 struct snd_soc_jack *jack, int jack_type)
4041{
4042 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
4043
4044 aic3262->headset_jack = jack;
4045 /*Enable the Headset Interrupts*/
4046 snd_soc_write(codec, INT1_CNTL, 0x80);
4047
4048 return 0;
4049}
4050EXPORT_SYMBOL_GPL(aic326x_headset_detect);
4051
4052int aic326x_headset_button_init(struct snd_soc_codec *codec,
4053 struct snd_soc_jack *jack, int jack_type)
4054{
4055 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
4056
4057 aic3262->button_dev = input_allocate_device();
4058 aic3262->button_dev->name = "aic326x_headset_button";
4059 aic3262->button_dev->phys = "codec/input0";
4060 aic3262->button_dev->dev.parent = snd_card_get_device_link(codec->card->snd_card);
4061 input_set_capability(aic3262->button_dev, EV_KEY, KEY_MEDIA);
4062
4063 if (input_register_device(aic3262->button_dev))
4064 {
4065 printk( "Unable to register input device headset button");
4066 }
4067
4068 aic3262_jack_handler(aic3262->irq, codec);
4069 return 0;
4070}
4071#ifdef AIC3262_MULTI_I2S
4072/*
4073* aic3262_asi_default_config
4074*
4075* This function is used to perform the default pin configurations for
4076* the functionalities which are specific to each ASI Port of the AIC3262
4077* Audio Codec Chipset. The user is encouraged to change these values
4078* if required on their platforms.
4079*/
4080static void aic3262_asi_default_config(struct snd_soc_codec *codec)
4081{
4082 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
4083 u16 counter;
4084
4085 DBG(KERN_INFO
4086 "#%s: Invoked. Will Config ASI Registers to Defaults..\n",
4087 __func__);
4088 for (counter = 0; counter < MAX_ASI_COUNT; counter++) {
4089 aic3262->asiCtxt[counter].asi_active = 0;
4090 aic3262->asiCtxt[counter].bclk_div = 1;
4091 aic3262->asiCtxt[counter].wclk_div = 1;
4092 aic3262->asiCtxt[counter].port_muted = 1;
4093 aic3262->asiCtxt[counter].bclk_div_option =
4094 BDIV_CLKIN_DAC_MOD_CLK;
4095 aic3262->asiCtxt[counter].offset1 = 0;
4096 aic3262->asiCtxt[counter].offset2 = 0;
4097 }
4098 /* ASI1 Defaults */
4099 aic3262->asiCtxt[0].bclk_output = ASI1_BCLK_DIVIDER_OUTPUT;
4100 aic3262->asiCtxt[0].wclk_output = GENERATED_DAC_FS;
4101 aic3262->asiCtxt[0].left_dac_output = DAC_PATH_LEFT;
4102 aic3262->asiCtxt[0].right_dac_output = DAC_PATH_LEFT;
4103 aic3262->asiCtxt[0].adc_input = ADC_PATH_MINIDSP_1;
4104 aic3262->asiCtxt[0].dout_option = ASI_OUTPUT;
4105
4106 /* ASI2 Defaults */
4107 aic3262->asiCtxt[1].bclk_output = ASI2_BCLK_DIVIDER_OUTPUT;
4108 aic3262->asiCtxt[1].wclk_output = GENERATED_DAC_FS;
4109 aic3262->asiCtxt[1].left_dac_output = DAC_PATH_LEFT;
4110 aic3262->asiCtxt[1].right_dac_output = DAC_PATH_LEFT;
4111 aic3262->asiCtxt[1].adc_input = ADC_PATH_MINIDSP_2;
4112 aic3262->asiCtxt[1].dout_option = ASI_OUTPUT;
4113
4114 /* ASI3 Defaults */
4115 aic3262->asiCtxt[2].bclk_output = ASI3_BCLK_DIVIDER_OUTPUT;
4116 aic3262->asiCtxt[2].wclk_output = GENERATED_DAC_FS;
4117 aic3262->asiCtxt[2].left_dac_output = DAC_PATH_LEFT;
4118 aic3262->asiCtxt[2].right_dac_output = DAC_PATH_LEFT;
4119 aic3262->asiCtxt[2].adc_input = ADC_PATH_MINIDSP_3;
4120 aic3262->asiCtxt[2].dout_option = ASI2_INPUT;
4121 return;
4122}
4123
4124#endif /* #ifdef AIC3262_MULTI_I2S */
4125
4126/*
4127 *----------------------------------------------------------------------------
4128 * Function : aic3262_probe
4129 * Purpose : This is first driver function called by the SoC core driver.
4130 *
4131 *----------------------------------------------------------------------------
4132 */
4133
4134static int aic3262_probe(struct snd_soc_codec *codec)
4135{
4136 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
4137 int ret = 0;
4138
4139 DBG(KERN_INFO "#%s: Invoked..\n", __func__);
4140
4141#if defined(EN_REG_CACHE)
4142 codec->reg_cache =
4143 kmemdup(aic3262_reg, sizeof(aic3262_reg), GFP_KERNEL);
4144
4145 if (!codec->reg_cache) {
4146 printk(KERN_ERR "aic3262: kmemdup failed\n");
4147 return -ENOMEM;
4148 }
4149#else
4150 /* Setting cache bypass - not to overwrite the cache registers,
4151 Codec registers have 4 pages which is not handled in the common
4152 cache code properly - bypass it in write value and save it
4153 using separate call*/
4154 codec->cache_bypass = 1;
4155#endif
4156
4157#if defined(LOCAL_REG_ACCESS)
4158 codec->control_data = aic3262->control_data;
4159 codec->hw_write = (hw_write_t) aic3262_write__;
4160 codec->hw_read = aic3262_hw_read;
4161#else
4162 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
4163 if (ret != 0) {
4164 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
4165 return ret;
4166 }
4167#endif
4168 ret = reg_def_conf(codec);
4169 if (ret != 0) {
4170 printk(KERN_ERR "Failed to init TI codec: %d\n", ret);
4171 return ret;
4172 }
4173
4174 if (aic3262->irq) {
4175 /* audio interrupt */
4176 ret = request_threaded_irq(aic3262->irq, NULL,
4177 aic3262_jack_handler,
4178 IRQF_TRIGGER_FALLING,
4179 "tlv320aic3262", codec);
4180 if (ret) {
4181 printk(KERN_INFO "#%s: IRQ Registration failed..[%d]",
4182 __func__, ret);
4183 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
4184 return ret;
4185 } else
4186 DBG(KERN_INFO
4187 "#%s: irq Registration for IRQ %d done..\n",
4188 __func__, aic3262->irq);
4189 } else {
4190 DBG(KERN_INFO "#%s: I2C IRQ Configuration is Wrong. \
4191 Please check it..\n", __func__);
4192 }
4193
4194 aic3262_asi_default_config(codec);
4195
4196 /* off, with power on */
4197 aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
4198
4199 ret = snd_soc_add_controls(codec, aic3262_snd_controls,
4200 ARRAY_SIZE(aic3262_snd_controls));
4201 if(ret)
4202 {
4203 printk(KERN_INFO "%s failed\n", __func__);
4204 }
4205
4206 aic3262_add_widgets(codec);
4207 /*TODO*/
4208 snd_soc_write(codec, MIC_BIAS_CNTL, 0x66);
4209
4210#ifdef AIC3262_TiLoad
4211 ret = aic3262_driver_init(codec);
4212 if (ret < 0)
4213 printk(KERN_ERR
4214 "\nAIC3262 CODEC: aic3262_probe :TiLoad Initialization failed\n");
4215#endif
4216
4217
4218#ifdef CONFIG_MINI_DSP
4219 /* Program MINI DSP for ADC and DAC */
4220 aic3262_minidsp_program(codec);
4221 aic3262_add_minidsp_controls(codec);
4222 aic3262_change_book(codec, 0x0);
4223#endif
4224
4225#ifdef MULTIBYTE_CONFIG_SUPPORT
4226 aic3262_add_multiconfig_controls(codec);
4227#endif
4228
4229 DBG(KERN_INFO "#%s: done..\n", __func__);
4230 return ret;
4231}
4232
4233
4234
4235/*
4236 *----------------------------------------------------------------------------
4237 * Function : aic3262_remove
4238 * Purpose : to remove aic3262 soc device
4239 *
4240 *----------------------------------------------------------------------------
4241 */
4242static int aic3262_remove(struct snd_soc_codec *codec)
4243{
4244
4245 /* power down chip */
4246 aic3262_set_bias_level(codec, SND_SOC_BIAS_OFF);
4247
4248 return 0;
4249}
4250
4251
4252/*
4253 *----------------------------------------------------------------------------
4254 * @struct snd_soc_codec_device |
4255 * This structure is soc audio codec device sturecute which pointer
4256 * to basic functions aic3262_probe(), aic3262_remove(),
4257 * aic3262_suspend() and aic3262_resume()
4258 *----------------------------------------------------------------------------
4259 */
4260static struct snd_soc_codec_driver soc_codec_dev_aic3262 = {
4261 .probe = aic3262_probe,
4262 .remove = aic3262_remove,
4263 .suspend = aic3262_suspend,
4264 .resume = aic3262_resume,
4265 .set_bias_level = aic3262_set_bias_level,
4266#if defined(LOCAL_REG_ACCESS)
4267 .read = aic3262_read,
4268 .write = aic3262_write,
4269#endif
4270#if !defined(EN_REG_CACHE)
4271 .reg_cache_size = ARRAY_SIZE(aic3262_reg),
4272 .reg_word_size = sizeof(u8),
4273 .reg_cache_default = aic3262_reg,
4274#endif
4275};
4276
4277
4278#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4279/*
4280 *----------------------------------------------------------------------------
4281 * Function : aic3262_codec_probe
4282 * Purpose : This function attaches the i2c client and initializes
4283 * AIC3262 CODEC.
4284 * NOTE:
4285 * This function is called from i2c core when the I2C address is
4286 * valid.
4287 * If the i2c layer weren't so broken, we could pass this kind of
4288 * data around
4289 *
4290 *----------------------------------------------------------------------------
4291 */
4292static __devinit int aic3262_codec_probe(struct i2c_client *i2c,
4293 const struct i2c_device_id *id)
4294{
4295 int ret;
4296
4297 struct aic3262_priv *aic3262;
4298
4299 DBG(KERN_INFO "#%s: Entered\n", __func__);
4300
4301 aic3262 = kzalloc(sizeof(struct aic3262_priv), GFP_KERNEL);
4302
4303 if (!aic3262) {
4304 printk(KERN_ERR "#%s: Unable to Allocate Priv struct..\n",
4305 __func__);
4306 return -ENOMEM;
4307 }
4308
4309 i2c_set_clientdata(i2c, aic3262);
4310#if defined(LOCAL_REG_ACCESS)
4311 aic3262->control_data = i2c;
4312#endif
4313 aic3262->control_type = SND_SOC_I2C;
4314 aic3262->irq = i2c->irq;
4315 aic3262->pdata = i2c->dev.platform_data;
4316
4317 /* The Configuration Support will be by default to 3 which
4318 * holds the MAIN Patch Configuration.
4319 */
4320 aic3262->current_dac_config[0] = -1;
4321 aic3262->current_dac_config[1] = -1;
4322 aic3262->current_adc_config[0] = -1;
4323 aic3262->current_adc_config[1] = -1;
4324
4325 aic3262->mute_codec = 1;
4326
4327 aic3262->page_no = 0;
4328 aic3262->book_no = 0;
4329 aic3262->active_count = 0;
4330 aic3262->dac_clkin_option = 3;
4331 aic3262->adc_clkin_option = 3;
4332
4333 ret = snd_soc_register_codec(&i2c->dev,
4334 &soc_codec_dev_aic3262,
4335 tlv320aic3262_dai, ARRAY_SIZE(tlv320aic3262_dai));
4336
4337 if (ret < 0)
4338 kfree(aic3262);
4339 DBG(KERN_INFO "#%s: Done ret %d\n", __func__, ret);
4340 return ret;
4341}
4342
4343/*
4344 *----------------------------------------------------------------------------
4345 * Function : aic3262_i2c_remove
4346 * Purpose : This function removes the i2c client and uninitializes
4347 * AIC3262 CODEC.
4348 * NOTE:
4349 * This function is called from i2c core
4350 * If the i2c layer weren't so broken, we could pass this kind of
4351 * data around
4352 *
4353 *----------------------------------------------------------------------------
4354 */
4355static __devexit int aic3262_i2c_remove(struct i2c_client *i2c)
4356{
4357 snd_soc_unregister_codec(&i2c->dev);
4358 kfree(i2c_get_clientdata(i2c));
4359 return 0;
4360}
4361
4362static const struct i2c_device_id tlv320aic3262_id[] = {
4363 {"aic3262-codec", 0},
4364 {}
4365};
4366MODULE_DEVICE_TABLE(i2c, tlv320aic3262_id);
4367
4368static struct i2c_driver tlv320aic3262_i2c_driver = {
4369 .driver = {
4370 .name = "aic3262-codec",
4371 .owner = THIS_MODULE,
4372 },
4373 .probe = aic3262_codec_probe,
4374 .remove = __devexit_p(aic3262_i2c_remove),
4375 .id_table = tlv320aic3262_id,
4376};
4377#endif /*#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)*/
4378
4379#if defined(CONFIG_SPI_MASTER)
4380static int aic3262_spi_write(struct spi_device *spi, const char *data, int len)
4381{
4382 struct spi_transfer t;
4383 struct spi_message m;
4384 u8 msg[2];
4385
4386 if (len <= 0)
4387 return 0;
4388
4389 msg[0] = data[0];
4390 msg[1] = data[1];
4391
4392 spi_message_init(&m);
4393 memset(&t, 0, (sizeof t));
4394 t.tx_buf = &msg[0];
4395 t.len = len;
4396
4397 spi_message_add_tail(&t, &m);
4398 spi_sync(spi, &m);
4399
4400 return len;
4401}
4402
4403/*
4404 * This function forces any delayed work to be queued and run.
4405 */
4406static int run_delayed_work(struct delayed_work *dwork)
4407{
4408 int ret;
4409
4410 /* cancel any work waiting to be queued. */
4411 ret = cancel_delayed_work(dwork);
4412
4413 /* if there was any work waiting then we run it now and
4414 * wait for it's completion */
4415 if (ret) {
4416 schedule_delayed_work(dwork, 0);
4417 flush_scheduled_work();
4418 }
4419 return ret;
4420}
4421static int __devinit aic3262_spi_probe(struct spi_device *spi)
4422{
4423 int ret;
4424 struct snd_soc_codec *codec;
4425 struct aic3262_priv *aic3262;
4426 printk(KERN_INFO "%s entering\n",__func__);
4427 aic3262 = kzalloc(sizeof(struct aic3262_priv), GFP_KERNEL);
4428
4429 if (!aic3262) {
4430 printk(KERN_ERR "#%s: Unable to Allocate Priv struct..\n",
4431 __func__);
4432 return -ENOMEM;
4433 }
4434 codec = &aic3262->codec;
4435 codec->control_data = spi;
4436 aic3262->control_type = SND_SOC_SPI;
4437 codec->hw_write = (hw_write_t)aic3262_spi_write;
4438 codec->dev = &spi->dev;
4439
4440 aic3262->pdata = spi->dev.platform_data;
4441
4442 /* The Configuration Support will be by default to 3 which
4443 * holds the MAIN Patch Configuration.
4444 */
4445 aic3262->current_dac_config[0] = -1;
4446 aic3262->current_dac_config[1] = -1;
4447 aic3262->current_adc_config[0] = -1;
4448 aic3262->current_adc_config[1] = -1;
4449
4450 aic3262->mute_codec = 1;
4451
4452 aic3262->page_no = 0;
4453 aic3262->book_no = 0;
4454 aic3262->active_count = 0;
4455 aic3262->dac_clkin_option = 3;
4456 aic3262->adc_clkin_option = 3;
4457 dev_set_drvdata(&spi->dev, aic3262);
4458 spi_set_drvdata(spi, aic3262);
4459 ret = snd_soc_register_codec(&spi->dev,
4460 &soc_codec_dev_aic3262,
4461 tlv320aic3262_dai, ARRAY_SIZE(tlv320aic3262_dai));
4462
4463 if (ret < 0) {
4464 printk(KERN_INFO "%s codec registeration failed\n",__func__);
4465 kfree(aic3262);
4466 }
4467 else {
4468 printk(KERN_INFO "%s registered\n",__func__);
4469 }
4470 printk(KERN_INFO "#%s: Done ret %d\n", __func__, ret);
4471 return ret;
4472}
4473
4474static int __devexit aic3262_spi_remove(struct spi_device *spi)
4475{
4476 struct aic3262_priv *aic3262 = dev_get_drvdata(&spi->dev);
4477 aic3262_set_bias_level(&aic3262->codec, SND_SOC_BIAS_OFF);
4478 snd_soc_unregister_codec(&spi->dev);
4479 kfree(aic3262);
4480 aic3262_codec = NULL;
4481 return 0;
4482
4483}
4484
4485static struct spi_driver aic3262_spi_driver = {
4486 .driver = {
4487 .name = "aic3262-codec",
4488 .bus = &spi_bus_type,
4489 .owner = THIS_MODULE,
4490 },
4491 .probe = aic3262_spi_probe,
4492 .remove = __devexit_p(aic3262_spi_remove),
4493};
4494#endif
4495static int __init tlv320aic3262_modinit(void)
4496{
4497 int ret = 0;
4498 printk(KERN_INFO "In %s\n",__func__);
4499#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4500 ret = i2c_add_driver(&tlv320aic3262_i2c_driver);
4501 if (ret != 0)
4502 printk(KERN_ERR "Failed to register aic326x i2c driver %d\n",
4503 ret);
4504#endif
4505#if defined(CONFIG_SPI_MASTER)
4506 printk(KERN_INFO "Inside config_spi_master\n");
4507 ret = spi_register_driver(&aic3262_spi_driver);
4508 if (ret != 0)
4509 printk(KERN_ERR "Failed to register aic3262 SPI driver: %d\n", ret);
4510#endif
4511 return ret;
4512
4513}
4514
4515module_init(tlv320aic3262_modinit);
4516
4517static void __exit tlv320aic3262_exit(void)
4518{
4519#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4520 i2c_del_driver(&tlv320aic3262_i2c_driver);
4521#endif
4522}
4523module_exit(tlv320aic3262_exit);
4524
4525MODULE_DESCRIPTION("ASoC TLV320AIC3262 codec driver");
4526MODULE_AUTHOR("Barani Prashanth<gvbarani@mistralsolutions.com>");
4527MODULE_AUTHOR("Ravindra<ravindra@mistralsolutions.com>");
4528MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320aic326x.h b/sound/soc/codecs/tlv320aic326x.h
new file mode 100644
index 00000000000..a31cc9eca5c
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x.h
@@ -0,0 +1,684 @@
1/*
2 * linux/sound/soc/codecs/tlv320aic3262.h
3 *
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 * History:
16 * Rev 0.1 ASoC driver support 20-01-2011
17 *
18 * The AIC3262 ASoC driver is ported for the codec AIC3262.
19 *
20 */
21
22#ifndef _TLV320AIC3262_H
23#define _TLV320AIC3262_H
24#include <linux/input.h>
25#define AUDIO_NAME "aic3262"
26#define AIC3262_VERSION "1.1"
27
28//#define AIC3262_ASI2_MASTER 1
29
30/* Enable this macro allow for different ASI formats */
31/*#define ASI_MULTI_FMT*/
32#undef ASI_MULTI_FMT
33
34#define INT_FLAG2_BUTTN_PRESSBIT 0x20
35
36/* Enable register caching on write */
37#define EN_REG_CACHE 1
38
39#define MULTIBYTE_CONFIG_SUPPORT
40
41/*Setting all codec reg/write locally*/
42/* This definition is added as the snd_ direct call are
43result some issue with cache. Common code doesnot support
44page, so fix that before commenting this line*/
45#define LOCAL_REG_ACCESS 1
46
47/* Macro to enable the inclusion of tiload kernel driver */
48#define AIC3262_TiLoad
49
50
51/* Macro enables or disables support for miniDSP in the driver */
52/* Enable the AIC3262_TiLoad macro first before enabling these macros */
53#define CONFIG_MINI_DSP
54/*#undef CONFIG_MINI_DSP*/
55
56/* Enable or disable controls to have Input routing*/
57/*#define FULL_IN_CNTL */
58#undef FULL_IN_CNTL
59/* AIC3262 supported sample rate are 8k to 192k */
60#define AIC3262_RATES SNDRV_PCM_RATE_8000_192000
61
62/* AIC3262 supports the word formats 16bits, 20bits, 24bits and 32 bits */
63#define AIC3262_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
64 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
65
66#define AIC3262_FREQ_12000000 12000000
67#define AIC3262_FREQ_12288000 12288000
68#define AIC3262_FREQ_24000000 24000000
69
70/* Macro for enabling the Multi_I2S Support in Driver */
71#define AIC3262_MULTI_I2S 1
72
73/* Driver Debug Messages Enabled */
74//#define DEBUG
75
76#ifdef DEBUG
77 #define DBG(x...) printk(x)
78#else
79 #define DBG(x...)
80#endif
81
82/*Select the below macro to decide on the DAC master volume controls.
83 *2 independent or one combined
84 */
85/*#define DAC_INDEPENDENT_VOL*/
86#undef DAC_INDEPENDENT_VOL
87
88/* Audio data word length = 16-bits (default setting) */
89#define AIC3262_WORD_LEN_16BITS 0x00
90#define AIC3262_WORD_LEN_20BITS 0x01
91#define AIC3262_WORD_LEN_24BITS 0x02
92#define AIC3262_WORD_LEN_32BITS 0x03
93
94/* sink: name of target widget */
95#define AIC3262_WIDGET_NAME 0
96/* control: mixer control name */
97#define AIC3262_CONTROL_NAME
98/* source: name of source name */
99#define AIC3262_SOURCE_NAME 2
100
101/* D15..D8 aic3262 register offset */
102#define AIC3262_REG_OFFSET_INDEX 0
103/* D7...D0 register data */
104#define AIC3262_REG_DATA_INDEX 1
105
106/* Serial data bus uses I2S mode (Default mode) */
107#define AIC3262_I2S_MODE 0x00
108#define AIC3262_DSP_MODE 0x01
109#define AIC3262_RIGHT_JUSTIFIED_MODE 0x02
110#define AIC3262_LEFT_JUSTIFIED_MODE 0x03
111
112/* 8 bit mask value */
113#define AIC3262_8BITS_MASK 0xFF
114
115/* shift value for CLK_REG_3 register */
116#define CLK_REG_3_SHIFT 6
117/* shift value for DAC_OSR_MSB register */
118#define DAC_OSR_MSB_SHIFT 4
119
120/* number of codec specific register for configuration */
121#define NO_FEATURE_REGS 2
122
123/* Total number of ASI Ports */
124#define MAX_ASI_COUNT 3
125
126
127/* AIC3262 register space */
128/* Updated from 256 to support Page 3 registers */
129#define AIC3262_CACHEREGNUM 1024
130#define BIT7 (0x01 << 7)
131#define BIT6 (0x01 << 6)
132#define BIT5 (0x01 << 5)
133#define BIT4 (0x01 << 4)
134#define BIT3 (0x01 << 3)
135#define BIT2 (0x01 << 2)
136#define BIT1 (0x01 << 1)
137#define BIT0 (0x01 << 0)
138
139#define DAC_FLAG_MIC_MASKBITS 0x30
140#define DAC_FLAG_HS_MASKBITS 0x03
141#define DAC_FLAG_R1_NOJACK 0
142#define DAC_FLAG_R1_NOMIC (0x1 << 4)
143#define DAC_FLAG_R1_MIC (0x3 << 4)
144#define DAC_FLAG_R1_NOHS 0
145#define DAC_FLAG_R1_MONOHS 1
146#define DAC_FLAG_R1_STEREOHS 2
147
148/*mask patterns for DAC and ADC polling logic*/
149#define LDAC_POW_FLAG_MASK 0x80
150#define RDAC_POW_FLAG_MASK 0x08
151#define LADC_POW_FLAG_MASK 0x40
152#define RADC_POW_FLAG_MASK 0x04
153
154/* ****************** Book 0 Registers **************************************/
155
156/* ****************** Page 0 Registers **************************************/
157
158#define PAGE_SEL_REG 0
159#define RESET_REG 1
160#define DAC_ADC_CLKIN_REG 4
161#define PLL_CLKIN_REG 5
162#define PLL_CLK_RANGE_REG 5
163#define PLL_PR_POW_REG 6
164#define PLL_J_REG 7
165#define PLL_D_MSB 8
166#define PLL_D_LSB 9
167#define PLL_CKIN_DIV 10
168
169#define NDAC_DIV_POW_REG 11
170#define MDAC_DIV_POW_REG 12
171#define DOSR_MSB_REG 13
172#define DOSR_LSB_REG 14
173
174#define NADC_DIV_POW_REG 18
175#define MADC_DIV_POW_REG 19
176#define AOSR_REG 20
177#define CLKOUT_MUX 21
178#define CLKOUT_MDIV_VAL 22
179#define TIMER_REG 23
180
181#define LF_CLK_CNTL 24
182#define HF_CLK_CNTL_R1 25
183#define HF_CLK_CNTL_R2 26
184#define HF_CLK_CNTL_R3 27
185#define HF_CLK_CNTL_R4 28
186#define HF_CLK_TRIM_R1 29
187#define HF_CLK_TRIM_R2 30
188#define HF_CLK_TRIM_R3 31
189#define HF_CLK_TRIM_R4 32
190#define ADC_FLAG_R1 36
191#define DAC_FLAG_R1 37
192#define DAC_FLAG_R2 38
193
194#define STICKY_FLAG1 42
195#define INT_FLAG1 43
196#define STICKY_FLAG2 44
197#define STICKY_FLAG3 45
198#define INT_FLAG2 46
199#define INT1_CNTL 48
200#define INT2_CNTL 49
201#define INT_FMT 51
202
203#define DAC_PRB 60
204#define ADC_PRB 61
205#define PASI_DAC_DP_SETUP 63
206#define DAC_MVOL_CONF 64
207#define DAC_LVOL 65
208#define DAC_RVOL 66
209#define HP_DETECT 67
210#define DRC_CNTL_R1 68
211#define DRC_CNTL_R2 69
212#define DRC_CNTL_R3 70
213#define BEEP_CNTL_R1 71
214#define BEEP_CNTL_R2 72
215
216#define ADC_CHANNEL_POW 81
217#define ADC_FINE_GAIN 82
218#define LADC_VOL 83
219#define RADC_VOL 84
220#define ADC_PHASE 85
221
222#define LAGC_CNTL 86
223#define LAGC_CNTL_R2 87
224#define LAGC_CNTL_R3 88
225#define LAGC_CNTL_R4 89
226#define LAGC_CNTL_R5 90
227#define LAGC_CNTL_R6 91
228#define LAGC_CNTL_R7 92
229#define LAGC_CNTL_R8 93
230
231#define RAGC_CNTL 94
232#define RAGC_CNTL_R2 95
233#define RAGC_CNTL_R3 96
234#define RAGC_CNTL_R4 97
235#define RAGC_CNTL_R5 98
236#define RAGC_CNTL_R6 99
237#define RAGC_CNTL_R7 100
238#define RAGC_CNTL_R8 101
239#define MINIDSP_ACCESS_CTRL 121
240/* ****************** Page 1 Registers **************************************/
241#define PAGE_1 128
242
243#define POWER_CONF (PAGE_1 + 1)
244#define LDAC_PTM (PAGE_1 + 3)
245#define RDAC_PTM (PAGE_1 + 4)
246#define CM_REG (PAGE_1 + 8)
247#define HP_CTL (PAGE_1 + 9)
248#define HP_DEPOP (PAGE_1 + 11)
249#define RECV_DEPOP (PAGE_1 + 12)
250#define MA_CNTL (PAGE_1 + 17)
251#define LADC_PGA_MAL_VOL (PAGE_1 + 18)
252#define RADC_PGA_MAR_VOL (PAGE_1 + 19)
253
254
255#define LINE_AMP_CNTL_R1 (PAGE_1 + 22)
256#define LINE_AMP_CNTL_R2 (PAGE_1 + 23)
257
258#define HP_AMP_CNTL_R1 (PAGE_1 + 27)
259#define HP_AMP_CNTL_R2 (PAGE_1 + 28)
260#define HP_AMP_CNTL_R3 (PAGE_1 + 29)
261
262#define HPL_VOL (PAGE_1 + 31)
263#define HPR_VOL (PAGE_1 + 32)
264#define INT1_SEL_L (PAGE_1 + 34)
265#define RAMP_CNTL_R1 (PAGE_1 + 36)
266#define RAMP_CNTL_R2 (PAGE_1 + 37)
267//#define INT1_SEL_RM (PAGE_1 + 39)
268#define IN1L_SEL_RM (PAGE_1 + 39)
269#define IN1R_SEL_RM (PAGE_1 + 39)
270
271#define REC_AMP_CNTL_R5 (PAGE_1 + 40)
272#define RAMPR_VOL (PAGE_1 + 41)
273#define RAMP_TIME_CNTL (PAGE_1 + 42)
274#define SPK_AMP_CNTL_R1 (PAGE_1 + 45)
275#define SPK_AMP_CNTL_R2 (PAGE_1 + 46)
276#define SPK_AMP_CNTL_R3 (PAGE_1 + 47)
277#define SPK_AMP_CNTL_R4 (PAGE_1 + 48)
278#define MIC_BIAS_CNTL (PAGE_1 + 51)
279
280#define LMIC_PGA_PIN (PAGE_1 + 52)
281#define LMIC_PGA_PM_IN4 (PAGE_1 + 53)
282#define LMIC_PGA_MIN (PAGE_1 + 54)
283#define RMIC_PGA_PIN (PAGE_1 + 55)
284#define RMIC_PGA_PM_IN4 (PAGE_1 + 56)
285#define RMIC_PGA_MIN (PAGE_1 + 57)
286/* MIC PGA Gain Registers */
287#define MICL_PGA (PAGE_1 + 59)
288#define MICR_PGA (PAGE_1 + 60)
289#define HEADSET_TUNING1_REG (PAGE_1 + 119)
290#define HEADSET_TUNING2_REG (PAGE_1 + 120)
291#define MIC_PWR_DLY (PAGE_1 + 121)
292#define REF_PWR_DLY (PAGE_1 + 122)
293
294/* ****************** Page 4 Registers **************************************/
295#define PAGE_4 512
296#define ASI1_BUS_FMT (PAGE_4 + 1)
297#define ASI1_LCH_OFFSET (PAGE_4 + 2)
298#define ASI1_RCH_OFFSET (PAGE_4 + 3)
299#define ASI1_CHNL_SETUP (PAGE_4 + 4)
300#define ASI1_MULTI_CH_SETUP_R1 (PAGE_4 + 5)
301#define ASI1_MULTI_CH_SETUP_R2 (PAGE_4 + 6)
302#define ASI1_ADC_INPUT_CNTL (PAGE_4 + 7)
303#define ASI1_DAC_OUT_CNTL (PAGE_4 + 8)
304#define ASI1_ADC_OUT_TRISTATE (PAGE_4 + 9)
305#define ASI1_BWCLK_CNTL_REG (PAGE_4 + 10)
306#define ASI1_BCLK_N_CNTL (PAGE_4 + 11)
307#define ASI1_BCLK_N (PAGE_4 + 12)
308#define ASI1_WCLK_N (PAGE_4 + 13)
309#define ASI1_BWCLK_OUT_CNTL (PAGE_4 + 14)
310#define ASI1_DATA_OUT (PAGE_4 + 15)
311#define ASI2_BUS_FMT (PAGE_4 + 17)
312#define ASI2_LCH_OFFSET (PAGE_4 + 18)
313#define ASI2_RCH_OFFSET (PAGE_4 + 19)
314#define ASI2_ADC_INPUT_CNTL (PAGE_4 + 23)
315#define ASI2_DAC_OUT_CNTL (PAGE_4 + 24)
316#define ASI2_BWCLK_CNTL_REG (PAGE_4 + 26)
317#define ASI2_BCLK_N_CNTL (PAGE_4 + 27)
318#define ASI2_BCLK_N (PAGE_4 + 28)
319#define ASI2_WCLK_N (PAGE_4 + 29)
320#define ASI2_BWCLK_OUT_CNTL (PAGE_4 + 30)
321#define ASI2_DATA_OUT (PAGE_4 + 31)
322#define ASI3_BUS_FMT (PAGE_4 + 33)
323#define ASI3_LCH_OFFSET (PAGE_4 + 34)
324#define ASI3_RCH_OFFSET (PAGE_4 + 35)
325#define ASI3_ADC_INPUT_CNTL (PAGE_4 + 39)
326#define ASI3_DAC_OUT_CNTL (PAGE_4 + 40)
327#define ASI3_BWCLK_CNTL_REG (PAGE_4 + 42)
328#define ASI3_BCLK_N_CNTL (PAGE_4 + 43)
329#define ASI3_BCLK_N (PAGE_4 + 44)
330#define ASI3_WCLK_N (PAGE_4 + 45)
331#define ASI3_BWCLK_OUT_CNTL (PAGE_4 + 46)
332#define ASI3_DATA_OUT (PAGE_4 + 47)
333#define WCLK1_PIN_CNTL_REG (PAGE_4 + 65)
334#define DOUT1_PIN_CNTL_REG (PAGE_4 + 67)
335#define DIN1_PIN_CNTL_REG (PAGE_4 + 68)
336#define WCLK2_PIN_CNTL_REG (PAGE_4 + 69)
337#define BCLK2_PIN_CNTL_REG (PAGE_4 + 70)
338#define DOUT2_PIN_CNTL_REG (PAGE_4 + 71)
339#define DIN2_PIN_CNTL_REG (PAGE_4 + 72)
340#define WCLK3_PIN_CNTL_REG (PAGE_4 + 73)
341#define BCLK3_PIN_CNTL_REG (PAGE_4 + 74)
342#define DOUT3_PIN_CNTL_REG (PAGE_4 + 75)
343#define DIN3_PIN_CNTL_REG (PAGE_4 + 76)
344#define MCLK2_PIN_CNTL_REG (PAGE_4 + 82)
345#define GPIO1_IO_CNTL (PAGE_4 + 86)
346#define GPIO2_IO_CNTL (PAGE_4 + 87)
347#define GPI1_EN (PAGE_4 + 91)
348#define GPO2_EN (PAGE_4 + 92)
349#define GPO1_PIN_CNTL (PAGE_4 + 96)
350#define MINIDSP_PORT_CNTL_REG (PAGE_4 + 118)
351
352/****************************************************************************
353* Mixer control related #defines
354***************************************************************************
355*/
356#define WCLK1_ENUM 0
357#define DOUT1_ENUM 1
358#define DIN1_ENUM 2
359#define WCLK2_ENUM 3
360#define BCLK2_ENUM 4
361#define DOUT2_ENUM 5
362#define DIN2_ENUM 6
363#define WCLK3_ENUM 7
364#define BCLK3_ENUM 8
365#define DOUT3_ENUM 9
366#define DIN3_ENUM 10
367#define CLKIN_ENUM 11
368/*
369*****************************************************************************
370* Enumeration Definitions
371*****************************************************************************
372*/
373/* The below enumeration lists down all the possible inputs to the
374* the PLL of the AIC3262. The Private structure will hold a member
375* of this Enumeration Type.
376*/
377enum AIC3262_PLL_OPTION {
378 PLL_CLKIN_MCLK1 = 0, /* 0000: (Device Pin) */
379 PLL_CLKIN_BLKC1, /* 0001: (Device Pin) */
380 PLL_CLKIN_GPIO1, /* 0010: (Device Pin)*/
381 PLL_CLKIN_DIN1, /* 0011: (Device Pin)*/
382 PLL_CLKIN_BCLK2, /* 0100: (Device Pin)*/
383 PLL_CLKIN_GPI1, /* 0101: (Device Pin)*/
384 PLL_CLKIN_HF_REF_CLK, /* 0110: (Device Pin)*/
385 PLL_CLKIN_GPIO2, /* 0111: (Device Pin)*/
386 PLL_CLKIN_GPI2, /* 1000: (Device Pin)*/
387 PLL_CLKIN_MCLK2 /* 1001: (Device Pin)*/
388};
389
390/* ASI Specific Bit Clock Divider Input Options.
391* Please refer to Page 4 Reg 11, Reg 27 and Reg 43
392*/
393enum ASI_BDIV_CLKIN_OPTION {
394 BDIV_CLKIN_DAC_CLK = 0, /* 00 DAC_CLK */
395 BDIV_CLKIN_DAC_MOD_CLK, /* 01 DAC_MOD_CLK */
396 BDIV_CLKIN_ADC_CLK, /* 02 ADC_CLK */
397 BDIV_CLKIN_ADC_MOD_CLK /* 03 ADC_MOD_CLK */
398};
399
400/* ASI Specific Bit Clock Output Mux Options.
401* Please refer to Page 4 Reg 14, Reg 30 and Reg 46
402* Please note that we are not handling the Reserved
403* cases here.
404*/
405enum ASI_BCLK_OPTION {
406 ASI1_BCLK_DIVIDER_OUTPUT = 0, /* 00 ASI1 Bit Clock Divider Output */
407 ASI1_BCLK_INPUT, /* 01 ASI1 Bit Clock Input */
408 ASI2_BCLK_DIVIDER_OUTPUT, /* 02 ASI2 Bit Clock Divider Output */
409 ASI2_BCLK_INPUT, /* 03 ASI2 Bit Clock Input */
410 ASI3_BCLK_DIVIDER_OUTPUT, /* 04 ASI3 Bit Clock Divider Output */
411 ASI3_BBCLK_INPUT /* 05 ASi3 Bit Clock Input */
412};
413
414/* Above bits are to be configured after Shifting 4 bits */
415#define AIC3262_ASI_BCLK_MUX_SHIFT 4
416#define AIC3262_ASI_BCLK_MUX_MASK (BIT6 | BIT5 | BIT4)
417#define AIC3262_ASI_WCLK_MUX_MASK (BIT2 | BIT1 | BIT0)
418
419/* ASI Specific Word Clock Output Mux Options */
420enum ASI_WCLK_OPTION {
421 GENERATED_DAC_FS = 0, /* 00 WCLK = DAC_FS */
422 GENERATED_ADC_FS = 1, /* 01 WCLK = ADC_FS */
423 ASI1_WCLK_DIV_OUTPUT = 2, /* 02 WCLK = ASI1 WCLK_DIV_OUT */
424 ASI1_WCLK_INPUT = 3, /* 03 WCLK = ASI1 WCLK Input */
425 ASI2_WCLK_DIV_OUTPUT = 4, /* 04 WCLK = ASI2 WCLK_DIV_OUT */
426 ASI2_WCLK_INPUT = 5, /* 05 WCLK = ASI2 WCLK Input */
427 ASI3_WCLK_DIV_OUTPUT = 6, /* 06 WCLK = ASI3 WCLK_DIV_OUT */
428 ASI3_WCLK_INPUT = 7 /* 07 WCLK = ASI3 WCLK Input */
429};
430
431/* ASI DAC Output Control Options */
432enum ASI_DAC_OUTPUT_OPTION {
433 DAC_PATH_OFF = 0, /* 00 DAC Datapath Off */
434 DAC_PATH_LEFT, /* 01 DAC Datapath left Data */
435 DAC_PATH_RIGHT, /* 02 DAC Datapath Right Data */
436};
437
438#define AIC3262_READ_COMMAND_WORD(addr) ((1 << 15) | (addr << 5))
439#define AIC3262_WRITE_COMMAND_WORD(addr) ((0 << 15) | (addr << 5))
440
441/* Shift the above options by so many bits */
442#define AIC3262_ASI_LDAC_PATH_SHIFT 6
443#define AIC3262_ASI_LDAC_PATH_MASK (BIT5 | BIT4)
444#define AIC3262_ASI_RDAC_PATH_SHIFT 4
445#define AIC3262_ASI_RDAC_PATH_MASK (BIT7 | BIT6)
446
447
448#define DAC_LR_MUTE_MASK 0xc
449#define DAC_LR_MUTE 0xc
450#define ENABLE_CLK_MASK 0x80
451#define ENABLE_CLK 0x80
452
453/* ASI specific ADC Input Control Options */
454enum ASI_ADC_INPUT_OPTION {
455 ADC_PATH_OFF = 0, /* 00 ASI Digital Output Disabled */
456 ADC_PATH_MINIDSP_1, /* 01 ASI Digital O/P from miniDSP_A(L1,R1) */
457 ADC_PATH_ASI1, /* 02 ASI Digital Output from ASI1 */
458 ADC_PATH_ASI2, /* 03 ASI Digital Output from ASI2 */
459 ADC_PATH_ASI3, /* 04 ASI Digital Output from ASI3 */
460 ADC_PATH_MINIDSP_2, /* 05 ASI Digital O/P from miniDSP_A(L2,R2) */
461 ADC_PATH_MINIDSP_3 /* 05 ASI Digital O/P from miniDSP_A(L3,R3) */
462};
463
464/* ASI Specific DOUT Pin Options */
465enum ASI_DOUT_OPTION {
466 ASI_OUTPUT = 0, /* 00 Default ASI Output */
467 ASI1_INPUT, /* 01 ASI1 Data Input */
468 ASI2_INPUT, /* 02 ASI2 Data Input */
469 ASI3_INPUT /* 03 ASI3 Data Input */
470};
471
472#define AIC3262_ASI_DOUT_MASK (BIT1 | BIT0)
473
474/*
475 *****************************************************************************
476 * Structures Definitions
477 *****************************************************************************
478 */
479#define AIC3262_MULTI_ASI_ACTIVE(x) (((x)->asiCtxt[0].asi_active) || \
480 ((x)->asiCtxt[1].asi_active) || \
481 ((x)->asiCtxt[2].asi_active))
482
483/*
484*----------------------------------------------------------------------------
485* @struct aic3262_setup_data |
486* i2c specific data setup for AIC3262.
487* @field unsigned short |i2c_address |
488* Unsigned short for i2c address.
489*----------------------------------------------------------------------------
490*/
491 struct aic3262_setup_data {
492 unsigned short i2c_address;
493};
494
495/*
496*----------------------------------------------------------------------------
497* @struct aic3262_asi_data
498* ASI specific data stored for each ASI Interface
499*
500*
501*---------------------------------------------------------------------------
502*/
503struct aic3262_asi_data {
504 u8 asi_active; /* ASI Active Flag */
505 u8 master; /* Frame Master */
506 u32 sampling_rate; /* Sampling Rate */
507 enum ASI_BDIV_CLKIN_OPTION bclk_div_option; /* BCLK DIV Mux Option*/
508 enum ASI_BCLK_OPTION bclk_output; /* BCLK Output Option*/
509 enum ASI_WCLK_OPTION wclk_output; /* WCLK Output Option*/
510 u8 bclk_div; /* BCLK Divider */
511 u8 wclk_div; /* WCLK Divider */
512 enum ASI_DAC_OUTPUT_OPTION left_dac_output; /* LDAC Path */
513 enum ASI_DAC_OUTPUT_OPTION right_dac_output; /* RDAC Path */
514 enum ASI_ADC_INPUT_OPTION adc_input; /* ADC Input Control */
515 enum ASI_DOUT_OPTION dout_option; /* DOUT Option */
516 u8 playback_mode; /* Playback Selected */
517 u8 capture_mode; /* Record Selected */
518 u8 port_muted; /* ASI Muted */
519 u8 pcm_format; /* PCM Format */
520 u8 word_len; /* Word Length */
521 u8 offset1; /* Left Ch offset */
522 u8 offset2; /* Right Ch Offset */
523};
524
525/*
526*----------------------------------------------------------------------------
527* @struct aic3262_priv |
528* AIC3262 priviate data structure to set the system clock, mode and
529* page number.
530* @field u32 | sysclk |
531* system clock
532* @field s32 | master |
533* master/slave mode setting for AIC3262
534* @field u8 | book_no |
535* book number.
536* @field u8 | page_no |
537* page number. Here, page 0 and page 1 are used.
538*----------------------------------------------------------------------------
539*/
540struct aic3262_priv {
541 enum snd_soc_control_type control_type;
542 struct aic326x_pdata *pdata;
543 struct snd_soc_codec codec;
544 u32 sysclk;
545 s32 master;
546 u8 book_no;
547 u8 page_no;
548 u8 process_flow;
549 u8 mute_codec;
550 u8 stream_status;
551 u32 active_count;
552 int current_dac_config[MAX_ASI_COUNT];
553 int current_adc_config[MAX_ASI_COUNT];
554 int current_config;
555 struct aic3262_asi_data asiCtxt[MAX_ASI_COUNT];
556 enum AIC3262_PLL_OPTION aic3262_pllclkin_option;
557 u8 dac_clkin_option;
558 u8 adc_clkin_option;
559 int irq;
560 u8 dac_reg;
561 u8 adc_gain;
562 u8 hpl;
563 u8 hpr;
564 u8 rec_amp;
565 u8 rampr;
566 u8 spk_amp;
567 struct spi_device *spi;
568 struct snd_soc_jack *headset_jack;
569 struct input_dev *button_dev;
570 int codec_audio_mode;
571#if defined(LOCAL_REG_ACCESS)
572 void *control_data;
573#endif
574};
575
576/*
577 *----------------------------------------------------------------------------
578 * @struct aic3262_configs |
579 * AIC3262 initialization data which has register offset and register
580 * value.
581 * @field u8 | book_no |
582 * AIC3262 Book Number Offsets required for initialization..
583 * @field u16 | reg_offset |
584 * AIC3262 Register offsets required for initialization..
585 * @field u8 | reg_val |
586 * value to set the AIC3262 register to initialize the AIC3262.
587 *----------------------------------------------------------------------------
588 */
589struct aic3262_configs {
590 u8 book_no;
591 u16 reg_offset;
592 u8 reg_val;
593};
594
595/*
596 *----------------------------------------------------------------------------
597 * @struct aic3262_rate_divs |
598 * Setting up the values to get different freqencies
599 * @field u32 | mclk |
600 * Master clock
601 * @field u32 | rate |
602 * sample rate
603 * @field u8 | p_val |
604 * value of p in PLL
605 * @field u32 | pll_j |
606 * value for pll_j
607 * @field u32 | pll_d |
608 * value for pll_d
609 * @field u32 | dosr |
610 * value to store dosr
611 * @field u32 | ndac |
612 * value for ndac
613 * @field u32 | mdac |
614 * value for mdac
615 * @field u32 | aosr |
616 * value for aosr
617 * @field u32 | nadc |
618 * value for nadc
619 * @field u32 | madc |
620 * value for madc
621 * @field u32 | blck_N |
622 * value for block N
623 * @field u32 | aic3262_configs |
624 * configurations for aic3262 register value
625 *----------------------------------------------------------------------------
626 */
627struct aic3262_rate_divs {
628 u32 mclk;
629 u32 rate;
630 u8 p_val;
631 u8 pll_j;
632 u16 pll_d;
633 u16 dosr;
634 u8 ndac;
635 u8 mdac;
636 u8 aosr;
637 u8 nadc;
638 u8 madc;
639 u8 blck_N;
640 struct aic3262_configs codec_specific_regs[NO_FEATURE_REGS];
641};
642
643/*
644*****************************************************************************
645* EXTERN DECLARATIONS
646*****************************************************************************
647*/
648/*
649 *----------------------------------------------------------------------------
650 * @func aic326x_headset_detect
651 * This function help to setup the needed registers to
652 * enable the headset detection
653 *
654 */
655extern int aic326x_headset_detect(struct snd_soc_codec *codec,
656 struct snd_soc_jack *jack, int jack_type);
657extern int aic326x_headset_button_init(struct snd_soc_codec *codec,
658 struct snd_soc_jack *jack, int jack_type);
659
660extern u8 aic3262_read(struct snd_soc_codec *codec, u16 reg);
661extern u16 aic3262_read_2byte(struct snd_soc_codec *codec, u16 reg);
662extern int aic3262_reset_cache(struct snd_soc_codec *codec);
663extern int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page);
664extern int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value);
665extern void aic3262_write_reg_cache(struct snd_soc_codec *codec,
666 u16 reg, u8 value);
667extern int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book);
668extern int reg_def_conf(struct snd_soc_codec *codec);
669extern int i2c_verify_book0(struct snd_soc_codec *codec);
670extern int poll_dac(struct snd_soc_codec *codec, int left_right, int on_off);
671extern int poll_adc(struct snd_soc_codec *codec, int left_right, int on_off);
672
673#ifdef CONFIG_MINI_DSP
674extern int aic3262_minidsp_program(struct snd_soc_codec *codec);
675extern int aic3262_add_minidsp_controls(struct snd_soc_codec *codec);
676#endif
677
678
679#ifdef MULTIBYTE_CONFIG_SUPPORT
680extern int aic3262_add_multiconfig_controls(struct snd_soc_codec *codec);
681#endif
682
683#endif /* _TLV320AIC3262_H */
684
diff --git a/sound/soc/codecs/tlv320aic326x_mini-dsp.c b/sound/soc/codecs/tlv320aic326x_mini-dsp.c
new file mode 100644
index 00000000000..6d55abb4dac
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_mini-dsp.c
@@ -0,0 +1,1796 @@
1/*
2 * linux/sound/soc/codecs/tlv320aic326x_mini-dsp.c
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
15 * codec with digital microphone inputs and programmable outputs.
16 *
17 * History:
18 *
19 * Rev 0.1 Added the miniDSP Support 01-03-2011
20 *
21 * Rev 0.2 Updated the code-base for miniDSP switching and
22 * mux control update. 21-03-2011
23 *
24 * Rev 0.3 Updated the code-base to support Multi-Configuration feature
25 * of PPS GDE
26 */
27
28/*
29 *****************************************************************************
30 * INCLUDES
31 *****************************************************************************
32 */
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/fs.h>
38#include <linux/types.h>
39#include <linux/kdev_t.h>
40#include <linux/cdev.h>
41#include <linux/device.h>
42#include <linux/io.h>
43#include <linux/delay.h>
44#include <linux/i2c.h>
45#include <linux/platform_device.h>
46#include <sound/soc.h>
47#include <sound/core.h>
48#include <sound/soc-dapm.h>
49#include <sound/control.h>
50#include <linux/time.h> /* For timing computations */
51#include "tlv320aic326x.h"
52#include "tlv320aic326x_mini-dsp.h"
53
54#include "base_main_Rate48_pps_driver.h"
55#include "second_rate_pps_driver.h"
56//#include "one_mic_aec_nc_latest.h"
57#ifdef CONFIG_MINI_DSP
58
59#ifdef REG_DUMP_MINIDSP
60static void aic3262_dump_page(struct i2c_client *i2c, u8 page);
61#endif
62
63/*
64 *****************************************************************************
65 * LOCAL STATIC DECLARATIONS
66 *****************************************************************************
67 */
68static int m_control_info(struct snd_kcontrol *kcontrol,
69 struct snd_ctl_elem_info *uinfo);
70static int m_control_get(struct snd_kcontrol *kcontrol,
71 struct snd_ctl_elem_value *ucontrol);
72static int m_control_put(struct snd_kcontrol *kcontrol,
73 struct snd_ctl_elem_value *ucontrol);
74
75/*
76 *****************************************************************************
77 * MINIDSP RELATED GLOBALS
78 *****************************************************************************
79 */
80/* The below variable is used to maintain the I2C Transactions
81 * to be carried out during miniDSP switching.
82 */
83 #if 1
84minidsp_parser_data dsp_parse_data[MINIDSP_PARSER_ARRAY_SIZE*2];
85
86struct i2c_msg i2c_transaction[MINIDSP_PARSER_ARRAY_SIZE * 2];
87/* Total count of I2C Messages are stored in the i2c_count */
88int i2c_count;
89
90/* The below array is used to store the burst array for I2C Multibyte
91 * Operations
92 */
93minidsp_i2c_page i2c_page_array[MINIDSP_PARSER_ARRAY_SIZE];
94int i2c_page_count;
95#else
96minidsp_parser_data dsp_parse_data;
97
98struct i2c_msg i2c_transaction;
99/* Total count of I2C Messages are stored in the i2c_count */
100int i2c_count;
101
102/* The below array is used to store the burst array for I2C Multibyte
103 * Operations
104 */
105minidsp_i2c_page i2c_page_array;
106int i2c_page_count;
107#endif
108
109/* kcontrol structure used to register with ALSA Core layer */
110static struct snd_kcontrol_new snd_mux_controls[MAX_MUX_CONTROLS];
111
112/* mode variables */
113static int amode;
114static int dmode;
115
116/* k-control macros used for miniDSP related Kcontrols */
117#define SOC_SINGLE_VALUE_M(xmax, xinvert) \
118 ((unsigned long)&(struct soc_mixer_control) \
119 {.max = xmax, \
120 .invert = xinvert})
121#define SOC_SINGLE_M(xname, max, invert) \
122{\
123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
124 .info = m_control_info, .get = m_control_get,\
125 .put = m_control_put, \
126 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
127 .private_value = SOC_SINGLE_VALUE_M(max, invert) }
128#define SOC_SINGLE_AIC3262_M(xname) \
129{\
130 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
131 .info = m_control_info, .get = m_control_get,\
132 .put = m_control_put, \
133 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
134}
135
136/*
137 * aic3262_minidsp_controls
138 *
139 * Contains the list of the Kcontrol macros required for modifying the
140 * miniDSP behavior at run-time.
141 */
142static const struct snd_kcontrol_new aic3262_minidsp_controls[] = {
143 SOC_SINGLE_AIC3262_M("Minidsp mode") ,
144 SOC_SINGLE_AIC3262_M("ADC Adaptive mode Enable") ,
145 SOC_SINGLE_AIC3262_M("DAC Adaptive mode Enable") ,
146 SOC_SINGLE_AIC3262_M("Dump Regs Book0") ,
147 SOC_SINGLE_AIC3262_M("Verify minidsp program") ,
148};
149
150#ifdef REG_DUMP_MINIDSP
151/*
152 *----------------------------------------------------------------------------
153 * Function : aic3262_dump_page
154 * Purpose : Read and display one codec register page, for debugging purpose
155 *----------------------------------------------------------------------------
156 */
157static void aic3262_dump_page(struct i2c_client *i2c, u8 page)
158{
159 int i;
160 u8 data;
161 u8 test_page_array[256];
162
163 aic3262_change_page(codec, page);
164
165 data = 0x0;
166
167 i2c_master_send(i2c, data, 1);
168 i2c_master_recv(i2c, test_page_array, 128);
169
170 DBG("\n------- MINI_DSP PAGE %d DUMP --------\n", page);
171 for (i = 0; i < 128; i++)
172 DBG(KERN_INFO " [ %d ] = 0x%x\n", i, test_page_array[i]);
173
174}
175#endif
176
177/*
178 *----------------------------------------------------------------------------
179 * Function : update_kcontrols
180 * Purpose : Given the miniDSP process flow, this function reads the
181 * corresponding Page Numbers and then performs I2C Read for those
182 * Pages.
183 *----------------------------------------------------------------------------
184 */
185void update_kcontrols(struct snd_soc_codec *codec, int process_flow)
186{
187 int i, val1, array_size;
188 char **knames;
189 control *cntl;
190
191#if 0
192 if (process_flow == 1) {
193 knames = Second_Rate_MUX_control_names;
194 cntl = Second_Rate_MUX_controls;
195 array_size = ARRAY_SIZE(Second_Rate_MUX_controls);
196 } else {
197#endif
198 knames = main44_MUX_control_names;
199 cntl = main44_MUX_controls;
200 array_size = ARRAY_SIZE(main44_MUX_controls);
201// }
202
203 DBG(KERN_INFO "%s: ARRAY_SIZE = %d\tmode=%d\n", __func__,
204 array_size, process_flow);
205 for (i = 0; i < array_size; i++) {
206 aic3262_change_book(codec, cntl[i].control_book);
207 aic3262_change_page(codec, cntl[i].control_page);
208 val1 = i2c_smbus_read_byte_data(codec->control_data,
209 cntl[i].control_base);
210 snd_mux_controls[i].private_value = 0;
211 }
212}
213
214/*
215 *----------------------------------------------------------------------------
216 * Function : byte_i2c_array_transfer
217 * Purpose : Function used only for debugging purpose. This function will
218 * be used while switching miniDSP Modes register by register.
219 * This needs to be used only during development.
220 *-----------------------------------------------------------------------------
221 */
222 #if 1
223int byte_i2c_array_transfer(struct snd_soc_codec *codec,
224 reg_value *program_ptr,
225 int size)
226{
227 int j;
228 u8 buf[3];
229
230 for (j = 0; j < size; j++) {
231 /* Check if current Reg offset is zero */
232 if (program_ptr[j].reg_off == 0) {
233 /* Check for the Book Change Request */
234 if ((j < (size - 1)) &&
235 (program_ptr[j+1].reg_off == 127)) {
236 aic3262_change_book(codec,
237 program_ptr[j+1].reg_val);
238 /* Increment for loop counter across Book Change */
239 j++;
240 continue;
241 }
242 /* Check for the Page Change Request in Current book */
243 aic3262_change_page(codec, program_ptr[j].reg_val);
244 continue;
245 }
246
247 buf[AIC3262_REG_OFFSET_INDEX] = program_ptr[j].reg_off % 128;
248 buf[AIC3262_REG_DATA_INDEX] =
249 program_ptr[j].reg_val & AIC3262_8BITS_MASK;
250
251 if (codec->hw_write(codec->control_data, buf, 2) != 2) {
252 printk(KERN_ERR "Error in i2c write\n");
253 return -EIO;
254 }
255 }
256 aic3262_change_book(codec, 0);
257 return 0;
258}
259
260#else
261int byte_i2c_array_transfer(struct snd_soc_codec *codec,
262 reg_value *program_ptr,
263 int size)
264{
265 int j;
266 u8 buf[3];
267 printk(KERN_INFO "%s: started with array size %d\n", __func__, size);
268 for (j = 0; j < size; j++) {
269 /* Check if current Reg offset is zero */
270 buf[AIC3262_REG_OFFSET_INDEX] = program_ptr[j].reg_off % 128;
271 buf[AIC3262_REG_DATA_INDEX] =
272 program_ptr[j].reg_val & AIC3262_8BITS_MASK;
273
274 if (codec->hw_write(codec->control_data, buf, 2) != 2) {
275 printk(KERN_ERR "Error in i2c write\n");
276 return -EIO;
277 }
278 }
279 printk(KERN_INFO "%s: ended\n", __func__);
280 return 0;
281}
282#endif
283/*
284 *----------------------------------------------------------------------------
285 * Function : byte_i2c_array_read
286 * Purpose : This function is used to perform Byte I2C Read. This is used
287 * only for debugging purposes to read back the Codec Page
288 * Registers after miniDSP Configuration.
289 *----------------------------------------------------------------------------
290 */
291int byte_i2c_array_read(struct snd_soc_codec *codec,
292 reg_value *program_ptr, int size)
293{
294 int j;
295 u8 val1;
296 u8 cur_page = 0;
297 u8 cur_book = 0;
298 for (j = 0; j < size; j++) {
299 /* Check if current Reg offset is zero */
300 if (program_ptr[j].reg_off == 0) {
301 /* Check for the Book Change Request */
302 if ((j < (size - 1)) &&
303 (program_ptr[j+1].reg_off == 127)) {
304 aic3262_change_book(codec,
305 program_ptr[j+1].reg_val);
306 cur_book = program_ptr[j+1].reg_val;
307 /* Increment for loop counter across Book Change */
308 j++;
309 continue;
310 }
311 /* Check for the Page Change Request in Current book */
312 aic3262_change_page(codec, program_ptr[j].reg_val);
313 cur_page = program_ptr[j].reg_val;
314 continue;
315 }
316
317 val1 = i2c_smbus_read_byte_data(codec->control_data,
318 program_ptr[j].reg_off);
319 if (val1 < 0)
320 printk(KERN_ERR "Error in smbus read\n");
321
322 if(val1 != program_ptr[j].reg_val)
323 /*printk(KERN_INFO "mismatch [%d][%d][%d] = %x %x\n",
324 cur_book, cur_page, program_ptr[j].reg_off, val1, program_ptr[j].reg_val);*/
325 DBG(KERN_INFO "[%d][%d][%d]= %x\n",
326 cur_book, cur_page, program_ptr[j].reg_off, val1);
327 }
328 aic3262_change_book(codec, 0);
329 return 0;
330}
331
332/*
333 *----------------------------------------------------------------------------
334 * Function : minidsp_get_burst
335 * Purpose : Format one I2C burst for transfer from mini dsp program array.
336 * This function will parse the program array and get next burst
337 * data for doing an I2C bulk transfer.
338 *----------------------------------------------------------------------------
339 */
340static void
341minidsp_get_burst(reg_value *program_ptr,
342 int program_size,
343 minidsp_parser_data *parse_data)
344{
345 int index = parse_data->current_loc;
346 int burst_write_count = 0;
347
348 /*DBG("GET_BURST: start\n");*/
349 /* check if first location is page register, and populate page addr */
350 if (program_ptr[index].reg_off == 0) {
351 if ((index < (program_size - 1)) &&
352 (program_ptr[index+1].reg_off == 127)) {
353 parse_data->book_change = 1;
354 parse_data->book_no = program_ptr[index+1].reg_val;
355 index += 2;
356 goto finish_out;
357
358 }
359 parse_data->page_num = program_ptr[index].reg_val;
360 parse_data->burst_array[burst_write_count++] =
361 program_ptr[index].reg_off;
362 parse_data->burst_array[burst_write_count++] =
363 program_ptr[index].reg_val;
364 index++;
365 goto finish_out;
366 }
367
368 parse_data->burst_array[burst_write_count++] =
369 program_ptr[index].reg_off;
370 parse_data->burst_array[burst_write_count++] =
371 program_ptr[index].reg_val;
372 index++;
373
374 for (; index < program_size; index++) {
375 if (program_ptr[index].reg_off !=
376 (program_ptr[index - 1].reg_off + 1))
377 break;
378 else
379 parse_data->burst_array[burst_write_count++] =
380 program_ptr[index].reg_val;
381
382 }
383finish_out:
384 parse_data->burst_size = burst_write_count;
385 if (index == program_size)
386 /* parsing completed */
387 parse_data->current_loc = MINIDSP_PARSING_END;
388 else
389 parse_data->current_loc = index;
390 /*DBG("GET_BURST: end\n");*/
391}
392/*
393 *----------------------------------------------------------------------------
394 * Function : minidsp_i2c_multibyte_transfer
395 * Purpose : Function used to perform multi-byte I2C Writes. Used to configure
396 * the miniDSP Pages.
397 *----------------------------------------------------------------------------
398 */
399 #if 1
400int
401minidsp_i2c_multibyte_transfer(struct snd_soc_codec *codec,
402 reg_value *program_ptr,
403 int program_size)
404{
405 struct i2c_client *client = codec->control_data;
406
407 minidsp_parser_data parse_data;
408 int count = 0;
409
410#ifdef DEBUG_MINIDSP_LOADING
411 int i = 0, j = 0;
412#endif
413 /* point the current location to start of program array */
414 parse_data.current_loc = 0;
415 parse_data.page_num = 0;
416 parse_data.book_change = 0;
417 parse_data.book_no = 0;
418
419 DBG(KERN_INFO "size is : %d", program_size);
420 do {
421 do {
422 /* Get first burst data */
423 minidsp_get_burst(program_ptr, program_size,
424 &parse_data);
425 if (parse_data.book_change == 1)
426 break;
427 dsp_parse_data[count] = parse_data;
428
429 i2c_transaction[count].addr = client->addr;
430 i2c_transaction[count].flags =
431 client->flags & I2C_M_TEN;
432 i2c_transaction[count].len =
433 dsp_parse_data[count].burst_size;
434 i2c_transaction[count].buf =
435 dsp_parse_data[count].burst_array;
436
437#ifdef DEBUG_MINIDSP_LOADING
438 DBG(KERN_INFO
439 "i: %d\taddr: %d\tflags: %d\tlen: %d\tbuf:",
440 i, client->addr, client->flags & I2C_M_TEN,
441 dsp_parse_data[count].burst_size);
442
443 for (j = 0; j <= dsp_parse_data[count].burst_size; j++)
444 DBG(KERN_INFO "%x ",
445 dsp_parse_data[i].burst_array[j]);
446
447 DBG(KERN_INFO "\n\n");
448 i++;
449#endif
450
451 count++;
452 /* Proceed to the next burst reg_addr_incruence */
453 } while (parse_data.current_loc != MINIDSP_PARSING_END);
454
455 if (count > 0) {
456 if (i2c_transfer(client->adapter,
457 i2c_transaction, count) != count) {
458 printk(KERN_ERR "Write burst i2c data error!\n");
459 }
460 }
461 if (parse_data.book_change == 1) {
462 aic3262_change_book(codec, parse_data.book_no);
463 parse_data.book_change = 0;
464 }
465 } while (parse_data.current_loc != MINIDSP_PARSING_END);
466 aic3262_change_book(codec, 0);
467 return 0;
468}
469#else
470int
471minidsp_i2c_multibyte_transfer(struct snd_soc_codec *codec,
472 reg_value *program_ptr,
473 int program_size)
474{
475 struct i2c_client *client = codec->control_data;
476
477 minidsp_parser_data parse_data;
478 int count = 1;
479
480#ifdef DEBUG_MINIDSP_LOADING
481 int i = 0, j = 0;
482#endif
483 /* point the current location to start of program array */
484 parse_data.current_loc = 0;
485 parse_data.page_num = 0;
486 parse_data.book_change = 0;
487 parse_data.book_no = 0;
488
489 DBG(KERN_INFO "size is : %d", program_size);
490
491 do {
492 /* Get first burst data */
493 minidsp_get_burst(program_ptr, program_size,
494 &parse_data);
495
496 dsp_parse_data = parse_data;
497
498 i2c_transaction.addr = client->addr;
499 i2c_transaction.flags =
500 client->flags & I2C_M_TEN;
501 i2c_transaction.len =
502 dsp_parse_data.burst_size;
503 i2c_transaction.buf =
504 dsp_parse_data.burst_array;
505
506#ifdef DEBUG_MINIDSP_LOADING
507 DBG(KERN_INFO
508 "i: %d\taddr: %d\tflags: %d\tlen: %d\tbuf:",
509 i, client->addr, client->flags & I2C_M_TEN,
510 dsp_parse_data.burst_size);
511
512 for (j = 0; j <= dsp_parse_data.burst_size; j++)
513 printk( "%x ",
514 dsp_parse_data.burst_array[j]);
515
516 DBG(KERN_INFO "\n\n");
517 i++;
518#endif
519
520 if (i2c_transfer(client->adapter,
521 &i2c_transaction, count) != count) {
522 printk(KERN_ERR "Write burst i2c data error!\n");
523 }
524 if (parse_data.book_change == 1) {
525 aic3262_change_book(codec, parse_data.book_no);
526 parse_data.book_change = 0;
527 }
528 /* Proceed to the next burst reg_addr_incruence */
529 } while (parse_data.current_loc != MINIDSP_PARSING_END);
530
531 return 0;
532}
533#endif
534/*
535* Process_Flow Structure
536* Structure used to maintain the mapping of each PFW like the miniDSP_A
537* miniDSP_D array values and sizes. It also contains information about
538* the patches required for each patch.
539*/
540struct process_flow{
541 int init_size;
542 reg_value *miniDSP_init;
543 int A_size;
544 reg_value *miniDSP_A_values;
545 int D_size;
546 reg_value *miniDSP_D_values;
547 int post_size;
548 reg_value *miniDSP_post;
549 struct minidsp_config {
550 int a_patch_size;
551 reg_value *a_patch;
552 int d_patch_size;
553 reg_value *d_patch;
554 } configs[MAXCONFIG];
555
556} miniDSP_programs[] = {
557 {
558 ARRAY_SIZE(main44_REG_Section_init_program), main44_REG_Section_init_program,
559 ARRAY_SIZE(main44_miniDSP_A_reg_values),main44_miniDSP_A_reg_values,
560 ARRAY_SIZE(main44_miniDSP_D_reg_values),main44_miniDSP_D_reg_values,
561 ARRAY_SIZE(main44_REG_Section_post_program),main44_REG_Section_post_program,
562 {
563
564 { 0, 0, 0, 0},
565 { 0, 0, 0, 0},
566 { 0, 0, 0, 0},
567 { 0, 0, 0, 0},
568
569
570 },
571},
572 {
573 ARRAY_SIZE(base_speaker_SRS_REG_init_Section_program),base_speaker_SRS_REG_init_Section_program,
574 ARRAY_SIZE(base_speaker_SRS_miniDSP_A_reg_values),base_speaker_SRS_miniDSP_A_reg_values,
575 ARRAY_SIZE(base_speaker_SRS_miniDSP_D_reg_values),base_speaker_SRS_miniDSP_D_reg_values,
576 ARRAY_SIZE(base_speaker_SRS_REG_post_Section_program),base_speaker_SRS_REG_post_Section_program,
577
578 {
579 {0, 0, ARRAY_SIZE(SRS_ON_miniDSP_D_reg_values), SRS_ON_miniDSP_D_reg_values},
580 {0, 0, ARRAY_SIZE(SRS_OFF_miniDSP_D_reg_values),SRS_OFF_miniDSP_D_reg_values},
581 {0, 0, 0, 0},
582 {0, 0, 0, 0},
583 },
584},
585#if 0
586 {ARRAY_SIZE(spkr_srs_REG_Section_init_program),spkr_srs_REG_Section_init_program,
587 ARRAY_SIZE(spkr_srs_miniDSP_A_reg_values),spkr_srs_miniDSP_A_reg_values,
588 ARRAY_SIZE(spkr_srs_miniDSP_D_reg_values),spkr_srs_miniDSP_D_reg_values,
589 ARRAY_SIZE(spkr_srs_REG_Section_post_program),spkr_srs_REG_Section_post_program,
590 {
591 { 0, 0, 0, 0},
592 { 0, 0, 0, 0},
593 { 0, 0, 0, 0},
594 { 0, 0, 0, 0},
595
596 },
597},
598#endif
599};
600
601int
602set_minidsp_mode(struct snd_soc_codec *codec, int new_mode, int new_config)
603{
604
605 if (codec == NULL) {
606 printk(KERN_INFO "%s codec is NULL\n",__func__);
607 }
608 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
609 struct snd_soc_dapm_context *dapm = &codec->dapm;
610 struct process_flow * pflows = &miniDSP_programs[new_mode];
611 u8 reg63, reg81, pll_pow, ndac_pow, mdac_pow, nadc_pow, madc_pow;
612
613 u8 adc_status,dac_status;
614 u8 reg, val;
615 u8 shift;
616 volatile u16 counter;
617
618 int (*ptransfer)(struct snd_soc_codec *codec,
619 reg_value *program_ptr,
620 int size);
621
622 printk("%s:New Switch mode = %d New Config= %d\n", __func__, new_mode,new_config);
623 if (new_mode >= ARRAY_SIZE(miniDSP_programs))
624 return 0; // error condition
625 if (new_config > MAXCONFIG)
626 return 0;
627#ifndef MULTIBYTE_I2C
628 ptransfer = byte_i2c_array_transfer;
629#else
630 ptransfer = minidsp_i2c_multibyte_transfer;
631#endif
632 if (new_mode != aic326x->process_flow) {
633
634 printk("== From PFW %d to PFW %d==\n", aic326x->process_flow , new_mode);
635
636 /* Change to book 0 page 0 and turn off the DAC and snd_soc_dapm_disable_piADC,
637 * while turning them down, poll for the power down completion.
638 */
639 aic3262_change_page(codec, 0);
640 aic3262_change_book(codec, 0);
641
642#if 0
643 reg63 = aic3262_read(codec, PASI_DAC_DP_SETUP);
644 aic3262_write(codec, PASI_DAC_DP_SETUP, (reg63 & ~0xC0));/*dac power down*/
645 mdelay (5);
646 counter = 0;
647 reg = DAC_FLAG_R1;
648
649 dac_status = aic3262_read(codec, reg);
650
651 do {
652 dac_status = snd_soc_read(codec, reg);
653 counter++;struct snd_soc_dapm_context *dapm
654 mdelay(5);
655 } while ((counter < 200) && ((dac_status & 0x88) == 1));
656 printk (KERN_INFO "#%s: Polled Register %d Bits set 0x%X counter %d\n",
657 __func__, reg, dac_status, counter);snd_soc_dapm_disable_pi
658 struct snd_soc_dapm_context *dapm
659 reg81= aic3262_read(codec, ADC_CHANNEL_POW);
660 aic3262_write(codec, ADC_CHANNEL_POW, (reg81 & ~0xC0));/*adc power down*/
661 mdelay (5);
662
663 adc_status=aic3262_read(codec,ADC_FLAG_R1);
664 counter = 0;
665 reg = ADC_FLAG_R1;
666 do {
667 adc_status = snd_soc_read(codec, reg);
668 counter++;
669 mdelay(5);
670 } while ((counter < 200) && ((adc_status & 0x44) == 1));
671
672 printk (KERN_INFO "#%s: Polled Register %d Bits set 0x%X counter %d\n",
673 __func__, reg, adc_status, counter);
674
675 dac_status = snd_soc_read(codec, DAC_FLAG_R1);
676 adc_status = snd_soc_read (codec, ADC_FLAG_R1);
677
678 printk (KERN_INFO "#%s: Initial DAC_STATUS 0x%x ADC_STATUS 0x%X\n",
679 __func__, dac_status, adc_status);
680
681#endif
682 /* Instead of hard-coding the switching off DAC and ADC, we will use the DAPM
683 * to switch off the Playback Paths and the ADC
684 */
685 snd_soc_dapm_disable_pin( dapm, "Headphone Jack");
686 snd_soc_dapm_disable_pin( dapm, "EarPiece");
687 snd_soc_dapm_disable_pin( dapm, "Int Spk");
688 snd_soc_dapm_disable_pin( dapm, "SPK out");
689 snd_soc_dapm_disable_pin( dapm, "Line Out");
690
691 snd_soc_dapm_disable_pin( dapm, "Mic Jack");
692 snd_soc_dapm_disable_pin( dapm, "Linein");
693 snd_soc_dapm_disable_pin( dapm, "Int Mic");
694
695 //snd_soc_dapm_disable_pin (codec, "Left DAC");
696 //snd_soc_dapm_disable_pin (codec, "Right DAC");
697 //snd_soc_dapm_disable_pin (codec, "Left ADC");
698 //snd_soc_dapm_disable_pin (codec, "Right ADC");
699 snd_soc_dapm_sync(dapm);
700 mdelay(10);
701
702 mdac_pow = aic3262_read(codec, MDAC_DIV_POW_REG);
703 aic3262_write(codec, MDAC_DIV_POW_REG, (mdac_pow & ~0x80));/*mdac power down*/
704 mdelay(5);
705 nadc_pow = aic3262_read(codec, MADC_DIV_POW_REG);
706 aic3262_write(codec, MADC_DIV_POW_REG, (nadc_pow & ~0x80));/*madc power down*/
707 mdelay(5);
708 pll_pow = aic3262_read(codec, PLL_PR_POW_REG);
709 aic3262_write(codec, PLL_PR_POW_REG, (pll_pow & ~0x80));/*pll power down*/
710 mdelay(5);
711 ndac_pow = aic3262_read(codec, NDAC_DIV_POW_REG);
712 aic3262_write(codec, NDAC_DIV_POW_REG, (ndac_pow & ~0x80)); /*ndac power down*/
713 mdelay(5);
714
715 dac_status = snd_soc_read(codec, DAC_FLAG_R1);
716 adc_status = snd_soc_read (codec, ADC_FLAG_R1);
717
718 printk (KERN_INFO "#%s: Before Switching DAC_STATUS 0x%x ADC_STATUS 0x%X\n",
719 __func__, dac_status, adc_status);
720
721 mdelay (10);
722 ptransfer(codec, pflows->miniDSP_init, pflows->init_size);
723 ptransfer(codec, pflows->miniDSP_A_values, pflows->A_size);
724 ptransfer(codec, pflows->miniDSP_D_values, pflows->D_size);
725 ptransfer(codec, pflows->miniDSP_post, pflows->post_size);
726
727
728 aic326x->process_flow = new_mode;
729
730 aic3262_change_page(codec, 0);
731 aic3262_change_book(codec, 0);
732#if 0
733
734 /* After the miniDSP Programming is completed, power up the DAC and ADC
735 * and poll for its power up operation.
736 */
737
738 aic3262_write(codec, PASI_DAC_DP_SETUP, reg63);/*reverting the old DAC values */
739 mdelay(5);
740
741 /* Poll for DAC Power-up first */
742 /* For DAC Power-up and Power-down event, we will poll for
743 * Book0 Page0 Register 37
744 */
745 reg = DAC_FLAG_R1;
746 counter = 0;
747 do {
748 dac_status = snd_soc_read(codec, reg);
749 counter++;
750 mdelay(5);
751 } while ((counter < 200) && ((dac_status & 0x88) == 0));
752
753 printk (KERN_INFO "#%s: Polled Register %d Bits set 0x%X counter %d\n",
754 __func__, reg, dac_status, counter);
755
756 aic3262_write(codec, ADC_CHANNEL_POW, reg81);/*reverting the old ADC values*/
757 mdelay (5);
758 /* For ADC Power-up and Power-down event, we will poll for
759 * Book0 Page0 Register 36
760 */
761 reg = ADC_FLAG_R1;
762 counter = 0;
763 do {
764 adc_status = snd_soc_read(codec, reg);
765 counter++;
766 mdelay(5);
767 } while ((counter < 200) && ((adc_status & 0x44) == 0));
768
769 printk (KERN_INFO "#%s: Polled Register %d Bits set 0x%X counter %d\n",
770 __func__, reg, adc_status, counter);
771 aic3262_write(codec, PLL_PR_POW_REG, pll_pow);/*reverting the old pll values*/
772 mdelay(10);
773
774 aic3262_write(codec, MDAC_DIV_POW_REG, mdac_pow);/*reverting the old mdac values*/
775 mdelay(5);
776 aic3262_write(codec, MADC_DIV_POW_REG, madc_pow);/*reverting the old madc values*/
777 mdelay(5);
778 aic3262_write(codec, NDAC_DIV_POW_REG, ndac_pow);/*reverting the old ndac values*/
779 mdelay(5);
780
781 /*if (new_config == 0) {
782 aic326x->current_config = 0;
783 return 0;
784 }
785 aic326x->current_config = -1;*/
786
787 //aic3262_change_book(codec, 0);
788 //aic3262_change_page(codec, 0);
789#endif
790 }
791
792#ifdef MULTICONFIG_SUPPORT
793 if (new_config < 0 )
794 return 0; // No configs supported in this pfw
795 if (new_config == aic326x->current_config)
796 return 0;
797 if (pflows->configs[new_config].a_patch_size || pflows->configs[new_config].d_patch_size)
798 minidsp_multiconfig(codec,
799 pflows->configs[new_config].a_patch, pflows->configs[new_config].a_patch_size,
800 pflows->configs[new_config].d_patch, pflows->configs[new_config].d_patch_size);
801#endif
802
803 aic326x->current_config = new_config;
804 aic3262_change_book( codec, 0);
805
806 DBG(KERN_INFO "%s: switch mode finished\n", __func__);
807 return 0;
808}
809
810/*
811 * i2c_verify
812 *
813 * Function used to validate the contents written into the miniDSP
814 * pages after miniDSP Configuration.
815*/
816int i2c_verify(struct snd_soc_codec *codec)
817{
818
819 DBG(KERN_INFO "#%s: Invoked.. Resetting to page 0\n", __func__);
820
821 aic3262_change_book(codec, 0);
822 DBG(KERN_INFO "#Reading reg_section_init_program\n");
823
824 byte_i2c_array_read(codec, main44_REG_Section_init_program,
825 ARRAY_SIZE(main44_REG_Section_init_program));
826
827 DBG(KERN_INFO "#Reading minidsp_A_reg_values\n");
828 byte_i2c_array_read(codec, main44_miniDSP_A_reg_values,
829 (main44_miniDSP_A_reg_values_COEFF_SIZE +
830 main44_miniDSP_A_reg_values_INST_SIZE));
831
832 DBG(KERN_INFO "#Reading minidsp_D_reg_values\n");
833 byte_i2c_array_read(codec, main44_miniDSP_D_reg_values,
834 (main44_miniDSP_D_reg_values_COEFF_SIZE +
835 main44_miniDSP_D_reg_values_INST_SIZE));
836
837 DBG(KERN_INFO "#Reading reg_section_post_program\n");
838 byte_i2c_array_read(codec, main44_REG_Section_post_program,
839 ARRAY_SIZE(main44_REG_Section_post_program));
840
841 aic3262_change_book(codec, 0);
842
843 DBG(KERN_INFO "i2c_verify completed\n");
844 return 0;
845}
846
847
848int change_codec_power_status(struct snd_soc_codec * codec, int off_restore, int power_mask)
849{
850 int minidsp_power_mask;
851 u8 dac_status;
852 u8 adc_status;
853
854 minidsp_power_mask = 0;
855
856 aic3262_change_page (codec, 0);
857 aic3262_change_book (codec, 0);
858
859
860 switch (off_restore) {
861
862 case 0: /* Power-off the Codec */
863 dac_status = snd_soc_read (codec, DAC_FLAG_R1);
864
865 if(dac_status & 0x88) {
866 minidsp_power_mask |= 0x1;
867 snd_soc_update_bits(codec, PASI_DAC_DP_SETUP, 0xC0, 0x0);
868
869 poll_dac(codec, 0x0, 0x0);
870 poll_dac(codec, 0x1, 0x0);
871 }
872
873 adc_status = snd_soc_read (codec, ADC_FLAG_R1);
874
875 if(adc_status & 0x44) {
876 minidsp_power_mask |= 0x2;
877 snd_soc_update_bits(codec, ADC_CHANNEL_POW, 0xC0, 0x0);
878
879 poll_adc(codec, 0x0, 0x0);
880 poll_adc(codec, 0x1, 0x0);
881 }
882 break;
883 case 1: /* For Restoring Codec to Previous Power State */
884
885 if(power_mask & 0x1) {
886
887 snd_soc_update_bits(codec, PASI_DAC_DP_SETUP, 0xC0, 0xC0);
888
889 poll_dac(codec, 0x0, 0x1);
890 poll_dac(codec, 0x1, 0x1);
891 }
892
893 if(power_mask & 0x2) {
894
895 snd_soc_update_bits(codec, ADC_CHANNEL_POW, 0xC0, 0xC0);
896
897 poll_adc(codec, 0x0, 0x1);
898 poll_adc(codec, 0x1, 0x1);
899 }
900 break;
901 default:
902 printk(KERN_ERR "#%s: Unknown Power State Requested..\n",
903 __func__);
904 }
905
906 return minidsp_power_mask;
907
908}
909
910/*
911 *----------------------------------------------------------------------------
912 * Function : boot_minidsp
913 * Purpose : for laoding the default minidsp mode for the first time .
914 *----------------------------------------------------------------------------
915 */
916int
917boot_minidsp(struct snd_soc_codec *codec, int new_mode)
918{
919 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
920 struct process_flow * pflows = &miniDSP_programs[new_mode];
921 int minidsp_stat;
922
923 int (*ptransfer)(struct snd_soc_codec *codec,
924 reg_value *program_ptr,
925 int size);
926
927 DBG("%s: switch mode start\n", __func__);
928 if (new_mode >= ARRAY_SIZE(miniDSP_programs))
929 return 0; // error condition
930 if (new_mode == aic326x->process_flow)
931 return 0;
932
933
934#ifndef MULTIBYTE_I2C
935 ptransfer = byte_i2c_array_transfer;
936#else
937 ptransfer = minidsp_i2c_multibyte_transfer;
938#endif
939
940 minidsp_stat = change_codec_power_status (codec, 0x0, 0x3);
941
942 ptransfer(codec, pflows->miniDSP_init, pflows->init_size);
943 ptransfer(codec, pflows->miniDSP_A_values, pflows->A_size);
944 ptransfer(codec, pflows->miniDSP_D_values, pflows->D_size);
945 ptransfer(codec, pflows->miniDSP_post, pflows->post_size);
946
947 aic326x->process_flow = new_mode;
948
949 change_codec_power_status(codec, 1, minidsp_stat);
950
951 aic3262_change_page( codec,0);
952 aic3262_change_book( codec,0);
953
954 return 0;
955}
956
957/*
958 *----------------------------------------------------------------------------
959 * Function : aic3262_minidsp_program
960 * Purpose : Program mini dsp for AIC3262 codec chip. This routine is
961 * called from the aic3262 codec driver, if mini dsp programming
962 * is enabled.
963 *----------------------------------------------------------------------------
964 */
965int aic3262_minidsp_program(struct snd_soc_codec *codec)
966{
967 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
968 DBG(KERN_INFO "#AIC3262: programming mini dsp\n");
969
970#if defined(PROGRAM_MINI_DSP_first)
971 #ifdef DEBUG
972 DBG("#Verifying book 0\n");
973 i2c_verify_book0(codec);
974#endif
975 aic3262_change_book(codec, 0);
976 boot_minidsp(codec, 1);
977 aic326x->process_flow = 0;
978 aic3262_change_book(codec, 0);
979#ifdef DEBUG
980 DBG("#verifying book 0\n");
981 i2c_verify_book0(codec);
982#endif
983#endif
984#if defined(PROGRAM_MINI_DSP_second)
985#ifdef DEBUG
986 DBG("#Verifying book 0\n");
987 aic3262_change_book(codec, 0);
988#endif
989 boot_minidsp(codec, 0);
990 aic326x->process_flow = 1;
991#ifdef DEBUG
992 DBG("#verifying book 0\n");
993 aic3262_change_book(codec, 0);
994#endif
995#endif
996 return 0;
997}
998/*
999 *----------------------------------------------------------------------------
1000 * Function : m_control_info
1001 * Purpose : This function is to initialize data for new control required to
1002 * program the AIC3262 registers.
1003 *
1004 *----------------------------------------------------------------------------
1005 */
1006static int m_control_info(struct snd_kcontrol *kcontrol,
1007 struct snd_ctl_elem_info *uinfo)
1008{
1009 uinfo->count = 1;
1010 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1011 uinfo->value.integer.min = 0;
1012 uinfo->value.integer.max = 1;
1013 return 0;
1014}
1015
1016/*
1017 *----------------------------------------------------------------------------
1018 * Function : m_control_get
1019 * Purpose : This function is to read data of new control for
1020 * program the AIC3262 registers.
1021 *
1022 *----------------------------------------------------------------------------
1023 */
1024static int m_control_get(struct snd_kcontrol *kcontrol,
1025 struct snd_ctl_elem_value *ucontrol)
1026{
1027 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1028 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1029 u32 val;
1030 u8 val1;
1031
1032 if (!strcmp(kcontrol->id.name, "Minidsp mode")) {
1033 val = aic3262->process_flow;
1034 ucontrol->value.integer.value[0] = val;
1035 DBG(KERN_INFO "control get : mode=%d\n", aic3262->process_flow);
1036 }
1037 if (!strcmp(kcontrol->id.name, "DAC Adaptive mode Enable")) {
1038 aic3262_change_book(codec, 80);
1039 val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
1040 ucontrol->value.integer.value[0] = ((val1>>1)&0x01);
1041 DBG(KERN_INFO "control get : mode=%d\n", aic3262->process_flow);
1042 aic3262_change_book(codec,0);
1043 }
1044 if (!strcmp(kcontrol->id.name, "ADC Adaptive mode Enable")) {
1045 aic3262_change_book(codec, 40);
1046 val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
1047 ucontrol->value.integer.value[0] = ((val1>>1)&0x01);
1048 DBG(KERN_INFO "control get : mode=%d\n", dmode);
1049 aic3262_change_book(codec,0);
1050 }
1051
1052 return 0;
1053}
1054
1055/*
1056 *----------------------------------------------------------------------------
1057 * Function : m_new_control_put
1058 * Purpose : new_control_put is called to pass data from user/application to
1059 * the driver.
1060 *
1061 *----------------------------------------------------------------------------
1062 */
1063static int m_control_put(struct snd_kcontrol *kcontrol,
1064 struct snd_ctl_elem_value *ucontrol)
1065{
1066 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1067 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1068
1069 u32 val;
1070 u8 val1;
1071 int mode = aic3262->process_flow;
1072
1073 DBG("n_control_put\n");
1074 val = ucontrol->value.integer.value[0];
1075 if (!strcmp(kcontrol->id.name, "Minidsp mode")) {
1076 DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
1077 aic3262->process_flow, val);
1078 if (val != mode) {
1079 if (aic3262->mute_codec == 1) {
1080 i2c_verify_book0(codec);
1081 aic3262_change_book(codec, 0);
1082 boot_minidsp(codec, val);
1083
1084 aic3262_change_book(codec, 0);
1085 i2c_verify_book0(codec);
1086 /* update_kcontrols(codec, val);*/
1087 } else {
1088 printk(KERN_ERR
1089 " Cant Switch Processflows, Playback in progress");
1090 }
1091 }
1092 }
1093
1094 if (!strcmp(kcontrol->id.name, "DAC Adaptive mode Enable")) {
1095 DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
1096 aic3262->process_flow, val);
1097 if (val != amode) {
1098 aic3262_change_book(codec, 80);
1099 val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
1100 aic3262_write(codec, 1, (val1&0xfb)|(val<<1));
1101 aic3262_change_book(codec,0);
1102 }
1103 amode = val;
1104 }
1105
1106 if (!strcmp(kcontrol->id.name, "ADC Adaptive mode Enable")) {
1107 DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
1108 aic3262->process_flow, val);
1109 if (val != dmode) {
1110 aic3262_change_book(codec, 40);
1111 val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
1112 aic3262_write(codec, 1, (val1&0xfb)|(val<<1));
1113 aic3262_change_book(codec,0);
1114 }
1115 dmode = val;
1116 }
1117
1118 if (!strcmp(kcontrol->id.name, "Dump Regs Book0"))
1119 i2c_verify_book0(codec);
1120
1121#if 0
1122 if (!strcmp(kcontrol->id.name, "Verify minidsp program")) {
1123
1124 if (mode == 0) {
1125 DBG("Current mod=%d\nVerifying minidsp_D_regs", mode);
1126 byte_i2c_array_read(codec, main44_miniDSP_D_reg_values,
1127 (main44_miniDSP_D_reg_values_COEFF_SIZE +
1128 main44_miniDSP_D_reg_values_INST_SIZE));
1129 } else {
1130 byte_i2c_array_read(codec,
1131 Second_Rate_miniDSP_A_reg_values,
1132 (Second_Rate_miniDSP_A_reg_values_COEFF_SIZE +
1133 Second_Rate_miniDSP_A_reg_values_INST_SIZE));
1134 byte_i2c_array_read(codec,
1135 Second_Rate_miniDSP_D_reg_values,
1136 (Second_Rate_miniDSP_D_reg_values_COEFF_SIZE +
1137 Second_Rate_miniDSP_D_reg_values_INST_SIZE));
1138 }
1139 }
1140#endif
1141 DBG("\nmode = %d\n", mode);
1142 return mode;
1143}
1144
1145/************************** MUX CONTROL section *****************************/
1146/*
1147 *----------------------------------------------------------------------------
1148 * Function : __new_control_info_minidsp_mux
1149 * Purpose : info routine for mini dsp mux control amixer kcontrols
1150 *----------------------------------------------------------------------------
1151 */
1152static int __new_control_info_minidsp_mux(struct snd_kcontrol *kcontrol,
1153 struct snd_ctl_elem_info *uinfo)
1154{
1155 int index,index2;
1156 int ret_val = -1;
1157
1158
1159 for (index = 0; index < ARRAY_SIZE(main44_MUX_controls); index++) {
1160 if (strstr(kcontrol->id.name, main44_MUX_control_names[index]))
1161 break;
1162 }
1163 if (index < ARRAY_SIZE(main44_MUX_controls))
1164 {
1165 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1166 uinfo->count = 1;
1167 uinfo->value.integer.min = MIN_MUX_CTRL;
1168 uinfo->value.integer.max = MAX_MUX_CTRL;
1169 ret_val = 0;
1170 }
1171
1172 #if 1
1173 else{
1174 printk(" The second rate kcontrol id name is====== %s\n",kcontrol->id.name);
1175
1176
1177 for (index2 = 0; index < ARRAY_SIZE(base_speaker_SRS_MUX_controls); index2++) {
1178 if (strstr(kcontrol->id.name, base_speaker_SRS_MUX_control_names[index2]))
1179 break;
1180 }
1181 if (index < ARRAY_SIZE(base_speaker_SRS_MUX_controls))
1182 {
1183 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1184 uinfo->count = 1;
1185 uinfo->value.integer.min = MIN_MUX_CTRL;
1186 uinfo->value.integer.max = MAX_MUX_CTRL;
1187 ret_val = 0;
1188 }
1189 }
1190
1191 #endif
1192
1193 return ret_val;
1194}
1195
1196/*
1197 *----------------------------------------------------------------------------
1198 * Function : __new_control_get_minidsp_mux
1199 *
1200 * Purpose : get routine for mux control amixer kcontrols,
1201 * read current register values to user.
1202 * Used for for mini dsp 'MUX control' amixer controls.
1203 *----------------------------------------------------------------------------
1204 */
1205static int __new_control_get_minidsp_mux(struct snd_kcontrol *kcontrol,
1206 struct snd_ctl_elem_value *ucontrol)
1207{
1208
1209 ucontrol->value.integer.value[0] = kcontrol->private_value;
1210 return 0;
1211}
1212
1213/*
1214 *----------------------------------------------------------------------------
1215 * Function : __new_control_put_minidsp_mux
1216 *
1217 * Purpose : put routine for amixer kcontrols, write user values to registers
1218 * values. Used for for mini dsp 'MUX control' amixer controls.
1219 *----------------------------------------------------------------------------
1220 */
1221static int __new_control_put_minidsp_mux(struct snd_kcontrol *kcontrol,
1222 struct snd_ctl_elem_value *ucontrol)
1223{
1224 u8 data[MUX_CTRL_REG_SIZE + 1];
1225 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1226 int index = 1;
1227 int user_value = ucontrol->value.integer.value[0];
1228 struct i2c_client *i2c;
1229 u8 value[2], swap_reg_pre, swap_reg_post;
1230 u8 page;
1231 int ret_val = -1, array_size;
1232 control *array;
1233 char **array_names;
1234 char *control_name, *control_name1, *control_name2;
1235 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
1236 i2c = codec->control_data;
1237
1238
1239
1240 if (aic326x->process_flow == 0) {
1241 DBG("#the current process flow is %d", aic326x->process_flow);
1242 array = main44_MUX_controls;
1243 array_size = ARRAY_SIZE(main44_MUX_controls);
1244 array_names = main44_MUX_control_names;
1245 control_name = "Stereo_Mux_TwoToOne_1";
1246 control_name1 = "Mono_Mux_1_1";
1247 }
1248
1249#if 0
1250
1251 /* Configure only for process flow 1 controls */
1252 if (strcmp(kcontrol->id.name, control_name) &&
1253 strcmp(kcontrol->id.name, control_name1))
1254 return 0;
1255 } else {
1256 array = Second_Rate_MUX_controls;
1257 array_size = ARRAY_SIZE(Second_Rate_MUX_controls);
1258 array_names = Second_Rate_MUX_control_names;
1259 control_name = "Stereo_Mux_TwoToOne_1_Second";
1260 control_name1 = "Mono_Mux_1_Second";
1261 control_name2 = "Mono_Mux_4_Second";
1262
1263 /* Configure only for process flow 2 controls */
1264 if (strcmp(kcontrol->id.name, control_name1) &&
1265 strcmp(kcontrol->id.name, control_name2))
1266 return 0;
1267 }
1268
1269#endif
1270
1271 page = array[index].control_page;
1272
1273 DBG("#user value = 0x%x\n", user_value);
1274 for (index = 0; index < array_size; index++) {
1275 if (strstr(kcontrol->id.name, array_names[index]))
1276 break;
1277 }
1278 if (index < array_size) {
1279 DBG(KERN_INFO "#Index %d Changing to Page %d\n", index,
1280 array[index].control_page);
1281
1282 aic3262_change_book(codec,
1283 array[index].control_book);
1284 aic3262_change_page(codec,
1285 array[index].control_page);
1286
1287 if (!strcmp(array_names[index], control_name)) {
1288 if (user_value > 0) {
1289 data[1] = 0x00;
1290 data[2] = 0x00;
1291 data[3] = 0x00;
1292 } else {
1293 data[1] = 0xFF;
1294 data[2] = 0xFf;
1295 data[3] = 0xFF;
1296 }
1297 } else {
1298 if (user_value > 0) {
1299 data[1] =
1300 (u8) ((user_value >> 16) &
1301 AIC3262_8BITS_MASK);
1302 data[2] =
1303 (u8) ((user_value >> 8) &
1304 AIC3262_8BITS_MASK);
1305 data[3] =
1306 (u8)((user_value) & AIC3262_8BITS_MASK);
1307 }
1308 }
1309 /* start register address */
1310 data[0] = array[index].control_base;
1311
1312 DBG(KERN_INFO
1313 "#Writing %d %d %d \r\n", data[0], data[1], data[2]);
1314
1315 ret_val = i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
1316
1317 if (ret_val != MUX_CTRL_REG_SIZE + 1)
1318 printk(KERN_ERR "i2c_master_send transfer failed\n");
1319 else {
1320 /* store the current level */
1321 kcontrol->private_value = user_value;
1322 ret_val = 0;
1323 /* Enable adaptive filtering for ADC/DAC */
1324 }
1325
1326 /* Perform a BUFFER SWAP Command. Check if we are currently not
1327 * in Page 8, if so, swap to Page 8 first
1328 */
1329
1330 value[0] = 1;
1331
1332 if (i2c_master_send(i2c, value, 1) != 1)
1333 printk(KERN_ERR "Can not write register address\n");
1334
1335 /* Read the Value of the Page 8 Register 1 which controls the
1336 Adaptive Switching Mode */
1337 if (i2c_master_recv(i2c, value, 1) != 1)
1338 printk(KERN_ERR "Can not read codec registers\n");
1339
1340 swap_reg_pre = value[0];
1341 /* Write the Register bit updates */
1342 value[1] = value[0] | 1;
1343 value[0] = 1;
1344
1345 if (i2c_master_send(i2c, value, 2) != 2)
1346 printk(KERN_ERR "Can not write register address\n");
1347
1348 value[0] = 1;
1349 /* verify buffer swap */
1350 if (i2c_master_send(i2c, value, 1) != 1)
1351 printk(KERN_ERR "Can not write register address\n");
1352
1353 /* Read the Value of the Page 8 Register 1 which controls the
1354 Adaptive Switching Mode */
1355 if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
1356 printk(KERN_ERR "Can not read codec registers\n");
1357
1358 if ((swap_reg_pre == 4 && swap_reg_post == 6)
1359 || (swap_reg_pre == 6 && swap_reg_post == 4))
1360 DBG("Buffer swap success\n");
1361 else
1362 printk(KERN_ERR
1363 "Buffer swap...FAILED\nswap_reg_pre=%x, \
1364 swap_reg_post=%x\n", swap_reg_pre, swap_reg_post);
1365
1366 }
1367 /* update the new buffer value in the old, just swapped out buffer */
1368 aic3262_change_book(codec, array[index].control_book);
1369 aic3262_change_page(codec, array[index].control_page);
1370 ret_val = i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
1371 ret_val = 0;
1372
1373 aic3262_change_book(codec, 0);
1374 return ret_val;
1375}
1376
1377/*
1378 *----------------------------------------------------------------------------
1379 * Function : minidsp_mux_ctrl_mixer_controls
1380 *
1381 * Purpose : Add amixer kcontrols for mini dsp mux controls,
1382 *----------------------------------------------------------------------------
1383 */
1384static int minidsp_mux_ctrl_mixer_controls(struct snd_soc_codec *codec,
1385 int size, control *cntl,
1386 char **name)
1387{
1388 int i, err;
1389 int val1;
1390
1391 printk("%d mixer controls for mini dsp MUX\n", size);
1392 if (size) {
1393 for (i = 0; i < size; i++) {
1394
1395 snd_mux_controls[i].name = name[i];
1396 snd_mux_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1397 snd_mux_controls[i].access =
1398 SNDRV_CTL_ELEM_ACCESS_READWRITE;
1399 snd_mux_controls[i].info =
1400 __new_control_info_minidsp_mux;
1401 snd_mux_controls[i].get = __new_control_get_minidsp_mux;
1402 snd_mux_controls[i].put = __new_control_put_minidsp_mux;
1403 /*
1404 * TBD: read volume reg and update the index number
1405 */
1406 aic3262_change_book(codec, cntl[i].control_book);
1407 aic3262_change_page(codec, cntl[i].control_page);
1408 val1 = i2c_smbus_read_byte_data(codec->control_data,
1409 cntl[i].control_base);
1410 DBG(KERN_INFO "Control data %x\n", val1);
1411 /*
1412 if( val1 >= 0 )
1413 snd_mux_controls[i].private_value = val1;
1414 else
1415 snd_mux_controls[i].private_value = 0;
1416 */
1417 DBG(KERN_INFO
1418 "the value of amixer control mux=%d", val1);
1419 if (val1 >= 0 && val1 != 255)
1420 snd_mux_controls[i].private_value = val1;
1421 else
1422 snd_mux_controls[i].private_value = 0;
1423
1424 snd_mux_controls[i].count = 0;
1425
1426 err = snd_ctl_add(codec->card->snd_card,
1427 snd_ctl_new1(&snd_mux_controls[i],
1428 codec));
1429 if (err < 0)
1430 printk(KERN_ERR
1431 "%s:Invalid control %s\n", __FILE__,
1432 snd_mux_controls[i].name);
1433 }
1434 }
1435 return 0;
1436}
1437
1438/*------------------------- Volume Controls -----------------------*/
1439static int volume_lite_table[] = {
1440
1441 0x00000D, 0x00000E, 0x00000E, 0x00000F,
1442 0x000010, 0x000011, 0x000012, 0x000013,
1443 0x000015, 0x000016, 0x000017, 0x000018,
1444 0x00001A, 0x00001C, 0x00001D, 0x00001F,
1445 0x000021, 0x000023, 0x000025, 0x000027,
1446 0x000029, 0x00002C, 0x00002F, 0x000031,
1447 0x000034, 0x000037, 0x00003B, 0x00003E,
1448 0x000042, 0x000046, 0x00004A, 0x00004F,
1449 0x000053, 0x000058, 0x00005D, 0x000063,
1450 0x000069, 0x00006F, 0x000076, 0x00007D,
1451 0x000084, 0x00008C, 0x000094, 0x00009D,
1452 0x0000A6, 0x0000B0, 0x0000BB, 0x0000C6,
1453 0x0000D2, 0x0000DE, 0x0000EB, 0x0000F9,
1454 0x000108, 0x000118, 0x000128, 0x00013A,
1455 0x00014D, 0x000160, 0x000175, 0x00018B,
1456 0x0001A3, 0x0001BC, 0x0001D6, 0x0001F2,
1457 0x000210, 0x00022F, 0x000250, 0x000273,
1458 0x000298, 0x0002C0, 0x0002E9, 0x000316,
1459 0x000344, 0x000376, 0x0003AA, 0x0003E2,
1460 0x00041D, 0x00045B, 0x00049E, 0x0004E4,
1461 0x00052E, 0x00057C, 0x0005D0, 0x000628,
1462 0x000685, 0x0006E8, 0x000751, 0x0007C0,
1463 0x000836, 0x0008B2, 0x000936, 0x0009C2,
1464 0x000A56, 0x000AF3, 0x000B99, 0x000C49,
1465 0x000D03, 0x000DC9, 0x000E9A, 0x000F77,
1466 0x001062, 0x00115A, 0x001262, 0x001378,
1467 0x0014A0, 0x0015D9, 0x001724, 0x001883,
1468 0x0019F7, 0x001B81, 0x001D22, 0x001EDC,
1469 0x0020B0, 0x0022A0, 0x0024AD, 0x0026DA,
1470 0x002927, 0x002B97, 0x002E2D, 0x0030E9,
1471 0x0033CF, 0x0036E1, 0x003A21, 0x003D93,
1472 0x004139, 0x004517, 0x00492F, 0x004D85,
1473 0x00521D, 0x0056FA, 0x005C22, 0x006197,
1474 0x006760, 0x006D80, 0x0073FD, 0x007ADC,
1475 0x008224, 0x0089DA, 0x009205, 0x009AAC,
1476 0x00A3D7, 0x00B7D4, 0x00AD8C, 0x00C2B9,
1477 0x00CE43, 0x00DA7B, 0x00E76E, 0x00F524,
1478 0x0103AB, 0x01130E, 0x01235A, 0x01349D,
1479 0x0146E7, 0x015A46, 0x016ECA, 0x018486,
1480 0x019B8C, 0x01B3EE, 0x01CDC3, 0x01E920,
1481 0x02061B, 0x0224CE, 0x024553, 0x0267C5,
1482 0x028C42, 0x02B2E8, 0x02DBD8, 0x030736,
1483 0x033525, 0x0365CD, 0x039957, 0x03CFEE,
1484 0x0409C2, 0x044703, 0x0487E5, 0x04CCA0,
1485 0x05156D, 0x05628A, 0x05B439, 0x060ABF,
1486 0x066666, 0x06C77B, 0x072E50, 0x079B3D,
1487 0x080E9F, 0x0888D7, 0x090A4D, 0x09936E,
1488 0x0A24B0, 0x0ABE8D, 0x0B6188, 0x0C0E2B,
1489 0x0CC509, 0x0D86BD, 0x0E53EB, 0x0F2D42,
1490 0x101379, 0x110754, 0x1209A3, 0x131B40,
1491 0x143D13, 0x157012, 0x16B543, 0x180DB8,
1492 0x197A96, 0x1AFD13, 0x1C9676, 0x1E481C,
1493 0x201373, 0x21FA02, 0x23FD66, 0x261F54,
1494 0x28619A, 0x2AC625, 0x2D4EFB, 0x2FFE44,
1495 0x32D646, 0x35D96B, 0x390A41, 0x3C6B7E,
1496 0x400000, 0x43CAD0, 0x47CF26, 0x4C106B,
1497 0x50923B, 0x55586A, 0x5A6703, 0x5FC253,
1498 0x656EE3, 0x6B7186, 0x71CF54, 0x788DB4,
1499 0x7FB260,
1500};
1501
1502static struct snd_kcontrol_new snd_vol_controls[MAX_VOLUME_CONTROLS];
1503/*
1504 *----------------------------------------------------------------------------
1505 * Function : __new_control_info_main44_minidsp_volume
1506 * Purpose : info routine for volumeLite amixer kcontrols
1507 *----------------------------------------------------------------------------
1508 */
1509
1510static int
1511__new_control_info_minidsp_volume(struct snd_kcontrol *kcontrol,
1512 struct snd_ctl_elem_info *uinfo)
1513{
1514 int index, index8;
1515 int ret_val = -1;
1516
1517 for (index = 0; index < ARRAY_SIZE(main44_VOLUME_controls); index++) {
1518 if (strstr
1519 (kcontrol->id.name, main44_VOLUME_control_names[index]))
1520 break;
1521 }
1522
1523 for (index8 = 0; index8 < ARRAY_SIZE(base_speaker_SRS_VOLUME_controls);
1524 index8++) {
1525 if (strstr
1526 (kcontrol->id.name,
1527 base_speaker_SRS_VOLUME_control_names[index]))
1528 break;
1529 }
1530
1531 if ((index < ARRAY_SIZE(main44_VOLUME_controls))
1532
1533 || (index8 < ARRAY_SIZE(base_speaker_SRS_VOLUME_controls))) {
1534 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1535 uinfo->count = 1;
1536 uinfo->value.integer.min = MIN_VOLUME;
1537 uinfo->value.integer.max = MAX_VOLUME;
1538 ret_val = 0;
1539 }
1540 return ret_val;
1541}
1542
1543/*
1544 *----------------------------------------------------------------------------
1545 * Function : __new_control_get_main44_minidsp_vol
1546 * Purpose : get routine for amixer kcontrols, read current register
1547 * values. Used for for mini dsp 'VolumeLite' amixer controls.
1548 *----------------------------------------------------------------------------
1549 */
1550static int
1551__new_control_get_minidsp_volume(struct snd_kcontrol *kcontrol,
1552 struct snd_ctl_elem_value *ucontrol)
1553{
1554 ucontrol->value.integer.value[0] = kcontrol->private_value;
1555 return 0;
1556}
1557
1558/*
1559 *----------------------------------------------------------------------------
1560 * Function : __new_control_put_main44_minidsp_volume
1561 * Purpose : put routine for amixer kcontrols, write user values to registers
1562 * values. Used for for mini dsp 'VolumeLite' amixer controls.
1563 *----------------------------------------------------------------------------
1564 */
1565static int
1566__new_control_put_minidsp_volume(struct snd_kcontrol *kcontrol,
1567 struct snd_ctl_elem_value *ucontrol)
1568{
1569 u8 data[4];
1570 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1571 int user_value = ucontrol->value.integer.value[0];
1572 struct i2c_client *i2c = codec->control_data;
1573 int ret_val = -1;
1574 int coeff;
1575 u8 value[2], swap_reg_pre, swap_reg_post;
1576 struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
1577
1578 control *volume_controls = NULL;
1579 printk(KERN_INFO "user value = 0x%x\n", user_value);
1580
1581 if (aic3262->process_flow == 0)
1582 volume_controls = main44_VOLUME_controls;
1583
1584 else
1585 volume_controls = base_speaker_SRS_VOLUME_controls;
1586
1587
1588 aic3262_change_book(codec, volume_controls->control_book);
1589 aic3262_change_page(codec, volume_controls->control_page);
1590
1591 coeff = volume_lite_table[user_value << 1];
1592
1593 data[1] = (u8) ((coeff >> 16) & AIC3262_8BITS_MASK);
1594 data[2] = (u8) ((coeff >> 8) & AIC3262_8BITS_MASK);
1595 data[3] = (u8) ((coeff) & AIC3262_8BITS_MASK);
1596
1597 /* Start register address */
1598 data[0] = volume_controls->control_base;
1599 ret_val = i2c_master_send(i2c, data, VOLUME_REG_SIZE + 1);
1600 if (ret_val != VOLUME_REG_SIZE + 1)
1601 printk(KERN_ERR "i2c_master_send transfer failed\n");
1602 else {
1603 /* store the current level */
1604 kcontrol->private_value = user_value;
1605 ret_val = 0;
1606 }
1607 /* Initiate buffer swap */
1608 value[0] = 1;
1609
1610 if (i2c_master_send(i2c, value, 1) != 1)
1611 printk(KERN_ERR "Can not write register address\n");
1612
1613 /* Read the Value of the Page 8 Register 1 which controls the
1614 Adaptive Switching Mode */
1615 if (i2c_master_recv(i2c, value, 1) != 1)
1616 printk(KERN_ERR "Can not read codec registers\n");
1617
1618 swap_reg_pre = value[0];
1619 /* Write the Register bit updates */
1620 value[1] = value[0] | 1;
1621 value[0] = 1;
1622 if (i2c_master_send(i2c, value, 2) != 2)
1623 printk(KERN_ERR "Can not write register address\n");
1624
1625 value[0] = 1;
1626 /* verify buffer swap */
1627 if (i2c_master_send(i2c, value, 1) != 1)
1628 printk(KERN_ERR "Can not write register address\n");
1629
1630 /* Read the Value of the Page 8 Register 1 which controls the
1631 Adaptive Switching Mode */
1632 if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
1633 printk(KERN_ERR "Can not read codec registers\n");
1634
1635 if ((swap_reg_pre == 4 && swap_reg_post == 6)
1636 || (swap_reg_pre == 6 && swap_reg_post == 4))
1637 DBG("Buffer swap success\n");
1638 else
1639 DBG("Buffer swap...FAILED\nswap_reg_pre=%x, swap_reg_post=%x\n",
1640 swap_reg_pre, swap_reg_post);
1641
1642 /* update the new buffer value in the old, just swapped out buffer */
1643 aic3262_change_book(codec, volume_controls->control_book);
1644 aic3262_change_page(codec, volume_controls->control_page);
1645 i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
1646
1647 aic3262_change_book(codec, 0);
1648
1649 return 0;
1650}
1651
1652/*
1653 *----------------------------------------------------------------------------
1654 * Function : minidsp_volume_main44_mixer_controls
1655 * Purpose : Add amixer kcontrols for mini dsp volume Lite controls,
1656 *----------------------------------------------------------------------------
1657 */
1658static int minidsp_volume_mixer_controls(struct snd_soc_codec *codec)
1659{
1660 int i, err, no_volume_controls;
1661 static char volume_control_name[MAX_VOLUME_CONTROLS][40];
1662
1663 /* ADD first process volume controls */
1664 no_volume_controls = ARRAY_SIZE(main44_VOLUME_controls);
1665
1666 printk(KERN_INFO " %d mixer controls for mini dsp 'volumeLite'\n",
1667 no_volume_controls);
1668
1669 if (no_volume_controls) {
1670
1671 for (i = 0; i < no_volume_controls; i++) {
1672 strcpy(volume_control_name[i],
1673 main44_VOLUME_control_names[i]);
1674 strcat(volume_control_name[i], VOLUME_KCONTROL_NAME);
1675
1676 printk(KERN_ERR "Volume controls: %s\n",
1677 volume_control_name[i]);
1678
1679 snd_vol_controls[i].name = volume_control_name[i];
1680 snd_vol_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1681 snd_vol_controls[i].access =
1682 SNDRV_CTL_ELEM_ACCESS_READWRITE;
1683 snd_vol_controls[i].info =
1684 __new_control_info_minidsp_volume;
1685 snd_vol_controls[i].get =
1686 __new_control_get_minidsp_volume;
1687 snd_vol_controls[i].put =
1688 __new_control_put_minidsp_volume;
1689 /*
1690 * TBD: read volume reg and update the index number
1691 */
1692 snd_vol_controls[i].private_value = 0;
1693 snd_vol_controls[i].count = 0;
1694
1695 err = snd_ctl_add(codec->card->snd_card,
1696 snd_ctl_new1(&snd_vol_controls[i],
1697 codec));
1698 if (err < 0) {
1699 printk(KERN_ERR
1700 "%s:Invalid control %s\n", __FILE__,
1701 snd_vol_controls[i].name);
1702 }
1703 }
1704 }
1705
1706
1707 /* ADD second process volume controls */
1708 no_volume_controls = ARRAY_SIZE(base_speaker_SRS_VOLUME_controls);
1709
1710 printk(KERN_ERR " %d mixer controls for mini dsp 'volumeLite'\n",
1711 no_volume_controls);
1712
1713 if (no_volume_controls) {
1714
1715 for (i = 0; i < no_volume_controls; i++) {
1716 strcpy(volume_control_name[i],
1717 base_speaker_SRS_VOLUME_control_names[i]);
1718 strcat(volume_control_name[i], VOLUME_KCONTROL_NAME);
1719
1720 printk(KERN_ERR "Volume controls: %s\n",
1721 volume_control_name[i]);
1722
1723 snd_vol_controls[i].name = volume_control_name[i];
1724 snd_vol_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1725 snd_vol_controls[i].access =
1726 SNDRV_CTL_ELEM_ACCESS_READWRITE;
1727 snd_vol_controls[i].info =
1728 __new_control_info_minidsp_volume;
1729 snd_vol_controls[i].get =
1730 __new_control_get_minidsp_volume;
1731 snd_vol_controls[i].put =
1732 __new_control_put_minidsp_volume;
1733 /*
1734 * TBD: read volume reg and update the index number
1735 */
1736 snd_vol_controls[i].private_value = 0;
1737 snd_vol_controls[i].count = 0;
1738
1739 err = snd_ctl_add(codec->card->snd_card,
1740 snd_ctl_new1(&snd_vol_controls[i],
1741 codec));
1742 if (err < 0) {
1743 printk(KERN_ERR
1744 "%s:Invalid control %s\n", __FILE__,
1745 snd_vol_controls[i].name);
1746 }
1747 }
1748 }
1749
1750 return 0;
1751}
1752
1753/*
1754 *--------------------------------------------------------------------------
1755 * Function : aic3262_add_minidsp_controls
1756 * Purpose : Configures the AMIXER Control Interfaces that can be exercised by
1757 * the user at run-time. Utilizes the the snd_adaptive_controls[]
1758 * array to specify two run-time controls.
1759 *---------------------------------------------------------------------------
1760 */
1761int aic3262_add_minidsp_controls(struct snd_soc_codec *codec)
1762{
1763#ifdef ADD_MINI_DSP_CONTROLS
1764 int i, err, no_mux_controls,no_mux_controls1;
1765 /* add mode k control */
1766 for (i = 0; i < ARRAY_SIZE(aic3262_minidsp_controls); i++) {
1767 err = snd_ctl_add(codec->card->snd_card,
1768 snd_ctl_new1(&aic3262_minidsp_controls[i], codec));
1769 if (err < 0) {
1770 printk(KERN_ERR "Invalid control\n");
1771 return err;
1772 }
1773 }
1774
1775
1776 /* add mux controls */
1777 no_mux_controls = ARRAY_SIZE(main44_MUX_controls);
1778 minidsp_mux_ctrl_mixer_controls(codec, no_mux_controls,
1779 main44_MUX_controls, main44_MUX_control_names);
1780
1781
1782 no_mux_controls1 = ARRAY_SIZE(base_speaker_SRS_MUX_controls);
1783 minidsp_mux_ctrl_mixer_controls(codec, no_mux_controls1,
1784 base_speaker_SRS_MUX_controls, base_speaker_SRS_MUX_control_names);
1785
1786
1787 /* add volume controls*/
1788 minidsp_volume_mixer_controls(codec);
1789#endif /* ADD_MINI_DSP_CONTROLS */
1790 return 0;
1791}
1792
1793MODULE_DESCRIPTION("ASoC TLV320AIC3262 miniDSP driver");
1794MODULE_AUTHOR("Y Preetam Sashank Reddy <preetam@mistralsolutions.com>");
1795MODULE_LICENSE("GPL");
1796#endif /* End of CONFIG_MINI_DSP */
diff --git a/sound/soc/codecs/tlv320aic326x_mini-dsp.h b/sound/soc/codecs/tlv320aic326x_mini-dsp.h
new file mode 100644
index 00000000000..bebb12fa680
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_mini-dsp.h
@@ -0,0 +1,128 @@
1/*
2 * linux/sound/soc/codecs/tlv320aic3262_mini-dsp.h
3 *
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 *
7 *
8 * This package is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
13 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
14 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15 *
16 * History:
17 * Rev 0.1 Added the multiconfig support 17-08-2011
18 *
19 * Rev 0.2 Migrated for aic3262 nVidia
20 * 21-10-2011
21 */
22
23#ifndef _TLV320AIC3262_MINI_DSP_H
24#define _TLV320AIC3262_MINI_DSP_H
25
26/* defines */
27
28#define MAXCONFIG 4
29
30//#define DEBUG_MINIDSP_LOADING
31
32/* Select the functionalities to be used in mini dsp module */
33#define PROGRAM_MINI_DSP_first
34//#define PROGRAM_MINI_DSP_second
35#define PROGRAM_CODEC_REG_SECTIONS
36#define ADD_MINI_DSP_CONTROLS
37
38/* use the following macros to select between burst and byte mode of i2c
39 * Byte mode uses standard read & write as provides debugging information if enabled
40 * if enabled.
41 * Multibyte should be used for production codes where performance is priority
42 */
43//#define MULTIBYTE_I2C
44#undef MULTIBYTE_I2C
45
46typedef struct {
47 u8 reg_off;
48 u8 reg_val;
49} reg_value;
50
51/*CONTROL LOCATIONS*/
52typedef struct {
53 u8 control_book; /*coefficient book location*/
54 u8 control_page; /*coefficient page location*/
55 u8 control_base; /*coefficient base address within page*/
56 u8 control_mute_flag; /*non-zero means muting required*/
57 u8 control_string_index; /*string table index*/
58} control;
59
60/* volume ranges from -110db to 6db
61 * amixer controls does not accept negative values
62 * Therefore we are normalizing values to start from value 0
63 * value 0 corresponds to -110db and 116 to 6db
64 */
65#define MAX_VOLUME_CONTROLS 2
66#define MIN_VOLUME 0
67#define MAX_VOLUME 116
68#define VOLUME_REG_SIZE 3 /* 3 bytes */
69#define VOLUME_KCONTROL_NAME "(0=-110dB, 116=+6dB)"
70
71#define FILT_CTL_NAME_ADC "ADC adaptive filter(0=Disable, 1=Enable)"
72#define FILT_CTL_NAME_DAC "DAC adaptive filter(0=Disable, 1=Enable)"
73#define COEFF_CTL_NAME_ADC "ADC coeff Buffer(0=Buffer A, 1=Buffer B)"
74#define COEFF_CTL_NAME_DAC "DAC coeff Buffer(0=Buffer A, 1=Buffer B)"
75
76#define BUFFER_PAGE_ADC 0x8
77#define BUFFER_PAGE_DAC 0x2c
78
79#define ADAPTIVE_MAX_CONTROLS 4
80
81/*
82 * MUX controls, 3 bytes of control data.
83 */
84#define MAX_MUX_CONTROLS 2
85#define MIN_MUX_CTRL 0
86#define MAX_MUX_CTRL 2
87#define MUX_CTRL_REG_SIZE 3 /* 3 bytes */
88
89#define MINIDSP_PARSING_START 0
90#define MINIDSP_PARSING_END (-1)
91
92#define CODEC_REG_DONT_IGNORE 0
93#define CODEC_REG_IGNORE 1
94
95#define CODEC_REG_PRE_INIT 0
96#define CODEC_REG_POST_INIT 1
97#define INIT_SEQ_DELIMITER 255 /* Delimiter register */
98#define DELIMITER_COUNT 2 /* 2 delimiter entries */
99
100/* Parser info structure */
101typedef struct {
102 char page_num;
103 char burst_array[129];
104 int burst_size;
105 int current_loc;
106 int book_change;CONFIG_MINI_DSP
107 u8 book_no;
108} minidsp_parser_data;
109
110/* I2c Page Change Structure */
111typedef struct {
112 char burst_array[4];
113} minidsp_i2c_page;
114
115/* This macro defines the total size of the miniDSP parser arrays
116 * that the driver will maintain as a data backup.
117 * The total memory requirement will be around
118 * sizeof(minidsp_parser_data) * 48 = 138 * 32 = 4416 bytes
119 */
120#define MINIDSP_PARSER_ARRAY_SIZE 200
121
122extern int
123minidsp_i2c_multibyte_transfer(struct snd_soc_codec *, reg_value *, int);
124extern int byte_i2c_array_transfer(struct snd_soc_codec *, reg_value *, int);
125extern void minidsp_multiconfig(struct snd_soc_codec *,reg_value *, int ,reg_value *, int );
126extern int reg_def_conf(struct snd_soc_codec *);
127
128#endif
diff --git a/sound/soc/codecs/tlv320aic326x_minidsp_config.c b/sound/soc/codecs/tlv320aic326x_minidsp_config.c
new file mode 100644
index 00000000000..e34ffbe2ca8
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_minidsp_config.c
@@ -0,0 +1,495 @@
1/*
2 * linux/sound/soc/codecs/tlv320aic326x_minidsp_config.c
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
15 * codec with digital microphone inputs and programmable outputs.
16 *
17 * History:
18 *
19 * Rev 0.1 Added the multiconfig support 17-08-2011
20 *
21 * Rev 0.2 Migrated for aic3262 nVidia
22 * 21-10-2011
23 */
24
25/*
26 *****************************************************************************
27 * INCLUDES
28 *****************************************************************************
29 */
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/fs.h>
35#include <linux/types.h>
36#include <linux/kdev_t.h>
37#include <linux/cdev.h>
38#include <linux/device.h>
39#include <linux/io.h>
40#include <linux/delay.h>
41#include <linux/i2c.h>
42#include <linux/platform_device.h>
43#include <sound/soc.h>
44#include <sound/core.h>
45#include <sound/soc-dapm.h>
46#include <sound/control.h>
47#include <linux/time.h> /* For timing computations */
48#include "tlv320aic326x.h"
49#include "tlv320aic326x_mini-dsp.h"
50
51#if 0
52#include "Patch_base_jazz_Rate48_pps_driver.h"
53#include "Patch_base_main_Rate48_pps_driver.h"
54#include "Patch_base_pop_Rate48_pps_driver.h"
55#include "Patch_base_rock_Rate48_pps_driver.h"
56#endif
57
58#ifdef CONFIG_MINI_DSP
59
60#define MAX_CONFIG_D_ARRAYS 4
61#define MAX_CONFIG_A_ARRAYS 0
62#define MAX_CONFIG_ARRAYS 4
63#define MINIDSP_DMODE 0
64#define MINIDSP_AMODE 1
65
66/*
67 *****************************************************************************
68 * LOCAL STATIC DECLARATIONS
69 *****************************************************************************
70 */
71static int multibyte_coeff_change(struct snd_soc_codec *codec, int);
72
73static int m_control_get(struct snd_kcontrol *kcontrol,
74 struct snd_ctl_elem_value *ucontrol);
75static int m_control_put(struct snd_kcontrol *kcontrol,
76 struct snd_ctl_elem_value *ucontrol);
77
78/* k-control macros used for miniDSP related Kcontrols */
79#define SOC_SINGLE_VALUE_M(xmax, xinvert) \
80 ((unsigned long)&(struct soc_mixer_control) \
81 {.max = xmax, \
82 .invert = xinvert})
83#define SOC_SINGLE_M(xname, max, invert) \
84{\
85 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
86 .info = m_control_info, .get = m_control_get,\
87 .put = m_control_put, \
88 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
89 .private_value = SOC_SINGLE_VALUE_M(max, invert) }
90#define SOC_SINGLE_AIC3262_M(xname) \
91{\
92 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
93 .info = m_control_info, .get = m_control_get,\
94 .put = m_control_put, \
95 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
96}
97
98
99/* The Multi-Configurations generated through PPS GDE has been
100 * named as Rock, Pop, Jazz and Main. These were the Configurations
101 * that were used while testing this AUdio Driver. If the user
102 * creates Process-flow with different names, it is advised to
103 * modify the names present in the below array.
104 */
105static const char *multi_config_support_DAC[] = {
106 "ROCK",
107 "POP",
108 "JAZZ",
109 "MAIN",
110};
111
112/* SOC_ENUM Declaration and kControl for switching Configurations
113 * at run-time.
114 */
115static const struct soc_enum aic3262_enum =
116 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(multi_config_support_DAC),
117 multi_config_support_DAC);
118
119static const struct snd_kcontrol_new aic3262_minidsp_controls1[] = {
120
121 SOC_ENUM_EXT("Multiconfig support for DAC",
122 aic3262_enum, m_control_get, m_control_put),
123
124};
125
126
127/*
128 * multibyte_config
129 *
130 * This structure has been devised to maintain information about each
131 * configuration provided with the PPS GDE Processflow. For each
132 * configuration, the Driver needs to know where the starting offset
133 * of the Coefficient change, Total Size of Coefficients being affected,
134 * and the Instruction Sizes.
135 * This has to be replicated for both miniDSP_A and miniDSP_D
136 */
137
138#if 0
139struct multibyte_config {
140 reg_value *regs;
141 unsigned int d_coeff_start;
142 unsigned int d_coeff_size;
143 unsigned int d_inst_start;
144 unsigned int d_inst_size;
145 unsigned int a_coeff_start;
146 unsigned int a_coeff_size;
147 unsigned int a_inst_start;
148 unsigned int a_inst_size;
149} config_array[][2][MAX_CONFIG_ARRAYS] = {
150 /* Process flow 1 */
151 {
152 {
153 /* DAC */
154 {rock_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
155 {pop_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
156 {jazz_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
157 {main_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
158 },
159 /* ADC */
160 {},
161 },
162
163 /* Process flow 2 */
164 {
165#if 0
166 {
167 {main, 0, 0, 0, 0, 0, 0, 0, 0},
168 {pop, 0, 0, 0, 0, 0, 0, 0, 0},
169 {jazz, 0, 0, 0, 0, 0, 0, 0, 0},
170 {rock, 0, 0, 0, 0, 0, 0, 0, 0},
171 },
172 /* ADC */
173 {},
174#endif
175 },
176};
177
178#else
179struct multibyte_config {
180 reg_value *regs;
181 unsigned int d_coeff_start;
182 unsigned int d_coeff_size;
183 unsigned int d_inst_start;
184 unsigned int d_inst_size;
185 unsigned int a_coeff_start;
186 unsigned int a_coeff_size;
187 unsigned int a_inst_start;
188 unsigned int a_inst_size;
189} config_array[][2][MAX_CONFIG_ARRAYS] = {
190 /* Process flow 1 */
191 {
192 {
193 /* DAC */
194 {},
195 },
196 /* ADC */
197 {},
198 },
199
200 /* Process flow 2 */
201 {
202#if 0
203 {
204 {main, 0, 0, 0, 0, 0, 0, 0, 0},
205 {pop, 0, 0, 0, 0, 0, 0, 0, 0},
206 {jazz, 0, 0, 0, 0, 0, 0, 0, 0},
207 {rock, 0, 0, 0, 0, 0, 0, 0, 0},
208 },
209 /* ADC */
210 {},
211#endif
212 },
213};
214#endif
215
216/*
217 *----------------------------------------------------------------------------
218 * Function : m_control_get
219 * Purpose : This function is to read data of new control for
220 * program the AIC3262 registers.
221 *
222 *----------------------------------------------------------------------------
223 */
224static int m_control_get(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_value *ucontrol)
226{
227
228 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
229 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
230 u32 val = 0;
231 u32 mode = aic326x->process_flow;
232
233
234 if (!strcmp(kcontrol->id.name, "Multiconfig support for DAC"))
235 val = aic326x->current_dac_config[mode];
236 else if (!strcmp(kcontrol->id.name, "Multiconfig support for ADC"))
237 val = aic326x->current_adc_config[mode];
238
239
240 ucontrol->value.integer.value[0] = val;
241 return 0;
242}
243
244/*
245 *----------------------------------------------------------------------------
246 * Function : m_new_control_put
247 * Purpose : new_control_put is called to pass data from user/application to
248 * the driver.
249 *
250 *----------------------------------------------------------------------------
251 */
252static int m_control_put(struct snd_kcontrol *kcontrol,
253 struct snd_ctl_elem_value *ucontrol)
254{
255 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
256 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
257 u32 val;
258 u8 value;
259 int pf = aic326x->process_flow;
260 struct multibyte_config *array;
261
262 val = ucontrol->value.integer.value[0];
263 if (!strcmp(kcontrol->id.name, "Multiconfig support for DAC")) {
264 if (aic326x->process_flow == MINIDSP_DMODE) {
265 if (val > MAX_CONFIG_D_ARRAYS) {
266 dev_err(codec->dev, "Value not in range\n");
267 return -1;
268 }
269
270 value = aic3262_read(codec, ADC_CHANNEL_POW);
271 value = aic3262_read(codec, PASI_DAC_DP_SETUP);
272
273 array = &config_array[pf][MINIDSP_DMODE][val];
274 minidsp_i2c_multibyte_transfer(codec,
275 array->regs,
276 (array->d_inst_size + array->d_coeff_size));
277
278
279 /*coefficent buffer change*/
280 multibyte_coeff_change(codec, 0x50);
281
282 minidsp_i2c_multibyte_transfer(codec,
283 array->regs,
284 (array->d_inst_size + array->d_coeff_size));
285
286
287
288 value = aic3262_read(codec, ADC_CHANNEL_POW);
289 value = aic3262_read(codec, PASI_DAC_DP_SETUP);
290 }
291 aic326x->current_dac_config[pf] = val;
292
293 } else {
294 if (aic326x->process_flow == MINIDSP_AMODE) {
295 if (val > MAX_CONFIG_A_ARRAYS) {
296 dev_err(codec->dev, "Value not in range\n");
297 return -1;
298 }
299 array = &config_array[pf][MINIDSP_AMODE][val];
300 minidsp_i2c_multibyte_transfer(codec,
301 array->regs,
302 (array->a_inst_size + array->a_coeff_size));
303 }
304 aic326x->current_adc_config[pf] = val;
305 }
306 return val;
307}
308
309
310/*
311 *--------------------------------------------------------------------------
312 * Function : aic3262_add_multiconfig_controls
313 * Purpose : Configures the AMIXER Control Interfaces that can be exercised by
314 * the user at run-time. Utilizes the the snd_adaptive_controls[]
315 * array to specify two run-time controls.
316 *---------------------------------------------------------------------------
317 */
318int aic3262_add_multiconfig_controls(struct snd_soc_codec *codec)
319{
320 int i, err;
321
322 DBG(KERN_INFO
323 "#%s: Invoked to add controls for Multi-Configuration\n",
324 __func__);
325
326 /* add mode k control */
327 for (i = 0; i < ARRAY_SIZE(aic3262_minidsp_controls1); i++) {
328 err = snd_ctl_add(codec->card->snd_card,
329 snd_ctl_new1(&aic3262_minidsp_controls1[i],
330 codec));
331 if (err < 0) {
332 printk(KERN_ERR
333 "Cannot add controls for mulibyte configuration\n");
334 return err;
335 }
336 }
337 DBG(KERN_INFO "#%s: Completed control addition.\n", __func__);
338 return 0;
339}
340
341/*
342 *--------------------------------------------------------------------------
343 * Function : minidsp_multiconfig
344 * Purpose : Function which is invoked when user changes the configuration
345 * at run-time. Internally configures/switches both
346 * miniDSP_D and miniDSP_A Coefficient arrays.
347 *---------------------------------------------------------------------------
348 */
349void minidsp_multiconfig(struct snd_soc_codec *codec,
350 reg_value *a_patch, int a_size,
351 reg_value *d_patch, int d_size)
352{
353 struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
354 int val1,val2;
355 int adc_status,dac_status;
356 int (*ptransfer)(struct snd_soc_codec *codec,
357 reg_value *program_ptr,
358 int size);
359
360printk("======in the config_multiconfiguration function==== \n");
361#ifndef MULTIBYTE_I2C
362 ptransfer = byte_i2c_array_transfer;
363#else
364 ptransfer = minidsp_i2c_multibyte_transfer;
365#endif
366 //DBG(KERN_INFO "#%s: Invoked for miniDSP Mode %d\n", __func__, mode);
367
368 adc_status=aic3262_read(codec,ADC_FLAG_R1);
369 printk("ADC STATUS = %x", adc_status);
370
371 dac_status=aic3262_read(codec,DAC_FLAG_R1);
372 printk("DAC STATUS = %x", dac_status);
373
374 #if 0
375 /* Switching off the adaptive filtering for loading the patch file*/
376 aic3262_change_book(codec, 40);
377 val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
378 aic3262_write(codec, 1, (val1&0xfb));
379
380 aic3262_change_book(codec, 80);
381 val2 = i2c_smbus_read_byte_data(codec->control_data, 1);
382 aic3262_write(codec, 1, (val2&0xfb));
383
384 #endif
385
386 /*apply patches to both pages (mirrored coeffs). this works when DSP are stopped*/
387 /* to apply patches when DSPs are runnig, the 'buffer swap' has to be executed, which is
388 done in the buffer swap section below*/
389
390 if (a_size)
391 ptransfer (codec, a_patch, a_size);
392 if (d_size)
393 ptransfer (codec, d_patch, d_size);
394
395
396 /*swap buffers for both a&d only if DSPs are running*/
397 if((dac_status & 0x80) || (dac_status & 0x8))
398 {
399 multibyte_coeff_change(codec, 0x50);/*swap DSP D Buffer*/
400 if (d_size)
401 ptransfer(codec, d_patch, d_size); /*apply patch after swapping buffer*/
402 }
403
404 if((adc_status & 0x40) || (adc_status & 0x4))
405 {
406 multibyte_coeff_change(codec, 0x28);/*swap DSP A Buffer*/
407 if (a_size)
408 ptransfer(codec, a_patch, a_size); /*apply patch after swapping buffer*/
409 }
410
411 #if 0
412 if (a_size)
413 ptransfer (codec, a_patch, a_size);
414 if (d_size)
415 ptransfer (codec, d_patch, d_size);
416 #endif
417
418
419 return ;
420}
421
422/*
423 *--------------------------------------------------------------------------
424 * Function : config_multibyte_for_mode
425 * Purpose : Function which is invoked when user changes the configuration
426 * at run-time. Internally configures/switches both
427 * miniDSP_D and miniDSP_A Coefficient arrays.
428 *---------------------------------------------------------------------------
429 */
430static int multibyte_coeff_change(struct snd_soc_codec *codec, int bk)
431{
432
433 u8 value[2], swap_reg_pre, swap_reg_post;
434 struct i2c_client *i2c;
435 i2c = codec->control_data;
436
437 aic3262_change_book(codec, bk);
438 aic3262_change_page(codec, 0);
439
440 value[0] = 1;
441
442 if (i2c_master_send(i2c, value, 1) != 1)
443 printk(KERN_ERR "Can not write register address\n");
444 else {
445 /* Read the Value of the Page 8 Register 1 which controls the
446 Adaptive Switching Mode */
447 if (i2c_master_recv(i2c, value, 1) != 1) {
448 printk(KERN_ERR "Can not read codec registers\n");
449 goto err;
450 }
451 swap_reg_pre = value[0];
452
453 /* Write the Register bit updates */
454 value[1] = value[0] | 1;
455 value[0] = 1;
456
457 if (i2c_master_send(i2c, value, 2) != 2) {
458 printk(KERN_ERR "Can not write register address\n");
459 goto err;
460 }
461 /*before verifying for buffer_swap, make sure we give one
462 frame delay, because the buffer swap happens at the end of the frame */
463 mdelay(5);
464 value[0] = 1;
465 /* verify buffer swap */
466 if (i2c_master_send(i2c, value, 1) != 1)
467 printk(KERN_ERR "Can not write register address\n");
468
469 /* Read the Value of the Page 8 Register 1 which controls the
470 Adaptive Switching Mode */
471 if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
472 printk(KERN_ERR "Can not read codec registers\n");
473
474 if ((swap_reg_pre == 4 && swap_reg_post == 6)
475 || (swap_reg_pre == 6 && swap_reg_post == 4))
476 printk(KERN_INFO "Buffer swap success\n");
477 else
478 printk(KERN_ERR
479 "Buffer swap...FAILED\nswap_reg_pre=%x, swap_reg_post=%x\n",
480 swap_reg_pre, swap_reg_post);
481
482 aic3262_change_book(codec, 0x00);
483 }
484
485err:
486 return 0;
487}
488
489
490
491#endif
492
493MODULE_DESCRIPTION("ASoC AIC3262 miniDSP multi-configuration");
494MODULE_AUTHOR("Barani Prashanth <gvbarani@mistralsolutions.com>");
495MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c
new file mode 100644
index 00000000000..a87adbd05ee
--- /dev/null
+++ b/sound/soc/codecs/wm8994-tables.c
@@ -0,0 +1,3147 @@
1#include "wm8994.h"
2
3const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = {
4 { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
5 { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
6 { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
7 { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
8 { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
9 { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
10 { 0x003F, 0x003F }, /* R6 - Power Management (6) */
11 { 0x0000, 0x0000 }, /* R7 */
12 { 0x0000, 0x0000 }, /* R8 */
13 { 0x0000, 0x0000 }, /* R9 */
14 { 0x0000, 0x0000 }, /* R10 */
15 { 0x0000, 0x0000 }, /* R11 */
16 { 0x0000, 0x0000 }, /* R12 */
17 { 0x0000, 0x0000 }, /* R13 */
18 { 0x0000, 0x0000 }, /* R14 */
19 { 0x0000, 0x0000 }, /* R15 */
20 { 0x0000, 0x0000 }, /* R16 */
21 { 0x0000, 0x0000 }, /* R17 */
22 { 0x0000, 0x0000 }, /* R18 */
23 { 0x0000, 0x0000 }, /* R19 */
24 { 0x0000, 0x0000 }, /* R20 */
25 { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
26 { 0x0000, 0x0000 }, /* R22 */
27 { 0x0000, 0x0000 }, /* R23 */
28 { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
29 { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
30 { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
31 { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
32 { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
33 { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
34 { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
35 { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
36 { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
37 { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
38 { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
39 { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
40 { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
41 { 0x003F, 0x003F }, /* R37 - ClassD */
42 { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
43 { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
44 { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
45 { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
46 { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
47 { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
48 { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
49 { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
50 { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
51 { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
52 { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
53 { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
54 { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
55 { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
56 { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
57 { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
58 { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
59 { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
60 { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
61 { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
62 { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
63 { 0x000F, 0x000F }, /* R59 - LDO 1 */
64 { 0x0007, 0x0007 }, /* R60 - LDO 2 */
65 { 0xFFFF, 0xFFFF }, /* R61 */
66 { 0xFFFF, 0xFFFF }, /* R62 */
67 { 0x0000, 0x0000 }, /* R63 */
68 { 0x0000, 0x0000 }, /* R64 */
69 { 0x0000, 0x0000 }, /* R65 */
70 { 0x0000, 0x0000 }, /* R66 */
71 { 0x0000, 0x0000 }, /* R67 */
72 { 0x0000, 0x0000 }, /* R68 */
73 { 0x0000, 0x0000 }, /* R69 */
74 { 0x0000, 0x0000 }, /* R70 */
75 { 0x0000, 0x0000 }, /* R71 */
76 { 0x0000, 0x0000 }, /* R72 */
77 { 0x0000, 0x0000 }, /* R73 */
78 { 0x0000, 0x0000 }, /* R74 */
79 { 0x0000, 0x0000 }, /* R75 */
80 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
81 { 0x0000, 0x0000 }, /* R77 */
82 { 0x0000, 0x0000 }, /* R78 */
83 { 0x0000, 0x0000 }, /* R79 */
84 { 0x0000, 0x0000 }, /* R80 */
85 { 0x0301, 0x0301 }, /* R81 - Class W (1) */
86 { 0x0000, 0x0000 }, /* R82 */
87 { 0x0000, 0x0000 }, /* R83 */
88 { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
89 { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
90 { 0x0000, 0x0000 }, /* R86 */
91 { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
92 { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
93 { 0x0000, 0x0000 }, /* R89 */
94 { 0x0000, 0x0000 }, /* R90 */
95 { 0x0000, 0x0000 }, /* R91 */
96 { 0x0000, 0x0000 }, /* R92 */
97 { 0x0000, 0x0000 }, /* R93 */
98 { 0x0000, 0x0000 }, /* R94 */
99 { 0x0000, 0x0000 }, /* R95 */
100 { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
101 { 0x0000, 0x0000 }, /* R97 */
102 { 0x0000, 0x0000 }, /* R98 */
103 { 0x0000, 0x0000 }, /* R99 */
104 { 0x0000, 0x0000 }, /* R100 */
105 { 0x0000, 0x0000 }, /* R101 */
106 { 0x0000, 0x0000 }, /* R102 */
107 { 0x0000, 0x0000 }, /* R103 */
108 { 0x0000, 0x0000 }, /* R104 */
109 { 0x0000, 0x0000 }, /* R105 */
110 { 0x0000, 0x0000 }, /* R106 */
111 { 0x0000, 0x0000 }, /* R107 */
112 { 0x0000, 0x0000 }, /* R108 */
113 { 0x0000, 0x0000 }, /* R109 */
114 { 0x0000, 0x0000 }, /* R110 */
115 { 0x0000, 0x0000 }, /* R111 */
116 { 0x0000, 0x0000 }, /* R112 */
117 { 0x0000, 0x0000 }, /* R113 */
118 { 0x0000, 0x0000 }, /* R114 */
119 { 0x0000, 0x0000 }, /* R115 */
120 { 0x0000, 0x0000 }, /* R116 */
121 { 0x0000, 0x0000 }, /* R117 */
122 { 0x0000, 0x0000 }, /* R118 */
123 { 0x0000, 0x0000 }, /* R119 */
124 { 0x0000, 0x0000 }, /* R120 */
125 { 0x0000, 0x0000 }, /* R121 */
126 { 0x0000, 0x0000 }, /* R122 */
127 { 0x0000, 0x0000 }, /* R123 */
128 { 0x0000, 0x0000 }, /* R124 */
129 { 0x0000, 0x0000 }, /* R125 */
130 { 0x0000, 0x0000 }, /* R126 */
131 { 0x0000, 0x0000 }, /* R127 */
132 { 0x0000, 0x0000 }, /* R128 */
133 { 0x0000, 0x0000 }, /* R129 */
134 { 0x0000, 0x0000 }, /* R130 */
135 { 0x0000, 0x0000 }, /* R131 */
136 { 0x0000, 0x0000 }, /* R132 */
137 { 0x0000, 0x0000 }, /* R133 */
138 { 0x0000, 0x0000 }, /* R134 */
139 { 0x0000, 0x0000 }, /* R135 */
140 { 0x0000, 0x0000 }, /* R136 */
141 { 0x0000, 0x0000 }, /* R137 */
142 { 0x0000, 0x0000 }, /* R138 */
143 { 0x0000, 0x0000 }, /* R139 */
144 { 0x0000, 0x0000 }, /* R140 */
145 { 0x0000, 0x0000 }, /* R141 */
146 { 0x0000, 0x0000 }, /* R142 */
147 { 0x0000, 0x0000 }, /* R143 */
148 { 0x0000, 0x0000 }, /* R144 */
149 { 0x0000, 0x0000 }, /* R145 */
150 { 0x0000, 0x0000 }, /* R146 */
151 { 0x0000, 0x0000 }, /* R147 */
152 { 0x0000, 0x0000 }, /* R148 */
153 { 0x0000, 0x0000 }, /* R149 */
154 { 0x0000, 0x0000 }, /* R150 */
155 { 0x0000, 0x0000 }, /* R151 */
156 { 0x0000, 0x0000 }, /* R152 */
157 { 0x0000, 0x0000 }, /* R153 */
158 { 0x0000, 0x0000 }, /* R154 */
159 { 0x0000, 0x0000 }, /* R155 */
160 { 0x0000, 0x0000 }, /* R156 */
161 { 0x0000, 0x0000 }, /* R157 */
162 { 0x0000, 0x0000 }, /* R158 */
163 { 0x0000, 0x0000 }, /* R159 */
164 { 0x0000, 0x0000 }, /* R160 */
165 { 0x0000, 0x0000 }, /* R161 */
166 { 0x0000, 0x0000 }, /* R162 */
167 { 0x0000, 0x0000 }, /* R163 */
168 { 0x0000, 0x0000 }, /* R164 */
169 { 0x0000, 0x0000 }, /* R165 */
170 { 0x0000, 0x0000 }, /* R166 */
171 { 0x0000, 0x0000 }, /* R167 */
172 { 0x0000, 0x0000 }, /* R168 */
173 { 0x0000, 0x0000 }, /* R169 */
174 { 0x0000, 0x0000 }, /* R170 */
175 { 0x0000, 0x0000 }, /* R171 */
176 { 0x0000, 0x0000 }, /* R172 */
177 { 0x0000, 0x0000 }, /* R173 */
178 { 0x0000, 0x0000 }, /* R174 */
179 { 0x0000, 0x0000 }, /* R175 */
180 { 0x0000, 0x0000 }, /* R176 */
181 { 0x0000, 0x0000 }, /* R177 */
182 { 0x0000, 0x0000 }, /* R178 */
183 { 0x0000, 0x0000 }, /* R179 */
184 { 0x0000, 0x0000 }, /* R180 */
185 { 0x0000, 0x0000 }, /* R181 */
186 { 0x0000, 0x0000 }, /* R182 */
187 { 0x0000, 0x0000 }, /* R183 */
188 { 0x0000, 0x0000 }, /* R184 */
189 { 0x0000, 0x0000 }, /* R185 */
190 { 0x0000, 0x0000 }, /* R186 */
191 { 0x0000, 0x0000 }, /* R187 */
192 { 0x0000, 0x0000 }, /* R188 */
193 { 0x0000, 0x0000 }, /* R189 */
194 { 0x0000, 0x0000 }, /* R190 */
195 { 0x0000, 0x0000 }, /* R191 */
196 { 0x0000, 0x0000 }, /* R192 */
197 { 0x0000, 0x0000 }, /* R193 */
198 { 0x0000, 0x0000 }, /* R194 */
199 { 0x0000, 0x0000 }, /* R195 */
200 { 0x0000, 0x0000 }, /* R196 */
201 { 0x0000, 0x0000 }, /* R197 */
202 { 0x0000, 0x0000 }, /* R198 */
203 { 0x0000, 0x0000 }, /* R199 */
204 { 0x0000, 0x0000 }, /* R200 */
205 { 0x0000, 0x0000 }, /* R201 */
206 { 0x0000, 0x0000 }, /* R202 */
207 { 0x0000, 0x0000 }, /* R203 */
208 { 0x0000, 0x0000 }, /* R204 */
209 { 0x0000, 0x0000 }, /* R205 */
210 { 0x0000, 0x0000 }, /* R206 */
211 { 0x0000, 0x0000 }, /* R207 */
212 { 0xFFFF, 0xFFFF }, /* R208 */
213 { 0xFFFF, 0xFFFF }, /* R209 */
214 { 0xFFFF, 0xFFFF }, /* R210 */
215 { 0x0000, 0x0000 }, /* R211 */
216 { 0x0000, 0x0000 }, /* R212 */
217 { 0x0000, 0x0000 }, /* R213 */
218 { 0x0000, 0x0000 }, /* R214 */
219 { 0x0000, 0x0000 }, /* R215 */
220 { 0x0000, 0x0000 }, /* R216 */
221 { 0x0000, 0x0000 }, /* R217 */
222 { 0x0000, 0x0000 }, /* R218 */
223 { 0x0000, 0x0000 }, /* R219 */
224 { 0x0000, 0x0000 }, /* R220 */
225 { 0x0000, 0x0000 }, /* R221 */
226 { 0x0000, 0x0000 }, /* R222 */
227 { 0x0000, 0x0000 }, /* R223 */
228 { 0x0000, 0x0000 }, /* R224 */
229 { 0x0000, 0x0000 }, /* R225 */
230 { 0x0000, 0x0000 }, /* R226 */
231 { 0x0000, 0x0000 }, /* R227 */
232 { 0x0000, 0x0000 }, /* R228 */
233 { 0x0000, 0x0000 }, /* R229 */
234 { 0x0000, 0x0000 }, /* R230 */
235 { 0x0000, 0x0000 }, /* R231 */
236 { 0x0000, 0x0000 }, /* R232 */
237 { 0x0000, 0x0000 }, /* R233 */
238 { 0x0000, 0x0000 }, /* R234 */
239 { 0x0000, 0x0000 }, /* R235 */
240 { 0x0000, 0x0000 }, /* R236 */
241 { 0x0000, 0x0000 }, /* R237 */
242 { 0x0000, 0x0000 }, /* R238 */
243 { 0x0000, 0x0000 }, /* R239 */
244 { 0x0000, 0x0000 }, /* R240 */
245 { 0x0000, 0x0000 }, /* R241 */
246 { 0x0000, 0x0000 }, /* R242 */
247 { 0x0000, 0x0000 }, /* R243 */
248 { 0x0000, 0x0000 }, /* R244 */
249 { 0x0000, 0x0000 }, /* R245 */
250 { 0x0000, 0x0000 }, /* R246 */
251 { 0x0000, 0x0000 }, /* R247 */
252 { 0x0000, 0x0000 }, /* R248 */
253 { 0x0000, 0x0000 }, /* R249 */
254 { 0x0000, 0x0000 }, /* R250 */
255 { 0x0000, 0x0000 }, /* R251 */
256 { 0x0000, 0x0000 }, /* R252 */
257 { 0x0000, 0x0000 }, /* R253 */
258 { 0x0000, 0x0000 }, /* R254 */
259 { 0x0000, 0x0000 }, /* R255 */
260 { 0x000F, 0x0000 }, /* R256 - Chip Revision */
261 { 0x0074, 0x0074 }, /* R257 - Control Interface */
262 { 0x0000, 0x0000 }, /* R258 */
263 { 0x0000, 0x0000 }, /* R259 */
264 { 0x0000, 0x0000 }, /* R260 */
265 { 0x0000, 0x0000 }, /* R261 */
266 { 0x0000, 0x0000 }, /* R262 */
267 { 0x0000, 0x0000 }, /* R263 */
268 { 0x0000, 0x0000 }, /* R264 */
269 { 0x0000, 0x0000 }, /* R265 */
270 { 0x0000, 0x0000 }, /* R266 */
271 { 0x0000, 0x0000 }, /* R267 */
272 { 0x0000, 0x0000 }, /* R268 */
273 { 0x0000, 0x0000 }, /* R269 */
274 { 0x0000, 0x0000 }, /* R270 */
275 { 0x0000, 0x0000 }, /* R271 */
276 { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
277 { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
278 { 0x0000, 0x0000 }, /* R274 */
279 { 0x0000, 0x0000 }, /* R275 */
280 { 0x0000, 0x0000 }, /* R276 */
281 { 0x0000, 0x0000 }, /* R277 */
282 { 0x0000, 0x0000 }, /* R278 */
283 { 0x0000, 0x0000 }, /* R279 */
284 { 0x0000, 0x0000 }, /* R280 */
285 { 0x0000, 0x0000 }, /* R281 */
286 { 0x0000, 0x0000 }, /* R282 */
287 { 0x0000, 0x0000 }, /* R283 */
288 { 0x0000, 0x0000 }, /* R284 */
289 { 0x0000, 0x0000 }, /* R285 */
290 { 0x0000, 0x0000 }, /* R286 */
291 { 0x0000, 0x0000 }, /* R287 */
292 { 0x0000, 0x0000 }, /* R288 */
293 { 0x0000, 0x0000 }, /* R289 */
294 { 0x0000, 0x0000 }, /* R290 */
295 { 0x0000, 0x0000 }, /* R291 */
296 { 0x0000, 0x0000 }, /* R292 */
297 { 0x0000, 0x0000 }, /* R293 */
298 { 0x0000, 0x0000 }, /* R294 */
299 { 0x0000, 0x0000 }, /* R295 */
300 { 0x0000, 0x0000 }, /* R296 */
301 { 0x0000, 0x0000 }, /* R297 */
302 { 0x0000, 0x0000 }, /* R298 */
303 { 0x0000, 0x0000 }, /* R299 */
304 { 0x0000, 0x0000 }, /* R300 */
305 { 0x0000, 0x0000 }, /* R301 */
306 { 0x0000, 0x0000 }, /* R302 */
307 { 0x0000, 0x0000 }, /* R303 */
308 { 0x0000, 0x0000 }, /* R304 */
309 { 0x0000, 0x0000 }, /* R305 */
310 { 0x0000, 0x0000 }, /* R306 */
311 { 0x0000, 0x0000 }, /* R307 */
312 { 0x0000, 0x0000 }, /* R308 */
313 { 0x0000, 0x0000 }, /* R309 */
314 { 0x0000, 0x0000 }, /* R310 */
315 { 0x0000, 0x0000 }, /* R311 */
316 { 0x0000, 0x0000 }, /* R312 */
317 { 0x0000, 0x0000 }, /* R313 */
318 { 0x0000, 0x0000 }, /* R314 */
319 { 0x0000, 0x0000 }, /* R315 */
320 { 0x0000, 0x0000 }, /* R316 */
321 { 0x0000, 0x0000 }, /* R317 */
322 { 0x0000, 0x0000 }, /* R318 */
323 { 0x0000, 0x0000 }, /* R319 */
324 { 0x0000, 0x0000 }, /* R320 */
325 { 0x0000, 0x0000 }, /* R321 */
326 { 0x0000, 0x0000 }, /* R322 */
327 { 0x0000, 0x0000 }, /* R323 */
328 { 0x0000, 0x0000 }, /* R324 */
329 { 0x0000, 0x0000 }, /* R325 */
330 { 0x0000, 0x0000 }, /* R326 */
331 { 0x0000, 0x0000 }, /* R327 */
332 { 0x0000, 0x0000 }, /* R328 */
333 { 0x0000, 0x0000 }, /* R329 */
334 { 0x0000, 0x0000 }, /* R330 */
335 { 0x0000, 0x0000 }, /* R331 */
336 { 0x0000, 0x0000 }, /* R332 */
337 { 0x0000, 0x0000 }, /* R333 */
338 { 0x0000, 0x0000 }, /* R334 */
339 { 0x0000, 0x0000 }, /* R335 */
340 { 0x0000, 0x0000 }, /* R336 */
341 { 0x0000, 0x0000 }, /* R337 */
342 { 0x0000, 0x0000 }, /* R338 */
343 { 0x0000, 0x0000 }, /* R339 */
344 { 0x0000, 0x0000 }, /* R340 */
345 { 0x0000, 0x0000 }, /* R341 */
346 { 0x0000, 0x0000 }, /* R342 */
347 { 0x0000, 0x0000 }, /* R343 */
348 { 0x0000, 0x0000 }, /* R344 */
349 { 0x0000, 0x0000 }, /* R345 */
350 { 0x0000, 0x0000 }, /* R346 */
351 { 0x0000, 0x0000 }, /* R347 */
352 { 0x0000, 0x0000 }, /* R348 */
353 { 0x0000, 0x0000 }, /* R349 */
354 { 0x0000, 0x0000 }, /* R350 */
355 { 0x0000, 0x0000 }, /* R351 */
356 { 0x0000, 0x0000 }, /* R352 */
357 { 0x0000, 0x0000 }, /* R353 */
358 { 0x0000, 0x0000 }, /* R354 */
359 { 0x0000, 0x0000 }, /* R355 */
360 { 0x0000, 0x0000 }, /* R356 */
361 { 0x0000, 0x0000 }, /* R357 */
362 { 0x0000, 0x0000 }, /* R358 */
363 { 0x0000, 0x0000 }, /* R359 */
364 { 0x0000, 0x0000 }, /* R360 */
365 { 0x0000, 0x0000 }, /* R361 */
366 { 0x0000, 0x0000 }, /* R362 */
367 { 0x0000, 0x0000 }, /* R363 */
368 { 0x0000, 0x0000 }, /* R364 */
369 { 0x0000, 0x0000 }, /* R365 */
370 { 0x0000, 0x0000 }, /* R366 */
371 { 0x0000, 0x0000 }, /* R367 */
372 { 0x0000, 0x0000 }, /* R368 */
373 { 0x0000, 0x0000 }, /* R369 */
374 { 0x0000, 0x0000 }, /* R370 */
375 { 0x0000, 0x0000 }, /* R371 */
376 { 0x0000, 0x0000 }, /* R372 */
377 { 0x0000, 0x0000 }, /* R373 */
378 { 0x0000, 0x0000 }, /* R374 */
379 { 0x0000, 0x0000 }, /* R375 */
380 { 0x0000, 0x0000 }, /* R376 */
381 { 0x0000, 0x0000 }, /* R377 */
382 { 0x0000, 0x0000 }, /* R378 */
383 { 0x0000, 0x0000 }, /* R379 */
384 { 0x0000, 0x0000 }, /* R380 */
385 { 0x0000, 0x0000 }, /* R381 */
386 { 0x0000, 0x0000 }, /* R382 */
387 { 0x0000, 0x0000 }, /* R383 */
388 { 0x0000, 0x0000 }, /* R384 */
389 { 0x0000, 0x0000 }, /* R385 */
390 { 0x0000, 0x0000 }, /* R386 */
391 { 0x0000, 0x0000 }, /* R387 */
392 { 0x0000, 0x0000 }, /* R388 */
393 { 0x0000, 0x0000 }, /* R389 */
394 { 0x0000, 0x0000 }, /* R390 */
395 { 0x0000, 0x0000 }, /* R391 */
396 { 0x0000, 0x0000 }, /* R392 */
397 { 0x0000, 0x0000 }, /* R393 */
398 { 0x0000, 0x0000 }, /* R394 */
399 { 0x0000, 0x0000 }, /* R395 */
400 { 0x0000, 0x0000 }, /* R396 */
401 { 0x0000, 0x0000 }, /* R397 */
402 { 0x0000, 0x0000 }, /* R398 */
403 { 0x0000, 0x0000 }, /* R399 */
404 { 0x0000, 0x0000 }, /* R400 */
405 { 0x0000, 0x0000 }, /* R401 */
406 { 0x0000, 0x0000 }, /* R402 */
407 { 0x0000, 0x0000 }, /* R403 */
408 { 0x0000, 0x0000 }, /* R404 */
409 { 0x0000, 0x0000 }, /* R405 */
410 { 0x0000, 0x0000 }, /* R406 */
411 { 0x0000, 0x0000 }, /* R407 */
412 { 0x0000, 0x0000 }, /* R408 */
413 { 0x0000, 0x0000 }, /* R409 */
414 { 0x0000, 0x0000 }, /* R410 */
415 { 0x0000, 0x0000 }, /* R411 */
416 { 0x0000, 0x0000 }, /* R412 */
417 { 0x0000, 0x0000 }, /* R413 */
418 { 0x0000, 0x0000 }, /* R414 */
419 { 0x0000, 0x0000 }, /* R415 */
420 { 0x0000, 0x0000 }, /* R416 */
421 { 0x0000, 0x0000 }, /* R417 */
422 { 0x0000, 0x0000 }, /* R418 */
423 { 0x0000, 0x0000 }, /* R419 */
424 { 0x0000, 0x0000 }, /* R420 */
425 { 0x0000, 0x0000 }, /* R421 */
426 { 0x0000, 0x0000 }, /* R422 */
427 { 0x0000, 0x0000 }, /* R423 */
428 { 0x0000, 0x0000 }, /* R424 */
429 { 0x0000, 0x0000 }, /* R425 */
430 { 0x0000, 0x0000 }, /* R426 */
431 { 0x0000, 0x0000 }, /* R427 */
432 { 0x0000, 0x0000 }, /* R428 */
433 { 0x0000, 0x0000 }, /* R429 */
434 { 0x0000, 0x0000 }, /* R430 */
435 { 0x0000, 0x0000 }, /* R431 */
436 { 0x0000, 0x0000 }, /* R432 */
437 { 0x0000, 0x0000 }, /* R433 */
438 { 0x0000, 0x0000 }, /* R434 */
439 { 0x0000, 0x0000 }, /* R435 */
440 { 0x0000, 0x0000 }, /* R436 */
441 { 0x0000, 0x0000 }, /* R437 */
442 { 0x0000, 0x0000 }, /* R438 */
443 { 0x0000, 0x0000 }, /* R439 */
444 { 0x0000, 0x0000 }, /* R440 */
445 { 0x0000, 0x0000 }, /* R441 */
446 { 0x0000, 0x0000 }, /* R442 */
447 { 0x0000, 0x0000 }, /* R443 */
448 { 0x0000, 0x0000 }, /* R444 */
449 { 0x0000, 0x0000 }, /* R445 */
450 { 0x0000, 0x0000 }, /* R446 */
451 { 0x0000, 0x0000 }, /* R447 */
452 { 0x0000, 0x0000 }, /* R448 */
453 { 0x0000, 0x0000 }, /* R449 */
454 { 0x0000, 0x0000 }, /* R450 */
455 { 0x0000, 0x0000 }, /* R451 */
456 { 0x0000, 0x0000 }, /* R452 */
457 { 0x0000, 0x0000 }, /* R453 */
458 { 0x0000, 0x0000 }, /* R454 */
459 { 0x0000, 0x0000 }, /* R455 */
460 { 0x0000, 0x0000 }, /* R456 */
461 { 0x0000, 0x0000 }, /* R457 */
462 { 0x0000, 0x0000 }, /* R458 */
463 { 0x0000, 0x0000 }, /* R459 */
464 { 0x0000, 0x0000 }, /* R460 */
465 { 0x0000, 0x0000 }, /* R461 */
466 { 0x0000, 0x0000 }, /* R462 */
467 { 0x0000, 0x0000 }, /* R463 */
468 { 0x0000, 0x0000 }, /* R464 */
469 { 0x0000, 0x0000 }, /* R465 */
470 { 0x0000, 0x0000 }, /* R466 */
471 { 0x0000, 0x0000 }, /* R467 */
472 { 0x0000, 0x0000 }, /* R468 */
473 { 0x0000, 0x0000 }, /* R469 */
474 { 0x0000, 0x0000 }, /* R470 */
475 { 0x0000, 0x0000 }, /* R471 */
476 { 0x0000, 0x0000 }, /* R472 */
477 { 0x0000, 0x0000 }, /* R473 */
478 { 0x0000, 0x0000 }, /* R474 */
479 { 0x0000, 0x0000 }, /* R475 */
480 { 0x0000, 0x0000 }, /* R476 */
481 { 0x0000, 0x0000 }, /* R477 */
482 { 0x0000, 0x0000 }, /* R478 */
483 { 0x0000, 0x0000 }, /* R479 */
484 { 0x0000, 0x0000 }, /* R480 */
485 { 0x0000, 0x0000 }, /* R481 */
486 { 0x0000, 0x0000 }, /* R482 */
487 { 0x0000, 0x0000 }, /* R483 */
488 { 0x0000, 0x0000 }, /* R484 */
489 { 0x0000, 0x0000 }, /* R485 */
490 { 0x0000, 0x0000 }, /* R486 */
491 { 0x0000, 0x0000 }, /* R487 */
492 { 0x0000, 0x0000 }, /* R488 */
493 { 0x0000, 0x0000 }, /* R489 */
494 { 0x0000, 0x0000 }, /* R490 */
495 { 0x0000, 0x0000 }, /* R491 */
496 { 0x0000, 0x0000 }, /* R492 */
497 { 0x0000, 0x0000 }, /* R493 */
498 { 0x0000, 0x0000 }, /* R494 */
499 { 0x0000, 0x0000 }, /* R495 */
500 { 0x0000, 0x0000 }, /* R496 */
501 { 0x0000, 0x0000 }, /* R497 */
502 { 0x0000, 0x0000 }, /* R498 */
503 { 0x0000, 0x0000 }, /* R499 */
504 { 0x0000, 0x0000 }, /* R500 */
505 { 0x0000, 0x0000 }, /* R501 */
506 { 0x0000, 0x0000 }, /* R502 */
507 { 0x0000, 0x0000 }, /* R503 */
508 { 0x0000, 0x0000 }, /* R504 */
509 { 0x0000, 0x0000 }, /* R505 */
510 { 0x0000, 0x0000 }, /* R506 */
511 { 0x0000, 0x0000 }, /* R507 */
512 { 0x0000, 0x0000 }, /* R508 */
513 { 0x0000, 0x0000 }, /* R509 */
514 { 0x0000, 0x0000 }, /* R510 */
515 { 0x0000, 0x0000 }, /* R511 */
516 { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
517 { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
518 { 0x0000, 0x0000 }, /* R514 */
519 { 0x0000, 0x0000 }, /* R515 */
520 { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
521 { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
522 { 0x0000, 0x0000 }, /* R518 */
523 { 0x0000, 0x0000 }, /* R519 */
524 { 0x001F, 0x001F }, /* R520 - Clocking (1) */
525 { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
526 { 0x0000, 0x0000 }, /* R522 */
527 { 0x0000, 0x0000 }, /* R523 */
528 { 0x0000, 0x0000 }, /* R524 */
529 { 0x0000, 0x0000 }, /* R525 */
530 { 0x0000, 0x0000 }, /* R526 */
531 { 0x0000, 0x0000 }, /* R527 */
532 { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
533 { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
534 { 0x000F, 0x0000 }, /* R530 - Rate Status */
535 { 0x0000, 0x0000 }, /* R531 */
536 { 0x0000, 0x0000 }, /* R532 */
537 { 0x0000, 0x0000 }, /* R533 */
538 { 0x0000, 0x0000 }, /* R534 */
539 { 0x0000, 0x0000 }, /* R535 */
540 { 0x0000, 0x0000 }, /* R536 */
541 { 0x0000, 0x0000 }, /* R537 */
542 { 0x0000, 0x0000 }, /* R538 */
543 { 0x0000, 0x0000 }, /* R539 */
544 { 0x0000, 0x0000 }, /* R540 */
545 { 0x0000, 0x0000 }, /* R541 */
546 { 0x0000, 0x0000 }, /* R542 */
547 { 0x0000, 0x0000 }, /* R543 */
548 { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
549 { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
550 { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
551 { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
552 { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
553 { 0x0000, 0x0000 }, /* R549 */
554 { 0x0000, 0x0000 }, /* R550 */
555 { 0x0000, 0x0000 }, /* R551 */
556 { 0x0000, 0x0000 }, /* R552 */
557 { 0x0000, 0x0000 }, /* R553 */
558 { 0x0000, 0x0000 }, /* R554 */
559 { 0x0000, 0x0000 }, /* R555 */
560 { 0x0000, 0x0000 }, /* R556 */
561 { 0x0000, 0x0000 }, /* R557 */
562 { 0x0000, 0x0000 }, /* R558 */
563 { 0x0000, 0x0000 }, /* R559 */
564 { 0x0000, 0x0000 }, /* R560 */
565 { 0x0000, 0x0000 }, /* R561 */
566 { 0x0000, 0x0000 }, /* R562 */
567 { 0x0000, 0x0000 }, /* R563 */
568 { 0x0000, 0x0000 }, /* R564 */
569 { 0x0000, 0x0000 }, /* R565 */
570 { 0x0000, 0x0000 }, /* R566 */
571 { 0x0000, 0x0000 }, /* R567 */
572 { 0x0000, 0x0000 }, /* R568 */
573 { 0x0000, 0x0000 }, /* R569 */
574 { 0x0000, 0x0000 }, /* R570 */
575 { 0x0000, 0x0000 }, /* R571 */
576 { 0x0000, 0x0000 }, /* R572 */
577 { 0x0000, 0x0000 }, /* R573 */
578 { 0x0000, 0x0000 }, /* R574 */
579 { 0x0000, 0x0000 }, /* R575 */
580 { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
581 { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
582 { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
583 { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
584 { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
585 { 0x0000, 0x0000 }, /* R581 */
586 { 0x0000, 0x0000 }, /* R582 */
587 { 0x0000, 0x0000 }, /* R583 */
588 { 0x0000, 0x0000 }, /* R584 */
589 { 0x0000, 0x0000 }, /* R585 */
590 { 0x0000, 0x0000 }, /* R586 */
591 { 0x0000, 0x0000 }, /* R587 */
592 { 0x0000, 0x0000 }, /* R588 */
593 { 0x0000, 0x0000 }, /* R589 */
594 { 0x0000, 0x0000 }, /* R590 */
595 { 0x0000, 0x0000 }, /* R591 */
596 { 0x0000, 0x0000 }, /* R592 */
597 { 0x0000, 0x0000 }, /* R593 */
598 { 0x0000, 0x0000 }, /* R594 */
599 { 0x0000, 0x0000 }, /* R595 */
600 { 0x0000, 0x0000 }, /* R596 */
601 { 0x0000, 0x0000 }, /* R597 */
602 { 0x0000, 0x0000 }, /* R598 */
603 { 0x0000, 0x0000 }, /* R599 */
604 { 0x0000, 0x0000 }, /* R600 */
605 { 0x0000, 0x0000 }, /* R601 */
606 { 0x0000, 0x0000 }, /* R602 */
607 { 0x0000, 0x0000 }, /* R603 */
608 { 0x0000, 0x0000 }, /* R604 */
609 { 0x0000, 0x0000 }, /* R605 */
610 { 0x0000, 0x0000 }, /* R606 */
611 { 0x0000, 0x0000 }, /* R607 */
612 { 0x0000, 0x0000 }, /* R608 */
613 { 0x0000, 0x0000 }, /* R609 */
614 { 0x0000, 0x0000 }, /* R610 */
615 { 0x0000, 0x0000 }, /* R611 */
616 { 0x0000, 0x0000 }, /* R612 */
617 { 0x0000, 0x0000 }, /* R613 */
618 { 0x0000, 0x0000 }, /* R614 */
619 { 0x0000, 0x0000 }, /* R615 */
620 { 0x0000, 0x0000 }, /* R616 */
621 { 0x0000, 0x0000 }, /* R617 */
622 { 0x0000, 0x0000 }, /* R618 */
623 { 0x0000, 0x0000 }, /* R619 */
624 { 0x0000, 0x0000 }, /* R620 */
625 { 0x0000, 0x0000 }, /* R621 */
626 { 0x0000, 0x0000 }, /* R622 */
627 { 0x0000, 0x0000 }, /* R623 */
628 { 0x0000, 0x0000 }, /* R624 */
629 { 0x0000, 0x0000 }, /* R625 */
630 { 0x0000, 0x0000 }, /* R626 */
631 { 0x0000, 0x0000 }, /* R627 */
632 { 0x0000, 0x0000 }, /* R628 */
633 { 0x0000, 0x0000 }, /* R629 */
634 { 0x0000, 0x0000 }, /* R630 */
635 { 0x0000, 0x0000 }, /* R631 */
636 { 0x0000, 0x0000 }, /* R632 */
637 { 0x0000, 0x0000 }, /* R633 */
638 { 0x0000, 0x0000 }, /* R634 */
639 { 0x0000, 0x0000 }, /* R635 */
640 { 0x0000, 0x0000 }, /* R636 */
641 { 0x0000, 0x0000 }, /* R637 */
642 { 0x0000, 0x0000 }, /* R638 */
643 { 0x0000, 0x0000 }, /* R639 */
644 { 0x0000, 0x0000 }, /* R640 */
645 { 0x0000, 0x0000 }, /* R641 */
646 { 0x0000, 0x0000 }, /* R642 */
647 { 0x0000, 0x0000 }, /* R643 */
648 { 0x0000, 0x0000 }, /* R644 */
649 { 0x0000, 0x0000 }, /* R645 */
650 { 0x0000, 0x0000 }, /* R646 */
651 { 0x0000, 0x0000 }, /* R647 */
652 { 0x0000, 0x0000 }, /* R648 */
653 { 0x0000, 0x0000 }, /* R649 */
654 { 0x0000, 0x0000 }, /* R650 */
655 { 0x0000, 0x0000 }, /* R651 */
656 { 0x0000, 0x0000 }, /* R652 */
657 { 0x0000, 0x0000 }, /* R653 */
658 { 0x0000, 0x0000 }, /* R654 */
659 { 0x0000, 0x0000 }, /* R655 */
660 { 0x0000, 0x0000 }, /* R656 */
661 { 0x0000, 0x0000 }, /* R657 */
662 { 0x0000, 0x0000 }, /* R658 */
663 { 0x0000, 0x0000 }, /* R659 */
664 { 0x0000, 0x0000 }, /* R660 */
665 { 0x0000, 0x0000 }, /* R661 */
666 { 0x0000, 0x0000 }, /* R662 */
667 { 0x0000, 0x0000 }, /* R663 */
668 { 0x0000, 0x0000 }, /* R664 */
669 { 0x0000, 0x0000 }, /* R665 */
670 { 0x0000, 0x0000 }, /* R666 */
671 { 0x0000, 0x0000 }, /* R667 */
672 { 0x0000, 0x0000 }, /* R668 */
673 { 0x0000, 0x0000 }, /* R669 */
674 { 0x0000, 0x0000 }, /* R670 */
675 { 0x0000, 0x0000 }, /* R671 */
676 { 0x0000, 0x0000 }, /* R672 */
677 { 0x0000, 0x0000 }, /* R673 */
678 { 0x0000, 0x0000 }, /* R674 */
679 { 0x0000, 0x0000 }, /* R675 */
680 { 0x0000, 0x0000 }, /* R676 */
681 { 0x0000, 0x0000 }, /* R677 */
682 { 0x0000, 0x0000 }, /* R678 */
683 { 0x0000, 0x0000 }, /* R679 */
684 { 0x0000, 0x0000 }, /* R680 */
685 { 0x0000, 0x0000 }, /* R681 */
686 { 0x0000, 0x0000 }, /* R682 */
687 { 0x0000, 0x0000 }, /* R683 */
688 { 0x0000, 0x0000 }, /* R684 */
689 { 0x0000, 0x0000 }, /* R685 */
690 { 0x0000, 0x0000 }, /* R686 */
691 { 0x0000, 0x0000 }, /* R687 */
692 { 0x0000, 0x0000 }, /* R688 */
693 { 0x0000, 0x0000 }, /* R689 */
694 { 0x0000, 0x0000 }, /* R690 */
695 { 0x0000, 0x0000 }, /* R691 */
696 { 0x0000, 0x0000 }, /* R692 */
697 { 0x0000, 0x0000 }, /* R693 */
698 { 0x0000, 0x0000 }, /* R694 */
699 { 0x0000, 0x0000 }, /* R695 */
700 { 0x0000, 0x0000 }, /* R696 */
701 { 0x0000, 0x0000 }, /* R697 */
702 { 0x0000, 0x0000 }, /* R698 */
703 { 0x0000, 0x0000 }, /* R699 */
704 { 0x0000, 0x0000 }, /* R700 */
705 { 0x0000, 0x0000 }, /* R701 */
706 { 0x0000, 0x0000 }, /* R702 */
707 { 0x0000, 0x0000 }, /* R703 */
708 { 0x0000, 0x0000 }, /* R704 */
709 { 0x0000, 0x0000 }, /* R705 */
710 { 0x0000, 0x0000 }, /* R706 */
711 { 0x0000, 0x0000 }, /* R707 */
712 { 0x0000, 0x0000 }, /* R708 */
713 { 0x0000, 0x0000 }, /* R709 */
714 { 0x0000, 0x0000 }, /* R710 */
715 { 0x0000, 0x0000 }, /* R711 */
716 { 0x0000, 0x0000 }, /* R712 */
717 { 0x0000, 0x0000 }, /* R713 */
718 { 0x0000, 0x0000 }, /* R714 */
719 { 0x0000, 0x0000 }, /* R715 */
720 { 0x0000, 0x0000 }, /* R716 */
721 { 0x0000, 0x0000 }, /* R717 */
722 { 0x0000, 0x0000 }, /* R718 */
723 { 0x0000, 0x0000 }, /* R719 */
724 { 0x0000, 0x0000 }, /* R720 */
725 { 0x0000, 0x0000 }, /* R721 */
726 { 0x0000, 0x0000 }, /* R722 */
727 { 0x0000, 0x0000 }, /* R723 */
728 { 0x0000, 0x0000 }, /* R724 */
729 { 0x0000, 0x0000 }, /* R725 */
730 { 0x0000, 0x0000 }, /* R726 */
731 { 0x0000, 0x0000 }, /* R727 */
732 { 0x0000, 0x0000 }, /* R728 */
733 { 0x0000, 0x0000 }, /* R729 */
734 { 0x0000, 0x0000 }, /* R730 */
735 { 0x0000, 0x0000 }, /* R731 */
736 { 0x0000, 0x0000 }, /* R732 */
737 { 0x0000, 0x0000 }, /* R733 */
738 { 0x0000, 0x0000 }, /* R734 */
739 { 0x0000, 0x0000 }, /* R735 */
740 { 0x0000, 0x0000 }, /* R736 */
741 { 0x0000, 0x0000 }, /* R737 */
742 { 0x0000, 0x0000 }, /* R738 */
743 { 0x0000, 0x0000 }, /* R739 */
744 { 0x0000, 0x0000 }, /* R740 */
745 { 0x0000, 0x0000 }, /* R741 */
746 { 0x0000, 0x0000 }, /* R742 */
747 { 0x0000, 0x0000 }, /* R743 */
748 { 0x0000, 0x0000 }, /* R744 */
749 { 0x0000, 0x0000 }, /* R745 */
750 { 0x0000, 0x0000 }, /* R746 */
751 { 0x0000, 0x0000 }, /* R747 */
752 { 0x0000, 0x0000 }, /* R748 */
753 { 0x0000, 0x0000 }, /* R749 */
754 { 0x0000, 0x0000 }, /* R750 */
755 { 0x0000, 0x0000 }, /* R751 */
756 { 0x0000, 0x0000 }, /* R752 */
757 { 0x0000, 0x0000 }, /* R753 */
758 { 0x0000, 0x0000 }, /* R754 */
759 { 0x0000, 0x0000 }, /* R755 */
760 { 0x0000, 0x0000 }, /* R756 */
761 { 0x0000, 0x0000 }, /* R757 */
762 { 0x0000, 0x0000 }, /* R758 */
763 { 0x0000, 0x0000 }, /* R759 */
764 { 0x0000, 0x0000 }, /* R760 */
765 { 0x0000, 0x0000 }, /* R761 */
766 { 0x0000, 0x0000 }, /* R762 */
767 { 0x0000, 0x0000 }, /* R763 */
768 { 0x0000, 0x0000 }, /* R764 */
769 { 0x0000, 0x0000 }, /* R765 */
770 { 0x0000, 0x0000 }, /* R766 */
771 { 0x0000, 0x0000 }, /* R767 */
772 { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
773 { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
774 { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
775 { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
776 { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
777 { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
778 { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
779 { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
780 { 0x0000, 0x0000 }, /* R776 */
781 { 0x0000, 0x0000 }, /* R777 */
782 { 0x0000, 0x0000 }, /* R778 */
783 { 0x0000, 0x0000 }, /* R779 */
784 { 0x0000, 0x0000 }, /* R780 */
785 { 0x0000, 0x0000 }, /* R781 */
786 { 0x0000, 0x0000 }, /* R782 */
787 { 0x0000, 0x0000 }, /* R783 */
788 { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
789 { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
790 { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
791 { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
792 { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
793 { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
794 { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
795 { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
796 { 0x0000, 0x0000 }, /* R792 */
797 { 0x0000, 0x0000 }, /* R793 */
798 { 0x0000, 0x0000 }, /* R794 */
799 { 0x0000, 0x0000 }, /* R795 */
800 { 0x0000, 0x0000 }, /* R796 */
801 { 0x0000, 0x0000 }, /* R797 */
802 { 0x0000, 0x0000 }, /* R798 */
803 { 0x0000, 0x0000 }, /* R799 */
804 { 0x0000, 0x0000 }, /* R800 */
805 { 0x0000, 0x0000 }, /* R801 */
806 { 0x0000, 0x0000 }, /* R802 */
807 { 0x0000, 0x0000 }, /* R803 */
808 { 0x0000, 0x0000 }, /* R804 */
809 { 0x0000, 0x0000 }, /* R805 */
810 { 0x0000, 0x0000 }, /* R806 */
811 { 0x0000, 0x0000 }, /* R807 */
812 { 0x0000, 0x0000 }, /* R808 */
813 { 0x0000, 0x0000 }, /* R809 */
814 { 0x0000, 0x0000 }, /* R810 */
815 { 0x0000, 0x0000 }, /* R811 */
816 { 0x0000, 0x0000 }, /* R812 */
817 { 0x0000, 0x0000 }, /* R813 */
818 { 0x0000, 0x0000 }, /* R814 */
819 { 0x0000, 0x0000 }, /* R815 */
820 { 0x0000, 0x0000 }, /* R816 */
821 { 0x0000, 0x0000 }, /* R817 */
822 { 0x0000, 0x0000 }, /* R818 */
823 { 0x0000, 0x0000 }, /* R819 */
824 { 0x0000, 0x0000 }, /* R820 */
825 { 0x0000, 0x0000 }, /* R821 */
826 { 0x0000, 0x0000 }, /* R822 */
827 { 0x0000, 0x0000 }, /* R823 */
828 { 0x0000, 0x0000 }, /* R824 */
829 { 0x0000, 0x0000 }, /* R825 */
830 { 0x0000, 0x0000 }, /* R826 */
831 { 0x0000, 0x0000 }, /* R827 */
832 { 0x0000, 0x0000 }, /* R828 */
833 { 0x0000, 0x0000 }, /* R829 */
834 { 0x0000, 0x0000 }, /* R830 */
835 { 0x0000, 0x0000 }, /* R831 */
836 { 0x0000, 0x0000 }, /* R832 */
837 { 0x0000, 0x0000 }, /* R833 */
838 { 0x0000, 0x0000 }, /* R834 */
839 { 0x0000, 0x0000 }, /* R835 */
840 { 0x0000, 0x0000 }, /* R836 */
841 { 0x0000, 0x0000 }, /* R837 */
842 { 0x0000, 0x0000 }, /* R838 */
843 { 0x0000, 0x0000 }, /* R839 */
844 { 0x0000, 0x0000 }, /* R840 */
845 { 0x0000, 0x0000 }, /* R841 */
846 { 0x0000, 0x0000 }, /* R842 */
847 { 0x0000, 0x0000 }, /* R843 */
848 { 0x0000, 0x0000 }, /* R844 */
849 { 0x0000, 0x0000 }, /* R845 */
850 { 0x0000, 0x0000 }, /* R846 */
851 { 0x0000, 0x0000 }, /* R847 */
852 { 0x0000, 0x0000 }, /* R848 */
853 { 0x0000, 0x0000 }, /* R849 */
854 { 0x0000, 0x0000 }, /* R850 */
855 { 0x0000, 0x0000 }, /* R851 */
856 { 0x0000, 0x0000 }, /* R852 */
857 { 0x0000, 0x0000 }, /* R853 */
858 { 0x0000, 0x0000 }, /* R854 */
859 { 0x0000, 0x0000 }, /* R855 */
860 { 0x0000, 0x0000 }, /* R856 */
861 { 0x0000, 0x0000 }, /* R857 */
862 { 0x0000, 0x0000 }, /* R858 */
863 { 0x0000, 0x0000 }, /* R859 */
864 { 0x0000, 0x0000 }, /* R860 */
865 { 0x0000, 0x0000 }, /* R861 */
866 { 0x0000, 0x0000 }, /* R862 */
867 { 0x0000, 0x0000 }, /* R863 */
868 { 0x0000, 0x0000 }, /* R864 */
869 { 0x0000, 0x0000 }, /* R865 */
870 { 0x0000, 0x0000 }, /* R866 */
871 { 0x0000, 0x0000 }, /* R867 */
872 { 0x0000, 0x0000 }, /* R868 */
873 { 0x0000, 0x0000 }, /* R869 */
874 { 0x0000, 0x0000 }, /* R870 */
875 { 0x0000, 0x0000 }, /* R871 */
876 { 0x0000, 0x0000 }, /* R872 */
877 { 0x0000, 0x0000 }, /* R873 */
878 { 0x0000, 0x0000 }, /* R874 */
879 { 0x0000, 0x0000 }, /* R875 */
880 { 0x0000, 0x0000 }, /* R876 */
881 { 0x0000, 0x0000 }, /* R877 */
882 { 0x0000, 0x0000 }, /* R878 */
883 { 0x0000, 0x0000 }, /* R879 */
884 { 0x0000, 0x0000 }, /* R880 */
885 { 0x0000, 0x0000 }, /* R881 */
886 { 0x0000, 0x0000 }, /* R882 */
887 { 0x0000, 0x0000 }, /* R883 */
888 { 0x0000, 0x0000 }, /* R884 */
889 { 0x0000, 0x0000 }, /* R885 */
890 { 0x0000, 0x0000 }, /* R886 */
891 { 0x0000, 0x0000 }, /* R887 */
892 { 0x0000, 0x0000 }, /* R888 */
893 { 0x0000, 0x0000 }, /* R889 */
894 { 0x0000, 0x0000 }, /* R890 */
895 { 0x0000, 0x0000 }, /* R891 */
896 { 0x0000, 0x0000 }, /* R892 */
897 { 0x0000, 0x0000 }, /* R893 */
898 { 0x0000, 0x0000 }, /* R894 */
899 { 0x0000, 0x0000 }, /* R895 */
900 { 0x0000, 0x0000 }, /* R896 */
901 { 0x0000, 0x0000 }, /* R897 */
902 { 0x0000, 0x0000 }, /* R898 */
903 { 0x0000, 0x0000 }, /* R899 */
904 { 0x0000, 0x0000 }, /* R900 */
905 { 0x0000, 0x0000 }, /* R901 */
906 { 0x0000, 0x0000 }, /* R902 */
907 { 0x0000, 0x0000 }, /* R903 */
908 { 0x0000, 0x0000 }, /* R904 */
909 { 0x0000, 0x0000 }, /* R905 */
910 { 0x0000, 0x0000 }, /* R906 */
911 { 0x0000, 0x0000 }, /* R907 */
912 { 0x0000, 0x0000 }, /* R908 */
913 { 0x0000, 0x0000 }, /* R909 */
914 { 0x0000, 0x0000 }, /* R910 */
915 { 0x0000, 0x0000 }, /* R911 */
916 { 0x0000, 0x0000 }, /* R912 */
917 { 0x0000, 0x0000 }, /* R913 */
918 { 0x0000, 0x0000 }, /* R914 */
919 { 0x0000, 0x0000 }, /* R915 */
920 { 0x0000, 0x0000 }, /* R916 */
921 { 0x0000, 0x0000 }, /* R917 */
922 { 0x0000, 0x0000 }, /* R918 */
923 { 0x0000, 0x0000 }, /* R919 */
924 { 0x0000, 0x0000 }, /* R920 */
925 { 0x0000, 0x0000 }, /* R921 */
926 { 0x0000, 0x0000 }, /* R922 */
927 { 0x0000, 0x0000 }, /* R923 */
928 { 0x0000, 0x0000 }, /* R924 */
929 { 0x0000, 0x0000 }, /* R925 */
930 { 0x0000, 0x0000 }, /* R926 */
931 { 0x0000, 0x0000 }, /* R927 */
932 { 0x0000, 0x0000 }, /* R928 */
933 { 0x0000, 0x0000 }, /* R929 */
934 { 0x0000, 0x0000 }, /* R930 */
935 { 0x0000, 0x0000 }, /* R931 */
936 { 0x0000, 0x0000 }, /* R932 */
937 { 0x0000, 0x0000 }, /* R933 */
938 { 0x0000, 0x0000 }, /* R934 */
939 { 0x0000, 0x0000 }, /* R935 */
940 { 0x0000, 0x0000 }, /* R936 */
941 { 0x0000, 0x0000 }, /* R937 */
942 { 0x0000, 0x0000 }, /* R938 */
943 { 0x0000, 0x0000 }, /* R939 */
944 { 0x0000, 0x0000 }, /* R940 */
945 { 0x0000, 0x0000 }, /* R941 */
946 { 0x0000, 0x0000 }, /* R942 */
947 { 0x0000, 0x0000 }, /* R943 */
948 { 0x0000, 0x0000 }, /* R944 */
949 { 0x0000, 0x0000 }, /* R945 */
950 { 0x0000, 0x0000 }, /* R946 */
951 { 0x0000, 0x0000 }, /* R947 */
952 { 0x0000, 0x0000 }, /* R948 */
953 { 0x0000, 0x0000 }, /* R949 */
954 { 0x0000, 0x0000 }, /* R950 */
955 { 0x0000, 0x0000 }, /* R951 */
956 { 0x0000, 0x0000 }, /* R952 */
957 { 0x0000, 0x0000 }, /* R953 */
958 { 0x0000, 0x0000 }, /* R954 */
959 { 0x0000, 0x0000 }, /* R955 */
960 { 0x0000, 0x0000 }, /* R956 */
961 { 0x0000, 0x0000 }, /* R957 */
962 { 0x0000, 0x0000 }, /* R958 */
963 { 0x0000, 0x0000 }, /* R959 */
964 { 0x0000, 0x0000 }, /* R960 */
965 { 0x0000, 0x0000 }, /* R961 */
966 { 0x0000, 0x0000 }, /* R962 */
967 { 0x0000, 0x0000 }, /* R963 */
968 { 0x0000, 0x0000 }, /* R964 */
969 { 0x0000, 0x0000 }, /* R965 */
970 { 0x0000, 0x0000 }, /* R966 */
971 { 0x0000, 0x0000 }, /* R967 */
972 { 0x0000, 0x0000 }, /* R968 */
973 { 0x0000, 0x0000 }, /* R969 */
974 { 0x0000, 0x0000 }, /* R970 */
975 { 0x0000, 0x0000 }, /* R971 */
976 { 0x0000, 0x0000 }, /* R972 */
977 { 0x0000, 0x0000 }, /* R973 */
978 { 0x0000, 0x0000 }, /* R974 */
979 { 0x0000, 0x0000 }, /* R975 */
980 { 0x0000, 0x0000 }, /* R976 */
981 { 0x0000, 0x0000 }, /* R977 */
982 { 0x0000, 0x0000 }, /* R978 */
983 { 0x0000, 0x0000 }, /* R979 */
984 { 0x0000, 0x0000 }, /* R980 */
985 { 0x0000, 0x0000 }, /* R981 */
986 { 0x0000, 0x0000 }, /* R982 */
987 { 0x0000, 0x0000 }, /* R983 */
988 { 0x0000, 0x0000 }, /* R984 */
989 { 0x0000, 0x0000 }, /* R985 */
990 { 0x0000, 0x0000 }, /* R986 */
991 { 0x0000, 0x0000 }, /* R987 */
992 { 0x0000, 0x0000 }, /* R988 */
993 { 0x0000, 0x0000 }, /* R989 */
994 { 0x0000, 0x0000 }, /* R990 */
995 { 0x0000, 0x0000 }, /* R991 */
996 { 0x0000, 0x0000 }, /* R992 */
997 { 0x0000, 0x0000 }, /* R993 */
998 { 0x0000, 0x0000 }, /* R994 */
999 { 0x0000, 0x0000 }, /* R995 */
1000 { 0x0000, 0x0000 }, /* R996 */
1001 { 0x0000, 0x0000 }, /* R997 */
1002 { 0x0000, 0x0000 }, /* R998 */
1003 { 0x0000, 0x0000 }, /* R999 */
1004 { 0x0000, 0x0000 }, /* R1000 */
1005 { 0x0000, 0x0000 }, /* R1001 */
1006 { 0x0000, 0x0000 }, /* R1002 */
1007 { 0x0000, 0x0000 }, /* R1003 */
1008 { 0x0000, 0x0000 }, /* R1004 */
1009 { 0x0000, 0x0000 }, /* R1005 */
1010 { 0x0000, 0x0000 }, /* R1006 */
1011 { 0x0000, 0x0000 }, /* R1007 */
1012 { 0x0000, 0x0000 }, /* R1008 */
1013 { 0x0000, 0x0000 }, /* R1009 */
1014 { 0x0000, 0x0000 }, /* R1010 */
1015 { 0x0000, 0x0000 }, /* R1011 */
1016 { 0x0000, 0x0000 }, /* R1012 */
1017 { 0x0000, 0x0000 }, /* R1013 */
1018 { 0x0000, 0x0000 }, /* R1014 */
1019 { 0x0000, 0x0000 }, /* R1015 */
1020 { 0x0000, 0x0000 }, /* R1016 */
1021 { 0x0000, 0x0000 }, /* R1017 */
1022 { 0x0000, 0x0000 }, /* R1018 */
1023 { 0x0000, 0x0000 }, /* R1019 */
1024 { 0x0000, 0x0000 }, /* R1020 */
1025 { 0x0000, 0x0000 }, /* R1021 */
1026 { 0x0000, 0x0000 }, /* R1022 */
1027 { 0x0000, 0x0000 }, /* R1023 */
1028 { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
1029 { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
1030 { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
1031 { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
1032 { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
1033 { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
1034 { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
1035 { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
1036 { 0x0000, 0x0000 }, /* R1032 */
1037 { 0x0000, 0x0000 }, /* R1033 */
1038 { 0x0000, 0x0000 }, /* R1034 */
1039 { 0x0000, 0x0000 }, /* R1035 */
1040 { 0x0000, 0x0000 }, /* R1036 */
1041 { 0x0000, 0x0000 }, /* R1037 */
1042 { 0x0000, 0x0000 }, /* R1038 */
1043 { 0x0000, 0x0000 }, /* R1039 */
1044 { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
1045 { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
1046 { 0x0000, 0x0000 }, /* R1042 */
1047 { 0x0000, 0x0000 }, /* R1043 */
1048 { 0x0000, 0x0000 }, /* R1044 */
1049 { 0x0000, 0x0000 }, /* R1045 */
1050 { 0x0000, 0x0000 }, /* R1046 */
1051 { 0x0000, 0x0000 }, /* R1047 */
1052 { 0x0000, 0x0000 }, /* R1048 */
1053 { 0x0000, 0x0000 }, /* R1049 */
1054 { 0x0000, 0x0000 }, /* R1050 */
1055 { 0x0000, 0x0000 }, /* R1051 */
1056 { 0x0000, 0x0000 }, /* R1052 */
1057 { 0x0000, 0x0000 }, /* R1053 */
1058 { 0x0000, 0x0000 }, /* R1054 */
1059 { 0x0000, 0x0000 }, /* R1055 */
1060 { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
1061 { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
1062 { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
1063 { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
1064 { 0x0000, 0x0000 }, /* R1060 */
1065 { 0x0000, 0x0000 }, /* R1061 */
1066 { 0x0000, 0x0000 }, /* R1062 */
1067 { 0x0000, 0x0000 }, /* R1063 */
1068 { 0x0000, 0x0000 }, /* R1064 */
1069 { 0x0000, 0x0000 }, /* R1065 */
1070 { 0x0000, 0x0000 }, /* R1066 */
1071 { 0x0000, 0x0000 }, /* R1067 */
1072 { 0x0000, 0x0000 }, /* R1068 */
1073 { 0x0000, 0x0000 }, /* R1069 */
1074 { 0x0000, 0x0000 }, /* R1070 */
1075 { 0x0000, 0x0000 }, /* R1071 */
1076 { 0x0000, 0x0000 }, /* R1072 */
1077 { 0x0000, 0x0000 }, /* R1073 */
1078 { 0x0000, 0x0000 }, /* R1074 */
1079 { 0x0000, 0x0000 }, /* R1075 */
1080 { 0x0000, 0x0000 }, /* R1076 */
1081 { 0x0000, 0x0000 }, /* R1077 */
1082 { 0x0000, 0x0000 }, /* R1078 */
1083 { 0x0000, 0x0000 }, /* R1079 */
1084 { 0x0000, 0x0000 }, /* R1080 */
1085 { 0x0000, 0x0000 }, /* R1081 */
1086 { 0x0000, 0x0000 }, /* R1082 */
1087 { 0x0000, 0x0000 }, /* R1083 */
1088 { 0x0000, 0x0000 }, /* R1084 */
1089 { 0x0000, 0x0000 }, /* R1085 */
1090 { 0x0000, 0x0000 }, /* R1086 */
1091 { 0x0000, 0x0000 }, /* R1087 */
1092 { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
1093 { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
1094 { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
1095 { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
1096 { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
1097 { 0x0000, 0x0000 }, /* R1093 */
1098 { 0x0000, 0x0000 }, /* R1094 */
1099 { 0x0000, 0x0000 }, /* R1095 */
1100 { 0x0000, 0x0000 }, /* R1096 */
1101 { 0x0000, 0x0000 }, /* R1097 */
1102 { 0x0000, 0x0000 }, /* R1098 */
1103 { 0x0000, 0x0000 }, /* R1099 */
1104 { 0x0000, 0x0000 }, /* R1100 */
1105 { 0x0000, 0x0000 }, /* R1101 */
1106 { 0x0000, 0x0000 }, /* R1102 */
1107 { 0x0000, 0x0000 }, /* R1103 */
1108 { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
1109 { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
1110 { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
1111 { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
1112 { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
1113 { 0x0000, 0x0000 }, /* R1109 */
1114 { 0x0000, 0x0000 }, /* R1110 */
1115 { 0x0000, 0x0000 }, /* R1111 */
1116 { 0x0000, 0x0000 }, /* R1112 */
1117 { 0x0000, 0x0000 }, /* R1113 */
1118 { 0x0000, 0x0000 }, /* R1114 */
1119 { 0x0000, 0x0000 }, /* R1115 */
1120 { 0x0000, 0x0000 }, /* R1116 */
1121 { 0x0000, 0x0000 }, /* R1117 */
1122 { 0x0000, 0x0000 }, /* R1118 */
1123 { 0x0000, 0x0000 }, /* R1119 */
1124 { 0x0000, 0x0000 }, /* R1120 */
1125 { 0x0000, 0x0000 }, /* R1121 */
1126 { 0x0000, 0x0000 }, /* R1122 */
1127 { 0x0000, 0x0000 }, /* R1123 */
1128 { 0x0000, 0x0000 }, /* R1124 */
1129 { 0x0000, 0x0000 }, /* R1125 */
1130 { 0x0000, 0x0000 }, /* R1126 */
1131 { 0x0000, 0x0000 }, /* R1127 */
1132 { 0x0000, 0x0000 }, /* R1128 */
1133 { 0x0000, 0x0000 }, /* R1129 */
1134 { 0x0000, 0x0000 }, /* R1130 */
1135 { 0x0000, 0x0000 }, /* R1131 */
1136 { 0x0000, 0x0000 }, /* R1132 */
1137 { 0x0000, 0x0000 }, /* R1133 */
1138 { 0x0000, 0x0000 }, /* R1134 */
1139 { 0x0000, 0x0000 }, /* R1135 */
1140 { 0x0000, 0x0000 }, /* R1136 */
1141 { 0x0000, 0x0000 }, /* R1137 */
1142 { 0x0000, 0x0000 }, /* R1138 */
1143 { 0x0000, 0x0000 }, /* R1139 */
1144 { 0x0000, 0x0000 }, /* R1140 */
1145 { 0x0000, 0x0000 }, /* R1141 */
1146 { 0x0000, 0x0000 }, /* R1142 */
1147 { 0x0000, 0x0000 }, /* R1143 */
1148 { 0x0000, 0x0000 }, /* R1144 */
1149 { 0x0000, 0x0000 }, /* R1145 */
1150 { 0x0000, 0x0000 }, /* R1146 */
1151 { 0x0000, 0x0000 }, /* R1147 */
1152 { 0x0000, 0x0000 }, /* R1148 */
1153 { 0x0000, 0x0000 }, /* R1149 */
1154 { 0x0000, 0x0000 }, /* R1150 */
1155 { 0x0000, 0x0000 }, /* R1151 */
1156 { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1157 { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1158 { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1159 { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1160 { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1161 { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1162 { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1163 { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1164 { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1165 { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1166 { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1167 { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1168 { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1169 { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1170 { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1171 { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1172 { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1173 { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1174 { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1175 { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1176 { 0x0000, 0x0000 }, /* R1172 */
1177 { 0x0000, 0x0000 }, /* R1173 */
1178 { 0x0000, 0x0000 }, /* R1174 */
1179 { 0x0000, 0x0000 }, /* R1175 */
1180 { 0x0000, 0x0000 }, /* R1176 */
1181 { 0x0000, 0x0000 }, /* R1177 */
1182 { 0x0000, 0x0000 }, /* R1178 */
1183 { 0x0000, 0x0000 }, /* R1179 */
1184 { 0x0000, 0x0000 }, /* R1180 */
1185 { 0x0000, 0x0000 }, /* R1181 */
1186 { 0x0000, 0x0000 }, /* R1182 */
1187 { 0x0000, 0x0000 }, /* R1183 */
1188 { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1189 { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1190 { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1191 { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1192 { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1193 { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1194 { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1195 { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1196 { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1197 { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1198 { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1199 { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1200 { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1201 { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1202 { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1203 { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1204 { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1205 { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1206 { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1207 { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1208 { 0x0000, 0x0000 }, /* R1204 */
1209 { 0x0000, 0x0000 }, /* R1205 */
1210 { 0x0000, 0x0000 }, /* R1206 */
1211 { 0x0000, 0x0000 }, /* R1207 */
1212 { 0x0000, 0x0000 }, /* R1208 */
1213 { 0x0000, 0x0000 }, /* R1209 */
1214 { 0x0000, 0x0000 }, /* R1210 */
1215 { 0x0000, 0x0000 }, /* R1211 */
1216 { 0x0000, 0x0000 }, /* R1212 */
1217 { 0x0000, 0x0000 }, /* R1213 */
1218 { 0x0000, 0x0000 }, /* R1214 */
1219 { 0x0000, 0x0000 }, /* R1215 */
1220 { 0x0000, 0x0000 }, /* R1216 */
1221 { 0x0000, 0x0000 }, /* R1217 */
1222 { 0x0000, 0x0000 }, /* R1218 */
1223 { 0x0000, 0x0000 }, /* R1219 */
1224 { 0x0000, 0x0000 }, /* R1220 */
1225 { 0x0000, 0x0000 }, /* R1221 */
1226 { 0x0000, 0x0000 }, /* R1222 */
1227 { 0x0000, 0x0000 }, /* R1223 */
1228 { 0x0000, 0x0000 }, /* R1224 */
1229 { 0x0000, 0x0000 }, /* R1225 */
1230 { 0x0000, 0x0000 }, /* R1226 */
1231 { 0x0000, 0x0000 }, /* R1227 */
1232 { 0x0000, 0x0000 }, /* R1228 */
1233 { 0x0000, 0x0000 }, /* R1229 */
1234 { 0x0000, 0x0000 }, /* R1230 */
1235 { 0x0000, 0x0000 }, /* R1231 */
1236 { 0x0000, 0x0000 }, /* R1232 */
1237 { 0x0000, 0x0000 }, /* R1233 */
1238 { 0x0000, 0x0000 }, /* R1234 */
1239 { 0x0000, 0x0000 }, /* R1235 */
1240 { 0x0000, 0x0000 }, /* R1236 */
1241 { 0x0000, 0x0000 }, /* R1237 */
1242 { 0x0000, 0x0000 }, /* R1238 */
1243 { 0x0000, 0x0000 }, /* R1239 */
1244 { 0x0000, 0x0000 }, /* R1240 */
1245 { 0x0000, 0x0000 }, /* R1241 */
1246 { 0x0000, 0x0000 }, /* R1242 */
1247 { 0x0000, 0x0000 }, /* R1243 */
1248 { 0x0000, 0x0000 }, /* R1244 */
1249 { 0x0000, 0x0000 }, /* R1245 */
1250 { 0x0000, 0x0000 }, /* R1246 */
1251 { 0x0000, 0x0000 }, /* R1247 */
1252 { 0x0000, 0x0000 }, /* R1248 */
1253 { 0x0000, 0x0000 }, /* R1249 */
1254 { 0x0000, 0x0000 }, /* R1250 */
1255 { 0x0000, 0x0000 }, /* R1251 */
1256 { 0x0000, 0x0000 }, /* R1252 */
1257 { 0x0000, 0x0000 }, /* R1253 */
1258 { 0x0000, 0x0000 }, /* R1254 */
1259 { 0x0000, 0x0000 }, /* R1255 */
1260 { 0x0000, 0x0000 }, /* R1256 */
1261 { 0x0000, 0x0000 }, /* R1257 */
1262 { 0x0000, 0x0000 }, /* R1258 */
1263 { 0x0000, 0x0000 }, /* R1259 */
1264 { 0x0000, 0x0000 }, /* R1260 */
1265 { 0x0000, 0x0000 }, /* R1261 */
1266 { 0x0000, 0x0000 }, /* R1262 */
1267 { 0x0000, 0x0000 }, /* R1263 */
1268 { 0x0000, 0x0000 }, /* R1264 */
1269 { 0x0000, 0x0000 }, /* R1265 */
1270 { 0x0000, 0x0000 }, /* R1266 */
1271 { 0x0000, 0x0000 }, /* R1267 */
1272 { 0x0000, 0x0000 }, /* R1268 */
1273 { 0x0000, 0x0000 }, /* R1269 */
1274 { 0x0000, 0x0000 }, /* R1270 */
1275 { 0x0000, 0x0000 }, /* R1271 */
1276 { 0x0000, 0x0000 }, /* R1272 */
1277 { 0x0000, 0x0000 }, /* R1273 */
1278 { 0x0000, 0x0000 }, /* R1274 */
1279 { 0x0000, 0x0000 }, /* R1275 */
1280 { 0x0000, 0x0000 }, /* R1276 */
1281 { 0x0000, 0x0000 }, /* R1277 */
1282 { 0x0000, 0x0000 }, /* R1278 */
1283 { 0x0000, 0x0000 }, /* R1279 */
1284 { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
1285 { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
1286 { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
1287 { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
1288 { 0x0000, 0x0000 }, /* R1284 */
1289 { 0x0000, 0x0000 }, /* R1285 */
1290 { 0x0000, 0x0000 }, /* R1286 */
1291 { 0x0000, 0x0000 }, /* R1287 */
1292 { 0x0000, 0x0000 }, /* R1288 */
1293 { 0x0000, 0x0000 }, /* R1289 */
1294 { 0x0000, 0x0000 }, /* R1290 */
1295 { 0x0000, 0x0000 }, /* R1291 */
1296 { 0x0000, 0x0000 }, /* R1292 */
1297 { 0x0000, 0x0000 }, /* R1293 */
1298 { 0x0000, 0x0000 }, /* R1294 */
1299 { 0x0000, 0x0000 }, /* R1295 */
1300 { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
1301 { 0x0000, 0x0000 }, /* R1297 */
1302 { 0x0000, 0x0000 }, /* R1298 */
1303 { 0x0000, 0x0000 }, /* R1299 */
1304 { 0x0000, 0x0000 }, /* R1300 */
1305 { 0x0000, 0x0000 }, /* R1301 */
1306 { 0x0000, 0x0000 }, /* R1302 */
1307 { 0x0000, 0x0000 }, /* R1303 */
1308 { 0x0000, 0x0000 }, /* R1304 */
1309 { 0x0000, 0x0000 }, /* R1305 */
1310 { 0x0000, 0x0000 }, /* R1306 */
1311 { 0x0000, 0x0000 }, /* R1307 */
1312 { 0x0000, 0x0000 }, /* R1308 */
1313 { 0x0000, 0x0000 }, /* R1309 */
1314 { 0x0000, 0x0000 }, /* R1310 */
1315 { 0x0000, 0x0000 }, /* R1311 */
1316 { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
1317 { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
1318 { 0x0000, 0x0000 }, /* R1314 */
1319 { 0x0000, 0x0000 }, /* R1315 */
1320 { 0x0000, 0x0000 }, /* R1316 */
1321 { 0x0000, 0x0000 }, /* R1317 */
1322 { 0x0000, 0x0000 }, /* R1318 */
1323 { 0x0000, 0x0000 }, /* R1319 */
1324 { 0x0000, 0x0000 }, /* R1320 */
1325 { 0x0000, 0x0000 }, /* R1321 */
1326 { 0x0000, 0x0000 }, /* R1322 */
1327 { 0x0000, 0x0000 }, /* R1323 */
1328 { 0x0000, 0x0000 }, /* R1324 */
1329 { 0x0000, 0x0000 }, /* R1325 */
1330 { 0x0000, 0x0000 }, /* R1326 */
1331 { 0x0000, 0x0000 }, /* R1327 */
1332 { 0x0000, 0x0000 }, /* R1328 */
1333 { 0x0000, 0x0000 }, /* R1329 */
1334 { 0x0000, 0x0000 }, /* R1330 */
1335 { 0x0000, 0x0000 }, /* R1331 */
1336 { 0x0000, 0x0000 }, /* R1332 */
1337 { 0x0000, 0x0000 }, /* R1333 */
1338 { 0x0000, 0x0000 }, /* R1334 */
1339 { 0x0000, 0x0000 }, /* R1335 */
1340 { 0x0000, 0x0000 }, /* R1336 */
1341 { 0x0000, 0x0000 }, /* R1337 */
1342 { 0x0000, 0x0000 }, /* R1338 */
1343 { 0x0000, 0x0000 }, /* R1339 */
1344 { 0x0000, 0x0000 }, /* R1340 */
1345 { 0x0000, 0x0000 }, /* R1341 */
1346 { 0x0000, 0x0000 }, /* R1342 */
1347 { 0x0000, 0x0000 }, /* R1343 */
1348 { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
1349 { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
1350 { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
1351 { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
1352 { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
1353 { 0x0000, 0x0000 }, /* R1349 */
1354 { 0x0000, 0x0000 }, /* R1350 */
1355 { 0x0000, 0x0000 }, /* R1351 */
1356 { 0x0000, 0x0000 }, /* R1352 */
1357 { 0x0000, 0x0000 }, /* R1353 */
1358 { 0x0000, 0x0000 }, /* R1354 */
1359 { 0x0000, 0x0000 }, /* R1355 */
1360 { 0x0000, 0x0000 }, /* R1356 */
1361 { 0x0000, 0x0000 }, /* R1357 */
1362 { 0x0000, 0x0000 }, /* R1358 */
1363 { 0x0000, 0x0000 }, /* R1359 */
1364 { 0x0000, 0x0000 }, /* R1360 */
1365 { 0x0000, 0x0000 }, /* R1361 */
1366 { 0x0000, 0x0000 }, /* R1362 */
1367 { 0x0000, 0x0000 }, /* R1363 */
1368 { 0x0000, 0x0000 }, /* R1364 */
1369 { 0x0000, 0x0000 }, /* R1365 */
1370 { 0x0000, 0x0000 }, /* R1366 */
1371 { 0x0000, 0x0000 }, /* R1367 */
1372 { 0x0000, 0x0000 }, /* R1368 */
1373 { 0x0000, 0x0000 }, /* R1369 */
1374 { 0x0000, 0x0000 }, /* R1370 */
1375 { 0x0000, 0x0000 }, /* R1371 */
1376 { 0x0000, 0x0000 }, /* R1372 */
1377 { 0x0000, 0x0000 }, /* R1373 */
1378 { 0x0000, 0x0000 }, /* R1374 */
1379 { 0x0000, 0x0000 }, /* R1375 */
1380 { 0x0000, 0x0000 }, /* R1376 */
1381 { 0x0000, 0x0000 }, /* R1377 */
1382 { 0x0000, 0x0000 }, /* R1378 */
1383 { 0x0000, 0x0000 }, /* R1379 */
1384 { 0x0000, 0x0000 }, /* R1380 */
1385 { 0x0000, 0x0000 }, /* R1381 */
1386 { 0x0000, 0x0000 }, /* R1382 */
1387 { 0x0000, 0x0000 }, /* R1383 */
1388 { 0x0000, 0x0000 }, /* R1384 */
1389 { 0x0000, 0x0000 }, /* R1385 */
1390 { 0x0000, 0x0000 }, /* R1386 */
1391 { 0x0000, 0x0000 }, /* R1387 */
1392 { 0x0000, 0x0000 }, /* R1388 */
1393 { 0x0000, 0x0000 }, /* R1389 */
1394 { 0x0000, 0x0000 }, /* R1390 */
1395 { 0x0000, 0x0000 }, /* R1391 */
1396 { 0x0000, 0x0000 }, /* R1392 */
1397 { 0x0000, 0x0000 }, /* R1393 */
1398 { 0x0000, 0x0000 }, /* R1394 */
1399 { 0x0000, 0x0000 }, /* R1395 */
1400 { 0x0000, 0x0000 }, /* R1396 */
1401 { 0x0000, 0x0000 }, /* R1397 */
1402 { 0x0000, 0x0000 }, /* R1398 */
1403 { 0x0000, 0x0000 }, /* R1399 */
1404 { 0x0000, 0x0000 }, /* R1400 */
1405 { 0x0000, 0x0000 }, /* R1401 */
1406 { 0x0000, 0x0000 }, /* R1402 */
1407 { 0x0000, 0x0000 }, /* R1403 */
1408 { 0x0000, 0x0000 }, /* R1404 */
1409 { 0x0000, 0x0000 }, /* R1405 */
1410 { 0x0000, 0x0000 }, /* R1406 */
1411 { 0x0000, 0x0000 }, /* R1407 */
1412 { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
1413 { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
1414 { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
1415 { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
1416 { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
1417 { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
1418 { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
1419 { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
1420 { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
1421 { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
1422 { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
1423 { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
1424 { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
1425 { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
1426 { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
1427 { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
1428 { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
1429 { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
1430 { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
1431 { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
1432 { 0x0000, 0x0000 }, /* R1428 */
1433 { 0x0000, 0x0000 }, /* R1429 */
1434 { 0x0000, 0x0000 }, /* R1430 */
1435 { 0x0000, 0x0000 }, /* R1431 */
1436 { 0x0000, 0x0000 }, /* R1432 */
1437 { 0x0000, 0x0000 }, /* R1433 */
1438 { 0x0000, 0x0000 }, /* R1434 */
1439 { 0x0000, 0x0000 }, /* R1435 */
1440 { 0x0000, 0x0000 }, /* R1436 */
1441 { 0x0000, 0x0000 }, /* R1437 */
1442 { 0x0000, 0x0000 }, /* R1438 */
1443 { 0x0000, 0x0000 }, /* R1439 */
1444 { 0x0000, 0x0000 }, /* R1440 */
1445 { 0x0000, 0x0000 }, /* R1441 */
1446 { 0x0000, 0x0000 }, /* R1442 */
1447 { 0x0000, 0x0000 }, /* R1443 */
1448 { 0x0000, 0x0000 }, /* R1444 */
1449 { 0x0000, 0x0000 }, /* R1445 */
1450 { 0x0000, 0x0000 }, /* R1446 */
1451 { 0x0000, 0x0000 }, /* R1447 */
1452 { 0x0000, 0x0000 }, /* R1448 */
1453 { 0x0000, 0x0000 }, /* R1449 */
1454 { 0x0000, 0x0000 }, /* R1450 */
1455 { 0x0000, 0x0000 }, /* R1451 */
1456 { 0x0000, 0x0000 }, /* R1452 */
1457 { 0x0000, 0x0000 }, /* R1453 */
1458 { 0x0000, 0x0000 }, /* R1454 */
1459 { 0x0000, 0x0000 }, /* R1455 */
1460 { 0x0000, 0x0000 }, /* R1456 */
1461 { 0x0000, 0x0000 }, /* R1457 */
1462 { 0x0000, 0x0000 }, /* R1458 */
1463 { 0x0000, 0x0000 }, /* R1459 */
1464 { 0x0000, 0x0000 }, /* R1460 */
1465 { 0x0000, 0x0000 }, /* R1461 */
1466 { 0x0000, 0x0000 }, /* R1462 */
1467 { 0x0000, 0x0000 }, /* R1463 */
1468 { 0x0000, 0x0000 }, /* R1464 */
1469 { 0x0000, 0x0000 }, /* R1465 */
1470 { 0x0000, 0x0000 }, /* R1466 */
1471 { 0x0000, 0x0000 }, /* R1467 */
1472 { 0x0000, 0x0000 }, /* R1468 */
1473 { 0x0000, 0x0000 }, /* R1469 */
1474 { 0x0000, 0x0000 }, /* R1470 */
1475 { 0x0000, 0x0000 }, /* R1471 */
1476 { 0x0000, 0x0000 }, /* R1472 */
1477 { 0x0000, 0x0000 }, /* R1473 */
1478 { 0x0000, 0x0000 }, /* R1474 */
1479 { 0x0000, 0x0000 }, /* R1475 */
1480 { 0x0000, 0x0000 }, /* R1476 */
1481 { 0x0000, 0x0000 }, /* R1477 */
1482 { 0x0000, 0x0000 }, /* R1478 */
1483 { 0x0000, 0x0000 }, /* R1479 */
1484 { 0x0000, 0x0000 }, /* R1480 */
1485 { 0x0000, 0x0000 }, /* R1481 */
1486 { 0x0000, 0x0000 }, /* R1482 */
1487 { 0x0000, 0x0000 }, /* R1483 */
1488 { 0x0000, 0x0000 }, /* R1484 */
1489 { 0x0000, 0x0000 }, /* R1485 */
1490 { 0x0000, 0x0000 }, /* R1486 */
1491 { 0x0000, 0x0000 }, /* R1487 */
1492 { 0x0000, 0x0000 }, /* R1488 */
1493 { 0x0000, 0x0000 }, /* R1489 */
1494 { 0x0000, 0x0000 }, /* R1490 */
1495 { 0x0000, 0x0000 }, /* R1491 */
1496 { 0x0000, 0x0000 }, /* R1492 */
1497 { 0x0000, 0x0000 }, /* R1493 */
1498 { 0x0000, 0x0000 }, /* R1494 */
1499 { 0x0000, 0x0000 }, /* R1495 */
1500 { 0x0000, 0x0000 }, /* R1496 */
1501 { 0x0000, 0x0000 }, /* R1497 */
1502 { 0x0000, 0x0000 }, /* R1498 */
1503 { 0x0000, 0x0000 }, /* R1499 */
1504 { 0x0000, 0x0000 }, /* R1500 */
1505 { 0x0000, 0x0000 }, /* R1501 */
1506 { 0x0000, 0x0000 }, /* R1502 */
1507 { 0x0000, 0x0000 }, /* R1503 */
1508 { 0x0000, 0x0000 }, /* R1504 */
1509 { 0x0000, 0x0000 }, /* R1505 */
1510 { 0x0000, 0x0000 }, /* R1506 */
1511 { 0x0000, 0x0000 }, /* R1507 */
1512 { 0x0000, 0x0000 }, /* R1508 */
1513 { 0x0000, 0x0000 }, /* R1509 */
1514 { 0x0000, 0x0000 }, /* R1510 */
1515 { 0x0000, 0x0000 }, /* R1511 */
1516 { 0x0000, 0x0000 }, /* R1512 */
1517 { 0x0000, 0x0000 }, /* R1513 */
1518 { 0x0000, 0x0000 }, /* R1514 */
1519 { 0x0000, 0x0000 }, /* R1515 */
1520 { 0x0000, 0x0000 }, /* R1516 */
1521 { 0x0000, 0x0000 }, /* R1517 */
1522 { 0x0000, 0x0000 }, /* R1518 */
1523 { 0x0000, 0x0000 }, /* R1519 */
1524 { 0x0000, 0x0000 }, /* R1520 */
1525 { 0x0000, 0x0000 }, /* R1521 */
1526 { 0x0000, 0x0000 }, /* R1522 */
1527 { 0x0000, 0x0000 }, /* R1523 */
1528 { 0x0000, 0x0000 }, /* R1524 */
1529 { 0x0000, 0x0000 }, /* R1525 */
1530 { 0x0000, 0x0000 }, /* R1526 */
1531 { 0x0000, 0x0000 }, /* R1527 */
1532 { 0x0000, 0x0000 }, /* R1528 */
1533 { 0x0000, 0x0000 }, /* R1529 */
1534 { 0x0000, 0x0000 }, /* R1530 */
1535 { 0x0000, 0x0000 }, /* R1531 */
1536 { 0x0000, 0x0000 }, /* R1532 */
1537 { 0x0000, 0x0000 }, /* R1533 */
1538 { 0x0000, 0x0000 }, /* R1534 */
1539 { 0x0000, 0x0000 }, /* R1535 */
1540 { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
1541 { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
1542 { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
1543 { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
1544 { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
1545 { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
1546 { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1547 { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1548 { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1549 { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1550 { 0x0000, 0x0000 }, /* R1546 */
1551 { 0x0000, 0x0000 }, /* R1547 */
1552 { 0x0000, 0x0000 }, /* R1548 */
1553 { 0x0000, 0x0000 }, /* R1549 */
1554 { 0x0000, 0x0000 }, /* R1550 */
1555 { 0x0000, 0x0000 }, /* R1551 */
1556 { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
1557 { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
1558 { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
1559 { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
1560 { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
1561 { 0x0000, 0x0000 }, /* R1557 */
1562 { 0x0000, 0x0000 }, /* R1558 */
1563 { 0x0000, 0x0000 }, /* R1559 */
1564 { 0x0000, 0x0000 }, /* R1560 */
1565 { 0x0000, 0x0000 }, /* R1561 */
1566 { 0x0000, 0x0000 }, /* R1562 */
1567 { 0x0000, 0x0000 }, /* R1563 */
1568 { 0x0000, 0x0000 }, /* R1564 */
1569 { 0x0000, 0x0000 }, /* R1565 */
1570 { 0x0000, 0x0000 }, /* R1566 */
1571 { 0x0000, 0x0000 }, /* R1567 */
1572 { 0x0003, 0x0003 }, /* R1568 - Oversampling */
1573 { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
1574};
1575
1576const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
1577 0x8994, /* R0 - Software Reset */
1578 0x0000, /* R1 - Power Management (1) */
1579 0x6000, /* R2 - Power Management (2) */
1580 0x0000, /* R3 - Power Management (3) */
1581 0x0000, /* R4 - Power Management (4) */
1582 0x0000, /* R5 - Power Management (5) */
1583 0x0000, /* R6 - Power Management (6) */
1584 0x0000, /* R7 */
1585 0x0000, /* R8 */
1586 0x0000, /* R9 */
1587 0x0000, /* R10 */
1588 0x0000, /* R11 */
1589 0x0000, /* R12 */
1590 0x0000, /* R13 */
1591 0x0000, /* R14 */
1592 0x0000, /* R15 */
1593 0x0000, /* R16 */
1594 0x0000, /* R17 */
1595 0x0000, /* R18 */
1596 0x0000, /* R19 */
1597 0x0000, /* R20 */
1598 0x0000, /* R21 - Input Mixer (1) */
1599 0x0000, /* R22 */
1600 0x0000, /* R23 */
1601 0x008B, /* R24 - Left Line Input 1&2 Volume */
1602 0x008B, /* R25 - Left Line Input 3&4 Volume */
1603 0x008B, /* R26 - Right Line Input 1&2 Volume */
1604 0x008B, /* R27 - Right Line Input 3&4 Volume */
1605 0x006D, /* R28 - Left Output Volume */
1606 0x006D, /* R29 - Right Output Volume */
1607 0x0066, /* R30 - Line Outputs Volume */
1608 0x0020, /* R31 - HPOUT2 Volume */
1609 0x0079, /* R32 - Left OPGA Volume */
1610 0x0079, /* R33 - Right OPGA Volume */
1611 0x0003, /* R34 - SPKMIXL Attenuation */
1612 0x0003, /* R35 - SPKMIXR Attenuation */
1613 0x0011, /* R36 - SPKOUT Mixers */
1614 0x0140, /* R37 - ClassD */
1615 0x0079, /* R38 - Speaker Volume Left */
1616 0x0079, /* R39 - Speaker Volume Right */
1617 0x0000, /* R40 - Input Mixer (2) */
1618 0x0000, /* R41 - Input Mixer (3) */
1619 0x0000, /* R42 - Input Mixer (4) */
1620 0x0000, /* R43 - Input Mixer (5) */
1621 0x0000, /* R44 - Input Mixer (6) */
1622 0x0000, /* R45 - Output Mixer (1) */
1623 0x0000, /* R46 - Output Mixer (2) */
1624 0x0000, /* R47 - Output Mixer (3) */
1625 0x0000, /* R48 - Output Mixer (4) */
1626 0x0000, /* R49 - Output Mixer (5) */
1627 0x0000, /* R50 - Output Mixer (6) */
1628 0x0000, /* R51 - HPOUT2 Mixer */
1629 0x0000, /* R52 - Line Mixer (1) */
1630 0x0000, /* R53 - Line Mixer (2) */
1631 0x0000, /* R54 - Speaker Mixer */
1632 0x0000, /* R55 - Additional Control */
1633 0x0000, /* R56 - AntiPOP (1) */
1634 0x0000, /* R57 - AntiPOP (2) */
1635 0x0000, /* R58 - MICBIAS */
1636 0x000D, /* R59 - LDO 1 */
1637 0x0003, /* R60 - LDO 2 */
1638 0x0000, /* R61 */
1639 0x0000, /* R62 */
1640 0x0000, /* R63 */
1641 0x0000, /* R64 */
1642 0x0000, /* R65 */
1643 0x0000, /* R66 */
1644 0x0000, /* R67 */
1645 0x0000, /* R68 */
1646 0x0000, /* R69 */
1647 0x0000, /* R70 */
1648 0x0000, /* R71 */
1649 0x0000, /* R72 */
1650 0x0000, /* R73 */
1651 0x0000, /* R74 */
1652 0x0000, /* R75 */
1653 0x1F25, /* R76 - Charge Pump (1) */
1654 0x0000, /* R77 */
1655 0x0000, /* R78 */
1656 0x0000, /* R79 */
1657 0x0000, /* R80 */
1658 0x0004, /* R81 - Class W (1) */
1659 0x0000, /* R82 */
1660 0x0000, /* R83 */
1661 0x0000, /* R84 - DC Servo (1) */
1662 0x054A, /* R85 - DC Servo (2) */
1663 0x0000, /* R86 */
1664 0x0000, /* R87 - DC Servo (4) */
1665 0x0000, /* R88 - DC Servo Readback */
1666 0x0000, /* R89 */
1667 0x0000, /* R90 */
1668 0x0000, /* R91 */
1669 0x0000, /* R92 */
1670 0x0000, /* R93 */
1671 0x0000, /* R94 */
1672 0x0000, /* R95 */
1673 0x0000, /* R96 - Analogue HP (1) */
1674 0x0000, /* R97 */
1675 0x0000, /* R98 */
1676 0x0000, /* R99 */
1677 0x0000, /* R100 */
1678 0x0000, /* R101 */
1679 0x0000, /* R102 */
1680 0x0000, /* R103 */
1681 0x0000, /* R104 */
1682 0x0000, /* R105 */
1683 0x0000, /* R106 */
1684 0x0000, /* R107 */
1685 0x0000, /* R108 */
1686 0x0000, /* R109 */
1687 0x0000, /* R110 */
1688 0x0000, /* R111 */
1689 0x0000, /* R112 */
1690 0x0000, /* R113 */
1691 0x0000, /* R114 */
1692 0x0000, /* R115 */
1693 0x0000, /* R116 */
1694 0x0000, /* R117 */
1695 0x0000, /* R118 */
1696 0x0000, /* R119 */
1697 0x0000, /* R120 */
1698 0x0000, /* R121 */
1699 0x0000, /* R122 */
1700 0x0000, /* R123 */
1701 0x0000, /* R124 */
1702 0x0000, /* R125 */
1703 0x0000, /* R126 */
1704 0x0000, /* R127 */
1705 0x0000, /* R128 */
1706 0x0000, /* R129 */
1707 0x0000, /* R130 */
1708 0x0000, /* R131 */
1709 0x0000, /* R132 */
1710 0x0000, /* R133 */
1711 0x0000, /* R134 */
1712 0x0000, /* R135 */
1713 0x0000, /* R136 */
1714 0x0000, /* R137 */
1715 0x0000, /* R138 */
1716 0x0000, /* R139 */
1717 0x0000, /* R140 */
1718 0x0000, /* R141 */
1719 0x0000, /* R142 */
1720 0x0000, /* R143 */
1721 0x0000, /* R144 */
1722 0x0000, /* R145 */
1723 0x0000, /* R146 */
1724 0x0000, /* R147 */
1725 0x0000, /* R148 */
1726 0x0000, /* R149 */
1727 0x0000, /* R150 */
1728 0x0000, /* R151 */
1729 0x0000, /* R152 */
1730 0x0000, /* R153 */
1731 0x0000, /* R154 */
1732 0x0000, /* R155 */
1733 0x0000, /* R156 */
1734 0x0000, /* R157 */
1735 0x0000, /* R158 */
1736 0x0000, /* R159 */
1737 0x0000, /* R160 */
1738 0x0000, /* R161 */
1739 0x0000, /* R162 */
1740 0x0000, /* R163 */
1741 0x0000, /* R164 */
1742 0x0000, /* R165 */
1743 0x0000, /* R166 */
1744 0x0000, /* R167 */
1745 0x0000, /* R168 */
1746 0x0000, /* R169 */
1747 0x0000, /* R170 */
1748 0x0000, /* R171 */
1749 0x0000, /* R172 */
1750 0x0000, /* R173 */
1751 0x0000, /* R174 */
1752 0x0000, /* R175 */
1753 0x0000, /* R176 */
1754 0x0000, /* R177 */
1755 0x0000, /* R178 */
1756 0x0000, /* R179 */
1757 0x0000, /* R180 */
1758 0x0000, /* R181 */
1759 0x0000, /* R182 */
1760 0x0000, /* R183 */
1761 0x0000, /* R184 */
1762 0x0000, /* R185 */
1763 0x0000, /* R186 */
1764 0x0000, /* R187 */
1765 0x0000, /* R188 */
1766 0x0000, /* R189 */
1767 0x0000, /* R190 */
1768 0x0000, /* R191 */
1769 0x0000, /* R192 */
1770 0x0000, /* R193 */
1771 0x0000, /* R194 */
1772 0x0000, /* R195 */
1773 0x0000, /* R196 */
1774 0x0000, /* R197 */
1775 0x0000, /* R198 */
1776 0x0000, /* R199 */
1777 0x0000, /* R200 */
1778 0x0000, /* R201 */
1779 0x0000, /* R202 */
1780 0x0000, /* R203 */
1781 0x0000, /* R204 */
1782 0x0000, /* R205 */
1783 0x0000, /* R206 */
1784 0x0000, /* R207 */
1785 0x0000, /* R208 */
1786 0x0000, /* R209 */
1787 0x0000, /* R210 */
1788 0x0000, /* R211 */
1789 0x0000, /* R212 */
1790 0x0000, /* R213 */
1791 0x0000, /* R214 */
1792 0x0000, /* R215 */
1793 0x0000, /* R216 */
1794 0x0000, /* R217 */
1795 0x0000, /* R218 */
1796 0x0000, /* R219 */
1797 0x0000, /* R220 */
1798 0x0000, /* R221 */
1799 0x0000, /* R222 */
1800 0x0000, /* R223 */
1801 0x0000, /* R224 */
1802 0x0000, /* R225 */
1803 0x0000, /* R226 */
1804 0x0000, /* R227 */
1805 0x0000, /* R228 */
1806 0x0000, /* R229 */
1807 0x0000, /* R230 */
1808 0x0000, /* R231 */
1809 0x0000, /* R232 */
1810 0x0000, /* R233 */
1811 0x0000, /* R234 */
1812 0x0000, /* R235 */
1813 0x0000, /* R236 */
1814 0x0000, /* R237 */
1815 0x0000, /* R238 */
1816 0x0000, /* R239 */
1817 0x0000, /* R240 */
1818 0x0000, /* R241 */
1819 0x0000, /* R242 */
1820 0x0000, /* R243 */
1821 0x0000, /* R244 */
1822 0x0000, /* R245 */
1823 0x0000, /* R246 */
1824 0x0000, /* R247 */
1825 0x0000, /* R248 */
1826 0x0000, /* R249 */
1827 0x0000, /* R250 */
1828 0x0000, /* R251 */
1829 0x0000, /* R252 */
1830 0x0000, /* R253 */
1831 0x0000, /* R254 */
1832 0x0000, /* R255 */
1833 0x0003, /* R256 - Chip Revision */
1834 0x8004, /* R257 - Control Interface */
1835 0x0000, /* R258 */
1836 0x0000, /* R259 */
1837 0x0000, /* R260 */
1838 0x0000, /* R261 */
1839 0x0000, /* R262 */
1840 0x0000, /* R263 */
1841 0x0000, /* R264 */
1842 0x0000, /* R265 */
1843 0x0000, /* R266 */
1844 0x0000, /* R267 */
1845 0x0000, /* R268 */
1846 0x0000, /* R269 */
1847 0x0000, /* R270 */
1848 0x0000, /* R271 */
1849 0x0000, /* R272 - Write Sequencer Ctrl (1) */
1850 0x0000, /* R273 - Write Sequencer Ctrl (2) */
1851 0x0000, /* R274 */
1852 0x0000, /* R275 */
1853 0x0000, /* R276 */
1854 0x0000, /* R277 */
1855 0x0000, /* R278 */
1856 0x0000, /* R279 */
1857 0x0000, /* R280 */
1858 0x0000, /* R281 */
1859 0x0000, /* R282 */
1860 0x0000, /* R283 */
1861 0x0000, /* R284 */
1862 0x0000, /* R285 */
1863 0x0000, /* R286 */
1864 0x0000, /* R287 */
1865 0x0000, /* R288 */
1866 0x0000, /* R289 */
1867 0x0000, /* R290 */
1868 0x0000, /* R291 */
1869 0x0000, /* R292 */
1870 0x0000, /* R293 */
1871 0x0000, /* R294 */
1872 0x0000, /* R295 */
1873 0x0000, /* R296 */
1874 0x0000, /* R297 */
1875 0x0000, /* R298 */
1876 0x0000, /* R299 */
1877 0x0000, /* R300 */
1878 0x0000, /* R301 */
1879 0x0000, /* R302 */
1880 0x0000, /* R303 */
1881 0x0000, /* R304 */
1882 0x0000, /* R305 */
1883 0x0000, /* R306 */
1884 0x0000, /* R307 */
1885 0x0000, /* R308 */
1886 0x0000, /* R309 */
1887 0x0000, /* R310 */
1888 0x0000, /* R311 */
1889 0x0000, /* R312 */
1890 0x0000, /* R313 */
1891 0x0000, /* R314 */
1892 0x0000, /* R315 */
1893 0x0000, /* R316 */
1894 0x0000, /* R317 */
1895 0x0000, /* R318 */
1896 0x0000, /* R319 */
1897 0x0000, /* R320 */
1898 0x0000, /* R321 */
1899 0x0000, /* R322 */
1900 0x0000, /* R323 */
1901 0x0000, /* R324 */
1902 0x0000, /* R325 */
1903 0x0000, /* R326 */
1904 0x0000, /* R327 */
1905 0x0000, /* R328 */
1906 0x0000, /* R329 */
1907 0x0000, /* R330 */
1908 0x0000, /* R331 */
1909 0x0000, /* R332 */
1910 0x0000, /* R333 */
1911 0x0000, /* R334 */
1912 0x0000, /* R335 */
1913 0x0000, /* R336 */
1914 0x0000, /* R337 */
1915 0x0000, /* R338 */
1916 0x0000, /* R339 */
1917 0x0000, /* R340 */
1918 0x0000, /* R341 */
1919 0x0000, /* R342 */
1920 0x0000, /* R343 */
1921 0x0000, /* R344 */
1922 0x0000, /* R345 */
1923 0x0000, /* R346 */
1924 0x0000, /* R347 */
1925 0x0000, /* R348 */
1926 0x0000, /* R349 */
1927 0x0000, /* R350 */
1928 0x0000, /* R351 */
1929 0x0000, /* R352 */
1930 0x0000, /* R353 */
1931 0x0000, /* R354 */
1932 0x0000, /* R355 */
1933 0x0000, /* R356 */
1934 0x0000, /* R357 */
1935 0x0000, /* R358 */
1936 0x0000, /* R359 */
1937 0x0000, /* R360 */
1938 0x0000, /* R361 */
1939 0x0000, /* R362 */
1940 0x0000, /* R363 */
1941 0x0000, /* R364 */
1942 0x0000, /* R365 */
1943 0x0000, /* R366 */
1944 0x0000, /* R367 */
1945 0x0000, /* R368 */
1946 0x0000, /* R369 */
1947 0x0000, /* R370 */
1948 0x0000, /* R371 */
1949 0x0000, /* R372 */
1950 0x0000, /* R373 */
1951 0x0000, /* R374 */
1952 0x0000, /* R375 */
1953 0x0000, /* R376 */
1954 0x0000, /* R377 */
1955 0x0000, /* R378 */
1956 0x0000, /* R379 */
1957 0x0000, /* R380 */
1958 0x0000, /* R381 */
1959 0x0000, /* R382 */
1960 0x0000, /* R383 */
1961 0x0000, /* R384 */
1962 0x0000, /* R385 */
1963 0x0000, /* R386 */
1964 0x0000, /* R387 */
1965 0x0000, /* R388 */
1966 0x0000, /* R389 */
1967 0x0000, /* R390 */
1968 0x0000, /* R391 */
1969 0x0000, /* R392 */
1970 0x0000, /* R393 */
1971 0x0000, /* R394 */
1972 0x0000, /* R395 */
1973 0x0000, /* R396 */
1974 0x0000, /* R397 */
1975 0x0000, /* R398 */
1976 0x0000, /* R399 */
1977 0x0000, /* R400 */
1978 0x0000, /* R401 */
1979 0x0000, /* R402 */
1980 0x0000, /* R403 */
1981 0x0000, /* R404 */
1982 0x0000, /* R405 */
1983 0x0000, /* R406 */
1984 0x0000, /* R407 */
1985 0x0000, /* R408 */
1986 0x0000, /* R409 */
1987 0x0000, /* R410 */
1988 0x0000, /* R411 */
1989 0x0000, /* R412 */
1990 0x0000, /* R413 */
1991 0x0000, /* R414 */
1992 0x0000, /* R415 */
1993 0x0000, /* R416 */
1994 0x0000, /* R417 */
1995 0x0000, /* R418 */
1996 0x0000, /* R419 */
1997 0x0000, /* R420 */
1998 0x0000, /* R421 */
1999 0x0000, /* R422 */
2000 0x0000, /* R423 */
2001 0x0000, /* R424 */
2002 0x0000, /* R425 */
2003 0x0000, /* R426 */
2004 0x0000, /* R427 */
2005 0x0000, /* R428 */
2006 0x0000, /* R429 */
2007 0x0000, /* R430 */
2008 0x0000, /* R431 */
2009 0x0000, /* R432 */
2010 0x0000, /* R433 */
2011 0x0000, /* R434 */
2012 0x0000, /* R435 */
2013 0x0000, /* R436 */
2014 0x0000, /* R437 */
2015 0x0000, /* R438 */
2016 0x0000, /* R439 */
2017 0x0000, /* R440 */
2018 0x0000, /* R441 */
2019 0x0000, /* R442 */
2020 0x0000, /* R443 */
2021 0x0000, /* R444 */
2022 0x0000, /* R445 */
2023 0x0000, /* R446 */
2024 0x0000, /* R447 */
2025 0x0000, /* R448 */
2026 0x0000, /* R449 */
2027 0x0000, /* R450 */
2028 0x0000, /* R451 */
2029 0x0000, /* R452 */
2030 0x0000, /* R453 */
2031 0x0000, /* R454 */
2032 0x0000, /* R455 */
2033 0x0000, /* R456 */
2034 0x0000, /* R457 */
2035 0x0000, /* R458 */
2036 0x0000, /* R459 */
2037 0x0000, /* R460 */
2038 0x0000, /* R461 */
2039 0x0000, /* R462 */
2040 0x0000, /* R463 */
2041 0x0000, /* R464 */
2042 0x0000, /* R465 */
2043 0x0000, /* R466 */
2044 0x0000, /* R467 */
2045 0x0000, /* R468 */
2046 0x0000, /* R469 */
2047 0x0000, /* R470 */
2048 0x0000, /* R471 */
2049 0x0000, /* R472 */
2050 0x0000, /* R473 */
2051 0x0000, /* R474 */
2052 0x0000, /* R475 */
2053 0x0000, /* R476 */
2054 0x0000, /* R477 */
2055 0x0000, /* R478 */
2056 0x0000, /* R479 */
2057 0x0000, /* R480 */
2058 0x0000, /* R481 */
2059 0x0000, /* R482 */
2060 0x0000, /* R483 */
2061 0x0000, /* R484 */
2062 0x0000, /* R485 */
2063 0x0000, /* R486 */
2064 0x0000, /* R487 */
2065 0x0000, /* R488 */
2066 0x0000, /* R489 */
2067 0x0000, /* R490 */
2068 0x0000, /* R491 */
2069 0x0000, /* R492 */
2070 0x0000, /* R493 */
2071 0x0000, /* R494 */
2072 0x0000, /* R495 */
2073 0x0000, /* R496 */
2074 0x0000, /* R497 */
2075 0x0000, /* R498 */
2076 0x0000, /* R499 */
2077 0x0000, /* R500 */
2078 0x0000, /* R501 */
2079 0x0000, /* R502 */
2080 0x0000, /* R503 */
2081 0x0000, /* R504 */
2082 0x0000, /* R505 */
2083 0x0000, /* R506 */
2084 0x0000, /* R507 */
2085 0x0000, /* R508 */
2086 0x0000, /* R509 */
2087 0x0000, /* R510 */
2088 0x0000, /* R511 */
2089 0x0000, /* R512 - AIF1 Clocking (1) */
2090 0x0000, /* R513 - AIF1 Clocking (2) */
2091 0x0000, /* R514 */
2092 0x0000, /* R515 */
2093 0x0000, /* R516 - AIF2 Clocking (1) */
2094 0x0000, /* R517 - AIF2 Clocking (2) */
2095 0x0000, /* R518 */
2096 0x0000, /* R519 */
2097 0x0000, /* R520 - Clocking (1) */
2098 0x0000, /* R521 - Clocking (2) */
2099 0x0000, /* R522 */
2100 0x0000, /* R523 */
2101 0x0000, /* R524 */
2102 0x0000, /* R525 */
2103 0x0000, /* R526 */
2104 0x0000, /* R527 */
2105 0x0083, /* R528 - AIF1 Rate */
2106 0x0083, /* R529 - AIF2 Rate */
2107 0x0000, /* R530 - Rate Status */
2108 0x0000, /* R531 */
2109 0x0000, /* R532 */
2110 0x0000, /* R533 */
2111 0x0000, /* R534 */
2112 0x0000, /* R535 */
2113 0x0000, /* R536 */
2114 0x0000, /* R537 */
2115 0x0000, /* R538 */
2116 0x0000, /* R539 */
2117 0x0000, /* R540 */
2118 0x0000, /* R541 */
2119 0x0000, /* R542 */
2120 0x0000, /* R543 */
2121 0x0000, /* R544 - FLL1 Control (1) */
2122 0x0000, /* R545 - FLL1 Control (2) */
2123 0x0000, /* R546 - FLL1 Control (3) */
2124 0x0000, /* R547 - FLL1 Control (4) */
2125 0x0C80, /* R548 - FLL1 Control (5) */
2126 0x0000, /* R549 */
2127 0x0000, /* R550 */
2128 0x0000, /* R551 */
2129 0x0000, /* R552 */
2130 0x0000, /* R553 */
2131 0x0000, /* R554 */
2132 0x0000, /* R555 */
2133 0x0000, /* R556 */
2134 0x0000, /* R557 */
2135 0x0000, /* R558 */
2136 0x0000, /* R559 */
2137 0x0000, /* R560 */
2138 0x0000, /* R561 */
2139 0x0000, /* R562 */
2140 0x0000, /* R563 */
2141 0x0000, /* R564 */
2142 0x0000, /* R565 */
2143 0x0000, /* R566 */
2144 0x0000, /* R567 */
2145 0x0000, /* R568 */
2146 0x0000, /* R569 */
2147 0x0000, /* R570 */
2148 0x0000, /* R571 */
2149 0x0000, /* R572 */
2150 0x0000, /* R573 */
2151 0x0000, /* R574 */
2152 0x0000, /* R575 */
2153 0x0000, /* R576 - FLL2 Control (1) */
2154 0x0000, /* R577 - FLL2 Control (2) */
2155 0x0000, /* R578 - FLL2 Control (3) */
2156 0x0000, /* R579 - FLL2 Control (4) */
2157 0x0C80, /* R580 - FLL2 Control (5) */
2158 0x0000, /* R581 */
2159 0x0000, /* R582 */
2160 0x0000, /* R583 */
2161 0x0000, /* R584 */
2162 0x0000, /* R585 */
2163 0x0000, /* R586 */
2164 0x0000, /* R587 */
2165 0x0000, /* R588 */
2166 0x0000, /* R589 */
2167 0x0000, /* R590 */
2168 0x0000, /* R591 */
2169 0x0000, /* R592 */
2170 0x0000, /* R593 */
2171 0x0000, /* R594 */
2172 0x0000, /* R595 */
2173 0x0000, /* R596 */
2174 0x0000, /* R597 */
2175 0x0000, /* R598 */
2176 0x0000, /* R599 */
2177 0x0000, /* R600 */
2178 0x0000, /* R601 */
2179 0x0000, /* R602 */
2180 0x0000, /* R603 */
2181 0x0000, /* R604 */
2182 0x0000, /* R605 */
2183 0x0000, /* R606 */
2184 0x0000, /* R607 */
2185 0x0000, /* R608 */
2186 0x0000, /* R609 */
2187 0x0000, /* R610 */
2188 0x0000, /* R611 */
2189 0x0000, /* R612 */
2190 0x0000, /* R613 */
2191 0x0000, /* R614 */
2192 0x0000, /* R615 */
2193 0x0000, /* R616 */
2194 0x0000, /* R617 */
2195 0x0000, /* R618 */
2196 0x0000, /* R619 */
2197 0x0000, /* R620 */
2198 0x0000, /* R621 */
2199 0x0000, /* R622 */
2200 0x0000, /* R623 */
2201 0x0000, /* R624 */
2202 0x0000, /* R625 */
2203 0x0000, /* R626 */
2204 0x0000, /* R627 */
2205 0x0000, /* R628 */
2206 0x0000, /* R629 */
2207 0x0000, /* R630 */
2208 0x0000, /* R631 */
2209 0x0000, /* R632 */
2210 0x0000, /* R633 */
2211 0x0000, /* R634 */
2212 0x0000, /* R635 */
2213 0x0000, /* R636 */
2214 0x0000, /* R637 */
2215 0x0000, /* R638 */
2216 0x0000, /* R639 */
2217 0x0000, /* R640 */
2218 0x0000, /* R641 */
2219 0x0000, /* R642 */
2220 0x0000, /* R643 */
2221 0x0000, /* R644 */
2222 0x0000, /* R645 */
2223 0x0000, /* R646 */
2224 0x0000, /* R647 */
2225 0x0000, /* R648 */
2226 0x0000, /* R649 */
2227 0x0000, /* R650 */
2228 0x0000, /* R651 */
2229 0x0000, /* R652 */
2230 0x0000, /* R653 */
2231 0x0000, /* R654 */
2232 0x0000, /* R655 */
2233 0x0000, /* R656 */
2234 0x0000, /* R657 */
2235 0x0000, /* R658 */
2236 0x0000, /* R659 */
2237 0x0000, /* R660 */
2238 0x0000, /* R661 */
2239 0x0000, /* R662 */
2240 0x0000, /* R663 */
2241 0x0000, /* R664 */
2242 0x0000, /* R665 */
2243 0x0000, /* R666 */
2244 0x0000, /* R667 */
2245 0x0000, /* R668 */
2246 0x0000, /* R669 */
2247 0x0000, /* R670 */
2248 0x0000, /* R671 */
2249 0x0000, /* R672 */
2250 0x0000, /* R673 */
2251 0x0000, /* R674 */
2252 0x0000, /* R675 */
2253 0x0000, /* R676 */
2254 0x0000, /* R677 */
2255 0x0000, /* R678 */
2256 0x0000, /* R679 */
2257 0x0000, /* R680 */
2258 0x0000, /* R681 */
2259 0x0000, /* R682 */
2260 0x0000, /* R683 */
2261 0x0000, /* R684 */
2262 0x0000, /* R685 */
2263 0x0000, /* R686 */
2264 0x0000, /* R687 */
2265 0x0000, /* R688 */
2266 0x0000, /* R689 */
2267 0x0000, /* R690 */
2268 0x0000, /* R691 */
2269 0x0000, /* R692 */
2270 0x0000, /* R693 */
2271 0x0000, /* R694 */
2272 0x0000, /* R695 */
2273 0x0000, /* R696 */
2274 0x0000, /* R697 */
2275 0x0000, /* R698 */
2276 0x0000, /* R699 */
2277 0x0000, /* R700 */
2278 0x0000, /* R701 */
2279 0x0000, /* R702 */
2280 0x0000, /* R703 */
2281 0x0000, /* R704 */
2282 0x0000, /* R705 */
2283 0x0000, /* R706 */
2284 0x0000, /* R707 */
2285 0x0000, /* R708 */
2286 0x0000, /* R709 */
2287 0x0000, /* R710 */
2288 0x0000, /* R711 */
2289 0x0000, /* R712 */
2290 0x0000, /* R713 */
2291 0x0000, /* R714 */
2292 0x0000, /* R715 */
2293 0x0000, /* R716 */
2294 0x0000, /* R717 */
2295 0x0000, /* R718 */
2296 0x0000, /* R719 */
2297 0x0000, /* R720 */
2298 0x0000, /* R721 */
2299 0x0000, /* R722 */
2300 0x0000, /* R723 */
2301 0x0000, /* R724 */
2302 0x0000, /* R725 */
2303 0x0000, /* R726 */
2304 0x0000, /* R727 */
2305 0x0000, /* R728 */
2306 0x0000, /* R729 */
2307 0x0000, /* R730 */
2308 0x0000, /* R731 */
2309 0x0000, /* R732 */
2310 0x0000, /* R733 */
2311 0x0000, /* R734 */
2312 0x0000, /* R735 */
2313 0x0000, /* R736 */
2314 0x0000, /* R737 */
2315 0x0000, /* R738 */
2316 0x0000, /* R739 */
2317 0x0000, /* R740 */
2318 0x0000, /* R741 */
2319 0x0000, /* R742 */
2320 0x0000, /* R743 */
2321 0x0000, /* R744 */
2322 0x0000, /* R745 */
2323 0x0000, /* R746 */
2324 0x0000, /* R747 */
2325 0x0000, /* R748 */
2326 0x0000, /* R749 */
2327 0x0000, /* R750 */
2328 0x0000, /* R751 */
2329 0x0000, /* R752 */
2330 0x0000, /* R753 */
2331 0x0000, /* R754 */
2332 0x0000, /* R755 */
2333 0x0000, /* R756 */
2334 0x0000, /* R757 */
2335 0x0000, /* R758 */
2336 0x0000, /* R759 */
2337 0x0000, /* R760 */
2338 0x0000, /* R761 */
2339 0x0000, /* R762 */
2340 0x0000, /* R763 */
2341 0x0000, /* R764 */
2342 0x0000, /* R765 */
2343 0x0000, /* R766 */
2344 0x0000, /* R767 */
2345 0x4050, /* R768 - AIF1 Control (1) */
2346 0x4000, /* R769 - AIF1 Control (2) */
2347 0x0000, /* R770 - AIF1 Master/Slave */
2348 0x0040, /* R771 - AIF1 BCLK */
2349 0x0040, /* R772 - AIF1ADC LRCLK */
2350 0x0040, /* R773 - AIF1DAC LRCLK */
2351 0x0004, /* R774 - AIF1DAC Data */
2352 0x0100, /* R775 - AIF1ADC Data */
2353 0x0000, /* R776 */
2354 0x0000, /* R777 */
2355 0x0000, /* R778 */
2356 0x0000, /* R779 */
2357 0x0000, /* R780 */
2358 0x0000, /* R781 */
2359 0x0000, /* R782 */
2360 0x0000, /* R783 */
2361 0x4050, /* R784 - AIF2 Control (1) */
2362 0x4000, /* R785 - AIF2 Control (2) */
2363 0x0000, /* R786 - AIF2 Master/Slave */
2364 0x0040, /* R787 - AIF2 BCLK */
2365 0x0040, /* R788 - AIF2ADC LRCLK */
2366 0x0040, /* R789 - AIF2DAC LRCLK */
2367 0x0000, /* R790 - AIF2DAC Data */
2368 0x0000, /* R791 - AIF2ADC Data */
2369 0x0000, /* R792 */
2370 0x0000, /* R793 */
2371 0x0000, /* R794 */
2372 0x0000, /* R795 */
2373 0x0000, /* R796 */
2374 0x0000, /* R797 */
2375 0x0000, /* R798 */
2376 0x0000, /* R799 */
2377 0x0000, /* R800 */
2378 0x0000, /* R801 */
2379 0x0000, /* R802 */
2380 0x0000, /* R803 */
2381 0x0000, /* R804 */
2382 0x0000, /* R805 */
2383 0x0000, /* R806 */
2384 0x0000, /* R807 */
2385 0x0000, /* R808 */
2386 0x0000, /* R809 */
2387 0x0000, /* R810 */
2388 0x0000, /* R811 */
2389 0x0000, /* R812 */
2390 0x0000, /* R813 */
2391 0x0000, /* R814 */
2392 0x0000, /* R815 */
2393 0x0000, /* R816 */
2394 0x0000, /* R817 */
2395 0x0000, /* R818 */
2396 0x0000, /* R819 */
2397 0x0000, /* R820 */
2398 0x0000, /* R821 */
2399 0x0000, /* R822 */
2400 0x0000, /* R823 */
2401 0x0000, /* R824 */
2402 0x0000, /* R825 */
2403 0x0000, /* R826 */
2404 0x0000, /* R827 */
2405 0x0000, /* R828 */
2406 0x0000, /* R829 */
2407 0x0000, /* R830 */
2408 0x0000, /* R831 */
2409 0x0000, /* R832 */
2410 0x0000, /* R833 */
2411 0x0000, /* R834 */
2412 0x0000, /* R835 */
2413 0x0000, /* R836 */
2414 0x0000, /* R837 */
2415 0x0000, /* R838 */
2416 0x0000, /* R839 */
2417 0x0000, /* R840 */
2418 0x0000, /* R841 */
2419 0x0000, /* R842 */
2420 0x0000, /* R843 */
2421 0x0000, /* R844 */
2422 0x0000, /* R845 */
2423 0x0000, /* R846 */
2424 0x0000, /* R847 */
2425 0x0000, /* R848 */
2426 0x0000, /* R849 */
2427 0x0000, /* R850 */
2428 0x0000, /* R851 */
2429 0x0000, /* R852 */
2430 0x0000, /* R853 */
2431 0x0000, /* R854 */
2432 0x0000, /* R855 */
2433 0x0000, /* R856 */
2434 0x0000, /* R857 */
2435 0x0000, /* R858 */
2436 0x0000, /* R859 */
2437 0x0000, /* R860 */
2438 0x0000, /* R861 */
2439 0x0000, /* R862 */
2440 0x0000, /* R863 */
2441 0x0000, /* R864 */
2442 0x0000, /* R865 */
2443 0x0000, /* R866 */
2444 0x0000, /* R867 */
2445 0x0000, /* R868 */
2446 0x0000, /* R869 */
2447 0x0000, /* R870 */
2448 0x0000, /* R871 */
2449 0x0000, /* R872 */
2450 0x0000, /* R873 */
2451 0x0000, /* R874 */
2452 0x0000, /* R875 */
2453 0x0000, /* R876 */
2454 0x0000, /* R877 */
2455 0x0000, /* R878 */
2456 0x0000, /* R879 */
2457 0x0000, /* R880 */
2458 0x0000, /* R881 */
2459 0x0000, /* R882 */
2460 0x0000, /* R883 */
2461 0x0000, /* R884 */
2462 0x0000, /* R885 */
2463 0x0000, /* R886 */
2464 0x0000, /* R887 */
2465 0x0000, /* R888 */
2466 0x0000, /* R889 */
2467 0x0000, /* R890 */
2468 0x0000, /* R891 */
2469 0x0000, /* R892 */
2470 0x0000, /* R893 */
2471 0x0000, /* R894 */
2472 0x0000, /* R895 */
2473 0x0000, /* R896 */
2474 0x0000, /* R897 */
2475 0x0000, /* R898 */
2476 0x0000, /* R899 */
2477 0x0000, /* R900 */
2478 0x0000, /* R901 */
2479 0x0000, /* R902 */
2480 0x0000, /* R903 */
2481 0x0000, /* R904 */
2482 0x0000, /* R905 */
2483 0x0000, /* R906 */
2484 0x0000, /* R907 */
2485 0x0000, /* R908 */
2486 0x0000, /* R909 */
2487 0x0000, /* R910 */
2488 0x0000, /* R911 */
2489 0x0000, /* R912 */
2490 0x0000, /* R913 */
2491 0x0000, /* R914 */
2492 0x0000, /* R915 */
2493 0x0000, /* R916 */
2494 0x0000, /* R917 */
2495 0x0000, /* R918 */
2496 0x0000, /* R919 */
2497 0x0000, /* R920 */
2498 0x0000, /* R921 */
2499 0x0000, /* R922 */
2500 0x0000, /* R923 */
2501 0x0000, /* R924 */
2502 0x0000, /* R925 */
2503 0x0000, /* R926 */
2504 0x0000, /* R927 */
2505 0x0000, /* R928 */
2506 0x0000, /* R929 */
2507 0x0000, /* R930 */
2508 0x0000, /* R931 */
2509 0x0000, /* R932 */
2510 0x0000, /* R933 */
2511 0x0000, /* R934 */
2512 0x0000, /* R935 */
2513 0x0000, /* R936 */
2514 0x0000, /* R937 */
2515 0x0000, /* R938 */
2516 0x0000, /* R939 */
2517 0x0000, /* R940 */
2518 0x0000, /* R941 */
2519 0x0000, /* R942 */
2520 0x0000, /* R943 */
2521 0x0000, /* R944 */
2522 0x0000, /* R945 */
2523 0x0000, /* R946 */
2524 0x0000, /* R947 */
2525 0x0000, /* R948 */
2526 0x0000, /* R949 */
2527 0x0000, /* R950 */
2528 0x0000, /* R951 */
2529 0x0000, /* R952 */
2530 0x0000, /* R953 */
2531 0x0000, /* R954 */
2532 0x0000, /* R955 */
2533 0x0000, /* R956 */
2534 0x0000, /* R957 */
2535 0x0000, /* R958 */
2536 0x0000, /* R959 */
2537 0x0000, /* R960 */
2538 0x0000, /* R961 */
2539 0x0000, /* R962 */
2540 0x0000, /* R963 */
2541 0x0000, /* R964 */
2542 0x0000, /* R965 */
2543 0x0000, /* R966 */
2544 0x0000, /* R967 */
2545 0x0000, /* R968 */
2546 0x0000, /* R969 */
2547 0x0000, /* R970 */
2548 0x0000, /* R971 */
2549 0x0000, /* R972 */
2550 0x0000, /* R973 */
2551 0x0000, /* R974 */
2552 0x0000, /* R975 */
2553 0x0000, /* R976 */
2554 0x0000, /* R977 */
2555 0x0000, /* R978 */
2556 0x0000, /* R979 */
2557 0x0000, /* R980 */
2558 0x0000, /* R981 */
2559 0x0000, /* R982 */
2560 0x0000, /* R983 */
2561 0x0000, /* R984 */
2562 0x0000, /* R985 */
2563 0x0000, /* R986 */
2564 0x0000, /* R987 */
2565 0x0000, /* R988 */
2566 0x0000, /* R989 */
2567 0x0000, /* R990 */
2568 0x0000, /* R991 */
2569 0x0000, /* R992 */
2570 0x0000, /* R993 */
2571 0x0000, /* R994 */
2572 0x0000, /* R995 */
2573 0x0000, /* R996 */
2574 0x0000, /* R997 */
2575 0x0000, /* R998 */
2576 0x0000, /* R999 */
2577 0x0000, /* R1000 */
2578 0x0000, /* R1001 */
2579 0x0000, /* R1002 */
2580 0x0000, /* R1003 */
2581 0x0000, /* R1004 */
2582 0x0000, /* R1005 */
2583 0x0000, /* R1006 */
2584 0x0000, /* R1007 */
2585 0x0000, /* R1008 */
2586 0x0000, /* R1009 */
2587 0x0000, /* R1010 */
2588 0x0000, /* R1011 */
2589 0x0000, /* R1012 */
2590 0x0000, /* R1013 */
2591 0x0000, /* R1014 */
2592 0x0000, /* R1015 */
2593 0x0000, /* R1016 */
2594 0x0000, /* R1017 */
2595 0x0000, /* R1018 */
2596 0x0000, /* R1019 */
2597 0x0000, /* R1020 */
2598 0x0000, /* R1021 */
2599 0x0000, /* R1022 */
2600 0x0000, /* R1023 */
2601 0x00C0, /* R1024 - AIF1 ADC1 Left Volume */
2602 0x00C0, /* R1025 - AIF1 ADC1 Right Volume */
2603 0x00C0, /* R1026 - AIF1 DAC1 Left Volume */
2604 0x00C0, /* R1027 - AIF1 DAC1 Right Volume */
2605 0x00C0, /* R1028 - AIF1 ADC2 Left Volume */
2606 0x00C0, /* R1029 - AIF1 ADC2 Right Volume */
2607 0x00C0, /* R1030 - AIF1 DAC2 Left Volume */
2608 0x00C0, /* R1031 - AIF1 DAC2 Right Volume */
2609 0x0000, /* R1032 */
2610 0x0000, /* R1033 */
2611 0x0000, /* R1034 */
2612 0x0000, /* R1035 */
2613 0x0000, /* R1036 */
2614 0x0000, /* R1037 */
2615 0x0000, /* R1038 */
2616 0x0000, /* R1039 */
2617 0x0000, /* R1040 - AIF1 ADC1 Filters */
2618 0x0000, /* R1041 - AIF1 ADC2 Filters */
2619 0x0000, /* R1042 */
2620 0x0000, /* R1043 */
2621 0x0000, /* R1044 */
2622 0x0000, /* R1045 */
2623 0x0000, /* R1046 */
2624 0x0000, /* R1047 */
2625 0x0000, /* R1048 */
2626 0x0000, /* R1049 */
2627 0x0000, /* R1050 */
2628 0x0000, /* R1051 */
2629 0x0000, /* R1052 */
2630 0x0000, /* R1053 */
2631 0x0000, /* R1054 */
2632 0x0000, /* R1055 */
2633 0x0200, /* R1056 - AIF1 DAC1 Filters (1) */
2634 0x0010, /* R1057 - AIF1 DAC1 Filters (2) */
2635 0x0200, /* R1058 - AIF1 DAC2 Filters (1) */
2636 0x0010, /* R1059 - AIF1 DAC2 Filters (2) */
2637 0x0000, /* R1060 */
2638 0x0000, /* R1061 */
2639 0x0000, /* R1062 */
2640 0x0000, /* R1063 */
2641 0x0000, /* R1064 */
2642 0x0000, /* R1065 */
2643 0x0000, /* R1066 */
2644 0x0000, /* R1067 */
2645 0x0000, /* R1068 */
2646 0x0000, /* R1069 */
2647 0x0000, /* R1070 */
2648 0x0000, /* R1071 */
2649 0x0000, /* R1072 */
2650 0x0000, /* R1073 */
2651 0x0000, /* R1074 */
2652 0x0000, /* R1075 */
2653 0x0000, /* R1076 */
2654 0x0000, /* R1077 */
2655 0x0000, /* R1078 */
2656 0x0000, /* R1079 */
2657 0x0000, /* R1080 */
2658 0x0000, /* R1081 */
2659 0x0000, /* R1082 */
2660 0x0000, /* R1083 */
2661 0x0000, /* R1084 */
2662 0x0000, /* R1085 */
2663 0x0000, /* R1086 */
2664 0x0000, /* R1087 */
2665 0x0098, /* R1088 - AIF1 DRC1 (1) */
2666 0x0845, /* R1089 - AIF1 DRC1 (2) */
2667 0x0000, /* R1090 - AIF1 DRC1 (3) */
2668 0x0000, /* R1091 - AIF1 DRC1 (4) */
2669 0x0000, /* R1092 - AIF1 DRC1 (5) */
2670 0x0000, /* R1093 */
2671 0x0000, /* R1094 */
2672 0x0000, /* R1095 */
2673 0x0000, /* R1096 */
2674 0x0000, /* R1097 */
2675 0x0000, /* R1098 */
2676 0x0000, /* R1099 */
2677 0x0000, /* R1100 */
2678 0x0000, /* R1101 */
2679 0x0000, /* R1102 */
2680 0x0000, /* R1103 */
2681 0x0098, /* R1104 - AIF1 DRC2 (1) */
2682 0x0845, /* R1105 - AIF1 DRC2 (2) */
2683 0x0000, /* R1106 - AIF1 DRC2 (3) */
2684 0x0000, /* R1107 - AIF1 DRC2 (4) */
2685 0x0000, /* R1108 - AIF1 DRC2 (5) */
2686 0x0000, /* R1109 */
2687 0x0000, /* R1110 */
2688 0x0000, /* R1111 */
2689 0x0000, /* R1112 */
2690 0x0000, /* R1113 */
2691 0x0000, /* R1114 */
2692 0x0000, /* R1115 */
2693 0x0000, /* R1116 */
2694 0x0000, /* R1117 */
2695 0x0000, /* R1118 */
2696 0x0000, /* R1119 */
2697 0x0000, /* R1120 */
2698 0x0000, /* R1121 */
2699 0x0000, /* R1122 */
2700 0x0000, /* R1123 */
2701 0x0000, /* R1124 */
2702 0x0000, /* R1125 */
2703 0x0000, /* R1126 */
2704 0x0000, /* R1127 */
2705 0x0000, /* R1128 */
2706 0x0000, /* R1129 */
2707 0x0000, /* R1130 */
2708 0x0000, /* R1131 */
2709 0x0000, /* R1132 */
2710 0x0000, /* R1133 */
2711 0x0000, /* R1134 */
2712 0x0000, /* R1135 */
2713 0x0000, /* R1136 */
2714 0x0000, /* R1137 */
2715 0x0000, /* R1138 */
2716 0x0000, /* R1139 */
2717 0x0000, /* R1140 */
2718 0x0000, /* R1141 */
2719 0x0000, /* R1142 */
2720 0x0000, /* R1143 */
2721 0x0000, /* R1144 */
2722 0x0000, /* R1145 */
2723 0x0000, /* R1146 */
2724 0x0000, /* R1147 */
2725 0x0000, /* R1148 */
2726 0x0000, /* R1149 */
2727 0x0000, /* R1150 */
2728 0x0000, /* R1151 */
2729 0x6318, /* R1152 - AIF1 DAC1 EQ Gains (1) */
2730 0x6300, /* R1153 - AIF1 DAC1 EQ Gains (2) */
2731 0x0FCA, /* R1154 - AIF1 DAC1 EQ Band 1 A */
2732 0x0400, /* R1155 - AIF1 DAC1 EQ Band 1 B */
2733 0x00D8, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
2734 0x1EB5, /* R1157 - AIF1 DAC1 EQ Band 2 A */
2735 0xF145, /* R1158 - AIF1 DAC1 EQ Band 2 B */
2736 0x0B75, /* R1159 - AIF1 DAC1 EQ Band 2 C */
2737 0x01C5, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
2738 0x1C58, /* R1161 - AIF1 DAC1 EQ Band 3 A */
2739 0xF373, /* R1162 - AIF1 DAC1 EQ Band 3 B */
2740 0x0A54, /* R1163 - AIF1 DAC1 EQ Band 3 C */
2741 0x0558, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
2742 0x168E, /* R1165 - AIF1 DAC1 EQ Band 4 A */
2743 0xF829, /* R1166 - AIF1 DAC1 EQ Band 4 B */
2744 0x07AD, /* R1167 - AIF1 DAC1 EQ Band 4 C */
2745 0x1103, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
2746 0x0564, /* R1169 - AIF1 DAC1 EQ Band 5 A */
2747 0x0559, /* R1170 - AIF1 DAC1 EQ Band 5 B */
2748 0x4000, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
2749 0x0000, /* R1172 */
2750 0x0000, /* R1173 */
2751 0x0000, /* R1174 */
2752 0x0000, /* R1175 */
2753 0x0000, /* R1176 */
2754 0x0000, /* R1177 */
2755 0x0000, /* R1178 */
2756 0x0000, /* R1179 */
2757 0x0000, /* R1180 */
2758 0x0000, /* R1181 */
2759 0x0000, /* R1182 */
2760 0x0000, /* R1183 */
2761 0x6318, /* R1184 - AIF1 DAC2 EQ Gains (1) */
2762 0x6300, /* R1185 - AIF1 DAC2 EQ Gains (2) */
2763 0x0FCA, /* R1186 - AIF1 DAC2 EQ Band 1 A */
2764 0x0400, /* R1187 - AIF1 DAC2 EQ Band 1 B */
2765 0x00D8, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
2766 0x1EB5, /* R1189 - AIF1 DAC2 EQ Band 2 A */
2767 0xF145, /* R1190 - AIF1 DAC2 EQ Band 2 B */
2768 0x0B75, /* R1191 - AIF1 DAC2 EQ Band 2 C */
2769 0x01C5, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
2770 0x1C58, /* R1193 - AIF1 DAC2 EQ Band 3 A */
2771 0xF373, /* R1194 - AIF1 DAC2 EQ Band 3 B */
2772 0x0A54, /* R1195 - AIF1 DAC2 EQ Band 3 C */
2773 0x0558, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
2774 0x168E, /* R1197 - AIF1 DAC2 EQ Band 4 A */
2775 0xF829, /* R1198 - AIF1 DAC2 EQ Band 4 B */
2776 0x07AD, /* R1199 - AIF1 DAC2 EQ Band 4 C */
2777 0x1103, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
2778 0x0564, /* R1201 - AIF1 DAC2 EQ Band 5 A */
2779 0x0559, /* R1202 - AIF1 DAC2 EQ Band 5 B */
2780 0x4000, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
2781 0x0000, /* R1204 */
2782 0x0000, /* R1205 */
2783 0x0000, /* R1206 */
2784 0x0000, /* R1207 */
2785 0x0000, /* R1208 */
2786 0x0000, /* R1209 */
2787 0x0000, /* R1210 */
2788 0x0000, /* R1211 */
2789 0x0000, /* R1212 */
2790 0x0000, /* R1213 */
2791 0x0000, /* R1214 */
2792 0x0000, /* R1215 */
2793 0x0000, /* R1216 */
2794 0x0000, /* R1217 */
2795 0x0000, /* R1218 */
2796 0x0000, /* R1219 */
2797 0x0000, /* R1220 */
2798 0x0000, /* R1221 */
2799 0x0000, /* R1222 */
2800 0x0000, /* R1223 */
2801 0x0000, /* R1224 */
2802 0x0000, /* R1225 */
2803 0x0000, /* R1226 */
2804 0x0000, /* R1227 */
2805 0x0000, /* R1228 */
2806 0x0000, /* R1229 */
2807 0x0000, /* R1230 */
2808 0x0000, /* R1231 */
2809 0x0000, /* R1232 */
2810 0x0000, /* R1233 */
2811 0x0000, /* R1234 */
2812 0x0000, /* R1235 */
2813 0x0000, /* R1236 */
2814 0x0000, /* R1237 */
2815 0x0000, /* R1238 */
2816 0x0000, /* R1239 */
2817 0x0000, /* R1240 */
2818 0x0000, /* R1241 */
2819 0x0000, /* R1242 */
2820 0x0000, /* R1243 */
2821 0x0000, /* R1244 */
2822 0x0000, /* R1245 */
2823 0x0000, /* R1246 */
2824 0x0000, /* R1247 */
2825 0x0000, /* R1248 */
2826 0x0000, /* R1249 */
2827 0x0000, /* R1250 */
2828 0x0000, /* R1251 */
2829 0x0000, /* R1252 */
2830 0x0000, /* R1253 */
2831 0x0000, /* R1254 */
2832 0x0000, /* R1255 */
2833 0x0000, /* R1256 */
2834 0x0000, /* R1257 */
2835 0x0000, /* R1258 */
2836 0x0000, /* R1259 */
2837 0x0000, /* R1260 */
2838 0x0000, /* R1261 */
2839 0x0000, /* R1262 */
2840 0x0000, /* R1263 */
2841 0x0000, /* R1264 */
2842 0x0000, /* R1265 */
2843 0x0000, /* R1266 */
2844 0x0000, /* R1267 */
2845 0x0000, /* R1268 */
2846 0x0000, /* R1269 */
2847 0x0000, /* R1270 */
2848 0x0000, /* R1271 */
2849 0x0000, /* R1272 */
2850 0x0000, /* R1273 */
2851 0x0000, /* R1274 */
2852 0x0000, /* R1275 */
2853 0x0000, /* R1276 */
2854 0x0000, /* R1277 */
2855 0x0000, /* R1278 */
2856 0x0000, /* R1279 */
2857 0x00C0, /* R1280 - AIF2 ADC Left Volume */
2858 0x00C0, /* R1281 - AIF2 ADC Right Volume */
2859 0x00C0, /* R1282 - AIF2 DAC Left Volume */
2860 0x00C0, /* R1283 - AIF2 DAC Right Volume */
2861 0x0000, /* R1284 */
2862 0x0000, /* R1285 */
2863 0x0000, /* R1286 */
2864 0x0000, /* R1287 */
2865 0x0000, /* R1288 */
2866 0x0000, /* R1289 */
2867 0x0000, /* R1290 */
2868 0x0000, /* R1291 */
2869 0x0000, /* R1292 */
2870 0x0000, /* R1293 */
2871 0x0000, /* R1294 */
2872 0x0000, /* R1295 */
2873 0x0000, /* R1296 - AIF2 ADC Filters */
2874 0x0000, /* R1297 */
2875 0x0000, /* R1298 */
2876 0x0000, /* R1299 */
2877 0x0000, /* R1300 */
2878 0x0000, /* R1301 */
2879 0x0000, /* R1302 */
2880 0x0000, /* R1303 */
2881 0x0000, /* R1304 */
2882 0x0000, /* R1305 */
2883 0x0000, /* R1306 */
2884 0x0000, /* R1307 */
2885 0x0000, /* R1308 */
2886 0x0000, /* R1309 */
2887 0x0000, /* R1310 */
2888 0x0000, /* R1311 */
2889 0x0200, /* R1312 - AIF2 DAC Filters (1) */
2890 0x0010, /* R1313 - AIF2 DAC Filters (2) */
2891 0x0000, /* R1314 */
2892 0x0000, /* R1315 */
2893 0x0000, /* R1316 */
2894 0x0000, /* R1317 */
2895 0x0000, /* R1318 */
2896 0x0000, /* R1319 */
2897 0x0000, /* R1320 */
2898 0x0000, /* R1321 */
2899 0x0000, /* R1322 */
2900 0x0000, /* R1323 */
2901 0x0000, /* R1324 */
2902 0x0000, /* R1325 */
2903 0x0000, /* R1326 */
2904 0x0000, /* R1327 */
2905 0x0000, /* R1328 */
2906 0x0000, /* R1329 */
2907 0x0000, /* R1330 */
2908 0x0000, /* R1331 */
2909 0x0000, /* R1332 */
2910 0x0000, /* R1333 */
2911 0x0000, /* R1334 */
2912 0x0000, /* R1335 */
2913 0x0000, /* R1336 */
2914 0x0000, /* R1337 */
2915 0x0000, /* R1338 */
2916 0x0000, /* R1339 */
2917 0x0000, /* R1340 */
2918 0x0000, /* R1341 */
2919 0x0000, /* R1342 */
2920 0x0000, /* R1343 */
2921 0x0098, /* R1344 - AIF2 DRC (1) */
2922 0x0845, /* R1345 - AIF2 DRC (2) */
2923 0x0000, /* R1346 - AIF2 DRC (3) */
2924 0x0000, /* R1347 - AIF2 DRC (4) */
2925 0x0000, /* R1348 - AIF2 DRC (5) */
2926 0x0000, /* R1349 */
2927 0x0000, /* R1350 */
2928 0x0000, /* R1351 */
2929 0x0000, /* R1352 */
2930 0x0000, /* R1353 */
2931 0x0000, /* R1354 */
2932 0x0000, /* R1355 */
2933 0x0000, /* R1356 */
2934 0x0000, /* R1357 */
2935 0x0000, /* R1358 */
2936 0x0000, /* R1359 */
2937 0x0000, /* R1360 */
2938 0x0000, /* R1361 */
2939 0x0000, /* R1362 */
2940 0x0000, /* R1363 */
2941 0x0000, /* R1364 */
2942 0x0000, /* R1365 */
2943 0x0000, /* R1366 */
2944 0x0000, /* R1367 */
2945 0x0000, /* R1368 */
2946 0x0000, /* R1369 */
2947 0x0000, /* R1370 */
2948 0x0000, /* R1371 */
2949 0x0000, /* R1372 */
2950 0x0000, /* R1373 */
2951 0x0000, /* R1374 */
2952 0x0000, /* R1375 */
2953 0x0000, /* R1376 */
2954 0x0000, /* R1377 */
2955 0x0000, /* R1378 */
2956 0x0000, /* R1379 */
2957 0x0000, /* R1380 */
2958 0x0000, /* R1381 */
2959 0x0000, /* R1382 */
2960 0x0000, /* R1383 */
2961 0x0000, /* R1384 */
2962 0x0000, /* R1385 */
2963 0x0000, /* R1386 */
2964 0x0000, /* R1387 */
2965 0x0000, /* R1388 */
2966 0x0000, /* R1389 */
2967 0x0000, /* R1390 */
2968 0x0000, /* R1391 */
2969 0x0000, /* R1392 */
2970 0x0000, /* R1393 */
2971 0x0000, /* R1394 */
2972 0x0000, /* R1395 */
2973 0x0000, /* R1396 */
2974 0x0000, /* R1397 */
2975 0x0000, /* R1398 */
2976 0x0000, /* R1399 */
2977 0x0000, /* R1400 */
2978 0x0000, /* R1401 */
2979 0x0000, /* R1402 */
2980 0x0000, /* R1403 */
2981 0x0000, /* R1404 */
2982 0x0000, /* R1405 */
2983 0x0000, /* R1406 */
2984 0x0000, /* R1407 */
2985 0x6318, /* R1408 - AIF2 EQ Gains (1) */
2986 0x6300, /* R1409 - AIF2 EQ Gains (2) */
2987 0x0FCA, /* R1410 - AIF2 EQ Band 1 A */
2988 0x0400, /* R1411 - AIF2 EQ Band 1 B */
2989 0x00D8, /* R1412 - AIF2 EQ Band 1 PG */
2990 0x1EB5, /* R1413 - AIF2 EQ Band 2 A */
2991 0xF145, /* R1414 - AIF2 EQ Band 2 B */
2992 0x0B75, /* R1415 - AIF2 EQ Band 2 C */
2993 0x01C5, /* R1416 - AIF2 EQ Band 2 PG */
2994 0x1C58, /* R1417 - AIF2 EQ Band 3 A */
2995 0xF373, /* R1418 - AIF2 EQ Band 3 B */
2996 0x0A54, /* R1419 - AIF2 EQ Band 3 C */
2997 0x0558, /* R1420 - AIF2 EQ Band 3 PG */
2998 0x168E, /* R1421 - AIF2 EQ Band 4 A */
2999 0xF829, /* R1422 - AIF2 EQ Band 4 B */
3000 0x07AD, /* R1423 - AIF2 EQ Band 4 C */
3001 0x1103, /* R1424 - AIF2 EQ Band 4 PG */
3002 0x0564, /* R1425 - AIF2 EQ Band 5 A */
3003 0x0559, /* R1426 - AIF2 EQ Band 5 B */
3004 0x4000, /* R1427 - AIF2 EQ Band 5 PG */
3005 0x0000, /* R1428 */
3006 0x0000, /* R1429 */
3007 0x0000, /* R1430 */
3008 0x0000, /* R1431 */
3009 0x0000, /* R1432 */
3010 0x0000, /* R1433 */
3011 0x0000, /* R1434 */
3012 0x0000, /* R1435 */
3013 0x0000, /* R1436 */
3014 0x0000, /* R1437 */
3015 0x0000, /* R1438 */
3016 0x0000, /* R1439 */
3017 0x0000, /* R1440 */
3018 0x0000, /* R1441 */
3019 0x0000, /* R1442 */
3020 0x0000, /* R1443 */
3021 0x0000, /* R1444 */
3022 0x0000, /* R1445 */
3023 0x0000, /* R1446 */
3024 0x0000, /* R1447 */
3025 0x0000, /* R1448 */
3026 0x0000, /* R1449 */
3027 0x0000, /* R1450 */
3028 0x0000, /* R1451 */
3029 0x0000, /* R1452 */
3030 0x0000, /* R1453 */
3031 0x0000, /* R1454 */
3032 0x0000, /* R1455 */
3033 0x0000, /* R1456 */
3034 0x0000, /* R1457 */
3035 0x0000, /* R1458 */
3036 0x0000, /* R1459 */
3037 0x0000, /* R1460 */
3038 0x0000, /* R1461 */
3039 0x0000, /* R1462 */
3040 0x0000, /* R1463 */
3041 0x0000, /* R1464 */
3042 0x0000, /* R1465 */
3043 0x0000, /* R1466 */
3044 0x0000, /* R1467 */
3045 0x0000, /* R1468 */
3046 0x0000, /* R1469 */
3047 0x0000, /* R1470 */
3048 0x0000, /* R1471 */
3049 0x0000, /* R1472 */
3050 0x0000, /* R1473 */
3051 0x0000, /* R1474 */
3052 0x0000, /* R1475 */
3053 0x0000, /* R1476 */
3054 0x0000, /* R1477 */
3055 0x0000, /* R1478 */
3056 0x0000, /* R1479 */
3057 0x0000, /* R1480 */
3058 0x0000, /* R1481 */
3059 0x0000, /* R1482 */
3060 0x0000, /* R1483 */
3061 0x0000, /* R1484 */
3062 0x0000, /* R1485 */
3063 0x0000, /* R1486 */
3064 0x0000, /* R1487 */
3065 0x0000, /* R1488 */
3066 0x0000, /* R1489 */
3067 0x0000, /* R1490 */
3068 0x0000, /* R1491 */
3069 0x0000, /* R1492 */
3070 0x0000, /* R1493 */
3071 0x0000, /* R1494 */
3072 0x0000, /* R1495 */
3073 0x0000, /* R1496 */
3074 0x0000, /* R1497 */
3075 0x0000, /* R1498 */
3076 0x0000, /* R1499 */
3077 0x0000, /* R1500 */
3078 0x0000, /* R1501 */
3079 0x0000, /* R1502 */
3080 0x0000, /* R1503 */
3081 0x0000, /* R1504 */
3082 0x0000, /* R1505 */
3083 0x0000, /* R1506 */
3084 0x0000, /* R1507 */
3085 0x0000, /* R1508 */
3086 0x0000, /* R1509 */
3087 0x0000, /* R1510 */
3088 0x0000, /* R1511 */
3089 0x0000, /* R1512 */
3090 0x0000, /* R1513 */
3091 0x0000, /* R1514 */
3092 0x0000, /* R1515 */
3093 0x0000, /* R1516 */
3094 0x0000, /* R1517 */
3095 0x0000, /* R1518 */
3096 0x0000, /* R1519 */
3097 0x0000, /* R1520 */
3098 0x0000, /* R1521 */
3099 0x0000, /* R1522 */
3100 0x0000, /* R1523 */
3101 0x0000, /* R1524 */
3102 0x0000, /* R1525 */
3103 0x0000, /* R1526 */
3104 0x0000, /* R1527 */
3105 0x0000, /* R1528 */
3106 0x0000, /* R1529 */
3107 0x0000, /* R1530 */
3108 0x0000, /* R1531 */
3109 0x0000, /* R1532 */
3110 0x0000, /* R1533 */
3111 0x0000, /* R1534 */
3112 0x0000, /* R1535 */
3113 0x0000, /* R1536 - DAC1 Mixer Volumes */
3114 0x0000, /* R1537 - DAC1 Left Mixer Routing */
3115 0x0000, /* R1538 - DAC1 Right Mixer Routing */
3116 0x0000, /* R1539 - DAC2 Mixer Volumes */
3117 0x0000, /* R1540 - DAC2 Left Mixer Routing */
3118 0x0000, /* R1541 - DAC2 Right Mixer Routing */
3119 0x0000, /* R1542 - AIF1 ADC1 Left Mixer Routing */
3120 0x0000, /* R1543 - AIF1 ADC1 Right Mixer Routing */
3121 0x0000, /* R1544 - AIF1 ADC2 Left Mixer Routing */
3122 0x0000, /* R1545 - AIF1 ADC2 Right mixer Routing */
3123 0x0000, /* R1546 */
3124 0x0000, /* R1547 */
3125 0x0000, /* R1548 */
3126 0x0000, /* R1549 */
3127 0x0000, /* R1550 */
3128 0x0000, /* R1551 */
3129 0x02C0, /* R1552 - DAC1 Left Volume */
3130 0x02C0, /* R1553 - DAC1 Right Volume */
3131 0x02C0, /* R1554 - DAC2 Left Volume */
3132 0x02C0, /* R1555 - DAC2 Right Volume */
3133 0x0000, /* R1556 - DAC Softmute */
3134 0x0000, /* R1557 */
3135 0x0000, /* R1558 */
3136 0x0000, /* R1559 */
3137 0x0000, /* R1560 */
3138 0x0000, /* R1561 */
3139 0x0000, /* R1562 */
3140 0x0000, /* R1563 */
3141 0x0000, /* R1564 */
3142 0x0000, /* R1565 */
3143 0x0000, /* R1566 */
3144 0x0000, /* R1567 */
3145 0x0002, /* R1568 - Oversampling */
3146 0x0000, /* R1569 - Sidetone */
3147};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 04:40:44 -0400