Added missing tegra files.HEADmaster

17 files changed, 1945 insertions, 0 deletions

diff --git a/include/media/ad5820.h b/include/media/ad5820.h
new file mode 100644
index 00000000000..c3e71011340
--- /dev/null
+++ b/include/media/ad5820.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * Contributors:
+ *      Sachin Nikam <snikam@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __AD5820_H__
+#define __AD5820_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define AD5820_IOCTL_GET_CONFIG   _IOR('o', 1, struct ad5820_config)
+#define AD5820_IOCTL_SET_POSITION _IOW('o', 2, u32)
+
+struct ad5820_config {
+        __u32 settle_time;
+        __u32 actuator_range;
+        __u32 pos_low;
+        __u32 pos_high;
+        float focal_length;
+        float fnumber;
+        float max_aperture;
+};
+
+#endif  /* __AD5820_H__ */
+
diff --git a/include/media/ar0832_main.h b/include/media/ar0832_main.h
new file mode 100644
index 00000000000..f5e3713b46f
--- /dev/null
+++ b/include/media/ar0832_main.h
@@ -0,0 +1,106 @@
+/*
+* ar0832_main.h
+*
+* Copyright (c) 2011, NVIDIA, All Rights Reserved.
+*
+* This file is licensed under the terms of the GNU General Public License
+* version 2. This program is licensed "as is" without any warranty of any
+* kind, whether express or implied.
+*/
+
+#ifndef __AR0832_MAIN_H__
+#define __AR0832_MAIN_H__
+
+#include <linux/ioctl.h> /* For IOCTL macros */
+
+#define AR0832_IOCTL_SET_MODE                   _IOW('o', 0x01, struct ar0832_mode)
+#define AR0832_IOCTL_SET_FRAME_LENGTH           _IOW('o', 0x02, __u32)
+#define AR0832_IOCTL_SET_COARSE_TIME            _IOW('o', 0x03, __u32)
+#define AR0832_IOCTL_SET_GAIN                   _IOW('o', 0x04, __u16)
+#define AR0832_IOCTL_GET_STATUS                 _IOR('o', 0x05, __u8)
+#define AR0832_IOCTL_GET_OTP                    _IOR('o', 0x06, struct ar0832_otp_data)
+#define AR0832_IOCTL_TEST_PATTERN               _IOW('o', 0x07, enum ar0832_test_pattern)
+#define AR0832_IOCTL_SET_POWER_ON               _IOW('o', 0x08, struct ar0832_mode)
+#define AR0832_IOCTL_SET_SENSOR_REGION          _IOW('o', 0x09, struct ar0832_stereo_region)
+
+#define AR0832_FOCUSER_IOCTL_GET_CONFIG         _IOR('o', 0x10, struct ar0832_focuser_config)
+#define AR0832_FOCUSER_IOCTL_SET_POSITION       _IOW('o', 0x11, __u32)
+
+#define AR0832_IOCTL_GET_SENSOR_ID              _IOR('o', 0x12, __u16)
+
+#define AR0832_SENSOR_ID_8141                   0x1006
+#define AR0832_SENSOR_ID_8140                   0x3006
+
+enum ar0832_test_pattern {
+        TEST_PATTERN_NONE,
+        TEST_PATTERN_COLORBARS,
+        TEST_PATTERN_CHECKERBOARD
+};
+
+struct ar0832_otp_data {
+        /* Only the first 5 bytes are actually used. */
+        __u8 sensor_serial_num[6];
+        __u8 part_num[8];
+        __u8 lens_id[1];
+        __u8 manufacture_id[2];
+        __u8 factory_id[2];
+        __u8 manufacture_date[9];
+        __u8 manufacture_line[2];
+
+        __u32 module_serial_num;
+        __u8 focuser_liftoff[2];
+        __u8 focuser_macro[2];
+        __u8 reserved1[12];
+        __u8 shutter_cal[16];
+        __u8 reserved2[183];
+
+        /* Big-endian. CRC16 over 0x00-0x41 (inclusive) */
+        __u16 crc;
+        __u8 reserved3[3];
+        __u8 auto_load[2];
+} __attribute__ ((packed));
+
+struct ar0832_mode {
+        int xres;
+        int yres;
+        __u32 frame_length;
+        __u32 coarse_time;
+        __u16 gain;
+        int stereo;
+};
+
+struct ar0832_point{
+        int x;
+        int y;
+};
+
+struct ar0832_reg {
+        __u16 addr;
+        __u16 val;
+};
+
+struct ar0832_stereo_region {
+        int camera_index;
+        struct ar0832_point image_start;
+        struct ar0832_point image_end;
+};
+
+struct ar0832_focuser_config {
+        __u32 settle_time;
+        __u32 actuator_range;
+        __u32 pos_low;
+        __u32 pos_high;
+        __u32 focal_length;
+        __u32 fnumber;
+        __u32 max_aperture;
+};
+
+#ifdef __KERNEL__
+struct ar0832_platform_data {
+        int (*power_on)(int is_stereo);
+        int (*power_off)(int is_stereo);
+        char *id;
+};
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/media/nvc.h b/include/media/nvc.h
new file mode 100644
index 00000000000..9b24b0ea019
--- /dev/null
+++ b/include/media/nvc.h
@@ -0,0 +1,284 @@
+/* Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __NVC_H__
+#define __NVC_H__
+
+#include <linux/ioctl.h>
+
+#define NVC_INT2FLOAT_DIVISOR_1K        1000
+#define NVC_INT2FLOAT_DIVISOR_1M        1000000
+#define NVC_INT2FLOAT_DIVISOR           1000
+
+struct nvc_param {
+        int param;
+        __u32 sizeofvalue;
+        void *p_value;
+} __packed;
+
+enum nvc_params {
+        NVC_PARAM_EXPOSURE = 0,
+        NVC_PARAM_GAIN,
+        NVC_PARAM_FRAMERATE,
+        NVC_PARAM_MAX_FRAMERATE,
+        NVC_PARAM_INPUT_CLOCK,
+        NVC_PARAM_LOCUS,
+        NVC_PARAM_FLASH_CAPS,
+        NVC_PARAM_FLASH_LEVEL,
+        NVC_PARAM_FLASH_PIN_STATE,
+        NVC_PARAM_TORCH_CAPS,
+        NVC_PARAM_TORCH_LEVEL,
+        NVC_PARAM_FOCAL_LEN,
+        NVC_PARAM_MAX_APERTURE,
+        NVC_PARAM_FNUMBER,
+        NVC_PARAM_EXPOSURE_LIMITS,
+        NVC_PARAM_GAIN_LIMITS,
+        NVC_PARAM_FRAMERATE_LIMITS,
+        NVC_PARAM_FRAME_RATES,
+        NVC_PARAM_CLOCK_LIMITS,
+        NVC_PARAM_EXP_LATCH_TIME,
+        NVC_PARAM_REGION_USED,
+        NVC_PARAM_CALIBRATION_DATA,
+        NVC_PARAM_CALIBRATION_OVERRIDES,
+        NVC_PARAM_SELF_TEST,
+        NVC_PARAM_STS,
+        NVC_PARAM_TESTMODE,
+        NVC_PARAM_EXPECTED_VALUES,
+        NVC_PARAM_RESET,
+        NVC_PARAM_OPTIMIZE_RES,
+        NVC_PARAM_DETECT_COLOR_TEMP,
+        NVC_PARAM_LINES_PER_SEC,
+        NVC_PARAM_CAPS,
+        NVC_PARAM_CUSTOM_BLOCK_INFO,
+        NVC_PARAM_STEREO_CAP,
+        NVC_PARAM_FOCUS_STEREO,
+        NVC_PARAM_STEREO,
+        NVC_PARAM_INHERENT_GAIN,
+        NVC_PARAM_VIEW_ANGLE_H,
+        NVC_PARAM_VIEW_ANGLE_V,
+        NVC_PARAM_ISP_SETTING,
+        NVC_PARAM_OPERATION_MODE,
+        NVC_PARAM_SUPPORT_ISP,
+        NVC_PARAM_AWB_LOCK,
+        NVC_PARAM_AE_LOCK,
+        NVC_PARAM_RES_CHANGE_WAIT_TIME,
+        NVC_PARAM_FACTORY_CALIBRATION_DATA,
+        NVC_PARAM_DEV_ID,
+        NVC_PARAM_GROUP_HOLD,
+        NVC_PARAM_BEGIN_VENDOR_EXTENSIONS = 0x10000000,
+        NVC_PARAM_CALIBRATION_STATUS,
+        NVC_PARAM_TEST_PATTERN,
+        NVC_PARAM_MODULE_INFO,
+        NVC_PARAM_FLASH_MAX_POWER,
+        NVC_PARAM_DIRECTION,
+        NVC_PARAM_SENSOR_TYPE,
+        NVC_PARAM_DLI_CHECK,
+        NVC_PARAM_PARALLEL_DLI_CHECK,
+        NVC_PARAM_BRACKET_CAPS,
+        NVC_PARAM_NUM,
+        NVC_PARAM_I2C,
+        NVC_PARAM_FORCE32 = 0x7FFFFFFF
+};
+
+/* sync off */
+#define NVC_SYNC_OFF                    0
+/* use only this device (the one receiving the call) */
+#define NVC_SYNC_MASTER                 1
+/* use only the synced device (the "other" device) */
+#define NVC_SYNC_SLAVE                  2
+/* use both synced devices at the same time */
+#define NVC_SYNC_STEREO                 3
+
+#define NVC_RESET_HARD                  0
+#define NVC_RESET_SOFT                  1
+
+struct nvc_param_isp {
+        int attr;
+        void *p_data;
+        __u32 data_size;
+} __packed;
+
+struct nvc_isp_focus_param {
+        __s32 min_pos;
+        __s32 max_pos;
+        __s32 hyperfocal;
+        __s32 macro;
+        __s32 powersave;
+} __packed;
+
+struct nvc_isp_focus_pos {
+        __u32 is_auto;
+        __s32 value;
+} __packed;
+
+struct nvc_isp_focus_region {
+        __u32 num_region;
+        __s32 value;
+} __packed;
+
+enum nvc_params_isp {
+        NVC_PARAM_ISP_FOCUS_CAF = 16389,
+        NVC_PARAM_ISP_FOCUS_CAF_PAUSE,
+        NVC_PARAM_ISP_FOCUS_CAF_STS,
+        NVC_PARAM_ISP_FOCUS_POS = 16407,
+        NVC_PARAM_ISP_FOCUS_RANGE,
+        NVC_PARAM_ISP_FOCUS_AF_RGN = 16413,
+        NVC_PARAM_ISP_FOCUS_AF_RGN_MASK,
+        NVC_PARAM_ISP_FOCUS_AF_RGN_STS,
+        NVC_PARAM_ISP_FOCUS_CTRL = 16424,
+        NVC_PARAM_ISP_FOCUS_TRGR,
+        NVC_PARAM_ISP_FOCUS_STS,
+};
+
+#define NVC_PARAM_ISP_FOCUS_STS_BUSY    0
+#define NVC_PARAM_ISP_FOCUS_STS_LOCKD   1
+#define NVC_PARAM_ISP_FOCUS_STS_FAILD   2
+#define NVC_PARAM_ISP_FOCUS_STS_ERR     3
+
+#define NVC_PARAM_ISP_FOCUS_CTRL_ON     0
+#define NVC_PARAM_ISP_FOCUS_CTRL_OFF    1
+#define NVC_PARAM_ISP_FOCUS_CTRL_AUTO   2
+#define NVC_PARAM_ISP_FOCUS_CTRL_ALOCK  3
+
+#define NVC_PARAM_ISP_FOCUS_CAF_CONVRG  1
+#define NVC_PARAM_ISP_FOCUS_CAF_SEARCH  2
+
+#define NVC_PARAM_ISP_FOCUS_POS_INF     0
+
+
+#define NVC_IOCTL_PWR_WR                _IOW('o', 102, int)
+#define NVC_IOCTL_PWR_RD                _IOW('o', 103, int)
+#define NVC_IOCTL_PARAM_WR              _IOW('o', 104, struct nvc_param)
+#define NVC_IOCTL_PARAM_RD              _IOWR('o', 105, struct nvc_param)
+#define NVC_IOCTL_PARAM_ISP_RD          _IOWR('o', 200, struct nvc_param_isp)
+#define NVC_IOCTL_PARAM_ISP_WR          _IOWR('o', 201, struct nvc_param_isp)
+
+
+#ifdef __KERNEL__
+
+#include <linux/regulator/consumer.h>
+
+/* The NVC_CFG_ defines are for the .cfg entry in the
+ * platform data structure.
+ */
+/* Device not registered if not found */
+#define NVC_CFG_NODEV                   (1 << 0)
+/* Don't return errors */
+#define NVC_CFG_NOERR                   (1 << 1)
+/* Always go to _PWR_STDBY instead of _PWR_OFF */
+#define NVC_CFG_OFF2STDBY               (1 << 2)
+/* Init device at sys boot */
+#define NVC_CFG_BOOT_INIT               (1 << 3)
+/* Sync mode uses an I2C MUX to send at same time */
+#define NVC_CFG_SYNC_I2C_MUX            (1 << 4)
+
+/* Expected higher level power calls are:
+ * 1 = OFF
+ * 2 = STANDBY
+ * 3 = ON
+ * These will be multiplied by 2 before given to the driver's PM code that
+ * uses the _PWR_ defines. This allows us to insert defines to give more power
+ * granularity and still remain linear with regards to the power usage and
+ * full power state transition latency for easy implementation of PM
+ * algorithms.
+ * The PM actions:
+ * _PWR_ERR = Non-valid state.
+ * _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms.
+ * _PWR_OFF = Device, regulators, clocks, etc is turned off.  The longest
+ *            transition time to _PWR_ON is from this state.
+ * _PWR_STDBY_OFF = Device is useless but powered.  No communication possible.
+ *                  Device does not retain programming.  Main purpose is for
+ *                  faster return to _PWR_ON without regulator delays.
+ * _PWR_STDBY = Device is in standby.  Device retains programming.
+ * _PWR_COMM = Device is powered enough to communicate with the device.
+ * _PWR_ON = Device is at full power with active output.
+ *
+ * The kernel drivers treat these calls as Guaranteed Level Of Service.
+ */
+
+#define NVC_PWR_ERR                     0
+#define NVC_PWR_OFF_FORCE               1
+#define NVC_PWR_OFF                     2
+#define NVC_PWR_STDBY_OFF               3
+#define NVC_PWR_STDBY                   4
+#define NVC_PWR_COMM                    5
+#define NVC_PWR_ON                      6
+
+struct nvc_regulator_init {
+        unsigned vreg_num;
+        const char *vreg_name;
+};
+
+struct nvc_regulator {
+        bool vreg_flag;
+        struct regulator *vreg;
+        const char *vreg_name;
+};
+
+/* The GPIO mechanism uses the _gpio_type in the device's header file as a key
+ * to define all the possible GPIO's the device will need.  The key is used to
+ * combine the GPIO's defined in the platform board file using the
+ * nvc_gpio_pdata structure with the nvc_gpio structure in the nvc kernel
+ * driver.
+ */
+struct nvc_gpio_pdata {
+        /* use a _gpio_type enum from the device's header file */
+        unsigned gpio_type;
+        /* the GPIO system number */
+        unsigned gpio;
+        /* init_en is typically set to true for all GPIO's used by the driver.
+         * However, some GPIO's are used by multiple drivers (CSI MUX, reset,
+         * etc.).  In this case, this is set true for only one of the drivers
+         * that uses the GPIO and false for the others.  If the platform board
+         * file initializes the GPIO, then this is false for all of the drivers
+         * using the GPIO.
+         */
+        bool init_en;
+        /* this defines the assert level for the general purpose GPIO's
+         * (_GPIO_TYPE_GPx, etc.).  The _GPIO_TYPE_GPx can be used for a GPIO
+         * that the driver doesn't know about but is needed in order for the
+         * device to work (CSI select, regulator, etc.).  The driver will
+         * blindly assert the GPIO when the device is operational and deassert
+         * when the device is turned off.
+         */
+        bool active_high;
+};
+
+struct nvc_gpio_init {
+        /* key to match in nvc_gpio_pdata */
+        unsigned gpio_type;
+        /* same as in gpio.h */
+        unsigned long flags;
+        /* same as in gpio.h */
+        const char *label;
+        /* used instead of nvc_gpio_pdata.active_high if use_flags true */
+        bool active_high;
+        /* false if nvc_gpio_pdata.active_high used else flags is used */
+        bool use_flags;
+};
+
+struct nvc_gpio {
+        unsigned gpio; /* system GPIO number */
+        bool own; /* gets set if driver initializes */
+        bool active_high; /* used for GP GPIOs */
+        bool flag; /* scratch flag for driver implementation */
+};
+
+#endif /* __KERNEL__ */
+
+#endif /* __NVC_H__ */
+
diff --git a/include/media/nvc_focus.h b/include/media/nvc_focus.h
new file mode 100644
index 00000000000..bed9df11a34
--- /dev/null
+++ b/include/media/nvc_focus.h
@@ -0,0 +1,63 @@
+/* Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __NVC_FOCUS_H__
+#define __NVC_FOCUS_H__
+
+/* NVC_FOCUS_CAP_VER0: invalid */
+/* NVC_FOCUS_CAP_VER1:
+ * __u32 version
+ * __u32 actuator_range
+ * __u32 settle_time
+ */
+#define NVC_FOCUS_CAP_VER1              1
+/* NVC_FOCUS_CAP_VER2 adds:
+ * __u32 focus_macro;
+ * __u32 focus_hyper;
+ * __u32 focus_infinity;
+ */
+#define NVC_FOCUS_CAP_VER2              2
+#define NVC_FOCUS_CAP_VER               2 /* latest version */
+
+enum nvc_focus_sts {
+        NVC_FOCUS_STS_UNKNOWN           = 1,
+        NVC_FOCUS_STS_NO_DEVICE,
+        NVC_FOCUS_STS_INITIALIZING,
+        NVC_FOCUS_STS_INIT_ERR,
+        NVC_FOCUS_STS_WAIT_FOR_MOVE_END,
+        NVC_FOCUS_STS_WAIT_FOR_SETTLE,
+        NVC_FOCUS_STS_LENS_SETTLED,
+        NVC_FOCUS_STS_FORCE32           = 0x7FFFFFFF
+};
+
+struct nvc_focus_nvc {
+        __u32 focal_length;
+        __u32 fnumber;
+        __u32 max_aperature;
+} __packed;
+
+struct nvc_focus_cap {
+        __u32 version;
+        __u32 actuator_range;
+        __u32 settle_time;
+        __u32 focus_macro;
+        __u32 focus_hyper;
+        __u32 focus_infinity;
+} __packed;
+
+#endif /* __NVC_FOCUS_H__ */
+
diff --git a/include/media/nvc_image.h b/include/media/nvc_image.h
new file mode 100644
index 00000000000..1bf884d8122
--- /dev/null
+++ b/include/media/nvc_image.h
@@ -0,0 +1,194 @@
+/* Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __NVC_IMAGE_H__
+#define __NVC_IMAGE_H__
+
+#include <linux/ioctl.h>
+
+#define NVC_IMAGER_API_CAPS_VER         2
+#define NVC_IMAGER_API_STATIC_VER       1
+#define NVC_IMAGER_API_DYNAMIC_VER      1
+#define NVC_IMAGER_API_BAYER_VER        1
+
+#define NVC_IMAGER_TEST_NONE            0
+#define NVC_IMAGER_TEST_COLORBARS       1
+#define NVC_IMAGER_TEST_CHECKERBOARD    2
+#define NVC_IMAGER_TEST_WALKING1S       3
+
+#define NVC_IMAGER_CROPMODE_NONE        1
+#define NVC_IMAGER_CROPMODE_PARTIAL     2
+
+#define NVC_IMAGER_TYPE_HUH             0
+#define NVC_IMAGER_TYPE_RAW             1
+#define NVC_IMAGER_TYPE_SOC             2
+
+#define NVC_IMAGER_INTERFACE_MIPI_A     3
+#define NVC_IMAGER_INTERFACE_MIPI_B     4
+#define NVC_IMAGER_INTERFACE_MIPI_AB    5
+
+#define NVC_IMAGER_IDENTIFIER_MAX       32
+#define NVC_IMAGER_FORMAT_MAX           4
+#define NVC_IMAGER_CLOCK_PROFILE_MAX    2
+#define NVC_IMAGER_CAPABILITIES_END     ((0x3434 << 16) | \
+                                        NVC_IMAGER_API_CAPS_VER)
+
+#define NVC_IMAGER_INT2FLOAT_DIVISOR    1000
+
+#define NVC_FOCUS_INTERNAL              (0x665F4E5643414D69ULL)
+#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF))
+#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF))
+
+
+struct nvc_imager_static_nvc {
+        __u32 api_version;
+        __u32 sensor_type;
+        __u32 sensor_id;
+        __u32 sensor_id_minor;
+        __u32 focal_len;
+        __u32 max_aperture;
+        __u32 fnumber;
+        __u32 view_angle_h;
+        __u32 view_angle_v;
+        __u32 stereo_cap;
+        __u32 res_chg_wait_time;
+        __u8 support_isp;
+        __u8 align1;
+        __u8 align2;
+        __u8 align3;
+        __u32 place_holder1;
+        __u32 place_holder2;
+        __u32 place_holder3;
+        __u32 place_holder4;
+} __packed;
+
+struct nvc_imager_dynamic_nvc {
+        __u32 api_version;
+        __s32 region_start_x;
+        __s32 region_start_y;
+        __u32 x_scale;
+        __u32 y_scale;
+        __u32 bracket_caps;
+        __u32 flush_count;
+        __u32 init_intra_frame_skip;
+        __u32 ss_intra_frame_skip;
+        __u32 ss_frame_number;
+        __u32 coarse_time;
+        __u32 max_coarse_diff;
+        __u32 min_exposure_course;
+        __u32 max_exposure_course;
+        __u32 diff_integration_time;
+        __u32 line_length;
+        __u32 frame_length;
+        __u32 min_frame_length;
+        __u32 max_frame_length;
+        __u32 min_gain;
+        __u32 max_gain;
+        __u32 inherent_gain;
+        __u32 inherent_gain_bin_en;
+        __u8 support_bin_control;
+        __u8 support_fast_mode;
+        __u8 align2;
+        __u8 align3;
+        __u32 pll_mult;
+        __u32 pll_div;
+        __u32 place_holder1;
+        __u32 place_holder2;
+        __u32 place_holder3;
+        __u32 place_holder4;
+} __packed;
+
+struct nvc_imager_bayer {
+        __u32 api_version;
+        __s32 res_x;
+        __s32 res_y;
+        __u32 frame_length;
+        __u32 coarse_time;
+        __u32 gain;
+        __u8 bin_en;
+        __u8 align1;
+        __u8 align2;
+        __u8 align3;
+        __u32 place_holder1;
+        __u32 place_holder2;
+        __u32 place_holder3;
+        __u32 place_holder4;
+} __packed;
+
+struct nvc_imager_mode {
+        __s32 res_x;
+        __s32 res_y;
+        __s32 active_start_x;
+        __s32 active_stary_y;
+        __u32 peak_frame_rate;
+        __u32 pixel_aspect_ratio;
+        __u32 pll_multiplier;
+        __u32 crop_mode;
+} __packed;
+
+struct nvc_imager_dnvc {
+        __s32 res_x;
+        __s32 res_y;
+        struct nvc_imager_mode *p_mode;
+        struct nvc_imager_dynamic_nvc *p_dnvc;
+} __packed;
+
+struct nvc_imager_mode_list {
+        struct nvc_imager_mode *p_modes;
+        __u32 *p_num_mode;
+} __packed;
+
+struct nvc_clock_profile {
+        __u32 external_clock_khz;
+        __u32 clock_multiplier;
+} __packed;
+
+struct nvc_imager_cap {
+        char identifier[NVC_IMAGER_IDENTIFIER_MAX];
+        __u32 sensor_nvc_interface;
+        __u32 pixel_types[NVC_IMAGER_FORMAT_MAX];
+        __u32 orientation;
+        __u32 direction;
+        __u32 initial_clock_rate_khz;
+        struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX];
+        __u32 h_sync_edge;
+        __u32 v_sync_edge;
+        __u32 mclk_on_vgp0;
+        __u8 csi_port;
+        __u8 data_lanes;
+        __u8 virtual_channel_id;
+        __u8 discontinuous_clk_mode;
+        __u8 cil_threshold_settle;
+        __u8 align1;
+        __u8 align2;
+        __u8 align3;
+        __s32 min_blank_time_width;
+        __s32 min_blank_time_height;
+        __u32 preferred_mode_index;
+        __u64 focuser_guid;
+        __u64 torch_guid;
+        __u32 cap_end;
+        __u32 align4;
+} __packed;
+
+#define NVC_IOCTL_CAPS_RD       _IOWR('o', 106, struct nvc_imager_cap)
+#define NVC_IOCTL_MODE_WR       _IOW('o', 107, struct nvc_imager_bayer)
+#define NVC_IOCTL_MODE_RD       _IOWR('o', 108, struct nvc_imager_mode_list)
+#define NVC_IOCTL_STATIC_RD     _IOWR('o', 109, struct nvc_imager_static_nvc)
+#define NVC_IOCTL_DYNAMIC_RD    _IOWR('o', 110, struct nvc_imager_dnvc)
+
+#endif /* __NVC_IMAGE_H__ */
diff --git a/include/media/nvc_torch.h b/include/media/nvc_torch.h
new file mode 100644
index 00000000000..7c88bc75af0
--- /dev/null
+++ b/include/media/nvc_torch.h
@@ -0,0 +1,43 @@
+/* Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __NVC_TORCH_H__
+#define __NVC_TORCH_H__
+
+struct nvc_torch_level_info {
+        __s32 guidenum;
+        __u32 sustaintime;
+        __s32 rechargefactor;
+} __packed;
+
+struct nvc_torch_pin_state {
+        __u16 mask;
+        __u16 values;
+} __packed;
+
+struct nvc_torch_flash_capabilities {
+        __u32 numberoflevels;
+        struct nvc_torch_level_info levels[];
+} __packed;
+
+struct nvc_torch_torch_capabilities {
+        __u32 numberoflevels;
+        __s32 guidenum[];
+} __packed;
+
+#endif /* __NVC_TORCH_H__ */
+
diff --git a/include/media/ov14810.h b/include/media/ov14810.h
new file mode 100644
index 00000000000..67a86495918
--- /dev/null
+++ b/include/media/ov14810.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __OV14810_H__
+#define __OV14810_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define OV14810_IOCTL_SET_MODE                  _IOW('o', 1, struct ov14810_mode)
+#define OV14810_IOCTL_SET_FRAME_LENGTH  _IOW('o', 2, __u32)
+#define OV14810_IOCTL_SET_COARSE_TIME   _IOW('o', 3, __u32)
+#define OV14810_IOCTL_SET_GAIN                  _IOW('o', 4, __u16)
+#define OV14810_IOCTL_GET_STATUS                _IOR('o', 5, __u8)
+#define OV14810_IOCTL_SET_CAMERA_MODE   _IOW('o', 10, __u32)
+#define OV14810_IOCTL_SYNC_SENSORS              _IOW('o', 11, __u32)
+
+struct ov14810_mode {
+        int xres;
+        int yres;
+        __u32 frame_length;
+        __u32 coarse_time;
+        __u16 gain;
+};
+#ifdef __KERNEL__
+struct ov14810_platform_data {
+        int (*power_on)(void);
+        int (*power_off)(void);
+        void (*synchronize_sensors)(void);
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __OV14810_H__ */
diff --git a/include/media/ov2710.h b/include/media/ov2710.h
new file mode 100644
index 00000000000..e3d43056d70
--- /dev/null
+++ b/include/media/ov2710.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2010 Motorola, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __OV2710_H__
+#define __OV2710_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define OV2710_IOCTL_SET_MODE           _IOW('o', 1, struct ov2710_mode)
+#define OV2710_IOCTL_SET_FRAME_LENGTH   _IOW('o', 2, __u32)
+#define OV2710_IOCTL_SET_COARSE_TIME    _IOW('o', 3, __u32)
+#define OV2710_IOCTL_SET_GAIN           _IOW('o', 4, __u16)
+#define OV2710_IOCTL_GET_STATUS         _IOR('o', 5, __u8)
+
+struct ov2710_mode {
+        int xres;
+        int yres;
+        __u32 frame_length;
+        __u32 coarse_time;
+        __u16 gain;
+};
+#ifdef __KERNEL__
+struct ov2710_platform_data {
+        int (*power_on)(void);
+        int (*power_off)(void);
+
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __OV2710_H__ */
+
diff --git a/include/media/ov5650.h b/include/media/ov5650.h
new file mode 100644
index 00000000000..5c4a87cfbe8
--- /dev/null
+++ b/include/media/ov5650.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2010 Motorola, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __OV5650_H__
+#define __OV5650_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define OV5650_IOCTL_SET_MODE                   _IOW('o', 1, struct ov5650_mode)
+#define OV5650_IOCTL_SET_FRAME_LENGTH   _IOW('o', 2, __u32)
+#define OV5650_IOCTL_SET_COARSE_TIME    _IOW('o', 3, __u32)
+#define OV5650_IOCTL_SET_GAIN                   _IOW('o', 4, __u16)
+#define OV5650_IOCTL_GET_STATUS                 _IOR('o', 5, __u8)
+#define OV5650_IOCTL_SET_BINNING        _IOW('o', 6, __u8)
+#define OV5650_IOCTL_TEST_PATTERN               _IOW('o', 7, enum ov5650_test_pattern)
+#define OV5650_IOCTL_SET_GROUP_HOLD         _IOW('o', 8, struct ov5650_ae)
+#define OV5650_IOCTL_SET_CAMERA_MODE    _IOW('o', 10, __u32)
+#define OV5650_IOCTL_SYNC_SENSORS               _IOW('o', 11, __u32)
+
+/* OV5650 registers */
+#define OV5650_SRM_GRUP_ACCESS          (0x3212)
+#define OV5650_ARRAY_CONTROL_01         (0x3621)
+#define OV5650_ANALOG_CONTROL_D         (0x370D)
+#define OV5650_TIMING_TC_REG_18         (0x3818)
+#define OV5650_TIMING_CONTROL_HS_HIGH   (0x3800)
+#define OV5650_TIMING_CONTROL_HS_LOW    (0x3801)
+#define OV5650_TIMING_CONTROL_VS_HIGH   (0x3802)
+#define OV5650_TIMING_CONTROL_VS_LOW    (0x3803)
+#define OV5650_TIMING_HW_HIGH           (0x3804)
+#define OV5650_TIMING_HW_LOW            (0x3805)
+#define OV5650_TIMING_VH_HIGH           (0x3806)
+#define OV5650_TIMING_VH_LOW            (0x3807)
+#define OV5650_TIMING_TC_REG_18         (0x3818)
+#define OV5650_TIMING_HREFST_MAN_HIGH   (0x3824)
+#define OV5650_TIMING_HREFST_MAN_LOW    (0x3825)
+#define OV5650_H_BINNING_BIT            (1 << 7)
+#define OV5650_H_SUBSAMPLING_BIT        (1 << 6)
+#define OV5650_V_BINNING_BIT            (1 << 6)
+#define OV5650_V_SUBSAMPLING_BIT        (1 << 0)
+#define OV5650_GROUP_HOLD_BIT           (1 << 7)
+#define OV5650_GROUP_LAUNCH_BIT         (1 << 5)
+#define OV5650_GROUP_HOLD_END_BIT       (1 << 4)
+#define OV5650_GROUP_ID(id)             (id)
+
+enum ov5650_test_pattern {
+        TEST_PATTERN_NONE,
+        TEST_PATTERN_COLORBARS,
+        TEST_PATTERN_CHECKERBOARD
+};
+
+struct ov5650_mode {
+        int xres;
+        int yres;
+        __u32 frame_length;
+        __u32 coarse_time;
+        __u16 gain;
+};
+
+struct ov5650_ae {
+        __u32 frame_length;
+        __u8 frame_length_enable;
+        __u32 coarse_time;
+        __u8 coarse_time_enable;
+        __s32 gain;
+        __u8 gain_enable;
+};
+
+#ifdef __KERNEL__
+struct ov5650_platform_data {
+        int (*power_on)(void);
+        int (*power_off)(void);
+        void (*synchronize_sensors)(void);
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __OV5650_H__ */
+
diff --git a/include/media/ov9726.h b/include/media/ov9726.h
new file mode 100644
index 00000000000..b1e759ba583
--- /dev/null
+++ b/include/media/ov9726.h
@@ -0,0 +1,62 @@
+/*
+* ov9726.h
+*
+* Copyright (c) 2011, NVIDIA, All Rights Reserved.
+*
+* This file is licensed under the terms of the GNU General Public License
+* version 2. This program is licensed "as is" without any warranty of any
+* kind, whether express or implied.
+*/
+
+#ifndef __OV9726_H__
+#define __OV9726_H__
+
+#include <linux/ioctl.h>
+
+#define OV9726_I2C_ADDR                 0x20
+
+#define OV9726_IOCTL_SET_MODE           _IOW('o', 1, struct ov9726_mode)
+#define OV9726_IOCTL_SET_FRAME_LENGTH   _IOW('o', 2, __u32)
+#define OV9726_IOCTL_SET_COARSE_TIME    _IOW('o', 3, __u32)
+#define OV9726_IOCTL_SET_GAIN           _IOW('o', 4, __u16)
+#define OV9726_IOCTL_GET_STATUS         _IOR('o', 5, __u8)
+
+struct ov9726_mode {
+        int     mode_id;
+        int     xres;
+        int     yres;
+        __u32   frame_length;
+        __u32   coarse_time;
+        __u16   gain;
+};
+
+struct ov9726_reg {
+        __u16   addr;
+        __u16   val;
+};
+
+#ifdef __KERNEL__
+#define OV9726_REG_FRAME_LENGTH_HI      0x340
+#define OV9726_REG_FRAME_LENGTH_LO      0x341
+#define OV9726_REG_COARSE_TIME_HI       0x202
+#define OV9726_REG_COARSE_TIME_LO       0x203
+#define OV9726_REG_GAIN_HI              0x204
+#define OV9726_REG_GAIN_LO              0x205
+
+#define OV9726_MAX_RETRIES              3
+
+#define OV9726_TABLE_WAIT_MS            0
+#define OV9726_TABLE_END                1
+
+struct ov9726_platform_data {
+        int     (*power_on)(void);
+        int     (*power_off)(void);
+        unsigned    gpio_rst;
+        bool        rst_low_active;
+        unsigned    gpio_pwdn;
+        bool        pwdn_low_active;
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __OV9726_H__ */
+
diff --git a/include/media/pwc-ioctl.h b/include/media/pwc-ioctl.h
new file mode 100644
index 00000000000..0f19779c463
--- /dev/null
+++ b/include/media/pwc-ioctl.h
@@ -0,0 +1,324 @@
+#ifndef PWC_IOCTL_H
+#define PWC_IOCTL_H
+
+/* (C) 2001-2004 Nemosoft Unv.
+   (C) 2004-2006 Luc Saillard (luc@saillard.org)
+
+   NOTE: this version of pwc is an unofficial (modified) release of pwc & pcwx
+   driver and thus may have bugs that are not present in the original version.
+   Please send bug reports and support requests to <luc@saillard.org>.
+   The decompression routines have been implemented by reverse-engineering the
+   Nemosoft binary pwcx module. Caveat emptor.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+/* This is pwc-ioctl.h belonging to PWC 10.0.10
+   It contains structures and defines to communicate from user space
+   directly to the driver.
+ */
+
+/*
+   Changes
+   2001/08/03  Alvarado   Added ioctl constants to access methods for
+                          changing white balance and red/blue gains
+   2002/12/15  G. H. Fernandez-Toribio   VIDIOCGREALSIZE
+   2003/12/13  Nemosft Unv. Some modifications to make interfacing to
+               PWCX easier
+   2006/01/01  Luc Saillard Add raw format definition
+ */
+
+/* These are private ioctl() commands, specific for the Philips webcams.
+   They contain functions not found in other webcams, and settings not
+   specified in the Video4Linux API.
+
+   The #define names are built up like follows:
+   VIDIOC               VIDeo IOCtl prefix
+         PWC            Philps WebCam
+            G           optional: Get
+            S           optional: Set
+             ...        the function
+ */
+
+#include <linux/types.h>
+#include <linux/version.h>
+
+/* Enumeration of image sizes */
+#define PSZ_SQCIF       0x00
+#define PSZ_QSIF        0x01
+#define PSZ_QCIF        0x02
+#define PSZ_SIF         0x03
+#define PSZ_CIF         0x04
+#define PSZ_VGA         0x05
+#define PSZ_MAX         6
+
+
+/* The frame rate is encoded in the video_window.flags parameter using
+   the upper 16 bits, since some flags are defined nowadays. The following
+   defines provide a mask and shift to filter out this value.
+   This value can also be passing using the private flag when using v4l2 and
+   VIDIOC_S_FMT ioctl.
+
+   In 'Snapshot' mode the camera freezes its automatic exposure and colour
+   balance controls.
+ */
+#define PWC_FPS_SHIFT           16
+#define PWC_FPS_MASK            0x00FF0000
+#define PWC_FPS_FRMASK          0x003F0000
+#define PWC_FPS_SNAPSHOT        0x00400000
+#define PWC_QLT_MASK            0x03000000
+#define PWC_QLT_SHIFT           24
+
+
+/* structure for transferring x & y coordinates */
+struct pwc_coord
+{
+        int x, y;               /* guess what */
+        int size;               /* size, or offset */
+};
+
+
+/* Used with VIDIOCPWCPROBE */
+struct pwc_probe
+{
+        char name[32];
+        int type;
+};
+
+struct pwc_serial
+{
+        char serial[30];        /* String with serial number. Contains terminating 0 */
+};
+
+/* pwc_whitebalance.mode values */
+#define PWC_WB_INDOOR           0
+#define PWC_WB_OUTDOOR          1
+#define PWC_WB_FL               2
+#define PWC_WB_MANUAL           3
+#define PWC_WB_AUTO             4
+
+/* Used with VIDIOCPWC[SG]AWB (Auto White Balance).
+   Set mode to one of the PWC_WB_* values above.
+   *red and *blue are the respective gains of these colour components inside
+   the camera; range 0..65535
+   When 'mode' == PWC_WB_MANUAL, 'manual_red' and 'manual_blue' are set or read;
+   otherwise undefined.
+   'read_red' and 'read_blue' are read-only.
+*/
+struct pwc_whitebalance
+{
+        int mode;
+        int manual_red, manual_blue;    /* R/W */
+        int read_red, read_blue;        /* R/O */
+};
+
+/*
+   'control_speed' and 'control_delay' are used in automatic whitebalance mode,
+   and tell the camera how fast it should react to changes in lighting, and
+   with how much delay. Valid values are 0..65535.
+*/
+struct pwc_wb_speed
+{
+        int control_speed;
+        int control_delay;
+
+};
+
+/* Used with VIDIOCPWC[SG]LED */
+struct pwc_leds
+{
+        int led_on;                     /* Led on-time; range = 0..25000 */
+        int led_off;                    /* Led off-time; range = 0..25000  */
+};
+
+/* Image size (used with GREALSIZE) */
+struct pwc_imagesize
+{
+        int width;
+        int height;
+};
+
+/* Defines and structures for Motorized Pan & Tilt */
+#define PWC_MPT_PAN             0x01
+#define PWC_MPT_TILT            0x02
+#define PWC_MPT_TIMEOUT         0x04 /* for status */
+
+/* Set angles; when absolute != 0, the angle is absolute and the
+   driver calculates the relative offset for you. This can only
+   be used with VIDIOCPWCSANGLE; VIDIOCPWCGANGLE always returns
+   absolute angles.
+ */
+struct pwc_mpt_angles
+{
+        int absolute;           /* write-only */
+        int pan;                /* degrees * 100 */
+        int tilt;               /* degress * 100 */
+};
+
+/* Range of angles of the camera, both horizontally and vertically.
+ */
+struct pwc_mpt_range
+{
+        int pan_min, pan_max;           /* degrees * 100 */
+        int tilt_min, tilt_max;
+};
+
+struct pwc_mpt_status
+{
+        int status;
+        int time_pan;
+        int time_tilt;
+};
+
+
+/* This is used for out-of-kernel decompression. With it, you can get
+   all the necessary information to initialize and use the decompressor
+   routines in standalone applications.
+ */
+struct pwc_video_command
+{
+        int type;               /* camera type (645, 675, 730, etc.) */
+        int release;            /* release number */
+
+        int size;               /* one of PSZ_* */
+        int alternate;
+        int command_len;        /* length of USB video command */
+        unsigned char command_buf[13];  /* Actual USB video command */
+        int bandlength;         /* >0 = compressed */
+        int frame_size;         /* Size of one (un)compressed frame */
+};
+
+/* Flags for PWCX subroutines. Not all modules honour all flags. */
+#define PWCX_FLAG_PLANAR        0x0001
+#define PWCX_FLAG_BAYER         0x0008
+
+
+/* IOCTL definitions */
+
+ /* Restore user settings */
+#define VIDIOCPWCRUSER          _IO('v', 192)
+ /* Save user settings */
+#define VIDIOCPWCSUSER          _IO('v', 193)
+ /* Restore factory settings */
+#define VIDIOCPWCFACTORY        _IO('v', 194)
+
+ /* You can manipulate the compression factor. A compression preference of 0
+    means use uncompressed modes when available; 1 is low compression, 2 is
+    medium and 3 is high compression preferred. Of course, the higher the
+    compression, the lower the bandwidth used but more chance of artefacts
+    in the image. The driver automatically chooses a higher compression when
+    the preferred mode is not available.
+  */
+ /* Set preferred compression quality (0 = uncompressed, 3 = highest compression) */
+#define VIDIOCPWCSCQUAL         _IOW('v', 195, int)
+ /* Get preferred compression quality */
+#define VIDIOCPWCGCQUAL         _IOR('v', 195, int)
+
+
+/* Retrieve serial number of camera */
+#define VIDIOCPWCGSERIAL        _IOR('v', 198, struct pwc_serial)
+
+ /* This is a probe function; since so many devices are supported, it
+    becomes difficult to include all the names in programs that want to
+    check for the enhanced Philips stuff. So in stead, try this PROBE;
+    it returns a structure with the original name, and the corresponding
+    Philips type.
+    To use, fill the structure with zeroes, call PROBE and if that succeeds,
+    compare the name with that returned from VIDIOCGCAP; they should be the
+    same. If so, you can be assured it is a Philips (OEM) cam and the type
+    is valid.
+ */
+#define VIDIOCPWCPROBE          _IOR('v', 199, struct pwc_probe)
+
+ /* Set AGC (Automatic Gain Control); int < 0 = auto, 0..65535 = fixed */
+#define VIDIOCPWCSAGC           _IOW('v', 200, int)
+ /* Get AGC; int < 0 = auto; >= 0 = fixed, range 0..65535 */
+#define VIDIOCPWCGAGC           _IOR('v', 200, int)
+ /* Set shutter speed; int < 0 = auto; >= 0 = fixed, range 0..65535 */
+#define VIDIOCPWCSSHUTTER       _IOW('v', 201, int)
+
+ /* Color compensation (Auto White Balance) */
+#define VIDIOCPWCSAWB           _IOW('v', 202, struct pwc_whitebalance)
+#define VIDIOCPWCGAWB           _IOR('v', 202, struct pwc_whitebalance)
+
+ /* Auto WB speed */
+#define VIDIOCPWCSAWBSPEED      _IOW('v', 203, struct pwc_wb_speed)
+#define VIDIOCPWCGAWBSPEED      _IOR('v', 203, struct pwc_wb_speed)
+
+ /* LEDs on/off/blink; int range 0..65535 */
+#define VIDIOCPWCSLED           _IOW('v', 205, struct pwc_leds)
+#define VIDIOCPWCGLED           _IOR('v', 205, struct pwc_leds)
+
+  /* Contour (sharpness); int < 0 = auto, 0..65536 = fixed */
+#define VIDIOCPWCSCONTOUR       _IOW('v', 206, int)
+#define VIDIOCPWCGCONTOUR       _IOR('v', 206, int)
+
+  /* Backlight compensation; 0 = off, otherwise on */
+#define VIDIOCPWCSBACKLIGHT     _IOW('v', 207, int)
+#define VIDIOCPWCGBACKLIGHT     _IOR('v', 207, int)
+
+  /* Flickerless mode; = 0 off, otherwise on */
+#define VIDIOCPWCSFLICKER       _IOW('v', 208, int)
+#define VIDIOCPWCGFLICKER       _IOR('v', 208, int)
+
+  /* Dynamic noise reduction; 0 off, 3 = high noise reduction */
+#define VIDIOCPWCSDYNNOISE      _IOW('v', 209, int)
+#define VIDIOCPWCGDYNNOISE      _IOR('v', 209, int)
+
+ /* Real image size as used by the camera; tells you whether or not there's a gray border around the image */
+#define VIDIOCPWCGREALSIZE      _IOR('v', 210, struct pwc_imagesize)
+
+ /* Motorized pan & tilt functions */
+#define VIDIOCPWCMPTRESET       _IOW('v', 211, int)
+#define VIDIOCPWCMPTGRANGE      _IOR('v', 211, struct pwc_mpt_range)
+#define VIDIOCPWCMPTSANGLE      _IOW('v', 212, struct pwc_mpt_angles)
+#define VIDIOCPWCMPTGANGLE      _IOR('v', 212, struct pwc_mpt_angles)
+#define VIDIOCPWCMPTSTATUS      _IOR('v', 213, struct pwc_mpt_status)
+
+ /* Get the USB set-video command; needed for initializing libpwcx */
+#define VIDIOCPWCGVIDCMD        _IOR('v', 215, struct pwc_video_command)
+struct pwc_table_init_buffer {
+   int len;
+   char *buffer;
+
+};
+#define VIDIOCPWCGVIDTABLE      _IOR('v', 216, struct pwc_table_init_buffer)
+
+/*
+ * This is private command used when communicating with v4l2.
+ * In the future all private ioctl will be remove/replace to
+ * use interface offer by v4l2.
+ */
+
+#define V4L2_CID_PRIVATE_SAVE_USER       (V4L2_CID_PRIVATE_BASE + 0)
+#define V4L2_CID_PRIVATE_RESTORE_USER    (V4L2_CID_PRIVATE_BASE + 1)
+#define V4L2_CID_PRIVATE_RESTORE_FACTORY (V4L2_CID_PRIVATE_BASE + 2)
+#define V4L2_CID_PRIVATE_COLOUR_MODE     (V4L2_CID_PRIVATE_BASE + 3)
+#define V4L2_CID_PRIVATE_AUTOCONTOUR     (V4L2_CID_PRIVATE_BASE + 4)
+#define V4L2_CID_PRIVATE_CONTOUR         (V4L2_CID_PRIVATE_BASE + 5)
+#define V4L2_CID_PRIVATE_BACKLIGHT       (V4L2_CID_PRIVATE_BASE + 6)
+#define V4L2_CID_PRIVATE_FLICKERLESS     (V4L2_CID_PRIVATE_BASE + 7)
+#define V4L2_CID_PRIVATE_NOISE_REDUCTION (V4L2_CID_PRIVATE_BASE + 8)
+
+struct pwc_raw_frame {
+   __le16 type;         /* type of the webcam */
+   __le16 vbandlength;  /* Size of 4lines compressed (used by the decompressor) */
+   __u8   cmd[4];       /* the four byte of the command (in case of nala,
+                           only the first 3 bytes is filled) */
+   __u8   rawframe[0];  /* frame_size = H/4*vbandlength */
+} __attribute__ ((packed));
+
+
+#endif
diff --git a/include/media/sh532u.h b/include/media/sh532u.h
new file mode 100644
index 00000000000..19da2070b70
--- /dev/null
+++ b/include/media/sh532u.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __SH532U_H__
+#define __SH532U_H__
+
+#include <media/nvc_focus.h>
+
+
+struct sh532u_platform_data {
+        int cfg;
+        int num;
+        int sync;
+        const char *dev_name;
+        struct nvc_focus_nvc (*nvc);
+        struct nvc_focus_cap (*cap);
+        struct sh532u_pdata_info (*info);
+        __u8 i2c_addr_rom;
+        unsigned gpio_reset;
+/* Due to a Linux limitation, a GPIO is defined to "enable" the device.  This
+ * workaround is for when the device's power GPIO's are behind an I2C expander.
+ * The Linux limitation doesn't allow the I2C GPIO expander to be ready for
+ * use when this device is probed.
+ */
+        unsigned gpio_en;
+};
+
+struct sh532u_pdata_info {
+        __s16 pos_low;
+        __s16 pos_high;
+        __s16 limit_low;
+        __s16 limit_high;
+        int move_timeoutms;
+        __u32 focus_hyper_ratio;
+        __u32 focus_hyper_div;
+};
+
+
+/* Register Definition  : Sany Driver IC */
+/* EEPROM addresses */
+#define addrHallOffset          0x10
+#define addrHallBias            0x11
+#define addrInf1                0x12
+#define addrMac1                0x13
+#define addrLoopGainH           0x14
+#define addrLoopGainL           0x15
+#define addrInf2                0x16
+#define addrMac2                0x17
+
+#define addrInf1_H              0x20 /* bottom mechanical limit of HVCA */
+#define addrInf1_L              0x21
+#define addrMac1_H              0x22 /* top mechanical limit of HVCA */
+#define addrMac1_L              0x23
+#define addrInf2_H              0x24 /* lens position when object is ?120cm */
+#define addrInf2_L              0x25
+#define addrMac2_H              0x26 /* lens position when object is ?10cm */
+#define addrMac2_L              0x27
+#define addrDacDeltaUp_H        0x28 /* difference between face up and down */
+#define addrDacDeltaUp_L        0x29
+#define addrAFoffset_H          0x2A /* best focus position subtract value */
+#define addrAFoffset_L          0x2B
+
+/* Convergence Judgement */
+#define INI_MSSET_211           0x00
+#define CHTGOKN_TIME            0x80
+#define CHTGOKN_WAIT            1
+#define CHTGOKN_TIMEOUT         50
+#define CHTGSTOKN_TOMEOUT       15
+
+/* StepMove */
+#define STMV_SIZE               0x0180
+
+#define STMCHTG_ON              0x08
+#define STMSV_ON                0x04
+#define STMLFF_ON               0x02
+#define STMVEN_ON               0x01
+#define STMCHTG_OFF             0x00
+#define STMSV_OFF               0x00
+#define STMLFF_OFF              0x00
+#define STMVEN_OFF              0x00
+
+#define STMCHTG_SET             STMCHTG_ON
+#define STMSV_SET               STMSV_ON
+#define STMLFF_SET              STMLFF_OFF
+
+#define CHTGST_ON               0x01
+#define DEFAULT_DADAT           0x8040
+
+/* Delay RAM 00h ~ 3Fh */
+#define ADHXI_211H              0x00
+#define ADHXI_211L              0x01
+#define PIDZO_211H              0x02
+#define PIDZO_211L              0x03
+#define RZ_211H                 0x04
+#define RZ_211L                 0x05
+#define DZ1_211H                0x06
+#define DZ1_211L                0x07
+#define DZ2_211H                0x08
+#define DZ2_211L                0x09
+#define UZ1_211H                0x0A
+#define UZ1_211L                0x0B
+#define UZ2_211H                0x0C
+#define UZ2_211L                0x0D
+#define IZ1_211H                0x0E
+#define IZ1_211L                0x0F
+#define IZ2_211H                0x10
+#define IZ2_211L                0x11
+#define MS1Z01_211H             0x12
+#define MS1Z01_211L             0x13
+#define MS1Z11_211H             0x14
+#define MS1Z11_211L             0x15
+#define MS1Z12_211H             0x16
+#define MS1Z12_211L             0x17
+#define MS1Z22_211H             0x18
+#define MS1Z22_211L             0x19
+#define MS2Z01_211H             0x1A
+#define MS2Z01_211L             0x1B
+#define MS2Z11_211H             0x1C
+#define MS2Z11_211L             0x1D
+#define MS2Z12_211H             0x1E
+#define MS2Z12_211L             0x1F
+#define MS2Z22_211H             0x20
+#define MS2Z22_211L             0x21
+#define MS2Z23_211H             0x22
+#define MS2Z23_211L             0x23
+#define OZ1_211H                0x24
+#define OZ1_211L                0x25
+#define OZ2_211H                0x26
+#define OZ2_211L                0x27
+#define DAHLXO_211H             0x28
+#define DAHLXO_211L             0x29
+#define OZ3_211H                0x2A
+#define OZ3_211L                0x2B
+#define OZ4_211H                0x2C
+#define OZ4_211L                0x2D
+#define OZ5_211H                0x2E
+#define OZ5_211L                0x2F
+#define oe_211H                 0x30
+#define oe_211L                 0x31
+#define MSR1CMAX_211H           0x32
+#define MSR1CMAX_211L           0x33
+#define MSR1CMIN_211H           0x34
+#define MSR1CMIN_211L           0x35
+#define MSR2CMAX_211H           0x36
+#define MSR2CMAX_211L           0x37
+#define MSR2CMIN_211H           0x38
+#define MSR2CMIN_211L           0x39
+#define OFFSET_211H             0x3A
+#define OFFSET_211L             0x3B
+#define ADOFFSET_211H           0x3C
+#define ADOFFSET_211L           0x3D
+#define EZ_211H                 0x3E
+#define EZ_211L                 0x3F
+
+/* Coefficient RAM 40h ~ 7Fh */
+#define ag_211H                 0x40
+#define ag_211L                 0x41
+#define da_211H                 0x42
+#define da_211L                 0x43
+#define db_211H                 0x44
+#define db_211L                 0x45
+#define dc_211H                 0x46
+#define dc_211L                 0x47
+#define dg_211H                 0x48
+#define dg_211L                 0x49
+#define pg_211H                 0x4A
+#define pg_211L                 0x4B
+#define gain1_211H              0x4C
+#define gain1_211L              0x4D
+#define gain2_211H              0x4E
+#define gain2_211L              0x4F
+#define ua_211H                 0x50
+#define ua_211L                 0x51
+#define uc_211H                 0x52
+#define uc_211L                 0x53
+#define ia_211H                 0x54
+#define ia_211L                 0x55
+#define ib_211H                 0x56
+#define ib_211L                 0x57
+#define i_c_211H                0x58
+#define i_c_211L                0x59
+#define ms11a_211H              0x5A
+#define ms11a_211L              0x5B
+#define ms11c_211H              0x5C
+#define ms11c_211L              0x5D
+#define ms12a_211H              0x5E
+#define ms12a_211L              0x5F
+#define ms12c_211H              0x60
+#define ms12c_211L              0x61
+#define ms21a_211H              0x62
+#define ms21a_211L              0x63
+#define ms21b_211H              0x64
+#define ms21b_211L              0x65
+#define ms21c_211H              0x66
+#define ms21c_211L              0x67
+#define ms22a_211H              0x68
+#define ms22a_211L              0x69
+#define ms22c_211H              0x6A
+#define ms22c_211L              0x6B
+#define ms22d_211H              0x6C
+#define ms22d_211L              0x6D
+#define ms22e_211H              0x6E
+#define ms22e_211L              0x6F
+#define ms23p_211H              0x70
+#define ms23p_211L              0x71
+#define oa_211H                 0x72
+#define oa_211L                 0x73
+#define oc_211H                 0x74
+#define oc_211L                 0x75
+#define PX12_211H               0x76
+#define PX12_211L               0x77
+#define PX3_211H                0x78
+#define PX3_211L                0x79
+#define MS2X_211H               0x7A
+#define MS2X_211L               0x7B
+#define CHTGX_211H              0x7C
+#define CHTGX_211L              0x7D
+#define CHTGN_211H              0x7E
+#define CHTGN_211L              0x7F
+
+/* Register 80h ~  9F */
+#define CLKSEL_211              0x80
+#define ADSET_211               0x81
+#define PWMSEL_211              0x82
+#define SWTCH_211               0x83
+#define STBY_211                0x84
+#define CLR_211                 0x85
+#define DSSEL_211               0x86
+#define ENBL_211                0x87
+#define ANA1_211                0x88
+#define STMVEN_211              0x8A
+#define STPT_211                0x8B
+#define SWFC_211                0x8C
+#define SWEN_211                0x8D
+#define MSNUM_211               0x8E
+#define MSSET_211               0x8F
+#define DLYMON_211              0x90
+#define MONA_211                0x91
+#define PWMLIMIT_211            0x92
+#define PINSEL_211              0x93
+#define PWMSEL2_211             0x94
+#define SFTRST_211              0x95
+#define TEST_211                0x96
+#define PWMZONE2_211            0x97
+#define PWMZONE1_211            0x98
+#define PWMZONE0_211            0x99
+#define ZONE3_211               0x9A
+#define ZONE2_211               0x9B
+#define ZONE1_211               0x9C
+#define ZONE0_211               0x9D
+#define GCTIM_211               0x9E
+#define GCTIM_211NU             0x9F
+#define STMINT_211              0xA0
+#define STMVENDH_211            0xA1
+#define STMVENDL_211            0xA2
+#define MSNUMR_211              0xA3
+#define  ANA2_211               0xA4
+
+/* Device ID of HVCA Drive IC */
+#define HVCA_DEVICE_ID          0xE4
+
+/* Device ID of E2P ROM */
+#define EEP_DEVICE_ID           0xA0
+#define EEP_PAGE0               0x00
+#define EEP_PAGE1               0x02
+#define EEP_PAGE2               0x04
+#define EEP_PAGE3               0x06
+/* E2P ROM has 1023 bytes. So there are 4 pages memory */
+/* E2PROM Device ID = 1 0 1 0  0 P0 P1 0 */
+/*
+P0  P1
+0   0   : Page 0
+0   1   : Page 1
+1   0   : Page 2
+1   1   : Page 3
+*/
+/* Page 0: address 0x000~0x0FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE0 */
+/* Page 1: address 0x100~0x1FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE1 */
+/* Page 2: address 0x200~0x2FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE2 */
+/* Page 3: address 0x300~0x3FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE3 */
+/*
+*/
+
+/* E2P data type define of HVCA Initial Value Section */
+#define DIRECT_MODE             0x00
+#define INDIRECT_EEPROM         0x10
+#define INDIRECT_HVCA           0x20
+#define MASK_AND                0x70
+#define MASK_OR                 0x80
+
+#define DATA_1BYTE              0x01
+#define DATA_2BYTE              0x02
+
+#define START_ADDR              0x0030
+#define END_ADDR                0x01BF
+
+/*Macro define*/
+#if !defined(abs)
+#define abs(a)          (((a) > 0) ? (a) : -(a))
+#endif
+
+#endif
+/* __SH532U_H__ */
+
diff --git a/include/media/soc380.h b/include/media/soc380.h
new file mode 100644
index 00000000000..254625f74f8
--- /dev/null
+++ b/include/media/soc380.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION, All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of NVIDIA CORPORATION nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC380_H__
+#define __SOC380_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define SOC380_IOCTL_SET_MODE           _IOW('o', 1, struct soc380_mode)
+#define SOC380_IOCTL_GET_STATUS         _IOR('o', 2, struct soc380_status)
+
+struct soc380_mode {
+        int xres;
+        int yres;
+};
+
+struct soc380_status {
+        int data;
+        int status;
+};
+
+#ifdef __KERNEL__
+struct soc380_platform_data {
+        int (*power_on)(void);
+        int (*power_off)(void);
+
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __SOC380_H__ */
+
diff --git a/include/media/ssl3250a.h b/include/media/ssl3250a.h
new file mode 100644
index 00000000000..c4e802fa2ef
--- /dev/null
+++ b/include/media/ssl3250a.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __SSL3250A_H__
+#define __SSL3250A_H__
+
+#include <media/nvc_torch.h>
+
+#define SSL3250A_MAX_TORCH_LEVEL        11
+#define SSL3250A_MAX_FLASH_LEVEL        20
+
+struct ssl3250a_platform_data {
+        unsigned cfg; /* use the NVC_CFG_ defines */
+        unsigned num; /* see implementation notes in driver */
+        unsigned sync; /* see implementation notes in driver */
+        const char *dev_name; /* see implementation notes in driver */
+        struct nvc_torch_pin_state (*pinstate); /* see notes in driver */
+        unsigned max_amp_torch; /* maximum torch value allowed */
+        unsigned max_amp_flash; /* maximum flash value allowed */
+        unsigned gpio_act; /* GPIO connected to the ACT signal */
+};
+
+#endif /* __SSL3250A_H__ */
+
diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h
new file mode 100644
index 00000000000..d7d08bd9a99
--- /dev/null
+++ b/include/media/tegra_camera.h
@@ -0,0 +1,55 @@
+/*
+ * include/linux/tegra_camera.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef TEGRA_CAMERA_H
+#define TEGRA_CAMERA_H
+
+/* this is to enable VI pattern generator (Null Sensor) */
+#define TEGRA_CAMERA_ENABLE_PD2VI_CLK 0x1
+
+enum {
+        TEGRA_CAMERA_MODULE_ISP = 0,
+        TEGRA_CAMERA_MODULE_VI,
+        TEGRA_CAMERA_MODULE_CSI,
+};
+
+enum {
+        TEGRA_CAMERA_VI_CLK,
+        TEGRA_CAMERA_VI_SENSOR_CLK,
+};
+
+struct tegra_camera_clk_info {
+        uint id;
+        uint clk_id;
+        unsigned long rate;
+        uint flag;      /* to inform if any special bits need to enabled/disabled */
+};
+
+enum StereoCameraMode {
+        Main = 0x0,             /* Sets the default camera to Main */
+        StereoCameraMode_Left = 0x01,   /* the left camera is on. */
+        StereoCameraMode_Right = 0x02,  /* the right camera is on. */
+        StereoCameraMode_Stereo = 0x03, /* both cameras are on. */
+        StereoCameraMode_Force32 = 0x7FFFFFFF
+};
+
+
+#define TEGRA_CAMERA_IOCTL_ENABLE               _IOWR('i', 1, uint)
+#define TEGRA_CAMERA_IOCTL_DISABLE              _IOWR('i', 2, uint)
+#define TEGRA_CAMERA_IOCTL_CLK_SET_RATE         \
+        _IOWR('i', 3, struct tegra_camera_clk_info)
+#define TEGRA_CAMERA_IOCTL_RESET                _IOWR('i', 4, uint)
+
+#endif
diff --git a/include/media/tegra_dtv.h b/include/media/tegra_dtv.h
new file mode 100644
index 00000000000..798e3e3bf9c
--- /dev/null
+++ b/include/media/tegra_dtv.h
@@ -0,0 +1,134 @@
+/*
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __TEGRA_DTV_H__
+#define __TEGRA_DTV_H__
+
+#include <linux/ioctl.h>
+
+#define TEGRA_DTV_MAGIC 'v'
+
+#define TEGRA_DTV_IOCTL_START           _IO(TEGRA_DTV_MAGIC, 0)
+#define TEGRA_DTV_IOCTL_STOP            _IO(TEGRA_DTV_MAGIC, 1)
+
+struct tegra_dtv_hw_config {
+        int clk_edge; /*< clock edge to be used to sample DTV input signals */
+        int byte_swz_enabled; /*< byte order during deserialization */
+        int bit_swz_enabled;  /*< bit order during deserialization */
+
+        int protocol_sel;   /*< VD pin configuration. */
+        int clk_mode;       /*< input clock characteristics */
+        int fec_size;       /*< FEC size */
+        int body_size;      /*< BODY size */
+        int body_valid_sel; /*< VALID signal gate */
+        int start_sel;      /*< START of the package */
+        int err_pol;        /*< ERROR pin polarity */
+        int psync_pol;      /*< PSYNC pin polarity */
+        int valid_pol;      /*< VALID pin polarity */
+};
+
+#define TEGRA_DTV_IOCTL_SET_HW_CONFIG  _IOW(TEGRA_DTV_MAGIC, 2,         \
+                                           const struct tegra_dtv_hw_config *)
+#define TEGRA_DTV_IOCTL_GET_HW_CONFIG  _IOR(TEGRA_DTV_MAGIC, 3,         \
+                                           struct tegra_dtv_hw_config *)
+
+/**
+ * clock edge settings for clk_edge
+ *
+ * RISE_EDGE: sample input signal at rising edge
+ * FALL_EDGE: sample input signal at falling edge
+ */
+enum {
+        TEGRA_DTV_CLK_RISE_EDGE = 0,
+        TEGRA_DTV_CLK_FALL_EDGE,
+};
+
+/**
+ * swizzle settings for byte_swz and bit_swz
+ *
+ * ENABLE: enable swizzle during deserialization
+ * DISABLE: disable swizzle during deserialization
+ *
+ * If swizzling is enabled then deserialized data will be re-ordered to
+ * fit the required format for tegra.
+ *
+ * For example, if raw BGR data is inputed into DTV interface, the data
+ * could be swizzled into RGB.
+ *
+ * For TS/MPEG-2 stream, please disable this feature.
+ */
+enum {
+        TEGRA_DTV_SWZ_DISABLE = 0,
+        TEGRA_DTV_SWZ_ENABLE,
+};
+
+/* for selecting the pin configuration for VD(valid).
+ * NONE : ERROR is tied to 0, PSYNC is tied to 0
+ * ERROR: ERROR is tied to VD, PSYNC is tied to 0
+ * PSYNC: ERROR is tied to 0, PSYNC is tied to VD
+ */
+enum {
+        TEGRA_DTV_PROTOCOL_NONE = 0,
+        TEGRA_DTV_PROTOCOL_ERROR,
+        TEGRA_DTV_PROTOCOL_PSYNC,
+};
+
+enum {
+        TEGRA_DTV_CLK_DISCONTINUOUS = 0,
+        TEGRA_DTV_CLK_CONTINUOUS,
+};
+
+enum {
+        TEGRA_DTV_BODY_VALID_IGNORE = 0,
+        TEGRA_DTV_BODY_VALID_GATE,
+};
+
+enum {
+        TEGRA_DTV_START_RESERVED = 0, /* never use this */
+        TEGRA_DTV_START_PSYNC,
+        TEGRA_DTV_START_VALID,
+        TEGRA_DTV_START_BOTH,
+};
+
+enum {
+        TEGRA_DTV_ERROR_POLARITY_HIGH = 0,
+        TEGRA_DTV_ERROR_POLARITY_LOW,
+};
+
+enum {
+        TEGRA_DTV_PSYNC_POLARITY_HIGH = 0,
+        TEGRA_DTV_PSYNC_POLARITY_LOW,
+};
+
+enum {
+        TEGRA_DTV_VALID_POLARITY_HIGH = 0,
+        TEGRA_DTV_VALID_POLARITY_LOW,
+};
+
+#ifdef __KERNEL__
+enum {
+        TEGRA_DTV_CLK_POSEDGE,
+        TEGRA_DTV_CLK_NEGEDGE,
+};
+
+struct tegra_dtv_platform_data {
+        unsigned int dma_buf_size;
+        int clk_edge;
+        bool byte_swz_enabled;
+        bool bit_swz_enabled;
+};
+#endif /* __KERNEL__ */
+
+#endif /* __TEGRA_DTV_H__ */
diff --git a/include/media/tps61050.h b/include/media/tps61050.h
new file mode 100644
index 00000000000..1c289eb3616
--- /dev/null
+++ b/include/media/tps61050.h
@@ -0,0 +1,36 @@
+/* Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#ifndef __TPS61050_H__
+#define __TPS61050_H__
+
+#include <media/nvc_torch.h>
+
+#define TPS61050_MAX_TORCH_LEVEL        7
+#define TPS61050_MAX_FLASH_LEVEL        8
+
+struct tps61050_platform_data {
+        unsigned cfg; /* use the  NVC_CFG_ defines */
+        unsigned num; /* see implementation notes in driver */
+        unsigned sync; /* see implementation notes in driver */
+        const char *dev_name; /* see implementation notes in driver */
+        struct nvc_torch_pin_state (*pinstate); /* see notes in driver */
+        unsigned max_amp_torch; /* see implementation notes in driver */
+        unsigned max_amp_flash; /* see implementation notes in driver */
+};
+
+#endif /* __TPS61050_H__ */