diff options
author | Jesper Nilsson <jespern@stork.se.axis.com> | 2007-11-29 11:21:59 -0500 |
---|---|---|
committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-02-08 05:06:23 -0500 |
commit | 58d083192825c5fbd46fa0b1ff4d1ecc9118b692 (patch) | |
tree | 3bd39bf385afe376272d4769c0af321d6e8ed992 /include/asm-cris/arch-v32/mach-a3/hwregs/iop | |
parent | 035e111f9a9b29843bc899f03d56f19d94bebb53 (diff) |
CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips.
The header files describe the hardware registers available in both
these chips, note that most of this documentation is automatically
generated from the hardware implementation.
Diffstat (limited to 'include/asm-cris/arch-v32/mach-a3/hwregs/iop')
16 files changed, 6610 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 00000000000..d75a74e9045 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* Autogenerated Changes here will be lost! | ||
2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
3 | */ | ||
4 | #define iop_version 0 | ||
5 | #define iop_fifo_in_extra 64 | ||
6 | #define iop_fifo_out_extra 128 | ||
7 | #define iop_trigger_grp0 192 | ||
8 | #define iop_trigger_grp1 256 | ||
9 | #define iop_trigger_grp2 320 | ||
10 | #define iop_trigger_grp3 384 | ||
11 | #define iop_trigger_grp4 448 | ||
12 | #define iop_trigger_grp5 512 | ||
13 | #define iop_trigger_grp6 576 | ||
14 | #define iop_trigger_grp7 640 | ||
15 | #define iop_crc_par 768 | ||
16 | #define iop_dmc_in 896 | ||
17 | #define iop_dmc_out 1024 | ||
18 | #define iop_fifo_in 1152 | ||
19 | #define iop_fifo_out 1280 | ||
20 | #define iop_scrc_in 1408 | ||
21 | #define iop_scrc_out 1536 | ||
22 | #define iop_timer_grp0 1664 | ||
23 | #define iop_timer_grp1 1792 | ||
24 | #define iop_sap_in 2048 | ||
25 | #define iop_sap_out 2304 | ||
26 | #define iop_spu 2560 | ||
27 | #define iop_sw_cfg 2816 | ||
28 | #define iop_sw_cpu 3072 | ||
29 | #define iop_sw_mpu 3328 | ||
30 | #define iop_sw_spu 3584 | ||
31 | #define iop_mpu 4096 | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 00000000000..7f90b5a0460 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h | |||
@@ -0,0 +1,109 @@ | |||
1 | #ifndef __iop_sap_in_defs_asm_h | ||
2 | #define __iop_sap_in_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sap_in.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
54 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
55 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 | ||
56 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 | ||
57 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 | ||
58 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 | ||
59 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 | ||
60 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 | ||
61 | #define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 | ||
62 | #define reg_iop_sap_in_rw_bus_byte___delay___width 2 | ||
63 | #define reg_iop_sap_in_rw_bus_byte_offset 0 | ||
64 | |||
65 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
66 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
67 | #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 | ||
68 | #define reg_iop_sap_in_rw_gio___sync_sel___width 2 | ||
69 | #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 | ||
70 | #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 | ||
71 | #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 | ||
72 | #define reg_iop_sap_in_rw_gio___sync_edge___width 2 | ||
73 | #define reg_iop_sap_in_rw_gio___delay___lsb 7 | ||
74 | #define reg_iop_sap_in_rw_gio___delay___width 2 | ||
75 | #define reg_iop_sap_in_rw_gio___logic___lsb 9 | ||
76 | #define reg_iop_sap_in_rw_gio___logic___width 2 | ||
77 | #define reg_iop_sap_in_rw_gio_offset 16 | ||
78 | |||
79 | |||
80 | /* Constants */ | ||
81 | #define regk_iop_sap_in_and 0x00000002 | ||
82 | #define regk_iop_sap_in_ext_clk200 0x00000003 | ||
83 | #define regk_iop_sap_in_gio0 0x00000000 | ||
84 | #define regk_iop_sap_in_gio12 0x00000003 | ||
85 | #define regk_iop_sap_in_gio16 0x00000004 | ||
86 | #define regk_iop_sap_in_gio20 0x00000005 | ||
87 | #define regk_iop_sap_in_gio24 0x00000006 | ||
88 | #define regk_iop_sap_in_gio28 0x00000007 | ||
89 | #define regk_iop_sap_in_gio4 0x00000001 | ||
90 | #define regk_iop_sap_in_gio8 0x00000002 | ||
91 | #define regk_iop_sap_in_inv 0x00000001 | ||
92 | #define regk_iop_sap_in_neg 0x00000002 | ||
93 | #define regk_iop_sap_in_no 0x00000000 | ||
94 | #define regk_iop_sap_in_no_del_ext_clk200 0x00000002 | ||
95 | #define regk_iop_sap_in_none 0x00000000 | ||
96 | #define regk_iop_sap_in_one 0x00000001 | ||
97 | #define regk_iop_sap_in_or 0x00000003 | ||
98 | #define regk_iop_sap_in_pos 0x00000001 | ||
99 | #define regk_iop_sap_in_pos_neg 0x00000003 | ||
100 | #define regk_iop_sap_in_rw_bus_byte_default 0x00000000 | ||
101 | #define regk_iop_sap_in_rw_bus_byte_size 0x00000004 | ||
102 | #define regk_iop_sap_in_rw_gio_default 0x00000000 | ||
103 | #define regk_iop_sap_in_rw_gio_size 0x00000020 | ||
104 | #define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 | ||
105 | #define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 | ||
106 | #define regk_iop_sap_in_tmr_clk200 0x00000001 | ||
107 | #define regk_iop_sap_in_two 0x00000002 | ||
108 | #define regk_iop_sap_in_two_clk200 0x00000000 | ||
109 | #endif /* __iop_sap_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 00000000000..399bd656406 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h | |||
@@ -0,0 +1,276 @@ | |||
1 | #ifndef __iop_sap_out_defs_asm_h | ||
2 | #define __iop_sap_out_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sap_out.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
54 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 | ||
55 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 | ||
56 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 | ||
57 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 | ||
58 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 | ||
59 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 | ||
60 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 | ||
61 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 | ||
62 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 | ||
63 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 | ||
64 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 | ||
65 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 | ||
66 | #define reg_iop_sap_out_rw_gen_gated_offset 0 | ||
67 | |||
68 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
69 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 | ||
70 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 | ||
71 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 | ||
72 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 | ||
73 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 | ||
74 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 | ||
75 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 | ||
76 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 | ||
77 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 | ||
78 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 | ||
79 | #define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 | ||
80 | #define reg_iop_sap_out_rw_bus___byte0_delay___width 1 | ||
81 | #define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 | ||
82 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 | ||
83 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 | ||
84 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 | ||
85 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 | ||
86 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 | ||
87 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 | ||
88 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 | ||
89 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 | ||
90 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 | ||
91 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 | ||
92 | #define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 | ||
93 | #define reg_iop_sap_out_rw_bus___byte1_delay___width 1 | ||
94 | #define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 | ||
95 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 | ||
96 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 | ||
97 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 | ||
98 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 | ||
99 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 | ||
100 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 | ||
101 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 | ||
102 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 | ||
103 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 | ||
104 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 | ||
105 | #define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 | ||
106 | #define reg_iop_sap_out_rw_bus___byte2_delay___width 1 | ||
107 | #define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 | ||
108 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 | ||
109 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 | ||
110 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 | ||
111 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 | ||
112 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 | ||
113 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 | ||
114 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 | ||
115 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 | ||
116 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 | ||
117 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 | ||
118 | #define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 | ||
119 | #define reg_iop_sap_out_rw_bus___byte3_delay___width 1 | ||
120 | #define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 | ||
121 | #define reg_iop_sap_out_rw_bus_offset 4 | ||
122 | |||
123 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
124 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 | ||
125 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 | ||
126 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 | ||
127 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 | ||
128 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 | ||
129 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 | ||
130 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 | ||
131 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 | ||
132 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 | ||
133 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 | ||
134 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 | ||
135 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 | ||
136 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 | ||
137 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 | ||
138 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 | ||
139 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 | ||
140 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 | ||
141 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 | ||
142 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 | ||
143 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 | ||
144 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 | ||
145 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 | ||
146 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 | ||
147 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 | ||
148 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 | ||
149 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 | ||
150 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 | ||
151 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 | ||
152 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 | ||
153 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 | ||
154 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 | ||
155 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 | ||
156 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 | ||
157 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 | ||
158 | #define reg_iop_sap_out_rw_bus_lo_oe_offset 8 | ||
159 | |||
160 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
161 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 | ||
162 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 | ||
163 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 | ||
164 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 | ||
165 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 | ||
166 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 | ||
167 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 | ||
168 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 | ||
169 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 | ||
170 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 | ||
171 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 | ||
172 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 | ||
173 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 | ||
174 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 | ||
175 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 | ||
176 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 | ||
177 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 | ||
178 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 | ||
179 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 | ||
180 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 | ||
181 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 | ||
182 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 | ||
183 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 | ||
184 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 | ||
185 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 | ||
186 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 | ||
187 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 | ||
188 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 | ||
189 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 | ||
190 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 | ||
191 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 | ||
192 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 | ||
193 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 | ||
194 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 | ||
195 | #define reg_iop_sap_out_rw_bus_hi_oe_offset 12 | ||
196 | |||
197 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
198 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
199 | #define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 | ||
200 | #define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 | ||
201 | #define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 | ||
202 | #define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 | ||
203 | #define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 | ||
204 | #define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 | ||
205 | #define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 | ||
206 | #define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 | ||
207 | #define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 | ||
208 | #define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 | ||
209 | #define reg_iop_sap_out_rw_gio___out_delay___lsb 7 | ||
210 | #define reg_iop_sap_out_rw_gio___out_delay___width 1 | ||
211 | #define reg_iop_sap_out_rw_gio___out_delay___bit 7 | ||
212 | #define reg_iop_sap_out_rw_gio___out_logic___lsb 8 | ||
213 | #define reg_iop_sap_out_rw_gio___out_logic___width 2 | ||
214 | #define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 | ||
215 | #define reg_iop_sap_out_rw_gio___out_logic_src___width 2 | ||
216 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 | ||
217 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 | ||
218 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 | ||
219 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 | ||
220 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 | ||
221 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 | ||
222 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 | ||
223 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 | ||
224 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 | ||
225 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 | ||
226 | #define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 | ||
227 | #define reg_iop_sap_out_rw_gio___oe_delay___width 1 | ||
228 | #define reg_iop_sap_out_rw_gio___oe_delay___bit 19 | ||
229 | #define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 | ||
230 | #define reg_iop_sap_out_rw_gio___oe_logic___width 2 | ||
231 | #define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 | ||
232 | #define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 | ||
233 | #define reg_iop_sap_out_rw_gio_offset 16 | ||
234 | |||
235 | |||
236 | /* Constants */ | ||
237 | #define regk_iop_sap_out_always 0x00000001 | ||
238 | #define regk_iop_sap_out_and 0x00000002 | ||
239 | #define regk_iop_sap_out_clk0 0x00000000 | ||
240 | #define regk_iop_sap_out_clk1 0x00000001 | ||
241 | #define regk_iop_sap_out_clk12 0x00000004 | ||
242 | #define regk_iop_sap_out_clk200 0x00000000 | ||
243 | #define regk_iop_sap_out_ext 0x00000002 | ||
244 | #define regk_iop_sap_out_gated 0x00000003 | ||
245 | #define regk_iop_sap_out_gio0 0x00000000 | ||
246 | #define regk_iop_sap_out_gio1 0x00000000 | ||
247 | #define regk_iop_sap_out_gio16 0x00000002 | ||
248 | #define regk_iop_sap_out_gio17 0x00000002 | ||
249 | #define regk_iop_sap_out_gio24 0x00000003 | ||
250 | #define regk_iop_sap_out_gio25 0x00000003 | ||
251 | #define regk_iop_sap_out_gio8 0x00000001 | ||
252 | #define regk_iop_sap_out_gio9 0x00000001 | ||
253 | #define regk_iop_sap_out_gio_out10 0x00000005 | ||
254 | #define regk_iop_sap_out_gio_out18 0x00000006 | ||
255 | #define regk_iop_sap_out_gio_out2 0x00000004 | ||
256 | #define regk_iop_sap_out_gio_out26 0x00000007 | ||
257 | #define regk_iop_sap_out_inv 0x00000001 | ||
258 | #define regk_iop_sap_out_nand 0x00000003 | ||
259 | #define regk_iop_sap_out_no 0x00000000 | ||
260 | #define regk_iop_sap_out_none 0x00000000 | ||
261 | #define regk_iop_sap_out_one 0x00000001 | ||
262 | #define regk_iop_sap_out_rw_bus_default 0x00000000 | ||
263 | #define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 | ||
264 | #define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 | ||
265 | #define regk_iop_sap_out_rw_gen_gated_default 0x00000000 | ||
266 | #define regk_iop_sap_out_rw_gio_default 0x00000000 | ||
267 | #define regk_iop_sap_out_rw_gio_size 0x00000020 | ||
268 | #define regk_iop_sap_out_spu_gio6 0x00000002 | ||
269 | #define regk_iop_sap_out_spu_gio7 0x00000003 | ||
270 | #define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 | ||
271 | #define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 | ||
272 | #define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 | ||
273 | #define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 | ||
274 | #define regk_iop_sap_out_tmr200 0x00000001 | ||
275 | #define regk_iop_sap_out_yes 0x00000001 | ||
276 | #endif /* __iop_sap_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 00000000000..3b3949b51a6 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h | |||
@@ -0,0 +1,739 @@ | |||
1 | #ifndef __iop_sw_cfg_defs_asm_h | ||
2 | #define __iop_sw_cfg_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_cfg.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
54 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 | ||
55 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 | ||
56 | #define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 | ||
57 | |||
58 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
59 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 | ||
60 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 | ||
61 | #define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 | ||
62 | |||
63 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
64 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 | ||
65 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 | ||
66 | #define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 | ||
67 | |||
68 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
69 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 | ||
70 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 | ||
71 | #define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 | ||
72 | |||
73 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
74 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 | ||
75 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 | ||
76 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 | ||
77 | |||
78 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
79 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 | ||
80 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 | ||
81 | #define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 | ||
82 | |||
83 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
84 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 | ||
85 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 | ||
86 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 | ||
87 | |||
88 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
89 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 | ||
90 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 | ||
91 | #define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 | ||
92 | |||
93 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
94 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 | ||
95 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 | ||
96 | #define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 | ||
97 | |||
98 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
99 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 | ||
100 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 | ||
101 | #define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 | ||
102 | |||
103 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
104 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 | ||
105 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 | ||
106 | #define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 | ||
107 | |||
108 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
109 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 | ||
110 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 | ||
111 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 | ||
112 | #define reg_iop_sw_cfg_rw_spu_owner_offset 44 | ||
113 | |||
114 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
115 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 | ||
116 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 | ||
117 | #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 | ||
118 | |||
119 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
120 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 | ||
121 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 | ||
122 | #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 | ||
123 | |||
124 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
125 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 | ||
126 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 | ||
127 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 | ||
128 | |||
129 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
130 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 | ||
131 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 | ||
132 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 | ||
133 | |||
134 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
135 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 | ||
136 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 | ||
137 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 | ||
138 | |||
139 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
140 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 | ||
141 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 | ||
142 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 | ||
143 | |||
144 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
145 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 | ||
146 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 | ||
147 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 | ||
148 | |||
149 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
150 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 | ||
151 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 | ||
152 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 | ||
153 | |||
154 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
155 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 | ||
156 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 | ||
157 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 | ||
158 | |||
159 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
160 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 | ||
161 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 | ||
162 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 | ||
163 | |||
164 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
165 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 | ||
166 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 | ||
167 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 | ||
168 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 | ||
169 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 | ||
170 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 | ||
171 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 | ||
172 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 | ||
173 | #define reg_iop_sw_cfg_rw_bus_mask_offset 88 | ||
174 | |||
175 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
176 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 | ||
177 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 | ||
178 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 | ||
179 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 | ||
180 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 | ||
181 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 | ||
182 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 | ||
183 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 | ||
184 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 | ||
185 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 | ||
186 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 | ||
187 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 | ||
188 | #define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 | ||
189 | |||
190 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
191 | #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 | ||
192 | #define reg_iop_sw_cfg_rw_gio_mask___val___width 32 | ||
193 | #define reg_iop_sw_cfg_rw_gio_mask_offset 96 | ||
194 | |||
195 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
196 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 | ||
197 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 | ||
198 | #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 | ||
199 | |||
200 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
201 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 | ||
202 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 | ||
203 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 | ||
204 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 | ||
205 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 | ||
206 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 | ||
207 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 | ||
208 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 | ||
209 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 | ||
210 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 | ||
211 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 | ||
212 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 | ||
213 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 | ||
214 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 | ||
215 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 | ||
216 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 | ||
217 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 | ||
218 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 | ||
219 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 | ||
220 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 | ||
221 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 | ||
222 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 | ||
223 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 | ||
224 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 | ||
225 | #define reg_iop_sw_cfg_rw_pinmapping_offset 104 | ||
226 | |||
227 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
228 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 | ||
229 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 | ||
230 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 | ||
231 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 | ||
232 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 | ||
233 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 | ||
234 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 | ||
235 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 | ||
236 | #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 | ||
237 | |||
238 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
239 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 | ||
240 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 | ||
241 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 | ||
242 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 | ||
243 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 | ||
244 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 | ||
245 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 | ||
246 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 | ||
247 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 | ||
248 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 | ||
249 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 | ||
250 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 | ||
251 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 | ||
252 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 | ||
253 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 | ||
254 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 | ||
255 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 | ||
256 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 | ||
257 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 | ||
258 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 | ||
259 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 | ||
260 | |||
261 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
262 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 | ||
263 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 | ||
264 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 | ||
265 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 | ||
266 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 | ||
267 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 | ||
268 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 | ||
269 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 | ||
270 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 | ||
271 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 | ||
272 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 | ||
273 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 | ||
274 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 | ||
275 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 | ||
276 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 | ||
277 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 | ||
278 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 | ||
279 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 | ||
280 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 | ||
281 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 | ||
282 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 | ||
283 | |||
284 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
285 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 | ||
286 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 | ||
287 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 | ||
288 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 | ||
289 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 | ||
290 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 | ||
291 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 | ||
292 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 | ||
293 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 | ||
294 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 | ||
295 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 | ||
296 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 | ||
297 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 | ||
298 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 | ||
299 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 | ||
300 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 | ||
301 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 | ||
302 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 | ||
303 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 | ||
304 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 | ||
305 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 | ||
306 | |||
307 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
308 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 | ||
309 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 | ||
310 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 | ||
311 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 | ||
312 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 | ||
313 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 | ||
314 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 | ||
315 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 | ||
316 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 | ||
317 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 | ||
318 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 | ||
319 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 | ||
320 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 | ||
321 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 | ||
322 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 | ||
323 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 | ||
324 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 | ||
325 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 | ||
326 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 | ||
327 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 | ||
328 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 | ||
329 | |||
330 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
331 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 | ||
332 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 | ||
333 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 | ||
334 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 | ||
335 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 | ||
336 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 | ||
337 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 | ||
338 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 | ||
339 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 | ||
340 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 | ||
341 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 | ||
342 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 | ||
343 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 | ||
344 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 | ||
345 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 | ||
346 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 | ||
347 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 | ||
348 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 | ||
349 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 | ||
350 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 | ||
351 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 | ||
352 | |||
353 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
354 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 | ||
355 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 | ||
356 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 | ||
357 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 | ||
358 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 | ||
359 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 | ||
360 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 | ||
361 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 | ||
362 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 | ||
363 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 | ||
364 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 | ||
365 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 | ||
366 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 | ||
367 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 | ||
368 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 | ||
369 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 | ||
370 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 | ||
371 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 | ||
372 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 | ||
373 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 | ||
374 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 | ||
375 | |||
376 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
377 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 | ||
378 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 | ||
379 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 | ||
380 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 | ||
381 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 | ||
382 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 | ||
383 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 | ||
384 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 | ||
385 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 | ||
386 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 | ||
387 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 | ||
388 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 | ||
389 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 | ||
390 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 | ||
391 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 | ||
392 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 | ||
393 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 | ||
394 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 | ||
395 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 | ||
396 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 | ||
397 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 | ||
398 | |||
399 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
400 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 | ||
401 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 | ||
402 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 | ||
403 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 | ||
404 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 | ||
405 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 | ||
406 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 | ||
407 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 | ||
408 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 | ||
409 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 | ||
410 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 | ||
411 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 | ||
412 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 | ||
413 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 | ||
414 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 | ||
415 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 | ||
416 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 | ||
417 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 | ||
418 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 | ||
419 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 | ||
420 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 | ||
421 | |||
422 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
423 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 | ||
424 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 | ||
425 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 | ||
426 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 | ||
427 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 | ||
428 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 | ||
429 | #define reg_iop_sw_cfg_rw_spu_cfg_offset 144 | ||
430 | |||
431 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
432 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 | ||
433 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 | ||
434 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 | ||
435 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 | ||
436 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 | ||
437 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 | ||
438 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 | ||
439 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 | ||
440 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 | ||
441 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 | ||
442 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 | ||
443 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 | ||
444 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 | ||
445 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 | ||
446 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 | ||
447 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 | ||
448 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 | ||
449 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 | ||
450 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 | ||
451 | |||
452 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
453 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 | ||
454 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 | ||
455 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 | ||
456 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 | ||
457 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 | ||
458 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 | ||
459 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 | ||
460 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 | ||
461 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 | ||
462 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 | ||
463 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 | ||
464 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 | ||
465 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 | ||
466 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 | ||
467 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 | ||
468 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 | ||
469 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 | ||
470 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 | ||
471 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 | ||
472 | |||
473 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
474 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 | ||
475 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 | ||
476 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 | ||
477 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 | ||
478 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 | ||
479 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 | ||
480 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 | ||
481 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 | ||
482 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 | ||
483 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 | ||
484 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 | ||
485 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 | ||
486 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 | ||
487 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 | ||
488 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 | ||
489 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 | ||
490 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 | ||
491 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 | ||
492 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 | ||
493 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 | ||
494 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 | ||
495 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 | ||
496 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 | ||
497 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 | ||
498 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 | ||
499 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 | ||
500 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 | ||
501 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 | ||
502 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 | ||
503 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 | ||
504 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 | ||
505 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 | ||
506 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 | ||
507 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 | ||
508 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 | ||
509 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 | ||
510 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 | ||
511 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 | ||
512 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 | ||
513 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 | ||
514 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 | ||
515 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 | ||
516 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 | ||
517 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 | ||
518 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 | ||
519 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 | ||
520 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 | ||
521 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 | ||
522 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 | ||
523 | |||
524 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
525 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 | ||
526 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 | ||
527 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 | ||
528 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 | ||
529 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 | ||
530 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 | ||
531 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 | ||
532 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 | ||
533 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 | ||
534 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 | ||
535 | #define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 | ||
536 | |||
537 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
538 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 | ||
539 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 | ||
540 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 | ||
541 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 | ||
542 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 | ||
543 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 | ||
544 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 | ||
545 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 | ||
546 | #define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 | ||
547 | |||
548 | |||
549 | /* Constants */ | ||
550 | #define regk_iop_sw_cfg_a 0x00000001 | ||
551 | #define regk_iop_sw_cfg_b 0x00000002 | ||
552 | #define regk_iop_sw_cfg_bus 0x00000000 | ||
553 | #define regk_iop_sw_cfg_bus_rot16 0x00000002 | ||
554 | #define regk_iop_sw_cfg_bus_rot24 0x00000003 | ||
555 | #define regk_iop_sw_cfg_bus_rot8 0x00000001 | ||
556 | #define regk_iop_sw_cfg_clk12 0x00000000 | ||
557 | #define regk_iop_sw_cfg_cpu 0x00000000 | ||
558 | #define regk_iop_sw_cfg_gated_clk0 0x0000000e | ||
559 | #define regk_iop_sw_cfg_gated_clk1 0x0000000f | ||
560 | #define regk_iop_sw_cfg_gio0 0x00000004 | ||
561 | #define regk_iop_sw_cfg_gio1 0x00000001 | ||
562 | #define regk_iop_sw_cfg_gio2 0x00000005 | ||
563 | #define regk_iop_sw_cfg_gio3 0x00000002 | ||
564 | #define regk_iop_sw_cfg_gio4 0x00000006 | ||
565 | #define regk_iop_sw_cfg_gio5 0x00000003 | ||
566 | #define regk_iop_sw_cfg_gio6 0x00000007 | ||
567 | #define regk_iop_sw_cfg_gio7 0x00000004 | ||
568 | #define regk_iop_sw_cfg_gio_in18 0x00000002 | ||
569 | #define regk_iop_sw_cfg_gio_in19 0x00000003 | ||
570 | #define regk_iop_sw_cfg_gio_in20 0x00000004 | ||
571 | #define regk_iop_sw_cfg_gio_in21 0x00000005 | ||
572 | #define regk_iop_sw_cfg_gio_in26 0x00000006 | ||
573 | #define regk_iop_sw_cfg_gio_in27 0x00000007 | ||
574 | #define regk_iop_sw_cfg_gio_in4 0x00000000 | ||
575 | #define regk_iop_sw_cfg_gio_in5 0x00000001 | ||
576 | #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 | ||
577 | #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 | ||
578 | #define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 | ||
579 | #define regk_iop_sw_cfg_mpu 0x00000001 | ||
580 | #define regk_iop_sw_cfg_none 0x00000000 | ||
581 | #define regk_iop_sw_cfg_pdp_out 0x00000001 | ||
582 | #define regk_iop_sw_cfg_pdp_out_hi 0x00000001 | ||
583 | #define regk_iop_sw_cfg_pdp_out_lo 0x00000000 | ||
584 | #define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 | ||
585 | #define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 | ||
586 | #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 | ||
587 | #define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 | ||
588 | #define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 | ||
589 | #define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 | ||
590 | #define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 | ||
591 | #define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 | ||
592 | #define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 | ||
593 | #define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 | ||
594 | #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 | ||
595 | #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 | ||
596 | #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 | ||
597 | #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 | ||
598 | #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 | ||
599 | #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 | ||
600 | #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 | ||
601 | #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 | ||
602 | #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 | ||
603 | #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 | ||
604 | #define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 | ||
605 | #define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 | ||
606 | #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 | ||
607 | #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 | ||
608 | #define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 | ||
609 | #define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 | ||
610 | #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 | ||
611 | #define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 | ||
612 | #define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 | ||
613 | #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 | ||
614 | #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 | ||
615 | #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 | ||
616 | #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 | ||
617 | #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 | ||
618 | #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 | ||
619 | #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 | ||
620 | #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 | ||
621 | #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 | ||
622 | #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 | ||
623 | #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 | ||
624 | #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 | ||
625 | #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 | ||
626 | #define regk_iop_sw_cfg_sdp_out 0x00000004 | ||
627 | #define regk_iop_sw_cfg_size16 0x00000002 | ||
628 | #define regk_iop_sw_cfg_size24 0x00000003 | ||
629 | #define regk_iop_sw_cfg_size32 0x00000004 | ||
630 | #define regk_iop_sw_cfg_size8 0x00000001 | ||
631 | #define regk_iop_sw_cfg_spu 0x00000002 | ||
632 | #define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 | ||
633 | #define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 | ||
634 | #define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 | ||
635 | #define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 | ||
636 | #define regk_iop_sw_cfg_spu_g0 0x00000007 | ||
637 | #define regk_iop_sw_cfg_spu_g1 0x00000007 | ||
638 | #define regk_iop_sw_cfg_spu_g2 0x00000007 | ||
639 | #define regk_iop_sw_cfg_spu_g3 0x00000007 | ||
640 | #define regk_iop_sw_cfg_spu_g4 0x00000007 | ||
641 | #define regk_iop_sw_cfg_spu_g5 0x00000007 | ||
642 | #define regk_iop_sw_cfg_spu_g6 0x00000007 | ||
643 | #define regk_iop_sw_cfg_spu_g7 0x00000007 | ||
644 | #define regk_iop_sw_cfg_spu_gio0 0x00000000 | ||
645 | #define regk_iop_sw_cfg_spu_gio1 0x00000001 | ||
646 | #define regk_iop_sw_cfg_spu_gio5 0x00000005 | ||
647 | #define regk_iop_sw_cfg_spu_gio6 0x00000006 | ||
648 | #define regk_iop_sw_cfg_spu_gio7 0x00000007 | ||
649 | #define regk_iop_sw_cfg_spu_gio_out0 0x00000008 | ||
650 | #define regk_iop_sw_cfg_spu_gio_out1 0x00000009 | ||
651 | #define regk_iop_sw_cfg_spu_gio_out2 0x0000000a | ||
652 | #define regk_iop_sw_cfg_spu_gio_out3 0x0000000b | ||
653 | #define regk_iop_sw_cfg_spu_gio_out4 0x0000000c | ||
654 | #define regk_iop_sw_cfg_spu_gio_out5 0x0000000d | ||
655 | #define regk_iop_sw_cfg_spu_gio_out6 0x0000000e | ||
656 | #define regk_iop_sw_cfg_spu_gio_out7 0x0000000f | ||
657 | #define regk_iop_sw_cfg_spu_gioout0 0x00000000 | ||
658 | #define regk_iop_sw_cfg_spu_gioout1 0x00000000 | ||
659 | #define regk_iop_sw_cfg_spu_gioout10 0x00000007 | ||
660 | #define regk_iop_sw_cfg_spu_gioout11 0x00000007 | ||
661 | #define regk_iop_sw_cfg_spu_gioout12 0x00000007 | ||
662 | #define regk_iop_sw_cfg_spu_gioout13 0x00000007 | ||
663 | #define regk_iop_sw_cfg_spu_gioout14 0x00000007 | ||
664 | #define regk_iop_sw_cfg_spu_gioout15 0x00000007 | ||
665 | #define regk_iop_sw_cfg_spu_gioout16 0x00000007 | ||
666 | #define regk_iop_sw_cfg_spu_gioout17 0x00000007 | ||
667 | #define regk_iop_sw_cfg_spu_gioout18 0x00000007 | ||
668 | #define regk_iop_sw_cfg_spu_gioout19 0x00000007 | ||
669 | #define regk_iop_sw_cfg_spu_gioout2 0x00000001 | ||
670 | #define regk_iop_sw_cfg_spu_gioout20 0x00000007 | ||
671 | #define regk_iop_sw_cfg_spu_gioout21 0x00000007 | ||
672 | #define regk_iop_sw_cfg_spu_gioout22 0x00000007 | ||
673 | #define regk_iop_sw_cfg_spu_gioout23 0x00000007 | ||
674 | #define regk_iop_sw_cfg_spu_gioout24 0x00000007 | ||
675 | #define regk_iop_sw_cfg_spu_gioout25 0x00000007 | ||
676 | #define regk_iop_sw_cfg_spu_gioout26 0x00000007 | ||
677 | #define regk_iop_sw_cfg_spu_gioout27 0x00000007 | ||
678 | #define regk_iop_sw_cfg_spu_gioout28 0x00000007 | ||
679 | #define regk_iop_sw_cfg_spu_gioout29 0x00000007 | ||
680 | #define regk_iop_sw_cfg_spu_gioout3 0x00000001 | ||
681 | #define regk_iop_sw_cfg_spu_gioout30 0x00000007 | ||
682 | #define regk_iop_sw_cfg_spu_gioout31 0x00000007 | ||
683 | #define regk_iop_sw_cfg_spu_gioout4 0x00000002 | ||
684 | #define regk_iop_sw_cfg_spu_gioout5 0x00000002 | ||
685 | #define regk_iop_sw_cfg_spu_gioout6 0x00000003 | ||
686 | #define regk_iop_sw_cfg_spu_gioout7 0x00000003 | ||
687 | #define regk_iop_sw_cfg_spu_gioout8 0x00000007 | ||
688 | #define regk_iop_sw_cfg_spu_gioout9 0x00000007 | ||
689 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 | ||
690 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 | ||
691 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 | ||
692 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 | ||
693 | #define regk_iop_sw_cfg_timer_grp0 0x00000000 | ||
694 | #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 | ||
695 | #define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 | ||
696 | #define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 | ||
697 | #define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 | ||
698 | #define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 | ||
699 | #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 | ||
700 | #define regk_iop_sw_cfg_timer_grp1 0x00000000 | ||
701 | #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 | ||
702 | #define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 | ||
703 | #define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 | ||
704 | #define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 | ||
705 | #define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 | ||
706 | #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 | ||
707 | #define regk_iop_sw_cfg_trig0_0 0x00000000 | ||
708 | #define regk_iop_sw_cfg_trig0_1 0x00000000 | ||
709 | #define regk_iop_sw_cfg_trig0_2 0x00000000 | ||
710 | #define regk_iop_sw_cfg_trig0_3 0x00000000 | ||
711 | #define regk_iop_sw_cfg_trig1_0 0x00000000 | ||
712 | #define regk_iop_sw_cfg_trig1_1 0x00000000 | ||
713 | #define regk_iop_sw_cfg_trig1_2 0x00000000 | ||
714 | #define regk_iop_sw_cfg_trig1_3 0x00000000 | ||
715 | #define regk_iop_sw_cfg_trig2_0 0x00000001 | ||
716 | #define regk_iop_sw_cfg_trig2_1 0x00000001 | ||
717 | #define regk_iop_sw_cfg_trig2_2 0x00000001 | ||
718 | #define regk_iop_sw_cfg_trig2_3 0x00000001 | ||
719 | #define regk_iop_sw_cfg_trig3_0 0x00000001 | ||
720 | #define regk_iop_sw_cfg_trig3_1 0x00000001 | ||
721 | #define regk_iop_sw_cfg_trig3_2 0x00000001 | ||
722 | #define regk_iop_sw_cfg_trig3_3 0x00000001 | ||
723 | #define regk_iop_sw_cfg_trig4_0 0x00000002 | ||
724 | #define regk_iop_sw_cfg_trig4_1 0x00000002 | ||
725 | #define regk_iop_sw_cfg_trig4_2 0x00000002 | ||
726 | #define regk_iop_sw_cfg_trig4_3 0x00000002 | ||
727 | #define regk_iop_sw_cfg_trig5_0 0x00000002 | ||
728 | #define regk_iop_sw_cfg_trig5_1 0x00000002 | ||
729 | #define regk_iop_sw_cfg_trig5_2 0x00000002 | ||
730 | #define regk_iop_sw_cfg_trig5_3 0x00000002 | ||
731 | #define regk_iop_sw_cfg_trig6_0 0x00000003 | ||
732 | #define regk_iop_sw_cfg_trig6_1 0x00000003 | ||
733 | #define regk_iop_sw_cfg_trig6_2 0x00000003 | ||
734 | #define regk_iop_sw_cfg_trig6_3 0x00000003 | ||
735 | #define regk_iop_sw_cfg_trig7_0 0x00000003 | ||
736 | #define regk_iop_sw_cfg_trig7_1 0x00000003 | ||
737 | #define regk_iop_sw_cfg_trig7_2 0x00000003 | ||
738 | #define regk_iop_sw_cfg_trig7_3 0x00000003 | ||
739 | #endif /* __iop_sw_cfg_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 00000000000..3f4fe1b3181 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h | |||
@@ -0,0 +1,950 @@ | |||
1 | #ifndef __iop_sw_cpu_defs_asm_h | ||
2 | #define __iop_sw_cpu_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_cpu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
54 | #define reg_iop_sw_cpu_r_mpu_trace_offset 0 | ||
55 | |||
56 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
57 | #define reg_iop_sw_cpu_r_spu_trace_offset 4 | ||
58 | |||
59 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
60 | #define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 | ||
61 | |||
62 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
63 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
64 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 | ||
65 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 | ||
66 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 | ||
67 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 | ||
68 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 | ||
69 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 | ||
70 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
71 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
72 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
73 | #define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 | ||
74 | |||
75 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
76 | #define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 | ||
77 | #define reg_iop_sw_cpu_rw_mc_data___val___width 32 | ||
78 | #define reg_iop_sw_cpu_rw_mc_data_offset 16 | ||
79 | |||
80 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
81 | #define reg_iop_sw_cpu_rw_mc_addr_offset 20 | ||
82 | |||
83 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
84 | #define reg_iop_sw_cpu_rs_mc_data_offset 24 | ||
85 | |||
86 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
87 | #define reg_iop_sw_cpu_r_mc_data_offset 28 | ||
88 | |||
89 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
90 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 | ||
91 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 | ||
92 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 | ||
93 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 | ||
94 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 | ||
95 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 | ||
96 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 | ||
97 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 | ||
98 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 | ||
99 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
100 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 | ||
101 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 | ||
102 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
103 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 | ||
104 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 | ||
105 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 | ||
106 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 | ||
107 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 | ||
108 | #define reg_iop_sw_cpu_r_mc_stat_offset 32 | ||
109 | |||
110 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
111 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 | ||
112 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 | ||
113 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 | ||
114 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 | ||
115 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 | ||
116 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 | ||
117 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 | ||
118 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 | ||
119 | #define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 | ||
120 | |||
121 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
122 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 | ||
123 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 | ||
124 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 | ||
125 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 | ||
126 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 | ||
127 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 | ||
128 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 | ||
129 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 | ||
130 | #define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 | ||
131 | |||
132 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
133 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
134 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
135 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
136 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
137 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
138 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
139 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
140 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
141 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
142 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
143 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
144 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
145 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 | ||
146 | |||
147 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
148 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
149 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 | ||
150 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
151 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
152 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 | ||
153 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
154 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
155 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 | ||
156 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
157 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
158 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 | ||
159 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
160 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 | ||
161 | |||
162 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
163 | #define reg_iop_sw_cpu_r_bus_in_offset 52 | ||
164 | |||
165 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
166 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 | ||
167 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 | ||
168 | #define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 | ||
169 | |||
170 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
171 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 | ||
172 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 | ||
173 | #define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 | ||
174 | |||
175 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
176 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
177 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 | ||
178 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 | ||
179 | |||
180 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
181 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 | ||
182 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 | ||
183 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 | ||
184 | |||
185 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
186 | #define reg_iop_sw_cpu_r_gio_in_offset 72 | ||
187 | |||
188 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
189 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 | ||
190 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 | ||
191 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 | ||
192 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 | ||
193 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 | ||
194 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 | ||
195 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 | ||
196 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 | ||
197 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 | ||
198 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 | ||
199 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 | ||
200 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 | ||
201 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 | ||
202 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 | ||
203 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 | ||
204 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 | ||
205 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 | ||
206 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 | ||
207 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 | ||
208 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 | ||
209 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 | ||
210 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 | ||
211 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 | ||
212 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 | ||
213 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 | ||
214 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 | ||
215 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 | ||
216 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 | ||
217 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 | ||
218 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 | ||
219 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 | ||
220 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 | ||
221 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 | ||
222 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 | ||
223 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 | ||
224 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 | ||
225 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 | ||
226 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 | ||
227 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 | ||
228 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 | ||
229 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 | ||
230 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 | ||
231 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 | ||
232 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 | ||
233 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 | ||
234 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 | ||
235 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 | ||
236 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 | ||
237 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 | ||
238 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 | ||
239 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 | ||
240 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 | ||
241 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 | ||
242 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 | ||
243 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 | ||
244 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 | ||
245 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 | ||
246 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 | ||
247 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 | ||
248 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 | ||
249 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 | ||
250 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 | ||
251 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 | ||
252 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 | ||
253 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 | ||
254 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 | ||
255 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 | ||
256 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 | ||
257 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 | ||
258 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 | ||
259 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 | ||
260 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 | ||
261 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 | ||
262 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 | ||
263 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 | ||
264 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 | ||
265 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 | ||
266 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 | ||
267 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 | ||
268 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 | ||
269 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 | ||
270 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 | ||
271 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 | ||
272 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 | ||
273 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 | ||
274 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 | ||
275 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 | ||
276 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 | ||
277 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 | ||
278 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 | ||
279 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 | ||
280 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 | ||
281 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 | ||
282 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 | ||
283 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 | ||
284 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 | ||
285 | #define reg_iop_sw_cpu_rw_intr0_mask_offset 76 | ||
286 | |||
287 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
288 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 | ||
289 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 | ||
290 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 | ||
291 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 | ||
292 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 | ||
293 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 | ||
294 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 | ||
295 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 | ||
296 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 | ||
297 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 | ||
298 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 | ||
299 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 | ||
300 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 | ||
301 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 | ||
302 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 | ||
303 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 | ||
304 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 | ||
305 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 | ||
306 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 | ||
307 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 | ||
308 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 | ||
309 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 | ||
310 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 | ||
311 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 | ||
312 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 | ||
313 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 | ||
314 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 | ||
315 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 | ||
316 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 | ||
317 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 | ||
318 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 | ||
319 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 | ||
320 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 | ||
321 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 | ||
322 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 | ||
323 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 | ||
324 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 | ||
325 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 | ||
326 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 | ||
327 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 | ||
328 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 | ||
329 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 | ||
330 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 | ||
331 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 | ||
332 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 | ||
333 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 | ||
334 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 | ||
335 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 | ||
336 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 | ||
337 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 | ||
338 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 | ||
339 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 | ||
340 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 | ||
341 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 | ||
342 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 | ||
343 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 | ||
344 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 | ||
345 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 | ||
346 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 | ||
347 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 | ||
348 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 | ||
349 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 | ||
350 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 | ||
351 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 | ||
352 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 | ||
353 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 | ||
354 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 | ||
355 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 | ||
356 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 | ||
357 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 | ||
358 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 | ||
359 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 | ||
360 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 | ||
361 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 | ||
362 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 | ||
363 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 | ||
364 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 | ||
365 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 | ||
366 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 | ||
367 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 | ||
368 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 | ||
369 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 | ||
370 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 | ||
371 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 | ||
372 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 | ||
373 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 | ||
374 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 | ||
375 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 | ||
376 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 | ||
377 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 | ||
378 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 | ||
379 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 | ||
380 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 | ||
381 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 | ||
382 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 | ||
383 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 | ||
384 | #define reg_iop_sw_cpu_rw_ack_intr0_offset 80 | ||
385 | |||
386 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
387 | #define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 | ||
388 | #define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 | ||
389 | #define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 | ||
390 | #define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 | ||
391 | #define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 | ||
392 | #define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 | ||
393 | #define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 | ||
394 | #define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 | ||
395 | #define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 | ||
396 | #define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 | ||
397 | #define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 | ||
398 | #define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 | ||
399 | #define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 | ||
400 | #define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 | ||
401 | #define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 | ||
402 | #define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 | ||
403 | #define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 | ||
404 | #define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 | ||
405 | #define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 | ||
406 | #define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 | ||
407 | #define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 | ||
408 | #define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 | ||
409 | #define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 | ||
410 | #define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 | ||
411 | #define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 | ||
412 | #define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 | ||
413 | #define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 | ||
414 | #define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 | ||
415 | #define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 | ||
416 | #define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 | ||
417 | #define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 | ||
418 | #define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 | ||
419 | #define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 | ||
420 | #define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 | ||
421 | #define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 | ||
422 | #define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 | ||
423 | #define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 | ||
424 | #define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 | ||
425 | #define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 | ||
426 | #define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 | ||
427 | #define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 | ||
428 | #define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 | ||
429 | #define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 | ||
430 | #define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 | ||
431 | #define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 | ||
432 | #define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 | ||
433 | #define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 | ||
434 | #define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 | ||
435 | #define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 | ||
436 | #define reg_iop_sw_cpu_r_intr0___spu_0___width 1 | ||
437 | #define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 | ||
438 | #define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 | ||
439 | #define reg_iop_sw_cpu_r_intr0___spu_1___width 1 | ||
440 | #define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 | ||
441 | #define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 | ||
442 | #define reg_iop_sw_cpu_r_intr0___spu_2___width 1 | ||
443 | #define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 | ||
444 | #define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 | ||
445 | #define reg_iop_sw_cpu_r_intr0___spu_3___width 1 | ||
446 | #define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 | ||
447 | #define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 | ||
448 | #define reg_iop_sw_cpu_r_intr0___spu_4___width 1 | ||
449 | #define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 | ||
450 | #define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 | ||
451 | #define reg_iop_sw_cpu_r_intr0___spu_5___width 1 | ||
452 | #define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 | ||
453 | #define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 | ||
454 | #define reg_iop_sw_cpu_r_intr0___spu_6___width 1 | ||
455 | #define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 | ||
456 | #define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 | ||
457 | #define reg_iop_sw_cpu_r_intr0___spu_7___width 1 | ||
458 | #define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 | ||
459 | #define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 | ||
460 | #define reg_iop_sw_cpu_r_intr0___spu_8___width 1 | ||
461 | #define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 | ||
462 | #define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 | ||
463 | #define reg_iop_sw_cpu_r_intr0___spu_9___width 1 | ||
464 | #define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 | ||
465 | #define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 | ||
466 | #define reg_iop_sw_cpu_r_intr0___spu_10___width 1 | ||
467 | #define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 | ||
468 | #define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 | ||
469 | #define reg_iop_sw_cpu_r_intr0___spu_11___width 1 | ||
470 | #define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 | ||
471 | #define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 | ||
472 | #define reg_iop_sw_cpu_r_intr0___spu_12___width 1 | ||
473 | #define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 | ||
474 | #define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 | ||
475 | #define reg_iop_sw_cpu_r_intr0___spu_13___width 1 | ||
476 | #define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 | ||
477 | #define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 | ||
478 | #define reg_iop_sw_cpu_r_intr0___spu_14___width 1 | ||
479 | #define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 | ||
480 | #define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 | ||
481 | #define reg_iop_sw_cpu_r_intr0___spu_15___width 1 | ||
482 | #define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 | ||
483 | #define reg_iop_sw_cpu_r_intr0_offset 84 | ||
484 | |||
485 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
486 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 | ||
487 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 | ||
488 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 | ||
489 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 | ||
490 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 | ||
491 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 | ||
492 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 | ||
493 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 | ||
494 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 | ||
495 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 | ||
496 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 | ||
497 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 | ||
498 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 | ||
499 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 | ||
500 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 | ||
501 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 | ||
502 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 | ||
503 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 | ||
504 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 | ||
505 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 | ||
506 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 | ||
507 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 | ||
508 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 | ||
509 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 | ||
510 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 | ||
511 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 | ||
512 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 | ||
513 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 | ||
514 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 | ||
515 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 | ||
516 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 | ||
517 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 | ||
518 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 | ||
519 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 | ||
520 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 | ||
521 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 | ||
522 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 | ||
523 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 | ||
524 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 | ||
525 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 | ||
526 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 | ||
527 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 | ||
528 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 | ||
529 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 | ||
530 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 | ||
531 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 | ||
532 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 | ||
533 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 | ||
534 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 | ||
535 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 | ||
536 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 | ||
537 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 | ||
538 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 | ||
539 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 | ||
540 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 | ||
541 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 | ||
542 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 | ||
543 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 | ||
544 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 | ||
545 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 | ||
546 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 | ||
547 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 | ||
548 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 | ||
549 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 | ||
550 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 | ||
551 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 | ||
552 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 | ||
553 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 | ||
554 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 | ||
555 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 | ||
556 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 | ||
557 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 | ||
558 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 | ||
559 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 | ||
560 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 | ||
561 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 | ||
562 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 | ||
563 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 | ||
564 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 | ||
565 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 | ||
566 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 | ||
567 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 | ||
568 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 | ||
569 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 | ||
570 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 | ||
571 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 | ||
572 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 | ||
573 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 | ||
574 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 | ||
575 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 | ||
576 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 | ||
577 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 | ||
578 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 | ||
579 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 | ||
580 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 | ||
581 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 | ||
582 | #define reg_iop_sw_cpu_r_masked_intr0_offset 88 | ||
583 | |||
584 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
585 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 | ||
586 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 | ||
587 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 | ||
588 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 | ||
589 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 | ||
590 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 | ||
591 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 | ||
592 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 | ||
593 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 | ||
594 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 | ||
595 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 | ||
596 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 | ||
597 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 | ||
598 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 | ||
599 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 | ||
600 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 | ||
601 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 | ||
602 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 | ||
603 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 | ||
604 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 | ||
605 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 | ||
606 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 | ||
607 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 | ||
608 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 | ||
609 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 | ||
610 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 | ||
611 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 | ||
612 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 | ||
613 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 | ||
614 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 | ||
615 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 | ||
616 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 | ||
617 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 | ||
618 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 | ||
619 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 | ||
620 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 | ||
621 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 | ||
622 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 | ||
623 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 | ||
624 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 | ||
625 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 | ||
626 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 | ||
627 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 | ||
628 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 | ||
629 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 | ||
630 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 | ||
631 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 | ||
632 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 | ||
633 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 | ||
634 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 | ||
635 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 | ||
636 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 | ||
637 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 | ||
638 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 | ||
639 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 | ||
640 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 | ||
641 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 | ||
642 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 | ||
643 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 | ||
644 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 | ||
645 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 | ||
646 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 | ||
647 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 | ||
648 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 | ||
649 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 | ||
650 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 | ||
651 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 | ||
652 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 | ||
653 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 | ||
654 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 | ||
655 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 | ||
656 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 | ||
657 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 | ||
658 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 | ||
659 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 | ||
660 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 | ||
661 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 | ||
662 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 | ||
663 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 | ||
664 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 | ||
665 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 | ||
666 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 | ||
667 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 | ||
668 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 | ||
669 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 | ||
670 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 | ||
671 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 | ||
672 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 | ||
673 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 | ||
674 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 | ||
675 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 | ||
676 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 | ||
677 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 | ||
678 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 | ||
679 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 | ||
680 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 | ||
681 | #define reg_iop_sw_cpu_rw_intr1_mask_offset 92 | ||
682 | |||
683 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
684 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 | ||
685 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 | ||
686 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 | ||
687 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 | ||
688 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 | ||
689 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 | ||
690 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 | ||
691 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 | ||
692 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 | ||
693 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 | ||
694 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 | ||
695 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 | ||
696 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 | ||
697 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 | ||
698 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 | ||
699 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 | ||
700 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 | ||
701 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 | ||
702 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 | ||
703 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 | ||
704 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 | ||
705 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 | ||
706 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 | ||
707 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 | ||
708 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 | ||
709 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 | ||
710 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 | ||
711 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 | ||
712 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 | ||
713 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 | ||
714 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 | ||
715 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 | ||
716 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 | ||
717 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 | ||
718 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 | ||
719 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 | ||
720 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 | ||
721 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 | ||
722 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 | ||
723 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 | ||
724 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 | ||
725 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 | ||
726 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 | ||
727 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 | ||
728 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 | ||
729 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 | ||
730 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 | ||
731 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 | ||
732 | #define reg_iop_sw_cpu_rw_ack_intr1_offset 96 | ||
733 | |||
734 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
735 | #define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 | ||
736 | #define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 | ||
737 | #define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 | ||
738 | #define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 | ||
739 | #define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 | ||
740 | #define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 | ||
741 | #define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 | ||
742 | #define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 | ||
743 | #define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 | ||
744 | #define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 | ||
745 | #define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 | ||
746 | #define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 | ||
747 | #define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 | ||
748 | #define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 | ||
749 | #define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 | ||
750 | #define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 | ||
751 | #define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 | ||
752 | #define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 | ||
753 | #define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 | ||
754 | #define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 | ||
755 | #define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 | ||
756 | #define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 | ||
757 | #define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 | ||
758 | #define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 | ||
759 | #define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 | ||
760 | #define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 | ||
761 | #define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 | ||
762 | #define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 | ||
763 | #define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 | ||
764 | #define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 | ||
765 | #define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 | ||
766 | #define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 | ||
767 | #define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 | ||
768 | #define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 | ||
769 | #define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 | ||
770 | #define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 | ||
771 | #define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 | ||
772 | #define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 | ||
773 | #define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 | ||
774 | #define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 | ||
775 | #define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 | ||
776 | #define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 | ||
777 | #define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 | ||
778 | #define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 | ||
779 | #define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 | ||
780 | #define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 | ||
781 | #define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 | ||
782 | #define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 | ||
783 | #define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 | ||
784 | #define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 | ||
785 | #define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 | ||
786 | #define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 | ||
787 | #define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 | ||
788 | #define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 | ||
789 | #define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 | ||
790 | #define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 | ||
791 | #define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 | ||
792 | #define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 | ||
793 | #define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 | ||
794 | #define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 | ||
795 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 | ||
796 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 | ||
797 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 | ||
798 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 | ||
799 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 | ||
800 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 | ||
801 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 | ||
802 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 | ||
803 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 | ||
804 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 | ||
805 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 | ||
806 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 | ||
807 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 | ||
808 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 | ||
809 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 | ||
810 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 | ||
811 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 | ||
812 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 | ||
813 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 | ||
814 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 | ||
815 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 | ||
816 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 | ||
817 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 | ||
818 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 | ||
819 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 | ||
820 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 | ||
821 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 | ||
822 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 | ||
823 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 | ||
824 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 | ||
825 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 | ||
826 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 | ||
827 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 | ||
828 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 | ||
829 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 | ||
830 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 | ||
831 | #define reg_iop_sw_cpu_r_intr1_offset 100 | ||
832 | |||
833 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
834 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 | ||
835 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 | ||
836 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 | ||
837 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 | ||
838 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 | ||
839 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 | ||
840 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 | ||
841 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 | ||
842 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 | ||
843 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 | ||
844 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 | ||
845 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 | ||
846 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 | ||
847 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 | ||
848 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 | ||
849 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 | ||
850 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 | ||
851 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 | ||
852 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 | ||
853 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 | ||
854 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 | ||
855 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 | ||
856 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 | ||
857 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 | ||
858 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 | ||
859 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 | ||
860 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 | ||
861 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 | ||
862 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 | ||
863 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 | ||
864 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 | ||
865 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 | ||
866 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 | ||
867 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 | ||
868 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 | ||
869 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 | ||
870 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 | ||
871 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 | ||
872 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 | ||
873 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 | ||
874 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 | ||
875 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 | ||
876 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 | ||
877 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 | ||
878 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 | ||
879 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 | ||
880 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 | ||
881 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 | ||
882 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 | ||
883 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 | ||
884 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 | ||
885 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 | ||
886 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 | ||
887 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 | ||
888 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 | ||
889 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 | ||
890 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 | ||
891 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 | ||
892 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 | ||
893 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 | ||
894 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 | ||
895 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 | ||
896 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 | ||
897 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 | ||
898 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 | ||
899 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 | ||
900 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 | ||
901 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 | ||
902 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 | ||
903 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 | ||
904 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 | ||
905 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 | ||
906 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 | ||
907 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 | ||
908 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 | ||
909 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 | ||
910 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 | ||
911 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 | ||
912 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 | ||
913 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 | ||
914 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 | ||
915 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 | ||
916 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 | ||
917 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 | ||
918 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 | ||
919 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 | ||
920 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 | ||
921 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 | ||
922 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 | ||
923 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 | ||
924 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 | ||
925 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 | ||
926 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 | ||
927 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 | ||
928 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 | ||
929 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 | ||
930 | #define reg_iop_sw_cpu_r_masked_intr1_offset 104 | ||
931 | |||
932 | |||
933 | /* Constants */ | ||
934 | #define regk_iop_sw_cpu_copy 0x00000000 | ||
935 | #define regk_iop_sw_cpu_no 0x00000000 | ||
936 | #define regk_iop_sw_cpu_rd 0x00000002 | ||
937 | #define regk_iop_sw_cpu_reg_copy 0x00000001 | ||
938 | #define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 | ||
939 | #define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
940 | #define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 | ||
941 | #define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 | ||
942 | #define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 | ||
943 | #define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
944 | #define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 | ||
945 | #define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 | ||
946 | #define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 | ||
947 | #define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 | ||
948 | #define regk_iop_sw_cpu_wr 0x00000003 | ||
949 | #define regk_iop_sw_cpu_yes 0x00000001 | ||
950 | #endif /* __iop_sw_cpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 00000000000..ffcc83b22d2 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h | |||
@@ -0,0 +1,1086 @@ | |||
1 | #ifndef __iop_sw_mpu_defs_asm_h | ||
2 | #define __iop_sw_mpu_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_mpu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
54 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 | ||
55 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 | ||
56 | #define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 | ||
57 | |||
58 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
59 | #define reg_iop_sw_mpu_r_spu_trace_offset 4 | ||
60 | |||
61 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
62 | #define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 | ||
63 | |||
64 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
65 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
66 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 | ||
67 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 | ||
68 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 | ||
69 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 | ||
70 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 | ||
71 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 | ||
72 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
73 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
74 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
75 | #define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 | ||
76 | |||
77 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
78 | #define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 | ||
79 | #define reg_iop_sw_mpu_rw_mc_data___val___width 32 | ||
80 | #define reg_iop_sw_mpu_rw_mc_data_offset 16 | ||
81 | |||
82 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
83 | #define reg_iop_sw_mpu_rw_mc_addr_offset 20 | ||
84 | |||
85 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
86 | #define reg_iop_sw_mpu_rs_mc_data_offset 24 | ||
87 | |||
88 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
89 | #define reg_iop_sw_mpu_r_mc_data_offset 28 | ||
90 | |||
91 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
92 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 | ||
93 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 | ||
94 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 | ||
95 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 | ||
96 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 | ||
97 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 | ||
98 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 | ||
99 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 | ||
100 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 | ||
101 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
102 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 | ||
103 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 | ||
104 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
105 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 | ||
106 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 | ||
107 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 | ||
108 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 | ||
109 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 | ||
110 | #define reg_iop_sw_mpu_r_mc_stat_offset 32 | ||
111 | |||
112 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
113 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 | ||
114 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 | ||
115 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 | ||
116 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 | ||
117 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 | ||
118 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 | ||
119 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 | ||
120 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 | ||
121 | #define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 | ||
122 | |||
123 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
124 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 | ||
125 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 | ||
126 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 | ||
127 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 | ||
128 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 | ||
129 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 | ||
130 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 | ||
131 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 | ||
132 | #define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 | ||
133 | |||
134 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
135 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
136 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
137 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
138 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
139 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
140 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
141 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
142 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
143 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
144 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
145 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
146 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
147 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 | ||
148 | |||
149 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
150 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
151 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 | ||
152 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
153 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
154 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 | ||
155 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
156 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
157 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 | ||
158 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
159 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
160 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 | ||
161 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
162 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 | ||
163 | |||
164 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
165 | #define reg_iop_sw_mpu_r_bus_in_offset 52 | ||
166 | |||
167 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
168 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 | ||
169 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 | ||
170 | #define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 | ||
171 | |||
172 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
173 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 | ||
174 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 | ||
175 | #define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 | ||
176 | |||
177 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
178 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
179 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 | ||
180 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 | ||
181 | |||
182 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
183 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 | ||
184 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 | ||
185 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 | ||
186 | |||
187 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
188 | #define reg_iop_sw_mpu_r_gio_in_offset 72 | ||
189 | |||
190 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
191 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 | ||
192 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 | ||
193 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 | ||
194 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 | ||
195 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 | ||
196 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 | ||
197 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 | ||
198 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 | ||
199 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 | ||
200 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 | ||
201 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 | ||
202 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 | ||
203 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 | ||
204 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 | ||
205 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 | ||
206 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 | ||
207 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 | ||
208 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 | ||
209 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 | ||
210 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 | ||
211 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 | ||
212 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 | ||
213 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 | ||
214 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 | ||
215 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 | ||
216 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 | ||
217 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 | ||
218 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 | ||
219 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 | ||
220 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 | ||
221 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 | ||
222 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 | ||
223 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 | ||
224 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 | ||
225 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 | ||
226 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 | ||
227 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 | ||
228 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 | ||
229 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 | ||
230 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 | ||
231 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 | ||
232 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 | ||
233 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 | ||
234 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 | ||
235 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 | ||
236 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 | ||
237 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 | ||
238 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 | ||
239 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 | ||
240 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 | ||
241 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 | ||
242 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 | ||
243 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 | ||
244 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 | ||
245 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 | ||
246 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 | ||
247 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 | ||
248 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 | ||
249 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 | ||
250 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 | ||
251 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 | ||
252 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 | ||
253 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 | ||
254 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 | ||
255 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 | ||
256 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 | ||
257 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 | ||
258 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 | ||
259 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 | ||
260 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 | ||
261 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 | ||
262 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 | ||
263 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 | ||
264 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 | ||
265 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 | ||
266 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 | ||
267 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 | ||
268 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 | ||
269 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 | ||
270 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 | ||
271 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 | ||
272 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 | ||
273 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 | ||
274 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 | ||
275 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 | ||
276 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 | ||
277 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 | ||
278 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 | ||
279 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 | ||
280 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 | ||
281 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 | ||
282 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 | ||
283 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 | ||
284 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 | ||
285 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 | ||
286 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 | ||
287 | #define reg_iop_sw_mpu_rw_cpu_intr_offset 76 | ||
288 | |||
289 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
290 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 | ||
291 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 | ||
292 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 | ||
293 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 | ||
294 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 | ||
295 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 | ||
296 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 | ||
297 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 | ||
298 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 | ||
299 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 | ||
300 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 | ||
301 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 | ||
302 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 | ||
303 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 | ||
304 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 | ||
305 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 | ||
306 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 | ||
307 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 | ||
308 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 | ||
309 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 | ||
310 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 | ||
311 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 | ||
312 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 | ||
313 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 | ||
314 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 | ||
315 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 | ||
316 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 | ||
317 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 | ||
318 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 | ||
319 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 | ||
320 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 | ||
321 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 | ||
322 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 | ||
323 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 | ||
324 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 | ||
325 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 | ||
326 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 | ||
327 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 | ||
328 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 | ||
329 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 | ||
330 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 | ||
331 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 | ||
332 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 | ||
333 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 | ||
334 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 | ||
335 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 | ||
336 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 | ||
337 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 | ||
338 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 | ||
339 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 | ||
340 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 | ||
341 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 | ||
342 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 | ||
343 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 | ||
344 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 | ||
345 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 | ||
346 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 | ||
347 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 | ||
348 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 | ||
349 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 | ||
350 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 | ||
351 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 | ||
352 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 | ||
353 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 | ||
354 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 | ||
355 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 | ||
356 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 | ||
357 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 | ||
358 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 | ||
359 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 | ||
360 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 | ||
361 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 | ||
362 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 | ||
363 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 | ||
364 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 | ||
365 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 | ||
366 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 | ||
367 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 | ||
368 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 | ||
369 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 | ||
370 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 | ||
371 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 | ||
372 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 | ||
373 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 | ||
374 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 | ||
375 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 | ||
376 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 | ||
377 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 | ||
378 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 | ||
379 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 | ||
380 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 | ||
381 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 | ||
382 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 | ||
383 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 | ||
384 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 | ||
385 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 | ||
386 | #define reg_iop_sw_mpu_r_cpu_intr_offset 80 | ||
387 | |||
388 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
389 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 | ||
390 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 | ||
391 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 | ||
392 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 | ||
393 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 | ||
394 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 | ||
395 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 | ||
396 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 | ||
397 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 | ||
398 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 | ||
399 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 | ||
400 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 | ||
401 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 | ||
402 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 | ||
403 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 | ||
404 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 | ||
405 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 | ||
406 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 | ||
407 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 | ||
408 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 | ||
409 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 | ||
410 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 | ||
411 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 | ||
412 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 | ||
413 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 | ||
414 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 | ||
415 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 | ||
416 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 | ||
417 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 | ||
418 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 | ||
419 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 | ||
420 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 | ||
421 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 | ||
422 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 | ||
423 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 | ||
424 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 | ||
425 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 | ||
426 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 | ||
427 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 | ||
428 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 | ||
429 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 | ||
430 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 | ||
431 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 | ||
432 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 | ||
433 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 | ||
434 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 | ||
435 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 | ||
436 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 | ||
437 | #define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 | ||
438 | |||
439 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
440 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 | ||
441 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 | ||
442 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 | ||
443 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 | ||
444 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 | ||
445 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 | ||
446 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 | ||
447 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 | ||
448 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 | ||
449 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 | ||
450 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 | ||
451 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 | ||
452 | #define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 | ||
453 | |||
454 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
455 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 | ||
456 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 | ||
457 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 | ||
458 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 | ||
459 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 | ||
460 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 | ||
461 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 | ||
462 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 | ||
463 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 | ||
464 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 | ||
465 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 | ||
466 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 | ||
467 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 | ||
468 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 | ||
469 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 | ||
470 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 | ||
471 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 | ||
472 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 | ||
473 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 | ||
474 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 | ||
475 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 | ||
476 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 | ||
477 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 | ||
478 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 | ||
479 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 | ||
480 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 | ||
481 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 | ||
482 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 | ||
483 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 | ||
484 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 | ||
485 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 | ||
486 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 | ||
487 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 | ||
488 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 | ||
489 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 | ||
490 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 | ||
491 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 | ||
492 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 | ||
493 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 | ||
494 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 | ||
495 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 | ||
496 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 | ||
497 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 | ||
498 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 | ||
499 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 | ||
500 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 | ||
501 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 | ||
502 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 | ||
503 | #define reg_iop_sw_mpu_r_intr_grp0_offset 92 | ||
504 | |||
505 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
506 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 | ||
507 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 | ||
508 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 | ||
509 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 | ||
510 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 | ||
511 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 | ||
512 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 | ||
513 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 | ||
514 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 | ||
515 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 | ||
516 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 | ||
517 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 | ||
518 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 | ||
519 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 | ||
520 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 | ||
521 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 | ||
522 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 | ||
523 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 | ||
524 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 | ||
525 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 | ||
526 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 | ||
527 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 | ||
528 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 | ||
529 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 | ||
530 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 | ||
531 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 | ||
532 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 | ||
533 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 | ||
534 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 | ||
535 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 | ||
536 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 | ||
537 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 | ||
538 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 | ||
539 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 | ||
540 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 | ||
541 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 | ||
542 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 | ||
543 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 | ||
544 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 | ||
545 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 | ||
546 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 | ||
547 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 | ||
548 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 | ||
549 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 | ||
550 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 | ||
551 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 | ||
552 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 | ||
553 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 | ||
554 | #define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 | ||
555 | |||
556 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
557 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 | ||
558 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 | ||
559 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 | ||
560 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 | ||
561 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 | ||
562 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 | ||
563 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 | ||
564 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 | ||
565 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 | ||
566 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 | ||
567 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 | ||
568 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 | ||
569 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 | ||
570 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 | ||
571 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 | ||
572 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 | ||
573 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 | ||
574 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 | ||
575 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 | ||
576 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 | ||
577 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 | ||
578 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 | ||
579 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 | ||
580 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 | ||
581 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 | ||
582 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 | ||
583 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 | ||
584 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 | ||
585 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 | ||
586 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 | ||
587 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 | ||
588 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 | ||
589 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 | ||
590 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 | ||
591 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 | ||
592 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 | ||
593 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 | ||
594 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 | ||
595 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 | ||
596 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 | ||
597 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 | ||
598 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 | ||
599 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 | ||
600 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 | ||
601 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 | ||
602 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 | ||
603 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 | ||
604 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 | ||
605 | #define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 | ||
606 | |||
607 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
608 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 | ||
609 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 | ||
610 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 | ||
611 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 | ||
612 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 | ||
613 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 | ||
614 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 | ||
615 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 | ||
616 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 | ||
617 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 | ||
618 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 | ||
619 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 | ||
620 | #define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 | ||
621 | |||
622 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
623 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 | ||
624 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 | ||
625 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 | ||
626 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 | ||
627 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 | ||
628 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 | ||
629 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 | ||
630 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 | ||
631 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 | ||
632 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 | ||
633 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 | ||
634 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 | ||
635 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 | ||
636 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 | ||
637 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 | ||
638 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 | ||
639 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 | ||
640 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 | ||
641 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 | ||
642 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 | ||
643 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 | ||
644 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 | ||
645 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 | ||
646 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 | ||
647 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 | ||
648 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 | ||
649 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 | ||
650 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 | ||
651 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 | ||
652 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 | ||
653 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 | ||
654 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 | ||
655 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 | ||
656 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 | ||
657 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 | ||
658 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 | ||
659 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 | ||
660 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 | ||
661 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 | ||
662 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 | ||
663 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 | ||
664 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 | ||
665 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 | ||
666 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 | ||
667 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 | ||
668 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 | ||
669 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 | ||
670 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 | ||
671 | #define reg_iop_sw_mpu_r_intr_grp1_offset 108 | ||
672 | |||
673 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
674 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 | ||
675 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 | ||
676 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 | ||
677 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 | ||
678 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 | ||
679 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 | ||
680 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 | ||
681 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 | ||
682 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 | ||
683 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 | ||
684 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 | ||
685 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 | ||
686 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 | ||
687 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 | ||
688 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 | ||
689 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 | ||
690 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 | ||
691 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 | ||
692 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 | ||
693 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 | ||
694 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 | ||
695 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 | ||
696 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 | ||
697 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 | ||
698 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 | ||
699 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 | ||
700 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 | ||
701 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 | ||
702 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 | ||
703 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 | ||
704 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 | ||
705 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 | ||
706 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 | ||
707 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 | ||
708 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 | ||
709 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 | ||
710 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 | ||
711 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 | ||
712 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 | ||
713 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 | ||
714 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 | ||
715 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 | ||
716 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 | ||
717 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 | ||
718 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 | ||
719 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 | ||
720 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 | ||
721 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 | ||
722 | #define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 | ||
723 | |||
724 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
725 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 | ||
726 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 | ||
727 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 | ||
728 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 | ||
729 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 | ||
730 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 | ||
731 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 | ||
732 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 | ||
733 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 | ||
734 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 | ||
735 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 | ||
736 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 | ||
737 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 | ||
738 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 | ||
739 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 | ||
740 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 | ||
741 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 | ||
742 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 | ||
743 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 | ||
744 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 | ||
745 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 | ||
746 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 | ||
747 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 | ||
748 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 | ||
749 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 | ||
750 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 | ||
751 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 | ||
752 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 | ||
753 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 | ||
754 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 | ||
755 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 | ||
756 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 | ||
757 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 | ||
758 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 | ||
759 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 | ||
760 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 | ||
761 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 | ||
762 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 | ||
763 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 | ||
764 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 | ||
765 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 | ||
766 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 | ||
767 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 | ||
768 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 | ||
769 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 | ||
770 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 | ||
771 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 | ||
772 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 | ||
773 | #define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 | ||
774 | |||
775 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
776 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 | ||
777 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 | ||
778 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 | ||
779 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 | ||
780 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 | ||
781 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 | ||
782 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 | ||
783 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 | ||
784 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 | ||
785 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 | ||
786 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 | ||
787 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 | ||
788 | #define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 | ||
789 | |||
790 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
791 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 | ||
792 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 | ||
793 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 | ||
794 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 | ||
795 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 | ||
796 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 | ||
797 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 | ||
798 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 | ||
799 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 | ||
800 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 | ||
801 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 | ||
802 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 | ||
803 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 | ||
804 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 | ||
805 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 | ||
806 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 | ||
807 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 | ||
808 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 | ||
809 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 | ||
810 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 | ||
811 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 | ||
812 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 | ||
813 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 | ||
814 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 | ||
815 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 | ||
816 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 | ||
817 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 | ||
818 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 | ||
819 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 | ||
820 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 | ||
821 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 | ||
822 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 | ||
823 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 | ||
824 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 | ||
825 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 | ||
826 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 | ||
827 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 | ||
828 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 | ||
829 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 | ||
830 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 | ||
831 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 | ||
832 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 | ||
833 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 | ||
834 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 | ||
835 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 | ||
836 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 | ||
837 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 | ||
838 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 | ||
839 | #define reg_iop_sw_mpu_r_intr_grp2_offset 124 | ||
840 | |||
841 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
842 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 | ||
843 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 | ||
844 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 | ||
845 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 | ||
846 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 | ||
847 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 | ||
848 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 | ||
849 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 | ||
850 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 | ||
851 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 | ||
852 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 | ||
853 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 | ||
854 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 | ||
855 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 | ||
856 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 | ||
857 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 | ||
858 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 | ||
859 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 | ||
860 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 | ||
861 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 | ||
862 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 | ||
863 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 | ||
864 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 | ||
865 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 | ||
866 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 | ||
867 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 | ||
868 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 | ||
869 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 | ||
870 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 | ||
871 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 | ||
872 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 | ||
873 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 | ||
874 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 | ||
875 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 | ||
876 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 | ||
877 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 | ||
878 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 | ||
879 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 | ||
880 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 | ||
881 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 | ||
882 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 | ||
883 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 | ||
884 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 | ||
885 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 | ||
886 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 | ||
887 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 | ||
888 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 | ||
889 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 | ||
890 | #define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 | ||
891 | |||
892 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
893 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 | ||
894 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 | ||
895 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 | ||
896 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 | ||
897 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 | ||
898 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 | ||
899 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 | ||
900 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 | ||
901 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 | ||
902 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 | ||
903 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 | ||
904 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 | ||
905 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 | ||
906 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 | ||
907 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 | ||
908 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 | ||
909 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 | ||
910 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 | ||
911 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 | ||
912 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 | ||
913 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 | ||
914 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 | ||
915 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 | ||
916 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 | ||
917 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 | ||
918 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 | ||
919 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 | ||
920 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 | ||
921 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 | ||
922 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 | ||
923 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 | ||
924 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 | ||
925 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 | ||
926 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 | ||
927 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 | ||
928 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 | ||
929 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 | ||
930 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 | ||
931 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 | ||
932 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 | ||
933 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 | ||
934 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 | ||
935 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 | ||
936 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 | ||
937 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 | ||
938 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 | ||
939 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 | ||
940 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 | ||
941 | #define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 | ||
942 | |||
943 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
944 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 | ||
945 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 | ||
946 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 | ||
947 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 | ||
948 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 | ||
949 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 | ||
950 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 | ||
951 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 | ||
952 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 | ||
953 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 | ||
954 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 | ||
955 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 | ||
956 | #define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 | ||
957 | |||
958 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
959 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 | ||
960 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 | ||
961 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 | ||
962 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 | ||
963 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 | ||
964 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 | ||
965 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 | ||
966 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 | ||
967 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 | ||
968 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 | ||
969 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 | ||
970 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 | ||
971 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 | ||
972 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 | ||
973 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 | ||
974 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 | ||
975 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 | ||
976 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 | ||
977 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 | ||
978 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 | ||
979 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 | ||
980 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 | ||
981 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 | ||
982 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 | ||
983 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 | ||
984 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 | ||
985 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 | ||
986 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 | ||
987 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 | ||
988 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 | ||
989 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 | ||
990 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 | ||
991 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 | ||
992 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 | ||
993 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 | ||
994 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 | ||
995 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 | ||
996 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 | ||
997 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 | ||
998 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 | ||
999 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 | ||
1000 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 | ||
1001 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 | ||
1002 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 | ||
1003 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 | ||
1004 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 | ||
1005 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 | ||
1006 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 | ||
1007 | #define reg_iop_sw_mpu_r_intr_grp3_offset 140 | ||
1008 | |||
1009 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
1010 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 | ||
1011 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 | ||
1012 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 | ||
1013 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 | ||
1014 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 | ||
1015 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 | ||
1016 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 | ||
1017 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 | ||
1018 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 | ||
1019 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 | ||
1020 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 | ||
1021 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 | ||
1022 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 | ||
1023 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 | ||
1024 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 | ||
1025 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 | ||
1026 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 | ||
1027 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 | ||
1028 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 | ||
1029 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 | ||
1030 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 | ||
1031 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 | ||
1032 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 | ||
1033 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 | ||
1034 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 | ||
1035 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 | ||
1036 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 | ||
1037 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 | ||
1038 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 | ||
1039 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 | ||
1040 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 | ||
1041 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 | ||
1042 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 | ||
1043 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 | ||
1044 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 | ||
1045 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 | ||
1046 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 | ||
1047 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 | ||
1048 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 | ||
1049 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 | ||
1050 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 | ||
1051 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 | ||
1052 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 | ||
1053 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 | ||
1054 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 | ||
1055 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 | ||
1056 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 | ||
1057 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 | ||
1058 | #define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 | ||
1059 | |||
1060 | |||
1061 | /* Constants */ | ||
1062 | #define regk_iop_sw_mpu_copy 0x00000000 | ||
1063 | #define regk_iop_sw_mpu_cpu 0x00000000 | ||
1064 | #define regk_iop_sw_mpu_mpu 0x00000001 | ||
1065 | #define regk_iop_sw_mpu_no 0x00000000 | ||
1066 | #define regk_iop_sw_mpu_nop 0x00000000 | ||
1067 | #define regk_iop_sw_mpu_rd 0x00000002 | ||
1068 | #define regk_iop_sw_mpu_reg_copy 0x00000001 | ||
1069 | #define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 | ||
1070 | #define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
1071 | #define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 | ||
1072 | #define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 | ||
1073 | #define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 | ||
1074 | #define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
1075 | #define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 | ||
1076 | #define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 | ||
1077 | #define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 | ||
1078 | #define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 | ||
1079 | #define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 | ||
1080 | #define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 | ||
1081 | #define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 | ||
1082 | #define regk_iop_sw_mpu_set 0x00000001 | ||
1083 | #define regk_iop_sw_mpu_spu 0x00000002 | ||
1084 | #define regk_iop_sw_mpu_wr 0x00000003 | ||
1085 | #define regk_iop_sw_mpu_yes 0x00000001 | ||
1086 | #endif /* __iop_sw_mpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 00000000000..67a74533808 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h | |||
@@ -0,0 +1,523 @@ | |||
1 | #ifndef __iop_sw_spu_defs_asm_h | ||
2 | #define __iop_sw_spu_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_spu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
54 | #define reg_iop_sw_spu_r_mpu_trace_offset 0 | ||
55 | |||
56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 | ||
58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 | ||
59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 | ||
60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 | ||
61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 | ||
62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 | ||
63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 | ||
64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
67 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 4 | ||
68 | |||
69 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
70 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 | ||
71 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 | ||
72 | #define reg_iop_sw_spu_rw_mc_data_offset 8 | ||
73 | |||
74 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
75 | #define reg_iop_sw_spu_rw_mc_addr_offset 12 | ||
76 | |||
77 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
78 | #define reg_iop_sw_spu_rs_mc_data_offset 16 | ||
79 | |||
80 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
81 | #define reg_iop_sw_spu_r_mc_data_offset 20 | ||
82 | |||
83 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
84 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 | ||
85 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 | ||
86 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 | ||
87 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 | ||
88 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 | ||
89 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 | ||
90 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 | ||
91 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 | ||
92 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 | ||
93 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 | ||
94 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 | ||
95 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 | ||
96 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 | ||
97 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 | ||
98 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 | ||
99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 | ||
100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 | ||
101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 | ||
102 | #define reg_iop_sw_spu_r_mc_stat_offset 24 | ||
103 | |||
104 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
105 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 | ||
106 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 | ||
107 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 | ||
108 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 | ||
109 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 | ||
110 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 | ||
111 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 | ||
112 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 | ||
113 | #define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 | ||
114 | |||
115 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
116 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 | ||
117 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 | ||
118 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 | ||
119 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 | ||
120 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 | ||
121 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 | ||
122 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 | ||
123 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 | ||
124 | #define reg_iop_sw_spu_rw_bus_set_mask_offset 32 | ||
125 | |||
126 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
127 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
128 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 | ||
129 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
130 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
131 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 | ||
132 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
133 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
134 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 | ||
135 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
136 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
137 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 | ||
138 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
139 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 | ||
140 | |||
141 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
142 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
143 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 | ||
144 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 | ||
145 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
146 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 | ||
147 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 | ||
148 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
149 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 | ||
150 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 | ||
151 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
152 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 | ||
153 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 | ||
154 | #define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 | ||
155 | |||
156 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
157 | #define reg_iop_sw_spu_r_bus_in_offset 44 | ||
158 | |||
159 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
160 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 | ||
161 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 | ||
162 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 | ||
163 | |||
164 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
165 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 | ||
166 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 | ||
167 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 52 | ||
168 | |||
169 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
170 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 | ||
171 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 | ||
172 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 | ||
173 | |||
174 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
175 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 | ||
176 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 | ||
177 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 | ||
178 | |||
179 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
180 | #define reg_iop_sw_spu_r_gio_in_offset 64 | ||
181 | |||
182 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
183 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 | ||
184 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 | ||
185 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 | ||
186 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 | ||
187 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 | ||
188 | |||
189 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
190 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 | ||
191 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 | ||
192 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 | ||
193 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 | ||
194 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 | ||
195 | |||
196 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
197 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 | ||
198 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 | ||
199 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 | ||
200 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 | ||
201 | #define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 | ||
202 | |||
203 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
204 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 | ||
205 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 | ||
206 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 | ||
207 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 | ||
208 | #define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 | ||
209 | |||
210 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
211 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 | ||
212 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 | ||
213 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 | ||
214 | |||
215 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
216 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 | ||
217 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 | ||
218 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 | ||
219 | |||
220 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
221 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 | ||
222 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 | ||
223 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 | ||
224 | |||
225 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
226 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 | ||
227 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 | ||
228 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 | ||
229 | |||
230 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
231 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 | ||
232 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 | ||
233 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 | ||
234 | |||
235 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 | ||
237 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 | ||
238 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 | ||
239 | |||
240 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 | ||
242 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 | ||
243 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 | ||
244 | |||
245 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
246 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 | ||
247 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 | ||
248 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 | ||
249 | |||
250 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
251 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 | ||
252 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 | ||
253 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 | ||
254 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 | ||
255 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 | ||
256 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 | ||
257 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 | ||
258 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 | ||
259 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 | ||
260 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 | ||
261 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 | ||
262 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 | ||
263 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 | ||
264 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 | ||
265 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 | ||
266 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 | ||
267 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 | ||
268 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 | ||
269 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 | ||
270 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 | ||
271 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 | ||
272 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 | ||
273 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 | ||
274 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 | ||
275 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 | ||
276 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 | ||
277 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 | ||
278 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 | ||
279 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 | ||
280 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 | ||
281 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 | ||
282 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 | ||
283 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 | ||
284 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 | ||
285 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 | ||
286 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 | ||
287 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 | ||
288 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 | ||
289 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 | ||
290 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 | ||
291 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 | ||
292 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 | ||
293 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 | ||
294 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 | ||
295 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 | ||
296 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 | ||
297 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 | ||
298 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 | ||
299 | #define reg_iop_sw_spu_rw_cpu_intr_offset 116 | ||
300 | |||
301 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
302 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 | ||
303 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 | ||
304 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 | ||
305 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 | ||
306 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 | ||
307 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 | ||
308 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 | ||
309 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 | ||
310 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 | ||
311 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 | ||
312 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 | ||
313 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 | ||
314 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 | ||
315 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 | ||
316 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 | ||
317 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 | ||
318 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 | ||
319 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 | ||
320 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 | ||
321 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 | ||
322 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 | ||
323 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 | ||
324 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 | ||
325 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 | ||
326 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 | ||
327 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 | ||
328 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 | ||
329 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 | ||
330 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 | ||
331 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 | ||
332 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 | ||
333 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 | ||
334 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 | ||
335 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 | ||
336 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 | ||
337 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 | ||
338 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 | ||
339 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 | ||
340 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 | ||
341 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 | ||
342 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 | ||
343 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 | ||
344 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 | ||
345 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 | ||
346 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 | ||
347 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 | ||
348 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 | ||
349 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 | ||
350 | #define reg_iop_sw_spu_r_cpu_intr_offset 120 | ||
351 | |||
352 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
353 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 | ||
354 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 | ||
355 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 | ||
356 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 | ||
357 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 | ||
358 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 | ||
359 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 | ||
360 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 | ||
361 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 | ||
362 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 | ||
363 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 | ||
364 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 | ||
365 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 | ||
366 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 | ||
367 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 | ||
368 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 | ||
369 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 | ||
370 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 | ||
371 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 | ||
372 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 | ||
373 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 | ||
374 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 | ||
375 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 | ||
376 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 | ||
377 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 | ||
378 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 | ||
379 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 | ||
380 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 | ||
381 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 | ||
382 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 | ||
383 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 | ||
384 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 | ||
385 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 | ||
386 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 | ||
387 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 | ||
388 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 | ||
389 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 | ||
390 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 | ||
391 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 | ||
392 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 | ||
393 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 | ||
394 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 | ||
395 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 | ||
396 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 | ||
397 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 | ||
398 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 | ||
399 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 | ||
400 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 | ||
401 | #define reg_iop_sw_spu_r_hw_intr_offset 124 | ||
402 | |||
403 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
404 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 | ||
405 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 | ||
406 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 | ||
407 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 | ||
408 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 | ||
409 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 | ||
410 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 | ||
411 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 | ||
412 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 | ||
413 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 | ||
414 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 | ||
415 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 | ||
416 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 | ||
417 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 | ||
418 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 | ||
419 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 | ||
420 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 | ||
421 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 | ||
422 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 | ||
423 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 | ||
424 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 | ||
425 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 | ||
426 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 | ||
427 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 | ||
428 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 | ||
429 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 | ||
430 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 | ||
431 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 | ||
432 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 | ||
433 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 | ||
434 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 | ||
435 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 | ||
436 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 | ||
437 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 | ||
438 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 | ||
439 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 | ||
440 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 | ||
441 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 | ||
442 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 | ||
443 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 | ||
444 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 | ||
445 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 | ||
446 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 | ||
447 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 | ||
448 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 | ||
449 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 | ||
450 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 | ||
451 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 | ||
452 | #define reg_iop_sw_spu_rw_mpu_intr_offset 128 | ||
453 | |||
454 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
455 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 | ||
456 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 | ||
457 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 | ||
458 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 | ||
459 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 | ||
460 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 | ||
461 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 | ||
462 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 | ||
463 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 | ||
464 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 | ||
465 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 | ||
466 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 | ||
467 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 | ||
468 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 | ||
469 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 | ||
470 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 | ||
471 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 | ||
472 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 | ||
473 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 | ||
474 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 | ||
475 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 | ||
476 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 | ||
477 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 | ||
478 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 | ||
479 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 | ||
480 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 | ||
481 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 | ||
482 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 | ||
483 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 | ||
484 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 | ||
485 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 | ||
486 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 | ||
487 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 | ||
488 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 | ||
489 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 | ||
490 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 | ||
491 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 | ||
492 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 | ||
493 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 | ||
494 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 | ||
495 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 | ||
496 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 | ||
497 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 | ||
498 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 | ||
499 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 | ||
500 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 | ||
501 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 | ||
502 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 | ||
503 | #define reg_iop_sw_spu_r_mpu_intr_offset 132 | ||
504 | |||
505 | |||
506 | /* Constants */ | ||
507 | #define regk_iop_sw_spu_copy 0x00000000 | ||
508 | #define regk_iop_sw_spu_no 0x00000000 | ||
509 | #define regk_iop_sw_spu_nop 0x00000000 | ||
510 | #define regk_iop_sw_spu_rd 0x00000002 | ||
511 | #define regk_iop_sw_spu_reg_copy 0x00000001 | ||
512 | #define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 | ||
513 | #define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 | ||
514 | #define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 | ||
515 | #define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 | ||
516 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 | ||
517 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 | ||
518 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 | ||
519 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 | ||
520 | #define regk_iop_sw_spu_set 0x00000001 | ||
521 | #define regk_iop_sw_spu_wr 0x00000003 | ||
522 | #define regk_iop_sw_spu_yes 0x00000001 | ||
523 | #endif /* __iop_sw_spu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 00000000000..4ad671202af --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h | |||
@@ -0,0 +1,61 @@ | |||
1 | #ifndef __iop_version_defs_asm_h | ||
2 | #define __iop_version_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_version.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register r_version, scope iop_version, type r */ | ||
54 | #define reg_iop_version_r_version___nr___lsb 0 | ||
55 | #define reg_iop_version_r_version___nr___width 8 | ||
56 | #define reg_iop_version_r_version_offset 0 | ||
57 | |||
58 | |||
59 | /* Constants */ | ||
60 | #define regk_iop_version_v2_0 0x00000002 | ||
61 | #endif /* __iop_version_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h new file mode 100644 index 00000000000..af3196c60a4 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* Autogenerated Changes here will be lost! | ||
2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
3 | */ | ||
4 | #define regi_iop_version (regi_iop + 0) | ||
5 | #define regi_iop_fifo_in_extra (regi_iop + 64) | ||
6 | #define regi_iop_fifo_out_extra (regi_iop + 128) | ||
7 | #define regi_iop_trigger_grp0 (regi_iop + 192) | ||
8 | #define regi_iop_trigger_grp1 (regi_iop + 256) | ||
9 | #define regi_iop_trigger_grp2 (regi_iop + 320) | ||
10 | #define regi_iop_trigger_grp3 (regi_iop + 384) | ||
11 | #define regi_iop_trigger_grp4 (regi_iop + 448) | ||
12 | #define regi_iop_trigger_grp5 (regi_iop + 512) | ||
13 | #define regi_iop_trigger_grp6 (regi_iop + 576) | ||
14 | #define regi_iop_trigger_grp7 (regi_iop + 640) | ||
15 | #define regi_iop_crc_par (regi_iop + 768) | ||
16 | #define regi_iop_dmc_in (regi_iop + 896) | ||
17 | #define regi_iop_dmc_out (regi_iop + 1024) | ||
18 | #define regi_iop_fifo_in (regi_iop + 1152) | ||
19 | #define regi_iop_fifo_out (regi_iop + 1280) | ||
20 | #define regi_iop_scrc_in (regi_iop + 1408) | ||
21 | #define regi_iop_scrc_out (regi_iop + 1536) | ||
22 | #define regi_iop_timer_grp0 (regi_iop + 1664) | ||
23 | #define regi_iop_timer_grp1 (regi_iop + 1792) | ||
24 | #define regi_iop_sap_in (regi_iop + 2048) | ||
25 | #define regi_iop_sap_out (regi_iop + 2304) | ||
26 | #define regi_iop_spu (regi_iop + 2560) | ||
27 | #define regi_iop_sw_cfg (regi_iop + 2816) | ||
28 | #define regi_iop_sw_cpu (regi_iop + 3072) | ||
29 | #define regi_iop_sw_mpu (regi_iop + 3328) | ||
30 | #define regi_iop_sw_spu (regi_iop + 3584) | ||
31 | #define regi_iop_mpu (regi_iop + 4096) | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 00000000000..51dde016c03 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h | |||
@@ -0,0 +1,141 @@ | |||
1 | #ifndef __iop_sap_in_defs_h | ||
2 | #define __iop_sap_in_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sap_in.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sap_in */ | ||
83 | |||
84 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
85 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
86 | typedef struct { | ||
87 | unsigned int sync_sel : 2; | ||
88 | unsigned int sync_ext_src : 3; | ||
89 | unsigned int sync_edge : 2; | ||
90 | unsigned int delay : 2; | ||
91 | unsigned int dummy1 : 23; | ||
92 | } reg_iop_sap_in_rw_bus_byte; | ||
93 | #define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 | ||
94 | #define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 | ||
95 | |||
96 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
97 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
98 | typedef struct { | ||
99 | unsigned int sync_sel : 2; | ||
100 | unsigned int sync_ext_src : 3; | ||
101 | unsigned int sync_edge : 2; | ||
102 | unsigned int delay : 2; | ||
103 | unsigned int logic : 2; | ||
104 | unsigned int dummy1 : 21; | ||
105 | } reg_iop_sap_in_rw_gio; | ||
106 | #define REG_RD_ADDR_iop_sap_in_rw_gio 16 | ||
107 | #define REG_WR_ADDR_iop_sap_in_rw_gio 16 | ||
108 | |||
109 | |||
110 | /* Constants */ | ||
111 | enum { | ||
112 | regk_iop_sap_in_and = 0x00000002, | ||
113 | regk_iop_sap_in_ext_clk200 = 0x00000003, | ||
114 | regk_iop_sap_in_gio0 = 0x00000000, | ||
115 | regk_iop_sap_in_gio12 = 0x00000003, | ||
116 | regk_iop_sap_in_gio16 = 0x00000004, | ||
117 | regk_iop_sap_in_gio20 = 0x00000005, | ||
118 | regk_iop_sap_in_gio24 = 0x00000006, | ||
119 | regk_iop_sap_in_gio28 = 0x00000007, | ||
120 | regk_iop_sap_in_gio4 = 0x00000001, | ||
121 | regk_iop_sap_in_gio8 = 0x00000002, | ||
122 | regk_iop_sap_in_inv = 0x00000001, | ||
123 | regk_iop_sap_in_neg = 0x00000002, | ||
124 | regk_iop_sap_in_no = 0x00000000, | ||
125 | regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, | ||
126 | regk_iop_sap_in_none = 0x00000000, | ||
127 | regk_iop_sap_in_one = 0x00000001, | ||
128 | regk_iop_sap_in_or = 0x00000003, | ||
129 | regk_iop_sap_in_pos = 0x00000001, | ||
130 | regk_iop_sap_in_pos_neg = 0x00000003, | ||
131 | regk_iop_sap_in_rw_bus_byte_default = 0x00000000, | ||
132 | regk_iop_sap_in_rw_bus_byte_size = 0x00000004, | ||
133 | regk_iop_sap_in_rw_gio_default = 0x00000000, | ||
134 | regk_iop_sap_in_rw_gio_size = 0x00000020, | ||
135 | regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, | ||
136 | regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, | ||
137 | regk_iop_sap_in_tmr_clk200 = 0x00000001, | ||
138 | regk_iop_sap_in_two = 0x00000002, | ||
139 | regk_iop_sap_in_two_clk200 = 0x00000000 | ||
140 | }; | ||
141 | #endif /* __iop_sap_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 00000000000..5af88baa2ac --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h | |||
@@ -0,0 +1,231 @@ | |||
1 | #ifndef __iop_sap_out_defs_h | ||
2 | #define __iop_sap_out_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sap_out.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sap_out */ | ||
83 | |||
84 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
85 | typedef struct { | ||
86 | unsigned int clk0_src : 2; | ||
87 | unsigned int clk0_gate_src : 2; | ||
88 | unsigned int clk0_force_src : 3; | ||
89 | unsigned int clk1_src : 2; | ||
90 | unsigned int clk1_gate_src : 2; | ||
91 | unsigned int clk1_force_src : 3; | ||
92 | unsigned int dummy1 : 18; | ||
93 | } reg_iop_sap_out_rw_gen_gated; | ||
94 | #define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 | ||
95 | #define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 | ||
96 | |||
97 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
98 | typedef struct { | ||
99 | unsigned int byte0_clk_sel : 2; | ||
100 | unsigned int byte0_clk_ext : 2; | ||
101 | unsigned int byte0_gated_clk : 1; | ||
102 | unsigned int byte0_clk_inv : 1; | ||
103 | unsigned int byte0_delay : 1; | ||
104 | unsigned int byte1_clk_sel : 2; | ||
105 | unsigned int byte1_clk_ext : 2; | ||
106 | unsigned int byte1_gated_clk : 1; | ||
107 | unsigned int byte1_clk_inv : 1; | ||
108 | unsigned int byte1_delay : 1; | ||
109 | unsigned int byte2_clk_sel : 2; | ||
110 | unsigned int byte2_clk_ext : 2; | ||
111 | unsigned int byte2_gated_clk : 1; | ||
112 | unsigned int byte2_clk_inv : 1; | ||
113 | unsigned int byte2_delay : 1; | ||
114 | unsigned int byte3_clk_sel : 2; | ||
115 | unsigned int byte3_clk_ext : 2; | ||
116 | unsigned int byte3_gated_clk : 1; | ||
117 | unsigned int byte3_clk_inv : 1; | ||
118 | unsigned int byte3_delay : 1; | ||
119 | unsigned int dummy1 : 4; | ||
120 | } reg_iop_sap_out_rw_bus; | ||
121 | #define REG_RD_ADDR_iop_sap_out_rw_bus 4 | ||
122 | #define REG_WR_ADDR_iop_sap_out_rw_bus 4 | ||
123 | |||
124 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
125 | typedef struct { | ||
126 | unsigned int byte0_clk_sel : 2; | ||
127 | unsigned int byte0_clk_ext : 2; | ||
128 | unsigned int byte0_gated_clk : 1; | ||
129 | unsigned int byte0_clk_inv : 1; | ||
130 | unsigned int byte0_delay : 1; | ||
131 | unsigned int byte0_logic : 2; | ||
132 | unsigned int byte0_logic_src : 2; | ||
133 | unsigned int byte1_clk_sel : 2; | ||
134 | unsigned int byte1_clk_ext : 2; | ||
135 | unsigned int byte1_gated_clk : 1; | ||
136 | unsigned int byte1_clk_inv : 1; | ||
137 | unsigned int byte1_delay : 1; | ||
138 | unsigned int byte1_logic : 2; | ||
139 | unsigned int byte1_logic_src : 2; | ||
140 | unsigned int dummy1 : 10; | ||
141 | } reg_iop_sap_out_rw_bus_lo_oe; | ||
142 | #define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
143 | #define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
144 | |||
145 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
146 | typedef struct { | ||
147 | unsigned int byte2_clk_sel : 2; | ||
148 | unsigned int byte2_clk_ext : 2; | ||
149 | unsigned int byte2_gated_clk : 1; | ||
150 | unsigned int byte2_clk_inv : 1; | ||
151 | unsigned int byte2_delay : 1; | ||
152 | unsigned int byte2_logic : 2; | ||
153 | unsigned int byte2_logic_src : 2; | ||
154 | unsigned int byte3_clk_sel : 2; | ||
155 | unsigned int byte3_clk_ext : 2; | ||
156 | unsigned int byte3_gated_clk : 1; | ||
157 | unsigned int byte3_clk_inv : 1; | ||
158 | unsigned int byte3_delay : 1; | ||
159 | unsigned int byte3_logic : 2; | ||
160 | unsigned int byte3_logic_src : 2; | ||
161 | unsigned int dummy1 : 10; | ||
162 | } reg_iop_sap_out_rw_bus_hi_oe; | ||
163 | #define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
164 | #define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
165 | |||
166 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
167 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
168 | typedef struct { | ||
169 | unsigned int out_clk_sel : 3; | ||
170 | unsigned int out_clk_ext : 2; | ||
171 | unsigned int out_gated_clk : 1; | ||
172 | unsigned int out_clk_inv : 1; | ||
173 | unsigned int out_delay : 1; | ||
174 | unsigned int out_logic : 2; | ||
175 | unsigned int out_logic_src : 2; | ||
176 | unsigned int oe_clk_sel : 3; | ||
177 | unsigned int oe_clk_ext : 2; | ||
178 | unsigned int oe_gated_clk : 1; | ||
179 | unsigned int oe_clk_inv : 1; | ||
180 | unsigned int oe_delay : 1; | ||
181 | unsigned int oe_logic : 2; | ||
182 | unsigned int oe_logic_src : 2; | ||
183 | unsigned int dummy1 : 8; | ||
184 | } reg_iop_sap_out_rw_gio; | ||
185 | #define REG_RD_ADDR_iop_sap_out_rw_gio 16 | ||
186 | #define REG_WR_ADDR_iop_sap_out_rw_gio 16 | ||
187 | |||
188 | |||
189 | /* Constants */ | ||
190 | enum { | ||
191 | regk_iop_sap_out_always = 0x00000001, | ||
192 | regk_iop_sap_out_and = 0x00000002, | ||
193 | regk_iop_sap_out_clk0 = 0x00000000, | ||
194 | regk_iop_sap_out_clk1 = 0x00000001, | ||
195 | regk_iop_sap_out_clk12 = 0x00000004, | ||
196 | regk_iop_sap_out_clk200 = 0x00000000, | ||
197 | regk_iop_sap_out_ext = 0x00000002, | ||
198 | regk_iop_sap_out_gated = 0x00000003, | ||
199 | regk_iop_sap_out_gio0 = 0x00000000, | ||
200 | regk_iop_sap_out_gio1 = 0x00000000, | ||
201 | regk_iop_sap_out_gio16 = 0x00000002, | ||
202 | regk_iop_sap_out_gio17 = 0x00000002, | ||
203 | regk_iop_sap_out_gio24 = 0x00000003, | ||
204 | regk_iop_sap_out_gio25 = 0x00000003, | ||
205 | regk_iop_sap_out_gio8 = 0x00000001, | ||
206 | regk_iop_sap_out_gio9 = 0x00000001, | ||
207 | regk_iop_sap_out_gio_out10 = 0x00000005, | ||
208 | regk_iop_sap_out_gio_out18 = 0x00000006, | ||
209 | regk_iop_sap_out_gio_out2 = 0x00000004, | ||
210 | regk_iop_sap_out_gio_out26 = 0x00000007, | ||
211 | regk_iop_sap_out_inv = 0x00000001, | ||
212 | regk_iop_sap_out_nand = 0x00000003, | ||
213 | regk_iop_sap_out_no = 0x00000000, | ||
214 | regk_iop_sap_out_none = 0x00000000, | ||
215 | regk_iop_sap_out_one = 0x00000001, | ||
216 | regk_iop_sap_out_rw_bus_default = 0x00000000, | ||
217 | regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, | ||
218 | regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, | ||
219 | regk_iop_sap_out_rw_gen_gated_default = 0x00000000, | ||
220 | regk_iop_sap_out_rw_gio_default = 0x00000000, | ||
221 | regk_iop_sap_out_rw_gio_size = 0x00000020, | ||
222 | regk_iop_sap_out_spu_gio6 = 0x00000002, | ||
223 | regk_iop_sap_out_spu_gio7 = 0x00000003, | ||
224 | regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, | ||
225 | regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, | ||
226 | regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, | ||
227 | regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, | ||
228 | regk_iop_sap_out_tmr200 = 0x00000001, | ||
229 | regk_iop_sap_out_yes = 0x00000001 | ||
230 | }; | ||
231 | #endif /* __iop_sap_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 00000000000..98ac95275a1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h | |||
@@ -0,0 +1,725 @@ | |||
1 | #ifndef __iop_sw_cfg_defs_h | ||
2 | #define __iop_sw_cfg_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_cfg.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sw_cfg */ | ||
83 | |||
84 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
85 | typedef struct { | ||
86 | unsigned int cfg : 2; | ||
87 | unsigned int dummy1 : 30; | ||
88 | } reg_iop_sw_cfg_rw_crc_par_owner; | ||
89 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
90 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
91 | |||
92 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
93 | typedef struct { | ||
94 | unsigned int cfg : 2; | ||
95 | unsigned int dummy1 : 30; | ||
96 | } reg_iop_sw_cfg_rw_dmc_in_owner; | ||
97 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
98 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
99 | |||
100 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
101 | typedef struct { | ||
102 | unsigned int cfg : 2; | ||
103 | unsigned int dummy1 : 30; | ||
104 | } reg_iop_sw_cfg_rw_dmc_out_owner; | ||
105 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
106 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
107 | |||
108 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
109 | typedef struct { | ||
110 | unsigned int cfg : 2; | ||
111 | unsigned int dummy1 : 30; | ||
112 | } reg_iop_sw_cfg_rw_fifo_in_owner; | ||
113 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
114 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
115 | |||
116 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
117 | typedef struct { | ||
118 | unsigned int cfg : 2; | ||
119 | unsigned int dummy1 : 30; | ||
120 | } reg_iop_sw_cfg_rw_fifo_in_extra_owner; | ||
121 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
122 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
123 | |||
124 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
125 | typedef struct { | ||
126 | unsigned int cfg : 2; | ||
127 | unsigned int dummy1 : 30; | ||
128 | } reg_iop_sw_cfg_rw_fifo_out_owner; | ||
129 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
130 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
131 | |||
132 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
133 | typedef struct { | ||
134 | unsigned int cfg : 2; | ||
135 | unsigned int dummy1 : 30; | ||
136 | } reg_iop_sw_cfg_rw_fifo_out_extra_owner; | ||
137 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
138 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
139 | |||
140 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
141 | typedef struct { | ||
142 | unsigned int cfg : 2; | ||
143 | unsigned int dummy1 : 30; | ||
144 | } reg_iop_sw_cfg_rw_sap_in_owner; | ||
145 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
146 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
147 | |||
148 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
149 | typedef struct { | ||
150 | unsigned int cfg : 2; | ||
151 | unsigned int dummy1 : 30; | ||
152 | } reg_iop_sw_cfg_rw_sap_out_owner; | ||
153 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
154 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
155 | |||
156 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
157 | typedef struct { | ||
158 | unsigned int cfg : 2; | ||
159 | unsigned int dummy1 : 30; | ||
160 | } reg_iop_sw_cfg_rw_scrc_in_owner; | ||
161 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
162 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
163 | |||
164 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
165 | typedef struct { | ||
166 | unsigned int cfg : 2; | ||
167 | unsigned int dummy1 : 30; | ||
168 | } reg_iop_sw_cfg_rw_scrc_out_owner; | ||
169 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
170 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
171 | |||
172 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
173 | typedef struct { | ||
174 | unsigned int cfg : 1; | ||
175 | unsigned int dummy1 : 31; | ||
176 | } reg_iop_sw_cfg_rw_spu_owner; | ||
177 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
178 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
179 | |||
180 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
181 | typedef struct { | ||
182 | unsigned int cfg : 2; | ||
183 | unsigned int dummy1 : 30; | ||
184 | } reg_iop_sw_cfg_rw_timer_grp0_owner; | ||
185 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
186 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
187 | |||
188 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
189 | typedef struct { | ||
190 | unsigned int cfg : 2; | ||
191 | unsigned int dummy1 : 30; | ||
192 | } reg_iop_sw_cfg_rw_timer_grp1_owner; | ||
193 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
194 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
195 | |||
196 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
197 | typedef struct { | ||
198 | unsigned int cfg : 2; | ||
199 | unsigned int dummy1 : 30; | ||
200 | } reg_iop_sw_cfg_rw_trigger_grp0_owner; | ||
201 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
202 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
203 | |||
204 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
205 | typedef struct { | ||
206 | unsigned int cfg : 2; | ||
207 | unsigned int dummy1 : 30; | ||
208 | } reg_iop_sw_cfg_rw_trigger_grp1_owner; | ||
209 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
210 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
211 | |||
212 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
213 | typedef struct { | ||
214 | unsigned int cfg : 2; | ||
215 | unsigned int dummy1 : 30; | ||
216 | } reg_iop_sw_cfg_rw_trigger_grp2_owner; | ||
217 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
218 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
219 | |||
220 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
221 | typedef struct { | ||
222 | unsigned int cfg : 2; | ||
223 | unsigned int dummy1 : 30; | ||
224 | } reg_iop_sw_cfg_rw_trigger_grp3_owner; | ||
225 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
226 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
227 | |||
228 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
229 | typedef struct { | ||
230 | unsigned int cfg : 2; | ||
231 | unsigned int dummy1 : 30; | ||
232 | } reg_iop_sw_cfg_rw_trigger_grp4_owner; | ||
233 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
234 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
235 | |||
236 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
237 | typedef struct { | ||
238 | unsigned int cfg : 2; | ||
239 | unsigned int dummy1 : 30; | ||
240 | } reg_iop_sw_cfg_rw_trigger_grp5_owner; | ||
241 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
242 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
243 | |||
244 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
245 | typedef struct { | ||
246 | unsigned int cfg : 2; | ||
247 | unsigned int dummy1 : 30; | ||
248 | } reg_iop_sw_cfg_rw_trigger_grp6_owner; | ||
249 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
250 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
251 | |||
252 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
253 | typedef struct { | ||
254 | unsigned int cfg : 2; | ||
255 | unsigned int dummy1 : 30; | ||
256 | } reg_iop_sw_cfg_rw_trigger_grp7_owner; | ||
257 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
258 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
259 | |||
260 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
261 | typedef struct { | ||
262 | unsigned int byte0 : 8; | ||
263 | unsigned int byte1 : 8; | ||
264 | unsigned int byte2 : 8; | ||
265 | unsigned int byte3 : 8; | ||
266 | } reg_iop_sw_cfg_rw_bus_mask; | ||
267 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
268 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
269 | |||
270 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
271 | typedef struct { | ||
272 | unsigned int byte0 : 1; | ||
273 | unsigned int byte1 : 1; | ||
274 | unsigned int byte2 : 1; | ||
275 | unsigned int byte3 : 1; | ||
276 | unsigned int dummy1 : 28; | ||
277 | } reg_iop_sw_cfg_rw_bus_oe_mask; | ||
278 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
279 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
280 | |||
281 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
282 | typedef struct { | ||
283 | unsigned int val : 32; | ||
284 | } reg_iop_sw_cfg_rw_gio_mask; | ||
285 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
286 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
287 | |||
288 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
289 | typedef struct { | ||
290 | unsigned int val : 32; | ||
291 | } reg_iop_sw_cfg_rw_gio_oe_mask; | ||
292 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
293 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
294 | |||
295 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
296 | typedef struct { | ||
297 | unsigned int bus_byte0 : 2; | ||
298 | unsigned int bus_byte1 : 2; | ||
299 | unsigned int bus_byte2 : 2; | ||
300 | unsigned int bus_byte3 : 2; | ||
301 | unsigned int gio3_0 : 2; | ||
302 | unsigned int gio7_4 : 2; | ||
303 | unsigned int gio11_8 : 2; | ||
304 | unsigned int gio15_12 : 2; | ||
305 | unsigned int gio19_16 : 2; | ||
306 | unsigned int gio23_20 : 2; | ||
307 | unsigned int gio27_24 : 2; | ||
308 | unsigned int gio31_28 : 2; | ||
309 | unsigned int dummy1 : 8; | ||
310 | } reg_iop_sw_cfg_rw_pinmapping; | ||
311 | #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
312 | #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
313 | |||
314 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
315 | typedef struct { | ||
316 | unsigned int bus_lo : 2; | ||
317 | unsigned int bus_hi : 2; | ||
318 | unsigned int bus_lo_oe : 2; | ||
319 | unsigned int bus_hi_oe : 2; | ||
320 | unsigned int dummy1 : 24; | ||
321 | } reg_iop_sw_cfg_rw_bus_out_cfg; | ||
322 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
323 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
324 | |||
325 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
326 | typedef struct { | ||
327 | unsigned int gio0 : 3; | ||
328 | unsigned int gio0_oe : 1; | ||
329 | unsigned int gio1 : 3; | ||
330 | unsigned int gio1_oe : 1; | ||
331 | unsigned int gio2 : 3; | ||
332 | unsigned int gio2_oe : 1; | ||
333 | unsigned int gio3 : 3; | ||
334 | unsigned int gio3_oe : 1; | ||
335 | unsigned int dummy1 : 16; | ||
336 | } reg_iop_sw_cfg_rw_gio_out_grp0_cfg; | ||
337 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
338 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
339 | |||
340 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
341 | typedef struct { | ||
342 | unsigned int gio4 : 3; | ||
343 | unsigned int gio4_oe : 1; | ||
344 | unsigned int gio5 : 3; | ||
345 | unsigned int gio5_oe : 1; | ||
346 | unsigned int gio6 : 3; | ||
347 | unsigned int gio6_oe : 1; | ||
348 | unsigned int gio7 : 3; | ||
349 | unsigned int gio7_oe : 1; | ||
350 | unsigned int dummy1 : 16; | ||
351 | } reg_iop_sw_cfg_rw_gio_out_grp1_cfg; | ||
352 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
353 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
354 | |||
355 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
356 | typedef struct { | ||
357 | unsigned int gio8 : 3; | ||
358 | unsigned int gio8_oe : 1; | ||
359 | unsigned int gio9 : 3; | ||
360 | unsigned int gio9_oe : 1; | ||
361 | unsigned int gio10 : 3; | ||
362 | unsigned int gio10_oe : 1; | ||
363 | unsigned int gio11 : 3; | ||
364 | unsigned int gio11_oe : 1; | ||
365 | unsigned int dummy1 : 16; | ||
366 | } reg_iop_sw_cfg_rw_gio_out_grp2_cfg; | ||
367 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
368 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
369 | |||
370 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
371 | typedef struct { | ||
372 | unsigned int gio12 : 3; | ||
373 | unsigned int gio12_oe : 1; | ||
374 | unsigned int gio13 : 3; | ||
375 | unsigned int gio13_oe : 1; | ||
376 | unsigned int gio14 : 3; | ||
377 | unsigned int gio14_oe : 1; | ||
378 | unsigned int gio15 : 3; | ||
379 | unsigned int gio15_oe : 1; | ||
380 | unsigned int dummy1 : 16; | ||
381 | } reg_iop_sw_cfg_rw_gio_out_grp3_cfg; | ||
382 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
383 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
384 | |||
385 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
386 | typedef struct { | ||
387 | unsigned int gio16 : 3; | ||
388 | unsigned int gio16_oe : 1; | ||
389 | unsigned int gio17 : 3; | ||
390 | unsigned int gio17_oe : 1; | ||
391 | unsigned int gio18 : 3; | ||
392 | unsigned int gio18_oe : 1; | ||
393 | unsigned int gio19 : 3; | ||
394 | unsigned int gio19_oe : 1; | ||
395 | unsigned int dummy1 : 16; | ||
396 | } reg_iop_sw_cfg_rw_gio_out_grp4_cfg; | ||
397 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
398 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
399 | |||
400 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
401 | typedef struct { | ||
402 | unsigned int gio20 : 3; | ||
403 | unsigned int gio20_oe : 1; | ||
404 | unsigned int gio21 : 3; | ||
405 | unsigned int gio21_oe : 1; | ||
406 | unsigned int gio22 : 3; | ||
407 | unsigned int gio22_oe : 1; | ||
408 | unsigned int gio23 : 3; | ||
409 | unsigned int gio23_oe : 1; | ||
410 | unsigned int dummy1 : 16; | ||
411 | } reg_iop_sw_cfg_rw_gio_out_grp5_cfg; | ||
412 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
413 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
414 | |||
415 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
416 | typedef struct { | ||
417 | unsigned int gio24 : 3; | ||
418 | unsigned int gio24_oe : 1; | ||
419 | unsigned int gio25 : 3; | ||
420 | unsigned int gio25_oe : 1; | ||
421 | unsigned int gio26 : 3; | ||
422 | unsigned int gio26_oe : 1; | ||
423 | unsigned int gio27 : 3; | ||
424 | unsigned int gio27_oe : 1; | ||
425 | unsigned int dummy1 : 16; | ||
426 | } reg_iop_sw_cfg_rw_gio_out_grp6_cfg; | ||
427 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
428 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
429 | |||
430 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
431 | typedef struct { | ||
432 | unsigned int gio28 : 3; | ||
433 | unsigned int gio28_oe : 1; | ||
434 | unsigned int gio29 : 3; | ||
435 | unsigned int gio29_oe : 1; | ||
436 | unsigned int gio30 : 3; | ||
437 | unsigned int gio30_oe : 1; | ||
438 | unsigned int gio31 : 3; | ||
439 | unsigned int gio31_oe : 1; | ||
440 | unsigned int dummy1 : 16; | ||
441 | } reg_iop_sw_cfg_rw_gio_out_grp7_cfg; | ||
442 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
443 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
444 | |||
445 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
446 | typedef struct { | ||
447 | unsigned int bus0_in : 1; | ||
448 | unsigned int bus1_in : 1; | ||
449 | unsigned int dummy1 : 30; | ||
450 | } reg_iop_sw_cfg_rw_spu_cfg; | ||
451 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
452 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
453 | |||
454 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
455 | typedef struct { | ||
456 | unsigned int ext_clk : 3; | ||
457 | unsigned int tmr0_en : 2; | ||
458 | unsigned int tmr1_en : 2; | ||
459 | unsigned int tmr2_en : 2; | ||
460 | unsigned int tmr3_en : 2; | ||
461 | unsigned int tmr0_dis : 2; | ||
462 | unsigned int tmr1_dis : 2; | ||
463 | unsigned int tmr2_dis : 2; | ||
464 | unsigned int tmr3_dis : 2; | ||
465 | unsigned int dummy1 : 13; | ||
466 | } reg_iop_sw_cfg_rw_timer_grp0_cfg; | ||
467 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
468 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
469 | |||
470 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
471 | typedef struct { | ||
472 | unsigned int ext_clk : 3; | ||
473 | unsigned int tmr0_en : 2; | ||
474 | unsigned int tmr1_en : 2; | ||
475 | unsigned int tmr2_en : 2; | ||
476 | unsigned int tmr3_en : 2; | ||
477 | unsigned int tmr0_dis : 2; | ||
478 | unsigned int tmr1_dis : 2; | ||
479 | unsigned int tmr2_dis : 2; | ||
480 | unsigned int tmr3_dis : 2; | ||
481 | unsigned int dummy1 : 13; | ||
482 | } reg_iop_sw_cfg_rw_timer_grp1_cfg; | ||
483 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
484 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
485 | |||
486 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
487 | typedef struct { | ||
488 | unsigned int grp0_dis : 1; | ||
489 | unsigned int grp0_en : 1; | ||
490 | unsigned int grp1_dis : 1; | ||
491 | unsigned int grp1_en : 1; | ||
492 | unsigned int grp2_dis : 1; | ||
493 | unsigned int grp2_en : 1; | ||
494 | unsigned int grp3_dis : 1; | ||
495 | unsigned int grp3_en : 1; | ||
496 | unsigned int grp4_dis : 1; | ||
497 | unsigned int grp4_en : 1; | ||
498 | unsigned int grp5_dis : 1; | ||
499 | unsigned int grp5_en : 1; | ||
500 | unsigned int grp6_dis : 1; | ||
501 | unsigned int grp6_en : 1; | ||
502 | unsigned int grp7_dis : 1; | ||
503 | unsigned int grp7_en : 1; | ||
504 | unsigned int dummy1 : 16; | ||
505 | } reg_iop_sw_cfg_rw_trigger_grps_cfg; | ||
506 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
507 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
508 | |||
509 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
510 | typedef struct { | ||
511 | unsigned int out_strb : 4; | ||
512 | unsigned int in_src : 2; | ||
513 | unsigned int in_size : 3; | ||
514 | unsigned int in_last : 2; | ||
515 | unsigned int in_strb : 4; | ||
516 | unsigned int dummy1 : 17; | ||
517 | } reg_iop_sw_cfg_rw_pdp_cfg; | ||
518 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
519 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
520 | |||
521 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
522 | typedef struct { | ||
523 | unsigned int sdp_out_strb : 3; | ||
524 | unsigned int sdp_in_data : 3; | ||
525 | unsigned int sdp_in_last : 2; | ||
526 | unsigned int sdp_in_strb : 3; | ||
527 | unsigned int dummy1 : 21; | ||
528 | } reg_iop_sw_cfg_rw_sdp_cfg; | ||
529 | #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
530 | #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
531 | |||
532 | |||
533 | /* Constants */ | ||
534 | enum { | ||
535 | regk_iop_sw_cfg_a = 0x00000001, | ||
536 | regk_iop_sw_cfg_b = 0x00000002, | ||
537 | regk_iop_sw_cfg_bus = 0x00000000, | ||
538 | regk_iop_sw_cfg_bus_rot16 = 0x00000002, | ||
539 | regk_iop_sw_cfg_bus_rot24 = 0x00000003, | ||
540 | regk_iop_sw_cfg_bus_rot8 = 0x00000001, | ||
541 | regk_iop_sw_cfg_clk12 = 0x00000000, | ||
542 | regk_iop_sw_cfg_cpu = 0x00000000, | ||
543 | regk_iop_sw_cfg_gated_clk0 = 0x0000000e, | ||
544 | regk_iop_sw_cfg_gated_clk1 = 0x0000000f, | ||
545 | regk_iop_sw_cfg_gio0 = 0x00000004, | ||
546 | regk_iop_sw_cfg_gio1 = 0x00000001, | ||
547 | regk_iop_sw_cfg_gio2 = 0x00000005, | ||
548 | regk_iop_sw_cfg_gio3 = 0x00000002, | ||
549 | regk_iop_sw_cfg_gio4 = 0x00000006, | ||
550 | regk_iop_sw_cfg_gio5 = 0x00000003, | ||
551 | regk_iop_sw_cfg_gio6 = 0x00000007, | ||
552 | regk_iop_sw_cfg_gio7 = 0x00000004, | ||
553 | regk_iop_sw_cfg_gio_in18 = 0x00000002, | ||
554 | regk_iop_sw_cfg_gio_in19 = 0x00000003, | ||
555 | regk_iop_sw_cfg_gio_in20 = 0x00000004, | ||
556 | regk_iop_sw_cfg_gio_in21 = 0x00000005, | ||
557 | regk_iop_sw_cfg_gio_in26 = 0x00000006, | ||
558 | regk_iop_sw_cfg_gio_in27 = 0x00000007, | ||
559 | regk_iop_sw_cfg_gio_in4 = 0x00000000, | ||
560 | regk_iop_sw_cfg_gio_in5 = 0x00000001, | ||
561 | regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, | ||
562 | regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, | ||
563 | regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, | ||
564 | regk_iop_sw_cfg_mpu = 0x00000001, | ||
565 | regk_iop_sw_cfg_none = 0x00000000, | ||
566 | regk_iop_sw_cfg_pdp_out = 0x00000001, | ||
567 | regk_iop_sw_cfg_pdp_out_hi = 0x00000001, | ||
568 | regk_iop_sw_cfg_pdp_out_lo = 0x00000000, | ||
569 | regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, | ||
570 | regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, | ||
571 | regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, | ||
572 | regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, | ||
573 | regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, | ||
574 | regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, | ||
575 | regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, | ||
576 | regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, | ||
577 | regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, | ||
578 | regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, | ||
579 | regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, | ||
580 | regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, | ||
581 | regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, | ||
582 | regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, | ||
583 | regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, | ||
584 | regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, | ||
585 | regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, | ||
586 | regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, | ||
587 | regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, | ||
588 | regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, | ||
589 | regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, | ||
590 | regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, | ||
591 | regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, | ||
592 | regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, | ||
593 | regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, | ||
594 | regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, | ||
595 | regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, | ||
596 | regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, | ||
597 | regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, | ||
598 | regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, | ||
599 | regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, | ||
600 | regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, | ||
601 | regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, | ||
602 | regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, | ||
603 | regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, | ||
604 | regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, | ||
605 | regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, | ||
606 | regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, | ||
607 | regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, | ||
608 | regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, | ||
609 | regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, | ||
610 | regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, | ||
611 | regk_iop_sw_cfg_sdp_out = 0x00000004, | ||
612 | regk_iop_sw_cfg_size16 = 0x00000002, | ||
613 | regk_iop_sw_cfg_size24 = 0x00000003, | ||
614 | regk_iop_sw_cfg_size32 = 0x00000004, | ||
615 | regk_iop_sw_cfg_size8 = 0x00000001, | ||
616 | regk_iop_sw_cfg_spu = 0x00000002, | ||
617 | regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, | ||
618 | regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, | ||
619 | regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, | ||
620 | regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, | ||
621 | regk_iop_sw_cfg_spu_g0 = 0x00000007, | ||
622 | regk_iop_sw_cfg_spu_g1 = 0x00000007, | ||
623 | regk_iop_sw_cfg_spu_g2 = 0x00000007, | ||
624 | regk_iop_sw_cfg_spu_g3 = 0x00000007, | ||
625 | regk_iop_sw_cfg_spu_g4 = 0x00000007, | ||
626 | regk_iop_sw_cfg_spu_g5 = 0x00000007, | ||
627 | regk_iop_sw_cfg_spu_g6 = 0x00000007, | ||
628 | regk_iop_sw_cfg_spu_g7 = 0x00000007, | ||
629 | regk_iop_sw_cfg_spu_gio0 = 0x00000000, | ||
630 | regk_iop_sw_cfg_spu_gio1 = 0x00000001, | ||
631 | regk_iop_sw_cfg_spu_gio5 = 0x00000005, | ||
632 | regk_iop_sw_cfg_spu_gio6 = 0x00000006, | ||
633 | regk_iop_sw_cfg_spu_gio7 = 0x00000007, | ||
634 | regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, | ||
635 | regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, | ||
636 | regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, | ||
637 | regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, | ||
638 | regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, | ||
639 | regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, | ||
640 | regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, | ||
641 | regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, | ||
642 | regk_iop_sw_cfg_spu_gioout0 = 0x00000000, | ||
643 | regk_iop_sw_cfg_spu_gioout1 = 0x00000000, | ||
644 | regk_iop_sw_cfg_spu_gioout10 = 0x00000007, | ||
645 | regk_iop_sw_cfg_spu_gioout11 = 0x00000007, | ||
646 | regk_iop_sw_cfg_spu_gioout12 = 0x00000007, | ||
647 | regk_iop_sw_cfg_spu_gioout13 = 0x00000007, | ||
648 | regk_iop_sw_cfg_spu_gioout14 = 0x00000007, | ||
649 | regk_iop_sw_cfg_spu_gioout15 = 0x00000007, | ||
650 | regk_iop_sw_cfg_spu_gioout16 = 0x00000007, | ||
651 | regk_iop_sw_cfg_spu_gioout17 = 0x00000007, | ||
652 | regk_iop_sw_cfg_spu_gioout18 = 0x00000007, | ||
653 | regk_iop_sw_cfg_spu_gioout19 = 0x00000007, | ||
654 | regk_iop_sw_cfg_spu_gioout2 = 0x00000001, | ||
655 | regk_iop_sw_cfg_spu_gioout20 = 0x00000007, | ||
656 | regk_iop_sw_cfg_spu_gioout21 = 0x00000007, | ||
657 | regk_iop_sw_cfg_spu_gioout22 = 0x00000007, | ||
658 | regk_iop_sw_cfg_spu_gioout23 = 0x00000007, | ||
659 | regk_iop_sw_cfg_spu_gioout24 = 0x00000007, | ||
660 | regk_iop_sw_cfg_spu_gioout25 = 0x00000007, | ||
661 | regk_iop_sw_cfg_spu_gioout26 = 0x00000007, | ||
662 | regk_iop_sw_cfg_spu_gioout27 = 0x00000007, | ||
663 | regk_iop_sw_cfg_spu_gioout28 = 0x00000007, | ||
664 | regk_iop_sw_cfg_spu_gioout29 = 0x00000007, | ||
665 | regk_iop_sw_cfg_spu_gioout3 = 0x00000001, | ||
666 | regk_iop_sw_cfg_spu_gioout30 = 0x00000007, | ||
667 | regk_iop_sw_cfg_spu_gioout31 = 0x00000007, | ||
668 | regk_iop_sw_cfg_spu_gioout4 = 0x00000002, | ||
669 | regk_iop_sw_cfg_spu_gioout5 = 0x00000002, | ||
670 | regk_iop_sw_cfg_spu_gioout6 = 0x00000003, | ||
671 | regk_iop_sw_cfg_spu_gioout7 = 0x00000003, | ||
672 | regk_iop_sw_cfg_spu_gioout8 = 0x00000007, | ||
673 | regk_iop_sw_cfg_spu_gioout9 = 0x00000007, | ||
674 | regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, | ||
675 | regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, | ||
676 | regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, | ||
677 | regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, | ||
678 | regk_iop_sw_cfg_timer_grp0 = 0x00000000, | ||
679 | regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, | ||
680 | regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, | ||
681 | regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, | ||
682 | regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, | ||
683 | regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, | ||
684 | regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, | ||
685 | regk_iop_sw_cfg_timer_grp1 = 0x00000000, | ||
686 | regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, | ||
687 | regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, | ||
688 | regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, | ||
689 | regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, | ||
690 | regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, | ||
691 | regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, | ||
692 | regk_iop_sw_cfg_trig0_0 = 0x00000000, | ||
693 | regk_iop_sw_cfg_trig0_1 = 0x00000000, | ||
694 | regk_iop_sw_cfg_trig0_2 = 0x00000000, | ||
695 | regk_iop_sw_cfg_trig0_3 = 0x00000000, | ||
696 | regk_iop_sw_cfg_trig1_0 = 0x00000000, | ||
697 | regk_iop_sw_cfg_trig1_1 = 0x00000000, | ||
698 | regk_iop_sw_cfg_trig1_2 = 0x00000000, | ||
699 | regk_iop_sw_cfg_trig1_3 = 0x00000000, | ||
700 | regk_iop_sw_cfg_trig2_0 = 0x00000001, | ||
701 | regk_iop_sw_cfg_trig2_1 = 0x00000001, | ||
702 | regk_iop_sw_cfg_trig2_2 = 0x00000001, | ||
703 | regk_iop_sw_cfg_trig2_3 = 0x00000001, | ||
704 | regk_iop_sw_cfg_trig3_0 = 0x00000001, | ||
705 | regk_iop_sw_cfg_trig3_1 = 0x00000001, | ||
706 | regk_iop_sw_cfg_trig3_2 = 0x00000001, | ||
707 | regk_iop_sw_cfg_trig3_3 = 0x00000001, | ||
708 | regk_iop_sw_cfg_trig4_0 = 0x00000002, | ||
709 | regk_iop_sw_cfg_trig4_1 = 0x00000002, | ||
710 | regk_iop_sw_cfg_trig4_2 = 0x00000002, | ||
711 | regk_iop_sw_cfg_trig4_3 = 0x00000002, | ||
712 | regk_iop_sw_cfg_trig5_0 = 0x00000002, | ||
713 | regk_iop_sw_cfg_trig5_1 = 0x00000002, | ||
714 | regk_iop_sw_cfg_trig5_2 = 0x00000002, | ||
715 | regk_iop_sw_cfg_trig5_3 = 0x00000002, | ||
716 | regk_iop_sw_cfg_trig6_0 = 0x00000003, | ||
717 | regk_iop_sw_cfg_trig6_1 = 0x00000003, | ||
718 | regk_iop_sw_cfg_trig6_2 = 0x00000003, | ||
719 | regk_iop_sw_cfg_trig6_3 = 0x00000003, | ||
720 | regk_iop_sw_cfg_trig7_0 = 0x00000003, | ||
721 | regk_iop_sw_cfg_trig7_1 = 0x00000003, | ||
722 | regk_iop_sw_cfg_trig7_2 = 0x00000003, | ||
723 | regk_iop_sw_cfg_trig7_3 = 0x00000003 | ||
724 | }; | ||
725 | #endif /* __iop_sw_cfg_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 00000000000..a16f556370e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h | |||
@@ -0,0 +1,522 @@ | |||
1 | #ifndef __iop_sw_cpu_defs_h | ||
2 | #define __iop_sw_cpu_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_cpu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sw_cpu */ | ||
83 | |||
84 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
85 | typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; | ||
86 | #define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 | ||
87 | |||
88 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
89 | typedef unsigned int reg_iop_sw_cpu_r_spu_trace; | ||
90 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 | ||
91 | |||
92 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
93 | typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; | ||
94 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 | ||
95 | |||
96 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
97 | typedef struct { | ||
98 | unsigned int keep_owner : 1; | ||
99 | unsigned int cmd : 2; | ||
100 | unsigned int size : 3; | ||
101 | unsigned int wr_spu_mem : 1; | ||
102 | unsigned int dummy1 : 25; | ||
103 | } reg_iop_sw_cpu_rw_mc_ctrl; | ||
104 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
105 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
106 | |||
107 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
108 | typedef struct { | ||
109 | unsigned int val : 32; | ||
110 | } reg_iop_sw_cpu_rw_mc_data; | ||
111 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
112 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
113 | |||
114 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
115 | typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; | ||
116 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
117 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
118 | |||
119 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
120 | typedef unsigned int reg_iop_sw_cpu_rs_mc_data; | ||
121 | #define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 | ||
122 | |||
123 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
124 | typedef unsigned int reg_iop_sw_cpu_r_mc_data; | ||
125 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 | ||
126 | |||
127 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
128 | typedef struct { | ||
129 | unsigned int busy_cpu : 1; | ||
130 | unsigned int busy_mpu : 1; | ||
131 | unsigned int busy_spu : 1; | ||
132 | unsigned int owned_by_cpu : 1; | ||
133 | unsigned int owned_by_mpu : 1; | ||
134 | unsigned int owned_by_spu : 1; | ||
135 | unsigned int dummy1 : 26; | ||
136 | } reg_iop_sw_cpu_r_mc_stat; | ||
137 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 | ||
138 | |||
139 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
140 | typedef struct { | ||
141 | unsigned int byte0 : 8; | ||
142 | unsigned int byte1 : 8; | ||
143 | unsigned int byte2 : 8; | ||
144 | unsigned int byte3 : 8; | ||
145 | } reg_iop_sw_cpu_rw_bus_clr_mask; | ||
146 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
147 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
148 | |||
149 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
150 | typedef struct { | ||
151 | unsigned int byte0 : 8; | ||
152 | unsigned int byte1 : 8; | ||
153 | unsigned int byte2 : 8; | ||
154 | unsigned int byte3 : 8; | ||
155 | } reg_iop_sw_cpu_rw_bus_set_mask; | ||
156 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
157 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
158 | |||
159 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
160 | typedef struct { | ||
161 | unsigned int byte0 : 1; | ||
162 | unsigned int byte1 : 1; | ||
163 | unsigned int byte2 : 1; | ||
164 | unsigned int byte3 : 1; | ||
165 | unsigned int dummy1 : 28; | ||
166 | } reg_iop_sw_cpu_rw_bus_oe_clr_mask; | ||
167 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
168 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
169 | |||
170 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
171 | typedef struct { | ||
172 | unsigned int byte0 : 1; | ||
173 | unsigned int byte1 : 1; | ||
174 | unsigned int byte2 : 1; | ||
175 | unsigned int byte3 : 1; | ||
176 | unsigned int dummy1 : 28; | ||
177 | } reg_iop_sw_cpu_rw_bus_oe_set_mask; | ||
178 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
179 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
180 | |||
181 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
182 | typedef unsigned int reg_iop_sw_cpu_r_bus_in; | ||
183 | #define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 | ||
184 | |||
185 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
186 | typedef struct { | ||
187 | unsigned int val : 32; | ||
188 | } reg_iop_sw_cpu_rw_gio_clr_mask; | ||
189 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
190 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
191 | |||
192 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
193 | typedef struct { | ||
194 | unsigned int val : 32; | ||
195 | } reg_iop_sw_cpu_rw_gio_set_mask; | ||
196 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
197 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
198 | |||
199 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
200 | typedef struct { | ||
201 | unsigned int val : 32; | ||
202 | } reg_iop_sw_cpu_rw_gio_oe_clr_mask; | ||
203 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
204 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
205 | |||
206 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
207 | typedef struct { | ||
208 | unsigned int val : 32; | ||
209 | } reg_iop_sw_cpu_rw_gio_oe_set_mask; | ||
210 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
211 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
212 | |||
213 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
214 | typedef unsigned int reg_iop_sw_cpu_r_gio_in; | ||
215 | #define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 | ||
216 | |||
217 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
218 | typedef struct { | ||
219 | unsigned int mpu_0 : 1; | ||
220 | unsigned int mpu_1 : 1; | ||
221 | unsigned int mpu_2 : 1; | ||
222 | unsigned int mpu_3 : 1; | ||
223 | unsigned int mpu_4 : 1; | ||
224 | unsigned int mpu_5 : 1; | ||
225 | unsigned int mpu_6 : 1; | ||
226 | unsigned int mpu_7 : 1; | ||
227 | unsigned int mpu_8 : 1; | ||
228 | unsigned int mpu_9 : 1; | ||
229 | unsigned int mpu_10 : 1; | ||
230 | unsigned int mpu_11 : 1; | ||
231 | unsigned int mpu_12 : 1; | ||
232 | unsigned int mpu_13 : 1; | ||
233 | unsigned int mpu_14 : 1; | ||
234 | unsigned int mpu_15 : 1; | ||
235 | unsigned int spu_0 : 1; | ||
236 | unsigned int spu_1 : 1; | ||
237 | unsigned int spu_2 : 1; | ||
238 | unsigned int spu_3 : 1; | ||
239 | unsigned int spu_4 : 1; | ||
240 | unsigned int spu_5 : 1; | ||
241 | unsigned int spu_6 : 1; | ||
242 | unsigned int spu_7 : 1; | ||
243 | unsigned int spu_8 : 1; | ||
244 | unsigned int spu_9 : 1; | ||
245 | unsigned int spu_10 : 1; | ||
246 | unsigned int spu_11 : 1; | ||
247 | unsigned int spu_12 : 1; | ||
248 | unsigned int spu_13 : 1; | ||
249 | unsigned int spu_14 : 1; | ||
250 | unsigned int spu_15 : 1; | ||
251 | } reg_iop_sw_cpu_rw_intr0_mask; | ||
252 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
253 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
254 | |||
255 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
256 | typedef struct { | ||
257 | unsigned int mpu_0 : 1; | ||
258 | unsigned int mpu_1 : 1; | ||
259 | unsigned int mpu_2 : 1; | ||
260 | unsigned int mpu_3 : 1; | ||
261 | unsigned int mpu_4 : 1; | ||
262 | unsigned int mpu_5 : 1; | ||
263 | unsigned int mpu_6 : 1; | ||
264 | unsigned int mpu_7 : 1; | ||
265 | unsigned int mpu_8 : 1; | ||
266 | unsigned int mpu_9 : 1; | ||
267 | unsigned int mpu_10 : 1; | ||
268 | unsigned int mpu_11 : 1; | ||
269 | unsigned int mpu_12 : 1; | ||
270 | unsigned int mpu_13 : 1; | ||
271 | unsigned int mpu_14 : 1; | ||
272 | unsigned int mpu_15 : 1; | ||
273 | unsigned int spu_0 : 1; | ||
274 | unsigned int spu_1 : 1; | ||
275 | unsigned int spu_2 : 1; | ||
276 | unsigned int spu_3 : 1; | ||
277 | unsigned int spu_4 : 1; | ||
278 | unsigned int spu_5 : 1; | ||
279 | unsigned int spu_6 : 1; | ||
280 | unsigned int spu_7 : 1; | ||
281 | unsigned int spu_8 : 1; | ||
282 | unsigned int spu_9 : 1; | ||
283 | unsigned int spu_10 : 1; | ||
284 | unsigned int spu_11 : 1; | ||
285 | unsigned int spu_12 : 1; | ||
286 | unsigned int spu_13 : 1; | ||
287 | unsigned int spu_14 : 1; | ||
288 | unsigned int spu_15 : 1; | ||
289 | } reg_iop_sw_cpu_rw_ack_intr0; | ||
290 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
291 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
292 | |||
293 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
294 | typedef struct { | ||
295 | unsigned int mpu_0 : 1; | ||
296 | unsigned int mpu_1 : 1; | ||
297 | unsigned int mpu_2 : 1; | ||
298 | unsigned int mpu_3 : 1; | ||
299 | unsigned int mpu_4 : 1; | ||
300 | unsigned int mpu_5 : 1; | ||
301 | unsigned int mpu_6 : 1; | ||
302 | unsigned int mpu_7 : 1; | ||
303 | unsigned int mpu_8 : 1; | ||
304 | unsigned int mpu_9 : 1; | ||
305 | unsigned int mpu_10 : 1; | ||
306 | unsigned int mpu_11 : 1; | ||
307 | unsigned int mpu_12 : 1; | ||
308 | unsigned int mpu_13 : 1; | ||
309 | unsigned int mpu_14 : 1; | ||
310 | unsigned int mpu_15 : 1; | ||
311 | unsigned int spu_0 : 1; | ||
312 | unsigned int spu_1 : 1; | ||
313 | unsigned int spu_2 : 1; | ||
314 | unsigned int spu_3 : 1; | ||
315 | unsigned int spu_4 : 1; | ||
316 | unsigned int spu_5 : 1; | ||
317 | unsigned int spu_6 : 1; | ||
318 | unsigned int spu_7 : 1; | ||
319 | unsigned int spu_8 : 1; | ||
320 | unsigned int spu_9 : 1; | ||
321 | unsigned int spu_10 : 1; | ||
322 | unsigned int spu_11 : 1; | ||
323 | unsigned int spu_12 : 1; | ||
324 | unsigned int spu_13 : 1; | ||
325 | unsigned int spu_14 : 1; | ||
326 | unsigned int spu_15 : 1; | ||
327 | } reg_iop_sw_cpu_r_intr0; | ||
328 | #define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 | ||
329 | |||
330 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
331 | typedef struct { | ||
332 | unsigned int mpu_0 : 1; | ||
333 | unsigned int mpu_1 : 1; | ||
334 | unsigned int mpu_2 : 1; | ||
335 | unsigned int mpu_3 : 1; | ||
336 | unsigned int mpu_4 : 1; | ||
337 | unsigned int mpu_5 : 1; | ||
338 | unsigned int mpu_6 : 1; | ||
339 | unsigned int mpu_7 : 1; | ||
340 | unsigned int mpu_8 : 1; | ||
341 | unsigned int mpu_9 : 1; | ||
342 | unsigned int mpu_10 : 1; | ||
343 | unsigned int mpu_11 : 1; | ||
344 | unsigned int mpu_12 : 1; | ||
345 | unsigned int mpu_13 : 1; | ||
346 | unsigned int mpu_14 : 1; | ||
347 | unsigned int mpu_15 : 1; | ||
348 | unsigned int spu_0 : 1; | ||
349 | unsigned int spu_1 : 1; | ||
350 | unsigned int spu_2 : 1; | ||
351 | unsigned int spu_3 : 1; | ||
352 | unsigned int spu_4 : 1; | ||
353 | unsigned int spu_5 : 1; | ||
354 | unsigned int spu_6 : 1; | ||
355 | unsigned int spu_7 : 1; | ||
356 | unsigned int spu_8 : 1; | ||
357 | unsigned int spu_9 : 1; | ||
358 | unsigned int spu_10 : 1; | ||
359 | unsigned int spu_11 : 1; | ||
360 | unsigned int spu_12 : 1; | ||
361 | unsigned int spu_13 : 1; | ||
362 | unsigned int spu_14 : 1; | ||
363 | unsigned int spu_15 : 1; | ||
364 | } reg_iop_sw_cpu_r_masked_intr0; | ||
365 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 | ||
366 | |||
367 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
368 | typedef struct { | ||
369 | unsigned int mpu_16 : 1; | ||
370 | unsigned int mpu_17 : 1; | ||
371 | unsigned int mpu_18 : 1; | ||
372 | unsigned int mpu_19 : 1; | ||
373 | unsigned int mpu_20 : 1; | ||
374 | unsigned int mpu_21 : 1; | ||
375 | unsigned int mpu_22 : 1; | ||
376 | unsigned int mpu_23 : 1; | ||
377 | unsigned int mpu_24 : 1; | ||
378 | unsigned int mpu_25 : 1; | ||
379 | unsigned int mpu_26 : 1; | ||
380 | unsigned int mpu_27 : 1; | ||
381 | unsigned int mpu_28 : 1; | ||
382 | unsigned int mpu_29 : 1; | ||
383 | unsigned int mpu_30 : 1; | ||
384 | unsigned int mpu_31 : 1; | ||
385 | unsigned int dmc_in : 1; | ||
386 | unsigned int dmc_out : 1; | ||
387 | unsigned int fifo_in : 1; | ||
388 | unsigned int fifo_out : 1; | ||
389 | unsigned int fifo_in_extra : 1; | ||
390 | unsigned int fifo_out_extra : 1; | ||
391 | unsigned int trigger_grp0 : 1; | ||
392 | unsigned int trigger_grp1 : 1; | ||
393 | unsigned int trigger_grp2 : 1; | ||
394 | unsigned int trigger_grp3 : 1; | ||
395 | unsigned int trigger_grp4 : 1; | ||
396 | unsigned int trigger_grp5 : 1; | ||
397 | unsigned int trigger_grp6 : 1; | ||
398 | unsigned int trigger_grp7 : 1; | ||
399 | unsigned int timer_grp0 : 1; | ||
400 | unsigned int timer_grp1 : 1; | ||
401 | } reg_iop_sw_cpu_rw_intr1_mask; | ||
402 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
403 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
404 | |||
405 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
406 | typedef struct { | ||
407 | unsigned int mpu_16 : 1; | ||
408 | unsigned int mpu_17 : 1; | ||
409 | unsigned int mpu_18 : 1; | ||
410 | unsigned int mpu_19 : 1; | ||
411 | unsigned int mpu_20 : 1; | ||
412 | unsigned int mpu_21 : 1; | ||
413 | unsigned int mpu_22 : 1; | ||
414 | unsigned int mpu_23 : 1; | ||
415 | unsigned int mpu_24 : 1; | ||
416 | unsigned int mpu_25 : 1; | ||
417 | unsigned int mpu_26 : 1; | ||
418 | unsigned int mpu_27 : 1; | ||
419 | unsigned int mpu_28 : 1; | ||
420 | unsigned int mpu_29 : 1; | ||
421 | unsigned int mpu_30 : 1; | ||
422 | unsigned int mpu_31 : 1; | ||
423 | unsigned int dummy1 : 16; | ||
424 | } reg_iop_sw_cpu_rw_ack_intr1; | ||
425 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
426 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
427 | |||
428 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
429 | typedef struct { | ||
430 | unsigned int mpu_16 : 1; | ||
431 | unsigned int mpu_17 : 1; | ||
432 | unsigned int mpu_18 : 1; | ||
433 | unsigned int mpu_19 : 1; | ||
434 | unsigned int mpu_20 : 1; | ||
435 | unsigned int mpu_21 : 1; | ||
436 | unsigned int mpu_22 : 1; | ||
437 | unsigned int mpu_23 : 1; | ||
438 | unsigned int mpu_24 : 1; | ||
439 | unsigned int mpu_25 : 1; | ||
440 | unsigned int mpu_26 : 1; | ||
441 | unsigned int mpu_27 : 1; | ||
442 | unsigned int mpu_28 : 1; | ||
443 | unsigned int mpu_29 : 1; | ||
444 | unsigned int mpu_30 : 1; | ||
445 | unsigned int mpu_31 : 1; | ||
446 | unsigned int dmc_in : 1; | ||
447 | unsigned int dmc_out : 1; | ||
448 | unsigned int fifo_in : 1; | ||
449 | unsigned int fifo_out : 1; | ||
450 | unsigned int fifo_in_extra : 1; | ||
451 | unsigned int fifo_out_extra : 1; | ||
452 | unsigned int trigger_grp0 : 1; | ||
453 | unsigned int trigger_grp1 : 1; | ||
454 | unsigned int trigger_grp2 : 1; | ||
455 | unsigned int trigger_grp3 : 1; | ||
456 | unsigned int trigger_grp4 : 1; | ||
457 | unsigned int trigger_grp5 : 1; | ||
458 | unsigned int trigger_grp6 : 1; | ||
459 | unsigned int trigger_grp7 : 1; | ||
460 | unsigned int timer_grp0 : 1; | ||
461 | unsigned int timer_grp1 : 1; | ||
462 | } reg_iop_sw_cpu_r_intr1; | ||
463 | #define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 | ||
464 | |||
465 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
466 | typedef struct { | ||
467 | unsigned int mpu_16 : 1; | ||
468 | unsigned int mpu_17 : 1; | ||
469 | unsigned int mpu_18 : 1; | ||
470 | unsigned int mpu_19 : 1; | ||
471 | unsigned int mpu_20 : 1; | ||
472 | unsigned int mpu_21 : 1; | ||
473 | unsigned int mpu_22 : 1; | ||
474 | unsigned int mpu_23 : 1; | ||
475 | unsigned int mpu_24 : 1; | ||
476 | unsigned int mpu_25 : 1; | ||
477 | unsigned int mpu_26 : 1; | ||
478 | unsigned int mpu_27 : 1; | ||
479 | unsigned int mpu_28 : 1; | ||
480 | unsigned int mpu_29 : 1; | ||
481 | unsigned int mpu_30 : 1; | ||
482 | unsigned int mpu_31 : 1; | ||
483 | unsigned int dmc_in : 1; | ||
484 | unsigned int dmc_out : 1; | ||
485 | unsigned int fifo_in : 1; | ||
486 | unsigned int fifo_out : 1; | ||
487 | unsigned int fifo_in_extra : 1; | ||
488 | unsigned int fifo_out_extra : 1; | ||
489 | unsigned int trigger_grp0 : 1; | ||
490 | unsigned int trigger_grp1 : 1; | ||
491 | unsigned int trigger_grp2 : 1; | ||
492 | unsigned int trigger_grp3 : 1; | ||
493 | unsigned int trigger_grp4 : 1; | ||
494 | unsigned int trigger_grp5 : 1; | ||
495 | unsigned int trigger_grp6 : 1; | ||
496 | unsigned int trigger_grp7 : 1; | ||
497 | unsigned int timer_grp0 : 1; | ||
498 | unsigned int timer_grp1 : 1; | ||
499 | } reg_iop_sw_cpu_r_masked_intr1; | ||
500 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 | ||
501 | |||
502 | |||
503 | /* Constants */ | ||
504 | enum { | ||
505 | regk_iop_sw_cpu_copy = 0x00000000, | ||
506 | regk_iop_sw_cpu_no = 0x00000000, | ||
507 | regk_iop_sw_cpu_rd = 0x00000002, | ||
508 | regk_iop_sw_cpu_reg_copy = 0x00000001, | ||
509 | regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, | ||
510 | regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
511 | regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
512 | regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, | ||
513 | regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, | ||
514 | regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
515 | regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
516 | regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, | ||
517 | regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, | ||
518 | regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, | ||
519 | regk_iop_sw_cpu_wr = 0x00000003, | ||
520 | regk_iop_sw_cpu_yes = 0x00000001 | ||
521 | }; | ||
522 | #endif /* __iop_sw_cpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 00000000000..a2e4e1a33e5 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h | |||
@@ -0,0 +1,648 @@ | |||
1 | #ifndef __iop_sw_mpu_defs_h | ||
2 | #define __iop_sw_mpu_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_mpu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sw_mpu */ | ||
83 | |||
84 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
85 | typedef struct { | ||
86 | unsigned int cfg : 2; | ||
87 | unsigned int dummy1 : 30; | ||
88 | } reg_iop_sw_mpu_rw_sw_cfg_owner; | ||
89 | #define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
90 | #define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
91 | |||
92 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
93 | typedef unsigned int reg_iop_sw_mpu_r_spu_trace; | ||
94 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 | ||
95 | |||
96 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
97 | typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; | ||
98 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 | ||
99 | |||
100 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
101 | typedef struct { | ||
102 | unsigned int keep_owner : 1; | ||
103 | unsigned int cmd : 2; | ||
104 | unsigned int size : 3; | ||
105 | unsigned int wr_spu_mem : 1; | ||
106 | unsigned int dummy1 : 25; | ||
107 | } reg_iop_sw_mpu_rw_mc_ctrl; | ||
108 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
109 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
110 | |||
111 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
112 | typedef struct { | ||
113 | unsigned int val : 32; | ||
114 | } reg_iop_sw_mpu_rw_mc_data; | ||
115 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
116 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
117 | |||
118 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
119 | typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; | ||
120 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
121 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
122 | |||
123 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
124 | typedef unsigned int reg_iop_sw_mpu_rs_mc_data; | ||
125 | #define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 | ||
126 | |||
127 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
128 | typedef unsigned int reg_iop_sw_mpu_r_mc_data; | ||
129 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 | ||
130 | |||
131 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
132 | typedef struct { | ||
133 | unsigned int busy_cpu : 1; | ||
134 | unsigned int busy_mpu : 1; | ||
135 | unsigned int busy_spu : 1; | ||
136 | unsigned int owned_by_cpu : 1; | ||
137 | unsigned int owned_by_mpu : 1; | ||
138 | unsigned int owned_by_spu : 1; | ||
139 | unsigned int dummy1 : 26; | ||
140 | } reg_iop_sw_mpu_r_mc_stat; | ||
141 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 | ||
142 | |||
143 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
144 | typedef struct { | ||
145 | unsigned int byte0 : 8; | ||
146 | unsigned int byte1 : 8; | ||
147 | unsigned int byte2 : 8; | ||
148 | unsigned int byte3 : 8; | ||
149 | } reg_iop_sw_mpu_rw_bus_clr_mask; | ||
150 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
151 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
152 | |||
153 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
154 | typedef struct { | ||
155 | unsigned int byte0 : 8; | ||
156 | unsigned int byte1 : 8; | ||
157 | unsigned int byte2 : 8; | ||
158 | unsigned int byte3 : 8; | ||
159 | } reg_iop_sw_mpu_rw_bus_set_mask; | ||
160 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
161 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
162 | |||
163 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
164 | typedef struct { | ||
165 | unsigned int byte0 : 1; | ||
166 | unsigned int byte1 : 1; | ||
167 | unsigned int byte2 : 1; | ||
168 | unsigned int byte3 : 1; | ||
169 | unsigned int dummy1 : 28; | ||
170 | } reg_iop_sw_mpu_rw_bus_oe_clr_mask; | ||
171 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
172 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
173 | |||
174 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
175 | typedef struct { | ||
176 | unsigned int byte0 : 1; | ||
177 | unsigned int byte1 : 1; | ||
178 | unsigned int byte2 : 1; | ||
179 | unsigned int byte3 : 1; | ||
180 | unsigned int dummy1 : 28; | ||
181 | } reg_iop_sw_mpu_rw_bus_oe_set_mask; | ||
182 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
183 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
184 | |||
185 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
186 | typedef unsigned int reg_iop_sw_mpu_r_bus_in; | ||
187 | #define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 | ||
188 | |||
189 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
190 | typedef struct { | ||
191 | unsigned int val : 32; | ||
192 | } reg_iop_sw_mpu_rw_gio_clr_mask; | ||
193 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
194 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
195 | |||
196 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
197 | typedef struct { | ||
198 | unsigned int val : 32; | ||
199 | } reg_iop_sw_mpu_rw_gio_set_mask; | ||
200 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
201 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
202 | |||
203 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
204 | typedef struct { | ||
205 | unsigned int val : 32; | ||
206 | } reg_iop_sw_mpu_rw_gio_oe_clr_mask; | ||
207 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
208 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
209 | |||
210 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
211 | typedef struct { | ||
212 | unsigned int val : 32; | ||
213 | } reg_iop_sw_mpu_rw_gio_oe_set_mask; | ||
214 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
215 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
216 | |||
217 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
218 | typedef unsigned int reg_iop_sw_mpu_r_gio_in; | ||
219 | #define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 | ||
220 | |||
221 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
222 | typedef struct { | ||
223 | unsigned int intr0 : 1; | ||
224 | unsigned int intr1 : 1; | ||
225 | unsigned int intr2 : 1; | ||
226 | unsigned int intr3 : 1; | ||
227 | unsigned int intr4 : 1; | ||
228 | unsigned int intr5 : 1; | ||
229 | unsigned int intr6 : 1; | ||
230 | unsigned int intr7 : 1; | ||
231 | unsigned int intr8 : 1; | ||
232 | unsigned int intr9 : 1; | ||
233 | unsigned int intr10 : 1; | ||
234 | unsigned int intr11 : 1; | ||
235 | unsigned int intr12 : 1; | ||
236 | unsigned int intr13 : 1; | ||
237 | unsigned int intr14 : 1; | ||
238 | unsigned int intr15 : 1; | ||
239 | unsigned int intr16 : 1; | ||
240 | unsigned int intr17 : 1; | ||
241 | unsigned int intr18 : 1; | ||
242 | unsigned int intr19 : 1; | ||
243 | unsigned int intr20 : 1; | ||
244 | unsigned int intr21 : 1; | ||
245 | unsigned int intr22 : 1; | ||
246 | unsigned int intr23 : 1; | ||
247 | unsigned int intr24 : 1; | ||
248 | unsigned int intr25 : 1; | ||
249 | unsigned int intr26 : 1; | ||
250 | unsigned int intr27 : 1; | ||
251 | unsigned int intr28 : 1; | ||
252 | unsigned int intr29 : 1; | ||
253 | unsigned int intr30 : 1; | ||
254 | unsigned int intr31 : 1; | ||
255 | } reg_iop_sw_mpu_rw_cpu_intr; | ||
256 | #define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
257 | #define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
258 | |||
259 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
260 | typedef struct { | ||
261 | unsigned int intr0 : 1; | ||
262 | unsigned int intr1 : 1; | ||
263 | unsigned int intr2 : 1; | ||
264 | unsigned int intr3 : 1; | ||
265 | unsigned int intr4 : 1; | ||
266 | unsigned int intr5 : 1; | ||
267 | unsigned int intr6 : 1; | ||
268 | unsigned int intr7 : 1; | ||
269 | unsigned int intr8 : 1; | ||
270 | unsigned int intr9 : 1; | ||
271 | unsigned int intr10 : 1; | ||
272 | unsigned int intr11 : 1; | ||
273 | unsigned int intr12 : 1; | ||
274 | unsigned int intr13 : 1; | ||
275 | unsigned int intr14 : 1; | ||
276 | unsigned int intr15 : 1; | ||
277 | unsigned int intr16 : 1; | ||
278 | unsigned int intr17 : 1; | ||
279 | unsigned int intr18 : 1; | ||
280 | unsigned int intr19 : 1; | ||
281 | unsigned int intr20 : 1; | ||
282 | unsigned int intr21 : 1; | ||
283 | unsigned int intr22 : 1; | ||
284 | unsigned int intr23 : 1; | ||
285 | unsigned int intr24 : 1; | ||
286 | unsigned int intr25 : 1; | ||
287 | unsigned int intr26 : 1; | ||
288 | unsigned int intr27 : 1; | ||
289 | unsigned int intr28 : 1; | ||
290 | unsigned int intr29 : 1; | ||
291 | unsigned int intr30 : 1; | ||
292 | unsigned int intr31 : 1; | ||
293 | } reg_iop_sw_mpu_r_cpu_intr; | ||
294 | #define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 | ||
295 | |||
296 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
297 | typedef struct { | ||
298 | unsigned int spu_intr0 : 1; | ||
299 | unsigned int trigger_grp0 : 1; | ||
300 | unsigned int timer_grp0 : 1; | ||
301 | unsigned int fifo_out : 1; | ||
302 | unsigned int spu_intr1 : 1; | ||
303 | unsigned int trigger_grp1 : 1; | ||
304 | unsigned int timer_grp1 : 1; | ||
305 | unsigned int fifo_in : 1; | ||
306 | unsigned int spu_intr2 : 1; | ||
307 | unsigned int trigger_grp2 : 1; | ||
308 | unsigned int fifo_out_extra : 1; | ||
309 | unsigned int dmc_out : 1; | ||
310 | unsigned int spu_intr3 : 1; | ||
311 | unsigned int trigger_grp3 : 1; | ||
312 | unsigned int fifo_in_extra : 1; | ||
313 | unsigned int dmc_in : 1; | ||
314 | unsigned int dummy1 : 16; | ||
315 | } reg_iop_sw_mpu_rw_intr_grp0_mask; | ||
316 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
317 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
318 | |||
319 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
320 | typedef struct { | ||
321 | unsigned int spu_intr0 : 1; | ||
322 | unsigned int dummy1 : 3; | ||
323 | unsigned int spu_intr1 : 1; | ||
324 | unsigned int dummy2 : 3; | ||
325 | unsigned int spu_intr2 : 1; | ||
326 | unsigned int dummy3 : 3; | ||
327 | unsigned int spu_intr3 : 1; | ||
328 | unsigned int dummy4 : 19; | ||
329 | } reg_iop_sw_mpu_rw_ack_intr_grp0; | ||
330 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
331 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
332 | |||
333 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
334 | typedef struct { | ||
335 | unsigned int spu_intr0 : 1; | ||
336 | unsigned int trigger_grp0 : 1; | ||
337 | unsigned int timer_grp0 : 1; | ||
338 | unsigned int fifo_out : 1; | ||
339 | unsigned int spu_intr1 : 1; | ||
340 | unsigned int trigger_grp1 : 1; | ||
341 | unsigned int timer_grp1 : 1; | ||
342 | unsigned int fifo_in : 1; | ||
343 | unsigned int spu_intr2 : 1; | ||
344 | unsigned int trigger_grp2 : 1; | ||
345 | unsigned int fifo_out_extra : 1; | ||
346 | unsigned int dmc_out : 1; | ||
347 | unsigned int spu_intr3 : 1; | ||
348 | unsigned int trigger_grp3 : 1; | ||
349 | unsigned int fifo_in_extra : 1; | ||
350 | unsigned int dmc_in : 1; | ||
351 | unsigned int dummy1 : 16; | ||
352 | } reg_iop_sw_mpu_r_intr_grp0; | ||
353 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 | ||
354 | |||
355 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
356 | typedef struct { | ||
357 | unsigned int spu_intr0 : 1; | ||
358 | unsigned int trigger_grp0 : 1; | ||
359 | unsigned int timer_grp0 : 1; | ||
360 | unsigned int fifo_out : 1; | ||
361 | unsigned int spu_intr1 : 1; | ||
362 | unsigned int trigger_grp1 : 1; | ||
363 | unsigned int timer_grp1 : 1; | ||
364 | unsigned int fifo_in : 1; | ||
365 | unsigned int spu_intr2 : 1; | ||
366 | unsigned int trigger_grp2 : 1; | ||
367 | unsigned int fifo_out_extra : 1; | ||
368 | unsigned int dmc_out : 1; | ||
369 | unsigned int spu_intr3 : 1; | ||
370 | unsigned int trigger_grp3 : 1; | ||
371 | unsigned int fifo_in_extra : 1; | ||
372 | unsigned int dmc_in : 1; | ||
373 | unsigned int dummy1 : 16; | ||
374 | } reg_iop_sw_mpu_r_masked_intr_grp0; | ||
375 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 | ||
376 | |||
377 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
378 | typedef struct { | ||
379 | unsigned int spu_intr4 : 1; | ||
380 | unsigned int trigger_grp4 : 1; | ||
381 | unsigned int fifo_out_extra : 1; | ||
382 | unsigned int dmc_out : 1; | ||
383 | unsigned int spu_intr5 : 1; | ||
384 | unsigned int trigger_grp5 : 1; | ||
385 | unsigned int fifo_in_extra : 1; | ||
386 | unsigned int dmc_in : 1; | ||
387 | unsigned int spu_intr6 : 1; | ||
388 | unsigned int trigger_grp6 : 1; | ||
389 | unsigned int timer_grp0 : 1; | ||
390 | unsigned int fifo_out : 1; | ||
391 | unsigned int spu_intr7 : 1; | ||
392 | unsigned int trigger_grp7 : 1; | ||
393 | unsigned int timer_grp1 : 1; | ||
394 | unsigned int fifo_in : 1; | ||
395 | unsigned int dummy1 : 16; | ||
396 | } reg_iop_sw_mpu_rw_intr_grp1_mask; | ||
397 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
398 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
399 | |||
400 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
401 | typedef struct { | ||
402 | unsigned int spu_intr4 : 1; | ||
403 | unsigned int dummy1 : 3; | ||
404 | unsigned int spu_intr5 : 1; | ||
405 | unsigned int dummy2 : 3; | ||
406 | unsigned int spu_intr6 : 1; | ||
407 | unsigned int dummy3 : 3; | ||
408 | unsigned int spu_intr7 : 1; | ||
409 | unsigned int dummy4 : 19; | ||
410 | } reg_iop_sw_mpu_rw_ack_intr_grp1; | ||
411 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
412 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
413 | |||
414 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
415 | typedef struct { | ||
416 | unsigned int spu_intr4 : 1; | ||
417 | unsigned int trigger_grp4 : 1; | ||
418 | unsigned int fifo_out_extra : 1; | ||
419 | unsigned int dmc_out : 1; | ||
420 | unsigned int spu_intr5 : 1; | ||
421 | unsigned int trigger_grp5 : 1; | ||
422 | unsigned int fifo_in_extra : 1; | ||
423 | unsigned int dmc_in : 1; | ||
424 | unsigned int spu_intr6 : 1; | ||
425 | unsigned int trigger_grp6 : 1; | ||
426 | unsigned int timer_grp0 : 1; | ||
427 | unsigned int fifo_out : 1; | ||
428 | unsigned int spu_intr7 : 1; | ||
429 | unsigned int trigger_grp7 : 1; | ||
430 | unsigned int timer_grp1 : 1; | ||
431 | unsigned int fifo_in : 1; | ||
432 | unsigned int dummy1 : 16; | ||
433 | } reg_iop_sw_mpu_r_intr_grp1; | ||
434 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 | ||
435 | |||
436 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
437 | typedef struct { | ||
438 | unsigned int spu_intr4 : 1; | ||
439 | unsigned int trigger_grp4 : 1; | ||
440 | unsigned int fifo_out_extra : 1; | ||
441 | unsigned int dmc_out : 1; | ||
442 | unsigned int spu_intr5 : 1; | ||
443 | unsigned int trigger_grp5 : 1; | ||
444 | unsigned int fifo_in_extra : 1; | ||
445 | unsigned int dmc_in : 1; | ||
446 | unsigned int spu_intr6 : 1; | ||
447 | unsigned int trigger_grp6 : 1; | ||
448 | unsigned int timer_grp0 : 1; | ||
449 | unsigned int fifo_out : 1; | ||
450 | unsigned int spu_intr7 : 1; | ||
451 | unsigned int trigger_grp7 : 1; | ||
452 | unsigned int timer_grp1 : 1; | ||
453 | unsigned int fifo_in : 1; | ||
454 | unsigned int dummy1 : 16; | ||
455 | } reg_iop_sw_mpu_r_masked_intr_grp1; | ||
456 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 | ||
457 | |||
458 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
459 | typedef struct { | ||
460 | unsigned int spu_intr8 : 1; | ||
461 | unsigned int trigger_grp0 : 1; | ||
462 | unsigned int timer_grp0 : 1; | ||
463 | unsigned int fifo_out : 1; | ||
464 | unsigned int spu_intr9 : 1; | ||
465 | unsigned int trigger_grp1 : 1; | ||
466 | unsigned int timer_grp1 : 1; | ||
467 | unsigned int fifo_in : 1; | ||
468 | unsigned int spu_intr10 : 1; | ||
469 | unsigned int trigger_grp2 : 1; | ||
470 | unsigned int fifo_out_extra : 1; | ||
471 | unsigned int dmc_out : 1; | ||
472 | unsigned int spu_intr11 : 1; | ||
473 | unsigned int trigger_grp3 : 1; | ||
474 | unsigned int fifo_in_extra : 1; | ||
475 | unsigned int dmc_in : 1; | ||
476 | unsigned int dummy1 : 16; | ||
477 | } reg_iop_sw_mpu_rw_intr_grp2_mask; | ||
478 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
479 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
480 | |||
481 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
482 | typedef struct { | ||
483 | unsigned int spu_intr8 : 1; | ||
484 | unsigned int dummy1 : 3; | ||
485 | unsigned int spu_intr9 : 1; | ||
486 | unsigned int dummy2 : 3; | ||
487 | unsigned int spu_intr10 : 1; | ||
488 | unsigned int dummy3 : 3; | ||
489 | unsigned int spu_intr11 : 1; | ||
490 | unsigned int dummy4 : 19; | ||
491 | } reg_iop_sw_mpu_rw_ack_intr_grp2; | ||
492 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
493 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
494 | |||
495 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
496 | typedef struct { | ||
497 | unsigned int spu_intr8 : 1; | ||
498 | unsigned int trigger_grp0 : 1; | ||
499 | unsigned int timer_grp0 : 1; | ||
500 | unsigned int fifo_out : 1; | ||
501 | unsigned int spu_intr9 : 1; | ||
502 | unsigned int trigger_grp1 : 1; | ||
503 | unsigned int timer_grp1 : 1; | ||
504 | unsigned int fifo_in : 1; | ||
505 | unsigned int spu_intr10 : 1; | ||
506 | unsigned int trigger_grp2 : 1; | ||
507 | unsigned int fifo_out_extra : 1; | ||
508 | unsigned int dmc_out : 1; | ||
509 | unsigned int spu_intr11 : 1; | ||
510 | unsigned int trigger_grp3 : 1; | ||
511 | unsigned int fifo_in_extra : 1; | ||
512 | unsigned int dmc_in : 1; | ||
513 | unsigned int dummy1 : 16; | ||
514 | } reg_iop_sw_mpu_r_intr_grp2; | ||
515 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 | ||
516 | |||
517 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
518 | typedef struct { | ||
519 | unsigned int spu_intr8 : 1; | ||
520 | unsigned int trigger_grp0 : 1; | ||
521 | unsigned int timer_grp0 : 1; | ||
522 | unsigned int fifo_out : 1; | ||
523 | unsigned int spu_intr9 : 1; | ||
524 | unsigned int trigger_grp1 : 1; | ||
525 | unsigned int timer_grp1 : 1; | ||
526 | unsigned int fifo_in : 1; | ||
527 | unsigned int spu_intr10 : 1; | ||
528 | unsigned int trigger_grp2 : 1; | ||
529 | unsigned int fifo_out_extra : 1; | ||
530 | unsigned int dmc_out : 1; | ||
531 | unsigned int spu_intr11 : 1; | ||
532 | unsigned int trigger_grp3 : 1; | ||
533 | unsigned int fifo_in_extra : 1; | ||
534 | unsigned int dmc_in : 1; | ||
535 | unsigned int dummy1 : 16; | ||
536 | } reg_iop_sw_mpu_r_masked_intr_grp2; | ||
537 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 | ||
538 | |||
539 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
540 | typedef struct { | ||
541 | unsigned int spu_intr12 : 1; | ||
542 | unsigned int trigger_grp4 : 1; | ||
543 | unsigned int fifo_out_extra : 1; | ||
544 | unsigned int dmc_out : 1; | ||
545 | unsigned int spu_intr13 : 1; | ||
546 | unsigned int trigger_grp5 : 1; | ||
547 | unsigned int fifo_in_extra : 1; | ||
548 | unsigned int dmc_in : 1; | ||
549 | unsigned int spu_intr14 : 1; | ||
550 | unsigned int trigger_grp6 : 1; | ||
551 | unsigned int timer_grp0 : 1; | ||
552 | unsigned int fifo_out : 1; | ||
553 | unsigned int spu_intr15 : 1; | ||
554 | unsigned int trigger_grp7 : 1; | ||
555 | unsigned int timer_grp1 : 1; | ||
556 | unsigned int fifo_in : 1; | ||
557 | unsigned int dummy1 : 16; | ||
558 | } reg_iop_sw_mpu_rw_intr_grp3_mask; | ||
559 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
560 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
561 | |||
562 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
563 | typedef struct { | ||
564 | unsigned int spu_intr12 : 1; | ||
565 | unsigned int dummy1 : 3; | ||
566 | unsigned int spu_intr13 : 1; | ||
567 | unsigned int dummy2 : 3; | ||
568 | unsigned int spu_intr14 : 1; | ||
569 | unsigned int dummy3 : 3; | ||
570 | unsigned int spu_intr15 : 1; | ||
571 | unsigned int dummy4 : 19; | ||
572 | } reg_iop_sw_mpu_rw_ack_intr_grp3; | ||
573 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
574 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
575 | |||
576 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
577 | typedef struct { | ||
578 | unsigned int spu_intr12 : 1; | ||
579 | unsigned int trigger_grp4 : 1; | ||
580 | unsigned int fifo_out_extra : 1; | ||
581 | unsigned int dmc_out : 1; | ||
582 | unsigned int spu_intr13 : 1; | ||
583 | unsigned int trigger_grp5 : 1; | ||
584 | unsigned int fifo_in_extra : 1; | ||
585 | unsigned int dmc_in : 1; | ||
586 | unsigned int spu_intr14 : 1; | ||
587 | unsigned int trigger_grp6 : 1; | ||
588 | unsigned int timer_grp0 : 1; | ||
589 | unsigned int fifo_out : 1; | ||
590 | unsigned int spu_intr15 : 1; | ||
591 | unsigned int trigger_grp7 : 1; | ||
592 | unsigned int timer_grp1 : 1; | ||
593 | unsigned int fifo_in : 1; | ||
594 | unsigned int dummy1 : 16; | ||
595 | } reg_iop_sw_mpu_r_intr_grp3; | ||
596 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 | ||
597 | |||
598 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
599 | typedef struct { | ||
600 | unsigned int spu_intr12 : 1; | ||
601 | unsigned int trigger_grp4 : 1; | ||
602 | unsigned int fifo_out_extra : 1; | ||
603 | unsigned int dmc_out : 1; | ||
604 | unsigned int spu_intr13 : 1; | ||
605 | unsigned int trigger_grp5 : 1; | ||
606 | unsigned int fifo_in_extra : 1; | ||
607 | unsigned int dmc_in : 1; | ||
608 | unsigned int spu_intr14 : 1; | ||
609 | unsigned int trigger_grp6 : 1; | ||
610 | unsigned int timer_grp0 : 1; | ||
611 | unsigned int fifo_out : 1; | ||
612 | unsigned int spu_intr15 : 1; | ||
613 | unsigned int trigger_grp7 : 1; | ||
614 | unsigned int timer_grp1 : 1; | ||
615 | unsigned int fifo_in : 1; | ||
616 | unsigned int dummy1 : 16; | ||
617 | } reg_iop_sw_mpu_r_masked_intr_grp3; | ||
618 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 | ||
619 | |||
620 | |||
621 | /* Constants */ | ||
622 | enum { | ||
623 | regk_iop_sw_mpu_copy = 0x00000000, | ||
624 | regk_iop_sw_mpu_cpu = 0x00000000, | ||
625 | regk_iop_sw_mpu_mpu = 0x00000001, | ||
626 | regk_iop_sw_mpu_no = 0x00000000, | ||
627 | regk_iop_sw_mpu_nop = 0x00000000, | ||
628 | regk_iop_sw_mpu_rd = 0x00000002, | ||
629 | regk_iop_sw_mpu_reg_copy = 0x00000001, | ||
630 | regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, | ||
631 | regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
632 | regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
633 | regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, | ||
634 | regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, | ||
635 | regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
636 | regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
637 | regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, | ||
638 | regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, | ||
639 | regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, | ||
640 | regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, | ||
641 | regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, | ||
642 | regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, | ||
643 | regk_iop_sw_mpu_set = 0x00000001, | ||
644 | regk_iop_sw_mpu_spu = 0x00000002, | ||
645 | regk_iop_sw_mpu_wr = 0x00000003, | ||
646 | regk_iop_sw_mpu_yes = 0x00000001 | ||
647 | }; | ||
648 | #endif /* __iop_sw_mpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 00000000000..c8560b865a1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h | |||
@@ -0,0 +1,441 @@ | |||
1 | #ifndef __iop_sw_spu_defs_h | ||
2 | #define __iop_sw_spu_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sw_spu.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_sw_spu */ | ||
83 | |||
84 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
85 | typedef unsigned int reg_iop_sw_spu_r_mpu_trace; | ||
86 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 | ||
87 | |||
88 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
89 | typedef struct { | ||
90 | unsigned int keep_owner : 1; | ||
91 | unsigned int cmd : 2; | ||
92 | unsigned int size : 3; | ||
93 | unsigned int wr_spu_mem : 1; | ||
94 | unsigned int dummy1 : 25; | ||
95 | } reg_iop_sw_spu_rw_mc_ctrl; | ||
96 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
97 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
98 | |||
99 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
100 | typedef struct { | ||
101 | unsigned int val : 32; | ||
102 | } reg_iop_sw_spu_rw_mc_data; | ||
103 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 | ||
104 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 | ||
105 | |||
106 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
107 | typedef unsigned int reg_iop_sw_spu_rw_mc_addr; | ||
108 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
109 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
110 | |||
111 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
112 | typedef unsigned int reg_iop_sw_spu_rs_mc_data; | ||
113 | #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 | ||
114 | |||
115 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
116 | typedef unsigned int reg_iop_sw_spu_r_mc_data; | ||
117 | #define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 | ||
118 | |||
119 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
120 | typedef struct { | ||
121 | unsigned int busy_cpu : 1; | ||
122 | unsigned int busy_mpu : 1; | ||
123 | unsigned int busy_spu : 1; | ||
124 | unsigned int owned_by_cpu : 1; | ||
125 | unsigned int owned_by_mpu : 1; | ||
126 | unsigned int owned_by_spu : 1; | ||
127 | unsigned int dummy1 : 26; | ||
128 | } reg_iop_sw_spu_r_mc_stat; | ||
129 | #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 | ||
130 | |||
131 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
132 | typedef struct { | ||
133 | unsigned int byte0 : 8; | ||
134 | unsigned int byte1 : 8; | ||
135 | unsigned int byte2 : 8; | ||
136 | unsigned int byte3 : 8; | ||
137 | } reg_iop_sw_spu_rw_bus_clr_mask; | ||
138 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
139 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
140 | |||
141 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
142 | typedef struct { | ||
143 | unsigned int byte0 : 8; | ||
144 | unsigned int byte1 : 8; | ||
145 | unsigned int byte2 : 8; | ||
146 | unsigned int byte3 : 8; | ||
147 | } reg_iop_sw_spu_rw_bus_set_mask; | ||
148 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
149 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
150 | |||
151 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
152 | typedef struct { | ||
153 | unsigned int byte0 : 1; | ||
154 | unsigned int byte1 : 1; | ||
155 | unsigned int byte2 : 1; | ||
156 | unsigned int byte3 : 1; | ||
157 | unsigned int dummy1 : 28; | ||
158 | } reg_iop_sw_spu_rw_bus_oe_clr_mask; | ||
159 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
160 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
161 | |||
162 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
163 | typedef struct { | ||
164 | unsigned int byte0 : 1; | ||
165 | unsigned int byte1 : 1; | ||
166 | unsigned int byte2 : 1; | ||
167 | unsigned int byte3 : 1; | ||
168 | unsigned int dummy1 : 28; | ||
169 | } reg_iop_sw_spu_rw_bus_oe_set_mask; | ||
170 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
171 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
172 | |||
173 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
174 | typedef unsigned int reg_iop_sw_spu_r_bus_in; | ||
175 | #define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 | ||
176 | |||
177 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
178 | typedef struct { | ||
179 | unsigned int val : 32; | ||
180 | } reg_iop_sw_spu_rw_gio_clr_mask; | ||
181 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
182 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
183 | |||
184 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
185 | typedef struct { | ||
186 | unsigned int val : 32; | ||
187 | } reg_iop_sw_spu_rw_gio_set_mask; | ||
188 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
189 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
190 | |||
191 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
192 | typedef struct { | ||
193 | unsigned int val : 32; | ||
194 | } reg_iop_sw_spu_rw_gio_oe_clr_mask; | ||
195 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
196 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
197 | |||
198 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
199 | typedef struct { | ||
200 | unsigned int val : 32; | ||
201 | } reg_iop_sw_spu_rw_gio_oe_set_mask; | ||
202 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
203 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
204 | |||
205 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
206 | typedef unsigned int reg_iop_sw_spu_r_gio_in; | ||
207 | #define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 | ||
208 | |||
209 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
210 | typedef struct { | ||
211 | unsigned int byte0 : 8; | ||
212 | unsigned int byte1 : 8; | ||
213 | unsigned int dummy1 : 16; | ||
214 | } reg_iop_sw_spu_rw_bus_clr_mask_lo; | ||
215 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
216 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
217 | |||
218 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
219 | typedef struct { | ||
220 | unsigned int byte2 : 8; | ||
221 | unsigned int byte3 : 8; | ||
222 | unsigned int dummy1 : 16; | ||
223 | } reg_iop_sw_spu_rw_bus_clr_mask_hi; | ||
224 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
225 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
226 | |||
227 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
228 | typedef struct { | ||
229 | unsigned int byte0 : 8; | ||
230 | unsigned int byte1 : 8; | ||
231 | unsigned int dummy1 : 16; | ||
232 | } reg_iop_sw_spu_rw_bus_set_mask_lo; | ||
233 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
234 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
235 | |||
236 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
237 | typedef struct { | ||
238 | unsigned int byte2 : 8; | ||
239 | unsigned int byte3 : 8; | ||
240 | unsigned int dummy1 : 16; | ||
241 | } reg_iop_sw_spu_rw_bus_set_mask_hi; | ||
242 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
243 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
244 | |||
245 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
246 | typedef struct { | ||
247 | unsigned int val : 16; | ||
248 | unsigned int dummy1 : 16; | ||
249 | } reg_iop_sw_spu_rw_gio_clr_mask_lo; | ||
250 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
251 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
252 | |||
253 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
254 | typedef struct { | ||
255 | unsigned int val : 16; | ||
256 | unsigned int dummy1 : 16; | ||
257 | } reg_iop_sw_spu_rw_gio_clr_mask_hi; | ||
258 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
259 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
260 | |||
261 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
262 | typedef struct { | ||
263 | unsigned int val : 16; | ||
264 | unsigned int dummy1 : 16; | ||
265 | } reg_iop_sw_spu_rw_gio_set_mask_lo; | ||
266 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
267 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
268 | |||
269 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
270 | typedef struct { | ||
271 | unsigned int val : 16; | ||
272 | unsigned int dummy1 : 16; | ||
273 | } reg_iop_sw_spu_rw_gio_set_mask_hi; | ||
274 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
275 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
276 | |||
277 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
278 | typedef struct { | ||
279 | unsigned int val : 16; | ||
280 | unsigned int dummy1 : 16; | ||
281 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; | ||
282 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
283 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
284 | |||
285 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
286 | typedef struct { | ||
287 | unsigned int val : 16; | ||
288 | unsigned int dummy1 : 16; | ||
289 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; | ||
290 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
291 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
292 | |||
293 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
294 | typedef struct { | ||
295 | unsigned int val : 16; | ||
296 | unsigned int dummy1 : 16; | ||
297 | } reg_iop_sw_spu_rw_gio_oe_set_mask_lo; | ||
298 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
299 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
300 | |||
301 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
302 | typedef struct { | ||
303 | unsigned int val : 16; | ||
304 | unsigned int dummy1 : 16; | ||
305 | } reg_iop_sw_spu_rw_gio_oe_set_mask_hi; | ||
306 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
307 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
308 | |||
309 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
310 | typedef struct { | ||
311 | unsigned int intr0 : 1; | ||
312 | unsigned int intr1 : 1; | ||
313 | unsigned int intr2 : 1; | ||
314 | unsigned int intr3 : 1; | ||
315 | unsigned int intr4 : 1; | ||
316 | unsigned int intr5 : 1; | ||
317 | unsigned int intr6 : 1; | ||
318 | unsigned int intr7 : 1; | ||
319 | unsigned int intr8 : 1; | ||
320 | unsigned int intr9 : 1; | ||
321 | unsigned int intr10 : 1; | ||
322 | unsigned int intr11 : 1; | ||
323 | unsigned int intr12 : 1; | ||
324 | unsigned int intr13 : 1; | ||
325 | unsigned int intr14 : 1; | ||
326 | unsigned int intr15 : 1; | ||
327 | unsigned int dummy1 : 16; | ||
328 | } reg_iop_sw_spu_rw_cpu_intr; | ||
329 | #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
330 | #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
331 | |||
332 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
333 | typedef struct { | ||
334 | unsigned int intr0 : 1; | ||
335 | unsigned int intr1 : 1; | ||
336 | unsigned int intr2 : 1; | ||
337 | unsigned int intr3 : 1; | ||
338 | unsigned int intr4 : 1; | ||
339 | unsigned int intr5 : 1; | ||
340 | unsigned int intr6 : 1; | ||
341 | unsigned int intr7 : 1; | ||
342 | unsigned int intr8 : 1; | ||
343 | unsigned int intr9 : 1; | ||
344 | unsigned int intr10 : 1; | ||
345 | unsigned int intr11 : 1; | ||
346 | unsigned int intr12 : 1; | ||
347 | unsigned int intr13 : 1; | ||
348 | unsigned int intr14 : 1; | ||
349 | unsigned int intr15 : 1; | ||
350 | unsigned int dummy1 : 16; | ||
351 | } reg_iop_sw_spu_r_cpu_intr; | ||
352 | #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 | ||
353 | |||
354 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
355 | typedef struct { | ||
356 | unsigned int trigger_grp0 : 1; | ||
357 | unsigned int trigger_grp1 : 1; | ||
358 | unsigned int trigger_grp2 : 1; | ||
359 | unsigned int trigger_grp3 : 1; | ||
360 | unsigned int trigger_grp4 : 1; | ||
361 | unsigned int trigger_grp5 : 1; | ||
362 | unsigned int trigger_grp6 : 1; | ||
363 | unsigned int trigger_grp7 : 1; | ||
364 | unsigned int timer_grp0 : 1; | ||
365 | unsigned int timer_grp1 : 1; | ||
366 | unsigned int fifo_out : 1; | ||
367 | unsigned int fifo_out_extra : 1; | ||
368 | unsigned int fifo_in : 1; | ||
369 | unsigned int fifo_in_extra : 1; | ||
370 | unsigned int dmc_out : 1; | ||
371 | unsigned int dmc_in : 1; | ||
372 | unsigned int dummy1 : 16; | ||
373 | } reg_iop_sw_spu_r_hw_intr; | ||
374 | #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 | ||
375 | |||
376 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
377 | typedef struct { | ||
378 | unsigned int intr0 : 1; | ||
379 | unsigned int intr1 : 1; | ||
380 | unsigned int intr2 : 1; | ||
381 | unsigned int intr3 : 1; | ||
382 | unsigned int intr4 : 1; | ||
383 | unsigned int intr5 : 1; | ||
384 | unsigned int intr6 : 1; | ||
385 | unsigned int intr7 : 1; | ||
386 | unsigned int intr8 : 1; | ||
387 | unsigned int intr9 : 1; | ||
388 | unsigned int intr10 : 1; | ||
389 | unsigned int intr11 : 1; | ||
390 | unsigned int intr12 : 1; | ||
391 | unsigned int intr13 : 1; | ||
392 | unsigned int intr14 : 1; | ||
393 | unsigned int intr15 : 1; | ||
394 | unsigned int dummy1 : 16; | ||
395 | } reg_iop_sw_spu_rw_mpu_intr; | ||
396 | #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
397 | #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
398 | |||
399 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
400 | typedef struct { | ||
401 | unsigned int intr0 : 1; | ||
402 | unsigned int intr1 : 1; | ||
403 | unsigned int intr2 : 1; | ||
404 | unsigned int intr3 : 1; | ||
405 | unsigned int intr4 : 1; | ||
406 | unsigned int intr5 : 1; | ||
407 | unsigned int intr6 : 1; | ||
408 | unsigned int intr7 : 1; | ||
409 | unsigned int intr8 : 1; | ||
410 | unsigned int intr9 : 1; | ||
411 | unsigned int intr10 : 1; | ||
412 | unsigned int intr11 : 1; | ||
413 | unsigned int intr12 : 1; | ||
414 | unsigned int intr13 : 1; | ||
415 | unsigned int intr14 : 1; | ||
416 | unsigned int intr15 : 1; | ||
417 | unsigned int dummy1 : 16; | ||
418 | } reg_iop_sw_spu_r_mpu_intr; | ||
419 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 | ||
420 | |||
421 | |||
422 | /* Constants */ | ||
423 | enum { | ||
424 | regk_iop_sw_spu_copy = 0x00000000, | ||
425 | regk_iop_sw_spu_no = 0x00000000, | ||
426 | regk_iop_sw_spu_nop = 0x00000000, | ||
427 | regk_iop_sw_spu_rd = 0x00000002, | ||
428 | regk_iop_sw_spu_reg_copy = 0x00000001, | ||
429 | regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, | ||
430 | regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
431 | regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, | ||
432 | regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, | ||
433 | regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, | ||
434 | regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
435 | regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, | ||
436 | regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, | ||
437 | regk_iop_sw_spu_set = 0x00000001, | ||
438 | regk_iop_sw_spu_wr = 0x00000003, | ||
439 | regk_iop_sw_spu_yes = 0x00000001 | ||
440 | }; | ||
441 | #endif /* __iop_sw_spu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h new file mode 100644 index 00000000000..20de425e652 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h | |||
@@ -0,0 +1,96 @@ | |||
1 | #ifndef __iop_version_defs_h | ||
2 | #define __iop_version_defs_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_version.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | /* Main access macros */ | ||
14 | #ifndef REG_RD | ||
15 | #define REG_RD( scope, inst, reg ) \ | ||
16 | REG_READ( reg_##scope##_##reg, \ | ||
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_WR | ||
21 | #define REG_WR( scope, inst, reg, val ) \ | ||
22 | REG_WRITE( reg_##scope##_##reg, \ | ||
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_RD_VECT | ||
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
28 | REG_READ( reg_##scope##_##reg, \ | ||
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
30 | (index) * STRIDE_##scope##_##reg ) | ||
31 | #endif | ||
32 | |||
33 | #ifndef REG_WR_VECT | ||
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
35 | REG_WRITE( reg_##scope##_##reg, \ | ||
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_RD_INT | ||
41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_WR_INT | ||
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
48 | #endif | ||
49 | |||
50 | #ifndef REG_RD_INT_VECT | ||
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
53 | (index) * STRIDE_##scope##_##reg ) | ||
54 | #endif | ||
55 | |||
56 | #ifndef REG_WR_INT_VECT | ||
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
60 | #endif | ||
61 | |||
62 | #ifndef REG_TYPE_CONV | ||
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
65 | #endif | ||
66 | |||
67 | #ifndef reg_page_size | ||
68 | #define reg_page_size 8192 | ||
69 | #endif | ||
70 | |||
71 | #ifndef REG_ADDR | ||
72 | #define REG_ADDR( scope, inst, reg ) \ | ||
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
74 | #endif | ||
75 | |||
76 | #ifndef REG_ADDR_VECT | ||
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
79 | (index) * STRIDE_##scope##_##reg ) | ||
80 | #endif | ||
81 | |||
82 | /* C-code for register scope iop_version */ | ||
83 | |||
84 | /* Register r_version, scope iop_version, type r */ | ||
85 | typedef struct { | ||
86 | unsigned int nr : 8; | ||
87 | unsigned int dummy1 : 24; | ||
88 | } reg_iop_version_r_version; | ||
89 | #define REG_RD_ADDR_iop_version_r_version 0 | ||
90 | |||
91 | |||
92 | /* Constants */ | ||
93 | enum { | ||
94 | regk_iop_version_v2_0 = 0x00000002 | ||
95 | }; | ||
96 | #endif /* __iop_version_defs_h */ | ||