diff options
Diffstat (limited to 'include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h')
-rw-r--r-- | include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h | 276 |
1 files changed, 276 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 00000000000..399bd656406 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h | |||
@@ -0,0 +1,276 @@ | |||
1 | #ifndef __iop_sap_out_defs_asm_h | ||
2 | #define __iop_sap_out_defs_asm_h | ||
3 | |||
4 | /* | ||
5 | * This file is autogenerated from | ||
6 | * file: iop_sap_out.r | ||
7 | * | ||
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r | ||
9 | * Any changes here will be lost. | ||
10 | * | ||
11 | * -*- buffer-read-only: t -*- | ||
12 | */ | ||
13 | |||
14 | #ifndef REG_FIELD | ||
15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
18 | #endif | ||
19 | |||
20 | #ifndef REG_STATE | ||
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
24 | #endif | ||
25 | |||
26 | #ifndef REG_MASK | ||
27 | #define REG_MASK( scope, reg, field ) \ | ||
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
30 | #endif | ||
31 | |||
32 | #ifndef REG_LSB | ||
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
34 | #endif | ||
35 | |||
36 | #ifndef REG_BIT | ||
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
38 | #endif | ||
39 | |||
40 | #ifndef REG_ADDR | ||
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
43 | #endif | ||
44 | |||
45 | #ifndef REG_ADDR_VECT | ||
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
48 | STRIDE_##scope##_##reg ) | ||
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
50 | ((inst) + offs + (index) * stride) | ||
51 | #endif | ||
52 | |||
53 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
54 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 | ||
55 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 | ||
56 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 | ||
57 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 | ||
58 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 | ||
59 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 | ||
60 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 | ||
61 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 | ||
62 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 | ||
63 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 | ||
64 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 | ||
65 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 | ||
66 | #define reg_iop_sap_out_rw_gen_gated_offset 0 | ||
67 | |||
68 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
69 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 | ||
70 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 | ||
71 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 | ||
72 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 | ||
73 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 | ||
74 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 | ||
75 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 | ||
76 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 | ||
77 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 | ||
78 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 | ||
79 | #define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 | ||
80 | #define reg_iop_sap_out_rw_bus___byte0_delay___width 1 | ||
81 | #define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 | ||
82 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 | ||
83 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 | ||
84 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 | ||
85 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 | ||
86 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 | ||
87 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 | ||
88 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 | ||
89 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 | ||
90 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 | ||
91 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 | ||
92 | #define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 | ||
93 | #define reg_iop_sap_out_rw_bus___byte1_delay___width 1 | ||
94 | #define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 | ||
95 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 | ||
96 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 | ||
97 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 | ||
98 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 | ||
99 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 | ||
100 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 | ||
101 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 | ||
102 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 | ||
103 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 | ||
104 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 | ||
105 | #define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 | ||
106 | #define reg_iop_sap_out_rw_bus___byte2_delay___width 1 | ||
107 | #define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 | ||
108 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 | ||
109 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 | ||
110 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 | ||
111 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 | ||
112 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 | ||
113 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 | ||
114 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 | ||
115 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 | ||
116 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 | ||
117 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 | ||
118 | #define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 | ||
119 | #define reg_iop_sap_out_rw_bus___byte3_delay___width 1 | ||
120 | #define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 | ||
121 | #define reg_iop_sap_out_rw_bus_offset 4 | ||
122 | |||
123 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
124 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 | ||
125 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 | ||
126 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 | ||
127 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 | ||
128 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 | ||
129 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 | ||
130 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 | ||
131 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 | ||
132 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 | ||
133 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 | ||
134 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 | ||
135 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 | ||
136 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 | ||
137 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 | ||
138 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 | ||
139 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 | ||
140 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 | ||
141 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 | ||
142 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 | ||
143 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 | ||
144 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 | ||
145 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 | ||
146 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 | ||
147 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 | ||
148 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 | ||
149 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 | ||
150 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 | ||
151 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 | ||
152 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 | ||
153 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 | ||
154 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 | ||
155 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 | ||
156 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 | ||
157 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 | ||
158 | #define reg_iop_sap_out_rw_bus_lo_oe_offset 8 | ||
159 | |||
160 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
161 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 | ||
162 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 | ||
163 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 | ||
164 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 | ||
165 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 | ||
166 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 | ||
167 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 | ||
168 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 | ||
169 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 | ||
170 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 | ||
171 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 | ||
172 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 | ||
173 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 | ||
174 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 | ||
175 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 | ||
176 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 | ||
177 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 | ||
178 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 | ||
179 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 | ||
180 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 | ||
181 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 | ||
182 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 | ||
183 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 | ||
184 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 | ||
185 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 | ||
186 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 | ||
187 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 | ||
188 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 | ||
189 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 | ||
190 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 | ||
191 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 | ||
192 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 | ||
193 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 | ||
194 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 | ||
195 | #define reg_iop_sap_out_rw_bus_hi_oe_offset 12 | ||
196 | |||
197 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
198 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
199 | #define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 | ||
200 | #define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 | ||
201 | #define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 | ||
202 | #define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 | ||
203 | #define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 | ||
204 | #define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 | ||
205 | #define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 | ||
206 | #define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 | ||
207 | #define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 | ||
208 | #define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 | ||
209 | #define reg_iop_sap_out_rw_gio___out_delay___lsb 7 | ||
210 | #define reg_iop_sap_out_rw_gio___out_delay___width 1 | ||
211 | #define reg_iop_sap_out_rw_gio___out_delay___bit 7 | ||
212 | #define reg_iop_sap_out_rw_gio___out_logic___lsb 8 | ||
213 | #define reg_iop_sap_out_rw_gio___out_logic___width 2 | ||
214 | #define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 | ||
215 | #define reg_iop_sap_out_rw_gio___out_logic_src___width 2 | ||
216 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 | ||
217 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 | ||
218 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 | ||
219 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 | ||
220 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 | ||
221 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 | ||
222 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 | ||
223 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 | ||
224 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 | ||
225 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 | ||
226 | #define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 | ||
227 | #define reg_iop_sap_out_rw_gio___oe_delay___width 1 | ||
228 | #define reg_iop_sap_out_rw_gio___oe_delay___bit 19 | ||
229 | #define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 | ||
230 | #define reg_iop_sap_out_rw_gio___oe_logic___width 2 | ||
231 | #define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 | ||
232 | #define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 | ||
233 | #define reg_iop_sap_out_rw_gio_offset 16 | ||
234 | |||
235 | |||
236 | /* Constants */ | ||
237 | #define regk_iop_sap_out_always 0x00000001 | ||
238 | #define regk_iop_sap_out_and 0x00000002 | ||
239 | #define regk_iop_sap_out_clk0 0x00000000 | ||
240 | #define regk_iop_sap_out_clk1 0x00000001 | ||
241 | #define regk_iop_sap_out_clk12 0x00000004 | ||
242 | #define regk_iop_sap_out_clk200 0x00000000 | ||
243 | #define regk_iop_sap_out_ext 0x00000002 | ||
244 | #define regk_iop_sap_out_gated 0x00000003 | ||
245 | #define regk_iop_sap_out_gio0 0x00000000 | ||
246 | #define regk_iop_sap_out_gio1 0x00000000 | ||
247 | #define regk_iop_sap_out_gio16 0x00000002 | ||
248 | #define regk_iop_sap_out_gio17 0x00000002 | ||
249 | #define regk_iop_sap_out_gio24 0x00000003 | ||
250 | #define regk_iop_sap_out_gio25 0x00000003 | ||
251 | #define regk_iop_sap_out_gio8 0x00000001 | ||
252 | #define regk_iop_sap_out_gio9 0x00000001 | ||
253 | #define regk_iop_sap_out_gio_out10 0x00000005 | ||
254 | #define regk_iop_sap_out_gio_out18 0x00000006 | ||
255 | #define regk_iop_sap_out_gio_out2 0x00000004 | ||
256 | #define regk_iop_sap_out_gio_out26 0x00000007 | ||
257 | #define regk_iop_sap_out_inv 0x00000001 | ||
258 | #define regk_iop_sap_out_nand 0x00000003 | ||
259 | #define regk_iop_sap_out_no 0x00000000 | ||
260 | #define regk_iop_sap_out_none 0x00000000 | ||
261 | #define regk_iop_sap_out_one 0x00000001 | ||
262 | #define regk_iop_sap_out_rw_bus_default 0x00000000 | ||
263 | #define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 | ||
264 | #define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 | ||
265 | #define regk_iop_sap_out_rw_gen_gated_default 0x00000000 | ||
266 | #define regk_iop_sap_out_rw_gio_default 0x00000000 | ||
267 | #define regk_iop_sap_out_rw_gio_size 0x00000020 | ||
268 | #define regk_iop_sap_out_spu_gio6 0x00000002 | ||
269 | #define regk_iop_sap_out_spu_gio7 0x00000003 | ||
270 | #define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 | ||
271 | #define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 | ||
272 | #define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 | ||
273 | #define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 | ||
274 | #define regk_iop_sap_out_tmr200 0x00000001 | ||
275 | #define regk_iop_sap_out_yes 0x00000001 | ||
276 | #endif /* __iop_sap_out_defs_asm_h */ | ||