diff options
author | Timo von Holtz <tvh@informatik.uni-kiel.de> | 2011-02-01 13:28:46 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-04 16:01:02 -0500 |
commit | 0838b87cae7e81e497218b5eba3c8e9ca6f3ddbe (patch) | |
tree | ca36e6718b437c78158170cbf442c832078e7b37 /drivers | |
parent | 404dc5f3f475ce3598d0e295883a28efafb90ac5 (diff) |
Staging: rts_pstor: fixed some brace code styling issues
Fixed all brace coding style issues in the following files:
drivers/staging/rts_pstor/rtsx_card.h
drivers/staging/rts_pstor/spi.c
drivers/staging/rts_pstor/trace.h
drivers/staging/rts_pstor/xd.c
Signed-off-by: Timo von Holtz <tvh@informatik.uni-kiel.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/staging/rts_pstor/rtsx_card.h | 10 | ||||
-rw-r--r-- | drivers/staging/rts_pstor/spi.c | 109 | ||||
-rw-r--r-- | drivers/staging/rts_pstor/trace.h | 7 | ||||
-rw-r--r-- | drivers/staging/rts_pstor/xd.c | 301 |
4 files changed, 150 insertions, 277 deletions
diff --git a/drivers/staging/rts_pstor/rtsx_card.h b/drivers/staging/rts_pstor/rtsx_card.h index 5a0e167a15d..3f727767620 100644 --- a/drivers/staging/rts_pstor/rtsx_card.h +++ b/drivers/staging/rts_pstor/rtsx_card.h | |||
@@ -1035,11 +1035,10 @@ static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun) | |||
1035 | #ifdef SUPPORT_SD_LOCK | 1035 | #ifdef SUPPORT_SD_LOCK |
1036 | struct sd_info *sd_card = &(chip->sd_card); | 1036 | struct sd_info *sd_card = &(chip->sd_card); |
1037 | 1037 | ||
1038 | if ((get_lun_card(chip, lun) == SD_CARD) && (sd_card->sd_lock_status & SD_LOCKED)) { | 1038 | if ((get_lun_card(chip, lun) == SD_CARD) && (sd_card->sd_lock_status & SD_LOCKED)) |
1039 | return 0; | 1039 | return 0; |
1040 | } else { | 1040 | else |
1041 | return chip->capacity[lun]; | 1041 | return chip->capacity[lun]; |
1042 | } | ||
1043 | #else | 1042 | #else |
1044 | return chip->capacity[lun]; | 1043 | return chip->capacity[lun]; |
1045 | #endif | 1044 | #endif |
@@ -1049,11 +1048,10 @@ static inline int switch_clock(struct rtsx_chip *chip, int clk) | |||
1049 | { | 1048 | { |
1050 | int retval = 0; | 1049 | int retval = 0; |
1051 | 1050 | ||
1052 | if (chip->asic_code) { | 1051 | if (chip->asic_code) |
1053 | retval = switch_ssc_clock(chip, clk); | 1052 | retval = switch_ssc_clock(chip, clk); |
1054 | } else { | 1053 | else |
1055 | retval = switch_normal_clock(chip, clk); | 1054 | retval = switch_normal_clock(chip, clk); |
1056 | } | ||
1057 | 1055 | ||
1058 | return retval; | 1056 | return retval; |
1059 | } | 1057 | } |
diff --git a/drivers/staging/rts_pstor/spi.c b/drivers/staging/rts_pstor/spi.c index 84e0af42ca1..e0682004756 100644 --- a/drivers/staging/rts_pstor/spi.c +++ b/drivers/staging/rts_pstor/spi.c | |||
@@ -55,14 +55,12 @@ static int spi_set_init_para(struct rtsx_chip *chip) | |||
55 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div)); | 55 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div)); |
56 | 56 | ||
57 | retval = switch_clock(chip, spi->spi_clock); | 57 | retval = switch_clock(chip, spi->spi_clock); |
58 | if (retval != STATUS_SUCCESS) { | 58 | if (retval != STATUS_SUCCESS) |
59 | TRACE_RET(chip, STATUS_FAIL); | 59 | TRACE_RET(chip, STATUS_FAIL); |
60 | } | ||
61 | 60 | ||
62 | retval = select_card(chip, SPI_CARD); | 61 | retval = select_card(chip, SPI_CARD); |
63 | if (retval != STATUS_SUCCESS) { | 62 | if (retval != STATUS_SUCCESS) |
64 | TRACE_RET(chip, STATUS_FAIL); | 63 | TRACE_RET(chip, STATUS_FAIL); |
65 | } | ||
66 | 64 | ||
67 | RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); | 65 | RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); |
68 | RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); | 66 | RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); |
@@ -70,9 +68,8 @@ static int spi_set_init_para(struct rtsx_chip *chip) | |||
70 | wait_timeout(10); | 68 | wait_timeout(10); |
71 | 69 | ||
72 | retval = spi_init(chip); | 70 | retval = spi_init(chip); |
73 | if (retval != STATUS_SUCCESS) { | 71 | if (retval != STATUS_SUCCESS) |
74 | TRACE_RET(chip, STATUS_FAIL); | 72 | TRACE_RET(chip, STATUS_FAIL); |
75 | } | ||
76 | 73 | ||
77 | return STATUS_SUCCESS; | 74 | return STATUS_SUCCESS; |
78 | } | 75 | } |
@@ -197,24 +194,21 @@ static int spi_init_eeprom(struct rtsx_chip *chip) | |||
197 | int retval; | 194 | int retval; |
198 | int clk; | 195 | int clk; |
199 | 196 | ||
200 | if (chip->asic_code) { | 197 | if (chip->asic_code) |
201 | clk = 30; | 198 | clk = 30; |
202 | } else { | 199 | else |
203 | clk = CLK_30; | 200 | clk = CLK_30; |
204 | } | ||
205 | 201 | ||
206 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); | 202 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); |
207 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); | 203 | RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); |
208 | 204 | ||
209 | retval = switch_clock(chip, clk); | 205 | retval = switch_clock(chip, clk); |
210 | if (retval != STATUS_SUCCESS) { | 206 | if (retval != STATUS_SUCCESS) |
211 | TRACE_RET(chip, STATUS_FAIL); | 207 | TRACE_RET(chip, STATUS_FAIL); |
212 | } | ||
213 | 208 | ||
214 | retval = select_card(chip, SPI_CARD); | 209 | retval = select_card(chip, SPI_CARD); |
215 | if (retval != STATUS_SUCCESS) { | 210 | if (retval != STATUS_SUCCESS) |
216 | TRACE_RET(chip, STATUS_FAIL); | 211 | TRACE_RET(chip, STATUS_FAIL); |
217 | } | ||
218 | 212 | ||
219 | RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); | 213 | RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); |
220 | RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); | 214 | RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); |
@@ -239,9 +233,8 @@ int spi_eeprom_program_enable(struct rtsx_chip *chip) | |||
239 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); | 233 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); |
240 | 234 | ||
241 | retval = rtsx_send_cmd(chip, 0, 100); | 235 | retval = rtsx_send_cmd(chip, 0, 100); |
242 | if (retval < 0) { | 236 | if (retval < 0) |
243 | TRACE_RET(chip, STATUS_FAIL); | 237 | TRACE_RET(chip, STATUS_FAIL); |
244 | } | ||
245 | 238 | ||
246 | return STATUS_SUCCESS; | 239 | return STATUS_SUCCESS; |
247 | } | 240 | } |
@@ -251,14 +244,12 @@ int spi_erase_eeprom_chip(struct rtsx_chip *chip) | |||
251 | int retval; | 244 | int retval; |
252 | 245 | ||
253 | retval = spi_init_eeprom(chip); | 246 | retval = spi_init_eeprom(chip); |
254 | if (retval != STATUS_SUCCESS) { | 247 | if (retval != STATUS_SUCCESS) |
255 | TRACE_RET(chip, STATUS_FAIL); | 248 | TRACE_RET(chip, STATUS_FAIL); |
256 | } | ||
257 | 249 | ||
258 | retval = spi_eeprom_program_enable(chip); | 250 | retval = spi_eeprom_program_enable(chip); |
259 | if (retval != STATUS_SUCCESS) { | 251 | if (retval != STATUS_SUCCESS) |
260 | TRACE_RET(chip, STATUS_FAIL); | 252 | TRACE_RET(chip, STATUS_FAIL); |
261 | } | ||
262 | 253 | ||
263 | rtsx_init_cmd(chip); | 254 | rtsx_init_cmd(chip); |
264 | 255 | ||
@@ -270,9 +261,8 @@ int spi_erase_eeprom_chip(struct rtsx_chip *chip) | |||
270 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); | 261 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); |
271 | 262 | ||
272 | retval = rtsx_send_cmd(chip, 0, 100); | 263 | retval = rtsx_send_cmd(chip, 0, 100); |
273 | if (retval < 0) { | 264 | if (retval < 0) |
274 | TRACE_RET(chip, STATUS_FAIL); | 265 | TRACE_RET(chip, STATUS_FAIL); |
275 | } | ||
276 | 266 | ||
277 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); | 267 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); |
278 | 268 | ||
@@ -284,14 +274,12 @@ int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) | |||
284 | int retval; | 274 | int retval; |
285 | 275 | ||
286 | retval = spi_init_eeprom(chip); | 276 | retval = spi_init_eeprom(chip); |
287 | if (retval != STATUS_SUCCESS) { | 277 | if (retval != STATUS_SUCCESS) |
288 | TRACE_RET(chip, STATUS_FAIL); | 278 | TRACE_RET(chip, STATUS_FAIL); |
289 | } | ||
290 | 279 | ||
291 | retval = spi_eeprom_program_enable(chip); | 280 | retval = spi_eeprom_program_enable(chip); |
292 | if (retval != STATUS_SUCCESS) { | 281 | if (retval != STATUS_SUCCESS) |
293 | TRACE_RET(chip, STATUS_FAIL); | 282 | TRACE_RET(chip, STATUS_FAIL); |
294 | } | ||
295 | 283 | ||
296 | rtsx_init_cmd(chip); | 284 | rtsx_init_cmd(chip); |
297 | 285 | ||
@@ -305,9 +293,8 @@ int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) | |||
305 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); | 293 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); |
306 | 294 | ||
307 | retval = rtsx_send_cmd(chip, 0, 100); | 295 | retval = rtsx_send_cmd(chip, 0, 100); |
308 | if (retval < 0) { | 296 | if (retval < 0) |
309 | TRACE_RET(chip, STATUS_FAIL); | 297 | TRACE_RET(chip, STATUS_FAIL); |
310 | } | ||
311 | 298 | ||
312 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); | 299 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); |
313 | 300 | ||
@@ -321,9 +308,8 @@ int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) | |||
321 | u8 data; | 308 | u8 data; |
322 | 309 | ||
323 | retval = spi_init_eeprom(chip); | 310 | retval = spi_init_eeprom(chip); |
324 | if (retval != STATUS_SUCCESS) { | 311 | if (retval != STATUS_SUCCESS) |
325 | TRACE_RET(chip, STATUS_FAIL); | 312 | TRACE_RET(chip, STATUS_FAIL); |
326 | } | ||
327 | 313 | ||
328 | rtsx_init_cmd(chip); | 314 | rtsx_init_cmd(chip); |
329 | 315 | ||
@@ -338,16 +324,14 @@ int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) | |||
338 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); | 324 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); |
339 | 325 | ||
340 | retval = rtsx_send_cmd(chip, 0, 100); | 326 | retval = rtsx_send_cmd(chip, 0, 100); |
341 | if (retval < 0) { | 327 | if (retval < 0) |
342 | TRACE_RET(chip, STATUS_FAIL); | 328 | TRACE_RET(chip, STATUS_FAIL); |
343 | } | ||
344 | 329 | ||
345 | wait_timeout(5); | 330 | wait_timeout(5); |
346 | RTSX_READ_REG(chip, SPI_DATA, &data); | 331 | RTSX_READ_REG(chip, SPI_DATA, &data); |
347 | 332 | ||
348 | if (val) { | 333 | if (val) |
349 | *val = data; | 334 | *val = data; |
350 | } | ||
351 | 335 | ||
352 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); | 336 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); |
353 | 337 | ||
@@ -359,14 +343,12 @@ int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) | |||
359 | int retval; | 343 | int retval; |
360 | 344 | ||
361 | retval = spi_init_eeprom(chip); | 345 | retval = spi_init_eeprom(chip); |
362 | if (retval != STATUS_SUCCESS) { | 346 | if (retval != STATUS_SUCCESS) |
363 | TRACE_RET(chip, STATUS_FAIL); | 347 | TRACE_RET(chip, STATUS_FAIL); |
364 | } | ||
365 | 348 | ||
366 | retval = spi_eeprom_program_enable(chip); | 349 | retval = spi_eeprom_program_enable(chip); |
367 | if (retval != STATUS_SUCCESS) { | 350 | if (retval != STATUS_SUCCESS) |
368 | TRACE_RET(chip, STATUS_FAIL); | 351 | TRACE_RET(chip, STATUS_FAIL); |
369 | } | ||
370 | 352 | ||
371 | rtsx_init_cmd(chip); | 353 | rtsx_init_cmd(chip); |
372 | 354 | ||
@@ -381,9 +363,8 @@ int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) | |||
381 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); | 363 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, SPI_TRANSFER0_END); |
382 | 364 | ||
383 | retval = rtsx_send_cmd(chip, 0, 100); | 365 | retval = rtsx_send_cmd(chip, 0, 100); |
384 | if (retval < 0) { | 366 | if (retval < 0) |
385 | TRACE_RET(chip, STATUS_FAIL); | 367 | TRACE_RET(chip, STATUS_FAIL); |
386 | } | ||
387 | 368 | ||
388 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); | 369 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); |
389 | 370 | ||
@@ -408,11 +389,10 @@ int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
408 | 389 | ||
409 | spi_set_err_code(chip, SPI_NO_ERR); | 390 | spi_set_err_code(chip, SPI_NO_ERR); |
410 | 391 | ||
411 | if (chip->asic_code) { | 392 | if (chip->asic_code) |
412 | spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; | 393 | spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; |
413 | } else { | 394 | else |
414 | spi->spi_clock = srb->cmnd[3]; | 395 | spi->spi_clock = srb->cmnd[3]; |
415 | } | ||
416 | 396 | ||
417 | spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; | 397 | spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; |
418 | spi->write_en = srb->cmnd[6]; | 398 | spi->write_en = srb->cmnd[6]; |
@@ -484,9 +464,8 @@ int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
484 | 464 | ||
485 | if (len) { | 465 | if (len) { |
486 | buf = (u8 *)kmalloc(len, GFP_KERNEL); | 466 | buf = (u8 *)kmalloc(len, GFP_KERNEL); |
487 | if (!buf) { | 467 | if (!buf) |
488 | TRACE_RET(chip, STATUS_ERROR); | 468 | TRACE_RET(chip, STATUS_ERROR); |
489 | } | ||
490 | 469 | ||
491 | retval = rtsx_read_ppbuf(chip, buf, len); | 470 | retval = rtsx_read_ppbuf(chip, buf, len); |
492 | if (retval != STATUS_SUCCESS) { | 471 | if (retval != STATUS_SUCCESS) { |
@@ -527,16 +506,14 @@ int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
527 | } | 506 | } |
528 | 507 | ||
529 | buf = (u8 *)rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL); | 508 | buf = (u8 *)rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL); |
530 | if (buf == NULL) { | 509 | if (buf == NULL) |
531 | TRACE_RET(chip, STATUS_ERROR); | 510 | TRACE_RET(chip, STATUS_ERROR); |
532 | } | ||
533 | 511 | ||
534 | while (len) { | 512 | while (len) { |
535 | u16 pagelen = SF_PAGE_LEN - (u8)addr; | 513 | u16 pagelen = SF_PAGE_LEN - (u8)addr; |
536 | 514 | ||
537 | if (pagelen > len) { | 515 | if (pagelen > len) |
538 | pagelen = len; | 516 | pagelen = len; |
539 | } | ||
540 | 517 | ||
541 | rtsx_init_cmd(chip); | 518 | rtsx_init_cmd(chip); |
542 | 519 | ||
@@ -608,9 +585,8 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
608 | 585 | ||
609 | if (program_mode == BYTE_PROGRAM) { | 586 | if (program_mode == BYTE_PROGRAM) { |
610 | buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL); | 587 | buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL); |
611 | if (!buf) { | 588 | if (!buf) |
612 | TRACE_RET(chip, STATUS_ERROR); | 589 | TRACE_RET(chip, STATUS_ERROR); |
613 | } | ||
614 | 590 | ||
615 | while (len) { | 591 | while (len) { |
616 | retval = sf_enable_write(chip, SPI_WREN); | 592 | retval = sf_enable_write(chip, SPI_WREN); |
@@ -651,14 +627,12 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
651 | int first_byte = 1; | 627 | int first_byte = 1; |
652 | 628 | ||
653 | retval = sf_enable_write(chip, SPI_WREN); | 629 | retval = sf_enable_write(chip, SPI_WREN); |
654 | if (retval != STATUS_SUCCESS) { | 630 | if (retval != STATUS_SUCCESS) |
655 | TRACE_RET(chip, STATUS_FAIL); | 631 | TRACE_RET(chip, STATUS_FAIL); |
656 | } | ||
657 | 632 | ||
658 | buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL); | 633 | buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL); |
659 | if (!buf) { | 634 | if (!buf) |
660 | TRACE_RET(chip, STATUS_ERROR); | 635 | TRACE_RET(chip, STATUS_ERROR); |
661 | } | ||
662 | 636 | ||
663 | while (len) { | 637 | while (len) { |
664 | rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, FROM_XFER_BUF); | 638 | rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, FROM_XFER_BUF); |
@@ -694,26 +668,22 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
694 | rtsx_free_dma_buf(chip, buf); | 668 | rtsx_free_dma_buf(chip, buf); |
695 | 669 | ||
696 | retval = sf_disable_write(chip, SPI_WRDI); | 670 | retval = sf_disable_write(chip, SPI_WRDI); |
697 | if (retval != STATUS_SUCCESS) { | 671 | if (retval != STATUS_SUCCESS) |
698 | TRACE_RET(chip, STATUS_FAIL); | 672 | TRACE_RET(chip, STATUS_FAIL); |
699 | } | ||
700 | 673 | ||
701 | retval = sf_polling_status(chip, 100); | 674 | retval = sf_polling_status(chip, 100); |
702 | if (retval != STATUS_SUCCESS) { | 675 | if (retval != STATUS_SUCCESS) |
703 | TRACE_RET(chip, STATUS_FAIL); | 676 | TRACE_RET(chip, STATUS_FAIL); |
704 | } | ||
705 | } else if (program_mode == PAGE_PROGRAM) { | 677 | } else if (program_mode == PAGE_PROGRAM) { |
706 | buf = rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL); | 678 | buf = rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL); |
707 | if (!buf) { | 679 | if (!buf) |
708 | TRACE_RET(chip, STATUS_NOMEM); | 680 | TRACE_RET(chip, STATUS_NOMEM); |
709 | } | ||
710 | 681 | ||
711 | while (len) { | 682 | while (len) { |
712 | u16 pagelen = SF_PAGE_LEN - (u8)addr; | 683 | u16 pagelen = SF_PAGE_LEN - (u8)addr; |
713 | 684 | ||
714 | if (pagelen > len) { | 685 | if (pagelen > len) |
715 | pagelen = len; | 686 | pagelen = len; |
716 | } | ||
717 | 687 | ||
718 | retval = sf_enable_write(chip, SPI_WREN); | 688 | retval = sf_enable_write(chip, SPI_WREN); |
719 | if (retval != STATUS_SUCCESS) { | 689 | if (retval != STATUS_SUCCESS) { |
@@ -777,24 +747,20 @@ int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
777 | 747 | ||
778 | if (erase_mode == PAGE_ERASE) { | 748 | if (erase_mode == PAGE_ERASE) { |
779 | retval = sf_enable_write(chip, SPI_WREN); | 749 | retval = sf_enable_write(chip, SPI_WREN); |
780 | if (retval != STATUS_SUCCESS) { | 750 | if (retval != STATUS_SUCCESS) |
781 | TRACE_RET(chip, STATUS_FAIL); | 751 | TRACE_RET(chip, STATUS_FAIL); |
782 | } | ||
783 | 752 | ||
784 | retval = sf_erase(chip, ins, 1, addr); | 753 | retval = sf_erase(chip, ins, 1, addr); |
785 | if (retval != STATUS_SUCCESS) { | 754 | if (retval != STATUS_SUCCESS) |
786 | TRACE_RET(chip, STATUS_FAIL); | 755 | TRACE_RET(chip, STATUS_FAIL); |
787 | } | ||
788 | } else if (erase_mode == CHIP_ERASE) { | 756 | } else if (erase_mode == CHIP_ERASE) { |
789 | retval = sf_enable_write(chip, SPI_WREN); | 757 | retval = sf_enable_write(chip, SPI_WREN); |
790 | if (retval != STATUS_SUCCESS) { | 758 | if (retval != STATUS_SUCCESS) |
791 | TRACE_RET(chip, STATUS_FAIL); | 759 | TRACE_RET(chip, STATUS_FAIL); |
792 | } | ||
793 | 760 | ||
794 | retval = sf_erase(chip, ins, 0, 0); | 761 | retval = sf_erase(chip, ins, 0, 0); |
795 | if (retval != STATUS_SUCCESS) { | 762 | if (retval != STATUS_SUCCESS) |
796 | TRACE_RET(chip, STATUS_FAIL); | 763 | TRACE_RET(chip, STATUS_FAIL); |
797 | } | ||
798 | } else { | 764 | } else { |
799 | spi_set_err_code(chip, SPI_INVALID_COMMAND); | 765 | spi_set_err_code(chip, SPI_INVALID_COMMAND); |
800 | TRACE_RET(chip, STATUS_FAIL); | 766 | TRACE_RET(chip, STATUS_FAIL); |
@@ -819,9 +785,8 @@ int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |||
819 | } | 785 | } |
820 | 786 | ||
821 | retval = sf_enable_write(chip, ewsr); | 787 | retval = sf_enable_write(chip, ewsr); |
822 | if (retval != STATUS_SUCCESS) { | 788 | if (retval != STATUS_SUCCESS) |
823 | TRACE_RET(chip, STATUS_FAIL); | 789 | TRACE_RET(chip, STATUS_FAIL); |
824 | } | ||
825 | 790 | ||
826 | rtsx_init_cmd(chip); | 791 | rtsx_init_cmd(chip); |
827 | 792 | ||
diff --git a/drivers/staging/rts_pstor/trace.h b/drivers/staging/rts_pstor/trace.h index 1b8958948f9..2c668bae6ff 100644 --- a/drivers/staging/rts_pstor/trace.h +++ b/drivers/staging/rts_pstor/trace.h | |||
@@ -31,16 +31,15 @@ static inline char *filename(char *path) | |||
31 | { | 31 | { |
32 | char *ptr; | 32 | char *ptr; |
33 | 33 | ||
34 | if (path == NULL) { | 34 | if (path == NULL) |
35 | return NULL; | 35 | return NULL; |
36 | } | ||
37 | 36 | ||
38 | ptr = path; | 37 | ptr = path; |
39 | 38 | ||
40 | while (*ptr != '\0') { | 39 | while (*ptr != '\0') { |
41 | if ((*ptr == '\\') || (*ptr == '/')) { | 40 | if ((*ptr == '\\') || (*ptr == '/')) |
42 | path = ptr + 1; | 41 | path = ptr + 1; |
43 | } | 42 | |
44 | ptr++; | 43 | ptr++; |
45 | } | 44 | } |
46 | 45 | ||
diff --git a/drivers/staging/rts_pstor/xd.c b/drivers/staging/rts_pstor/xd.c index f654c8b031c..7bcd468b8f2 100644 --- a/drivers/staging/rts_pstor/xd.c +++ b/drivers/staging/rts_pstor/xd.c | |||
@@ -52,16 +52,14 @@ static int xd_set_init_para(struct rtsx_chip *chip) | |||
52 | struct xd_info *xd_card = &(chip->xd_card); | 52 | struct xd_info *xd_card = &(chip->xd_card); |
53 | int retval; | 53 | int retval; |
54 | 54 | ||
55 | if (chip->asic_code) { | 55 | if (chip->asic_code) |
56 | xd_card->xd_clock = 47; | 56 | xd_card->xd_clock = 47; |
57 | } else { | 57 | else |
58 | xd_card->xd_clock = CLK_50; | 58 | xd_card->xd_clock = CLK_50; |
59 | } | ||
60 | 59 | ||
61 | retval = switch_clock(chip, xd_card->xd_clock); | 60 | retval = switch_clock(chip, xd_card->xd_clock); |
62 | if (retval != STATUS_SUCCESS) { | 61 | if (retval != STATUS_SUCCESS) |
63 | TRACE_RET(chip, STATUS_FAIL); | 62 | TRACE_RET(chip, STATUS_FAIL); |
64 | } | ||
65 | 63 | ||
66 | return STATUS_SUCCESS; | 64 | return STATUS_SUCCESS; |
67 | } | 65 | } |
@@ -72,14 +70,12 @@ static int xd_switch_clock(struct rtsx_chip *chip) | |||
72 | int retval; | 70 | int retval; |
73 | 71 | ||
74 | retval = select_card(chip, XD_CARD); | 72 | retval = select_card(chip, XD_CARD); |
75 | if (retval != STATUS_SUCCESS) { | 73 | if (retval != STATUS_SUCCESS) |
76 | TRACE_RET(chip, STATUS_FAIL); | 74 | TRACE_RET(chip, STATUS_FAIL); |
77 | } | ||
78 | 75 | ||
79 | retval = switch_clock(chip, xd_card->xd_clock); | 76 | retval = switch_clock(chip, xd_card->xd_clock); |
80 | if (retval != STATUS_SUCCESS) { | 77 | if (retval != STATUS_SUCCESS) |
81 | TRACE_RET(chip, STATUS_FAIL); | 78 | TRACE_RET(chip, STATUS_FAIL); |
82 | } | ||
83 | 79 | ||
84 | return STATUS_SUCCESS; | 80 | return STATUS_SUCCESS; |
85 | } | 81 | } |
@@ -95,14 +91,12 @@ static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) | |||
95 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID); | 91 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID); |
96 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); | 92 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); |
97 | 93 | ||
98 | for (i = 0; i < 4; i++) { | 94 | for (i = 0; i < 4; i++) |
99 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); | 95 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); |
100 | } | ||
101 | 96 | ||
102 | retval = rtsx_send_cmd(chip, XD_CARD, 20); | 97 | retval = rtsx_send_cmd(chip, XD_CARD, 20); |
103 | if (retval < 0) { | 98 | if (retval < 0) |
104 | TRACE_RET(chip, STATUS_FAIL); | 99 | TRACE_RET(chip, STATUS_FAIL); |
105 | } | ||
106 | 100 | ||
107 | ptr = rtsx_get_cmd_data(chip) + 1; | 101 | ptr = rtsx_get_cmd_data(chip) + 1; |
108 | if (id_buf && buf_len) { | 102 | if (id_buf && buf_len) { |
@@ -152,18 +146,15 @@ static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int | |||
152 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); | 146 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); |
153 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); | 147 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); |
154 | 148 | ||
155 | for (i = 0; i < 6; i++) { | 149 | for (i = 0; i < 6; i++) |
156 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 0, 0); | 150 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 0, 0); |
157 | } | 151 | for (i = 0; i < 4; i++) |
158 | for (i = 0; i < 4; i++) { | ||
159 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 0, 0); | 152 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 0, 0); |
160 | } | ||
161 | rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); | 153 | rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); |
162 | 154 | ||
163 | retval = rtsx_send_cmd(chip, XD_CARD, 500); | 155 | retval = rtsx_send_cmd(chip, XD_CARD, 500); |
164 | if (retval < 0) { | 156 | if (retval < 0) |
165 | TRACE_RET(chip, STATUS_FAIL); | 157 | TRACE_RET(chip, STATUS_FAIL); |
166 | } | ||
167 | 158 | ||
168 | if (buf && buf_len) { | 159 | if (buf && buf_len) { |
169 | u8 *ptr = rtsx_get_cmd_data(chip) + 1; | 160 | u8 *ptr = rtsx_get_cmd_data(chip) + 1; |
@@ -180,15 +171,13 @@ static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, u8 *buf, in | |||
180 | { | 171 | { |
181 | int retval, i; | 172 | int retval, i; |
182 | 173 | ||
183 | if (!buf || (buf_len < 0)) { | 174 | if (!buf || (buf_len < 0)) |
184 | TRACE_RET(chip, STATUS_FAIL); | 175 | TRACE_RET(chip, STATUS_FAIL); |
185 | } | ||
186 | 176 | ||
187 | rtsx_init_cmd(chip); | 177 | rtsx_init_cmd(chip); |
188 | 178 | ||
189 | for (i = 0; i < buf_len; i++) { | 179 | for (i = 0; i < buf_len; i++) |
190 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0); | 180 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0); |
191 | } | ||
192 | 181 | ||
193 | retval = rtsx_send_cmd(chip, 0, 250); | 182 | retval = rtsx_send_cmd(chip, 0, 250); |
194 | if (retval < 0) { | 183 | if (retval < 0) { |
@@ -206,9 +195,8 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_l | |||
206 | int retval; | 195 | int retval; |
207 | u8 reg; | 196 | u8 reg; |
208 | 197 | ||
209 | if (!buf || (buf_len < 10)) { | 198 | if (!buf || (buf_len < 10)) |
210 | TRACE_RET(chip, STATUS_FAIL); | 199 | TRACE_RET(chip, STATUS_FAIL); |
211 | } | ||
212 | 200 | ||
213 | rtsx_init_cmd(chip); | 201 | rtsx_init_cmd(chip); |
214 | 202 | ||
@@ -236,9 +224,8 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_l | |||
236 | RTSX_READ_REG(chip, XD_CTL, ®); | 224 | RTSX_READ_REG(chip, XD_CTL, ®); |
237 | if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { | 225 | if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { |
238 | retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); | 226 | retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); |
239 | if (retval != STATUS_SUCCESS) { | 227 | if (retval != STATUS_SUCCESS) |
240 | TRACE_RET(chip, STATUS_FAIL); | 228 | TRACE_RET(chip, STATUS_FAIL); |
241 | } | ||
242 | if (reg & XD_ECC1_ERROR) { | 229 | if (reg & XD_ECC1_ERROR) { |
243 | u8 ecc_bit, ecc_byte; | 230 | u8 ecc_bit, ecc_byte; |
244 | 231 | ||
@@ -256,9 +243,8 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_l | |||
256 | rtsx_clear_xd_error(chip); | 243 | rtsx_clear_xd_error(chip); |
257 | 244 | ||
258 | retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); | 245 | retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); |
259 | if (retval != STATUS_SUCCESS) { | 246 | if (retval != STATUS_SUCCESS) |
260 | TRACE_RET(chip, STATUS_FAIL); | 247 | TRACE_RET(chip, STATUS_FAIL); |
261 | } | ||
262 | if (reg & XD_ECC2_ERROR) { | 248 | if (reg & XD_ECC2_ERROR) { |
263 | u8 ecc_bit, ecc_byte; | 249 | u8 ecc_bit, ecc_byte; |
264 | 250 | ||
@@ -394,9 +380,8 @@ static void xd_clear_dma_buffer(struct rtsx_chip *chip) | |||
394 | RTSX_DEBUGP("xD ECC error, dummy write!\n"); | 380 | RTSX_DEBUGP("xD ECC error, dummy write!\n"); |
395 | 381 | ||
396 | buf = (u8 *)rtsx_alloc_dma_buf(chip, 512, GFP_KERNEL); | 382 | buf = (u8 *)rtsx_alloc_dma_buf(chip, 512, GFP_KERNEL); |
397 | if (!buf) { | 383 | if (!buf) |
398 | return; | 384 | return; |
399 | } | ||
400 | 385 | ||
401 | rtsx_init_cmd(chip); | 386 | rtsx_init_cmd(chip); |
402 | 387 | ||
@@ -461,46 +446,40 @@ static int reset_xd(struct rtsx_chip *chip) | |||
461 | u8 *ptr, id_buf[4], redunt[11]; | 446 | u8 *ptr, id_buf[4], redunt[11]; |
462 | 447 | ||
463 | retval = select_card(chip, XD_CARD); | 448 | retval = select_card(chip, XD_CARD); |
464 | if (retval != STATUS_SUCCESS) { | 449 | if (retval != STATUS_SUCCESS) |
465 | TRACE_RET(chip, STATUS_FAIL); | 450 | TRACE_RET(chip, STATUS_FAIL); |
466 | } | ||
467 | 451 | ||
468 | rtsx_init_cmd(chip); | 452 | rtsx_init_cmd(chip); |
469 | 453 | ||
470 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, XD_PGSTS_NOT_FF); | 454 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, XD_PGSTS_NOT_FF); |
471 | if (chip->asic_code) { | 455 | if (chip->asic_code) { |
472 | if (!CHECK_PID(chip, 0x5288)) { | 456 | if (!CHECK_PID(chip, 0x5288)) |
473 | xd_fill_pull_ctl_disable(chip); | 457 | xd_fill_pull_ctl_disable(chip); |
474 | } else { | 458 | else |
475 | xd_fill_pull_ctl_stage1_barossa(chip); | 459 | xd_fill_pull_ctl_stage1_barossa(chip); |
476 | } | ||
477 | } else { | 460 | } else { |
478 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, | 461 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, |
479 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); | 462 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); |
480 | } | 463 | } |
481 | 464 | ||
482 | if (!chip->ft2_fast_mode) { | 465 | if (!chip->ft2_fast_mode) |
483 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF, 0); | 466 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF, 0); |
484 | } | ||
485 | 467 | ||
486 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); | 468 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); |
487 | 469 | ||
488 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | 470 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
489 | if (retval < 0) { | 471 | if (retval < 0) |
490 | TRACE_RET(chip, STATUS_FAIL); | 472 | TRACE_RET(chip, STATUS_FAIL); |
491 | } | ||
492 | 473 | ||
493 | if (!chip->ft2_fast_mode) { | 474 | if (!chip->ft2_fast_mode) { |
494 | retval = card_power_off(chip, XD_CARD); | 475 | retval = card_power_off(chip, XD_CARD); |
495 | if (retval != STATUS_SUCCESS) { | 476 | if (retval != STATUS_SUCCESS) |
496 | TRACE_RET(chip, STATUS_FAIL); | 477 | TRACE_RET(chip, STATUS_FAIL); |
497 | } | ||
498 | 478 | ||
499 | wait_timeout(250); | 479 | wait_timeout(250); |
500 | 480 | ||
501 | if (CHECK_PID(chip, 0x5209)) { | 481 | if (CHECK_PID(chip, 0x5209)) |
502 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0xAA); | 482 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0xAA); |
503 | } | ||
504 | 483 | ||
505 | rtsx_init_cmd(chip); | 484 | rtsx_init_cmd(chip); |
506 | 485 | ||
@@ -512,14 +491,12 @@ static int reset_xd(struct rtsx_chip *chip) | |||
512 | } | 491 | } |
513 | 492 | ||
514 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | 493 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
515 | if (retval < 0) { | 494 | if (retval < 0) |
516 | TRACE_RET(chip, STATUS_FAIL); | 495 | TRACE_RET(chip, STATUS_FAIL); |
517 | } | ||
518 | 496 | ||
519 | retval = card_power_on(chip, XD_CARD); | 497 | retval = card_power_on(chip, XD_CARD); |
520 | if (retval != STATUS_SUCCESS) { | 498 | if (retval != STATUS_SUCCESS) |
521 | TRACE_RET(chip, STATUS_FAIL); | 499 | TRACE_RET(chip, STATUS_FAIL); |
522 | } | ||
523 | 500 | ||
524 | #ifdef SUPPORT_OCP | 501 | #ifdef SUPPORT_OCP |
525 | wait_timeout(50); | 502 | wait_timeout(50); |
@@ -545,18 +522,15 @@ static int reset_xd(struct rtsx_chip *chip) | |||
545 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); | 522 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); |
546 | 523 | ||
547 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | 524 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
548 | if (retval < 0) { | 525 | if (retval < 0) |
549 | TRACE_RET(chip, STATUS_FAIL); | 526 | TRACE_RET(chip, STATUS_FAIL); |
550 | } | ||
551 | 527 | ||
552 | if (!chip->ft2_fast_mode) { | 528 | if (!chip->ft2_fast_mode) |
553 | wait_timeout(200); | 529 | wait_timeout(200); |
554 | } | ||
555 | 530 | ||
556 | retval = xd_set_init_para(chip); | 531 | retval = xd_set_init_para(chip); |
557 | if (retval != STATUS_SUCCESS) { | 532 | if (retval != STATUS_SUCCESS) |
558 | TRACE_RET(chip, STATUS_FAIL); | 533 | TRACE_RET(chip, STATUS_FAIL); |
559 | } | ||
560 | 534 | ||
561 | /* Read ID to check if the timing setting is right */ | 535 | /* Read ID to check if the timing setting is right */ |
562 | for (i = 0; i < 4; i++) { | 536 | for (i = 0; i < 4; i++) { |
@@ -574,22 +548,19 @@ static int reset_xd(struct rtsx_chip *chip) | |||
574 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); | 548 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); |
575 | 549 | ||
576 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | 550 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
577 | if (retval < 0) { | 551 | if (retval < 0) |
578 | TRACE_RET(chip, STATUS_FAIL); | 552 | TRACE_RET(chip, STATUS_FAIL); |
579 | } | ||
580 | 553 | ||
581 | ptr = rtsx_get_cmd_data(chip) + 1; | 554 | ptr = rtsx_get_cmd_data(chip) + 1; |
582 | 555 | ||
583 | RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]); | 556 | RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]); |
584 | 557 | ||
585 | if (((ptr[0] & READY_FLAG) != READY_STATE) || !(ptr[1] & XD_RDY)) { | 558 | if (((ptr[0] & READY_FLAG) != READY_STATE) || !(ptr[1] & XD_RDY)) |
586 | continue; | 559 | continue; |
587 | } | ||
588 | 560 | ||
589 | retval = xd_read_id(chip, READ_ID, id_buf, 4); | 561 | retval = xd_read_id(chip, READ_ID, id_buf, 4); |
590 | if (retval != STATUS_SUCCESS) { | 562 | if (retval != STATUS_SUCCESS) |
591 | TRACE_RET(chip, STATUS_FAIL); | 563 | TRACE_RET(chip, STATUS_FAIL); |
592 | } | ||
593 | 564 | ||
594 | RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n", | 565 | RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n", |
595 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); | 566 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); |
@@ -669,9 +640,8 @@ static int reset_xd(struct rtsx_chip *chip) | |||
669 | /* Confirm timing setting */ | 640 | /* Confirm timing setting */ |
670 | for (j = 0; j < 10; j++) { | 641 | for (j = 0; j < 10; j++) { |
671 | retval = xd_read_id(chip, READ_ID, id_buf, 4); | 642 | retval = xd_read_id(chip, READ_ID, id_buf, 4); |
672 | if (retval != STATUS_SUCCESS) { | 643 | if (retval != STATUS_SUCCESS) |
673 | TRACE_RET(chip, STATUS_FAIL); | 644 | TRACE_RET(chip, STATUS_FAIL); |
674 | } | ||
675 | 645 | ||
676 | if (id_buf[1] != xd_card->device_code) | 646 | if (id_buf[1] != xd_card->device_code) |
677 | break; | 647 | break; |
@@ -691,34 +661,29 @@ static int reset_xd(struct rtsx_chip *chip) | |||
691 | } | 661 | } |
692 | 662 | ||
693 | retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); | 663 | retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); |
694 | if (retval != STATUS_SUCCESS) { | 664 | if (retval != STATUS_SUCCESS) |
695 | TRACE_RET(chip, STATUS_FAIL); | 665 | TRACE_RET(chip, STATUS_FAIL); |
696 | } | ||
697 | RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", | 666 | RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", |
698 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); | 667 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); |
699 | if (id_buf[2] != XD_ID_CODE) { | 668 | if (id_buf[2] != XD_ID_CODE) |
700 | TRACE_RET(chip, STATUS_FAIL); | 669 | TRACE_RET(chip, STATUS_FAIL); |
701 | } | ||
702 | 670 | ||
703 | /* Search CIS block */ | 671 | /* Search CIS block */ |
704 | for (i = 0; i < 24; i++) { | 672 | for (i = 0; i < 24; i++) { |
705 | u32 page_addr; | 673 | u32 page_addr; |
706 | 674 | ||
707 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | 675 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) |
708 | TRACE_RET(chip, STATUS_FAIL); | 676 | TRACE_RET(chip, STATUS_FAIL); |
709 | } | ||
710 | 677 | ||
711 | page_addr = (u32)i << xd_card->block_shift; | 678 | page_addr = (u32)i << xd_card->block_shift; |
712 | 679 | ||
713 | for (j = 0; j < 3; j++) { | 680 | for (j = 0; j < 3; j++) { |
714 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | 681 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
715 | if (retval == STATUS_SUCCESS) { | 682 | if (retval == STATUS_SUCCESS) |
716 | break; | 683 | break; |
717 | } | ||
718 | } | 684 | } |
719 | if (j == 3) { | 685 | if (j == 3) |
720 | continue; | 686 | continue; |
721 | } | ||
722 | 687 | ||
723 | if (redunt[BLOCK_STATUS] != XD_GBLK) | 688 | if (redunt[BLOCK_STATUS] != XD_GBLK) |
724 | continue; | 689 | continue; |
@@ -728,9 +693,8 @@ static int reset_xd(struct rtsx_chip *chip) | |||
728 | for (j = 1; j <= 8; j++) { | 693 | for (j = 1; j <= 8; j++) { |
729 | retval = xd_read_redundant(chip, page_addr + j, redunt, 11); | 694 | retval = xd_read_redundant(chip, page_addr + j, redunt, 11); |
730 | if (retval == STATUS_SUCCESS) { | 695 | if (retval == STATUS_SUCCESS) { |
731 | if (redunt[PAGE_STATUS] == XD_GPG) { | 696 | if (redunt[PAGE_STATUS] == XD_GPG) |
732 | break; | 697 | break; |
733 | } | ||
734 | } | 698 | } |
735 | } | 699 | } |
736 | 700 | ||
@@ -745,9 +709,8 @@ static int reset_xd(struct rtsx_chip *chip) | |||
745 | page_addr += j; | 709 | page_addr += j; |
746 | 710 | ||
747 | retval = xd_read_cis(chip, page_addr, buf, 10); | 711 | retval = xd_read_cis(chip, page_addr, buf, 10); |
748 | if (retval != STATUS_SUCCESS) { | 712 | if (retval != STATUS_SUCCESS) |
749 | TRACE_RET(chip, STATUS_FAIL); | 713 | TRACE_RET(chip, STATUS_FAIL); |
750 | } | ||
751 | 714 | ||
752 | if ((buf[0] == 0x01) && (buf[1] == 0x03) && (buf[2] == 0xD9) | 715 | if ((buf[0] == 0x01) && (buf[1] == 0x03) && (buf[2] == 0xD9) |
753 | && (buf[3] == 0x01) && (buf[4] == 0xFF) | 716 | && (buf[3] == 0x01) && (buf[4] == 0xFF) |
@@ -762,9 +725,8 @@ static int reset_xd(struct rtsx_chip *chip) | |||
762 | } | 725 | } |
763 | 726 | ||
764 | RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block); | 727 | RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block); |
765 | if (xd_card->cis_block == 0xFFFF) { | 728 | if (xd_card->cis_block == 0xFFFF) |
766 | TRACE_RET(chip, STATUS_FAIL); | 729 | TRACE_RET(chip, STATUS_FAIL); |
767 | } | ||
768 | 730 | ||
769 | chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; | 731 | chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; |
770 | 732 | ||
@@ -780,9 +742,9 @@ static int xd_check_data_blank(u8 *redunt) | |||
780 | return 0; | 742 | return 0; |
781 | } | 743 | } |
782 | 744 | ||
783 | if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) { | 745 | if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) |
784 | return 0; | 746 | return 0; |
785 | } | 747 | |
786 | 748 | ||
787 | for (i = 0; i < 4; i++) { | 749 | for (i = 0; i < 4; i++) { |
788 | if (redunt[RESERVED0 + i] != 0xFF) | 750 | if (redunt[RESERVED0 + i] != 0xFF) |
@@ -796,13 +758,12 @@ static u16 xd_load_log_block_addr(u8 *redunt) | |||
796 | { | 758 | { |
797 | u16 addr = 0xFFFF; | 759 | u16 addr = 0xFFFF; |
798 | 760 | ||
799 | if (redunt[PARITY] & XD_BA1_BA2_EQL) { | 761 | if (redunt[PARITY] & XD_BA1_BA2_EQL) |
800 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L]; | 762 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L]; |
801 | } else if (redunt[PARITY] & XD_BA1_VALID) { | 763 | else if (redunt[PARITY] & XD_BA1_VALID) |
802 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L]; | 764 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L]; |
803 | } else if (redunt[PARITY] & XD_BA2_VALID) { | 765 | else if (redunt[PARITY] & XD_BA2_VALID) |
804 | addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L]; | 766 | addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L]; |
805 | } | ||
806 | 767 | ||
807 | return addr; | 768 | return addr; |
808 | } | 769 | } |
@@ -814,17 +775,15 @@ static int xd_init_l2p_tbl(struct rtsx_chip *chip) | |||
814 | 775 | ||
815 | RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt); | 776 | RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt); |
816 | 777 | ||
817 | if (xd_card->zone_cnt < 1) { | 778 | if (xd_card->zone_cnt < 1) |
818 | TRACE_RET(chip, STATUS_FAIL); | 779 | TRACE_RET(chip, STATUS_FAIL); |
819 | } | ||
820 | 780 | ||
821 | size = xd_card->zone_cnt * sizeof(struct zone_entry); | 781 | size = xd_card->zone_cnt * sizeof(struct zone_entry); |
822 | RTSX_DEBUGP("Buffer size for l2p table is %d\n", size); | 782 | RTSX_DEBUGP("Buffer size for l2p table is %d\n", size); |
823 | 783 | ||
824 | xd_card->zone = (struct zone_entry *)vmalloc(size); | 784 | xd_card->zone = (struct zone_entry *)vmalloc(size); |
825 | if (!xd_card->zone) { | 785 | if (!xd_card->zone) |
826 | TRACE_RET(chip, STATUS_ERROR); | 786 | TRACE_RET(chip, STATUS_ERROR); |
827 | } | ||
828 | 787 | ||
829 | for (i = 0; i < xd_card->zone_cnt; i++) { | 788 | for (i = 0; i < xd_card->zone_cnt; i++) { |
830 | xd_card->zone[i].build_flag = 0; | 789 | xd_card->zone[i].build_flag = 0; |
@@ -874,9 +833,8 @@ static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) | |||
874 | zone = &(xd_card->zone[zone_no]); | 833 | zone = &(xd_card->zone[zone_no]); |
875 | 834 | ||
876 | if (zone->free_table == NULL) { | 835 | if (zone->free_table == NULL) { |
877 | if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) { | 836 | if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) |
878 | return; | 837 | return; |
879 | } | ||
880 | } | 838 | } |
881 | 839 | ||
882 | if ((zone->set_index >= XD_FREE_TABLE_CNT) | 840 | if ((zone->set_index >= XD_FREE_TABLE_CNT) |
@@ -889,9 +847,8 @@ static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) | |||
889 | RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index); | 847 | RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index); |
890 | 848 | ||
891 | zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff); | 849 | zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff); |
892 | if (zone->set_index >= XD_FREE_TABLE_CNT) { | 850 | if (zone->set_index >= XD_FREE_TABLE_CNT) |
893 | zone->set_index = 0; | 851 | zone->set_index = 0; |
894 | } | ||
895 | zone->unused_blk_cnt++; | 852 | zone->unused_blk_cnt++; |
896 | } | 853 | } |
897 | 854 | ||
@@ -923,9 +880,8 @@ static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) | |||
923 | 880 | ||
924 | phy_blk = zone->free_table[zone->get_index]; | 881 | phy_blk = zone->free_table[zone->get_index]; |
925 | zone->free_table[zone->get_index++] = 0xFFFF; | 882 | zone->free_table[zone->get_index++] = 0xFFFF; |
926 | if (zone->get_index >= XD_FREE_TABLE_CNT) { | 883 | if (zone->get_index >= XD_FREE_TABLE_CNT) |
927 | zone->get_index = 0; | 884 | zone->get_index = 0; |
928 | } | ||
929 | zone->unused_blk_cnt--; | 885 | zone->unused_blk_cnt--; |
930 | 886 | ||
931 | phy_blk += ((u32)(zone_no) << 10); | 887 | phy_blk += ((u32)(zone_no) << 10); |
@@ -1004,19 +960,16 @@ int reset_xd_card(struct rtsx_chip *chip) | |||
1004 | xd_card->delay_write.delay_write_flag = 0; | 960 | xd_card->delay_write.delay_write_flag = 0; |
1005 | 961 | ||
1006 | retval = enable_card_clock(chip, XD_CARD); | 962 | retval = enable_card_clock(chip, XD_CARD); |
1007 | if (retval != STATUS_SUCCESS) { | 963 | if (retval != STATUS_SUCCESS) |
1008 | TRACE_RET(chip, STATUS_FAIL); | 964 | TRACE_RET(chip, STATUS_FAIL); |
1009 | } | ||
1010 | 965 | ||
1011 | retval = reset_xd(chip); | 966 | retval = reset_xd(chip); |
1012 | if (retval != STATUS_SUCCESS) { | 967 | if (retval != STATUS_SUCCESS) |
1013 | TRACE_RET(chip, STATUS_FAIL); | 968 | TRACE_RET(chip, STATUS_FAIL); |
1014 | } | ||
1015 | 969 | ||
1016 | retval = xd_init_l2p_tbl(chip); | 970 | retval = xd_init_l2p_tbl(chip); |
1017 | if (retval != STATUS_SUCCESS) { | 971 | if (retval != STATUS_SUCCESS) |
1018 | TRACE_RET(chip, STATUS_FAIL); | 972 | TRACE_RET(chip, STATUS_FAIL); |
1019 | } | ||
1020 | 973 | ||
1021 | return STATUS_SUCCESS; | 974 | return STATUS_SUCCESS; |
1022 | } | 975 | } |
@@ -1030,9 +983,8 @@ static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) | |||
1030 | 983 | ||
1031 | RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk); | 984 | RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk); |
1032 | 985 | ||
1033 | if (phy_blk == BLK_NOT_FOUND) { | 986 | if (phy_blk == BLK_NOT_FOUND) |
1034 | TRACE_RET(chip, STATUS_FAIL); | 987 | TRACE_RET(chip, STATUS_FAIL); |
1035 | } | ||
1036 | 988 | ||
1037 | rtsx_init_cmd(chip); | 989 | rtsx_init_cmd(chip); |
1038 | 990 | ||
@@ -1060,11 +1012,10 @@ static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) | |||
1060 | if (retval < 0) { | 1012 | if (retval < 0) { |
1061 | rtsx_clear_xd_error(chip); | 1013 | rtsx_clear_xd_error(chip); |
1062 | rtsx_read_register(chip, XD_DAT, ®); | 1014 | rtsx_read_register(chip, XD_DAT, ®); |
1063 | if (reg & PROGRAM_ERROR) { | 1015 | if (reg & PROGRAM_ERROR) |
1064 | xd_set_err_code(chip, XD_PRG_ERROR); | 1016 | xd_set_err_code(chip, XD_PRG_ERROR); |
1065 | } else { | 1017 | else |
1066 | xd_set_err_code(chip, XD_TO_ERROR); | 1018 | xd_set_err_code(chip, XD_TO_ERROR); |
1067 | } | ||
1068 | TRACE_RET(chip, STATUS_FAIL); | 1019 | TRACE_RET(chip, STATUS_FAIL); |
1069 | } | 1020 | } |
1070 | 1021 | ||
@@ -1080,12 +1031,10 @@ static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 star | |||
1080 | 1031 | ||
1081 | RTSX_DEBUGP("Init block 0x%x\n", phy_blk); | 1032 | RTSX_DEBUGP("Init block 0x%x\n", phy_blk); |
1082 | 1033 | ||
1083 | if (start_page > end_page) { | 1034 | if (start_page > end_page) |
1084 | TRACE_RET(chip, STATUS_FAIL); | 1035 | TRACE_RET(chip, STATUS_FAIL); |
1085 | } | 1036 | if (phy_blk == BLK_NOT_FOUND) |
1086 | if (phy_blk == BLK_NOT_FOUND) { | ||
1087 | TRACE_RET(chip, STATUS_FAIL); | 1037 | TRACE_RET(chip, STATUS_FAIL); |
1088 | } | ||
1089 | 1038 | ||
1090 | rtsx_init_cmd(chip); | 1039 | rtsx_init_cmd(chip); |
1091 | 1040 | ||
@@ -1130,13 +1079,11 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u8 sta | |||
1130 | 1079 | ||
1131 | RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk, new_blk); | 1080 | RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk, new_blk); |
1132 | 1081 | ||
1133 | if (start_page > end_page) { | 1082 | if (start_page > end_page) |
1134 | TRACE_RET(chip, STATUS_FAIL); | 1083 | TRACE_RET(chip, STATUS_FAIL); |
1135 | } | ||
1136 | 1084 | ||
1137 | if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) { | 1085 | if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) |
1138 | TRACE_RET(chip, STATUS_FAIL); | 1086 | TRACE_RET(chip, STATUS_FAIL); |
1139 | } | ||
1140 | 1087 | ||
1141 | old_page = (old_blk << xd_card->block_shift) + start_page; | 1088 | old_page = (old_blk << xd_card->block_shift) + start_page; |
1142 | new_page = (new_blk << xd_card->block_shift) + start_page; | 1089 | new_page = (new_blk << xd_card->block_shift) + start_page; |
@@ -1189,9 +1136,8 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u8 sta | |||
1189 | } | 1136 | } |
1190 | } | 1137 | } |
1191 | 1138 | ||
1192 | if (XD_CHK_BAD_OLDBLK(xd_card)) { | 1139 | if (XD_CHK_BAD_OLDBLK(xd_card)) |
1193 | rtsx_clear_xd_error(chip); | 1140 | rtsx_clear_xd_error(chip); |
1194 | } | ||
1195 | 1141 | ||
1196 | rtsx_init_cmd(chip); | 1142 | rtsx_init_cmd(chip); |
1197 | 1143 | ||
@@ -1236,14 +1182,12 @@ static int xd_reset_cmd(struct rtsx_chip *chip) | |||
1236 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); | 1182 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); |
1237 | 1183 | ||
1238 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | 1184 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
1239 | if (retval < 0) { | 1185 | if (retval < 0) |
1240 | TRACE_RET(chip, STATUS_FAIL); | 1186 | TRACE_RET(chip, STATUS_FAIL); |
1241 | } | ||
1242 | 1187 | ||
1243 | ptr = rtsx_get_cmd_data(chip) + 1; | 1188 | ptr = rtsx_get_cmd_data(chip) + 1; |
1244 | if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) { | 1189 | if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) |
1245 | return STATUS_SUCCESS; | 1190 | return STATUS_SUCCESS; |
1246 | } | ||
1247 | 1191 | ||
1248 | TRACE_RET(chip, STATUS_FAIL); | 1192 | TRACE_RET(chip, STATUS_FAIL); |
1249 | } | 1193 | } |
@@ -1255,9 +1199,8 @@ static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) | |||
1255 | u8 reg = 0, *ptr; | 1199 | u8 reg = 0, *ptr; |
1256 | int i, retval; | 1200 | int i, retval; |
1257 | 1201 | ||
1258 | if (phy_blk == BLK_NOT_FOUND) { | 1202 | if (phy_blk == BLK_NOT_FOUND) |
1259 | TRACE_RET(chip, STATUS_FAIL); | 1203 | TRACE_RET(chip, STATUS_FAIL); |
1260 | } | ||
1261 | 1204 | ||
1262 | page_addr = phy_blk << xd_card->block_shift; | 1205 | page_addr = phy_blk << xd_card->block_shift; |
1263 | 1206 | ||
@@ -1282,9 +1225,8 @@ static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) | |||
1282 | xd_set_err_code(chip, XD_ERASE_FAIL); | 1225 | xd_set_err_code(chip, XD_ERASE_FAIL); |
1283 | } | 1226 | } |
1284 | retval = xd_reset_cmd(chip); | 1227 | retval = xd_reset_cmd(chip); |
1285 | if (retval != STATUS_SUCCESS) { | 1228 | if (retval != STATUS_SUCCESS) |
1286 | TRACE_RET(chip, STATUS_FAIL); | 1229 | TRACE_RET(chip, STATUS_FAIL); |
1287 | } | ||
1288 | continue; | 1230 | continue; |
1289 | } | 1231 | } |
1290 | 1232 | ||
@@ -1317,9 +1259,8 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1317 | 1259 | ||
1318 | if (xd_card->zone == NULL) { | 1260 | if (xd_card->zone == NULL) { |
1319 | retval = xd_init_l2p_tbl(chip); | 1261 | retval = xd_init_l2p_tbl(chip); |
1320 | if (retval != STATUS_SUCCESS) { | 1262 | if (retval != STATUS_SUCCESS) |
1321 | return retval; | 1263 | return retval; |
1322 | } | ||
1323 | } | 1264 | } |
1324 | 1265 | ||
1325 | if (xd_card->zone[zone_no].build_flag) { | 1266 | if (xd_card->zone[zone_no].build_flag) { |
@@ -1331,26 +1272,23 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1331 | 1272 | ||
1332 | if (zone->l2p_table == NULL) { | 1273 | if (zone->l2p_table == NULL) { |
1333 | zone->l2p_table = (u16 *)vmalloc(2000); | 1274 | zone->l2p_table = (u16 *)vmalloc(2000); |
1334 | if (zone->l2p_table == NULL) { | 1275 | if (zone->l2p_table == NULL) |
1335 | TRACE_GOTO(chip, Build_Fail); | 1276 | TRACE_GOTO(chip, Build_Fail); |
1336 | } | ||
1337 | } | 1277 | } |
1338 | memset((u8 *)(zone->l2p_table), 0xff, 2000); | 1278 | memset((u8 *)(zone->l2p_table), 0xff, 2000); |
1339 | 1279 | ||
1340 | if (zone->free_table == NULL) { | 1280 | if (zone->free_table == NULL) { |
1341 | zone->free_table = (u16 *)vmalloc(XD_FREE_TABLE_CNT * 2); | 1281 | zone->free_table = (u16 *)vmalloc(XD_FREE_TABLE_CNT * 2); |
1342 | if (zone->free_table == NULL) { | 1282 | if (zone->free_table == NULL) |
1343 | TRACE_GOTO(chip, Build_Fail); | 1283 | TRACE_GOTO(chip, Build_Fail); |
1344 | } | ||
1345 | } | 1284 | } |
1346 | memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); | 1285 | memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); |
1347 | 1286 | ||
1348 | if (zone_no == 0) { | 1287 | if (zone_no == 0) { |
1349 | if (xd_card->cis_block == 0xFFFF) { | 1288 | if (xd_card->cis_block == 0xFFFF) |
1350 | start = 0; | 1289 | start = 0; |
1351 | } else { | 1290 | else |
1352 | start = xd_card->cis_block + 1; | 1291 | start = xd_card->cis_block + 1; |
1353 | } | ||
1354 | if (XD_CHK_4MB(xd_card)) { | 1292 | if (XD_CHK_4MB(xd_card)) { |
1355 | end = 0x200; | 1293 | end = 0x200; |
1356 | max_logoff = 499; | 1294 | max_logoff = 499; |
@@ -1374,9 +1312,8 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1374 | u32 phy_block; | 1312 | u32 phy_block; |
1375 | 1313 | ||
1376 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | 1314 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
1377 | if (retval != STATUS_SUCCESS) { | 1315 | if (retval != STATUS_SUCCESS) |
1378 | continue; | 1316 | continue; |
1379 | } | ||
1380 | 1317 | ||
1381 | if (redunt[BLOCK_STATUS] != 0xFF) { | 1318 | if (redunt[BLOCK_STATUS] != 0xFF) { |
1382 | RTSX_DEBUGP("bad block\n"); | 1319 | RTSX_DEBUGP("bad block\n"); |
@@ -1392,15 +1329,13 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1392 | cur_fst_page_logoff = xd_load_log_block_addr(redunt); | 1329 | cur_fst_page_logoff = xd_load_log_block_addr(redunt); |
1393 | if ((cur_fst_page_logoff == 0xFFFF) || (cur_fst_page_logoff > max_logoff)) { | 1330 | if ((cur_fst_page_logoff == 0xFFFF) || (cur_fst_page_logoff > max_logoff)) { |
1394 | retval = xd_erase_block(chip, i); | 1331 | retval = xd_erase_block(chip, i); |
1395 | if (retval == STATUS_SUCCESS) { | 1332 | if (retval == STATUS_SUCCESS) |
1396 | xd_set_unused_block(chip, i); | 1333 | xd_set_unused_block(chip, i); |
1397 | } | ||
1398 | continue; | 1334 | continue; |
1399 | } | 1335 | } |
1400 | 1336 | ||
1401 | if ((zone_no == 0) && (cur_fst_page_logoff == 0) && (redunt[PAGE_STATUS] != XD_GPG)) { | 1337 | if ((zone_no == 0) && (cur_fst_page_logoff == 0) && (redunt[PAGE_STATUS] != XD_GPG)) |
1402 | XD_SET_MBR_FAIL(xd_card); | 1338 | XD_SET_MBR_FAIL(xd_card); |
1403 | } | ||
1404 | 1339 | ||
1405 | if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { | 1340 | if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { |
1406 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); | 1341 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); |
@@ -1412,9 +1347,8 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1412 | page_addr = ((i + 1) << xd_card->block_shift) - 1; | 1347 | page_addr = ((i + 1) << xd_card->block_shift) - 1; |
1413 | 1348 | ||
1414 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | 1349 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
1415 | if (retval != STATUS_SUCCESS) { | 1350 | if (retval != STATUS_SUCCESS) |
1416 | continue; | 1351 | continue; |
1417 | } | ||
1418 | 1352 | ||
1419 | cur_lst_page_logoff = xd_load_log_block_addr(redunt); | 1353 | cur_lst_page_logoff = xd_load_log_block_addr(redunt); |
1420 | if (cur_lst_page_logoff == cur_fst_page_logoff) { | 1354 | if (cur_lst_page_logoff == cur_fst_page_logoff) { |
@@ -1431,9 +1365,8 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1431 | if (m == 3) { | 1365 | if (m == 3) { |
1432 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); | 1366 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); |
1433 | retval = xd_erase_block(chip, phy_block); | 1367 | retval = xd_erase_block(chip, phy_block); |
1434 | if (retval == STATUS_SUCCESS) { | 1368 | if (retval == STATUS_SUCCESS) |
1435 | xd_set_unused_block(chip, phy_block); | 1369 | xd_set_unused_block(chip, phy_block); |
1436 | } | ||
1437 | continue; | 1370 | continue; |
1438 | } | 1371 | } |
1439 | 1372 | ||
@@ -1441,43 +1374,37 @@ static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) | |||
1441 | if (ent_lst_page_logoff != cur_fst_page_logoff) { | 1374 | if (ent_lst_page_logoff != cur_fst_page_logoff) { |
1442 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); | 1375 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); |
1443 | retval = xd_erase_block(chip, phy_block); | 1376 | retval = xd_erase_block(chip, phy_block); |
1444 | if (retval == STATUS_SUCCESS) { | 1377 | if (retval == STATUS_SUCCESS) |
1445 | xd_set_unused_block(chip, phy_block); | 1378 | xd_set_unused_block(chip, phy_block); |
1446 | } | ||
1447 | continue; | 1379 | continue; |
1448 | } else { | 1380 | } else { |
1449 | retval = xd_erase_block(chip, i); | 1381 | retval = xd_erase_block(chip, i); |
1450 | if (retval == STATUS_SUCCESS) { | 1382 | if (retval == STATUS_SUCCESS) |
1451 | xd_set_unused_block(chip, i); | 1383 | xd_set_unused_block(chip, i); |
1452 | } | ||
1453 | } | 1384 | } |
1454 | } else { | 1385 | } else { |
1455 | retval = xd_erase_block(chip, i); | 1386 | retval = xd_erase_block(chip, i); |
1456 | if (retval == STATUS_SUCCESS) { | 1387 | if (retval == STATUS_SUCCESS) |
1457 | xd_set_unused_block(chip, i); | 1388 | xd_set_unused_block(chip, i); |
1458 | } | ||
1459 | } | 1389 | } |
1460 | } | 1390 | } |
1461 | 1391 | ||
1462 | if (XD_CHK_4MB(xd_card)) { | 1392 | if (XD_CHK_4MB(xd_card)) |
1463 | end = 500; | 1393 | end = 500; |
1464 | } else { | 1394 | else |
1465 | end = 1000; | 1395 | end = 1000; |
1466 | } | ||
1467 | 1396 | ||
1468 | i = 0; | 1397 | i = 0; |
1469 | for (start = 0; start < end; start++) { | 1398 | for (start = 0; start < end; start++) { |
1470 | if (zone->l2p_table[start] == 0xFFFF) { | 1399 | if (zone->l2p_table[start] == 0xFFFF) |
1471 | i++; | 1400 | i++; |
1472 | } | ||
1473 | } | 1401 | } |
1474 | 1402 | ||
1475 | RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i); | 1403 | RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i); |
1476 | RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt); | 1404 | RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt); |
1477 | 1405 | ||
1478 | if ((zone->unused_blk_cnt - i) < 1) { | 1406 | if ((zone->unused_blk_cnt - i) < 1) |
1479 | chip->card_wp |= XD_CARD; | 1407 | chip->card_wp |= XD_CARD; |
1480 | } | ||
1481 | 1408 | ||
1482 | zone->build_flag = 1; | 1409 | zone->build_flag = 1; |
1483 | 1410 | ||
@@ -1507,9 +1434,8 @@ static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) | |||
1507 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); | 1434 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END); |
1508 | 1435 | ||
1509 | retval = rtsx_send_cmd(chip, XD_CARD, 200); | 1436 | retval = rtsx_send_cmd(chip, XD_CARD, 200); |
1510 | if (retval < 0) { | 1437 | if (retval < 0) |
1511 | TRACE_RET(chip, STATUS_FAIL); | 1438 | TRACE_RET(chip, STATUS_FAIL); |
1512 | } | ||
1513 | 1439 | ||
1514 | return STATUS_SUCCESS; | 1440 | return STATUS_SUCCESS; |
1515 | } | 1441 | } |
@@ -1523,9 +1449,8 @@ static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, u32 log_b | |||
1523 | u8 reg_val, page_cnt; | 1449 | u8 reg_val, page_cnt; |
1524 | int zone_no, retval, i; | 1450 | int zone_no, retval, i; |
1525 | 1451 | ||
1526 | if (start_page > end_page) { | 1452 | if (start_page > end_page) |
1527 | TRACE_RET(chip, STATUS_FAIL); | 1453 | TRACE_RET(chip, STATUS_FAIL); |
1528 | } | ||
1529 | 1454 | ||
1530 | page_cnt = end_page - start_page; | 1455 | page_cnt = end_page - start_page; |
1531 | zone_no = (int)(log_blk / 1000); | 1456 | zone_no = (int)(log_blk / 1000); |
@@ -1584,9 +1509,8 @@ static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, u32 log_b | |||
1584 | Fail: | 1509 | Fail: |
1585 | RTSX_READ_REG(chip, XD_PAGE_STATUS, ®_val); | 1510 | RTSX_READ_REG(chip, XD_PAGE_STATUS, ®_val); |
1586 | 1511 | ||
1587 | if (reg_val != XD_GPG) { | 1512 | if (reg_val != XD_GPG) |
1588 | xd_set_err_code(chip, XD_PRG_ERROR); | 1513 | xd_set_err_code(chip, XD_PRG_ERROR); |
1589 | } | ||
1590 | 1514 | ||
1591 | RTSX_READ_REG(chip, XD_CTL, ®_val); | 1515 | RTSX_READ_REG(chip, XD_CTL, ®_val); |
1592 | 1516 | ||
@@ -1613,9 +1537,8 @@ Fail: | |||
1613 | if (retval != STATUS_SUCCESS) { | 1537 | if (retval != STATUS_SUCCESS) { |
1614 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { | 1538 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { |
1615 | retval = xd_erase_block(chip, new_blk); | 1539 | retval = xd_erase_block(chip, new_blk); |
1616 | if (retval == STATUS_SUCCESS) { | 1540 | if (retval == STATUS_SUCCESS) |
1617 | xd_set_unused_block(chip, new_blk); | 1541 | xd_set_unused_block(chip, new_blk); |
1618 | } | ||
1619 | } else { | 1542 | } else { |
1620 | XD_CLR_BAD_NEWBLK(xd_card); | 1543 | XD_CLR_BAD_NEWBLK(xd_card); |
1621 | } | 1544 | } |
@@ -1641,9 +1564,8 @@ static int xd_finish_write(struct rtsx_chip *chip, | |||
1641 | RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", | 1564 | RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
1642 | old_blk, new_blk, log_blk); | 1565 | old_blk, new_blk, log_blk); |
1643 | 1566 | ||
1644 | if (page_off > xd_card->page_off) { | 1567 | if (page_off > xd_card->page_off) |
1645 | TRACE_RET(chip, STATUS_FAIL); | 1568 | TRACE_RET(chip, STATUS_FAIL); |
1646 | } | ||
1647 | 1569 | ||
1648 | zone_no = (int)(log_blk / 1000); | 1570 | zone_no = (int)(log_blk / 1000); |
1649 | log_off = (u16)(log_blk % 1000); | 1571 | log_off = (u16)(log_blk % 1000); |
@@ -1653,9 +1575,8 @@ static int xd_finish_write(struct rtsx_chip *chip, | |||
1653 | page_off, xd_card->page_off + 1); | 1575 | page_off, xd_card->page_off + 1); |
1654 | if (retval != STATUS_SUCCESS) { | 1576 | if (retval != STATUS_SUCCESS) { |
1655 | retval = xd_erase_block(chip, new_blk); | 1577 | retval = xd_erase_block(chip, new_blk); |
1656 | if (retval == STATUS_SUCCESS) { | 1578 | if (retval == STATUS_SUCCESS) |
1657 | xd_set_unused_block(chip, new_blk); | 1579 | xd_set_unused_block(chip, new_blk); |
1658 | } | ||
1659 | TRACE_RET(chip, STATUS_FAIL); | 1580 | TRACE_RET(chip, STATUS_FAIL); |
1660 | } | 1581 | } |
1661 | } else { | 1582 | } else { |
@@ -1664,9 +1585,8 @@ static int xd_finish_write(struct rtsx_chip *chip, | |||
1664 | if (retval != STATUS_SUCCESS) { | 1585 | if (retval != STATUS_SUCCESS) { |
1665 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { | 1586 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { |
1666 | retval = xd_erase_block(chip, new_blk); | 1587 | retval = xd_erase_block(chip, new_blk); |
1667 | if (retval == STATUS_SUCCESS) { | 1588 | if (retval == STATUS_SUCCESS) |
1668 | xd_set_unused_block(chip, new_blk); | 1589 | xd_set_unused_block(chip, new_blk); |
1669 | } | ||
1670 | } | 1590 | } |
1671 | XD_CLR_BAD_NEWBLK(xd_card); | 1591 | XD_CLR_BAD_NEWBLK(xd_card); |
1672 | TRACE_RET(chip, STATUS_FAIL); | 1592 | TRACE_RET(chip, STATUS_FAIL); |
@@ -1701,9 +1621,8 @@ static int xd_prepare_write(struct rtsx_chip *chip, | |||
1701 | 1621 | ||
1702 | if (page_off) { | 1622 | if (page_off) { |
1703 | retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); | 1623 | retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); |
1704 | if (retval != STATUS_SUCCESS) { | 1624 | if (retval != STATUS_SUCCESS) |
1705 | TRACE_RET(chip, STATUS_FAIL); | 1625 | TRACE_RET(chip, STATUS_FAIL); |
1706 | } | ||
1707 | } | 1626 | } |
1708 | 1627 | ||
1709 | return STATUS_SUCCESS; | 1628 | return STATUS_SUCCESS; |
@@ -1722,9 +1641,8 @@ static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, u32 new_ | |||
1722 | RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", | 1641 | RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
1723 | __func__, old_blk, new_blk, log_blk); | 1642 | __func__, old_blk, new_blk, log_blk); |
1724 | 1643 | ||
1725 | if (start_page > end_page) { | 1644 | if (start_page > end_page) |
1726 | TRACE_RET(chip, STATUS_FAIL); | 1645 | TRACE_RET(chip, STATUS_FAIL); |
1727 | } | ||
1728 | 1646 | ||
1729 | page_cnt = end_page - start_page; | 1647 | page_cnt = end_page - start_page; |
1730 | zone_no = (int)(log_blk / 1000); | 1648 | zone_no = (int)(log_blk / 1000); |
@@ -1733,9 +1651,8 @@ static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, u32 new_ | |||
1733 | page_addr = (new_blk << xd_card->block_shift) + start_page; | 1651 | page_addr = (new_blk << xd_card->block_shift) + start_page; |
1734 | 1652 | ||
1735 | retval = xd_send_cmd(chip, READ1_1); | 1653 | retval = xd_send_cmd(chip, READ1_1); |
1736 | if (retval != STATUS_SUCCESS) { | 1654 | if (retval != STATUS_SUCCESS) |
1737 | TRACE_RET(chip, STATUS_FAIL); | 1655 | TRACE_RET(chip, STATUS_FAIL); |
1738 | } | ||
1739 | 1656 | ||
1740 | rtsx_init_cmd(chip); | 1657 | rtsx_init_cmd(chip); |
1741 | 1658 | ||
@@ -1812,17 +1729,15 @@ int xd_delay_write(struct rtsx_chip *chip) | |||
1812 | if (delay_write->delay_write_flag) { | 1729 | if (delay_write->delay_write_flag) { |
1813 | RTSX_DEBUGP("xd_delay_write\n"); | 1730 | RTSX_DEBUGP("xd_delay_write\n"); |
1814 | retval = xd_switch_clock(chip); | 1731 | retval = xd_switch_clock(chip); |
1815 | if (retval != STATUS_SUCCESS) { | 1732 | if (retval != STATUS_SUCCESS) |
1816 | TRACE_RET(chip, STATUS_FAIL); | 1733 | TRACE_RET(chip, STATUS_FAIL); |
1817 | } | ||
1818 | 1734 | ||
1819 | delay_write->delay_write_flag = 0; | 1735 | delay_write->delay_write_flag = 0; |
1820 | retval = xd_finish_write(chip, | 1736 | retval = xd_finish_write(chip, |
1821 | delay_write->old_phyblock, delay_write->new_phyblock, | 1737 | delay_write->old_phyblock, delay_write->new_phyblock, |
1822 | delay_write->logblock, delay_write->pageoff); | 1738 | delay_write->logblock, delay_write->pageoff); |
1823 | if (retval != STATUS_SUCCESS) { | 1739 | if (retval != STATUS_SUCCESS) |
1824 | TRACE_RET(chip, STATUS_FAIL); | 1740 | TRACE_RET(chip, STATUS_FAIL); |
1825 | } | ||
1826 | } | 1741 | } |
1827 | 1742 | ||
1828 | return STATUS_SUCCESS; | 1743 | return STATUS_SUCCESS; |
@@ -1852,9 +1767,9 @@ int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 s | |||
1852 | ptr = (u8 *)scsi_sglist(srb); | 1767 | ptr = (u8 *)scsi_sglist(srb); |
1853 | 1768 | ||
1854 | retval = xd_switch_clock(chip); | 1769 | retval = xd_switch_clock(chip); |
1855 | if (retval != STATUS_SUCCESS) { | 1770 | if (retval != STATUS_SUCCESS) |
1856 | TRACE_RET(chip, STATUS_FAIL); | 1771 | TRACE_RET(chip, STATUS_FAIL); |
1857 | } | 1772 | |
1858 | 1773 | ||
1859 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | 1774 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
1860 | chip->card_fail |= XD_CARD; | 1775 | chip->card_fail |= XD_CARD; |
@@ -1955,11 +1870,11 @@ int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 s | |||
1955 | TRACE_RET(chip, STATUS_FAIL); | 1870 | TRACE_RET(chip, STATUS_FAIL); |
1956 | } | 1871 | } |
1957 | 1872 | ||
1958 | if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) { | 1873 | if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) |
1959 | end_page = xd_card->page_off + 1; | 1874 | end_page = xd_card->page_off + 1; |
1960 | } else { | 1875 | else |
1961 | end_page = start_page + (u8)total_sec_cnt; | 1876 | end_page = start_page + (u8)total_sec_cnt; |
1962 | } | 1877 | |
1963 | page_cnt = end_page - start_page; | 1878 | page_cnt = end_page - start_page; |
1964 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | 1879 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { |
1965 | retval = xd_read_multiple_pages(chip, old_blk, log_blk, | 1880 | retval = xd_read_multiple_pages(chip, old_blk, log_blk, |
@@ -1999,11 +1914,11 @@ int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 s | |||
1999 | 1914 | ||
2000 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); | 1915 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); |
2001 | if (old_blk == BLK_NOT_FOUND) { | 1916 | if (old_blk == BLK_NOT_FOUND) { |
2002 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | 1917 | if (srb->sc_data_direction == DMA_FROM_DEVICE) |
2003 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); | 1918 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
2004 | } else { | 1919 | else |
2005 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); | 1920 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); |
2006 | } | 1921 | |
2007 | TRACE_RET(chip, STATUS_FAIL); | 1922 | TRACE_RET(chip, STATUS_FAIL); |
2008 | } | 1923 | } |
2009 | 1924 | ||
@@ -2089,26 +2004,23 @@ int xd_power_off_card3v3(struct rtsx_chip *chip) | |||
2089 | int retval; | 2004 | int retval; |
2090 | 2005 | ||
2091 | retval = disable_card_clock(chip, XD_CARD); | 2006 | retval = disable_card_clock(chip, XD_CARD); |
2092 | if (retval != STATUS_SUCCESS) { | 2007 | if (retval != STATUS_SUCCESS) |
2093 | TRACE_RET(chip, STATUS_FAIL); | 2008 | TRACE_RET(chip, STATUS_FAIL); |
2094 | } | ||
2095 | 2009 | ||
2096 | RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0); | 2010 | RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0); |
2097 | 2011 | ||
2098 | if (!chip->ft2_fast_mode) { | 2012 | if (!chip->ft2_fast_mode) { |
2099 | retval = card_power_off(chip, XD_CARD); | 2013 | retval = card_power_off(chip, XD_CARD); |
2100 | if (retval != STATUS_SUCCESS) { | 2014 | if (retval != STATUS_SUCCESS) |
2101 | TRACE_RET(chip, STATUS_FAIL); | 2015 | TRACE_RET(chip, STATUS_FAIL); |
2102 | } | ||
2103 | 2016 | ||
2104 | wait_timeout(50); | 2017 | wait_timeout(50); |
2105 | } | 2018 | } |
2106 | 2019 | ||
2107 | if (chip->asic_code) { | 2020 | if (chip->asic_code) { |
2108 | retval = xd_pull_ctl_disable(chip); | 2021 | retval = xd_pull_ctl_disable(chip); |
2109 | if (retval != STATUS_SUCCESS) { | 2022 | if (retval != STATUS_SUCCESS) |
2110 | TRACE_RET(chip, STATUS_FAIL); | 2023 | TRACE_RET(chip, STATUS_FAIL); |
2111 | } | ||
2112 | } else { | 2024 | } else { |
2113 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF); | 2025 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF); |
2114 | } | 2026 | } |
@@ -2132,9 +2044,8 @@ int release_xd_card(struct rtsx_chip *chip) | |||
2132 | xd_free_l2p_tbl(chip); | 2044 | xd_free_l2p_tbl(chip); |
2133 | 2045 | ||
2134 | retval = xd_power_off_card3v3(chip); | 2046 | retval = xd_power_off_card3v3(chip); |
2135 | if (retval != STATUS_SUCCESS) { | 2047 | if (retval != STATUS_SUCCESS) |
2136 | TRACE_RET(chip, STATUS_FAIL); | 2048 | TRACE_RET(chip, STATUS_FAIL); |
2137 | } | ||
2138 | 2049 | ||
2139 | return STATUS_SUCCESS; | 2050 | return STATUS_SUCCESS; |
2140 | } | 2051 | } |