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authorAlan Cox <alan@linux.intel.com>2011-02-01 10:42:22 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-02-04 16:01:01 -0500
commit404dc5f3f475ce3598d0e295883a28efafb90ac5 (patch)
tree5cc8b817d32e788778b5e19ad494aed8831e27b2 /drivers
parentae3e5f0e9a27b0c015570cb2899484c1456846a7 (diff)
staging: et131x: Begin cleaning up the MI registers
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/et131x/et1310_phy.c50
-rw-r--r--drivers/staging/et131x/et1310_phy.h649
-rw-r--r--drivers/staging/et131x/et131x_isr.c8
3 files changed, 199 insertions, 508 deletions
diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
index a0ec75ed90e..2798a2ff612 100644
--- a/drivers/staging/et131x/et1310_phy.c
+++ b/drivers/staging/et131x/et1310_phy.c
@@ -242,23 +242,23 @@ int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
242int et131x_xcvr_find(struct et131x_adapter *etdev) 242int et131x_xcvr_find(struct et131x_adapter *etdev)
243{ 243{
244 u8 xcvr_addr; 244 u8 xcvr_addr;
245 MI_IDR1_t idr1; 245 u16 idr1;
246 MI_IDR2_t idr2; 246 u16 idr2;
247 u32 xcvr_id; 247 u32 xcvr_id;
248 248
249 /* We need to get xcvr id and address we just get the first one */ 249 /* We need to get xcvr id and address we just get the first one */
250 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) { 250 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
251 /* Read the ID from the PHY */ 251 /* Read the ID from the PHY */
252 PhyMiRead(etdev, xcvr_addr, 252 PhyMiRead(etdev, xcvr_addr,
253 (u8) offsetof(MI_REGS_t, idr1), 253 (u8) offsetof(struct mi_regs, idr1),
254 &idr1.value); 254 &idr1);
255 PhyMiRead(etdev, xcvr_addr, 255 PhyMiRead(etdev, xcvr_addr,
256 (u8) offsetof(MI_REGS_t, idr2), 256 (u8) offsetof(struct mi_regs, idr2),
257 &idr2.value); 257 &idr2);
258 258
259 xcvr_id = (u32) ((idr1.value << 16) | idr2.value); 259 xcvr_id = (u32) ((idr1 << 16) | idr2);
260 260
261 if (idr1.value != 0 && idr1.value != 0xffff) { 261 if (idr1 != 0 && idr1 != 0xffff) {
262 etdev->Stats.xcvr_id = xcvr_id; 262 etdev->Stats.xcvr_id = xcvr_id;
263 etdev->Stats.xcvr_addr = xcvr_addr; 263 etdev->Stats.xcvr_addr = xcvr_addr;
264 return 0; 264 return 0;
@@ -577,24 +577,22 @@ void et131x_setphy_normal(struct et131x_adapter *etdev)
577 */ 577 */
578static void et131x_xcvr_init(struct et131x_adapter *etdev) 578static void et131x_xcvr_init(struct et131x_adapter *etdev)
579{ 579{
580 MI_IMR_t imr; 580 u16 imr;
581 MI_ISR_t isr; 581 u16 isr;
582 MI_LCR2_t lcr2; 582 u16 lcr2;
583 583
584 /* Zero out the adapter structure variable representing BMSR */ 584 /* Zero out the adapter structure variable representing BMSR */
585 etdev->Bmsr.value = 0; 585 etdev->Bmsr.value = 0;
586 586
587 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value); 587 MiRead(etdev, (u8) offsetof(struct mi_regs, isr), &isr);
588 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value); 588 MiRead(etdev, (u8) offsetof(struct mi_regs, imr), &imr);
589 589
590 /* Set the link status interrupt only. Bad behavior when link status 590 /* Set the link status interrupt only. Bad behavior when link status
591 * and auto neg are set, we run into a nested interrupt problem 591 * and auto neg are set, we run into a nested interrupt problem
592 */ 592 */
593 imr.bits.int_en = 0x1; 593 imr |= 0x0105;
594 imr.bits.link_status = 0x1;
595 imr.bits.autoneg_status = 0x1;
596 594
597 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value); 595 MiWrite(etdev, (u8) offsetof(struct mi_regs, imr), imr);
598 596
599 /* Set the LED behavior such that LED 1 indicates speed (off = 597 /* Set the LED behavior such that LED 1 indicates speed (off =
600 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates 598 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
@@ -605,15 +603,19 @@ static void et131x_xcvr_init(struct et131x_adapter *etdev)
605 * EEPROM. However, the above description is the default. 603 * EEPROM. However, the above description is the default.
606 */ 604 */
607 if ((etdev->eeprom_data[1] & 0x4) == 0) { 605 if ((etdev->eeprom_data[1] & 0x4) == 0) {
608 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2), 606 MiRead(etdev, (u8) offsetof(struct mi_regs, lcr2),
609 &lcr2.value); 607 &lcr2);
608
609 lcr2 &= 0x00FF;
610 lcr2 |= 0xA000; /* led link */
611
610 if ((etdev->eeprom_data[1] & 0x8) == 0) 612 if ((etdev->eeprom_data[1] & 0x8) == 0)
611 lcr2.bits.led_tx_rx = 0x3; 613 lcr2 |= 0x0300;
612 else 614 else
613 lcr2.bits.led_tx_rx = 0x4; 615 lcr2 |= 0x0400;
614 lcr2.bits.led_link = 0xa; 616
615 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2), 617 MiWrite(etdev, (u8) offsetof(struct mi_regs, lcr2),
616 lcr2.value); 618 lcr2);
617 } 619 }
618 620
619 /* Determine if we need to go into a force mode and set it */ 621 /* Determine if we need to go into a force mode and set it */
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
index 47907ba7601..78349adc7d8 100644
--- a/drivers/staging/et131x/et1310_phy.h
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -98,7 +98,7 @@
98#define VMI_RESERVED31_REG 31 98#define VMI_RESERVED31_REG 31
99 99
100/* PHY Register Mapping(MI) Management Interface Regs */ 100/* PHY Register Mapping(MI) Management Interface Regs */
101typedef struct _MI_REGS_t { 101struct mi_regs {
102 u8 bmcr; /* Basic mode control reg(Reg 0x00) */ 102 u8 bmcr; /* Basic mode control reg(Reg 0x00) */
103 u8 bmsr; /* Basic mode status reg(Reg 0x01) */ 103 u8 bmsr; /* Basic mode status reg(Reg 0x01) */
104 u8 idr1; /* Phy identifier reg 1(Reg 0x02) */ 104 u8 idr1; /* Phy identifier reg 1(Reg 0x02) */
@@ -124,7 +124,7 @@ typedef struct _MI_REGS_t {
124 u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */ 124 u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */
125 u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */ 125 u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */
126 u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */ 126 u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
127} MI_REGS_t, *PMI_REGS_t; 127};
128 128
129/* MI Register 0: Basic mode control register */ 129/* MI Register 0: Basic mode control register */
130typedef union _MI_BMCR_t { 130typedef union _MI_BMCR_t {
@@ -200,30 +200,6 @@ typedef union _MI_BMSR_t {
200 } bits; 200 } bits;
201} MI_BMSR_t, *PMI_BMSR_t; 201} MI_BMSR_t, *PMI_BMSR_t;
202 202
203/* MI Register 2: Physical Identifier 1 */
204typedef union _MI_IDR1_t {
205 u16 value;
206 struct {
207 u16 ieee_address:16; /* 0x0282 default(bits 0-15) */
208 } bits;
209} MI_IDR1_t, *PMI_IDR1_t;
210
211/* MI Register 3: Physical Identifier 2 */
212typedef union _MI_IDR2_t {
213 u16 value;
214 struct {
215#ifdef _BIT_FIELDS_HTOL
216 u16 ieee_address:6; /* 111100 default(bits 10-15) */
217 u16 model_no:6; /* 000001 default(bits 4-9) */
218 u16 rev_no:4; /* 0010 default(bits 0-3) */
219#else
220 u16 rev_no:4; /* 0010 default(bits 0-3) */
221 u16 model_no:6; /* 000001 default(bits 4-9) */
222 u16 ieee_address:6; /* 111100 default(bits 10-15) */
223#endif
224 } bits;
225} MI_IDR2_t, *PMI_IDR2_t;
226
227/* MI Register 4: Auto-negotiation advertisement register */ 203/* MI Register 4: Auto-negotiation advertisement register */
228typedef union _MI_ANAR_t { 204typedef union _MI_ANAR_t {
229 u16 value; 205 u16 value;
@@ -258,481 +234,194 @@ typedef union _MI_ANAR_t {
258 } bits; 234 } bits;
259} MI_ANAR_t, *PMI_ANAR_t; 235} MI_ANAR_t, *PMI_ANAR_t;
260 236
261/* MI Register 5: Auto-negotiation link partner advertisement register */ 237/* MI Register 5: Auto-negotiation link partner advertisement register
262typedef struct _MI_ANLPAR_t { 238 * 15: np_indication
263 u16 value; 239 * 14: acknowledge
264 struct { 240 * 13: remote_fault
265#ifdef _BIT_FIELDS_HTOL 241 * 12: res1:1;
266 u16 np_indication:1; /* bit 15 */ 242 * 11: cap_asmpause
267 u16 acknowledge:1; /* bit 14 */ 243 * 10: cap_pause
268 u16 remote_fault:1; /* bit 13 */ 244 * 9: cap_100T4
269 u16 res1:1; /* bit 12 */ 245 * 8: cap_100fdx
270 u16 cap_asmpause:1; /* bit 11 */ 246 * 7: cap_100hdx
271 u16 cap_pause:1; /* bit 10 */ 247 * 6: cap_10fdx
272 u16 cap_100T4:1; /* bit 9 */ 248 * 5: cap_10hdx
273 u16 cap_100fdx:1; /* bit 8 */ 249 * 4-0: selector
274 u16 cap_100hdx:1; /* bit 7 */ 250 */
275 u16 cap_10fdx:1; /* bit 6 */
276 u16 cap_10hdx:1; /* bit 5 */
277 u16 selector:5; /* bits 0-4 */
278#else
279 u16 selector:5; /* bits 0-4 */
280 u16 cap_10hdx:1; /* bit 5 */
281 u16 cap_10fdx:1; /* bit 6 */
282 u16 cap_100hdx:1; /* bit 7 */
283 u16 cap_100fdx:1; /* bit 8 */
284 u16 cap_100T4:1; /* bit 9 */
285 u16 cap_pause:1; /* bit 10 */
286 u16 cap_asmpause:1; /* bit 11 */
287 u16 res1:1; /* bit 12 */
288 u16 remote_fault:1; /* bit 13 */
289 u16 acknowledge:1; /* bit 14 */
290 u16 np_indication:1; /* bit 15 */
291#endif
292 } bits;
293} MI_ANLPAR_t, *PMI_ANLPAR_t;
294 251
295/* MI Register 6: Auto-negotiation expansion register */ 252/* MI Register 6: Auto-negotiation expansion register
296typedef union _MI_ANER_t { 253 * 15-5: reserved
297 u16 value; 254 * 4: pdf
298 struct { 255 * 3: lp_np_able
299#ifdef _BIT_FIELDS_HTOL 256 * 2: np_able
300 u16 res:11; /* bits 5-15 */ 257 * 1: page_rx
301 u16 pdf:1; /* bit 4 */ 258 * 0: lp_an_able
302 u16 lp_np_able:1; /* bit 3 */ 259 */
303 u16 np_able:1; /* bit 2 */
304 u16 page_rx:1; /* bit 1 */
305 u16 lp_an_able:1; /* bit 0 */
306#else
307 u16 lp_an_able:1; /* bit 0 */
308 u16 page_rx:1; /* bit 1 */
309 u16 np_able:1; /* bit 2 */
310 u16 lp_np_able:1; /* bit 3 */
311 u16 pdf:1; /* bit 4 */
312 u16 res:11; /* bits 5-15 */
313#endif
314 } bits;
315} MI_ANER_t, *PMI_ANER_t;
316 260
317/* MI Register 7: Auto-negotiation next page transmit reg(0x07) */ 261/* MI Register 7: Auto-negotiation next page transmit reg(0x07)
318typedef union _MI_ANNPTR_t { 262 * 15: np
319 u16 value; 263 * 14: reserved
320 struct { 264 * 13: msg_page
321#ifdef _BIT_FIELDS_HTOL 265 * 12: ack2
322 u16 np:1; /* bit 15 */ 266 * 11: toggle
323 u16 res1:1; /* bit 14 */ 267 * 10-0 msg
324 u16 msg_page:1; /* bit 13 */ 268 */
325 u16 ack2:1; /* bit 12 */
326 u16 toggle:1; /* bit 11 */
327 u16 msg:11; /* bits 0-10 */
328#else
329 u16 msg:11; /* bits 0-10 */
330 u16 toggle:1; /* bit 11 */
331 u16 ack2:1; /* bit 12 */
332 u16 msg_page:1; /* bit 13 */
333 u16 res1:1; /* bit 14 */
334 u16 np:1; /* bit 15 */
335#endif
336 } bits;
337} MI_ANNPTR_t, *PMI_ANNPTR_t;
338 269
339/* MI Register 8: Link Partner Next Page Reg(0x08) */ 270/* MI Register 8: Link Partner Next Page Reg(0x08)
340typedef union _MI_LPNPR_t { 271 * 15: np
341 u16 value; 272 * 14: ack
342 struct { 273 * 13: msg_page
343#ifdef _BIT_FIELDS_HTOL 274 * 12: ack2
344 u16 np:1; /* bit 15 */ 275 * 11: toggle
345 u16 ack:1; /* bit 14 */ 276 * 10-0: msg
346 u16 msg_page:1; /* bit 13 */ 277 */
347 u16 ack2:1; /* bit 12 */
348 u16 toggle:1; /* bit 11 */
349 u16 msg:11; /* bits 0-10 */
350#else
351 u16 msg:11; /* bits 0-10 */
352 u16 toggle:1; /* bit 11 */
353 u16 ack2:1; /* bit 12 */
354 u16 msg_page:1; /* bit 13 */
355 u16 ack:1; /* bit 14 */
356 u16 np:1; /* bit 15 */
357#endif
358 } bits;
359} MI_LPNPR_t, *PMI_LPNPR_t;
360 278
361/* MI Register 9: 1000BaseT Control Reg(0x09) */ 279/* MI Register 9: 1000BaseT Control Reg(0x09)
362typedef union _MI_GCR_t { 280 * 15-13: test_mode
363 u16 value; 281 * 12: ms_config_en
364 struct { 282 * 11: ms_value
365#ifdef _BIT_FIELDS_HTOL 283 * 10: port_type
366 u16 test_mode:3; /* bits 13-15 */ 284 * 9: link_1000fdx
367 u16 ms_config_en:1; /* bit 12 */ 285 * 8: link_1000hdx
368 u16 ms_value:1; /* bit 11 */ 286 * 7-0: reserved
369 u16 port_type:1; /* bit 10 */ 287 */
370 u16 link_1000fdx:1; /* bit 9 */
371 u16 link_1000hdx:1; /* bit 8 */
372 u16 res:8; /* bit 0-7 */
373#else
374 u16 res:8; /* bit 0-7 */
375 u16 link_1000hdx:1; /* bit 8 */
376 u16 link_1000fdx:1; /* bit 9 */
377 u16 port_type:1; /* bit 10 */
378 u16 ms_value:1; /* bit 11 */
379 u16 ms_config_en:1; /* bit 12 */
380 u16 test_mode:3; /* bits 13-15 */
381#endif
382 } bits;
383} MI_GCR_t, *PMI_GCR_t;
384 288
385/* MI Register 10: 1000BaseT Status Reg(0x0A) */ 289/* MI Register 10: 1000BaseT Status Reg(0x0A)
386typedef union _MI_GSR_t { 290 * 15: ms_config_fault
387 u16 value; 291 * 14: ms_resolve
388 struct { 292 * 13: local_rx_status
389#ifdef _BIT_FIELDS_HTOL 293 * 12: remote_rx_status
390 u16 ms_config_fault:1; /* bit 15 */ 294 * 11: link_1000fdx
391 u16 ms_resolve:1; /* bit 14 */ 295 * 10: link_1000hdx
392 u16 local_rx_status:1; /* bit 13 */ 296 * 9-8: reserved
393 u16 remote_rx_status:1; /* bit 12 */ 297 * 7-0: idle_err_cnt
394 u16 link_1000fdx:1; /* bit 11 */ 298 */
395 u16 link_1000hdx:1; /* bit 10 */
396 u16 res:2; /* bits 8-9 */
397 u16 idle_err_cnt:8; /* bits 0-7 */
398#else
399 u16 idle_err_cnt:8; /* bits 0-7 */
400 u16 res:2; /* bits 8-9 */
401 u16 link_1000hdx:1; /* bit 10 */
402 u16 link_1000fdx:1; /* bit 11 */
403 u16 remote_rx_status:1; /* bit 12 */
404 u16 local_rx_status:1; /* bit 13 */
405 u16 ms_resolve:1; /* bit 14 */
406 u16 ms_config_fault:1; /* bit 15 */
407#endif
408 } bits;
409} MI_GSR_t, *PMI_GSR_t;
410 299
411/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */ 300/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
412typedef union _MI_RES_t {
413 u16 value;
414 struct {
415#ifdef _BIT_FIELDS_HTOL
416 u16 res15:1; /* bit 15 */
417 u16 res14:1; /* bit 14 */
418 u16 res13:1; /* bit 13 */
419 u16 res12:1; /* bit 12 */
420 u16 res11:1; /* bit 11 */
421 u16 res10:1; /* bit 10 */
422 u16 res9:1; /* bit 9 */
423 u16 res8:1; /* bit 8 */
424 u16 res7:1; /* bit 7 */
425 u16 res6:1; /* bit 6 */
426 u16 res5:1; /* bit 5 */
427 u16 res4:1; /* bit 4 */
428 u16 res3:1; /* bit 3 */
429 u16 res2:1; /* bit 2 */
430 u16 res1:1; /* bit 1 */
431 u16 res0:1; /* bit 0 */
432#else
433 u16 res0:1; /* bit 0 */
434 u16 res1:1; /* bit 1 */
435 u16 res2:1; /* bit 2 */
436 u16 res3:1; /* bit 3 */
437 u16 res4:1; /* bit 4 */
438 u16 res5:1; /* bit 5 */
439 u16 res6:1; /* bit 6 */
440 u16 res7:1; /* bit 7 */
441 u16 res8:1; /* bit 8 */
442 u16 res9:1; /* bit 9 */
443 u16 res10:1; /* bit 10 */
444 u16 res11:1; /* bit 11 */
445 u16 res12:1; /* bit 12 */
446 u16 res13:1; /* bit 13 */
447 u16 res14:1; /* bit 14 */
448 u16 res15:1; /* bit 15 */
449#endif
450 } bits;
451} MI_RES_t, *PMI_RES_t;
452 301
453/* MI Register 15: Extended status Reg(0x0F) */ 302/* MI Register 15: Extended status Reg(0x0F)
454typedef union _MI_ESR_t { 303 * 15: link_1000Xfdx
455 u16 value; 304 * 14: link_1000Xhdx
456 struct { 305 * 13: link_1000fdx
457#ifdef _BIT_FIELDS_HTOL 306 * 12: link_1000hdx
458 u16 link_1000Xfdx:1; /* bit 15 */ 307 * 11-0: reserved
459 u16 link_1000Xhdx:1; /* bit 14 */ 308 */
460 u16 link_1000fdx:1; /* bit 13 */
461 u16 link_1000hdx:1; /* bit 12 */
462 u16 res:12; /* bit 0-11 */
463#else
464 u16 res:12; /* bit 0-11 */
465 u16 link_1000hdx:1; /* bit 12 */
466 u16 link_1000fdx:1; /* bit 13 */
467 u16 link_1000Xhdx:1; /* bit 14 */
468 u16 link_1000Xfdx:1; /* bit 15 */
469#endif
470 } bits;
471} MI_ESR_t, *PMI_ESR_t;
472 309
473/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */ 310/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
474 311
475/* MI Register 19: Loopback Control Reg(0x13) */ 312/* MI Register 19: Loopback Control Reg(0x13)
476typedef union _MI_LCR_t { 313 * 15: mii_en
477 u16 value; 314 * 14: pcs_en
478 struct { 315 * 13: pmd_en
479#ifdef _BIT_FIELDS_HTOL 316 * 12: all_digital_en
480 u16 mii_en:1; /* bit 15 */ 317 * 11: replica_en
481 u16 pcs_en:1; /* bit 14 */ 318 * 10: line_driver_en
482 u16 pmd_en:1; /* bit 13 */ 319 * 9-0: reserved
483 u16 all_digital_en:1; /* bit 12 */ 320 */
484 u16 replica_en:1; /* bit 11 */
485 u16 line_driver_en:1; /* bit 10 */
486 u16 res:10; /* bit 0-9 */
487#else
488 u16 res:10; /* bit 0-9 */
489 u16 line_driver_en:1; /* bit 10 */
490 u16 replica_en:1; /* bit 11 */
491 u16 all_digital_en:1; /* bit 12 */
492 u16 pmd_en:1; /* bit 13 */
493 u16 pcs_en:1; /* bit 14 */
494 u16 mii_en:1; /* bit 15 */
495#endif
496 } bits;
497} MI_LCR_t, *PMI_LCR_t;
498 321
499/* MI Register 20: Reserved Reg(0x14) */ 322/* MI Register 20: Reserved Reg(0x14) */
500 323
501/* MI Register 21: Management Interface Control Reg(0x15) */ 324/* MI Register 21: Management Interface Control Reg(0x15)
502typedef union _MI_MICR_t { 325 * 15-11: reserved
503 u16 value; 326 * 10-4: mi_error_count
504 struct { 327 * 3: reserved
505#ifdef _BIT_FIELDS_HTOL 328 * 2: ignore_10g_fr
506 u16 res1:5; /* bits 11-15 */ 329 * 1: reserved
507 u16 mi_error_count:7; /* bits 4-10 */ 330 * 0: preamble_supress_en
508 u16 res2:1; /* bit 3 */ 331 */
509 u16 ignore_10g_fr:1; /* bit 2 */
510 u16 res3:1; /* bit 1 */
511 u16 preamble_supress_en:1; /* bit 0 */
512#else
513 u16 preamble_supress_en:1; /* bit 0 */
514 u16 res3:1; /* bit 1 */
515 u16 ignore_10g_fr:1; /* bit 2 */
516 u16 res2:1; /* bit 3 */
517 u16 mi_error_count:7; /* bits 4-10 */
518 u16 res1:5; /* bits 11-15 */
519#endif
520 } bits;
521} MI_MICR_t, *PMI_MICR_t;
522 332
523/* MI Register 22: PHY Configuration Reg(0x16) */ 333/* MI Register 22: PHY Configuration Reg(0x16)
524typedef union _MI_PHY_CONFIG_t { 334 * 15: crs_tx_en
525 u16 value; 335 * 14: reserved
526 struct { 336 * 13-12: tx_fifo_depth
527#ifdef _BIT_FIELDS_HTOL 337 * 11-10: speed_downshift
528 u16 crs_tx_en:1; /* bit 15 */ 338 * 9: pbi_detect
529 u16 res1:1; /* bit 14 */ 339 * 8: tbi_rate
530 u16 tx_fifo_depth:2; /* bits 12-13 */ 340 * 7: alternate_np
531 u16 speed_downshift:2; /* bits 10-11 */ 341 * 6: group_mdio_en
532 u16 pbi_detect:1; /* bit 9 */ 342 * 5: tx_clock_en
533 u16 tbi_rate:1; /* bit 8 */ 343 * 4: sys_clock_en
534 u16 alternate_np:1; /* bit 7 */ 344 * 3: reserved
535 u16 group_mdio_en:1; /* bit 6 */ 345 * 2-0: mac_if_mode
536 u16 tx_clock_en:1; /* bit 5 */ 346 */
537 u16 sys_clock_en:1; /* bit 4 */
538 u16 res2:1; /* bit 3 */
539 u16 mac_if_mode:3; /* bits 0-2 */
540#else
541 u16 mac_if_mode:3; /* bits 0-2 */
542 u16 res2:1; /* bit 3 */
543 u16 sys_clock_en:1; /* bit 4 */
544 u16 tx_clock_en:1; /* bit 5 */
545 u16 group_mdio_en:1; /* bit 6 */
546 u16 alternate_np:1; /* bit 7 */
547 u16 tbi_rate:1; /* bit 8 */
548 u16 pbi_detect:1; /* bit 9 */
549 u16 speed_downshift:2; /* bits 10-11 */
550 u16 tx_fifo_depth:2; /* bits 12-13 */
551 u16 res1:1; /* bit 14 */
552 u16 crs_tx_en:1; /* bit 15 */
553#endif
554 } bits;
555} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
556 347
557/* MI Register 23: PHY CONTROL Reg(0x17) */ 348/* MI Register 23: PHY CONTROL Reg(0x17)
558typedef union _MI_PHY_CONTROL_t { 349 * 15: reserved
559 u16 value; 350 * 14: tdr_en
560 struct { 351 * 13: reserved
561#ifdef _BIT_FIELDS_HTOL 352 * 12-11: downshift_attempts
562 u16 res1:1; /* bit 15 */ 353 * 10-6: reserved
563 u16 tdr_en:1; /* bit 14 */ 354 * 5: jabber_10baseT
564 u16 res2:1; /* bit 13 */ 355 * 4: sqe_10baseT
565 u16 downshift_attempts:2; /* bits 11-12 */ 356 * 3: tp_loopback_10baseT
566 u16 res3:5; /* bit 6-10 */ 357 * 2: preamble_gen_en
567 u16 jabber_10baseT:1; /* bit 5 */ 358 * 1: reserved
568 u16 sqe_10baseT:1; /* bit 4 */ 359 * 0: force_int
569 u16 tp_loopback_10baseT:1; /* bit 3 */ 360 */
570 u16 preamble_gen_en:1; /* bit 2 */
571 u16 res4:1; /* bit 1 */
572 u16 force_int:1; /* bit 0 */
573#else
574 u16 force_int:1; /* bit 0 */
575 u16 res4:1; /* bit 1 */
576 u16 preamble_gen_en:1; /* bit 2 */
577 u16 tp_loopback_10baseT:1; /* bit 3 */
578 u16 sqe_10baseT:1; /* bit 4 */
579 u16 jabber_10baseT:1; /* bit 5 */
580 u16 res3:5; /* bit 6-10 */
581 u16 downshift_attempts:2; /* bits 11-12 */
582 u16 res2:1; /* bit 13 */
583 u16 tdr_en:1; /* bit 14 */
584 u16 res1:1; /* bit 15 */
585#endif
586 } bits;
587} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
588 361
589/* MI Register 24: Interrupt Mask Reg(0x18) */ 362/* MI Register 24: Interrupt Mask Reg(0x18)
590typedef union _MI_IMR_t { 363 * 15-10: reserved
591 u16 value; 364 * 9: mdio_sync_lost
592 struct { 365 * 8: autoneg_status
593#ifdef _BIT_FIELDS_HTOL 366 * 7: hi_bit_err
594 u16 res1:6; /* bits 10-15 */ 367 * 6: np_rx
595 u16 mdio_sync_lost:1; /* bit 9 */ 368 * 5: err_counter_full
596 u16 autoneg_status:1; /* bit 8 */ 369 * 4: fifo_over_underflow
597 u16 hi_bit_err:1; /* bit 7 */ 370 * 3: rx_status
598 u16 np_rx:1; /* bit 6 */ 371 * 2: link_status
599 u16 err_counter_full:1; /* bit 5 */ 372 * 1: automatic_speed
600 u16 fifo_over_underflow:1; /* bit 4 */ 373 * 0: int_en
601 u16 rx_status:1; /* bit 3 */ 374 */
602 u16 link_status:1; /* bit 2 */
603 u16 automatic_speed:1; /* bit 1 */
604 u16 int_en:1; /* bit 0 */
605#else
606 u16 int_en:1; /* bit 0 */
607 u16 automatic_speed:1; /* bit 1 */
608 u16 link_status:1; /* bit 2 */
609 u16 rx_status:1; /* bit 3 */
610 u16 fifo_over_underflow:1; /* bit 4 */
611 u16 err_counter_full:1; /* bit 5 */
612 u16 np_rx:1; /* bit 6 */
613 u16 hi_bit_err:1; /* bit 7 */
614 u16 autoneg_status:1; /* bit 8 */
615 u16 mdio_sync_lost:1; /* bit 9 */
616 u16 res1:6; /* bits 10-15 */
617#endif
618 } bits;
619} MI_IMR_t, *PMI_IMR_t;
620 375
621/* MI Register 25: Interrupt Status Reg(0x19) */
622typedef union _MI_ISR_t {
623 u16 value;
624 struct {
625#ifdef _BIT_FIELDS_HTOL
626 u16 res1:6; /* bits 10-15 */
627 u16 mdio_sync_lost:1; /* bit 9 */
628 u16 autoneg_status:1; /* bit 8 */
629 u16 hi_bit_err:1; /* bit 7 */
630 u16 np_rx:1; /* bit 6 */
631 u16 err_counter_full:1; /* bit 5 */
632 u16 fifo_over_underflow:1; /* bit 4 */
633 u16 rx_status:1; /* bit 3 */
634 u16 link_status:1; /* bit 2 */
635 u16 automatic_speed:1; /* bit 1 */
636 u16 int_en:1; /* bit 0 */
637#else
638 u16 int_en:1; /* bit 0 */
639 u16 automatic_speed:1; /* bit 1 */
640 u16 link_status:1; /* bit 2 */
641 u16 rx_status:1; /* bit 3 */
642 u16 fifo_over_underflow:1; /* bit 4 */
643 u16 err_counter_full:1; /* bit 5 */
644 u16 np_rx:1; /* bit 6 */
645 u16 hi_bit_err:1; /* bit 7 */
646 u16 autoneg_status:1; /* bit 8 */
647 u16 mdio_sync_lost:1; /* bit 9 */
648 u16 res1:6; /* bits 10-15 */
649#endif
650 } bits;
651} MI_ISR_t, *PMI_ISR_t;
652 376
653/* MI Register 26: PHY Status Reg(0x1A) */ 377/* MI Register 25: Interrupt Status Reg(0x19)
654typedef union _MI_PSR_t { 378 * 15-10: reserved
655 u16 value; 379 * 9: mdio_sync_lost
656 struct { 380 * 8: autoneg_status
657#ifdef _BIT_FIELDS_HTOL 381 * 7: hi_bit_err
658 u16 res1:1; /* bit 15 */ 382 * 6: np_rx
659 u16 autoneg_fault:2; /* bit 13-14 */ 383 * 5: err_counter_full
660 u16 autoneg_status:1; /* bit 12 */ 384 * 4: fifo_over_underflow
661 u16 mdi_x_status:1; /* bit 11 */ 385 * 3: rx_status
662 u16 polarity_status:1; /* bit 10 */ 386 * 2: link_status
663 u16 speed_status:2; /* bits 8-9 */ 387 * 1: automatic_speed
664 u16 duplex_status:1; /* bit 7 */ 388 * 0: int_en
665 u16 link_status:1; /* bit 6 */ 389 */
666 u16 tx_status:1; /* bit 5 */
667 u16 rx_status:1; /* bit 4 */
668 u16 collision_status:1; /* bit 3 */
669 u16 autoneg_en:1; /* bit 2 */
670 u16 pause_en:1; /* bit 1 */
671 u16 asymmetric_dir:1; /* bit 0 */
672#else
673 u16 asymmetric_dir:1; /* bit 0 */
674 u16 pause_en:1; /* bit 1 */
675 u16 autoneg_en:1; /* bit 2 */
676 u16 collision_status:1; /* bit 3 */
677 u16 rx_status:1; /* bit 4 */
678 u16 tx_status:1; /* bit 5 */
679 u16 link_status:1; /* bit 6 */
680 u16 duplex_status:1; /* bit 7 */
681 u16 speed_status:2; /* bits 8-9 */
682 u16 polarity_status:1; /* bit 10 */
683 u16 mdi_x_status:1; /* bit 11 */
684 u16 autoneg_status:1; /* bit 12 */
685 u16 autoneg_fault:2; /* bit 13-14 */
686 u16 res1:1; /* bit 15 */
687#endif
688 } bits;
689} MI_PSR_t, *PMI_PSR_t;
690 390
691/* MI Register 27: LED Control Reg 1(0x1B) */ 391/* MI Register 26: PHY Status Reg(0x1A)
692typedef union _MI_LCR1_t { 392 * 15: reserved
693 u16 value; 393 * 14-13: autoneg_fault
694 struct { 394 * 12: autoneg_status
695#ifdef _BIT_FIELDS_HTOL 395 * 11: mdi_x_status
696 u16 res1:2; /* bits 14-15 */ 396 * 10: polarity_status
697 u16 led_dup_indicate:2; /* bits 12-13 */ 397 * 9-8: speed_status
698 u16 led_10baseT:2; /* bits 10-11 */ 398 * 7: duplex_status
699 u16 led_collision:2; /* bits 8-9 */ 399 * 6: link_status
700 u16 res2:2; /* bits 6-7 */ 400 * 5: tx_status
701 u16 res3:2; /* bits 4-5 */ 401 * 4: rx_status
702 u16 pulse_dur:2; /* bits 2-3 */ 402 * 3: collision_status
703 u16 pulse_stretch1:1; /* bit 1 */ 403 * 2: autoneg_en
704 u16 pulse_stretch0:1; /* bit 0 */ 404 * 1: pause_en
705#else 405 * 0: asymmetric_dir
706 u16 pulse_stretch0:1; /* bit 0 */ 406 */
707 u16 pulse_stretch1:1; /* bit 1 */
708 u16 pulse_dur:2; /* bits 2-3 */
709 u16 res3:2; /* bits 4-5 */
710 u16 res2:2; /* bits 6-7 */
711 u16 led_collision:2; /* bits 8-9 */
712 u16 led_10baseT:2; /* bits 10-11 */
713 u16 led_dup_indicate:2; /* bits 12-13 */
714 u16 res1:2; /* bits 14-15 */
715#endif
716 } bits;
717} MI_LCR1_t, *PMI_LCR1_t;
718 407
719/* MI Register 28: LED Control Reg 2(0x1C) */ 408/* MI Register 27: LED Control Reg 1(0x1B)
720typedef union _MI_LCR2_t { 409 * 15-14: reserved
721 u16 value; 410 * 13-12: led_dup_indicate
722 struct { 411 * 11-10: led_10baseT
723#ifdef _BIT_FIELDS_HTOL 412 * 9-8: led_collision
724 u16 led_link:4; /* bits 12-15 */ 413 * 7-4: reserved
725 u16 led_tx_rx:4; /* bits 8-11 */ 414 * 3-2: pulse_dur
726 u16 led_100BaseTX:4; /* bits 4-7 */ 415 * 1: pulse_stretch1
727 u16 led_1000BaseT:4; /* bits 0-3 */ 416 * 0: pulse_stretch0
728#else 417 */
729 u16 led_1000BaseT:4; /* bits 0-3 */ 418
730 u16 led_100BaseTX:4; /* bits 4-7 */ 419/* MI Register 28: LED Control Reg 2(0x1C)
731 u16 led_tx_rx:4; /* bits 8-11 */ 420 * 15-12: led_link
732 u16 led_link:4; /* bits 12-15 */ 421 * 11-8: led_tx_rx
733#endif 422 * 7-4: led_100BaseTX
734 } bits; 423 * 3-0: led_1000BaseT
735} MI_LCR2_t, *PMI_LCR2_t; 424 */
736 425
737/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */ 426/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
738 427
diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c
index 0cc6c68fdfd..ce4d9304267 100644
--- a/drivers/staging/et131x/et131x_isr.c
+++ b/drivers/staging/et131x/et131x_isr.c
@@ -366,7 +366,7 @@ void et131x_isr_handler(struct work_struct *work)
366 if (status & ET_INTR_PHY) { 366 if (status & ET_INTR_PHY) {
367 u32 pm_csr; 367 u32 pm_csr;
368 MI_BMSR_t BmsrInts, BmsrData; 368 MI_BMSR_t BmsrInts, BmsrData;
369 MI_ISR_t myIsr; 369 u16 myisr;
370 370
371 /* If we are in coma mode when we get this interrupt, 371 /* If we are in coma mode when we get this interrupt,
372 * we need to disable it. 372 * we need to disable it.
@@ -384,12 +384,12 @@ void et131x_isr_handler(struct work_struct *work)
384 /* Read the PHY ISR to clear the reason for the 384 /* Read the PHY ISR to clear the reason for the
385 * interrupt. 385 * interrupt.
386 */ 386 */
387 MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr), 387 MiRead(etdev, (uint8_t) offsetof(struct mi_regs, isr),
388 &myIsr.value); 388 &myisr);
389 389
390 if (!etdev->ReplicaPhyLoopbk) { 390 if (!etdev->ReplicaPhyLoopbk) {
391 MiRead(etdev, 391 MiRead(etdev,
392 (uint8_t) offsetof(MI_REGS_t, bmsr), 392 (uint8_t) offsetof(struct mi_regs, bmsr),
393 &BmsrData.value); 393 &BmsrData.value);
394 394
395 BmsrInts.value = 395 BmsrInts.value =
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 17:38:39 -0400