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authorJerry Chuang <wlanfae@realtek.com>2009-05-22 01:16:02 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-06-19 14:00:53 -0400
commit5f53d8ca3d5d6afa55011e1e858a4bf255a3abf4 (patch)
tree5dfc036b97b9e68336298a61384e86f619d361e8 /drivers/staging
parentd01c3c8e13f7be29fae5b55bbd4a01d6f84d3d5e (diff)
Staging: add rtl8192SU wireless usb driver
Driver from Realtek for the Realtek RTL8192 USB wifi device Based on the r8187 driver from Andrea Merello <andreamrl@tiscali.it> and others. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/rtl8192su/Kconfig6
-rw-r--r--drivers/staging/rtl8192su/Makefile66
-rw-r--r--drivers/staging/rtl8192su/authors1
-rw-r--r--drivers/staging/rtl8192su/dot11d.h102
-rw-r--r--drivers/staging/rtl8192su/ieee80211.h2901
-rw-r--r--drivers/staging/rtl8192su/ieee80211/EndianFree.h199
-rw-r--r--drivers/staging/rtl8192su/ieee80211/Makefile31
-rw-r--r--drivers/staging/rtl8192su/ieee80211/aes.c469
-rw-r--r--drivers/staging/rtl8192su/ieee80211/api.c246
-rw-r--r--drivers/staging/rtl8192su/ieee80211/arc4.c103
-rw-r--r--drivers/staging/rtl8192su/ieee80211/autoload.c40
-rw-r--r--drivers/staging/rtl8192su/ieee80211/cipher.c299
-rw-r--r--drivers/staging/rtl8192su/ieee80211/compress.c64
-rw-r--r--drivers/staging/rtl8192su/ieee80211/crypto_compat.h90
-rw-r--r--drivers/staging/rtl8192su/ieee80211/digest.c108
-rw-r--r--drivers/staging/rtl8192su/ieee80211/dot11d.c239
-rw-r--r--drivers/staging/rtl8192su/ieee80211/dot11d.h102
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211.h2901
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c273
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h93
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c534
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c1034
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c397
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_module.c394
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c2832
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c3580
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c711
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c947
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c1032
-rw-r--r--drivers/staging/rtl8192su/ieee80211/internal.h115
-rw-r--r--drivers/staging/rtl8192su/ieee80211/kmap_types.h20
-rw-r--r--drivers/staging/rtl8192su/ieee80211/michael_mic.c194
-rw-r--r--drivers/staging/rtl8192su/ieee80211/proc.c116
-rw-r--r--drivers/staging/rtl8192su/ieee80211/readme162
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h69
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c781
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h517
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c2037
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h749
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h56
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c667
-rw-r--r--drivers/staging/rtl8192su/ieee80211/rtl_crypto.h399
-rw-r--r--drivers/staging/rtl8192su/ieee80211/scatterwalk.c126
-rw-r--r--drivers/staging/rtl8192su/ieee80211/scatterwalk.h51
-rw-r--r--drivers/staging/rtl8192su/ieee80211_crypt.h86
-rw-r--r--drivers/staging/rtl8192su/r8180_93cx6.c146
-rw-r--r--drivers/staging/rtl8192su/r8180_93cx6.h45
-rw-r--r--drivers/staging/rtl8192su/r8190_rtl8256.c312
-rw-r--r--drivers/staging/rtl8192su/r8190_rtl8256.h27
-rw-r--r--drivers/staging/rtl8192su/r8192SU_HWImg.c4902
-rw-r--r--drivers/staging/rtl8192su/r8192SU_HWImg.h44
-rw-r--r--drivers/staging/rtl8192su/r8192S_Efuse.c2442
-rw-r--r--drivers/staging/rtl8192su/r8192S_Efuse.h101
-rw-r--r--drivers/staging/rtl8192su/r8192S_FwImgDTM.h3797
-rw-r--r--drivers/staging/rtl8192su/r8192S_firmware.c1023
-rw-r--r--drivers/staging/rtl8192su/r8192S_firmware.h212
-rw-r--r--drivers/staging/rtl8192su/r8192S_hw.h1677
-rw-r--r--drivers/staging/rtl8192su/r8192S_phy.c5028
-rw-r--r--drivers/staging/rtl8192su/r8192S_phy.h138
-rw-r--r--drivers/staging/rtl8192su/r8192S_phyreg.h1033
-rw-r--r--drivers/staging/rtl8192su/r8192S_rtl6052.c946
-rw-r--r--drivers/staging/rtl8192su/r8192S_rtl6052.h134
-rw-r--r--drivers/staging/rtl8192su/r8192S_rtl8225.c292
-rw-r--r--drivers/staging/rtl8192su/r8192S_rtl8225.h30
-rw-r--r--drivers/staging/rtl8192su/r8192U.h2112
-rw-r--r--drivers/staging/rtl8192su/r8192U_core.c12460
-rw-r--r--drivers/staging/rtl8192su/r8192U_dm.c4521
-rw-r--r--drivers/staging/rtl8192su/r8192U_dm.h309
-rw-r--r--drivers/staging/rtl8192su/r8192U_hw.h746
-rw-r--r--drivers/staging/rtl8192su/r8192U_pm.c77
-rw-r--r--drivers/staging/rtl8192su/r8192U_pm.h27
-rw-r--r--drivers/staging/rtl8192su/r8192U_wx.c1350
-rw-r--r--drivers/staging/rtl8192su/r8192U_wx.h23
-rw-r--r--drivers/staging/rtl8192su/r819xU_HTGen.h22
-rw-r--r--drivers/staging/rtl8192su/r819xU_HTType.h392
-rw-r--r--drivers/staging/rtl8192su/r819xU_cmdpkt.c826
-rw-r--r--drivers/staging/rtl8192su/r819xU_cmdpkt.h219
-rw-r--r--drivers/staging/rtl8192su/r819xU_firmware.c707
-rw-r--r--drivers/staging/rtl8192su/r819xU_firmware.h106
-rw-r--r--drivers/staging/rtl8192su/r819xU_firmware_img.c3447
-rw-r--r--drivers/staging/rtl8192su/r819xU_firmware_img.h35
-rw-r--r--drivers/staging/rtl8192su/r819xU_phy.c1826
-rw-r--r--drivers/staging/rtl8192su/r819xU_phy.h94
-rw-r--r--drivers/staging/rtl8192su/r819xU_phyreg.h871
86 files changed, 78441 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index f9371ab9d08..07998730d8e 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -85,6 +85,8 @@ source "drivers/staging/altpciechdma/Kconfig"
85 85
86source "drivers/staging/rtl8187se/Kconfig" 86source "drivers/staging/rtl8187se/Kconfig"
87 87
88source "drivers/staging/rtl8192su/Kconfig"
89
88source "drivers/staging/rspiusb/Kconfig" 90source "drivers/staging/rspiusb/Kconfig"
89 91
90source "drivers/staging/mimio/Kconfig" 92source "drivers/staging/mimio/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index d6bafe2ff9c..8fb84310bb3 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_ASUS_OLED) += asus_oled/
25obj-$(CONFIG_PANEL) += panel/ 25obj-$(CONFIG_PANEL) += panel/
26obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma/ 26obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma/
27obj-$(CONFIG_RTL8187SE) += rtl8187se/ 27obj-$(CONFIG_RTL8187SE) += rtl8187se/
28obj-$(CONFIG_RTL8192SU) += rtl8192su/
28obj-$(CONFIG_USB_RSPI) += rspiusb/ 29obj-$(CONFIG_USB_RSPI) += rspiusb/
29obj-$(CONFIG_INPUT_MIMIO) += mimio/ 30obj-$(CONFIG_INPUT_MIMIO) += mimio/
30obj-$(CONFIG_TRANZPORT) += frontier/ 31obj-$(CONFIG_TRANZPORT) += frontier/
diff --git a/drivers/staging/rtl8192su/Kconfig b/drivers/staging/rtl8192su/Kconfig
new file mode 100644
index 00000000000..4b5552c5926
--- /dev/null
+++ b/drivers/staging/rtl8192su/Kconfig
@@ -0,0 +1,6 @@
1config RTL8192SU
2 tristate "RealTek RTL8192SU Wireless LAN NIC driver"
3 depends on PCI
4 depends on WIRELESS_EXT && COMPAT_NET_DEV_OPS
5 default N
6 ---help---
diff --git a/drivers/staging/rtl8192su/Makefile b/drivers/staging/rtl8192su/Makefile
new file mode 100644
index 00000000000..f010ab502a9
--- /dev/null
+++ b/drivers/staging/rtl8192su/Makefile
@@ -0,0 +1,66 @@
1NIC_SELECT = RTL8192SU
2
3EXTRA_CFLAGS += -std=gnu89
4EXTRA_CFLAGS += -O2
5EXTRA_CFLAGS += -mhard-float -DCONFIG_FORCE_HARD_FLOAT=y
6
7EXTRA_CFLAGS += -DJACKSON_NEW_RX
8EXTRA_CFLAGS += -DTHOMAS_BEACON -DTHOMAS_TURBO
9#EXTRA_CFLAGS += -DUSE_ONE_PIPE
10EXTRA_CFLAGS += -DENABLE_DOT11D
11
12EXTRA_CFLAGS += -DRTL8192SU
13EXTRA_CFLAGS += -DRTL8190_Download_Firmware_From_Header=1
14EXTRA_CFLAGS += -DRTL8192S_PREPARE_FOR_NORMAL_RELEASE
15EXTRA_CFLAGS += -DRTL8192SU_DISABLE_IQK=1
16
17#EXTRA_CFLAGS += -DEEPROM_OLD_FORMAT_SUPPORT
18
19#EXTRA_CFLAGS += -DUSB_RX_AGGREGATION_SUPPORT=0
20#EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE=0
21#EXTRA_CFLAGS += -DRTL8192SU_DISABLE_CCK_RATE=0
22EXTRA_CFLAGS += -DRTL8192S_DISABLE_FW_DM=0
23EXTRA_CFLAGS += -DDISABLE_BB_RF=0
24EXTRA_CFLAGS += -DRTL8192SU_USE_PARAM_TXPWR=0
25EXTRA_CFLAGS += -DRTL8192SU_FPGA_UNSPECIFIED_NETWORK=0
26#EXTRA_CFLAGS += -DRTL8192SU_FPGA_2MAC_VERIFICATION #=0
27EXTRA_CFLAGS += -DRTL8192SU_ASIC_VERIFICATION
28EXTRA_CFLAGS += -DRTL8192SU_USB_PHY_TEST=0
29
30#EXTRA_CFLAGS += -DMUTIPLE_BULK_OUT
31EXTRA_CFLAGS += -DCONFIG_RTL8192_PM
32
33r8192s_usb-objs := \
34 r8180_93cx6.o \
35 r8192U_wx.o \
36 r8192S_phy.o \
37 r8192S_rtl6052.o \
38 r8192S_rtl8225.o \
39 r819xU_cmdpkt.o \
40 r8192U_dm.o \
41 r8192SU_HWImg.o \
42 r8192S_firmware.o \
43 r8192S_Efuse.o \
44 r8192U_core.o \
45 r8192U_pm.o
46
47ieee80211-rsl-objs := \
48 ieee80211/ieee80211_rx.o \
49 ieee80211/ieee80211_softmac.o \
50 ieee80211/ieee80211_tx.o \
51 ieee80211/ieee80211_wx.o \
52 ieee80211/ieee80211_module.o \
53 ieee80211/ieee80211_softmac_wx.o\
54 ieee80211/rtl819x_HTProc.o \
55 ieee80211/rtl819x_TSProc.o \
56 ieee80211/rtl819x_BAProc.o \
57 ieee80211/dot11d.o
58
59obj-$(CONFIG_RTL8192SU) += r8192s_usb.o
60obj-$(CONFIG_RTL8192SU) += ieee80211-rsl.o
61obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt.o
62obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_tkip.o
63obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_ccmp.o
64obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_wep.o
65
66
diff --git a/drivers/staging/rtl8192su/authors b/drivers/staging/rtl8192su/authors
new file mode 100644
index 00000000000..b08bbae39e7
--- /dev/null
+++ b/drivers/staging/rtl8192su/authors
@@ -0,0 +1 @@
Andrea Merello <andreamrl@tiscali.it>
diff --git a/drivers/staging/rtl8192su/dot11d.h b/drivers/staging/rtl8192su/dot11d.h
new file mode 100644
index 00000000000..15b7a4ba37b
--- /dev/null
+++ b/drivers/staging/rtl8192su/dot11d.h
@@ -0,0 +1,102 @@
1#ifndef __INC_DOT11D_H
2#define __INC_DOT11D_H
3
4#ifdef ENABLE_DOT11D
5#include "ieee80211.h"
6
7//#define ENABLE_DOT11D
8
9//#define DOT11D_MAX_CHNL_NUM 83
10
11typedef struct _CHNL_TXPOWER_TRIPLE {
12 u8 FirstChnl;
13 u8 NumChnls;
14 u8 MaxTxPowerInDbm;
15}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE;
16
17typedef enum _DOT11D_STATE {
18 DOT11D_STATE_NONE = 0,
19 DOT11D_STATE_LEARNED,
20 DOT11D_STATE_DONE,
21}DOT11D_STATE;
22
23typedef struct _RT_DOT11D_INFO {
24 //DECLARE_RT_OBJECT(RT_DOT11D_INFO);
25
26 bool bEnabled; // dot11MultiDomainCapabilityEnabled
27
28 u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element.
29 u8 CountryIeBuf[MAX_IE_LEN];
30 u8 CountryIeSrcAddr[6]; // Source AP of the country IE.
31 u8 CountryIeWatchdog;
32
33 u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan)
34 //u8 ChnlListLen; // #Bytes valid in ChnlList[].
35 //u8 ChnlList[DOT11D_MAX_CHNL_NUM];
36 u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1];
37
38 DOT11D_STATE State;
39}RT_DOT11D_INFO, *PRT_DOT11D_INFO;
40#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
41#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
42#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo))
43
44#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled
45#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0)
46
47#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
48#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
49
50#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \
51 (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \
52 FALSE : \
53 (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length)))
54
55#define CIE_WATCHDOG_TH 1
56#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog
57#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0
58#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev)
59
60#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)
61
62
63void
64Dot11d_Init(
65 struct ieee80211_device *dev
66 );
67
68void
69Dot11d_Reset(
70 struct ieee80211_device *dev
71 );
72
73void
74Dot11d_UpdateCountryIe(
75 struct ieee80211_device *dev,
76 u8 * pTaddr,
77 u16 CoutryIeLen,
78 u8 * pCoutryIe
79 );
80
81u8
82DOT11D_GetMaxTxPwrInDbm(
83 struct ieee80211_device *dev,
84 u8 Channel
85 );
86
87void
88DOT11D_ScanComplete(
89 struct ieee80211_device * dev
90 );
91
92int IsLegalChannel(
93 struct ieee80211_device * dev,
94 u8 channel
95);
96
97int ToLegalChannel(
98 struct ieee80211_device * dev,
99 u8 channel
100);
101#endif //ENABLE_DOT11D
102#endif // #ifndef __INC_DOT11D_H
diff --git a/drivers/staging/rtl8192su/ieee80211.h b/drivers/staging/rtl8192su/ieee80211.h
new file mode 100644
index 00000000000..0edb09a536f
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211.h
@@ -0,0 +1,2901 @@
1/*
2 * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11
3 * remains copyright by the original authors
4 *
5 * Portions of the merged code are based on Host AP (software wireless
6 * LAN access point) driver for Intersil Prism2/2.5/3.
7 *
8 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
9 * <jkmaline@cc.hut.fi>
10 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
11 *
12 * Adaption to a generic IEEE 802.11 stack by James Ketrenos
13 * <jketreno@linux.intel.com>
14 * Copyright (c) 2004, Intel Corporation
15 *
16 * Modified for Realtek's wi-fi cards by Andrea Merello
17 * <andreamrl@tiscali.it>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation. See README and COPYING for
22 * more details.
23 */
24#ifndef IEEE80211_H
25#define IEEE80211_H
26#include <linux/if_ether.h> /* ETH_ALEN */
27#include <linux/kernel.h> /* ARRAY_SIZE */
28#include <linux/version.h>
29#include <linux/module.h>
30#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
31#include <linux/jiffies.h>
32#else
33#include <linux/jffs.h>
34#include <linux/tqueue.h>
35#endif
36#include <linux/timer.h>
37#include <linux/sched.h>
38
39#include <linux/delay.h>
40#include <linux/wireless.h>
41
42#include "ieee80211/rtl819x_HT.h"
43#include "ieee80211/rtl819x_BA.h"
44#include "ieee80211/rtl819x_TS.h"
45
46#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
47#ifndef bool
48typedef enum{false = 0, true} bool;
49#endif
50#endif
51
52#ifndef IW_MODE_MONITOR
53#define IW_MODE_MONITOR 6
54#endif
55
56#ifndef IWEVCUSTOM
57#define IWEVCUSTOM 0x8c02
58#endif
59
60#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
61#ifndef __bitwise
62#define __bitwise __attribute__((bitwise))
63#endif
64typedef __u16 __le16;
65#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27))
66struct iw_spy_data{
67 /* --- Standard spy support --- */
68 int spy_number;
69 u_char spy_address[IW_MAX_SPY][ETH_ALEN];
70 struct iw_quality spy_stat[IW_MAX_SPY];
71 /* --- Enhanced spy support (event) */
72 struct iw_quality spy_thr_low; /* Low threshold */
73 struct iw_quality spy_thr_high; /* High threshold */
74 u_char spy_thr_under[IW_MAX_SPY];
75};
76#endif
77#endif
78
79#ifndef container_of
80/**
81 * container_of - cast a member of a structure out to the containing structure
82 *
83 * @ptr: the pointer to the member.
84 * @type: the type of the container struct this is embedded in.
85 * @member: the name of the member within the struct.
86 *
87 */
88#define container_of(ptr, type, member) ({ \
89 const typeof( ((type *)0)->member ) *__mptr = (ptr); \
90 (type *)( (char *)__mptr - offsetof(type,member) );})
91#endif
92
93#define KEY_TYPE_NA 0x0
94#define KEY_TYPE_WEP40 0x1
95#define KEY_TYPE_TKIP 0x2
96#define KEY_TYPE_CCMP 0x4
97#define KEY_TYPE_WEP104 0x5
98
99/* added for rtl819x tx procedure */
100#define MAX_QUEUE_SIZE 0x10
101
102//
103// 8190 queue mapping
104//
105#define BK_QUEUE 0
106#define BE_QUEUE 1
107#define VI_QUEUE 2
108#define VO_QUEUE 3
109#define HCCA_QUEUE 4
110#define TXCMD_QUEUE 5
111#define MGNT_QUEUE 6
112#define HIGH_QUEUE 7
113#define BEACON_QUEUE 8
114
115#define LOW_QUEUE BE_QUEUE
116#define NORMAL_QUEUE MGNT_QUEUE
117
118//added by amy for ps
119#define SWRF_TIMEOUT 50
120
121//added by amy for LEAP related
122#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0.
123#define SUPPORT_CKIP_MIC 0x08 // bit3
124#define SUPPORT_CKIP_PK 0x10 // bit4
125//added by amy for ps
126// RF Off Level for IPS or HW/SW radio off
127#define RT_RF_OFF_LEVL_ASPM BIT0 // PCI ASPM
128#define RT_RF_OFF_LEVL_CLK_REQ BIT1 // PCI clock request
129#define RT_RF_OFF_LEVL_PCI_D3 BIT2 // PCI D3 mode
130#define RT_RF_OFF_LEVL_HALT_NIC BIT3 // NIC halt, re-initialize hw parameters
131#define RT_RF_OFF_LEVL_FREE_FW BIT4 // FW free, re-download the FW
132#define RT_RF_OFF_LEVL_FW_32K BIT5 // FW in 32k
133#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6 // Always enable ASPM and Clock Req in initialization.
134#define RT_RF_LPS_DISALBE_2R BIT30 // When LPS is on, disable 2R if no packet is received or transmittd.
135#define RT_RF_LPS_LEVEL_ASPM BIT31 // LPS with ASPM
136#define RT_IN_PS_LEVEL(pPSC, _PS_FLAG) ((pPSC->CurPsLevel & _PS_FLAG) ? true : false)
137#define RT_CLEAR_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel &= (~(_PS_FLAG)))
138#define RT_SET_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel->CurPsLevel |= _PS_FLAG)
139/* defined for skb cb field */
140/* At most 28 byte */
141typedef struct cb_desc {
142 /* Tx Desc Related flags (8-9) */
143 u8 bLastIniPkt:1;
144 u8 bCmdOrInit:1;
145 u8 bFirstSeg:1;
146 u8 bLastSeg:1;
147 u8 bEncrypt:1;
148 u8 bTxDisableRateFallBack:1;
149 u8 bTxUseDriverAssingedRate:1;
150 u8 bHwSec:1; //indicate whether use Hw security. WB
151
152 u8 reserved1;
153
154 /* Tx Firmware Relaged flags (10-11)*/
155 u8 bCTSEnable:1;
156 u8 bRTSEnable:1;
157 u8 bUseShortGI:1;
158 u8 bUseShortPreamble:1;
159 u8 bTxEnableFwCalcDur:1;
160 u8 bAMPDUEnable:1;
161 u8 bRTSSTBC:1;
162 u8 RTSSC:1;
163
164 u8 bRTSBW:1;
165 u8 bPacketBW:1;
166 u8 bRTSUseShortPreamble:1;
167 u8 bRTSUseShortGI:1;
168 u8 bMulticast:1;
169 u8 bBroadcast:1;
170 //u8 reserved2:2;
171 u8 drv_agg_enable:1;
172 u8 reserved2:1;
173
174 /* Tx Desc related element(12-19) */
175 u8 rata_index;
176 u8 queue_index;
177 //u8 reserved3;
178 //u8 reserved4;
179 u16 txbuf_size;
180 //u8 reserved5;
181 u8 RATRIndex;
182 u8 reserved6;
183 u8 reserved7;
184 u8 reserved8;
185
186 /* Tx firmware related element(20-27) */
187 u8 data_rate;
188 u8 rts_rate;
189 u8 ampdu_factor;
190 u8 ampdu_density;
191 //u8 reserved9;
192 //u8 reserved10;
193 //u8 reserved11;
194 u8 DrvAggrNum;
195 u16 pkt_size;
196 u8 reserved12;
197}cb_desc, *pcb_desc;
198
199/*--------------------------Define -------------------------------------------*/
200#define MGN_1M 0x02
201#define MGN_2M 0x04
202#define MGN_5_5M 0x0b
203#define MGN_11M 0x16
204
205#define MGN_6M 0x0c
206#define MGN_9M 0x12
207#define MGN_12M 0x18
208#define MGN_18M 0x24
209#define MGN_24M 0x30
210#define MGN_36M 0x48
211#define MGN_48M 0x60
212#define MGN_54M 0x6c
213
214#define MGN_MCS0 0x80
215#define MGN_MCS1 0x81
216#define MGN_MCS2 0x82
217#define MGN_MCS3 0x83
218#define MGN_MCS4 0x84
219#define MGN_MCS5 0x85
220#define MGN_MCS6 0x86
221#define MGN_MCS7 0x87
222#define MGN_MCS8 0x88
223#define MGN_MCS9 0x89
224#define MGN_MCS10 0x8a
225#define MGN_MCS11 0x8b
226#define MGN_MCS12 0x8c
227#define MGN_MCS13 0x8d
228#define MGN_MCS14 0x8e
229#define MGN_MCS15 0x8f
230#define MGN_MCS0_SG 0x90
231#define MGN_MCS1_SG 0x91
232#define MGN_MCS2_SG 0x92
233#define MGN_MCS3_SG 0x93
234#define MGN_MCS4_SG 0x94
235#define MGN_MCS5_SG 0x95
236#define MGN_MCS6_SG 0x96
237#define MGN_MCS7_SG 0x97
238#define MGN_MCS8_SG 0x98
239#define MGN_MCS9_SG 0x99
240#define MGN_MCS10_SG 0x9a
241#define MGN_MCS11_SG 0x9b
242#define MGN_MCS12_SG 0x9c
243#define MGN_MCS13_SG 0x9d
244#define MGN_MCS14_SG 0x9e
245#define MGN_MCS15_SG 0x9f
246
247
248//----------------------------------------------------------------------------
249// 802.11 Management frame Reason Code field
250//----------------------------------------------------------------------------
251enum _ReasonCode{
252 unspec_reason = 0x1,
253 auth_not_valid = 0x2,
254 deauth_lv_ss = 0x3,
255 inactivity = 0x4,
256 ap_overload = 0x5,
257 class2_err = 0x6,
258 class3_err = 0x7,
259 disas_lv_ss = 0x8,
260 asoc_not_auth = 0x9,
261
262 //----MIC_CHECK
263 mic_failure = 0xe,
264 //----END MIC_CHECK
265
266 // Reason code defined in 802.11i D10.0 p.28.
267 invalid_IE = 0x0d,
268 four_way_tmout = 0x0f,
269 two_way_tmout = 0x10,
270 IE_dismatch = 0x11,
271 invalid_Gcipher = 0x12,
272 invalid_Pcipher = 0x13,
273 invalid_AKMP = 0x14,
274 unsup_RSNIEver = 0x15,
275 invalid_RSNIE = 0x16,
276 auth_802_1x_fail= 0x17,
277 ciper_reject = 0x18,
278
279 // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15.
280 QoS_unspec = 0x20, // 32
281 QAP_bandwidth = 0x21, // 33
282 poor_condition = 0x22, // 34
283 no_facility = 0x23, // 35
284 // Where is 36???
285 req_declined = 0x25, // 37
286 invalid_param = 0x26, // 38
287 req_not_honored= 0x27, // 39
288 TS_not_created = 0x2F, // 47
289 DL_not_allowed = 0x30, // 48
290 dest_not_exist = 0x31, // 49
291 dest_not_QSTA = 0x32, // 50
292};
293
294
295
296#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10)
297
298#define MGMT_QUEUE_NUM 5
299
300#define IEEE_CMD_SET_WPA_PARAM 1
301#define IEEE_CMD_SET_WPA_IE 2
302#define IEEE_CMD_SET_ENCRYPTION 3
303#define IEEE_CMD_MLME 4
304
305#define IEEE_PARAM_WPA_ENABLED 1
306#define IEEE_PARAM_TKIP_COUNTERMEASURES 2
307#define IEEE_PARAM_DROP_UNENCRYPTED 3
308#define IEEE_PARAM_PRIVACY_INVOKED 4
309#define IEEE_PARAM_AUTH_ALGS 5
310#define IEEE_PARAM_IEEE_802_1X 6
311//It should consistent with the driver_XXX.c
312// David, 2006.9.26
313#define IEEE_PARAM_WPAX_SELECT 7
314//Added for notify the encryption type selection
315// David, 2006.9.26
316#define IEEE_PROTO_WPA 1
317#define IEEE_PROTO_RSN 2
318//Added for notify the encryption type selection
319// David, 2006.9.26
320#define IEEE_WPAX_USEGROUP 0
321#define IEEE_WPAX_WEP40 1
322#define IEEE_WPAX_TKIP 2
323#define IEEE_WPAX_WRAP 3
324#define IEEE_WPAX_CCMP 4
325#define IEEE_WPAX_WEP104 5
326
327#define IEEE_KEY_MGMT_IEEE8021X 1
328#define IEEE_KEY_MGMT_PSK 2
329
330#define IEEE_MLME_STA_DEAUTH 1
331#define IEEE_MLME_STA_DISASSOC 2
332
333
334#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2
335#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3
336#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4
337#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5
338#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6
339#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7
340
341
342#define IEEE_CRYPT_ALG_NAME_LEN 16
343
344#define MAX_IE_LEN 0xff
345
346// added for kernel conflict
347#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl
348#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl
349#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl
350#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl
351#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl
352#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl
353
354#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl
355
356#define ieee80211_tkip_null ieee80211_tkip_null_rsl
357
358#define ieee80211_wep_null ieee80211_wep_null_rsl
359
360#define free_ieee80211 free_ieee80211_rsl
361#define alloc_ieee80211 alloc_ieee80211_rsl
362
363#define ieee80211_rx ieee80211_rx_rsl
364#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl
365
366#define ieee80211_get_beacon ieee80211_get_beacon_rsl
367#define ieee80211_wake_queue ieee80211_wake_queue_rsl
368#define ieee80211_stop_queue ieee80211_stop_queue_rsl
369#define ieee80211_reset_queue ieee80211_reset_queue_rsl
370#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl
371#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl
372#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl
373#define ieee80211_is_54g ieee80211_is_54g_rsl
374#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl
375#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl
376#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl
377#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl
378#define notify_wx_assoc_event notify_wx_assoc_event_rsl
379#define SendDisassociation SendDisassociation_rsl
380#define ieee80211_disassociate ieee80211_disassociate_rsl
381#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl
382#define ieee80211_stop_scan ieee80211_stop_scan_rsl
383#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl
384#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl
385#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl
386
387#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl
388#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl
389#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl
390#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl
391#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl
392#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl
393#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl
394#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl
395#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl
396#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl
397#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl
398#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl
399#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl
400#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl
401#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl
402#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl
403#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl
404#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl
405
406#define ieee80211_txb_free ieee80211_txb_free_rsl
407
408#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl
409#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl
410#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl
411#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl
412#if WIRELESS_EXT >= 18
413#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl
414#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl
415#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl
416#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl
417#endif
418
419
420typedef struct ieee_param {
421 u32 cmd;
422 u8 sta_addr[ETH_ALEN];
423 union {
424 struct {
425 u8 name;
426 u32 value;
427 } wpa_param;
428 struct {
429 u32 len;
430 u8 reserved[32];
431 u8 data[0];
432 } wpa_ie;
433 struct{
434 int command;
435 int reason_code;
436 } mlme;
437 struct {
438 u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
439 u8 set_tx;
440 u32 err;
441 u8 idx;
442 u8 seq[8]; /* sequence counter (set: RX, get: TX) */
443 u16 key_len;
444 u8 key[0];
445 } crypt;
446 } u;
447}ieee_param;
448
449
450#if WIRELESS_EXT < 17
451#define IW_QUAL_QUAL_INVALID 0x10
452#define IW_QUAL_LEVEL_INVALID 0x20
453#define IW_QUAL_NOISE_INVALID 0x40
454#define IW_QUAL_QUAL_UPDATED 0x1
455#define IW_QUAL_LEVEL_UPDATED 0x2
456#define IW_QUAL_NOISE_UPDATED 0x4
457#endif
458
459#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
460static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data)
461{
462 task->routine = func;
463 task->data = data;
464 //task->next = NULL;
465 INIT_LIST_HEAD(&task->list);
466 task->sync = 0;
467}
468#endif
469
470// linux under 2.6.9 release may not support it, so modify it for common use
471#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
472//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ)
473#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
474static inline unsigned long msleep_interruptible_rsl(unsigned int msecs)
475{
476 unsigned long timeout = MSECS(msecs) + 1;
477
478 while (timeout) {
479 set_current_state(TASK_INTERRUPTIBLE);
480 timeout = schedule_timeout(timeout);
481 }
482 return timeout;
483}
484#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31))
485static inline void msleep(unsigned int msecs)
486{
487 unsigned long timeout = MSECS(msecs) + 1;
488
489 while (timeout) {
490 set_current_state(TASK_UNINTERRUPTIBLE);
491 timeout = schedule_timeout(timeout);
492 }
493}
494#endif
495#else
496#define MSECS(t) msecs_to_jiffies(t)
497#define msleep_interruptible_rsl msleep_interruptible
498#endif
499
500#define IEEE80211_DATA_LEN 2304
501/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
502 6.2.1.1.2.
503
504 The figure in section 7.1.2 suggests a body size of up to 2312
505 bytes is allowed, which is a bit confusing, I suspect this
506 represents the 2304 bytes of real data, plus a possible 8 bytes of
507 WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
508#define IEEE80211_1ADDR_LEN 10
509#define IEEE80211_2ADDR_LEN 16
510#define IEEE80211_3ADDR_LEN 24
511#define IEEE80211_4ADDR_LEN 30
512#define IEEE80211_FCS_LEN 4
513#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
514#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
515#define IEEE80211_MGMT_HDR_LEN 24
516#define IEEE80211_DATA_HDR3_LEN 24
517#define IEEE80211_DATA_HDR4_LEN 30
518
519#define MIN_FRAG_THRESHOLD 256U
520#define MAX_FRAG_THRESHOLD 2346U
521
522
523/* Frame control field constants */
524#define IEEE80211_FCTL_VERS 0x0003
525#define IEEE80211_FCTL_FTYPE 0x000c
526#define IEEE80211_FCTL_STYPE 0x00f0
527#define IEEE80211_FCTL_FRAMETYPE 0x00fc
528#define IEEE80211_FCTL_TODS 0x0100
529#define IEEE80211_FCTL_FROMDS 0x0200
530#define IEEE80211_FCTL_DSTODS 0x0300 //added by david
531#define IEEE80211_FCTL_MOREFRAGS 0x0400
532#define IEEE80211_FCTL_RETRY 0x0800
533#define IEEE80211_FCTL_PM 0x1000
534#define IEEE80211_FCTL_MOREDATA 0x2000
535#define IEEE80211_FCTL_WEP 0x4000
536#define IEEE80211_FCTL_ORDER 0x8000
537
538#define IEEE80211_FTYPE_MGMT 0x0000
539#define IEEE80211_FTYPE_CTL 0x0004
540#define IEEE80211_FTYPE_DATA 0x0008
541
542/* management */
543#define IEEE80211_STYPE_ASSOC_REQ 0x0000
544#define IEEE80211_STYPE_ASSOC_RESP 0x0010
545#define IEEE80211_STYPE_REASSOC_REQ 0x0020
546#define IEEE80211_STYPE_REASSOC_RESP 0x0030
547#define IEEE80211_STYPE_PROBE_REQ 0x0040
548#define IEEE80211_STYPE_PROBE_RESP 0x0050
549#define IEEE80211_STYPE_BEACON 0x0080
550#define IEEE80211_STYPE_ATIM 0x0090
551#define IEEE80211_STYPE_DISASSOC 0x00A0
552#define IEEE80211_STYPE_AUTH 0x00B0
553#define IEEE80211_STYPE_DEAUTH 0x00C0
554#define IEEE80211_STYPE_MANAGE_ACT 0x00D0
555
556/* control */
557#define IEEE80211_STYPE_PSPOLL 0x00A0
558#define IEEE80211_STYPE_RTS 0x00B0
559#define IEEE80211_STYPE_CTS 0x00C0
560#define IEEE80211_STYPE_ACK 0x00D0
561#define IEEE80211_STYPE_CFEND 0x00E0
562#define IEEE80211_STYPE_CFENDACK 0x00F0
563#define IEEE80211_STYPE_BLOCKACK 0x0094
564
565/* data */
566#define IEEE80211_STYPE_DATA 0x0000
567#define IEEE80211_STYPE_DATA_CFACK 0x0010
568#define IEEE80211_STYPE_DATA_CFPOLL 0x0020
569#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030
570#define IEEE80211_STYPE_NULLFUNC 0x0040
571#define IEEE80211_STYPE_CFACK 0x0050
572#define IEEE80211_STYPE_CFPOLL 0x0060
573#define IEEE80211_STYPE_CFACKPOLL 0x0070
574#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2
575#define IEEE80211_STYPE_QOS_NULL 0x00C0
576
577#define IEEE80211_SCTL_FRAG 0x000F
578#define IEEE80211_SCTL_SEQ 0xFFF0
579
580/* QOS control */
581#define IEEE80211_QCTL_TID 0x000F
582
583#define FC_QOS_BIT BIT7
584#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false )
585#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) )
586//added by wb. Is this right?
587#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA))
588#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER)
589#define SN_LESS(a, b) (((a-b)&0x800)!=0)
590#define SN_EQUAL(a, b) (a == b)
591#define MAX_DEV_ADDR_SIZE 8
592typedef enum _ACT_CATEGORY{
593 ACT_CAT_QOS = 1,
594 ACT_CAT_DLS = 2,
595 ACT_CAT_BA = 3,
596 ACT_CAT_HT = 7,
597 ACT_CAT_WMM = 17,
598} ACT_CATEGORY, *PACT_CATEGORY;
599
600typedef enum _TS_ACTION{
601 ACT_ADDTSREQ = 0,
602 ACT_ADDTSRSP = 1,
603 ACT_DELTS = 2,
604 ACT_SCHEDULE = 3,
605} TS_ACTION, *PTS_ACTION;
606
607typedef enum _BA_ACTION{
608 ACT_ADDBAREQ = 0,
609 ACT_ADDBARSP = 1,
610 ACT_DELBA = 2,
611} BA_ACTION, *PBA_ACTION;
612
613typedef enum _InitialGainOpType{
614 IG_Backup=0,
615 IG_Restore,
616 IG_Max
617}InitialGainOpType;
618//added by amy for LED 090319
619//================================================================================
620// LED customization.
621//================================================================================
622typedef enum _LED_CTL_MODE{
623 LED_CTL_POWER_ON = 1,
624 LED_CTL_LINK = 2,
625 LED_CTL_NO_LINK = 3,
626 LED_CTL_TX = 4,
627 LED_CTL_RX = 5,
628 LED_CTL_SITE_SURVEY = 6,
629 LED_CTL_POWER_OFF = 7,
630 LED_CTL_START_TO_LINK = 8,
631 LED_CTL_START_WPS = 9,
632 LED_CTL_STOP_WPS = 10,
633 LED_CTL_START_WPS_BOTTON = 11, //added for runtop
634}LED_CTL_MODE;
635
636/* debug macros */
637#define CONFIG_IEEE80211_DEBUG
638#ifdef CONFIG_IEEE80211_DEBUG
639extern u32 ieee80211_debug_level;
640#define IEEE80211_DEBUG(level, fmt, args...) \
641do { if (ieee80211_debug_level & (level)) \
642 printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0)
643//wb added to debug out data buf
644//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
645#define IEEE80211_DEBUG_DATA(level, data, datalen) \
646 do{ if ((ieee80211_debug_level & (level)) == (level)) \
647 { \
648 int i; \
649 u8* pdata = (u8*) data; \
650 printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \
651 for(i=0; i<(int)(datalen); i++) \
652 { \
653 printk("%2x ", pdata[i]); \
654 if ((i+1)%16 == 0) printk("\n"); \
655 } \
656 printk("\n"); \
657 } \
658 } while (0)
659#else
660#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0)
661#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0)
662#endif /* CONFIG_IEEE80211_DEBUG */
663
664/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */
665
666#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
667#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
668
669/*
670 * To use the debug system;
671 *
672 * If you are defining a new debug classification, simply add it to the #define
673 * list here in the form of:
674 *
675 * #define IEEE80211_DL_xxxx VALUE
676 *
677 * shifting value to the left one bit from the previous entry. xxxx should be
678 * the name of the classification (for example, WEP)
679 *
680 * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your
681 * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want
682 * to send output to that classification.
683 *
684 * To add your debug level to the list of levels seen when you perform
685 *
686 * % cat /proc/net/ipw/debug_level
687 *
688 * you simply need to add your entry to the ipw_debug_levels array.
689 *
690 * If you do not see debug_level in /proc/net/ipw then you do not have
691 * CONFIG_IEEE80211_DEBUG defined in your kernel configuration
692 *
693 */
694
695#define IEEE80211_DL_INFO (1<<0)
696#define IEEE80211_DL_WX (1<<1)
697#define IEEE80211_DL_SCAN (1<<2)
698#define IEEE80211_DL_STATE (1<<3)
699#define IEEE80211_DL_MGMT (1<<4)
700#define IEEE80211_DL_FRAG (1<<5)
701#define IEEE80211_DL_EAP (1<<6)
702#define IEEE80211_DL_DROP (1<<7)
703
704#define IEEE80211_DL_TX (1<<8)
705#define IEEE80211_DL_RX (1<<9)
706
707#define IEEE80211_DL_HT (1<<10) //HT
708#define IEEE80211_DL_BA (1<<11) //ba
709#define IEEE80211_DL_TS (1<<12) //TS
710#define IEEE80211_DL_QOS (1<<13)
711#define IEEE80211_DL_REORDER (1<<14)
712#define IEEE80211_DL_IOT (1<<15)
713#define IEEE80211_DL_IPS (1<<16)
714#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen
715#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out.
716#define IEEE80211_DL_ERR (1<<31) //always open
717#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a)
718#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a)
719#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a)
720
721#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a)
722#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a)
723#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a)
724#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a)
725#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a)
726#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a)
727#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a)
728#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a)
729#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a)
730#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a)
731
732#ifdef CONFIG_IEEE80211_DEBUG
733/* Added by Annie, 2005-11-22. */
734#define MAX_STR_LEN 64
735/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/
736#define PRINTABLE(_ch) (_ch>'!' && _ch<'~')
737#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \
738 if((_Comp) & level) \
739 { \
740 int __i; \
741 u8 buffer[MAX_STR_LEN]; \
742 int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
743 memset(buffer, 0, MAX_STR_LEN); \
744 memcpy(buffer, (u8 *)_Ptr, length ); \
745 for( __i=0; __i<MAX_STR_LEN; __i++ ) \
746 { \
747 if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
748 } \
749 buffer[length] = '\0'; \
750 printk("Rtl819x: "); \
751 printk(_TitleString); \
752 printk(": %d, <%s>\n", _Len, buffer); \
753 }
754#else
755#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0)
756#endif
757
758#include <linux/netdevice.h>
759#include <linux/if_arp.h> /* ARPHRD_ETHER */
760
761#ifndef WIRELESS_SPY
762#define WIRELESS_SPY // enable iwspy support
763#endif
764#include <net/iw_handler.h> // new driver API
765
766#ifndef ETH_P_PAE
767#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
768#endif /* ETH_P_PAE */
769
770#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
771
772#ifndef ETH_P_80211_RAW
773#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
774#endif
775
776/* IEEE 802.11 defines */
777
778#define P80211_OUI_LEN 3
779
780struct ieee80211_snap_hdr {
781
782 u8 dsap; /* always 0xAA */
783 u8 ssap; /* always 0xAA */
784 u8 ctrl; /* always 0x03 */
785 u8 oui[P80211_OUI_LEN]; /* organizational universal id */
786
787} __attribute__ ((packed));
788
789#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
790
791#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
792#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
793#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
794
795#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE)
796#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG)
797#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
798
799/* Authentication algorithms */
800#define WLAN_AUTH_OPEN 0
801#define WLAN_AUTH_SHARED_KEY 1
802#define WLAN_AUTH_LEAP 2
803
804#define WLAN_AUTH_CHALLENGE_LEN 128
805
806#define WLAN_CAPABILITY_BSS (1<<0)
807#define WLAN_CAPABILITY_IBSS (1<<1)
808#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
809#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
810#define WLAN_CAPABILITY_PRIVACY (1<<4)
811#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
812#define WLAN_CAPABILITY_PBCC (1<<6)
813#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
814#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
815#define WLAN_CAPABILITY_QOS (1<<9)
816#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
817#define WLAN_CAPABILITY_DSSS_OFDM (1<<13)
818
819/* 802.11g ERP information element */
820#define WLAN_ERP_NON_ERP_PRESENT (1<<0)
821#define WLAN_ERP_USE_PROTECTION (1<<1)
822#define WLAN_ERP_BARKER_PREAMBLE (1<<2)
823
824/* Status codes */
825enum ieee80211_statuscode {
826 WLAN_STATUS_SUCCESS = 0,
827 WLAN_STATUS_UNSPECIFIED_FAILURE = 1,
828 WLAN_STATUS_CAPS_UNSUPPORTED = 10,
829 WLAN_STATUS_REASSOC_NO_ASSOC = 11,
830 WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,
831 WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,
832 WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,
833 WLAN_STATUS_CHALLENGE_FAIL = 15,
834 WLAN_STATUS_AUTH_TIMEOUT = 16,
835 WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,
836 WLAN_STATUS_ASSOC_DENIED_RATES = 18,
837 /* 802.11b */
838 WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,
839 WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,
840 WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,
841 /* 802.11h */
842 WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,
843 WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,
844 WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,
845 /* 802.11g */
846 WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,
847 WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,
848 /* 802.11i */
849 WLAN_STATUS_INVALID_IE = 40,
850 WLAN_STATUS_INVALID_GROUP_CIPHER = 41,
851 WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,
852 WLAN_STATUS_INVALID_AKMP = 43,
853 WLAN_STATUS_UNSUPP_RSN_VERSION = 44,
854 WLAN_STATUS_INVALID_RSN_IE_CAP = 45,
855 WLAN_STATUS_CIPHER_SUITE_REJECTED = 46,
856};
857
858/* Reason codes */
859enum ieee80211_reasoncode {
860 WLAN_REASON_UNSPECIFIED = 1,
861 WLAN_REASON_PREV_AUTH_NOT_VALID = 2,
862 WLAN_REASON_DEAUTH_LEAVING = 3,
863 WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,
864 WLAN_REASON_DISASSOC_AP_BUSY = 5,
865 WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,
866 WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,
867 WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,
868 WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,
869 /* 802.11h */
870 WLAN_REASON_DISASSOC_BAD_POWER = 10,
871 WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,
872 /* 802.11i */
873 WLAN_REASON_INVALID_IE = 13,
874 WLAN_REASON_MIC_FAILURE = 14,
875 WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
876 WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,
877 WLAN_REASON_IE_DIFFERENT = 17,
878 WLAN_REASON_INVALID_GROUP_CIPHER = 18,
879 WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,
880 WLAN_REASON_INVALID_AKMP = 20,
881 WLAN_REASON_UNSUPP_RSN_VERSION = 21,
882 WLAN_REASON_INVALID_RSN_IE_CAP = 22,
883 WLAN_REASON_IEEE8021X_FAILED = 23,
884 WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
885};
886
887#define IEEE80211_STATMASK_SIGNAL (1<<0)
888#define IEEE80211_STATMASK_RSSI (1<<1)
889#define IEEE80211_STATMASK_NOISE (1<<2)
890#define IEEE80211_STATMASK_RATE (1<<3)
891#define IEEE80211_STATMASK_WEMASK 0x7
892
893#define IEEE80211_CCK_MODULATION (1<<0)
894#define IEEE80211_OFDM_MODULATION (1<<1)
895
896#define IEEE80211_24GHZ_BAND (1<<0)
897#define IEEE80211_52GHZ_BAND (1<<1)
898
899#define IEEE80211_CCK_RATE_LEN 4
900#define IEEE80211_CCK_RATE_1MB 0x02
901#define IEEE80211_CCK_RATE_2MB 0x04
902#define IEEE80211_CCK_RATE_5MB 0x0B
903#define IEEE80211_CCK_RATE_11MB 0x16
904#define IEEE80211_OFDM_RATE_LEN 8
905#define IEEE80211_OFDM_RATE_6MB 0x0C
906#define IEEE80211_OFDM_RATE_9MB 0x12
907#define IEEE80211_OFDM_RATE_12MB 0x18
908#define IEEE80211_OFDM_RATE_18MB 0x24
909#define IEEE80211_OFDM_RATE_24MB 0x30
910#define IEEE80211_OFDM_RATE_36MB 0x48
911#define IEEE80211_OFDM_RATE_48MB 0x60
912#define IEEE80211_OFDM_RATE_54MB 0x6C
913#define IEEE80211_BASIC_RATE_MASK 0x80
914
915#define IEEE80211_CCK_RATE_1MB_MASK (1<<0)
916#define IEEE80211_CCK_RATE_2MB_MASK (1<<1)
917#define IEEE80211_CCK_RATE_5MB_MASK (1<<2)
918#define IEEE80211_CCK_RATE_11MB_MASK (1<<3)
919#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4)
920#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5)
921#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6)
922#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7)
923#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8)
924#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9)
925#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
926#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
927
928#define IEEE80211_CCK_RATES_MASK 0x0000000F
929#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
930 IEEE80211_CCK_RATE_2MB_MASK)
931#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \
932 IEEE80211_CCK_RATE_5MB_MASK | \
933 IEEE80211_CCK_RATE_11MB_MASK)
934
935#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
936#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
937 IEEE80211_OFDM_RATE_12MB_MASK | \
938 IEEE80211_OFDM_RATE_24MB_MASK)
939#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \
940 IEEE80211_OFDM_RATE_9MB_MASK | \
941 IEEE80211_OFDM_RATE_18MB_MASK | \
942 IEEE80211_OFDM_RATE_36MB_MASK | \
943 IEEE80211_OFDM_RATE_48MB_MASK | \
944 IEEE80211_OFDM_RATE_54MB_MASK)
945#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
946 IEEE80211_CCK_DEFAULT_RATES_MASK)
947
948#define IEEE80211_NUM_OFDM_RATES 8
949#define IEEE80211_NUM_CCK_RATES 4
950#define IEEE80211_OFDM_SHIFT_MASK_A 4
951
952
953/* this is stolen and modified from the madwifi driver*/
954#define IEEE80211_FC0_TYPE_MASK 0x0c
955#define IEEE80211_FC0_TYPE_DATA 0x08
956#define IEEE80211_FC0_SUBTYPE_MASK 0xB0
957#define IEEE80211_FC0_SUBTYPE_QOS 0x80
958
959#define IEEE80211_QOS_HAS_SEQ(fc) \
960 (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \
961 (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS))
962
963/* this is stolen from ipw2200 driver */
964#define IEEE_IBSS_MAC_HASH_SIZE 31
965struct ieee_ibss_seq {
966 u8 mac[ETH_ALEN];
967 u16 seq_num[17];
968 u16 frag_num[17];
969 unsigned long packet_time[17];
970 struct list_head list;
971};
972
973/* NOTE: This data is for statistical purposes; not all hardware provides this
974 * information for frames received. Not setting these will not cause
975 * any adverse affects. */
976struct ieee80211_rx_stats {
977#if 1
978 u32 mac_time[2];
979 s8 rssi;
980 u8 signal;
981 u8 noise;
982 u16 rate; /* in 100 kbps */
983 u8 received_channel;
984 u8 control;
985 u8 mask;
986 u8 freq;
987 u16 len;
988 u64 tsf;
989 u32 beacon_time;
990 u8 nic_type;
991 u16 Length;
992 // u8 DataRate; // In 0.5 Mbps
993 u8 SignalQuality; // in 0-100 index.
994 s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation.
995 s8 RxPower; // in dBm Translate from PWdB
996 u8 SignalStrength; // in 0-100 index.
997 u16 bHwError:1;
998 u16 bCRC:1;
999 u16 bICV:1;
1000 u16 bShortPreamble:1;
1001 u16 Antenna:1; //for rtl8185
1002 u16 Decrypted:1; //for rtl8185, rtl8187
1003 u16 Wakeup:1; //for rtl8185
1004 u16 Reserved0:1; //for rtl8185
1005 u8 AGC;
1006 u32 TimeStampLow;
1007 u32 TimeStampHigh;
1008 bool bShift;
1009 bool bIsQosData; // Added by Annie, 2005-12-22.
1010 u8 UserPriority;
1011
1012 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
1013 //1Attention Please!!!<11n or 8190 specific code should be put below this line>
1014 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
1015
1016 u8 RxDrvInfoSize;
1017 u8 RxBufShift;
1018 bool bIsAMPDU;
1019 bool bFirstMPDU;
1020 bool bContainHTC;
1021 bool RxIs40MHzPacket;
1022 u32 RxPWDBAll;
1023 u8 RxMIMOSignalStrength[4]; // in 0~100 index
1024 s8 RxMIMOSignalQuality[2];
1025 bool bPacketMatchBSSID;
1026 bool bIsCCK;
1027 bool bPacketToSelf;
1028 //added by amy
1029 u8* virtual_address;
1030 u16 packetlength; // Total packet length: Must equal to sum of all FragLength
1031 u16 fraglength; // FragLength should equal to PacketLength in non-fragment case
1032 u16 fragoffset; // Data offset for this fragment
1033 u16 ntotalfrag;
1034 bool bisrxaggrsubframe;
1035 bool bPacketBeacon; //cosa add for rssi
1036 bool bToSelfBA; //cosa add for rssi
1037 char cck_adc_pwdb[4]; //cosa add for rx path selection
1038 u16 Seq_Num;
1039 u8 nTotalAggPkt; // Number of aggregated packets.
1040#endif
1041
1042};
1043
1044/* IEEE 802.11 requires that STA supports concurrent reception of at least
1045 * three fragmented frames. This define can be increased to support more
1046 * concurrent frames, but it should be noted that each entry can consume about
1047 * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
1048#define IEEE80211_FRAG_CACHE_LEN 4
1049
1050struct ieee80211_frag_entry {
1051 unsigned long first_frag_time;
1052 unsigned int seq;
1053 unsigned int last_frag;
1054 struct sk_buff *skb;
1055 u8 src_addr[ETH_ALEN];
1056 u8 dst_addr[ETH_ALEN];
1057};
1058
1059struct ieee80211_stats {
1060 unsigned int tx_unicast_frames;
1061 unsigned int tx_multicast_frames;
1062 unsigned int tx_fragments;
1063 unsigned int tx_unicast_octets;
1064 unsigned int tx_multicast_octets;
1065 unsigned int tx_deferred_transmissions;
1066 unsigned int tx_single_retry_frames;
1067 unsigned int tx_multiple_retry_frames;
1068 unsigned int tx_retry_limit_exceeded;
1069 unsigned int tx_discards;
1070 unsigned int rx_unicast_frames;
1071 unsigned int rx_multicast_frames;
1072 unsigned int rx_fragments;
1073 unsigned int rx_unicast_octets;
1074 unsigned int rx_multicast_octets;
1075 unsigned int rx_fcs_errors;
1076 unsigned int rx_discards_no_buffer;
1077 unsigned int tx_discards_wrong_sa;
1078 unsigned int rx_discards_undecryptable;
1079 unsigned int rx_message_in_msg_fragments;
1080 unsigned int rx_message_in_bad_msg_fragments;
1081};
1082
1083struct ieee80211_device;
1084
1085#include "ieee80211_crypt.h"
1086
1087#define SEC_KEY_1 (1<<0)
1088#define SEC_KEY_2 (1<<1)
1089#define SEC_KEY_3 (1<<2)
1090#define SEC_KEY_4 (1<<3)
1091#define SEC_ACTIVE_KEY (1<<4)
1092#define SEC_AUTH_MODE (1<<5)
1093#define SEC_UNICAST_GROUP (1<<6)
1094#define SEC_LEVEL (1<<7)
1095#define SEC_ENABLED (1<<8)
1096#define SEC_ENCRYPT (1<<9)
1097
1098#define SEC_LEVEL_0 0 /* None */
1099#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */
1100#define SEC_LEVEL_2 2 /* Level 1 + TKIP */
1101#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
1102#define SEC_LEVEL_3 4 /* Level 2 + CCMP */
1103
1104#define SEC_ALG_NONE 0
1105#define SEC_ALG_WEP 1
1106#define SEC_ALG_TKIP 2
1107#define SEC_ALG_CCMP 3
1108
1109#define WEP_KEYS 4
1110#define WEP_KEY_LEN 13
1111#define SCM_KEY_LEN 32
1112#define SCM_TEMPORAL_KEY_LENGTH 16
1113
1114struct ieee80211_security {
1115 u16 active_key:2,
1116 enabled:1,
1117 auth_mode:2,
1118 auth_algo:4,
1119 unicast_uses_group:1,
1120 encrypt:1;
1121 u8 key_sizes[WEP_KEYS];
1122 u8 keys[WEP_KEYS][SCM_KEY_LEN];
1123 u8 level;
1124 u16 flags;
1125} __attribute__ ((packed));
1126
1127
1128/*
1129 802.11 data frame from AP
1130 ,-------------------------------------------------------------------.
1131Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
1132 |------|------|---------|---------|---------|------|---------|------|
1133Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs |
1134 | | tion | (BSSID) | | | ence | data | |
1135 `-------------------------------------------------------------------'
1136Total: 28-2340 bytes
1137*/
1138
1139/* Management Frame Information Element Types */
1140enum ieee80211_mfie {
1141 MFIE_TYPE_SSID = 0,
1142 MFIE_TYPE_RATES = 1,
1143 MFIE_TYPE_FH_SET = 2,
1144 MFIE_TYPE_DS_SET = 3,
1145 MFIE_TYPE_CF_SET = 4,
1146 MFIE_TYPE_TIM = 5,
1147 MFIE_TYPE_IBSS_SET = 6,
1148 MFIE_TYPE_COUNTRY = 7,
1149 MFIE_TYPE_HOP_PARAMS = 8,
1150 MFIE_TYPE_HOP_TABLE = 9,
1151 MFIE_TYPE_REQUEST = 10,
1152 MFIE_TYPE_CHALLENGE = 16,
1153 MFIE_TYPE_POWER_CONSTRAINT = 32,
1154 MFIE_TYPE_POWER_CAPABILITY = 33,
1155 MFIE_TYPE_TPC_REQUEST = 34,
1156 MFIE_TYPE_TPC_REPORT = 35,
1157 MFIE_TYPE_SUPP_CHANNELS = 36,
1158 MFIE_TYPE_CSA = 37,
1159 MFIE_TYPE_MEASURE_REQUEST = 38,
1160 MFIE_TYPE_MEASURE_REPORT = 39,
1161 MFIE_TYPE_QUIET = 40,
1162 MFIE_TYPE_IBSS_DFS = 41,
1163 MFIE_TYPE_ERP = 42,
1164 MFIE_TYPE_RSN = 48,
1165 MFIE_TYPE_RATES_EX = 50,
1166 MFIE_TYPE_HT_CAP= 45,
1167 MFIE_TYPE_HT_INFO= 61,
1168 MFIE_TYPE_AIRONET=133,
1169 MFIE_TYPE_GENERIC = 221,
1170 MFIE_TYPE_QOS_PARAMETER = 222,
1171};
1172
1173/* Minimal header; can be used for passing 802.11 frames with sufficient
1174 * information to determine what type of underlying data type is actually
1175 * stored in the data. */
1176struct ieee80211_hdr {
1177 __le16 frame_ctl;
1178 __le16 duration_id;
1179 u8 payload[0];
1180} __attribute__ ((packed));
1181
1182struct ieee80211_hdr_1addr {
1183 __le16 frame_ctl;
1184 __le16 duration_id;
1185 u8 addr1[ETH_ALEN];
1186 u8 payload[0];
1187} __attribute__ ((packed));
1188
1189struct ieee80211_hdr_2addr {
1190 __le16 frame_ctl;
1191 __le16 duration_id;
1192 u8 addr1[ETH_ALEN];
1193 u8 addr2[ETH_ALEN];
1194 u8 payload[0];
1195} __attribute__ ((packed));
1196
1197struct ieee80211_hdr_3addr {
1198 __le16 frame_ctl;
1199 __le16 duration_id;
1200 u8 addr1[ETH_ALEN];
1201 u8 addr2[ETH_ALEN];
1202 u8 addr3[ETH_ALEN];
1203 __le16 seq_ctl;
1204 u8 payload[0];
1205} __attribute__ ((packed));
1206
1207struct ieee80211_hdr_4addr {
1208 __le16 frame_ctl;
1209 __le16 duration_id;
1210 u8 addr1[ETH_ALEN];
1211 u8 addr2[ETH_ALEN];
1212 u8 addr3[ETH_ALEN];
1213 __le16 seq_ctl;
1214 u8 addr4[ETH_ALEN];
1215 u8 payload[0];
1216} __attribute__ ((packed));
1217
1218struct ieee80211_hdr_3addrqos {
1219 __le16 frame_ctl;
1220 __le16 duration_id;
1221 u8 addr1[ETH_ALEN];
1222 u8 addr2[ETH_ALEN];
1223 u8 addr3[ETH_ALEN];
1224 __le16 seq_ctl;
1225 u8 payload[0];
1226 __le16 qos_ctl;
1227} __attribute__ ((packed));
1228
1229struct ieee80211_hdr_4addrqos {
1230 __le16 frame_ctl;
1231 __le16 duration_id;
1232 u8 addr1[ETH_ALEN];
1233 u8 addr2[ETH_ALEN];
1234 u8 addr3[ETH_ALEN];
1235 __le16 seq_ctl;
1236 u8 addr4[ETH_ALEN];
1237 u8 payload[0];
1238 __le16 qos_ctl;
1239} __attribute__ ((packed));
1240
1241struct ieee80211_info_element {
1242 u8 id;
1243 u8 len;
1244 u8 data[0];
1245} __attribute__ ((packed));
1246
1247struct ieee80211_authentication {
1248 struct ieee80211_hdr_3addr header;
1249 __le16 algorithm;
1250 __le16 transaction;
1251 __le16 status;
1252 /*challenge*/
1253 struct ieee80211_info_element info_element[0];
1254} __attribute__ ((packed));
1255
1256struct ieee80211_disassoc {
1257 struct ieee80211_hdr_3addr header;
1258 __le16 reason;
1259} __attribute__ ((packed));
1260
1261struct ieee80211_probe_request {
1262 struct ieee80211_hdr_3addr header;
1263 /* SSID, supported rates */
1264 struct ieee80211_info_element info_element[0];
1265} __attribute__ ((packed));
1266
1267struct ieee80211_probe_response {
1268 struct ieee80211_hdr_3addr header;
1269 u32 time_stamp[2];
1270 __le16 beacon_interval;
1271 __le16 capability;
1272 /* SSID, supported rates, FH params, DS params,
1273 * CF params, IBSS params, TIM (if beacon), RSN */
1274 struct ieee80211_info_element info_element[0];
1275} __attribute__ ((packed));
1276
1277/* Alias beacon for probe_response */
1278#define ieee80211_beacon ieee80211_probe_response
1279
1280struct ieee80211_assoc_request_frame {
1281 struct ieee80211_hdr_3addr header;
1282 __le16 capability;
1283 __le16 listen_interval;
1284 /* SSID, supported rates, RSN */
1285 struct ieee80211_info_element info_element[0];
1286} __attribute__ ((packed));
1287
1288struct ieee80211_reassoc_request_frame {
1289 struct ieee80211_hdr_3addr header;
1290 __le16 capability;
1291 __le16 listen_interval;
1292 u8 current_ap[ETH_ALEN];
1293 /* SSID, supported rates, RSN */
1294 struct ieee80211_info_element info_element[0];
1295} __attribute__ ((packed));
1296
1297struct ieee80211_assoc_response_frame {
1298 struct ieee80211_hdr_3addr header;
1299 __le16 capability;
1300 __le16 status;
1301 __le16 aid;
1302 struct ieee80211_info_element info_element[0]; /* supported rates */
1303} __attribute__ ((packed));
1304
1305struct ieee80211_txb {
1306 u8 nr_frags;
1307 u8 encrypted;
1308 u8 queue_index;
1309 u8 rts_included;
1310 u16 reserved;
1311 __le16 frag_size;
1312 __le16 payload_size;
1313 struct sk_buff *fragments[0];
1314};
1315
1316#define MAX_TX_AGG_COUNT 16
1317struct ieee80211_drv_agg_txb {
1318 u8 nr_drv_agg_frames;
1319 struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT];
1320}__attribute__((packed));
1321
1322#define MAX_SUBFRAME_COUNT 64
1323struct ieee80211_rxb {
1324 u8 nr_subframes;
1325 struct sk_buff *subframes[MAX_SUBFRAME_COUNT];
1326 u8 dst[ETH_ALEN];
1327 u8 src[ETH_ALEN];
1328}__attribute__((packed));
1329
1330typedef union _frameqos {
1331 u16 shortdata;
1332 u8 chardata[2];
1333 struct {
1334 u16 tid:4;
1335 u16 eosp:1;
1336 u16 ack_policy:2;
1337 u16 reserved:1;
1338 u16 txop:8;
1339 }field;
1340}frameqos,*pframeqos;
1341
1342/* SWEEP TABLE ENTRIES NUMBER*/
1343#define MAX_SWEEP_TAB_ENTRIES 42
1344#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7
1345/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
1346 * only use 8, and then use extended rates for the remaining supported
1347 * rates. Other APs, however, stick all of their supported rates on the
1348 * main rates information element... */
1349#define MAX_RATES_LENGTH ((u8)12)
1350#define MAX_RATES_EX_LENGTH ((u8)16)
1351#define MAX_NETWORK_COUNT 128
1352
1353#define MAX_CHANNEL_NUMBER 161
1354#define IEEE80211_SOFTMAC_SCAN_TIME 100
1355//(HZ / 2)
1356#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
1357
1358#define CRC_LENGTH 4U
1359
1360#define MAX_WPA_IE_LEN 64
1361
1362#define NETWORK_EMPTY_ESSID (1<<0)
1363#define NETWORK_HAS_OFDM (1<<1)
1364#define NETWORK_HAS_CCK (1<<2)
1365
1366/* QoS structure */
1367#define NETWORK_HAS_QOS_PARAMETERS (1<<3)
1368#define NETWORK_HAS_QOS_INFORMATION (1<<4)
1369#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \
1370 NETWORK_HAS_QOS_INFORMATION)
1371/* 802.11h */
1372#define NETWORK_HAS_POWER_CONSTRAINT (1<<5)
1373#define NETWORK_HAS_CSA (1<<6)
1374#define NETWORK_HAS_QUIET (1<<7)
1375#define NETWORK_HAS_IBSS_DFS (1<<8)
1376#define NETWORK_HAS_TPC_REPORT (1<<9)
1377
1378#define NETWORK_HAS_ERP_VALUE (1<<10)
1379
1380#define QOS_QUEUE_NUM 4
1381#define QOS_OUI_LEN 3
1382#define QOS_OUI_TYPE 2
1383#define QOS_ELEMENT_ID 221
1384#define QOS_OUI_INFO_SUB_TYPE 0
1385#define QOS_OUI_PARAM_SUB_TYPE 1
1386#define QOS_VERSION_1 1
1387#define QOS_AIFSN_MIN_VALUE 2
1388#if 1
1389struct ieee80211_qos_information_element {
1390 u8 elementID;
1391 u8 length;
1392 u8 qui[QOS_OUI_LEN];
1393 u8 qui_type;
1394 u8 qui_subtype;
1395 u8 version;
1396 u8 ac_info;
1397} __attribute__ ((packed));
1398
1399struct ieee80211_qos_ac_parameter {
1400 u8 aci_aifsn;
1401 u8 ecw_min_max;
1402 __le16 tx_op_limit;
1403} __attribute__ ((packed));
1404
1405struct ieee80211_qos_parameter_info {
1406 struct ieee80211_qos_information_element info_element;
1407 u8 reserved;
1408 struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM];
1409} __attribute__ ((packed));
1410
1411struct ieee80211_qos_parameters {
1412 __le16 cw_min[QOS_QUEUE_NUM];
1413 __le16 cw_max[QOS_QUEUE_NUM];
1414 u8 aifs[QOS_QUEUE_NUM];
1415 u8 flag[QOS_QUEUE_NUM];
1416 __le16 tx_op_limit[QOS_QUEUE_NUM];
1417} __attribute__ ((packed));
1418
1419struct ieee80211_qos_data {
1420 struct ieee80211_qos_parameters parameters;
1421 int active;
1422 int supported;
1423 u8 param_count;
1424 u8 old_param_count;
1425};
1426
1427struct ieee80211_tim_parameters {
1428 u8 tim_count;
1429 u8 tim_period;
1430} __attribute__ ((packed));
1431
1432//#else
1433struct ieee80211_wmm_ac_param {
1434 u8 ac_aci_acm_aifsn;
1435 u8 ac_ecwmin_ecwmax;
1436 u16 ac_txop_limit;
1437};
1438
1439struct ieee80211_wmm_ts_info {
1440 u8 ac_dir_tid;
1441 u8 ac_up_psb;
1442 u8 reserved;
1443} __attribute__ ((packed));
1444
1445struct ieee80211_wmm_tspec_elem {
1446 struct ieee80211_wmm_ts_info ts_info;
1447 u16 norm_msdu_size;
1448 u16 max_msdu_size;
1449 u32 min_serv_inter;
1450 u32 max_serv_inter;
1451 u32 inact_inter;
1452 u32 suspen_inter;
1453 u32 serv_start_time;
1454 u32 min_data_rate;
1455 u32 mean_data_rate;
1456 u32 peak_data_rate;
1457 u32 max_burst_size;
1458 u32 delay_bound;
1459 u32 min_phy_rate;
1460 u16 surp_band_allow;
1461 u16 medium_time;
1462}__attribute__((packed));
1463#endif
1464enum eap_type {
1465 EAP_PACKET = 0,
1466 EAPOL_START,
1467 EAPOL_LOGOFF,
1468 EAPOL_KEY,
1469 EAPOL_ENCAP_ASF_ALERT
1470};
1471
1472static const char *eap_types[] = {
1473 [EAP_PACKET] = "EAP-Packet",
1474 [EAPOL_START] = "EAPOL-Start",
1475 [EAPOL_LOGOFF] = "EAPOL-Logoff",
1476 [EAPOL_KEY] = "EAPOL-Key",
1477 [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert"
1478};
1479
1480static inline const char *eap_get_type(int type)
1481{
1482 return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type];
1483}
1484//added by amy for reorder
1485static inline u8 Frame_QoSTID(u8* buf)
1486{
1487 struct ieee80211_hdr_3addr *hdr;
1488 u16 fc;
1489 hdr = (struct ieee80211_hdr_3addr *)buf;
1490 fc = le16_to_cpu(hdr->frame_ctl);
1491 return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid;
1492}
1493
1494//added by amy for reorder
1495
1496struct eapol {
1497 u8 snap[6];
1498 u16 ethertype;
1499 u8 version;
1500 u8 type;
1501 u16 length;
1502} __attribute__ ((packed));
1503
1504struct ieee80211_softmac_stats{
1505 unsigned int rx_ass_ok;
1506 unsigned int rx_ass_err;
1507 unsigned int rx_probe_rq;
1508 unsigned int tx_probe_rs;
1509 unsigned int tx_beacons;
1510 unsigned int rx_auth_rq;
1511 unsigned int rx_auth_rs_ok;
1512 unsigned int rx_auth_rs_err;
1513 unsigned int tx_auth_rq;
1514 unsigned int no_auth_rs;
1515 unsigned int no_ass_rs;
1516 unsigned int tx_ass_rq;
1517 unsigned int rx_ass_rq;
1518 unsigned int tx_probe_rq;
1519 unsigned int reassoc;
1520 unsigned int swtxstop;
1521 unsigned int swtxawake;
1522 unsigned char CurrentShowTxate;
1523 unsigned char last_packet_rate;
1524 unsigned int txretrycount;
1525};
1526
1527#define BEACON_PROBE_SSID_ID_POSITION 12
1528
1529struct ieee80211_info_element_hdr {
1530 u8 id;
1531 u8 len;
1532} __attribute__ ((packed));
1533
1534/*
1535 * These are the data types that can make up management packets
1536 *
1537 u16 auth_algorithm;
1538 u16 auth_sequence;
1539 u16 beacon_interval;
1540 u16 capability;
1541 u8 current_ap[ETH_ALEN];
1542 u16 listen_interval;
1543 struct {
1544 u16 association_id:14, reserved:2;
1545 } __attribute__ ((packed));
1546 u32 time_stamp[2];
1547 u16 reason;
1548 u16 status;
1549*/
1550
1551#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
1552#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps
1553
1554enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame};
1555#define MAX_SP_Len (WMM_all_frame << 4)
1556#define IEEE80211_QOS_TID 0x0f
1557#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5)
1558
1559#define IEEE80211_DTIM_MBCAST 4
1560#define IEEE80211_DTIM_UCAST 2
1561#define IEEE80211_DTIM_VALID 1
1562#define IEEE80211_DTIM_INVALID 0
1563
1564#define IEEE80211_PS_DISABLED 0
1565#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
1566#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
1567
1568//added by David for QoS 2006/6/30
1569//#define WMM_Hang_8187
1570#ifdef WMM_Hang_8187
1571#undef WMM_Hang_8187
1572#endif
1573
1574#define WME_AC_BK 0x00
1575#define WME_AC_BE 0x01
1576#define WME_AC_VI 0x02
1577#define WME_AC_VO 0x03
1578#define WME_ACI_MASK 0x03
1579#define WME_AIFSN_MASK 0x03
1580#define WME_AC_PRAM_LEN 16
1581
1582#define MAX_RECEIVE_BUFFER_SIZE 9100
1583
1584//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP
1585//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1))
1586#if 1
1587#define UP2AC(up) ( \
1588 ((up) < 1) ? WME_AC_BE : \
1589 ((up) < 3) ? WME_AC_BK : \
1590 ((up) < 4) ? WME_AC_BE : \
1591 ((up) < 6) ? WME_AC_VI : \
1592 WME_AC_VO)
1593#endif
1594//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue
1595#define AC2UP(_ac) ( \
1596 ((_ac) == WME_AC_VO) ? 6 : \
1597 ((_ac) == WME_AC_VI) ? 5 : \
1598 ((_ac) == WME_AC_BK) ? 1 : \
1599 0)
1600
1601#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */
1602#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/
1603
1604struct ether_header {
1605 u8 ether_dhost[ETHER_ADDR_LEN];
1606 u8 ether_shost[ETHER_ADDR_LEN];
1607 u16 ether_type;
1608} __attribute__((packed));
1609
1610#ifndef ETHERTYPE_PAE
1611#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */
1612#endif
1613#ifndef ETHERTYPE_IP
1614#define ETHERTYPE_IP 0x0800 /* IP protocol */
1615#endif
1616
1617typedef struct _bss_ht{
1618
1619 bool support_ht;
1620
1621 // HT related elements
1622 u8 ht_cap_buf[32];
1623 u16 ht_cap_len;
1624 u8 ht_info_buf[32];
1625 u16 ht_info_len;
1626
1627 HT_SPEC_VER ht_spec_ver;
1628 //HT_CAPABILITY_ELE bdHTCapEle;
1629 //HT_INFORMATION_ELE bdHTInfoEle;
1630
1631 bool aggregation;
1632 bool long_slot_time;
1633}bss_ht, *pbss_ht;
1634
1635typedef enum _erp_t{
1636 ERP_NonERPpresent = 0x01,
1637 ERP_UseProtection = 0x02,
1638 ERP_BarkerPreambleMode = 0x04,
1639} erp_t;
1640
1641
1642struct ieee80211_network {
1643 /* These entries are used to identify a unique network */
1644 u8 bssid[ETH_ALEN];
1645 u8 channel;
1646 /* Ensure null-terminated for any debug msgs */
1647 u8 ssid[IW_ESSID_MAX_SIZE + 1];
1648 u8 ssid_len;
1649#if 1
1650 struct ieee80211_qos_data qos_data;
1651#else
1652 // Qos related. Added by Annie, 2005-11-01.
1653 BSS_QOS BssQos;
1654#endif
1655
1656 //added by amy for LEAP
1657 bool bWithAironetIE;
1658 bool bCkipSupported;
1659 bool bCcxRmEnable;
1660 u16 CcxRmState[2];
1661 // CCXv4 S59, MBSSID.
1662 bool bMBssidValid;
1663 u8 MBssidMask;
1664 u8 MBssid[6];
1665 // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20.
1666 bool bWithCcxVerNum;
1667 u8 BssCcxVerNumber;
1668 /* These are network statistics */
1669 struct ieee80211_rx_stats stats;
1670 u16 capability;
1671 u8 rates[MAX_RATES_LENGTH];
1672 u8 rates_len;
1673 u8 rates_ex[MAX_RATES_EX_LENGTH];
1674 u8 rates_ex_len;
1675 unsigned long last_scanned;
1676 u8 mode;
1677 u32 flags;
1678 u32 last_associate;
1679 u32 time_stamp[2];
1680 u16 beacon_interval;
1681 u16 listen_interval;
1682 u16 atim_window;
1683 u8 erp_value;
1684 u8 wpa_ie[MAX_WPA_IE_LEN];
1685 size_t wpa_ie_len;
1686 u8 rsn_ie[MAX_WPA_IE_LEN];
1687 size_t rsn_ie_len;
1688
1689 struct ieee80211_tim_parameters tim;
1690 u8 dtim_period;
1691 u8 dtim_data;
1692 u32 last_dtim_sta_time[2];
1693
1694 //appeded for QoS
1695 u8 wmm_info;
1696 struct ieee80211_wmm_ac_param wmm_param[4];
1697 u8 QoS_Enable;
1698#ifdef THOMAS_TURBO
1699 u8 Turbo_Enable;//enable turbo mode, added by thomas
1700#endif
1701#ifdef ENABLE_DOT11D
1702 u16 CountryIeLen;
1703 u8 CountryIeBuf[MAX_IE_LEN];
1704#endif
1705 // HT Related, by amy, 2008.04.29
1706 BSS_HT bssht;
1707 // Add to handle broadcom AP management frame CCK rate.
1708 bool broadcom_cap_exist;
1709 bool realtek_cap_exit;
1710 bool marvell_cap_exist;
1711 bool ralink_cap_exist;
1712 bool atheros_cap_exist;
1713 bool cisco_cap_exist;
1714 bool unknown_cap_exist;
1715// u8 berp_info;
1716 bool berp_info_valid;
1717 bool buseprotection;
1718 //put at the end of the structure.
1719 struct list_head list;
1720};
1721
1722#if 1
1723enum ieee80211_state {
1724
1725 /* the card is not linked at all */
1726 IEEE80211_NOLINK = 0,
1727
1728 /* IEEE80211_ASSOCIATING* are for BSS client mode
1729 * the driver shall not perform RX filtering unless
1730 * the state is LINKED.
1731 * The driver shall just check for the state LINKED and
1732 * defaults to NOLINK for ALL the other states (including
1733 * LINKED_SCANNING)
1734 */
1735
1736 /* the association procedure will start (wq scheduling)*/
1737 IEEE80211_ASSOCIATING,
1738 IEEE80211_ASSOCIATING_RETRY,
1739
1740 /* the association procedure is sending AUTH request*/
1741 IEEE80211_ASSOCIATING_AUTHENTICATING,
1742
1743 /* the association procedure has successfully authentcated
1744 * and is sending association request
1745 */
1746 IEEE80211_ASSOCIATING_AUTHENTICATED,
1747
1748 /* the link is ok. the card associated to a BSS or linked
1749 * to a ibss cell or acting as an AP and creating the bss
1750 */
1751 IEEE80211_LINKED,
1752
1753 /* same as LINKED, but the driver shall apply RX filter
1754 * rules as we are in NO_LINK mode. As the card is still
1755 * logically linked, but it is doing a syncro site survey
1756 * then it will be back to LINKED state.
1757 */
1758 IEEE80211_LINKED_SCANNING,
1759
1760};
1761#else
1762enum ieee80211_state {
1763 IEEE80211_UNINITIALIZED = 0,
1764 IEEE80211_INITIALIZED,
1765 IEEE80211_ASSOCIATING,
1766 IEEE80211_ASSOCIATED,
1767 IEEE80211_AUTHENTICATING,
1768 IEEE80211_AUTHENTICATED,
1769 IEEE80211_SHUTDOWN
1770};
1771#endif
1772
1773#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
1774#define DEFAULT_FTS 2346
1775
1776#define CFG_IEEE80211_RESERVE_FCS (1<<0)
1777#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
1778#define CFG_IEEE80211_RTS (1<<2)
1779
1780#define IEEE80211_24GHZ_MIN_CHANNEL 1
1781#define IEEE80211_24GHZ_MAX_CHANNEL 14
1782#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \
1783 IEEE80211_24GHZ_MIN_CHANNEL + 1)
1784
1785#define IEEE80211_52GHZ_MIN_CHANNEL 34
1786#define IEEE80211_52GHZ_MAX_CHANNEL 165
1787#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \
1788 IEEE80211_52GHZ_MIN_CHANNEL + 1)
1789
1790#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11))
1791extern inline int is_multicast_ether_addr(const u8 *addr)
1792{
1793 return ((addr[0] != 0xff) && (0x01 & addr[0]));
1794}
1795#endif
1796
1797#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13))
1798extern inline int is_broadcast_ether_addr(const u8 *addr)
1799{
1800 return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \
1801 (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
1802}
1803#endif
1804
1805typedef struct tx_pending_t{
1806 int frag;
1807 struct ieee80211_txb *txb;
1808}tx_pending_t;
1809
1810typedef struct _bandwidth_autoswitch
1811{
1812 long threshold_20Mhzto40Mhz;
1813 long threshold_40Mhzto20Mhz;
1814 bool bforced_tx20Mhz;
1815 bool bautoswitch_enable;
1816}bandwidth_autoswitch,*pbandwidth_autoswitch;
1817
1818
1819//added by amy for order
1820
1821#define REORDER_WIN_SIZE 128
1822#define REORDER_ENTRY_NUM 128
1823typedef struct _RX_REORDER_ENTRY
1824{
1825 struct list_head List;
1826 u16 SeqNum;
1827 struct ieee80211_rxb* prxb;
1828} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY;
1829//added by amy for order
1830typedef enum _Fsync_State{
1831 Default_Fsync,
1832 HW_Fsync,
1833 SW_Fsync
1834}Fsync_State;
1835
1836// Power save mode configured.
1837typedef enum _RT_PS_MODE
1838{
1839 eActive, // Active/Continuous access.
1840 eMaxPs, // Max power save mode.
1841 eFastPs // Fast power save mode.
1842}RT_PS_MODE;
1843
1844typedef enum _IPS_CALLBACK_FUNCION
1845{
1846 IPS_CALLBACK_NONE = 0,
1847 IPS_CALLBACK_MGNT_LINK_REQUEST = 1,
1848 IPS_CALLBACK_JOIN_REQUEST = 2,
1849}IPS_CALLBACK_FUNCION;
1850
1851typedef enum _RT_JOIN_ACTION{
1852 RT_JOIN_INFRA = 1,
1853 RT_JOIN_IBSS = 2,
1854 RT_START_IBSS = 3,
1855 RT_NO_ACTION = 4,
1856}RT_JOIN_ACTION;
1857
1858typedef struct _IbssParms{
1859 u16 atimWin;
1860}IbssParms, *PIbssParms;
1861#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko.
1862
1863// RF state.
1864typedef enum _RT_RF_POWER_STATE
1865{
1866 eRfOn,
1867 eRfSleep,
1868 eRfOff
1869}RT_RF_POWER_STATE;
1870
1871typedef struct _RT_POWER_SAVE_CONTROL
1872{
1873
1874 //
1875 // Inactive Power Save(IPS) : Disable RF when disconnected
1876 //
1877 bool bInactivePs;
1878 bool bIPSModeBackup;
1879 bool bHaltAdapterClkRQ;
1880 bool bSwRfProcessing;
1881 RT_RF_POWER_STATE eInactivePowerState;
1882#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1883 struct work_struct InactivePsWorkItem;
1884#else
1885 struct tq_struct InactivePsWorkItem;
1886#endif
1887 struct timer_list InactivePsTimer;
1888
1889 // Return point for join action
1890 IPS_CALLBACK_FUNCION ReturnPoint;
1891
1892 // Recored Parameters for rescheduled JoinRequest
1893 bool bTmpBssDesc;
1894 RT_JOIN_ACTION tmpJoinAction;
1895 struct ieee80211_network tmpBssDesc;
1896
1897 // Recored Parameters for rescheduled MgntLinkRequest
1898 bool bTmpScanOnly;
1899 bool bTmpActiveScan;
1900 bool bTmpFilterHiddenAP;
1901 bool bTmpUpdateParms;
1902 u8 tmpSsidBuf[33];
1903 OCTET_STRING tmpSsid2Scan;
1904 bool bTmpSsid2Scan;
1905 u8 tmpNetworkType;
1906 u8 tmpChannelNumber;
1907 u16 tmpBcnPeriod;
1908 u8 tmpDtimPeriod;
1909 u16 tmpmCap;
1910 OCTET_STRING tmpSuppRateSet;
1911 u8 tmpSuppRateBuf[MAX_NUM_RATES];
1912 bool bTmpSuppRate;
1913 IbssParms tmpIbpm;
1914 bool bTmpIbpm;
1915
1916 //
1917 // Leisre Poswer Save : Disable RF if connected but traffic is not busy
1918 //
1919 bool bLeisurePs;
1920 u32 PowerProfile;
1921 u8 LpsIdleCount;
1922 u8 RegMaxLPSAwakeIntvl;
1923 u8 LPSAwakeIntvl;
1924
1925 //RF OFF Level
1926 u32 CurPsLevel;
1927 u32 RegRfPsLevel;
1928
1929 //Fw Control LPS
1930 bool bFwCtrlLPS;
1931 u8 FWCtrlPSMode;
1932
1933 //2009.01.01 added by tynli
1934 // Record if there is a link request in IPS RF off progress.
1935 bool LinkReqInIPSRFOffPgs;
1936 // To make sure that connect info should be executed, so we set the bit to filter the link info which comes after the connect info.
1937 bool BufConnectinfoBefore;
1938
1939}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL;
1940
1941typedef u32 RT_RF_CHANGE_SOURCE;
1942#define RF_CHANGE_BY_SW BIT31
1943#define RF_CHANGE_BY_HW BIT30
1944#define RF_CHANGE_BY_PS BIT29
1945#define RF_CHANGE_BY_IPS BIT28
1946#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17.
1947
1948#ifdef ENABLE_DOT11D
1949typedef enum
1950{
1951 COUNTRY_CODE_FCC = 0,
1952 COUNTRY_CODE_IC = 1,
1953 COUNTRY_CODE_ETSI = 2,
1954 COUNTRY_CODE_SPAIN = 3,
1955 COUNTRY_CODE_FRANCE = 4,
1956 COUNTRY_CODE_MKK = 5,
1957 COUNTRY_CODE_MKK1 = 6,
1958 COUNTRY_CODE_ISRAEL = 7,
1959 COUNTRY_CODE_TELEC,
1960 COUNTRY_CODE_MIC,
1961 COUNTRY_CODE_GLOBAL_DOMAIN
1962}country_code_type_t;
1963#endif
1964 // Firmware realted CMD IO.
1965typedef enum _FW_CMD_IO_TYPE{
1966 FW_CMD_DIG_ENABLE = 0, // For DIG DM
1967 FW_CMD_DIG_DISABLE = 1,
1968 FW_CMD_DIG_HALT = 2,
1969 FW_CMD_DIG_RESUME = 3,
1970 FW_CMD_HIGH_PWR_ENABLE = 4, // For High Power DM
1971 FW_CMD_HIGH_PWR_DISABLE = 5,
1972 FW_CMD_RA_RESET = 6, // For Rate adaptive DM
1973 FW_CMD_RA_ACTIVE= 7,
1974 FW_CMD_RA_REFRESH_N= 8,
1975 FW_CMD_RA_REFRESH_BG= 9,
1976 FW_CMD_IQK_ENABLE = 10, // For FW supported IQK
1977 FW_CMD_TXPWR_TRACK_ENABLE = 11, // Tx power tracking switch
1978 FW_CMD_TXPWR_TRACK_DISABLE = 12, // Tx power tracking switch
1979 FW_CMD_PAUSE_DM_BY_SCAN = 13,
1980 FW_CMD_RESUME_DM_BY_SCAN = 14,
1981 FW_CMD_MID_HIGH_PWR_ENABLE = 15,
1982 FW_CMD_LPS_ENTER = 16, // Indifate firmware that driver enters LPS, For PS-Poll hardware bug
1983 FW_CMD_LPS_LEAVE = 17, // Indicate firmware that driver leave LPS, 2009/1/4, by Emily
1984}FW_CMD_IO_TYPE,*PFW_CMD_IO_TYPE;
1985#define RT_MAX_LD_SLOT_NUM 10
1986typedef struct _RT_LINK_DETECT_T{
1987
1988 u32 NumRecvBcnInPeriod;
1989 u32 NumRecvDataInPeriod;
1990
1991 u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status
1992 u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status
1993 u16 SlotNum; // number of CheckForHang period to determine link status
1994 u16 SlotIndex;
1995
1996 u32 NumTxOkInPeriod;
1997 u32 NumRxOkInPeriod;
1998 bool bBusyTraffic;
1999}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
2000
2001
2002struct ieee80211_device {
2003 struct net_device *dev;
2004 struct ieee80211_security sec;
2005
2006 //hw security related
2007// u8 hwsec_support; //support?
2008 u8 hwsec_active; //hw security active.
2009 bool is_silent_reset;
2010 bool is_roaming;
2011 bool ieee_up;
2012 //added by amy
2013 bool bSupportRemoteWakeUp;
2014 RT_PS_MODE dot11PowerSaveMode; // Power save mode configured.
2015 bool actscanning;
2016 //added by amy 090313
2017 bool be_scan_inprogress;
2018 bool beinretry;
2019 RT_RF_POWER_STATE eRFPowerState;
2020 RT_RF_CHANGE_SOURCE RfOffReason;
2021 bool is_set_key;
2022 //11n spec related I wonder if These info structure need to be moved out of ieee80211_device
2023
2024 //11n HT below
2025 PRT_HIGH_THROUGHPUT pHTInfo;
2026 //struct timer_list SwBwTimer;
2027// spinlock_t chnlop_spinlock;
2028 spinlock_t bw_spinlock;
2029
2030 spinlock_t reorder_spinlock;
2031 // for HT operation rate set. we use this one for HT data rate to seperate different descriptors
2032 //the way fill this is the same as in the IE
2033 u8 Regdot11HTOperationalRateSet[16]; //use RATR format
2034 u8 dot11HTOperationalRateSet[16]; //use RATR format
2035 u8 RegHTSuppRateSet[16];
2036 u8 HTCurrentOperaRate;
2037 u8 HTHighestOperaRate;
2038 //wb added for rate operation mode to firmware
2039 u8 bTxDisableRateFallBack;
2040 u8 bTxUseDriverAssingedRate;
2041 atomic_t atm_chnlop;
2042 atomic_t atm_swbw;
2043// u8 HTHighestOperaRate;
2044// u8 HTCurrentOperaRate;
2045
2046 // 802.11e and WMM Traffic Stream Info (TX)
2047 struct list_head Tx_TS_Admit_List;
2048 struct list_head Tx_TS_Pending_List;
2049 struct list_head Tx_TS_Unused_List;
2050 TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM];
2051 // 802.11e and WMM Traffic Stream Info (RX)
2052 struct list_head Rx_TS_Admit_List;
2053 struct list_head Rx_TS_Pending_List;
2054 struct list_head Rx_TS_Unused_List;
2055 RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM];
2056//#ifdef TO_DO_LIST
2057 RX_REORDER_ENTRY RxReorderEntry[128];
2058 struct list_head RxReorder_Unused_List;
2059//#endif
2060 // Qos related. Added by Annie, 2005-11-01.
2061// PSTA_QOS pStaQos;
2062 u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.)
2063
2064
2065 /* Bookkeeping structures */
2066 struct net_device_stats stats;
2067 struct ieee80211_stats ieee_stats;
2068 struct ieee80211_softmac_stats softmac_stats;
2069
2070 /* Probe / Beacon management */
2071 struct list_head network_free_list;
2072 struct list_head network_list;
2073 struct ieee80211_network *networks;
2074 int scans;
2075 int scan_age;
2076
2077 int iw_mode; /* operating mode (IW_MODE_*) */
2078 struct iw_spy_data spy_data;
2079
2080 spinlock_t lock;
2081 spinlock_t wpax_suitlist_lock;
2082
2083 int tx_headroom; /* Set to size of any additional room needed at front
2084 * of allocated Tx SKBs */
2085 u32 config;
2086
2087 /* WEP and other encryption related settings at the device level */
2088 int open_wep; /* Set to 1 to allow unencrypted frames */
2089 int auth_mode;
2090 int reset_on_keychange; /* Set to 1 if the HW needs to be reset on
2091 * WEP key changes */
2092
2093 /* If the host performs {en,de}cryption, then set to 1 */
2094 int host_encrypt;
2095 int host_encrypt_msdu;
2096 int host_decrypt;
2097 /* host performs multicast decryption */
2098 int host_mc_decrypt;
2099
2100 /* host should strip IV and ICV from protected frames */
2101 /* meaningful only when hardware decryption is being used */
2102 int host_strip_iv_icv;
2103
2104 int host_open_frag;
2105 int host_build_iv;
2106 int ieee802_1x; /* is IEEE 802.1X used */
2107
2108 /* WPA data */
2109 bool bHalfWirelessN24GMode;
2110 int wpa_enabled;
2111 int drop_unencrypted;
2112 int tkip_countermeasures;
2113 int privacy_invoked;
2114 size_t wpa_ie_len;
2115 u8 *wpa_ie;
2116 u8 ap_mac_addr[6];
2117 u16 pairwise_key_type;
2118 u16 group_key_type;
2119 struct list_head crypt_deinit_list;
2120 struct ieee80211_crypt_data *crypt[WEP_KEYS];
2121 int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */
2122 struct timer_list crypt_deinit_timer;
2123 int crypt_quiesced;
2124
2125 int bcrx_sta_key; /* use individual keys to override default keys even
2126 * with RX of broad/multicast frames */
2127
2128 /* Fragmentation structures */
2129 // each streaming contain a entry
2130 struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN];
2131 unsigned int frag_next_idx[17];
2132 u16 fts; /* Fragmentation Threshold */
2133#define DEFAULT_RTS_THRESHOLD 2346U
2134#define MIN_RTS_THRESHOLD 1
2135#define MAX_RTS_THRESHOLD 2346U
2136 u16 rts; /* RTS threshold */
2137
2138 /* Association info */
2139 u8 bssid[ETH_ALEN];
2140
2141 /* This stores infos for the current network.
2142 * Either the network we are associated in INFRASTRUCTURE
2143 * or the network that we are creating in MASTER mode.
2144 * ad-hoc is a mixture ;-).
2145 * Note that in infrastructure mode, even when not associated,
2146 * fields bssid and essid may be valid (if wpa_set and essid_set
2147 * are true) as thy carry the value set by the user via iwconfig
2148 */
2149 struct ieee80211_network current_network;
2150
2151 enum ieee80211_state state;
2152
2153 int short_slot;
2154 int reg_mode;
2155 int mode; /* A, B, G */
2156 int modulation; /* CCK, OFDM */
2157 int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */
2158 int abg_true; /* ABG flag */
2159
2160 /* used for forcing the ibss workqueue to terminate
2161 * without wait for the syncro scan to terminate
2162 */
2163 short sync_scan_hurryup;
2164 u16 scan_watch_dog;
2165 int perfect_rssi;
2166 int worst_rssi;
2167
2168 u16 prev_seq_ctl; /* used to drop duplicate frames */
2169
2170 /* map of allowed channels. 0 is dummy */
2171 // FIXME: remeber to default to a basic channel plan depending of the PHY type
2172#ifdef ENABLE_DOT11D
2173 void* pDot11dInfo;
2174 bool bGlobalDomain;
2175#else
2176 int channel_map[MAX_CHANNEL_NUMBER+1];
2177#endif
2178 int rate; /* current rate */
2179 int basic_rate;
2180 //FIXME: pleace callback, see if redundant with softmac_features
2181 short active_scan;
2182
2183 /* this contains flags for selectively enable softmac support */
2184 u16 softmac_features;
2185
2186 /* if the sequence control field is not filled by HW */
2187 u16 seq_ctrl[5];
2188
2189 /* association procedure transaction sequence number */
2190 u16 associate_seq;
2191
2192 /* AID for RTXed association responses */
2193 u16 assoc_id;
2194
2195 /* power save mode related*/
2196 u8 ack_tx_to_ieee;
2197 short ps;
2198 short sta_sleep;
2199 int ps_timeout;
2200 int ps_period;
2201 struct tasklet_struct ps_task;
2202 u32 ps_th;
2203 u32 ps_tl;
2204
2205 short raw_tx;
2206 /* used if IEEE_SOFTMAC_TX_QUEUE is set */
2207 short queue_stop;
2208 short scanning;
2209 short proto_started;
2210
2211 struct semaphore wx_sem;
2212 struct semaphore scan_sem;
2213
2214 spinlock_t mgmt_tx_lock;
2215 spinlock_t beacon_lock;
2216
2217 short beacon_txing;
2218
2219 short wap_set;
2220 short ssid_set;
2221
2222 u8 wpax_type_set; //{added by David, 2006.9.28}
2223 u32 wpax_type_notify; //{added by David, 2006.9.26}
2224
2225 /* QoS related flag */
2226 char init_wmmparam_flag;
2227 /* set on initialization */
2228 u8 qos_support;
2229
2230 /* for discarding duplicated packets in IBSS */
2231 struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE];
2232
2233 /* for discarding duplicated packets in BSS */
2234 u16 last_rxseq_num[17]; /* rx seq previous per-tid */
2235 u16 last_rxfrag_num[17];/* tx frag previous per-tid */
2236 unsigned long last_packet_time[17];
2237
2238 /* for PS mode */
2239 unsigned long last_rx_ps_time;
2240
2241 /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */
2242 struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM];
2243 int mgmt_queue_head;
2244 int mgmt_queue_tail;
2245//{ added for rtl819x
2246#define IEEE80211_QUEUE_LIMIT 128
2247 u8 AsocRetryCount;
2248 unsigned int hw_header;
2249 struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE];
2250 struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE];
2251 struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE];
2252 u32 sta_edca_param[4];
2253 bool aggregation;
2254 // Enable/Disable Rx immediate BA capability.
2255 bool enable_rx_imm_BA;
2256 bool bibsscoordinator;
2257
2258 //+by amy for DM ,080515
2259 //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15
2260 bool bdynamic_txpower_enable;
2261
2262 bool bCTSToSelfEnable;
2263 u8 CTSToSelfTH;
2264
2265 u32 fsync_time_interval;
2266 u32 fsync_rate_bitmap;
2267 u8 fsync_rssi_threshold;
2268 bool bfsync_enable;
2269
2270 u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval
2271 u32 fsync_firstdiff_ratethreshold; // low threshold
2272 u32 fsync_seconddiff_ratethreshold; // decrease threshold
2273 Fsync_State fsync_state;
2274 bool bis_any_nonbepkts;
2275 //20Mhz 40Mhz AutoSwitch Threshold
2276 bandwidth_autoswitch bandwidth_auto_switch;
2277 //for txpower tracking
2278 bool FwRWRF;
2279
2280 //added by amy for AP roaming
2281 RT_LINK_DETECT_T LinkDetectInfo;
2282 //added by amy for ps
2283 RT_POWER_SAVE_CONTROL PowerSaveControl;
2284//}
2285 /* used if IEEE_SOFTMAC_TX_QUEUE is set */
2286 struct tx_pending_t tx_pending;
2287
2288 /* used if IEEE_SOFTMAC_ASSOCIATE is set */
2289 struct timer_list associate_timer;
2290
2291 /* used if IEEE_SOFTMAC_BEACONS is set */
2292 struct timer_list beacon_timer;
2293#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2294 struct work_struct associate_complete_wq;
2295 struct work_struct associate_procedure_wq;
2296#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2297 struct delayed_work softmac_scan_wq;
2298 struct delayed_work associate_retry_wq;
2299 struct delayed_work start_ibss_wq;
2300 struct delayed_work hw_wakeup_wq;
2301 struct delayed_work hw_sleep_wq;
2302 struct delayed_work link_change_wq;
2303#else
2304 struct work_struct softmac_scan_wq;
2305 struct work_struct associate_retry_wq;
2306 struct work_struct start_ibss_wq;
2307 struct work_struct hw_wakeup_wq;
2308 struct work_struct hw_sleep_wq;
2309 struct work_struct link_change_wq;
2310#endif
2311 struct work_struct wx_sync_scan_wq;
2312 struct workqueue_struct *wq;
2313#else
2314 /* used for periodly scan */
2315 struct timer_list scan_timer;
2316
2317 struct tq_struct associate_complete_wq;
2318 struct tq_struct associate_retry_wq;
2319 struct tq_struct start_ibss_wq;
2320 struct tq_struct associate_procedure_wq;
2321 struct tq_struct softmac_scan_wq;
2322 struct tq_struct wx_sync_scan_wq;
2323 struct tq_struct hw_wakeup_wq;
2324 struct tq_struct hw_sleep_wq;
2325 struct tq_struct link_change_wq;
2326
2327#endif
2328 // Qos related. Added by Annie, 2005-11-01.
2329 //STA_QOS StaQos;
2330
2331 //u32 STA_EDCA_PARAM[4];
2332 //CHANNEL_ACCESS_SETTING ChannelAccessSetting;
2333
2334
2335 /* Callback functions */
2336 void (*set_security)(struct net_device *dev,
2337 struct ieee80211_security *sec);
2338
2339 /* Used to TX data frame by using txb structs.
2340 * this is not used if in the softmac_features
2341 * is set the flag IEEE_SOFTMAC_TX_QUEUE
2342 */
2343 int (*hard_start_xmit)(struct ieee80211_txb *txb,
2344 struct net_device *dev);
2345
2346 int (*reset_port)(struct net_device *dev);
2347 int (*is_queue_full) (struct net_device * dev, int pri);
2348
2349 int (*handle_management) (struct net_device * dev,
2350 struct ieee80211_network * network, u16 type);
2351 int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb);
2352
2353 /* Softmac-generated frames (mamagement) are TXed via this
2354 * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is
2355 * not set. As some cards may have different HW queues that
2356 * one might want to use for data and management frames
2357 * the option to have two callbacks might be useful.
2358 * This fucntion can't sleep.
2359 */
2360 int (*softmac_hard_start_xmit)(struct sk_buff *skb,
2361 struct net_device *dev);
2362
2363 /* used instead of hard_start_xmit (not softmac_hard_start_xmit)
2364 * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data
2365 * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set
2366 * then also management frames are sent via this callback.
2367 * This function can't sleep.
2368 */
2369 void (*softmac_data_hard_start_xmit)(struct sk_buff *skb,
2370 struct net_device *dev,int rate);
2371
2372 /* stops the HW queue for DATA frames. Useful to avoid
2373 * waste time to TX data frame when we are reassociating
2374 * This function can sleep.
2375 */
2376 void (*data_hard_stop)(struct net_device *dev);
2377
2378 /* OK this is complementar to data_poll_hard_stop */
2379 void (*data_hard_resume)(struct net_device *dev);
2380
2381 /* ask to the driver to retune the radio .
2382 * This function can sleep. the driver should ensure
2383 * the radio has been swithced before return.
2384 */
2385 void (*set_chan)(struct net_device *dev,short ch);
2386
2387 /* These are not used if the ieee stack takes care of
2388 * scanning (IEEE_SOFTMAC_SCAN feature set).
2389 * In this case only the set_chan is used.
2390 *
2391 * The syncro version is similar to the start_scan but
2392 * does not return until all channels has been scanned.
2393 * this is called in user context and should sleep,
2394 * it is called in a work_queue when swithcing to ad-hoc mode
2395 * or in behalf of iwlist scan when the card is associated
2396 * and root user ask for a scan.
2397 * the fucntion stop_scan should stop both the syncro and
2398 * background scanning and can sleep.
2399 * The fucntion start_scan should initiate the background
2400 * scanning and can't sleep.
2401 */
2402 void (*scan_syncro)(struct net_device *dev);
2403 void (*start_scan)(struct net_device *dev);
2404 void (*stop_scan)(struct net_device *dev);
2405
2406 /* indicate the driver that the link state is changed
2407 * for example it may indicate the card is associated now.
2408 * Driver might be interested in this to apply RX filter
2409 * rules or simply light the LINK led
2410 */
2411 void (*link_change)(struct net_device *dev);
2412
2413 /* these two function indicates to the HW when to start
2414 * and stop to send beacons. This is used when the
2415 * IEEE_SOFTMAC_BEACONS is not set. For now the
2416 * stop_send_bacons is NOT guaranteed to be called only
2417 * after start_send_beacons.
2418 */
2419 void (*start_send_beacons) (struct net_device *dev);
2420 void (*stop_send_beacons) (struct net_device *dev);
2421
2422 /* power save mode related */
2423 void (*sta_wake_up) (struct net_device *dev);
2424// void (*ps_request_tx_ack) (struct net_device *dev);
2425 void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl);
2426 short (*ps_is_queue_empty) (struct net_device *dev);
2427#if 0
2428 /* Typical STA methods */
2429 int (*handle_auth) (struct net_device * dev,
2430 struct ieee80211_auth * auth);
2431 int (*handle_deauth) (struct net_device * dev,
2432 struct ieee80211_deauth * auth);
2433 int (*handle_action) (struct net_device * dev,
2434 struct ieee80211_action * action,
2435 struct ieee80211_rx_stats * stats);
2436 int (*handle_disassoc) (struct net_device * dev,
2437 struct ieee80211_disassoc * assoc);
2438#endif
2439 int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network);
2440#if 0
2441 int (*handle_probe_response) (struct net_device * dev,
2442 struct ieee80211_probe_response * resp,
2443 struct ieee80211_network * network);
2444 int (*handle_probe_request) (struct net_device * dev,
2445 struct ieee80211_probe_request * req,
2446 struct ieee80211_rx_stats * stats);
2447#endif
2448 int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network);
2449
2450#if 0
2451 /* Typical AP methods */
2452 int (*handle_assoc_request) (struct net_device * dev);
2453 int (*handle_reassoc_request) (struct net_device * dev,
2454 struct ieee80211_reassoc_request * req);
2455#endif
2456
2457 /* check whether Tx hw resouce available */
2458 short (*check_nic_enough_desc)(struct net_device *dev, int queue_index);
2459 //added by wb for HT related
2460// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel);
2461 void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
2462// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate);
2463 bool (*GetNmodeSupportBySecCfg)(struct net_device* dev);
2464 void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode);
2465 bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev);
2466 bool (*is_ap_in_wep_tkip)(struct net_device* dev);
2467 void (*InitialGainHandler)(struct net_device *dev, u8 Operation);
2468 bool (*SetFwCmdHandler)(struct net_device *dev, FW_CMD_IO_TYPE FwCmdIO);
2469 void (*LedControlHandler)(struct net_device * dev, LED_CTL_MODE LedAction);
2470 /* This must be the last item so that it points to the data
2471 * allocated beyond this structure by alloc_ieee80211 */
2472 u8 priv[0];
2473};
2474
2475#define IEEE_A (1<<0)
2476#define IEEE_B (1<<1)
2477#define IEEE_G (1<<2)
2478#define IEEE_N_24G (1<<4)
2479#define IEEE_N_5G (1<<5)
2480#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
2481
2482/* Generate a 802.11 header */
2483
2484/* Uses the channel change callback directly
2485 * instead of [start/stop] scan callbacks
2486 */
2487#define IEEE_SOFTMAC_SCAN (1<<2)
2488
2489/* Perform authentication and association handshake */
2490#define IEEE_SOFTMAC_ASSOCIATE (1<<3)
2491
2492/* Generate probe requests */
2493#define IEEE_SOFTMAC_PROBERQ (1<<4)
2494
2495/* Generate respones to probe requests */
2496#define IEEE_SOFTMAC_PROBERS (1<<5)
2497
2498/* The ieee802.11 stack will manages the netif queue
2499 * wake/stop for the driver, taking care of 802.11
2500 * fragmentation. See softmac.c for details. */
2501#define IEEE_SOFTMAC_TX_QUEUE (1<<7)
2502
2503/* Uses only the softmac_data_hard_start_xmit
2504 * even for TX management frames.
2505 */
2506#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8)
2507
2508/* Generate beacons. The stack will enqueue beacons
2509 * to the card
2510 */
2511#define IEEE_SOFTMAC_BEACONS (1<<6)
2512
2513static inline void *ieee80211_priv(struct net_device *dev)
2514{
2515#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2516 return ((struct ieee80211_device *)netdev_priv(dev))->priv;
2517#else
2518 return ((struct ieee80211_device *)dev->priv)->priv;
2519#endif
2520}
2521
2522extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
2523{
2524 /* Single white space is for Linksys APs */
2525 if (essid_len == 1 && essid[0] == ' ')
2526 return 1;
2527
2528 /* Otherwise, if the entire essid is 0, we assume it is hidden */
2529 while (essid_len) {
2530 essid_len--;
2531 if (essid[essid_len] != '\0')
2532 return 0;
2533 }
2534
2535 return 1;
2536}
2537
2538extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
2539{
2540 /*
2541 * It is possible for both access points and our device to support
2542 * combinations of modes, so as long as there is one valid combination
2543 * of ap/device supported modes, then return success
2544 *
2545 */
2546 if ((mode & IEEE_A) &&
2547 (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
2548 (ieee->freq_band & IEEE80211_52GHZ_BAND))
2549 return 1;
2550
2551 if ((mode & IEEE_G) &&
2552 (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
2553 (ieee->freq_band & IEEE80211_24GHZ_BAND))
2554 return 1;
2555
2556 if ((mode & IEEE_B) &&
2557 (ieee->modulation & IEEE80211_CCK_MODULATION) &&
2558 (ieee->freq_band & IEEE80211_24GHZ_BAND))
2559 return 1;
2560
2561 return 0;
2562}
2563
2564extern inline int ieee80211_get_hdrlen(u16 fc)
2565{
2566 int hdrlen = IEEE80211_3ADDR_LEN;
2567
2568 switch (WLAN_FC_GET_TYPE(fc)) {
2569 case IEEE80211_FTYPE_DATA:
2570 if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))
2571 hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */
2572 if(IEEE80211_QOS_HAS_SEQ(fc))
2573 hdrlen += 2; /* QOS ctrl*/
2574 break;
2575 case IEEE80211_FTYPE_CTL:
2576 switch (WLAN_FC_GET_STYPE(fc)) {
2577 case IEEE80211_STYPE_CTS:
2578 case IEEE80211_STYPE_ACK:
2579 hdrlen = IEEE80211_1ADDR_LEN;
2580 break;
2581 default:
2582 hdrlen = IEEE80211_2ADDR_LEN;
2583 break;
2584 }
2585 break;
2586 }
2587
2588 return hdrlen;
2589}
2590
2591static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr)
2592{
2593 switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) {
2594 case IEEE80211_1ADDR_LEN:
2595 return ((struct ieee80211_hdr_1addr *)hdr)->payload;
2596 case IEEE80211_2ADDR_LEN:
2597 return ((struct ieee80211_hdr_2addr *)hdr)->payload;
2598 case IEEE80211_3ADDR_LEN:
2599 return ((struct ieee80211_hdr_3addr *)hdr)->payload;
2600 case IEEE80211_4ADDR_LEN:
2601 return ((struct ieee80211_hdr_4addr *)hdr)->payload;
2602 }
2603 return NULL;
2604}
2605
2606static inline int ieee80211_is_ofdm_rate(u8 rate)
2607{
2608 switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
2609 case IEEE80211_OFDM_RATE_6MB:
2610 case IEEE80211_OFDM_RATE_9MB:
2611 case IEEE80211_OFDM_RATE_12MB:
2612 case IEEE80211_OFDM_RATE_18MB:
2613 case IEEE80211_OFDM_RATE_24MB:
2614 case IEEE80211_OFDM_RATE_36MB:
2615 case IEEE80211_OFDM_RATE_48MB:
2616 case IEEE80211_OFDM_RATE_54MB:
2617 return 1;
2618 }
2619 return 0;
2620}
2621
2622static inline int ieee80211_is_cck_rate(u8 rate)
2623{
2624 switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
2625 case IEEE80211_CCK_RATE_1MB:
2626 case IEEE80211_CCK_RATE_2MB:
2627 case IEEE80211_CCK_RATE_5MB:
2628 case IEEE80211_CCK_RATE_11MB:
2629 return 1;
2630 }
2631 return 0;
2632}
2633
2634
2635/* ieee80211.c */
2636extern void free_ieee80211(struct net_device *dev);
2637extern struct net_device *alloc_ieee80211(int sizeof_priv);
2638
2639extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
2640
2641/* ieee80211_tx.c */
2642
2643extern int ieee80211_encrypt_fragment(
2644 struct ieee80211_device *ieee,
2645 struct sk_buff *frag,
2646 int hdr_len);
2647
2648extern int ieee80211_xmit(struct sk_buff *skb,
2649 struct net_device *dev);
2650extern void ieee80211_txb_free(struct ieee80211_txb *);
2651
2652
2653/* ieee80211_rx.c */
2654extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
2655 struct ieee80211_rx_stats *rx_stats);
2656extern void ieee80211_rx_mgt(struct ieee80211_device *ieee,
2657 struct ieee80211_hdr_4addr *header,
2658 struct ieee80211_rx_stats *stats);
2659
2660/* ieee80211_wx.c */
2661extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
2662 struct iw_request_info *info,
2663 union iwreq_data *wrqu, char *key);
2664extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee,
2665 struct iw_request_info *info,
2666 union iwreq_data *wrqu, char *key);
2667extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
2668 struct iw_request_info *info,
2669 union iwreq_data *wrqu, char *key);
2670#if WIRELESS_EXT >= 18
2671extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee,
2672 struct iw_request_info *info,
2673 union iwreq_data* wrqu, char *extra);
2674extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee,
2675 struct iw_request_info *info,
2676 union iwreq_data* wrqu, char *extra);
2677extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee,
2678 struct iw_request_info *info,
2679 struct iw_param *data, char *extra);
2680extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee,
2681 struct iw_request_info *info,
2682 union iwreq_data *wrqu, char *extra);
2683#endif
2684extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len);
2685
2686/* ieee80211_softmac.c */
2687extern short ieee80211_is_54g(struct ieee80211_network net);
2688extern short ieee80211_is_shortslot(struct ieee80211_network net);
2689extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb,
2690 struct ieee80211_rx_stats *rx_stats, u16 type,
2691 u16 stype);
2692extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net);
2693
2694void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn);
2695extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee);
2696
2697extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee);
2698extern void notify_wx_assoc_event(struct ieee80211_device *ieee);
2699extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee);
2700extern void ieee80211_start_bss(struct ieee80211_device *ieee);
2701extern void ieee80211_start_master_bss(struct ieee80211_device *ieee);
2702extern void ieee80211_start_ibss(struct ieee80211_device *ieee);
2703extern void ieee80211_softmac_init(struct ieee80211_device *ieee);
2704extern void ieee80211_softmac_free(struct ieee80211_device *ieee);
2705extern void ieee80211_associate_abort(struct ieee80211_device *ieee);
2706extern void ieee80211_disassociate(struct ieee80211_device *ieee);
2707extern void ieee80211_stop_scan(struct ieee80211_device *ieee);
2708extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee);
2709extern void ieee80211_check_all_nets(struct ieee80211_device *ieee);
2710extern void ieee80211_start_protocol(struct ieee80211_device *ieee);
2711extern void ieee80211_stop_protocol(struct ieee80211_device *ieee);
2712extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee);
2713extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee);
2714extern void ieee80211_reset_queue(struct ieee80211_device *ieee);
2715extern void ieee80211_wake_queue(struct ieee80211_device *ieee);
2716extern void ieee80211_stop_queue(struct ieee80211_device *ieee);
2717extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee);
2718extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee);
2719extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee);
2720extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p);
2721extern void notify_wx_assoc_event(struct ieee80211_device *ieee);
2722extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success);
2723
2724extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee);
2725
2726/* ieee80211_crypt_ccmp&tkip&wep.c */
2727extern void ieee80211_tkip_null(void);
2728extern void ieee80211_wep_null(void);
2729extern void ieee80211_ccmp_null(void);
2730
2731/* ieee80211_softmac_wx.c */
2732
2733extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee,
2734 struct iw_request_info *info,
2735 union iwreq_data *wrqu, char *ext);
2736
2737extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee,
2738 struct iw_request_info *info,
2739 union iwreq_data *awrq,
2740 char *extra);
2741
2742extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b);
2743
2744extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee,
2745 struct iw_request_info *info,
2746 union iwreq_data *wrqu, char *extra);
2747
2748extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee,
2749 struct iw_request_info *info,
2750 union iwreq_data *wrqu, char *extra);
2751
2752extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
2753 union iwreq_data *wrqu, char *b);
2754
2755extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a,
2756 union iwreq_data *wrqu, char *b);
2757
2758extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee,
2759 struct iw_request_info *a,
2760 union iwreq_data *wrqu, char *extra);
2761
2762extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
2763 union iwreq_data *wrqu, char *b);
2764
2765extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a,
2766 union iwreq_data *wrqu, char *b);
2767
2768extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a,
2769 union iwreq_data *wrqu, char *b);
2770
2771//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee);
2772#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2773extern void ieee80211_wx_sync_scan_wq(struct work_struct *work);
2774#else
2775 extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee);
2776#endif
2777
2778
2779extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee,
2780 struct iw_request_info *info,
2781 union iwreq_data *wrqu, char *extra);
2782
2783extern int ieee80211_wx_get_name(struct ieee80211_device *ieee,
2784 struct iw_request_info *info,
2785 union iwreq_data *wrqu, char *extra);
2786
2787extern int ieee80211_wx_set_power(struct ieee80211_device *ieee,
2788 struct iw_request_info *info,
2789 union iwreq_data *wrqu, char *extra);
2790
2791extern int ieee80211_wx_get_power(struct ieee80211_device *ieee,
2792 struct iw_request_info *info,
2793 union iwreq_data *wrqu, char *extra);
2794
2795extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee,
2796 struct iw_request_info *info,
2797 union iwreq_data *wrqu, char *extra);
2798
2799extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee,
2800 struct iw_request_info *info,
2801 union iwreq_data *wrqu, char *extra);
2802//HT
2803#define MAX_RECEIVE_BUFFER_SIZE 9100 //
2804extern void HTDebugHTCapability(u8* CapIE, u8* TitleString );
2805extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString);
2806
2807void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
2808extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee);
2809extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt);
2810extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt);
2811extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len);
2812extern void HTOnAssocRsp(struct ieee80211_device *ieee);
2813extern void HTInitializeHTInfo(struct ieee80211_device* ieee);
2814extern void HTInitializeBssDesc(PBSS_HT pBssHT);
2815extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork);
2816extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork);
2817extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter);
2818extern u8 MCS_FILTER_ALL[];
2819extern u16 MCS_DATA_RATE[2][2][77] ;
2820extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame);
2821//extern void HTSetConnectBwModeCallback(unsigned long data);
2822extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo);
2823extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee);
2824extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate);
2825extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate);
2826extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate);
2827//function in BAPROC.c
2828extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb);
2829extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb);
2830extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb);
2831extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending);
2832extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect);
2833extern void BaSetupTimeOut(unsigned long data);
2834extern void TxBaInactTimeout(unsigned long data);
2835extern void RxBaInactTimeout(unsigned long data);
2836extern void ResetBaEntry( PBA_RECORD pBA);
2837//function in TS.c
2838extern bool GetTs(
2839 struct ieee80211_device* ieee,
2840 PTS_COMMON_INFO *ppTS,
2841 u8* Addr,
2842 u8 TID,
2843 TR_SELECT TxRxSelect, //Rx:1, Tx:0
2844 bool bAddNewTs
2845 );
2846extern void TSInitialize(struct ieee80211_device *ieee);
2847extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS);
2848extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr);
2849extern void RemoveAllTS(struct ieee80211_device* ieee);
2850void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee);
2851
2852extern const long ieee80211_wlan_frequencies[];
2853
2854extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
2855{
2856 ieee->scans++;
2857}
2858
2859extern inline int ieee80211_get_scans(struct ieee80211_device *ieee)
2860{
2861 return ieee->scans;
2862}
2863
2864static inline const char *escape_essid(const char *essid, u8 essid_len) {
2865 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
2866 const char *s = essid;
2867 char *d = escaped;
2868
2869 if (ieee80211_is_empty_essid(essid, essid_len)) {
2870 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
2871 return escaped;
2872 }
2873
2874 essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE);
2875 while (essid_len--) {
2876 if (*s == '\0') {
2877 *d++ = '\\';
2878 *d++ = '0';
2879 s++;
2880 } else {
2881 *d++ = *s++;
2882 }
2883 }
2884 *d = '\0';
2885 return escaped;
2886}
2887
2888/* For the function is more related to hardware setting, it's better to use the
2889 * ieee handler to refer to it.
2890 */
2891extern short check_nic_enough_desc(struct net_device *dev, int queue_index);
2892extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev);
2893extern int ieee80211_parse_info_param(struct ieee80211_device *ieee,
2894 struct ieee80211_info_element *info_element,
2895 u16 length,
2896 struct ieee80211_network *network,
2897 struct ieee80211_rx_stats *stats);
2898
2899void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index);
2900#define RT_ASOC_RETRY_LIMIT 5
2901#endif /* IEEE80211_H */
diff --git a/drivers/staging/rtl8192su/ieee80211/EndianFree.h b/drivers/staging/rtl8192su/ieee80211/EndianFree.h
new file mode 100644
index 00000000000..0c417a6234a
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/EndianFree.h
@@ -0,0 +1,199 @@
1#ifndef __INC_ENDIANFREE_H
2#define __INC_ENDIANFREE_H
3
4/*
5 * Call endian free function when
6 * 1. Read/write packet content.
7 * 2. Before write integer to IO.
8 * 3. After read integer from IO.
9 */
10#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
11#ifndef bool
12typedef enum{false = 0, true} bool;
13#endif
14#endif
15
16#define __MACHINE_LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
17#define __MACHINE_BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net, ppc */
18
19#define BYTE_ORDER __MACHINE_LITTLE_ENDIAN
20
21#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN
22// Convert data
23#define EF1Byte(_val) ((u8)(_val))
24#define EF2Byte(_val) ((u16)(_val))
25#define EF4Byte(_val) ((u32)(_val))
26
27#else
28// Convert data
29#define EF1Byte(_val) ((u8)(_val))
30#define EF2Byte(_val) (((((u16)(_val))&0x00ff)<<8)|((((u16)(_val))&0xff00)>>8))
31#define EF4Byte(_val) (((((u32)(_val))&0x000000ff)<<24)|\
32 ((((u32)(_val))&0x0000ff00)<<8)|\
33 ((((u32)(_val))&0x00ff0000)>>8)|\
34 ((((u32)(_val))&0xff000000)>>24))
35#endif
36
37// Read data from memory
38#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
39#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
40#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
41
42// Write data to memory
43#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
44#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
45#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
46// Convert Host system specific byte ording (litten or big endia) to Network byte ording (big endian).
47// 2006.05.07, by rcnjko.
48#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN
49#define H2N1BYTE(_val) ((u8)(_val))
50#define H2N2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\
51 ((((u16)(_val))&0xff00)>>8))
52#define H2N4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\
53 ((((u32)(_val))&0x0000ff00)<<8) |\
54 ((((u32)(_val))&0x00ff0000)>>8) |\
55 ((((u32)(_val))&0xff000000)>>24))
56#else
57#define H2N1BYTE(_val) ((u8)(_val))
58#define H2N2BYTE(_val) ((u16)(_val))
59#define H2N4BYTE(_val) ((u32)(_val))
60#endif
61
62// Convert from Network byte ording (big endian) to Host system specific byte ording (litten or big endia).
63// 2006.05.07, by rcnjko.
64#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN
65#define N2H1BYTE(_val) ((u8)(_val))
66#define N2H2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\
67 ((((u16)(_val))&0xff00)>>8))
68#define N2H4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\
69 ((((u32)(_val))&0x0000ff00)<<8) |\
70 ((((u32)(_val))&0x00ff0000)>>8) |\
71 ((((u32)(_val))&0xff000000)>>24))
72#else
73#define N2H1BYTE(_val) ((u8)(_val))
74#define N2H2BYTE(_val) ((u16)(_val))
75#define N2H4BYTE(_val) ((u32)(_val))
76#endif
77
78//
79// Example:
80// BIT_LEN_MASK_32(0) => 0x00000000
81// BIT_LEN_MASK_32(1) => 0x00000001
82// BIT_LEN_MASK_32(2) => 0x00000003
83// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
84//
85#define BIT_LEN_MASK_32(__BitLen) (0xFFFFFFFF >> (32 - (__BitLen)))
86//
87// Example:
88// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
89// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
90//
91#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) (BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
92
93//
94// Description:
95// Return 4-byte value in host byte ordering from
96// 4-byte pointer in litten-endian system.
97//
98#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (EF4Byte(*((u32 *)(__pStart))))
99
100//
101// Description:
102// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
103// 4-byte value in host byte ordering.
104//
105#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
106 ( \
107 ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
108 & \
109 BIT_LEN_MASK_32(__BitLen) \
110 )
111
112//
113// Description:
114// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
115// and return the result in 4-byte value in host byte ordering.
116//
117#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
118 ( \
119 LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
120 & \
121 ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
122 )
123
124//
125// Description:
126// Set subfield of little-endian 4-byte value to specified value.
127//
128#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
129 *((u32 *)(__pStart)) = \
130 EF4Byte( \
131 LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
132 | \
133 ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
134 );
135
136
137#define BIT_LEN_MASK_16(__BitLen) \
138 (0xFFFF >> (16 - (__BitLen)))
139
140#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
141 (BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
142
143#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
144 (EF2Byte(*((u16 *)(__pStart))))
145
146#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
147 ( \
148 ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
149 & \
150 BIT_LEN_MASK_16(__BitLen) \
151 )
152
153#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
154 ( \
155 LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
156 & \
157 ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
158 )
159
160#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
161 *((u16 *)(__pStart)) = \
162 EF2Byte( \
163 LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
164 | \
165 ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
166 );
167
168#define BIT_LEN_MASK_8(__BitLen) \
169 (0xFF >> (8 - (__BitLen)))
170
171#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
172 (BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
173
174#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
175 (EF1Byte(*((u8 *)(__pStart))))
176
177#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
178 ( \
179 ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
180 & \
181 BIT_LEN_MASK_8(__BitLen) \
182 )
183
184#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
185 ( \
186 LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
187 & \
188 ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
189 )
190
191#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
192 *((u8 *)(__pStart)) = \
193 EF1Byte( \
194 LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
195 | \
196 ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
197 );
198
199#endif // #ifndef __INC_ENDIANFREE_H
diff --git a/drivers/staging/rtl8192su/ieee80211/Makefile b/drivers/staging/rtl8192su/ieee80211/Makefile
new file mode 100644
index 00000000000..295a18f3c9c
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/Makefile
@@ -0,0 +1,31 @@
1NIC_SELECT = RTL8192SU
2
3EXTRA_CFLAGS += -O2
4EXTRA_CFLAGS += -DRTL8192S_DISABLE_FW_DM=0
5EXTRA_CFLAGS += -DRTL8192SU
6#EXTRA_CFLAGS += -DJOHN_NOCPY
7EXTRA_CFLAGS += -DTHOMAS_TURBO
8#flags to enable or disble 80211D feature
9EXTRA_CFLAGS += -DENABLE_DOT11D
10ieee80211-rsl-objs := ieee80211_rx.o \
11 ieee80211_softmac.o \
12 ieee80211_tx.o \
13 ieee80211_wx.o \
14 ieee80211_module.o \
15 ieee80211_softmac_wx.o\
16 rtl819x_HTProc.o\
17 rtl819x_TSProc.o\
18 rtl819x_BAProc.o\
19 dot11d.o
20
21ieee80211_crypt-rsl-objs := ieee80211_crypt.o
22ieee80211_crypt_tkip-rsl-objs := ieee80211_crypt_tkip.o
23ieee80211_crypt_ccmp-rsl-objs := ieee80211_crypt_ccmp.o
24ieee80211_crypt_wep-rsl-objs := ieee80211_crypt_wep.o
25
26obj-m +=ieee80211-rsl.o
27obj-m +=ieee80211_crypt-rsl.o
28obj-m +=ieee80211_crypt_wep-rsl.o
29obj-m +=ieee80211_crypt_tkip-rsl.o
30obj-m +=ieee80211_crypt_ccmp-rsl.o
31
diff --git a/drivers/staging/rtl8192su/ieee80211/aes.c b/drivers/staging/rtl8192su/ieee80211/aes.c
new file mode 100644
index 00000000000..0c176e29a79
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/aes.c
@@ -0,0 +1,469 @@
1/*
2 * Cryptographic API.
3 *
4 * AES Cipher Algorithm.
5 *
6 * Based on Brian Gladman's code.
7 *
8 * Linux developers:
9 * Alexander Kjeldaas <astor@fast.no>
10 * Herbert Valerio Riedel <hvr@hvrlab.org>
11 * Kyle McMartin <kyle@debian.org>
12 * Adam J. Richter <adam@yggdrasil.com> (conversion to 2.5 API).
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * ---------------------------------------------------------------------------
20 * Copyright (c) 2002, Dr Brian Gladman <brg@gladman.me.uk>, Worcester, UK.
21 * All rights reserved.
22 *
23 * LICENSE TERMS
24 *
25 * The free distribution and use of this software in both source and binary
26 * form is allowed (with or without changes) provided that:
27 *
28 * 1. distributions of this source code include the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 *
31 * 2. distributions in binary form include the above copyright
32 * notice, this list of conditions and the following disclaimer
33 * in the documentation and/or other associated materials;
34 *
35 * 3. the copyright holder's name is not used to endorse products
36 * built using this software without specific written permission.
37 *
38 * ALTERNATIVELY, provided that this notice is retained in full, this product
39 * may be distributed under the terms of the GNU General Public License (GPL),
40 * in which case the provisions of the GPL apply INSTEAD OF those given above.
41 *
42 * DISCLAIMER
43 *
44 * This software is provided 'as is' with no explicit or implied warranties
45 * in respect of its properties, including, but not limited to, correctness
46 * and/or fitness for purpose.
47 * ---------------------------------------------------------------------------
48 */
49
50/* Some changes from the Gladman version:
51 s/RIJNDAEL(e_key)/E_KEY/g
52 s/RIJNDAEL(d_key)/D_KEY/g
53*/
54
55#include <linux/module.h>
56#include <linux/init.h>
57#include <linux/types.h>
58#include <linux/errno.h>
59//#include <linux/crypto.h>
60#include "rtl_crypto.h"
61#include <asm/byteorder.h>
62
63#define AES_MIN_KEY_SIZE 16
64#define AES_MAX_KEY_SIZE 32
65
66#define AES_BLOCK_SIZE 16
67
68static inline
69u32 generic_rotr32 (const u32 x, const unsigned bits)
70{
71 const unsigned n = bits % 32;
72 return (x >> n) | (x << (32 - n));
73}
74
75static inline
76u32 generic_rotl32 (const u32 x, const unsigned bits)
77{
78 const unsigned n = bits % 32;
79 return (x << n) | (x >> (32 - n));
80}
81
82#define rotl generic_rotl32
83#define rotr generic_rotr32
84
85/*
86 * #define byte(x, nr) ((unsigned char)((x) >> (nr*8)))
87 */
88inline static u8
89byte(const u32 x, const unsigned n)
90{
91 return x >> (n << 3);
92}
93
94#define u32_in(x) le32_to_cpu(*(const u32 *)(x))
95#define u32_out(to, from) (*(u32 *)(to) = cpu_to_le32(from))
96
97struct aes_ctx {
98 int key_length;
99 u32 E[60];
100 u32 D[60];
101};
102
103#define E_KEY ctx->E
104#define D_KEY ctx->D
105
106static u8 pow_tab[256] __initdata;
107static u8 log_tab[256] __initdata;
108static u8 sbx_tab[256] __initdata;
109static u8 isb_tab[256] __initdata;
110static u32 rco_tab[10];
111static u32 ft_tab[4][256];
112static u32 it_tab[4][256];
113
114static u32 fl_tab[4][256];
115static u32 il_tab[4][256];
116
117static inline u8 __init
118f_mult (u8 a, u8 b)
119{
120 u8 aa = log_tab[a], cc = aa + log_tab[b];
121
122 return pow_tab[cc + (cc < aa ? 1 : 0)];
123}
124
125#define ff_mult(a,b) (a && b ? f_mult(a, b) : 0)
126
127#define f_rn(bo, bi, n, k) \
128 bo[n] = ft_tab[0][byte(bi[n],0)] ^ \
129 ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
130 ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
131 ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
132
133#define i_rn(bo, bi, n, k) \
134 bo[n] = it_tab[0][byte(bi[n],0)] ^ \
135 it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
136 it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
137 it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
138
139#define ls_box(x) \
140 ( fl_tab[0][byte(x, 0)] ^ \
141 fl_tab[1][byte(x, 1)] ^ \
142 fl_tab[2][byte(x, 2)] ^ \
143 fl_tab[3][byte(x, 3)] )
144
145#define f_rl(bo, bi, n, k) \
146 bo[n] = fl_tab[0][byte(bi[n],0)] ^ \
147 fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
148 fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
149 fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
150
151#define i_rl(bo, bi, n, k) \
152 bo[n] = il_tab[0][byte(bi[n],0)] ^ \
153 il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
154 il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
155 il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
156
157static void __init
158gen_tabs (void)
159{
160 u32 i, t;
161 u8 p, q;
162
163 /* log and power tables for GF(2**8) finite field with
164 0x011b as modular polynomial - the simplest primitive
165 root is 0x03, used here to generate the tables */
166
167 for (i = 0, p = 1; i < 256; ++i) {
168 pow_tab[i] = (u8) p;
169 log_tab[p] = (u8) i;
170
171 p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0);
172 }
173
174 log_tab[1] = 0;
175
176 for (i = 0, p = 1; i < 10; ++i) {
177 rco_tab[i] = p;
178
179 p = (p << 1) ^ (p & 0x80 ? 0x01b : 0);
180 }
181
182 for (i = 0; i < 256; ++i) {
183 p = (i ? pow_tab[255 - log_tab[i]] : 0);
184 q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2));
185 p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2));
186 sbx_tab[i] = p;
187 isb_tab[p] = (u8) i;
188 }
189
190 for (i = 0; i < 256; ++i) {
191 p = sbx_tab[i];
192
193 t = p;
194 fl_tab[0][i] = t;
195 fl_tab[1][i] = rotl (t, 8);
196 fl_tab[2][i] = rotl (t, 16);
197 fl_tab[3][i] = rotl (t, 24);
198
199 t = ((u32) ff_mult (2, p)) |
200 ((u32) p << 8) |
201 ((u32) p << 16) | ((u32) ff_mult (3, p) << 24);
202
203 ft_tab[0][i] = t;
204 ft_tab[1][i] = rotl (t, 8);
205 ft_tab[2][i] = rotl (t, 16);
206 ft_tab[3][i] = rotl (t, 24);
207
208 p = isb_tab[i];
209
210 t = p;
211 il_tab[0][i] = t;
212 il_tab[1][i] = rotl (t, 8);
213 il_tab[2][i] = rotl (t, 16);
214 il_tab[3][i] = rotl (t, 24);
215
216 t = ((u32) ff_mult (14, p)) |
217 ((u32) ff_mult (9, p) << 8) |
218 ((u32) ff_mult (13, p) << 16) |
219 ((u32) ff_mult (11, p) << 24);
220
221 it_tab[0][i] = t;
222 it_tab[1][i] = rotl (t, 8);
223 it_tab[2][i] = rotl (t, 16);
224 it_tab[3][i] = rotl (t, 24);
225 }
226}
227
228#define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b)
229
230#define imix_col(y,x) \
231 u = star_x(x); \
232 v = star_x(u); \
233 w = star_x(v); \
234 t = w ^ (x); \
235 (y) = u ^ v ^ w; \
236 (y) ^= rotr(u ^ t, 8) ^ \
237 rotr(v ^ t, 16) ^ \
238 rotr(t,24)
239
240/* initialise the key schedule from the user supplied key */
241
242#define loop4(i) \
243{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
244 t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \
245 t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \
246 t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \
247 t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \
248}
249
250#define loop6(i) \
251{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
252 t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \
253 t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \
254 t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \
255 t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \
256 t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \
257 t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \
258}
259
260#define loop8(i) \
261{ t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \
262 t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \
263 t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \
264 t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \
265 t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \
266 t = E_KEY[8 * i + 4] ^ ls_box(t); \
267 E_KEY[8 * i + 12] = t; \
268 t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \
269 t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \
270 t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \
271}
272
273static int
274aes_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags)
275{
276 struct aes_ctx *ctx = ctx_arg;
277 u32 i, t, u, v, w;
278
279 if (key_len != 16 && key_len != 24 && key_len != 32) {
280 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
281 return -EINVAL;
282 }
283
284 ctx->key_length = key_len;
285
286 E_KEY[0] = u32_in (in_key);
287 E_KEY[1] = u32_in (in_key + 4);
288 E_KEY[2] = u32_in (in_key + 8);
289 E_KEY[3] = u32_in (in_key + 12);
290
291 switch (key_len) {
292 case 16:
293 t = E_KEY[3];
294 for (i = 0; i < 10; ++i)
295 loop4 (i);
296 break;
297
298 case 24:
299 E_KEY[4] = u32_in (in_key + 16);
300 t = E_KEY[5] = u32_in (in_key + 20);
301 for (i = 0; i < 8; ++i)
302 loop6 (i);
303 break;
304
305 case 32:
306 E_KEY[4] = u32_in (in_key + 16);
307 E_KEY[5] = u32_in (in_key + 20);
308 E_KEY[6] = u32_in (in_key + 24);
309 t = E_KEY[7] = u32_in (in_key + 28);
310 for (i = 0; i < 7; ++i)
311 loop8 (i);
312 break;
313 }
314
315 D_KEY[0] = E_KEY[0];
316 D_KEY[1] = E_KEY[1];
317 D_KEY[2] = E_KEY[2];
318 D_KEY[3] = E_KEY[3];
319
320 for (i = 4; i < key_len + 24; ++i) {
321 imix_col (D_KEY[i], E_KEY[i]);
322 }
323
324 return 0;
325}
326
327/* encrypt a block of text */
328
329#define f_nround(bo, bi, k) \
330 f_rn(bo, bi, 0, k); \
331 f_rn(bo, bi, 1, k); \
332 f_rn(bo, bi, 2, k); \
333 f_rn(bo, bi, 3, k); \
334 k += 4
335
336#define f_lround(bo, bi, k) \
337 f_rl(bo, bi, 0, k); \
338 f_rl(bo, bi, 1, k); \
339 f_rl(bo, bi, 2, k); \
340 f_rl(bo, bi, 3, k)
341
342static void aes_encrypt(void *ctx_arg, u8 *out, const u8 *in)
343{
344 const struct aes_ctx *ctx = ctx_arg;
345 u32 b0[4], b1[4];
346 const u32 *kp = E_KEY + 4;
347
348 b0[0] = u32_in (in) ^ E_KEY[0];
349 b0[1] = u32_in (in + 4) ^ E_KEY[1];
350 b0[2] = u32_in (in + 8) ^ E_KEY[2];
351 b0[3] = u32_in (in + 12) ^ E_KEY[3];
352
353 if (ctx->key_length > 24) {
354 f_nround (b1, b0, kp);
355 f_nround (b0, b1, kp);
356 }
357
358 if (ctx->key_length > 16) {
359 f_nround (b1, b0, kp);
360 f_nround (b0, b1, kp);
361 }
362
363 f_nround (b1, b0, kp);
364 f_nround (b0, b1, kp);
365 f_nround (b1, b0, kp);
366 f_nround (b0, b1, kp);
367 f_nround (b1, b0, kp);
368 f_nround (b0, b1, kp);
369 f_nround (b1, b0, kp);
370 f_nround (b0, b1, kp);
371 f_nround (b1, b0, kp);
372 f_lround (b0, b1, kp);
373
374 u32_out (out, b0[0]);
375 u32_out (out + 4, b0[1]);
376 u32_out (out + 8, b0[2]);
377 u32_out (out + 12, b0[3]);
378}
379
380/* decrypt a block of text */
381
382#define i_nround(bo, bi, k) \
383 i_rn(bo, bi, 0, k); \
384 i_rn(bo, bi, 1, k); \
385 i_rn(bo, bi, 2, k); \
386 i_rn(bo, bi, 3, k); \
387 k -= 4
388
389#define i_lround(bo, bi, k) \
390 i_rl(bo, bi, 0, k); \
391 i_rl(bo, bi, 1, k); \
392 i_rl(bo, bi, 2, k); \
393 i_rl(bo, bi, 3, k)
394
395static void aes_decrypt(void *ctx_arg, u8 *out, const u8 *in)
396{
397 const struct aes_ctx *ctx = ctx_arg;
398 u32 b0[4], b1[4];
399 const int key_len = ctx->key_length;
400 const u32 *kp = D_KEY + key_len + 20;
401
402 b0[0] = u32_in (in) ^ E_KEY[key_len + 24];
403 b0[1] = u32_in (in + 4) ^ E_KEY[key_len + 25];
404 b0[2] = u32_in (in + 8) ^ E_KEY[key_len + 26];
405 b0[3] = u32_in (in + 12) ^ E_KEY[key_len + 27];
406
407 if (key_len > 24) {
408 i_nround (b1, b0, kp);
409 i_nround (b0, b1, kp);
410 }
411
412 if (key_len > 16) {
413 i_nround (b1, b0, kp);
414 i_nround (b0, b1, kp);
415 }
416
417 i_nround (b1, b0, kp);
418 i_nround (b0, b1, kp);
419 i_nround (b1, b0, kp);
420 i_nround (b0, b1, kp);
421 i_nround (b1, b0, kp);
422 i_nround (b0, b1, kp);
423 i_nround (b1, b0, kp);
424 i_nround (b0, b1, kp);
425 i_nround (b1, b0, kp);
426 i_lround (b0, b1, kp);
427
428 u32_out (out, b0[0]);
429 u32_out (out + 4, b0[1]);
430 u32_out (out + 8, b0[2]);
431 u32_out (out + 12, b0[3]);
432}
433
434
435static struct crypto_alg aes_alg = {
436 .cra_name = "aes",
437 .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
438 .cra_blocksize = AES_BLOCK_SIZE,
439 .cra_ctxsize = sizeof(struct aes_ctx),
440 .cra_module = THIS_MODULE,
441 .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
442 .cra_u = {
443 .cipher = {
444 .cia_min_keysize = AES_MIN_KEY_SIZE,
445 .cia_max_keysize = AES_MAX_KEY_SIZE,
446 .cia_setkey = aes_set_key,
447 .cia_encrypt = aes_encrypt,
448 .cia_decrypt = aes_decrypt
449 }
450 }
451};
452
453static int __init aes_init(void)
454{
455 gen_tabs();
456 return crypto_register_alg(&aes_alg);
457}
458
459static void __exit aes_fini(void)
460{
461 crypto_unregister_alg(&aes_alg);
462}
463
464module_init(aes_init);
465module_exit(aes_fini);
466
467MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
468MODULE_LICENSE("Dual BSD/GPL");
469
diff --git a/drivers/staging/rtl8192su/ieee80211/api.c b/drivers/staging/rtl8192su/ieee80211/api.c
new file mode 100644
index 00000000000..c627d029528
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/api.c
@@ -0,0 +1,246 @@
1/*
2 * Scatterlist Cryptographic API.
3 *
4 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
5 * Copyright (c) 2002 David S. Miller (davem@redhat.com)
6 *
7 * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no>
8 * and Nettle, by Niels Mé°ˆler.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 */
16#include "kmap_types.h"
17
18#include <linux/init.h>
19#include <linux/module.h>
20//#include <linux/crypto.h>
21#include "rtl_crypto.h"
22#include <linux/errno.h>
23#include <linux/rwsem.h>
24#include <linux/slab.h>
25#include "internal.h"
26
27LIST_HEAD(crypto_alg_list);
28DECLARE_RWSEM(crypto_alg_sem);
29
30static inline int crypto_alg_get(struct crypto_alg *alg)
31{
32 return try_inc_mod_count(alg->cra_module);
33}
34
35static inline void crypto_alg_put(struct crypto_alg *alg)
36{
37 if (alg->cra_module)
38 __MOD_DEC_USE_COUNT(alg->cra_module);
39}
40
41struct crypto_alg *crypto_alg_lookup(const char *name)
42{
43 struct crypto_alg *q, *alg = NULL;
44
45 if (!name)
46 return NULL;
47
48 down_read(&crypto_alg_sem);
49
50 list_for_each_entry(q, &crypto_alg_list, cra_list) {
51 if (!(strcmp(q->cra_name, name))) {
52 if (crypto_alg_get(q))
53 alg = q;
54 break;
55 }
56 }
57
58 up_read(&crypto_alg_sem);
59 return alg;
60}
61
62static int crypto_init_flags(struct crypto_tfm *tfm, u32 flags)
63{
64 tfm->crt_flags = 0;
65
66 switch (crypto_tfm_alg_type(tfm)) {
67 case CRYPTO_ALG_TYPE_CIPHER:
68 return crypto_init_cipher_flags(tfm, flags);
69
70 case CRYPTO_ALG_TYPE_DIGEST:
71 return crypto_init_digest_flags(tfm, flags);
72
73 case CRYPTO_ALG_TYPE_COMPRESS:
74 return crypto_init_compress_flags(tfm, flags);
75
76 default:
77 break;
78 }
79
80 BUG();
81 return -EINVAL;
82}
83
84static int crypto_init_ops(struct crypto_tfm *tfm)
85{
86 switch (crypto_tfm_alg_type(tfm)) {
87 case CRYPTO_ALG_TYPE_CIPHER:
88 return crypto_init_cipher_ops(tfm);
89
90 case CRYPTO_ALG_TYPE_DIGEST:
91 return crypto_init_digest_ops(tfm);
92
93 case CRYPTO_ALG_TYPE_COMPRESS:
94 return crypto_init_compress_ops(tfm);
95
96 default:
97 break;
98 }
99
100 BUG();
101 return -EINVAL;
102}
103
104static void crypto_exit_ops(struct crypto_tfm *tfm)
105{
106 switch (crypto_tfm_alg_type(tfm)) {
107 case CRYPTO_ALG_TYPE_CIPHER:
108 crypto_exit_cipher_ops(tfm);
109 break;
110
111 case CRYPTO_ALG_TYPE_DIGEST:
112 crypto_exit_digest_ops(tfm);
113 break;
114
115 case CRYPTO_ALG_TYPE_COMPRESS:
116 crypto_exit_compress_ops(tfm);
117 break;
118
119 default:
120 BUG();
121
122 }
123}
124
125struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags)
126{
127 struct crypto_tfm *tfm = NULL;
128 struct crypto_alg *alg;
129
130 alg = crypto_alg_mod_lookup(name);
131 if (alg == NULL)
132 goto out;
133
134 tfm = kmalloc(sizeof(*tfm) + alg->cra_ctxsize, GFP_KERNEL);
135 if (tfm == NULL)
136 goto out_put;
137
138 memset(tfm, 0, sizeof(*tfm) + alg->cra_ctxsize);
139
140 tfm->__crt_alg = alg;
141
142 if (crypto_init_flags(tfm, flags))
143 goto out_free_tfm;
144
145 if (crypto_init_ops(tfm)) {
146 crypto_exit_ops(tfm);
147 goto out_free_tfm;
148 }
149
150 goto out;
151
152out_free_tfm:
153 kfree(tfm);
154 tfm = NULL;
155out_put:
156 crypto_alg_put(alg);
157out:
158 return tfm;
159}
160
161void crypto_free_tfm(struct crypto_tfm *tfm)
162{
163 struct crypto_alg *alg = tfm->__crt_alg;
164 int size = sizeof(*tfm) + alg->cra_ctxsize;
165
166 crypto_exit_ops(tfm);
167 crypto_alg_put(alg);
168 memset(tfm, 0, size);
169 kfree(tfm);
170}
171
172int crypto_register_alg(struct crypto_alg *alg)
173{
174 int ret = 0;
175 struct crypto_alg *q;
176
177 down_write(&crypto_alg_sem);
178
179 list_for_each_entry(q, &crypto_alg_list, cra_list) {
180 if (!(strcmp(q->cra_name, alg->cra_name))) {
181 ret = -EEXIST;
182 goto out;
183 }
184 }
185
186 list_add_tail(&alg->cra_list, &crypto_alg_list);
187out:
188 up_write(&crypto_alg_sem);
189 return ret;
190}
191
192int crypto_unregister_alg(struct crypto_alg *alg)
193{
194 int ret = -ENOENT;
195 struct crypto_alg *q;
196
197 BUG_ON(!alg->cra_module);
198
199 down_write(&crypto_alg_sem);
200 list_for_each_entry(q, &crypto_alg_list, cra_list) {
201 if (alg == q) {
202 list_del(&alg->cra_list);
203 ret = 0;
204 goto out;
205 }
206 }
207out:
208 up_write(&crypto_alg_sem);
209 return ret;
210}
211
212int crypto_alg_available(const char *name, u32 flags)
213{
214 int ret = 0;
215 struct crypto_alg *alg = crypto_alg_mod_lookup(name);
216
217 if (alg) {
218 crypto_alg_put(alg);
219 ret = 1;
220 }
221
222 return ret;
223}
224
225static int __init init_crypto(void)
226{
227 printk(KERN_INFO "Initializing Cryptographic API\n");
228 crypto_init_proc();
229 return 0;
230}
231
232__initcall(init_crypto);
233
234/*
235EXPORT_SYMBOL_GPL(crypto_register_alg);
236EXPORT_SYMBOL_GPL(crypto_unregister_alg);
237EXPORT_SYMBOL_GPL(crypto_alloc_tfm);
238EXPORT_SYMBOL_GPL(crypto_free_tfm);
239EXPORT_SYMBOL_GPL(crypto_alg_available);
240*/
241
242EXPORT_SYMBOL_NOVERS(crypto_register_alg);
243EXPORT_SYMBOL_NOVERS(crypto_unregister_alg);
244EXPORT_SYMBOL_NOVERS(crypto_alloc_tfm);
245EXPORT_SYMBOL_NOVERS(crypto_free_tfm);
246EXPORT_SYMBOL_NOVERS(crypto_alg_available);
diff --git a/drivers/staging/rtl8192su/ieee80211/arc4.c b/drivers/staging/rtl8192su/ieee80211/arc4.c
new file mode 100644
index 00000000000..e408472af30
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/arc4.c
@@ -0,0 +1,103 @@
1/*
2 * Cryptographic API
3 *
4 * ARC4 Cipher Algorithm
5 *
6 * Jon Oberheide <jon@oberheide.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include "rtl_crypto.h"
17
18#define ARC4_MIN_KEY_SIZE 1
19#define ARC4_MAX_KEY_SIZE 256
20#define ARC4_BLOCK_SIZE 1
21
22struct arc4_ctx {
23 u8 S[256];
24 u8 x, y;
25};
26
27static int arc4_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags)
28{
29 struct arc4_ctx *ctx = ctx_arg;
30 int i, j = 0, k = 0;
31
32 ctx->x = 1;
33 ctx->y = 0;
34
35 for(i = 0; i < 256; i++)
36 ctx->S[i] = i;
37
38 for(i = 0; i < 256; i++)
39 {
40 u8 a = ctx->S[i];
41 j = (j + in_key[k] + a) & 0xff;
42 ctx->S[i] = ctx->S[j];
43 ctx->S[j] = a;
44 if((unsigned int)++k >= key_len)
45 k = 0;
46 }
47
48 return 0;
49}
50
51static void arc4_crypt(void *ctx_arg, u8 *out, const u8 *in)
52{
53 struct arc4_ctx *ctx = ctx_arg;
54
55 u8 *const S = ctx->S;
56 u8 x = ctx->x;
57 u8 y = ctx->y;
58 u8 a, b;
59
60 a = S[x];
61 y = (y + a) & 0xff;
62 b = S[y];
63 S[x] = b;
64 S[y] = a;
65 x = (x + 1) & 0xff;
66 *out++ = *in ^ S[(a + b) & 0xff];
67
68 ctx->x = x;
69 ctx->y = y;
70}
71
72static struct crypto_alg arc4_alg = {
73 .cra_name = "arc4",
74 .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
75 .cra_blocksize = ARC4_BLOCK_SIZE,
76 .cra_ctxsize = sizeof(struct arc4_ctx),
77 .cra_module = THIS_MODULE,
78 .cra_list = LIST_HEAD_INIT(arc4_alg.cra_list),
79 .cra_u = { .cipher = {
80 .cia_min_keysize = ARC4_MIN_KEY_SIZE,
81 .cia_max_keysize = ARC4_MAX_KEY_SIZE,
82 .cia_setkey = arc4_set_key,
83 .cia_encrypt = arc4_crypt,
84 .cia_decrypt = arc4_crypt } }
85};
86
87static int __init arc4_init(void)
88{
89 return crypto_register_alg(&arc4_alg);
90}
91
92
93static void __exit arc4_exit(void)
94{
95 crypto_unregister_alg(&arc4_alg);
96}
97
98module_init(arc4_init);
99module_exit(arc4_exit);
100
101MODULE_LICENSE("GPL");
102MODULE_DESCRIPTION("ARC4 Cipher Algorithm");
103MODULE_AUTHOR("Jon Oberheide <jon@oberheide.org>");
diff --git a/drivers/staging/rtl8192su/ieee80211/autoload.c b/drivers/staging/rtl8192su/ieee80211/autoload.c
new file mode 100644
index 00000000000..c97756f3b2e
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/autoload.c
@@ -0,0 +1,40 @@
1/*
2 * Cryptographic API.
3 *
4 * Algorithm autoloader.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14#include "kmap_types.h"
15
16#include <linux/kernel.h>
17//#include <linux/crypto.h>
18#include "rtl_crypto.h"
19#include <linux/string.h>
20#include <linux/kmod.h>
21#include "internal.h"
22
23/*
24 * A far more intelligent version of this is planned. For now, just
25 * try an exact match on the name of the algorithm.
26 */
27void crypto_alg_autoload(const char *name)
28{
29 request_module(name);
30}
31
32struct crypto_alg *crypto_alg_mod_lookup(const char *name)
33{
34 struct crypto_alg *alg = crypto_alg_lookup(name);
35 if (alg == NULL) {
36 crypto_alg_autoload(name);
37 alg = crypto_alg_lookup(name);
38 }
39 return alg;
40}
diff --git a/drivers/staging/rtl8192su/ieee80211/cipher.c b/drivers/staging/rtl8192su/ieee80211/cipher.c
new file mode 100644
index 00000000000..1968acfe32b
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/cipher.c
@@ -0,0 +1,299 @@
1/*
2 * Cryptographic API.
3 *
4 * Cipher operations.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14#include <linux/kernel.h>
15//#include <linux/crypto.h>
16#include "rtl_crypto.h"
17#include <linux/errno.h>
18#include <linux/mm.h>
19#include <linux/slab.h>
20#include <asm/scatterlist.h>
21#include "internal.h"
22#include "scatterwalk.h"
23
24typedef void (cryptfn_t)(void *, u8 *, const u8 *);
25typedef void (procfn_t)(struct crypto_tfm *, u8 *,
26 u8*, cryptfn_t, int enc, void *, int);
27
28static inline void xor_64(u8 *a, const u8 *b)
29{
30 ((u32 *)a)[0] ^= ((u32 *)b)[0];
31 ((u32 *)a)[1] ^= ((u32 *)b)[1];
32}
33
34static inline void xor_128(u8 *a, const u8 *b)
35{
36 ((u32 *)a)[0] ^= ((u32 *)b)[0];
37 ((u32 *)a)[1] ^= ((u32 *)b)[1];
38 ((u32 *)a)[2] ^= ((u32 *)b)[2];
39 ((u32 *)a)[3] ^= ((u32 *)b)[3];
40}
41
42
43/*
44 * Generic encrypt/decrypt wrapper for ciphers, handles operations across
45 * multiple page boundaries by using temporary blocks. In user context,
46 * the kernel is given a chance to schedule us once per block.
47 */
48static int crypt(struct crypto_tfm *tfm,
49 struct scatterlist *dst,
50 struct scatterlist *src,
51 unsigned int nbytes, cryptfn_t crfn,
52 procfn_t prfn, int enc, void *info)
53{
54 struct scatter_walk walk_in, walk_out;
55 const unsigned int bsize = crypto_tfm_alg_blocksize(tfm);
56 u8 tmp_src[bsize];
57 u8 tmp_dst[bsize];
58
59 if (!nbytes)
60 return 0;
61
62 if (nbytes % bsize) {
63 tfm->crt_flags |= CRYPTO_TFM_RES_BAD_BLOCK_LEN;
64 return -EINVAL;
65 }
66
67 scatterwalk_start(&walk_in, src);
68 scatterwalk_start(&walk_out, dst);
69
70 for(;;) {
71 u8 *src_p, *dst_p;
72 int in_place;
73
74 scatterwalk_map(&walk_in, 0);
75 scatterwalk_map(&walk_out, 1);
76 src_p = scatterwalk_whichbuf(&walk_in, bsize, tmp_src);
77 dst_p = scatterwalk_whichbuf(&walk_out, bsize, tmp_dst);
78 in_place = scatterwalk_samebuf(&walk_in, &walk_out,
79 src_p, dst_p);
80
81 nbytes -= bsize;
82
83 scatterwalk_copychunks(src_p, &walk_in, bsize, 0);
84
85 prfn(tfm, dst_p, src_p, crfn, enc, info, in_place);
86
87 scatterwalk_done(&walk_in, 0, nbytes);
88
89 scatterwalk_copychunks(dst_p, &walk_out, bsize, 1);
90 scatterwalk_done(&walk_out, 1, nbytes);
91
92 if (!nbytes)
93 return 0;
94
95 crypto_yield(tfm);
96 }
97}
98
99static void cbc_process(struct crypto_tfm *tfm, u8 *dst, u8 *src,
100 cryptfn_t fn, int enc, void *info, int in_place)
101{
102 u8 *iv = info;
103
104 /* Null encryption */
105 if (!iv)
106 return;
107
108 if (enc) {
109 tfm->crt_u.cipher.cit_xor_block(iv, src);
110 fn(crypto_tfm_ctx(tfm), dst, iv);
111 memcpy(iv, dst, crypto_tfm_alg_blocksize(tfm));
112 } else {
113 u8 stack[in_place ? crypto_tfm_alg_blocksize(tfm) : 0];
114 u8 *buf = in_place ? stack : dst;
115
116 fn(crypto_tfm_ctx(tfm), buf, src);
117 tfm->crt_u.cipher.cit_xor_block(buf, iv);
118 memcpy(iv, src, crypto_tfm_alg_blocksize(tfm));
119 if (buf != dst)
120 memcpy(dst, buf, crypto_tfm_alg_blocksize(tfm));
121 }
122}
123
124static void ecb_process(struct crypto_tfm *tfm, u8 *dst, u8 *src,
125 cryptfn_t fn, int enc, void *info, int in_place)
126{
127 fn(crypto_tfm_ctx(tfm), dst, src);
128}
129
130static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
131{
132 struct cipher_alg *cia = &tfm->__crt_alg->cra_cipher;
133
134 if (keylen < cia->cia_min_keysize || keylen > cia->cia_max_keysize) {
135 tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
136 return -EINVAL;
137 } else
138 return cia->cia_setkey(crypto_tfm_ctx(tfm), key, keylen,
139 &tfm->crt_flags);
140}
141
142static int ecb_encrypt(struct crypto_tfm *tfm,
143 struct scatterlist *dst,
144 struct scatterlist *src, unsigned int nbytes)
145{
146 return crypt(tfm, dst, src, nbytes,
147 tfm->__crt_alg->cra_cipher.cia_encrypt,
148 ecb_process, 1, NULL);
149}
150
151static int ecb_decrypt(struct crypto_tfm *tfm,
152 struct scatterlist *dst,
153 struct scatterlist *src,
154 unsigned int nbytes)
155{
156 return crypt(tfm, dst, src, nbytes,
157 tfm->__crt_alg->cra_cipher.cia_decrypt,
158 ecb_process, 1, NULL);
159}
160
161static int cbc_encrypt(struct crypto_tfm *tfm,
162 struct scatterlist *dst,
163 struct scatterlist *src,
164 unsigned int nbytes)
165{
166 return crypt(tfm, dst, src, nbytes,
167 tfm->__crt_alg->cra_cipher.cia_encrypt,
168 cbc_process, 1, tfm->crt_cipher.cit_iv);
169}
170
171static int cbc_encrypt_iv(struct crypto_tfm *tfm,
172 struct scatterlist *dst,
173 struct scatterlist *src,
174 unsigned int nbytes, u8 *iv)
175{
176 return crypt(tfm, dst, src, nbytes,
177 tfm->__crt_alg->cra_cipher.cia_encrypt,
178 cbc_process, 1, iv);
179}
180
181static int cbc_decrypt(struct crypto_tfm *tfm,
182 struct scatterlist *dst,
183 struct scatterlist *src,
184 unsigned int nbytes)
185{
186 return crypt(tfm, dst, src, nbytes,
187 tfm->__crt_alg->cra_cipher.cia_decrypt,
188 cbc_process, 0, tfm->crt_cipher.cit_iv);
189}
190
191static int cbc_decrypt_iv(struct crypto_tfm *tfm,
192 struct scatterlist *dst,
193 struct scatterlist *src,
194 unsigned int nbytes, u8 *iv)
195{
196 return crypt(tfm, dst, src, nbytes,
197 tfm->__crt_alg->cra_cipher.cia_decrypt,
198 cbc_process, 0, iv);
199}
200
201static int nocrypt(struct crypto_tfm *tfm,
202 struct scatterlist *dst,
203 struct scatterlist *src,
204 unsigned int nbytes)
205{
206 return -ENOSYS;
207}
208
209static int nocrypt_iv(struct crypto_tfm *tfm,
210 struct scatterlist *dst,
211 struct scatterlist *src,
212 unsigned int nbytes, u8 *iv)
213{
214 return -ENOSYS;
215}
216
217int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags)
218{
219 u32 mode = flags & CRYPTO_TFM_MODE_MASK;
220
221 tfm->crt_cipher.cit_mode = mode ? mode : CRYPTO_TFM_MODE_ECB;
222 if (flags & CRYPTO_TFM_REQ_WEAK_KEY)
223 tfm->crt_flags = CRYPTO_TFM_REQ_WEAK_KEY;
224
225 return 0;
226}
227
228int crypto_init_cipher_ops(struct crypto_tfm *tfm)
229{
230 int ret = 0;
231 struct cipher_tfm *ops = &tfm->crt_cipher;
232
233 ops->cit_setkey = setkey;
234
235 switch (tfm->crt_cipher.cit_mode) {
236 case CRYPTO_TFM_MODE_ECB:
237 ops->cit_encrypt = ecb_encrypt;
238 ops->cit_decrypt = ecb_decrypt;
239 break;
240
241 case CRYPTO_TFM_MODE_CBC:
242 ops->cit_encrypt = cbc_encrypt;
243 ops->cit_decrypt = cbc_decrypt;
244 ops->cit_encrypt_iv = cbc_encrypt_iv;
245 ops->cit_decrypt_iv = cbc_decrypt_iv;
246 break;
247
248 case CRYPTO_TFM_MODE_CFB:
249 ops->cit_encrypt = nocrypt;
250 ops->cit_decrypt = nocrypt;
251 ops->cit_encrypt_iv = nocrypt_iv;
252 ops->cit_decrypt_iv = nocrypt_iv;
253 break;
254
255 case CRYPTO_TFM_MODE_CTR:
256 ops->cit_encrypt = nocrypt;
257 ops->cit_decrypt = nocrypt;
258 ops->cit_encrypt_iv = nocrypt_iv;
259 ops->cit_decrypt_iv = nocrypt_iv;
260 break;
261
262 default:
263 BUG();
264 }
265
266 if (ops->cit_mode == CRYPTO_TFM_MODE_CBC) {
267
268 switch (crypto_tfm_alg_blocksize(tfm)) {
269 case 8:
270 ops->cit_xor_block = xor_64;
271 break;
272
273 case 16:
274 ops->cit_xor_block = xor_128;
275 break;
276
277 default:
278 printk(KERN_WARNING "%s: block size %u not supported\n",
279 crypto_tfm_alg_name(tfm),
280 crypto_tfm_alg_blocksize(tfm));
281 ret = -EINVAL;
282 goto out;
283 }
284
285 ops->cit_ivsize = crypto_tfm_alg_blocksize(tfm);
286 ops->cit_iv = kmalloc(ops->cit_ivsize, GFP_KERNEL);
287 if (ops->cit_iv == NULL)
288 ret = -ENOMEM;
289 }
290
291out:
292 return ret;
293}
294
295void crypto_exit_cipher_ops(struct crypto_tfm *tfm)
296{
297 if (tfm->crt_cipher.cit_iv)
298 kfree(tfm->crt_cipher.cit_iv);
299}
diff --git a/drivers/staging/rtl8192su/ieee80211/compress.c b/drivers/staging/rtl8192su/ieee80211/compress.c
new file mode 100644
index 00000000000..c2df80e2ed9
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/compress.c
@@ -0,0 +1,64 @@
1/*
2 * Cryptographic API.
3 *
4 * Compression operations.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14#include <linux/types.h>
15//#include <linux/crypto.h>
16#include "rtl_crypto.h"
17#include <linux/errno.h>
18#include <asm/scatterlist.h>
19#include <linux/string.h>
20#include "internal.h"
21
22static int crypto_compress(struct crypto_tfm *tfm,
23 const u8 *src, unsigned int slen,
24 u8 *dst, unsigned int *dlen)
25{
26 return tfm->__crt_alg->cra_compress.coa_compress(crypto_tfm_ctx(tfm),
27 src, slen, dst,
28 dlen);
29}
30
31static int crypto_decompress(struct crypto_tfm *tfm,
32 const u8 *src, unsigned int slen,
33 u8 *dst, unsigned int *dlen)
34{
35 return tfm->__crt_alg->cra_compress.coa_decompress(crypto_tfm_ctx(tfm),
36 src, slen, dst,
37 dlen);
38}
39
40int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags)
41{
42 return flags ? -EINVAL : 0;
43}
44
45int crypto_init_compress_ops(struct crypto_tfm *tfm)
46{
47 int ret = 0;
48 struct compress_tfm *ops = &tfm->crt_compress;
49
50 ret = tfm->__crt_alg->cra_compress.coa_init(crypto_tfm_ctx(tfm));
51 if (ret)
52 goto out;
53
54 ops->cot_compress = crypto_compress;
55 ops->cot_decompress = crypto_decompress;
56
57out:
58 return ret;
59}
60
61void crypto_exit_compress_ops(struct crypto_tfm *tfm)
62{
63 tfm->__crt_alg->cra_compress.coa_exit(crypto_tfm_ctx(tfm));
64}
diff --git a/drivers/staging/rtl8192su/ieee80211/crypto_compat.h b/drivers/staging/rtl8192su/ieee80211/crypto_compat.h
new file mode 100644
index 00000000000..587e8bb2db6
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/crypto_compat.h
@@ -0,0 +1,90 @@
1/*
2 * Header file to maintain compatibility among different kernel versions.
3 *
4 * Copyright (c) 2004-2006 <lawrence_wang@realsil.com.cn>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. See README and COPYING for
9 * more details.
10 */
11
12#include <linux/crypto.h>
13
14static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm,
15 struct scatterlist *dst,
16 struct scatterlist *src,
17 unsigned int nbytes)
18{
19 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
20 return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes);
21}
22
23
24static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm,
25 struct scatterlist *dst,
26 struct scatterlist *src,
27 unsigned int nbytes)
28{
29 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
30 return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes);
31}
32
33#if 0
34/*
35 * crypto_free_tfm - Free crypto transform
36 * @tfm: Transform to free
37 *
38 * crypto_free_tfm() frees up the transform and any associated resources,
39 * then drops the refcount on the associated algorithm.
40 */
41void crypto_free_tfm(struct crypto_tfm *tfm)
42{
43 struct crypto_alg *alg;
44 int size;
45
46 if (unlikely(!tfm))
47 return;
48
49 alg = tfm->__crt_alg;
50 size = sizeof(*tfm) + alg->cra_ctxsize;
51
52 if (alg->cra_exit)
53 alg->cra_exit(tfm);
54 crypto_exit_ops(tfm);
55 crypto_mod_put(alg);
56 memset(tfm, 0, size);
57 kfree(tfm);
58}
59
60#endif
61#if 1
62 struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags)
63{
64 struct crypto_tfm *tfm = NULL;
65 int err;
66 printk("call crypto_alloc_tfm!!!\n");
67 do {
68 struct crypto_alg *alg;
69
70 alg = crypto_alg_mod_lookup(name, 0, CRYPTO_ALG_ASYNC);
71 err = PTR_ERR(alg);
72 if (IS_ERR(alg))
73 continue;
74
75 tfm = __crypto_alloc_tfm(alg, flags);
76 err = 0;
77 if (IS_ERR(tfm)) {
78 crypto_mod_put(alg);
79 err = PTR_ERR(tfm);
80 tfm = NULL;
81 }
82 } while (err == -EAGAIN && !signal_pending(current));
83
84 return tfm;
85}
86#endif
87//EXPORT_SYMBOL_GPL(crypto_alloc_tfm);
88//EXPORT_SYMBOL_GPL(crypto_free_tfm);
89
90
diff --git a/drivers/staging/rtl8192su/ieee80211/digest.c b/drivers/staging/rtl8192su/ieee80211/digest.c
new file mode 100644
index 00000000000..1a95f2d3783
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/digest.c
@@ -0,0 +1,108 @@
1/*
2 * Cryptographic API.
3 *
4 * Digest operations.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14//#include <linux/crypto.h>
15#include "rtl_crypto.h"
16#include <linux/mm.h>
17#include <linux/errno.h>
18#include <linux/highmem.h>
19#include <asm/scatterlist.h>
20#include "internal.h"
21
22static void init(struct crypto_tfm *tfm)
23{
24 tfm->__crt_alg->cra_digest.dia_init(crypto_tfm_ctx(tfm));
25}
26
27static void update(struct crypto_tfm *tfm,
28 struct scatterlist *sg, unsigned int nsg)
29{
30 unsigned int i;
31
32 for (i = 0; i < nsg; i++) {
33
34 struct page *pg = sg[i].page;
35 unsigned int offset = sg[i].offset;
36 unsigned int l = sg[i].length;
37
38 do {
39 unsigned int bytes_from_page = min(l, ((unsigned int)
40 (PAGE_SIZE)) -
41 offset);
42 char *p = crypto_kmap(pg, 0) + offset;
43
44 tfm->__crt_alg->cra_digest.dia_update
45 (crypto_tfm_ctx(tfm), p,
46 bytes_from_page);
47 crypto_kunmap(p, 0);
48 crypto_yield(tfm);
49 offset = 0;
50 pg++;
51 l -= bytes_from_page;
52 } while (l > 0);
53 }
54}
55
56static void final(struct crypto_tfm *tfm, u8 *out)
57{
58 tfm->__crt_alg->cra_digest.dia_final(crypto_tfm_ctx(tfm), out);
59}
60
61static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
62{
63 u32 flags;
64 if (tfm->__crt_alg->cra_digest.dia_setkey == NULL)
65 return -ENOSYS;
66 return tfm->__crt_alg->cra_digest.dia_setkey(crypto_tfm_ctx(tfm),
67 key, keylen, &flags);
68}
69
70static void digest(struct crypto_tfm *tfm,
71 struct scatterlist *sg, unsigned int nsg, u8 *out)
72{
73 unsigned int i;
74
75 tfm->crt_digest.dit_init(tfm);
76
77 for (i = 0; i < nsg; i++) {
78 char *p = crypto_kmap(sg[i].page, 0) + sg[i].offset;
79 tfm->__crt_alg->cra_digest.dia_update(crypto_tfm_ctx(tfm),
80 p, sg[i].length);
81 crypto_kunmap(p, 0);
82 crypto_yield(tfm);
83 }
84 crypto_digest_final(tfm, out);
85}
86
87int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags)
88{
89 return flags ? -EINVAL : 0;
90}
91
92int crypto_init_digest_ops(struct crypto_tfm *tfm)
93{
94 struct digest_tfm *ops = &tfm->crt_digest;
95
96 ops->dit_init = init;
97 ops->dit_update = update;
98 ops->dit_final = final;
99 ops->dit_digest = digest;
100 ops->dit_setkey = setkey;
101
102 return crypto_alloc_hmac_block(tfm);
103}
104
105void crypto_exit_digest_ops(struct crypto_tfm *tfm)
106{
107 crypto_free_hmac_block(tfm);
108}
diff --git a/drivers/staging/rtl8192su/ieee80211/dot11d.c b/drivers/staging/rtl8192su/ieee80211/dot11d.c
new file mode 100644
index 00000000000..e5f2dedc437
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/dot11d.c
@@ -0,0 +1,239 @@
1#ifdef ENABLE_DOT11D
2//-----------------------------------------------------------------------------
3// File:
4// Dot11d.c
5//
6// Description:
7// Implement 802.11d.
8//
9//-----------------------------------------------------------------------------
10
11#include "dot11d.h"
12
13void
14Dot11d_Init(struct ieee80211_device *ieee)
15{
16 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee);
17
18 pDot11dInfo->bEnabled = 0;
19
20 pDot11dInfo->State = DOT11D_STATE_NONE;
21 pDot11dInfo->CountryIeLen = 0;
22 memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
23 memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
24 RESET_CIE_WATCHDOG(ieee);
25
26 printk("Dot11d_Init()\n");
27}
28
29//
30// Description:
31// Reset to the state as we are just entering a regulatory domain.
32//
33void
34Dot11d_Reset(struct ieee80211_device *ieee)
35{
36 u32 i;
37 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee);
38#if 0
39 if(!pDot11dInfo->bEnabled)
40 return;
41#endif
42 // Clear old channel map
43 memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
44 memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
45 // Set new channel map
46 for (i=1; i<=11; i++) {
47 (pDot11dInfo->channel_map)[i] = 1;
48 }
49 for (i=12; i<=14; i++) {
50 (pDot11dInfo->channel_map)[i] = 2;
51 }
52
53 pDot11dInfo->State = DOT11D_STATE_NONE;
54 pDot11dInfo->CountryIeLen = 0;
55 RESET_CIE_WATCHDOG(ieee);
56
57 //printk("Dot11d_Reset()\n");
58}
59
60//
61// Description:
62// Update country IE from Beacon or Probe Resopnse
63// and configure PHY for operation in the regulatory domain.
64//
65// TODO:
66// Configure Tx power.
67//
68// Assumption:
69// 1. IS_DOT11D_ENABLE() is TRUE.
70// 2. Input IE is an valid one.
71//
72void
73Dot11d_UpdateCountryIe(
74 struct ieee80211_device *dev,
75 u8 * pTaddr,
76 u16 CoutryIeLen,
77 u8 * pCoutryIe
78 )
79{
80 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
81 u8 i, j, NumTriples, MaxChnlNum;
82 PCHNL_TXPOWER_TRIPLE pTriple;
83
84 memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
85 memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
86 MaxChnlNum = 0;
87 NumTriples = (CoutryIeLen - 3) / 3; // skip 3-byte country string.
88 pTriple = (PCHNL_TXPOWER_TRIPLE)(pCoutryIe + 3);
89 for(i = 0; i < NumTriples; i++)
90 {
91 if(MaxChnlNum >= pTriple->FirstChnl)
92 { // It is not in a monotonically increasing order, so stop processing.
93 printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........1\n");
94 return;
95 }
96 if(MAX_CHANNEL_NUMBER < (pTriple->FirstChnl + pTriple->NumChnls))
97 { // It is not a valid set of channel id, so stop processing.
98 printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........2\n");
99 return;
100 }
101
102 for(j = 0 ; j < pTriple->NumChnls; j++)
103 {
104 pDot11dInfo->channel_map[pTriple->FirstChnl + j] = 1;
105 pDot11dInfo->MaxTxPwrDbmList[pTriple->FirstChnl + j] = pTriple->MaxTxPowerInDbm;
106 MaxChnlNum = pTriple->FirstChnl + j;
107 }
108
109 pTriple = (PCHNL_TXPOWER_TRIPLE)((u8*)pTriple + 3);
110 }
111#if 1
112 //printk("Dot11d_UpdateCountryIe(): Channel List:\n");
113 printk("Channel List:");
114 for(i=1; i<= MAX_CHANNEL_NUMBER; i++)
115 if(pDot11dInfo->channel_map[i] > 0)
116 printk(" %d", i);
117 printk("\n");
118#endif
119
120 UPDATE_CIE_SRC(dev, pTaddr);
121
122 pDot11dInfo->CountryIeLen = CoutryIeLen;
123 memcpy(pDot11dInfo->CountryIeBuf, pCoutryIe,CoutryIeLen);
124 pDot11dInfo->State = DOT11D_STATE_LEARNED;
125}
126
127
128u8
129DOT11D_GetMaxTxPwrInDbm(
130 struct ieee80211_device *dev,
131 u8 Channel
132 )
133{
134 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
135 u8 MaxTxPwrInDbm = 255;
136
137 if(MAX_CHANNEL_NUMBER < Channel)
138 {
139 printk("DOT11D_GetMaxTxPwrInDbm(): Invalid Channel\n");
140 return MaxTxPwrInDbm;
141 }
142 if(pDot11dInfo->channel_map[Channel])
143 {
144 MaxTxPwrInDbm = pDot11dInfo->MaxTxPwrDbmList[Channel];
145 }
146
147 return MaxTxPwrInDbm;
148}
149
150
151void
152DOT11D_ScanComplete(
153 struct ieee80211_device * dev
154 )
155{
156 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
157
158 switch(pDot11dInfo->State)
159 {
160 case DOT11D_STATE_LEARNED:
161 pDot11dInfo->State = DOT11D_STATE_DONE;
162 break;
163
164 case DOT11D_STATE_DONE:
165 if( GET_CIE_WATCHDOG(dev) == 0 )
166 { // Reset country IE if previous one is gone.
167 Dot11d_Reset(dev);
168 }
169 break;
170 case DOT11D_STATE_NONE:
171 break;
172 }
173}
174
175int IsLegalChannel(
176 struct ieee80211_device * dev,
177 u8 channel
178)
179{
180 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
181
182 if(MAX_CHANNEL_NUMBER < channel)
183 {
184 printk("IsLegalChannel(): Invalid Channel\n");
185 return 0;
186 }
187 if(pDot11dInfo->channel_map[channel] > 0)
188 return 1;
189 return 0;
190}
191
192int ToLegalChannel(
193 struct ieee80211_device * dev,
194 u8 channel
195)
196{
197 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
198 u8 default_chn = 0;
199 u32 i = 0;
200
201 for (i=1; i<= MAX_CHANNEL_NUMBER; i++)
202 {
203 if(pDot11dInfo->channel_map[i] > 0)
204 {
205 default_chn = i;
206 break;
207 }
208 }
209
210 if(MAX_CHANNEL_NUMBER < channel)
211 {
212 printk("IsLegalChannel(): Invalid Channel\n");
213 return default_chn;
214 }
215
216 if(pDot11dInfo->channel_map[channel] > 0)
217 return channel;
218
219 return default_chn;
220}
221#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
222EXPORT_SYMBOL(Dot11d_Init);
223EXPORT_SYMBOL(Dot11d_Reset);
224EXPORT_SYMBOL(Dot11d_UpdateCountryIe);
225EXPORT_SYMBOL(DOT11D_GetMaxTxPwrInDbm);
226EXPORT_SYMBOL(DOT11D_ScanComplete);
227EXPORT_SYMBOL(IsLegalChannel);
228EXPORT_SYMBOL(ToLegalChannel);
229#else
230EXPORT_SYMBOL_NOVERS(Dot11d_Init);
231EXPORT_SYMBOL_NOVERS(Dot11d_Reset);
232EXPORT_SYMBOL_NOVERS(Dot11d_UpdateCountryIe);
233EXPORT_SYMBOL_NOVERS(DOT11D_GetMaxTxPwrInDbm);
234EXPORT_SYMBOL_NOVERS(DOT11D_ScanComplete);
235EXPORT_SYMBOL_NOVERS(IsLegalChannel);
236EXPORT_SYMBOL_NOVERS(ToLegalChannel);
237#endif
238
239#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/dot11d.h b/drivers/staging/rtl8192su/ieee80211/dot11d.h
new file mode 100644
index 00000000000..15b7a4ba37b
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/dot11d.h
@@ -0,0 +1,102 @@
1#ifndef __INC_DOT11D_H
2#define __INC_DOT11D_H
3
4#ifdef ENABLE_DOT11D
5#include "ieee80211.h"
6
7//#define ENABLE_DOT11D
8
9//#define DOT11D_MAX_CHNL_NUM 83
10
11typedef struct _CHNL_TXPOWER_TRIPLE {
12 u8 FirstChnl;
13 u8 NumChnls;
14 u8 MaxTxPowerInDbm;
15}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE;
16
17typedef enum _DOT11D_STATE {
18 DOT11D_STATE_NONE = 0,
19 DOT11D_STATE_LEARNED,
20 DOT11D_STATE_DONE,
21}DOT11D_STATE;
22
23typedef struct _RT_DOT11D_INFO {
24 //DECLARE_RT_OBJECT(RT_DOT11D_INFO);
25
26 bool bEnabled; // dot11MultiDomainCapabilityEnabled
27
28 u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element.
29 u8 CountryIeBuf[MAX_IE_LEN];
30 u8 CountryIeSrcAddr[6]; // Source AP of the country IE.
31 u8 CountryIeWatchdog;
32
33 u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan)
34 //u8 ChnlListLen; // #Bytes valid in ChnlList[].
35 //u8 ChnlList[DOT11D_MAX_CHNL_NUM];
36 u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1];
37
38 DOT11D_STATE State;
39}RT_DOT11D_INFO, *PRT_DOT11D_INFO;
40#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
41#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
42#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo))
43
44#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled
45#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0)
46
47#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
48#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
49
50#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \
51 (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \
52 FALSE : \
53 (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length)))
54
55#define CIE_WATCHDOG_TH 1
56#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog
57#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0
58#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev)
59
60#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)
61
62
63void
64Dot11d_Init(
65 struct ieee80211_device *dev
66 );
67
68void
69Dot11d_Reset(
70 struct ieee80211_device *dev
71 );
72
73void
74Dot11d_UpdateCountryIe(
75 struct ieee80211_device *dev,
76 u8 * pTaddr,
77 u16 CoutryIeLen,
78 u8 * pCoutryIe
79 );
80
81u8
82DOT11D_GetMaxTxPwrInDbm(
83 struct ieee80211_device *dev,
84 u8 Channel
85 );
86
87void
88DOT11D_ScanComplete(
89 struct ieee80211_device * dev
90 );
91
92int IsLegalChannel(
93 struct ieee80211_device * dev,
94 u8 channel
95);
96
97int ToLegalChannel(
98 struct ieee80211_device * dev,
99 u8 channel
100);
101#endif //ENABLE_DOT11D
102#endif // #ifndef __INC_DOT11D_H
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211.h b/drivers/staging/rtl8192su/ieee80211/ieee80211.h
new file mode 100644
index 00000000000..720bfcbfadc
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211.h
@@ -0,0 +1,2901 @@
1/*
2 * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11
3 * remains copyright by the original authors
4 *
5 * Portions of the merged code are based on Host AP (software wireless
6 * LAN access point) driver for Intersil Prism2/2.5/3.
7 *
8 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
9 * <jkmaline@cc.hut.fi>
10 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
11 *
12 * Adaption to a generic IEEE 802.11 stack by James Ketrenos
13 * <jketreno@linux.intel.com>
14 * Copyright (c) 2004, Intel Corporation
15 *
16 * Modified for Realtek's wi-fi cards by Andrea Merello
17 * <andreamrl@tiscali.it>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation. See README and COPYING for
22 * more details.
23 */
24#ifndef IEEE80211_H
25#define IEEE80211_H
26#include <linux/if_ether.h> /* ETH_ALEN */
27#include <linux/kernel.h> /* ARRAY_SIZE */
28#include <linux/version.h>
29#include <linux/module.h>
30#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
31#include <linux/jiffies.h>
32#else
33#include <linux/jffs.h>
34#include <linux/tqueue.h>
35#endif
36#include <linux/timer.h>
37#include <linux/sched.h>
38
39#include <linux/delay.h>
40#include <linux/wireless.h>
41
42#include "rtl819x_HT.h"
43#include "rtl819x_BA.h"
44#include "rtl819x_TS.h"
45
46#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
47#ifndef bool
48typedef enum{false = 0, true} bool;
49#endif
50#endif
51
52#ifndef IW_MODE_MONITOR
53#define IW_MODE_MONITOR 6
54#endif
55
56#ifndef IWEVCUSTOM
57#define IWEVCUSTOM 0x8c02
58#endif
59
60#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
61#ifndef __bitwise
62#define __bitwise __attribute__((bitwise))
63#endif
64typedef __u16 __le16;
65#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27))
66struct iw_spy_data{
67 /* --- Standard spy support --- */
68 int spy_number;
69 u_char spy_address[IW_MAX_SPY][ETH_ALEN];
70 struct iw_quality spy_stat[IW_MAX_SPY];
71 /* --- Enhanced spy support (event) */
72 struct iw_quality spy_thr_low; /* Low threshold */
73 struct iw_quality spy_thr_high; /* High threshold */
74 u_char spy_thr_under[IW_MAX_SPY];
75};
76#endif
77#endif
78
79#ifndef container_of
80/**
81 * container_of - cast a member of a structure out to the containing structure
82 *
83 * @ptr: the pointer to the member.
84 * @type: the type of the container struct this is embedded in.
85 * @member: the name of the member within the struct.
86 *
87 */
88#define container_of(ptr, type, member) ({ \
89 const typeof( ((type *)0)->member ) *__mptr = (ptr); \
90 (type *)( (char *)__mptr - offsetof(type,member) );})
91#endif
92
93#define KEY_TYPE_NA 0x0
94#define KEY_TYPE_WEP40 0x1
95#define KEY_TYPE_TKIP 0x2
96#define KEY_TYPE_CCMP 0x4
97#define KEY_TYPE_WEP104 0x5
98
99/* added for rtl819x tx procedure */
100#define MAX_QUEUE_SIZE 0x10
101
102//
103// 8190 queue mapping
104//
105#define BK_QUEUE 0
106#define BE_QUEUE 1
107#define VI_QUEUE 2
108#define VO_QUEUE 3
109#define HCCA_QUEUE 4
110#define TXCMD_QUEUE 5
111#define MGNT_QUEUE 6
112#define HIGH_QUEUE 7
113#define BEACON_QUEUE 8
114
115#define LOW_QUEUE BE_QUEUE
116#define NORMAL_QUEUE MGNT_QUEUE
117
118//added by amy for ps
119#define SWRF_TIMEOUT 50
120
121//added by amy for LEAP related
122#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0.
123#define SUPPORT_CKIP_MIC 0x08 // bit3
124#define SUPPORT_CKIP_PK 0x10 // bit4
125//added by amy for ps
126// RF Off Level for IPS or HW/SW radio off
127#define RT_RF_OFF_LEVL_ASPM BIT0 // PCI ASPM
128#define RT_RF_OFF_LEVL_CLK_REQ BIT1 // PCI clock request
129#define RT_RF_OFF_LEVL_PCI_D3 BIT2 // PCI D3 mode
130#define RT_RF_OFF_LEVL_HALT_NIC BIT3 // NIC halt, re-initialize hw parameters
131#define RT_RF_OFF_LEVL_FREE_FW BIT4 // FW free, re-download the FW
132#define RT_RF_OFF_LEVL_FW_32K BIT5 // FW in 32k
133#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6 // Always enable ASPM and Clock Req in initialization.
134#define RT_RF_LPS_DISALBE_2R BIT30 // When LPS is on, disable 2R if no packet is received or transmittd.
135#define RT_RF_LPS_LEVEL_ASPM BIT31 // LPS with ASPM
136#define RT_IN_PS_LEVEL(pPSC, _PS_FLAG) ((pPSC->CurPsLevel & _PS_FLAG) ? true : false)
137#define RT_CLEAR_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel &= (~(_PS_FLAG)))
138#define RT_SET_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel->CurPsLevel |= _PS_FLAG)
139/* defined for skb cb field */
140/* At most 28 byte */
141typedef struct cb_desc {
142 /* Tx Desc Related flags (8-9) */
143 u8 bLastIniPkt:1;
144 u8 bCmdOrInit:1;
145 u8 bFirstSeg:1;
146 u8 bLastSeg:1;
147 u8 bEncrypt:1;
148 u8 bTxDisableRateFallBack:1;
149 u8 bTxUseDriverAssingedRate:1;
150 u8 bHwSec:1; //indicate whether use Hw security. WB
151
152 u8 reserved1;
153
154 /* Tx Firmware Relaged flags (10-11)*/
155 u8 bCTSEnable:1;
156 u8 bRTSEnable:1;
157 u8 bUseShortGI:1;
158 u8 bUseShortPreamble:1;
159 u8 bTxEnableFwCalcDur:1;
160 u8 bAMPDUEnable:1;
161 u8 bRTSSTBC:1;
162 u8 RTSSC:1;
163
164 u8 bRTSBW:1;
165 u8 bPacketBW:1;
166 u8 bRTSUseShortPreamble:1;
167 u8 bRTSUseShortGI:1;
168 u8 bMulticast:1;
169 u8 bBroadcast:1;
170 //u8 reserved2:2;
171 u8 drv_agg_enable:1;
172 u8 reserved2:1;
173
174 /* Tx Desc related element(12-19) */
175 u8 rata_index;
176 u8 queue_index;
177 //u8 reserved3;
178 //u8 reserved4;
179 u16 txbuf_size;
180 //u8 reserved5;
181 u8 RATRIndex;
182 u8 reserved6;
183 u8 reserved7;
184 u8 reserved8;
185
186 /* Tx firmware related element(20-27) */
187 u8 data_rate;
188 u8 rts_rate;
189 u8 ampdu_factor;
190 u8 ampdu_density;
191 //u8 reserved9;
192 //u8 reserved10;
193 //u8 reserved11;
194 u8 DrvAggrNum;
195 u16 pkt_size;
196 u8 reserved12;
197}cb_desc, *pcb_desc;
198
199/*--------------------------Define -------------------------------------------*/
200#define MGN_1M 0x02
201#define MGN_2M 0x04
202#define MGN_5_5M 0x0b
203#define MGN_11M 0x16
204
205#define MGN_6M 0x0c
206#define MGN_9M 0x12
207#define MGN_12M 0x18
208#define MGN_18M 0x24
209#define MGN_24M 0x30
210#define MGN_36M 0x48
211#define MGN_48M 0x60
212#define MGN_54M 0x6c
213
214#define MGN_MCS0 0x80
215#define MGN_MCS1 0x81
216#define MGN_MCS2 0x82
217#define MGN_MCS3 0x83
218#define MGN_MCS4 0x84
219#define MGN_MCS5 0x85
220#define MGN_MCS6 0x86
221#define MGN_MCS7 0x87
222#define MGN_MCS8 0x88
223#define MGN_MCS9 0x89
224#define MGN_MCS10 0x8a
225#define MGN_MCS11 0x8b
226#define MGN_MCS12 0x8c
227#define MGN_MCS13 0x8d
228#define MGN_MCS14 0x8e
229#define MGN_MCS15 0x8f
230#define MGN_MCS0_SG 0x90
231#define MGN_MCS1_SG 0x91
232#define MGN_MCS2_SG 0x92
233#define MGN_MCS3_SG 0x93
234#define MGN_MCS4_SG 0x94
235#define MGN_MCS5_SG 0x95
236#define MGN_MCS6_SG 0x96
237#define MGN_MCS7_SG 0x97
238#define MGN_MCS8_SG 0x98
239#define MGN_MCS9_SG 0x99
240#define MGN_MCS10_SG 0x9a
241#define MGN_MCS11_SG 0x9b
242#define MGN_MCS12_SG 0x9c
243#define MGN_MCS13_SG 0x9d
244#define MGN_MCS14_SG 0x9e
245#define MGN_MCS15_SG 0x9f
246
247
248//----------------------------------------------------------------------------
249// 802.11 Management frame Reason Code field
250//----------------------------------------------------------------------------
251enum _ReasonCode{
252 unspec_reason = 0x1,
253 auth_not_valid = 0x2,
254 deauth_lv_ss = 0x3,
255 inactivity = 0x4,
256 ap_overload = 0x5,
257 class2_err = 0x6,
258 class3_err = 0x7,
259 disas_lv_ss = 0x8,
260 asoc_not_auth = 0x9,
261
262 //----MIC_CHECK
263 mic_failure = 0xe,
264 //----END MIC_CHECK
265
266 // Reason code defined in 802.11i D10.0 p.28.
267 invalid_IE = 0x0d,
268 four_way_tmout = 0x0f,
269 two_way_tmout = 0x10,
270 IE_dismatch = 0x11,
271 invalid_Gcipher = 0x12,
272 invalid_Pcipher = 0x13,
273 invalid_AKMP = 0x14,
274 unsup_RSNIEver = 0x15,
275 invalid_RSNIE = 0x16,
276 auth_802_1x_fail= 0x17,
277 ciper_reject = 0x18,
278
279 // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15.
280 QoS_unspec = 0x20, // 32
281 QAP_bandwidth = 0x21, // 33
282 poor_condition = 0x22, // 34
283 no_facility = 0x23, // 35
284 // Where is 36???
285 req_declined = 0x25, // 37
286 invalid_param = 0x26, // 38
287 req_not_honored= 0x27, // 39
288 TS_not_created = 0x2F, // 47
289 DL_not_allowed = 0x30, // 48
290 dest_not_exist = 0x31, // 49
291 dest_not_QSTA = 0x32, // 50
292};
293
294
295
296#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10)
297
298#define MGMT_QUEUE_NUM 5
299
300#define IEEE_CMD_SET_WPA_PARAM 1
301#define IEEE_CMD_SET_WPA_IE 2
302#define IEEE_CMD_SET_ENCRYPTION 3
303#define IEEE_CMD_MLME 4
304
305#define IEEE_PARAM_WPA_ENABLED 1
306#define IEEE_PARAM_TKIP_COUNTERMEASURES 2
307#define IEEE_PARAM_DROP_UNENCRYPTED 3
308#define IEEE_PARAM_PRIVACY_INVOKED 4
309#define IEEE_PARAM_AUTH_ALGS 5
310#define IEEE_PARAM_IEEE_802_1X 6
311//It should consistent with the driver_XXX.c
312// David, 2006.9.26
313#define IEEE_PARAM_WPAX_SELECT 7
314//Added for notify the encryption type selection
315// David, 2006.9.26
316#define IEEE_PROTO_WPA 1
317#define IEEE_PROTO_RSN 2
318//Added for notify the encryption type selection
319// David, 2006.9.26
320#define IEEE_WPAX_USEGROUP 0
321#define IEEE_WPAX_WEP40 1
322#define IEEE_WPAX_TKIP 2
323#define IEEE_WPAX_WRAP 3
324#define IEEE_WPAX_CCMP 4
325#define IEEE_WPAX_WEP104 5
326
327#define IEEE_KEY_MGMT_IEEE8021X 1
328#define IEEE_KEY_MGMT_PSK 2
329
330#define IEEE_MLME_STA_DEAUTH 1
331#define IEEE_MLME_STA_DISASSOC 2
332
333
334#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2
335#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3
336#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4
337#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5
338#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6
339#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7
340
341
342#define IEEE_CRYPT_ALG_NAME_LEN 16
343
344#define MAX_IE_LEN 0xff
345
346// added for kernel conflict
347#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl
348#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl
349#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl
350#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl
351#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl
352#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl
353
354#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl
355
356#define ieee80211_tkip_null ieee80211_tkip_null_rsl
357
358#define ieee80211_wep_null ieee80211_wep_null_rsl
359
360#define free_ieee80211 free_ieee80211_rsl
361#define alloc_ieee80211 alloc_ieee80211_rsl
362
363#define ieee80211_rx ieee80211_rx_rsl
364#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl
365
366#define ieee80211_get_beacon ieee80211_get_beacon_rsl
367#define ieee80211_wake_queue ieee80211_wake_queue_rsl
368#define ieee80211_stop_queue ieee80211_stop_queue_rsl
369#define ieee80211_reset_queue ieee80211_reset_queue_rsl
370#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl
371#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl
372#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl
373#define ieee80211_is_54g ieee80211_is_54g_rsl
374#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl
375#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl
376#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl
377#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl
378#define notify_wx_assoc_event notify_wx_assoc_event_rsl
379#define SendDisassociation SendDisassociation_rsl
380#define ieee80211_disassociate ieee80211_disassociate_rsl
381#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl
382#define ieee80211_stop_scan ieee80211_stop_scan_rsl
383#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl
384#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl
385#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl
386
387#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl
388#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl
389#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl
390#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl
391#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl
392#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl
393#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl
394#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl
395#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl
396#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl
397#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl
398#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl
399#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl
400#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl
401#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl
402#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl
403#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl
404#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl
405
406#define ieee80211_txb_free ieee80211_txb_free_rsl
407
408#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl
409#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl
410#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl
411#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl
412#if WIRELESS_EXT >= 18
413#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl
414#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl
415#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl
416#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl
417#endif
418
419
420typedef struct ieee_param {
421 u32 cmd;
422 u8 sta_addr[ETH_ALEN];
423 union {
424 struct {
425 u8 name;
426 u32 value;
427 } wpa_param;
428 struct {
429 u32 len;
430 u8 reserved[32];
431 u8 data[0];
432 } wpa_ie;
433 struct{
434 int command;
435 int reason_code;
436 } mlme;
437 struct {
438 u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
439 u8 set_tx;
440 u32 err;
441 u8 idx;
442 u8 seq[8]; /* sequence counter (set: RX, get: TX) */
443 u16 key_len;
444 u8 key[0];
445 } crypt;
446 } u;
447}ieee_param;
448
449
450#if WIRELESS_EXT < 17
451#define IW_QUAL_QUAL_INVALID 0x10
452#define IW_QUAL_LEVEL_INVALID 0x20
453#define IW_QUAL_NOISE_INVALID 0x40
454#define IW_QUAL_QUAL_UPDATED 0x1
455#define IW_QUAL_LEVEL_UPDATED 0x2
456#define IW_QUAL_NOISE_UPDATED 0x4
457#endif
458
459#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
460static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data)
461{
462 task->routine = func;
463 task->data = data;
464 //task->next = NULL;
465 INIT_LIST_HEAD(&task->list);
466 task->sync = 0;
467}
468#endif
469
470// linux under 2.6.9 release may not support it, so modify it for common use
471#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
472//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ)
473#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
474static inline unsigned long msleep_interruptible_rsl(unsigned int msecs)
475{
476 unsigned long timeout = MSECS(msecs) + 1;
477
478 while (timeout) {
479 set_current_state(TASK_INTERRUPTIBLE);
480 timeout = schedule_timeout(timeout);
481 }
482 return timeout;
483}
484#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31))
485static inline void msleep(unsigned int msecs)
486{
487 unsigned long timeout = MSECS(msecs) + 1;
488
489 while (timeout) {
490 set_current_state(TASK_UNINTERRUPTIBLE);
491 timeout = schedule_timeout(timeout);
492 }
493}
494#endif
495#else
496#define MSECS(t) msecs_to_jiffies(t)
497#define msleep_interruptible_rsl msleep_interruptible
498#endif
499
500#define IEEE80211_DATA_LEN 2304
501/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
502 6.2.1.1.2.
503
504 The figure in section 7.1.2 suggests a body size of up to 2312
505 bytes is allowed, which is a bit confusing, I suspect this
506 represents the 2304 bytes of real data, plus a possible 8 bytes of
507 WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
508#define IEEE80211_1ADDR_LEN 10
509#define IEEE80211_2ADDR_LEN 16
510#define IEEE80211_3ADDR_LEN 24
511#define IEEE80211_4ADDR_LEN 30
512#define IEEE80211_FCS_LEN 4
513#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
514#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
515#define IEEE80211_MGMT_HDR_LEN 24
516#define IEEE80211_DATA_HDR3_LEN 24
517#define IEEE80211_DATA_HDR4_LEN 30
518
519#define MIN_FRAG_THRESHOLD 256U
520#define MAX_FRAG_THRESHOLD 2346U
521
522
523/* Frame control field constants */
524#define IEEE80211_FCTL_VERS 0x0003
525#define IEEE80211_FCTL_FTYPE 0x000c
526#define IEEE80211_FCTL_STYPE 0x00f0
527#define IEEE80211_FCTL_FRAMETYPE 0x00fc
528#define IEEE80211_FCTL_TODS 0x0100
529#define IEEE80211_FCTL_FROMDS 0x0200
530#define IEEE80211_FCTL_DSTODS 0x0300 //added by david
531#define IEEE80211_FCTL_MOREFRAGS 0x0400
532#define IEEE80211_FCTL_RETRY 0x0800
533#define IEEE80211_FCTL_PM 0x1000
534#define IEEE80211_FCTL_MOREDATA 0x2000
535#define IEEE80211_FCTL_WEP 0x4000
536#define IEEE80211_FCTL_ORDER 0x8000
537
538#define IEEE80211_FTYPE_MGMT 0x0000
539#define IEEE80211_FTYPE_CTL 0x0004
540#define IEEE80211_FTYPE_DATA 0x0008
541
542/* management */
543#define IEEE80211_STYPE_ASSOC_REQ 0x0000
544#define IEEE80211_STYPE_ASSOC_RESP 0x0010
545#define IEEE80211_STYPE_REASSOC_REQ 0x0020
546#define IEEE80211_STYPE_REASSOC_RESP 0x0030
547#define IEEE80211_STYPE_PROBE_REQ 0x0040
548#define IEEE80211_STYPE_PROBE_RESP 0x0050
549#define IEEE80211_STYPE_BEACON 0x0080
550#define IEEE80211_STYPE_ATIM 0x0090
551#define IEEE80211_STYPE_DISASSOC 0x00A0
552#define IEEE80211_STYPE_AUTH 0x00B0
553#define IEEE80211_STYPE_DEAUTH 0x00C0
554#define IEEE80211_STYPE_MANAGE_ACT 0x00D0
555
556/* control */
557#define IEEE80211_STYPE_PSPOLL 0x00A0
558#define IEEE80211_STYPE_RTS 0x00B0
559#define IEEE80211_STYPE_CTS 0x00C0
560#define IEEE80211_STYPE_ACK 0x00D0
561#define IEEE80211_STYPE_CFEND 0x00E0
562#define IEEE80211_STYPE_CFENDACK 0x00F0
563#define IEEE80211_STYPE_BLOCKACK 0x0094
564
565/* data */
566#define IEEE80211_STYPE_DATA 0x0000
567#define IEEE80211_STYPE_DATA_CFACK 0x0010
568#define IEEE80211_STYPE_DATA_CFPOLL 0x0020
569#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030
570#define IEEE80211_STYPE_NULLFUNC 0x0040
571#define IEEE80211_STYPE_CFACK 0x0050
572#define IEEE80211_STYPE_CFPOLL 0x0060
573#define IEEE80211_STYPE_CFACKPOLL 0x0070
574#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2
575#define IEEE80211_STYPE_QOS_NULL 0x00C0
576
577#define IEEE80211_SCTL_FRAG 0x000F
578#define IEEE80211_SCTL_SEQ 0xFFF0
579
580/* QOS control */
581#define IEEE80211_QCTL_TID 0x000F
582
583#define FC_QOS_BIT BIT7
584#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false )
585#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) )
586//added by wb. Is this right?
587#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA))
588#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER)
589#define SN_LESS(a, b) (((a-b)&0x800)!=0)
590#define SN_EQUAL(a, b) (a == b)
591#define MAX_DEV_ADDR_SIZE 8
592typedef enum _ACT_CATEGORY{
593 ACT_CAT_QOS = 1,
594 ACT_CAT_DLS = 2,
595 ACT_CAT_BA = 3,
596 ACT_CAT_HT = 7,
597 ACT_CAT_WMM = 17,
598} ACT_CATEGORY, *PACT_CATEGORY;
599
600typedef enum _TS_ACTION{
601 ACT_ADDTSREQ = 0,
602 ACT_ADDTSRSP = 1,
603 ACT_DELTS = 2,
604 ACT_SCHEDULE = 3,
605} TS_ACTION, *PTS_ACTION;
606
607typedef enum _BA_ACTION{
608 ACT_ADDBAREQ = 0,
609 ACT_ADDBARSP = 1,
610 ACT_DELBA = 2,
611} BA_ACTION, *PBA_ACTION;
612
613typedef enum _InitialGainOpType{
614 IG_Backup=0,
615 IG_Restore,
616 IG_Max
617}InitialGainOpType;
618//added by amy for LED 090319
619//================================================================================
620// LED customization.
621//================================================================================
622typedef enum _LED_CTL_MODE{
623 LED_CTL_POWER_ON = 1,
624 LED_CTL_LINK = 2,
625 LED_CTL_NO_LINK = 3,
626 LED_CTL_TX = 4,
627 LED_CTL_RX = 5,
628 LED_CTL_SITE_SURVEY = 6,
629 LED_CTL_POWER_OFF = 7,
630 LED_CTL_START_TO_LINK = 8,
631 LED_CTL_START_WPS = 9,
632 LED_CTL_STOP_WPS = 10,
633 LED_CTL_START_WPS_BOTTON = 11, //added for runtop
634}LED_CTL_MODE;
635
636/* debug macros */
637#define CONFIG_IEEE80211_DEBUG
638#ifdef CONFIG_IEEE80211_DEBUG
639extern u32 ieee80211_debug_level;
640#define IEEE80211_DEBUG(level, fmt, args...) \
641do { if (ieee80211_debug_level & (level)) \
642 printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0)
643//wb added to debug out data buf
644//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
645#define IEEE80211_DEBUG_DATA(level, data, datalen) \
646 do{ if ((ieee80211_debug_level & (level)) == (level)) \
647 { \
648 int i; \
649 u8* pdata = (u8*) data; \
650 printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \
651 for(i=0; i<(int)(datalen); i++) \
652 { \
653 printk("%2x ", pdata[i]); \
654 if ((i+1)%16 == 0) printk("\n"); \
655 } \
656 printk("\n"); \
657 } \
658 } while (0)
659#else
660#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0)
661#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0)
662#endif /* CONFIG_IEEE80211_DEBUG */
663
664/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */
665
666#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
667#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
668
669/*
670 * To use the debug system;
671 *
672 * If you are defining a new debug classification, simply add it to the #define
673 * list here in the form of:
674 *
675 * #define IEEE80211_DL_xxxx VALUE
676 *
677 * shifting value to the left one bit from the previous entry. xxxx should be
678 * the name of the classification (for example, WEP)
679 *
680 * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your
681 * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want
682 * to send output to that classification.
683 *
684 * To add your debug level to the list of levels seen when you perform
685 *
686 * % cat /proc/net/ipw/debug_level
687 *
688 * you simply need to add your entry to the ipw_debug_levels array.
689 *
690 * If you do not see debug_level in /proc/net/ipw then you do not have
691 * CONFIG_IEEE80211_DEBUG defined in your kernel configuration
692 *
693 */
694
695#define IEEE80211_DL_INFO (1<<0)
696#define IEEE80211_DL_WX (1<<1)
697#define IEEE80211_DL_SCAN (1<<2)
698#define IEEE80211_DL_STATE (1<<3)
699#define IEEE80211_DL_MGMT (1<<4)
700#define IEEE80211_DL_FRAG (1<<5)
701#define IEEE80211_DL_EAP (1<<6)
702#define IEEE80211_DL_DROP (1<<7)
703
704#define IEEE80211_DL_TX (1<<8)
705#define IEEE80211_DL_RX (1<<9)
706
707#define IEEE80211_DL_HT (1<<10) //HT
708#define IEEE80211_DL_BA (1<<11) //ba
709#define IEEE80211_DL_TS (1<<12) //TS
710#define IEEE80211_DL_QOS (1<<13)
711#define IEEE80211_DL_REORDER (1<<14)
712#define IEEE80211_DL_IOT (1<<15)
713#define IEEE80211_DL_IPS (1<<16)
714#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen
715#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out.
716#define IEEE80211_DL_ERR (1<<31) //always open
717#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a)
718#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a)
719#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a)
720
721#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a)
722#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a)
723#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a)
724#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a)
725#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a)
726#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a)
727#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a)
728#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a)
729#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a)
730#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a)
731
732#ifdef CONFIG_IEEE80211_DEBUG
733/* Added by Annie, 2005-11-22. */
734#define MAX_STR_LEN 64
735/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/
736#define PRINTABLE(_ch) (_ch>'!' && _ch<'~')
737#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \
738 if((_Comp) & level) \
739 { \
740 int __i; \
741 u8 buffer[MAX_STR_LEN]; \
742 int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
743 memset(buffer, 0, MAX_STR_LEN); \
744 memcpy(buffer, (u8 *)_Ptr, length ); \
745 for( __i=0; __i<MAX_STR_LEN; __i++ ) \
746 { \
747 if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
748 } \
749 buffer[length] = '\0'; \
750 printk("Rtl819x: "); \
751 printk(_TitleString); \
752 printk(": %d, <%s>\n", _Len, buffer); \
753 }
754#else
755#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0)
756#endif
757
758#include <linux/netdevice.h>
759#include <linux/if_arp.h> /* ARPHRD_ETHER */
760
761#ifndef WIRELESS_SPY
762#define WIRELESS_SPY // enable iwspy support
763#endif
764#include <net/iw_handler.h> // new driver API
765
766#ifndef ETH_P_PAE
767#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
768#endif /* ETH_P_PAE */
769
770#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
771
772#ifndef ETH_P_80211_RAW
773#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
774#endif
775
776/* IEEE 802.11 defines */
777
778#define P80211_OUI_LEN 3
779
780struct ieee80211_snap_hdr {
781
782 u8 dsap; /* always 0xAA */
783 u8 ssap; /* always 0xAA */
784 u8 ctrl; /* always 0x03 */
785 u8 oui[P80211_OUI_LEN]; /* organizational universal id */
786
787} __attribute__ ((packed));
788
789#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
790
791#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
792#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
793#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
794
795#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE)
796#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG)
797#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
798
799/* Authentication algorithms */
800#define WLAN_AUTH_OPEN 0
801#define WLAN_AUTH_SHARED_KEY 1
802#define WLAN_AUTH_LEAP 2
803
804#define WLAN_AUTH_CHALLENGE_LEN 128
805
806#define WLAN_CAPABILITY_BSS (1<<0)
807#define WLAN_CAPABILITY_IBSS (1<<1)
808#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
809#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
810#define WLAN_CAPABILITY_PRIVACY (1<<4)
811#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
812#define WLAN_CAPABILITY_PBCC (1<<6)
813#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
814#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
815#define WLAN_CAPABILITY_QOS (1<<9)
816#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
817#define WLAN_CAPABILITY_DSSS_OFDM (1<<13)
818
819/* 802.11g ERP information element */
820#define WLAN_ERP_NON_ERP_PRESENT (1<<0)
821#define WLAN_ERP_USE_PROTECTION (1<<1)
822#define WLAN_ERP_BARKER_PREAMBLE (1<<2)
823
824/* Status codes */
825enum ieee80211_statuscode {
826 WLAN_STATUS_SUCCESS = 0,
827 WLAN_STATUS_UNSPECIFIED_FAILURE = 1,
828 WLAN_STATUS_CAPS_UNSUPPORTED = 10,
829 WLAN_STATUS_REASSOC_NO_ASSOC = 11,
830 WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,
831 WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,
832 WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,
833 WLAN_STATUS_CHALLENGE_FAIL = 15,
834 WLAN_STATUS_AUTH_TIMEOUT = 16,
835 WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,
836 WLAN_STATUS_ASSOC_DENIED_RATES = 18,
837 /* 802.11b */
838 WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,
839 WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,
840 WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,
841 /* 802.11h */
842 WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,
843 WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,
844 WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,
845 /* 802.11g */
846 WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,
847 WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,
848 /* 802.11i */
849 WLAN_STATUS_INVALID_IE = 40,
850 WLAN_STATUS_INVALID_GROUP_CIPHER = 41,
851 WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,
852 WLAN_STATUS_INVALID_AKMP = 43,
853 WLAN_STATUS_UNSUPP_RSN_VERSION = 44,
854 WLAN_STATUS_INVALID_RSN_IE_CAP = 45,
855 WLAN_STATUS_CIPHER_SUITE_REJECTED = 46,
856};
857
858/* Reason codes */
859enum ieee80211_reasoncode {
860 WLAN_REASON_UNSPECIFIED = 1,
861 WLAN_REASON_PREV_AUTH_NOT_VALID = 2,
862 WLAN_REASON_DEAUTH_LEAVING = 3,
863 WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,
864 WLAN_REASON_DISASSOC_AP_BUSY = 5,
865 WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,
866 WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,
867 WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,
868 WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,
869 /* 802.11h */
870 WLAN_REASON_DISASSOC_BAD_POWER = 10,
871 WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,
872 /* 802.11i */
873 WLAN_REASON_INVALID_IE = 13,
874 WLAN_REASON_MIC_FAILURE = 14,
875 WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
876 WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,
877 WLAN_REASON_IE_DIFFERENT = 17,
878 WLAN_REASON_INVALID_GROUP_CIPHER = 18,
879 WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,
880 WLAN_REASON_INVALID_AKMP = 20,
881 WLAN_REASON_UNSUPP_RSN_VERSION = 21,
882 WLAN_REASON_INVALID_RSN_IE_CAP = 22,
883 WLAN_REASON_IEEE8021X_FAILED = 23,
884 WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
885};
886
887#define IEEE80211_STATMASK_SIGNAL (1<<0)
888#define IEEE80211_STATMASK_RSSI (1<<1)
889#define IEEE80211_STATMASK_NOISE (1<<2)
890#define IEEE80211_STATMASK_RATE (1<<3)
891#define IEEE80211_STATMASK_WEMASK 0x7
892
893#define IEEE80211_CCK_MODULATION (1<<0)
894#define IEEE80211_OFDM_MODULATION (1<<1)
895
896#define IEEE80211_24GHZ_BAND (1<<0)
897#define IEEE80211_52GHZ_BAND (1<<1)
898
899#define IEEE80211_CCK_RATE_LEN 4
900#define IEEE80211_CCK_RATE_1MB 0x02
901#define IEEE80211_CCK_RATE_2MB 0x04
902#define IEEE80211_CCK_RATE_5MB 0x0B
903#define IEEE80211_CCK_RATE_11MB 0x16
904#define IEEE80211_OFDM_RATE_LEN 8
905#define IEEE80211_OFDM_RATE_6MB 0x0C
906#define IEEE80211_OFDM_RATE_9MB 0x12
907#define IEEE80211_OFDM_RATE_12MB 0x18
908#define IEEE80211_OFDM_RATE_18MB 0x24
909#define IEEE80211_OFDM_RATE_24MB 0x30
910#define IEEE80211_OFDM_RATE_36MB 0x48
911#define IEEE80211_OFDM_RATE_48MB 0x60
912#define IEEE80211_OFDM_RATE_54MB 0x6C
913#define IEEE80211_BASIC_RATE_MASK 0x80
914
915#define IEEE80211_CCK_RATE_1MB_MASK (1<<0)
916#define IEEE80211_CCK_RATE_2MB_MASK (1<<1)
917#define IEEE80211_CCK_RATE_5MB_MASK (1<<2)
918#define IEEE80211_CCK_RATE_11MB_MASK (1<<3)
919#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4)
920#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5)
921#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6)
922#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7)
923#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8)
924#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9)
925#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
926#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
927
928#define IEEE80211_CCK_RATES_MASK 0x0000000F
929#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
930 IEEE80211_CCK_RATE_2MB_MASK)
931#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \
932 IEEE80211_CCK_RATE_5MB_MASK | \
933 IEEE80211_CCK_RATE_11MB_MASK)
934
935#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
936#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
937 IEEE80211_OFDM_RATE_12MB_MASK | \
938 IEEE80211_OFDM_RATE_24MB_MASK)
939#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \
940 IEEE80211_OFDM_RATE_9MB_MASK | \
941 IEEE80211_OFDM_RATE_18MB_MASK | \
942 IEEE80211_OFDM_RATE_36MB_MASK | \
943 IEEE80211_OFDM_RATE_48MB_MASK | \
944 IEEE80211_OFDM_RATE_54MB_MASK)
945#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
946 IEEE80211_CCK_DEFAULT_RATES_MASK)
947
948#define IEEE80211_NUM_OFDM_RATES 8
949#define IEEE80211_NUM_CCK_RATES 4
950#define IEEE80211_OFDM_SHIFT_MASK_A 4
951
952
953/* this is stolen and modified from the madwifi driver*/
954#define IEEE80211_FC0_TYPE_MASK 0x0c
955#define IEEE80211_FC0_TYPE_DATA 0x08
956#define IEEE80211_FC0_SUBTYPE_MASK 0xB0
957#define IEEE80211_FC0_SUBTYPE_QOS 0x80
958
959#define IEEE80211_QOS_HAS_SEQ(fc) \
960 (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \
961 (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS))
962
963/* this is stolen from ipw2200 driver */
964#define IEEE_IBSS_MAC_HASH_SIZE 31
965struct ieee_ibss_seq {
966 u8 mac[ETH_ALEN];
967 u16 seq_num[17];
968 u16 frag_num[17];
969 unsigned long packet_time[17];
970 struct list_head list;
971};
972
973/* NOTE: This data is for statistical purposes; not all hardware provides this
974 * information for frames received. Not setting these will not cause
975 * any adverse affects. */
976struct ieee80211_rx_stats {
977#if 1
978 u32 mac_time[2];
979 s8 rssi;
980 u8 signal;
981 u8 noise;
982 u16 rate; /* in 100 kbps */
983 u8 received_channel;
984 u8 control;
985 u8 mask;
986 u8 freq;
987 u16 len;
988 u64 tsf;
989 u32 beacon_time;
990 u8 nic_type;
991 u16 Length;
992 // u8 DataRate; // In 0.5 Mbps
993 u8 SignalQuality; // in 0-100 index.
994 s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation.
995 s8 RxPower; // in dBm Translate from PWdB
996 u8 SignalStrength; // in 0-100 index.
997 u16 bHwError:1;
998 u16 bCRC:1;
999 u16 bICV:1;
1000 u16 bShortPreamble:1;
1001 u16 Antenna:1; //for rtl8185
1002 u16 Decrypted:1; //for rtl8185, rtl8187
1003 u16 Wakeup:1; //for rtl8185
1004 u16 Reserved0:1; //for rtl8185
1005 u8 AGC;
1006 u32 TimeStampLow;
1007 u32 TimeStampHigh;
1008 bool bShift;
1009 bool bIsQosData; // Added by Annie, 2005-12-22.
1010 u8 UserPriority;
1011
1012 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
1013 //1Attention Please!!!<11n or 8190 specific code should be put below this line>
1014 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
1015
1016 u8 RxDrvInfoSize;
1017 u8 RxBufShift;
1018 bool bIsAMPDU;
1019 bool bFirstMPDU;
1020 bool bContainHTC;
1021 bool RxIs40MHzPacket;
1022 u32 RxPWDBAll;
1023 u8 RxMIMOSignalStrength[4]; // in 0~100 index
1024 s8 RxMIMOSignalQuality[2];
1025 bool bPacketMatchBSSID;
1026 bool bIsCCK;
1027 bool bPacketToSelf;
1028 //added by amy
1029 u8* virtual_address;
1030 u16 packetlength; // Total packet length: Must equal to sum of all FragLength
1031 u16 fraglength; // FragLength should equal to PacketLength in non-fragment case
1032 u16 fragoffset; // Data offset for this fragment
1033 u16 ntotalfrag;
1034 bool bisrxaggrsubframe;
1035 bool bPacketBeacon; //cosa add for rssi
1036 bool bToSelfBA; //cosa add for rssi
1037 char cck_adc_pwdb[4]; //cosa add for rx path selection
1038 u16 Seq_Num;
1039 u8 nTotalAggPkt; // Number of aggregated packets.
1040#endif
1041
1042};
1043
1044/* IEEE 802.11 requires that STA supports concurrent reception of at least
1045 * three fragmented frames. This define can be increased to support more
1046 * concurrent frames, but it should be noted that each entry can consume about
1047 * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
1048#define IEEE80211_FRAG_CACHE_LEN 4
1049
1050struct ieee80211_frag_entry {
1051 unsigned long first_frag_time;
1052 unsigned int seq;
1053 unsigned int last_frag;
1054 struct sk_buff *skb;
1055 u8 src_addr[ETH_ALEN];
1056 u8 dst_addr[ETH_ALEN];
1057};
1058
1059struct ieee80211_stats {
1060 unsigned int tx_unicast_frames;
1061 unsigned int tx_multicast_frames;
1062 unsigned int tx_fragments;
1063 unsigned int tx_unicast_octets;
1064 unsigned int tx_multicast_octets;
1065 unsigned int tx_deferred_transmissions;
1066 unsigned int tx_single_retry_frames;
1067 unsigned int tx_multiple_retry_frames;
1068 unsigned int tx_retry_limit_exceeded;
1069 unsigned int tx_discards;
1070 unsigned int rx_unicast_frames;
1071 unsigned int rx_multicast_frames;
1072 unsigned int rx_fragments;
1073 unsigned int rx_unicast_octets;
1074 unsigned int rx_multicast_octets;
1075 unsigned int rx_fcs_errors;
1076 unsigned int rx_discards_no_buffer;
1077 unsigned int tx_discards_wrong_sa;
1078 unsigned int rx_discards_undecryptable;
1079 unsigned int rx_message_in_msg_fragments;
1080 unsigned int rx_message_in_bad_msg_fragments;
1081};
1082
1083struct ieee80211_device;
1084
1085#include "ieee80211_crypt.h"
1086
1087#define SEC_KEY_1 (1<<0)
1088#define SEC_KEY_2 (1<<1)
1089#define SEC_KEY_3 (1<<2)
1090#define SEC_KEY_4 (1<<3)
1091#define SEC_ACTIVE_KEY (1<<4)
1092#define SEC_AUTH_MODE (1<<5)
1093#define SEC_UNICAST_GROUP (1<<6)
1094#define SEC_LEVEL (1<<7)
1095#define SEC_ENABLED (1<<8)
1096#define SEC_ENCRYPT (1<<9)
1097
1098#define SEC_LEVEL_0 0 /* None */
1099#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */
1100#define SEC_LEVEL_2 2 /* Level 1 + TKIP */
1101#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
1102#define SEC_LEVEL_3 4 /* Level 2 + CCMP */
1103
1104#define SEC_ALG_NONE 0
1105#define SEC_ALG_WEP 1
1106#define SEC_ALG_TKIP 2
1107#define SEC_ALG_CCMP 3
1108
1109#define WEP_KEYS 4
1110#define WEP_KEY_LEN 13
1111#define SCM_KEY_LEN 32
1112#define SCM_TEMPORAL_KEY_LENGTH 16
1113
1114struct ieee80211_security {
1115 u16 active_key:2,
1116 enabled:1,
1117 auth_mode:2,
1118 auth_algo:4,
1119 unicast_uses_group:1,
1120 encrypt:1;
1121 u8 key_sizes[WEP_KEYS];
1122 u8 keys[WEP_KEYS][SCM_KEY_LEN];
1123 u8 level;
1124 u16 flags;
1125} __attribute__ ((packed));
1126
1127
1128/*
1129 802.11 data frame from AP
1130 ,-------------------------------------------------------------------.
1131Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
1132 |------|------|---------|---------|---------|------|---------|------|
1133Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs |
1134 | | tion | (BSSID) | | | ence | data | |
1135 `-------------------------------------------------------------------'
1136Total: 28-2340 bytes
1137*/
1138
1139/* Management Frame Information Element Types */
1140enum ieee80211_mfie {
1141 MFIE_TYPE_SSID = 0,
1142 MFIE_TYPE_RATES = 1,
1143 MFIE_TYPE_FH_SET = 2,
1144 MFIE_TYPE_DS_SET = 3,
1145 MFIE_TYPE_CF_SET = 4,
1146 MFIE_TYPE_TIM = 5,
1147 MFIE_TYPE_IBSS_SET = 6,
1148 MFIE_TYPE_COUNTRY = 7,
1149 MFIE_TYPE_HOP_PARAMS = 8,
1150 MFIE_TYPE_HOP_TABLE = 9,
1151 MFIE_TYPE_REQUEST = 10,
1152 MFIE_TYPE_CHALLENGE = 16,
1153 MFIE_TYPE_POWER_CONSTRAINT = 32,
1154 MFIE_TYPE_POWER_CAPABILITY = 33,
1155 MFIE_TYPE_TPC_REQUEST = 34,
1156 MFIE_TYPE_TPC_REPORT = 35,
1157 MFIE_TYPE_SUPP_CHANNELS = 36,
1158 MFIE_TYPE_CSA = 37,
1159 MFIE_TYPE_MEASURE_REQUEST = 38,
1160 MFIE_TYPE_MEASURE_REPORT = 39,
1161 MFIE_TYPE_QUIET = 40,
1162 MFIE_TYPE_IBSS_DFS = 41,
1163 MFIE_TYPE_ERP = 42,
1164 MFIE_TYPE_RSN = 48,
1165 MFIE_TYPE_RATES_EX = 50,
1166 MFIE_TYPE_HT_CAP= 45,
1167 MFIE_TYPE_HT_INFO= 61,
1168 MFIE_TYPE_AIRONET=133,
1169 MFIE_TYPE_GENERIC = 221,
1170 MFIE_TYPE_QOS_PARAMETER = 222,
1171};
1172
1173/* Minimal header; can be used for passing 802.11 frames with sufficient
1174 * information to determine what type of underlying data type is actually
1175 * stored in the data. */
1176struct ieee80211_hdr {
1177 __le16 frame_ctl;
1178 __le16 duration_id;
1179 u8 payload[0];
1180} __attribute__ ((packed));
1181
1182struct ieee80211_hdr_1addr {
1183 __le16 frame_ctl;
1184 __le16 duration_id;
1185 u8 addr1[ETH_ALEN];
1186 u8 payload[0];
1187} __attribute__ ((packed));
1188
1189struct ieee80211_hdr_2addr {
1190 __le16 frame_ctl;
1191 __le16 duration_id;
1192 u8 addr1[ETH_ALEN];
1193 u8 addr2[ETH_ALEN];
1194 u8 payload[0];
1195} __attribute__ ((packed));
1196
1197struct ieee80211_hdr_3addr {
1198 __le16 frame_ctl;
1199 __le16 duration_id;
1200 u8 addr1[ETH_ALEN];
1201 u8 addr2[ETH_ALEN];
1202 u8 addr3[ETH_ALEN];
1203 __le16 seq_ctl;
1204 u8 payload[0];
1205} __attribute__ ((packed));
1206
1207struct ieee80211_hdr_4addr {
1208 __le16 frame_ctl;
1209 __le16 duration_id;
1210 u8 addr1[ETH_ALEN];
1211 u8 addr2[ETH_ALEN];
1212 u8 addr3[ETH_ALEN];
1213 __le16 seq_ctl;
1214 u8 addr4[ETH_ALEN];
1215 u8 payload[0];
1216} __attribute__ ((packed));
1217
1218struct ieee80211_hdr_3addrqos {
1219 __le16 frame_ctl;
1220 __le16 duration_id;
1221 u8 addr1[ETH_ALEN];
1222 u8 addr2[ETH_ALEN];
1223 u8 addr3[ETH_ALEN];
1224 __le16 seq_ctl;
1225 u8 payload[0];
1226 __le16 qos_ctl;
1227} __attribute__ ((packed));
1228
1229struct ieee80211_hdr_4addrqos {
1230 __le16 frame_ctl;
1231 __le16 duration_id;
1232 u8 addr1[ETH_ALEN];
1233 u8 addr2[ETH_ALEN];
1234 u8 addr3[ETH_ALEN];
1235 __le16 seq_ctl;
1236 u8 addr4[ETH_ALEN];
1237 u8 payload[0];
1238 __le16 qos_ctl;
1239} __attribute__ ((packed));
1240
1241struct ieee80211_info_element {
1242 u8 id;
1243 u8 len;
1244 u8 data[0];
1245} __attribute__ ((packed));
1246
1247struct ieee80211_authentication {
1248 struct ieee80211_hdr_3addr header;
1249 __le16 algorithm;
1250 __le16 transaction;
1251 __le16 status;
1252 /*challenge*/
1253 struct ieee80211_info_element info_element[0];
1254} __attribute__ ((packed));
1255
1256struct ieee80211_disassoc {
1257 struct ieee80211_hdr_3addr header;
1258 __le16 reason;
1259} __attribute__ ((packed));
1260
1261struct ieee80211_probe_request {
1262 struct ieee80211_hdr_3addr header;
1263 /* SSID, supported rates */
1264 struct ieee80211_info_element info_element[0];
1265} __attribute__ ((packed));
1266
1267struct ieee80211_probe_response {
1268 struct ieee80211_hdr_3addr header;
1269 u32 time_stamp[2];
1270 __le16 beacon_interval;
1271 __le16 capability;
1272 /* SSID, supported rates, FH params, DS params,
1273 * CF params, IBSS params, TIM (if beacon), RSN */
1274 struct ieee80211_info_element info_element[0];
1275} __attribute__ ((packed));
1276
1277/* Alias beacon for probe_response */
1278#define ieee80211_beacon ieee80211_probe_response
1279
1280struct ieee80211_assoc_request_frame {
1281 struct ieee80211_hdr_3addr header;
1282 __le16 capability;
1283 __le16 listen_interval;
1284 /* SSID, supported rates, RSN */
1285 struct ieee80211_info_element info_element[0];
1286} __attribute__ ((packed));
1287
1288struct ieee80211_reassoc_request_frame {
1289 struct ieee80211_hdr_3addr header;
1290 __le16 capability;
1291 __le16 listen_interval;
1292 u8 current_ap[ETH_ALEN];
1293 /* SSID, supported rates, RSN */
1294 struct ieee80211_info_element info_element[0];
1295} __attribute__ ((packed));
1296
1297struct ieee80211_assoc_response_frame {
1298 struct ieee80211_hdr_3addr header;
1299 __le16 capability;
1300 __le16 status;
1301 __le16 aid;
1302 struct ieee80211_info_element info_element[0]; /* supported rates */
1303} __attribute__ ((packed));
1304
1305struct ieee80211_txb {
1306 u8 nr_frags;
1307 u8 encrypted;
1308 u8 queue_index;
1309 u8 rts_included;
1310 u16 reserved;
1311 __le16 frag_size;
1312 __le16 payload_size;
1313 struct sk_buff *fragments[0];
1314};
1315
1316#define MAX_TX_AGG_COUNT 16
1317struct ieee80211_drv_agg_txb {
1318 u8 nr_drv_agg_frames;
1319 struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT];
1320}__attribute__((packed));
1321
1322#define MAX_SUBFRAME_COUNT 64
1323struct ieee80211_rxb {
1324 u8 nr_subframes;
1325 struct sk_buff *subframes[MAX_SUBFRAME_COUNT];
1326 u8 dst[ETH_ALEN];
1327 u8 src[ETH_ALEN];
1328}__attribute__((packed));
1329
1330typedef union _frameqos {
1331 u16 shortdata;
1332 u8 chardata[2];
1333 struct {
1334 u16 tid:4;
1335 u16 eosp:1;
1336 u16 ack_policy:2;
1337 u16 reserved:1;
1338 u16 txop:8;
1339 }field;
1340}frameqos,*pframeqos;
1341
1342/* SWEEP TABLE ENTRIES NUMBER*/
1343#define MAX_SWEEP_TAB_ENTRIES 42
1344#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7
1345/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
1346 * only use 8, and then use extended rates for the remaining supported
1347 * rates. Other APs, however, stick all of their supported rates on the
1348 * main rates information element... */
1349#define MAX_RATES_LENGTH ((u8)12)
1350#define MAX_RATES_EX_LENGTH ((u8)16)
1351#define MAX_NETWORK_COUNT 128
1352
1353#define MAX_CHANNEL_NUMBER 161
1354#define IEEE80211_SOFTMAC_SCAN_TIME 100
1355//(HZ / 2)
1356#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
1357
1358#define CRC_LENGTH 4U
1359
1360#define MAX_WPA_IE_LEN 64
1361
1362#define NETWORK_EMPTY_ESSID (1<<0)
1363#define NETWORK_HAS_OFDM (1<<1)
1364#define NETWORK_HAS_CCK (1<<2)
1365
1366/* QoS structure */
1367#define NETWORK_HAS_QOS_PARAMETERS (1<<3)
1368#define NETWORK_HAS_QOS_INFORMATION (1<<4)
1369#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \
1370 NETWORK_HAS_QOS_INFORMATION)
1371/* 802.11h */
1372#define NETWORK_HAS_POWER_CONSTRAINT (1<<5)
1373#define NETWORK_HAS_CSA (1<<6)
1374#define NETWORK_HAS_QUIET (1<<7)
1375#define NETWORK_HAS_IBSS_DFS (1<<8)
1376#define NETWORK_HAS_TPC_REPORT (1<<9)
1377
1378#define NETWORK_HAS_ERP_VALUE (1<<10)
1379
1380#define QOS_QUEUE_NUM 4
1381#define QOS_OUI_LEN 3
1382#define QOS_OUI_TYPE 2
1383#define QOS_ELEMENT_ID 221
1384#define QOS_OUI_INFO_SUB_TYPE 0
1385#define QOS_OUI_PARAM_SUB_TYPE 1
1386#define QOS_VERSION_1 1
1387#define QOS_AIFSN_MIN_VALUE 2
1388#if 1
1389struct ieee80211_qos_information_element {
1390 u8 elementID;
1391 u8 length;
1392 u8 qui[QOS_OUI_LEN];
1393 u8 qui_type;
1394 u8 qui_subtype;
1395 u8 version;
1396 u8 ac_info;
1397} __attribute__ ((packed));
1398
1399struct ieee80211_qos_ac_parameter {
1400 u8 aci_aifsn;
1401 u8 ecw_min_max;
1402 __le16 tx_op_limit;
1403} __attribute__ ((packed));
1404
1405struct ieee80211_qos_parameter_info {
1406 struct ieee80211_qos_information_element info_element;
1407 u8 reserved;
1408 struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM];
1409} __attribute__ ((packed));
1410
1411struct ieee80211_qos_parameters {
1412 __le16 cw_min[QOS_QUEUE_NUM];
1413 __le16 cw_max[QOS_QUEUE_NUM];
1414 u8 aifs[QOS_QUEUE_NUM];
1415 u8 flag[QOS_QUEUE_NUM];
1416 __le16 tx_op_limit[QOS_QUEUE_NUM];
1417} __attribute__ ((packed));
1418
1419struct ieee80211_qos_data {
1420 struct ieee80211_qos_parameters parameters;
1421 int active;
1422 int supported;
1423 u8 param_count;
1424 u8 old_param_count;
1425};
1426
1427struct ieee80211_tim_parameters {
1428 u8 tim_count;
1429 u8 tim_period;
1430} __attribute__ ((packed));
1431
1432//#else
1433struct ieee80211_wmm_ac_param {
1434 u8 ac_aci_acm_aifsn;
1435 u8 ac_ecwmin_ecwmax;
1436 u16 ac_txop_limit;
1437};
1438
1439struct ieee80211_wmm_ts_info {
1440 u8 ac_dir_tid;
1441 u8 ac_up_psb;
1442 u8 reserved;
1443} __attribute__ ((packed));
1444
1445struct ieee80211_wmm_tspec_elem {
1446 struct ieee80211_wmm_ts_info ts_info;
1447 u16 norm_msdu_size;
1448 u16 max_msdu_size;
1449 u32 min_serv_inter;
1450 u32 max_serv_inter;
1451 u32 inact_inter;
1452 u32 suspen_inter;
1453 u32 serv_start_time;
1454 u32 min_data_rate;
1455 u32 mean_data_rate;
1456 u32 peak_data_rate;
1457 u32 max_burst_size;
1458 u32 delay_bound;
1459 u32 min_phy_rate;
1460 u16 surp_band_allow;
1461 u16 medium_time;
1462}__attribute__((packed));
1463#endif
1464enum eap_type {
1465 EAP_PACKET = 0,
1466 EAPOL_START,
1467 EAPOL_LOGOFF,
1468 EAPOL_KEY,
1469 EAPOL_ENCAP_ASF_ALERT
1470};
1471
1472static const char *eap_types[] = {
1473 [EAP_PACKET] = "EAP-Packet",
1474 [EAPOL_START] = "EAPOL-Start",
1475 [EAPOL_LOGOFF] = "EAPOL-Logoff",
1476 [EAPOL_KEY] = "EAPOL-Key",
1477 [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert"
1478};
1479
1480static inline const char *eap_get_type(int type)
1481{
1482 return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type];
1483}
1484//added by amy for reorder
1485static inline u8 Frame_QoSTID(u8* buf)
1486{
1487 struct ieee80211_hdr_3addr *hdr;
1488 u16 fc;
1489 hdr = (struct ieee80211_hdr_3addr *)buf;
1490 fc = le16_to_cpu(hdr->frame_ctl);
1491 return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid;
1492}
1493
1494//added by amy for reorder
1495
1496struct eapol {
1497 u8 snap[6];
1498 u16 ethertype;
1499 u8 version;
1500 u8 type;
1501 u16 length;
1502} __attribute__ ((packed));
1503
1504struct ieee80211_softmac_stats{
1505 unsigned int rx_ass_ok;
1506 unsigned int rx_ass_err;
1507 unsigned int rx_probe_rq;
1508 unsigned int tx_probe_rs;
1509 unsigned int tx_beacons;
1510 unsigned int rx_auth_rq;
1511 unsigned int rx_auth_rs_ok;
1512 unsigned int rx_auth_rs_err;
1513 unsigned int tx_auth_rq;
1514 unsigned int no_auth_rs;
1515 unsigned int no_ass_rs;
1516 unsigned int tx_ass_rq;
1517 unsigned int rx_ass_rq;
1518 unsigned int tx_probe_rq;
1519 unsigned int reassoc;
1520 unsigned int swtxstop;
1521 unsigned int swtxawake;
1522 unsigned char CurrentShowTxate;
1523 unsigned char last_packet_rate;
1524 unsigned int txretrycount;
1525};
1526
1527#define BEACON_PROBE_SSID_ID_POSITION 12
1528
1529struct ieee80211_info_element_hdr {
1530 u8 id;
1531 u8 len;
1532} __attribute__ ((packed));
1533
1534/*
1535 * These are the data types that can make up management packets
1536 *
1537 u16 auth_algorithm;
1538 u16 auth_sequence;
1539 u16 beacon_interval;
1540 u16 capability;
1541 u8 current_ap[ETH_ALEN];
1542 u16 listen_interval;
1543 struct {
1544 u16 association_id:14, reserved:2;
1545 } __attribute__ ((packed));
1546 u32 time_stamp[2];
1547 u16 reason;
1548 u16 status;
1549*/
1550
1551#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
1552#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps
1553
1554enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame};
1555#define MAX_SP_Len (WMM_all_frame << 4)
1556#define IEEE80211_QOS_TID 0x0f
1557#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5)
1558
1559#define IEEE80211_DTIM_MBCAST 4
1560#define IEEE80211_DTIM_UCAST 2
1561#define IEEE80211_DTIM_VALID 1
1562#define IEEE80211_DTIM_INVALID 0
1563
1564#define IEEE80211_PS_DISABLED 0
1565#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
1566#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
1567
1568//added by David for QoS 2006/6/30
1569//#define WMM_Hang_8187
1570#ifdef WMM_Hang_8187
1571#undef WMM_Hang_8187
1572#endif
1573
1574#define WME_AC_BK 0x00
1575#define WME_AC_BE 0x01
1576#define WME_AC_VI 0x02
1577#define WME_AC_VO 0x03
1578#define WME_ACI_MASK 0x03
1579#define WME_AIFSN_MASK 0x03
1580#define WME_AC_PRAM_LEN 16
1581
1582#define MAX_RECEIVE_BUFFER_SIZE 9100
1583
1584//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP
1585//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1))
1586#if 1
1587#define UP2AC(up) ( \
1588 ((up) < 1) ? WME_AC_BE : \
1589 ((up) < 3) ? WME_AC_BK : \
1590 ((up) < 4) ? WME_AC_BE : \
1591 ((up) < 6) ? WME_AC_VI : \
1592 WME_AC_VO)
1593#endif
1594//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue
1595#define AC2UP(_ac) ( \
1596 ((_ac) == WME_AC_VO) ? 6 : \
1597 ((_ac) == WME_AC_VI) ? 5 : \
1598 ((_ac) == WME_AC_BK) ? 1 : \
1599 0)
1600
1601#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */
1602#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/
1603
1604struct ether_header {
1605 u8 ether_dhost[ETHER_ADDR_LEN];
1606 u8 ether_shost[ETHER_ADDR_LEN];
1607 u16 ether_type;
1608} __attribute__((packed));
1609
1610#ifndef ETHERTYPE_PAE
1611#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */
1612#endif
1613#ifndef ETHERTYPE_IP
1614#define ETHERTYPE_IP 0x0800 /* IP protocol */
1615#endif
1616
1617typedef struct _bss_ht{
1618
1619 bool support_ht;
1620
1621 // HT related elements
1622 u8 ht_cap_buf[32];
1623 u16 ht_cap_len;
1624 u8 ht_info_buf[32];
1625 u16 ht_info_len;
1626
1627 HT_SPEC_VER ht_spec_ver;
1628 //HT_CAPABILITY_ELE bdHTCapEle;
1629 //HT_INFORMATION_ELE bdHTInfoEle;
1630
1631 bool aggregation;
1632 bool long_slot_time;
1633}bss_ht, *pbss_ht;
1634
1635typedef enum _erp_t{
1636 ERP_NonERPpresent = 0x01,
1637 ERP_UseProtection = 0x02,
1638 ERP_BarkerPreambleMode = 0x04,
1639} erp_t;
1640
1641
1642struct ieee80211_network {
1643 /* These entries are used to identify a unique network */
1644 u8 bssid[ETH_ALEN];
1645 u8 channel;
1646 /* Ensure null-terminated for any debug msgs */
1647 u8 ssid[IW_ESSID_MAX_SIZE + 1];
1648 u8 ssid_len;
1649#if 1
1650 struct ieee80211_qos_data qos_data;
1651#else
1652 // Qos related. Added by Annie, 2005-11-01.
1653 BSS_QOS BssQos;
1654#endif
1655
1656 //added by amy for LEAP
1657 bool bWithAironetIE;
1658 bool bCkipSupported;
1659 bool bCcxRmEnable;
1660 u16 CcxRmState[2];
1661 // CCXv4 S59, MBSSID.
1662 bool bMBssidValid;
1663 u8 MBssidMask;
1664 u8 MBssid[6];
1665 // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20.
1666 bool bWithCcxVerNum;
1667 u8 BssCcxVerNumber;
1668 /* These are network statistics */
1669 struct ieee80211_rx_stats stats;
1670 u16 capability;
1671 u8 rates[MAX_RATES_LENGTH];
1672 u8 rates_len;
1673 u8 rates_ex[MAX_RATES_EX_LENGTH];
1674 u8 rates_ex_len;
1675 unsigned long last_scanned;
1676 u8 mode;
1677 u32 flags;
1678 u32 last_associate;
1679 u32 time_stamp[2];
1680 u16 beacon_interval;
1681 u16 listen_interval;
1682 u16 atim_window;
1683 u8 erp_value;
1684 u8 wpa_ie[MAX_WPA_IE_LEN];
1685 size_t wpa_ie_len;
1686 u8 rsn_ie[MAX_WPA_IE_LEN];
1687 size_t rsn_ie_len;
1688
1689 struct ieee80211_tim_parameters tim;
1690 u8 dtim_period;
1691 u8 dtim_data;
1692 u32 last_dtim_sta_time[2];
1693
1694 //appeded for QoS
1695 u8 wmm_info;
1696 struct ieee80211_wmm_ac_param wmm_param[4];
1697 u8 QoS_Enable;
1698#ifdef THOMAS_TURBO
1699 u8 Turbo_Enable;//enable turbo mode, added by thomas
1700#endif
1701#ifdef ENABLE_DOT11D
1702 u16 CountryIeLen;
1703 u8 CountryIeBuf[MAX_IE_LEN];
1704#endif
1705 // HT Related, by amy, 2008.04.29
1706 BSS_HT bssht;
1707 // Add to handle broadcom AP management frame CCK rate.
1708 bool broadcom_cap_exist;
1709 bool realtek_cap_exit;
1710 bool marvell_cap_exist;
1711 bool ralink_cap_exist;
1712 bool atheros_cap_exist;
1713 bool cisco_cap_exist;
1714 bool unknown_cap_exist;
1715// u8 berp_info;
1716 bool berp_info_valid;
1717 bool buseprotection;
1718 //put at the end of the structure.
1719 struct list_head list;
1720};
1721
1722#if 1
1723enum ieee80211_state {
1724
1725 /* the card is not linked at all */
1726 IEEE80211_NOLINK = 0,
1727
1728 /* IEEE80211_ASSOCIATING* are for BSS client mode
1729 * the driver shall not perform RX filtering unless
1730 * the state is LINKED.
1731 * The driver shall just check for the state LINKED and
1732 * defaults to NOLINK for ALL the other states (including
1733 * LINKED_SCANNING)
1734 */
1735
1736 /* the association procedure will start (wq scheduling)*/
1737 IEEE80211_ASSOCIATING,
1738 IEEE80211_ASSOCIATING_RETRY,
1739
1740 /* the association procedure is sending AUTH request*/
1741 IEEE80211_ASSOCIATING_AUTHENTICATING,
1742
1743 /* the association procedure has successfully authentcated
1744 * and is sending association request
1745 */
1746 IEEE80211_ASSOCIATING_AUTHENTICATED,
1747
1748 /* the link is ok. the card associated to a BSS or linked
1749 * to a ibss cell or acting as an AP and creating the bss
1750 */
1751 IEEE80211_LINKED,
1752
1753 /* same as LINKED, but the driver shall apply RX filter
1754 * rules as we are in NO_LINK mode. As the card is still
1755 * logically linked, but it is doing a syncro site survey
1756 * then it will be back to LINKED state.
1757 */
1758 IEEE80211_LINKED_SCANNING,
1759
1760};
1761#else
1762enum ieee80211_state {
1763 IEEE80211_UNINITIALIZED = 0,
1764 IEEE80211_INITIALIZED,
1765 IEEE80211_ASSOCIATING,
1766 IEEE80211_ASSOCIATED,
1767 IEEE80211_AUTHENTICATING,
1768 IEEE80211_AUTHENTICATED,
1769 IEEE80211_SHUTDOWN
1770};
1771#endif
1772
1773#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
1774#define DEFAULT_FTS 2346
1775
1776#define CFG_IEEE80211_RESERVE_FCS (1<<0)
1777#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
1778#define CFG_IEEE80211_RTS (1<<2)
1779
1780#define IEEE80211_24GHZ_MIN_CHANNEL 1
1781#define IEEE80211_24GHZ_MAX_CHANNEL 14
1782#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \
1783 IEEE80211_24GHZ_MIN_CHANNEL + 1)
1784
1785#define IEEE80211_52GHZ_MIN_CHANNEL 34
1786#define IEEE80211_52GHZ_MAX_CHANNEL 165
1787#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \
1788 IEEE80211_52GHZ_MIN_CHANNEL + 1)
1789
1790#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11))
1791extern inline int is_multicast_ether_addr(const u8 *addr)
1792{
1793 return ((addr[0] != 0xff) && (0x01 & addr[0]));
1794}
1795#endif
1796
1797#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13))
1798extern inline int is_broadcast_ether_addr(const u8 *addr)
1799{
1800 return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \
1801 (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
1802}
1803#endif
1804
1805typedef struct tx_pending_t{
1806 int frag;
1807 struct ieee80211_txb *txb;
1808}tx_pending_t;
1809
1810typedef struct _bandwidth_autoswitch
1811{
1812 long threshold_20Mhzto40Mhz;
1813 long threshold_40Mhzto20Mhz;
1814 bool bforced_tx20Mhz;
1815 bool bautoswitch_enable;
1816}bandwidth_autoswitch,*pbandwidth_autoswitch;
1817
1818
1819//added by amy for order
1820
1821#define REORDER_WIN_SIZE 128
1822#define REORDER_ENTRY_NUM 128
1823typedef struct _RX_REORDER_ENTRY
1824{
1825 struct list_head List;
1826 u16 SeqNum;
1827 struct ieee80211_rxb* prxb;
1828} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY;
1829//added by amy for order
1830typedef enum _Fsync_State{
1831 Default_Fsync,
1832 HW_Fsync,
1833 SW_Fsync
1834}Fsync_State;
1835
1836// Power save mode configured.
1837typedef enum _RT_PS_MODE
1838{
1839 eActive, // Active/Continuous access.
1840 eMaxPs, // Max power save mode.
1841 eFastPs // Fast power save mode.
1842}RT_PS_MODE;
1843
1844typedef enum _IPS_CALLBACK_FUNCION
1845{
1846 IPS_CALLBACK_NONE = 0,
1847 IPS_CALLBACK_MGNT_LINK_REQUEST = 1,
1848 IPS_CALLBACK_JOIN_REQUEST = 2,
1849}IPS_CALLBACK_FUNCION;
1850
1851typedef enum _RT_JOIN_ACTION{
1852 RT_JOIN_INFRA = 1,
1853 RT_JOIN_IBSS = 2,
1854 RT_START_IBSS = 3,
1855 RT_NO_ACTION = 4,
1856}RT_JOIN_ACTION;
1857
1858typedef struct _IbssParms{
1859 u16 atimWin;
1860}IbssParms, *PIbssParms;
1861#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko.
1862
1863// RF state.
1864typedef enum _RT_RF_POWER_STATE
1865{
1866 eRfOn,
1867 eRfSleep,
1868 eRfOff
1869}RT_RF_POWER_STATE;
1870
1871typedef struct _RT_POWER_SAVE_CONTROL
1872{
1873
1874 //
1875 // Inactive Power Save(IPS) : Disable RF when disconnected
1876 //
1877 bool bInactivePs;
1878 bool bIPSModeBackup;
1879 bool bHaltAdapterClkRQ;
1880 bool bSwRfProcessing;
1881 RT_RF_POWER_STATE eInactivePowerState;
1882#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1883 struct work_struct InactivePsWorkItem;
1884#else
1885 struct tq_struct InactivePsWorkItem;
1886#endif
1887 struct timer_list InactivePsTimer;
1888
1889 // Return point for join action
1890 IPS_CALLBACK_FUNCION ReturnPoint;
1891
1892 // Recored Parameters for rescheduled JoinRequest
1893 bool bTmpBssDesc;
1894 RT_JOIN_ACTION tmpJoinAction;
1895 struct ieee80211_network tmpBssDesc;
1896
1897 // Recored Parameters for rescheduled MgntLinkRequest
1898 bool bTmpScanOnly;
1899 bool bTmpActiveScan;
1900 bool bTmpFilterHiddenAP;
1901 bool bTmpUpdateParms;
1902 u8 tmpSsidBuf[33];
1903 OCTET_STRING tmpSsid2Scan;
1904 bool bTmpSsid2Scan;
1905 u8 tmpNetworkType;
1906 u8 tmpChannelNumber;
1907 u16 tmpBcnPeriod;
1908 u8 tmpDtimPeriod;
1909 u16 tmpmCap;
1910 OCTET_STRING tmpSuppRateSet;
1911 u8 tmpSuppRateBuf[MAX_NUM_RATES];
1912 bool bTmpSuppRate;
1913 IbssParms tmpIbpm;
1914 bool bTmpIbpm;
1915
1916 //
1917 // Leisre Poswer Save : Disable RF if connected but traffic is not busy
1918 //
1919 bool bLeisurePs;
1920 u32 PowerProfile;
1921 u8 LpsIdleCount;
1922 u8 RegMaxLPSAwakeIntvl;
1923 u8 LPSAwakeIntvl;
1924
1925 //RF OFF Level
1926 u32 CurPsLevel;
1927 u32 RegRfPsLevel;
1928
1929 //Fw Control LPS
1930 bool bFwCtrlLPS;
1931 u8 FWCtrlPSMode;
1932
1933 //2009.01.01 added by tynli
1934 // Record if there is a link request in IPS RF off progress.
1935 bool LinkReqInIPSRFOffPgs;
1936 // To make sure that connect info should be executed, so we set the bit to filter the link info which comes after the connect info.
1937 bool BufConnectinfoBefore;
1938
1939}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL;
1940
1941typedef u32 RT_RF_CHANGE_SOURCE;
1942#define RF_CHANGE_BY_SW BIT31
1943#define RF_CHANGE_BY_HW BIT30
1944#define RF_CHANGE_BY_PS BIT29
1945#define RF_CHANGE_BY_IPS BIT28
1946#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17.
1947
1948#ifdef ENABLE_DOT11D
1949typedef enum
1950{
1951 COUNTRY_CODE_FCC = 0,
1952 COUNTRY_CODE_IC = 1,
1953 COUNTRY_CODE_ETSI = 2,
1954 COUNTRY_CODE_SPAIN = 3,
1955 COUNTRY_CODE_FRANCE = 4,
1956 COUNTRY_CODE_MKK = 5,
1957 COUNTRY_CODE_MKK1 = 6,
1958 COUNTRY_CODE_ISRAEL = 7,
1959 COUNTRY_CODE_TELEC,
1960 COUNTRY_CODE_MIC,
1961 COUNTRY_CODE_GLOBAL_DOMAIN
1962}country_code_type_t;
1963#endif
1964 // Firmware realted CMD IO.
1965typedef enum _FW_CMD_IO_TYPE{
1966 FW_CMD_DIG_ENABLE = 0, // For DIG DM
1967 FW_CMD_DIG_DISABLE = 1,
1968 FW_CMD_DIG_HALT = 2,
1969 FW_CMD_DIG_RESUME = 3,
1970 FW_CMD_HIGH_PWR_ENABLE = 4, // For High Power DM
1971 FW_CMD_HIGH_PWR_DISABLE = 5,
1972 FW_CMD_RA_RESET = 6, // For Rate adaptive DM
1973 FW_CMD_RA_ACTIVE= 7,
1974 FW_CMD_RA_REFRESH_N= 8,
1975 FW_CMD_RA_REFRESH_BG= 9,
1976 FW_CMD_IQK_ENABLE = 10, // For FW supported IQK
1977 FW_CMD_TXPWR_TRACK_ENABLE = 11, // Tx power tracking switch
1978 FW_CMD_TXPWR_TRACK_DISABLE = 12, // Tx power tracking switch
1979 FW_CMD_PAUSE_DM_BY_SCAN = 13,
1980 FW_CMD_RESUME_DM_BY_SCAN = 14,
1981 FW_CMD_MID_HIGH_PWR_ENABLE = 15,
1982 FW_CMD_LPS_ENTER = 16, // Indifate firmware that driver enters LPS, For PS-Poll hardware bug
1983 FW_CMD_LPS_LEAVE = 17, // Indicate firmware that driver leave LPS, 2009/1/4, by Emily
1984}FW_CMD_IO_TYPE,*PFW_CMD_IO_TYPE;
1985#define RT_MAX_LD_SLOT_NUM 10
1986typedef struct _RT_LINK_DETECT_T{
1987
1988 u32 NumRecvBcnInPeriod;
1989 u32 NumRecvDataInPeriod;
1990
1991 u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status
1992 u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status
1993 u16 SlotNum; // number of CheckForHang period to determine link status
1994 u16 SlotIndex;
1995
1996 u32 NumTxOkInPeriod;
1997 u32 NumRxOkInPeriod;
1998 bool bBusyTraffic;
1999}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
2000
2001
2002struct ieee80211_device {
2003 struct net_device *dev;
2004 struct ieee80211_security sec;
2005
2006 //hw security related
2007// u8 hwsec_support; //support?
2008 u8 hwsec_active; //hw security active.
2009 bool is_silent_reset;
2010 bool is_roaming;
2011 bool ieee_up;
2012 //added by amy
2013 bool bSupportRemoteWakeUp;
2014 RT_PS_MODE dot11PowerSaveMode; // Power save mode configured.
2015 bool actscanning;
2016 //added by amy 090313
2017 bool be_scan_inprogress;
2018 bool beinretry;
2019 RT_RF_POWER_STATE eRFPowerState;
2020 RT_RF_CHANGE_SOURCE RfOffReason;
2021 bool is_set_key;
2022 //11n spec related I wonder if These info structure need to be moved out of ieee80211_device
2023
2024 //11n HT below
2025 PRT_HIGH_THROUGHPUT pHTInfo;
2026 //struct timer_list SwBwTimer;
2027// spinlock_t chnlop_spinlock;
2028 spinlock_t bw_spinlock;
2029
2030 spinlock_t reorder_spinlock;
2031 // for HT operation rate set. we use this one for HT data rate to seperate different descriptors
2032 //the way fill this is the same as in the IE
2033 u8 Regdot11HTOperationalRateSet[16]; //use RATR format
2034 u8 dot11HTOperationalRateSet[16]; //use RATR format
2035 u8 RegHTSuppRateSet[16];
2036 u8 HTCurrentOperaRate;
2037 u8 HTHighestOperaRate;
2038 //wb added for rate operation mode to firmware
2039 u8 bTxDisableRateFallBack;
2040 u8 bTxUseDriverAssingedRate;
2041 atomic_t atm_chnlop;
2042 atomic_t atm_swbw;
2043// u8 HTHighestOperaRate;
2044// u8 HTCurrentOperaRate;
2045
2046 // 802.11e and WMM Traffic Stream Info (TX)
2047 struct list_head Tx_TS_Admit_List;
2048 struct list_head Tx_TS_Pending_List;
2049 struct list_head Tx_TS_Unused_List;
2050 TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM];
2051 // 802.11e and WMM Traffic Stream Info (RX)
2052 struct list_head Rx_TS_Admit_List;
2053 struct list_head Rx_TS_Pending_List;
2054 struct list_head Rx_TS_Unused_List;
2055 RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM];
2056//#ifdef TO_DO_LIST
2057 RX_REORDER_ENTRY RxReorderEntry[128];
2058 struct list_head RxReorder_Unused_List;
2059//#endif
2060 // Qos related. Added by Annie, 2005-11-01.
2061// PSTA_QOS pStaQos;
2062 u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.)
2063
2064
2065 /* Bookkeeping structures */
2066 struct net_device_stats stats;
2067 struct ieee80211_stats ieee_stats;
2068 struct ieee80211_softmac_stats softmac_stats;
2069
2070 /* Probe / Beacon management */
2071 struct list_head network_free_list;
2072 struct list_head network_list;
2073 struct ieee80211_network *networks;
2074 int scans;
2075 int scan_age;
2076
2077 int iw_mode; /* operating mode (IW_MODE_*) */
2078 struct iw_spy_data spy_data;
2079
2080 spinlock_t lock;
2081 spinlock_t wpax_suitlist_lock;
2082
2083 int tx_headroom; /* Set to size of any additional room needed at front
2084 * of allocated Tx SKBs */
2085 u32 config;
2086
2087 /* WEP and other encryption related settings at the device level */
2088 int open_wep; /* Set to 1 to allow unencrypted frames */
2089 int auth_mode;
2090 int reset_on_keychange; /* Set to 1 if the HW needs to be reset on
2091 * WEP key changes */
2092
2093 /* If the host performs {en,de}cryption, then set to 1 */
2094 int host_encrypt;
2095 int host_encrypt_msdu;
2096 int host_decrypt;
2097 /* host performs multicast decryption */
2098 int host_mc_decrypt;
2099
2100 /* host should strip IV and ICV from protected frames */
2101 /* meaningful only when hardware decryption is being used */
2102 int host_strip_iv_icv;
2103
2104 int host_open_frag;
2105 int host_build_iv;
2106 int ieee802_1x; /* is IEEE 802.1X used */
2107
2108 /* WPA data */
2109 bool bHalfWirelessN24GMode;
2110 int wpa_enabled;
2111 int drop_unencrypted;
2112 int tkip_countermeasures;
2113 int privacy_invoked;
2114 size_t wpa_ie_len;
2115 u8 *wpa_ie;
2116 u8 ap_mac_addr[6];
2117 u16 pairwise_key_type;
2118 u16 group_key_type;
2119 struct list_head crypt_deinit_list;
2120 struct ieee80211_crypt_data *crypt[WEP_KEYS];
2121 int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */
2122 struct timer_list crypt_deinit_timer;
2123 int crypt_quiesced;
2124
2125 int bcrx_sta_key; /* use individual keys to override default keys even
2126 * with RX of broad/multicast frames */
2127
2128 /* Fragmentation structures */
2129 // each streaming contain a entry
2130 struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN];
2131 unsigned int frag_next_idx[17];
2132 u16 fts; /* Fragmentation Threshold */
2133#define DEFAULT_RTS_THRESHOLD 2346U
2134#define MIN_RTS_THRESHOLD 1
2135#define MAX_RTS_THRESHOLD 2346U
2136 u16 rts; /* RTS threshold */
2137
2138 /* Association info */
2139 u8 bssid[ETH_ALEN];
2140
2141 /* This stores infos for the current network.
2142 * Either the network we are associated in INFRASTRUCTURE
2143 * or the network that we are creating in MASTER mode.
2144 * ad-hoc is a mixture ;-).
2145 * Note that in infrastructure mode, even when not associated,
2146 * fields bssid and essid may be valid (if wpa_set and essid_set
2147 * are true) as thy carry the value set by the user via iwconfig
2148 */
2149 struct ieee80211_network current_network;
2150
2151 enum ieee80211_state state;
2152
2153 int short_slot;
2154 int reg_mode;
2155 int mode; /* A, B, G */
2156 int modulation; /* CCK, OFDM */
2157 int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */
2158 int abg_true; /* ABG flag */
2159
2160 /* used for forcing the ibss workqueue to terminate
2161 * without wait for the syncro scan to terminate
2162 */
2163 short sync_scan_hurryup;
2164 u16 scan_watch_dog;
2165 int perfect_rssi;
2166 int worst_rssi;
2167
2168 u16 prev_seq_ctl; /* used to drop duplicate frames */
2169
2170 /* map of allowed channels. 0 is dummy */
2171 // FIXME: remeber to default to a basic channel plan depending of the PHY type
2172#ifdef ENABLE_DOT11D
2173 void* pDot11dInfo;
2174 bool bGlobalDomain;
2175#else
2176 int channel_map[MAX_CHANNEL_NUMBER+1];
2177#endif
2178 int rate; /* current rate */
2179 int basic_rate;
2180 //FIXME: pleace callback, see if redundant with softmac_features
2181 short active_scan;
2182
2183 /* this contains flags for selectively enable softmac support */
2184 u16 softmac_features;
2185
2186 /* if the sequence control field is not filled by HW */
2187 u16 seq_ctrl[5];
2188
2189 /* association procedure transaction sequence number */
2190 u16 associate_seq;
2191
2192 /* AID for RTXed association responses */
2193 u16 assoc_id;
2194
2195 /* power save mode related*/
2196 u8 ack_tx_to_ieee;
2197 short ps;
2198 short sta_sleep;
2199 int ps_timeout;
2200 int ps_period;
2201 struct tasklet_struct ps_task;
2202 u32 ps_th;
2203 u32 ps_tl;
2204
2205 short raw_tx;
2206 /* used if IEEE_SOFTMAC_TX_QUEUE is set */
2207 short queue_stop;
2208 short scanning;
2209 short proto_started;
2210
2211 struct semaphore wx_sem;
2212 struct semaphore scan_sem;
2213
2214 spinlock_t mgmt_tx_lock;
2215 spinlock_t beacon_lock;
2216
2217 short beacon_txing;
2218
2219 short wap_set;
2220 short ssid_set;
2221
2222 u8 wpax_type_set; //{added by David, 2006.9.28}
2223 u32 wpax_type_notify; //{added by David, 2006.9.26}
2224
2225 /* QoS related flag */
2226 char init_wmmparam_flag;
2227 /* set on initialization */
2228 u8 qos_support;
2229
2230 /* for discarding duplicated packets in IBSS */
2231 struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE];
2232
2233 /* for discarding duplicated packets in BSS */
2234 u16 last_rxseq_num[17]; /* rx seq previous per-tid */
2235 u16 last_rxfrag_num[17];/* tx frag previous per-tid */
2236 unsigned long last_packet_time[17];
2237
2238 /* for PS mode */
2239 unsigned long last_rx_ps_time;
2240
2241 /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */
2242 struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM];
2243 int mgmt_queue_head;
2244 int mgmt_queue_tail;
2245//{ added for rtl819x
2246#define IEEE80211_QUEUE_LIMIT 128
2247 u8 AsocRetryCount;
2248 unsigned int hw_header;
2249 struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE];
2250 struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE];
2251 struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE];
2252 u32 sta_edca_param[4];
2253 bool aggregation;
2254 // Enable/Disable Rx immediate BA capability.
2255 bool enable_rx_imm_BA;
2256 bool bibsscoordinator;
2257
2258 //+by amy for DM ,080515
2259 //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15
2260 bool bdynamic_txpower_enable;
2261
2262 bool bCTSToSelfEnable;
2263 u8 CTSToSelfTH;
2264
2265 u32 fsync_time_interval;
2266 u32 fsync_rate_bitmap;
2267 u8 fsync_rssi_threshold;
2268 bool bfsync_enable;
2269
2270 u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval
2271 u32 fsync_firstdiff_ratethreshold; // low threshold
2272 u32 fsync_seconddiff_ratethreshold; // decrease threshold
2273 Fsync_State fsync_state;
2274 bool bis_any_nonbepkts;
2275 //20Mhz 40Mhz AutoSwitch Threshold
2276 bandwidth_autoswitch bandwidth_auto_switch;
2277 //for txpower tracking
2278 bool FwRWRF;
2279
2280 //added by amy for AP roaming
2281 RT_LINK_DETECT_T LinkDetectInfo;
2282 //added by amy for ps
2283 RT_POWER_SAVE_CONTROL PowerSaveControl;
2284//}
2285 /* used if IEEE_SOFTMAC_TX_QUEUE is set */
2286 struct tx_pending_t tx_pending;
2287
2288 /* used if IEEE_SOFTMAC_ASSOCIATE is set */
2289 struct timer_list associate_timer;
2290
2291 /* used if IEEE_SOFTMAC_BEACONS is set */
2292 struct timer_list beacon_timer;
2293#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2294 struct work_struct associate_complete_wq;
2295 struct work_struct associate_procedure_wq;
2296#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2297 struct delayed_work softmac_scan_wq;
2298 struct delayed_work associate_retry_wq;
2299 struct delayed_work start_ibss_wq;
2300 struct delayed_work hw_wakeup_wq;
2301 struct delayed_work hw_sleep_wq;
2302 struct delayed_work link_change_wq;
2303#else
2304 struct work_struct softmac_scan_wq;
2305 struct work_struct associate_retry_wq;
2306 struct work_struct start_ibss_wq;
2307 struct work_struct hw_wakeup_wq;
2308 struct work_struct hw_sleep_wq;
2309 struct work_struct link_change_wq;
2310#endif
2311 struct work_struct wx_sync_scan_wq;
2312 struct workqueue_struct *wq;
2313#else
2314 /* used for periodly scan */
2315 struct timer_list scan_timer;
2316
2317 struct tq_struct associate_complete_wq;
2318 struct tq_struct associate_retry_wq;
2319 struct tq_struct start_ibss_wq;
2320 struct tq_struct associate_procedure_wq;
2321 struct tq_struct softmac_scan_wq;
2322 struct tq_struct wx_sync_scan_wq;
2323 struct tq_struct hw_wakeup_wq;
2324 struct tq_struct hw_sleep_wq;
2325 struct tq_struct link_change_wq;
2326
2327#endif
2328 // Qos related. Added by Annie, 2005-11-01.
2329 //STA_QOS StaQos;
2330
2331 //u32 STA_EDCA_PARAM[4];
2332 //CHANNEL_ACCESS_SETTING ChannelAccessSetting;
2333
2334
2335 /* Callback functions */
2336 void (*set_security)(struct net_device *dev,
2337 struct ieee80211_security *sec);
2338
2339 /* Used to TX data frame by using txb structs.
2340 * this is not used if in the softmac_features
2341 * is set the flag IEEE_SOFTMAC_TX_QUEUE
2342 */
2343 int (*hard_start_xmit)(struct ieee80211_txb *txb,
2344 struct net_device *dev);
2345
2346 int (*reset_port)(struct net_device *dev);
2347 int (*is_queue_full) (struct net_device * dev, int pri);
2348
2349 int (*handle_management) (struct net_device * dev,
2350 struct ieee80211_network * network, u16 type);
2351 int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb);
2352
2353 /* Softmac-generated frames (mamagement) are TXed via this
2354 * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is
2355 * not set. As some cards may have different HW queues that
2356 * one might want to use for data and management frames
2357 * the option to have two callbacks might be useful.
2358 * This fucntion can't sleep.
2359 */
2360 int (*softmac_hard_start_xmit)(struct sk_buff *skb,
2361 struct net_device *dev);
2362
2363 /* used instead of hard_start_xmit (not softmac_hard_start_xmit)
2364 * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data
2365 * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set
2366 * then also management frames are sent via this callback.
2367 * This function can't sleep.
2368 */
2369 void (*softmac_data_hard_start_xmit)(struct sk_buff *skb,
2370 struct net_device *dev,int rate);
2371
2372 /* stops the HW queue for DATA frames. Useful to avoid
2373 * waste time to TX data frame when we are reassociating
2374 * This function can sleep.
2375 */
2376 void (*data_hard_stop)(struct net_device *dev);
2377
2378 /* OK this is complementar to data_poll_hard_stop */
2379 void (*data_hard_resume)(struct net_device *dev);
2380
2381 /* ask to the driver to retune the radio .
2382 * This function can sleep. the driver should ensure
2383 * the radio has been swithced before return.
2384 */
2385 void (*set_chan)(struct net_device *dev,short ch);
2386
2387 /* These are not used if the ieee stack takes care of
2388 * scanning (IEEE_SOFTMAC_SCAN feature set).
2389 * In this case only the set_chan is used.
2390 *
2391 * The syncro version is similar to the start_scan but
2392 * does not return until all channels has been scanned.
2393 * this is called in user context and should sleep,
2394 * it is called in a work_queue when swithcing to ad-hoc mode
2395 * or in behalf of iwlist scan when the card is associated
2396 * and root user ask for a scan.
2397 * the fucntion stop_scan should stop both the syncro and
2398 * background scanning and can sleep.
2399 * The fucntion start_scan should initiate the background
2400 * scanning and can't sleep.
2401 */
2402 void (*scan_syncro)(struct net_device *dev);
2403 void (*start_scan)(struct net_device *dev);
2404 void (*stop_scan)(struct net_device *dev);
2405
2406 /* indicate the driver that the link state is changed
2407 * for example it may indicate the card is associated now.
2408 * Driver might be interested in this to apply RX filter
2409 * rules or simply light the LINK led
2410 */
2411 void (*link_change)(struct net_device *dev);
2412
2413 /* these two function indicates to the HW when to start
2414 * and stop to send beacons. This is used when the
2415 * IEEE_SOFTMAC_BEACONS is not set. For now the
2416 * stop_send_bacons is NOT guaranteed to be called only
2417 * after start_send_beacons.
2418 */
2419 void (*start_send_beacons) (struct net_device *dev);
2420 void (*stop_send_beacons) (struct net_device *dev);
2421
2422 /* power save mode related */
2423 void (*sta_wake_up) (struct net_device *dev);
2424// void (*ps_request_tx_ack) (struct net_device *dev);
2425 void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl);
2426 short (*ps_is_queue_empty) (struct net_device *dev);
2427#if 0
2428 /* Typical STA methods */
2429 int (*handle_auth) (struct net_device * dev,
2430 struct ieee80211_auth * auth);
2431 int (*handle_deauth) (struct net_device * dev,
2432 struct ieee80211_deauth * auth);
2433 int (*handle_action) (struct net_device * dev,
2434 struct ieee80211_action * action,
2435 struct ieee80211_rx_stats * stats);
2436 int (*handle_disassoc) (struct net_device * dev,
2437 struct ieee80211_disassoc * assoc);
2438#endif
2439 int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network);
2440#if 0
2441 int (*handle_probe_response) (struct net_device * dev,
2442 struct ieee80211_probe_response * resp,
2443 struct ieee80211_network * network);
2444 int (*handle_probe_request) (struct net_device * dev,
2445 struct ieee80211_probe_request * req,
2446 struct ieee80211_rx_stats * stats);
2447#endif
2448 int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network);
2449
2450#if 0
2451 /* Typical AP methods */
2452 int (*handle_assoc_request) (struct net_device * dev);
2453 int (*handle_reassoc_request) (struct net_device * dev,
2454 struct ieee80211_reassoc_request * req);
2455#endif
2456
2457 /* check whether Tx hw resouce available */
2458 short (*check_nic_enough_desc)(struct net_device *dev, int queue_index);
2459 //added by wb for HT related
2460// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel);
2461 void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
2462// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate);
2463 bool (*GetNmodeSupportBySecCfg)(struct net_device* dev);
2464 void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode);
2465 bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev);
2466 bool (*is_ap_in_wep_tkip)(struct net_device* dev);
2467 void (*InitialGainHandler)(struct net_device *dev, u8 Operation);
2468 bool (*SetFwCmdHandler)(struct net_device *dev, FW_CMD_IO_TYPE FwCmdIO);
2469 void (*LedControlHandler)(struct net_device * dev, LED_CTL_MODE LedAction);
2470 /* This must be the last item so that it points to the data
2471 * allocated beyond this structure by alloc_ieee80211 */
2472 u8 priv[0];
2473};
2474
2475#define IEEE_A (1<<0)
2476#define IEEE_B (1<<1)
2477#define IEEE_G (1<<2)
2478#define IEEE_N_24G (1<<4)
2479#define IEEE_N_5G (1<<5)
2480#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
2481
2482/* Generate a 802.11 header */
2483
2484/* Uses the channel change callback directly
2485 * instead of [start/stop] scan callbacks
2486 */
2487#define IEEE_SOFTMAC_SCAN (1<<2)
2488
2489/* Perform authentication and association handshake */
2490#define IEEE_SOFTMAC_ASSOCIATE (1<<3)
2491
2492/* Generate probe requests */
2493#define IEEE_SOFTMAC_PROBERQ (1<<4)
2494
2495/* Generate respones to probe requests */
2496#define IEEE_SOFTMAC_PROBERS (1<<5)
2497
2498/* The ieee802.11 stack will manages the netif queue
2499 * wake/stop for the driver, taking care of 802.11
2500 * fragmentation. See softmac.c for details. */
2501#define IEEE_SOFTMAC_TX_QUEUE (1<<7)
2502
2503/* Uses only the softmac_data_hard_start_xmit
2504 * even for TX management frames.
2505 */
2506#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8)
2507
2508/* Generate beacons. The stack will enqueue beacons
2509 * to the card
2510 */
2511#define IEEE_SOFTMAC_BEACONS (1<<6)
2512
2513static inline void *ieee80211_priv(struct net_device *dev)
2514{
2515#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2516 return ((struct ieee80211_device *)netdev_priv(dev))->priv;
2517#else
2518 return ((struct ieee80211_device *)dev->priv)->priv;
2519#endif
2520}
2521
2522extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
2523{
2524 /* Single white space is for Linksys APs */
2525 if (essid_len == 1 && essid[0] == ' ')
2526 return 1;
2527
2528 /* Otherwise, if the entire essid is 0, we assume it is hidden */
2529 while (essid_len) {
2530 essid_len--;
2531 if (essid[essid_len] != '\0')
2532 return 0;
2533 }
2534
2535 return 1;
2536}
2537
2538extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
2539{
2540 /*
2541 * It is possible for both access points and our device to support
2542 * combinations of modes, so as long as there is one valid combination
2543 * of ap/device supported modes, then return success
2544 *
2545 */
2546 if ((mode & IEEE_A) &&
2547 (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
2548 (ieee->freq_band & IEEE80211_52GHZ_BAND))
2549 return 1;
2550
2551 if ((mode & IEEE_G) &&
2552 (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
2553 (ieee->freq_band & IEEE80211_24GHZ_BAND))
2554 return 1;
2555
2556 if ((mode & IEEE_B) &&
2557 (ieee->modulation & IEEE80211_CCK_MODULATION) &&
2558 (ieee->freq_band & IEEE80211_24GHZ_BAND))
2559 return 1;
2560
2561 return 0;
2562}
2563
2564extern inline int ieee80211_get_hdrlen(u16 fc)
2565{
2566 int hdrlen = IEEE80211_3ADDR_LEN;
2567
2568 switch (WLAN_FC_GET_TYPE(fc)) {
2569 case IEEE80211_FTYPE_DATA:
2570 if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))
2571 hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */
2572 if(IEEE80211_QOS_HAS_SEQ(fc))
2573 hdrlen += 2; /* QOS ctrl*/
2574 break;
2575 case IEEE80211_FTYPE_CTL:
2576 switch (WLAN_FC_GET_STYPE(fc)) {
2577 case IEEE80211_STYPE_CTS:
2578 case IEEE80211_STYPE_ACK:
2579 hdrlen = IEEE80211_1ADDR_LEN;
2580 break;
2581 default:
2582 hdrlen = IEEE80211_2ADDR_LEN;
2583 break;
2584 }
2585 break;
2586 }
2587
2588 return hdrlen;
2589}
2590
2591static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr)
2592{
2593 switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) {
2594 case IEEE80211_1ADDR_LEN:
2595 return ((struct ieee80211_hdr_1addr *)hdr)->payload;
2596 case IEEE80211_2ADDR_LEN:
2597 return ((struct ieee80211_hdr_2addr *)hdr)->payload;
2598 case IEEE80211_3ADDR_LEN:
2599 return ((struct ieee80211_hdr_3addr *)hdr)->payload;
2600 case IEEE80211_4ADDR_LEN:
2601 return ((struct ieee80211_hdr_4addr *)hdr)->payload;
2602 }
2603 return NULL;
2604}
2605
2606static inline int ieee80211_is_ofdm_rate(u8 rate)
2607{
2608 switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
2609 case IEEE80211_OFDM_RATE_6MB:
2610 case IEEE80211_OFDM_RATE_9MB:
2611 case IEEE80211_OFDM_RATE_12MB:
2612 case IEEE80211_OFDM_RATE_18MB:
2613 case IEEE80211_OFDM_RATE_24MB:
2614 case IEEE80211_OFDM_RATE_36MB:
2615 case IEEE80211_OFDM_RATE_48MB:
2616 case IEEE80211_OFDM_RATE_54MB:
2617 return 1;
2618 }
2619 return 0;
2620}
2621
2622static inline int ieee80211_is_cck_rate(u8 rate)
2623{
2624 switch (rate & ~IEEE80211_BASIC_RATE_MASK) {
2625 case IEEE80211_CCK_RATE_1MB:
2626 case IEEE80211_CCK_RATE_2MB:
2627 case IEEE80211_CCK_RATE_5MB:
2628 case IEEE80211_CCK_RATE_11MB:
2629 return 1;
2630 }
2631 return 0;
2632}
2633
2634
2635/* ieee80211.c */
2636extern void free_ieee80211(struct net_device *dev);
2637extern struct net_device *alloc_ieee80211(int sizeof_priv);
2638
2639extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
2640
2641/* ieee80211_tx.c */
2642
2643extern int ieee80211_encrypt_fragment(
2644 struct ieee80211_device *ieee,
2645 struct sk_buff *frag,
2646 int hdr_len);
2647
2648extern int ieee80211_xmit(struct sk_buff *skb,
2649 struct net_device *dev);
2650extern void ieee80211_txb_free(struct ieee80211_txb *);
2651
2652
2653/* ieee80211_rx.c */
2654extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
2655 struct ieee80211_rx_stats *rx_stats);
2656extern void ieee80211_rx_mgt(struct ieee80211_device *ieee,
2657 struct ieee80211_hdr_4addr *header,
2658 struct ieee80211_rx_stats *stats);
2659
2660/* ieee80211_wx.c */
2661extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
2662 struct iw_request_info *info,
2663 union iwreq_data *wrqu, char *key);
2664extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee,
2665 struct iw_request_info *info,
2666 union iwreq_data *wrqu, char *key);
2667extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
2668 struct iw_request_info *info,
2669 union iwreq_data *wrqu, char *key);
2670#if WIRELESS_EXT >= 18
2671extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee,
2672 struct iw_request_info *info,
2673 union iwreq_data* wrqu, char *extra);
2674extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee,
2675 struct iw_request_info *info,
2676 union iwreq_data* wrqu, char *extra);
2677extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee,
2678 struct iw_request_info *info,
2679 struct iw_param *data, char *extra);
2680extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee,
2681 struct iw_request_info *info,
2682 union iwreq_data *wrqu, char *extra);
2683#endif
2684extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len);
2685
2686/* ieee80211_softmac.c */
2687extern short ieee80211_is_54g(struct ieee80211_network net);
2688extern short ieee80211_is_shortslot(struct ieee80211_network net);
2689extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb,
2690 struct ieee80211_rx_stats *rx_stats, u16 type,
2691 u16 stype);
2692extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net);
2693
2694void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn);
2695extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee);
2696
2697extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee);
2698extern void notify_wx_assoc_event(struct ieee80211_device *ieee);
2699extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee);
2700extern void ieee80211_start_bss(struct ieee80211_device *ieee);
2701extern void ieee80211_start_master_bss(struct ieee80211_device *ieee);
2702extern void ieee80211_start_ibss(struct ieee80211_device *ieee);
2703extern void ieee80211_softmac_init(struct ieee80211_device *ieee);
2704extern void ieee80211_softmac_free(struct ieee80211_device *ieee);
2705extern void ieee80211_associate_abort(struct ieee80211_device *ieee);
2706extern void ieee80211_disassociate(struct ieee80211_device *ieee);
2707extern void ieee80211_stop_scan(struct ieee80211_device *ieee);
2708extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee);
2709extern void ieee80211_check_all_nets(struct ieee80211_device *ieee);
2710extern void ieee80211_start_protocol(struct ieee80211_device *ieee);
2711extern void ieee80211_stop_protocol(struct ieee80211_device *ieee);
2712extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee);
2713extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee);
2714extern void ieee80211_reset_queue(struct ieee80211_device *ieee);
2715extern void ieee80211_wake_queue(struct ieee80211_device *ieee);
2716extern void ieee80211_stop_queue(struct ieee80211_device *ieee);
2717extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee);
2718extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee);
2719extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee);
2720extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p);
2721extern void notify_wx_assoc_event(struct ieee80211_device *ieee);
2722extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success);
2723
2724extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee);
2725
2726/* ieee80211_crypt_ccmp&tkip&wep.c */
2727extern void ieee80211_tkip_null(void);
2728extern void ieee80211_wep_null(void);
2729extern void ieee80211_ccmp_null(void);
2730
2731/* ieee80211_softmac_wx.c */
2732
2733extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee,
2734 struct iw_request_info *info,
2735 union iwreq_data *wrqu, char *ext);
2736
2737extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee,
2738 struct iw_request_info *info,
2739 union iwreq_data *awrq,
2740 char *extra);
2741
2742extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b);
2743
2744extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee,
2745 struct iw_request_info *info,
2746 union iwreq_data *wrqu, char *extra);
2747
2748extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee,
2749 struct iw_request_info *info,
2750 union iwreq_data *wrqu, char *extra);
2751
2752extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
2753 union iwreq_data *wrqu, char *b);
2754
2755extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a,
2756 union iwreq_data *wrqu, char *b);
2757
2758extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee,
2759 struct iw_request_info *a,
2760 union iwreq_data *wrqu, char *extra);
2761
2762extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
2763 union iwreq_data *wrqu, char *b);
2764
2765extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a,
2766 union iwreq_data *wrqu, char *b);
2767
2768extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a,
2769 union iwreq_data *wrqu, char *b);
2770
2771//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee);
2772#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2773extern void ieee80211_wx_sync_scan_wq(struct work_struct *work);
2774#else
2775 extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee);
2776#endif
2777
2778
2779extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee,
2780 struct iw_request_info *info,
2781 union iwreq_data *wrqu, char *extra);
2782
2783extern int ieee80211_wx_get_name(struct ieee80211_device *ieee,
2784 struct iw_request_info *info,
2785 union iwreq_data *wrqu, char *extra);
2786
2787extern int ieee80211_wx_set_power(struct ieee80211_device *ieee,
2788 struct iw_request_info *info,
2789 union iwreq_data *wrqu, char *extra);
2790
2791extern int ieee80211_wx_get_power(struct ieee80211_device *ieee,
2792 struct iw_request_info *info,
2793 union iwreq_data *wrqu, char *extra);
2794
2795extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee,
2796 struct iw_request_info *info,
2797 union iwreq_data *wrqu, char *extra);
2798
2799extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee,
2800 struct iw_request_info *info,
2801 union iwreq_data *wrqu, char *extra);
2802//HT
2803#define MAX_RECEIVE_BUFFER_SIZE 9100 //
2804extern void HTDebugHTCapability(u8* CapIE, u8* TitleString );
2805extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString);
2806
2807void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
2808extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee);
2809extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt);
2810extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt);
2811extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len);
2812extern void HTOnAssocRsp(struct ieee80211_device *ieee);
2813extern void HTInitializeHTInfo(struct ieee80211_device* ieee);
2814extern void HTInitializeBssDesc(PBSS_HT pBssHT);
2815extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork);
2816extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork);
2817extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter);
2818extern u8 MCS_FILTER_ALL[];
2819extern u16 MCS_DATA_RATE[2][2][77] ;
2820extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame);
2821//extern void HTSetConnectBwModeCallback(unsigned long data);
2822extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo);
2823extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee);
2824extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate);
2825extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate);
2826extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate);
2827//function in BAPROC.c
2828extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb);
2829extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb);
2830extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb);
2831extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending);
2832extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect);
2833extern void BaSetupTimeOut(unsigned long data);
2834extern void TxBaInactTimeout(unsigned long data);
2835extern void RxBaInactTimeout(unsigned long data);
2836extern void ResetBaEntry( PBA_RECORD pBA);
2837//function in TS.c
2838extern bool GetTs(
2839 struct ieee80211_device* ieee,
2840 PTS_COMMON_INFO *ppTS,
2841 u8* Addr,
2842 u8 TID,
2843 TR_SELECT TxRxSelect, //Rx:1, Tx:0
2844 bool bAddNewTs
2845 );
2846extern void TSInitialize(struct ieee80211_device *ieee);
2847extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS);
2848extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr);
2849extern void RemoveAllTS(struct ieee80211_device* ieee);
2850void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee);
2851
2852extern const long ieee80211_wlan_frequencies[];
2853
2854extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
2855{
2856 ieee->scans++;
2857}
2858
2859extern inline int ieee80211_get_scans(struct ieee80211_device *ieee)
2860{
2861 return ieee->scans;
2862}
2863
2864static inline const char *escape_essid(const char *essid, u8 essid_len) {
2865 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
2866 const char *s = essid;
2867 char *d = escaped;
2868
2869 if (ieee80211_is_empty_essid(essid, essid_len)) {
2870 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
2871 return escaped;
2872 }
2873
2874 essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE);
2875 while (essid_len--) {
2876 if (*s == '\0') {
2877 *d++ = '\\';
2878 *d++ = '0';
2879 s++;
2880 } else {
2881 *d++ = *s++;
2882 }
2883 }
2884 *d = '\0';
2885 return escaped;
2886}
2887
2888/* For the function is more related to hardware setting, it's better to use the
2889 * ieee handler to refer to it.
2890 */
2891extern short check_nic_enough_desc(struct net_device *dev, int queue_index);
2892extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev);
2893extern int ieee80211_parse_info_param(struct ieee80211_device *ieee,
2894 struct ieee80211_info_element *info_element,
2895 u16 length,
2896 struct ieee80211_network *network,
2897 struct ieee80211_rx_stats *stats);
2898
2899void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index);
2900#define RT_ASOC_RETRY_LIMIT 5
2901#endif /* IEEE80211_H */
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c
new file mode 100644
index 00000000000..199ee1695ad
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c
@@ -0,0 +1,273 @@
1/*
2 * Host AP crypto routines
3 *
4 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
5 * Portions Copyright (C) 2004, Intel Corporation <jketreno@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. See README and COPYING for
10 * more details.
11 *
12 */
13
14//#include <linux/config.h>
15#include <linux/version.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <asm/string.h>
20#include <asm/errno.h>
21
22#include "ieee80211.h"
23
24MODULE_AUTHOR("Jouni Malinen");
25MODULE_DESCRIPTION("HostAP crypto");
26MODULE_LICENSE("GPL");
27
28struct ieee80211_crypto_alg {
29 struct list_head list;
30 struct ieee80211_crypto_ops *ops;
31};
32
33
34struct ieee80211_crypto {
35 struct list_head algs;
36 spinlock_t lock;
37};
38
39static struct ieee80211_crypto *hcrypt;
40
41void ieee80211_crypt_deinit_entries(struct ieee80211_device *ieee,
42 int force)
43{
44 struct list_head *ptr, *n;
45 struct ieee80211_crypt_data *entry;
46
47 for (ptr = ieee->crypt_deinit_list.next, n = ptr->next;
48 ptr != &ieee->crypt_deinit_list; ptr = n, n = ptr->next) {
49 entry = list_entry(ptr, struct ieee80211_crypt_data, list);
50
51 if (atomic_read(&entry->refcnt) != 0 && !force)
52 continue;
53
54 list_del(ptr);
55
56 if (entry->ops) {
57 entry->ops->deinit(entry->priv);
58#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
59 module_put(entry->ops->owner);
60#else
61 __MOD_DEC_USE_COUNT(entry->ops->owner);
62#endif
63 }
64 kfree(entry);
65 }
66}
67
68void ieee80211_crypt_deinit_handler(unsigned long data)
69{
70 struct ieee80211_device *ieee = (struct ieee80211_device *)data;
71 unsigned long flags;
72
73 spin_lock_irqsave(&ieee->lock, flags);
74 ieee80211_crypt_deinit_entries(ieee, 0);
75 if (!list_empty(&ieee->crypt_deinit_list)) {
76 printk(KERN_DEBUG "%s: entries remaining in delayed crypt "
77 "deletion list\n", ieee->dev->name);
78 ieee->crypt_deinit_timer.expires = jiffies + HZ;
79 add_timer(&ieee->crypt_deinit_timer);
80 }
81 spin_unlock_irqrestore(&ieee->lock, flags);
82
83}
84
85void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
86 struct ieee80211_crypt_data **crypt)
87{
88 struct ieee80211_crypt_data *tmp;
89 unsigned long flags;
90
91 if (*crypt == NULL)
92 return;
93
94 tmp = *crypt;
95 *crypt = NULL;
96
97 /* must not run ops->deinit() while there may be pending encrypt or
98 * decrypt operations. Use a list of delayed deinits to avoid needing
99 * locking. */
100
101 spin_lock_irqsave(&ieee->lock, flags);
102 list_add(&tmp->list, &ieee->crypt_deinit_list);
103 if (!timer_pending(&ieee->crypt_deinit_timer)) {
104 ieee->crypt_deinit_timer.expires = jiffies + HZ;
105 add_timer(&ieee->crypt_deinit_timer);
106 }
107 spin_unlock_irqrestore(&ieee->lock, flags);
108}
109
110int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops)
111{
112 unsigned long flags;
113 struct ieee80211_crypto_alg *alg;
114
115 if (hcrypt == NULL)
116 return -1;
117
118 alg = kmalloc(sizeof(*alg), GFP_KERNEL);
119 if (alg == NULL)
120 return -ENOMEM;
121
122 memset(alg, 0, sizeof(*alg));
123 alg->ops = ops;
124
125 spin_lock_irqsave(&hcrypt->lock, flags);
126 list_add(&alg->list, &hcrypt->algs);
127 spin_unlock_irqrestore(&hcrypt->lock, flags);
128
129 printk(KERN_DEBUG "ieee80211_crypt: registered algorithm '%s'\n",
130 ops->name);
131
132 return 0;
133}
134
135int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops)
136{
137 unsigned long flags;
138 struct list_head *ptr;
139 struct ieee80211_crypto_alg *del_alg = NULL;
140
141 if (hcrypt == NULL)
142 return -1;
143
144 spin_lock_irqsave(&hcrypt->lock, flags);
145 for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) {
146 struct ieee80211_crypto_alg *alg =
147 (struct ieee80211_crypto_alg *) ptr;
148 if (alg->ops == ops) {
149 list_del(&alg->list);
150 del_alg = alg;
151 break;
152 }
153 }
154 spin_unlock_irqrestore(&hcrypt->lock, flags);
155
156 if (del_alg) {
157 printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm "
158 "'%s'\n", ops->name);
159 kfree(del_alg);
160 }
161
162 return del_alg ? 0 : -1;
163}
164
165
166struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name)
167{
168 unsigned long flags;
169 struct list_head *ptr;
170 struct ieee80211_crypto_alg *found_alg = NULL;
171
172 if (hcrypt == NULL)
173 return NULL;
174
175 spin_lock_irqsave(&hcrypt->lock, flags);
176 for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) {
177 struct ieee80211_crypto_alg *alg =
178 (struct ieee80211_crypto_alg *) ptr;
179 if (strcmp(alg->ops->name, name) == 0) {
180 found_alg = alg;
181 break;
182 }
183 }
184 spin_unlock_irqrestore(&hcrypt->lock, flags);
185
186 if (found_alg)
187 return found_alg->ops;
188 else
189 return NULL;
190}
191
192
193static void * ieee80211_crypt_null_init(int keyidx) { return (void *) 1; }
194static void ieee80211_crypt_null_deinit(void *priv) {}
195
196static struct ieee80211_crypto_ops ieee80211_crypt_null = {
197 .name = "NULL",
198 .init = ieee80211_crypt_null_init,
199 .deinit = ieee80211_crypt_null_deinit,
200 .encrypt_mpdu = NULL,
201 .decrypt_mpdu = NULL,
202 .encrypt_msdu = NULL,
203 .decrypt_msdu = NULL,
204 .set_key = NULL,
205 .get_key = NULL,
206 .extra_prefix_len = 0,
207 .extra_postfix_len = 0,
208 .owner = THIS_MODULE,
209};
210
211
212static int __init ieee80211_crypto_init(void)
213{
214 int ret = -ENOMEM;
215
216 hcrypt = kmalloc(sizeof(*hcrypt), GFP_KERNEL);
217 if (!hcrypt)
218 goto out;
219
220 memset(hcrypt, 0, sizeof(*hcrypt));
221 INIT_LIST_HEAD(&hcrypt->algs);
222 spin_lock_init(&hcrypt->lock);
223
224 ret = ieee80211_register_crypto_ops(&ieee80211_crypt_null);
225 if (ret < 0) {
226 kfree(hcrypt);
227 hcrypt = NULL;
228 }
229out:
230 return ret;
231}
232
233
234static void __exit ieee80211_crypto_deinit(void)
235{
236 struct list_head *ptr, *n;
237
238 if (hcrypt == NULL)
239 return;
240
241 for (ptr = hcrypt->algs.next, n = ptr->next; ptr != &hcrypt->algs;
242 ptr = n, n = ptr->next) {
243 struct ieee80211_crypto_alg *alg =
244 (struct ieee80211_crypto_alg *) ptr;
245 list_del(ptr);
246 printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm "
247 "'%s' (deinit)\n", alg->ops->name);
248 kfree(alg);
249 }
250
251 kfree(hcrypt);
252}
253
254#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
255EXPORT_SYMBOL(ieee80211_crypt_deinit_entries);
256EXPORT_SYMBOL(ieee80211_crypt_deinit_handler);
257EXPORT_SYMBOL(ieee80211_crypt_delayed_deinit);
258
259EXPORT_SYMBOL(ieee80211_register_crypto_ops);
260EXPORT_SYMBOL(ieee80211_unregister_crypto_ops);
261EXPORT_SYMBOL(ieee80211_get_crypto_ops);
262#else
263EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_entries);
264EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_handler);
265EXPORT_SYMBOL_NOVERS(ieee80211_crypt_delayed_deinit);
266
267EXPORT_SYMBOL_NOVERS(ieee80211_register_crypto_ops);
268EXPORT_SYMBOL_NOVERS(ieee80211_unregister_crypto_ops);
269EXPORT_SYMBOL_NOVERS(ieee80211_get_crypto_ops);
270#endif
271
272module_init(ieee80211_crypto_init);
273module_exit(ieee80211_crypto_deinit);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h
new file mode 100644
index 00000000000..a84df4b7648
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h
@@ -0,0 +1,93 @@
1/*
2 * Original code based on Host AP (software wireless LAN access point) driver
3 * for Intersil Prism2/2.5/3.
4 *
5 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
6 * <jkmaline@cc.hut.fi>
7 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
8 *
9 * Adaption to a generic IEEE 802.11 stack by James Ketrenos
10 * <jketreno@linux.intel.com>
11 *
12 * Copyright (c) 2004, Intel Corporation
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. See README and COPYING for
17 * more details.
18 */
19
20/*
21 * This file defines the interface to the ieee80211 crypto module.
22 */
23#ifndef IEEE80211_CRYPT_H
24#define IEEE80211_CRYPT_H
25
26#include <linux/skbuff.h>
27
28struct ieee80211_crypto_ops {
29 const char *name;
30
31 /* init new crypto context (e.g., allocate private data space,
32 * select IV, etc.); returns NULL on failure or pointer to allocated
33 * private data on success */
34 void * (*init)(int keyidx);
35
36 /* deinitialize crypto context and free allocated private data */
37 void (*deinit)(void *priv);
38
39 /* encrypt/decrypt return < 0 on error or >= 0 on success. The return
40 * value from decrypt_mpdu is passed as the keyidx value for
41 * decrypt_msdu. skb must have enough head and tail room for the
42 * encryption; if not, error will be returned; these functions are
43 * called for all MPDUs (i.e., fragments).
44 */
45 int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
46 int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
47
48 /* These functions are called for full MSDUs, i.e. full frames.
49 * These can be NULL if full MSDU operations are not needed. */
50 int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv);
51 int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len,
52 void *priv);
53
54 int (*set_key)(void *key, int len, u8 *seq, void *priv);
55 int (*get_key)(void *key, int len, u8 *seq, void *priv);
56
57 /* procfs handler for printing out key information and possible
58 * statistics */
59 char * (*print_stats)(char *p, void *priv);
60
61 /* maximum number of bytes added by encryption; encrypt buf is
62 * allocated with extra_prefix_len bytes, copy of in_buf, and
63 * extra_postfix_len; encrypt need not use all this space, but
64 * the result must start at the beginning of the buffer and correct
65 * length must be returned */
66 int extra_prefix_len, extra_postfix_len;
67
68 struct module *owner;
69};
70
71struct ieee80211_crypt_data {
72 struct list_head list; /* delayed deletion list */
73 struct ieee80211_crypto_ops *ops;
74 void *priv;
75 atomic_t refcnt;
76};
77
78int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops);
79int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops);
80struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name);
81void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int);
82void ieee80211_crypt_deinit_handler(unsigned long);
83void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
84 struct ieee80211_crypt_data **crypt);
85#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
86#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
87#endif
88#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31))
89#define crypto_alloc_tfm crypto_alloc_tfm_rsl
90#define crypto_free_tfm crypto_free_tfm_rsl
91#endif
92
93#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c
new file mode 100644
index 00000000000..a86c26eceb3
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c
@@ -0,0 +1,534 @@
1/*
2 * Host AP crypt: host-based CCMP encryption implementation for Host AP driver
3 *
4 * Copyright (c) 2003-2004, Jouni Malinen <jkmaline@cc.hut.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. See README and COPYING for
9 * more details.
10 */
11
12//#include <linux/config.h>
13#include <linux/version.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/random.h>
18#include <linux/skbuff.h>
19#include <linux/netdevice.h>
20#include <linux/if_ether.h>
21#include <linux/if_arp.h>
22#include <asm/string.h>
23#include <linux/wireless.h>
24
25#include "ieee80211.h"
26
27#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
28#include "rtl_crypto.h"
29#else
30#include <linux/crypto.h>
31#endif
32
33#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
34 #include <asm/scatterlist.h>
35#else
36 #include <linux/scatterlist.h>
37#endif
38//#include <asm/scatterlist.h>
39
40MODULE_AUTHOR("Jouni Malinen");
41MODULE_DESCRIPTION("Host AP crypt: CCMP");
42MODULE_LICENSE("GPL");
43
44#ifndef OPENSUSE_SLED
45#define OPENSUSE_SLED 0
46#endif
47
48#define AES_BLOCK_LEN 16
49#define CCMP_HDR_LEN 8
50#define CCMP_MIC_LEN 8
51#define CCMP_TK_LEN 16
52#define CCMP_PN_LEN 6
53
54struct ieee80211_ccmp_data {
55 u8 key[CCMP_TK_LEN];
56 int key_set;
57
58 u8 tx_pn[CCMP_PN_LEN];
59 u8 rx_pn[CCMP_PN_LEN];
60
61 u32 dot11RSNAStatsCCMPFormatErrors;
62 u32 dot11RSNAStatsCCMPReplays;
63 u32 dot11RSNAStatsCCMPDecryptErrors;
64
65 int key_idx;
66
67 struct crypto_tfm *tfm;
68
69 /* scratch buffers for virt_to_page() (crypto API) */
70 u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],
71 tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];
72 u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];
73};
74
75void ieee80211_ccmp_aes_encrypt(struct crypto_tfm *tfm,
76 const u8 pt[16], u8 ct[16])
77{
78#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
79 struct scatterlist src, dst;
80
81 src.page = virt_to_page(pt);
82 src.offset = offset_in_page(pt);
83 src.length = AES_BLOCK_LEN;
84
85 dst.page = virt_to_page(ct);
86 dst.offset = offset_in_page(ct);
87 dst.length = AES_BLOCK_LEN;
88
89 crypto_cipher_encrypt(tfm, &dst, &src, AES_BLOCK_LEN);
90#else
91 crypto_cipher_encrypt_one((void*)tfm, ct, pt);
92#endif
93}
94
95static void * ieee80211_ccmp_init(int key_idx)
96{
97 struct ieee80211_ccmp_data *priv;
98
99 priv = kmalloc(sizeof(*priv), GFP_ATOMIC);
100 if (priv == NULL)
101 goto fail;
102 memset(priv, 0, sizeof(*priv));
103 priv->key_idx = key_idx;
104
105#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
106 priv->tfm = crypto_alloc_tfm("aes", 0);
107 if (priv->tfm == NULL) {
108 printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate "
109 "crypto API aes\n");
110 goto fail;
111 }
112 #else
113 priv->tfm = (void*)crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC);
114 if (IS_ERR(priv->tfm)) {
115 printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate "
116 "crypto API aes\n");
117 priv->tfm = NULL;
118 goto fail;
119 }
120 #endif
121 return priv;
122
123fail:
124 if (priv) {
125 if (priv->tfm)
126 #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
127 crypto_free_tfm(priv->tfm);
128 #else
129 crypto_free_cipher((void*)priv->tfm);
130 #endif
131 kfree(priv);
132 }
133
134 return NULL;
135}
136
137
138static void ieee80211_ccmp_deinit(void *priv)
139{
140 struct ieee80211_ccmp_data *_priv = priv;
141 if (_priv && _priv->tfm)
142#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
143 crypto_free_tfm(_priv->tfm);
144#else
145 crypto_free_cipher((void*)_priv->tfm);
146#endif
147 kfree(priv);
148}
149
150
151static inline void xor_block(u8 *b, u8 *a, size_t len)
152{
153 int i;
154 for (i = 0; i < len; i++)
155 b[i] ^= a[i];
156}
157
158
159
160static void ccmp_init_blocks(struct crypto_tfm *tfm,
161 struct ieee80211_hdr_4addr *hdr,
162 u8 *pn, size_t dlen, u8 *b0, u8 *auth,
163 u8 *s0)
164{
165 u8 *pos, qc = 0;
166 size_t aad_len;
167 u16 fc;
168 int a4_included, qc_included;
169 u8 aad[2 * AES_BLOCK_LEN];
170
171 fc = le16_to_cpu(hdr->frame_ctl);
172 a4_included = ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) ==
173 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS));
174 /*
175 qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) &&
176 (WLAN_FC_GET_STYPE(fc) & 0x08));
177 */
178 // fixed by David :2006.9.6
179 qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) &&
180 (WLAN_FC_GET_STYPE(fc) & 0x80));
181 aad_len = 22;
182 if (a4_included)
183 aad_len += 6;
184 if (qc_included) {
185 pos = (u8 *) &hdr->addr4;
186 if (a4_included)
187 pos += 6;
188 qc = *pos & 0x0f;
189 aad_len += 2;
190 }
191 /* CCM Initial Block:
192 * Flag (Include authentication header, M=3 (8-octet MIC),
193 * L=1 (2-octet Dlen))
194 * Nonce: 0x00 | A2 | PN
195 * Dlen */
196 b0[0] = 0x59;
197 b0[1] = qc;
198 memcpy(b0 + 2, hdr->addr2, ETH_ALEN);
199 memcpy(b0 + 8, pn, CCMP_PN_LEN);
200 b0[14] = (dlen >> 8) & 0xff;
201 b0[15] = dlen & 0xff;
202
203 /* AAD:
204 * FC with bits 4..6 and 11..13 masked to zero; 14 is always one
205 * A1 | A2 | A3
206 * SC with bits 4..15 (seq#) masked to zero
207 * A4 (if present)
208 * QC (if present)
209 */
210 pos = (u8 *) hdr;
211 aad[0] = 0; /* aad_len >> 8 */
212 aad[1] = aad_len & 0xff;
213 aad[2] = pos[0] & 0x8f;
214 aad[3] = pos[1] & 0xc7;
215 memcpy(aad + 4, hdr->addr1, 3 * ETH_ALEN);
216 pos = (u8 *) &hdr->seq_ctl;
217 aad[22] = pos[0] & 0x0f;
218 aad[23] = 0; /* all bits masked */
219 memset(aad + 24, 0, 8);
220 if (a4_included)
221 memcpy(aad + 24, hdr->addr4, ETH_ALEN);
222 if (qc_included) {
223 aad[a4_included ? 30 : 24] = qc;
224 /* rest of QC masked */
225 }
226
227 /* Start with the first block and AAD */
228 ieee80211_ccmp_aes_encrypt(tfm, b0, auth);
229 xor_block(auth, aad, AES_BLOCK_LEN);
230 ieee80211_ccmp_aes_encrypt(tfm, auth, auth);
231 xor_block(auth, &aad[AES_BLOCK_LEN], AES_BLOCK_LEN);
232 ieee80211_ccmp_aes_encrypt(tfm, auth, auth);
233 b0[0] &= 0x07;
234 b0[14] = b0[15] = 0;
235 ieee80211_ccmp_aes_encrypt(tfm, b0, s0);
236}
237
238
239
240static int ieee80211_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
241{
242 struct ieee80211_ccmp_data *key = priv;
243 int data_len, i;
244 u8 *pos;
245 struct ieee80211_hdr_4addr *hdr;
246 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
247
248 if (skb_headroom(skb) < CCMP_HDR_LEN ||
249 skb_tailroom(skb) < CCMP_MIC_LEN ||
250 skb->len < hdr_len)
251 return -1;
252
253 data_len = skb->len - hdr_len;
254 pos = skb_push(skb, CCMP_HDR_LEN);
255 memmove(pos, pos + CCMP_HDR_LEN, hdr_len);
256 pos += hdr_len;
257// mic = skb_put(skb, CCMP_MIC_LEN);
258
259 i = CCMP_PN_LEN - 1;
260 while (i >= 0) {
261 key->tx_pn[i]++;
262 if (key->tx_pn[i] != 0)
263 break;
264 i--;
265 }
266
267 *pos++ = key->tx_pn[5];
268 *pos++ = key->tx_pn[4];
269 *pos++ = 0;
270 *pos++ = (key->key_idx << 6) | (1 << 5) /* Ext IV included */;
271 *pos++ = key->tx_pn[3];
272 *pos++ = key->tx_pn[2];
273 *pos++ = key->tx_pn[1];
274 *pos++ = key->tx_pn[0];
275
276
277 hdr = (struct ieee80211_hdr_4addr *) skb->data;
278 if (!tcb_desc->bHwSec)
279 {
280 int blocks, last, len;
281 u8 *mic;
282 u8 *b0 = key->tx_b0;
283 u8 *b = key->tx_b;
284 u8 *e = key->tx_e;
285 u8 *s0 = key->tx_s0;
286
287 //mic is moved to here by john
288 mic = skb_put(skb, CCMP_MIC_LEN);
289
290 ccmp_init_blocks(key->tfm, hdr, key->tx_pn, data_len, b0, b, s0);
291
292 blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN;
293 last = data_len % AES_BLOCK_LEN;
294
295 for (i = 1; i <= blocks; i++) {
296 len = (i == blocks && last) ? last : AES_BLOCK_LEN;
297 /* Authentication */
298 xor_block(b, pos, len);
299 ieee80211_ccmp_aes_encrypt(key->tfm, b, b);
300 /* Encryption, with counter */
301 b0[14] = (i >> 8) & 0xff;
302 b0[15] = i & 0xff;
303 ieee80211_ccmp_aes_encrypt(key->tfm, b0, e);
304 xor_block(pos, e, len);
305 pos += len;
306 }
307
308 for (i = 0; i < CCMP_MIC_LEN; i++)
309 mic[i] = b[i] ^ s0[i];
310 }
311 return 0;
312}
313
314
315static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
316{
317 struct ieee80211_ccmp_data *key = priv;
318 u8 keyidx, *pos;
319 struct ieee80211_hdr_4addr *hdr;
320 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
321 u8 pn[6];
322
323 if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) {
324 key->dot11RSNAStatsCCMPFormatErrors++;
325 return -1;
326 }
327
328 hdr = (struct ieee80211_hdr_4addr *) skb->data;
329 pos = skb->data + hdr_len;
330 keyidx = pos[3];
331 if (!(keyidx & (1 << 5))) {
332 if (net_ratelimit()) {
333 printk(KERN_DEBUG "CCMP: received packet without ExtIV"
334 " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2));
335 }
336 key->dot11RSNAStatsCCMPFormatErrors++;
337 return -2;
338 }
339 keyidx >>= 6;
340 if (key->key_idx != keyidx) {
341 printk(KERN_DEBUG "CCMP: RX tkey->key_idx=%d frame "
342 "keyidx=%d priv=%p\n", key->key_idx, keyidx, priv);
343 return -6;
344 }
345 if (!key->key_set) {
346 if (net_ratelimit()) {
347 printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT
348 " with keyid=%d that does not have a configured"
349 " key\n", MAC_ARG(hdr->addr2), keyidx);
350 }
351 return -3;
352 }
353
354 pn[0] = pos[7];
355 pn[1] = pos[6];
356 pn[2] = pos[5];
357 pn[3] = pos[4];
358 pn[4] = pos[1];
359 pn[5] = pos[0];
360 pos += 8;
361
362 if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) {
363 if (net_ratelimit()) {
364 printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT
365 " previous PN %02x%02x%02x%02x%02x%02x "
366 "received PN %02x%02x%02x%02x%02x%02x\n",
367 MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn),
368 MAC_ARG(pn));
369 }
370 key->dot11RSNAStatsCCMPReplays++;
371 return -4;
372 }
373 if (!tcb_desc->bHwSec)
374 {
375 size_t data_len = skb->len - hdr_len - CCMP_HDR_LEN - CCMP_MIC_LEN;
376 u8 *mic = skb->data + skb->len - CCMP_MIC_LEN;
377 u8 *b0 = key->rx_b0;
378 u8 *b = key->rx_b;
379 u8 *a = key->rx_a;
380 int i, blocks, last, len;
381
382
383 ccmp_init_blocks(key->tfm, hdr, pn, data_len, b0, a, b);
384 xor_block(mic, b, CCMP_MIC_LEN);
385
386 blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN;
387 last = data_len % AES_BLOCK_LEN;
388
389 for (i = 1; i <= blocks; i++) {
390 len = (i == blocks && last) ? last : AES_BLOCK_LEN;
391 /* Decrypt, with counter */
392 b0[14] = (i >> 8) & 0xff;
393 b0[15] = i & 0xff;
394 ieee80211_ccmp_aes_encrypt(key->tfm, b0, b);
395 xor_block(pos, b, len);
396 /* Authentication */
397 xor_block(a, pos, len);
398 ieee80211_ccmp_aes_encrypt(key->tfm, a, a);
399 pos += len;
400 }
401
402 if (memcmp(mic, a, CCMP_MIC_LEN) != 0) {
403 if (net_ratelimit()) {
404 printk(KERN_DEBUG "CCMP: decrypt failed: STA="
405 MAC_FMT "\n", MAC_ARG(hdr->addr2));
406 }
407 key->dot11RSNAStatsCCMPDecryptErrors++;
408 return -5;
409 }
410
411 memcpy(key->rx_pn, pn, CCMP_PN_LEN);
412 }
413 /* Remove hdr and MIC */
414 memmove(skb->data + CCMP_HDR_LEN, skb->data, hdr_len);
415 skb_pull(skb, CCMP_HDR_LEN);
416 skb_trim(skb, skb->len - CCMP_MIC_LEN);
417
418 return keyidx;
419}
420
421
422static int ieee80211_ccmp_set_key(void *key, int len, u8 *seq, void *priv)
423{
424 struct ieee80211_ccmp_data *data = priv;
425 int keyidx;
426 struct crypto_tfm *tfm = data->tfm;
427
428 keyidx = data->key_idx;
429 memset(data, 0, sizeof(*data));
430 data->key_idx = keyidx;
431 data->tfm = tfm;
432 if (len == CCMP_TK_LEN) {
433 memcpy(data->key, key, CCMP_TK_LEN);
434 data->key_set = 1;
435 if (seq) {
436 data->rx_pn[0] = seq[5];
437 data->rx_pn[1] = seq[4];
438 data->rx_pn[2] = seq[3];
439 data->rx_pn[3] = seq[2];
440 data->rx_pn[4] = seq[1];
441 data->rx_pn[5] = seq[0];
442 }
443 crypto_cipher_setkey((void*)data->tfm, data->key, CCMP_TK_LEN);
444 } else if (len == 0)
445 data->key_set = 0;
446 else
447 return -1;
448
449 return 0;
450}
451
452
453static int ieee80211_ccmp_get_key(void *key, int len, u8 *seq, void *priv)
454{
455 struct ieee80211_ccmp_data *data = priv;
456
457 if (len < CCMP_TK_LEN)
458 return -1;
459
460 if (!data->key_set)
461 return 0;
462 memcpy(key, data->key, CCMP_TK_LEN);
463
464 if (seq) {
465 seq[0] = data->tx_pn[5];
466 seq[1] = data->tx_pn[4];
467 seq[2] = data->tx_pn[3];
468 seq[3] = data->tx_pn[2];
469 seq[4] = data->tx_pn[1];
470 seq[5] = data->tx_pn[0];
471 }
472
473 return CCMP_TK_LEN;
474}
475
476
477static char * ieee80211_ccmp_print_stats(char *p, void *priv)
478{
479 struct ieee80211_ccmp_data *ccmp = priv;
480 p += sprintf(p, "key[%d] alg=CCMP key_set=%d "
481 "tx_pn=%02x%02x%02x%02x%02x%02x "
482 "rx_pn=%02x%02x%02x%02x%02x%02x "
483 "format_errors=%d replays=%d decrypt_errors=%d\n",
484 ccmp->key_idx, ccmp->key_set,
485 MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn),
486 ccmp->dot11RSNAStatsCCMPFormatErrors,
487 ccmp->dot11RSNAStatsCCMPReplays,
488 ccmp->dot11RSNAStatsCCMPDecryptErrors);
489
490 return p;
491}
492
493void ieee80211_ccmp_null(void)
494{
495// printk("============>%s()\n", __FUNCTION__);
496 return;
497}
498
499static struct ieee80211_crypto_ops ieee80211_crypt_ccmp = {
500 .name = "CCMP",
501 .init = ieee80211_ccmp_init,
502 .deinit = ieee80211_ccmp_deinit,
503 .encrypt_mpdu = ieee80211_ccmp_encrypt,
504 .decrypt_mpdu = ieee80211_ccmp_decrypt,
505 .encrypt_msdu = NULL,
506 .decrypt_msdu = NULL,
507 .set_key = ieee80211_ccmp_set_key,
508 .get_key = ieee80211_ccmp_get_key,
509 .print_stats = ieee80211_ccmp_print_stats,
510 .extra_prefix_len = CCMP_HDR_LEN,
511 .extra_postfix_len = CCMP_MIC_LEN,
512 .owner = THIS_MODULE,
513};
514
515
516static int __init ieee80211_crypto_ccmp_init(void)
517{
518 return ieee80211_register_crypto_ops(&ieee80211_crypt_ccmp);
519}
520
521
522static void __exit ieee80211_crypto_ccmp_exit(void)
523{
524 ieee80211_unregister_crypto_ops(&ieee80211_crypt_ccmp);
525}
526
527#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
528EXPORT_SYMBOL(ieee80211_ccmp_null);
529#else
530EXPORT_SYMBOL_NOVERS(ieee80211_ccmp_null);
531#endif
532
533module_init(ieee80211_crypto_ccmp_init);
534module_exit(ieee80211_crypto_ccmp_exit);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c
new file mode 100644
index 00000000000..b031b649524
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c
@@ -0,0 +1,1034 @@
1/*
2 * Host AP crypt: host-based TKIP encryption implementation for Host AP driver
3 *
4 * Copyright (c) 2003-2004, Jouni Malinen <jkmaline@cc.hut.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. See README and COPYING for
9 * more details.
10 */
11
12//#include <linux/config.h>
13#include <linux/version.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/random.h>
18#include <linux/skbuff.h>
19#include <linux/netdevice.h>
20#include <linux/if_ether.h>
21#include <linux/if_arp.h>
22#include <asm/string.h>
23
24#include "ieee80211.h"
25#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20))
26//#include "crypto_compat.h"
27#endif
28
29
30#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
31#include "rtl_crypto.h"
32#else
33#include <linux/crypto.h>
34#endif
35//#include <asm/scatterlist.h>
36#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
37 #include <asm/scatterlist.h>
38#else
39 #include <linux/scatterlist.h>
40#endif
41
42#include <linux/crc32.h>
43
44MODULE_AUTHOR("Jouni Malinen");
45MODULE_DESCRIPTION("Host AP crypt: TKIP");
46MODULE_LICENSE("GPL");
47
48#ifndef OPENSUSE_SLED
49#define OPENSUSE_SLED 0
50#endif
51
52struct ieee80211_tkip_data {
53#define TKIP_KEY_LEN 32
54 u8 key[TKIP_KEY_LEN];
55 int key_set;
56
57 u32 tx_iv32;
58 u16 tx_iv16;
59 u16 tx_ttak[5];
60 int tx_phase1_done;
61
62 u32 rx_iv32;
63 u16 rx_iv16;
64 u16 rx_ttak[5];
65 int rx_phase1_done;
66 u32 rx_iv32_new;
67 u16 rx_iv16_new;
68
69 u32 dot11RSNAStatsTKIPReplays;
70 u32 dot11RSNAStatsTKIPICVErrors;
71 u32 dot11RSNAStatsTKIPLocalMICFailures;
72
73 int key_idx;
74#if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED))
75 struct crypto_blkcipher *rx_tfm_arc4;
76 struct crypto_hash *rx_tfm_michael;
77 struct crypto_blkcipher *tx_tfm_arc4;
78 struct crypto_hash *tx_tfm_michael;
79#else
80 struct crypto_tfm *tx_tfm_arc4;
81 struct crypto_tfm *tx_tfm_michael;
82 struct crypto_tfm *rx_tfm_arc4;
83 struct crypto_tfm *rx_tfm_michael;
84#endif
85 /* scratch buffers for virt_to_page() (crypto API) */
86 u8 rx_hdr[16], tx_hdr[16];
87};
88
89static void * ieee80211_tkip_init(int key_idx)
90{
91 struct ieee80211_tkip_data *priv;
92
93 priv = kmalloc(sizeof(*priv), GFP_ATOMIC);
94 if (priv == NULL)
95 goto fail;
96 memset(priv, 0, sizeof(*priv));
97 priv->key_idx = key_idx;
98#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
99 priv->tx_tfm_arc4 = crypto_alloc_tfm("arc4", 0);
100 if (priv->tx_tfm_arc4 == NULL) {
101 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
102 "crypto API arc4\n");
103 goto fail;
104 }
105
106 priv->tx_tfm_michael = crypto_alloc_tfm("michael_mic", 0);
107 if (priv->tx_tfm_michael == NULL) {
108 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
109 "crypto API michael_mic\n");
110 goto fail;
111 }
112
113 priv->rx_tfm_arc4 = crypto_alloc_tfm("arc4", 0);
114 if (priv->rx_tfm_arc4 == NULL) {
115 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
116 "crypto API arc4\n");
117 goto fail;
118 }
119
120 priv->rx_tfm_michael = crypto_alloc_tfm("michael_mic", 0);
121 if (priv->rx_tfm_michael == NULL) {
122 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
123 "crypto API michael_mic\n");
124 goto fail;
125 }
126#else
127 priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0,
128 CRYPTO_ALG_ASYNC);
129 if (IS_ERR(priv->tx_tfm_arc4)) {
130 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
131 "crypto API arc4\n");
132 priv->tx_tfm_arc4 = NULL;
133 goto fail;
134 }
135
136 priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0,
137 CRYPTO_ALG_ASYNC);
138 if (IS_ERR(priv->tx_tfm_michael)) {
139 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
140 "crypto API michael_mic\n");
141 priv->tx_tfm_michael = NULL;
142 goto fail;
143 }
144
145 priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0,
146 CRYPTO_ALG_ASYNC);
147 if (IS_ERR(priv->rx_tfm_arc4)) {
148 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
149 "crypto API arc4\n");
150 priv->rx_tfm_arc4 = NULL;
151 goto fail;
152 }
153
154 priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0,
155 CRYPTO_ALG_ASYNC);
156 if (IS_ERR(priv->rx_tfm_michael)) {
157 printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate "
158 "crypto API michael_mic\n");
159 priv->rx_tfm_michael = NULL;
160 goto fail;
161 }
162#endif
163 return priv;
164
165fail:
166 if (priv) {
167#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
168 if (priv->tx_tfm_michael)
169 crypto_free_tfm(priv->tx_tfm_michael);
170 if (priv->tx_tfm_arc4)
171 crypto_free_tfm(priv->tx_tfm_arc4);
172 if (priv->rx_tfm_michael)
173 crypto_free_tfm(priv->rx_tfm_michael);
174 if (priv->rx_tfm_arc4)
175 crypto_free_tfm(priv->rx_tfm_arc4);
176
177#else
178 if (priv->tx_tfm_michael)
179 crypto_free_hash(priv->tx_tfm_michael);
180 if (priv->tx_tfm_arc4)
181 crypto_free_blkcipher(priv->tx_tfm_arc4);
182 if (priv->rx_tfm_michael)
183 crypto_free_hash(priv->rx_tfm_michael);
184 if (priv->rx_tfm_arc4)
185 crypto_free_blkcipher(priv->rx_tfm_arc4);
186#endif
187 kfree(priv);
188 }
189
190 return NULL;
191}
192
193
194static void ieee80211_tkip_deinit(void *priv)
195{
196 struct ieee80211_tkip_data *_priv = priv;
197#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
198 if (_priv->tx_tfm_michael)
199 crypto_free_tfm(_priv->tx_tfm_michael);
200 if (_priv->tx_tfm_arc4)
201 crypto_free_tfm(_priv->tx_tfm_arc4);
202 if (_priv->rx_tfm_michael)
203 crypto_free_tfm(_priv->rx_tfm_michael);
204 if (_priv->rx_tfm_arc4)
205 crypto_free_tfm(_priv->rx_tfm_arc4);
206#else
207 if (_priv) {
208 if (_priv->tx_tfm_michael)
209 crypto_free_hash(_priv->tx_tfm_michael);
210 if (_priv->tx_tfm_arc4)
211 crypto_free_blkcipher(_priv->tx_tfm_arc4);
212 if (_priv->rx_tfm_michael)
213 crypto_free_hash(_priv->rx_tfm_michael);
214 if (_priv->rx_tfm_arc4)
215 crypto_free_blkcipher(_priv->rx_tfm_arc4);
216 }
217#endif
218 kfree(priv);
219}
220
221
222static inline u16 RotR1(u16 val)
223{
224 return (val >> 1) | (val << 15);
225}
226
227
228static inline u8 Lo8(u16 val)
229{
230 return val & 0xff;
231}
232
233
234static inline u8 Hi8(u16 val)
235{
236 return val >> 8;
237}
238
239
240static inline u16 Lo16(u32 val)
241{
242 return val & 0xffff;
243}
244
245
246static inline u16 Hi16(u32 val)
247{
248 return val >> 16;
249}
250
251
252static inline u16 Mk16(u8 hi, u8 lo)
253{
254 return lo | (((u16) hi) << 8);
255}
256
257
258static inline u16 Mk16_le(u16 *v)
259{
260 return le16_to_cpu(*v);
261}
262
263
264static const u16 Sbox[256] =
265{
266 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
267 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
268 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
269 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
270 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
271 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
272 0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
273 0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
274 0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
275 0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
276 0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
277 0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
278 0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
279 0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
280 0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
281 0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
282 0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
283 0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
284 0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
285 0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
286 0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
287 0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
288 0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
289 0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
290 0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
291 0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
292 0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
293 0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
294 0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
295 0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
296 0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
297 0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
298};
299
300
301static inline u16 _S_(u16 v)
302{
303 u16 t = Sbox[Hi8(v)];
304 return Sbox[Lo8(v)] ^ ((t << 8) | (t >> 8));
305}
306
307
308#define PHASE1_LOOP_COUNT 8
309
310
311static void tkip_mixing_phase1(u16 *TTAK, const u8 *TK, const u8 *TA, u32 IV32)
312{
313 int i, j;
314
315 /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */
316 TTAK[0] = Lo16(IV32);
317 TTAK[1] = Hi16(IV32);
318 TTAK[2] = Mk16(TA[1], TA[0]);
319 TTAK[3] = Mk16(TA[3], TA[2]);
320 TTAK[4] = Mk16(TA[5], TA[4]);
321
322 for (i = 0; i < PHASE1_LOOP_COUNT; i++) {
323 j = 2 * (i & 1);
324 TTAK[0] += _S_(TTAK[4] ^ Mk16(TK[1 + j], TK[0 + j]));
325 TTAK[1] += _S_(TTAK[0] ^ Mk16(TK[5 + j], TK[4 + j]));
326 TTAK[2] += _S_(TTAK[1] ^ Mk16(TK[9 + j], TK[8 + j]));
327 TTAK[3] += _S_(TTAK[2] ^ Mk16(TK[13 + j], TK[12 + j]));
328 TTAK[4] += _S_(TTAK[3] ^ Mk16(TK[1 + j], TK[0 + j])) + i;
329 }
330}
331
332
333static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK,
334 u16 IV16)
335{
336 /* Make temporary area overlap WEP seed so that the final copy can be
337 * avoided on little endian hosts. */
338 u16 *PPK = (u16 *) &WEPSeed[4];
339
340 /* Step 1 - make copy of TTAK and bring in TSC */
341 PPK[0] = TTAK[0];
342 PPK[1] = TTAK[1];
343 PPK[2] = TTAK[2];
344 PPK[3] = TTAK[3];
345 PPK[4] = TTAK[4];
346 PPK[5] = TTAK[4] + IV16;
347
348 /* Step 2 - 96-bit bijective mixing using S-box */
349 PPK[0] += _S_(PPK[5] ^ Mk16_le((u16 *) &TK[0]));
350 PPK[1] += _S_(PPK[0] ^ Mk16_le((u16 *) &TK[2]));
351 PPK[2] += _S_(PPK[1] ^ Mk16_le((u16 *) &TK[4]));
352 PPK[3] += _S_(PPK[2] ^ Mk16_le((u16 *) &TK[6]));
353 PPK[4] += _S_(PPK[3] ^ Mk16_le((u16 *) &TK[8]));
354 PPK[5] += _S_(PPK[4] ^ Mk16_le((u16 *) &TK[10]));
355
356 PPK[0] += RotR1(PPK[5] ^ Mk16_le((u16 *) &TK[12]));
357 PPK[1] += RotR1(PPK[0] ^ Mk16_le((u16 *) &TK[14]));
358 PPK[2] += RotR1(PPK[1]);
359 PPK[3] += RotR1(PPK[2]);
360 PPK[4] += RotR1(PPK[3]);
361 PPK[5] += RotR1(PPK[4]);
362
363 /* Step 3 - bring in last of TK bits, assign 24-bit WEP IV value
364 * WEPSeed[0..2] is transmitted as WEP IV */
365 WEPSeed[0] = Hi8(IV16);
366 WEPSeed[1] = (Hi8(IV16) | 0x20) & 0x7F;
367 WEPSeed[2] = Lo8(IV16);
368 WEPSeed[3] = Lo8((PPK[5] ^ Mk16_le((u16 *) &TK[0])) >> 1);
369
370#ifdef __BIG_ENDIAN
371 {
372 int i;
373 for (i = 0; i < 6; i++)
374 PPK[i] = (PPK[i] << 8) | (PPK[i] >> 8);
375 }
376#endif
377}
378
379
380static int ieee80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
381{
382 struct ieee80211_tkip_data *tkey = priv;
383 int len;
384 u8 *pos;
385 struct ieee80211_hdr_4addr *hdr;
386 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
387
388 #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED))
389 struct blkcipher_desc desc = {.tfm = tkey->tx_tfm_arc4};
390 int ret = 0;
391 #endif
392 u8 rc4key[16], *icv;
393 u32 crc;
394 struct scatterlist sg;
395
396 if (skb_headroom(skb) < 8 || skb_tailroom(skb) < 4 ||
397 skb->len < hdr_len)
398 return -1;
399
400 hdr = (struct ieee80211_hdr_4addr *) skb->data;
401
402#if 0
403printk("@@ tkey\n");
404printk("%x|", ((u32*)tkey->key)[0]);
405printk("%x|", ((u32*)tkey->key)[1]);
406printk("%x|", ((u32*)tkey->key)[2]);
407printk("%x|", ((u32*)tkey->key)[3]);
408printk("%x|", ((u32*)tkey->key)[4]);
409printk("%x|", ((u32*)tkey->key)[5]);
410printk("%x|", ((u32*)tkey->key)[6]);
411printk("%x\n", ((u32*)tkey->key)[7]);
412#endif
413
414 if (!tcb_desc->bHwSec)
415 {
416 if (!tkey->tx_phase1_done) {
417 tkip_mixing_phase1(tkey->tx_ttak, tkey->key, hdr->addr2,
418 tkey->tx_iv32);
419 tkey->tx_phase1_done = 1;
420 }
421 tkip_mixing_phase2(rc4key, tkey->key, tkey->tx_ttak, tkey->tx_iv16);
422 }
423 else
424 tkey->tx_phase1_done = 1;
425
426
427 len = skb->len - hdr_len;
428 pos = skb_push(skb, 8);
429 memmove(pos, pos + 8, hdr_len);
430 pos += hdr_len;
431
432 if (tcb_desc->bHwSec)
433 {
434 *pos++ = Hi8(tkey->tx_iv16);
435 *pos++ = (Hi8(tkey->tx_iv16) | 0x20) & 0x7F;
436 *pos++ = Lo8(tkey->tx_iv16);
437 }
438 else
439 {
440 *pos++ = rc4key[0];
441 *pos++ = rc4key[1];
442 *pos++ = rc4key[2];
443 }
444
445 *pos++ = (tkey->key_idx << 6) | (1 << 5) /* Ext IV included */;
446 *pos++ = tkey->tx_iv32 & 0xff;
447 *pos++ = (tkey->tx_iv32 >> 8) & 0xff;
448 *pos++ = (tkey->tx_iv32 >> 16) & 0xff;
449 *pos++ = (tkey->tx_iv32 >> 24) & 0xff;
450
451 if (!tcb_desc->bHwSec)
452 {
453 icv = skb_put(skb, 4);
454#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
455 crc = ~crc32_le(~0, pos, len);
456#else
457 crc = ~ether_crc_le(len, pos);
458#endif
459 icv[0] = crc;
460 icv[1] = crc >> 8;
461 icv[2] = crc >> 16;
462 icv[3] = crc >> 24;
463#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
464 crypto_cipher_setkey(tkey->tx_tfm_arc4, rc4key, 16);
465 sg.page = virt_to_page(pos);
466 sg.offset = offset_in_page(pos);
467 sg.length = len + 4;
468 crypto_cipher_encrypt(tkey->tx_tfm_arc4, &sg, &sg, len + 4);
469#else
470 crypto_blkcipher_setkey(tkey->tx_tfm_arc4, rc4key, 16);
471#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
472 sg.page = virt_to_page(pos);
473 sg.offset = offset_in_page(pos);
474 sg.length = len + 4;
475#else
476 sg_init_one(&sg, pos, len+4);
477#endif
478 ret= crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4);
479#endif
480
481 }
482
483 tkey->tx_iv16++;
484 if (tkey->tx_iv16 == 0) {
485 tkey->tx_phase1_done = 0;
486 tkey->tx_iv32++;
487 }
488
489 if (!tcb_desc->bHwSec)
490#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
491 return 0;
492 #else
493 return ret;
494 #endif
495 else
496 return 0;
497
498
499}
500
501static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
502{
503 struct ieee80211_tkip_data *tkey = priv;
504 u8 keyidx, *pos;
505 u32 iv32;
506 u16 iv16;
507 struct ieee80211_hdr_4addr *hdr;
508 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
509 #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED))
510 struct blkcipher_desc desc = {.tfm = tkey->rx_tfm_arc4};
511 #endif
512 u8 rc4key[16];
513 u8 icv[4];
514 u32 crc;
515 struct scatterlist sg;
516 int plen;
517 if (skb->len < hdr_len + 8 + 4)
518 return -1;
519
520 hdr = (struct ieee80211_hdr_4addr *) skb->data;
521 pos = skb->data + hdr_len;
522 keyidx = pos[3];
523 if (!(keyidx & (1 << 5))) {
524 if (net_ratelimit()) {
525 printk(KERN_DEBUG "TKIP: received packet without ExtIV"
526 " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2));
527 }
528 return -2;
529 }
530 keyidx >>= 6;
531 if (tkey->key_idx != keyidx) {
532 printk(KERN_DEBUG "TKIP: RX tkey->key_idx=%d frame "
533 "keyidx=%d priv=%p\n", tkey->key_idx, keyidx, priv);
534 return -6;
535 }
536 if (!tkey->key_set) {
537 if (net_ratelimit()) {
538 printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT
539 " with keyid=%d that does not have a configured"
540 " key\n", MAC_ARG(hdr->addr2), keyidx);
541 }
542 return -3;
543 }
544 iv16 = (pos[0] << 8) | pos[2];
545 iv32 = pos[4] | (pos[5] << 8) | (pos[6] << 16) | (pos[7] << 24);
546 pos += 8;
547
548 if (!tcb_desc->bHwSec)
549 {
550 if (iv32 < tkey->rx_iv32 ||
551 (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) {
552 if (net_ratelimit()) {
553 printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT
554 " previous TSC %08x%04x received TSC "
555 "%08x%04x\n", MAC_ARG(hdr->addr2),
556 tkey->rx_iv32, tkey->rx_iv16, iv32, iv16);
557 }
558 tkey->dot11RSNAStatsTKIPReplays++;
559 return -4;
560 }
561
562 if (iv32 != tkey->rx_iv32 || !tkey->rx_phase1_done) {
563 tkip_mixing_phase1(tkey->rx_ttak, tkey->key, hdr->addr2, iv32);
564 tkey->rx_phase1_done = 1;
565 }
566 tkip_mixing_phase2(rc4key, tkey->key, tkey->rx_ttak, iv16);
567
568 plen = skb->len - hdr_len - 12;
569
570#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
571 crypto_cipher_setkey(tkey->rx_tfm_arc4, rc4key, 16);
572 sg.page = virt_to_page(pos);
573 sg.offset = offset_in_page(pos);
574 sg.length = plen + 4;
575 crypto_cipher_decrypt(tkey->rx_tfm_arc4, &sg, &sg, plen + 4);
576#else
577 crypto_blkcipher_setkey(tkey->rx_tfm_arc4, rc4key, 16);
578#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
579 sg.page = virt_to_page(pos);
580 sg.offset = offset_in_page(pos);
581 sg.length = plen + 4;
582#else
583 sg_init_one(&sg, pos, plen+4);
584#endif
585 if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) {
586 if (net_ratelimit()) {
587 printk(KERN_DEBUG ": TKIP: failed to decrypt "
588 "received packet from " MAC_FMT "\n",
589 MAC_ARG(hdr->addr2));
590 }
591 return -7;
592 }
593#endif
594
595 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
596 crc = ~crc32_le(~0, pos, plen);
597 #else
598 crc = ~ether_crc_le(plen, pos);
599 #endif
600 icv[0] = crc;
601 icv[1] = crc >> 8;
602 icv[2] = crc >> 16;
603 icv[3] = crc >> 24;
604
605 if (memcmp(icv, pos + plen, 4) != 0) {
606 if (iv32 != tkey->rx_iv32) {
607 /* Previously cached Phase1 result was already lost, so
608 * it needs to be recalculated for the next packet. */
609 tkey->rx_phase1_done = 0;
610 }
611 if (net_ratelimit()) {
612 printk(KERN_DEBUG "TKIP: ICV error detected: STA="
613 MAC_FMT "\n", MAC_ARG(hdr->addr2));
614 }
615 tkey->dot11RSNAStatsTKIPICVErrors++;
616 return -5;
617 }
618
619 }
620
621 /* Update real counters only after Michael MIC verification has
622 * completed */
623 tkey->rx_iv32_new = iv32;
624 tkey->rx_iv16_new = iv16;
625
626 /* Remove IV and ICV */
627 memmove(skb->data + 8, skb->data, hdr_len);
628 skb_pull(skb, 8);
629 skb_trim(skb, skb->len - 4);
630
631//john's test
632#ifdef JOHN_DUMP
633if( ((u16*)skb->data)[0] & 0x4000){
634 printk("@@ rx decrypted skb->data");
635 int i;
636 for(i=0;i<skb->len;i++){
637 if( (i%24)==0 ) printk("\n");
638 printk("%2x ", ((u8*)skb->data)[i]);
639 }
640 printk("\n");
641}
642#endif /*JOHN_DUMP*/
643 return keyidx;
644}
645
646
647#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
648static int michael_mic(struct crypto_tfm * tfm_michael, u8 *key, u8 *hdr,
649 u8 *data, size_t data_len, u8 *mic)
650{
651 struct scatterlist sg[2];
652#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
653 struct hash_desc desc;
654 int ret = 0;
655#endif
656
657 if (tfm_michael == NULL){
658 printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n");
659 return -1;
660 }
661 sg[0].page = virt_to_page(hdr);
662 sg[0].offset = offset_in_page(hdr);
663 sg[0].length = 16;
664
665 sg[1].page = virt_to_page(data);
666 sg[1].offset = offset_in_page(data);
667 sg[1].length = data_len;
668
669
670#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
671 crypto_digest_init(tfm_michael);
672 crypto_digest_setkey(tfm_michael, key, 8);
673 crypto_digest_update(tfm_michael, sg, 2);
674 crypto_digest_final(tfm_michael, mic);
675 return 0;
676#else
677if (crypto_hash_setkey(tkey->tfm_michael, key, 8))
678 return -1;
679
680// return 0;
681 desc.tfm = tkey->tfm_michael;
682 desc.flags = 0;
683 ret = crypto_hash_digest(&desc, sg, data_len + 16, mic);
684 return ret;
685#endif
686}
687#else
688static int michael_mic(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr,
689 u8 * data, size_t data_len, u8 * mic)
690{
691 struct hash_desc desc;
692 struct scatterlist sg[2];
693
694 if (tfm_michael == NULL) {
695 printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n");
696 return -1;
697 }
698#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
699 sg[0].page = virt_to_page(hdr);
700 sg[0].offset = offset_in_page(hdr);
701 sg[0].length = 16;
702
703 sg[1].page = virt_to_page(data);
704 sg[1].offset = offset_in_page(data);
705 sg[1].length = data_len;
706#else
707 sg_init_table(sg, 2);
708 sg_set_buf(&sg[0], hdr, 16);
709 sg_set_buf(&sg[1], data, data_len);
710#endif
711
712 if (crypto_hash_setkey(tfm_michael, key, 8))
713 return -1;
714
715 desc.tfm = tfm_michael;
716 desc.flags = 0;
717 return crypto_hash_digest(&desc, sg, data_len + 16, mic);
718}
719#endif
720
721
722
723static void michael_mic_hdr(struct sk_buff *skb, u8 *hdr)
724{
725 struct ieee80211_hdr_4addr *hdr11;
726
727 hdr11 = (struct ieee80211_hdr_4addr *) skb->data;
728 switch (le16_to_cpu(hdr11->frame_ctl) &
729 (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) {
730 case IEEE80211_FCTL_TODS:
731 memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */
732 memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */
733 break;
734 case IEEE80211_FCTL_FROMDS:
735 memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */
736 memcpy(hdr + ETH_ALEN, hdr11->addr3, ETH_ALEN); /* SA */
737 break;
738 case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS:
739 memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */
740 memcpy(hdr + ETH_ALEN, hdr11->addr4, ETH_ALEN); /* SA */
741 break;
742 case 0:
743 memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */
744 memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */
745 break;
746 }
747
748 hdr[12] = 0; /* priority */
749
750 hdr[13] = hdr[14] = hdr[15] = 0; /* reserved */
751}
752
753
754static int ieee80211_michael_mic_add(struct sk_buff *skb, int hdr_len, void *priv)
755{
756 struct ieee80211_tkip_data *tkey = priv;
757 u8 *pos;
758 struct ieee80211_hdr_4addr *hdr;
759
760 hdr = (struct ieee80211_hdr_4addr *) skb->data;
761
762 if (skb_tailroom(skb) < 8 || skb->len < hdr_len) {
763 printk(KERN_DEBUG "Invalid packet for Michael MIC add "
764 "(tailroom=%d hdr_len=%d skb->len=%d)\n",
765 skb_tailroom(skb), hdr_len, skb->len);
766 return -1;
767 }
768
769 michael_mic_hdr(skb, tkey->tx_hdr);
770
771 // { david, 2006.9.1
772 // fix the wpa process with wmm enabled.
773 if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) {
774 tkey->tx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07;
775 }
776 // }
777 pos = skb_put(skb, 8);
778#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
779 if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr,
780 skb->data + hdr_len, skb->len - 8 - hdr_len, pos))
781#else
782 if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr,
783 skb->data + hdr_len, skb->len - 8 - hdr_len, pos))
784#endif
785 return -1;
786
787 return 0;
788}
789
790
791#if WIRELESS_EXT >= 18
792static void ieee80211_michael_mic_failure(struct net_device *dev,
793 struct ieee80211_hdr_4addr *hdr,
794 int keyidx)
795{
796 union iwreq_data wrqu;
797 struct iw_michaelmicfailure ev;
798
799 /* TODO: needed parameters: count, keyid, key type, TSC */
800 memset(&ev, 0, sizeof(ev));
801 ev.flags = keyidx & IW_MICFAILURE_KEY_ID;
802 if (hdr->addr1[0] & 0x01)
803 ev.flags |= IW_MICFAILURE_GROUP;
804 else
805 ev.flags |= IW_MICFAILURE_PAIRWISE;
806 ev.src_addr.sa_family = ARPHRD_ETHER;
807 memcpy(ev.src_addr.sa_data, hdr->addr2, ETH_ALEN);
808 memset(&wrqu, 0, sizeof(wrqu));
809 wrqu.data.length = sizeof(ev);
810 wireless_send_event(dev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev);
811}
812#elif WIRELESS_EXT >= 15
813static void ieee80211_michael_mic_failure(struct net_device *dev,
814 struct ieee80211_hdr_4addr *hdr,
815 int keyidx)
816{
817 union iwreq_data wrqu;
818 char buf[128];
819
820 /* TODO: needed parameters: count, keyid, key type, TSC */
821 sprintf(buf, "MLME-MICHAELMICFAILURE.indication(keyid=%d %scast addr="
822 MAC_FMT ")", keyidx, hdr->addr1[0] & 0x01 ? "broad" : "uni",
823 MAC_ARG(hdr->addr2));
824 memset(&wrqu, 0, sizeof(wrqu));
825 wrqu.data.length = strlen(buf);
826 wireless_send_event(dev, IWEVCUSTOM, &wrqu, buf);
827}
828#else /* WIRELESS_EXT >= 15 */
829static inline void ieee80211_michael_mic_failure(struct net_device *dev,
830 struct ieee80211_hdr_4addr *hdr,
831 int keyidx)
832{
833}
834#endif /* WIRELESS_EXT >= 15 */
835
836static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx,
837 int hdr_len, void *priv)
838{
839 struct ieee80211_tkip_data *tkey = priv;
840 u8 mic[8];
841 struct ieee80211_hdr_4addr *hdr;
842
843 hdr = (struct ieee80211_hdr_4addr *) skb->data;
844
845 if (!tkey->key_set)
846 return -1;
847
848 michael_mic_hdr(skb, tkey->rx_hdr);
849 // { david, 2006.9.1
850 // fix the wpa process with wmm enabled.
851 if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) {
852 tkey->rx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07;
853 }
854 // }
855
856#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
857 if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr,
858 skb->data + hdr_len, skb->len - 8 - hdr_len, mic))
859#else
860 if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr,
861 skb->data + hdr_len, skb->len - 8 - hdr_len, mic))
862#endif
863 return -1;
864 if (memcmp(mic, skb->data + skb->len - 8, 8) != 0) {
865 struct ieee80211_hdr_4addr *hdr;
866 hdr = (struct ieee80211_hdr_4addr *) skb->data;
867 printk(KERN_DEBUG "%s: Michael MIC verification failed for "
868 "MSDU from " MAC_FMT " keyidx=%d\n",
869 skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2),
870 keyidx);
871 if (skb->dev)
872 ieee80211_michael_mic_failure(skb->dev, hdr, keyidx);
873 tkey->dot11RSNAStatsTKIPLocalMICFailures++;
874 return -1;
875 }
876
877 /* Update TSC counters for RX now that the packet verification has
878 * completed. */
879 tkey->rx_iv32 = tkey->rx_iv32_new;
880 tkey->rx_iv16 = tkey->rx_iv16_new;
881
882 skb_trim(skb, skb->len - 8);
883
884 return 0;
885}
886
887
888static int ieee80211_tkip_set_key(void *key, int len, u8 *seq, void *priv)
889{
890 struct ieee80211_tkip_data *tkey = priv;
891 int keyidx;
892#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
893 struct crypto_tfm *tfm = tkey->tx_tfm_michael;
894 struct crypto_tfm *tfm2 = tkey->tx_tfm_arc4;
895 struct crypto_tfm *tfm3 = tkey->rx_tfm_michael;
896 struct crypto_tfm *tfm4 = tkey->rx_tfm_arc4;
897#else
898 struct crypto_hash *tfm = tkey->tx_tfm_michael;
899 struct crypto_blkcipher *tfm2 = tkey->tx_tfm_arc4;
900 struct crypto_hash *tfm3 = tkey->rx_tfm_michael;
901 struct crypto_blkcipher *tfm4 = tkey->rx_tfm_arc4;
902#endif
903
904 keyidx = tkey->key_idx;
905 memset(tkey, 0, sizeof(*tkey));
906 tkey->key_idx = keyidx;
907#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
908 tkey->tx_tfm_michael = tfm;
909 tkey->tx_tfm_arc4 = tfm2;
910 tkey->rx_tfm_michael = tfm3;
911 tkey->rx_tfm_arc4 = tfm4;
912#else
913 tkey->tx_tfm_michael = tfm;
914 tkey->tx_tfm_arc4 = tfm2;
915 tkey->rx_tfm_michael = tfm3;
916 tkey->rx_tfm_arc4 = tfm4;
917#endif
918
919 if (len == TKIP_KEY_LEN) {
920 memcpy(tkey->key, key, TKIP_KEY_LEN);
921 tkey->key_set = 1;
922 tkey->tx_iv16 = 1; /* TSC is initialized to 1 */
923 if (seq) {
924 tkey->rx_iv32 = (seq[5] << 24) | (seq[4] << 16) |
925 (seq[3] << 8) | seq[2];
926 tkey->rx_iv16 = (seq[1] << 8) | seq[0];
927 }
928 } else if (len == 0)
929 tkey->key_set = 0;
930 else
931 return -1;
932
933 return 0;
934}
935
936
937static int ieee80211_tkip_get_key(void *key, int len, u8 *seq, void *priv)
938{
939 struct ieee80211_tkip_data *tkey = priv;
940
941 if (len < TKIP_KEY_LEN)
942 return -1;
943
944 if (!tkey->key_set)
945 return 0;
946 memcpy(key, tkey->key, TKIP_KEY_LEN);
947
948 if (seq) {
949 /* Return the sequence number of the last transmitted frame. */
950 u16 iv16 = tkey->tx_iv16;
951 u32 iv32 = tkey->tx_iv32;
952 if (iv16 == 0)
953 iv32--;
954 iv16--;
955 seq[0] = tkey->tx_iv16;
956 seq[1] = tkey->tx_iv16 >> 8;
957 seq[2] = tkey->tx_iv32;
958 seq[3] = tkey->tx_iv32 >> 8;
959 seq[4] = tkey->tx_iv32 >> 16;
960 seq[5] = tkey->tx_iv32 >> 24;
961 }
962
963 return TKIP_KEY_LEN;
964}
965
966
967static char * ieee80211_tkip_print_stats(char *p, void *priv)
968{
969 struct ieee80211_tkip_data *tkip = priv;
970 p += sprintf(p, "key[%d] alg=TKIP key_set=%d "
971 "tx_pn=%02x%02x%02x%02x%02x%02x "
972 "rx_pn=%02x%02x%02x%02x%02x%02x "
973 "replays=%d icv_errors=%d local_mic_failures=%d\n",
974 tkip->key_idx, tkip->key_set,
975 (tkip->tx_iv32 >> 24) & 0xff,
976 (tkip->tx_iv32 >> 16) & 0xff,
977 (tkip->tx_iv32 >> 8) & 0xff,
978 tkip->tx_iv32 & 0xff,
979 (tkip->tx_iv16 >> 8) & 0xff,
980 tkip->tx_iv16 & 0xff,
981 (tkip->rx_iv32 >> 24) & 0xff,
982 (tkip->rx_iv32 >> 16) & 0xff,
983 (tkip->rx_iv32 >> 8) & 0xff,
984 tkip->rx_iv32 & 0xff,
985 (tkip->rx_iv16 >> 8) & 0xff,
986 tkip->rx_iv16 & 0xff,
987 tkip->dot11RSNAStatsTKIPReplays,
988 tkip->dot11RSNAStatsTKIPICVErrors,
989 tkip->dot11RSNAStatsTKIPLocalMICFailures);
990 return p;
991}
992
993
994static struct ieee80211_crypto_ops ieee80211_crypt_tkip = {
995 .name = "TKIP",
996 .init = ieee80211_tkip_init,
997 .deinit = ieee80211_tkip_deinit,
998 .encrypt_mpdu = ieee80211_tkip_encrypt,
999 .decrypt_mpdu = ieee80211_tkip_decrypt,
1000 .encrypt_msdu = ieee80211_michael_mic_add,
1001 .decrypt_msdu = ieee80211_michael_mic_verify,
1002 .set_key = ieee80211_tkip_set_key,
1003 .get_key = ieee80211_tkip_get_key,
1004 .print_stats = ieee80211_tkip_print_stats,
1005 .extra_prefix_len = 4 + 4, /* IV + ExtIV */
1006 .extra_postfix_len = 8 + 4, /* MIC + ICV */
1007 .owner = THIS_MODULE,
1008};
1009
1010
1011static int __init ieee80211_crypto_tkip_init(void)
1012{
1013 return ieee80211_register_crypto_ops(&ieee80211_crypt_tkip);
1014}
1015
1016
1017static void __exit ieee80211_crypto_tkip_exit(void)
1018{
1019 ieee80211_unregister_crypto_ops(&ieee80211_crypt_tkip);
1020}
1021
1022void ieee80211_tkip_null(void)
1023{
1024// printk("============>%s()\n", __FUNCTION__);
1025 return;
1026}
1027#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
1028EXPORT_SYMBOL(ieee80211_tkip_null);
1029#else
1030EXPORT_SYMBOL_NOVERS(ieee80211_tkip_null);
1031#endif
1032
1033module_init(ieee80211_crypto_tkip_init);
1034module_exit(ieee80211_crypto_tkip_exit);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c
new file mode 100644
index 00000000000..7e394328ec9
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c
@@ -0,0 +1,397 @@
1/*
2 * Host AP crypt: host-based WEP encryption implementation for Host AP driver
3 *
4 * Copyright (c) 2002-2004, Jouni Malinen <jkmaline@cc.hut.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. See README and COPYING for
9 * more details.
10 */
11
12//#include <linux/config.h>
13#include <linux/version.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/random.h>
18#include <linux/skbuff.h>
19#include <asm/string.h>
20
21#include "ieee80211.h"
22
23#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20))
24//#include "crypto_compat.h"
25#endif
26
27
28#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
29#include "rtl_crypto.h"
30#else
31#include <linux/crypto.h>
32#endif
33
34#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
35 #include <asm/scatterlist.h>
36#else
37 #include <linux/scatterlist.h>
38#endif
39//#include <asm/scatterlist.h>
40#include <linux/crc32.h>
41//
42/*
43#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
44#include "rtl_crypto.h"
45#else
46#include <linux/crypto.h>
47#endif
48
49#include <asm/scatterlist.h>
50#include <linux/crc32.h>
51*/
52MODULE_AUTHOR("Jouni Malinen");
53MODULE_DESCRIPTION("Host AP crypt: WEP");
54MODULE_LICENSE("GPL");
55#ifndef OPENSUSE_SLED
56#define OPENSUSE_SLED 0
57#endif
58
59struct prism2_wep_data {
60 u32 iv;
61#define WEP_KEY_LEN 13
62 u8 key[WEP_KEY_LEN + 1];
63 u8 key_len;
64 u8 key_idx;
65#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
66 struct crypto_tfm *tfm;
67 #else
68 struct crypto_blkcipher *tx_tfm;
69 struct crypto_blkcipher *rx_tfm;
70 #endif
71};
72
73
74static void * prism2_wep_init(int keyidx)
75{
76 struct prism2_wep_data *priv;
77
78 priv = kmalloc(sizeof(*priv), GFP_ATOMIC);
79 if (priv == NULL)
80 goto fail;
81 memset(priv, 0, sizeof(*priv));
82 priv->key_idx = keyidx;
83
84#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
85 priv->tfm = crypto_alloc_tfm("arc4", 0);
86 if (priv->tfm == NULL) {
87 printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate "
88 "crypto API arc4\n");
89 goto fail;
90 }
91 #else
92 priv->tx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
93 if (IS_ERR(priv->tx_tfm)) {
94 printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate "
95 "crypto API arc4\n");
96 priv->tx_tfm = NULL;
97 goto fail;
98 }
99 priv->rx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
100 if (IS_ERR(priv->rx_tfm)) {
101 printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate "
102 "crypto API arc4\n");
103 priv->rx_tfm = NULL;
104 goto fail;
105 }
106 #endif
107
108 /* start WEP IV from a random value */
109 get_random_bytes(&priv->iv, 4);
110
111 return priv;
112
113fail:
114#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
115 if (priv) {
116 if (priv->tfm)
117 crypto_free_tfm(priv->tfm);
118 kfree(priv);
119 }
120 #else
121 if (priv) {
122 if (priv->tx_tfm)
123 crypto_free_blkcipher(priv->tx_tfm);
124 if (priv->rx_tfm)
125 crypto_free_blkcipher(priv->rx_tfm);
126 kfree(priv);
127 }
128 #endif
129 return NULL;
130}
131
132
133static void prism2_wep_deinit(void *priv)
134{
135 struct prism2_wep_data *_priv = priv;
136#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
137 if (_priv && _priv->tfm)
138 crypto_free_tfm(_priv->tfm);
139 #else
140 if (_priv) {
141 if (_priv->tx_tfm)
142 crypto_free_blkcipher(_priv->tx_tfm);
143 if (_priv->rx_tfm)
144 crypto_free_blkcipher(_priv->rx_tfm);
145 }
146 #endif
147 kfree(priv);
148}
149
150/* Perform WEP encryption on given skb that has at least 4 bytes of headroom
151 * for IV and 4 bytes of tailroom for ICV. Both IV and ICV will be transmitted,
152 * so the payload length increases with 8 bytes.
153 *
154 * WEP frame payload: IV + TX key idx, RC4(data), ICV = RC4(CRC32(data))
155 */
156static int prism2_wep_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
157{
158 struct prism2_wep_data *wep = priv;
159 u32 klen, len;
160 u8 key[WEP_KEY_LEN + 3];
161 u8 *pos;
162 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
163 #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED))
164 struct blkcipher_desc desc = {.tfm = wep->tx_tfm};
165 #endif
166 u32 crc;
167 u8 *icv;
168 struct scatterlist sg;
169 if (skb_headroom(skb) < 4 || skb_tailroom(skb) < 4 ||
170 skb->len < hdr_len)
171 return -1;
172
173 len = skb->len - hdr_len;
174 pos = skb_push(skb, 4);
175 memmove(pos, pos + 4, hdr_len);
176 pos += hdr_len;
177
178 klen = 3 + wep->key_len;
179
180 wep->iv++;
181
182 /* Fluhrer, Mantin, and Shamir have reported weaknesses in the key
183 * scheduling algorithm of RC4. At least IVs (KeyByte + 3, 0xff, N)
184 * can be used to speedup attacks, so avoid using them. */
185 if ((wep->iv & 0xff00) == 0xff00) {
186 u8 B = (wep->iv >> 16) & 0xff;
187 if (B >= 3 && B < klen)
188 wep->iv += 0x0100;
189 }
190
191 /* Prepend 24-bit IV to RC4 key and TX frame */
192 *pos++ = key[0] = (wep->iv >> 16) & 0xff;
193 *pos++ = key[1] = (wep->iv >> 8) & 0xff;
194 *pos++ = key[2] = wep->iv & 0xff;
195 *pos++ = wep->key_idx << 6;
196
197 /* Copy rest of the WEP key (the secret part) */
198 memcpy(key + 3, wep->key, wep->key_len);
199
200 if (!tcb_desc->bHwSec)
201 {
202
203 /* Append little-endian CRC32 and encrypt it to produce ICV */
204 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
205 crc = ~crc32_le(~0, pos, len);
206 #else
207 crc = ~ether_crc_le(len, pos);
208 #endif
209 icv = skb_put(skb, 4);
210 icv[0] = crc;
211 icv[1] = crc >> 8;
212 icv[2] = crc >> 16;
213 icv[3] = crc >> 24;
214
215#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
216 crypto_cipher_setkey(wep->tfm, key, klen);
217 sg.page = virt_to_page(pos);
218 sg.offset = offset_in_page(pos);
219 sg.length = len + 4;
220 crypto_cipher_encrypt(wep->tfm, &sg, &sg, len + 4);
221 return 0;
222 #else
223 crypto_blkcipher_setkey(wep->tx_tfm, key, klen);
224 #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
225 sg.page = virt_to_page(pos);
226 sg.offset = offset_in_page(pos);
227 sg.length = len + 4;
228 #else
229 sg_init_one(&sg, pos, len+4);
230 #endif
231 return crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4);
232 #endif
233 }
234
235 return 0;
236}
237
238
239/* Perform WEP decryption on given buffer. Buffer includes whole WEP part of
240 * the frame: IV (4 bytes), encrypted payload (including SNAP header),
241 * ICV (4 bytes). len includes both IV and ICV.
242 *
243 * Returns 0 if frame was decrypted successfully and ICV was correct and -1 on
244 * failure. If frame is OK, IV and ICV will be removed.
245 */
246static int prism2_wep_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
247{
248 struct prism2_wep_data *wep = priv;
249 u32 klen, plen;
250 u8 key[WEP_KEY_LEN + 3];
251 u8 keyidx, *pos;
252 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
253 #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED))
254 struct blkcipher_desc desc = {.tfm = wep->rx_tfm};
255 #endif
256 u32 crc;
257 u8 icv[4];
258 struct scatterlist sg;
259 if (skb->len < hdr_len + 8)
260 return -1;
261
262 pos = skb->data + hdr_len;
263 key[0] = *pos++;
264 key[1] = *pos++;
265 key[2] = *pos++;
266 keyidx = *pos++ >> 6;
267 if (keyidx != wep->key_idx)
268 return -1;
269
270 klen = 3 + wep->key_len;
271
272 /* Copy rest of the WEP key (the secret part) */
273 memcpy(key + 3, wep->key, wep->key_len);
274
275 /* Apply RC4 to data and compute CRC32 over decrypted data */
276 plen = skb->len - hdr_len - 8;
277
278 if (!tcb_desc->bHwSec)
279 {
280#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED))
281 crypto_cipher_setkey(wep->tfm, key, klen);
282 sg.page = virt_to_page(pos);
283 sg.offset = offset_in_page(pos);
284 sg.length = plen + 4;
285 crypto_cipher_decrypt(wep->tfm, &sg, &sg, plen + 4);
286 #else
287 crypto_blkcipher_setkey(wep->rx_tfm, key, klen);
288 #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
289 sg.page = virt_to_page(pos);
290 sg.offset = offset_in_page(pos);
291 sg.length = plen + 4;
292 #else
293 sg_init_one(&sg, pos, plen+4);
294 #endif
295 if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4))
296 return -7;
297 #endif
298 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
299 crc = ~crc32_le(~0, pos, plen);
300 #else
301 crc = ~ether_crc_le(plen, pos);
302 #endif
303 icv[0] = crc;
304 icv[1] = crc >> 8;
305 icv[2] = crc >> 16;
306 icv[3] = crc >> 24;
307 if (memcmp(icv, pos + plen, 4) != 0) {
308 /* ICV mismatch - drop frame */
309 return -2;
310 }
311 }
312 /* Remove IV and ICV */
313 memmove(skb->data + 4, skb->data, hdr_len);
314 skb_pull(skb, 4);
315 skb_trim(skb, skb->len - 4);
316
317 return 0;
318}
319
320
321static int prism2_wep_set_key(void *key, int len, u8 *seq, void *priv)
322{
323 struct prism2_wep_data *wep = priv;
324
325 if (len < 0 || len > WEP_KEY_LEN)
326 return -1;
327
328 memcpy(wep->key, key, len);
329 wep->key_len = len;
330
331 return 0;
332}
333
334
335static int prism2_wep_get_key(void *key, int len, u8 *seq, void *priv)
336{
337 struct prism2_wep_data *wep = priv;
338
339 if (len < wep->key_len)
340 return -1;
341
342 memcpy(key, wep->key, wep->key_len);
343
344 return wep->key_len;
345}
346
347
348static char * prism2_wep_print_stats(char *p, void *priv)
349{
350 struct prism2_wep_data *wep = priv;
351 p += sprintf(p, "key[%d] alg=WEP len=%d\n",
352 wep->key_idx, wep->key_len);
353 return p;
354}
355
356
357static struct ieee80211_crypto_ops ieee80211_crypt_wep = {
358 .name = "WEP",
359 .init = prism2_wep_init,
360 .deinit = prism2_wep_deinit,
361 .encrypt_mpdu = prism2_wep_encrypt,
362 .decrypt_mpdu = prism2_wep_decrypt,
363 .encrypt_msdu = NULL,
364 .decrypt_msdu = NULL,
365 .set_key = prism2_wep_set_key,
366 .get_key = prism2_wep_get_key,
367 .print_stats = prism2_wep_print_stats,
368 .extra_prefix_len = 4, /* IV */
369 .extra_postfix_len = 4, /* ICV */
370 .owner = THIS_MODULE,
371};
372
373
374static int __init ieee80211_crypto_wep_init(void)
375{
376 return ieee80211_register_crypto_ops(&ieee80211_crypt_wep);
377}
378
379
380static void __exit ieee80211_crypto_wep_exit(void)
381{
382 ieee80211_unregister_crypto_ops(&ieee80211_crypt_wep);
383}
384
385void ieee80211_wep_null(void)
386{
387// printk("============>%s()\n", __FUNCTION__);
388 return;
389}
390#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
391EXPORT_SYMBOL(ieee80211_wep_null);
392#else
393EXPORT_SYMBOL_NOVERS(ieee80211_wep_null);
394#endif
395
396module_init(ieee80211_crypto_wep_init);
397module_exit(ieee80211_crypto_wep_exit);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c
new file mode 100644
index 00000000000..f408b4583b8
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c
@@ -0,0 +1,394 @@
1/*******************************************************************************
2
3 Copyright(c) 2004 Intel Corporation. All rights reserved.
4
5 Portions of this file are based on the WEP enablement code provided by the
6 Host AP project hostap-drivers v0.1.3
7 Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
8 <jkmaline@cc.hut.fi>
9 Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of version 2 of the GNU General Public License as
13 published by the Free Software Foundation.
14
15 This program is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 more details.
19
20 You should have received a copy of the GNU General Public License along with
21 this program; if not, write to the Free Software Foundation, Inc., 59
22 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23
24 The full GNU General Public License is included in this distribution in the
25 file called LICENSE.
26
27 Contact Information:
28 James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31*******************************************************************************/
32
33#include <linux/compiler.h>
34//#include <linux/config.h>
35#include <linux/errno.h>
36#include <linux/if_arp.h>
37#include <linux/in6.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/netdevice.h>
43#include <linux/pci.h>
44#include <linux/proc_fs.h>
45#include <linux/skbuff.h>
46#include <linux/slab.h>
47#include <linux/tcp.h>
48#include <linux/types.h>
49#include <linux/version.h>
50#include <linux/wireless.h>
51#include <linux/etherdevice.h>
52#include <asm/uaccess.h>
53#include <net/arp.h>
54
55#include "ieee80211.h"
56
57MODULE_DESCRIPTION("802.11 data/management/control stack");
58MODULE_AUTHOR("Copyright (C) 2004 Intel Corporation <jketreno@linux.intel.com>");
59MODULE_LICENSE("GPL");
60
61#define DRV_NAME "ieee80211"
62
63static inline int ieee80211_networks_allocate(struct ieee80211_device *ieee)
64{
65 if (ieee->networks)
66 return 0;
67
68 ieee->networks = kmalloc(
69 MAX_NETWORK_COUNT * sizeof(struct ieee80211_network),
70 GFP_KERNEL);
71 if (!ieee->networks) {
72 printk(KERN_WARNING "%s: Out of memory allocating beacons\n",
73 ieee->dev->name);
74 return -ENOMEM;
75 }
76
77 memset(ieee->networks, 0,
78 MAX_NETWORK_COUNT * sizeof(struct ieee80211_network));
79
80 return 0;
81}
82
83static inline void ieee80211_networks_free(struct ieee80211_device *ieee)
84{
85 if (!ieee->networks)
86 return;
87 kfree(ieee->networks);
88 ieee->networks = NULL;
89}
90
91static inline void ieee80211_networks_initialize(struct ieee80211_device *ieee)
92{
93 int i;
94
95 INIT_LIST_HEAD(&ieee->network_free_list);
96 INIT_LIST_HEAD(&ieee->network_list);
97 for (i = 0; i < MAX_NETWORK_COUNT; i++)
98 list_add_tail(&ieee->networks[i].list, &ieee->network_free_list);
99}
100
101
102struct net_device *alloc_ieee80211(int sizeof_priv)
103{
104 struct ieee80211_device *ieee;
105 struct net_device *dev;
106 int i,err;
107
108 IEEE80211_DEBUG_INFO("Initializing...\n");
109
110 dev = alloc_etherdev(sizeof(struct ieee80211_device) + sizeof_priv);
111 if (!dev) {
112 IEEE80211_ERROR("Unable to network device.\n");
113 goto failed;
114 }
115
116#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
117 ieee = netdev_priv(dev);
118#else
119 ieee = (struct ieee80211_device *)dev->priv;
120#endif
121 dev->hard_start_xmit = ieee80211_xmit;
122
123 memset(ieee, 0, sizeof(struct ieee80211_device)+sizeof_priv);
124 ieee->dev = dev;
125
126 err = ieee80211_networks_allocate(ieee);
127 if (err) {
128 IEEE80211_ERROR("Unable to allocate beacon storage: %d\n",
129 err);
130 goto failed;
131 }
132 ieee80211_networks_initialize(ieee);
133
134
135 /* Default fragmentation threshold is maximum payload size */
136 ieee->fts = DEFAULT_FTS;
137 ieee->scan_age = DEFAULT_MAX_SCAN_AGE;
138 ieee->open_wep = 1;
139
140 /* Default to enabling full open WEP with host based encrypt/decrypt */
141 ieee->host_encrypt = 1;
142 ieee->host_decrypt = 1;
143 ieee->ieee802_1x = 1; /* Default to supporting 802.1x */
144
145 INIT_LIST_HEAD(&ieee->crypt_deinit_list);
146 init_timer(&ieee->crypt_deinit_timer);
147 ieee->crypt_deinit_timer.data = (unsigned long)ieee;
148 ieee->crypt_deinit_timer.function = ieee80211_crypt_deinit_handler;
149
150 spin_lock_init(&ieee->lock);
151 spin_lock_init(&ieee->wpax_suitlist_lock);
152 spin_lock_init(&ieee->bw_spinlock);
153 spin_lock_init(&ieee->reorder_spinlock);
154 //added by WB
155 atomic_set(&(ieee->atm_chnlop), 0);
156 atomic_set(&(ieee->atm_swbw), 0);
157
158 ieee->wpax_type_set = 0;
159 ieee->wpa_enabled = 0;
160 ieee->tkip_countermeasures = 0;
161 ieee->drop_unencrypted = 0;
162 ieee->privacy_invoked = 0;
163 ieee->ieee802_1x = 1;
164 ieee->raw_tx = 0;
165 //ieee->hwsec_support = 1; //defalt support hw security. //use module_param instead.
166 ieee->hwsec_active = 0; //disable hwsec, switch it on when necessary.
167
168 ieee80211_softmac_init(ieee);
169
170#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
171 ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kzalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL);
172#else
173 ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kmalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL);
174 memset(ieee->pHTInfo,0,sizeof(RT_HIGH_THROUGHPUT));
175#endif
176 if (ieee->pHTInfo == NULL)
177 {
178 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for HTInfo\n");
179 return NULL;
180 }
181 HTUpdateDefaultSetting(ieee);
182 HTInitializeHTInfo(ieee); //may move to other place.
183 TSInitialize(ieee);
184#if 0
185#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
186 INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq);
187#else
188 INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq, ieee);
189#endif
190#endif
191 for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++)
192 INIT_LIST_HEAD(&ieee->ibss_mac_hash[i]);
193
194 for (i = 0; i < 17; i++) {
195 ieee->last_rxseq_num[i] = -1;
196 ieee->last_rxfrag_num[i] = -1;
197 ieee->last_packet_time[i] = 0;
198 }
199
200//These function were added to load crypte module autoly
201 ieee80211_tkip_null();
202 ieee80211_wep_null();
203 ieee80211_ccmp_null();
204
205 return dev;
206
207 failed:
208 if (dev)
209#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
210 free_netdev(dev);
211#else
212 kfree(dev);
213#endif
214 return NULL;
215}
216
217
218void free_ieee80211(struct net_device *dev)
219{
220#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
221 struct ieee80211_device *ieee = netdev_priv(dev);
222#else
223 struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv;
224#endif
225 int i;
226 //struct list_head *p, *q;
227// del_timer_sync(&ieee->SwBwTimer);
228#if 1
229 if (ieee->pHTInfo != NULL)
230 {
231 kfree(ieee->pHTInfo);
232 ieee->pHTInfo = NULL;
233 }
234#endif
235 RemoveAllTS(ieee);
236 ieee80211_softmac_free(ieee);
237 del_timer_sync(&ieee->crypt_deinit_timer);
238 ieee80211_crypt_deinit_entries(ieee, 1);
239
240 for (i = 0; i < WEP_KEYS; i++) {
241 struct ieee80211_crypt_data *crypt = ieee->crypt[i];
242 if (crypt) {
243 if (crypt->ops) {
244 crypt->ops->deinit(crypt->priv);
245#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
246 module_put(crypt->ops->owner);
247#else
248 __MOD_DEC_USE_COUNT(crypt->ops->owner);
249#endif
250 }
251 kfree(crypt);
252 ieee->crypt[i] = NULL;
253 }
254 }
255
256 ieee80211_networks_free(ieee);
257#if 0
258 for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) {
259 list_for_each_safe(p, q, &ieee->ibss_mac_hash[i]) {
260 kfree(list_entry(p, struct ieee_ibss_seq, list));
261 list_del(p);
262 }
263 }
264
265#endif
266#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
267 free_netdev(dev);
268#else
269 kfree(dev);
270#endif
271}
272
273#ifdef CONFIG_IEEE80211_DEBUG
274
275u32 ieee80211_debug_level = 0;
276static int debug = \
277 // IEEE80211_DL_INFO |
278 // IEEE80211_DL_WX |
279 // IEEE80211_DL_SCAN |
280 // IEEE80211_DL_STATE |
281 // IEEE80211_DL_MGMT |
282 // IEEE80211_DL_FRAG |
283 // IEEE80211_DL_EAP |
284 // IEEE80211_DL_DROP |
285 // IEEE80211_DL_TX |
286 // IEEE80211_DL_RX |
287 //IEEE80211_DL_QOS |
288 // IEEE80211_DL_HT |
289 // IEEE80211_DL_TS |
290// IEEE80211_DL_BA |
291 // IEEE80211_DL_REORDER|
292// IEEE80211_DL_TRACE |
293 //IEEE80211_DL_DATA |
294 IEEE80211_DL_ERR //awayls open this flags to show error out
295 ;
296struct proc_dir_entry *ieee80211_proc = NULL;
297
298static int show_debug_level(char *page, char **start, off_t offset,
299 int count, int *eof, void *data)
300{
301 return snprintf(page, count, "0x%08X\n", ieee80211_debug_level);
302}
303
304static int store_debug_level(struct file *file, const char *buffer,
305 unsigned long count, void *data)
306{
307 char buf[] = "0x00000000";
308 unsigned long len = min(sizeof(buf) - 1, (u32)count);
309 char *p = (char *)buf;
310 unsigned long val;
311
312 if (copy_from_user(buf, buffer, len))
313 return count;
314 buf[len] = 0;
315 if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
316 p++;
317 if (p[0] == 'x' || p[0] == 'X')
318 p++;
319 val = simple_strtoul(p, &p, 16);
320 } else
321 val = simple_strtoul(p, &p, 10);
322 if (p == buf)
323 printk(KERN_INFO DRV_NAME
324 ": %s is not in hex or decimal form.\n", buf);
325 else
326 ieee80211_debug_level = val;
327
328 return strnlen(buf, count);
329}
330
331static int __init ieee80211_init(void)
332{
333 struct proc_dir_entry *e;
334
335 ieee80211_debug_level = debug;
336#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
337 ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, proc_net);
338#else
339 ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, init_net.proc_net);
340#endif
341 if (ieee80211_proc == NULL) {
342 IEEE80211_ERROR("Unable to create " DRV_NAME
343 " proc directory\n");
344 return -EIO;
345 }
346 e = create_proc_entry("debug_level", S_IFREG | S_IRUGO | S_IWUSR,
347 ieee80211_proc);
348 if (!e) {
349#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
350 remove_proc_entry(DRV_NAME, proc_net);
351#else
352 remove_proc_entry(DRV_NAME, init_net.proc_net);
353#endif
354 ieee80211_proc = NULL;
355 return -EIO;
356 }
357 e->read_proc = show_debug_level;
358 e->write_proc = store_debug_level;
359 e->data = NULL;
360
361 return 0;
362}
363
364static void __exit ieee80211_exit(void)
365{
366 if (ieee80211_proc) {
367 remove_proc_entry("debug_level", ieee80211_proc);
368#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
369 remove_proc_entry(DRV_NAME, proc_net);
370#else
371 remove_proc_entry(DRV_NAME, init_net.proc_net);
372#endif
373 ieee80211_proc = NULL;
374 }
375}
376
377#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
378#include <linux/moduleparam.h>
379module_param(debug, int, 0444);
380MODULE_PARM_DESC(debug, "debug output mask");
381
382
383module_exit(ieee80211_exit);
384module_init(ieee80211_init);
385#endif
386#endif
387
388#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
389EXPORT_SYMBOL(alloc_ieee80211);
390EXPORT_SYMBOL(free_ieee80211);
391#else
392EXPORT_SYMBOL_NOVERS(alloc_ieee80211);
393EXPORT_SYMBOL_NOVERS(free_ieee80211);
394#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c
new file mode 100644
index 00000000000..2b2ffd34bc9
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c
@@ -0,0 +1,2832 @@
1/*
2 * Original code based Host AP (software wireless LAN access point) driver
3 * for Intersil Prism2/2.5/3 - hostap.o module, common routines
4 *
5 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
6 * <jkmaline@cc.hut.fi>
7 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
8 * Copyright (c) 2004, Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. See README and COPYING for
13 * more details.
14 ******************************************************************************
15
16 Few modifications for Realtek's Wi-Fi drivers by
17 Andrea Merello <andreamrl@tiscali.it>
18
19 A special thanks goes to Realtek for their support !
20
21******************************************************************************/
22
23
24#include <linux/compiler.h>
25//#include <linux/config.h>
26#include <linux/errno.h>
27#include <linux/if_arp.h>
28#include <linux/in6.h>
29#include <linux/in.h>
30#include <linux/ip.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/netdevice.h>
34#include <linux/pci.h>
35#include <linux/proc_fs.h>
36#include <linux/skbuff.h>
37#include <linux/slab.h>
38#include <linux/tcp.h>
39#include <linux/types.h>
40#include <linux/version.h>
41#include <linux/wireless.h>
42#include <linux/etherdevice.h>
43#include <asm/uaccess.h>
44#include <linux/ctype.h>
45
46#include "ieee80211.h"
47#ifdef ENABLE_DOT11D
48#include "dot11d.h"
49#endif
50static inline void ieee80211_monitor_rx(struct ieee80211_device *ieee,
51 struct sk_buff *skb,
52 struct ieee80211_rx_stats *rx_stats)
53{
54 struct ieee80211_hdr_4addr *hdr = (struct ieee80211_hdr_4addr *)skb->data;
55 u16 fc = le16_to_cpu(hdr->frame_ctl);
56
57 skb->dev = ieee->dev;
58#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
59 skb_reset_mac_header(skb);
60#else
61 skb->mac.raw = skb->data;
62#endif
63
64 skb_pull(skb, ieee80211_get_hdrlen(fc));
65 skb->pkt_type = PACKET_OTHERHOST;
66 skb->protocol = __constant_htons(ETH_P_80211_RAW);
67 memset(skb->cb, 0, sizeof(skb->cb));
68 netif_rx(skb);
69}
70
71
72/* Called only as a tasklet (software IRQ) */
73static struct ieee80211_frag_entry *
74ieee80211_frag_cache_find(struct ieee80211_device *ieee, unsigned int seq,
75 unsigned int frag, u8 tid,u8 *src, u8 *dst)
76{
77 struct ieee80211_frag_entry *entry;
78 int i;
79
80 for (i = 0; i < IEEE80211_FRAG_CACHE_LEN; i++) {
81 entry = &ieee->frag_cache[tid][i];
82 if (entry->skb != NULL &&
83 time_after(jiffies, entry->first_frag_time + 2 * HZ)) {
84 IEEE80211_DEBUG_FRAG(
85 "expiring fragment cache entry "
86 "seq=%u last_frag=%u\n",
87 entry->seq, entry->last_frag);
88 dev_kfree_skb_any(entry->skb);
89 entry->skb = NULL;
90 }
91
92 if (entry->skb != NULL && entry->seq == seq &&
93 (entry->last_frag + 1 == frag || frag == -1) &&
94 memcmp(entry->src_addr, src, ETH_ALEN) == 0 &&
95 memcmp(entry->dst_addr, dst, ETH_ALEN) == 0)
96 return entry;
97 }
98
99 return NULL;
100}
101
102/* Called only as a tasklet (software IRQ) */
103static struct sk_buff *
104ieee80211_frag_cache_get(struct ieee80211_device *ieee,
105 struct ieee80211_hdr_4addr *hdr)
106{
107 struct sk_buff *skb = NULL;
108 u16 fc = le16_to_cpu(hdr->frame_ctl);
109 u16 sc = le16_to_cpu(hdr->seq_ctl);
110 unsigned int frag = WLAN_GET_SEQ_FRAG(sc);
111 unsigned int seq = WLAN_GET_SEQ_SEQ(sc);
112 struct ieee80211_frag_entry *entry;
113 struct ieee80211_hdr_3addrqos *hdr_3addrqos;
114 struct ieee80211_hdr_4addrqos *hdr_4addrqos;
115 u8 tid;
116
117 if (((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) {
118 hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr;
119 tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID;
120 tid = UP2AC(tid);
121 tid ++;
122 } else if (IEEE80211_QOS_HAS_SEQ(fc)) {
123 hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr;
124 tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID;
125 tid = UP2AC(tid);
126 tid ++;
127 } else {
128 tid = 0;
129 }
130
131 if (frag == 0) {
132 /* Reserve enough space to fit maximum frame length */
133 skb = dev_alloc_skb(ieee->dev->mtu +
134 sizeof(struct ieee80211_hdr_4addr) +
135 8 /* LLC */ +
136 2 /* alignment */ +
137 8 /* WEP */ +
138 ETH_ALEN /* WDS */ +
139 (IEEE80211_QOS_HAS_SEQ(fc)?2:0) /* QOS Control */);
140 if (skb == NULL)
141 return NULL;
142
143 entry = &ieee->frag_cache[tid][ieee->frag_next_idx[tid]];
144 ieee->frag_next_idx[tid]++;
145 if (ieee->frag_next_idx[tid] >= IEEE80211_FRAG_CACHE_LEN)
146 ieee->frag_next_idx[tid] = 0;
147
148 if (entry->skb != NULL)
149 dev_kfree_skb_any(entry->skb);
150
151 entry->first_frag_time = jiffies;
152 entry->seq = seq;
153 entry->last_frag = frag;
154 entry->skb = skb;
155 memcpy(entry->src_addr, hdr->addr2, ETH_ALEN);
156 memcpy(entry->dst_addr, hdr->addr1, ETH_ALEN);
157 } else {
158 /* received a fragment of a frame for which the head fragment
159 * should have already been received */
160 entry = ieee80211_frag_cache_find(ieee, seq, frag, tid,hdr->addr2,
161 hdr->addr1);
162 if (entry != NULL) {
163 entry->last_frag = frag;
164 skb = entry->skb;
165 }
166 }
167
168 return skb;
169}
170
171
172/* Called only as a tasklet (software IRQ) */
173static int ieee80211_frag_cache_invalidate(struct ieee80211_device *ieee,
174 struct ieee80211_hdr_4addr *hdr)
175{
176 u16 fc = le16_to_cpu(hdr->frame_ctl);
177 u16 sc = le16_to_cpu(hdr->seq_ctl);
178 unsigned int seq = WLAN_GET_SEQ_SEQ(sc);
179 struct ieee80211_frag_entry *entry;
180 struct ieee80211_hdr_3addrqos *hdr_3addrqos;
181 struct ieee80211_hdr_4addrqos *hdr_4addrqos;
182 u8 tid;
183
184 if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) {
185 hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr;
186 tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID;
187 tid = UP2AC(tid);
188 tid ++;
189 } else if (IEEE80211_QOS_HAS_SEQ(fc)) {
190 hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr;
191 tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID;
192 tid = UP2AC(tid);
193 tid ++;
194 } else {
195 tid = 0;
196 }
197
198 entry = ieee80211_frag_cache_find(ieee, seq, -1, tid,hdr->addr2,
199 hdr->addr1);
200
201 if (entry == NULL) {
202 IEEE80211_DEBUG_FRAG(
203 "could not invalidate fragment cache "
204 "entry (seq=%u)\n", seq);
205 return -1;
206 }
207
208 entry->skb = NULL;
209 return 0;
210}
211
212
213
214/* ieee80211_rx_frame_mgtmt
215 *
216 * Responsible for handling management control frames
217 *
218 * Called by ieee80211_rx */
219static inline int
220ieee80211_rx_frame_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb,
221 struct ieee80211_rx_stats *rx_stats, u16 type,
222 u16 stype)
223{
224 /* On the struct stats definition there is written that
225 * this is not mandatory.... but seems that the probe
226 * response parser uses it
227 */
228 struct ieee80211_hdr_3addr * hdr = (struct ieee80211_hdr_3addr *)skb->data;
229
230 rx_stats->len = skb->len;
231 ieee80211_rx_mgt(ieee,(struct ieee80211_hdr_4addr *)skb->data,rx_stats);
232 //if ((ieee->state == IEEE80211_LINKED) && (memcmp(hdr->addr3, ieee->current_network.bssid, ETH_ALEN)))
233 if ((memcmp(hdr->addr1, ieee->dev->dev_addr, ETH_ALEN)))//use ADDR1 to perform address matching for Management frames
234 {
235 dev_kfree_skb_any(skb);
236 return 0;
237 }
238
239 ieee80211_rx_frame_softmac(ieee, skb, rx_stats, type, stype);
240
241 dev_kfree_skb_any(skb);
242
243 return 0;
244
245 #ifdef NOT_YET
246 if (ieee->iw_mode == IW_MODE_MASTER) {
247 printk(KERN_DEBUG "%s: Master mode not yet suppported.\n",
248 ieee->dev->name);
249 return 0;
250/*
251 hostap_update_sta_ps(ieee, (struct hostap_ieee80211_hdr_4addr *)
252 skb->data);*/
253 }
254
255 if (ieee->hostapd && type == IEEE80211_TYPE_MGMT) {
256 if (stype == WLAN_FC_STYPE_BEACON &&
257 ieee->iw_mode == IW_MODE_MASTER) {
258 struct sk_buff *skb2;
259 /* Process beacon frames also in kernel driver to
260 * update STA(AP) table statistics */
261 skb2 = skb_clone(skb, GFP_ATOMIC);
262 if (skb2)
263 hostap_rx(skb2->dev, skb2, rx_stats);
264 }
265
266 /* send management frames to the user space daemon for
267 * processing */
268 ieee->apdevstats.rx_packets++;
269 ieee->apdevstats.rx_bytes += skb->len;
270 prism2_rx_80211(ieee->apdev, skb, rx_stats, PRISM2_RX_MGMT);
271 return 0;
272 }
273
274 if (ieee->iw_mode == IW_MODE_MASTER) {
275 if (type != WLAN_FC_TYPE_MGMT && type != WLAN_FC_TYPE_CTRL) {
276 printk(KERN_DEBUG "%s: unknown management frame "
277 "(type=0x%02x, stype=0x%02x) dropped\n",
278 skb->dev->name, type, stype);
279 return -1;
280 }
281
282 hostap_rx(skb->dev, skb, rx_stats);
283 return 0;
284 }
285
286 printk(KERN_DEBUG "%s: hostap_rx_frame_mgmt: management frame "
287 "received in non-Host AP mode\n", skb->dev->name);
288 return -1;
289 #endif
290}
291
292
293
294/* See IEEE 802.1H for LLC/SNAP encapsulation/decapsulation */
295/* Ethernet-II snap header (RFC1042 for most EtherTypes) */
296static unsigned char rfc1042_header[] =
297{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
298/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
299static unsigned char bridge_tunnel_header[] =
300{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
301/* No encapsulation header if EtherType < 0x600 (=length) */
302
303/* Called by ieee80211_rx_frame_decrypt */
304static int ieee80211_is_eapol_frame(struct ieee80211_device *ieee,
305 struct sk_buff *skb, size_t hdrlen)
306{
307 struct net_device *dev = ieee->dev;
308 u16 fc, ethertype;
309 struct ieee80211_hdr_4addr *hdr;
310 u8 *pos;
311
312 if (skb->len < 24)
313 return 0;
314
315 hdr = (struct ieee80211_hdr_4addr *) skb->data;
316 fc = le16_to_cpu(hdr->frame_ctl);
317
318 /* check that the frame is unicast frame to us */
319 if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) ==
320 IEEE80211_FCTL_TODS &&
321 memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0 &&
322 memcmp(hdr->addr3, dev->dev_addr, ETH_ALEN) == 0) {
323 /* ToDS frame with own addr BSSID and DA */
324 } else if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) ==
325 IEEE80211_FCTL_FROMDS &&
326 memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0) {
327 /* FromDS frame with own addr as DA */
328 } else
329 return 0;
330
331 if (skb->len < 24 + 8)
332 return 0;
333
334 /* check for port access entity Ethernet type */
335// pos = skb->data + 24;
336 pos = skb->data + hdrlen;
337 ethertype = (pos[6] << 8) | pos[7];
338 if (ethertype == ETH_P_PAE)
339 return 1;
340
341 return 0;
342}
343
344/* Called only as a tasklet (software IRQ), by ieee80211_rx */
345static inline int
346ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb,
347 struct ieee80211_crypt_data *crypt)
348{
349 struct ieee80211_hdr_4addr *hdr;
350 int res, hdrlen;
351
352 if (crypt == NULL || crypt->ops->decrypt_mpdu == NULL)
353 return 0;
354#if 1
355 if (ieee->hwsec_active)
356 {
357 cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE);
358 tcb_desc->bHwSec = 1;
359 }
360#endif
361 hdr = (struct ieee80211_hdr_4addr *) skb->data;
362 hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl));
363
364#ifdef CONFIG_IEEE80211_CRYPT_TKIP
365 if (ieee->tkip_countermeasures &&
366 strcmp(crypt->ops->name, "TKIP") == 0) {
367 if (net_ratelimit()) {
368 printk(KERN_DEBUG "%s: TKIP countermeasures: dropped "
369 "received packet from " MAC_FMT "\n",
370 ieee->dev->name, MAC_ARG(hdr->addr2));
371 }
372 return -1;
373 }
374#endif
375
376 atomic_inc(&crypt->refcnt);
377 res = crypt->ops->decrypt_mpdu(skb, hdrlen, crypt->priv);
378 atomic_dec(&crypt->refcnt);
379 if (res < 0) {
380 IEEE80211_DEBUG_DROP(
381 "decryption failed (SA=" MAC_FMT
382 ") res=%d\n", MAC_ARG(hdr->addr2), res);
383 if (res == -2)
384 IEEE80211_DEBUG_DROP("Decryption failed ICV "
385 "mismatch (key %d)\n",
386 skb->data[hdrlen + 3] >> 6);
387 ieee->ieee_stats.rx_discards_undecryptable++;
388 return -1;
389 }
390
391 return res;
392}
393
394
395/* Called only as a tasklet (software IRQ), by ieee80211_rx */
396static inline int
397ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *skb,
398 int keyidx, struct ieee80211_crypt_data *crypt)
399{
400 struct ieee80211_hdr_4addr *hdr;
401 int res, hdrlen;
402
403 if (crypt == NULL || crypt->ops->decrypt_msdu == NULL)
404 return 0;
405 if (ieee->hwsec_active)
406 {
407 cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE);
408 tcb_desc->bHwSec = 1;
409 }
410
411 hdr = (struct ieee80211_hdr_4addr *) skb->data;
412 hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl));
413
414 atomic_inc(&crypt->refcnt);
415 res = crypt->ops->decrypt_msdu(skb, keyidx, hdrlen, crypt->priv);
416 atomic_dec(&crypt->refcnt);
417 if (res < 0) {
418 printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed"
419 " (SA=" MAC_FMT " keyidx=%d)\n",
420 ieee->dev->name, MAC_ARG(hdr->addr2), keyidx);
421 return -1;
422 }
423
424 return 0;
425}
426
427
428/* this function is stolen from ipw2200 driver*/
429#define IEEE_PACKET_RETRY_TIME (5*HZ)
430static int is_duplicate_packet(struct ieee80211_device *ieee,
431 struct ieee80211_hdr_4addr *header)
432{
433 u16 fc = le16_to_cpu(header->frame_ctl);
434 u16 sc = le16_to_cpu(header->seq_ctl);
435 u16 seq = WLAN_GET_SEQ_SEQ(sc);
436 u16 frag = WLAN_GET_SEQ_FRAG(sc);
437 u16 *last_seq, *last_frag;
438 unsigned long *last_time;
439 struct ieee80211_hdr_3addrqos *hdr_3addrqos;
440 struct ieee80211_hdr_4addrqos *hdr_4addrqos;
441 u8 tid;
442
443
444 //TO2DS and QoS
445 if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) {
446 hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)header;
447 tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID;
448 tid = UP2AC(tid);
449 tid ++;
450 } else if(IEEE80211_QOS_HAS_SEQ(fc)) { //QoS
451 hdr_3addrqos = (struct ieee80211_hdr_3addrqos*)header;
452 tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID;
453 tid = UP2AC(tid);
454 tid ++;
455 } else { // no QoS
456 tid = 0;
457 }
458
459 switch (ieee->iw_mode) {
460 case IW_MODE_ADHOC:
461 {
462 struct list_head *p;
463 struct ieee_ibss_seq *entry = NULL;
464 u8 *mac = header->addr2;
465 int index = mac[5] % IEEE_IBSS_MAC_HASH_SIZE;
466 //for (pos = (head)->next; pos != (head); pos = pos->next)
467 //__list_for_each(p, &ieee->ibss_mac_hash[index]) {
468 list_for_each(p, &ieee->ibss_mac_hash[index]) {
469 entry = list_entry(p, struct ieee_ibss_seq, list);
470 if (!memcmp(entry->mac, mac, ETH_ALEN))
471 break;
472 }
473 // if (memcmp(entry->mac, mac, ETH_ALEN)){
474 if (p == &ieee->ibss_mac_hash[index]) {
475 entry = kmalloc(sizeof(struct ieee_ibss_seq), GFP_ATOMIC);
476 if (!entry) {
477 printk(KERN_WARNING "Cannot malloc new mac entry\n");
478 return 0;
479 }
480 memcpy(entry->mac, mac, ETH_ALEN);
481 entry->seq_num[tid] = seq;
482 entry->frag_num[tid] = frag;
483 entry->packet_time[tid] = jiffies;
484 list_add(&entry->list, &ieee->ibss_mac_hash[index]);
485 return 0;
486 }
487 last_seq = &entry->seq_num[tid];
488 last_frag = &entry->frag_num[tid];
489 last_time = &entry->packet_time[tid];
490 break;
491 }
492
493 case IW_MODE_INFRA:
494 last_seq = &ieee->last_rxseq_num[tid];
495 last_frag = &ieee->last_rxfrag_num[tid];
496 last_time = &ieee->last_packet_time[tid];
497
498 break;
499 default:
500 return 0;
501 }
502
503// if(tid != 0) {
504// printk(KERN_WARNING ":)))))))))))%x %x %x, fc(%x)\n", tid, *last_seq, seq, header->frame_ctl);
505// }
506 if ((*last_seq == seq) &&
507 time_after(*last_time + IEEE_PACKET_RETRY_TIME, jiffies)) {
508 if (*last_frag == frag){
509 //printk(KERN_WARNING "[1] go drop!\n");
510 goto drop;
511
512 }
513 if (*last_frag + 1 != frag)
514 /* out-of-order fragment */
515 //printk(KERN_WARNING "[2] go drop!\n");
516 goto drop;
517 } else
518 *last_seq = seq;
519
520 *last_frag = frag;
521 *last_time = jiffies;
522 return 0;
523
524drop:
525// BUG_ON(!(fc & IEEE80211_FCTL_RETRY));
526// printk("DUP\n");
527
528 return 1;
529}
530bool
531AddReorderEntry(
532 PRX_TS_RECORD pTS,
533 PRX_REORDER_ENTRY pReorderEntry
534 )
535{
536 struct list_head *pList = &pTS->RxPendingPktList;
537#if 1
538 while(pList->next != &pTS->RxPendingPktList)
539 {
540 if( SN_LESS(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) )
541 {
542 pList = pList->next;
543 }
544 else if( SN_EQUAL(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) )
545 {
546 return false;
547 }
548 else
549 {
550 break;
551 }
552 }
553#endif
554 pReorderEntry->List.next = pList->next;
555 pReorderEntry->List.next->prev = &pReorderEntry->List;
556 pReorderEntry->List.prev = pList;
557 pList->next = &pReorderEntry->List;
558
559 return true;
560}
561
562void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index)
563{
564 u8 i = 0 , j=0;
565 u16 ethertype;
566// if(index > 1)
567// IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): hahahahhhh, We indicate packet from reorder list, index is %u\n",__FUNCTION__,index);
568 for(j = 0; j<index; j++)
569 {
570//added by amy for reorder
571 struct ieee80211_rxb* prxb = prxbIndicateArray[j];
572 for(i = 0; i<prxb->nr_subframes; i++) {
573 struct sk_buff *sub_skb = prxb->subframes[i];
574
575 /* convert hdr + possible LLC headers into Ethernet header */
576 ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7];
577 if (sub_skb->len >= 8 &&
578 ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 &&
579 ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) ||
580 memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) {
581 /* remove RFC1042 or Bridge-Tunnel encapsulation and
582 * replace EtherType */
583 skb_pull(sub_skb, SNAP_SIZE);
584 memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN);
585 memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN);
586 } else {
587 u16 len;
588 /* Leave Ethernet header part of hdr and full payload */
589 len = htons(sub_skb->len);
590 memcpy(skb_push(sub_skb, 2), &len, 2);
591 memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN);
592 memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN);
593 }
594 //stats->rx_packets++;
595 //stats->rx_bytes += sub_skb->len;
596
597 /* Indicat the packets to upper layer */
598 if (sub_skb) {
599 //printk("0skb_len(%d)\n", skb->len);
600 sub_skb->protocol = eth_type_trans(sub_skb, ieee->dev);
601 memset(sub_skb->cb, 0, sizeof(sub_skb->cb));
602 sub_skb->dev = ieee->dev;
603 sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */
604 //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */
605 ieee->last_rx_ps_time = jiffies;
606 //printk("1skb_len(%d)\n", skb->len);
607 netif_rx(sub_skb);
608 }
609 }
610 kfree(prxb);
611 prxb = NULL;
612 }
613}
614
615
616void RxReorderIndicatePacket( struct ieee80211_device *ieee,
617 struct ieee80211_rxb* prxb,
618 PRX_TS_RECORD pTS,
619 u16 SeqNum)
620{
621 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
622 PRX_REORDER_ENTRY pReorderEntry = NULL;
623 struct ieee80211_rxb* prxbIndicateArray[REORDER_WIN_SIZE];
624 u8 WinSize = pHTInfo->RxReorderWinSize;
625 u16 WinEnd = (pTS->RxIndicateSeq + WinSize -1)%4096;
626 u8 index = 0;
627 bool bMatchWinStart = false, bPktInBuf = false;
628 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): Seq is %d,pTS->RxIndicateSeq is %d, WinSize is %d\n",__FUNCTION__,SeqNum,pTS->RxIndicateSeq,WinSize);
629#if 0
630 if(!list_empty(&ieee->RxReorder_Unused_List))
631 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): ieee->RxReorder_Unused_List is nut NULL\n");
632#endif
633 /* Rx Reorder initialize condition.*/
634 if(pTS->RxIndicateSeq == 0xffff) {
635 pTS->RxIndicateSeq = SeqNum;
636 }
637
638 /* Drop out the packet which SeqNum is smaller than WinStart */
639 if(SN_LESS(SeqNum, pTS->RxIndicateSeq)) {
640 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packet Drop! IndicateSeq: %d, NewSeq: %d\n",
641 pTS->RxIndicateSeq, SeqNum);
642 pHTInfo->RxReorderDropCounter++;
643 {
644 int i;
645 for(i =0; i < prxb->nr_subframes; i++) {
646 dev_kfree_skb(prxb->subframes[i]);
647 }
648 kfree(prxb);
649 prxb = NULL;
650 }
651 return;
652 }
653
654 /*
655 * Sliding window manipulation. Conditions includes:
656 * 1. Incoming SeqNum is equal to WinStart =>Window shift 1
657 * 2. Incoming SeqNum is larger than the WinEnd => Window shift N
658 */
659 if(SN_EQUAL(SeqNum, pTS->RxIndicateSeq)) {
660 pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096;
661 bMatchWinStart = true;
662 } else if(SN_LESS(WinEnd, SeqNum)) {
663 if(SeqNum >= (WinSize - 1)) {
664 pTS->RxIndicateSeq = SeqNum + 1 -WinSize;
665 } else {
666 pTS->RxIndicateSeq = 4095 - (WinSize - (SeqNum +1)) + 1;
667 }
668 IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Window Shift! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum);
669 }
670
671 /*
672 * Indication process.
673 * After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets
674 * with the SeqNum smaller than latest WinStart and buffer other packets.
675 */
676 /* For Rx Reorder condition:
677 * 1. All packets with SeqNum smaller than WinStart => Indicate
678 * 2. All packets with SeqNum larger than or equal to WinStart => Buffer it.
679 */
680 if(bMatchWinStart) {
681 /* Current packet is going to be indicated.*/
682 IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Packets indication!! IndicateSeq: %d, NewSeq: %d\n",\
683 pTS->RxIndicateSeq, SeqNum);
684 prxbIndicateArray[0] = prxb;
685// printk("========================>%s(): SeqNum is %d\n",__FUNCTION__,SeqNum);
686 index = 1;
687 } else {
688 /* Current packet is going to be inserted into pending list.*/
689 //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): We RX no ordered packed, insert to orderd list\n",__FUNCTION__);
690 if(!list_empty(&ieee->RxReorder_Unused_List)) {
691 pReorderEntry = (PRX_REORDER_ENTRY)list_entry(ieee->RxReorder_Unused_List.next,RX_REORDER_ENTRY,List);
692 list_del_init(&pReorderEntry->List);
693
694 /* Make a reorder entry and insert into a the packet list.*/
695 pReorderEntry->SeqNum = SeqNum;
696 pReorderEntry->prxb = prxb;
697 // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pREorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum);
698
699#if 1
700 if(!AddReorderEntry(pTS, pReorderEntry)) {
701 IEEE80211_DEBUG(IEEE80211_DL_REORDER, "%s(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n",
702 __FUNCTION__, pTS->RxIndicateSeq, SeqNum);
703 list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List);
704 {
705 int i;
706 for(i =0; i < prxb->nr_subframes; i++) {
707 dev_kfree_skb(prxb->subframes[i]);
708 }
709 kfree(prxb);
710 prxb = NULL;
711 }
712 } else {
713 IEEE80211_DEBUG(IEEE80211_DL_REORDER,
714 "Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum);
715 }
716#endif
717 }
718 else {
719 /*
720 * Packets are dropped if there is not enough reorder entries.
721 * This part shall be modified!! We can just indicate all the
722 * packets in buffer and get reorder entries.
723 */
724 IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): There is no reorder entry!! Packet is dropped!!\n");
725 {
726 int i;
727 for(i =0; i < prxb->nr_subframes; i++) {
728 dev_kfree_skb(prxb->subframes[i]);
729 }
730 kfree(prxb);
731 prxb = NULL;
732 }
733 }
734 }
735
736 /* Check if there is any packet need indicate.*/
737 while(!list_empty(&pTS->RxPendingPktList)) {
738 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): start RREORDER indicate\n",__FUNCTION__);
739#if 1
740 pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List);
741 if( SN_LESS(pReorderEntry->SeqNum, pTS->RxIndicateSeq) ||
742 SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq))
743 {
744 /* This protect buffer from overflow. */
745 if(index >= REORDER_WIN_SIZE) {
746 IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Buffer overflow!! \n");
747 bPktInBuf = true;
748 break;
749 }
750
751 list_del_init(&pReorderEntry->List);
752
753 if(SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq))
754 pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096;
755
756 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packets indication!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum);
757 prxbIndicateArray[index] = pReorderEntry->prxb;
758 // printk("========================>%s(): pReorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum);
759 index++;
760
761 list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List);
762 } else {
763 bPktInBuf = true;
764 break;
765 }
766#endif
767 }
768
769 /* Handling pending timer. Set this timer to prevent from long time Rx buffering.*/
770 if(index>0) {
771 // Cancel previous pending timer.
772 if(timer_pending(&pTS->RxPktPendingTimer))
773 {
774 del_timer_sync(&pTS->RxPktPendingTimer);
775 }
776 // del_timer_sync(&pTS->RxPktPendingTimer);
777 pTS->RxTimeoutIndicateSeq = 0xffff;
778
779 // Indicate packets
780 if(index>REORDER_WIN_SIZE){
781 IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n");
782 return;
783 }
784 ieee80211_indicate_packets(ieee, prxbIndicateArray, index);
785 bPktInBuf = false;
786 }
787
788#if 1
789 if(bPktInBuf && pTS->RxTimeoutIndicateSeq==0xffff) {
790 // Set new pending timer.
791 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): SET rx timeout timer\n", __FUNCTION__);
792 pTS->RxTimeoutIndicateSeq = pTS->RxIndicateSeq;
793#if 0
794 if(timer_pending(&pTS->RxPktPendingTimer))
795 del_timer_sync(&pTS->RxPktPendingTimer);
796 pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime);
797 add_timer(&pTS->RxPktPendingTimer);
798#else
799 mod_timer(&pTS->RxPktPendingTimer, jiffies + MSECS(pHTInfo->RxReorderPendingTime));
800#endif
801 }
802#endif
803}
804
805u8 parse_subframe(struct sk_buff *skb,
806 struct ieee80211_rx_stats *rx_stats,
807 struct ieee80211_rxb *rxb,u8* src,u8* dst)
808{
809 struct ieee80211_hdr_3addr *hdr = (struct ieee80211_hdr_3addr* )skb->data;
810 u16 fc = le16_to_cpu(hdr->frame_ctl);
811
812 u16 LLCOffset= sizeof(struct ieee80211_hdr_3addr);
813 u16 ChkLength;
814 bool bIsAggregateFrame = false;
815 u16 nSubframe_Length;
816 u8 nPadding_Length = 0;
817 u16 SeqNum=0;
818
819 struct sk_buff *sub_skb;
820 u8 *data_ptr;
821 /* just for debug purpose */
822 SeqNum = WLAN_GET_SEQ_SEQ(le16_to_cpu(hdr->seq_ctl));
823
824 if((IEEE80211_QOS_HAS_SEQ(fc))&&\
825 (((frameqos *)(skb->data + IEEE80211_3ADDR_LEN))->field.reserved)) {
826 bIsAggregateFrame = true;
827 }
828
829 if(IEEE80211_QOS_HAS_SEQ(fc)) {
830 LLCOffset += 2;
831 }
832
833 if(rx_stats->bContainHTC) {
834 LLCOffset += sHTCLng;
835 }
836 //printk("ChkLength = %d\n", LLCOffset);
837 // Null packet, don't indicate it to upper layer
838 ChkLength = LLCOffset;/* + (Frame_WEP(frame)!=0 ?Adapter->MgntInfo.SecurityInfo.EncryptionHeadOverhead:0);*/
839
840 if( skb->len <= ChkLength ) {
841 return 0;
842 }
843
844 skb_pull(skb, LLCOffset);
845
846 if(!bIsAggregateFrame) {
847 rxb->nr_subframes = 1;
848#ifdef JOHN_NOCPY
849 rxb->subframes[0] = skb;
850#else
851 rxb->subframes[0] = skb_copy(skb, GFP_ATOMIC);
852#endif
853
854 memcpy(rxb->src,src,ETH_ALEN);
855 memcpy(rxb->dst,dst,ETH_ALEN);
856 //IEEE80211_DEBUG_DATA(IEEE80211_DL_RX,skb->data,skb->len);
857 return 1;
858 } else {
859 rxb->nr_subframes = 0;
860 memcpy(rxb->src,src,ETH_ALEN);
861 memcpy(rxb->dst,dst,ETH_ALEN);
862 while(skb->len > ETHERNET_HEADER_SIZE) {
863 /* Offset 12 denote 2 mac address */
864 nSubframe_Length = *((u16*)(skb->data + 12));
865 //==m==>change the length order
866 nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8);
867
868 if(skb->len<(ETHERNET_HEADER_SIZE + nSubframe_Length)) {
869#if 0//cosa
870 RT_ASSERT(
871 (nRemain_Length>=(ETHERNET_HEADER_SIZE + nSubframe_Length)),
872 ("ParseSubframe(): A-MSDU subframe parse error!! Subframe Length: %d\n", nSubframe_Length) );
873#endif
874 printk("%s: A-MSDU parse error!! pRfd->nTotalSubframe : %d\n",\
875 __FUNCTION__,rxb->nr_subframes);
876 printk("%s: A-MSDU parse error!! Subframe Length: %d\n",__FUNCTION__, nSubframe_Length);
877 printk("nRemain_Length is %d and nSubframe_Length is : %d\n",skb->len,nSubframe_Length);
878 printk("The Packet SeqNum is %d\n",SeqNum);
879 return 0;
880 }
881
882 /* move the data point to data content */
883 skb_pull(skb, ETHERNET_HEADER_SIZE);
884
885#ifdef JOHN_NOCPY
886 sub_skb = skb_clone(skb, GFP_ATOMIC);
887 sub_skb->len = nSubframe_Length;
888 sub_skb->tail = sub_skb->data + nSubframe_Length;
889#else
890 /* Allocate new skb for releasing to upper layer */
891 sub_skb = dev_alloc_skb(nSubframe_Length + 12);
892 skb_reserve(sub_skb, 12);
893 data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length);
894 memcpy(data_ptr,skb->data,nSubframe_Length);
895#endif
896 rxb->subframes[rxb->nr_subframes++] = sub_skb;
897 if(rxb->nr_subframes >= MAX_SUBFRAME_COUNT) {
898 IEEE80211_DEBUG_RX("ParseSubframe(): Too many Subframes! Packets dropped!\n");
899 break;
900 }
901 skb_pull(skb,nSubframe_Length);
902
903 if(skb->len != 0) {
904 nPadding_Length = 4 - ((nSubframe_Length + ETHERNET_HEADER_SIZE) % 4);
905 if(nPadding_Length == 4) {
906 nPadding_Length = 0;
907 }
908
909 if(skb->len < nPadding_Length) {
910 return 0;
911 }
912
913 skb_pull(skb,nPadding_Length);
914 }
915 }
916#ifdef JOHN_NOCPY
917 dev_kfree_skb(skb);
918#endif
919 //{just for debug added by david
920 //printk("AMSDU::rxb->nr_subframes = %d\n",rxb->nr_subframes);
921 //}
922 return rxb->nr_subframes;
923 }
924}
925
926/* All received frames are sent to this function. @skb contains the frame in
927 * IEEE 802.11 format, i.e., in the format it was sent over air.
928 * This function is called only as a tasklet (software IRQ). */
929int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
930 struct ieee80211_rx_stats *rx_stats)
931{
932 struct net_device *dev = ieee->dev;
933 struct ieee80211_hdr_4addr *hdr;
934 //struct ieee80211_hdr_3addrqos *hdr;
935
936 size_t hdrlen;
937 u16 fc, type, stype, sc;
938 struct net_device_stats *stats;
939 unsigned int frag;
940 u8 *payload;
941 u16 ethertype;
942 //added by amy for reorder
943 u8 TID = 0;
944 u16 SeqNum = 0;
945 PRX_TS_RECORD pTS = NULL;
946 //bool bIsAggregateFrame = false;
947 //added by amy for reorder
948#ifdef NOT_YET
949 struct net_device *wds = NULL;
950 struct sk_buff *skb2 = NULL;
951 struct net_device *wds = NULL;
952 int frame_authorized = 0;
953 int from_assoc_ap = 0;
954 void *sta = NULL;
955#endif
956// u16 qos_ctl = 0;
957 u8 dst[ETH_ALEN];
958 u8 src[ETH_ALEN];
959 u8 bssid[ETH_ALEN];
960 struct ieee80211_crypt_data *crypt = NULL;
961 int keyidx = 0;
962
963 int i;
964 struct ieee80211_rxb* rxb = NULL;
965 // cheat the the hdr type
966 hdr = (struct ieee80211_hdr_4addr *)skb->data;
967 stats = &ieee->stats;
968
969 if (skb->len < 10) {
970 printk(KERN_INFO "%s: SKB length < 10\n",
971 dev->name);
972 goto rx_dropped;
973 }
974
975 fc = le16_to_cpu(hdr->frame_ctl);
976 type = WLAN_FC_GET_TYPE(fc);
977 stype = WLAN_FC_GET_STYPE(fc);
978 sc = le16_to_cpu(hdr->seq_ctl);
979
980 frag = WLAN_GET_SEQ_FRAG(sc);
981 hdrlen = ieee80211_get_hdrlen(fc);
982
983 if(HTCCheck(ieee, skb->data))
984 {
985 if(net_ratelimit())
986 printk("find HTCControl\n");
987 hdrlen += 4;
988 rx_stats->bContainHTC = 1;
989 }
990
991 //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
992#ifdef NOT_YET
993#if WIRELESS_EXT > 15
994 /* Put this code here so that we avoid duplicating it in all
995 * Rx paths. - Jean II */
996#ifdef IW_WIRELESS_SPY /* defined in iw_handler.h */
997 /* If spy monitoring on */
998 if (iface->spy_data.spy_number > 0) {
999 struct iw_quality wstats;
1000 wstats.level = rx_stats->rssi;
1001 wstats.noise = rx_stats->noise;
1002 wstats.updated = 6; /* No qual value */
1003 /* Update spy records */
1004 wireless_spy_update(dev, hdr->addr2, &wstats);
1005 }
1006#endif /* IW_WIRELESS_SPY */
1007#endif /* WIRELESS_EXT > 15 */
1008 hostap_update_rx_stats(local->ap, hdr, rx_stats);
1009#endif
1010
1011#if WIRELESS_EXT > 15
1012 if (ieee->iw_mode == IW_MODE_MONITOR) {
1013 ieee80211_monitor_rx(ieee, skb, rx_stats);
1014 stats->rx_packets++;
1015 stats->rx_bytes += skb->len;
1016 return 1;
1017 }
1018#endif
1019 if (ieee->host_decrypt) {
1020 int idx = 0;
1021 if (skb->len >= hdrlen + 3)
1022 idx = skb->data[hdrlen + 3] >> 6;
1023 crypt = ieee->crypt[idx];
1024#ifdef NOT_YET
1025 sta = NULL;
1026
1027 /* Use station specific key to override default keys if the
1028 * receiver address is a unicast address ("individual RA"). If
1029 * bcrx_sta_key parameter is set, station specific key is used
1030 * even with broad/multicast targets (this is against IEEE
1031 * 802.11, but makes it easier to use different keys with
1032 * stations that do not support WEP key mapping). */
1033
1034 if (!(hdr->addr1[0] & 0x01) || local->bcrx_sta_key)
1035 (void) hostap_handle_sta_crypto(local, hdr, &crypt,
1036 &sta);
1037#endif
1038
1039 /* allow NULL decrypt to indicate an station specific override
1040 * for default encryption */
1041 if (crypt && (crypt->ops == NULL ||
1042 crypt->ops->decrypt_mpdu == NULL))
1043 crypt = NULL;
1044
1045 if (!crypt && (fc & IEEE80211_FCTL_WEP)) {
1046 /* This seems to be triggered by some (multicast?)
1047 * frames from other than current BSS, so just drop the
1048 * frames silently instead of filling system log with
1049 * these reports. */
1050 IEEE80211_DEBUG_DROP("Decryption failed (not set)"
1051 " (SA=" MAC_FMT ")\n",
1052 MAC_ARG(hdr->addr2));
1053 ieee->ieee_stats.rx_discards_undecryptable++;
1054 goto rx_dropped;
1055 }
1056 }
1057
1058 if (skb->len < IEEE80211_DATA_HDR3_LEN)
1059 goto rx_dropped;
1060
1061 // if QoS enabled, should check the sequence for each of the AC
1062 if( (ieee->pHTInfo->bCurRxReorderEnable == false) || !ieee->current_network.qos_data.active|| !IsDataFrame(skb->data) || IsLegacyDataFrame(skb->data)){
1063 if (is_duplicate_packet(ieee, hdr))
1064 goto rx_dropped;
1065
1066 }
1067 else
1068 {
1069 PRX_TS_RECORD pRxTS = NULL;
1070 #if 0
1071 struct ieee80211_hdr_3addr *hdr;
1072 u16 fc;
1073 hdr = (struct ieee80211_hdr_3addr *)skb->data;
1074 fc = le16_to_cpu(hdr->frame_ctl);
1075 u8 tmp = (fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS);
1076
1077 u8 tid = (*((u8*)skb->data + (((fc& IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))?30:24)))&0xf;
1078 printk("====================>fc:%x, tid:%d, tmp:%d\n", fc, tid, tmp);
1079 //u8 tid = (u8)((frameqos*)(buf + ((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24))->field.tid;
1080 #endif
1081 //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): QOS ENABLE AND RECEIVE QOS DATA , we will get Ts, tid:%d\n",__FUNCTION__, tid);
1082#if 1
1083 if(GetTs(
1084 ieee,
1085 (PTS_COMMON_INFO*) &pRxTS,
1086 hdr->addr2,
1087 (u8)Frame_QoSTID((u8*)(skb->data)),
1088 RX_DIR,
1089 true))
1090 {
1091
1092 // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pRxTS->RxLastFragNum is %d,frag is %d,pRxTS->RxLastSeqNum is %d,seq is %d\n",__FUNCTION__,pRxTS->RxLastFragNum,frag,pRxTS->RxLastSeqNum,WLAN_GET_SEQ_SEQ(sc));
1093 if( (fc & (1<<11)) &&
1094 (frag == pRxTS->RxLastFragNum) &&
1095 (WLAN_GET_SEQ_SEQ(sc) == pRxTS->RxLastSeqNum) )
1096 {
1097 goto rx_dropped;
1098 }
1099 else
1100 {
1101 pRxTS->RxLastFragNum = frag;
1102 pRxTS->RxLastSeqNum = WLAN_GET_SEQ_SEQ(sc);
1103 }
1104 }
1105 else
1106 {
1107 IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s(): No TS!! Skip the check!!\n",__FUNCTION__);
1108 goto rx_dropped;
1109 }
1110 }
1111#endif
1112 if (type == IEEE80211_FTYPE_MGMT) {
1113
1114 #if 0
1115 if ( stype == IEEE80211_STYPE_AUTH &&
1116 fc & IEEE80211_FCTL_WEP && ieee->host_decrypt &&
1117 (keyidx = hostap_rx_frame_decrypt(ieee, skb, crypt)) < 0)
1118 {
1119 printk(KERN_DEBUG "%s: failed to decrypt mgmt::auth "
1120 "from " MAC_FMT "\n", dev->name,
1121 MAC_ARG(hdr->addr2));
1122 /* TODO: could inform hostapd about this so that it
1123 * could send auth failure report */
1124 goto rx_dropped;
1125 }
1126 #endif
1127
1128 //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
1129 if (ieee80211_rx_frame_mgmt(ieee, skb, rx_stats, type, stype))
1130 goto rx_dropped;
1131 else
1132 goto rx_exit;
1133 }
1134
1135 /* Data frame - extract src/dst addresses */
1136 switch (fc & (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) {
1137 case IEEE80211_FCTL_FROMDS:
1138 memcpy(dst, hdr->addr1, ETH_ALEN);
1139 memcpy(src, hdr->addr3, ETH_ALEN);
1140 memcpy(bssid, hdr->addr2, ETH_ALEN);
1141 break;
1142 case IEEE80211_FCTL_TODS:
1143 memcpy(dst, hdr->addr3, ETH_ALEN);
1144 memcpy(src, hdr->addr2, ETH_ALEN);
1145 memcpy(bssid, hdr->addr1, ETH_ALEN);
1146 break;
1147 case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS:
1148 if (skb->len < IEEE80211_DATA_HDR4_LEN)
1149 goto rx_dropped;
1150 memcpy(dst, hdr->addr3, ETH_ALEN);
1151 memcpy(src, hdr->addr4, ETH_ALEN);
1152 memcpy(bssid, ieee->current_network.bssid, ETH_ALEN);
1153 break;
1154 case 0:
1155 memcpy(dst, hdr->addr1, ETH_ALEN);
1156 memcpy(src, hdr->addr2, ETH_ALEN);
1157 memcpy(bssid, hdr->addr3, ETH_ALEN);
1158 break;
1159 }
1160
1161#ifdef NOT_YET
1162 if (hostap_rx_frame_wds(ieee, hdr, fc, &wds))
1163 goto rx_dropped;
1164 if (wds) {
1165 skb->dev = dev = wds;
1166 stats = hostap_get_stats(dev);
1167 }
1168
1169 if (ieee->iw_mode == IW_MODE_MASTER && !wds &&
1170 (fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == IEEE80211_FCTL_FROMDS &&
1171 ieee->stadev &&
1172 memcmp(hdr->addr2, ieee->assoc_ap_addr, ETH_ALEN) == 0) {
1173 /* Frame from BSSID of the AP for which we are a client */
1174 skb->dev = dev = ieee->stadev;
1175 stats = hostap_get_stats(dev);
1176 from_assoc_ap = 1;
1177 }
1178#endif
1179
1180 dev->last_rx = jiffies;
1181
1182#ifdef NOT_YET
1183 if ((ieee->iw_mode == IW_MODE_MASTER ||
1184 ieee->iw_mode == IW_MODE_REPEAT) &&
1185 !from_assoc_ap) {
1186 switch (hostap_handle_sta_rx(ieee, dev, skb, rx_stats,
1187 wds != NULL)) {
1188 case AP_RX_CONTINUE_NOT_AUTHORIZED:
1189 frame_authorized = 0;
1190 break;
1191 case AP_RX_CONTINUE:
1192 frame_authorized = 1;
1193 break;
1194 case AP_RX_DROP:
1195 goto rx_dropped;
1196 case AP_RX_EXIT:
1197 goto rx_exit;
1198 }
1199 }
1200#endif
1201 //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
1202 /* Nullfunc frames may have PS-bit set, so they must be passed to
1203 * hostap_handle_sta_rx() before being dropped here. */
1204 if (stype != IEEE80211_STYPE_DATA &&
1205 stype != IEEE80211_STYPE_DATA_CFACK &&
1206 stype != IEEE80211_STYPE_DATA_CFPOLL &&
1207 stype != IEEE80211_STYPE_DATA_CFACKPOLL&&
1208 stype != IEEE80211_STYPE_QOS_DATA//add by David,2006.8.4
1209 ) {
1210 if (stype != IEEE80211_STYPE_NULLFUNC)
1211 IEEE80211_DEBUG_DROP(
1212 "RX: dropped data frame "
1213 "with no data (type=0x%02x, "
1214 "subtype=0x%02x, len=%d)\n",
1215 type, stype, skb->len);
1216 goto rx_dropped;
1217 }
1218 if (memcmp(bssid, ieee->current_network.bssid, ETH_ALEN))
1219 goto rx_dropped;
1220
1221 /* skb: hdr + (possibly fragmented, possibly encrypted) payload */
1222
1223 if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) &&
1224 (keyidx = ieee80211_rx_frame_decrypt(ieee, skb, crypt)) < 0)
1225 {
1226 printk("decrypt frame error\n");
1227 goto rx_dropped;
1228 }
1229
1230
1231 hdr = (struct ieee80211_hdr_4addr *) skb->data;
1232
1233 /* skb: hdr + (possibly fragmented) plaintext payload */
1234 // PR: FIXME: hostap has additional conditions in the "if" below:
1235 // ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) &&
1236 if ((frag != 0 || (fc & IEEE80211_FCTL_MOREFRAGS))) {
1237 int flen;
1238 struct sk_buff *frag_skb = ieee80211_frag_cache_get(ieee, hdr);
1239 IEEE80211_DEBUG_FRAG("Rx Fragment received (%u)\n", frag);
1240
1241 if (!frag_skb) {
1242 IEEE80211_DEBUG(IEEE80211_DL_RX | IEEE80211_DL_FRAG,
1243 "Rx cannot get skb from fragment "
1244 "cache (morefrag=%d seq=%u frag=%u)\n",
1245 (fc & IEEE80211_FCTL_MOREFRAGS) != 0,
1246 WLAN_GET_SEQ_SEQ(sc), frag);
1247 goto rx_dropped;
1248 }
1249 flen = skb->len;
1250 if (frag != 0)
1251 flen -= hdrlen;
1252
1253 if (frag_skb->tail + flen > frag_skb->end) {
1254 printk(KERN_WARNING "%s: host decrypted and "
1255 "reassembled frame did not fit skb\n",
1256 dev->name);
1257 ieee80211_frag_cache_invalidate(ieee, hdr);
1258 goto rx_dropped;
1259 }
1260
1261 if (frag == 0) {
1262 /* copy first fragment (including full headers) into
1263 * beginning of the fragment cache skb */
1264 memcpy(skb_put(frag_skb, flen), skb->data, flen);
1265 } else {
1266 /* append frame payload to the end of the fragment
1267 * cache skb */
1268 memcpy(skb_put(frag_skb, flen), skb->data + hdrlen,
1269 flen);
1270 }
1271 dev_kfree_skb_any(skb);
1272 skb = NULL;
1273
1274 if (fc & IEEE80211_FCTL_MOREFRAGS) {
1275 /* more fragments expected - leave the skb in fragment
1276 * cache for now; it will be delivered to upper layers
1277 * after all fragments have been received */
1278 goto rx_exit;
1279 }
1280
1281 /* this was the last fragment and the frame will be
1282 * delivered, so remove skb from fragment cache */
1283 skb = frag_skb;
1284 hdr = (struct ieee80211_hdr_4addr *) skb->data;
1285 ieee80211_frag_cache_invalidate(ieee, hdr);
1286 }
1287
1288 /* skb: hdr + (possible reassembled) full MSDU payload; possibly still
1289 * encrypted/authenticated */
1290 if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) &&
1291 ieee80211_rx_frame_decrypt_msdu(ieee, skb, keyidx, crypt))
1292 {
1293 printk("==>decrypt msdu error\n");
1294 goto rx_dropped;
1295 }
1296
1297 //added by amy for AP roaming
1298 ieee->LinkDetectInfo.NumRecvDataInPeriod++;
1299 ieee->LinkDetectInfo.NumRxOkInPeriod++;
1300
1301 hdr = (struct ieee80211_hdr_4addr *) skb->data;
1302 if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep) {
1303 if (/*ieee->ieee802_1x &&*/
1304 ieee80211_is_eapol_frame(ieee, skb, hdrlen)) {
1305
1306#ifdef CONFIG_IEEE80211_DEBUG
1307 /* pass unencrypted EAPOL frames even if encryption is
1308 * configured */
1309 struct eapol *eap = (struct eapol *)(skb->data +
1310 24);
1311 IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n",
1312 eap_get_type(eap->type));
1313#endif
1314 } else {
1315 IEEE80211_DEBUG_DROP(
1316 "encryption configured, but RX "
1317 "frame not encrypted (SA=" MAC_FMT ")\n",
1318 MAC_ARG(hdr->addr2));
1319 goto rx_dropped;
1320 }
1321 }
1322
1323#ifdef CONFIG_IEEE80211_DEBUG
1324 if (crypt && !(fc & IEEE80211_FCTL_WEP) &&
1325 ieee80211_is_eapol_frame(ieee, skb, hdrlen)) {
1326 struct eapol *eap = (struct eapol *)(skb->data +
1327 24);
1328 IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n",
1329 eap_get_type(eap->type));
1330 }
1331#endif
1332
1333 if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep &&
1334 !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) {
1335 IEEE80211_DEBUG_DROP(
1336 "dropped unencrypted RX data "
1337 "frame from " MAC_FMT
1338 " (drop_unencrypted=1)\n",
1339 MAC_ARG(hdr->addr2));
1340 goto rx_dropped;
1341 }
1342/*
1343 if(ieee80211_is_eapol_frame(ieee, skb, hdrlen)) {
1344 printk(KERN_WARNING "RX: IEEE802.1X EPAOL frame!\n");
1345 }
1346*/
1347//added by amy for reorder
1348#if 1
1349 if(ieee->current_network.qos_data.active && IsQoSDataFrame(skb->data)
1350 && !is_multicast_ether_addr(hdr->addr1) && !is_broadcast_ether_addr(hdr->addr1))
1351 {
1352 TID = Frame_QoSTID(skb->data);
1353 SeqNum = WLAN_GET_SEQ_SEQ(sc);
1354 GetTs(ieee,(PTS_COMMON_INFO*) &pTS,hdr->addr2,TID,RX_DIR,true);
1355 if(TID !=0 && TID !=3)
1356 {
1357 ieee->bis_any_nonbepkts = true;
1358 }
1359 }
1360#endif
1361//added by amy for reorder
1362 /* skb: hdr + (possible reassembled) full plaintext payload */
1363 payload = skb->data + hdrlen;
1364 //ethertype = (payload[6] << 8) | payload[7];
1365 rxb = (struct ieee80211_rxb*)kmalloc(sizeof(struct ieee80211_rxb),GFP_ATOMIC);
1366 if(rxb == NULL)
1367 {
1368 IEEE80211_DEBUG(IEEE80211_DL_ERR,"%s(): kmalloc rxb error\n",__FUNCTION__);
1369 goto rx_dropped;
1370 }
1371 /* to parse amsdu packets */
1372 /* qos data packets & reserved bit is 1 */
1373 if(parse_subframe(skb,rx_stats,rxb,src,dst) == 0) {
1374 /* only to free rxb, and not submit the packets to upper layer */
1375 for(i =0; i < rxb->nr_subframes; i++) {
1376 dev_kfree_skb(rxb->subframes[i]);
1377 }
1378 kfree(rxb);
1379 rxb = NULL;
1380 goto rx_dropped;
1381 }
1382
1383 ieee->last_rx_ps_time = jiffies;
1384//added by amy for reorder
1385 if(ieee->pHTInfo->bCurRxReorderEnable == false ||pTS == NULL){
1386//added by amy for reorder
1387 for(i = 0; i<rxb->nr_subframes; i++) {
1388 struct sk_buff *sub_skb = rxb->subframes[i];
1389
1390 if (sub_skb) {
1391 /* convert hdr + possible LLC headers into Ethernet header */
1392 ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7];
1393 if (sub_skb->len >= 8 &&
1394 ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 &&
1395 ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) ||
1396 memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) {
1397 /* remove RFC1042 or Bridge-Tunnel encapsulation and
1398 * replace EtherType */
1399 skb_pull(sub_skb, SNAP_SIZE);
1400 memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN);
1401 memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN);
1402 } else {
1403 u16 len;
1404 /* Leave Ethernet header part of hdr and full payload */
1405 len = htons(sub_skb->len);
1406 memcpy(skb_push(sub_skb, 2), &len, 2);
1407 memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN);
1408 memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN);
1409 }
1410
1411 stats->rx_packets++;
1412 stats->rx_bytes += sub_skb->len;
1413 if(is_multicast_ether_addr(dst)) {
1414 stats->multicast++;
1415 }
1416
1417 /* Indicat the packets to upper layer */
1418 //printk("0skb_len(%d)\n", skb->len);
1419 sub_skb->protocol = eth_type_trans(sub_skb, dev);
1420 memset(sub_skb->cb, 0, sizeof(sub_skb->cb));
1421 sub_skb->dev = dev;
1422 sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */
1423 //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */
1424 //printk("1skb_len(%d)\n", skb->len);
1425 netif_rx(sub_skb);
1426 }
1427 }
1428 kfree(rxb);
1429 rxb = NULL;
1430
1431 }
1432 else
1433 {
1434 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): REORDER ENABLE AND PTS not NULL, and we will enter RxReorderIndicatePacket()\n",__FUNCTION__);
1435 RxReorderIndicatePacket(ieee, rxb, pTS, SeqNum);
1436 }
1437#ifndef JOHN_NOCPY
1438 dev_kfree_skb(skb);
1439#endif
1440
1441 rx_exit:
1442#ifdef NOT_YET
1443 if (sta)
1444 hostap_handle_sta_release(sta);
1445#endif
1446 return 1;
1447
1448 rx_dropped:
1449 if (rxb != NULL)
1450 {
1451 kfree(rxb);
1452 rxb = NULL;
1453 }
1454 stats->rx_dropped++;
1455
1456 /* Returning 0 indicates to caller that we have not handled the SKB--
1457 * so it is still allocated and can be used again by underlying
1458 * hardware as a DMA target */
1459 return 0;
1460}
1461
1462#define MGMT_FRAME_FIXED_PART_LENGTH 0x24
1463
1464static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
1465
1466/*
1467* Make ther structure we read from the beacon packet has
1468* the right values
1469*/
1470static int ieee80211_verify_qos_info(struct ieee80211_qos_information_element
1471 *info_element, int sub_type)
1472{
1473
1474 if (info_element->qui_subtype != sub_type)
1475 return -1;
1476 if (memcmp(info_element->qui, qos_oui, QOS_OUI_LEN))
1477 return -1;
1478 if (info_element->qui_type != QOS_OUI_TYPE)
1479 return -1;
1480 if (info_element->version != QOS_VERSION_1)
1481 return -1;
1482
1483 return 0;
1484}
1485
1486
1487/*
1488 * Parse a QoS parameter element
1489 */
1490static int ieee80211_read_qos_param_element(struct ieee80211_qos_parameter_info
1491 *element_param, struct ieee80211_info_element
1492 *info_element)
1493{
1494 int ret = 0;
1495 u16 size = sizeof(struct ieee80211_qos_parameter_info) - 2;
1496
1497 if ((info_element == NULL) || (element_param == NULL))
1498 return -1;
1499
1500 if (info_element->id == QOS_ELEMENT_ID && info_element->len == size) {
1501 memcpy(element_param->info_element.qui, info_element->data,
1502 info_element->len);
1503 element_param->info_element.elementID = info_element->id;
1504 element_param->info_element.length = info_element->len;
1505 } else
1506 ret = -1;
1507 if (ret == 0)
1508 ret = ieee80211_verify_qos_info(&element_param->info_element,
1509 QOS_OUI_PARAM_SUB_TYPE);
1510 return ret;
1511}
1512
1513/*
1514 * Parse a QoS information element
1515 */
1516static int ieee80211_read_qos_info_element(struct
1517 ieee80211_qos_information_element
1518 *element_info, struct ieee80211_info_element
1519 *info_element)
1520{
1521 int ret = 0;
1522 u16 size = sizeof(struct ieee80211_qos_information_element) - 2;
1523
1524 if (element_info == NULL)
1525 return -1;
1526 if (info_element == NULL)
1527 return -1;
1528
1529 if ((info_element->id == QOS_ELEMENT_ID) && (info_element->len == size)) {
1530 memcpy(element_info->qui, info_element->data,
1531 info_element->len);
1532 element_info->elementID = info_element->id;
1533 element_info->length = info_element->len;
1534 } else
1535 ret = -1;
1536
1537 if (ret == 0)
1538 ret = ieee80211_verify_qos_info(element_info,
1539 QOS_OUI_INFO_SUB_TYPE);
1540 return ret;
1541}
1542
1543
1544/*
1545 * Write QoS parameters from the ac parameters.
1546 */
1547static int ieee80211_qos_convert_ac_to_parameters(struct
1548 ieee80211_qos_parameter_info
1549 *param_elm, struct
1550 ieee80211_qos_parameters
1551 *qos_param)
1552{
1553 int rc = 0;
1554 int i;
1555 struct ieee80211_qos_ac_parameter *ac_params;
1556 u8 aci;
1557 //u8 cw_min;
1558 //u8 cw_max;
1559
1560 for (i = 0; i < QOS_QUEUE_NUM; i++) {
1561 ac_params = &(param_elm->ac_params_record[i]);
1562
1563 aci = (ac_params->aci_aifsn & 0x60) >> 5;
1564
1565 if(aci >= QOS_QUEUE_NUM)
1566 continue;
1567 qos_param->aifs[aci] = (ac_params->aci_aifsn) & 0x0f;
1568
1569 /* WMM spec P.11: The minimum value for AIFSN shall be 2 */
1570 qos_param->aifs[aci] = (qos_param->aifs[aci] < 2) ? 2:qos_param->aifs[aci];
1571
1572 qos_param->cw_min[aci] = ac_params->ecw_min_max & 0x0F;
1573
1574 qos_param->cw_max[aci] = (ac_params->ecw_min_max & 0xF0) >> 4;
1575
1576 qos_param->flag[aci] =
1577 (ac_params->aci_aifsn & 0x10) ? 0x01 : 0x00;
1578 qos_param->tx_op_limit[aci] = le16_to_cpu(ac_params->tx_op_limit);
1579 }
1580 return rc;
1581}
1582
1583/*
1584 * we have a generic data element which it may contain QoS information or
1585 * parameters element. check the information element length to decide
1586 * which type to read
1587 */
1588static int ieee80211_parse_qos_info_param_IE(struct ieee80211_info_element
1589 *info_element,
1590 struct ieee80211_network *network)
1591{
1592 int rc = 0;
1593 struct ieee80211_qos_parameters *qos_param = NULL;
1594 struct ieee80211_qos_information_element qos_info_element;
1595
1596 rc = ieee80211_read_qos_info_element(&qos_info_element, info_element);
1597
1598 if (rc == 0) {
1599 network->qos_data.param_count = qos_info_element.ac_info & 0x0F;
1600 network->flags |= NETWORK_HAS_QOS_INFORMATION;
1601 } else {
1602 struct ieee80211_qos_parameter_info param_element;
1603
1604 rc = ieee80211_read_qos_param_element(&param_element,
1605 info_element);
1606 if (rc == 0) {
1607 qos_param = &(network->qos_data.parameters);
1608 ieee80211_qos_convert_ac_to_parameters(&param_element,
1609 qos_param);
1610 network->flags |= NETWORK_HAS_QOS_PARAMETERS;
1611 network->qos_data.param_count =
1612 param_element.info_element.ac_info & 0x0F;
1613 }
1614 }
1615
1616 if (rc == 0) {
1617 IEEE80211_DEBUG_QOS("QoS is supported\n");
1618 network->qos_data.supported = 1;
1619 }
1620 return rc;
1621}
1622
1623#ifdef CONFIG_IEEE80211_DEBUG
1624#define MFIE_STRING(x) case MFIE_TYPE_ ##x: return #x
1625
1626static const char *get_info_element_string(u16 id)
1627{
1628 switch (id) {
1629 MFIE_STRING(SSID);
1630 MFIE_STRING(RATES);
1631 MFIE_STRING(FH_SET);
1632 MFIE_STRING(DS_SET);
1633 MFIE_STRING(CF_SET);
1634 MFIE_STRING(TIM);
1635 MFIE_STRING(IBSS_SET);
1636 MFIE_STRING(COUNTRY);
1637 MFIE_STRING(HOP_PARAMS);
1638 MFIE_STRING(HOP_TABLE);
1639 MFIE_STRING(REQUEST);
1640 MFIE_STRING(CHALLENGE);
1641 MFIE_STRING(POWER_CONSTRAINT);
1642 MFIE_STRING(POWER_CAPABILITY);
1643 MFIE_STRING(TPC_REQUEST);
1644 MFIE_STRING(TPC_REPORT);
1645 MFIE_STRING(SUPP_CHANNELS);
1646 MFIE_STRING(CSA);
1647 MFIE_STRING(MEASURE_REQUEST);
1648 MFIE_STRING(MEASURE_REPORT);
1649 MFIE_STRING(QUIET);
1650 MFIE_STRING(IBSS_DFS);
1651 // MFIE_STRING(ERP_INFO);
1652 MFIE_STRING(RSN);
1653 MFIE_STRING(RATES_EX);
1654 MFIE_STRING(GENERIC);
1655 MFIE_STRING(QOS_PARAMETER);
1656 default:
1657 return "UNKNOWN";
1658 }
1659}
1660#endif
1661
1662#ifdef ENABLE_DOT11D
1663static inline void ieee80211_extract_country_ie(
1664 struct ieee80211_device *ieee,
1665 struct ieee80211_info_element *info_element,
1666 struct ieee80211_network *network,
1667 u8 * addr2
1668)
1669{
1670 if(IS_DOT11D_ENABLE(ieee))
1671 {
1672 if(info_element->len!= 0)
1673 {
1674 memcpy(network->CountryIeBuf, info_element->data, info_element->len);
1675 network->CountryIeLen = info_element->len;
1676
1677 if(!IS_COUNTRY_IE_VALID(ieee))
1678 {
1679 Dot11d_UpdateCountryIe(ieee, addr2, info_element->len, info_element->data);
1680 }
1681 }
1682
1683 //
1684 // 070305, rcnjko: I update country IE watch dog here because
1685 // some AP (e.g. Cisco 1242) don't include country IE in their
1686 // probe response frame.
1687 //
1688 if(IS_EQUAL_CIE_SRC(ieee, addr2) )
1689 {
1690 UPDATE_CIE_WATCHDOG(ieee);
1691 }
1692 }
1693
1694}
1695#endif
1696
1697int ieee80211_parse_info_param(struct ieee80211_device *ieee,
1698 struct ieee80211_info_element *info_element,
1699 u16 length,
1700 struct ieee80211_network *network,
1701 struct ieee80211_rx_stats *stats)
1702{
1703 u8 i;
1704 short offset;
1705 u16 tmp_htcap_len=0;
1706 u16 tmp_htinfo_len=0;
1707 u16 ht_realtek_agg_len=0;
1708 u8 ht_realtek_agg_buf[MAX_IE_LEN];
1709// u16 broadcom_len = 0;
1710#ifdef CONFIG_IEEE80211_DEBUG
1711 char rates_str[64];
1712 char *p;
1713#endif
1714
1715 while (length >= sizeof(*info_element)) {
1716 if (sizeof(*info_element) + info_element->len > length) {
1717 IEEE80211_DEBUG_MGMT("Info elem: parse failed: "
1718 "info_element->len + 2 > left : "
1719 "info_element->len+2=%zd left=%d, id=%d.\n",
1720 info_element->len +
1721 sizeof(*info_element),
1722 length, info_element->id);
1723 /* We stop processing but don't return an error here
1724 * because some misbehaviour APs break this rule. ie.
1725 * Orinoco AP1000. */
1726 break;
1727 }
1728
1729 switch (info_element->id) {
1730 case MFIE_TYPE_SSID:
1731 if (ieee80211_is_empty_essid(info_element->data,
1732 info_element->len)) {
1733 network->flags |= NETWORK_EMPTY_ESSID;
1734 break;
1735 }
1736
1737 network->ssid_len = min(info_element->len,
1738 (u8) IW_ESSID_MAX_SIZE);
1739 memcpy(network->ssid, info_element->data, network->ssid_len);
1740 if (network->ssid_len < IW_ESSID_MAX_SIZE)
1741 memset(network->ssid + network->ssid_len, 0,
1742 IW_ESSID_MAX_SIZE - network->ssid_len);
1743
1744 IEEE80211_DEBUG_MGMT("MFIE_TYPE_SSID: '%s' len=%d.\n",
1745 network->ssid, network->ssid_len);
1746 break;
1747
1748 case MFIE_TYPE_RATES:
1749#ifdef CONFIG_IEEE80211_DEBUG
1750 p = rates_str;
1751#endif
1752 network->rates_len = min(info_element->len,
1753 MAX_RATES_LENGTH);
1754 for (i = 0; i < network->rates_len; i++) {
1755 network->rates[i] = info_element->data[i];
1756#ifdef CONFIG_IEEE80211_DEBUG
1757 p += snprintf(p, sizeof(rates_str) -
1758 (p - rates_str), "%02X ",
1759 network->rates[i]);
1760#endif
1761 if (ieee80211_is_ofdm_rate
1762 (info_element->data[i])) {
1763 network->flags |= NETWORK_HAS_OFDM;
1764 if (info_element->data[i] &
1765 IEEE80211_BASIC_RATE_MASK)
1766 network->flags &=
1767 ~NETWORK_HAS_CCK;
1768 }
1769 }
1770
1771 IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES: '%s' (%d)\n",
1772 rates_str, network->rates_len);
1773 break;
1774
1775 case MFIE_TYPE_RATES_EX:
1776#ifdef CONFIG_IEEE80211_DEBUG
1777 p = rates_str;
1778#endif
1779 network->rates_ex_len = min(info_element->len,
1780 MAX_RATES_EX_LENGTH);
1781 for (i = 0; i < network->rates_ex_len; i++) {
1782 network->rates_ex[i] = info_element->data[i];
1783#ifdef CONFIG_IEEE80211_DEBUG
1784 p += snprintf(p, sizeof(rates_str) -
1785 (p - rates_str), "%02X ",
1786 network->rates[i]);
1787#endif
1788 if (ieee80211_is_ofdm_rate
1789 (info_element->data[i])) {
1790 network->flags |= NETWORK_HAS_OFDM;
1791 if (info_element->data[i] &
1792 IEEE80211_BASIC_RATE_MASK)
1793 network->flags &=
1794 ~NETWORK_HAS_CCK;
1795 }
1796 }
1797
1798 IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES_EX: '%s' (%d)\n",
1799 rates_str, network->rates_ex_len);
1800 break;
1801
1802 case MFIE_TYPE_DS_SET:
1803 IEEE80211_DEBUG_MGMT("MFIE_TYPE_DS_SET: %d\n",
1804 info_element->data[0]);
1805 network->channel = info_element->data[0];
1806 break;
1807
1808 case MFIE_TYPE_FH_SET:
1809 IEEE80211_DEBUG_MGMT("MFIE_TYPE_FH_SET: ignored\n");
1810 break;
1811
1812 case MFIE_TYPE_CF_SET:
1813 IEEE80211_DEBUG_MGMT("MFIE_TYPE_CF_SET: ignored\n");
1814 break;
1815
1816 case MFIE_TYPE_TIM:
1817 if(info_element->len < 4)
1818 break;
1819
1820 network->tim.tim_count = info_element->data[0];
1821 network->tim.tim_period = info_element->data[1];
1822
1823 network->dtim_period = info_element->data[1];
1824 if(ieee->state != IEEE80211_LINKED)
1825 break;
1826#if 0
1827 network->last_dtim_sta_time[0] = stats->mac_time[0];
1828#else
1829 //we use jiffies for legacy Power save
1830 network->last_dtim_sta_time[0] = jiffies;
1831#endif
1832 network->last_dtim_sta_time[1] = stats->mac_time[1];
1833
1834 network->dtim_data = IEEE80211_DTIM_VALID;
1835
1836 if(info_element->data[0] != 0)
1837 break;
1838
1839 if(info_element->data[2] & 1)
1840 network->dtim_data |= IEEE80211_DTIM_MBCAST;
1841
1842 offset = (info_element->data[2] >> 1)*2;
1843
1844 //printk("offset1:%x aid:%x\n",offset, ieee->assoc_id);
1845
1846 if(ieee->assoc_id < 8*offset ||
1847 ieee->assoc_id > 8*(offset + info_element->len -3))
1848
1849 break;
1850
1851 offset = (ieee->assoc_id / 8) - offset;// + ((aid % 8)? 0 : 1) ;
1852
1853 if(info_element->data[3+offset] & (1<<(ieee->assoc_id%8)))
1854 network->dtim_data |= IEEE80211_DTIM_UCAST;
1855
1856 //IEEE80211_DEBUG_MGMT("MFIE_TYPE_TIM: partially ignored\n");
1857 break;
1858
1859 case MFIE_TYPE_ERP:
1860 network->erp_value = info_element->data[0];
1861 network->flags |= NETWORK_HAS_ERP_VALUE;
1862 IEEE80211_DEBUG_MGMT("MFIE_TYPE_ERP_SET: %d\n",
1863 network->erp_value);
1864 break;
1865 case MFIE_TYPE_IBSS_SET:
1866 network->atim_window = info_element->data[0];
1867 IEEE80211_DEBUG_MGMT("MFIE_TYPE_IBSS_SET: %d\n",
1868 network->atim_window);
1869 break;
1870
1871 case MFIE_TYPE_CHALLENGE:
1872 IEEE80211_DEBUG_MGMT("MFIE_TYPE_CHALLENGE: ignored\n");
1873 break;
1874
1875 case MFIE_TYPE_GENERIC:
1876 IEEE80211_DEBUG_MGMT("MFIE_TYPE_GENERIC: %d bytes\n",
1877 info_element->len);
1878 if (!ieee80211_parse_qos_info_param_IE(info_element,
1879 network))
1880 break;
1881
1882 if (info_element->len >= 4 &&
1883 info_element->data[0] == 0x00 &&
1884 info_element->data[1] == 0x50 &&
1885 info_element->data[2] == 0xf2 &&
1886 info_element->data[3] == 0x01) {
1887 network->wpa_ie_len = min(info_element->len + 2,
1888 MAX_WPA_IE_LEN);
1889 memcpy(network->wpa_ie, info_element,
1890 network->wpa_ie_len);
1891 break;
1892 }
1893
1894#ifdef THOMAS_TURBO
1895 if (info_element->len == 7 &&
1896 info_element->data[0] == 0x00 &&
1897 info_element->data[1] == 0xe0 &&
1898 info_element->data[2] == 0x4c &&
1899 info_element->data[3] == 0x01 &&
1900 info_element->data[4] == 0x02) {
1901 network->Turbo_Enable = 1;
1902 }
1903#endif
1904
1905 //for HTcap and HTinfo parameters
1906 if(tmp_htcap_len == 0){
1907 if(info_element->len >= 4 &&
1908 info_element->data[0] == 0x00 &&
1909 info_element->data[1] == 0x90 &&
1910 info_element->data[2] == 0x4c &&
1911 info_element->data[3] == 0x033){
1912
1913 tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN);
1914 if(tmp_htcap_len != 0){
1915 network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC;
1916 network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\
1917 sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len;
1918 memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen);
1919 }
1920 }
1921 if(tmp_htcap_len != 0){
1922 network->bssht.bdSupportHT = true;
1923 network->bssht.bdHT1R = ((((PHT_CAPABILITY_ELE)(network->bssht.bdHTCapBuf))->MCS[1]) == 0);
1924 }else{
1925 network->bssht.bdSupportHT = false;
1926 network->bssht.bdHT1R = false;
1927 }
1928 }
1929
1930
1931 if(tmp_htinfo_len == 0){
1932 if(info_element->len >= 4 &&
1933 info_element->data[0] == 0x00 &&
1934 info_element->data[1] == 0x90 &&
1935 info_element->data[2] == 0x4c &&
1936 info_element->data[3] == 0x034){
1937
1938 tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN);
1939 if(tmp_htinfo_len != 0){
1940 network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC;
1941 if(tmp_htinfo_len){
1942 network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\
1943 sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len;
1944 memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen);
1945 }
1946
1947 }
1948
1949 }
1950 }
1951
1952 if(ieee->aggregation){
1953 if(network->bssht.bdSupportHT){
1954 if(info_element->len >= 4 &&
1955 info_element->data[0] == 0x00 &&
1956 info_element->data[1] == 0xe0 &&
1957 info_element->data[2] == 0x4c &&
1958 info_element->data[3] == 0x02){
1959
1960 ht_realtek_agg_len = min(info_element->len,(u8)MAX_IE_LEN);
1961 memcpy(ht_realtek_agg_buf,info_element->data,info_element->len);
1962
1963 }
1964 if(ht_realtek_agg_len >= 5){
1965 network->realtek_cap_exit = true;
1966 network->bssht.bdRT2RTAggregation = true;
1967
1968 if((ht_realtek_agg_buf[4] == 1) && (ht_realtek_agg_buf[5] & 0x02))
1969 network->bssht.bdRT2RTLongSlotTime = true;
1970
1971 if((ht_realtek_agg_buf[4]==1) && (ht_realtek_agg_buf[5] & RT_HT_CAP_USE_92SE))
1972 {
1973 network->bssht.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE;
1974 //bssDesc->Vender = HT_IOT_PEER_REALTEK_92SE;
1975 }
1976 }
1977 }
1978
1979 }
1980
1981 //if(tmp_htcap_len !=0 || tmp_htinfo_len != 0)
1982 {
1983 if((info_element->len >= 3 &&
1984 info_element->data[0] == 0x00 &&
1985 info_element->data[1] == 0x05 &&
1986 info_element->data[2] == 0xb5) ||
1987 (info_element->len >= 3 &&
1988 info_element->data[0] == 0x00 &&
1989 info_element->data[1] == 0x0a &&
1990 info_element->data[2] == 0xf7) ||
1991 (info_element->len >= 3 &&
1992 info_element->data[0] == 0x00 &&
1993 info_element->data[1] == 0x10 &&
1994 info_element->data[2] == 0x18)){
1995
1996 network->broadcom_cap_exist = true;
1997
1998 }
1999 }
2000#if 0
2001 if (tmp_htcap_len !=0)
2002 {
2003 u16 cap_ext = ((PHT_CAPABILITY_ELE)&info_element->data[0])->ExtHTCapInfo;
2004 if ((cap_ext & 0x0c00) == 0x0c00)
2005 {
2006 network->ralink_cap_exist = true;
2007 }
2008 }
2009#endif
2010 if(info_element->len >= 3 &&
2011 info_element->data[0] == 0x00 &&
2012 info_element->data[1] == 0x0c &&
2013 info_element->data[2] == 0x43)
2014 {
2015 network->ralink_cap_exist = true;
2016 }
2017 else
2018 network->ralink_cap_exist = false;
2019 //added by amy for atheros AP
2020 if((info_element->len >= 3 &&
2021 info_element->data[0] == 0x00 &&
2022 info_element->data[1] == 0x03 &&
2023 info_element->data[2] == 0x7f) ||
2024 (info_element->len >= 3 &&
2025 info_element->data[0] == 0x00 &&
2026 info_element->data[1] == 0x13 &&
2027 info_element->data[2] == 0x74))
2028 {
2029 // printk("========>%s(): athros AP is exist\n",__FUNCTION__);
2030 network->atheros_cap_exist = true;
2031 }
2032 else
2033 network->atheros_cap_exist = false;
2034
2035 if ((info_element->len >= 3 &&
2036 info_element->data[0] == 0x00 &&
2037 info_element->data[1] == 0x50 &&
2038 info_element->data[2] == 0x43) )
2039 {
2040 network->marvell_cap_exist = true;
2041 }
2042 else
2043 network->marvell_cap_exist = false;
2044
2045 if(info_element->len >= 3 &&
2046 info_element->data[0] == 0x00 &&
2047 info_element->data[1] == 0x40 &&
2048 info_element->data[2] == 0x96)
2049 {
2050 network->cisco_cap_exist = true;
2051 }
2052 else
2053 network->cisco_cap_exist = false;
2054 //added by amy for LEAP of cisco
2055 if(info_element->len > 4 &&
2056 info_element->data[0] == 0x00 &&
2057 info_element->data[1] == 0x40 &&
2058 info_element->data[2] == 0x96 &&
2059 info_element->data[3] == 0x01)
2060 {
2061 if(info_element->len == 6)
2062 {
2063 memcpy(network->CcxRmState, &info_element[4], 2);
2064 if(network->CcxRmState[0] != 0)
2065 {
2066 network->bCcxRmEnable = true;
2067 }
2068 else
2069 network->bCcxRmEnable = false;
2070 //
2071 // CCXv4 Table 59-1 MBSSID Masks.
2072 //
2073 network->MBssidMask = network->CcxRmState[1] & 0x07;
2074 if(network->MBssidMask != 0)
2075 {
2076 network->bMBssidValid = true;
2077 network->MBssidMask = 0xff << (network->MBssidMask);
2078 cpMacAddr(network->MBssid, network->bssid);
2079 network->MBssid[5] &= network->MBssidMask;
2080 }
2081 else
2082 {
2083 network->bMBssidValid = false;
2084 }
2085 }
2086 else
2087 {
2088 network->bCcxRmEnable = false;
2089 }
2090 }
2091 if(info_element->len > 4 &&
2092 info_element->data[0] == 0x00 &&
2093 info_element->data[1] == 0x40 &&
2094 info_element->data[2] == 0x96 &&
2095 info_element->data[3] == 0x03)
2096 {
2097 if(info_element->len == 5)
2098 {
2099 network->bWithCcxVerNum = true;
2100 network->BssCcxVerNumber = info_element->data[4];
2101 }
2102 else
2103 {
2104 network->bWithCcxVerNum = false;
2105 network->BssCcxVerNumber = 0;
2106 }
2107 }
2108 break;
2109
2110 case MFIE_TYPE_RSN:
2111 IEEE80211_DEBUG_MGMT("MFIE_TYPE_RSN: %d bytes\n",
2112 info_element->len);
2113 network->rsn_ie_len = min(info_element->len + 2,
2114 MAX_WPA_IE_LEN);
2115 memcpy(network->rsn_ie, info_element,
2116 network->rsn_ie_len);
2117 break;
2118
2119 //HT related element.
2120 case MFIE_TYPE_HT_CAP:
2121 IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_CAP: %d bytes\n",
2122 info_element->len);
2123 tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN);
2124 if(tmp_htcap_len != 0){
2125 network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC;
2126 network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\
2127 sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len;
2128 memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen);
2129
2130 //If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT()
2131 // windows driver will update WMM parameters each beacon received once connected
2132 // Linux driver is a bit different.
2133 network->bssht.bdSupportHT = true;
2134 network->bssht.bdHT1R = ((((PHT_CAPABILITY_ELE)(network->bssht.bdHTCapBuf))->MCS[1]) == 0);
2135 }
2136 else{
2137 network->bssht.bdSupportHT = false;
2138 network->bssht.bdHT1R = false;
2139 }
2140 break;
2141
2142
2143 case MFIE_TYPE_HT_INFO:
2144 IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_INFO: %d bytes\n",
2145 info_element->len);
2146 tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN);
2147 if(tmp_htinfo_len){
2148 network->bssht.bdHTSpecVer = HT_SPEC_VER_IEEE;
2149 network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\
2150 sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len;
2151 memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen);
2152 }
2153 break;
2154
2155 case MFIE_TYPE_AIRONET:
2156 IEEE80211_DEBUG_SCAN("MFIE_TYPE_AIRONET: %d bytes\n",
2157 info_element->len);
2158 if(info_element->len >IE_CISCO_FLAG_POSITION)
2159 {
2160 network->bWithAironetIE = true;
2161
2162 // CCX 1 spec v1.13, A01.1 CKIP Negotiation (page23):
2163 // "A Cisco access point advertises support for CKIP in beacon and probe response packets,
2164 // by adding an Aironet element and setting one or both of the CKIP negotiation bits."
2165 if( (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_MIC) ||
2166 (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_PK) )
2167 {
2168 network->bCkipSupported = true;
2169 }
2170 else
2171 {
2172 network->bCkipSupported = false;
2173 }
2174 }
2175 else
2176 {
2177 network->bWithAironetIE = false;
2178 network->bCkipSupported = false;
2179 }
2180 break;
2181 case MFIE_TYPE_QOS_PARAMETER:
2182 printk(KERN_ERR
2183 "QoS Error need to parse QOS_PARAMETER IE\n");
2184 break;
2185
2186#ifdef ENABLE_DOT11D
2187 case MFIE_TYPE_COUNTRY:
2188 IEEE80211_DEBUG_SCAN("MFIE_TYPE_COUNTRY: %d bytes\n",
2189 info_element->len);
2190 //printk("=====>Receive <%s> Country IE\n",network->ssid);
2191 ieee80211_extract_country_ie(ieee, info_element, network, network->bssid);//addr2 is same as addr3 when from an AP
2192 break;
2193#endif
2194/* TODO */
2195#if 0
2196 /* 802.11h */
2197 case MFIE_TYPE_POWER_CONSTRAINT:
2198 network->power_constraint = info_element->data[0];
2199 network->flags |= NETWORK_HAS_POWER_CONSTRAINT;
2200 break;
2201
2202 case MFIE_TYPE_CSA:
2203 network->power_constraint = info_element->data[0];
2204 network->flags |= NETWORK_HAS_CSA;
2205 break;
2206
2207 case MFIE_TYPE_QUIET:
2208 network->quiet.count = info_element->data[0];
2209 network->quiet.period = info_element->data[1];
2210 network->quiet.duration = info_element->data[2];
2211 network->quiet.offset = info_element->data[3];
2212 network->flags |= NETWORK_HAS_QUIET;
2213 break;
2214
2215 case MFIE_TYPE_IBSS_DFS:
2216 if (network->ibss_dfs)
2217 break;
2218 network->ibss_dfs = kmemdup(info_element->data,
2219 info_element->len,
2220 GFP_ATOMIC);
2221 if (!network->ibss_dfs)
2222 return 1;
2223 network->flags |= NETWORK_HAS_IBSS_DFS;
2224 break;
2225
2226 case MFIE_TYPE_TPC_REPORT:
2227 network->tpc_report.transmit_power =
2228 info_element->data[0];
2229 network->tpc_report.link_margin = info_element->data[1];
2230 network->flags |= NETWORK_HAS_TPC_REPORT;
2231 break;
2232#endif
2233 default:
2234 IEEE80211_DEBUG_MGMT
2235 ("Unsupported info element: %s (%d)\n",
2236 get_info_element_string(info_element->id),
2237 info_element->id);
2238 break;
2239 }
2240
2241 length -= sizeof(*info_element) + info_element->len;
2242 info_element =
2243 (struct ieee80211_info_element *)&info_element->
2244 data[info_element->len];
2245 }
2246
2247 if(!network->atheros_cap_exist && !network->broadcom_cap_exist &&
2248 !network->cisco_cap_exist && !network->ralink_cap_exist && !network->bssht.bdRT2RTAggregation)
2249 {
2250 network->unknown_cap_exist = true;
2251 }
2252 else
2253 {
2254 network->unknown_cap_exist = false;
2255 }
2256 return 0;
2257}
2258
2259static inline u8 ieee80211_SignalStrengthTranslate(
2260 u8 CurrSS
2261 )
2262{
2263 u8 RetSS;
2264
2265 // Step 1. Scale mapping.
2266 if(CurrSS >= 71 && CurrSS <= 100)
2267 {
2268 RetSS = 90 + ((CurrSS - 70) / 3);
2269 }
2270 else if(CurrSS >= 41 && CurrSS <= 70)
2271 {
2272 RetSS = 78 + ((CurrSS - 40) / 3);
2273 }
2274 else if(CurrSS >= 31 && CurrSS <= 40)
2275 {
2276 RetSS = 66 + (CurrSS - 30);
2277 }
2278 else if(CurrSS >= 21 && CurrSS <= 30)
2279 {
2280 RetSS = 54 + (CurrSS - 20);
2281 }
2282 else if(CurrSS >= 5 && CurrSS <= 20)
2283 {
2284 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
2285 }
2286 else if(CurrSS == 4)
2287 {
2288 RetSS = 36;
2289 }
2290 else if(CurrSS == 3)
2291 {
2292 RetSS = 27;
2293 }
2294 else if(CurrSS == 2)
2295 {
2296 RetSS = 18;
2297 }
2298 else if(CurrSS == 1)
2299 {
2300 RetSS = 9;
2301 }
2302 else
2303 {
2304 RetSS = CurrSS;
2305 }
2306 //RT_TRACE(COMP_DBG, DBG_LOUD, ("##### After Mapping: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
2307
2308 // Step 2. Smoothing.
2309
2310 //RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$$$ After Smoothing: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS));
2311
2312 return RetSS;
2313}
2314
2315long ieee80211_translate_todbm(u8 signal_strength_index )// 0-100 index.
2316{
2317 long signal_power; // in dBm.
2318
2319 // Translate to dBm (x=0.5y-95).
2320 signal_power = (long)((signal_strength_index + 1) >> 1);
2321 signal_power -= 95;
2322
2323 return signal_power;
2324}
2325
2326static inline int ieee80211_network_init(
2327 struct ieee80211_device *ieee,
2328 struct ieee80211_probe_response *beacon,
2329 struct ieee80211_network *network,
2330 struct ieee80211_rx_stats *stats)
2331{
2332#ifdef CONFIG_IEEE80211_DEBUG
2333 //char rates_str[64];
2334 //char *p;
2335#endif
2336
2337 network->qos_data.active = 0;
2338 network->qos_data.supported = 0;
2339 network->qos_data.param_count = 0;
2340 network->qos_data.old_param_count = 0;
2341
2342 /* Pull out fixed field data */
2343 memcpy(network->bssid, beacon->header.addr3, ETH_ALEN);
2344 network->capability = le16_to_cpu(beacon->capability);
2345 network->last_scanned = jiffies;
2346 network->time_stamp[0] = le32_to_cpu(beacon->time_stamp[0]);
2347 network->time_stamp[1] = le32_to_cpu(beacon->time_stamp[1]);
2348 network->beacon_interval = le32_to_cpu(beacon->beacon_interval);
2349 /* Where to pull this? beacon->listen_interval;*/
2350 network->listen_interval = 0x0A;
2351 network->rates_len = network->rates_ex_len = 0;
2352 network->last_associate = 0;
2353 network->ssid_len = 0;
2354 network->flags = 0;
2355 network->atim_window = 0;
2356 network->erp_value = (network->capability & WLAN_CAPABILITY_IBSS) ?
2357 0x3 : 0x0;
2358 network->berp_info_valid = false;
2359 network->broadcom_cap_exist = false;
2360 network->ralink_cap_exist = false;
2361 network->atheros_cap_exist = false;
2362 network->cisco_cap_exist = false;
2363 network->unknown_cap_exist = false;
2364 network->realtek_cap_exit = false;
2365 network->marvell_cap_exist = false;
2366#ifdef THOMAS_TURBO
2367 network->Turbo_Enable = 0;
2368#endif
2369#ifdef ENABLE_DOT11D
2370 network->CountryIeLen = 0;
2371 memset(network->CountryIeBuf, 0, MAX_IE_LEN);
2372#endif
2373//Initialize HT parameters
2374 //ieee80211_ht_initialize(&network->bssht);
2375 HTInitializeBssDesc(&network->bssht);
2376 if (stats->freq == IEEE80211_52GHZ_BAND) {
2377 /* for A band (No DS info) */
2378 network->channel = stats->received_channel;
2379 } else
2380 network->flags |= NETWORK_HAS_CCK;
2381
2382 network->wpa_ie_len = 0;
2383 network->rsn_ie_len = 0;
2384
2385 if (ieee80211_parse_info_param
2386 (ieee,beacon->info_element, stats->len - sizeof(*beacon), network, stats))
2387 return 1;
2388
2389 network->mode = 0;
2390 if (stats->freq == IEEE80211_52GHZ_BAND)
2391 network->mode = IEEE_A;
2392 else {
2393 if (network->flags & NETWORK_HAS_OFDM)
2394 network->mode |= IEEE_G;
2395 if (network->flags & NETWORK_HAS_CCK)
2396 network->mode |= IEEE_B;
2397 }
2398
2399 if (network->mode == 0) {
2400 IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' "
2401 "network.\n",
2402 escape_essid(network->ssid,
2403 network->ssid_len),
2404 MAC_ARG(network->bssid));
2405 return 1;
2406 }
2407
2408 if(network->bssht.bdSupportHT){
2409 if(network->mode == IEEE_A)
2410 network->mode = IEEE_N_5G;
2411 else if(network->mode & (IEEE_G | IEEE_B))
2412 network->mode = IEEE_N_24G;
2413 }
2414 if (ieee80211_is_empty_essid(network->ssid, network->ssid_len))
2415 network->flags |= NETWORK_EMPTY_ESSID;
2416
2417#if 1
2418 stats->signal = 30 + (stats->SignalStrength * 70) / 100;
2419 //stats->signal = ieee80211_SignalStrengthTranslate(stats->signal);
2420 stats->noise = ieee80211_translate_todbm((u8)(100-stats->signal)) -25;
2421#endif
2422
2423 memcpy(&network->stats, stats, sizeof(network->stats));
2424
2425 return 0;
2426}
2427
2428static inline int is_same_network(struct ieee80211_network *src,
2429 struct ieee80211_network *dst, struct ieee80211_device* ieee)
2430{
2431 /* A network is only a duplicate if the channel, BSSID, ESSID
2432 * and the capability field (in particular IBSS and BSS) all match.
2433 * We treat all <hidden> with the same BSSID and channel
2434 * as one network */
2435 return //((src->ssid_len == dst->ssid_len) &&
2436 (((src->ssid_len == dst->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) &&
2437 (src->channel == dst->channel) &&
2438 !memcmp(src->bssid, dst->bssid, ETH_ALEN) &&
2439 //!memcmp(src->ssid, dst->ssid, src->ssid_len) &&
2440 (!memcmp(src->ssid, dst->ssid, src->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) &&
2441 ((src->capability & WLAN_CAPABILITY_IBSS) ==
2442 (dst->capability & WLAN_CAPABILITY_IBSS)) &&
2443 ((src->capability & WLAN_CAPABILITY_BSS) ==
2444 (dst->capability & WLAN_CAPABILITY_BSS)));
2445}
2446
2447static inline void update_network(struct ieee80211_network *dst,
2448 struct ieee80211_network *src)
2449{
2450 int qos_active;
2451 u8 old_param;
2452
2453 memcpy(&dst->stats, &src->stats, sizeof(struct ieee80211_rx_stats));
2454 dst->capability = src->capability;
2455 memcpy(dst->rates, src->rates, src->rates_len);
2456 dst->rates_len = src->rates_len;
2457 memcpy(dst->rates_ex, src->rates_ex, src->rates_ex_len);
2458 dst->rates_ex_len = src->rates_ex_len;
2459 if(src->ssid_len > 0)
2460 {
2461 memset(dst->ssid, 0, dst->ssid_len);
2462 dst->ssid_len = src->ssid_len;
2463 memcpy(dst->ssid, src->ssid, src->ssid_len);
2464 }
2465 dst->mode = src->mode;
2466 dst->flags = src->flags;
2467 dst->time_stamp[0] = src->time_stamp[0];
2468 dst->time_stamp[1] = src->time_stamp[1];
2469 if (src->flags & NETWORK_HAS_ERP_VALUE)
2470 {
2471 dst->erp_value = src->erp_value;
2472 dst->berp_info_valid = src->berp_info_valid = true;
2473 }
2474 dst->beacon_interval = src->beacon_interval;
2475 dst->listen_interval = src->listen_interval;
2476 dst->atim_window = src->atim_window;
2477 dst->dtim_period = src->dtim_period;
2478 dst->dtim_data = src->dtim_data;
2479 dst->last_dtim_sta_time[0] = src->last_dtim_sta_time[0];
2480 dst->last_dtim_sta_time[1] = src->last_dtim_sta_time[1];
2481 memcpy(&dst->tim, &src->tim, sizeof(struct ieee80211_tim_parameters));
2482
2483 dst->bssht.bdSupportHT = src->bssht.bdSupportHT;
2484 dst->bssht.bdRT2RTAggregation = src->bssht.bdRT2RTAggregation;
2485 dst->bssht.bdHTCapLen= src->bssht.bdHTCapLen;
2486 memcpy(dst->bssht.bdHTCapBuf,src->bssht.bdHTCapBuf,src->bssht.bdHTCapLen);
2487 dst->bssht.bdHTInfoLen= src->bssht.bdHTInfoLen;
2488 memcpy(dst->bssht.bdHTInfoBuf,src->bssht.bdHTInfoBuf,src->bssht.bdHTInfoLen);
2489 dst->bssht.bdHTSpecVer = src->bssht.bdHTSpecVer;
2490 dst->bssht.bdRT2RTLongSlotTime = src->bssht.bdRT2RTLongSlotTime;
2491 dst->broadcom_cap_exist = src->broadcom_cap_exist;
2492 dst->ralink_cap_exist = src->ralink_cap_exist;
2493 dst->atheros_cap_exist = src->atheros_cap_exist;
2494 dst->realtek_cap_exit = src->realtek_cap_exit;
2495 dst->marvell_cap_exist = src->marvell_cap_exist;
2496 dst->cisco_cap_exist = src->cisco_cap_exist;
2497 dst->unknown_cap_exist = src->unknown_cap_exist;
2498 memcpy(dst->wpa_ie, src->wpa_ie, src->wpa_ie_len);
2499 dst->wpa_ie_len = src->wpa_ie_len;
2500 memcpy(dst->rsn_ie, src->rsn_ie, src->rsn_ie_len);
2501 dst->rsn_ie_len = src->rsn_ie_len;
2502
2503 dst->last_scanned = jiffies;
2504 /* qos related parameters */
2505 //qos_active = src->qos_data.active;
2506 qos_active = dst->qos_data.active;
2507 //old_param = dst->qos_data.old_param_count;
2508 old_param = dst->qos_data.param_count;
2509 if(dst->flags & NETWORK_HAS_QOS_MASK){
2510 //not update QOS paramter in beacon, as most AP will set all these parameter to 0.//WB
2511 // printk("====>%s(), aifs:%x, %x\n", __FUNCTION__, dst->qos_data.parameters.aifs[0], src->qos_data.parameters.aifs[0]);
2512 // memcpy(&dst->qos_data, &src->qos_data,
2513 // sizeof(struct ieee80211_qos_data));
2514 }
2515 else {
2516 dst->qos_data.supported = src->qos_data.supported;
2517 dst->qos_data.param_count = src->qos_data.param_count;
2518 }
2519
2520 if(dst->qos_data.supported == 1) {
2521 dst->QoS_Enable = 1;
2522 if(dst->ssid_len)
2523 IEEE80211_DEBUG_QOS
2524 ("QoS the network %s is QoS supported\n",
2525 dst->ssid);
2526 else
2527 IEEE80211_DEBUG_QOS
2528 ("QoS the network is QoS supported\n");
2529 }
2530 dst->qos_data.active = qos_active;
2531 dst->qos_data.old_param_count = old_param;
2532
2533 /* dst->last_associate is not overwritten */
2534#if 1
2535 dst->wmm_info = src->wmm_info; //sure to exist in beacon or probe response frame.
2536 if(src->wmm_param[0].ac_aci_acm_aifsn|| \
2537 src->wmm_param[1].ac_aci_acm_aifsn|| \
2538 src->wmm_param[2].ac_aci_acm_aifsn|| \
2539 src->wmm_param[1].ac_aci_acm_aifsn) {
2540 memcpy(dst->wmm_param, src->wmm_param, WME_AC_PRAM_LEN);
2541 }
2542 //dst->QoS_Enable = src->QoS_Enable;
2543#else
2544 dst->QoS_Enable = 1;//for Rtl8187 simulation
2545#endif
2546#ifdef THOMAS_TURBO
2547 dst->Turbo_Enable = src->Turbo_Enable;
2548#endif
2549
2550#ifdef ENABLE_DOT11D
2551 dst->CountryIeLen = src->CountryIeLen;
2552 memcpy(dst->CountryIeBuf, src->CountryIeBuf, src->CountryIeLen);
2553#endif
2554
2555 //added by amy for LEAP
2556 dst->bWithAironetIE = src->bWithAironetIE;
2557 dst->bCkipSupported = src->bCkipSupported;
2558 memcpy(dst->CcxRmState,src->CcxRmState,2);
2559 dst->bCcxRmEnable = src->bCcxRmEnable;
2560 dst->MBssidMask = src->MBssidMask;
2561 dst->bMBssidValid = src->bMBssidValid;
2562 memcpy(dst->MBssid,src->MBssid,6);
2563 dst->bWithCcxVerNum = src->bWithCcxVerNum;
2564 dst->BssCcxVerNumber = src->BssCcxVerNumber;
2565
2566}
2567
2568static inline int is_beacon(__le16 fc)
2569{
2570 return (WLAN_FC_GET_STYPE(le16_to_cpu(fc)) == IEEE80211_STYPE_BEACON);
2571}
2572
2573static inline void ieee80211_process_probe_response(
2574 struct ieee80211_device *ieee,
2575 struct ieee80211_probe_response *beacon,
2576 struct ieee80211_rx_stats *stats)
2577{
2578 struct ieee80211_network network;
2579 struct ieee80211_network *target;
2580 struct ieee80211_network *oldest = NULL;
2581#ifdef CONFIG_IEEE80211_DEBUG
2582 struct ieee80211_info_element *info_element = &beacon->info_element[0];
2583#endif
2584 unsigned long flags;
2585 short renew;
2586 //u8 wmm_info;
2587
2588 memset(&network, 0, sizeof(struct ieee80211_network));
2589 IEEE80211_DEBUG_SCAN(
2590 "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n",
2591 escape_essid(info_element->data, info_element->len),
2592 MAC_ARG(beacon->header.addr3),
2593 (beacon->capability & (1<<0xf)) ? '1' : '0',
2594 (beacon->capability & (1<<0xe)) ? '1' : '0',
2595 (beacon->capability & (1<<0xd)) ? '1' : '0',
2596 (beacon->capability & (1<<0xc)) ? '1' : '0',
2597 (beacon->capability & (1<<0xb)) ? '1' : '0',
2598 (beacon->capability & (1<<0xa)) ? '1' : '0',
2599 (beacon->capability & (1<<0x9)) ? '1' : '0',
2600 (beacon->capability & (1<<0x8)) ? '1' : '0',
2601 (beacon->capability & (1<<0x7)) ? '1' : '0',
2602 (beacon->capability & (1<<0x6)) ? '1' : '0',
2603 (beacon->capability & (1<<0x5)) ? '1' : '0',
2604 (beacon->capability & (1<<0x4)) ? '1' : '0',
2605 (beacon->capability & (1<<0x3)) ? '1' : '0',
2606 (beacon->capability & (1<<0x2)) ? '1' : '0',
2607 (beacon->capability & (1<<0x1)) ? '1' : '0',
2608 (beacon->capability & (1<<0x0)) ? '1' : '0');
2609
2610 if (ieee80211_network_init(ieee, beacon, &network, stats)) {
2611 IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n",
2612 escape_essid(info_element->data,
2613 info_element->len),
2614 MAC_ARG(beacon->header.addr3),
2615 WLAN_FC_GET_STYPE(beacon->header.frame_ctl) ==
2616 IEEE80211_STYPE_PROBE_RESP ?
2617 "PROBE RESPONSE" : "BEACON");
2618 return;
2619 }
2620
2621#ifdef ENABLE_DOT11D
2622 // For Asus EeePc request,
2623 // (1) if wireless adapter receive get any 802.11d country code in AP beacon,
2624 // wireless adapter should follow the country code.
2625 // (2) If there is no any country code in beacon,
2626 // then wireless adapter should do active scan from ch1~11 and
2627 // passive scan from ch12~14
2628
2629 if( !IsLegalChannel(ieee, network.channel) )
2630 return;
2631 if(ieee->bGlobalDomain)
2632 {
2633 if (WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP)
2634 {
2635 // Case 1: Country code
2636 if(IS_COUNTRY_IE_VALID(ieee) )
2637 {
2638 if( !IsLegalChannel(ieee, network.channel) )
2639 {
2640 printk("GetScanInfo(): For Country code, filter probe response at channel(%d).\n", network.channel);
2641 return;
2642 }
2643 }
2644 // Case 2: No any country code.
2645 else
2646 {
2647 // Filter over channel ch12~14
2648 if(network.channel > 11)
2649 {
2650 printk("GetScanInfo(): For Global Domain, filter probe response at channel(%d).\n", network.channel);
2651 return;
2652 }
2653 }
2654 }
2655 else
2656 {
2657 // Case 1: Country code
2658 if(IS_COUNTRY_IE_VALID(ieee) )
2659 {
2660 if( !IsLegalChannel(ieee, network.channel) )
2661 {
2662 printk("GetScanInfo(): For Country code, filter beacon at channel(%d).\n",network.channel);
2663 return;
2664 }
2665 }
2666 // Case 2: No any country code.
2667 else
2668 {
2669 // Filter over channel ch12~14
2670 if(network.channel > 14)
2671 {
2672 printk("GetScanInfo(): For Global Domain, filter beacon at channel(%d).\n",network.channel);
2673 return;
2674 }
2675 }
2676 }
2677 }
2678#endif
2679
2680 /* The network parsed correctly -- so now we scan our known networks
2681 * to see if we can find it in our list.
2682 *
2683 * NOTE: This search is definitely not optimized. Once its doing
2684 * the "right thing" we'll optimize it for efficiency if
2685 * necessary */
2686
2687 /* Search for this entry in the list and update it if it is
2688 * already there. */
2689
2690 spin_lock_irqsave(&ieee->lock, flags);
2691
2692 if(is_same_network(&ieee->current_network, &network, ieee)) {
2693 update_network(&ieee->current_network, &network);
2694 if((ieee->current_network.mode == IEEE_N_24G || ieee->current_network.mode == IEEE_G)
2695 && ieee->current_network.berp_info_valid){
2696 if(ieee->current_network.erp_value& ERP_UseProtection)
2697 ieee->current_network.buseprotection = true;
2698 else
2699 ieee->current_network.buseprotection = false;
2700 }
2701 if(is_beacon(beacon->header.frame_ctl))
2702 {
2703 if(ieee->state == IEEE80211_LINKED)
2704 ieee->LinkDetectInfo.NumRecvBcnInPeriod++;
2705 }
2706 else //hidden AP
2707 network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & ieee->current_network.flags);
2708 }
2709
2710 list_for_each_entry(target, &ieee->network_list, list) {
2711 if (is_same_network(target, &network, ieee))
2712 break;
2713 if ((oldest == NULL) ||
2714 (target->last_scanned < oldest->last_scanned))
2715 oldest = target;
2716 }
2717
2718 /* If we didn't find a match, then get a new network slot to initialize
2719 * with this beacon's information */
2720 if (&target->list == &ieee->network_list) {
2721 if (list_empty(&ieee->network_free_list)) {
2722 /* If there are no more slots, expire the oldest */
2723 list_del(&oldest->list);
2724 target = oldest;
2725 IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from "
2726 "network list.\n",
2727 escape_essid(target->ssid,
2728 target->ssid_len),
2729 MAC_ARG(target->bssid));
2730 } else {
2731 /* Otherwise just pull from the free list */
2732 target = list_entry(ieee->network_free_list.next,
2733 struct ieee80211_network, list);
2734 list_del(ieee->network_free_list.next);
2735 }
2736
2737
2738#ifdef CONFIG_IEEE80211_DEBUG
2739 IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n",
2740 escape_essid(network.ssid,
2741 network.ssid_len),
2742 MAC_ARG(network.bssid),
2743 WLAN_FC_GET_STYPE(beacon->header.frame_ctl) ==
2744 IEEE80211_STYPE_PROBE_RESP ?
2745 "PROBE RESPONSE" : "BEACON");
2746#endif
2747 memcpy(target, &network, sizeof(*target));
2748 list_add_tail(&target->list, &ieee->network_list);
2749 if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE)
2750 ieee80211_softmac_new_net(ieee,&network);
2751 } else {
2752 IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n",
2753 escape_essid(target->ssid,
2754 target->ssid_len),
2755 MAC_ARG(target->bssid),
2756 WLAN_FC_GET_STYPE(beacon->header.frame_ctl) ==
2757 IEEE80211_STYPE_PROBE_RESP ?
2758 "PROBE RESPONSE" : "BEACON");
2759
2760 /* we have an entry and we are going to update it. But this entry may
2761 * be already expired. In this case we do the same as we found a new
2762 * net and call the new_net handler
2763 */
2764 renew = !time_after(target->last_scanned + ieee->scan_age, jiffies);
2765 //YJ,add,080819,for hidden ap
2766 if(is_beacon(beacon->header.frame_ctl) == 0)
2767 network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & target->flags);
2768 //if(strncmp(network.ssid, "linksys-c",9) == 0)
2769 // printk("====>2 network.ssid=%s FLAG=%d target.ssid=%s FLAG=%d\n", network.ssid, network.flags, target->ssid, target->flags);
2770 if(((network.flags & NETWORK_EMPTY_ESSID) == NETWORK_EMPTY_ESSID) \
2771 && (((network.ssid_len > 0) && (strncmp(target->ssid, network.ssid, network.ssid_len)))\
2772 ||((ieee->current_network.ssid_len == network.ssid_len)&&(strncmp(ieee->current_network.ssid, network.ssid, network.ssid_len) == 0)&&(ieee->state == IEEE80211_NOLINK))))
2773 renew = 1;
2774 //YJ,add,080819,for hidden ap,end
2775
2776 update_network(target, &network);
2777 if(renew && (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE))
2778 ieee80211_softmac_new_net(ieee,&network);
2779 }
2780
2781 spin_unlock_irqrestore(&ieee->lock, flags);
2782 if (is_beacon(beacon->header.frame_ctl)&&is_same_network(&ieee->current_network, &network, ieee)&&\
2783 (ieee->state == IEEE80211_LINKED)) {
2784 if(ieee->handle_beacon != NULL) {
2785 ieee->handle_beacon(ieee->dev,beacon,&ieee->current_network);
2786 }
2787 }
2788}
2789
2790void ieee80211_rx_mgt(struct ieee80211_device *ieee,
2791 struct ieee80211_hdr_4addr *header,
2792 struct ieee80211_rx_stats *stats)
2793{
2794 if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED &&
2795 ieee->iw_mode == IW_MODE_INFRA &&
2796 ieee->state == IEEE80211_LINKED))
2797 {
2798 tasklet_schedule(&ieee->ps_task);
2799 }
2800
2801 if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP &&
2802 WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON)
2803 ieee->last_rx_ps_time = jiffies;
2804
2805 switch (WLAN_FC_GET_STYPE(header->frame_ctl)) {
2806
2807 case IEEE80211_STYPE_BEACON:
2808 IEEE80211_DEBUG_MGMT("received BEACON (%d)\n",
2809 WLAN_FC_GET_STYPE(header->frame_ctl));
2810 IEEE80211_DEBUG_SCAN("Beacon\n");
2811 ieee80211_process_probe_response(
2812 ieee, (struct ieee80211_probe_response *)header, stats);
2813 break;
2814
2815 case IEEE80211_STYPE_PROBE_RESP:
2816 IEEE80211_DEBUG_MGMT("received PROBE RESPONSE (%d)\n",
2817 WLAN_FC_GET_STYPE(header->frame_ctl));
2818 IEEE80211_DEBUG_SCAN("Probe response\n");
2819 ieee80211_process_probe_response(
2820 ieee, (struct ieee80211_probe_response *)header, stats);
2821 break;
2822
2823 }
2824}
2825
2826#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
2827EXPORT_SYMBOL(ieee80211_rx_mgt);
2828EXPORT_SYMBOL(ieee80211_rx);
2829#else
2830EXPORT_SYMBOL_NOVERS(ieee80211_rx_mgt);
2831EXPORT_SYMBOL_NOVERS(ieee80211_rx);
2832#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c
new file mode 100644
index 00000000000..6773e84c778
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c
@@ -0,0 +1,3580 @@
1/* IEEE 802.11 SoftMAC layer
2 * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
3 *
4 * Mostly extracted from the rtl8180-sa2400 driver for the
5 * in-kernel generic ieee802.11 stack.
6 *
7 * Few lines might be stolen from other part of the ieee80211
8 * stack. Copyright who own it's copyright
9 *
10 * WPA code stolen from the ipw2200 driver.
11 * Copyright who own it's copyright.
12 *
13 * released under the GPL
14 */
15
16
17#include "ieee80211.h"
18
19#include <linux/random.h>
20#include <linux/delay.h>
21#include <linux/version.h>
22#include <asm/uaccess.h>
23#ifdef ENABLE_DOT11D
24#include "dot11d.h"
25#endif
26
27u8 rsn_authen_cipher_suite[16][4] = {
28 {0x00,0x0F,0xAC,0x00}, //Use group key, //Reserved
29 {0x00,0x0F,0xAC,0x01}, //WEP-40 //RSNA default
30 {0x00,0x0F,0xAC,0x02}, //TKIP //NONE //{used just as default}
31 {0x00,0x0F,0xAC,0x03}, //WRAP-historical
32 {0x00,0x0F,0xAC,0x04}, //CCMP
33 {0x00,0x0F,0xAC,0x05}, //WEP-104
34};
35
36short ieee80211_is_54g(struct ieee80211_network net)
37{
38 return ((net.rates_ex_len > 0) || (net.rates_len > 4));
39}
40
41short ieee80211_is_shortslot(struct ieee80211_network net)
42{
43 return (net.capability & WLAN_CAPABILITY_SHORT_SLOT);
44}
45
46/* returns the total length needed for pleacing the RATE MFIE
47 * tag and the EXTENDED RATE MFIE tag if needed.
48 * It encludes two bytes per tag for the tag itself and its len
49 */
50unsigned int ieee80211_MFIE_rate_len(struct ieee80211_device *ieee)
51{
52 unsigned int rate_len = 0;
53
54 if (ieee->modulation & IEEE80211_CCK_MODULATION)
55 rate_len = IEEE80211_CCK_RATE_LEN + 2;
56
57 if (ieee->modulation & IEEE80211_OFDM_MODULATION)
58
59 rate_len += IEEE80211_OFDM_RATE_LEN + 2;
60
61 return rate_len;
62}
63
64/* pleace the MFIE rate, tag to the memory (double) poined.
65 * Then it updates the pointer so that
66 * it points after the new MFIE tag added.
67 */
68void ieee80211_MFIE_Brate(struct ieee80211_device *ieee, u8 **tag_p)
69{
70 u8 *tag = *tag_p;
71
72 if (ieee->modulation & IEEE80211_CCK_MODULATION){
73 *tag++ = MFIE_TYPE_RATES;
74 *tag++ = 4;
75 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB;
76 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB;
77 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB;
78 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB;
79 }
80
81 /* We may add an option for custom rates that specific HW might support */
82 *tag_p = tag;
83}
84
85void ieee80211_MFIE_Grate(struct ieee80211_device *ieee, u8 **tag_p)
86{
87 u8 *tag = *tag_p;
88
89 if (ieee->modulation & IEEE80211_OFDM_MODULATION){
90
91 *tag++ = MFIE_TYPE_RATES_EX;
92 *tag++ = 8;
93 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB;
94 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB;
95 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB;
96 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB;
97 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB;
98 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB;
99 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB;
100 *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB;
101
102 }
103
104 /* We may add an option for custom rates that specific HW might support */
105 *tag_p = tag;
106}
107
108
109void ieee80211_WMM_Info(struct ieee80211_device *ieee, u8 **tag_p) {
110 u8 *tag = *tag_p;
111
112 *tag++ = MFIE_TYPE_GENERIC; //0
113 *tag++ = 7;
114 *tag++ = 0x00;
115 *tag++ = 0x50;
116 *tag++ = 0xf2;
117 *tag++ = 0x02;//5
118 *tag++ = 0x00;
119 *tag++ = 0x01;
120#ifdef SUPPORT_USPD
121 if(ieee->current_network.wmm_info & 0x80) {
122 *tag++ = 0x0f|MAX_SP_Len;
123 } else {
124 *tag++ = MAX_SP_Len;
125 }
126#else
127 *tag++ = MAX_SP_Len;
128#endif
129 *tag_p = tag;
130}
131
132#ifdef THOMAS_TURBO
133void ieee80211_TURBO_Info(struct ieee80211_device *ieee, u8 **tag_p) {
134 u8 *tag = *tag_p;
135
136 *tag++ = MFIE_TYPE_GENERIC; //0
137 *tag++ = 7;
138 *tag++ = 0x00;
139 *tag++ = 0xe0;
140 *tag++ = 0x4c;
141 *tag++ = 0x01;//5
142 *tag++ = 0x02;
143 *tag++ = 0x11;
144 *tag++ = 0x00;
145
146 *tag_p = tag;
147 printk(KERN_ALERT "This is enable turbo mode IE process\n");
148}
149#endif
150
151void enqueue_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb)
152{
153 int nh;
154 nh = (ieee->mgmt_queue_head +1) % MGMT_QUEUE_NUM;
155
156/*
157 * if the queue is full but we have newer frames then
158 * just overwrites the oldest.
159 *
160 * if (nh == ieee->mgmt_queue_tail)
161 * return -1;
162 */
163 ieee->mgmt_queue_head = nh;
164 ieee->mgmt_queue_ring[nh] = skb;
165
166 //return 0;
167}
168
169struct sk_buff *dequeue_mgmt(struct ieee80211_device *ieee)
170{
171 struct sk_buff *ret;
172
173 if(ieee->mgmt_queue_tail == ieee->mgmt_queue_head)
174 return NULL;
175
176 ret = ieee->mgmt_queue_ring[ieee->mgmt_queue_tail];
177
178 ieee->mgmt_queue_tail =
179 (ieee->mgmt_queue_tail+1) % MGMT_QUEUE_NUM;
180
181 return ret;
182}
183
184void init_mgmt_queue(struct ieee80211_device *ieee)
185{
186 ieee->mgmt_queue_tail = ieee->mgmt_queue_head = 0;
187}
188
189u8 MgntQuery_MgntFrameTxRate(struct ieee80211_device *ieee)
190{
191 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
192 u8 rate;
193
194 // 2008/01/25 MH For broadcom, MGNT frame set as OFDM 6M.
195 if(pHTInfo->IOTAction & HT_IOT_ACT_MGNT_USE_CCK_6M)
196 rate = 0x0c;
197 else
198 rate = ieee->basic_rate & 0x7f;
199
200 if(rate == 0){
201 // 2005.01.26, by rcnjko.
202 if(ieee->mode == IEEE_A||
203 ieee->mode== IEEE_N_5G||
204 (ieee->mode== IEEE_N_24G&&!pHTInfo->bCurSuppCCK))
205 rate = 0x0c;
206 else
207 rate = 0x02;
208 }
209
210 /*
211 // Data rate of ProbeReq is already decided. Annie, 2005-03-31
212 if( pMgntInfo->bScanInProgress || (pMgntInfo->bDualModeScanStep!=0) )
213 {
214 if(pMgntInfo->dot11CurrentWirelessMode==WIRELESS_MODE_A)
215 rate = 0x0c;
216 else
217 rate = 0x02;
218 }
219 */
220 return rate;
221}
222
223
224void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl);
225
226inline void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee)
227{
228 unsigned long flags;
229 short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE;
230 struct ieee80211_hdr_3addr *header=
231 (struct ieee80211_hdr_3addr *) skb->data;
232
233 cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8);
234 spin_lock_irqsave(&ieee->lock, flags);
235
236 /* called with 2nd param 0, no mgmt lock required */
237 ieee80211_sta_wakeup(ieee,0);
238
239 tcb_desc->queue_index = MGNT_QUEUE;
240 tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee);
241 tcb_desc->RATRIndex = 7;
242 tcb_desc->bTxDisableRateFallBack = 1;
243 tcb_desc->bTxUseDriverAssingedRate = 1;
244
245 if(single){
246 if(ieee->queue_stop){
247 enqueue_mgmt(ieee,skb);
248 }else{
249 header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4);
250
251 if (ieee->seq_ctrl[0] == 0xFFF)
252 ieee->seq_ctrl[0] = 0;
253 else
254 ieee->seq_ctrl[0]++;
255
256 /* avoid watchdog triggers */
257 // ieee->dev->trans_start = jiffies;
258 ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate);
259 //dev_kfree_skb_any(skb);//edit by thomas
260 }
261
262 spin_unlock_irqrestore(&ieee->lock, flags);
263 }else{
264 spin_unlock_irqrestore(&ieee->lock, flags);
265 spin_lock_irqsave(&ieee->mgmt_tx_lock, flags);
266
267 header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4);
268
269 if (ieee->seq_ctrl[0] == 0xFFF)
270 ieee->seq_ctrl[0] = 0;
271 else
272 ieee->seq_ctrl[0]++;
273
274 /* check wether the managed packet queued greater than 5 */
275 if(!ieee->check_nic_enough_desc(ieee->dev,tcb_desc->queue_index)||\
276 (skb_queue_len(&ieee->skb_waitQ[tcb_desc->queue_index]) != 0)||\
277 (ieee->queue_stop) ) {
278 /* insert the skb packet to the management queue */
279 /* as for the completion function, it does not need
280 * to check it any more.
281 * */
282 printk("%s():insert to waitqueue!\n",__FUNCTION__);
283 skb_queue_tail(&ieee->skb_waitQ[tcb_desc->queue_index], skb);
284 } else {
285 //printk("TX packet!\n");
286 ieee->softmac_hard_start_xmit(skb,ieee->dev);
287 //dev_kfree_skb_any(skb);//edit by thomas
288 }
289 spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags);
290 }
291}
292
293inline void softmac_ps_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee)
294{
295
296 short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE;
297 struct ieee80211_hdr_3addr *header =
298 (struct ieee80211_hdr_3addr *) skb->data;
299 cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8);
300
301 tcb_desc->queue_index = MGNT_QUEUE;
302 tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee);
303 tcb_desc->RATRIndex = 7;
304 tcb_desc->bTxDisableRateFallBack = 1;
305 tcb_desc->bTxUseDriverAssingedRate = 1;
306 //printk("=============>%s()\n", __FUNCTION__);
307 if(single){
308
309 header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4);
310
311 if (ieee->seq_ctrl[0] == 0xFFF)
312 ieee->seq_ctrl[0] = 0;
313 else
314 ieee->seq_ctrl[0]++;
315
316 /* avoid watchdog triggers */
317 // ieee->dev->trans_start = jiffies;
318 ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate);
319
320 }else{
321
322 header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4);
323
324 if (ieee->seq_ctrl[0] == 0xFFF)
325 ieee->seq_ctrl[0] = 0;
326 else
327 ieee->seq_ctrl[0]++;
328
329 ieee->softmac_hard_start_xmit(skb,ieee->dev);
330
331 }
332 //dev_kfree_skb_any(skb);//edit by thomas
333}
334
335inline struct sk_buff *ieee80211_probe_req(struct ieee80211_device *ieee)
336{
337 unsigned int len,rate_len;
338 u8 *tag;
339 struct sk_buff *skb;
340 struct ieee80211_probe_request *req;
341
342 len = ieee->current_network.ssid_len;
343
344 rate_len = ieee80211_MFIE_rate_len(ieee);
345
346 skb = dev_alloc_skb(sizeof(struct ieee80211_probe_request) +
347 2 + len + rate_len + ieee->tx_headroom);
348 if (!skb)
349 return NULL;
350
351 skb_reserve(skb, ieee->tx_headroom);
352
353 req = (struct ieee80211_probe_request *) skb_put(skb,sizeof(struct ieee80211_probe_request));
354 req->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
355 req->header.duration_id = 0; //FIXME: is this OK ?
356
357 memset(req->header.addr1, 0xff, ETH_ALEN);
358 memcpy(req->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
359 memset(req->header.addr3, 0xff, ETH_ALEN);
360
361 tag = (u8 *) skb_put(skb,len+2+rate_len);
362
363 *tag++ = MFIE_TYPE_SSID;
364 *tag++ = len;
365 memcpy(tag, ieee->current_network.ssid, len);
366 tag += len;
367
368 ieee80211_MFIE_Brate(ieee,&tag);
369 ieee80211_MFIE_Grate(ieee,&tag);
370 return skb;
371}
372
373struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee);
374void ieee80211_send_beacon(struct ieee80211_device *ieee)
375{
376 struct sk_buff *skb;
377 if(!ieee->ieee_up)
378 return;
379 //unsigned long flags;
380 skb = ieee80211_get_beacon_(ieee);
381
382 if (skb){
383 softmac_mgmt_xmit(skb, ieee);
384 ieee->softmac_stats.tx_beacons++;
385 //dev_kfree_skb_any(skb);//edit by thomas
386 }
387// ieee->beacon_timer.expires = jiffies +
388// (MSECS( ieee->current_network.beacon_interval -5));
389
390 //spin_lock_irqsave(&ieee->beacon_lock,flags);
391 if(ieee->beacon_txing && ieee->ieee_up){
392// if(!timer_pending(&ieee->beacon_timer))
393// add_timer(&ieee->beacon_timer);
394 mod_timer(&ieee->beacon_timer,jiffies+(MSECS(ieee->current_network.beacon_interval-5)));
395 }
396 //spin_unlock_irqrestore(&ieee->beacon_lock,flags);
397}
398
399
400void ieee80211_send_beacon_cb(unsigned long _ieee)
401{
402 struct ieee80211_device *ieee =
403 (struct ieee80211_device *) _ieee;
404 unsigned long flags;
405
406 spin_lock_irqsave(&ieee->beacon_lock, flags);
407 ieee80211_send_beacon(ieee);
408 spin_unlock_irqrestore(&ieee->beacon_lock, flags);
409}
410
411
412void ieee80211_send_probe(struct ieee80211_device *ieee)
413{
414 struct sk_buff *skb;
415
416 skb = ieee80211_probe_req(ieee);
417 if (skb){
418 softmac_mgmt_xmit(skb, ieee);
419 ieee->softmac_stats.tx_probe_rq++;
420 //dev_kfree_skb_any(skb);//edit by thomas
421 }
422}
423
424void ieee80211_send_probe_requests(struct ieee80211_device *ieee)
425{
426 if (ieee->active_scan && (ieee->softmac_features & IEEE_SOFTMAC_PROBERQ)){
427 ieee80211_send_probe(ieee);
428 ieee80211_send_probe(ieee);
429 }
430}
431
432/* this performs syncro scan blocking the caller until all channels
433 * in the allowed channel map has been checked.
434 */
435void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee)
436{
437 short ch = 0;
438#ifdef ENABLE_DOT11D
439 u8 channel_map[MAX_CHANNEL_NUMBER+1];
440 memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1);
441#endif
442 ieee->be_scan_inprogress = true;
443 down(&ieee->scan_sem);
444
445 while(1)
446 {
447
448 do{
449 ch++;
450 if (ch > MAX_CHANNEL_NUMBER)
451 goto out; /* scan completed */
452#ifdef ENABLE_DOT11D
453 }while(!channel_map[ch]);
454#else
455 }while(!ieee->channel_map[ch]);
456#endif
457
458 /* this fuction can be called in two situations
459 * 1- We have switched to ad-hoc mode and we are
460 * performing a complete syncro scan before conclude
461 * there are no interesting cell and to create a
462 * new one. In this case the link state is
463 * IEEE80211_NOLINK until we found an interesting cell.
464 * If so the ieee8021_new_net, called by the RX path
465 * will set the state to IEEE80211_LINKED, so we stop
466 * scanning
467 * 2- We are linked and the root uses run iwlist scan.
468 * So we switch to IEEE80211_LINKED_SCANNING to remember
469 * that we are still logically linked (not interested in
470 * new network events, despite for updating the net list,
471 * but we are temporarly 'unlinked' as the driver shall
472 * not filter RX frames and the channel is changing.
473 * So the only situation in witch are interested is to check
474 * if the state become LINKED because of the #1 situation
475 */
476
477 if (ieee->state == IEEE80211_LINKED)
478 goto out;
479 ieee->set_chan(ieee->dev, ch);
480#ifdef ENABLE_DOT11D
481 if(channel_map[ch] == 1)
482#endif
483 ieee80211_send_probe_requests(ieee);
484
485 /* this prevent excessive time wait when we
486 * need to wait for a syncro scan to end..
487 */
488 if(ieee->state < IEEE80211_LINKED)
489 ;
490 else
491 if (ieee->sync_scan_hurryup)
492 goto out;
493
494
495 msleep_interruptible_rsl(IEEE80211_SOFTMAC_SCAN_TIME);
496
497 }
498out:
499 if(ieee->state < IEEE80211_LINKED){
500 ieee->actscanning = false;
501 up(&ieee->scan_sem);
502 ieee->be_scan_inprogress = false;
503 }
504 else{
505 ieee->sync_scan_hurryup = 0;
506#ifdef ENABLE_DOT11D
507 if(IS_DOT11D_ENABLE(ieee))
508 DOT11D_ScanComplete(ieee);
509#endif
510 up(&ieee->scan_sem);
511 ieee->be_scan_inprogress = false;
512}
513}
514
515#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
516/* called both by wq with ieee->lock held */
517void ieee80211_softmac_scan(struct ieee80211_device *ieee)
518{
519#if 0
520 short watchdog = 0;
521 do{
522 ieee->current_network.channel =
523 (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER;
524 if (watchdog++ > MAX_CHANNEL_NUMBER)
525 return; /* no good chans */
526
527 }while(!ieee->channel_map[ieee->current_network.channel]);
528#endif
529
530 schedule_task(&ieee->softmac_scan_wq);
531}
532#endif
533
534#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
535void ieee80211_softmac_scan_wq(struct work_struct *work)
536{
537 struct delayed_work *dwork = container_of(work, struct delayed_work, work);
538 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, softmac_scan_wq);
539#else
540void ieee80211_softmac_scan_wq(struct ieee80211_device *ieee)
541{
542#endif
543 u8 last_channel = ieee->current_network.channel; //recored init channel inorder not change current channel when comming out the scan unexpectedly. WB.
544#ifdef ENABLE_DOT11D
545 u8 channel_map[MAX_CHANNEL_NUMBER+1];
546 memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1);
547#endif
548 if(!ieee->ieee_up)
549 return;
550 down(&ieee->scan_sem);
551 do{
552 ieee->current_network.channel =
553 (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER;
554 if (ieee->scan_watch_dog++ > MAX_CHANNEL_NUMBER)
555 {
556 //if current channel is not in channel map, set to default channel.
557 #ifdef ENABLE_DOT11D
558 if (!channel_map[ieee->current_network.channel]);
559 #else
560 if (!ieee->channel_map[ieee->current_network.channel]);
561 #endif
562 ieee->current_network.channel = 6;
563 goto out; /* no good chans */
564 }
565#ifdef ENABLE_DOT11D
566 }while(!channel_map[ieee->current_network.channel]);
567#else
568 }while(!ieee->channel_map[ieee->current_network.channel]);
569#endif
570 if (ieee->scanning == 0 )
571 goto out;
572 ieee->set_chan(ieee->dev, ieee->current_network.channel);
573#ifdef ENABLE_DOT11D
574 if(channel_map[ieee->current_network.channel] == 1)
575#endif
576 ieee80211_send_probe_requests(ieee);
577
578
579#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
580 queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, IEEE80211_SOFTMAC_SCAN_TIME);
581#else
582 //ieee->scan_timer.expires = jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME);
583 if (ieee->scanning == 1)
584 mod_timer(&ieee->scan_timer,(jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME)));
585#endif
586
587 up(&ieee->scan_sem);
588 return;
589out:
590#ifdef ENABLE_DOT11D
591 if(IS_DOT11D_ENABLE(ieee))
592 DOT11D_ScanComplete(ieee);
593#endif
594 ieee->current_network.channel = last_channel;
595 ieee->actscanning = false;
596 ieee->scan_watch_dog = 0;
597 ieee->scanning = 0;
598 up(&ieee->scan_sem);
599}
600
601#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
602void ieee80211_softmac_scan_cb(unsigned long _dev)
603{
604 unsigned long flags;
605 struct ieee80211_device *ieee = (struct ieee80211_device *)_dev;
606
607 spin_lock_irqsave(&ieee->lock, flags);
608 ieee80211_softmac_scan(ieee);
609 spin_unlock_irqrestore(&ieee->lock, flags);
610}
611#endif
612
613
614void ieee80211_beacons_start(struct ieee80211_device *ieee)
615{
616 unsigned long flags;
617 spin_lock_irqsave(&ieee->beacon_lock,flags);
618
619 ieee->beacon_txing = 1;
620 ieee80211_send_beacon(ieee);
621
622 spin_unlock_irqrestore(&ieee->beacon_lock,flags);
623}
624
625void ieee80211_beacons_stop(struct ieee80211_device *ieee)
626{
627 unsigned long flags;
628
629 spin_lock_irqsave(&ieee->beacon_lock,flags);
630
631 ieee->beacon_txing = 0;
632 del_timer_sync(&ieee->beacon_timer);
633
634 spin_unlock_irqrestore(&ieee->beacon_lock,flags);
635
636}
637
638
639void ieee80211_stop_send_beacons(struct ieee80211_device *ieee)
640{
641 if(ieee->stop_send_beacons)
642 ieee->stop_send_beacons(ieee->dev);
643 if (ieee->softmac_features & IEEE_SOFTMAC_BEACONS)
644 ieee80211_beacons_stop(ieee);
645}
646
647
648void ieee80211_start_send_beacons(struct ieee80211_device *ieee)
649{
650 if(ieee->start_send_beacons)
651 ieee->start_send_beacons(ieee->dev);
652 if(ieee->softmac_features & IEEE_SOFTMAC_BEACONS)
653 ieee80211_beacons_start(ieee);
654}
655
656
657void ieee80211_softmac_stop_scan(struct ieee80211_device *ieee)
658{
659// unsigned long flags;
660
661 //ieee->sync_scan_hurryup = 1;
662
663 down(&ieee->scan_sem);
664// spin_lock_irqsave(&ieee->lock, flags);
665 ieee->scan_watch_dog = 0;
666 if (ieee->scanning == 1){
667 ieee->scanning = 0;
668
669#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
670 cancel_delayed_work(&ieee->softmac_scan_wq);
671#else
672 del_timer_sync(&ieee->scan_timer);
673#endif
674 }
675
676// spin_unlock_irqrestore(&ieee->lock, flags);
677 up(&ieee->scan_sem);
678}
679
680void ieee80211_stop_scan(struct ieee80211_device *ieee)
681{
682 if (ieee->softmac_features & IEEE_SOFTMAC_SCAN)
683 ieee80211_softmac_stop_scan(ieee);
684 else
685 ieee->stop_scan(ieee->dev);
686}
687
688/* called with ieee->lock held */
689void ieee80211_start_scan(struct ieee80211_device *ieee)
690{
691#ifdef ENABLE_DOT11D
692 if(IS_DOT11D_ENABLE(ieee) )
693 {
694 if(IS_COUNTRY_IE_VALID(ieee))
695 {
696 RESET_CIE_WATCHDOG(ieee);
697 }
698 }
699#endif
700 if (ieee->softmac_features & IEEE_SOFTMAC_SCAN){
701 if (ieee->scanning == 0){
702 ieee->scanning = 1;
703#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
704#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
705 queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, 0);
706#else
707
708 queue_work(ieee->wq, &ieee->softmac_scan_wq);
709#endif
710#else
711 ieee80211_softmac_scan(ieee);
712#endif
713 }
714 }else
715 ieee->start_scan(ieee->dev);
716
717}
718
719/* called with wx_sem held */
720void ieee80211_start_scan_syncro(struct ieee80211_device *ieee)
721{
722#ifdef ENABLE_DOT11D
723 if(IS_DOT11D_ENABLE(ieee) )
724 {
725 if(IS_COUNTRY_IE_VALID(ieee))
726 {
727 RESET_CIE_WATCHDOG(ieee);
728 }
729 }
730#endif
731 ieee->sync_scan_hurryup = 0;
732 if (ieee->softmac_features & IEEE_SOFTMAC_SCAN)
733 ieee80211_softmac_scan_syncro(ieee);
734 else
735 ieee->scan_syncro(ieee->dev);
736
737}
738
739inline struct sk_buff *ieee80211_authentication_req(struct ieee80211_network *beacon,
740 struct ieee80211_device *ieee, int challengelen)
741{
742 struct sk_buff *skb;
743 struct ieee80211_authentication *auth;
744 int len = sizeof(struct ieee80211_authentication) + challengelen + ieee->tx_headroom;
745
746
747 skb = dev_alloc_skb(len);
748 if (!skb) return NULL;
749
750 skb_reserve(skb, ieee->tx_headroom);
751 auth = (struct ieee80211_authentication *)
752 skb_put(skb, sizeof(struct ieee80211_authentication));
753
754 auth->header.frame_ctl = IEEE80211_STYPE_AUTH;
755 if (challengelen) auth->header.frame_ctl |= IEEE80211_FCTL_WEP;
756
757 auth->header.duration_id = 0x013a; //FIXME
758
759 memcpy(auth->header.addr1, beacon->bssid, ETH_ALEN);
760 memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
761 memcpy(auth->header.addr3, beacon->bssid, ETH_ALEN);
762
763 //auth->algorithm = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY;
764 if(ieee->auth_mode == 0)
765 auth->algorithm = WLAN_AUTH_OPEN;
766 else if(ieee->auth_mode == 1)
767 auth->algorithm = WLAN_AUTH_SHARED_KEY;
768 else if(ieee->auth_mode == 2)
769 auth->algorithm = WLAN_AUTH_OPEN;//0x80;
770 printk("=================>%s():auth->algorithm is %d\n",__FUNCTION__,auth->algorithm);
771 auth->transaction = cpu_to_le16(ieee->associate_seq);
772 ieee->associate_seq++;
773
774 auth->status = cpu_to_le16(WLAN_STATUS_SUCCESS);
775
776 return skb;
777
778}
779
780
781static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *dest)
782{
783 u8 *tag;
784 int beacon_size;
785 struct ieee80211_probe_response *beacon_buf;
786 struct sk_buff *skb = NULL;
787 int encrypt;
788 int atim_len,erp_len;
789 struct ieee80211_crypt_data* crypt;
790
791 char *ssid = ieee->current_network.ssid;
792 int ssid_len = ieee->current_network.ssid_len;
793 int rate_len = ieee->current_network.rates_len+2;
794 int rate_ex_len = ieee->current_network.rates_ex_len;
795 int wpa_ie_len = ieee->wpa_ie_len;
796 u8 erpinfo_content = 0;
797
798 u8* tmp_ht_cap_buf;
799 u8 tmp_ht_cap_len=0;
800 u8* tmp_ht_info_buf;
801 u8 tmp_ht_info_len=0;
802 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
803 u8* tmp_generic_ie_buf=NULL;
804 u8 tmp_generic_ie_len=0;
805
806 if(rate_ex_len > 0) rate_ex_len+=2;
807
808 if(ieee->current_network.capability & WLAN_CAPABILITY_IBSS)
809 atim_len = 4;
810 else
811 atim_len = 0;
812
813#if 1
814 if(ieee80211_is_54g(ieee->current_network))
815 erp_len = 3;
816 else
817 erp_len = 0;
818#else
819 if((ieee->current_network.mode == IEEE_G)
820 ||( ieee->current_network.mode == IEEE_N_24G && ieee->pHTInfo->bCurSuppCCK)) {
821 erp_len = 3;
822 erpinfo_content = 0;
823 if(ieee->current_network.buseprotection)
824 erpinfo_content |= ERP_UseProtection;
825 }
826 else
827 erp_len = 0;
828#endif
829
830
831 crypt = ieee->crypt[ieee->tx_keyidx];
832
833
834 encrypt = ieee->host_encrypt && crypt && crypt->ops &&
835 ((0 == strcmp(crypt->ops->name, "WEP") || wpa_ie_len));
836 //HT ralated element
837#if 1
838 tmp_ht_cap_buf =(u8*) &(ieee->pHTInfo->SelfHTCap);
839 tmp_ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap);
840 tmp_ht_info_buf =(u8*) &(ieee->pHTInfo->SelfHTInfo);
841 tmp_ht_info_len = sizeof(ieee->pHTInfo->SelfHTInfo);
842 HTConstructCapabilityElement(ieee, tmp_ht_cap_buf, &tmp_ht_cap_len,encrypt);
843 HTConstructInfoElement(ieee,tmp_ht_info_buf,&tmp_ht_info_len, encrypt);
844
845
846 if(pHTInfo->bRegRT2RTAggregation)
847 {
848 tmp_generic_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer;
849 tmp_generic_ie_len = sizeof(ieee->pHTInfo->szRT2RTAggBuffer);
850 HTConstructRT2RTAggElement(ieee, tmp_generic_ie_buf, &tmp_generic_ie_len);
851 }
852// printk("===============>tmp_ht_cap_len is %d,tmp_ht_info_len is %d, tmp_generic_ie_len is %d\n",tmp_ht_cap_len,tmp_ht_info_len,tmp_generic_ie_len);
853#endif
854 beacon_size = sizeof(struct ieee80211_probe_response)+2+
855 ssid_len
856 +3 //channel
857 +rate_len
858 +rate_ex_len
859 +atim_len
860 +erp_len
861 +wpa_ie_len
862 // +tmp_ht_cap_len
863 // +tmp_ht_info_len
864 // +tmp_generic_ie_len
865// +wmm_len+2
866 +ieee->tx_headroom;
867 skb = dev_alloc_skb(beacon_size);
868 if (!skb)
869 return NULL;
870 skb_reserve(skb, ieee->tx_headroom);
871 beacon_buf = (struct ieee80211_probe_response*) skb_put(skb, (beacon_size - ieee->tx_headroom));
872 memcpy (beacon_buf->header.addr1, dest,ETH_ALEN);
873 memcpy (beacon_buf->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
874 memcpy (beacon_buf->header.addr3, ieee->current_network.bssid, ETH_ALEN);
875
876 beacon_buf->header.duration_id = 0; //FIXME
877 beacon_buf->beacon_interval =
878 cpu_to_le16(ieee->current_network.beacon_interval);
879 beacon_buf->capability =
880 cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_IBSS);
881 beacon_buf->capability |=
882 cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE); //add short preamble here
883
884 if(ieee->short_slot && (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_SLOT))
885 cpu_to_le16((beacon_buf->capability |= WLAN_CAPABILITY_SHORT_SLOT));
886
887 crypt = ieee->crypt[ieee->tx_keyidx];
888#if 0
889 encrypt = ieee->host_encrypt && crypt && crypt->ops &&
890 (0 == strcmp(crypt->ops->name, "WEP"));
891#endif
892 if (encrypt)
893 beacon_buf->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
894
895
896 beacon_buf->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_RESP);
897 beacon_buf->info_element[0].id = MFIE_TYPE_SSID;
898 beacon_buf->info_element[0].len = ssid_len;
899
900 tag = (u8*) beacon_buf->info_element[0].data;
901
902 memcpy(tag, ssid, ssid_len);
903
904 tag += ssid_len;
905
906 *(tag++) = MFIE_TYPE_RATES;
907 *(tag++) = rate_len-2;
908 memcpy(tag,ieee->current_network.rates,rate_len-2);
909 tag+=rate_len-2;
910
911 *(tag++) = MFIE_TYPE_DS_SET;
912 *(tag++) = 1;
913 *(tag++) = ieee->current_network.channel;
914
915 if(atim_len){
916 u16 val16;
917 *(tag++) = MFIE_TYPE_IBSS_SET;
918 *(tag++) = 2;
919 //*((u16*)(tag)) = cpu_to_le16(ieee->current_network.atim_window);
920 val16 = cpu_to_le16(ieee->current_network.atim_window);
921 memcpy((u8 *)tag, (u8 *)&val16, 2);
922 tag+=2;
923 }
924
925 if(erp_len){
926 *(tag++) = MFIE_TYPE_ERP;
927 *(tag++) = 1;
928 *(tag++) = erpinfo_content;
929 }
930#if 0
931 //Include High Throuput capability
932
933 *(tag++) = MFIE_TYPE_HT_CAP;
934 *(tag++) = tmp_ht_cap_len - 2;
935 memcpy(tag, tmp_ht_cap_buf, tmp_ht_cap_len - 2);
936 tag += tmp_ht_cap_len - 2;
937#endif
938 if(rate_ex_len){
939 *(tag++) = MFIE_TYPE_RATES_EX;
940 *(tag++) = rate_ex_len-2;
941 memcpy(tag,ieee->current_network.rates_ex,rate_ex_len-2);
942 tag+=rate_ex_len-2;
943 }
944
945#if 0
946 //Include High Throuput info
947
948 *(tag++) = MFIE_TYPE_HT_INFO;
949 *(tag++) = tmp_ht_info_len - 2;
950 memcpy(tag, tmp_ht_info_buf, tmp_ht_info_len -2);
951 tag += tmp_ht_info_len - 2;
952#endif
953 if (wpa_ie_len)
954 {
955 if (ieee->iw_mode == IW_MODE_ADHOC)
956 {//as Windows will set pairwise key same as the group key which is not allowed in Linux, so set this for IOT issue. WB 2008.07.07
957 memcpy(&ieee->wpa_ie[14], &ieee->wpa_ie[8], 4);
958 }
959 memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len);
960 tag += wpa_ie_len;
961 }
962
963#if 0
964 //
965 // Construct Realtek Proprietary Aggregation mode (Set AMPDU Factor to 2, 32k)
966 //
967 if(pHTInfo->bRegRT2RTAggregation)
968 {
969 (*tag++) = 0xdd;
970 (*tag++) = tmp_generic_ie_len - 2;
971 memcpy(tag,tmp_generic_ie_buf,tmp_generic_ie_len -2);
972 tag += tmp_generic_ie_len -2;
973
974 }
975#endif
976#if 0
977 if(ieee->qos_support)
978 {
979 (*tag++) = 0xdd;
980 (*tag++) = wmm_len;
981 memcpy(tag,QosOui,wmm_len);
982 tag += wmm_len;
983 }
984#endif
985 //skb->dev = ieee->dev;
986 return skb;
987}
988
989
990struct sk_buff* ieee80211_assoc_resp(struct ieee80211_device *ieee, u8 *dest)
991{
992 struct sk_buff *skb;
993 u8* tag;
994
995 struct ieee80211_crypt_data* crypt;
996 struct ieee80211_assoc_response_frame *assoc;
997 short encrypt;
998
999 unsigned int rate_len = ieee80211_MFIE_rate_len(ieee);
1000 int len = sizeof(struct ieee80211_assoc_response_frame) + rate_len + ieee->tx_headroom;
1001
1002 skb = dev_alloc_skb(len);
1003
1004 if (!skb)
1005 return NULL;
1006
1007 skb_reserve(skb, ieee->tx_headroom);
1008
1009 assoc = (struct ieee80211_assoc_response_frame *)
1010 skb_put(skb,sizeof(struct ieee80211_assoc_response_frame));
1011
1012 assoc->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP);
1013 memcpy(assoc->header.addr1, dest,ETH_ALEN);
1014 memcpy(assoc->header.addr3, ieee->dev->dev_addr, ETH_ALEN);
1015 memcpy(assoc->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
1016 assoc->capability = cpu_to_le16(ieee->iw_mode == IW_MODE_MASTER ?
1017 WLAN_CAPABILITY_BSS : WLAN_CAPABILITY_IBSS);
1018
1019
1020 if(ieee->short_slot)
1021 assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT);
1022
1023 if (ieee->host_encrypt)
1024 crypt = ieee->crypt[ieee->tx_keyidx];
1025 else crypt = NULL;
1026
1027 encrypt = ( crypt && crypt->ops);
1028
1029 if (encrypt)
1030 assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
1031
1032 assoc->status = 0;
1033 assoc->aid = cpu_to_le16(ieee->assoc_id);
1034 if (ieee->assoc_id == 0x2007) ieee->assoc_id=0;
1035 else ieee->assoc_id++;
1036
1037 tag = (u8*) skb_put(skb, rate_len);
1038
1039 ieee80211_MFIE_Brate(ieee, &tag);
1040 ieee80211_MFIE_Grate(ieee, &tag);
1041
1042 return skb;
1043}
1044
1045struct sk_buff* ieee80211_auth_resp(struct ieee80211_device *ieee,int status, u8 *dest)
1046{
1047 struct sk_buff *skb;
1048 struct ieee80211_authentication *auth;
1049 int len = ieee->tx_headroom + sizeof(struct ieee80211_authentication)+1;
1050
1051 skb = dev_alloc_skb(len);
1052
1053 if (!skb)
1054 return NULL;
1055
1056 skb->len = sizeof(struct ieee80211_authentication);
1057
1058 auth = (struct ieee80211_authentication *)skb->data;
1059
1060 auth->status = cpu_to_le16(status);
1061 auth->transaction = cpu_to_le16(2);
1062 auth->algorithm = cpu_to_le16(WLAN_AUTH_OPEN);
1063
1064 memcpy(auth->header.addr3, ieee->dev->dev_addr, ETH_ALEN);
1065 memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
1066 memcpy(auth->header.addr1, dest, ETH_ALEN);
1067 auth->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_AUTH);
1068 return skb;
1069
1070
1071}
1072
1073struct sk_buff* ieee80211_null_func(struct ieee80211_device *ieee,short pwr)
1074{
1075 struct sk_buff *skb;
1076 struct ieee80211_hdr_3addr* hdr;
1077
1078 skb = dev_alloc_skb(sizeof(struct ieee80211_hdr_3addr));
1079
1080 if (!skb)
1081 return NULL;
1082
1083 hdr = (struct ieee80211_hdr_3addr*)skb_put(skb,sizeof(struct ieee80211_hdr_3addr));
1084
1085 memcpy(hdr->addr1, ieee->current_network.bssid, ETH_ALEN);
1086 memcpy(hdr->addr2, ieee->dev->dev_addr, ETH_ALEN);
1087 memcpy(hdr->addr3, ieee->current_network.bssid, ETH_ALEN);
1088
1089 hdr->frame_ctl = cpu_to_le16(IEEE80211_FTYPE_DATA |
1090 IEEE80211_STYPE_NULLFUNC | IEEE80211_FCTL_TODS |
1091 (pwr ? IEEE80211_FCTL_PM:0));
1092
1093 return skb;
1094
1095
1096}
1097
1098
1099void ieee80211_resp_to_assoc_rq(struct ieee80211_device *ieee, u8* dest)
1100{
1101 struct sk_buff *buf = ieee80211_assoc_resp(ieee, dest);
1102
1103 if (buf)
1104 softmac_mgmt_xmit(buf, ieee);
1105}
1106
1107
1108void ieee80211_resp_to_auth(struct ieee80211_device *ieee, int s, u8* dest)
1109{
1110 struct sk_buff *buf = ieee80211_auth_resp(ieee, s, dest);
1111
1112 if (buf)
1113 softmac_mgmt_xmit(buf, ieee);
1114}
1115
1116
1117void ieee80211_resp_to_probe(struct ieee80211_device *ieee, u8 *dest)
1118{
1119
1120
1121 struct sk_buff *buf = ieee80211_probe_resp(ieee, dest);
1122 if (buf)
1123 softmac_mgmt_xmit(buf, ieee);
1124}
1125
1126
1127inline struct sk_buff *ieee80211_association_req(struct ieee80211_network *beacon,struct ieee80211_device *ieee)
1128{
1129 struct sk_buff *skb;
1130 //unsigned long flags;
1131
1132 struct ieee80211_assoc_request_frame *hdr;
1133 u8 *tag;//,*rsn_ie;
1134 //short info_addr = 0;
1135 //int i;
1136 //u16 suite_count = 0;
1137 //u8 suit_select = 0;
1138 //unsigned int wpa_len = beacon->wpa_ie_len;
1139 //for HT
1140 u8* ht_cap_buf = NULL;
1141 u8 ht_cap_len=0;
1142 u8* realtek_ie_buf=NULL;
1143 u8 realtek_ie_len=0;
1144 int wpa_ie_len= ieee->wpa_ie_len;
1145 unsigned int ckip_ie_len=0;
1146 unsigned int ccxrm_ie_len=0;
1147 unsigned int cxvernum_ie_len=0;
1148 struct ieee80211_crypt_data* crypt;
1149 int encrypt;
1150
1151 unsigned int rate_len = ieee80211_MFIE_rate_len(ieee);
1152 unsigned int wmm_info_len = beacon->qos_data.supported?9:0;
1153#ifdef THOMAS_TURBO
1154 unsigned int turbo_info_len = beacon->Turbo_Enable?9:0;
1155#endif
1156
1157 int len = 0;
1158
1159 crypt = ieee->crypt[ieee->tx_keyidx];
1160 encrypt = ieee->host_encrypt && crypt && crypt->ops && ((0 == strcmp(crypt->ops->name,"WEP") || wpa_ie_len));
1161
1162 //Include High Throuput capability && Realtek proprietary
1163 if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT)
1164 {
1165 ht_cap_buf = (u8*)&(ieee->pHTInfo->SelfHTCap);
1166 ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap);
1167 HTConstructCapabilityElement(ieee, ht_cap_buf, &ht_cap_len, encrypt);
1168 if(ieee->pHTInfo->bCurrentRT2RTAggregation)
1169 {
1170 realtek_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer;
1171 realtek_ie_len = sizeof( ieee->pHTInfo->szRT2RTAggBuffer);
1172 HTConstructRT2RTAggElement(ieee, realtek_ie_buf, &realtek_ie_len);
1173
1174 }
1175 }
1176 if(ieee->qos_support){
1177 wmm_info_len = beacon->qos_data.supported?9:0;
1178 }
1179
1180
1181 if(beacon->bCkipSupported)
1182 {
1183 ckip_ie_len = 30+2;
1184 }
1185 if(beacon->bCcxRmEnable)
1186 {
1187 ccxrm_ie_len = 6+2;
1188 }
1189 if( beacon->BssCcxVerNumber >= 2 )
1190 {
1191 cxvernum_ie_len = 5+2;
1192 }
1193#ifdef THOMAS_TURBO
1194 len = sizeof(struct ieee80211_assoc_request_frame)+ 2
1195 + beacon->ssid_len//essid tagged val
1196 + rate_len//rates tagged val
1197 + wpa_ie_len
1198 + wmm_info_len
1199 + turbo_info_len
1200 + ht_cap_len
1201 + realtek_ie_len
1202 + ckip_ie_len
1203 + ccxrm_ie_len
1204 + cxvernum_ie_len
1205 + ieee->tx_headroom;
1206#else
1207 len = sizeof(struct ieee80211_assoc_request_frame)+ 2
1208 + beacon->ssid_len//essid tagged val
1209 + rate_len//rates tagged val
1210 + wpa_ie_len
1211 + wmm_info_len
1212 + ht_cap_len
1213 + realtek_ie_len
1214 + ckip_ie_len
1215 + ccxrm_ie_len
1216 + cxvernum_ie_len
1217 + ieee->tx_headroom;
1218#endif
1219
1220 skb = dev_alloc_skb(len);
1221
1222 if (!skb)
1223 return NULL;
1224
1225 skb_reserve(skb, ieee->tx_headroom);
1226
1227 hdr = (struct ieee80211_assoc_request_frame *)
1228 skb_put(skb, sizeof(struct ieee80211_assoc_request_frame)+2);
1229
1230
1231 hdr->header.frame_ctl = IEEE80211_STYPE_ASSOC_REQ;
1232 hdr->header.duration_id= 37; //FIXME
1233 memcpy(hdr->header.addr1, beacon->bssid, ETH_ALEN);
1234 memcpy(hdr->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
1235 memcpy(hdr->header.addr3, beacon->bssid, ETH_ALEN);
1236
1237 memcpy(ieee->ap_mac_addr, beacon->bssid, ETH_ALEN);//for HW security, John
1238
1239 hdr->capability = cpu_to_le16(WLAN_CAPABILITY_BSS);
1240 if (beacon->capability & WLAN_CAPABILITY_PRIVACY )
1241 hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
1242
1243 if (beacon->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
1244 hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE); //add short_preamble here
1245
1246 if(ieee->short_slot)
1247 hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT);
1248 if (wmm_info_len) //QOS
1249 hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_QOS);
1250
1251 hdr->listen_interval = 0xa; //FIXME
1252
1253 hdr->info_element[0].id = MFIE_TYPE_SSID;
1254
1255 hdr->info_element[0].len = beacon->ssid_len;
1256 tag = skb_put(skb, beacon->ssid_len);
1257 memcpy(tag, beacon->ssid, beacon->ssid_len);
1258
1259 tag = skb_put(skb, rate_len);
1260
1261 ieee80211_MFIE_Brate(ieee, &tag);
1262 ieee80211_MFIE_Grate(ieee, &tag);
1263 // For CCX 1 S13, CKIP. Added by Annie, 2006-08-14.
1264 if( beacon->bCkipSupported )
1265 {
1266 static u8 AironetIeOui[] = {0x00, 0x01, 0x66}; // "4500-client"
1267 u8 CcxAironetBuf[30];
1268 OCTET_STRING osCcxAironetIE;
1269
1270 memset(CcxAironetBuf, 0,30);
1271 osCcxAironetIE.Octet = CcxAironetBuf;
1272 osCcxAironetIE.Length = sizeof(CcxAironetBuf);
1273 //
1274 // Ref. CCX test plan v3.61, 3.2.3.1 step 13.
1275 // We want to make the device type as "4500-client". 060926, by CCW.
1276 //
1277 memcpy(osCcxAironetIE.Octet, AironetIeOui, sizeof(AironetIeOui));
1278
1279 // CCX1 spec V1.13, A01.1 CKIP Negotiation (page23):
1280 // "The CKIP negotiation is started with the associate request from the client to the access point,
1281 // containing an Aironet element with both the MIC and KP bits set."
1282 osCcxAironetIE.Octet[IE_CISCO_FLAG_POSITION] |= (SUPPORT_CKIP_PK|SUPPORT_CKIP_MIC) ;
1283 tag = skb_put(skb, ckip_ie_len);
1284 *tag++ = MFIE_TYPE_AIRONET;
1285 *tag++ = osCcxAironetIE.Length;
1286 memcpy(tag,osCcxAironetIE.Octet,osCcxAironetIE.Length);
1287 tag += osCcxAironetIE.Length;
1288 }
1289
1290 if(beacon->bCcxRmEnable)
1291 {
1292 static u8 CcxRmCapBuf[] = {0x00, 0x40, 0x96, 0x01, 0x01, 0x00};
1293 OCTET_STRING osCcxRmCap;
1294
1295 osCcxRmCap.Octet = CcxRmCapBuf;
1296 osCcxRmCap.Length = sizeof(CcxRmCapBuf);
1297 tag = skb_put(skb,ccxrm_ie_len);
1298 *tag++ = MFIE_TYPE_GENERIC;
1299 *tag++ = osCcxRmCap.Length;
1300 memcpy(tag,osCcxRmCap.Octet,osCcxRmCap.Length);
1301 tag += osCcxRmCap.Length;
1302 }
1303
1304 if( beacon->BssCcxVerNumber >= 2 )
1305 {
1306 u8 CcxVerNumBuf[] = {0x00, 0x40, 0x96, 0x03, 0x00};
1307 OCTET_STRING osCcxVerNum;
1308 CcxVerNumBuf[4] = beacon->BssCcxVerNumber;
1309 osCcxVerNum.Octet = CcxVerNumBuf;
1310 osCcxVerNum.Length = sizeof(CcxVerNumBuf);
1311 tag = skb_put(skb,cxvernum_ie_len);
1312 *tag++ = MFIE_TYPE_GENERIC;
1313 *tag++ = osCcxVerNum.Length;
1314 memcpy(tag,osCcxVerNum.Octet,osCcxVerNum.Length);
1315 tag += osCcxVerNum.Length;
1316 }
1317 //HT cap element
1318 if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){
1319 if(ieee->pHTInfo->ePeerHTSpecVer != HT_SPEC_VER_EWC)
1320 {
1321 tag = skb_put(skb, ht_cap_len);
1322 *tag++ = MFIE_TYPE_HT_CAP;
1323 *tag++ = ht_cap_len - 2;
1324 memcpy(tag, ht_cap_buf,ht_cap_len -2);
1325 tag += ht_cap_len -2;
1326 }
1327 }
1328
1329
1330 //choose what wpa_supplicant gives to associate.
1331 tag = skb_put(skb, wpa_ie_len);
1332 if (wpa_ie_len){
1333 memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len);
1334 }
1335
1336 tag = skb_put(skb,wmm_info_len);
1337 if(wmm_info_len) {
1338 ieee80211_WMM_Info(ieee, &tag);
1339 }
1340#ifdef THOMAS_TURBO
1341 tag = skb_put(skb,turbo_info_len);
1342 if(turbo_info_len) {
1343 ieee80211_TURBO_Info(ieee, &tag);
1344 }
1345#endif
1346
1347 if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){
1348 if(ieee->pHTInfo->ePeerHTSpecVer == HT_SPEC_VER_EWC)
1349 {
1350 tag = skb_put(skb, ht_cap_len);
1351 *tag++ = MFIE_TYPE_GENERIC;
1352 *tag++ = ht_cap_len - 2;
1353 memcpy(tag, ht_cap_buf,ht_cap_len - 2);
1354 tag += ht_cap_len -2;
1355 }
1356
1357 if(ieee->pHTInfo->bCurrentRT2RTAggregation){
1358 tag = skb_put(skb, realtek_ie_len);
1359 *tag++ = MFIE_TYPE_GENERIC;
1360 *tag++ = realtek_ie_len - 2;
1361 memcpy(tag, realtek_ie_buf,realtek_ie_len -2 );
1362 }
1363 }
1364// printk("<=====%s(), %p, %p\n", __FUNCTION__, ieee->dev, ieee->dev->dev_addr);
1365// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
1366 return skb;
1367}
1368
1369void ieee80211_associate_abort(struct ieee80211_device *ieee)
1370{
1371
1372 unsigned long flags;
1373 spin_lock_irqsave(&ieee->lock, flags);
1374
1375 ieee->associate_seq++;
1376
1377 /* don't scan, and avoid to have the RX path possibily
1378 * try again to associate. Even do not react to AUTH or
1379 * ASSOC response. Just wait for the retry wq to be scheduled.
1380 * Here we will check if there are good nets to associate
1381 * with, so we retry or just get back to NO_LINK and scanning
1382 */
1383 if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING){
1384 IEEE80211_DEBUG_MGMT("Authentication failed\n");
1385 ieee->softmac_stats.no_auth_rs++;
1386 }else{
1387 IEEE80211_DEBUG_MGMT("Association failed\n");
1388 ieee->softmac_stats.no_ass_rs++;
1389 }
1390
1391 ieee->state = IEEE80211_ASSOCIATING_RETRY;
1392
1393#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1394 queue_delayed_work(ieee->wq, &ieee->associate_retry_wq, \
1395 IEEE80211_SOFTMAC_ASSOC_RETRY_TIME);
1396#else
1397 schedule_task(&ieee->associate_retry_wq);
1398#endif
1399
1400 spin_unlock_irqrestore(&ieee->lock, flags);
1401}
1402
1403void ieee80211_associate_abort_cb(unsigned long dev)
1404{
1405 ieee80211_associate_abort((struct ieee80211_device *) dev);
1406}
1407
1408
1409void ieee80211_associate_step1(struct ieee80211_device *ieee)
1410{
1411 struct ieee80211_network *beacon = &ieee->current_network;
1412 struct sk_buff *skb;
1413
1414 IEEE80211_DEBUG_MGMT("Stopping scan\n");
1415
1416 ieee->softmac_stats.tx_auth_rq++;
1417 skb=ieee80211_authentication_req(beacon, ieee, 0);
1418
1419 if (!skb)
1420 ieee80211_associate_abort(ieee);
1421 else{
1422 ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATING ;
1423 IEEE80211_DEBUG_MGMT("Sending authentication request\n");
1424 //printk(KERN_WARNING "Sending authentication request\n");
1425 softmac_mgmt_xmit(skb, ieee);
1426 //BUGON when you try to add_timer twice, using mod_timer may be better, john0709
1427 if(!timer_pending(&ieee->associate_timer)){
1428 ieee->associate_timer.expires = jiffies + (HZ / 2);
1429 add_timer(&ieee->associate_timer);
1430 }
1431 //dev_kfree_skb_any(skb);//edit by thomas
1432 }
1433}
1434
1435void ieee80211_auth_challenge(struct ieee80211_device *ieee, u8 *challenge, int chlen)
1436{
1437 u8 *c;
1438 struct sk_buff *skb;
1439 struct ieee80211_network *beacon = &ieee->current_network;
1440// int hlen = sizeof(struct ieee80211_authentication);
1441
1442 ieee->associate_seq++;
1443 ieee->softmac_stats.tx_auth_rq++;
1444
1445 skb = ieee80211_authentication_req(beacon, ieee, chlen+2);
1446 if (!skb)
1447 ieee80211_associate_abort(ieee);
1448 else{
1449 c = skb_put(skb, chlen+2);
1450 *(c++) = MFIE_TYPE_CHALLENGE;
1451 *(c++) = chlen;
1452 memcpy(c, challenge, chlen);
1453
1454 IEEE80211_DEBUG_MGMT("Sending authentication challenge response\n");
1455
1456 ieee80211_encrypt_fragment(ieee, skb, sizeof(struct ieee80211_hdr_3addr ));
1457
1458 softmac_mgmt_xmit(skb, ieee);
1459 mod_timer(&ieee->associate_timer, jiffies + (HZ/2));
1460#if 0
1461 ieee->associate_timer.expires = jiffies + (HZ / 2);
1462 add_timer(&ieee->associate_timer);
1463#endif
1464 //dev_kfree_skb_any(skb);//edit by thomas
1465 }
1466 kfree(challenge);
1467}
1468
1469void ieee80211_associate_step2(struct ieee80211_device *ieee)
1470{
1471 struct sk_buff* skb;
1472 struct ieee80211_network *beacon = &ieee->current_network;
1473
1474 del_timer_sync(&ieee->associate_timer);
1475
1476 IEEE80211_DEBUG_MGMT("Sending association request\n");
1477
1478 ieee->softmac_stats.tx_ass_rq++;
1479 skb=ieee80211_association_req(beacon, ieee);
1480 if (!skb)
1481 ieee80211_associate_abort(ieee);
1482 else{
1483 softmac_mgmt_xmit(skb, ieee);
1484 mod_timer(&ieee->associate_timer, jiffies + (HZ/2));
1485#if 0
1486 ieee->associate_timer.expires = jiffies + (HZ / 2);
1487 add_timer(&ieee->associate_timer);
1488#endif
1489 //dev_kfree_skb_any(skb);//edit by thomas
1490 }
1491}
1492#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1493void ieee80211_associate_complete_wq(struct work_struct *work)
1494{
1495 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_complete_wq);
1496#else
1497void ieee80211_associate_complete_wq(struct ieee80211_device *ieee)
1498{
1499#endif
1500 printk(KERN_INFO "Associated successfully\n");
1501 ieee->is_roaming = false;
1502 if(ieee80211_is_54g(ieee->current_network) &&
1503 (ieee->modulation & IEEE80211_OFDM_MODULATION)){
1504
1505 ieee->rate = 108;
1506 printk(KERN_INFO"Using G rates:%d\n", ieee->rate);
1507 }else{
1508 ieee->rate = 22;
1509 printk(KERN_INFO"Using B rates:%d\n", ieee->rate);
1510 }
1511 if (ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT)
1512 {
1513 printk("Successfully associated, ht enabled\n");
1514 HTOnAssocRsp(ieee);
1515 }
1516 else
1517 {
1518 printk("Successfully associated, ht not enabled(%d, %d)\n", ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bEnableHT);
1519 memset(ieee->dot11HTOperationalRateSet, 0, 16);
1520 //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
1521 }
1522 ieee->LinkDetectInfo.SlotNum = 2 * (1 + ieee->current_network.beacon_interval/500);
1523 // To prevent the immediately calling watch_dog after association.
1524 if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 )
1525 {
1526 ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1;
1527 ieee->LinkDetectInfo.NumRecvDataInPeriod= 1;
1528 }
1529 ieee->link_change(ieee->dev);
1530 if(ieee->is_silent_reset == 0){
1531 printk("============>normal associate\n");
1532 notify_wx_assoc_event(ieee);
1533 }
1534 else if(ieee->is_silent_reset == 1)
1535 {
1536 printk("==================>silent reset associate\n");
1537 ieee->is_silent_reset = 0;
1538 }
1539
1540 if (ieee->data_hard_resume)
1541 ieee->data_hard_resume(ieee->dev);
1542 netif_carrier_on(ieee->dev);
1543}
1544
1545void ieee80211_associate_complete(struct ieee80211_device *ieee)
1546{
1547// int i;
1548// struct net_device* dev = ieee->dev;
1549 del_timer_sync(&ieee->associate_timer);
1550
1551#if 0
1552 for(i = 0; i < 6; i++) {
1553 ieee->seq_ctrl[i] = 0;
1554 }
1555#endif
1556 ieee->state = IEEE80211_LINKED;
1557#if 0
1558 if (ieee->pHTInfo->bCurrentHTSupport)
1559 {
1560 printk("Successfully associated, ht enabled\n");
1561 queue_work(ieee->wq, &ieee->ht_onAssRsp);
1562 }
1563 else
1564 {
1565 printk("Successfully associated, ht not enabled\n");
1566 memset(ieee->dot11HTOperationalRateSet, 0, 16);
1567 HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
1568 }
1569#endif
1570 //ieee->UpdateHalRATRTableHandler(dev, ieee->dot11HTOperationalRateSet);
1571#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1572 queue_work(ieee->wq, &ieee->associate_complete_wq);
1573#else
1574 schedule_task(&ieee->associate_complete_wq);
1575#endif
1576}
1577
1578#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1579void ieee80211_associate_procedure_wq(struct work_struct *work)
1580{
1581 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_procedure_wq);
1582#else
1583void ieee80211_associate_procedure_wq(struct ieee80211_device *ieee)
1584{
1585#endif
1586 ieee->sync_scan_hurryup = 1;
1587 down(&ieee->wx_sem);
1588
1589 if (ieee->data_hard_stop)
1590 ieee->data_hard_stop(ieee->dev);
1591
1592 ieee80211_stop_scan(ieee);
1593 printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel);
1594 //ieee->set_chan(ieee->dev, ieee->current_network.channel);
1595 HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
1596
1597 ieee->associate_seq = 1;
1598 ieee80211_associate_step1(ieee);
1599
1600 up(&ieee->wx_sem);
1601}
1602
1603inline void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net)
1604{
1605 u8 tmp_ssid[IW_ESSID_MAX_SIZE+1];
1606 int tmp_ssid_len = 0;
1607
1608 short apset,ssidset,ssidbroad,apmatch,ssidmatch;
1609
1610 /* we are interested in new new only if we are not associated
1611 * and we are not associating / authenticating
1612 */
1613 if (ieee->state != IEEE80211_NOLINK)
1614 return;
1615
1616 if ((ieee->iw_mode == IW_MODE_INFRA) && !(net->capability & WLAN_CAPABILITY_BSS))
1617 return;
1618
1619 if ((ieee->iw_mode == IW_MODE_ADHOC) && !(net->capability & WLAN_CAPABILITY_IBSS))
1620 return;
1621
1622
1623 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC){
1624 /* if the user specified the AP MAC, we need also the essid
1625 * This could be obtained by beacons or, if the network does not
1626 * broadcast it, it can be put manually.
1627 */
1628 apset = ieee->wap_set;//(memcmp(ieee->current_network.bssid, zero,ETH_ALEN)!=0 );
1629 ssidset = ieee->ssid_set;//ieee->current_network.ssid[0] != '\0';
1630 ssidbroad = !(net->ssid_len == 0 || net->ssid[0]== '\0');
1631 apmatch = (memcmp(ieee->current_network.bssid, net->bssid, ETH_ALEN)==0);
1632 ssidmatch = (ieee->current_network.ssid_len == net->ssid_len)&&\
1633 (!strncmp(ieee->current_network.ssid, net->ssid, net->ssid_len));
1634
1635
1636 if ( /* if the user set the AP check if match.
1637 * if the network does not broadcast essid we check the user supplyed ANY essid
1638 * if the network does broadcast and the user does not set essid it is OK
1639 * if the network does broadcast and the user did set essid chech if essid match
1640 */
1641 ( apset && apmatch &&
1642 ((ssidset && ssidbroad && ssidmatch) || (ssidbroad && !ssidset) || (!ssidbroad && ssidset)) ) ||
1643 /* if the ap is not set, check that the user set the bssid
1644 * and the network does bradcast and that those two bssid matches
1645 */
1646 (!apset && ssidset && ssidbroad && ssidmatch)
1647 ){
1648 /* if the essid is hidden replace it with the
1649 * essid provided by the user.
1650 */
1651 if (!ssidbroad){
1652 strncpy(tmp_ssid, ieee->current_network.ssid, IW_ESSID_MAX_SIZE);
1653 tmp_ssid_len = ieee->current_network.ssid_len;
1654 }
1655 memcpy(&ieee->current_network, net, sizeof(struct ieee80211_network));
1656
1657 if (!ssidbroad){
1658 strncpy(ieee->current_network.ssid, tmp_ssid, IW_ESSID_MAX_SIZE);
1659 ieee->current_network.ssid_len = tmp_ssid_len;
1660 }
1661 printk(KERN_INFO"Linking with %s,channel:%d, qos:%d, myHT:%d, networkHT:%d, mode:%x\n",ieee->current_network.ssid,ieee->current_network.channel, ieee->current_network.qos_data.supported, ieee->pHTInfo->bEnableHT, ieee->current_network.bssht.bdSupportHT, ieee->current_network.mode);
1662
1663 //ieee->pHTInfo->IOTAction = 0;
1664 HTResetIOTSetting(ieee->pHTInfo);
1665 if (ieee->iw_mode == IW_MODE_INFRA){
1666 /* Join the network for the first time */
1667 ieee->AsocRetryCount = 0;
1668 //for HT by amy 080514
1669 if((ieee->current_network.qos_data.supported == 1) &&
1670 // (ieee->pHTInfo->bEnableHT && ieee->current_network.bssht.bdSupportHT))
1671 ieee->current_network.bssht.bdSupportHT)
1672/*WB, 2008.09.09:bCurrentHTSupport and bEnableHT two flags are going to put together to check whether we are in HT now, so needn't to check bEnableHT flags here. That's is to say we will set to HT support whenever joined AP has the ability to support HT. And whether we are in HT or not, please check bCurrentHTSupport&&bEnableHT now please.*/
1673 {
1674 // ieee->pHTInfo->bCurrentHTSupport = true;
1675 HTResetSelfAndSavePeerSetting(ieee, &(ieee->current_network));
1676 }
1677 else
1678 {
1679 ieee->pHTInfo->bCurrentHTSupport = false;
1680 }
1681
1682 ieee->state = IEEE80211_ASSOCIATING;
1683 if(ieee->LedControlHandler != NULL)
1684 ieee->LedControlHandler(ieee->dev, LED_CTL_START_TO_LINK);
1685#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1686 queue_work(ieee->wq, &ieee->associate_procedure_wq);
1687#else
1688 schedule_task(&ieee->associate_procedure_wq);
1689#endif
1690 }else{
1691 if(ieee80211_is_54g(ieee->current_network) &&
1692 (ieee->modulation & IEEE80211_OFDM_MODULATION)){
1693 ieee->rate = 108;
1694 ieee->SetWirelessMode(ieee->dev, IEEE_G);
1695 printk(KERN_INFO"Using G rates\n");
1696 }else{
1697 ieee->rate = 22;
1698 ieee->SetWirelessMode(ieee->dev, IEEE_B);
1699 printk(KERN_INFO"Using B rates\n");
1700 }
1701 memset(ieee->dot11HTOperationalRateSet, 0, 16);
1702 //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
1703 ieee->state = IEEE80211_LINKED;
1704 }
1705
1706 }
1707 }
1708
1709}
1710
1711void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee)
1712{
1713 unsigned long flags;
1714 struct ieee80211_network *target;
1715
1716 spin_lock_irqsave(&ieee->lock, flags);
1717
1718 list_for_each_entry(target, &ieee->network_list, list) {
1719
1720 /* if the state become different that NOLINK means
1721 * we had found what we are searching for
1722 */
1723
1724 if (ieee->state != IEEE80211_NOLINK)
1725 break;
1726
1727 if (ieee->scan_age == 0 || time_after(target->last_scanned + ieee->scan_age, jiffies))
1728 ieee80211_softmac_new_net(ieee, target);
1729 }
1730
1731 spin_unlock_irqrestore(&ieee->lock, flags);
1732
1733}
1734
1735
1736static inline u16 auth_parse(struct sk_buff *skb, u8** challenge, int *chlen)
1737{
1738 struct ieee80211_authentication *a;
1739 u8 *t;
1740 if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){
1741 IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n",skb->len);
1742 return 0xcafe;
1743 }
1744 *challenge = NULL;
1745 a = (struct ieee80211_authentication*) skb->data;
1746 if(skb->len > (sizeof(struct ieee80211_authentication) +3)){
1747 t = skb->data + sizeof(struct ieee80211_authentication);
1748
1749 if(*(t++) == MFIE_TYPE_CHALLENGE){
1750 *chlen = *(t++);
1751 *challenge = (u8*)kmalloc(*chlen, GFP_ATOMIC);
1752 memcpy(*challenge, t, *chlen);
1753 }
1754 }
1755
1756 return cpu_to_le16(a->status);
1757
1758}
1759
1760
1761int auth_rq_parse(struct sk_buff *skb,u8* dest)
1762{
1763 struct ieee80211_authentication *a;
1764
1765 if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){
1766 IEEE80211_DEBUG_MGMT("invalid len in auth request: %d\n",skb->len);
1767 return -1;
1768 }
1769 a = (struct ieee80211_authentication*) skb->data;
1770
1771 memcpy(dest,a->header.addr2, ETH_ALEN);
1772
1773 if (le16_to_cpu(a->algorithm) != WLAN_AUTH_OPEN)
1774 return WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG;
1775
1776 return WLAN_STATUS_SUCCESS;
1777}
1778
1779static short probe_rq_parse(struct ieee80211_device *ieee, struct sk_buff *skb, u8 *src)
1780{
1781 u8 *tag;
1782 u8 *skbend;
1783 u8 *ssid=NULL;
1784 u8 ssidlen = 0;
1785
1786 struct ieee80211_hdr_3addr *header =
1787 (struct ieee80211_hdr_3addr *) skb->data;
1788
1789 if (skb->len < sizeof (struct ieee80211_hdr_3addr ))
1790 return -1; /* corrupted */
1791
1792 memcpy(src,header->addr2, ETH_ALEN);
1793
1794 skbend = (u8*)skb->data + skb->len;
1795
1796 tag = skb->data + sizeof (struct ieee80211_hdr_3addr );
1797
1798 while (tag+1 < skbend){
1799 if (*tag == 0){
1800 ssid = tag+2;
1801 ssidlen = *(tag+1);
1802 break;
1803 }
1804 tag++; /* point to the len field */
1805 tag = tag + *(tag); /* point to the last data byte of the tag */
1806 tag++; /* point to the next tag */
1807 }
1808
1809 //IEEE80211DMESG("Card MAC address is "MACSTR, MAC2STR(src));
1810 if (ssidlen == 0) return 1;
1811
1812 if (!ssid) return 1; /* ssid not found in tagged param */
1813 return (!strncmp(ssid, ieee->current_network.ssid, ssidlen));
1814
1815}
1816
1817int assoc_rq_parse(struct sk_buff *skb,u8* dest)
1818{
1819 struct ieee80211_assoc_request_frame *a;
1820
1821 if (skb->len < (sizeof(struct ieee80211_assoc_request_frame) -
1822 sizeof(struct ieee80211_info_element))) {
1823
1824 IEEE80211_DEBUG_MGMT("invalid len in auth request:%d \n", skb->len);
1825 return -1;
1826 }
1827
1828 a = (struct ieee80211_assoc_request_frame*) skb->data;
1829
1830 memcpy(dest,a->header.addr2,ETH_ALEN);
1831
1832 return 0;
1833}
1834
1835static inline u16 assoc_parse(struct ieee80211_device *ieee, struct sk_buff *skb, int *aid)
1836{
1837 struct ieee80211_assoc_response_frame *response_head;
1838 u16 status_code;
1839
1840 if (skb->len < sizeof(struct ieee80211_assoc_response_frame)){
1841 IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n", skb->len);
1842 return 0xcafe;
1843 }
1844
1845 response_head = (struct ieee80211_assoc_response_frame*) skb->data;
1846 *aid = le16_to_cpu(response_head->aid) & 0x3fff;
1847
1848 status_code = le16_to_cpu(response_head->status);
1849 if((status_code==WLAN_STATUS_ASSOC_DENIED_RATES || \
1850 status_code==WLAN_STATUS_CAPS_UNSUPPORTED)&&
1851 ((ieee->mode == IEEE_G) &&
1852 (ieee->current_network.mode == IEEE_N_24G) &&
1853 (ieee->AsocRetryCount++ < (RT_ASOC_RETRY_LIMIT-1)))) {
1854 ieee->pHTInfo->IOTAction |= HT_IOT_ACT_PURE_N_MODE;
1855 }else {
1856 ieee->AsocRetryCount = 0;
1857 }
1858
1859 return le16_to_cpu(response_head->status);
1860}
1861
1862static inline void
1863ieee80211_rx_probe_rq(struct ieee80211_device *ieee, struct sk_buff *skb)
1864{
1865 u8 dest[ETH_ALEN];
1866
1867 //IEEE80211DMESG("Rx probe");
1868 ieee->softmac_stats.rx_probe_rq++;
1869 //DMESG("Dest is "MACSTR, MAC2STR(dest));
1870 if (probe_rq_parse(ieee, skb, dest)){
1871 //IEEE80211DMESG("Was for me!");
1872 ieee->softmac_stats.tx_probe_rs++;
1873 ieee80211_resp_to_probe(ieee, dest);
1874 }
1875}
1876
1877static inline void
1878ieee80211_rx_auth_rq(struct ieee80211_device *ieee, struct sk_buff *skb)
1879{
1880 u8 dest[ETH_ALEN];
1881 int status;
1882 //IEEE80211DMESG("Rx probe");
1883 ieee->softmac_stats.rx_auth_rq++;
1884
1885 if ((status = auth_rq_parse(skb, dest))!= -1){
1886 ieee80211_resp_to_auth(ieee, status, dest);
1887 }
1888 //DMESG("Dest is "MACSTR, MAC2STR(dest));
1889
1890}
1891
1892static inline void
1893ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb)
1894{
1895
1896 u8 dest[ETH_ALEN];
1897 //unsigned long flags;
1898
1899 ieee->softmac_stats.rx_ass_rq++;
1900 if (assoc_rq_parse(skb,dest) != -1){
1901 ieee80211_resp_to_assoc_rq(ieee, dest);
1902 }
1903
1904 printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest));
1905 //FIXME
1906 #if 0
1907 spin_lock_irqsave(&ieee->lock,flags);
1908 add_associate(ieee,dest);
1909 spin_unlock_irqrestore(&ieee->lock,flags);
1910 #endif
1911}
1912
1913
1914
1915void ieee80211_sta_ps_send_null_frame(struct ieee80211_device *ieee, short pwr)
1916{
1917
1918 struct sk_buff *buf = ieee80211_null_func(ieee, pwr);
1919
1920 if (buf)
1921 softmac_ps_mgmt_xmit(buf, ieee);
1922
1923}
1924
1925
1926short ieee80211_sta_ps_sleep(struct ieee80211_device *ieee, u32 *time_h, u32 *time_l)
1927{
1928 int timeout = ieee->ps_timeout;
1929 u8 dtim;
1930 /*if(ieee->ps == IEEE80211_PS_DISABLED ||
1931 ieee->iw_mode != IW_MODE_INFRA ||
1932 ieee->state != IEEE80211_LINKED)
1933
1934 return 0;
1935 */
1936 dtim = ieee->current_network.dtim_data;
1937 //printk("DTIM\n");
1938 if(!(dtim & IEEE80211_DTIM_VALID))
1939 return 0;
1940 timeout = ieee->current_network.beacon_interval; //should we use ps_timeout value or beacon_interval
1941 //printk("VALID\n");
1942 ieee->current_network.dtim_data = IEEE80211_DTIM_INVALID;
1943
1944 if(dtim & ((IEEE80211_DTIM_UCAST | IEEE80211_DTIM_MBCAST)& ieee->ps))
1945 return 2;
1946
1947 if(!time_after(jiffies, ieee->dev->trans_start + MSECS(timeout)))
1948 return 0;
1949
1950 if(!time_after(jiffies, ieee->last_rx_ps_time + MSECS(timeout)))
1951 return 0;
1952
1953 if((ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE ) &&
1954 (ieee->mgmt_queue_tail != ieee->mgmt_queue_head))
1955 return 0;
1956
1957 if(time_l){
1958 *time_l = ieee->current_network.last_dtim_sta_time[0]
1959 + (ieee->current_network.beacon_interval);
1960 // * ieee->current_network.dtim_period) * 1000;
1961 }
1962
1963 if(time_h){
1964 *time_h = ieee->current_network.last_dtim_sta_time[1];
1965 if(time_l && *time_l < ieee->current_network.last_dtim_sta_time[0])
1966 *time_h += 1;
1967 }
1968
1969 return 1;
1970
1971
1972}
1973
1974inline void ieee80211_sta_ps(struct ieee80211_device *ieee)
1975{
1976
1977 u32 th,tl;
1978 short sleep;
1979
1980 unsigned long flags,flags2;
1981
1982 spin_lock_irqsave(&ieee->lock, flags);
1983
1984 if((ieee->ps == IEEE80211_PS_DISABLED ||
1985 ieee->iw_mode != IW_MODE_INFRA ||
1986 ieee->state != IEEE80211_LINKED)){
1987
1988 // #warning CHECK_LOCK_HERE
1989 spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2);
1990
1991 ieee80211_sta_wakeup(ieee, 1);
1992
1993 spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2);
1994 }
1995
1996 sleep = ieee80211_sta_ps_sleep(ieee,&th, &tl);
1997 /* 2 wake, 1 sleep, 0 do nothing */
1998 if(sleep == 0)
1999 goto out;
2000
2001 if(sleep == 1){
2002
2003 if(ieee->sta_sleep == 1)
2004 ieee->enter_sleep_state(ieee->dev,th,tl);
2005
2006 else if(ieee->sta_sleep == 0){
2007 // printk("send null 1\n");
2008 spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2);
2009
2010 if(ieee->ps_is_queue_empty(ieee->dev)){
2011
2012
2013 ieee->sta_sleep = 2;
2014
2015 ieee->ack_tx_to_ieee = 1;
2016
2017 ieee80211_sta_ps_send_null_frame(ieee,1);
2018
2019 ieee->ps_th = th;
2020 ieee->ps_tl = tl;
2021 }
2022 spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2);
2023
2024 }
2025
2026
2027 }else if(sleep == 2){
2028//#warning CHECK_LOCK_HERE
2029 spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2);
2030
2031 ieee80211_sta_wakeup(ieee,1);
2032
2033 spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2);
2034 }
2035
2036out:
2037 spin_unlock_irqrestore(&ieee->lock, flags);
2038
2039}
2040
2041void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl)
2042{
2043 if(ieee->sta_sleep == 0){
2044 if(nl){
2045 printk("Warning: driver is probably failing to report TX ps error\n");
2046 ieee->ack_tx_to_ieee = 1;
2047 ieee80211_sta_ps_send_null_frame(ieee, 0);
2048 }
2049 return;
2050
2051 }
2052
2053 if(ieee->sta_sleep == 1)
2054 ieee->sta_wake_up(ieee->dev);
2055
2056 ieee->sta_sleep = 0;
2057
2058 if(nl){
2059 ieee->ack_tx_to_ieee = 1;
2060 ieee80211_sta_ps_send_null_frame(ieee, 0);
2061 }
2062}
2063
2064void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success)
2065{
2066 unsigned long flags,flags2;
2067
2068 spin_lock_irqsave(&ieee->lock, flags);
2069
2070 if(ieee->sta_sleep == 2){
2071 /* Null frame with PS bit set */
2072 if(success){
2073 ieee->sta_sleep = 1;
2074 ieee->enter_sleep_state(ieee->dev,ieee->ps_th,ieee->ps_tl);
2075 }
2076 /* if the card report not success we can't be sure the AP
2077 * has not RXed so we can't assume the AP believe us awake
2078 */
2079 }
2080 /* 21112005 - tx again null without PS bit if lost */
2081 else {
2082
2083 if((ieee->sta_sleep == 0) && !success){
2084 spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2);
2085 ieee80211_sta_ps_send_null_frame(ieee, 0);
2086 spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2);
2087 }
2088 }
2089 spin_unlock_irqrestore(&ieee->lock, flags);
2090}
2091void ieee80211_process_action(struct ieee80211_device* ieee, struct sk_buff* skb)
2092{
2093 struct ieee80211_hdr* header = (struct ieee80211_hdr*)skb->data;
2094 u8* act = ieee80211_get_payload(header);
2095 u8 tmp = 0;
2096// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len);
2097 if (act == NULL)
2098 {
2099 IEEE80211_DEBUG(IEEE80211_DL_ERR, "error to get payload of action frame\n");
2100 return;
2101 }
2102 tmp = *act;
2103 act ++;
2104 switch (tmp)
2105 {
2106 case ACT_CAT_BA:
2107 if (*act == ACT_ADDBAREQ)
2108 ieee80211_rx_ADDBAReq(ieee, skb);
2109 else if (*act == ACT_ADDBARSP)
2110 ieee80211_rx_ADDBARsp(ieee, skb);
2111 else if (*act == ACT_DELBA)
2112 ieee80211_rx_DELBA(ieee, skb);
2113 break;
2114 default:
2115// if (net_ratelimit())
2116// IEEE80211_DEBUG(IEEE80211_DL_BA, "unknown action frame(%d)\n", tmp);
2117 break;
2118 }
2119 return;
2120
2121}
2122inline int
2123ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb,
2124 struct ieee80211_rx_stats *rx_stats, u16 type,
2125 u16 stype)
2126{
2127 struct ieee80211_hdr_3addr *header = (struct ieee80211_hdr_3addr *) skb->data;
2128 u16 errcode;
2129 u8* challenge;
2130 int chlen=0;
2131 int aid;
2132 struct ieee80211_assoc_response_frame *assoc_resp;
2133// struct ieee80211_info_element *info_element;
2134 bool bSupportNmode = true, bHalfSupportNmode = false; //default support N mode, disable halfNmode
2135
2136 if(!ieee->proto_started)
2137 return 0;
2138#if 0
2139 printk("%d, %d, %d, %d\n", ieee->sta_sleep, ieee->ps, ieee->iw_mode, ieee->state);
2140 if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED &&
2141 ieee->iw_mode == IW_MODE_INFRA &&
2142 ieee->state == IEEE80211_LINKED))
2143
2144 tasklet_schedule(&ieee->ps_task);
2145
2146 if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP &&
2147 WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON)
2148 ieee->last_rx_ps_time = jiffies;
2149#endif
2150
2151 switch (WLAN_FC_GET_STYPE(header->frame_ctl)) {
2152
2153 case IEEE80211_STYPE_ASSOC_RESP:
2154 case IEEE80211_STYPE_REASSOC_RESP:
2155
2156 IEEE80211_DEBUG_MGMT("received [RE]ASSOCIATION RESPONSE (%d)\n",
2157 WLAN_FC_GET_STYPE(header->frame_ctl));
2158 if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) &&
2159 ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATED &&
2160 ieee->iw_mode == IW_MODE_INFRA){
2161 struct ieee80211_network network_resp;
2162 struct ieee80211_network *network = &network_resp;
2163
2164 if (0 == (errcode=assoc_parse(ieee,skb, &aid))){
2165 ieee->state=IEEE80211_LINKED;
2166 ieee->assoc_id = aid;
2167 ieee->softmac_stats.rx_ass_ok++;
2168 /* station support qos */
2169 /* Let the register setting defaultly with Legacy station */
2170 if(ieee->qos_support) {
2171 assoc_resp = (struct ieee80211_assoc_response_frame*)skb->data;
2172 memset(network, 0, sizeof(*network));
2173 if (ieee80211_parse_info_param(ieee,assoc_resp->info_element,\
2174 rx_stats->len - sizeof(*assoc_resp),\
2175 network,rx_stats)){
2176 return 1;
2177 }
2178 else
2179 { //filling the PeerHTCap. //maybe not neccesary as we can get its info from current_network.
2180 memcpy(ieee->pHTInfo->PeerHTCapBuf, network->bssht.bdHTCapBuf, network->bssht.bdHTCapLen);
2181 memcpy(ieee->pHTInfo->PeerHTInfoBuf, network->bssht.bdHTInfoBuf, network->bssht.bdHTInfoLen);
2182 }
2183 if (ieee->handle_assoc_response != NULL)
2184 ieee->handle_assoc_response(ieee->dev, (struct ieee80211_assoc_response_frame*)header, network);
2185 }
2186 ieee80211_associate_complete(ieee);
2187 } else {
2188 /* aid could not been allocated */
2189 ieee->softmac_stats.rx_ass_err++;
2190 printk(
2191 "Association response status code 0x%x\n",
2192 errcode);
2193 IEEE80211_DEBUG_MGMT(
2194 "Association response status code 0x%x\n",
2195 errcode);
2196 if(ieee->AsocRetryCount < RT_ASOC_RETRY_LIMIT) {
2197#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2198 queue_work(ieee->wq, &ieee->associate_procedure_wq);
2199#else
2200 schedule_task(&ieee->associate_procedure_wq);
2201#endif
2202 } else {
2203 ieee80211_associate_abort(ieee);
2204 }
2205 }
2206 }
2207 break;
2208
2209 case IEEE80211_STYPE_ASSOC_REQ:
2210 case IEEE80211_STYPE_REASSOC_REQ:
2211
2212 if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) &&
2213 ieee->iw_mode == IW_MODE_MASTER)
2214
2215 ieee80211_rx_assoc_rq(ieee, skb);
2216 break;
2217
2218 case IEEE80211_STYPE_AUTH:
2219
2220 if (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE){
2221 if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING &&
2222 ieee->iw_mode == IW_MODE_INFRA){
2223
2224 IEEE80211_DEBUG_MGMT("Received authentication response");
2225
2226 if (0 == (errcode=auth_parse(skb, &challenge, &chlen))){
2227 if(ieee->open_wep || !challenge){
2228 ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATED;
2229 ieee->softmac_stats.rx_auth_rs_ok++;
2230 if(!(ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE))
2231 {
2232 if (!ieee->GetNmodeSupportBySecCfg(ieee->dev))
2233 {
2234 // WEP or TKIP encryption
2235 if(IsHTHalfNmodeAPs(ieee))
2236 {
2237 bSupportNmode = true;
2238 bHalfSupportNmode = true;
2239 }
2240 else
2241 {
2242 bSupportNmode = false;
2243 bHalfSupportNmode = false;
2244 }
2245 printk("==========>to link with AP using SEC(%d, %d)", bSupportNmode, bHalfSupportNmode);
2246 }
2247 }
2248 /* Dummy wirless mode setting to avoid encryption issue */
2249 if(bSupportNmode) {
2250 //N mode setting
2251 ieee->SetWirelessMode(ieee->dev, \
2252 ieee->current_network.mode);
2253 }else{
2254 //b/g mode setting
2255 /*TODO*/
2256 ieee->SetWirelessMode(ieee->dev, IEEE_G);
2257 }
2258
2259 if (ieee->current_network.mode == IEEE_N_24G && bHalfSupportNmode == true)
2260 {
2261 printk("===============>entern half N mode\n");
2262 ieee->bHalfWirelessN24GMode = true;
2263 }
2264 else
2265 ieee->bHalfWirelessN24GMode = false;
2266
2267 ieee80211_associate_step2(ieee);
2268 }else{
2269 ieee80211_auth_challenge(ieee, challenge, chlen);
2270 }
2271 }else{
2272 ieee->softmac_stats.rx_auth_rs_err++;
2273 IEEE80211_DEBUG_MGMT("Authentication respose status code 0x%x",errcode);
2274
2275 printk("Authentication respose status code 0x%x",errcode);
2276 ieee80211_associate_abort(ieee);
2277 }
2278
2279 }else if (ieee->iw_mode == IW_MODE_MASTER){
2280 ieee80211_rx_auth_rq(ieee, skb);
2281 }
2282 }
2283 break;
2284
2285 case IEEE80211_STYPE_PROBE_REQ:
2286
2287 if ((ieee->softmac_features & IEEE_SOFTMAC_PROBERS) &&
2288 ((ieee->iw_mode == IW_MODE_ADHOC ||
2289 ieee->iw_mode == IW_MODE_MASTER) &&
2290 ieee->state == IEEE80211_LINKED)){
2291 ieee80211_rx_probe_rq(ieee, skb);
2292 }
2293 break;
2294
2295 case IEEE80211_STYPE_DISASSOC:
2296 case IEEE80211_STYPE_DEAUTH:
2297 /* FIXME for now repeat all the association procedure
2298 * both for disassociation and deauthentication
2299 */
2300 if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) &&
2301 ieee->state == IEEE80211_LINKED &&
2302 ieee->iw_mode == IW_MODE_INFRA){
2303 printk("==========>received disassoc/deauth(%x) frame, reason code:%x\n",WLAN_FC_GET_STYPE(header->frame_ctl), ((struct ieee80211_disassoc*)skb->data)->reason);
2304 ieee->state = IEEE80211_ASSOCIATING;
2305 ieee->softmac_stats.reassoc++;
2306 ieee->is_roaming = true;
2307 ieee80211_disassociate(ieee);
2308 // notify_wx_assoc_event(ieee);
2309 //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
2310 RemovePeerTS(ieee, header->addr2);
2311 if(ieee->LedControlHandler != NULL)
2312 ieee->LedControlHandler(ieee->dev, LED_CTL_START_TO_LINK); //added by amy for LED 090318
2313#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2314 queue_work(ieee->wq, &ieee->associate_procedure_wq);
2315#else
2316 schedule_task(&ieee->associate_procedure_wq);
2317#endif
2318 }
2319 break;
2320 case IEEE80211_STYPE_MANAGE_ACT:
2321 ieee80211_process_action(ieee,skb);
2322 break;
2323 default:
2324 return -1;
2325 break;
2326 }
2327
2328 //dev_kfree_skb_any(skb);
2329 return 0;
2330}
2331
2332/* following are for a simplier TX queue management.
2333 * Instead of using netif_[stop/wake]_queue the driver
2334 * will uses these two function (plus a reset one), that
2335 * will internally uses the kernel netif_* and takes
2336 * care of the ieee802.11 fragmentation.
2337 * So the driver receives a fragment per time and might
2338 * call the stop function when it want without take care
2339 * to have enought room to TX an entire packet.
2340 * This might be useful if each fragment need it's own
2341 * descriptor, thus just keep a total free memory > than
2342 * the max fragmentation treshold is not enought.. If the
2343 * ieee802.11 stack passed a TXB struct then you needed
2344 * to keep N free descriptors where
2345 * N = MAX_PACKET_SIZE / MIN_FRAG_TRESHOLD
2346 * In this way you need just one and the 802.11 stack
2347 * will take care of buffering fragments and pass them to
2348 * to the driver later, when it wakes the queue.
2349 */
2350void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee)
2351{
2352
2353 unsigned int queue_index = txb->queue_index;
2354 unsigned long flags;
2355 int i;
2356 cb_desc *tcb_desc = NULL;
2357
2358 spin_lock_irqsave(&ieee->lock,flags);
2359
2360 /* called with 2nd parm 0, no tx mgmt lock required */
2361 ieee80211_sta_wakeup(ieee,0);
2362
2363 /* update the tx status */
2364// ieee->stats.tx_bytes += txb->payload_size;
2365// ieee->stats.tx_packets++;
2366 tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE);
2367 if(tcb_desc->bMulticast) {
2368 ieee->stats.multicast++;
2369 }
2370#if 1
2371 /* if xmit available, just xmit it immediately, else just insert it to the wait queue */
2372 for(i = 0; i < txb->nr_frags; i++) {
2373#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2374 if ((skb_queue_len(&ieee->skb_drv_aggQ[queue_index]) != 0) ||
2375#else
2376 if ((skb_queue_len(&ieee->skb_waitQ[queue_index]) != 0) ||
2377#endif
2378 (!ieee->check_nic_enough_desc(ieee->dev,queue_index))||\
2379 (ieee->queue_stop)) {
2380 /* insert the skb packet to the wait queue */
2381 /* as for the completion function, it does not need
2382 * to check it any more.
2383 * */
2384 //printk("error:no descriptor left@queue_index %d, %d, %d\n", queue_index, skb_queue_len(&ieee->skb_waitQ[queue_index]), ieee->check_nic_enough_desc(ieee->dev,queue_index));
2385 //ieee80211_stop_queue(ieee);
2386#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2387 skb_queue_tail(&ieee->skb_drv_aggQ[queue_index], txb->fragments[i]);
2388#else
2389 skb_queue_tail(&ieee->skb_waitQ[queue_index], txb->fragments[i]);
2390#endif
2391 }else{
2392 ieee->softmac_data_hard_start_xmit(
2393 txb->fragments[i],
2394 ieee->dev,ieee->rate);
2395 //ieee->stats.tx_packets++;
2396 //ieee->stats.tx_bytes += txb->fragments[i]->len;
2397 //ieee->dev->trans_start = jiffies;
2398 }
2399 }
2400#endif
2401 ieee80211_txb_free(txb);
2402
2403//exit:
2404 spin_unlock_irqrestore(&ieee->lock,flags);
2405
2406}
2407
2408/* called with ieee->lock acquired */
2409void ieee80211_resume_tx(struct ieee80211_device *ieee)
2410{
2411 int i;
2412 for(i = ieee->tx_pending.frag; i < ieee->tx_pending.txb->nr_frags; i++) {
2413
2414 if (ieee->queue_stop){
2415 ieee->tx_pending.frag = i;
2416 return;
2417 }else{
2418
2419 ieee->softmac_data_hard_start_xmit(
2420 ieee->tx_pending.txb->fragments[i],
2421 ieee->dev,ieee->rate);
2422 //(i+1)<ieee->tx_pending.txb->nr_frags);
2423 ieee->stats.tx_packets++;
2424 // ieee->dev->trans_start = jiffies;
2425 }
2426 }
2427
2428
2429 ieee80211_txb_free(ieee->tx_pending.txb);
2430 ieee->tx_pending.txb = NULL;
2431}
2432
2433
2434void ieee80211_reset_queue(struct ieee80211_device *ieee)
2435{
2436 unsigned long flags;
2437
2438 spin_lock_irqsave(&ieee->lock,flags);
2439 init_mgmt_queue(ieee);
2440 if (ieee->tx_pending.txb){
2441 ieee80211_txb_free(ieee->tx_pending.txb);
2442 ieee->tx_pending.txb = NULL;
2443 }
2444 ieee->queue_stop = 0;
2445 spin_unlock_irqrestore(&ieee->lock,flags);
2446
2447}
2448
2449void ieee80211_wake_queue(struct ieee80211_device *ieee)
2450{
2451
2452 unsigned long flags;
2453 struct sk_buff *skb;
2454 struct ieee80211_hdr_3addr *header;
2455
2456 spin_lock_irqsave(&ieee->lock,flags);
2457 if (! ieee->queue_stop) goto exit;
2458
2459 ieee->queue_stop = 0;
2460
2461 if(ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE){
2462 while (!ieee->queue_stop && (skb = dequeue_mgmt(ieee))){
2463
2464 header = (struct ieee80211_hdr_3addr *) skb->data;
2465
2466 header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4);
2467
2468 if (ieee->seq_ctrl[0] == 0xFFF)
2469 ieee->seq_ctrl[0] = 0;
2470 else
2471 ieee->seq_ctrl[0]++;
2472
2473 ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate);
2474 //dev_kfree_skb_any(skb);//edit by thomas
2475 }
2476 }
2477 if (!ieee->queue_stop && ieee->tx_pending.txb)
2478 ieee80211_resume_tx(ieee);
2479
2480 if (!ieee->queue_stop && netif_queue_stopped(ieee->dev)){
2481 ieee->softmac_stats.swtxawake++;
2482 netif_wake_queue(ieee->dev);
2483 }
2484
2485exit :
2486 spin_unlock_irqrestore(&ieee->lock,flags);
2487}
2488
2489
2490void ieee80211_stop_queue(struct ieee80211_device *ieee)
2491{
2492 //unsigned long flags;
2493 //spin_lock_irqsave(&ieee->lock,flags);
2494
2495 if (! netif_queue_stopped(ieee->dev)){
2496 netif_stop_queue(ieee->dev);
2497 ieee->softmac_stats.swtxstop++;
2498 }
2499 ieee->queue_stop = 1;
2500 //spin_unlock_irqrestore(&ieee->lock,flags);
2501
2502}
2503
2504
2505inline void ieee80211_randomize_cell(struct ieee80211_device *ieee)
2506{
2507
2508 get_random_bytes(ieee->current_network.bssid, ETH_ALEN);
2509
2510 /* an IBSS cell address must have the two less significant
2511 * bits of the first byte = 2
2512 */
2513 ieee->current_network.bssid[0] &= ~0x01;
2514 ieee->current_network.bssid[0] |= 0x02;
2515}
2516
2517/* called in user context only */
2518void ieee80211_start_master_bss(struct ieee80211_device *ieee)
2519{
2520 ieee->assoc_id = 1;
2521
2522 if (ieee->current_network.ssid_len == 0){
2523 strncpy(ieee->current_network.ssid,
2524 IEEE80211_DEFAULT_TX_ESSID,
2525 IW_ESSID_MAX_SIZE);
2526
2527 ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID);
2528 ieee->ssid_set = 1;
2529 }
2530
2531 memcpy(ieee->current_network.bssid, ieee->dev->dev_addr, ETH_ALEN);
2532
2533 ieee->set_chan(ieee->dev, ieee->current_network.channel);
2534 ieee->state = IEEE80211_LINKED;
2535 ieee->link_change(ieee->dev);
2536 notify_wx_assoc_event(ieee);
2537
2538 if (ieee->data_hard_resume)
2539 ieee->data_hard_resume(ieee->dev);
2540
2541 netif_carrier_on(ieee->dev);
2542}
2543
2544void ieee80211_start_monitor_mode(struct ieee80211_device *ieee)
2545{
2546 if(ieee->raw_tx){
2547
2548 if (ieee->data_hard_resume)
2549 ieee->data_hard_resume(ieee->dev);
2550
2551 netif_carrier_on(ieee->dev);
2552 }
2553}
2554#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2555void ieee80211_start_ibss_wq(struct work_struct *work)
2556{
2557
2558 struct delayed_work *dwork = container_of(work, struct delayed_work, work);
2559 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, start_ibss_wq);
2560#else
2561void ieee80211_start_ibss_wq(struct ieee80211_device *ieee)
2562{
2563#endif
2564 /* iwconfig mode ad-hoc will schedule this and return
2565 * on the other hand this will block further iwconfig SET
2566 * operations because of the wx_sem hold.
2567 * Anyway some most set operations set a flag to speed-up
2568 * (abort) this wq (when syncro scanning) before sleeping
2569 * on the semaphore
2570 */
2571 if(!ieee->proto_started){
2572 printk("==========oh driver down return\n");
2573 return;
2574 }
2575 down(&ieee->wx_sem);
2576 //FIXME:set back to 20M whenever HT for ibss is not ready. Otherwise,after being connected to 40M AP, it will still stay in 40M when set to ibss mode. WB 2009.02.04
2577 HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
2578
2579 if (ieee->current_network.ssid_len == 0){
2580 strcpy(ieee->current_network.ssid,IEEE80211_DEFAULT_TX_ESSID);
2581 ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID);
2582 ieee->ssid_set = 1;
2583 }
2584
2585 /* check if we have this cell in our network list */
2586 ieee80211_softmac_check_all_nets(ieee);
2587
2588
2589#ifdef ENABLE_DOT11D //if creating an ad-hoc, set its channel to 10 temporarily--this is the requirement for ASUS, not 11D, so disable 11d.
2590// if((IS_DOT11D_ENABLE(ieee)) && (ieee->state == IEEE80211_NOLINK))
2591 if (ieee->state == IEEE80211_NOLINK)
2592 ieee->current_network.channel = 6;
2593#endif
2594 /* if not then the state is not linked. Maybe the user swithced to
2595 * ad-hoc mode just after being in monitor mode, or just after
2596 * being very few time in managed mode (so the card have had no
2597 * time to scan all the chans..) or we have just run up the iface
2598 * after setting ad-hoc mode. So we have to give another try..
2599 * Here, in ibss mode, should be safe to do this without extra care
2600 * (in bss mode we had to make sure no-one tryed to associate when
2601 * we had just checked the ieee->state and we was going to start the
2602 * scan) beacause in ibss mode the ieee80211_new_net function, when
2603 * finds a good net, just set the ieee->state to IEEE80211_LINKED,
2604 * so, at worst, we waste a bit of time to initiate an unneeded syncro
2605 * scan, that will stop at the first round because it sees the state
2606 * associated.
2607 */
2608 if (ieee->state == IEEE80211_NOLINK)
2609 ieee80211_start_scan_syncro(ieee);
2610
2611 /* the network definitively is not here.. create a new cell */
2612 if (ieee->state == IEEE80211_NOLINK){
2613 printk("creating new IBSS cell\n");
2614 if(!ieee->wap_set)
2615 ieee80211_randomize_cell(ieee);
2616
2617 if(ieee->modulation & IEEE80211_CCK_MODULATION){
2618
2619 ieee->current_network.rates_len = 4;
2620
2621 ieee->current_network.rates[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB;
2622 ieee->current_network.rates[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB;
2623 ieee->current_network.rates[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB;
2624 ieee->current_network.rates[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB;
2625
2626 }else
2627 ieee->current_network.rates_len = 0;
2628
2629 if(ieee->modulation & IEEE80211_OFDM_MODULATION){
2630 ieee->current_network.rates_ex_len = 8;
2631
2632 ieee->current_network.rates_ex[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB;
2633 ieee->current_network.rates_ex[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB;
2634 ieee->current_network.rates_ex[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB;
2635 ieee->current_network.rates_ex[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB;
2636 ieee->current_network.rates_ex[4] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB;
2637 ieee->current_network.rates_ex[5] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB;
2638 ieee->current_network.rates_ex[6] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB;
2639 ieee->current_network.rates_ex[7] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB;
2640
2641 ieee->rate = 108;
2642 }else{
2643 ieee->current_network.rates_ex_len = 0;
2644 ieee->rate = 22;
2645 }
2646
2647 // By default, WMM function will be disabled in IBSS mode
2648 ieee->current_network.QoS_Enable = 0;
2649 ieee->SetWirelessMode(ieee->dev, IEEE_G);
2650 ieee->current_network.atim_window = 0;
2651 ieee->current_network.capability = WLAN_CAPABILITY_IBSS;
2652 if(ieee->short_slot)
2653 ieee->current_network.capability |= WLAN_CAPABILITY_SHORT_SLOT;
2654
2655 }
2656
2657 ieee->state = IEEE80211_LINKED;
2658
2659 ieee->set_chan(ieee->dev, ieee->current_network.channel);
2660 ieee->link_change(ieee->dev);
2661 if(ieee->LedControlHandler != NULL)
2662 ieee->LedControlHandler(ieee->dev,LED_CTL_LINK);
2663 notify_wx_assoc_event(ieee);
2664
2665 ieee80211_start_send_beacons(ieee);
2666
2667 if (ieee->data_hard_resume)
2668 ieee->data_hard_resume(ieee->dev);
2669 netif_carrier_on(ieee->dev);
2670
2671 up(&ieee->wx_sem);
2672}
2673
2674inline void ieee80211_start_ibss(struct ieee80211_device *ieee)
2675{
2676#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2677 queue_delayed_work(ieee->wq, &ieee->start_ibss_wq, 150);
2678#else
2679 schedule_task(&ieee->start_ibss_wq);
2680#endif
2681}
2682
2683/* this is called only in user context, with wx_sem held */
2684void ieee80211_start_bss(struct ieee80211_device *ieee)
2685{
2686 unsigned long flags;
2687#ifdef ENABLE_DOT11D
2688 //
2689 // Ref: 802.11d 11.1.3.3
2690 // STA shall not start a BSS unless properly formed Beacon frame including a Country IE.
2691 //
2692 if(IS_DOT11D_ENABLE(ieee) && !IS_COUNTRY_IE_VALID(ieee))
2693 {
2694 if(! ieee->bGlobalDomain)
2695 {
2696 return;
2697 }
2698 }
2699#endif
2700 /* check if we have already found the net we
2701 * are interested in (if any).
2702 * if not (we are disassociated and we are not
2703 * in associating / authenticating phase) start the background scanning.
2704 */
2705 ieee80211_softmac_check_all_nets(ieee);
2706
2707 /* ensure no-one start an associating process (thus setting
2708 * the ieee->state to ieee80211_ASSOCIATING) while we
2709 * have just cheked it and we are going to enable scan.
2710 * The ieee80211_new_net function is always called with
2711 * lock held (from both ieee80211_softmac_check_all_nets and
2712 * the rx path), so we cannot be in the middle of such function
2713 */
2714 spin_lock_irqsave(&ieee->lock, flags);
2715
2716 if (ieee->state == IEEE80211_NOLINK){
2717 ieee->actscanning = true;
2718 ieee80211_start_scan(ieee);
2719 }
2720 spin_unlock_irqrestore(&ieee->lock, flags);
2721}
2722
2723#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2724void ieee80211_link_change_wq(struct work_struct *work)
2725{
2726 struct delayed_work *dwork = container_of(work, struct delayed_work, work);
2727 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, link_change_wq);
2728#else
2729void ieee80211_link_change_wq(struct ieee80211_device *ieee)
2730{
2731#endif
2732 ieee->link_change(ieee->dev);
2733}
2734/* called only in userspace context */
2735void ieee80211_disassociate(struct ieee80211_device *ieee)
2736{
2737
2738
2739 netif_carrier_off(ieee->dev);
2740 if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)
2741 ieee80211_reset_queue(ieee);
2742
2743 if (ieee->data_hard_stop)
2744 ieee->data_hard_stop(ieee->dev);
2745#ifdef ENABLE_DOT11D
2746 if(IS_DOT11D_ENABLE(ieee))
2747 Dot11d_Reset(ieee);
2748#endif
2749 ieee->state = IEEE80211_NOLINK;
2750 ieee->is_set_key = false;
2751
2752 //LZM for usb dev crash.
2753 //ieee->link_change(ieee->dev);
2754#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2755 queue_delayed_work(ieee->wq, &ieee->link_change_wq, 0);
2756#else
2757 schedule_task(&ieee->link_change_wq);
2758#endif
2759
2760 //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
2761 notify_wx_assoc_event(ieee);
2762
2763}
2764#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2765void ieee80211_associate_retry_wq(struct work_struct *work)
2766{
2767 struct delayed_work *dwork = container_of(work, struct delayed_work, work);
2768 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, associate_retry_wq);
2769#else
2770void ieee80211_associate_retry_wq(struct ieee80211_device *ieee)
2771{
2772#endif
2773 unsigned long flags;
2774
2775 down(&ieee->wx_sem);
2776 if(!ieee->proto_started)
2777 goto exit;
2778
2779 if(ieee->state != IEEE80211_ASSOCIATING_RETRY)
2780 goto exit;
2781
2782 /* until we do not set the state to IEEE80211_NOLINK
2783 * there are no possibility to have someone else trying
2784 * to start an association procdure (we get here with
2785 * ieee->state = IEEE80211_ASSOCIATING).
2786 * When we set the state to IEEE80211_NOLINK it is possible
2787 * that the RX path run an attempt to associate, but
2788 * both ieee80211_softmac_check_all_nets and the
2789 * RX path works with ieee->lock held so there are no
2790 * problems. If we are still disassociated then start a scan.
2791 * the lock here is necessary to ensure no one try to start
2792 * an association procedure when we have just checked the
2793 * state and we are going to start the scan.
2794 */
2795 ieee->beinretry = true;
2796 ieee->state = IEEE80211_NOLINK;
2797
2798 ieee80211_softmac_check_all_nets(ieee);
2799
2800 spin_lock_irqsave(&ieee->lock, flags);
2801
2802 if(ieee->state == IEEE80211_NOLINK)
2803 {
2804 ieee->actscanning = true;
2805 ieee80211_start_scan(ieee);
2806 }
2807 spin_unlock_irqrestore(&ieee->lock, flags);
2808
2809 ieee->beinretry = false;
2810exit:
2811 up(&ieee->wx_sem);
2812}
2813
2814struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee)
2815{
2816 u8 broadcast_addr[] = {0xff,0xff,0xff,0xff,0xff,0xff};
2817
2818 struct sk_buff *skb;
2819 struct ieee80211_probe_response *b;
2820
2821 skb = ieee80211_probe_resp(ieee, broadcast_addr);
2822
2823 if (!skb)
2824 return NULL;
2825
2826 b = (struct ieee80211_probe_response *) skb->data;
2827 b->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_BEACON);
2828
2829 return skb;
2830
2831}
2832
2833struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee)
2834{
2835 struct sk_buff *skb;
2836 struct ieee80211_probe_response *b;
2837
2838 skb = ieee80211_get_beacon_(ieee);
2839 if(!skb)
2840 return NULL;
2841
2842 b = (struct ieee80211_probe_response *) skb->data;
2843 b->header.seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4);
2844
2845 if (ieee->seq_ctrl[0] == 0xFFF)
2846 ieee->seq_ctrl[0] = 0;
2847 else
2848 ieee->seq_ctrl[0]++;
2849
2850 return skb;
2851}
2852
2853void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee)
2854{
2855 ieee->sync_scan_hurryup = 1;
2856 down(&ieee->wx_sem);
2857 ieee80211_stop_protocol(ieee);
2858 up(&ieee->wx_sem);
2859}
2860
2861
2862void ieee80211_stop_protocol(struct ieee80211_device *ieee)
2863{
2864 if (!ieee->proto_started)
2865 return;
2866
2867 ieee->proto_started = 0;
2868
2869 ieee80211_stop_send_beacons(ieee);
2870 del_timer_sync(&ieee->associate_timer);
2871#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2872 cancel_delayed_work(&ieee->associate_retry_wq);
2873 cancel_delayed_work(&ieee->start_ibss_wq);
2874 cancel_delayed_work(&ieee->link_change_wq);
2875#endif
2876 ieee80211_stop_scan(ieee);
2877
2878 ieee80211_disassociate(ieee);
2879 RemoveAllTS(ieee); //added as we disconnect from the previous BSS, Remove all TS
2880}
2881
2882void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee)
2883{
2884 ieee->sync_scan_hurryup = 0;
2885 down(&ieee->wx_sem);
2886 ieee80211_start_protocol(ieee);
2887 up(&ieee->wx_sem);
2888}
2889
2890void ieee80211_start_protocol(struct ieee80211_device *ieee)
2891{
2892 short ch = 0;
2893 int i = 0;
2894 if (ieee->proto_started)
2895 return;
2896
2897 ieee->proto_started = 1;
2898
2899 if (ieee->current_network.channel == 0){
2900 do{
2901 ch++;
2902 if (ch > MAX_CHANNEL_NUMBER)
2903 return; /* no channel found */
2904#ifdef ENABLE_DOT11D
2905 }while(!GET_DOT11D_INFO(ieee)->channel_map[ch]);
2906#else
2907 }while(!ieee->channel_map[ch]);
2908#endif
2909 ieee->current_network.channel = ch;
2910 }
2911
2912 if (ieee->current_network.beacon_interval == 0)
2913 ieee->current_network.beacon_interval = 100;
2914// printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel);
2915// ieee->set_chan(ieee->dev,ieee->current_network.channel);
2916
2917 for(i = 0; i < 17; i++) {
2918 ieee->last_rxseq_num[i] = -1;
2919 ieee->last_rxfrag_num[i] = -1;
2920 ieee->last_packet_time[i] = 0;
2921 }
2922
2923 ieee->init_wmmparam_flag = 0;//reinitialize AC_xx_PARAM registers.
2924
2925
2926 /* if the user set the MAC of the ad-hoc cell and then
2927 * switch to managed mode, shall we make sure that association
2928 * attempts does not fail just because the user provide the essid
2929 * and the nic is still checking for the AP MAC ??
2930 */
2931 if (ieee->iw_mode == IW_MODE_INFRA)
2932 ieee80211_start_bss(ieee);
2933
2934 else if (ieee->iw_mode == IW_MODE_ADHOC)
2935 ieee80211_start_ibss(ieee);
2936
2937 else if (ieee->iw_mode == IW_MODE_MASTER)
2938 ieee80211_start_master_bss(ieee);
2939
2940 else if(ieee->iw_mode == IW_MODE_MONITOR)
2941 ieee80211_start_monitor_mode(ieee);
2942}
2943
2944
2945#define DRV_NAME "Ieee80211"
2946void ieee80211_softmac_init(struct ieee80211_device *ieee)
2947{
2948 int i;
2949 memset(&ieee->current_network, 0, sizeof(struct ieee80211_network));
2950
2951 ieee->state = IEEE80211_NOLINK;
2952 ieee->sync_scan_hurryup = 0;
2953 for(i = 0; i < 5; i++) {
2954 ieee->seq_ctrl[i] = 0;
2955 }
2956#ifdef ENABLE_DOT11D
2957 ieee->pDot11dInfo = kmalloc(sizeof(RT_DOT11D_INFO), GFP_ATOMIC);
2958 if (!ieee->pDot11dInfo)
2959 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for DOT11D\n");
2960 memset(ieee->pDot11dInfo, 0, sizeof(RT_DOT11D_INFO));
2961#endif
2962 //added for AP roaming
2963 ieee->LinkDetectInfo.SlotNum = 2;
2964 ieee->LinkDetectInfo.NumRecvBcnInPeriod=0;
2965 ieee->LinkDetectInfo.NumRecvDataInPeriod=0;
2966
2967 ieee->assoc_id = 0;
2968 ieee->queue_stop = 0;
2969 ieee->scanning = 0;
2970 ieee->softmac_features = 0; //so IEEE2100-like driver are happy
2971 ieee->wap_set = 0;
2972 ieee->ssid_set = 0;
2973 ieee->proto_started = 0;
2974 ieee->basic_rate = IEEE80211_DEFAULT_BASIC_RATE;
2975 ieee->rate = 22;
2976 ieee->ps = IEEE80211_PS_DISABLED;
2977 ieee->sta_sleep = 0;
2978 ieee->Regdot11HTOperationalRateSet[0]= 0xff;//support MCS 0~7
2979 ieee->Regdot11HTOperationalRateSet[1]= 0xff;//support MCS 8~15
2980 ieee->Regdot11HTOperationalRateSet[4]= 0x01;
2981 //added by amy
2982 ieee->actscanning = false;
2983 ieee->beinretry = false;
2984 ieee->is_set_key = false;
2985 init_mgmt_queue(ieee);
2986
2987 ieee->sta_edca_param[0] = 0x0000A403;
2988 ieee->sta_edca_param[1] = 0x0000A427;
2989 ieee->sta_edca_param[2] = 0x005E4342;
2990 ieee->sta_edca_param[3] = 0x002F3262;
2991 ieee->aggregation = true;
2992 ieee->enable_rx_imm_BA = 1;
2993#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2994 init_timer(&ieee->scan_timer);
2995 ieee->scan_timer.data = (unsigned long)ieee;
2996 ieee->scan_timer.function = ieee80211_softmac_scan_cb;
2997#endif
2998 ieee->tx_pending.txb = NULL;
2999
3000 init_timer(&ieee->associate_timer);
3001 ieee->associate_timer.data = (unsigned long)ieee;
3002 ieee->associate_timer.function = ieee80211_associate_abort_cb;
3003
3004 init_timer(&ieee->beacon_timer);
3005 ieee->beacon_timer.data = (unsigned long) ieee;
3006 ieee->beacon_timer.function = ieee80211_send_beacon_cb;
3007
3008#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3009#ifdef PF_SYNCTHREAD
3010 ieee->wq = create_workqueue(DRV_NAME,0);
3011#else
3012 ieee->wq = create_workqueue(DRV_NAME);
3013#endif
3014#endif
3015
3016#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3017#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3018 INIT_DELAYED_WORK(&ieee->link_change_wq,ieee80211_link_change_wq);
3019 INIT_DELAYED_WORK(&ieee->start_ibss_wq,ieee80211_start_ibss_wq);
3020 INIT_WORK(&ieee->associate_complete_wq, ieee80211_associate_complete_wq);
3021 INIT_WORK(&ieee->associate_procedure_wq, ieee80211_associate_procedure_wq);
3022 INIT_DELAYED_WORK(&ieee->softmac_scan_wq,ieee80211_softmac_scan_wq);
3023 INIT_DELAYED_WORK(&ieee->associate_retry_wq, ieee80211_associate_retry_wq);
3024 INIT_WORK(&ieee->wx_sync_scan_wq,ieee80211_wx_sync_scan_wq);
3025
3026#else
3027 INIT_WORK(&ieee->link_change_wq,(void(*)(void*)) ieee80211_link_change_wq,ieee);
3028 INIT_WORK(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee);
3029 INIT_WORK(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee);
3030 INIT_WORK(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee);
3031 INIT_WORK(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee);
3032 INIT_WORK(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee);
3033 INIT_WORK(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee);
3034#endif
3035
3036#else
3037 tq_init(&ieee->link_change_wq,(void(*)(void*)) ieee80211_link_change_wq,ieee);
3038 tq_init(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee);
3039 tq_init(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee);
3040 tq_init(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee);
3041 tq_init(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee);
3042 tq_init(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee);
3043 tq_init(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee);
3044#endif
3045 sema_init(&ieee->wx_sem, 1);
3046 sema_init(&ieee->scan_sem, 1);
3047
3048 spin_lock_init(&ieee->mgmt_tx_lock);
3049 spin_lock_init(&ieee->beacon_lock);
3050
3051 tasklet_init(&ieee->ps_task,
3052 (void(*)(unsigned long)) ieee80211_sta_ps,
3053 (unsigned long)ieee);
3054
3055}
3056
3057void ieee80211_softmac_free(struct ieee80211_device *ieee)
3058{
3059 down(&ieee->wx_sem);
3060#ifdef ENABLE_DOT11D
3061 if(NULL != ieee->pDot11dInfo)
3062 {
3063 kfree(ieee->pDot11dInfo);
3064 ieee->pDot11dInfo = NULL;
3065 }
3066#endif
3067 del_timer_sync(&ieee->associate_timer);
3068
3069#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3070 cancel_delayed_work(&ieee->associate_retry_wq);
3071 destroy_workqueue(ieee->wq);
3072#endif
3073
3074 up(&ieee->wx_sem);
3075}
3076
3077/********************************************************
3078 * Start of WPA code. *
3079 * this is stolen from the ipw2200 driver *
3080 ********************************************************/
3081
3082
3083static int ieee80211_wpa_enable(struct ieee80211_device *ieee, int value)
3084{
3085 /* This is called when wpa_supplicant loads and closes the driver
3086 * interface. */
3087 printk("%s WPA\n",value ? "enabling" : "disabling");
3088 ieee->wpa_enabled = value;
3089 memset(ieee->ap_mac_addr, 0, 6); //reset ap_mac_addr everytime it starts wpa.
3090 return 0;
3091}
3092
3093
3094void ieee80211_wpa_assoc_frame(struct ieee80211_device *ieee, char *wpa_ie, int wpa_ie_len)
3095{
3096 /* make sure WPA is enabled */
3097 ieee80211_wpa_enable(ieee, 1);
3098
3099 ieee80211_disassociate(ieee);
3100}
3101
3102
3103static int ieee80211_wpa_mlme(struct ieee80211_device *ieee, int command, int reason)
3104{
3105
3106 int ret = 0;
3107
3108 switch (command) {
3109 case IEEE_MLME_STA_DEAUTH:
3110 // silently ignore
3111 break;
3112
3113 case IEEE_MLME_STA_DISASSOC:
3114 ieee80211_disassociate(ieee);
3115 break;
3116
3117 default:
3118 printk("Unknown MLME request: %d\n", command);
3119 ret = -EOPNOTSUPP;
3120 }
3121
3122 return ret;
3123}
3124
3125
3126static int ieee80211_wpa_set_wpa_ie(struct ieee80211_device *ieee,
3127 struct ieee_param *param, int plen)
3128{
3129 u8 *buf;
3130
3131 if (param->u.wpa_ie.len > MAX_WPA_IE_LEN ||
3132 (param->u.wpa_ie.len && param->u.wpa_ie.data == NULL))
3133 return -EINVAL;
3134
3135 if (param->u.wpa_ie.len) {
3136 buf = kmalloc(param->u.wpa_ie.len, GFP_KERNEL);
3137 if (buf == NULL)
3138 return -ENOMEM;
3139
3140 memcpy(buf, param->u.wpa_ie.data, param->u.wpa_ie.len);
3141 kfree(ieee->wpa_ie);
3142 ieee->wpa_ie = buf;
3143 ieee->wpa_ie_len = param->u.wpa_ie.len;
3144 } else {
3145 kfree(ieee->wpa_ie);
3146 ieee->wpa_ie = NULL;
3147 ieee->wpa_ie_len = 0;
3148 }
3149
3150 ieee80211_wpa_assoc_frame(ieee, ieee->wpa_ie, ieee->wpa_ie_len);
3151 return 0;
3152}
3153
3154#define AUTH_ALG_OPEN_SYSTEM 0x1
3155#define AUTH_ALG_SHARED_KEY 0x2
3156#define AUTH_ALG_LEAP 0x4
3157static int ieee80211_wpa_set_auth_algs(struct ieee80211_device *ieee, int value)
3158{
3159
3160 struct ieee80211_security sec = {
3161 .flags = SEC_AUTH_MODE,
3162 };
3163 int ret = 0;
3164
3165 if (value & AUTH_ALG_SHARED_KEY) {
3166 sec.auth_mode = WLAN_AUTH_SHARED_KEY;
3167 ieee->open_wep = 0;
3168 ieee->auth_mode = 1;
3169 } else if (value & AUTH_ALG_OPEN_SYSTEM){
3170 sec.auth_mode = WLAN_AUTH_OPEN;
3171 ieee->open_wep = 1;
3172 ieee->auth_mode = 0;
3173 }
3174 else if (value & AUTH_ALG_LEAP){
3175 sec.auth_mode = WLAN_AUTH_LEAP;
3176 ieee->open_wep = 1;
3177 ieee->auth_mode = 2;
3178 }
3179
3180
3181 if (ieee->set_security)
3182 ieee->set_security(ieee->dev, &sec);
3183 //else
3184 // ret = -EOPNOTSUPP;
3185
3186 return ret;
3187}
3188
3189static int ieee80211_wpa_set_param(struct ieee80211_device *ieee, u8 name, u32 value)
3190{
3191 int ret=0;
3192 unsigned long flags;
3193
3194 switch (name) {
3195 case IEEE_PARAM_WPA_ENABLED:
3196 ret = ieee80211_wpa_enable(ieee, value);
3197 break;
3198
3199 case IEEE_PARAM_TKIP_COUNTERMEASURES:
3200 ieee->tkip_countermeasures=value;
3201 break;
3202
3203 case IEEE_PARAM_DROP_UNENCRYPTED: {
3204 /* HACK:
3205 *
3206 * wpa_supplicant calls set_wpa_enabled when the driver
3207 * is loaded and unloaded, regardless of if WPA is being
3208 * used. No other calls are made which can be used to
3209 * determine if encryption will be used or not prior to
3210 * association being expected. If encryption is not being
3211 * used, drop_unencrypted is set to false, else true -- we
3212 * can use this to determine if the CAP_PRIVACY_ON bit should
3213 * be set.
3214 */
3215 struct ieee80211_security sec = {
3216 .flags = SEC_ENABLED,
3217 .enabled = value,
3218 };
3219 ieee->drop_unencrypted = value;
3220 /* We only change SEC_LEVEL for open mode. Others
3221 * are set by ipw_wpa_set_encryption.
3222 */
3223 if (!value) {
3224 sec.flags |= SEC_LEVEL;
3225 sec.level = SEC_LEVEL_0;
3226 }
3227 else {
3228 sec.flags |= SEC_LEVEL;
3229 sec.level = SEC_LEVEL_1;
3230 }
3231 if (ieee->set_security)
3232 ieee->set_security(ieee->dev, &sec);
3233 break;
3234 }
3235
3236 case IEEE_PARAM_PRIVACY_INVOKED:
3237 ieee->privacy_invoked=value;
3238 break;
3239
3240 case IEEE_PARAM_AUTH_ALGS:
3241 ret = ieee80211_wpa_set_auth_algs(ieee, value);
3242 break;
3243
3244 case IEEE_PARAM_IEEE_802_1X:
3245 ieee->ieee802_1x=value;
3246 break;
3247 case IEEE_PARAM_WPAX_SELECT:
3248 // added for WPA2 mixed mode
3249 spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);
3250 ieee->wpax_type_set = 1;
3251 ieee->wpax_type_notify = value;
3252 spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);
3253 break;
3254
3255 default:
3256 printk("Unknown WPA param: %d\n",name);
3257 ret = -EOPNOTSUPP;
3258 }
3259
3260 return ret;
3261}
3262
3263/* implementation borrowed from hostap driver */
3264
3265static int ieee80211_wpa_set_encryption(struct ieee80211_device *ieee,
3266 struct ieee_param *param, int param_len)
3267{
3268 int ret = 0;
3269
3270 struct ieee80211_crypto_ops *ops;
3271 struct ieee80211_crypt_data **crypt;
3272
3273 struct ieee80211_security sec = {
3274 .flags = 0,
3275 };
3276
3277 param->u.crypt.err = 0;
3278 param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
3279
3280 if (param_len !=
3281 (int) ((char *) param->u.crypt.key - (char *) param) +
3282 param->u.crypt.key_len) {
3283 printk("Len mismatch %d, %d\n", param_len,
3284 param->u.crypt.key_len);
3285 return -EINVAL;
3286 }
3287 if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
3288 param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
3289 param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
3290 if (param->u.crypt.idx >= WEP_KEYS)
3291 return -EINVAL;
3292 crypt = &ieee->crypt[param->u.crypt.idx];
3293 } else {
3294 return -EINVAL;
3295 }
3296
3297 if (strcmp(param->u.crypt.alg, "none") == 0) {
3298 if (crypt) {
3299 sec.enabled = 0;
3300 // FIXME FIXME
3301 //sec.encrypt = 0;
3302 sec.level = SEC_LEVEL_0;
3303 sec.flags |= SEC_ENABLED | SEC_LEVEL;
3304 ieee80211_crypt_delayed_deinit(ieee, crypt);
3305 }
3306 goto done;
3307 }
3308 sec.enabled = 1;
3309// FIXME FIXME
3310// sec.encrypt = 1;
3311 sec.flags |= SEC_ENABLED;
3312
3313 /* IPW HW cannot build TKIP MIC, host decryption still needed. */
3314 if (!(ieee->host_encrypt || ieee->host_decrypt) &&
3315 strcmp(param->u.crypt.alg, "TKIP"))
3316 goto skip_host_crypt;
3317
3318 ops = ieee80211_get_crypto_ops(param->u.crypt.alg);
3319 if (ops == NULL && strcmp(param->u.crypt.alg, "WEP") == 0) {
3320 request_module("ieee80211_crypt_wep");
3321 ops = ieee80211_get_crypto_ops(param->u.crypt.alg);
3322 //set WEP40 first, it will be modified according to WEP104 or WEP40 at other place
3323 } else if (ops == NULL && strcmp(param->u.crypt.alg, "TKIP") == 0) {
3324 request_module("ieee80211_crypt_tkip");
3325 ops = ieee80211_get_crypto_ops(param->u.crypt.alg);
3326 } else if (ops == NULL && strcmp(param->u.crypt.alg, "CCMP") == 0) {
3327 request_module("ieee80211_crypt_ccmp");
3328 ops = ieee80211_get_crypto_ops(param->u.crypt.alg);
3329 }
3330 if (ops == NULL) {
3331 printk("unknown crypto alg '%s'\n", param->u.crypt.alg);
3332 param->u.crypt.err = IEEE_CRYPT_ERR_UNKNOWN_ALG;
3333 ret = -EINVAL;
3334 goto done;
3335 }
3336
3337 if (*crypt == NULL || (*crypt)->ops != ops) {
3338 struct ieee80211_crypt_data *new_crypt;
3339
3340 ieee80211_crypt_delayed_deinit(ieee, crypt);
3341
3342 new_crypt = (struct ieee80211_crypt_data *)
3343 kmalloc(sizeof(*new_crypt), GFP_KERNEL);
3344 if (new_crypt == NULL) {
3345 ret = -ENOMEM;
3346 goto done;
3347 }
3348 memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data));
3349 new_crypt->ops = ops;
3350#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3351 if (new_crypt->ops && try_module_get(new_crypt->ops->owner))
3352#else
3353 if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner))
3354#endif
3355 new_crypt->priv =
3356 new_crypt->ops->init(param->u.crypt.idx);
3357
3358 if (new_crypt->priv == NULL) {
3359 kfree(new_crypt);
3360 param->u.crypt.err = IEEE_CRYPT_ERR_CRYPT_INIT_FAILED;
3361 ret = -EINVAL;
3362 goto done;
3363 }
3364
3365 *crypt = new_crypt;
3366 }
3367
3368 if (param->u.crypt.key_len > 0 && (*crypt)->ops->set_key &&
3369 (*crypt)->ops->set_key(param->u.crypt.key,
3370 param->u.crypt.key_len, param->u.crypt.seq,
3371 (*crypt)->priv) < 0) {
3372 printk("key setting failed\n");
3373 param->u.crypt.err = IEEE_CRYPT_ERR_KEY_SET_FAILED;
3374 ret = -EINVAL;
3375 goto done;
3376 }
3377
3378 skip_host_crypt:
3379 if (param->u.crypt.set_tx) {
3380 ieee->tx_keyidx = param->u.crypt.idx;
3381 sec.active_key = param->u.crypt.idx;
3382 sec.flags |= SEC_ACTIVE_KEY;
3383 } else
3384 sec.flags &= ~SEC_ACTIVE_KEY;
3385
3386 if (param->u.crypt.alg != NULL) {
3387 memcpy(sec.keys[param->u.crypt.idx],
3388 param->u.crypt.key,
3389 param->u.crypt.key_len);
3390 sec.key_sizes[param->u.crypt.idx] = param->u.crypt.key_len;
3391 sec.flags |= (1 << param->u.crypt.idx);
3392
3393 if (strcmp(param->u.crypt.alg, "WEP") == 0) {
3394 sec.flags |= SEC_LEVEL;
3395 sec.level = SEC_LEVEL_1;
3396 } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
3397 sec.flags |= SEC_LEVEL;
3398 sec.level = SEC_LEVEL_2;
3399 } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
3400 sec.flags |= SEC_LEVEL;
3401 sec.level = SEC_LEVEL_3;
3402 }
3403 }
3404 done:
3405 if (ieee->set_security)
3406 ieee->set_security(ieee->dev, &sec);
3407
3408 /* Do not reset port if card is in Managed mode since resetting will
3409 * generate new IEEE 802.11 authentication which may end up in looping
3410 * with IEEE 802.1X. If your hardware requires a reset after WEP
3411 * configuration (for example... Prism2), implement the reset_port in
3412 * the callbacks structures used to initialize the 802.11 stack. */
3413 if (ieee->reset_on_keychange &&
3414 ieee->iw_mode != IW_MODE_INFRA &&
3415 ieee->reset_port &&
3416 ieee->reset_port(ieee->dev)) {
3417 printk("reset_port failed\n");
3418 param->u.crypt.err = IEEE_CRYPT_ERR_CARD_CONF_FAILED;
3419 return -EINVAL;
3420 }
3421
3422 return ret;
3423}
3424
3425inline struct sk_buff *ieee80211_disassociate_skb(
3426 struct ieee80211_network *beacon,
3427 struct ieee80211_device *ieee,
3428 u8 asRsn)
3429{
3430 struct sk_buff *skb;
3431 struct ieee80211_disassoc *disass;
3432
3433 skb = dev_alloc_skb(sizeof(struct ieee80211_disassoc));
3434 if (!skb)
3435 return NULL;
3436
3437 disass = (struct ieee80211_disassoc *) skb_put(skb,sizeof(struct ieee80211_disassoc));
3438 disass->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_DISASSOC);
3439 disass->header.duration_id = 0;
3440
3441 memcpy(disass->header.addr1, beacon->bssid, ETH_ALEN);
3442 memcpy(disass->header.addr2, ieee->dev->dev_addr, ETH_ALEN);
3443 memcpy(disass->header.addr3, beacon->bssid, ETH_ALEN);
3444
3445 disass->reason = asRsn;
3446 return skb;
3447}
3448
3449
3450void
3451SendDisassociation(
3452 struct ieee80211_device *ieee,
3453 u8* asSta,
3454 u8 asRsn
3455)
3456{
3457 struct ieee80211_network *beacon = &ieee->current_network;
3458 struct sk_buff *skb;
3459 skb = ieee80211_disassociate_skb(beacon,ieee,asRsn);
3460 if (skb){
3461 softmac_mgmt_xmit(skb, ieee);
3462 //dev_kfree_skb_any(skb);//edit by thomas
3463 }
3464}
3465
3466int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p)
3467{
3468 struct ieee_param *param;
3469 int ret=0;
3470
3471 down(&ieee->wx_sem);
3472 //IEEE_DEBUG_INFO("wpa_supplicant: len=%d\n", p->length);
3473
3474 if (p->length < sizeof(struct ieee_param) || !p->pointer){
3475 ret = -EINVAL;
3476 goto out;
3477 }
3478
3479 param = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL);
3480 if (param == NULL){
3481 ret = -ENOMEM;
3482 goto out;
3483 }
3484 if (copy_from_user(param, p->pointer, p->length)) {
3485 kfree(param);
3486 ret = -EFAULT;
3487 goto out;
3488 }
3489
3490 switch (param->cmd) {
3491
3492 case IEEE_CMD_SET_WPA_PARAM:
3493 ret = ieee80211_wpa_set_param(ieee, param->u.wpa_param.name,
3494 param->u.wpa_param.value);
3495 break;
3496
3497 case IEEE_CMD_SET_WPA_IE:
3498 ret = ieee80211_wpa_set_wpa_ie(ieee, param, p->length);
3499 break;
3500
3501 case IEEE_CMD_SET_ENCRYPTION:
3502 ret = ieee80211_wpa_set_encryption(ieee, param, p->length);
3503 break;
3504
3505 case IEEE_CMD_MLME:
3506 ret = ieee80211_wpa_mlme(ieee, param->u.mlme.command,
3507 param->u.mlme.reason_code);
3508 break;
3509
3510 default:
3511 printk("Unknown WPA supplicant request: %d\n",param->cmd);
3512 ret = -EOPNOTSUPP;
3513 break;
3514 }
3515
3516 if (ret == 0 && copy_to_user(p->pointer, param, p->length))
3517 ret = -EFAULT;
3518
3519 kfree(param);
3520out:
3521 up(&ieee->wx_sem);
3522
3523 return ret;
3524}
3525
3526void notify_wx_assoc_event(struct ieee80211_device *ieee)
3527{
3528 union iwreq_data wrqu;
3529 wrqu.ap_addr.sa_family = ARPHRD_ETHER;
3530 if (ieee->state == IEEE80211_LINKED)
3531 memcpy(wrqu.ap_addr.sa_data, ieee->current_network.bssid, ETH_ALEN);
3532 else
3533 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
3534 wireless_send_event(ieee->dev, SIOCGIWAP, &wrqu, NULL);
3535}
3536
3537#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
3538EXPORT_SYMBOL(ieee80211_get_beacon);
3539EXPORT_SYMBOL(ieee80211_wake_queue);
3540EXPORT_SYMBOL(ieee80211_stop_queue);
3541EXPORT_SYMBOL(ieee80211_reset_queue);
3542EXPORT_SYMBOL(ieee80211_softmac_stop_protocol);
3543EXPORT_SYMBOL(ieee80211_softmac_start_protocol);
3544EXPORT_SYMBOL(ieee80211_is_shortslot);
3545EXPORT_SYMBOL(ieee80211_is_54g);
3546EXPORT_SYMBOL(ieee80211_wpa_supplicant_ioctl);
3547EXPORT_SYMBOL(ieee80211_ps_tx_ack);
3548EXPORT_SYMBOL(ieee80211_softmac_xmit);
3549EXPORT_SYMBOL(ieee80211_stop_send_beacons);
3550EXPORT_SYMBOL(notify_wx_assoc_event);
3551EXPORT_SYMBOL(SendDisassociation);
3552EXPORT_SYMBOL(ieee80211_disassociate);
3553EXPORT_SYMBOL(ieee80211_start_send_beacons);
3554EXPORT_SYMBOL(ieee80211_stop_scan);
3555EXPORT_SYMBOL(ieee80211_send_probe_requests);
3556EXPORT_SYMBOL(ieee80211_softmac_scan_syncro);
3557EXPORT_SYMBOL(ieee80211_start_scan_syncro);
3558#else
3559EXPORT_SYMBOL_NOVERS(ieee80211_get_beacon);
3560EXPORT_SYMBOL_NOVERS(ieee80211_wake_queue);
3561EXPORT_SYMBOL_NOVERS(ieee80211_stop_queue);
3562EXPORT_SYMBOL_NOVERS(ieee80211_reset_queue);
3563EXPORT_SYMBOL_NOVERS(ieee80211_softmac_stop_protocol);
3564EXPORT_SYMBOL_NOVERS(ieee80211_softmac_start_protocol);
3565EXPORT_SYMBOL_NOVERS(ieee80211_is_shortslot);
3566EXPORT_SYMBOL_NOVERS(ieee80211_is_54g);
3567EXPORT_SYMBOL_NOVERS(ieee80211_wpa_supplicant_ioctl);
3568EXPORT_SYMBOL_NOVERS(ieee80211_ps_tx_ack);
3569EXPORT_SYMBOL_NOVERS(ieee80211_softmac_xmit);
3570EXPORT_SYMBOL_NOVERS(ieee80211_stop_send_beacons);
3571EXPORT_SYMBOL_NOVERS(notify_wx_assoc_event);
3572EXPORT_SYMBOL_NOVERS(SendDisassociation);
3573EXPORT_SYMBOL_NOVERS(ieee80211_disassociate);
3574EXPORT_SYMBOL_NOVERS(ieee80211_start_send_beacons);
3575EXPORT_SYMBOL_NOVERS(ieee80211_stop_scan);
3576EXPORT_SYMBOL_NOVERS(ieee80211_send_probe_requests);
3577EXPORT_SYMBOL_NOVERS(ieee80211_softmac_scan_syncro);
3578EXPORT_SYMBOL_NOVERS(ieee80211_start_scan_syncro);
3579#endif
3580//EXPORT_SYMBOL(ieee80211_sta_ps_send_null_frame);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c
new file mode 100644
index 00000000000..1f50c46dcb9
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c
@@ -0,0 +1,711 @@
1/* IEEE 802.11 SoftMAC layer
2 * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
3 *
4 * Mostly extracted from the rtl8180-sa2400 driver for the
5 * in-kernel generic ieee802.11 stack.
6 *
7 * Some pieces of code might be stolen from ipw2100 driver
8 * copyright of who own it's copyright ;-)
9 *
10 * PS wx handler mostly stolen from hostap, copyright who
11 * own it's copyright ;-)
12 *
13 * released under the GPL
14 */
15
16
17#include "ieee80211.h"
18#ifdef ENABLE_DOT11D
19#include "dot11d.h"
20#endif
21/* FIXME: add A freqs */
22
23const long ieee80211_wlan_frequencies[] = {
24 2412, 2417, 2422, 2427,
25 2432, 2437, 2442, 2447,
26 2452, 2457, 2462, 2467,
27 2472, 2484
28};
29
30
31int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a,
32 union iwreq_data *wrqu, char *b)
33{
34 int ret;
35 struct iw_freq *fwrq = & wrqu->freq;
36
37 down(&ieee->wx_sem);
38
39 if(ieee->iw_mode == IW_MODE_INFRA){
40 ret = -EOPNOTSUPP;
41 goto out;
42 }
43
44 /* if setting by freq convert to channel */
45 if (fwrq->e == 1) {
46 if ((fwrq->m >= (int) 2.412e8 &&
47 fwrq->m <= (int) 2.487e8)) {
48 int f = fwrq->m / 100000;
49 int c = 0;
50
51 while ((c < 14) && (f != ieee80211_wlan_frequencies[c]))
52 c++;
53
54 /* hack to fall through */
55 fwrq->e = 0;
56 fwrq->m = c + 1;
57 }
58 }
59
60 if (fwrq->e > 0 || fwrq->m > 14 || fwrq->m < 1 ){
61 ret = -EOPNOTSUPP;
62 goto out;
63
64 }else { /* Set the channel */
65
66#ifdef ENABLE_DOT11D
67 if (!(GET_DOT11D_INFO(ieee)->channel_map)[fwrq->m]) {
68 ret = -EINVAL;
69 goto out;
70 }
71#endif
72 ieee->current_network.channel = fwrq->m;
73 ieee->set_chan(ieee->dev, ieee->current_network.channel);
74
75 if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER)
76 if(ieee->state == IEEE80211_LINKED){
77
78 ieee80211_stop_send_beacons(ieee);
79 ieee80211_start_send_beacons(ieee);
80 }
81 }
82
83 ret = 0;
84out:
85 up(&ieee->wx_sem);
86 return ret;
87}
88
89
90int ieee80211_wx_get_freq(struct ieee80211_device *ieee,
91 struct iw_request_info *a,
92 union iwreq_data *wrqu, char *b)
93{
94 struct iw_freq *fwrq = & wrqu->freq;
95
96 if (ieee->current_network.channel == 0)
97 return -1;
98 //NM 0.7.0 will not accept channel any more.
99 fwrq->m = ieee80211_wlan_frequencies[ieee->current_network.channel-1] * 100000;
100 fwrq->e = 1;
101// fwrq->m = ieee->current_network.channel;
102// fwrq->e = 0;
103
104 return 0;
105}
106
107int ieee80211_wx_get_wap(struct ieee80211_device *ieee,
108 struct iw_request_info *info,
109 union iwreq_data *wrqu, char *extra)
110{
111 unsigned long flags;
112
113 wrqu->ap_addr.sa_family = ARPHRD_ETHER;
114
115 if (ieee->iw_mode == IW_MODE_MONITOR)
116 return -1;
117
118 /* We want avoid to give to the user inconsistent infos*/
119 spin_lock_irqsave(&ieee->lock, flags);
120
121 if (ieee->state != IEEE80211_LINKED &&
122 ieee->state != IEEE80211_LINKED_SCANNING &&
123 ieee->wap_set == 0)
124
125 memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
126 else
127 memcpy(wrqu->ap_addr.sa_data,
128 ieee->current_network.bssid, ETH_ALEN);
129
130 spin_unlock_irqrestore(&ieee->lock, flags);
131
132 return 0;
133}
134
135
136int ieee80211_wx_set_wap(struct ieee80211_device *ieee,
137 struct iw_request_info *info,
138 union iwreq_data *awrq,
139 char *extra)
140{
141
142 int ret = 0;
143 u8 zero[] = {0,0,0,0,0,0};
144 unsigned long flags;
145
146 short ifup = ieee->proto_started;//dev->flags & IFF_UP;
147 struct sockaddr *temp = (struct sockaddr *)awrq;
148
149 ieee->sync_scan_hurryup = 1;
150
151 down(&ieee->wx_sem);
152 /* use ifconfig hw ether */
153 if (ieee->iw_mode == IW_MODE_MASTER){
154 ret = -1;
155 goto out;
156 }
157
158 if (temp->sa_family != ARPHRD_ETHER){
159 ret = -EINVAL;
160 goto out;
161 }
162
163 if (ifup)
164 ieee80211_stop_protocol(ieee);
165
166 /* just to avoid to give inconsistent infos in the
167 * get wx method. not really needed otherwise
168 */
169 spin_lock_irqsave(&ieee->lock, flags);
170
171 memcpy(ieee->current_network.bssid, temp->sa_data, ETH_ALEN);
172 ieee->wap_set = memcmp(temp->sa_data, zero,ETH_ALEN)!=0;
173
174 spin_unlock_irqrestore(&ieee->lock, flags);
175
176 if (ifup)
177 ieee80211_start_protocol(ieee);
178out:
179 up(&ieee->wx_sem);
180 return ret;
181}
182
183 int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b)
184{
185 int len,ret = 0;
186 unsigned long flags;
187
188 if (ieee->iw_mode == IW_MODE_MONITOR)
189 return -1;
190
191 /* We want avoid to give to the user inconsistent infos*/
192 spin_lock_irqsave(&ieee->lock, flags);
193
194 if (ieee->current_network.ssid[0] == '\0' ||
195 ieee->current_network.ssid_len == 0){
196 ret = -1;
197 goto out;
198 }
199
200 if (ieee->state != IEEE80211_LINKED &&
201 ieee->state != IEEE80211_LINKED_SCANNING &&
202 ieee->ssid_set == 0){
203 ret = -1;
204 goto out;
205 }
206 len = ieee->current_network.ssid_len;
207 wrqu->essid.length = len;
208 strncpy(b,ieee->current_network.ssid,len);
209 wrqu->essid.flags = 1;
210
211out:
212 spin_unlock_irqrestore(&ieee->lock, flags);
213
214 return ret;
215
216}
217
218int ieee80211_wx_set_rate(struct ieee80211_device *ieee,
219 struct iw_request_info *info,
220 union iwreq_data *wrqu, char *extra)
221{
222
223 u32 target_rate = wrqu->bitrate.value;
224
225 ieee->rate = target_rate/100000;
226 //FIXME: we might want to limit rate also in management protocols.
227 return 0;
228}
229
230
231
232int ieee80211_wx_get_rate(struct ieee80211_device *ieee,
233 struct iw_request_info *info,
234 union iwreq_data *wrqu, char *extra)
235{
236 u32 tmp_rate = 0;
237#ifdef RTL8192SU
238 //printk("===>mode:%d, halfNmode:%d\n", ieee->mode, ieee->bHalfWirelessN24GMode);
239 if (ieee->mode & (IEEE_A | IEEE_B | IEEE_G))
240 tmp_rate = ieee->rate;
241 else if (ieee->mode & IEEE_N_5G)
242 tmp_rate = 580;
243 else if (ieee->mode & IEEE_N_24G)
244 {
245 if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))
246 tmp_rate = HTHalfMcsToDataRate(ieee, 15);
247 else
248 tmp_rate = HTMcsToDataRate(ieee, 15);
249 }
250#else
251 tmp_rate = TxCountToDataRate(ieee, ieee->softmac_stats.CurrentShowTxate);
252
253#endif
254 wrqu->bitrate.value = tmp_rate * 500000;
255
256 return 0;
257}
258
259
260int ieee80211_wx_set_rts(struct ieee80211_device *ieee,
261 struct iw_request_info *info,
262 union iwreq_data *wrqu, char *extra)
263{
264 if (wrqu->rts.disabled || !wrqu->rts.fixed)
265 ieee->rts = DEFAULT_RTS_THRESHOLD;
266 else
267 {
268 if (wrqu->rts.value < MIN_RTS_THRESHOLD ||
269 wrqu->rts.value > MAX_RTS_THRESHOLD)
270 return -EINVAL;
271 ieee->rts = wrqu->rts.value;
272 }
273 return 0;
274}
275
276int ieee80211_wx_get_rts(struct ieee80211_device *ieee,
277 struct iw_request_info *info,
278 union iwreq_data *wrqu, char *extra)
279{
280 wrqu->rts.value = ieee->rts;
281 wrqu->rts.fixed = 0; /* no auto select */
282 wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD);
283 return 0;
284}
285int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
286 union iwreq_data *wrqu, char *b)
287{
288
289 ieee->sync_scan_hurryup = 1;
290
291 down(&ieee->wx_sem);
292
293 if (wrqu->mode == ieee->iw_mode)
294 goto out;
295
296 if (wrqu->mode == IW_MODE_MONITOR){
297
298 ieee->dev->type = ARPHRD_IEEE80211;
299 }else{
300 ieee->dev->type = ARPHRD_ETHER;
301 }
302
303 if (!ieee->proto_started){
304 ieee->iw_mode = wrqu->mode;
305 }else{
306 ieee80211_stop_protocol(ieee);
307 ieee->iw_mode = wrqu->mode;
308 ieee80211_start_protocol(ieee);
309 }
310
311out:
312 up(&ieee->wx_sem);
313 return 0;
314}
315
316#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
317void ieee80211_wx_sync_scan_wq(struct work_struct *work)
318{
319 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wx_sync_scan_wq);
320#else
321void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee)
322{
323#endif
324 short chan;
325 HT_EXTCHNL_OFFSET chan_offset=0;
326 HT_CHANNEL_WIDTH bandwidth=0;
327 int b40M = 0;
328 static int count = 0;
329 chan = ieee->current_network.channel;
330 netif_carrier_off(ieee->dev);
331
332 if (ieee->data_hard_stop)
333 ieee->data_hard_stop(ieee->dev);
334
335 ieee80211_stop_send_beacons(ieee);
336
337 ieee->state = IEEE80211_LINKED_SCANNING;
338 ieee->link_change(ieee->dev);
339#ifndef RTL8192SE
340 ieee->InitialGainHandler(ieee->dev,IG_Backup);
341#endif
342#if(RTL8192S_DISABLE_FW_DM == 0)
343 if (ieee->SetFwCmdHandler)
344 {
345 ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_HALT);
346 ieee->SetFwCmdHandler(ieee->dev, FW_CMD_HIGH_PWR_DISABLE);
347 }
348#endif
349 if (ieee->pHTInfo->bCurrentHTSupport && ieee->pHTInfo->bEnableHT && ieee->pHTInfo->bCurBW40MHz) {
350 b40M = 1;
351 chan_offset = ieee->pHTInfo->CurSTAExtChnlOffset;
352 bandwidth = (HT_CHANNEL_WIDTH)ieee->pHTInfo->bCurBW40MHz;
353 printk("Scan in 40M, force to 20M first:%d, %d\n", chan_offset, bandwidth);
354 ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
355 }
356 ieee80211_start_scan_syncro(ieee);
357 if (b40M) {
358 printk("Scan in 20M, back to 40M\n");
359 if (chan_offset == HT_EXTCHNL_OFFSET_UPPER)
360 ieee->set_chan(ieee->dev, chan + 2);
361 else if (chan_offset == HT_EXTCHNL_OFFSET_LOWER)
362 ieee->set_chan(ieee->dev, chan - 2);
363 else
364 ieee->set_chan(ieee->dev, chan);
365 ieee->SetBWModeHandler(ieee->dev, bandwidth, chan_offset);
366 } else {
367 ieee->set_chan(ieee->dev, chan);
368 }
369
370#ifndef RTL8192SE
371 ieee->InitialGainHandler(ieee->dev,IG_Restore);
372#endif
373#if(RTL8192S_DISABLE_FW_DM == 0)
374 if (ieee->SetFwCmdHandler)
375 {
376 ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_RESUME);
377 ieee->SetFwCmdHandler(ieee->dev, FW_CMD_HIGH_PWR_ENABLE);
378 }
379#endif
380 ieee->state = IEEE80211_LINKED;
381 ieee->link_change(ieee->dev);
382 // To prevent the immediately calling watch_dog after scan.
383 if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 )
384 {
385 ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1;
386 ieee->LinkDetectInfo.NumRecvDataInPeriod= 1;
387 }
388 if (ieee->data_hard_resume)
389 ieee->data_hard_resume(ieee->dev);
390
391 if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER)
392 ieee80211_start_send_beacons(ieee);
393
394 netif_carrier_on(ieee->dev);
395 count = 0;
396 up(&ieee->wx_sem);
397
398}
399
400int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a,
401 union iwreq_data *wrqu, char *b)
402{
403 int ret = 0;
404
405 down(&ieee->wx_sem);
406
407 if (ieee->iw_mode == IW_MODE_MONITOR || !(ieee->proto_started)){
408 ret = -1;
409 goto out;
410 }
411
412 if ( ieee->state == IEEE80211_LINKED){
413#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
414 queue_work(ieee->wq, &ieee->wx_sync_scan_wq);
415#else
416 schedule_task(&ieee->wx_sync_scan_wq);
417#endif
418 /* intentionally forget to up sem */
419 return 0;
420 }
421
422out:
423 up(&ieee->wx_sem);
424 return ret;
425}
426
427int ieee80211_wx_set_essid(struct ieee80211_device *ieee,
428 struct iw_request_info *a,
429 union iwreq_data *wrqu, char *extra)
430{
431
432 int ret=0,len;
433 short proto_started;
434 unsigned long flags;
435
436 ieee->sync_scan_hurryup = 1;
437 down(&ieee->wx_sem);
438
439 proto_started = ieee->proto_started;
440
441 if (wrqu->essid.length > IW_ESSID_MAX_SIZE){
442 ret= -E2BIG;
443 goto out;
444 }
445
446 if (ieee->iw_mode == IW_MODE_MONITOR){
447 ret= -1;
448 goto out;
449 }
450
451 if(proto_started)
452 ieee80211_stop_protocol(ieee);
453
454
455 /* this is just to be sure that the GET wx callback
456 * has consisten infos. not needed otherwise
457 */
458 spin_lock_irqsave(&ieee->lock, flags);
459
460 if (wrqu->essid.flags && wrqu->essid.length) {
461 //first flush current network.ssid
462 len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE;
463#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
464 strncpy(ieee->current_network.ssid, extra, len);
465 ieee->current_network.ssid_len = len;
466#if 0
467 {
468 int i;
469 for (i=0; i<len; i++)
470 printk("%c ", extra[i]);
471 printk("\n");
472 }
473#endif
474#else
475 strncpy(ieee->current_network.ssid, extra, len+1);
476 ieee->current_network.ssid_len = len+1;
477#if 0
478 {
479 int i;
480 for (i=0; i<len + 1; i++)
481 printk("%c ", extra[i]);
482 printk("\n");
483 }
484#endif
485#endif
486 ieee->ssid_set = 1;
487 }
488 else{
489 ieee->ssid_set = 0;
490 ieee->current_network.ssid[0] = '\0';
491 ieee->current_network.ssid_len = 0;
492 }
493 spin_unlock_irqrestore(&ieee->lock, flags);
494
495 if (proto_started)
496 ieee80211_start_protocol(ieee);
497out:
498 up(&ieee->wx_sem);
499 return ret;
500}
501
502 int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a,
503 union iwreq_data *wrqu, char *b)
504{
505
506 wrqu->mode = ieee->iw_mode;
507 return 0;
508}
509
510 int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee,
511 struct iw_request_info *info,
512 union iwreq_data *wrqu, char *extra)
513{
514
515 int *parms = (int *)extra;
516 int enable = (parms[0] > 0);
517 short prev = ieee->raw_tx;
518
519 down(&ieee->wx_sem);
520
521 if(enable)
522 ieee->raw_tx = 1;
523 else
524 ieee->raw_tx = 0;
525
526 printk(KERN_INFO"raw TX is %s\n",
527 ieee->raw_tx ? "enabled" : "disabled");
528
529 if(ieee->iw_mode == IW_MODE_MONITOR)
530 {
531 if(prev == 0 && ieee->raw_tx){
532 if (ieee->data_hard_resume)
533 ieee->data_hard_resume(ieee->dev);
534
535 netif_carrier_on(ieee->dev);
536 }
537
538 if(prev && ieee->raw_tx == 1)
539 netif_carrier_off(ieee->dev);
540 }
541
542 up(&ieee->wx_sem);
543
544 return 0;
545}
546
547int ieee80211_wx_get_name(struct ieee80211_device *ieee,
548 struct iw_request_info *info,
549 union iwreq_data *wrqu, char *extra)
550{
551 strcpy(wrqu->name, "802.11");
552 if(ieee->modulation & IEEE80211_CCK_MODULATION){
553 strcat(wrqu->name, "b");
554 if(ieee->modulation & IEEE80211_OFDM_MODULATION)
555 strcat(wrqu->name, "/g");
556 }else if(ieee->modulation & IEEE80211_OFDM_MODULATION)
557 strcat(wrqu->name, "g");
558 if (ieee->mode & (IEEE_N_24G | IEEE_N_5G))
559 strcat(wrqu->name, "/n");
560
561 if((ieee->state == IEEE80211_LINKED) ||
562 (ieee->state == IEEE80211_LINKED_SCANNING))
563 strcat(wrqu->name," linked");
564 else if(ieee->state != IEEE80211_NOLINK)
565 strcat(wrqu->name," link..");
566
567
568 return 0;
569}
570
571
572/* this is mostly stolen from hostap */
573int ieee80211_wx_set_power(struct ieee80211_device *ieee,
574 struct iw_request_info *info,
575 union iwreq_data *wrqu, char *extra)
576{
577 int ret = 0;
578#if 1
579 if(
580 (!ieee->sta_wake_up) ||
581 // (!ieee->ps_request_tx_ack) ||
582 (!ieee->enter_sleep_state) ||
583 (!ieee->ps_is_queue_empty)){
584
585 // printk("ERROR. PS mode is tryied to be use but driver missed a callback\n\n");
586
587 return -1;
588 }
589#endif
590 down(&ieee->wx_sem);
591
592 if (wrqu->power.disabled){
593 ieee->ps = IEEE80211_PS_DISABLED;
594 goto exit;
595 }
596 if (wrqu->power.flags & IW_POWER_TIMEOUT) {
597 //ieee->ps_period = wrqu->power.value / 1000;
598 ieee->ps_timeout = wrqu->power.value / 1000;
599 }
600
601 if (wrqu->power.flags & IW_POWER_PERIOD) {
602
603 //ieee->ps_timeout = wrqu->power.value / 1000;
604 ieee->ps_period = wrqu->power.value / 1000;
605 //wrq->value / 1024;
606
607 }
608 switch (wrqu->power.flags & IW_POWER_MODE) {
609 case IW_POWER_UNICAST_R:
610 ieee->ps = IEEE80211_PS_UNICAST;
611 break;
612 case IW_POWER_MULTICAST_R:
613 ieee->ps = IEEE80211_PS_MBCAST;
614 break;
615 case IW_POWER_ALL_R:
616 ieee->ps = IEEE80211_PS_UNICAST | IEEE80211_PS_MBCAST;
617 break;
618
619 case IW_POWER_ON:
620 // ieee->ps = IEEE80211_PS_DISABLED;
621 break;
622
623 default:
624 ret = -EINVAL;
625 goto exit;
626
627 }
628exit:
629 up(&ieee->wx_sem);
630 return ret;
631
632}
633
634/* this is stolen from hostap */
635int ieee80211_wx_get_power(struct ieee80211_device *ieee,
636 struct iw_request_info *info,
637 union iwreq_data *wrqu, char *extra)
638{
639 int ret =0;
640
641 down(&ieee->wx_sem);
642
643 if(ieee->ps == IEEE80211_PS_DISABLED){
644 wrqu->power.disabled = 1;
645 goto exit;
646 }
647
648 wrqu->power.disabled = 0;
649
650 if ((wrqu->power.flags & IW_POWER_TYPE) == IW_POWER_TIMEOUT) {
651 wrqu->power.flags = IW_POWER_TIMEOUT;
652 wrqu->power.value = ieee->ps_timeout * 1000;
653 } else {
654// ret = -EOPNOTSUPP;
655// goto exit;
656 wrqu->power.flags = IW_POWER_PERIOD;
657 wrqu->power.value = ieee->ps_period * 1000;
658//ieee->current_network.dtim_period * ieee->current_network.beacon_interval * 1024;
659 }
660
661 if ((ieee->ps & (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST)) == (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST))
662 wrqu->power.flags |= IW_POWER_ALL_R;
663 else if (ieee->ps & IEEE80211_PS_MBCAST)
664 wrqu->power.flags |= IW_POWER_MULTICAST_R;
665 else
666 wrqu->power.flags |= IW_POWER_UNICAST_R;
667
668exit:
669 up(&ieee->wx_sem);
670 return ret;
671
672}
673#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
674EXPORT_SYMBOL(ieee80211_wx_get_essid);
675EXPORT_SYMBOL(ieee80211_wx_set_essid);
676EXPORT_SYMBOL(ieee80211_wx_set_rate);
677EXPORT_SYMBOL(ieee80211_wx_get_rate);
678EXPORT_SYMBOL(ieee80211_wx_set_wap);
679EXPORT_SYMBOL(ieee80211_wx_get_wap);
680EXPORT_SYMBOL(ieee80211_wx_set_mode);
681EXPORT_SYMBOL(ieee80211_wx_get_mode);
682EXPORT_SYMBOL(ieee80211_wx_set_scan);
683EXPORT_SYMBOL(ieee80211_wx_get_freq);
684EXPORT_SYMBOL(ieee80211_wx_set_freq);
685EXPORT_SYMBOL(ieee80211_wx_set_rawtx);
686EXPORT_SYMBOL(ieee80211_wx_get_name);
687EXPORT_SYMBOL(ieee80211_wx_set_power);
688EXPORT_SYMBOL(ieee80211_wx_get_power);
689EXPORT_SYMBOL(ieee80211_wlan_frequencies);
690EXPORT_SYMBOL(ieee80211_wx_set_rts);
691EXPORT_SYMBOL(ieee80211_wx_get_rts);
692#else
693EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_essid);
694EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_essid);
695EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rate);
696EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rate);
697EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_wap);
698EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_wap);
699EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mode);
700EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_mode);
701EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_scan);
702EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_freq);
703EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_freq);
704EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rawtx);
705EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_name);
706EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_power);
707EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_power);
708EXPORT_SYMBOL_NOVERS(ieee80211_wlan_frequencies);
709EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rts);
710EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rts);
711#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
new file mode 100644
index 00000000000..7294572b990
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
@@ -0,0 +1,947 @@
1/******************************************************************************
2
3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 more details.
13
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17
18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
20
21 Contact Information:
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************
26
27 Few modifications for Realtek's Wi-Fi drivers by
28 Andrea Merello <andreamrl@tiscali.it>
29
30 A special thanks goes to Realtek for their support !
31
32******************************************************************************/
33
34#include <linux/compiler.h>
35//#include <linux/config.h>
36#include <linux/errno.h>
37#include <linux/if_arp.h>
38#include <linux/in6.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/netdevice.h>
44#include <linux/pci.h>
45#include <linux/proc_fs.h>
46#include <linux/skbuff.h>
47#include <linux/slab.h>
48#include <linux/tcp.h>
49#include <linux/types.h>
50#include <linux/version.h>
51#include <linux/wireless.h>
52#include <linux/etherdevice.h>
53#include <asm/uaccess.h>
54#include <linux/if_vlan.h>
55
56#include "ieee80211.h"
57
58
59/*
60
61
62802.11 Data Frame
63
64
65802.11 frame_contorl for data frames - 2 bytes
66 ,-----------------------------------------------------------------------------------------.
67bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e |
68 |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|
69val | 0 | 0 | 0 | 1 | x | 0 | 0 | 0 | 1 | 0 | x | x | x | x | x |
70 |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|
71desc | ^-ver-^ | ^type-^ | ^-----subtype-----^ | to |from |more |retry| pwr |more |wep |
72 | | | x=0 data,x=1 data+ack | DS | DS |frag | | mgm |data | |
73 '-----------------------------------------------------------------------------------------'
74 /\
75 |
76802.11 Data Frame |
77 ,--------- 'ctrl' expands to >-----------'
78 |
79 ,--'---,-------------------------------------------------------------.
80Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
81 |------|------|---------|---------|---------|------|---------|------|
82Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | Frame | fcs |
83 | | tion | (BSSID) | | | ence | data | |
84 `--------------------------------------------------| |------'
85Total: 28 non-data bytes `----.----'
86 |
87 .- 'Frame data' expands to <---------------------------'
88 |
89 V
90 ,---------------------------------------------------.
91Bytes | 1 | 1 | 1 | 3 | 2 | 0-2304 |
92 |------|------|---------|----------|------|---------|
93Desc. | SNAP | SNAP | Control |Eth Tunnel| Type | IP |
94 | DSAP | SSAP | | | | Packet |
95 | 0xAA | 0xAA |0x03 (UI)|0x00-00-F8| | |
96 `-----------------------------------------| |
97Total: 8 non-data bytes `----.----'
98 |
99 .- 'IP Packet' expands, if WEP enabled, to <--'
100 |
101 V
102 ,-----------------------.
103Bytes | 4 | 0-2296 | 4 |
104 |-----|-----------|-----|
105Desc. | IV | Encrypted | ICV |
106 | | IP Packet | |
107 `-----------------------'
108Total: 8 non-data bytes
109
110
111802.3 Ethernet Data Frame
112
113 ,-----------------------------------------.
114Bytes | 6 | 6 | 2 | Variable | 4 |
115 |-------|-------|------|-----------|------|
116Desc. | Dest. | Source| Type | IP Packet | fcs |
117 | MAC | MAC | | | |
118 `-----------------------------------------'
119Total: 18 non-data bytes
120
121In the event that fragmentation is required, the incoming payload is split into
122N parts of size ieee->fts. The first fragment contains the SNAP header and the
123remaining packets are just data.
124
125If encryption is enabled, each fragment payload size is reduced by enough space
126to add the prefix and postfix (IV and ICV totalling 8 bytes in the case of WEP)
127So if you have 1500 bytes of payload with ieee->fts set to 500 without
128encryption it will take 3 frames. With WEP it will take 4 frames as the
129payload of each frame is reduced to 492 bytes.
130
131* SKB visualization
132*
133* ,- skb->data
134* |
135* | ETHERNET HEADER ,-<-- PAYLOAD
136* | | 14 bytes from skb->data
137* | 2 bytes for Type --> ,T. | (sizeof ethhdr)
138* | | | |
139* |,-Dest.--. ,--Src.---. | | |
140* | 6 bytes| | 6 bytes | | | |
141* v | | | | | |
142* 0 | v 1 | v | v 2
143* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
144* ^ | ^ | ^ |
145* | | | | | |
146* | | | | `T' <---- 2 bytes for Type
147* | | | |
148* | | '---SNAP--' <-------- 6 bytes for SNAP
149* | |
150* `-IV--' <-------------------- 4 bytes for IV (WEP)
151*
152* SNAP HEADER
153*
154*/
155
156static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
157static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
158
159static inline int ieee80211_put_snap(u8 *data, u16 h_proto)
160{
161 struct ieee80211_snap_hdr *snap;
162 u8 *oui;
163
164 snap = (struct ieee80211_snap_hdr *)data;
165 snap->dsap = 0xaa;
166 snap->ssap = 0xaa;
167 snap->ctrl = 0x03;
168
169 if (h_proto == 0x8137 || h_proto == 0x80f3)
170 oui = P802_1H_OUI;
171 else
172 oui = RFC1042_OUI;
173 snap->oui[0] = oui[0];
174 snap->oui[1] = oui[1];
175 snap->oui[2] = oui[2];
176
177 *(u16 *)(data + SNAP_SIZE) = htons(h_proto);
178
179 return SNAP_SIZE + sizeof(u16);
180}
181
182int ieee80211_encrypt_fragment(
183 struct ieee80211_device *ieee,
184 struct sk_buff *frag,
185 int hdr_len)
186{
187 struct ieee80211_crypt_data* crypt = ieee->crypt[ieee->tx_keyidx];
188 int res;
189
190 if (!(crypt && crypt->ops))
191 {
192 printk("=========>%s(), crypt is null\n", __FUNCTION__);
193 return -1;
194 }
195#ifdef CONFIG_IEEE80211_CRYPT_TKIP
196 struct ieee80211_hdr *header;
197
198 if (ieee->tkip_countermeasures &&
199 crypt && crypt->ops && strcmp(crypt->ops->name, "TKIP") == 0) {
200 header = (struct ieee80211_hdr *) frag->data;
201 if (net_ratelimit()) {
202 printk(KERN_DEBUG "%s: TKIP countermeasures: dropped "
203 "TX packet to " MAC_FMT "\n",
204 ieee->dev->name, MAC_ARG(header->addr1));
205 }
206 return -1;
207 }
208#endif
209 /* To encrypt, frame format is:
210 * IV (4 bytes), clear payload (including SNAP), ICV (4 bytes) */
211
212 // PR: FIXME: Copied from hostap. Check fragmentation/MSDU/MPDU encryption.
213 /* Host-based IEEE 802.11 fragmentation for TX is not yet supported, so
214 * call both MSDU and MPDU encryption functions from here. */
215 atomic_inc(&crypt->refcnt);
216 res = 0;
217 if (crypt->ops->encrypt_msdu)
218 res = crypt->ops->encrypt_msdu(frag, hdr_len, crypt->priv);
219 if (res == 0 && crypt->ops->encrypt_mpdu)
220 res = crypt->ops->encrypt_mpdu(frag, hdr_len, crypt->priv);
221
222 atomic_dec(&crypt->refcnt);
223 if (res < 0) {
224 printk(KERN_INFO "%s: Encryption failed: len=%d.\n",
225 ieee->dev->name, frag->len);
226 ieee->ieee_stats.tx_discards++;
227 return -1;
228 }
229
230 return 0;
231}
232
233
234void ieee80211_txb_free(struct ieee80211_txb *txb) {
235 //int i;
236 if (unlikely(!txb))
237 return;
238#if 0
239 for (i = 0; i < txb->nr_frags; i++)
240 if (txb->fragments[i])
241 dev_kfree_skb_any(txb->fragments[i]);
242#endif
243 kfree(txb);
244}
245
246struct ieee80211_txb *ieee80211_alloc_txb(int nr_frags, int txb_size,
247 int gfp_mask)
248{
249 struct ieee80211_txb *txb;
250 int i;
251 txb = kmalloc(
252 sizeof(struct ieee80211_txb) + (sizeof(u8*) * nr_frags),
253 gfp_mask);
254 if (!txb)
255 return NULL;
256
257 memset(txb, 0, sizeof(struct ieee80211_txb));
258 txb->nr_frags = nr_frags;
259 txb->frag_size = txb_size;
260
261 for (i = 0; i < nr_frags; i++) {
262 txb->fragments[i] = dev_alloc_skb(txb_size);
263 if (unlikely(!txb->fragments[i])) {
264 i--;
265 break;
266 }
267 memset(txb->fragments[i]->cb, 0, sizeof(txb->fragments[i]->cb));
268 }
269 if (unlikely(i != nr_frags)) {
270 while (i >= 0)
271 dev_kfree_skb_any(txb->fragments[i--]);
272 kfree(txb);
273 return NULL;
274 }
275 return txb;
276}
277
278// Classify the to-be send data packet
279// Need to acquire the sent queue index.
280static int
281ieee80211_classify(struct sk_buff *skb, struct ieee80211_network *network)
282{
283 struct ethhdr *eth;
284 struct iphdr *ip;
285 eth = (struct ethhdr *)skb->data;
286 if (eth->h_proto != htons(ETH_P_IP))
287 return 0;
288
289// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
290#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
291 ip = ip_hdr(skb);
292#else
293 ip = (struct iphdr*)(skb->data + sizeof(struct ether_header));
294#endif
295 switch (ip->tos & 0xfc) {
296 case 0x20:
297 return 2;
298 case 0x40:
299 return 1;
300 case 0x60:
301 return 3;
302 case 0x80:
303 return 4;
304 case 0xa0:
305 return 5;
306 case 0xc0:
307 return 6;
308 case 0xe0:
309 return 7;
310 default:
311 return 0;
312 }
313}
314
315#define SN_LESS(a, b) (((a-b)&0x800)!=0)
316void ieee80211_tx_query_agg_cap(struct ieee80211_device* ieee, struct sk_buff* skb, cb_desc* tcb_desc)
317{
318 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
319 PTX_TS_RECORD pTxTs = NULL;
320 struct ieee80211_hdr_1addr* hdr = (struct ieee80211_hdr_1addr*)skb->data;
321
322 if (!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT)
323 return;
324 if (!IsQoSDataFrame(skb->data))
325 return;
326
327 if (is_multicast_ether_addr(hdr->addr1) || is_broadcast_ether_addr(hdr->addr1))
328 return;
329 //check packet and mode later
330#ifdef TO_DO_LIST
331 if(pTcb->PacketLength >= 4096)
332 return;
333 // For RTL819X, if pairwisekey = wep/tkip, we don't aggrregation.
334 if(!Adapter->HalFunc.GetNmodeSupportBySecCfgHandler(Adapter))
335 return;
336#endif
337
338 if(pHTInfo->IOTAction & HT_IOT_ACT_TX_NO_AGGREGATION)
339 return;
340
341#if 1
342 if(!ieee->GetNmodeSupportBySecCfg(ieee->dev))
343 {
344 return;
345 }
346#endif
347 if(pHTInfo->bCurrentAMPDUEnable)
348 {
349 if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTxTs), hdr->addr1, skb->priority, TX_DIR, true))
350 {
351 printk("===>can't get TS\n");
352 return;
353 }
354 if (pTxTs->TxAdmittedBARecord.bValid == false)
355 {
356 //as some AP will refuse our action frame until key handshake has been finished. WB
357 if (ieee->wpa_ie_len && (ieee->pairwise_key_type == KEY_TYPE_NA))
358 ;
359 else
360 TsStartAddBaProcess(ieee, pTxTs);
361 goto FORCED_AGG_SETTING;
362 }
363 else if (pTxTs->bUsingBa == false)
364 {
365 if (SN_LESS(pTxTs->TxAdmittedBARecord.BaStartSeqCtrl.field.SeqNum, (pTxTs->TxCurSeq+1)%4096))
366 pTxTs->bUsingBa = true;
367 else
368 goto FORCED_AGG_SETTING;
369 }
370
371 if (ieee->iw_mode == IW_MODE_INFRA)
372 {
373 tcb_desc->bAMPDUEnable = true;
374 tcb_desc->ampdu_factor = pHTInfo->CurrentAMPDUFactor;
375 tcb_desc->ampdu_density = pHTInfo->CurrentMPDUDensity;
376 }
377 }
378FORCED_AGG_SETTING:
379 switch(pHTInfo->ForcedAMPDUMode )
380 {
381 case HT_AGG_AUTO:
382 break;
383
384 case HT_AGG_FORCE_ENABLE:
385 tcb_desc->bAMPDUEnable = true;
386 tcb_desc->ampdu_density = pHTInfo->ForcedMPDUDensity;
387 tcb_desc->ampdu_factor = pHTInfo->ForcedAMPDUFactor;
388 break;
389
390 case HT_AGG_FORCE_DISABLE:
391 tcb_desc->bAMPDUEnable = false;
392 tcb_desc->ampdu_density = 0;
393 tcb_desc->ampdu_factor = 0;
394 break;
395
396 }
397 return;
398}
399
400extern void ieee80211_qurey_ShortPreambleMode(struct ieee80211_device* ieee, cb_desc* tcb_desc)
401{
402 tcb_desc->bUseShortPreamble = false;
403 if (tcb_desc->data_rate == 2)
404 {//// 1M can only use Long Preamble. 11B spec
405 return;
406 }
407 else if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
408 {
409 tcb_desc->bUseShortPreamble = true;
410 }
411 return;
412}
413extern void
414ieee80211_query_HTCapShortGI(struct ieee80211_device *ieee, cb_desc *tcb_desc)
415{
416 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
417
418 tcb_desc->bUseShortGI = false;
419
420 if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT)
421 return;
422
423 if(pHTInfo->bForcedShortGI)
424 {
425 tcb_desc->bUseShortGI = true;
426 return;
427 }
428
429 if((pHTInfo->bCurBW40MHz==true) && pHTInfo->bCurShortGI40MHz)
430 tcb_desc->bUseShortGI = true;
431 else if((pHTInfo->bCurBW40MHz==false) && pHTInfo->bCurShortGI20MHz)
432 tcb_desc->bUseShortGI = true;
433}
434
435void ieee80211_query_BandwidthMode(struct ieee80211_device* ieee, cb_desc *tcb_desc)
436{
437 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
438
439 tcb_desc->bPacketBW = false;
440
441 if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT)
442 return;
443
444 if(tcb_desc->bMulticast || tcb_desc->bBroadcast)
445 return;
446
447 if((tcb_desc->data_rate & 0x80)==0) // If using legacy rate, it shall use 20MHz channel.
448 return;
449 //BandWidthAutoSwitch is for auto switch to 20 or 40 in long distance
450 if(pHTInfo->bCurBW40MHz && pHTInfo->bCurTxBW40MHz && !ieee->bandwidth_auto_switch.bforced_tx20Mhz)
451 tcb_desc->bPacketBW = true;
452 return;
453}
454
455void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_desc, struct sk_buff* skb)
456{
457 // Common Settings
458 tcb_desc->bRTSSTBC = false;
459 tcb_desc->bRTSUseShortGI = false; // Since protection frames are always sent by legacy rate, ShortGI will never be used.
460 tcb_desc->bCTSEnable = false; // Most of protection using RTS/CTS
461 tcb_desc->RTSSC = 0; // 20MHz: Don't care; 40MHz: Duplicate.
462 tcb_desc->bRTSBW = false; // RTS frame bandwidth is always 20MHz
463
464 if(tcb_desc->bBroadcast || tcb_desc->bMulticast)//only unicast frame will use rts/cts
465 return;
466
467 if (is_broadcast_ether_addr(skb->data+16)) //check addr3 as infrastructure add3 is DA.
468 return;
469
470 if (ieee->mode < IEEE_N_24G) //b, g mode
471 {
472 // (1) RTS_Threshold is compared to the MPDU, not MSDU.
473 // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame.
474 // Other fragments are protected by previous fragment.
475 // So we only need to check the length of first fragment.
476 if (skb->len > ieee->rts)
477 {
478 tcb_desc->bRTSEnable = true;
479 tcb_desc->rts_rate = MGN_24M;
480 }
481 else if (ieee->current_network.buseprotection)
482 {
483 // Use CTS-to-SELF in protection mode.
484 tcb_desc->bRTSEnable = true;
485 tcb_desc->bCTSEnable = true;
486 tcb_desc->rts_rate = MGN_24M;
487 }
488 //otherwise return;
489 return;
490 }
491 else
492 {// 11n High throughput case.
493 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
494 while (true)
495 {
496 //check IOT action
497 if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF)
498 {
499 tcb_desc->bCTSEnable = true;
500 tcb_desc->rts_rate = MGN_24M;
501#if defined(RTL8192SE) || defined(RTL8192SU)
502 tcb_desc->bRTSEnable = false;
503#else
504 tcb_desc->bRTSEnable = true;
505#endif
506 break;
507 }
508 else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE))
509 {
510 tcb_desc->bRTSEnable = true;
511 tcb_desc->rts_rate = MGN_24M;
512 break;
513 }
514 //check ERP protection
515 if (ieee->current_network.buseprotection)
516 {// CTS-to-SELF
517 tcb_desc->bRTSEnable = true;
518 tcb_desc->bCTSEnable = true;
519 tcb_desc->rts_rate = MGN_24M;
520 break;
521 }
522 //check HT op mode
523 if(pHTInfo->bCurrentHTSupport && pHTInfo->bEnableHT)
524 {
525 u8 HTOpMode = pHTInfo->CurrentOpMode;
526 if((pHTInfo->bCurBW40MHz && (HTOpMode == 2 || HTOpMode == 3)) ||
527 (!pHTInfo->bCurBW40MHz && HTOpMode == 3) )
528 {
529 tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps.
530 tcb_desc->bRTSEnable = true;
531 break;
532 }
533 }
534 //check rts
535 if (skb->len > ieee->rts)
536 {
537 tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps.
538 tcb_desc->bRTSEnable = true;
539 break;
540 }
541 //to do list: check MIMO power save condition.
542 //check AMPDU aggregation for TXOP
543 if(tcb_desc->bAMPDUEnable)
544 {
545 tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps.
546 // According to 8190 design, firmware sends CF-End only if RTS/CTS is enabled. However, it degrads
547 // throughput around 10M, so we disable of this mechanism. 2007.08.03 by Emily
548 tcb_desc->bRTSEnable = false;
549 break;
550 }
551 // Totally no protection case!!
552 goto NO_PROTECTION;
553 }
554 }
555 // For test , CTS replace with RTS
556 if( 0 )
557 {
558 tcb_desc->bCTSEnable = true;
559 tcb_desc->rts_rate = MGN_24M;
560 tcb_desc->bRTSEnable = true;
561 }
562 if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
563 tcb_desc->bUseShortPreamble = true;
564 if (ieee->mode == IW_MODE_MASTER)
565 goto NO_PROTECTION;
566 return;
567NO_PROTECTION:
568 tcb_desc->bRTSEnable = false;
569 tcb_desc->bCTSEnable = false;
570 tcb_desc->rts_rate = 0;
571 tcb_desc->RTSSC = 0;
572 tcb_desc->bRTSBW = false;
573}
574
575
576void ieee80211_txrate_selectmode(struct ieee80211_device* ieee, cb_desc* tcb_desc)
577{
578#ifdef TO_DO_LIST
579 if(!IsDataFrame(pFrame))
580 {
581 pTcb->bTxDisableRateFallBack = TRUE;
582 pTcb->bTxUseDriverAssingedRate = TRUE;
583 pTcb->RATRIndex = 7;
584 return;
585 }
586
587 if(pMgntInfo->ForcedDataRate!= 0)
588 {
589 pTcb->bTxDisableRateFallBack = TRUE;
590 pTcb->bTxUseDriverAssingedRate = TRUE;
591 return;
592 }
593#endif
594 if(ieee->bTxDisableRateFallBack)
595 tcb_desc->bTxDisableRateFallBack = true;
596
597 if(ieee->bTxUseDriverAssingedRate)
598 tcb_desc->bTxUseDriverAssingedRate = true;
599 if(!tcb_desc->bTxDisableRateFallBack || !tcb_desc->bTxUseDriverAssingedRate)
600 {
601 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
602 tcb_desc->RATRIndex = 0;
603 }
604}
605
606void ieee80211_query_seqnum(struct ieee80211_device*ieee, struct sk_buff* skb, u8* dst)
607{
608 if (is_multicast_ether_addr(dst) || is_broadcast_ether_addr(dst))
609 return;
610 if (IsQoSDataFrame(skb->data)) //we deal qos data only
611 {
612 PTX_TS_RECORD pTS = NULL;
613 if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTS), dst, skb->priority, TX_DIR, true))
614 {
615 return;
616 }
617 pTS->TxCurSeq = (pTS->TxCurSeq+1)%4096;
618 }
619}
620
621int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
622{
623#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
624 struct ieee80211_device *ieee = netdev_priv(dev);
625#else
626 struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv;
627#endif
628 struct ieee80211_txb *txb = NULL;
629 struct ieee80211_hdr_3addrqos *frag_hdr;
630 int i, bytes_per_frag, nr_frags, bytes_last_frag, frag_size;
631 unsigned long flags;
632 struct net_device_stats *stats = &ieee->stats;
633 int ether_type = 0, encrypt;
634 int bytes, fc, qos_ctl = 0, hdr_len;
635 struct sk_buff *skb_frag;
636 struct ieee80211_hdr_3addrqos header = { /* Ensure zero initialized */
637 .duration_id = 0,
638 .seq_ctl = 0,
639 .qos_ctl = 0
640 };
641 u8 dest[ETH_ALEN], src[ETH_ALEN];
642 int qos_actived = ieee->current_network.qos_data.active;
643
644 struct ieee80211_crypt_data* crypt;
645
646 cb_desc *tcb_desc;
647
648 spin_lock_irqsave(&ieee->lock, flags);
649
650 /* If there is no driver handler to take the TXB, dont' bother
651 * creating it... */
652 if ((!ieee->hard_start_xmit && !(ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE))||
653 ((!ieee->softmac_data_hard_start_xmit && (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) {
654 printk(KERN_WARNING "%s: No xmit handler.\n",
655 ieee->dev->name);
656 goto success;
657 }
658
659
660 if(likely(ieee->raw_tx == 0)){
661 if (unlikely(skb->len < SNAP_SIZE + sizeof(u16))) {
662 printk(KERN_WARNING "%s: skb too small (%d).\n",
663 ieee->dev->name, skb->len);
664 goto success;
665 }
666
667 memset(skb->cb, 0, sizeof(skb->cb));
668 ether_type = ntohs(((struct ethhdr *)skb->data)->h_proto);
669
670 crypt = ieee->crypt[ieee->tx_keyidx];
671
672 encrypt = !(ether_type == ETH_P_PAE && ieee->ieee802_1x) &&
673 ieee->host_encrypt && crypt && crypt->ops;
674
675 if (!encrypt && ieee->ieee802_1x &&
676 ieee->drop_unencrypted && ether_type != ETH_P_PAE) {
677 stats->tx_dropped++;
678 goto success;
679 }
680 #ifdef CONFIG_IEEE80211_DEBUG
681 if (crypt && !encrypt && ether_type == ETH_P_PAE) {
682 struct eapol *eap = (struct eapol *)(skb->data +
683 sizeof(struct ethhdr) - SNAP_SIZE - sizeof(u16));
684 IEEE80211_DEBUG_EAP("TX: IEEE 802.11 EAPOL frame: %s\n",
685 eap_get_type(eap->type));
686 }
687 #endif
688
689 /* Save source and destination addresses */
690 memcpy(&dest, skb->data, ETH_ALEN);
691 memcpy(&src, skb->data+ETH_ALEN, ETH_ALEN);
692
693 /* Advance the SKB to the start of the payload */
694 skb_pull(skb, sizeof(struct ethhdr));
695
696 /* Determine total amount of storage required for TXB packets */
697 bytes = skb->len + SNAP_SIZE + sizeof(u16);
698
699 if (encrypt)
700 fc = IEEE80211_FTYPE_DATA | IEEE80211_FCTL_WEP;
701 else
702
703 fc = IEEE80211_FTYPE_DATA;
704
705 //if(ieee->current_network.QoS_Enable)
706 if(qos_actived)
707 fc |= IEEE80211_STYPE_QOS_DATA;
708 else
709 fc |= IEEE80211_STYPE_DATA;
710
711 if (ieee->iw_mode == IW_MODE_INFRA) {
712 fc |= IEEE80211_FCTL_TODS;
713 /* To DS: Addr1 = BSSID, Addr2 = SA,
714 Addr3 = DA */
715 memcpy(&header.addr1, ieee->current_network.bssid, ETH_ALEN);
716 memcpy(&header.addr2, &src, ETH_ALEN);
717 memcpy(&header.addr3, &dest, ETH_ALEN);
718 } else if (ieee->iw_mode == IW_MODE_ADHOC) {
719 /* not From/To DS: Addr1 = DA, Addr2 = SA,
720 Addr3 = BSSID */
721 memcpy(&header.addr1, dest, ETH_ALEN);
722 memcpy(&header.addr2, src, ETH_ALEN);
723 memcpy(&header.addr3, ieee->current_network.bssid, ETH_ALEN);
724 }
725
726 header.frame_ctl = cpu_to_le16(fc);
727
728 /* Determine fragmentation size based on destination (multicast
729 * and broadcast are not fragmented) */
730 if (is_multicast_ether_addr(header.addr1) ||
731 is_broadcast_ether_addr(header.addr1)) {
732 frag_size = MAX_FRAG_THRESHOLD;
733 qos_ctl |= QOS_CTL_NOTCONTAIN_ACK;
734 }
735 else {
736 frag_size = ieee->fts;//default:392
737 qos_ctl = 0;
738 }
739
740 //if (ieee->current_network.QoS_Enable)
741 if(qos_actived)
742 {
743 hdr_len = IEEE80211_3ADDR_LEN + 2;
744
745 skb->priority = ieee80211_classify(skb, &ieee->current_network);
746 qos_ctl |= skb->priority; //set in the ieee80211_classify
747 header.qos_ctl = cpu_to_le16(qos_ctl & IEEE80211_QOS_TID);
748 } else {
749 hdr_len = IEEE80211_3ADDR_LEN;
750 }
751 /* Determine amount of payload per fragment. Regardless of if
752 * this stack is providing the full 802.11 header, one will
753 * eventually be affixed to this fragment -- so we must account for
754 * it when determining the amount of payload space. */
755 bytes_per_frag = frag_size - hdr_len;
756 if (ieee->config &
757 (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS))
758 bytes_per_frag -= IEEE80211_FCS_LEN;
759
760 /* Each fragment may need to have room for encryptiong pre/postfix */
761 if (encrypt)
762 bytes_per_frag -= crypt->ops->extra_prefix_len +
763 crypt->ops->extra_postfix_len;
764
765 /* Number of fragments is the total bytes_per_frag /
766 * payload_per_fragment */
767 nr_frags = bytes / bytes_per_frag;
768 bytes_last_frag = bytes % bytes_per_frag;
769 if (bytes_last_frag)
770 nr_frags++;
771 else
772 bytes_last_frag = bytes_per_frag;
773
774 /* When we allocate the TXB we allocate enough space for the reserve
775 * and full fragment bytes (bytes_per_frag doesn't include prefix,
776 * postfix, header, FCS, etc.) */
777 txb = ieee80211_alloc_txb(nr_frags, frag_size + ieee->tx_headroom, GFP_ATOMIC);
778 if (unlikely(!txb)) {
779 printk(KERN_WARNING "%s: Could not allocate TXB\n",
780 ieee->dev->name);
781 goto failed;
782 }
783 txb->encrypted = encrypt;
784 txb->payload_size = bytes;
785
786 //if (ieee->current_network.QoS_Enable)
787 if(qos_actived)
788 {
789 txb->queue_index = UP2AC(skb->priority);
790 } else {
791 txb->queue_index = WME_AC_BK;;
792 }
793
794
795
796 for (i = 0; i < nr_frags; i++) {
797 skb_frag = txb->fragments[i];
798 tcb_desc = (cb_desc *)(skb_frag->cb + MAX_DEV_ADDR_SIZE);
799 if(qos_actived){
800 skb_frag->priority = skb->priority;//UP2AC(skb->priority);
801 tcb_desc->queue_index = UP2AC(skb->priority);
802 } else {
803 skb_frag->priority = WME_AC_BK;
804 tcb_desc->queue_index = WME_AC_BK;
805 }
806 skb_reserve(skb_frag, ieee->tx_headroom);
807
808 if (encrypt){
809 if (ieee->hwsec_active)
810 tcb_desc->bHwSec = 1;
811 else
812 tcb_desc->bHwSec = 0;
813 skb_reserve(skb_frag, crypt->ops->extra_prefix_len);
814 }
815 else
816 {
817 tcb_desc->bHwSec = 0;
818 }
819 frag_hdr = (struct ieee80211_hdr_3addrqos *)skb_put(skb_frag, hdr_len);
820 memcpy(frag_hdr, &header, hdr_len);
821
822 /* If this is not the last fragment, then add the MOREFRAGS
823 * bit to the frame control */
824 if (i != nr_frags - 1) {
825 frag_hdr->frame_ctl = cpu_to_le16(
826 fc | IEEE80211_FCTL_MOREFRAGS);
827 bytes = bytes_per_frag;
828
829 } else {
830 /* The last fragment takes the remaining length */
831 bytes = bytes_last_frag;
832 }
833 //if(ieee->current_network.QoS_Enable)
834 if(qos_actived)
835 {
836 // add 1 only indicate to corresponding seq number control 2006/7/12
837 frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[UP2AC(skb->priority)+1]<<4 | i);
838 } else {
839 frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4 | i);
840 }
841
842 /* Put a SNAP header on the first fragment */
843 if (i == 0) {
844 ieee80211_put_snap(
845 skb_put(skb_frag, SNAP_SIZE + sizeof(u16)),
846 ether_type);
847 bytes -= SNAP_SIZE + sizeof(u16);
848 }
849
850 memcpy(skb_put(skb_frag, bytes), skb->data, bytes);
851
852 /* Advance the SKB... */
853 skb_pull(skb, bytes);
854
855 /* Encryption routine will move the header forward in order
856 * to insert the IV between the header and the payload */
857 if (encrypt)
858 ieee80211_encrypt_fragment(ieee, skb_frag, hdr_len);
859 if (ieee->config &
860 (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS))
861 skb_put(skb_frag, 4);
862 }
863
864 if(qos_actived)
865 {
866 if (ieee->seq_ctrl[UP2AC(skb->priority) + 1] == 0xFFF)
867 ieee->seq_ctrl[UP2AC(skb->priority) + 1] = 0;
868 else
869 ieee->seq_ctrl[UP2AC(skb->priority) + 1]++;
870 } else {
871 if (ieee->seq_ctrl[0] == 0xFFF)
872 ieee->seq_ctrl[0] = 0;
873 else
874 ieee->seq_ctrl[0]++;
875 }
876 }else{
877 if (unlikely(skb->len < sizeof(struct ieee80211_hdr_3addr))) {
878 printk(KERN_WARNING "%s: skb too small (%d).\n",
879 ieee->dev->name, skb->len);
880 goto success;
881 }
882
883 txb = ieee80211_alloc_txb(1, skb->len, GFP_ATOMIC);
884 if(!txb){
885 printk(KERN_WARNING "%s: Could not allocate TXB\n",
886 ieee->dev->name);
887 goto failed;
888 }
889
890 txb->encrypted = 0;
891 txb->payload_size = skb->len;
892 memcpy(skb_put(txb->fragments[0],skb->len), skb->data, skb->len);
893 }
894
895 success:
896//WB add to fill data tcb_desc here. only first fragment is considered, need to change, and you may remove to other place.
897 if (txb)
898 {
899#if 1
900 cb_desc *tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE);
901 tcb_desc->bTxEnableFwCalcDur = 1;
902 if (is_multicast_ether_addr(header.addr1))
903 tcb_desc->bMulticast = 1;
904 if (is_broadcast_ether_addr(header.addr1))
905 tcb_desc->bBroadcast = 1;
906 ieee80211_txrate_selectmode(ieee, tcb_desc);
907 if ( tcb_desc->bMulticast || tcb_desc->bBroadcast)
908 tcb_desc->data_rate = ieee->basic_rate;
909 else
910 //tcb_desc->data_rate = CURRENT_RATE(ieee->current_network.mode, ieee->rate, ieee->HTCurrentOperaRate);
911 tcb_desc->data_rate = CURRENT_RATE(ieee->mode, ieee->rate, ieee->HTCurrentOperaRate);
912 ieee80211_qurey_ShortPreambleMode(ieee, tcb_desc);
913 ieee80211_tx_query_agg_cap(ieee, txb->fragments[0], tcb_desc);
914 ieee80211_query_HTCapShortGI(ieee, tcb_desc);
915 ieee80211_query_BandwidthMode(ieee, tcb_desc);
916 ieee80211_query_protectionmode(ieee, tcb_desc, txb->fragments[0]);
917 ieee80211_query_seqnum(ieee, txb->fragments[0], header.addr1);
918// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, txb->fragments[0]->data, txb->fragments[0]->len);
919 //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, tcb_desc, sizeof(cb_desc));
920#endif
921 }
922 spin_unlock_irqrestore(&ieee->lock, flags);
923 dev_kfree_skb_any(skb);
924 if (txb) {
925 if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE){
926 ieee80211_softmac_xmit(txb, ieee);
927 }else{
928 if ((*ieee->hard_start_xmit)(txb, dev) == 0) {
929 stats->tx_packets++;
930 stats->tx_bytes += txb->payload_size;
931 return 0;
932 }
933 ieee80211_txb_free(txb);
934 }
935 }
936
937 return 0;
938
939 failed:
940 spin_unlock_irqrestore(&ieee->lock, flags);
941 netif_stop_queue(dev);
942 stats->tx_errors++;
943 return 1;
944
945}
946
947EXPORT_SYMBOL(ieee80211_txb_free);
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c
new file mode 100644
index 00000000000..118dfe1c977
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c
@@ -0,0 +1,1032 @@
1/******************************************************************************
2
3 Copyright(c) 2004 Intel Corporation. All rights reserved.
4
5 Portions of this file are based on the WEP enablement code provided by the
6 Host AP project hostap-drivers v0.1.3
7 Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
8 <jkmaline@cc.hut.fi>
9 Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of version 2 of the GNU General Public License as
13 published by the Free Software Foundation.
14
15 This program is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 more details.
19
20 You should have received a copy of the GNU General Public License along with
21 this program; if not, write to the Free Software Foundation, Inc., 59
22 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23
24 The full GNU General Public License is included in this distribution in the
25 file called LICENSE.
26
27 Contact Information:
28 James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31******************************************************************************/
32#include <linux/wireless.h>
33#include <linux/version.h>
34#include <linux/kmod.h>
35#include <linux/module.h>
36
37#include "ieee80211.h"
38#if 0
39static const char *ieee80211_modes[] = {
40 "?", "a", "b", "ab", "g", "ag", "bg", "abg"
41};
42#endif
43struct modes_unit {
44 char *mode_string;
45 int mode_size;
46};
47struct modes_unit ieee80211_modes[] = {
48 {"a",1},
49 {"b",1},
50 {"g",1},
51 {"?",1},
52 {"N-24G",5},
53 {"N-5G",4},
54};
55
56#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
57static inline char *
58iwe_stream_add_event_rsl(char * stream, /* Stream of events */
59 char * ends, /* End of stream */
60 struct iw_event *iwe, /* Payload */
61 int event_len) /* Real size of payload */
62{
63 /* Check if it's possible */
64 if((stream + event_len) < ends) {
65 iwe->len = event_len;
66 ndelay(1); //new
67 memcpy(stream, (char *) iwe, event_len);
68 stream += event_len;
69 }
70 return stream;
71}
72#else
73#define iwe_stream_add_event_rsl iwe_stream_add_event
74#endif
75
76#define MAX_CUSTOM_LEN 64
77static inline char *rtl819x_translate_scan(struct ieee80211_device *ieee,
78 char *start, char *stop,
79 struct ieee80211_network *network,
80 struct iw_request_info *info)
81{
82 char custom[MAX_CUSTOM_LEN];
83 char proto_name[IFNAMSIZ];
84 char *pname = proto_name;
85 char *p;
86 struct iw_event iwe;
87 int i, j;
88 u16 max_rate, rate;
89 static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33};
90
91 /* First entry *MUST* be the AP MAC address */
92 iwe.cmd = SIOCGIWAP;
93 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
94 memcpy(iwe.u.ap_addr.sa_data, network->bssid, ETH_ALEN);
95#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
96 start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_ADDR_LEN);
97#else
98 start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_ADDR_LEN);
99#endif
100 /* Remaining entries will be displayed in the order we provide them */
101
102 /* Add the ESSID */
103 iwe.cmd = SIOCGIWESSID;
104 iwe.u.data.flags = 1;
105// if (network->flags & NETWORK_EMPTY_ESSID) {
106 if (network->ssid_len == 0) {
107 iwe.u.data.length = sizeof("<hidden>");
108#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
109 start = iwe_stream_add_point(info, start, stop, &iwe, "<hidden>");
110#else
111 start = iwe_stream_add_point(start, stop, &iwe, "<hidden>");
112#endif
113 } else {
114 iwe.u.data.length = min(network->ssid_len, (u8)32);
115#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
116 start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid);
117#else
118 start = iwe_stream_add_point(start, stop, &iwe, network->ssid);
119#endif
120 }
121 /* Add the protocol name */
122 iwe.cmd = SIOCGIWNAME;
123 for(i=0; i<(sizeof(ieee80211_modes)/sizeof(ieee80211_modes[0])); i++) {
124 if(network->mode&(1<<i)) {
125 sprintf(pname,ieee80211_modes[i].mode_string,ieee80211_modes[i].mode_size);
126 pname +=ieee80211_modes[i].mode_size;
127 }
128 }
129 *pname = '\0';
130 snprintf(iwe.u.name, IFNAMSIZ, "IEEE802.11%s", proto_name);
131#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
132 start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_CHAR_LEN);
133#else
134 start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_CHAR_LEN);
135#endif
136 /* Add mode */
137 iwe.cmd = SIOCGIWMODE;
138 if (network->capability &
139 (WLAN_CAPABILITY_BSS | WLAN_CAPABILITY_IBSS)) {
140 if (network->capability & WLAN_CAPABILITY_BSS)
141 iwe.u.mode = IW_MODE_MASTER;
142 else
143 iwe.u.mode = IW_MODE_ADHOC;
144#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
145 start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_UINT_LEN);
146#else
147 start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_UINT_LEN);
148#endif
149 }
150
151 /* Add frequency/channel */
152 iwe.cmd = SIOCGIWFREQ;
153/* iwe.u.freq.m = ieee80211_frequency(network->channel, network->mode);
154 iwe.u.freq.e = 3; */
155 iwe.u.freq.m = network->channel;
156 iwe.u.freq.e = 0;
157 iwe.u.freq.i = 0;
158#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
159 start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_FREQ_LEN);
160#else
161 start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_FREQ_LEN);
162#endif
163 /* Add encryption capability */
164 iwe.cmd = SIOCGIWENCODE;
165 if (network->capability & WLAN_CAPABILITY_PRIVACY)
166 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
167 else
168 iwe.u.data.flags = IW_ENCODE_DISABLED;
169 iwe.u.data.length = 0;
170#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
171 start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid);
172#else
173 start = iwe_stream_add_point(start, stop, &iwe, network->ssid);
174#endif
175 /* Add basic and extended rates */
176 max_rate = 0;
177 p = custom;
178 p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): ");
179 for (i = 0, j = 0; i < network->rates_len; ) {
180 if (j < network->rates_ex_len &&
181 ((network->rates_ex[j] & 0x7F) <
182 (network->rates[i] & 0x7F)))
183 rate = network->rates_ex[j++] & 0x7F;
184 else
185 rate = network->rates[i++] & 0x7F;
186 if (rate > max_rate)
187 max_rate = rate;
188 p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
189 "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
190 }
191 for (; j < network->rates_ex_len; j++) {
192 rate = network->rates_ex[j] & 0x7F;
193 p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
194 "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
195 if (rate > max_rate)
196 max_rate = rate;
197 }
198
199 if (network->mode >= IEEE_N_24G)//add N rate here;
200 {
201 PHT_CAPABILITY_ELE ht_cap = NULL;
202 bool is40M = false, isShortGI = false;
203 u8 max_mcs = 0;
204 if (!memcmp(network->bssht.bdHTCapBuf, EWC11NHTCap, 4))
205 ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[4];
206 else
207 ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[0];
208 is40M = (ht_cap->ChlWidth)?1:0;
209 isShortGI = (ht_cap->ChlWidth)?
210 ((ht_cap->ShortGI40Mhz)?1:0):
211 ((ht_cap->ShortGI20Mhz)?1:0);
212
213 max_mcs = HTGetHighestMCSRate(ieee, ht_cap->MCS, MCS_FILTER_ALL);
214 rate = MCS_DATA_RATE[is40M][isShortGI][max_mcs&0x7f];
215 if (rate > max_rate)
216 max_rate = rate;
217 }
218#if 0
219 printk("max rate:%d ===basic rate:\n", max_rate);
220 for (i=0;i<network->rates_len;i++)
221 printk(" %x", network->rates[i]);
222 printk("\n=======extend rate\n");
223 for (i=0; i<network->rates_ex_len; i++)
224 printk(" %x", network->rates_ex[i]);
225 printk("\n");
226#endif
227 iwe.cmd = SIOCGIWRATE;
228 iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
229 iwe.u.bitrate.value = max_rate * 500000;
230#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
231 start = iwe_stream_add_event_rsl(info, start, stop, &iwe,
232 IW_EV_PARAM_LEN);
233#else
234 start = iwe_stream_add_event_rsl(start, stop, &iwe,
235 IW_EV_PARAM_LEN);
236#endif
237 iwe.cmd = IWEVCUSTOM;
238 iwe.u.data.length = p - custom;
239 if (iwe.u.data.length)
240#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
241 start = iwe_stream_add_point(info, start, stop, &iwe, custom);
242#else
243 start = iwe_stream_add_point(start, stop, &iwe, custom);
244#endif
245 /* Add quality statistics */
246 /* TODO: Fix these values... */
247 iwe.cmd = IWEVQUAL;
248 iwe.u.qual.qual = network->stats.signal;
249 iwe.u.qual.level = network->stats.rssi;
250 iwe.u.qual.noise = network->stats.noise;
251 iwe.u.qual.updated = network->stats.mask & IEEE80211_STATMASK_WEMASK;
252 if (!(network->stats.mask & IEEE80211_STATMASK_RSSI))
253 iwe.u.qual.updated |= IW_QUAL_LEVEL_INVALID;
254 if (!(network->stats.mask & IEEE80211_STATMASK_NOISE))
255 iwe.u.qual.updated |= IW_QUAL_NOISE_INVALID;
256 if (!(network->stats.mask & IEEE80211_STATMASK_SIGNAL))
257 iwe.u.qual.updated |= IW_QUAL_QUAL_INVALID;
258 iwe.u.qual.updated = 7;
259#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
260 start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_QUAL_LEN);
261#else
262 start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_QUAL_LEN);
263#endif
264 iwe.cmd = IWEVCUSTOM;
265 p = custom;
266
267 iwe.u.data.length = p - custom;
268 if (iwe.u.data.length)
269#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
270 start = iwe_stream_add_point(info, start, stop, &iwe, custom);
271#else
272 start = iwe_stream_add_point(start, stop, &iwe, custom);
273#endif
274#if (WIRELESS_EXT < 18)
275 if (ieee->wpa_enabled && network->wpa_ie_len){
276 char buf[MAX_WPA_IE_LEN * 2 + 30];
277 // printk("WPA IE\n");
278 u8 *p = buf;
279 p += sprintf(p, "wpa_ie=");
280 for (i = 0; i < network->wpa_ie_len; i++) {
281 p += sprintf(p, "%02x", network->wpa_ie[i]);
282 }
283
284 memset(&iwe, 0, sizeof(iwe));
285 iwe.cmd = IWEVCUSTOM;
286 iwe.u.data.length = strlen(buf);
287#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
288 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
289#else
290 start = iwe_stream_add_point(start, stop, &iwe, buf);
291#endif
292 }
293
294 if (ieee->wpa_enabled && network->rsn_ie_len){
295 char buf[MAX_WPA_IE_LEN * 2 + 30];
296
297 u8 *p = buf;
298 p += sprintf(p, "rsn_ie=");
299 for (i = 0; i < network->rsn_ie_len; i++) {
300 p += sprintf(p, "%02x", network->rsn_ie[i]);
301 }
302
303 memset(&iwe, 0, sizeof(iwe));
304 iwe.cmd = IWEVCUSTOM;
305 iwe.u.data.length = strlen(buf);
306#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
307 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
308#else
309 start = iwe_stream_add_point(start, stop, &iwe, buf);
310#endif
311 }
312#else
313 memset(&iwe, 0, sizeof(iwe));
314 if (network->wpa_ie_len)
315 {
316 char buf[MAX_WPA_IE_LEN];
317 memcpy(buf, network->wpa_ie, network->wpa_ie_len);
318 iwe.cmd = IWEVGENIE;
319 iwe.u.data.length = network->wpa_ie_len;
320#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
321 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
322#else
323 start = iwe_stream_add_point(start, stop, &iwe, buf);
324#endif
325 }
326 memset(&iwe, 0, sizeof(iwe));
327 if (network->rsn_ie_len)
328 {
329 char buf[MAX_WPA_IE_LEN];
330 memcpy(buf, network->rsn_ie, network->rsn_ie_len);
331 iwe.cmd = IWEVGENIE;
332 iwe.u.data.length = network->rsn_ie_len;
333#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
334 start = iwe_stream_add_point(info, start, stop, &iwe, buf);
335#else
336 start = iwe_stream_add_point(start, stop, &iwe, buf);
337#endif
338 }
339#endif
340
341
342 /* Add EXTRA: Age to display seconds since last beacon/probe response
343 * for given network. */
344 iwe.cmd = IWEVCUSTOM;
345 p = custom;
346 p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
347 " Last beacon: %lums ago", (jiffies - network->last_scanned) / (HZ / 100));
348 iwe.u.data.length = p - custom;
349 if (iwe.u.data.length)
350#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
351 start = iwe_stream_add_point(info, start, stop, &iwe, custom);
352#else
353 start = iwe_stream_add_point(start, stop, &iwe, custom);
354#endif
355
356 return start;
357}
358
359int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
360 struct iw_request_info *info,
361 union iwreq_data *wrqu, char *extra)
362{
363 struct ieee80211_network *network;
364 unsigned long flags;
365
366 char *ev = extra;
367// char *stop = ev + IW_SCAN_MAX_DATA;
368 char *stop = ev + wrqu->data.length;//IW_SCAN_MAX_DATA;
369 //char *stop = ev + IW_SCAN_MAX_DATA;
370 int i = 0;
371 int err = 0;
372 IEEE80211_DEBUG_WX("Getting scan\n");
373 down(&ieee->wx_sem);
374 spin_lock_irqsave(&ieee->lock, flags);
375
376 list_for_each_entry(network, &ieee->network_list, list) {
377 i++;
378 if((stop-ev)<200)
379 {
380 err = -E2BIG;
381 break;
382 }
383 if (ieee->scan_age == 0 ||
384 time_after(network->last_scanned + ieee->scan_age, jiffies))
385 ev = rtl819x_translate_scan(ieee, ev, stop, network, info);
386 else
387 IEEE80211_DEBUG_SCAN(
388 "Not showing network '%s ("
389 MAC_FMT ")' due to age (%lums).\n",
390 escape_essid(network->ssid,
391 network->ssid_len),
392 MAC_ARG(network->bssid),
393 (jiffies - network->last_scanned) / (HZ / 100));
394 }
395
396 spin_unlock_irqrestore(&ieee->lock, flags);
397 up(&ieee->wx_sem);
398 wrqu->data.length = ev - extra;
399 wrqu->data.flags = 0;
400
401 IEEE80211_DEBUG_WX("exit: %d networks returned.\n", i);
402
403 return err;
404}
405
406int ieee80211_wx_set_encode(struct ieee80211_device *ieee,
407 struct iw_request_info *info,
408 union iwreq_data *wrqu, char *keybuf)
409{
410 struct iw_point *erq = &(wrqu->encoding);
411 struct net_device *dev = ieee->dev;
412 struct ieee80211_security sec = {
413 .flags = 0
414 };
415 int i, key, key_provided, len;
416 struct ieee80211_crypt_data **crypt;
417
418 IEEE80211_DEBUG_WX("SET_ENCODE\n");
419
420 key = erq->flags & IW_ENCODE_INDEX;
421 if (key) {
422 if (key > WEP_KEYS)
423 return -EINVAL;
424 key--;
425 key_provided = 1;
426 } else {
427 key_provided = 0;
428 key = ieee->tx_keyidx;
429 }
430
431 IEEE80211_DEBUG_WX("Key: %d [%s]\n", key, key_provided ?
432 "provided" : "default");
433 crypt = &ieee->crypt[key];
434
435 if (erq->flags & IW_ENCODE_DISABLED) {
436 if (key_provided && *crypt) {
437 IEEE80211_DEBUG_WX("Disabling encryption on key %d.\n",
438 key);
439 ieee80211_crypt_delayed_deinit(ieee, crypt);
440 } else
441 IEEE80211_DEBUG_WX("Disabling encryption.\n");
442
443 /* Check all the keys to see if any are still configured,
444 * and if no key index was provided, de-init them all */
445 for (i = 0; i < WEP_KEYS; i++) {
446 if (ieee->crypt[i] != NULL) {
447 if (key_provided)
448 break;
449 ieee80211_crypt_delayed_deinit(
450 ieee, &ieee->crypt[i]);
451 }
452 }
453
454 if (i == WEP_KEYS) {
455 sec.enabled = 0;
456 sec.level = SEC_LEVEL_0;
457 sec.flags |= SEC_ENABLED | SEC_LEVEL;
458 }
459
460 goto done;
461 }
462
463
464
465 sec.enabled = 1;
466 sec.flags |= SEC_ENABLED;
467
468 if (*crypt != NULL && (*crypt)->ops != NULL &&
469 strcmp((*crypt)->ops->name, "WEP") != 0) {
470 /* changing to use WEP; deinit previously used algorithm
471 * on this key */
472 ieee80211_crypt_delayed_deinit(ieee, crypt);
473 }
474
475 if (*crypt == NULL) {
476 struct ieee80211_crypt_data *new_crypt;
477
478 /* take WEP into use */
479 new_crypt = kmalloc(sizeof(struct ieee80211_crypt_data),
480 GFP_KERNEL);
481 if (new_crypt == NULL)
482 return -ENOMEM;
483 memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data));
484 new_crypt->ops = ieee80211_get_crypto_ops("WEP");
485 if (!new_crypt->ops) {
486 request_module("ieee80211_crypt_wep");
487 new_crypt->ops = ieee80211_get_crypto_ops("WEP");
488 }
489#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
490 if (new_crypt->ops && try_module_get(new_crypt->ops->owner))
491#else
492 if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner))
493#endif
494 new_crypt->priv = new_crypt->ops->init(key);
495
496 if (!new_crypt->ops || !new_crypt->priv) {
497 kfree(new_crypt);
498 new_crypt = NULL;
499
500 printk(KERN_WARNING "%s: could not initialize WEP: "
501 "load module ieee80211_crypt_wep\n",
502 dev->name);
503 return -EOPNOTSUPP;
504 }
505 *crypt = new_crypt;
506 }
507
508 /* If a new key was provided, set it up */
509 if (erq->length > 0) {
510 len = erq->length <= 5 ? 5 : 13;
511 memcpy(sec.keys[key], keybuf, erq->length);
512 if (len > erq->length)
513 memset(sec.keys[key] + erq->length, 0,
514 len - erq->length);
515 IEEE80211_DEBUG_WX("Setting key %d to '%s' (%d:%d bytes)\n",
516 key, escape_essid(sec.keys[key], len),
517 erq->length, len);
518 sec.key_sizes[key] = len;
519 (*crypt)->ops->set_key(sec.keys[key], len, NULL,
520 (*crypt)->priv);
521 sec.flags |= (1 << key);
522 /* This ensures a key will be activated if no key is
523 * explicitely set */
524 if (key == sec.active_key)
525 sec.flags |= SEC_ACTIVE_KEY;
526 ieee->tx_keyidx = key;
527
528 } else {
529 len = (*crypt)->ops->get_key(sec.keys[key], WEP_KEY_LEN,
530 NULL, (*crypt)->priv);
531 if (len == 0) {
532 /* Set a default key of all 0 */
533 printk("Setting key %d to all zero.\n",
534 key);
535
536 IEEE80211_DEBUG_WX("Setting key %d to all zero.\n",
537 key);
538 memset(sec.keys[key], 0, 13);
539 (*crypt)->ops->set_key(sec.keys[key], 13, NULL,
540 (*crypt)->priv);
541 sec.key_sizes[key] = 13;
542 sec.flags |= (1 << key);
543 }
544
545 /* No key data - just set the default TX key index */
546 if (key_provided) {
547 IEEE80211_DEBUG_WX(
548 "Setting key %d to default Tx key.\n", key);
549 ieee->tx_keyidx = key;
550 sec.active_key = key;
551 sec.flags |= SEC_ACTIVE_KEY;
552 }
553 }
554
555 done:
556 ieee->open_wep = !(erq->flags & IW_ENCODE_RESTRICTED);
557 ieee->auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY;
558 sec.auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY;
559 sec.flags |= SEC_AUTH_MODE;
560 IEEE80211_DEBUG_WX("Auth: %s\n", sec.auth_mode == WLAN_AUTH_OPEN ?
561 "OPEN" : "SHARED KEY");
562
563 /* For now we just support WEP, so only set that security level...
564 * TODO: When WPA is added this is one place that needs to change */
565 sec.flags |= SEC_LEVEL;
566 sec.level = SEC_LEVEL_1; /* 40 and 104 bit WEP */
567
568 if (ieee->set_security)
569 ieee->set_security(dev, &sec);
570
571 /* Do not reset port if card is in Managed mode since resetting will
572 * generate new IEEE 802.11 authentication which may end up in looping
573 * with IEEE 802.1X. If your hardware requires a reset after WEP
574 * configuration (for example... Prism2), implement the reset_port in
575 * the callbacks structures used to initialize the 802.11 stack. */
576 if (ieee->reset_on_keychange &&
577 ieee->iw_mode != IW_MODE_INFRA &&
578 ieee->reset_port && ieee->reset_port(dev)) {
579 printk(KERN_DEBUG "%s: reset_port failed\n", dev->name);
580 return -EINVAL;
581 }
582 return 0;
583}
584
585int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
586 struct iw_request_info *info,
587 union iwreq_data *wrqu, char *keybuf)
588{
589 struct iw_point *erq = &(wrqu->encoding);
590 int len, key;
591 struct ieee80211_crypt_data *crypt;
592
593 IEEE80211_DEBUG_WX("GET_ENCODE\n");
594
595 if(ieee->iw_mode == IW_MODE_MONITOR)
596 return -1;
597
598 key = erq->flags & IW_ENCODE_INDEX;
599 if (key) {
600 if (key > WEP_KEYS)
601 return -EINVAL;
602 key--;
603 } else
604 key = ieee->tx_keyidx;
605
606 crypt = ieee->crypt[key];
607 erq->flags = key + 1;
608
609 if (crypt == NULL || crypt->ops == NULL) {
610 erq->length = 0;
611 erq->flags |= IW_ENCODE_DISABLED;
612 return 0;
613 }
614#if 0
615 if (strcmp(crypt->ops->name, "WEP") != 0) {
616 /* only WEP is supported with wireless extensions, so just
617 * report that encryption is used */
618 erq->length = 0;
619 erq->flags |= IW_ENCODE_ENABLED;
620 return 0;
621 }
622#endif
623 len = crypt->ops->get_key(keybuf, SCM_KEY_LEN, NULL, crypt->priv);
624 erq->length = (len >= 0 ? len : 0);
625
626 erq->flags |= IW_ENCODE_ENABLED;
627
628 if (ieee->open_wep)
629 erq->flags |= IW_ENCODE_OPEN;
630 else
631 erq->flags |= IW_ENCODE_RESTRICTED;
632
633 return 0;
634}
635#if (WIRELESS_EXT >= 18)
636int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee,
637 struct iw_request_info *info,
638 union iwreq_data *wrqu, char *extra)
639{
640 int ret = 0;
641#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
642 struct net_device *dev = ieee->dev;
643 struct iw_point *encoding = &wrqu->encoding;
644 struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
645 int i, idx;
646 int group_key = 0;
647 const char *alg, *module;
648 struct ieee80211_crypto_ops *ops;
649 struct ieee80211_crypt_data **crypt;
650
651 struct ieee80211_security sec = {
652 .flags = 0,
653 };
654 //printk("======>encoding flag:%x,ext flag:%x, ext alg:%d\n", encoding->flags,ext->ext_flags, ext->alg);
655 idx = encoding->flags & IW_ENCODE_INDEX;
656 if (idx) {
657 if (idx < 1 || idx > WEP_KEYS)
658 return -EINVAL;
659 idx--;
660 } else
661 idx = ieee->tx_keyidx;
662
663 if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
664
665 crypt = &ieee->crypt[idx];
666
667 group_key = 1;
668 } else {
669 /* some Cisco APs use idx>0 for unicast in dynamic WEP */
670 //printk("not group key, flags:%x, ext->alg:%d\n", ext->ext_flags, ext->alg);
671 if (idx != 0 && ext->alg != IW_ENCODE_ALG_WEP)
672 return -EINVAL;
673 if (ieee->iw_mode == IW_MODE_INFRA)
674
675 crypt = &ieee->crypt[idx];
676
677 else
678 return -EINVAL;
679 }
680
681 sec.flags |= SEC_ENABLED;// | SEC_ENCRYPT;
682 if ((encoding->flags & IW_ENCODE_DISABLED) ||
683 ext->alg == IW_ENCODE_ALG_NONE) {
684 if (*crypt)
685 ieee80211_crypt_delayed_deinit(ieee, crypt);
686
687 for (i = 0; i < WEP_KEYS; i++)
688
689 if (ieee->crypt[i] != NULL)
690
691 break;
692
693 if (i == WEP_KEYS) {
694 sec.enabled = 0;
695 // sec.encrypt = 0;
696 sec.level = SEC_LEVEL_0;
697 sec.flags |= SEC_LEVEL;
698 }
699 //printk("disabled: flag:%x\n", encoding->flags);
700 goto done;
701 }
702
703 sec.enabled = 1;
704 // sec.encrypt = 1;
705#if 0
706 if (group_key ? !ieee->host_mc_decrypt :
707 !(ieee->host_encrypt || ieee->host_decrypt ||
708 ieee->host_encrypt_msdu))
709 goto skip_host_crypt;
710#endif
711 switch (ext->alg) {
712 case IW_ENCODE_ALG_WEP:
713 alg = "WEP";
714 module = "ieee80211_crypt_wep";
715 break;
716 case IW_ENCODE_ALG_TKIP:
717 alg = "TKIP";
718 module = "ieee80211_crypt_tkip";
719 break;
720 case IW_ENCODE_ALG_CCMP:
721 alg = "CCMP";
722 module = "ieee80211_crypt_ccmp";
723 break;
724 default:
725 IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n",
726 dev->name, ext->alg);
727 ret = -EINVAL;
728 goto done;
729 }
730 printk("alg name:%s\n",alg);
731
732 ops = ieee80211_get_crypto_ops(alg);
733 if (ops == NULL) {
734 request_module(module);
735 ops = ieee80211_get_crypto_ops(alg);
736 }
737 if (ops == NULL) {
738 IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n",
739 dev->name, ext->alg);
740 printk("========>unknown crypto alg %d\n", ext->alg);
741 ret = -EINVAL;
742 goto done;
743 }
744
745 if (*crypt == NULL || (*crypt)->ops != ops) {
746 struct ieee80211_crypt_data *new_crypt;
747
748 ieee80211_crypt_delayed_deinit(ieee, crypt);
749
750#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
751 new_crypt = kzalloc(sizeof(*new_crypt), GFP_KERNEL);
752#else
753 new_crypt = kmalloc(sizeof(*new_crypt), GFP_KERNEL);
754 memset(new_crypt,0,sizeof(*new_crypt));
755#endif
756 if (new_crypt == NULL) {
757 ret = -ENOMEM;
758 goto done;
759 }
760 new_crypt->ops = ops;
761 if (new_crypt->ops && try_module_get(new_crypt->ops->owner))
762 new_crypt->priv = new_crypt->ops->init(idx);
763 if (new_crypt->priv == NULL) {
764 kfree(new_crypt);
765 ret = -EINVAL;
766 goto done;
767 }
768 *crypt = new_crypt;
769
770 }
771
772 if (ext->key_len > 0 && (*crypt)->ops->set_key &&
773 (*crypt)->ops->set_key(ext->key, ext->key_len, ext->rx_seq,
774 (*crypt)->priv) < 0) {
775 IEEE80211_DEBUG_WX("%s: key setting failed\n", dev->name);
776 printk("key setting failed\n");
777 ret = -EINVAL;
778 goto done;
779 }
780#if 1
781 //skip_host_crypt:
782 //printk("skip_host_crypt:ext_flags:%x\n", ext->ext_flags);
783 if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
784 ieee->tx_keyidx = idx;
785 sec.active_key = idx;
786 sec.flags |= SEC_ACTIVE_KEY;
787 }
788
789 if (ext->alg != IW_ENCODE_ALG_NONE) {
790 //memcpy(sec.keys[idx], ext->key, ext->key_len);
791 sec.key_sizes[idx] = ext->key_len;
792 sec.flags |= (1 << idx);
793 if (ext->alg == IW_ENCODE_ALG_WEP) {
794 // sec.encode_alg[idx] = SEC_ALG_WEP;
795 sec.flags |= SEC_LEVEL;
796 sec.level = SEC_LEVEL_1;
797 } else if (ext->alg == IW_ENCODE_ALG_TKIP) {
798 // sec.encode_alg[idx] = SEC_ALG_TKIP;
799 sec.flags |= SEC_LEVEL;
800 sec.level = SEC_LEVEL_2;
801 } else if (ext->alg == IW_ENCODE_ALG_CCMP) {
802 // sec.encode_alg[idx] = SEC_ALG_CCMP;
803 sec.flags |= SEC_LEVEL;
804 sec.level = SEC_LEVEL_3;
805 }
806 /* Don't set sec level for group keys. */
807 if (group_key)
808 sec.flags &= ~SEC_LEVEL;
809 }
810#endif
811done:
812 if (ieee->set_security)
813 ieee->set_security(ieee->dev, &sec);
814
815 if (ieee->reset_on_keychange &&
816 ieee->iw_mode != IW_MODE_INFRA &&
817 ieee->reset_port && ieee->reset_port(dev)) {
818 IEEE80211_DEBUG_WX("%s: reset_port failed\n", dev->name);
819 return -EINVAL;
820 }
821#endif
822 return ret;
823}
824
825int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee,
826 struct iw_request_info *info,
827 union iwreq_data *wrqu, char *extra)
828{
829 struct iw_point *encoding = &wrqu->encoding;
830 struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
831 struct ieee80211_crypt_data *crypt;
832 int idx, max_key_len;
833
834 max_key_len = encoding->length - sizeof(*ext);
835 if (max_key_len < 0)
836 return -EINVAL;
837
838 idx = encoding->flags & IW_ENCODE_INDEX;
839 if (idx) {
840 if (idx < 1 || idx > WEP_KEYS)
841 return -EINVAL;
842 idx--;
843 } else
844 idx = ieee->tx_keyidx;
845
846 if (!ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY &&
847 ext->alg != IW_ENCODE_ALG_WEP)
848 if (idx != 0 || ieee->iw_mode != IW_MODE_INFRA)
849 return -EINVAL;
850
851 crypt = ieee->crypt[idx];
852 encoding->flags = idx + 1;
853 memset(ext, 0, sizeof(*ext));
854
855 if (crypt == NULL || crypt->ops == NULL ) {
856 ext->alg = IW_ENCODE_ALG_NONE;
857 ext->key_len = 0;
858 encoding->flags |= IW_ENCODE_DISABLED;
859 } else {
860 if (strcmp(crypt->ops->name, "WEP") == 0 )
861 ext->alg = IW_ENCODE_ALG_WEP;
862 else if (strcmp(crypt->ops->name, "TKIP"))
863 ext->alg = IW_ENCODE_ALG_TKIP;
864 else if (strcmp(crypt->ops->name, "CCMP"))
865 ext->alg = IW_ENCODE_ALG_CCMP;
866 else
867 return -EINVAL;
868 ext->key_len = crypt->ops->get_key(ext->key, SCM_KEY_LEN, NULL, crypt->priv);
869 encoding->flags |= IW_ENCODE_ENABLED;
870 if (ext->key_len &&
871 (ext->alg == IW_ENCODE_ALG_TKIP ||
872 ext->alg == IW_ENCODE_ALG_CCMP))
873 ext->ext_flags |= IW_ENCODE_EXT_TX_SEQ_VALID;
874
875 }
876
877 return 0;
878}
879
880int ieee80211_wx_set_mlme(struct ieee80211_device *ieee,
881 struct iw_request_info *info,
882 union iwreq_data *wrqu, char *extra)
883{
884#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
885 struct iw_mlme *mlme = (struct iw_mlme *) extra;
886 switch (mlme->cmd) {
887 case IW_MLME_DEAUTH:
888 case IW_MLME_DISASSOC:
889 ieee80211_disassociate(ieee);
890 break;
891 default:
892 return -EOPNOTSUPP;
893 }
894#endif
895 return 0;
896}
897
898int ieee80211_wx_set_auth(struct ieee80211_device *ieee,
899 struct iw_request_info *info,
900 struct iw_param *data, char *extra)
901{
902#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
903 switch (data->flags & IW_AUTH_INDEX) {
904 case IW_AUTH_WPA_VERSION:
905 /*need to support wpa2 here*/
906 //printk("wpa version:%x\n", data->value);
907 break;
908 case IW_AUTH_CIPHER_PAIRWISE:
909 case IW_AUTH_CIPHER_GROUP:
910 case IW_AUTH_KEY_MGMT:
911 /*
912 * * Host AP driver does not use these parameters and allows
913 * * wpa_supplicant to control them internally.
914 * */
915 break;
916 case IW_AUTH_TKIP_COUNTERMEASURES:
917 ieee->tkip_countermeasures = data->value;
918 break;
919 case IW_AUTH_DROP_UNENCRYPTED:
920 ieee->drop_unencrypted = data->value;
921 break;
922
923 case IW_AUTH_80211_AUTH_ALG:
924 //printk("======>%s():data->value is %d\n",__FUNCTION__,data->value);
925 // ieee->open_wep = (data->value&IW_AUTH_ALG_OPEN_SYSTEM)?1:0;
926 if(data->value & IW_AUTH_ALG_SHARED_KEY){
927 ieee->open_wep = 0;
928 ieee->auth_mode = 1;
929 }
930 else if(data->value & IW_AUTH_ALG_OPEN_SYSTEM){
931 ieee->open_wep = 1;
932 ieee->auth_mode = 0;
933 }
934 else if(data->value & IW_AUTH_ALG_LEAP){
935 ieee->open_wep = 1;
936 ieee->auth_mode = 2;
937 //printk("hahahaa:LEAP\n");
938 }
939 else
940 return -EINVAL;
941 //printk("open_wep:%d\n", ieee->open_wep);
942 break;
943
944#if 1
945 case IW_AUTH_WPA_ENABLED:
946 ieee->wpa_enabled = (data->value)?1:0;
947 //printk("enalbe wpa:%d\n", ieee->wpa_enabled);
948 break;
949
950#endif
951 case IW_AUTH_RX_UNENCRYPTED_EAPOL:
952 ieee->ieee802_1x = data->value;
953 break;
954 case IW_AUTH_PRIVACY_INVOKED:
955 ieee->privacy_invoked = data->value;
956 break;
957 default:
958 return -EOPNOTSUPP;
959 }
960#endif
961 return 0;
962}
963#endif
964#if 1
965int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len)
966{
967#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
968#if 0
969 printk("====>%s()\n", __FUNCTION__);
970 {
971 int i;
972 for (i=0; i<len; i++)
973 printk("%2x ", ie[i]&0xff);
974 printk("\n");
975 }
976#endif
977 u8 *buf;
978
979 if (len>MAX_WPA_IE_LEN || (len && ie == NULL))
980 {
981 // printk("return error out, len:%d\n", len);
982 return -EINVAL;
983 }
984
985
986 if (len)
987 {
988 if (len != ie[1]+2)
989 {
990 printk("len:%d, ie:%d\n", len, ie[1]);
991 return -EINVAL;
992 }
993 buf = kmalloc(len, GFP_KERNEL);
994 if (buf == NULL)
995 return -ENOMEM;
996 memcpy(buf, ie, len);
997 kfree(ieee->wpa_ie);
998 ieee->wpa_ie = buf;
999 ieee->wpa_ie_len = len;
1000 }
1001 else{
1002 if (ieee->wpa_ie)
1003 kfree(ieee->wpa_ie);
1004 ieee->wpa_ie = NULL;
1005 ieee->wpa_ie_len = 0;
1006 }
1007#endif
1008 return 0;
1009
1010}
1011#endif
1012
1013#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
1014EXPORT_SYMBOL(ieee80211_wx_set_gen_ie);
1015#if (WIRELESS_EXT >= 18)
1016EXPORT_SYMBOL(ieee80211_wx_set_mlme);
1017EXPORT_SYMBOL(ieee80211_wx_set_auth);
1018EXPORT_SYMBOL(ieee80211_wx_set_encode_ext);
1019EXPORT_SYMBOL(ieee80211_wx_get_encode_ext);
1020#endif
1021EXPORT_SYMBOL(ieee80211_wx_get_scan);
1022EXPORT_SYMBOL(ieee80211_wx_set_encode);
1023EXPORT_SYMBOL(ieee80211_wx_get_encode);
1024#else
1025EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_gen_ie);
1026//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mlme);
1027//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_auth);
1028//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode_ext);
1029EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_scan);
1030EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode);
1031EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_encode);
1032#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/internal.h b/drivers/staging/rtl8192su/ieee80211/internal.h
new file mode 100644
index 00000000000..ddc22350d00
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/internal.h
@@ -0,0 +1,115 @@
1/*
2 * Cryptographic API.
3 *
4 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 */
12#ifndef _CRYPTO_INTERNAL_H
13#define _CRYPTO_INTERNAL_H
14
15
16//#include <linux/crypto.h>
17#include "rtl_crypto.h"
18#include <linux/mm.h>
19#include <linux/highmem.h>
20#include <linux/init.h>
21#include <asm/hardirq.h>
22#include <asm/softirq.h>
23#include <asm/kmap_types.h>
24
25#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20))
26#define list_for_each_entry(pos, head, member) \
27 for (pos = list_entry((head)->next, typeof(*pos), member), \
28 prefetch(pos->member.next); \
29 &pos->member != (head); \
30 pos = list_entry(pos->member.next, typeof(*pos), member), \
31 prefetch(pos->member.next))
32
33static inline void cond_resched(void)
34{
35 if (need_resched()) {
36 set_current_state(TASK_RUNNING);
37 schedule();
38 }
39}
40#endif
41
42extern enum km_type crypto_km_types[];
43
44static inline enum km_type crypto_kmap_type(int out)
45{
46 return crypto_km_types[(in_softirq() ? 2 : 0) + out];
47}
48
49static inline void *crypto_kmap(struct page *page, int out)
50{
51 return kmap_atomic(page, crypto_kmap_type(out));
52}
53
54static inline void crypto_kunmap(void *vaddr, int out)
55{
56 kunmap_atomic(vaddr, crypto_kmap_type(out));
57}
58
59static inline void crypto_yield(struct crypto_tfm *tfm)
60{
61 if (!in_softirq())
62 cond_resched();
63}
64
65static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm)
66{
67 return (void *)&tfm[1];
68}
69
70struct crypto_alg *crypto_alg_lookup(const char *name);
71
72#ifdef CONFIG_KMOD
73void crypto_alg_autoload(const char *name);
74struct crypto_alg *crypto_alg_mod_lookup(const char *name);
75#else
76static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name)
77{
78 return crypto_alg_lookup(name);
79}
80#endif
81
82#ifdef CONFIG_CRYPTO_HMAC
83int crypto_alloc_hmac_block(struct crypto_tfm *tfm);
84void crypto_free_hmac_block(struct crypto_tfm *tfm);
85#else
86static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm)
87{
88 return 0;
89}
90
91static inline void crypto_free_hmac_block(struct crypto_tfm *tfm)
92{ }
93#endif
94
95#ifdef CONFIG_PROC_FS
96void __init crypto_init_proc(void);
97#else
98static inline void crypto_init_proc(void)
99{ }
100#endif
101
102int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags);
103int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags);
104int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags);
105
106int crypto_init_digest_ops(struct crypto_tfm *tfm);
107int crypto_init_cipher_ops(struct crypto_tfm *tfm);
108int crypto_init_compress_ops(struct crypto_tfm *tfm);
109
110void crypto_exit_digest_ops(struct crypto_tfm *tfm);
111void crypto_exit_cipher_ops(struct crypto_tfm *tfm);
112void crypto_exit_compress_ops(struct crypto_tfm *tfm);
113
114#endif /* _CRYPTO_INTERNAL_H */
115
diff --git a/drivers/staging/rtl8192su/ieee80211/kmap_types.h b/drivers/staging/rtl8192su/ieee80211/kmap_types.h
new file mode 100644
index 00000000000..de67bb01b5f
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/kmap_types.h
@@ -0,0 +1,20 @@
1#ifndef __KMAP_TYPES_H
2
3#define __KMAP_TYPES_H
4
5
6enum km_type {
7 KM_BOUNCE_READ,
8 KM_SKB_SUNRPC_DATA,
9 KM_SKB_DATA_SOFTIRQ,
10 KM_USER0,
11 KM_USER1,
12 KM_BH_IRQ,
13 KM_SOFTIRQ0,
14 KM_SOFTIRQ1,
15 KM_TYPE_NR
16};
17
18#define _ASM_KMAP_TYPES_H
19
20#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/michael_mic.c b/drivers/staging/rtl8192su/ieee80211/michael_mic.c
new file mode 100644
index 00000000000..df256e487c2
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/michael_mic.c
@@ -0,0 +1,194 @@
1/*
2 * Cryptographic API
3 *
4 * Michael MIC (IEEE 802.11i/TKIP) keyed digest
5 *
6 * Copyright (c) 2004 Jouni Malinen <jkmaline@cc.hut.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/string.h>
16//#include <linux/crypto.h>
17#include "rtl_crypto.h"
18
19
20struct michael_mic_ctx {
21 u8 pending[4];
22 size_t pending_len;
23
24 u32 l, r;
25};
26
27
28static inline u32 rotl(u32 val, int bits)
29{
30 return (val << bits) | (val >> (32 - bits));
31}
32
33
34static inline u32 rotr(u32 val, int bits)
35{
36 return (val >> bits) | (val << (32 - bits));
37}
38
39
40static inline u32 xswap(u32 val)
41{
42 return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8);
43}
44
45
46#define michael_block(l, r) \
47do { \
48 r ^= rotl(l, 17); \
49 l += r; \
50 r ^= xswap(l); \
51 l += r; \
52 r ^= rotl(l, 3); \
53 l += r; \
54 r ^= rotr(l, 2); \
55 l += r; \
56} while (0)
57
58
59static inline u32 get_le32(const u8 *p)
60{
61 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
62}
63
64
65static inline void put_le32(u8 *p, u32 v)
66{
67 p[0] = v;
68 p[1] = v >> 8;
69 p[2] = v >> 16;
70 p[3] = v >> 24;
71}
72
73
74static void michael_init(void *ctx)
75{
76 struct michael_mic_ctx *mctx = ctx;
77 mctx->pending_len = 0;
78}
79
80
81static void michael_update(void *ctx, const u8 *data, unsigned int len)
82{
83 struct michael_mic_ctx *mctx = ctx;
84
85 if (mctx->pending_len) {
86 int flen = 4 - mctx->pending_len;
87 if (flen > len)
88 flen = len;
89 memcpy(&mctx->pending[mctx->pending_len], data, flen);
90 mctx->pending_len += flen;
91 data += flen;
92 len -= flen;
93
94 if (mctx->pending_len < 4)
95 return;
96
97 mctx->l ^= get_le32(mctx->pending);
98 michael_block(mctx->l, mctx->r);
99 mctx->pending_len = 0;
100 }
101
102 while (len >= 4) {
103 mctx->l ^= get_le32(data);
104 michael_block(mctx->l, mctx->r);
105 data += 4;
106 len -= 4;
107 }
108
109 if (len > 0) {
110 mctx->pending_len = len;
111 memcpy(mctx->pending, data, len);
112 }
113}
114
115
116static void michael_final(void *ctx, u8 *out)
117{
118 struct michael_mic_ctx *mctx = ctx;
119 u8 *data = mctx->pending;
120
121 /* Last block and padding (0x5a, 4..7 x 0) */
122 switch (mctx->pending_len) {
123 case 0:
124 mctx->l ^= 0x5a;
125 break;
126 case 1:
127 mctx->l ^= data[0] | 0x5a00;
128 break;
129 case 2:
130 mctx->l ^= data[0] | (data[1] << 8) | 0x5a0000;
131 break;
132 case 3:
133 mctx->l ^= data[0] | (data[1] << 8) | (data[2] << 16) |
134 0x5a000000;
135 break;
136 }
137 michael_block(mctx->l, mctx->r);
138 /* l ^= 0; */
139 michael_block(mctx->l, mctx->r);
140
141 put_le32(out, mctx->l);
142 put_le32(out + 4, mctx->r);
143}
144
145
146static int michael_setkey(void *ctx, const u8 *key, unsigned int keylen,
147 u32 *flags)
148{
149 struct michael_mic_ctx *mctx = ctx;
150 if (keylen != 8) {
151 if (flags)
152 *flags = CRYPTO_TFM_RES_BAD_KEY_LEN;
153 return -EINVAL;
154 }
155 mctx->l = get_le32(key);
156 mctx->r = get_le32(key + 4);
157 return 0;
158}
159
160
161static struct crypto_alg michael_mic_alg = {
162 .cra_name = "michael_mic",
163 .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
164 .cra_blocksize = 8,
165 .cra_ctxsize = sizeof(struct michael_mic_ctx),
166 .cra_module = THIS_MODULE,
167 .cra_list = LIST_HEAD_INIT(michael_mic_alg.cra_list),
168 .cra_u = { .digest = {
169 .dia_digestsize = 8,
170 .dia_init = michael_init,
171 .dia_update = michael_update,
172 .dia_final = michael_final,
173 .dia_setkey = michael_setkey } }
174};
175
176
177static int __init michael_mic_init(void)
178{
179 return crypto_register_alg(&michael_mic_alg);
180}
181
182
183static void __exit michael_mic_exit(void)
184{
185 crypto_unregister_alg(&michael_mic_alg);
186}
187
188
189module_init(michael_mic_init);
190module_exit(michael_mic_exit);
191
192MODULE_LICENSE("GPL v2");
193MODULE_DESCRIPTION("Michael MIC");
194MODULE_AUTHOR("Jouni Malinen <jkmaline@cc.hut.fi>");
diff --git a/drivers/staging/rtl8192su/ieee80211/proc.c b/drivers/staging/rtl8192su/ieee80211/proc.c
new file mode 100644
index 00000000000..4f3f9ed7751
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/proc.c
@@ -0,0 +1,116 @@
1/*
2 * Scatterlist Cryptographic API.
3 *
4 * Procfs information.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14#include <linux/init.h>
15//#include <linux/crypto.h>
16#include "rtl_crypto.h"
17#include <linux/rwsem.h>
18#include <linux/proc_fs.h>
19#include <linux/seq_file.h>
20#include "internal.h"
21
22extern struct list_head crypto_alg_list;
23extern struct rw_semaphore crypto_alg_sem;
24
25static void *c_start(struct seq_file *m, loff_t *pos)
26{
27 struct list_head *v;
28 loff_t n = *pos;
29
30 down_read(&crypto_alg_sem);
31 list_for_each(v, &crypto_alg_list)
32 if (!n--)
33 return list_entry(v, struct crypto_alg, cra_list);
34 return NULL;
35}
36
37static void *c_next(struct seq_file *m, void *p, loff_t *pos)
38{
39 struct list_head *v = p;
40
41 (*pos)++;
42 v = v->next;
43 return (v == &crypto_alg_list) ?
44 NULL : list_entry(v, struct crypto_alg, cra_list);
45}
46
47static void c_stop(struct seq_file *m, void *p)
48{
49 up_read(&crypto_alg_sem);
50}
51
52static int c_show(struct seq_file *m, void *p)
53{
54 struct crypto_alg *alg = (struct crypto_alg *)p;
55
56 seq_printf(m, "name : %s\n", alg->cra_name);
57 seq_printf(m, "module : %s\n",
58 (alg->cra_module ?
59 alg->cra_module->name :
60 "kernel"));
61
62 switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
63 case CRYPTO_ALG_TYPE_CIPHER:
64 seq_printf(m, "type : cipher\n");
65 seq_printf(m, "blocksize : %u\n", alg->cra_blocksize);
66 seq_printf(m, "min keysize : %u\n",
67 alg->cra_cipher.cia_min_keysize);
68 seq_printf(m, "max keysize : %u\n",
69 alg->cra_cipher.cia_max_keysize);
70 break;
71
72 case CRYPTO_ALG_TYPE_DIGEST:
73 seq_printf(m, "type : digest\n");
74 seq_printf(m, "blocksize : %u\n", alg->cra_blocksize);
75 seq_printf(m, "digestsize : %u\n",
76 alg->cra_digest.dia_digestsize);
77 break;
78 case CRYPTO_ALG_TYPE_COMPRESS:
79 seq_printf(m, "type : compression\n");
80 break;
81 default:
82 seq_printf(m, "type : unknown\n");
83 break;
84 }
85
86 seq_putc(m, '\n');
87 return 0;
88}
89
90static struct seq_operations crypto_seq_ops = {
91 .start = c_start,
92 .next = c_next,
93 .stop = c_stop,
94 .show = c_show
95};
96
97static int crypto_info_open(struct inode *inode, struct file *file)
98{
99 return seq_open(file, &crypto_seq_ops);
100}
101
102static struct file_operations proc_crypto_ops = {
103 .open = crypto_info_open,
104 .read = seq_read,
105 .llseek = seq_lseek,
106 .release = seq_release
107};
108
109void __init crypto_init_proc(void)
110{
111 struct proc_dir_entry *proc;
112
113 proc = create_proc_entry("crypto", 0, NULL);
114 if (proc)
115 proc->proc_fops = &proc_crypto_ops;
116}
diff --git a/drivers/staging/rtl8192su/ieee80211/readme b/drivers/staging/rtl8192su/ieee80211/readme
new file mode 100644
index 00000000000..5764f285928
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/readme
@@ -0,0 +1,162 @@
1What this layer should do
2
3- It mantain the old mechanism as alternative, so the
4 ipw2100 driver works with really few changes.
5- Encapsulate / Decapsulate ieee80211 packet
6- Handle fragmentation
7- Optionally provide an alterantive mechanism for netif queue stop/wake,
8 so that the ieee80211 layer will pass one fragment per time instead of
9 one txb struct per time. so the driver can stop the queue in the middle
10 of a packet.
11- Provide two different TX interfaces for cards that can handle management
12 frames on one HW queue, and data on another, and for cards that have only
13 one HW queue (the latter untested and very, very rough).
14- Optionally provide the logic for handling IBSS/MASTER/MONITOR/BSS modes
15 and for the channel, essid and wap get/set wireless extension requests.
16 so that the driver has only to change channel when the ieee stack tell it.
17- Optionally provide a scanning mechanism so that the driver has not to
18 worry about this, just implement the set channel calback and pass
19 frames to the upper layer
20- Optionally provide the bss client protocol handshaking (just with open
21 authentication)
22- Optionally provide the probe request send mechanism
23- Optionally provide the bss master mode logic to handle association
24 protocol (only open authentication) and probe responses.
25- SW wep encryption (with open authentication)
26- It collects some stats
27- It provides beacons to the card when it ask for them
28
29What this layer doesn't do (yet)
30- Perform shared authentication
31- Have full support for master mode (the AP should loop back in the air
32 frames from an associated client to another. This could be done easily
33 with few lines of code, and it is done in my previous version of the
34 stach, but a table of association must be keept and a disassociation
35 policy must be decided and implemented.
36- Handle cleanly the full ieee 802.11 protocol. In AP mode it never
37 disassociate clients, and it is really prone to always allow access.
38 In bss client mode it is a bit rough with AP deauth and disassoc requests.
39- It has not any entry point to view the collected stats.
40- Altought it takes care of the card supported rates in the management frame
41 it sends, support for rate changing on TXed packet is not complete.
42- Give up once associated in bss client mode (it never detect a
43 signal loss condition to disassociate and restart scanning)
44- Provide a mechanism for enabling the TX in monitor mode, so
45 userspace programs can TX raw packets.
46- Provide a mechanism for cards that need that the SW take care of beacon
47 TX completely, in sense that the SW has to enqueue by itself beacons
48 to the card so it TX them (if any...)
49APIs
50
51Callback functions in the original stack has been mantained.
52following has been added (from ieee80211.h)
53
54 /* Softmac-generated frames (mamagement) are TXed via this
55 * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is
56 * not set. As some cards may have different HW queues that
57 * one might want to use for data and management frames
58 * the option to have two callbacks might be useful.
59 * This fucntion can't sleep.
60 */
61 int (*softmac_hard_start_xmit)(struct sk_buff *skb,
62 struct net_device *dev);
63
64 /* used instead of hard_start_xmit (not softmac_hard_start_xmit)
65 * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data
66 * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set
67 * then also management frames are sent via this callback.
68 * This function can't sleep.
69 */
70 void (*softmac_data_hard_start_xmit)(struct sk_buff *skb,
71 struct net_device *dev);
72
73 /* stops the HW queue for DATA frames. Useful to avoid
74 * waste time to TX data frame when we are reassociating
75 * This function can sleep.
76 */
77 void (*data_hard_stop)(struct net_device *dev);
78
79 /* OK this is complementar to data_poll_hard_stop */
80 void (*data_hard_resume)(struct net_device *dev);
81
82 /* ask to the driver to retune the radio .
83 * This function can sleep. the driver should ensure
84 * the radio has been swithced before return.
85 */
86 void (*set_chan)(struct net_device *dev,short ch);
87
88 /* These are not used if the ieee stack takes care of
89 * scanning (IEEE_SOFTMAC_SCAN feature set).
90 * In this case only the set_chan is used.
91 *
92 * The syncro version is similar to the start_scan but
93 * does not return until all channels has been scanned.
94 * this is called in user context and should sleep,
95 * it is called in a work_queue when swithcing to ad-hoc mode
96 * or in behalf of iwlist scan when the card is associated
97 * and root user ask for a scan.
98 * the fucntion stop_scan should stop both the syncro and
99 * background scanning and can sleep.
100 * The fucntion start_scan should initiate the background
101 * scanning and can't sleep.
102 */
103 void (*scan_syncro)(struct net_device *dev);
104 void (*start_scan)(struct net_device *dev);
105 void (*stop_scan)(struct net_device *dev);
106
107 /* indicate the driver that the link state is changed
108 * for example it may indicate the card is associated now.
109 * Driver might be interested in this to apply RX filter
110 * rules or simply light the LINK led
111 */
112 void (*link_change)(struct net_device *dev);
113
114Functions hard_data_[resume/stop] are optional and should not be used
115if the driver decides to uses data+management frames enqueue in a
116single HQ queue (thus using just the softmac_hard_data_start_xmit
117callback).
118
119Function that the driver can use are:
120
121ieee80211_get_beacon - this is called by the driver when
122 the HW needs a beacon.
123ieee80211_softmac_start_protocol - this should normally be called in the
124 driver open function
125ieee80211_softmac_stop_protocol - the opposite of the above
126ieee80211_wake_queue - this is similar to netif_wake_queue
127ieee80211_reset_queue - this throw away fragments pending(if any)
128ieee80211_stop_queue - this is similar to netif_stop_queue
129
130
131known BUGS:
132- When performing syncro scan (possiblily when swithcing to ad-hoc mode
133 and when running iwlist scan when associated) there is still an odd
134 behaviour.. I have not looked in this more accurately (yet).
135
136locking:
137locking is done by means of three structures.
1381- ieee->lock (by means of spin_[un]lock_irq[save/restore]
1392- ieee->wx_sem
1403- ieee->scan_sem
141
142the lock 1 is what protect most of the critical sections in the ieee stack.
143the lock 2 is used to avoid that more than one of the SET wireless extension
144handlers (as well as start/stop protocol function) are running at the same time.
145the lock 1 is used when we need to modify or read the shared data in the wx handlers.
146In other words the lock 2 will prevent one SET action will run across another SET
147action (by make sleep the 2nd one) but allow GET actions, while the lock 1
148make atomic those little shared data access in both GET and SET operation.
149So get operation will be never be delayed really: they will never sleep..
150Furthermore in the top of some SET operations a flag is set before acquiring
151the lock. This is an help to make the previous running SET operation to
152finish faster if needed (just in case the second one will totally undo the
153first, so there is not need to complete the 1st really.. ).
154The background scanning mechaninsm is protected by the lock 1 except for the
155workqueue. this wq is here just to let the set_chan callback sleep (I thinked it
156might be appreciated by USB network card driver developer). In this case the lock 3
157take its turn.
158Thus the stop function needs both the locks.
159Funny in the syncro scan the lock 2 play its role (as both the syncro_scan
160function and the stop scan function are called with this semaphore held).
161
162
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h
new file mode 100644
index 00000000000..8ddc8bf9dc2
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h
@@ -0,0 +1,69 @@
1#ifndef _BATYPE_H_
2#define _BATYPE_H_
3
4#define TOTAL_TXBA_NUM 16
5#define TOTAL_RXBA_NUM 16
6
7#define BA_SETUP_TIMEOUT 200
8#define BA_INACT_TIMEOUT 60000
9
10#define BA_POLICY_DELAYED 0
11#define BA_POLICY_IMMEDIATE 1
12
13#define ADDBA_STATUS_SUCCESS 0
14#define ADDBA_STATUS_REFUSED 37
15#define ADDBA_STATUS_INVALID_PARAM 38
16
17#define DELBA_REASON_QSTA_LEAVING 36
18#define DELBA_REASON_END_BA 37
19#define DELBA_REASON_UNKNOWN_BA 38
20#define DELBA_REASON_TIMEOUT 39
21/* whether need define BA Action frames here?
22struct ieee80211_ADDBA_Req{
23 struct ieee80211_header_data header;
24 u8 category;
25 u8
26} __attribute__ ((packed));
27*/
28//Is this need?I put here just to make it easier to define structure BA_RECORD //WB
29typedef union _SEQUENCE_CONTROL{
30 u16 ShortData;
31 struct
32 {
33 u16 FragNum:4;
34 u16 SeqNum:12;
35 }field;
36}SEQUENCE_CONTROL, *PSEQUENCE_CONTROL;
37
38typedef union _BA_PARAM_SET {
39 u8 charData[2];
40 u16 shortData;
41 struct {
42 u16 AMSDU_Support:1;
43 u16 BAPolicy:1;
44 u16 TID:4;
45 u16 BufferSize:10;
46 } field;
47} BA_PARAM_SET, *PBA_PARAM_SET;
48
49typedef union _DELBA_PARAM_SET {
50 u8 charData[2];
51 u16 shortData;
52 struct {
53 u16 Reserved:11;
54 u16 Initiator:1;
55 u16 TID:4;
56 } field;
57} DELBA_PARAM_SET, *PDELBA_PARAM_SET;
58
59typedef struct _BA_RECORD {
60 struct timer_list Timer;
61 u8 bValid;
62 u8 DialogToken;
63 BA_PARAM_SET BaParamSet;
64 u16 BaTimeoutValue;
65 SEQUENCE_CONTROL BaStartSeqCtrl;
66} BA_RECORD, *PBA_RECORD;
67
68#endif //end _BATYPE_H_
69
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c
new file mode 100644
index 00000000000..cc5623a94b4
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c
@@ -0,0 +1,781 @@
1/********************************************************************************************************************************
2 * This file is created to process BA Action Frame. According to 802.11 spec, there are 3 BA action types at all. And as BA is
3 * related to TS, this part need some struture defined in QOS side code. Also TX RX is going to be resturctured, so how to send
4 * ADDBAREQ ADDBARSP and DELBA packet is still on consideration. Temporarily use MANAGE QUEUE instead of Normal Queue.
5 * WB 2008-05-27
6 * *****************************************************************************************************************************/
7#include "ieee80211.h"
8#include "rtl819x_BA.h"
9
10/********************************************************************************************************************
11 *function: Activate BA entry. And if Time is nozero, start timer.
12 * input: PBA_RECORD pBA //BA entry to be enabled
13 * u16 Time //indicate time delay.
14 * output: none
15********************************************************************************************************************/
16void ActivateBAEntry(struct ieee80211_device* ieee, PBA_RECORD pBA, u16 Time)
17{
18 pBA->bValid = true;
19 if(Time != 0)
20 mod_timer(&pBA->Timer, jiffies + MSECS(Time));
21}
22
23/********************************************************************************************************************
24 *function: deactivate BA entry, including its timer.
25 * input: PBA_RECORD pBA //BA entry to be disabled
26 * output: none
27********************************************************************************************************************/
28void DeActivateBAEntry( struct ieee80211_device* ieee, PBA_RECORD pBA)
29{
30 pBA->bValid = false;
31 del_timer_sync(&pBA->Timer);
32}
33/********************************************************************************************************************
34 *function: deactivete BA entry in Tx Ts, and send DELBA.
35 * input:
36 * PTX_TS_RECORD pTxTs //Tx Ts which is to deactivate BA entry.
37 * output: none
38 * notice: As PTX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME
39********************************************************************************************************************/
40u8 TxTsDeleteBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTxTs)
41{
42 PBA_RECORD pAdmittedBa = &pTxTs->TxAdmittedBARecord; //These two BA entries must exist in TS structure
43 PBA_RECORD pPendingBa = &pTxTs->TxPendingBARecord;
44 u8 bSendDELBA = false;
45
46 // Delete pending BA
47 if(pPendingBa->bValid)
48 {
49 DeActivateBAEntry(ieee, pPendingBa);
50 bSendDELBA = true;
51 }
52
53 // Delete admitted BA
54 if(pAdmittedBa->bValid)
55 {
56 DeActivateBAEntry(ieee, pAdmittedBa);
57 bSendDELBA = true;
58 }
59
60 return bSendDELBA;
61}
62
63/********************************************************************************************************************
64 *function: deactivete BA entry in Tx Ts, and send DELBA.
65 * input:
66 * PRX_TS_RECORD pRxTs //Rx Ts which is to deactivate BA entry.
67 * output: none
68 * notice: As PRX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME, same with above
69********************************************************************************************************************/
70u8 RxTsDeleteBA( struct ieee80211_device* ieee, PRX_TS_RECORD pRxTs)
71{
72 PBA_RECORD pBa = &pRxTs->RxAdmittedBARecord;
73 u8 bSendDELBA = false;
74
75 if(pBa->bValid)
76 {
77 DeActivateBAEntry(ieee, pBa);
78 bSendDELBA = true;
79 }
80
81 return bSendDELBA;
82}
83
84/********************************************************************************************************************
85 *function: reset BA entry
86 * input:
87 * PBA_RECORD pBA //entry to be reset
88 * output: none
89********************************************************************************************************************/
90void ResetBaEntry( PBA_RECORD pBA)
91{
92 pBA->bValid = false;
93 pBA->BaParamSet.shortData = 0;
94 pBA->BaTimeoutValue = 0;
95 pBA->DialogToken = 0;
96 pBA->BaStartSeqCtrl.ShortData = 0;
97}
98//These functions need porting here or not?
99/*******************************************************************************************************************************
100 *function: construct ADDBAREQ and ADDBARSP frame here together.
101 * input: u8* Dst //ADDBA frame's destination
102 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA.
103 * u16 StatusCode //status code in RSP and I will use it to indicate whether it's RSP or REQ(will I?)
104 * u8 type //indicate whether it's RSP(ACT_ADDBARSP) ow REQ(ACT_ADDBAREQ)
105 * output: none
106 * return: sk_buff* skb //return constructed skb to xmit
107*******************************************************************************************************************************/
108static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, PBA_RECORD pBA, u16 StatusCode, u8 type)
109{
110 struct sk_buff *skb = NULL;
111 struct ieee80211_hdr_3addr* BAReq = NULL;
112 u8* tag = NULL;
113 u16 tmp = 0;
114 u16 len = ieee->tx_headroom + 9;
115 //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2))
116 IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev);
117 if (pBA == NULL||ieee == NULL)
118 {
119 IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee);
120 return NULL;
121 }
122 skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME
123 if (skb == NULL)
124 {
125 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n");
126 return NULL;
127 }
128
129 memset(skb->data, 0, sizeof( struct ieee80211_hdr_3addr)); //I wonder whether it's necessary. Apparently kernel will not do it when alloc a skb.
130 skb_reserve(skb, ieee->tx_headroom);
131
132 BAReq = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr));
133
134 memcpy(BAReq->addr1, Dst, ETH_ALEN);
135 memcpy(BAReq->addr2, ieee->dev->dev_addr, ETH_ALEN);
136
137 memcpy(BAReq->addr3, ieee->current_network.bssid, ETH_ALEN);
138
139 BAReq->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame
140
141 //tag += sizeof( struct ieee80211_hdr_3addr); //move to action field
142 tag = (u8*)skb_put(skb, 9);
143 *tag ++= ACT_CAT_BA;
144 *tag ++= type;
145 // Dialog Token
146 *tag ++= pBA->DialogToken;
147
148 if (ACT_ADDBARSP == type)
149 {
150 // Status Code
151 printk("=====>to send ADDBARSP\n");
152 tmp = cpu_to_le16(StatusCode);
153 memcpy(tag, (u8*)&tmp, 2);
154 tag += 2;
155 }
156 // BA Parameter Set
157 tmp = cpu_to_le16(pBA->BaParamSet.shortData);
158 memcpy(tag, (u8*)&tmp, 2);
159 tag += 2;
160 // BA Timeout Value
161 tmp = cpu_to_le16(pBA->BaTimeoutValue);
162 memcpy(tag, (u8*)&tmp, 2);
163 tag += 2;
164
165 if (ACT_ADDBAREQ == type)
166 {
167 // BA Start SeqCtrl
168 memcpy(tag,(u8*)&(pBA->BaStartSeqCtrl), 2);
169 tag += 2;
170 }
171
172 IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len);
173 return skb;
174 //return NULL;
175}
176
177#if 0 //I try to merge ADDBA_REQ and ADDBA_RSP frames together..
178/********************************************************************************************************************
179 *function: construct ADDBAREQ frame
180 * input: u8* dst //ADDBARsp frame's destination
181 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA_RSP.
182 * u16 StatusCode //status code.
183 * output: none
184 * return: sk_buff* skb //return constructed skb to xmit
185********************************************************************************************************************/
186static struct sk_buff* ieee80211_ADDBA_Rsp( IN struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode)
187{
188 OCTET_STRING osADDBAFrame, tmp;
189
190 FillOctetString(osADDBAFrame, Buffer, 0);
191 *pLength = 0;
192
193 ConstructMaFrameHdr(
194 Adapter,
195 Addr,
196 ACT_CAT_BA,
197 ACT_ADDBARSP,
198 &osADDBAFrame );
199
200 // Dialog Token
201 FillOctetString(tmp, &pBA->DialogToken, 1);
202 PacketAppendData(&osADDBAFrame, tmp);
203
204 // Status Code
205 FillOctetString(tmp, &StatusCode, 2);
206 PacketAppendData(&osADDBAFrame, tmp);
207
208 // BA Parameter Set
209 FillOctetString(tmp, &pBA->BaParamSet, 2);
210 PacketAppendData(&osADDBAFrame, tmp);
211
212 // BA Timeout Value
213 FillOctetString(tmp, &pBA->BaTimeoutValue, 2);
214 PacketAppendData(&osADDBAFrame, tmp);
215
216 *pLength = osADDBAFrame.Length;
217}
218#endif
219
220/********************************************************************************************************************
221 *function: construct DELBA frame
222 * input: u8* dst //DELBA frame's destination
223 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA
224 * TR_SELECT TxRxSelect //TX RX direction
225 * u16 ReasonCode //status code.
226 * output: none
227 * return: sk_buff* skb //return constructed skb to xmit
228********************************************************************************************************************/
229static struct sk_buff* ieee80211_DELBA(
230 struct ieee80211_device* ieee,
231 u8* dst,
232 PBA_RECORD pBA,
233 TR_SELECT TxRxSelect,
234 u16 ReasonCode
235 )
236{
237 DELBA_PARAM_SET DelbaParamSet;
238 struct sk_buff *skb = NULL;
239 struct ieee80211_hdr_3addr* Delba = NULL;
240 u8* tag = NULL;
241 u16 tmp = 0;
242 //len = head len + DELBA Parameter Set(2) + Reason Code(2)
243 u16 len = 6 + ieee->tx_headroom;
244
245 if (net_ratelimit())
246 IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst));
247
248 memset(&DelbaParamSet, 0, 2);
249
250 DelbaParamSet.field.Initiator = (TxRxSelect==TX_DIR)?1:0;
251 DelbaParamSet.field.TID = pBA->BaParamSet.field.TID;
252
253 skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME
254 if (skb == NULL)
255 {
256 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n");
257 return NULL;
258 }
259// memset(skb->data, 0, len+sizeof( struct ieee80211_hdr_3addr));
260 skb_reserve(skb, ieee->tx_headroom);
261
262 Delba = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr));
263
264 memcpy(Delba->addr1, dst, ETH_ALEN);
265 memcpy(Delba->addr2, ieee->dev->dev_addr, ETH_ALEN);
266 memcpy(Delba->addr3, ieee->current_network.bssid, ETH_ALEN);
267 Delba->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame
268
269 tag = (u8*)skb_put(skb, 6);
270
271 *tag ++= ACT_CAT_BA;
272 *tag ++= ACT_DELBA;
273
274 // DELBA Parameter Set
275 tmp = cpu_to_le16(DelbaParamSet.shortData);
276 memcpy(tag, (u8*)&tmp, 2);
277 tag += 2;
278 // Reason Code
279 tmp = cpu_to_le16(ReasonCode);
280 memcpy(tag, (u8*)&tmp, 2);
281 tag += 2;
282
283 IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len);
284 if (net_ratelimit())
285 IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "<=====%s()\n", __FUNCTION__);
286 return skb;
287}
288
289/********************************************************************************************************************
290 *function: send ADDBAReq frame out
291 * input: u8* dst //ADDBAReq frame's destination
292 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA
293 * output: none
294 * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does
295********************************************************************************************************************/
296void ieee80211_send_ADDBAReq(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA)
297{
298 struct sk_buff *skb = NULL;
299 skb = ieee80211_ADDBA(ieee, dst, pBA, 0, ACT_ADDBAREQ); //construct ACT_ADDBAREQ frames so set statuscode zero.
300
301 if (skb)
302 {
303 softmac_mgmt_xmit(skb, ieee);
304 //add statistic needed here.
305 //and skb will be freed in softmac_mgmt_xmit(), so omit all dev_kfree_skb_any() outside softmac_mgmt_xmit()
306 //WB
307 }
308 else
309 {
310 IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__);
311 }
312 return;
313}
314
315/********************************************************************************************************************
316 *function: send ADDBARSP frame out
317 * input: u8* dst //DELBA frame's destination
318 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA
319 * u16 StatusCode //RSP StatusCode
320 * output: none
321 * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does
322********************************************************************************************************************/
323void ieee80211_send_ADDBARsp(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode)
324{
325 struct sk_buff *skb = NULL;
326 skb = ieee80211_ADDBA(ieee, dst, pBA, StatusCode, ACT_ADDBARSP); //construct ACT_ADDBARSP frames
327 if (skb)
328 {
329 softmac_mgmt_xmit(skb, ieee);
330 //same above
331 }
332 else
333 {
334 IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__);
335 }
336
337 return;
338
339}
340/********************************************************************************************************************
341 *function: send ADDBARSP frame out
342 * input: u8* dst //DELBA frame's destination
343 * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA
344 * TR_SELECT TxRxSelect //TX or RX
345 * u16 ReasonCode //DEL ReasonCode
346 * output: none
347 * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does
348********************************************************************************************************************/
349
350void ieee80211_send_DELBA(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, TR_SELECT TxRxSelect, u16 ReasonCode)
351{
352 struct sk_buff *skb = NULL;
353 skb = ieee80211_DELBA(ieee, dst, pBA, TxRxSelect, ReasonCode); //construct ACT_ADDBARSP frames
354 if (skb)
355 {
356 softmac_mgmt_xmit(skb, ieee);
357 //same above
358 }
359 else
360 {
361 IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__);
362 }
363 return ;
364}
365
366/********************************************************************************************************************
367 *function: RX ADDBAReq
368 * input: struct sk_buff * skb //incoming ADDBAReq skb.
369 * return: 0(pass), other(fail)
370 * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support.
371********************************************************************************************************************/
372int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb)
373{
374 struct ieee80211_hdr_3addr* req = NULL;
375 u16 rc = 0;
376 u8 * dst = NULL, *pDialogToken = NULL, *tag = NULL;
377 PBA_RECORD pBA = NULL;
378 PBA_PARAM_SET pBaParamSet = NULL;
379 u16* pBaTimeoutVal = NULL;
380 PSEQUENCE_CONTROL pBaStartSeqCtrl = NULL;
381 PRX_TS_RECORD pTS = NULL;
382
383 if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9)
384 {
385 IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BAREQ(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9));
386 return -1;
387 }
388
389 IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len);
390
391 req = ( struct ieee80211_hdr_3addr*) skb->data;
392 tag = (u8*)req;
393 dst = (u8*)(&req->addr2[0]);
394 tag += sizeof( struct ieee80211_hdr_3addr);
395 pDialogToken = tag + 2; //category+action
396 pBaParamSet = (PBA_PARAM_SET)(tag + 3); //+DialogToken
397 pBaTimeoutVal = (u16*)(tag + 5);
398 pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7);
399
400 printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst));
401//some other capability is not ready now.
402 if( (ieee->current_network.qos_data.active == 0) ||
403 (ieee->pHTInfo->bCurrentHTSupport == false) ||
404 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_REJECT_ADDBA_REQ)) //||
405 // (ieee->pStaQos->bEnableRxImmBA == false) )
406 {
407 rc = ADDBA_STATUS_REFUSED;
408 IEEE80211_DEBUG(IEEE80211_DL_ERR, "Failed to reply on ADDBA_REQ as some capability is not ready(%d, %d)\n", ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport);
409 goto OnADDBAReq_Fail;
410 }
411 // Search for related traffic stream.
412 // If there is no matched TS, reject the ADDBA request.
413 if( !GetTs(
414 ieee,
415 (PTS_COMMON_INFO*)(&pTS),
416 dst,
417 (u8)(pBaParamSet->field.TID),
418 RX_DIR,
419 true) )
420 {
421 rc = ADDBA_STATUS_REFUSED;
422 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__);
423 goto OnADDBAReq_Fail;
424 }
425 pBA = &pTS->RxAdmittedBARecord;
426 // To Determine the ADDBA Req content
427 // We can do much more check here, including BufferSize, AMSDU_Support, Policy, StartSeqCtrl...
428 // I want to check StartSeqCtrl to make sure when we start aggregation!!!
429 //
430 if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED)
431 {
432 rc = ADDBA_STATUS_INVALID_PARAM;
433 IEEE80211_DEBUG(IEEE80211_DL_ERR, "BA Policy is not correct in %s()\n", __FUNCTION__);
434 goto OnADDBAReq_Fail;
435 }
436 // Admit the ADDBA Request
437 //
438 DeActivateBAEntry(ieee, pBA);
439 pBA->DialogToken = *pDialogToken;
440 pBA->BaParamSet = *pBaParamSet;
441 pBA->BaTimeoutValue = *pBaTimeoutVal;
442 pBA->BaStartSeqCtrl = *pBaStartSeqCtrl;
443 //for half N mode we only aggregate 1 frame
444 if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)||
445 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT))
446 pBA->BaParamSet.field.BufferSize = 1;
447 else
448 pBA->BaParamSet.field.BufferSize = 32;
449 ActivateBAEntry(ieee, pBA, 0);//pBA->BaTimeoutValue);
450 ieee80211_send_ADDBARsp(ieee, dst, pBA, ADDBA_STATUS_SUCCESS);
451
452 // End of procedure.
453 return 0;
454
455OnADDBAReq_Fail:
456 {
457 BA_RECORD BA;
458 BA.BaParamSet = *pBaParamSet;
459 BA.BaTimeoutValue = *pBaTimeoutVal;
460 BA.DialogToken = *pDialogToken;
461 BA.BaParamSet.field.BAPolicy = BA_POLICY_IMMEDIATE;
462 ieee80211_send_ADDBARsp(ieee, dst, &BA, rc);
463 return 0; //we send RSP out.
464 }
465
466}
467
468/********************************************************************************************************************
469 *function: RX ADDBARSP
470 * input: struct sk_buff * skb //incoming ADDBAReq skb.
471 * return: 0(pass), other(fail)
472 * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support.
473********************************************************************************************************************/
474int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb)
475{
476 struct ieee80211_hdr_3addr* rsp = NULL;
477 PBA_RECORD pPendingBA, pAdmittedBA;
478 PTX_TS_RECORD pTS = NULL;
479 u8* dst = NULL, *pDialogToken = NULL, *tag = NULL;
480 u16* pStatusCode = NULL, *pBaTimeoutVal = NULL;
481 PBA_PARAM_SET pBaParamSet = NULL;
482 u16 ReasonCode;
483
484 if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9)
485 {
486 IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BARSP(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9));
487 return -1;
488 }
489 rsp = ( struct ieee80211_hdr_3addr*)skb->data;
490 tag = (u8*)rsp;
491 dst = (u8*)(&rsp->addr2[0]);
492 tag += sizeof( struct ieee80211_hdr_3addr);
493 pDialogToken = tag + 2;
494 pStatusCode = (u16*)(tag + 3);
495 pBaParamSet = (PBA_PARAM_SET)(tag + 5);
496 pBaTimeoutVal = (u16*)(tag + 7);
497
498 // Check the capability
499 // Since we can always receive A-MPDU, we just check if it is under HT mode.
500 if( ieee->current_network.qos_data.active == 0 ||
501 ieee->pHTInfo->bCurrentHTSupport == false ||
502 ieee->pHTInfo->bCurrentAMPDUEnable == false )
503 {
504 IEEE80211_DEBUG(IEEE80211_DL_ERR, "reject to ADDBA_RSP as some capability is not ready(%d, %d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bCurrentAMPDUEnable);
505 ReasonCode = DELBA_REASON_UNKNOWN_BA;
506 goto OnADDBARsp_Reject;
507 }
508
509
510 //
511 // Search for related TS.
512 // If there is no TS found, we wil reject ADDBA Rsp by sending DELBA frame.
513 //
514 if (!GetTs(
515 ieee,
516 (PTS_COMMON_INFO*)(&pTS),
517 dst,
518 (u8)(pBaParamSet->field.TID),
519 TX_DIR,
520 false) )
521 {
522 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__);
523 ReasonCode = DELBA_REASON_UNKNOWN_BA;
524 goto OnADDBARsp_Reject;
525 }
526
527 pTS->bAddBaReqInProgress = false;
528 pPendingBA = &pTS->TxPendingBARecord;
529 pAdmittedBA = &pTS->TxAdmittedBARecord;
530
531
532 //
533 // Check if related BA is waiting for setup.
534 // If not, reject by sending DELBA frame.
535 //
536 if((pAdmittedBA->bValid==true))
537 {
538 // Since BA is already setup, we ignore all other ADDBA Response.
539 IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. Drop because already admit it! \n");
540 return -1;
541 }
542 else if((pPendingBA->bValid == false) ||(*pDialogToken != pPendingBA->DialogToken))
543 {
544 IEEE80211_DEBUG(IEEE80211_DL_ERR, "OnADDBARsp(): Recv ADDBA Rsp. BA invalid, DELBA! \n");
545 ReasonCode = DELBA_REASON_UNKNOWN_BA;
546 goto OnADDBARsp_Reject;
547 }
548 else
549 {
550 IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. BA is admitted! Status code:%X\n", *pStatusCode);
551 DeActivateBAEntry(ieee, pPendingBA);
552 }
553
554
555 if(*pStatusCode == ADDBA_STATUS_SUCCESS)
556 {
557 //
558 // Determine ADDBA Rsp content here.
559 // We can compare the value of BA parameter set that Peer returned and Self sent.
560 // If it is OK, then admitted. Or we can send DELBA to cancel BA mechanism.
561 //
562 if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED)
563 {
564 // Since this is a kind of ADDBA failed, we delay next ADDBA process.
565 pTS->bAddBaReqDelayed = true;
566 DeActivateBAEntry(ieee, pAdmittedBA);
567 ReasonCode = DELBA_REASON_END_BA;
568 goto OnADDBARsp_Reject;
569 }
570
571
572 //
573 // Admitted condition
574 //
575 pAdmittedBA->DialogToken = *pDialogToken;
576 pAdmittedBA->BaTimeoutValue = *pBaTimeoutVal;
577 pAdmittedBA->BaStartSeqCtrl = pPendingBA->BaStartSeqCtrl;
578 pAdmittedBA->BaParamSet = *pBaParamSet;
579 DeActivateBAEntry(ieee, pAdmittedBA);
580 ActivateBAEntry(ieee, pAdmittedBA, *pBaTimeoutVal);
581 }
582 else
583 {
584 // Delay next ADDBA process.
585 pTS->bAddBaReqDelayed = true;
586 }
587
588 // End of procedure
589 return 0;
590
591OnADDBARsp_Reject:
592 {
593 BA_RECORD BA;
594 BA.BaParamSet = *pBaParamSet;
595 ieee80211_send_DELBA(ieee, dst, &BA, TX_DIR, ReasonCode);
596 return 0;
597 }
598
599}
600
601/********************************************************************************************************************
602 *function: RX DELBA
603 * input: struct sk_buff * skb //incoming ADDBAReq skb.
604 * return: 0(pass), other(fail)
605 * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support.
606********************************************************************************************************************/
607int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb)
608{
609 struct ieee80211_hdr_3addr* delba = NULL;
610 PDELBA_PARAM_SET pDelBaParamSet = NULL;
611 u16* pReasonCode = NULL;
612 u8* dst = NULL;
613
614 if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 6)
615 {
616 IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in DELBA(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 6));
617 return -1;
618 }
619
620 if(ieee->current_network.qos_data.active == 0 ||
621 ieee->pHTInfo->bCurrentHTSupport == false )
622 {
623 IEEE80211_DEBUG(IEEE80211_DL_ERR, "received DELBA while QOS or HT is not supported(%d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport);
624 return -1;
625 }
626
627 IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len);
628 delba = ( struct ieee80211_hdr_3addr*)skb->data;
629 dst = (u8*)(&delba->addr2[0]);
630 delba += sizeof( struct ieee80211_hdr_3addr);
631 pDelBaParamSet = (PDELBA_PARAM_SET)(delba+2);
632 pReasonCode = (u16*)(delba+4);
633
634 if(pDelBaParamSet->field.Initiator == 1)
635 {
636 PRX_TS_RECORD pRxTs;
637
638 if( !GetTs(
639 ieee,
640 (PTS_COMMON_INFO*)&pRxTs,
641 dst,
642 (u8)pDelBaParamSet->field.TID,
643 RX_DIR,
644 false) )
645 {
646 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for RXTS in %s()\n", __FUNCTION__);
647 return -1;
648 }
649
650 RxTsDeleteBA(ieee, pRxTs);
651 }
652 else
653 {
654 PTX_TS_RECORD pTxTs;
655
656 if(!GetTs(
657 ieee,
658 (PTS_COMMON_INFO*)&pTxTs,
659 dst,
660 (u8)pDelBaParamSet->field.TID,
661 TX_DIR,
662 false) )
663 {
664 IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for TXTS in %s()\n", __FUNCTION__);
665 return -1;
666 }
667
668 pTxTs->bUsingBa = false;
669 pTxTs->bAddBaReqInProgress = false;
670 pTxTs->bAddBaReqDelayed = false;
671 del_timer_sync(&pTxTs->TsAddBaTimer);
672 //PlatformCancelTimer(Adapter, &pTxTs->TsAddBaTimer);
673 TxTsDeleteBA(ieee, pTxTs);
674 }
675 return 0;
676}
677
678//
679// ADDBA initiate. This can only be called by TX side.
680//
681void
682TsInitAddBA(
683 struct ieee80211_device* ieee,
684 PTX_TS_RECORD pTS,
685 u8 Policy,
686 u8 bOverwritePending
687 )
688{
689 PBA_RECORD pBA = &pTS->TxPendingBARecord;
690
691 if(pBA->bValid==true && bOverwritePending==false)
692 return;
693
694 // Set parameters to "Pending" variable set
695 DeActivateBAEntry(ieee, pBA);
696
697 pBA->DialogToken++; // DialogToken: Only keep the latest dialog token
698 pBA->BaParamSet.field.AMSDU_Support = 0; // Do not support A-MSDU with A-MPDU now!!
699 pBA->BaParamSet.field.BAPolicy = Policy; // Policy: Delayed or Immediate
700 pBA->BaParamSet.field.TID = pTS->TsCommonInfo.TSpec.f.TSInfo.field.ucTSID; // TID
701 // BufferSize: This need to be set according to A-MPDU vector
702 pBA->BaParamSet.field.BufferSize = 32; // BufferSize: This need to be set according to A-MPDU vector
703 pBA->BaTimeoutValue = 0; // Timeout value: Set 0 to disable Timer
704 pBA->BaStartSeqCtrl.field.SeqNum = (pTS->TxCurSeq + 3) % 4096; // Block Ack will start after 3 packets later.
705
706 ActivateBAEntry(ieee, pBA, BA_SETUP_TIMEOUT);
707
708 ieee80211_send_ADDBAReq(ieee, pTS->TsCommonInfo.Addr, pBA);
709}
710
711void
712TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect)
713{
714
715 if(TxRxSelect == TX_DIR)
716 {
717 PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)pTsCommonInfo;
718
719 if(TxTsDeleteBA(ieee, pTxTs))
720 ieee80211_send_DELBA(
721 ieee,
722 pTsCommonInfo->Addr,
723 (pTxTs->TxAdmittedBARecord.bValid)?(&pTxTs->TxAdmittedBARecord):(&pTxTs->TxPendingBARecord),
724 TxRxSelect,
725 DELBA_REASON_END_BA);
726 }
727 else if(TxRxSelect == RX_DIR)
728 {
729 PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)pTsCommonInfo;
730 if(RxTsDeleteBA(ieee, pRxTs))
731 ieee80211_send_DELBA(
732 ieee,
733 pTsCommonInfo->Addr,
734 &pRxTs->RxAdmittedBARecord,
735 TxRxSelect,
736 DELBA_REASON_END_BA );
737 }
738}
739/********************************************************************************************************************
740 *function: BA setup timer
741 * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer
742 * return: NULL
743 * notice:
744********************************************************************************************************************/
745void BaSetupTimeOut(unsigned long data)
746{
747 PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data;
748
749 pTxTs->bAddBaReqInProgress = false;
750 pTxTs->bAddBaReqDelayed = true;
751 pTxTs->TxPendingBARecord.bValid = false;
752}
753
754void TxBaInactTimeout(unsigned long data)
755{
756 PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data;
757 struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[pTxTs->num]);
758 TxTsDeleteBA(ieee, pTxTs);
759 ieee80211_send_DELBA(
760 ieee,
761 pTxTs->TsCommonInfo.Addr,
762 &pTxTs->TxAdmittedBARecord,
763 TX_DIR,
764 DELBA_REASON_TIMEOUT);
765}
766
767void RxBaInactTimeout(unsigned long data)
768{
769 PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data;
770 struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]);
771
772 RxTsDeleteBA(ieee, pRxTs);
773 ieee80211_send_DELBA(
774 ieee,
775 pRxTs->TsCommonInfo.Addr,
776 &pRxTs->RxAdmittedBARecord,
777 RX_DIR,
778 DELBA_REASON_TIMEOUT);
779 return ;
780}
781
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h
new file mode 100644
index 00000000000..16a7462d7df
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h
@@ -0,0 +1,517 @@
1#ifndef _RTL819XU_HTTYPE_H_
2#define _RTL819XU_HTTYPE_H_
3
4//------------------------------------------------------------
5// The HT Capability element is present in beacons, association request,
6// reassociation request and probe response frames
7//------------------------------------------------------------
8
9//
10// Operation mode value
11//
12#define HT_OPMODE_NO_PROTECT 0
13#define HT_OPMODE_OPTIONAL 1
14#define HT_OPMODE_40MHZ_PROTECT 2
15#define HT_OPMODE_MIXED 3
16
17//
18// MIMO Power Save Setings
19//
20#define MIMO_PS_STATIC 0
21#define MIMO_PS_DYNAMIC 1
22#define MIMO_PS_NOLIMIT 3
23
24
25//
26// There should be 128 bits to cover all of the MCS rates. However, since
27// 8190 does not support too much rates, one integer is quite enough.
28//
29
30#define sHTCLng 4
31
32
33#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
34#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
35#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
36
37
38typedef enum _HT_MCS_RATE{
39 HT_MCS0 = 0x00000001,
40 HT_MCS1 = 0x00000002,
41 HT_MCS2 = 0x00000004,
42 HT_MCS3 = 0x00000008,
43 HT_MCS4 = 0x00000010,
44 HT_MCS5 = 0x00000020,
45 HT_MCS6 = 0x00000040,
46 HT_MCS7 = 0x00000080,
47 HT_MCS8 = 0x00000100,
48 HT_MCS9 = 0x00000200,
49 HT_MCS10 = 0x00000400,
50 HT_MCS11 = 0x00000800,
51 HT_MCS12 = 0x00001000,
52 HT_MCS13 = 0x00002000,
53 HT_MCS14 = 0x00004000,
54 HT_MCS15 = 0x00008000,
55 // Do not define MCS32 here although 8190 support MCS32
56}HT_MCS_RATE,*PHT_MCS_RATE;
57
58//
59// Represent Channel Width in HT Capabilities
60//
61typedef enum _HT_CHANNEL_WIDTH{
62 HT_CHANNEL_WIDTH_20 = 0,
63 HT_CHANNEL_WIDTH_20_40 = 1,
64}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
65
66//
67// Represent Extention Channel Offset in HT Capabilities
68// This is available only in 40Mhz mode.
69//
70typedef enum _HT_EXTCHNL_OFFSET{
71 HT_EXTCHNL_OFFSET_NO_EXT = 0,
72 HT_EXTCHNL_OFFSET_UPPER = 1,
73 HT_EXTCHNL_OFFSET_NO_DEF = 2,
74 HT_EXTCHNL_OFFSET_LOWER = 3,
75}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
76
77typedef enum _CHNLOP{
78 CHNLOP_NONE = 0, // No Action now
79 CHNLOP_SCAN = 1, // Scan in progress
80 CHNLOP_SWBW = 2, // Bandwidth switching in progress
81 CHNLOP_SWCHNL = 3, // Software Channel switching in progress
82} CHNLOP, *PCHNLOP;
83
84// Determine if the Channel Operation is in progress
85#define CHHLOP_IN_PROGRESS(_pHTInfo) \
86 ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE
87
88/*
89typedef union _HT_CAPABILITY{
90 u16 ShortData;
91 u8 CharData[2];
92 struct
93 {
94 u16 AdvCoding:1;
95 u16 ChlWidth:1;
96 u16 MimoPwrSave:2;
97 u16 GreenField:1;
98 u16 ShortGI20Mhz:1;
99 u16 ShortGI40Mhz:1;
100 u16 STBC:1;
101 u16 BeamForm:1;
102 u16 DelayBA:1;
103 u16 MaxAMSDUSize:1;
104 u16 DssCCk:1;
105 u16 PSMP:1;
106 u16 Rsvd:3;
107 }Field;
108}HT_CAPABILITY, *PHT_CAPABILITY;
109
110typedef union _HT_CAPABILITY_MACPARA{
111 u8 ShortData;
112 u8 CharData[1];
113 struct
114 {
115 u8 MaxRxAMPDU:2;
116 u8 MPDUDensity:2;
117 u8 Rsvd:4;
118 }Field;
119}HT_CAPABILITY_MACPARA, *PHT_CAPABILITY_MACPARA;
120*/
121
122typedef enum _HT_ACTION{
123 ACT_RECOMMAND_WIDTH = 0,
124 ACT_MIMO_PWR_SAVE = 1,
125 ACT_PSMP = 2,
126 ACT_SET_PCO_PHASE = 3,
127 ACT_MIMO_CHL_MEASURE = 4,
128 ACT_RECIPROCITY_CORRECT = 5,
129 ACT_MIMO_CSI_MATRICS = 6,
130 ACT_MIMO_NOCOMPR_STEER = 7,
131 ACT_MIMO_COMPR_STEER = 8,
132 ACT_ANTENNA_SELECT = 9,
133} HT_ACTION, *PHT_ACTION;
134
135
136/* 2007/06/07 MH Define sub-carrier mode for 40MHZ. */
137typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
138 SC_MODE_DUPLICATE = 0,
139 SC_MODE_LOWER = 1,
140 SC_MODE_UPPER = 2,
141 SC_MODE_FULL40MHZ = 3,
142}HT_BW40_SC_E;
143
144typedef struct _HT_CAPABILITY_ELE{
145
146 //HT capability info
147 u8 AdvCoding:1;
148 u8 ChlWidth:1;
149 u8 MimoPwrSave:2;
150 u8 GreenField:1;
151 u8 ShortGI20Mhz:1;
152 u8 ShortGI40Mhz:1;
153 u8 TxSTBC:1;
154 u8 RxSTBC:2;
155 u8 DelayBA:1;
156 u8 MaxAMSDUSize:1;
157 u8 DssCCk:1;
158 u8 PSMP:1;
159 u8 Rsvd1:1;
160 u8 LSigTxopProtect:1;
161
162 //MAC HT parameters info
163 u8 MaxRxAMPDUFactor:2;
164 u8 MPDUDensity:3;
165 u8 Rsvd2:3;
166
167 //Supported MCS set
168 u8 MCS[16];
169
170
171 //Extended HT Capability Info
172 u16 ExtHTCapInfo;
173
174 //TXBF Capabilities
175 u8 TxBFCap[4];
176
177 //Antenna Selection Capabilities
178 u8 ASCap;
179
180} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE;
181
182//------------------------------------------------------------
183// The HT Information element is present in beacons
184// Only AP is required to include this element
185//------------------------------------------------------------
186
187typedef struct _HT_INFORMATION_ELE{
188 u8 ControlChl;
189
190 u8 ExtChlOffset:2;
191 u8 RecommemdedTxWidth:1;
192 u8 RIFS:1;
193 u8 PSMPAccessOnly:1;
194 u8 SrvIntGranularity:3;
195
196 u8 OptMode:2;
197 u8 NonGFDevPresent:1;
198 u8 Revd1:5;
199 u8 Revd2:8;
200
201 u8 Rsvd3:6;
202 u8 DualBeacon:1;
203 u8 DualCTSProtect:1;
204
205 u8 SecondaryBeacon:1;
206 u8 LSigTxopProtectFull:1;
207 u8 PcoActive:1;
208 u8 PcoPhase:1;
209 u8 Rsvd4:4;
210
211 u8 BasicMSC[16];
212} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE;
213
214//
215// MIMO Power Save control field.
216// This is appear in MIMO Power Save Action Frame
217//
218typedef struct _MIMOPS_CTRL{
219 u8 MimoPsEnable:1;
220 u8 MimoPsMode:1;
221 u8 Reserved:6;
222} MIMOPS_CTRL, *PMIMOPS_CTRL;
223
224typedef enum _HT_SPEC_VER{
225 HT_SPEC_VER_IEEE = 0,
226 HT_SPEC_VER_EWC = 1,
227}HT_SPEC_VER, *PHT_SPEC_VER;
228
229typedef enum _HT_AGGRE_MODE_E{
230 HT_AGG_AUTO = 0,
231 HT_AGG_FORCE_ENABLE = 1,
232 HT_AGG_FORCE_DISABLE = 2,
233}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
234
235//------------------------------------------------------------
236// The Data structure is used to keep HT related variables when card is
237// configured as non-AP STA mode. **Note** Current_xxx should be set
238// to default value in HTInitializeHTInfo()
239//------------------------------------------------------------
240
241typedef struct _RT_HIGH_THROUGHPUT{
242 u8 bEnableHT;
243 u8 bCurrentHTSupport;
244
245 u8 bRegBW40MHz; // Tx 40MHz channel capablity
246 u8 bCurBW40MHz; // Tx 40MHz channel capability
247
248 u8 bRegShortGI40MHz; // Tx Short GI for 40Mhz
249 u8 bCurShortGI40MHz; // Tx Short GI for 40MHz
250
251 u8 bRegShortGI20MHz; // Tx Short GI for 20MHz
252 u8 bCurShortGI20MHz; // Tx Short GI for 20MHz
253
254 u8 bRegSuppCCK; // Tx CCK rate capability
255 u8 bCurSuppCCK; // Tx CCK rate capability
256
257 // 802.11n spec version for "peer"
258 HT_SPEC_VER ePeerHTSpecVer;
259
260
261 // HT related information for "Self"
262 HT_CAPABILITY_ELE SelfHTCap; // This is HT cap element sent to peer STA, which also indicate HT Rx capabilities.
263 HT_INFORMATION_ELE SelfHTInfo; // This is HT info element sent to peer STA, which also indicate HT Rx capabilities.
264
265 // HT related information for "Peer"
266 u8 PeerHTCapBuf[32];
267 u8 PeerHTInfoBuf[32];
268
269
270 // A-MSDU related
271 u8 bAMSDU_Support; // This indicates Tx A-MSDU capability
272 u16 nAMSDU_MaxSize; // This indicates Tx A-MSDU capability
273 u8 bCurrent_AMSDU_Support; // This indicates Tx A-MSDU capability
274 u16 nCurrent_AMSDU_MaxSize; // This indicates Tx A-MSDU capability
275
276
277 // AMPDU related <2006.08.10 Emily>
278 u8 bAMPDUEnable; // This indicate Tx A-MPDU capability
279 u8 bCurrentAMPDUEnable; // This indicate Tx A-MPDU capability
280 u8 AMPDU_Factor; // This indicate Tx A-MPDU capability
281 u8 CurrentAMPDUFactor; // This indicate Tx A-MPDU capability
282 u8 MPDU_Density; // This indicate Tx A-MPDU capability
283 u8 CurrentMPDUDensity; // This indicate Tx A-MPDU capability
284
285 // Forced A-MPDU enable
286 HT_AGGRE_MODE_E ForcedAMPDUMode;
287 u8 ForcedAMPDUFactor;
288 u8 ForcedMPDUDensity;
289
290 // Forced A-MSDU enable
291 HT_AGGRE_MODE_E ForcedAMSDUMode;
292 u16 ForcedAMSDUMaxSize;
293
294 u8 bForcedShortGI;
295
296 u8 CurrentOpMode;
297
298 // MIMO PS related
299 u8 SelfMimoPs;
300 u8 PeerMimoPs;
301
302 // 40MHz Channel Offset settings.
303 HT_EXTCHNL_OFFSET CurSTAExtChnlOffset;
304 u8 bCurTxBW40MHz; // If we use 40 MHz to Tx
305 u8 PeerBandwidth;
306
307 // For Bandwidth Switching
308 u8 bSwBwInProgress;
309 CHNLOP ChnlOp; // software switching channel in progress. By Bruce, 2008-02-15.
310 u8 SwBwStep;
311 //struct timer_list SwBwTimer; //moved to ieee80211_device. as timer_list need include some header file here.
312
313 // For Realtek proprietary A-MPDU factor for aggregation
314 u8 bRegRT2RTAggregation;
315 u8 RT2RT_HT_Mode;
316 u8 bCurrentRT2RTAggregation;
317 u8 bCurrentRT2RTLongSlotTime;
318 u8 szRT2RTAggBuffer[10];
319
320 // Rx Reorder control
321 u8 bRegRxReorderEnable;
322 u8 bCurRxReorderEnable;
323 u8 RxReorderWinSize;
324 u8 RxReorderPendingTime;
325 u16 RxReorderDropCounter;
326
327#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
328 u8 UsbTxAggrNum;
329#endif
330#ifdef USB_RX_AGGREGATION_SUPPORT
331 u8 UsbRxFwAggrEn;
332 u8 UsbRxFwAggrPageNum;
333 u8 UsbRxFwAggrPacketNum;
334 u8 UsbRxFwAggrTimeout;
335#endif
336
337 // Add for Broadcom(Linksys) IOT. Joseph
338 u8 bIsPeerBcm;
339
340 // For IOT issue.
341 u8 IOTPeer;
342 u32 IOTAction;
343 u8 IOTRaFunc;
344} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT;
345
346
347//------------------------------------------------------------
348// The Data structure is used to keep HT related variable for "each Sta"
349// when card is configured as "AP mode"
350//------------------------------------------------------------
351
352typedef struct _RT_HTINFO_STA_ENTRY{
353 u8 bEnableHT;
354
355 u8 bSupportCck;
356
357 u16 AMSDU_MaxSize;
358
359 u8 AMPDU_Factor;
360 u8 MPDU_Density;
361
362 u8 HTHighestOperaRate;
363
364 u8 bBw40MHz;
365
366 u8 MimoPs;
367
368 u8 McsRateSet[16];
369
370
371}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY;
372
373
374
375
376
377//------------------------------------------------------------
378// The Data structure is used to keep HT related variable for "each AP"
379// when card is configured as "STA mode"
380//------------------------------------------------------------
381
382typedef struct _BSS_HT{
383
384 u8 bdSupportHT;
385
386 // HT related elements
387 u8 bdHTCapBuf[32];
388 u16 bdHTCapLen;
389 u8 bdHTInfoBuf[32];
390 u16 bdHTInfoLen;
391
392 HT_SPEC_VER bdHTSpecVer;
393 //HT_CAPABILITY_ELE bdHTCapEle;
394 //HT_INFORMATION_ELE bdHTInfoEle;
395
396 u8 bdRT2RTAggregation;
397 u8 bdRT2RTLongSlotTime;
398 u8 RT2RT_HT_Mode;
399 bool bdHT1R;
400} __attribute__ ((packed)) BSS_HT, *PBSS_HT;
401
402typedef struct _MIMO_RSSI{
403 u32 EnableAntenna;
404 u32 AntennaA;
405 u32 AntennaB;
406 u32 AntennaC;
407 u32 AntennaD;
408 u32 Average;
409}MIMO_RSSI, *PMIMO_RSSI;
410
411typedef struct _MIMO_EVM{
412 u32 EVM1;
413 u32 EVM2;
414}MIMO_EVM, *PMIMO_EVM;
415
416typedef struct _FALSE_ALARM_STATISTICS{
417 u32 Cnt_Parity_Fail;
418 u32 Cnt_Rate_Illegal;
419 u32 Cnt_Crc8_fail;
420 u32 Cnt_all;
421}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
422
423
424extern u8 MCS_FILTER_ALL[16];
425extern u8 MCS_FILTER_1SS[16];
426
427/* 2007/07/11 MH Modify the macro. Becaus STA may link with a N-AP. If we set
428 STA in A/B/G mode and AP is still in N mode. The macro will be wrong. We have
429 to add a macro to judge wireless mode. */
430#define PICK_RATE(_nLegacyRate, _nMcsRate) \
431 (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
432/* 2007/07/12 MH We only define legacy and HT wireless mode now. */
433#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
434
435#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
436 ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
437 (LegacyRate):\
438 (PICK_RATE(LegacyRate, HTRate))
439
440
441
442// MCS Bw 40 {1~7, 12~15,32}
443#define RATE_ADPT_1SS_MASK 0xFF
444#define RATE_ADPT_2SS_MASK 0xF0 //Skip MCS8~11 because mcs7 > mcs6, 9, 10, 11. 2007.01.16 by Emily
445#define RATE_ADPT_MCS32_MASK 0x01
446
447#define IS_11N_MCS_RATE(rate) (rate&0x80)
448
449typedef enum _HT_AGGRE_SIZE{
450 HT_AGG_SIZE_8K = 0,
451 HT_AGG_SIZE_16K = 1,
452 HT_AGG_SIZE_32K = 2,
453 HT_AGG_SIZE_64K = 3,
454}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
455
456/* Indicate different AP vendor for IOT issue */
457typedef enum _HT_IOT_PEER
458{
459 HT_IOT_PEER_UNKNOWN = 0,
460 HT_IOT_PEER_REALTEK = 1,
461 HT_IOT_PEER_REALTEK_92SE = 2,
462 HT_IOT_PEER_BROADCOM = 3,
463 HT_IOT_PEER_RALINK = 4,
464 HT_IOT_PEER_ATHEROS = 5,
465 HT_IOT_PEER_CISCO= 6,
466 HT_IOT_PEER_MARVELL=7,
467 HT_IOT_PEER_92U_SOFTAP = 8,
468 HT_IOT_PEER_SELF_SOFTAP = 9,
469 HT_IOT_PEER_MAX = 10,
470}HT_IOT_PEER_E, *PHTIOT_PEER_E;
471
472//
473// IOT Action for different AP
474//
475typedef enum _HT_IOT_ACTION{
476 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
477 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
478 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
479 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
480 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
481 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
482 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
483 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
484 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
485 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
486 HT_IOT_ACT_FORCED_RTS = 0x00000400,
487 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
488 HT_IOT_ACT_MID_HIGHPOWER = 0x00001000,
489 HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00002000,
490 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00004000,
491 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00008000,
492
493 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
494 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
495 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
496 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
497 HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
498 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
499}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
500
501typedef enum _HT_IOT_RAFUNC{
502 HT_IOT_RAFUNC_PEER_1R = 0x01,
503 HT_IOT_RAFUNC_TX_AMSDU = 0x02,
504 HT_IOT_RAFUNC_DISABLE_ALL = 0x80,
505}HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
506
507typedef enum _RT_HT_CAP{
508 RT_HT_CAP_USE_TURBO_AGGR = 0x01,
509 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
510 RT_HT_CAP_USE_AMPDU = 0x04,
511 RT_HT_CAP_USE_WOW = 0x8,
512 RT_HT_CAP_USE_SOFTAP = 0x10,
513 RT_HT_CAP_USE_92SE = 0x20,
514}RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;
515
516#endif //_RTL819XU_HTTYPE_H_
517
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c
new file mode 100644
index 00000000000..f357085f664
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c
@@ -0,0 +1,2037 @@
1
2//As this function is mainly ported from Windows driver, so leave the name little changed. If any confusion caused, tell me. Created by WB. 2008.05.08
3#include "ieee80211.h"
4#include "rtl819x_HT.h"
5u8 MCS_FILTER_ALL[16] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
6
7u8 MCS_FILTER_1SS[16] = {0xff, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
8
9u16 MCS_DATA_RATE[2][2][77] =
10 { { {13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78 ,104, 156, 208, 234, 260,
11 39, 78, 117, 234, 312, 351, 390, 52, 104, 156, 208, 312, 416, 468, 520,
12 0, 78, 104, 130, 117, 156, 195, 104, 130, 130, 156, 182, 182, 208, 156, 195,
13 195, 234, 273, 273, 312, 130, 156, 181, 156, 181, 208, 234, 208, 234, 260, 260,
14 286, 195, 234, 273, 234, 273, 312, 351, 312, 351, 390, 390, 429}, // Long GI, 20MHz
15 {14, 29, 43, 58, 87, 116, 130, 144, 29, 58, 87, 116, 173, 231, 260, 289,
16 43, 87, 130, 173, 260, 347, 390, 433, 58, 116, 173, 231, 347, 462, 520, 578,
17 0, 87, 116, 144, 130, 173, 217, 116, 144, 144, 173, 202, 202, 231, 173, 217,
18 217, 260, 303, 303, 347, 144, 173, 202, 173, 202, 231, 260, 231, 260, 289, 289,
19 318, 217, 260, 303, 260, 303, 347, 390, 347, 390, 433, 433, 477} }, // Short GI, 20MHz
20 { {27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540,
21 81, 162, 243, 324, 486, 648, 729, 810, 108, 216, 324, 432, 648, 864, 972, 1080,
22 12, 162, 216, 270, 243, 324, 405, 216, 270, 270, 324, 378, 378, 432, 324, 405,
23 405, 486, 567, 567, 648, 270, 324, 378, 324, 378, 432, 486, 432, 486, 540, 540,
24 594, 405, 486, 567, 486, 567, 648, 729, 648, 729, 810, 810, 891}, // Long GI, 40MHz
25 {30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600,
26 90, 180, 270, 360, 540, 720, 810, 900, 120, 240, 360, 480, 720, 960, 1080, 1200,
27 13, 180, 240, 300, 270, 360, 450, 240, 300, 300, 360, 420, 420, 480, 360, 450,
28 450, 540, 630, 630, 720, 300, 360, 420, 360, 420, 480, 540, 480, 540, 600, 600,
29 660, 450, 540, 630, 540, 630, 720, 810, 720, 810, 900, 900, 990} } // Short GI, 40MHz
30 };
31
32static u8 UNKNOWN_BORADCOM[3] = {0x00, 0x14, 0xbf};
33static u8 LINKSYSWRT330_LINKSYSWRT300_BROADCOM[3] = {0x00, 0x1a, 0x70};
34static u8 LINKSYSWRT350_LINKSYSWRT150_BROADCOM[3] = {0x00, 0x1d, 0x7e};
35static u8 NETGEAR834Bv2_BROADCOM[3] = {0x00, 0x1b, 0x2f};
36static u8 BELKINF5D8233V1_RALINK[3] = {0x00, 0x17, 0x3f}; //cosa 03202008
37static u8 BELKINF5D82334V3_RALINK[3] = {0x00, 0x1c, 0xdf};
38static u8 PCI_RALINK[3] = {0x00, 0x90, 0xcc};
39static u8 EDIMAX_RALINK[3] = {0x00, 0x0e, 0x2e};
40static u8 AIRLINK_RALINK[3] = {0x00, 0x18, 0x02};
41static u8 DLINK_ATHEROS_1[3] = {0x00, 0x1c, 0xf0};
42static u8 DLINK_ATHEROS_2[3] = {0x00, 0x21, 0x91};
43static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94};
44static u8 LINKSYS_MARVELL_4400N[3] = {0x00, 0x14, 0xa4};
45// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the
46// code in other place??
47//static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96};
48/********************************************************************************************************************
49 *function: This function update default settings in pHTInfo structure
50 * input: PRT_HIGH_THROUGHPUT pHTInfo
51 * output: none
52 * return: none
53 * notice: These value need be modified if any changes.
54 * *****************************************************************************************************************/
55void HTUpdateDefaultSetting(struct ieee80211_device* ieee)
56{
57 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
58 //const typeof( ((struct ieee80211_device *)0)->pHTInfo ) *__mptr = &pHTInfo;
59
60 //printk("pHTinfo:%p, &pHTinfo:%p, mptr:%p, offsetof:%x\n", pHTInfo, &pHTInfo, __mptr, offsetof(struct ieee80211_device, pHTInfo));
61 //printk("===>ieee:%p,\n", ieee);
62 // ShortGI support
63 pHTInfo->bRegShortGI20MHz= 1;
64 pHTInfo->bRegShortGI40MHz= 1;
65
66 // 40MHz channel support
67 pHTInfo->bRegBW40MHz = 1;
68
69 // CCK rate support in 40MHz channel
70 if(pHTInfo->bRegBW40MHz)
71 pHTInfo->bRegSuppCCK = 1;
72 else
73 pHTInfo->bRegSuppCCK = true;
74
75 // AMSDU related
76 pHTInfo->nAMSDU_MaxSize = 7935UL;
77 pHTInfo->bAMSDU_Support = 0;
78
79 // AMPDU related
80 pHTInfo->bAMPDUEnable = 1; //YJ,test,090311
81 pHTInfo->AMPDU_Factor = 2; //// 0: 2n13(8K), 1:2n14(16K), 2:2n15(32K), 3:2n16(64k)
82 pHTInfo->MPDU_Density = 0;// 0: No restriction, 1: 1/8usec, 2: 1/4usec, 3: 1/2usec, 4: 1usec, 5: 2usec, 6: 4usec, 7:8usec
83
84 // MIMO Power Save
85 pHTInfo->SelfMimoPs = 3;// 0: Static Mimo Ps, 1: Dynamic Mimo Ps, 3: No Limitation, 2: Reserved(Set to 3 automatically.)
86 if(pHTInfo->SelfMimoPs == 2)
87 pHTInfo->SelfMimoPs = 3;
88 // 8190 only. Assign rate operation mode to firmware
89 ieee->bTxDisableRateFallBack = 0;
90 ieee->bTxUseDriverAssingedRate = 0;
91
92#ifdef TO_DO_LIST
93 // 8190 only. Assign duration operation mode to firmware
94 pMgntInfo->bTxEnableFwCalcDur = (BOOLEAN)pNdisCommon->bRegTxEnableFwCalcDur;
95#endif
96 // 8190 only, Realtek proprietary aggregation mode
97 // Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others
98 pHTInfo->bRegRT2RTAggregation = 1;//0: Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others
99
100 // For Rx Reorder Control
101 pHTInfo->bRegRxReorderEnable = 1;//YJ,test,090311
102 pHTInfo->RxReorderWinSize = 64;
103 pHTInfo->RxReorderPendingTime = 30;
104
105#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
106 pHTInfo->UsbTxAggrNum = 4;
107#endif
108#ifdef USB_RX_AGGREGATION_SUPPORT
109#ifdef RTL8192SU
110 pHTInfo->UsbRxFwAggrEn = 1;
111 pHTInfo->UsbRxFwAggrPageNum = 16;
112 pHTInfo->UsbRxFwAggrPacketNum = 8;
113 pHTInfo->UsbRxFwAggrTimeout = 4; ////usb rx FW aggregation timeout threshold.It's in units of 64us
114 // For page size of receive packet buffer.
115 pHTInfo->UsbRxPageSize= 128;
116#else
117 pHTInfo->UsbRxFwAggrEn = 1;
118 pHTInfo->UsbRxFwAggrPageNum = 24;
119 pHTInfo->UsbRxFwAggrPacketNum = 8;
120 pHTInfo->UsbRxFwAggrTimeout = 16; ////usb rx FW aggregation timeout threshold.It's in units of 64us
121#endif
122#endif
123
124
125}
126/********************************************************************************************************************
127 *function: This function print out each field on HT capability IE mainly from (Beacon/ProbeRsp/AssocReq)
128 * input: u8* CapIE //Capability IE to be printed out
129 * u8* TitleString //mainly print out caller function
130 * output: none
131 * return: none
132 * notice: Driver should not print out this message by default.
133 * *****************************************************************************************************************/
134void HTDebugHTCapability(u8* CapIE, u8* TitleString )
135{
136
137 static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily
138 PHT_CAPABILITY_ELE pCapELE;
139
140 if(!memcmp(CapIE, EWC11NHTCap, sizeof(EWC11NHTCap)))
141 {
142 //EWC IE
143 IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__);
144 pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[4]);
145 }else
146 pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[0]);
147
148 IEEE80211_DEBUG(IEEE80211_DL_HT, "<Log HT Capability>. Called by %s\n", TitleString );
149
150 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupported Channel Width = %s\n", (pCapELE->ChlWidth)?"20MHz": "20/40MHz");
151 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 20M = %s\n", (pCapELE->ShortGI20Mhz)?"YES": "NO");
152 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 40M = %s\n", (pCapELE->ShortGI40Mhz)?"YES": "NO");
153 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport TX STBC = %s\n", (pCapELE->TxSTBC)?"YES": "NO");
154 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMSDU Size = %s\n", (pCapELE->MaxAMSDUSize)?"3839": "7935");
155 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport CCK in 20/40 mode = %s\n", (pCapELE->DssCCk)?"YES": "NO");
156 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMPDU Factor = %d\n", pCapELE->MaxRxAMPDUFactor);
157 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMPDU Density = %d\n", pCapELE->MPDUDensity);
158 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMCS Rate Set = [%x][%x][%x][%x][%x]\n", pCapELE->MCS[0],\
159 pCapELE->MCS[1], pCapELE->MCS[2], pCapELE->MCS[3], pCapELE->MCS[4]);
160 return;
161
162}
163/********************************************************************************************************************
164 *function: This function print out each field on HT Information IE mainly from (Beacon/ProbeRsp)
165 * input: u8* InfoIE //Capability IE to be printed out
166 * u8* TitleString //mainly print out caller function
167 * output: none
168 * return: none
169 * notice: Driver should not print out this message by default.
170 * *****************************************************************************************************************/
171void HTDebugHTInfo(u8* InfoIE, u8* TitleString)
172{
173
174 static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily
175 PHT_INFORMATION_ELE pHTInfoEle;
176
177 if(!memcmp(InfoIE, EWC11NHTInfo, sizeof(EWC11NHTInfo)))
178 {
179 // Not EWC IE
180 IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__);
181 pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[4]);
182 }else
183 pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[0]);
184
185
186 IEEE80211_DEBUG(IEEE80211_DL_HT, "<Log HT Information Element>. Called by %s\n", TitleString);
187
188 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tPrimary channel = %d\n", pHTInfoEle->ControlChl);
189 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSenondary channel =");
190 switch(pHTInfoEle->ExtChlOffset)
191 {
192 case 0:
193 IEEE80211_DEBUG(IEEE80211_DL_HT, "Not Present\n");
194 break;
195 case 1:
196 IEEE80211_DEBUG(IEEE80211_DL_HT, "Upper channel\n");
197 break;
198 case 2:
199 IEEE80211_DEBUG(IEEE80211_DL_HT, "Reserved. Eooro!!!\n");
200 break;
201 case 3:
202 IEEE80211_DEBUG(IEEE80211_DL_HT, "Lower Channel\n");
203 break;
204 }
205 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tRecommended channel width = %s\n", (pHTInfoEle->RecommemdedTxWidth)?"20Mhz": "40Mhz");
206
207 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tOperation mode for protection = ");
208 switch(pHTInfoEle->OptMode)
209 {
210 case 0:
211 IEEE80211_DEBUG(IEEE80211_DL_HT, "No Protection\n");
212 break;
213 case 1:
214 IEEE80211_DEBUG(IEEE80211_DL_HT, "HT non-member protection mode\n");
215 break;
216 case 2:
217 IEEE80211_DEBUG(IEEE80211_DL_HT, "Suggest to open protection\n");
218 break;
219 case 3:
220 IEEE80211_DEBUG(IEEE80211_DL_HT, "HT mixed mode\n");
221 break;
222 }
223
224 IEEE80211_DEBUG(IEEE80211_DL_HT, "\tBasic MCS Rate Set = [%x][%x][%x][%x][%x]\n", pHTInfoEle->BasicMSC[0],\
225 pHTInfoEle->BasicMSC[1], pHTInfoEle->BasicMSC[2], pHTInfoEle->BasicMSC[3], pHTInfoEle->BasicMSC[4]);
226 return;
227}
228
229/*
230* Return: true if station in half n mode and AP supports 40 bw
231*/
232bool IsHTHalfNmode40Bandwidth(struct ieee80211_device* ieee)
233{
234 bool retValue = false;
235 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
236
237 if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode
238 retValue = false;
239 else if(pHTInfo->bRegBW40MHz == false) // station supports 40 bw
240 retValue = false;
241 else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode
242 retValue = false;
243 else if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ChlWidth) // ap support 40 bw
244 retValue = true;
245 else
246 retValue = false;
247
248 return retValue;
249}
250
251bool IsHTHalfNmodeSGI(struct ieee80211_device* ieee, bool is40MHz)
252{
253 bool retValue = false;
254 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
255
256 if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode
257 retValue = false;
258 else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode
259 retValue = false;
260 else if(is40MHz) // ap support 40 bw
261 {
262 if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI40Mhz) // ap support 40 bw short GI
263 retValue = true;
264 else
265 retValue = false;
266 }
267 else
268 {
269 if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI20Mhz) // ap support 40 bw short GI
270 retValue = true;
271 else
272 retValue = false;
273 }
274
275 return retValue;
276}
277
278u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate)
279{
280
281 u8 is40MHz;
282 u8 isShortGI;
283
284 is40MHz = (IsHTHalfNmode40Bandwidth(ieee))?1:0;
285 isShortGI = (IsHTHalfNmodeSGI(ieee, is40MHz))? 1:0;
286
287 return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)];
288}
289
290
291u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate)
292{
293 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
294
295 u8 is40MHz = (pHTInfo->bCurBW40MHz)?1:0;
296 u8 isShortGI = (pHTInfo->bCurBW40MHz)?
297 ((pHTInfo->bCurShortGI40MHz)?1:0):
298 ((pHTInfo->bCurShortGI20MHz)?1:0);
299 return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)];
300}
301
302/********************************************************************************************************************
303 *function: This function returns current datarate.
304 * input: struct ieee80211_device* ieee
305 * u8 nDataRate
306 * output: none
307 * return: tx rate
308 * notice: quite unsure about how to use this function //wb
309 * *****************************************************************************************************************/
310u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate)
311{
312 //PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
313 u16 CCKOFDMRate[12] = {0x02 , 0x04 , 0x0b , 0x16 , 0x0c , 0x12 , 0x18 , 0x24 , 0x30 , 0x48 , 0x60 , 0x6c};
314 u8 is40MHz = 0;
315 u8 isShortGI = 0;
316
317 if(nDataRate < 12)
318 {
319 return CCKOFDMRate[nDataRate];
320 }
321 else
322 {
323 if (nDataRate >= 0x10 && nDataRate <= 0x1f)//if(nDataRate > 11 && nDataRate < 28 )
324 {
325 is40MHz = 0;
326 isShortGI = 0;
327
328 // nDataRate = nDataRate - 12;
329 }
330 else if(nDataRate >=0x20 && nDataRate <= 0x2f ) //(27, 44)
331 {
332 is40MHz = 1;
333 isShortGI = 0;
334
335 //nDataRate = nDataRate - 28;
336 }
337 else if(nDataRate >= 0x30 && nDataRate <= 0x3f ) //(43, 60)
338 {
339 is40MHz = 0;
340 isShortGI = 1;
341
342 //nDataRate = nDataRate - 44;
343 }
344 else if(nDataRate >= 0x40 && nDataRate <= 0x4f ) //(59, 76)
345 {
346 is40MHz = 1;
347 isShortGI = 1;
348
349 //nDataRate = nDataRate - 60;
350 }
351 return MCS_DATA_RATE[is40MHz][isShortGI][nDataRate&0xf];
352 }
353}
354
355
356
357bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee)
358{
359 bool retValue = false;
360 struct ieee80211_network* net = &ieee->current_network;
361#if 0
362 if(pMgntInfo->bHalfNMode == false)
363 retValue = false;
364 else
365#endif
366 if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) ||
367 (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) ||
368 (memcmp(net->bssid, PCI_RALINK, 3)==0) ||
369 (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) ||
370 (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) ||
371 (net->ralink_cap_exist))
372 retValue = true;
373 else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) ||
374 (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)||
375 (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)||
376 (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ||
377 (net->broadcom_cap_exist))
378 retValue = true;
379 else if(net->bssht.bdRT2RTAggregation)
380 retValue = true;
381 else
382 retValue = false;
383
384 return retValue;
385}
386
387/********************************************************************************************************************
388 *function: This function returns peer IOT.
389 * input: struct ieee80211_device* ieee
390 * output: none
391 * return:
392 * notice:
393 * *****************************************************************************************************************/
394void HTIOTPeerDetermine(struct ieee80211_device* ieee)
395{
396 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
397 struct ieee80211_network* net = &ieee->current_network;
398 //FIXME: need to decide 92U_SOFTAP //LZM,090320
399 if(net->bssht.bdRT2RTAggregation){
400 pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK;
401 if(net->bssht.RT2RT_HT_Mode & RT_HT_CAP_USE_92SE){
402 pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK_92SE;
403 }
404 }
405 else if(net->broadcom_cap_exist)
406 pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM;
407 else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) ||
408 (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)||
409 (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)||
410 (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) )
411 pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM;
412 else if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) ||
413 (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) ||
414 (memcmp(net->bssid, PCI_RALINK, 3)==0) ||
415 (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) ||
416 (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) ||
417 net->ralink_cap_exist)
418 pHTInfo->IOTPeer = HT_IOT_PEER_RALINK;
419 else if((net->atheros_cap_exist )||
420 (memcmp(net->bssid, DLINK_ATHEROS_1, 3) == 0)||
421 (memcmp(net->bssid, DLINK_ATHEROS_2, 3) == 0))
422 pHTInfo->IOTPeer = HT_IOT_PEER_ATHEROS;
423 else if(memcmp(net->bssid, CISCO_BROADCOM, 3)==0)
424 pHTInfo->IOTPeer = HT_IOT_PEER_CISCO;
425 else if ((memcmp(net->bssid, LINKSYS_MARVELL_4400N, 3) == 0) ||
426 net->marvell_cap_exist)
427 pHTInfo->IOTPeer = HT_IOT_PEER_MARVELL;
428 else
429 pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN;
430
431 IEEE80211_DEBUG(IEEE80211_DL_IOT, "Joseph debug!! IOTPEER: %x\n", pHTInfo->IOTPeer);
432}
433/********************************************************************************************************************
434 *function: Check whether driver should declare received rate up to MCS13 only since some chipset is not good
435 * at receiving MCS14~15 frame from some AP.
436 * input: struct ieee80211_device* ieee
437 * u8 * PeerMacAddr
438 * output: none
439 * return: return 1 if driver should declare MCS13 only(otherwise return 0)
440 * *****************************************************************************************************************/
441u8 HTIOTActIsDisableMCS14(struct ieee80211_device* ieee, u8* PeerMacAddr)
442{
443 u8 ret = 0;
444#if 0
445 // Apply for 819u only
446#if (HAL_CODE_BASE==RTL8192 && DEV_BUS_TYPE==USB_INTERFACE)
447 if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) ||
448 (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)
449 )
450 {
451 ret = 1;
452 }
453
454
455 if(pHTInfo->bCurrentRT2RTAggregation)
456 {
457 // The parameter of pHTInfo->bCurrentRT2RTAggregation must be decided previously
458 ret = 1;
459 }
460#endif
461#endif
462 return ret;
463 }
464
465
466/**
467* Function: HTIOTActIsDisableMCS15
468*
469* Overview: Check whether driver should declare capability of receving MCS15
470*
471* Input:
472* PADAPTER Adapter,
473*
474* Output: None
475* Return: true if driver should disable MCS15
476* 2008.04.15 Emily
477*/
478bool HTIOTActIsDisableMCS15(struct ieee80211_device* ieee)
479{
480 bool retValue = false;
481
482#ifdef TODO
483 // Apply for 819u only
484#if (HAL_CODE_BASE==RTL8192)
485
486#if (DEV_BUS_TYPE == USB_INTERFACE)
487 // Alway disable MCS15 by Jerry Chang's request.by Emily, 2008.04.15
488 retValue = true;
489#elif (DEV_BUS_TYPE == PCI_INTERFACE)
490 // Enable MCS15 if the peer is Cisco AP. by Emily, 2008.05.12
491// if(pBssDesc->bCiscoCapExist)
492// retValue = false;
493// else
494 retValue = false;
495#endif
496#endif
497#endif
498 // Jerry Chang suggest that 8190 1x2 does not need to disable MCS15
499
500 return retValue;
501}
502
503/**
504* Function: HTIOTActIsDisableMCSTwoSpatialStream
505*
506* Overview: Check whether driver should declare capability of receving All 2 ss packets
507*
508* Input:
509* PADAPTER Adapter,
510*
511* Output: None
512* Return: true if driver should disable all two spatial stream packet
513* 2008.04.21 Emily
514*/
515bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee)
516{
517 bool retValue = false;
518#ifdef TODO
519 // Apply for 819u only
520//#if (HAL_CODE_BASE==RTL8192)
521
522 //This rule only apply to Belkin(Ralink) AP
523 if(IS_UNDER_11N_AES_MODE(Adapter))
524 {
525 if((PlatformCompareMemory(PeerMacAddr, BELKINF5D8233V1_RALINK, 3)==0) ||
526 (PlatformCompareMemory(PeerMacAddr, PCI_RALINK, 3)==0) ||
527 (PlatformCompareMemory(PeerMacAddr, EDIMAX_RALINK, 3)==0))
528 {
529 //Set True to disable this function. Disable by default, Emily, 2008.04.23
530 retValue = false;
531 }
532 }
533
534//#endif
535#endif
536#if 1
537#if (defined(RTL8192SE) || (defined(RTL8192SU)))
538 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
539 if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev))
540 {
541 if( (pHTInfo->IOTPeer != HT_IOT_PEER_ATHEROS) &&
542 (pHTInfo->IOTPeer != HT_IOT_PEER_UNKNOWN) &&
543 (pHTInfo->IOTPeer != HT_IOT_PEER_MARVELL) )
544 retValue = true;
545 }
546#endif
547#endif
548 return retValue;
549}
550
551/********************************************************************************************************************
552 *function: Check whether driver should disable EDCA turbo mode
553 * input: struct ieee80211_device* ieee
554 * u8* PeerMacAddr
555 * output: none
556 * return: return 1 if driver should disable EDCA turbo mode(otherwise return 0)
557 * *****************************************************************************************************************/
558u8 HTIOTActIsDisableEDCATurbo(struct ieee80211_device* ieee, u8* PeerMacAddr)
559{
560 u8 retValue = false; // default enable EDCA Turbo mode.
561 // Set specific EDCA parameter for different AP in DM handler.
562
563 return retValue;
564#if 0
565 if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0)||
566 (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)||
567 (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)||
568 (memcmp(PeerMacAddr, NETGEAR834Bv2_BROADCOM, 3)==0))
569
570 {
571 retValue = 1; //Linksys disable EDCA turbo mode
572 }
573
574 return retValue;
575#endif
576}
577
578/********************************************************************************************************************
579 *function: Check whether we need to use OFDM to sned MGNT frame for broadcom AP
580 * input: struct ieee80211_network *network //current network we live
581 * output: none
582 * return: return 1 if true
583 * *****************************************************************************************************************/
584u8 HTIOTActIsMgntUseCCK6M(struct ieee80211_network *network)
585{
586 u8 retValue = 0;
587
588 // 2008/01/25 MH Judeg if we need to use OFDM to sned MGNT frame for broadcom AP.
589 // 2008/01/28 MH We must prevent that we select null bssid to link.
590
591 if(network->broadcom_cap_exist)
592 {
593 retValue = 1;
594 }
595
596 return retValue;
597}
598
599u8 HTIOTActIsForcedCTS2Self(struct ieee80211_network *network)
600{
601 u8 retValue = 0;
602
603 if(network->marvell_cap_exist)
604 {
605 retValue = 1;
606 }
607
608 return retValue;
609}
610
611u8 HTIOTActIsForcedRTSCTS(struct ieee80211_device *ieee, struct ieee80211_network *network)
612{
613 u8 retValue = 0;
614 printk("============>%s(), %d\n", __FUNCTION__, network->realtek_cap_exit);
615 // Force protection
616#if defined(RTL8192SE) || defined(RTL8192SU)
617 if(ieee->pHTInfo->bCurrentHTSupport)
618 {
619 //if(!network->realtek_cap_exit)
620 if((ieee->pHTInfo->IOTPeer != HT_IOT_PEER_REALTEK)&&
621 (ieee->pHTInfo->IOTPeer != HT_IOT_PEER_REALTEK_92SE))
622 {
623 if((ieee->pHTInfo->IOTAction & HT_IOT_ACT_TX_NO_AGGREGATION) == 0)
624 retValue = 1;
625 }
626 }
627#endif
628 return retValue;
629}
630
631u8
632HTIOTActIsForcedAMSDU8K(struct ieee80211_device *ieee, struct ieee80211_network *network)
633{
634 u8 retValue = 0;
635
636 return retValue;
637}
638
639u8 HTIOTActIsCCDFsync(u8* PeerMacAddr)
640{
641 u8 retValue = 0;
642#ifndef RTL8192SE
643 if( (memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) ||
644 (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) ||
645 (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3) ==0))
646 {
647 retValue = 1;
648 }
649#endif
650 return retValue;
651}
652
653/*
654 * 819xS single chip b-cut series cannot handle BAR
655 */
656u8
657HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
658{
659 u8 retValue = 0;
660 //if(IS_HARDWARE_TYPE_8192SE(Adapter) ||
661 // IS_HARDWARE_TYPE_8192SU(Adapter)
662 //)
663#if (defined RTL8192SE || defined RTL8192SU)
664 {
665 // Do not reject ADDBA REQ because some of the AP may
666 // keep on sending ADDBA REQ qhich cause DHCP fail or ping loss!
667 // by HPFan, 2008/12/30
668
669 //if(pBssDesc->Vender == HT_IOT_PEER_MARVELL)
670 // return FALSE;
671
672 }
673#endif
674
675 return retValue;
676
677}
678
679/*
680 * EDCA parameters bias on downlink
681 */
682 u8
683 HTIOTActIsEDCABiasRx(struct ieee80211_device* ieee,struct ieee80211_network *network)
684{
685 u8 retValue = 0;
686 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
687#ifdef RTL8192SU
688 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
689 {
690//#if UNDER_VISTA
691// if(pBssDesc->Vender==HT_IOT_PEER_ATHEROS ||
692// pBssDesc->Vender==HT_IOT_PEER_RALINK)
693//#else
694 if(pHTInfo->IOTPeer==HT_IOT_PEER_ATHEROS ||
695 pHTInfo->IOTPeer==HT_IOT_PEER_BROADCOM ||
696 pHTInfo->IOTPeer==HT_IOT_PEER_RALINK)
697//#endif
698 return 1;
699
700 }
701#endif
702 return retValue;
703}
704
705u8
706HTIOTActDisableShortGI(struct ieee80211_device* ieee,struct ieee80211_network *network)
707{
708 u8 retValue = 0;
709 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
710
711 if(pHTInfo->IOTPeer==HT_IOT_PEER_RALINK)
712 {
713 if(network->bssht.bdHT1R)
714 retValue = 1;
715 }
716
717 return retValue;
718}
719
720u8
721HTIOTActDisableHighPower(struct ieee80211_device* ieee,struct ieee80211_network *network)
722{
723 u8 retValue = 0;
724 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
725
726 if(pHTInfo->IOTPeer==HT_IOT_PEER_RALINK)
727 {
728 if(network->bssht.bdHT1R)
729 retValue = 1;
730 }
731
732 return retValue;
733}
734
735void
736HTIOTActDetermineRaFunc(struct ieee80211_device* ieee, bool bPeerRx2ss)
737{
738 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
739 pHTInfo->IOTRaFunc &= HT_IOT_RAFUNC_DISABLE_ALL;
740
741 if(pHTInfo->IOTPeer == HT_IOT_PEER_RALINK && !bPeerRx2ss)
742 pHTInfo->IOTRaFunc |= HT_IOT_RAFUNC_PEER_1R;
743
744 if(pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE)
745 pHTInfo->IOTRaFunc |= HT_IOT_RAFUNC_TX_AMSDU;
746
747 printk("!!!!!!!!!!!!!!!!!!!!!!!!!!!IOTRaFunc = %8.8x\n", pHTInfo->IOTRaFunc);
748}
749
750
751u8
752HTIOTActIsDisableTx40MHz(struct ieee80211_device* ieee,struct ieee80211_network *network)
753{
754 u8 retValue = 0;
755
756#if (defined RTL8192SU || defined RTL8192SE)
757 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
758 if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
759 (KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
760 (KEY_TYPE_WEP104 == ieee->group_key_type) ||
761 (KEY_TYPE_WEP40 == ieee->group_key_type) ||
762 (KEY_TYPE_TKIP == ieee->pairwise_key_type) )
763 {
764 if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT))
765 retValue = 1;
766 }
767#endif
768
769 return retValue;
770}
771
772u8
773HTIOTActIsTxNoAggregation(struct ieee80211_device* ieee,struct ieee80211_network *network)
774{
775 u8 retValue = 0;
776
777#if (defined RTL8192SU || defined RTL8192SE)
778 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
779 if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
780 (KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
781 (KEY_TYPE_WEP104 == ieee->group_key_type) ||
782 (KEY_TYPE_WEP40 == ieee->group_key_type) ||
783 (KEY_TYPE_TKIP == ieee->pairwise_key_type) )
784 {
785 if(pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK ||
786 pHTInfo->IOTPeer==HT_IOT_PEER_UNKNOWN)
787 retValue = 1;
788 }
789#endif
790
791 return retValue;
792}
793
794
795u8
796HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *network)
797{
798 u8 retValue = 0;
799
800#if (defined RTL8192SU || defined RTL8192SE)
801 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
802 if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
803 (KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
804 (KEY_TYPE_WEP104 == ieee->group_key_type) ||
805 (KEY_TYPE_WEP40 == ieee->group_key_type) ||
806 (KEY_TYPE_TKIP == ieee->pairwise_key_type) )
807 {
808 if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT))
809 retValue = 1;
810 }
811#endif
812
813 return retValue;
814}
815
816
817bool HTIOCActAllowPeerAggOnePacket(struct ieee80211_device* ieee,struct ieee80211_network *network)
818{
819 bool retValue = false;
820#if defined(RTL8192SE) || defined(RTL8192SU)
821 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
822 {
823 if(pHTInfo->IOTPeer == HT_IOT_PEER_MARVELL)
824 return true;
825
826 }
827#endif
828 return retValue;
829}
830
831void HTResetIOTSetting(
832 PRT_HIGH_THROUGHPUT pHTInfo
833)
834{
835 pHTInfo->IOTAction = 0;
836 pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN;
837 pHTInfo->IOTRaFunc = 0;
838}
839
840
841/********************************************************************************************************************
842 *function: Construct Capablility Element in Beacon... if HTEnable is turned on
843 * input: struct ieee80211_device* ieee
844 * u8* posHTCap //pointer to store Capability Ele
845 * u8* len //store length of CE
846 * u8 IsEncrypt //whether encrypt, needed further
847 * output: none
848 * return: none
849 * notice: posHTCap can't be null and should be initialized before.
850 * *****************************************************************************************************************/
851void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 IsEncrypt)
852{
853 PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo;
854 PHT_CAPABILITY_ELE pCapELE = NULL;
855 //u8 bIsDeclareMCS13;
856
857 if ((posHTCap == NULL) || (pHT == NULL))
858 {
859 IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTCap or pHTInfo can't be null in HTConstructCapabilityElement()\n");
860 return;
861 }
862 memset(posHTCap, 0, *len);
863 if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC)
864 {
865 u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily
866 memcpy(posHTCap, EWC11NHTCap, sizeof(EWC11NHTCap));
867 pCapELE = (PHT_CAPABILITY_ELE)&(posHTCap[4]);
868 }else
869 {
870 pCapELE = (PHT_CAPABILITY_ELE)posHTCap;
871 }
872
873
874 //HT capability info
875 pCapELE->AdvCoding = 0; // This feature is not supported now!!
876 if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))
877 {
878 pCapELE->ChlWidth = 0;
879 }
880 else
881 {
882 pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0);
883 }
884
885// pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0);
886 pCapELE->MimoPwrSave = pHT->SelfMimoPs;
887 pCapELE->GreenField = 0; // This feature is not supported now!!
888 pCapELE->ShortGI20Mhz = 1; // We can receive Short GI!!
889 pCapELE->ShortGI40Mhz = 1; // We can receive Short GI!!
890 //DbgPrint("TX HT cap/info ele BW=%d SG20=%d SG40=%d\n\r",
891 //pCapELE->ChlWidth, pCapELE->ShortGI20Mhz, pCapELE->ShortGI40Mhz);
892 pCapELE->TxSTBC = 1;
893 pCapELE->RxSTBC = 0;
894 pCapELE->DelayBA = 0; // Do not support now!!
895 pCapELE->MaxAMSDUSize = (MAX_RECEIVE_BUFFER_SIZE>=7935)?1:0;
896 pCapELE->DssCCk = ((pHT->bRegBW40MHz)?(pHT->bRegSuppCCK?1:0):0);
897 pCapELE->PSMP = 0; // Do not support now!!
898 pCapELE->LSigTxopProtect = 0; // Do not support now!!
899
900
901 //MAC HT parameters info
902 // TODO: Nedd to take care of this part
903 IEEE80211_DEBUG(IEEE80211_DL_HT, "TX HT cap/info ele BW=%d MaxAMSDUSize:%d DssCCk:%d\n", pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk);
904
905 if( IsEncrypt)
906 {
907 pCapELE->MPDUDensity = 7; // 8us
908 pCapELE->MaxRxAMPDUFactor = 2; // 2 is for 32 K and 3 is 64K
909 }
910 else
911 {
912 pCapELE->MaxRxAMPDUFactor = 3; // 2 is for 32 K and 3 is 64K
913 pCapELE->MPDUDensity = 0; // no density
914 }
915
916 //Supported MCS set
917 memcpy(pCapELE->MCS, ieee->Regdot11HTOperationalRateSet, 16);
918 if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS15)
919 pCapELE->MCS[1] &= 0x7f;
920
921 if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS14)
922 pCapELE->MCS[1] &= 0xbf;
923
924 if(pHT->IOTAction & HT_IOT_ACT_DISABLE_ALL_2SS)
925 pCapELE->MCS[1] &= 0x00;
926
927 // 2008.06.12
928 // For RTL819X, if pairwisekey = wep/tkip, ap is ralink, we support only MCS0~7.
929 if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))
930 {
931 int i;
932 for(i = 1; i< 16; i++)
933 pCapELE->MCS[i] = 0;
934 }
935
936 //Extended HT Capability Info
937 memset(&pCapELE->ExtHTCapInfo, 0, 2);
938
939
940 //TXBF Capabilities
941 memset(pCapELE->TxBFCap, 0, 4);
942
943 //Antenna Selection Capabilities
944 pCapELE->ASCap = 0;
945//add 2 to give space for element ID and len when construct frames
946 if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC)
947 *len = 30 + 2;
948 else
949 *len = 26 + 2;
950
951
952
953// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTCap, *len -2);
954
955 //Print each field in detail. Driver should not print out this message by default
956// HTDebugHTCapability(posHTCap, (u8*)"HTConstructCapability()");
957 return;
958
959}
960/********************************************************************************************************************
961 *function: Construct Information Element in Beacon... if HTEnable is turned on
962 * input: struct ieee80211_device* ieee
963 * u8* posHTCap //pointer to store Information Ele
964 * u8* len //store len of
965 * u8 IsEncrypt //whether encrypt, needed further
966 * output: none
967 * return: none
968 * notice: posHTCap can't be null and be initialized before. only AP and IBSS sta should do this
969 * *****************************************************************************************************************/
970void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 IsEncrypt)
971{
972 PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo;
973 PHT_INFORMATION_ELE pHTInfoEle = (PHT_INFORMATION_ELE)posHTInfo;
974 if ((posHTInfo == NULL) || (pHTInfoEle == NULL))
975 {
976 IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTInfo or pHTInfoEle can't be null in HTConstructInfoElement()\n");
977 return;
978 }
979
980 memset(posHTInfo, 0, *len);
981 if ( (ieee->iw_mode == IW_MODE_ADHOC) || (ieee->iw_mode == IW_MODE_MASTER)) //ap mode is not currently supported
982 {
983 pHTInfoEle->ControlChl = ieee->current_network.channel;
984 pHTInfoEle->ExtChlOffset = ((pHT->bRegBW40MHz == false)?HT_EXTCHNL_OFFSET_NO_EXT:
985 (ieee->current_network.channel<=6)?
986 HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER);
987 pHTInfoEle->RecommemdedTxWidth = pHT->bRegBW40MHz;
988 pHTInfoEle->RIFS = 0;
989 pHTInfoEle->PSMPAccessOnly = 0;
990 pHTInfoEle->SrvIntGranularity = 0;
991 pHTInfoEle->OptMode = pHT->CurrentOpMode;
992 pHTInfoEle->NonGFDevPresent = 0;
993 pHTInfoEle->DualBeacon = 0;
994 pHTInfoEle->SecondaryBeacon = 0;
995 pHTInfoEle->LSigTxopProtectFull = 0;
996 pHTInfoEle->PcoActive = 0;
997 pHTInfoEle->PcoPhase = 0;
998
999 memset(pHTInfoEle->BasicMSC, 0, 16);
1000
1001
1002 *len = 22 + 2; //same above
1003
1004 }
1005 else
1006 {
1007 //STA should not generate High Throughput Information Element
1008 *len = 0;
1009 }
1010 //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTInfo, *len - 2);
1011 //HTDebugHTInfo(posHTInfo, "HTConstructInforElement");
1012 return;
1013}
1014
1015/*
1016 * According to experiment, Realtek AP to STA (based on rtl8190) may achieve best performance
1017 * if both STA and AP set limitation of aggregation size to 32K, that is, set AMPDU density to 2
1018 * (Ref: IEEE 11n specification). However, if Realtek STA associates to other AP, STA should set
1019 * limitation of aggregation size to 8K, otherwise, performance of traffic stream from STA to AP
1020 * will be much less than the traffic stream from AP to STA if both of the stream runs concurrently
1021 * at the same time.
1022 *
1023 * Frame Format
1024 * Element ID Length OUI Type1 Reserved
1025 * 1 byte 1 byte 3 bytes 1 byte 1 byte
1026 *
1027 * OUI = 0x00, 0xe0, 0x4c,
1028 * Type = 0x02
1029 * Reserved = 0x00
1030 *
1031 * 2007.8.21 by Emily
1032*/
1033/********************************************************************************************************************
1034 *function: Construct Information Element in Beacon... in RT2RT condition
1035 * input: struct ieee80211_device* ieee
1036 * u8* posRT2RTAgg //pointer to store Information Ele
1037 * u8* len //store len
1038 * output: none
1039 * return: none
1040 * notice:
1041 * *****************************************************************************************************************/
1042void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len)
1043{
1044 if (posRT2RTAgg == NULL) {
1045 IEEE80211_DEBUG(IEEE80211_DL_ERR, "posRT2RTAgg can't be null in HTConstructRT2RTAggElement()\n");
1046 return;
1047 }
1048 memset(posRT2RTAgg, 0, *len);
1049 *posRT2RTAgg++ = 0x00;
1050 *posRT2RTAgg++ = 0xe0;
1051 *posRT2RTAgg++ = 0x4c;
1052 *posRT2RTAgg++ = 0x02;
1053 *posRT2RTAgg++ = 0x01;
1054 *posRT2RTAgg = 0x10;//*posRT2RTAgg = 0x02;
1055
1056 if(ieee->bSupportRemoteWakeUp) {
1057 *posRT2RTAgg |= 0x08;//RT_HT_CAP_USE_WOW;
1058 }
1059
1060 *len = 6 + 2;
1061 return;
1062#ifdef TODO
1063#if(HAL_CODE_BASE == RTL8192 && DEV_BUS_TYPE == USB_INTERFACE)
1064 /*
1065 //Emily. If it is required to Ask Realtek AP to send AMPDU during AES mode, enable this
1066 section of code.
1067 if(IS_UNDER_11N_AES_MODE(Adapter))
1068 {
1069 posRT2RTAgg->Octet[5] |=RT_HT_CAP_USE_AMPDU;
1070 }else
1071 {
1072 posRT2RTAgg->Octet[5] &= 0xfb;
1073 }
1074 */
1075
1076#else
1077 // Do Nothing
1078#endif
1079
1080 posRT2RTAgg->Length = 6;
1081#endif
1082
1083
1084
1085
1086}
1087
1088
1089/********************************************************************************************************************
1090 *function: Pick the right Rate Adaptive table to use
1091 * input: struct ieee80211_device* ieee
1092 * u8* pOperateMCS //A pointer to MCS rate bitmap
1093 * return: always we return true
1094 * notice:
1095 * *****************************************************************************************************************/
1096u8 HT_PickMCSRate(struct ieee80211_device* ieee, u8* pOperateMCS)
1097{
1098 u8 i;
1099 if (pOperateMCS == NULL)
1100 {
1101 IEEE80211_DEBUG(IEEE80211_DL_ERR, "pOperateMCS can't be null in HT_PickMCSRate()\n");
1102 return false;
1103 }
1104
1105 switch(ieee->mode)
1106 {
1107 case IEEE_A:
1108 case IEEE_B:
1109 case IEEE_G:
1110 //legacy rate routine handled at selectedrate
1111
1112 //no MCS rate
1113 for(i=0;i<=15;i++){
1114 pOperateMCS[i] = 0;
1115 }
1116 break;
1117
1118 case IEEE_N_24G: //assume CCK rate ok
1119 case IEEE_N_5G:
1120 // Legacy part we only use 6, 5.5,2,1 for N_24G and 6 for N_5G.
1121 // Legacy part shall be handled at SelectRateSet().
1122
1123 //HT part
1124 // TODO: may be different if we have different number of antenna
1125 pOperateMCS[0] &=RATE_ADPT_1SS_MASK; //support MCS 0~7
1126 pOperateMCS[1] &=RATE_ADPT_2SS_MASK;
1127 pOperateMCS[3] &=RATE_ADPT_MCS32_MASK;
1128 break;
1129
1130 //should never reach here
1131 default:
1132
1133 break;
1134
1135 }
1136
1137 return true;
1138}
1139
1140/*
1141* Description:
1142* This function will get the highest speed rate in input MCS set.
1143*
1144* /param Adapter Pionter to Adapter entity
1145* pMCSRateSet Pointer to MCS rate bitmap
1146* pMCSFilter Pointer to MCS rate filter
1147*
1148* /return Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter.
1149*
1150*/
1151/********************************************************************************************************************
1152 *function: This function will get the highest speed rate in input MCS set.
1153 * input: struct ieee80211_device* ieee
1154 * u8* pMCSRateSet //Pointer to MCS rate bitmap
1155 * u8* pMCSFilter //Pointer to MCS rate filter
1156 * return: Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter
1157 * notice:
1158 * *****************************************************************************************************************/
1159u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter)
1160{
1161 u8 i, j;
1162 u8 bitMap;
1163 u8 mcsRate = 0;
1164 u8 availableMcsRate[16];
1165 if (pMCSRateSet == NULL || pMCSFilter == NULL)
1166 {
1167 IEEE80211_DEBUG(IEEE80211_DL_ERR, "pMCSRateSet or pMCSFilter can't be null in HTGetHighestMCSRate()\n");
1168 return false;
1169 }
1170 for(i=0; i<16; i++)
1171 availableMcsRate[i] = pMCSRateSet[i] & pMCSFilter[i];
1172
1173 for(i = 0; i < 16; i++)
1174 {
1175 if(availableMcsRate[i] != 0)
1176 break;
1177 }
1178 if(i == 16)
1179 return false;
1180
1181 for(i = 0; i < 16; i++)
1182 {
1183 if(availableMcsRate[i] != 0)
1184 {
1185 bitMap = availableMcsRate[i];
1186 for(j = 0; j < 8; j++)
1187 {
1188 if((bitMap%2) != 0)
1189 {
1190 if(HTMcsToDataRate(ieee, (8*i+j)) > HTMcsToDataRate(ieee, mcsRate))
1191 mcsRate = (8*i+j);
1192 }
1193 bitMap = bitMap>>1;
1194 }
1195 }
1196 }
1197 return (mcsRate|0x80);
1198}
1199
1200
1201
1202/*
1203**
1204**1.Filter our operation rate set with AP's rate set
1205**2.shall reference channel bandwidth, STBC, Antenna number
1206**3.generate rate adative table for firmware
1207**David 20060906
1208**
1209** \pHTSupportedCap: the connected STA's supported rate Capability element
1210*/
1211u8 HTFilterMCSRate( struct ieee80211_device* ieee, u8* pSupportMCS, u8* pOperateMCS)
1212{
1213
1214 u8 i=0;
1215
1216 // filter out operational rate set not supported by AP, the lenth of it is 16
1217 for(i=0;i<=15;i++){
1218 pOperateMCS[i] = ieee->Regdot11HTOperationalRateSet[i]&pSupportMCS[i];
1219 }
1220
1221
1222 // TODO: adjust our operational rate set according to our channel bandwidth, STBC and Antenna number
1223
1224 // TODO: fill suggested rate adaptive rate index and give firmware info using Tx command packet
1225 // we also shall suggested the first start rate set according to our singal strength
1226 HT_PickMCSRate(ieee, pOperateMCS);
1227
1228 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
1229 if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))
1230 pOperateMCS[1] = 0;
1231
1232 //
1233 // For RTL819X, we support only MCS0~15.
1234 // And also, we do not know how to use MCS32 now.
1235 //
1236 for(i=2; i<=15; i++)
1237 pOperateMCS[i] = 0;
1238
1239 return true;
1240}
1241void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
1242#if 0
1243//I need move this function to other places, such as rx?
1244#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1245void HTOnAssocRsp_wq(struct work_struct *work)
1246{
1247 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, ht_onAssRsp);
1248#else
1249void HTOnAssocRsp_wq(struct ieee80211_device *ieee)
1250{
1251#endif
1252#endif
1253void HTOnAssocRsp(struct ieee80211_device *ieee)
1254{
1255 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1256 PHT_CAPABILITY_ELE pPeerHTCap = NULL;
1257 PHT_INFORMATION_ELE pPeerHTInfo = NULL;
1258 u16 nMaxAMSDUSize = 0;
1259 u8* pMcsFilter = NULL;
1260
1261 static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily
1262 static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily
1263
1264 if( pHTInfo->bCurrentHTSupport == false )
1265 {
1266 IEEE80211_DEBUG(IEEE80211_DL_ERR, "<=== HTOnAssocRsp(): HT_DISABLE\n");
1267 return;
1268 }
1269 IEEE80211_DEBUG(IEEE80211_DL_HT, "===> HTOnAssocRsp_wq(): HT_ENABLE\n");
1270// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTCapBuf, sizeof(HT_CAPABILITY_ELE));
1271// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTInfoBuf, sizeof(HT_INFORMATION_ELE));
1272
1273// HTDebugHTCapability(pHTInfo->PeerHTCapBuf,"HTOnAssocRsp_wq");
1274// HTDebugHTInfo(pHTInfo->PeerHTInfoBuf,"HTOnAssocRsp_wq");
1275 //
1276 if(!memcmp(pHTInfo->PeerHTCapBuf,EWC11NHTCap, sizeof(EWC11NHTCap)))
1277 pPeerHTCap = (PHT_CAPABILITY_ELE)(&pHTInfo->PeerHTCapBuf[4]);
1278 else
1279 pPeerHTCap = (PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf);
1280
1281 if(!memcmp(pHTInfo->PeerHTInfoBuf, EWC11NHTInfo, sizeof(EWC11NHTInfo)))
1282 pPeerHTInfo = (PHT_INFORMATION_ELE)(&pHTInfo->PeerHTInfoBuf[4]);
1283 else
1284 pPeerHTInfo = (PHT_INFORMATION_ELE)(pHTInfo->PeerHTInfoBuf);
1285
1286
1287 ////////////////////////////////////////////////////////
1288 // Configurations:
1289 ////////////////////////////////////////////////////////
1290 IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTCap, sizeof(HT_CAPABILITY_ELE));
1291// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTInfo, sizeof(HT_INFORMATION_ELE));
1292 // Config Supported Channel Width setting
1293 //
1294 HTSetConnectBwMode(ieee, (HT_CHANNEL_WIDTH)(pPeerHTCap->ChlWidth), (HT_EXTCHNL_OFFSET)(pPeerHTInfo->ExtChlOffset));
1295
1296// if(pHTInfo->bCurBW40MHz == true)
1297 pHTInfo->bCurTxBW40MHz = ((pPeerHTInfo->RecommemdedTxWidth == 1)?true:false);
1298
1299 //
1300 // Update short GI/ long GI setting
1301 //
1302 // TODO:
1303 pHTInfo->bCurShortGI20MHz=
1304 ((pHTInfo->bRegShortGI20MHz)?((pPeerHTCap->ShortGI20Mhz==1)?true:false):false);
1305 pHTInfo->bCurShortGI40MHz=
1306 ((pHTInfo->bRegShortGI40MHz)?((pPeerHTCap->ShortGI40Mhz==1)?true:false):false);
1307
1308 //
1309 // Config TX STBC setting
1310 //
1311 // TODO:
1312
1313 //
1314 // Config DSSS/CCK mode in 40MHz mode
1315 //
1316 // TODO:
1317 pHTInfo->bCurSuppCCK =
1318 ((pHTInfo->bRegSuppCCK)?((pPeerHTCap->DssCCk==1)?true:false):false);
1319
1320
1321 //
1322 // Config and configure A-MSDU setting
1323 //
1324 pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support;
1325
1326 nMaxAMSDUSize = (pPeerHTCap->MaxAMSDUSize==0)?3839:7935;
1327
1328 if(pHTInfo->nAMSDU_MaxSize > nMaxAMSDUSize )
1329 pHTInfo->nCurrent_AMSDU_MaxSize = nMaxAMSDUSize;
1330 else
1331 pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize;
1332
1333 //
1334 // Config A-MPDU setting
1335 //
1336 pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable;
1337 if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev))
1338 {
1339 if( (pHTInfo->IOTPeer== HT_IOT_PEER_ATHEROS) ||
1340 (pHTInfo->IOTPeer == HT_IOT_PEER_UNKNOWN) )
1341 pHTInfo->bCurrentAMPDUEnable = false;
1342 }
1343
1344 // <1> Decide AMPDU Factor
1345
1346 // By Emily
1347 if(!pHTInfo->bRegRT2RTAggregation)
1348 {
1349 // Decide AMPDU Factor according to protocol handshake
1350 if(pHTInfo->AMPDU_Factor > pPeerHTCap->MaxRxAMPDUFactor)
1351 pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor;
1352 else
1353 pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor;
1354
1355 }else
1356 {
1357 // Set MPDU density to 2 to Realtek AP, and set it to 0 for others
1358 // Replace MPDU factor declared in original association response frame format. 2007.08.20 by Emily
1359#if 0
1360 osTmp= PacketGetElement( asocpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE);
1361 if(osTmp.Length >= 5) //00:e0:4c:02:00
1362#endif
1363 if (ieee->current_network.bssht.bdRT2RTAggregation)
1364 {
1365 if( ieee->pairwise_key_type != KEY_TYPE_NA)
1366 // Realtek may set 32k in security mode and 64k for others
1367 pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor;
1368 else
1369 pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_64K;
1370 }else
1371 {
1372 if(pPeerHTCap->MaxRxAMPDUFactor < HT_AGG_SIZE_32K)
1373 pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor;
1374 else
1375 pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_32K;
1376 }
1377 }
1378
1379 // <2> Set AMPDU Minimum MPDU Start Spacing
1380 // 802.11n 3.0 section 9.7d.3
1381#if 1
1382 if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity)
1383 pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density;
1384 else
1385 pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity;
1386 if(ieee->pairwise_key_type != KEY_TYPE_NA )
1387 pHTInfo->CurrentMPDUDensity = 7; // 8us
1388#else
1389 if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity)
1390 pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density;
1391 else
1392 pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity;
1393#endif
1394 // Force TX AMSDU
1395
1396 // Lanhsin: mark for tmp to avoid deauth by ap from s3
1397 //if(memcmp(pMgntInfo->Bssid, NETGEAR834Bv2_BROADCOM, 3)==0)
1398 if(pHTInfo->IOTAction & HT_IOT_ACT_TX_USE_AMSDU_8K)
1399 {
1400
1401 pHTInfo->bCurrentAMPDUEnable = false;
1402 pHTInfo->ForcedAMSDUMode = HT_AGG_FORCE_ENABLE;
1403 pHTInfo->ForcedAMSDUMaxSize = 7935;
1404 }
1405
1406 // Rx Reorder Setting
1407 pHTInfo->bCurRxReorderEnable = pHTInfo->bRegRxReorderEnable;
1408
1409 //
1410 // Filter out unsupported HT rate for this AP
1411 // Update RATR table
1412 // This is only for 8190 ,8192 or later product which using firmware to handle rate adaptive mechanism.
1413 //
1414
1415 // Handle Ralink AP bad MCS rate set condition. Joseph.
1416 // This fix the bug of Ralink AP. This may be removed in the future.
1417 if(pPeerHTCap->MCS[0] == 0)
1418 pPeerHTCap->MCS[0] = 0xff;
1419
1420 // Joseph test //LZM ADD 090318
1421 HTIOTActDetermineRaFunc(ieee, ((pPeerHTCap->MCS[1])!=0));
1422
1423 HTFilterMCSRate(ieee, pPeerHTCap->MCS, ieee->dot11HTOperationalRateSet);
1424
1425 //
1426 // Config MIMO Power Save setting
1427 //
1428 pHTInfo->PeerMimoPs = pPeerHTCap->MimoPwrSave;
1429 if(pHTInfo->PeerMimoPs == MIMO_PS_STATIC)
1430 pMcsFilter = MCS_FILTER_1SS;
1431 else
1432 pMcsFilter = MCS_FILTER_ALL;
1433 //WB add for MCS8 bug
1434// pMcsFilter = MCS_FILTER_1SS;
1435 ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, pMcsFilter);
1436 ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate;
1437
1438 //
1439 // Config current operation mode.
1440 //
1441 pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode;
1442
1443
1444
1445}
1446
1447void HTSetConnectBwModeCallback(struct ieee80211_device* ieee);
1448/********************************************************************************************************************
1449 *function: initialize HT info(struct PRT_HIGH_THROUGHPUT)
1450 * input: struct ieee80211_device* ieee
1451 * output: none
1452 * return: none
1453 * notice: This function is called when * (1) MPInitialization Phase * (2) Receiving of Deauthentication from AP
1454********************************************************************************************************************/
1455// TODO: Should this funciton be called when receiving of Disassociation?
1456void HTInitializeHTInfo(struct ieee80211_device* ieee)
1457{
1458 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1459
1460 //
1461 // These parameters will be reset when receiving deauthentication packet
1462 //
1463 IEEE80211_DEBUG(IEEE80211_DL_HT, "===========>%s()\n", __FUNCTION__);
1464 pHTInfo->bCurrentHTSupport = false;
1465
1466 // 40MHz channel support
1467 pHTInfo->bCurBW40MHz = false;
1468 pHTInfo->bCurTxBW40MHz = false;
1469
1470 // Short GI support
1471 pHTInfo->bCurShortGI20MHz = false;
1472 pHTInfo->bCurShortGI40MHz = false;
1473 pHTInfo->bForcedShortGI = false;
1474
1475 // CCK rate support
1476 // This flag is set to true to support CCK rate by default.
1477 // It will be affected by "pHTInfo->bRegSuppCCK" and AP capabilities only when associate to
1478 // 11N BSS.
1479 pHTInfo->bCurSuppCCK = true;
1480
1481 // AMSDU related
1482 pHTInfo->bCurrent_AMSDU_Support = false;
1483 pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize;
1484
1485 // AMPUD related
1486 pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density;
1487 pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor;
1488
1489
1490
1491 // Initialize all of the parameters related to 11n
1492 memset((void*)(&(pHTInfo->SelfHTCap)), 0, sizeof(pHTInfo->SelfHTCap));
1493 memset((void*)(&(pHTInfo->SelfHTInfo)), 0, sizeof(pHTInfo->SelfHTInfo));
1494 memset((void*)(&(pHTInfo->PeerHTCapBuf)), 0, sizeof(pHTInfo->PeerHTCapBuf));
1495 memset((void*)(&(pHTInfo->PeerHTInfoBuf)), 0, sizeof(pHTInfo->PeerHTInfoBuf));
1496
1497 pHTInfo->bSwBwInProgress = false;
1498 pHTInfo->ChnlOp = CHNLOP_NONE;
1499
1500 // Set default IEEE spec for Draft N
1501 pHTInfo->ePeerHTSpecVer = HT_SPEC_VER_IEEE;
1502
1503 // Realtek proprietary aggregation mode
1504 pHTInfo->bCurrentRT2RTAggregation = false;
1505 pHTInfo->bCurrentRT2RTLongSlotTime = false;
1506 pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0;
1507
1508 pHTInfo->IOTPeer = 0;
1509 pHTInfo->IOTAction = 0;
1510 pHTInfo->IOTRaFunc = 0;
1511
1512 //MCS rate initialized here
1513 {
1514 u8* RegHTSuppRateSets = &(ieee->RegHTSuppRateSet[0]);
1515 RegHTSuppRateSets[0] = 0xFF; //support MCS 0~7
1516 RegHTSuppRateSets[1] = 0xFF; //support MCS 8~15
1517 RegHTSuppRateSets[4] = 0x01; //support MCS 32
1518 }
1519}
1520/********************************************************************************************************************
1521 *function: initialize Bss HT structure(struct PBSS_HT)
1522 * input: PBSS_HT pBssHT //to be initialized
1523 * output: none
1524 * return: none
1525 * notice: This function is called when initialize network structure
1526********************************************************************************************************************/
1527void HTInitializeBssDesc(PBSS_HT pBssHT)
1528{
1529
1530 pBssHT->bdSupportHT = false;
1531 memset(pBssHT->bdHTCapBuf, 0, sizeof(pBssHT->bdHTCapBuf));
1532 pBssHT->bdHTCapLen = 0;
1533 memset(pBssHT->bdHTInfoBuf, 0, sizeof(pBssHT->bdHTInfoBuf));
1534 pBssHT->bdHTInfoLen = 0;
1535
1536 pBssHT->bdHTSpecVer= HT_SPEC_VER_IEEE;
1537
1538 pBssHT->bdRT2RTAggregation = false;
1539 pBssHT->bdRT2RTLongSlotTime = false;
1540 pBssHT->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0;
1541}
1542#if 0
1543//below function has merged into ieee80211_network_init() in ieee80211_rx.c
1544void
1545HTParsingHTCapElement(
1546 IN PADAPTER Adapter,
1547 IN OCTET_STRING HTCapIE,
1548 OUT PRT_WLAN_BSS pBssDesc
1549)
1550{
1551 PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
1552
1553 if( HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf) )
1554 {
1555 RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTCapElement(): HT Capability Element length is too long!\n") );
1556 return;
1557 }
1558
1559 // TODO: Check the correctness of HT Cap
1560 //Print each field in detail. Driver should not print out this message by default
1561 if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc)
1562 HTDebugHTCapability(DBG_TRACE, Adapter, &HTCapIE, (pu8)"HTParsingHTCapElement()");
1563
1564 HTCapIE.Length = HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf)?\
1565 sizeof(pBssDesc->BssHT.bdHTCapBuf):HTCapIE.Length; //prevent from overflow
1566
1567 CopyMem(pBssDesc->BssHT.bdHTCapBuf, HTCapIE.Octet, HTCapIE.Length);
1568 pBssDesc->BssHT.bdHTCapLen = HTCapIE.Length;
1569
1570}
1571
1572
1573void
1574HTParsingHTInfoElement(
1575 PADAPTER Adapter,
1576 OCTET_STRING HTInfoIE,
1577 PRT_WLAN_BSS pBssDesc
1578)
1579{
1580 PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
1581
1582 if( HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf))
1583 {
1584 RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTInfoElement(): HT Information Element length is too long!\n") );
1585 return;
1586 }
1587
1588 // TODO: Check the correctness of HT Info
1589 //Print each field in detail. Driver should not print out this message by default
1590 if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc)
1591 HTDebugHTInfo(DBG_TRACE, Adapter, &HTInfoIE, (pu8)"HTParsingHTInfoElement()");
1592
1593 HTInfoIE.Length = HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)?\
1594 sizeof(pBssDesc->BssHT.bdHTInfoBuf):HTInfoIE.Length; //prevent from overflow
1595
1596 CopyMem( pBssDesc->BssHT.bdHTInfoBuf, HTInfoIE.Octet, HTInfoIE.Length);
1597 pBssDesc->BssHT.bdHTInfoLen = HTInfoIE.Length;
1598}
1599
1600/*
1601 * Get HT related information from beacon and save it in BssDesc
1602 *
1603 * (1) Parse HTCap, and HTInfo, and record whether it is 11n AP
1604 * (2) If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT()
1605 * (3) Check whether peer is Realtek AP (for Realtek proprietary aggregation mode).
1606 * Input:
1607 * PADAPTER Adapter
1608 *
1609 * Output:
1610 * PRT_TCB BssDesc
1611 *
1612*/
1613void HTGetValueFromBeaconOrProbeRsp(
1614 PADAPTER Adapter,
1615 POCTET_STRING pSRCmmpdu,
1616 PRT_WLAN_BSS bssDesc
1617)
1618{
1619 PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
1620 PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);
1621 OCTET_STRING HTCapIE, HTInfoIE, HTRealtekAgg, mmpdu;
1622 OCTET_STRING BroadcomElement, CiscoElement;
1623
1624 mmpdu.Octet = pSRCmmpdu->Octet;
1625 mmpdu.Length = pSRCmmpdu->Length;
1626
1627 //2Note:
1628 // Mark for IOT testing using Linksys WRT350N, This AP does not contain WMM IE when
1629 // it is configured at pure-N mode.
1630 // if(bssDesc->BssQos.bdQoSMode & QOS_WMM)
1631 //
1632
1633 HTInitializeBssDesc (&bssDesc->BssHT);
1634
1635 //2<1> Parse HTCap, and HTInfo
1636 // Get HT Capability IE: (1) Get IEEE Draft N IE or (2) Get EWC IE
1637 HTCapIE = PacketGetElement(mmpdu, EID_HTCapability, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE);
1638 if(HTCapIE.Length == 0)
1639 {
1640 HTCapIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_CAP, OUI_SUBTYPE_DONT_CARE);
1641 if(HTCapIE.Length != 0)
1642 bssDesc->BssHT.bdHTSpecVer= HT_SPEC_VER_EWC;
1643 }
1644 if(HTCapIE.Length != 0)
1645 HTParsingHTCapElement(Adapter, HTCapIE, bssDesc);
1646
1647 // Get HT Information IE: (1) Get IEEE Draft N IE or (2) Get EWC IE
1648 HTInfoIE = PacketGetElement(mmpdu, EID_HTInfo, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE);
1649 if(HTInfoIE.Length == 0)
1650 {
1651 HTInfoIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_INFO, OUI_SUBTYPE_DONT_CARE);
1652 if(HTInfoIE.Length != 0)
1653 bssDesc->BssHT.bdHTSpecVer = HT_SPEC_VER_EWC;
1654 }
1655 if(HTInfoIE.Length != 0)
1656 HTParsingHTInfoElement(Adapter, HTInfoIE, bssDesc);
1657
1658 //2<2>If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT()
1659 if(HTCapIE.Length != 0)
1660 {
1661 bssDesc->BssHT.bdSupportHT = true;
1662 if(bssDesc->BssQos.bdQoSMode == QOS_DISABLE)
1663 QosSetLegacyWMMParamWithHT(Adapter, bssDesc);
1664 }
1665 else
1666 {
1667 bssDesc->BssHT.bdSupportHT = false;
1668 }
1669
1670 //2<3>Check whether the peer is Realtek AP/STA
1671 if(pHTInfo->bRegRT2RTAggregation)
1672 {
1673 if(bssDesc->BssHT.bdSupportHT)
1674 {
1675 HTRealtekAgg = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE);
1676 if(HTRealtekAgg.Length >=5 )
1677 {
1678 bssDesc->BssHT.bdRT2RTAggregation = true;
1679
1680 if((HTRealtekAgg.Octet[4]==1) && (HTRealtekAgg.Octet[5] & 0x02))
1681 bssDesc->BssHT.bdRT2RTLongSlotTime = true;
1682 }
1683 }
1684 }
1685
1686 //
1687 // 2008/01/25 MH Get Broadcom AP IE for manamgent frame CCK rate problem.
1688 // AP can not receive CCK managemtn from from 92E.
1689 //
1690
1691 // Initialize every new bss broadcom cap exist as false..
1692 bssDesc->bBroadcomCapExist= false;
1693
1694 if(HTCapIE.Length != 0 || HTInfoIE.Length != 0)
1695 {
1696 u4Byte Length = 0;
1697
1698 FillOctetString(BroadcomElement, NULL, 0);
1699
1700 BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_1, OUI_SUBTYPE_DONT_CARE);
1701 Length += BroadcomElement.Length;
1702 BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_2, OUI_SUBTYPE_DONT_CARE);
1703 Length += BroadcomElement.Length;
1704 BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_3, OUI_SUBTYPE_DONT_CARE);
1705 Length += BroadcomElement.Length;
1706
1707 if(Length > 0)
1708 bssDesc->bBroadcomCapExist = true;
1709 }
1710
1711
1712 // For Cisco IOT issue
1713 CiscoElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_CISCO_IE, OUI_SUBTYPE_DONT_CARE);
1714 if(CiscoElement.Length != 0){ // 3: 0x00, 0x40, 0x96 ....
1715 bssDesc->bCiscoCapExist = true;
1716 }else{
1717 bssDesc->bCiscoCapExist = false;
1718 }
1719}
1720
1721
1722#endif
1723/********************************************************************************************************************
1724 *function: initialize Bss HT structure(struct PBSS_HT)
1725 * input: struct ieee80211_device *ieee
1726 * struct ieee80211_network *pNetwork //usually current network we are live in
1727 * output: none
1728 * return: none
1729 * notice: This function should ONLY be called before association
1730********************************************************************************************************************/
1731void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork)
1732{
1733 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1734// u16 nMaxAMSDUSize;
1735// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf;
1736// PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf;
1737// u8* pMcsFilter;
1738 u8 bIOTAction = 0;
1739
1740 //
1741 // Save Peer Setting before Association
1742 //
1743 IEEE80211_DEBUG(IEEE80211_DL_HT, "==============>%s()\n", __FUNCTION__);
1744 /*unmark bEnableHT flag here is the same reason why unmarked in function ieee80211_softmac_new_net. WB 2008.09.10*/
1745// if( pHTInfo->bEnableHT && pNetwork->bssht.bdSupportHT)
1746 if (pNetwork->bssht.bdSupportHT)
1747 {
1748 pHTInfo->bCurrentHTSupport = true;
1749 pHTInfo->ePeerHTSpecVer = pNetwork->bssht.bdHTSpecVer;
1750
1751 // Save HTCap and HTInfo information Element
1752 if(pNetwork->bssht.bdHTCapLen > 0 && pNetwork->bssht.bdHTCapLen <= sizeof(pHTInfo->PeerHTCapBuf))
1753 memcpy(pHTInfo->PeerHTCapBuf, pNetwork->bssht.bdHTCapBuf, pNetwork->bssht.bdHTCapLen);
1754
1755 if(pNetwork->bssht.bdHTInfoLen > 0 && pNetwork->bssht.bdHTInfoLen <= sizeof(pHTInfo->PeerHTInfoBuf))
1756 memcpy(pHTInfo->PeerHTInfoBuf, pNetwork->bssht.bdHTInfoBuf, pNetwork->bssht.bdHTInfoLen);
1757
1758 // Check whether RT to RT aggregation mode is enabled
1759 if(pHTInfo->bRegRT2RTAggregation)
1760 {
1761 pHTInfo->bCurrentRT2RTAggregation = pNetwork->bssht.bdRT2RTAggregation;
1762 pHTInfo->bCurrentRT2RTLongSlotTime = pNetwork->bssht.bdRT2RTLongSlotTime;
1763 pHTInfo->RT2RT_HT_Mode = pNetwork->bssht.RT2RT_HT_Mode;
1764 }
1765 else
1766 {
1767 pHTInfo->bCurrentRT2RTAggregation = false;
1768 pHTInfo->bCurrentRT2RTLongSlotTime = false;
1769 pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0;
1770 }
1771
1772 // Determine the IOT Peer Vendor.
1773 HTIOTPeerDetermine(ieee);
1774
1775 // Decide IOT Action
1776 // Must be called after the parameter of pHTInfo->bCurrentRT2RTAggregation is decided
1777 pHTInfo->IOTAction = 0;
1778 bIOTAction = HTIOTActIsDisableMCS14(ieee, pNetwork->bssid);
1779 if(bIOTAction)
1780 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS14;
1781
1782 bIOTAction = HTIOTActIsDisableMCS15(ieee);
1783 if(bIOTAction)
1784 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS15;
1785
1786 bIOTAction = HTIOTActIsDisableMCSTwoSpatialStream(ieee);
1787 if(bIOTAction)
1788 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_ALL_2SS;
1789
1790
1791 bIOTAction = HTIOTActIsDisableEDCATurbo(ieee, pNetwork->bssid);
1792 if(bIOTAction)
1793 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;
1794
1795 bIOTAction = HTIOTActIsMgntUseCCK6M(pNetwork);
1796 if(bIOTAction)
1797 pHTInfo->IOTAction |= HT_IOT_ACT_MGNT_USE_CCK_6M;
1798
1799 bIOTAction = HTIOTActIsCCDFsync(pNetwork->bssid);
1800 if(bIOTAction)
1801 pHTInfo->IOTAction |= HT_IOT_ACT_CDD_FSYNC;
1802
1803 bIOTAction = HTIOTActIsForcedCTS2Self(pNetwork);
1804 if(bIOTAction)
1805 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
1806
1807 //bIOTAction = HTIOTActIsForcedRTSCTS(ieee, pNetwork);
1808 //if(bIOTAction)
1809 // pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_RTS;
1810
1811#if defined(RTL8192SU)
1812 bIOTAction = HTIOCActRejcectADDBARequest(pNetwork);
1813 if(bIOTAction)
1814 pHTInfo->IOTAction |= HT_IOT_ACT_REJECT_ADDBA_REQ;
1815#endif
1816
1817 bIOTAction = HTIOCActAllowPeerAggOnePacket(ieee, pNetwork);
1818 if(bIOTAction)
1819 pHTInfo->IOTAction |= HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT;
1820
1821 bIOTAction = HTIOTActIsEDCABiasRx(ieee, pNetwork);
1822 if(bIOTAction)
1823 pHTInfo->IOTAction |= HT_IOT_ACT_EDCA_BIAS_ON_RX;
1824
1825#if defined(RTL8192SU)
1826 bIOTAction = HTIOTActDisableShortGI(ieee, pNetwork);
1827 if(bIOTAction)
1828 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_SHORT_GI;
1829
1830 bIOTAction = HTIOTActDisableHighPower(ieee, pNetwork);
1831 if(bIOTAction)
1832 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_HIGH_POWER;
1833#endif
1834
1835 bIOTAction = HTIOTActIsForcedAMSDU8K(ieee, pNetwork);
1836 if(bIOTAction)
1837 pHTInfo->IOTAction |= HT_IOT_ACT_TX_USE_AMSDU_8K;
1838
1839#if defined(RTL8192SU)
1840 bIOTAction = HTIOTActIsTxNoAggregation(ieee, pNetwork);
1841 if(bIOTAction)
1842 pHTInfo->IOTAction |= HT_IOT_ACT_TX_NO_AGGREGATION;
1843
1844 bIOTAction = HTIOTActIsDisableTx40MHz(ieee, pNetwork);
1845 if(bIOTAction)
1846 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_TX_40_MHZ;
1847
1848 bIOTAction = HTIOTActIsDisableTx2SS(ieee, pNetwork);
1849 if(bIOTAction)
1850 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_TX_2SS;
1851#endif
1852 //must after HT_IOT_ACT_TX_NO_AGGREGATION
1853 bIOTAction = HTIOTActIsForcedRTSCTS(ieee, pNetwork);
1854 if(bIOTAction)
1855 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_RTS;
1856
1857 printk("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!IOTAction = %8.8x\n", pHTInfo->IOTAction);
1858 }
1859 else
1860 {
1861 pHTInfo->bCurrentHTSupport = false;
1862 pHTInfo->bCurrentRT2RTAggregation = false;
1863 pHTInfo->bCurrentRT2RTLongSlotTime = false;
1864 pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0;
1865
1866 pHTInfo->IOTAction = 0;
1867 pHTInfo->IOTRaFunc = 0;
1868 }
1869
1870}
1871
1872void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork)
1873{
1874 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1875// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf;
1876 PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf;
1877
1878 if(pHTInfo->bCurrentHTSupport)
1879 {
1880 //
1881 // Config current operation mode.
1882 //
1883 if(pNetwork->bssht.bdHTInfoLen != 0)
1884 pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode;
1885
1886 //
1887 // <TODO: Config according to OBSS non-HT STA present!!>
1888 //
1889 }
1890}
1891
1892void HTUseDefaultSetting(struct ieee80211_device* ieee)
1893{
1894 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1895// u8 regBwOpMode;
1896
1897 if(pHTInfo->bEnableHT)
1898 {
1899 pHTInfo->bCurrentHTSupport = true;
1900
1901 pHTInfo->bCurSuppCCK = pHTInfo->bRegSuppCCK;
1902
1903 pHTInfo->bCurBW40MHz = pHTInfo->bRegBW40MHz;
1904
1905 pHTInfo->bCurShortGI20MHz= pHTInfo->bRegShortGI20MHz;
1906
1907 pHTInfo->bCurShortGI40MHz= pHTInfo->bRegShortGI40MHz;
1908
1909 pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support;
1910
1911 pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize;
1912
1913 pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable;
1914
1915 pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor;
1916
1917 pHTInfo->CurrentMPDUDensity = pHTInfo->CurrentMPDUDensity;
1918
1919 // Set BWOpMode register
1920
1921 //update RATR index0
1922 HTFilterMCSRate(ieee, ieee->Regdot11HTOperationalRateSet, ieee->dot11HTOperationalRateSet);
1923 //function below is not implemented at all. WB
1924#ifdef TODO
1925 Adapter->HalFunc.InitHalRATRTableHandler( Adapter, &pMgntInfo->dot11OperationalRateSet, pMgntInfo->dot11HTOperationalRateSet);
1926#endif
1927 ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, MCS_FILTER_ALL);
1928 ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate;
1929
1930 }
1931 else
1932 {
1933 pHTInfo->bCurrentHTSupport = false;
1934 }
1935 return;
1936}
1937/********************************************************************************************************************
1938 *function: check whether HT control field exists
1939 * input: struct ieee80211_device *ieee
1940 * u8* pFrame //coming skb->data
1941 * output: none
1942 * return: return true if HT control field exists(false otherwise)
1943 * notice:
1944********************************************************************************************************************/
1945u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame)
1946{
1947 if(ieee->pHTInfo->bCurrentHTSupport)
1948 {
1949 if( (IsQoSDataFrame(pFrame) && Frame_Order(pFrame)) == 1)
1950 {
1951 IEEE80211_DEBUG(IEEE80211_DL_HT, "HT CONTROL FILED EXIST!!\n");
1952 return true;
1953 }
1954 }
1955 return false;
1956}
1957
1958//
1959// This function set bandwidth mode in protocol layer.
1960//
1961void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1962{
1963 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
1964// u32 flags = 0;
1965
1966 if(pHTInfo->bRegBW40MHz == false)
1967 return;
1968
1969
1970
1971 // To reduce dummy operation
1972// if((pHTInfo->bCurBW40MHz==false && Bandwidth==HT_CHANNEL_WIDTH_20) ||
1973// (pHTInfo->bCurBW40MHz==true && Bandwidth==HT_CHANNEL_WIDTH_20_40 && Offset==pHTInfo->CurSTAExtChnlOffset))
1974// return;
1975
1976// spin_lock_irqsave(&(ieee->bw_spinlock), flags);
1977 if(pHTInfo->bSwBwInProgress) {
1978// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags);
1979 return;
1980 }
1981 //if in half N mode, set to 20M bandwidth please 09.08.2008 WB.
1982 if(Bandwidth==HT_CHANNEL_WIDTH_20_40 && (!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)))
1983 {
1984 // Handle Illegal extention channel offset!!
1985 if(ieee->current_network.channel<2 && Offset==HT_EXTCHNL_OFFSET_LOWER)
1986 Offset = HT_EXTCHNL_OFFSET_NO_EXT;
1987 if(Offset==HT_EXTCHNL_OFFSET_UPPER || Offset==HT_EXTCHNL_OFFSET_LOWER) {
1988 pHTInfo->bCurBW40MHz = true;
1989 pHTInfo->CurSTAExtChnlOffset = Offset;
1990 } else {
1991 pHTInfo->bCurBW40MHz = false;
1992 pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT;
1993 }
1994 } else {
1995 pHTInfo->bCurBW40MHz = false;
1996 pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT;
1997 }
1998
1999 pHTInfo->bSwBwInProgress = true;
2000
2001 // TODO: 2007.7.13 by Emily Wait 2000ms in order to garantee that switching
2002 // bandwidth is executed after scan is finished. It is a temporal solution
2003 // because software should ganrantee the last operation of switching bandwidth
2004 // is executed properlly.
2005 HTSetConnectBwModeCallback(ieee);
2006
2007// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags);
2008}
2009
2010void HTSetConnectBwModeCallback(struct ieee80211_device* ieee)
2011{
2012 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
2013
2014 IEEE80211_DEBUG(IEEE80211_DL_HT, "======>%s()\n", __FUNCTION__);
2015 if(pHTInfo->bCurBW40MHz)
2016 {
2017 if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_UPPER)
2018 ieee->set_chan(ieee->dev, ieee->current_network.channel+2);
2019 else if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_LOWER)
2020 ieee->set_chan(ieee->dev, ieee->current_network.channel-2);
2021 else
2022 ieee->set_chan(ieee->dev, ieee->current_network.channel);
2023
2024 ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset);
2025 } else {
2026 ieee->set_chan(ieee->dev, ieee->current_network.channel);
2027 ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
2028 }
2029
2030 pHTInfo->bSwBwInProgress = false;
2031}
2032
2033#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2034EXPORT_SYMBOL_NOVERS(HTUpdateSelfAndPeerSetting);
2035#else
2036EXPORT_SYMBOL(HTUpdateSelfAndPeerSetting);
2037#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h
new file mode 100644
index 00000000000..f7b882b99d1
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h
@@ -0,0 +1,749 @@
1#ifndef __INC_QOS_TYPE_H
2#define __INC_QOS_TYPE_H
3
4//#include "EndianFree.h"
5#define BIT0 0x00000001
6#define BIT1 0x00000002
7#define BIT2 0x00000004
8#define BIT3 0x00000008
9#define BIT4 0x00000010
10#define BIT5 0x00000020
11#define BIT6 0x00000040
12#define BIT7 0x00000080
13#define BIT8 0x00000100
14#define BIT9 0x00000200
15#define BIT10 0x00000400
16#define BIT11 0x00000800
17#define BIT12 0x00001000
18#define BIT13 0x00002000
19#define BIT14 0x00004000
20#define BIT15 0x00008000
21#define BIT16 0x00010000
22#define BIT17 0x00020000
23#define BIT18 0x00040000
24#define BIT19 0x00080000
25#define BIT20 0x00100000
26#define BIT21 0x00200000
27#define BIT22 0x00400000
28#define BIT23 0x00800000
29#define BIT24 0x01000000
30#define BIT25 0x02000000
31#define BIT26 0x04000000
32#define BIT27 0x08000000
33#define BIT28 0x10000000
34#define BIT29 0x20000000
35#define BIT30 0x40000000
36#define BIT31 0x80000000
37
38#define MAX_WMMELE_LENGTH 64
39
40//
41// QoS mode.
42// enum 0, 1, 2, 4: since we can use the OR(|) operation.
43//
44// QOS_MODE is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko.
45//typedef enum _QOS_MODE{
46// QOS_DISABLE = 0,
47// QOS_WMM = 1,
48// QOS_EDCA = 2,
49// QOS_HCCA = 4,
50//}QOS_MODE,*PQOS_MODE;
51//
52typedef u32 QOS_MODE, *PQOS_MODE;
53#define QOS_DISABLE 0
54#define QOS_WMM 1
55#define QOS_WMMSA 2
56#define QOS_EDCA 4
57#define QOS_HCCA 8
58#define QOS_WMM_UAPSD 16 //WMM Power Save, 2006-06-14 Isaiah
59
60#define AC_PARAM_SIZE 4
61#define WMM_PARAM_ELE_BODY_LEN 18
62
63//
64// QoS ACK Policy Field Values
65// Ref: WMM spec 2.1.6: QoS Control Field, p.10.
66//
67typedef enum _ACK_POLICY{
68 eAckPlc0_ACK = 0x00,
69 eAckPlc1_NoACK = 0x01,
70}ACK_POLICY,*PACK_POLICY;
71
72#define WMM_PARAM_ELEMENT_SIZE (8+(4*AC_PARAM_SIZE))
73#if 0
74#define GET_QOS_CTRL(_pStart) ReadEF2Byte((u8 *)(_pStart) + 24)
75#define SET_QOS_CTRL(_pStart, _value) WriteEF2Byte((u8 *)(_pStart) + 24, _value)
76
77// WMM control field.
78#define GET_QOS_CTRL_WMM_UP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 3))
79#define SET_QOS_CTRL_WMM_UP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 3, (u8)(_value))
80
81#define GET_QOS_CTRL_WMM_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
82#define SET_QOS_CTRL_WMM_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
83
84#define GET_QOS_CTRL_WMM_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
85#define SET_QOS_CTRL_WMM_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
86
87// 802.11e control field (by STA, data)
88#define GET_QOS_CTRL_STA_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
89#define SET_QOS_CTRL_STA_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
90
91#define GET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
92#define SET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
93
94#define GET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
95#define SET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
96
97#define GET_QOS_CTRL_STA_DATA_TXOP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
98#define SET_QOS_CTRL_STA_DATA_TXOP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
99
100#define GET_QOS_CTRL_STA_DATA_QSIZE(_pStart) GET_QOS_CTRL_STA_DATA_TXOP(_pStart)
101#define SET_QOS_CTRL_STA_DATA_QSIZE(_pStart, _value) SET_QOS_CTRL_STA_DATA_TXOP(_pStart)
102
103// 802.11e control field (by HC, data)
104#define GET_QOS_CTRL_HC_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
105#define SET_QOS_CTRL_HC_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
106
107#define GET_QOS_CTRL_HC_DATA_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
108#define SET_QOS_CTRL_HC_DATA_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
109
110#define GET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
111#define SET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
112
113#define GET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
114#define SET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
115
116// 802.11e control field (by HC, CFP)
117#define GET_QOS_CTRL_HC_CFP_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
118#define SET_QOS_CTRL_HC_CFP_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
119
120#define GET_QOS_CTRL_HC_CFP_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
121#define SET_QOS_CTRL_HC_CFP_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
122
123#define GET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
124#define SET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
125
126#define GET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
127#define SET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
128
129#define SET_WMM_QOS_INFO_FIELD(_pStart, _val) WriteEF1Byte(_pStart, _val)
130
131#define GET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 4)
132#define SET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 4, _val)
133
134#define GET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 7, 1)
135#define SET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 7, 1, _val)
136
137#define GET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 1)
138#define SET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 1, _val)
139
140#define GET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 1, 1)
141#define SET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 1, 1, _val)
142
143#define GET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 2, 1)
144#define SET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 2, 1, _val)
145
146#define GET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 3, 1)
147#define SET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 3, 1, _val)
148
149#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) LE_BITS_TO_1BYTE(_pStart, 5, 2)
150#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val)
151
152
153#define WMM_INFO_ELEMENT_SIZE 7
154
155#define GET_WMM_INFO_ELE_OUI(_pStart) ((u8 *)(_pStart))
156#define SET_WMM_INFO_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3);
157
158#define GET_WMM_INFO_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) )
159#define SET_WMM_INFO_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) )
160
161#define GET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) )
162#define SET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) )
163
164#define GET_WMM_INFO_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) )
165#define SET_WMM_INFO_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) )
166
167#define GET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) )
168#define SET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) )
169
170
171
172#define GET_WMM_AC_PARAM_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 4) )
173#define SET_WMM_AC_PARAM_AIFSN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 0, 4, _val)
174
175#define GET_WMM_AC_PARAM_ACM(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 4, 1) )
176#define SET_WMM_AC_PARAM_ACM(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 4, 1, _val)
177
178#define GET_WMM_AC_PARAM_ACI(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 5, 2) )
179#define SET_WMM_AC_PARAM_ACI(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 5, 2, _val)
180
181#define GET_WMM_AC_PARAM_ACI_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 8) )
182#define SET_WMM_AC_PARAM_ACI_AIFSN(_pStart, _val) SET_BTIS_TO_LE_4BYTE(_pStart, 0, 8, _val)
183
184#define GET_WMM_AC_PARAM_ECWMIN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 8, 4) )
185#define SET_WMM_AC_PARAM_ECWMIN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 8, 4, _val)
186
187#define GET_WMM_AC_PARAM_ECWMAX(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 12, 4) )
188#define SET_WMM_AC_PARAM_ECWMAX(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 12, 4, _val)
189
190#define GET_WMM_AC_PARAM_TXOP_LIMIT(_pStart) ( (u16)LE_BITS_TO_4BYTE(_pStart, 16, 16) )
191#define SET_WMM_AC_PARAM_TXOP_LIMIT(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 16, 16, _val)
192
193
194
195
196#define GET_WMM_PARAM_ELE_OUI(_pStart) ((u8 *)(_pStart))
197#define SET_WMM_PARAM_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3)
198
199#define GET_WMM_PARAM_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) )
200#define SET_WMM_PARAM_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) )
201
202#define GET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) )
203#define SET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) )
204
205#define GET_WMM_PARAM_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) )
206#define SET_WMM_PARAM_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) )
207
208#define GET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) )
209#define SET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) )
210
211#define GET_WMM_PARAM_ELE_AC_PARAM(_pStart) ( (u8 *)(_pStart)+8 )
212#define SET_WMM_PARAM_ELE_AC_PARAM(_pStart, _pVal) PlatformMoveMemory((_pStart)+8, _pVal, 16)
213#endif
214
215//
216// QoS Control Field
217// Ref:
218// 1. WMM spec 2.1.6: QoS Control Field, p.9.
219// 2. 802.11e/D13.0 7.1.3.5, p.26.
220//
221typedef union _QOS_CTRL_FIELD{
222 u8 charData[2];
223 u16 shortData;
224
225 // WMM spec
226 struct
227 {
228 u8 UP:3;
229 u8 usRsvd1:1;
230 u8 EOSP:1;
231 u8 AckPolicy:2;
232 u8 usRsvd2:1;
233 u8 ucRsvdByte;
234 }WMM;
235
236 // 802.11e: QoS data type frame sent by non-AP QSTAs.
237 struct
238 {
239 u8 TID:4;
240 u8 bIsQsize:1;// 0: BIT[8:15] is TXOP Duration Requested, 1: BIT[8:15] is Queue Size.
241 u8 AckPolicy:2;
242 u8 usRsvd:1;
243 u8 TxopOrQsize; // (BIT4=0)TXOP Duration Requested or (BIT4=1)Queue Size.
244 }BySta;
245
246 // 802.11e: QoS data, QoS Null, and QoS Data+CF-Ack frames sent by HC.
247 struct
248 {
249 u8 TID:4;
250 u8 EOSP:1;
251 u8 AckPolicy:2;
252 u8 usRsvd:1;
253 u8 PSBufState; // QAP PS Buffer State.
254 }ByHc_Data;
255
256 // 802.11e: QoS (+) CF-Poll frames sent by HC.
257 struct
258 {
259 u8 TID:4;
260 u8 EOSP:1;
261 u8 AckPolicy:2;
262 u8 usRsvd:1;
263 u8 TxopLimit; // TXOP Limit.
264 }ByHc_CFP;
265
266}QOS_CTRL_FIELD, *PQOS_CTRL_FIELD;
267
268
269//
270// QoS Info Field
271// Ref:
272// 1. WMM spec 2.2.1: WME Information Element, p.11.
273// 2. 8185 QoS code: QOS_INFO [def. in QoS_mp.h]
274//
275typedef union _QOS_INFO_FIELD{
276 u8 charData;
277
278 struct
279 {
280 u8 ucParameterSetCount:4;
281 u8 ucReserved:4;
282 }WMM;
283
284 struct
285 {
286 //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah
287 u8 ucAC_VO_UAPSD:1;
288 u8 ucAC_VI_UAPSD:1;
289 u8 ucAC_BE_UAPSD:1;
290 u8 ucAC_BK_UAPSD:1;
291 u8 ucReserved1:1;
292 u8 ucMaxSPLen:2;
293 u8 ucReserved2:1;
294
295 }ByWmmPsSta;
296
297 struct
298 {
299 //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah
300 u8 ucParameterSetCount:4;
301 u8 ucReserved:3;
302 u8 ucApUapsd:1;
303 }ByWmmPsAp;
304
305 struct
306 {
307 u8 ucAC3_UAPSD:1;
308 u8 ucAC2_UAPSD:1;
309 u8 ucAC1_UAPSD:1;
310 u8 ucAC0_UAPSD:1;
311 u8 ucQAck:1;
312 u8 ucMaxSPLen:2;
313 u8 ucMoreDataAck:1;
314 } By11eSta;
315
316 struct
317 {
318 u8 ucParameterSetCount:4;
319 u8 ucQAck:1;
320 u8 ucQueueReq:1;
321 u8 ucTXOPReq:1;
322 u8 ucReserved:1;
323 } By11eAp;
324
325 struct
326 {
327 u8 ucReserved1:4;
328 u8 ucQAck:1;
329 u8 ucReserved2:2;
330 u8 ucMoreDataAck:1;
331 } ByWmmsaSta;
332
333 struct
334 {
335 u8 ucReserved1:4;
336 u8 ucQAck:1;
337 u8 ucQueueReq:1;
338 u8 ucTXOPReq:1;
339 u8 ucReserved2:1;
340 } ByWmmsaAp;
341
342 struct
343 {
344 u8 ucAC3_UAPSD:1;
345 u8 ucAC2_UAPSD:1;
346 u8 ucAC1_UAPSD:1;
347 u8 ucAC0_UAPSD:1;
348 u8 ucQAck:1;
349 u8 ucMaxSPLen:2;
350 u8 ucMoreDataAck:1;
351 } ByAllSta;
352
353 struct
354 {
355 u8 ucParameterSetCount:4;
356 u8 ucQAck:1;
357 u8 ucQueueReq:1;
358 u8 ucTXOPReq:1;
359 u8 ucApUapsd:1;
360 } ByAllAp;
361
362}QOS_INFO_FIELD, *PQOS_INFO_FIELD;
363
364#if 0
365//
366// WMM Information Element
367// Ref: WMM spec 2.2.1: WME Information Element, p.10.
368//
369typedef struct _WMM_INFO_ELEMENT{
370// u8 ElementID;
371// u8 Length;
372 u8 OUI[3];
373 u8 OUI_Type;
374 u8 OUI_SubType;
375 u8 Version;
376 QOS_INFO_FIELD QosInfo;
377}WMM_INFO_ELEMENT, *PWMM_INFO_ELEMENT;
378#endif
379
380//
381// ACI to AC coding.
382// Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
383//
384// AC_CODING is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko.
385//typedef enum _AC_CODING{
386// AC0_BE = 0, // ACI: 0x00 // Best Effort
387// AC1_BK = 1, // ACI: 0x01 // Background
388// AC2_VI = 2, // ACI: 0x10 // Video
389// AC3_VO = 3, // ACI: 0x11 // Voice
390// AC_MAX = 4, // Max: define total number; Should not to be used as a real enum.
391//}AC_CODING,*PAC_CODING;
392//
393typedef u32 AC_CODING;
394#define AC0_BE 0 // ACI: 0x00 // Best Effort
395#define AC1_BK 1 // ACI: 0x01 // Background
396#define AC2_VI 2 // ACI: 0x10 // Video
397#define AC3_VO 3 // ACI: 0x11 // Voice
398#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
399
400//
401// ACI/AIFSN Field.
402// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
403//
404typedef union _ACI_AIFSN{
405 u8 charData;
406
407 struct
408 {
409 u8 AIFSN:4;
410 u8 ACM:1;
411 u8 ACI:2;
412 u8 Reserved:1;
413 }f; // Field
414}ACI_AIFSN, *PACI_AIFSN;
415
416//
417// ECWmin/ECWmax field.
418// Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
419//
420typedef union _ECW{
421 u8 charData;
422 struct
423 {
424 u8 ECWmin:4;
425 u8 ECWmax:4;
426 }f; // Field
427}ECW, *PECW;
428
429//
430// AC Parameters Record Format.
431// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
432//
433typedef union _AC_PARAM{
434 u32 longData;
435 u8 charData[4];
436
437 struct
438 {
439 ACI_AIFSN AciAifsn;
440 ECW Ecw;
441 u16 TXOPLimit;
442 }f; // Field
443}AC_PARAM, *PAC_PARAM;
444
445
446
447//
448// QoS element subtype
449//
450typedef enum _QOS_ELE_SUBTYPE{
451 QOSELE_TYPE_INFO = 0x00, // 0x00: Information element
452 QOSELE_TYPE_PARAM = 0x01, // 0x01: parameter element
453}QOS_ELE_SUBTYPE,*PQOS_ELE_SUBTYPE;
454
455
456//
457// Direction Field Values.
458// Ref: WMM spec 2.2.11: WME TSPEC Element, p.18.
459//
460typedef enum _DIRECTION_VALUE{
461 DIR_UP = 0, // 0x00 // UpLink
462 DIR_DOWN = 1, // 0x01 // DownLink
463 DIR_DIRECT = 2, // 0x10 // DirectLink
464 DIR_BI_DIR = 3, // 0x11 // Bi-Direction
465}DIRECTION_VALUE,*PDIRECTION_VALUE;
466
467
468//
469// TS Info field in WMM TSPEC Element.
470// Ref:
471// 1. WMM spec 2.2.11: WME TSPEC Element, p.18.
472// 2. 8185 QoS code: QOS_TSINFO [def. in QoS_mp.h]
473//
474typedef union _QOS_TSINFO{
475 u8 charData[3];
476 struct {
477 u8 ucTrafficType:1; //WMM is reserved
478 u8 ucTSID:4;
479 u8 ucDirection:2;
480 u8 ucAccessPolicy:2; //WMM: bit8=0, bit7=1
481 u8 ucAggregation:1; //WMM is reserved
482 u8 ucPSB:1; //WMMSA is APSD
483 u8 ucUP:3;
484 u8 ucTSInfoAckPolicy:2; //WMM is reserved
485 u8 ucSchedule:1; //WMM is reserved
486 u8 ucReserved:7;
487 }field;
488}QOS_TSINFO, *PQOS_TSINFO;
489
490//
491// WMM TSPEC Body.
492// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16.
493//
494typedef union _TSPEC_BODY{
495 u8 charData[55];
496
497 struct
498 {
499 QOS_TSINFO TSInfo; //u8 TSInfo[3];
500 u16 NominalMSDUsize;
501 u16 MaxMSDUsize;
502 u32 MinServiceItv;
503 u32 MaxServiceItv;
504 u32 InactivityItv;
505 u32 SuspenItv;
506 u32 ServiceStartTime;
507 u32 MinDataRate;
508 u32 MeanDataRate;
509 u32 PeakDataRate;
510 u32 MaxBurstSize;
511 u32 DelayBound;
512 u32 MinPhyRate;
513 u16 SurplusBandwidthAllowance;
514 u16 MediumTime;
515 } f; // Field
516}TSPEC_BODY, *PTSPEC_BODY;
517
518
519//
520// WMM TSPEC Element.
521// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16.
522//
523typedef struct _WMM_TSPEC{
524 u8 ID;
525 u8 Length;
526 u8 OUI[3];
527 u8 OUI_Type;
528 u8 OUI_SubType;
529 u8 Version;
530 TSPEC_BODY Body;
531} WMM_TSPEC, *PWMM_TSPEC;
532
533//
534// ACM implementation method.
535// Annie, 2005-12-13.
536//
537typedef enum _ACM_METHOD{
538 eAcmWay0_SwAndHw = 0, // By SW and HW.
539 eAcmWay1_HW = 1, // By HW.
540 eAcmWay2_SW = 2, // By SW.
541}ACM_METHOD,*PACM_METHOD;
542
543
544typedef struct _ACM{
545// u8 RegEnableACM;
546 u64 UsedTime;
547 u64 MediumTime;
548 u8 HwAcmCtl; // TRUE: UsedTime exceed => Do NOT USE this AC. It wll be written to ACM_CONTROL(0xBF BIT 0/1/2 in 8185B).
549}ACM, *PACM;
550
551typedef u8 AC_UAPSD, *PAC_UAPSD;
552
553#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
554#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
555
556#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
557#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
558
559#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2)
560#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2)
561
562#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3)
563#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
564
565
566//typedef struct _TCLASS{
567// TODO
568//} TCLASS, *PTCLASS;
569typedef union _QOS_TCLAS{
570
571 struct _TYPE_GENERAL{
572 u8 Priority;
573 u8 ClassifierType;
574 u8 Mask;
575 } TYPE_GENERAL;
576
577 struct _TYPE0_ETH{
578 u8 Priority;
579 u8 ClassifierType;
580 u8 Mask;
581 u8 SrcAddr[6];
582 u8 DstAddr[6];
583 u16 Type;
584 } TYPE0_ETH;
585
586 struct _TYPE1_IPV4{
587 u8 Priority;
588 u8 ClassifierType;
589 u8 Mask;
590 u8 Version;
591 u8 SrcIP[4];
592 u8 DstIP[4];
593 u16 SrcPort;
594 u16 DstPort;
595 u8 DSCP;
596 u8 Protocol;
597 u8 Reserved;
598 } TYPE1_IPV4;
599
600 struct _TYPE1_IPV6{
601 u8 Priority;
602 u8 ClassifierType;
603 u8 Mask;
604 u8 Version;
605 u8 SrcIP[16];
606 u8 DstIP[16];
607 u16 SrcPort;
608 u16 DstPort;
609 u8 FlowLabel[3];
610 } TYPE1_IPV6;
611
612 struct _TYPE2_8021Q{
613 u8 Priority;
614 u8 ClassifierType;
615 u8 Mask;
616 u16 TagType;
617 } TYPE2_8021Q;
618} QOS_TCLAS, *PQOS_TCLAS;
619
620//typedef struct _WMM_TSTREAM{
621//
622//- TSPEC
623//- AC (which to mapping)
624//} WMM_TSTREAM, *PWMM_TSTREAM;
625typedef struct _QOS_TSTREAM{
626 u8 AC;
627 WMM_TSPEC TSpec;
628 QOS_TCLAS TClass;
629} QOS_TSTREAM, *PQOS_TSTREAM;
630
631//typedef struct _U_APSD{
632//- TriggerEnable [4]
633//- MaxSPLength
634//- HighestAcBuffered
635//} U_APSD, *PU_APSD;
636
637//joseph TODO:
638// UAPSD function should be implemented by 2 data structure
639// "Qos control field" and "Qos info field"
640//typedef struct _QOS_UAPSD{
641// u8 bTriggerEnable[4];
642// u8 MaxSPLength;
643// u8 HighestBufAC;
644//} QOS_UAPSD, *PQOS_APSD;
645
646//----------------------------------------------------------------------------
647// 802.11 Management frame Status Code field
648//----------------------------------------------------------------------------
649typedef struct _OCTET_STRING{
650 u8 *Octet;
651 u16 Length;
652}OCTET_STRING, *POCTET_STRING;
653#if 0
654#define FillOctetString(_os,_octet,_len) \
655 (_os).Octet=(u8 *)(_octet); \
656 (_os).Length=(_len);
657
658#define WMM_ELEM_HDR_LEN 6
659#define WMMElemSkipHdr(_osWMMElem) \
660 (_osWMMElem).Octet += WMM_ELEM_HDR_LEN; \
661 (_osWMMElem).Length -= WMM_ELEM_HDR_LEN;
662#endif
663//
664// STA QoS data.
665// Ref: DOT11_QOS in 8185 code. [def. in QoS_mp.h]
666//
667typedef struct _STA_QOS{
668 //DECLARE_RT_OBJECT(STA_QOS);
669 u8 WMMIEBuf[MAX_WMMELE_LENGTH];
670 u8* WMMIE;
671
672 // Part 1. Self QoS Mode.
673 QOS_MODE QosCapability; //QoS Capability, 2006-06-14 Isaiah
674 QOS_MODE CurrentQosMode;
675
676 // For WMM Power Save Mode :
677 // ACs are trigger/delivery enabled or legacy power save enabled. 2006-06-13 Isaiah
678 AC_UAPSD b4ac_Uapsd; //VoUapsd(bit0), ViUapsd(bit1), BkUapsd(bit2), BeUapsd(bit3),
679 AC_UAPSD Curr4acUapsd;
680 u8 bInServicePeriod;
681 u8 MaxSPLength;
682 int NumBcnBeforeTrigger;
683
684 // Part 2. EDCA Parameter (perAC)
685 u8 * pWMMInfoEle;
686 u8 WMMParamEle[WMM_PARAM_ELEMENT_SIZE];
687 u8 WMMPELength;
688
689 // <Bruce_Note>
690 //2 ToDo: remove the Qos Info Field and replace it by the above WMM Info element.
691 // By Bruce, 2008-01-30.
692 // Part 2. EDCA Parameter (perAC)
693 QOS_INFO_FIELD QosInfoField_STA; // Maintained by STA
694 QOS_INFO_FIELD QosInfoField_AP; // Retrieved from AP
695
696 AC_PARAM CurAcParameters[4];
697
698 // Part 3. ACM
699 ACM acm[4];
700 ACM_METHOD AcmMethod;
701
702 // Part 4. Per TID (Part 5: TCLASS will be described by TStream)
703 QOS_TSTREAM TStream[16];
704 WMM_TSPEC TSpec;
705
706 u32 QBssWirelessMode;
707
708 // No Ack Setting
709 u8 bNoAck;
710
711 // Enable/Disable Rx immediate BA capability.
712 u8 bEnableRxImmBA;
713
714}STA_QOS, *PSTA_QOS;
715
716//
717// BSS QOS data.
718// Ref: BssDscr in 8185 code. [def. in BssDscr.h]
719//
720typedef struct _BSS_QOS{
721 QOS_MODE bdQoSMode;
722
723 u8 bdWMMIEBuf[MAX_WMMELE_LENGTH];
724 u8* bdWMMIE;
725
726 QOS_ELE_SUBTYPE EleSubType;
727
728 u8 * pWMMInfoEle;
729 u8 * pWMMParamEle;
730
731 QOS_INFO_FIELD QosInfoField;
732 AC_PARAM AcParameter[4];
733}BSS_QOS, *PBSS_QOS;
734
735
736//
737// Ref: sQoSCtlLng and QoSCtl definition in 8185 QoS code.
738//#define QoSCtl (( (Adapter->bRegQoS) && (Adapter->dot11QoS.QoSMode &(QOS_EDCA|QOS_HCCA)) ) ?sQoSCtlLng:0)
739//
740#define sQoSCtlLng 2
741#define QOS_CTRL_LEN(_QosMode) ((_QosMode > QOS_DISABLE)? sQoSCtlLng : 0)
742
743
744//Added by joseph
745//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP
746//#define UP2AC(up) ((up<3)?((up==0)?1:0):(up>>1))
747#define IsACValid(ac) ((ac<=7 )?true:false )
748
749#endif // #ifndef __INC_QOS_TYPE_H
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h
new file mode 100644
index 00000000000..baaac2149de
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h
@@ -0,0 +1,56 @@
1#ifndef _TSTYPE_H_
2#define _TSTYPE_H_
3#include "rtl819x_Qos.h"
4#define TS_SETUP_TIMEOUT 60 // In millisecond
5#define TS_INACT_TIMEOUT 60
6#define TS_ADDBA_DELAY 60
7
8#define TOTAL_TS_NUM 16
9#define TCLAS_NUM 4
10
11// This define the Tx/Rx directions
12typedef enum _TR_SELECT {
13 TX_DIR = 0,
14 RX_DIR = 1,
15} TR_SELECT, *PTR_SELECT;
16
17typedef struct _TS_COMMON_INFO{
18 struct list_head List;
19 struct timer_list SetupTimer;
20 struct timer_list InactTimer;
21 u8 Addr[6];
22 TSPEC_BODY TSpec;
23 QOS_TCLAS TClass[TCLAS_NUM];
24 u8 TClasProc;
25 u8 TClasNum;
26} TS_COMMON_INFO, *PTS_COMMON_INFO;
27
28typedef struct _TX_TS_RECORD{
29 TS_COMMON_INFO TsCommonInfo;
30 u16 TxCurSeq;
31 BA_RECORD TxPendingBARecord; // For BA Originator
32 BA_RECORD TxAdmittedBARecord; // For BA Originator
33// QOS_DL_RECORD DLRecord;
34 u8 bAddBaReqInProgress;
35 u8 bAddBaReqDelayed;
36 u8 bUsingBa;
37 struct timer_list TsAddBaTimer;
38 u8 num;
39} TX_TS_RECORD, *PTX_TS_RECORD;
40
41typedef struct _RX_TS_RECORD {
42 TS_COMMON_INFO TsCommonInfo;
43 u16 RxIndicateSeq;
44 u16 RxTimeoutIndicateSeq;
45 struct list_head RxPendingPktList;
46 struct timer_list RxPktPendingTimer;
47 BA_RECORD RxAdmittedBARecord; // For BA Recepient
48 u16 RxLastSeqNum;
49 u8 RxLastFragNum;
50 u8 num;
51// QOS_DL_RECORD DLRecord;
52} RX_TS_RECORD, *PRX_TS_RECORD;
53
54
55#endif
56
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c
new file mode 100644
index 00000000000..6fb7033ed36
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c
@@ -0,0 +1,667 @@
1#include "ieee80211.h"
2#include <linux/etherdevice.h>
3#include "rtl819x_TS.h"
4
5#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
6#define list_for_each_entry_safe(pos, n, head, member) \
7 for (pos = list_entry((head)->next, typeof(*pos), member), \
8 n = list_entry(pos->member.next, typeof(*pos), member); \
9 &pos->member != (head); \
10 pos = n, n = list_entry(n->member.next, typeof(*n), member))
11#endif
12void TsSetupTimeOut(unsigned long data)
13{
14 // Not implement yet
15 // This is used for WMMSA and ACM , that would send ADDTSReq frame.
16}
17
18void TsInactTimeout(unsigned long data)
19{
20 // Not implement yet
21 // This is used for WMMSA and ACM.
22 // This function would be call when TS is no Tx/Rx for some period of time.
23}
24
25/********************************************************************************************************************
26 *function: I still not understand this function, so wait for further implementation
27 * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer
28 * return: NULL
29 * notice:
30********************************************************************************************************************/
31#if 1
32void RxPktPendingTimeout(unsigned long data)
33{
34 PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data;
35 struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]);
36
37 PRX_REORDER_ENTRY pReorderEntry = NULL;
38
39 //u32 flags = 0;
40 unsigned long flags = 0;
41 struct ieee80211_rxb *stats_IndicateArray[REORDER_WIN_SIZE];
42 u8 index = 0;
43 bool bPktInBuf = false;
44
45
46 spin_lock_irqsave(&(ieee->reorder_spinlock), flags);
47 //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
48 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"==================>%s()\n",__FUNCTION__);
49 if(pRxTs->RxTimeoutIndicateSeq != 0xffff)
50 {
51 // Indicate the pending packets sequentially according to SeqNum until meet the gap.
52 while(!list_empty(&pRxTs->RxPendingPktList))
53 {
54 pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTs->RxPendingPktList.prev,RX_REORDER_ENTRY,List);
55 if(index == 0)
56 pRxTs->RxIndicateSeq = pReorderEntry->SeqNum;
57
58 if( SN_LESS(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) ||
59 SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) )
60 {
61 list_del_init(&pReorderEntry->List);
62
63 if(SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq))
64 pRxTs->RxIndicateSeq = (pRxTs->RxIndicateSeq + 1) % 4096;
65
66 IEEE80211_DEBUG(IEEE80211_DL_REORDER,"RxPktPendingTimeout(): IndicateSeq: %d\n", pReorderEntry->SeqNum);
67 stats_IndicateArray[index] = pReorderEntry->prxb;
68 index++;
69
70 list_add_tail(&pReorderEntry->List, &ieee->RxReorder_Unused_List);
71 }
72 else
73 {
74 bPktInBuf = true;
75 break;
76 }
77 }
78 }
79
80 if(index>0)
81 {
82 // Set RxTimeoutIndicateSeq to 0xffff to indicate no pending packets in buffer now.
83 pRxTs->RxTimeoutIndicateSeq = 0xffff;
84
85 // Indicate packets
86 if(index > REORDER_WIN_SIZE){
87 IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n");
88 spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags);
89 return;
90 }
91 ieee80211_indicate_packets(ieee, stats_IndicateArray, index);
92 bPktInBuf = false;
93
94 }
95
96 if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff))
97 {
98 pRxTs->RxTimeoutIndicateSeq = pRxTs->RxIndicateSeq;
99#if 0
100 if(timer_pending(&pTS->RxPktPendingTimer))
101 del_timer_sync(&pTS->RxPktPendingTimer);
102 pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime);
103 add_timer(&pTS->RxPktPendingTimer);
104#else
105 mod_timer(&pRxTs->RxPktPendingTimer, jiffies + MSECS(ieee->pHTInfo->RxReorderPendingTime));
106#endif
107
108#if 0
109 if(timer_pending(&pRxTs->RxPktPendingTimer))
110 del_timer_sync(&pRxTs->RxPktPendingTimer);
111 pRxTs->RxPktPendingTimer.expires = jiffies + ieee->pHTInfo->RxReorderPendingTime;
112 add_timer(&pRxTs->RxPktPendingTimer);
113#endif
114 }
115 spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags);
116 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
117}
118#endif
119
120/********************************************************************************************************************
121 *function: Add BA timer function
122 * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer
123 * return: NULL
124 * notice:
125********************************************************************************************************************/
126void TsAddBaProcess(unsigned long data)
127{
128 PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data;
129 u8 num = pTxTs->num;
130 struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[num]);
131
132 TsInitAddBA(ieee, pTxTs, BA_POLICY_IMMEDIATE, false);
133 IEEE80211_DEBUG(IEEE80211_DL_BA, "TsAddBaProcess(): ADDBA Req is started!! \n");
134}
135
136
137void ResetTsCommonInfo(PTS_COMMON_INFO pTsCommonInfo)
138{
139 memset(pTsCommonInfo->Addr, 0, 6);
140 memset(&pTsCommonInfo->TSpec, 0, sizeof(TSPEC_BODY));
141 memset(&pTsCommonInfo->TClass, 0, sizeof(QOS_TCLAS)*TCLAS_NUM);
142 pTsCommonInfo->TClasProc = 0;
143 pTsCommonInfo->TClasNum = 0;
144}
145
146void ResetTxTsEntry(PTX_TS_RECORD pTS)
147{
148 ResetTsCommonInfo(&pTS->TsCommonInfo);
149 pTS->TxCurSeq = 0;
150 pTS->bAddBaReqInProgress = false;
151 pTS->bAddBaReqDelayed = false;
152 pTS->bUsingBa = false;
153 ResetBaEntry(&pTS->TxAdmittedBARecord); //For BA Originator
154 ResetBaEntry(&pTS->TxPendingBARecord);
155}
156
157void ResetRxTsEntry(PRX_TS_RECORD pTS)
158{
159 ResetTsCommonInfo(&pTS->TsCommonInfo);
160 pTS->RxIndicateSeq = 0xffff; // This indicate the RxIndicateSeq is not used now!!
161 pTS->RxTimeoutIndicateSeq = 0xffff; // This indicate the RxTimeoutIndicateSeq is not used now!!
162 ResetBaEntry(&pTS->RxAdmittedBARecord); // For BA Recepient
163}
164
165void TSInitialize(struct ieee80211_device *ieee)
166{
167 PTX_TS_RECORD pTxTS = ieee->TxTsRecord;
168 PRX_TS_RECORD pRxTS = ieee->RxTsRecord;
169 PRX_REORDER_ENTRY pRxReorderEntry = ieee->RxReorderEntry;
170 u8 count = 0;
171 IEEE80211_DEBUG(IEEE80211_DL_TS, "==========>%s()\n", __FUNCTION__);
172 // Initialize Tx TS related info.
173 INIT_LIST_HEAD(&ieee->Tx_TS_Admit_List);
174 INIT_LIST_HEAD(&ieee->Tx_TS_Pending_List);
175 INIT_LIST_HEAD(&ieee->Tx_TS_Unused_List);
176
177 for(count = 0; count < TOTAL_TS_NUM; count++)
178 {
179 //
180 pTxTS->num = count;
181 // The timers for the operation of Traffic Stream and Block Ack.
182 // DLS related timer will be add here in the future!!
183 init_timer(&pTxTS->TsCommonInfo.SetupTimer);
184 pTxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pTxTS;
185 pTxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut;
186
187 init_timer(&pTxTS->TsCommonInfo.InactTimer);
188 pTxTS->TsCommonInfo.InactTimer.data = (unsigned long)pTxTS;
189 pTxTS->TsCommonInfo.InactTimer.function = TsInactTimeout;
190
191 init_timer(&pTxTS->TsAddBaTimer);
192 pTxTS->TsAddBaTimer.data = (unsigned long)pTxTS;
193 pTxTS->TsAddBaTimer.function = TsAddBaProcess;
194
195 init_timer(&pTxTS->TxPendingBARecord.Timer);
196 pTxTS->TxPendingBARecord.Timer.data = (unsigned long)pTxTS;
197 pTxTS->TxPendingBARecord.Timer.function = BaSetupTimeOut;
198
199 init_timer(&pTxTS->TxAdmittedBARecord.Timer);
200 pTxTS->TxAdmittedBARecord.Timer.data = (unsigned long)pTxTS;
201 pTxTS->TxAdmittedBARecord.Timer.function = TxBaInactTimeout;
202
203 ResetTxTsEntry(pTxTS);
204 list_add_tail(&pTxTS->TsCommonInfo.List, &ieee->Tx_TS_Unused_List);
205 pTxTS++;
206 }
207
208 // Initialize Rx TS related info.
209 INIT_LIST_HEAD(&ieee->Rx_TS_Admit_List);
210 INIT_LIST_HEAD(&ieee->Rx_TS_Pending_List);
211 INIT_LIST_HEAD(&ieee->Rx_TS_Unused_List);
212 for(count = 0; count < TOTAL_TS_NUM; count++)
213 {
214 pRxTS->num = count;
215 INIT_LIST_HEAD(&pRxTS->RxPendingPktList);
216
217 init_timer(&pRxTS->TsCommonInfo.SetupTimer);
218 pRxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pRxTS;
219 pRxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut;
220
221 init_timer(&pRxTS->TsCommonInfo.InactTimer);
222 pRxTS->TsCommonInfo.InactTimer.data = (unsigned long)pRxTS;
223 pRxTS->TsCommonInfo.InactTimer.function = TsInactTimeout;
224
225 init_timer(&pRxTS->RxAdmittedBARecord.Timer);
226 pRxTS->RxAdmittedBARecord.Timer.data = (unsigned long)pRxTS;
227 pRxTS->RxAdmittedBARecord.Timer.function = RxBaInactTimeout;
228
229 init_timer(&pRxTS->RxPktPendingTimer);
230 pRxTS->RxPktPendingTimer.data = (unsigned long)pRxTS;
231 pRxTS->RxPktPendingTimer.function = RxPktPendingTimeout;
232
233 ResetRxTsEntry(pRxTS);
234 list_add_tail(&pRxTS->TsCommonInfo.List, &ieee->Rx_TS_Unused_List);
235 pRxTS++;
236 }
237 // Initialize unused Rx Reorder List.
238 INIT_LIST_HEAD(&ieee->RxReorder_Unused_List);
239//#ifdef TO_DO_LIST
240 for(count = 0; count < REORDER_ENTRY_NUM; count++)
241 {
242 list_add_tail( &pRxReorderEntry->List,&ieee->RxReorder_Unused_List);
243 if(count == (REORDER_ENTRY_NUM-1))
244 break;
245 pRxReorderEntry = &ieee->RxReorderEntry[count+1];
246 }
247//#endif
248
249}
250
251void AdmitTS(struct ieee80211_device *ieee, PTS_COMMON_INFO pTsCommonInfo, u32 InactTime)
252{
253 del_timer_sync(&pTsCommonInfo->SetupTimer);
254 del_timer_sync(&pTsCommonInfo->InactTimer);
255
256 if(InactTime!=0)
257 mod_timer(&pTsCommonInfo->InactTimer, jiffies + MSECS(InactTime));
258}
259
260
261PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 TID, TR_SELECT TxRxSelect)
262{
263 //DIRECTION_VALUE dir;
264 u8 dir;
265 bool search_dir[4] = {0, 0, 0, 0};
266 struct list_head* psearch_list; //FIXME
267 PTS_COMMON_INFO pRet = NULL;
268 if(ieee->iw_mode == IW_MODE_MASTER) //ap mode
269 {
270 if(TxRxSelect == TX_DIR)
271 {
272 search_dir[DIR_DOWN] = true;
273 search_dir[DIR_BI_DIR]= true;
274 }
275 else
276 {
277 search_dir[DIR_UP] = true;
278 search_dir[DIR_BI_DIR]= true;
279 }
280 }
281 else if(ieee->iw_mode == IW_MODE_ADHOC)
282 {
283 if(TxRxSelect == TX_DIR)
284 search_dir[DIR_UP] = true;
285 else
286 search_dir[DIR_DOWN] = true;
287 }
288 else
289 {
290 if(TxRxSelect == TX_DIR)
291 {
292 search_dir[DIR_UP] = true;
293 search_dir[DIR_BI_DIR]= true;
294 search_dir[DIR_DIRECT]= true;
295 }
296 else
297 {
298 search_dir[DIR_DOWN] = true;
299 search_dir[DIR_BI_DIR]= true;
300 search_dir[DIR_DIRECT]= true;
301 }
302 }
303
304 if(TxRxSelect == TX_DIR)
305 psearch_list = &ieee->Tx_TS_Admit_List;
306 else
307 psearch_list = &ieee->Rx_TS_Admit_List;
308
309 //for(dir = DIR_UP; dir <= DIR_BI_DIR; dir++)
310 for(dir = 0; dir <= DIR_BI_DIR; dir++)
311 {
312 if(search_dir[dir] ==false )
313 continue;
314 list_for_each_entry(pRet, psearch_list, List){
315 // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection);
316 if (memcmp(pRet->Addr, Addr, 6) == 0)
317 if (pRet->TSpec.f.TSInfo.field.ucTSID == TID)
318 if(pRet->TSpec.f.TSInfo.field.ucDirection == dir)
319 {
320 // printk("Bingo! got it\n");
321 break;
322 }
323
324 }
325 if(&pRet->List != psearch_list)
326 break;
327 }
328
329 if(&pRet->List != psearch_list){
330 return pRet ;
331 }
332 else
333 return NULL;
334}
335
336void MakeTSEntry(
337 PTS_COMMON_INFO pTsCommonInfo,
338 u8* Addr,
339 PTSPEC_BODY pTSPEC,
340 PQOS_TCLAS pTCLAS,
341 u8 TCLAS_Num,
342 u8 TCLAS_Proc
343 )
344{
345 u8 count;
346
347 if(pTsCommonInfo == NULL)
348 return;
349
350 memcpy(pTsCommonInfo->Addr, Addr, 6);
351
352 if(pTSPEC != NULL)
353 memcpy((u8*)(&(pTsCommonInfo->TSpec)), (u8*)pTSPEC, sizeof(TSPEC_BODY));
354
355 for(count = 0; count < TCLAS_Num; count++)
356 memcpy((u8*)(&(pTsCommonInfo->TClass[count])), (u8*)pTCLAS, sizeof(QOS_TCLAS));
357
358 pTsCommonInfo->TClasProc = TCLAS_Proc;
359 pTsCommonInfo->TClasNum = TCLAS_Num;
360}
361
362
363bool GetTs(
364 struct ieee80211_device* ieee,
365 PTS_COMMON_INFO *ppTS,
366 u8* Addr,
367 u8 TID,
368 TR_SELECT TxRxSelect, //Rx:1, Tx:0
369 bool bAddNewTs
370 )
371{
372 u8 UP = 0;
373 //
374 // We do not build any TS for Broadcast or Multicast stream.
375 // So reject these kinds of search here.
376 //
377 if(is_broadcast_ether_addr(Addr) || is_multicast_ether_addr(Addr))
378 {
379 IEEE80211_DEBUG(IEEE80211_DL_ERR, "get TS for Broadcast or Multicast\n");
380 return false;
381 }
382#if 0
383 if(ieee->pStaQos->CurrentQosMode == QOS_DISABLE)
384 { UP = 0; } //only use one TS
385 else if(ieee->pStaQos->CurrentQosMode & QOS_WMM)
386 {
387#else
388 if (ieee->current_network.qos_data.supported == 0)
389 UP = 0;
390 else
391 {
392#endif
393 // In WMM case: we use 4 TID only
394 if (!IsACValid(TID))
395 {
396 IEEE80211_DEBUG(IEEE80211_DL_ERR, " in %s(), TID(%d) is not valid\n", __FUNCTION__, TID);
397 return false;
398 }
399
400 switch(TID)
401 {
402 case 0:
403 case 3:
404 UP = 0;
405 break;
406
407 case 1:
408 case 2:
409 UP = 2;
410 break;
411
412 case 4:
413 case 5:
414 UP = 5;
415 break;
416
417 case 6:
418 case 7:
419 UP = 7;
420 break;
421 }
422 }
423
424 *ppTS = SearchAdmitTRStream(
425 ieee,
426 Addr,
427 UP,
428 TxRxSelect);
429 if(*ppTS != NULL)
430 {
431 return true;
432 }
433 else
434 {
435 if(bAddNewTs == false)
436 {
437 IEEE80211_DEBUG(IEEE80211_DL_TS, "add new TS failed(tid:%d)\n", UP);
438 return false;
439 }
440 else
441 {
442 //
443 // Create a new Traffic stream for current Tx/Rx
444 // This is for EDCA and WMM to add a new TS.
445 // For HCCA or WMMSA, TS cannot be addmit without negotiation.
446 //
447 TSPEC_BODY TSpec;
448 PQOS_TSINFO pTSInfo = &TSpec.f.TSInfo;
449 struct list_head* pUnusedList =
450 (TxRxSelect == TX_DIR)?
451 (&ieee->Tx_TS_Unused_List):
452 (&ieee->Rx_TS_Unused_List);
453
454 struct list_head* pAddmitList =
455 (TxRxSelect == TX_DIR)?
456 (&ieee->Tx_TS_Admit_List):
457 (&ieee->Rx_TS_Admit_List);
458
459 DIRECTION_VALUE Dir = (ieee->iw_mode == IW_MODE_MASTER)?
460 ((TxRxSelect==TX_DIR)?DIR_DOWN:DIR_UP):
461 ((TxRxSelect==TX_DIR)?DIR_UP:DIR_DOWN);
462 IEEE80211_DEBUG(IEEE80211_DL_TS, "to add Ts\n");
463 if(!list_empty(pUnusedList))
464 {
465 (*ppTS) = list_entry(pUnusedList->next, TS_COMMON_INFO, List);
466 list_del_init(&(*ppTS)->List);
467 if(TxRxSelect==TX_DIR)
468 {
469 PTX_TS_RECORD tmp = container_of(*ppTS, TX_TS_RECORD, TsCommonInfo);
470 ResetTxTsEntry(tmp);
471 }
472 else{
473 PRX_TS_RECORD tmp = container_of(*ppTS, RX_TS_RECORD, TsCommonInfo);
474 ResetRxTsEntry(tmp);
475 }
476
477 IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr));
478 // Prepare TS Info releated field
479 pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field
480 pTSInfo->field.ucTSID = UP; // TSID
481 pTSInfo->field.ucDirection = Dir; // Direction: if there is DirectLink, this need additional consideration.
482 pTSInfo->field.ucAccessPolicy = 1; // Access policy
483 pTSInfo->field.ucAggregation = 0; // Aggregation
484 pTSInfo->field.ucPSB = 0; // Aggregation
485 pTSInfo->field.ucUP = UP; // User priority
486 pTSInfo->field.ucTSInfoAckPolicy = 0; // Ack policy
487 pTSInfo->field.ucSchedule = 0; // Schedule
488
489 MakeTSEntry(*ppTS, Addr, &TSpec, NULL, 0, 0);
490 AdmitTS(ieee, *ppTS, 0);
491 list_add_tail(&((*ppTS)->List), pAddmitList);
492 // if there is DirectLink, we need to do additional operation here!!
493
494 return true;
495 }
496 else
497 {
498 IEEE80211_DEBUG(IEEE80211_DL_ERR, "in function %s() There is not enough TS record to be used!!", __FUNCTION__);
499 return false;
500 }
501 }
502 }
503}
504
505void RemoveTsEntry(
506 struct ieee80211_device* ieee,
507 PTS_COMMON_INFO pTs,
508 TR_SELECT TxRxSelect
509 )
510{
511 //u32 flags = 0;
512 unsigned long flags = 0;
513 del_timer_sync(&pTs->SetupTimer);
514 del_timer_sync(&pTs->InactTimer);
515 TsInitDelBA(ieee, pTs, TxRxSelect);
516
517 if(TxRxSelect == RX_DIR)
518 {
519//#ifdef TO_DO_LIST
520 PRX_REORDER_ENTRY pRxReorderEntry;
521 PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs;
522 if(timer_pending(&pRxTS->RxPktPendingTimer))
523 del_timer_sync(&pRxTS->RxPktPendingTimer);
524
525 while(!list_empty(&pRxTS->RxPendingPktList))
526 {
527 // PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
528 spin_lock_irqsave(&(ieee->reorder_spinlock), flags);
529 //pRxReorderEntry = list_entry(&pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List);
530 pRxReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List);
531 list_del_init(&pRxReorderEntry->List);
532 {
533 int i = 0;
534 struct ieee80211_rxb * prxb = pRxReorderEntry->prxb;
535 if (unlikely(!prxb))
536 {
537 spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags);
538 return;
539 }
540 for(i =0; i < prxb->nr_subframes; i++) {
541 dev_kfree_skb(prxb->subframes[i]);
542 }
543 kfree(prxb);
544 prxb = NULL;
545 }
546 list_add_tail(&pRxReorderEntry->List,&ieee->RxReorder_Unused_List);
547 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
548 spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags);
549 }
550
551//#endif
552 }
553 else
554 {
555 PTX_TS_RECORD pTxTS = (PTX_TS_RECORD)pTs;
556 del_timer_sync(&pTxTS->TsAddBaTimer);
557 }
558}
559
560void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr)
561{
562 PTS_COMMON_INFO pTS, pTmpTS;
563 printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr));
564#if 1
565 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List)
566 {
567 if (memcmp(pTS->Addr, Addr, 6) == 0)
568 {
569 RemoveTsEntry(ieee, pTS, TX_DIR);
570 list_del_init(&pTS->List);
571 list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List);
572 }
573 }
574
575 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List)
576 {
577 if (memcmp(pTS->Addr, Addr, 6) == 0)
578 {
579 printk("====>remove Tx_TS_admin_list\n");
580 RemoveTsEntry(ieee, pTS, TX_DIR);
581 list_del_init(&pTS->List);
582 list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List);
583 }
584 }
585
586 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List)
587 {
588 if (memcmp(pTS->Addr, Addr, 6) == 0)
589 {
590 RemoveTsEntry(ieee, pTS, RX_DIR);
591 list_del_init(&pTS->List);
592 list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List);
593 }
594 }
595
596 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List)
597 {
598 if (memcmp(pTS->Addr, Addr, 6) == 0)
599 {
600 RemoveTsEntry(ieee, pTS, RX_DIR);
601 list_del_init(&pTS->List);
602 list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List);
603 }
604 }
605#endif
606}
607
608void RemoveAllTS(struct ieee80211_device* ieee)
609{
610 PTS_COMMON_INFO pTS, pTmpTS;
611#if 1
612 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List)
613 {
614 RemoveTsEntry(ieee, pTS, TX_DIR);
615 list_del_init(&pTS->List);
616 list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List);
617 }
618
619 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List)
620 {
621 RemoveTsEntry(ieee, pTS, TX_DIR);
622 list_del_init(&pTS->List);
623 list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List);
624 }
625
626 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List)
627 {
628 RemoveTsEntry(ieee, pTS, RX_DIR);
629 list_del_init(&pTS->List);
630 list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List);
631 }
632
633 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List)
634 {
635 RemoveTsEntry(ieee, pTS, RX_DIR);
636 list_del_init(&pTS->List);
637 list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List);
638 }
639#endif
640}
641
642void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS)
643{
644 if(pTxTS->bAddBaReqInProgress == false)
645 {
646 pTxTS->bAddBaReqInProgress = true;
647#if 1
648 if(pTxTS->bAddBaReqDelayed)
649 {
650 IEEE80211_DEBUG(IEEE80211_DL_BA, "TsStartAddBaProcess(): Delayed Start ADDBA after 60 sec!!\n");
651 mod_timer(&pTxTS->TsAddBaTimer, jiffies + MSECS(TS_ADDBA_DELAY));
652 }
653 else
654 {
655 IEEE80211_DEBUG(IEEE80211_DL_BA,"TsStartAddBaProcess(): Immediately Start ADDBA now!!\n");
656 mod_timer(&pTxTS->TsAddBaTimer, jiffies+10); //set 10 ticks
657 }
658#endif
659 }
660 else
661 IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s()==>BA timer is already added\n", __FUNCTION__);
662}
663#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
664EXPORT_SYMBOL_NOVERS(RemovePeerTS);
665#else
666EXPORT_SYMBOL(RemovePeerTS);
667#endif
diff --git a/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h b/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h
new file mode 100644
index 00000000000..ccf6ae76357
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h
@@ -0,0 +1,399 @@
1/*
2 * Scatterlist Cryptographic API.
3 *
4 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
5 * Copyright (c) 2002 David S. Miller (davem@redhat.com)
6 *
7 * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no>
8 * and Nettle, by Niels Mé°ˆler.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 */
16#ifndef _LINUX_CRYPTO_H
17#define _LINUX_CRYPTO_H
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22#include <linux/list.h>
23#include <linux/string.h>
24#include <asm/page.h>
25#include <asm/errno.h>
26
27#define crypto_register_alg crypto_register_alg_rsl
28#define crypto_unregister_alg crypto_unregister_alg_rsl
29#define crypto_alloc_tfm crypto_alloc_tfm_rsl
30#define crypto_free_tfm crypto_free_tfm_rsl
31#define crypto_alg_available crypto_alg_available_rsl
32
33/*
34 * Algorithm masks and types.
35 */
36#define CRYPTO_ALG_TYPE_MASK 0x000000ff
37#define CRYPTO_ALG_TYPE_CIPHER 0x00000001
38#define CRYPTO_ALG_TYPE_DIGEST 0x00000002
39#define CRYPTO_ALG_TYPE_COMPRESS 0x00000004
40
41/*
42 * Transform masks and values (for crt_flags).
43 */
44#define CRYPTO_TFM_MODE_MASK 0x000000ff
45#define CRYPTO_TFM_REQ_MASK 0x000fff00
46#define CRYPTO_TFM_RES_MASK 0xfff00000
47
48#define CRYPTO_TFM_MODE_ECB 0x00000001
49#define CRYPTO_TFM_MODE_CBC 0x00000002
50#define CRYPTO_TFM_MODE_CFB 0x00000004
51#define CRYPTO_TFM_MODE_CTR 0x00000008
52
53#define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100
54#define CRYPTO_TFM_RES_WEAK_KEY 0x00100000
55#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000
56#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000
57#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000
58#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000
59
60/*
61 * Miscellaneous stuff.
62 */
63#define CRYPTO_UNSPEC 0
64#define CRYPTO_MAX_ALG_NAME 64
65
66struct scatterlist;
67
68/*
69 * Algorithms: modular crypto algorithm implementations, managed
70 * via crypto_register_alg() and crypto_unregister_alg().
71 */
72struct cipher_alg {
73 unsigned int cia_min_keysize;
74 unsigned int cia_max_keysize;
75 int (*cia_setkey)(void *ctx, const u8 *key,
76 unsigned int keylen, u32 *flags);
77 void (*cia_encrypt)(void *ctx, u8 *dst, const u8 *src);
78 void (*cia_decrypt)(void *ctx, u8 *dst, const u8 *src);
79};
80
81struct digest_alg {
82 unsigned int dia_digestsize;
83 void (*dia_init)(void *ctx);
84 void (*dia_update)(void *ctx, const u8 *data, unsigned int len);
85 void (*dia_final)(void *ctx, u8 *out);
86 int (*dia_setkey)(void *ctx, const u8 *key,
87 unsigned int keylen, u32 *flags);
88};
89
90struct compress_alg {
91 int (*coa_init)(void *ctx);
92 void (*coa_exit)(void *ctx);
93 int (*coa_compress)(void *ctx, const u8 *src, unsigned int slen,
94 u8 *dst, unsigned int *dlen);
95 int (*coa_decompress)(void *ctx, const u8 *src, unsigned int slen,
96 u8 *dst, unsigned int *dlen);
97};
98
99#define cra_cipher cra_u.cipher
100#define cra_digest cra_u.digest
101#define cra_compress cra_u.compress
102
103struct crypto_alg {
104 struct list_head cra_list;
105 u32 cra_flags;
106 unsigned int cra_blocksize;
107 unsigned int cra_ctxsize;
108 const char cra_name[CRYPTO_MAX_ALG_NAME];
109
110 union {
111 struct cipher_alg cipher;
112 struct digest_alg digest;
113 struct compress_alg compress;
114 } cra_u;
115
116 struct module *cra_module;
117};
118
119/*
120 * Algorithm registration interface.
121 */
122int crypto_register_alg(struct crypto_alg *alg);
123int crypto_unregister_alg(struct crypto_alg *alg);
124
125/*
126 * Algorithm query interface.
127 */
128int crypto_alg_available(const char *name, u32 flags);
129
130/*
131 * Transforms: user-instantiated objects which encapsulate algorithms
132 * and core processing logic. Managed via crypto_alloc_tfm() and
133 * crypto_free_tfm(), as well as the various helpers below.
134 */
135struct crypto_tfm;
136
137struct cipher_tfm {
138 void *cit_iv;
139 unsigned int cit_ivsize;
140 u32 cit_mode;
141 int (*cit_setkey)(struct crypto_tfm *tfm,
142 const u8 *key, unsigned int keylen);
143 int (*cit_encrypt)(struct crypto_tfm *tfm,
144 struct scatterlist *dst,
145 struct scatterlist *src,
146 unsigned int nbytes);
147 int (*cit_encrypt_iv)(struct crypto_tfm *tfm,
148 struct scatterlist *dst,
149 struct scatterlist *src,
150 unsigned int nbytes, u8 *iv);
151 int (*cit_decrypt)(struct crypto_tfm *tfm,
152 struct scatterlist *dst,
153 struct scatterlist *src,
154 unsigned int nbytes);
155 int (*cit_decrypt_iv)(struct crypto_tfm *tfm,
156 struct scatterlist *dst,
157 struct scatterlist *src,
158 unsigned int nbytes, u8 *iv);
159 void (*cit_xor_block)(u8 *dst, const u8 *src);
160};
161
162struct digest_tfm {
163 void (*dit_init)(struct crypto_tfm *tfm);
164 void (*dit_update)(struct crypto_tfm *tfm,
165 struct scatterlist *sg, unsigned int nsg);
166 void (*dit_final)(struct crypto_tfm *tfm, u8 *out);
167 void (*dit_digest)(struct crypto_tfm *tfm, struct scatterlist *sg,
168 unsigned int nsg, u8 *out);
169 int (*dit_setkey)(struct crypto_tfm *tfm,
170 const u8 *key, unsigned int keylen);
171#ifdef CONFIG_CRYPTO_HMAC
172 void *dit_hmac_block;
173#endif
174};
175
176struct compress_tfm {
177 int (*cot_compress)(struct crypto_tfm *tfm,
178 const u8 *src, unsigned int slen,
179 u8 *dst, unsigned int *dlen);
180 int (*cot_decompress)(struct crypto_tfm *tfm,
181 const u8 *src, unsigned int slen,
182 u8 *dst, unsigned int *dlen);
183};
184
185#define crt_cipher crt_u.cipher
186#define crt_digest crt_u.digest
187#define crt_compress crt_u.compress
188
189struct crypto_tfm {
190
191 u32 crt_flags;
192
193 union {
194 struct cipher_tfm cipher;
195 struct digest_tfm digest;
196 struct compress_tfm compress;
197 } crt_u;
198
199 struct crypto_alg *__crt_alg;
200};
201
202/*
203 * Transform user interface.
204 */
205
206/*
207 * crypto_alloc_tfm() will first attempt to locate an already loaded algorithm.
208 * If that fails and the kernel supports dynamically loadable modules, it
209 * will then attempt to load a module of the same name or alias. A refcount
210 * is grabbed on the algorithm which is then associated with the new transform.
211 *
212 * crypto_free_tfm() frees up the transform and any associated resources,
213 * then drops the refcount on the associated algorithm.
214 */
215struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags);
216void crypto_free_tfm(struct crypto_tfm *tfm);
217
218/*
219 * Transform helpers which query the underlying algorithm.
220 */
221static inline const char *crypto_tfm_alg_name(struct crypto_tfm *tfm)
222{
223 return tfm->__crt_alg->cra_name;
224}
225
226static inline const char *crypto_tfm_alg_modname(struct crypto_tfm *tfm)
227{
228 struct crypto_alg *alg = tfm->__crt_alg;
229
230 if (alg->cra_module)
231 return alg->cra_module->name;
232 else
233 return NULL;
234}
235
236static inline u32 crypto_tfm_alg_type(struct crypto_tfm *tfm)
237{
238 return tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK;
239}
240
241static inline unsigned int crypto_tfm_alg_min_keysize(struct crypto_tfm *tfm)
242{
243 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
244 return tfm->__crt_alg->cra_cipher.cia_min_keysize;
245}
246
247static inline unsigned int crypto_tfm_alg_max_keysize(struct crypto_tfm *tfm)
248{
249 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
250 return tfm->__crt_alg->cra_cipher.cia_max_keysize;
251}
252
253static inline unsigned int crypto_tfm_alg_ivsize(struct crypto_tfm *tfm)
254{
255 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
256 return tfm->crt_cipher.cit_ivsize;
257}
258
259static inline unsigned int crypto_tfm_alg_blocksize(struct crypto_tfm *tfm)
260{
261 return tfm->__crt_alg->cra_blocksize;
262}
263
264static inline unsigned int crypto_tfm_alg_digestsize(struct crypto_tfm *tfm)
265{
266 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
267 return tfm->__crt_alg->cra_digest.dia_digestsize;
268}
269
270/*
271 * API wrappers.
272 */
273static inline void crypto_digest_init(struct crypto_tfm *tfm)
274{
275 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
276 tfm->crt_digest.dit_init(tfm);
277}
278
279static inline void crypto_digest_update(struct crypto_tfm *tfm,
280 struct scatterlist *sg,
281 unsigned int nsg)
282{
283 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
284 tfm->crt_digest.dit_update(tfm, sg, nsg);
285}
286
287static inline void crypto_digest_final(struct crypto_tfm *tfm, u8 *out)
288{
289 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
290 tfm->crt_digest.dit_final(tfm, out);
291}
292
293static inline void crypto_digest_digest(struct crypto_tfm *tfm,
294 struct scatterlist *sg,
295 unsigned int nsg, u8 *out)
296{
297 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
298 tfm->crt_digest.dit_digest(tfm, sg, nsg, out);
299}
300
301static inline int crypto_digest_setkey(struct crypto_tfm *tfm,
302 const u8 *key, unsigned int keylen)
303{
304 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST);
305 if (tfm->crt_digest.dit_setkey == NULL)
306 return -ENOSYS;
307 return tfm->crt_digest.dit_setkey(tfm, key, keylen);
308}
309
310static inline int crypto_cipher_setkey(struct crypto_tfm *tfm,
311 const u8 *key, unsigned int keylen)
312{
313 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
314 return tfm->crt_cipher.cit_setkey(tfm, key, keylen);
315}
316
317static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm,
318 struct scatterlist *dst,
319 struct scatterlist *src,
320 unsigned int nbytes)
321{
322 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
323 return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes);
324}
325
326static inline int crypto_cipher_encrypt_iv(struct crypto_tfm *tfm,
327 struct scatterlist *dst,
328 struct scatterlist *src,
329 unsigned int nbytes, u8 *iv)
330{
331 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
332 BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB);
333 return tfm->crt_cipher.cit_encrypt_iv(tfm, dst, src, nbytes, iv);
334}
335
336static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm,
337 struct scatterlist *dst,
338 struct scatterlist *src,
339 unsigned int nbytes)
340{
341 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
342 return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes);
343}
344
345static inline int crypto_cipher_decrypt_iv(struct crypto_tfm *tfm,
346 struct scatterlist *dst,
347 struct scatterlist *src,
348 unsigned int nbytes, u8 *iv)
349{
350 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
351 BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB);
352 return tfm->crt_cipher.cit_decrypt_iv(tfm, dst, src, nbytes, iv);
353}
354
355static inline void crypto_cipher_set_iv(struct crypto_tfm *tfm,
356 const u8 *src, unsigned int len)
357{
358 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
359 memcpy(tfm->crt_cipher.cit_iv, src, len);
360}
361
362static inline void crypto_cipher_get_iv(struct crypto_tfm *tfm,
363 u8 *dst, unsigned int len)
364{
365 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER);
366 memcpy(dst, tfm->crt_cipher.cit_iv, len);
367}
368
369static inline int crypto_comp_compress(struct crypto_tfm *tfm,
370 const u8 *src, unsigned int slen,
371 u8 *dst, unsigned int *dlen)
372{
373 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS);
374 return tfm->crt_compress.cot_compress(tfm, src, slen, dst, dlen);
375}
376
377static inline int crypto_comp_decompress(struct crypto_tfm *tfm,
378 const u8 *src, unsigned int slen,
379 u8 *dst, unsigned int *dlen)
380{
381 BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS);
382 return tfm->crt_compress.cot_decompress(tfm, src, slen, dst, dlen);
383}
384
385/*
386 * HMAC support.
387 */
388#ifdef CONFIG_CRYPTO_HMAC
389void crypto_hmac_init(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen);
390void crypto_hmac_update(struct crypto_tfm *tfm,
391 struct scatterlist *sg, unsigned int nsg);
392void crypto_hmac_final(struct crypto_tfm *tfm, u8 *key,
393 unsigned int *keylen, u8 *out);
394void crypto_hmac(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen,
395 struct scatterlist *sg, unsigned int nsg, u8 *out);
396#endif /* CONFIG_CRYPTO_HMAC */
397
398#endif /* _LINUX_CRYPTO_H */
399
diff --git a/drivers/staging/rtl8192su/ieee80211/scatterwalk.c b/drivers/staging/rtl8192su/ieee80211/scatterwalk.c
new file mode 100644
index 00000000000..49f401fbce8
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/scatterwalk.c
@@ -0,0 +1,126 @@
1/*
2 * Cryptographic API.
3 *
4 * Cipher operations.
5 *
6 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
7 * 2002 Adam J. Richter <adam@yggdrasil.com>
8 * 2004 Jean-Luc Cooke <jlcooke@certainkey.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 */
16#include "kmap_types.h"
17
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/pagemap.h>
21#include <linux/highmem.h>
22#include <asm/scatterlist.h>
23#include "internal.h"
24#include "scatterwalk.h"
25
26enum km_type crypto_km_types[] = {
27 KM_USER0,
28 KM_USER1,
29 KM_SOFTIRQ0,
30 KM_SOFTIRQ1,
31};
32
33void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch)
34{
35 if (nbytes <= walk->len_this_page &&
36 (((unsigned long)walk->data) & (PAGE_CACHE_SIZE - 1)) + nbytes <=
37 PAGE_CACHE_SIZE)
38 return walk->data;
39 else
40 return scratch;
41}
42
43static void memcpy_dir(void *buf, void *sgdata, size_t nbytes, int out)
44{
45 if (out)
46 memcpy(sgdata, buf, nbytes);
47 else
48 memcpy(buf, sgdata, nbytes);
49}
50
51void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg)
52{
53 unsigned int rest_of_page;
54
55 walk->sg = sg;
56
57 walk->page = sg->page;
58 walk->len_this_segment = sg->length;
59
60 rest_of_page = PAGE_CACHE_SIZE - (sg->offset & (PAGE_CACHE_SIZE - 1));
61 walk->len_this_page = min(sg->length, rest_of_page);
62 walk->offset = sg->offset;
63}
64
65void scatterwalk_map(struct scatter_walk *walk, int out)
66{
67 walk->data = crypto_kmap(walk->page, out) + walk->offset;
68}
69
70static void scatterwalk_pagedone(struct scatter_walk *walk, int out,
71 unsigned int more)
72{
73 /* walk->data may be pointing the first byte of the next page;
74 however, we know we transfered at least one byte. So,
75 walk->data - 1 will be a virtual address in the mapped page. */
76
77 if (out)
78 flush_dcache_page(walk->page);
79
80 if (more) {
81 walk->len_this_segment -= walk->len_this_page;
82
83 if (walk->len_this_segment) {
84 walk->page++;
85 walk->len_this_page = min(walk->len_this_segment,
86 (unsigned)PAGE_CACHE_SIZE);
87 walk->offset = 0;
88 }
89 else
90 scatterwalk_start(walk, sg_next(walk->sg));
91 }
92}
93
94void scatterwalk_done(struct scatter_walk *walk, int out, int more)
95{
96 crypto_kunmap(walk->data, out);
97 if (walk->len_this_page == 0 || !more)
98 scatterwalk_pagedone(walk, out, more);
99}
100
101/*
102 * Do not call this unless the total length of all of the fragments
103 * has been verified as multiple of the block size.
104 */
105int scatterwalk_copychunks(void *buf, struct scatter_walk *walk,
106 size_t nbytes, int out)
107{
108 if (buf != walk->data) {
109 while (nbytes > walk->len_this_page) {
110 memcpy_dir(buf, walk->data, walk->len_this_page, out);
111 buf += walk->len_this_page;
112 nbytes -= walk->len_this_page;
113
114 crypto_kunmap(walk->data, out);
115 scatterwalk_pagedone(walk, out, 1);
116 scatterwalk_map(walk, out);
117 }
118
119 memcpy_dir(buf, walk->data, nbytes, out);
120 }
121
122 walk->offset += nbytes;
123 walk->len_this_page -= nbytes;
124 walk->len_this_segment -= nbytes;
125 return 0;
126}
diff --git a/drivers/staging/rtl8192su/ieee80211/scatterwalk.h b/drivers/staging/rtl8192su/ieee80211/scatterwalk.h
new file mode 100644
index 00000000000..b1644651901
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211/scatterwalk.h
@@ -0,0 +1,51 @@
1/*
2 * Cryptographic API.
3 *
4 * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
5 * Copyright (c) 2002 Adam J. Richter <adam@yggdrasil.com>
6 * Copyright (c) 2004 Jean-Luc Cooke <jlcooke@certainkey.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 */
14
15#ifndef _CRYPTO_SCATTERWALK_H
16#define _CRYPTO_SCATTERWALK_H
17#include <linux/mm.h>
18#include <asm/scatterlist.h>
19
20struct scatter_walk {
21 struct scatterlist *sg;
22 struct page *page;
23 void *data;
24 unsigned int len_this_page;
25 unsigned int len_this_segment;
26 unsigned int offset;
27};
28
29/* Define sg_next is an inline routine now in case we want to change
30 scatterlist to a linked list later. */
31static inline struct scatterlist *sg_next(struct scatterlist *sg)
32{
33 return sg + 1;
34}
35
36static inline int scatterwalk_samebuf(struct scatter_walk *walk_in,
37 struct scatter_walk *walk_out,
38 void *src_p, void *dst_p)
39{
40 return walk_in->page == walk_out->page &&
41 walk_in->offset == walk_out->offset &&
42 walk_in->data == src_p && walk_out->data == dst_p;
43}
44
45void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch);
46void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg);
47int scatterwalk_copychunks(void *buf, struct scatter_walk *walk, size_t nbytes, int out);
48void scatterwalk_map(struct scatter_walk *walk, int out);
49void scatterwalk_done(struct scatter_walk *walk, int out, int more);
50
51#endif /* _CRYPTO_SCATTERWALK_H */
diff --git a/drivers/staging/rtl8192su/ieee80211_crypt.h b/drivers/staging/rtl8192su/ieee80211_crypt.h
new file mode 100644
index 00000000000..b58a3bcc0dc
--- /dev/null
+++ b/drivers/staging/rtl8192su/ieee80211_crypt.h
@@ -0,0 +1,86 @@
1/*
2 * Original code based on Host AP (software wireless LAN access point) driver
3 * for Intersil Prism2/2.5/3.
4 *
5 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
6 * <jkmaline@cc.hut.fi>
7 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
8 *
9 * Adaption to a generic IEEE 802.11 stack by James Ketrenos
10 * <jketreno@linux.intel.com>
11 *
12 * Copyright (c) 2004, Intel Corporation
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. See README and COPYING for
17 * more details.
18 */
19
20/*
21 * This file defines the interface to the ieee80211 crypto module.
22 */
23#ifndef IEEE80211_CRYPT_H
24#define IEEE80211_CRYPT_H
25
26#include <linux/skbuff.h>
27
28struct ieee80211_crypto_ops {
29 const char *name;
30
31 /* init new crypto context (e.g., allocate private data space,
32 * select IV, etc.); returns NULL on failure or pointer to allocated
33 * private data on success */
34 void * (*init)(int keyidx);
35
36 /* deinitialize crypto context and free allocated private data */
37 void (*deinit)(void *priv);
38
39 /* encrypt/decrypt return < 0 on error or >= 0 on success. The return
40 * value from decrypt_mpdu is passed as the keyidx value for
41 * decrypt_msdu. skb must have enough head and tail room for the
42 * encryption; if not, error will be returned; these functions are
43 * called for all MPDUs (i.e., fragments).
44 */
45 int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
46 int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
47
48 /* These functions are called for full MSDUs, i.e. full frames.
49 * These can be NULL if full MSDU operations are not needed. */
50 int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv);
51 int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len,
52 void *priv);
53
54 int (*set_key)(void *key, int len, u8 *seq, void *priv);
55 int (*get_key)(void *key, int len, u8 *seq, void *priv);
56
57 /* procfs handler for printing out key information and possible
58 * statistics */
59 char * (*print_stats)(char *p, void *priv);
60
61 /* maximum number of bytes added by encryption; encrypt buf is
62 * allocated with extra_prefix_len bytes, copy of in_buf, and
63 * extra_postfix_len; encrypt need not use all this space, but
64 * the result must start at the beginning of the buffer and correct
65 * length must be returned */
66 int extra_prefix_len, extra_postfix_len;
67
68 struct module *owner;
69};
70
71struct ieee80211_crypt_data {
72 struct list_head list; /* delayed deletion list */
73 struct ieee80211_crypto_ops *ops;
74 void *priv;
75 atomic_t refcnt;
76};
77
78int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops);
79int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops);
80struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name);
81void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int);
82void ieee80211_crypt_deinit_handler(unsigned long);
83void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
84 struct ieee80211_crypt_data **crypt);
85
86#endif
diff --git a/drivers/staging/rtl8192su/r8180_93cx6.c b/drivers/staging/rtl8192su/r8180_93cx6.c
new file mode 100644
index 00000000000..8878cfeb0fb
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8180_93cx6.c
@@ -0,0 +1,146 @@
1/*
2 This files contains card eeprom (93c46 or 93c56) programming routines,
3 memory is addressed by 16 bits words.
4
5 This is part of rtl8180 OpenSource driver.
6 Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
7 Released under the terms of GPL (General Public Licence)
8
9 Parts of this driver are based on the GPL part of the
10 official realtek driver.
11
12 Parts of this driver are based on the rtl8180 driver skeleton
13 from Patric Schenke & Andres Salomon.
14
15 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
16
17 We want to tanks the Authors of those projects and the Ndiswrapper
18 project Authors.
19*/
20
21#include "r8180_93cx6.h"
22
23void eprom_cs(struct net_device *dev, short bit)
24{
25 if(bit)
26 write_nic_byte_E(dev, EPROM_CMD,
27 (1<<EPROM_CS_SHIFT) | \
28 read_nic_byte_E(dev, EPROM_CMD)); //enable EPROM
29 else
30 write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev, EPROM_CMD)\
31 &~(1<<EPROM_CS_SHIFT)); //disable EPROM
32
33 force_pci_posting(dev);
34 udelay(EPROM_DELAY);
35}
36
37
38void eprom_ck_cycle(struct net_device *dev)
39{
40 write_nic_byte_E(dev, EPROM_CMD,
41 (1<<EPROM_CK_SHIFT) | read_nic_byte_E(dev,EPROM_CMD));
42 force_pci_posting(dev);
43 udelay(EPROM_DELAY);
44 write_nic_byte_E(dev, EPROM_CMD,
45 read_nic_byte_E(dev, EPROM_CMD) &~ (1<<EPROM_CK_SHIFT));
46 force_pci_posting(dev);
47 udelay(EPROM_DELAY);
48}
49
50
51void eprom_w(struct net_device *dev,short bit)
52{
53 if(bit)
54 write_nic_byte_E(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | \
55 read_nic_byte_E(dev,EPROM_CMD));
56 else
57 write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev,EPROM_CMD)\
58 &~(1<<EPROM_W_SHIFT));
59
60 force_pci_posting(dev);
61 udelay(EPROM_DELAY);
62}
63
64
65short eprom_r(struct net_device *dev)
66{
67 short bit;
68
69 bit=(read_nic_byte_E(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT) );
70 udelay(EPROM_DELAY);
71
72 if(bit) return 1;
73 return 0;
74}
75
76
77void eprom_send_bits_string(struct net_device *dev, short b[], int len)
78{
79 int i;
80
81 for(i=0; i<len; i++){
82 eprom_w(dev, b[i]);
83 eprom_ck_cycle(dev);
84 }
85}
86
87
88u32 eprom_read(struct net_device *dev, u32 addr)
89{
90 struct r8192_priv *priv = ieee80211_priv(dev);
91 short read_cmd[]={1,1,0};
92 short addr_str[8];
93 int i;
94 int addr_len;
95 u32 ret;
96
97 ret=0;
98 //enable EPROM programming
99 write_nic_byte_E(dev, EPROM_CMD,
100 (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
101 force_pci_posting(dev);
102 udelay(EPROM_DELAY);
103
104 if (priv->epromtype==EPROM_93c56){
105 addr_str[7]=addr & 1;
106 addr_str[6]=addr & (1<<1);
107 addr_str[5]=addr & (1<<2);
108 addr_str[4]=addr & (1<<3);
109 addr_str[3]=addr & (1<<4);
110 addr_str[2]=addr & (1<<5);
111 addr_str[1]=addr & (1<<6);
112 addr_str[0]=addr & (1<<7);
113 addr_len=8;
114 }else{
115 addr_str[5]=addr & 1;
116 addr_str[4]=addr & (1<<1);
117 addr_str[3]=addr & (1<<2);
118 addr_str[2]=addr & (1<<3);
119 addr_str[1]=addr & (1<<4);
120 addr_str[0]=addr & (1<<5);
121 addr_len=6;
122 }
123 eprom_cs(dev, 1);
124 eprom_ck_cycle(dev);
125 eprom_send_bits_string(dev, read_cmd, 3);
126 eprom_send_bits_string(dev, addr_str, addr_len);
127
128 //keep chip pin D to low state while reading.
129 //I'm unsure if it is necessary, but anyway shouldn't hurt
130 eprom_w(dev, 0);
131
132 for(i=0;i<16;i++){
133 //eeprom needs a clk cycle between writing opcode&adr
134 //and reading data. (eeprom outs a dummy 0)
135 eprom_ck_cycle(dev);
136 ret |= (eprom_r(dev)<<(15-i));
137 }
138
139 eprom_cs(dev, 0);
140 eprom_ck_cycle(dev);
141
142 //disable EPROM programming
143 write_nic_byte_E(dev, EPROM_CMD,
144 (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
145 return ret;
146}
diff --git a/drivers/staging/rtl8192su/r8180_93cx6.h b/drivers/staging/rtl8192su/r8180_93cx6.h
new file mode 100644
index 00000000000..ca228d36817
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8180_93cx6.h
@@ -0,0 +1,45 @@
1/*
2 This is part of rtl8187 OpenSource driver
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the official realtek driver
7 Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon
8 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
9
10 We want to tanks the Authors of such projects and the Ndiswrapper project Authors.
11*/
12
13/*This files contains card eeprom (93c46 or 93c56) programming routines*/
14/*memory is addressed by WORDS*/
15
16#ifdef RTL8192SU
17#include "r8192U.h"
18#include "r8192S_hw.h"
19#else
20#include "r8192U.h"
21#include "r8192U_hw.h"
22#endif
23
24#define EPROM_DELAY 10
25
26#define EPROM_ANAPARAM_ADDRLWORD 0xd
27#define EPROM_ANAPARAM_ADDRHWORD 0xe
28
29#define EPROM_RFCHIPID 0x6
30#define EPROM_TXPW_BASE 0x05
31#define EPROM_RFCHIPID_RTL8225U 5
32#define EPROM_RF_PARAM 0x4
33#define EPROM_CONFIG2 0xc
34
35#define EPROM_VERSION 0x1E
36#define MAC_ADR 0x7
37
38#define CIS 0x18
39
40#define EPROM_TXPW0 0x16
41#define EPROM_TXPW2 0x1b
42#define EPROM_TXPW1 0x3d
43
44
45u32 eprom_read(struct net_device *dev,u32 addr); //reads a 16 bits word
diff --git a/drivers/staging/rtl8192su/r8190_rtl8256.c b/drivers/staging/rtl8192su/r8190_rtl8256.c
new file mode 100644
index 00000000000..74ff337b058
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8190_rtl8256.c
@@ -0,0 +1,312 @@
1/*
2 This is part of the rtl8192 driver
3 released under the GPL (See file COPYING for details).
4
5 This files contains programming code for the rtl8256
6 radio frontend.
7
8 *Many* thanks to Realtek Corp. for their great support!
9
10*/
11
12#include "r8192U.h"
13#include "r8192U_hw.h"
14#include "r819xU_phyreg.h"
15#include "r819xU_phy.h"
16#include "r8190_rtl8256.h"
17
18/*--------------------------------------------------------------------------
19 * Overview: set RF band width (20M or 40M)
20 * Input: struct net_device* dev
21 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
22 * Output: NONE
23 * Return: NONE
24 * Note: 8226 support both 20M and 40 MHz
25 *---------------------------------------------------------------------------*/
26void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
27{
28 u8 eRFPath;
29 struct r8192_priv *priv = ieee80211_priv(dev);
30
31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
32 for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
33 {
34 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
35 continue;
36
37 switch(Bandwidth)
38 {
39 case HT_CHANNEL_WIDTH_20:
40 if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
41 {
42 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
43 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
44 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
45
46 //cosa add for sd3's request 01/23/2008
47 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
48 }
49 else
50 {
51 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
52 }
53
54 break;
55 case HT_CHANNEL_WIDTH_20_40:
56 if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
57 {
58 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
59 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
60 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
61
62 //cosa add for sd3's request 01/23/2008
63 if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
64 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
65 else
66 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
67 }
68 else
69 {
70 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
71 }
72
73
74 break;
75 default:
76 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
77 break;
78
79 }
80 }
81 return;
82}
83/*--------------------------------------------------------------------------
84 * Overview: Interface to config 8256
85 * Input: struct net_device* dev
86 * Output: NONE
87 * Return: NONE
88 *---------------------------------------------------------------------------*/
89void PHY_RF8256_Config(struct net_device* dev)
90{
91 struct r8192_priv *priv = ieee80211_priv(dev);
92 // Initialize general global value
93 //
94 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
95 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
96 // Config BB and RF
97 phy_RF8256_Config_ParaFile(dev);
98
99 return;
100}
101/*--------------------------------------------------------------------------
102 * Overview: Interface to config 8256
103 * Input: struct net_device* dev
104 * Output: NONE
105 * Return: NONE
106 *---------------------------------------------------------------------------*/
107void phy_RF8256_Config_ParaFile(struct net_device* dev)
108{
109 u32 u4RegValue = 0;
110 //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
111 //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
112 //static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
113 //static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
114 u8 eRFPath;
115 BB_REGISTER_DEFINITION_T *pPhyReg;
116 struct r8192_priv *priv = ieee80211_priv(dev);
117 u32 RegOffSetToBeCheck = 0x3;
118 u32 RegValueToBeCheck = 0x7f1;
119 u32 RF3_Final_Value = 0;
120 u8 ConstRetryTimes = 5, RetryTimes = 5;
121 u8 ret = 0;
122 //3//-----------------------------------------------------------------
123 //3// <2> Initialize RF
124 //3//-----------------------------------------------------------------
125 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
126 {
127 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
128 continue;
129
130 pPhyReg = &priv->PHYRegDef[eRFPath];
131
132 // Joseph test for shorten RF config
133 // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
134
135 /*----Store original RFENV control type----*/
136 switch(eRFPath)
137 {
138 case RF90_PATH_A:
139 case RF90_PATH_C:
140 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
141 break;
142 case RF90_PATH_B :
143 case RF90_PATH_D:
144 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
145 break;
146 }
147
148 /*----Set RF_ENV enable----*/
149 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
150
151 /*----Set RF_ENV output high----*/
152 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
153
154 /* Set bit number of Address and Data for RF register */
155 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
156 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
157
158 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
159
160 /*----Check RF block (for FPGA platform only)----*/
161 // TODO: this function should be removed on ASIC , Emily 2007.2.2
162 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath))
163 {
164 RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
165 goto phy_RF8256_Config_ParaFile_Fail;
166 }
167
168 RetryTimes = ConstRetryTimes;
169 RF3_Final_Value = 0;
170 /*----Initialize RF fom connfiguration file----*/
171 switch(eRFPath)
172 {
173 case RF90_PATH_A:
174 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
175 {
176 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
177 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
178 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
179 RetryTimes--;
180 }
181 break;
182 case RF90_PATH_B:
183 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
184 {
185 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
186 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
187 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
188 RetryTimes--;
189 }
190 break;
191 case RF90_PATH_C:
192 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
193 {
194 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
195 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
196 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
197 RetryTimes--;
198 }
199 break;
200 case RF90_PATH_D:
201 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
202 {
203 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
204 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
205 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
206 RetryTimes--;
207 }
208 break;
209 }
210
211 /*----Restore RFENV control type----*/;
212 switch(eRFPath)
213 {
214 case RF90_PATH_A:
215 case RF90_PATH_C:
216 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
217 break;
218 case RF90_PATH_B :
219 case RF90_PATH_D:
220 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
221 break;
222 }
223
224 if(ret){
225 RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
226 goto phy_RF8256_Config_ParaFile_Fail;
227 }
228
229 }
230
231 RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
232 return ;
233
234phy_RF8256_Config_ParaFile_Fail:
235 RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
236 return ;
237}
238
239
240void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
241{
242 u32 TxAGC=0;
243 struct r8192_priv *priv = ieee80211_priv(dev);
244 //modified by vivi, 20080109
245 TxAGC = powerlevel;
246
247 if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan
248 {
249 if(priv->CustomerID == RT_CID_819x_Netcore)
250 TxAGC = 0x22;
251 else
252 TxAGC += priv->CckPwEnl;
253 }
254
255 if(TxAGC > 0x24)
256 TxAGC = 0x24;
257 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
258}
259
260
261void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
262{
263 struct r8192_priv *priv = ieee80211_priv(dev);
264 //Joseph TxPower for 8192 testing
265 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
266 u8 index = 0;
267 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
268 u8 byte0, byte1, byte2, byte3;
269
270 powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates
271 powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
272 powerBase1 = powerlevel; //MCS rates
273 powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
274
275 for(index=0; index<6; index++)
276 {
277 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
278 byte0 = (u8)(writeVal & 0x7f);
279 byte1 = (u8)((writeVal & 0x7f00)>>8);
280 byte2 = (u8)((writeVal & 0x7f0000)>>16);
281 byte3 = (u8)((writeVal & 0x7f000000)>>24);
282 if(byte0 > 0x24) // Max power index = 0x24
283 byte0 = 0x24;
284 if(byte1 > 0x24)
285 byte1 = 0x24;
286 if(byte2 > 0x24)
287 byte2 = 0x24;
288 if(byte3 > 0x24)
289 byte3 = 0x24;
290
291 //for tx power track
292 if(index == 3)
293 {
294 writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
295 priv->Pwr_Track = writeVal_tmp;
296 }
297
298 if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06
299 {
300 // Emily, 20080613. Set low tx power for both MCS and legacy OFDM
301 writeVal = 0x03030303;
302 }
303 else
304 {
305 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
306 }
307 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
308 }
309 return;
310
311}
312
diff --git a/drivers/staging/rtl8192su/r8190_rtl8256.h b/drivers/staging/rtl8192su/r8190_rtl8256.h
new file mode 100644
index 00000000000..5c1f650fe82
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8190_rtl8256.h
@@ -0,0 +1,27 @@
1/*
2 This is part of the rtl8180-sa2400 driver
3 released under the GPL (See file COPYING for details).
4 Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
5
6 This files contains programming code for the rtl8256
7 radio frontend.
8
9 *Many* thanks to Realtek Corp. for their great support!
10
11*/
12
13#ifndef RTL8225H
14#define RTL8225H
15
16#ifdef RTL8190P
17#define RTL819X_TOTAL_RF_PATH 4 //for 90P
18#else
19#define RTL819X_TOTAL_RF_PATH 2 //for 8192U
20#endif
21extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
22extern void PHY_RF8256_Config(struct net_device* dev);
23extern void phy_RF8256_Config_ParaFile(struct net_device* dev);
24extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel);
25extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel);
26
27#endif
diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.c b/drivers/staging/rtl8192su/r8192SU_HWImg.c
new file mode 100644
index 00000000000..cbb65795a30
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192SU_HWImg.c
@@ -0,0 +1,4902 @@
1/*Created on 2009/ 1/15, 3:10*/
2
3#include "r8192SU_HWImg.h"
4
5u8 Rtl8192SUFwImgArray[ImgArrayLength] = {
60x92,0x81,0x2b,0x90,0x30,0x00,0x00,0x00,0x08,0x74,0x00,0x00,0x88,0x96,0x00,0x00,
70x30,0x00,0x00,0x00,0x00,0x95,0x00,0x00,0x00,0x00,0x2b,0x00,0x03,0x03,0x23,0x00,
80x92,0x81,0x02,0x01,0x00,0x00,0x12,0x04,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,
90x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x01,0x01,0x01,0x00,0x00,
100x00,0x01,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
110x7f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
120x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
130x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
140x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
150x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
160x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
170x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
180x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
190x1f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
200x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
210x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
220x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
230x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
240x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
250x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
260x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
270x25,0xb0,0x1a,0x3c,0x80,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,0x80,0x00,0x7b,0x37,
280x00,0x00,0x5b,0xaf,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,
290x80,0x00,0x7b,0x37,0x00,0x00,0x5b,0xaf,0x00,0x80,0x1a,0x3c,0x10,0x6d,0x5a,0x27,
300x08,0x00,0x40,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
310x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
320x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
330x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
340x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
350x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
360x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
370x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
380x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
390x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
400x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
410x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
420x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
430x04,0x00,0xa1,0xaf,0x08,0x00,0xa2,0xaf,0x0c,0x00,0xa3,0xaf,0x10,0x00,0xa4,0xaf,
440x14,0x00,0xa5,0xaf,0x18,0x00,0xa6,0xaf,0x1c,0x00,0xa7,0xaf,0x20,0x00,0xa8,0xaf,
450x24,0x00,0xa9,0xaf,0x28,0x00,0xaa,0xaf,0x2c,0x00,0xab,0xaf,0x30,0x00,0xac,0xaf,
460x34,0x00,0xad,0xaf,0x38,0x00,0xae,0xaf,0x3c,0x00,0xaf,0xaf,0x12,0x40,0x00,0x00,
470x10,0x48,0x00,0x00,0x00,0x70,0x0a,0x40,0x40,0x00,0xb0,0xaf,0x44,0x00,0xb1,0xaf,
480x48,0x00,0xb2,0xaf,0x4c,0x00,0xb3,0xaf,0x50,0x00,0xb4,0xaf,0x54,0x00,0xb5,0xaf,
490x58,0x00,0xb6,0xaf,0x5c,0x00,0xb7,0xaf,0x60,0x00,0xb8,0xaf,0x64,0x00,0xb9,0xaf,
500x68,0x00,0xbc,0xaf,0x6c,0x00,0xbd,0xaf,0x70,0x00,0xbe,0xaf,0x74,0x00,0xbf,0xaf,
510x78,0x00,0xa8,0xaf,0x7c,0x00,0xa9,0xaf,0x80,0x00,0xaa,0xaf,0xdf,0x1a,0x00,0x08,
520x21,0x20,0xa0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
530x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
540x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
550x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
560x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
570x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
580x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
590x25,0xb0,0x06,0x3c,0x00,0x80,0x02,0x3c,0xe8,0xff,0xbd,0x27,0x18,0x03,0xc3,0x34,
600x00,0x03,0x42,0x24,0x14,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x00,0x62,0xac,
610x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x42,0xb0,0x03,0x3c,
620x03,0x00,0x63,0x34,0x00,0x00,0x62,0x90,0x02,0x80,0x0a,0x3c,0x02,0x80,0x10,0x3c,
630xff,0x00,0x42,0x30,0x00,0x46,0x02,0x00,0x10,0x00,0x42,0x30,0x13,0x00,0x40,0x10,
640x03,0x46,0x08,0x00,0xc4,0x7d,0x42,0x8d,0x68,0x15,0x05,0x26,0xd4,0x63,0xa4,0x94,
650x01,0x00,0x47,0x24,0x10,0x00,0x02,0x24,0xb0,0x03,0xc9,0x34,0x00,0x00,0x62,0xa0,
660x07,0x00,0x80,0x10,0x1c,0x03,0xc6,0x34,0xd8,0x63,0xa2,0x8c,0xd4,0x63,0xa0,0xa4,
670xd8,0x63,0xa0,0xac,0x00,0x00,0x04,0x24,0x00,0x00,0xc2,0xac,0x00,0x00,0x20,0xad,
680x01,0x00,0x82,0x24,0xc4,0x7d,0x47,0xad,0xd4,0x63,0xa2,0xa4,0x12,0x00,0x00,0x05,
690x42,0xb0,0x02,0x3c,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
700x00,0x60,0x81,0x40,0x68,0x15,0x04,0x26,0x0c,0x4b,0x83,0x94,0x08,0x4b,0x85,0x94,
710x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x80,0x00,0x63,0x30,0x41,0xb0,0x02,0x3c,
720x25,0x18,0x65,0x00,0x08,0x00,0x42,0x34,0x18,0x00,0xbd,0x27,0x00,0x00,0x43,0xa4,
730x08,0x00,0xe0,0x03,0x08,0x4b,0x83,0xa4,0x80,0xff,0x03,0x24,0x03,0x00,0x42,0x34,
740x00,0x00,0x43,0xa0,0xc8,0x0e,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,
750x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x68,0x15,0x04,0x26,
760x0c,0x4b,0x83,0x94,0x08,0x4b,0x85,0x94,0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,
770x80,0x00,0x63,0x30,0x41,0xb0,0x02,0x3c,0x25,0x18,0x65,0x00,0x08,0x00,0x42,0x34,
780x18,0x00,0xbd,0x27,0x00,0x00,0x43,0xa4,0x08,0x00,0xe0,0x03,0x08,0x4b,0x83,0xa4,
790xff,0x00,0x84,0x30,0x0b,0x00,0x82,0x2c,0xff,0xff,0xe7,0x30,0x10,0x00,0xa8,0x93,
800x19,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0x02,0x80,0x03,0x3c,0x80,0x10,0x04,0x00,
810xc0,0x91,0x63,0x24,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0x00,0x00,0x00,0x00,
820x08,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x43,0xb0,0x02,0x3c,0x78,0x00,0x44,0x34,
830x07,0x00,0xe2,0x30,0x00,0x00,0x85,0xac,0x04,0x00,0x86,0xac,0x04,0x00,0x40,0x18,
840x00,0x00,0x00,0x00,0xf8,0xff,0xe2,0x30,0x08,0x00,0x42,0x24,0xff,0xff,0x47,0x30,
850x21,0x10,0xe8,0x00,0x00,0x80,0x03,0x3c,0x08,0x00,0x82,0xac,0x25,0x10,0x43,0x00,
860x08,0x00,0x82,0xac,0x01,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
870x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x6c,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,
880x20,0x01,0x00,0x08,0x60,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,
890x54,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x48,0x00,0x44,0x34,
900x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x3c,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,
910x20,0x01,0x00,0x08,0x30,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,
920x24,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x18,0x00,0x44,0x34,
930x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x0c,0x00,0x44,0x34,0x20,0x01,0x00,0x08,
940x43,0xb0,0x04,0x3c,0x01,0x00,0x02,0x24,0x25,0xb0,0x03,0x3c,0x04,0x20,0x82,0x00,
950x18,0x03,0x67,0x34,0x00,0x80,0x02,0x3c,0x43,0xb0,0x03,0x3c,0x34,0x05,0x46,0x24,
960x88,0x00,0x65,0x34,0x21,0x10,0x00,0x00,0x01,0x00,0x42,0x24,0xff,0xff,0x42,0x30,
970x05,0x00,0x43,0x2c,0xfd,0xff,0x60,0x14,0x01,0x00,0x42,0x24,0x00,0x00,0xe6,0xac,
980x00,0x00,0xa2,0x94,0x00,0x00,0x00,0x00,0xff,0xff,0x42,0x30,0x24,0x10,0x44,0x00,
990xf4,0xff,0x40,0x1c,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
1000x25,0xb0,0x08,0x3c,0x00,0x80,0x02,0x3c,0xc8,0xff,0xbd,0x27,0x18,0x03,0x03,0x35,
1010x90,0x05,0x42,0x24,0x00,0x00,0x62,0xac,0x30,0x00,0xb6,0xaf,0x28,0x00,0xb4,0xaf,
1020x24,0x00,0xb3,0xaf,0x1c,0x00,0xb1,0xaf,0x34,0x00,0xbf,0xaf,0x2c,0x00,0xb5,0xaf,
1030x20,0x00,0xb2,0xaf,0x18,0x00,0xb0,0xaf,0x0c,0x00,0xf2,0x84,0x08,0x00,0xf5,0x8c,
1040xff,0x00,0xc6,0x30,0x00,0x01,0x02,0x24,0x23,0x10,0x46,0x00,0xff,0xff,0x51,0x30,
1050xd0,0x03,0x08,0x35,0xff,0x00,0x96,0x30,0x00,0x00,0x12,0xad,0x21,0xa0,0xa0,0x00,
1060x21,0x30,0xc5,0x00,0x00,0x00,0x15,0xad,0x21,0x20,0xc0,0x02,0x21,0x28,0xa0,0x02,
1070x21,0x38,0x20,0x02,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x23,0x18,0x51,0x02,
1080xff,0xff,0x82,0x32,0x00,0x94,0x03,0x00,0x03,0x94,0x12,0x00,0xa6,0x01,0x00,0x08,
1090x02,0x9a,0x02,0x00,0x28,0xb0,0x03,0x3c,0xc0,0x10,0x13,0x00,0x21,0x10,0x43,0x00,
1100x00,0x00,0x44,0x90,0x25,0xb0,0x10,0x3c,0x20,0x10,0x02,0x3c,0xff,0x00,0x93,0x30,
1110x00,0x22,0x13,0x00,0xff,0xff,0x43,0x32,0x01,0x01,0x45,0x2a,0x21,0xa0,0x82,0x00,
1120x21,0xa8,0xb1,0x02,0xd0,0x03,0x02,0x36,0x00,0x01,0x11,0x24,0x0b,0x88,0x65,0x00,
1130x21,0x20,0xc0,0x02,0x00,0x00,0x53,0xac,0x4d,0x01,0x00,0x0c,0xb0,0x03,0x10,0x36,
1140x21,0x30,0x80,0x02,0x21,0x20,0xc0,0x02,0x21,0x28,0xa0,0x02,0x21,0x38,0x20,0x02,
1150x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x23,0x18,0x51,0x02,0x00,0x94,0x03,0x00,
1160x03,0x94,0x12,0x00,0x00,0x00,0x12,0xae,0xe2,0xff,0x40,0x1e,0x00,0x00,0x00,0x00,
1170x34,0x00,0xbf,0x8f,0x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,
1180x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
1190x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0xc8,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,
1200x25,0xb0,0x04,0x3c,0x20,0x00,0xb2,0xaf,0x68,0x15,0x52,0x24,0x00,0x80,0x02,0x3c,
1210x18,0x03,0x83,0x34,0xc8,0x06,0x42,0x24,0x28,0x00,0xb4,0xaf,0x24,0x00,0xb3,0xaf,
1220x30,0x00,0xbf,0xaf,0x2c,0x00,0xb5,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
1230x00,0x00,0x62,0xac,0xb0,0x03,0x93,0x34,0x21,0xa0,0x40,0x02,0x54,0x64,0x42,0x8e,
1240xc0,0x64,0x50,0x8e,0x21,0x20,0x00,0x00,0x00,0x00,0x62,0xae,0x58,0x64,0x42,0xae,
1250x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,0xc0,0x64,0x44,0x8e,
1260xc4,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,0x3f,0x00,0x62,0x24,0x2b,0x10,0x44,0x00,
1270x0a,0x18,0x82,0x00,0xc0,0x64,0x43,0xae,0xc0,0x64,0x85,0x8e,0x00,0x00,0x00,0x00,
1280x00,0x00,0x65,0xae,0x02,0x80,0x02,0x3c,0xff,0xff,0x10,0x32,0x25,0x80,0x02,0x02,
1290x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,0xff,0x00,0x15,0x24,0x21,0x20,0x00,0x00,
1300x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,0x20,0x10,0x02,0x3c,0x20,0x00,0x07,0x24,
1310x00,0x1a,0x11,0x00,0x21,0x18,0x62,0x00,0x05,0x00,0x35,0x12,0x21,0x30,0x60,0x00,
1320x08,0x64,0x91,0xa2,0x54,0x64,0x83,0xae,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
1330x04,0x00,0x04,0x8e,0x08,0x00,0x03,0x8e,0xff,0xe0,0x02,0x3c,0xff,0xff,0x42,0x34,
1340x1f,0x00,0x84,0x30,0x24,0x18,0x62,0x00,0x00,0x26,0x04,0x00,0xff,0xdf,0x02,0x3c,
1350x25,0x18,0x64,0x00,0xff,0xff,0x42,0x34,0x24,0x18,0x62,0x00,0x00,0x40,0x04,0x3c,
1360x25,0x18,0x64,0x00,0xc0,0xff,0x02,0x24,0x24,0x18,0x62,0x00,0x08,0x00,0x03,0xae,
1370xc9,0x64,0x84,0x92,0x2a,0xb0,0x02,0x3c,0x01,0x00,0x03,0x24,0x01,0x00,0x84,0x24,
1380x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0xc4,0xff,0x35,0x16,0xc9,0x64,0x84,0xa2,
1390xfc,0x4a,0x82,0x8e,0x41,0xb0,0x03,0x3c,0x30,0x00,0xbf,0x8f,0x00,0x38,0x42,0x34,
1400x00,0x00,0x62,0xac,0x2c,0x00,0xb5,0x8f,0xfc,0x4a,0x82,0xae,0x24,0x00,0xb3,0x8f,
1410x28,0x00,0xb4,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
1420x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0x25,0xb0,0x04,0x3c,0x00,0x80,0x02,0x3c,
1430xc8,0xff,0xbd,0x27,0x18,0x03,0x83,0x34,0x38,0x08,0x42,0x24,0x34,0x00,0xbf,0xaf,
1440x30,0x00,0xb6,0xaf,0x2c,0x00,0xb5,0xaf,0x28,0x00,0xb4,0xaf,0x24,0x00,0xb3,0xaf,
1450x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,0x00,0x00,0x62,0xac,
1460x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x02,0x80,0x16,0x3c,
1470x68,0x15,0xd2,0x26,0xb0,0x03,0x93,0x34,0x2d,0x02,0x00,0x08,0x21,0xa8,0x40,0x02,
1480x2a,0xb0,0x02,0x3c,0x08,0x00,0x04,0xae,0x09,0x00,0x42,0x34,0x01,0x00,0x03,0x24,
1490x02,0x00,0x04,0x24,0x00,0x00,0x43,0xa0,0x00,0x00,0x44,0xa0,0x42,0x00,0x34,0x12,
1500x00,0x00,0x00,0x00,0x6c,0x64,0x42,0x8e,0xd8,0x64,0x50,0x8e,0x01,0x00,0x04,0x24,
1510x00,0x00,0x62,0xae,0x70,0x64,0x42,0xae,0x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,
1520x00,0x00,0x00,0x00,0xd8,0x64,0x44,0x8e,0xdc,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,
1530x3f,0x00,0x62,0x24,0x2b,0x10,0x44,0x00,0x0a,0x18,0x82,0x00,0xd8,0x64,0x43,0xae,
1540xd8,0x64,0xa5,0x8e,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0xae,0x02,0x80,0x02,0x3c,
1550xff,0xff,0x10,0x32,0x25,0x80,0x02,0x02,0x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,
1560xff,0x00,0x14,0x24,0x01,0x00,0x04,0x24,0x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,
1570x20,0x10,0x02,0x3c,0x20,0x00,0x07,0x24,0x00,0x1a,0x11,0x00,0x21,0x18,0x62,0x00,
1580x05,0x00,0x34,0x12,0x21,0x30,0x60,0x00,0x6c,0x64,0xa3,0xae,0x10,0x64,0xb1,0xa2,
1590x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x04,0x00,0x04,0x8e,0x08,0x00,0x03,0x8e,
1600xff,0xe0,0x02,0x3c,0xff,0xff,0x42,0x34,0x1f,0x00,0x84,0x30,0x24,0x18,0x62,0x00,
1610x00,0x26,0x04,0x00,0xff,0xdf,0x02,0x3c,0x25,0x18,0x64,0x00,0xff,0xff,0x42,0x34,
1620x24,0x18,0x62,0x00,0x00,0x40,0x04,0x3c,0x25,0x18,0x64,0x00,0xc0,0xff,0x05,0x24,
1630x82,0x11,0x03,0x00,0x24,0x20,0x65,0x00,0x01,0x00,0x42,0x30,0xc0,0xff,0x40,0x10,
1640x04,0x00,0x84,0x34,0x2a,0xb0,0x02,0x3c,0x08,0x00,0x03,0xae,0x09,0x00,0x42,0x34,
1650x01,0x00,0x03,0x24,0x02,0x00,0x04,0x24,0x00,0x00,0x43,0xa0,0x00,0x00,0x44,0xa0,
1660xc0,0xff,0x34,0x16,0x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
1670x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x68,0x15,0xc2,0x26,0xfc,0x4a,0x43,0x8c,
1680x34,0x00,0xbf,0x8f,0x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,
1690x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
1700x00,0x38,0x63,0x34,0x41,0xb0,0x04,0x3c,0x38,0x00,0xbd,0x27,0x00,0x00,0x83,0xac,
1710x08,0x00,0xe0,0x03,0xfc,0x4a,0x43,0xac,0x25,0xb0,0x04,0x3c,0x00,0x80,0x02,0x3c,
1720xc0,0xff,0xbd,0x27,0x18,0x03,0x83,0x34,0x08,0x0a,0x42,0x24,0x38,0x00,0xbf,0xaf,
1730x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x2c,0x00,0xb5,0xaf,0x28,0x00,0xb4,0xaf,
1740x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
1750x00,0x00,0x62,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
1760x02,0x80,0x17,0x3c,0x68,0x15,0xf2,0x26,0xb0,0x03,0x93,0x34,0x02,0x80,0x14,0x3c,
1770xab,0x02,0x00,0x08,0x21,0xb0,0x40,0x02,0x2a,0xb0,0x03,0x3c,0x08,0x00,0x04,0xae,
1780x05,0x00,0x63,0x34,0x01,0x00,0x02,0x24,0x02,0x00,0x04,0x24,0x00,0x00,0x62,0xa0,
1790x00,0x00,0x64,0xa0,0xca,0x7d,0x82,0x96,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,
1800xca,0x7d,0x82,0xa6,0xca,0x7d,0x83,0x96,0x25,0xb0,0x02,0x3c,0x66,0x03,0x42,0x34,
1810x00,0x00,0x43,0xa4,0x4a,0x00,0x35,0x12,0x00,0x00,0x00,0x00,0x60,0x64,0x42,0x8e,
1820xcc,0x64,0x50,0x8e,0x01,0x00,0x04,0x24,0x00,0x00,0x62,0xae,0x64,0x64,0x42,0xae,
1830x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,0xcc,0x64,0x44,0x8e,
1840xd0,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,0x3f,0x00,0x62,0x24,0x2b,0x10,0x44,0x00,
1850x0a,0x18,0x82,0x00,0xcc,0x64,0x43,0xae,0xcc,0x64,0xc5,0x8e,0x00,0x00,0x00,0x00,
1860x00,0x00,0x65,0xae,0x02,0x80,0x02,0x3c,0xff,0xff,0x10,0x32,0x25,0x80,0x02,0x02,
1870x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,0xff,0x00,0x15,0x24,0x01,0x00,0x04,0x24,
1880x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,0x20,0x10,0x02,0x3c,0x20,0x00,0x07,0x24,
1890x00,0x1a,0x11,0x00,0x21,0x18,0x62,0x00,0x05,0x00,0x35,0x12,0x21,0x30,0x60,0x00,
1900x60,0x64,0xc3,0xae,0x0c,0x64,0xd1,0xa2,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
1910x04,0x00,0x04,0x8e,0x08,0x00,0x03,0x8e,0xff,0xe0,0x02,0x3c,0xff,0xff,0x42,0x34,
1920x1f,0x00,0x84,0x30,0x24,0x18,0x62,0x00,0x00,0x26,0x04,0x00,0xff,0xdf,0x02,0x3c,
1930x25,0x18,0x64,0x00,0xff,0xff,0x42,0x34,0x24,0x18,0x62,0x00,0x00,0x40,0x04,0x3c,
1940x25,0x18,0x64,0x00,0xc0,0xff,0x05,0x24,0x82,0x11,0x03,0x00,0x24,0x20,0x65,0x00,
1950x01,0x00,0x42,0x30,0xb8,0xff,0x40,0x10,0x04,0x00,0x84,0x34,0x08,0x00,0x03,0xae,
1960x2a,0xb0,0x03,0x3c,0x05,0x00,0x63,0x34,0x01,0x00,0x02,0x24,0x02,0x00,0x04,0x24,
1970x00,0x00,0x62,0xa0,0x00,0x00,0x64,0xa0,0xca,0x7d,0x82,0x96,0x00,0x00,0x00,0x00,
1980x01,0x00,0x42,0x24,0xca,0x7d,0x82,0xa6,0xca,0x7d,0x83,0x96,0x25,0xb0,0x02,0x3c,
1990x66,0x03,0x42,0x34,0x00,0x00,0x43,0xa4,0xb8,0xff,0x35,0x16,0x00,0x00,0x00,0x00,
2000x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
2010x68,0x15,0xe2,0x26,0xfc,0x4a,0x43,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
2020x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
2030x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x00,0x38,0x63,0x34,
2040x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x83,0xac,0x08,0x00,0xe0,0x03,
2050xfc,0x4a,0x43,0xac,0xc0,0xff,0xbd,0x27,0x2c,0x00,0xb5,0xaf,0x38,0x00,0xbf,0xaf,
2060x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x28,0x00,0xb4,0xaf,0x24,0x00,0xb3,0xaf,
2070x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,0x02,0x80,0x06,0x3c,
2080x7c,0x7e,0xc5,0x90,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,0x18,0x03,0x42,0x34,
2090x24,0x0c,0x63,0x24,0x40,0x00,0xa4,0x30,0x00,0x00,0x43,0xac,0x21,0xa8,0x00,0x00,
2100x03,0x00,0x80,0x10,0x7f,0x00,0xa2,0x30,0xbf,0x00,0xa2,0x30,0x01,0x00,0x15,0x24,
2110x7c,0x7e,0xc2,0xa0,0x7c,0x7e,0xc2,0x90,0x25,0xb0,0x04,0x3c,0x88,0x02,0x83,0x34,
2120x00,0x00,0x62,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
2130x02,0x80,0x16,0x3c,0x68,0x15,0xd2,0x26,0xb0,0x03,0x93,0x34,0x02,0x80,0x14,0x3c,
2140x43,0x03,0x00,0x08,0x21,0xb8,0x40,0x02,0x24,0x10,0xa2,0x00,0x04,0x00,0x42,0x34,
2150x2a,0xb0,0x07,0x3c,0x08,0x00,0x02,0xae,0x0d,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,
2160x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,0x02,0x00,0x03,0x24,0x00,0x00,0x44,0xa0,
2170x00,0x00,0x43,0xa0,0xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,0x66,0x03,0xc5,0x34,
2180x01,0x00,0x84,0x24,0xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,0xff,0x00,0x03,0x24,
2190x00,0x00,0xa2,0xa4,0x5a,0x00,0x23,0x12,0x00,0x00,0x00,0x00,0x24,0x64,0x42,0x8e,
2200x90,0x64,0x50,0x8e,0x03,0x00,0x04,0x24,0x00,0x00,0x62,0xae,0x28,0x64,0x42,0xae,
2210x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,0x90,0x64,0x44,0x8e,
2220x94,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,0x3f,0x00,0x62,0x24,0x2b,0x10,0x44,0x00,
2230x0a,0x18,0x82,0x00,0x90,0x64,0x43,0xae,0x90,0x64,0xe2,0x8e,0x00,0x00,0x00,0x00,
2240x00,0x00,0x62,0xae,0x02,0x80,0x02,0x3c,0xff,0xff,0x10,0x32,0x25,0x80,0x02,0x02,
2250x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0xae,
2260x0c,0x00,0x11,0x92,0xff,0x00,0x02,0x24,0x0d,0x00,0x22,0x12,0x00,0x12,0x11,0x00,
2270x20,0x10,0x03,0x3c,0x21,0x10,0x43,0x00,0x5a,0x00,0xa0,0x12,0x24,0x64,0xe2,0xae,
2280xec,0x63,0xf1,0xa2,0x68,0x15,0xc2,0x26,0x24,0x64,0x46,0x8c,0x90,0x64,0x45,0x8c,
2290x03,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
2300x04,0x00,0x04,0x8e,0x14,0x00,0x03,0x8e,0x08,0x00,0x05,0x8e,0xff,0xe0,0x02,0x3c,
2310x1f,0x00,0x84,0x30,0x42,0x1a,0x03,0x00,0xff,0xff,0x42,0x34,0x00,0x26,0x04,0x00,
2320x24,0x28,0xa2,0x00,0x3f,0x00,0x63,0x30,0x25,0x28,0xa4,0x00,0x0c,0x00,0x63,0x28,
2330x06,0x00,0x60,0x14,0x21,0x20,0xa0,0x00,0x00,0x00,0x02,0x96,0x00,0x00,0x00,0x00,
2340xfd,0x0f,0x42,0x28,0x08,0x00,0x40,0x14,0x82,0x11,0x05,0x00,0xff,0xdf,0x02,0x3c,
2350xff,0xff,0x42,0x34,0x24,0x28,0x82,0x00,0x00,0x40,0x03,0x3c,0x25,0x20,0xa3,0x00,
2360x21,0x28,0x80,0x00,0x82,0x11,0x05,0x00,0x01,0x00,0x42,0x30,0xa6,0xff,0x40,0x10,
2370xc0,0xff,0x02,0x24,0x2a,0xb0,0x07,0x3c,0x0d,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,
2380x08,0x00,0x04,0xae,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,0x02,0x00,0x03,0x24,
2390x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,0xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,
2400x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,0xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,
2410xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,0xa8,0xff,0x23,0x16,0x00,0x00,0x00,0x00,
2420x22,0x00,0xa0,0x12,0x68,0x15,0xc2,0x26,0xec,0x63,0x43,0x90,0x41,0x00,0xe4,0x34,
2430xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,0x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,
2440x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
2450x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x68,0x15,0xc5,0x26,0xfc,0x4a,0xa4,0x8c,
2460x01,0x00,0x02,0x3c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,0x30,0x00,0xb6,0x8f,
2470x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,
2480x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x00,0x80,0x42,0x34,0x25,0x20,0x82,0x00,
2490x41,0xb0,0x03,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x64,0xac,0x08,0x00,0xe0,0x03,
2500xfc,0x4a,0xa4,0xac,0x65,0x03,0x00,0x08,0xe8,0x63,0xf1,0xa2,0xe8,0x63,0x43,0x90,
2510x40,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,0x00,0x00,0xa3,0xac,
2520x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x00,0x60,0x01,0x40,
2530x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x68,0x15,0xc5,0x26,
2540xfc,0x4a,0xa4,0x8c,0x01,0x00,0x02,0x3c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
2550x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
2560x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x00,0x80,0x42,0x34,
2570x25,0x20,0x82,0x00,0x41,0xb0,0x03,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x64,0xac,
2580x08,0x00,0xe0,0x03,0xfc,0x4a,0xa4,0xac,0xc0,0xff,0xbd,0x27,0x2c,0x00,0xb5,0xaf,
2590x38,0x00,0xbf,0xaf,0x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x28,0x00,0xb4,0xaf,
2600x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
2610x02,0x80,0x06,0x3c,0x7c,0x7e,0xc5,0x90,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
2620x18,0x03,0x42,0x34,0x78,0x0f,0x63,0x24,0x10,0x00,0xa4,0x30,0x00,0x00,0x43,0xac,
2630x21,0xa8,0x00,0x00,0x03,0x00,0x80,0x10,0xdf,0x00,0xa2,0x30,0xef,0x00,0xa2,0x30,
2640x01,0x00,0x15,0x24,0x7c,0x7e,0xc2,0xa0,0x7c,0x7e,0xc3,0x90,0x25,0xb0,0x02,0x3c,
2650xb0,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,
2660x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x02,0x80,0x16,0x3c,0x68,0x15,0xd2,0x26,
2670x21,0x98,0x40,0x00,0x02,0x80,0x14,0x3c,0x19,0x04,0x00,0x08,0x21,0xb8,0x40,0x02,
2680x24,0x10,0xa2,0x00,0x04,0x00,0x42,0x34,0x2a,0xb0,0x07,0x3c,0x08,0x00,0x02,0xae,
2690x15,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,
2700x02,0x00,0x03,0x24,0x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,0xca,0x7d,0x84,0x96,
2710x25,0xb0,0x06,0x3c,0x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,0xca,0x7d,0x84,0xa6,
2720xca,0x7d,0x82,0x96,0xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,0x5a,0x00,0x23,0x12,
2730x00,0x00,0x00,0x00,0x30,0x64,0x42,0x8e,0x9c,0x64,0x50,0x8e,0x04,0x00,0x04,0x24,
2740x00,0x00,0x62,0xae,0x34,0x64,0x42,0xae,0x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,
2750x00,0x00,0x00,0x00,0x9c,0x64,0x44,0x8e,0xa0,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,
2760x3f,0x00,0x62,0x24,0x2b,0x10,0x44,0x00,0x0a,0x18,0x82,0x00,0x9c,0x64,0x43,0xae,
2770x9c,0x64,0xe2,0x8e,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0xae,0x02,0x80,0x02,0x3c,
2780xff,0xff,0x10,0x32,0x25,0x80,0x02,0x02,0x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,
2790x00,0x00,0x00,0x00,0x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,0xff,0x00,0x02,0x24,
2800x0d,0x00,0x22,0x12,0x00,0x12,0x11,0x00,0x20,0x10,0x03,0x3c,0x21,0x10,0x43,0x00,
2810x59,0x00,0xa0,0x12,0x30,0x64,0xe2,0xae,0xf4,0x63,0xf1,0xa2,0x68,0x15,0xc2,0x26,
2820x30,0x64,0x46,0x8c,0x9c,0x64,0x45,0x8c,0x04,0x00,0x04,0x24,0x20,0x00,0x07,0x24,
2830x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x04,0x00,0x04,0x8e,0x14,0x00,0x03,0x8e,
2840x08,0x00,0x05,0x8e,0xff,0xe0,0x02,0x3c,0x1f,0x00,0x84,0x30,0x42,0x1a,0x03,0x00,
2850xff,0xff,0x42,0x34,0x00,0x26,0x04,0x00,0x24,0x28,0xa2,0x00,0x3f,0x00,0x63,0x30,
2860x25,0x28,0xa4,0x00,0x0c,0x00,0x63,0x28,0x06,0x00,0x60,0x14,0x21,0x20,0xa0,0x00,
2870x00,0x00,0x02,0x96,0x00,0x00,0x00,0x00,0xfd,0x0f,0x42,0x28,0x08,0x00,0x40,0x14,
2880x82,0x11,0x05,0x00,0xff,0xdf,0x02,0x3c,0xff,0xff,0x42,0x34,0x24,0x28,0x82,0x00,
2890x00,0x40,0x03,0x3c,0x25,0x20,0xa3,0x00,0x21,0x28,0x80,0x00,0x82,0x11,0x05,0x00,
2900x01,0x00,0x42,0x30,0xa6,0xff,0x40,0x10,0xc0,0xff,0x02,0x24,0x2a,0xb0,0x07,0x3c,
2910x15,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,0x08,0x00,0x04,0xae,0x0b,0x10,0x75,0x00,
2920x01,0x00,0x04,0x24,0x02,0x00,0x03,0x24,0x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,
2930xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,0x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,
2940xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,0xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,
2950xa8,0xff,0x23,0x16,0x00,0x00,0x00,0x00,0x21,0x00,0xa0,0x12,0x68,0x15,0xc2,0x26,
2960xf4,0x63,0x43,0x90,0x43,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
2970x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
2980x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
2990x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
3000x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
3010x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x06,0x00,0x03,0x3c,
3020x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
3030x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0x3b,0x04,0x00,0x08,0xf0,0x63,0xf1,0xa2,
3040xf0,0x63,0x43,0x90,0x42,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
3050x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
3060x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
3070x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
3080x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
3090x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x06,0x00,0x03,0x3c,
3100x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
3110x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0xc0,0xff,0xbd,0x27,0x2c,0x00,0xb5,0xaf,
3120x38,0x00,0xbf,0xaf,0x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x28,0x00,0xb4,0xaf,
3130x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
3140x02,0x80,0x06,0x3c,0x7c,0x7e,0xc5,0x90,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
3150x18,0x03,0x42,0x34,0xc8,0x12,0x63,0x24,0x01,0x00,0xa4,0x30,0x00,0x00,0x43,0xac,
3160x21,0xa8,0x00,0x00,0x03,0x00,0x80,0x10,0xf7,0x00,0xa2,0x30,0xfe,0x00,0xa2,0x30,
3170x01,0x00,0x15,0x24,0x7c,0x7e,0xc2,0xa0,0x7c,0x7e,0xc3,0x90,0x25,0xb0,0x02,0x3c,
3180xb0,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
3190x00,0x60,0x81,0x40,0x02,0x80,0x16,0x3c,0x68,0x15,0xd2,0x26,0x21,0x98,0x40,0x00,
3200x02,0x80,0x14,0x3c,0xf8,0x04,0x00,0x08,0x21,0xb8,0x40,0x02,0x00,0x00,0x02,0x96,
3210x00,0x00,0x00,0x00,0xfd,0x0f,0x42,0x28,0x54,0x00,0x40,0x10,0xff,0xdf,0x02,0x3c,
3220x00,0x20,0x02,0x3c,0x25,0x28,0xa2,0x00,0x82,0x11,0x05,0x00,0x01,0x00,0x42,0x30,
3230x57,0x00,0x40,0x14,0x2a,0xb0,0x07,0x3c,0xc0,0xff,0x02,0x24,0x24,0x10,0xa2,0x00,
3240x04,0x00,0x42,0x34,0x2a,0xb0,0x07,0x3c,0x08,0x00,0x02,0xae,0x1d,0x00,0xe2,0x34,
3250x04,0x00,0x43,0x24,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,0x02,0x00,0x03,0x24,
3260x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,0xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,
3270x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,0xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,
3280xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,0x53,0x00,0x23,0x12,0x00,0x00,0x00,0x00,
3290x3c,0x64,0x42,0x8e,0xa8,0x64,0x50,0x8e,0x05,0x00,0x04,0x24,0x00,0x00,0x62,0xae,
3300x40,0x64,0x42,0xae,0x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,
3310xa8,0x64,0x44,0x8e,0xac,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,0x3f,0x00,0x62,0x24,
3320x2b,0x10,0x44,0x00,0x0a,0x18,0x82,0x00,0xa8,0x64,0x43,0xae,0xa8,0x64,0xe2,0x8e,
3330x00,0x00,0x00,0x00,0x00,0x00,0x62,0xae,0x02,0x80,0x02,0x3c,0xff,0xff,0x10,0x32,
3340x25,0x80,0x02,0x02,0x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,0x00,0x00,0x00,0x00,
3350x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,0xff,0x00,0x02,0x24,0x0d,0x00,0x22,0x12,
3360x00,0x12,0x11,0x00,0x20,0x10,0x03,0x3c,0x21,0x10,0x43,0x00,0x52,0x00,0xa0,0x12,
3370x3c,0x64,0xe2,0xae,0x04,0x64,0xf1,0xa2,0x68,0x15,0xc2,0x26,0x3c,0x64,0x46,0x8c,
3380xa8,0x64,0x45,0x8c,0x05,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,
3390x10,0x00,0xa0,0xaf,0x14,0x00,0x03,0x8e,0x04,0x00,0x04,0x8e,0x08,0x00,0x05,0x8e,
3400x42,0x1a,0x03,0x00,0xff,0xe0,0x02,0x3c,0x1f,0x00,0x84,0x30,0x3f,0x00,0x63,0x30,
3410xff,0xff,0x42,0x34,0x24,0x28,0xa2,0x00,0x00,0x26,0x04,0x00,0x0c,0x00,0x63,0x28,
3420xaa,0xff,0x60,0x10,0x25,0x28,0xa4,0x00,0xff,0xdf,0x02,0x3c,0xff,0xff,0x42,0x34,
3430x24,0x10,0xa2,0x00,0x00,0x40,0x03,0x3c,0x25,0x28,0x43,0x00,0x82,0x11,0x05,0x00,
3440x01,0x00,0x42,0x30,0xad,0xff,0x40,0x10,0xc0,0xff,0x02,0x24,0x2a,0xb0,0x07,0x3c,
3450x1d,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,
3460x02,0x00,0x03,0x24,0x08,0x00,0x05,0xae,0x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,
3470xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,0x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,
3480xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,0xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,
3490xaf,0xff,0x23,0x16,0x00,0x00,0x00,0x00,0x21,0x00,0xa0,0x12,0x68,0x15,0xc2,0x26,
3500x04,0x64,0x43,0x90,0x45,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
3510x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
3520x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
3530x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
3540x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
3550x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x18,0x00,0x03,0x3c,
3560x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
3570x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0x1a,0x05,0x00,0x08,0xf8,0x63,0xf1,0xa2,
3580xf8,0x63,0x43,0x90,0x44,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
3590x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
3600x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
3610x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
3620x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
3630x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x18,0x00,0x03,0x3c,
3640x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
3650x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0xc0,0xff,0xbd,0x27,0x2c,0x00,0xb5,0xaf,
3660x38,0x00,0xbf,0xaf,0x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x28,0x00,0xb4,0xaf,
3670x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
3680x02,0x80,0x06,0x3c,0x7c,0x7e,0xc5,0x90,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
3690x18,0x03,0x42,0x34,0x28,0x16,0x63,0x24,0x02,0x00,0xa4,0x30,0x00,0x00,0x43,0xac,
3700x21,0xa8,0x00,0x00,0x03,0x00,0x80,0x10,0xfb,0x00,0xa2,0x30,0xfd,0x00,0xa2,0x30,
3710x01,0x00,0x15,0x24,0x7c,0x7e,0xc2,0xa0,0x7c,0x7e,0xc3,0x90,0x25,0xb0,0x02,0x3c,
3720xb0,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
3730x00,0x60,0x81,0x40,0x02,0x80,0x16,0x3c,0x68,0x15,0xd2,0x26,0x21,0x98,0x40,0x00,
3740x02,0x80,0x14,0x3c,0xd0,0x05,0x00,0x08,0x21,0xb8,0x40,0x02,0x00,0x00,0x02,0x96,
3750x00,0x00,0x00,0x00,0xfd,0x0f,0x42,0x28,0x54,0x00,0x40,0x10,0xff,0xdf,0x02,0x3c,
3760x00,0x20,0x02,0x3c,0x25,0x28,0xa2,0x00,0x82,0x11,0x05,0x00,0x01,0x00,0x42,0x30,
3770x57,0x00,0x40,0x14,0x2a,0xb0,0x07,0x3c,0xc0,0xff,0x02,0x24,0x24,0x10,0xa2,0x00,
3780x04,0x00,0x42,0x34,0x2a,0xb0,0x07,0x3c,0x08,0x00,0x02,0xae,0x25,0x00,0xe2,0x34,
3790x04,0x00,0x43,0x24,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,0x02,0x00,0x03,0x24,
3800x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,0xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,
3810x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,0xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,
3820xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,0x53,0x00,0x23,0x12,0x00,0x00,0x00,0x00,
3830x48,0x64,0x42,0x8e,0xb4,0x64,0x50,0x8e,0x06,0x00,0x04,0x24,0x00,0x00,0x62,0xae,
3840x4c,0x64,0x42,0xae,0x00,0x00,0x70,0xae,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,
3850xb4,0x64,0x44,0x8e,0xb8,0x64,0x43,0x8e,0x20,0x00,0x84,0x24,0x3f,0x00,0x62,0x24,
3860x2b,0x10,0x44,0x00,0x0a,0x18,0x82,0x00,0xb4,0x64,0x43,0xae,0xb4,0x64,0xe2,0x8e,
3870x00,0x00,0x00,0x00,0x00,0x00,0x62,0xae,0x02,0x80,0x02,0x3c,0xff,0xff,0x10,0x32,
3880x25,0x80,0x02,0x02,0x00,0x00,0x70,0xae,0x0c,0x00,0x02,0x92,0x00,0x00,0x00,0x00,
3890x00,0x00,0x62,0xae,0x0c,0x00,0x11,0x92,0xff,0x00,0x02,0x24,0x0d,0x00,0x22,0x12,
3900x00,0x12,0x11,0x00,0x20,0x10,0x03,0x3c,0x21,0x10,0x43,0x00,0x52,0x00,0xa0,0x12,
3910x48,0x64,0xe2,0xae,0x00,0x64,0xf1,0xa2,0x68,0x15,0xc2,0x26,0x48,0x64,0x46,0x8c,
3920xb4,0x64,0x45,0x8c,0x06,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,
3930x10,0x00,0xa0,0xaf,0x14,0x00,0x03,0x8e,0x04,0x00,0x04,0x8e,0x08,0x00,0x05,0x8e,
3940x42,0x1a,0x03,0x00,0xff,0xe0,0x02,0x3c,0x1f,0x00,0x84,0x30,0x3f,0x00,0x63,0x30,
3950xff,0xff,0x42,0x34,0x24,0x28,0xa2,0x00,0x00,0x26,0x04,0x00,0x0c,0x00,0x63,0x28,
3960xaa,0xff,0x60,0x10,0x25,0x28,0xa4,0x00,0xff,0xdf,0x02,0x3c,0xff,0xff,0x42,0x34,
3970x24,0x10,0xa2,0x00,0x00,0x40,0x03,0x3c,0x25,0x28,0x43,0x00,0x82,0x11,0x05,0x00,
3980x01,0x00,0x42,0x30,0xad,0xff,0x40,0x10,0xc0,0xff,0x02,0x24,0x2a,0xb0,0x07,0x3c,
3990x25,0x00,0xe2,0x34,0x04,0x00,0x43,0x24,0x0b,0x10,0x75,0x00,0x01,0x00,0x04,0x24,
4000x02,0x00,0x03,0x24,0x08,0x00,0x05,0xae,0x00,0x00,0x44,0xa0,0x00,0x00,0x43,0xa0,
4010xca,0x7d,0x84,0x96,0x25,0xb0,0x06,0x3c,0x66,0x03,0xc5,0x34,0x01,0x00,0x84,0x24,
4020xca,0x7d,0x84,0xa6,0xca,0x7d,0x82,0x96,0xff,0x00,0x03,0x24,0x00,0x00,0xa2,0xa4,
4030xaf,0xff,0x23,0x16,0x00,0x00,0x00,0x00,0x21,0x00,0xa0,0x12,0x68,0x15,0xc2,0x26,
4040x00,0x64,0x43,0x90,0x47,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
4050x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
4060x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
4070x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
4080x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
4090x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x60,0x00,0x03,0x3c,
4100x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
4110x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0xf2,0x05,0x00,0x08,0xfc,0x63,0xf1,0xa2,
4120xfc,0x63,0x43,0x90,0x46,0x00,0xe4,0x34,0xb0,0x03,0xc5,0x34,0x00,0x00,0x83,0xa0,
4130x00,0x00,0xa3,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
4140x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
4150x68,0x15,0xc5,0x26,0xfc,0x4a,0xa2,0x8c,0x38,0x00,0xbf,0x8f,0x34,0x00,0xb7,0x8f,
4160x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
4170x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x60,0x00,0x03,0x3c,
4180x25,0x10,0x43,0x00,0x41,0xb0,0x04,0x3c,0x40,0x00,0xbd,0x27,0x00,0x00,0x82,0xac,
4190x08,0x00,0xe0,0x03,0xfc,0x4a,0xa2,0xac,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
4200x88,0x19,0x63,0x24,0x18,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,
4210x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
4220x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x02,0x80,0x05,0x3c,0x68,0x15,0xa5,0x24,
4230x04,0x4b,0xa2,0x8c,0xfc,0x4a,0xa4,0x8c,0x00,0x08,0x03,0x3c,0x24,0x10,0x43,0x00,
4240x25,0x20,0x82,0x00,0x41,0xb0,0x03,0x3c,0x00,0x00,0x64,0xac,0x08,0x00,0xe0,0x03,
4250xfc,0x4a,0xa4,0xac,0x25,0xb0,0x04,0x3c,0x00,0x80,0x02,0x3c,0xc0,0xff,0xbd,0x27,
4260x18,0x03,0x83,0x34,0xe4,0x19,0x42,0x24,0x3c,0x00,0xbf,0xaf,0x38,0x00,0xbe,0xaf,
4270x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x2c,0x00,0xb5,0xaf,0x28,0x00,0xb4,0xaf,
4280x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
4290x00,0x00,0x62,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
4300x02,0x80,0x02,0x3c,0x2a,0xb0,0x03,0x3c,0x68,0x15,0x51,0x24,0xb0,0x03,0x93,0x34,
4310x2c,0x00,0x77,0x34,0x02,0x80,0x15,0x3c,0x02,0x80,0x16,0x3c,0x9c,0x06,0x00,0x08,
4320x02,0x80,0x1e,0x3c,0x14,0x64,0x26,0x92,0xe4,0x64,0x25,0x8e,0x00,0x32,0x06,0x00,
4330x21,0x30,0xc2,0x00,0x78,0x64,0x26,0xae,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
4340xe4,0x64,0x30,0x8e,0x0a,0x00,0x04,0x24,0x21,0x90,0x00,0x00,0x00,0x00,0x70,0xae,
4350x4d,0x01,0x00,0x0c,0xff,0xff,0x10,0x32,0x02,0x80,0x02,0x3c,0x25,0x80,0x02,0x02,
4360x0c,0x00,0x05,0x92,0x02,0x00,0x04,0x92,0xff,0x00,0x02,0x24,0xff,0x00,0xa3,0x30,
4370x04,0x00,0x62,0x10,0x21,0x80,0x04,0x02,0x00,0x00,0x63,0xae,0x01,0x00,0x12,0x24,
4380x14,0x64,0x25,0xa2,0x88,0x96,0xb0,0xae,0x21,0x28,0x00,0x02,0x02,0x00,0xa2,0x90,
4390x08,0x00,0x10,0x26,0x21,0x20,0x00,0x02,0xff,0x00,0x42,0x30,0x00,0x00,0x62,0xae,
4400x03,0x00,0xa3,0x90,0x00,0x00,0x00,0x00,0x7f,0x00,0x63,0x30,0x00,0x00,0x63,0xae,
4410x00,0x00,0x72,0xae,0x03,0x00,0xa2,0x90,0x84,0x96,0xc3,0x92,0x02,0x00,0xa2,0x90,
4420x00,0x00,0x00,0x00,0xff,0x00,0x42,0x30,0x2c,0x00,0x42,0x28,0x11,0x00,0x40,0x10,
4430x08,0x00,0x02,0x24,0x03,0x00,0xa2,0x90,0x00,0x00,0x00,0x00,0x7f,0x00,0x42,0x30,
4440x84,0x96,0xc2,0xa2,0x02,0x00,0xa3,0x90,0x02,0x80,0x02,0x3c,0x74,0x84,0x42,0x24,
4450xff,0x00,0x63,0x30,0xc0,0x18,0x03,0x00,0x21,0x18,0x62,0x00,0x04,0x00,0x62,0x8c,
4460x00,0x00,0x00,0x00,0x09,0xf8,0x40,0x00,0x80,0x96,0xc2,0xaf,0x21,0xa0,0x40,0x00,
4470x08,0x00,0x02,0x24,0x0a,0x00,0x04,0x24,0x05,0x00,0x82,0x12,0x00,0x01,0x07,0x24,
4480x01,0x00,0x02,0x24,0x02,0x00,0x03,0x24,0x01,0x00,0xe2,0xa2,0x01,0x00,0xe3,0xa2,
4490xbc,0xff,0x40,0x16,0x20,0x10,0x02,0x3c,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
4500x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0xfc,0x4a,0x22,0x8e,0x00,0x04,0x03,0x3c,
4510x41,0xb0,0x04,0x3c,0x25,0x10,0x43,0x00,0x00,0x00,0x82,0xac,0x3c,0x00,0xbf,0x8f,
4520xfc,0x4a,0x22,0xae,0x38,0x00,0xbe,0x8f,0x34,0x00,0xb7,0x8f,0x30,0x00,0xb6,0x8f,
4530x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,
4540x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x40,0x00,0xbd,0x27,
4550xc8,0xff,0xbd,0x27,0xff,0xff,0xa8,0x30,0x02,0x80,0x02,0x3c,0x25,0x40,0x02,0x01,
4560x30,0x00,0xb6,0xaf,0x20,0x00,0xb2,0xaf,0x34,0x00,0xbf,0xaf,0x2c,0x00,0xb5,0xaf,
4570x28,0x00,0xb4,0xaf,0x24,0x00,0xb3,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
4580x00,0x00,0x03,0x8d,0xff,0xff,0xd2,0x30,0x21,0xb0,0xa0,0x00,0x00,0xc0,0x02,0x24,
4590x08,0x00,0x45,0x26,0x04,0x00,0x06,0x8d,0x24,0x18,0x62,0x00,0xff,0x3f,0xa5,0x30,
4600xf0,0xff,0x02,0x3c,0x25,0x18,0x65,0x00,0xff,0xff,0x42,0x34,0x24,0x18,0x62,0x00,
4610x00,0x80,0x05,0x3c,0x25,0x18,0x65,0x00,0xff,0x01,0xc6,0x34,0x00,0x00,0x03,0xad,
4620x04,0x00,0x06,0xad,0x21,0x48,0x80,0x00,0xff,0xff,0xe7,0x30,0x18,0x00,0x12,0xa5,
4630x1a,0x00,0x07,0xa1,0x18,0x00,0x03,0x8d,0xff,0x7f,0x02,0x3c,0xff,0xff,0x42,0x34,
4640x24,0x18,0x62,0x00,0x02,0x80,0x15,0x3c,0x18,0x00,0x03,0xad,0x68,0x15,0xa5,0x26,
4650xd6,0x63,0xa3,0x90,0x00,0x00,0x00,0x00,0x01,0x00,0x62,0x24,0xd6,0x63,0xa2,0xa0,
4660x18,0x00,0x04,0x8d,0xff,0x80,0x02,0x3c,0x20,0x00,0x45,0x26,0xff,0xff,0x42,0x34,
4670x7f,0x00,0x63,0x30,0xff,0xff,0xb2,0x30,0x24,0x20,0x82,0x00,0x00,0x1e,0x03,0x00,
4680x25,0xb0,0x02,0x3c,0xc0,0x00,0x42,0x34,0x25,0x20,0x83,0x00,0x07,0x00,0x45,0x32,
4690x18,0x00,0x04,0xad,0x00,0x00,0x52,0xa4,0x03,0x00,0xa0,0x10,0xff,0xff,0x42,0x32,
4700x08,0x00,0x42,0x26,0xff,0xff,0x42,0x30,0x68,0x15,0xb4,0x26,0x54,0x65,0x86,0x8e,
4710x58,0x65,0x90,0x8e,0xf8,0xff,0x52,0x30,0x21,0x10,0xd2,0x00,0x2b,0x10,0x02,0x02,
4720x31,0x00,0x40,0x10,0xff,0x00,0x33,0x31,0x23,0x80,0x06,0x02,0x21,0x28,0xc0,0x02,
4730xff,0xff,0x07,0x32,0x01,0x00,0x11,0x24,0x21,0x20,0x60,0x02,0x10,0x01,0x00,0x0c,
4740x10,0x00,0xb1,0xaf,0x23,0x18,0x50,0x02,0xff,0xff,0x72,0x30,0x22,0x10,0x02,0x3c,
4750x21,0x10,0x42,0x02,0x21,0x20,0x60,0x02,0x4d,0x01,0x00,0x0c,0x54,0x65,0x82,0xae,
4760x21,0x28,0xd0,0x02,0x21,0x38,0x40,0x02,0x21,0x20,0x60,0x02,0x10,0x00,0xb1,0xaf,
4770x22,0x10,0x06,0x3c,0x10,0x01,0x00,0x0c,0x68,0x15,0xb1,0x26,0x54,0x65,0x23,0x8e,
4780x25,0xb0,0x10,0x3c,0xb0,0x03,0x02,0x36,0x21,0x20,0x60,0x02,0x00,0x00,0x43,0xac,
4790x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,0x54,0x65,0x25,0x8e,0xec,0x00,0x02,0x36,
4800xbd,0x00,0x04,0x36,0x00,0x00,0x45,0xac,0x00,0x00,0x83,0x90,0xc2,0x00,0x10,0x36,
4810x34,0x00,0xbf,0x8f,0x10,0x00,0x63,0x34,0x00,0x00,0x83,0xa0,0x30,0x00,0xb6,0x8f,
4820x00,0x00,0x05,0xa6,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,
4830x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,0x01,0x00,0x02,0x24,
4840x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0x21,0x28,0xc0,0x02,0x21,0x20,0x60,0x02,
4850x21,0x38,0x40,0x02,0x01,0x00,0x02,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa2,0xaf,
4860x54,0x65,0x83,0x8e,0x68,0x15,0xb1,0x26,0x25,0xb0,0x10,0x3c,0x21,0x18,0x72,0x00,
4870x54,0x65,0x83,0xae,0x54,0x65,0x23,0x8e,0xb0,0x03,0x02,0x36,0x21,0x20,0x60,0x02,
4880x00,0x00,0x43,0xac,0x4d,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,0x54,0x65,0x25,0x8e,
4890xec,0x00,0x02,0x36,0xbd,0x00,0x04,0x36,0x00,0x00,0x45,0xac,0x00,0x00,0x83,0x90,
4900xc2,0x00,0x10,0x36,0x34,0x00,0xbf,0x8f,0x10,0x00,0x63,0x34,0x00,0x00,0x83,0xa0,
4910x30,0x00,0xb6,0x8f,0x00,0x00,0x05,0xa6,0x2c,0x00,0xb5,0x8f,0x28,0x00,0xb4,0x8f,
4920x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
4930x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,
4940x25,0xb0,0x02,0x3c,0x14,0x00,0xb1,0xaf,0x18,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,
4950xbf,0x00,0x42,0x34,0x00,0x00,0x43,0x90,0x21,0x28,0x00,0x00,0x08,0x00,0x06,0x24,
4960x04,0x00,0x63,0x2c,0x12,0x00,0x60,0x14,0x21,0x88,0x80,0x00,0x00,0x60,0x02,0x40,
4970x01,0x00,0x41,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x02,0x80,0x03,0x3c,
4980x00,0x7b,0x63,0x24,0x04,0x00,0x64,0x8c,0x00,0x00,0x23,0xae,0x04,0x00,0x71,0xac,
4990x00,0x00,0x91,0xac,0x04,0x00,0x24,0xae,0x00,0x60,0x82,0x40,0x18,0x00,0xbf,0x8f,
5000x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
5010x08,0x00,0x82,0x94,0x02,0x80,0x04,0x3c,0x97,0x45,0x00,0x0c,0x25,0x20,0x44,0x00,
5020x00,0x60,0x10,0x40,0x01,0x00,0x01,0x36,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
5030x08,0x00,0x25,0x8e,0x0c,0x00,0x26,0x96,0x14,0x00,0x27,0x96,0xf0,0x06,0x00,0x0c,
5040x09,0x00,0x04,0x24,0x04,0x00,0x23,0x8e,0x00,0x00,0x22,0x8e,0x21,0x20,0x20,0x02,
5050x00,0x00,0x62,0xac,0x04,0x00,0x43,0xac,0x00,0x00,0x31,0xae,0xbd,0x4e,0x00,0x0c,
5060x04,0x00,0x31,0xae,0x00,0x60,0x90,0x40,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,
5070x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0x02,0x80,0x02,0x3c,
5080x68,0x15,0x47,0x24,0x8c,0x64,0xe3,0x90,0xff,0xff,0xa5,0x30,0x09,0x00,0xa3,0x10,
5090x21,0x20,0xc0,0x00,0xfc,0x64,0xe2,0x8c,0x00,0x00,0x00,0x00,0x08,0x00,0xc2,0xac,
5100x06,0x65,0xe3,0x94,0x0e,0x00,0x02,0x24,0x14,0x00,0xc2,0xac,0x8b,0x07,0x00,0x08,
5110x0c,0x00,0xc3,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x80,0x03,0x3c,
5120x25,0xb0,0x02,0x3c,0xd0,0xff,0xbd,0x27,0x4c,0x1f,0x63,0x24,0x18,0x03,0x42,0x34,
5130x28,0x00,0xbf,0xaf,0x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,
5140x18,0x00,0xb0,0xaf,0x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
5150x00,0x60,0x81,0x40,0x2a,0xb0,0x02,0x3c,0x36,0x00,0x42,0x34,0x00,0x00,0x43,0x90,
5160x02,0x80,0x13,0x3c,0x68,0x15,0x66,0x26,0xc0,0x18,0x03,0x00,0x5c,0x65,0xc5,0x8c,
5170x23,0xb0,0x04,0x3c,0xf0,0x07,0x63,0x30,0xff,0x1f,0x02,0x3c,0x21,0x18,0x64,0x00,
5180xff,0xff,0x42,0x34,0x24,0x20,0x62,0x00,0x23,0x88,0x85,0x00,0x2b,0x38,0x85,0x00,
5190x00,0x04,0x22,0x26,0x00,0x65,0xc3,0x8c,0x0b,0x88,0x47,0x00,0x01,0x04,0x25,0x2e,
5200xfc,0x64,0xc3,0xac,0x60,0x65,0xc4,0xac,0x06,0x65,0xc0,0xa4,0x11,0x00,0xa0,0x14,
5210x05,0x65,0xc0,0xa0,0x00,0xfc,0x83,0x24,0x23,0x10,0x02,0x3c,0x0b,0x18,0x87,0x00,
5220xff,0x03,0x42,0x34,0x2b,0x10,0x43,0x00,0x33,0x00,0x40,0x14,0x00,0x00,0x00,0x00,
5230x23,0x88,0x83,0x00,0x2b,0x10,0x83,0x00,0x5c,0x65,0xc3,0xac,0x03,0x00,0x40,0x10,
5240x01,0x04,0x25,0x2e,0x00,0x04,0x31,0x26,0x01,0x04,0x25,0x2e,0x0e,0x00,0xa0,0x10,
5250x68,0x15,0x70,0x26,0x68,0x15,0x70,0x26,0x60,0x65,0x03,0x8e,0x5c,0x65,0x04,0x8e,
5260x00,0x00,0x00,0x00,0x2b,0x10,0x83,0x00,0x25,0x00,0x40,0x14,0x2b,0x10,0x64,0x00,
5270x51,0x00,0x40,0x14,0x25,0xb0,0x02,0x3c,0x80,0x00,0x03,0x24,0xd0,0x03,0x42,0x34,
5280x00,0x00,0x43,0xac,0x68,0x15,0x70,0x26,0x5c,0x65,0x03,0x96,0x2a,0xb0,0x02,0x3c,
5290x35,0x00,0x42,0x34,0xc2,0x88,0x03,0x00,0x00,0x00,0x51,0xa0,0x8f,0x10,0x00,0x0c,
5300x00,0x00,0x00,0x00,0x06,0x65,0x03,0x96,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,
5310x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
5320x00,0x60,0x81,0x40,0xfc,0x4a,0x02,0x8e,0x80,0x00,0x03,0x3c,0x41,0xb0,0x04,0x3c,
5330x25,0x10,0x43,0x00,0x00,0x00,0x82,0xac,0x28,0x00,0xbf,0x8f,0xfc,0x4a,0x02,0xae,
5340x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
5350x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,0x00,0x08,0x00,0x08,0x00,0xfc,0x63,0x24,
5360xfc,0x64,0x05,0x8e,0x21,0x30,0x80,0x00,0xff,0xff,0x27,0x32,0x09,0x00,0x04,0x24,
5370x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0xfc,0x64,0x03,0x8e,0x06,0x65,0x05,0x96,
5380x5c,0x65,0x02,0x8e,0x21,0x18,0x71,0x00,0x21,0x28,0x25,0x02,0x21,0x10,0x51,0x00,
5390x09,0x00,0x04,0x24,0x5c,0x65,0x02,0xae,0xfc,0x64,0x03,0xae,0x4d,0x01,0x00,0x0c,
5400x06,0x65,0x05,0xa6,0x68,0x15,0x70,0x26,0x5c,0x65,0x03,0x96,0x2a,0xb0,0x02,0x3c,
5410x35,0x00,0x42,0x34,0xc2,0x88,0x03,0x00,0x00,0x00,0x51,0xa0,0x8f,0x10,0x00,0x0c,
5420x00,0x00,0x00,0x00,0x06,0x65,0x03,0x96,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,
5430x00,0x00,0x43,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
5440x00,0x60,0x81,0x40,0xfc,0x4a,0x02,0x8e,0x80,0x00,0x03,0x3c,0x41,0xb0,0x04,0x3c,
5450x25,0x10,0x43,0x00,0x00,0x00,0x82,0xac,0x28,0x00,0xbf,0x8f,0xfc,0x4a,0x02,0xae,
5460x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
5470x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,0x64,0x65,0x02,0x8e,0xfc,0x64,0x05,0x8e,
5480x21,0x30,0x80,0x00,0x23,0x88,0x44,0x00,0xff,0xff,0x27,0x32,0x09,0x00,0x04,0x24,
5490x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0xfc,0x64,0x03,0x8e,0x06,0x65,0x02,0x96,
5500x60,0x65,0x12,0x96,0x21,0x18,0x71,0x00,0x21,0x10,0x22,0x02,0x23,0x10,0x11,0x3c,
5510xfc,0x64,0x03,0xae,0x06,0x65,0x02,0xa6,0x06,0x00,0x40,0x16,0x5c,0x65,0x11,0xae,
5520x09,0x00,0x04,0x24,0x4d,0x01,0x00,0x0c,0x68,0x15,0x70,0x26,0x46,0x08,0x00,0x08,
5530x00,0x00,0x00,0x00,0x4d,0x01,0x00,0x0c,0x09,0x00,0x04,0x24,0xfc,0x64,0x05,0x8e,
5540x09,0x00,0x04,0x24,0x23,0x10,0x06,0x3c,0x21,0x38,0x40,0x02,0x10,0x01,0x00,0x0c,
5550x10,0x00,0xa0,0xaf,0xfc,0x64,0x03,0x8e,0x06,0x65,0x02,0x96,0x21,0x20,0x51,0x02,
5560x21,0x18,0x72,0x00,0x21,0x10,0x42,0x02,0x5c,0x65,0x04,0xae,0x09,0x00,0x04,0x24,
5570xfc,0x64,0x03,0xae,0x75,0x08,0x00,0x08,0x06,0x65,0x02,0xa6,0x02,0x80,0x09,0x3c,
5580x68,0x15,0x28,0x25,0xdc,0x63,0x06,0x8d,0xff,0xff,0x02,0x34,0x3f,0x00,0xc2,0x10,
5590x21,0x38,0x80,0x00,0x2b,0x10,0xc7,0x00,0x30,0x00,0x40,0x10,0x02,0x19,0x06,0x00,
5600x21,0x10,0xc7,0x00,0x23,0x10,0x43,0x00,0x10,0x00,0x46,0x24,0xdc,0x63,0x06,0xad,
5610x68,0x15,0x26,0x25,0x04,0x40,0xc4,0x8c,0xe0,0x63,0x02,0xad,0xff,0xff,0x02,0x34,
5620x2f,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0x2b,0x10,0x87,0x00,0x1f,0x00,0x40,0x10,
5630x02,0x19,0x04,0x00,0x21,0x10,0x87,0x00,0x23,0x10,0x43,0x00,0x10,0x00,0x44,0x24,
5640x04,0x40,0xc4,0xac,0xe0,0x63,0xc2,0xac,0xc0,0x10,0x05,0x00,0x21,0x10,0x45,0x00,
5650x80,0x10,0x02,0x00,0x21,0x10,0x45,0x00,0x68,0x15,0x23,0x25,0x80,0x10,0x02,0x00,
5660x21,0x28,0x43,0x00,0x68,0x51,0xa6,0x8c,0x00,0x21,0x07,0x00,0xff,0xff,0xc2,0x38,
5670x0a,0x30,0x82,0x00,0x2b,0x18,0xc7,0x00,0x07,0x00,0x60,0x10,0x21,0x10,0xc7,0x00,
5680x02,0x19,0x06,0x00,0x23,0x10,0x43,0x00,0x10,0x00,0x46,0x24,0x68,0x51,0xa6,0xac,
5690x08,0x00,0xe0,0x03,0x6c,0x51,0xa2,0xac,0x02,0x19,0x06,0x00,0x23,0x10,0x43,0x00,
5700x68,0x51,0xa2,0xac,0x08,0x00,0xe0,0x03,0x6c,0x51,0xa2,0xac,0x21,0x10,0x87,0x00,
5710x23,0x10,0x43,0x00,0xa5,0x08,0x00,0x08,0x04,0x40,0xc2,0xac,0x21,0x10,0xc7,0x00,
5720x68,0x15,0x26,0x25,0x04,0x40,0xc4,0x8c,0x23,0x10,0x43,0x00,0xdc,0x63,0x02,0xad,
5730xe0,0x63,0x02,0xad,0xff,0xff,0x02,0x34,0xd4,0xff,0x82,0x14,0x2b,0x10,0x87,0x00,
5740x00,0x21,0x07,0x00,0x9e,0x08,0x00,0x08,0x04,0x40,0xc4,0xac,0x00,0x31,0x04,0x00,
5750x91,0x08,0x00,0x08,0xdc,0x63,0x06,0xad,0x63,0x00,0x82,0x24,0x77,0x00,0x42,0x2c,
5760x00,0x00,0x85,0x28,0x04,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0x64,0x00,0x82,0x24,
5770x64,0x00,0x03,0x24,0x0b,0x18,0x45,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
5780x0c,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x3f,0x00,0x42,0x30,0x04,0x00,0x42,0x28,
5790x17,0x00,0x40,0x10,0x25,0xb0,0x02,0x3c,0x24,0x08,0x42,0x34,0x00,0x00,0x43,0x8c,
5800x00,0x00,0x00,0x00,0x00,0x02,0x63,0x30,0x16,0x00,0x60,0x14,0x01,0x00,0x02,0x24,
5810x05,0x00,0xa3,0x90,0x00,0x00,0x00,0x00,0x82,0x21,0x03,0x00,0x28,0x00,0x82,0x10,
5820xf5,0xff,0x02,0x24,0x02,0x00,0x82,0x28,0x39,0x00,0x40,0x14,0x02,0x00,0x02,0x24,
5830x2e,0x00,0x82,0x10,0xe9,0xff,0x02,0x24,0x03,0x00,0x02,0x24,0x24,0x00,0x82,0x10,
5840x3e,0x00,0x63,0x30,0x05,0x00,0xc4,0x24,0xd2,0x08,0x00,0x08,0x00,0x00,0x00,0x00,
5850x04,0x00,0xa4,0x90,0x00,0x00,0x00,0x00,0x42,0x20,0x04,0x00,0xd2,0x08,0x00,0x08,
5860x96,0xff,0x84,0x24,0x05,0x00,0xa3,0x90,0x00,0x00,0x00,0x00,0x60,0x00,0x64,0x30,
5870x42,0x21,0x04,0x00,0x0e,0x00,0x82,0x10,0x1f,0x00,0x62,0x30,0x02,0x00,0x82,0x28,
5880x1d,0x00,0x40,0x14,0x02,0x00,0x02,0x24,0x14,0x00,0x82,0x10,0x1f,0x00,0x62,0x30,
5890x03,0x00,0x02,0x24,0xeb,0xff,0x82,0x14,0x1f,0x00,0x62,0x30,0x40,0x10,0x02,0x00,
5900xdd,0xff,0x03,0x24,0x23,0x30,0x62,0x00,0xf6,0x08,0x00,0x08,0x05,0x00,0xc4,0x24,
5910x40,0x10,0x02,0x00,0xf5,0xff,0x03,0x24,0x0e,0x09,0x00,0x08,0x23,0x30,0x62,0x00,
5920x3e,0x00,0x63,0x30,0x23,0x30,0x43,0x00,0xf6,0x08,0x00,0x08,0x05,0x00,0xc4,0x24,
5930xdd,0xff,0x02,0x24,0x16,0x09,0x00,0x08,0x23,0x30,0x43,0x00,0x40,0x10,0x02,0x00,
5940xe9,0xff,0x03,0x24,0x0e,0x09,0x00,0x08,0x23,0x30,0x62,0x00,0x3e,0x00,0x63,0x30,
5950x16,0x09,0x00,0x08,0x23,0x30,0x43,0x00,0xd2,0xff,0x80,0x14,0x1f,0x00,0x62,0x30,
5960x40,0x10,0x02,0x00,0xf8,0xff,0x03,0x24,0x0e,0x09,0x00,0x08,0x23,0x30,0x62,0x00,
5970xcc,0xff,0x80,0x14,0x3e,0x00,0x63,0x30,0xf8,0xff,0x02,0x24,0x16,0x09,0x00,0x08,
5980x23,0x30,0x43,0x00,0xa0,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x4c,0x00,0xb5,0xaf,
5990x5c,0x00,0xbf,0xaf,0x58,0x00,0xbe,0xaf,0x54,0x00,0xb7,0xaf,0x50,0x00,0xb6,0xaf,
6000x48,0x00,0xb4,0xaf,0x44,0x00,0xb3,0xaf,0x40,0x00,0xb2,0xaf,0x3c,0x00,0xb1,0xaf,
6010x38,0x00,0xb0,0xaf,0x68,0x15,0x55,0x24,0x25,0xb0,0x03,0x3c,0x04,0x01,0x62,0x34,
6020x00,0x00,0x43,0x8c,0x44,0x65,0xa7,0x8e,0x00,0x00,0x00,0x00,0x33,0x00,0xe3,0x10,
6030x48,0x65,0xa3,0xae,0x2b,0x10,0x67,0x00,0xa8,0x00,0x40,0x14,0x2b,0x10,0xe3,0x00,
6040xd1,0x00,0x40,0x14,0x02,0x80,0x02,0x3c,0x68,0x15,0x44,0x24,0x18,0x65,0x83,0x94,
6050x02,0x80,0x02,0x3c,0x21,0x88,0x00,0x00,0x19,0x00,0x40,0x1a,0x25,0x98,0x62,0x00,
6060x21,0xb8,0x80,0x00,0x21,0xb0,0x80,0x00,0x01,0x00,0x14,0x24,0x21,0x20,0x00,0x00,
6070x21,0x80,0x93,0x00,0x00,0x00,0x05,0x8e,0x00,0x00,0x00,0x00,0x07,0x00,0xa0,0x10,
6080x01,0x00,0x22,0x26,0x04,0x00,0x02,0x8e,0x00,0xf0,0x03,0x3c,0x00,0x20,0x04,0x3c,
6090x24,0x10,0x43,0x00,0x1e,0x00,0x44,0x10,0x06,0x00,0x22,0x26,0xff,0xff,0x51,0x30,
6100x82,0x16,0x05,0x00,0x01,0x00,0x42,0x30,0x34,0x00,0x54,0x10,0x00,0x00,0x00,0x00,
6110x80,0x20,0x11,0x00,0x2a,0x10,0x92,0x00,0xed,0xff,0x40,0x14,0x00,0x00,0x00,0x00,
6120xbd,0x4e,0x00,0x0c,0x21,0x20,0xc0,0x03,0x02,0x80,0x02,0x3c,0x08,0x04,0x44,0x24,
6130x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x31,0x1c,0x00,0x0c,0x21,0x38,0x00,0x00,
6140x25,0xb0,0x03,0x3c,0x04,0x01,0x62,0x34,0x00,0x00,0x43,0x8c,0x44,0x65,0xa7,0x8e,
6150x00,0x00,0x00,0x00,0xcf,0xff,0xe3,0x14,0x48,0x65,0xa3,0xae,0x25,0xb0,0x03,0x3c,
6160x00,0x01,0x62,0x34,0x00,0x00,0x47,0xac,0x66,0x09,0x00,0x08,0x44,0x65,0xa7,0xae,
6170xb0,0x4c,0xe2,0x8e,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0xb0,0x4c,0xe2,0xae,
6180x0c,0x00,0x04,0x8e,0x0c,0x00,0x02,0x24,0x3f,0x00,0x83,0x30,0x64,0x00,0x62,0x10,
6190x21,0x28,0xe0,0x02,0x3f,0x00,0x83,0x30,0x0d,0x00,0x02,0x24,0x59,0x00,0x62,0x10,
6200x00,0x00,0x00,0x00,0x3f,0x00,0x83,0x30,0x0e,0x00,0x02,0x24,0x04,0x00,0x62,0x10,
6210x00,0x00,0x00,0x00,0x00,0x00,0x05,0x8e,0x5b,0x09,0x00,0x08,0x06,0x00,0x22,0x26,
6220xbc,0x4c,0xe2,0x8e,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0xbc,0x4c,0xe2,0xae,
6230x00,0x00,0x05,0x8e,0x5b,0x09,0x00,0x08,0x06,0x00,0x22,0x26,0x00,0x40,0xc2,0x8e,
6240x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,0x0f,0x00,0x42,0x30,0x05,0x00,0x54,0x10,
6250xc2,0x13,0x05,0x00,0x1e,0x00,0x42,0x30,0x21,0x10,0x51,0x00,0x60,0x09,0x00,0x08,
6260xff,0xff,0x51,0x30,0x02,0x40,0xc2,0x92,0x00,0x00,0x00,0x00,0x1e,0x00,0x40,0x14,
6270x02,0x80,0x03,0x3c,0x04,0x00,0x03,0x8e,0x00,0x00,0x00,0x00,0x02,0x14,0x03,0x00,
6280x0f,0x00,0x42,0x30,0x17,0x00,0x40,0x14,0x02,0x17,0x03,0x00,0x03,0x00,0x44,0x30,
6290x08,0x00,0x80,0x10,0x00,0xc0,0x02,0x3c,0x24,0x10,0x62,0x00,0x11,0x00,0x40,0x14,
6300x03,0x00,0x02,0x24,0x10,0x00,0x82,0x10,0x02,0x80,0x03,0x3c,0x0f,0x00,0x80,0x10,
6310x68,0x15,0x63,0x24,0x80,0x10,0x11,0x00,0x21,0x28,0x53,0x00,0xec,0xff,0xa3,0x8c,
6320x25,0xb0,0x02,0x3c,0xd4,0x02,0x42,0x34,0x21,0x20,0x00,0x02,0x00,0x00,0x43,0xac,
6330xdc,0x08,0x00,0x0c,0x00,0x00,0x00,0x00,0x21,0x20,0x40,0x00,0x8b,0x08,0x00,0x0c,
6340x21,0x28,0x00,0x00,0x02,0x80,0x03,0x3c,0x68,0x15,0x63,0x24,0x02,0x40,0x62,0x90,
6350x00,0x00,0x00,0x00,0x85,0x00,0x54,0x10,0x00,0x00,0x00,0x00,0x02,0x80,0x04,0x3c,
6360x68,0x15,0x84,0x24,0x02,0x40,0x83,0x90,0x02,0x00,0x02,0x24,0x68,0x00,0x62,0x10,
6370x00,0x00,0x00,0x00,0x25,0xb0,0x03,0x3c,0x4c,0x00,0x63,0x34,0x00,0x00,0x62,0x90,
6380x00,0x00,0x00,0x00,0x03,0x00,0x42,0x30,0x08,0x00,0x54,0x10,0x02,0x80,0x04,0x3c,
6390x00,0x00,0x05,0x8e,0x00,0x00,0x00,0x00,0xc2,0x13,0x05,0x00,0x1e,0x00,0x42,0x30,
6400x21,0x10,0x51,0x00,0x60,0x09,0x00,0x08,0xff,0xff,0x51,0x30,0xd0,0x02,0x02,0x24,
6410x68,0x15,0x84,0x24,0xdc,0x63,0x82,0xac,0x00,0x00,0x05,0x8e,0xd3,0x09,0x00,0x08,
6420xc2,0x13,0x05,0x00,0xb8,0x4c,0xa2,0x8c,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,
6430xb8,0x4c,0xa2,0xac,0x0c,0x00,0x04,0x8e,0x86,0x09,0x00,0x08,0x3f,0x00,0x83,0x30,
6440xb4,0x4c,0xe2,0x8e,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0xb4,0x4c,0xe2,0xae,
6450x0c,0x00,0x04,0x8e,0x82,0x09,0x00,0x08,0x3f,0x00,0x83,0x30,0x4c,0x65,0xa2,0x8e,
6460xff,0xff,0x71,0x30,0x23,0x10,0x47,0x00,0xff,0xff,0x50,0x30,0x21,0x18,0x11,0x02,
6470xff,0xff,0x72,0x30,0xa1,0x4e,0x00,0x0c,0x21,0x20,0x40,0x02,0x76,0x00,0x40,0x10,
6480x21,0xf0,0x40,0x00,0x08,0x00,0x42,0x8c,0x44,0x65,0xa6,0x8e,0x21,0x38,0x00,0x02,
6490x21,0x18,0x52,0x00,0x21,0x28,0x40,0x00,0x08,0x00,0x04,0x24,0x14,0x65,0xa3,0xae,
6500x18,0x65,0xa2,0xae,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x4d,0x01,0x00,0x0c,
6510x08,0x00,0x04,0x24,0x18,0x65,0xa5,0x8e,0x25,0xb0,0x03,0x3c,0x24,0x10,0x02,0x3c,
6520x21,0x28,0xb0,0x00,0x00,0x01,0x70,0x34,0x00,0x00,0x02,0xae,0x21,0x38,0x20,0x02,
6530x08,0x00,0x04,0x24,0x24,0x10,0x06,0x3c,0x44,0x65,0xa2,0xae,0x10,0x01,0x00,0x0c,
6540x10,0x00,0xa0,0xaf,0x48,0x65,0xa3,0x8e,0x08,0x00,0x04,0x24,0x4d,0x01,0x00,0x0c,
6550x44,0x65,0xa3,0xae,0x44,0x65,0xa2,0x8e,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0xae,
6560x46,0x09,0x00,0x08,0x02,0x80,0x02,0x3c,0x23,0x10,0x67,0x00,0xff,0xff,0x52,0x30,
6570xa1,0x4e,0x00,0x0c,0x21,0x20,0x40,0x02,0x56,0x00,0x40,0x10,0x21,0xf0,0x40,0x00,
6580x08,0x00,0x42,0x8c,0x44,0x65,0xa6,0x8e,0x08,0x00,0x04,0x24,0x21,0x18,0x52,0x00,
6590x21,0x28,0x40,0x00,0x21,0x38,0x40,0x02,0x14,0x65,0xa3,0xae,0x18,0x65,0xa2,0xae,
6600x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x48,0x65,0xa3,0x8e,0x08,0x00,0x04,0x24,
6610x4d,0x01,0x00,0x0c,0x44,0x65,0xa3,0xae,0x44,0x65,0xa3,0x8e,0x25,0xb0,0x04,0x3c,
6620x00,0x01,0x82,0x34,0x00,0x00,0x43,0xac,0x46,0x09,0x00,0x08,0x02,0x80,0x02,0x3c,
6630x04,0x00,0x03,0x8e,0x00,0x00,0x00,0x00,0x02,0x14,0x03,0x00,0x0f,0x00,0x42,0x30,
6640x08,0x00,0x42,0x28,0x93,0xff,0x40,0x10,0x02,0x17,0x03,0x00,0x03,0x00,0x42,0x30,
6650x90,0xff,0x40,0x14,0x80,0x10,0x11,0x00,0x21,0x28,0x53,0x00,0xec,0xff,0xa3,0x8c,
6660x25,0xb0,0x02,0x3c,0xd4,0x02,0x42,0x34,0x21,0x20,0x00,0x02,0x00,0x00,0x43,0xac,
6670xdc,0x08,0x00,0x0c,0x00,0x00,0x00,0x00,0x21,0x20,0x40,0x00,0x8b,0x08,0x00,0x0c,
6680x21,0x28,0x00,0x00,0xca,0x09,0x00,0x08,0x25,0xb0,0x03,0x3c,0x04,0x00,0x03,0x8e,
6690x00,0x00,0x00,0x00,0x02,0x14,0x03,0x00,0x0f,0x00,0x42,0x30,0x08,0x00,0x42,0x28,
6700x06,0x00,0x40,0x10,0x00,0xc0,0x02,0x3c,0x02,0x17,0x03,0x00,0x03,0x00,0x42,0x30,
6710x0c,0x00,0x40,0x10,0x80,0x10,0x11,0x00,0x00,0xc0,0x02,0x3c,0x24,0x10,0x62,0x00,
6720x6f,0xff,0x40,0x14,0x02,0x80,0x04,0x3c,0x02,0x17,0x03,0x00,0x03,0x00,0x42,0x30,
6730x03,0x00,0x03,0x24,0x6b,0xff,0x43,0x10,0x68,0x15,0x84,0x24,0x67,0xff,0x40,0x10,
6740x80,0x10,0x11,0x00,0x21,0x28,0x53,0x00,0xec,0xff,0xa3,0x8c,0x25,0xb0,0x02,0x3c,
6750xd4,0x02,0x42,0x34,0x21,0x20,0x00,0x02,0x00,0x00,0x43,0xac,0xdc,0x08,0x00,0x0c,
6760x00,0x00,0x00,0x00,0x21,0x20,0x40,0x00,0x8b,0x08,0x00,0x0c,0x21,0x28,0x00,0x00,
6770xc4,0x09,0x00,0x08,0x02,0x80,0x04,0x3c,0x25,0xb0,0x04,0x3c,0x44,0x44,0x02,0x3c,
6780xbc,0x02,0x83,0x34,0x44,0x44,0x42,0x34,0x00,0x00,0x62,0xac,0x67,0x09,0x00,0x08,
6790x02,0x80,0x02,0x3c,0x48,0x65,0xa5,0x8e,0x25,0xb0,0x04,0x3c,0x66,0x66,0x02,0x3c,
6800x00,0x01,0x83,0x34,0x66,0x66,0x42,0x34,0xbc,0x02,0x84,0x34,0x00,0x00,0x65,0xac,
6810x00,0x00,0x82,0xac,0x66,0x09,0x00,0x08,0x44,0x65,0xa5,0xae,0x00,0x60,0x02,0x40,
6820x01,0x00,0x41,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x02,0x80,0x03,0x3c,
6830xd8,0x8c,0x64,0xac,0x00,0x60,0x82,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
6840x02,0x80,0x02,0x3c,0xd8,0x8c,0x45,0x8c,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
6850x18,0x03,0x42,0x34,0x10,0x2a,0x63,0x24,0x00,0x00,0x43,0xac,0x04,0x00,0x02,0x24,
6860x1e,0x00,0xa2,0x10,0x05,0x00,0xa2,0x2c,0x10,0x00,0x40,0x10,0x05,0x00,0x02,0x24,
6870x03,0x00,0x02,0x24,0x08,0x00,0xa2,0x10,0x00,0x19,0x04,0x00,0x80,0x10,0x04,0x00,
6880x21,0x10,0x44,0x00,0xc0,0x10,0x02,0x00,0x23,0x10,0x44,0x00,0x00,0x11,0x02,0x00,
6890x21,0x10,0x44,0x00,0x40,0x19,0x02,0x00,0xff,0xff,0x63,0x24,0xfe,0xff,0x60,0x14,
6900x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xf3,0xff,0xa2,0x10,
6910x06,0x00,0x02,0x24,0xf2,0xff,0xa2,0x14,0x80,0x10,0x04,0x00,0x40,0x11,0x04,0x00,
6920x23,0x10,0x44,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x44,0x00,0x00,0x19,0x02,0x00,
6930x23,0x18,0x62,0x00,0x9a,0x0a,0x00,0x08,0x00,0x19,0x03,0x00,0x80,0x10,0x04,0x00,
6940x21,0x10,0x44,0x00,0xc0,0x10,0x02,0x00,0x23,0x10,0x44,0x00,0x00,0x11,0x02,0x00,
6950x21,0x10,0x44,0x00,0x9a,0x0a,0x00,0x08,0x00,0x19,0x02,0x00,0x02,0x80,0x02,0x3c,
6960xd8,0x8c,0x45,0x8c,0x00,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,0x18,0x03,0x42,0x34,
6970xcc,0x2a,0x63,0x24,0x00,0x00,0x43,0xac,0x05,0x00,0x02,0x24,0x10,0x00,0xa2,0x10,
6980x06,0x00,0xa2,0x2c,0x09,0x00,0x40,0x14,0x04,0x00,0x02,0x24,0x06,0x00,0x02,0x24,
6990x0f,0x00,0xa2,0x10,0x00,0x11,0x04,0x00,0xff,0xff,0x84,0x24,0xfe,0xff,0x80,0x14,
7000x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xfa,0xff,0xa2,0x14,
7010x80,0x10,0x04,0x00,0x21,0x10,0x44,0x00,0xc2,0x0a,0x00,0x08,0x40,0x20,0x02,0x00,
7020x80,0x10,0x04,0x00,0x21,0x10,0x44,0x00,0xc2,0x0a,0x00,0x08,0x80,0x20,0x02,0x00,
7030x23,0x10,0x44,0x00,0xc2,0x0a,0x00,0x08,0x40,0x20,0x02,0x00,0xff,0xff,0x85,0x30,
7040x21,0x30,0x00,0x00,0x25,0xb0,0x03,0x3c,0x2a,0xb0,0x04,0x3c,0xb4,0x00,0x63,0x34,
7050x01,0x00,0xa2,0x24,0x31,0x00,0x84,0x34,0x00,0x00,0x65,0xa0,0x00,0x00,0x85,0xa0,
7060xff,0xff,0x45,0x30,0x12,0x00,0xa0,0x10,0x01,0x00,0x03,0x24,0x28,0xb0,0x07,0x3c,
7070xe8,0x0a,0x00,0x08,0xff,0xff,0x08,0x24,0x00,0x00,0x83,0xa0,0x01,0x00,0x63,0x24,
7080xff,0xff,0x63,0x30,0x2b,0x10,0xa3,0x00,0x09,0x00,0x40,0x14,0x08,0x00,0xc6,0x24,
7090xf9,0xff,0x65,0x14,0x21,0x20,0xc7,0x00,0x01,0x00,0x63,0x24,0xff,0xff,0x63,0x30,
7100x2b,0x10,0xa3,0x00,0x00,0x00,0x88,0xa0,0xf9,0xff,0x40,0x10,0x08,0x00,0xc6,0x24,
7110x00,0x01,0xa2,0x2c,0x13,0x00,0x40,0x10,0x21,0x18,0xa0,0x00,0xff,0x00,0x08,0x24,
7120x28,0xb0,0x07,0x3c,0xfc,0x0a,0x00,0x08,0xff,0xff,0x09,0x24,0xff,0xff,0x43,0x30,
7130x00,0x00,0xa2,0xa0,0x00,0x01,0x62,0x2c,0x0a,0x00,0x40,0x10,0x08,0x00,0xc6,0x24,
7140x01,0x00,0x62,0x24,0xf9,0xff,0x68,0x14,0x21,0x28,0xc7,0x00,0x00,0x01,0x02,0x24,
7150xff,0xff,0x43,0x30,0x00,0x01,0x62,0x2c,0x00,0x00,0xa9,0xa0,0xf8,0xff,0x40,0x14,
7160x08,0x00,0xc6,0x24,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xd8,0xff,0xbd,0x27,
7170x24,0x00,0xbf,0xaf,0x20,0x00,0xb4,0xaf,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,
7180x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
7190x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x25,0xb0,0x10,0x3c,0x42,0x00,0x14,0x36,
7200xff,0xff,0x02,0x24,0x00,0x00,0x82,0xa2,0xd8,0x00,0x05,0x36,0x40,0x00,0x11,0x36,
7210xa8,0x00,0x13,0x36,0xa0,0x00,0x12,0x36,0x00,0x10,0x03,0x24,0xa4,0x00,0x10,0x36,
7220x00,0x80,0x02,0x3c,0x00,0x00,0x23,0xa6,0x00,0x00,0xa0,0xa0,0x00,0x00,0x40,0xae,
7230x00,0x00,0x00,0xae,0x00,0x00,0x62,0xae,0x00,0x00,0xa3,0x90,0x80,0xff,0x02,0x24,
7240xfd,0x00,0x04,0x24,0x25,0x18,0x62,0x00,0xfc,0x17,0x02,0x24,0x00,0x00,0xa3,0xa0,
7250x00,0x00,0x22,0xa6,0xd3,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,
7260x68,0x15,0x42,0x24,0x68,0x4b,0x45,0x8c,0x60,0x4b,0x43,0x8c,0x64,0x4b,0x44,0x8c,
7270xfc,0x37,0x02,0x24,0x00,0x00,0x43,0xae,0x00,0x00,0x04,0xae,0x00,0x00,0x65,0xae,
7280x00,0x00,0x22,0xa6,0x00,0x00,0x80,0xa2,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
7290x00,0x60,0x81,0x40,0x24,0x00,0xbf,0x8f,0x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,
7300x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,
7310x28,0x00,0xbd,0x27,0xd0,0xff,0xbd,0x27,0x2c,0x00,0xbf,0xaf,0x28,0x00,0xb6,0xaf,
7320x24,0x00,0xb5,0xaf,0x20,0x00,0xb4,0xaf,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,
7330x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
7340x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x25,0xb0,0x10,0x3c,0x40,0x00,0x05,0x36,
7350x00,0x00,0xa2,0x94,0x24,0xfa,0x03,0x24,0xa8,0x00,0x13,0x36,0x24,0x10,0x43,0x00,
7360x00,0x00,0xa2,0xa4,0xa0,0x00,0x12,0x36,0xa4,0x00,0x10,0x36,0x00,0x00,0x55,0x8e,
7370x00,0x00,0x16,0x8e,0x00,0x00,0x71,0x8e,0x00,0x80,0x14,0x3c,0xfc,0x37,0x02,0x24,
7380x00,0x00,0x40,0xae,0xfd,0x00,0x04,0x24,0x00,0x00,0x00,0xae,0x21,0x88,0x34,0x02,
7390x00,0x00,0x74,0xae,0x00,0x00,0xa2,0xa4,0xd3,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,
7400x00,0x00,0x55,0xae,0x00,0x00,0x16,0xae,0x00,0x00,0x71,0xae,0x00,0x60,0x01,0x40,
7410x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x2c,0x00,0xbf,0x8f,0x28,0x00,0xb6,0x8f,
7420x24,0x00,0xb5,0x8f,0x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,
7430x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,
7440xd0,0xff,0xbd,0x27,0x2c,0x00,0xbf,0xaf,0x28,0x00,0xb6,0xaf,0x24,0x00,0xb5,0xaf,
7450x20,0x00,0xb4,0xaf,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,0x14,0x00,0xb1,0xaf,
7460x10,0x00,0xb0,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
7470x00,0x60,0x81,0x40,0x25,0xb0,0x10,0x3c,0x40,0x00,0x05,0x36,0x00,0x00,0xa2,0x94,
7480xaf,0xff,0x03,0x24,0xa8,0x00,0x13,0x36,0x24,0x10,0x43,0x00,0x00,0x00,0xa2,0xa4,
7490xa0,0x00,0x12,0x36,0xa4,0x00,0x10,0x36,0x00,0x00,0x55,0x8e,0x00,0x00,0x16,0x8e,
7500x00,0x00,0x71,0x8e,0x00,0x80,0x14,0x3c,0xfc,0x37,0x02,0x24,0x00,0x00,0x40,0xae,
7510xfd,0x00,0x04,0x24,0x00,0x00,0x00,0xae,0x21,0x88,0x34,0x02,0x00,0x00,0x74,0xae,
7520x00,0x00,0xa2,0xa4,0xd3,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x55,0xae,
7530x00,0x00,0x16,0xae,0x00,0x00,0x71,0xae,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
7540x00,0x60,0x81,0x40,0x2c,0x00,0xbf,0x8f,0x28,0x00,0xb6,0x8f,0x24,0x00,0xb5,0x8f,
7550x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
7560x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,0x00,0x60,0x01,0x40,
7570x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x25,0xb0,0x04,0x3c,
7580x40,0x00,0x84,0x34,0x00,0x00,0x82,0x94,0xd8,0xfd,0x03,0x24,0x24,0x10,0x43,0x00,
7590xfc,0x37,0x03,0x24,0x00,0x00,0x82,0xa4,0x00,0x00,0x83,0xa4,0x00,0x60,0x01,0x40,
7600x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
7610x00,0x00,0x82,0x8c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xff,0xff,0xc6,0x30,
7620x10,0x00,0x02,0x24,0x0c,0x00,0xc2,0x10,0x11,0x00,0xc3,0x28,0x06,0x00,0x60,0x10,
7630x20,0x00,0x02,0x24,0x08,0x00,0x02,0x24,0x0d,0x00,0xc2,0x10,0x00,0x00,0x00,0x00,
7640x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x06,0x00,0xc2,0x10,0x00,0x00,0x00,0x00,
7650x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0xa4,0x08,0x00,0xe0,0x03,
7660x00,0x00,0x00,0x00,0x00,0x00,0x85,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
7670x00,0x00,0x85,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
7680x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x25,0xb0,0x02,0x3c,
7690x0a,0x00,0x42,0x34,0x00,0x00,0x43,0x90,0xff,0xff,0xa5,0x24,0x00,0x2c,0x05,0x00,
7700xfd,0x00,0x63,0x30,0x03,0x2c,0x05,0x00,0xff,0xff,0x87,0x30,0x00,0x00,0x43,0xa0,
7710x1a,0x00,0xa0,0x04,0x00,0x00,0x00,0x00,0x21,0x30,0x40,0x00,0x07,0x10,0xa7,0x00,
7720x01,0x00,0x42,0x30,0xfd,0x00,0x64,0x30,0x00,0x00,0x42,0x38,0x02,0x00,0x63,0x34,
7730x0a,0x18,0x82,0x00,0x00,0x00,0xc3,0xa0,0x04,0x00,0x63,0x34,0x00,0x00,0xc3,0xa0,
7740x09,0x00,0x02,0x24,0xff,0xff,0x42,0x24,0xff,0xff,0x41,0x04,0xff,0xff,0x42,0x24,
7750xfb,0x00,0x63,0x30,0x00,0x00,0xc3,0xa0,0x04,0x00,0x02,0x24,0xff,0xff,0x42,0x24,
7760xff,0xff,0x41,0x04,0xff,0xff,0x42,0x24,0xff,0xff,0xa2,0x24,0x00,0x2c,0x02,0x00,
7770x03,0x2c,0x05,0x00,0xea,0xff,0xa1,0x04,0x07,0x10,0xa7,0x00,0x08,0x00,0xe0,0x03,
7780x00,0x00,0x00,0x00,0x25,0xb0,0x02,0x3c,0x0a,0x00,0x42,0x34,0x00,0x00,0x43,0x90,
7790xff,0xff,0x84,0x24,0x00,0x24,0x04,0x00,0x03,0x24,0x04,0x00,0xff,0x00,0x65,0x30,
7800x1d,0x00,0x80,0x04,0x21,0x38,0x00,0x00,0x21,0x30,0x40,0x00,0x01,0x00,0x08,0x24,
7810x04,0x00,0xa5,0x34,0x00,0x00,0xc5,0xa0,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,
7820xff,0x00,0x45,0x30,0x01,0x00,0xa3,0x30,0x05,0x00,0x60,0x10,0x04,0x00,0x02,0x24,
7830x04,0x10,0x88,0x00,0x25,0x10,0x47,0x00,0xff,0xff,0x47,0x30,0x04,0x00,0x02,0x24,
7840xff,0xff,0x42,0x24,0xff,0xff,0x41,0x04,0xff,0xff,0x42,0x24,0xfb,0x00,0xa5,0x30,
7850x00,0x00,0xc5,0xa0,0x09,0x00,0x02,0x24,0xff,0xff,0x42,0x24,0xff,0xff,0x41,0x04,
7860xff,0xff,0x42,0x24,0xff,0xff,0x82,0x24,0x00,0x24,0x02,0x00,0x03,0x24,0x04,0x00,
7870xe7,0xff,0x81,0x04,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0xe0,0x00,
7880xe0,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0x25,0xb0,0x10,0x3c,0x0a,0x00,0x10,0x36,
7890x18,0x00,0xbf,0xaf,0x14,0x00,0xb1,0xaf,0x00,0x00,0x02,0x92,0xff,0xff,0x91,0x30,
7900x03,0x00,0x05,0x24,0xc0,0x00,0x42,0x30,0x80,0x00,0x43,0x34,0x00,0x00,0x03,0xa2,
7910x04,0x00,0x63,0x34,0x00,0x00,0x03,0xa2,0xfb,0x00,0x63,0x30,0x00,0x00,0x03,0xa2,
7920x08,0x00,0x63,0x34,0x00,0x00,0x03,0xa2,0x04,0x00,0x63,0x34,0x00,0x00,0x03,0xa2,
7930xfb,0x00,0x63,0x30,0x00,0x00,0x03,0xa2,0xd7,0x0b,0x00,0x0c,0x06,0x00,0x04,0x24,
7940x42,0x20,0x11,0x00,0xd7,0x0b,0x00,0x0c,0x06,0x00,0x05,0x24,0xfd,0x0b,0x00,0x0c,
7950x10,0x00,0x04,0x24,0x00,0x00,0x03,0x92,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,
7960xc0,0x00,0x63,0x30,0x00,0x00,0x03,0xa2,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,
7970x20,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0xff,0xff,0xb1,0x30,
7980x18,0x00,0xb2,0xaf,0x10,0x00,0xb0,0xaf,0x1c,0x00,0xbf,0xaf,0x21,0x90,0xc0,0x00,
7990x0a,0x00,0x20,0x12,0xff,0xff,0x90,0x30,0x24,0x0c,0x00,0x0c,0x21,0x20,0x00,0x02,
8000xfe,0xff,0x23,0x26,0x02,0x00,0x04,0x26,0x00,0x00,0x42,0xa6,0xff,0xff,0x71,0x30,
8010xff,0xff,0x90,0x30,0xf8,0xff,0x20,0x16,0x02,0x00,0x52,0x26,0x1c,0x00,0xbf,0x8f,
8020x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,
8030x20,0x00,0xbd,0x27,0x25,0xb0,0x03,0x3c,0x0a,0x00,0x68,0x34,0x00,0x00,0x02,0x91,
8040xff,0xff,0xa5,0x30,0xff,0x00,0x84,0x30,0x1f,0x00,0xa0,0x10,0xff,0x00,0x47,0x30,
8050x21,0x48,0x00,0x01,0x0c,0x00,0x6c,0x34,0x0b,0x00,0x6b,0x34,0xc0,0xff,0x0a,0x24,
8060x21,0x68,0x00,0x01,0x25,0x10,0xea,0x00,0xff,0x00,0x47,0x30,0x00,0x00,0x64,0xa1,
8070x00,0x00,0x27,0xa1,0x00,0x00,0x22,0x91,0x00,0x00,0x00,0x00,0xff,0x00,0x47,0x30,
8080xc0,0x00,0xe3,0x30,0x08,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x21,0x40,0xa0,0x01,
8090x00,0x00,0x02,0x91,0x00,0x00,0x00,0x00,0xff,0x00,0x47,0x30,0xc0,0x00,0xe3,0x30,
8100xfb,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x8d,0xfc,0xff,0xa3,0x24,
8110x04,0x00,0x84,0x24,0xff,0xff,0x65,0x30,0x00,0x00,0xc2,0xac,0xff,0x00,0x84,0x30,
8120xe8,0xff,0xa0,0x14,0x04,0x00,0xc6,0x24,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
8130xff,0x00,0x84,0x30,0x21,0x68,0xe0,0x00,0xff,0xff,0xa5,0x30,0xc0,0x50,0x04,0x00,
8140x00,0x60,0x0c,0x40,0x01,0x00,0x81,0x35,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
8150x00,0x00,0xc2,0x90,0x01,0x00,0xc3,0x90,0x25,0xb0,0x07,0x3c,0x00,0x14,0x02,0x00,
8160x25,0x28,0xa2,0x00,0x00,0x1e,0x03,0x00,0x01,0x80,0x08,0x3c,0x25,0x20,0xa3,0x00,
8170x40,0x02,0xe9,0x34,0x25,0x18,0x48,0x01,0x44,0x02,0xe7,0x34,0x00,0x00,0xe4,0xac,
8180x00,0x00,0x23,0xad,0x03,0x00,0xc2,0x90,0x02,0x00,0xc4,0x90,0x04,0x00,0xc3,0x90,
8190x05,0x00,0xc5,0x90,0x00,0x12,0x02,0x00,0x25,0x20,0x82,0x00,0x00,0x1c,0x03,0x00,
8200x01,0x00,0x4a,0x25,0x25,0x20,0x83,0x00,0x00,0x2e,0x05,0x00,0x25,0x40,0x48,0x01,
8210x25,0x20,0x85,0x00,0x00,0x00,0xe4,0xac,0x01,0x00,0x4a,0x25,0x00,0x00,0x28,0xad,
8220x01,0x80,0x0b,0x3c,0x21,0x40,0x00,0x00,0x21,0x10,0xa8,0x01,0x01,0x00,0x43,0x90,
8230x00,0x00,0x45,0x90,0x02,0x00,0x44,0x90,0x03,0x00,0x46,0x90,0x00,0x1a,0x03,0x00,
8240x25,0x28,0xa3,0x00,0x00,0x24,0x04,0x00,0x25,0x28,0xa4,0x00,0x00,0x36,0x06,0x00,
8250x04,0x00,0x08,0x25,0x25,0x10,0x4b,0x01,0x25,0x20,0xa6,0x00,0x10,0x00,0x03,0x2d,
8260x00,0x00,0xe4,0xac,0x01,0x00,0x4a,0x25,0x00,0x00,0x22,0xad,0xee,0xff,0x60,0x14,
8270x00,0x00,0x00,0x00,0x00,0x60,0x8c,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
8280xff,0xff,0x84,0x30,0x42,0xb0,0x08,0x3c,0x80,0x10,0x04,0x00,0x21,0x10,0x48,0x00,
8290x04,0x00,0x46,0xac,0x00,0x00,0x07,0x91,0x40,0x18,0x04,0x00,0x03,0x00,0x06,0x24,
8300xff,0x00,0xe7,0x30,0x04,0x30,0x66,0x00,0x01,0x00,0x02,0x24,0x04,0x10,0x62,0x00,
8310x25,0x30,0xc7,0x00,0xff,0xff,0xa5,0x30,0x25,0x10,0x47,0x00,0x02,0x00,0xa0,0x14,
8320xff,0x00,0xc7,0x30,0xff,0x00,0x47,0x30,0x42,0xb0,0x02,0x3c,0x00,0x00,0x47,0xa0,
8330x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x42,0xb0,0x02,0x3c,0x03,0x00,0x47,0x34,
8340x00,0x00,0xe3,0x90,0xff,0x00,0x84,0x30,0x04,0x00,0x84,0x24,0xff,0x00,0x65,0x30,
8350x01,0x00,0x02,0x24,0x04,0x30,0x82,0x00,0x07,0x18,0x85,0x00,0x25,0xb0,0x02,0x3c,
8360xe8,0x03,0x42,0x34,0x01,0x00,0x63,0x30,0x21,0x20,0xc0,0x00,0x00,0x00,0x45,0xa0,
8370x02,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0xe6,0xa0,0x08,0x00,0xe0,0x03,
8380x24,0x10,0x85,0x00,0x00,0x60,0x03,0x40,0x01,0x00,0x61,0x34,0x01,0x00,0x21,0x38,
8390x00,0x60,0x81,0x40,0x02,0x80,0x02,0x3c,0xdc,0x8c,0x42,0x24,0x04,0x00,0x45,0x8c,
8400x00,0x00,0x82,0xac,0x04,0x00,0x44,0xac,0x00,0x00,0xa4,0xac,0x04,0x00,0x85,0xac,
8410x00,0x60,0x83,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x14,0x00,0x83,0x90,
8420x01,0x00,0x02,0x24,0x08,0x00,0x86,0xac,0x18,0x00,0x85,0xac,0x00,0x00,0x84,0xac,
8430x03,0x00,0x62,0x10,0x04,0x00,0x84,0xac,0xed,0x0c,0x00,0x08,0x0c,0x00,0x80,0xac,
8440x0c,0x00,0x82,0x8c,0xed,0x0c,0x00,0x08,0x10,0x00,0x82,0xac,0x00,0x60,0x03,0x40,
8450x01,0x00,0x61,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x04,0x00,0x85,0x8c,
8460x00,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xa2,0xac,0x04,0x00,0x45,0xac,
8470x00,0x00,0x84,0xac,0x04,0x00,0x84,0xac,0x00,0x60,0x83,0x40,0x08,0x00,0xe0,0x03,
8480x00,0x00,0x00,0x00,0xd0,0xff,0xbd,0x27,0x28,0x00,0xb6,0xaf,0x24,0x00,0xb5,0xaf,
8490x20,0x00,0xb4,0xaf,0x14,0x00,0xb1,0xaf,0x2c,0x00,0xbf,0xaf,0x1c,0x00,0xb3,0xaf,
8500x18,0x00,0xb2,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x80,0x16,0x3c,0x02,0x80,0x14,0x3c,
8510x02,0x80,0x11,0x3c,0x02,0x80,0x15,0x3c,0xc4,0x7d,0x24,0x8e,0x25,0xb0,0x02,0x3c,
8520x54,0x34,0xc3,0x26,0x18,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0xdc,0x8c,0x90,0x8e,
8530x18,0x00,0x80,0x10,0xdc,0x8c,0x82,0x26,0x15,0x00,0x02,0x12,0x00,0x00,0x00,0x00,
8540x21,0x98,0x40,0x00,0x01,0x00,0x12,0x24,0x14,0x00,0x02,0x92,0x00,0x00,0x00,0x00,
8550x1d,0x00,0x52,0x10,0x00,0x00,0x00,0x00,0x09,0x00,0x40,0x14,0x00,0x00,0x00,0x00,
8560x0c,0x00,0x03,0x8e,0xc4,0x7d,0x22,0x8e,0x00,0x00,0x00,0x00,0x23,0x20,0x62,0x00,
8570x2b,0x10,0x43,0x00,0x0e,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0xae,
8580x00,0x00,0x10,0x8e,0x00,0x00,0x00,0x00,0xef,0xff,0x13,0x16,0x00,0x00,0x00,0x00,
8590xc4,0x7d,0x20,0xae,0x08,0x0c,0xa4,0x26,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,
8600x31,0x1c,0x00,0x0c,0x21,0x38,0x00,0x00,0x22,0x0d,0x00,0x08,0x00,0x00,0x00,0x00,
8610x08,0x00,0x02,0x8e,0x18,0x00,0x04,0x8e,0x09,0xf8,0x40,0x00,0x00,0x00,0x00,0x00,
8620x3c,0x0d,0x00,0x08,0x0c,0x00,0x02,0xae,0x0c,0x00,0x03,0x8e,0xc4,0x7d,0x22,0x8e,
8630x00,0x00,0x00,0x00,0x23,0x20,0x62,0x00,0x2b,0x10,0x43,0x00,0xe7,0xff,0x40,0x14,
8640x00,0x00,0x00,0x00,0x08,0x00,0x02,0x8e,0x18,0x00,0x04,0x8e,0x09,0xf8,0x40,0x00,
8650x00,0x00,0x00,0x00,0x10,0x00,0x03,0x8e,0x3c,0x0d,0x00,0x08,0x0c,0x00,0x03,0xae,
8660xff,0x00,0xa5,0x30,0x25,0xb0,0x02,0x3c,0x21,0x28,0xa2,0x00,0xff,0x00,0x84,0x30,
8670x60,0x01,0xa4,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xff,0x00,0x84,0x30,
8680x01,0x00,0x03,0x24,0x10,0x00,0x02,0x3c,0x04,0x18,0x83,0x00,0xf0,0x70,0x42,0x34,
8690x15,0x00,0x84,0x2c,0x06,0x00,0x80,0x10,0x24,0x28,0x62,0x00,0x0f,0x00,0x63,0x30,
8700x04,0x00,0xa0,0x14,0x01,0x00,0x02,0x24,0x02,0x00,0x60,0x14,0x02,0x00,0x02,0x24,
8710x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xff,0x00,0xa5,0x30,
8720x04,0x00,0xa2,0x2c,0x14,0x00,0x40,0x10,0xff,0x00,0x84,0x30,0x02,0x80,0x03,0x3c,
8730x8e,0x7d,0x62,0x90,0x00,0x00,0x00,0x00,0xef,0xff,0x42,0x24,0xff,0x00,0x42,0x30,
8740x02,0x00,0x42,0x2c,0x0e,0x00,0x40,0x10,0x02,0x00,0x03,0x24,0x24,0x00,0x83,0x10,
8750x0f,0x10,0x02,0x3c,0x03,0x00,0x82,0x28,0x14,0x00,0x40,0x10,0x03,0x00,0x02,0x24,
8760x01,0x00,0x02,0x24,0x2f,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0xff,0x1f,0x02,0x3c,
8770x08,0x00,0xe0,0x03,0xff,0xff,0x42,0x34,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
8780x35,0x00,0x83,0x10,0x0f,0x1f,0x02,0x3c,0x03,0x00,0x82,0x28,0x16,0x00,0x40,0x10,
8790x03,0x00,0x02,0x24,0x01,0x00,0x02,0x24,0xf4,0xff,0x82,0x14,0x00,0x00,0x00,0x00,
8800x0f,0x1f,0x02,0x3c,0x08,0x00,0xe0,0x03,0x00,0x80,0x42,0x34,0xf0,0xff,0x82,0x14,
8810xff,0x1f,0x02,0x3c,0x01,0x00,0x02,0x24,0x29,0x00,0xa2,0x10,0x0f,0x10,0x02,0x3c,
8820x02,0x00,0xa2,0x28,0x1f,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x28,0x00,0xa3,0x10,
8830x00,0x00,0x00,0x00,0xe5,0xff,0xa4,0x14,0x00,0x00,0x00,0x00,0x0f,0x10,0x02,0x3c,
8840x08,0x00,0xe0,0x03,0x00,0xf0,0x42,0x34,0xe1,0xff,0x82,0x14,0xff,0x1f,0x02,0x3c,
8850x01,0x00,0x02,0x24,0x1c,0x00,0xa2,0x10,0x0f,0x00,0x02,0x3c,0x02,0x00,0xa2,0x28,
8860x0b,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x1c,0x00,0xa3,0x10,0x00,0x00,0x00,0x00,
8870xd6,0xff,0xa4,0x14,0x00,0x00,0x00,0x00,0x0f,0x00,0x02,0x3c,0x08,0x00,0xe0,0x03,
8880x00,0xf0,0x42,0x34,0x0f,0x10,0x02,0x3c,0x08,0x00,0xe0,0x03,0x00,0x80,0x42,0x34,
8890xce,0xff,0xa0,0x14,0x00,0x00,0x00,0x00,0x0f,0x00,0x02,0x3c,0x08,0x00,0xe0,0x03,
8900x15,0xf0,0x42,0x34,0xc9,0xff,0xa0,0x14,0x00,0x00,0x00,0x00,0x0f,0x10,0x02,0x3c,
8910x08,0x00,0xe0,0x03,0x15,0xf0,0x42,0x34,0x08,0x00,0xe0,0x03,0x00,0xf0,0x42,0x34,
8920x08,0x00,0xe0,0x03,0x10,0xf0,0x42,0x34,0x08,0x00,0xe0,0x03,0x10,0xf0,0x42,0x34,
8930x0f,0x10,0x02,0x3c,0x08,0x00,0xe0,0x03,0x05,0xf0,0x42,0x34,0x0f,0x00,0x02,0x3c,
8940x08,0x00,0xe0,0x03,0x05,0xf0,0x42,0x34,0xc0,0x40,0x04,0x00,0x21,0x18,0x04,0x01,
8950x80,0x18,0x03,0x00,0x21,0x18,0x64,0x00,0x02,0x80,0x02,0x3c,0x80,0x18,0x03,0x00,
8960x68,0x15,0x42,0x24,0x21,0x18,0x62,0x00,0x74,0x51,0x66,0x8c,0x21,0x38,0x60,0x00,
8970x7a,0x51,0x60,0xa0,0x7b,0x51,0x60,0xa0,0x1c,0x00,0x05,0x24,0xdf,0x0d,0x00,0x08,
8980x01,0x00,0x03,0x24,0x08,0x00,0xa0,0x04,0x21,0x10,0x04,0x01,0x04,0x10,0xa3,0x00,
8990x24,0x10,0xc2,0x00,0xfb,0xff,0x40,0x10,0xff,0xff,0xa5,0x24,0x01,0x00,0xa5,0x24,
9000x7a,0x51,0xe5,0xa0,0x21,0x10,0x04,0x01,0x80,0x10,0x02,0x00,0x21,0x10,0x44,0x00,
9010x02,0x80,0x03,0x3c,0x80,0x10,0x02,0x00,0x68,0x15,0x63,0x24,0x21,0x18,0x43,0x00,
9020x74,0x51,0x66,0x8c,0x21,0x28,0x00,0x00,0xf3,0x0d,0x00,0x08,0x01,0x00,0x07,0x24,
9030x1d,0x00,0xa2,0x28,0x08,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x04,0x10,0xa7,0x00,
9040x24,0x10,0xc2,0x00,0xfa,0xff,0x40,0x10,0x01,0x00,0xa5,0x24,0xff,0xff,0xa5,0x24,
9050x08,0x00,0xe0,0x03,0x7b,0x51,0x65,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
9060xc8,0xff,0xbd,0x27,0x28,0x00,0xb6,0xaf,0x02,0x80,0x16,0x3c,0x30,0x00,0xbe,0xaf,
9070x2c,0x00,0xb7,0xaf,0x24,0x00,0xb5,0xaf,0x20,0x00,0xb4,0xaf,0x18,0x00,0xb2,0xaf,
9080x14,0x00,0xb1,0xaf,0x01,0x00,0x15,0x24,0x21,0x88,0x00,0x00,0x68,0x15,0xde,0x26,
9090x21,0xa0,0x00,0x00,0x21,0x90,0x00,0x00,0x25,0xb0,0x17,0x3c,0x34,0x00,0xbf,0xaf,
9100x1c,0x00,0xb3,0xaf,0x14,0x0e,0x00,0x08,0x10,0x00,0xb0,0xaf,0x01,0x00,0x31,0x26,
9110x20,0x00,0x22,0x2e,0x94,0x00,0x52,0x26,0x2e,0x00,0x40,0x10,0x94,0x00,0x94,0x26,
9120x68,0x15,0xc2,0x26,0x21,0x30,0x42,0x02,0x78,0x51,0xc5,0x8c,0x00,0x00,0x00,0x00,
9130x02,0x13,0x05,0x00,0x01,0x00,0x42,0x30,0xf4,0xff,0x55,0x14,0x42,0x1a,0x05,0x00,
9140x68,0x51,0xc2,0x8c,0x07,0x00,0x64,0x30,0x02,0x11,0x02,0x00,0x7f,0x00,0x43,0x30,
9150x2d,0x00,0x95,0x10,0x07,0x00,0xb3,0x30,0x02,0x00,0x82,0x28,0x3a,0x00,0x40,0x14,
9160x02,0x00,0x02,0x24,0x30,0x00,0x82,0x10,0x03,0x00,0x02,0x24,0x3c,0x00,0x82,0x10,
9170x1a,0x00,0x62,0x2c,0x21,0x80,0x9e,0x02,0x78,0x51,0x02,0x8e,0x04,0x00,0x63,0x2e,
9180x42,0x12,0x02,0x00,0x0a,0x00,0x60,0x10,0x07,0x00,0x44,0x30,0x73,0x0d,0x00,0x0c,
9190x21,0x28,0x60,0x02,0x80,0x20,0x13,0x00,0x70,0x51,0x02,0xae,0x21,0x20,0x97,0x00,
9200x84,0x01,0x83,0x8c,0x00,0x00,0x00,0x00,0x24,0x18,0x62,0x00,0x74,0x51,0x03,0xae,
9210xce,0x0d,0x00,0x0c,0x21,0x20,0x20,0x02,0x21,0x10,0x37,0x02,0x01,0x00,0x31,0x26,
9220x60,0x01,0x43,0x90,0x20,0x00,0x22,0x2e,0x94,0x00,0x52,0x26,0xd4,0xff,0x40,0x14,
9230x94,0x00,0x94,0x26,0x34,0x00,0xbf,0x8f,0x30,0x00,0xbe,0x8f,0x2c,0x00,0xb7,0x8f,
9240x28,0x00,0xb6,0x8f,0x24,0x00,0xb5,0x8f,0x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,
9250x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,
9260x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0x32,0x00,0x62,0x2c,0xda,0xff,0x40,0x10,
9270x21,0x80,0x9e,0x02,0xff,0xf1,0x03,0x24,0x24,0x10,0xa3,0x00,0x00,0x04,0x42,0x34,
9280x29,0x0e,0x00,0x08,0x78,0x51,0xc2,0xac,0x38,0x00,0x62,0x2c,0x12,0x00,0x40,0x14,
9290x14,0x00,0x62,0x2c,0xff,0xf1,0x03,0x24,0x24,0x10,0xa3,0x00,0x00,0x02,0x42,0x34,
9300x29,0x0e,0x00,0x08,0x78,0x51,0xc2,0xac,0xcb,0xff,0x80,0x14,0x21,0x80,0x9e,0x02,
9310xff,0xf1,0x03,0x24,0x24,0x10,0xa3,0x00,0x2a,0x0e,0x00,0x08,0x78,0x51,0xc2,0xac,
9320xc5,0xff,0x40,0x14,0x21,0x80,0x9e,0x02,0xff,0xf1,0x03,0x24,0x24,0x10,0xa3,0x00,
9330x54,0x0e,0x00,0x08,0x00,0x04,0x42,0x34,0xbf,0xff,0x40,0x10,0x21,0x80,0x9e,0x02,
9340xff,0xf1,0x03,0x24,0x24,0x10,0xa3,0x00,0x00,0x06,0x42,0x34,0x2a,0x0e,0x00,0x08,
9350x78,0x51,0xc2,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xd8,0xff,0xbd,0x27,
9360x10,0x00,0xb0,0xaf,0xc0,0x80,0x04,0x00,0x21,0x80,0x04,0x02,0x80,0x80,0x10,0x00,
9370x21,0x80,0x04,0x02,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0x80,0x80,0x10,0x00,
9380x20,0x00,0xbf,0xaf,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,0x21,0x80,0x02,0x02,
9390x14,0x00,0xb1,0xaf,0x78,0x51,0x03,0x8e,0x25,0xb0,0x02,0x3c,0x80,0x01,0x53,0x34,
9400x07,0x00,0x63,0x30,0x80,0x18,0x03,0x00,0x21,0x18,0x62,0x00,0x00,0x00,0x71,0x92,
9410x70,0x51,0x05,0x8e,0x84,0x01,0x62,0x8c,0x21,0x90,0x80,0x00,0xff,0x00,0x31,0x32,
9420x24,0x10,0x45,0x00,0xce,0x0d,0x00,0x0c,0x74,0x51,0x02,0xae,0x7a,0x51,0x04,0x92,
9430x5c,0x0d,0x00,0x0c,0xff,0x00,0x45,0x32,0x7a,0x51,0x04,0x92,0x63,0x0d,0x00,0x0c,
9440x00,0x00,0x00,0x00,0x01,0x00,0x42,0x38,0x04,0x00,0x03,0x24,0x0a,0x88,0x62,0x00,
9450x00,0x00,0x71,0xa2,0x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,
9460x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,
9470xff,0xff,0x84,0x30,0x00,0x02,0x82,0x30,0x07,0x00,0x03,0x24,0x0d,0x00,0x40,0x14,
9480x0b,0x00,0x84,0x30,0x0c,0x00,0x82,0x2c,0x0a,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
9490x02,0x80,0x03,0x3c,0x80,0x10,0x04,0x00,0xf0,0x91,0x63,0x24,0x21,0x10,0x43,0x00,
9500x00,0x00,0x44,0x8c,0x00,0x00,0x00,0x00,0x08,0x00,0x80,0x00,0x00,0x00,0x00,0x00,
9510x07,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,0x06,0x00,0x03,0x24,
9520x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,0x05,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,
9530x21,0x10,0x60,0x00,0x04,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
9540x03,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,0x02,0x00,0x03,0x24,
9550x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,0x01,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,
9560x21,0x10,0x60,0x00,0x21,0x18,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
9570xa0,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x58,0x00,0xbe,0xaf,0x54,0x00,0xb7,0xaf,
9580x50,0x00,0xb6,0xaf,0x4c,0x00,0xb5,0xaf,0x48,0x00,0xb4,0xaf,0x40,0x00,0xb2,0xaf,
9590x3c,0x00,0xb1,0xaf,0x5c,0x00,0xbf,0xaf,0x44,0x00,0xb3,0xaf,0x38,0x00,0xb0,0xaf,
9600x20,0x92,0x42,0x24,0x00,0x00,0x53,0x8c,0x08,0x00,0x03,0x24,0x02,0x80,0x0b,0x3c,
9610x21,0x90,0x00,0x00,0x21,0xa0,0x00,0x00,0x21,0xb8,0x00,0x00,0x21,0xf0,0x00,0x00,
9620x21,0xa8,0x00,0x00,0x21,0xb0,0x00,0x00,0x21,0x88,0x60,0x02,0x10,0x00,0xa3,0xaf,
9630x14,0x00,0xa0,0xaf,0x18,0x00,0xa0,0xaf,0x1c,0x00,0xa0,0xaf,0x20,0x00,0xa0,0xaf,
9640x24,0x00,0xa0,0xaf,0x28,0x00,0xa0,0xaf,0x7a,0x0f,0x00,0x08,0x2c,0x00,0xa0,0xaf,
9650x44,0x51,0x22,0xae,0x60,0x51,0x24,0x8e,0x5c,0x51,0x27,0x8e,0x48,0x51,0x28,0x8e,
9660x4c,0x51,0x25,0x8e,0x54,0x51,0x26,0x8e,0x58,0x51,0x23,0x8e,0x21,0x38,0xe4,0x00,
9670x02,0x80,0x04,0x3c,0x68,0x15,0x84,0x24,0x21,0x10,0x04,0x02,0x21,0x40,0x05,0x01,
9680x21,0x30,0xc3,0x00,0xca,0x44,0x42,0x90,0x44,0x51,0x2a,0x8e,0x0c,0x00,0xe0,0x10,
9690x21,0x48,0x00,0x00,0x2b,0x48,0x47,0x00,0x0b,0x00,0x20,0x15,0x02,0x80,0x02,0x3c,
9700x07,0x00,0x02,0x2e,0x59,0x01,0x40,0x14,0xc0,0x10,0x07,0x00,0x0c,0x00,0x02,0x24,
9710x55,0x01,0x02,0x12,0x0d,0x00,0x02,0x24,0x54,0x01,0x02,0x12,0xc0,0x10,0x07,0x00,
9720x92,0x00,0x20,0x11,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0x80,0x18,0x10,0x00,
9730x21,0x18,0x62,0x00,0x21,0x20,0x30,0x02,0xb6,0x51,0x85,0x90,0xec,0x44,0x62,0x8c,
9740x00,0x00,0x00,0x00,0x04,0x10,0xa2,0x00,0x2b,0x10,0x4a,0x00,0x87,0x00,0x40,0x10,
9750x00,0x00,0x00,0x00,0xd4,0x51,0x22,0x8e,0x01,0x00,0x07,0x24,0x04,0x18,0x07,0x02,
9760x24,0x10,0x43,0x00,0xf0,0x00,0x40,0x10,0x1c,0x00,0x02,0x2e,0x21,0x28,0x30,0x02,
9770x7c,0x51,0xa6,0x90,0xb6,0x51,0xa2,0x90,0x0a,0x00,0x04,0x24,0xff,0x00,0xc3,0x30,
9780x04,0x20,0x44,0x00,0x2a,0x18,0x64,0x00,0xe7,0x00,0x60,0x10,0x1c,0x00,0x02,0x2e,
9790x01,0x00,0xc2,0x24,0xff,0x00,0x43,0x30,0x56,0x01,0x64,0x10,0x7c,0x51,0xa2,0xa0,
9800x68,0x15,0x65,0x25,0x80,0x10,0x10,0x00,0x21,0x10,0x45,0x00,0x60,0x45,0x44,0x8c,
9810xec,0x44,0x43,0x8c,0x21,0x30,0xc5,0x02,0x40,0x10,0x04,0x00,0x21,0x10,0x44,0x00,
9820x21,0x18,0x62,0x00,0x82,0x50,0x03,0x00,0x44,0x51,0xca,0xac,0x8c,0x65,0xa3,0x8c,
9830xff,0xff,0x02,0x34,0x07,0x00,0x62,0x10,0x21,0x20,0x00,0x02,0x21,0x20,0x00,0x02,
9840xff,0x00,0x45,0x32,0x5c,0x0d,0x00,0x0c,0x30,0x00,0xab,0xaf,0x30,0x00,0xab,0x8f,
9850x21,0x20,0x00,0x02,0x63,0x0d,0x00,0x0c,0x30,0x00,0xab,0xaf,0x10,0x00,0xa4,0x8f,
9860x01,0x00,0x42,0x38,0x04,0x00,0x03,0x24,0x0a,0x20,0x62,0x00,0x10,0x00,0xa4,0xaf,
9870x30,0x00,0xab,0x8f,0x11,0x00,0x40,0x16,0x68,0x15,0x62,0x25,0x58,0x51,0x47,0x8c,
9880x54,0x51,0x43,0x8c,0x4c,0x51,0x44,0x94,0x48,0x51,0x45,0x94,0x50,0x51,0x46,0x94,
9890x21,0x18,0x67,0x00,0x00,0x24,0x04,0x00,0x25,0xb0,0x02,0x3c,0x00,0x1c,0x03,0x00,
9900x21,0x28,0xa4,0x00,0x21,0x30,0xc3,0x00,0x6c,0x0c,0x44,0x34,0x68,0x0c,0x42,0x34,
9910x00,0x00,0x45,0xac,0x00,0x00,0x86,0xac,0x68,0x15,0x62,0x25,0x21,0x10,0x82,0x02,
9920x58,0x51,0x40,0xac,0x5c,0x51,0x40,0xac,0x60,0x51,0x40,0xac,0x48,0x51,0x40,0xac,
9930x4c,0x51,0x40,0xac,0x50,0x51,0x40,0xac,0x54,0x51,0x40,0xac,0x2c,0x00,0xa2,0x8f,
9940x28,0x00,0xa4,0x8f,0x01,0x00,0x52,0x26,0x94,0x00,0x42,0x24,0x2c,0x00,0xa2,0xaf,
9950x24,0x00,0xa2,0x8f,0x94,0x00,0x84,0x24,0x28,0x00,0xa4,0xaf,0x94,0x00,0x42,0x24,
9960x20,0x00,0xa4,0x8f,0x24,0x00,0xa2,0xaf,0x1c,0x00,0xa2,0x8f,0x94,0x00,0x84,0x24,
9970x20,0x00,0xa4,0xaf,0x94,0x00,0x42,0x24,0x18,0x00,0xa4,0x8f,0x1c,0x00,0xa2,0xaf,
9980x14,0x00,0xa2,0x8f,0x94,0x00,0x84,0x24,0x20,0x00,0x43,0x2a,0x94,0x00,0x42,0x24,
9990x94,0x00,0x31,0x26,0x94,0x00,0xd6,0x26,0x94,0x00,0xb5,0x26,0x18,0x00,0xa4,0xaf,
10000x14,0x00,0xa2,0xaf,0x94,0x00,0xde,0x27,0x94,0x00,0x73,0x26,0x94,0x00,0xf7,0x26,
10010xe5,0x00,0x60,0x10,0x94,0x00,0x94,0x26,0x78,0x51,0x22,0x8e,0x00,0x00,0x00,0x00,
10020x02,0x13,0x02,0x00,0x01,0x00,0x42,0x30,0xd3,0xff,0x40,0x10,0x25,0xb0,0x02,0x3c,
10030x21,0x10,0x42,0x02,0x60,0x01,0x44,0x90,0x60,0x51,0x23,0x8e,0x5c,0x51,0x26,0x8e,
10040xff,0x00,0x90,0x30,0x02,0x80,0x04,0x3c,0x68,0x15,0x84,0x24,0x21,0x10,0x04,0x02,
10050x73,0x44,0x44,0x90,0x56,0x44,0x45,0x90,0x44,0x51,0x27,0x8e,0x18,0x00,0x64,0x00,
10060x12,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0xc5,0x00,
10070x12,0x30,0x00,0x00,0x21,0x30,0xc3,0x00,0x2b,0x10,0xe6,0x00,0x54,0xff,0x40,0x10,
10080x23,0x10,0xe6,0x00,0xe9,0x0e,0x00,0x08,0x44,0x51,0x20,0xae,0x62,0x00,0xe0,0x10,
10090x00,0x00,0x00,0x00,0x63,0x00,0x20,0x15,0x68,0x15,0x62,0x25,0x40,0x10,0x07,0x00,
10100x21,0x10,0x47,0x00,0x82,0x10,0x02,0x00,0x2b,0x10,0x46,0x00,0x99,0xff,0x40,0x10,
10110x21,0x20,0x00,0x02,0x68,0x15,0x68,0x25,0x21,0x20,0xa8,0x02,0x21,0x30,0x90,0x00,
10120xd4,0x51,0x83,0x8c,0x01,0x00,0x05,0x24,0x04,0x10,0x05,0x02,0x99,0x51,0xc7,0x90,
10130x27,0x10,0x02,0x00,0x24,0x18,0x62,0x00,0xd4,0x51,0x83,0xac,0x09,0x00,0xe5,0x10,
10140x7c,0x51,0xc0,0xa0,0x18,0x00,0xa2,0x8f,0x21,0x38,0x00,0x00,0x21,0x20,0x48,0x00,
10150x21,0x18,0x87,0x00,0x01,0x00,0xe7,0x24,0x1d,0x00,0xe2,0x28,0xfc,0xff,0x40,0x14,
10160xb6,0x51,0x60,0xa0,0x14,0x00,0xa4,0x8f,0x68,0x15,0x63,0x25,0x21,0x50,0x60,0x00,
10170x21,0x10,0x83,0x00,0x21,0x10,0x50,0x00,0x99,0x51,0x40,0xa0,0x02,0x80,0x03,0x3c,
10180x02,0x80,0x02,0x3c,0x4c,0x91,0x49,0x24,0xd8,0x90,0x68,0x24,0x21,0x38,0x00,0x00,
10190x80,0x18,0x07,0x00,0x21,0x10,0x69,0x00,0x21,0x20,0x68,0x00,0x00,0x00,0x46,0x8c,
10200x00,0x00,0x85,0x8c,0x01,0x00,0xe7,0x24,0x21,0x18,0x6a,0x00,0x1d,0x00,0xe2,0x28,
10210xec,0x44,0x65,0xac,0xf6,0xff,0x40,0x14,0x60,0x45,0x66,0xac,0x14,0x00,0x00,0x12,
10220x68,0x15,0x63,0x25,0x7b,0x51,0x62,0x92,0xff,0xff,0x07,0x26,0x2a,0x10,0xe2,0x00,
10230x0e,0x00,0x40,0x14,0x02,0x80,0x0b,0x3c,0x68,0x15,0x62,0x25,0x21,0x10,0xc2,0x03,
10240x7b,0x51,0x45,0x90,0x74,0x51,0x44,0x8c,0x01,0x00,0x06,0x24,0x04,0x18,0xe6,0x00,
10250x24,0x10,0x83,0x00,0xb3,0x00,0x43,0x10,0x00,0x00,0x00,0x00,0xff,0xff,0xe7,0x24,
10260x2a,0x10,0xe5,0x00,0xfa,0xff,0x40,0x10,0x04,0x18,0xe6,0x00,0x68,0x15,0x63,0x25,
10270x80,0x10,0x10,0x00,0x21,0x10,0x43,0x00,0x60,0x45,0x45,0x8c,0xec,0x44,0x44,0x8c,
10280x02,0x80,0x03,0x3c,0x40,0x10,0x05,0x00,0x8e,0x7d,0x66,0x90,0x21,0x10,0x45,0x00,
10290x21,0x20,0x82,0x00,0x22,0x00,0x02,0x24,0x98,0x00,0xc2,0x10,0x82,0x50,0x04,0x00,
10300xd4,0x51,0x63,0x8e,0x01,0x00,0x02,0x24,0x04,0x10,0x02,0x02,0x25,0x18,0x62,0x00,
10310xd4,0x51,0x63,0xae,0x68,0x15,0x63,0x25,0x21,0x10,0xe3,0x02,0x44,0x51,0x4a,0xac,
10320x8c,0x65,0x64,0x8c,0xff,0xff,0x02,0x34,0x3c,0xff,0x82,0x14,0x21,0x20,0x00,0x02,
10330x39,0x0f,0x00,0x08,0x00,0x00,0x00,0x00,0x3e,0xff,0x20,0x11,0x21,0x20,0x00,0x02,
10340x68,0x15,0x62,0x25,0x80,0x18,0x10,0x00,0x21,0x18,0x62,0x00,0x60,0x45,0x64,0x8c,
10350x00,0x00,0x00,0x00,0x2b,0x20,0x44,0x01,0x36,0xff,0x80,0x10,0x21,0x20,0x00,0x02,
10360xa2,0x0f,0x00,0x08,0x68,0x15,0x68,0x25,0x1e,0xff,0x40,0x10,0x68,0x15,0x65,0x25,
10370x21,0x20,0x30,0x02,0x99,0x51,0x83,0x90,0x01,0x00,0x02,0x24,0x63,0x00,0x62,0x10,
10380x02,0x80,0x02,0x3c,0x2c,0x00,0xa3,0x8f,0x68,0x15,0x42,0x24,0x21,0x38,0x00,0x00,
10390x21,0x20,0x62,0x00,0x21,0x18,0x87,0x00,0x01,0x00,0xe7,0x24,0x1d,0x00,0xe2,0x28,
10400xfc,0xff,0x40,0x14,0xb6,0x51,0x60,0xa0,0x28,0x00,0xa3,0x8f,0x02,0x80,0x0b,0x3c,
10410x68,0x15,0x65,0x25,0x21,0x30,0x65,0x00,0xd4,0x51,0xc2,0x8c,0x01,0x00,0x03,0x24,
10420x04,0x18,0x03,0x02,0x27,0x18,0x03,0x00,0x21,0x20,0xd0,0x00,0x24,0x10,0x43,0x00,
10430x99,0x51,0x80,0xa0,0xd4,0x51,0xc2,0xac,0x12,0x00,0x00,0x16,0x7c,0x51,0x80,0xa0,
10440x7a,0x51,0xc2,0x90,0x00,0x00,0x00,0x00,0x0e,0x00,0x40,0x10,0x01,0x00,0x07,0x24,
10450x24,0x00,0xa4,0x8f,0x01,0x00,0x06,0x24,0x21,0x10,0x85,0x00,0x7a,0x51,0x44,0x90,
10460x74,0x51,0x45,0x8c,0x04,0x18,0xe6,0x00,0x24,0x10,0xa3,0x00,0x5b,0x00,0x43,0x10,
10470x00,0x00,0x00,0x00,0x01,0x00,0xe7,0x24,0x2a,0x10,0x87,0x00,0xfa,0xff,0x40,0x10,
10480x04,0x18,0xe6,0x00,0x20,0x00,0xa2,0x8f,0x02,0x80,0x0b,0x3c,0x68,0x15,0x64,0x25,
10490x21,0x18,0x44,0x00,0x7a,0x51,0x62,0x90,0x01,0x00,0x07,0x26,0x2a,0x10,0x47,0x00,
10500x0e,0x00,0x40,0x14,0x01,0x00,0x06,0x24,0x1c,0x00,0xa3,0x8f,0x00,0x00,0x00,0x00,
10510x21,0x10,0x64,0x00,0x7a,0x51,0x45,0x90,0x74,0x51,0x44,0x8c,0x04,0x18,0xe6,0x00,
10520x24,0x10,0x83,0x00,0x42,0x00,0x43,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0xe7,0x24,
10530x2a,0x10,0xa7,0x00,0xfa,0xff,0x40,0x10,0x04,0x18,0xe6,0x00,0x02,0x80,0x02,0x3c,
10540x8e,0x7d,0x44,0x90,0x22,0x00,0x03,0x24,0xd6,0xfe,0x83,0x14,0x68,0x15,0x65,0x25,
10550xee,0xff,0x02,0x26,0xff,0x00,0x42,0x30,0x02,0x00,0x42,0x2c,0x18,0x00,0x03,0x24,
10560x25,0x0f,0x00,0x08,0x0b,0x80,0x62,0x00,0xc0,0x10,0x07,0x00,0x23,0x10,0x47,0x00,
10570xc2,0x10,0x02,0x00,0x2b,0x10,0x48,0x00,0xb6,0xfe,0x40,0x14,0x00,0x00,0x00,0x00,
10580x04,0x0f,0x00,0x08,0x00,0x00,0x00,0x00,0x10,0x00,0xa3,0x8f,0x5c,0x00,0xbf,0x8f,
10590x58,0x00,0xbe,0x8f,0x54,0x00,0xb7,0x8f,0x50,0x00,0xb6,0x8f,0x4c,0x00,0xb5,0x8f,
10600x48,0x00,0xb4,0x8f,0x44,0x00,0xb3,0x8f,0x40,0x00,0xb2,0x8f,0x3c,0x00,0xb1,0x8f,
10610x38,0x00,0xb0,0x8f,0x25,0xb0,0x02,0x3c,0x80,0x01,0x42,0x34,0x60,0x00,0xbd,0x27,
10620x00,0x00,0x43,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x18,0x00,0x02,0x2e,
10630x0a,0x00,0x40,0x14,0x05,0x00,0x02,0x2e,0xb6,0x51,0x83,0x90,0x00,0x00,0x00,0x00,
10640x05,0x00,0x62,0x2c,0xa0,0xff,0x40,0x10,0x01,0x00,0x62,0x24,0x16,0x10,0x00,0x08,
10650xb6,0x51,0x82,0xa0,0x24,0x0f,0x00,0x08,0x99,0x51,0xa7,0xa0,0x04,0x00,0x40,0x10,
10660x00,0x00,0x00,0x00,0xb6,0x51,0x83,0x90,0x75,0x10,0x00,0x08,0x03,0x00,0x62,0x2c,
10670xb6,0x51,0x83,0x90,0x75,0x10,0x00,0x08,0x04,0x00,0x62,0x2c,0x13,0x00,0x02,0x24,
10680x67,0xff,0x02,0x16,0x68,0x15,0x63,0x25,0xf3,0x0f,0x00,0x08,0x21,0x10,0xe3,0x02,
10690xff,0x00,0xf0,0x30,0x4c,0x10,0x00,0x08,0x02,0x80,0x02,0x3c,0x35,0x10,0x00,0x08,
10700xff,0x00,0xf0,0x30,0xdf,0x0f,0x00,0x08,0xff,0x00,0xf0,0x30,0xd8,0xff,0xbd,0x27,
10710x02,0x80,0x02,0x3c,0x14,0x00,0xb1,0xaf,0x24,0x00,0xbf,0xaf,0x20,0x00,0xb4,0xaf,
10720x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,0x10,0x00,0xb0,0xaf,0x68,0x15,0x45,0x24,
10730x05,0x65,0xa4,0x90,0x00,0x65,0xa3,0x8c,0xfc,0x64,0xa2,0x8c,0x21,0x88,0x64,0x00,
10740x2b,0x10,0x22,0x02,0x60,0x00,0x40,0x10,0x21,0x80,0xa0,0x00,0x02,0x80,0x14,0x3c,
10750x21,0x98,0xa0,0x00,0xa8,0x10,0x00,0x08,0x21,0x90,0xa0,0x00,0xfc,0x64,0x42,0x8e,
10760x10,0x00,0x31,0x26,0x2b,0x10,0x22,0x02,0x57,0x00,0x40,0x10,0x21,0x80,0x40,0x02,
10770x05,0x65,0x02,0x92,0xff,0xff,0x23,0x32,0x02,0x80,0x05,0x3c,0x10,0x00,0x42,0x24,
10780x25,0x28,0x65,0x00,0x2c,0x79,0x84,0x26,0x10,0x00,0x06,0x24,0x9f,0x45,0x00,0x0c,
10790x05,0x65,0x02,0xa2,0xc8,0x63,0x06,0x8e,0x00,0x00,0x00,0x00,0x42,0x24,0x06,0x00,
10800x1f,0x00,0x84,0x30,0xc0,0x10,0x04,0x00,0x21,0x10,0x44,0x00,0x80,0x10,0x02,0x00,
10810x21,0x10,0x44,0x00,0x80,0x10,0x02,0x00,0x21,0x38,0x50,0x00,0x78,0x51,0xe3,0x8c,
10820x00,0x00,0x00,0x00,0x02,0x1b,0x03,0x00,0x01,0x00,0x63,0x30,0xe3,0xff,0x60,0x10,
10830x25,0xb0,0x02,0x3c,0xc4,0x63,0x05,0x8e,0x21,0x10,0x82,0x00,0x60,0x01,0x44,0x90,
10840x82,0x1d,0x05,0x00,0x3f,0x00,0x63,0x30,0x04,0x00,0x0a,0x24,0x05,0x00,0x62,0x28,
10850x21,0x40,0x40,0x01,0x0b,0x40,0x62,0x00,0x07,0x00,0xa0,0x04,0xff,0x00,0x89,0x30,
10860x64,0x51,0xe2,0x8c,0x04,0x00,0x08,0x24,0x01,0x00,0x42,0x24,0x64,0x51,0xe2,0xac,
10870xc8,0x63,0x66,0x8e,0x00,0x00,0x00,0x00,0x02,0x13,0x06,0x00,0x1f,0x00,0x42,0x30,
10880x08,0x00,0x42,0x28,0xcd,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0xc4,0x63,0x62,0x8e,
10890x00,0x00,0x00,0x00,0x3f,0x00,0x42,0x30,0xc8,0xff,0x49,0x14,0x00,0x00,0x00,0x00,
10900x29,0x00,0x00,0x11,0x01,0x00,0x02,0x24,0x2e,0x00,0x02,0x11,0x02,0x00,0x02,0x24,
10910x33,0x00,0x02,0x11,0x03,0x00,0x02,0x24,0x38,0x00,0x02,0x11,0x00,0x00,0x00,0x00,
10920x3b,0x00,0x0a,0x11,0x00,0x00,0x00,0x00,0x68,0x51,0xe2,0x8c,0x21,0x18,0x33,0x01,
10930x90,0x44,0x64,0x90,0x02,0x11,0x02,0x00,0x2b,0x10,0x44,0x00,0x3e,0x00,0x40,0x14,
10940x00,0x00,0x00,0x00,0x5c,0x51,0xe3,0x8c,0x80,0x10,0x09,0x00,0x21,0x10,0x49,0x00,
10950x01,0x00,0x63,0x24,0x21,0x10,0x53,0x00,0x5c,0x51,0xe3,0xac,0x21,0x10,0x48,0x00,
10960x34,0x43,0x44,0x90,0x44,0x51,0xe3,0x8c,0x00,0x00,0x00,0x00,0x21,0x18,0x64,0x00,
10970x44,0x51,0xe3,0xac,0xfc,0x64,0x42,0x8e,0x10,0x00,0x31,0x26,0x2b,0x10,0x22,0x02,
10980xab,0xff,0x40,0x14,0x21,0x80,0x40,0x02,0x24,0x00,0xbf,0x8f,0x20,0x00,0xb4,0x8f,
10990x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,
11000x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,0x48,0x51,0xe2,0x8c,0x00,0x00,0x00,0x00,
11010x01,0x00,0x42,0x24,0x48,0x51,0xe2,0xac,0x01,0x00,0x02,0x24,0xd4,0xff,0x02,0x15,
11020x02,0x00,0x02,0x24,0x4c,0x51,0xe2,0x8c,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,
11030x4c,0x51,0xe2,0xac,0x02,0x00,0x02,0x24,0xcf,0xff,0x02,0x15,0x03,0x00,0x02,0x24,
11040x50,0x51,0xe2,0x8c,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0x50,0x51,0xe2,0xac,
11050x03,0x00,0x02,0x24,0xca,0xff,0x02,0x15,0x00,0x00,0x00,0x00,0x54,0x51,0xe2,0x8c,
11060x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0xc7,0xff,0x0a,0x15,0x54,0x51,0xe2,0xac,
11070x58,0x51,0xe2,0x8c,0x21,0x18,0x33,0x01,0x01,0x00,0x42,0x24,0x58,0x51,0xe2,0xac,
11080x68,0x51,0xe2,0x8c,0x90,0x44,0x64,0x90,0x02,0x11,0x02,0x00,0x2b,0x10,0x44,0x00,
11090xc4,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0x60,0x51,0xe3,0x8c,0x80,0x10,0x09,0x00,
11100x21,0x10,0x49,0x00,0x01,0x00,0x63,0x24,0x21,0x10,0x53,0x00,0x60,0x51,0xe3,0xac,
11110x21,0x10,0x48,0x00,0xc5,0x43,0x44,0x90,0x44,0x51,0xe3,0x8c,0x00,0x00,0x00,0x00,
11120x21,0x18,0x64,0x00,0xf9,0x10,0x00,0x08,0x44,0x51,0xe3,0xac,0x25,0xb0,0x02,0x3c,
11130x25,0xb0,0x05,0x3c,0x02,0x80,0x03,0x3c,0x58,0x00,0x4a,0x34,0x5c,0x00,0x4b,0x34,
11140x4c,0x00,0xa2,0x34,0x00,0x00,0x44,0x90,0x68,0x15,0x66,0x24,0xed,0x4a,0xc2,0x90,
11150x29,0xb0,0x07,0x3c,0x03,0x00,0x84,0x30,0x21,0x18,0xc0,0x00,0x0f,0x00,0x44,0x10,
11160x04,0x00,0xe8,0x34,0x07,0x00,0x80,0x14,0x58,0x0c,0xa9,0x34,0xe6,0x42,0xc2,0x90,
11170x1c,0x00,0x06,0x24,0x03,0x00,0x40,0x14,0x50,0x0c,0xa5,0x34,0x00,0x00,0xa6,0xa0,
11180x00,0x00,0x26,0xa1,0x00,0x00,0x42,0x8d,0xed,0x4a,0x64,0xa0,0x00,0x00,0xe2,0xac,
11190x00,0x00,0x62,0x8d,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0xad,0x08,0x00,0xe0,0x03,
11200x21,0x10,0x00,0x00,0x25,0xb0,0x0d,0x3c,0xe8,0xff,0xbd,0x27,0x10,0x00,0xbf,0xaf,
11210x2d,0x0a,0xa7,0x35,0xa2,0x0d,0xa2,0x35,0xa4,0x0d,0xa3,0x35,0xa6,0x0d,0xa4,0x35,
11220xa8,0x0d,0xa5,0x35,0x00,0x00,0x48,0x94,0x00,0x00,0x69,0x94,0x00,0x00,0x8a,0x94,
11230x00,0x00,0xab,0x94,0x00,0x00,0xe3,0x90,0x5b,0x0a,0xa4,0x35,0x5c,0x0a,0xa6,0x35,
11240x00,0x2e,0x03,0x00,0x03,0x2e,0x05,0x00,0x40,0x00,0xa2,0x34,0x00,0x00,0xe2,0xa0,
11250x00,0x00,0x85,0x90,0x00,0x00,0xc3,0x90,0x02,0x80,0x0e,0x3c,0x68,0x15,0xcc,0x25,
11260xff,0xff,0x22,0x31,0xff,0x00,0xa5,0x30,0xff,0xff,0x04,0x31,0x21,0x20,0x82,0x00,
11270xff,0x00,0x63,0x30,0x00,0x40,0x87,0x8d,0x00,0x2a,0x05,0x00,0xff,0xff,0x46,0x31,
11280x21,0x28,0xa3,0x00,0xff,0xff,0x62,0x31,0x21,0x20,0x86,0x00,0x21,0x20,0x82,0x00,
11290xff,0xff,0xa3,0x30,0x64,0x0c,0xa2,0x35,0x00,0x00,0x45,0xa4,0x21,0x20,0x83,0x00,
11300x0f,0x00,0xe7,0x30,0x01,0x00,0x02,0x24,0xe0,0x42,0x84,0xad,0xd8,0x42,0x88,0xa5,
11310xda,0x42,0x89,0xa5,0xdc,0x42,0x8a,0xa5,0xde,0x42,0x8b,0xa5,0x07,0x00,0xe2,0x10,
11320xe4,0x42,0x85,0xa5,0xa8,0x56,0x00,0x0c,0x00,0x00,0x00,0x00,0x10,0x00,0xbf,0x8f,
11330x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,0x4c,0x00,0xa3,0x35,
11340x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x03,0x00,0x42,0x30,0x67,0x00,0x47,0x10,
11350x68,0x15,0xc4,0x25,0xe6,0x42,0x82,0x90,0x00,0x00,0x00,0x00,0x2d,0x00,0x40,0x10,
11360x01,0x00,0x03,0x24,0x68,0x15,0xc5,0x25,0xe6,0x42,0xa3,0x90,0xff,0x00,0x02,0x24,
11370xec,0xff,0x62,0x14,0x25,0xb0,0x03,0x3c,0xc8,0x42,0xa2,0x94,0xe0,0x42,0xa6,0x8c,
11380x50,0x0c,0x63,0x34,0x00,0x00,0x64,0x90,0x2b,0x10,0xc2,0x00,0x5e,0x00,0x40,0x14,
11390x7f,0x00,0x84,0x30,0xca,0x42,0xa2,0x94,0x00,0x00,0x00,0x00,0x2b,0x10,0xc2,0x00,
11400x09,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0xcc,0x42,0xa2,0x94,0x00,0x00,0x00,0x00,
11410x2b,0x10,0xc2,0x00,0x02,0x00,0x40,0x10,0x02,0x00,0x82,0x24,0x01,0x00,0x82,0x24,
11420xff,0x00,0x44,0x30,0x68,0x15,0xc5,0x25,0xd0,0x42,0xa3,0x90,0x00,0x00,0x00,0x00,
11430x2b,0x10,0x64,0x00,0x4e,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x21,0x20,0x60,0x00,
11440x68,0x15,0xc3,0x25,0xe0,0x42,0x62,0x8c,0x00,0x00,0x00,0x00,0xe9,0x03,0x42,0x2c,
11450x02,0x00,0x40,0x14,0x25,0xb0,0x02,0x3c,0xd0,0x42,0x64,0x90,0x58,0x0c,0x43,0x34,
11460x50,0x0c,0x42,0x34,0x00,0x00,0x44,0xa0,0x00,0x00,0x64,0xa0,0x85,0x11,0x00,0x08,
11470x00,0x00,0x00,0x00,0x00,0x40,0x82,0x8c,0x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,
11480x0f,0x00,0x42,0x30,0xd0,0xff,0x43,0x14,0x68,0x15,0xc5,0x25,0x25,0xb0,0x02,0x3c,
11490x4c,0x00,0x42,0x34,0x00,0x00,0x43,0x90,0x00,0x00,0x00,0x00,0x03,0x00,0x63,0x30,
11500xb8,0xff,0x60,0x10,0xff,0xff,0x02,0x34,0xdc,0x63,0x83,0x8c,0x00,0x00,0x00,0x00,
11510xb4,0xff,0x62,0x10,0x00,0x00,0x00,0x00,0xe0,0x42,0x83,0x8c,0x00,0x00,0x00,0x00,
11520x65,0x00,0x62,0x2c,0x3b,0x00,0x40,0x14,0x28,0x00,0x62,0x2c,0xd2,0x42,0x83,0x90,
11530x00,0x00,0x00,0x00,0x00,0x16,0x03,0x00,0x03,0x16,0x02,0x00,0xfe,0xff,0x42,0x24,
11540xfc,0xff,0x42,0x28,0x02,0x00,0x40,0x10,0xfe,0xff,0x62,0x24,0xfc,0xff,0x02,0x24,
11550xd2,0x42,0x82,0xa0,0x68,0x15,0xc4,0x25,0xdc,0x63,0x82,0x8c,0xd2,0x42,0x83,0x90,
11560xce,0x42,0x86,0x90,0x02,0x11,0x02,0x00,0x7f,0x00,0x42,0x30,0x0a,0x00,0x45,0x24,
11570x23,0x18,0xa3,0x00,0x00,0x2e,0x03,0x00,0x03,0x2e,0x05,0x00,0xff,0x00,0xc2,0x30,
11580x2a,0x10,0x45,0x00,0x17,0x00,0x40,0x10,0x25,0xb0,0x02,0x3c,0x00,0x2e,0x06,0x00,
11590x03,0x2e,0x05,0x00,0x58,0x0c,0x43,0x34,0x50,0x0c,0x42,0x34,0x00,0x00,0x45,0xa0,
11600x00,0x00,0x65,0xa0,0x85,0x11,0x00,0x08,0x00,0x00,0x00,0x00,0xe6,0x42,0x82,0x91,
11610x00,0x00,0x00,0x00,0x97,0xff,0x40,0x14,0x00,0x00,0x00,0x00,0xff,0xff,0x02,0x24,
11620x91,0x11,0x00,0x08,0xe6,0x42,0x82,0xa1,0xac,0x11,0x00,0x08,0xff,0xff,0x82,0x24,
11630xd1,0x42,0xa3,0x90,0x00,0x00,0x00,0x00,0x2b,0x10,0x83,0x00,0xb4,0x11,0x00,0x08,
11640x0b,0x20,0x62,0x00,0xcf,0x42,0x83,0x80,0x00,0x00,0x00,0x00,0xff,0x00,0x62,0x30,
11650x2a,0x10,0xa2,0x00,0x0b,0x28,0x62,0x00,0x25,0xb0,0x02,0x3c,0x58,0x0c,0x43,0x34,
11660x50,0x0c,0x42,0x34,0x00,0x00,0x45,0xa0,0x00,0x00,0x65,0xa0,0x85,0x11,0x00,0x08,
11670x00,0x00,0x00,0x00,0xcf,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0xd2,0x42,0x83,0x90,
11680x00,0x00,0x00,0x00,0x00,0x16,0x03,0x00,0x03,0x16,0x02,0x00,0x02,0x00,0x42,0x24,
11690x0d,0x00,0x42,0x28,0x03,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0xe0,0x11,0x00,0x08,
11700x0c,0x00,0x02,0x24,0xe0,0x11,0x00,0x08,0x02,0x00,0x62,0x24,0xc0,0xff,0xbd,0x27,
11710x18,0x00,0xb0,0xaf,0x25,0xb0,0x10,0x3c,0x28,0x00,0xb4,0xaf,0x24,0x00,0xb3,0xaf,
11720x1c,0x00,0xb1,0xaf,0x3c,0x00,0xbf,0xaf,0x38,0x00,0xbe,0xaf,0x34,0x00,0xb7,0xaf,
11730x30,0x00,0xb6,0xaf,0x2c,0x00,0xb5,0xaf,0x20,0x00,0xb2,0xaf,0xd8,0x00,0x06,0x36,
11740x00,0x00,0xc3,0x90,0x02,0x80,0x02,0x3c,0x68,0x15,0x54,0x24,0x2a,0xb0,0x11,0x3c,
11750xa0,0xff,0x02,0x24,0x25,0x18,0x62,0x00,0x34,0x00,0x25,0x36,0xfe,0xff,0x02,0x24,
11760xbc,0x42,0x92,0x92,0x40,0x00,0x04,0x24,0x00,0x00,0xc3,0xa0,0x00,0x00,0xa2,0xa0,
11770xa1,0x4e,0x00,0x0c,0x00,0x96,0x12,0x00,0x21,0x98,0x40,0x00,0x6b,0x00,0x60,0x12,
11780x00,0x40,0x02,0x3c,0x08,0x00,0x63,0x8e,0xb0,0x03,0x02,0x36,0x21,0x20,0x60,0x02,
11790x00,0x00,0x43,0xac,0x3a,0x45,0x00,0x0c,0x21,0xb8,0x80,0x02,0x01,0x00,0x1e,0x24,
11800x42,0x00,0x16,0x36,0x03,0x0c,0x11,0x36,0x17,0x0e,0x15,0x36,0x04,0x00,0x14,0x24,
11810x2a,0xb0,0x03,0x3c,0x06,0x00,0x63,0x34,0x00,0x00,0x62,0x94,0x00,0x00,0x00,0x00,
11820x00,0xff,0x42,0x30,0x0a,0x00,0x40,0x18,0x00,0x00,0x00,0x00,0x02,0x80,0x04,0x3c,
11830xc8,0x94,0x84,0x24,0x00,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x94,
11840x00,0x00,0x00,0x00,0x00,0xff,0x42,0x30,0xfc,0xff,0x40,0x1c,0x00,0x00,0x00,0x00,
11850x08,0x00,0x65,0x8e,0x20,0x10,0x06,0x3c,0x00,0xfe,0xc6,0x34,0x40,0x00,0x07,0x24,
11860x01,0x00,0x04,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xbe,0xaf,0x4d,0x01,0x00,0x0c,
11870x01,0x00,0x04,0x24,0x2a,0xb0,0x02,0x3c,0x05,0x00,0x42,0x34,0xff,0xff,0x03,0x24,
11880x00,0x00,0x5e,0xa0,0x00,0x00,0xc3,0xa2,0x00,0x00,0x22,0x92,0xc1,0x42,0xe5,0x92,
11890x2a,0xb0,0x04,0x3c,0x02,0x00,0x03,0x24,0x40,0x00,0x42,0x34,0x05,0x00,0x84,0x34,
11900x00,0x00,0x22,0xa2,0x00,0x00,0x83,0xa0,0xef,0xff,0x02,0x24,0x00,0x00,0xb0,0x92,
11910x64,0x00,0x04,0x24,0x00,0x00,0xa5,0xa2,0x00,0x00,0xc2,0xa2,0xb3,0x0a,0x00,0x0c,
11920x00,0x00,0x00,0x00,0x00,0x00,0x22,0x92,0xbf,0xff,0x03,0x24,0x84,0x03,0x04,0x24,
11930x24,0x10,0x43,0x00,0x00,0x00,0x22,0xa2,0xb3,0x0a,0x00,0x0c,0xff,0x00,0x10,0x32,
11940x25,0xb0,0x02,0x3c,0xf4,0x08,0x42,0x34,0x00,0x00,0x44,0x8c,0x00,0x00,0xb0,0xa2,
11950x00,0x00,0xc0,0xa2,0x00,0x00,0x22,0x92,0xbe,0x42,0xe3,0x92,0x1f,0x00,0x85,0x30,
11960x40,0x00,0x42,0x34,0x00,0x00,0x22,0xa2,0x00,0x80,0x02,0x3c,0xdf,0x07,0x42,0x34,
11970x2b,0x18,0xa3,0x00,0x09,0x00,0x60,0x10,0x24,0x20,0x82,0x00,0xbf,0x42,0xe2,0x92,
11980x00,0x00,0x00,0x00,0x2b,0x10,0x45,0x00,0x05,0x00,0x40,0x10,0x02,0x80,0x02,0x3c,
11990x01,0x00,0x02,0x3c,0x25,0x10,0xa2,0x00,0x21,0x90,0x42,0x02,0x02,0x80,0x02,0x3c,
12000x8e,0x7d,0x43,0x90,0x22,0x00,0x02,0x24,0x1c,0x00,0x62,0x10,0x92,0x00,0x02,0x24,
12010x1b,0x00,0x62,0x10,0x02,0x80,0x03,0x3c,0xff,0xff,0x94,0x26,0xb3,0x0a,0x00,0x0c,
12020xf4,0x01,0x04,0x24,0xab,0xff,0x81,0x06,0x2a,0xb0,0x03,0x3c,0x04,0x00,0x60,0x12,
12030x25,0xb0,0x02,0x3c,0xbd,0x4e,0x00,0x0c,0x21,0x20,0x60,0x02,0x25,0xb0,0x02,0x3c,
12040xd8,0x02,0x42,0x34,0x00,0x00,0x52,0xac,0x21,0x10,0x40,0x02,0x3c,0x00,0xbf,0x8f,
12050x38,0x00,0xbe,0x8f,0x34,0x00,0xb7,0x8f,0x30,0x00,0xb6,0x8f,0x2c,0x00,0xb5,0x8f,
12060x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,
12070x18,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x40,0x00,0xbd,0x27,0x02,0x80,0x03,0x3c,
12080x68,0x15,0x63,0x24,0xbe,0x42,0x62,0x90,0xc0,0x07,0x83,0x30,0x82,0x19,0x03,0x00,
12090x2b,0x10,0x62,0x00,0xe0,0xff,0x40,0x10,0x02,0x80,0x04,0x3c,0x68,0x15,0x84,0x24,
12100xbf,0x42,0x82,0x90,0x00,0x00,0x00,0x00,0x2b,0x10,0x43,0x00,0xda,0xff,0x40,0x10,
12110x00,0x12,0x03,0x00,0x10,0x00,0x03,0x3c,0x25,0x10,0x43,0x00,0x9a,0x12,0x00,0x08,
12120x21,0x90,0x42,0x02,0xe8,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0x0f,0x00,0x10,0x3c,
12130xff,0xff,0x05,0x36,0xf0,0xf8,0x06,0x34,0x14,0x00,0xbf,0xaf,0xba,0x44,0x00,0x0c,
12140x15,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0xff,0xff,0x05,0x36,
12150x56,0x30,0x06,0x24,0xba,0x44,0x00,0x0c,0x1a,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,
12160x64,0x00,0x04,0x24,0x02,0x80,0x0b,0x3c,0x68,0x15,0x64,0x25,0x04,0x43,0x83,0x90,
12170x04,0x00,0x02,0x24,0x19,0x00,0x62,0x10,0x25,0xb0,0x02,0x3c,0x14,0x43,0x8a,0x8c,
12180x18,0x43,0x88,0x8c,0x25,0xb0,0x02,0x3c,0x1c,0x0e,0x49,0x34,0x00,0x0e,0x43,0x34,
12190x04,0x0e,0x44,0x34,0x08,0x0e,0x45,0x34,0x10,0x0e,0x46,0x34,0x14,0x0e,0x47,0x34,
12200x18,0x0e,0x42,0x34,0x00,0x00,0x6a,0xac,0x00,0x00,0x8a,0xac,0x00,0x00,0xa8,0xac,
12210x00,0x00,0xca,0xac,0x00,0x00,0xea,0xac,0x00,0x00,0x4a,0xac,0x00,0x00,0x2a,0xad,
12220x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x68,0x15,0x63,0x25,0x04,0x00,0x02,0x24,
12230x18,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,0x04,0x43,0x62,0xa0,0x00,0x0e,0x42,0x34,
12240x00,0x00,0x43,0x8c,0x14,0x43,0x8a,0x8c,0x00,0x00,0x00,0x00,0xe4,0xff,0x6a,0x14,
12250x00,0x00,0x00,0x00,0xec,0x12,0x00,0x08,0x00,0x00,0x00,0x00,0xe8,0xff,0xbd,0x27,
12260x10,0x00,0xb0,0xaf,0x0f,0x00,0x10,0x3c,0xff,0xff,0x05,0x36,0xf0,0xf8,0x06,0x34,
12270x14,0x00,0xbf,0xaf,0xba,0x44,0x00,0x0c,0x15,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,
12280x64,0x00,0x04,0x24,0xff,0xff,0x05,0x36,0x56,0x30,0x06,0x24,0xba,0x44,0x00,0x0c,
12290x1a,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x02,0x80,0x04,0x3c,
12300x68,0x15,0x83,0x24,0x04,0x43,0x65,0x90,0x21,0x70,0x60,0x00,0x10,0x10,0x03,0x3c,
12310x25,0xb0,0x02,0x3c,0x10,0x10,0x66,0x34,0x01,0x00,0x03,0x24,0x1c,0x0e,0x4d,0x34,
12320x00,0x0e,0x4a,0x34,0x04,0x0e,0x4b,0x34,0x08,0x0e,0x4c,0x34,0x10,0x0e,0x47,0x34,
12330x14,0x0e,0x48,0x34,0x0f,0x00,0xa3,0x10,0x18,0x0e,0x49,0x34,0x10,0x10,0x02,0x24,
12340x00,0x00,0x46,0xad,0x00,0x00,0x66,0xad,0x00,0x00,0x82,0xad,0x00,0x00,0xe6,0xac,
12350x00,0x00,0x06,0xad,0x00,0x00,0x26,0xad,0x00,0x00,0xa6,0xad,0x14,0x00,0xbf,0x8f,
12360x10,0x00,0xb0,0x8f,0x01,0x00,0x02,0x24,0x18,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,
12370x04,0x43,0xc2,0xa1,0x00,0x00,0x44,0x8d,0x00,0x00,0x00,0x00,0xf0,0xff,0x86,0x14,
12380x10,0x10,0x02,0x24,0x23,0x13,0x00,0x08,0x00,0x00,0x00,0x00,0xe0,0xff,0xbd,0x27,
12390x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x01,0x00,0x11,0x3c,0x0f,0x00,0x10,0x3c,
12400xff,0xff,0x05,0x36,0xf4,0x98,0x26,0x36,0x18,0x00,0xbf,0xaf,0xba,0x44,0x00,0x0c,
12410x15,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0xff,0xff,0x05,0x36,
12420x56,0x30,0x26,0x36,0xba,0x44,0x00,0x0c,0x1a,0x00,0x04,0x24,0x02,0x80,0x10,0x3c,
12430xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x68,0x15,0x04,0x26,0x04,0x43,0x82,0x90,
12440x00,0x00,0x00,0x00,0x0d,0x00,0x40,0x14,0x25,0xb0,0x02,0x3c,0x00,0x0e,0x42,0x34,
12450x00,0x00,0x43,0x8c,0xec,0x42,0x8f,0x8c,0x00,0x00,0x00,0x00,0x08,0x00,0x6f,0x14,
12460x68,0x15,0x02,0x26,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,
12470x20,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,0x04,0x43,0x40,0xa0,0xec,0x42,0x8f,0x8c,
12480xe8,0x42,0x88,0x8c,0xf0,0x42,0x8a,0x8c,0xf4,0x42,0x8b,0x8c,0xf8,0x42,0x8c,0x8c,
12490xfc,0x42,0x8d,0x8c,0x25,0xb0,0x02,0x3c,0x00,0x43,0x8e,0x8c,0x1c,0x0e,0x49,0x34,
12500x08,0x0e,0x43,0x34,0x00,0x0e,0x44,0x34,0x04,0x0e,0x45,0x34,0x10,0x0e,0x46,0x34,
12510x14,0x0e,0x47,0x34,0x18,0x0e,0x42,0x34,0x00,0x00,0x68,0xac,0x18,0x00,0xbf,0x8f,
12520x00,0x00,0x8f,0xac,0x14,0x00,0xb1,0x8f,0x00,0x00,0xaa,0xac,0x00,0x00,0xcb,0xac,
12530x00,0x00,0xec,0xac,0x00,0x00,0x4d,0xac,0x68,0x15,0x02,0x26,0x10,0x00,0xb0,0x8f,
12540x20,0x00,0xbd,0x27,0x00,0x00,0x2e,0xad,0x08,0x00,0xe0,0x03,0x04,0x43,0x40,0xa0,
12550xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x01,0x00,0x11,0x3c,
12560x0f,0x00,0x10,0x3c,0xff,0xff,0x05,0x36,0xf4,0x98,0x26,0x36,0x18,0x00,0xbf,0xaf,
12570xba,0x44,0x00,0x0c,0x15,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,
12580xff,0xff,0x05,0x36,0x56,0x30,0x26,0x36,0xba,0x44,0x00,0x0c,0x1a,0x00,0x04,0x24,
12590xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x02,0x80,0x18,0x3c,0x68,0x15,0x05,0x27,
12600x04,0x43,0xa3,0x90,0x03,0x00,0x02,0x24,0x2a,0x00,0x62,0x10,0x25,0xb0,0x02,0x3c,
12610xec,0x42,0xaf,0x8c,0x08,0x43,0xa3,0x8c,0xe8,0x42,0xa2,0x8c,0xf0,0x42,0xac,0x8c,
12620xf4,0x42,0xad,0x8c,0xf8,0x42,0xa9,0x8c,0xfc,0x42,0xaa,0x8c,0x00,0x43,0xab,0x8c,
12630x21,0x70,0x43,0x00,0xff,0xff,0x02,0x3c,0x25,0xb0,0x03,0x3c,0xff,0x00,0x42,0x34,
12640x00,0xff,0xc4,0x31,0x04,0x0e,0x65,0x34,0x10,0x0e,0x66,0x34,0x14,0x0e,0x67,0x34,
12650x18,0x0e,0x68,0x34,0x24,0x80,0xc2,0x01,0x08,0x0e,0x71,0x34,0x00,0x0e,0x62,0x34,
12660x01,0x3f,0x84,0x2c,0x1c,0x0e,0x63,0x34,0x00,0x00,0x4f,0xac,0x00,0x00,0xac,0xac,
12670x00,0x00,0xcd,0xac,0x00,0x00,0xe9,0xac,0x00,0x00,0x0a,0xad,0x00,0x00,0x6b,0xac,
12680x0a,0x00,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x2e,0xae,0x18,0x00,0xbf,0x8f,
12690x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x68,0x15,0x03,0x27,0x03,0x00,0x02,0x24,
12700x20,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,0x04,0x43,0x62,0xa0,0xa6,0x13,0x00,0x08,
12710x00,0x3f,0x0e,0x36,0x00,0x0e,0x42,0x34,0x00,0x00,0x43,0x8c,0xec,0x42,0xaf,0x8c,
12720x00,0x00,0x00,0x00,0xd3,0xff,0x6f,0x14,0x00,0x00,0x00,0x00,0xa7,0x13,0x00,0x08,
12730x00,0x00,0x00,0x00,0xd0,0xff,0xbd,0x27,0x18,0x00,0xb2,0xaf,0x02,0x80,0x12,0x3c,
12740x24,0x00,0xb5,0xaf,0x20,0x00,0xb4,0xaf,0x28,0x00,0xbf,0xaf,0x1c,0x00,0xb3,0xaf,
12750x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x68,0x15,0x44,0x26,0x02,0x80,0x14,0x3c,
12760x00,0x40,0x85,0x8c,0xdc,0x63,0x83,0x8c,0x8e,0x7d,0x86,0x92,0x25,0xb0,0x02,0x3c,
12770x0f,0x0c,0x42,0x34,0x00,0x00,0x46,0xa0,0x02,0x19,0x03,0x00,0xf0,0xf0,0xa5,0x30,
12780x00,0x10,0x02,0x24,0x04,0x43,0x93,0x90,0x71,0x00,0xa2,0x10,0x7f,0x00,0x75,0x30,
12790x25,0xb0,0x09,0x3c,0x4c,0x00,0x23,0x35,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,
12800x03,0x00,0x42,0x30,0x09,0x00,0x40,0x10,0x68,0x15,0x45,0x26,0x68,0x15,0x4a,0x26,
12810x00,0x40,0x42,0x8d,0x00,0x00,0x00,0x00,0x02,0x13,0x02,0x00,0x0f,0x00,0x42,0x30,
12820x33,0x00,0x40,0x10,0x00,0x0e,0x25,0x35,0x68,0x15,0x45,0x26,0x04,0x43,0xa2,0x8c,
12830x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,0x0f,0x00,0x40,0x14,0x68,0x15,0x4a,0x26,
12840x25,0xb0,0x02,0x3c,0x84,0x01,0x42,0x34,0x00,0x00,0x44,0x8c,0x0d,0x00,0x03,0x24,
12850x7e,0x00,0x83,0x10,0x3e,0x00,0x02,0x24,0x4a,0x00,0x03,0x24,0x1f,0x43,0xa2,0xa0,
12860x1c,0x43,0xa3,0xa0,0x45,0x00,0x02,0x24,0x43,0x00,0x03,0x24,0x1d,0x43,0xa2,0xa0,
12870x1e,0x43,0xa3,0xa0,0x68,0x15,0x4a,0x26,0xdc,0x63,0x4c,0x8d,0x04,0x40,0x42,0x8d,
12880x00,0x40,0x4b,0x8d,0x1e,0x43,0x4d,0x91,0x1c,0x43,0x4e,0x91,0x25,0xb0,0x09,0x3c,
12890x02,0x11,0x02,0x00,0x60,0x0c,0x27,0x35,0x02,0x19,0x0c,0x00,0x98,0x0c,0x24,0x35,
12900x00,0x00,0xe3,0xa0,0x66,0x0c,0x25,0x35,0x00,0x00,0x82,0xa0,0x67,0x0c,0x26,0x35,
12910xf0,0xf0,0x68,0x31,0x10,0x10,0x02,0x24,0x00,0x00,0xad,0xa0,0x00,0x00,0xce,0xa0,
12920x43,0x00,0x02,0x11,0xff,0xff,0x02,0x34,0x28,0x00,0xbf,0x8f,0x24,0x00,0xb5,0x8f,
12930x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
12940x10,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,
12950x00,0x00,0xa2,0x8c,0x00,0x00,0x00,0x00,0x5d,0x00,0x40,0x10,0x10,0x0e,0x28,0x35,
12960x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
12970x08,0x0e,0x22,0x35,0x04,0x0e,0x24,0x35,0x00,0x00,0x43,0x8c,0x00,0x00,0xa5,0x8c,
12980x00,0x00,0x82,0x8c,0xe8,0x42,0x43,0xad,0xec,0x42,0x45,0xad,0xf0,0x42,0x42,0xad,
12990x14,0x0e,0x24,0x35,0x18,0x0e,0x22,0x35,0x1c,0x0e,0x25,0x35,0x00,0x00,0x08,0x8d,
13000x8e,0x7d,0x8b,0x92,0x00,0x00,0x86,0x8c,0x00,0xff,0x63,0x30,0x00,0x00,0x47,0x8c,
13010x00,0x00,0xa4,0x8c,0x9a,0x0c,0x22,0x35,0x02,0x1a,0x03,0x00,0x00,0x00,0x43,0xa0,
13020x22,0x00,0x02,0x24,0xf4,0x42,0x48,0xad,0xf8,0x42,0x46,0xad,0xfc,0x42,0x47,0xad,
13030x58,0x00,0x62,0x11,0x00,0x43,0x44,0xad,0x92,0x00,0x02,0x24,0x56,0x00,0x62,0x11,
13040x0d,0x08,0x22,0x35,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
13050x68,0x15,0x44,0x26,0x00,0x40,0x83,0x8c,0xff,0xff,0x02,0x3c,0xff,0x0f,0x42,0x34,
13060x24,0x18,0x62,0x00,0x00,0x10,0x63,0x34,0xde,0x13,0x00,0x08,0x00,0x40,0x83,0xac,
13070x01,0x00,0x02,0x24,0x35,0x00,0x62,0x12,0x04,0x00,0x02,0x24,0x33,0x00,0x62,0x12,
13080x68,0x15,0x43,0x26,0xff,0xff,0x02,0x24,0xd0,0x13,0x00,0x08,0x04,0x43,0x62,0xa0,
13090xbd,0xff,0x82,0x11,0x02,0x12,0x0b,0x00,0x0f,0x00,0x48,0x30,0x01,0x00,0x03,0x24,
13100xb9,0xff,0x03,0x15,0x4c,0x00,0x23,0x35,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,
13110x03,0x00,0x42,0x30,0xb4,0xff,0x40,0x10,0x03,0x00,0x02,0x24,0x5f,0x00,0x62,0x12,
13120x04,0x00,0x62,0x2a,0x45,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x64,0x00,0x60,0x12,
13130xff,0x00,0xa2,0x31,0xac,0xff,0x68,0x16,0xff,0x00,0xc2,0x31,0x2b,0x10,0xa2,0x02,
13140x52,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x1f,0x43,0x42,0x91,0x00,0x00,0x00,0x00,
13150x2b,0x10,0x55,0x00,0x44,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x2f,0x13,0x00,0x0c,
13160x00,0x00,0x00,0x00,0x06,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x3b,0x00,0x02,0x24,
13170x46,0x00,0x03,0x24,0x1f,0x43,0xa2,0xa0,0x1c,0x43,0xa3,0xa0,0x41,0x00,0x02,0x24,
13180x40,0x00,0x03,0x24,0x1d,0x43,0xa2,0xa0,0xf1,0x13,0x00,0x08,0x1e,0x43,0xa3,0xa0,
13190x00,0x00,0x03,0x8d,0x3f,0x3f,0x02,0x3c,0x3f,0x3f,0x42,0x34,0xa0,0xff,0x62,0x14,
13200x00,0x00,0x00,0x00,0xdf,0x13,0x00,0x08,0x68,0x15,0x45,0x26,0x0f,0x00,0x10,0x3c,
13210x01,0x00,0x11,0x3c,0xff,0xff,0x05,0x36,0xf4,0x98,0x26,0x36,0xba,0x44,0x00,0x0c,
13220x15,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0xff,0xff,0x05,0x36,
13230x56,0x30,0x26,0x36,0xba,0x44,0x00,0x0c,0x1a,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,
13240x64,0x00,0x04,0x24,0x68,0x15,0x43,0x26,0xff,0xff,0x02,0x24,0xd0,0x13,0x00,0x08,
13250x04,0x43,0x62,0xa0,0x0d,0x08,0x22,0x35,0x00,0x00,0x43,0x90,0x00,0x00,0x00,0x00,
13260x0f,0x00,0x63,0x30,0x08,0x00,0x62,0x2c,0x0f,0x00,0x63,0x38,0xa5,0xff,0x40,0x14,
13270x01,0x00,0x65,0x24,0x00,0x16,0x05,0x00,0x00,0x24,0x05,0x00,0x00,0x1a,0x05,0x00,
13280x25,0x10,0x44,0x00,0x25,0x10,0x43,0x00,0x25,0x10,0x45,0x00,0x25,0x18,0x65,0x00,
13290x18,0x43,0x43,0xad,0x35,0x14,0x00,0x08,0x14,0x43,0x42,0xad,0x04,0x00,0x02,0x24,
13300x0d,0x00,0x62,0x12,0xff,0x00,0x02,0x24,0x67,0xff,0x62,0x16,0xff,0x00,0xa2,0x31,
13310x2b,0x10,0xa2,0x02,0x1d,0x00,0x40,0x14,0xff,0x00,0xc2,0x31,0x2b,0x10,0xa2,0x02,
13320x0a,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0xfb,0x12,0x00,0x0c,0x00,0x00,0x00,0x00,
13330x06,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x1d,0x43,0x42,0x91,0x00,0x00,0x00,0x00,
13340x2b,0x10,0x55,0x00,0xf8,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0xc5,0x12,0x00,0x0c,
13350x00,0x00,0x00,0x00,0x06,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x20,0x43,0x42,0x91,
13360x00,0x00,0x00,0x00,0x2b,0x10,0xa2,0x02,0xac,0xff,0x40,0x10,0x00,0x00,0x00,0x00,
13370x70,0x13,0x00,0x0c,0x00,0x00,0x00,0x00,0x06,0x14,0x00,0x08,0x00,0x00,0x00,0x00,
13380x2b,0x10,0xa2,0x02,0xe8,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0x21,0x43,0x42,0x91,
13390x00,0x00,0x00,0x00,0x2b,0x10,0x55,0x00,0xa0,0xff,0x40,0x14,0x00,0x00,0x00,0x00,
13400x70,0x13,0x00,0x0c,0x00,0x00,0x00,0x00,0x06,0x14,0x00,0x08,0x00,0x00,0x00,0x00,
13410x02,0x80,0x08,0x3c,0x68,0x15,0x05,0x25,0xdc,0x63,0xa4,0x8c,0xe6,0x42,0xa3,0x90,
13420x02,0x11,0x04,0x00,0x1f,0x00,0x60,0x14,0x7f,0x00,0x46,0x30,0x25,0xb0,0x07,0x3c,
13430x4c,0x00,0xe2,0x34,0x00,0x00,0x43,0x90,0x00,0x00,0x00,0x00,0x19,0x00,0x60,0x10,
13440x00,0x00,0x00,0x00,0xff,0xff,0x02,0x34,0x16,0x00,0x82,0x10,0x00,0x00,0x00,0x00,
13450x00,0x08,0xe3,0x34,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x30,
13460x12,0x00,0x40,0x10,0x4b,0x00,0xc2,0x2c,0x29,0x00,0x40,0x10,0x01,0x00,0x04,0x24,
13470xd8,0xff,0xc2,0x24,0x1e,0x00,0x42,0x2c,0x2f,0x00,0x40,0x10,0x23,0x00,0xc2,0x2c,
13480x68,0x15,0x04,0x25,0xd3,0x42,0x82,0x90,0x00,0x00,0x00,0x00,0x29,0x00,0x40,0x10,
13490x25,0xb0,0x02,0x3c,0x20,0x00,0x03,0x24,0x87,0x0c,0x42,0x34,0x00,0x00,0x43,0xa0,
13500xd3,0x42,0x80,0xa0,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x0f,0x00,0x40,0x10,
13510x01,0x00,0x04,0x24,0xd8,0xff,0xc2,0x24,0x1e,0x00,0x42,0x2c,0x2c,0x00,0x40,0x10,
13520x23,0x00,0xc2,0x2c,0x68,0x15,0x04,0x25,0xd3,0x42,0x82,0x90,0x00,0x00,0x00,0x00,
13530x26,0x00,0x40,0x10,0x25,0xb0,0x02,0x3c,0x44,0x00,0x03,0x24,0x30,0x0c,0x42,0x34,
13540x00,0x00,0x43,0xa0,0xed,0x14,0x00,0x08,0xd3,0x42,0x80,0xa0,0xd3,0x42,0xa2,0x90,
13550x00,0x00,0x00,0x00,0xef,0xff,0x44,0x10,0x30,0x0c,0xe3,0x34,0x43,0x00,0x02,0x24,
13560xd3,0x42,0xa4,0xa0,0x00,0x00,0x62,0xa0,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
13570xd3,0x42,0xa2,0x90,0x00,0x00,0x00,0x00,0xd5,0xff,0x44,0x10,0x87,0x0c,0xe3,0x34,
13580x10,0x00,0x02,0x24,0xd3,0x42,0xa4,0xa0,0x00,0x00,0x62,0xa0,0x06,0x15,0x00,0x08,
13590x00,0x00,0x00,0x00,0x23,0x00,0xc2,0x2c,0xda,0xff,0x40,0x10,0x00,0x00,0x00,0x00,
13600x68,0x15,0x04,0x25,0xd3,0x42,0x82,0x90,0x02,0x00,0x03,0x24,0xd5,0xff,0x43,0x10,
13610x00,0x00,0x00,0x00,0x25,0xb0,0x02,0x3c,0x87,0x0c,0x42,0x34,0xd3,0x42,0x83,0xa0,
13620x00,0x00,0x40,0xa0,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x23,0x00,0xc2,0x2c,
13630xcc,0xff,0x40,0x10,0x00,0x00,0x00,0x00,0x68,0x15,0x04,0x25,0xd3,0x42,0x82,0x90,
13640x02,0x00,0x03,0x24,0xc7,0xff,0x43,0x10,0x00,0x00,0x00,0x00,0x25,0xb0,0x02,0x3c,
13650xd3,0x42,0x83,0xa0,0x30,0x0c,0x42,0x34,0x42,0x00,0x03,0x24,0x00,0x00,0x43,0xa0,
13660x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x02,0x80,0x02,0x3c,0x68,0x15,0x45,0x24,
13670xd5,0x42,0xa3,0x90,0x02,0x00,0x02,0x24,0x03,0x00,0x62,0x10,0x00,0x00,0x00,0x00,
13680x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0xdc,0x63,0xa2,0x8c,0x25,0xb0,0x03,0x3c,
13690x0a,0x0a,0x68,0x34,0x02,0x11,0x02,0x00,0x7f,0x00,0x42,0x30,0x1a,0x00,0x44,0x2c,
13700x14,0x00,0x42,0x2c,0x01,0x0a,0x66,0x34,0x0b,0x00,0x40,0x14,0x2e,0x0a,0x67,0x34,
13710xf3,0xff,0x80,0x14,0x00,0x00,0x00,0x00,0xd4,0x42,0xa4,0x90,0x01,0x00,0x02,0x24,
13720x01,0x0a,0x67,0x34,0x0f,0x00,0x82,0x10,0x2e,0x0a,0x66,0x34,0xd4,0x42,0xa0,0xa0,
13730x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x40,0x00,0x02,0x24,0x00,0x00,0xc2,0xa0,
13740x01,0x00,0x03,0x24,0xdf,0xff,0x02,0x24,0xd4,0x42,0xa3,0xa0,0x00,0x00,0xe2,0xa0,
13750x03,0x00,0x03,0x24,0x21,0x10,0x00,0x00,0x00,0x00,0x03,0xa1,0x08,0x00,0xe0,0x03,
13760x00,0x00,0x00,0x00,0x47,0x00,0x02,0x24,0x00,0x00,0xe2,0xa0,0xd3,0xff,0x03,0x24,
13770x83,0xff,0x02,0x24,0x00,0x00,0xc3,0xa0,0x00,0x00,0x02,0xa1,0x48,0x15,0x00,0x08,
13780xd4,0x42,0xa0,0xa0,0xd0,0xff,0xbd,0x27,0x1c,0x00,0xb1,0xaf,0x28,0x00,0xbf,0xaf,
13790x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x18,0x00,0xb0,0xaf,0xff,0xff,0x11,0x24,
13800x02,0x80,0x13,0x3c,0x41,0xb0,0x02,0x3c,0x68,0x15,0x66,0x26,0x04,0x00,0x42,0x34,
13810x00,0x00,0x47,0x8c,0x00,0x4b,0xc5,0x8c,0x02,0x80,0x03,0x3c,0x96,0x7d,0x64,0x90,
13820xfc,0x4a,0xc8,0x8c,0x02,0x80,0x02,0x3c,0xb8,0x7d,0x49,0x90,0x25,0xb0,0x0a,0x3c,
13830x25,0x90,0xa7,0x00,0xb0,0x03,0x42,0x35,0x00,0x00,0x52,0xac,0x00,0x24,0x04,0x00,
13840x00,0x00,0x48,0xac,0x84,0x02,0x43,0x35,0x8c,0x02,0x45,0x35,0x01,0x00,0x02,0x24,
13850x00,0x00,0x72,0xac,0x00,0x00,0xa4,0xac,0xb9,0x04,0x22,0x11,0x00,0x4b,0xd2,0xac,
13860x68,0x15,0x66,0x26,0xfc,0x4a,0xc2,0x8c,0x00,0x00,0x00,0x00,0x24,0x28,0x52,0x00,
13870x01,0x00,0xa3,0x30,0x09,0x00,0x60,0x10,0x04,0x00,0xa2,0x30,0x00,0x4b,0xc2,0x8c,
13880x25,0xb0,0x03,0x3c,0x01,0x00,0x04,0x24,0x01,0x00,0x42,0x38,0xb0,0x03,0x63,0x34,
13890x00,0x00,0x64,0xac,0x00,0x4b,0xc2,0xac,0x04,0x00,0xa2,0x30,0x09,0x00,0x40,0x10,
13900x08,0x00,0xa2,0x30,0x00,0x4b,0xc2,0x8c,0x25,0xb0,0x03,0x3c,0x04,0x00,0x04,0x24,
13910x04,0x00,0x42,0x38,0xb0,0x03,0x63,0x34,0x00,0x00,0x64,0xac,0x00,0x4b,0xc2,0xac,
13920x08,0x00,0xa2,0x30,0x0e,0x00,0x40,0x10,0x68,0x15,0x64,0x26,0xc9,0x64,0xc2,0x90,
13930x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,
13940x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0xc9,0x64,0xc0,0xa0,0x00,0x4b,0xc2,0x8c,
13950x00,0x00,0x00,0x00,0x08,0x00,0x42,0x38,0x00,0x4b,0xc2,0xac,0x68,0x15,0x64,0x26,
13960xfc,0x4a,0x82,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,0x10,0x00,0x42,0x30,
13970x0d,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,
13980x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,
13990x00,0x00,0x43,0xa0,0xc9,0x64,0x80,0xa0,0x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,
14000x10,0x00,0x42,0x38,0x00,0x4b,0x82,0xac,0x68,0x15,0x64,0x26,0xfc,0x4a,0x82,0x8c,
14010x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,0x20,0x00,0x42,0x30,0x0e,0x00,0x40,0x10,
14020x00,0x00,0x00,0x00,0xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,
14030x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,
14040xc9,0x64,0x80,0xa0,0x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,0x20,0x00,0x42,0x38,
14050x00,0x4b,0x82,0xac,0x68,0x15,0x64,0x26,0xfc,0x4a,0x82,0x8c,0x00,0x00,0x00,0x00,
14060x24,0x10,0x52,0x00,0x40,0x00,0x42,0x30,0x0d,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
14070xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,
14080x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0xc9,0x64,0x80,0xa0,
14090x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,0x40,0x00,0x42,0x38,0x00,0x4b,0x82,0xac,
14100x68,0x15,0x64,0x26,0xfc,0x4a,0x82,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,
14110x80,0x00,0x42,0x30,0x0e,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0xc9,0x64,0x82,0x90,
14120x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,
14130x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0xc9,0x64,0x80,0xa0,0x00,0x4b,0x82,0x8c,
14140x00,0x00,0x00,0x00,0x80,0x00,0x42,0x38,0x00,0x4b,0x82,0xac,0x68,0x15,0x64,0x26,
14150xfc,0x4a,0x82,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,0x00,0x01,0x42,0x30,
14160x0d,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,
14170x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,
14180x00,0x00,0x43,0xa0,0xc9,0x64,0x80,0xa0,0x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,
14190x00,0x01,0x42,0x38,0x00,0x4b,0x82,0xac,0x68,0x15,0x64,0x26,0xfc,0x4a,0x82,0x8c,
14200x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,0x00,0x02,0x42,0x30,0x0e,0x00,0x40,0x10,
14210x00,0x00,0x00,0x00,0xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,
14220x2a,0xb0,0x02,0x3c,0x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,
14230xc9,0x64,0x80,0xa0,0x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x02,0x42,0x38,
14240x00,0x4b,0x82,0xac,0x68,0x15,0x64,0x26,0xfc,0x4a,0x82,0x8c,0x00,0x00,0x00,0x00,
14250x24,0x10,0x52,0x00,0x00,0x04,0x42,0x30,0x0d,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
14260xc9,0x64,0x82,0x90,0x00,0x00,0x00,0x00,0x05,0x00,0x40,0x18,0x2a,0xb0,0x02,0x3c,
14270x02,0x00,0x03,0x24,0x01,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0xc9,0x64,0x80,0xa0,
14280x00,0x4b,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x04,0x42,0x38,0x00,0x4b,0x82,0xac,
14290x68,0x15,0x63,0x26,0xfc,0x4a,0x62,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,
14300x00,0x08,0x42,0x30,0x3a,0x00,0x40,0x10,0x2a,0xb0,0x05,0x3c,0x00,0x00,0xa8,0x8c,
14310xff,0x00,0x02,0x24,0xff,0x00,0x04,0x31,0x31,0x00,0x82,0x10,0x00,0x80,0x02,0x31,
14320x08,0x04,0x40,0x14,0x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,
14330x05,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0xc9,0x64,0x62,0x90,0x00,0x00,0x00,0x00,
14340x0b,0x00,0x40,0x18,0xff,0x00,0x02,0x24,0x08,0x64,0x62,0x90,0x20,0xb0,0x03,0x3c,
14350x00,0x12,0x02,0x00,0x21,0x10,0x43,0x00,0x0c,0x00,0x48,0x8c,0x25,0xb0,0x03,0x3c,
14360xb0,0x03,0x63,0x34,0x00,0x00,0x68,0xac,0xff,0x00,0x04,0x31,0xff,0x00,0x02,0x24,
14370x1a,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,0xc0,0x64,0x05,0x8e,
14380x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,
14390x54,0x64,0x03,0xae,0x21,0x20,0x00,0x00,0x08,0x64,0x08,0xa2,0x20,0x00,0x07,0x24,
14400x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0xfc,0x4a,0x05,0x8e,0x02,0x80,0x06,0x3c,
14410x6c,0x7e,0xc4,0x8c,0xff,0xc7,0x02,0x24,0x24,0x28,0xa2,0x00,0x25,0xb0,0x02,0x3c,
14420x04,0x00,0x84,0x34,0x80,0x03,0x42,0x34,0x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,
14430x00,0x00,0x65,0xac,0x6c,0x7e,0xc4,0xac,0xfc,0x4a,0x05,0xae,0x68,0x15,0x63,0x26,
14440x00,0x4b,0x62,0x8c,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x38,0x00,0x4b,0x62,0xac,
14450x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,
14460x00,0x10,0x42,0x30,0x38,0x00,0x40,0x10,0x2a,0xb0,0x02,0x3c,0x08,0x00,0x43,0x34,
14470x00,0x00,0x68,0x8c,0xff,0x00,0x02,0x24,0xff,0x00,0x04,0x31,0x2c,0x00,0x82,0x10,
14480x00,0x80,0x02,0x31,0xca,0x03,0x40,0x14,0x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,
14490x24,0x10,0x02,0x01,0x0b,0x00,0x40,0x10,0xff,0x00,0x02,0x24,0x10,0x64,0xa2,0x90,
14500x20,0xb0,0x03,0x3c,0x00,0x12,0x02,0x00,0x21,0x10,0x43,0x00,0x0c,0x00,0x48,0x8c,
14510x25,0xb0,0x03,0x3c,0xb0,0x03,0x63,0x34,0x00,0x00,0x68,0xac,0xff,0x00,0x04,0x31,
14520xff,0x00,0x02,0x24,0x1a,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,
14530xd8,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
14540x21,0x30,0x60,0x00,0x6c,0x64,0x03,0xae,0x01,0x00,0x04,0x24,0x10,0x64,0x08,0xa2,
14550x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0xfc,0x4a,0x05,0x8e,
14560x02,0x80,0x06,0x3c,0x6c,0x7e,0xc4,0x8c,0xff,0xc7,0x02,0x24,0x24,0x28,0xa2,0x00,
14570x25,0xb0,0x02,0x3c,0x10,0x00,0x84,0x34,0x80,0x03,0x42,0x34,0x41,0xb0,0x03,0x3c,
14580x00,0x00,0x44,0xac,0x00,0x00,0x65,0xac,0x6c,0x7e,0xc4,0xac,0xfc,0x4a,0x05,0xae,
14590x68,0x15,0x63,0x26,0x00,0x4b,0x62,0x8c,0x00,0x00,0x00,0x00,0x00,0x10,0x42,0x38,
14600x00,0x4b,0x62,0xac,0x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x00,0x00,0x00,0x00,
14610x24,0x10,0x52,0x00,0x00,0x20,0x42,0x30,0x37,0x00,0x40,0x10,0x2a,0xb0,0x02,0x3c,
14620x04,0x00,0x43,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x02,0x24,0xff,0x00,0x04,0x31,
14630xab,0x03,0x82,0x10,0x00,0x80,0x02,0x31,0x90,0x03,0x40,0x14,0x00,0x80,0x02,0x3c,
14640x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x0b,0x00,0x40,0x10,0xff,0x00,0x02,0x24,
14650x0c,0x64,0xa2,0x90,0x20,0xb0,0x03,0x3c,0x00,0x12,0x02,0x00,0x21,0x10,0x43,0x00,
14660x0c,0x00,0x48,0x8c,0x25,0xb0,0x03,0x3c,0xb0,0x03,0x63,0x34,0x00,0x00,0x68,0xac,
14670xff,0x00,0x04,0x31,0xff,0x00,0x02,0x24,0x1a,0x00,0x82,0x10,0xff,0x00,0x03,0x31,
14680x68,0x15,0x70,0x26,0xcc,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,
14690x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,0x60,0x64,0x03,0xae,0x01,0x00,0x04,0x24,
14700x0c,0x64,0x08,0xa2,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
14710xfc,0x4a,0x05,0x8e,0x02,0x80,0x06,0x3c,0x6c,0x7e,0xc4,0x8c,0xff,0xc7,0x02,0x24,
14720x24,0x28,0xa2,0x00,0x25,0xb0,0x02,0x3c,0x20,0x00,0x84,0x34,0x80,0x03,0x42,0x34,
14730x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,0x00,0x00,0x65,0xac,0x6c,0x7e,0xc4,0xac,
14740xfc,0x4a,0x05,0xae,0x68,0x15,0x63,0x26,0x00,0x4b,0x62,0x8c,0x00,0x00,0x00,0x00,
14750x00,0x20,0x42,0x38,0x00,0x4b,0x62,0xac,0x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,
14760x00,0x00,0x00,0x00,0x24,0x10,0x52,0x00,0x00,0x80,0x42,0x30,0x59,0x00,0x40,0x10,
14770x2a,0xb0,0x06,0x3c,0x0c,0x00,0xc3,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x07,0x24,
14780xff,0x00,0x04,0x31,0x78,0x03,0x87,0x10,0x00,0x80,0x02,0x31,0x24,0x00,0x40,0x14,
14790x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x22,0x00,0x40,0x10,
14800xff,0x00,0x02,0x24,0x40,0x00,0xc6,0x34,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,
14810xff,0x00,0x44,0x30,0x0f,0x00,0x87,0x10,0x68,0x15,0x62,0x26,0xe8,0x63,0xa4,0xa0,
14820x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x09,0x00,0x83,0x10,
14830x68,0x15,0x62,0x26,0x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,
14840x21,0x18,0x80,0x00,0xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0xe8,0x63,0xe3,0xa0,
14850x68,0x15,0x62,0x26,0xe8,0x63,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,
14860x21,0x18,0x62,0x00,0x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,
14870xff,0x00,0x04,0x31,0x00,0x00,0x48,0xac,0x16,0x17,0x00,0x08,0xff,0x00,0x02,0x24,
14880x00,0x00,0x62,0xac,0xff,0x00,0x02,0x24,0x24,0x00,0x82,0x10,0x68,0x15,0x70,0x26,
14890xff,0x00,0x03,0x31,0x90,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,
14900x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,0xe8,0x63,0x08,0xa2,0x24,0x64,0x03,0xae,
14910x03,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
14920x02,0x80,0x0a,0x3c,0x7c,0x7e,0x47,0x91,0x02,0x80,0x09,0x3c,0x6c,0x7e,0x25,0x8d,
14930xfc,0x4a,0x06,0x8e,0x01,0x00,0x08,0x3c,0x80,0xff,0x02,0x24,0x25,0x38,0xe2,0x00,
14940x00,0x80,0x03,0x35,0x80,0x00,0xa5,0x34,0x27,0x18,0x03,0x00,0x00,0x26,0x07,0x00,
14950x25,0xb0,0x02,0x3c,0x24,0x30,0xc3,0x00,0x25,0x20,0x85,0x00,0x80,0x03,0x42,0x34,
14960x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,0x27,0x88,0x08,0x00,0x00,0x00,0x66,0xac,
14970x6c,0x7e,0x25,0xad,0x7c,0x7e,0x47,0xa1,0xfc,0x4a,0x06,0xae,0x68,0x15,0x63,0x26,
14980x00,0x4b,0x62,0x8c,0x00,0x00,0x00,0x00,0x00,0x80,0x42,0x38,0x00,0x4b,0x62,0xac,
14990x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x01,0x00,0x03,0x3c,0x24,0x10,0x52,0x00,
15000x24,0x10,0x51,0x00,0x24,0x10,0x43,0x00,0x56,0x00,0x40,0x10,0x2a,0xb0,0x06,0x3c,
15010x10,0x00,0xc3,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x07,0x24,0xff,0x00,0x04,0x31,
15020x23,0x03,0x87,0x10,0x25,0xb0,0x02,0x3c,0x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,
15030x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,
15040xff,0x00,0x02,0x24,0x41,0x00,0xc6,0x34,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,
15050xff,0x00,0x44,0x30,0x0e,0x00,0x87,0x10,0x68,0x15,0x62,0x26,0xec,0x63,0xa4,0xa0,
15060x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,
15070x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,
15080xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0xec,0x63,0xe3,0xa0,0x68,0x15,0x62,0x26,
15090xec,0x63,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
15100x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,
15110x00,0x00,0x48,0xac,0x75,0x17,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
15120xff,0x00,0x02,0x24,0x22,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,
15130x90,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
15140x21,0x30,0x60,0x00,0xec,0x63,0x08,0xa2,0x24,0x64,0x03,0xae,0x03,0x00,0x04,0x24,
15150x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x02,0x80,0x09,0x3c,
15160x7c,0x7e,0x27,0x91,0x02,0x80,0x08,0x3c,0x6c,0x7e,0x05,0x8d,0xfc,0x4a,0x06,0x8e,
15170x01,0x00,0x02,0x3c,0x00,0x80,0x42,0x34,0x40,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,
15180x24,0x30,0xc2,0x00,0x80,0x00,0xa5,0x34,0x00,0x26,0x07,0x00,0x25,0xb0,0x02,0x3c,
15190x25,0x20,0x85,0x00,0x80,0x03,0x42,0x34,0x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,
15200x00,0x00,0x66,0xac,0x6c,0x7e,0x05,0xad,0x7c,0x7e,0x27,0xa1,0xfc,0x4a,0x06,0xae,
15210x68,0x15,0x62,0x26,0x00,0x4b,0x43,0x8c,0x01,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,
15220x00,0x4b,0x43,0xac,0x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x02,0x00,0x03,0x3c,
15230x24,0x10,0x52,0x00,0x24,0x10,0x43,0x00,0x5a,0x00,0x40,0x10,0x2a,0xb0,0x06,0x3c,
15240x14,0x00,0xc3,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x07,0x24,0xff,0x00,0x04,0x31,
15250xcc,0x02,0x87,0x10,0x25,0xb0,0x02,0x3c,0x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,
15260x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,
15270xff,0x00,0x02,0x24,0x42,0x00,0xc6,0x34,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,
15280xff,0x00,0x44,0x30,0x0e,0x00,0x87,0x10,0x68,0x15,0x62,0x26,0xf0,0x63,0xa4,0xa0,
15290x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,
15300x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,
15310xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0xf0,0x63,0xe3,0xa0,0x68,0x15,0x62,0x26,
15320xf0,0x63,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
15330x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,
15340x00,0x00,0x48,0xac,0xd1,0x17,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
15350xff,0x00,0x02,0x24,0x25,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,
15360x9c,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
15370x21,0x30,0x60,0x00,0xf0,0x63,0x08,0xa2,0x30,0x64,0x03,0xae,0x04,0x00,0x04,0x24,
15380x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x02,0x80,0x0a,0x3c,
15390x7c,0x7e,0x47,0x91,0x02,0x80,0x09,0x3c,0x6c,0x7e,0x25,0x8d,0xfc,0x4a,0x06,0x8e,
15400x06,0x00,0x02,0x3c,0x20,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,0x24,0x30,0xc2,0x00,
15410x00,0x01,0xa5,0x34,0x25,0xb0,0x03,0x3c,0x04,0x00,0x02,0x3c,0x00,0x26,0x07,0x00,
15420x26,0x88,0x22,0x02,0xb0,0x03,0x68,0x34,0x25,0x20,0x85,0x00,0x80,0x03,0x63,0x34,
15430x41,0xb0,0x02,0x3c,0x00,0x00,0x64,0xac,0x00,0x00,0x46,0xac,0x6c,0x7e,0x25,0xad,
15440x7c,0x7e,0x47,0xa1,0xfc,0x4a,0x06,0xae,0x00,0x00,0x11,0xad,0x68,0x15,0x62,0x26,
15450x00,0x4b,0x43,0x8c,0x02,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,
15460x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x04,0x00,0x03,0x3c,0x24,0x10,0x52,0x00,
15470x24,0x10,0x51,0x00,0x24,0x10,0x43,0x00,0x58,0x00,0x40,0x10,0x25,0xb0,0x03,0x3c,
15480xb0,0x03,0x62,0x34,0x2a,0xb0,0x09,0x3c,0x00,0x00,0x51,0xac,0x18,0x00,0x26,0x35,
15490x00,0x00,0xc8,0x8c,0xff,0x00,0x07,0x24,0xff,0x00,0x04,0x31,0x3a,0x02,0x87,0x10,
15500x04,0x00,0x02,0x24,0x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,0x00,0x80,0x02,0x3c,
15510x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,0xff,0x00,0x02,0x24,
15520x43,0x00,0x26,0x35,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,0xff,0x00,0x44,0x30,
15530x0e,0x00,0x87,0x10,0x68,0x15,0x62,0x26,0xf4,0x63,0xa4,0xa0,0x00,0x00,0xc2,0x90,
15540xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,0x21,0x38,0xa0,0x00,
15550x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,0xfd,0xff,0x62,0x14,
15560xff,0x00,0x44,0x30,0xf4,0x63,0xe3,0xa0,0x68,0x15,0x62,0x26,0xf4,0x63,0x43,0x90,
15570x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,0x0c,0x00,0x68,0x8c,
15580x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,0x00,0x00,0x48,0xac,
15590x34,0x18,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0xc2,0xac,0xff,0x00,0x02,0x24,
15600x21,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,0x9c,0x64,0x05,0x8e,
15610x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,
15620xf4,0x63,0x08,0xa2,0x30,0x64,0x03,0xae,0x04,0x00,0x04,0x24,0x20,0x00,0x07,0x24,
15630x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x02,0x80,0x09,0x3c,0x7c,0x7e,0x27,0x91,
15640x02,0x80,0x08,0x3c,0x6c,0x7e,0x05,0x8d,0xfc,0x4a,0x06,0x8e,0x06,0x00,0x02,0x3c,
15650x10,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,0x24,0x30,0xc2,0x00,0x00,0x01,0xa5,0x34,
15660x00,0x26,0x07,0x00,0x25,0xb0,0x02,0x3c,0x25,0x20,0x85,0x00,0x80,0x03,0x42,0x34,
15670x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,0x00,0x00,0x66,0xac,0x6c,0x7e,0x05,0xad,
15680x7c,0x7e,0x27,0xa1,0xfc,0x4a,0x06,0xae,0x68,0x15,0x62,0x26,0x00,0x4b,0x43,0x8c,
15690x04,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,0x68,0x15,0x65,0x26,
15700xfc,0x4a,0xa2,0x8c,0x08,0x00,0x03,0x3c,0x24,0x10,0x52,0x00,0x24,0x10,0x43,0x00,
15710x5a,0x00,0x40,0x10,0x2a,0xb0,0x06,0x3c,0x1c,0x00,0xc3,0x34,0x00,0x00,0x68,0x8c,
15720xff,0x00,0x07,0x24,0xff,0x00,0x04,0x31,0x13,0x02,0x87,0x10,0x25,0xb0,0x02,0x3c,
15730x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,0x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,
15740x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,0xff,0x00,0x02,0x24,0x44,0x00,0xc6,0x34,
15750x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,0xff,0x00,0x44,0x30,0x0e,0x00,0x87,0x10,
15760x68,0x15,0x62,0x26,0xf8,0x63,0xa4,0xa0,0x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,
15770xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,0x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,
15780x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,0xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,
15790xf8,0x63,0xe3,0xa0,0x68,0x15,0x62,0x26,0xf8,0x63,0x43,0x90,0x20,0xb0,0x02,0x3c,
15800x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,0x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,
15810xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,0x00,0x00,0x48,0xac,0x8f,0x18,0x00,0x08,
15820xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,0xff,0x00,0x02,0x24,0x25,0x00,0x82,0x10,
15830x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,0xa8,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,
15840x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,0xf8,0x63,0x08,0xa2,
15850x3c,0x64,0x03,0xae,0x05,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,
15860x10,0x00,0xa0,0xaf,0x02,0x80,0x0a,0x3c,0x7c,0x7e,0x47,0x91,0x02,0x80,0x09,0x3c,
15870x6c,0x7e,0x25,0x8d,0xfc,0x4a,0x06,0x8e,0x18,0x00,0x02,0x3c,0x08,0x00,0xe7,0x34,
15880x27,0x10,0x02,0x00,0x24,0x30,0xc2,0x00,0x00,0x02,0xa5,0x34,0x25,0xb0,0x03,0x3c,
15890x10,0x00,0x02,0x3c,0x00,0x26,0x07,0x00,0x26,0x88,0x22,0x02,0xb0,0x03,0x68,0x34,
15900x25,0x20,0x85,0x00,0x80,0x03,0x63,0x34,0x41,0xb0,0x02,0x3c,0x00,0x00,0x64,0xac,
15910x00,0x00,0x46,0xac,0x6c,0x7e,0x25,0xad,0x7c,0x7e,0x47,0xa1,0xfc,0x4a,0x06,0xae,
15920x00,0x00,0x11,0xad,0x68,0x15,0x62,0x26,0x00,0x4b,0x43,0x8c,0x08,0x00,0x04,0x3c,
15930x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,0x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,
15940x10,0x00,0x03,0x3c,0x24,0x10,0x52,0x00,0x24,0x10,0x51,0x00,0x24,0x10,0x43,0x00,
15950x58,0x00,0x40,0x10,0x25,0xb0,0x06,0x3c,0xb0,0x03,0xc2,0x34,0x2a,0xb0,0x09,0x3c,
15960x00,0x00,0x51,0xac,0x20,0x00,0x23,0x35,0x00,0x00,0x68,0x8c,0xff,0x00,0x07,0x24,
15970xff,0x00,0x04,0x31,0x80,0x01,0x87,0x10,0x90,0x03,0xc2,0x34,0x00,0x80,0x02,0x31,
15980x23,0x00,0x40,0x14,0x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,
15990x21,0x00,0x40,0x10,0xff,0x00,0x02,0x24,0x45,0x00,0x26,0x35,0x00,0x00,0xc2,0x90,
16000x00,0x00,0x00,0x00,0xff,0x00,0x44,0x30,0x0e,0x00,0x87,0x10,0x68,0x15,0x62,0x26,
16010x04,0x64,0xa4,0xa0,0x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,
16020x07,0x00,0x83,0x10,0x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,
16030x21,0x18,0x80,0x00,0xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0x04,0x64,0xe3,0xa0,
16040x68,0x15,0x62,0x26,0x04,0x64,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,
16050x21,0x18,0x62,0x00,0x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,
16060xff,0x00,0x04,0x31,0x00,0x00,0x48,0xac,0xf2,0x18,0x00,0x08,0xff,0x00,0x02,0x24,
16070x00,0x00,0x62,0xac,0xff,0x00,0x02,0x24,0x21,0x00,0x82,0x10,0x68,0x15,0x70,0x26,
16080xff,0x00,0x03,0x31,0xa8,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,
16090x21,0x18,0x62,0x00,0x21,0x30,0x60,0x00,0x04,0x64,0x08,0xa2,0x3c,0x64,0x03,0xae,
16100x05,0x00,0x04,0x24,0x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,
16110x02,0x80,0x09,0x3c,0x7c,0x7e,0x27,0x91,0x02,0x80,0x08,0x3c,0x6c,0x7e,0x05,0x8d,
16120xfc,0x4a,0x06,0x8e,0x18,0x00,0x02,0x3c,0x01,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,
16130x24,0x30,0xc2,0x00,0x00,0x02,0xa5,0x34,0x00,0x26,0x07,0x00,0x25,0xb0,0x02,0x3c,
16140x25,0x20,0x85,0x00,0x80,0x03,0x42,0x34,0x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,
16150x00,0x00,0x66,0xac,0x6c,0x7e,0x05,0xad,0x7c,0x7e,0x27,0xa1,0xfc,0x4a,0x06,0xae,
16160x68,0x15,0x62,0x26,0x00,0x4b,0x43,0x8c,0x10,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,
16170x00,0x4b,0x43,0xac,0x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x20,0x00,0x03,0x3c,
16180x24,0x10,0x52,0x00,0x24,0x10,0x43,0x00,0x5a,0x00,0x40,0x10,0x2a,0xb0,0x06,0x3c,
16190x24,0x00,0xc3,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x07,0x24,0xff,0x00,0x04,0x31,
16200x28,0x01,0x87,0x10,0x25,0xb0,0x02,0x3c,0x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,
16210x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,
16220xff,0x00,0x02,0x24,0x46,0x00,0xc6,0x34,0x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,
16230xff,0x00,0x44,0x30,0x0e,0x00,0x87,0x10,0x68,0x15,0x62,0x26,0xfc,0x63,0xa4,0xa0,
16240x00,0x00,0xc2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,
16250x21,0x38,0xa0,0x00,0x21,0x28,0xc0,0x00,0x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,
16260xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0xfc,0x63,0xe3,0xa0,0x68,0x15,0x62,0x26,
16270xfc,0x63,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
16280x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,
16290x00,0x00,0x48,0xac,0x4d,0x19,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
16300xff,0x00,0x02,0x24,0x25,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,
16310xb4,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
16320x21,0x30,0x60,0x00,0xfc,0x63,0x08,0xa2,0x48,0x64,0x03,0xae,0x06,0x00,0x04,0x24,
16330x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x02,0x80,0x0a,0x3c,
16340x7c,0x7e,0x47,0x91,0x02,0x80,0x09,0x3c,0x6c,0x7e,0x25,0x8d,0xfc,0x4a,0x06,0x8e,
16350x60,0x00,0x02,0x3c,0x04,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,0x24,0x30,0xc2,0x00,
16360x00,0x04,0xa5,0x34,0x25,0xb0,0x03,0x3c,0x40,0x00,0x02,0x3c,0x00,0x26,0x07,0x00,
16370x26,0x88,0x22,0x02,0xb0,0x03,0x68,0x34,0x25,0x20,0x85,0x00,0x80,0x03,0x63,0x34,
16380x41,0xb0,0x02,0x3c,0x00,0x00,0x64,0xac,0x00,0x00,0x46,0xac,0x6c,0x7e,0x25,0xad,
16390x7c,0x7e,0x47,0xa1,0xfc,0x4a,0x06,0xae,0x00,0x00,0x11,0xad,0x68,0x15,0x62,0x26,
16400x00,0x4b,0x43,0x8c,0x20,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,
16410x68,0x15,0x65,0x26,0xfc,0x4a,0xa2,0x8c,0x40,0x00,0x03,0x3c,0x24,0x10,0x52,0x00,
16420x24,0x10,0x51,0x00,0x24,0x10,0x43,0x00,0x5a,0x00,0x40,0x10,0x68,0x15,0x70,0x26,
16430x25,0xb0,0x02,0x3c,0x2a,0xb0,0x07,0x3c,0xb0,0x03,0x42,0x34,0x00,0x00,0x51,0xac,
16440x28,0x00,0xe3,0x34,0x00,0x00,0x68,0x8c,0xff,0x00,0x06,0x24,0xff,0x00,0x04,0x31,
16450xc9,0x00,0x86,0x10,0x25,0xbd,0x02,0x3c,0x00,0x80,0x02,0x31,0x23,0x00,0x40,0x14,
16460x00,0x80,0x02,0x3c,0x00,0xff,0x02,0x3c,0x24,0x10,0x02,0x01,0x21,0x00,0x40,0x10,
16470xff,0x00,0x02,0x24,0x47,0x00,0xe7,0x34,0x00,0x00,0xe2,0x90,0x00,0x00,0x00,0x00,
16480xff,0x00,0x44,0x30,0x0e,0x00,0x86,0x10,0x68,0x15,0x62,0x26,0x00,0x64,0xa4,0xa0,
16490x00,0x00,0xe2,0x90,0xff,0x00,0x83,0x30,0xff,0x00,0x44,0x30,0x07,0x00,0x83,0x10,
16500x21,0x30,0xa0,0x00,0x21,0x28,0xe0,0x00,0x00,0x00,0xa2,0x90,0x21,0x18,0x80,0x00,
16510xfd,0xff,0x62,0x14,0xff,0x00,0x44,0x30,0x00,0x64,0xc3,0xa0,0x68,0x15,0x62,0x26,
16520x00,0x64,0x43,0x90,0x20,0xb0,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
16530x0c,0x00,0x68,0x8c,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0xff,0x00,0x04,0x31,
16540x00,0x00,0x48,0xac,0xb1,0x19,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
16550xff,0x00,0x02,0x24,0x21,0x00,0x82,0x10,0x68,0x15,0x70,0x26,0xff,0x00,0x03,0x31,
16560xb4,0x64,0x05,0x8e,0x20,0x10,0x02,0x3c,0x00,0x1a,0x03,0x00,0x21,0x18,0x62,0x00,
16570x21,0x30,0x60,0x00,0x00,0x64,0x08,0xa2,0x48,0x64,0x03,0xae,0x06,0x00,0x04,0x24,
16580x20,0x00,0x07,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xa0,0xaf,0x02,0x80,0x09,0x3c,
16590x7c,0x7e,0x27,0x91,0x02,0x80,0x08,0x3c,0x6c,0x7e,0x05,0x8d,0xfc,0x4a,0x06,0x8e,
16600x60,0x00,0x02,0x3c,0x02,0x00,0xe7,0x34,0x27,0x10,0x02,0x00,0x24,0x30,0xc2,0x00,
16610x00,0x04,0xa5,0x34,0x00,0x26,0x07,0x00,0x25,0xb0,0x02,0x3c,0x25,0x20,0x85,0x00,
16620x80,0x03,0x42,0x34,0x41,0xb0,0x03,0x3c,0x00,0x00,0x44,0xac,0x00,0x00,0x66,0xac,
16630x6c,0x7e,0x05,0xad,0x7c,0x7e,0x27,0xa1,0xfc,0x4a,0x06,0xae,0x68,0x15,0x62,0x26,
16640x00,0x4b,0x43,0x8c,0x40,0x00,0x04,0x3c,0x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,
16650x68,0x15,0x70,0x26,0xfc,0x4a,0x06,0x8e,0x00,0x04,0x11,0x3c,0x24,0x10,0xd2,0x00,
16660x24,0x10,0x51,0x00,0x4c,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x24,0x28,0xd2,0x00,
16670x00,0x08,0x04,0x3c,0x24,0x10,0xa4,0x00,0x08,0x00,0x40,0x10,0x80,0x00,0x07,0x3c,
16680x00,0x4b,0x03,0x8e,0x25,0xb0,0x02,0x3c,0xb0,0x03,0x42,0x34,0x26,0x18,0x64,0x00,
16690x00,0x00,0x44,0xac,0x00,0x4b,0x03,0xae,0x80,0x00,0x07,0x3c,0x24,0x10,0xa7,0x00,
16700x21,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x00,0x4b,0x03,0x8e,0x25,0xb0,0x08,0x3c,
16710xb0,0x03,0x09,0x35,0x2a,0xb0,0x02,0x3c,0x00,0x00,0x23,0xad,0x36,0x00,0x42,0x34,
16720x00,0x00,0x43,0x90,0x23,0xb0,0x04,0x3c,0xff,0x1f,0x02,0x3c,0xc0,0x18,0x03,0x00,
16730xf0,0x07,0x63,0x30,0x5c,0x65,0x05,0x8e,0x21,0x18,0x64,0x00,0xff,0xff,0x42,0x34,
16740x24,0x18,0x62,0x00,0x59,0x00,0x65,0x10,0x60,0x65,0x03,0xae,0x02,0x80,0x05,0x3c,
16750x6c,0x7e,0xa3,0x8c,0x27,0x20,0x07,0x00,0x24,0x20,0xc4,0x00,0x00,0x08,0x63,0x34,
16760x41,0xb0,0x02,0x3c,0x00,0x00,0x23,0xad,0x00,0x00,0x44,0xac,0x6c,0x7e,0xa3,0xac,
16770xfc,0x4a,0x04,0xae,0x68,0x15,0x62,0x26,0x00,0x4b,0x43,0x8c,0x80,0x00,0x04,0x3c,
16780x26,0x18,0x64,0x00,0x00,0x4b,0x43,0xac,0x68,0x15,0x66,0x26,0xfc,0x4a,0xc3,0x8c,
16790x00,0x01,0x04,0x3c,0x24,0x28,0x72,0x00,0x24,0x10,0xa4,0x00,0x06,0x00,0x40,0x10,
16800x25,0xb0,0x02,0x3c,0x00,0x4b,0xc3,0x8c,0xb0,0x03,0x42,0x34,0x26,0x18,0x64,0x00,
16810x00,0x00,0x44,0xac,0x00,0x4b,0xc3,0xac,0x00,0x02,0x04,0x3c,0x24,0x10,0xa4,0x00,
16820x06,0x00,0x40,0x10,0x25,0xb0,0x03,0x3c,0x00,0x4b,0xc2,0x8c,0xb0,0x03,0x63,0x34,
16830x26,0x10,0x44,0x00,0x00,0x4b,0xc2,0xac,0x00,0x00,0x64,0xac,0x28,0x00,0xbf,0x8f,
16840x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,0x18,0x00,0xb0,0x8f,
16850x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,0x5b,0x4e,0x00,0x0c,0x07,0x00,0x04,0x24,
16860x00,0x4b,0x03,0x8e,0xfc,0x4a,0x06,0x8e,0x25,0xb0,0x02,0x3c,0x26,0x18,0x71,0x00,
16870xb0,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0xdf,0x19,0x00,0x08,0x00,0x4b,0x03,0xae,
16880x56,0x01,0x42,0x35,0x00,0x00,0x43,0x94,0x00,0x00,0x00,0x00,0x44,0xfb,0x60,0x10,
16890x00,0x00,0x00,0x00,0x5b,0x4e,0x00,0x0c,0x07,0x00,0x04,0x24,0x7d,0x15,0x00,0x08,
16900x68,0x15,0x66,0x26,0x00,0x00,0xa2,0xac,0x48,0x16,0x00,0x08,0xff,0x00,0x02,0x24,
16910x00,0x00,0x62,0xac,0x85,0x16,0x00,0x08,0xff,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
16920xc2,0x16,0x00,0x08,0xff,0x00,0x02,0x24,0x90,0x03,0x63,0x34,0x00,0x00,0x62,0xac,
16930x57,0x18,0x00,0x08,0x68,0x15,0x62,0x26,0x00,0x00,0x40,0xac,0x15,0x19,0x00,0x08,
16940x68,0x15,0x62,0x26,0x02,0x00,0x03,0x24,0x90,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
16950x74,0x19,0x00,0x08,0x68,0x15,0x62,0x26,0x01,0x00,0x03,0x24,0x90,0x03,0x42,0x34,
16960x00,0x00,0x43,0xac,0xd4,0x19,0x00,0x08,0x68,0x15,0x62,0x26,0xd0,0x03,0x03,0x35,
16970x80,0x00,0x02,0x24,0x00,0x00,0x62,0xac,0x0a,0x1a,0x00,0x08,0x68,0x15,0x62,0x26,
16980x25,0xb0,0x02,0x3c,0x07,0x00,0x03,0x24,0x90,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
16990x68,0x15,0x63,0x26,0x00,0x4b,0x62,0x8c,0x00,0x00,0x00,0x00,0x00,0x20,0x42,0x38,
17000xe2,0x16,0x00,0x08,0x00,0x4b,0x62,0xac,0x25,0xb0,0x02,0x3c,0x07,0x00,0x03,0x24,
17010x90,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x68,0x15,0x63,0x26,0x00,0x4b,0x62,0x8c,
17020x00,0x00,0x00,0x00,0x00,0x80,0x42,0x38,0x40,0x17,0x00,0x08,0x00,0x4b,0x62,0xac,
17030x06,0x00,0x03,0x24,0x90,0x03,0x42,0x34,0x00,0x00,0x43,0xac,0x99,0x17,0x00,0x08,
17040x68,0x15,0x62,0x26,0x05,0x00,0x03,0x24,0x90,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
17050xf8,0x17,0x00,0x08,0x68,0x15,0x62,0x26,0x03,0x00,0x03,0x24,0x90,0x03,0x42,0x34,
17060x00,0x00,0x43,0xac,0xb6,0x18,0x00,0x08,0x68,0x15,0x62,0x26,0x25,0xb0,0x0d,0x3c,
17070x00,0x80,0x02,0x3c,0x18,0x03,0xa4,0x35,0xfc,0x69,0x42,0x24,0x02,0x80,0x03,0x3c,
17080x41,0xb0,0x08,0x3c,0x00,0x00,0x82,0xac,0x68,0x15,0x6a,0x24,0x0a,0x00,0x02,0x35,
17090x00,0x00,0x44,0x94,0x0a,0x4b,0x43,0x95,0x08,0x4b,0x4b,0x95,0x25,0x18,0x64,0x00,
17100xff,0xff,0x6c,0x30,0x24,0x10,0x8b,0x01,0x02,0x00,0x42,0x30,0x4d,0x00,0x40,0x10,
17110x02,0x00,0x64,0x38,0x02,0x00,0x02,0x24,0xc0,0x03,0xa3,0x35,0x00,0x00,0x62,0xac,
17120x0a,0x4b,0x44,0xa5,0x24,0x38,0x8b,0x01,0x04,0x00,0xe2,0x30,0x0a,0x00,0x40,0x10,
17130x08,0x00,0xe2,0x30,0x0a,0x4b,0x43,0x95,0x0c,0x00,0x04,0x35,0xc0,0x03,0xa5,0x35,
17140x04,0x00,0x63,0x38,0x04,0x00,0x02,0x24,0x00,0x00,0x86,0x8c,0x00,0x00,0xa2,0xac,
17150x0a,0x4b,0x43,0xa5,0x08,0x00,0xe2,0x30,0x08,0x00,0x40,0x10,0x10,0x00,0xe2,0x30,
17160x0a,0x4b,0x42,0x95,0xc0,0x03,0xa4,0x35,0x08,0x00,0x03,0x24,0x08,0x00,0x42,0x38,
17170x00,0x00,0x83,0xac,0x0a,0x4b,0x42,0xa5,0x10,0x00,0xe2,0x30,0x08,0x00,0x40,0x10,
17180x20,0x00,0xe2,0x30,0x0a,0x4b,0x42,0x95,0xc0,0x03,0xa4,0x35,0x10,0x00,0x03,0x24,
17190x10,0x00,0x42,0x38,0x00,0x00,0x83,0xac,0x0a,0x4b,0x42,0xa5,0x20,0x00,0xe2,0x30,
17200x08,0x00,0x40,0x10,0x80,0x00,0xe2,0x30,0x0a,0x4b,0x42,0x95,0xc0,0x03,0xa4,0x35,
17210x20,0x00,0x03,0x24,0x20,0x00,0x42,0x38,0x00,0x00,0x83,0xac,0x0a,0x4b,0x42,0xa5,
17220x80,0x00,0xe2,0x30,0x15,0x00,0x40,0x10,0x24,0x10,0x8b,0x01,0x02,0x80,0x09,0x3c,
17230x0a,0x4b,0x46,0x95,0x6c,0x7e,0x25,0x8d,0x08,0x00,0x02,0x3c,0x7f,0xff,0x04,0x24,
17240x24,0x20,0x64,0x01,0x25,0x28,0xa2,0x00,0x80,0x00,0xc6,0x38,0xb0,0x03,0xa7,0x35,
17250x08,0x00,0x08,0x35,0xc0,0x03,0xa3,0x35,0x80,0x00,0x02,0x24,0x00,0x00,0x62,0xac,
17260x21,0x58,0x80,0x00,0x00,0x00,0xe5,0xac,0x0a,0x4b,0x46,0xa5,0x6c,0x7e,0x25,0xad,
17270x00,0x00,0x04,0xa5,0x08,0x4b,0x44,0xa5,0x24,0x10,0x8b,0x01,0x00,0x30,0x42,0x30,
17280x06,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x0a,0x4b,0x42,0x95,0x00,0x00,0x00,0x00,
17290x00,0x10,0x42,0x38,0x00,0x20,0x42,0x34,0x0a,0x4b,0x42,0xa5,0x08,0x00,0xe0,0x03,
17300x00,0x00,0x00,0x00,0x95,0x1a,0x00,0x08,0x0a,0x4b,0x43,0xa5,0xf8,0xff,0xbd,0x27,
17310x04,0x00,0xb1,0xaf,0x00,0x00,0xb0,0xaf,0x00,0x40,0x02,0x40,0x00,0x68,0x08,0x40,
17320x00,0x70,0x02,0x40,0x00,0x60,0x09,0x40,0x25,0xb0,0x05,0x3c,0x00,0x80,0x02,0x3c,
17330x18,0x03,0xa3,0x34,0x7c,0x6b,0x42,0x24,0x00,0x00,0x62,0xac,0x80,0x00,0x87,0x8c,
17340x7c,0x02,0xa2,0x34,0x84,0x02,0xa3,0x34,0x88,0x02,0xa6,0x34,0x00,0x00,0x47,0xac,
17350x00,0x00,0x68,0xac,0x00,0x00,0xc9,0xac,0x74,0x00,0x83,0x8c,0x8c,0x02,0xa2,0x34,
17360x90,0x02,0xa7,0x34,0x00,0x00,0x43,0xac,0x08,0x00,0x86,0x8c,0x94,0x02,0xa8,0x34,
17370x98,0x02,0xa9,0x34,0x00,0x00,0xe6,0xac,0x0c,0x00,0x82,0x8c,0x9c,0x02,0xa6,0x34,
17380xa0,0x02,0xa7,0x34,0x00,0x00,0x02,0xad,0x10,0x00,0x83,0x8c,0xa4,0x02,0xa8,0x34,
17390xa8,0x02,0xaa,0x34,0x00,0x00,0x23,0xad,0x14,0x00,0x82,0x8c,0xac,0x02,0xa9,0x34,
17400xb0,0x02,0xab,0x34,0x00,0x00,0xc2,0xac,0x18,0x00,0x83,0x8c,0xb4,0x02,0xa6,0x34,
17410xb8,0x02,0xac,0x34,0x00,0x00,0xe3,0xac,0x1c,0x00,0x82,0x8c,0xbc,0x02,0xa7,0x34,
17420xc0,0x02,0xad,0x34,0x00,0x00,0x02,0xad,0x20,0x00,0x83,0x8c,0xc4,0x02,0xa8,0x34,
17430xc8,0x02,0xae,0x34,0x00,0x00,0x43,0xad,0x24,0x00,0x82,0x8c,0xcc,0x02,0xaa,0x34,
17440xd0,0x02,0xaf,0x34,0x00,0x00,0x22,0xad,0x28,0x00,0x83,0x8c,0xd4,0x02,0xa9,0x34,
17450xd8,0x02,0xb0,0x34,0x00,0x00,0x63,0xad,0x2c,0x00,0x82,0x8c,0x70,0x02,0xab,0x34,
17460x74,0x02,0xb1,0x34,0x00,0x00,0xc2,0xac,0x30,0x00,0x83,0x8c,0x78,0x02,0xa5,0x34,
17470x00,0x00,0x83,0xad,0x34,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xe2,0xac,
17480x38,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xad,0x3c,0x00,0x82,0x8c,
17490x00,0x00,0x00,0x00,0x00,0x00,0x02,0xad,0x40,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,
17500x00,0x00,0xc3,0xad,0x44,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0xad,
17510x48,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xe3,0xad,0x4c,0x00,0x82,0x8c,
17520x00,0x00,0x00,0x00,0x00,0x00,0x22,0xad,0x50,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,
17530x00,0x00,0x03,0xae,0x54,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0xad,
17540x58,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x23,0xae,0x5c,0x00,0x82,0x8c,
17550x00,0x00,0x00,0x00,0x00,0x00,0xa2,0xac,0x42,0x1b,0x00,0x08,0x00,0x00,0x00,0x00,
17560x00,0x80,0x1b,0x3c,0x10,0x6d,0x7b,0x27,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,
17570x00,0x00,0x5b,0xaf,0x21,0xd8,0xa0,0x03,0x82,0xda,0x1b,0x00,0x80,0xda,0x1b,0x00,
17580x08,0x00,0x7b,0x27,0x04,0x00,0x61,0xaf,0x08,0x00,0x62,0xaf,0x0c,0x00,0x63,0xaf,
17590x10,0x00,0x64,0xaf,0x14,0x00,0x65,0xaf,0x18,0x00,0x66,0xaf,0x1c,0x00,0x67,0xaf,
17600x20,0x00,0x68,0xaf,0x24,0x00,0x69,0xaf,0x28,0x00,0x6a,0xaf,0x2c,0x00,0x6b,0xaf,
17610x30,0x00,0x6c,0xaf,0x34,0x00,0x6d,0xaf,0x38,0x00,0x6e,0xaf,0x3c,0x00,0x6f,0xaf,
17620x12,0x40,0x00,0x00,0x10,0x48,0x00,0x00,0x00,0x70,0x0a,0x40,0x40,0x00,0x70,0xaf,
17630x44,0x00,0x71,0xaf,0x48,0x00,0x72,0xaf,0x4c,0x00,0x73,0xaf,0x50,0x00,0x74,0xaf,
17640x54,0x00,0x75,0xaf,0x58,0x00,0x76,0xaf,0x5c,0x00,0x77,0xaf,0x60,0x00,0x78,0xaf,
17650x64,0x00,0x79,0xaf,0x68,0x00,0x7c,0xaf,0x6c,0x00,0x7d,0xaf,0x70,0x00,0x7e,0xaf,
17660x74,0x00,0x7f,0xaf,0x78,0x00,0x68,0xaf,0x7c,0x00,0x69,0xaf,0x80,0x00,0x6a,0xaf,
17670x00,0x68,0x1a,0x40,0x25,0xb0,0x1b,0x3c,0x1c,0x03,0x7b,0x37,0x00,0x00,0x00,0x00,
17680x00,0x00,0x7a,0xaf,0x7f,0x00,0x5b,0x33,0x30,0x00,0x60,0x13,0x00,0x00,0x00,0x00,
17690x25,0xb0,0x1b,0x3c,0x30,0x03,0x7b,0x37,0x00,0x00,0x00,0x00,0x00,0x00,0x7a,0xaf,
17700x00,0x00,0x00,0x00,0x21,0xd8,0xa0,0x03,0x82,0xda,0x1b,0x00,0x80,0xda,0x1b,0x00,
17710x08,0x00,0x7b,0x27,0x04,0x00,0x61,0xaf,0x08,0x00,0x62,0xaf,0x0c,0x00,0x63,0xaf,
17720x10,0x00,0x64,0xaf,0x14,0x00,0x65,0xaf,0x18,0x00,0x66,0xaf,0x1c,0x00,0x67,0xaf,
17730x20,0x00,0x68,0xaf,0x24,0x00,0x69,0xaf,0x28,0x00,0x6a,0xaf,0x2c,0x00,0x6b,0xaf,
17740x30,0x00,0x6c,0xaf,0x34,0x00,0x6d,0xaf,0x38,0x00,0x6e,0xaf,0x3c,0x00,0x6f,0xaf,
17750x12,0x40,0x00,0x00,0x10,0x48,0x00,0x00,0x00,0x70,0x0a,0x40,0x40,0x00,0x70,0xaf,
17760x44,0x00,0x71,0xaf,0x48,0x00,0x72,0xaf,0x4c,0x00,0x73,0xaf,0x50,0x00,0x74,0xaf,
17770x54,0x00,0x75,0xaf,0x58,0x00,0x76,0xaf,0x5c,0x00,0x77,0xaf,0x60,0x00,0x78,0xaf,
17780x64,0x00,0x79,0xaf,0x68,0x00,0x7c,0xaf,0x6c,0x00,0x7d,0xaf,0x70,0x00,0x7e,0xaf,
17790x74,0x00,0x7f,0xaf,0x78,0x00,0x68,0xaf,0x7c,0x00,0x69,0xaf,0x80,0x00,0x6a,0xaf,
17800xdf,0x1a,0x00,0x08,0x21,0x20,0x60,0x03,0x00,0x00,0x00,0x00,0x25,0xb0,0x08,0x3c,
17810x20,0x03,0x08,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x1a,0xad,0x00,0x04,0x5b,0x33,
17820x0a,0x00,0x60,0x13,0x00,0x00,0x00,0x00,0x00,0x80,0x08,0x3c,0x74,0x55,0x08,0x25,
17830x00,0x00,0x00,0x00,0x25,0xb0,0x1b,0x3c,0x24,0x03,0x7b,0x37,0x00,0x00,0x00,0x00,
17840x00,0x00,0x68,0xaf,0x09,0xf8,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x08,0x5b,0x33,
17850x25,0xb0,0x08,0x3c,0x28,0x03,0x08,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x1b,0xad,
17860x06,0x00,0x60,0x13,0x00,0x00,0x00,0x00,0x00,0x80,0x08,0x3c,0xfc,0x69,0x08,0x25,
17870x00,0x00,0x00,0x00,0x09,0xf8,0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x80,0x1a,0x3c,
17880x6c,0x7e,0x5a,0x27,0x04,0x00,0x5b,0x97,0x25,0xb0,0x08,0x3c,0x30,0x03,0x08,0x35,
17890x00,0x00,0x00,0x00,0x00,0x00,0x1b,0xad,0x18,0x00,0x60,0x13,0x00,0x00,0x00,0x00,
17900x08,0xec,0x9b,0x27,0x00,0x00,0x00,0x00,0x04,0x00,0x61,0x8f,0xfc,0x03,0x70,0x7b,
17910x7c,0x00,0x62,0x7b,0xbc,0x00,0x64,0x7b,0xfc,0x00,0x66,0x7b,0x3c,0x01,0x68,0x7b,
17920x13,0x00,0x00,0x02,0x11,0x00,0x20,0x02,0x7c,0x01,0x6a,0x7b,0xbc,0x01,0x6c,0x7b,
17930xfc,0x01,0x6e,0x7b,0x3c,0x02,0x70,0x7b,0x7c,0x02,0x72,0x7b,0xbc,0x02,0x74,0x7b,
17940xfc,0x02,0x76,0x7b,0x3c,0x03,0x78,0x7b,0x7c,0x03,0x7c,0x7b,0xbc,0x03,0x7e,0x7b,
17950x80,0x00,0x7b,0x8f,0x2f,0x1c,0x00,0x08,0x00,0x00,0x00,0x00,0x21,0xd8,0xa0,0x03,
17960x82,0xda,0x1b,0x00,0x80,0xda,0x1b,0x00,0x08,0x00,0x7b,0x27,0x08,0x00,0x5b,0xaf,
17970xfc,0xef,0x9d,0x27,0x00,0x00,0x4a,0x8f,0x00,0x00,0x00,0x00,0x21,0x00,0x40,0x11,
17980x00,0x00,0x00,0x00,0x02,0x80,0x08,0x3c,0xcc,0x7d,0x08,0x25,0x21,0x48,0x00,0x00,
17990x21,0x58,0x00,0x00,0x01,0x00,0x6b,0x25,0x1a,0x00,0x40,0x11,0x24,0x70,0x4b,0x01,
18000x14,0x00,0xc0,0x11,0x01,0x00,0x04,0x24,0x00,0x00,0x00,0x00,0x04,0x00,0x44,0xa3,
18010x26,0x50,0x4b,0x01,0x00,0x00,0x4a,0xaf,0x80,0x80,0x09,0x00,0x21,0x80,0x08,0x02,
18020x00,0x00,0x10,0x8e,0x00,0x00,0x00,0x00,0x09,0xf8,0x00,0x02,0x00,0x00,0x00,0x00,
18030x00,0x80,0x1b,0x3c,0xe8,0x6f,0x7b,0x27,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,
18040x00,0x00,0x5b,0xaf,0x02,0x80,0x1a,0x3c,0x6c,0x7e,0x5a,0x27,0xe1,0xff,0x00,0x10,
18050x00,0x00,0x00,0x00,0x01,0x00,0x29,0x25,0x40,0x58,0x0b,0x00,0xf2,0x1b,0x00,0x08,
18060x00,0x00,0x00,0x00,0x02,0x80,0x1b,0x3c,0x6c,0x7e,0x7b,0x27,0x21,0x60,0x00,0x00,
18070x04,0x00,0x6c,0xa7,0x08,0x00,0x7a,0x8f,0x00,0x00,0x00,0x00,0xf8,0xff,0x5a,0x27,
18080x00,0x00,0x5a,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0x5a,0x27,0x84,0x00,0x44,0x8f,
18090x00,0x00,0x00,0x00,0xf9,0xff,0x80,0x10,0x00,0x00,0x00,0x00,0x04,0x00,0x41,0x8f,
18100xfc,0x03,0x50,0x7b,0x7c,0x00,0x42,0x7b,0xbc,0x00,0x44,0x7b,0xfc,0x00,0x46,0x7b,
18110x3c,0x01,0x48,0x7b,0x13,0x00,0x00,0x02,0x11,0x00,0x20,0x02,0x7c,0x01,0x4a,0x7b,
18120xbc,0x01,0x4c,0x7b,0xfc,0x01,0x4e,0x7b,0x3c,0x02,0x50,0x7b,0x7c,0x02,0x52,0x7b,
18130xbc,0x02,0x54,0x7b,0xfc,0x02,0x56,0x7b,0x3c,0x03,0x58,0x7b,0x7c,0x03,0x5c,0x7b,
18140xbc,0x03,0x5e,0x7b,0x80,0x00,0x5b,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0x60,0x03,
18150x10,0x00,0x00,0x42,0x00,0x60,0x05,0x40,0x42,0x28,0x05,0x00,0x40,0x28,0x05,0x00,
18160x00,0x60,0x85,0x40,0x04,0x00,0x81,0xac,0x08,0x00,0x82,0xac,0x0c,0x00,0x83,0xac,
18170x20,0x00,0x88,0xac,0x24,0x00,0x89,0xac,0x28,0x00,0x8a,0xac,0x2c,0x00,0x8b,0xac,
18180x30,0x00,0x8c,0xac,0x34,0x00,0x8d,0xac,0x38,0x00,0x8e,0xac,0x3c,0x00,0x8f,0xac,
18190x12,0x40,0x00,0x00,0x10,0x48,0x00,0x00,0x40,0x00,0x90,0xac,0x44,0x00,0x91,0xac,
18200x48,0x00,0x92,0xac,0x4c,0x00,0x93,0xac,0x50,0x00,0x94,0xac,0x54,0x00,0x95,0xac,
18210x58,0x00,0x96,0xac,0x5c,0x00,0x97,0xac,0x60,0x00,0x98,0xac,0x64,0x00,0x99,0xac,
18220x68,0x00,0x9c,0xac,0x6c,0x00,0x9d,0xac,0x70,0x00,0x9e,0xac,0x74,0x00,0x9f,0xac,
18230x78,0x00,0x88,0xac,0x7c,0x00,0x89,0xac,0x80,0x00,0x9f,0xac,0xf8,0xff,0x84,0x24,
18240x00,0x00,0x84,0x8c,0x00,0x00,0x00,0x00,0x08,0x00,0x84,0x24,0x84,0x00,0x86,0x8c,
18250x00,0x00,0x00,0x00,0xf9,0xff,0xc0,0x10,0x00,0x00,0x00,0x00,0x21,0xd8,0x80,0x00,
18260x01,0x00,0xba,0x24,0x04,0x00,0x61,0x8f,0xfc,0x03,0x70,0x7b,0x7c,0x00,0x62,0x7b,
18270xbc,0x00,0x64,0x7b,0xfc,0x00,0x66,0x7b,0x3c,0x01,0x68,0x7b,0x13,0x00,0x00,0x02,
18280x11,0x00,0x20,0x02,0x7c,0x01,0x6a,0x7b,0xbc,0x01,0x6c,0x7b,0xfc,0x01,0x6e,0x7b,
18290x3c,0x02,0x70,0x7b,0x7c,0x02,0x72,0x7b,0xbc,0x02,0x74,0x7b,0xfc,0x02,0x76,0x7b,
18300x3c,0x03,0x78,0x7b,0x7c,0x03,0x7c,0x7b,0xbc,0x03,0x7e,0x7b,0x80,0x00,0x7b,0x8f,
18310x00,0x00,0x00,0x00,0x08,0x00,0x60,0x03,0x00,0x60,0x9a,0x40,0x00,0x60,0x05,0x40,
18320x42,0x28,0x05,0x00,0x40,0x28,0x05,0x00,0x00,0x60,0x85,0x40,0x04,0x00,0x81,0xac,
18330x08,0x00,0x82,0xac,0x0c,0x00,0x83,0xac,0x20,0x00,0x88,0xac,0x24,0x00,0x89,0xac,
18340x28,0x00,0x8a,0xac,0x2c,0x00,0x8b,0xac,0x30,0x00,0x8c,0xac,0x34,0x00,0x8d,0xac,
18350x38,0x00,0x8e,0xac,0x3c,0x00,0x8f,0xac,0x12,0x40,0x00,0x00,0x10,0x48,0x00,0x00,
18360x40,0x00,0x90,0xac,0x44,0x00,0x91,0xac,0x48,0x00,0x92,0xac,0x4c,0x00,0x93,0xac,
18370x50,0x00,0x94,0xac,0x54,0x00,0x94,0xac,0x58,0x00,0x96,0xac,0x5c,0x00,0x96,0xac,
18380x60,0x00,0x98,0xac,0x64,0x00,0x99,0xac,0x68,0x00,0x9c,0xac,0x6c,0x00,0x9d,0xac,
18390x70,0x00,0x9e,0xac,0x78,0x00,0x88,0xac,0x7c,0x00,0x89,0xac,0x80,0x00,0x9f,0xac,
18400x84,0x00,0x80,0xac,0xf8,0xff,0x84,0x24,0x00,0x00,0x84,0x8c,0x00,0x00,0x00,0x00,
18410x08,0x00,0x84,0x24,0x84,0x00,0x86,0x8c,0xfa,0xff,0xc0,0x10,0x00,0x00,0x00,0x00,
18420x21,0xd8,0x80,0x00,0x01,0x00,0xba,0x24,0x04,0x00,0x61,0x8f,0xfc,0x03,0x70,0x7b,
18430x7c,0x00,0x62,0x7b,0xbc,0x00,0x64,0x7b,0xfc,0x00,0x66,0x7b,0x3c,0x01,0x68,0x7b,
18440x13,0x00,0x00,0x02,0x11,0x00,0x20,0x02,0x7c,0x01,0x6a,0x7b,0xbc,0x01,0x6c,0x7b,
18450xfc,0x01,0x6e,0x7b,0x3c,0x02,0x70,0x7b,0x7c,0x02,0x72,0x7b,0xbc,0x02,0x74,0x7b,
18460xfc,0x02,0x76,0x7b,0x3c,0x03,0x78,0x7b,0x7c,0x03,0x7c,0x7b,0xbc,0x03,0x7e,0x7b,
18470x80,0x00,0x7b,0x8f,0x08,0x00,0x60,0x03,0x00,0x60,0x9a,0x40,0x00,0x00,0x00,0x00,
18480x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18490x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18500x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18510x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18520x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18530x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18540x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18550x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18560x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18570x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18580x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18590x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18600x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18610x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18620x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18630x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18640x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18650x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18660x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18670xc6,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x1b,0x3c,0x00,0x00,0x7b,0x27,
18680x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,0x00,0x00,0x5b,0xaf,0x00,0x00,0x05,0x24,
18690x03,0x00,0xa4,0x24,0x00,0xa0,0x80,0x40,0x00,0xa0,0x84,0x40,0x01,0x80,0x04,0x3c,
18700x98,0x03,0x84,0x24,0x08,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18710x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18720x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18730x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18740x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18750x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18760x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18770x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18780x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18790x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18800x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18810x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18820x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18830x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18840x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18850x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18860x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18870x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18880x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18890x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18900x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18910x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18920x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18930x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18940x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18950x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18960x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18970x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18980x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
18990x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19010x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19020x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19030x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19040x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19050x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19060x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19070x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19080x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19090x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19100x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19110x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19120x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19130x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19140x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19150x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19160x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19170x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19180x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19190x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19200x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19210x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19220x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19230x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19240x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
19250x01,0x80,0x1b,0x3c,0x98,0x03,0x7b,0x27,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,
19260x00,0x00,0x5b,0xaf,0x02,0x80,0x1a,0x3c,0x00,0x00,0x5a,0x27,0xfc,0x03,0x5d,0x27,
19270x02,0x80,0x1c,0x3c,0x00,0x14,0x9c,0x27,0x00,0xf0,0x08,0x3c,0x00,0x0c,0x08,0x35,
19280x00,0x60,0x88,0x40,0x02,0x80,0x04,0x3c,0x00,0x00,0x84,0x24,0xff,0x7f,0x05,0x3c,
19290xff,0xff,0xa5,0x34,0x24,0x20,0x85,0x00,0x00,0x20,0x84,0x4c,0xff,0xff,0x05,0x34,
19300x21,0x28,0xa4,0x00,0x00,0x28,0x85,0x4c,0x00,0x80,0x04,0x3c,0x00,0x00,0x84,0x24,
19310xff,0x7f,0x05,0x3c,0xff,0xff,0xa5,0x34,0x24,0x20,0x85,0x00,0x00,0x00,0x84,0x4c,
19320xff,0x7f,0x06,0x24,0x21,0x30,0xc4,0x00,0x24,0x30,0xc5,0x00,0x00,0x08,0x86,0x4c,
19330x00,0xa0,0x04,0x40,0x10,0x00,0x84,0x34,0x00,0xa0,0x84,0x40,0x01,0x80,0x1b,0x3c,
19340x24,0x04,0x7b,0x27,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,0x00,0x00,0x5b,0xaf,
19350x00,0x00,0x00,0x00,0x25,0xb0,0x04,0x3c,0x44,0x00,0x84,0x34,0x00,0x00,0x85,0x84,
19360x20,0x00,0x06,0x24,0x25,0x28,0xa6,0x00,0x00,0x00,0x85,0xa4,0x01,0x80,0x1b,0x3c,
19370x54,0x04,0x7b,0x27,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x27,0x00,0x00,0x5b,0xaf,
19380x25,0xb0,0x04,0x3c,0x44,0x00,0x84,0x34,0x00,0x00,0x85,0x8c,0x00,0x00,0x00,0x00,
19390x10,0x00,0xa5,0x30,0xfc,0xff,0xa0,0x10,0x00,0x00,0x00,0x00,0xff,0x1f,0x07,0x3c,
19400xff,0xff,0xe7,0x34,0x02,0x80,0x05,0x3c,0x88,0x7d,0xa5,0x24,0xff,0xff,0xa5,0x30,
19410x40,0xb0,0x04,0x3c,0x25,0x28,0xa4,0x00,0x24,0x28,0xa7,0x00,0x21,0x30,0x00,0x00,
19420x43,0xb0,0x02,0x3c,0x00,0x80,0x04,0x3c,0x40,0x00,0x84,0x34,0x00,0x00,0x45,0xac,
19430x04,0x00,0x46,0xac,0x08,0x00,0x44,0xac,0x4e,0x58,0x00,0x08,0x00,0x00,0x00,0x00,
19440x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x24,0xff,0xff,0x42,0x24,
19450xff,0xff,0x41,0x04,0xff,0xff,0x42,0x24,0x08,0x00,0xe0,0x03,0x01,0x00,0x42,0x24,
19460x00,0x60,0x02,0x40,0x01,0x00,0x41,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
19470x08,0x00,0xe0,0x03,0x00,0x00,0x82,0xac,0x00,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,
19480x21,0x18,0x40,0x00,0x00,0x60,0x83,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x82,0xac,
19490x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x08,0x00,0xe0,0x03,
19500x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
19510x00,0x60,0x81,0x40,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x03,0x3c,
19520x25,0xb0,0x02,0x3c,0x44,0x05,0x63,0x24,0x18,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
19530x04,0x00,0x85,0x8c,0x00,0x80,0x03,0x3c,0x01,0x00,0x02,0x24,0x25,0x28,0xa3,0x00,
19540x00,0x00,0xa4,0x8c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x03,0x3c,
19550x25,0xb0,0x02,0x3c,0x74,0x05,0x63,0x24,0x18,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
19560x04,0x00,0x82,0x8c,0x02,0x00,0x83,0x94,0x00,0x80,0x07,0x3c,0x25,0x28,0x47,0x00,
19570x00,0x00,0xa2,0x8c,0x10,0x00,0x02,0x24,0x13,0x00,0x62,0x10,0x11,0x00,0x66,0x28,
19580x06,0x00,0xc0,0x10,0x20,0x00,0x02,0x24,0x08,0x00,0x02,0x24,0x17,0x00,0x62,0x10,
19590x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0xfd,0xff,0x62,0x14,
19600x00,0x00,0x00,0x00,0x08,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xac,
19610x04,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x25,0x10,0x47,0x00,0x00,0x00,0x42,0x8c,
19620x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0x08,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,
19630x00,0x00,0xa2,0xa4,0x04,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,0x25,0x18,0x67,0x00,
19640x00,0x00,0x62,0x94,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0x08,0x00,0x82,0x8c,
19650x00,0x00,0x00,0x00,0x00,0x00,0xa2,0xa0,0x04,0x00,0x83,0x8c,0x00,0x00,0x00,0x00,
19660x25,0x18,0x67,0x00,0x00,0x00,0x62,0x90,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
19670xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0x02,0x80,0x11,0x3c,0x1c,0x00,0xbf,0xaf,
19680x18,0x00,0xb2,0xaf,0x10,0x00,0xb0,0xaf,0x68,0x15,0x31,0x26,0xe4,0x64,0x30,0x96,
19690x02,0x80,0x02,0x3c,0x01,0x80,0x03,0x3c,0x25,0x80,0x02,0x02,0x25,0xb0,0x02,0x3c,
19700x38,0x06,0x63,0x24,0x18,0x03,0x42,0x34,0x60,0x00,0x04,0x26,0x80,0x00,0x05,0x26,
19710x00,0x00,0x43,0xac,0xab,0x45,0x00,0x0c,0x03,0x00,0x06,0x24,0x21,0x20,0x00,0x02,
19720x21,0x28,0x00,0x00,0x97,0x45,0x00,0x0c,0x08,0x00,0x06,0x24,0xe4,0x64,0x22,0x8e,
19730x0c,0x00,0x03,0x24,0x0c,0x00,0x43,0xae,0x08,0x00,0x42,0xae,0x12,0x00,0x02,0x24,
19740x14,0x00,0x42,0xae,0x21,0x20,0x40,0x02,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,
19750x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x8b,0x07,0x00,0x08,0x20,0x00,0xbd,0x27,
19760x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19770x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19780x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19790x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19800x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19810x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
19820x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19830x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19840x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19850x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
19860x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
19870x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19880x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19890x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
19900x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
19910x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,0x02,0x80,0x02,0x3c,0x21,0x48,0x80,0x00,
19920x68,0x15,0x48,0x24,0x21,0x38,0x00,0x00,0x21,0x28,0x27,0x01,0x00,0x00,0xa2,0x90,
19930x21,0x20,0xe8,0x00,0x01,0x00,0xe7,0x24,0x38,0x4c,0x82,0xa0,0x1e,0x00,0xa3,0x90,
19940x1e,0x00,0xe6,0x28,0x56,0x4c,0x83,0xa0,0x3c,0x00,0xa2,0x90,0x00,0x00,0x00,0x00,
19950x74,0x4c,0x82,0xa0,0x5a,0x00,0xa3,0x90,0xf3,0xff,0xc0,0x14,0x92,0x4c,0x83,0xa0,
19960x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
19970x20,0xbd,0x03,0x3c,0x58,0x00,0x63,0x34,0x00,0x00,0x62,0x90,0x0f,0x27,0x07,0x24,
19980x20,0x00,0x42,0x34,0x00,0x00,0x62,0xa0,0xff,0xff,0xe7,0x24,0xff,0xff,0xe1,0x04,
19990xff,0xff,0xe7,0x24,0x62,0xbd,0x04,0x3c,0x24,0x10,0x82,0x34,0x00,0x00,0x40,0xa0,
20000x28,0x10,0x83,0x34,0x0c,0x11,0x86,0x34,0x0e,0x00,0x02,0x24,0x00,0x00,0x60,0xa0,
20010x00,0x11,0x85,0x34,0x00,0x00,0xc2,0xa0,0x00,0x00,0xa7,0x8c,0xdf,0xff,0x02,0x24,
20020x10,0x00,0x86,0x34,0x24,0x38,0xe2,0x00,0x49,0x0c,0x03,0x24,0xcf,0xff,0x02,0x24,
20030x00,0x00,0xc3,0xac,0x04,0x00,0x84,0x34,0x00,0x00,0xa7,0xac,0x24,0x38,0xe2,0x00,
20040x41,0x0c,0x02,0x24,0x00,0x00,0xa7,0xac,0x00,0x00,0x80,0xac,0x00,0x00,0xc2,0xac,
20050x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0xd0,0xff,0xbd,0x27,0x25,0xb0,0x03,0x3c,
20060x01,0x80,0x02,0x3c,0xb0,0x03,0x68,0x34,0x1c,0x00,0xb1,0xaf,0x18,0x03,0x63,0x34,
20070xd8,0xff,0x91,0x24,0xa0,0x08,0x42,0x24,0x00,0x00,0x62,0xac,0x28,0x00,0xbf,0xaf,
20080x00,0x00,0x11,0xad,0x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x18,0x00,0xb0,0xaf,
20090x02,0x80,0x13,0x3c,0x00,0x00,0x23,0x96,0x68,0x15,0x73,0x26,0xff,0xff,0x32,0x32,
20100x40,0x10,0x02,0x3c,0x78,0x64,0x65,0x8e,0x25,0x90,0x42,0x02,0x02,0x80,0x10,0x3c,
20110x8c,0x96,0x10,0x26,0x20,0x00,0x42,0x26,0x00,0x00,0x03,0xad,0x20,0x00,0x06,0x24,
20120x00,0x00,0x02,0xad,0x21,0x38,0x00,0x02,0x0c,0x00,0x03,0xae,0x0a,0x00,0x04,0x24,
20130x64,0x01,0x00,0x0c,0x08,0x00,0x02,0xae,0x04,0x00,0x23,0x8e,0xff,0xe0,0x02,0x24,
20140x28,0x00,0x04,0x24,0x24,0x18,0x62,0x00,0x00,0x10,0x63,0x34,0x02,0x00,0x24,0xa2,
20150x04,0x00,0x23,0xae,0x0c,0x00,0x02,0x8e,0x0a,0x00,0x04,0x24,0xf8,0xff,0x42,0x24,
20160x4d,0x01,0x00,0x0c,0x00,0x00,0x22,0xa6,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
20170x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x0c,0x00,0x07,0x8e,0x20,0x10,0x06,0x3c,
20180x21,0x28,0x40,0x02,0x20,0x00,0xe7,0x24,0x00,0xfe,0xc6,0x34,0xff,0xff,0xe7,0x30,
20190x01,0x00,0x11,0x24,0x0a,0x00,0x04,0x24,0x10,0x01,0x00,0x0c,0x10,0x00,0xb1,0xaf,
20200xd5,0x4a,0x63,0x92,0x2a,0xb0,0x10,0x3c,0x32,0x00,0x02,0x36,0x01,0x00,0x63,0x24,
20210x00,0x00,0x43,0xa0,0x4d,0x01,0x00,0x0c,0x0a,0x00,0x04,0x24,0xc9,0x64,0x62,0x92,
20220x00,0x00,0x00,0x00,0x01,0x00,0x42,0x24,0xc9,0x64,0x62,0xa2,0x00,0x60,0x01,0x40,
20230x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x01,0x00,0x10,0x36,0x00,0x00,0x11,0xa2,
20240x28,0x00,0xbf,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,
20250x18,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,
20260x25,0xb0,0x05,0x3c,0x01,0x80,0x03,0x3c,0x21,0x38,0x80,0x00,0x18,0x03,0xa2,0x34,
20270xe8,0x09,0x63,0x24,0x01,0x00,0x04,0x24,0x00,0x00,0x43,0xac,0x35,0x00,0xe4,0x10,
20280x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x10,0x20,0x08,0xa2,0x34,0x02,0x00,0x02,0x24,
20290x83,0x00,0xe2,0x10,0x03,0x00,0x02,0x24,0x5a,0x00,0xe2,0x10,0x00,0x00,0x00,0x00,
20300x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x02,0x80,0x03,0x3c,0x00,0x00,0x44,0x8c,
20310x68,0x15,0x66,0x24,0x70,0x08,0x02,0x24,0xe0,0x08,0x03,0x24,0x74,0x4b,0xc2,0xac,
20320x40,0x08,0x02,0x24,0x78,0x4b,0xc3,0xac,0x84,0x4b,0xc2,0xac,0x78,0x08,0x03,0x24,
20330x0c,0x08,0x02,0x24,0x88,0x4b,0xc3,0xac,0x8c,0x4b,0xc2,0xac,0x10,0x08,0x03,0x24,
20340x20,0x08,0x02,0x24,0x90,0x4b,0xc3,0xac,0x94,0x4b,0xc2,0xac,0x24,0x08,0x03,0x24,
20350x58,0x08,0x02,0x24,0x98,0x4b,0xc3,0xac,0x9c,0x4b,0xc2,0xac,0x50,0x0c,0x03,0x24,
20360x54,0x0c,0x02,0x24,0xa0,0x4b,0xc3,0xac,0xa4,0x4b,0xc2,0xac,0x14,0x0c,0x03,0x24,
20370x10,0x0c,0x02,0x24,0x60,0x08,0x05,0x24,0xa8,0x4b,0xc3,0xac,0xac,0x4b,0xc2,0xac,
20380x80,0x0c,0x03,0x24,0x84,0x0c,0x02,0x24,0x00,0x01,0x84,0x30,0xb4,0x4b,0xc2,0xac,
20390x80,0x4b,0xc5,0xac,0xb0,0x4b,0xc3,0xac,0x71,0x4b,0xc0,0xa0,0x7c,0x4b,0xc5,0xac,
20400x02,0x00,0x80,0x10,0xa0,0x08,0x02,0x24,0xb8,0x08,0x02,0x24,0x08,0x00,0xe0,0x03,
20410xb8,0x4b,0xc2,0xac,0x28,0x08,0xa2,0x34,0x02,0x80,0x03,0x3c,0x00,0x00,0x44,0x8c,
20420x68,0x15,0x66,0x24,0x70,0x08,0x02,0x24,0xe0,0x08,0x03,0x24,0x74,0x4b,0xc2,0xac,
20430x44,0x08,0x02,0x24,0x78,0x4b,0xc3,0xac,0x84,0x4b,0xc2,0xac,0x78,0x08,0x03,0x24,
20440x0c,0x08,0x02,0x24,0x88,0x4b,0xc3,0xac,0x8c,0x4b,0xc2,0xac,0x14,0x08,0x03,0x24,
20450x28,0x08,0x02,0x24,0x90,0x4b,0xc3,0xac,0x94,0x4b,0xc2,0xac,0x2c,0x08,0x03,0x24,
20460x58,0x08,0x02,0x24,0x98,0x4b,0xc3,0xac,0x9c,0x4b,0xc2,0xac,0x58,0x0c,0x03,0x24,
20470x5c,0x0c,0x02,0x24,0xa0,0x4b,0xc3,0xac,0xa4,0x4b,0xc2,0xac,0x1c,0x0c,0x03,0x24,
20480x18,0x0c,0x02,0x24,0x64,0x08,0x05,0x24,0xa8,0x4b,0xc3,0xac,0xac,0x4b,0xc2,0xac,
20490x88,0x0c,0x03,0x24,0x8c,0x0c,0x02,0x24,0x00,0x01,0x84,0x30,0xb4,0x4b,0xc2,0xac,
20500x71,0x4b,0xc7,0xa0,0x80,0x4b,0xc5,0xac,0xb0,0x4b,0xc3,0xac,0x7c,0x4b,0xc5,0xac,
20510xd6,0xff,0x80,0x10,0xa4,0x08,0x02,0x24,0xbc,0x08,0x02,0x24,0x08,0x00,0xe0,0x03,
20520xb8,0x4b,0xc2,0xac,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0xac,0x08,0x03,0x24,
20530xb8,0x4b,0x43,0xac,0x74,0x08,0x03,0x24,0xe4,0x08,0x04,0x24,0x74,0x4b,0x43,0xac,
20540x4c,0x08,0x03,0x24,0x78,0x4b,0x44,0xac,0x84,0x4b,0x43,0xac,0x7c,0x08,0x04,0x24,
20550x0c,0x08,0x03,0x24,0x88,0x4b,0x44,0xac,0x8c,0x4b,0x43,0xac,0x1c,0x08,0x04,0x24,
20560x38,0x08,0x03,0x24,0x90,0x4b,0x44,0xac,0x94,0x4b,0x43,0xac,0x3c,0x08,0x04,0x24,
20570x5c,0x08,0x03,0x24,0x98,0x4b,0x44,0xac,0x9c,0x4b,0x43,0xac,0x68,0x0c,0x04,0x24,
20580x6c,0x0c,0x03,0x24,0xa0,0x4b,0x44,0xac,0xa4,0x4b,0x43,0xac,0x2c,0x0c,0x04,0x24,
20590x28,0x0c,0x03,0x24,0x6c,0x08,0x05,0x24,0xa8,0x4b,0x44,0xac,0xac,0x4b,0x43,0xac,
20600x98,0x0c,0x04,0x24,0x9c,0x0c,0x03,0x24,0x71,0x4b,0x47,0xa0,0x80,0x4b,0x45,0xac,
20610xb0,0x4b,0x44,0xac,0xb4,0x4b,0x43,0xac,0x08,0x00,0xe0,0x03,0x7c,0x4b,0x45,0xac,
20620x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0xa8,0x08,0x03,0x24,0xb8,0x4b,0x43,0xac,
20630x74,0x08,0x03,0x24,0xe4,0x08,0x04,0x24,0x74,0x4b,0x43,0xac,0x48,0x08,0x03,0x24,
20640x78,0x4b,0x44,0xac,0x84,0x4b,0x43,0xac,0x7c,0x08,0x04,0x24,0x0c,0x08,0x03,0x24,
20650x88,0x4b,0x44,0xac,0x8c,0x4b,0x43,0xac,0x18,0x08,0x04,0x24,0x30,0x08,0x03,0x24,
20660x90,0x4b,0x44,0xac,0x94,0x4b,0x43,0xac,0x34,0x08,0x04,0x24,0x5c,0x08,0x03,0x24,
20670x98,0x4b,0x44,0xac,0x9c,0x4b,0x43,0xac,0x60,0x0c,0x04,0x24,0x64,0x0c,0x03,0x24,
20680xa0,0x4b,0x44,0xac,0xa4,0x4b,0x43,0xac,0x24,0x0c,0x04,0x24,0x20,0x0c,0x03,0x24,
20690x68,0x08,0x05,0x24,0xa8,0x4b,0x44,0xac,0xac,0x4b,0x43,0xac,0x90,0x0c,0x04,0x24,
20700x94,0x0c,0x03,0x24,0x71,0x4b,0x47,0xa0,0x80,0x4b,0x45,0xac,0xb0,0x4b,0x44,0xac,
20710xb4,0x4b,0x43,0xac,0x08,0x00,0xe0,0x03,0x7c,0x4b,0x45,0xac,0x36,0x43,0x00,0x08,
20720x21,0x18,0x00,0x00,0x20,0x00,0x62,0x2c,0x06,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
20730x06,0x10,0x64,0x00,0x01,0x00,0x42,0x30,0xfa,0xff,0x40,0x10,0x01,0x00,0x63,0x24,
20740xff,0xff,0x63,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,0xd8,0xff,0xbd,0x27,
20750x25,0xb0,0x02,0x3c,0x18,0x00,0xb2,0xaf,0x21,0x90,0x82,0x00,0xff,0xff,0x02,0x24,
20760x1c,0x00,0xb3,0xaf,0x14,0x00,0xb1,0xaf,0x20,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,
20770x21,0x88,0xa0,0x00,0x21,0x20,0xa0,0x00,0x21,0x18,0x40,0x02,0x10,0x00,0xa2,0x10,
20780x21,0x98,0xc0,0x00,0x00,0x00,0x50,0x8e,0x31,0x43,0x00,0x0c,0x00,0x00,0x00,0x00,
20790x04,0x10,0x53,0x00,0x27,0x18,0x11,0x00,0x25,0x18,0x62,0x00,0x24,0x18,0x70,0x00,
20800x00,0x00,0x43,0xae,0x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,
20810x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,
20820x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
20830x10,0x00,0xb0,0x8f,0x28,0x00,0xbd,0x27,0x00,0x00,0x66,0xac,0x08,0x00,0xe0,0x03,
20840x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,0x21,0x30,0x80,0x00,0xec,0x60,0x44,0x8c,
20850x3d,0x43,0x00,0x08,0xff,0xff,0x05,0x24,0xe0,0xff,0xbd,0x27,0x25,0xb0,0x02,0x3c,
20860x18,0x00,0xbf,0xaf,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x21,0x20,0x82,0x00,
20870x00,0x00,0x90,0x8c,0x21,0x88,0xa0,0x00,0x31,0x43,0x00,0x0c,0x21,0x20,0xa0,0x00,
20880x24,0x80,0x11,0x02,0x06,0x10,0x50,0x00,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,
20890x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0xd0,0xff,0xbd,0x27,
20900x14,0x00,0xb1,0xaf,0x02,0x80,0x11,0x3c,0x28,0x00,0xbf,0xaf,0x20,0x00,0xb4,0xaf,
20910x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,0x24,0x00,0xb5,0xaf,0x10,0x00,0xb0,0xaf,
20920x68,0x15,0x31,0x26,0x98,0x4b,0x22,0x8e,0x25,0xb0,0x12,0x3c,0x24,0x08,0x53,0x36,
20930x21,0x10,0x52,0x00,0x00,0x00,0x70,0x8e,0x00,0x00,0x55,0x8c,0x7f,0x80,0x03,0x3c,
20940xff,0x7f,0x02,0x3c,0xff,0xff,0x63,0x34,0xff,0xff,0x42,0x34,0x24,0x10,0x02,0x02,
20950x24,0x18,0xa3,0x02,0xc0,0x25,0x04,0x00,0x25,0x18,0x64,0x00,0x00,0x80,0x14,0x3c,
20960x00,0x00,0x62,0xae,0x01,0x00,0x04,0x24,0x84,0x0a,0x00,0x0c,0x25,0xa8,0x74,0x00,
20970x98,0x4b,0x22,0x8e,0x25,0x80,0x14,0x02,0x01,0x00,0x04,0x24,0x21,0x10,0x52,0x00,
20980x00,0x00,0x55,0xac,0x84,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xae,
20990x84,0x0a,0x00,0x0c,0x01,0x00,0x04,0x24,0xb8,0x4b,0x24,0x8e,0x0f,0x00,0x05,0x3c,
21000x28,0x00,0xbf,0x8f,0x24,0x00,0xb5,0x8f,0x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,
21010x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0xff,0xff,0xa5,0x34,
21020x68,0x43,0x00,0x08,0x30,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,
21030x02,0x80,0x11,0x3c,0x10,0x00,0xb0,0xaf,0x18,0x00,0xbf,0xaf,0x68,0x15,0x27,0x26,
21040x73,0x4b,0xe5,0x90,0x01,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,0xb0,0x0e,0x63,0x24,
21050x18,0x03,0x42,0x34,0x02,0x00,0x06,0x24,0x00,0x00,0x43,0xac,0x34,0x00,0xa6,0x10,
21060x21,0x80,0x80,0x00,0x03,0x00,0x03,0x24,0x3a,0x00,0xa3,0x10,0x2e,0x00,0x02,0x2e,
21070x10,0x00,0x02,0x2e,0x07,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0xff,0x00,0x04,0x32,
21080x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x79,0x43,0x00,0x08,
21090x20,0x00,0xbd,0x27,0xfa,0xff,0xa6,0x14,0xff,0x00,0x04,0x32,0x71,0x4b,0xe4,0x90,
21100x01,0x00,0x02,0x24,0x33,0x00,0x82,0x10,0x02,0x00,0x82,0x28,0x38,0x00,0x40,0x14,
21110x00,0x00,0x00,0x00,0x38,0x00,0x85,0x10,0x68,0x15,0x22,0x26,0x2e,0x00,0x83,0x10,
21120x00,0x00,0x00,0x00,0x00,0x08,0x04,0x24,0x68,0x43,0x00,0x0c,0xff,0xff,0x05,0x24,
21130xff,0xfc,0x06,0x3c,0xff,0xff,0xc6,0x34,0x24,0x30,0x46,0x00,0x00,0x08,0x04,0x24,
21140x3d,0x43,0x00,0x0c,0xff,0xff,0x05,0x24,0x68,0x15,0x22,0x26,0x71,0x4b,0x44,0x90,
21150x01,0x00,0x03,0x24,0x07,0x00,0x83,0x10,0x02,0x00,0x82,0x28,0x2c,0x00,0x40,0x14,
21160x02,0x00,0x02,0x24,0x2c,0x00,0x82,0x10,0x03,0x00,0x02,0x24,0xdb,0xff,0x82,0x14,
21170x00,0x00,0x00,0x00,0x68,0x15,0x22,0x26,0x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x3c,
21180x3d,0x43,0x00,0x0c,0x21,0x30,0x00,0x00,0xc2,0x43,0x00,0x08,0xff,0x00,0x04,0x32,
21190x25,0x00,0x82,0x2c,0xcc,0xff,0x40,0x14,0x03,0x00,0x03,0x24,0x18,0x00,0xbf,0x8f,
21200x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,
21210x20,0x00,0xbd,0x27,0xc7,0xff,0x40,0x14,0x10,0x00,0x02,0x2e,0x18,0x00,0xbf,0x8f,
21220x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,
21230x20,0x00,0xbd,0x27,0x68,0x15,0x22,0x26,0x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x3c,
21240x3d,0x43,0x00,0x0c,0x0f,0x00,0x06,0x24,0xd4,0x43,0x00,0x08,0x00,0x08,0x04,0x24,
21250xcc,0xff,0x80,0x14,0x68,0x15,0x22,0x26,0x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x24,
21260x3d,0x43,0x00,0x0c,0x0f,0x00,0x06,0x24,0xd4,0x43,0x00,0x08,0x00,0x08,0x04,0x24,
21270xb2,0xff,0x80,0x14,0x00,0x00,0x00,0x00,0x68,0x15,0x22,0x26,0x74,0x4b,0x44,0x8c,
21280x0f,0x00,0x05,0x24,0x3d,0x43,0x00,0x0c,0x21,0x30,0x00,0x00,0xc2,0x43,0x00,0x08,
21290xff,0x00,0x04,0x32,0xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0x02,0x80,0x11,0x3c,
21300x68,0x15,0x28,0x26,0x73,0x4b,0x06,0x91,0x01,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
21310x5c,0x10,0x63,0x24,0x18,0x03,0x42,0x34,0x02,0x00,0x07,0x24,0x18,0x00,0xb2,0xaf,
21320x10,0x00,0xb0,0xaf,0x1c,0x00,0xbf,0xaf,0x00,0x00,0x43,0xac,0x21,0x90,0xa0,0x00,
21330x39,0x00,0xc7,0x10,0xff,0x00,0x90,0x30,0x03,0x00,0x03,0x24,0x3f,0x00,0xc3,0x10,
21340x2e,0x00,0x02,0x2e,0x10,0x00,0x02,0x2e,0x0c,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
21350x0f,0x00,0x04,0x3c,0xff,0xff,0x84,0x34,0x24,0x20,0x44,0x02,0x00,0x15,0x10,0x00,
21360x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,
21370x25,0x20,0x44,0x00,0x63,0x43,0x00,0x08,0x20,0x00,0xbd,0x27,0xf5,0xff,0xc7,0x14,
21380x0f,0x00,0x04,0x3c,0x71,0x4b,0x04,0x91,0x01,0x00,0x02,0x24,0x33,0x00,0x82,0x10,
21390x02,0x00,0x82,0x28,0x38,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x38,0x00,0x86,0x10,
21400x68,0x15,0x22,0x26,0x2e,0x00,0x83,0x10,0x00,0x00,0x00,0x00,0x00,0x08,0x04,0x24,
21410x68,0x43,0x00,0x0c,0xff,0xff,0x05,0x24,0xff,0xfc,0x06,0x3c,0xff,0xff,0xc6,0x34,
21420x24,0x30,0x46,0x00,0x00,0x08,0x04,0x24,0x3d,0x43,0x00,0x0c,0xff,0xff,0x05,0x24,
21430x68,0x15,0x22,0x26,0x71,0x4b,0x44,0x90,0x01,0x00,0x03,0x24,0x07,0x00,0x83,0x10,
21440x02,0x00,0x82,0x28,0x2c,0x00,0x40,0x14,0x02,0x00,0x02,0x24,0x2c,0x00,0x82,0x10,
21450x03,0x00,0x02,0x24,0xd6,0xff,0x82,0x14,0x00,0x00,0x00,0x00,0x68,0x15,0x22,0x26,
21460x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x3c,0x3d,0x43,0x00,0x0c,0x21,0x30,0x00,0x00,
21470x2f,0x44,0x00,0x08,0x0f,0x00,0x04,0x3c,0x25,0x00,0x02,0x2e,0xc7,0xff,0x40,0x14,
21480x03,0x00,0x03,0x24,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
21490x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0xc1,0xff,0x40,0x14,
21500x00,0x00,0x00,0x00,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
21510x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0x68,0x15,0x22,0x26,
21520x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x3c,0x3d,0x43,0x00,0x0c,0x0f,0x00,0x06,0x24,
21530x46,0x44,0x00,0x08,0x00,0x08,0x04,0x24,0xcc,0xff,0x80,0x14,0x68,0x15,0x22,0x26,
21540x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x24,0x3d,0x43,0x00,0x0c,0x0f,0x00,0x06,0x24,
21550x46,0x44,0x00,0x08,0x00,0x08,0x04,0x24,0xad,0xff,0x80,0x14,0x00,0x00,0x00,0x00,
21560x68,0x15,0x22,0x26,0x74,0x4b,0x44,0x8c,0x0f,0x00,0x05,0x24,0x3d,0x43,0x00,0x0c,
21570x21,0x30,0x00,0x00,0x2f,0x44,0x00,0x08,0x0f,0x00,0x04,0x3c,0xe8,0xff,0xbd,0x27,
21580x10,0x00,0xb0,0xaf,0x21,0x80,0x80,0x00,0x14,0x00,0xbf,0xaf,0x79,0x43,0x00,0x0c,
21590x21,0x20,0x00,0x00,0x40,0x01,0x44,0x34,0x21,0x18,0x40,0x00,0x1f,0x00,0x02,0x2e,
21600x00,0x23,0x04,0x00,0x10,0x00,0x40,0x10,0x10,0x00,0x05,0x2e,0x00,0x01,0x64,0x34,
21610x06,0x00,0xa0,0x10,0x00,0x23,0x04,0x00,0x21,0x10,0x00,0x02,0x14,0x00,0xbf,0x8f,
21620x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,0x63,0x43,0x00,0x0c,
21630xf1,0xff,0x10,0x26,0x21,0x10,0x00,0x02,0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,
21640x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,0x63,0x43,0x00,0x0c,0xe2,0xff,0x10,0x26,
21650x21,0x10,0x00,0x02,0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,
21660x18,0x00,0xbd,0x27,0x25,0xb0,0x02,0x3c,0x27,0x38,0x05,0x00,0x21,0x40,0x82,0x00,
21670xff,0xff,0x02,0x24,0x07,0x00,0xa2,0x10,0x25,0x38,0xe6,0x00,0x00,0x00,0x02,0x8d,
21680x00,0x00,0x00,0x00,0x24,0x10,0xe2,0x00,0x00,0x00,0x02,0xad,0x08,0x00,0xe0,0x03,
21690x00,0x00,0x00,0x00,0x00,0x00,0x06,0xad,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21700x01,0x80,0x02,0x3c,0x25,0xb0,0x03,0x3c,0xe8,0x12,0x42,0x24,0x18,0x03,0x63,0x34,
21710xd8,0xff,0xbd,0x27,0x00,0x00,0x62,0xac,0x0f,0x00,0x02,0x3c,0x14,0x00,0xb1,0xaf,
21720xff,0xff,0x42,0x34,0x21,0x88,0xa0,0x00,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,
21730x20,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,0x21,0x90,0xc0,0x00,0x21,0x28,0xc0,0x00,
21740x0a,0x00,0x22,0x12,0x21,0x98,0x80,0x00,0xac,0x43,0x00,0x0c,0x00,0x00,0x00,0x00,
21750x21,0x20,0x20,0x02,0x31,0x43,0x00,0x0c,0x21,0x80,0x40,0x00,0x04,0x10,0x52,0x00,
21760x27,0x28,0x11,0x00,0x25,0x28,0xa2,0x00,0x24,0x28,0xb0,0x00,0xff,0x00,0x64,0x32,
21770x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
21780x10,0x00,0xb0,0x8f,0x17,0x44,0x00,0x08,0x28,0x00,0xbd,0x27,0x01,0x80,0x03,0x3c,
21790x25,0xb0,0x02,0x3c,0x74,0x13,0x63,0x24,0x18,0x03,0x42,0x34,0xe0,0xff,0xbd,0x27,
21800x00,0x00,0x43,0xac,0x18,0x00,0xbf,0xaf,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,
21810xac,0x43,0x00,0x0c,0x21,0x88,0xa0,0x00,0x21,0x80,0x40,0x00,0x31,0x43,0x00,0x0c,
21820x21,0x20,0x20,0x02,0x24,0x80,0x11,0x02,0x06,0x10,0x50,0x00,0x18,0x00,0xbf,0x8f,
21830x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
21840x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21850x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21860x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21870x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21880x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21890x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21900x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21910x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21920x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21930x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21940x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21950x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x01,0x00,0x02,0x24,
21960x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21970x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
21980x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
21990x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
22000x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
22010x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
22020xc8,0xff,0xbd,0x27,0x2c,0x00,0xb1,0xaf,0xff,0xff,0x05,0x24,0x21,0x88,0x80,0x00,
22030x02,0x00,0x06,0x24,0x10,0x00,0xa4,0x27,0x34,0x00,0xbf,0xaf,0x30,0x00,0xb2,0xaf,
22040x97,0x45,0x00,0x0c,0x28,0x00,0xb0,0xaf,0x08,0x00,0x30,0x96,0x02,0x80,0x02,0x3c,
22050x21,0x28,0x00,0x00,0x25,0x80,0x02,0x02,0x21,0x20,0x00,0x02,0x97,0x45,0x00,0x0c,
22060x10,0x00,0x06,0x24,0x20,0x00,0x02,0x96,0x24,0x00,0x04,0x26,0x10,0x00,0xa5,0x27,
22070x03,0xff,0x42,0x30,0xc8,0x00,0x42,0x34,0x20,0x00,0x02,0xa6,0x9f,0x45,0x00,0x0c,
22080x06,0x00,0x06,0x24,0x25,0xb0,0x03,0x3c,0x50,0x00,0x62,0x34,0x00,0x00,0x44,0x8c,
22090x54,0x00,0x65,0x34,0x58,0x00,0x66,0x34,0x18,0x00,0xa4,0xaf,0x00,0x00,0xa2,0x8c,
22100x5c,0x00,0x63,0x34,0x2a,0x00,0x04,0x26,0x1c,0x00,0xa2,0xaf,0x00,0x00,0xc7,0x8c,
22110x18,0x00,0xa5,0x27,0x06,0x00,0x06,0x24,0x20,0x00,0xa7,0xaf,0x00,0x00,0x62,0x8c,
22120x1a,0x00,0x12,0x24,0x9f,0x45,0x00,0x0c,0x24,0x00,0xa2,0xaf,0x30,0x00,0x04,0x26,
22130x20,0x00,0xa5,0x27,0x9f,0x45,0x00,0x0c,0x06,0x00,0x06,0x24,0x13,0x00,0x03,0x24,
22140x14,0x00,0x23,0xae,0x0c,0x00,0x32,0xae,0x08,0x00,0x05,0x8e,0x04,0x00,0x04,0x8e,
22150xff,0xdf,0x02,0x3c,0x14,0x00,0x06,0x8e,0xff,0xff,0x42,0x34,0x10,0x00,0x07,0x8e,
22160xff,0xe0,0x03,0x24,0x24,0x28,0xa2,0x00,0x00,0x40,0x02,0x3c,0x24,0x20,0x83,0x00,
22170x25,0x28,0xa2,0x00,0xff,0x81,0x03,0x24,0xfe,0xff,0x02,0x3c,0x24,0x30,0xc3,0x00,
22180xff,0xff,0x42,0x34,0x00,0x12,0x84,0x34,0x00,0x80,0x03,0x3c,0x24,0x20,0x82,0x00,
22190x25,0x38,0xe3,0x00,0x00,0x26,0xc6,0x34,0x80,0x00,0xa5,0x34,0x20,0x00,0x02,0x24,
22200x00,0x00,0x12,0xa6,0x10,0x00,0x07,0xae,0x02,0x00,0x02,0xa2,0x14,0x00,0x06,0xae,
22210x04,0x00,0x04,0xae,0x08,0x00,0x05,0xae,0x34,0x00,0xbf,0x8f,0x30,0x00,0xb2,0x8f,
22220x2c,0x00,0xb1,0x8f,0x28,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,
22230x93,0x45,0x00,0x08,0xff,0x00,0xa5,0x30,0x00,0x00,0x85,0xa0,0xff,0xff,0xc6,0x24,
22240x01,0x00,0x84,0x24,0xfc,0xff,0xc0,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
22250x00,0x00,0x00,0x00,0x05,0x00,0xc0,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0xac,
22260xff,0xff,0xc6,0x24,0xfd,0xff,0xc0,0x14,0x04,0x00,0x84,0x24,0x08,0x00,0xe0,0x03,
22270x00,0x00,0x00,0x00,0x21,0x38,0x80,0x00,0x08,0x00,0xc0,0x10,0xff,0xff,0xc3,0x24,
22280xff,0xff,0x06,0x24,0x00,0x00,0xa2,0x90,0xff,0xff,0x63,0x24,0x01,0x00,0xa5,0x24,
22290x00,0x00,0xe2,0xa0,0xfb,0xff,0x66,0x14,0x01,0x00,0xe7,0x24,0x08,0x00,0xe0,0x03,
22300x21,0x10,0x80,0x00,0x21,0x38,0x80,0x00,0x08,0x00,0xc0,0x10,0xff,0xff,0xc3,0x24,
22310xff,0xff,0x06,0x24,0x00,0x00,0xa2,0x8c,0xff,0xff,0x63,0x24,0x04,0x00,0xa5,0x24,
22320x00,0x00,0xe2,0xac,0xfb,0xff,0x66,0x14,0x04,0x00,0xe7,0x24,0x08,0x00,0xe0,0x03,
22330x21,0x10,0x80,0x00,0x2b,0x10,0xa4,0x00,0x0d,0x00,0x40,0x14,0xff,0xff,0x02,0x24,
22340xff,0xff,0xc6,0x24,0x08,0x00,0xc2,0x10,0x21,0x18,0x80,0x00,0xff,0xff,0x07,0x24,
22350x00,0x00,0xa2,0x90,0xff,0xff,0xc6,0x24,0x01,0x00,0xa5,0x24,0x00,0x00,0x62,0xa0,
22360xfb,0xff,0xc7,0x14,0x01,0x00,0x63,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x80,0x00,
22370x21,0x28,0xa6,0x00,0x21,0x18,0x86,0x00,0xff,0xff,0xc6,0x24,0xfa,0xff,0xc2,0x10,
22380x00,0x00,0x00,0x00,0xff,0xff,0x07,0x24,0xff,0xff,0xa5,0x24,0x00,0x00,0xa2,0x90,
22390xff,0xff,0x63,0x24,0xff,0xff,0xc6,0x24,0xfb,0xff,0xc7,0x14,0x00,0x00,0x62,0xa0,
22400x08,0x00,0xe0,0x03,0x21,0x10,0x80,0x00,0x0c,0x00,0xc0,0x10,0x00,0x00,0x00,0x00,
22410x00,0x00,0x82,0x90,0x00,0x00,0xa3,0x90,0x01,0x00,0x84,0x24,0x23,0x10,0x43,0x00,
22420x00,0x16,0x02,0x00,0x03,0x16,0x02,0x00,0x04,0x00,0x40,0x14,0x01,0x00,0xa5,0x24,
22430xff,0xff,0xc6,0x24,0xf6,0xff,0xc0,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
22440x21,0x10,0xc0,0x00,0xea,0x45,0x00,0x08,0x21,0x18,0x86,0x00,0x00,0x00,0x82,0x90,
22450x00,0x00,0x00,0x00,0x04,0x00,0x45,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x84,0x24,
22460xfa,0xff,0x83,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x80,0x00,
22470x09,0x00,0xc0,0x10,0xff,0xff,0xc3,0x24,0xff,0x00,0xa5,0x30,0xff,0xff,0x06,0x24,
22480x00,0x00,0x82,0x90,0xff,0xff,0x63,0x24,0x05,0x00,0x45,0x10,0x01,0x00,0x84,0x24,
22490xfb,0xff,0x66,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,
22500x08,0x00,0xe0,0x03,0xff,0xff,0x82,0x24,0x21,0x38,0x00,0x00,0x1f,0x00,0xc0,0x10,
22510x21,0x18,0x00,0x00,0x02,0x80,0x02,0x3c,0x80,0x95,0x4b,0x24,0x00,0x00,0x87,0x90,
22520x00,0x00,0xa3,0x90,0xff,0xff,0xc6,0x24,0x01,0x00,0x84,0x24,0x21,0x10,0xeb,0x00,
22530x16,0x00,0xe0,0x10,0x01,0x00,0xa5,0x24,0x14,0x00,0x60,0x10,0x21,0x48,0x6b,0x00,
22540x10,0x00,0xe3,0x10,0x20,0x00,0xe8,0x24,0x00,0x00,0x42,0x90,0x00,0x00,0x00,0x00,
22550x01,0x00,0x42,0x30,0x02,0x00,0x40,0x10,0x20,0x00,0x6a,0x24,0xff,0x00,0x07,0x31,
22560x00,0x00,0x22,0x91,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x30,0x02,0x00,0x40,0x10,
22570xff,0x00,0xe7,0x30,0xff,0x00,0x43,0x31,0xff,0x00,0x63,0x30,0x03,0x00,0xe3,0x14,
22580x00,0x00,0x00,0x00,0xe5,0xff,0xc0,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
22590x23,0x10,0xe3,0x00,0x21,0x18,0x80,0x00,0x00,0x00,0xa2,0x90,0x01,0x00,0xa5,0x24,
22600x00,0x00,0x82,0xa0,0xfc,0xff,0x40,0x14,0x01,0x00,0x84,0x24,0x08,0x00,0xe0,0x03,
22610x21,0x10,0x60,0x00,0x21,0x38,0x80,0x00,0xff,0xff,0x03,0x24,0xff,0xff,0xc6,0x24,
22620x06,0x00,0xc3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0xa2,0x90,0x01,0x00,0xa5,0x24,
22630x00,0x00,0x82,0xa0,0xf9,0xff,0x40,0x14,0x01,0x00,0x84,0x24,0x08,0x00,0xe0,0x03,
22640x21,0x10,0xe0,0x00,0x00,0x00,0x82,0x80,0x39,0x46,0x00,0x08,0x21,0x18,0x80,0x00,
22650x01,0x00,0x84,0x24,0x00,0x00,0x82,0x80,0x00,0x00,0x00,0x00,0xfc,0xff,0x40,0x14,
22660x00,0x00,0x00,0x00,0x00,0x00,0xa2,0x90,0x01,0x00,0xa5,0x24,0x00,0x00,0x82,0xa0,
22670xfc,0xff,0x40,0x14,0x01,0x00,0x84,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
22680x12,0x00,0xc0,0x10,0x21,0x18,0x80,0x00,0x00,0x00,0x82,0x80,0x4a,0x46,0x00,0x08,
22690x00,0x00,0x00,0x00,0x01,0x00,0x84,0x24,0x00,0x00,0x82,0x80,0x00,0x00,0x00,0x00,
22700xfc,0xff,0x40,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0xa2,0x90,0x01,0x00,0xa5,0x24,
22710x00,0x00,0x82,0xa0,0x05,0x00,0x40,0x10,0x01,0x00,0x84,0x24,0xff,0xff,0xc6,0x24,
22720xf9,0xff,0xc0,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xa0,0x08,0x00,0xe0,0x03,
22730x21,0x10,0x60,0x00,0x00,0x00,0x83,0x90,0x00,0x00,0xa2,0x90,0x01,0x00,0x84,0x24,
22740x23,0x10,0x62,0x00,0x00,0x16,0x02,0x00,0x03,0x16,0x02,0x00,0x03,0x00,0x40,0x14,
22750x01,0x00,0xa5,0x24,0xf7,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
22760x00,0x00,0x00,0x00,0x21,0x10,0x00,0x00,0x0b,0x00,0xc0,0x10,0x00,0x00,0x00,0x00,
22770x00,0x00,0xa2,0x90,0x00,0x00,0x83,0x90,0xff,0xff,0xc6,0x24,0x23,0x10,0x62,0x00,
22780x00,0x16,0x02,0x00,0x03,0x16,0x02,0x00,0x03,0x00,0x40,0x14,0x01,0x00,0xa5,0x24,
22790xf5,0xff,0x60,0x14,0x01,0x00,0x84,0x24,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
22800x00,0x00,0x83,0x80,0x00,0x2e,0x05,0x00,0x21,0x10,0x80,0x00,0x7b,0x46,0x00,0x08,
22810x03,0x2e,0x05,0x00,0x07,0x00,0x60,0x10,0x01,0x00,0x42,0x24,0x00,0x00,0x43,0x80,
22820x00,0x00,0x00,0x00,0xfb,0xff,0x65,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
22830x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x00,0x00,0x00,0x82,0x80,
22840x87,0x46,0x00,0x08,0x21,0x18,0x80,0x00,0x01,0x00,0x63,0x24,0x00,0x00,0x62,0x80,
22850x00,0x00,0x00,0x00,0xfc,0xff,0x40,0x14,0x23,0x10,0x64,0x00,0x08,0x00,0xe0,0x03,
22860x00,0x00,0x00,0x00,0xe0,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0x21,0x80,0xa0,0x00,
22870x14,0x00,0xb1,0xaf,0x18,0x00,0xbf,0xaf,0x21,0x88,0x80,0x00,0x81,0x46,0x00,0x0c,
22880x00,0x86,0x10,0x00,0x21,0x18,0x51,0x00,0x03,0x86,0x10,0x00,0x00,0x00,0x62,0x80,
22890x00,0x00,0x00,0x00,0x0a,0x00,0x50,0x10,0x21,0x10,0x60,0x00,0xff,0xff,0x63,0x24,
22900x2b,0x10,0x71,0x00,0xf9,0xff,0x40,0x10,0x21,0x10,0x00,0x00,0x18,0x00,0xbf,0x8f,
22910x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
22920x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,
22930x20,0x00,0xbd,0x27,0x21,0x30,0x80,0x00,0x0d,0x00,0xa0,0x10,0xff,0xff,0xa3,0x24,
22940x00,0x00,0x82,0x80,0x00,0x00,0x00,0x00,0x09,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
22950xff,0xff,0x05,0x24,0xff,0xff,0x63,0x24,0x05,0x00,0x65,0x10,0x01,0x00,0xc6,0x24,
22960x00,0x00,0xc2,0x80,0x00,0x00,0x00,0x00,0xfa,0xff,0x40,0x14,0x00,0x00,0x00,0x00,
22970x08,0x00,0xe0,0x03,0x23,0x10,0xc4,0x00,0x00,0x00,0x82,0x90,0x00,0x00,0x00,0x00,
22980x19,0x00,0x40,0x10,0x21,0x40,0x00,0x00,0x00,0x00,0xa9,0x80,0x00,0x00,0x00,0x00,
22990x17,0x00,0x20,0x11,0x21,0x30,0xa0,0x00,0x00,0x3e,0x02,0x00,0x03,0x3e,0x07,0x00,
23000x21,0x18,0x20,0x01,0x15,0x00,0xe3,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0xc6,0x24,
23010x00,0x00,0xc2,0x90,0x00,0x00,0x00,0x00,0x00,0x1e,0x02,0x00,0x03,0x1e,0x03,0x00,
23020xf8,0xff,0x60,0x14,0x00,0x16,0x02,0x00,0x03,0x16,0x02,0x00,0x06,0x00,0x40,0x10,
23030x00,0x00,0x00,0x00,0x01,0x00,0x84,0x24,0x00,0x00,0x82,0x90,0x00,0x00,0x00,0x00,
23040xeb,0xff,0x40,0x14,0x01,0x00,0x08,0x25,0x08,0x00,0xe0,0x03,0x21,0x10,0x00,0x01,
23050x00,0x00,0xa2,0x90,0xcc,0x46,0x00,0x08,0x00,0x16,0x02,0x00,0x00,0x00,0xc2,0x90,
23060xcc,0x46,0x00,0x08,0x00,0x16,0x02,0x00,0x00,0x00,0x87,0x90,0x00,0x00,0x00,0x00,
23070x14,0x00,0xe0,0x10,0x21,0x10,0x80,0x00,0x00,0x00,0xa4,0x90,0x00,0x00,0x00,0x00,
23080x00,0x1e,0x04,0x00,0x03,0x1e,0x03,0x00,0x09,0x00,0x60,0x10,0x21,0x30,0xa0,0x00,
23090x00,0x3e,0x07,0x00,0x03,0x3e,0x07,0x00,0x0b,0x00,0xe3,0x10,0x01,0x00,0xc6,0x24,
23100x00,0x00,0xc3,0x80,0x00,0x00,0x00,0x00,0xfb,0xff,0x60,0x14,0x00,0x00,0x00,0x00,
23110x01,0x00,0x42,0x24,0x00,0x00,0x47,0x90,0x00,0x00,0x00,0x00,0xf0,0xff,0xe0,0x14,
23120x00,0x00,0x00,0x00,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
23130xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x18,0x00,0xbf,0xaf,
23140x21,0x80,0x80,0x00,0x1d,0x00,0x80,0x10,0x21,0x88,0xa0,0x00,0xb8,0x46,0x00,0x0c,
23150x21,0x20,0x00,0x02,0x21,0x80,0x02,0x02,0x00,0x00,0x02,0x82,0x21,0x28,0x20,0x02,
23160x21,0x20,0x00,0x02,0x22,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0xdc,0x46,0x00,0x0c,
23170x00,0x00,0x00,0x00,0x05,0x00,0x40,0x10,0x21,0x18,0x40,0x00,0x00,0x00,0x42,0x80,
23180x00,0x00,0x00,0x00,0x0a,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,
23190xa8,0x96,0x43,0xac,0x21,0x18,0x00,0x02,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,
23200x10,0x00,0xb0,0x8f,0x21,0x10,0x60,0x00,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
23210x00,0x00,0x60,0xa0,0x0d,0x47,0x00,0x08,0x01,0x00,0x63,0x24,0x02,0x80,0x02,0x3c,
23220xa8,0x96,0x50,0x8c,0x00,0x00,0x00,0x00,0xf3,0xff,0x00,0x12,0x21,0x18,0x00,0x00,
23230xb8,0x46,0x00,0x0c,0x21,0x20,0x00,0x02,0x21,0x80,0x02,0x02,0x00,0x00,0x02,0x82,
23240x21,0x28,0x20,0x02,0x21,0x20,0x00,0x02,0xe0,0xff,0x40,0x14,0x21,0x18,0x00,0x00,
23250x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x02,0x80,0x02,0x3c,
23260xa8,0x96,0x40,0xac,0x20,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
23270xe0,0xff,0xbd,0x27,0x18,0x00,0xb2,0xaf,0x14,0x00,0xb1,0xaf,0x1c,0x00,0xbf,0xaf,
23280x10,0x00,0xb0,0xaf,0x00,0x00,0x90,0x8c,0x21,0x90,0x80,0x00,0x21,0x88,0xa0,0x00,
23290x21,0x18,0x00,0x00,0x0f,0x00,0x00,0x12,0x21,0x20,0x00,0x02,0xb8,0x46,0x00,0x0c,
23300x00,0x00,0x00,0x00,0x21,0x80,0x02,0x02,0x00,0x00,0x02,0x82,0x21,0x28,0x20,0x02,
23310x21,0x20,0x00,0x02,0x07,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0xdc,0x46,0x00,0x0c,
23320x00,0x00,0x00,0x00,0x21,0x18,0x40,0x00,0x09,0x00,0x40,0x14,0x00,0x00,0x42,0xae,
23330x21,0x18,0x00,0x02,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
23340x10,0x00,0xb0,0x8f,0x21,0x10,0x60,0x00,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
23350x00,0x00,0x42,0x80,0x00,0x00,0x00,0x00,0xf5,0xff,0x40,0x10,0x01,0x00,0x64,0x24,
23360x00,0x00,0x60,0xa0,0x46,0x47,0x00,0x08,0x00,0x00,0x44,0xae,0xd8,0xff,0xbd,0x27,
23370x14,0x00,0xb1,0xaf,0x21,0x88,0x80,0x00,0x21,0x20,0xa0,0x00,0x1c,0x00,0xb3,0xaf,
23380x18,0x00,0xb2,0xaf,0x20,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,0x81,0x46,0x00,0x0c,
23390x21,0x98,0xa0,0x00,0x21,0x90,0x40,0x00,0x08,0x00,0x40,0x16,0x21,0x10,0x20,0x02,
23400x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
23410x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,0x81,0x46,0x00,0x0c,
23420x21,0x20,0x20,0x02,0x21,0x80,0x40,0x00,0x2a,0x10,0x52,0x00,0x0a,0x00,0x40,0x14,
23430x00,0x00,0x00,0x00,0x21,0x20,0x20,0x02,0x21,0x28,0x60,0x02,0x21,0x30,0x40,0x02,
23440xd4,0x45,0x00,0x0c,0xff,0xff,0x10,0x26,0x0b,0x00,0x40,0x10,0x2a,0x18,0x12,0x02,
23450xf8,0xff,0x60,0x10,0x01,0x00,0x31,0x26,0x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,
23460x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,
23470x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,0x62,0x47,0x00,0x08,0x21,0x10,0x20,0x02,
23480x01,0x80,0x02,0x3c,0xc0,0xff,0xbd,0x27,0x08,0x1e,0x44,0x24,0x25,0xb0,0x02,0x3c,
23490x28,0x00,0xb4,0xaf,0x02,0x80,0x03,0x3c,0x25,0xb0,0x14,0x3c,0x18,0x03,0x42,0x34,
23500x38,0x00,0xbe,0xaf,0x34,0x00,0xb7,0xaf,0x30,0x00,0xb6,0xaf,0x2c,0x00,0xb5,0xaf,
23510x24,0x00,0xb3,0xaf,0x3c,0x00,0xbf,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,
23520x18,0x00,0xb0,0xaf,0x68,0x15,0x73,0x24,0x00,0x00,0x44,0xac,0x02,0x80,0x16,0x3c,
23530x02,0x80,0x15,0x3c,0xc4,0x02,0x9e,0x36,0x64,0x03,0x97,0x36,0x01,0x80,0x04,0x3c,
23540x08,0x1e,0x82,0x24,0x18,0x03,0x83,0x36,0x00,0x00,0x62,0xac,0xa0,0x02,0x87,0x36,
23550x00,0x00,0xe4,0x8c,0xd8,0x63,0x63,0x8e,0xff,0x0f,0x02,0x3c,0xff,0xff,0x46,0x34,
23560x24,0x80,0x86,0x00,0x01,0x00,0x05,0x3c,0x01,0x00,0x63,0x24,0x2b,0x10,0xb0,0x00,
23570x07,0x00,0x40,0x10,0xd8,0x63,0x63,0xae,0xa4,0x02,0x82,0x36,0x00,0x00,0x51,0x8c,
23580x00,0xb0,0x03,0x3c,0x25,0x80,0x03,0x02,0x00,0x00,0x11,0xae,0x00,0x00,0xe0,0xac,
23590xb0,0x02,0x84,0x36,0x00,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x24,0x80,0x46,0x00,
23600x2b,0x18,0xb0,0x00,0x08,0x00,0x60,0x10,0xc0,0x02,0x82,0x36,0x00,0xb0,0x02,0x3c,
23610x25,0x80,0x02,0x02,0x00,0x00,0x11,0x8e,0xb4,0x02,0x82,0x36,0x00,0x00,0x51,0xac,
23620x00,0x00,0x80,0xac,0xc0,0x02,0x82,0x36,0x00,0x00,0x50,0x8c,0xff,0x00,0x08,0x3c,
23630xff,0xff,0x02,0x35,0x2b,0x10,0x50,0x00,0x47,0x00,0x40,0x10,0x00,0x00,0x00,0x00,
23640x00,0x00,0x82,0x8e,0x00,0xff,0x06,0x3c,0xac,0x02,0x84,0x36,0x01,0x00,0x45,0x24,
23650xbc,0x02,0x83,0x36,0xff,0x00,0xc2,0x34,0x00,0xfd,0x07,0x3c,0x00,0x00,0x85,0xac,
23660x00,0x00,0x70,0xac,0x24,0x18,0x02,0x02,0x07,0x00,0xe2,0x34,0x00,0x00,0x85,0x8c,
23670x52,0x03,0x62,0x10,0x25,0xb0,0x12,0x3c,0x2b,0x10,0x43,0x00,0xa2,0x00,0x40,0x14,
23680xa4,0x00,0xe2,0x34,0x00,0xf8,0x04,0x3c,0x15,0x00,0x82,0x34,0x57,0x03,0x62,0x10,
23690x2b,0x10,0x43,0x00,0xc8,0x00,0x40,0x14,0x00,0xf9,0x05,0x3c,0x00,0xf0,0x05,0x3c,
23700x20,0x00,0xa2,0x34,0x67,0x03,0x62,0x10,0x2b,0x10,0x43,0x00,0x20,0x01,0x40,0x14,
23710x10,0x00,0x82,0x34,0x70,0x03,0x65,0x10,0x2b,0x10,0xa3,0x00,0xc8,0x01,0x40,0x14,
23720x02,0x00,0xa2,0x34,0x00,0xd0,0x02,0x3c,0x2a,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,
23730xaf,0x02,0x40,0x14,0x00,0xe0,0x02,0x3c,0x00,0xc0,0x02,0x3c,0xbb,0x03,0x62,0x10,
23740xff,0x00,0x03,0x3c,0x00,0xf0,0x02,0x3c,0x24,0x30,0x02,0x02,0x18,0x00,0xc2,0x10,
23750x02,0x1d,0x10,0x00,0x00,0x70,0x05,0x3c,0x24,0x10,0x05,0x02,0x02,0x4f,0x02,0x00,
23760x0f,0x00,0x02,0x3c,0xff,0xff,0x42,0x34,0x00,0x50,0x07,0x3c,0xff,0x00,0x68,0x30,
23770xff,0x00,0x04,0x32,0x96,0x01,0xc7,0x10,0x24,0x18,0x02,0x02,0x2b,0x10,0xe6,0x00,
23780x8a,0x01,0x40,0x14,0x00,0x80,0x02,0x3c,0x00,0x20,0x02,0x3c,0x1a,0x03,0xc2,0x10,
23790x2b,0x10,0x46,0x00,0x82,0x02,0x40,0x14,0x00,0x30,0x02,0x3c,0x17,0x03,0xc0,0x10,
23800x80,0x10,0x08,0x00,0x00,0x10,0x02,0x3c,0x14,0x03,0xc2,0x10,0x80,0x10,0x08,0x00,
23810xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
23820x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x00,0x00,0xe2,0x92,0x25,0xb0,0x07,0x3c,
23830xc8,0x7d,0xc2,0xa2,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
23840xc8,0x7d,0xc2,0x92,0x00,0x00,0x00,0x00,0x01,0x00,0x42,0x30,0x4e,0x00,0x40,0x10,
23850x02,0x80,0x03,0x3c,0x00,0x40,0x62,0x8e,0xf0,0xff,0x03,0x24,0xd7,0x42,0x60,0xa2,
23860x24,0x10,0x43,0x00,0x01,0x00,0x42,0x34,0x00,0x40,0x62,0xae,0xc8,0x7d,0xc2,0x92,
23870x00,0x00,0x00,0x00,0x02,0x00,0x42,0x30,0x3d,0x00,0x40,0x10,0x0f,0xff,0x03,0x24,
23880x00,0x40,0x62,0x8e,0x00,0x00,0x00,0x00,0x24,0x10,0x43,0x00,0x10,0x00,0x42,0x34,
23890x00,0x40,0x62,0xae,0xc8,0x7d,0xc2,0x92,0x00,0x00,0x00,0x00,0x04,0x00,0x42,0x30,
23900x30,0x00,0x40,0x10,0xff,0xf0,0x03,0x24,0x00,0x40,0x62,0x8e,0x00,0x00,0x00,0x00,
23910x24,0x10,0x43,0x00,0x00,0x01,0x42,0x34,0x25,0xb0,0x05,0x3c,0x00,0x40,0x62,0xae,
23920x4c,0x00,0xa3,0x34,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x03,0x00,0x42,0x30,
23930x05,0x00,0x40,0x14,0xff,0xff,0x02,0x3c,0x00,0x40,0x63,0x8e,0xff,0x0f,0x42,0x34,
23940x24,0x18,0x62,0x00,0x00,0x40,0x63,0xae,0x00,0x7b,0xa4,0x8e,0x01,0x80,0x06,0x3c,
23950x08,0x1f,0xc2,0x24,0x18,0x03,0xa3,0x34,0x00,0x7b,0xa6,0x26,0x00,0x00,0x62,0xac,
23960x10,0x00,0x86,0x10,0x02,0x80,0x02,0x3c,0xbf,0x00,0xb2,0x34,0x68,0x15,0x51,0x24,
23970x21,0x80,0xc0,0x00,0x00,0x00,0x42,0x92,0x00,0x00,0x00,0x00,0x04,0x00,0x42,0x2c,
23980x09,0x00,0x40,0x10,0x02,0x80,0x07,0x3c,0x98,0x65,0x24,0x8e,0x8b,0x07,0x00,0x0c,
23990x00,0x00,0x00,0x00,0x00,0x7b,0xa2,0x8e,0x00,0x00,0x00,0x00,0xf5,0xff,0x50,0x14,
24000x00,0x00,0x00,0x00,0x02,0x80,0x07,0x3c,0x08,0x08,0xe4,0x24,0x21,0x28,0x00,0x00,
24010x21,0x30,0x00,0x00,0x31,0x1c,0x00,0x0c,0x21,0x38,0x00,0x00,0x9a,0x47,0x00,0x08,
24020x01,0x80,0x04,0x3c,0x00,0x40,0x62,0x8e,0x30,0x48,0x00,0x08,0x24,0x10,0x43,0x00,
24030x00,0x40,0x62,0x8e,0x04,0x43,0x64,0x92,0x24,0x10,0x43,0x00,0x00,0x40,0x62,0xae,
24040x27,0x48,0x00,0x08,0x04,0x43,0x64,0xae,0x68,0x15,0x66,0x24,0x00,0x40,0xc2,0x8c,
24050xd7,0x42,0xc4,0x90,0xf0,0xff,0x03,0x24,0x24,0x10,0x43,0x00,0xb3,0xff,0x80,0x14,
24060x00,0x40,0xc2,0xac,0x1c,0x00,0x04,0x24,0x58,0x0c,0xe5,0x34,0x50,0x0c,0xe3,0x34,
24070x01,0x00,0x02,0x24,0xd7,0x42,0xc2,0xa0,0x00,0x00,0x64,0xa0,0x00,0x00,0xa4,0xa0,
24080x1d,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xb2,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,
24090x3f,0x00,0x40,0x14,0xaf,0x00,0xe2,0x34,0x20,0x00,0xe2,0x34,0xc0,0x02,0x62,0x10,
24100x2b,0x10,0x43,0x00,0xe3,0x00,0x40,0x14,0x29,0x00,0xe2,0x34,0x15,0x00,0xe2,0x34,
24110x0c,0x03,0x62,0x10,0x2b,0x10,0x43,0x00,0x9d,0x01,0x40,0x14,0x17,0x00,0xe2,0x34,
24120x09,0x00,0xe2,0x34,0xd8,0x03,0x62,0x10,0x2b,0x10,0x62,0x00,0x81,0x02,0x40,0x14,
24130x14,0x00,0xe2,0x34,0x64,0xff,0x62,0x14,0x00,0xf0,0x02,0x3c,0xff,0x00,0x07,0x3c,
24140x00,0xff,0xe7,0x34,0x24,0x10,0x07,0x02,0x7a,0xff,0x40,0x10,0xc0,0x02,0x82,0x36,
24150x04,0x43,0x64,0x92,0xff,0x00,0x02,0x3c,0x24,0x10,0x02,0x02,0x00,0xff,0x03,0x32,
24160x02,0x14,0x02,0x00,0x02,0x1a,0x03,0x00,0xfb,0xff,0x45,0x24,0x1c,0x43,0x62,0xa2,
24170x00,0x01,0x84,0x34,0xfb,0xff,0x66,0x24,0xc0,0x02,0x82,0x36,0x04,0x43,0x64,0xae,
24180x1d,0x43,0x65,0xa2,0x1f,0x43,0x66,0xa2,0x1e,0x43,0x63,0xa2,0x00,0x00,0x40,0xac,
24190x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x05,0x00,0xa2,0x34,0x91,0x02,0x62,0x10,
24200x2b,0x10,0x43,0x00,0x8e,0x00,0x40,0x14,0x00,0x00,0x00,0x00,0xde,0x02,0x65,0x10,
24210x2b,0x10,0xa3,0x00,0x32,0x01,0x40,0x14,0x02,0x00,0xa2,0x34,0x17,0x00,0x82,0x34,
24220x61,0x04,0x62,0x10,0x2b,0x10,0x62,0x00,0xa9,0x03,0x40,0x14,0x18,0x00,0x82,0x34,
24230x3d,0xff,0x62,0x14,0x00,0xf0,0x02,0x3c,0x74,0x0b,0x00,0x0c,0x00,0x00,0x00,0x00,
24240xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24250xa8,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,0x95,0x00,0x40,0x14,0x0c,0x00,0xc2,0x34,
24260xaa,0x00,0xe2,0x34,0xdc,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,0xd9,0x00,0x40,0x14,
24270xac,0x00,0xe2,0x34,0xa6,0x00,0xe2,0x34,0x1c,0x04,0x62,0x10,0x2b,0x10,0x62,0x00,
24280x69,0x03,0x40,0x14,0xa7,0x00,0xe2,0x34,0x27,0xff,0x62,0x14,0x00,0xf0,0x02,0x3c,
24290x00,0xff,0x02,0x32,0xff,0x00,0x04,0x3c,0x02,0x8a,0x02,0x00,0x24,0x18,0x04,0x02,
24300x01,0x00,0x02,0x24,0xa6,0x04,0x22,0x12,0x02,0x1c,0x03,0x00,0x02,0x00,0x02,0x24,
24310xc9,0x04,0x22,0x12,0x03,0x00,0x02,0x24,0xdf,0x04,0x22,0x12,0x04,0x00,0x02,0x24,
24320xd1,0x04,0x22,0x12,0x08,0x00,0x02,0x24,0x2e,0x05,0x22,0x12,0x09,0x00,0x02,0x24,
24330x1e,0x05,0x22,0x12,0x0a,0x00,0x02,0x24,0x0e,0x05,0x22,0x12,0x0b,0x00,0x02,0x24,
24340xfe,0x04,0x22,0x12,0x0c,0x00,0x02,0x24,0x5e,0x05,0x22,0x12,0x0d,0x00,0x02,0x24,
24350x4e,0x05,0x22,0x12,0x0e,0x00,0x02,0x24,0x3e,0x05,0x22,0x12,0x0f,0x00,0x02,0x24,
24360x2e,0x05,0x22,0x12,0x10,0x00,0x02,0x24,0x22,0xff,0x22,0x16,0xc0,0x02,0x82,0x36,
24370xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,
24380x80,0x10,0x02,0x00,0x21,0x10,0x53,0x00,0x4c,0x51,0x43,0x94,0x48,0x51,0x44,0x94,
24390x25,0xb0,0x06,0x3c,0x00,0x1c,0x03,0x00,0x21,0x20,0x83,0x00,0x00,0x00,0xc4,0xaf,
24400x58,0x51,0x45,0x8c,0x54,0x51,0x43,0x8c,0x50,0x51,0x44,0x94,0xc8,0x02,0xc6,0x34,
24410x21,0x18,0x65,0x00,0x00,0x1c,0x03,0x00,0x21,0x20,0x83,0x00,0xc0,0x02,0x82,0x36,
24420x00,0x00,0xc4,0xac,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24430x66,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,0xbf,0x00,0x40,0x14,0x12,0x00,0x82,0x34,
24440x00,0xf1,0x04,0x3c,0x01,0x00,0x82,0x34,0xc1,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,
24450xb7,0x01,0x40,0x14,0x02,0x00,0x82,0x34,0xe3,0xfe,0x64,0x14,0x00,0xf0,0x02,0x3c,
24460xff,0x00,0x04,0x3c,0x00,0xff,0x84,0x34,0x24,0x10,0x04,0x02,0x02,0x8a,0x02,0x00,
24470x80,0x1a,0x11,0x00,0x00,0xf4,0x63,0x24,0x94,0x00,0x82,0x36,0x00,0x00,0x51,0xa4,
24480x26,0xb0,0x04,0x3c,0x42,0x89,0x03,0x00,0x98,0x00,0x86,0x36,0xff,0x01,0x02,0x24,
24490x10,0x00,0x03,0x24,0x9a,0x00,0x85,0x36,0x00,0x00,0xa2,0xa4,0x7c,0x00,0x89,0x34,
24500x00,0x00,0xc3,0xa4,0x01,0x00,0x02,0x24,0x04,0x00,0x03,0x24,0x96,0x00,0x87,0x36,
24510x7a,0x00,0x84,0x34,0xb0,0x03,0x88,0x36,0x25,0xb0,0x06,0x3c,0x00,0x00,0xe2,0xa4,
24520x44,0x00,0xc6,0x34,0x00,0x00,0x83,0xa0,0x00,0x00,0x11,0xad,0x00,0x00,0x31,0xa5,
24530x00,0x00,0xc3,0x94,0xff,0xfd,0x02,0x24,0x24,0x18,0x62,0x00,0x00,0x00,0xc3,0xa4,
24540x00,0x00,0xc2,0x94,0x00,0x00,0x00,0x00,0x00,0x02,0x42,0x34,0x00,0x00,0xc2,0xa4,
24550xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24560x65,0x01,0x67,0x10,0x2b,0x10,0xe3,0x00,0xc5,0x00,0x40,0x14,0x02,0x00,0xe2,0x34,
24570x07,0x00,0xa2,0x34,0xfc,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,0xa9,0x01,0x40,0x14,
24580x20,0x00,0xa2,0x34,0xb0,0xfe,0x62,0x14,0x00,0xf0,0x02,0x3c,0xff,0x00,0x03,0x3c,
24590x00,0xff,0x63,0x34,0x24,0x10,0x03,0x02,0x02,0x3a,0x02,0x00,0x80,0x04,0xe0,0x10,
24600x02,0x80,0x04,0x3c,0x05,0x00,0x02,0x24,0xc2,0xfe,0xe2,0x14,0xc0,0x02,0x82,0x36,
24610x02,0x80,0x06,0x3c,0x8f,0x7d,0xc2,0x90,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,
24620xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24630x2e,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,0x98,0x00,0x40,0x14,0x0e,0x00,0xc2,0x34,
24640x01,0x00,0xc2,0x34,0xab,0x03,0x62,0x10,0x2b,0x10,0x43,0x00,0x48,0x01,0x40,0x14,
24650x00,0xff,0x02,0x3c,0x94,0xfe,0x66,0x14,0x00,0xf0,0x02,0x3c,0x5b,0x4e,0x00,0x0c,
24660x21,0x20,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
24670x00,0x00,0x00,0x00,0x4c,0x02,0x62,0x10,0x2b,0x10,0x43,0x00,0xa6,0x00,0x40,0x14,
24680xa1,0x00,0xe2,0x34,0x22,0x00,0xe2,0x34,0xbd,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,
24690x88,0x01,0x40,0x14,0x00,0x20,0x02,0x3c,0x28,0x00,0xe2,0x34,0x82,0xfe,0x62,0x14,
24700x00,0xf0,0x02,0x3c,0x0f,0x00,0x04,0x3c,0xff,0xff,0x85,0x34,0x60,0x00,0x06,0x24,
24710xba,0x44,0x00,0x0c,0x24,0x00,0x04,0x24,0x84,0x0a,0x00,0x0c,0xe8,0x03,0x04,0x24,
24720x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
24730x0f,0x00,0x06,0x3c,0x24,0x00,0x04,0x24,0xdd,0x44,0x00,0x0c,0xff,0xff,0xc5,0x34,
24740x1f,0x00,0x51,0x30,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
24750xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,0x00,0x00,0xd1,0xa3,
24760x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x18,0x02,0xc2,0x10,
24770x2b,0x10,0x46,0x00,0x01,0x01,0x40,0x14,0x00,0xa0,0x02,0x3c,0x00,0x60,0x02,0x3c,
24780x04,0x00,0xc2,0x10,0x80,0x10,0x08,0x00,0x7a,0xfe,0xc5,0x14,0xc0,0x02,0x82,0x36,
24790x80,0x10,0x08,0x00,0x21,0x10,0x48,0x00,0x21,0x10,0x53,0x00,0x21,0x10,0x49,0x00,
24800xc1,0x43,0x44,0xa0,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
24810x00,0x00,0x00,0x00,0x3f,0x03,0x62,0x10,0x2b,0x10,0x62,0x00,0xb6,0x02,0x40,0x14,
24820xad,0x00,0xe2,0x34,0xc7,0x03,0x62,0x10,0xae,0x00,0xe2,0x34,0x4e,0xfe,0x62,0x14,
24830x00,0xf0,0x02,0x3c,0xff,0x00,0x02,0x3c,0x24,0x20,0x02,0x02,0x00,0xff,0x05,0x32,
24840x02,0x24,0x04,0x00,0x69,0x4f,0x00,0x0c,0x02,0x2a,0x05,0x00,0x00,0x00,0xc2,0xa3,
24850xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24860x4b,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,0x17,0x01,0x40,0x14,0x03,0x00,0xa2,0x34,
24870x82,0x03,0x62,0x10,0x08,0x00,0xa2,0x34,0x3b,0xfe,0x62,0x14,0x00,0xf0,0x02,0x3c,
24880x00,0xff,0x02,0x32,0x02,0x82,0x02,0x00,0xcc,0x02,0x83,0x36,0x00,0x00,0x70,0xac,
24890x12,0x04,0x00,0x12,0x01,0x00,0x02,0x24,0x9c,0x04,0x02,0x12,0x00,0x00,0x00,0x00,
24900x7a,0x42,0x00,0x0c,0x21,0x20,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
24910x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x4e,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,
24920xe4,0x00,0x40,0x14,0x00,0xff,0x02,0x32,0x13,0x00,0x82,0x34,0x4c,0x03,0x62,0x10,
24930x14,0x00,0x82,0x34,0x24,0xfe,0x62,0x14,0x00,0xf0,0x02,0x3c,0xd3,0x0a,0x00,0x0c,
24940xfd,0x00,0x04,0x24,0x10,0x10,0x03,0x3c,0xa0,0x00,0x82,0x36,0x10,0x10,0x63,0x34,
24950x00,0xc0,0x07,0x3c,0x25,0xb0,0x06,0x3c,0x00,0x00,0x43,0xac,0xa4,0x00,0x84,0x36,
24960x00,0xa1,0xe7,0x34,0xa8,0x00,0xc6,0x34,0xc0,0x02,0x82,0x36,0x00,0x00,0x80,0xac,
24970x00,0x00,0xc7,0xac,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
24980x60,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,0xf6,0x00,0x40,0x14,0x03,0x00,0xa2,0x34,
24990x4b,0x03,0x62,0x10,0x04,0x00,0xa2,0x34,0x0b,0xfe,0x62,0x14,0x00,0xf0,0x02,0x3c,
25000xf4,0x63,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,
25010x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x61,0x02,0x62,0x10,
25020x2b,0x10,0x62,0x00,0xfe,0x00,0x40,0x14,0x01,0x00,0x02,0x24,0x0f,0x00,0xc2,0x34,
25030x63,0x03,0x62,0x10,0x10,0x00,0xc2,0x34,0xfb,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,
25040x00,0xff,0x03,0x32,0x00,0xff,0x02,0x34,0x9d,0x03,0x62,0x10,0xc0,0x02,0x82,0x36,
25050x8c,0x65,0x60,0xae,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25060x47,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,0x02,0x01,0x40,0x14,0x03,0x00,0xe2,0x34,
25070x8d,0x03,0x62,0x10,0x04,0x00,0xe2,0x34,0xeb,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,
25080x1e,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
25090x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x9b,0x01,0x62,0x10,0x2b,0x10,0x43,0x00,
25100xcf,0x00,0x40,0x14,0xa2,0x00,0xe2,0x34,0xa0,0x00,0xe2,0x34,0xde,0xfd,0x62,0x14,
25110x00,0xf0,0x02,0x3c,0x00,0x0f,0x02,0x32,0x02,0x22,0x02,0x00,0x01,0x00,0x03,0x24,
25120x3c,0x04,0x83,0x10,0x02,0x00,0x02,0x24,0x34,0x04,0x82,0x10,0x03,0x00,0x02,0x24,
25130x46,0x03,0x82,0x10,0x00,0x00,0x00,0x00,0xde,0x4f,0x00,0x0c,0x21,0x20,0x00,0x00,
25140xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25150x46,0x02,0x62,0x10,0x2b,0x10,0x62,0x00,0xe6,0xfd,0x40,0x14,0xc0,0x02,0x82,0x36,
25160x18,0x00,0xe2,0x34,0x45,0x03,0x62,0x10,0x19,0x00,0xe2,0x34,0xc6,0xfd,0x62,0x14,
25170x00,0xf0,0x02,0x3c,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x94,0x0e,0x83,0x36,
25180x9c,0x0e,0x82,0x36,0xa4,0x0e,0x84,0x36,0xac,0x0e,0x87,0x36,0x00,0x00,0x65,0x8c,
25190x00,0x00,0x48,0x8c,0x00,0x00,0x8a,0x8c,0x00,0x00,0xe6,0x8c,0x02,0x80,0x07,0x3c,
25200x68,0x15,0xed,0x24,0xb4,0x0e,0x82,0x36,0x00,0x00,0x47,0x8c,0x0c,0x40,0xa3,0x8d,
25210xff,0x03,0x02,0x3c,0x10,0x40,0xa4,0x8d,0x24,0x28,0xa2,0x00,0x24,0x30,0xc2,0x00,
25220xbc,0x0e,0x82,0x36,0x00,0x00,0x4b,0x8c,0x00,0xfc,0x02,0x24,0x02,0x2c,0x05,0x00,
25230x24,0x18,0x62,0x00,0x02,0x34,0x06,0x00,0x24,0x20,0x82,0x00,0xc4,0x0e,0x82,0x36,
25240x25,0x18,0x65,0x00,0x25,0x20,0x86,0x00,0x00,0x00,0x45,0x8c,0xff,0x03,0x06,0x3c,
25250xf0,0xff,0x02,0x3c,0xff,0x03,0x42,0x34,0x24,0x38,0xe6,0x00,0x82,0x39,0x07,0x00,
25260x24,0x20,0x82,0x00,0x24,0x40,0x06,0x01,0x08,0x40,0xa9,0x8d,0x25,0x20,0x87,0x00,
25270xcc,0x0e,0x8c,0x36,0xff,0x03,0x07,0x3c,0x00,0x00,0x86,0x8d,0x24,0x18,0x62,0x00,
25280x24,0x50,0x47,0x01,0x24,0x58,0x67,0x01,0x82,0x41,0x08,0x00,0xff,0x9f,0x02,0x3c,
25290x0f,0xc0,0x07,0x3c,0xff,0xff,0xe7,0x34,0xff,0xff,0x42,0x34,0x25,0x18,0x68,0x00,
25300x24,0x48,0x22,0x01,0x24,0x18,0x67,0x00,0xff,0x03,0x02,0x3c,0x24,0x20,0x87,0x00,
25310xff,0x00,0x07,0x3c,0x24,0x28,0xa2,0x00,0x24,0x30,0xc2,0x00,0x00,0x51,0x0a,0x00,
25320x00,0x20,0x02,0x3c,0x00,0x59,0x0b,0x00,0x00,0xff,0xe7,0x34,0x25,0x48,0x22,0x01,
25330x25,0x18,0x6a,0x00,0x25,0x20,0x8b,0x00,0x02,0x2c,0x05,0x00,0x02,0x34,0x06,0x00,
25340x24,0x10,0x07,0x02,0x08,0x40,0xa9,0xad,0x0c,0x40,0xa3,0xad,0x10,0x40,0xa4,0xad,
25350x14,0x40,0xa5,0xa5,0x4e,0x03,0x40,0x10,0x16,0x40,0xa6,0xa5,0xff,0x00,0x02,0x3c,
25360x24,0x10,0x02,0x02,0x02,0x14,0x02,0x00,0x02,0x1a,0x10,0x00,0xc7,0x42,0xa2,0xa1,
25370xc3,0x42,0xa3,0xa1,0xc3,0x42,0x62,0x92,0x25,0xb0,0x03,0x3c,0x61,0x0c,0x63,0x34,
25380x10,0x00,0xa4,0x27,0x00,0x00,0x62,0xa0,0x7a,0x54,0x00,0x0c,0x00,0x00,0x00,0x00,
25390xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25400x95,0x00,0xc2,0x10,0x00,0x40,0x02,0x3c,0x09,0xff,0xc2,0x10,0xc0,0x02,0x82,0x36,
25410x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x7b,0x02,0xc2,0x10,
25420x2b,0x10,0x46,0x00,0x83,0x00,0x40,0x14,0x00,0xb0,0x02,0x3c,0x00,0x90,0x02,0x3c,
25430x78,0xfd,0xc2,0x14,0xc0,0x02,0x82,0x36,0x21,0x10,0x13,0x01,0x73,0x44,0x44,0xa0,
25440xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25450x55,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,0x6a,0x56,0x00,0x0c,0x21,0x20,0x00,0x02,
25460xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25470x07,0x00,0x42,0x34,0x4c,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,0x5b,0x4e,0x00,0x0c,
25480x07,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25490x00,0x00,0x00,0x00,0x02,0x1a,0x02,0x00,0x21,0x88,0x00,0x00,0xaf,0x4a,0x00,0x08,
25500x27,0xb0,0x06,0x3c,0x01,0x00,0x31,0x26,0x00,0x01,0x22,0x2e,0x08,0x00,0x40,0x10,
25510xff,0x00,0x22,0x2e,0x00,0x00,0xc2,0x94,0x00,0x00,0x00,0x00,0xff,0x00,0x42,0x30,
25520xf8,0xff,0x43,0x14,0x08,0x00,0xc6,0x24,0x00,0x00,0xd1,0xa7,0xff,0x00,0x22,0x2e,
25530x50,0xfd,0x40,0x14,0xc0,0x02,0x82,0x36,0x12,0x87,0x02,0x3c,0x00,0x00,0xc2,0xaf,
25540xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25550x2d,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
25560x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xff,0x00,0x03,0x3c,0x00,0xff,0x63,0x34,
25570x24,0x10,0x03,0x02,0x02,0x82,0x02,0x00,0xcc,0x02,0x83,0x36,0x00,0x00,0x70,0xac,
25580x00,0x00,0xd1,0x8f,0x21,0x10,0x14,0x02,0x00,0x00,0x51,0xac,0x00,0x00,0x51,0x8c,
25590xc0,0x02,0x82,0x36,0x00,0x00,0xd1,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25600x00,0x00,0x00,0x00,0x00,0x64,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,
25610xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25620xf4,0x02,0x62,0x10,0xa3,0x00,0xe2,0x34,0x0f,0xfd,0x62,0x14,0x00,0xf0,0x02,0x3c,
25630xc0,0x02,0x82,0x36,0x8c,0x65,0x60,0xae,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25640x00,0x00,0x00,0x00,0xec,0x63,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,
25650xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25660xe6,0x63,0x62,0xa6,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25670x00,0x00,0x00,0x00,0x08,0x40,0x63,0x8e,0xff,0x9f,0x07,0x3c,0xff,0xff,0xe7,0x34,
25680x02,0x2c,0x10,0x00,0x00,0x1f,0x04,0x32,0x24,0x18,0x67,0x00,0x25,0x18,0x62,0x00,
25690x02,0x8a,0x04,0x00,0x3f,0x00,0xa5,0x30,0xc0,0x02,0x82,0x36,0x08,0x40,0x63,0xae,
25700xbc,0x42,0x71,0xa2,0xc1,0x42,0x65,0xa2,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25710x00,0x00,0x00,0x00,0x00,0x00,0xe2,0x92,0x00,0x00,0x00,0x00,0xfa,0x00,0x42,0x30,
25720x00,0x00,0xe2,0xa2,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25730x00,0x00,0x00,0x00,0x00,0x00,0xe2,0x92,0x00,0x00,0x00,0x00,0xfd,0x00,0x42,0x30,
25740x00,0x00,0xe2,0xa2,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25750x00,0x00,0x00,0x00,0xf7,0xfc,0xc2,0x14,0xc0,0x02,0x82,0x36,0x80,0x10,0x08,0x00,
25760x21,0x10,0x53,0x00,0x60,0x45,0x43,0xac,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
25770x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x80,0x10,0x08,0x00,0x21,0x10,0x48,0x00,
25780x21,0x10,0x53,0x00,0x21,0x10,0x49,0x00,0x34,0x43,0x44,0xa0,0xc0,0x02,0x82,0x36,
25790x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x77,0x56,0x00,0x0c,
25800x21,0x20,0x00,0x02,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25810x00,0x00,0x00,0x00,0xff,0xff,0x02,0x34,0x8c,0x65,0x62,0xae,0xc0,0x02,0x82,0x36,
25820x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x07,0x0b,0x00,0x0c,
25830x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25840x00,0x00,0x00,0x00,0xf0,0x63,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,
25850xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
25860x08,0x40,0x62,0x8e,0xff,0x9f,0x03,0x3c,0xff,0xff,0x63,0x34,0x24,0x10,0x43,0x00,
25870x08,0x40,0x62,0xae,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25880x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
25890x00,0x60,0x81,0x40,0x22,0x51,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,
25900x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
25910x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xff,0x00,0x07,0x3c,0x00,0xff,0xe7,0x34,
25920x24,0x10,0x07,0x02,0x02,0x82,0x02,0x00,0xcc,0x02,0x43,0x36,0x00,0x00,0x70,0xac,
25930x21,0x10,0x12,0x02,0x00,0x00,0x51,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0xd1,0xaf,
25940x00,0x00,0x51,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
25950x00,0x00,0x00,0x00,0xb7,0x4f,0x00,0x0c,0x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,
25960x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x21,0x88,0x00,0x00,
25970x6c,0x4b,0x00,0x08,0x27,0xb0,0x04,0x3c,0x01,0x00,0x31,0x26,0x00,0x01,0x22,0x2e,
25980x0a,0x00,0x40,0x10,0xff,0x00,0x22,0x2e,0x00,0x00,0x83,0x94,0x00,0x00,0x00,0x00,
25990xff,0xff,0x67,0x30,0xff,0x00,0xe2,0x30,0xf0,0x00,0x42,0x28,0xf6,0xff,0x40,0x14,
26000x08,0x00,0x84,0x24,0x00,0x00,0xc7,0xa7,0xff,0x00,0x22,0x2e,0x91,0xfc,0x40,0x14,
26010xc0,0x02,0x82,0x36,0x12,0x87,0x02,0x3c,0x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,
26020x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xe4,0x63,0x62,0x96,
26030x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xa7,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26040x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x04,0x64,0x62,0x92,0x00,0x00,0x00,0x00,
26050x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26060x00,0x00,0x00,0x00,0x00,0xff,0x02,0x32,0x02,0x12,0x02,0x00,0x03,0x00,0x43,0x2c,
26070x02,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x02,0x40,0x62,0xa2,0x02,0x40,0x63,0x92,
26080x90,0x0c,0x42,0x36,0x00,0x00,0x43,0xa0,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26090x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xd7,0x56,0x00,0x0c,0x00,0x00,0x00,0x00,
26100xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26110x21,0x10,0x13,0x01,0x56,0x44,0x44,0xa0,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26120x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xff,0x00,0x03,0x3c,0x24,0x20,0x03,0x02,
26130x73,0x0e,0x00,0x0c,0x02,0x24,0x04,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26140x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x02,0x1c,0x10,0x00,0x00,0x1f,0x02,0x32,
26150x02,0x8a,0x02,0x00,0x3f,0x00,0x65,0x30,0xc1,0x42,0x65,0xa2,0xbc,0x42,0x71,0xa2,
26160x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
26170x1f,0x12,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,0x00,0x60,0x01,0x40,
26180x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x03,0x40,0x62,0x92,0x0e,0x0c,0x44,0x36,
26190x01,0x00,0x42,0x24,0xff,0x00,0x43,0x30,0x00,0x00,0x83,0xa0,0x03,0x40,0x62,0xa2,
26200xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26210x00,0xff,0x02,0x32,0x02,0x3a,0x02,0x00,0x1a,0x01,0xe0,0x10,0x4f,0x00,0x82,0x36,
26220x94,0x00,0x42,0x36,0x00,0x00,0x43,0x94,0xff,0xff,0xe2,0x24,0xb0,0x03,0x45,0x36,
26230xff,0xff,0x71,0x30,0x1b,0x00,0x27,0x02,0x02,0x00,0xe0,0x14,0x00,0x00,0x00,0x00,
26240x0d,0x00,0x07,0x00,0xff,0xff,0x47,0x30,0x00,0x00,0xb1,0xac,0x80,0xff,0x02,0x24,
26250x00,0x19,0x07,0x00,0x25,0x18,0x62,0x00,0x4f,0x00,0x44,0x36,0x9e,0x00,0x46,0x36,
26260x00,0x00,0xa7,0xac,0x00,0x00,0x83,0xa0,0x25,0xb0,0x04,0x3c,0x44,0x00,0x84,0x34,
26270x12,0x88,0x00,0x00,0x80,0x12,0x11,0x00,0x00,0xfc,0x42,0x24,0x00,0x00,0xb1,0xac,
26280x00,0x00,0xd1,0xa4,0x42,0x89,0x02,0x00,0x26,0xb0,0x02,0x3c,0x7c,0x00,0x42,0x34,
26290x00,0x00,0xb1,0xac,0x00,0x00,0x51,0xa4,0x25,0xb0,0x02,0x3c,0x44,0x00,0x42,0x34,
26300x00,0x00,0x43,0x94,0xff,0xfd,0x02,0x24,0x24,0x18,0x62,0x00,0x00,0x00,0x83,0xa4,
26310x00,0x00,0x82,0x94,0x00,0x00,0x00,0x00,0x00,0x02,0x42,0x34,0x00,0x00,0x82,0xa4,
26320xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26330x24,0x10,0x08,0x02,0xcc,0x02,0x43,0x36,0x00,0xff,0x04,0x32,0x02,0x3c,0x02,0x00,
26340x00,0x00,0x70,0xac,0x04,0x00,0xe0,0x10,0x02,0x82,0x04,0x00,0x01,0x00,0x02,0x24,
26350x02,0x00,0xe2,0x10,0x01,0x00,0x04,0x24,0x21,0x20,0x00,0x00,0x7a,0x42,0x00,0x0c,
26360x00,0x00,0x00,0x00,0x0f,0x00,0x06,0x3c,0x21,0x20,0x00,0x02,0xdd,0x44,0x00,0x0c,
26370xff,0xff,0xc5,0x34,0x0f,0x00,0x07,0x3c,0xff,0xff,0xe7,0x34,0x24,0x88,0x47,0x00,
26380xc0,0x02,0x82,0x36,0x00,0x00,0xd1,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26390x00,0x00,0x00,0x00,0x28,0xb0,0x02,0x3c,0x00,0x00,0x43,0x90,0xff,0x00,0x02,0x24,
26400xff,0x00,0x70,0x30,0xf3,0xfb,0x02,0x12,0xc0,0x02,0x82,0x36,0x28,0xb0,0x05,0x3c,
26410xff,0x00,0x04,0x24,0xc0,0x10,0x10,0x00,0x21,0x10,0x45,0x00,0x00,0x00,0x43,0x90,
26420x00,0x00,0x00,0x00,0xff,0x00,0x70,0x30,0xfb,0xff,0x04,0x16,0xc0,0x10,0x10,0x00,
26430xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26440x00,0x1f,0x02,0x32,0x02,0x1c,0x10,0x00,0x02,0x8a,0x02,0x00,0x3f,0x00,0x65,0x30,
26450xc0,0x02,0x82,0x36,0xbc,0x42,0x71,0xa2,0xc1,0x42,0x65,0xa2,0x00,0x00,0x40,0xac,
26460x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xff,0x00,0x07,0x3c,0x24,0x20,0x07,0x02,
26470x15,0x51,0x00,0x0c,0x02,0x24,0x04,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26480x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xe8,0x63,0x62,0x92,0x00,0x00,0x00,0x00,
26490x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26500x00,0x00,0x00,0x00,0xfc,0x63,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,
26510xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26520x00,0x00,0xe2,0x92,0x00,0x00,0x00,0x00,0xff,0x00,0x51,0x30,0x05,0x00,0x23,0x36,
26530xc0,0x02,0x82,0x36,0x00,0x00,0xe3,0xa2,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26540x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,0xe6,0x63,0x60,0xa6,0x00,0x00,0x40,0xac,
26550x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xbd,0x56,0x00,0x0c,0x21,0x20,0x00,0x02,
26560xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
26570x41,0x0b,0x00,0x0c,0x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
26580x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0xe2,0x92,0x00,0x00,0x00,0x00,
26590xff,0x00,0x51,0x30,0x02,0x00,0x23,0x36,0xc0,0x02,0x82,0x36,0x00,0x00,0xe3,0xa2,
26600x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,
26610xec,0x91,0x42,0x24,0x00,0x00,0x47,0x8c,0xc0,0x02,0x43,0x36,0x25,0xb0,0x0c,0x3c,
26620x08,0x40,0xe4,0x8c,0x00,0x00,0x60,0xac,0x42,0x17,0x04,0x00,0x03,0x00,0x42,0x30,
26630x60,0x00,0x40,0x14,0x03,0x0d,0x42,0x36,0x00,0x00,0x45,0x90,0x10,0x40,0xe6,0x8c,
26640xff,0x9f,0x03,0x3c,0xff,0xff,0x63,0x34,0xff,0x3f,0x02,0x3c,0x24,0x20,0x83,0x00,
26650xff,0xff,0x42,0x34,0x00,0x20,0x03,0x3c,0x24,0x58,0xc2,0x00,0x25,0x20,0x83,0x00,
26660x00,0x40,0x02,0x3c,0x70,0x00,0xa5,0x30,0x25,0x58,0x62,0x01,0x08,0x01,0xa0,0x10,
26670x08,0x40,0xe4,0xac,0x94,0x0e,0x82,0x35,0x9c,0x0e,0x83,0x35,0xa4,0x0e,0x86,0x35,
26680x00,0x00,0x45,0x8c,0xac,0x0e,0x87,0x35,0x00,0x00,0x68,0x8c,0x00,0x00,0xca,0x8c,
26690x02,0x80,0x06,0x3c,0x00,0x00,0xe4,0x8c,0x68,0x15,0xc6,0x24,0x0c,0x40,0xc3,0x8c,
26700xb4,0x0e,0x82,0x35,0x00,0x00,0x47,0x8c,0xff,0x03,0x02,0x3c,0x00,0xfc,0x06,0x24,
26710x24,0x28,0xa2,0x00,0x24,0x20,0x82,0x00,0xbc,0x0e,0x82,0x35,0x00,0x00,0x49,0x8c,
26720x02,0x2c,0x05,0x00,0x24,0x10,0x66,0x01,0x24,0x18,0x66,0x00,0x02,0x24,0x04,0x00,
26730xc4,0x0e,0x86,0x35,0x25,0x18,0x65,0x00,0x25,0x10,0x44,0x00,0x00,0x00,0xc5,0x8c,
26740xff,0x03,0x04,0x3c,0xf0,0xff,0x06,0x3c,0xff,0x03,0xc6,0x34,0x24,0x38,0xe4,0x00,
26750xcc,0x0e,0x8b,0x35,0x24,0x40,0x04,0x01,0x82,0x39,0x07,0x00,0x00,0x00,0x64,0x8d,
26760x24,0x10,0x46,0x00,0x24,0x18,0x66,0x00,0x25,0x10,0x47,0x00,0x82,0x41,0x08,0x00,
26770xff,0x03,0x07,0x3c,0x0f,0xc0,0x06,0x3c,0x24,0x50,0x47,0x01,0x24,0x48,0x27,0x01,
26780xff,0xff,0xc6,0x34,0x25,0x18,0x68,0x00,0x24,0x28,0xa7,0x00,0x24,0x20,0x87,0x00,
26790x00,0x51,0x0a,0x00,0x24,0x18,0x66,0x00,0x00,0x49,0x09,0x00,0x24,0x10,0x46,0x00,
26800x02,0x80,0x07,0x3c,0x68,0x15,0xe7,0x24,0x25,0x18,0x6a,0x00,0x25,0x10,0x49,0x00,
26810x02,0x2c,0x05,0x00,0x02,0x24,0x04,0x00,0x0c,0x40,0xe3,0xac,0x10,0x40,0xe2,0xac,
26820x14,0x40,0xe5,0xa4,0x16,0x40,0xe4,0xa4,0x02,0x80,0x02,0x3c,0x68,0x15,0x43,0x24,
26830x0c,0x40,0x62,0x8c,0x00,0x00,0x00,0x00,0xbd,0x00,0x40,0x04,0x00,0x00,0x00,0x00,
26840x00,0xff,0x02,0x32,0xc6,0x00,0x40,0x10,0x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,
26850xc3,0x42,0x62,0xa0,0x7a,0x54,0x00,0x0c,0x10,0x00,0xa4,0x27,0xc2,0x53,0x00,0x0c,
26860x00,0x00,0x00,0x00,0x0c,0x40,0x62,0x8e,0x00,0x80,0x03,0x3c,0x25,0x10,0x43,0x00,
26870x0c,0x40,0x62,0xae,0xc3,0x42,0x62,0x92,0x25,0xb0,0x03,0x3c,0x61,0x0c,0x63,0x34,
26880x00,0x00,0x62,0xa0,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26890x00,0x00,0x00,0x00,0xcf,0x4e,0x00,0x0c,0x21,0x20,0x00,0x02,0xc0,0x02,0x82,0x36,
26900x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x17,0x51,0x00,0x0c,
26910x00,0x00,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26920x00,0x00,0x00,0x00,0x9e,0x00,0x83,0x36,0x00,0x00,0x40,0xa0,0x00,0x00,0x60,0xa4,
26930x94,0x00,0x82,0x36,0x00,0x00,0x43,0x94,0x25,0xb0,0x06,0x3c,0x44,0x00,0xc6,0x34,
26940xff,0xff,0x71,0x30,0x80,0x12,0x11,0x00,0x00,0xf8,0x42,0x24,0x42,0x89,0x02,0x00,
26950x26,0xb0,0x02,0x3c,0xb0,0x03,0x83,0x36,0x7c,0x00,0x42,0x34,0x00,0x00,0x71,0xac,
26960x00,0x00,0x51,0xa4,0x00,0x00,0xc3,0x94,0xff,0xfd,0x02,0x24,0x24,0x18,0x62,0x00,
26970x00,0x00,0xc3,0xa4,0x00,0x00,0xc2,0x94,0x00,0x00,0x00,0x00,0x00,0x02,0x42,0x34,
26980x00,0x00,0xc2,0xa4,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
26990x00,0x00,0x00,0x00,0x5b,0x4e,0x00,0x0c,0x01,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,
27000x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x80,0x10,0x08,0x00,
27010x21,0x10,0x53,0x00,0xec,0x44,0x43,0xac,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
27020x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xa7,0x0b,0x00,0x0c,0x00,0x00,0x00,0x00,
27030xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27040x28,0xb0,0x11,0x3c,0x00,0x00,0x22,0x96,0xff,0x00,0x04,0x3c,0x24,0x18,0x04,0x02,
27050x02,0x24,0x03,0x00,0xff,0x00,0x42,0x30,0x0a,0x00,0x82,0x10,0xff,0x7f,0x02,0x3c,
27060x08,0x00,0x31,0x26,0x00,0x00,0x22,0x96,0xff,0xff,0x23,0x32,0xff,0x00,0x42,0x30,
27070x03,0x00,0x82,0x10,0x00,0x08,0x63,0x2c,0xf9,0xff,0x60,0x14,0x00,0x00,0x00,0x00,
27080xff,0x7f,0x02,0x3c,0xff,0xff,0x42,0x34,0x24,0x10,0x22,0x02,0x00,0x00,0xc2,0xaf,
27090xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27100xf8,0x63,0x62,0x92,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,
27110x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xff,0x00,0x03,0x3c,
27120x24,0x10,0x03,0x02,0x00,0xff,0x04,0x32,0xcc,0x02,0x83,0x36,0x02,0x3c,0x02,0x00,
27130x00,0x00,0x70,0xac,0x04,0x00,0xe0,0x10,0x02,0x82,0x04,0x00,0x01,0x00,0x02,0x24,
27140x02,0x00,0xe2,0x10,0x01,0x00,0x04,0x24,0x21,0x20,0x00,0x00,0x7a,0x42,0x00,0x0c,
27150x00,0x00,0x00,0x00,0x00,0x00,0xd1,0x8f,0x0f,0x00,0x06,0x3c,0xff,0xff,0xc5,0x34,
27160x21,0x20,0x00,0x02,0xba,0x44,0x00,0x0c,0x21,0x30,0x20,0x02,0x0f,0x00,0x07,0x3c,
27170x21,0x20,0x00,0x02,0xdd,0x44,0x00,0x0c,0xff,0xff,0xe5,0x34,0x00,0x00,0xc2,0xaf,
27180x21,0x88,0x40,0x00,0x25,0xb0,0x02,0x3c,0xc8,0x02,0x42,0x34,0x00,0x00,0x51,0xac,
27190xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27200x25,0xb0,0x06,0x3c,0xff,0x00,0x02,0x24,0x56,0x01,0xc6,0x34,0x00,0x00,0xc2,0xa4,
27210x01,0x00,0x03,0x24,0x02,0x80,0x07,0x3c,0xc0,0x02,0x82,0x36,0xb8,0x7d,0xe3,0xa0,
27220x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xde,0x4f,0x00,0x0c,
27230x03,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27240x00,0x00,0x00,0x00,0xde,0x4e,0x00,0x0c,0x21,0x20,0x00,0x02,0xc0,0x02,0x82,0x36,
27250x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x40,0x62,0x8e,
27260xff,0x9f,0x04,0x3c,0xff,0xff,0x84,0x34,0x24,0x10,0x44,0x00,0x08,0x40,0x62,0xae,
27270xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27280xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,
27290x80,0x10,0x02,0x00,0x21,0x10,0x53,0x00,0x70,0x51,0x43,0x8c,0xc0,0x02,0x82,0x36,
27300x00,0x00,0xc3,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27310x7a,0x54,0x00,0x0c,0x10,0x00,0xa4,0x27,0xc3,0x42,0x62,0x92,0x25,0xb0,0x03,0x3c,
27320x61,0x0c,0x63,0x34,0x00,0x00,0x62,0xa0,0xd4,0x4c,0x00,0x08,0xc0,0x02,0x82,0x36,
27330x22,0x51,0x00,0x0c,0x10,0x40,0xeb,0xac,0xbd,0x4c,0x00,0x08,0x02,0x80,0x02,0x3c,
27340xc6,0x4c,0x00,0x08,0x12,0x00,0x02,0x24,0x1a,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,
27350xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27360xff,0xff,0x02,0x34,0x8c,0x65,0x62,0xae,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,
27370x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,
27380x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x53,0x00,
27390x74,0x51,0x43,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc3,0xaf,0x00,0x00,0x40,0xac,
27400x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,
27410x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x53,0x00,
27420xd4,0x51,0x43,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc3,0xaf,0x00,0x00,0x40,0xac,
27430x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,
27440x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x02,0x80,0x06,0x3c,0x80,0x10,0x02,0x00,
27450xe0,0x66,0xc3,0x24,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0xc0,0x02,0x82,0x36,
27460x00,0x00,0xc4,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,
27470x12,0x00,0x02,0x24,0xc7,0x42,0xa2,0xa1,0x77,0x4a,0x00,0x08,0xc3,0x42,0xa2,0xa1,
27480x88,0x7d,0x82,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0xc2,0xaf,0xc0,0x02,0x82,0x36,
27490x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x7a,0x42,0x00,0x0c,
27500x21,0x20,0x00,0x00,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27510x00,0x00,0x00,0x00,0xff,0x00,0x06,0x3c,0x00,0xff,0xc6,0x34,0x00,0x00,0xc5,0x8f,
27520x24,0x20,0x06,0x02,0xe1,0x50,0x00,0x0c,0x02,0x22,0x04,0x00,0xc0,0x02,0x82,0x36,
27530x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,
27540x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x02,0x80,0x07,0x3c,
27550x80,0x10,0x02,0x00,0xf0,0x66,0xe3,0x24,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,
27560xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27570x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,
27580x21,0x10,0x43,0x00,0x02,0x80,0x06,0x3c,0x80,0x10,0x02,0x00,0xec,0x66,0xc3,0x24,
27590x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,
27600x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,
27610x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x02,0x80,0x04,0x3c,
27620xe8,0x66,0x83,0x24,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,
27630xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27640x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,
27650x21,0x10,0x43,0x00,0x02,0x80,0x07,0x3c,0x80,0x10,0x02,0x00,0xe4,0x66,0xe3,0x24,
27660x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,
27670x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,
27680x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x02,0x80,0x04,0x3c,
27690x00,0x67,0x83,0x24,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,
27700xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27710x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,
27720x21,0x10,0x43,0x00,0x02,0x80,0x07,0x3c,0x80,0x10,0x02,0x00,0xfc,0x66,0xe3,0x24,
27730x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,
27740x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,
27750x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,0x02,0x80,0x06,0x3c,
27760x80,0x10,0x02,0x00,0xf8,0x66,0xc3,0x24,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,
27770xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27780x00,0x00,0x00,0x00,0xc0,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x80,0x10,0x02,0x00,
27790x21,0x10,0x43,0x00,0x02,0x80,0x04,0x3c,0xf4,0x66,0x83,0x24,0x80,0x10,0x02,0x00,
27800x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0xc0,0x02,0x82,0x36,0x00,0x00,0xc4,0xaf,
27810x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0xde,0x4f,0x00,0x0c,
27820x02,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27830x00,0x00,0x00,0x00,0xde,0x4f,0x00,0x0c,0x01,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,
27840x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,0x00,0x00,0x00,0x00,0x7a,0x42,0x00,0x0c,
27850x01,0x00,0x04,0x24,0xc0,0x02,0x82,0x36,0x00,0x00,0x40,0xac,0x08,0x48,0x00,0x08,
27860x00,0x00,0x00,0x00,0x25,0xb0,0x05,0x3c,0x01,0x00,0x06,0x24,0x01,0x80,0x02,0x3c,
27870x04,0x30,0x86,0x00,0xf1,0x02,0xa7,0x34,0xed,0x02,0xa4,0x34,0x6c,0x39,0x42,0x24,
27880x18,0x03,0xa5,0x34,0x08,0x00,0x03,0x24,0x00,0x00,0xa2,0xac,0x00,0x00,0xe3,0xa0,
27890x00,0x00,0x80,0xa0,0x00,0x00,0x86,0xa0,0x00,0x00,0x80,0xa0,0x00,0x00,0x86,0xa0,
27900x00,0x00,0x80,0xa0,0x00,0x00,0x86,0xa0,0x00,0x00,0x80,0xa0,0x00,0x00,0x86,0xa0,
27910x00,0x00,0x80,0xa0,0x00,0x00,0xe0,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
27920x01,0x80,0x02,0x3c,0x25,0xb0,0x03,0x3c,0xc8,0x39,0x42,0x24,0x18,0x03,0x63,0x34,
27930x00,0x00,0x62,0xac,0x00,0x00,0x83,0x90,0x30,0x00,0x02,0x24,0x05,0x00,0x62,0x10,
27940x21,0x20,0x00,0x00,0x31,0x00,0x02,0x24,0x02,0x00,0x62,0x10,0x01,0x00,0x04,0x24,
27950x07,0x00,0x04,0x24,0x5b,0x4e,0x00,0x08,0x00,0x00,0x00,0x00,0x01,0x80,0x02,0x3c,
27960x25,0xb0,0x03,0x3c,0x04,0x3a,0x42,0x24,0x18,0x03,0x63,0x34,0x02,0x80,0x04,0x3c,
27970x00,0x00,0x62,0xac,0x08,0x00,0xe0,0x03,0xc4,0x7d,0x80,0xac,0x02,0x80,0x02,0x3c,
27980x08,0x7b,0x42,0x24,0xc0,0x20,0x04,0x00,0x21,0x20,0x82,0x00,0x21,0x28,0x00,0x00,
27990x00,0x60,0x06,0x40,0x01,0x00,0xc1,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,
28000x00,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x09,0x00,0x44,0x10,0x00,0x00,0x00,0x00,
28010x04,0x00,0x43,0x8c,0x21,0x28,0x40,0x00,0x00,0x00,0x42,0x8c,0x00,0x00,0x00,0x00,
28020x00,0x00,0x62,0xac,0x04,0x00,0x43,0xac,0x00,0x00,0xa5,0xac,0x04,0x00,0xa5,0xac,
28030x00,0x60,0x86,0x40,0x08,0x00,0xe0,0x03,0x21,0x10,0xa0,0x00,0x21,0x18,0x80,0x00,
28040xe8,0xff,0xbd,0x27,0x01,0x01,0x62,0x2c,0x10,0x00,0xbf,0xaf,0x01,0x00,0x04,0x24,
28050x01,0x02,0x65,0x2c,0x0a,0x00,0x40,0x14,0x21,0x30,0x00,0x00,0x02,0x00,0x04,0x24,
28060x07,0x00,0xa0,0x14,0x01,0x08,0x62,0x2c,0x05,0x00,0x40,0x14,0x03,0x00,0x04,0x24,
28070x10,0x00,0xbf,0x8f,0x21,0x10,0xc0,0x00,0x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,
28080x89,0x4e,0x00,0x0c,0x00,0x00,0x00,0x00,0x10,0x00,0xbf,0x8f,0x21,0x30,0x40,0x00,
28090x21,0x10,0xc0,0x00,0x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,0x02,0x80,0x03,0x3c,
28100x20,0x7b,0x62,0x8c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x60,0x06,0x40,
28110x01,0x00,0xc1,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x10,0x00,0x83,0x8c,
28120x02,0x80,0x02,0x3c,0x08,0x7b,0x42,0x24,0xc0,0x18,0x03,0x00,0x21,0x18,0x62,0x00,
28130x00,0x00,0x65,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0xac,0x04,0x00,0xa4,0xac,
28140x00,0x00,0x64,0xac,0x04,0x00,0x83,0xac,0x00,0x60,0x86,0x40,0x08,0x00,0xe0,0x03,
28150x00,0x00,0x00,0x00,0x02,0x24,0x04,0x00,0xff,0x00,0x84,0x30,0xc0,0x18,0x04,0x00,
28160x21,0x18,0x64,0x00,0x80,0x18,0x03,0x00,0x21,0x18,0x64,0x00,0x02,0x80,0x02,0x3c,
28170x68,0x15,0x42,0x24,0x80,0x18,0x03,0x00,0x21,0x18,0x62,0x00,0x78,0x51,0x64,0x8c,
28180xff,0xf1,0x02,0x24,0x24,0x20,0x82,0x00,0x08,0x00,0xe0,0x03,0x78,0x51,0x64,0xac,
28190x02,0x24,0x04,0x00,0xff,0x00,0x84,0x30,0xc0,0x18,0x04,0x00,0x21,0x18,0x64,0x00,
28200x80,0x18,0x03,0x00,0x21,0x18,0x64,0x00,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,
28210x80,0x18,0x03,0x00,0x21,0x18,0x62,0x00,0x78,0x51,0x64,0x8c,0xff,0xf1,0x02,0x24,
28220x24,0x20,0x82,0x00,0x00,0x02,0x84,0x34,0x08,0x00,0xe0,0x03,0x78,0x51,0x64,0xac,
28230xe0,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0xc0,0x80,0x04,0x00,0x21,0x80,0x04,0x02,
28240x80,0x80,0x10,0x00,0x21,0x80,0x04,0x02,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,
28250x80,0x80,0x10,0x00,0x21,0x80,0x02,0x02,0x1c,0x00,0xbf,0xaf,0x18,0x00,0xb2,0xaf,
28260x14,0x00,0xb1,0xaf,0x78,0x51,0x05,0x8e,0xff,0x1f,0x02,0x3c,0x25,0xb0,0x12,0x3c,
28270xff,0xff,0x42,0x34,0x70,0x51,0x02,0xae,0x84,0x01,0x43,0x36,0xf8,0xff,0x02,0x24,
28280x00,0x00,0x66,0x8c,0x24,0x28,0xa2,0x00,0xff,0xfe,0x02,0x24,0x24,0x28,0xa2,0x00,
28290xff,0xef,0x03,0x24,0x24,0x28,0xa3,0x00,0x74,0x51,0x06,0xae,0x78,0x51,0x05,0xae,
28300xce,0x0d,0x00,0x0c,0x21,0x88,0x80,0x00,0x7a,0x51,0x02,0x92,0x21,0x88,0x32,0x02,
28310x1c,0x00,0xbf,0x8f,0x60,0x01,0x22,0xa2,0x18,0x00,0xb2,0x8f,0x64,0x51,0x00,0xae,
28320x48,0x51,0x00,0xae,0x4c,0x51,0x00,0xae,0x50,0x51,0x00,0xae,0x54,0x51,0x00,0xae,
28330x58,0x51,0x00,0xae,0x5c,0x51,0x00,0xae,0x60,0x51,0x00,0xae,0x14,0x00,0xb1,0x8f,
28340x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0xff,0x00,0xa5,0x30,
28350xc0,0x10,0x05,0x00,0x21,0x10,0x45,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x45,0x00,
28360x02,0x80,0x03,0x3c,0x68,0x15,0x63,0x24,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,
28370x78,0x51,0x43,0x8c,0x25,0xb0,0x05,0x3c,0xff,0x00,0xc6,0x30,0x21,0x30,0xc5,0x00,
28380xaf,0x01,0xc2,0x90,0x07,0x00,0x63,0x30,0x80,0x18,0x03,0x00,0x21,0x18,0x65,0x00,
28390xff,0x00,0x88,0x30,0xff,0x00,0x49,0x30,0x84,0x01,0x66,0x8c,0x21,0x50,0x00,0x00,
28400x21,0x58,0x00,0x00,0x2b,0x00,0x20,0x11,0x21,0x20,0x00,0x01,0x2b,0x00,0xc0,0x10,
28410x2b,0x10,0x09,0x01,0x21,0x28,0x00,0x00,0x3e,0x4f,0x00,0x08,0x01,0x00,0x07,0x24,
28420xff,0x00,0x65,0x30,0x1d,0x00,0xa2,0x2c,0x07,0x00,0x40,0x10,0xff,0xff,0x02,0x25,
28430x04,0x10,0xa7,0x00,0x24,0x10,0x46,0x00,0xf9,0xff,0x40,0x10,0x01,0x00,0xa3,0x24,
28440x21,0x58,0xa0,0x00,0xff,0xff,0x02,0x25,0xff,0x00,0x45,0x30,0x2b,0x18,0xab,0x00,
28450x0f,0x00,0x60,0x14,0x2b,0x10,0x49,0x01,0x01,0x00,0x04,0x24,0x04,0x10,0xa4,0x00,
28460x24,0x10,0x46,0x00,0xff,0xff,0xa7,0x24,0x04,0x00,0x40,0x10,0x01,0x00,0x43,0x25,
28470x17,0x00,0x49,0x11,0xff,0x00,0x6a,0x30,0x21,0x40,0xa0,0x00,0xff,0x00,0xe5,0x30,
28480x2b,0x10,0xab,0x00,0xf6,0xff,0x40,0x10,0x04,0x10,0xa4,0x00,0x2b,0x10,0x49,0x01,
28490x08,0x00,0x40,0x10,0x21,0x20,0x00,0x01,0x23,0x10,0x2a,0x01,0x2a,0x10,0x62,0x01,
28500x04,0x00,0x40,0x14,0x21,0x20,0x00,0x00,0x23,0x10,0x69,0x01,0x21,0x10,0x4a,0x00,
28510xff,0x00,0x44,0x30,0x08,0x00,0xe0,0x03,0x21,0x10,0x80,0x00,0xfd,0xff,0x40,0x14,
28520x21,0x20,0x00,0x00,0x23,0x10,0x09,0x01,0x5f,0x4f,0x00,0x08,0xff,0x00,0x44,0x30,
28530x21,0x20,0x00,0x01,0x08,0x00,0xe0,0x03,0x21,0x10,0x80,0x00,0xff,0x00,0x84,0x30,
28540xc0,0x10,0x04,0x00,0x21,0x10,0x44,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x44,0x00,
28550x02,0x80,0x03,0x3c,0x68,0x15,0x63,0x24,0x80,0x10,0x02,0x00,0x21,0x10,0x43,0x00,
28560x25,0xb0,0x06,0x3c,0x78,0x51,0x43,0x8c,0xff,0x00,0xa5,0x30,0x21,0x20,0x86,0x00,
28570x21,0x28,0xa6,0x00,0x60,0x01,0x82,0x90,0xaf,0x01,0xa4,0x90,0x07,0x00,0x63,0x30,
28580x80,0x18,0x03,0x00,0x21,0x18,0x66,0x00,0xff,0x00,0x48,0x30,0xff,0x00,0x89,0x30,
28590x84,0x01,0x66,0x8c,0x21,0x50,0x00,0x00,0x21,0x58,0x00,0x00,0x2b,0x00,0x20,0x11,
28600x21,0x20,0x00,0x01,0x2b,0x00,0xc0,0x10,0x2b,0x10,0x09,0x01,0x21,0x28,0x00,0x00,
28610x8c,0x4f,0x00,0x08,0x01,0x00,0x07,0x24,0xff,0x00,0x65,0x30,0x1d,0x00,0xa2,0x2c,
28620x07,0x00,0x40,0x10,0xff,0xff,0x02,0x25,0x04,0x10,0xa7,0x00,0x24,0x10,0x46,0x00,
28630xf9,0xff,0x40,0x10,0x01,0x00,0xa3,0x24,0x21,0x58,0xa0,0x00,0xff,0xff,0x02,0x25,
28640xff,0x00,0x45,0x30,0x2b,0x18,0xab,0x00,0x0f,0x00,0x60,0x14,0x2b,0x10,0x49,0x01,
28650x01,0x00,0x04,0x24,0x04,0x10,0xa4,0x00,0x24,0x10,0x46,0x00,0xff,0xff,0xa7,0x24,
28660x04,0x00,0x40,0x10,0x01,0x00,0x43,0x25,0x17,0x00,0x49,0x11,0xff,0x00,0x6a,0x30,
28670x21,0x40,0xa0,0x00,0xff,0x00,0xe5,0x30,0x2b,0x10,0xab,0x00,0xf6,0xff,0x40,0x10,
28680x04,0x10,0xa4,0x00,0x2b,0x10,0x49,0x01,0x08,0x00,0x40,0x10,0x21,0x20,0x00,0x01,
28690x23,0x10,0x2a,0x01,0x2a,0x10,0x62,0x01,0x04,0x00,0x40,0x14,0x21,0x20,0x00,0x00,
28700x23,0x10,0x69,0x01,0x21,0x10,0x4a,0x00,0xff,0x00,0x44,0x30,0x08,0x00,0xe0,0x03,
28710x21,0x10,0x80,0x00,0xfd,0xff,0x40,0x14,0x21,0x20,0x00,0x00,0x23,0x10,0x09,0x01,
28720xad,0x4f,0x00,0x08,0xff,0x00,0x44,0x30,0x21,0x20,0x00,0x01,0x08,0x00,0xe0,0x03,
28730x21,0x10,0x80,0x00,0xe0,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x10,0x00,0xb0,0xaf,
28740x68,0x15,0x50,0x24,0x18,0x00,0xb2,0xaf,0x14,0x00,0xb1,0xaf,0x1c,0x00,0xbf,0xaf,
28750x21,0x88,0x00,0x00,0x21,0x90,0x00,0x02,0xee,0x4e,0x00,0x0c,0x21,0x20,0x20,0x02,
28760x7a,0x51,0x02,0x92,0x21,0x28,0x00,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x52,0x00,
28770xec,0x44,0x44,0x8c,0x60,0x45,0x43,0x8c,0x00,0x00,0x00,0x00,0x21,0x18,0x64,0x00,
28780x42,0x18,0x03,0x00,0x44,0x51,0x03,0xae,0x21,0x10,0x05,0x02,0x01,0x00,0xa5,0x24,
28790x1d,0x00,0xa3,0x28,0xb6,0x51,0x40,0xa0,0x7c,0x51,0x40,0xa0,0xfa,0xff,0x60,0x14,
28800x99,0x51,0x40,0xa0,0x01,0x00,0x31,0x26,0x20,0x00,0x22,0x2a,0xd4,0x51,0x00,0xae,
28810xe9,0xff,0x40,0x14,0x94,0x00,0x10,0x26,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,
28820x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
28830xc8,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x30,0x00,0xbe,0xaf,0x28,0x00,0xb6,0xaf,
28840x68,0x15,0x46,0x24,0x34,0x00,0xbf,0xaf,0x2c,0x00,0xb7,0xaf,0x24,0x00,0xb5,0xaf,
28850x20,0x00,0xb4,0xaf,0x1c,0x00,0xb3,0xaf,0x18,0x00,0xb2,0xaf,0x14,0x00,0xb1,0xaf,
28860x10,0x00,0xb0,0xaf,0x8c,0x65,0xc2,0x8c,0xff,0x00,0x8d,0x30,0xff,0x00,0x03,0x24,
28870xff,0xff,0x42,0x38,0x21,0xf0,0x00,0x00,0xff,0xff,0x04,0x34,0x0a,0xf0,0x62,0x00,
28880x8c,0x65,0xc4,0xac,0xb0,0x00,0xa0,0x11,0x08,0x00,0x16,0x24,0x02,0x80,0x02,0x3c,
28890xb8,0x90,0x45,0x24,0x90,0x44,0xc4,0x24,0xff,0x4f,0x00,0x08,0x21,0x88,0x00,0x00,
28900x01,0x00,0x31,0x26,0x00,0x00,0x82,0xa0,0x1d,0x00,0x22,0x2a,0x0b,0x00,0x40,0x10,
28910x01,0x00,0x84,0x24,0x21,0x10,0x25,0x02,0x00,0x00,0x42,0x90,0x00,0x00,0x00,0x00,
28920xf7,0xff,0x40,0x10,0xfd,0xff,0x43,0x24,0x01,0x00,0x31,0x26,0x1d,0x00,0x22,0x2a,
28930x00,0x00,0x83,0xa0,0xf7,0xff,0x40,0x14,0x01,0x00,0x84,0x24,0x02,0x80,0x02,0x3c,
28940x68,0x15,0x4a,0x24,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x50,0x8e,0x6c,0x24,
28950xd8,0x8d,0x4b,0x24,0x21,0x88,0x00,0x00,0x21,0x48,0x00,0x00,0x21,0x30,0x00,0x00,
28960x21,0x40,0x2a,0x01,0x21,0x38,0x2c,0x01,0x21,0x10,0xe6,0x00,0x91,0x00,0x44,0x90,
28970x00,0x00,0x45,0x90,0x21,0x18,0x06,0x01,0x01,0x00,0xc6,0x24,0x05,0x00,0xc2,0x28,
28980xc5,0x43,0x64,0xa0,0xf8,0xff,0x40,0x14,0x34,0x43,0x65,0xa0,0x21,0x10,0x2b,0x02,
28990x1d,0x00,0x44,0x90,0x00,0x00,0x45,0x90,0x21,0x18,0x2a,0x02,0x01,0x00,0x31,0x26,
29000x1d,0x00,0x22,0x2a,0x73,0x44,0x64,0xa0,0x56,0x44,0x65,0xa0,0xeb,0xff,0x40,0x14,
29010x05,0x00,0x29,0x25,0xa6,0x00,0xa0,0x11,0x02,0x80,0x02,0x3c,0x68,0x15,0x48,0x24,
29020x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x4c,0x91,0x69,0x24,0xd8,0x90,0x47,0x24,
29030x21,0x88,0x00,0x00,0x80,0x18,0x11,0x00,0x21,0x10,0x69,0x00,0x21,0x20,0x67,0x00,
29040x00,0x00,0x46,0x8c,0x00,0x00,0x85,0x8c,0x01,0x00,0x31,0x26,0x21,0x18,0x68,0x00,
29050x04,0x00,0x22,0x2a,0xec,0x44,0x65,0xac,0xf6,0xff,0x40,0x14,0x60,0x45,0x66,0xac,
29060x02,0x80,0x02,0x3c,0x68,0x15,0x49,0x24,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,
29070x4c,0x91,0x68,0x24,0xd8,0x90,0x47,0x24,0x04,0x00,0x11,0x24,0x80,0x20,0x11,0x00,
29080x21,0x10,0x88,0x00,0x21,0x30,0x87,0x00,0x00,0x00,0x45,0x8c,0x00,0x00,0xc3,0x8c,
29090x01,0x00,0x31,0x26,0x21,0x20,0x89,0x00,0x82,0x28,0x05,0x00,0x82,0x18,0x03,0x00,
29100x1d,0x00,0x22,0x2a,0xec,0x44,0x83,0xac,0xf4,0xff,0x40,0x14,0x60,0x45,0x85,0xac,
29110x02,0x80,0x02,0x3c,0x68,0x15,0x55,0x24,0x21,0x88,0x00,0x00,0x21,0xb8,0xa0,0x02,
29120x21,0xa0,0x00,0x00,0x5a,0x50,0x00,0x08,0x21,0x90,0xa0,0x02,0x01,0x00,0x31,0x26,
29130x20,0x00,0x22,0x2a,0x94,0x00,0x52,0x26,0x38,0x00,0x40,0x10,0x94,0x00,0x94,0x26,
29140x78,0x51,0x44,0x8e,0x01,0x00,0x03,0x24,0x02,0x13,0x04,0x00,0x01,0x00,0x53,0x30,
29150xf6,0xff,0x63,0x16,0x07,0x00,0x82,0x30,0x25,0xb0,0x03,0x3c,0x80,0x10,0x02,0x00,
29160x21,0x10,0x43,0x00,0x84,0x01,0x45,0x8c,0x70,0x51,0x43,0x8e,0x21,0x20,0x20,0x02,
29170x24,0x28,0xa3,0x00,0xce,0x0d,0x00,0x0c,0x74,0x51,0x45,0xae,0x7a,0x51,0x44,0x92,
29180x5c,0x0d,0x00,0x0c,0xff,0x00,0x25,0x32,0x7a,0x51,0x50,0x92,0x00,0x00,0x00,0x00,
29190x21,0x20,0x00,0x02,0x63,0x0d,0x00,0x0c,0x80,0x80,0x10,0x00,0x21,0x80,0x17,0x02,
29200x48,0x51,0x40,0xae,0x4c,0x51,0x40,0xae,0x50,0x51,0x40,0xae,0x54,0x51,0x40,0xae,
29210x58,0x51,0x40,0xae,0x5c,0x51,0x40,0xae,0x60,0x51,0x40,0xae,0x64,0x51,0x40,0xae,
29220xec,0x44,0x04,0x8e,0x60,0x45,0x03,0x8e,0x26,0x10,0x53,0x00,0x21,0x30,0x00,0x00,
29230x21,0x18,0x64,0x00,0x42,0x18,0x03,0x00,0x04,0x00,0x04,0x24,0x0a,0xb0,0x82,0x00,
29240x44,0x51,0x43,0xae,0x21,0x20,0x95,0x02,0x21,0x10,0x86,0x00,0x01,0x00,0xc6,0x24,
29250x1d,0x00,0xc3,0x28,0xb6,0x51,0x40,0xa0,0x7c,0x51,0x40,0xa0,0xfa,0xff,0x60,0x14,
29260x99,0x51,0x40,0xa0,0x01,0x00,0x31,0x26,0x20,0x00,0x22,0x2a,0xd4,0x51,0x80,0xac,
29270x94,0x00,0x52,0x26,0xca,0xff,0x40,0x14,0x94,0x00,0x94,0x26,0x25,0xb0,0x02,0x3c,
29280x80,0x01,0x42,0x34,0x00,0x00,0x56,0xa0,0x03,0x00,0xc0,0x17,0x02,0x80,0x03,0x3c,
29290x68,0x15,0x62,0x24,0x8c,0x65,0x40,0xac,0x34,0x00,0xbf,0x8f,0x30,0x00,0xbe,0x8f,
29300x2c,0x00,0xb7,0x8f,0x28,0x00,0xb6,0x8f,0x24,0x00,0xb5,0x8f,0x20,0x00,0xb4,0x8f,
29310x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,
29320x08,0x00,0xe0,0x03,0x38,0x00,0xbd,0x27,0x02,0x80,0x02,0x3c,0xb8,0x90,0x45,0x24,
29330x90,0x44,0xc4,0x24,0x21,0x88,0x00,0x00,0x21,0x10,0x25,0x02,0x00,0x00,0x43,0x90,
29340x01,0x00,0x31,0x26,0x1d,0x00,0x22,0x2a,0x00,0x00,0x83,0xa0,0xfa,0xff,0x40,0x14,
29350x01,0x00,0x84,0x24,0x02,0x80,0x02,0x3c,0x68,0x15,0x4a,0x24,0x02,0x80,0x03,0x3c,
29360x02,0x80,0x02,0x3c,0x74,0x8f,0x6c,0x24,0x14,0x8e,0x4b,0x24,0x21,0x88,0x00,0x00,
29370x21,0x48,0x00,0x00,0x21,0x30,0x00,0x00,0x21,0x40,0x2a,0x01,0x21,0x38,0x2c,0x01,
29380x21,0x10,0xe6,0x00,0x91,0x00,0x44,0x90,0x00,0x00,0x45,0x90,0x21,0x18,0x06,0x01,
29390x01,0x00,0xc6,0x24,0x05,0x00,0xc2,0x28,0xc5,0x43,0x64,0xa0,0xf8,0xff,0x40,0x14,
29400x34,0x43,0x65,0xa0,0x21,0x10,0x2b,0x02,0x1d,0x00,0x44,0x90,0x00,0x00,0x45,0x90,
29410x21,0x18,0x2a,0x02,0x01,0x00,0x31,0x26,0x1d,0x00,0x22,0x2a,0x73,0x44,0x64,0xa0,
29420x56,0x44,0x65,0xa0,0xeb,0xff,0x40,0x14,0x05,0x00,0x29,0x25,0x02,0x80,0x02,0x3c,
29430x68,0x15,0x49,0x24,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x4c,0x91,0x68,0x24,
29440xd8,0x90,0x47,0x24,0x21,0x88,0x00,0x00,0x80,0x18,0x11,0x00,0x21,0x10,0x68,0x00,
29450x21,0x20,0x67,0x00,0x00,0x00,0x46,0x8c,0x00,0x00,0x85,0x8c,0x01,0x00,0x31,0x26,
29460x21,0x18,0x69,0x00,0x1d,0x00,0x22,0x2a,0xec,0x44,0x65,0xac,0xf6,0xff,0x40,0x14,
29470x60,0x45,0x66,0xac,0x4f,0x50,0x00,0x08,0x02,0x80,0x02,0x3c,0xd8,0xff,0xbd,0x27,
29480xff,0xff,0x84,0x30,0x18,0x00,0xb2,0xaf,0xf0,0x01,0x92,0x30,0x02,0x91,0x12,0x00,
29490x14,0x00,0xb1,0xaf,0xc0,0x88,0x12,0x00,0x21,0x88,0x32,0x02,0x80,0x88,0x11,0x00,
29500x21,0x88,0x32,0x02,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0x80,0x88,0x11,0x00,
29510x21,0x88,0x22,0x02,0x20,0x00,0xbf,0xaf,0x1c,0x00,0xb3,0xaf,0x10,0x00,0xb0,0xaf,
29520x78,0x51,0x30,0x8e,0x00,0x02,0x82,0x30,0xff,0xfe,0x03,0x24,0x2b,0x10,0x02,0x00,
29530x00,0x10,0x10,0x36,0x24,0x80,0x03,0x02,0x00,0x12,0x02,0x00,0x25,0x80,0x02,0x02,
29540x70,0x51,0x25,0xae,0x78,0x51,0x30,0xae,0xa0,0x0e,0x00,0x0c,0x21,0x98,0xa0,0x00,
29550xf8,0xff,0x03,0x24,0x24,0x80,0x03,0x02,0x07,0x00,0x42,0x30,0x25,0x80,0x02,0x02,
29560x07,0x00,0x03,0x32,0x25,0xb0,0x02,0x3c,0x80,0x18,0x03,0x00,0x78,0x51,0x30,0xae,
29570x21,0x18,0x62,0x00,0x84,0x01,0x62,0x8c,0x21,0x20,0x40,0x02,0x24,0x10,0x53,0x00,
29580xce,0x0d,0x00,0x0c,0x74,0x51,0x22,0xae,0x7a,0x51,0x24,0x92,0x21,0x28,0x40,0x02,
29590x20,0x00,0xbf,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
29600x10,0x00,0xb0,0x8f,0x5c,0x0d,0x00,0x08,0x28,0x00,0xbd,0x27,0xee,0x4e,0x00,0x08,
29610xff,0x00,0x84,0x30,0x02,0x80,0x02,0x3c,0x68,0x15,0x43,0x24,0x1f,0x00,0x04,0x24,
29620x78,0x51,0x62,0x8c,0xff,0xff,0x84,0x24,0x00,0x10,0x42,0x34,0x78,0x51,0x62,0xac,
29630xfb,0xff,0x81,0x04,0x94,0x00,0x63,0x24,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
29640x78,0xff,0xbd,0x27,0x60,0x00,0xb0,0xaf,0x25,0xb0,0x10,0x3c,0x70,0x00,0xb4,0xaf,
29650xc4,0x02,0x14,0x36,0x00,0x00,0x80,0xae,0x74,0x00,0xb5,0xaf,0x6c,0x00,0xb3,0xaf,
29660x68,0x00,0xb2,0xaf,0x64,0x00,0xb1,0xaf,0x84,0x00,0xbf,0xaf,0x80,0x00,0xbe,0xaf,
29670x7c,0x00,0xb7,0xaf,0x78,0x00,0xb6,0xaf,0x04,0x00,0x02,0x36,0x04,0x0c,0x13,0x36,
29680x00,0x00,0x43,0x8c,0x00,0x00,0x62,0x8e,0x0f,0x00,0x11,0x3c,0x24,0x18,0x71,0x00,
29690x08,0x0c,0x12,0x36,0x4c,0x00,0xa2,0xaf,0x02,0xac,0x03,0x00,0x00,0x00,0x43,0x8e,
29700x00,0x00,0x00,0x00,0x50,0x00,0xa3,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
29710x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x21,0x20,0x00,0x00,0xdd,0x44,0x00,0x0c,
29720xff,0xff,0x25,0x36,0x10,0x00,0xa2,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
29730x00,0x60,0x81,0x40,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x7a,0x42,0x00,0x0c,
29740x01,0x00,0x04,0x24,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
29750x00,0x60,0x81,0x40,0x21,0x20,0x00,0x00,0xdd,0x44,0x00,0x0c,0xff,0xff,0x25,0x36,
29760x14,0x00,0xa2,0xaf,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
29770xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x7a,0x42,0x00,0x0c,0x21,0x20,0x00,0x00,
29780xe0,0x0e,0x05,0x36,0x00,0x00,0xad,0x8c,0xdc,0x0e,0x06,0x36,0x70,0x0e,0x07,0x36,
29790x18,0x00,0xad,0xaf,0x00,0x00,0xc2,0x8c,0x74,0x0e,0x08,0x36,0x78,0x0e,0x09,0x36,
29800x1c,0x00,0xa2,0xaf,0x00,0x00,0xe3,0x8c,0x7c,0x0e,0x0a,0x36,0x80,0x0e,0x0b,0x36,
29810x20,0x00,0xa3,0xaf,0x00,0x00,0x0d,0x8d,0x84,0x0e,0x0c,0x36,0x88,0x0e,0x17,0x36,
29820x24,0x00,0xad,0xaf,0x00,0x00,0x22,0x8d,0x8c,0x0e,0x0e,0x36,0xd0,0x0e,0x18,0x36,
29830x28,0x00,0xa2,0xaf,0x00,0x00,0x43,0x8d,0xd8,0x0e,0x11,0x36,0xd4,0x0e,0x10,0x36,
29840x2c,0x00,0xa3,0xaf,0x00,0x00,0x6d,0x8d,0xed,0x3f,0x04,0x3c,0xfb,0x92,0x84,0x34,
29850x30,0x00,0xad,0xaf,0x00,0x00,0x82,0x8d,0x25,0xb0,0x1e,0x3c,0x21,0xb0,0x00,0x00,
29860x34,0x00,0xa2,0xaf,0x00,0x00,0xe3,0x8e,0xff,0x03,0x0f,0x3c,0x38,0x00,0xa3,0xaf,
29870x00,0x00,0xcd,0x8d,0x00,0x00,0x00,0x00,0x3c,0x00,0xad,0xaf,0x00,0x00,0x02,0x8f,
29880x00,0x00,0x00,0x00,0x40,0x00,0xa2,0xaf,0x00,0x00,0x03,0x8e,0x00,0x00,0x00,0x00,
29890x44,0x00,0xa3,0xaf,0x00,0x00,0x2d,0x8e,0x00,0x00,0x00,0x00,0x48,0x00,0xad,0xaf,
29900x00,0x00,0xa4,0xac,0x00,0x00,0xc4,0xac,0x00,0x00,0xe4,0xac,0x00,0x00,0x04,0xad,
29910x00,0x00,0x24,0xad,0x00,0x00,0x44,0xad,0x00,0x00,0x64,0xad,0x00,0x00,0x84,0xad,
29920x00,0x00,0xe4,0xae,0x00,0x00,0xc4,0xad,0x00,0x00,0x04,0xaf,0x00,0x00,0x04,0xae,
29930x00,0x00,0x24,0xae,0xd0,0x51,0x00,0x08,0x00,0x00,0x00,0x00,0x7a,0x00,0xa2,0x12,
29940x00,0x10,0x03,0x3c,0xac,0x0e,0xc2,0x37,0x94,0x0e,0xc3,0x37,0x25,0xb0,0x09,0x3c,
29950x00,0x00,0x4a,0x8c,0xbc,0x0e,0x29,0x35,0x00,0x00,0x64,0x8c,0xb4,0x0e,0xc2,0x37,
29960x9c,0x0e,0xc3,0x37,0x00,0x00,0x45,0x8c,0x00,0x00,0x66,0x8c,0x00,0x00,0x27,0x8d,
29970x24,0x20,0x8f,0x00,0x00,0xd8,0x02,0x3c,0x24,0x10,0x42,0x01,0x24,0x28,0xaf,0x00,
29980x24,0x30,0xcf,0x00,0x24,0x38,0xef,0x00,0x02,0x24,0x04,0x00,0x20,0x01,0x03,0x24,
29990x01,0x00,0x42,0x2c,0x02,0x2c,0x05,0x00,0x02,0x34,0x06,0x00,0xf2,0x00,0x83,0x10,
30000x02,0x3c,0x07,0x00,0xf0,0x00,0xa3,0x10,0x20,0x00,0x03,0x24,0xee,0x00,0xc3,0x10,
30010x00,0x00,0x00,0x00,0xec,0x00,0xe3,0x10,0x01,0x00,0x08,0x24,0x80,0x00,0x03,0x24,
30020x08,0x00,0x83,0x10,0x21,0x20,0x00,0x00,0x06,0x00,0xa3,0x10,0x21,0x20,0x00,0x00,
30030xe0,0x03,0x03,0x24,0x03,0x00,0xc3,0x10,0x00,0x00,0x00,0x00,0xe5,0x00,0xe3,0x10,
30040x01,0x00,0x04,0x24,0x06,0x00,0x40,0x10,0x09,0x00,0x02,0x24,0x04,0x00,0x00,0x11,
30050x00,0x00,0x00,0x00,0x6d,0x01,0x80,0x14,0x25,0xb0,0x12,0x3c,0x09,0x00,0x02,0x24,
30060xde,0x00,0xc2,0x12,0x25,0xb0,0x04,0x3c,0x01,0x00,0xd6,0x26,0x0a,0x00,0xc2,0x2e,
30070x1d,0x01,0x40,0x10,0x00,0x00,0x00,0x00,0xc8,0xff,0xa0,0x16,0x01,0x00,0x02,0x24,
30080xa0,0x00,0x03,0x3c,0x25,0xb0,0x09,0x3c,0x30,0x54,0x62,0x34,0x04,0x0c,0x29,0x35,
30090x00,0x00,0x22,0xad,0x25,0xb0,0x0d,0x3c,0x08,0x00,0x02,0x3c,0xe4,0x00,0x42,0x34,
30100x08,0x0c,0xad,0x35,0x25,0xb0,0x09,0x3c,0x00,0x00,0xa2,0xad,0x28,0x0e,0x29,0x35,
30110x80,0x80,0x02,0x3c,0x00,0x00,0x22,0xad,0x14,0x02,0x04,0x3c,0x16,0x68,0x02,0x3c,
30120x48,0x01,0x83,0x34,0x40,0x0e,0xc5,0x37,0x44,0x0e,0xc6,0x37,0xa2,0x04,0x42,0x34,
30130x25,0xb0,0x0d,0x3c,0x00,0x00,0xa3,0xac,0x4c,0x0e,0xad,0x35,0x00,0x00,0xc2,0xac,
30140xd1,0x28,0x02,0x24,0x00,0x00,0xa2,0xad,0x14,0x02,0x03,0x3c,0x16,0x28,0x02,0x3c,
30150x4d,0x01,0x63,0x34,0x60,0x0e,0xc7,0x37,0x64,0x0e,0xc8,0x37,0xba,0x08,0x42,0x34,
30160x00,0x00,0xe3,0xac,0x25,0xb0,0x06,0x3c,0x00,0x00,0x02,0xad,0x00,0xfb,0x0d,0x3c,
30170x25,0xb0,0x09,0x3c,0x00,0xf8,0x02,0x3c,0xd1,0x28,0x07,0x24,0x6c,0x0e,0xc6,0x34,
30180x48,0x0e,0x29,0x35,0x01,0x00,0x42,0x34,0x01,0x00,0xad,0x35,0x00,0x00,0xc7,0xac,
30190x03,0x00,0x04,0x24,0x00,0x00,0x2d,0xad,0x00,0x00,0x22,0xad,0x84,0x0a,0x00,0x0c,
30200x58,0x00,0xaf,0xaf,0xa0,0x00,0x04,0x3c,0x25,0xb0,0x03,0x3c,0x25,0xb0,0x06,0x3c,
30210x25,0xb0,0x07,0x3c,0xe4,0x00,0x02,0x24,0x33,0x54,0x84,0x34,0x04,0x0c,0x63,0x34,
30220x08,0x0c,0xc6,0x34,0x28,0x0e,0xe7,0x34,0x00,0x00,0x64,0xac,0x00,0x00,0xc2,0xac,
30230x00,0x00,0xe0,0xac,0x01,0x00,0x02,0x24,0x58,0x00,0xaf,0x8f,0x8a,0xff,0xa2,0x16,
30240xac,0x0e,0xc2,0x37,0x00,0x10,0x03,0x3c,0x1f,0xdc,0x79,0x34,0x1f,0x8c,0x7f,0x34,
30250x23,0x8c,0x6d,0x34,0xa0,0x00,0x03,0x3c,0x30,0x54,0x65,0x34,0x00,0x01,0x17,0x3c,
30260x25,0xb0,0x09,0x3c,0x25,0xb0,0x03,0x3c,0x00,0x01,0xe2,0x36,0x20,0x08,0x29,0x35,
30270x20,0x08,0x63,0x34,0x00,0x00,0x30,0x8d,0x00,0x00,0x62,0xac,0x25,0xb0,0x03,0x3c,
30280x28,0x08,0x63,0x34,0x00,0x00,0x62,0xac,0x25,0xb0,0x02,0x3c,0x04,0x0c,0x42,0x34,
30290x00,0x00,0x45,0xac,0x25,0xb0,0x03,0x3c,0x08,0x00,0x02,0x3c,0xe4,0x00,0x42,0x34,
30300x08,0x0c,0x63,0x34,0x00,0x00,0x62,0xac,0x25,0xb0,0x03,0x3c,0x00,0x7c,0xf3,0x36,
30310x00,0x48,0xf4,0x36,0x30,0x0e,0xc6,0x37,0x34,0x0e,0xc7,0x37,0x80,0x80,0x02,0x3c,
30320x28,0x0e,0x63,0x34,0x00,0x00,0x62,0xac,0x00,0x00,0xd3,0xac,0x00,0x00,0xf4,0xac,
30330x14,0x02,0x06,0x3c,0x16,0x68,0x07,0x3c,0x38,0x0e,0xc8,0x37,0x40,0x0e,0xca,0x37,
30340x44,0x0e,0xcb,0x37,0x3c,0x0e,0xc9,0x37,0x02,0x01,0xc6,0x34,0xc7,0x04,0xe7,0x34,
30350x00,0x00,0x19,0xad,0x25,0xb0,0x03,0x3c,0x00,0x00,0x3f,0xad,0x00,0x00,0x46,0xad,
30360x25,0xb0,0x09,0x3c,0x00,0x00,0x67,0xad,0x25,0xb0,0x06,0x3c,0x00,0x10,0x07,0x3c,
30370x50,0x0e,0xcc,0x37,0x58,0x0e,0xce,0x37,0x5c,0x0e,0xd8,0x37,0xd1,0x28,0x02,0x24,
30380x23,0xdc,0xe7,0x34,0x4c,0x0e,0x29,0x35,0x6c,0x0e,0x63,0x34,0x54,0x0e,0xc6,0x34,
30390x00,0x00,0x22,0xad,0x00,0x00,0x62,0xac,0x14,0x02,0x09,0x3c,0x00,0x00,0x93,0xad,
30400x25,0xb0,0x02,0x3c,0x00,0x00,0xd4,0xac,0x00,0x00,0xc7,0xad,0x00,0x00,0x0d,0xaf,
30410x16,0x28,0x0d,0x3c,0x48,0x0e,0x42,0x34,0x00,0xf8,0x06,0x3c,0x02,0x01,0x29,0x35,
30420x07,0x0d,0xad,0x35,0x00,0xfb,0x03,0x3c,0x60,0x0e,0xd1,0x37,0x64,0x0e,0xd2,0x37,
30430x00,0x00,0x29,0xae,0x03,0x00,0x04,0x24,0x00,0x00,0x4d,0xae,0x00,0x00,0x43,0xac,
30440x00,0x00,0x46,0xac,0x84,0x0a,0x00,0x0c,0x58,0x00,0xaf,0xaf,0x00,0x02,0x02,0x3c,
30450x25,0xb0,0x07,0x3c,0x25,0xb0,0x09,0x3c,0xd1,0x28,0x42,0x34,0x4c,0x0e,0xe7,0x34,
30460x6c,0x0e,0x29,0x35,0x25,0xb0,0x0d,0x3c,0x00,0x00,0xe2,0xac,0x48,0x0e,0xad,0x35,
30470x00,0x00,0x22,0xad,0x00,0xf8,0x03,0x3c,0x00,0xfb,0x02,0x3c,0x00,0x00,0xa2,0xad,
30480x03,0x00,0x04,0x24,0x00,0x00,0xa3,0xad,0x84,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,
30490x4c,0x00,0xa6,0x8f,0x25,0xb0,0x04,0x3c,0x04,0x0c,0x84,0x34,0x00,0x00,0x86,0xac,
30500x50,0x00,0xa9,0x8f,0x25,0xb0,0x07,0x3c,0x25,0xb0,0x0d,0x3c,0x00,0x01,0x10,0x32,
30510x08,0x0c,0xe7,0x34,0x28,0x0e,0xad,0x35,0x00,0x00,0xe9,0xac,0x2b,0x80,0x10,0x00,
30520x00,0x00,0xa0,0xad,0x58,0x00,0xaf,0x8f,0x17,0xff,0x00,0x16,0xac,0x0e,0xc2,0x37,
30530x25,0xb0,0x02,0x3c,0x25,0xb0,0x03,0x3c,0x20,0x08,0x42,0x34,0x28,0x08,0x63,0x34,
30540x00,0x00,0x57,0xac,0x25,0xb0,0x09,0x3c,0x00,0x00,0x77,0xac,0xac,0x0e,0xc2,0x37,
30550x94,0x0e,0xc3,0x37,0x00,0x00,0x4a,0x8c,0xbc,0x0e,0x29,0x35,0x00,0x00,0x64,0x8c,
30560xb4,0x0e,0xc2,0x37,0x9c,0x0e,0xc3,0x37,0x00,0x00,0x45,0x8c,0x00,0x00,0x66,0x8c,
30570x00,0x00,0x27,0x8d,0x24,0x20,0x8f,0x00,0x00,0xd8,0x02,0x3c,0x24,0x10,0x42,0x01,
30580x24,0x28,0xaf,0x00,0x24,0x30,0xcf,0x00,0x24,0x38,0xef,0x00,0x02,0x24,0x04,0x00,
30590x20,0x01,0x03,0x24,0x01,0x00,0x42,0x2c,0x02,0x2c,0x05,0x00,0x02,0x34,0x06,0x00,
30600x10,0xff,0x83,0x14,0x02,0x3c,0x07,0x00,0x80,0x00,0x03,0x24,0x16,0xff,0x83,0x14,
30610x21,0x40,0x00,0x00,0xc3,0x51,0x00,0x08,0x21,0x20,0x00,0x00,0xff,0xff,0x02,0x34,
30620xc4,0x02,0x84,0x34,0x00,0x00,0x82,0xac,0x94,0x0e,0xc3,0x37,0x9c,0x0e,0xc2,0x37,
30630xa4,0x0e,0xc4,0x37,0xac,0x0e,0xc7,0x37,0x00,0x00,0x66,0x8c,0x00,0x00,0x49,0x8c,
30640x00,0x00,0x8b,0x8c,0x00,0x00,0xe5,0x8c,0x02,0x80,0x07,0x3c,0x68,0x15,0xe7,0x24,
30650x0c,0x40,0xe3,0x8c,0x10,0x40,0xe4,0x8c,0xb4,0x0e,0xc2,0x37,0x00,0x00,0x47,0x8c,
30660x25,0xb0,0x0d,0x3c,0x00,0xfc,0x02,0x24,0x24,0x30,0xcf,0x00,0x24,0x28,0xaf,0x00,
30670xbc,0x0e,0xad,0x35,0x00,0x00,0xa8,0x8d,0x24,0x20,0x82,0x00,0x02,0x34,0x06,0x00,
30680x24,0x18,0x62,0x00,0x02,0x2c,0x05,0x00,0xc4,0x0e,0xca,0x37,0xcc,0x0e,0xcc,0x37,
30690xf0,0xff,0x02,0x3c,0xff,0x03,0x42,0x34,0x25,0x18,0x66,0x00,0x25,0x20,0x85,0x00,
30700x00,0x00,0x46,0x8d,0x24,0x48,0x2f,0x01,0x00,0x00,0x85,0x8d,0x24,0x38,0xef,0x00,
30710x24,0x20,0x82,0x00,0x24,0x18,0x62,0x00,0x82,0x49,0x09,0x00,0x82,0x39,0x07,0x00,
30720x0f,0xc0,0x02,0x3c,0xff,0xff,0x42,0x34,0x25,0x18,0x69,0x00,0x25,0x20,0x87,0x00,
30730x24,0x58,0x6f,0x01,0x24,0x40,0x0f,0x01,0x24,0x20,0x82,0x00,0x24,0x18,0x62,0x00,
30740x00,0x59,0x0b,0x00,0x00,0x41,0x08,0x00,0x24,0x30,0xcf,0x00,0x24,0x28,0xaf,0x00,
30750x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,0x25,0x18,0x6b,0x00,0x25,0x20,0x88,0x00,
30760x02,0x34,0x06,0x00,0x02,0x2c,0x05,0x00,0x01,0x00,0xd6,0x26,0x0c,0x40,0x43,0xac,
30770x10,0x40,0x44,0xac,0x14,0x40,0x46,0xa4,0x16,0x40,0x45,0xa4,0x0a,0x00,0xc2,0x2e,
30780xe5,0xfe,0x40,0x14,0x00,0x00,0x00,0x00,0x18,0x00,0xad,0x8f,0x25,0xb0,0x02,0x3c,
30790xe0,0x0e,0x43,0x34,0x10,0x00,0xa6,0x8f,0x00,0x00,0x6d,0xac,0x1c,0x00,0xa3,0x8f,
30800xdc,0x0e,0x47,0x34,0x70,0x0e,0x48,0x34,0x00,0x00,0xe3,0xac,0x20,0x00,0xa7,0x8f,
30810x74,0x0e,0x49,0x34,0x78,0x0e,0x4a,0x34,0x00,0x00,0x07,0xad,0x24,0x00,0xad,0x8f,
30820x7c,0x0e,0x4b,0x34,0x80,0x0e,0x4c,0x34,0x00,0x00,0x2d,0xad,0x28,0x00,0xa3,0x8f,
30830x25,0xb0,0x0d,0x3c,0x84,0x0e,0xad,0x35,0x00,0x00,0x43,0xad,0x2c,0x00,0xa7,0x8f,
30840x88,0x0e,0x52,0x34,0x8c,0x0e,0x4e,0x34,0x00,0x00,0x67,0xad,0x30,0x00,0xa9,0x8f,
30850xd4,0x0e,0x51,0x34,0xd0,0x0e,0x42,0x34,0x00,0x00,0x89,0xad,0x34,0x00,0xa3,0x8f,
30860x0f,0x00,0x10,0x3c,0xff,0xff,0x05,0x36,0x00,0x00,0xa3,0xad,0x38,0x00,0xa7,0x8f,
30870x21,0x20,0x00,0x00,0x00,0x00,0x47,0xae,0x3c,0x00,0xa9,0x8f,0x00,0x00,0x00,0x00,
30880x00,0x00,0xc9,0xad,0x40,0x00,0xad,0x8f,0x00,0x00,0x00,0x00,0x00,0x00,0x4d,0xac,
30890x44,0x00,0xa2,0x8f,0x00,0x00,0x00,0x00,0x00,0x00,0x22,0xae,0x48,0x00,0xa3,0x8f,
30900x00,0x00,0x00,0x00,0x00,0x00,0x43,0xae,0xba,0x44,0x00,0x0c,0x00,0x00,0x00,0x00,
30910xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x7a,0x42,0x00,0x0c,0x01,0x00,0x04,0x24,
30920x14,0x00,0xa6,0x8f,0xff,0xff,0x05,0x36,0xba,0x44,0x00,0x0c,0x21,0x20,0x00,0x00,
30930xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x84,0x00,0xbf,0x8f,0x80,0x00,0xbe,0x8f,
30940x7c,0x00,0xb7,0x8f,0x78,0x00,0xb6,0x8f,0x74,0x00,0xb5,0x8f,0x70,0x00,0xb4,0x8f,
30950x6c,0x00,0xb3,0x8f,0x68,0x00,0xb2,0x8f,0x64,0x00,0xb1,0x8f,0x60,0x00,0xb0,0x8f,
30960x21,0x20,0x00,0x00,0x7a,0x42,0x00,0x08,0x88,0x00,0xbd,0x27,0x94,0x0e,0x42,0x36,
30970x9c,0x0e,0x43,0x36,0xa4,0x0e,0x44,0x36,0xac,0x0e,0x45,0x36,0x02,0x80,0x0d,0x3c,
30980x00,0x00,0x47,0x8c,0x68,0x15,0xad,0x25,0x00,0x00,0x6a,0x8c,0x00,0x00,0x8c,0x8c,
30990x00,0x00,0xa3,0x8c,0x10,0x40,0xa4,0x8d,0xb4,0x0e,0x42,0x36,0x00,0x00,0x48,0x8c,
31000x0c,0x40,0xa5,0x8d,0x25,0xb0,0x02,0x3c,0x00,0xfc,0x13,0x24,0xbc,0x0e,0x42,0x34,
31010x24,0x18,0x6f,0x00,0x00,0x00,0x49,0x8c,0x02,0x1c,0x03,0x00,0x24,0x38,0xef,0x00,
31020x24,0x20,0x93,0x00,0xf0,0xff,0x06,0x3c,0x25,0x20,0x83,0x00,0xff,0x03,0xc6,0x34,
31030x02,0x3c,0x07,0x00,0xc4,0x0e,0x42,0x36,0x24,0x28,0xb3,0x00,0x24,0x40,0x0f,0x01,
31040xcc,0x0e,0x4b,0x36,0x25,0x28,0xa7,0x00,0x24,0x20,0x86,0x00,0x00,0x00,0x47,0x8c,
31050x24,0x50,0x4f,0x01,0x00,0x00,0x63,0x8d,0x82,0x41,0x08,0x00,0x0f,0xc0,0x02,0x3c,
31060xff,0xff,0x42,0x34,0x25,0x20,0x88,0x00,0x82,0x51,0x0a,0x00,0x24,0x28,0xa6,0x00,
31070x24,0x48,0x2f,0x01,0x24,0x88,0x82,0x00,0x25,0x28,0xaa,0x00,0x24,0x60,0x8f,0x01,
31080x00,0x49,0x09,0x00,0x25,0x88,0x29,0x02,0x24,0x28,0xa2,0x00,0x24,0x18,0x6f,0x00,
31090x00,0x61,0x0c,0x00,0x24,0x38,0xef,0x00,0x25,0x28,0xac,0x00,0x02,0x3c,0x07,0x00,
31100x02,0x1c,0x03,0x00,0x82,0x27,0x11,0x00,0x01,0x00,0x02,0x24,0x16,0x40,0xa3,0xa5,
31110x14,0x40,0xa7,0xa5,0x0c,0x40,0xa5,0xad,0x4a,0x00,0x82,0x10,0x10,0x40,0xb1,0xad,
31120x80,0x0c,0x4c,0x36,0x00,0x00,0x8a,0x8d,0x82,0x72,0x05,0x00,0xff,0x03,0xce,0x31,
31130x00,0x02,0xc3,0x31,0x25,0x10,0xd3,0x01,0x0b,0x70,0x43,0x00,0x82,0x85,0x0a,0x00,
31140x18,0x00,0xd0,0x01,0xff,0x03,0xaf,0x30,0x00,0x02,0xa3,0x30,0x25,0x10,0xf3,0x01,
31150x0b,0x78,0x43,0x00,0x02,0x75,0x11,0x00,0xff,0x03,0xce,0x31,0xc0,0xff,0x08,0x3c,
31160x25,0x18,0xd3,0x01,0x00,0x02,0xc2,0x31,0x00,0xfc,0x06,0x35,0x0b,0x70,0x62,0x00,
31170x24,0x38,0x46,0x01,0x94,0x0c,0x4a,0x36,0xff,0x0f,0x09,0x3c,0xff,0xff,0x29,0x35,
31180x88,0x0c,0x54,0x36,0x12,0x20,0x00,0x00,0x02,0x22,0x04,0x00,0x3f,0x00,0x82,0x30,
31190x18,0x00,0xf0,0x01,0x82,0x7a,0x11,0x00,0xff,0x03,0xef,0x31,0x00,0x14,0x02,0x00,
31200x25,0x38,0xe2,0x00,0x00,0x02,0xe3,0x31,0x25,0x10,0xf3,0x01,0x0b,0x78,0x43,0x00,
31210xc0,0x03,0x84,0x30,0x80,0x25,0x04,0x00,0x9c,0x0c,0x4b,0x36,0x12,0x28,0x00,0x00,
31220x02,0x2a,0x05,0x00,0xff,0x03,0xa2,0x30,0x25,0x10,0xe2,0x00,0x00,0x00,0x82,0xad,
31230x00,0x00,0x42,0x8d,0x00,0x00,0x00,0x00,0x24,0x10,0x49,0x00,0x25,0x10,0x44,0x00,
31240x00,0x00,0x42,0xad,0x00,0x00,0x8a,0x8e,0x00,0x00,0x00,0x00,0x24,0x40,0x48,0x01,
31250x82,0x85,0x08,0x00,0x18,0x00,0xd0,0x01,0x24,0x30,0x46,0x01,0x12,0x18,0x00,0x00,
31260x02,0x1a,0x03,0x00,0x3f,0x00,0x62,0x30,0x18,0x00,0xf0,0x01,0x00,0x14,0x02,0x00,
31270x25,0x30,0xc2,0x00,0xc0,0x03,0x63,0x30,0x80,0x1d,0x03,0x00,0x12,0x20,0x00,0x00,
31280x02,0x22,0x04,0x00,0xff,0x03,0x82,0x30,0x25,0x10,0xc2,0x00,0x00,0x00,0x82,0xae,
31290x00,0x00,0x62,0x8d,0x00,0x00,0x00,0x00,0x24,0x10,0x49,0x00,0x25,0x10,0x43,0x00,
31300x00,0x00,0x62,0xad,0x00,0x17,0x16,0x00,0x25,0xb0,0x03,0x3c,0xdd,0xdd,0x42,0x34,
31310xc4,0x02,0x63,0x34,0x00,0x00,0x62,0xac,0xec,0x52,0x00,0x08,0x00,0x00,0x00,0x00,
31320xe0,0xff,0xbd,0x27,0x44,0x00,0x02,0x24,0x10,0x00,0xa2,0xa3,0x49,0x00,0x03,0x24,
31330x47,0x00,0x02,0x24,0x02,0x80,0x07,0x3c,0x8c,0x97,0xe7,0x24,0x11,0x00,0xa3,0xa3,
31340x12,0x00,0xa2,0xa3,0x10,0x27,0x03,0x24,0x01,0x00,0x02,0x24,0x01,0x80,0x06,0x3c,
31350x10,0x00,0xa5,0x27,0x21,0x20,0xe0,0x00,0xe8,0x51,0xc6,0x24,0x0c,0x00,0xe3,0xac,
31360x14,0x00,0xe2,0xa0,0x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,0x13,0x00,0xa0,0xa3,
31370x18,0x00,0xbf,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,
31380xd0,0xff,0xbd,0x27,0x25,0xb0,0x02,0x3c,0x20,0x00,0xb4,0xaf,0x1c,0x00,0xb3,0xaf,
31390x03,0x0d,0x44,0x34,0x2c,0x00,0xbf,0xaf,0x28,0x00,0xb6,0xaf,0x24,0x00,0xb5,0xaf,
31400x18,0x00,0xb2,0xaf,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x00,0x83,0x90,
31410x42,0x00,0x45,0x34,0xff,0x00,0x73,0x30,0x70,0x00,0x74,0x32,0x29,0x00,0x80,0x16,
31420x8f,0x00,0x62,0x32,0xff,0xff,0x02,0x24,0x00,0x00,0xa2,0xa0,0x00,0x60,0x01,0x40,
31430x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x0f,0x00,0x11,0x3c,
31440x18,0x00,0x04,0x24,0xdd,0x44,0x00,0x0c,0xff,0xff,0x25,0x36,0x21,0x80,0x40,0x00,
31450x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0xb3,0x0a,0x00,0x0c,
31460x64,0x00,0x04,0x24,0x00,0x80,0x06,0x36,0xff,0xff,0x25,0x36,0xba,0x44,0x00,0x0c,
31470x18,0x00,0x04,0x24,0x84,0x0a,0x00,0x0c,0x03,0x00,0x04,0x24,0x21,0x30,0xa0,0x02,
31480xff,0xff,0x25,0x36,0x5c,0x00,0x80,0x16,0x21,0x20,0x00,0x00,0x2c,0x00,0xbf,0x8f,
31490x28,0x00,0xb6,0x8f,0x24,0x00,0xb5,0x8f,0x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,
31500x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,0x25,0xb0,0x02,0x3c,
31510x42,0x00,0x42,0x34,0x30,0x00,0xbd,0x27,0x00,0x00,0x40,0xa0,0x08,0x00,0xe0,0x03,
31520x00,0x00,0x00,0x00,0x00,0x00,0x82,0xa0,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
31530x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x0f,0x00,0x11,0x3c,0x21,0x20,0x00,0x00,
31540xdd,0x44,0x00,0x0c,0xff,0xff,0x25,0x36,0x21,0xa8,0x40,0x00,0x00,0x60,0x01,0x40,
31550x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,
31560x7a,0x42,0x00,0x0c,0x01,0x00,0x04,0x24,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
31570x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x21,0x20,0x00,0x00,0xdd,0x44,0x00,0x0c,
31580xff,0xff,0x25,0x36,0x21,0xb0,0x40,0x00,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
31590x00,0x60,0x81,0x40,0x64,0x00,0x04,0x24,0xb3,0x0a,0x00,0x0c,0x08,0x00,0x10,0x3c,
31600xff,0xff,0x10,0x36,0x7a,0x42,0x00,0x0c,0x21,0x20,0x00,0x00,0x01,0x00,0x12,0x3c,
31610x24,0x30,0xb0,0x02,0x25,0x30,0xd2,0x00,0xff,0xff,0x25,0x36,0xba,0x44,0x00,0x0c,
31620x21,0x20,0x00,0x00,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0x24,0x80,0xd0,0x02,
31630x7a,0x42,0x00,0x0c,0x01,0x00,0x04,0x24,0x25,0x30,0x12,0x02,0xff,0xff,0x25,0x36,
31640xba,0x44,0x00,0x0c,0x21,0x20,0x00,0x00,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,
31650x7a,0x42,0x00,0x0c,0x21,0x20,0x00,0x00,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,
31660x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x0f,0x00,0x11,0x3c,0x18,0x00,0x04,0x24,
31670xdd,0x44,0x00,0x0c,0xff,0xff,0x25,0x36,0x21,0x80,0x40,0x00,0x00,0x60,0x01,0x40,
31680x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,
31690x00,0x80,0x06,0x36,0xff,0xff,0x25,0x36,0xba,0x44,0x00,0x0c,0x18,0x00,0x04,0x24,
31700x84,0x0a,0x00,0x0c,0x03,0x00,0x04,0x24,0x21,0x30,0xa0,0x02,0xff,0xff,0x25,0x36,
31710xa6,0xff,0x80,0x12,0x21,0x20,0x00,0x00,0x25,0xb0,0x02,0x3c,0x03,0x0d,0x42,0x34,
31720x00,0x00,0x53,0xa0,0xba,0x44,0x00,0x0c,0x00,0x00,0x00,0x00,0xb3,0x0a,0x00,0x0c,
31730x64,0x00,0x04,0x24,0x7a,0x42,0x00,0x0c,0x01,0x00,0x04,0x24,0xff,0xff,0x25,0x36,
31740x21,0x30,0xc0,0x02,0xba,0x44,0x00,0x0c,0x21,0x20,0x00,0x00,0xb3,0x0a,0x00,0x0c,
31750x64,0x00,0x04,0x24,0x2c,0x00,0xbf,0x8f,0x28,0x00,0xb6,0x8f,0x24,0x00,0xb5,0x8f,
31760x20,0x00,0xb4,0x8f,0x1c,0x00,0xb3,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
31770x10,0x00,0xb0,0x8f,0x21,0x20,0x00,0x00,0x7a,0x42,0x00,0x08,0x30,0x00,0xbd,0x27,
31780xd0,0xff,0xbd,0x27,0x28,0x00,0xb4,0xaf,0x02,0x80,0x14,0x3c,0x2c,0x00,0xbf,0xaf,
31790x24,0x00,0xb3,0xaf,0x20,0x00,0xb2,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,
31800x68,0x15,0x86,0x26,0x0c,0x40,0xc2,0x8c,0x00,0x00,0x00,0x00,0x82,0x17,0x02,0x00,
31810x01,0x00,0x42,0x30,0x07,0x00,0x40,0x14,0x68,0x15,0x85,0x26,0x08,0x40,0xc2,0x8c,
31820x01,0x00,0x03,0x24,0x42,0x17,0x02,0x00,0x03,0x00,0x42,0x30,0xf0,0x00,0x43,0x10,
31830x25,0xb0,0x02,0x3c,0x0c,0x40,0xa2,0x8c,0x01,0x00,0x03,0x24,0x82,0x17,0x02,0x00,
31840x01,0x00,0x44,0x30,0x0a,0x00,0x83,0x10,0x00,0x00,0x00,0x00,0x2c,0x00,0xbf,0x8f,
31850x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,
31860x18,0x00,0xb0,0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,
31870x08,0x40,0xa2,0x8c,0x00,0x00,0x00,0x00,0x42,0x17,0x02,0x00,0x03,0x00,0x42,0x30,
31880xf2,0xff,0x44,0x14,0x25,0xb0,0x02,0x3c,0x0e,0x0c,0x44,0x34,0x00,0x00,0x83,0x90,
31890x00,0x01,0x02,0x24,0xff,0x00,0x63,0x30,0x01,0x00,0x63,0x24,0x8b,0x01,0x62,0x10,
31900x00,0x00,0x00,0x00,0x00,0x00,0x83,0xa0,0x68,0x15,0x84,0x26,0x10,0x40,0x82,0x8c,
31910x01,0x00,0x03,0x24,0x82,0x17,0x02,0x00,0xa4,0x01,0x43,0x10,0x0f,0x00,0x10,0x3c,
31920xc7,0x42,0x92,0x90,0x68,0x15,0x90,0x26,0xc6,0x42,0x03,0x92,0x25,0xb0,0x11,0x3c,
31930x62,0x0c,0x22,0x36,0x00,0x00,0x52,0xa0,0x17,0x01,0x60,0x10,0x01,0x00,0x02,0x24,
31940x03,0x0d,0x23,0x36,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x70,0x00,0x42,0x30,
31950x3e,0x01,0x40,0x14,0x63,0x0c,0x23,0x36,0xc4,0x42,0x02,0x96,0x00,0x00,0x00,0x00,
31960x23,0x20,0x52,0x00,0x2b,0x18,0x52,0x00,0x23,0x10,0x42,0x02,0x0a,0x10,0x83,0x00,
31970x03,0x00,0x42,0x2c,0x0b,0x01,0x40,0x10,0x00,0x00,0x00,0x00,0xc4,0x42,0x03,0x96,
31980x63,0x0c,0x22,0x36,0x00,0x00,0x43,0xa0,0x68,0x15,0x83,0x26,0xc3,0x42,0x62,0x90,
31990x08,0x40,0x66,0x8c,0xc2,0x42,0x72,0xa0,0x23,0x20,0x52,0x00,0x2b,0x38,0x42,0x02,
32000x23,0x50,0x42,0x02,0x02,0x2c,0x06,0x00,0x0b,0x50,0x87,0x00,0x3f,0x00,0xa5,0x30,
32010x3f,0x00,0xc4,0x30,0x24,0x00,0x02,0x24,0x20,0x00,0x03,0x24,0x23,0x10,0x44,0x00,
32020x2d,0x01,0x40,0x15,0x23,0x18,0x65,0x00,0x21,0x30,0x80,0x00,0x21,0x48,0xa0,0x00,
32030x02,0x80,0x0b,0x3c,0x68,0x15,0x83,0x26,0x80,0x10,0x06,0x00,0x21,0x10,0x43,0x00,
32040x0c,0x40,0x63,0x8c,0x18,0x40,0x44,0x8c,0xff,0x03,0x67,0x30,0x1b,0x01,0xe0,0x10,
32050x82,0x2d,0x04,0x00,0x00,0x02,0x62,0x30,0x04,0x00,0x40,0x10,0x18,0x00,0xe5,0x00,
32060x00,0xfc,0x02,0x24,0x25,0x38,0xe2,0x00,0x18,0x00,0xe5,0x00,0x82,0x22,0x03,0x00,
32070xff,0x03,0x84,0x30,0x00,0x02,0x83,0x30,0x12,0x10,0x00,0x00,0x02,0x12,0x02,0x00,
32080x03,0x00,0x60,0x10,0xff,0x03,0x48,0x30,0x00,0xfc,0x02,0x24,0x25,0x20,0x82,0x00,
32090x18,0x00,0x85,0x00,0x80,0x2d,0x05,0x00,0x25,0xb0,0x06,0x3c,0x80,0x0c,0xc7,0x34,
32100x94,0x0c,0xc6,0x34,0x12,0x20,0x00,0x00,0x02,0x22,0x04,0x00,0x3f,0x00,0x82,0x30,
32110x00,0x14,0x02,0x00,0x25,0x28,0xa2,0x00,0x25,0x28,0xa8,0x00,0x10,0x00,0xa5,0xaf,
32120x00,0x00,0xe5,0xac,0x00,0x00,0xc3,0x8c,0xff,0x0f,0x02,0x3c,0xc0,0x03,0x84,0x30,
32130xff,0xff,0x42,0x34,0x80,0x25,0x04,0x00,0x24,0x18,0x62,0x00,0x25,0x18,0x64,0x00,
32140x10,0x00,0xa3,0xaf,0x00,0x00,0xc3,0xac,0x68,0x15,0x83,0x26,0x08,0x40,0x62,0x8c,
32150x00,0x00,0x00,0x00,0x08,0x01,0x40,0x04,0xc0,0x28,0x09,0x00,0x21,0x28,0xa3,0x00,
32160xac,0x40,0xa3,0x90,0x25,0xb0,0x04,0x3c,0x22,0x0a,0x82,0x34,0x00,0x00,0x43,0xa0,
32170xad,0x40,0xa6,0x90,0x23,0x0a,0x82,0x34,0x24,0x0a,0x87,0x34,0x00,0x00,0x46,0xa0,
32180xae,0x40,0xa3,0x90,0x25,0x0a,0x86,0x34,0x26,0x0a,0x88,0x34,0x00,0x00,0xe3,0xa0,
32190xaf,0x40,0xa2,0x90,0x27,0x0a,0x87,0x34,0x28,0x0a,0x89,0x34,0x00,0x00,0xc2,0xa0,
32200xb0,0x40,0xa3,0x90,0x29,0x0a,0x84,0x34,0x00,0x00,0x03,0xa1,0xb1,0x40,0xa2,0x90,
32210x00,0x00,0x00,0x00,0x00,0x00,0xe2,0xa0,0xb2,0x40,0xa3,0x90,0x00,0x00,0x00,0x00,
32220x00,0x00,0x23,0xa1,0xb3,0x40,0xa2,0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0xa0,
32230x8e,0x7d,0x63,0x91,0x22,0x00,0x02,0x24,0x03,0x00,0x62,0x10,0x92,0x00,0x02,0x24,
32240x62,0xff,0x62,0x14,0x00,0x00,0x00,0x00,0x68,0x15,0x82,0x26,0x08,0x40,0x43,0x8c,
32250x01,0x00,0x44,0x39,0x24,0x00,0x02,0x24,0x02,0x1a,0x03,0x00,0x3f,0x00,0x63,0x30,
32260x01,0x00,0x84,0x30,0x04,0x01,0x80,0x10,0x23,0x28,0x43,0x00,0x42,0x18,0x0a,0x00,
32270x40,0x10,0x03,0x00,0x21,0x50,0x43,0x00,0x68,0x15,0x83,0x26,0xc3,0x42,0x62,0x90,
32280x00,0x00,0x00,0x00,0x2b,0x10,0x42,0x02,0x08,0x01,0x40,0x10,0x21,0x20,0x00,0x00,
32290x2b,0x10,0x45,0x01,0x07,0x00,0x40,0x10,0x24,0x00,0x04,0x24,0x08,0x40,0x62,0x8c,
32300x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,0x3f,0x00,0x42,0x30,0x21,0x20,0x4a,0x00,
32310x68,0x15,0x83,0x26,0x80,0x10,0x04,0x00,0x10,0x40,0x66,0x8c,0x21,0x10,0x43,0x00,
32320x18,0x40,0x44,0x8c,0x82,0x3a,0x06,0x00,0xff,0x03,0xe7,0x30,0xf0,0x00,0xe0,0x10,
32330x82,0x2d,0x04,0x00,0x00,0x02,0xe2,0x30,0x04,0x00,0x40,0x10,0x18,0x00,0xe5,0x00,
32340x00,0xfc,0x02,0x24,0x25,0x38,0xe2,0x00,0x18,0x00,0xe5,0x00,0x02,0x25,0x06,0x00,
32350xff,0x03,0x84,0x30,0x00,0x02,0x83,0x30,0x12,0x10,0x00,0x00,0x02,0x12,0x02,0x00,
32360x03,0x00,0x60,0x10,0xff,0x03,0x48,0x30,0x00,0xfc,0x02,0x24,0x25,0x20,0x82,0x00,
32370x18,0x00,0x85,0x00,0x80,0x2d,0x05,0x00,0x25,0xb0,0x06,0x3c,0x88,0x0c,0xc7,0x34,
32380x9c,0x0c,0xc6,0x34,0x12,0x20,0x00,0x00,0x02,0x22,0x04,0x00,0x3f,0x00,0x82,0x30,
32390x00,0x14,0x02,0x00,0x25,0x28,0xa2,0x00,0x25,0x28,0xa8,0x00,0x10,0x00,0xa5,0xaf,
32400x00,0x00,0xe5,0xac,0x00,0x00,0xc3,0x8c,0xff,0x0f,0x02,0x3c,0xc0,0x03,0x84,0x30,
32410xff,0xff,0x42,0x34,0x80,0x25,0x04,0x00,0x24,0x18,0x62,0x00,0x25,0x18,0x64,0x00,
32420x10,0x00,0xa3,0xaf,0x00,0x00,0xc3,0xac,0x95,0x54,0x00,0x08,0x00,0x00,0x00,0x00,
32430x80,0x0c,0x42,0x34,0x00,0x00,0x43,0x8c,0xc0,0xff,0x02,0x3c,0x21,0x88,0x00,0x00,
32440x24,0x28,0x62,0x00,0xc0,0xff,0x04,0x3c,0x8a,0x55,0x00,0x08,0x18,0x40,0xc3,0x24,
32450x01,0x00,0x31,0x26,0x25,0x00,0x22,0x2e,0x0d,0x00,0x40,0x10,0x02,0x80,0x0b,0x3c,
32460x00,0x00,0x62,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x44,0x00,0xf8,0xff,0x45,0x14,
32470x04,0x00,0x63,0x24,0x08,0x40,0xc2,0x8c,0xc0,0xff,0x03,0x24,0x3f,0x00,0x24,0x32,
32480x24,0x10,0x43,0x00,0x25,0x10,0x44,0x00,0x08,0x40,0xc2,0xac,0x02,0x80,0x0b,0x3c,
32490x8e,0x7d,0x63,0x91,0x22,0x00,0x02,0x24,0x3e,0x00,0x62,0x10,0x92,0x00,0x02,0x24,
32500x3d,0x00,0x62,0x10,0x25,0xb0,0x02,0x3c,0x25,0xb0,0x02,0x3c,0x24,0x0a,0x42,0x34,
32510x00,0x00,0x44,0x8c,0x3f,0x3f,0x03,0x3c,0x3f,0x3f,0x63,0x34,0x24,0x20,0x83,0x00,
32520x02,0x80,0x02,0x3c,0x02,0x80,0x03,0x3c,0x16,0x56,0x53,0x24,0x1e,0x57,0x72,0x24,
32530x21,0x88,0x00,0x00,0xb1,0x55,0x00,0x08,0x10,0x00,0xa4,0xaf,0xd4,0x45,0x00,0x0c,
32540x00,0x00,0x00,0x00,0x47,0x00,0x40,0x10,0x68,0x15,0x85,0x26,0x01,0x00,0x31,0x26,
32550x21,0x00,0x22,0x2e,0x17,0x00,0x40,0x10,0x68,0x15,0x84,0x26,0xc0,0x80,0x11,0x00,
32560x10,0x00,0xa4,0x27,0x21,0x28,0x13,0x02,0xd4,0x45,0x00,0x0c,0x04,0x00,0x06,0x24,
32570x21,0x28,0x12,0x02,0x10,0x00,0xa4,0x27,0xf0,0xff,0x40,0x14,0x04,0x00,0x06,0x24,
32580x68,0x15,0x85,0x26,0x08,0x40,0xa3,0x8c,0xc0,0xff,0x02,0x3c,0xff,0xff,0x42,0x34,
32590x3f,0x00,0x24,0x32,0x24,0x18,0x62,0x00,0x00,0x24,0x04,0x00,0xff,0x7f,0x02,0x3c,
32600x25,0x18,0x64,0x00,0xff,0xff,0x42,0x34,0x24,0x18,0x62,0x00,0x08,0x40,0xa3,0xac,
32610x68,0x15,0x84,0x26,0x0c,0x40,0x83,0x8c,0x00,0x40,0x02,0x3c,0x25,0x18,0x62,0x00,
32620x25,0xb0,0x02,0x3c,0x0e,0x0c,0x42,0x34,0x0c,0x40,0x83,0xac,0x00,0x00,0x40,0xa0,
32630x8f,0x54,0x00,0x08,0x68,0x15,0x85,0x26,0xc6,0x42,0x02,0xa2,0xba,0x54,0x00,0x08,
32640xc4,0x42,0x12,0xa6,0xda,0x53,0x00,0x0c,0x00,0x00,0x00,0x00,0xc9,0x54,0x00,0x08,
32650xc4,0x42,0x12,0xa6,0x25,0xb0,0x02,0x3c,0x88,0x0c,0x42,0x34,0x00,0x00,0x44,0x8c,
32660x02,0x80,0x03,0x3c,0x68,0x15,0x66,0x24,0xc0,0xff,0x02,0x3c,0x24,0x28,0x82,0x00,
32670x21,0x88,0x00,0x00,0xc0,0xff,0x04,0x3c,0xe6,0x55,0x00,0x08,0x18,0x40,0xc3,0x24,
32680x01,0x00,0x31,0x26,0x25,0x00,0x22,0x2e,0xb8,0xff,0x40,0x10,0x25,0xb0,0x02,0x3c,
32690x00,0x00,0x62,0x8c,0x00,0x00,0x00,0x00,0x24,0x10,0x44,0x00,0xf8,0xff,0x45,0x14,
32700x04,0x00,0x63,0x24,0x08,0x40,0xc2,0x8c,0x3f,0x00,0x23,0x32,0xff,0xc0,0x04,0x24,
32710x24,0x10,0x44,0x00,0x00,0x1a,0x03,0x00,0x25,0x10,0x43,0x00,0x9c,0x55,0x00,0x08,
32720x08,0x40,0xc2,0xac,0x08,0x40,0xa3,0x8c,0xc0,0xff,0x02,0x3c,0xff,0xff,0x42,0x34,
32730x3f,0x00,0x24,0x32,0x24,0x18,0x62,0x00,0x00,0x24,0x04,0x00,0x25,0x18,0x64,0x00,
32740x00,0x80,0x02,0x3c,0xc5,0x55,0x00,0x08,0x25,0x18,0x62,0x00,0xcc,0xff,0x02,0x24,
32750x00,0x00,0x62,0xa0,0xcd,0x54,0x00,0x08,0x68,0x15,0x83,0x26,0x25,0xb0,0x02,0x3c,
32760x94,0x0c,0x43,0x34,0x80,0x0c,0x42,0x34,0x00,0x00,0x44,0xac,0x00,0x00,0x60,0xac,
32770x0d,0x55,0x00,0x08,0x68,0x15,0x83,0x26,0x2f,0x00,0xe0,0x10,0x21,0x30,0x00,0x00,
32780x2b,0x10,0x42,0x01,0x21,0x20,0x8a,0x00,0x00,0x00,0x42,0x38,0x24,0x00,0x06,0x24,
32790x2b,0x18,0x43,0x01,0x0b,0x30,0x82,0x00,0xcd,0xfe,0x60,0x10,0x20,0x00,0x09,0x24,
32800x68,0x15,0x83,0x26,0x0a,0x40,0x62,0x94,0x02,0x80,0x0b,0x3c,0x3f,0x00,0x42,0x30,
32810xe0,0x54,0x00,0x08,0x21,0x48,0x4a,0x00,0x21,0x28,0xa3,0x00,0xb4,0x41,0xa3,0x90,
32820x25,0xb0,0x04,0x3c,0x22,0x0a,0x82,0x34,0x00,0x00,0x43,0xa0,0xb5,0x41,0xa6,0x90,
32830x23,0x0a,0x82,0x34,0x24,0x0a,0x87,0x34,0x00,0x00,0x46,0xa0,0xb6,0x41,0xa3,0x90,
32840x25,0x0a,0x86,0x34,0x26,0x0a,0x88,0x34,0x00,0x00,0xe3,0xa0,0xb7,0x41,0xa2,0x90,
32850x27,0x0a,0x87,0x34,0x28,0x0a,0x89,0x34,0x00,0x00,0xc2,0xa0,0xb8,0x41,0xa3,0x90,
32860x29,0x0a,0x84,0x34,0x00,0x00,0x03,0xa1,0xb9,0x41,0xa2,0x90,0x00,0x00,0x00,0x00,
32870x00,0x00,0xe2,0xa0,0xba,0x41,0xa3,0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x23,0xa1,
32880xbb,0x41,0xa2,0x90,0x2d,0x55,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xa0,
32890xad,0x54,0x00,0x08,0x68,0x15,0x84,0x26,0x23,0x10,0x8a,0x00,0x2b,0x18,0x44,0x01,
32900x2b,0x20,0x45,0x01,0x0b,0x30,0x43,0x00,0xa1,0xfe,0x80,0x14,0x23,0x48,0xaa,0x00,
32910xde,0x54,0x00,0x08,0x21,0x48,0x00,0x00,0xff,0xff,0x43,0x25,0x42,0x18,0x03,0x00,
32920x40,0x10,0x03,0x00,0x21,0x10,0x43,0x00,0x40,0x55,0x00,0x08,0x01,0x00,0x4a,0x24,
32930x25,0xb0,0x02,0x3c,0x9c,0x0c,0x43,0x34,0x88,0x0c,0x42,0x34,0x00,0x00,0x44,0xac,
32940x00,0x00,0x60,0xac,0x95,0x54,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x40,0x62,0x8c,
32950x00,0x00,0x00,0x00,0x02,0x12,0x02,0x00,0x3f,0x00,0x42,0x30,0x23,0x18,0x4a,0x00,
32960x2b,0x10,0x42,0x01,0x4e,0x55,0x00,0x08,0x0b,0x20,0x62,0x00,0xff,0xff,0x05,0x36,
32970x60,0x00,0x06,0x24,0xba,0x44,0x00,0x0c,0x24,0x00,0x04,0x24,0x84,0x0a,0x00,0x0c,
32980xe8,0x03,0x04,0x24,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
32990x00,0x60,0x81,0x40,0x24,0x00,0x04,0x24,0xdd,0x44,0x00,0x0c,0xff,0xff,0x05,0x36,
33000x1f,0x00,0x52,0x30,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
33010xb3,0x0a,0x00,0x0c,0x64,0x00,0x04,0x24,0xb4,0x54,0x00,0x08,0x68,0x15,0x90,0x26,
33020x00,0xff,0x84,0x30,0x02,0x22,0x04,0x00,0x08,0x00,0x80,0x10,0x02,0x80,0x02,0x3c,
33030xff,0x00,0x02,0x24,0x04,0x00,0x82,0x10,0xcc,0xff,0x03,0x24,0x02,0x80,0x02,0x3c,
33040x08,0x00,0xe0,0x03,0x4e,0x58,0x43,0xa0,0x02,0x80,0x02,0x3c,0x08,0x00,0xe0,0x03,
33050x4e,0x58,0x44,0xa0,0x02,0x24,0x04,0x00,0xff,0x00,0x84,0x30,0xc0,0x10,0x04,0x00,
33060x21,0x10,0x44,0x00,0x80,0x10,0x02,0x00,0x21,0x10,0x44,0x00,0x02,0x80,0x03,0x3c,
33070x80,0x10,0x02,0x00,0x68,0x15,0x63,0x24,0x20,0x00,0x84,0x2c,0x09,0x00,0x80,0x10,
33080x21,0x10,0x43,0x00,0x68,0x51,0x43,0x8c,0x25,0xb0,0x02,0x3c,0xc4,0x02,0x42,0x34,
33090x02,0x19,0x03,0x00,0x7f,0x00,0x63,0x30,0x00,0x00,0x43,0xac,0x08,0x00,0xe0,0x03,
33100x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,0x44,0x79,0x43,0x8c,0x25,0xb0,0x02,0x3c,
33110xc4,0x02,0x42,0x34,0x02,0x19,0x03,0x00,0x7f,0x00,0x63,0x30,0x00,0x00,0x43,0xac,
33120x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xff,0x00,0x85,0x30,0xd2,0xff,0xa3,0x24,
33130xfe,0xff,0xa2,0x24,0xda,0xff,0xa4,0x24,0x04,0x00,0x63,0x2c,0x08,0x00,0x84,0x2c,
33140x06,0x00,0x60,0x14,0xff,0x00,0x42,0x30,0xf0,0xff,0xa2,0x24,0xfc,0xff,0xa3,0x24,
33150x16,0x00,0x46,0x2c,0x03,0x00,0x80,0x10,0xff,0x00,0x62,0x30,0x08,0x00,0xe0,0x03,
33160x00,0x00,0x00,0x00,0xfa,0xff,0xa3,0x24,0xfc,0xff,0xc0,0x10,0x21,0x10,0xa0,0x00,
33170x08,0x00,0xe0,0x03,0xff,0x00,0x62,0x30,0x25,0xb0,0x04,0x3c,0x03,0x0d,0x85,0x34,
33180x00,0x00,0xa3,0x90,0x2d,0x0a,0x84,0x34,0xff,0x00,0x63,0x30,0x08,0x00,0x63,0x34,
33190x00,0x00,0xa3,0xa0,0x00,0x00,0xa2,0x90,0x00,0x00,0x00,0x00,0xf7,0x00,0x42,0x30,
33200x00,0x00,0xa2,0xa0,0x00,0x00,0x83,0x90,0x00,0x00,0x00,0x00,0x3f,0x00,0x63,0x30,
33210x00,0x00,0x83,0xa0,0x00,0x00,0x82,0x90,0x80,0xff,0x03,0x24,0x25,0x10,0x43,0x00,
33220x00,0x00,0x82,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x25,0xb0,0x02,0x3c,
33230xff,0x00,0x03,0x3c,0x82,0x01,0x49,0x34,0x81,0x01,0x48,0x34,0x24,0x10,0x83,0x00,
33240x02,0x3c,0x02,0x00,0x00,0xff,0x63,0x34,0x02,0x80,0x02,0x3c,0x68,0x15,0x45,0x24,
33250x02,0x32,0x04,0x00,0x01,0x00,0x02,0x24,0x24,0x20,0x83,0x00,0xc2,0x4c,0xa2,0xa0,
33260xb0,0x4c,0xa0,0xac,0xb4,0x4c,0xa0,0xac,0xb8,0x4c,0xa0,0xac,0x06,0x00,0x80,0x14,
33270xbc,0x4c,0xa0,0xac,0x00,0x00,0x02,0x91,0x00,0x00,0x23,0x91,0xc0,0x4c,0xa2,0xa0,
33280x08,0x00,0xe0,0x03,0xc1,0x4c,0xa3,0xa0,0xc1,0x4c,0xa7,0xa0,0x08,0x00,0xe0,0x03,
33290xc0,0x4c,0xa6,0xa0,0x02,0x80,0x03,0x3c,0x68,0x15,0x63,0x24,0xc1,0x4c,0x66,0x90,
33300xc0,0x4c,0x65,0x90,0x25,0xb0,0x02,0x3c,0x82,0x01,0x44,0x34,0x81,0x01,0x42,0x34,
33310x00,0x00,0x45,0xa0,0x00,0x00,0x86,0xa0,0x08,0x00,0xe0,0x03,0xc2,0x4c,0x60,0xa0,
33320x02,0x80,0x08,0x3c,0x68,0x15,0x04,0x25,0xc2,0x4c,0x82,0x90,0x00,0x00,0x00,0x00,
33330x15,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0xb4,0x4c,0x82,0x8c,0xb0,0x4c,0x85,0x8c,
33340x25,0xb0,0x03,0x3c,0x40,0x11,0x02,0x00,0x2b,0x10,0xa2,0x00,0x82,0x01,0x67,0x34,
33350x0f,0x00,0x40,0x10,0x81,0x01,0x66,0x34,0xc1,0x4c,0x83,0x90,0xc0,0x4c,0x82,0x90,
33360xf0,0x00,0x63,0x30,0x1f,0x00,0x42,0x30,0x00,0x00,0xc2,0xa0,0x00,0x00,0xe3,0xa0,
33370x68,0x15,0x02,0x25,0x01,0x00,0x03,0x24,0xbc,0x4c,0x40,0xac,0xb0,0x4c,0x40,0xac,
33380xb4,0x4c,0x40,0xac,0xb8,0x4c,0x40,0xac,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
33390xb8,0x4c,0x82,0x8c,0x25,0xb0,0x03,0x3c,0x82,0x01,0x69,0x34,0x40,0x11,0x02,0x00,
33400x2b,0x10,0xa2,0x00,0x0e,0x00,0x40,0x14,0x81,0x01,0x66,0x34,0xbc,0x4c,0x82,0x8c,
33410x00,0x00,0x00,0x00,0x40,0x11,0x02,0x00,0x2b,0x10,0xa2,0x00,0x08,0x00,0x40,0x14,
33420x00,0x00,0x00,0x00,0xc1,0x4c,0x83,0x90,0xc0,0x4c,0x82,0x90,0x00,0x00,0x00,0x00,
33430x00,0x00,0xc2,0xa0,0x00,0x00,0x23,0xa1,0xf7,0x56,0x00,0x08,0x68,0x15,0x02,0x25,
33440xc1,0x4c,0x83,0x90,0xc0,0x4c,0x82,0x90,0xf0,0x00,0x63,0x30,0x7f,0x00,0x42,0x30,
33450x00,0x00,0xc2,0xa0,0x00,0x00,0x23,0xa1,0xf7,0x56,0x00,0x08,0x68,0x15,0x02,0x25,
33460x02,0x00,0x03,0x24,0x02,0x80,0x02,0x3c,0x08,0x00,0xe0,0x03,0x3d,0x58,0x43,0xa0,
33470xcc,0xff,0x03,0x24,0x02,0x80,0x02,0x3c,0x08,0x00,0xe0,0x03,0x3d,0x58,0x43,0xa0,
33480x25,0xb0,0x03,0x3c,0x33,0x02,0x65,0x34,0x00,0x11,0x04,0x00,0x00,0x00,0xa2,0xa0,
33490x30,0x02,0x63,0x34,0x00,0x00,0x65,0x8c,0x0f,0x00,0x02,0x3c,0xff,0xff,0x42,0x34,
33500x24,0x28,0xa2,0x00,0x01,0x00,0x03,0x24,0x04,0x18,0x83,0x00,0x02,0x00,0xa0,0x10,
33510x21,0x10,0x00,0x00,0xff,0xff,0x62,0x30,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
33520xe0,0xff,0xbd,0x27,0x14,0x00,0xb1,0xaf,0x25,0xb0,0x11,0x3c,0x18,0x00,0xb2,0xaf,
33530x4c,0x00,0x22,0x36,0x1c,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x00,0x44,0x90,
33540x02,0x80,0x03,0x3c,0x02,0x00,0x02,0x24,0xff,0x00,0x84,0x30,0x07,0x00,0x82,0x10,
33550x68,0x15,0x72,0x24,0x1c,0x00,0xbf,0x8f,0x18,0x00,0xb2,0x8f,0x14,0x00,0xb1,0x8f,
33560x10,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0xe6,0x63,0x43,0x96,
33570x01,0x00,0x02,0x24,0xf7,0xff,0x62,0x14,0x21,0x20,0x00,0x00,0x22,0x57,0x00,0x0c,
33580x00,0x00,0x00,0x00,0x04,0x00,0x04,0x24,0x22,0x57,0x00,0x0c,0x21,0x80,0x40,0x00,
33590x25,0x80,0x02,0x02,0x33,0x02,0x23,0x36,0x08,0x00,0x02,0x24,0xff,0xff,0x10,0x32,
33600x40,0x00,0x25,0x36,0x00,0x00,0x62,0xa0,0xea,0xff,0x00,0x16,0x00,0x00,0x00,0x00,
33610x00,0x00,0xa2,0x94,0xe4,0x63,0x43,0x96,0xff,0xdf,0x42,0x30,0x00,0x20,0x44,0x34,
33620x01,0x00,0x63,0x24,0xe4,0x63,0x43,0xa6,0x00,0x00,0xa2,0xa4,0x00,0x00,0xa4,0xa4,
33630x3f,0x57,0x00,0x08,0x00,0x00,0x00,0x00,0x01,0x80,0x03,0x3c,0x25,0xb0,0x02,0x3c,
33640x18,0x03,0x42,0x34,0x80,0x5d,0x63,0x24,0x00,0x00,0x43,0xac,0x63,0x00,0x02,0x24,
33650xff,0xff,0x42,0x24,0xff,0xff,0x41,0x04,0xff,0xff,0x42,0x24,0x02,0x80,0x02,0x3c,
33660x88,0x7d,0x45,0x94,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x8b,0x7d,0x66,0x90,
33670x98,0x7d,0x47,0x90,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0xa3,0x7d,0x69,0x90,
33680xa5,0x7d,0x4a,0x90,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0xa8,0x7d,0x6b,0x90,
33690xaa,0x7d,0x4c,0x90,0x07,0x00,0x03,0x24,0x02,0x80,0x02,0x3c,0x25,0xb0,0x04,0x3c,
33700x95,0x7d,0x43,0xa0,0xb0,0x03,0x84,0x34,0x02,0x80,0x02,0x3c,0x02,0x80,0x18,0x3c,
33710x8a,0x7d,0x08,0x93,0x00,0x00,0x85,0xac,0x96,0x7d,0x40,0xa0,0x02,0x80,0x02,0x3c,
33720x00,0x00,0x86,0xac,0x02,0x80,0x0f,0x3c,0x97,0x7d,0x40,0xa0,0x02,0x80,0x02,0x3c,
33730x00,0x00,0x87,0xac,0x68,0x15,0xee,0x25,0xb8,0x7d,0x40,0xa0,0xfd,0xff,0x02,0x24,
33740xd5,0x4a,0xc2,0xa1,0x01,0x00,0x03,0x24,0x00,0x78,0x02,0x24,0xd4,0x4a,0xc3,0xa1,
33750xd8,0x4a,0xc2,0xa5,0xff,0x07,0x03,0x24,0x0f,0x00,0x0d,0x31,0x02,0x00,0x02,0x24,
33760xda,0x4a,0xc3,0xa5,0x00,0x00,0x88,0xac,0x00,0x00,0x89,0xac,0x00,0x00,0x8a,0xac,
33770x00,0x00,0x8b,0xac,0x00,0x00,0x8c,0xac,0x17,0x00,0xa2,0x11,0x02,0x80,0x02,0x3c,
33780x8a,0x7d,0x02,0x93,0x01,0x00,0x03,0x24,0x0f,0x00,0x42,0x30,0x05,0x00,0x43,0x10,
33790x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,0xca,0x7d,0x40,0xa4,0x08,0x00,0xe0,0x03,
33800x00,0x00,0x00,0x00,0x00,0x80,0x02,0x3c,0x68,0x15,0xe4,0x25,0x02,0xbc,0x42,0x34,
33810x68,0x4b,0x82,0xac,0x15,0x15,0x03,0x3c,0x02,0x02,0x02,0x3c,0x07,0x07,0x63,0x34,
33820x64,0x4b,0x82,0xac,0x02,0x80,0x02,0x3c,0x60,0x4b,0x83,0xac,0xca,0x7d,0x40,0xa4,
33830x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x8f,0x7d,0x44,0x90,0x06,0x00,0x03,0x24,
33840x15,0x00,0x83,0x10,0x0b,0x00,0x02,0x24,0x0a,0x00,0x82,0x10,0x00,0xe0,0x02,0x3c,
33850x68,0x15,0xe4,0x25,0x00,0xb2,0x42,0x34,0x00,0x1c,0x03,0x3c,0x68,0x4b,0x82,0xac,
33860x00,0x1c,0x63,0x34,0x00,0x04,0x02,0x24,0x60,0x4b,0x83,0xac,0x9a,0x57,0x00,0x08,
33870x64,0x4b,0x82,0xac,0x00,0x80,0x02,0x3c,0x00,0xbc,0x42,0x34,0x15,0x15,0x03,0x3c,
33880x68,0x4b,0xc2,0xad,0x07,0x07,0x63,0x34,0x03,0x03,0x02,0x3c,0x60,0x4b,0xc3,0xad,
33890x9a,0x57,0x00,0x08,0x64,0x4b,0xc2,0xad,0x00,0xc0,0x02,0x3c,0x00,0xb2,0x42,0x34,
33900x1c,0x1c,0x03,0x3c,0x68,0x4b,0xc2,0xad,0x07,0x07,0x63,0x34,0x00,0x04,0x02,0x24,
33910x60,0x4b,0xc3,0xad,0x9a,0x57,0x00,0x08,0x64,0x4b,0xc2,0xad,0x25,0xb0,0x02,0x3c,
33920x4d,0x00,0x44,0x34,0xff,0x00,0x03,0x3c,0xec,0x02,0x42,0x34,0x00,0x00,0x43,0xac,
33930x00,0x00,0x80,0xa0,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x03,0x3c,
33940x25,0xb0,0x02,0x3c,0x64,0x5f,0x63,0x24,0x18,0x03,0x42,0x34,0x00,0x00,0x43,0xac,
33950x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x7f,0x00,0x02,0x3c,0xfd,0xbf,0x45,0x34,
33960x80,0x04,0x03,0x3c,0x25,0x28,0xa3,0x00,0x00,0x08,0x04,0x3c,0x02,0x80,0x02,0x3c,
33970x68,0x15,0x42,0x24,0x25,0x28,0xa4,0x00,0x41,0xb0,0x03,0x3c,0x00,0x00,0x65,0xac,
33980x04,0x4b,0x45,0xac,0xfc,0x4a,0x45,0xac,0x08,0x00,0x63,0x34,0x86,0x00,0x05,0x24,
33990x00,0x00,0x65,0xa4,0x08,0x4b,0x45,0xa4,0x00,0x4b,0x40,0xac,0x0a,0x4b,0x40,0xa4,
34000x0c,0x4b,0x45,0xa4,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,
34010x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xf8,0x57,0x00,0x08,0x00,0x00,0x00,0x00,
34020x42,0xb0,0x02,0x3c,0xa0,0xff,0x03,0x24,0x01,0x00,0x42,0x34,0xe8,0xff,0xbd,0x27,
34030x21,0x20,0x00,0x00,0x01,0x00,0x05,0x24,0x00,0x01,0x06,0x24,0x00,0x00,0x43,0xa0,
34040x10,0x00,0xbf,0xaf,0xc4,0x0c,0x00,0x0c,0x00,0x00,0x00,0x00,0x10,0x00,0xbf,0x8f,
34050x03,0x00,0x04,0x24,0x01,0x00,0x05,0x24,0x40,0x1f,0x06,0x24,0xc4,0x0c,0x00,0x08,
34060x18,0x00,0xbd,0x27,0xe8,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0x14,0x00,0xbf,0xaf,
34070x21,0x5b,0x00,0x0c,0x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,0x68,0x15,0x42,0x24,
34080x48,0x01,0x03,0x24,0xe0,0x63,0x43,0xac,0xdc,0x63,0x43,0xac,0x21,0x80,0x40,0x00,
34090x1f,0x00,0x03,0x24,0xff,0xff,0x63,0x24,0xc4,0x4c,0x40,0xa4,0xc6,0x4c,0x40,0xa4,
34100xc8,0x4c,0x40,0xa4,0xca,0x4c,0x40,0xa4,0xcc,0x4c,0x40,0xa4,0xce,0x4c,0x40,0xa4,
34110xd0,0x4c,0x40,0xa4,0xd2,0x4c,0x40,0xa4,0xd4,0x4c,0x40,0xa4,0xf5,0xff,0x61,0x04,
34120x24,0x00,0x42,0x24,0x25,0xb0,0x02,0x3c,0x10,0x00,0x03,0x24,0xb0,0x03,0x42,0x34,
34130x02,0x80,0x04,0x3c,0x8c,0x58,0x84,0x24,0x00,0x00,0x43,0xac,0x21,0x28,0x00,0x00,
34140x97,0x45,0x00,0x0c,0x04,0x00,0x06,0x24,0xef,0x5b,0x00,0x0c,0x00,0x00,0x00,0x00,
34150x71,0x5c,0x00,0x0c,0x8c,0x65,0x00,0xae,0xa7,0x5d,0x00,0x0c,0x00,0x00,0x00,0x00,
34160x4b,0x5e,0x00,0x0c,0x00,0x00,0x00,0x00,0x02,0x80,0x03,0x3c,0x8e,0x7d,0x64,0x90,
34170x92,0x00,0x02,0x24,0x03,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0xf7,0x5d,0x00,0x0c,
34180x00,0x00,0x00,0x00,0xdd,0x5d,0x00,0x0c,0x00,0x00,0x00,0x00,0x8b,0x5c,0x00,0x0c,
34190x00,0x00,0x00,0x00,0xe4,0x63,0x00,0xa6,0x67,0x5e,0x00,0x0c,0xe6,0x63,0x00,0xa6,
34200x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x02,0x80,0x04,0x3c,0x02,0x80,0x05,0x3c,
34210xf8,0x7a,0x82,0x24,0x00,0x7b,0xa3,0x24,0x18,0x00,0xbd,0x27,0x04,0x00,0x42,0xac,
34220xf8,0x7a,0x82,0xac,0x00,0x7b,0xa3,0xac,0x08,0x00,0xe0,0x03,0x04,0x00,0x63,0xac,
34230xe8,0xff,0xbd,0x27,0x10,0x00,0xb0,0xaf,0x01,0x80,0x02,0x3c,0x25,0xb0,0x10,0x3c,
34240x18,0x03,0x03,0x36,0x38,0x61,0x42,0x24,0x00,0x00,0x62,0xac,0x14,0x00,0xbf,0xaf,
34250x60,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0xd5,0x58,0x00,0x0c,0x00,0x00,0x00,0x00,
34260x01,0x00,0x03,0x24,0x02,0x80,0x02,0x3c,0xfd,0x5a,0x00,0x0c,0xdb,0x60,0x43,0xa0,
34270xd1,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0x32,0x41,0x00,0x0c,0x00,0x00,0x00,0x00,
34280x0b,0x58,0x00,0x0c,0x00,0x00,0x00,0x00,0x44,0x00,0x03,0x36,0x00,0x00,0x62,0x94,
34290x00,0x00,0x00,0x00,0x40,0x00,0x42,0x34,0x00,0x00,0x62,0xa4,0xd9,0x57,0x00,0x0c,
34300x00,0x00,0x00,0x00,0xfa,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0xc9,0x5a,0x00,0x0c,
34310x00,0x00,0x00,0x00,0x8e,0x5a,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x80,0x04,0x3c,
34320xb4,0x24,0x84,0x24,0xe6,0x5a,0x00,0x0c,0x01,0x00,0x05,0x24,0x01,0x80,0x04,0x3c,
34330x08,0x1e,0x84,0x24,0xe6,0x5a,0x00,0x0c,0x02,0x00,0x05,0x24,0x81,0x4e,0x00,0x0c,
34340x00,0x00,0x00,0x00,0x00,0x80,0x04,0x3c,0x54,0x34,0x84,0x24,0xe6,0x5a,0x00,0x0c,
34350x03,0x00,0x05,0x24,0x02,0x80,0x02,0x3c,0x98,0x7d,0x43,0x90,0x43,0x00,0x04,0x36,
34360x29,0x00,0x60,0x10,0xd8,0x00,0x10,0x36,0x07,0x00,0x02,0x24,0x2b,0x00,0x62,0x10,
34370x25,0xb0,0x04,0x3c,0x10,0x02,0x86,0x34,0x43,0x00,0x85,0x34,0x03,0x00,0x02,0x24,
34380x10,0x00,0x03,0x24,0x00,0x00,0xa2,0xa0,0xd8,0x00,0x84,0x34,0x00,0x00,0xc3,0xa0,
34390x00,0x00,0x82,0x90,0x80,0xff,0x03,0x24,0x42,0xb0,0x05,0x3c,0x25,0x10,0x43,0x00,
34400x00,0x00,0x82,0xa0,0x25,0xb0,0x04,0x3c,0x44,0x00,0x84,0x34,0x00,0x00,0x82,0x94,
34410x00,0x00,0x00,0x00,0xc0,0x00,0x42,0x34,0x00,0x00,0x82,0xa4,0x00,0x00,0xa3,0x90,
34420x00,0x00,0x00,0x00,0x01,0x00,0x63,0x34,0x00,0x00,0xa3,0xa0,0xe0,0x57,0x00,0x0c,
34430x00,0x00,0x00,0x00,0x02,0x80,0x04,0x3c,0x08,0x00,0x84,0x24,0x21,0x28,0x00,0x00,
34440x21,0x30,0x00,0x00,0x31,0x1c,0x00,0x0c,0x21,0x38,0x00,0x00,0xf8,0x57,0x00,0x0c,
34450x00,0x00,0x00,0x00,0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x01,0x00,0x02,0x24,
34460x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,0x00,0x00,0x80,0xa0,0x00,0x00,0x03,0x92,
34470x80,0xff,0x02,0x24,0x25,0x18,0x62,0x00,0x00,0x00,0x03,0xa2,0x25,0xb0,0x04,0x3c,
34480x44,0x00,0x84,0x34,0x00,0x00,0x82,0x94,0x42,0xb0,0x05,0x3c,0xc0,0x00,0x42,0x34,
34490x00,0x00,0x82,0xa4,0x00,0x00,0xa3,0x90,0x00,0x00,0x00,0x00,0x01,0x00,0x63,0x34,
34500x00,0x00,0xa3,0xa0,0xe0,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0x02,0x80,0x04,0x3c,
34510x08,0x00,0x84,0x24,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x31,0x1c,0x00,0x0c,
34520x21,0x38,0x00,0x00,0xf8,0x57,0x00,0x0c,0x00,0x00,0x00,0x00,0x14,0x00,0xbf,0x8f,
34530x10,0x00,0xb0,0x8f,0x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x18,0x00,0xbd,0x27,
34540x21,0x20,0x00,0x00,0x20,0xb0,0x06,0x3c,0xff,0xff,0x05,0x34,0x21,0x18,0x86,0x00,
34550x04,0x00,0x84,0x24,0x2a,0x10,0xa4,0x00,0x00,0x00,0x60,0xac,0xfb,0xff,0x40,0x10,
34560x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xb8,0xff,0xbd,0x27,
34570x25,0xb0,0x04,0x3c,0x44,0x00,0xbf,0xaf,0x40,0x00,0xbe,0xaf,0x3c,0x00,0xb7,0xaf,
34580x38,0x00,0xb6,0xaf,0x34,0x00,0xb5,0xaf,0x30,0x00,0xb4,0xaf,0x2c,0x00,0xb3,0xaf,
34590x28,0x00,0xb2,0xaf,0x24,0x00,0xb1,0xaf,0x20,0x00,0xb0,0xaf,0x0a,0x00,0x83,0x34,
34600x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x20,0x00,0x42,0x30,0x0c,0x00,0x40,0x10,
34610x4c,0x87,0x02,0x3c,0x00,0x00,0x62,0x90,0x00,0x00,0x00,0x00,0x10,0x00,0x42,0x30,
34620x66,0x01,0x40,0x10,0x4c,0x87,0x02,0x3c,0x54,0x00,0x83,0x34,0x50,0x00,0x82,0x34,
34630x00,0x00,0x45,0xac,0x00,0x00,0x65,0xa4,0xf9,0x58,0x00,0x08,0x02,0x80,0x03,0x3c,
34640x54,0x00,0x85,0x34,0x00,0xe0,0x42,0x34,0x50,0x00,0x84,0x34,0x12,0x01,0x03,0x24,
34650x00,0x00,0x82,0xac,0x00,0x00,0xa3,0xac,0x02,0x80,0x03,0x3c,0x68,0x15,0x62,0x24,
34660xd5,0x4a,0x43,0x90,0xda,0x4a,0x45,0x94,0x25,0xb0,0x1e,0x3c,0x1c,0x00,0xa3,0xa3,
34670x60,0x4b,0x43,0x8c,0x58,0x00,0xc6,0x37,0xff,0xff,0x04,0x24,0x10,0x00,0xa3,0xaf,
34680x64,0x4b,0x43,0x8c,0x5c,0x00,0xc7,0x37,0x60,0x00,0xc8,0x37,0x14,0x00,0xa3,0xaf,
34690x68,0x4b,0x42,0x8c,0x64,0x00,0xc9,0x37,0x8a,0x00,0xca,0x37,0x18,0x00,0xa2,0xaf,
34700x24,0x10,0x02,0x3c,0x21,0x28,0xa2,0x00,0x4c,0x81,0x02,0x3c,0x00,0xe0,0x42,0x34,
34710x00,0x00,0xc2,0xac,0x96,0x01,0x03,0x24,0x28,0x28,0x02,0x24,0x00,0x00,0xe3,0xac,
34720x89,0x00,0xcb,0x37,0x00,0x00,0x04,0xad,0x8c,0x00,0xcc,0x37,0x00,0x00,0x24,0xad,
34730x09,0x00,0x03,0x24,0x00,0x00,0x42,0xa5,0x10,0x10,0x02,0x24,0x00,0x00,0x63,0xa1,
34740x8e,0x00,0xcd,0x37,0x00,0x00,0x82,0xa5,0x0a,0x0a,0x03,0x24,0x13,0x00,0x02,0x24,
34750x90,0x00,0xce,0x37,0x00,0x00,0xa3,0xa5,0x00,0x00,0xc2,0xa1,0x25,0xb0,0x02,0x3c,
34760x40,0x00,0x03,0x24,0x91,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0x25,0xb0,0x03,0x3c,
34770x3a,0x01,0x02,0x24,0x92,0x00,0x63,0x34,0x00,0x00,0x62,0xa4,0xb5,0x00,0xd1,0x37,
34780x21,0x00,0x03,0x24,0x00,0x00,0x23,0xa2,0x10,0x00,0xa2,0x8f,0xa0,0x00,0xd2,0x37,
34790xa4,0x00,0xd3,0x37,0x00,0x00,0x42,0xae,0x14,0x00,0xa3,0x8f,0xa8,0x00,0xd4,0x37,
34800xac,0x00,0xd5,0x37,0x00,0x00,0x63,0xae,0x18,0x00,0xa2,0x8f,0x25,0xb0,0x03,0x3c,
34810xb0,0x00,0x63,0x34,0x00,0x00,0x82,0xae,0x21,0x10,0x02,0x3c,0xff,0x77,0x42,0x34,
34820x00,0x00,0xa2,0xae,0x25,0xb0,0x02,0x3c,0xd8,0x00,0x42,0x34,0x00,0x00,0x65,0xac,
34830x00,0x00,0x40,0xa0,0x1c,0x00,0xa2,0x93,0x25,0xb0,0x03,0x3c,0xb4,0x00,0x63,0x34,
34840x00,0x00,0x62,0xa0,0x25,0xb0,0x03,0x3c,0x04,0x00,0x02,0x24,0xb6,0x00,0x63,0x34,
34850x00,0x00,0x62,0xa0,0x25,0xb0,0x03,0x3c,0x0f,0x00,0x02,0x24,0xba,0x00,0x63,0x34,
34860xb9,0x00,0xdf,0x37,0x00,0x00,0xe4,0xa3,0x00,0x00,0x62,0xa4,0x25,0xb0,0x02,0x3c,
34870x1a,0x01,0x42,0x34,0x16,0x01,0xd0,0x37,0x18,0x01,0xcf,0x37,0x00,0x00,0x00,0xa6,
34880x25,0xb0,0x03,0x3c,0x00,0x00,0xe0,0xa5,0x00,0x00,0x40,0xa4,0xff,0xff,0x02,0x3c,
34890xff,0x0f,0x42,0x34,0xdc,0x00,0x63,0x34,0x00,0x00,0x62,0xac,0x2f,0x00,0x03,0x3c,
34900x25,0xb0,0x02,0x3c,0x32,0x32,0x63,0x34,0xd0,0x01,0x42,0x34,0x00,0x00,0x43,0xac,
34910x5e,0x00,0x02,0x3c,0x25,0xb0,0x03,0x3c,0x32,0x43,0x42,0x34,0xd4,0x01,0x63,0x34,
34920x00,0x00,0x62,0xac,0x08,0x00,0x03,0x3c,0x25,0xb0,0x02,0x3c,0x30,0xa5,0x63,0x34,
34930xd8,0x01,0x42,0x34,0x00,0x00,0x43,0xac,0xdc,0x01,0xc4,0x37,0x02,0x80,0x03,0x3c,
34940x49,0xa5,0x02,0x34,0x8e,0x7d,0x6d,0x90,0x00,0x00,0x82,0xac,0xc2,0x00,0x02,0x3c,
34950x1a,0x06,0x03,0x24,0x51,0x10,0x42,0x34,0xe0,0x01,0xc5,0x37,0xf4,0x01,0xc6,0x37,
34960xf8,0x01,0xc7,0x37,0x07,0x07,0x04,0x24,0x00,0x00,0xa3,0xa4,0x00,0x02,0xc8,0x37,
34970x00,0x00,0xc4,0xa4,0x26,0x00,0x03,0x24,0x00,0x00,0xe2,0xac,0x03,0x02,0xc9,0x37,
34980x04,0x00,0x02,0x24,0x00,0x00,0x03,0xa5,0x36,0x02,0xca,0x37,0x00,0x00,0x22,0xa1,
34990xc0,0x01,0x03,0x24,0x0c,0x00,0x02,0x24,0x34,0x02,0xcb,0x37,0x00,0x00,0x42,0xa1,
35000x37,0x02,0xcc,0x37,0x00,0x00,0x63,0xa5,0x03,0x00,0x02,0x24,0x22,0x00,0x03,0x24,
35010x00,0x00,0x82,0xa1,0xd6,0x00,0xa3,0x11,0x1b,0x1b,0x02,0x3c,0x13,0x13,0x02,0x3c,
35020x13,0x13,0x42,0x34,0x60,0x01,0xc3,0x37,0x64,0x01,0xc4,0x37,0x68,0x01,0xc5,0x37,
35030x7c,0x01,0xca,0x37,0x6c,0x01,0xc6,0x37,0x70,0x01,0xc7,0x37,0x74,0x01,0xc8,0x37,
35040x78,0x01,0xc9,0x37,0x00,0x00,0x62,0xac,0x00,0x00,0x82,0xac,0x02,0x80,0x03,0x3c,
35050x00,0x00,0xa2,0xac,0x00,0x00,0xc2,0xac,0x00,0x00,0xe2,0xac,0x00,0x00,0x02,0xad,
35060x00,0x00,0x22,0xad,0x00,0x00,0x42,0xad,0x8e,0x7d,0x65,0x90,0x25,0xb0,0x0c,0x3c,
35070x01,0x70,0x03,0x3c,0x80,0x01,0x82,0x35,0x08,0x5f,0x63,0x34,0x22,0x00,0x04,0x24,
35080x00,0x00,0x43,0xac,0xb5,0x00,0xa4,0x10,0x0f,0x1f,0x02,0x3c,0x92,0x00,0x02,0x24,
35090xb2,0x00,0xa2,0x10,0x0f,0x1f,0x02,0x3c,0x0f,0x10,0x02,0x3c,0x00,0xf0,0x51,0x34,
35100xf7,0x01,0x92,0x35,0x15,0xf0,0x4d,0x34,0x77,0x00,0x0e,0x24,0x84,0x01,0x87,0x35,
35110x88,0x01,0x88,0x35,0x10,0xf0,0x44,0x34,0x8c,0x01,0x85,0x35,0x05,0xf0,0x42,0x34,
35120x00,0x00,0xed,0xac,0x90,0x01,0x83,0x35,0x00,0x00,0x04,0xad,0x94,0x01,0x86,0x35,
35130x00,0x00,0xa2,0xac,0xf5,0x0f,0x02,0x24,0x00,0x00,0x71,0xac,0x25,0xb0,0x05,0x3c,
35140x00,0x00,0xc2,0xac,0x98,0x01,0x89,0x35,0x9c,0x01,0x8a,0x35,0xf0,0x0f,0x03,0x24,
35150x0d,0x00,0x02,0x24,0x00,0x00,0x23,0xad,0xa0,0x01,0x8b,0x35,0x00,0x00,0x42,0xad,
35160xa7,0x01,0xb7,0x34,0xf6,0x01,0x8c,0x35,0xff,0xff,0x02,0x24,0x00,0x00,0x6d,0xad,
35170x00,0x00,0x8e,0xa1,0x00,0x00,0x4e,0xa2,0x00,0x00,0xe2,0xa2,0x25,0xb0,0x02,0x3c,
35180xa8,0x01,0xb6,0x34,0xff,0xff,0x09,0x24,0xac,0x01,0x42,0x34,0x00,0x00,0xc9,0xae,
35190x03,0x04,0x04,0x3c,0x00,0x00,0x49,0xac,0x07,0x08,0x03,0x3c,0x25,0xb0,0x02,0x3c,
35200x01,0x02,0x84,0x34,0x05,0x06,0x63,0x34,0xb4,0x01,0xb1,0x34,0xb8,0x01,0xb2,0x34,
35210xbc,0x01,0xb3,0x34,0xb0,0x01,0x42,0x34,0x00,0x00,0x44,0xac,0x00,0x00,0x23,0xae,
35220x25,0xb0,0x02,0x3c,0x00,0x00,0x44,0xae,0x00,0x00,0x63,0xae,0x25,0xb0,0x03,0x3c,
35230x0c,0x00,0x06,0x24,0xc0,0x01,0xb4,0x34,0xc1,0x01,0xb5,0x34,0x0d,0x00,0x08,0x24,
35240xc2,0x01,0x63,0x34,0xc3,0x01,0x42,0x34,0x00,0x00,0x86,0xa2,0xc4,0x01,0xab,0x34,
35250x00,0x00,0xa6,0xa2,0xc5,0x01,0xac,0x34,0x00,0x00,0x66,0xa0,0x0e,0x00,0x07,0x24,
35260x00,0x00,0x48,0xa0,0xc6,0x01,0xaa,0x34,0xc7,0x01,0xad,0x34,0x0f,0x00,0x02,0x24,
35270x00,0x00,0x68,0xa1,0x00,0x00,0x87,0xa1,0x00,0x00,0x47,0xa1,0x00,0x00,0xa2,0xa1,
35280x57,0x01,0x02,0x3c,0x48,0x00,0xbf,0x34,0x46,0x00,0xae,0x34,0x0e,0xe2,0x42,0x34,
35290x00,0x00,0xc0,0xa5,0x4c,0x00,0xbe,0x34,0x00,0x00,0xe2,0xaf,0x4d,0x00,0xb9,0x34,
35300x80,0xff,0x02,0x24,0x00,0x00,0xc0,0xa3,0x00,0x00,0x22,0xa3,0x25,0xb0,0x02,0x3c,
35310xbc,0x00,0x03,0x24,0x40,0x00,0x42,0x34,0x00,0x00,0x43,0xa4,0x25,0xb0,0x03,0x3c,
35320x64,0x03,0xb8,0x34,0xfc,0x37,0x02,0x24,0x40,0x00,0x63,0x34,0x00,0x00,0x00,0xa3,
35330xd8,0x00,0xa7,0x34,0x00,0x00,0x62,0xa4,0x00,0x00,0xe3,0x90,0x2a,0xb0,0x04,0x3c,
35340x80,0xff,0x02,0x24,0x26,0xb0,0x06,0x3c,0x25,0x18,0x62,0x00,0x30,0x00,0x89,0x34,
35350x20,0x20,0x02,0x24,0x38,0x00,0x84,0x34,0x00,0x00,0xe3,0xa0,0x79,0x00,0xc8,0x34,
35360x00,0x00,0x82,0xa4,0x40,0x00,0x03,0x24,0x16,0x00,0x02,0x24,0x00,0x00,0x23,0xa1,
35370x94,0x00,0xaa,0x34,0x00,0x00,0x02,0xa1,0x98,0x00,0xab,0x34,0x64,0x00,0x03,0x24,
35380x22,0x00,0x02,0x24,0x00,0x00,0x43,0xa5,0x7c,0x00,0xd1,0x34,0x00,0x00,0x62,0xa5,
35390x04,0x00,0x12,0x24,0x9c,0x00,0xac,0x34,0x7a,0x00,0xc6,0x34,0x20,0x0c,0x02,0x24,
35400x0a,0x00,0x03,0x24,0x00,0x00,0xd2,0xa0,0x9a,0x00,0xad,0x34,0x00,0x00,0x22,0xa6,
35410x96,0x00,0xae,0x34,0x00,0x00,0x83,0xa1,0xff,0x03,0x02,0x24,0x02,0x00,0x03,0x24,
35420x00,0x00,0xa2,0xa5,0x00,0x00,0xc3,0xa5,0x25,0xb0,0x03,0x3c,0x20,0x00,0x02,0x24,
35430xb7,0x00,0x63,0x34,0x00,0x00,0x62,0xa0,0x25,0xb0,0x02,0x3c,0x09,0x00,0x03,0x24,
35440x89,0x00,0x42,0x34,0x00,0x00,0x43,0xa0,0x44,0x00,0xa5,0x34,0x00,0x00,0xa2,0x94,
35450x02,0x80,0x03,0x3c,0x68,0x15,0x66,0x24,0xff,0xfd,0x03,0x24,0x24,0x10,0x43,0x00,
35460x00,0x00,0xa2,0xa4,0x00,0x00,0xa3,0x94,0xd5,0x4a,0xc4,0x90,0x29,0xb0,0x02,0x3c,
35470x40,0x00,0x42,0x34,0x00,0x02,0x63,0x34,0x00,0x00,0xa3,0xa4,0x00,0x00,0x52,0xa0,
35480xd3,0x0a,0x00,0x0c,0x00,0x00,0x00,0x00,0x44,0x00,0xbf,0x8f,0x40,0x00,0xbe,0x8f,
35490x3c,0x00,0xb7,0x8f,0x38,0x00,0xb6,0x8f,0x34,0x00,0xb5,0x8f,0x30,0x00,0xb4,0x8f,
35500x2c,0x00,0xb3,0x8f,0x28,0x00,0xb2,0x8f,0x24,0x00,0xb1,0x8f,0x20,0x00,0xb0,0x8f,
35510x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x48,0x00,0xbd,0x27,0x54,0x00,0x85,0x34,
35520x00,0xe0,0x42,0x34,0x50,0x00,0x84,0x34,0x12,0x01,0x03,0x24,0x00,0x00,0x82,0xac,
35530x00,0x00,0xa3,0xa4,0xf9,0x58,0x00,0x08,0x02,0x80,0x03,0x3c,0x00,0xf0,0x51,0x34,
35540xf7,0x01,0x92,0x35,0x15,0xf0,0x4d,0x34,0xad,0x59,0x00,0x08,0xff,0xff,0x0e,0x24,
35550x8b,0x59,0x00,0x08,0x1b,0x1b,0x42,0x34,0x25,0xb0,0x03,0x3c,0x25,0xb0,0x08,0x3c,
35560xfc,0x37,0x02,0x24,0x40,0x00,0x63,0x34,0x02,0x80,0x04,0x3c,0x00,0x00,0x62,0xa4,
35570x14,0x80,0x84,0x24,0xff,0x00,0x07,0x24,0xb0,0x03,0x06,0x35,0x00,0x00,0x83,0x94,
35580x00,0x00,0x00,0x00,0xff,0x00,0x62,0x30,0x21,0x18,0x68,0x00,0x0a,0x00,0x47,0x10,
35590xff,0x00,0x65,0x30,0x04,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0xac,
35600x00,0x00,0xc3,0xac,0x04,0x00,0x82,0x8c,0x08,0x00,0x84,0x24,0x00,0x00,0xc2,0xac,
35610xf2,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x25,0xb0,0x08,0x3c,0x01,0x80,0x02,0x3c,
35620x0c,0x7a,0x44,0x24,0xff,0x00,0x07,0x24,0xb0,0x03,0x06,0x35,0x00,0x00,0x83,0x94,
35630x00,0x00,0x00,0x00,0xff,0x00,0x62,0x30,0x21,0x18,0x68,0x00,0x0a,0x00,0x47,0x10,
35640xff,0x00,0x65,0x30,0x04,0x00,0x82,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0xac,
35650x00,0x00,0xc3,0xac,0x04,0x00,0x82,0x8c,0x08,0x00,0x84,0x24,0x00,0x00,0xc2,0xac,
35660xf2,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,
35670x01,0x80,0x02,0x3c,0x02,0x80,0x05,0x3c,0x10,0x6b,0x42,0x24,0x02,0x80,0x03,0x3c,
35680xcc,0x7d,0xa2,0xac,0x00,0x80,0x02,0x3c,0x6c,0x7e,0x60,0xac,0xcc,0x7d,0xa4,0x24,
35690x02,0x80,0x03,0x3c,0xc8,0x06,0x42,0x24,0x70,0x7e,0x60,0xa4,0x08,0x00,0x82,0xac,
35700x02,0x80,0x03,0x3c,0x00,0x80,0x02,0x3c,0x72,0x7e,0x60,0xa4,0x02,0x80,0x06,0x3c,
35710x08,0x0a,0x42,0x24,0x00,0x80,0x03,0x3c,0x74,0x7e,0xc7,0x24,0x14,0x00,0x82,0xac,
35720x38,0x08,0x63,0x24,0x02,0x80,0x02,0x3c,0x74,0x7e,0xc0,0xac,0x10,0x00,0x83,0xac,
35730x04,0x00,0xe0,0xac,0x7c,0x7e,0x40,0xa0,0x00,0x80,0x02,0x3c,0x88,0x19,0x42,0x24,
35740x3c,0x00,0x82,0xac,0x00,0x80,0x03,0x3c,0x00,0x80,0x02,0x3c,0x24,0x0c,0x63,0x24,
35750x78,0x0f,0x42,0x24,0x1c,0x00,0x83,0xac,0x20,0x00,0x82,0xac,0x00,0x80,0x03,0x3c,
35760x00,0x80,0x02,0x3c,0xc8,0x12,0x63,0x24,0x28,0x16,0x42,0x24,0x24,0x00,0x83,0xac,
35770x28,0x00,0x82,0xac,0x00,0x80,0x03,0x3c,0x01,0x80,0x02,0x3c,0x4c,0x1f,0x63,0x24,
35780xd0,0x04,0x42,0x24,0x2c,0x00,0x83,0xac,0x30,0x00,0x82,0xac,0x00,0x80,0x03,0x3c,
35790x00,0x80,0x02,0x3c,0xe4,0x19,0x63,0x24,0x00,0x03,0x42,0x24,0x38,0x00,0x83,0xac,
35800x08,0x00,0xe0,0x03,0x4c,0x00,0x82,0xac,0x25,0xb0,0x02,0x3c,0x08,0x00,0x42,0x34,
35810x00,0x00,0x43,0x8c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x02,0x80,0x0e,0x3c,
35820x02,0x80,0x08,0x3c,0x02,0x80,0x02,0x3c,0x02,0x80,0x03,0x3c,0xf8,0x03,0x4d,0x24,
35830x00,0x14,0x6c,0x24,0x01,0x00,0x07,0x24,0x00,0x00,0xcb,0x25,0xff,0xff,0x0a,0x24,
35840x00,0x04,0x09,0x25,0x80,0x1a,0x07,0x00,0x21,0x10,0x6b,0x00,0x00,0x00,0x42,0xac,
35850x90,0x00,0x4a,0xac,0x00,0x04,0x04,0x8d,0x01,0x00,0xe7,0x24,0x08,0x00,0x45,0x24,
35860x21,0x18,0x6d,0x00,0x05,0x00,0xe6,0x28,0x04,0x00,0x82,0xac,0x00,0x00,0x44,0xac,
35870x04,0x00,0x49,0xac,0x00,0x04,0x02,0xad,0x8c,0x00,0x40,0xac,0x6c,0x00,0xa3,0xac,
35880xf0,0xff,0xc0,0x14,0x68,0x00,0xac,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0xc9,0xad,
35890x05,0x00,0xa2,0x2c,0x13,0x00,0x40,0x10,0xff,0xff,0x07,0x24,0x02,0x80,0x02,0x3c,
35900x80,0x1a,0x05,0x00,0x00,0x00,0x42,0x24,0x0e,0x00,0xa0,0x10,0x21,0x30,0x62,0x00,
35910x90,0x00,0xc3,0x8c,0xff,0xff,0x02,0x24,0x0a,0x00,0x62,0x14,0x00,0x00,0x00,0x00,
35920x8c,0x00,0xc2,0x8c,0x00,0x00,0x00,0x00,0x06,0x00,0x40,0x14,0x00,0x00,0x00,0x00,
35930x01,0x00,0x02,0x24,0x88,0x00,0xc4,0xac,0x8c,0x00,0xc2,0xac,0x90,0x00,0xc5,0xac,
35940x21,0x38,0xa0,0x00,0x08,0x00,0xe0,0x03,0x21,0x10,0xe0,0x00,0x25,0xb0,0x04,0x3c,
35950x01,0x80,0x02,0x3c,0x18,0x03,0x85,0x34,0xf4,0x6b,0x42,0x24,0xe0,0xff,0xbd,0x27,
35960x00,0x00,0xa2,0xac,0x1b,0x00,0x86,0x34,0xdb,0xff,0x03,0x24,0x27,0x00,0x84,0x34,
35970x07,0x00,0x02,0x24,0x14,0x00,0xb1,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x00,0x83,0xa0,
35980x18,0x00,0xbf,0xaf,0x00,0x00,0xc2,0xa0,0x01,0x00,0x11,0x24,0x21,0x80,0x00,0x00,
35990x7a,0x42,0x00,0x0c,0x21,0x20,0x00,0x02,0x01,0x00,0x02,0x26,0xff,0x00,0x50,0x30,
36000x2b,0x18,0x30,0x02,0xfa,0xff,0x60,0x10,0x00,0x00,0x00,0x00,0x7a,0x42,0x00,0x0c,
36010x21,0x20,0x00,0x00,0x18,0x00,0xbf,0x8f,0x14,0x00,0xb1,0x8f,0x10,0x00,0xb0,0x8f,
36020x01,0x00,0x02,0x24,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0x08,0x00,0xe0,0x03,
36030x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x02,0x80,0x02,0x3c,
36040x68,0x15,0x42,0x24,0x40,0x10,0x03,0x3c,0xff,0xff,0x44,0x30,0x25,0xc0,0x83,0x00,
36050x94,0x64,0x58,0xac,0x40,0x00,0x18,0x27,0xa0,0x64,0x58,0xac,0x40,0x00,0x18,0x27,
36060xac,0x64,0x58,0xac,0x40,0x00,0x18,0x27,0xb8,0x64,0x58,0xac,0x40,0x00,0x18,0x27,
36070xe0,0xff,0xbd,0x27,0xc4,0x64,0x58,0xac,0x40,0x00,0x18,0x27,0x1c,0x00,0xb7,0xaf,
36080x18,0x00,0xb6,0xaf,0x14,0x00,0xb5,0xaf,0x10,0x00,0xb4,0xaf,0x0c,0x00,0xb3,0xaf,
36090x08,0x00,0xb2,0xaf,0x04,0x00,0xb1,0xaf,0x00,0x00,0xb0,0xaf,0xd0,0x64,0x58,0xac,
36100xa0,0x64,0x45,0x8c,0xac,0x64,0x46,0x8c,0xb8,0x64,0x47,0x8c,0xc4,0x64,0x48,0x8c,
36110xd0,0x64,0x49,0x8c,0x40,0x00,0x18,0x27,0xdc,0x64,0x58,0xac,0x21,0x50,0x00,0x03,
36120x25,0x20,0x83,0x00,0x40,0x00,0x18,0x27,0x20,0x10,0x03,0x3c,0x90,0x64,0x44,0xac,
36130x9c,0x64,0x45,0xac,0xa8,0x64,0x46,0xac,0xb4,0x64,0x47,0xac,0xc0,0x64,0x48,0xac,
36140xcc,0x64,0x49,0xac,0x25,0xb0,0x06,0x3c,0x28,0x64,0x43,0xac,0x24,0x64,0x43,0xac,
36150x34,0x64,0x43,0xac,0x30,0x64,0x43,0xac,0x40,0x64,0x43,0xac,0x3c,0x64,0x43,0xac,
36160x4c,0x64,0x43,0xac,0x48,0x64,0x43,0xac,0xe8,0x64,0x58,0xac,0x00,0x02,0x18,0x27,
36170xd8,0x64,0x4a,0xac,0x00,0x65,0x58,0xac,0x58,0x64,0x43,0xac,0x54,0x64,0x43,0xac,
36180x64,0x64,0x43,0xac,0x60,0x64,0x43,0xac,0x70,0x64,0x43,0xac,0x6c,0x64,0x43,0xac,
36190xac,0x00,0xc4,0x34,0xb0,0x00,0xc5,0x34,0x00,0x00,0x92,0x8c,0xe8,0x64,0x50,0x8c,
36200x00,0x00,0xb3,0x8c,0x21,0x10,0x04,0x3c,0x23,0x10,0x09,0x3c,0x22,0x10,0x0c,0x3c,
36210x02,0x80,0x14,0x3c,0x02,0x80,0x15,0x3c,0x02,0x80,0x16,0x3c,0x02,0x80,0x17,0x3c,
36220x24,0x10,0x05,0x3c,0x21,0x88,0x00,0x03,0x08,0x7b,0x87,0x26,0x00,0x04,0x18,0x27,
36230x10,0x7b,0xa8,0x26,0x18,0x7b,0xca,0x26,0x20,0x7b,0xeb,0x26,0x00,0x04,0x2d,0x35,
36240x00,0x40,0x8e,0x34,0x00,0x80,0x8f,0x35,0x00,0x01,0xc6,0x34,0xe4,0x64,0x50,0xac,
36250xfc,0x64,0x51,0xac,0x64,0x65,0x4d,0xac,0x28,0x65,0x52,0xac,0x34,0x65,0x4e,0xac,
36260x58,0x65,0x4f,0xac,0x4c,0x65,0x53,0xac,0x00,0x00,0xc5,0xac,0x48,0x65,0x45,0xac,
36270x68,0x65,0x43,0xac,0x74,0x65,0x58,0xac,0x7c,0x64,0x43,0xac,0x78,0x64,0x43,0xac,
36280x06,0x65,0x40,0xa4,0x05,0x65,0x40,0xa0,0x04,0x65,0x40,0xa0,0x5c,0x65,0x49,0xac,
36290x60,0x65,0x49,0xac,0x20,0x65,0x44,0xac,0x24,0x65,0x44,0xac,0x2c,0x65,0x44,0xac,
36300x30,0x65,0x44,0xac,0x50,0x65,0x4c,0xac,0x54,0x65,0x4c,0xac,0x44,0x65,0x45,0xac,
36310x6c,0x65,0x43,0xac,0x78,0x65,0x58,0xac,0x04,0x00,0x08,0xad,0x08,0x7b,0x87,0xae,
36320x04,0x00,0x4a,0xad,0x10,0x7b,0xa8,0xae,0x04,0x00,0x6b,0xad,0x18,0x7b,0xca,0xae,
36330x20,0x7b,0xeb,0xae,0x04,0x00,0xe7,0xac,0x02,0x80,0x02,0x3c,0x00,0x14,0x43,0x24,
36340x21,0x20,0xe0,0x00,0x03,0x00,0x06,0x24,0x21,0x10,0x80,0x00,0xff,0xff,0xc6,0x24,
36350x08,0x00,0x78,0xac,0x00,0x00,0x63,0xac,0x10,0x00,0x60,0xac,0x00,0x00,0x67,0xac,
36360x21,0x20,0x60,0x00,0x04,0x00,0x62,0xac,0x00,0x00,0x43,0xac,0x00,0x01,0x18,0x27,
36370xf5,0xff,0xc1,0x04,0x18,0x00,0x63,0x24,0x02,0x80,0x02,0x3c,0x10,0x7b,0x49,0x24,
36380x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x04,0x00,0x28,0x8d,0x60,0x14,0x4b,0x24,
36390x04,0x00,0xe4,0xac,0x00,0x14,0x6a,0x24,0x01,0x00,0x07,0x24,0x21,0x28,0x00,0x00,
36400x07,0x00,0x06,0x24,0x21,0x20,0xab,0x00,0x21,0x10,0xaa,0x00,0xff,0xff,0xc6,0x24,
36410x68,0x00,0x58,0xac,0x70,0x00,0x47,0xac,0x18,0x00,0xa5,0x24,0x00,0x00,0x89,0xac,
36420x04,0x00,0x88,0xac,0x00,0x00,0x04,0xad,0x00,0x01,0x18,0x27,0xf5,0xff,0xc1,0x04,
36430x21,0x40,0x80,0x00,0x02,0x80,0x02,0x3c,0x18,0x7b,0x4a,0x24,0x02,0x80,0x03,0x3c,
36440x02,0x80,0x02,0x3c,0x04,0x00,0x45,0x8d,0x20,0x15,0x4b,0x24,0x04,0x00,0x24,0xad,
36450x02,0x00,0x07,0x24,0x00,0x14,0x69,0x24,0x21,0x20,0x00,0x00,0x01,0x00,0x06,0x24,
36460x21,0x40,0x8b,0x00,0x21,0x10,0x89,0x00,0xff,0xff,0xc6,0x24,0x28,0x01,0x58,0xac,
36470x30,0x01,0x47,0xac,0x18,0x00,0x84,0x24,0x00,0x00,0x0a,0xad,0x04,0x00,0x05,0xad,
36480x00,0x00,0xa8,0xac,0x00,0x02,0x18,0x27,0xf5,0xff,0xc1,0x04,0x21,0x28,0x00,0x01,
36490x02,0x80,0x05,0x3c,0x20,0x7b,0xa5,0x24,0x04,0x00,0xa6,0x8c,0x1c,0x00,0xb7,0x8f,
36500x18,0x00,0xb6,0x8f,0x14,0x00,0xb5,0x8f,0x10,0x00,0xb4,0x8f,0x0c,0x00,0xb3,0x8f,
36510x08,0x00,0xb2,0x8f,0x04,0x00,0xb1,0x8f,0x00,0x00,0xb0,0x8f,0x02,0x80,0x07,0x3c,
36520x02,0x80,0x03,0x3c,0x50,0x15,0xe4,0x24,0x00,0x14,0x63,0x24,0x03,0x00,0x02,0x24,
36530x20,0x00,0xbd,0x27,0x58,0x01,0x78,0xac,0x04,0x00,0x48,0xad,0x04,0x00,0xa4,0xac,
36540x60,0x01,0x62,0xac,0x50,0x15,0xe5,0xac,0x04,0x00,0x86,0xac,0x08,0x00,0xe0,0x03,
36550x00,0x00,0xc4,0xac,0xd0,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x20,0x00,0xb2,0xaf,
36560x02,0x80,0x03,0x3c,0x4c,0x91,0x52,0x24,0x02,0x80,0x02,0x3c,0x28,0x00,0xb4,0xaf,
36570x24,0x00,0xb3,0xaf,0x1c,0x00,0xb1,0xaf,0x18,0x00,0xb0,0xaf,0x2c,0x00,0xbf,0xaf,
36580xd8,0x90,0x73,0x24,0x68,0x15,0x50,0x24,0x21,0x88,0x00,0x00,0x02,0x80,0x14,0x3c,
36590xee,0x4e,0x00,0x0c,0x21,0x20,0x20,0x02,0x78,0x51,0x05,0x8e,0x6c,0x00,0x66,0x8e,
36600xb8,0x90,0x82,0x26,0x6c,0x00,0x43,0x8e,0x1b,0x00,0x44,0x90,0xff,0xf1,0x02,0x24,
36610x21,0x18,0x66,0x00,0x24,0x28,0xa2,0x00,0x00,0x21,0x04,0x00,0x42,0x18,0x03,0x00,
36620x00,0x02,0xa5,0x34,0x44,0x51,0x03,0xae,0x68,0x51,0x04,0xae,0x78,0x51,0x05,0xae,
36630x6c,0x51,0x04,0xae,0x21,0x30,0x00,0x00,0x21,0x10,0x06,0x02,0x01,0x00,0xc6,0x24,
36640x1d,0x00,0xc3,0x28,0x99,0x51,0x40,0xa0,0x7c,0x51,0x40,0xa0,0xfa,0xff,0x60,0x14,
36650xb6,0x51,0x40,0xa0,0x01,0x00,0x31,0x26,0x20,0x00,0x22,0x2a,0xd4,0x51,0x00,0xae,
36660xe3,0xff,0x40,0x14,0x94,0x00,0x10,0x26,0x02,0x80,0x02,0x3c,0x02,0x80,0x03,0x3c,
36670x68,0x15,0x4b,0x24,0x02,0x80,0x02,0x3c,0x4c,0x91,0x6f,0x24,0xd8,0x90,0x4d,0x24,
36680x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0xb8,0x90,0x6e,0x24,0x98,0x90,0x4c,0x24,
36690x21,0x88,0x00,0x00,0x80,0x18,0x11,0x00,0x21,0x20,0x6d,0x00,0x21,0x10,0x6f,0x00,
36700x21,0x28,0x2e,0x02,0x21,0x30,0x2c,0x02,0x00,0x00,0x88,0x8c,0x00,0x00,0xa9,0x90,
36710x00,0x00,0xc7,0x90,0x00,0x00,0x4a,0x8c,0x21,0x10,0x2b,0x02,0x01,0x00,0x31,0x26,
36720x21,0x18,0x6b,0x00,0x1d,0x00,0x24,0x2a,0xec,0x44,0x68,0xac,0xca,0x44,0x47,0xa0,
36730x60,0x45,0x6a,0xac,0xef,0xff,0x80,0x14,0x90,0x44,0x49,0xa0,0x02,0x80,0x02,0x3c,
36740x68,0x15,0x4a,0x24,0x02,0x80,0x03,0x3c,0x02,0x80,0x02,0x3c,0x74,0x8f,0x6b,0x24,
36750x14,0x8e,0x4c,0x24,0x21,0x88,0x00,0x00,0x21,0x48,0x00,0x00,0x21,0x30,0x00,0x00,
36760x21,0x40,0x2a,0x01,0x21,0x38,0x2b,0x01,0x21,0x10,0xe6,0x00,0x91,0x00,0x44,0x90,
36770x00,0x00,0x45,0x90,0x21,0x18,0x06,0x01,0x01,0x00,0xc6,0x24,0x05,0x00,0xc2,0x28,
36780xc5,0x43,0x64,0xa0,0xf8,0xff,0x40,0x14,0x34,0x43,0x65,0xa0,0x21,0x10,0x2c,0x02,
36790x1d,0x00,0x44,0x90,0x00,0x00,0x45,0x90,0x21,0x18,0x2a,0x02,0x01,0x00,0x31,0x26,
36800x1d,0x00,0x22,0x2a,0x73,0x44,0x64,0xa0,0x56,0x44,0x65,0xa0,0xeb,0xff,0x40,0x14,
36810x05,0x00,0x29,0x25,0x52,0x00,0x02,0x24,0x10,0x00,0xa2,0xa3,0x41,0x00,0x03,0x24,
36820x4d,0x00,0x02,0x24,0x02,0x80,0x07,0x3c,0x1c,0x97,0xe7,0x24,0x11,0x00,0xa3,0xa3,
36830x12,0x00,0xa2,0xa3,0xe8,0x03,0x03,0x24,0x01,0x00,0x02,0x24,0x00,0x80,0x06,0x3c,
36840x10,0x00,0xa5,0x27,0x21,0x20,0xe0,0x00,0xf0,0x37,0xc6,0x24,0x0c,0x00,0xe3,0xac,
36850x14,0x00,0xe2,0xa0,0xfb,0x0c,0x00,0x0c,0x13,0x00,0xa0,0xa3,0x2c,0x00,0xbf,0x8f,
36860x28,0x00,0xb4,0x8f,0x24,0x00,0xb3,0x8f,0x20,0x00,0xb2,0x8f,0x1c,0x00,0xb1,0x8f,
36870x18,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x30,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,
36880x02,0x80,0x02,0x3c,0x42,0x00,0x03,0x24,0x10,0x00,0xa3,0xa3,0x55,0x60,0x40,0xa0,
36890x4e,0x00,0x03,0x24,0x43,0x00,0x02,0x24,0x02,0x80,0x07,0x3c,0x54,0x97,0xe7,0x24,
36900x11,0x00,0xa2,0xa3,0x12,0x00,0xa3,0xa3,0xd0,0x07,0x02,0x24,0x01,0x00,0x03,0x24,
36910x00,0x80,0x06,0x3c,0x10,0x00,0xa5,0x27,0x21,0x20,0xe0,0x00,0xdc,0x44,0xc6,0x24,
36920x0c,0x00,0xe2,0xac,0x14,0x00,0xe3,0xa0,0x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,
36930x13,0x00,0xa0,0xa3,0x18,0x00,0xbf,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
36940x20,0x00,0xbd,0x27,0x48,0xfd,0xbd,0x27,0xb4,0x02,0xb3,0xaf,0x02,0x80,0x02,0x3c,
36950x02,0x80,0x13,0x3c,0x24,0x92,0x46,0x24,0x68,0x15,0x63,0x26,0xb0,0x02,0xb2,0xaf,
36960xac,0x02,0xb1,0xaf,0xa8,0x02,0xb0,0xaf,0x03,0x40,0x60,0xa0,0x21,0x38,0xa0,0x03,
36970x90,0x00,0xc8,0x24,0x00,0x00,0xc2,0x8c,0x04,0x00,0xc3,0x8c,0x08,0x00,0xc4,0x8c,
36980x0c,0x00,0xc5,0x8c,0x10,0x00,0xc6,0x24,0x00,0x00,0xe2,0xac,0x04,0x00,0xe3,0xac,
36990x08,0x00,0xe4,0xac,0x0c,0x00,0xe5,0xac,0xf6,0xff,0xc8,0x14,0x10,0x00,0xe7,0x24,
37000x00,0x00,0xc3,0x8c,0x02,0x80,0x02,0x3c,0xb8,0x92,0x58,0x24,0x00,0x00,0xe3,0xac,
37010x98,0x00,0xb9,0x27,0x00,0x01,0x12,0x27,0x01,0x00,0x02,0x93,0x05,0x00,0x03,0x93,
37020x09,0x00,0x04,0x93,0x0d,0x00,0x05,0x93,0x00,0x00,0x11,0x93,0x02,0x00,0x0d,0x93,
37030x04,0x00,0x10,0x93,0x06,0x00,0x0c,0x93,0x08,0x00,0x0f,0x93,0x0a,0x00,0x07,0x93,
37040x0c,0x00,0x0e,0x93,0x0e,0x00,0x06,0x93,0x03,0x00,0x08,0x93,0x07,0x00,0x09,0x93,
37050x0b,0x00,0x0a,0x93,0x0f,0x00,0x0b,0x93,0x00,0x12,0x02,0x00,0x00,0x1a,0x03,0x00,
37060x00,0x22,0x04,0x00,0x00,0x2a,0x05,0x00,0x25,0x10,0x51,0x00,0x25,0x18,0x70,0x00,
37070x25,0x20,0x8f,0x00,0x25,0x28,0xae,0x00,0x00,0x6c,0x0d,0x00,0x00,0x64,0x0c,0x00,
37080x00,0x3c,0x07,0x00,0x00,0x34,0x06,0x00,0x25,0x68,0xa2,0x01,0x25,0x60,0x83,0x01,
37090x25,0x38,0xe4,0x00,0x25,0x30,0xc5,0x00,0x00,0x46,0x08,0x00,0x00,0x4e,0x09,0x00,
37100x00,0x56,0x0a,0x00,0x00,0x5e,0x0b,0x00,0x25,0x40,0x0d,0x01,0x25,0x48,0x2c,0x01,
37110x25,0x50,0x47,0x01,0x25,0x58,0x66,0x01,0x10,0x00,0x18,0x27,0x00,0x00,0x28,0xaf,
37120x04,0x00,0x29,0xaf,0x08,0x00,0x2a,0xaf,0x0c,0x00,0x2b,0xaf,0xd2,0xff,0x12,0x17,
37130x10,0x00,0x39,0x27,0x01,0x00,0x02,0x93,0x05,0x00,0x03,0x93,0x00,0x00,0x09,0x93,
37140x02,0x00,0x04,0x93,0x04,0x00,0x08,0x93,0x06,0x00,0x05,0x93,0x07,0x00,0x06,0x93,
37150x03,0x00,0x07,0x93,0x00,0x12,0x02,0x00,0x00,0x1a,0x03,0x00,0x25,0x10,0x49,0x00,
37160x25,0x18,0x68,0x00,0x00,0x24,0x04,0x00,0x00,0x2c,0x05,0x00,0x25,0x20,0x82,0x00,
37170x25,0x28,0xa3,0x00,0x00,0x3e,0x07,0x00,0x00,0x36,0x06,0x00,0x02,0x80,0x02,0x3c,
37180x25,0x38,0xe4,0x00,0x25,0x30,0xc5,0x00,0xc0,0x93,0x58,0x24,0x04,0x00,0x26,0xaf,
37190x00,0x00,0x27,0xaf,0x00,0x01,0x12,0x27,0xa0,0x01,0xb9,0x27,0x01,0x00,0x02,0x93,
37200x05,0x00,0x03,0x93,0x09,0x00,0x04,0x93,0x0d,0x00,0x05,0x93,0x00,0x00,0x11,0x93,
37210x02,0x00,0x0d,0x93,0x04,0x00,0x10,0x93,0x06,0x00,0x0c,0x93,0x08,0x00,0x0f,0x93,
37220x0a,0x00,0x07,0x93,0x0c,0x00,0x0e,0x93,0x0e,0x00,0x06,0x93,0x03,0x00,0x08,0x93,
37230x07,0x00,0x09,0x93,0x0b,0x00,0x0a,0x93,0x0f,0x00,0x0b,0x93,0x00,0x12,0x02,0x00,
37240x00,0x1a,0x03,0x00,0x00,0x22,0x04,0x00,0x00,0x2a,0x05,0x00,0x25,0x10,0x51,0x00,
37250x25,0x18,0x70,0x00,0x25,0x20,0x8f,0x00,0x25,0x28,0xae,0x00,0x00,0x6c,0x0d,0x00,
37260x00,0x64,0x0c,0x00,0x00,0x3c,0x07,0x00,0x00,0x34,0x06,0x00,0x25,0x68,0xa2,0x01,
37270x25,0x60,0x83,0x01,0x25,0x38,0xe4,0x00,0x25,0x30,0xc5,0x00,0x00,0x46,0x08,0x00,
37280x00,0x4e,0x09,0x00,0x00,0x56,0x0a,0x00,0x00,0x5e,0x0b,0x00,0x25,0x40,0x0d,0x01,
37290x25,0x48,0x2c,0x01,0x25,0x50,0x47,0x01,0x25,0x58,0x66,0x01,0x10,0x00,0x18,0x27,
37300x00,0x00,0x28,0xaf,0x04,0x00,0x29,0xaf,0x08,0x00,0x2a,0xaf,0x0c,0x00,0x2b,0xaf,
37310xd2,0xff,0x12,0x17,0x10,0x00,0x39,0x27,0x01,0x00,0x02,0x93,0x05,0x00,0x03,0x93,
37320x00,0x00,0x09,0x93,0x02,0x00,0x04,0x93,0x04,0x00,0x08,0x93,0x06,0x00,0x05,0x93,
37330x07,0x00,0x06,0x93,0x03,0x00,0x07,0x93,0x00,0x12,0x02,0x00,0x00,0x1a,0x03,0x00,
37340x25,0x10,0x49,0x00,0x25,0x18,0x68,0x00,0x00,0x24,0x04,0x00,0x00,0x2c,0x05,0x00,
37350x25,0x20,0x82,0x00,0x25,0x28,0xa3,0x00,0x00,0x3e,0x07,0x00,0x00,0x36,0x06,0x00,
37360x25,0x30,0xc5,0x00,0x25,0x38,0xe4,0x00,0x02,0x80,0x02,0x3c,0x04,0x00,0x26,0xaf,
37370x00,0x00,0x27,0xaf,0x68,0x15,0x46,0x24,0x21,0x50,0x00,0x00,0x80,0x20,0x0a,0x00,
37380x21,0x10,0x9d,0x00,0x00,0x00,0x45,0x8c,0x01,0x00,0x43,0x25,0xff,0x00,0x6a,0x30,
37390x21,0x20,0x86,0x00,0x25,0x00,0x42,0x2d,0xf8,0xff,0x40,0x14,0x18,0x40,0x85,0xac,
37400x02,0x80,0x02,0x3c,0x68,0x15,0x4b,0x24,0x21,0x50,0x00,0x00,0xc0,0x10,0x0a,0x00,
37410x21,0x48,0x5d,0x00,0x21,0x38,0x00,0x00,0x21,0x40,0x4b,0x00,0x21,0x10,0x27,0x01,
37420xa0,0x01,0x46,0x90,0x98,0x00,0x45,0x90,0x01,0x00,0xe4,0x24,0x21,0x18,0x07,0x01,
37430xff,0x00,0x87,0x30,0x08,0x00,0xe2,0x2c,0xb4,0x41,0x66,0xa0,0xf7,0xff,0x40,0x14,
37440xac,0x40,0x65,0xa0,0x01,0x00,0x42,0x25,0xff,0x00,0x4a,0x30,0x21,0x00,0x43,0x2d,
37450xef,0xff,0x60,0x14,0xc0,0x10,0x0a,0x00,0x25,0xb0,0x02,0x3c,0x0a,0x00,0x42,0x34,
37460x00,0x00,0x43,0x90,0x00,0x00,0x00,0x00,0x20,0x00,0x63,0x30,0x42,0x00,0x60,0x10,
37470x68,0x15,0x64,0x26,0x33,0x00,0x02,0x24,0xc1,0x42,0x62,0xa1,0x1c,0x00,0x03,0x24,
37480x0f,0x00,0x02,0x24,0xbc,0x42,0x63,0xa1,0xbd,0x42,0x62,0xa1,0x68,0x15,0x65,0x26,
37490x08,0x40,0xa4,0x8c,0xff,0x7f,0x08,0x3c,0xff,0xff,0x08,0x35,0xc0,0xff,0x02,0x24,
37500x24,0x20,0x88,0x00,0x24,0x20,0x82,0x00,0x0c,0x00,0x84,0x34,0xff,0xc0,0x02,0x24,
37510x24,0x20,0x82,0x00,0xc0,0xff,0x02,0x3c,0xff,0xff,0x42,0x34,0x00,0x18,0x84,0x34,
37520xbf,0xff,0x03,0x3c,0x24,0x20,0x82,0x00,0xff,0xff,0x63,0x34,0x7f,0xff,0x02,0x3c,
37530x24,0x20,0x83,0x00,0xff,0xff,0x42,0x34,0x24,0x20,0x82,0x00,0x0c,0x40,0xa6,0x8c,
37540x7f,0xff,0x03,0x24,0x40,0x40,0x84,0x34,0xff,0xff,0x02,0x3c,0x24,0x20,0x83,0x00,
37550xff,0x7f,0x42,0x34,0xff,0xbf,0x03,0x3c,0x10,0x40,0xa7,0x8c,0x24,0x20,0x82,0x00,
37560xff,0xff,0x63,0x34,0xff,0x9f,0x02,0x3c,0x24,0x30,0xc3,0x00,0xff,0xff,0x42,0x34,
37570xff,0x3f,0x03,0x3c,0x24,0x20,0x82,0x00,0xff,0xff,0x63,0x34,0x12,0x00,0x02,0x24,
37580xb4,0x02,0xb3,0x8f,0xb0,0x02,0xb2,0x8f,0xac,0x02,0xb1,0x8f,0xa8,0x02,0xb0,0x8f,
37590x24,0x38,0xe3,0x00,0xc7,0x42,0xa2,0xa0,0x1f,0x00,0x03,0x24,0x01,0x00,0x02,0x24,
37600x24,0x30,0xc8,0x00,0xbe,0x42,0xa3,0xa0,0xc0,0x42,0xa2,0xa0,0xff,0x00,0x03,0x24,
37610xff,0xff,0x02,0x24,0xb8,0x02,0xbd,0x27,0x08,0x40,0xa4,0xac,0x10,0x40,0xa7,0xac,
37620x0c,0x40,0xa6,0xac,0xc2,0x42,0xa2,0xa0,0xc4,0x42,0xa3,0xa4,0xbf,0x42,0xa0,0xa0,
37630x08,0x00,0xe0,0x03,0xc6,0x42,0xa0,0xa0,0x33,0x00,0x02,0x24,0xc1,0x42,0x82,0xa0,
37640x0d,0x00,0x03,0x24,0x03,0x00,0x02,0x24,0xbc,0x42,0x83,0xa0,0x65,0x5d,0x00,0x08,
37650xbd,0x42,0x82,0xa0,0xe0,0xff,0xbd,0x27,0x02,0x80,0x07,0x3c,0x68,0x15,0xe7,0x24,
37660x18,0x00,0xbf,0xaf,0x00,0x40,0xe3,0x8c,0xf0,0xff,0x02,0x24,0x02,0x80,0x08,0x3c,
37670x24,0x18,0x62,0x00,0xff,0xf0,0x02,0x24,0x24,0x18,0x62,0x00,0x00,0x40,0xe3,0xac,
37680x1c,0x00,0x03,0x24,0x36,0x00,0x02,0x24,0xcf,0x42,0xe3,0xa0,0x20,0x00,0x03,0x24,
37690xce,0x42,0xe2,0xa0,0xd1,0x42,0xe3,0xa0,0x32,0x00,0x02,0x24,0x20,0x00,0x03,0x24,
37700xd0,0x42,0xe2,0xa0,0xc8,0x42,0xe3,0xa4,0x0a,0x00,0x02,0x24,0x00,0x02,0x03,0x24,
37710xd2,0x42,0xe2,0xa0,0xcc,0x42,0xe3,0xa4,0x00,0x01,0x02,0x24,0x49,0x00,0x03,0x24,
37720x38,0x97,0x08,0x25,0xff,0xff,0x0a,0x34,0x01,0x00,0x09,0x24,0x11,0x00,0xa3,0xa3,
37730xca,0x42,0xe2,0xa4,0xd0,0x07,0x03,0x24,0x44,0x00,0x02,0x24,0x00,0x80,0x06,0x3c,
37740x10,0x00,0xa2,0xa3,0x10,0x00,0xa5,0x27,0x47,0x00,0x02,0x24,0x21,0x20,0x00,0x01,
37750x54,0x45,0xc6,0x24,0x04,0x40,0xea,0xac,0x02,0x40,0xe9,0xa0,0x0c,0x00,0x03,0xad,
37760x14,0x00,0x09,0xa1,0xe6,0x42,0xe0,0xa0,0xdc,0x63,0xea,0xac,0xd7,0x42,0xe0,0xa0,
37770x12,0x00,0xa2,0xa3,0xfb,0x0c,0x00,0x0c,0x13,0x00,0xa0,0xa3,0x18,0x00,0xbf,0x8f,
37780x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,
37790x02,0x80,0x02,0x3c,0x50,0x00,0x03,0x24,0x10,0x00,0xa3,0xa3,0x2a,0x62,0x40,0xa0,
37800x41,0x00,0x03,0x24,0x52,0x00,0x02,0x24,0x02,0x80,0x07,0x3c,0xc4,0x97,0xe7,0x24,
37810x11,0x00,0xa2,0xa3,0x12,0x00,0xa3,0xa3,0xd0,0x07,0x02,0x24,0x01,0x00,0x03,0x24,
37820x01,0x80,0x06,0x3c,0x10,0x00,0xa5,0x27,0x21,0x20,0xe0,0x00,0x88,0x5b,0xc6,0x24,
37830x0c,0x00,0xe2,0xac,0x14,0x00,0xe3,0xa0,0x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,
37840x13,0x00,0xa0,0xa3,0x18,0x00,0xbf,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
37850x20,0x00,0xbd,0x27,0xd8,0xff,0xbd,0x27,0x18,0x00,0xb0,0xaf,0x02,0x80,0x10,0x3c,
37860x68,0x15,0x10,0x26,0x20,0x00,0xbf,0xaf,0x1c,0x00,0xb1,0xaf,0x00,0x40,0x09,0x8e,
37870xff,0xff,0x02,0x24,0xff,0x00,0x4b,0x30,0x0f,0xff,0x02,0x24,0x24,0x48,0x22,0x01,
37880xff,0xff,0x02,0x3c,0xff,0x0f,0x42,0x34,0x24,0x48,0x22,0x01,0x01,0x00,0x07,0x3c,
37890x47,0x00,0x02,0x24,0x3b,0x00,0x03,0x24,0x02,0x80,0x08,0x3c,0x10,0x00,0xa2,0xa3,
37900x11,0x00,0xa3,0xa3,0xe0,0x97,0x08,0x25,0x56,0x30,0xea,0x34,0xd0,0x07,0x02,0x24,
37910x01,0x00,0x03,0x24,0xf4,0x98,0xe7,0x34,0x00,0x80,0x06,0x3c,0x04,0x43,0x0b,0xae,
37920x00,0x40,0x09,0xae,0x43,0x00,0x11,0x24,0x10,0x00,0xa5,0x27,0x0c,0x43,0x07,0xae,
37930x10,0x43,0x0a,0xae,0x0c,0x00,0x02,0xad,0x14,0x00,0x03,0xa1,0x08,0x43,0x00,0xae,
37940x14,0x43,0x00,0xae,0x18,0x43,0x00,0xae,0x21,0x20,0x00,0x01,0xe4,0x4e,0xc6,0x24,
37950x12,0x00,0xb1,0xa3,0xfb,0x0c,0x00,0x0c,0x13,0x00,0xa0,0xa3,0x1e,0x00,0x02,0x24,
37960x21,0x43,0x02,0xa2,0x4a,0x00,0x03,0x24,0x45,0x00,0x02,0x24,0x1c,0x43,0x03,0xa2,
37970x1d,0x43,0x02,0xa2,0x23,0x00,0x03,0x24,0x3e,0x00,0x02,0x24,0x1e,0x43,0x11,0xa2,
37980x1f,0x43,0x02,0xa2,0x20,0x43,0x03,0xa2,0x20,0x00,0xbf,0x8f,0x1c,0x00,0xb1,0x8f,
37990x18,0x00,0xb0,0x8f,0x08,0x00,0xe0,0x03,0x28,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,
38000x3b,0x00,0x02,0x24,0x43,0x00,0x03,0x24,0x10,0x00,0xa2,0xa3,0x11,0x00,0xa3,0xa3,
38010x36,0x00,0x02,0x24,0x02,0x80,0x03,0x3c,0x02,0x80,0x07,0x3c,0xfc,0x97,0xe7,0x24,
38020x12,0x00,0xa2,0xa3,0x3b,0x58,0x60,0xa0,0xd0,0x07,0x02,0x24,0x01,0x00,0x03,0x24,
38030x00,0x80,0x06,0x3c,0x10,0x00,0xa5,0x27,0x21,0x20,0xe0,0x00,0x20,0x53,0xc6,0x24,
38040x0c,0x00,0xe2,0xac,0x14,0x00,0xe3,0xa0,0x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,
38050x13,0x00,0xa0,0xa3,0x18,0x00,0xbf,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
38060x20,0x00,0xbd,0x27,0xff,0xff,0x07,0x24,0x02,0x80,0x02,0x3c,0xe0,0xff,0xbd,0x27,
38070x3d,0x58,0x47,0xa0,0x3b,0x00,0x03,0x24,0x43,0x00,0x02,0x24,0x10,0x00,0xa3,0xa3,
38080x11,0x00,0xa2,0xa3,0x36,0x00,0x03,0x24,0x16,0x00,0x02,0x24,0x02,0x80,0x08,0x3c,
38090x18,0x98,0x08,0x25,0x12,0x00,0xa3,0xa3,0x13,0x00,0xa2,0xa3,0xd0,0x07,0x03,0x24,
38100x01,0x00,0x02,0x24,0x00,0x80,0x06,0x3c,0x10,0x00,0xa5,0x27,0x21,0x20,0x00,0x01,
38110x0c,0x00,0x03,0xad,0x14,0x00,0x02,0xa1,0x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,
38120xb8,0x54,0xc6,0x24,0x18,0x00,0xbf,0x8f,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,
38130x20,0x00,0xbd,0x27,0xe0,0xff,0xbd,0x27,0x02,0x80,0x02,0x3c,0x52,0x00,0x03,0x24,
38140x10,0x00,0xa3,0xa3,0x4c,0x79,0x40,0xa4,0x54,0x00,0x03,0x24,0x53,0x00,0x02,0x24,
38150x02,0x80,0x07,0x3c,0x34,0x98,0xe7,0x24,0x11,0x00,0xa2,0xa3,0x12,0x00,0xa3,0xa3,
38160xf4,0x01,0x02,0x24,0x01,0x00,0x03,0x24,0x01,0x80,0x06,0x3c,0x10,0x00,0xa5,0x27,
38170x21,0x20,0xe0,0x00,0xc8,0x5c,0xc6,0x24,0x0c,0x00,0xe2,0xac,0x14,0x00,0xe3,0xa0,
38180x18,0x00,0xbf,0xaf,0xfb,0x0c,0x00,0x0c,0x13,0x00,0xa0,0xa3,0x18,0x00,0xbf,0x8f,
38190x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x20,0x00,0xbd,0x27,0x00,0x00,0x00,0x00,
38200x00,0x00,0x00,0x00,0x78,0x0c,0x00,0x00,0x01,0x00,0x00,0x5e,0x78,0x0c,0x00,0x00,
38210x01,0x00,0x01,0x5e,0x78,0x0c,0x00,0x00,0x01,0x00,0x02,0x5e,0x78,0x0c,0x00,0x00,
38220x01,0x00,0x03,0x5e,0x78,0x0c,0x00,0x00,0x01,0x00,0x04,0x5d,0x78,0x0c,0x00,0x00,
38230x01,0x00,0x05,0x5b,0x78,0x0c,0x00,0x00,0x01,0x00,0x06,0x59,0x78,0x0c,0x00,0x00,
38240x01,0x00,0x07,0x57,0x78,0x0c,0x00,0x00,0x01,0x00,0x08,0x55,0x78,0x0c,0x00,0x00,
38250x01,0x00,0x09,0x53,0x78,0x0c,0x00,0x00,0x01,0x00,0x0a,0x51,0x78,0x0c,0x00,0x00,
38260x01,0x00,0x0b,0x4f,0x78,0x0c,0x00,0x00,0x01,0x00,0x0c,0x4d,0x78,0x0c,0x00,0x00,
38270x01,0x00,0x0d,0x4b,0x78,0x0c,0x00,0x00,0x01,0x00,0x0e,0x49,0x78,0x0c,0x00,0x00,
38280x01,0x00,0x0f,0x47,0x78,0x0c,0x00,0x00,0x01,0x00,0x10,0x45,0x78,0x0c,0x00,0x00,
38290x01,0x00,0x11,0x43,0x78,0x0c,0x00,0x00,0x01,0x00,0x12,0x41,0x78,0x0c,0x00,0x00,
38300x01,0x00,0x13,0x3f,0x78,0x0c,0x00,0x00,0x01,0x00,0x14,0x3d,0x78,0x0c,0x00,0x00,
38310x01,0x00,0x15,0x3b,0x78,0x0c,0x00,0x00,0x01,0x00,0x16,0x39,0x78,0x0c,0x00,0x00,
38320x01,0x00,0x17,0x37,0x78,0x0c,0x00,0x00,0x01,0x00,0x18,0x35,0x78,0x0c,0x00,0x00,
38330x01,0x00,0x19,0x33,0x78,0x0c,0x00,0x00,0x01,0x00,0x1a,0x31,0x78,0x0c,0x00,0x00,
38340x01,0x00,0x1b,0x2f,0x78,0x0c,0x00,0x00,0x01,0x00,0x1c,0x2d,0x78,0x0c,0x00,0x00,
38350x01,0x00,0x1d,0x2b,0x78,0x0c,0x00,0x00,0x01,0x00,0x1e,0x29,0x78,0x0c,0x00,0x00,
38360x01,0x00,0x1f,0x27,0x78,0x0c,0x00,0x00,0x01,0x00,0x20,0x25,0x78,0x0c,0x00,0x00,
38370x01,0x00,0x21,0x23,0x78,0x0c,0x00,0x00,0x01,0x00,0x22,0x21,0x78,0x0c,0x00,0x00,
38380x01,0x00,0x23,0x1f,0x78,0x0c,0x00,0x00,0x01,0x00,0x24,0x1d,0x78,0x0c,0x00,0x00,
38390x01,0x00,0x25,0x1b,0x78,0x0c,0x00,0x00,0x01,0x00,0x26,0x19,0x78,0x0c,0x00,0x00,
38400x01,0x00,0x27,0x17,0x78,0x0c,0x00,0x00,0x01,0x00,0x28,0x15,0x78,0x0c,0x00,0x00,
38410x01,0x00,0x29,0x13,0x78,0x0c,0x00,0x00,0x01,0x00,0x2a,0x11,0x78,0x0c,0x00,0x00,
38420x01,0x00,0x2b,0x0f,0x78,0x0c,0x00,0x00,0x01,0x00,0x2c,0x0d,0x78,0x0c,0x00,0x00,
38430x01,0x00,0x2d,0x0b,0x78,0x0c,0x00,0x00,0x01,0x00,0x2e,0x09,0x78,0x0c,0x00,0x00,
38440x01,0x00,0x2f,0x07,0x78,0x0c,0x00,0x00,0x01,0x00,0x30,0x05,0x78,0x0c,0x00,0x00,
38450x01,0x00,0x31,0x03,0x78,0x0c,0x00,0x00,0x01,0x00,0x32,0x01,0x78,0x0c,0x00,0x00,
38460x01,0x00,0x33,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x34,0x01,0x78,0x0c,0x00,0x00,
38470x01,0x00,0x35,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x36,0x01,0x78,0x0c,0x00,0x00,
38480x01,0x00,0x37,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x38,0x01,0x78,0x0c,0x00,0x00,
38490x01,0x00,0x39,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x3a,0x01,0x78,0x0c,0x00,0x00,
38500x01,0x00,0x3b,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x3c,0x01,0x78,0x0c,0x00,0x00,
38510x01,0x00,0x3d,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x3e,0x01,0x78,0x0c,0x00,0x00,
38520x01,0x00,0x3f,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x40,0x5e,0x78,0x0c,0x00,0x00,
38530x01,0x00,0x41,0x5e,0x78,0x0c,0x00,0x00,0x01,0x00,0x42,0x5e,0x78,0x0c,0x00,0x00,
38540x01,0x00,0x43,0x5e,0x78,0x0c,0x00,0x00,0x01,0x00,0x44,0x5d,0x78,0x0c,0x00,0x00,
38550x01,0x00,0x45,0x5b,0x78,0x0c,0x00,0x00,0x01,0x00,0x46,0x59,0x78,0x0c,0x00,0x00,
38560x01,0x00,0x47,0x57,0x78,0x0c,0x00,0x00,0x01,0x00,0x48,0x55,0x78,0x0c,0x00,0x00,
38570x01,0x00,0x49,0x53,0x78,0x0c,0x00,0x00,0x01,0x00,0x4a,0x51,0x78,0x0c,0x00,0x00,
38580x01,0x00,0x4b,0x4f,0x78,0x0c,0x00,0x00,0x01,0x00,0x4c,0x4d,0x78,0x0c,0x00,0x00,
38590x01,0x00,0x4d,0x4b,0x78,0x0c,0x00,0x00,0x01,0x00,0x4e,0x49,0x78,0x0c,0x00,0x00,
38600x01,0x00,0x4f,0x47,0x78,0x0c,0x00,0x00,0x01,0x00,0x50,0x45,0x78,0x0c,0x00,0x00,
38610x01,0x00,0x51,0x43,0x78,0x0c,0x00,0x00,0x01,0x00,0x52,0x41,0x78,0x0c,0x00,0x00,
38620x01,0x00,0x53,0x3f,0x78,0x0c,0x00,0x00,0x01,0x00,0x54,0x3d,0x78,0x0c,0x00,0x00,
38630x01,0x00,0x55,0x3b,0x78,0x0c,0x00,0x00,0x01,0x00,0x56,0x39,0x78,0x0c,0x00,0x00,
38640x01,0x00,0x57,0x37,0x78,0x0c,0x00,0x00,0x01,0x00,0x58,0x35,0x78,0x0c,0x00,0x00,
38650x01,0x00,0x59,0x33,0x78,0x0c,0x00,0x00,0x01,0x00,0x5a,0x31,0x78,0x0c,0x00,0x00,
38660x01,0x00,0x5b,0x2f,0x78,0x0c,0x00,0x00,0x01,0x00,0x5c,0x2d,0x78,0x0c,0x00,0x00,
38670x01,0x00,0x5d,0x2b,0x78,0x0c,0x00,0x00,0x01,0x00,0x5e,0x29,0x78,0x0c,0x00,0x00,
38680x01,0x00,0x5f,0x27,0x78,0x0c,0x00,0x00,0x01,0x00,0x60,0x25,0x78,0x0c,0x00,0x00,
38690x01,0x00,0x61,0x23,0x78,0x0c,0x00,0x00,0x01,0x00,0x62,0x21,0x78,0x0c,0x00,0x00,
38700x01,0x00,0x63,0x1f,0x78,0x0c,0x00,0x00,0x01,0x00,0x64,0x1d,0x78,0x0c,0x00,0x00,
38710x01,0x00,0x65,0x1b,0x78,0x0c,0x00,0x00,0x01,0x00,0x66,0x19,0x78,0x0c,0x00,0x00,
38720x01,0x00,0x67,0x17,0x78,0x0c,0x00,0x00,0x01,0x00,0x68,0x15,0x78,0x0c,0x00,0x00,
38730x01,0x00,0x69,0x13,0x78,0x0c,0x00,0x00,0x01,0x00,0x6a,0x11,0x78,0x0c,0x00,0x00,
38740x01,0x00,0x6b,0x0f,0x78,0x0c,0x00,0x00,0x01,0x00,0x6c,0x0d,0x78,0x0c,0x00,0x00,
38750x01,0x00,0x6d,0x0b,0x78,0x0c,0x00,0x00,0x01,0x00,0x6e,0x09,0x78,0x0c,0x00,0x00,
38760x01,0x00,0x6f,0x07,0x78,0x0c,0x00,0x00,0x01,0x00,0x70,0x05,0x78,0x0c,0x00,0x00,
38770x01,0x00,0x71,0x03,0x78,0x0c,0x00,0x00,0x01,0x00,0x72,0x01,0x78,0x0c,0x00,0x00,
38780x01,0x00,0x73,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x74,0x01,0x78,0x0c,0x00,0x00,
38790x01,0x00,0x75,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x76,0x01,0x78,0x0c,0x00,0x00,
38800x01,0x00,0x77,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x78,0x01,0x78,0x0c,0x00,0x00,
38810x01,0x00,0x79,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x7a,0x01,0x78,0x0c,0x00,0x00,
38820x01,0x00,0x7b,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x7c,0x01,0x78,0x0c,0x00,0x00,
38830x01,0x00,0x7d,0x01,0x78,0x0c,0x00,0x00,0x01,0x00,0x7e,0x01,0x78,0x0c,0x00,0x00,
38840x01,0x00,0x7f,0x01,0x78,0x0c,0x00,0x00,0x1e,0x00,0x00,0x30,0x78,0x0c,0x00,0x00,
38850x1e,0x00,0x01,0x30,0x78,0x0c,0x00,0x00,0x1e,0x00,0x02,0x30,0x78,0x0c,0x00,0x00,
38860x1e,0x00,0x03,0x30,0x78,0x0c,0x00,0x00,0x1e,0x00,0x04,0x30,0x78,0x0c,0x00,0x00,
38870x1e,0x00,0x05,0x30,0x78,0x0c,0x00,0x00,0x1e,0x00,0x06,0x30,0x78,0x0c,0x00,0x00,
38880x1e,0x00,0x07,0x30,0x78,0x0c,0x00,0x00,0x1e,0x00,0x08,0x3e,0x78,0x0c,0x00,0x00,
38890x1e,0x00,0x09,0x40,0x78,0x0c,0x00,0x00,0x1e,0x00,0x0a,0x42,0x78,0x0c,0x00,0x00,
38900x1e,0x00,0x0b,0x44,0x78,0x0c,0x00,0x00,0x1e,0x00,0x0c,0x46,0x78,0x0c,0x00,0x00,
38910x1e,0x00,0x0d,0x48,0x78,0x0c,0x00,0x00,0x1e,0x00,0x0e,0x48,0x78,0x0c,0x00,0x00,
38920x1e,0x00,0x0f,0x4a,0x78,0x0c,0x00,0x00,0x1e,0x00,0x10,0x4a,0x78,0x0c,0x00,0x00,
38930x1e,0x00,0x11,0x4c,0x78,0x0c,0x00,0x00,0x1e,0x00,0x12,0x4c,0x78,0x0c,0x00,0x00,
38940x1e,0x00,0x13,0x4e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x14,0x50,0x78,0x0c,0x00,0x00,
38950x1e,0x00,0x15,0x50,0x78,0x0c,0x00,0x00,0x1e,0x00,0x16,0x50,0x78,0x0c,0x00,0x00,
38960x1e,0x00,0x17,0x52,0x78,0x0c,0x00,0x00,0x1e,0x00,0x18,0x52,0x78,0x0c,0x00,0x00,
38970x1e,0x00,0x19,0x52,0x78,0x0c,0x00,0x00,0x1e,0x00,0x1a,0x54,0x78,0x0c,0x00,0x00,
38980x1e,0x00,0x1b,0x54,0x78,0x0c,0x00,0x00,0x1e,0x00,0x1c,0x54,0x78,0x0c,0x00,0x00,
38990x1e,0x00,0x1d,0x56,0x78,0x0c,0x00,0x00,0x1e,0x00,0x1e,0x56,0x78,0x0c,0x00,0x00,
39000x1e,0x00,0x1f,0x56,0x78,0x0c,0x00,0x00,0x1e,0x00,0x20,0x56,0x78,0x0c,0x00,0x00,
39010x1e,0x00,0x21,0x58,0x78,0x0c,0x00,0x00,0x1e,0x00,0x22,0x58,0x78,0x0c,0x00,0x00,
39020x1e,0x00,0x23,0x58,0x78,0x0c,0x00,0x00,0x1e,0x00,0x24,0x58,0x78,0x0c,0x00,0x00,
39030x1e,0x00,0x25,0x5a,0x78,0x0c,0x00,0x00,0x1e,0x00,0x26,0x5a,0x78,0x0c,0x00,0x00,
39040x1e,0x00,0x27,0x5a,0x78,0x0c,0x00,0x00,0x1e,0x00,0x28,0x5c,0x78,0x0c,0x00,0x00,
39050x1e,0x00,0x29,0x5c,0x78,0x0c,0x00,0x00,0x1e,0x00,0x2a,0x5e,0x78,0x0c,0x00,0x00,
39060x1e,0x00,0x2b,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x2c,0x5e,0x78,0x0c,0x00,0x00,
39070x1e,0x00,0x2d,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x2e,0x5e,0x78,0x0c,0x00,0x00,
39080x1e,0x00,0x2f,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x30,0x5e,0x78,0x0c,0x00,0x00,
39090x1e,0x00,0x31,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x32,0x5e,0x78,0x0c,0x00,0x00,
39100x1e,0x00,0x33,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x34,0x5e,0x78,0x0c,0x00,0x00,
39110x1e,0x00,0x35,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x36,0x5e,0x78,0x0c,0x00,0x00,
39120x1e,0x00,0x37,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x38,0x5e,0x78,0x0c,0x00,0x00,
39130x1e,0x00,0x39,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x3a,0x5e,0x78,0x0c,0x00,0x00,
39140x1e,0x00,0x3b,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x3c,0x5e,0x78,0x0c,0x00,0x00,
39150x1e,0x00,0x3d,0x5e,0x78,0x0c,0x00,0x00,0x1e,0x00,0x3e,0x5e,0x78,0x0c,0x00,0x00,
39160x1e,0x00,0x3f,0x5e,0xff,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x00,0x08,0x00,0x00,
39170x00,0x00,0x04,0x03,0x04,0x08,0x00,0x00,0x03,0x00,0x00,0x00,0x08,0x08,0x00,0x00,
39180x00,0xfc,0x00,0x00,0x0c,0x08,0x00,0x00,0x0a,0x00,0x00,0x04,0x10,0x08,0x00,0x00,
39190xff,0x10,0x10,0x80,0x14,0x08,0x00,0x00,0x10,0x3d,0x0c,0x02,0x18,0x08,0x00,0x00,
39200xc5,0x03,0x00,0x00,0x1c,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x00,
39210x04,0x00,0x00,0x00,0x24,0x08,0x00,0x00,0x00,0x02,0x69,0x00,0x28,0x08,0x00,0x00,
39220x04,0x00,0x00,0x00,0x2c,0x08,0x00,0x00,0x00,0x02,0x69,0x00,0x30,0x08,0x00,0x00,
39230x04,0x00,0x00,0x00,0x34,0x08,0x00,0x00,0x00,0x02,0x69,0x00,0x38,0x08,0x00,0x00,
39240x04,0x00,0x00,0x00,0x3c,0x08,0x00,0x00,0x00,0x02,0x69,0x00,0x40,0x08,0x00,0x00,
39250x00,0x00,0x00,0x00,0x44,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x08,0x00,0x00,
39260x00,0x00,0x00,0x00,0x4c,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x08,0x00,0x00,
39270x00,0x00,0x00,0x00,0x54,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x58,0x08,0x00,0x00,
39280x65,0xa9,0x65,0xa9,0x5c,0x08,0x00,0x00,0x65,0xa9,0x65,0xa9,0x60,0x08,0x00,0x00,
39290x30,0x01,0x7f,0x0f,0x64,0x08,0x00,0x00,0x30,0x01,0x7f,0x0f,0x68,0x08,0x00,0x00,
39300x30,0x01,0x7f,0x0f,0x6c,0x08,0x00,0x00,0x30,0x01,0x7f,0x0f,0x70,0x08,0x00,0x00,
39310x00,0x03,0x00,0x03,0x74,0x08,0x00,0x00,0x00,0x03,0x00,0x03,0x78,0x08,0x00,0x00,
39320x00,0x00,0x00,0x00,0x7c,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x08,0x00,0x00,
39330x00,0x00,0x00,0x00,0x94,0x08,0x00,0x00,0xfe,0xff,0xff,0xff,0x98,0x08,0x00,0x00,
39340x10,0x20,0x30,0x40,0x9c,0x08,0x00,0x00,0x50,0x60,0x70,0x00,0xb0,0x08,0x00,0x00,
39350x00,0x00,0x00,0x00,0xe0,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x08,0x00,0x00,
39360x00,0x00,0x00,0x00,0x00,0x0e,0x00,0x00,0x03,0x03,0x03,0x03,0x04,0x0e,0x00,0x00,
39370x03,0x03,0x03,0x03,0x08,0x0e,0x00,0x00,0x03,0x03,0x00,0x00,0x0c,0x0e,0x00,0x00,
39380x00,0x00,0x00,0x00,0x10,0x0e,0x00,0x00,0x03,0x03,0x03,0x03,0x14,0x0e,0x00,0x00,
39390x03,0x03,0x03,0x03,0x18,0x0e,0x00,0x00,0x03,0x03,0x03,0x03,0x1c,0x0e,0x00,0x00,
39400x03,0x03,0x03,0x03,0x00,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x09,0x00,0x00,
39410x23,0x00,0x00,0x00,0x08,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x09,0x00,0x00,
39420x33,0x13,0x32,0x03,0x08,0x0a,0x00,0x00,0x00,0x86,0x88,0x8f,0x2c,0x0a,0x00,0x00,
39430x00,0x00,0x92,0x00,0x00,0x0c,0x00,0x00,0x80,0x00,0x00,0x00,0x04,0x0c,0x00,0x00,
39440x33,0x54,0x00,0x00,0x08,0x0c,0x00,0x00,0xe4,0x00,0x00,0x00,0x0c,0x0c,0x00,0x00,
39450x6c,0x6c,0x6c,0x6c,0x10,0x0c,0x00,0x00,0x00,0x00,0x00,0x08,0x14,0x0c,0x00,0x00,
39460x00,0x01,0x00,0x40,0x18,0x0c,0x00,0x00,0x00,0x00,0x00,0x08,0x1c,0x0c,0x00,0x00,
39470x00,0x01,0x00,0x40,0x20,0x0c,0x00,0x00,0x00,0x00,0x00,0x08,0x24,0x0c,0x00,0x00,
39480x00,0x01,0x00,0x40,0x28,0x0c,0x00,0x00,0x00,0x00,0x00,0x08,0x2c,0x0c,0x00,0x00,
39490x00,0x01,0x00,0x40,0x30,0x0c,0x00,0x00,0x44,0x6a,0xe9,0x8d,0x34,0x0c,0x00,0x00,
39500xcd,0x52,0x96,0x46,0x38,0x0c,0x00,0x00,0x90,0x5a,0x01,0x48,0x3c,0x0c,0x00,0x00,
39510x64,0x97,0x97,0x1a,0x40,0x0c,0x00,0x00,0x3f,0x42,0x7c,0x1f,0x44,0x0c,0x00,0x00,
39520xb7,0x00,0x01,0x00,0x48,0x0c,0x00,0x00,0x00,0x00,0x02,0xec,0x4c,0x0c,0x00,0x00,
39530x03,0x03,0xfc,0x00,0x50,0x0c,0x00,0x00,0x1c,0x34,0x54,0x69,0x54,0x0c,0x00,0x00,
39540x94,0x00,0x3c,0x43,0x58,0x0c,0x00,0x00,0x1c,0x34,0x54,0x69,0x5c,0x0c,0x00,0x00,
39550x94,0x00,0x3c,0x43,0x60,0x0c,0x00,0x00,0x1c,0x34,0x54,0x69,0x64,0x0c,0x00,0x00,
39560x94,0x00,0x3c,0x43,0x68,0x0c,0x00,0x00,0x1c,0x34,0x54,0x69,0x6c,0x0c,0x00,0x00,
39570x94,0x00,0x3c,0x43,0x70,0x0c,0x00,0x00,0x0d,0x00,0x5a,0x2c,0x74,0x0c,0x00,0x00,
39580x1b,0x15,0x86,0x01,0x78,0x0c,0x00,0x00,0x1f,0x00,0x00,0x00,0x7c,0x0c,0x00,0x00,
39590x12,0x16,0xb9,0x00,0x80,0x0c,0x00,0x00,0x80,0x00,0x00,0x20,0x84,0x0c,0x00,0x00,
39600x00,0x00,0x00,0x00,0x88,0x0c,0x00,0x00,0x80,0x00,0x00,0x20,0x8c,0x0c,0x00,0x00,
39610x00,0x00,0x20,0x08,0x90,0x0c,0x00,0x00,0x00,0x01,0x00,0x40,0x94,0x0c,0x00,0x00,
39620x00,0x00,0x00,0x00,0x98,0x0c,0x00,0x00,0x00,0x01,0x00,0x40,0x9c,0x0c,0x00,0x00,
39630x00,0x00,0x00,0x00,0xa0,0x0c,0x00,0x00,0x92,0x24,0x49,0x00,0xa4,0x0c,0x00,0x00,
39640x00,0x00,0x00,0x00,0xa8,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xac,0x0c,0x00,0x00,
39650x00,0x00,0x00,0x00,0xb0,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xb4,0x0c,0x00,0x00,
39660x00,0x00,0x00,0x00,0xb8,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xbc,0x0c,0x00,0x00,
39670x92,0x24,0x49,0x00,0xc0,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xc4,0x0c,0x00,0x00,
39680x00,0x00,0x00,0x00,0xc8,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xcc,0x0c,0x00,0x00,
39690x00,0x00,0x00,0x00,0xd0,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0xd4,0x0c,0x00,0x00,
39700x00,0x00,0x00,0x00,0xd8,0x0c,0x00,0x00,0x27,0x24,0xb2,0x64,0xdc,0x0c,0x00,0x00,
39710x32,0x69,0x76,0x00,0xe0,0x0c,0x00,0x00,0x22,0x22,0x22,0x00,0xe4,0x0c,0x00,0x00,
39720x00,0x00,0x00,0x00,0xe8,0x0c,0x00,0x00,0x02,0x43,0x64,0x07,0x00,0x0d,0x00,0x00,
39730x80,0x07,0x00,0x00,0x04,0x0d,0x00,0x00,0x03,0x04,0x00,0x00,0x08,0x0d,0x00,0x00,
39740x7f,0x90,0x00,0x00,0x0c,0x0d,0x00,0x00,0x01,0x00,0x00,0x00,0x10,0x0d,0x00,0x00,
39750x99,0x99,0x69,0xa0,0x14,0x0d,0x00,0x00,0x67,0x3c,0x99,0x99,0x18,0x0d,0x00,0x00,
39760x6b,0x5b,0x8f,0x6a,0x1c,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x0d,0x00,0x00,
39770x00,0x00,0x00,0x00,0x24,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x0d,0x00,0x00,
39780x00,0x00,0x00,0x00,0x2c,0x0d,0x00,0x00,0x75,0x19,0x97,0xcc,0x30,0x0d,0x00,0x00,
39790x00,0x00,0x00,0x00,0x34,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x0d,0x00,0x00,
39800x00,0x00,0x00,0x00,0x3c,0x0d,0x00,0x00,0x93,0x72,0x02,0x00,0x40,0x0d,0x00,0x00,
39810x00,0x00,0x00,0x00,0x44,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x0d,0x00,0x00,
39820x00,0x00,0x00,0x00,0x50,0x0d,0x00,0x00,0x0a,0x14,0x37,0x64,0x54,0x0d,0x00,0x00,
39830x02,0xbd,0x4d,0x02,0x58,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x5c,0x0d,0x00,0x00,
39840x64,0x20,0x03,0x30,0x60,0x0d,0x00,0x00,0x68,0xde,0x53,0x46,0x64,0x0d,0x00,0x00,
39850x3c,0x8a,0x51,0x00,0x68,0x0d,0x00,0x00,0x06,0x01,0x00,0x00,0xff,0x00,0x00,0x00,
39860xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,
39870x44,0x05,0x01,0x80,0x10,0x00,0x00,0x00,0x74,0x05,0x01,0x80,0x10,0x00,0x00,0x00,
39880xe0,0x2e,0x00,0x80,0x10,0x00,0x00,0x00,0xec,0x2e,0x00,0x80,0x10,0x00,0x00,0x00,
39890xa0,0x08,0x01,0x80,0x08,0x00,0x00,0x00,0x38,0x06,0x01,0x80,0x00,0xb7,0x00,0x00,
39900x01,0xe0,0x0e,0x00,0x02,0x4d,0x04,0x00,0x03,0x41,0x04,0x00,0x04,0xc3,0x08,0x00,
39910x05,0x72,0x0c,0x00,0x06,0xe6,0x00,0x00,0x07,0x2a,0x08,0x00,0x08,0x3f,0x00,0x00,
39920x09,0x35,0x03,0x00,0x0a,0xd4,0x09,0x00,0x0b,0xbb,0x07,0x00,0x0c,0x50,0x08,0x00,
39930x0d,0xdf,0x0c,0x00,0x0e,0x2b,0x00,0x00,0x0f,0x14,0x01,0x00,0x00,0xb7,0x01,0x00,
39940x01,0x01,0x00,0x00,0x02,0x00,0x04,0x00,0x01,0x02,0x00,0x00,0x02,0x01,0x04,0x00,
39950x01,0x03,0x00,0x00,0x02,0x02,0x04,0x00,0x01,0x04,0x00,0x00,0x02,0x03,0x04,0x00,
39960x01,0x05,0x00,0x00,0x02,0x04,0x04,0x00,0x01,0x06,0x00,0x00,0x02,0x05,0x04,0x00,
39970x01,0x07,0x00,0x00,0x02,0x08,0x04,0x00,0x01,0x08,0x00,0x00,0x02,0x09,0x04,0x00,
39980x01,0x09,0x00,0x00,0x02,0x0a,0x04,0x00,0x01,0x0a,0x00,0x00,0x02,0x0b,0x04,0x00,
39990x01,0x0b,0x00,0x00,0x02,0x02,0x05,0x00,0x01,0x0c,0x00,0x00,0x02,0x03,0x05,0x00,
40000x01,0x0d,0x00,0x00,0x02,0x04,0x05,0x00,0x01,0x0e,0x00,0x00,0x02,0x05,0x05,0x00,
40010x01,0x0f,0x00,0x00,0x02,0x40,0x05,0x00,0x01,0x10,0x00,0x00,0x02,0x41,0x05,0x00,
40020x01,0x11,0x00,0x00,0x02,0x42,0x05,0x00,0x01,0x12,0x00,0x00,0x02,0x43,0x05,0x00,
40030x01,0x13,0x00,0x00,0x02,0x44,0x05,0x00,0x01,0x14,0x00,0x00,0x02,0x45,0x05,0x00,
40040x01,0x15,0x00,0x00,0x02,0x80,0x05,0x00,0x01,0x16,0x00,0x00,0x02,0x81,0x05,0x00,
40050x01,0x17,0x00,0x00,0x02,0x82,0x05,0x00,0x01,0x18,0x00,0x00,0x02,0x83,0x05,0x00,
40060x01,0x19,0x00,0x00,0x02,0x84,0x05,0x00,0x01,0x1a,0x00,0x00,0x02,0x85,0x05,0x00,
40070x01,0x1b,0x00,0x00,0x02,0x88,0x05,0x00,0x01,0x1c,0x00,0x00,0x02,0x89,0x05,0x00,
40080x01,0x1d,0x00,0x00,0x02,0x8a,0x05,0x00,0x01,0x1e,0x00,0x00,0x02,0x8b,0x05,0x00,
40090x01,0x1f,0x00,0x00,0x02,0x43,0x06,0x00,0x01,0x20,0x00,0x00,0x02,0x44,0x06,0x00,
40100x01,0x21,0x00,0x00,0x02,0x45,0x06,0x00,0x01,0x22,0x00,0x00,0x02,0x80,0x06,0x00,
40110x01,0x23,0x00,0x00,0x02,0x81,0x06,0x00,0x01,0x24,0x00,0x00,0x02,0x82,0x06,0x00,
40120x01,0x25,0x00,0x00,0x02,0x83,0x06,0x00,0x01,0x26,0x00,0x00,0x02,0x84,0x06,0x00,
40130x01,0x27,0x00,0x00,0x02,0x85,0x06,0x00,0x01,0x28,0x00,0x00,0x02,0x88,0x06,0x00,
40140x01,0x29,0x00,0x00,0x02,0x89,0x06,0x00,0x01,0x2a,0x00,0x00,0x02,0x8a,0x06,0x00,
40150x01,0x2b,0x00,0x00,0x02,0x8b,0x06,0x00,0x01,0x2c,0x00,0x00,0x02,0x8c,0x06,0x00,
40160x01,0x2d,0x00,0x00,0x02,0x42,0x07,0x00,0x01,0x2e,0x00,0x00,0x02,0x43,0x07,0x00,
40170x01,0x2f,0x00,0x00,0x02,0x44,0x07,0x00,0x01,0x30,0x00,0x00,0x02,0x45,0x07,0x00,
40180x01,0x31,0x00,0x00,0x02,0x80,0x07,0x00,0x01,0x32,0x00,0x00,0x02,0x81,0x07,0x00,
40190x01,0x33,0x00,0x00,0x02,0x82,0x07,0x00,0x01,0x34,0x00,0x00,0x02,0x83,0x07,0x00,
40200x01,0x35,0x00,0x00,0x02,0x84,0x07,0x00,0x01,0x36,0x00,0x00,0x02,0x85,0x07,0x00,
40210x01,0x37,0x00,0x00,0x02,0x88,0x07,0x00,0x01,0x38,0x00,0x00,0x02,0x89,0x07,0x00,
40220x01,0x39,0x00,0x00,0x02,0x8a,0x07,0x00,0x01,0x3a,0x00,0x00,0x02,0x8b,0x07,0x00,
40230x01,0x3b,0x00,0x00,0x02,0x8c,0x07,0x00,0x01,0x3c,0x00,0x00,0x02,0x8d,0x07,0x00,
40240x01,0x3d,0x00,0x00,0x02,0x90,0x07,0x00,0x01,0x3e,0x00,0x00,0x02,0x91,0x07,0x00,
40250x01,0x3f,0x00,0x00,0x02,0x92,0x07,0x00,0x01,0x40,0x00,0x00,0x02,0x93,0x07,0x00,
40260x01,0x41,0x00,0x00,0x02,0x94,0x07,0x00,0x01,0x42,0x00,0x00,0x02,0x95,0x07,0x00,
40270x01,0x43,0x00,0x00,0x02,0x98,0x07,0x00,0x01,0x44,0x00,0x00,0x02,0x99,0x07,0x00,
40280x01,0x45,0x00,0x00,0x02,0x9a,0x07,0x00,0x01,0x46,0x00,0x00,0x02,0x9b,0x07,0x00,
40290x01,0x47,0x00,0x00,0x02,0x9c,0x07,0x00,0x01,0x48,0x00,0x00,0x02,0x9d,0x07,0x00,
40300x01,0x49,0x00,0x00,0x02,0xa0,0x07,0x00,0x01,0x4a,0x00,0x00,0x02,0xa1,0x07,0x00,
40310x01,0x4b,0x00,0x00,0x02,0xa2,0x07,0x00,0x01,0x4c,0x00,0x00,0x02,0xa3,0x07,0x00,
40320x01,0x4d,0x00,0x00,0x02,0xa4,0x07,0x00,0x01,0x4e,0x00,0x00,0x02,0xa5,0x07,0x00,
40330x01,0x4f,0x00,0x00,0x02,0xa8,0x07,0x00,0x01,0x50,0x00,0x00,0x02,0xa9,0x07,0x00,
40340x01,0x51,0x00,0x00,0x02,0xaa,0x03,0x00,0x01,0x52,0x00,0x00,0x02,0xab,0x03,0x00,
40350x01,0x53,0x00,0x00,0x02,0xac,0x03,0x00,0x01,0x54,0x00,0x00,0x02,0xad,0x03,0x00,
40360x01,0x55,0x00,0x00,0x02,0xb0,0x03,0x00,0x01,0x56,0x00,0x00,0x02,0xb1,0x03,0x00,
40370x01,0x57,0x00,0x00,0x02,0xb2,0x03,0x00,0x01,0x58,0x00,0x00,0x02,0xb3,0x03,0x00,
40380x01,0x59,0x00,0x00,0x02,0xb4,0x03,0x00,0x01,0x5a,0x00,0x00,0x02,0xb5,0x03,0x00,
40390x01,0x5b,0x00,0x00,0x02,0xb8,0x03,0x00,0x01,0x5c,0x00,0x00,0x02,0xb9,0x03,0x00,
40400x01,0x5d,0x00,0x00,0x02,0xba,0x03,0x00,0x01,0x5e,0x00,0x00,0x02,0xbb,0x03,0x00,
40410x01,0x5f,0x00,0x00,0x02,0xbb,0x03,0x00,0x03,0x80,0x00,0x00,0x05,0x04,0x00,0x00,
40420x00,0xb7,0x00,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,
40430x02,0x4d,0x0c,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,0x02,0x4d,0x04,0x00,
40440x00,0xbf,0x02,0x00,0xff,0xff,0xff,0x00,0xff,0xff,0xff,0x00,0x00,0xb7,0x00,0x00,
40450x01,0xe0,0x0e,0x00,0x02,0x4d,0x04,0x00,0x03,0x41,0x04,0x00,0x04,0xc3,0x08,0x00,
40460x05,0x72,0x0c,0x00,0x06,0xe6,0x00,0x00,0x07,0x2a,0x08,0x00,0x08,0x3f,0x00,0x00,
40470x09,0x35,0x03,0x00,0x0a,0xd4,0x09,0x00,0x0b,0xbb,0x07,0x00,0x0c,0x50,0x08,0x00,
40480x0d,0xdf,0x0c,0x00,0x0e,0x2b,0x00,0x00,0x0f,0x14,0x01,0x00,0x00,0xb7,0x01,0x00,
40490x01,0x01,0x00,0x00,0x02,0x00,0x04,0x00,0x01,0x02,0x00,0x00,0x02,0x01,0x04,0x00,
40500x01,0x03,0x00,0x00,0x02,0x02,0x04,0x00,0x01,0x04,0x00,0x00,0x02,0x03,0x04,0x00,
40510x01,0x05,0x00,0x00,0x02,0x04,0x04,0x00,0x01,0x06,0x00,0x00,0x02,0x05,0x04,0x00,
40520x01,0x07,0x00,0x00,0x02,0x08,0x04,0x00,0x01,0x08,0x00,0x00,0x02,0x09,0x04,0x00,
40530x01,0x09,0x00,0x00,0x02,0x0a,0x04,0x00,0x01,0x0a,0x00,0x00,0x02,0x0b,0x04,0x00,
40540x01,0x0b,0x00,0x00,0x02,0x02,0x05,0x00,0x01,0x0c,0x00,0x00,0x02,0x03,0x05,0x00,
40550x01,0x0d,0x00,0x00,0x02,0x04,0x05,0x00,0x01,0x0e,0x00,0x00,0x02,0x05,0x05,0x00,
40560x01,0x0f,0x00,0x00,0x02,0x40,0x05,0x00,0x01,0x10,0x00,0x00,0x02,0x41,0x05,0x00,
40570x01,0x11,0x00,0x00,0x02,0x42,0x05,0x00,0x01,0x12,0x00,0x00,0x02,0x43,0x05,0x00,
40580x01,0x13,0x00,0x00,0x02,0x44,0x05,0x00,0x01,0x14,0x00,0x00,0x02,0x45,0x05,0x00,
40590x01,0x15,0x00,0x00,0x02,0x80,0x05,0x00,0x01,0x16,0x00,0x00,0x02,0x81,0x05,0x00,
40600x01,0x17,0x00,0x00,0x02,0x82,0x05,0x00,0x01,0x18,0x00,0x00,0x02,0x83,0x05,0x00,
40610x01,0x19,0x00,0x00,0x02,0x84,0x05,0x00,0x01,0x1a,0x00,0x00,0x02,0x85,0x05,0x00,
40620x01,0x1b,0x00,0x00,0x02,0x88,0x05,0x00,0x01,0x1c,0x00,0x00,0x02,0x89,0x05,0x00,
40630x01,0x1d,0x00,0x00,0x02,0x8a,0x05,0x00,0x01,0x1e,0x00,0x00,0x02,0x8b,0x05,0x00,
40640x01,0x1f,0x00,0x00,0x02,0x43,0x06,0x00,0x01,0x20,0x00,0x00,0x02,0x44,0x06,0x00,
40650x01,0x21,0x00,0x00,0x02,0x45,0x06,0x00,0x01,0x22,0x00,0x00,0x02,0x80,0x06,0x00,
40660x01,0x23,0x00,0x00,0x02,0x81,0x06,0x00,0x01,0x24,0x00,0x00,0x02,0x82,0x06,0x00,
40670x01,0x25,0x00,0x00,0x02,0x83,0x06,0x00,0x01,0x26,0x00,0x00,0x02,0x84,0x06,0x00,
40680x01,0x27,0x00,0x00,0x02,0x85,0x06,0x00,0x01,0x28,0x00,0x00,0x02,0x88,0x06,0x00,
40690x01,0x29,0x00,0x00,0x02,0x89,0x06,0x00,0x01,0x2a,0x00,0x00,0x02,0x8a,0x06,0x00,
40700x01,0x2b,0x00,0x00,0x02,0x8b,0x06,0x00,0x01,0x2c,0x00,0x00,0x02,0x8c,0x06,0x00,
40710x01,0x2d,0x00,0x00,0x02,0x42,0x07,0x00,0x01,0x2e,0x00,0x00,0x02,0x43,0x07,0x00,
40720x01,0x2f,0x00,0x00,0x02,0x44,0x07,0x00,0x01,0x30,0x00,0x00,0x02,0x45,0x07,0x00,
40730x01,0x31,0x00,0x00,0x02,0x80,0x07,0x00,0x01,0x32,0x00,0x00,0x02,0x81,0x07,0x00,
40740x01,0x33,0x00,0x00,0x02,0x82,0x07,0x00,0x01,0x34,0x00,0x00,0x02,0x83,0x07,0x00,
40750x01,0x35,0x00,0x00,0x02,0x84,0x07,0x00,0x01,0x36,0x00,0x00,0x02,0x85,0x07,0x00,
40760x01,0x37,0x00,0x00,0x02,0x88,0x07,0x00,0x01,0x38,0x00,0x00,0x02,0x89,0x07,0x00,
40770x01,0x39,0x00,0x00,0x02,0x8a,0x07,0x00,0x01,0x3a,0x00,0x00,0x02,0x8b,0x07,0x00,
40780x01,0x3b,0x00,0x00,0x02,0x8c,0x07,0x00,0x01,0x3c,0x00,0x00,0x02,0x8d,0x07,0x00,
40790x01,0x3d,0x00,0x00,0x02,0x90,0x07,0x00,0x01,0x3e,0x00,0x00,0x02,0x91,0x07,0x00,
40800x01,0x3f,0x00,0x00,0x02,0x92,0x07,0x00,0x01,0x40,0x00,0x00,0x02,0x93,0x07,0x00,
40810x01,0x41,0x00,0x00,0x02,0x94,0x07,0x00,0x01,0x42,0x00,0x00,0x02,0x95,0x07,0x00,
40820x01,0x43,0x00,0x00,0x02,0x98,0x07,0x00,0x01,0x44,0x00,0x00,0x02,0x99,0x07,0x00,
40830x01,0x45,0x00,0x00,0x02,0x9a,0x07,0x00,0x01,0x46,0x00,0x00,0x02,0x9b,0x07,0x00,
40840x01,0x47,0x00,0x00,0x02,0x9c,0x07,0x00,0x01,0x48,0x00,0x00,0x02,0x9d,0x07,0x00,
40850x01,0x49,0x00,0x00,0x02,0xa0,0x07,0x00,0x01,0x4a,0x00,0x00,0x02,0xa1,0x07,0x00,
40860x01,0x4b,0x00,0x00,0x02,0xa2,0x07,0x00,0x01,0x4c,0x00,0x00,0x02,0xa3,0x07,0x00,
40870x01,0x4d,0x00,0x00,0x02,0xa4,0x07,0x00,0x01,0x4e,0x00,0x00,0x02,0xa5,0x07,0x00,
40880x01,0x4f,0x00,0x00,0x02,0xa8,0x07,0x00,0x01,0x50,0x00,0x00,0x02,0xa9,0x07,0x00,
40890x01,0x51,0x00,0x00,0x02,0xaa,0x03,0x00,0x01,0x52,0x00,0x00,0x02,0xab,0x03,0x00,
40900x01,0x53,0x00,0x00,0x02,0xac,0x03,0x00,0x01,0x54,0x00,0x00,0x02,0xad,0x03,0x00,
40910x01,0x55,0x00,0x00,0x02,0xb0,0x03,0x00,0x01,0x56,0x00,0x00,0x02,0xb1,0x03,0x00,
40920x01,0x57,0x00,0x00,0x02,0xb2,0x03,0x00,0x01,0x58,0x00,0x00,0x02,0xb3,0x03,0x00,
40930x01,0x59,0x00,0x00,0x02,0xb4,0x03,0x00,0x01,0x5a,0x00,0x00,0x02,0xb5,0x03,0x00,
40940x01,0x5b,0x00,0x00,0x02,0xb8,0x03,0x00,0x01,0x5c,0x00,0x00,0x02,0xb9,0x03,0x00,
40950x01,0x5d,0x00,0x00,0x02,0xba,0x03,0x00,0x01,0x5e,0x00,0x00,0x02,0xbb,0x03,0x00,
40960x01,0x5f,0x00,0x00,0x02,0xbb,0x03,0x00,0x03,0x80,0x00,0x00,0x05,0x04,0x00,0x00,
40970x00,0xb7,0x00,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,
40980x02,0x4d,0x0c,0x00,0xfe,0x00,0x00,0x00,0xfe,0x00,0x00,0x00,0x02,0x4d,0x04,0x00,
40990x00,0xbf,0x02,0x00,0xff,0xff,0xff,0x00,0xff,0xff,0xff,0x00,0x0a,0x00,0x00,0x00,
41000x4f,0x6e,0x41,0x73,0x73,0x6f,0x63,0x52,0x65,0x71,0x00,0x00,0x4f,0x6e,0x41,0x73,
41010x73,0x6f,0x63,0x52,0x73,0x70,0x00,0x00,0x4f,0x6e,0x52,0x65,0x41,0x73,0x73,0x6f,
41020x63,0x52,0x65,0x71,0x00,0x00,0x00,0x00,0x4f,0x6e,0x52,0x65,0x41,0x73,0x73,0x6f,
41030x63,0x52,0x73,0x70,0x00,0x00,0x00,0x00,0x4f,0x6e,0x50,0x72,0x6f,0x62,0x65,0x52,
41040x65,0x71,0x00,0x00,0x4f,0x6e,0x50,0x72,0x6f,0x62,0x65,0x52,0x73,0x70,0x00,0x00,
41050x44,0x6f,0x52,0x65,0x73,0x65,0x72,0x76,0x65,0x64,0x00,0x00,0x44,0x6f,0x52,0x65,
41060x73,0x65,0x72,0x76,0x65,0x64,0x00,0x00,0x4f,0x6e,0x42,0x65,0x61,0x63,0x6f,0x6e,
41070x00,0x00,0x00,0x00,0x4f,0x6e,0x41,0x54,0x49,0x4d,0x00,0x00,0x4f,0x6e,0x44,0x69,
41080x73,0x61,0x73,0x73,0x6f,0x63,0x00,0x00,0x4f,0x6e,0x41,0x75,0x74,0x68,0x00,0x00,
41090x4f,0x6e,0x44,0x65,0x41,0x75,0x74,0x68,0x00,0x00,0x00,0x00,0x4f,0x6e,0x41,0x63,
41100x74,0x69,0x6f,0x6e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0x8b,0x01,0x80,
41110x28,0x14,0x01,0x80,0x10,0x00,0x00,0x00,0x94,0x8b,0x01,0x80,0x30,0x14,0x01,0x80,
41120x20,0x00,0x00,0x00,0xa0,0x8b,0x01,0x80,0x28,0x14,0x01,0x80,0x30,0x00,0x00,0x00,
41130xb0,0x8b,0x01,0x80,0x30,0x14,0x01,0x80,0x40,0x00,0x00,0x00,0xc0,0x8b,0x01,0x80,
41140x38,0x14,0x01,0x80,0x50,0x00,0x00,0x00,0xcc,0x8b,0x01,0x80,0x40,0x14,0x01,0x80,
41150x00,0x00,0x00,0x00,0xd8,0x8b,0x01,0x80,0xa8,0x14,0x01,0x80,0x00,0x00,0x00,0x00,
41160xe4,0x8b,0x01,0x80,0xa8,0x14,0x01,0x80,0x80,0x00,0x00,0x00,0xf0,0x8b,0x01,0x80,
41170x48,0x14,0x01,0x80,0x90,0x00,0x00,0x00,0xfc,0x8b,0x01,0x80,0x50,0x14,0x01,0x80,
41180xa0,0x00,0x00,0x00,0x04,0x8c,0x01,0x80,0x58,0x14,0x01,0x80,0xb0,0x00,0x00,0x00,
41190x10,0x8c,0x01,0x80,0x90,0x14,0x01,0x80,0xc0,0x00,0x00,0x00,0x18,0x8c,0x01,0x80,
41200x98,0x14,0x01,0x80,0xd0,0x00,0x00,0x00,0x24,0x8c,0x01,0x80,0xa0,0x14,0x01,0x80,
41210x00,0x00,0x00,0x00,0xdc,0x8c,0x01,0x80,0xdc,0x8c,0x01,0x80,0x31,0x10,0x10,0x00,
41220x00,0x30,0x00,0x00,0x31,0x20,0x10,0x00,0x00,0x30,0x00,0x00,0x31,0x28,0x10,0x00,
41230x00,0x30,0x00,0x00,0x31,0x2c,0x10,0x10,0x00,0x30,0x00,0x00,0x31,0x2f,0x10,0x10,
41240x00,0x30,0x00,0x00,0x31,0x30,0x18,0x00,0x00,0x30,0x00,0x00,0x31,0x30,0x20,0x10,
41250x00,0x30,0x00,0x00,0x22,0x20,0x18,0x08,0x00,0x20,0x00,0x00,0x22,0x21,0x14,0x08,
41260x00,0x20,0x00,0x00,0x22,0x21,0x1c,0x08,0x00,0x20,0x00,0x00,0x22,0x21,0x20,0x08,
41270x00,0x20,0x00,0x00,0x22,0x21,0x20,0x10,0x00,0x20,0x00,0x00,0x22,0x21,0x20,0x18,
41280x00,0x20,0x00,0x00,0x1a,0x19,0x18,0x10,0x00,0x18,0x00,0x00,0x12,0x11,0x10,0x08,
41290x00,0x10,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x08,0x00,0x00,0x0a,0x09,0x08,0x02,
41300x00,0x08,0x00,0x00,0x0a,0x09,0x08,0x04,0x00,0x08,0x00,0x00,0x0a,0x09,0x08,0x06,
41310x00,0x08,0x00,0x00,0x08,0x07,0x06,0x04,0x00,0x06,0x00,0x00,0x06,0x05,0x04,0x02,
41320x00,0x04,0x00,0x00,0x06,0x05,0x04,0x03,0x00,0x04,0x00,0x00,0x05,0x04,0x03,0x02,
41330x00,0x03,0x00,0x00,0x09,0x08,0x07,0x06,0x07,0x06,0x06,0x05,0x05,0x04,0x04,0x03,
41340x06,0x05,0x05,0x04,0x04,0x03,0x03,0x03,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x02,
41350x00,0x09,0x08,0x07,0x06,0x07,0x06,0x06,0x05,0x05,0x04,0x04,0x03,0x05,0x04,0x04,
41360x03,0x03,0x02,0x02,0x02,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x00,0x00,0x00,
41370x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x08,0x08,0x08,0x08,
41380x20,0x20,0x20,0x20,0x08,0x08,0x08,0x08,0x08,0x20,0x20,0x20,0x30,0x08,0x08,0x08,
41390x08,0x18,0x18,0x18,0x18,0x18,0x20,0x30,0x30,0x10,0x20,0x20,0x20,0x20,0x20,0x30,
41400x30,0x08,0x10,0x20,0x30,0x30,0x30,0x30,0x30,0x30,0x00,0x00,0x08,0x08,0x08,0x08,
41410x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x08,0x08,0x08,0x08,0x08,0x20,0x20,0x20,
41420x08,0x08,0x08,0x08,0x08,0x20,0x20,0x20,0x20,0x08,0x08,0x08,0x08,0x18,0x18,0x18,
41430x18,0x18,0x20,0x30,0x30,0x10,0x20,0x20,0x20,0x20,0x20,0x30,0x30,0x08,0x10,0x20,
41440x30,0x30,0x30,0x30,0x30,0x30,0x00,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,
41450x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x00,
41460x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,
41470x0a,0x09,0x08,0x00,0x00,0x12,0x11,0x10,0x08,0x00,0x12,0x11,0x10,0x08,0x00,0x22,
41480x21,0x20,0x18,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,
41490x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x22,0x21,0x20,0x18,0x00,0x22,0x21,0x20,
41500x18,0x00,0x22,0x21,0x1c,0x08,0x00,0x22,0x20,0x18,0x08,0x00,0x0a,0x09,0x08,0x02,
41510x00,0x0a,0x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x02,0x00,
41520x0a,0x09,0x08,0x00,0x00,0x22,0x21,0x20,0x10,0x00,0x22,0x21,0x20,0x08,0x00,0x22,
41530x21,0x1c,0x08,0x00,0x31,0x30,0x18,0x00,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,
41540x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x1a,0x19,0x18,
41550x10,0x00,0x1a,0x19,0x18,0x10,0x00,0x1a,0x19,0x18,0x10,0x00,0x1a,0x19,0x18,0x10,
41560x00,0x1a,0x19,0x18,0x10,0x00,0x22,0x21,0x20,0x08,0x00,0x31,0x2c,0x10,0x10,0x00,
41570x31,0x28,0x10,0x00,0x00,0x12,0x11,0x10,0x08,0x00,0x22,0x21,0x20,0x18,0x00,0x22,
41580x21,0x20,0x18,0x00,0x22,0x21,0x20,0x08,0x00,0x22,0x21,0x14,0x08,0x00,0x22,0x20,
41590x18,0x08,0x00,0x31,0x30,0x20,0x10,0x00,0x31,0x2c,0x10,0x10,0x00,0x0a,0x09,0x08,
41600x00,0x00,0x12,0x11,0x10,0x08,0x00,0x22,0x21,0x20,0x18,0x00,0x22,0x21,0x20,0x18,
41610x00,0x31,0x30,0x20,0x10,0x00,0x31,0x2f,0x10,0x10,0x00,0x31,0x2f,0x10,0x10,0x00,
41620x31,0x10,0x10,0x00,0x00,0x31,0x2c,0x10,0x10,0x00,0x00,0x00,0x0a,0x09,0x08,0x04,
41630x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,
41640x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,
41650x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,0x00,0x12,0x11,0x10,0x08,0x00,0x12,0x11,
41660x10,0x08,0x00,0x22,0x21,0x20,0x18,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,
41670x04,0x00,0x0a,0x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x00,0x00,0x0a,0x09,0x08,0x00,
41680x00,0x22,0x21,0x20,0x18,0x00,0x22,0x21,0x1c,0x08,0x00,0x22,0x21,0x14,0x08,0x00,
41690x0a,0x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x02,0x00,0x0a,
41700x09,0x08,0x02,0x00,0x0a,0x09,0x08,0x00,0x00,0x22,0x21,0x20,0x10,0x00,0x22,0x21,
41710x20,0x08,0x00,0x22,0x21,0x14,0x08,0x00,0x22,0x21,0x14,0x08,0x00,0x0a,0x09,0x08,
41720x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,0x00,0x0a,0x09,0x08,0x04,
41730x00,0x1a,0x19,0x18,0x10,0x00,0x1a,0x19,0x18,0x10,0x00,0x1a,0x19,0x18,0x10,0x00,
41740x1a,0x19,0x18,0x10,0x00,0x1a,0x19,0x18,0x10,0x00,0x22,0x21,0x20,0x08,0x00,0x31,
41750x2c,0x10,0x10,0x00,0x31,0x28,0x10,0x00,0x00,0x12,0x11,0x10,0x08,0x00,0x22,0x21,
41760x20,0x18,0x00,0x22,0x21,0x20,0x18,0x00,0x22,0x21,0x20,0x08,0x00,0x22,0x21,0x14,
41770x08,0x00,0x22,0x20,0x18,0x08,0x00,0x31,0x30,0x20,0x10,0x00,0x31,0x2c,0x10,0x10,
41780x00,0x0a,0x09,0x08,0x00,0x00,0x12,0x11,0x10,0x08,0x00,0x22,0x21,0x20,0x18,0x00,
41790x22,0x21,0x20,0x18,0x00,0x31,0x30,0x20,0x10,0x00,0x31,0x2f,0x10,0x10,0x00,0x31,
41800x2f,0x10,0x10,0x00,0x31,0x10,0x10,0x00,0x00,0x31,0x2c,0x10,0x10,0x00,0x00,0x00,
41810x01,0x02,0x04,0x08,0x02,0x04,0x08,0x0c,0x10,0x18,0x20,0x30,0x02,0x04,0x08,0x0c,
41820x10,0x18,0x20,0x30,0x06,0x0c,0x10,0x18,0x24,0x30,0x3c,0x48,0x48,0x00,0x00,0x00,
41830x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x27,0x2c,0x19,0x1b,0x1e,0x20,
41840x23,0x29,0x2a,0x2b,0x00,0x00,0x00,0x00,0x25,0x29,0x2b,0x2e,0x2e,0x00,0x00,0x00,
41850x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,
41860x18,0x00,0x00,0x00,0x24,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,
41870x60,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,0xd8,0x00,0x00,0x00,
41880x50,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0xc8,0x00,0x00,0x00,
41890x40,0x01,0x00,0x00,0x90,0x01,0x00,0x00,0xe0,0x01,0x00,0x00,0x30,0x02,0x00,0x00,
41900x2c,0x01,0x00,0x00,0x40,0x01,0x00,0x00,0xe0,0x01,0x00,0x00,0xd0,0x02,0x00,0x00,
41910x80,0x0c,0x00,0x00,0x80,0x0c,0x00,0x00,0x80,0x0c,0x00,0x00,0xa0,0x0f,0x00,0x00,
41920xa0,0x0f,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
41930x08,0x00,0x00,0x00,0x0c,0x00,0x00,0x00,0x12,0x00,0x00,0x00,0x18,0x00,0x00,0x00,
41940x24,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60,0x00,0x00,0x00,
41950x6c,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x3c,0x00,0x00,0x00,0x50,0x00,0x00,0x00,
41960x64,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0xc8,0x00,0x00,0x00,0xf0,0x00,0x00,0x00,
41970x18,0x01,0x00,0x00,0x64,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0xf0,0x00,0x00,0x00,
41980x68,0x01,0x00,0x00,0x40,0x06,0x00,0x00,0x40,0x06,0x00,0x00,0x40,0x06,0x00,0x00,
41990xd0,0x07,0x00,0x00,0xd0,0x07,0x00,0x00,0x2c,0x05,0x00,0x80,0x20,0x05,0x00,0x80,
42000x14,0x05,0x00,0x80,0x08,0x05,0x00,0x80,0xfc,0x04,0x00,0x80,0xf0,0x04,0x00,0x80,
42010xe4,0x04,0x00,0x80,0xd8,0x04,0x00,0x80,0xcc,0x04,0x00,0x80,0xc0,0x04,0x00,0x80,
42020x78,0x04,0x00,0x80,0x68,0x15,0x02,0x80,0xc0,0x3a,0x00,0x80,0xcc,0x3a,0x00,0x80,
42030xd8,0x3a,0x00,0x80,0xe4,0x3a,0x00,0x80,0xc0,0x3a,0x00,0x80,0xc0,0x3a,0x00,0x80,
42040xc0,0x3a,0x00,0x80,0xc0,0x3a,0x00,0x80,0xf0,0x3a,0x00,0x80,0xfc,0x3a,0x00,0x80,
42050x08,0x3b,0x00,0x80,0x14,0x3b,0x00,0x80,0x68,0x15,0x02,0x80,0xfe,0x01,0x80,0x7f,
42060xe2,0x01,0x80,0x78,0xc7,0x01,0xc0,0x71,0xae,0x01,0x80,0x6b,0x95,0x01,0x40,0x65,
42070x7f,0x01,0xc0,0x5f,0x69,0x01,0x40,0x5a,0x55,0x01,0x40,0x55,0x42,0x01,0x80,0x50,
42080x30,0x01,0x00,0x4c,0x1f,0x01,0xc0,0x47,0x0f,0x01,0xc0,0x43,0x00,0x01,0x00,0x40,
42090xf2,0x00,0x80,0x3c,0xe4,0x00,0x00,0x39,0xd7,0x00,0xc0,0x35,0xcb,0x00,0xc0,0x32,
42100xc0,0x00,0x00,0x30,0xb5,0x00,0x40,0x2d,0xab,0x00,0xc0,0x2a,0xa2,0x00,0x80,0x28,
42110x98,0x00,0x00,0x26,0x90,0x00,0x00,0x24,0x88,0x00,0x00,0x22,0x80,0x00,0x00,0x20,
42120x79,0x00,0x40,0x1e,0x72,0x00,0x80,0x1c,0x6c,0x00,0x00,0x1b,0x66,0x00,0x80,0x19,
42130x60,0x00,0x00,0x18,0x5b,0x00,0xc0,0x16,0x56,0x00,0x80,0x15,0x51,0x00,0x40,0x14,
42140x4c,0x00,0x00,0x13,0x48,0x00,0x00,0x12,0x44,0x00,0x00,0x11,0x40,0x00,0x00,0x10,
42150x36,0x35,0x2e,0x25,0x1c,0x12,0x09,0x04,0x33,0x32,0x2b,0x23,0x1a,0x11,0x08,0x04,
42160x30,0x2f,0x29,0x21,0x19,0x10,0x08,0x03,0x2d,0x2d,0x27,0x1f,0x18,0x0f,0x08,0x03,
42170x2b,0x2a,0x25,0x1e,0x16,0x0e,0x07,0x03,0x28,0x28,0x22,0x1c,0x15,0x0d,0x07,0x03,
42180x26,0x25,0x21,0x1b,0x14,0x0d,0x06,0x03,0x24,0x23,0x1f,0x19,0x13,0x0c,0x06,0x03,
42190x22,0x21,0x1d,0x18,0x11,0x0b,0x06,0x02,0x20,0x20,0x1b,0x16,0x11,0x08,0x05,0x02,
42200x1f,0x1e,0x1a,0x15,0x10,0x0a,0x05,0x02,0x1d,0x1c,0x18,0x14,0x0f,0x0a,0x05,0x02,
42210x1b,0x1a,0x17,0x13,0x0e,0x09,0x04,0x02,0x1a,0x19,0x16,0x12,0x0d,0x09,0x04,0x02,
42220x18,0x17,0x15,0x11,0x0c,0x08,0x04,0x02,0x17,0x16,0x13,0x10,0x0c,0x08,0x04,0x02,
42230x16,0x15,0x12,0x0f,0x0b,0x07,0x04,0x01,0x14,0x14,0x11,0x0e,0x0b,0x07,0x03,0x02,
42240x13,0x13,0x10,0x0d,0x0a,0x06,0x03,0x01,0x12,0x12,0x0f,0x0c,0x09,0x06,0x03,0x01,
42250x11,0x11,0x0f,0x0c,0x09,0x06,0x03,0x01,0x10,0x10,0x0e,0x0b,0x08,0x05,0x03,0x01,
42260x0f,0x0f,0x0d,0x0b,0x08,0x05,0x03,0x01,0x0e,0x0e,0x0c,0x0a,0x08,0x05,0x02,0x01,
42270x0d,0x0d,0x0c,0x0a,0x07,0x05,0x02,0x01,0x0d,0x0c,0x0b,0x09,0x07,0x04,0x02,0x01,
42280x0c,0x0c,0x0a,0x09,0x06,0x04,0x02,0x01,0x0b,0x0b,0x0a,0x08,0x06,0x04,0x02,0x01,
42290x0b,0x0a,0x09,0x08,0x06,0x04,0x02,0x01,0x0a,0x0a,0x09,0x07,0x05,0x03,0x02,0x01,
42300x0a,0x09,0x08,0x07,0x05,0x03,0x02,0x01,0x09,0x09,0x08,0x06,0x05,0x03,0x01,0x01,
42310x09,0x08,0x07,0x06,0x04,0x03,0x01,0x01,0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00,
42320x33,0x32,0x2b,0x19,0x00,0x00,0x00,0x00,0x30,0x2f,0x29,0x18,0x00,0x00,0x00,0x00,
42330x2d,0x2d,0x17,0x17,0x00,0x00,0x00,0x00,0x2b,0x2a,0x25,0x15,0x00,0x00,0x00,0x00,
42340x28,0x28,0x24,0x14,0x00,0x00,0x00,0x00,0x26,0x25,0x21,0x13,0x00,0x00,0x00,0x00,
42350x24,0x23,0x1f,0x12,0x00,0x00,0x00,0x00,0x22,0x21,0x1d,0x11,0x00,0x00,0x00,0x00,
42360x20,0x20,0x1b,0x10,0x00,0x00,0x00,0x00,0x1f,0x1e,0x1a,0x0f,0x00,0x00,0x00,0x00,
42370x1d,0x1c,0x18,0x0e,0x00,0x00,0x00,0x00,0x1b,0x1a,0x17,0x0e,0x00,0x00,0x00,0x00,
42380x1a,0x19,0x16,0x0d,0x00,0x00,0x00,0x00,0x18,0x17,0x15,0x0c,0x00,0x00,0x00,0x00,
42390x17,0x16,0x13,0x0b,0x00,0x00,0x00,0x00,0x16,0x15,0x12,0x0b,0x00,0x00,0x00,0x00,
42400x14,0x14,0x11,0x0a,0x00,0x00,0x00,0x00,0x13,0x13,0x10,0x0a,0x00,0x00,0x00,0x00,
42410x12,0x12,0x0f,0x09,0x00,0x00,0x00,0x00,0x11,0x11,0x0f,0x09,0x00,0x00,0x00,0x00,
42420x10,0x10,0x0e,0x08,0x00,0x00,0x00,0x00,0x0f,0x0f,0x0d,0x08,0x00,0x00,0x00,0x00,
42430x0e,0x0e,0x0c,0x07,0x00,0x00,0x00,0x00,0x0d,0x0d,0x0c,0x07,0x00,0x00,0x00,0x00,
42440x0d,0x0c,0x0b,0x06,0x00,0x00,0x00,0x00,0x0c,0x0c,0x0a,0x06,0x00,0x00,0x00,0x00,
42450x0b,0x0b,0x0a,0x06,0x00,0x00,0x00,0x00,0x0b,0x0a,0x09,0x05,0x00,0x00,0x00,0x00,
42460x0a,0x0a,0x09,0x05,0x00,0x00,0x00,0x00,0x0a,0x09,0x08,0x05,0x00,0x00,0x00,0x00,
42470x09,0x09,0x08,0x05,0x00,0x00,0x00,0x00,0x09,0x08,0x07,0x04,0x00,0x00,0x00,0x00,
42480x06,0x00,0x2a,0xb0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42490x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42500x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42510x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42520x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42530x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42540x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42550x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42560x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42570x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42580x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42590x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
42600x08,0x28,0x28,0x28,0x28,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
42610x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
42620x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
42630x04,0x04,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x41,0x41,0x41,0x41,0x41,0x41,0x01,
42640x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
42650x01,0x01,0x01,0x10,0x10,0x10,0x10,0x10,0x10,0x42,0x42,0x42,0x42,0x42,0x42,0x02,
42660x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
42670x02,0x02,0x02,0x10,0x10,0x10,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42680x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42690x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
42700x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
42710x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
42720x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,
42730x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
42740x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,
42750x02,0x02,0x02,0x02,0x02,0x02,0x02,0x00,0x19,0x77,0x00,0x00,0x00,0x00,0x00,0x00,
42760x00,0x26,0x72,0xb0,0x00,0x26,0x72,0xb0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42770x00,0x00,0x00,0x00,0x00,0x26,0x65,0x60,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x02,
42780x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0xf2,0x30,0xb8,0xff,0xff,0xff,0xff,
4279};
4280
4281u8 Rtl8192SUFwMainArray[MainArrayLength] = {
42820x0, };
4283
4284u8 Rtl8192SUFwDataArray[DataArrayLength] = {
42850x0, };
4286
4287u32 Rtl8192SUPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength] = {
42880x01c,0x07000000,
42890x800,0x00040000,
42900x804,0x00008003,
42910x808,0x0000fc00,
42920x80c,0x0000000a,
42930x810,0x10005088,
42940x814,0x020c3d10,
42950x818,0x00200185,
42960x81c,0x00000000,
42970x820,0x01000000,
42980x824,0x00390004,
42990x828,0x01000000,
43000x82c,0x00390004,
43010x830,0x00000004,
43020x834,0x00690200,
43030x838,0x00000004,
43040x83c,0x00690200,
43050x840,0x00010000,
43060x844,0x00010000,
43070x848,0x00000000,
43080x84c,0x00000000,
43090x850,0x00000000,
43100x854,0x00000000,
43110x858,0x48484848,
43120x85c,0x65a965a9,
43130x860,0x0f7f0130,
43140x864,0x0f7f0130,
43150x868,0x0f7f0130,
43160x86c,0x0f7f0130,
43170x870,0x03000700,
43180x874,0x03000300,
43190x878,0x00020002,
43200x87c,0x004f0201,
43210x880,0xa8300ac1,
43220x884,0x00000058,
43230x888,0x00000008,
43240x88c,0x00000004,
43250x890,0x00000000,
43260x894,0xfffffffe,
43270x898,0x40302010,
43280x89c,0x00706050,
43290x8b0,0x00000000,
43300x8e0,0x00000000,
43310x8e4,0x00000000,
43320xe00,0x30333333,
43330xe04,0x2a2d2e2f,
43340xe08,0x00003232,
43350xe10,0x30333333,
43360xe14,0x2a2d2e2f,
43370xe18,0x30333333,
43380xe1c,0x2a2d2e2f,
43390xe30,0x01007c00,
43400xe34,0x01004800,
43410xe38,0x1000dc1f,
43420xe3c,0x10008c1f,
43430xe40,0x021400a0,
43440xe44,0x281600a0,
43450xe48,0xf8000001,
43460xe4c,0x00002910,
43470xe50,0x01007c00,
43480xe54,0x01004800,
43490xe58,0x1000dc1f,
43500xe5c,0x10008c1f,
43510xe60,0x021400a0,
43520xe64,0x281600a0,
43530xe6c,0x00002910,
43540xe70,0x31ed92fb,
43550xe74,0x361536fb,
43560xe78,0x361536fb,
43570xe7c,0x361536fb,
43580xe80,0x361536fb,
43590xe84,0x000d92fb,
43600xe88,0x000d92fb,
43610xe8c,0x31ed92fb,
43620xed0,0x31ed92fb,
43630xed4,0x31ed92fb,
43640xed8,0x000d92fb,
43650xedc,0x000d92fb,
43660xee0,0x000d92fb,
43670xee4,0x015e5448,
43680xee8,0x21555448,
43690x900,0x00000000,
43700x904,0x00000023,
43710x908,0x00000000,
43720x90c,0x03321333,
43730xa00,0x00d047c8,
43740xa04,0x80ff0008,
43750xa08,0x8ccd8300,
43760xa0c,0x2e62120f,
43770xa10,0x9500bb78,
43780xa14,0x11144028,
43790xa18,0x00881117,
43800xa1c,0x89140f00,
43810xa20,0x1a1b0000,
43820xa24,0x090e1317,
43830xa28,0x00000204,
43840xa2c,0x10d30000,
43850xc00,0x40071d40,
43860xc04,0x00a05633,
43870xc08,0x000000e4,
43880xc0c,0x6c6c6c6c,
43890xc10,0x08800000,
43900xc14,0x40000100,
43910xc18,0x08000000,
43920xc1c,0x40000100,
43930xc20,0x08000000,
43940xc24,0x40000100,
43950xc28,0x08000000,
43960xc2c,0x40000100,
43970xc30,0x6de9ac44,
43980xc34,0x469652cf,
43990xc38,0x49795994,
44000xc3c,0x0a979764,
44010xc40,0x1f7c403f,
44020xc44,0x000100b7,
44030xc48,0xec020000,
44040xc4c,0x007f037f,
44050xc50,0x69543420,
44060xc54,0x433c0094,
44070xc58,0x69543420,
44080xc5c,0x433c0094,
44090xc60,0x69543420,
44100xc64,0x433c0094,
44110xc68,0x69543420,
44120xc6c,0x433c0094,
44130xc70,0x2c7f000d,
44140xc74,0x0186155b,
44150xc78,0x0000001f,
44160xc7c,0x00b91612,
44170xc80,0x40000100,
44180xc84,0x20f60000,
44190xc88,0x20000080,
44200xc8c,0x20200000,
44210xc90,0x40000100,
44220xc94,0x00000000,
44230xc98,0x40000100,
44240xc9c,0x00000000,
44250xca0,0x00492492,
44260xca4,0x00000000,
44270xca8,0x00000000,
44280xcac,0x00000000,
44290xcb0,0x00000000,
44300xcb4,0x00000000,
44310xcb8,0x00000000,
44320xcbc,0x28000000,
44330xcc0,0x00000000,
44340xcc4,0x00000000,
44350xcc8,0x00000000,
44360xccc,0x00000000,
44370xcd0,0x00000000,
44380xcd4,0x00000000,
44390xcd8,0x64b22427,
44400xcdc,0x00766932,
44410xce0,0x00222222,
44420xce4,0x00000000,
44430xce8,0x37644302,
44440xcec,0x2f97d40c,
44450xd00,0x00000750,
44460xd04,0x00000403,
44470xd08,0x0000907f,
44480xd0c,0x00000001,
44490xd10,0xa0633333,
44500xd14,0x33333c63,
44510xd18,0x6a8f5b6b,
44520xd1c,0x00000000,
44530xd20,0x00000000,
44540xd24,0x00000000,
44550xd28,0x00000000,
44560xd2c,0xcc979975,
44570xd30,0x00000000,
44580xd34,0x00000000,
44590xd38,0x00000000,
44600xd3c,0x00027293,
44610xd40,0x00000000,
44620xd44,0x00000000,
44630xd48,0x00000000,
44640xd50,0x6437140a,
44650xd54,0x024dbd02,
44660xd58,0x00000000,
44670xd5c,0x30032064,
44680xd60,0x4653de68,
44690xd64,0x00518a3c,
44700xd68,0x00002101,
44710xf14,0x00000003,
44720xf4c,0x00000000,
44730xf00,0x00000300,
4474};
4475
4476u32 Rtl8192SUPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
44770x0, };
4478
4479u32 Rtl8192SUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = {
44800x844,0xffffffff,0x00010000,
44810x804,0x0000000f,0x00000001,
44820x824,0x00f0000f,0x00300004,
44830x82c,0x00f0000f,0x00100002,
44840x870,0x04000000,0x00000001,
44850x864,0x00000400,0x00000000,
44860x878,0x000f000f,0x00000002,
44870xe74,0x0f000000,0x00000002,
44880xe78,0x0f000000,0x00000002,
44890xe7c,0x0f000000,0x00000002,
44900xe80,0x0f000000,0x00000002,
44910x90c,0x000000ff,0x00000011,
44920xc04,0x000000ff,0x00000011,
44930xd04,0x0000000f,0x00000001,
44940x1f4,0xffff0000,0x00007777,
44950x234,0xf8000000,0x0000000a,
4496};
4497
4498u32 Rtl8192SUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = {
44990x804,0x0000000f,0x00000003,
45000x824,0x00f0000f,0x00300004,
45010x82c,0x00f0000f,0x00300002,
45020x870,0x04000000,0x00000001,
45030x864,0x00000400,0x00000000,
45040x878,0x000f000f,0x00000002,
45050xe74,0x0f000000,0x00000002,
45060xe78,0x0f000000,0x00000002,
45070xe7c,0x0f000000,0x00000002,
45080xe80,0x0f000000,0x00000002,
45090x90c,0x000000ff,0x00000011,
45100xc04,0x000000ff,0x00000033,
45110xd04,0x0000000f,0x00000003,
45120x1f4,0xffff0000,0x00007777,
45130x234,0xf8000000,0x0000000a,
4514};
4515
4516u32 Rtl8192SUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = {
45170x804,0x0000000f,0x00000003,
45180x824,0x00f0000f,0x00300004,
45190x82c,0x00f0000f,0x00300004,
45200x870,0x04000000,0x00000001,
45210x864,0x00000400,0x00000001,
45220x878,0x000f000f,0x00020002,
45230xe74,0x0f000000,0x00000006,
45240xe78,0x0f000000,0x00000006,
45250xe7c,0x0f000000,0x00000006,
45260xe80,0x0f000000,0x00000006,
45270x90c,0x000000ff,0x00000033,
45280xc04,0x000000ff,0x00000033,
45290xd04,0x0000000f,0x00000003,
45300x1f4,0xffff0000,0x0000ffff,
45310x234,0xf8000000,0x00000013,
4532};
4533
4534u32 Rtl8192SUPHY_REG_Array_PG[PHY_REG_Array_PGLength] = {
45350xe00,0xffffffff,0x06090909,
45360xe04,0xffffffff,0x00030406,
45370xe08,0x0000ff00,0x00000000,
45380xe10,0xffffffff,0x0a0c0d0e,
45390xe14,0xffffffff,0x04070809,
45400xe18,0xffffffff,0x0a0c0d0e,
45410xe1c,0xffffffff,0x04070809,
4542};
4543
4544u32 Rtl8192SURadioA_1T_Array[RadioA_1T_ArrayLength] = {
45450x000,0x00030159,
45460x001,0x00030250,
45470x002,0x00010000,
45480x010,0x0008000f,
45490x011,0x000231fc,
45500x010,0x000c000f,
45510x011,0x0003f9f8,
45520x010,0x0002000f,
45530x011,0x00020101,
45540x014,0x0001093e,
45550x014,0x0009093e,
45560x015,0x000198f4,
45570x017,0x000f6500,
45580x01a,0x00013056,
45590x01b,0x00060000,
45600x01c,0x00000300,
45610x01e,0x00031059,
45620x021,0x00054000,
45630x022,0x0000083c,
45640x023,0x00001558,
45650x024,0x00000060,
45660x025,0x00022583,
45670x026,0x0000f200,
45680x027,0x000eacf1,
45690x028,0x0009bd54,
45700x029,0x00004582,
45710x02a,0x00000001,
45720x02b,0x00021334,
45730x02a,0x00000000,
45740x02b,0x0000000a,
45750x02a,0x00000001,
45760x02b,0x00000808,
45770x02b,0x00053333,
45780x02c,0x0000000c,
45790x02a,0x00000002,
45800x02b,0x00000808,
45810x02b,0x0005b333,
45820x02c,0x0000000d,
45830x02a,0x00000003,
45840x02b,0x00000808,
45850x02b,0x00063333,
45860x02c,0x0000000d,
45870x02a,0x00000004,
45880x02b,0x00000808,
45890x02b,0x0006b333,
45900x02c,0x0000000d,
45910x02a,0x00000005,
45920x02b,0x00000709,
45930x02b,0x00053333,
45940x02c,0x0000000d,
45950x02a,0x00000006,
45960x02b,0x00000709,
45970x02b,0x0005b333,
45980x02c,0x0000000d,
45990x02a,0x00000007,
46000x02b,0x00000709,
46010x02b,0x00063333,
46020x02c,0x0000000d,
46030x02a,0x00000008,
46040x02b,0x00000709,
46050x02b,0x0006b333,
46060x02c,0x0000000d,
46070x02a,0x00000009,
46080x02b,0x0000060a,
46090x02b,0x00053333,
46100x02c,0x0000000d,
46110x02a,0x0000000a,
46120x02b,0x0000060a,
46130x02b,0x0005b333,
46140x02c,0x0000000d,
46150x02a,0x0000000b,
46160x02b,0x0000060a,
46170x02b,0x00063333,
46180x02c,0x0000000d,
46190x02a,0x0000000c,
46200x02b,0x0000060a,
46210x02b,0x0006b333,
46220x02c,0x0000000d,
46230x02a,0x0000000d,
46240x02b,0x0000050b,
46250x02b,0x00053333,
46260x02c,0x0000000d,
46270x02a,0x0000000e,
46280x02b,0x0000050b,
46290x02b,0x00066623,
46300x02c,0x0000001a,
46310x02a,0x000e4000,
46320x030,0x00020000,
46330x031,0x000b9631,
46340x032,0x0000130d,
46350x033,0x00000187,
46360x013,0x00019e6c,
46370x013,0x00015e94,
46380x000,0x00010159,
46390x018,0x0000f401,
46400x0fe,0x00000000,
46410x01e,0x0003105b,
46420x0fe,0x00000000,
46430x000,0x00030159,
46440x010,0x0004000f,
46450x011,0x000203f9,
4646};
4647
4648u32 Rtl8192SURadioB_Array[RadioB_ArrayLength] = {
46490x000,0x00030159,
46500x001,0x00001041,
46510x002,0x00011000,
46520x005,0x00080fc0,
46530x007,0x000fc803,
46540x013,0x00017cb0,
46550x013,0x00011cc0,
46560x013,0x0000dc60,
46570x013,0x00008c60,
46580x013,0x00004450,
46590x013,0x00000020,
4660};
4661
4662u32 Rtl8192SURadioA_to1T_Array[RadioA_to1T_ArrayLength] = {
46630x000,0x00000000,
4664};
4665
4666u32 Rtl8192SURadioA_to2T_Array[RadioA_to2T_ArrayLength] = {
46670x000,0x00000000,
4668};
4669
4670u32 Rtl8192SURadioB_GM_Array[RadioB_GM_ArrayLength] = {
46710x000,0x00030159,
46720x001,0x00001041,
46730x002,0x00011000,
46740x005,0x00080fc0,
46750x007,0x000fc803,
46760x013,0x0000bef0,
46770x013,0x00007e90,
46780x013,0x00003e30,
4679};
4680
4681u32 Rtl8192SUMAC_2T_Array[MAC_2T_ArrayLength] = {
46820x020,0x00000035,
46830x048,0x0000000e,
46840x049,0x000000f0,
46850x04a,0x00000077,
46860x04b,0x00000083,
46870x0b5,0x00000021,
46880x0dc,0x000000ff,
46890x0dd,0x000000ff,
46900x0de,0x000000ff,
46910x0df,0x000000ff,
46920x116,0x00000000,
46930x117,0x00000000,
46940x118,0x00000000,
46950x119,0x00000000,
46960x11a,0x00000000,
46970x11b,0x00000000,
46980x11c,0x00000000,
46990x11d,0x00000000,
47000x160,0x0000000b,
47010x161,0x0000000b,
47020x162,0x0000000b,
47030x163,0x0000000b,
47040x164,0x0000000b,
47050x165,0x0000000b,
47060x166,0x0000000b,
47070x167,0x0000000b,
47080x168,0x0000000b,
47090x169,0x0000000b,
47100x16a,0x0000000b,
47110x16b,0x0000000b,
47120x16c,0x0000000b,
47130x16d,0x0000000b,
47140x16e,0x0000000b,
47150x16f,0x0000000b,
47160x170,0x0000000b,
47170x171,0x0000000b,
47180x172,0x0000000b,
47190x173,0x0000000b,
47200x174,0x0000000b,
47210x175,0x0000000b,
47220x176,0x0000000b,
47230x177,0x0000000b,
47240x178,0x0000000b,
47250x179,0x0000000b,
47260x17a,0x0000000b,
47270x17b,0x0000000b,
47280x17c,0x0000000b,
47290x17d,0x0000000b,
47300x17e,0x0000000b,
47310x17f,0x0000000b,
47320x236,0x0000000c,
47330x503,0x00000022,
47340x560,0x00000009,
4735};
4736
4737u32 Rtl8192SUMACPHY_Array_PG[MACPHY_Array_PGLength] = {
47380x0, };
4739
4740u32 Rtl8192SUAGCTAB_Array[AGCTAB_ArrayLength] = {
47410xc78,0x7f000001,
47420xc78,0x7f010001,
47430xc78,0x7e020001,
47440xc78,0x7d030001,
47450xc78,0x7c040001,
47460xc78,0x7b050001,
47470xc78,0x7a060001,
47480xc78,0x79070001,
47490xc78,0x78080001,
47500xc78,0x77090001,
47510xc78,0x760a0001,
47520xc78,0x750b0001,
47530xc78,0x740c0001,
47540xc78,0x730d0001,
47550xc78,0x720e0001,
47560xc78,0x710f0001,
47570xc78,0x70100001,
47580xc78,0x6f110001,
47590xc78,0x6f120001,
47600xc78,0x6e130001,
47610xc78,0x6d140001,
47620xc78,0x6d150001,
47630xc78,0x6c160001,
47640xc78,0x6b170001,
47650xc78,0x6a180001,
47660xc78,0x6a190001,
47670xc78,0x691a0001,
47680xc78,0x681b0001,
47690xc78,0x671c0001,
47700xc78,0x661d0001,
47710xc78,0x651e0001,
47720xc78,0x641f0001,
47730xc78,0x63200001,
47740xc78,0x4c210001,
47750xc78,0x4b220001,
47760xc78,0x4a230001,
47770xc78,0x49240001,
47780xc78,0x48250001,
47790xc78,0x47260001,
47800xc78,0x46270001,
47810xc78,0x45280001,
47820xc78,0x44290001,
47830xc78,0x2c2a0001,
47840xc78,0x2b2b0001,
47850xc78,0x2a2c0001,
47860xc78,0x292d0001,
47870xc78,0x282e0001,
47880xc78,0x272f0001,
47890xc78,0x26300001,
47900xc78,0x25310001,
47910xc78,0x24320001,
47920xc78,0x23330001,
47930xc78,0x22340001,
47940xc78,0x09350001,
47950xc78,0x08360001,
47960xc78,0x07370001,
47970xc78,0x06380001,
47980xc78,0x05390001,
47990xc78,0x043a0001,
48000xc78,0x033b0001,
48010xc78,0x023c0001,
48020xc78,0x013d0001,
48030xc78,0x003e0001,
48040xc78,0x003f0001,
48050xc78,0x7f400001,
48060xc78,0x7f410001,
48070xc78,0x7e420001,
48080xc78,0x7d430001,
48090xc78,0x7c440001,
48100xc78,0x7b450001,
48110xc78,0x7a460001,
48120xc78,0x79470001,
48130xc78,0x78480001,
48140xc78,0x77490001,
48150xc78,0x764a0001,
48160xc78,0x754b0001,
48170xc78,0x744c0001,
48180xc78,0x734d0001,
48190xc78,0x724e0001,
48200xc78,0x714f0001,
48210xc78,0x70500001,
48220xc78,0x6f510001,
48230xc78,0x6f520001,
48240xc78,0x6e530001,
48250xc78,0x6d540001,
48260xc78,0x6d550001,
48270xc78,0x6c560001,
48280xc78,0x6b570001,
48290xc78,0x6a580001,
48300xc78,0x6a590001,
48310xc78,0x695a0001,
48320xc78,0x685b0001,
48330xc78,0x675c0001,
48340xc78,0x665d0001,
48350xc78,0x655e0001,
48360xc78,0x645f0001,
48370xc78,0x63600001,
48380xc78,0x4c610001,
48390xc78,0x4b620001,
48400xc78,0x4a630001,
48410xc78,0x49640001,
48420xc78,0x48650001,
48430xc78,0x47660001,
48440xc78,0x46670001,
48450xc78,0x45680001,
48460xc78,0x44690001,
48470xc78,0x2c6a0001,
48480xc78,0x2b6b0001,
48490xc78,0x2a6c0001,
48500xc78,0x296d0001,
48510xc78,0x286e0001,
48520xc78,0x276f0001,
48530xc78,0x26700001,
48540xc78,0x25710001,
48550xc78,0x24720001,
48560xc78,0x23730001,
48570xc78,0x22740001,
48580xc78,0x09750001,
48590xc78,0x08760001,
48600xc78,0x07770001,
48610xc78,0x06780001,
48620xc78,0x05790001,
48630xc78,0x047a0001,
48640xc78,0x037b0001,
48650xc78,0x027c0001,
48660xc78,0x017d0001,
48670xc78,0x007e0001,
48680xc78,0x007f0001,
48690xc78,0x3000001e,
48700xc78,0x3001001e,
48710xc78,0x3002001e,
48720xc78,0x3003001e,
48730xc78,0x3004001e,
48740xc78,0x3405001e,
48750xc78,0x3806001e,
48760xc78,0x3e07001e,
48770xc78,0x3e08001e,
48780xc78,0x4409001e,
48790xc78,0x460a001e,
48800xc78,0x480b001e,
48810xc78,0x480c001e,
48820xc78,0x4e0d001e,
48830xc78,0x560e001e,
48840xc78,0x5a0f001e,
48850xc78,0x5e10001e,
48860xc78,0x6211001e,
48870xc78,0x6c12001e,
48880xc78,0x7213001e,
48890xc78,0x7214001e,
48900xc78,0x7215001e,
48910xc78,0x7216001e,
48920xc78,0x7217001e,
48930xc78,0x7218001e,
48940xc78,0x7219001e,
48950xc78,0x721a001e,
48960xc78,0x721b001e,
48970xc78,0x721c001e,
48980xc78,0x721d001e,
48990xc78,0x721e001e,
49000xc78,0x721f001e,
4901};
4902
diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.h b/drivers/staging/rtl8192su/r8192SU_HWImg.h
new file mode 100644
index 00000000000..96b15252ea8
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192SU_HWImg.h
@@ -0,0 +1,44 @@
1#ifndef __INC_HAL8192SU_FW_IMG_H
2#define __INC_HAL8192SU_FW_IMG_H
3
4#include <linux/types.h>
5
6/*Created on 2009/ 3/ 6, 5:29*/
7
8#define ImgArrayLength 68368
9extern u8 Rtl8192SUFwImgArray[ImgArrayLength];
10#define MainArrayLength 1
11extern u8 Rtl8192SUFwMainArray[MainArrayLength];
12#define DataArrayLength 1
13extern u8 Rtl8192SUFwDataArray[DataArrayLength];
14#define PHY_REG_2T2RArrayLength 372
15extern u32 Rtl8192SUPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength];
16#define PHY_REG_1T2RArrayLength 1
17extern u32 Rtl8192SUPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength];
18#define PHY_ChangeTo_1T1RArrayLength 48
19extern u32 Rtl8192SUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
20#define PHY_ChangeTo_1T2RArrayLength 45
21extern u32 Rtl8192SUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
22#define PHY_ChangeTo_2T2RArrayLength 45
23extern u32 Rtl8192SUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
24#define PHY_REG_Array_PGLength 21
25extern u32 Rtl8192SUPHY_REG_Array_PG[PHY_REG_Array_PGLength];
26#define RadioA_1T_ArrayLength 202
27extern u32 Rtl8192SURadioA_1T_Array[RadioA_1T_ArrayLength];
28#define RadioB_ArrayLength 22
29extern u32 Rtl8192SURadioB_Array[RadioB_ArrayLength];
30#define RadioA_to1T_ArrayLength 2
31extern u32 Rtl8192SURadioA_to1T_Array[RadioA_to1T_ArrayLength];
32#define RadioA_to2T_ArrayLength 2
33extern u32 Rtl8192SURadioA_to2T_Array[RadioA_to2T_ArrayLength];
34#define RadioB_GM_ArrayLength 16
35extern u32 Rtl8192SURadioB_GM_Array[RadioB_GM_ArrayLength];
36#define MAC_2T_ArrayLength 106
37extern u32 Rtl8192SUMAC_2T_Array[MAC_2T_ArrayLength];
38#define MACPHY_Array_PGLength 1
39extern u32 Rtl8192SUMACPHY_Array_PG[MACPHY_Array_PGLength];
40#define AGCTAB_ArrayLength 320
41extern u32 Rtl8192SUAGCTAB_Array[AGCTAB_ArrayLength];
42
43#endif //__INC_HAL8192SU_FW_IMG_H
44
diff --git a/drivers/staging/rtl8192su/r8192S_Efuse.c b/drivers/staging/rtl8192su/r8192S_Efuse.c
new file mode 100644
index 00000000000..394ab967435
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_Efuse.c
@@ -0,0 +1,2442 @@
1/******************************************************************************
2 *
3 * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4 *
5 * Module: Efuse.c ( Source C File)
6 *
7 * Note: Copy from WMAC for the first version!!!!
8 *
9 *
10 * Function:
11 *
12 * Export:
13 *
14 * Abbrev:
15 *
16 * History:
17 * Data Who Remark
18 *
19 * 09/23/2008 MHC Porting Efuse R/W API from WMAC.
20 * 11/10/2008 MHC 1. Porting from 8712 EFUSE.
21 * 2. Add description and reorganize code arch.
22 * 11/16/2008 MHC 1. Reorganize code architecture.
23 * 2. Rename for some API and change extern or static type.
24 *
25******************************************************************************/
26#include "r8192U.h"
27#include "r8192S_hw.h"
28#include "r8192S_phy.h"
29#include "r8192S_phyreg.h"
30#include "r8192S_Efuse.h"
31
32#include <linux/types.h>
33
34//typedef int INT32;
35//
36// In the future, we will always support EFUSE!!
37//
38#ifdef RTL8192SU
39/*---------------------------Define Local Constant---------------------------*/
40#define _POWERON_DELAY_
41#define _PRE_EXECUTE_READ_CMD_
42
43#define EFUSE_REPEAT_THRESHOLD_ 3
44#define EFUSE_ERROE_HANDLE 1
45
46
47// From 8712!!!!!
48typedef struct _EFUSE_MAP_A{
49 u8 offset; //0~15
50 u8 word_start; //0~3
51 u8 byte_start; //0 or 1
52 u8 byte_cnts;
53
54}EFUSE_MAP, *PEFUSE_MAP;
55
56typedef struct PG_PKT_STRUCT_A{
57 u8 offset;
58 u8 word_en;
59 u8 data[8];
60}PGPKT_STRUCT,*PPGPKT_STRUCT;
61
62typedef enum _EFUSE_DATA_ITEM{
63 EFUSE_CHIP_ID=0,
64 EFUSE_LDO_SETTING,
65 EFUSE_CLK_SETTING,
66 EFUSE_SDIO_SETTING,
67 EFUSE_CCCR,
68 EFUSE_SDIO_MODE,
69 EFUSE_OCR,
70 EFUSE_F0CIS,
71 EFUSE_F1CIS,
72 EFUSE_MAC_ADDR,
73 EFUSE_EEPROM_VER,
74 EFUSE_CHAN_PLAN,
75 EFUSE_TXPW_TAB
76} EFUSE_DATA_ITEM;
77
78struct efuse_priv
79{
80 u8 id[2];
81 u8 ldo_setting[2];
82 u8 clk_setting[2];
83 u8 cccr;
84 u8 sdio_mode;
85 u8 ocr[3];
86 u8 cis0[17];
87 u8 cis1[48];
88 u8 mac_addr[6];
89 u8 eeprom_verno;
90 u8 channel_plan;
91 u8 tx_power_b[14];
92 u8 tx_power_g[14];
93};
94
95/*---------------------------Define Local Constant---------------------------*/
96
97
98/*------------------------Define global variable-----------------------------*/
99const u8 MAX_PGPKT_SIZE = 9; //header+ 2* 4 words (BYTES)
100const u8 PGPKT_DATA_SIZE = 8; //BYTES sizeof(u8)*8
101const u32 EFUSE_MAX_SIZE = 512;
102
103
104const EFUSE_MAP RTL8712_SDIO_EFUSE_TABLE[]={
105 //offset word_s byte_start byte_cnts
106/*ID*/ {0 ,0 ,0 ,2 }, // 00~01h
107/*LDO Setting*/ {0 ,1 ,0 ,2 }, // 02~03h
108/*CLK Setting*/ {0 ,2 ,0 ,2 }, // 04~05h
109/*SDIO Setting*/ {1 ,0 ,0 ,1 }, // 08h
110/*CCCR*/ {1 ,0 ,1 ,1 }, // 09h
111/*SDIO MODE*/ {1 ,1 ,0 ,1 }, // 0Ah
112/*OCR*/ {1 ,1 ,1 ,3 }, // 0B~0Dh
113/*CCIS*/ {1 ,3 ,0 ,17 }, // 0E~1Eh 2...1
114/*F1CIS*/ {3 ,3 ,1 ,48 }, // 1F~4Eh 6...0
115/*MAC Addr*/ {10 ,0 ,0 ,6 }, // 50~55h
116/*EEPROM ver*/ {10 ,3 ,0 ,1 }, // 56h
117/*Channel plan*/ {10 ,3 ,1 ,1 }, // 57h
118/*TxPwIndex */ {11 ,0 ,0 ,28 } // 58~73h 3...4
119};
120
121/*------------------------Define global variable-----------------------------*/
122
123
124/*------------------------Define local variable------------------------------*/
125
126/*------------------------Define local variable------------------------------*/
127
128
129/*--------------------Define function prototype-----------------------*/
130//
131// From WMAC Efuse one byte R/W
132//
133extern void
134EFUSE_Initialize(struct net_device* dev);
135extern u8
136EFUSE_Read1Byte(struct net_device* dev, u16 Address);
137extern void
138EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value);
139
140//
141// Efuse Shadow Area operation
142//
143static void
144efuse_ShadowRead1Byte(struct net_device* dev,u16 Offset,u8 *Value);
145static void
146efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset,u16 *Value );
147static void
148efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset,u32 *Value );
149static void
150efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value);
151static void
152efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset,u16 Value);
153static void
154efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset,u32 Value);
155
156//
157// Real Efuse operation
158//
159static u8
160efuse_OneByteRead(struct net_device* dev,u16 addr,u8 *data);
161static u8
162efuse_OneByteWrite(struct net_device* dev,u16 addr, u8 data);
163
164//
165// HW setting map file operation
166//
167static void
168efuse_ReadAllMap(struct net_device* dev,u8 *Efuse);
169#ifdef TO_DO_LIST
170static void
171efuse_WriteAllMap(struct net_device* dev,u8 *eeprom,u32 eeprom_size);
172static bool
173efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove);
174#endif
175//
176// Reald Efuse R/W or other operation API.
177//
178static u8
179efuse_PgPacketRead( struct net_device* dev,u8 offset,u8 *data);
180static u8
181efuse_PgPacketWrite(struct net_device* dev,u8 offset,u8 word_en,u8 *data);
182static void
183efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata);
184static u8
185efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data);
186static void
187efuse_PowerSwitch(struct net_device* dev,u8 PwrState);
188static u16
189efuse_GetCurrentSize(struct net_device* dev);
190static u8
191efuse_CalculateWordCnts(u8 word_en);
192#if 0
193static void
194efuse_ResetLoader(struct net_device* dev);
195#endif
196//
197// API for power on power off!!!
198//
199#ifdef TO_DO_LIST
200static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn);
201#endif
202/*--------------------Define function prototype-----------------------*/
203
204
205
206/*-----------------------------------------------------------------------------
207 * Function: EFUSE_Initialize
208 *
209 * Overview: Copy from WMAC fot EFUSE testing setting init.
210 *
211 * Input: NONE
212 *
213 * Output: NONE
214 *
215 * Return: NONE
216 *
217 * Revised History:
218 * When Who Remark
219 * 09/23/2008 MHC Copy from WMAC.
220 *
221 *---------------------------------------------------------------------------*/
222extern void
223EFUSE_Initialize(struct net_device* dev)
224{
225 u8 Bytetemp = {0x00};
226 u8 temp = {0x00};
227
228 //Enable Digital Core Vdd : 0x2[13]=1
229 Bytetemp = read_nic_byte(dev, SYS_FUNC_EN+1);
230 temp = Bytetemp | 0x20;
231 write_nic_byte(dev, SYS_FUNC_EN+1, temp);
232
233 //EE loader to retention path1: attach 0x0[8]=0
234 Bytetemp = read_nic_byte(dev, SYS_ISO_CTRL+1);
235 temp = Bytetemp & 0xFE;
236 write_nic_byte(dev, SYS_ISO_CTRL+1, temp);
237
238
239 //Enable E-fuse use 2.5V LDO : 0x37[7]=1
240 Bytetemp = read_nic_byte(dev, EFUSE_TEST+3);
241 temp = Bytetemp | 0x80;
242 write_nic_byte(dev, EFUSE_TEST+3, temp);
243
244 //E-fuse clk switch from 500k to 40M : 0x2F8[1:0]=11b
245 write_nic_byte(dev, 0x2F8, 0x3);
246
247 //Set E-fuse program time & read time : 0x30[30:24]=1110010b
248 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
249
250} /* EFUSE_Initialize */
251
252
253/*-----------------------------------------------------------------------------
254 * Function: EFUSE_Read1Byte
255 *
256 * Overview: Copy from WMAC fot EFUSE read 1 byte.
257 *
258 * Input: NONE
259 *
260 * Output: NONE
261 *
262 * Return: NONE
263 *
264 * Revised History:
265 * When Who Remark
266 * 09/23/2008 MHC Copy from WMAC.
267 *
268 *---------------------------------------------------------------------------*/
269extern u8
270EFUSE_Read1Byte(struct net_device* dev, u16 Address)
271{
272 u8 data;
273 u8 Bytetemp = {0x00};
274 u8 temp = {0x00};
275 u32 k=0;
276
277 if (Address < EFUSE_MAC_LEN) //E-fuse 512Byte
278 {
279 //Write E-fuse Register address bit0~7
280 temp = Address & 0xFF;
281 write_nic_byte(dev, EFUSE_CTRL+1, temp);
282 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2);
283 //Write E-fuse Register address bit8~9
284 temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
285 write_nic_byte(dev, EFUSE_CTRL+2, temp);
286
287 //Write 0x30[31]=0
288 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
289 temp = Bytetemp & 0x7F;
290 write_nic_byte(dev, EFUSE_CTRL+3, temp);
291
292 //Wait Write-ready (0x30[31]=1)
293 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
294 while(!(Bytetemp & 0x80))
295 {
296 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
297 k++;
298 if(k==1000)
299 {
300 k=0;
301 break;
302 }
303 }
304 data=read_nic_byte(dev, EFUSE_CTRL);
305 return data;
306 }
307 else
308 return 0xFF;
309
310} /* EFUSE_Read1Byte */
311
312
313/*-----------------------------------------------------------------------------
314 * Function: EFUSE_Write1Byte
315 *
316 * Overview: Copy from WMAC fot EFUSE write 1 byte.
317 *
318 * Input: NONE
319 *
320 * Output: NONE
321 *
322 * Return: NONE
323 *
324 * Revised History:
325 * When Who Remark
326 * 09/23/2008 MHC Copy from WMAC.
327 *
328 *---------------------------------------------------------------------------*/
329extern void
330EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value)
331{
332 //u8 data;
333 u8 Bytetemp = {0x00};
334 u8 temp = {0x00};
335 u32 k=0;
336
337 //RT_TRACE(COMP_EFUSE, "Addr=%x Data =%x\n", Address, Value);
338
339 if( Address < EFUSE_MAC_LEN) //E-fuse 512Byte
340 {
341 write_nic_byte(dev, EFUSE_CTRL, Value);
342
343 //Write E-fuse Register address bit0~7
344 temp = Address & 0xFF;
345 write_nic_byte(dev, EFUSE_CTRL+1, temp);
346 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2);
347
348 //Write E-fuse Register address bit8~9
349 temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
350 write_nic_byte(dev, EFUSE_CTRL+2, temp);
351
352 //Write 0x30[31]=1
353 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
354 temp = Bytetemp | 0x80;
355 write_nic_byte(dev, EFUSE_CTRL+3, temp);
356
357 //Wait Write-ready (0x30[31]=0)
358 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
359 while(Bytetemp & 0x80)
360 {
361 Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
362 k++;
363 if(k==100)
364 {
365 k=0;
366 break;
367 }
368 }
369 }
370
371} /* EFUSE_Write1Byte */
372
373
374#ifdef EFUSE_FOR_92SU
375//
376// Description:
377// 1. Process CR93C46 Data polling cycle.
378// 2. Refered from SD1 Richard.
379//
380// Assumption:
381// 1. Boot from E-Fuse and successfully auto-load.
382// 2. PASSIVE_LEVEL (USB interface)
383//
384// Created by Roger, 2008.10.21.
385//
386void do_93c46(struct net_device* dev, u8 addorvalue)
387{
388 //u8 clear[1] = {0x0}; // cs=0 , sk=0 , di=0 , do=0
389 u8 cs[1] = {0x88}; // cs=1 , sk=0 , di=0 , do=0
390 u8 cssk[1] = {0x8c}; // cs=1 , sk=1 , di=0 , do=0
391 u8 csdi[1] = {0x8a}; // cs=1 , sk=0 , di=1 , do=0
392 u8 csskdi[1] = {0x8e}; // cs=1 , sk=1 , di=1 , do=0
393 //u8 di[1] = {0x82}; // cs=0 , sk=0 , di=1 , do=0
394 u8 count;
395
396 for(count=0 ; count<8 ; count++)
397 {
398 if((addorvalue&0x80)!=0)
399 {
400 write_nic_byte(dev, EPROM_CMD, csdi[0]);
401 write_nic_byte(dev, EPROM_CMD, csskdi[0]);
402 }
403 else
404 {
405 write_nic_byte(dev, EPROM_CMD, cs[0]);
406 write_nic_byte(dev, EPROM_CMD, cssk[0]);
407 }
408 addorvalue = addorvalue << 1;
409 }
410}
411
412
413//
414// Description:
415// Process CR93C46 Data read polling cycle.
416// Refered from SD1 Richard.
417//
418// Assumption:
419// 1. Boot from E-Fuse and successfully auto-load.
420// 2. PASSIVE_LEVEL (USB interface)
421//
422// Created by Roger, 2008.10.21.
423//
424u16 Read93C46(struct net_device* dev, u16 Reg )
425{
426
427 u8 clear[1] = {0x0}; // cs=0 , sk=0 , di=0 , do=0
428 u8 cs[1] = {0x88}; // cs=1 , sk=0 , di=0 , do=0
429 u8 cssk[1] = {0x8c}; // cs=1 , sk=1 , di=0 , do=0
430 u8 csdi[1] = {0x8a}; // cs=1 , sk=0 , di=1 , do=0
431 u8 csskdi[1] = {0x8e}; // cs=1 , sk=1 , di=1 , do=0
432 //u8 di[1] = {0x82}; // cs=0 , sk=0 , di=1 , do=0
433 u8 EepromSEL[1]={0x00};
434 u8 address;
435
436 u16 storedataF[1] = {0x0}; //93c46 data packet for 16bits
437 u8 t,data[1],storedata[1];
438
439
440 address = (u8)Reg;
441
442 // Suggested by SD1 Alex, 2008.10.20. Revised by Roger.
443 *EepromSEL= read_nic_byte(dev, EPROM_CMD);
444
445 if((*EepromSEL & 0x10) == 0x10) // select 93c46
446 {
447 address = address | 0x80;
448
449 write_nic_byte(dev, EPROM_CMD, csdi[0]);
450 write_nic_byte(dev, EPROM_CMD, csskdi[0]);
451 do_93c46(dev, address);
452 }
453
454
455 for(t=0 ; t<16 ; t++) //if read 93c46 , t=16
456 {
457 write_nic_byte(dev, EPROM_CMD, cs[0]);
458 write_nic_byte(dev, EPROM_CMD, cssk[0]);
459 *data= read_nic_byte(dev, EPROM_CMD);
460
461 if(*data & 0x8d) //original code
462 {
463 *data = *data & 0x01;
464 *storedata = *data;
465 }
466 else
467 {
468 *data = *data & 0x01 ;
469 *storedata = *data;
470 }
471 *storedataF = (*storedataF << 1 ) + *storedata;
472 }
473 write_nic_byte(dev, EPROM_CMD, cs[0]);
474 write_nic_byte(dev, EPROM_CMD, clear[0]);
475
476 return *storedataF;
477}
478
479
480//
481// Description:
482// Execute E-Fuse read byte operation.
483// Refered from SD1 Richard.
484//
485// Assumption:
486// 1. Boot from E-Fuse and successfully auto-load.
487// 2. PASSIVE_LEVEL (USB interface)
488//
489// Created by Roger, 2008.10.21.
490//
491void
492ReadEFuseByte(struct net_device* dev,u16 _offset, u8 *pbuf)
493{
494
495 //u16 indexk=0;
496 u32 value32;
497 u8 readbyte;
498 u16 retry;
499
500
501 //Write Address
502 write_nic_byte(dev, EFUSE_CTRL+1, (_offset & 0xff));
503 readbyte = read_nic_byte(dev, EFUSE_CTRL+2);
504 write_nic_byte(dev, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
505
506 //Write bit 32 0
507 readbyte = read_nic_byte(dev, EFUSE_CTRL+3);
508 write_nic_byte(dev, EFUSE_CTRL+3, (readbyte & 0x7f));
509
510 //Check bit 32 read-ready
511 retry = 0;
512 value32 = read_nic_dword(dev, EFUSE_CTRL);
513 //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10))
514 while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000))
515 {
516 value32 = read_nic_dword(dev, EFUSE_CTRL);
517 retry++;
518 }
519 *pbuf = (u8)(value32 & 0xff);
520}
521
522
523#define EFUSE_READ_SWITCH 1
524//
525// Description:
526// 1. Execute E-Fuse read byte operation according as map offset and
527// save to E-Fuse table.
528// 2. Refered from SD1 Richard.
529//
530// Assumption:
531// 1. Boot from E-Fuse and successfully auto-load.
532// 2. PASSIVE_LEVEL (USB interface)
533//
534// Created by Roger, 2008.10.21.
535//
536void
537ReadEFuse(struct net_device* dev, u16 _offset, u16 _size_byte, u8 *pbuf)
538{
539
540 u8 efuseTbl[128];
541 u8 rtemp8[1];
542 u16 eFuse_Addr = 0;
543 u8 offset, wren;
544 u16 i, j;
545 u16 eFuseWord[16][4];// = {0xFF};//FIXLZM
546
547 for(i=0; i<16; i++)
548 for(j=0; j<4; j++)
549 eFuseWord[i][j]=0xFF;
550
551 // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
552 if((_offset + _size_byte)>128)
553 {// total E-Fuse table is 128bytes
554 //RT_TRACE(COMP_EFUSE, "ReadEFuse(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte);
555 printk("ReadEFuse(): Invalid offset with read bytes!!\n");
556 return;
557 }
558
559 // Refresh efuse init map as all oxFF.
560 for (i = 0; i < 128; i++)
561 efuseTbl[i] = 0xFF;
562
563#if (EFUSE_READ_SWITCH == 1)
564 ReadEFuseByte(dev, eFuse_Addr, rtemp8);
565#else
566 rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr);
567#endif
568 if(*rtemp8 != 0xFF) eFuse_Addr++;
569 while((*rtemp8 != 0xFF) && (eFuse_Addr < 512)){
570 offset = ((*rtemp8 >> 4) & 0x0f);
571 if(offset <= 0x0F){
572 wren = (*rtemp8 & 0x0f);
573 for(i=0; i<4; i++){
574 if(!(wren & 0x01)){
575#if (EFUSE_READ_SWITCH == 1)
576 ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++;
577#else
578 rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++;
579#endif
580 eFuseWord[offset][i] = (*rtemp8 & 0xff);
581 if(eFuse_Addr >= 512) break;
582#if (EFUSE_READ_SWITCH == 1)
583 ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++;
584#else
585 rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++;
586#endif
587 eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
588 if(eFuse_Addr >= 512) break;
589 }
590 wren >>= 1;
591 }
592 }
593#if (EFUSE_READ_SWITCH == 1)
594 ReadEFuseByte(dev, eFuse_Addr, rtemp8);
595#else
596 rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++;
597#endif
598 if(*rtemp8 != 0xFF && (eFuse_Addr < 512)) eFuse_Addr++;
599 }
600
601 for(i=0; i<16; i++){
602 for(j=0; j<4; j++){
603 efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
604 efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
605 }
606 }
607 for(i=0; i<_size_byte; i++)
608 pbuf[i] = efuseTbl[_offset+i];
609}
610#endif // #if (EFUSE_FOR_92SU == 1)
611
612
613/*-----------------------------------------------------------------------------
614 * Function: EFUSE_ShadowRead
615 *
616 * Overview: Read from efuse init map !!!!!
617 *
618 * Input: NONE
619 *
620 * Output: NONE
621 *
622 * Return: NONE
623 *
624 * Revised History:
625 * When Who Remark
626 * 11/12/2008 MHC Create Version 0.
627 *
628 *---------------------------------------------------------------------------*/
629extern void
630EFUSE_ShadowRead( struct net_device* dev, u8 Type, u16 Offset, u32 *Value)
631{
632 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
633
634 if (Type == 1)
635 efuse_ShadowRead1Byte(dev, Offset, (u8 *)Value);
636 else if (Type == 2)
637 efuse_ShadowRead2Byte(dev, Offset, (u16 *)Value);
638 else if (Type == 4)
639 efuse_ShadowRead4Byte(dev, Offset, (u32 *)Value);
640
641} // EFUSE_ShadowRead
642
643
644/*-----------------------------------------------------------------------------
645 * Function: EFUSE_ShadowWrite
646 *
647 * Overview: Write efuse modify map for later update operation to use!!!!!
648 *
649 * Input: NONE
650 *
651 * Output: NONE
652 *
653 * Return: NONE
654 *
655 * Revised History:
656 * When Who Remark
657 * 11/12/2008 MHC Create Version 0.
658 *
659 *---------------------------------------------------------------------------*/
660extern void
661EFUSE_ShadowWrite( struct net_device* dev, u8 Type, u16 Offset,u32 Value)
662{
663 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
664
665 if (Offset >= 0x18 && Offset <= 0x1F)
666 return;
667
668 if (Type == 1)
669 efuse_ShadowWrite1Byte(dev, Offset, (u8)Value);
670 else if (Type == 2)
671 efuse_ShadowWrite2Byte(dev, Offset, (u16)Value);
672 else if (Type == 4)
673 efuse_ShadowWrite4Byte(dev, Offset, (u32)Value);
674
675} // EFUSE_ShadowWrite
676
677
678/*-----------------------------------------------------------------------------
679 * Function: EFUSE_ShadowUpdate
680 *
681 * Overview: Compare init and modify map to update Efuse!!!!!
682 *
683 * Input: NONE
684 *
685 * Output: NONE
686 *
687 * Return: NONE
688 *
689 * Revised History:
690 * When Who Remark
691 * 11/12/2008 MHC Create Version 0.
692 *
693 *---------------------------------------------------------------------------*/
694extern void
695EFUSE_ShadowUpdate(struct net_device* dev)
696{
697 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
698 struct r8192_priv *priv = ieee80211_priv(dev);
699 u16 i, offset, base = 0;
700 u8 word_en = 0x0F;
701 bool first_pg = false;
702 // For Efuse write action, we must enable LDO2.5V and 40MHZ clk.
703 efuse_PowerSwitch(dev, TRUE);
704
705 //
706 // Efuse support 16 write are with PG header packet!!!!
707 //
708 for (offset = 0; offset < 16; offset++)
709 {
710 // Offset 0x18-1F are reserved now!!!
711#ifdef RTL8192SE
712 if(priv->card_8192 == NIC_8192SE){
713 if (offset == 3)
714 continue;
715 }
716#endif
717 word_en = 0x0F;
718 base = offset * 8;
719
720 //
721 // Decide Word Enable Bit for the Efuse section
722 // One section contain 4 words = 8 bytes!!!!!
723 //
724 for (i = 0; i < 8; i++)
725 {
726 if (offset == 0 && priv->EfuseMap[EFUSE_INIT_MAP][base+i] == 0xFF)
727 {
728 first_pg = TRUE;
729 }
730
731 // 2008/12/11 MH HW autoload fail workaround for A/BCUT.
732#ifdef RTL8192SE
733 if (first_pg == TRUE && offset == 1 && (priv->card_8192 == NIC_8192SE))
734 {
735 continue;
736 }
737#endif
738
739 if (first_pg == TRUE)
740 {
741 word_en &= ~(1<<(i/2));
742 priv->EfuseMap[EFUSE_INIT_MAP][base+i] =
743 priv->EfuseMap[EFUSE_MODIFY_MAP][base+i];
744 }else
745 {
746 if ( priv->EfuseMap[EFUSE_INIT_MAP][base+i] !=
747 priv->EfuseMap[EFUSE_MODIFY_MAP][base+i])
748 {
749 word_en &= ~(EFUSE_BIT(i/2));
750 //RT_TRACE(COMP_EFUSE, "Offset=%d Addr%x %x ==> %x Word_En=%02x\n",
751 //offset, base+i, priv->EfuseMap[0][base+i], priv->EfuseMap[1][base+i],word_en);
752
753 // Update init table!!!
754 priv->EfuseMap[EFUSE_INIT_MAP][base+i] =
755 priv->EfuseMap[EFUSE_MODIFY_MAP][base+i];
756 }
757 }
758 }
759
760 //
761 // Call Efuse real write section !!!!
762 //
763 if (word_en != 0x0F)
764 {
765 u8 tmpdata[8];
766
767 //FIXLZM
768 memcpy(tmpdata, &(priv->EfuseMap[EFUSE_MODIFY_MAP][base]), 8);
769 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("U-EFUSE\n"), tmpdata, 8);
770 efuse_PgPacketWrite(dev,(u8)offset,word_en,tmpdata);
771 }
772
773 }
774 // 2008/12/01 MH For Efuse HW load bug workarounf method!!!!
775 // We will force write 0x10EC into address 10&11 after all Efuse content.
776 //
777#ifdef RTL8192SE
778 if (first_pg == TRUE && (priv->card_8192 == NIC_8192SE))
779 {
780 // 2008/12/11 MH Use new method to prevent HW autoload fail.
781 u8 tmpdata[8];
782
783 memcpy(tmpdata, (&priv->EfuseMap[EFUSE_MODIFY_MAP][8]), 8);
784 efuse_PgPacketWrite(dev, 1, 0x0, tmpdata);
785#if 0
786 u1Byte tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF};
787
788 efuse_PgPacketWrite(pAdapter, 1, 0xD, tmpdata);
789#endif
790 }
791#endif
792
793
794 // For warm reboot, we must resume Efuse clock to 500K.
795 efuse_PowerSwitch(dev, FALSE);
796 // 2008/12/01 MH We update shadow content again!!!!
797 EFUSE_ShadowMapUpdate(dev);
798
799} // EFUSE_ShadowUpdate
800
801
802/*-----------------------------------------------------------------------------
803 * Function: EFUSE_ShadowMapUpdate
804 *
805 * Overview: Transfer current EFUSE content to shadow init and modify map.
806 *
807 * Input: NONE
808 *
809 * Output: NONE
810 *
811 * Return: NONE
812 *
813 * Revised History:
814 * When Who Remark
815 * 11/13/2008 MHC Create Version 0.
816 *
817 *---------------------------------------------------------------------------*/
818extern void EFUSE_ShadowMapUpdate(struct net_device* dev)
819{
820 struct r8192_priv *priv = ieee80211_priv(dev);
821
822 if (priv->AutoloadFailFlag == true){
823 memset(&(priv->EfuseMap[EFUSE_INIT_MAP][0]), 0xff, 128);
824 }else{
825 efuse_ReadAllMap(dev, &priv->EfuseMap[EFUSE_INIT_MAP][0]);
826 }
827 //PlatformMoveMemory(&priv->EfuseMap[EFUSE_MODIFY_MAP][0],
828 //&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);//FIXLZM
829 memcpy(&priv->EfuseMap[EFUSE_MODIFY_MAP][0],
830 &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
831
832} // EFUSE_ShadowMapUpdate
833
834extern void
835EFUSE_ForceWriteVendorId( struct net_device* dev)
836{
837 u8 tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF};
838
839 efuse_PowerSwitch(dev, TRUE);
840
841 efuse_PgPacketWrite(dev, 1, 0xD, tmpdata);
842
843 efuse_PowerSwitch(dev, FALSE);
844
845} // EFUSE_ForceWriteVendorId
846
847/*-----------------------------------------------------------------------------
848 * Function: efuse_ShadowRead1Byte
849 * efuse_ShadowRead2Byte
850 * efuse_ShadowRead4Byte
851 *
852 * Overview: Read from efuse init map by one/two/four bytes !!!!!
853 *
854 * Input: NONE
855 *
856 * Output: NONE
857 *
858 * Return: NONE
859 *
860 * Revised History:
861 * When Who Remark
862 * 11/12/2008 MHC Create Version 0.
863 *
864 *---------------------------------------------------------------------------*/
865static void
866efuse_ShadowRead1Byte(struct net_device* dev, u16 Offset, u8 *Value)
867{
868 struct r8192_priv *priv = ieee80211_priv(dev);
869
870 *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
871
872} // EFUSE_ShadowRead1Byte
873
874//---------------Read Two Bytes
875static void
876efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset, u16 *Value)
877{
878 struct r8192_priv *priv = ieee80211_priv(dev);
879
880 *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
881 *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8;
882
883} // EFUSE_ShadowRead2Byte
884
885//---------------Read Four Bytes
886static void
887efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset, u32 *Value)
888{
889 struct r8192_priv *priv = ieee80211_priv(dev);
890
891 *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
892 *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8;
893 *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2]<<16;
894 *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3]<<24;
895
896} // efuse_ShadowRead4Byte
897
898
899
900/*-----------------------------------------------------------------------------
901 * Function: efuse_ShadowWrite1Byte
902 * efuse_ShadowWrite2Byte
903 * efuse_ShadowWrite4Byte
904 *
905 * Overview: Write efuse modify map by one/two/four byte.
906 *
907 * Input: NONE
908 *
909 * Output: NONE
910 *
911 * Return: NONE
912 *
913 * Revised History:
914 * When Who Remark
915 * 11/12/2008 MHC Create Version 0.
916 *
917 *---------------------------------------------------------------------------*/
918static void
919efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value)
920{
921 struct r8192_priv *priv = ieee80211_priv(dev);
922
923 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value;
924
925} // efuse_ShadowWrite1Byte
926
927//---------------Write Two Bytes
928static void
929efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset, u16 Value)
930{
931 struct r8192_priv *priv = ieee80211_priv(dev);
932
933 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value&0x00FF;
934 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = Value>>8;
935
936} // efuse_ShadowWrite1Byte
937
938//---------------Write Four Bytes
939static void
940efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset, u32 Value)
941{
942 struct r8192_priv *priv = ieee80211_priv(dev);
943
944 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = (u8)(Value&0x000000FF);
945 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = (u8)((Value>>8)&0x0000FF);
946 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2] = (u8)((Value>>16)&0x00FF);
947 priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3] = (u8)((Value>>24)&0xFF);
948
949} // efuse_ShadowWrite1Byte
950
951
952/* 11/16/2008 MH Read one byte from real Efuse. */
953static u8
954efuse_OneByteRead(struct net_device* dev, u16 addr,u8 *data)
955{
956 u8 tmpidx = 0;
957 u8 bResult;
958
959 // -----------------e-fuse reg ctrl ---------------------------------
960 //address
961 write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff));
962 write_nic_byte(dev, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) |
963 (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC ));
964
965 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);//read cmd
966
967 while(!(0x80 &read_nic_byte(dev, EFUSE_CTRL+3))&&(tmpidx<100))
968 {
969 tmpidx++;
970 }
971 if(tmpidx<100)
972 {
973 *data=read_nic_byte(dev, EFUSE_CTRL);
974 bResult = TRUE;
975 }
976 else
977 {
978 *data = 0xff;
979 bResult = FALSE;
980 }
981 return bResult;
982} // efuse_OneByteRead
983
984/* 11/16/2008 MH Write one byte to reald Efuse. */
985static u8
986efuse_OneByteWrite(struct net_device* dev, u16 addr, u8 data)
987{
988 u8 tmpidx = 0;
989 u8 bResult;
990
991 //RT_TRACE(COMP_EFUSE, "Addr = %x Data=%x\n", addr, data);
992
993 //return 0;
994
995 // -----------------e-fuse reg ctrl ---------------------------------
996 //address
997 write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff));
998 write_nic_byte(dev, EFUSE_CTRL+2,
999 read_nic_byte(dev, EFUSE_CTRL+2)|(u8)((addr>>8)&0x03) );
1000
1001 write_nic_byte(dev, EFUSE_CTRL, data);//data
1002 write_nic_byte(dev, EFUSE_CTRL+3, 0xF2);//write cmd
1003
1004 while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
1005 tmpidx++;
1006 }
1007
1008 if(tmpidx<100)
1009 {
1010 bResult = TRUE;
1011 }
1012 else
1013 {
1014 bResult = FALSE;
1015 }
1016
1017 return bResult;
1018} // efuse_OneByteWrite
1019
1020
1021/*-----------------------------------------------------------------------------
1022 * Function: efuse_ReadAllMap
1023 *
1024 * Overview: Read All Efuse content
1025 *
1026 * Input: NONE
1027 *
1028 * Output: NONE
1029 *
1030 * Return: NONE
1031 *
1032 * Revised History:
1033 * When Who Remark
1034 * 11/11/2008 MHC Create Version 0.
1035 *
1036 *---------------------------------------------------------------------------*/
1037static void
1038efuse_ReadAllMap(struct net_device* dev, u8 *Efuse)
1039{
1040 //u8 pg_data[8];
1041 //u8 offset = 0;
1042 //u8 tmpidx;
1043 //static u8 index = 0;
1044
1045 //
1046 // We must enable clock and LDO 2.5V otherwise, read all map will be fail!!!!
1047 //
1048 efuse_PowerSwitch(dev, TRUE);
1049 ReadEFuse(dev, 0, 128, Efuse);
1050 efuse_PowerSwitch(dev, FALSE);
1051#if 0
1052 // ==> Prevent efuse read error!!!
1053 RT_TRACE(COMP_INIT, "efuse_ResetLoader\n");
1054 efuse_ResetLoader(dev);
1055
1056 // Change Efuse Clock for write action to 40MHZ
1057 write_nic_byte(dev, EFUSE_CLK, 0x03);
1058
1059 ReadEFuse(dev, 0, 128, Efuse);
1060
1061 // Change Efuse Clock for write action to 500K
1062 write_nic_byte(dev, EFUSE_CLK, 0x02);
1063#if 0 // Error !!!!!!
1064 for(offset = 0;offset<16;offset++) // For 8192SE
1065 {
1066 PlatformFillMemory((PVOID)pg_data, 8, 0xff);
1067 efuse_PgPacketRead(pAdapter,offset,pg_data);
1068
1069 PlatformMoveMemory((PVOID)&Efuse[offset*8], (PVOID)pg_data, 8);
1070 }
1071#endif
1072
1073 //
1074 // Error Check and Reset Again!!!!
1075 //
1076 if (Efuse[0] != 0x29 || Efuse[1] != 0x81)
1077 {
1078 // SW autoload fail, we have to read again!!!
1079 if (index ++ < 5)
1080 {
1081 RT_TRACE(COMP_INIT, "EFUSE R FAIL %d\n", index);
1082 efuse_ReadAllMap(dev, Efuse);
1083 // Wait a few time ???? Or need to do some setting ???
1084 // When we reload driver, efuse will be OK!!
1085 }
1086 }
1087 else
1088 {
1089 index = 0;
1090 }
1091
1092 //efuse_PowerSwitch(pAdapter, FALSE);
1093#endif
1094} // efuse_ReadAllMap
1095
1096
1097/*-----------------------------------------------------------------------------
1098 * Function: efuse_WriteAllMap
1099 *
1100 * Overview: Write All Efuse content
1101 *
1102 * Input: NONE
1103 *
1104 * Output: NONE
1105 *
1106 * Return: NONE
1107 *
1108 * Revised History:
1109 * When Who Remark
1110 * 11/11/2008 MHC Create Version 0.
1111 *
1112 *---------------------------------------------------------------------------*/
1113#ifdef TO_DO_LIST
1114static void
1115efuse_WriteAllMap(struct net_device* dev,u8 *eeprom, u32 eeprom_size)
1116{
1117 unsigned char word_en = 0x00;
1118
1119 unsigned char tmpdata[8];
1120 unsigned char offset;
1121
1122 // For Efuse write action, we must enable LDO2.5V and 40MHZ clk.
1123 efuse_PowerSwitch(dev, TRUE);
1124
1125 //sdio contents
1126 for(offset=0 ; offset< eeprom_size/PGPKT_DATA_SIZE ; offset++)
1127 {
1128 // 92S will only reserv 0x18-1F 8 bytes now. The 3rd efuse write area!
1129 if (IS_HARDWARE_TYPE_8192SE(dev))
1130 {
1131 // Refer to
1132 // 0x18-1f Reserve >0x50 Reserve for tx power
1133 if (offset == 3/* || offset > 9*/)
1134 continue;//word_en = 0x0F;
1135 //else if (offset == 9) // 0x4c-4f Reserve
1136 //word_en = 0x0C;
1137 else
1138 word_en = 0x00;
1139 }
1140 //RT_TRACE(COMP_EFUSE, ("Addr=%d size=%d Word_En=%02x\n", offset, eeprom_size, word_en));
1141
1142 //memcpy(tmpdata,eeprom+(offset*PGPKT_DATA_SIZE),8);
1143 memcpy(tmpdata, (eeprom+(offset*PGPKT_DATA_SIZE)), 8);
1144
1145 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("EFUSE\t"), tmpdata, 8);
1146
1147 efuse_PgPacketWrite(dev,offset,word_en,tmpdata);
1148
1149
1150 }
1151
1152 // For warm reboot, we must resume Efuse clock to 500K.
1153 efuse_PowerSwitch(dev, FALSE);
1154
1155} // efuse_WriteAllMap
1156#endif
1157
1158/*-----------------------------------------------------------------------------
1159 * Function: efuse_PgPacketRead
1160 *
1161 * Overview: Receive dedicated Efuse are content. For92s, we support 16
1162 * area now. It will return 8 bytes content for every area.
1163 *
1164 * Input: NONE
1165 *
1166 * Output: NONE
1167 *
1168 * Return: NONE
1169 *
1170 * Revised History:
1171 * When Who Remark
1172 * 11/16/2008 MHC Reorganize code Arch and assign as local API.
1173 *
1174 *---------------------------------------------------------------------------*/
1175static u8
1176efuse_PgPacketRead( struct net_device* dev, u8 offset, u8 *data)
1177{
1178 u8 ReadState = PG_STATE_HEADER;
1179
1180 bool bContinual = TRUE;
1181 bool bDataEmpty = TRUE ;
1182
1183 u8 efuse_data,word_cnts=0;
1184 u16 efuse_addr = 0;
1185 u8 hoffset=0,hworden=0;
1186 u8 tmpidx=0;
1187 u8 tmpdata[8];
1188
1189 if(data==NULL) return FALSE;
1190 if(offset>15) return FALSE;
1191
1192 //FIXLZM
1193 //PlatformFillMemory((PVOID)data, sizeof(u8)*PGPKT_DATA_SIZE, 0xff);
1194 //PlatformFillMemory((PVOID)tmpdata, sizeof(u8)*PGPKT_DATA_SIZE, 0xff);
1195 memset(data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1196 memset(tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1197
1198 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("efuse_PgPacketRead-1\n"), data, 8);
1199
1200 //efuse_reg_ctrl(pAdapter,TRUE);//power on
1201 while(bContinual && (efuse_addr < EFUSE_MAX_SIZE) )
1202 {
1203 //------- Header Read -------------
1204 if(ReadState & PG_STATE_HEADER)
1205 {
1206 if(efuse_OneByteRead(dev, efuse_addr ,&efuse_data)&&(efuse_data!=0xFF)){
1207 hoffset = (efuse_data>>4) & 0x0F;
1208 hworden = efuse_data & 0x0F;
1209 word_cnts = efuse_CalculateWordCnts(hworden);
1210 bDataEmpty = TRUE ;
1211
1212 if(hoffset==offset){
1213 for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++){
1214 if(efuse_OneByteRead(dev, efuse_addr+1+tmpidx ,&efuse_data) ){
1215 tmpdata[tmpidx] = efuse_data;
1216 if(efuse_data!=0xff){
1217 bDataEmpty = FALSE;
1218 }
1219 }
1220 }
1221 if(bDataEmpty==FALSE){
1222 ReadState = PG_STATE_DATA;
1223 }else{//read next header
1224 efuse_addr = efuse_addr + (word_cnts*2)+1;
1225 ReadState = PG_STATE_HEADER;
1226 }
1227 }
1228 else{//read next header
1229 efuse_addr = efuse_addr + (word_cnts*2)+1;
1230 ReadState = PG_STATE_HEADER;
1231 }
1232
1233 }
1234 else{
1235 bContinual = FALSE ;
1236 }
1237 }
1238 //------- Data section Read -------------
1239 else if(ReadState & PG_STATE_DATA)
1240 {
1241 efuse_WordEnableDataRead(hworden,tmpdata,data);
1242 efuse_addr = efuse_addr + (word_cnts*2)+1;
1243 ReadState = PG_STATE_HEADER;
1244 }
1245
1246 }
1247 //efuse_reg_ctrl(pAdapter,FALSE);//power off
1248
1249 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("efuse_PgPacketRead-2\n"), data, 8);
1250
1251 if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) &&
1252 (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff))
1253 return FALSE;
1254 else
1255 return TRUE;
1256
1257} // efuse_PgPacketRead
1258
1259
1260/*-----------------------------------------------------------------------------
1261 * Function: efuse_PgPacketWrite
1262 *
1263 * Overview: Send A G package for different section in real efuse area.
1264 * For 92S, One PG package contain 8 bytes content and 4 word
1265 * unit. PG header = 0x[bit7-4=offset][bit3-0word enable]
1266 *
1267 * Input: NONE
1268 *
1269 * Output: NONE
1270 *
1271 * Return: NONE
1272 *
1273 * Revised History:
1274 * When Who Remark
1275 * 11/16/2008 MHC Reorganize code Arch and assign as local API.
1276 *
1277 *---------------------------------------------------------------------------*/
1278static u8 efuse_PgPacketWrite(struct net_device* dev, u8 offset, u8 word_en,u8 *data)
1279{
1280 u8 WriteState = PG_STATE_HEADER;
1281
1282 bool bContinual = TRUE,bDataEmpty=TRUE, bResult = TRUE;
1283 u16 efuse_addr = 0;
1284 u8 efuse_data;
1285
1286 u8 pg_header = 0;
1287
1288 //u16 tmp_addr=0;
1289 u8 tmp_word_cnts=0,target_word_cnts=0;
1290 u8 tmp_header,match_word_en,tmp_word_en;
1291
1292 //u8 efuse_clk_ori,efuse_clk_new;
1293
1294 PGPKT_STRUCT target_pkt;
1295 PGPKT_STRUCT tmp_pkt;
1296
1297 u8 originaldata[sizeof(u8)*8];
1298 u8 tmpindex = 0,badworden = 0x0F;
1299
1300 static u32 repeat_times = 0;
1301
1302 if( efuse_GetCurrentSize(dev) >= EFUSE_MAX_SIZE)
1303 {
1304 printk("efuse_PgPacketWrite error \n");
1305 return FALSE;
1306 }
1307
1308 // Init the 8 bytes content as 0xff
1309 target_pkt.offset = offset;
1310 target_pkt.word_en= word_en;
1311
1312 //PlatformFillMemory((PVOID)target_pkt.data, sizeof(u8)*8, 0xFF);
1313 memset(target_pkt.data,0xFF,sizeof(u8)*8);
1314
1315 efuse_WordEnableDataRead(word_en,data,target_pkt.data);
1316 target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en);
1317
1318 //efuse_reg_ctrl(pAdapter,TRUE);//power on
1319 printk("EFUSE Power ON\n");
1320
1321 while( bContinual && (efuse_addr < EFUSE_MAX_SIZE) )
1322 {
1323
1324 if(WriteState==PG_STATE_HEADER)
1325 {
1326 bDataEmpty=TRUE;
1327 badworden = 0x0F;
1328 //************ so *******************
1329 printk("EFUSE PG_STATE_HEADER\n");
1330 if ( efuse_OneByteRead(dev, efuse_addr ,&efuse_data) &&
1331 (efuse_data!=0xFF))
1332 {
1333 tmp_header = efuse_data;
1334
1335 tmp_pkt.offset = (tmp_header>>4) & 0x0F;
1336 tmp_pkt.word_en = tmp_header & 0x0F;
1337 tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en);
1338
1339 //************ so-1 *******************
1340 if(tmp_pkt.offset != target_pkt.offset)
1341 {
1342 efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
1343 #if (EFUSE_ERROE_HANDLE == 1)
1344 WriteState = PG_STATE_HEADER;
1345 #endif
1346 }
1347 else
1348 {
1349 //************ so-2 *******************
1350 for(tmpindex=0 ; tmpindex<(tmp_word_cnts*2) ; tmpindex++)
1351 {
1352 if(efuse_OneByteRead(dev, (efuse_addr+1+tmpindex) ,&efuse_data)&&(efuse_data != 0xFF)){
1353 bDataEmpty = FALSE;
1354 }
1355 }
1356 //************ so-2-1 *******************
1357 if(bDataEmpty == FALSE)
1358 {
1359 efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
1360 #if (EFUSE_ERROE_HANDLE == 1)
1361 WriteState=PG_STATE_HEADER;
1362 #endif
1363 }
1364 else
1365 {//************ so-2-2 *******************
1366 match_word_en = 0x0F;
1367 if( !( (target_pkt.word_en&BIT0)|(tmp_pkt.word_en&BIT0) ))
1368 {
1369 match_word_en &= (~BIT0);
1370 }
1371 if( !( (target_pkt.word_en&BIT1)|(tmp_pkt.word_en&BIT1) ))
1372 {
1373 match_word_en &= (~BIT1);
1374 }
1375 if( !( (target_pkt.word_en&BIT2)|(tmp_pkt.word_en&BIT2) ))
1376 {
1377 match_word_en &= (~BIT2);
1378 }
1379 if( !( (target_pkt.word_en&BIT3)|(tmp_pkt.word_en&BIT3) ))
1380 {
1381 match_word_en &= (~BIT3);
1382 }
1383
1384 //************ so-2-2-A *******************
1385 if((match_word_en&0x0F)!=0x0F)
1386 {
1387 badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1, tmp_pkt.word_en ,target_pkt.data);
1388
1389 //************ so-2-2-A-1 *******************
1390 //############################
1391 if(0x0F != (badworden&0x0F))
1392 {
1393 u8 reorg_offset = offset;
1394 u8 reorg_worden=badworden;
1395 efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata);
1396 }
1397 //############################
1398
1399 tmp_word_en = 0x0F;
1400 if( (target_pkt.word_en&BIT0)^(match_word_en&BIT0) )
1401 {
1402 tmp_word_en &= (~BIT0);
1403 }
1404 if( (target_pkt.word_en&BIT1)^(match_word_en&BIT1) )
1405 {
1406 tmp_word_en &= (~BIT1);
1407 }
1408 if( (target_pkt.word_en&BIT2)^(match_word_en&BIT2) )
1409 {
1410 tmp_word_en &= (~BIT2);
1411 }
1412 if( (target_pkt.word_en&BIT3)^(match_word_en&BIT3) )
1413 {
1414 tmp_word_en &=(~BIT3);
1415 }
1416
1417 //************ so-2-2-A-2 *******************
1418 if((tmp_word_en&0x0F)!=0x0F){
1419 //reorganize other pg packet
1420 //efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr
1421 efuse_addr = efuse_GetCurrentSize(dev);
1422 //===========================
1423 target_pkt.offset = offset;
1424 target_pkt.word_en= tmp_word_en;
1425 //===========================
1426 }else{
1427 bContinual = FALSE;
1428 }
1429 #if (EFUSE_ERROE_HANDLE == 1)
1430 WriteState=PG_STATE_HEADER;
1431 repeat_times++;
1432 if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
1433 bContinual = FALSE;
1434 bResult = FALSE;
1435 }
1436 #endif
1437 }
1438 else{//************ so-2-2-B *******************
1439 //reorganize other pg packet
1440 efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr
1441 //===========================
1442 target_pkt.offset = offset;
1443 target_pkt.word_en= target_pkt.word_en;
1444 //===========================
1445 #if (EFUSE_ERROE_HANDLE == 1)
1446 WriteState=PG_STATE_HEADER;
1447 #endif
1448 }
1449 }
1450 }
1451 printk("EFUSE PG_STATE_HEADER-1\n");
1452 }
1453 else //************ s1: header == oxff *******************
1454 {
1455 pg_header = ((target_pkt.offset << 4)&0xf0) |target_pkt.word_en;
1456
1457 efuse_OneByteWrite(dev,efuse_addr, pg_header);
1458 efuse_OneByteRead(dev,efuse_addr, &tmp_header);
1459
1460 if(tmp_header == pg_header)
1461 { //************ s1-1*******************
1462 WriteState = PG_STATE_DATA;
1463 }
1464 #if (EFUSE_ERROE_HANDLE == 1)
1465 else if(tmp_header == 0xFF){//************ s1-3: if Write or read func doesn't work *******************
1466 //efuse_addr doesn't change
1467 WriteState = PG_STATE_HEADER;
1468 repeat_times++;
1469 if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
1470 bContinual = FALSE;
1471 bResult = FALSE;
1472 }
1473 }
1474 #endif
1475 else
1476 {//************ s1-2 : fixed the header procedure *******************
1477 tmp_pkt.offset = (tmp_header>>4) & 0x0F;
1478 tmp_pkt.word_en= tmp_header & 0x0F;
1479 tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en);
1480
1481 //************ s1-2-A :cover the exist data *******************
1482 memset(originaldata,0xff,sizeof(u8)*8);
1483 //PlatformFillMemory((PVOID)originaldata, sizeof(u8)*8, 0xff);
1484
1485 if(efuse_PgPacketRead( dev, tmp_pkt.offset,originaldata))
1486 { //check if data exist
1487 //efuse_reg_ctrl(pAdapter,TRUE);//power on
1488 badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,tmp_pkt.word_en,originaldata);
1489 //############################
1490 if(0x0F != (badworden&0x0F))
1491 {
1492 u8 reorg_offset = tmp_pkt.offset;
1493 u8 reorg_worden=badworden;
1494 efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata);
1495 efuse_addr = efuse_GetCurrentSize(dev);
1496 }
1497 //############################
1498 else{
1499 efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
1500 }
1501 }
1502 //************ s1-2-B: wrong address*******************
1503 else
1504 {
1505 efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet
1506 }
1507
1508 #if (EFUSE_ERROE_HANDLE == 1)
1509 WriteState=PG_STATE_HEADER;
1510 repeat_times++;
1511 if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
1512 bContinual = FALSE;
1513 bResult = FALSE;
1514 }
1515 #endif
1516
1517 printk("EFUSE PG_STATE_HEADER-2\n");
1518 }
1519
1520 }
1521
1522 }
1523 //write data state
1524 else if(WriteState==PG_STATE_DATA)
1525 { //************ s1-1 *******************
1526 printk("EFUSE PG_STATE_DATA\n");
1527 badworden = 0x0f;
1528 badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,target_pkt.word_en,target_pkt.data);
1529 if((badworden&0x0F)==0x0F)
1530 { //************ s1-1-A *******************
1531 bContinual = FALSE;
1532 }
1533 else
1534 {//reorganize other pg packet //************ s1-1-B *******************
1535 efuse_addr = efuse_addr + (2*target_word_cnts) +1;//next pg packet addr
1536
1537 //===========================
1538 target_pkt.offset = offset;
1539 target_pkt.word_en= badworden;
1540 target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en);
1541 //===========================
1542 #if (EFUSE_ERROE_HANDLE == 1)
1543 WriteState=PG_STATE_HEADER;
1544 repeat_times++;
1545 if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
1546 bContinual = FALSE;
1547 bResult = FALSE;
1548 }
1549 #endif
1550 printk("EFUSE PG_STATE_HEADER-3\n");
1551 }
1552 }
1553 }
1554
1555 //efuse_reg_ctrl(pAdapter,FALSE);//power off
1556
1557 return TRUE;
1558} // efuse_PgPacketWrite
1559
1560
1561/*-----------------------------------------------------------------------------
1562 * Function: efuse_WordEnableDataRead
1563 *
1564 * Overview: Read allowed word in current efuse section data.
1565 *
1566 * Input: NONE
1567 *
1568 * Output: NONE
1569 *
1570 * Return: NONE
1571 *
1572 * Revised History:
1573 * When Who Remark
1574 * 11/16/2008 MHC Create Version 0.
1575 * 11/21/2008 MHC Fix Write bug when we only enable late word.
1576 *
1577 *---------------------------------------------------------------------------*/
1578static void
1579efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata)
1580{
1581 //u8 tmpindex = 0;
1582
1583 //DbgPrint("efuse_WordEnableDataRead word_en = %x\n", word_en);
1584
1585 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("sourdata\n"), sourdata, 8);
1586 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("targetdata\n"), targetdata, 8);
1587
1588 if (!(word_en&BIT0))
1589 {
1590 targetdata[0] = sourdata[0];//sourdata[tmpindex++];
1591 targetdata[1] = sourdata[1];//sourdata[tmpindex++];
1592 }
1593 if (!(word_en&BIT1))
1594 {
1595 targetdata[2] = sourdata[2];//sourdata[tmpindex++];
1596 targetdata[3] = sourdata[3];//sourdata[tmpindex++];
1597 }
1598 if (!(word_en&BIT2))
1599 {
1600 targetdata[4] = sourdata[4];//sourdata[tmpindex++];
1601 targetdata[5] = sourdata[5];//sourdata[tmpindex++];
1602 }
1603 if (!(word_en&BIT3))
1604 {
1605 targetdata[6] = sourdata[6];//sourdata[tmpindex++];
1606 targetdata[7] = sourdata[7];//sourdata[tmpindex++];
1607 }
1608} // efuse_WordEnableDataRead
1609
1610
1611/*-----------------------------------------------------------------------------
1612 * Function: efuse_WordEnableDataWrite
1613 *
1614 * Overview: Write necessary word unit into current efuse section!
1615 *
1616 * Input: NONE
1617 *
1618 * Output: NONE
1619 *
1620 * Return: NONE
1621 *
1622 * Revised History:
1623 * When Who Remark
1624 * 11/16/2008 MHC Reorganize Efuse operate flow!!.
1625 *
1626 *---------------------------------------------------------------------------*/
1627static u8
1628efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data)
1629{
1630 u16 tmpaddr = 0;
1631 u16 start_addr = efuse_addr;
1632 u8 badworden = 0x0F;
1633 //u8 NextState;
1634 u8 tmpdata[8];
1635
1636 memset(tmpdata,0xff,PGPKT_DATA_SIZE);
1637 //PlatformFillMemory((PVOID)tmpdata, PGPKT_DATA_SIZE, 0xff);
1638
1639 //RT_TRACE(COMP_EFUSE, "word_en = %x efuse_addr=%x\n", word_en, efuse_addr);
1640
1641 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("U-EFUSE\n"), data, 8);
1642
1643 if(!(word_en&BIT0))
1644 {
1645 tmpaddr = start_addr;
1646 efuse_OneByteWrite(dev,start_addr++, data[0]);
1647 efuse_OneByteWrite(dev,start_addr++, data[1]);
1648
1649 efuse_OneByteRead(dev,tmpaddr, &tmpdata[0]);
1650 efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[1]);
1651 if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
1652 badworden &= (~BIT0);
1653 }
1654 }
1655 if(!(word_en&BIT1))
1656 {
1657 tmpaddr = start_addr;
1658 efuse_OneByteWrite(dev,start_addr++, data[2]);
1659 efuse_OneByteWrite(dev,start_addr++, data[3]);
1660
1661 efuse_OneByteRead(dev,tmpaddr , &tmpdata[2]);
1662 efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[3]);
1663 if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
1664 badworden &=( ~BIT1);
1665 }
1666 }
1667 if(!(word_en&BIT2))
1668 {
1669 tmpaddr = start_addr;
1670 efuse_OneByteWrite(dev,start_addr++, data[4]);
1671 efuse_OneByteWrite(dev,start_addr++, data[5]);
1672
1673 efuse_OneByteRead(dev,tmpaddr, &tmpdata[4]);
1674 efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[5]);
1675 if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
1676 badworden &=( ~BIT2);
1677 }
1678 }
1679 if(!(word_en&BIT3))
1680 {
1681 tmpaddr = start_addr;
1682 efuse_OneByteWrite(dev,start_addr++, data[6]);
1683 efuse_OneByteWrite(dev,start_addr++, data[7]);
1684
1685 efuse_OneByteRead(dev,tmpaddr, &tmpdata[6]);
1686 efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[7]);
1687 if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
1688 badworden &=( ~BIT3);
1689 }
1690 }
1691 return badworden;
1692} // efuse_WordEnableDataWrite
1693
1694
1695/*-----------------------------------------------------------------------------
1696 * Function: efuse_PowerSwitch
1697 *
1698 * Overview: When we want to enable write operation, we should change to
1699 * pwr on state. When we stop write, we should switch to 500k mode
1700 * and disable LDO 2.5V.
1701 *
1702 * Input: NONE
1703 *
1704 * Output: NONE
1705 *
1706 * Return: NONE
1707 *
1708 * Revised History:
1709 * When Who Remark
1710 * 11/17/2008 MHC Create Version 0.
1711 *
1712 *---------------------------------------------------------------------------*/
1713static void
1714efuse_PowerSwitch(struct net_device* dev, u8 PwrState)
1715{
1716 u8 tempval;
1717 if (PwrState == TRUE)
1718 {
1719 // Enable LDO 2.5V for write action
1720 tempval = read_nic_byte(dev, EFUSE_TEST+3);
1721 write_nic_byte(dev, EFUSE_TEST+3, (tempval | 0x80));
1722
1723 // Change Efuse Clock for write action to 40MHZ
1724 write_nic_byte(dev, EFUSE_CLK, 0x03);
1725 }
1726 else
1727 {
1728 // Enable LDO 2.5V for write action
1729 tempval = read_nic_byte(dev, EFUSE_TEST+3);
1730 write_nic_byte(dev, EFUSE_TEST+3, (tempval & 0x7F));
1731
1732 // Change Efuse Clock for write action to 500K
1733 write_nic_byte(dev, EFUSE_CLK, 0x02);
1734 }
1735
1736} /* efuse_PowerSwitch */
1737
1738
1739/*-----------------------------------------------------------------------------
1740 * Function: efuse_GetCurrentSize
1741 *
1742 * Overview: Get current efuse size!!!
1743 *
1744 * Input: NONE
1745 *
1746 * Output: NONE
1747 *
1748 * Return: NONE
1749 *
1750 * Revised History:
1751 * When Who Remark
1752 * 11/16/2008 MHC Create Version 0.
1753 *
1754 *---------------------------------------------------------------------------*/
1755static u16
1756efuse_GetCurrentSize(struct net_device* dev)
1757{
1758 bool bContinual = TRUE;
1759
1760 u16 efuse_addr = 0;
1761 u8 hoffset=0,hworden=0;
1762 u8 efuse_data,word_cnts=0;
1763
1764 //efuse_reg_ctrl(pAdapter,TRUE);//power on
1765
1766 while ( bContinual &&
1767 efuse_OneByteRead(dev, efuse_addr ,&efuse_data) &&
1768 (efuse_addr < EFUSE_MAX_SIZE) )
1769 {
1770 if(efuse_data!=0xFF)
1771 {
1772 hoffset = (efuse_data>>4) & 0x0F;
1773 hworden = efuse_data & 0x0F;
1774 word_cnts = efuse_CalculateWordCnts(hworden);
1775 //read next header
1776 efuse_addr = efuse_addr + (word_cnts*2)+1;
1777 }
1778 else
1779 {
1780 bContinual = FALSE ;
1781 }
1782 }
1783
1784 //efuse_reg_ctrl(pAdapter,FALSE);//power off
1785
1786 return efuse_addr;
1787
1788} // efuse_GetCurrentSize}
1789
1790
1791/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */
1792static u8
1793efuse_CalculateWordCnts(u8 word_en)
1794{
1795 u8 word_cnts = 0;
1796 if(!(word_en & BIT0)) word_cnts++; // 0 : write enable
1797 if(!(word_en & BIT1)) word_cnts++;
1798 if(!(word_en & BIT2)) word_cnts++;
1799 if(!(word_en & BIT3)) word_cnts++;
1800 return word_cnts;
1801} // efuse_CalculateWordCnts
1802
1803
1804/*-----------------------------------------------------------------------------
1805 * Function: efuse_ResetLoader
1806 *
1807 * Overview: When read Efuse Fail we must reset loader!!!!
1808 *
1809 * Input: NONE
1810 *
1811 * Output: NONE
1812 *
1813 * Return: NONE
1814 *
1815 * Revised History:
1816 * When Who Remark
1817 * 11/22/2008 MHC Create Version 0.
1818 *
1819 *---------------------------------------------------------------------------*/
1820#if 0
1821static void efuse_ResetLoader(struct net_device* dev)
1822{
1823 u16 tmpU2b;
1824
1825 //
1826 // 2008/11/22 MH Sometimes, we may read efuse fail, for preventing the condition
1827 // We have to reset loader.
1828 //
1829 tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
1830 write_nic_word(dev, SYS_FUNC_EN, (tmpU2b&~(BIT12)));
1831 //PlatformStallExecution(10000); // How long should we delay!!!
1832 mdelay(10);
1833 write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT12));
1834 //PlatformStallExecution(10000); // How long should we delay!!!
1835 mdelay(10);
1836
1837} // efuse_ResetLoader
1838#endif
1839
1840/*-----------------------------------------------------------------------------
1841 * Function: EFUSE_ProgramMap
1842 *
1843 * Overview: Read EFUSE map file and execute PG.
1844 *
1845 * Input: NONE
1846 *
1847 * Output: NONE
1848 *
1849 * Return: NONE
1850 *
1851 * Revised History:
1852 * When Who Remark
1853 * 11/10/2008 MHC Create Version 0.
1854 *
1855 *---------------------------------------------------------------------------*/
1856 #ifdef TO_DO_LIST
1857extern bool // 0=Shadow 1=Real Efuse
1858EFUSE_ProgramMap(struct net_device* dev, char* pFileName,u8 TableType)
1859{
1860 struct r8192_priv *priv = ieee80211_priv(dev);
1861 s4Byte nLinesRead, ithLine;
1862 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1863 char* szLine;
1864 u32 u4bRegValue, u4RegMask;
1865 u32 u4bMove;
1866 u16 index = 0;
1867 u16 i;
1868 u8 eeprom[HWSET_MAX_SIZE_92S];
1869
1870 rtStatus = PlatformReadFile(
1871 dev,
1872 pFileName,
1873 (u8*)(priv->BufOfLines),
1874 MAX_LINES_HWCONFIG_TXT,
1875 MAX_BYTES_LINE_HWCONFIG_TXT,
1876 &nLinesRead
1877 );
1878
1879 if(rtStatus == RT_STATUS_SUCCESS)
1880 {
1881 memcp(pHalData->BufOfLines3, pHalData->BufOfLines,
1882 nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
1883 pHalData->nLinesRead3 = nLinesRead;
1884 }
1885
1886 if(rtStatus == RT_STATUS_SUCCESS)
1887 {
1888 printk("szEepromFile(): read %s ok\n", pFileName);
1889 for(ithLine = 0; ithLine < nLinesRead; ithLine++)
1890 {
1891 szLine = pHalData->BufOfLines[ithLine];
1892 printk("Line-%d String =%s\n", ithLine, szLine);
1893
1894 if(!IsCommentString(szLine))
1895 {
1896 // EEPROM map one line has 8 words content.
1897 for (i = 0; i < 8; i++)
1898 {
1899 u32 j;
1900
1901 //GetHexValueFromString(szLine, &u4bRegValue, &u4bMove);
1902 efuse_ParsingMap(szLine, &u4bRegValue, &u4bMove);
1903
1904 // Get next hex value as EEPROM value.
1905 szLine += u4bMove;
1906 //WriteEEprom(dev, (u16)(ithLine*8+i), (u16)u4bRegValue);
1907 eeprom[index++] = (u8)(u4bRegValue&0xff);
1908 eeprom[index++] = (u8)((u4bRegValue>>8)&0xff);
1909
1910 printk("Addr-%d = %x\n", (ithLine*8+i), u4bRegValue);
1911 }
1912 }
1913
1914 }
1915
1916 }
1917 else
1918 {
1919 printk("szEepromFile(): Fail read%s\n", pFileName);
1920 return RT_STATUS_FAILURE;
1921 }
1922
1923
1924 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("EFUSE "), eeprom, HWSET_MAX_SIZE_92S);
1925
1926 // Use map file to update real Efuse or shadow modify table.
1927 if (TableType == 1)
1928 {
1929 efuse_WriteAllMap(dev, eeprom, HWSET_MAX_SIZE_92S);
1930 }
1931 else
1932 {
1933 // Modify shadow table.
1934 for (i = 0; i < HWSET_MAX_SIZE_92S; i++)
1935 EFUSE_ShadowWrite(dev, 1, i, (u32)eeprom[i]);
1936 }
1937
1938 return rtStatus;
1939} /* EFUSE_ProgramMap */
1940
1941#endif
1942
1943//
1944// Description:
1945// Return TRUE if chTmp is represent for hex digit and
1946// FALSE otherwise.
1947//
1948//
1949bool IsHexDigit( char chTmp)
1950{
1951 if( (chTmp >= '0' && chTmp <= '9') ||
1952 (chTmp >= 'a' && chTmp <= 'f') ||
1953 (chTmp >= 'A' && chTmp <= 'F') )
1954 {
1955 return TRUE;
1956 }
1957 else
1958 {
1959 return FALSE;
1960 }
1961}
1962
1963//
1964// Description:
1965// Translate a character to hex digit.
1966//
1967u32 MapCharToHexDigit(char chTmp)
1968{
1969 if(chTmp >= '0' && chTmp <= '9')
1970 return (chTmp - '0');
1971 else if(chTmp >= 'a' && chTmp <= 'f')
1972 return (10 + (chTmp - 'a'));
1973 else if(chTmp >= 'A' && chTmp <= 'F')
1974 return (10 + (chTmp - 'A'));
1975 else
1976 return 0;
1977}
1978
1979/*-----------------------------------------------------------------------------
1980 * Function: efuse_ParsingMap
1981 *
1982 * Overview:
1983 *
1984 * Input: NONE
1985 *
1986 * Output: NONE
1987 *
1988 * Return: NONE
1989 *
1990 * Revised History:
1991 * When Who Remark
1992 * 11/08/2008 MHC Create Version 0.
1993 *
1994 *---------------------------------------------------------------------------*/
1995#ifdef TO_DO_LIST
1996static bool
1997efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove)
1998{
1999 char* szScan = szStr;
2000
2001 // Check input parameter.
2002 if(szStr == NULL || pu4bVal == NULL || pu4bMove == NULL)
2003 {
2004 //RT_TRACE(COMP_EFUSE,
2005 //"eeprom_ParsingMap(): Invalid IN args! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
2006 //szStr, pu4bVal, pu4bMove);
2007 return FALSE;
2008 }
2009
2010 // Initialize output.
2011 *pu4bMove = 0;
2012 *pu4bVal = 0;
2013
2014 // Skip leading space.
2015 while( *szScan != '\0' &&
2016 (*szScan == ' ' || *szScan == '\t') )
2017 {
2018 szScan++;
2019 (*pu4bMove)++;
2020 }
2021
2022 // Check if szScan is now pointer to a character for hex digit,
2023 // if not, it means this is not a valid hex number.
2024 if(!IsHexDigit(*szScan))
2025 {
2026 return FALSE;
2027 }
2028
2029 // Parse each digit.
2030 do
2031 {
2032 (*pu4bVal) <<= 4;
2033 *pu4bVal += MapCharToHexDigit(*szScan);
2034
2035 szScan++;
2036 (*pu4bMove)++;
2037 } while(IsHexDigit(*szScan));
2038
2039 return TRUE;
2040
2041} /* efuse_ParsingMap */
2042#endif
2043
2044//
2045// Useless Section Code Now!!!!!!
2046//
2047// Porting from 8712 SDIO
2048int efuse_one_byte_rw(struct net_device* dev, u8 bRead, u16 addr, u8 *data)
2049{
2050 u32 bResult;
2051 //u8 efuse_ctlreg,tmpidx = 0;
2052 u8 tmpidx = 0;
2053 u8 tmpv8=0;
2054
2055 // -----------------e-fuse reg ctrl ---------------------------------
2056
2057 write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff)); //address
2058 tmpv8 = ((u8)((addr>>8) &0x03) ) | (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC );
2059 write_nic_byte(dev, EFUSE_CTRL+2, tmpv8);
2060
2061 if(TRUE==bRead){
2062
2063 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);//read cmd
2064
2065 while(!(0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
2066 tmpidx++;
2067 }
2068 if(tmpidx<100){
2069 *data=read_nic_byte(dev, EFUSE_CTRL);
2070 bResult = TRUE;
2071 }
2072 else
2073 {
2074 *data = 0;
2075 bResult = FALSE;
2076 }
2077
2078 }
2079 else{
2080 //return 0;
2081 write_nic_byte(dev, EFUSE_CTRL, *data);//data
2082
2083 write_nic_byte(dev, EFUSE_CTRL+3, 0xF2);//write cmd
2084
2085 while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
2086 tmpidx++;
2087 }
2088 if(tmpidx<100)
2089 {
2090 *data=read_nic_byte(dev, EFUSE_CTRL);
2091 bResult = TRUE;
2092 }
2093 else
2094 {
2095 *data = 0;
2096 bResult = FALSE;
2097 }
2098
2099 }
2100 return bResult;
2101}
2102//------------------------------------------------------------------------------
2103void efuse_access(struct net_device* dev, u8 bRead,u16 start_addr, u8 cnts, u8 *data)
2104{
2105 u8 efuse_clk_ori,efuse_clk_new;//,tmp8;
2106 u32 i = 0;
2107
2108 if(start_addr>0x200) return;
2109 //RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,
2110 // ("\n ===> efuse_access [start_addr=0x%x cnts:%d dataarray:0x%08x Query Efuse].\n",start_addr,cnts,data));
2111 // -----------------SYS_FUNC_EN Digital Core Vdd enable ---------------------------------
2112 efuse_clk_ori = read_nic_byte(dev,SYS_FUNC_EN+1);
2113 efuse_clk_new = efuse_clk_ori|0x20;
2114
2115 if(efuse_clk_new!= efuse_clk_ori){
2116 //RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
2117 write_nic_byte(dev, SYS_FUNC_EN+1, efuse_clk_new);
2118 }
2119#ifdef _POWERON_DELAY_
2120 mdelay(10);
2121#endif
2122 // -----------------e-fuse pwr & clk reg ctrl ---------------------------------
2123 write_nic_byte(dev, EFUSE_TEST+3, (read_nic_byte(dev, EFUSE_TEST+3)|0x80));
2124 write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03));
2125
2126#ifdef _PRE_EXECUTE_READ_CMD_
2127 {
2128 unsigned char tmpdata;
2129 efuse_OneByteRead(dev, 0,&tmpdata);
2130 }
2131#endif
2132
2133 //-----------------e-fuse one byte read / write ------------------------------
2134 for(i=0;i<cnts;i++){
2135 efuse_one_byte_rw(dev,bRead, start_addr+i , data+i);
2136 ////RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("==>efuse_access addr:0x%02x value:0x%02x\n",data+i,*(data+i)));
2137 }
2138 // -----------------e-fuse pwr & clk reg ctrl ---------------------------------
2139 write_nic_byte(dev, EFUSE_TEST+3, read_nic_byte(dev, EFUSE_TEST+3)&0x7f);
2140 write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd);
2141
2142 // -----------------SYS_FUNC_EN Digital Core Vdd disable ---------------------------------
2143 if(efuse_clk_new != efuse_clk_ori) write_nic_byte(dev, 0x10250003, efuse_clk_ori);
2144
2145}
2146//------------------------------------------------------------------------------
2147//------------------------------------------------------------------------------
2148
2149#ifdef TO_DO_LIST
2150static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn)
2151{
2152 if(TRUE==bPowerOn){
2153 // -----------------SYS_FUNC_EN Digital Core Vdd enable ---------------------------------
2154 write_nic_byte(dev, SYS_FUNC_EN+1, read_nic_byte(dev,SYS_FUNC_EN+1)|0x20);
2155#ifdef _POWERON_DELAY_
2156 mdelay(10);
2157#endif
2158 // -----------------e-fuse pwr & clk reg ctrl ---------------------------------
2159 write_nic_byte(dev, EFUSE_TEST+4, (read_nic_byte(dev, EFUSE_TEST+4)|0x80));
2160 write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03));
2161#ifdef _PRE_EXECUTE_READ_CMD_
2162 {
2163 unsigned char tmpdata;
2164 efuse_OneByteRead(dev, 0,&tmpdata);
2165 }
2166
2167#endif
2168 }
2169 else{
2170 // -----------------e-fuse pwr & clk reg ctrl ---------------------------------
2171 write_nic_byte(dev, EFUSE_TEST+4, read_nic_byte(dev, EFUSE_TEST+4)&0x7f);
2172 write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd);
2173 // -----------------SYS_FUNC_EN Digital Core Vdd disable ---------------------------------
2174
2175 //write_nic_byte(pAdapter, SYS_FUNC_EN+1, read_nic_byte(pAdapter,SYS_FUNC_EN+1)&0xDF);
2176 }
2177
2178
2179}
2180#endif
2181//------------------------------------------------------------------------------
2182
2183//------------------------------------------------------------------------------
2184void efuse_read_data(struct net_device* dev,u8 efuse_read_item,u8 *data,u32 data_size)
2185{
2186 u8 offset, word_start,byte_start,byte_cnts;
2187 u8 efusedata[EFUSE_MAC_LEN];
2188 u8 *tmpdata = NULL;
2189
2190 u8 pg_pkt_cnts ;
2191
2192 u8 tmpidx;
2193 u8 pg_data[8];
2194 //u8 temp_value[8] = {0xff};
2195
2196 if(efuse_read_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){
2197 //error msg
2198 return ;
2199 }
2200
2201 offset = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].offset ;
2202 word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].word_start;
2203 byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_start;
2204 byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_cnts;
2205
2206 if(data_size!=byte_cnts){
2207 //error msg
2208 return;
2209 }
2210
2211 pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1;
2212
2213 if(pg_pkt_cnts > 1){
2214 //tmpdata = _malloc(pg_pkt_cnts*PGPKT_DATA_SIZE);
2215 tmpdata = efusedata;
2216
2217 if(tmpdata!=NULL)
2218 {
2219 memset(tmpdata,0xff,pg_pkt_cnts*PGPKT_DATA_SIZE);
2220 //PlatformFillMemory((PVOID)pg_data, pg_pkt_cnts*PGPKT_DATA_SIZE, 0xff);
2221
2222 for(tmpidx=0;tmpidx<pg_pkt_cnts;tmpidx++)
2223 {
2224 memset(pg_data,0xff,PGPKT_DATA_SIZE);
2225 //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff);
2226 if(TRUE== efuse_PgPacketRead(dev,offset+tmpidx,pg_data))
2227 {
2228 memcpy(tmpdata+(PGPKT_DATA_SIZE*tmpidx),pg_data,PGPKT_DATA_SIZE);
2229 //PlatformMoveMemory((PVOID)(tmpdata+(PGPKT_DATA_SIZE*tmpidx)), (PVOID)pg_data, PGPKT_DATA_SIZE);
2230 }
2231 }
2232 memcpy(data,(tmpdata+ (2*word_start)+byte_start ),data_size);
2233 //PlatformMoveMemory((PVOID)data, (PVOID)(tmpdata+ (2*word_start)+byte_start ), data_size);
2234 //_mfree(tmpdata, pg_pkt_cnts*PGPKT_DATA_SIZE);
2235 }
2236 }
2237 else
2238 {
2239 memset(pg_data,0xff,PGPKT_DATA_SIZE);
2240 //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff);
2241 if(TRUE==efuse_PgPacketRead(dev,offset,pg_data)){
2242 memcpy(data,pg_data+ (2*word_start)+byte_start ,data_size);
2243 //PlatformMoveMemory((PVOID)data, (PVOID)(pg_data+ (2*word_start)+byte_start), data_size);
2244 }
2245 }
2246
2247}
2248//------------------------------------------------------------------------------
2249//per interface doesn't alike
2250void efuse_write_data(struct net_device* dev,u8 efuse_write_item,u8 *data,u32 data_size,u32 bWordUnit)
2251{
2252 u8 offset, word_start,byte_start,byte_cnts;
2253 u8 word_en = 0x0f,word_cnts;
2254 u8 pg_pkt_cnts ;
2255
2256 u8 tmpidx,tmpbitmask;
2257 u8 pg_data[8],tmpbytes=0;
2258
2259 if(efuse_write_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){
2260 //error msg
2261 return ;
2262 }
2263
2264 offset = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].offset ;
2265 word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].word_start;
2266 byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_start;
2267 byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_cnts;
2268
2269 if(data_size > byte_cnts){
2270 //error msg
2271 return;
2272 }
2273 pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1;
2274 word_cnts = byte_cnts /2 ;
2275
2276 if(byte_cnts %2){
2277 word_cnts+=1;
2278 }
2279 if((byte_start==1)||((byte_cnts%2)==1)){//situation A
2280
2281 if((efuse_write_item==EFUSE_F0CIS)||(efuse_write_item==EFUSE_F1CIS)){
2282 memset(pg_data,0xff,PGPKT_DATA_SIZE);
2283 //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff);
2284 efuse_PgPacketRead(dev,offset,pg_data);
2285
2286 if(efuse_write_item==EFUSE_F0CIS){
2287 word_en = 0x07;
2288 memcpy(pg_data+word_start*2+byte_start,data,sizeof(u8)*2);
2289 //PlatformMoveMemory((PVOID)(pg_data+word_start*2+byte_start), (PVOID)data, sizeof(u8)*2);
2290 efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
2291
2292 word_en = 0x00;
2293 efuse_PgPacketWrite(dev,(offset+1),word_en,data+2);
2294
2295 word_en = 0x00;
2296 efuse_PgPacketRead(dev,offset+2,pg_data);
2297 memcpy(pg_data,data+2+8,sizeof(u8)*7);
2298 //PlatformMoveMemory((PVOID)(pg_data), (PVOID)(data+2+8), sizeof(u8)*7);
2299
2300 efuse_PgPacketWrite(dev,(offset+2),word_en,pg_data);
2301 }
2302 else if(efuse_write_item==EFUSE_F1CIS){
2303 word_en = 0x07;
2304 efuse_PgPacketRead(dev,offset,pg_data);
2305 pg_data[7] = data[0];
2306 efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
2307
2308 word_en = 0x00;
2309 for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++){
2310 efuse_PgPacketWrite(dev,(offset+1+tmpidx),word_en,data+1+(tmpidx*PGPKT_DATA_SIZE));
2311 }
2312 }
2313
2314 }
2315 else{
2316 memset(pg_data,0xff,PGPKT_DATA_SIZE);
2317 //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff);
2318 if((efuse_write_item==EFUSE_SDIO_SETTING)||(efuse_write_item==EFUSE_CCCR)){
2319 word_en = 0x0e ;
2320 tmpbytes = 2;
2321 }
2322 else if(efuse_write_item == EFUSE_SDIO_MODE){
2323 word_en = 0x0d ;
2324 tmpbytes = 2;
2325 }
2326 else if(efuse_write_item == EFUSE_OCR){
2327 word_en = 0x09 ;
2328 tmpbytes = 4;
2329 }
2330 else if((efuse_write_item == EFUSE_EEPROM_VER)||(efuse_write_item==EFUSE_CHAN_PLAN)){
2331 word_en = 0x07 ;
2332 tmpbytes = 2;
2333 }
2334 if(bWordUnit==TRUE){
2335 memcpy(pg_data+word_start*2 ,data,sizeof(u8)*tmpbytes);
2336 //PlatformMoveMemory((PVOID)(pg_data+word_start*2), (PVOID)(data), sizeof(u8)*tmpbytes);
2337 }
2338 else{
2339 efuse_PgPacketRead(dev,offset,pg_data);
2340 memcpy(pg_data+(2*word_start)+byte_start,data,sizeof(u8)*byte_cnts);
2341 //PlatformMoveMemory((PVOID)(pg_data+(2*word_start)+byte_start), (PVOID)(data), sizeof(u8)*byte_cnts);
2342 }
2343
2344 efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
2345
2346 }
2347
2348 }
2349 //========================================================================
2350 else if(pg_pkt_cnts>1){//situation B
2351 if(word_start==0){
2352 word_en = 0x00;
2353 for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++)
2354 {
2355 efuse_PgPacketWrite(dev,(offset+tmpidx),word_en,data+(tmpidx*PGPKT_DATA_SIZE));
2356 }
2357 word_en = 0x0f;
2358 for(tmpidx= 0; tmpidx<(word_cnts%4) ; tmpidx++)
2359 {
2360 tmpbitmask =tmpidx;
2361 word_en &= (~(EFUSE_BIT(tmpbitmask)));
2362 //BIT0
2363 }
2364 efuse_PgPacketWrite(dev,offset+(word_cnts/4),word_en,data+((word_cnts/4)*PGPKT_DATA_SIZE));
2365 }else
2366 {
2367
2368 }
2369 }
2370 //========================================================================
2371 else{//situation C
2372 word_en = 0x0f;
2373 for(tmpidx= 0; tmpidx<word_cnts ; tmpidx++)
2374 {
2375 tmpbitmask = word_start + tmpidx ;
2376 word_en &= (~(EFUSE_BIT(tmpbitmask)));
2377 }
2378 efuse_PgPacketWrite(dev,offset,word_en,data);
2379 }
2380
2381}
2382//------------------------------------------------------------------------------
2383
2384void efuset_test_func_read(struct net_device* dev)
2385{
2386 u8 chipid[2];
2387 u8 ocr[3];
2388 u8 macaddr[6];
2389 u8 txpowertable[28];
2390
2391 memset(chipid,0,sizeof(u8)*2);
2392 efuse_read_data(dev,EFUSE_CHIP_ID,chipid,sizeof(chipid));
2393
2394 memset(ocr,0,sizeof(u8)*3);
2395 efuse_read_data(dev,EFUSE_CCCR,ocr,sizeof(ocr));
2396
2397 memset(macaddr,0,sizeof(u8)*6);
2398 efuse_read_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr));
2399
2400 memset(txpowertable,0,sizeof(u8)*28);
2401 efuse_read_data(dev,EFUSE_TXPW_TAB,txpowertable,sizeof(txpowertable));
2402}
2403//------------------------------------------------------------------------------
2404
2405void efuset_test_func_write(struct net_device* dev)
2406{
2407 u32 bWordUnit = TRUE;
2408 u8 CCCR=0x02,SDIO_SETTING = 0xFF;
2409 u8 tmpdata[2];
2410
2411 u8 macaddr[6] = {0x00,0xe0,0x4c,0x87,0x12,0x66};
2412 efuse_write_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr),bWordUnit);
2413
2414 bWordUnit = FALSE;
2415 efuse_write_data(dev,EFUSE_CCCR,&CCCR,sizeof(u8),bWordUnit);
2416
2417 bWordUnit = FALSE;
2418 efuse_write_data(dev,EFUSE_SDIO_SETTING,&SDIO_SETTING,sizeof(u8),bWordUnit);
2419
2420 bWordUnit = TRUE;
2421 tmpdata[0] =SDIO_SETTING ;
2422 tmpdata[1] =CCCR ;
2423 efuse_write_data(dev,EFUSE_SDIO_SETTING,tmpdata,sizeof(tmpdata),bWordUnit);
2424
2425}
2426//------------------------------------------------------------------------------
2427
2428
2429
2430
2431#endif // #if (HAL_CODE_BASE == RTL8192_S)
2432
2433
2434
2435
2436
2437
2438/* End of Efuse.c */
2439
2440
2441
2442
diff --git a/drivers/staging/rtl8192su/r8192S_Efuse.h b/drivers/staging/rtl8192su/r8192S_Efuse.h
new file mode 100644
index 00000000000..1e50153ba02
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_Efuse.h
@@ -0,0 +1,101 @@
1/******************************************************************************
2 *
3 * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4 *
5 * Module: Efuse.h ( Header File)
6 *
7 * Note:
8 *
9 * Function:
10 *
11 * Export:
12 *
13 * Abbrev:
14 *
15 * History:
16 * Data Who Remark
17 *
18 * 09/23/2008 MHC Porting Efuse R/W API from WMAC.
19 * 11/10/2008 MHC Porting Efuse.h from 8712 SDIO.
20 * 1. We muse redefine the header file to fit our coding
21 * style.
22 * 2. THe API we export to other module, we must redefine
23 * for 8192S series.
24 *
25 *
26******************************************************************************/
27/* Check to see if the file has been included already. */
28
29#ifndef __INC_EFUSE_H
30#define __INC_EFUSE_H
31
32// Roger porting for 8192SU
33#define EFUSE_FOR_92SU 1
34
35/*--------------------------Define Parameters-------------------------------*/
36#define EFUSE_MAC_LEN 0x200
37
38#define EFUSE_INIT_MAP 0
39#define EFUSE_MODIFY_MAP 1
40
41#define EFUSE_CLK_CTRL EFUSE_CTRL
42#define EFUSE_BIT(x) (1 << (x))
43
44// From 8712!!!!!!!!
45#define PG_STATE_HEADER 0x01
46#define PG_STATE_WORD_0 0x02
47#define PG_STATE_WORD_1 0x04
48#define PG_STATE_WORD_2 0x08
49#define PG_STATE_WORD_3 0x10
50#define PG_STATE_DATA 0x20
51
52#define PG_SWBYTE_H 0x01
53#define PG_SWBYTE_L 0x02
54
55/*--------------------------Define Parameters-------------------------------*/
56
57
58/*------------------------------Define structure----------------------------*/
59
60/*------------------------------Define structure----------------------------*/
61
62
63/*------------------------Export global variable----------------------------*/
64/*------------------------Export global variable----------------------------*/
65
66/*------------------------Export Marco Definition---------------------------*/
67
68/*------------------------Export Marco Definition---------------------------*/
69
70
71/*--------------------------Exported Function prototype---------------------*/
72extern void
73EFUSE_Initialize(struct net_device* dev);
74extern u8
75EFUSE_Read1Byte(struct net_device* dev,u16 Address);
76extern void
77EFUSE_Write1Byte(struct net_device* dev,u16 Address,u8 Value);
78
79#ifdef EFUSE_FOR_92SU
80extern void
81ReadEFuse(struct net_device* dev,u16 _offset,u16 _size_byte,u8* pbuf);
82extern void
83ReadEFuseByte(struct net_device* dev,u16 _offset,u8 *pbuf);
84#endif // #if (EFUSE_FOR_92SU == 1)
85
86extern void
87EFUSE_ShadowRead(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 *Value);
88extern void
89EFUSE_ShadowWrite(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 Value);
90extern void
91EFUSE_ShadowUpdate(struct net_device* dev);
92extern void
93EFUSE_ShadowMapUpdate(struct net_device* dev);
94
95extern bool
96EFUSE_ProgramMap(struct net_device* dev,char* pFileName, u8 TableType); // 0=Shadow 1=Real Efuse
97/*--------------------------Exported Function prototype---------------------*/
98
99/* End of Efuse.h */
100
101#endif //__INC_EFUSE_H
diff --git a/drivers/staging/rtl8192su/r8192S_FwImgDTM.h b/drivers/staging/rtl8192su/r8192S_FwImgDTM.h
new file mode 100644
index 00000000000..afced75271b
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_FwImgDTM.h
@@ -0,0 +1,3797 @@
1#ifndef HAL8192PciE_FW_IMG_DTM_H
2#define HAL8192PciE_FW_IMG_DTM_H
3
4/*Created on 2008/ 3/11, 8:34*/
5#include <linux/types.h>
6
7#define MACPHY_ArrayLengthDTM 18
8#define MACPHY_Array_PGLengthDTM 30
9#define AGCTAB_ArrayLengthDTM 384
10#define AGCTAB_ArrayLength 384
11
12#define BootArrayLengthDTM 344
13u8 Rtl8192PciEFwBootArrayDTM[BootArrayLengthDTM] = {
140x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08,
150x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00,
160x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
170x25,0x08,0xbc,0xf0,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,
180x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b,
190x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00,
200x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
210x25,0x08,0xbc,0xf0,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0,
220x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00,
230x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,
240x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,
250x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,
260x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01,
270x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24,
280x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00,
290x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10,
300x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
310x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,
320x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
330x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10,
340xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x5f,0x84,
350x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,};
36
37#define MainArrayLengthDTM 48368
38u8 Rtl8192PciEFwMainArrayDTM[MainArrayLengthDTM] = {
390x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
400x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
410x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
420x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
430x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
440x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
450x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
460x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
470x40,0x04,0x68,0x00,0x40,0x05,0x70,0x00,0x40,0x06,0x40,0x00,0x0c,0x00,0x17,0x50,
480x00,0x00,0x00,0x00,0x40,0x1a,0x68,0x00,0x33,0x5b,0x00,0x3c,0x17,0x60,0x00,0x09,
490x00,0x00,0x00,0x00,0x40,0x1b,0x60,0x00,0x00,0x00,0x00,0x00,0x03,0x5b,0xd0,0x24,
500x40,0x1a,0x70,0x00,0x03,0x40,0x00,0x08,0x42,0x00,0x00,0x10,0x00,0x00,0x00,0x00,
510x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0xff,0xff,0x8c,0x43,0x00,0x00,
520x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x00,0xd0,
530xac,0x62,0x00,0x00,0x00,0x00,0x20,0x21,0x27,0x85,0x91,0x50,0x00,0x85,0x18,0x21,
540x24,0x84,0x00,0x01,0x28,0x82,0x00,0x0a,0x14,0x40,0xff,0xfc,0xa0,0x60,0x00,0x00,
550x27,0x82,0x91,0x5a,0x24,0x04,0x00,0x06,0x24,0x84,0xff,0xff,0xa4,0x40,0x00,0x00,
560x04,0x81,0xff,0xfd,0x24,0x42,0x00,0x02,0x24,0x02,0x00,0x03,0xa3,0x82,0x91,0x50,
570x24,0x02,0x00,0x0a,0x24,0x03,0x09,0xc4,0xa3,0x82,0x91,0x52,0x24,0x02,0x00,0x04,
580x24,0x04,0x00,0x01,0x24,0x05,0x00,0x02,0xa7,0x83,0x91,0x66,0xa3,0x82,0x91,0x58,
590x24,0x03,0x04,0x00,0x24,0x02,0x02,0x00,0xaf,0x83,0x91,0x6c,0xa3,0x85,0x91,0x59,
600xa7,0x82,0x91,0x5a,0xa7,0x84,0x91,0x5c,0xaf,0x84,0x91,0x68,0xa3,0x84,0x91,0x51,
610xa3,0x80,0x91,0x53,0xa3,0x80,0x91,0x54,0xa3,0x80,0x91,0x55,0xa3,0x84,0x91,0x56,
620xa3,0x85,0x91,0x57,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
630x3c,0x02,0x80,0x00,0x24,0x42,0x01,0x7c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,
640x27,0x84,0x91,0x78,0x00,0x00,0x10,0x21,0x24,0x42,0x00,0x01,0x00,0x02,0x16,0x00,
650x00,0x02,0x16,0x03,0x28,0x43,0x00,0x03,0xac,0x80,0xff,0xfc,0xa0,0x80,0x00,0x00,
660x14,0x60,0xff,0xf9,0x24,0x84,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
670x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x01,0xc0,
680x3c,0x08,0xb0,0x03,0xac,0x62,0x00,0x00,0x35,0x08,0x00,0x70,0x8d,0x02,0x00,0x00,
690x00,0xa0,0x48,0x21,0x00,0x04,0x26,0x00,0x00,0x02,0x2a,0x43,0x00,0x06,0x36,0x00,
700x00,0x07,0x3e,0x00,0x00,0x02,0x12,0x03,0x29,0x23,0x00,0x03,0x00,0x04,0x56,0x03,
710x00,0x06,0x36,0x03,0x00,0x07,0x3e,0x03,0x30,0x48,0x00,0x01,0x10,0x60,0x00,0x11,
720x30,0xa5,0x00,0x07,0x24,0x02,0x00,0x02,0x00,0x49,0x10,0x23,0x00,0x45,0x10,0x07,
730x30,0x42,0x00,0x01,0x10,0x40,0x00,0x66,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x10,
740x00,0x00,0x00,0x00,0x00,0x02,0x21,0x43,0x11,0x00,0x00,0x10,0x00,0x07,0x20,0x0b,
750x15,0x20,0x00,0x06,0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x05,0x34,0x42,0x01,0x20,
760xa4,0x44,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x11,0x22,0x00,0x04,
770x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x24,
780x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x22,0x15,0x20,0x00,0x54,
790x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x74,0x90,0x43,0x00,0x00,
800x00,0x00,0x00,0x00,0xaf,0x83,0x91,0x74,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x70,
810x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x6b,0x00,0x08,0x11,0x60,0x00,0x18,
820x00,0x09,0x28,0x40,0x00,0x00,0x40,0x21,0x27,0x85,0x91,0x70,0x8c,0xa3,0x00,0x00,
830x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x62,0x38,0x23,0x00,0x43,0x10,0x2a,
840x10,0x40,0x00,0x3d,0x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x25,0x02,0x00,0x01,
850x00,0x02,0x16,0x00,0x00,0x02,0x46,0x03,0x29,0x03,0x00,0x03,0x14,0x60,0xff,0xf3,
860x24,0xa5,0x00,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x70,0x90,0x62,0x00,0x00,
870x00,0x00,0x00,0x00,0x00,0x4b,0x10,0x23,0xa0,0x62,0x00,0x00,0x00,0x09,0x28,0x40,
880x00,0xa9,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x91,0x78,0x00,0x0a,0x20,0x0b,
890x00,0x43,0x18,0x21,0x10,0xc0,0x00,0x05,0x00,0x00,0x38,0x21,0x80,0x62,0x00,0x01,
900x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x80,0x62,0x00,0x00,
910x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0xa9,0x10,0x21,0x24,0x07,0x00,0x01,
920x00,0xa9,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x91,0x78,0xa0,0x67,0x00,0x01,
930x00,0xc2,0x38,0x21,0x80,0xe3,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x07,
940x00,0x00,0x00,0x00,0x27,0x83,0x91,0x70,0x00,0xc3,0x18,0x21,0x8c,0x62,0x00,0x00,
950x00,0x00,0x00,0x00,0x00,0x44,0x10,0x21,0xac,0x62,0x00,0x00,0x27,0x85,0x91,0x74,
960x27,0x82,0x91,0x70,0x00,0xc5,0x28,0x21,0x00,0xc2,0x10,0x21,0x8c,0x43,0x00,0x00,
970x8c,0xa4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x2a,0x14,0x60,0x00,0x03,
980x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xe2,0x00,0x00,0xa0,0xe0,0x00,0x00,
990x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0xb7,0xac,0xa0,0x00,0x00,
1000x11,0x22,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x7c,
1010x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x91,0x8c,0x08,0x00,0x00,0xa7,
1020x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x78,0x90,0x43,0x00,0x00,
1030x00,0x00,0x00,0x00,0xaf,0x83,0x91,0x80,0x08,0x00,0x00,0xa7,0x3c,0x02,0xb0,0x03,
1040x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x04,0x10,
1050x3c,0x05,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0xa5,0x00,0x70,0x8c,0xa2,0x00,0x00,
1060x90,0x84,0x00,0x08,0x3c,0x06,0xb0,0x03,0x00,0x02,0x16,0x00,0x2c,0x83,0x00,0x03,
1070x34,0xc6,0x00,0x72,0x24,0x07,0x00,0x01,0x10,0x60,0x00,0x11,0x00,0x02,0x2f,0xc2,
1080x90,0xc2,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x02,0x16,0x00,0x10,0xa7,0x00,0x09,
1090x00,0x02,0x16,0x03,0x14,0x80,0x00,0x0c,0x30,0x43,0x00,0x03,0x83,0x82,0x91,0x78,
1100x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x16,0x00,
1110x00,0x02,0x1e,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x72,0xa0,0x43,0x00,0x00,
1120x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x45,0x00,0x05,0x10,0x87,0x00,0x04,
1130x30,0x43,0x00,0x06,0x93,0x82,0x91,0x90,0x08,0x00,0x01,0x1f,0x00,0x43,0x10,0x21,
1140x83,0x82,0x91,0x84,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x40,0x08,0x00,0x01,0x1f,
1150x00,0x45,0x10,0x21,0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,
1160x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
1170x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x04,0xe4,
1180x3c,0x04,0xb0,0x02,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x08,
1190x24,0x02,0x00,0x01,0xaf,0x84,0x91,0xa0,0xa3,0x82,0x91,0xb0,0xa7,0x80,0x91,0xa4,
1200xa7,0x80,0x91,0xa6,0xaf,0x80,0x91,0xa8,0xaf,0x80,0x91,0xac,0x03,0xe0,0x00,0x08,
1210x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
1220x24,0x42,0x05,0x24,0x27,0xbd,0xff,0xe0,0xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x14,
1230xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21,0xaf,0xbf,0x00,0x18,0x0c,0x00,0x01,0xe3,
1240x00,0x80,0x80,0x21,0x02,0x00,0x20,0x21,0x10,0x40,0x00,0x05,0x02,0x20,0x28,0x21,
1250x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
1260x0c,0x00,0x01,0xf9,0x00,0x00,0x00,0x00,0x08,0x00,0x01,0x58,0x00,0x00,0x00,0x00,
1270x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x05,0x80,
1280x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
1290xaf,0xbf,0x00,0x18,0x8f,0x90,0x91,0xa0,0x0c,0x00,0x01,0xe3,0x00,0x80,0x88,0x21,
1300x14,0x40,0x00,0x2a,0x3c,0x02,0x00,0x80,0x16,0x20,0x00,0x02,0x34,0x42,0x02,0x01,
1310x24,0x02,0x02,0x01,0xae,0x02,0x00,0x00,0x97,0x84,0x91,0xa4,0x97,0x82,0x91,0xa6,
1320x3c,0x03,0xb0,0x02,0x00,0x83,0x20,0x21,0x24,0x42,0x00,0x04,0xa7,0x82,0x91,0xa6,
1330xa4,0x82,0x00,0x00,0x8f,0x84,0x91,0xa8,0x8f,0x82,0x91,0xa0,0x93,0x85,0x91,0x52,
1340x24,0x84,0x00,0x01,0x24,0x42,0x00,0x04,0x24,0x03,0x8f,0xff,0x3c,0x07,0xb0,0x06,
1350x3c,0x06,0xb0,0x03,0x00,0x43,0x10,0x24,0x00,0x85,0x28,0x2a,0x34,0xe7,0x80,0x18,
1360xaf,0x82,0x91,0xa0,0xaf,0x84,0x91,0xa8,0x10,0xa0,0x00,0x08,0x34,0xc6,0x01,0x08,
1370x8f,0x83,0x91,0xac,0x8f,0x84,0x91,0x6c,0x8c,0xc2,0x00,0x00,0x00,0x64,0x18,0x21,
1380x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x8c,0xe2,0x00,0x00,
1390x3c,0x03,0x0f,0x00,0x3c,0x04,0x04,0x00,0x00,0x43,0x10,0x24,0x10,0x44,0x00,0x03,
1400x00,0x00,0x00,0x00,0x0c,0x00,0x03,0x95,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,
1410x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,
1420x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x24,0x63,0x06,0x6c,0xaf,0xb0,0x00,0x10,
1430x34,0x42,0x00,0x20,0x8f,0x90,0x91,0xa0,0xac,0x43,0x00,0x00,0xaf,0xb3,0x00,0x1c,
1440xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0x00,0x80,0x88,0x21,
1450x00,0xa0,0x90,0x21,0x0c,0x00,0x01,0xe3,0x00,0xc0,0x98,0x21,0x24,0x07,0x8f,0xff,
1460x14,0x40,0x00,0x19,0x26,0x03,0x00,0x04,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,
1470x00,0x67,0x80,0x24,0x26,0x02,0x00,0x04,0xae,0x11,0x00,0x00,0x00,0x47,0x80,0x24,
1480x97,0x86,0x91,0xa4,0x26,0x03,0x00,0x04,0xae,0x12,0x00,0x00,0x00,0x67,0x80,0x24,
1490xae,0x13,0x00,0x00,0x8f,0x84,0x91,0xa0,0x3c,0x02,0xb0,0x02,0x97,0x85,0x91,0xa6,
1500x00,0xc2,0x30,0x21,0x8f,0x82,0x91,0xa8,0x24,0x84,0x00,0x10,0x24,0xa5,0x00,0x10,
1510x00,0x87,0x20,0x24,0x24,0x42,0x00,0x01,0xa7,0x85,0x91,0xa6,0xaf,0x84,0x91,0xa0,
1520xaf,0x82,0x91,0xa8,0xa4,0xc5,0x00,0x00,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,
1530x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x87,0x83,0x88,0x86,
1540x93,0x82,0x80,0x11,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,
1550x93,0x83,0x88,0x87,0x24,0x02,0x00,0x01,0xa3,0x82,0x80,0x10,0xa3,0x83,0x80,0x12,
1560xa3,0x83,0x80,0x11,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x93,0x82,0x80,0x12,
1570x00,0x00,0x00,0x00,0x14,0x62,0xff,0xf6,0x00,0x00,0x00,0x00,0x08,0x00,0x01,0xd5,
1580x00,0x00,0x00,0x00,0x30,0x84,0x00,0xff,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,
1590xa3,0x85,0x8b,0x6b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x93,0x82,0x91,0xb0,
1600x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,0x24,0x06,0x00,0x01,0x8f,0x82,0x91,0xa8,
1610x3c,0x05,0xb0,0x06,0x3c,0x04,0xb0,0x03,0x34,0xa5,0x80,0x18,0x34,0x84,0x01,0x08,
1620x14,0x40,0x00,0x09,0x00,0x00,0x30,0x21,0x97,0x82,0x91,0xa4,0x8c,0x84,0x00,0x00,
1630x3c,0x03,0xb0,0x02,0x00,0x43,0x10,0x21,0xaf,0x84,0x91,0xac,0xa7,0x80,0x91,0xa6,
1640xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0x8c,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,
1650x00,0xc0,0x10,0x21,0x8f,0x86,0x91,0xa0,0x8f,0x82,0x91,0xa8,0x27,0xbd,0xff,0xe8,
1660xaf,0xbf,0x00,0x10,0x00,0xc0,0x40,0x21,0x14,0x40,0x00,0x0a,0x00,0x40,0x50,0x21,
1670x00,0x00,0x38,0x21,0x27,0x89,0x8b,0x40,0x24,0xe2,0x00,0x01,0x00,0x07,0x18,0x80,
1680x30,0x47,0x00,0xff,0x00,0x69,0x18,0x21,0x2c,0xe2,0x00,0x0a,0x14,0x40,0xff,0xfa,
1690xac,0x60,0x00,0x00,0x3c,0x02,0x00,0x80,0x10,0x82,0x00,0x6d,0x00,0x00,0x00,0x00,
1700x97,0x82,0x8b,0x46,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0x46,
1710x90,0xa3,0x00,0x15,0x97,0x82,0x8b,0x48,0x00,0x03,0x1e,0x00,0x00,0x03,0x1e,0x03,
1720x00,0x43,0x10,0x21,0xa7,0x82,0x8b,0x48,0x8c,0xa4,0x00,0x20,0x3c,0x02,0x00,0x60,
1730x3c,0x03,0x00,0x20,0x00,0x82,0x20,0x24,0x10,0x83,0x00,0x52,0x00,0x00,0x00,0x00,
1740x14,0x80,0x00,0x45,0x00,0x00,0x00,0x00,0x97,0x82,0x8b,0x4c,0x00,0x00,0x00,0x00,
1750x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0x4c,0x84,0xa3,0x00,0x06,0x8f,0x82,0x8b,0x5c,
1760x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x8b,0x5c,0x25,0x42,0x00,0x01,
1770x28,0x43,0x27,0x10,0xaf,0x82,0x91,0xa8,0x10,0x60,0x00,0x09,0x24,0x02,0x00,0x04,
1780x93,0x83,0x80,0x10,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x04,
1790x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
1800x24,0x03,0x00,0x28,0xa3,0x83,0x8b,0x42,0xa3,0x82,0x8b,0x43,0x90,0xa2,0x00,0x18,
1810x93,0x83,0x8b,0x6b,0x00,0x00,0x38,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
1820xa7,0x82,0x8b,0x56,0xa3,0x83,0x8b,0x64,0x27,0x89,0x8b,0x40,0x24,0x05,0x8f,0xff,
1830x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xe3,0x00,0x01,
1840x30,0x67,0x00,0xff,0x25,0x02,0x00,0x04,0x2c,0xe3,0x00,0x0a,0xad,0x04,0x00,0x00,
1850x14,0x60,0xff,0xf7,0x00,0x45,0x40,0x24,0x97,0x83,0x91,0xa6,0x97,0x85,0x91,0xa4,
1860x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x28,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,
1870xa7,0x83,0x91,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,
1880x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x28,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,
1890x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x91,0xa0,0x10,0xa2,0xff,0xd4,
1900x00,0x00,0x00,0x00,0xa3,0x80,0x80,0x10,0x0c,0x00,0x03,0x95,0x00,0x00,0x00,0x00,
1910x08,0x00,0x02,0x30,0x00,0x00,0x00,0x00,0x97,0x82,0x8b,0x4e,0x00,0x00,0x00,0x00,
1920x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0x4e,0x84,0xa3,0x00,0x06,0x8f,0x82,0x8b,0x60,
1930x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x8b,0x60,0x08,0x00,0x02,0x28,
1940x25,0x42,0x00,0x01,0x97,0x82,0x8b,0x4a,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
1950xa7,0x82,0x8b,0x4a,0x84,0xa3,0x00,0x06,0x8f,0x82,0x8b,0x58,0x00,0x00,0x00,0x00,
1960x00,0x43,0x10,0x21,0xaf,0x82,0x8b,0x58,0x08,0x00,0x02,0x28,0x25,0x42,0x00,0x01,
1970x97,0x82,0x8b,0x44,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x8b,0x44,
1980x08,0x00,0x02,0x10,0x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,
1990x27,0xbd,0xff,0xc8,0x00,0x04,0x22,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x09,0xf8,
2000x3c,0x03,0xb0,0x00,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xb2,0x00,0x18,
2010xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x30,0x00,0x83,0x80,0x21,0xaf,0xb7,0x00,0x2c,
2020xaf,0xb6,0x00,0x28,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xac,0xa2,0x00,0x00,
2030x8e,0x09,0x00,0x00,0x00,0x00,0x90,0x21,0x26,0x10,0x00,0x08,0x00,0x09,0xa6,0x02,
2040x12,0x80,0x00,0x13,0x00,0x00,0xa8,0x21,0x24,0x13,0x00,0x02,0x3c,0x16,0x00,0xff,
2050x3c,0x17,0xff,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x12,0x02,
2060x24,0x42,0x00,0x02,0x31,0x25,0x00,0xff,0x10,0xb3,0x00,0x76,0x30,0x51,0x00,0xff,
2070x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x18,0x00,0x00,0x00,0x00,0x02,0x51,0x10,0x21,
2080x30,0x52,0xff,0xff,0x02,0x54,0x18,0x2b,0x14,0x60,0xff,0xf2,0x02,0x11,0x80,0x21,
2090x12,0xa0,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,0x8c,0x43,0x00,0x00,
2100x3c,0x04,0x0f,0x00,0x3c,0x02,0x04,0x00,0x00,0x64,0x18,0x24,0x10,0x62,0x00,0x03,
2110x00,0x00,0x00,0x00,0x0c,0x00,0x03,0x95,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x30,
2120x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,
2130x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8e,0x09,0x00,0x04,0x24,0x15,0x00,0x01,
2140x8e,0x06,0x00,0x0c,0x00,0x09,0x11,0x42,0x00,0x09,0x18,0xc2,0x30,0x48,0x00,0x03,
2150x00,0x09,0x14,0x02,0x30,0x6c,0x00,0x03,0x00,0x09,0x26,0x02,0x11,0x15,0x00,0x45,
2160x30,0x43,0x00,0x0f,0x29,0x02,0x00,0x02,0x14,0x40,0x00,0x26,0x00,0x00,0x00,0x00,
2170x11,0x13,0x00,0x0f,0x00,0x00,0x38,0x21,0x00,0x07,0x22,0x02,0x30,0x84,0xff,0x00,
2180x3c,0x03,0x00,0xff,0x00,0x07,0x2e,0x02,0x00,0x07,0x12,0x00,0x00,0x43,0x10,0x24,
2190x00,0xa4,0x28,0x25,0x00,0xa2,0x28,0x25,0x00,0x07,0x1e,0x00,0x00,0xa3,0x28,0x25,
2200x0c,0x00,0x01,0x9b,0x01,0x20,0x20,0x21,0x08,0x00,0x02,0xa4,0x02,0x51,0x10,0x21,
2210x11,0x95,0x00,0x0f,0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x07,0x00,0x00,0x00,0x00,
2220x00,0x04,0x10,0x80,0x27,0x83,0x91,0x50,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,
2230x08,0x00,0x02,0xcb,0x00,0x07,0x22,0x02,0x00,0x04,0x10,0x40,0x27,0x83,0x91,0x58,
2240x00,0x43,0x10,0x21,0x94,0x47,0x00,0x02,0x08,0x00,0x02,0xcb,0x00,0x07,0x22,0x02,
2250x27,0x82,0x91,0x50,0x00,0x82,0x10,0x21,0x90,0x47,0x00,0x00,0x08,0x00,0x02,0xcb,
2260x00,0x07,0x22,0x02,0x15,0x00,0xff,0xdc,0x00,0x00,0x38,0x21,0x10,0x75,0x00,0x05,
2270x00,0x80,0x38,0x21,0x00,0x65,0x18,0x26,0x24,0x82,0x01,0x00,0x00,0x00,0x38,0x21,
2280x00,0x43,0x38,0x0a,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x0e,0x3c,0x02,0xb0,0x03,
2290x24,0x02,0x00,0x02,0x11,0x82,0x00,0x06,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
2300x00,0xe2,0x10,0x21,0x8c,0x47,0x00,0x00,0x08,0x00,0x02,0xcb,0x00,0x07,0x22,0x02,
2310x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x94,0x43,0x00,0x00,0x08,0x00,0x02,0xca,
2320x30,0x67,0xff,0xff,0x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00,0x08,0x00,0x02,0xca,
2330x30,0x67,0x00,0xff,0x30,0x62,0x00,0x03,0x00,0x02,0x12,0x00,0x11,0x95,0x00,0x07,
2340x00,0x44,0x38,0x21,0x11,0x93,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x02,0xfc,
2350x3c,0x02,0xb0,0x0a,0x08,0x00,0x03,0x01,0x3c,0x02,0xb0,0x0a,0x08,0x00,0x03,0x05,
2360x3c,0x02,0xb0,0x0a,0x8e,0x09,0x00,0x04,0x8e,0x02,0x00,0x08,0x8e,0x03,0x00,0x0c,
2370x00,0x09,0x41,0x42,0x00,0x02,0x22,0x02,0x00,0x03,0x3a,0x02,0x30,0x84,0xff,0x00,
2380x30,0xe7,0xff,0x00,0x00,0x02,0x5e,0x02,0x00,0x02,0x32,0x00,0x00,0x03,0x56,0x02,
2390x00,0x03,0x2a,0x00,0x01,0x64,0x58,0x25,0x00,0xd6,0x30,0x24,0x01,0x47,0x50,0x25,
2400x00,0x02,0x16,0x00,0x00,0xb6,0x28,0x24,0x00,0x03,0x1e,0x00,0x01,0x66,0x58,0x25,
2410x01,0x45,0x50,0x25,0x00,0x57,0x10,0x24,0x00,0x77,0x18,0x24,0x01,0x62,0x38,0x25,
2420x01,0x43,0x30,0x25,0x00,0x09,0x10,0xc2,0x00,0x09,0x1c,0x02,0x31,0x08,0x00,0x03,
2430x30,0x4c,0x00,0x03,0x30,0x63,0x00,0x0f,0x00,0x09,0x26,0x02,0x00,0xe0,0x58,0x21,
2440x15,0x00,0x00,0x28,0x00,0xc0,0x50,0x21,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x06,
2450x00,0x80,0x28,0x21,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0x69,0x02,0x51,0x10,0x21,
2460x24,0x85,0x01,0x00,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x15,0x24,0x02,0x00,0x02,
2470x11,0x82,0x00,0x0a,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00,
2480x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,
2490xac,0x62,0x00,0x00,0x08,0x00,0x02,0xa4,0x02,0x51,0x10,0x21,0x00,0xa3,0x18,0x21,
2500x94,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,
2510x00,0x45,0x10,0x25,0xa4,0x62,0x00,0x00,0x08,0x00,0x02,0xa4,0x02,0x51,0x10,0x21,
2520x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,
2530x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x02,0xa3,
2540xa0,0x62,0x00,0x00,0x24,0x02,0x00,0x01,0x11,0x02,0x00,0x21,0x00,0x00,0x00,0x00,
2550x15,0x13,0xff,0x42,0x00,0x00,0x00,0x00,0x11,0x82,0x00,0x17,0x00,0x00,0x00,0x00,
2560x11,0x88,0x00,0x0b,0x00,0x00,0x00,0x00,0x27,0x83,0x91,0x50,0x00,0x04,0x20,0x80,
2570x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x18,0x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,
2580x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x02,0xa3,0xac,0x82,0x00,0x18,
2590x27,0x83,0x91,0x58,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x21,0x94,0x82,0x00,0x02,
2600x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,
2610x08,0x00,0x02,0xa3,0xa4,0x82,0x00,0x02,0x27,0x83,0x91,0x50,0x00,0x83,0x18,0x21,
2620x90,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x03,0x59,0x00,0xe6,0x28,0x24,
2630x30,0x62,0x00,0x07,0x00,0x02,0x12,0x00,0x11,0x88,0x00,0x0f,0x00,0x44,0x10,0x21,
2640x11,0x93,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,
2650x8c,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x03,0x46,0x00,0xe6,0x28,0x24,
2660x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x06,0x20,0x27,
2670x08,0x00,0x03,0x4f,0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,0x08,0x00,0x03,0x7c,
2680x00,0x43,0x18,0x21,0x97,0x85,0x91,0xa4,0x3c,0x07,0xb0,0x02,0x3c,0x04,0xb0,0x03,
2690x3c,0x02,0x80,0x00,0x00,0xa7,0x28,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x0e,0x54,
2700x24,0x03,0xff,0x80,0xac,0x82,0x00,0x00,0xa0,0xa3,0x00,0x07,0x97,0x82,0x91,0xa6,
2710x97,0x85,0x91,0xa4,0x3c,0x06,0xb0,0x06,0x30,0x42,0xff,0xf8,0x24,0x42,0x00,0x10,
2720x00,0xa2,0x10,0x21,0x30,0x42,0x0f,0xff,0x24,0x44,0x00,0x08,0x30,0x84,0x0f,0xff,
2730x00,0x05,0x28,0xc2,0x3c,0x03,0x00,0x40,0x00,0xa3,0x28,0x25,0x00,0x87,0x20,0x21,
2740x34,0xc6,0x80,0x18,0xac,0xc5,0x00,0x00,0xaf,0x84,0x91,0xa0,0xa7,0x82,0x91,0xa4,
2750xa7,0x80,0x91,0xa6,0xaf,0x80,0x91,0xa8,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
2760x30,0xa5,0x00,0xff,0x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01,0x00,0xe0,0x48,0x21,
2770x30,0xc6,0x00,0xff,0x8f,0xa7,0x00,0x10,0x10,0x82,0x00,0x07,0x00,0xa0,0x40,0x21,
2780x24,0x02,0x00,0x03,0x10,0x82,0x00,0x03,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
2790x00,0x00,0x00,0x00,0x24,0xa8,0x01,0x00,0x3c,0x03,0xb0,0x03,0x24,0x02,0x00,0x01,
2800x00,0x07,0x20,0x27,0x01,0x27,0x28,0x24,0x10,0xc2,0x00,0x14,0x01,0x03,0x18,0x21,
2810x24,0x02,0x00,0x02,0x10,0xc2,0x00,0x09,0x00,0x07,0x50,0x27,0x3c,0x03,0xb0,0x03,
2820x01,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,
2830x00,0x45,0x10,0x25,0x08,0x00,0x03,0xe0,0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x03,
2840x01,0x03,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,
2850x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00,0x90,0x62,0x00,0x00,
2860x00,0x00,0x00,0x00,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xa0,0x62,0x00,0x00,
2870x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0x07,0x00,0x04,0x22,0x00,
2880x30,0xa5,0x00,0xff,0x00,0x85,0x28,0x21,0x3c,0x02,0xb0,0x0a,0x00,0xa2,0x40,0x21,
2890x30,0xc6,0x00,0xff,0x24,0x02,0x00,0x01,0x8f,0xa4,0x00,0x10,0x10,0xc2,0x00,0x14,
2900x24,0x02,0x00,0x02,0x00,0x04,0x50,0x27,0x10,0xc2,0x00,0x09,0x00,0xe4,0x48,0x24,
2910x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
2920x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,
2930x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
2940x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00,
2950x91,0x02,0x00,0x00,0x00,0x04,0x18,0x27,0x00,0xe4,0x20,0x24,0x00,0x43,0x10,0x24,
2960x00,0x44,0x10,0x25,0x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x00,0x30,0xa9,0x00,0xff,
2970x27,0x83,0x91,0x50,0x30,0x85,0x00,0xff,0x24,0x02,0x00,0x01,0x00,0x07,0x50,0x27,
2980x00,0xc7,0x40,0x24,0x11,0x22,0x00,0x17,0x00,0xa3,0x18,0x21,0x00,0x05,0x20,0x40,
2990x27,0x82,0x91,0x50,0x00,0x05,0x28,0x80,0x27,0x83,0x91,0x58,0x00,0x83,0x50,0x21,
3000x00,0xa2,0x20,0x21,0x24,0x02,0x00,0x02,0x00,0x07,0x40,0x27,0x11,0x22,0x00,0x07,
3010x00,0xc7,0x28,0x24,0x8c,0x82,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,
3020x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x18,0x95,0x42,0x00,0x02,
3030x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,
3040xa5,0x42,0x00,0x02,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,
3050x00,0x48,0x10,0x25,0x03,0xe0,0x00,0x08,0xa0,0x62,0x00,0x00,0x00,0x04,0x32,0x02,
3060x30,0xc6,0xff,0x00,0x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00,0x3c,0x05,0x00,0xff,
3070x00,0x65,0x18,0x24,0x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25,0x00,0x04,0x26,0x00,
3080x03,0xe0,0x00,0x08,0x00,0x44,0x10,0x25,0x3c,0x02,0xb0,0x02,0x34,0x42,0x00,0x08,
3090x3c,0x03,0xb0,0x02,0xaf,0x82,0x8b,0x78,0xaf,0x83,0x8b,0x7c,0xa7,0x80,0x8b,0x80,
3100xa7,0x80,0x8b,0x82,0xaf,0x80,0x8b,0x84,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
3110x27,0xbd,0xff,0xd8,0xaf,0xbf,0x00,0x20,0x94,0x82,0x00,0x04,0x00,0x00,0x00,0x00,
3120x30,0x42,0xe0,0x00,0x10,0x40,0x00,0x05,0x00,0x80,0x18,0x21,0x8f,0xbf,0x00,0x20,
3130x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x90,0x84,0x00,0x02,
3140x00,0x00,0x00,0x00,0x30,0x84,0x00,0xfc,0x0c,0x00,0x06,0xc9,0x00,0x64,0x20,0x21,
3150x08,0x00,0x04,0x47,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb2,0x00,0x18,
3160xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,
3170x8f,0x90,0x91,0xa0,0x0c,0x00,0x2b,0xd1,0x00,0x80,0x90,0x21,0x00,0x40,0x88,0x21,
3180x93,0x82,0x82,0x20,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1b,0x24,0x02,0x00,0x01,
3190xa3,0x82,0x82,0x20,0x24,0x03,0x00,0x05,0x24,0x02,0x00,0x04,0xa3,0x83,0x8b,0x73,
3200xa3,0x82,0x8b,0x72,0xa7,0x80,0x82,0x22,0x00,0x00,0x28,0x21,0x27,0x86,0x8b,0x70,
3210x00,0x05,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01,
3220x30,0x65,0xff,0xff,0xae,0x04,0x00,0x00,0x10,0xa0,0xff,0xfa,0x00,0x05,0x10,0x80,
3230x8f,0x83,0x91,0xa0,0x97,0x82,0x91,0xa6,0x24,0x05,0x8f,0xff,0x24,0x63,0x00,0x04,
3240x00,0x65,0x18,0x24,0x26,0x04,0x00,0x04,0x24,0x42,0x00,0x04,0xaf,0x83,0x91,0xa0,
3250xa7,0x82,0x91,0xa6,0x00,0x85,0x80,0x24,0x97,0x84,0x82,0x22,0x27,0x93,0x80,0x2c,
3260x02,0x40,0x28,0x21,0x00,0x93,0x20,0x21,0x0c,0x00,0x2c,0x55,0x02,0x20,0x30,0x21,
3270x97,0x87,0x82,0x22,0x24,0x02,0x00,0x52,0x00,0xf1,0x18,0x21,0xa7,0x83,0x82,0x22,
3280x82,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x06,0x00,0x60,0x38,0x21,
3290x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
3300x27,0xbd,0x00,0x28,0x82,0x43,0x00,0x01,0x24,0x02,0x00,0x54,0x14,0x62,0xff,0xf8,
3310x24,0x02,0x00,0x4c,0x82,0x43,0x00,0x02,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xf4,
3320x00,0x00,0x00,0x00,0x30,0xe6,0xff,0xff,0x10,0xc0,0x00,0x0c,0x00,0x00,0x28,0x21,
3330x02,0x60,0x48,0x21,0x24,0x08,0x8f,0xff,0x00,0xa9,0x10,0x21,0x8c,0x44,0x00,0x00,
3340x24,0xa3,0x00,0x04,0x30,0x65,0xff,0xff,0x26,0x02,0x00,0x04,0x00,0xa6,0x18,0x2b,
3350xae,0x04,0x00,0x00,0x14,0x60,0xff,0xf8,0x00,0x48,0x80,0x24,0x97,0x83,0x91,0xa6,
3360x97,0x85,0x91,0xa4,0x3c,0x02,0xb0,0x02,0x00,0x67,0x18,0x21,0x00,0xa2,0x28,0x21,
3370x3c,0x04,0xb0,0x06,0xa7,0x83,0x91,0xa6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,
3380x8f,0x82,0x91,0xa0,0x8c,0x86,0x00,0x00,0x30,0xe5,0xff,0xff,0x24,0x03,0x8f,0xff,
3390x00,0x45,0x10,0x21,0x3c,0x04,0x0f,0x00,0x00,0x43,0x10,0x24,0x00,0xc4,0x30,0x24,
3400x3c,0x03,0x04,0x00,0xaf,0x82,0x91,0xa0,0x10,0xc3,0xff,0xd1,0x00,0x00,0x00,0x00,
3410x0c,0x00,0x03,0x95,0x00,0x00,0x00,0x00,0xa3,0x80,0x82,0x20,0x08,0x00,0x04,0x88,
3420x00,0x00,0x00,0x00,0x8f,0x82,0x8b,0x7c,0x97,0x83,0x8b,0x80,0x8f,0x87,0x8b,0x78,
3430x3c,0x06,0xff,0xff,0xac,0x43,0x00,0x00,0x8f,0x82,0x8b,0x7c,0x3c,0x03,0x80,0x00,
3440x24,0xe5,0x00,0x08,0xac,0x43,0x00,0x04,0x8f,0x82,0x8b,0x7c,0x34,0xc6,0x1f,0xff,
3450x3c,0x03,0x00,0x40,0x30,0x42,0x0f,0xff,0x3c,0x04,0xb0,0x06,0x00,0x02,0x10,0xc2,
3460x00,0x43,0x10,0x25,0x00,0xa6,0x28,0x24,0x34,0x84,0x80,0x18,0x27,0xbd,0xff,0xf8,
3470xac,0x82,0x00,0x00,0xaf,0x85,0x8b,0x78,0xaf,0x87,0x8b,0x7c,0xa7,0x80,0x8b,0x80,
3480xa7,0x80,0x8b,0x82,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,0x03,0xe0,0x00,0x08,
3490x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
3500x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,
3510xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x8f,0x91,0x8b,0x78,
3520x00,0x80,0x80,0x21,0xaf,0xbf,0x00,0x1c,0x0c,0x00,0x05,0x78,0x00,0xa0,0x90,0x21,
3530x97,0x82,0x8b,0x80,0x36,0x10,0x12,0x00,0x26,0x2a,0x00,0x04,0x24,0x4c,0x00,0x14,
3540x2c,0x42,0x04,0x01,0x14,0x40,0x00,0x0a,0x24,0x09,0x8f,0xff,0x8f,0x82,0x80,0x18,
3550x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x80,0x18,0x8f,0xbf,0x00,0x1c,
3560x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
3570x8e,0x44,0x00,0x1c,0x86,0x47,0x00,0x06,0x97,0x86,0x8b,0x82,0x8c,0x82,0x00,0x08,
3580x00,0x07,0x3c,0x00,0x8f,0x85,0x8b,0x78,0x00,0x02,0x11,0x02,0x30,0x42,0x40,0x00,
3590x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x8c,0x82,0x00,0x04,0x82,0x43,0x00,0x15,
3600x01,0x49,0x88,0x24,0x00,0x02,0x14,0xc2,0x00,0x03,0x1a,0x00,0x00,0x02,0x14,0x00,
3610x00,0x62,0x80,0x25,0xae,0x30,0x00,0x00,0x92,0x43,0x00,0x13,0x92,0x44,0x00,0x10,
3620x96,0x50,0x00,0x1a,0x00,0x03,0x1c,0x00,0x00,0x04,0x26,0x00,0x02,0x03,0x80,0x25,
3630x26,0x22,0x00,0x04,0x00,0x49,0x88,0x24,0x02,0x04,0x80,0x25,0xae,0x30,0x00,0x00,
3640x92,0x42,0x00,0x0f,0x92,0x43,0x00,0x11,0x26,0x24,0x00,0x04,0x00,0x02,0x12,0x00,
3650x00,0x89,0x88,0x24,0x00,0x62,0x80,0x25,0x02,0x07,0x80,0x25,0x26,0x22,0x00,0x04,
3660xae,0x30,0x00,0x00,0x00,0x49,0x88,0x24,0xae,0x20,0x00,0x00,0x8f,0x82,0x80,0x14,
3670x24,0xc6,0x00,0x01,0x24,0xa5,0x00,0x14,0x30,0xc8,0xff,0xff,0x3c,0x0b,0xb0,0x03,
3680x00,0xa9,0x28,0x24,0x24,0x42,0x00,0x01,0x2d,0x08,0x00,0x0a,0xaf,0x85,0x8b,0x78,
3690xa7,0x8c,0x8b,0x80,0xaf,0x82,0x80,0x14,0xa7,0x86,0x8b,0x82,0x11,0x00,0x00,0x07,
3700x35,0x6b,0x01,0x08,0x8f,0x82,0x8b,0x84,0x8d,0x63,0x00,0x00,0x24,0x42,0x04,0x00,
3710x00,0x62,0x18,0x2b,0x14,0x60,0xff,0xc1,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0xbd,
3720x00,0x00,0x00,0x00,0x08,0x00,0x04,0xf3,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,
3730xaf,0xbf,0x00,0x10,0x0c,0x00,0x05,0x78,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,
3740x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe0,
3750xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,
3760x8f,0x90,0x8b,0x78,0x0c,0x00,0x05,0x78,0x00,0x80,0x90,0x21,0x97,0x82,0x8b,0x80,
3770x24,0x11,0x8f,0xff,0x2c,0x42,0x04,0x01,0x14,0x40,0x00,0x06,0x26,0x03,0x00,0x04,
3780x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
3790x27,0xbd,0x00,0x20,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,0x00,0x71,0x80,0x24,
3800xae,0x00,0x00,0x00,0x8e,0x44,0x00,0x08,0x26,0x02,0x00,0x04,0x0c,0x00,0x05,0x86,
3810x00,0x51,0x80,0x24,0x97,0x86,0x8b,0x82,0x8f,0x83,0x8b,0x78,0xae,0x02,0x00,0x00,
3820x97,0x82,0x8b,0x80,0x24,0xc6,0x00,0x01,0x8e,0x47,0x00,0x0c,0x24,0x63,0x00,0x10,
3830x30,0xc5,0xff,0xff,0x26,0x04,0x00,0x04,0x3c,0x08,0xb0,0x03,0x00,0x71,0x18,0x24,
3840x00,0x91,0x80,0x24,0x24,0x42,0x00,0x10,0x2c,0xa5,0x00,0x0a,0x35,0x08,0x01,0x08,
3850xae,0x07,0x00,0x00,0xaf,0x83,0x8b,0x78,0xa7,0x82,0x8b,0x80,0xa7,0x86,0x8b,0x82,
3860x10,0xa0,0x00,0x07,0x00,0x00,0x00,0x00,0x8f,0x82,0x8b,0x84,0x8d,0x03,0x00,0x00,
3870x24,0x42,0x04,0x00,0x00,0x62,0x18,0x2b,0x14,0x60,0xff,0xd9,0x00,0x00,0x00,0x00,
3880x0c,0x00,0x04,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x05,0x4c,0x00,0x00,0x00,0x00,
3890x97,0x82,0x8b,0x82,0x3c,0x03,0xb0,0x03,0x14,0x40,0x00,0x09,0x34,0x63,0x01,0x08,
3900x8c,0x62,0x00,0x00,0x8f,0x83,0x8b,0x7c,0xa7,0x80,0x8b,0x80,0xaf,0x82,0x8b,0x84,
3910xac,0x60,0x00,0x00,0x8f,0x82,0x8b,0x7c,0x00,0x00,0x00,0x00,0xac,0x40,0x00,0x04,
3920x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00,
3930x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00,0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24,
3940x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25,0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08,
3950x00,0x44,0x10,0x25,0x80,0x82,0x00,0x00,0x90,0x83,0x00,0x00,0x10,0x40,0x00,0x0c,
3960x00,0x80,0x28,0x21,0x24,0x62,0xff,0x9f,0x30,0x42,0x00,0xff,0x2c,0x42,0x00,0x1a,
3970x10,0x40,0x00,0x02,0x24,0x63,0xff,0xe0,0xa0,0xa3,0x00,0x00,0x24,0xa5,0x00,0x01,
3980x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xf6,0x00,0x40,0x18,0x21,
3990x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x80,0x82,0x00,0x00,0x90,0x83,0x00,0x00,
4000x10,0x40,0x00,0x0c,0x00,0x80,0x28,0x21,0x24,0x62,0xff,0xbf,0x30,0x42,0x00,0xff,
4010x2c,0x42,0x00,0x1a,0x10,0x40,0x00,0x02,0x24,0x63,0x00,0x20,0xa0,0xa3,0x00,0x00,
4020x24,0xa5,0x00,0x01,0x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xf6,
4030x00,0x40,0x18,0x21,0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x27,0xbd,0xff,0xe8,
4040xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x24,0x10,0xff,0xff,0x0c,0x00,0x29,0x11,
4050x00,0x00,0x00,0x00,0x10,0x50,0xff,0xfd,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
4060x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
4070x27,0xbd,0xff,0xc8,0xaf,0xb3,0x00,0x1c,0x00,0x00,0x98,0x21,0xaf,0xb1,0x00,0x14,
4080x02,0x65,0x88,0x2b,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb0,0x00,0x10,
4090xaf,0xbf,0x00,0x34,0xaf,0xbe,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb4,0x00,0x20,
4100xaf,0xb2,0x00,0x18,0x00,0xa0,0xb0,0x21,0xaf,0xa4,0x00,0x38,0x00,0xc0,0xa8,0x21,
4110x12,0x20,0x00,0x17,0x00,0x80,0x80,0x21,0x24,0x17,0xff,0xff,0x24,0x1e,0x00,0x0a,
4120x0c,0x00,0x29,0x11,0x00,0x00,0x00,0x00,0x10,0x57,0x00,0x0f,0x00,0x02,0x16,0x00,
4130x00,0x02,0x26,0x03,0x10,0x9e,0x00,0x0e,0x24,0x02,0x00,0x0d,0x10,0x82,0x00,0x34,
4140x24,0x02,0x00,0x08,0x10,0x82,0x00,0x25,0x24,0x02,0x00,0x09,0x10,0x82,0x00,0x13,
4150x00,0x00,0x90,0x21,0xa2,0x04,0x00,0x00,0x26,0x73,0x00,0x01,0x16,0xa0,0x00,0x0b,
4160x26,0x10,0x00,0x01,0x02,0x76,0x88,0x2b,0x16,0x20,0xff,0xed,0x00,0x00,0x00,0x00,
4170x7b,0xbe,0x01,0xbc,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,
4180x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x0c,0x00,0x29,0x04,
4190x02,0x76,0x88,0x2b,0x08,0x00,0x05,0xe6,0x00,0x00,0x00,0x00,0x24,0x14,0x00,0x20,
4200xa2,0x14,0x00,0x00,0x26,0x52,0x00,0x01,0x24,0x04,0x00,0x20,0x26,0x73,0x00,0x01,
4210x16,0xa0,0x00,0x06,0x26,0x10,0x00,0x01,0x2a,0x42,0x00,0x08,0x10,0x40,0xff,0xea,
4220x02,0x76,0x88,0x2b,0x08,0x00,0x05,0xf5,0xa2,0x14,0x00,0x00,0x0c,0x00,0x29,0x04,
4230x00,0x00,0x00,0x00,0x08,0x00,0x05,0xfb,0x2a,0x42,0x00,0x08,0x8f,0xa2,0x00,0x38,
4240x00,0x00,0x00,0x00,0x12,0x02,0xff,0xe0,0x00,0x00,0x00,0x00,0x26,0x10,0xff,0xff,
4250x12,0xa0,0xff,0xdc,0x26,0x73,0xff,0xff,0x0c,0x00,0x29,0x04,0x24,0x04,0x00,0x08,
4260x0c,0x00,0x29,0x04,0x24,0x04,0x00,0x20,0x08,0x00,0x05,0xef,0x24,0x04,0x00,0x08,
4270x08,0x00,0x05,0xe8,0xa2,0x00,0x00,0x00,0x90,0x82,0x00,0x00,0x00,0x00,0x00,0x00,
4280x00,0x02,0x1e,0x00,0x10,0x60,0x00,0x16,0x00,0x00,0x30,0x21,0x24,0x07,0x00,0x20,
4290x00,0x03,0x1e,0x03,0x10,0x67,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x15,
4300x00,0x00,0x00,0x00,0x10,0x67,0x00,0x0b,0x24,0xc6,0x00,0x01,0x10,0x60,0x00,0x0a,
4310x00,0x02,0x1e,0x00,0x24,0x05,0x00,0x20,0x24,0x84,0x00,0x01,0x80,0x83,0x00,0x00,
4320x90,0x82,0x00,0x00,0x10,0x65,0x00,0x03,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xfa,
4330x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,0x14,0x60,0xff,0xed,0x00,0x00,0x00,0x00,
4340x28,0xc3,0x00,0x08,0x24,0x02,0x00,0x07,0x00,0x43,0x30,0x0a,0x03,0xe0,0x00,0x08,
4350x00,0xc0,0x10,0x21,0x24,0x84,0x00,0x01,0x90,0x82,0x00,0x00,0x08,0x00,0x06,0x2a,
4360x00,0x02,0x1e,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb1,0x00,0x14,0x27,0x91,0x8b,0x88,
4370xaf,0xb0,0x00,0x10,0x24,0x06,0x00,0x20,0x00,0x80,0x80,0x21,0x00,0x00,0x28,0x21,
4380xaf,0xbf,0x00,0x18,0x0c,0x00,0x2c,0x4b,0x02,0x20,0x20,0x21,0x82,0x02,0x00,0x00,
4390x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1f,0x00,0x00,0x30,0x21,0x02,0x20,0x20,0x21,
4400x24,0x09,0x00,0x20,0x24,0x08,0x00,0x20,0x24,0x07,0x00,0x08,0xac,0x90,0x00,0x00,
4410x82,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x49,0x00,0x0a,0x00,0x00,0x00,0x00,
4420x10,0x40,0x00,0x08,0x24,0x03,0x00,0x20,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00,
4430x00,0x00,0x00,0x00,0x10,0x43,0x00,0x03,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfa,
4440x00,0x00,0x00,0x00,0xa2,0x00,0x00,0x00,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00,
4450x92,0x03,0x00,0x00,0x10,0x48,0x00,0x0c,0x24,0x05,0x00,0x20,0x24,0xc6,0x00,0x01,
4460x10,0xc7,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x03,0x16,0x00,0x14,0x40,0xff,0xe7,
4470x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x27,0x82,0x8b,0x88,
4480x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x26,0x10,0x00,0x01,0x82,0x02,0x00,0x00,
4490x92,0x03,0x00,0x00,0x10,0x45,0xff,0xfc,0x00,0x00,0x00,0x00,0x08,0x00,0x06,0x5c,
4500x24,0xc6,0x00,0x01,0x00,0x80,0x30,0x21,0x90,0x84,0x00,0x00,0x00,0x00,0x38,0x21,
4510x10,0x80,0x00,0x19,0x24,0xc6,0x00,0x01,0x24,0x82,0xff,0xd0,0x30,0x42,0x00,0xff,
4520x2c,0x43,0x00,0x0a,0x14,0x60,0x00,0x0c,0x00,0x07,0x19,0x00,0x24,0x83,0xff,0x9f,
4530x24,0x82,0xff,0xa9,0x24,0x88,0xff,0xc9,0x2c,0x63,0x00,0x06,0x24,0x84,0xff,0xbf,
4540x2c,0x84,0x00,0x06,0x14,0x60,0x00,0x03,0x30,0x42,0x00,0xff,0x10,0x80,0x00,0x0e,
4550x31,0x02,0x00,0xff,0x00,0x07,0x19,0x00,0x00,0x62,0x18,0x21,0x00,0x67,0x10,0x2b,
4560x14,0x40,0x00,0x07,0x00,0x00,0x20,0x21,0x90,0xc4,0x00,0x00,0x00,0x60,0x38,0x21,
4570x14,0x80,0xff,0xe9,0x24,0xc6,0x00,0x01,0xac,0xa7,0x00,0x00,0x24,0x04,0x00,0x01,
4580x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x08,0x00,0x06,0x8c,0x00,0x00,0x20,0x21,
4590x00,0x00,0x20,0x21,0x27,0x85,0x91,0xc0,0x24,0x82,0x00,0x01,0x00,0x04,0x18,0x80,
4600x30,0x44,0x00,0xff,0x00,0x65,0x18,0x21,0x2c,0x82,0x00,0x0b,0x14,0x40,0xff,0xfa,
4610xac,0x60,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0xaf,0x84,0x8c,0x08,
4620xaf,0x85,0x8c,0x0c,0xaf,0x86,0x8c,0x10,0xaf,0x87,0x8c,0x14,0x03,0xe0,0x00,0x08,
4630x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x90,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
4640x2c,0x43,0x00,0x64,0x24,0x42,0x00,0x01,0x27,0x84,0x8b,0xa8,0xaf,0x82,0x84,0x90,
4650x10,0x60,0x00,0x05,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
4660x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0xaf,0x80,0x84,0x90,0x0c,0x00,0x06,0xf6,
4670x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,0x28,0x44,0x00,0x08,0x24,0x02,0x00,0x07,
4680x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x80,0xff,0xf3,0x24,0x02,0x00,0x08,
4690x27,0x84,0x8b,0xa8,0x14,0x62,0xff,0xf0,0x00,0x00,0x00,0x00,0x0c,0x00,0x17,0xb0,
4700x00,0x00,0x00,0x00,0x27,0x84,0x8b,0xa8,0x0c,0x00,0x07,0x54,0x00,0x00,0x00,0x00,
4710x8f,0x83,0x84,0x94,0x3c,0x04,0x80,0x01,0x00,0x60,0x28,0x21,0x24,0x63,0x00,0x01,
4720xaf,0x83,0x84,0x94,0x0c,0x00,0x17,0x9d,0x24,0x84,0x04,0x88,0x08,0x00,0x06,0xaa,
4730x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xbf,0x00,0x38,0x8c,0x85,0x00,0x0c,
4740x8c,0x88,0x00,0x08,0x18,0xa0,0x00,0x0e,0x00,0x00,0x30,0x21,0x24,0x87,0x00,0x08,
4750x27,0xa9,0x00,0x10,0x00,0x06,0x10,0x80,0x00,0x06,0x19,0x00,0x00,0x49,0x10,0x21,
4760x14,0xc0,0x00,0x1f,0x00,0x83,0x18,0x21,0xaf,0xa7,0x00,0x10,0x24,0xc2,0x00,0x01,
4770x30,0x46,0x00,0xff,0x00,0xc5,0x18,0x2a,0x14,0x60,0xff,0xf7,0x00,0x06,0x10,0x80,
4780x29,0x02,0x00,0x0a,0x14,0x40,0x00,0x05,0x00,0x08,0x18,0x40,0x8f,0xbf,0x00,0x38,
4790x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x00,0x68,0x18,0x21,
4800x27,0x82,0x83,0x8c,0x00,0x03,0x18,0xc0,0x00,0x62,0x18,0x21,0x8c,0x62,0x00,0x10,
4810x01,0x00,0x20,0x21,0x00,0x40,0xf8,0x09,0x27,0xa6,0x00,0x10,0x8f,0x83,0x84,0xa8,
4820x3c,0x04,0x80,0x01,0x00,0x60,0x28,0x21,0x24,0x63,0x00,0x01,0xaf,0x83,0x84,0xa8,
4830x0c,0x00,0x17,0x9d,0x24,0x84,0x04,0x9c,0x08,0x00,0x06,0xdf,0x00,0x00,0x00,0x00,
4840x08,0x00,0x06,0xd7,0xac,0x43,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb1,0x00,0x14,
4850xaf,0xbf,0x00,0x18,0x00,0x80,0x88,0x21,0x0c,0x00,0x17,0xd4,0xaf,0xb0,0x00,0x10,
4860x00,0x40,0x20,0x21,0x24,0x02,0xff,0xff,0x10,0x82,0x00,0x1f,0x24,0x03,0x00,0x06,
4870x8f,0x85,0x84,0xbc,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x0a,0x24,0x02,0x00,0x08,
4880x24,0x02,0x00,0x02,0x10,0x82,0x00,0x3b,0x28,0x82,0x00,0x03,0x10,0x40,0x00,0x32,
4890x24,0x02,0x00,0x1b,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x13,0x24,0x03,0x00,0x08,
4900x24,0x02,0x00,0x08,0x10,0x82,0x00,0x23,0x24,0x02,0x00,0x0d,0x10,0x82,0x00,0x18,
4910x02,0x25,0x10,0x21,0x24,0xa3,0x00,0x01,0xa0,0x44,0x00,0x00,0xaf,0x83,0x84,0xbc,
4920x18,0x60,0x00,0x08,0x24,0x02,0x00,0x43,0x82,0x23,0x00,0x00,0x00,0x00,0x00,0x00,
4930x10,0x62,0x00,0x0a,0x00,0x00,0x00,0x00,0x30,0x84,0xff,0xff,0x0c,0x00,0x17,0xd0,
4940x00,0x00,0x00,0x00,0x24,0x03,0x00,0x06,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,
4950x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x3c,0x04,0x80,0x01,
4960x0c,0x00,0x17,0xb0,0x24,0x84,0x04,0xb0,0x08,0x00,0x07,0x1e,0x24,0x03,0x00,0x06,
4970xa0,0x40,0x00,0x00,0x24,0xa5,0x00,0x01,0xaf,0x85,0x84,0xbc,0x0c,0x00,0x17,0xd0,
4980x24,0x04,0x00,0x0d,0x24,0x03,0x00,0x07,0xaf,0x80,0x84,0xbc,0x08,0x00,0x07,0x1e,
4990x00,0x00,0x00,0x00,0x18,0xa0,0xff,0xeb,0x24,0xa5,0xff,0xff,0xaf,0x85,0x84,0xbc,
5000x0c,0x00,0x17,0xd0,0x24,0x04,0x00,0x08,0x0c,0x00,0x17,0xd0,0x24,0x04,0x00,0x20,
5010x08,0x00,0x07,0x1b,0x24,0x04,0x00,0x08,0x14,0x82,0xff,0xd2,0x24,0x02,0x00,0x08,
5020x0c,0x00,0x06,0x90,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0xbc,0x08,0x00,0x07,0x0c,
5030x24,0x04,0x00,0x0d,0x0c,0x00,0x2b,0xd1,0x02,0x20,0x20,0x21,0xaf,0x82,0x84,0xbc,
5040x04,0x40,0x00,0x0d,0x00,0x00,0x80,0x21,0x02,0x30,0x10,0x21,0x90,0x44,0x00,0x00,
5050x26,0x10,0x00,0x01,0x00,0x04,0x26,0x00,0x00,0x04,0x26,0x03,0x0c,0x00,0x17,0xd0,
5060x30,0x84,0xff,0xff,0x8f,0x83,0x84,0xbc,0x00,0x00,0x00,0x00,0x00,0x70,0x18,0x2a,
5070x10,0x60,0xff,0xf6,0x02,0x30,0x10,0x21,0x08,0x00,0x07,0x2e,0x24,0x03,0x00,0x06,
5080x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x27,0x83,0x8b,0xe8,0x24,0x02,0x00,0x07,
5090x24,0x42,0xff,0xff,0xac,0x60,0x00,0x00,0x04,0x41,0xff,0xfd,0x24,0x63,0x00,0x04,
5100x0c,0x00,0x07,0x66,0x00,0x00,0x00,0x00,0x8f,0x84,0x8b,0xe8,0x27,0x86,0x8b,0xe8,
5110x0c,0x00,0x07,0x83,0x00,0x40,0x28,0x21,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
5120x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe0,0x00,0x80,0x28,0x21,
5130x27,0x84,0x8b,0xc8,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0x0c,0x00,0x2c,0x62,
5140xaf,0xb0,0x00,0x10,0x8f,0x85,0x83,0x2c,0x27,0x84,0x8b,0xc8,0x0c,0x00,0x2c,0x26,
5150x00,0x00,0x88,0x21,0x10,0x40,0x00,0x0c,0x00,0x00,0x00,0x00,0x27,0x90,0x8b,0xe8,
5160x8f,0x85,0x83,0x2c,0x00,0x00,0x20,0x21,0xae,0x02,0x00,0x00,0x0c,0x00,0x2c,0x26,
5170x26,0x31,0x00,0x01,0x26,0x10,0x00,0x04,0x10,0x40,0x00,0x03,0x2a,0x23,0x00,0x64,
5180x14,0x60,0xff,0xf7,0x00,0x00,0x00,0x00,0x02,0x20,0x10,0x21,0x8f,0xbf,0x00,0x18,
5190x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd0,
5200xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xbf,0x00,0x2c,
5210xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
5220x00,0xa0,0xa8,0x21,0x00,0x80,0xa0,0x21,0x00,0xc0,0xb0,0x21,0x10,0xa0,0x00,0x1d,
5230x24,0x02,0x00,0x05,0x3c,0x02,0x80,0x00,0x24,0x43,0x29,0x1c,0x8f,0x82,0x83,0x9c,
5240x00,0x00,0x00,0x00,0x10,0x43,0x00,0x1e,0x00,0x00,0x88,0x21,0x00,0x60,0x98,0x21,
5250x00,0x00,0x90,0x21,0x27,0x90,0x83,0x9c,0x8e,0x05,0xff,0xec,0x02,0x80,0x20,0x21,
5260x0c,0x00,0x2c,0x6a,0x26,0x10,0x00,0x18,0x10,0x40,0x00,0x06,0x02,0x51,0x18,0x21,
5270x8e,0x02,0x00,0x00,0x26,0x31,0x00,0x01,0x14,0x53,0xff,0xf7,0x00,0x11,0x90,0x40,
5280x02,0x51,0x18,0x21,0x27,0x82,0x83,0x8c,0x00,0x03,0x18,0xc0,0x00,0x62,0x18,0x21,
5290x8c,0x62,0x00,0x10,0x02,0x20,0x20,0x21,0x02,0xa0,0x28,0x21,0x00,0x40,0xf8,0x09,
5300x02,0xc0,0x30,0x21,0x8f,0xbf,0x00,0x2c,0x8f,0xb6,0x00,0x28,0x7b,0xb4,0x01,0x3c,
5310x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
5320x08,0x00,0x07,0xa4,0x00,0x00,0x90,0x21,0x27,0xbd,0xff,0xc0,0xaf,0xb5,0x00,0x34,
5330xaf,0xb3,0x00,0x2c,0xaf,0xb1,0x00,0x24,0xaf,0xbf,0x00,0x38,0xaf,0xb4,0x00,0x30,
5340xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20,0x00,0xc0,0x98,0x21,0x30,0xa5,0x00,0xff,
5350xac,0xc0,0x00,0x00,0x24,0x15,0x00,0x0a,0x00,0x00,0x88,0x21,0x27,0xa8,0x00,0x10,
5360x00,0x91,0x18,0x21,0x80,0x62,0x00,0x00,0x26,0x27,0x00,0x01,0x10,0x40,0x00,0x0c,
5370x01,0x11,0x30,0x21,0x90,0x63,0x00,0x00,0x30,0xf1,0x00,0xff,0x2e,0x22,0x00,0x0a,
5380x14,0x40,0xff,0xf7,0xa0,0xc3,0x00,0x00,0x8f,0xbf,0x00,0x38,0x7b,0xb4,0x01,0xbc,
5390x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,
5400x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x23,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x1f,
5410x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x1a,0x00,0x00,0x00,0x00,0x02,0x20,0x90,0x21,
5420x12,0x40,0xff,0xf1,0x00,0x00,0x88,0x21,0x27,0xb4,0x00,0x10,0x02,0x91,0x10,0x21,
5430x90,0x44,0x00,0x00,0x0c,0x00,0x08,0x0a,0x00,0x00,0x00,0x00,0x02,0x51,0x20,0x23,
5440x24,0x84,0xff,0xff,0x30,0x84,0x00,0xff,0x02,0xa0,0x28,0x21,0x0c,0x00,0x07,0xfb,
5450x00,0x40,0x80,0x21,0x02,0x02,0x00,0x18,0x8e,0x63,0x00,0x00,0x26,0x22,0x00,0x01,
5460x30,0x51,0x00,0xff,0x02,0x32,0x20,0x2b,0x00,0x00,0x80,0x12,0x00,0x70,0x18,0x21,
5470x14,0x80,0xff,0xee,0xae,0x63,0x00,0x00,0x08,0x00,0x07,0xce,0x00,0x00,0x00,0x00,
5480x80,0x82,0x00,0x00,0x08,0x00,0x07,0xce,0xae,0x62,0x00,0x00,0x08,0x00,0x07,0xdb,
5490x24,0x15,0x00,0x10,0x08,0x00,0x07,0xdb,0x24,0x15,0x00,0x0a,0x30,0x84,0x00,0xff,
5500x30,0xa5,0x00,0xff,0x24,0x06,0x00,0x01,0x10,0x80,0x00,0x09,0x00,0x00,0x10,0x21,
5510x00,0xc5,0x00,0x18,0x24,0x42,0x00,0x01,0x30,0x42,0x00,0xff,0x00,0x44,0x18,0x2b,
5520x00,0x00,0x30,0x12,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xfa,0x00,0xc5,0x00,0x18,
5530x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,0x30,0x84,0x00,0xff,0x24,0x83,0xff,0xd0,
5540x30,0x62,0x00,0xff,0x2c,0x42,0x00,0x0a,0x14,0x40,0x00,0x06,0x00,0x00,0x00,0x00,
5550x24,0x82,0xff,0xbf,0x2c,0x42,0x00,0x06,0x14,0x40,0x00,0x02,0x24,0x83,0xff,0xc9,
5560x24,0x83,0xff,0xa9,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xc8,
5570x24,0x02,0x00,0x01,0xaf,0xbf,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,
5580xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0x10,0xa2,0x00,0x3e,
5590xaf,0xb0,0x00,0x18,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x08,0x24,0x05,0x00,0x01,
5600x00,0x00,0x10,0x21,0x8f,0xbf,0x00,0x30,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,
5610x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8c,0xc4,0x00,0x04,
5620x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x10,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,
5630x28,0x42,0x00,0x65,0x14,0x40,0x00,0x06,0x00,0x00,0x00,0x00,0x3c,0x04,0x80,0x01,
5640x0c,0x00,0x17,0xb0,0x24,0x84,0x04,0xb4,0x08,0x00,0x08,0x25,0x24,0x02,0x00,0x01,
5650x3c,0x04,0x80,0x01,0x0c,0x00,0x17,0xb0,0x24,0x84,0x04,0xc0,0x8f,0x83,0x83,0x9c,
5660x3c,0x02,0x80,0x00,0x24,0x42,0x29,0x1c,0x10,0x62,0xff,0xe5,0x00,0x40,0x90,0x21,
5670x3c,0x13,0x80,0x01,0x27,0x95,0x83,0x88,0x3c,0x14,0x80,0x01,0x27,0x90,0x83,0x8c,
5680x00,0x00,0x88,0x21,0x8e,0x03,0x00,0x08,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,
5690x10,0x62,0x00,0x08,0x26,0x64,0x04,0xcc,0x26,0x10,0x00,0x18,0x8e,0x02,0x00,0x10,
5700x00,0x00,0x00,0x00,0x14,0x52,0xff,0xf7,0x26,0x31,0x00,0x18,0x08,0x00,0x08,0x25,
5710x00,0x00,0x10,0x21,0x0c,0x00,0x17,0xb0,0x00,0x00,0x00,0x00,0x02,0x35,0x10,0x21,
5720x8c,0x44,0x00,0x00,0x0c,0x00,0x17,0xb0,0x00,0x00,0x00,0x00,0x0c,0x00,0x17,0xb0,
5730x26,0x84,0x04,0xd0,0x8e,0x04,0x00,0x00,0x0c,0x00,0x17,0xb0,0x26,0x10,0x00,0x18,
5740x08,0x00,0x08,0x4b,0x00,0x00,0x00,0x00,0x3c,0x04,0x80,0x01,0x0c,0x00,0x17,0xb0,
5750x24,0x84,0x04,0xd4,0x3c,0x04,0x80,0x01,0x0c,0x00,0x17,0x9d,0x24,0x84,0x04,0xe4,
5760x24,0x11,0x00,0x05,0x3c,0x12,0x80,0x01,0x27,0x90,0x88,0x8e,0x86,0x05,0x00,0x00,
5770x26,0x44,0x05,0x04,0x0c,0x00,0x17,0x9d,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xfb,
5780x26,0x10,0xff,0xfe,0x08,0x00,0x08,0x25,0x00,0x00,0x10,0x21,0x27,0xbd,0xff,0xd0,
5790x28,0xa2,0x00,0x02,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x2c,
5800xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0x00,0xa0,0x80,0x21,
5810x14,0x40,0x00,0x51,0x00,0xc0,0x88,0x21,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x02,
5820x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x10,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x48,
5830x24,0x05,0x00,0x01,0x8e,0x24,0x00,0x08,0x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x14,
5840x8f,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x30,0x42,0x0f,0xff,0xaf,0xa2,0x00,0x14,
5850x7b,0xa4,0x00,0xbc,0x0c,0x00,0x09,0x06,0x24,0x06,0x00,0x04,0x24,0x03,0x00,0x04,
5860x10,0x43,0x00,0x2a,0x24,0x04,0x00,0x04,0x8f,0xa2,0x00,0x10,0x3c,0x04,0x80,0x01,
5870x24,0x84,0x05,0x08,0x00,0x02,0x19,0x02,0x00,0x03,0x81,0x00,0x8f,0xa3,0x00,0x14,
5880x00,0x50,0x10,0x23,0x00,0x02,0x10,0x82,0x00,0x62,0x18,0x21,0x0c,0x00,0x17,0xb0,
5890xaf,0xa3,0x00,0x14,0x3c,0x04,0x80,0x01,0x0c,0x00,0x17,0xb0,0x24,0x84,0x05,0x30,
5900x8f,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x00,0x00,0x88,0x21,
5910x3c,0x13,0x80,0x01,0x3c,0x12,0x80,0x01,0x3c,0x14,0x80,0x01,0x0c,0x00,0x29,0xa1,
5920x24,0x04,0x27,0x10,0x32,0x23,0x00,0x03,0x02,0x00,0x28,0x21,0x10,0x60,0x00,0x1c,
5930x26,0x64,0x05,0x5c,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,0x02,0x02,0x10,0x23,
5940x28,0x42,0xff,0xfd,0x10,0x40,0x00,0x10,0x26,0x44,0x05,0x68,0x0c,0x00,0x17,0xb0,
5950x26,0x10,0x00,0x04,0x8f,0xa2,0x00,0x14,0x26,0x31,0x00,0x01,0x02,0x22,0x10,0x2b,
5960x14,0x40,0xff,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x21,0x8f,0xbf,0x00,0x2c,
5970x8f,0xb4,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x00,0x80,0x10,0x21,
5980x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x8e,0x05,0x00,0x00,0x26,0x84,0x05,0x6c,
5990x0c,0x00,0x17,0x9d,0x26,0x10,0x00,0x04,0x08,0x00,0x08,0xb1,0x00,0x00,0x00,0x00,
6000x0c,0x00,0x17,0x9d,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0xa9,0x00,0x00,0x00,0x00,
6010x08,0x00,0x08,0x87,0x24,0x02,0x00,0x01,0x0c,0x00,0x0a,0x52,0x00,0x00,0x00,0x00,
6020x08,0x00,0x08,0xb7,0x24,0x04,0x00,0x04,0x27,0xbd,0xff,0xd0,0x28,0xa2,0x00,0x03,
6030xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0xaf,0xbf,0x00,0x28,0x00,0xa0,0x88,0x21,
6040x10,0x40,0x00,0x09,0x00,0xc0,0x80,0x21,0x0c,0x00,0x0a,0x52,0x00,0x00,0x00,0x00,
6050x24,0x04,0x00,0x04,0x8f,0xbf,0x00,0x28,0x7b,0xb0,0x01,0x3c,0x00,0x80,0x10,0x21,
6060x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x02,
6070x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x10,0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x02,
6080x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x14,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x1b,
6090x24,0x05,0x00,0x01,0x8e,0x04,0x00,0x0c,0x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x18,
6100x8f,0xa4,0x00,0x10,0x8f,0xa5,0x00,0x18,0x0c,0x00,0x09,0x06,0x24,0x06,0x00,0x04,
6110x24,0x03,0x00,0x04,0x10,0x43,0xff,0xe7,0x24,0x04,0x00,0x04,0x8f,0xa2,0x00,0x18,
6120x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,0x00,0x00,0x28,0x21,0x8f,0xa2,0x00,0x10,
6130x8f,0xa4,0x00,0x14,0x24,0xa5,0x00,0x01,0xac,0x44,0x00,0x00,0x8f,0xa3,0x00,0x10,
6140x8f,0xa2,0x00,0x18,0x24,0x63,0x00,0x04,0x00,0xa2,0x10,0x2b,0x14,0x40,0xff,0xf7,
6150xaf,0xa3,0x00,0x10,0x08,0x00,0x08,0xd9,0x00,0x00,0x20,0x21,0x24,0x02,0x00,0x01,
6160x08,0x00,0x08,0xec,0xaf,0xa2,0x00,0x18,0x30,0xc6,0x00,0xff,0x00,0xa6,0x00,0x18,
6170x00,0x00,0x28,0x12,0x04,0x81,0x00,0x07,0x00,0x00,0x30,0x21,0x3c,0x02,0x80,0x01,
6180x00,0x85,0x18,0x21,0x34,0x42,0x7f,0xff,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x0b,
6190x3c,0x02,0xb0,0x03,0x3c,0x02,0xaf,0xff,0x34,0x42,0xff,0xff,0x00,0x44,0x10,0x2b,
6200x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x0a,0x00,0x85,0x18,0x21,0x34,0x42,0xff,0xff,
6210x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x12,0x3c,0x02,0xb0,0x03,0x34,0x42,0xff,0xff,
6220x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x06,0x3c,0x02,0xb0,0x07,0x3c,0x02,0xb0,0x04,
6230x34,0x42,0xff,0xff,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x09,0x3c,0x02,0xb0,0x07,
6240x34,0x42,0x00,0x3f,0x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x06,0x3c,0x02,0xb0,0x07,
6250x34,0x42,0xff,0xff,0x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x02,0x00,0x00,0x00,0x00,
6260x24,0x06,0x00,0x01,0x14,0xc0,0x00,0x11,0x24,0x02,0x00,0x04,0x3c,0x02,0xb0,0x08,
6270x34,0x42,0x0f,0xff,0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x08,0x3c,0x02,0x4f,0xf7,
6280x00,0x85,0x20,0x21,0x34,0x42,0xf0,0x00,0x00,0x82,0x20,0x21,0x34,0x03,0xef,0xff,
6290x00,0x64,0x18,0x2b,0x14,0x60,0x00,0x02,0x00,0x00,0x00,0x00,0x24,0x06,0x00,0x02,
6300x10,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08,
6310x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,0x24,0x02,0x00,0x02,0xaf,0xb0,0x00,0x18,
6320xaf,0xbf,0x00,0x1c,0x10,0xa2,0x00,0x23,0x00,0xc0,0x80,0x21,0x28,0xa2,0x00,0x03,
6330x10,0x40,0x00,0x0c,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x04,
6340x00,0x00,0x18,0x21,0x0c,0x00,0x0a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21,
6350x8f,0xbf,0x00,0x1c,0x8f,0xb0,0x00,0x18,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,
6360x27,0xbd,0x00,0x20,0x14,0xa2,0xff,0xf7,0x24,0x05,0x00,0x01,0x8c,0xc4,0x00,0x04,
6370x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x10,0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x02,
6380x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x14,0x8f,0xa4,0x00,0x10,0x00,0x00,0x00,0x00,
6390x2c,0x82,0x00,0x0b,0x10,0x40,0xff,0xee,0x24,0x03,0x00,0x04,0x00,0x04,0x10,0x80,
6400x8f,0xa4,0x00,0x14,0x27,0x83,0x91,0xc0,0x00,0x43,0x10,0x21,0x08,0x00,0x09,0x4f,
6410xac,0x44,0x00,0x00,0x8c,0xc4,0x00,0x04,0x24,0x05,0x00,0x01,0x0c,0x00,0x07,0xb6,
6420x27,0xa6,0x00,0x10,0x8f,0xa5,0x00,0x10,0x27,0x83,0x91,0xc0,0x3c,0x04,0x80,0x01,
6430x00,0x05,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x46,0x00,0x00,0x0c,0x00,0x17,0x9d,
6440x24,0x84,0x05,0x74,0x08,0x00,0x09,0x50,0x00,0x00,0x18,0x21,0x03,0xe0,0x00,0x08,
6450x00,0x00,0x00,0x00,0x8f,0x82,0x92,0x10,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
6460x8c,0x45,0x00,0x24,0x3c,0x04,0x80,0x01,0x0c,0x00,0x17,0x9d,0x24,0x84,0x05,0x88,
6470x8f,0x83,0x92,0x10,0x3c,0x04,0x80,0x01,0x8c,0x65,0x00,0x28,0x0c,0x00,0x17,0x9d,
6480x24,0x84,0x05,0x9c,0x8f,0x83,0x92,0x10,0x3c,0x04,0x80,0x01,0x8c,0x65,0x00,0x2c,
6490x0c,0x00,0x17,0x9d,0x24,0x84,0x05,0xb0,0x8f,0x83,0x92,0x10,0x3c,0x04,0x80,0x01,
6500x8c,0x65,0x00,0x30,0x0c,0x00,0x17,0x9d,0x24,0x84,0x05,0xc4,0x8f,0x83,0x92,0x10,
6510x3c,0x04,0x80,0x01,0x8c,0x65,0x00,0x34,0x0c,0x00,0x17,0x9d,0x24,0x84,0x05,0xd8,
6520x8f,0x83,0x92,0x10,0x3c,0x04,0x80,0x01,0x8c,0x65,0x00,0x38,0x0c,0x00,0x17,0x9d,
6530x24,0x84,0x05,0xec,0x8f,0x83,0x92,0x10,0x3c,0x04,0x80,0x01,0x8c,0x65,0x00,0x3c,
6540x0c,0x00,0x17,0x9d,0x24,0x84,0x05,0xfc,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
6550x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
6560x27,0xbd,0xff,0xb8,0x28,0xa5,0x00,0x04,0xaf,0xb0,0x00,0x20,0xaf,0xbf,0x00,0x40,
6570xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,
6580xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb1,0x00,0x24,0x10,0xa0,0x00,0x0b,
6590x00,0xc0,0x80,0x21,0x0c,0x00,0x0a,0x52,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,
6600x8f,0xbf,0x00,0x40,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,
6610x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x8c,0xc4,0x00,0x04,
6620x24,0x05,0x00,0x01,0x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x10,0x8e,0x04,0x00,0x08,
6630x24,0x05,0x00,0x01,0x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x14,0x8e,0x04,0x00,0x0c,
6640x24,0x05,0x00,0x01,0x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x18,0x8f,0xa3,0x00,0x18,
6650x00,0x00,0x00,0x00,0x10,0x60,0x00,0x3a,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x33,
6660x3c,0x04,0x80,0x01,0x97,0xb0,0x00,0x12,0x8f,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,
6670x02,0x02,0x10,0x2b,0x10,0x40,0xff,0xe2,0x3c,0x15,0x80,0x01,0x3c,0x02,0x80,0x01,
6680x24,0x52,0x06,0x3c,0x3c,0x14,0xb0,0x06,0x24,0x13,0x00,0x01,0x3c,0x17,0xb0,0x08,
6690x3c,0x16,0x80,0x01,0x32,0x02,0x00,0x01,0x02,0x00,0x28,0x21,0x10,0x40,0x00,0x1f,
6700x26,0xa4,0x06,0x30,0x8f,0xa3,0x00,0x18,0x00,0x10,0x10,0xc0,0x00,0x54,0x10,0x21,
6710x10,0x60,0x00,0x14,0x02,0x40,0x20,0x21,0x00,0x10,0x10,0xc0,0x00,0x57,0x10,0x21,
6720x10,0x73,0x00,0x09,0x26,0xc4,0x06,0x44,0x8f,0xa2,0x00,0x14,0x26,0x03,0x00,0x01,
6730x30,0x70,0xff,0xff,0x02,0x02,0x10,0x2b,0x14,0x40,0xff,0xee,0x00,0x00,0x00,0x00,
6740x08,0x00,0x09,0xb4,0x00,0x00,0x00,0x00,0x8c,0x51,0x00,0x00,0x00,0x00,0x00,0x00,
6750x32,0x25,0x00,0xff,0x0c,0x00,0x17,0x9d,0x00,0x00,0x00,0x00,0x08,0x00,0x09,0xe6,
6760x00,0x00,0x00,0x00,0x8c,0x51,0x00,0x00,0x0c,0x00,0x17,0x9d,0x00,0x11,0x2c,0x02,
6770x32,0x25,0x00,0xff,0x08,0x00,0x09,0xf1,0x02,0x40,0x20,0x21,0x0c,0x00,0x17,0x9d,
6780x00,0x00,0x00,0x00,0x08,0x00,0x09,0xdd,0x00,0x00,0x00,0x00,0x24,0x84,0x06,0x10,
6790x0c,0x00,0x17,0xb0,0x00,0x00,0x00,0x00,0x08,0x00,0x09,0xcd,0x00,0x00,0x00,0x00,
6800x3c,0x04,0x80,0x01,0x08,0x00,0x0a,0x00,0x24,0x84,0x06,0x50,0x00,0xa0,0x10,0x21,
6810x27,0xbd,0xff,0xd8,0x28,0x42,0x00,0x04,0xaf,0xb0,0x00,0x20,0xaf,0xbf,0x00,0x24,
6820x00,0xc0,0x80,0x21,0x24,0x05,0x00,0x01,0x10,0x40,0x00,0x08,0x27,0xa6,0x00,0x10,
6830x0c,0x00,0x0a,0x52,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x24,
6840x8f,0xb0,0x00,0x20,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x8e,0x04,0x00,0x04,
6850x0c,0x00,0x07,0xb6,0x00,0x00,0x00,0x00,0x8e,0x04,0x00,0x08,0x24,0x05,0x00,0x01,
6860x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x14,0x8e,0x04,0x00,0x0c,0x24,0x05,0x00,0x01,
6870x0c,0x00,0x07,0xb6,0x27,0xa6,0x00,0x18,0x08,0x00,0x0a,0x13,0x24,0x02,0x00,0x01,
6880x24,0x03,0x00,0x01,0x00,0x65,0x10,0x2a,0x27,0xbd,0xff,0xd8,0x00,0xa0,0x40,0x21,
6890x10,0x40,0x00,0x0b,0x00,0xc0,0x38,0x21,0x00,0x03,0x20,0x80,0x00,0x87,0x10,0x21,
6900x8c,0x45,0x00,0x00,0x24,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x8c,0xa6,0x00,0x00,
6910x00,0x9d,0x20,0x21,0x00,0x68,0x10,0x2a,0x14,0x40,0xff,0xf7,0xac,0x86,0xff,0xfc,
6920x8f,0xa3,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x0b,0x00,0x00,0x00,0x00,
6930x24,0x02,0x00,0x02,0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
6940x27,0xbd,0x00,0x28,0x93,0xa2,0x00,0x07,0x00,0x00,0x00,0x00,0xa3,0x82,0x87,0xec,
6950x08,0x00,0x0a,0x3b,0x00,0x00,0x00,0x00,0x93,0xa2,0x00,0x07,0x00,0x00,0x00,0x00,
6960xa3,0x82,0x91,0xb0,0x08,0x00,0x0a,0x3b,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,
6970x3c,0x04,0x80,0x01,0xaf,0xbf,0x00,0x10,0x18,0xa0,0x00,0x03,0x24,0x84,0x06,0x78,
6980x0c,0x00,0x17,0xb0,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x24,0x02,0x00,0x01,
6990x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x27,0xbd,0xff,0xe8,0xaf,0xb0,0x00,0x10,
7000x00,0x80,0x80,0x21,0x3c,0x04,0x80,0x01,0xaf,0xbf,0x00,0x14,0x0c,0x00,0x17,0xb0,
7010x24,0x84,0x06,0x8c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21,0x27,0x83,0x83,0x88,
7020x00,0x02,0x10,0xc0,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08,0x0c,0x00,0x17,0xb0,
7030x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
7040x27,0xbd,0x00,0x18,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe8,
7050x34,0x63,0x00,0x20,0x24,0x42,0x29,0x94,0x3c,0x04,0xb0,0x03,0xaf,0xbf,0x00,0x14,
7060xac,0x62,0x00,0x00,0xaf,0xb0,0x00,0x10,0x34,0x84,0x00,0x2c,0x8c,0x83,0x00,0x00,
7070xa7,0x80,0xc2,0x40,0x00,0x03,0x12,0x02,0x00,0x03,0x2d,0x02,0x30,0x42,0x0f,0xff,
7080xa3,0x83,0xc2,0x48,0xa7,0x85,0xc2,0x4c,0xa7,0x82,0xc2,0x4a,0xa7,0x80,0xc2,0x42,
7090xa7,0x80,0xc2,0x44,0xa7,0x80,0xc2,0x46,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x05,0x00,
7100x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,0x0c,0x00,0x0b,0xed,
7110x00,0x40,0x80,0x21,0x3c,0x02,0xf7,0xff,0x34,0x42,0xff,0xff,0x02,0x02,0x80,0x24,
7120x02,0x00,0x28,0x21,0x0c,0x00,0x0b,0xed,0x24,0x04,0x05,0x00,0x3c,0x02,0xb0,0x03,
7130x3c,0x03,0xb0,0x03,0x34,0x42,0x01,0x08,0x34,0x63,0x01,0x18,0x8c,0x45,0x00,0x00,
7140x8c,0x64,0x00,0x00,0x3c,0x02,0x00,0x0f,0x3c,0x03,0x00,0x4c,0x30,0x84,0x02,0x00,
7150x34,0x63,0x4b,0x40,0xaf,0x85,0xc2,0x50,0x10,0x80,0x00,0x06,0x34,0x42,0x42,0x40,
7160xaf,0x83,0xc2,0x54,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
7170x27,0xbd,0x00,0x18,0xaf,0x82,0xc2,0x54,0x08,0x00,0x0a,0x95,0x00,0x00,0x00,0x00,
7180x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,0x34,0x63,0x00,0x20,
7190x24,0x42,0x2a,0x70,0x30,0x84,0x00,0xff,0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c,
7200xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,
7210xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xac,0x62,0x00,0x00,
7220x10,0x80,0x00,0x1c,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x08,0x00,0x00,0x00,0x00,
7230x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,
7240x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0xa7,0x80,0xc2,0x40,
7250xa7,0x80,0xc2,0x42,0xa7,0x80,0xc2,0x44,0xa7,0x80,0xc2,0x46,0x0c,0x00,0x0b,0xfa,
7260x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,
7270x0c,0x00,0x0b,0xed,0x00,0x40,0x80,0x21,0x3c,0x05,0xf7,0xff,0x34,0xa5,0xff,0xff,
7280x02,0x05,0x28,0x24,0x0c,0x00,0x0b,0xed,0x24,0x04,0x05,0x00,0x08,0x00,0x0a,0xb0,
7290x00,0x00,0x00,0x00,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x05,0xa0,0x24,0x04,0x05,0xa4,
7300x0c,0x00,0x0b,0xfa,0x00,0x02,0xbc,0x02,0x24,0x04,0x05,0xa8,0x00,0x02,0xb4,0x02,
7310x0c,0x00,0x0b,0xfa,0x30,0x55,0xff,0xff,0x00,0x40,0x80,0x21,0x97,0x84,0xc2,0x40,
7320x97,0x82,0xc2,0x42,0x97,0x83,0xc2,0x46,0x02,0xe4,0x20,0x23,0x02,0xa2,0x10,0x23,
7330x00,0x82,0x20,0x21,0x97,0x82,0xc2,0x44,0x32,0x14,0xff,0xff,0x02,0x83,0x18,0x23,
7340x02,0xc2,0x10,0x23,0x00,0x82,0x20,0x21,0x93,0x82,0xc2,0x48,0x00,0x83,0x20,0x21,
7350x30,0x84,0xff,0xff,0x00,0x82,0x10,0x2b,0x14,0x40,0x00,0xaa,0x00,0x00,0x00,0x00,
7360x97,0x82,0xc2,0x4c,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x7f,
7370x00,0x00,0x00,0x00,0x97,0x82,0xc2,0x4a,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,
7380x10,0x40,0x00,0x3a,0x00,0x00,0x00,0x00,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x04,0x50,
7390x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,0x10,0x40,0x00,0x13,
7400x24,0x02,0x00,0x20,0x12,0x22,0x00,0x17,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,
7410x26,0x31,0x00,0x01,0x00,0x51,0x80,0x25,0x02,0x00,0x28,0x21,0x0c,0x00,0x0b,0xed,
7420x24,0x04,0x04,0x50,0x02,0x00,0x28,0x21,0x0c,0x00,0x0b,0xed,0x24,0x04,0x04,0x58,
7430x02,0x00,0x28,0x21,0x0c,0x00,0x0b,0xed,0x24,0x04,0x04,0x60,0x02,0x00,0x28,0x21,
7440x24,0x04,0x04,0x68,0x0c,0x00,0x0b,0xed,0x00,0x00,0x00,0x00,0xa7,0x97,0xc2,0x40,
7450xa7,0x95,0xc2,0x42,0xa7,0x96,0xc2,0x44,0xa7,0x94,0xc2,0x46,0x08,0x00,0x0a,0xb0,
7460x00,0x00,0x00,0x00,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,
7470x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,
7480x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
7490x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x08,
7500x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,
7510x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x0c,0x00,0x0b,0xed,
7520x24,0x04,0x02,0x2c,0x08,0x00,0x0a,0xf7,0x24,0x02,0xff,0x80,0x0c,0x00,0x0b,0xfa,
7530x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20,0x16,0x22,0xff,0xdb,
7540x00,0x00,0x00,0x00,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,
7550x02,0x40,0x28,0x21,0x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x2c,0x0c,0x00,0x0b,0xfa,
7560x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c,0x0c,0x00,0x0b,0xfa,0x00,0x02,0x9e,0x02,
7570x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,
7580x14,0x60,0x00,0x1d,0x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,
7590x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,
7600x24,0x04,0x02,0x2c,0x0c,0x00,0x0b,0xed,0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,
7610x08,0x00,0x0b,0x05,0x24,0x04,0x02,0x2c,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x08,
7620x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,
7630x24,0x03,0x00,0x02,0x14,0x43,0xff,0xee,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
7640x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x08,
7650x08,0x00,0x0b,0x41,0x3c,0x02,0xff,0xff,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x08,
7660x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,
7670x14,0x43,0xff,0xdf,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,
7680x3c,0x03,0x00,0x80,0x08,0x00,0x0b,0x56,0x00,0x43,0x28,0x25,0x0c,0x00,0x0b,0xfa,
7690x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,
7700x10,0x40,0xff,0x9a,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x04,0x24,0x02,0xff,0x80,
7710x02,0x02,0x10,0x24,0x08,0x00,0x0a,0xf9,0x26,0x31,0x00,0x02,0x0c,0x00,0x0b,0xfa,
7720x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,
7730x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,
7740x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
7750x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x08,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x2c,
7760x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,
7770x02,0x40,0x28,0x21,0x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x2c,0x08,0x00,0x0b,0x70,
7780x24,0x02,0xff,0x80,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x04,0x50,0x00,0x40,0x80,0x21,
7790x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x1d,0x2e,0x22,0x00,0x21,
7800x14,0x40,0xff,0x72,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x26,0x31,0xff,0xff,
7810x00,0x51,0x80,0x25,0x24,0x04,0x04,0x50,0x0c,0x00,0x0b,0xed,0x02,0x00,0x28,0x21,
7820x24,0x04,0x04,0x58,0x0c,0x00,0x0b,0xed,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x60,
7830x0c,0x00,0x0b,0xed,0x02,0x00,0x28,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x0b,0xed,
7840x24,0x04,0x04,0x68,0x24,0x02,0x00,0x20,0x16,0x22,0xff,0x60,0x00,0x00,0x00,0x00,
7850x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,
7860x34,0x42,0x3f,0xff,0x02,0x42,0x10,0x24,0x08,0x00,0x0b,0x47,0x34,0x52,0x80,0x00,
7870x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,
7880x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x2c,0x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x58,
7890x24,0x04,0x02,0x5c,0x0c,0x00,0x0b,0xfa,0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,
7900x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x20,
7910x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,
7920x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,
7930x0c,0x00,0x0b,0xed,0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x0b,0xed,
7940x24,0x04,0x02,0x2c,0x08,0x00,0x0b,0x94,0x2e,0x22,0x00,0x21,0x0c,0x00,0x0b,0xfa,
7950x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,
7960x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02,0x14,0x43,0xff,0xec,0x00,0x00,0x00,0x00,
7970x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
7980x0c,0x00,0x0b,0xed,0x24,0x04,0x02,0x08,0x08,0x00,0x0b,0xc4,0x3c,0x02,0xff,0xff,
7990x0c,0x00,0x0b,0xfa,0x24,0x04,0x02,0x08,0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,
8000x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,0x14,0x43,0xff,0xdc,0x3c,0x03,0x00,0x80,
8010x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x08,0x00,0x0b,0xdc,
8020x00,0x43,0x28,0x25,0x30,0x83,0x00,0x03,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x23,
8030x3c,0x02,0xb0,0x0a,0x00,0x82,0x20,0x21,0xac,0x85,0x00,0x00,0x00,0x00,0x18,0x21,
8040x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x0a,0x14,0x40,0xff,0xfe,0x24,0x63,0x00,0x01,
8050x03,0xe0,0x00,0x08,0x24,0x63,0xff,0xff,0x30,0x86,0x00,0x03,0x00,0x04,0x28,0x40,
8060x3c,0x03,0xb0,0x0a,0x00,0xa6,0x10,0x23,0x00,0x43,0x10,0x21,0x24,0x04,0xff,0xff,
8070xac,0x44,0x10,0x00,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x0a,
8080x14,0x40,0xff,0xfe,0x24,0x63,0x00,0x01,0x24,0x63,0xff,0xff,0x00,0xa6,0x18,0x23,
8090x3c,0x02,0xb0,0x0a,0x00,0x62,0x18,0x21,0x8c,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,
8100x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x30,0x34,
8110x24,0x03,0x00,0x01,0x34,0xa5,0x00,0x20,0x3c,0x06,0xb0,0x03,0xac,0xa2,0x00,0x00,
8120x34,0xc6,0x01,0x04,0xa0,0x83,0x00,0x48,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
8130xa0,0x80,0x00,0x06,0xa0,0x80,0x00,0x07,0xa0,0x80,0x00,0x08,0xa0,0x80,0x00,0x09,
8140xa0,0x80,0x00,0x0a,0xa0,0x80,0x00,0x11,0xa0,0x80,0x00,0x13,0xa0,0x80,0x00,0x49,
8150x94,0xc2,0x00,0x00,0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x24,0x00,0x02,0x14,0x00,
8160x00,0x02,0x14,0x03,0x30,0x43,0x00,0xff,0x30,0x42,0xff,0x00,0xa4,0x83,0x00,0x46,
8170xa4,0x82,0x00,0x44,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,0xac,0x80,0x00,0x30,
8180xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xac,0x80,0x00,0x3c,0x03,0xe0,0x00,0x08,
8190xac,0x80,0x00,0x40,0x84,0x83,0x00,0x0c,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x20,
8200x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x96,0x44,
8210x00,0x43,0x10,0x21,0x8c,0x48,0x00,0x18,0x3c,0x02,0x80,0x00,0x24,0x42,0x30,0xc4,
8220xac,0xe2,0x00,0x00,0x8d,0x03,0x00,0x08,0x80,0x82,0x00,0x13,0x00,0x05,0x2c,0x00,
8230x00,0x03,0x1e,0x02,0x00,0x02,0x12,0x00,0x30,0x63,0x00,0x7e,0x00,0x62,0x18,0x21,
8240x00,0x65,0x18,0x21,0x3c,0x02,0xc0,0x00,0x3c,0x05,0xb0,0x05,0x34,0x42,0x04,0x00,
8250x24,0x63,0x00,0x01,0x3c,0x07,0xb0,0x05,0x3c,0x08,0xb0,0x05,0x34,0xa5,0x04,0x20,
8260xac,0xa3,0x00,0x00,0x00,0xc2,0x30,0x21,0x34,0xe7,0x04,0x24,0x35,0x08,0x02,0x28,
8270x24,0x02,0x00,0x01,0x24,0x03,0x00,0x20,0xac,0xe6,0x00,0x00,0xac,0x82,0x00,0x3c,
8280x03,0xe0,0x00,0x08,0xa1,0x03,0x00,0x00,0x27,0xbd,0xff,0xc0,0x00,0x07,0x60,0x80,
8290x27,0x82,0xba,0x40,0xaf,0xb7,0x00,0x34,0xaf,0xb5,0x00,0x2c,0xaf,0xb3,0x00,0x24,
8300xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38,0xaf,0xb6,0x00,0x30,0xaf,0xb4,0x00,0x28,
8310xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x01,0x82,0x10,0x21,
8320x8c,0x43,0x00,0x00,0x3c,0x07,0xb0,0x03,0x3c,0x02,0x80,0x00,0x94,0x71,0x00,0x14,
8330x34,0xe7,0x00,0x20,0x24,0x42,0x31,0x58,0x3c,0x03,0xb0,0x05,0xac,0xe2,0x00,0x00,
8340x34,0x63,0x01,0x28,0x90,0x67,0x00,0x00,0x00,0x11,0xa8,0xc0,0x02,0xb1,0x18,0x21,
8350x27,0x82,0x96,0x44,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x00,0x05,0x2c,0x00,
8360x00,0x07,0x3e,0x00,0x28,0xc2,0x00,0x03,0x00,0xc0,0x98,0x21,0xaf,0xa4,0x00,0x40,
8370x00,0x05,0x6c,0x03,0x8c,0x68,0x00,0x18,0x02,0xa0,0x58,0x21,0x10,0x40,0x01,0x4f,
8380x00,0x07,0xbe,0x03,0x00,0xd7,0x10,0x07,0x30,0x57,0x00,0x01,0x01,0x71,0x10,0x21,
8390x27,0x83,0x96,0x48,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x80,0x4e,0x00,0x06,
8400x8d,0x03,0x00,0x00,0x8d,0x0f,0x00,0x04,0x8d,0x0a,0x00,0x08,0x8d,0x10,0x00,0x0c,
8410x11,0xc0,0x00,0x1c,0x00,0x00,0xa0,0x21,0x27,0x82,0xba,0x40,0x01,0x82,0x10,0x21,
8420x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,
8430x30,0x63,0x00,0x04,0x14,0x60,0x00,0x13,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,
8440x90,0x43,0x00,0x00,0x2a,0x64,0x00,0x04,0x10,0x80,0x01,0x26,0x30,0x65,0x00,0x01,
8450x8f,0xa3,0x00,0x40,0x00,0x00,0x00,0x00,0x90,0x62,0x00,0x09,0x00,0x00,0x00,0x00,
8460x12,0x62,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x21,0x14,0xa0,0x00,0x03,
8470x00,0x00,0x38,0x21,0x12,0xe0,0x00,0x03,0x38,0xf4,0x00,0x01,0x24,0x07,0x00,0x01,
8480x38,0xf4,0x00,0x01,0x01,0x71,0x10,0x21,0x00,0x02,0x38,0x80,0x27,0x83,0x96,0x50,
8490x00,0xe3,0x48,0x21,0x91,0x25,0x00,0x00,0x00,0x0f,0x11,0xc3,0x2c,0xa3,0x00,0x04,
8500x00,0x03,0xa0,0x0b,0x12,0x80,0x00,0xc7,0x30,0x52,0x00,0x01,0x93,0x88,0xc2,0x2a,
8510x00,0x0a,0x16,0x42,0x30,0x4a,0x00,0x3f,0x2d,0x06,0x00,0x0c,0x10,0xc0,0x00,0xaf,
8520x00,0xa0,0x20,0x21,0x2c,0xa2,0x00,0x10,0x14,0x40,0x00,0x04,0x00,0x88,0x10,0x2b,
8530x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x04,0x00,0x88,0x10,0x2b,0x10,0x40,0x00,0x0b,
8540x01,0x71,0x10,0x21,0x27,0x85,0xc1,0x5c,0x00,0x08,0x10,0x40,0x00,0x48,0x10,0x21,
8550x00,0x45,0x10,0x21,0x90,0x48,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0x18,0x2b,
8560x14,0x60,0xff,0xfa,0x00,0x08,0x10,0x40,0x01,0x71,0x10,0x21,0x00,0x02,0x10,0x80,
8570x27,0x83,0x96,0x48,0x00,0x43,0x10,0x21,0x31,0xc4,0x00,0x01,0x10,0x80,0x00,0x94,
8580xa0,0x48,0x00,0x07,0x24,0x0d,0x00,0x0e,0x24,0x11,0x01,0x06,0x27,0x82,0xba,0x40,
8590x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x24,0x16,0x00,0x01,0x00,0x11,0xa8,0xc0,
8600x90,0x62,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x04,0xa0,0x62,0x00,0x16,
8610x00,0x0f,0x1b,0x43,0x30,0x7e,0x00,0x01,0x00,0x0a,0x10,0x40,0x00,0x12,0x19,0xc0,
8620x00,0x5e,0x10,0x21,0x00,0x08,0x22,0x00,0x00,0x43,0x10,0x21,0x00,0x44,0x10,0x21,
8630x00,0x0d,0x1c,0x00,0x00,0x10,0x82,0x02,0x01,0x00,0x28,0x21,0x00,0x00,0x20,0x21,
8640x00,0x43,0x90,0x21,0x0c,0x00,0x01,0xdd,0x32,0x10,0x07,0xff,0x00,0x16,0x12,0x80,
8650x00,0x10,0x84,0x80,0x02,0x22,0x10,0x21,0x00,0x50,0x10,0x21,0x3c,0x03,0xc0,0x00,
8660x16,0x60,0x00,0x2b,0x00,0x43,0x80,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x00,
8670x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x52,0x00,0x00,0x34,0x63,0x04,0x04,
8680x34,0x84,0x02,0x28,0x24,0x02,0x00,0x01,0xac,0x70,0x00,0x00,0xa0,0x82,0x00,0x00,
8690x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,0x90,0x44,0x00,0x00,0x8f,0xa2,0x00,0x40,
8700x30,0x86,0x00,0x01,0x90,0x43,0x00,0x09,0x00,0x00,0x00,0x00,0x02,0x63,0x18,0x26,
8710x00,0x03,0x30,0x0b,0x14,0xc0,0x00,0x03,0x00,0x00,0x28,0x21,0x12,0xe0,0x00,0x03,
8720x02,0xb1,0x10,0x21,0x24,0x05,0x00,0x01,0x02,0xb1,0x10,0x21,0x27,0x83,0x96,0x48,
8730x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x84,0x48,0x00,0x04,0x00,0xa0,0x30,0x21,
8740x03,0xc0,0x20,0x21,0x02,0x60,0x28,0x21,0x02,0x80,0x38,0x21,0x0c,0x00,0x00,0x70,
8750xaf,0xa8,0x00,0x10,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,
8760x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,
8770x24,0x02,0x00,0x01,0x12,0x62,0x00,0x3d,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x02,
8780x12,0x62,0x00,0x31,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x03,0x12,0x62,0x00,0x25,
8790x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,0x12,0x62,0x00,0x19,0x3c,0x02,0xb0,0x05,
8800x24,0x02,0x00,0x11,0x12,0x62,0x00,0x0d,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x12,
8810x16,0x62,0xff,0xcf,0x3c,0x02,0xb0,0x05,0x3c,0x03,0xb0,0x05,0x34,0x42,0x04,0x20,
8820x3c,0x04,0xb0,0x05,0x34,0x63,0x04,0x24,0xac,0x52,0x00,0x00,0x34,0x84,0x02,0x28,
8830xac,0x70,0x00,0x00,0x08,0x00,0x0c,0xf7,0x24,0x02,0x00,0x20,0x34,0x42,0x04,0x40,
8840x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x52,0x00,0x00,0x34,0x63,0x04,0x44,
8850x34,0x84,0x02,0x28,0x24,0x02,0x00,0x40,0x08,0x00,0x0c,0xf7,0xac,0x70,0x00,0x00,
8860x34,0x42,0x04,0x28,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x52,0x00,0x00,
8870x34,0x63,0x04,0x2c,0x34,0x84,0x02,0x28,0x24,0x02,0xff,0x80,0x08,0x00,0x0c,0xf7,
8880xac,0x70,0x00,0x00,0x34,0x42,0x04,0x18,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,
8890xac,0x52,0x00,0x00,0x34,0x63,0x04,0x1c,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x08,
8900x08,0x00,0x0c,0xf7,0xac,0x70,0x00,0x00,0x34,0x42,0x04,0x10,0x3c,0x03,0xb0,0x05,
8910x3c,0x04,0xb0,0x05,0xac,0x52,0x00,0x00,0x34,0x63,0x04,0x14,0x34,0x84,0x02,0x28,
8920x24,0x02,0x00,0x04,0x08,0x00,0x0c,0xf7,0xac,0x70,0x00,0x00,0x34,0x42,0x04,0x08,
8930x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x52,0x00,0x00,0x34,0x63,0x04,0x0c,
8940x34,0x84,0x02,0x28,0x24,0x02,0x00,0x02,0x08,0x00,0x0c,0xf7,0xac,0x70,0x00,0x00,
8950x24,0x0d,0x00,0x14,0x08,0x00,0x0c,0xcf,0x24,0x11,0x01,0x02,0x30,0xa2,0x00,0x07,
8960x24,0x44,0x00,0x0c,0x00,0x88,0x18,0x2b,0x10,0x60,0x00,0x0c,0x25,0x02,0x00,0x04,
8970x27,0x85,0xc1,0x5c,0x00,0x08,0x10,0x40,0x00,0x48,0x10,0x21,0x00,0x45,0x10,0x21,
8980x90,0x48,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0x18,0x2b,0x14,0x60,0xff,0xfa,
8990x00,0x08,0x10,0x40,0x2d,0x06,0x00,0x0c,0x25,0x02,0x00,0x04,0x08,0x00,0x0c,0xc6,
9000x00,0x46,0x40,0x0a,0x27,0x82,0xba,0x40,0x01,0x82,0x20,0x21,0x8c,0x86,0x00,0x00,
9010x00,0x00,0x00,0x00,0x90,0xc2,0x00,0x19,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x07,
9020x00,0x00,0x00,0x00,0x27,0x82,0x96,0x60,0x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00,
9030x00,0x00,0x00,0x00,0x10,0x60,0x00,0x12,0x00,0x00,0x00,0x00,0x90,0xc3,0x00,0x16,
9040x27,0x82,0x96,0x48,0x00,0xe2,0x10,0x21,0x34,0x63,0x00,0x20,0x90,0x48,0x00,0x07,
9050xa0,0xc3,0x00,0x16,0x8c,0x84,0x00,0x00,0x00,0x0a,0x16,0x42,0x30,0x4a,0x00,0x3f,
9060x90,0x83,0x00,0x16,0x24,0x0d,0x00,0x18,0x24,0x11,0x01,0x03,0x30,0x63,0x00,0xfb,
9070x24,0x16,0x00,0x01,0x24,0x15,0x08,0x18,0x08,0x00,0x0c,0xd8,0xa0,0x83,0x00,0x16,
9080x8d,0x02,0x00,0x04,0x00,0x0a,0x1c,0x42,0x30,0x42,0x00,0x10,0x14,0x40,0x00,0x15,
9090x30,0x6a,0x00,0x3f,0x81,0x22,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x11,
9100x30,0x6a,0x00,0x3e,0x27,0x83,0x96,0x58,0x00,0xe3,0x18,0x21,0x80,0x64,0x00,0x00,
9110x27,0x83,0xbb,0xb8,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,
9120x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x05,
9130x90,0x43,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x24,0x30,0x63,0x00,0x01,
9140x01,0x43,0x50,0x25,0x27,0x85,0xba,0x40,0x01,0x85,0x28,0x21,0x8c,0xa6,0x00,0x00,
9150x01,0x71,0x10,0x21,0x27,0x83,0x96,0x50,0x90,0xc4,0x00,0x16,0x00,0x02,0x10,0x80,
9160x00,0x43,0x10,0x21,0x30,0x84,0x00,0xdf,0x90,0x48,0x00,0x00,0xa0,0xc4,0x00,0x16,
9170x8c,0xa3,0x00,0x00,0x80,0xd6,0x00,0x12,0x90,0x62,0x00,0x16,0x08,0x00,0x0c,0xd7,
9180x30,0x42,0x00,0xfb,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x42,0x90,0x62,0x00,0x00,
9190x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0x14,0x40,0xfe,0xdc,0x00,0x00,0x00,0x00,
9200x8f,0xa3,0x00,0x40,0x00,0x00,0x00,0x00,0x90,0x62,0x00,0x09,0x00,0x00,0x00,0x00,
9210x02,0x62,0x10,0x26,0x08,0x00,0x0c,0x9f,0x00,0x02,0x28,0x0b,0x24,0x02,0x00,0x10,
9220x10,0xc2,0x00,0x08,0x24,0x02,0x00,0x11,0x10,0xc2,0xfe,0xaf,0x00,0x07,0x17,0x83,
9230x24,0x02,0x00,0x12,0x14,0xc2,0xfe,0xad,0x00,0x07,0x17,0x43,0x08,0x00,0x0c,0x7f,
9240x30,0x57,0x00,0x01,0x08,0x00,0x0c,0x7f,0x00,0x07,0xbf,0xc2,0x00,0x04,0x10,0x40,
9250x27,0x83,0x86,0xb0,0x00,0x43,0x10,0x21,0x00,0x80,0x40,0x21,0x94,0x44,0x00,0x00,
9260x2d,0x07,0x00,0x04,0x24,0xc2,0x00,0x03,0x00,0x47,0x30,0x0a,0x00,0x86,0x00,0x18,
9270x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x37,0x5c,
9280xac,0x62,0x00,0x00,0x2d,0x06,0x00,0x10,0x00,0x00,0x20,0x12,0x00,0x04,0x22,0x42,
9290x24,0x84,0x00,0x01,0x24,0x83,0x00,0xc0,0x10,0xe0,0x00,0x0b,0x24,0x82,0x00,0x60,
9300x00,0x40,0x20,0x21,0x00,0x65,0x20,0x0a,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,
9310x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x00,0x44,0x20,0x04,
9320x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x24,0x85,0x00,0x28,0x24,0x83,0x00,0x24,
9330x31,0x02,0x00,0x08,0x14,0xc0,0xff,0xf4,0x24,0x84,0x00,0x14,0x00,0x60,0x20,0x21,
9340x08,0x00,0x0d,0xee,0x00,0xa2,0x20,0x0b,0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x03,
9350x3c,0x02,0x80,0x00,0xaf,0xb0,0x00,0x10,0x24,0x42,0x37,0xf8,0x00,0x80,0x80,0x21,
9360x34,0x63,0x00,0x20,0x3c,0x04,0xb0,0x03,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
9370xaf,0xbf,0x00,0x1c,0x83,0xb1,0x00,0x33,0x83,0xa8,0x00,0x37,0x34,0x84,0x01,0x10,
9380xac,0x62,0x00,0x00,0x2e,0x02,0x00,0x10,0x00,0xe0,0x90,0x21,0x8c,0x87,0x00,0x00,
9390x14,0x40,0x00,0x0c,0x2e,0x02,0x00,0x0c,0x3c,0x02,0x00,0x0f,0x34,0x42,0xf0,0x00,
9400x00,0xe2,0x10,0x24,0x14,0x40,0x00,0x37,0x32,0x02,0x00,0x08,0x32,0x02,0x00,0x07,
9410x27,0x83,0x87,0x60,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,
9420x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x03,0x02,0x00,0x20,0x21,0x32,0x02,0x00,0x0f,
9430x24,0x44,0x00,0x0c,0x00,0x87,0x10,0x06,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x07,
9440x2c,0x82,0x00,0x0c,0x00,0x04,0x10,0x80,0x27,0x83,0xba,0x90,0x00,0x43,0x10,0x21,
9450x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x82,0x00,0x0c,0x14,0x40,0x00,0x05,
9460x00,0x05,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21,
9470x24,0x44,0x00,0x04,0x15,0x00,0x00,0x02,0x24,0x06,0x00,0x20,0x24,0x06,0x00,0x0e,
9480x0c,0x00,0x0d,0xd7,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0x3c,0x02,0xb0,0x03,
9490x34,0x42,0x01,0x00,0x90,0x43,0x00,0x00,0x2e,0x04,0x00,0x04,0x24,0x02,0x00,0x10,
9500x24,0x05,0x00,0x0a,0x00,0x44,0x28,0x0a,0x30,0x63,0x00,0x01,0x14,0x60,0x00,0x02,
9510x00,0x05,0x10,0x40,0x00,0xa0,0x10,0x21,0x30,0x45,0x00,0xff,0x00,0xc5,0x10,0x21,
9520x24,0x46,0x00,0x46,0x02,0x26,0x18,0x04,0xa6,0x43,0x00,0x00,0x8f,0xbf,0x00,0x1c,
9530x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08,
9540x27,0xbd,0x00,0x20,0x10,0x40,0xff,0xcf,0x2e,0x02,0x00,0x0c,0x32,0x02,0x00,0x07,
9550x27,0x83,0x87,0x58,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x08,0x00,0x0e,0x1c,
9560x02,0x04,0x80,0x23,0x27,0xbd,0xff,0xb8,0x00,0x05,0x38,0x80,0x27,0x82,0xba,0x40,
9570xaf,0xbe,0x00,0x40,0xaf,0xb6,0x00,0x38,0xaf,0xb4,0x00,0x30,0xaf,0xbf,0x00,0x44,
9580xaf,0xb7,0x00,0x3c,0xaf,0xb5,0x00,0x34,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,
9590xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0x00,0xe2,0x38,0x21,0x8c,0xe6,0x00,0x00,
9600xaf,0xa5,0x00,0x4c,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,
9610x24,0x42,0x39,0x54,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,0xa0,0xc3,0x00,0x12,
9620x8c,0xe5,0x00,0x00,0x94,0xc3,0x00,0x06,0x90,0xa2,0x00,0x16,0xa4,0xc3,0x00,0x14,
9630x27,0x83,0x96,0x40,0x34,0x42,0x00,0x08,0xa0,0xa2,0x00,0x16,0x8c,0xe8,0x00,0x00,
9640xaf,0xa4,0x00,0x48,0x27,0x82,0x96,0x44,0x95,0x11,0x00,0x14,0x00,0x00,0x00,0x00,
9650x00,0x11,0xa0,0xc0,0x02,0x91,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x82,0x10,0x21,
9660x8c,0x53,0x00,0x18,0x00,0x83,0x18,0x21,0x84,0x75,0x00,0x06,0x8e,0x65,0x00,0x08,
9670x8e,0x66,0x00,0x04,0x8e,0x67,0x00,0x04,0x00,0x05,0x1c,0x82,0x00,0x06,0x31,0x42,
9680x27,0x82,0x96,0x50,0x30,0x63,0x00,0x01,0x30,0xc6,0x00,0x01,0x00,0x82,0x20,0x21,
9690xa5,0x15,0x00,0x1a,0x00,0x05,0x14,0x42,0xaf,0xa3,0x00,0x18,0xaf,0xa6,0x00,0x1c,
9700x30,0xe7,0x00,0x10,0x30,0x56,0x00,0x01,0x80,0x97,0x00,0x06,0x14,0xe0,0x00,0x42,
9710x00,0x05,0xf7,0xc2,0x80,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x3f,
9720x02,0x91,0x10,0x21,0x93,0x90,0xc2,0x29,0x00,0x00,0x00,0x00,0x2e,0x02,0x00,0x0c,
9730x14,0x40,0x00,0x06,0x02,0x00,0x20,0x21,0x00,0x16,0x10,0x40,0x00,0x43,0x10,0x21,
9740x00,0x02,0x11,0x00,0x02,0x02,0x10,0x21,0x24,0x44,0x00,0x04,0x02,0x91,0x10,0x21,
9750x00,0x02,0x10,0x80,0x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0x00,0x80,0x80,0x21,
9760xa0,0x44,0x00,0x03,0xa0,0x44,0x00,0x00,0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,
9770x0c,0x00,0x0d,0xd7,0x02,0xa0,0x30,0x21,0x02,0x91,0x18,0x21,0x00,0x03,0x88,0x80,
9780x00,0x40,0x90,0x21,0x27,0x82,0x96,0x60,0x02,0x22,0x10,0x21,0x8c,0x44,0x00,0x00,
9790x26,0xe3,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x04,0x25,0xc2,
9800x00,0x03,0x18,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x18,0x40,0x03,0xc4,0x20,0x24,
9810x14,0x80,0x00,0x10,0x02,0x63,0x38,0x21,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x48,
9820x27,0x82,0x96,0x48,0x02,0x22,0x10,0x21,0x02,0xa0,0x28,0x21,0xa4,0x52,0x00,0x04,
9830x0c,0x00,0x0c,0x56,0x00,0xc0,0x38,0x21,0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,
9840x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,
9850x27,0xbd,0x00,0x48,0x8f,0xa2,0x00,0x1c,0x8f,0xa6,0x00,0x18,0x02,0x00,0x20,0x21,
9860x02,0xc0,0x28,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x0d,0xfe,0xaf,0xa0,0x00,0x14,
9870x08,0x00,0x0e,0xba,0x02,0x42,0x90,0x21,0x02,0x91,0x10,0x21,0x00,0x02,0x10,0x80,
9880x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,0x08,0x00,0x0e,0xa6,
9890xa0,0x50,0x00,0x03,0x27,0xbd,0xff,0xb8,0xaf,0xb1,0x00,0x24,0x8f,0xb1,0x00,0x5c,
9900x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x3b,0x64,
9910xaf,0xbe,0x00,0x40,0xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38,0xaf,0xb5,0x00,0x34,
9920xaf,0xb4,0x00,0x30,0xaf,0xa5,0x00,0x4c,0x8f,0xb5,0x00,0x58,0xaf,0xbf,0x00,0x44,
9930xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20,0x00,0xe0,0xb0,0x21,
9940xac,0x62,0x00,0x00,0x00,0x80,0xf0,0x21,0x00,0x00,0xb8,0x21,0x16,0x20,0x00,0x2b,
9950x00,0x00,0xa0,0x21,0x27,0x85,0xba,0x40,0x00,0x07,0x10,0x80,0x00,0x45,0x10,0x21,
9960x8c,0x53,0x00,0x00,0x00,0x15,0x18,0x80,0x00,0x65,0x18,0x21,0x92,0x62,0x00,0x16,
9970x8c,0x72,0x00,0x00,0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x2d,0x00,0x00,0x00,0x00,
9980x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x28,
9990x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x18,
10000x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x14,
10010x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x3c,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0f,
10020x3c,0x03,0xb0,0x09,0x3c,0x05,0xb0,0x05,0x34,0x63,0x01,0x44,0x34,0xa5,0x02,0x52,
10030x94,0x66,0x00,0x00,0x90,0xa2,0x00,0x00,0x8f,0xa3,0x00,0x4c,0x00,0x00,0x00,0x00,
10040x00,0x62,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x04,0x30,0xc6,0xff,0xff,
10050x2c,0xc2,0x00,0x41,0x10,0x40,0x00,0x09,0x24,0x05,0x00,0x14,0x02,0x20,0x10,0x21,
10060x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,
10070x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x0c,0x00,0x0c,0x31,
10080x24,0x06,0x01,0x07,0x24,0x02,0x00,0x01,0x08,0x00,0x0f,0x1b,0xa3,0xc2,0x00,0x11,
10090x10,0xc0,0x00,0x1c,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x17,0x00,0xc0,0x88,0x21,
10100x96,0x54,0x00,0x1a,0x02,0xa0,0xb8,0x21,0x12,0x20,0xff,0xed,0x02,0x20,0x10,0x21,
10110x27,0x83,0xba,0x40,0x00,0x17,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,
10120x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x28,0x80,0x86,0x00,0x12,0x8c,0x62,0x00,0x00,
10130x00,0x14,0x2c,0x00,0x00,0x05,0x2c,0x03,0x00,0x46,0x10,0x21,0x8f,0xa6,0x00,0x4c,
10140x02,0xe0,0x38,0x21,0x03,0xc0,0x20,0x21,0x0c,0x00,0x0c,0x56,0xac,0x62,0x00,0x00,
10150x08,0x00,0x0f,0x1b,0xaf,0xd1,0x00,0x40,0x96,0x74,0x00,0x1a,0x08,0x00,0x0f,0x2e,
10160x02,0xc0,0xb8,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x50,0x00,0x00,
10170x02,0x60,0x20,0x21,0x0c,0x00,0x23,0x25,0x02,0x00,0x28,0x21,0x30,0x42,0x00,0xff,
10180x02,0x00,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x23,0x25,0xaf,0xa2,0x00,0x18,
10190x30,0x50,0x00,0xff,0x8f,0xa2,0x00,0x18,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0xc3,
10200x00,0x00,0x00,0x00,0x12,0x00,0x00,0x18,0x24,0x11,0x00,0x01,0x96,0x63,0x00,0x14,
10210x96,0x44,0x00,0x14,0x27,0x85,0x96,0x40,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
10220x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x00,0x04,0x18,0xc0,0x8c,0x46,0x00,0x08,
10230x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x00,0x06,0x17,0x02,
10240x24,0x04,0x00,0xff,0x8c,0x63,0x00,0x08,0x10,0x44,0x00,0xac,0x00,0x03,0x17,0x02,
10250x10,0x44,0x00,0xab,0x3c,0x02,0x80,0x00,0x00,0x66,0x18,0x2b,0x24,0x11,0x00,0x02,
10260x24,0x02,0x00,0x01,0x00,0x43,0x88,0x0a,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x45,
10270x24,0x02,0x00,0x02,0x16,0x22,0xff,0xbc,0x00,0x00,0x00,0x00,0x96,0x49,0x00,0x14,
10280x27,0x82,0x96,0x44,0x02,0xa0,0xb8,0x21,0x00,0x09,0x50,0xc0,0x01,0x49,0x18,0x21,
10290x00,0x03,0x40,0x80,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00,
10300x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42,
10310x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,0x14,0x40,0x00,0x2c,
10320x30,0x87,0x00,0x01,0x27,0x83,0x96,0x58,0x01,0x03,0x18,0x21,0x80,0x64,0x00,0x00,
10330x27,0x83,0xba,0xe0,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,
10340x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x45,0x00,0x00,
10350x00,0x00,0x00,0x00,0x2c,0xa3,0x00,0x0c,0x14,0x60,0x00,0x07,0x01,0x49,0x10,0x21,
10360x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0xa2,0x10,0x21,
10370x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x96,0x50,
10380x00,0x43,0x10,0x21,0xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x24,0x02,0x00,0x08,
10390x12,0x02,0x00,0x0a,0x24,0x02,0x00,0x01,0x02,0x40,0x20,0x21,0x0c,0x00,0x23,0xa1,
10400xaf,0xa2,0x00,0x10,0x30,0x54,0xff,0xff,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,
10410x02,0x02,0x10,0x25,0x08,0x00,0x0f,0x2e,0xa2,0x42,0x00,0x16,0x02,0x40,0x20,0x21,
10420x0c,0x00,0x23,0x52,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0f,0xa6,0x30,0x54,0xff,0xff,
10430x27,0x82,0x96,0x50,0x01,0x02,0x10,0x21,0x90,0x45,0x00,0x00,0x08,0x00,0x0f,0x9f,
10440xa0,0x45,0x00,0x03,0x96,0x69,0x00,0x14,0x02,0xc0,0xb8,0x21,0x24,0x0b,0x00,0x01,
10450x00,0x09,0x10,0xc0,0x00,0x49,0x18,0x21,0x00,0x03,0x40,0x80,0x00,0x40,0x50,0x21,
10460x27,0x82,0x96,0x44,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00,
10470x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42,
10480x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,0x10,0x40,0x00,0x0d,
10490x30,0x87,0x00,0x01,0x27,0x82,0x96,0x58,0x01,0x02,0x10,0x21,0x80,0x43,0x00,0x00,
10500x00,0x00,0x58,0x21,0x00,0x03,0x11,0x00,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,
10510x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xbb,0xb0,0x00,0x43,0x10,0x21,
10520xa0,0x40,0x00,0x04,0x11,0x60,0x00,0x3a,0x00,0x00,0x00,0x00,0x01,0x49,0x10,0x21,
10530x00,0x02,0x20,0x80,0x27,0x85,0x96,0x50,0x00,0x85,0x10,0x21,0x80,0x43,0x00,0x05,
10540x00,0x00,0x00,0x00,0x14,0x60,0x00,0x2d,0x01,0x49,0x10,0x21,0x27,0x83,0x96,0x58,
10550x00,0x83,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xba,0xe0,0x00,0x04,0x11,0x00,
10560x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,
10570x00,0x43,0x10,0x21,0x90,0x45,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xa3,0x00,0x0c,
10580x14,0x60,0x00,0x07,0x01,0x49,0x10,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,
10590x00,0x02,0x11,0x00,0x00,0xa2,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,
10600x00,0x02,0x10,0x80,0x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0xa0,0x45,0x00,0x03,
10610xa0,0x45,0x00,0x00,0x8f,0xa3,0x00,0x18,0x24,0x02,0x00,0x08,0x10,0x62,0x00,0x0b,
10620x02,0x60,0x20,0x21,0x24,0x02,0x00,0x01,0x0c,0x00,0x23,0xa1,0xaf,0xa2,0x00,0x10,
10630x8f,0xa3,0x00,0x18,0x30,0x54,0xff,0xff,0x92,0x62,0x00,0x16,0x00,0x00,0x00,0x00,
10640x00,0x62,0x10,0x25,0x08,0x00,0x0f,0x2e,0xa2,0x62,0x00,0x16,0x0c,0x00,0x23,0x52,
10650xaf,0xa0,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,
10660x00,0x45,0x10,0x21,0x90,0x45,0x00,0x00,0x08,0x00,0x0f,0xf9,0xa0,0x45,0x00,0x03,
10670x27,0x85,0x96,0x50,0x08,0x00,0x10,0x0b,0x01,0x49,0x10,0x21,0x3c,0x02,0x80,0x00,
10680x00,0x62,0x18,0x26,0x08,0x00,0x0f,0x6a,0x00,0xc2,0x30,0x26,0x12,0x00,0xff,0x57,
10690x24,0x02,0x00,0x01,0x08,0x00,0x0f,0x6f,0x24,0x11,0x00,0x02,0x3c,0x03,0xb0,0x03,
10700x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,0x24,0x42,0x40,0x6c,0x34,0x63,0x00,0x20,
10710x3c,0x05,0xb0,0x05,0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,
10720xaf,0xbf,0x00,0x28,0xaf,0xb0,0x00,0x18,0xac,0x62,0x00,0x00,0x34,0xa5,0x02,0x42,
10730x90,0xa2,0x00,0x00,0x00,0x80,0x90,0x21,0x24,0x11,0x00,0x10,0x30,0x53,0x00,0xff,
10740x24,0x02,0x00,0x10,0x12,0x22,0x00,0xcf,0x00,0x00,0x18,0x21,0x24,0x02,0x00,0x11,
10750x12,0x22,0x00,0xc1,0x24,0x02,0x00,0x12,0x12,0x22,0x00,0xb4,0x00,0x00,0x00,0x00,
10760x14,0x60,0x00,0xad,0xae,0x43,0x00,0x40,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,
10770x8c,0x44,0x00,0x00,0x3c,0x03,0x00,0x02,0x34,0x63,0x00,0xff,0x00,0x83,0x80,0x24,
10780x00,0x10,0x14,0x43,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x8e,0x42,0x00,0x34,
10790x00,0x00,0x00,0x00,0x14,0x40,0x00,0x92,0x00,0x00,0x00,0x00,0x93,0x83,0x91,0x51,
10800x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,0x10,0x40,0x00,0x04,0x32,0x10,0x00,0xff,
10810x00,0x10,0x11,0xc3,0x14,0x40,0x00,0x86,0x00,0x00,0x00,0x00,0x16,0x00,0x00,0x15,
10820x02,0x00,0x10,0x21,0x26,0x22,0x00,0x01,0x30,0x51,0x00,0xff,0x2e,0x23,0x00,0x13,
10830x14,0x60,0xff,0xdb,0x24,0x03,0x00,0x02,0x12,0x63,0x00,0x73,0x24,0x02,0x00,0x05,
10840x2a,0x62,0x00,0x03,0x10,0x40,0x00,0x58,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,
10850x12,0x62,0x00,0x4b,0x02,0x40,0x20,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,
10860x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x70,0x00,0xff,0x12,0x00,0x00,0x06,
10870x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,
10880x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,
10890x24,0x02,0x00,0x07,0x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,
10900xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x24,
10910x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,
10920x16,0x00,0xff,0xec,0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,
10930x24,0x02,0x00,0x05,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,
10940xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x28,
10950x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,
10960x16,0x00,0xff,0xdc,0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,
10970x24,0x02,0x00,0x03,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,
10980xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x2c,
10990x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,
11000x16,0x00,0xff,0xcc,0x02,0x00,0x10,0x21,0x92,0x46,0x00,0x07,0x8e,0x43,0x00,0x30,
11010x24,0x02,0x00,0x02,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,
11020xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x30,
11030x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,0x08,0x00,0x10,0x61,0x30,0x42,0x00,0xff,
11040x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07,0x00,0x00,0x28,0x21,
11050x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,
11060x08,0x00,0x10,0x5a,0xae,0x42,0x00,0x24,0x12,0x62,0x00,0x0d,0x24,0x02,0x00,0x03,
11070x24,0x02,0x00,0x08,0x16,0x62,0xff,0xa8,0x02,0x40,0x20,0x21,0x92,0x46,0x00,0x07,
11080x8e,0x42,0x00,0x30,0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa3,0x00,0x10,
11090x0c,0x00,0x0e,0xd9,0xaf,0xa2,0x00,0x14,0x08,0x00,0x10,0x5a,0xae,0x42,0x00,0x30,
11100x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,
11110x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,
11120x08,0x00,0x10,0x5a,0xae,0x42,0x00,0x2c,0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,
11130x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,
11140x0c,0x00,0x0e,0xd9,0xaf,0xa3,0x00,0x14,0x08,0x00,0x10,0x5a,0xae,0x42,0x00,0x28,
11150x0c,0x00,0x01,0x60,0x24,0x04,0x00,0x01,0x08,0x00,0x10,0x4b,0x00,0x00,0x00,0x00,
11160x8f,0x84,0xba,0x80,0xae,0x40,0x00,0x34,0x94,0x85,0x00,0x14,0x0c,0x00,0x1f,0xdd,
11170x00,0x00,0x00,0x00,0x93,0x83,0x91,0x51,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,
11180x10,0x40,0xff,0x69,0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x60,0x00,0x00,0x20,0x21,
11190x08,0x00,0x10,0x43,0x00,0x00,0x00,0x00,0x02,0x40,0x20,0x21,0x0c,0x00,0x0e,0x55,
11200x02,0x20,0x28,0x21,0x08,0x00,0x10,0x37,0x3c,0x02,0xb0,0x05,0x8e,0x42,0x00,0x3c,
11210x00,0x00,0x00,0x00,0x14,0x40,0xff,0x4a,0x00,0x00,0x00,0x00,0x8f,0x82,0xba,0x88,
11220x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,
11230x08,0x00,0x10,0x34,0xae,0x43,0x00,0x3c,0x8e,0x42,0x00,0x38,0x00,0x00,0x00,0x00,
11240x14,0x40,0xff,0x3d,0x24,0x02,0x00,0x12,0x8f,0x82,0xba,0x84,0x00,0x00,0x00,0x00,
11250x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x10,0x34,
11260xae,0x43,0x00,0x38,0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x30,
11270x24,0x02,0x00,0x11,0x8f,0x82,0xba,0x80,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,
11280x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x10,0x34,0xae,0x43,0x00,0x34,
11290x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe0,0x34,0x63,0x00,0x20,
11300x24,0x42,0x44,0x20,0x3c,0x08,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xac,0x62,0x00,0x00,
11310x35,0x08,0x01,0x00,0xaf,0xbf,0x00,0x18,0xaf,0xb0,0x00,0x10,0x91,0x03,0x00,0x00,
11320x00,0xa0,0x48,0x21,0x24,0x11,0x00,0x0a,0x2c,0xa5,0x00,0x04,0x24,0x02,0x00,0x10,
11330x00,0x45,0x88,0x0a,0x30,0x63,0x00,0x01,0x00,0xc0,0x28,0x21,0x14,0x60,0x00,0x02,
11340x00,0x11,0x40,0x40,0x02,0x20,0x40,0x21,0x84,0x83,0x00,0x0c,0x31,0x11,0x00,0xff,
11350x01,0x20,0x20,0x21,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
11360x27,0x83,0x96,0x48,0x00,0x43,0x10,0x21,0x84,0x43,0x00,0x04,0x24,0x06,0x00,0x0e,
11370x10,0xe0,0x00,0x06,0x02,0x23,0x80,0x21,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,
11380x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x0d,0xd7,
11390x00,0x00,0x00,0x00,0x02,0x11,0x18,0x21,0x08,0x00,0x11,0x2a,0x00,0x62,0x80,0x21,
11400x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,
11410xaf,0xb2,0x00,0x18,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
11420x84,0x82,0x00,0x0c,0x3c,0x06,0xb0,0x03,0x34,0xc6,0x00,0x20,0x00,0x02,0x18,0xc0,
11430x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x27,0x82,0x96,0x44,0x00,0x62,0x10,0x21,
11440x8c,0x53,0x00,0x18,0x3c,0x02,0x80,0x00,0x24,0x42,0x44,0xd0,0xac,0xc2,0x00,0x00,
11450x8e,0x70,0x00,0x08,0x27,0x82,0x96,0x48,0x00,0x62,0x18,0x21,0x90,0x71,0x00,0x07,
11460x00,0x10,0x86,0x43,0x32,0x10,0x00,0x01,0x00,0xa0,0x38,0x21,0x02,0x00,0x30,0x21,
11470x00,0xa0,0xa0,0x21,0x02,0x20,0x28,0x21,0x0c,0x00,0x11,0x08,0x00,0x80,0xa8,0x21,
11480x02,0x20,0x20,0x21,0x02,0x00,0x28,0x21,0x24,0x06,0x00,0x14,0x0c,0x00,0x0d,0xd7,
11490x00,0x40,0x90,0x21,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x40,0x94,0x64,0x00,0x00,
11500x3c,0x0a,0xb0,0x09,0x3c,0x0b,0xb0,0x09,0x00,0x04,0x21,0x40,0x00,0x82,0x28,0x23,
11510x35,0x4a,0x01,0x10,0x35,0x6b,0x01,0x14,0x3c,0x0c,0xb0,0x09,0x3c,0x08,0xb0,0x09,
11520x3c,0x06,0xb0,0x09,0x00,0x44,0x10,0x2b,0x01,0x40,0x48,0x21,0x35,0x8c,0x01,0x20,
11530x01,0x60,0x38,0x21,0x35,0x08,0x01,0x24,0x34,0xc6,0x01,0x02,0x10,0x40,0x00,0x02,
11540x02,0x45,0x18,0x2b,0x00,0xa3,0x90,0x0b,0x86,0xa3,0x00,0x0c,0x27,0x84,0x96,0x50,
11550x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,
11560x80,0x43,0x00,0x06,0xa4,0xd2,0x00,0x00,0x24,0x64,0x00,0x03,0x28,0x62,0x00,0x00,
11570x00,0x82,0x18,0x0b,0x00,0x03,0x18,0x83,0x00,0x03,0x18,0x80,0x12,0x80,0x00,0x11,
11580x02,0x63,0x28,0x21,0x8c,0xa2,0x00,0x0c,0x8c,0xa3,0x00,0x08,0x00,0x02,0x14,0x00,
11590x00,0x03,0x1c,0x02,0x00,0x43,0x10,0x21,0xad,0x22,0x00,0x00,0x8c,0xa3,0x00,0x0c,
11600x00,0x00,0x00,0x00,0x00,0x03,0x1c,0x02,0xa4,0xe3,0x00,0x00,0x8f,0xbf,0x00,0x28,
11610x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
11620x27,0xbd,0x00,0x30,0x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0xad,0x42,0x00,0x00,
11630x8c,0xa4,0x00,0x08,0x00,0x00,0x00,0x00,0xa5,0x64,0x00,0x00,0x78,0xa2,0x00,0x7c,
11640x00,0x00,0x00,0x00,0x00,0x03,0x1c,0x00,0x00,0x02,0x14,0x02,0x00,0x62,0x18,0x21,
11650xad,0x83,0x00,0x00,0x8c,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x02,
11660x08,0x00,0x11,0x87,0xa5,0x02,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb2,0x00,0x18,
11670xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0xaf,0xb1,0x00,0x14,0x84,0x82,0x00,0x0c,
11680x00,0x80,0x90,0x21,0x3c,0x05,0xb0,0x03,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,
11690x00,0x04,0x20,0x80,0x27,0x82,0x96,0x44,0x00,0x82,0x10,0x21,0x8c,0x51,0x00,0x18,
11700x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x46,0x78,0x27,0x83,0x96,0x48,
11710xac,0xa2,0x00,0x00,0x00,0x83,0x20,0x21,0x3c,0x02,0xb0,0x03,0x90,0x86,0x00,0x07,
11720x34,0x42,0x01,0x00,0x8e,0x23,0x00,0x08,0x90,0x44,0x00,0x00,0x2c,0xc5,0x00,0x04,
11730x24,0x02,0x00,0x10,0x24,0x10,0x00,0x0a,0x00,0x45,0x80,0x0a,0x00,0x03,0x1e,0x43,
11740x30,0x84,0x00,0x01,0x30,0x65,0x00,0x01,0x14,0x80,0x00,0x02,0x00,0x10,0x10,0x40,
11750x02,0x00,0x10,0x21,0x00,0xc0,0x20,0x21,0x24,0x06,0x00,0x20,0x0c,0x00,0x0d,0xd7,
11760x30,0x50,0x00,0xff,0x86,0x44,0x00,0x0c,0x27,0x85,0x96,0x50,0x3c,0x06,0xb0,0x09,
11770x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,
11780x80,0x64,0x00,0x06,0x00,0x50,0x10,0x21,0x34,0xc6,0x01,0x02,0x24,0x85,0x00,0x03,
11790x28,0x83,0x00,0x00,0x00,0xa3,0x20,0x0b,0x00,0x04,0x20,0x83,0x00,0x04,0x20,0x80,
11800xa4,0xc2,0x00,0x00,0x02,0x24,0x20,0x21,0x8c,0x83,0x00,0x04,0x3c,0x02,0xb0,0x09,
11810x34,0x42,0x01,0x10,0xac,0x43,0x00,0x00,0x8c,0x86,0x00,0x08,0x3c,0x02,0xb0,0x09,
11820x34,0x42,0x01,0x14,0xa4,0x46,0x00,0x00,0x8c,0x85,0x00,0x0c,0x8c,0x82,0x00,0x08,
11830x3c,0x06,0xb0,0x09,0x00,0x05,0x2c,0x00,0x00,0x02,0x14,0x02,0x00,0xa2,0x28,0x21,
11840x34,0xc6,0x01,0x20,0xac,0xc5,0x00,0x00,0x8c,0x83,0x00,0x0c,0x3c,0x05,0xb0,0x09,
11850x34,0xa5,0x01,0x24,0x00,0x03,0x1c,0x02,0xa4,0xa3,0x00,0x00,0x92,0x42,0x00,0x0a,
11860x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x30,0x00,0x02,0x13,0x00,0x24,0x42,0x00,0x04,
11870x30,0x42,0xff,0xff,0xa4,0x62,0x00,0x00,0x86,0x44,0x00,0x0c,0x27,0x83,0x96,0x58,
11880x8f,0xbf,0x00,0x1c,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,
11890x00,0x43,0x10,0x21,0x94,0x44,0x00,0x02,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,
11900x3c,0x05,0xb0,0x09,0x34,0xa5,0x01,0x32,0xa4,0xa4,0x00,0x00,0x03,0xe0,0x00,0x08,
11910x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,
11920xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20,0x00,0xa0,0x80,0x21,0x24,0x63,0x48,0x04,
11930x00,0x05,0x2c,0x43,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,
11940x10,0xa0,0x00,0x05,0x00,0x80,0x88,0x21,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,
11950x14,0x40,0x00,0xaf,0x00,0x00,0x00,0x00,0x32,0x10,0x00,0xff,0x12,0x00,0x00,0x47,
11960x00,0x00,0x10,0x21,0x24,0x02,0x00,0x08,0x12,0x02,0x00,0x9c,0x2a,0x02,0x00,0x09,
11970x10,0x40,0x00,0x84,0x24,0x02,0x00,0x40,0x24,0x04,0x00,0x02,0x12,0x04,0x00,0x74,
11980x2a,0x02,0x00,0x03,0x10,0x40,0x00,0x64,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,
11990x12,0x02,0x00,0x55,0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x11,0x92,0x27,0x00,0x11,
12000x10,0x40,0x00,0x4e,0x00,0x00,0x00,0x00,0x92,0x26,0x00,0x0a,0x24,0x02,0x00,0x12,
12010x10,0x46,0x00,0x09,0x30,0xc2,0x00,0xff,0x27,0x83,0xba,0x40,0x00,0x02,0x10,0x80,
12020x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x94,0x83,0x00,0x14,
12030x00,0x00,0x00,0x00,0xa6,0x23,0x00,0x0c,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x40,
12040x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x03,0xa2,0x23,0x00,0x10,
12050x14,0x60,0x00,0x2b,0x30,0x65,0x00,0x01,0x30,0xc2,0x00,0xff,0x27,0x83,0xba,0x40,
12060x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x82,0x23,0x00,0x12,
12070x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x30,0x42,0x00,0x01,
12080x00,0x62,0x18,0x21,0x00,0x03,0x26,0x00,0x14,0x80,0x00,0x18,0xa2,0x23,0x00,0x12,
12090x00,0x07,0x16,0x00,0x14,0x40,0x00,0x11,0x24,0x02,0x00,0x01,0x96,0x23,0x00,0x0c,
12100x27,0x84,0x96,0x50,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
12110x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x02,0xb0,0x00,
12120x00,0x65,0x18,0x21,0x00,0x62,0x18,0x21,0x90,0x64,0x00,0x00,0x90,0x62,0x00,0x04,
12130xa2,0x20,0x00,0x15,0xa3,0x80,0x92,0x15,0x24,0x02,0x00,0x01,0x8f,0xbf,0x00,0x18,
12140x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x11,0x9e,
12150x02,0x20,0x20,0x21,0x92,0x27,0x00,0x11,0x08,0x00,0x12,0x49,0x00,0x07,0x16,0x00,
12160x0c,0x00,0x11,0x34,0x02,0x20,0x20,0x21,0x86,0x23,0x00,0x0c,0x27,0x84,0x96,0x48,
12170x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x20,0x21,
12180x90,0x85,0x00,0x07,0x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0xa2,0x25,0x00,0x13,
12190x90,0x83,0x00,0x07,0x08,0x00,0x12,0x61,0xa0,0x43,0x00,0x02,0x92,0x26,0x00,0x0a,
12200x08,0x00,0x12,0x2a,0x30,0xc2,0x00,0xff,0x8e,0x22,0x00,0x24,0x00,0x00,0x00,0x00,
12210x10,0x50,0x00,0x07,0xa2,0x20,0x00,0x08,0x24,0x02,0x00,0x07,0xa2,0x22,0x00,0x0a,
12220x92,0x22,0x00,0x27,0xae,0x20,0x00,0x24,0x08,0x00,0x12,0x22,0xa2,0x22,0x00,0x04,
12230x08,0x00,0x12,0x7b,0x24,0x02,0x00,0x06,0x16,0x02,0xff,0x9f,0x24,0x02,0x00,0x01,
12240x8e,0x23,0x00,0x2c,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x07,0xa2,0x24,0x00,0x08,
12250x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2f,0xae,0x20,0x00,0x2c,
12260x08,0x00,0x12,0x22,0xa2,0x22,0x00,0x06,0x08,0x00,0x12,0x8a,0xa2,0x20,0x00,0x0a,
12270x8e,0x22,0x00,0x28,0x24,0x03,0x00,0x01,0x24,0x04,0x00,0x01,0x10,0x44,0x00,0x07,
12280xa2,0x23,0x00,0x08,0x24,0x02,0x00,0x05,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2b,
12290xae,0x20,0x00,0x28,0x08,0x00,0x12,0x22,0xa2,0x22,0x00,0x05,0x08,0x00,0x12,0x96,
12300x24,0x02,0x00,0x04,0x12,0x02,0x00,0x10,0x2a,0x02,0x00,0x41,0x10,0x40,0x00,0x08,
12310x24,0x02,0x00,0x80,0x24,0x02,0x00,0x20,0x16,0x02,0xff,0x7f,0x24,0x02,0x00,0x12,
12320xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x12,0x22,0xae,0x20,0x00,0x3c,
12330x16,0x02,0xff,0x79,0x24,0x02,0x00,0x10,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,
12340x08,0x00,0x12,0x22,0xae,0x20,0x00,0x34,0x24,0x02,0x00,0x11,0xa2,0x22,0x00,0x0a,
12350xa2,0x22,0x00,0x08,0x08,0x00,0x12,0x22,0xae,0x20,0x00,0x38,0x8e,0x24,0x00,0x30,
12360x24,0x02,0x00,0x03,0x24,0x03,0x00,0x01,0x10,0x83,0x00,0x07,0xa2,0x22,0x00,0x08,
12370x24,0x02,0x00,0x02,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x33,0xae,0x20,0x00,0x30,
12380x08,0x00,0x12,0x22,0xa2,0x22,0x00,0x07,0x08,0x00,0x12,0xba,0xa2,0x24,0x00,0x0a,
12390x8f,0x84,0xba,0x80,0xae,0x20,0x00,0x34,0x94,0x85,0x00,0x14,0x0c,0x00,0x1f,0xdd,
12400x32,0x10,0x00,0xff,0x08,0x00,0x12,0x13,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
12410x3c,0x02,0x80,0x00,0x24,0x42,0x4b,0x1c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,
12420x80,0xa2,0x00,0x15,0x3c,0x06,0xb0,0x05,0x10,0x40,0x00,0x0a,0x34,0xc6,0x02,0x54,
12430x83,0x83,0x92,0x15,0x00,0x00,0x00,0x00,0xac,0x83,0x00,0x24,0x8c,0xc2,0x00,0x00,
12440x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,
12450xac,0x82,0x00,0x28,0x8c,0x82,0x00,0x2c,0x3c,0x06,0xb0,0x05,0x34,0xc6,0x04,0x50,
12460x00,0x02,0x18,0x43,0x30,0x63,0x00,0x01,0x10,0x40,0x00,0x04,0x30,0x45,0x00,0x01,
12470xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x24,0x90,0xc2,0x00,0x00,
12480x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x30,0x43,0x00,0x02,0x30,0x42,0x00,0x01,
12490xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x24,0x3c,0x03,0xb0,0x03,
12500x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd8,0x34,0x63,0x00,0x20,0x24,0x42,0x4b,0xac,
12510xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x20,0xaf,0xb0,0x00,0x18,
12520x90,0xa6,0x00,0x0a,0x27,0x83,0xba,0x40,0x00,0xa0,0x88,0x21,0x00,0x06,0x10,0x80,
12530x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x80,0xa5,0x00,0x11,0x92,0x03,0x00,0x12,
12540x10,0xa0,0x00,0x04,0xa2,0x20,0x00,0x15,0x24,0x02,0x00,0x12,0x10,0xc2,0x00,0xd9,
12550x00,0x00,0x00,0x00,0x82,0x22,0x00,0x12,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x67,
12560x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x12,0xa2,0x00,0x00,0x19,0x86,0x23,0x00,0x0c,
12570x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
12580x27,0x83,0x96,0x60,0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0x92,0x03,0x00,0x16,
12590x00,0x00,0x00,0x00,0x30,0x63,0x00,0xdf,0xa2,0x03,0x00,0x16,0x82,0x02,0x00,0x12,
12600x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x92,0x23,0x00,0x08,
12610x00,0x00,0x00,0x00,0x14,0x60,0x00,0x45,0x24,0x02,0x00,0x01,0xa2,0x20,0x00,0x04,
12620x92,0x08,0x00,0x04,0x00,0x00,0x00,0x00,0x15,0x00,0x00,0x1e,0x24,0x02,0x00,0x01,
12630x92,0x07,0x00,0x0a,0xa2,0x02,0x00,0x17,0x92,0x02,0x00,0x16,0x30,0xe3,0x00,0xff,
12640x30,0x42,0x00,0xe4,0x10,0x60,0x00,0x03,0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,
12650xa2,0x02,0x00,0x16,0x11,0x00,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,
12660x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0xa2,0x02,0x00,0x16,0x92,0x02,0x00,0x17,
12670x00,0x00,0x00,0x00,0x10,0x40,0x00,0x08,0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x06,
12680x00,0x00,0x00,0x00,0xa6,0x02,0x00,0x14,0x8f,0xbf,0x00,0x20,0x7b,0xb0,0x00,0xfc,
12690x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x96,0x02,0x00,0x00,0x08,0x00,0x13,0x36,
12700xa6,0x02,0x00,0x14,0x92,0x07,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03,
12710x00,0x00,0x00,0x00,0x08,0x00,0x13,0x22,0xa2,0x00,0x00,0x17,0x96,0x04,0x00,0x00,
12720x96,0x05,0x00,0x06,0x27,0x86,0x96,0x40,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,
12730x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,
12740x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x66,0x00,0x08,0x8c,0x45,0x00,0x08,
12750x3c,0x03,0x80,0x00,0x00,0xc3,0x20,0x24,0x10,0x80,0x00,0x08,0x00,0xa3,0x10,0x24,
12760x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0x80,0x00,0x02,0x24,0x03,0x00,0x01,
12770x00,0xa6,0x18,0x2b,0x08,0x00,0x13,0x22,0xa2,0x03,0x00,0x17,0x10,0x40,0xff,0xfd,
12780x00,0xa6,0x18,0x2b,0x08,0x00,0x13,0x56,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,
12790x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0xb8,
12800x00,0x00,0x00,0x00,0x08,0x00,0x13,0x1c,0xa2,0x20,0x00,0x07,0x08,0x00,0x13,0x1c,
12810xa2,0x20,0x00,0x06,0x08,0x00,0x13,0x1c,0xa2,0x20,0x00,0x05,0x82,0x22,0x00,0x10,
12820x00,0x00,0x00,0x00,0x14,0x40,0x00,0x68,0x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x48,
12830x3c,0x02,0xb0,0x09,0x92,0x25,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,
12840x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x3a,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,
12850x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,
12860x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x86,0x23,0x00,0x0c,
12870x96,0x26,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,
12880x27,0x83,0x96,0x44,0x00,0xa3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,
12890x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x18,
12900x00,0x00,0x00,0x00,0x93,0x82,0x91,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,
12910x14,0x40,0x00,0x0a,0x24,0x05,0x00,0x24,0x00,0x06,0x2c,0x00,0x00,0x05,0x2c,0x03,
12920x0c,0x00,0x1f,0xdd,0x02,0x00,0x20,0x21,0x92,0x02,0x00,0x16,0xa2,0x00,0x00,0x12,
12930x30,0x42,0x00,0xe7,0x08,0x00,0x13,0x13,0xa2,0x02,0x00,0x16,0xf0,0xc5,0x00,0x06,
12940x00,0x00,0x28,0x12,0x27,0x82,0x96,0x40,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,
12950x3c,0x04,0x00,0x80,0x96,0x26,0x00,0x0c,0x08,0x00,0x13,0x93,0x00,0x06,0x2c,0x00,
12960x27,0x83,0x96,0x50,0x27,0x82,0x96,0x58,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,
12970x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05,0x00,0x00,0x30,0x21,0x0c,0x00,0x25,0xc4,
12980x24,0x07,0x00,0x01,0x96,0x26,0x00,0x0c,0x08,0x00,0x13,0x8d,0x00,0x00,0x00,0x00,
12990x14,0x40,0xff,0xce,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
13000x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x13,0x7c,0x00,0xa2,0x10,0x07,
13010x86,0x26,0x00,0x0c,0x3c,0x03,0xb0,0x09,0x34,0x42,0x01,0x72,0x34,0x63,0x01,0x78,
13020x94,0x47,0x00,0x00,0x8c,0x65,0x00,0x00,0x00,0x06,0x10,0xc0,0x00,0x46,0x10,0x21,
13030x3c,0x04,0xb0,0x09,0xae,0x25,0x00,0x1c,0x34,0x84,0x01,0x7c,0x27,0x83,0x96,0x44,
13040x00,0x02,0x10,0x80,0x8c,0x85,0x00,0x00,0x00,0x43,0x10,0x21,0x8c,0x43,0x00,0x18,
13050xae,0x25,0x00,0x20,0xa6,0x27,0x00,0x18,0x8c,0x66,0x00,0x08,0x02,0x20,0x20,0x21,
13060x0c,0x00,0x13,0xe2,0x00,0x00,0x28,0x21,0x86,0x25,0x00,0x18,0x8e,0x26,0x00,0x1c,
13070x8e,0x27,0x00,0x20,0x02,0x20,0x20,0x21,0x0c,0x00,0x20,0xdf,0xaf,0xa2,0x00,0x10,
13080x08,0x00,0x13,0x13,0xa2,0x02,0x00,0x12,0x92,0x22,0x00,0x08,0x08,0x00,0x13,0x13,
13090xa2,0x22,0x00,0x09,0xa2,0x20,0x00,0x11,0x80,0x82,0x00,0x50,0x00,0x00,0x00,0x00,
13100x10,0x40,0x00,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xac,0x40,0x00,0x00,
13110x08,0x00,0x13,0x13,0xa0,0x80,0x00,0x50,0x94,0x8a,0x00,0x0c,0x24,0x03,0x00,0x24,
13120x00,0x80,0x70,0x21,0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x24,0x42,0x4f,0x88,
13130xf1,0x43,0x00,0x06,0x34,0x84,0x00,0x20,0x00,0x00,0x18,0x12,0x00,0xa0,0x68,0x21,
13140xac,0x82,0x00,0x00,0x27,0x85,0x96,0x50,0x27,0x82,0x96,0x4f,0x27,0xbd,0xff,0xf8,
13150x00,0x62,0x60,0x21,0x00,0x65,0x58,0x21,0x00,0x00,0xc0,0x21,0x11,0xa0,0x00,0xcc,
13160x00,0x00,0x78,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,
13170x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x91,0x87,0x00,0x00,
13180x80,0x48,0x00,0x04,0x03,0xa0,0x60,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,
13190x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x48,0x80,0x27,0x83,0x96,0x44,
13200xa3,0xa7,0x00,0x00,0x01,0x23,0x18,0x21,0x8c,0x64,0x00,0x18,0x25,0x02,0xff,0xff,
13210x00,0x48,0x40,0x0b,0x8c,0x83,0x00,0x04,0x2d,0x05,0x00,0x07,0x24,0x02,0x00,0x06,
13220x30,0x63,0x00,0x08,0x14,0x60,0x00,0x35,0x00,0x45,0x40,0x0a,0x93,0xa7,0x00,0x00,
13230x27,0x82,0x96,0x58,0x01,0x22,0x10,0x21,0x30,0xe3,0x00,0xf0,0x38,0x63,0x00,0x50,
13240x30,0xe5,0x00,0xff,0x00,0x05,0x20,0x2b,0x00,0x03,0x18,0x2b,0x00,0x64,0x18,0x24,
13250x90,0x49,0x00,0x00,0x10,0x60,0x00,0x16,0x30,0xe4,0x00,0x0f,0x24,0x02,0x00,0x04,
13260x10,0xa2,0x00,0x9d,0x00,0x00,0x00,0x00,0x11,0xa0,0x00,0x3a,0x2c,0xa2,0x00,0x0c,
13270x10,0x40,0x00,0x02,0x24,0x84,0x00,0x0c,0x00,0xe0,0x20,0x21,0x30,0x84,0x00,0xff,
13280x00,0x04,0x10,0x40,0x27,0x83,0xc1,0x5c,0x00,0x44,0x10,0x21,0x00,0x43,0x10,0x21,
13290x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe3,0x00,0x0c,0xa3,0xa7,0x00,0x00,
13300x10,0x60,0x00,0x02,0x24,0xe2,0x00,0x04,0x00,0xe0,0x10,0x21,0xa3,0xa2,0x00,0x00,
13310x91,0x65,0x00,0x00,0x91,0x82,0x00,0x00,0x30,0xa3,0x00,0xff,0x00,0x62,0x10,0x2b,
13320x10,0x40,0x00,0x0e,0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0x60,0x20,0x21,
13330x30,0xa2,0x00,0x0f,0x24,0x44,0x00,0x0c,0x00,0x04,0x10,0x40,0x00,0x44,0x20,0x21,
13340x27,0x83,0xc1,0x5c,0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x02,0x00,0x00,0x00,0x00,
13350x10,0x40,0x00,0x05,0x00,0x09,0x11,0x00,0xa1,0x85,0x00,0x00,0x93,0xa2,0x00,0x00,
13360x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,
13370x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x27,0x83,0xba,0xe8,
13380x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x83,0x00,0x0c,
13390x14,0x60,0x00,0x06,0x00,0x80,0x10,0x21,0x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,
13400x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04,0x08,0x00,0x14,0x43,
13410xa1,0x82,0x00,0x00,0x8f,0x8d,0x87,0xf0,0x00,0x00,0x00,0x00,0x01,0xa8,0x10,0x21,
13420x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xd1,0x00,0x00,0x28,0x21,
13430x00,0x06,0x74,0x82,0x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x03,
13440x00,0xe0,0x10,0x21,0x30,0xe2,0x00,0x0f,0x24,0x42,0x00,0x0c,0x30,0x44,0x00,0xff,
13450xa3,0xa2,0x00,0x00,0x24,0x02,0x00,0x0c,0x10,0x82,0x00,0x0d,0x00,0x09,0x11,0x00,
13460x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x04,0x18,0x40,0x00,0x49,0x10,0x23,
13470x00,0x64,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x27,0x84,0xba,0xe8,
13480x00,0x44,0x10,0x21,0x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xa7,0x00,0x00,
13490x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
13500x00,0x02,0x10,0x80,0x27,0x83,0x96,0x44,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,
13510x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,
13520x14,0x60,0x00,0x33,0x00,0x06,0x14,0x42,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,
13530x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23,0x27,0x83,0xbb,0xb8,0x00,0x02,0x10,0x80,
13540x00,0x43,0x10,0x21,0x90,0x44,0x00,0x04,0x90,0x43,0x00,0x05,0x00,0x00,0x00,0x00,
13550x00,0x64,0xc0,0x24,0x93,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe2,0x00,0x0f,
13560x10,0x40,0x00,0x0f,0x31,0xcf,0x00,0x01,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,
13570x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x96,0x40,
13580x00,0x44,0x10,0x21,0x84,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0x28,0x63,0x06,0x41,
13590x14,0x60,0x00,0x04,0x30,0xe2,0x00,0xff,0x24,0x07,0x00,0x0f,0xa3,0xa7,0x00,0x00,
13600x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x06,0x00,0xe0,0x10,0x21,
13610x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x47,0x10,0x21,
13620x24,0x42,0x00,0x04,0xa3,0xa2,0x00,0x00,0x00,0x40,0x38,0x21,0x01,0xa8,0x10,0x21,
13630x90,0x43,0x00,0x00,0x24,0xa4,0x00,0x01,0x30,0x85,0xff,0xff,0x00,0xa3,0x18,0x2b,
13640x14,0x60,0xff,0xad,0x30,0xe2,0x00,0xff,0x08,0x00,0x14,0x30,0x00,0x00,0x00,0x00,
13650x08,0x00,0x14,0x91,0x30,0x58,0x00,0x01,0x81,0xc2,0x00,0x48,0x00,0x00,0x00,0x00,
13660x10,0x40,0xff,0x73,0x00,0x00,0x00,0x00,0x08,0x00,0x14,0x1e,0x00,0x00,0x00,0x00,
13670x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
13680x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x80,0x48,0x00,0x05,0x91,0x67,0x00,0x00,
13690x08,0x00,0x13,0xfe,0x03,0xa0,0x58,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
13700x34,0x63,0x00,0x20,0x24,0x42,0x53,0x28,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,
13710x27,0xbd,0xff,0xc0,0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,
13720xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xbf,0x00,0x3c,
13730xaf,0xbe,0x00,0x38,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x84,0x82,0x00,0x0c,
13740x27,0x93,0x96,0x44,0x3c,0x05,0xb0,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,
13750x00,0x03,0x18,0x80,0x00,0x73,0x10,0x21,0x8c,0x5e,0x00,0x18,0x3c,0x02,0x80,0x00,
13760x34,0xa5,0x00,0x20,0x24,0x42,0x53,0x40,0xac,0xa2,0x00,0x00,0x8f,0xd0,0x00,0x08,
13770x27,0x95,0x96,0x50,0x00,0x75,0x18,0x21,0x00,0x00,0x28,0x21,0x02,0x00,0x30,0x21,
13780x90,0x71,0x00,0x00,0x0c,0x00,0x13,0xe2,0x00,0x80,0xb0,0x21,0x00,0x40,0x90,0x21,
13790x00,0x10,0x14,0x42,0x30,0x54,0x00,0x01,0x02,0x40,0x20,0x21,0x00,0x10,0x14,0x82,
13800x02,0x80,0x28,0x21,0x12,0x51,0x00,0x23,0x00,0x10,0xbf,0xc2,0x86,0xc3,0x00,0x0c,
13810x30,0x50,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
13820x00,0x55,0x10,0x21,0xa0,0x52,0x00,0x00,0x86,0xc3,0x00,0x0c,0x00,0x00,0x00,0x00,
13830x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x53,0x30,0x21,
13840x8c,0xc7,0x00,0x18,0x27,0x83,0x96,0x40,0x00,0x43,0x10,0x21,0x8c,0xe3,0x00,0x04,
13850x84,0x46,0x00,0x06,0x00,0x03,0x19,0x42,0x0c,0x00,0x0d,0xd7,0x30,0x73,0x00,0x01,
13860x00,0x40,0x88,0x21,0x02,0x40,0x20,0x21,0x02,0x80,0x28,0x21,0x16,0xe0,0x00,0x10,
13870x02,0x00,0x30,0x21,0x86,0xc2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0xc0,
13880x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x27,0x82,0x96,0x48,0x00,0x62,0x18,0x21,
13890xa4,0x71,0x00,0x04,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,
13900x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,
13910x86,0xc3,0x00,0x0c,0xaf,0xb3,0x00,0x10,0xaf,0xa0,0x00,0x14,0x00,0x03,0x10,0xc0,
13920x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,0x80,0x47,0x00,0x06,
13930x00,0x00,0x00,0x00,0x24,0xe7,0x00,0x02,0x00,0x07,0x17,0xc2,0x00,0xe2,0x38,0x21,
13940x00,0x07,0x38,0x43,0x00,0x07,0x38,0x40,0x0c,0x00,0x0d,0xfe,0x03,0xc7,0x38,0x21,
13950x08,0x00,0x15,0x11,0x02,0x22,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
13960x27,0xbd,0xff,0xd0,0x34,0x63,0x00,0x20,0x24,0x42,0x54,0xc8,0xaf,0xb2,0x00,0x20,
13970xac,0x62,0x00,0x00,0xaf,0xbf,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,
13980xaf,0xb0,0x00,0x18,0x3c,0x02,0xb0,0x03,0x90,0x83,0x00,0x0a,0x34,0x42,0x01,0x04,
13990x94,0x45,0x00,0x00,0x00,0x03,0x18,0x80,0x27,0x82,0xba,0x40,0x00,0x62,0x18,0x21,
14000x30,0xa6,0xff,0xff,0x8c,0x71,0x00,0x00,0x80,0x85,0x00,0x12,0x30,0xc8,0x00,0xff,
14010x00,0x06,0x32,0x02,0xa4,0x86,0x00,0x44,0xa4,0x88,0x00,0x46,0x82,0x22,0x00,0x12,
14020x00,0x80,0x90,0x21,0x10,0xa0,0x00,0x1b,0xa0,0x80,0x00,0x15,0x00,0xc5,0x10,0x2a,
14030x10,0x40,0x00,0x14,0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x19,0x84,0x83,0x00,0x0c,
14040x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
14050x27,0x83,0x96,0x60,0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x80,0x00,0x12,
14060x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xdf,0xa2,0x22,0x00,0x16,
14070x8f,0xbf,0x00,0x28,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,
14080x27,0xbd,0x00,0x30,0x0c,0x00,0x14,0xca,0x00,0x00,0x00,0x00,0x08,0x00,0x15,0x60,
14090x00,0x00,0x00,0x00,0x28,0x42,0x00,0x02,0x10,0x40,0x01,0x65,0x00,0x00,0x28,0x21,
14100x84,0x83,0x00,0x0c,0x27,0x84,0x96,0x50,0x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0,
14110x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x96,0x48,0x00,0x43,0x18,0x21,
14120x80,0x65,0x00,0x06,0x00,0x44,0x10,0x21,0x80,0x49,0x00,0x05,0x38,0xa5,0x00,0x00,
14130x80,0x4a,0x00,0x04,0x15,0x20,0x00,0x27,0x01,0x05,0x30,0x0b,0x15,0x40,0x00,0x11,
14140x30,0xe3,0xff,0xff,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa8,0x00,0xff,
14150x2d,0x02,0x00,0x04,0x10,0x40,0x01,0x45,0x2d,0x02,0x00,0x10,0x3c,0x04,0xb0,0x05,
14160x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x01,0x02,0x10,0x04,
14170x00,0x62,0x18,0x25,0xa0,0x83,0x00,0x00,0x96,0x47,0x00,0x0c,0x00,0x00,0x00,0x00,
14180x30,0xe3,0xff,0xff,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x27,0x84,0x96,0x50,
14190x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,
14200x3c,0x04,0xb0,0x00,0x00,0x65,0x18,0x21,0x00,0x64,0x28,0x21,0x94,0xa2,0x00,0x00,
14210x82,0x43,0x00,0x10,0x00,0x02,0x14,0x00,0x14,0x60,0x00,0x06,0x00,0x02,0x24,0x03,
14220x30,0x82,0x00,0x04,0x14,0x40,0x00,0x04,0x01,0x49,0x10,0x21,0x34,0x82,0x08,0x00,
14230xa4,0xa2,0x00,0x00,0x01,0x49,0x10,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
14240x00,0x46,0x10,0x2a,0x10,0x40,0x00,0x7c,0x00,0x00,0x00,0x00,0x82,0x42,0x00,0x10,
14250x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x86,0x43,0x00,0x0c,
14260x25,0x44,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
14270x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x04,0x92,0x23,0x00,0x16,
14280x02,0x40,0x20,0x21,0x30,0x63,0x00,0xfb,0x08,0x00,0x15,0x65,0xa2,0x23,0x00,0x16,
14290x86,0x43,0x00,0x0c,0x25,0x24,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
14300x00,0x02,0x10,0x80,0x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x05,
14310x86,0x45,0x00,0x0c,0x0c,0x00,0x23,0x1c,0x02,0x20,0x20,0x21,0x10,0x40,0x00,0x5a,
14320x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,
14330x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x4c,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,
14340x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,
14350x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08,
14360x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x33,0x24,0x02,0x00,0x01,
14370xa2,0x40,0x00,0x04,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0c,
14380x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,
14390x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x96,0x22,0x00,0x06,0x08,0x00,0x15,0x60,
14400xa6,0x22,0x00,0x14,0x96,0x22,0x00,0x00,0x08,0x00,0x15,0x60,0xa6,0x22,0x00,0x14,
14410x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
14420x08,0x00,0x15,0xde,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,
14430x27,0x86,0x96,0x40,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,
14440x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,
14450x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,
14460x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,
14470x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,
14480x08,0x00,0x15,0xde,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,
14490x08,0x00,0x16,0x01,0x00,0x00,0x00,0x00,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,
14500x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xca,0x00,0x00,0x00,0x00,
14510x08,0x00,0x15,0xd9,0xa2,0x40,0x00,0x07,0x08,0x00,0x15,0xd9,0xa2,0x40,0x00,0x06,
14520x08,0x00,0x15,0xd9,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0xbe,0x3c,0x04,0xb0,0x05,
14530x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,
14540x08,0x00,0x15,0xd0,0x00,0xa2,0x10,0x07,0x0c,0x00,0x14,0xd0,0x02,0x40,0x20,0x21,
14550x08,0x00,0x15,0x60,0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,
14560x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x98,0x2c,0xc2,0x00,0x10,
14570x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,
14580x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,
14590x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x7f,
14600x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x86,0x43,0x00,0x0c,0x27,0x93,0x96,0x44,
14610x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,
14620x00,0xb3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,
14630x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x64,0x00,0x00,0x00,0x00,
14640x00,0x07,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
14650x00,0x02,0x10,0x80,0x00,0x53,0x10,0x21,0x8c,0x43,0x00,0x18,0x93,0x82,0x91,0x51,
14660x8c,0x64,0x00,0x04,0x30,0x42,0x00,0x01,0x00,0x04,0x21,0x42,0x14,0x40,0x00,0x4d,
14670x30,0x90,0x00,0x01,0x00,0x07,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1f,0xdd,
14680x02,0x20,0x20,0x21,0x96,0x26,0x00,0x06,0x12,0x00,0x00,0x14,0x30,0xc5,0xff,0xff,
14690x02,0x60,0x90,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x02,0x10,0x80,
14700x00,0x52,0x18,0x21,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,
14710x02,0x20,0x20,0x21,0x8c,0x63,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x62,0x00,0x04,
14720x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x0c,0x00,0x1f,0xdd,0x30,0x50,0x00,0x01,
14730x96,0x26,0x00,0x06,0x16,0x00,0xff,0xef,0x30,0xc5,0xff,0xff,0x92,0x22,0x00,0x04,
14740x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0d,0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,
14750x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,
14760xa6,0x26,0x00,0x14,0x92,0x22,0x00,0x16,0x08,0x00,0x15,0x5f,0x30,0x42,0x00,0xc3,
14770x96,0x22,0x00,0x00,0x08,0x00,0x16,0x75,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a,
14780x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0x70,
14790xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x30,0xc5,0xff,0xff,0x00,0x05,0x18,0xc0,
14800x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x27,0x84,0x96,0x40,
14810x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x00,0x03,0x18,0x80,0x8c,0x45,0x00,0x08,
14820x00,0x64,0x18,0x21,0x8c,0x64,0x00,0x08,0x3c,0x02,0x80,0x00,0x00,0xa2,0x38,0x24,
14830x10,0xe0,0x00,0x08,0x00,0x82,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,
14840x10,0xe0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x16,0x70,
14850xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x16,0x94,
14860x00,0x00,0x00,0x00,0x24,0x05,0x00,0x24,0xf0,0xe5,0x00,0x06,0x00,0x00,0x28,0x12,
14870x27,0x82,0x96,0x40,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,0x00,0x00,0x20,0x21,
14880x96,0x47,0x00,0x0c,0x08,0x00,0x16,0x52,0x00,0x07,0x2c,0x00,0x27,0x83,0x96,0x50,
14890x27,0x82,0x96,0x58,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,
14900x90,0x65,0x00,0x05,0x24,0x07,0x00,0x01,0x0c,0x00,0x25,0xc4,0x00,0x00,0x30,0x21,
14910x96,0x47,0x00,0x0c,0x08,0x00,0x16,0x45,0x00,0x07,0x1c,0x00,0x10,0xa2,0x00,0x09,
14920x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x7e,
14930x00,0x00,0x00,0x00,0x08,0x00,0x16,0x36,0xa2,0x40,0x00,0x07,0x08,0x00,0x16,0x36,
14940xa2,0x40,0x00,0x06,0x08,0x00,0x16,0x36,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0x72,
14950x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,
14960x24,0x02,0x00,0x80,0x08,0x00,0x16,0x2d,0x00,0xa2,0x10,0x07,0x14,0x40,0xfe,0xc4,
14970x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
14980x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x15,0x88,0x00,0xa2,0x10,0x07,
14990x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
15000x00,0x02,0x10,0x80,0x27,0x83,0x96,0x44,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,
15010x00,0x00,0x00,0x00,0x8c,0xe6,0x00,0x08,0x0c,0x00,0x13,0xe2,0x00,0x00,0x00,0x00,
15020x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x00,0x00,0x30,0x21,0x00,0x00,0x38,0x21,
15030x0c,0x00,0x20,0xdf,0xaf,0xa2,0x00,0x10,0x00,0x02,0x1e,0x00,0x14,0x60,0xfe,0x7c,
15040xa2,0x22,0x00,0x12,0x92,0x43,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x40,
15050x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x92,0x28,0x00,0x04,0x00,0x00,0x00,0x00,
15060x15,0x00,0x00,0x19,0x24,0x02,0x00,0x01,0x92,0x27,0x00,0x0a,0xa2,0x22,0x00,0x17,
15070x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x10,0x00,0x00,0x00,0x00,
15080x96,0x22,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x16,
15090x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xc0,0x10,0x60,0x00,0x03,0xa2,0x22,0x00,0x16,
15100x34,0x42,0x00,0x01,0xa2,0x22,0x00,0x16,0x11,0x00,0xfe,0x61,0x00,0x00,0x00,0x00,
15110x92,0x22,0x00,0x16,0x08,0x00,0x15,0x5f,0x34,0x42,0x00,0x02,0x96,0x22,0x00,0x00,
15120x08,0x00,0x16,0xf7,0xa6,0x22,0x00,0x14,0x92,0x27,0x00,0x0a,0x00,0x00,0x00,0x00,
15130x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0xf0,0xa2,0x20,0x00,0x17,
15140x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,0x27,0x86,0x96,0x40,0x00,0x04,0x18,0xc0,
15150x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,
15160x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,
15170x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,
15180x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,
15190x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x16,0xf0,0xa2,0x23,0x00,0x17,
15200x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x17,0x1f,0x00,0x00,0x00,0x00,
15210x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,
15220x14,0x62,0xff,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0xea,0xa2,0x40,0x00,0x07,
15230x08,0x00,0x16,0xea,0xa2,0x40,0x00,0x06,0x08,0x00,0x16,0xea,0xa2,0x40,0x00,0x05,
15240x3c,0x02,0x80,0x00,0x00,0x82,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0xa2,0x18,0x24,
15250x10,0x60,0x00,0x04,0x00,0x00,0x10,0x21,0x10,0xc0,0x00,0x02,0x24,0x02,0x00,0x01,
15260x00,0xa4,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xfd,
15270x00,0xa4,0x10,0x2b,0x08,0x00,0x17,0x3a,0x00,0x00,0x00,0x00,0x30,0x82,0xff,0xff,
15280x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x27,0x84,0x96,0x50,0x00,0x03,0x18,0x80,
15290x00,0x64,0x18,0x21,0x80,0x66,0x00,0x06,0x00,0x02,0x12,0x00,0x3c,0x03,0xb0,0x00,
15300x00,0x46,0x10,0x21,0x00,0x45,0x10,0x21,0x03,0xe0,0x00,0x08,0x00,0x43,0x10,0x21,
15310x27,0xbd,0xff,0xe0,0x30,0x82,0x00,0x7c,0x30,0x84,0xff,0x00,0xaf,0xbf,0x00,0x1c,
15320xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x14,0x40,0x00,0x41,
15330x00,0x04,0x22,0x03,0x24,0x02,0x00,0x04,0x3c,0x10,0xb0,0x03,0x8e,0x10,0x00,0x00,
15340x10,0x82,0x00,0x32,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x03,0x32,0x02,0x00,0x20,
15350x08,0x00,0x17,0x60,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x06,
15360x34,0x42,0x80,0x24,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x67,0x00,0xff,
15370x10,0xe0,0x00,0x23,0x00,0x00,0x88,0x21,0x8f,0x85,0x96,0x20,0x00,0x40,0x30,0x21,
15380x94,0xa2,0x00,0x08,0x8c,0xc3,0x00,0x00,0x26,0x31,0x00,0x01,0x24,0x42,0x00,0x02,
15390x30,0x42,0x01,0xff,0x34,0x63,0x01,0x00,0x02,0x27,0x20,0x2a,0xa4,0xa2,0x00,0x08,
15400x14,0x80,0xff,0xf7,0xac,0xc3,0x00,0x00,0x84,0xa3,0x00,0x08,0x3c,0x02,0xb0,0x03,
15410x34,0x42,0x00,0x30,0xac,0x43,0x00,0x00,0x27,0x92,0xba,0x40,0x24,0x11,0x00,0x12,
15420x8e,0x44,0x00,0x00,0x26,0x31,0xff,0xff,0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,
15430x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04,0x0c,0x00,0x1d,0x55,0x00,0x00,0x00,0x00,
15440x06,0x21,0xff,0xf7,0x24,0x02,0xff,0xdf,0x02,0x02,0x80,0x24,0x3c,0x01,0xb0,0x03,
15450x0c,0x00,0x18,0x18,0xac,0x30,0x00,0x00,0x08,0x00,0x17,0x60,0x00,0x00,0x00,0x00,
15460x8f,0x85,0x96,0x20,0x08,0x00,0x17,0x76,0x00,0x00,0x00,0x00,0x24,0x02,0xff,0x95,
15470x3c,0x03,0xb0,0x03,0x02,0x02,0x80,0x24,0x34,0x63,0x00,0x30,0x3c,0x01,0xb0,0x03,
15480xac,0x30,0x00,0x00,0x0c,0x00,0x17,0xe1,0xac,0x60,0x00,0x00,0x08,0x00,0x17,0x60,
15490x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x50,0x08,0x00,0x17,0x60,
15500xac,0x46,0x00,0x00,0xaf,0xa7,0x00,0x0c,0xaf,0xa4,0x00,0x00,0xaf,0xa5,0x00,0x04,
15510xaf,0xa6,0x00,0x08,0x27,0xbd,0xfe,0xe8,0x00,0x80,0x28,0x21,0x27,0xa6,0x01,0x1c,
15520x27,0xa4,0x00,0x10,0xaf,0xbf,0x01,0x14,0x0c,0x00,0x29,0xa9,0xaf,0xb0,0x01,0x10,
15530x00,0x40,0x80,0x21,0x0c,0x00,0x17,0xb0,0x27,0xa4,0x00,0x10,0x02,0x00,0x10,0x21,
15540x8f,0xbf,0x01,0x14,0x8f,0xb0,0x01,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x01,0x18,
15550x93,0x83,0x87,0xec,0x27,0xbd,0xff,0xe8,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
15560x14,0x60,0x00,0x14,0x00,0x80,0x80,0x21,0x80,0x82,0x00,0x00,0x90,0x84,0x00,0x00,
15570x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
15580x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x00,0x04,0x26,0x00,0x00,0x04,0x26,0x03,
15590x30,0x84,0xff,0xff,0x0c,0x00,0x17,0xd0,0x26,0x10,0x00,0x01,0x92,0x03,0x00,0x00,
15600x00,0x00,0x00,0x00,0x14,0x60,0xff,0xf8,0x00,0x60,0x20,0x21,0x08,0x00,0x17,0xba,
15610x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x14,0x43,0xff,0xef,0x00,0x00,0x00,0x00,
15620x0c,0x00,0x04,0x52,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0xba,0x00,0x00,0x00,0x00,
15630x30,0x84,0xff,0xff,0x48,0x84,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
15640x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x0c,0x00,0x29,0x11,0x00,0x00,0x00,0x00,
15650x8f,0xbf,0x00,0x10,0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03,0x03,0xe0,0x00,0x08,
15660x27,0xbd,0x00,0x18,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,
15670x24,0x02,0x00,0x01,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x5f,0x84,0x3c,0x0b,0xb0,0x03,
15680xad,0x6a,0x00,0x20,0x3c,0x08,0x80,0x01,0x25,0x08,0x00,0x00,0x3c,0x09,0x80,0x01,
15690x25,0x29,0x0b,0x2c,0x11,0x09,0x00,0x10,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,
15700x25,0x4a,0x5f,0xac,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x08,0xb0,0x06,
15710x35,0x08,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,
15720x00,0x00,0x00,0x00,0x31,0x29,0x00,0x01,0x00,0x00,0x00,0x00,0x24,0x01,0x00,0x01,
15730x15,0x21,0xff,0xf2,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x5f,0xe8,
15740x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0xb0,0x03,0x8c,0x43,0x00,0x00,
15750x00,0x00,0x00,0x00,0x34,0x63,0x00,0x40,0x00,0x00,0x00,0x00,0xac,0x43,0x00,0x00,
15760x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x60,0x14,0x3c,0x0b,0xb0,0x03,
15770xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01,0x24,0x42,0x00,0x00,0x3c,0x03,0x80,0x01,
15780x24,0x63,0x0b,0x2c,0x3c,0x04,0xb0,0x00,0x8c,0x85,0x00,0x00,0x00,0x00,0x00,0x00,
15790xac,0x45,0x00,0x00,0x24,0x42,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x43,0x08,0x2a,
15800x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x18,0x00,0x00,0x00,0x00,
15810x3c,0x0a,0x80,0x00,0x25,0x4a,0x60,0x60,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
15820x3c,0x02,0x80,0x01,0x24,0x42,0x0b,0x30,0x3c,0x03,0x80,0x01,0x24,0x63,0x42,0x50,
15830xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0xac,0x40,0x00,0x08,0xac,0x40,0x00,0x0c,
15840x24,0x42,0x00,0x10,0x00,0x43,0x08,0x2a,0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,
15850x3c,0x0a,0x80,0x00,0x25,0x4a,0x60,0xa0,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
15860x3c,0x1c,0x80,0x01,0x27,0x9c,0x7f,0xf0,0x27,0x9d,0x92,0x20,0x00,0x00,0x00,0x00,
15870x27,0x9d,0x96,0x08,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x60,0xc4,0x3c,0x0b,0xb0,0x03,
15880xad,0x6a,0x00,0x20,0x40,0x80,0x68,0x00,0x40,0x08,0x60,0x00,0x00,0x00,0x00,0x00,
15890x35,0x08,0xff,0x01,0x40,0x88,0x60,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x1a,0x4d,
15900x00,0x00,0x00,0x00,0x24,0x84,0xf8,0x00,0x30,0x87,0x00,0x03,0x00,0x04,0x30,0x40,
15910x00,0xc7,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x27,0xbd,0xff,0xe0,0x24,0x03,0xff,0xff,
15920x00,0x82,0x20,0x21,0xaf,0xb1,0x00,0x14,0xac,0x83,0x10,0x00,0xaf,0xbf,0x00,0x18,
15930xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x10,0x00,
15940x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0xc7,0x10,0x23,0x3c,0x03,0xb0,0x0a,
15950x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x0c,0x00,0x18,0x95,0x02,0x20,0x20,0x21,
15960x02,0x11,0x80,0x24,0x00,0x50,0x80,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,
15970x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,
15980xaf,0xb2,0x00,0x18,0x00,0xa0,0x90,0x21,0x24,0x05,0xff,0xff,0xaf,0xb3,0x00,0x1c,
15990xaf,0xbf,0x00,0x20,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x00,0xc0,0x98,0x21,
16000x12,0x45,0x00,0x23,0x24,0x84,0xf8,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x10,0x40,
16010x00,0x40,0x88,0x21,0x00,0x60,0x20,0x21,0x00,0x43,0x10,0x23,0x3c,0x03,0xb0,0x0a,
16020x00,0x43,0x10,0x21,0xac,0x45,0x10,0x00,0x00,0x40,0x18,0x21,0x24,0x05,0x00,0x01,
16030x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x45,0xff,0xfd,0x3c,0x02,0xb0,0x0a,
16040x02,0x24,0x88,0x23,0x02,0x22,0x88,0x21,0x8e,0x30,0x00,0x00,0x0c,0x00,0x18,0x95,
16050x02,0x40,0x20,0x21,0x00,0x12,0x18,0x27,0x02,0x03,0x80,0x24,0x00,0x53,0x10,0x04,
16060x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x24,0x03,0x00,0x01,0x8e,0x22,0x10,0x00,
16070x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20,
16080x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
16090x30,0x82,0x00,0x03,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x23,0x3c,0x04,0xb0,0x0a,
16100x00,0x64,0x18,0x21,0xac,0x66,0x00,0x00,0x24,0x04,0x00,0x01,0x8c,0x62,0x10,0x00,
16110x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x18,0x83,
16120x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x64,0x10,0x06,0x30,0x42,0x00,0x01,
16130x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x20,
16140x14,0x40,0xff,0xf9,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,
16150x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x05,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
16160xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0x00,0x80,0x80,0x21,0x00,0xa0,0x88,0x21,
16170x00,0xc0,0x90,0x21,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
16180x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfc,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0,
16190x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,
16200x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x03,0x82,0x02,0x00,0x13,0x00,0x11,0x24,0x00,
16210x3c,0x03,0xc0,0x00,0x00,0x02,0x12,0x00,0x00,0x44,0x10,0x21,0x3c,0x04,0xb0,0x05,
16220x24,0x42,0x00,0x09,0x34,0x84,0x04,0x20,0x34,0x63,0x04,0x00,0x3c,0x05,0xb0,0x05,
16230x3c,0x06,0xb0,0x05,0xac,0x82,0x00,0x00,0x24,0x07,0x00,0x01,0x02,0x43,0x18,0x21,
16240x34,0xa5,0x04,0x24,0x34,0xc6,0x02,0x28,0x24,0x02,0x00,0x20,0xac,0xa3,0x00,0x00,
16250xae,0x07,0x00,0x3c,0xa0,0xc2,0x00,0x00,0xa2,0x07,0x00,0x11,0x3c,0x02,0xb0,0x05,
16260x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0,
16270x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x01,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,
16280x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x01,0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,
16290x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x02,0x00,0x06,
16300xac,0x82,0x00,0x0c,0xa0,0x80,0x00,0x50,0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,
16310xac,0x80,0x00,0x08,0xac,0x80,0x00,0x14,0xac,0x80,0x00,0x18,0xac,0x80,0x00,0x1c,
16320xa4,0x80,0x00,0x20,0xac,0x80,0x00,0x24,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,
16330xa0,0x80,0x00,0x30,0xa0,0x80,0x00,0x31,0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,
16340xa0,0x80,0x00,0x3c,0xac,0x82,0x00,0x10,0xa0,0x80,0x00,0x44,0xac,0x80,0x00,0x48,
16350x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x4c,0x3c,0x04,0xb0,0x06,0x34,0x84,0x80,0x00,
16360x8c,0x83,0x00,0x00,0x3c,0x02,0x12,0x00,0x3c,0x05,0xb0,0x03,0x00,0x62,0x18,0x25,
16370x34,0xa5,0x00,0x8b,0x24,0x02,0xff,0x80,0xac,0x83,0x00,0x00,0x03,0xe0,0x00,0x08,
16380xa0,0xa2,0x00,0x00,0x3c,0x04,0xb0,0x03,0x34,0x84,0x00,0x0b,0x24,0x02,0x00,0x22,
16390x3c,0x05,0xb0,0x01,0x3c,0x06,0x45,0x67,0x3c,0x0a,0xb0,0x09,0xa0,0x82,0x00,0x00,
16400x34,0xa5,0x00,0x04,0x34,0xc6,0x89,0xaa,0x35,0x4a,0x00,0x04,0x24,0x02,0x01,0x23,
16410x3c,0x0b,0xb0,0x09,0x3c,0x07,0x01,0x23,0x3c,0x0c,0xb0,0x09,0x3c,0x01,0xb0,0x01,
16420xac,0x20,0x00,0x00,0x27,0xbd,0xff,0xe0,0xac,0xa0,0x00,0x00,0x35,0x6b,0x00,0x08,
16430x3c,0x01,0xb0,0x09,0xac,0x26,0x00,0x00,0x34,0xe7,0x45,0x66,0xa5,0x42,0x00,0x00,
16440x35,0x8c,0x00,0x0c,0x24,0x02,0xcd,0xef,0x3c,0x0d,0xb0,0x09,0x3c,0x08,0xcd,0xef,
16450x3c,0x0e,0xb0,0x09,0xad,0x67,0x00,0x00,0xaf,0xb7,0x00,0x1c,0xa5,0x82,0x00,0x00,
16460xaf,0xb6,0x00,0x18,0xaf,0xb5,0x00,0x14,0xaf,0xb4,0x00,0x10,0xaf,0xb3,0x00,0x0c,
16470xaf,0xb2,0x00,0x08,0xaf,0xb1,0x00,0x04,0xaf,0xb0,0x00,0x00,0x35,0xad,0x00,0x10,
16480x35,0x08,0x01,0x22,0x35,0xce,0x00,0x14,0x24,0x02,0x89,0xab,0x3c,0x0f,0xb0,0x09,
16490x3c,0x09,0x89,0xab,0x3c,0x10,0xb0,0x09,0x3c,0x11,0xb0,0x09,0x3c,0x12,0xb0,0x09,
16500x3c,0x13,0xb0,0x09,0x3c,0x14,0xb0,0x09,0x3c,0x15,0xb0,0x09,0x3c,0x16,0xb0,0x09,
16510x3c,0x17,0xb0,0x09,0xad,0xa8,0x00,0x00,0x24,0x03,0xff,0xff,0xa5,0xc2,0x00,0x00,
16520x35,0xef,0x00,0x18,0x35,0x29,0xcd,0xee,0x36,0x10,0x00,0x1c,0x36,0x31,0x00,0x20,
16530x36,0x52,0x00,0x24,0x36,0x73,0x00,0x28,0x36,0x94,0x00,0x2c,0x36,0xb5,0x00,0x30,
16540x36,0xd6,0x00,0x34,0x36,0xf7,0x00,0x38,0x24,0x02,0x45,0x67,0xad,0xe9,0x00,0x00,
16550xa6,0x02,0x00,0x00,0xae,0x23,0x00,0x00,0x8f,0xb0,0x00,0x00,0xa6,0x43,0x00,0x00,
16560x8f,0xb1,0x00,0x04,0xae,0x63,0x00,0x00,0x8f,0xb2,0x00,0x08,0xa6,0x83,0x00,0x00,
16570x8f,0xb3,0x00,0x0c,0xae,0xa3,0x00,0x00,0x8f,0xb4,0x00,0x10,0xa6,0xc3,0x00,0x00,
16580x8f,0xb5,0x00,0x14,0xae,0xe3,0x00,0x00,0x7b,0xb6,0x00,0xfc,0x3c,0x18,0xb0,0x09,
16590x37,0x18,0x00,0x3c,0xa7,0x03,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
16600x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x65,0x50,
16610xac,0x62,0x00,0x00,0x8c,0x83,0x00,0x34,0x34,0x02,0xff,0xff,0x00,0x43,0x10,0x2a,
16620x14,0x40,0x00,0xed,0x00,0x80,0x28,0x21,0x8c,0x84,0x00,0x08,0x24,0x02,0x00,0x03,
16630x10,0x82,0x00,0xe0,0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x2c,0x00,0x00,0x00,0x00,
16640x14,0x40,0x00,0x38,0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,
16650x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x14,0x40,0x00,0xc6,
16660xac,0xa2,0x00,0x2c,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0xc5,0x00,0x00,0x00,0x00,
16670x24,0x02,0x00,0x02,0x10,0x82,0x00,0xb3,0x00,0x00,0x00,0x00,0x8c,0xa6,0x00,0x04,
16680x24,0x02,0x00,0x02,0x10,0xc2,0x00,0xa9,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
16690x34,0x42,0x00,0xd0,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x61,0x00,0x16,
16700x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
16710x30,0x42,0x00,0x01,0x14,0x40,0x00,0x10,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42,
16720x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0b,0x00,0x00,0x00,0x00,
16730x80,0xa2,0x00,0x50,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,
16740x14,0x80,0x00,0x05,0x24,0x02,0x00,0x0e,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,
16750x03,0xe0,0x00,0x08,0xa0,0xa3,0x00,0x50,0x80,0xa2,0x00,0x31,0x00,0x00,0x00,0x00,
16760x10,0x40,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,0x8c,0x43,0x00,0x00,
16770x3c,0x04,0xf0,0x00,0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24,0x10,0x62,0x00,0x03,
16780x24,0x02,0x00,0x09,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x00,0x8c,0xa2,0x00,0x40,
16790x00,0x00,0x00,0x00,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x09,
16800x3c,0x03,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00,
16810x3c,0x04,0x00,0x02,0x00,0x64,0x18,0x24,0x14,0x60,0xff,0xf2,0x24,0x02,0x00,0x10,
16820x3c,0x03,0xb0,0x03,0x34,0x63,0x02,0x01,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
16830x30,0x42,0x00,0x80,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x8c,0xa3,0x00,0x0c,
16840x00,0x00,0x00,0x00,0xac,0xa3,0x00,0x10,0x3c,0x02,0xb0,0x03,0x90,0x42,0x02,0x01,
16850x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0xac,0xa2,0x00,0x0c,0x90,0xa3,0x00,0x0f,
16860x24,0x02,0x00,0x0d,0x3c,0x01,0xb0,0x03,0x08,0x00,0x19,0x9d,0xa0,0x23,0x02,0x01,
16870x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x80,0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
16880x00,0x04,0x1e,0x00,0x00,0x03,0x1e,0x03,0x10,0x60,0x00,0x15,0xa0,0xa4,0x00,0x44,
16890x24,0x02,0x00,0x01,0x10,0x62,0x00,0x0b,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x03,
16900x24,0x03,0x00,0x0d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x0c,
16910xac,0xa3,0x00,0x00,0x24,0x03,0x00,0x04,0xac,0xa2,0x00,0x10,0x03,0xe0,0x00,0x08,
16920xac,0xa3,0x00,0x0c,0x24,0x02,0x00,0x0d,0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x04,
16930x24,0x02,0x00,0x06,0xac,0xa3,0x00,0x10,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x0c,
16940x8c,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x09,0x24,0x02,0x00,0x01,
16950x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
16960x30,0x42,0x00,0xff,0x10,0x40,0x00,0x05,0xac,0xa2,0x00,0x14,0x24,0x02,0x00,0x01,
16970xac,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x14,0x8c,0xa3,0x00,0x38,
16980x24,0x04,0x00,0x01,0x10,0x64,0x00,0x2d,0x24,0x02,0x00,0x02,0x10,0x60,0x00,0x19,
16990x00,0x00,0x00,0x00,0x10,0x62,0x00,0x10,0x24,0x02,0x00,0x04,0x10,0x62,0x00,0x04,
17000x00,0x00,0x00,0x00,0xac,0xa0,0x00,0x38,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x00,
17010x10,0xc4,0x00,0x07,0x24,0x02,0x00,0x03,0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00,
17020x00,0x02,0x18,0x0b,0xac,0xa3,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x38,
17030x08,0x00,0x19,0xfe,0xac,0xa2,0x00,0x00,0x10,0xc4,0x00,0x02,0x24,0x02,0x00,0x03,
17040x24,0x02,0x00,0x0c,0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08,
17050xac,0xa2,0x00,0x38,0x10,0xc4,0x00,0x0e,0x3c,0x03,0xb0,0x06,0x34,0x63,0x80,0x24,
17060x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x06,
17070xac,0xa2,0x00,0x18,0x24,0x02,0x00,0x02,0xac,0xa2,0x00,0x00,0xac,0xa0,0x00,0x18,
17080x08,0x00,0x1a,0x07,0x24,0x02,0x00,0x01,0x08,0x00,0x1a,0x14,0xac,0xa0,0x00,0x00,
17090x24,0x02,0x00,0x03,0x08,0x00,0x1a,0x14,0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x0b,
17100xac,0xa2,0x00,0x38,0x03,0xe0,0x00,0x08,0xac,0xa3,0x00,0x00,0x80,0xa2,0x00,0x30,
17110x00,0x00,0x00,0x00,0x14,0x40,0xff,0x55,0x24,0x02,0x00,0x04,0x08,0x00,0x19,0x9d,
17120x00,0x00,0x00,0x00,0x84,0xa2,0x00,0x20,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x75,
17130x24,0x02,0x00,0x06,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,
17140x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,
17150x14,0x40,0xff,0x42,0xa4,0xa3,0x00,0x20,0x08,0x00,0x19,0x9d,0x24,0x02,0x00,0x06,
17160x8c,0xa2,0x00,0x1c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x66,0x24,0x02,0x00,0x05,
17170x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
17180x30,0x42,0x00,0xff,0x10,0x40,0xff,0x32,0xac,0xa2,0x00,0x1c,0x08,0x00,0x19,0x9d,
17190x24,0x02,0x00,0x05,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
17200x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x56,0x24,0x02,0x00,0x06,
17210x08,0x00,0x19,0x62,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0a,0x03,0xe0,0x00,0x08,
17220xac,0x82,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
17230x27,0x91,0x90,0xf8,0x27,0x90,0x8e,0x38,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,
17240x0c,0x00,0x28,0x9e,0xaf,0xb2,0x00,0x18,0x0c,0x00,0x06,0x90,0x00,0x00,0x00,0x00,
17250xaf,0x91,0x92,0x10,0xaf,0x90,0x96,0x20,0x48,0x02,0x00,0x00,0x0c,0x00,0x18,0xf2,
17260x00,0x00,0x00,0x00,0x0c,0x00,0x1c,0x9b,0x02,0x00,0x20,0x21,0x3c,0x02,0xb0,0x03,
17270x34,0x42,0x00,0x3a,0x94,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0x83,0x96,0x24,
17280x0c,0x00,0x00,0x34,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0xfd,0x00,0x00,0x00,0x00,
17290x27,0x84,0x8c,0x78,0x0c,0x00,0x2c,0x78,0x00,0x00,0x00,0x00,0x0c,0x00,0x25,0x71,
17300x00,0x00,0x00,0x00,0x0c,0x00,0x0c,0x0d,0x02,0x20,0x20,0x21,0x0c,0x00,0x01,0x39,
17310x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x20,0x0c,0x00,0x18,0xdb,0x00,0x00,0x00,0x00,
17320x27,0x82,0x91,0x2c,0xaf,0x82,0x8c,0x60,0x0c,0x00,0x00,0x5f,0x00,0x00,0x00,0x00,
17330x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x08,0x3c,0x04,0xb0,0x09,0x3c,0x05,0xb0,0x09,
17340x8c,0x66,0x00,0x00,0x34,0x84,0x01,0x68,0x24,0x02,0xd1,0x10,0x34,0xa5,0x01,0x40,
17350x24,0x03,0x00,0x0a,0xa4,0x82,0x00,0x00,0xa4,0xa3,0x00,0x00,0x3c,0x04,0xb0,0x03,
17360x8c,0x82,0x00,0x00,0xaf,0x86,0x8c,0x18,0x34,0x42,0x00,0x20,0xac,0x82,0x00,0x00,
17370x0c,0x00,0x06,0xa1,0x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x05,0x0c,0x00,0x28,0xb6,
17380x34,0x84,0x00,0x04,0x8f,0x83,0x8c,0x20,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x11,
17390x10,0x40,0xff,0xf7,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x09,0x08,
17400x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,
17410x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x20,0x0c,0x00,0x19,0x54,0x00,0x00,0x00,0x00,
17420x8f,0x82,0x8c,0x54,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x8c,0x54,
17430x08,0x00,0x1a,0x88,0x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x78,0x0c,0x00,0x2d,0xe5,
17440x00,0x00,0x00,0x00,0xa3,0x82,0x8c,0x51,0xaf,0x80,0x8c,0x20,0x08,0x00,0x1a,0x9c,
17450x00,0x00,0x00,0x00,0x27,0x84,0x8e,0x38,0x0c,0x00,0x1d,0xe0,0x00,0x00,0x00,0x00,
17460x30,0x42,0x00,0xff,0x14,0x40,0x00,0x05,0x3c,0x03,0xb0,0x05,0xaf,0x80,0x8c,0x20,
17470xaf,0x80,0x8c,0x24,0x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0x34,0x63,0x04,0x50,
17480x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x8c,0x4c,
17490x14,0x40,0x00,0x1e,0x24,0x02,0x00,0x01,0x8f,0x84,0x8c,0x28,0x00,0x00,0x00,0x00,
17500x10,0x82,0x00,0x1d,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,
17510x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x8c,0x34,0x14,0x40,0x00,0x13,
17520x24,0x02,0x00,0x01,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x07,0x3c,0x02,0xb0,0x05,
17530x24,0x02,0x00,0x01,0x24,0x03,0x00,0x03,0xaf,0x82,0x8c,0x24,0xaf,0x83,0x8c,0x20,
17540x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,
17550x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,
17560xa7,0x83,0x8c,0x40,0x14,0x40,0xff,0xf3,0x24,0x02,0x00,0x01,0xaf,0x82,0x8c,0x24,
17570x08,0x00,0x1a,0xa6,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,
17580x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x8c,0x3c,
17590x14,0x40,0xff,0xf6,0x24,0x02,0x00,0x01,0x08,0x00,0x1a,0xbe,0x3c,0x03,0xb0,0x09,
17600x27,0x84,0x8e,0x38,0x0c,0x00,0x1f,0x44,0x00,0x00,0x00,0x00,0x83,0x82,0x8c,0x50,
17610x00,0x00,0x00,0x00,0x14,0x40,0xff,0xed,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,
17620x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,
17630xaf,0x82,0x8c,0x4c,0x14,0x40,0xff,0xe5,0x24,0x02,0x00,0x02,0x8f,0x84,0x8c,0x28,
17640x24,0x02,0x00,0x01,0x10,0x82,0x00,0x12,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x05,
17650x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x02,0xaf,0x82,0x8c,0x24,0x08,0x00,0x1a,0xcb,
17660x24,0x03,0x00,0x04,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
17670x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x8c,0x40,
17680x14,0x40,0xff,0xf4,0x00,0x00,0x00,0x00,0x08,0x00,0x1a,0xd7,0x24,0x02,0x00,0x02,
17690x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
17700x30,0x42,0x00,0xff,0xaf,0x82,0x8c,0x3c,0x14,0x40,0xff,0xf7,0x00,0x00,0x00,0x00,
17710x08,0x00,0x1a,0xf7,0x24,0x02,0x00,0x02,0x27,0x84,0x90,0xf8,0x0c,0x00,0x10,0x1b,
17720x00,0x00,0x00,0x00,0x8f,0x83,0x8c,0x24,0xaf,0x82,0x8c,0x3c,0x38,0x64,0x00,0x02,
17730x00,0x04,0x18,0x0a,0xaf,0x83,0x8c,0x24,0x14,0x40,0x00,0x08,0x24,0x02,0x00,0x05,
17740x8f,0x82,0x91,0x38,0xaf,0x80,0x8c,0x20,0x10,0x40,0xff,0x7d,0x24,0x04,0x00,0x01,
17750xaf,0x84,0x8c,0x28,0x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0xaf,0x82,0x8c,0x20,
17760x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0x83,0x82,0x8c,0x70,0x00,0x00,0x00,0x00,
17770x10,0x40,0x00,0x02,0x24,0x02,0x00,0x20,0xaf,0x82,0x8c,0x3c,0x8f,0x85,0x8c,0x3c,
17780x27,0x84,0x90,0xf8,0x0c,0x00,0x12,0x01,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,
17790xa3,0x82,0x8c,0x50,0xaf,0x80,0x8c,0x3c,0x10,0x60,0xff,0x73,0x3c,0x02,0xb0,0x05,
17800x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,
17810x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x8c,0x40,0x10,0x40,0xff,0xe7,
17820x24,0x02,0x00,0x06,0x24,0x04,0x00,0x02,0xaf,0x84,0x8c,0x28,0x08,0x00,0x1a,0xa6,
17830x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x20,0x27,0x85,0x90,0xf8,0x0c,0x00,0x12,0xc7,
17840x00,0x00,0x00,0x00,0x8f,0x82,0x8c,0x44,0xaf,0x80,0x8c,0x4c,0x14,0x40,0x00,0x18,
17850x00,0x40,0x18,0x21,0x8f,0x82,0x8c,0x48,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x14,
17860x24,0x02,0x00,0x02,0x8f,0x83,0x8c,0x28,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,
17870x24,0x02,0x00,0x01,0x8f,0x83,0x8c,0x24,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x02,
17880x24,0x02,0x00,0x03,0x24,0x02,0x00,0x06,0xaf,0x82,0x8c,0x20,0x08,0x00,0x1b,0x20,
17890x24,0x04,0x00,0x03,0x3c,0x02,0x40,0x00,0x34,0x42,0x00,0x14,0x3c,0x01,0xb0,0x05,
17900xac,0x22,0x00,0x00,0xaf,0x80,0x8c,0x20,0x08,0x00,0x1b,0x20,0x24,0x04,0x00,0x03,
17910x10,0x60,0x00,0x10,0x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x20,0x27,0x85,0x90,0xf8,
17920x0c,0x00,0x12,0xeb,0x00,0x00,0x00,0x00,0x8f,0x83,0x8c,0x24,0x24,0x02,0x00,0x01,
17930xa3,0x80,0x8c,0x50,0xaf,0x80,0x8c,0x28,0x10,0x62,0x00,0x02,0x24,0x02,0x00,0x03,
17940x24,0x02,0x00,0x04,0xaf,0x82,0x8c,0x20,0xaf,0x80,0x8c,0x44,0x08,0x00,0x1a,0x9c,
17950x00,0x00,0x00,0x00,0x83,0x82,0x8c,0x70,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x04,
17960x00,0x00,0x00,0x00,0x27,0x84,0x90,0xf8,0x0c,0x00,0x15,0x32,0x00,0x00,0x00,0x00,
17970x8f,0x82,0x8c,0x24,0xa3,0x80,0x8c,0x50,0xaf,0x80,0x8c,0x20,0xaf,0x80,0x8c,0x28,
17980x14,0x40,0x00,0x02,0x24,0x02,0x00,0x02,0xaf,0x82,0x8c,0x24,0xaf,0x80,0x8c,0x48,
17990x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0x27,0x84,0x8c,0x20,0x27,0x85,0x90,0xf8,
18000x0c,0x00,0x12,0xeb,0x00,0x00,0x00,0x00,0x8f,0x82,0x8c,0x24,0xa3,0x80,0x8c,0x50,
18010xaf,0x80,0x8c,0x20,0xaf,0x80,0x8c,0x28,0x14,0x40,0xff,0x11,0x24,0x02,0x00,0x02,
18020xaf,0x82,0x8c,0x24,0x08,0x00,0x1a,0x9c,0x00,0x00,0x00,0x00,0x27,0x84,0x90,0xf8,
18030x0c,0x00,0x15,0x32,0x00,0x00,0x00,0x00,0x08,0x00,0x1b,0x86,0x00,0x00,0x00,0x00,
18040x27,0x84,0x8c,0x78,0x0c,0x00,0x2e,0x70,0x00,0x00,0x00,0x00,0x08,0x00,0x1a,0xa5,
18050x00,0x00,0x00,0x00,0x0c,0x00,0x27,0x0a,0x00,0x00,0x00,0x00,0x93,0x82,0x92,0x14,
18060x00,0x00,0x00,0x00,0x14,0x40,0x00,0x2b,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,
18070x8c,0x44,0x00,0x00,0x8f,0x83,0xc2,0x50,0x8f,0x82,0xc2,0x54,0x00,0x83,0x18,0x23,
18080x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x23,0x3c,0x02,0xb0,0x03,0x24,0x04,0x05,0xa0,
18090x34,0x42,0x01,0x18,0x8c,0x42,0x00,0x00,0x0c,0x00,0x0b,0xfa,0x00,0x00,0x00,0x00,
18100x24,0x04,0x05,0xa4,0x0c,0x00,0x0b,0xfa,0x00,0x02,0x84,0x02,0x30,0x51,0xff,0xff,
18110x24,0x04,0x05,0xa8,0x00,0x02,0x94,0x02,0x0c,0x00,0x0b,0xfa,0x3a,0x10,0xff,0xff,
18120x3a,0x31,0xff,0xff,0x30,0x42,0xff,0xff,0x2e,0x10,0x00,0x01,0x2e,0x31,0x00,0x01,
18130x3a,0x52,0xff,0xff,0x02,0x11,0x80,0x25,0x2e,0x52,0x00,0x01,0x38,0x42,0xff,0xff,
18140x02,0x12,0x80,0x25,0x2c,0x42,0x00,0x01,0x02,0x02,0x80,0x25,0x16,0x00,0x00,0x02,
18150x24,0x04,0x00,0x02,0x00,0x00,0x20,0x21,0x0c,0x00,0x0a,0x9c,0x00,0x00,0x00,0x00,
18160x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
18170xaf,0x83,0xc2,0x50,0x0c,0x00,0x01,0xcb,0x00,0x00,0x00,0x00,0xaf,0x80,0x8c,0x20,
18180xaf,0x80,0x8c,0x54,0x08,0x00,0x1a,0x88,0x00,0x00,0x00,0x00,0x27,0x90,0xba,0x40,
18190x24,0x11,0x00,0x12,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x10,
18200x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x1d,0x55,
18210x00,0x00,0x00,0x00,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xf6,0x26,0x10,0x00,0x04,
18220x08,0x00,0x1a,0xa6,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,
18230x8c,0x44,0x00,0x00,0x8f,0x82,0x8c,0x18,0x00,0x04,0x19,0xc2,0x00,0x02,0x11,0xc2,
18240x10,0x62,0xfe,0xc1,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x02,0x90,0x43,0x00,0x00,
18250x3c,0x12,0xb0,0x05,0xaf,0x84,0x8c,0x18,0x30,0x63,0x00,0xff,0x00,0x03,0x11,0x40,
18260x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x99,0x00,
18270x00,0x00,0x88,0x21,0x36,0x52,0x02,0x2c,0x27,0x90,0xba,0x40,0x8e,0x04,0x00,0x00,
18280x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x03,
18290x10,0x40,0x00,0x06,0x30,0x62,0x00,0x1c,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,
18300x8f,0x85,0x8c,0x18,0x0c,0x00,0x22,0xc6,0x02,0x60,0x30,0x21,0x8e,0x42,0x00,0x00,
18310x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x14,0x40,0xfe,0xa3,0x00,0x00,0x00,0x00,
18320x26,0x31,0x00,0x01,0x2a,0x22,0x00,0x13,0x14,0x40,0xff,0xec,0x26,0x10,0x00,0x04,
18330x08,0x00,0x1a,0xa6,0x00,0x00,0x00,0x00,0x8f,0x84,0x8c,0x2c,0x27,0x85,0x90,0xf8,
18340x0c,0x00,0x1c,0x2e,0x00,0x00,0x00,0x00,0x8f,0x83,0x8c,0x2c,0x24,0x02,0x00,0x04,
18350x14,0x62,0xfe,0x95,0x24,0x02,0x00,0x05,0x08,0x00,0x1b,0x23,0x00,0x00,0x00,0x00,
18360x27,0x84,0x90,0xf8,0x0c,0x00,0x27,0x2e,0x00,0x00,0x00,0x00,0x08,0x00,0x1a,0xcb,
18370x24,0x03,0x00,0x05,0x8f,0x82,0x91,0x2c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,
18380x00,0x00,0x00,0x00,0x8f,0x84,0xba,0x80,0xaf,0x80,0x91,0x2c,0x94,0x85,0x00,0x14,
18390x0c,0x00,0x1f,0xdd,0x00,0x00,0x00,0x00,0x93,0x82,0x91,0x51,0x00,0x00,0x00,0x00,
18400x30,0x42,0x00,0x02,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x60,
18410x00,0x00,0x20,0x21,0x8f,0x84,0xba,0x80,0x0c,0x00,0x1d,0x55,0x00,0x00,0x00,0x00,
18420x08,0x00,0x1a,0xa6,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,0x3c,0x06,0xb0,0x03,
18430xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x34,0xc6,0x00,0x5f,0xaf,0xbf,0x00,0x18,
18440x90,0xc3,0x00,0x00,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x5d,0x34,0x63,0x00,0x01,
18450x3c,0x09,0xb0,0x03,0x24,0x02,0x00,0x01,0xa0,0xc3,0x00,0x00,0x00,0x80,0x80,0x21,
18460xa0,0xe2,0x00,0x00,0x00,0xa0,0x88,0x21,0x35,0x29,0x00,0x5e,0x00,0xe0,0x40,0x21,
18470x24,0x04,0x00,0x01,0x91,0x22,0x00,0x00,0x91,0x03,0x00,0x00,0x30,0x42,0x00,0x01,
18480x14,0x83,0x00,0x03,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,
18490x24,0x02,0x00,0x04,0x12,0x02,0x00,0x2c,0x24,0x05,0x0f,0x00,0x24,0x02,0x00,0x06,
18500x12,0x02,0x00,0x08,0x24,0x05,0x00,0x0f,0x3c,0x02,0xb0,0x03,0x34,0x42,0x02,0x00,
18510xa0,0x50,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
18520x27,0xbd,0x00,0x20,0x24,0x04,0x0c,0x04,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x0f,
18530x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x0f,
18540x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x0f,
18550x24,0x04,0x08,0x8c,0x24,0x05,0x0f,0x00,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x0f,
18560x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x02,
18570x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x02,
18580x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x02,
18590x24,0x04,0x08,0x3c,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,0x24,0x06,0x00,0x02,
18600x08,0x00,0x1c,0x4f,0x3c,0x02,0xb0,0x03,0x24,0x04,0x08,0x8c,0x0c,0x00,0x18,0x5b,
18610x24,0x06,0x00,0x04,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00,0x0c,0x00,0x18,0x5b,
18620x24,0x06,0x00,0x04,0x24,0x04,0x0c,0x04,0x24,0x05,0x00,0x0f,0x0c,0x00,0x18,0x5b,
18630x24,0x06,0x00,0x04,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f,0x0c,0x00,0x18,0x5b,
18640x24,0x06,0x00,0x04,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,
18650x24,0x06,0x00,0x03,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,
18660x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30,0x0c,0x00,0x18,0x5b,
18670x24,0x06,0x00,0x02,0x3c,0x05,0x00,0x30,0x24,0x06,0x00,0x03,0x0c,0x00,0x18,0x5b,
18680x24,0x04,0x08,0x3c,0x02,0x20,0x20,0x21,0x24,0x05,0x00,0x14,0x0c,0x00,0x18,0xa0,
18690x24,0x06,0x01,0x07,0x08,0x00,0x1c,0x4f,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,
18700x3c,0x02,0x80,0x00,0x00,0x80,0x70,0x21,0x34,0x63,0x00,0x20,0x24,0x42,0x72,0x6c,
18710x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x30,0xad,0xc0,0x02,0xb8,
18720x8c,0x83,0x00,0x00,0x24,0x02,0x00,0xff,0xa5,0xc0,0x00,0x0a,0x00,0x00,0x30,0x21,
18730xa7,0x82,0x96,0x30,0x27,0x88,0x96,0x40,0xa5,0xc3,0x00,0x08,0x3c,0x07,0xb0,0x08,
18740x30,0xc2,0xff,0xff,0x00,0x02,0x20,0xc0,0x24,0xc3,0x00,0x01,0x00,0x82,0x10,0x21,
18750x00,0x60,0x30,0x21,0x00,0x02,0x10,0x80,0x30,0x63,0xff,0xff,0x00,0x48,0x10,0x21,
18760x00,0x87,0x20,0x21,0x28,0xc5,0x00,0xff,0xac,0x83,0x00,0x00,0x14,0xa0,0xff,0xf4,
18770xa4,0x43,0x00,0x00,0x3c,0x02,0xb0,0x08,0x34,0x03,0xff,0xff,0x34,0x42,0x07,0xf8,
18780x3c,0x04,0xb0,0x08,0xac,0x43,0x00,0x00,0xa7,0x83,0xba,0x1c,0x24,0x06,0x01,0x00,
18790x34,0x84,0x08,0x00,0x24,0xc2,0x00,0x01,0x28,0x43,0x02,0x00,0xac,0x82,0x00,0x00,
18800x00,0x40,0x30,0x21,0x14,0x60,0xff,0xfb,0x24,0x84,0x00,0x08,0x25,0xc2,0x00,0x0c,
18810x24,0x0a,0x00,0x02,0x3c,0x06,0xb0,0x03,0xaf,0x82,0xba,0x40,0x34,0xc6,0x00,0x64,
18820xa0,0x4a,0x00,0x18,0x94,0xc5,0x00,0x00,0x8f,0x82,0xba,0x40,0x25,0xc4,0x00,0x30,
18830x24,0x08,0x00,0x03,0x3c,0x03,0xb0,0x03,0xa0,0x45,0x00,0x21,0x34,0x63,0x00,0x66,
18840xaf,0x84,0xba,0x44,0xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xba,0x44,
18850x25,0xc4,0x00,0x54,0x25,0xc7,0x00,0x78,0xa0,0x45,0x00,0x21,0xaf,0x84,0xba,0x48,
18860xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xba,0x48,0x25,0xc8,0x00,0x9c,
18870x24,0x09,0x00,0x01,0xa0,0x45,0x00,0x21,0xaf,0x87,0xba,0x4c,0xa0,0xea,0x00,0x18,
18880x94,0xc4,0x00,0x00,0x8f,0x82,0xba,0x4c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x62,
18890xa0,0x44,0x00,0x21,0xaf,0x88,0xba,0x50,0xa1,0x09,0x00,0x18,0x94,0x65,0x00,0x00,
18900x8f,0x82,0xba,0x50,0x25,0xc4,0x00,0xc0,0x25,0xc6,0x00,0xe4,0xa0,0x45,0x00,0x21,
18910xaf,0x84,0xba,0x54,0xa0,0x89,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xba,0x54,
18920x3c,0x04,0xb0,0x03,0x34,0x84,0x00,0x60,0xa0,0x45,0x00,0x21,0xaf,0x86,0xba,0x58,
18930xa0,0xc0,0x00,0x18,0x94,0x85,0x00,0x00,0x8f,0x82,0xba,0x58,0x25,0xc3,0x01,0x08,
18940x25,0xc6,0x01,0x2c,0xa0,0x45,0x00,0x21,0xaf,0x83,0xba,0x5c,0xa0,0x60,0x00,0x18,
18950x94,0x87,0x00,0x00,0x8f,0x82,0xba,0x5c,0x25,0xc5,0x01,0x50,0x25,0xc4,0x01,0x74,
18960xa0,0x47,0x00,0x21,0x25,0xc8,0x01,0x98,0x25,0xc9,0x01,0xbc,0x25,0xca,0x01,0xe0,
18970x25,0xcb,0x02,0x04,0x25,0xcc,0x02,0x28,0x25,0xcd,0x02,0x4c,0x24,0x02,0x00,0x10,
18980x3c,0x03,0xb0,0x03,0xaf,0x86,0xba,0x60,0x34,0x63,0x00,0x38,0xa0,0xc0,0x00,0x18,
18990xaf,0x85,0xba,0x64,0xa0,0xa0,0x00,0x18,0xaf,0x84,0xba,0x68,0xa0,0x80,0x00,0x18,
19000xaf,0x88,0xba,0x6c,0xa1,0x00,0x00,0x18,0xaf,0x89,0xba,0x70,0xa1,0x20,0x00,0x18,
19010xaf,0x8a,0xba,0x74,0xa1,0x40,0x00,0x18,0xaf,0x8b,0xba,0x78,0xa1,0x60,0x00,0x18,
19020xaf,0x8c,0xba,0x7c,0xa1,0x80,0x00,0x18,0xaf,0x8d,0xba,0x80,0xa1,0xa2,0x00,0x18,
19030x94,0x64,0x00,0x00,0x8f,0x82,0xba,0x80,0x25,0xc5,0x02,0x70,0x3c,0x03,0xb0,0x03,
19040xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x11,0xaf,0x85,0xba,0x84,0x34,0x63,0x00,0x6e,
19050xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xba,0x84,0x25,0xc5,0x02,0x94,
19060x3c,0x03,0xb0,0x03,0xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x12,0xaf,0x85,0xba,0x88,
19070x34,0x63,0x00,0x6c,0xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xba,0x88,
19080x24,0x05,0xff,0xff,0x24,0x07,0x00,0x01,0xa0,0x44,0x00,0x21,0x24,0x06,0x00,0x12,
19090x27,0x84,0xba,0x40,0x8c,0x82,0x00,0x00,0x24,0xc6,0xff,0xff,0xa0,0x40,0x00,0x04,
19100x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x00,0xa4,0x45,0x00,0x02,0xa0,0x60,0x00,0x0a,
19110x8c,0x82,0x00,0x00,0xa4,0x65,0x00,0x06,0xa4,0x65,0x00,0x08,0xa0,0x40,0x00,0x10,
19120x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x0c,0xa4,0x45,0x00,0x0e,0xa0,0x60,0x00,0x12,
19130x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x40,0x00,0x16,0x8c,0x83,0x00,0x00,
19140xa4,0x45,0x00,0x14,0xa0,0x67,0x00,0x17,0x8c,0x82,0x00,0x00,0x24,0x84,0x00,0x04,
19150xa0,0x40,0x00,0x20,0x04,0xc1,0xff,0xe7,0xac,0x40,0x00,0x1c,0x03,0xe0,0x00,0x08,
19160x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,
19170x24,0x63,0x75,0x54,0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x10,0x00,0x80,0x60,0x21,
19180x10,0x40,0x00,0x56,0x00,0x00,0x70,0x21,0x97,0x82,0x96,0x30,0x94,0x8a,0x00,0x0c,
19190x27,0x87,0x96,0x40,0x00,0x02,0x40,0xc0,0x01,0x02,0x10,0x21,0x00,0x02,0x10,0x80,
19200x00,0x47,0x10,0x21,0x90,0x8b,0x00,0x18,0xa4,0x4a,0x00,0x00,0x94,0x83,0x00,0x0e,
19210x39,0x64,0x00,0x10,0x2c,0x84,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
19220x34,0x85,0x00,0x02,0x39,0x63,0x00,0x11,0x00,0x83,0x28,0x0b,0x34,0xa3,0x00,0x08,
19230x39,0x64,0x00,0x12,0x00,0x02,0x10,0x80,0x00,0xa4,0x18,0x0b,0x00,0x47,0x10,0x21,
19240x94,0x49,0x00,0x04,0x34,0x64,0x00,0x20,0x00,0x6b,0x20,0x0b,0x34,0x83,0x00,0x40,
19250x39,0x62,0x00,0x01,0x00,0x82,0x18,0x0b,0x00,0x09,0x30,0xc0,0x34,0x64,0x00,0x80,
19260x00,0xc9,0x28,0x21,0x39,0x62,0x00,0x02,0x00,0x60,0x68,0x21,0x00,0x82,0x68,0x0a,
19270x00,0x05,0x28,0x80,0x3c,0x02,0xb0,0x08,0x00,0xa7,0x28,0x21,0x00,0xc2,0x30,0x21,
19280x01,0x02,0x40,0x21,0x34,0x03,0xff,0xff,0x35,0xa4,0x01,0x00,0x39,0x62,0x00,0x03,
19290x2d,0x67,0x00,0x13,0xad,0x0a,0x00,0x00,0xa4,0xa3,0x00,0x00,0xac,0xc3,0x00,0x00,
19300xa7,0x89,0x96,0x30,0x10,0xe0,0x00,0x0f,0x00,0x82,0x68,0x0a,0x3c,0x03,0x80,0x01,
19310x00,0x0b,0x10,0x80,0x24,0x63,0x09,0x4c,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,
19320x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
19330x34,0x63,0x00,0x60,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x00,
19340x00,0x02,0x74,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x44,0x00,0x00,
19350x93,0x83,0x96,0x24,0x91,0x82,0x00,0x21,0x01,0xc4,0x20,0x21,0x91,0x85,0x00,0x10,
19360x00,0x04,0x24,0x00,0x00,0x62,0x18,0x21,0x00,0x04,0x74,0x03,0x00,0x6e,0x18,0x23,
19370x00,0x65,0x10,0x2a,0x00,0xa2,0x18,0x0a,0x00,0x0d,0x24,0x00,0x3c,0x02,0xb0,0x06,
19380x24,0x05,0xff,0xff,0x00,0x64,0x18,0x25,0x34,0x42,0x80,0x20,0xac,0x43,0x00,0x00,
19390xa5,0x85,0x00,0x0e,0xa1,0x80,0x00,0x10,0xa5,0x85,0x00,0x0c,0x03,0xe0,0x00,0x08,
19400x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x08,0x00,0x1d,0x99,0x34,0x63,0x00,0x62,
19410x3c,0x03,0xb0,0x03,0x08,0x00,0x1d,0x99,0x34,0x63,0x00,0x64,0x3c,0x03,0xb0,0x03,
19420x08,0x00,0x1d,0x99,0x34,0x63,0x00,0x66,0x3c,0x03,0xb0,0x03,0x08,0x00,0x1d,0x99,
19430x34,0x63,0x00,0x38,0x3c,0x03,0xb0,0x03,0x08,0x00,0x1d,0x99,0x34,0x63,0x00,0x6e,
19440x3c,0x03,0xb0,0x03,0x08,0x00,0x1d,0x99,0x34,0x63,0x00,0x6c,0x3c,0x03,0xb0,0x03,
19450x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x77,0x1c,0x00,0x05,0x28,0x40,
19460xac,0x62,0x00,0x00,0x00,0xa6,0x28,0x21,0x2c,0xe2,0x00,0x10,0x14,0x80,0x00,0x06,
19470x00,0x00,0x18,0x21,0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0xe0,0x18,0x21,
19480x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x24,0x02,0x00,0x20,0x10,0xe2,0x00,0x06,
19490x2c,0xe4,0x00,0x10,0x24,0xa2,0x00,0x01,0x10,0x80,0xff,0xf9,0x00,0x02,0x11,0x00,
19500x08,0x00,0x1d,0xd4,0x00,0x47,0x18,0x21,0x08,0x00,0x1d,0xd4,0x24,0xa3,0x00,0x50,
19510x27,0xbd,0xff,0xc0,0xaf,0xb7,0x00,0x34,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,
19520xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38,
19530xaf,0xb6,0x00,0x30,0xaf,0xb3,0x00,0x24,0xaf,0xb0,0x00,0x18,0x84,0x85,0x00,0x08,
19540x00,0x80,0x90,0x21,0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x34,0x84,0x00,0x20,
19550x24,0x42,0x77,0x80,0x3c,0x03,0xb0,0x06,0x00,0x05,0x28,0x80,0xac,0x82,0x00,0x00,
19560x00,0xa3,0x28,0x21,0x3c,0x04,0xb0,0x06,0x8c,0xa3,0x00,0x00,0x34,0x84,0x80,0x24,
19570x8c,0xa6,0x00,0x00,0x8c,0x82,0x00,0x00,0x30,0x71,0xff,0xff,0x00,0x11,0x2a,0x00,
19580x34,0x42,0x01,0x00,0x3c,0x03,0xb0,0x00,0xac,0x82,0x00,0x00,0x00,0xa3,0x40,0x21,
19590x8d,0x1e,0x00,0x00,0x8d,0x13,0x00,0x04,0x96,0x44,0x00,0x08,0x00,0x11,0xa0,0xc0,
19600x02,0x91,0x10,0x21,0x00,0x02,0x38,0x80,0x00,0x13,0x12,0x02,0x30,0x42,0x00,0x1f,
19610x24,0x84,0x00,0x02,0x27,0x83,0x96,0x50,0xa6,0x42,0x00,0x06,0x30,0x84,0x01,0xff,
19620x24,0x02,0x00,0x10,0x00,0xe3,0x18,0x21,0xa6,0x44,0x00,0x08,0x8d,0x10,0x00,0x08,
19630xa0,0x62,0x00,0x06,0x86,0x44,0x00,0x06,0x27,0x82,0x96,0x44,0x00,0xe2,0x10,0x21,
19640xac,0x48,0x00,0x18,0x24,0x02,0x00,0x13,0x00,0x06,0xbc,0x02,0x10,0x82,0x00,0xe6,
19650x00,0x00,0xa8,0x21,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,0xa6,0x40,0x00,0x02,
19660x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x45,0x00,0x00,
19670x00,0x10,0x1b,0xc2,0x00,0x04,0x20,0x82,0x27,0x82,0x96,0x40,0x00,0xe2,0x10,0x21,
19680x30,0x84,0x00,0x01,0x30,0x63,0x00,0x01,0xac,0x45,0x00,0x08,0x10,0x60,0x00,0xbc,
19690xaf,0xa4,0x00,0x10,0x00,0x10,0x16,0x82,0x30,0x46,0x00,0x01,0x00,0x10,0x12,0x02,
19700x00,0x10,0x19,0xc2,0x00,0x10,0x26,0x02,0x00,0x10,0x2e,0x42,0x30,0x47,0x00,0x7f,
19710x24,0x02,0x00,0x01,0x30,0x76,0x00,0x01,0x30,0x84,0x00,0x01,0x10,0xc2,0x00,0xa7,
19720x30,0xa3,0x00,0x01,0x0c,0x00,0x1d,0xc7,0x00,0x60,0x28,0x21,0x00,0x40,0xa8,0x21,
19730x02,0x91,0x10,0x21,0x00,0x02,0x10,0x80,0x2e,0xa4,0x00,0x54,0x27,0x85,0x96,0x50,
19740x27,0x83,0x96,0x48,0x00,0x04,0xa8,0x0a,0x00,0x45,0x28,0x21,0x26,0xc4,0x00,0x02,
19750x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x06,0xa0,0x55,0x00,0x07,0xa0,0xb5,0x00,0x02,
19760xa0,0xb5,0x00,0x01,0x00,0x10,0x14,0x82,0x00,0x10,0x1d,0xc2,0x30,0x48,0x00,0x01,
19770x00,0x13,0x15,0x82,0x00,0x13,0x21,0x82,0x30,0x63,0x00,0x01,0x00,0x10,0x2c,0x02,
19780x00,0x10,0x34,0x42,0x30,0x49,0x00,0x03,0x24,0x02,0x00,0x01,0xa6,0x5e,0x00,0x04,
19790xa6,0x43,0x00,0x00,0x30,0x8a,0x00,0x01,0x32,0x73,0x00,0x07,0x30,0xa5,0x00,0x01,
19800x30,0xc6,0x00,0x01,0x11,0x02,0x00,0x77,0x32,0x07,0x00,0x7f,0x15,0x40,0x00,0x03,
19810x00,0x00,0x00,0x00,0x15,0x20,0x00,0x68,0x24,0x02,0x00,0x01,0x96,0x42,0x00,0x04,
19820x00,0x00,0x00,0x00,0x24,0x42,0x00,0x04,0xa6,0x42,0x00,0x04,0x00,0xa0,0x20,0x21,
19830x00,0xc0,0x28,0x21,0x0c,0x00,0x1d,0xc7,0x01,0x00,0x30,0x21,0x02,0x91,0x18,0x21,
19840x00,0x03,0x38,0x80,0x2e,0xa5,0x00,0x54,0x27,0x84,0x96,0x50,0x00,0xe4,0x20,0x21,
19850x00,0x05,0x10,0x0a,0xa0,0x82,0x00,0x00,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
19860x96,0x45,0x00,0x04,0x27,0x82,0x96,0x40,0x00,0xe2,0x10,0x21,0xa4,0x45,0x00,0x06,
19870x27,0x83,0x96,0x44,0x00,0xe3,0x18,0x21,0x92,0x45,0x00,0x01,0x8c,0x66,0x00,0x18,
19880x27,0x82,0x96,0x60,0x00,0xe2,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x85,0x00,0x07,
19890x94,0xc3,0x00,0x10,0x24,0x02,0x00,0x04,0x30,0x63,0x00,0x0f,0x10,0x62,0x00,0x42,
19900x24,0xc6,0x00,0x10,0x94,0xc3,0x00,0x16,0x27,0x88,0x96,0x58,0x00,0xe8,0x10,0x21,
19910xa4,0x43,0x00,0x02,0x94,0xc2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,
19920x14,0x40,0x00,0x30,0x02,0x91,0x20,0x21,0x94,0xc2,0x00,0x00,0x24,0x03,0x00,0xa4,
19930x30,0x42,0x00,0xff,0x10,0x43,0x00,0x2b,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x00,
19940x24,0x03,0x00,0x88,0x30,0x42,0x00,0x88,0x10,0x43,0x00,0x20,0x02,0x91,0x18,0x21,
19950x27,0x84,0x96,0x60,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00,
19960x3c,0x04,0x00,0x80,0x00,0x44,0x10,0x25,0xac,0x62,0x00,0x00,0x00,0x17,0x10,0xc0,
19970x00,0x57,0x10,0x21,0x27,0x84,0x96,0x40,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,
19980x94,0x45,0x00,0x00,0x02,0x91,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x64,0x20,0x21,
19990x24,0x02,0xff,0xff,0x00,0x68,0x18,0x21,0xa0,0x73,0x00,0x00,0xa4,0x82,0x00,0x02,
20000xa4,0x97,0x00,0x04,0xae,0x51,0x02,0xb8,0xa6,0x45,0x00,0x0a,0x7b,0xbe,0x01,0xfc,
20010x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,
20020x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x94,0xc2,0x00,0x18,
20030x00,0x00,0x00,0x00,0x30,0x42,0x00,0x60,0x10,0x40,0xff,0xdd,0x02,0x91,0x18,0x21,
20040x02,0x91,0x20,0x21,0x27,0x82,0x96,0x60,0x00,0x04,0x20,0x80,0x00,0x82,0x20,0x21,
20050x8c,0x83,0x00,0x00,0x3c,0x02,0xff,0x7f,0x34,0x42,0xff,0xff,0x00,0x62,0x18,0x24,
20060x08,0x00,0x1e,0x97,0xac,0x83,0x00,0x00,0x27,0x88,0x96,0x58,0x00,0xe8,0x10,0x21,
20070x08,0x00,0x1e,0x81,0xa4,0x40,0x00,0x02,0x11,0x22,0x00,0x07,0x00,0x00,0x00,0x00,
20080x2d,0x22,0x00,0x02,0x14,0x40,0xff,0x9a,0x00,0xa0,0x20,0x21,0x96,0x42,0x00,0x04,
20090x08,0x00,0x1e,0x5e,0x24,0x42,0x00,0x0c,0x96,0x42,0x00,0x04,0x08,0x00,0x1e,0x5e,
20100x24,0x42,0x00,0x08,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x48,0xff,0x87,
20110x02,0x91,0x18,0x21,0x27,0x82,0x96,0x44,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,
20120x8c,0x64,0x00,0x18,0x3c,0x02,0xff,0xfb,0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,
20130xac,0x82,0x00,0x08,0x08,0x00,0x1e,0x57,0x00,0x00,0x40,0x21,0x8f,0xa2,0x00,0x10,
20140x00,0x00,0x00,0x00,0x14,0x46,0xff,0x57,0x3c,0x02,0xfb,0xff,0x34,0x42,0xff,0xff,
20150x02,0x02,0x10,0x24,0xad,0x02,0x00,0x08,0x08,0x00,0x1e,0x35,0x00,0x00,0x30,0x21,
20160x93,0x88,0xc1,0x54,0x00,0x10,0x1e,0x42,0x00,0x10,0x26,0x82,0x27,0x82,0x96,0x48,
20170x2d,0x05,0x00,0x0c,0x00,0xe2,0x48,0x21,0x30,0x63,0x00,0x01,0x30,0x86,0x00,0x01,
20180x14,0xa0,0x00,0x06,0x01,0x00,0x38,0x21,0x00,0x03,0x10,0x40,0x00,0x46,0x10,0x21,
20190x00,0x02,0x11,0x00,0x01,0x02,0x10,0x21,0x24,0x47,0x00,0x04,0x02,0x91,0x10,0x21,
20200x00,0x02,0x10,0x80,0x27,0x84,0x96,0x50,0x27,0x83,0x96,0x48,0x00,0x44,0x20,0x21,
20210x00,0x43,0x10,0x21,0xa1,0x27,0x00,0x07,0xa0,0x40,0x00,0x06,0xa0,0x80,0x00,0x02,
20220x08,0x00,0x1e,0x45,0xa0,0x80,0x00,0x01,0x24,0x02,0x00,0x01,0xa6,0x42,0x00,0x02,
20230x0c,0x00,0x04,0x40,0x01,0x00,0x20,0x21,0x08,0x00,0x1e,0xa7,0x00,0x00,0x00,0x00,
20240x30,0xa7,0xff,0xff,0x00,0x07,0x18,0xc0,0x00,0x67,0x18,0x21,0x3c,0x06,0xb0,0x03,
20250x3c,0x02,0x80,0x00,0x24,0x42,0x7c,0x10,0x27,0x85,0x96,0x50,0x00,0x03,0x18,0x80,
20260x34,0xc6,0x00,0x20,0x00,0x65,0x18,0x21,0xac,0xc2,0x00,0x00,0x80,0x62,0x00,0x07,
20270x00,0x00,0x00,0x00,0x10,0x40,0x00,0x29,0x00,0x80,0x28,0x21,0x90,0x82,0x00,0x16,
20280x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0x30,0x43,0x00,0x01,0x14,0x60,0x00,0x02,
20290xa0,0x82,0x00,0x16,0xa0,0x80,0x00,0x17,0x90,0xa2,0x00,0x04,0x3c,0x03,0xb0,0x03,
20300x27,0x86,0x96,0x40,0x14,0x40,0x00,0x06,0x34,0x63,0x00,0x20,0x24,0x02,0x00,0x01,
20310xa0,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02,0x03,0xe0,0x00,0x08,0xa4,0xa7,0x00,0x00,
20320x94,0xa4,0x00,0x02,0x3c,0x02,0x80,0x01,0x24,0x42,0x93,0x34,0xac,0x62,0x00,0x00,
20330x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,
20340x94,0x62,0x00,0x04,0xa4,0x67,0x00,0x02,0x3c,0x03,0xb0,0x08,0x00,0x02,0x20,0xc0,
20350x00,0x82,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x00,0x83,0x20,0x21,
20360xa4,0x47,0x00,0x00,0xac,0x87,0x00,0x00,0x90,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02,
20370x24,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x04,0x90,0x82,0x00,0x16,
20380x24,0x85,0x00,0x06,0x34,0x42,0x00,0x01,0x30,0x43,0x00,0x02,0x14,0x60,0xff,0xda,
20390xa0,0x82,0x00,0x16,0x24,0x02,0x00,0x01,0x08,0x00,0x1f,0x1a,0xa0,0x82,0x00,0x17,
20400x27,0xbd,0xff,0xe8,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x00,0x80,0x80,0x21,
20410x84,0x84,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
20420x24,0x42,0x7d,0x10,0x10,0x80,0x00,0x38,0xac,0x62,0x00,0x00,0x8e,0x04,0x02,0xb8,
20430x0c,0x00,0x02,0x7e,0x00,0x00,0x00,0x00,0x97,0x88,0x96,0x30,0x96,0x0c,0x02,0xba,
20440x3c,0x04,0xb0,0x08,0x00,0x08,0x30,0xc0,0x00,0xc4,0x10,0x21,0xac,0x4c,0x00,0x00,
20450x8e,0x03,0x02,0xb8,0x27,0x89,0x96,0x40,0x34,0x0b,0xff,0xff,0x00,0x03,0x10,0xc0,
20460x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,0x94,0x4a,0x00,0x04,
20470x00,0xc8,0x30,0x21,0x00,0x06,0x30,0x80,0x00,0x0a,0x28,0xc0,0x00,0xa4,0x20,0x21,
20480xac,0x8b,0x00,0x00,0x8e,0x02,0x02,0xb8,0x27,0x84,0x96,0x50,0x00,0xaa,0x28,0x21,
20490x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,0x27,0x82,0x96,0x44,
20500x00,0x62,0x10,0x21,0x8c,0x47,0x00,0x18,0x00,0x64,0x18,0x21,0x80,0x68,0x00,0x06,
20510x8c,0xe4,0x00,0x00,0x00,0x05,0x28,0x80,0x3c,0x03,0xb0,0x06,0x30,0x84,0xff,0xff,
20520x00,0x88,0x20,0x21,0x30,0x82,0x00,0xff,0x00,0x02,0x10,0x2b,0x00,0x04,0x22,0x02,
20530x00,0x82,0x20,0x21,0x3c,0x02,0x00,0x04,0x00,0xa9,0x28,0x21,0x00,0x82,0x20,0x25,
20540x00,0xc9,0x30,0x21,0x34,0x63,0x80,0x20,0xa4,0xcc,0x00,0x00,0xac,0x64,0x00,0x00,
20550xa4,0xab,0x00,0x00,0xa7,0x8a,0x96,0x30,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
20560x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x86,0x03,0x00,0x06,0x27,0x82,0xba,0x40,
20570x96,0x05,0x02,0xba,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,
20580x0c,0x00,0x1f,0x04,0x00,0x00,0x00,0x00,0x08,0x00,0x1f,0x82,0x00,0x00,0x00,0x00,
20590x94,0x88,0x00,0x00,0x00,0x80,0x58,0x21,0x27,0x8a,0x96,0x40,0x00,0x08,0x18,0xc0,
20600x00,0x68,0x18,0x21,0x3c,0x04,0xb0,0x03,0x00,0x03,0x18,0x80,0x3c,0x02,0x80,0x00,
20610x00,0x6a,0x18,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x7e,0x40,0x30,0xa5,0xff,0xff,
20620xac,0x82,0x00,0x00,0x94,0x67,0x00,0x02,0x11,0x05,0x00,0x35,0x24,0x04,0x00,0x01,
20630x91,0x66,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x86,0x10,0x2a,0x10,0x40,0x00,0x10,
20640x00,0xc0,0x48,0x21,0x3c,0x0d,0xb0,0x03,0x01,0x40,0x60,0x21,0x35,0xad,0x00,0x20,
20650x10,0xe5,0x00,0x0d,0x24,0x84,0x00,0x01,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21,
20660x00,0x02,0x10,0x80,0x01,0x20,0x30,0x21,0x00,0x4a,0x10,0x21,0x00,0x86,0x18,0x2a,
20670x00,0xe0,0x40,0x21,0x94,0x47,0x00,0x02,0x14,0x60,0xff,0xf5,0x00,0x00,0x00,0x00,
20680x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,0x00,0x08,0x20,0xc0,0x00,0x88,0x20,0x21,
20690x24,0xc2,0xff,0xff,0x00,0x04,0x20,0x80,0xa1,0x62,0x00,0x04,0x00,0x8c,0x20,0x21,
20700x94,0x83,0x00,0x04,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80,
20710x00,0x4c,0x10,0x21,0x00,0x03,0x28,0xc0,0x94,0x46,0x00,0x02,0x00,0xa3,0x18,0x21,
20720x00,0x03,0x18,0x80,0x00,0x6c,0x18,0x21,0xa4,0x66,0x00,0x00,0xa4,0x86,0x00,0x02,
20730x95,0x64,0x00,0x02,0x3c,0x03,0xb0,0x08,0x3c,0x02,0x80,0x01,0x00,0xa3,0x28,0x21,
20740x24,0x42,0x93,0x34,0xad,0xa2,0x00,0x00,0x10,0x87,0x00,0x03,0xac,0xa6,0x00,0x00,
20750x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x08,0x00,0x1f,0xd0,0xa5,0x68,0x00,0x02,
20760x91,0x62,0x00,0x04,0xa5,0x67,0x00,0x00,0x24,0x42,0xff,0xff,0x30,0x43,0x00,0xff,
20770x14,0x60,0xff,0xf7,0xa1,0x62,0x00,0x04,0x24,0x02,0xff,0xff,0x08,0x00,0x1f,0xd0,
20780xa5,0x62,0x00,0x02,0x00,0x05,0x40,0xc0,0x01,0x05,0x30,0x21,0x27,0xbd,0xff,0xd8,
20790x00,0x06,0x30,0x80,0x27,0x82,0x96,0x44,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
20800xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb0,0x00,0x10,0x00,0xc2,0x10,0x21,
20810x8c,0x47,0x00,0x18,0x00,0xa0,0x90,0x21,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,
20820x34,0xa5,0x00,0x20,0x24,0x42,0x7f,0x74,0xac,0xa2,0x00,0x00,0x27,0x83,0x96,0x50,
20830x00,0xc3,0x30,0x21,0x8c,0xe2,0x00,0x00,0x80,0xc5,0x00,0x06,0x00,0x80,0x88,0x21,
20840x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x02,
20850x00,0x02,0x12,0x02,0x24,0x42,0x00,0x01,0x30,0x53,0x00,0xff,0x01,0x12,0x10,0x21,
20860x00,0x02,0x10,0x80,0x27,0x83,0x96,0x50,0x00,0x43,0x10,0x21,0x80,0x44,0x00,0x07,
20870x00,0x00,0x00,0x00,0x10,0x80,0x00,0x4b,0x26,0x24,0x00,0x06,0x32,0x50,0xff,0xff,
20880x02,0x20,0x20,0x21,0x0c,0x00,0x1f,0x90,0x02,0x00,0x28,0x21,0x92,0x22,0x00,0x10,
20890x00,0x00,0x00,0x00,0x14,0x40,0x00,0x2e,0x3c,0x03,0xb0,0x08,0x3c,0x09,0x80,0x01,
20900x27,0x88,0x96,0x40,0xa6,0x32,0x00,0x0c,0x00,0x10,0x20,0xc0,0x00,0x90,0x20,0x21,
20910x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08,
20920x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,
20930x00,0x48,0x10,0x21,0x00,0xa3,0x28,0x21,0x25,0x26,0x93,0x34,0x34,0x03,0xff,0xff,
20940x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00,
20950xac,0xa3,0x00,0x00,0x92,0x22,0x00,0x10,0x92,0x23,0x00,0x0a,0xa6,0x32,0x00,0x0e,
20960x02,0x62,0x10,0x21,0x14,0x60,0x00,0x05,0xa2,0x22,0x00,0x10,0x92,0x22,0x00,0x16,
20970x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfe,0xa2,0x22,0x00,0x16,0x92,0x22,0x00,0x04,
20980x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x22,0x00,0x16,
20990x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x20,
21000x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
21010x96,0x22,0x00,0x0e,0x27,0x88,0x96,0x40,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,
21020x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x06,0xb0,0x03,
21030x3c,0x09,0x80,0x01,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,
21040x00,0xa3,0x28,0x21,0x00,0x48,0x10,0x21,0x34,0xc6,0x00,0x20,0x25,0x23,0x93,0x34,
21050xac,0xc3,0x00,0x00,0xa4,0x50,0x00,0x00,0xac,0xb0,0x00,0x00,0x08,0x00,0x20,0x0e,
21060xa4,0x90,0x00,0x02,0x08,0x00,0x20,0x05,0x32,0x50,0xff,0xff,0x3c,0x03,0xb0,0x03,
21070x3c,0x02,0x80,0x01,0x24,0x42,0x81,0x3c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,
21080x90,0x82,0x00,0x04,0x97,0xaa,0x00,0x12,0x00,0x80,0x60,0x21,0x30,0xa8,0xff,0xff,
21090x00,0x4a,0x20,0x23,0x34,0x09,0xff,0xff,0x30,0xcf,0xff,0xff,0x30,0xee,0xff,0xff,
21100x11,0x09,0x00,0x73,0xa1,0x84,0x00,0x04,0x00,0x0e,0xc0,0xc0,0x00,0x08,0x10,0xc0,
21110x00,0x48,0x10,0x21,0x03,0x0e,0x20,0x21,0x27,0x8d,0x96,0x40,0x00,0x04,0x20,0x80,
21120x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0x8d,0x20,0x21,0x94,0x86,0x00,0x02,
21130x94,0x43,0x00,0x04,0x3c,0x19,0x80,0x01,0xa4,0x46,0x00,0x02,0x00,0x03,0x28,0xc0,
21140x00,0xa3,0x18,0x21,0x94,0x87,0x00,0x02,0x3c,0x02,0xb0,0x08,0x00,0x03,0x18,0x80,
21150x00,0xa2,0x28,0x21,0x00,0x6d,0x18,0x21,0x27,0x22,0x93,0x34,0x3c,0x01,0xb0,0x03,
21160xac,0x22,0x00,0x20,0xa4,0x66,0x00,0x00,0x10,0xe9,0x00,0x57,0xac,0xa6,0x00,0x00,
21170x01,0xe0,0x30,0x21,0x11,0x40,0x00,0x1d,0x00,0x00,0x48,0x21,0x01,0x40,0x38,0x21,
21180x27,0x8b,0x96,0x44,0x27,0x8a,0x96,0x50,0x00,0x06,0x40,0xc0,0x01,0x06,0x18,0x21,
21190x00,0x03,0x18,0x80,0x00,0x6b,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x6a,0x18,0x21,
21200x80,0x65,0x00,0x06,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0xff,0xff,
21210x00,0x45,0x10,0x21,0x30,0x44,0x00,0xff,0x00,0x02,0x12,0x02,0x01,0x22,0x18,0x21,
21220x24,0x62,0x00,0x01,0x14,0x80,0x00,0x02,0x30,0x49,0x00,0xff,0x30,0x69,0x00,0xff,
21230x01,0x06,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x24,0xe7,0xff,0xff,
21240x94,0x46,0x00,0x02,0x14,0xe0,0xff,0xe9,0x00,0x06,0x40,0xc0,0x91,0x82,0x00,0x10,
21250x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x3c,0x06,0xb0,0x03,0xa5,0x8f,0x00,0x0c,
21260x03,0x0e,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04,
21270x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,
21280x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0xa3,0x28,0x21,0x27,0x26,0x93,0x34,
21290x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,
21300xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x91,0x82,0x00,0x10,0x91,0x83,0x00,0x04,
21310xa5,0x8e,0x00,0x0e,0x01,0x22,0x10,0x21,0x14,0x60,0x00,0x05,0xa1,0x82,0x00,0x10,
21320x91,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa1,0x82,0x00,0x16,
21330x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x95,0x82,0x00,0x0e,0x3c,0x03,0xb0,0x08,
21340x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,
21350x94,0x82,0x00,0x04,0x34,0xc6,0x00,0x20,0x27,0x27,0x93,0x34,0x00,0x02,0x28,0xc0,
21360x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,0x00,0x4d,0x10,0x21,
21370xac,0xc7,0x00,0x00,0xa4,0x8f,0x00,0x02,0xa4,0x4f,0x00,0x00,0xac,0xaf,0x00,0x00,
21380x08,0x00,0x20,0x9d,0x03,0x0e,0x20,0x21,0x08,0x00,0x20,0x78,0xa5,0x88,0x00,0x02,
21390x00,0x0e,0xc0,0xc0,0x03,0x0e,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x8d,0x96,0x40,
21400x00,0x4d,0x10,0x21,0x94,0x43,0x00,0x02,0x30,0x84,0x00,0xff,0x14,0x80,0x00,0x05,
21410xa5,0x83,0x00,0x00,0x24,0x02,0xff,0xff,0x3c,0x19,0x80,0x01,0x08,0x00,0x20,0x78,
21420xa5,0x82,0x00,0x02,0x08,0x00,0x20,0x78,0x3c,0x19,0x80,0x01,0x3c,0x08,0xb0,0x03,
21430x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0x80,0x24,0x42,0x83,0x7c,0x35,0x08,0x00,0x20,
21440xaf,0xb2,0x00,0x60,0xaf,0xb1,0x00,0x5c,0xaf,0xbf,0x00,0x7c,0xaf,0xbe,0x00,0x78,
21450xaf,0xb7,0x00,0x74,0xaf,0xb6,0x00,0x70,0xaf,0xb5,0x00,0x6c,0xaf,0xb4,0x00,0x68,
21460xaf,0xb3,0x00,0x64,0xaf,0xb0,0x00,0x58,0xad,0x02,0x00,0x00,0xaf,0xa4,0x00,0x80,
21470x90,0x83,0x00,0x0a,0x27,0x82,0xba,0x40,0xaf,0xa6,0x00,0x88,0x00,0x03,0x18,0x80,
21480x00,0x62,0x18,0x21,0x8c,0x7e,0x00,0x00,0xaf,0xa7,0x00,0x8c,0x27,0x86,0x96,0x44,
21490x97,0xc3,0x00,0x14,0x30,0xb1,0xff,0xff,0x00,0x03,0x20,0xc0,0xaf,0xa3,0x00,0x1c,
21500x00,0x83,0x18,0x21,0xaf,0xa4,0x00,0x50,0x00,0x03,0x18,0x80,0x27,0x84,0x96,0x50,
21510x00,0x64,0x20,0x21,0x80,0x82,0x00,0x06,0x00,0x66,0x18,0x21,0x8c,0x66,0x00,0x18,
21520x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x8c,0xc4,0x00,0x08,0x00,0x43,0x10,0x21,
21530x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0x04,0x2f,0xc2,0x00,0x04,0x1c,0x82,
21540x00,0x04,0x24,0x42,0x30,0x63,0x00,0x01,0x00,0xc2,0x38,0x21,0x30,0x84,0x00,0x01,
21550x24,0x02,0x00,0x01,0xaf,0xa5,0x00,0x3c,0xaf,0xa3,0x00,0x34,0xaf,0xa4,0x00,0x38,
21560xaf,0xa0,0x00,0x40,0xaf,0xa0,0x00,0x44,0xaf,0xa2,0x00,0x20,0x83,0xc3,0x00,0x12,
21570x8f,0xb2,0x00,0x1c,0x8c,0xd0,0x00,0x0c,0x14,0xa0,0x01,0xa2,0xaf,0xa3,0x00,0x28,
21580x00,0x10,0x10,0x82,0x30,0x45,0x00,0x07,0x10,0xa0,0x00,0x11,0xaf,0xa0,0x00,0x30,
21590x8f,0xa4,0x00,0x90,0x27,0x82,0x86,0xb0,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x21,
21600x24,0xa2,0x00,0x06,0x8f,0xa5,0x00,0x20,0x94,0x64,0x00,0x00,0x00,0x45,0x10,0x04,
21610x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,
21620x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,0x30,0x42,0xff,0xfc,0xaf,0xa2,0x00,0x30,
21630x8f,0xa3,0x00,0x1c,0x8f,0xa4,0x00,0x28,0x34,0x02,0xff,0xff,0xaf,0xa0,0x00,0x2c,
21640xaf,0xa2,0x00,0x48,0xaf,0xa3,0x00,0x4c,0x00,0x60,0xb0,0x21,0x00,0x00,0xb8,0x21,
21650x18,0x80,0x00,0x3b,0xaf,0xa0,0x00,0x24,0x00,0x11,0x89,0x02,0xaf,0xb1,0x00,0x54,
21660x00,0x80,0xa8,0x21,0x00,0x12,0xa0,0xc0,0x02,0x92,0x10,0x21,0x00,0x02,0x80,0x80,
21670x27,0x85,0x96,0x40,0x02,0x05,0x18,0x21,0x94,0x63,0x00,0x02,0x02,0x40,0x20,0x21,
21680x00,0x00,0x28,0x21,0x0c,0x00,0x17,0x43,0xaf,0xa3,0x00,0x18,0x90,0x42,0x00,0x00,
21690x24,0x03,0x00,0x08,0x30,0x42,0x00,0x0c,0x10,0x43,0x01,0x5c,0x24,0x04,0x00,0x01,
21700x24,0x02,0x00,0x01,0x10,0x82,0x01,0x3b,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x04,
21710x02,0x92,0x20,0x21,0x94,0x66,0x00,0x00,0x00,0x04,0x20,0x80,0x27,0x82,0x96,0x48,
21720x00,0x82,0x10,0x21,0x27,0x83,0x96,0x50,0x80,0x45,0x00,0x06,0x00,0x83,0x20,0x21,
21730x30,0xd0,0xff,0xff,0x80,0x91,0x00,0x05,0x80,0x93,0x00,0x04,0x8f,0xa4,0x00,0x80,
21740x32,0x03,0x00,0xff,0x00,0x10,0x12,0x03,0x38,0xa5,0x00,0x00,0x00,0x60,0x80,0x21,
21750x00,0x45,0x80,0x0a,0xa4,0x82,0x00,0x44,0x12,0x20,0x01,0x1c,0xa4,0x83,0x00,0x46,
21760x02,0x71,0x10,0x21,0x00,0x50,0x10,0x2a,0x14,0x40,0x00,0xbb,0x02,0x92,0x10,0x21,
21770x93,0x82,0x91,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0xae,
21780x02,0x92,0x28,0x21,0x26,0xe2,0x00,0x01,0x30,0x57,0xff,0xff,0x02,0x40,0xb0,0x21,
21790x26,0xb5,0xff,0xff,0x8f,0xb2,0x00,0x18,0x16,0xa0,0xff,0xca,0x00,0x00,0x00,0x00,
21800x16,0xe0,0x00,0x9e,0x02,0xc0,0x38,0x21,0x8f,0xa5,0x00,0x90,0x00,0x00,0x00,0x00,
21810x2c,0xa2,0x00,0x10,0x10,0x40,0x00,0x2e,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x24,
21820x00,0x00,0x00,0x00,0x18,0x40,0x00,0x2a,0x24,0x03,0x00,0x01,0x97,0xd2,0x00,0x14,
21830xa3,0xc3,0x00,0x12,0x00,0x12,0x10,0xc0,0x00,0x52,0x10,0x21,0x00,0x02,0x80,0x80,
21840x27,0x82,0x96,0x50,0x02,0x02,0x10,0x21,0x80,0x43,0x00,0x06,0x27,0x84,0x96,0x44,
21850x02,0x04,0x20,0x21,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,
21860x8c,0x85,0x00,0x18,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0x00,0xa3,0x38,0x21,
21870x8f,0xa3,0x00,0x3c,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0d,0x00,0x00,0x00,0x00,
21880x27,0x82,0x96,0x40,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,0x24,0x02,0x00,0x01,
21890xa7,0xc3,0x00,0x1a,0x7b,0xbe,0x03,0xfc,0x7b,0xb6,0x03,0xbc,0x7b,0xb4,0x03,0x7c,
21900x7b,0xb2,0x03,0x3c,0x7b,0xb0,0x02,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x80,
21910x8f,0xa4,0x00,0x90,0x8f,0xa5,0x00,0x38,0x8f,0xa6,0x00,0x34,0xaf,0xa0,0x00,0x10,
21920x0c,0x00,0x0d,0xfe,0xaf,0xa0,0x00,0x14,0x08,0x00,0x21,0x94,0x00,0x00,0x00,0x00,
21930x8f,0xa4,0x00,0x44,0x8f,0xa3,0x00,0x24,0x8f,0xa5,0x00,0x2c,0x30,0x82,0x00,0x03,
21940xa3,0xc3,0x00,0x12,0x00,0x02,0x10,0x23,0x8f,0xa4,0x00,0x80,0x30,0x42,0x00,0x03,
21950x00,0xa2,0x10,0x23,0xa7,0xc2,0x00,0x1a,0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,
21960x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x96,0x44,
21970x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,
21980x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0x00,0x18,0x00,0x00,0x00,0x00,
21990x8f,0xa5,0x00,0x50,0x8f,0xa2,0x00,0x1c,0x00,0x00,0x00,0x00,0x00,0xa2,0x18,0x21,
22000x00,0x03,0x18,0x80,0x27,0x82,0x96,0x58,0x00,0x62,0x18,0x21,0x90,0x65,0x00,0x00,
22010x27,0x83,0xba,0xe0,0x00,0x05,0x11,0x00,0x00,0x45,0x10,0x23,0x00,0x02,0x10,0x80,
22020x00,0x45,0x10,0x23,0x00,0x02,0x30,0x80,0x00,0xc3,0x38,0x21,0x90,0xe4,0x00,0x00,
22030x24,0x02,0x00,0x1b,0x10,0x82,0x00,0x0e,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x24,
22040x00,0x00,0x00,0x00,0x10,0x40,0x00,0x04,0x00,0xa0,0x20,0x21,0x8f,0xa2,0x00,0x24,
22050x08,0x00,0x21,0x99,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x21,0x00,0x00,0x28,0x21,
22060x0c,0x00,0x25,0xc4,0x00,0x00,0x38,0x21,0x08,0x00,0x21,0xd7,0x00,0x00,0x00,0x00,
22070x27,0x82,0xbb,0xc0,0x00,0xc2,0x20,0x21,0x94,0x83,0x00,0x00,0x24,0x02,0x00,0x05,
22080x10,0x43,0x00,0x25,0x24,0x62,0x00,0x01,0xa4,0x82,0x00,0x00,0x8f,0xa3,0x00,0x24,
22090x8f,0xa4,0x00,0x28,0x00,0x00,0x00,0x00,0x10,0x64,0xff,0xec,0x00,0x00,0x00,0x00,
22100x10,0x60,0xff,0xea,0x00,0x00,0x00,0x00,0x27,0x82,0xbb,0xb8,0x00,0xc2,0x20,0x21,
22110x90,0x83,0x00,0x06,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x03,
22120x24,0x62,0x00,0x01,0xa0,0x82,0x00,0x06,0x00,0x40,0x18,0x21,0x30,0x63,0x00,0xff,
22130x24,0x02,0x00,0x02,0x10,0x62,0x00,0x09,0x00,0x00,0x00,0x00,0x27,0x84,0xba,0xe4,
22140x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x58,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x23,
22150x24,0x42,0xff,0xc0,0x08,0x00,0x21,0xd7,0xac,0xe2,0x00,0xd0,0x3c,0x02,0xb0,0x03,
22160x34,0x42,0x01,0x08,0x8c,0x43,0x00,0x00,0x27,0x84,0xba,0xe4,0x00,0xc4,0x10,0x21,
22170x08,0x00,0x21,0xfc,0xac,0x43,0x00,0xe0,0x27,0x83,0xbb,0xb8,0x00,0xc3,0x18,0x21,
22180x90,0x62,0x00,0x06,0x00,0x00,0x00,0x00,0x2c,0x42,0x00,0x02,0x10,0x40,0xff,0xc7,
22190xa4,0x80,0x00,0x00,0x08,0x00,0x21,0xd7,0xa0,0x60,0x00,0x06,0x8f,0xa5,0x00,0x48,
22200x8f,0xa6,0x00,0x4c,0x03,0xc0,0x20,0x21,0x0c,0x00,0x20,0x4f,0xaf,0xb7,0x00,0x10,
22210x08,0x00,0x21,0x76,0x00,0x00,0x00,0x00,0x00,0x05,0x28,0x80,0x27,0x82,0x96,0x40,
22220x00,0xa2,0x28,0x21,0x00,0x00,0x20,0x21,0x0c,0x00,0x01,0x49,0x00,0x00,0x00,0x00,
22230x08,0x00,0x21,0x6e,0x26,0xe2,0x00,0x01,0x00,0x02,0x80,0x80,0x27,0x83,0x96,0x50,
22240x02,0x03,0x18,0x21,0x26,0x31,0x00,0x01,0x03,0xc0,0x20,0x21,0x02,0x40,0x28,0x21,
22250x0c,0x00,0x23,0x1c,0xa0,0x71,0x00,0x05,0x14,0x40,0xff,0x45,0x00,0x00,0x00,0x00,
22260x16,0xe0,0x00,0x4b,0x02,0xc0,0x38,0x21,0x8f,0xa5,0x00,0x24,0x8f,0xb6,0x00,0x18,
22270x8f,0xa3,0x00,0x20,0x24,0xa5,0x00,0x01,0x24,0x02,0x00,0x01,0xaf,0xb2,0x00,0x48,
22280xaf,0xb6,0x00,0x4c,0x10,0x62,0x00,0x40,0xaf,0xa5,0x00,0x24,0x27,0x82,0x96,0x40,
22290x02,0x02,0x10,0x21,0x94,0x42,0x00,0x06,0x8f,0xa5,0x00,0x30,0xaf,0xa0,0x00,0x20,
22300xaf,0xa2,0x00,0x44,0x8f,0xa4,0x00,0x44,0x30,0x42,0x00,0x03,0x00,0x02,0x10,0x23,
22310x30,0x42,0x00,0x03,0x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,
22320x00,0x45,0x18,0x2b,0x10,0x60,0x00,0x29,0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x2c,
22330x00,0xa2,0x10,0x23,0x00,0x85,0x18,0x21,0x30,0x63,0xff,0xff,0x30,0x45,0xff,0xff,
22340xaf,0xa3,0x00,0x2c,0x02,0x92,0x30,0x21,0x00,0x06,0x30,0x80,0x27,0x82,0x96,0x44,
22350x00,0xc2,0x10,0x21,0x8c,0x47,0x00,0x18,0x3c,0x04,0x80,0xff,0x34,0x84,0xff,0xff,
22360x8c,0xe3,0x00,0x04,0x3c,0x02,0x7f,0x00,0x00,0x05,0x2d,0x40,0x00,0xa2,0x28,0x24,
22370x00,0x64,0x18,0x24,0x00,0x65,0x18,0x25,0xac,0xe3,0x00,0x04,0x8f,0xa3,0x00,0x90,
22380x27,0x82,0x96,0x50,0x00,0xc2,0x10,0x21,0xa0,0x43,0x00,0x00,0x8c,0xe4,0x00,0x08,
22390x00,0x00,0x00,0x00,0x00,0x04,0x27,0xc2,0x10,0x80,0xff,0x0d,0xaf,0xa4,0x00,0x3c,
22400x80,0x42,0x00,0x06,0x8f,0xa4,0x00,0x40,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,
22410x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0xe2,0x38,0x21,
22420xa4,0xe4,0x00,0x00,0x08,0x00,0x21,0x71,0x26,0xb5,0xff,0xff,0x8f,0xa5,0x00,0x2c,
22430x00,0x00,0x00,0x00,0x00,0xa2,0x10,0x21,0x30,0x42,0xff,0xff,0xaf,0xa2,0x00,0x2c,
22440x08,0x00,0x22,0x4d,0x00,0x00,0x28,0x21,0x08,0x00,0x22,0x37,0xa7,0xd2,0x00,0x14,
22450x8f,0xa5,0x00,0x48,0x8f,0xa6,0x00,0x4c,0x03,0xc0,0x20,0x21,0x0c,0x00,0x20,0x4f,
22460xaf,0xb7,0x00,0x10,0x08,0x00,0x22,0x2e,0x00,0x00,0xb8,0x21,0x02,0x40,0x20,0x21,
22470x0c,0x00,0x17,0x43,0x00,0x00,0x28,0x21,0x00,0x40,0x18,0x21,0x94,0x42,0x00,0x00,
22480x00,0x00,0x00,0x00,0x34,0x42,0x08,0x00,0xa4,0x62,0x00,0x00,0x08,0x00,0x21,0x65,
22490x02,0x71,0x10,0x21,0x02,0x92,0x18,0x21,0x00,0x03,0x80,0x80,0x27,0x82,0x96,0x44,
22500x02,0x02,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,
22510x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x10,0x60,0x00,0x0a,0x24,0x06,0x00,0x01,
22520x93,0x82,0x91,0x51,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x10,0x40,0xfe,0xd5,
22530x00,0x00,0x00,0x00,0x27,0x85,0x96,0x40,0x02,0x05,0x28,0x21,0x08,0x00,0x22,0x1e,
22540x3c,0x04,0x00,0x80,0x27,0x83,0x96,0x58,0x27,0x82,0x96,0x50,0x02,0x03,0x18,0x21,
22550x02,0x02,0x10,0x21,0x90,0x64,0x00,0x00,0x90,0x45,0x00,0x05,0x0c,0x00,0x25,0xc4,
22560x00,0x00,0x38,0x21,0x08,0x00,0x22,0x94,0x00,0x00,0x00,0x00,0x27,0x82,0x96,0x58,
22570x02,0x02,0x10,0x21,0x94,0x43,0x00,0x02,0x8f,0xa2,0x00,0x54,0x00,0x03,0x19,0x02,
22580x00,0x62,0x18,0x23,0x30,0x63,0x0f,0xff,0x28,0x62,0x00,0x20,0x10,0x40,0x00,0x06,
22590x28,0x62,0x00,0x40,0x8f,0xa4,0x00,0x88,0x00,0x00,0x00,0x00,0x00,0x64,0x10,0x06,
22600x08,0x00,0x21,0x4c,0x30,0x44,0x00,0x01,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,
22610x8f,0xa5,0x00,0x8c,0x08,0x00,0x22,0xb4,0x00,0x65,0x10,0x06,0x08,0x00,0x21,0x4c,
22620x00,0x00,0x20,0x21,0x8f,0xa4,0x00,0x90,0x8f,0xa5,0x00,0x38,0x8f,0xa6,0x00,0x34,
22630xaf,0xa0,0x00,0x10,0x0c,0x00,0x0d,0xfe,0xaf,0xa2,0x00,0x14,0x30,0x42,0xff,0xff,
22640x08,0x00,0x21,0x1c,0xaf,0xa2,0x00,0x40,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
22650x27,0xbd,0xff,0xe0,0x34,0x42,0x00,0x20,0x24,0x63,0x8b,0x18,0xaf,0xb1,0x00,0x14,
22660xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x0a,
22670x00,0x80,0x80,0x21,0x14,0x40,0x00,0x45,0x00,0x00,0x88,0x21,0x92,0x02,0x00,0x04,
22680x00,0x00,0x00,0x00,0x14,0x40,0x00,0x3c,0x00,0x00,0x00,0x00,0x12,0x20,0x00,0x18,
22690x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x92,0x05,0x00,0x0a,0x30,0x42,0x00,0xfc,
22700x10,0xa0,0x00,0x03,0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,
22710x92,0x04,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x10,0x60,0x00,0x05,
22720x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,
22730xa2,0x02,0x00,0x16,0x10,0x60,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x08,
22740x00,0x00,0x00,0x00,0x96,0x02,0x00,0x00,0xa2,0x00,0x00,0x17,0xa6,0x02,0x00,0x14,
22750x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
22760x14,0x80,0x00,0x05,0x24,0x02,0x00,0x01,0x96,0x03,0x00,0x06,0xa2,0x02,0x00,0x17,
22770x08,0x00,0x22,0xf0,0xa6,0x03,0x00,0x14,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,
22780x27,0x86,0x96,0x40,0x00,0x04,0x10,0xc0,0x00,0x05,0x18,0xc0,0x00,0x44,0x10,0x21,
22790x00,0x65,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,
22800x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x0c,0x00,0x17,0x34,
22810x00,0x00,0x00,0x00,0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x04,0xa2,0x02,0x00,0x17,
22820x96,0x02,0x00,0x06,0x08,0x00,0x22,0xf0,0xa6,0x02,0x00,0x14,0x96,0x02,0x00,0x00,
22830x08,0x00,0x22,0xf0,0xa6,0x02,0x00,0x14,0x96,0x05,0x00,0x00,0x0c,0x00,0x23,0x1c,
22840x02,0x00,0x20,0x21,0x08,0x00,0x22,0xd7,0x02,0x22,0x88,0x21,0x94,0x85,0x00,0x06,
22850x0c,0x00,0x23,0x1c,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xd3,0x00,0x40,0x88,0x21,
22860x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x8c,0x70,
22870x27,0xbd,0xff,0xf0,0xac,0x62,0x00,0x00,0x00,0x00,0x10,0x21,0x03,0xe0,0x00,0x08,
22880x27,0xbd,0x00,0x10,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,
22890x24,0x42,0x8c,0x94,0xac,0x62,0x00,0x00,0x90,0x89,0x00,0x0a,0x00,0x80,0x30,0x21,
22900x11,0x20,0x00,0x05,0x00,0xa0,0x50,0x21,0x90,0x82,0x00,0x17,0x00,0x00,0x00,0x00,
22910x14,0x40,0x00,0x1b,0x00,0x00,0x00,0x00,0x90,0xc7,0x00,0x04,0x00,0x00,0x00,0x00,
22920x10,0xe0,0x00,0x1b,0x00,0x00,0x00,0x00,0x94,0xc8,0x00,0x00,0x27,0x83,0x96,0x40,
22930x93,0x85,0x91,0x50,0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x00,0x02,0x10,0x80,
22940x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08,0x00,0xe5,0x28,0x2b,0x10,0xa0,0x00,0x06,
22950x01,0x44,0x18,0x23,0x8f,0x82,0x91,0x68,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x2b,
22960x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x10,0xa4,0xc8,0x00,0x14,
22970x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x11,0x20,0x00,0x05,0x00,0x00,0x00,0x00,
22980x94,0xc2,0x00,0x06,0x24,0x03,0x00,0x08,0x08,0x00,0x23,0x48,0xa4,0xc2,0x00,0x14,
22990x08,0x00,0x23,0x48,0x00,0x00,0x18,0x21,0x27,0xbd,0xff,0xc8,0xaf,0xb5,0x00,0x2c,
23000xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x30,
23010xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0x94,0x91,0x00,0x06,0x00,0x80,0xa0,0x21,
23020x3c,0x02,0x80,0x01,0x3c,0x04,0xb0,0x03,0x00,0x11,0xa8,0xc0,0x34,0x84,0x00,0x20,
23030x24,0x42,0x8d,0x48,0x02,0xb1,0x48,0x21,0xac,0x82,0x00,0x00,0x00,0x09,0x48,0x80,
23040x24,0x03,0x00,0x01,0x27,0x82,0x96,0x50,0xa2,0x83,0x00,0x12,0x01,0x22,0x10,0x21,
23050x27,0x84,0x96,0x44,0x01,0x24,0x20,0x21,0x80,0x48,0x00,0x06,0x8c,0x8a,0x00,0x18,
23060x27,0x83,0x96,0x60,0x01,0x23,0x48,0x21,0x8d,0x24,0x00,0x00,0x25,0x08,0x00,0x02,
23070x8d,0x42,0x00,0x00,0x8d,0x49,0x00,0x04,0x00,0x08,0x17,0xc2,0x8d,0x43,0x00,0x08,
23080x01,0x02,0x40,0x21,0x00,0x04,0x25,0xc2,0x00,0x08,0x40,0x43,0x30,0x84,0x00,0x01,
23090x00,0x03,0x1f,0xc2,0x00,0x08,0x40,0x40,0x00,0xe0,0x80,0x21,0x00,0x64,0x18,0x24,
23100x00,0x09,0x49,0x42,0x01,0x48,0x10,0x21,0x00,0xa0,0x98,0x21,0x00,0xa0,0x20,0x21,
23110x00,0x40,0x38,0x21,0x02,0x00,0x28,0x21,0x14,0x60,0x00,0x19,0x31,0x29,0x00,0x01,
23120x94,0x42,0x00,0x00,0x02,0xb1,0x88,0x21,0x02,0x00,0x28,0x21,0x00,0x11,0x88,0x80,
23130x27,0x90,0x96,0x40,0x02,0x30,0x80,0x21,0x96,0x03,0x00,0x06,0x30,0x52,0xff,0xff,
23140x02,0x60,0x20,0x21,0x00,0x60,0x30,0x21,0xa6,0x83,0x00,0x1a,0x27,0x82,0x96,0x48,
23150x0c,0x00,0x0d,0xd7,0x02,0x22,0x88,0x21,0x00,0x52,0x10,0x21,0x96,0x03,0x00,0x06,
23160xa6,0x22,0x00,0x04,0x8f,0xbf,0x00,0x30,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,
23170x7b,0xb0,0x00,0xfc,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,
23180xaf,0xa9,0x00,0x10,0x0c,0x00,0x0d,0xfe,0xaf,0xa0,0x00,0x14,0x08,0x00,0x23,0x86,
23190x02,0xb1,0x88,0x21,0x27,0xbd,0xff,0xc0,0xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,
23200xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,
23210xaf,0xbf,0x00,0x3c,0xaf,0xb4,0x00,0x28,0xaf,0xb2,0x00,0x20,0xaf,0xb0,0x00,0x18,
23220x94,0x90,0x00,0x00,0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x20,0x00,0x10,0x10,0xc0,
23230x00,0x50,0x18,0x21,0x00,0x40,0x88,0x21,0x3c,0x02,0x80,0x01,0x00,0x03,0x48,0x80,
23240x24,0x42,0x8e,0x84,0x00,0x80,0x98,0x21,0x27,0x84,0x96,0x50,0x01,0x24,0x20,0x21,
23250x93,0xb7,0x00,0x53,0xad,0x02,0x00,0x00,0x80,0x83,0x00,0x06,0x27,0x82,0x96,0x44,
23260x01,0x22,0x10,0x21,0x8c,0x44,0x00,0x18,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,
23270x8c,0x88,0x00,0x08,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,
23280xaf,0xa7,0x00,0x4c,0x2c,0xa2,0x00,0x10,0x00,0xa0,0xa8,0x21,0x00,0x83,0x50,0x21,
23290x00,0x08,0x47,0xc2,0x00,0xc0,0x58,0x21,0x00,0x00,0xb0,0x21,0x8c,0x92,0x00,0x0c,
23300x14,0x40,0x00,0x13,0x00,0x00,0xf0,0x21,0x92,0x67,0x00,0x04,0x24,0x14,0x00,0x01,
23310x12,0x87,0x00,0x10,0x02,0x30,0x10,0x21,0x27,0x83,0x96,0x58,0x01,0x23,0x18,0x21,
23320x80,0x64,0x00,0x00,0x27,0x83,0xbb,0xb0,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,
23330x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
23340x90,0x44,0x00,0x04,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x23,0x00,0x00,0x00,0x00,
23350x02,0x30,0x10,0x21,0x00,0x02,0x80,0x80,0x24,0x04,0x00,0x01,0x27,0x83,0x96,0x60,
23360xa2,0x64,0x00,0x12,0x02,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
23370x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x14,0x40,0x00,0x0e,
23380x02,0xa0,0x20,0x21,0x27,0x82,0x96,0x40,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,
23390x00,0x00,0x00,0x00,0xa6,0x63,0x00,0x1a,0x94,0x42,0x00,0x06,0x7b,0xbe,0x01,0xfc,
23400x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,
23410x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x8f,0xa5,0x00,0x4c,0x01,0x60,0x30,0x21,
23420x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x0d,0xfe,0xaf,0xa0,0x00,0x14,
23430x08,0x00,0x23,0xed,0x00,0x00,0x00,0x00,0x27,0x83,0x96,0x60,0x01,0x23,0x18,0x21,
23440x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,
23450x01,0x02,0x10,0x24,0x14,0x40,0x00,0xaf,0x00,0xa0,0x20,0x21,0x32,0x4f,0x00,0x03,
23460x00,0x12,0x10,0x82,0x25,0xe3,0x00,0x0d,0x30,0x45,0x00,0x07,0x00,0x74,0x78,0x04,
23470x10,0xa0,0x00,0x0e,0x00,0x00,0x90,0x21,0x27,0x82,0x86,0xb0,0x00,0x15,0x18,0x40,
23480x00,0x62,0x18,0x21,0x94,0x64,0x00,0x00,0x24,0xa2,0x00,0x06,0x00,0x54,0x10,0x04,
23490x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,
23500x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,0x30,0x52,0xff,0xfc,0x02,0x30,0x10,0x21,
23510x27,0x83,0x96,0x50,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x03,
23520x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x04,
23530x2c,0x62,0x00,0x19,0x30,0x82,0x00,0x0f,0x24,0x43,0x00,0x0c,0x2c,0x62,0x00,0x19,
23540x10,0x40,0x00,0x19,0x24,0x0e,0x00,0x20,0x24,0x62,0xff,0xe9,0x2c,0x42,0x00,0x02,
23550x14,0x40,0x00,0x15,0x24,0x0e,0x00,0x08,0x24,0x62,0xff,0xeb,0x2c,0x42,0x00,0x02,
23560x14,0x40,0x00,0x11,0x24,0x0e,0x00,0x04,0x24,0x02,0x00,0x14,0x10,0x62,0x00,0x0e,
23570x24,0x0e,0x00,0x02,0x24,0x62,0xff,0xef,0x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,
23580x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xf1,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x06,
23590x24,0x0e,0x00,0x04,0x24,0x62,0xff,0xf3,0x2c,0x42,0x00,0x02,0x24,0x0e,0x00,0x02,
23600x24,0x03,0x00,0x01,0x00,0x62,0x70,0x0a,0x30,0xe2,0x00,0xff,0x00,0x00,0x48,0x21,
23610x00,0x00,0x68,0x21,0x10,0x40,0x00,0x6d,0x00,0x00,0x58,0x21,0x3c,0x14,0x80,0xff,
23620x27,0x99,0x96,0x40,0x01,0xf2,0xc0,0x23,0x36,0x94,0xff,0xff,0x01,0xc9,0x10,0x2a,
23630x14,0x40,0x00,0x64,0x24,0x03,0x00,0x04,0x00,0x10,0x28,0xc0,0x00,0xb0,0x10,0x21,
23640x00,0x02,0x10,0x80,0x00,0x59,0x10,0x21,0x94,0x56,0x00,0x06,0x00,0x00,0x00,0x00,
23650x32,0xcc,0x00,0x03,0x00,0x6c,0x10,0x23,0x30,0x42,0x00,0x03,0x02,0xc2,0x10,0x21,
23660x24,0x42,0x00,0x04,0x30,0x51,0xff,0xff,0x02,0x32,0x18,0x2b,0x10,0x60,0x00,0x4d,
23670x01,0xf1,0x10,0x23,0x02,0x51,0x10,0x23,0x01,0x78,0x18,0x2b,0x10,0x60,0x00,0x34,
23680x30,0x44,0xff,0xff,0x29,0x22,0x00,0x40,0x10,0x40,0x00,0x31,0x01,0x72,0x18,0x21,
23690x25,0x22,0x00,0x01,0x00,0x02,0x16,0x00,0x00,0x02,0x4e,0x03,0x00,0xb0,0x10,0x21,
23700x00,0x02,0x30,0x80,0x27,0x82,0x96,0x44,0x30,0x6b,0xff,0xff,0x00,0xc2,0x18,0x21,
23710x8c,0x67,0x00,0x18,0x00,0x04,0x25,0x40,0x3c,0x03,0x7f,0x00,0x8c,0xe2,0x00,0x04,
23720x00,0x83,0x20,0x24,0x27,0x83,0x96,0x50,0x00,0x54,0x10,0x24,0x00,0xc3,0x28,0x21,
23730x00,0x44,0x10,0x25,0xac,0xe2,0x00,0x04,0x16,0xe0,0x00,0x02,0xa0,0xb5,0x00,0x00,
23740xa0,0xb5,0x00,0x03,0x27,0x84,0x96,0x60,0x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x00,
23750x8c,0xe8,0x00,0x08,0x00,0x02,0x15,0xc2,0x00,0x08,0x47,0xc2,0x30,0x42,0x00,0x01,
23760x01,0x02,0x10,0x24,0x10,0x40,0x00,0x0a,0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x06,
23770x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,
23780x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0xe2,0x50,0x21,0xa5,0x5e,0x00,0x00,
23790x92,0x62,0x00,0x04,0x25,0xad,0x00,0x01,0x27,0x84,0x96,0x40,0x00,0xc4,0x18,0x21,
23800x01,0xa2,0x10,0x2a,0x94,0x70,0x00,0x02,0x14,0x40,0xff,0xb8,0x00,0x00,0x00,0x00,
23810x96,0x63,0x00,0x14,0x00,0x0c,0x10,0x23,0xa2,0x69,0x00,0x12,0x30,0x42,0x00,0x03,
23820x01,0x62,0x10,0x23,0x00,0x03,0x80,0xc0,0x8f,0xa5,0x00,0x4c,0x30,0x4b,0xff,0xff,
23830x02,0x03,0x80,0x21,0x27,0x82,0x96,0x48,0x00,0x10,0x80,0x80,0xa6,0x6b,0x00,0x1a,
23840x02,0xa0,0x20,0x21,0x01,0x60,0x30,0x21,0x01,0x60,0x88,0x21,0x0c,0x00,0x0d,0xd7,
23850x02,0x02,0x80,0x21,0x00,0x5e,0x10,0x21,0xa6,0x02,0x00,0x04,0x08,0x00,0x23,0xf3,
23860x02,0x20,0x10,0x21,0x01,0x62,0x10,0x2b,0x10,0x40,0xff,0xe9,0x00,0x00,0x20,0x21,
23870x29,0x22,0x00,0x40,0x10,0x40,0xff,0xe6,0x01,0x71,0x18,0x21,0x08,0x00,0x24,0x69,
23880x25,0x22,0x00,0x01,0x08,0x00,0x24,0x98,0x32,0xcc,0x00,0x03,0x08,0x00,0x24,0x98,
23890x00,0x00,0x60,0x21,0x8f,0xa5,0x00,0x4c,0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,
23900x0c,0x00,0x0d,0xfe,0xaf,0xb4,0x00,0x14,0x92,0x67,0x00,0x04,0x08,0x00,0x24,0x0b,
23910x30,0x5e,0xff,0xff,0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x20,0x21,
23920x00,0x04,0x20,0x80,0x27,0x82,0x96,0x40,0x3c,0x03,0xb0,0x08,0x30,0xa5,0xff,0xff,
23930x00,0x82,0x20,0x21,0x00,0xc3,0x30,0x21,0xac,0xc5,0x00,0x00,0x03,0xe0,0x00,0x08,
23940xa4,0x85,0x00,0x00,0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x30,0x21,
23950x27,0x88,0x96,0x40,0x00,0x06,0x30,0x80,0x00,0xc8,0x30,0x21,0x94,0xc3,0x00,0x04,
23960x3c,0x02,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x03,0x20,0xc0,0x00,0x83,0x18,0x21,
23970x00,0x03,0x18,0x80,0x00,0x82,0x20,0x21,0x3c,0x02,0x80,0x01,0x30,0xa5,0xff,0xff,
23980x00,0x68,0x18,0x21,0x34,0xe7,0x00,0x20,0x24,0x42,0x93,0x34,0xac,0xe2,0x00,0x00,
23990xa4,0xc5,0x00,0x02,0xa4,0x65,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x00,
24000x30,0x84,0xff,0xff,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x27,0x89,0x96,0x40,
24010x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,0x97,0x83,0x96,0x30,0x94,0x4a,0x00,0x04,
24020x3c,0x02,0xb0,0x08,0x00,0x03,0x38,0xc0,0x00,0x0a,0x40,0xc0,0x00,0xe3,0x18,0x21,
24030x01,0x0a,0x28,0x21,0x00,0xe2,0x38,0x21,0x01,0x02,0x40,0x21,0x00,0x03,0x18,0x80,
24040x00,0x05,0x28,0x80,0x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x01,0x00,0xa9,0x28,0x21,
24050x00,0x69,0x18,0x21,0x34,0xc6,0x00,0x20,0x34,0x09,0xff,0xff,0x24,0x42,0x93,0x90,
24060xac,0xc2,0x00,0x00,0xa4,0x64,0x00,0x00,0xac,0xe4,0x00,0x00,0xa4,0xa9,0x00,0x00,
24070xad,0x09,0x00,0x00,0xa7,0x8a,0x96,0x30,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
24080x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x94,0x10,
24090x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x01,0x10,0x8c,0x82,0x00,0x00,
24100x97,0x83,0x87,0xf4,0x30,0x42,0xff,0xff,0x10,0x62,0x00,0x16,0x24,0x0a,0x00,0x01,
24110xa7,0x82,0x87,0xf4,0xaf,0x80,0xba,0x90,0x00,0x40,0x28,0x21,0x24,0x06,0x00,0x01,
24120x27,0x84,0xba,0x94,0x25,0x43,0xff,0xff,0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,
24130x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x8c,0x83,0xff,0xfc,0x00,0x00,0x00,0x00,
24140x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,0x38,0x42,0x00,0x00,0x01,0x42,0x18,0x0a,
24150x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x14,0xac,0x83,0x00,0x00,0x14,0x40,0xff,0xf1,
24160x24,0x84,0x00,0x04,0x3c,0x0b,0xb0,0x03,0x00,0x00,0x50,0x21,0x3c,0x0c,0x80,0x00,
24170x27,0x89,0xba,0xe0,0x35,0x6b,0x01,0x20,0x8d,0x68,0x00,0x00,0x8d,0x23,0x00,0x04,
24180x01,0x0c,0x10,0x24,0x00,0x02,0x17,0xc2,0x11,0x03,0x00,0x37,0xa1,0x22,0x00,0xdc,
24190xa1,0x20,0x00,0xd5,0xa1,0x20,0x00,0xd6,0x01,0x20,0x30,0x21,0x00,0x00,0x38,0x21,
24200x00,0x00,0x28,0x21,0x01,0x20,0x20,0x21,0x00,0xa8,0x10,0x06,0x30,0x42,0x00,0x01,
24210x10,0xe0,0x00,0x10,0xa0,0x82,0x00,0x0a,0x90,0x82,0x00,0x07,0x00,0x00,0x00,0x00,
24220x10,0x40,0x00,0x31,0x24,0xa2,0xff,0xff,0xa0,0x82,0x00,0x08,0x90,0x82,0x00,0x0a,
24230x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x08,
24240x00,0x00,0x00,0x00,0x00,0x03,0x10,0x40,0x00,0x43,0x10,0x21,0x00,0x46,0x10,0x21,
24250xa0,0x45,0x00,0x09,0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x07,
24260x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x04,0x00,0x00,0x00,0x00,0xa0,0xc5,0x00,0xd5,
24270x24,0x07,0x00,0x01,0xa0,0x85,0x00,0x08,0xa0,0xc5,0x00,0xd6,0x24,0xa5,0x00,0x01,
24280x2c,0xa2,0x00,0x1c,0x14,0x40,0xff,0xe0,0x24,0x84,0x00,0x03,0x90,0xc4,0x00,0xd5,
24290x00,0x00,0x28,0x21,0x00,0xa4,0x10,0x2b,0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,
24300x00,0xc0,0x18,0x21,0xa0,0x64,0x00,0x08,0x90,0xc2,0x00,0xd5,0x24,0xa5,0x00,0x01,
24310xa0,0x62,0x00,0x09,0x90,0xc4,0x00,0xd5,0x00,0x00,0x00,0x00,0x00,0xa4,0x10,0x2b,
24320x14,0x40,0xff,0xf8,0x24,0x63,0x00,0x03,0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x08,
24330xad,0x28,0x00,0x04,0x25,0x6b,0x00,0x04,0x14,0x40,0xff,0xbf,0x25,0x29,0x00,0xec,
24340x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x05,0x08,0x00,0x25,0x3f,
24350xa0,0x82,0x00,0x08,0x97,0x84,0x91,0x5a,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,
24360x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0x95,0xc4,0xaf,0xbf,0x00,0x10,
24370xac,0x62,0x00,0x00,0x00,0x04,0x20,0x42,0x00,0x00,0x40,0x21,0x27,0x8f,0xba,0xe4,
24380x00,0x00,0x50,0x21,0x00,0x00,0x58,0x21,0x27,0x98,0xbb,0xc4,0x27,0x99,0xbb,0xc0,
24390x27,0x8e,0xbb,0xbe,0x27,0x8c,0xba,0xe8,0x27,0x8d,0xbb,0x40,0x27,0x89,0xbb,0xb8,
24400x00,0x0a,0x18,0x80,0x01,0x6f,0x10,0x21,0xac,0x40,0x00,0x00,0xac,0x44,0x00,0x58,
24410x00,0x6e,0x28,0x21,0x00,0x78,0x10,0x21,0xa1,0x20,0xff,0xfc,0xad,0x20,0x00,0x00,
24420xa1,0x20,0x00,0x04,0xa1,0x20,0x00,0x05,0xad,0x20,0xff,0xf8,0x00,0x79,0x18,0x21,
24430x24,0x06,0x00,0x01,0x24,0xc6,0xff,0xff,0xa0,0xa0,0x00,0x00,0xa4,0x60,0x00,0x00,
24440xac,0x40,0x00,0x00,0x24,0x63,0x00,0x02,0x24,0x42,0x00,0x04,0x04,0xc1,0xff,0xf9,
24450x24,0xa5,0x00,0x01,0x00,0x0a,0x10,0x80,0x00,0x4d,0x28,0x21,0x00,0x00,0x30,0x21,
24460x00,0x4c,0x18,0x21,0x27,0x87,0x87,0xf8,0x8c,0xe2,0x00,0x00,0x24,0xe7,0x00,0x04,
24470xac,0xa2,0x00,0x00,0xa0,0x66,0x00,0x00,0xa0,0x66,0x00,0x01,0x24,0xc6,0x00,0x01,
24480x28,0xc2,0x00,0x1c,0xa0,0x60,0x00,0x02,0x24,0xa5,0x00,0x04,0x14,0x40,0xff,0xf6,
24490x24,0x63,0x00,0x03,0x25,0x08,0x00,0x01,0x29,0x02,0x00,0x08,0x25,0x4a,0x00,0x3b,
24500x25,0x29,0x00,0xec,0x14,0x40,0xff,0xd6,0x25,0x6b,0x00,0xec,0xa7,0x80,0x87,0xf4,
24510x00,0x00,0x40,0x21,0x27,0x83,0xba,0x90,0xac,0x68,0x00,0x00,0x25,0x08,0x00,0x01,
24520x29,0x02,0x00,0x0c,0x14,0x40,0xff,0xfc,0x24,0x63,0x00,0x04,0x0c,0x00,0x25,0x04,
24530x00,0x00,0x00,0x00,0x27,0x83,0xba,0xe0,0x24,0x08,0x00,0x07,0x90,0x62,0x00,0xd6,
24540x25,0x08,0xff,0xff,0xa0,0x62,0x00,0x00,0x05,0x01,0xff,0xfc,0x24,0x63,0x00,0xec,
24550x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
24560x30,0x84,0x00,0xff,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,
24570x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xba,0xe0,0x00,0x43,0x40,0x21,
24580x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x84,0x00,0x20,0x24,0x42,0x97,0x10,
24590x30,0xc6,0x00,0xff,0xac,0x82,0x00,0x00,0x30,0xa5,0x00,0xff,0x30,0xe7,0x00,0xff,
24600x10,0xc0,0x00,0x41,0x25,0x0f,0x00,0xd0,0x91,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
24610x24,0x62,0xff,0xee,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x31,0x30,0x63,0x00,0xff,
24620x24,0x02,0x00,0x1a,0x10,0x62,0x00,0x2e,0x24,0x02,0x00,0x1b,0x10,0x62,0x00,0x2c,
24630x24,0x02,0x00,0x11,0x10,0x62,0x00,0x1e,0x24,0x02,0x00,0x18,0x10,0x62,0x00,0x1c,
24640x24,0x02,0x00,0x19,0x10,0x62,0x00,0x1a,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x06,
24650x24,0x02,0x00,0x01,0x8d,0x02,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,
24660x03,0xe0,0x00,0x08,0xad,0x02,0x00,0xd0,0x10,0xa2,0x00,0x0e,0x00,0x00,0x00,0x00,
24670x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x04,
24680x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,0x08,0x00,0x25,0xec,0x24,0x42,0xff,0xe0,
24690x8d,0x02,0x00,0xd0,0x08,0x00,0x25,0xec,0x24,0x42,0xff,0xf8,0x03,0xe0,0x00,0x08,
24700x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,0x08,0x00,0x25,0xec,0x24,0x42,0x00,0x01,
24710x10,0xa0,0xff,0xe8,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xfa,0x00,0x00,0x00,0x00,
24720x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xf5,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xed,
24730x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,0x08,0x00,0x25,0xec,0x24,0x42,0xff,0xe8,
24740x10,0xa0,0xff,0xf0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xeb,
24750x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe6,0x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,
24760x08,0x00,0x25,0xec,0x24,0x42,0xff,0xd0,0x91,0x06,0x00,0x00,0x91,0x03,0x00,0xd4,
24770x25,0x0d,0x00,0x5c,0x30,0xc4,0x00,0xff,0x00,0x04,0x10,0x40,0x00,0x44,0x10,0x21,
24780x00,0x04,0x50,0x80,0x01,0x02,0x58,0x21,0x01,0x0a,0x48,0x21,0x00,0xc0,0x60,0x21,
24790x25,0x78,0x00,0x08,0x10,0x60,0x00,0x36,0x25,0x2e,0x00,0x60,0x10,0xa0,0x00,0x25,
24800x00,0x00,0x00,0x00,0x91,0x02,0x00,0xdd,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1e,
24810x00,0x00,0x00,0x00,0x27,0x86,0x87,0xf8,0x01,0x46,0x10,0x21,0x8c,0x43,0x00,0x00,
24820x00,0x00,0x00,0x00,0xad,0x23,0x00,0x60,0x91,0x62,0x00,0x08,0x00,0x00,0x00,0x00,
24830x00,0x40,0x60,0x21,0xa1,0x02,0x00,0x00,0x31,0x82,0x00,0xff,0x00,0x02,0x10,0x80,
24840x00,0x46,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x18,0x42,
24850xad,0xa3,0x00,0x00,0x91,0x04,0x00,0x00,0x8d,0xc5,0x00,0x00,0x00,0x04,0x20,0x80,
24860x00,0x86,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x05,0x28,0x40,0x00,0x88,0x20,0x21,
24870x00,0x03,0x32,0x80,0x00,0xa6,0x10,0x2b,0x00,0xc2,0x28,0x0a,0xac,0x85,0x00,0x60,
24880x03,0xe0,0x00,0x08,0xa1,0x00,0x00,0xd4,0x27,0x86,0x87,0xf8,0x08,0x00,0x26,0x32,
24890xa1,0x00,0x00,0xdd,0x27,0x82,0x88,0x68,0x8d,0x03,0x00,0xd8,0x00,0x82,0x10,0x21,
24900x90,0x44,0x00,0x00,0x24,0x63,0x00,0x01,0x00,0x64,0x20,0x2b,0x14,0x80,0xff,0xab,
24910xad,0x03,0x00,0xd8,0x8d,0x22,0x00,0x60,0xa1,0x00,0x00,0xd4,0x00,0x02,0x1f,0xc2,
24920x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x03,0xe0,0x00,0x08,0xad,0x02,0x00,0x5c,
24930x10,0xe0,0x00,0x14,0x24,0xc2,0xff,0xee,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0xa4,
24940x24,0x02,0x00,0x1a,0x10,0x82,0x00,0xa2,0x24,0x02,0x00,0x1b,0x10,0x82,0x00,0xa0,
24950x24,0x02,0x00,0x11,0x10,0x82,0x00,0x92,0x24,0x02,0x00,0x18,0x10,0x82,0x00,0x90,
24960x24,0x02,0x00,0x19,0x10,0x82,0x00,0x8e,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x7c,
24970x24,0x02,0x00,0x01,0x8d,0x02,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,
24980xad,0x02,0x00,0xd0,0x8d,0xe3,0x00,0x00,0x8d,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,
24990x00,0x43,0x10,0x21,0xad,0xa2,0x00,0x00,0xad,0xe0,0x00,0x00,0x8d,0xa3,0x00,0x00,
25000x8d,0xc4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x10,0x2a,0x10,0x40,0x00,0x4d,
25010x24,0x02,0x00,0x1b,0x93,0x05,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x21,
25020x00,0x00,0x00,0x00,0x91,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x05,
25030x24,0x02,0x00,0x01,0xa1,0x05,0x00,0x00,0xa1,0x02,0x00,0xd4,0x03,0xe0,0x00,0x08,
25040xad,0x00,0x00,0xd8,0x91,0x02,0x00,0xdd,0x24,0x03,0x00,0x01,0x10,0x43,0x00,0x05,
25050x00,0x00,0x00,0x00,0xa1,0x03,0x00,0xd4,0xad,0x00,0x00,0xd8,0x03,0xe0,0x00,0x08,
25060xa1,0x03,0x00,0xdd,0x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43,
25070xad,0xa2,0x00,0x00,0x91,0x03,0x00,0x00,0x27,0x82,0x87,0xf8,0x8d,0xc5,0x00,0x00,
25080x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40,
25090x00,0x04,0x32,0x80,0x00,0xa6,0x10,0x2b,0x00,0xc2,0x28,0x0a,0x08,0x00,0x26,0x44,
25100xad,0xc5,0x00,0x00,0x91,0x02,0x00,0xde,0x00,0x00,0x00,0x00,0x2c,0x42,0x00,0x02,
25110x14,0x40,0xff,0xdc,0x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43,
25120xad,0xa2,0x00,0x00,0x91,0x03,0x00,0x00,0x27,0x82,0x87,0xf8,0x8d,0xc5,0x00,0x00,
25130x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40,
25140x3c,0x03,0xb0,0x03,0x00,0x04,0x32,0x80,0x00,0xa6,0x10,0x2b,0x00,0xc2,0x28,0x0a,
25150xad,0xc5,0x00,0x00,0x34,0x63,0x01,0x08,0x8c,0x64,0x00,0x00,0x8d,0x03,0x00,0xe4,
25160x00,0x00,0x00,0x00,0x00,0x64,0x10,0x2b,0x14,0x40,0x00,0x03,0x00,0x83,0x28,0x23,
25170x00,0x83,0x10,0x23,0x24,0x45,0xff,0xff,0x3c,0x02,0x00,0x98,0x34,0x42,0x96,0x80,
25180x00,0x45,0x10,0x2b,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0xa5,0x00,0x00,0xe0,
25190x03,0xe0,0x00,0x08,0xa1,0x00,0x00,0xde,0x24,0x02,0x00,0x03,0x03,0xe0,0x00,0x08,
25200xa1,0x02,0x00,0xde,0x97,0x82,0x91,0x5c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x2a,
25210x10,0x40,0xff,0x32,0x00,0x00,0x00,0x00,0x91,0x02,0x00,0xdd,0x00,0x00,0x00,0x00,
25220x14,0x40,0x00,0x15,0x00,0x00,0x00,0x00,0x91,0x03,0x00,0x00,0x27,0x82,0x87,0xf8,
25230x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x68,0x18,0x21,
25240xac,0x64,0x00,0x60,0x93,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x10,0x80,
25250x01,0x02,0x10,0x21,0x24,0x4e,0x00,0x60,0xa1,0x05,0x00,0x00,0x8d,0xc2,0x00,0x00,
25260x00,0x00,0x00,0x00,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,
25270x03,0xe0,0x00,0x08,0xad,0xa2,0x00,0x00,0x08,0x00,0x26,0xdb,0xa1,0x00,0x00,0xdd,
25280x10,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x85,
25290x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,
25300x08,0x00,0x26,0x6c,0x24,0x42,0xff,0xe0,0x8d,0x02,0x00,0xd0,0x08,0x00,0x26,0x6c,
25310x24,0x42,0xff,0xf8,0x8d,0x02,0x00,0xd0,0x08,0x00,0x26,0x6c,0x24,0x42,0x00,0x01,
25320x10,0xa0,0xff,0x74,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xfa,0x00,0x00,0x00,0x00,
25330x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x73,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xef,
25340x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,0x08,0x00,0x26,0x6c,0x24,0x42,0xff,0xe8,
25350x10,0xa0,0xff,0xf0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x69,
25360x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe8,0x00,0x00,0x00,0x00,0x8d,0x02,0x00,0xd0,
25370x08,0x00,0x26,0x6c,0x24,0x42,0xff,0xd0,0x27,0xbd,0xff,0xe8,0x3c,0x02,0xb0,0x03,
25380xaf,0xbf,0x00,0x14,0xaf,0xb0,0x00,0x10,0x34,0x42,0x01,0x18,0x8c,0x50,0x00,0x00,
25390x00,0x00,0x00,0x00,0x32,0x03,0x00,0x01,0x14,0x60,0x00,0x14,0x00,0x00,0x00,0x00,
25400x32,0x02,0x01,0x00,0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x32,0x02,0x08,0x00,
25410x10,0x40,0x00,0x02,0x24,0x02,0x00,0x01,0xa3,0x82,0x92,0x14,0x8f,0xbf,0x00,0x14,
25420x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x0a,0x65,
25430x00,0x00,0x00,0x00,0x26,0x02,0xff,0x00,0xa3,0x80,0x92,0x14,0x3c,0x01,0xb0,0x03,
25440xac,0x22,0x01,0x18,0x08,0x00,0x27,0x18,0x32,0x02,0x08,0x00,0x0c,0x00,0x25,0x71,
25450x00,0x00,0x00,0x00,0x26,0x02,0xff,0xff,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,
25460x08,0x00,0x27,0x15,0x32,0x02,0x01,0x00,0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,
25470x34,0x42,0x00,0xd0,0xaf,0xbf,0x00,0x18,0x8c,0x43,0x00,0x00,0x3c,0x02,0x00,0x40,
25480x24,0x07,0x0f,0xff,0x00,0x03,0x33,0x02,0x00,0x03,0x2d,0x02,0x00,0x03,0x43,0x02,
25490x30,0x69,0x0f,0xff,0x00,0x62,0x18,0x24,0x30,0xa5,0x00,0x03,0x30,0xc6,0x00,0xff,
25500x10,0x60,0x00,0x08,0x31,0x08,0x00,0xff,0x01,0x00,0x30,0x21,0x0c,0x00,0x27,0x4b,
25510xaf,0xa9,0x00,0x10,0x8f,0xbf,0x00,0x18,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
25520x27,0xbd,0x00,0x20,0x0c,0x00,0x27,0xae,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
25530x34,0x63,0x00,0xd4,0x08,0x00,0x27,0x41,0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xd8,
25540xaf,0xb0,0x00,0x10,0x30,0xd0,0x00,0xff,0x2e,0x02,0x00,0x2e,0xaf,0xb4,0x00,0x20,
25550xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x24,0xaf,0xb3,0x00,0x1c,
25560x30,0xb1,0x00,0xff,0x8f,0xb4,0x00,0x38,0x14,0x40,0x00,0x07,0x00,0x80,0x90,0x21,
25570x8f,0xbf,0x00,0x24,0x8f,0xb4,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,
25580x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10,0x24,0x05,0x00,0x14,
25590x0c,0x00,0x18,0xa0,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x46,0x02,0x40,0x20,0x21,
25600x02,0x00,0x90,0x21,0x00,0x14,0x1c,0x00,0x32,0x42,0x00,0x3f,0x24,0x04,0x00,0x50,
25610x0c,0x00,0x01,0x31,0x00,0x62,0x80,0x25,0x24,0x03,0x00,0x01,0x12,0x23,0x00,0x3a,
25620x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x34,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x2f,
25630x24,0x02,0x00,0x03,0x12,0x22,0x00,0x28,0x02,0x00,0x30,0x21,0x16,0x60,0xff,0xe4,
25640x00,0x00,0x00,0x00,0x16,0x40,0x00,0x1f,0x02,0x80,0x80,0x21,0x0c,0x00,0x01,0x31,
25650x24,0x04,0x00,0x50,0x24,0x03,0x00,0x01,0x12,0x23,0x00,0x16,0x2a,0x22,0x00,0x02,
25660x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,
25670x16,0x22,0xff,0xd7,0x32,0x06,0x0e,0xbf,0x00,0x06,0x34,0x00,0x24,0x04,0x08,0x4c,
25680x0c,0x00,0x18,0x5b,0x24,0x05,0xff,0xff,0x08,0x00,0x27,0x58,0x00,0x00,0x00,0x00,
25690x32,0x06,0x0e,0xbf,0x00,0x06,0x34,0x00,0x08,0x00,0x27,0x84,0x24,0x04,0x08,0x48,
25700x16,0x20,0xff,0xcb,0x32,0x06,0x0e,0xbf,0x00,0x06,0x34,0x00,0x08,0x00,0x27,0x84,
25710x24,0x04,0x08,0x40,0x32,0x06,0x0e,0xbf,0x00,0x06,0x34,0x00,0x08,0x00,0x27,0x84,
25720x24,0x04,0x08,0x44,0x02,0x20,0x20,0x21,0x0c,0x00,0x28,0x46,0x00,0x00,0x28,0x21,
25730x08,0x00,0x27,0x77,0x00,0x40,0x80,0x21,0x24,0x04,0x08,0x4c,0x0c,0x00,0x18,0x5b,
25740x24,0x05,0xff,0xff,0x08,0x00,0x27,0x73,0x00,0x00,0x00,0x00,0x02,0x00,0x30,0x21,
25750x08,0x00,0x27,0x9b,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xd0,0x02,0x00,0x30,0x21,
25760x08,0x00,0x27,0x9b,0x24,0x04,0x08,0x40,0x02,0x00,0x30,0x21,0x08,0x00,0x27,0x9b,
25770x24,0x04,0x08,0x44,0x02,0x00,0x30,0x21,0x0c,0x00,0x27,0xf5,0x02,0x20,0x28,0x21,
25780x08,0x00,0x27,0x65,0x00,0x40,0x90,0x21,0x27,0xbd,0xff,0xd8,0x2c,0xc2,0x00,0x2e,
25790xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,
25800xaf,0xb2,0x00,0x18,0x00,0xc0,0x80,0x21,0x30,0xb1,0x00,0xff,0x00,0x80,0x98,0x21,
25810x14,0x40,0x00,0x07,0x00,0x00,0x18,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,
25820x7b,0xb0,0x00,0xbc,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
25830x2e,0x12,0x00,0x10,0x24,0x05,0x00,0x14,0x0c,0x00,0x18,0xa0,0x24,0x06,0x01,0x07,
25840x12,0x40,0x00,0x2a,0x02,0x00,0x10,0x21,0x30,0x45,0x00,0x3f,0x0c,0x00,0x28,0x46,
25850x02,0x20,0x20,0x21,0x12,0x40,0x00,0x03,0x00,0x40,0x98,0x21,0x08,0x00,0x27,0xba,
25860x02,0x60,0x18,0x21,0x02,0x20,0x20,0x21,0x0c,0x00,0x28,0x46,0x00,0x00,0x28,0x21,
25870x24,0x04,0x00,0x50,0x0c,0x00,0x01,0x31,0x00,0x40,0x80,0x21,0x24,0x03,0x00,0x01,
25880x12,0x23,0x00,0x16,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02,
25890x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,0x16,0x22,0xff,0xf0,0x32,0x06,0x0e,0xbf,
25900x00,0x06,0x34,0x00,0x24,0x04,0x08,0x4c,0x0c,0x00,0x18,0x5b,0x24,0x05,0xff,0xff,
25910x08,0x00,0x27,0xba,0x02,0x60,0x18,0x21,0x32,0x06,0x0e,0xbf,0x00,0x06,0x34,0x00,
25920x08,0x00,0x27,0xde,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xe4,0x32,0x06,0x0e,0xbf,
25930x00,0x06,0x34,0x00,0x08,0x00,0x27,0xde,0x24,0x04,0x08,0x40,0x32,0x06,0x0e,0xbf,
25940x00,0x06,0x34,0x00,0x08,0x00,0x27,0xde,0x24,0x04,0x08,0x44,0x02,0x60,0x20,0x21,
25950x02,0x00,0x30,0x21,0x0c,0x00,0x27,0xf5,0x02,0x20,0x28,0x21,0x08,0x00,0x27,0xc7,
25960x30,0x45,0x00,0x3f,0x27,0xbd,0xff,0xe0,0xaf,0xb0,0x00,0x10,0x30,0xb0,0x00,0xff,
25970x02,0x00,0x20,0x21,0x00,0x00,0x28,0x21,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x1c,
25980x00,0xc0,0x88,0x21,0x0c,0x00,0x28,0x46,0xaf,0xb2,0x00,0x18,0x00,0x40,0x18,0x21,
25990x2e,0x22,0x00,0x1f,0x10,0x40,0x00,0x26,0x2e,0x22,0x00,0x10,0x10,0x40,0x00,0x07,
26000x34,0x62,0x01,0x00,0x02,0x20,0x10,0x21,0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,
26010x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x04,0x00,0x50,
26020x0c,0x00,0x01,0x31,0x00,0x02,0x94,0x00,0x24,0x03,0x00,0x01,0x12,0x03,0x00,0x15,
26030x2a,0x02,0x00,0x02,0x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x0a,
26040x24,0x02,0x00,0x03,0x12,0x02,0x00,0x03,0x02,0x40,0x30,0x21,0x08,0x00,0x28,0x05,
26050x26,0x31,0xff,0xf1,0x24,0x04,0x08,0x4c,0x0c,0x00,0x18,0x5b,0x24,0x05,0xff,0xff,
26060x08,0x00,0x28,0x05,0x26,0x31,0xff,0xf1,0x02,0x40,0x30,0x21,0x08,0x00,0x28,0x1a,
26070x24,0x04,0x08,0x48,0x16,0x00,0xff,0xf5,0x02,0x40,0x30,0x21,0x08,0x00,0x28,0x1a,
26080x24,0x04,0x08,0x40,0x02,0x40,0x30,0x21,0x08,0x00,0x28,0x1a,0x24,0x04,0x08,0x44,
26090x34,0x62,0x01,0x40,0x24,0x04,0x00,0x50,0x0c,0x00,0x01,0x31,0x00,0x02,0x94,0x00,
26100x24,0x03,0x00,0x01,0x12,0x03,0x00,0x15,0x2a,0x02,0x00,0x02,0x14,0x40,0x00,0x0f,
26110x24,0x02,0x00,0x02,0x12,0x02,0x00,0x0a,0x24,0x02,0x00,0x03,0x12,0x02,0x00,0x03,
26120x02,0x40,0x30,0x21,0x08,0x00,0x28,0x05,0x26,0x31,0xff,0xe2,0x24,0x04,0x08,0x4c,
26130x0c,0x00,0x18,0x5b,0x24,0x05,0xff,0xff,0x08,0x00,0x28,0x05,0x26,0x31,0xff,0xe2,
26140x02,0x40,0x30,0x21,0x08,0x00,0x28,0x38,0x24,0x04,0x08,0x48,0x16,0x00,0xff,0xf5,
26150x02,0x40,0x30,0x21,0x08,0x00,0x28,0x38,0x24,0x04,0x08,0x40,0x02,0x40,0x30,0x21,
26160x08,0x00,0x28,0x38,0x24,0x04,0x08,0x44,0x27,0xbd,0xff,0xe0,0x00,0x80,0x10,0x21,
26170x24,0x04,0x00,0x50,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,
26180x00,0xa0,0x88,0x21,0x0c,0x00,0x01,0x31,0x30,0x50,0x00,0xff,0x24,0x03,0x00,0x01,
26190x12,0x03,0x00,0x3e,0x02,0x20,0x30,0x21,0x2a,0x02,0x00,0x02,0x14,0x40,0x00,0x2a,
26200x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x12,0x02,0x00,0x19,0x24,0x04,0x08,0x34,
26210x24,0x02,0x00,0x03,0x12,0x02,0x00,0x05,0x24,0x04,0x08,0x3c,0x8f,0xbf,0x00,0x18,
26220x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x18,0x5b,
26230x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00,0x0c,0x00,0x18,0x5b,
26240x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01,0x0c,0x00,0x18,0x5b,
26250x24,0x04,0x08,0x3c,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28,0x24,0x04,0x08,0xac,
26260x0c,0x00,0x18,0x3d,0x24,0x05,0x0f,0xff,0x08,0x00,0x28,0x5b,0x00,0x00,0x00,0x00,
26270x0c,0x00,0x18,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00,
26280x0c,0x00,0x18,0x5b,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01,
26290x0c,0x00,0x18,0x5b,0x24,0x04,0x08,0x34,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28,
26300x08,0x00,0x28,0x6c,0x24,0x04,0x08,0xa8,0x16,0x00,0xff,0xdc,0x02,0x20,0x30,0x21,
26310x24,0x04,0x08,0x24,0x0c,0x00,0x18,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x24,
26320x3c,0x05,0x80,0x00,0x0c,0x00,0x18,0x5b,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,
26330x24,0x06,0x00,0x01,0x0c,0x00,0x18,0x5b,0x24,0x04,0x08,0x24,0x0c,0x00,0x01,0x31,
26340x24,0x04,0x00,0x28,0x08,0x00,0x28,0x6c,0x24,0x04,0x08,0xa0,0x24,0x04,0x08,0x2c,
26350x0c,0x00,0x18,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x2c,0x3c,0x05,0x80,0x00,
26360x0c,0x00,0x18,0x5b,0x00,0x00,0x30,0x21,0x3c,0x05,0x80,0x00,0x24,0x06,0x00,0x01,
26370x0c,0x00,0x18,0x5b,0x24,0x04,0x08,0x2c,0x0c,0x00,0x01,0x31,0x24,0x04,0x00,0x28,
26380x08,0x00,0x28,0x6c,0x24,0x04,0x08,0xa4,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
26390x0c,0x00,0x29,0x4c,0x00,0x00,0x00,0x00,0x0c,0x00,0x29,0x4e,0x00,0x00,0x00,0x00,
26400x0c,0x00,0x29,0x75,0x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x05,0x34,0x84,0x00,0x04,
26410x0c,0x00,0x29,0x55,0x34,0x05,0x9c,0x40,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
26420x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
26430x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,
26440x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x97,0x82,0x88,0x90,0x00,0x00,0x00,0x00,
26450x2c,0x43,0x00,0x64,0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x90,0x14,0x60,0x00,0x28,
26460x00,0x80,0x30,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0x20,0x00,0xa7,0x80,0x88,0x90,
26470x00,0x43,0x10,0x24,0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,
26480x3c,0x03,0x80,0x00,0x00,0x43,0x10,0x25,0x97,0x83,0x88,0x84,0xac,0x82,0x00,0x00,
26490x8c,0x85,0x00,0x00,0x24,0x63,0x00,0x01,0x3c,0x02,0x40,0x64,0x34,0x42,0x64,0x00,
26500x00,0x03,0x24,0x00,0x00,0xa2,0x28,0x25,0x00,0x04,0x24,0x03,0x24,0x02,0x00,0x64,
26510xac,0xc5,0x00,0x00,0xa7,0x83,0x88,0x84,0x10,0x82,0x00,0x2b,0x00,0x00,0x00,0x00,
26520x87,0x82,0x88,0x86,0x24,0x03,0x00,0x3c,0x10,0x43,0x00,0x21,0x00,0x00,0x00,0x00,
26530x87,0x82,0x88,0x88,0x00,0x00,0x00,0x00,0x10,0x43,0x00,0x17,0x00,0x00,0x00,0x00,
26540x87,0x83,0x88,0x8a,0x24,0x02,0x00,0x18,0x10,0x62,0x00,0x0d,0x00,0x00,0x00,0x00,
26550x87,0x83,0x88,0x8c,0x24,0x02,0x01,0x6d,0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,
26560x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x8e,0xa7,0x80,0x88,0x8c,
26570x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x8e,0x08,0x00,0x28,0xe4,0x00,0x00,0x00,0x00,
26580x97,0x82,0x88,0x8c,0xa7,0x80,0x88,0x8a,0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x8c,
26590x08,0x00,0x28,0xe0,0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x8a,0xa7,0x80,0x88,0x88,
26600x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x8a,0x08,0x00,0x28,0xdc,0x00,0x00,0x00,0x00,
26610x97,0x82,0x88,0x88,0xa7,0x80,0x88,0x86,0x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x88,
26620x08,0x00,0x28,0xd8,0x00,0x00,0x00,0x00,0x97,0x82,0x88,0x86,0xa7,0x80,0x88,0x84,
26630x24,0x42,0x00,0x01,0xa7,0x82,0x88,0x86,0x08,0x00,0x28,0xd4,0x00,0x00,0x00,0x00,
26640x00,0x04,0x24,0x00,0x3c,0x03,0xb0,0x07,0x00,0x04,0x24,0x03,0x34,0x63,0x00,0x28,
26650x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x40,0x10,0x40,0xff,0xfc,
26660x00,0x00,0x00,0x00,0x3c,0x01,0xb0,0x07,0xa0,0x24,0x00,0x00,0x03,0xe0,0x00,0x08,
26670x00,0x00,0x10,0x21,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x28,0x90,0x43,0x00,0x00,
26680x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x10,0x60,0x00,0x06,0x24,0x02,0xff,0xff,
26690x3c,0x02,0xb0,0x07,0x90,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x16,0x00,
26700x00,0x02,0x16,0x03,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe0,
26710xaf,0xb0,0x00,0x10,0x3c,0x10,0x04,0xc4,0x00,0x04,0x11,0x00,0x36,0x10,0xb4,0x00,
26720x02,0x02,0x00,0x1b,0xaf,0xb1,0x00,0x14,0x3c,0x11,0xb0,0x07,0x36,0x31,0x00,0x18,
26730x24,0x04,0x00,0x0a,0xaf,0xbf,0x00,0x18,0x14,0x40,0x00,0x02,0x00,0x00,0x00,0x00,
26740x00,0x07,0x00,0x0d,0x00,0x00,0x80,0x12,0x0c,0x00,0x29,0xa1,0x00,0x00,0x00,0x00,
26750x92,0x22,0x00,0x00,0x24,0x03,0xff,0x80,0x24,0x04,0x00,0x0a,0x00,0x43,0x10,0x25,
26760x0c,0x00,0x29,0xa1,0xa2,0x22,0x00,0x00,0x24,0x04,0x00,0x0a,0x3c,0x01,0xb0,0x07,
26770xa0,0x30,0x00,0x00,0x0c,0x00,0x29,0xa1,0x00,0x10,0x82,0x03,0x3c,0x02,0xb0,0x07,
26780x34,0x42,0x00,0x08,0xa0,0x50,0x00,0x00,0x0c,0x00,0x29,0xa1,0x24,0x04,0x00,0x0a,
26790x92,0x22,0x00,0x00,0x8f,0xbf,0x00,0x18,0x8f,0xb0,0x00,0x10,0x30,0x42,0x00,0x7f,
26800xa2,0x22,0x00,0x00,0x8f,0xb1,0x00,0x14,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
26810x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
26820x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x58,
26830x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x42,0x07,0xa4,0x03,0xe0,0x00,0x08,
26840xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xf8,0x00,0x80,0x38,0x21,0x00,0xa0,0x30,0x21,
26850x00,0x00,0x18,0x21,0x00,0x63,0x00,0x18,0x00,0x00,0x10,0x12,0x00,0xc2,0x10,0x2b,
26860x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x01,0x00,
26870x14,0x40,0xff,0xf9,0x00,0x63,0x00,0x18,0x24,0x63,0xff,0xff,0x00,0x63,0x00,0x18,
26880x30,0x63,0x00,0xff,0x8c,0xe4,0x00,0x00,0x00,0x03,0x2a,0x00,0x00,0x03,0x1c,0x00,
26890x00,0x00,0x10,0x12,0x00,0xc2,0x10,0x23,0x30,0x42,0x00,0xff,0x00,0x45,0x10,0x21,
26900x00,0x43,0x10,0x21,0x00,0x82,0x20,0x25,0xac,0xe4,0x00,0x00,0x8c,0xe2,0x00,0x00,
26910x3c,0x03,0x40,0x00,0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x00,0x03,0xe0,0x00,0x08,
26920x27,0xbd,0x00,0x08,0x27,0xbd,0xff,0xe0,0xaf,0xbf,0x00,0x18,0xaf,0xb1,0x00,0x14,
26930xaf,0xb0,0x00,0x10,0x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00,0x3c,0x06,0xb0,0x03,
26940x34,0xc6,0x00,0x08,0x34,0x42,0x40,0x00,0xac,0x82,0x00,0x00,0x8c,0x83,0x00,0x00,
26950x24,0x02,0xcf,0xff,0x3c,0x11,0xb0,0x07,0x00,0x62,0x18,0x24,0xac,0x83,0x00,0x00,
26960x8c,0xc5,0x00,0x00,0x3c,0x02,0x00,0xff,0x24,0x04,0x00,0x0a,0x00,0xa2,0x28,0x25,
26970xac,0xc5,0x00,0x00,0x0c,0x00,0x29,0xa1,0x36,0x31,0x00,0x18,0x24,0x02,0xff,0x83,
26980x3c,0x04,0x00,0x01,0xa2,0x22,0x00,0x00,0x0c,0x00,0x29,0x1f,0x34,0x84,0xc2,0x00,
26990x0c,0x00,0x29,0xa1,0x24,0x04,0x00,0x0a,0x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x00,
27000x24,0x04,0x00,0x0a,0x0c,0x00,0x29,0xa1,0x3c,0x10,0xb0,0x07,0x36,0x10,0x00,0x10,
27010x24,0x02,0x00,0x06,0xa2,0x02,0x00,0x00,0x0c,0x00,0x29,0xa1,0x24,0x04,0x00,0x0a,
27020xa2,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
27030x27,0xbd,0x00,0x20,0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,
27040x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
27050x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xb5,0x00,0x34,0xaf,0xb2,0x00,0x28,
27060xaf,0xb0,0x00,0x20,0xaf,0xbf,0x00,0x38,0xaf,0xb4,0x00,0x30,0xaf,0xb3,0x00,0x2c,
27070xaf,0xb1,0x00,0x24,0xaf,0xa5,0x00,0x44,0x90,0xa7,0x00,0x00,0x00,0x80,0xa8,0x21,
27080x00,0xc0,0x90,0x21,0x00,0x07,0x1e,0x00,0x10,0x60,0x00,0x0f,0x00,0x80,0x80,0x21,
27090x00,0x03,0x1e,0x03,0x24,0x02,0x00,0x25,0x10,0x62,0x00,0x13,0x00,0x00,0x88,0x21,
27100xa2,0x07,0x00,0x00,0x8f,0xa5,0x00,0x44,0x26,0x10,0x00,0x01,0x24,0xa5,0x00,0x01,
27110xaf,0xa5,0x00,0x44,0x90,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x1e,0x00,
27120x14,0x60,0xff,0xf3,0x00,0x00,0x00,0x00,0x02,0x15,0x10,0x23,0xa2,0x00,0x00,0x00,
27130x8f,0xbf,0x00,0x38,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,
27140x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x24,0xa5,0x00,0x01,0xaf,0xa5,0x00,0x44,
27150x80,0xa3,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x63,0xff,0xe0,0x2c,0x62,0x00,0x11,
27160x10,0x40,0x00,0x11,0x00,0xa0,0x38,0x21,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,
27170x24,0x63,0x09,0x98,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
27180x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x29,0xce,0x36,0x31,0x00,0x10,
27190x08,0x00,0x29,0xce,0x36,0x31,0x00,0x08,0x08,0x00,0x29,0xce,0x36,0x31,0x00,0x20,
27200x08,0x00,0x29,0xce,0x36,0x31,0x00,0x04,0x90,0xe4,0x00,0x00,0x3c,0x02,0x80,0x01,
27210x24,0x42,0x02,0x14,0x00,0x44,0x10,0x21,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
27220x30,0x63,0x00,0x04,0x14,0x60,0x00,0xfd,0x24,0x14,0xff,0xff,0x00,0x04,0x16,0x00,
27230x00,0x02,0x16,0x03,0x24,0x03,0x00,0x2a,0x10,0x43,0x00,0xee,0x26,0x42,0x00,0x03,
27240x80,0xa3,0x00,0x00,0x24,0x02,0x00,0x2e,0x10,0x62,0x00,0xcc,0x24,0x08,0xff,0xff,
27250x80,0xa3,0x00,0x00,0x24,0x02,0x00,0x68,0x10,0x62,0x00,0xc4,0x24,0x06,0xff,0xff,
27260x24,0x02,0x00,0x6c,0x10,0x62,0x00,0xc1,0x24,0x02,0x00,0x4c,0x10,0x62,0x00,0xbf,
27270x24,0x02,0x00,0x5a,0x10,0x62,0x00,0xbd,0x00,0x00,0x00,0x00,0x80,0xa3,0x00,0x00,
27280x00,0x00,0x00,0x00,0x24,0x63,0xff,0xdb,0x2c,0x62,0x00,0x54,0x10,0x40,0x00,0xaa,
27290x24,0x09,0x00,0x0a,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x09,0xdc,
27300x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,
27310x00,0x00,0x00,0x00,0x32,0x22,0x00,0x10,0x14,0x40,0x00,0x09,0x24,0x02,0xff,0xfc,
27320x26,0x94,0xff,0xff,0x1a,0x80,0x00,0x05,0x24,0x02,0x00,0x20,0x26,0x94,0xff,0xff,
27330xa2,0x02,0x00,0x00,0x1e,0x80,0xff,0xfd,0x26,0x10,0x00,0x01,0x24,0x02,0xff,0xfc,
27340x26,0x44,0x00,0x03,0x00,0x82,0x90,0x24,0x92,0x42,0x00,0x03,0x26,0x94,0xff,0xff,
27350x26,0x52,0x00,0x04,0xa2,0x02,0x00,0x00,0x1a,0x80,0x00,0x06,0x26,0x10,0x00,0x01,
27360x24,0x02,0x00,0x20,0x26,0x94,0xff,0xff,0xa2,0x02,0x00,0x00,0x1e,0x80,0xff,0xfd,
27370x26,0x10,0x00,0x01,0x8f,0xa5,0x00,0x44,0x08,0x00,0x29,0xc0,0x24,0xa5,0x00,0x01,
27380x24,0x02,0x00,0x25,0x08,0x00,0x29,0xbd,0xa2,0x02,0x00,0x00,0x36,0x31,0x00,0x40,
27390x24,0x09,0x00,0x10,0x24,0x02,0x00,0x4c,0x10,0xc2,0x00,0x2a,0x24,0x02,0x00,0x6c,
27400x10,0xc2,0x00,0x05,0x24,0x02,0x00,0x5a,0x10,0xc2,0x00,0x1f,0x24,0x02,0x00,0x68,
27410x10,0xc2,0x00,0x13,0x24,0x02,0xff,0xfc,0x24,0x02,0xff,0xfc,0x26,0x43,0x00,0x03,
27420x00,0x62,0x90,0x24,0x32,0x22,0x00,0x02,0x8e,0x47,0x00,0x00,0x00,0x00,0x30,0x21,
27430x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04,0x00,0xe0,0x10,0x21,0x00,0x02,0x37,0xc3,
27440x02,0x00,0x20,0x21,0xaf,0xa9,0x00,0x10,0xaf,0xb4,0x00,0x14,0xaf,0xa8,0x00,0x18,
27450x0c,0x00,0x2b,0x0e,0xaf,0xb1,0x00,0x1c,0x08,0x00,0x2a,0x29,0x00,0x40,0x80,0x21,
27460x26,0x43,0x00,0x03,0x00,0x62,0x90,0x24,0x32,0x22,0x00,0x02,0x96,0x47,0x00,0x02,
27470x00,0x00,0x30,0x21,0x10,0x40,0xff,0xf2,0x26,0x52,0x00,0x04,0x00,0x07,0x14,0x00,
27480x08,0x00,0x2a,0x43,0x00,0x02,0x3c,0x03,0x26,0x42,0x00,0x03,0x24,0x03,0xff,0xfc,
27490x00,0x43,0x90,0x24,0x8e,0x47,0x00,0x00,0x00,0x00,0x30,0x21,0x08,0x00,0x2a,0x44,
27500x26,0x52,0x00,0x04,0x26,0x42,0x00,0x07,0x24,0x03,0xff,0xf8,0x00,0x43,0x90,0x24,
27510x8e,0x46,0x00,0x00,0x8e,0x47,0x00,0x04,0x08,0x00,0x2a,0x44,0x26,0x52,0x00,0x08,
27520x08,0x00,0x2a,0x31,0x36,0x31,0x00,0x02,0x26,0x44,0x00,0x03,0x24,0x02,0xff,0xfc,
27530x00,0x82,0x90,0x24,0x8e,0x44,0x00,0x00,0x02,0x15,0x10,0x23,0x26,0x52,0x00,0x04,
27540x08,0x00,0x29,0xbf,0xac,0x82,0x00,0x00,0x08,0x00,0x2a,0x31,0x24,0x09,0x00,0x08,
27550x24,0x02,0xff,0xff,0x12,0x82,0x00,0x11,0x00,0x00,0x00,0x00,0x26,0x43,0x00,0x03,
27560x24,0x02,0xff,0xfc,0x00,0x62,0x90,0x24,0x8e,0x47,0x00,0x00,0x02,0x00,0x20,0x21,
27570x24,0x02,0x00,0x10,0x00,0x00,0x30,0x21,0xaf,0xa2,0x00,0x10,0xaf,0xb4,0x00,0x14,
27580xaf,0xa8,0x00,0x18,0x0c,0x00,0x2b,0x0e,0xaf,0xb1,0x00,0x1c,0x8f,0xa5,0x00,0x44,
27590x00,0x40,0x80,0x21,0x08,0x00,0x29,0xbf,0x26,0x52,0x00,0x04,0x24,0x14,0x00,0x08,
27600x08,0x00,0x2a,0x73,0x36,0x31,0x00,0x01,0x26,0x42,0x00,0x03,0x24,0x03,0xff,0xfc,
27610x00,0x43,0x90,0x24,0x8e,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x60,0x00,0x23,
27620x26,0x52,0x00,0x04,0x02,0x60,0x20,0x21,0x0c,0x00,0x2b,0xdc,0x01,0x00,0x28,0x21,
27630x00,0x40,0x20,0x21,0x32,0x22,0x00,0x10,0x14,0x40,0x00,0x09,0x00,0x94,0x10,0x2a,
27640x10,0x40,0x00,0x07,0x26,0x94,0xff,0xff,0x24,0x03,0x00,0x20,0x00,0x94,0x10,0x2a,
27650xa2,0x03,0x00,0x00,0x26,0x94,0xff,0xff,0x14,0x40,0xff,0xfc,0x26,0x10,0x00,0x01,
27660x18,0x80,0x00,0x07,0x00,0x80,0x18,0x21,0x92,0x62,0x00,0x00,0x24,0x63,0xff,0xff,
27670x26,0x73,0x00,0x01,0xa2,0x02,0x00,0x00,0x14,0x60,0xff,0xfb,0x26,0x10,0x00,0x01,
27680x00,0x94,0x10,0x2a,0x10,0x40,0xff,0x83,0x26,0x94,0xff,0xff,0x24,0x03,0x00,0x20,
27690x00,0x94,0x10,0x2a,0xa2,0x03,0x00,0x00,0x26,0x94,0xff,0xff,0x14,0x40,0xff,0xfc,
27700x26,0x10,0x00,0x01,0x08,0x00,0x2a,0x29,0x00,0x00,0x00,0x00,0x3c,0x02,0x80,0x01,
27710x08,0x00,0x2a,0x8d,0x24,0x53,0x08,0x84,0x24,0x02,0x00,0x25,0xa2,0x02,0x00,0x00,
27720x8f,0xa5,0x00,0x44,0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x00,0x90,0xa3,0x00,0x00,
27730x10,0x40,0x00,0x03,0x26,0x10,0x00,0x01,0x08,0x00,0x29,0xbd,0xa2,0x03,0x00,0x00,
27740x24,0xa5,0xff,0xff,0x08,0x00,0x29,0xbf,0xaf,0xa5,0x00,0x44,0x80,0xa6,0x00,0x00,
27750x24,0xa5,0x00,0x01,0x08,0x00,0x2a,0x03,0xaf,0xa5,0x00,0x44,0x24,0xa5,0x00,0x01,
27760xaf,0xa5,0x00,0x44,0x90,0xa4,0x00,0x00,0x3c,0x02,0x80,0x01,0x24,0x42,0x02,0x14,
27770x00,0x44,0x10,0x21,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04,
27780x14,0x60,0x00,0x0f,0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03,0x24,0x03,0x00,0x2a,
27790x10,0x43,0x00,0x04,0x26,0x42,0x00,0x03,0x29,0x02,0x00,0x00,0x08,0x00,0x29,0xf8,
27800x00,0x02,0x40,0x0b,0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24,0x24,0xa5,0x00,0x01,
27810x8e,0x48,0x00,0x00,0xaf,0xa5,0x00,0x44,0x08,0x00,0x2a,0xd2,0x26,0x52,0x00,0x04,
27820x0c,0x00,0x2a,0xf2,0x27,0xa4,0x00,0x44,0x8f,0xa5,0x00,0x44,0x08,0x00,0x2a,0xd2,
27830x00,0x40,0x40,0x21,0x24,0x03,0xff,0xfc,0x00,0x43,0x90,0x24,0x8e,0x54,0x00,0x00,
27840x24,0xe5,0x00,0x01,0xaf,0xa5,0x00,0x44,0x06,0x81,0xff,0x0d,0x26,0x52,0x00,0x04,
27850x00,0x14,0xa0,0x23,0x08,0x00,0x29,0xf4,0x36,0x31,0x00,0x10,0x0c,0x00,0x2a,0xf2,
27860x27,0xa4,0x00,0x44,0x8f,0xa5,0x00,0x44,0x08,0x00,0x29,0xf4,0x00,0x40,0xa0,0x21,
27870x08,0x00,0x29,0xce,0x36,0x31,0x00,0x01,0x8c,0x86,0x00,0x00,0x3c,0x02,0x80,0x01,
27880x00,0x80,0x48,0x21,0x90,0xc3,0x00,0x00,0x24,0x44,0x02,0x14,0x00,0x64,0x18,0x21,
27890x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x04,0x10,0x40,0x00,0x10,
27900x00,0x00,0x38,0x21,0x00,0x80,0x40,0x21,0x24,0xc2,0x00,0x01,0x80,0xc5,0x00,0x00,
27910xad,0x22,0x00,0x00,0x90,0x43,0x00,0x00,0x00,0x40,0x30,0x21,0x00,0x07,0x10,0x80,
27920x00,0x68,0x18,0x21,0x90,0x64,0x00,0x00,0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x40,
27930x00,0x45,0x10,0x21,0x30,0x84,0x00,0x04,0x14,0x80,0xff,0xf3,0x24,0x47,0xff,0xd0,
27940x03,0xe0,0x00,0x08,0x00,0xe0,0x10,0x21,0x27,0xbd,0xff,0x98,0xaf,0xb2,0x00,0x50,
27950x8f,0xb2,0x00,0x84,0x3c,0x02,0x80,0x01,0xaf,0xb4,0x00,0x58,0x32,0x43,0x00,0x40,
27960xaf,0xb1,0x00,0x4c,0xaf,0xb0,0x00,0x48,0xaf,0xb7,0x00,0x64,0xaf,0xb6,0x00,0x60,
27970xaf,0xb5,0x00,0x5c,0xaf,0xb3,0x00,0x54,0x00,0x80,0x68,0x21,0x00,0xc0,0x70,0x21,
27980x00,0xe0,0x78,0x21,0x8f,0xb0,0x00,0x78,0x8f,0xb8,0x00,0x7c,0x8f,0xb1,0x00,0x80,
27990x10,0x60,0x00,0x03,0x24,0x54,0x08,0x8c,0x3c,0x02,0x80,0x01,0x24,0x54,0x08,0xb4,
28000x32,0x42,0x00,0x10,0x10,0x40,0x00,0x04,0x26,0x02,0xff,0xfe,0x24,0x02,0xff,0xfe,
28010x02,0x42,0x90,0x24,0x26,0x02,0xff,0xfe,0x2c,0x42,0x00,0x23,0x10,0x40,0x00,0x5d,
28020x00,0x00,0x18,0x21,0x32,0x42,0x00,0x01,0x24,0x15,0x00,0x30,0x24,0x03,0x00,0x20,
28030x32,0x44,0x00,0x02,0x00,0x62,0xa8,0x0a,0x10,0x80,0x00,0x07,0x00,0x00,0xb8,0x21,
28040x05,0xc0,0x00,0x96,0x32,0x42,0x00,0x04,0x10,0x40,0x00,0x90,0x32,0x42,0x00,0x08,
28050x24,0x17,0x00,0x2b,0x27,0x18,0xff,0xff,0x32,0x56,0x00,0x20,0x12,0xc0,0x00,0x07,
28060x01,0xcf,0x10,0x25,0x24,0x02,0x00,0x10,0x12,0x02,0x00,0x86,0x27,0x03,0xff,0xff,
28070x3a,0x02,0x00,0x08,0x00,0x62,0xc0,0x0a,0x01,0xcf,0x10,0x25,0x14,0x40,0x00,0x55,
28080x00,0x00,0xc8,0x21,0x24,0x02,0x00,0x30,0x24,0x19,0x00,0x01,0xa3,0xa2,0x00,0x00,
28090x02,0x39,0x10,0x2a,0x03,0x22,0x88,0x0b,0x32,0x43,0x00,0x11,0x14,0x60,0x00,0x0a,
28100x03,0x11,0xc0,0x23,0x03,0x00,0x10,0x21,0x18,0x40,0x00,0x07,0x27,0x18,0xff,0xff,
28110x24,0x03,0x00,0x20,0x03,0x00,0x10,0x21,0xa1,0xa3,0x00,0x00,0x27,0x18,0xff,0xff,
28120x1c,0x40,0xff,0xfc,0x25,0xad,0x00,0x01,0x12,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,
28130xa1,0xb7,0x00,0x00,0x25,0xad,0x00,0x01,0x12,0xc0,0x00,0x07,0x32,0x42,0x00,0x10,
28140x24,0x02,0x00,0x08,0x12,0x02,0x00,0x38,0x24,0x02,0x00,0x10,0x12,0x02,0x00,0x30,
28150x24,0x02,0x00,0x30,0x32,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,0x03,0x31,0x10,0x2a,
28160x03,0x00,0x10,0x21,0x18,0x40,0x00,0x06,0x27,0x18,0xff,0xff,0x03,0x00,0x10,0x21,
28170xa1,0xb5,0x00,0x00,0x27,0x18,0xff,0xff,0x1c,0x40,0xff,0xfc,0x25,0xad,0x00,0x01,
28180x03,0x31,0x10,0x2a,0x10,0x40,0x00,0x07,0x26,0x31,0xff,0xff,0x24,0x03,0x00,0x30,
28190x03,0x31,0x10,0x2a,0xa1,0xa3,0x00,0x00,0x26,0x31,0xff,0xff,0x14,0x40,0xff,0xfc,
28200x25,0xad,0x00,0x01,0x03,0x20,0x10,0x21,0x18,0x40,0x00,0x08,0x27,0x39,0xff,0xff,
28210x03,0xb9,0x10,0x21,0x90,0x43,0x00,0x00,0x03,0x20,0x20,0x21,0x27,0x39,0xff,0xff,
28220xa1,0xa3,0x00,0x00,0x1c,0x80,0xff,0xfa,0x25,0xad,0x00,0x01,0x03,0x00,0x10,0x21,
28230x18,0x40,0x00,0x07,0x27,0x18,0xff,0xff,0x24,0x03,0x00,0x20,0x03,0x00,0x10,0x21,
28240xa1,0xa3,0x00,0x00,0x27,0x18,0xff,0xff,0x1c,0x40,0xff,0xfc,0x25,0xad,0x00,0x01,
28250x01,0xa0,0x18,0x21,0x7b,0xb6,0x03,0x3c,0x7b,0xb4,0x02,0xfc,0x7b,0xb2,0x02,0xbc,
28260x7b,0xb0,0x02,0x7c,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x68,
28270xa1,0xa2,0x00,0x00,0x92,0x83,0x00,0x21,0x25,0xad,0x00,0x01,0xa1,0xa3,0x00,0x00,
28280x08,0x00,0x2b,0x61,0x25,0xad,0x00,0x01,0x24,0x02,0x00,0x30,0x08,0x00,0x2b,0x94,
28290xa1,0xa2,0x00,0x00,0x01,0xcf,0x10,0x25,0x10,0x40,0xff,0xad,0x00,0x00,0x60,0x21,
28300x00,0x0e,0x18,0x02,0x03,0x3d,0x98,0x21,0x00,0x60,0x20,0x21,0x01,0xe0,0x38,0x21,
28310x10,0x60,0x00,0x04,0x27,0x39,0x00,0x01,0x00,0x70,0x00,0x1b,0x00,0x00,0x20,0x12,
28320x00,0x00,0x18,0x10,0x00,0x80,0x48,0x21,0x00,0xe0,0x30,0x21,0x01,0x80,0x70,0x21,
28330x01,0x80,0x28,0x21,0x10,0x00,0x00,0x06,0x24,0x04,0x00,0x21,0x00,0x03,0x08,0x40,
28340x00,0x03,0x2f,0xc2,0x00,0x22,0x18,0x25,0x00,0x06,0x30,0x40,0x00,0x0e,0x70,0x40,
28350x14,0xa0,0x00,0x02,0x00,0x70,0x10,0x2b,0x14,0x40,0x00,0x03,0x24,0x84,0xff,0xff,
28360x00,0x70,0x18,0x23,0x25,0xce,0x00,0x01,0x14,0x80,0xff,0xf4,0x00,0x06,0x17,0xc2,
28370x02,0x83,0x18,0x21,0x01,0xc0,0x38,0x21,0x00,0x00,0x50,0x21,0x00,0x09,0x20,0x00,
28380x00,0x00,0x28,0x21,0x90,0x66,0x00,0x00,0x00,0x8a,0x70,0x25,0x00,0xa7,0x78,0x25,
28390x01,0xcf,0x10,0x25,0x14,0x40,0xff,0xda,0xa2,0x66,0x00,0x00,0x08,0x00,0x2b,0x49,
28400x02,0x39,0x10,0x2a,0x08,0x00,0x2b,0x42,0x27,0x18,0xff,0xfe,0x10,0x40,0xff,0x73,
28410x32,0x56,0x00,0x20,0x08,0x00,0x2b,0x39,0x24,0x17,0x00,0x20,0x00,0x0f,0x78,0x23,
28420x00,0x0e,0x70,0x23,0x00,0x0f,0x10,0x2b,0x01,0xc2,0x70,0x23,0x08,0x00,0x2b,0x39,
28430x24,0x17,0x00,0x2d,0x80,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x06,
28440x00,0x80,0x18,0x21,0x24,0x63,0x00,0x01,0x80,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
28450x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x64,0x10,0x23,
28460x24,0xa5,0xff,0xff,0x24,0x02,0xff,0xff,0x10,0xa2,0x00,0x0d,0x00,0x80,0x18,0x21,
28470x80,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09,0x00,0x00,0x00,0x00,
28480x24,0x06,0xff,0xff,0x24,0xa5,0xff,0xff,0x10,0xa6,0x00,0x05,0x24,0x63,0x00,0x01,
28490x80,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,
28500x03,0xe0,0x00,0x08,0x00,0x64,0x10,0x23,0x80,0x82,0x00,0x00,0x90,0x88,0x00,0x00,
28510x10,0x40,0x00,0x17,0x00,0x00,0x48,0x21,0x90,0xa3,0x00,0x00,0x00,0xa0,0x30,0x21,
28520x10,0x60,0x00,0x0b,0x00,0x60,0x38,0x21,0x00,0x08,0x16,0x00,0x00,0x02,0x46,0x03,
28530x00,0x07,0x16,0x00,0x00,0x02,0x16,0x03,0x11,0x02,0x00,0x05,0x24,0xc6,0x00,0x01,
28540x90,0xc3,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0xf9,0x00,0x60,0x38,0x21,
28550x00,0x03,0x16,0x00,0x10,0x40,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x84,0x00,0x01,
28560x90,0x82,0x00,0x00,0x25,0x29,0x00,0x01,0x14,0x40,0xff,0xeb,0x00,0x40,0x40,0x21,
28570x03,0xe0,0x00,0x08,0x01,0x20,0x10,0x21,0x80,0x82,0x00,0x00,0x90,0x87,0x00,0x00,
28580x10,0x40,0x00,0x17,0x00,0x00,0x18,0x21,0x90,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,
28590x00,0x02,0x1e,0x00,0x10,0x60,0x00,0x0c,0x00,0xa0,0x30,0x21,0x00,0x07,0x16,0x00,
28600x00,0x02,0x3e,0x03,0x00,0x03,0x16,0x03,0x10,0xe2,0x00,0x0d,0x00,0x80,0x18,0x21,
28610x24,0xc6,0x00,0x01,0x90,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,
28620x14,0x60,0xff,0xf9,0x00,0x03,0x16,0x03,0x24,0x84,0x00,0x01,0x90,0x82,0x00,0x00,
28630x00,0x00,0x00,0x00,0x14,0x40,0xff,0xec,0x00,0x40,0x38,0x21,0x00,0x00,0x18,0x21,
28640x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xe0,0xaf,0xb0,0x00,0x10,
28650x8f,0x90,0xc2,0x58,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0x00,0x84,0x80,0x0b,
28660x00,0x00,0x30,0x21,0x12,0x00,0x00,0x0a,0x00,0xa0,0x88,0x21,0x0c,0x00,0x2b,0xee,
28670x02,0x00,0x20,0x21,0x02,0x02,0x80,0x21,0x82,0x02,0x00,0x00,0x02,0x20,0x28,0x21,
28680x02,0x00,0x20,0x21,0x14,0x40,0x00,0x07,0x00,0x00,0x30,0x21,0xaf,0x80,0xc2,0x58,
28690x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08,
28700x27,0xbd,0x00,0x20,0x0c,0x00,0x2c,0x0a,0x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,
28710x10,0x40,0x00,0x07,0x02,0x00,0x30,0x21,0x80,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
28720x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0xa0,0x60,0x00,0x00,0x24,0x63,0x00,0x01,
28730xaf,0x83,0xc2,0x58,0x08,0x00,0x2c,0x38,0x00,0x00,0x00,0x00,0x24,0xc6,0xff,0xff,
28740x24,0x02,0xff,0xff,0x10,0xc2,0x00,0x05,0x00,0x80,0x18,0x21,0x24,0xc6,0xff,0xff,
28750xa0,0x65,0x00,0x00,0x14,0xc2,0xff,0xfd,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,
28760x00,0x80,0x10,0x21,0x24,0xc6,0xff,0xff,0x24,0x02,0xff,0xff,0x10,0xc2,0x00,0x08,
28770x00,0x80,0x18,0x21,0x24,0x07,0xff,0xff,0x90,0xa2,0x00,0x00,0x24,0xc6,0xff,0xff,
28780x24,0xa5,0x00,0x01,0xa0,0x62,0x00,0x00,0x14,0xc7,0xff,0xfb,0x24,0x63,0x00,0x01,
28790x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x00,0x80,0x18,0x21,0x90,0xa2,0x00,0x00,
28800x24,0xa5,0x00,0x01,0xa0,0x82,0x00,0x00,0x14,0x40,0xff,0xfc,0x24,0x84,0x00,0x01,
28810x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x90,0x83,0x00,0x00,0x90,0xa2,0x00,0x00,
28820x24,0x84,0x00,0x01,0x00,0x62,0x10,0x23,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
28830x14,0x40,0x00,0x03,0x24,0xa5,0x00,0x01,0x14,0x60,0xff,0xf7,0x00,0x00,0x00,0x00,
28840x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,
28850x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0xa5,0x00,0x20,0x24,0x42,0xb1,0xe0,
28860xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x20,0xac,0x82,0x00,0x64,
28870x3c,0x02,0x80,0x01,0xac,0x83,0x00,0x60,0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,
28880xac,0x80,0x00,0x08,0xac,0x80,0x00,0x4c,0xac,0x80,0x00,0x50,0xac,0x80,0x00,0x54,
28890xac,0x80,0x00,0x0c,0xac,0x80,0x00,0x58,0xa0,0x80,0x00,0x5c,0x24,0x42,0xb2,0xb0,
28900x24,0x83,0x00,0x68,0x24,0x05,0x00,0x0f,0x24,0xa5,0xff,0xff,0xac,0x62,0x00,0x00,
28910x04,0xa1,0xff,0xfd,0x24,0x63,0x00,0x04,0x3c,0x02,0x80,0x01,0x3c,0x03,0x80,0x01,
28920x24,0x42,0xb3,0xe0,0x24,0x63,0xb4,0x44,0xac,0x82,0x00,0x78,0xac,0x83,0x00,0x84,
28930x3c,0x02,0x80,0x01,0x3c,0x03,0x80,0x01,0x24,0x42,0xb5,0x6c,0x24,0x63,0xb4,0xd8,
28940xac,0x82,0x00,0x88,0xac,0x83,0x00,0x98,0x3c,0x02,0x80,0x01,0x3c,0x03,0x80,0x01,
28950x24,0x42,0xb6,0x14,0x24,0x63,0xb6,0xd4,0xac,0x82,0x00,0xa0,0xac,0x83,0x00,0xa4,
28960xa0,0x80,0x01,0xba,0xac,0x80,0x01,0xa8,0xac,0x80,0x01,0xac,0xac,0x80,0x01,0xb0,
28970xac,0x80,0x01,0xb4,0xa0,0x80,0x01,0xb8,0x03,0xe0,0x00,0x08,0xa0,0x80,0x01,0xb9,
28980x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0xb2,0xb0,
28990x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,
29000x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0xb2,0xc8,0xaf,0xb0,0x00,0x10,
29010xac,0x62,0x00,0x00,0xaf,0xbf,0x00,0x14,0x8c,0x83,0x00,0x10,0x8f,0x82,0x91,0xe8,
29020x00,0x80,0x80,0x21,0x3c,0x04,0x80,0x01,0x30,0x46,0x00,0x01,0x10,0x60,0x00,0x11,
29030x24,0x84,0x08,0xdc,0x8e,0x02,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,
29040x00,0x00,0x00,0x00,0x8e,0x05,0x00,0x10,0x8e,0x03,0x00,0x14,0x8e,0x02,0x00,0x04,
29050x00,0xa3,0x28,0x21,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,
29060x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21,0x00,0x02,0x12,0x00,0x30,0x42,0x3f,0xff,
29070xae,0x02,0x00,0x04,0x14,0xc0,0x00,0x0a,0x00,0x00,0x00,0x00,0xae,0x00,0x00,0x00,
29080xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,
29090x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
29100x8e,0x05,0x00,0x10,0x8e,0x07,0x00,0x04,0x8e,0x06,0x00,0x14,0x0c,0x00,0x17,0x9d,
29110x00,0x00,0x00,0x00,0x08,0x00,0x2c,0xd4,0xae,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
29120x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0xb3,0x8c,0xac,0x62,0x00,0x00,
29130x8c,0x86,0x00,0x04,0x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01,0x00,0xc2,0x10,0x21,
29140x8c,0x45,0x00,0x00,0xac,0x83,0x00,0x4c,0x00,0x05,0x14,0x02,0x30,0xa3,0x3f,0xff,
29150x30,0x42,0x00,0xff,0xac,0x83,0x00,0x10,0xac,0x82,0x00,0x14,0x8c,0x83,0x00,0x14,
29160xac,0x85,0x00,0x40,0x00,0xc3,0x30,0x21,0x03,0xe0,0x00,0x08,0xac,0x86,0x00,0x08,
29170x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,
29180x24,0x63,0xb3,0xe0,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,
29190x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x00,0x80,0x80,0x21,
29200xae,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,
29210xae,0x00,0x00,0x0c,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
29220x27,0xbd,0x00,0x18,0x0c,0x00,0x2c,0xe3,0x00,0x00,0x00,0x00,0x08,0x00,0x2d,0x05,
29230xae,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
29240x34,0x42,0x00,0x20,0x24,0x63,0xb4,0x44,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
29250xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16,
29260x00,0x80,0x80,0x21,0x8e,0x03,0x00,0x08,0x3c,0x02,0xb0,0x01,0x8e,0x04,0x00,0x44,
29270x00,0x62,0x18,0x21,0x90,0x65,0x00,0x00,0x24,0x02,0x00,0x01,0xae,0x02,0x00,0x50,
29280x30,0xa3,0x00,0xff,0x00,0x03,0x10,0x82,0x00,0x04,0x23,0x02,0x30,0x84,0x00,0x0f,
29290x30,0x42,0x00,0x03,0x00,0x03,0x19,0x02,0xae,0x04,0x00,0x34,0xae,0x02,0x00,0x2c,
29300xae,0x03,0x00,0x30,0xa2,0x05,0x00,0x48,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
29310x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x2c,0xe3,0x00,0x00,0x00,0x00,
29320x08,0x00,0x2d,0x1d,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
29330x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xb4,0xd8,0xaf,0xb0,0x00,0x10,
29340xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00,
29350x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,0x92,0x03,0x00,0x44,0x8e,0x02,0x00,0x40,
29360x83,0x85,0x92,0x15,0x92,0x04,0x00,0x41,0x30,0x63,0x00,0x01,0x00,0x02,0x16,0x02,
29370xae,0x04,0x00,0x14,0x00,0x00,0x30,0x21,0xae,0x02,0x00,0x18,0x10,0xa0,0x00,0x04,
29380xae,0x03,0x00,0x3c,0x10,0x60,0x00,0x03,0x24,0x02,0x00,0x01,0x24,0x06,0x00,0x01,
29390x24,0x02,0x00,0x01,0xa3,0x86,0x92,0x15,0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,
29400x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x2d,0x11,
29410x00,0x00,0x00,0x00,0x08,0x00,0x2d,0x42,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
29420x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xb5,0x6c,
29430xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,
29440x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1b,0x00,0x80,0x80,0x21,0x3c,0x02,0xb0,0x03,
29450x8c,0x42,0x00,0x00,0x92,0x04,0x00,0x44,0x8e,0x03,0x00,0x40,0x83,0x86,0x92,0x15,
29460x92,0x05,0x00,0x41,0x30,0x42,0x08,0x00,0x30,0x84,0x00,0x01,0x00,0x02,0x12,0xc2,
29470x00,0x03,0x1e,0x02,0x00,0x82,0x20,0x25,0xae,0x05,0x00,0x14,0x00,0x00,0x38,0x21,
29480xae,0x03,0x00,0x18,0x10,0xc0,0x00,0x04,0xae,0x04,0x00,0x3c,0x10,0x80,0x00,0x03,
29490x24,0x02,0x00,0x01,0x24,0x07,0x00,0x01,0x24,0x02,0x00,0x01,0xa3,0x87,0x92,0x15,
29500x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
29510x27,0xbd,0x00,0x18,0x0c,0x00,0x2d,0x11,0x00,0x00,0x00,0x00,0x08,0x00,0x2d,0x67,
29520x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
29530x34,0x42,0x00,0x20,0x24,0x63,0xb6,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
29540xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x21,
29550x00,0x80,0x80,0x21,0x8e,0x05,0x00,0x04,0x8e,0x04,0x00,0x44,0x3c,0x03,0x80,0x00,
29560x34,0x63,0x00,0x10,0x3c,0x02,0xb0,0x01,0x00,0xa2,0x28,0x21,0x00,0x83,0x20,0x25,
29570xac,0xa4,0x00,0x04,0x8e,0x03,0x01,0xac,0x8e,0x08,0x00,0x04,0x3c,0x07,0xb0,0x03,
29580x24,0x66,0x00,0x01,0x28,0xc5,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xc5,0x10,0x0a,
29590x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xc2,0x30,0x23,
29600x00,0x70,0x18,0x21,0xae,0x06,0x01,0xac,0x34,0xe7,0x00,0x30,0xac,0x68,0x00,0xa8,
29610x8c,0xe2,0x00,0x00,0x02,0x00,0x20,0x21,0x24,0x42,0x00,0x01,0x0c,0x00,0x2c,0xb2,
29620xac,0xe2,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
29630x27,0xbd,0x00,0x18,0x0c,0x00,0x2d,0x5b,0x00,0x00,0x00,0x00,0x08,0x00,0x2d,0x91,
29640x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
29650x34,0x42,0x00,0x20,0x24,0x63,0xb6,0xd4,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
29660xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x21,
29670x00,0x80,0x80,0x21,0x8e,0x05,0x00,0x04,0x8e,0x04,0x00,0x44,0x3c,0x03,0x80,0x00,
29680x34,0x63,0x00,0x10,0x3c,0x02,0xb0,0x01,0x00,0xa2,0x28,0x21,0x00,0x83,0x20,0x25,
29690xac,0xa4,0x00,0x04,0x8e,0x03,0x01,0xac,0x8e,0x08,0x00,0x04,0x3c,0x07,0xb0,0x03,
29700x24,0x66,0x00,0x01,0x28,0xc5,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xc5,0x10,0x0a,
29710x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xc2,0x30,0x23,
29720x00,0x70,0x18,0x21,0xae,0x06,0x01,0xac,0x34,0xe7,0x00,0x30,0xac,0x68,0x00,0xa8,
29730x8c,0xe2,0x00,0x00,0x02,0x00,0x20,0x21,0x24,0x42,0x00,0x01,0x0c,0x00,0x2c,0xb2,
29740xac,0xe2,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
29750x27,0xbd,0x00,0x18,0x0c,0x00,0x2d,0x5b,0x00,0x00,0x00,0x00,0x08,0x00,0x2d,0xc1,
29760x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,
29770x24,0x63,0xb7,0x94,0x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00,0x3c,0x02,0x80,0x01,
29780xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,0x00,0x80,0x80,0x21,
29790x24,0x51,0xb2,0xb0,0x3c,0x03,0xb0,0x09,0x34,0x63,0x00,0x06,0x8e,0x07,0x00,0x04,
29800x90,0x62,0x00,0x00,0x00,0x07,0x22,0x02,0x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,
29810x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,
29820x00,0x02,0x11,0x80,0x24,0x84,0xff,0xff,0x10,0x44,0x00,0x5f,0x00,0x00,0x40,0x21,
29830x3c,0x02,0xb0,0x01,0x00,0xe2,0x10,0x21,0x8c,0x44,0x00,0x04,0x3c,0x03,0x7c,0x00,
29840x34,0x63,0x00,0xf0,0x00,0x83,0x18,0x24,0xae,0x04,0x00,0x44,0x8c,0x44,0x00,0x00,
29850x10,0x60,0x00,0x60,0x00,0x00,0x48,0x21,0x24,0xe2,0x01,0x00,0x30,0x45,0x3f,0xff,
29860x3c,0x03,0xb0,0x01,0xae,0x05,0x00,0x04,0x00,0xa3,0x18,0x21,0x8c,0x64,0x00,0x04,
29870x3c,0x02,0x7c,0x00,0x34,0x42,0x00,0xf0,0x00,0x82,0x30,0x24,0xae,0x04,0x00,0x44,
29880x25,0x08,0x00,0x01,0x24,0x02,0x00,0x40,0x00,0xa0,0x38,0x21,0x8c,0x64,0x00,0x00,
29890x11,0x02,0x00,0x30,0x24,0x09,0x00,0x01,0x3c,0x02,0xff,0xff,0x14,0xc0,0xff,0xee,
29900x00,0x82,0x18,0x24,0x3c,0x02,0x28,0x38,0x14,0x62,0xff,0xec,0x24,0xe2,0x01,0x00,
29910x24,0x02,0x00,0x01,0x11,0x22,0x00,0x2e,0x3c,0x03,0xb0,0x09,0x8e,0x02,0x00,0x44,
29920x8e,0x04,0x00,0x60,0x00,0x02,0x1e,0x42,0x00,0x02,0x12,0x02,0x30,0x42,0x00,0x0f,
29930x30,0x63,0x00,0x01,0xae,0x02,0x00,0x00,0x10,0x44,0x00,0x1a,0xae,0x03,0x00,0x58,
29940x8e,0x02,0x00,0x64,0x8e,0x04,0x00,0x58,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x05,
29950x00,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,
29960xae,0x00,0x00,0x0c,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x80,
29970x00,0x50,0x10,0x21,0x8c,0x42,0x00,0x68,0x00,0x00,0x00,0x00,0x10,0x51,0x00,0x06,
29980x00,0x00,0x00,0x00,0x00,0x40,0xf8,0x09,0x02,0x00,0x20,0x21,0x8e,0x04,0x00,0x58,
29990x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x03,0x00,0x60,0x08,0x00,0x2d,0xf1,
30000xae,0x04,0x00,0x64,0x8e,0x02,0x00,0x64,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xe5,
30010x00,0x00,0x00,0x00,0x7a,0x02,0x0d,0x7c,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,
30020x00,0x43,0x10,0x26,0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
30030x34,0x63,0x00,0x06,0x8e,0x04,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x04,0x22,0x02,
30040x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,
30050x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,
30060x14,0x89,0xff,0xc6,0x00,0x00,0x00,0x00,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
30070x2c,0x62,0x00,0x03,0x14,0x40,0x00,0x05,0x24,0x02,0x00,0x0d,0x10,0x62,0x00,0x03,
30080x24,0x02,0x00,0x01,0x08,0x00,0x2e,0x49,0xa2,0x02,0x00,0x5c,0x08,0x00,0x2e,0x49,
30090xa2,0x00,0x00,0x5c,0x3c,0x02,0xff,0xff,0x00,0x82,0x10,0x24,0x3c,0x03,0x28,0x38,
30100x14,0x43,0xff,0x9d,0x24,0x02,0x00,0x01,0x08,0x00,0x2e,0x21,0x00,0x00,0x00,0x00,
30110x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0xb9,0xc0,
30120xac,0x62,0x00,0x00,0x8c,0x83,0x01,0xa8,0x3c,0x05,0xb0,0x06,0x34,0xa5,0x80,0x18,
30130x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0xa8,0x3c,0x03,0x00,0x80,
30140x00,0x02,0x10,0xc2,0x00,0x02,0x12,0x00,0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x00,
30150x8c,0x83,0x01,0xa8,0x8c,0x82,0x01,0xac,0x24,0x66,0x00,0x01,0x28,0xc5,0x00,0x00,
30160x24,0x63,0x00,0x40,0x00,0xc5,0x18,0x0a,0x00,0x03,0x19,0x83,0x00,0x03,0x19,0x80,
30170x00,0xc3,0x30,0x23,0x00,0xc2,0x10,0x26,0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,
30180xac,0x86,0x01,0xa8,0x90,0x87,0x00,0x00,0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8,
30190x24,0x48,0x02,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x01,0x07,0x18,0x21,
30200x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x20,0x10,0x40,0x00,0x0a,
30210x00,0x00,0x80,0x21,0x24,0x84,0x00,0x01,0x90,0x87,0x00,0x00,0x00,0x00,0x00,0x00,
30220x01,0x07,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x20,
30230x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x07,0x16,0x00,0x00,0x02,0x16,0x03,
30240x24,0x03,0x00,0x2d,0x10,0x43,0x00,0x0f,0x00,0x00,0x00,0x00,0x0c,0x00,0x2e,0xb8,
30250x00,0x00,0x00,0x00,0x00,0x40,0x18,0x21,0x00,0x02,0x10,0x23,0x04,0x61,0x00,0x05,
30260x00,0x70,0x10,0x0a,0x16,0x00,0x00,0x03,0x3c,0x02,0x80,0x00,0x3c,0x02,0x7f,0xff,
30270x34,0x42,0xff,0xff,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
30280x27,0xbd,0x00,0x18,0x24,0x10,0xff,0xff,0x08,0x00,0x2e,0xa7,0x24,0x84,0x00,0x01,
30290x00,0x80,0x38,0x21,0x90,0x84,0x00,0x00,0x3c,0x02,0x80,0x01,0x24,0x48,0x02,0x14,
30300x01,0x04,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x20,
30310x10,0x40,0x00,0x0a,0x00,0x00,0x50,0x21,0x24,0xe7,0x00,0x01,0x90,0xe4,0x00,0x00,
30320x00,0x00,0x00,0x00,0x01,0x04,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
30330x30,0x42,0x00,0x20,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x04,0x16,0x00,
30340x00,0x02,0x16,0x03,0x38,0x42,0x00,0x2b,0x24,0xe3,0x00,0x01,0x24,0x04,0x00,0x10,
30350x10,0xc4,0x00,0x38,0x00,0x62,0x38,0x0a,0x90,0xe4,0x00,0x00,0x14,0xc0,0x00,0x07,
30360x00,0x80,0x18,0x21,0x00,0x04,0x16,0x00,0x00,0x02,0x16,0x03,0x24,0x03,0x00,0x30,
30370x10,0x43,0x00,0x25,0x24,0x06,0x00,0x0a,0x00,0x80,0x18,0x21,0x00,0x03,0x16,0x00,
30380x10,0x40,0x00,0x1a,0x30,0x64,0x00,0xff,0x24,0x82,0xff,0xa9,0x2c,0x83,0x00,0x61,
30390x30,0x48,0x00,0xff,0x10,0x60,0x00,0x09,0x2c,0x89,0x00,0x41,0x24,0x82,0xff,0xc9,
30400x30,0x48,0x00,0xff,0x11,0x20,0x00,0x05,0x2c,0x83,0x00,0x3a,0x24,0x82,0xff,0xd0,
30410x14,0x60,0x00,0x02,0x30,0x48,0x00,0xff,0x24,0x08,0x00,0xff,0x01,0x06,0x10,0x2a,
30420x10,0x40,0x00,0x0a,0x01,0x46,0x00,0x18,0x24,0xe7,0x00,0x01,0x00,0x00,0x18,0x12,
30430x00,0x6a,0x10,0x2b,0x14,0x40,0x00,0x0a,0x00,0x68,0x50,0x21,0x80,0xe2,0x00,0x00,
30440x90,0xe3,0x00,0x00,0x14,0x40,0xff,0xe8,0x30,0x64,0x00,0xff,0x10,0xa0,0x00,0x02,
30450x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x03,0xe0,0x00,0x08,0x01,0x40,0x10,0x21,
30460x03,0xe0,0x00,0x08,0x24,0x02,0xff,0xff,0x24,0x06,0x00,0x08,0x80,0xe3,0x00,0x01,
30470x24,0x02,0x00,0x78,0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x58,0x14,0x62,0xff,0xd7,
30480x00,0x80,0x18,0x21,0x24,0xe7,0x00,0x02,0x90,0xe4,0x00,0x00,0x08,0x00,0x2e,0xda,
30490x24,0x06,0x00,0x10,0x80,0xe3,0x00,0x00,0x24,0x02,0x00,0x30,0x90,0xe4,0x00,0x00,
30500x10,0x62,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x2e,0xd3,0x00,0x00,0x00,0x00,
30510x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01,0x34,0xc6,0x00,0x18,
30520x34,0x84,0x00,0x20,0x24,0x42,0xbc,0x40,0x24,0x03,0xff,0x83,0xac,0x82,0x00,0x00,
30530xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8,0x3c,0x03,0xb0,0x07,
30540x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00,0x90,0x64,0x00,0x00,
30550x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01,0xa0,0x40,0x00,0x00,
30560x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07,0xa3,0xa3,0x00,0x00,
30570xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10,0x24,0x02,0x00,0x06,
30580x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38,0xa0,0xa2,0x00,0x00,
30590x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20,0xa3,0xa4,0x00,0x00,
30600xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xc2,0x5c,0xa3,0xa3,0x00,0x00,
30610xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,
3062};
3063
3064#define DataArrayLengthDTM 2860
3065u8 Rtl8192PciEFwDataArrayDTM[DataArrayLengthDTM] = {
30660x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x0d,0x5b,0x43,
30670x4d,0x50,0x4b,0x5d,0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x0c,0x00,0x00,0x00,0x00,
30680x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30690x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30700x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30710x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30720x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30730x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30740x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30750x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30760x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30770x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30780x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30790x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30800x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30810x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30820x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30830x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30840x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30850x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30860x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30870x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30880x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30890x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30900x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30910x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30920x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30930x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30940x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30950x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30960x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30970x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30980x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30990x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x28,0x28,0x28,
31000x28,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
31010x08,0x08,0x08,0x08,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
31020x10,0x10,0x10,0x10,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x10,0x10,
31030x10,0x10,0x10,0x10,0x10,0x41,0x41,0x41,0x41,0x41,0x41,0x01,0x01,0x01,0x01,0x01,
31040x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,
31050x10,0x10,0x10,0x10,0x10,0x42,0x42,0x42,0x42,0x42,0x42,0x02,0x02,0x02,0x02,0x02,
31060x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,
31070x10,0x10,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31080x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31090x00,0x00,0x00,0x00,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
31100x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
31110x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
31120x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,0x01,0x01,0x01,0x01,
31130x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
31140x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,0x02,0x02,0x02,0x02,
31150x02,0x02,0x02,0x02,0x20,0x09,0x0d,0x0a,0x00,0x00,0x00,0x00,0x80,0x01,0x03,0x14,
31160x00,0x00,0x00,0x00,0x43,0x6e,0x73,0x64,0x31,0x00,0x00,0x00,0x68,0x65,0x6c,0x70,
31170x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x72,0x34,0x00,0x00,0x77,0x34,0x00,0x00,
31180x64,0x62,0x67,0x00,0x72,0x61,0x63,0x74,0x72,0x6c,0x00,0x00,0x73,0x79,0x73,0x64,
31190x00,0x00,0x00,0x00,0x73,0x79,0x73,0x63,0x74,0x72,0x6c,0x00,0x74,0x78,0x74,0x62,
31200x6c,0x00,0x00,0x00,0x70,0x72,0x61,0x6e,0x67,0x65,0x00,0x00,0x64,0x6d,0x00,0x00,
31210x75,0x6e,0x6b,0x6e,0x6f,0x77,0x00,0x00,0x80,0x01,0x03,0x2c,0x80,0x01,0x03,0x34,
31220x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x20,0x5c,
31230x80,0x01,0x03,0x38,0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,
31240x00,0x00,0x00,0x00,0x80,0x00,0x21,0xbc,0x80,0x01,0x03,0x3c,0x80,0x01,0x03,0x34,
31250x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x23,0x38,
31260x80,0x01,0x03,0x40,0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,
31270x00,0x00,0x00,0x00,0x80,0x00,0x25,0x04,0x80,0x01,0x03,0x44,0x80,0x01,0x03,0x34,
31280x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x25,0xdc,
31290x80,0x01,0x03,0x4c,0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,
31300x00,0x00,0x00,0x00,0x80,0x00,0x25,0xe4,0x80,0x01,0x03,0x54,0x80,0x01,0x03,0x34,
31310x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x26,0x88,
31320x80,0x01,0x03,0x5c,0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,
31330x00,0x00,0x00,0x00,0x80,0x00,0x26,0x90,0x80,0x01,0x03,0x64,0x80,0x01,0x03,0x34,
31340x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x80,0x00,0x28,0x1c,
31350x80,0x01,0x03,0x6c,0x80,0x01,0x03,0x34,0x80,0x01,0x03,0x34,0x00,0x00,0x00,0x01,
31360x00,0x00,0x00,0x00,0x80,0x00,0x28,0x90,0x80,0x01,0x03,0x70,0x80,0x01,0x03,0x34,
31370x80,0x01,0x03,0x34,0x00,0x00,0x00,0x0f,0x00,0x00,0x00,0x01,0x80,0x00,0x29,0x1c,
31380x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x0d,0x52,0x54,0x4c,0x38,0x31,0x39,
31390x58,0x2d,0x25,0x64,0x3e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x54,0x4c,0x38,
31400x31,0x39,0x58,0x2d,0x25,0x64,0x3e,0x0a,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31410x2a,0x00,0x00,0x00,0x0a,0x0d,0x45,0x72,0x72,0x20,0x44,0x49,0x52,0x00,0x00,0x00,
31420x0a,0x0d,0x44,0x42,0x47,0x20,0x43,0x4d,0x44,0x73,0x3a,0x00,0x0a,0x0d,0x5b,0x00,
31430x5d,0x2d,0x00,0x00,0x0a,0x0d,0x3c,0x31,0x2e,0x43,0x4d,0x4e,0x3e,0x20,0x3c,0x32,
31440x2e,0x3f,0x3e,0x00,0x0a,0x0d,0x20,0x79,0x65,0x61,0x72,0x2d,0x64,0x61,0x79,0x2d,
31450x68,0x6f,0x75,0x72,0x2d,0x6d,0x69,0x6e,0x2d,0x73,0x65,0x63,0x2d,0x31,0x30,0x6d,
31460x73,0x3d,0x00,0x00,0x25,0x64,0x2d,0x00,0x0a,0x0d,0x09,0x20,0x20,0x20,0x20,0x20,
31470x30,0x30,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x30,0x34,0x20,0x20,0x20,0x20,0x20,
31480x20,0x20,0x30,0x38,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x30,0x43,0x00,0x00,0x00,
31490x0a,0x0d,0x09,0x20,0x20,0x20,0x20,0x20,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,
31500x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,
31510x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x3d,0x00,0x0d,0x0a,0x20,0x30,
31520x78,0x25,0x30,0x38,0x58,0x20,0x20,0x00,0x09,0x00,0x00,0x00,0x25,0x30,0x38,0x58,
31530x20,0x00,0x00,0x00,0x0a,0x0d,0x44,0x62,0x67,0x5f,0x46,0x6c,0x61,0x67,0x25,0x64,
31540x3d,0x30,0x78,0x25,0x30,0x38,0x78,0x00,0x0a,0x0d,0x20,0x76,0x6f,0x71,0x74,0x78,
31550x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,0x00,0x00,0x00,0x00,0x0a,0x0d,0x20,0x76,
31560x69,0x71,0x74,0x78,0x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,0x00,0x00,0x00,0x00,
31570x0a,0x0d,0x20,0x62,0x65,0x71,0x74,0x78,0x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,
31580x00,0x00,0x00,0x00,0x0a,0x0d,0x20,0x62,0x6b,0x71,0x74,0x78,0x72,0x65,0x71,0x20,
31590x3d,0x20,0x25,0x64,0x00,0x00,0x00,0x00,0x0a,0x0d,0x20,0x62,0x63,0x6e,0x71,0x74,
31600x78,0x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,0x00,0x00,0x00,0x0a,0x0d,0x20,0x68,
31610x71,0x74,0x78,0x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,0x00,0x0a,0x0d,0x20,0x6d,
31620x67,0x71,0x74,0x78,0x72,0x65,0x71,0x20,0x3d,0x20,0x25,0x64,0x00,0x00,0x00,0x00,
31630x0a,0x0d,0x54,0x58,0x4c,0x4c,0x54,0x09,0x09,0x4e,0x45,0x58,0x54,0x20,0x20,0x20,
31640x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x4e,0x45,0x58,0x54,0x0a,0x0d,0x00,
31650x0a,0x0d,0x20,0x50,0x61,0x67,0x65,0x25,0x33,0x64,0x09,0x00,0x25,0x34,0x64,0x20,
31660x20,0x20,0x20,0x00,0x25,0x34,0x64,0x20,0x20,0x20,0x20,0x09,0x00,0x00,0x00,0x00,
31670x0a,0x0d,0x54,0x58,0x4f,0x51,0x54,0x09,0x09,0x48,0x65,0x61,0x64,0x20,0x20,0x20,
31680x20,0x54,0x61,0x69,0x6c,0x20,0x20,0x20,0x20,0x48,0x65,0x61,0x64,0x20,0x20,0x20,
31690x20,0x54,0x61,0x69,0x6c,0x0a,0x0d,0x00,0x0a,0x0d,0x55,0x6e,0x6b,0x6e,0x6f,0x77,
31700x20,0x63,0x6f,0x6d,0x6d,0x61,0x6e,0x64,0x00,0x00,0x00,0x00,0x0a,0x0d,0x45,0x72,
31710x72,0x20,0x41,0x72,0x67,0x0a,0x0d,0x55,0x53,0x41,0x47,0x45,0x3a,0x00,0x00,0x00,
31720x10,0x00,0x08,0x00,0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,
31730x00,0xab,0x00,0x72,0x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,
31740x02,0x76,0x01,0x3b,0x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f,
31750x01,0x3b,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20,
31760x01,0x2f,0x00,0x98,0x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e,
31770x00,0x98,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f,
31780x02,0x39,0x01,0x1c,0x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39,
31790x01,0x1c,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c,
31800x01,0x11,0x00,0x89,0x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b,
31810x00,0x89,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e,
31820x02,0xab,0x02,0xab,0x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08,
31830x04,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00,
31840x00,0x00,0x54,0x4c,0x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c,
31850x5f,0x64,0x61,0x74,0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,
31860x41,0x64,0x45,0x4c,0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,
31870x00,0x00,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,
31880x63,0x43,0x6f,0x64,0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,
31890x00,0x00,0x42,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,
31900x00,0x00,0x00,0x00,0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31910x4f,0x76,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31920x80,0x01,0x11,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x10,
31930x00,0x00,0x00,0x30,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x50,
31940x00,0x00,0x00,0x60,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,
31950x00,0x00,0x01,0x80,0x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xd0,
31960x00,0x00,0x01,0x30,0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x70,0x00,0x00,0x03,0x40,
31970x00,0x00,0x03,0xa0,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0xa0,
31980x00,0x00,0x02,0x70,0x00,0x00,0x03,0x40,0x00,0x00,0x04,0xe0,0x00,0x00,0x06,0x80,
31990x00,0x00,0x07,0x50,0x00,0x00,0x07,0xf8,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,
32000x02,0x02,0x02,0x02,0x01,0x01,0x02,0x02,0x04,0x05,0x06,0x06,0x02,0x02,0x04,0x06,
32010x07,0x09,0x0a,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
32020x00,0x00,0x00,0x00,0x3c,0x4e,0x55,0x4c,0x4c,0x3e,0x00,0x00,0x30,0x31,0x32,0x33,
32030x34,0x35,0x36,0x37,0x38,0x39,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,
32040x6b,0x6c,0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,
32050x00,0x00,0x00,0x00,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x41,0x42,
32060x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,0x50,0x51,0x52,
32070x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x00,0x00,0x00,0x00,0x5b,0x52,0x58,0x5d,
32080x20,0x70,0x6b,0x74,0x5f,0x6c,0x65,0x6e,0x3d,0x25,0x64,0x20,0x6f,0x66,0x66,0x73,
32090x65,0x74,0x3d,0x25,0x64,0x20,0x73,0x74,0x61,0x72,0x74,0x5f,0x61,0x64,0x64,0x72,
32100x3d,0x25,0x30,0x38,0x78,0x0a,0x0d,0x00,0x80,0x00,0x6a,0x64,0x80,0x00,0x6a,0x88,
32110x80,0x00,0x6a,0xa4,0x80,0x00,0x6b,0x90,0x80,0x00,0x6c,0x48,0x80,0x00,0x6c,0x98,
32120x80,0x00,0x6d,0x04,0x80,0x00,0x6e,0x08,0x80,0x00,0x6e,0x3c,0x80,0x00,0x6e,0x50,
32130x80,0x00,0x6e,0x64,0x80,0x00,0x6f,0x3c,0x80,0x00,0x6f,0x78,0x80,0x00,0x70,0x28,
32140x80,0x00,0x70,0x50,0x80,0x00,0x6a,0x20,0x80,0x00,0x70,0x64,0x80,0x00,0x76,0x5c,
32150x80,0x00,0x76,0xd4,0x80,0x00,0x76,0xe0,0x80,0x00,0x76,0xec,0x80,0x00,0x76,0x74,
32160x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,
32170x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,
32180x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0x74,0x80,0x00,0x76,0xf8,
32190x80,0x00,0x77,0x04,0x80,0x00,0x77,0x10,0x80,0x00,0xa7,0x80,0x80,0x00,0xa7,0x98,
32200x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x88,0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,
32210x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,
32220x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x90,0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x78,
32230x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,0x80,0x00,0xab,0xc0,0x80,0x00,0xa8,0xb0,
32240x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32250x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32260x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32270x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32280x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32290x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32300x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32310x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32320x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32330x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32340x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32350x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32360x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xbc,0x80,0x00,0xaa,0xc8,
32370x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32380x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32390x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0x44,0x80,0x00,0xa9,0x90,0x80,0x00,0xaa,0xc8,
32400x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa9,0x90,
32410x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,
32420x80,0x00,0xa9,0x98,0x80,0x00,0xa9,0xb8,0x80,0x00,0xa9,0xc0,0x80,0x00,0xaa,0xc8,
32430x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0x18,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xc4,
32440x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xc0,};
3245
3246#define PHY_REGArrayLengthDTM 1
3247u32 Rtl8192PciEPHY_REGArrayDTM[PHY_REGArrayLengthDTM] = {
32480x0, };
3249
3250#define PHY_REG_1T2RArrayLengthDTM 296
3251u32 Rtl8192PciEPHY_REG_1T2RArrayDTM[PHY_REG_1T2RArrayLengthDTM] = {
32520x800,0x00000000,
32530x804,0x00000001,
32540x808,0x0000fc00,
32550x80c,0x0000001c,
32560x810,0x801010aa,
32570x814,0x008514d0,
32580x818,0x00000040,
32590x81c,0x00000000,
32600x820,0x00000004,
32610x824,0x00690000,
32620x828,0x00000004,
32630x82c,0x00e90000,
32640x830,0x00000004,
32650x834,0x00690000,
32660x838,0x00000004,
32670x83c,0x00e90000,
32680x840,0x00000000,
32690x844,0x00000000,
32700x848,0x00000000,
32710x84c,0x00000000,
32720x850,0x00000000,
32730x854,0x00000000,
32740x858,0x65a965a9,
32750x85c,0x65a965a9,
32760x860,0x001f0010,
32770x864,0x007f0010,
32780x868,0x001f0010,
32790x86c,0x007f0010,
32800x870,0x0f100f70,
32810x874,0x0f100f70,
32820x878,0x00000000,
32830x87c,0x00000000,
32840x880,0x6870e36c,
32850x884,0xe3573600,
32860x888,0x4260c340,
32870x88c,0x0000ff00,
32880x890,0x00000000,
32890x894,0xfffffffe,
32900x898,0x40302010,
32910x89c,0x00706050,
32920x8b0,0x00000000,
32930x8e0,0x00000000,
32940x8e4,0x00000000,
32950x900,0x00000000,
32960x904,0x00000023,
32970x908,0x00000000,
32980x90c,0x31121311,
32990xa00,0x00d0c7d8,
33000xa04,0x811f0008,
33010xa08,0x80cd8300,
33020xa0c,0x2e62740f,
33030xa10,0x95009b78,
33040xa14,0x11145008,
33050xa18,0x00881117,
33060xa1c,0x89140fa0,
33070xa20,0x1a1b0000,
33080xa24,0x090e1317,
33090xa28,0x00000204,
33100xa2c,0x00000000,
33110xc00,0x00000040,
33120xc04,0x00005411,
33130xc08,0x000000e4,
33140xc0c,0x6c6c6c6c,
33150xc10,0x08800000,
33160xc14,0x40000100,
33170xc18,0x08000000,
33180xc1c,0x40000100,
33190xc20,0x08000000,
33200xc24,0x40000100,
33210xc28,0x08000000,
33220xc2c,0x40000100,
33230xc30,0x6de98a44,
33240xc34,0x469652cd,
33250xc38,0x49475996,
33260xc3c,0x0a9a9764,
33270xc40,0x1f7c423f,
33280xc44,0x000100b7,
33290xc48,0xec020000,
33300xc4c,0x00000300,
33310xc50,0x69543430,
33320xc54,0x433c0094,
33330xc58,0x69543430,
33340xc5c,0x433c0094,
33350xc60,0x69543430,
33360xc64,0x433c0094,
33370xc68,0x69543430,
33380xc6c,0x433c0094,
33390xc70,0x2c7f000d,
33400xc74,0x0186175b,
33410xc78,0x0000001f,
33420xc7c,0x00b91612,
33430xc80,0x40000100,
33440xc84,0x20000000,
33450xc88,0x40000100,
33460xc8c,0x08000000,
33470xc90,0x40000100,
33480xc94,0x00000000,
33490xc98,0x40000100,
33500xc9c,0x00000000,
33510xca0,0x00492492,
33520xca4,0x00000000,
33530xca8,0x00000000,
33540xcac,0x00000000,
33550xcb0,0x00000000,
33560xcb4,0x00000000,
33570xcb8,0x00000000,
33580xcbc,0x00492492,
33590xcc0,0x00000000,
33600xcc4,0x00000000,
33610xcc8,0x00000000,
33620xccc,0x00000000,
33630xcd0,0x00000000,
33640xcd4,0x00000000,
33650xcd8,0x64b22427,
33660xcdc,0x00766932,
33670xce0,0x00222222,
33680xd00,0x00000740,
33690xd04,0x00000401,
33700xd08,0x0000907f,
33710xd0c,0x00000001,
33720xd10,0xa0633333,
33730xd14,0x33333c63,
33740xd18,0x6a8f5b6b,
33750xd1c,0x00000000,
33760xd20,0x00000000,
33770xd24,0x00000000,
33780xd28,0x00000000,
33790xd2c,0xcc979975,
33800xd30,0x00000000,
33810xd34,0x00000000,
33820xd38,0x00000000,
33830xd3c,0x00027293,
33840xd40,0x00000000,
33850xd44,0x00000000,
33860xd48,0x00000000,
33870xd4c,0x00000000,
33880xd50,0x6437140a,
33890xd54,0x024dbd02,
33900xd58,0x00000000,
33910xd5c,0x2d432064,
33920xe00,0x161a1a1a,
33930xe04,0x12121416,
33940xe08,0x00001800,
33950xe0c,0x00000000,
33960xe10,0x161a1a1a,
33970xe14,0x12121416,
33980xe18,0x161a1a1a,
33990xe1c,0x12121416,
3400};
3401
3402#define RadioA_ArrayLengthDTM 246
3403u32 Rtl8192PciERadioA_ArrayDTM[RadioA_ArrayLengthDTM] = {
34040x019,0x00000003,
34050x000,0x000000bf,
34060x001,0x00000ee0,
34070x002,0x0000004c,
34080x003,0x000007f1,
34090x004,0x00000975,
34100x005,0x00000c58,
34110x006,0x00000ae6,
34120x007,0x000000ca,
34130x008,0x00000e1c,
34140x009,0x000007f0,
34150x00a,0x000009d0,
34160x00b,0x000001ba,
34170x00c,0x00000240,
34180x00e,0x00000020,
34190x00f,0x00000ff0,
34200x012,0x00000806,
34210x014,0x000005ab,
34220x015,0x00000f80,
34230x016,0x00000020,
34240x017,0x00000597,
34250x018,0x0000050a,
34260x01a,0x00000e00,
34270x01b,0x00000f5e,
34280x01c,0x00000008,
34290x01d,0x00000607,
34300x01e,0x000006cc,
34310x01f,0x00000000,
34320x020,0x00000096,
34330x01f,0x00000001,
34340x020,0x00000076,
34350x01f,0x00000002,
34360x020,0x00000056,
34370x01f,0x00000003,
34380x020,0x00000036,
34390x01f,0x00000004,
34400x020,0x00000016,
34410x01f,0x00000005,
34420x020,0x000001f6,
34430x01f,0x00000006,
34440x020,0x000001d6,
34450x01f,0x00000007,
34460x020,0x000001b6,
34470x01f,0x00000008,
34480x020,0x00000196,
34490x01f,0x00000009,
34500x020,0x00000176,
34510x01f,0x0000000a,
34520x020,0x000000f7,
34530x01f,0x0000000b,
34540x020,0x000000d7,
34550x01f,0x0000000c,
34560x020,0x000000b7,
34570x01f,0x0000000d,
34580x020,0x00000097,
34590x01f,0x0000000e,
34600x020,0x00000077,
34610x01f,0x0000000f,
34620x020,0x00000057,
34630x01f,0x00000010,
34640x020,0x00000037,
34650x01f,0x00000011,
34660x020,0x000000fb,
34670x01f,0x00000012,
34680x020,0x000000db,
34690x01f,0x00000013,
34700x020,0x000000bb,
34710x01f,0x00000014,
34720x020,0x000000ff,
34730x01f,0x00000015,
34740x020,0x000000e3,
34750x01f,0x00000016,
34760x020,0x000000c3,
34770x01f,0x00000017,
34780x020,0x000000a3,
34790x01f,0x00000018,
34800x020,0x00000083,
34810x01f,0x00000019,
34820x020,0x00000063,
34830x01f,0x0000001a,
34840x020,0x00000043,
34850x01f,0x0000001b,
34860x020,0x00000023,
34870x01f,0x0000001c,
34880x020,0x00000003,
34890x01f,0x0000001d,
34900x020,0x000001e3,
34910x01f,0x0000001e,
34920x020,0x000001c3,
34930x01f,0x0000001f,
34940x020,0x000001a3,
34950x01f,0x00000020,
34960x020,0x00000183,
34970x01f,0x00000021,
34980x020,0x00000163,
34990x01f,0x00000022,
35000x020,0x00000143,
35010x01f,0x00000023,
35020x020,0x00000123,
35030x01f,0x00000024,
35040x020,0x00000103,
35050x023,0x00000203,
35060x024,0x00000200,
35070x00b,0x000001ba,
35080x02c,0x000003d7,
35090x02d,0x00000ff0,
35100x000,0x00000037,
35110x004,0x00000160,
35120x007,0x00000080,
35130x002,0x0000088d,
35140x0fe,0x00000000,
35150x0fe,0x00000000,
35160x016,0x00000200,
35170x016,0x00000380,
35180x016,0x00000020,
35190x016,0x000001a0,
35200x000,0x000000bf,
35210x00d,0x0000001f,
35220x00d,0x00000c9f,
35230x002,0x0000004d,
35240x000,0x00000cbf,
35250x004,0x00000975,
35260x007,0x00000700,
3527};
3528
3529#define RadioB_ArrayLengthDTM 78
3530u32 Rtl8192PciERadioB_ArrayDTM[RadioB_ArrayLengthDTM] = {
35310x019,0x00000003,
35320x000,0x000000bf,
35330x001,0x000006e0,
35340x002,0x0000004c,
35350x003,0x000007f1,
35360x004,0x00000975,
35370x005,0x00000c58,
35380x006,0x00000ae6,
35390x007,0x000000ca,
35400x008,0x00000e1c,
35410x000,0x000000b7,
35420x00a,0x00000850,
35430x000,0x000000bf,
35440x00b,0x000001ba,
35450x00c,0x00000240,
35460x00e,0x00000020,
35470x015,0x00000f80,
35480x016,0x00000020,
35490x017,0x00000597,
35500x018,0x0000050a,
35510x01a,0x00000e00,
35520x01b,0x00000f5e,
35530x01d,0x00000607,
35540x01e,0x000006cc,
35550x00b,0x000001ba,
35560x023,0x00000203,
35570x024,0x00000200,
35580x000,0x00000037,
35590x004,0x00000160,
35600x016,0x00000200,
35610x016,0x00000380,
35620x016,0x00000020,
35630x016,0x000001a0,
35640x00d,0x00000ccc,
35650x000,0x000000bf,
35660x002,0x0000004d,
35670x000,0x00000cbf,
35680x004,0x00000975,
35690x007,0x00000700,
3570};
3571
3572#define RadioC_ArrayLengthDTM 1
3573u32 Rtl8192PciERadioC_ArrayDTM[RadioC_ArrayLengthDTM] = {
35740x0, };
3575
3576#define RadioD_ArrayLengthDTM 1
3577u32 Rtl8192PciERadioD_ArrayDTM[RadioD_ArrayLengthDTM] = {
35780x0, };
3579
3580u32 Rtl8192PciEMACPHY_ArrayDTM[] = {
35810x03c,0xffff0000,0x00000f0f,
35820x340,0xffffffff,0x161a1a1a,
35830x344,0xffffffff,0x12121416,
35840x348,0x0000ffff,0x00001818,
35850x12c,0xffffffff,0x04000802,
35860x318,0x00000fff,0x00000100,
3587};
3588
3589u32 Rtl8192PciEMACPHY_Array_PGDTM[] = {
35900x03c,0xffff0000,0x00000f0f,
35910xe00,0xffffffff,0x06090909,
35920xe04,0xffffffff,0x00030306,
35930xe08,0x0000ff00,0x00000000,
35940xe10,0xffffffff,0x050b0b0e,
35950xe14,0xffffffff,0x00030305,
35960xe18,0xffffffff,0x050b0b0e,
35970xe1c,0xffffffff,0x00030305,
35980x12c,0xffffffff,0x04000802,
35990x318,0x00000fff,0x00000800,
3600};
3601
3602u32 Rtl8192PciEAGCTAB_ArrayDTM[AGCTAB_ArrayLength] = {
36030xc78,0x7d000001,
36040xc78,0x7d010001,
36050xc78,0x7d020001,
36060xc78,0x7d030001,
36070xc78,0x7d040001,
36080xc78,0x7d050001,
36090xc78,0x7c060001,
36100xc78,0x7b070001,
36110xc78,0x7a080001,
36120xc78,0x79090001,
36130xc78,0x780a0001,
36140xc78,0x770b0001,
36150xc78,0x760c0001,
36160xc78,0x750d0001,
36170xc78,0x740e0001,
36180xc78,0x730f0001,
36190xc78,0x72100001,
36200xc78,0x71110001,
36210xc78,0x70120001,
36220xc78,0x6f130001,
36230xc78,0x6e140001,
36240xc78,0x6d150001,
36250xc78,0x6c160001,
36260xc78,0x6b170001,
36270xc78,0x6a180001,
36280xc78,0x69190001,
36290xc78,0x681a0001,
36300xc78,0x671b0001,
36310xc78,0x661c0001,
36320xc78,0x651d0001,
36330xc78,0x641e0001,
36340xc78,0x491f0001,
36350xc78,0x48200001,
36360xc78,0x47210001,
36370xc78,0x46220001,
36380xc78,0x45230001,
36390xc78,0x44240001,
36400xc78,0x43250001,
36410xc78,0x28260001,
36420xc78,0x27270001,
36430xc78,0x26280001,
36440xc78,0x25290001,
36450xc78,0x242a0001,
36460xc78,0x232b0001,
36470xc78,0x222c0001,
36480xc78,0x212d0001,
36490xc78,0x202e0001,
36500xc78,0x0a2f0001,
36510xc78,0x08300001,
36520xc78,0x06310001,
36530xc78,0x05320001,
36540xc78,0x04330001,
36550xc78,0x03340001,
36560xc78,0x02350001,
36570xc78,0x01360001,
36580xc78,0x00370001,
36590xc78,0x00380001,
36600xc78,0x00390001,
36610xc78,0x003a0001,
36620xc78,0x003b0001,
36630xc78,0x003c0001,
36640xc78,0x003d0001,
36650xc78,0x003e0001,
36660xc78,0x003f0001,
36670xc78,0x7d400001,
36680xc78,0x7d410001,
36690xc78,0x7d420001,
36700xc78,0x7d430001,
36710xc78,0x7d440001,
36720xc78,0x7d450001,
36730xc78,0x7c460001,
36740xc78,0x7b470001,
36750xc78,0x7a480001,
36760xc78,0x79490001,
36770xc78,0x784a0001,
36780xc78,0x774b0001,
36790xc78,0x764c0001,
36800xc78,0x754d0001,
36810xc78,0x744e0001,
36820xc78,0x734f0001,
36830xc78,0x72500001,
36840xc78,0x71510001,
36850xc78,0x70520001,
36860xc78,0x6f530001,
36870xc78,0x6e540001,
36880xc78,0x6d550001,
36890xc78,0x6c560001,
36900xc78,0x6b570001,
36910xc78,0x6a580001,
36920xc78,0x69590001,
36930xc78,0x685a0001,
36940xc78,0x675b0001,
36950xc78,0x665c0001,
36960xc78,0x655d0001,
36970xc78,0x645e0001,
36980xc78,0x495f0001,
36990xc78,0x48600001,
37000xc78,0x47610001,
37010xc78,0x46620001,
37020xc78,0x45630001,
37030xc78,0x44640001,
37040xc78,0x43650001,
37050xc78,0x28660001,
37060xc78,0x27670001,
37070xc78,0x26680001,
37080xc78,0x25690001,
37090xc78,0x246a0001,
37100xc78,0x236b0001,
37110xc78,0x226c0001,
37120xc78,0x216d0001,
37130xc78,0x206e0001,
37140xc78,0x0a6f0001,
37150xc78,0x08700001,
37160xc78,0x06710001,
37170xc78,0x05720001,
37180xc78,0x04730001,
37190xc78,0x03740001,
37200xc78,0x02750001,
37210xc78,0x01760001,
37220xc78,0x00770001,
37230xc78,0x00780001,
37240xc78,0x00790001,
37250xc78,0x007a0001,
37260xc78,0x007b0001,
37270xc78,0x007c0001,
37280xc78,0x007d0001,
37290xc78,0x007e0001,
37300xc78,0x007f0001,
37310xc78,0x2e00001e,
37320xc78,0x2e01001e,
37330xc78,0x2e02001e,
37340xc78,0x2e03001e,
37350xc78,0x2e04001e,
37360xc78,0x2e05001e,
37370xc78,0x3006001e,
37380xc78,0x3407001e,
37390xc78,0x3908001e,
37400xc78,0x3c09001e,
37410xc78,0x3f0a001e,
37420xc78,0x420b001e,
37430xc78,0x440c001e,
37440xc78,0x450d001e,
37450xc78,0x460e001e,
37460xc78,0x460f001e,
37470xc78,0x4710001e,
37480xc78,0x4811001e,
37490xc78,0x4912001e,
37500xc78,0x4a13001e,
37510xc78,0x4b14001e,
37520xc78,0x4b15001e,
37530xc78,0x4c16001e,
37540xc78,0x4d17001e,
37550xc78,0x4e18001e,
37560xc78,0x4f19001e,
37570xc78,0x4f1a001e,
37580xc78,0x501b001e,
37590xc78,0x511c001e,
37600xc78,0x521d001e,
37610xc78,0x521e001e,
37620xc78,0x531f001e,
37630xc78,0x5320001e,
37640xc78,0x5421001e,
37650xc78,0x5522001e,
37660xc78,0x5523001e,
37670xc78,0x5624001e,
37680xc78,0x5725001e,
37690xc78,0x5726001e,
37700xc78,0x5827001e,
37710xc78,0x5828001e,
37720xc78,0x5929001e,
37730xc78,0x592a001e,
37740xc78,0x5a2b001e,
37750xc78,0x5b2c001e,
37760xc78,0x5c2d001e,
37770xc78,0x5c2e001e,
37780xc78,0x5d2f001e,
37790xc78,0x5e30001e,
37800xc78,0x5f31001e,
37810xc78,0x6032001e,
37820xc78,0x6033001e,
37830xc78,0x6134001e,
37840xc78,0x6235001e,
37850xc78,0x6336001e,
37860xc78,0x6437001e,
37870xc78,0x6438001e,
37880xc78,0x6539001e,
37890xc78,0x663a001e,
37900xc78,0x673b001e,
37910xc78,0x673c001e,
37920xc78,0x683d001e,
37930xc78,0x693e001e,
37940xc78,0x6a3f001e,
3795};
3796
3797#endif //__INC_HAL8192PciE_FW_IMG_DTM_H
diff --git a/drivers/staging/rtl8192su/r8192S_firmware.c b/drivers/staging/rtl8192su/r8192S_firmware.c
new file mode 100644
index 00000000000..b3d69b33acb
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_firmware.c
@@ -0,0 +1,1023 @@
1/**************************************************************************************************
2 * Procedure: Init boot code/firmware code/data session
3 *
4 * Description: This routine will intialize firmware. If any error occurs during the initialization
5 * process, the routine shall terminate immediately and return fail.
6 * NIC driver should call NdisOpenFile only from MiniportInitialize.
7 *
8 * Arguments: The pointer of the adapter
9
10 * Returns:
11 * NDIS_STATUS_FAILURE - the following initialization process should be terminated
12 * NDIS_STATUS_SUCCESS - if firmware initialization process success
13**************************************************************************************************/
14//#include "ieee80211.h"
15#if defined(RTL8192SE)||defined(RTL8192SU)
16#include "r8192U.h"
17#include "r8192S_firmware.h"
18#include <linux/unistd.h>
19
20#ifdef RTL8192SU
21#include "r8192S_hw.h"
22#include "r8192SU_HWImg.h"
23//#include "r8192S_FwImgDTM.h"
24#else
25//#include "r8192U_hw.h"
26#include "r8192xU_firmware_img.h"
27#endif
28
29#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
30#include <linux/firmware.h>
31#endif
32
33#define byte(x,n) ( (x >> (8 * n)) & 0xff )
34
35//
36// Description: This routine will intialize firmware. If any error occurs during the initialization
37// process, the routine shall terminate immediately and return fail.
38//
39// Arguments: The pointer of the adapter
40// Code address (Virtual address, should fill descriptor with physical address)
41// Code size
42// Created by Roger, 2008.04.10.
43//
44bool FirmwareDownloadCode(struct net_device *dev, u8 * code_virtual_address,u32 buffer_len)
45{
46 struct r8192_priv *priv = ieee80211_priv(dev);
47 bool rt_status = true;
48 u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE; //Fragmentation might be required in 90/92 but not in 92S
49 u16 frag_length, frag_offset = 0;
50 struct sk_buff *skb;
51 unsigned char *seg_ptr;
52 cb_desc *tcb_desc;
53 u8 bLastIniPkt = 0;
54 u16 ExtraDescOffset = 0;
55
56#ifdef RTL8192SE
57 fw_SetRQPN(dev); // For 92SE only
58#endif
59
60 RT_TRACE(COMP_FIRMWARE, "--->FirmwareDownloadCode()\n" );
61
62 //MAX_TRANSMIT_BUFFER_SIZE
63 if(buffer_len >= MAX_FIRMWARE_CODE_SIZE-USB_HWDESC_HEADER_LEN)
64 {
65 RT_TRACE(COMP_ERR, "Size over MAX_FIRMWARE_CODE_SIZE! \n");
66 goto cmdsend_downloadcode_fail;
67 }
68
69 ExtraDescOffset = USB_HWDESC_HEADER_LEN;
70
71 do {
72 if((buffer_len-frag_offset) > frag_threshold)
73 {
74 frag_length = frag_threshold + ExtraDescOffset;
75 }
76 else
77 {
78 frag_length = (u16)(buffer_len - frag_offset + ExtraDescOffset);
79 bLastIniPkt = 1;
80 }
81
82 /* Allocate skb buffer to contain firmware info and tx descriptor info. */
83 skb = dev_alloc_skb(frag_length);
84 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
85
86 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
87 tcb_desc->queue_index = TXCMD_QUEUE;
88 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
89 tcb_desc->bLastIniPkt = bLastIniPkt;
90
91 skb_reserve(skb, ExtraDescOffset);
92 seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length-ExtraDescOffset));
93 memcpy(seg_ptr, code_virtual_address+frag_offset, (u32)(frag_length-ExtraDescOffset));
94
95 tcb_desc->txbuf_size= frag_length;
96
97 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
98 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
99 (priv->ieee80211->queue_stop) )
100 {
101 RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
102 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
103 }
104 else
105 {
106 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
107 }
108
109 frag_offset += (frag_length - ExtraDescOffset);
110
111 }while(frag_offset < buffer_len);
112
113 return rt_status ;
114
115
116cmdsend_downloadcode_fail:
117 rt_status = false;
118 RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n");
119 return rt_status;
120
121}
122
123#ifdef RTL8192SE
124static void fw_SetRQPN(struct net_device *dev)
125{
126 // Only for 92SE HW bug, we have to set RAPN before every FW download
127 // We can remove the code later.
128 write_nic_dword(dev, RQPN, 0xffffffff);
129 write_nic_dword(dev, RQPN+4, 0xffffffff);
130 write_nic_byte(dev, RQPN+8, 0xff);
131 write_nic_byte(dev, RQPN+0xB, 0x80);
132 //#if ((HAL_CODE_BASE == RTL8192_S) && (PLATFORM != PLATFORM_WINDOWS_USB))
133
134} /* fw_SetRQPN */
135#endif
136
137RT_STATUS
138FirmwareEnableCPU(struct net_device *dev)
139{
140
141 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
142 u8 tmpU1b, CPUStatus = 0;
143 u16 tmpU2b;
144 u32 iCheckTime = 200;
145
146 RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" );
147#ifdef RTL8192SE
148 fw_SetRQPN(dev); // For 92SE only
149#endif
150 // Enable CPU.
151 tmpU1b = read_nic_byte(dev, SYS_CLKR);
152 write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL)); //AFE source
153
154 tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
155 write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));
156
157 //Polling IMEM Ready after CPU has refilled.
158 do
159 {
160 CPUStatus = read_nic_byte(dev, TCR);
161 if(CPUStatus& IMEM_RDY)
162 {
163 RT_TRACE(COMP_FIRMWARE, "IMEM Ready after CPU has refilled.\n");
164 break;
165 }
166
167 //usleep(100);
168 udelay(100);
169 }while(iCheckTime--);
170
171 if(!(CPUStatus & IMEM_RDY))
172 return RT_STATUS_FAILURE;
173
174 RT_TRACE(COMP_FIRMWARE, "<--FirmwareEnableCPU(): rtStatus(%#x)\n", rtStatus);
175 return rtStatus;
176}
177
178FIRMWARE_8192S_STATUS
179FirmwareGetNextStatus(FIRMWARE_8192S_STATUS FWCurrentStatus)
180{
181 FIRMWARE_8192S_STATUS NextFWStatus = 0;
182
183 switch(FWCurrentStatus)
184 {
185 case FW_STATUS_INIT:
186 NextFWStatus = FW_STATUS_LOAD_IMEM;
187 break;
188
189 case FW_STATUS_LOAD_IMEM:
190 NextFWStatus = FW_STATUS_LOAD_EMEM;
191 break;
192
193 case FW_STATUS_LOAD_EMEM:
194 NextFWStatus = FW_STATUS_LOAD_DMEM;
195 break;
196
197 case FW_STATUS_LOAD_DMEM:
198 NextFWStatus = FW_STATUS_READY;
199 break;
200
201 default:
202 RT_TRACE(COMP_ERR,"Invalid FW Status(%#x)!!\n", FWCurrentStatus);
203 break;
204 }
205 return NextFWStatus;
206}
207
208bool
209FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
210{
211 struct r8192_priv *priv = ieee80211_priv(dev);
212 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
213 rt_firmware *pFirmware = priv->pFirmware;
214 int PollingCnt = 1000;
215 //u8 tmpU1b, CPUStatus = 0;
216 u8 CPUStatus = 0;
217 u32 tmpU4b;
218 //bool bOrgIMREnable;
219
220 RT_TRACE(COMP_FIRMWARE, "--->FirmwareCheckReady(): LoadStaus(%d),", LoadFWStatus);
221
222 pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus;
223 if( LoadFWStatus == FW_STATUS_LOAD_IMEM)
224 {
225 do
226 {//Polling IMEM code done.
227 CPUStatus = read_nic_byte(dev, TCR);
228 if(CPUStatus& IMEM_CODE_DONE)
229 break;
230
231 udelay(5);
232 }while(PollingCnt--);
233 if(!(CPUStatus & IMEM_CHK_RPT) || PollingCnt <= 0)
234 {
235 RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus);
236 return false;
237 }
238 }
239 else if( LoadFWStatus == FW_STATUS_LOAD_EMEM)
240 {//Check Put Code OK and Turn On CPU
241 do
242 {//Polling EMEM code done.
243 CPUStatus = read_nic_byte(dev, TCR);
244 if(CPUStatus& EMEM_CODE_DONE)
245 break;
246
247 udelay(5);
248 }while(PollingCnt--);
249 if(!(CPUStatus & EMEM_CHK_RPT))
250 {
251 RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus);
252 return false;
253 }
254
255 // Turn On CPU
256 rtStatus = FirmwareEnableCPU(dev);
257 if(rtStatus != RT_STATUS_SUCCESS)
258 {
259 RT_TRACE(COMP_ERR, "Enable CPU fail ! \n" );
260 return false;
261 }
262 }
263 else if( LoadFWStatus == FW_STATUS_LOAD_DMEM)
264 {
265 do
266 {//Polling DMEM code done
267 CPUStatus = read_nic_byte(dev, TCR);
268 if(CPUStatus& DMEM_CODE_DONE)
269 break;
270
271 udelay(5);
272 }while(PollingCnt--);
273
274 if(!(CPUStatus & DMEM_CODE_DONE))
275 {
276 RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus);
277 return false;
278 }
279
280 RT_TRACE(COMP_FIRMWARE, "DMEM code download success, CPUStatus(%#x)\n", CPUStatus);
281
282// PollingCnt = 100; // Set polling cycle to 10ms.
283 PollingCnt = 10000; // Set polling cycle to 10ms.
284
285 do
286 {//Polling Load Firmware ready
287 CPUStatus = read_nic_byte(dev, TCR);
288 if(CPUStatus & FWRDY)
289 break;
290
291 udelay(100);
292 }while(PollingCnt--);
293
294 RT_TRACE(COMP_FIRMWARE, "Polling Load Firmware ready, CPUStatus(%x)\n", CPUStatus);
295
296 //if(!(CPUStatus & LOAD_FW_READY))
297 //if((CPUStatus & LOAD_FW_READY) != 0xff)
298 if((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY)
299 {
300 RT_TRACE(COMP_ERR, "Polling Load Firmware ready fail ! CPUStatus(%x)\n", CPUStatus);
301 return false;
302 }
303
304 //
305 // <Roger_Notes> USB interface will update reserved followings parameters later!!
306 // 2008.08.28.
307 //
308#ifdef RTL8192SE
309 //write_nic_dword(dev, RQPN, 0x10101010);
310 //write_nic_byte(dev, 0xAB, 0x80);
311#endif
312
313 //
314 // <Roger_Notes> If right here, we can set TCR/RCR to desired value
315 // and config MAC lookback mode to normal mode. 2008.08.28.
316 //
317 tmpU4b = read_nic_dword(dev,TCR);
318 write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV)));
319
320 tmpU4b = read_nic_dword(dev, RCR);
321 write_nic_dword(dev, RCR,
322 (tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC));
323
324 RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current RCR settings(%#x)\n", tmpU4b);
325
326#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION) ||defined (RTL8192SU_ASIC_VERIFICATION))
327#ifdef NOT_YET //YJ,TMP
328 priv->TransmitConfig = read_nic_dword(dev, TCR);
329 RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current TCR settings(%x)\n", priv->TransmitConfig);
330 pHalData->FwRsvdTxPageCfg = read_nic_byte(dev, FW_RSVD_PG_CRTL);
331#endif
332#endif
333
334 // Set to normal mode.
335 write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL);
336
337 }
338
339 RT_TRACE(COMP_FIRMWARE, "<---FirmwareCheckReady(): LoadFWStatus(%d), rtStatus(%x)\n", LoadFWStatus, rtStatus);
340 return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
341}
342
343//
344// Description: This routine is to update the RF types in FW header partially.
345//
346// Created by Roger, 2008.12.24.
347//
348u8 FirmwareHeaderMapRfType(struct net_device *dev)
349{
350 struct r8192_priv *priv = ieee80211_priv(dev);
351 switch(priv->rf_type)
352 {
353 case RF_1T1R: return 0x11;
354 case RF_1T2R: return 0x12;
355 case RF_2T2R: return 0x22;
356 case RF_2T2R_GREEN: return 0x92;
357 default:
358 RT_TRACE(COMP_INIT, "Unknown RF type(%x)\n",priv->rf_type);
359 break;
360 }
361 return 0x22;
362}
363
364
365//
366// Description: This routine is to update the private parts in FW header partially.
367//
368// Created by Roger, 2008.12.18.
369//
370void FirmwareHeaderPriveUpdate(struct net_device *dev, PRT_8192S_FIRMWARE_PRIV pFwPriv)
371{
372 struct r8192_priv *priv = ieee80211_priv(dev);
373#ifdef RTL8192SU
374 // Update USB endpoint number for RQPN settings.
375 pFwPriv->usb_ep_num = priv->EEPROMUsbEndPointNumber; // endpoint number: 4, 6 and 11.
376 RT_TRACE(COMP_INIT, "FirmwarePriveUpdate(): usb_ep_num(%#x)\n", pFwPriv->usb_ep_num);
377#endif
378
379 // Update RF types for RATR settings.
380 pFwPriv->rf_config = FirmwareHeaderMapRfType(dev);
381}
382
383
384
385bool FirmwareDownload92S(struct net_device *dev)
386{
387 struct r8192_priv *priv = ieee80211_priv(dev);
388 bool rtStatus = true;
389 const char *pFwImageFileName[1] = {"RTL8192SU/rtl8192sfw.bin"};
390 u8 *pucMappedFile = NULL;
391 u32 ulFileLength, ulInitStep = 0;
392 u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
393 rt_firmware *pFirmware = priv->pFirmware;
394 u8 FwStatus = FW_STATUS_INIT;
395 PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
396 PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL;
397 int rc;
398 const struct firmware *fw_entry;
399 u32 file_length = 0;
400
401 pFirmware->FWStatus = FW_STATUS_INIT;
402
403 RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n");
404
405 //3//
406 //3 //<1> Open Image file, and map file to contineous memory if open file success.
407 //3 // or read image file from array. Default load from BIN file
408 //3//
409#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
410 priv->firmware_source = FW_SOURCE_HEADER_FILE;
411#else
412 priv->firmware_source = FW_SOURCE_IMG_FILE;// We should decided by Reg.
413#endif
414
415 switch( priv->firmware_source )
416 {
417 case FW_SOURCE_IMG_FILE:
418#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
419 if(pFirmware->szFwTmpBufferLen == 0)
420 {
421
422 rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->udev->dev);//===>1
423 if(rc < 0 ) {
424 RT_TRACE(COMP_ERR, "request firmware fail!\n");
425 goto DownloadFirmware_Fail;
426 }
427
428 if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer))
429 {
430 RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
431 release_firmware(fw_entry);
432 goto DownloadFirmware_Fail;
433 }
434
435 memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size);
436 pFirmware->szFwTmpBufferLen = fw_entry->size;
437 release_firmware(fw_entry);
438
439 pucMappedFile = pFirmware->szFwTmpBuffer;
440 file_length = pFirmware->szFwTmpBufferLen;
441
442 //Retrieve FW header.
443 pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
444 pFwHdr = pFirmware->pFwHeader;
445 RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
446 pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
447 pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
448 pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
449 if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
450 {
451 RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\
452 __FUNCTION__);
453 goto DownloadFirmware_Fail;
454 } else {
455 pucMappedFile+=FwHdrSize;
456
457 //Retrieve IMEM image.
458 memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
459 pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
460 }
461
462 if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
463 {
464 RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\
465 __FUNCTION__);
466 goto DownloadFirmware_Fail;
467 } else {
468 pucMappedFile += pFirmware->FwIMEMLen;
469
470 /* Retriecve EMEM image */
471 memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);//===>6
472 pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
473 }
474
475
476 }
477#endif
478 break;
479
480 case FW_SOURCE_HEADER_FILE:
481#if 1
482#define Rtl819XFwImageArray Rtl8192SUFwImgArray
483 //2008.11.10 Add by tynli.
484 pucMappedFile = Rtl819XFwImageArray;
485 ulFileLength = ImgArrayLength;
486
487 RT_TRACE(COMP_INIT,"Fw download from header.\n");
488 /* Retrieve FW header*/
489 pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
490 pFwHdr = pFirmware->pFwHeader;
491 RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
492 pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
493 pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
494 pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
495
496 if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
497 {
498 printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n");
499 goto DownloadFirmware_Fail;
500 } else {
501 pucMappedFile+=FwHdrSize;
502 //Retrieve IMEM image.
503 memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
504 pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
505 }
506
507 if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
508 {
509 printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n");
510 goto DownloadFirmware_Fail;
511 } else {
512 pucMappedFile+= pFirmware->FwIMEMLen;
513
514 //Retriecve EMEM image.
515 memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
516 pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
517 }
518#endif
519 break;
520 default:
521 break;
522 }
523
524 FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
525 while(FwStatus!= FW_STATUS_READY)
526 {
527 // Image buffer redirection.
528 switch(FwStatus)
529 {
530 case FW_STATUS_LOAD_IMEM:
531 pucMappedFile = pFirmware->FwIMEM;
532 ulFileLength = pFirmware->FwIMEMLen;
533 break;
534
535 case FW_STATUS_LOAD_EMEM:
536 pucMappedFile = pFirmware->FwEMEM;
537 ulFileLength = pFirmware->FwEMEMLen;
538 break;
539
540 case FW_STATUS_LOAD_DMEM:
541 /* <Roger_Notes> Partial update the content of header private. 2008.12.18 */
542 pFwHdr = pFirmware->pFwHeader;
543 pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv;
544 FirmwareHeaderPriveUpdate(dev, pFwPriv);
545 pucMappedFile = (u8*)(pFirmware->pFwHeader)+RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
546 ulFileLength = FwHdrSize-RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
547 break;
548
549 default:
550 RT_TRACE(COMP_ERR, "Unexpected Download step!!\n");
551 goto DownloadFirmware_Fail;
552 break;
553 }
554
555 //3//
556 //3// <2> Download image file
557 //3 //
558 rtStatus = FirmwareDownloadCode(dev, pucMappedFile, ulFileLength);
559
560 if(rtStatus != true)
561 {
562 RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n" );
563 goto DownloadFirmware_Fail;
564 }
565
566 //3//
567 //3// <3> Check whether load FW process is ready
568 //3 //
569 rtStatus = FirmwareCheckReady(dev, FwStatus);
570
571 if(rtStatus != true)
572 {
573 RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n");
574 goto DownloadFirmware_Fail;
575 }
576
577 FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
578 }
579
580 RT_TRACE(COMP_FIRMWARE, "Firmware Download Success!!\n");
581 return rtStatus;
582
583 DownloadFirmware_Fail:
584 RT_TRACE(COMP_ERR, "Firmware Download Fail!!%x\n",read_nic_word(dev, TCR));
585 rtStatus = false;
586 return rtStatus;
587}
588#else
589void firmware_init_param(struct net_device *dev)
590{
591 struct r8192_priv *priv = ieee80211_priv(dev);
592 rt_firmware *pfirmware = priv->pFirmware;
593
594 pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
595}
596
597/*
598 * segment the img and use the ptr and length to remember info on each segment
599 *
600 */
601bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len)
602{
603 struct r8192_priv *priv = ieee80211_priv(dev);
604 bool rt_status = true;
605 //u16 frag_threshold;
606 u16 frag_length, frag_offset = 0;
607 //u16 total_size;
608 int i;
609
610 //rt_firmware *pfirmware = priv->pFirmware;
611 struct sk_buff *skb;
612 unsigned char *seg_ptr;
613 cb_desc *tcb_desc;
614 u8 bLastIniPkt;
615#ifdef RTL8192SE
616 fw_SetRQPN(dev); // For 92SE only
617#endif
618
619#ifndef RTL8192SU
620 if(buffer_len >= 64000-USB_HWDESC_HEADER_LEN)
621 {
622 return rt_status;
623 }
624 firmware_init_param(dev);
625 //Fragmentation might be required
626 frag_threshold = pfirmware->cmdpacket_frag_thresold;
627#endif
628
629 do {
630#ifndef RTL8192SU
631 if((buffer_len - frag_offset) > frag_threshold) {
632 frag_length = frag_threshold ;
633 bLastIniPkt = 0;
634
635 } else
636#endif
637 {
638 frag_length = buffer_len - frag_offset;
639 bLastIniPkt = 1;
640
641 }
642
643 /* Allocate skb buffer to contain firmware info and tx descriptor info
644 * add 4 to avoid packet appending overflow.
645 * */
646 #ifdef RTL8192U
647 skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
648 #else
649 skb = dev_alloc_skb(frag_length + 4);
650 #endif
651 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
652 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
653 tcb_desc->queue_index = TXCMD_QUEUE;
654 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
655 tcb_desc->bLastIniPkt = bLastIniPkt;
656
657 #ifdef RTL8192U
658 skb_reserve(skb, USB_HWDESC_HEADER_LEN);
659 #endif
660 seg_ptr = skb->data;
661 /*
662 * Transform from little endian to big endian
663 * and pending zero
664 */
665 for(i=0 ; i < frag_length; i+=4) {
666 *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0;
667 *seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0;
668 *seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0;
669 *seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0;
670 }
671 tcb_desc->txbuf_size= (u16)i;
672 skb_put(skb, i);
673
674 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
675 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
676 (priv->ieee80211->queue_stop) ) {
677 RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
678 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
679 } else {
680 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
681 }
682
683 code_virtual_address += frag_length;
684 frag_offset += frag_length;
685
686 }while(frag_offset < buffer_len);
687
688 return rt_status;
689
690#if 0
691cmdsend_downloadcode_fail:
692 rt_status = false;
693 RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n");
694 return rt_status;
695#endif
696}
697
698bool
699fwSendNullPacket(
700 struct net_device *dev,
701 u32 Length
702)
703{
704 bool rtStatus = true;
705 struct r8192_priv *priv = ieee80211_priv(dev);
706 struct sk_buff *skb;
707 cb_desc *tcb_desc;
708 unsigned char *ptr_buf;
709 bool bLastInitPacket = false;
710
711 //PlatformAcquireSpinLock(dev, RT_TX_SPINLOCK);
712
713 //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ)
714 skb = dev_alloc_skb(Length+ 4);
715 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
716 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
717 tcb_desc->queue_index = TXCMD_QUEUE;
718 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
719 tcb_desc->bLastIniPkt = bLastInitPacket;
720 ptr_buf = skb_put(skb, Length);
721 memset(ptr_buf,0,Length);
722 tcb_desc->txbuf_size= (u16)Length;
723
724 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
725 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
726 (priv->ieee80211->queue_stop) ) {
727 RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n");
728 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
729 } else {
730 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
731 }
732
733 //PlatformReleaseSpinLock(dev, RT_TX_SPINLOCK);
734 return rtStatus;
735}
736
737//-----------------------------------------------------------------------------
738// Procedure: Check whether main code is download OK. If OK, turn on CPU
739//
740// Description: CPU register locates in different page against general register.
741// Switch to CPU register in the begin and switch back before return
742//
743//
744// Arguments: The pointer of the dev
745//
746// Returns:
747// NDIS_STATUS_FAILURE - the following initialization process should be terminated
748// NDIS_STATUS_SUCCESS - if firmware initialization process success
749//-----------------------------------------------------------------------------
750bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
751{
752 bool rt_status = true;
753 int check_putcodeOK_time = 200000, check_bootOk_time = 200000;
754 u32 CPU_status = 0;
755
756 /* Check whether put code OK */
757 do {
758 CPU_status = read_nic_dword(dev, CPU_GEN);
759
760 if(CPU_status&CPU_GEN_PUT_CODE_OK)
761 break;
762
763 }while(check_putcodeOK_time--);
764
765 if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) {
766 RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n");
767 goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
768 } else {
769 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n");
770 }
771
772 /* Turn On CPU */
773 CPU_status = read_nic_dword(dev, CPU_GEN);
774 write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
775 mdelay(1000);
776
777 /* Check whether CPU boot OK */
778 do {
779 CPU_status = read_nic_dword(dev, CPU_GEN);
780
781 if(CPU_status&CPU_GEN_BOOT_RDY)
782 break;
783 }while(check_bootOk_time--);
784
785 if(!(CPU_status&CPU_GEN_BOOT_RDY)) {
786 goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
787 } else {
788 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n");
789 }
790
791 return rt_status;
792
793CPUCheckMainCodeOKAndTurnOnCPU_Fail:
794 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
795 rt_status = FALSE;
796 return rt_status;
797}
798
799bool CPUcheck_firmware_ready(struct net_device *dev)
800{
801
802 bool rt_status = true;
803 int check_time = 200000;
804 u32 CPU_status = 0;
805
806 /* Check Firmware Ready */
807 do {
808 CPU_status = read_nic_dword(dev, CPU_GEN);
809
810 if(CPU_status&CPU_GEN_FIRM_RDY)
811 break;
812
813 }while(check_time--);
814
815 if(!(CPU_status&CPU_GEN_FIRM_RDY))
816 goto CPUCheckFirmwareReady_Fail;
817 else
818 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n");
819
820 return rt_status;
821
822CPUCheckFirmwareReady_Fail:
823 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
824 rt_status = false;
825 return rt_status;
826
827}
828
829bool init_firmware(struct net_device *dev)
830{
831 struct r8192_priv *priv = ieee80211_priv(dev);
832 bool rt_status = TRUE;
833
834 u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0],
835 &rtl8190_fwmain_array[0],
836 &rtl8190_fwdata_array[0]};
837
838 u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array),
839 sizeof(rtl8190_fwmain_array),
840 sizeof(rtl8190_fwdata_array)};
841 u32 file_length = 0;
842 u8 *mapped_file = NULL;
843 u32 init_step = 0;
844 opt_rst_type_e rst_opt = OPT_SYSTEM_RESET;
845 firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
846
847 rt_firmware *pfirmware = priv->pFirmware;
848 const struct firmware *fw_entry;
849 const char *fw_name[3] = { "RTL8192U/boot.img",
850 "RTL8192U/main.img",
851 "RTL8192U/data.img"};
852 int rc;
853
854 RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n");
855
856 if (pfirmware->firmware_status == FW_STATUS_0_INIT ) {
857 /* it is called by reset */
858 rst_opt = OPT_SYSTEM_RESET;
859 starting_state = FW_INIT_STEP0_BOOT;
860 // TODO: system reset
861
862 }else if(pfirmware->firmware_status == FW_STATUS_5_READY) {
863 /* it is called by Initialize */
864 rst_opt = OPT_FIRMWARE_RESET;
865 starting_state = FW_INIT_STEP2_DATA;
866 }else {
867 RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n");
868 }
869
870 /*
871 * Download boot, main, and data image for System reset.
872 * Download data image for firmware reseta
873 */
874#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
875 priv->firmware_source = FW_SOURCE_HEADER_FILE;
876#else
877 priv->firmware_source = FW_SOURCE_IMG_FILE;
878#endif
879 for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) {
880 /*
881 * Open Image file, and map file to contineous memory if open file success.
882 * or read image file from array. Default load from IMG file
883 */
884 if(rst_opt == OPT_SYSTEM_RESET) {
885 switch(priv->firmware_source) {
886 case FW_SOURCE_IMG_FILE:
887 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
888 rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev);
889 if(rc < 0 ) {
890 RT_TRACE(COMP_ERR, "request firmware fail!\n");
891 goto download_firmware_fail;
892 }
893
894 if(fw_entry->size > sizeof(pfirmware->firmware_buf)) {
895 RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
896 goto download_firmware_fail;
897 }
898
899 if(init_step != FW_INIT_STEP1_MAIN) {
900 memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size);
901 mapped_file = pfirmware->firmware_buf;
902 file_length = fw_entry->size;
903 } else {
904 #ifdef RTL8190P
905 memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size);
906 mapped_file = pfirmware->firmware_buf;
907 file_length = fw_entry->size;
908 #else
909 memset(pfirmware->firmware_buf,0,128);
910 memcpy(&pfirmware->firmware_buf[128],fw_entry->data,fw_entry->size);
911 mapped_file = pfirmware->firmware_buf;
912 file_length = fw_entry->size + 128;
913 #endif
914 }
915 pfirmware->firmware_buf_size = file_length;
916 #endif
917 break;
918
919 case FW_SOURCE_HEADER_FILE:
920 mapped_file = firmware_img_buf[init_step];
921 file_length = firmware_img_len[init_step];
922 if(init_step == FW_INIT_STEP2_DATA) {
923 memcpy(pfirmware->firmware_buf, mapped_file, file_length);
924 pfirmware->firmware_buf_size = file_length;
925 }
926 break;
927
928 default:
929 break;
930 }
931
932
933 }else if(rst_opt == OPT_FIRMWARE_RESET ) {
934 /* we only need to download data.img here */
935 mapped_file = pfirmware->firmware_buf;
936 file_length = pfirmware->firmware_buf_size;
937 }
938
939 /* Download image file */
940 /* The firmware download process is just as following,
941 * 1. that is each packet will be segmented and inserted to the wait queue.
942 * 2. each packet segment will be put in the skb_buff packet.
943 * 3. each skb_buff packet data content will already include the firmware info
944 * and Tx descriptor info
945 * */
946 rt_status = fw_download_code(dev,mapped_file,file_length);
947 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
948 if(rst_opt == OPT_SYSTEM_RESET) {
949 release_firmware(fw_entry);
950 }
951 #endif
952
953 if(rt_status != TRUE) {
954 goto download_firmware_fail;
955 }
956
957 switch(init_step) {
958 case FW_INIT_STEP0_BOOT:
959 /* Download boot
960 * initialize command descriptor.
961 * will set polling bit when firmware code is also configured
962 */
963 pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE;
964#ifdef RTL8190P
965 // To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet
966 rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET);
967 if(rt_status != true)
968 {
969 RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n");
970 goto download_firmware_fail;
971 }
972#endif
973 //mdelay(1000);
974 /*
975 * To initialize IMEM, CPU move code from 0x80000080,
976 * hence, we send 0x80 byte packet
977 */
978 break;
979
980 case FW_INIT_STEP1_MAIN:
981 /* Download firmware code. Wait until Boot Ready and Turn on CPU */
982 pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE;
983
984 /* Check Put Code OK and Turn On CPU */
985 rt_status = CPUcheck_maincodeok_turnonCPU(dev);
986 if(rt_status != TRUE) {
987 RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n");
988 goto download_firmware_fail;
989 }
990
991 pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU;
992 break;
993
994 case FW_INIT_STEP2_DATA:
995 /* download initial data code */
996 pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE;
997 mdelay(1);
998
999 rt_status = CPUcheck_firmware_ready(dev);
1000 if(rt_status != TRUE) {
1001 RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status);
1002 goto download_firmware_fail;
1003 }
1004
1005 /* wait until data code is initialized ready.*/
1006 pfirmware->firmware_status = FW_STATUS_5_READY;
1007 break;
1008 }
1009 }
1010
1011 RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n");
1012 //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n"));
1013
1014 return rt_status;
1015
1016download_firmware_fail:
1017 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
1018 rt_status = FALSE;
1019 return rt_status;
1020
1021}
1022#endif
1023
diff --git a/drivers/staging/rtl8192su/r8192S_firmware.h b/drivers/staging/rtl8192su/r8192S_firmware.h
new file mode 100644
index 00000000000..047f8ae4474
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_firmware.h
@@ -0,0 +1,212 @@
1#ifndef __INC_FIRMWARE_H
2#define __INC_FIRMWARE_H
3
4
5//#define RTL8190_CPU_START_OFFSET 0x80
6/* TODO: this definition is TBD */
7//#define USB_HWDESC_HEADER_LEN 0
8
9/* It should be double word alignment */
10//#if DEV_BUS_TYPE==PCI_INTERFACE
11//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
12//#else
13//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
14//#endif
15
16//typedef enum _firmware_init_step{
17// FW_INIT_STEP0_BOOT = 0,
18// FW_INIT_STEP1_MAIN = 1,
19// FW_INIT_STEP2_DATA = 2,
20//}firmware_init_step_e;
21
22//typedef enum _DESC_PACKET_TYPE{
23// DESC_PACKET_TYPE_INIT = 0,
24// DESC_PACKET_TYPE_NORMAL = 1,
25//}DESC_PACKET_TYPE;
26#define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K
27
28
29#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
30#define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
31#define RTL8190_CPU_START_OFFSET 0x80
32
33#ifdef RTL8192SE
34//It should be double word alignment
35#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
36#else
37#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
38#endif
39
40//typedef enum _DESC_PACKET_TYPE{
41// DESC_PACKET_TYPE_INIT = 0,
42// DESC_PACKET_TYPE_NORMAL = 1,
43//}DESC_PACKET_TYPE;
44
45// Forward declaration.
46//typedef struct _ADAPTER ADAPTER, *PADAPTER;
47#ifdef RTL8192S
48typedef enum _firmware_init_step{
49 FW_INIT_STEP0_IMEM = 0,
50 FW_INIT_STEP1_MAIN = 1,
51 FW_INIT_STEP2_DATA = 2,
52}firmware_init_step_e;
53#else
54typedef enum _firmware_init_step{
55 FW_INIT_STEP0_BOOT = 0,
56 FW_INIT_STEP1_MAIN = 1,
57 FW_INIT_STEP2_DATA = 2,
58}firmware_init_step_e;
59#endif
60
61/* due to rtl8192 firmware */
62typedef enum _desc_packet_type_e{
63 DESC_PACKET_TYPE_INIT = 0,
64 DESC_PACKET_TYPE_NORMAL = 1,
65}desc_packet_type_e;
66
67typedef enum _firmware_source{
68 FW_SOURCE_IMG_FILE = 0,
69 FW_SOURCE_HEADER_FILE = 1,
70}firmware_source_e, *pfirmware_source_e;
71
72
73typedef enum _opt_rst_type{
74 OPT_SYSTEM_RESET = 0,
75 OPT_FIRMWARE_RESET = 1,
76}opt_rst_type_e;
77
78/*typedef enum _FIRMWARE_STATUS{
79 FW_STATUS_0_INIT = 0,
80 FW_STATUS_1_MOVE_BOOT_CODE = 1,
81 FW_STATUS_2_MOVE_MAIN_CODE = 2,
82 FW_STATUS_3_TURNON_CPU = 3,
83 FW_STATUS_4_MOVE_DATA_CODE = 4,
84 FW_STATUS_5_READY = 5,
85}FIRMWARE_STATUS;
86*/
87//--------------------------------------------------------------------------------
88// RTL8192S Firmware related, Revised by Roger, 2008.12.18.
89//--------------------------------------------------------------------------------
90typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
91
92 //--- long word 0 ----
93 u8 signature_0; //0x12: CE product, 0x92: IT product
94 u8 signature_1; //0x87: CE product, 0x81: IT product
95 u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO
96 u8 chip_version; //the same value as reigster value
97 u8 customer_ID_0; //customer ID low byte
98 u8 customer_ID_1; //customer ID high byte
99 u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
100 u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP
101
102 //--- long word 1 ----
103 u8 regulatory_class_0; //regulatory class bit map 0
104 u8 regulatory_class_1; //regulatory class bit map 1
105 u8 regulatory_class_2; //regulatory class bit map 2
106 u8 regulatory_class_3; //regulatory class bit map 3
107 u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI
108 u8 def_nettype;
109 u8 rsvd010;
110 u8 rsvd011;
111
112
113 //--- long word 2 ----
114 u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK
115 u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed)
116 u8 rsvd020;
117 u8 rsvd021;
118 u8 rsvd022;
119 u8 rsvd023;
120 u8 rsvd024;
121 u8 rsvd025;
122
123 //--- long word 3 ----
124 u8 qos_en; // QoS enable
125 u8 bw_40MHz_en; // 40MHz BW enable
126 u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable
127 u8 AMPDU_en; // 11n AMPDU enable
128 u8 rate_control_offload;//FW offloads, 0: driver handles
129 u8 aggregation_offload; // FW offloads, 0: driver handles
130 u8 rsvd030;
131 u8 rsvd031;
132
133
134 //--- long word 4 ----
135 unsigned char beacon_offload; // 1. FW offloads, 0: driver handles
136 unsigned char MLME_offload; // 2. FW offloads, 0: driver handles
137 unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles
138 unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles
139 unsigned char tcp_offload; // 5. FW offloads, 0: driver handles
140 unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles
141 unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles
142 unsigned char rsvd040;
143
144 //--- long word 5 ----
145 u8 tcp_tx_frame_len_L; //tcp tx packet length low byte
146 u8 tcp_tx_frame_len_H; //tcp tx packet length high byte
147 u8 tcp_rx_frame_len_L; //tcp rx packet length low byte
148 u8 tcp_rx_frame_len_H; //tcp rx packet length high byte
149 u8 rsvd050;
150 u8 rsvd051;
151 u8 rsvd052;
152 u8 rsvd053;
153}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
154
155typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
156
157 //--- LONG WORD 0 ----
158 u16 Signature;
159 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
160 u32 DMEMSize; //define the size of boot loader
161
162
163 //--- LONG WORD 1 ----
164 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
165 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
166
167 //--- LONG WORD 2 ----
168 u32 FW_PRIV_SIZE; //define the size of DMEM variable
169 u32 Rsvd0;
170
171 //--- LONG WORD 3 ----
172 u32 Rsvd1;
173 u32 Rsvd2;
174
175 RT_8192S_FIRMWARE_PRIV FWPriv;
176
177}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
178
179#define RT_8192S_FIRMWARE_HDR_SIZE 80
180#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
181
182typedef enum _FIRMWARE_8192S_STATUS{
183 FW_STATUS_INIT = 0,
184 FW_STATUS_LOAD_IMEM = 1,
185 FW_STATUS_LOAD_EMEM = 2,
186 FW_STATUS_LOAD_DMEM = 3,
187 FW_STATUS_READY = 4,
188}FIRMWARE_8192S_STATUS;
189
190#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
191
192typedef struct _rt_firmware{
193 firmware_source_e eFWSource;
194 PRT_8192S_FIRMWARE_HDR pFwHeader;
195 FIRMWARE_8192S_STATUS FWStatus;
196 u16 FirmwareVersion;
197 u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
198 u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
199 u32 FwIMEMLen;
200 u32 FwEMEMLen;
201 u8 szFwTmpBuffer[164000];
202 u32 szFwTmpBufferLen;
203 u16 CmdPacketFragThresold;
204}rt_firmware, *prt_firmware;
205
206//typedef struct _RT_FIRMWARE_INFO_8192SU{
207// u8 szInfo[16];
208//}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU;
209bool FirmwareDownload92S(struct net_device *dev);
210
211#endif
212
diff --git a/drivers/staging/rtl8192su/r8192S_hw.h b/drivers/staging/rtl8192su/r8192S_hw.h
new file mode 100644
index 00000000000..7a3d850de0b
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_hw.h
@@ -0,0 +1,1677 @@
1/*****************************************************************************
2 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.
3 *
4 * Module: __INC_HAL8192SEREG_H
5 *
6 *
7 * Note: 1. Define Mac register address and corresponding bit mask map
8 * 2. CCX register
9 * 3. Backward compatible register with useless address.
10 * 4. Define 92SU required register address and definition.
11 *
12 *
13 * Export: Constants, macro, functions(API), global variables(None).
14 *
15 * Abbrev:
16 *
17 * History:
18 * Data Who Remark
19 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
20 * 2. Reorganize code architecture.
21 *
22 *****************************************************************************/
23#ifndef R8192S_HW
24#define R8192S_HW
25
26typedef enum _VERSION_8192S{
27 VERSION_8192S_ACUT,
28 VERSION_8192S_BCUT,
29 VERSION_8192S_CCUT
30}VERSION_8192S,*PVERSION_8192S;
31
32//#ifdef RTL8192SU
33typedef enum _VERSION_8192SUsb{
34 VERSION_8192SU_A, //A-Cut
35 VERSION_8192SU_B, //B-Cut
36 VERSION_8192SU_C, //C-Cut
37}VERSION_8192SUsb, *PVERSION_8192SUsb;
38//#else
39typedef enum _VERSION_819xU{
40 VERSION_819xU_A, // A-cut
41 VERSION_819xU_B, // B-cut
42 VERSION_819xU_C,// C-cut
43}VERSION_819xU,*PVERSION_819xU;
44//#endif
45
46/* 2007/11/15 MH Define different RF type. */
47typedef enum _RT_RF_TYPE_DEFINITION
48{
49 RF_1T2R = 0,
50 RF_2T4R,
51 RF_2T2R,
52#ifdef RTL8192SU
53 RF_1T1R,
54 RF_2T2R_GREEN,
55#endif
56 //RF_3T3R,
57 //RF_3T4R,
58 //RF_4T4R,
59 RF_819X_MAX_TYPE
60}RT_RF_TYPE_DEF_E;
61
62typedef enum _BaseBand_Config_Type{
63 BaseBand_Config_PHY_REG = 0, //Radio Path A
64 BaseBand_Config_AGC_TAB = 1, //Radio Path B
65}BaseBand_Config_Type, *PBaseBand_Config_Type;
66
67#if 0
68typedef enum _RT_RF_TYPE_819xU{
69 RF_TYPE_MIN = 0,
70 RF_8225,
71 RF_8256,
72 RF_8258,
73 RF_PSEUDO_11N = 4,
74}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
75#endif
76
77#define RTL8187_REQT_READ 0xc0
78#define RTL8187_REQT_WRITE 0x40
79#define RTL8187_REQ_GET_REGS 0x05
80#define RTL8187_REQ_SET_REGS 0x05
81
82#define MAX_TX_URB 5
83#define MAX_RX_URB 16
84
85#define R8180_MAX_RETRY 255
86//#define MAX_RX_NORMAL_URB 3
87//#define MAX_RX_COMMAND_URB 2
88#define RX_URB_SIZE 9100
89
90#define BB_ANTATTEN_CHAN14 0x0c
91#define BB_ANTENNA_B 0x40
92
93#define BB_HOST_BANG (1<<30)
94#define BB_HOST_BANG_EN (1<<2)
95#define BB_HOST_BANG_CLK (1<<1)
96#define BB_HOST_BANG_RW (1<<3)
97#define BB_HOST_BANG_DATA 1
98
99
100//============================================================
101// 8192S Regsiter bit
102//============================================================
103#define BB_GLOBAL_RESET_BIT 0x1
104
105#define CR_RST 0x10
106#define CR_RE 0x08
107#define CR_TE 0x04
108#define CR_MulRW 0x01
109
110#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
111 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
112
113#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
114#define RX_FIFO_THRESHOLD_SHIFT 13
115#define RX_FIFO_THRESHOLD_128 3
116#define RX_FIFO_THRESHOLD_256 4
117#define RX_FIFO_THRESHOLD_512 5
118#define RX_FIFO_THRESHOLD_1024 6
119#define RX_FIFO_THRESHOLD_NONE 7
120
121#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
122
123//----------------------------------------------------------------------------
124// 8190 CPU General Register (offset 0x100, 4 byte)
125//----------------------------------------------------------------------------
126#define CPU_CCK_LOOPBACK 0x00030000
127#define CPU_GEN_SYSTEM_RESET 0x00000001
128#define CPU_GEN_FIRMWARE_RESET 0x00000008
129#define CPU_GEN_BOOT_RDY 0x00000010
130#define CPU_GEN_FIRM_RDY 0x00000020
131#define CPU_GEN_PUT_CODE_OK 0x00000080
132#define CPU_GEN_BB_RST 0x00000100
133#define CPU_GEN_PWR_STB_CPU 0x00000004
134#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
135#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
136//----------------------------------------------------------------------------
137////
138//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
139////----------------------------------------------------------------------------
140#define MSR_LINK_MASK ((1<<0)|(1<<1))
141#define MSR_LINK_MANAGED 2
142#define MSR_LINK_NONE 0
143#define MSR_LINK_SHIFT 0
144#define MSR_LINK_ADHOC 1
145#define MSR_LINK_MASTER 3
146#define MSR_LINK_ENEDCA (1<<4)
147
148
149//#define Cmd9346CR_9356SEL (1<<4)
150#define EPROM_CMD_RESERVED_MASK (1<<5)
151#define EPROM_CMD_OPERATING_MODE_SHIFT 6
152#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
153#define EPROM_CMD_CONFIG 0x3
154#define EPROM_CMD_NORMAL 0
155#define EPROM_CMD_LOAD 1
156#define EPROM_CMD_PROGRAM 2
157#define EPROM_CS_SHIFT 3
158#define EPROM_CK_SHIFT 2
159#define EPROM_W_SHIFT 1
160#define EPROM_R_SHIFT 0
161
162//#define MAC0 0x000,
163//#define MAC1 0x001,
164//#define MAC2 0x002,
165//#define MAC3 0x003,
166//#define MAC4 0x004,
167//#define MAC5 0x005,
168
169//============================================================
170// 8192S Regsiter offset definition
171//============================================================
172
173//
174// MAC register 0x0 - 0x5xx
175// 1. System configuration registers.
176// 2. Command Control Registers
177// 3. MACID Setting Registers
178// 4. Timing Control Registers
179// 5. FIFO Control Registers
180// 6. Adaptive Control Registers
181// 7. EDCA Setting Registers
182// 8. WMAC, BA and CCX related Register.
183// 9. Security Control Registers
184// 10. Power Save Control Registers
185// 11. General Purpose Registers
186// 12. Host Interrupt Status Registers
187// 13. Test Mode and Debug Control Registers
188// 14. PCIE config register
189//
190
191
192//
193// 1. System Configuration Registers (Offset: 0x0000 - 0x003F)
194//
195#define SYS_ISO_CTRL 0x0000 // System Isolation Interface Control.
196#define SYS_FUNC_EN 0x0002 // System Function Enable.
197#define PMC_FSM 0x0004 // Power Sequence Control.
198#define SYS_CLKR 0x0008 // System Clock.
199#define EPROM_CMD 0x000A // 93C46/93C56 Command Register. (win CR93C46)
200#define EE_VPD 0x000C // EEPROM VPD Data.
201#define AFE_MISC 0x0010 // AFE Misc.
202#define SPS0_CTRL 0x0011 // Switching Power Supply 0 Control.
203#define SPS1_CTRL 0x0018 // Switching Power Supply 1 Control.
204#define RF_CTRL 0x001F // RF Block Control.
205#define LDOA15_CTRL 0x0020 // V15 Digital LDO Control.
206#define LDOV12D_CTRL 0x0021 // V12 Digital LDO Control.
207#define LDOHCI12_CTRL 0x0022 // V12 Digital LDO Control.
208#define LDO_USB_SDIO 0x0023 // LDO USB Control.
209#define LPLDO_CTRL 0x0024 // Low Power LDO Control.
210#define AFE_XTAL_CTRL 0x0026 // AFE Crystal Control.
211#define AFE_PLL_CTRL 0x0028 // System Function Enable.
212#define EFUSE_CTRL 0x0030 // E-Fuse Control.
213#define EFUSE_TEST 0x0034 // E-Fuse Test.
214#define PWR_DATA 0x0038 // Power on date.
215#define DBG_PORT 0x003A // MAC debug port select
216#define DPS_TIMER 0x003C // Deep Power Save Timer Register.
217#define RCLK_MON 0x003E // Retention Clock Monitor.
218
219//
220// 2. Command Control Registers (Offset: 0x0040 - 0x004F)
221//
222#define CMDR 0x0040 // MAC Command Register.
223#define TXPAUSE 0x0042 // Transmission Pause Register.
224#define LBKMD_SEL 0x0043 // Loopback Mode Select Register.
225#define TCR 0x0044 // Transmit Configuration Register
226#define RCR 0x0048 // Receive Configuration Register
227#define MSR 0x004C // Media Status register
228#define SYSF_CFG 0x004D // System Function Configuration.
229#define RX_PKY_LIMIT 0x004E // RX packet length limit
230#define MBIDCTRL 0x004F // MBSSID Control.
231
232//
233// 3. MACID Setting Registers (Offset: 0x0050 - 0x007F)
234//
235#define MACIDR 0x0050 // MAC ID Register, Offset 0x0050-0x0055
236#define MACIDR0 0x0050 // MAC ID Register, Offset 0x0050-0x0053
237#define MACIDR4 0x0054 // MAC ID Register, Offset 0x0054-0x0055
238#define BSSIDR 0x0058 // BSSID Register, Offset 0x0058-0x005D
239#define HWVID 0x005E // HW Version ID.
240#define MAR 0x0060 // Multicase Address.
241#define MBIDCAMCONTENT 0x0068 // MBSSID CAM Content.
242#define MBIDCAMCFG 0x0070 // MBSSID CAM Configuration.
243#define BUILDTIME 0x0074 // Build Time Register.
244#define BUILDUSER 0x0078 // Build User Register.
245
246// Redifine MACID register, to compatible prior ICs.
247#define IDR0 MACIDR0
248#define IDR4 MACIDR4
249
250//
251// 4. Timing Control Registers (Offset: 0x0080 - 0x009F)
252//
253#define TSFR 0x0080 // Timing Sync Function Timer Register.
254#define SLOT_TIME 0x0089 // Slot Time Register, in us.
255#define USTIME 0x008A // EDCA/TSF clock unit time us unit.
256#define SIFS_CCK 0x008C // SIFS for CCK, in us.
257#define SIFS_OFDM 0x008E // SIFS for OFDM, in us.
258#define PIFS_TIME 0x0090 // PIFS time register.
259#define ACK_TIMEOUT 0x0091 // Ack Timeout Register
260#define EIFSTR 0x0092 // EIFS time regiser.
261#define BCN_INTERVAL 0x0094 // Beacon Interval, in TU.
262#define ATIMWND 0x0096 // ATIM Window width, in TU.
263#define BCN_DRV_EARLY_INT 0x0098 // Driver Early Interrupt.
264#define BCN_DMATIME 0x009A // Beacon DMA and ATIM INT Time.
265#define BCN_ERR_THRESH 0x009C // Beacon Error Threshold.
266#define MLT 0x009D // MSDU Lifetime.
267#define RSVD_MAC_TUNE_US 0x009E // MAC Internal USE.
268
269//
270// 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F)
271//
272#define RQPN 0x00A0
273#define RQPN1 0x00A0 // Reserved Queue Page Number for BK
274#define RQPN2 0x00A1 // Reserved Queue Page Number for BE
275#define RQPN3 0x00A2 // Reserved Queue Page Number for VI
276#define RQPN4 0x00A3 // Reserved Queue Page Number for VO
277#define RQPN5 0x00A4 // Reserved Queue Page Number for HCCA
278#define RQPN6 0x00A5 // Reserved Queue Page Number for CMD
279#define RQPN7 0x00A6 // Reserved Queue Page Number for MGNT
280#define RQPN8 0x00A7 // Reserved Queue Page Number for HIGH
281#define RQPN9 0x00A8 // Reserved Queue Page Number for Beacon
282#define RQPN10 0x00A9 // Reserved Queue Page Number for Public
283#define LD_RQPN 0x00AB //
284#define RXFF_BNDY 0x00AC //
285#define RXRPT_BNDY 0x00B0 //
286#define TXPKTBUF_PGBNDY 0x00B4 //
287#define PBP 0x00B5 //
288#define RXDRVINFO_SZ 0x00B6 //
289#define TXFF_STATUS 0x00B7 //
290#define RXFF_STATUS 0x00B8 //
291#define TXFF_EMPTY_TH 0x00B9 //
292#define SDIO_RX_BLKSZ 0x00BC //
293#define RXDMA 0x00BD //
294#define RXPKT_NUM 0x00BE //
295#define C2HCMD_UDT_SIZE 0x00C0 //
296#define C2HCMD_UDT_ADDR 0x00C2 //
297#define FIFOPAGE1 0x00C4 // Available public queue page number
298#define FIFOPAGE2 0x00C8 //
299#define FIFOPAGE3 0x00CC //
300#define FIFOPAGE4 0x00D0 //
301#define FIFOPAGE5 0x00D4 //
302#define FW_RSVD_PG_CRTL 0x00D8 //
303#define RXDMA_AGG_PG_TH 0x00D9 //
304#define TXRPTFF_RDPTR 0x00E0 //
305#define TXRPTFF_WTPTR 0x00E4 //
306#define C2HFF_RDPTR 0x00E8 //FIFO Read pointer register.
307#define C2HFF_WTPTR 0x00EC //FIFO Write pointer register.
308#define RXFF0_RDPTR 0x00F0 //
309#define RXFF0_WTPTR 0x00F4 //
310#define RXFF1_RDPTR 0x00F8 //
311#define RXFF1_WTPTR 0x00FC //
312#define RXRPT0_RDPTR 0x0100 //
313#define RXRPT0_WTPTR 0x0104 //
314#define RXRPT1_RDPTR 0x0108 //
315#define RXRPT1_WTPTR 0x010C //
316#define RX0_UDT_SIZE 0x0110 //
317#define RX1PKTNUM 0x0114 //
318#define RXFILTERMAP 0x0116 //
319#define RXFILTERMAP_GP1 0x0118 //
320#define RXFILTERMAP_GP2 0x011A //
321#define RXFILTERMAP_GP3 0x011C //
322#define BCNQ_CTRL 0x0120 //
323#define MGTQ_CTRL 0x0124 //
324#define HIQ_CTRL 0x0128 //
325#define VOTID7_CTRL 0x012c //
326#define VOTID6_CTRL 0x0130 //
327#define VITID5_CTRL 0x0134 //
328#define VITID4_CTRL 0x0138 //
329#define BETID3_CTRL 0x013c //
330#define BETID0_CTRL 0x0140 //
331#define BKTID2_CTRL 0x0144 //
332#define BKTID1_CTRL 0x0148 //
333#define CMDQ_CTRL 0x014c //
334#define TXPKT_NUM_CTRL 0x0150 //
335#define TXQ_PGADD 0x0152 //
336#define TXFF_PG_NUM 0x0154 //
337#define TRXDMA_STATUS 0x0156 //
338
339//
340// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
341//
342#define INIMCS_SEL 0x0160 // Init MCSrate for 32 MACID 0x160-17f
343#define TX_RATE_REG INIMCS_SEL //Current Tx rate register
344#define INIRTSMCS_SEL 0x0180 // Init RTSMCSrate
345#define RRSR 0x0181 // Response rate setting.
346#define ARFR0 0x0184 // Auto Rate Fallback 0 Register.
347#define ARFR1 0x0188 //
348#define ARFR2 0x018C //
349#define ARFR3 0x0190 //
350#define ARFR4 0x0194 //
351#define ARFR5 0x0198 //
352#define ARFR6 0x019C //
353#define ARFR7 0x01A0 //
354#define AGGLEN_LMT_H 0x01A7 // Aggregation Length Limit for High-MCS
355#define AGGLEN_LMT_L 0x01A8 // Aggregation Length Limit for Low-MCS.
356#define DARFRC 0x01B0 // Data Auto Rate Fallback Retry Count.
357#define RARFRC 0x01B8 // Response Auto Rate Fallback Count.
358#define MCS_TXAGC 0x01C0
359#define CCK_TXAGC 0x01C8
360
361//
362// 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF)
363//
364#define EDCAPARA_VO 0x01D0 // EDCA Parameter Register for VO queue.
365#define EDCAPARA_VI 0x01D4 // EDCA Parameter Register for VI queue.
366#define EDCAPARA_BE 0x01D8 // EDCA Parameter Register for BE queue.
367#define EDCAPARA_BK 0x01DC // EDCA Parameter Register for BK queue.
368#define BCNTCFG 0x01E0 // Beacon Time Configuration Register.
369#define CWRR 0x01E2 // Contention Window Report Register.
370#define ACMAVG 0x01E4 // ACM Average Register.
371#define AcmHwCtrl 0x01E7
372#define VO_ADMTM 0x01E8 // Admission Time Register.
373#define VI_ADMTM 0x01EC
374#define BE_ADMTM 0x01F0
375#define RETRY_LIMIT 0x01F4 // Retry Limit Registers[15:8]-short, [7:0]-long
376#define SG_RATE 0x01F6 // Max MCS Rate Available Register, which we Set the hightst SG rate.
377
378//
379// 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F)
380//
381#define NAV_CTRL 0x0200
382#define BW_OPMODE 0x0203
383#define BACAMCMD 0x0204
384#define BACAMCONTENT 0x0208 // Block ACK CAM R/W Register.
385
386// Roger had defined the 0x2xx register WMAC definition
387#define LBDLY 0x0210 // Loopback Delay Register.
388#define FWDLY 0x0211 // FW Delay Register.
389#define HWPC_RX_CTRL 0x0218 // HW Packet Conversion RX Control Reg
390#define MQIR 0x0220 // Mesh Qos Type Indication Register.
391#define MAIR 0x0222 // Mesh ACK.
392#define MSIR 0x0224 // Mesh HW Security Requirement Indication Reg
393#define CLM_RESULT 0x0227 // CCA Busy Fraction(Channel Load)
394#define NHM_RPI_CNT 0x0228 // Noise Histogram Measurement (NHM) RPI Report.
395#define RXERR_RPT 0x0230 // Rx Error Report.
396#define NAV_PROT_LEN 0x0234 // NAV Protection Length.
397#define CFEND_TH 0x0236 // CF-End Threshold.
398#define AMPDU_MIN_SPACE 0x0237 // AMPDU Min Space.
399#define TXOP_STALL_CTRL 0x0238
400
401//
402// 9. Security Control Registers (Offset: 0x0240 - 0x025F)
403//
404#define RWCAM 0x0240 //IN 8190 Data Sheet is called CAMcmd
405#define WCAMI 0x0244 // Software write CAM input content
406#define RCAMO 0x0248 // Software read/write CAM config
407#define CAMDBG 0x024C
408#define SECR 0x0250 //Security Configuration Register
409
410//
411// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF)
412//
413#define WOW_CTRL 0x0260 //Wake On WLAN Control.
414#define PSSTATUS 0x0261 // Power Save Status.
415#define PSSWITCH 0x0262 // Power Save Switch.
416#define MIMOPS_WAIT_PERIOD 0x0263
417#define LPNAV_CTRL 0x0264
418#define WFM0 0x0270 // Wakeup Frame Mask.
419#define WFM1 0x0280 //
420#define WFM2 0x0290 //
421#define WFM3 0x02A0 //
422#define WFM4 0x02B0 //
423#define WFM5 0x02C0 // FW Control register.
424#define WFCRC 0x02D0 // Wakeup Frame CRC.
425#define RPWM 0x02DC // Host Request Power Mode.
426#define CPWM 0x02DD // Current Power Mode.
427#define FW_RPT_REG 0x02c4
428
429//
430// 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)
431//
432#define PSTIME 0x02E0 // Power Save Timer Register
433#define TIMER0 0x02E4 //
434#define TIMER1 0x02E8 //
435#define GPIO_CTRL 0x02EC // GPIO Control Register
436#define GPIO_IN 0x02EC // GPIO pins input value
437#define GPIO_OUT 0x02ED // GPIO pins output value
438#define GPIO_IO_SEL 0x02EE // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
439#define GPIO_MOD 0x02EF //
440#define GPIO_INTCTRL 0x02F0 // GPIO Interrupt Control Register[7:0]
441#define MAC_PINMUX_CFG 0x02F1 // MAC PINMUX Configuration Reg[7:0]
442#define LEDCFG 0x02F2 // System PINMUX Configuration Reg[7:0]
443#define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0]
444#define PHY_REG_DATA 0x02F4 // PHY REG Read DATA Register [31:0]
445#define EFUSE_CLK 0x02F8 // CTRL: E-FUSE Clock Control Reg[7:0]
446//#define GPIO_INTCTRL 0x02F9 // GPIO Interrupt Control Register[7:0]
447
448//
449// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
450//
451#define IMR 0x0300 // Interrupt Mask Register
452#define ISR 0x0308 // Interrupt Status Register
453
454//
455// 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F)
456//
457#define DBG_PORT_SWITCH 0x003A
458#define BIST 0x0310 // Bist reg definition
459#define DBS 0x0314 // Debug Select ???
460#define CPUINST 0x0318 // CPU Instruction Read Register
461#define CPUCAUSE 0x031C // CPU Cause Register
462#define LBUS_ERR_ADDR 0x0320 // Lexra Bus Error Address Register
463#define LBUS_ERR_CMD 0x0324 // Lexra Bus Error Command Register
464#define LBUS_ERR_DATA_L 0x0328 // Lexra Bus Error Data Low DW Register
465#define LBUS_ERR_DATA_H 0x032C //
466#define LX_EXCEPTION_ADDR 0x0330 // Lexra Bus Exception Address Register
467#define WDG_CTRL 0x0334 // Watch Dog Control Register
468#define INTMTU 0x0338 // Interrupt Mitigation Time Unit Reg
469#define INTM 0x033A // Interrupt Mitigation Register
470#define FDLOCKTURN0 0x033C // FW/DRV Lock Turn 0 Register
471#define FDLOCKTURN1 0x033D // FW/DRV Lock Turn 1 Register
472#define TRXPKTBUF_DBG_DATA 0x0340 // TRX Packet Buffer Debug Data Register
473#define TRXPKTBUF_DBG_CTRL 0x0348 // TRX Packet Buffer Debug Control Reg
474#define DPLL 0x034A // DPLL Monitor Register [15:0]
475#define CBUS_ERR_ADDR 0x0350 // CPU Bus Error Address Register
476#define CBUS_ERR_CMD 0x0354 // CPU Bus Error Command Register
477#define CBUS_ERR_DATA_L 0x0358 // CPU Bus Error Data Low DW Register
478#define CBUS_ERR_DATA_H 0x035C //
479#define USB_SIE_INTF_ADDR 0x0360 // USB SIE Access Interface Address Reg
480#define USB_SIE_INTF_WD 0x0361 // USB SIE Access Interface WData Reg
481#define USB_SIE_INTF_RD 0x0362 // USB SIE Access Interface RData Reg
482#define USB_SIE_INTF_CTRL 0x0363 // USB SIE Access Interface Control Reg
483
484// Boundary is 0x37F
485
486//
487// 14. PCIE config register (Offset 0x500-)
488//
489#define TPPoll 0x0500 // Transmit Polling
490#define PM_CTRL 0x0502 // PCIE power management control Register
491#define PCIF 0x0503 // PCI Function Register 0x0009h~0x000bh
492
493#define THPDA 0x0514 // Transmit High Priority Desc Addr
494#define TMDA 0x0518 // Transmit Management Desc Addr
495#define TCDA 0x051C // Transmit Command Desc Addr
496#define HDA 0x0520 // HCCA Desc Addr
497#define TVODA 0x0524 // Transmit VO Desc Addr
498#define TVIDA 0x0528 // Transmit VI Desc Addr
499#define TBEDA 0x052C // Transmit BE Desc Addr
500#define TBKDA 0x0530 // Transmit BK Desc Addr
501#define TBDA 0x0534 // Transmit Beacon Desc Addr
502#define RCDA 0x0538 // Receive Command Desc Addr
503#define RDSA 0x053C // Receive Desc Starting Addr
504#define DBI_WDATA 0x0540 // DBI write data Register
505#define DBI_RDATA 0x0544 // DBI read data Register
506#define DBI_CTRL 0x0548 // PCIE DBI control Register
507#define MDIO_DATA 0x0550 // PCIE MDIO data Register
508#define MDIO_CTRL 0x0554 // PCIE MDIO control Register
509#define PCI_RPWM 0x0561 // PCIE RPWM register
510#define PCI_CPWM 0x0563 // Current Power Mode.
511
512//
513// Config register (Offset 0x800-)
514//
515#define PHY_CCA 0x803 // CCA related register
516
517//============================================================================
518// 8192S USB specific Regsiter Offset and Content definition,
519// 2008.08.28, added by Roger.
520//============================================================================
521// Rx Aggregation time-out reg.
522#define USB_RX_AGG_TIMEOUT 0xFE5B
523
524// Firware reserved Tx page control.
525#define FW_OFFLOAD_EN BIT7
526
527// Min Spacing related settings.
528#define MAX_MSS_DENSITY 0x13
529#define MAX_MSS_DENSITY_2T 0x13
530#define MAX_MSS_DENSITY_1T 0x0A
531
532// Rx DMA Control related settings
533#define RXDMA_AGG_EN BIT7
534
535// USB Rx Aggregation TimeOut settings
536#define RXDMA_AGG_TIMEOUT_DISABLE 0x00
537#define RXDMA_AGG_TIMEOUT_17MS 0x01
538#define RXDMA_AGG_TIMEOUT_17_2_MS 0x02
539#define RXDMA_AGG_TIMEOUT_17_4_MS 0x04
540#define RXDMA_AGG_TIMEOUT_17_10_MS 0x0A
541// USB RPWM register
542#define USB_RPWM 0xFE58
543
544//FIXLZM SVN_BRACH NOT MOD HERE, IF MOD RX IS LITTLE LOW
545//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==PCI_INTERFACE))
546//#define RPWM PCI_RPWM
547//#elif ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
548//#define RPWM USB_RPWM
549//#endif
550
551
552//============================================================================
553// 8190 Regsiter offset definition
554//============================================================================
555#if 1 // Delete the register later
556#define AFR 0x010 // AutoLoad Function Register
557#define BCN_TCFG 0x062 // Beacon Time Configuration
558#define RATR0 0x320 // Rate Adaptive Table register1
559#endif
560// TODO: Remove unused register, We must declare backward compatiable
561//Undefined register set in 8192S. 0x320/350 DW is useless
562#define UnusedRegister 0x0320
563#define PSR UnusedRegister // Page Select Register
564//Security Related
565#define DCAM UnusedRegister // Debug CAM Interface
566//PHY Configuration related
567#define BBAddr UnusedRegister // Phy register address register
568#define PhyDataR UnusedRegister // Phy register data read
569#define UFWP UnusedRegister
570
571
572//============================================================================
573// 8192S Regsiter Bit and Content definition
574//============================================================================
575
576//
577// 1. System Configuration Registers (Offset: 0x0000 - 0x003F)
578//
579//----------------------------------------------------------------------------
580// 8192S SYS_ISO_CTRL bits (Offset 0x0, 16bit)
581//----------------------------------------------------------------------------
582#define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On.
583#define ISO_PA2PCIE BIT3 // PCIe Analog 1.2V to PCIe 3.3V
584#define ISO_PLL2MD BIT4 // AFE PLL to MACTOP/BB/PCIe Digital.
585#define ISO_PWC_DV2RP BIT11 // Digital Vdd to Retention Path
586#define ISO_PWC_RV2RP BIT12 // LPLDOR12 to Retenrion Path, 1: isolation, 0: attach.
587
588//----------------------------------------------------------------------------
589// 8192S SYS_FUNC_EN bits (Offset 0x2, 16bit)
590//----------------------------------------------------------------------------
591#define FEN_MREGEN BIT15 // MAC I/O Registers Enable.
592#define FEN_DCORE BIT11 // Enable Core Digital.
593#define FEN_CPUEN BIT10 // Enable CPU Core Digital.
594// 8192S PMC_FSM bits (Offset 0x4, 32bit)
595//----------------------------------------------------------------------------
596#define PAD_HWPD_IDN BIT22 // HWPDN PAD status Indicator
597
598//----------------------------------------------------------------------------
599
600//----------------------------------------------------------------------------
601// 8192S SYS_CLKR bits (Offset 0x8, 16bit)
602//----------------------------------------------------------------------------
603#define SYS_CLKSEL_80M BIT0 // System Clock 80MHz
604#define SYS_PS_CLKSEL BIT1 //System power save clock select.
605#define SYS_CPU_CLKSEL BIT2 // System Clock select, 1: AFE source, 0: System clock(L-Bus)
606#define SYS_MAC_CLK_EN BIT11 // MAC Clock Enable.
607#define SYS_SWHW_SEL BIT14 // Load done, control path seitch.
608#define SYS_FWHW_SEL BIT15 // Sleep exit, control path swith.
609
610
611//----------------------------------------------------------------------------
612// 8192S Cmd9346CR bits (Offset 0xA, 16bit)
613//----------------------------------------------------------------------------
614#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
615#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
616#define Cmd9346CR_9356SEL BIT4
617#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
618#define AutoLoadEFUSE CmdEEPROM_En
619
620
621//----------------------------------------------------------------------------
622// 8192S AFE_MISC bits AFE Misc (Offset 0x10, 8bits)
623//----------------------------------------------------------------------------
624#define AFE_MBEN BIT1 // Enable AFE Macro Block's Mbias.
625#define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap.
626
627//----------------------------------------------------------------------------
628// 8192S SPS1_CTRL bits (Offset 0x18-1E, 56bits)
629//----------------------------------------------------------------------------
630#define SPS1_SWEN BIT1 // Enable vsps18 SW Macro Block.
631#define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block.
632
633//----------------------------------------------------------------------------
634// 8192S RF_CTRL bits (Offset 0x1F, 8bits)
635//----------------------------------------------------------------------------
636#define RF_EN BIT0 // Enable RF module.
637#define RF_RSTB BIT1 // Reset RF module.
638#define RF_SDMRSTB BIT2 // Reset RF SDM module.
639
640//----------------------------------------------------------------------------
641// 8192S LDOA15_CTRL bits (Offset 0x20, 8bits)
642//----------------------------------------------------------------------------
643#define LDA15_EN BIT0 // Enable LDOA15 Macro Block
644
645//----------------------------------------------------------------------------
646// 8192S LDOV12D_CTRL bits (Offset 0x21, 8bits)
647//----------------------------------------------------------------------------
648#define LDV12_EN BIT0 // Enable LDOVD12 Macro Block
649#define LDV12_SDBY BIT1 // LDOVD12 standby mode
650
651//----------------------------------------------------------------------------
652// 8192S AFE_XTAL_CTRL bits AFE Crystal Control. (Offset 0x26,16bits)
653//----------------------------------------------------------------------------
654#define XTAL_GATE_AFE BIT10
655// Gated Control. 1: AFE Clock source gated, 0: Clock enable.
656
657//----------------------------------------------------------------------------
658// 8192S AFE_PLL_CTRL bits System Function Enable (Offset 0x28,64bits)
659//----------------------------------------------------------------------------
660#define APLL_EN BIT0 // Enable AFE PLL Macro Block.
661
662// Find which card bus type
663#define AFR_CardBEn BIT0
664#define AFR_CLKRUN_SEL BIT1
665#define AFR_FuncRegEn BIT2
666
667//
668// 2. Command Control Registers (Offset: 0x0040 - 0x004F)
669//
670//----------------------------------------------------------------------------
671// 8192S (CMD) command register bits (Offset 0x40, 16 bits)
672//----------------------------------------------------------------------------
673#define APSDOFF_STATUS BIT15 //
674#define APSDOFF BIT14 //
675#define BBRSTn BIT13 //Enable OFDM/CCK
676#define BB_GLB_RSTn BIT12 //Enable BB
677#define SCHEDULE_EN BIT10 //Enable MAC scheduler
678#define MACRXEN BIT9 //
679#define MACTXEN BIT8 //
680#define DDMA_EN BIT7 //FW off load function enable
681#define FW2HW_EN BIT6 //MAC every module reset as below
682#define RXDMA_EN BIT5 //
683#define TXDMA_EN BIT4 //
684#define HCI_RXDMA_EN BIT3 //
685#define HCI_TXDMA_EN BIT2 //
686
687//----------------------------------------------------------------------------
688// 8192S (TXPAUSE) transmission pause (Offset 0x42, 8 bits)
689//----------------------------------------------------------------------------
690#define StopHCCA BIT6
691#define StopHigh BIT5
692#define StopMgt BIT4
693#define StopVO BIT3
694#define StopVI BIT2
695#define StopBE BIT1
696#define StopBK BIT0
697
698//----------------------------------------------------------------------------
699// 8192S (LBKMD) LoopBack Mode Select (Offset 0x43, 8 bits)
700//----------------------------------------------------------------------------
701//
702// [3] no buffer, 1: no delay, 0: delay; [2] dmalbk, [1] no_txphy, [0] diglbk.
703// 0000: Normal
704// 1011: MAC loopback (involving CPU)
705// 0011: MAC Delay Loopback
706// 0001: PHY loopback (not yet implemented)
707// 0111: DMA loopback (only uses TxPktBuffer and DMA engine)
708// All other combinations are reserved.
709// Default: 0000b.
710//
711#define LBK_NORMAL 0x00
712#define LBK_MAC_LB (BIT0|BIT1|BIT3)
713#define LBK_MAC_DLB (BIT0|BIT1)
714#define LBK_DMA_LB (BIT0|BIT1|BIT2)
715
716//----------------------------------------------------------------------------
717// 8192S (TCR) transmission Configuration Register (Offset 0x44, 32 bits)
718//----------------------------------------------------------------------------
719#define TCP_OFDL_EN BIT25 //For CE packet conversion
720#define HWPC_TX_EN BIT24 //""
721#define TXDMAPRE2FULL BIT23 //TXDMA enable pre2full sync
722#define DISCW BIT20 //CW disable
723#define TCRICV BIT19 //Append ICV or not
724#define CfendForm BIT17 //AP mode
725#define TCRCRC BIT16 //Append CRC32
726#define FAKE_IMEM_EN BIT15 //
727#define TSFRST BIT9 //
728#define TSFEN BIT8 //
729// For TCR FW download ready --> write by FW Bit0-7 must all one
730#define FWALLRDY (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
731#define FWRDY BIT7
732#define BASECHG BIT6
733#define IMEM BIT5
734#define DMEM_CODE_DONE BIT4
735#define EXT_IMEM_CHK_RPT BIT3
736#define EXT_IMEM_CODE_DONE BIT2
737#define IMEM_CHK_RPT BIT1
738#define IMEM_CODE_DONE BIT0
739// Copy fomr 92SU definition
740#define IMEM_CODE_DONE BIT0
741#define IMEM_CHK_RPT BIT1
742#define EMEM_CODE_DONE BIT2
743#define EMEM_CHK_RPT BIT3
744#define DMEM_CODE_DONE BIT4
745#define IMEM_RDY BIT5
746#define BASECHG BIT6
747#define FWRDY BIT7
748#define LOAD_FW_READY (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\
749 EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\
750 FWRDY)
751#define TCR_TSFEN BIT8 // TSF function on or off.
752#define TCR_TSFRST BIT9 // Reset TSF function to zero.
753#define TCR_FAKE_IMEM_EN BIT15
754#define TCR_CRC BIT16
755#define TCR_ICV BIT19 // Integrity Check Value.
756#define TCR_DISCW BIT20 // Disable Contention Windows Backoff.
757#define TCR_HWPC_TX_EN BIT24
758#define TCR_TCP_OFDL_EN BIT25
759#define TXDMA_INIT_VALUE (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT)
760//----------------------------------------------------------------------------
761// 8192S (RCR) Receive Configuration Register (Offset 0x48, 32 bits)
762//----------------------------------------------------------------------------
763#define RCR_APPFCS BIT31 //WMAC append FCS after pauload
764#define RCR_DIS_ENC_2BYTE BIT30 //HW encrypt 2 or 1 byte mode
765#define RCR_DIS_AES_2BYTE BIT29 //
766#define RCR_HTC_LOC_CTRL BIT28 //MFC<--HTC=1 MFC-->HTC=0
767#define RCR_ENMBID BIT27 //Enable Multiple BssId.
768#define RCR_RX_TCPOFDL_EN BIT26 //
769#define RCR_APP_PHYST_RXFF BIT25 //
770#define RCR_APP_PHYST_STAFF BIT24 //
771#define RCR_CBSSID BIT23 //Accept BSSID match packet
772#define RCR_APWRMGT BIT22 //Accept power management packet
773#define RCR_ADD3 BIT21 //Accept address 3 match packet
774#define RCR_AMF BIT20 //Accept management type frame
775#define RCR_ACF BIT19 //Accept control type frame
776#define RCR_ADF BIT18 //Accept data type frame
777#define RCR_APP_MIC BIT17 //
778#define RCR_APP_ICV BIT16 //
779#define RCR_RXFTH BIT13 //Rx FIFO Threshold Bot 13 - 15
780#define RCR_AICV BIT12 //Accept ICV error packet
781#define RCR_RXDESC_LK_EN BIT11 //Accept to update rx desc length
782#define RCR_APP_BA_SSN BIT6 //Accept BA SSN
783#define RCR_ACRC32 BIT5 //Accept CRC32 error packet
784#define RCR_RXSHFT_EN BIT4 //Accept broadcast packet
785#define RCR_AB BIT3 //Accept broadcast packet
786#define RCR_AM BIT2 //Accept multicast packet
787#define RCR_APM BIT1 //Accept physical match packet
788#define RCR_AAP BIT0 //Accept all unicast packet
789#define RCR_MXDMA_OFFSET 8
790#define RCR_FIFO_OFFSET 13
791
792//in 92U FIXLZM
793//#ifdef RTL8192U
794#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
795#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
796#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1
797#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
798//#endif
799//----------------------------------------------------------------------------
800// 8192S (MSR) Media Status Register (Offset 0x4C, 8 bits)
801//----------------------------------------------------------------------------
802/*
803Network Type
80400: No link
80501: Link in ad hoc network
80610: Link in infrastructure network
80711: AP mode
808Default: 00b.
809*/
810#define MSR_NOLINK 0x00
811#define MSR_ADHOC 0x01
812#define MSR_INFRA 0x02
813#define MSR_AP 0x03
814
815//----------------------------------------------------------------------------
816// 8192S (SYSF_CFG) system Fucntion Config Reg (Offset 0x4D, 8 bits)
817//----------------------------------------------------------------------------
818#define ENUART BIT7
819#define ENJTAG BIT3
820#define BTMODE (BIT2|BIT1)
821#define ENBT BIT0
822
823//----------------------------------------------------------------------------
824// 8192S (MBIDCTRL) MBSSID Control Register (Offset 0x4F, 8 bits)
825//----------------------------------------------------------------------------
826#define ENMBID BIT7
827#define BCNUM (BIT6|BIT5|BIT4)
828
829//
830// 3. MACID Setting Registers (Offset: 0x0050 - 0x007F)
831//
832
833//
834// 4. Timing Control Registers (Offset: 0x0080 - 0x009F)
835//
836//----------------------------------------------------------------------------
837// 8192S (USTIME) US Time Tunning Register (Offset 0x8A, 16 bits)
838//----------------------------------------------------------------------------
839#define USTIME_EDCA 0xFF00
840#define USTIME_TSF 0x00FF
841
842//----------------------------------------------------------------------------
843// 8192S (SIFS_CCK/OFDM) US Time Tunning Register (Offset 0x8C/8E,16 bits)
844//----------------------------------------------------------------------------
845#define SIFS_TRX 0xFF00
846#define SIFS_CTX 0x00FF
847
848//----------------------------------------------------------------------------
849// 8192S (DRVERLYINT) Driver Early Interrupt Reg (Offset 0x98, 16bit)
850//----------------------------------------------------------------------------
851#define ENSWBCN BIT15
852#define DRVERLY_TU 0x0FF0
853#define DRVERLY_US 0x000F
854#define BCN_TCFG_CW_SHIFT 8
855#define BCN_TCFG_IFS 0
856
857//
858// 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F)
859//
860
861//
862// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF)
863//
864//----------------------------------------------------------------------------
865// 8192S Response Rate Set Register (offset 0x181, 24bits)
866//----------------------------------------------------------------------------
867#define RRSR_RSC_OFFSET 21
868#define RRSR_SHORT_OFFSET 23
869#define RRSR_RSC_BW_40M 0x600000
870#define RRSR_RSC_UPSUBCHNL 0x400000
871#define RRSR_RSC_LOWSUBCHNL 0x200000
872#define RRSR_SHORT 0x800000
873#define RRSR_1M BIT0
874#define RRSR_2M BIT1
875#define RRSR_5_5M BIT2
876#define RRSR_11M BIT3
877#define RRSR_6M BIT4
878#define RRSR_9M BIT5
879#define RRSR_12M BIT6
880#define RRSR_18M BIT7
881#define RRSR_24M BIT8
882#define RRSR_36M BIT9
883#define RRSR_48M BIT10
884#define RRSR_54M BIT11
885#define RRSR_MCS0 BIT12
886#define RRSR_MCS1 BIT13
887#define RRSR_MCS2 BIT14
888#define RRSR_MCS3 BIT15
889#define RRSR_MCS4 BIT16
890#define RRSR_MCS5 BIT17
891#define RRSR_MCS6 BIT18
892#define RRSR_MCS7 BIT19
893#define BRSR_AckShortPmb BIT23
894
895#define RRSR_RSC_UPSUBCHANL 0x200000
896// CCK ACK: use Short Preamble or not
897
898//----------------------------------------------------------------------------
899// 8192S Rate Definition
900//----------------------------------------------------------------------------
901//CCK
902#define RATR_1M 0x00000001
903#define RATR_2M 0x00000002
904#define RATR_55M 0x00000004
905#define RATR_11M 0x00000008
906//OFDM
907#define RATR_6M 0x00000010
908#define RATR_9M 0x00000020
909#define RATR_12M 0x00000040
910#define RATR_18M 0x00000080
911#define RATR_24M 0x00000100
912#define RATR_36M 0x00000200
913#define RATR_48M 0x00000400
914#define RATR_54M 0x00000800
915//MCS 1 Spatial Stream
916#define RATR_MCS0 0x00001000
917#define RATR_MCS1 0x00002000
918#define RATR_MCS2 0x00004000
919#define RATR_MCS3 0x00008000
920#define RATR_MCS4 0x00010000
921#define RATR_MCS5 0x00020000
922#define RATR_MCS6 0x00040000
923#define RATR_MCS7 0x00080000
924//MCS 2 Spatial Stream
925#define RATR_MCS8 0x00100000
926#define RATR_MCS9 0x00200000
927#define RATR_MCS10 0x00400000
928#define RATR_MCS11 0x00800000
929#define RATR_MCS12 0x01000000
930#define RATR_MCS13 0x02000000
931#define RATR_MCS14 0x04000000
932#define RATR_MCS15 0x08000000
933// ALL CCK Rate
934#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
935#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
936 RATR_36M|RATR_48M|RATR_54M
937#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
938 RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
939#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
940 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
941
942//
943// 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF)
944//
945//----------------------------------------------------------------------------
946// 8192S EDCA Setting (offset 0x1D0-1DF, 4DW VO/VI/BE/BK)
947//----------------------------------------------------------------------------
948#define AC_PARAM_TXOP_LIMIT_OFFSET 16
949#define AC_PARAM_ECW_MAX_OFFSET 12
950#define AC_PARAM_ECW_MIN_OFFSET 8
951#define AC_PARAM_AIFS_OFFSET 0
952
953//----------------------------------------------------------------------------
954// 8192S AcmHwCtrl bits (offset 0x1E7, 1 byte)
955//----------------------------------------------------------------------------
956#define AcmHw_HwEn BIT0
957#define AcmHw_BeqEn BIT1
958#define AcmHw_ViqEn BIT2
959#define AcmHw_VoqEn BIT3
960#define AcmHw_BeqStatus BIT4
961#define AcmHw_ViqStatus BIT5
962#define AcmHw_VoqStatus BIT6
963
964//----------------------------------------------------------------------------
965// 8192S Retry Limit (Offset 0x1F4, 16bit)
966//----------------------------------------------------------------------------
967#define RETRY_LIMIT_SHORT_SHIFT 8
968#define RETRY_LIMIT_LONG_SHIFT 0
969
970//
971// 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F)
972//
973//----------------------------------------------------------------------------
974// 8192S NAV_CTRL bits (Offset 0x200, 24bit)
975//----------------------------------------------------------------------------
976#define NAV_UPPER_EN BIT16
977#define NAV_UPPER 0xFF00
978#define NAV_RTSRST 0xFF
979//----------------------------------------------------------------------------
980// 8192S BW_OPMODE bits (Offset 0x203, 8bit)
981//----------------------------------------------------------------------------
982#define BW_OPMODE_20MHZ BIT2
983#define BW_OPMODE_5G BIT1
984#define BW_OPMODE_11J BIT0
985//----------------------------------------------------------------------------
986// 8192S BW_OPMODE bits (Offset 0x230, 4 Byte)
987//----------------------------------------------------------------------------
988#define RXERR_RPT_RST BIT27 // Write "one" to set the counter to zero.
989// RXERR_RPT_SEL
990#define RXERR_OFDM_PPDU 0
991#define RXERR_OFDM_FALSE_ALARM 1
992#define RXERR_OFDM_MPDU_OK 2
993#define RXERR_OFDM_MPDU_FAIL 3
994#define RXERR_CCK_PPDU 4
995#define RXERR_CCK_FALSE_ALARM 5
996#define RXERR_CCK_MPDU_OK 6
997#define RXERR_CCK_MPDU_FAIL 7
998#define RXERR_HT_PPDU 8
999#define RXERR_HT_FALSE_ALARM 9
1000#define RXERR_HT_MPDU_TOTAL 10
1001#define RXERR_HT_MPDU_OK 11
1002#define RXERR_HT_MPDU_FAIL 12
1003#define RXERR_RX_FULL_DROP 15
1004
1005//
1006// 9. Security Control Registers (Offset: 0x0240 - 0x025F)
1007//
1008//----------------------------------------------------------------------------
1009// 8192S RWCAM CAM Command Register (offset 0x240, 4 byte)
1010//----------------------------------------------------------------------------
1011#define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling
1012#define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM
1013#define CAM_CM_SecCAMWE BIT16 //Security CAM enable
1014#define CAM_ADDR 0xFF //CAM Address Offset
1015
1016//----------------------------------------------------------------------------
1017// 8192S CAMDBG Debug CAM Register (offset 0x24C, 4 byte)
1018//----------------------------------------------------------------------------
1019#define Dbg_CAM_TXSecCAMInfo BIT31 //Retrieve lastest Tx Info
1020#define Dbg_CAM_SecKeyFound BIT30 //Security KEY Found
1021
1022
1023//----------------------------------------------------------------------------
1024// 8192S SECR Security Configuration Register (offset 0x250, 1 byte)
1025//----------------------------------------------------------------------------
1026#define SCR_TxUseDK BIT0 //Force Tx Use Default Key
1027#define SCR_RxUseDK BIT1 //Force Rx Use Default Key
1028#define SCR_TxEncEnable BIT2 //Enable Tx Encryption
1029#define SCR_RxDecEnable BIT3 //Enable Rx Decryption
1030#define SCR_SKByA2 BIT4 //Search kEY BY A2
1031#define SCR_NoSKMC BIT5 //No Key Search Multicast
1032//----------------------------------------------------------------------------
1033// 8192S CAM Config Setting (offset 0x250, 1 byte)
1034//----------------------------------------------------------------------------
1035#define CAM_VALID BIT15
1036#define CAM_NOTVALID 0x0000
1037#define CAM_USEDK BIT5
1038
1039#define CAM_NONE 0x0
1040#define CAM_WEP40 0x01
1041#define CAM_TKIP 0x02
1042#define CAM_AES 0x04
1043#define CAM_WEP104 0x05
1044
1045#define TOTAL_CAM_ENTRY 32
1046
1047#define CAM_CONFIG_USEDK TRUE
1048#define CAM_CONFIG_NO_USEDK FALSE
1049
1050#define CAM_WRITE BIT16
1051#define CAM_READ 0x00000000
1052#define CAM_POLLINIG BIT31
1053
1054#define SCR_UseDK 0x01
1055#define SCR_TxSecEnable 0x02
1056#define SCR_RxSecEnable 0x04
1057
1058//
1059// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF)
1060//
1061#define WOW_PMEN BIT0 // Power management Enable.
1062#define WOW_WOMEN BIT1 // WoW function on or off.
1063#define WOW_MAGIC BIT2 // Magic packet
1064#define WOW_UWF BIT3 // Unicast Wakeup frame.
1065
1066//
1067// 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)
1068// 8192S GPIO Config Setting (offset 0x2F1, 1 byte)
1069//----------------------------------------------------------------------------
1070#define GPIOMUX_EN BIT3 // When this bit is set to "1", GPIO PINs will switch to MAC GPIO Function
1071#define GPIOSEL_GPIO 0 // UART or JTAG or pure GPIO
1072#define GPIOSEL_PHYDBG 1 // PHYDBG
1073#define GPIOSEL_BT 2 // BT_coex
1074#define GPIOSEL_WLANDBG 3 // WLANDBG
1075#define GPIOSEL_GPIO_MASK ~(BIT0|BIT1)
1076
1077//----------------------------------------------------------------------------
1078
1079//----------------------------------------------------------------------------
1080// PHY REG Access Report Register definition
1081//----------------------------------------------------------------------------
1082#define HST_RDBUSY BIT0
1083#define CPU_WTBUSY BIT1
1084
1085//
1086// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F)
1087//
1088//----------------------------------------------------------------------------
1089// 8190 IMR/ISR bits (offset 0xfd, 8bits)
1090//----------------------------------------------------------------------------
1091#define IMR8190_DISABLED 0x0
1092
1093// IMR DW1 Bit 0-31
1094#define IMR_CPUERR BIT5 // CPU error interrupt
1095#define IMR_ATIMEND BIT4 // ATIM Window End Interrupt
1096#define IMR_TBDOK BIT3 // Transmit Beacon OK Interrupt
1097#define IMR_TBDER BIT2 // Transmit Beacon Error Interrupt
1098#define IMR_BCNDMAINT8 BIT1 // Beacon DMA Interrupt 8
1099#define IMR_BCNDMAINT7 BIT0 // Beacon DMA Interrupt 7
1100// IMR DW0 Bit 0-31
1101
1102#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6
1103#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5
1104#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4
1105#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3
1106#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2
1107#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1
1108#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8
1109#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7
1110#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6
1111#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5
1112#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4
1113#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3
1114#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2
1115#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1
1116#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
1117#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
1118#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
1119#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
1120#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
1121#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
1122#define IMR_RDU BIT11 // Receive Descriptor Unavailable
1123#define IMR_RXCMDOK BIT10 // Receive Command Packet OK
1124#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
1125#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
1126#define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt
1127#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
1128#define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt
1129#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
1130#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
1131#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
1132#define IMR_VODOK BIT1 // AC_VO DMA Interrupt
1133#define IMR_ROK BIT0 // Receive DMA OK Interrupt
1134
1135//
1136// 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F)
1137//
1138
1139//
1140// 14. PCIE config register (Offset 0x500-)
1141//
1142//----------------------------------------------------------------------------
1143// 8190 TPPool bits (offset 0xd9, 2 byte)
1144//----------------------------------------------------------------------------
1145#define TPPoll_BKQ BIT0 // BK queue polling
1146#define TPPoll_BEQ BIT1 // BE queue polling
1147#define TPPoll_VIQ BIT2 // VI queue polling
1148#define TPPoll_VOQ BIT3 // VO queue polling
1149#define TPPoll_BQ BIT4 // Beacon queue polling
1150#define TPPoll_CQ BIT5 // Command queue polling
1151#define TPPoll_MQ BIT6 // Management queue polling
1152#define TPPoll_HQ BIT7 // High queue polling
1153#define TPPoll_HCCAQ BIT8 // HCCA queue polling
1154#define TPPoll_StopBK BIT9 // Stop BK queue
1155#define TPPoll_StopBE BIT10 // Stop BE queue
1156#define TPPoll_StopVI BIT11 // Stop VI queue
1157#define TPPoll_StopVO BIT12 // Stop VO queue
1158#define TPPoll_StopMgt BIT13 // Stop Mgnt queue
1159#define TPPoll_StopHigh BIT14 // Stop High queue
1160#define TPPoll_StopHCCA BIT15 // Stop HCCA queue
1161#define TPPoll_SHIFT 8 // Queue ID mapping
1162
1163//----------------------------------------------------------------------------
1164// 8192S PCIF (Offset 0x500, 32bit)
1165//----------------------------------------------------------------------------
1166#define MXDMA2_16bytes 0x000
1167#define MXDMA2_32bytes 0x001
1168#define MXDMA2_64bytes 0x010
1169#define MXDMA2_128bytes 0x011
1170#define MXDMA2_256bytes 0x100
1171#define MXDMA2_512bytes 0x101
1172#define MXDMA2_1024bytes 0x110
1173#define MXDMA2_NoLimit 0x7
1174
1175#define MULRW_SHIFT 3
1176#define MXDMA2_RX_SHIFT 4
1177#define MXDMA2_TX_SHIFT 0
1178
1179//----------------------------------------------------------------------------
1180// 8190 CCX_COMMAND_REG Setting (offset 0x25A, 1 byte)
1181//----------------------------------------------------------------------------
1182#define CCX_CMD_CLM_ENABLE BIT0 // Enable Channel Load
1183#define CCX_CMD_NHM_ENABLE BIT1 // Enable Noise Histogram
1184#define CCX_CMD_FUNCTION_ENABLE BIT8
1185// CCX function (Channel Load/RPI/Noise Histogram).
1186#define CCX_CMD_IGNORE_CCA BIT9
1187// Treat CCA period as IDLE time for NHM.
1188#define CCX_CMD_IGNORE_TXON BIT10
1189// Treat TXON period as IDLE time for NHM.
1190#define CCX_CLM_RESULT_READY BIT16
1191// 1: Indicate the result of Channel Load is ready.
1192#define CCX_NHM_RESULT_READY BIT16
1193// 1: Indicate the result of Noise histogram is ready.
1194#define CCX_CMD_RESET 0x0
1195// Clear all the result of CCX measurement and disable the CCX function.
1196
1197
1198//----------------------------------------------------------------------------
1199// 8192S EFUSE
1200//----------------------------------------------------------------------------
1201//#define HWSET_MAX_SIZE_92S 128
1202
1203
1204//----------------------------------------------------------------------------
1205// 8192S EEPROM/EFUSE share register definition.
1206//----------------------------------------------------------------------------
1207
1208#ifdef RTL8192SE
1209//
1210// 2008/11/05 MH Redefine EEPROM address for 8192SE
1211// 92SE/SU EEPROM definition seems not the same!!!!!!
1212// EEPROM MAP REgister Definition!!!! Please refer to 8192SE EEPROM V0.5 2008/10/21
1213// Update to 8192SE EEPROM V0.6 2008/11/11
1214//
1215#define RTL8190_EEPROM_ID 0x8129 // 0-1
1216#define EEPROM_HPON 0x02 // LDO settings.2-5
1217#define EEPROM_CLK 0x06 // Clock settings.6-7
1218#define EEPROM_TESTR 0x08 // SE Test mode.8
1219
1220#define EEPROM_VID 0x0A // SE Vendor ID.A-B
1221#define EEPROM_DID 0x0C // SE Device ID. C-D
1222#define EEPROM_SVID 0x0E // SE Vendor ID.E-F
1223#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11
1224
1225#define EEPROM_MAC_ADDR 0x12 // SEMAC Address. 12-17
1226#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address.
1227
1228#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
1229
1230//
1231// 0x20 - 4B EPHY parameter!!!
1232//
1233//
1234#define EEPROM_TxPowerBase 0x50 // Tx Power of serving station.
1235#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24//FIXLZM
1236#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24//FIXLZM
1237#define EEPROM_TX_PWR_INDEX_RANGE 28 // CCK and OFDM 14 channel
1238
1239
1240// 2009/01/21 MH Add for SD3 requirement
1241#define EEPROM_TX_PWR_HT20_DIFF 0x62// HT20 Tx Power Index Difference
1242#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
1243#define EEPROM_TX_PWR_OFDM_DIFF 0x65// OFDM Tx Power Index Difference
1244#define EEPROM_TX_PWR_BAND_EDGE 0x67// TX Power offset at band-edge channel
1245#define TX_PWR_BAND_EDGE_CHK 0x6D// Check if band-edge scheme is enabled
1246
1247// Oly old EEPROM format support the definition=============================
1248//
1249#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24
1250#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24
1251#define EEPROM_HT2T_CH1_A 0x6c //HT 2T path A channel 1 Power Index.
1252#define EEPROM_HT2T_CH7_A 0x6d //HT 2T path A channel 7 Power Index.
1253#define EEPROM_HT2T_CH13_A 0x6e //HT 2T path A channel 13 Power Index.
1254#define EEPROM_HT2T_CH1_B 0x6f //HT 2T path B channel 1 Power Index.
1255#define EEPROM_HT2T_CH7_B 0x70 //HT 2T path B channel 7 Power Index.
1256#define EEPROM_HT2T_CH13_B 0x71 //HT 2T path B channel 13 Power Index.
1257//
1258#define EEPROM_TSSI_A 0x74 //TSSI value of path A.
1259#define EEPROM_TSSI_B 0x75 //TSSI value of path B.
1260//
1261#define EEPROM_RFInd_PowerDiff 0x76
1262#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1263//
1264#define EEPROM_ThermalMeter 0x77 // Thermal meter default value.
1265#define EEPROM_CrystalCap 0x79 // Crystal Cap.
1266#define EEPROM_ChannelPlan 0x7B // Map of supported channels.
1267#define EEPROM_Version 0x7C // The EEPROM content version
1268#define EEPROM_CustomID 0x7A
1269#define EEPROM_BoardType 0x7E
1270// 0: 2x2 Green RTL8192GE miniCard (QFN68)
1271// 1: 1x2 RTL8191SE miniCard (QFN64)
1272// 2: 2x2 RTL8192SE miniCard (QFN68)
1273// 3: 1x2 RTL8191SR minicCard(QFN64)
1274
1275//
1276// Default Value for EEPROM or EFUSE!!!
1277//
1278#define EEPROM_Default_TSSI 0x0
1279#define EEPROM_Default_TxPowerDiff 0x0
1280#define EEPROM_Default_CrystalCap 0x5
1281#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SE(QFPN68)
1282#define EEPROM_Default_TxPower 0x1010
1283#define EEPROM_Default_HT2T_TxPwr 0x10
1284
1285#ifdef EEPROM_OLD_FORMAT_SUPPORT
1286#define EEPROM_Default_TxPowerBase 0x0
1287#define EEPROM_Default_ThermalMeter 0x12
1288#define EEPROM_Default_PwDiff 0x4
1289#else
1290#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1291#define EEPROM_Default_ThermalMeter 0x12
1292#define EEPROM_Default_AntTxPowerDiff 0x0
1293#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1294#define EEPROM_Default_TxPowerLevel 0x22
1295#endif
1296
1297#define EEPROM_CHANNEL_PLAN_FCC 0x0
1298#define EEPROM_CHANNEL_PLAN_IC 0x1
1299#define EEPROM_CHANNEL_PLAN_ETSI 0x2
1300#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
1301#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
1302#define EEPROM_CHANNEL_PLAN_MKK 0x5
1303#define EEPROM_CHANNEL_PLAN_MKK1 0x6
1304#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
1305#define EEPROM_CHANNEL_PLAN_TELEC 0x8
1306#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
1307#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
1308#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
1309
1310
1311#define EEPROM_CID_DEFAULT 0x0
1312#define EEPROM_CID_TOSHIBA 0x4
1313#else
1314//----------------------------------------------------------------------------
1315// 8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21.
1316//----------------------------------------------------------------------------
1317#define RTL8190_EEPROM_ID 0x8129
1318#define EEPROM_HPON 0x02 // LDO settings.
1319#define EEPROM_VID 0x08 // USB Vendor ID.
1320#define EEPROM_PID 0x0A // USB Product ID.
1321#define EEPROM_USB_OPTIONAL 0x0C // For optional function.
1322#define EEPROM_USB_PHY_PARA1 0x0D // For fine tune USB PHY.
1323#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address.
1324#define EEPROM_TxPowerDiff 0x1F
1325
1326#define EEPROM_Version 0x50
1327#define EEPROM_ChannelPlan 0x51 // Map of supported channels.
1328#define EEPROM_CustomID 0x52
1329#define EEPROM_SubCustomID 0x53 // Reserved for customer use.
1330
1331
1332 // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22.
1333#ifdef EEPROM_OLD_FORMAT_SUPPORT
1334#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
1335#define EEPROM_ThermalMeter 0x55 // Thermal meter default value.
1336#define EEPROM_Reserved 0x56 // Reserved.
1337#define EEPROM_CrystalCap 0x57 // Crystal Cap.
1338#define EEPROM_TxPowerBase 0x58 // Tx Power of serving station.
1339#define EEPROM_TxPwIndex_CCK_24G 0x59 // 0x59~0x66
1340#define EEPROM_TxPwIndex_OFDM_24G 0x67 // 0x67~0x74
1341#define EEPROM_TSSI_A 0x75 //TSSI value of path A.
1342#define EEPROM_TSSI_B 0x76 //TSSI value of path B.
1343#define EEPROM_TxPwTkMode 0x77 //Tx Power tracking mode.
1344#define EEPROM_HT2T_CH1_A 0x78 //HT 2T path A channel 1 Power Index.
1345#define EEPROM_HT2T_CH7_A 0x79 //HT 2T path A channel 7 Power Index.
1346#define EEPROM_HT2T_CH13_A 0x7a //HT 2T path A channel 13 Power Index.
1347#define EEPROM_HT2T_CH1_B 0x7b //HT 2T path B channel 1 Power Index.
1348#define EEPROM_HT2T_CH7_B 0x7c //HT 2T path B channel 7 Power Index.
1349#define EEPROM_HT2T_CH13_B 0x7d //HT 2T path B channel 13 Power Index.
1350#define EEPROM_BoardType 0x7e //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1351#else
1352#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1353#define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index.
1354#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM.
1355#define EEPROM_ThermalMeter 0x68 // Thermal meter default value.
1356#define EEPROM_CrystalCap 0x69 // Crystal Cap.
1357#define EEPROM_TxPowerBase 0x6a // Tx Power of serving station.
1358#define EEPROM_TSSI_A 0x6b //TSSI value of path A.
1359#define EEPROM_TSSI_B 0x6c //TSSI value of path B.
1360#define EEPROM_TxPwTkMode 0x6d //Tx Power tracking mode.
1361//#define EEPROM_Reserved 0x6e //0x6e-0x7f, reserved.
1362
1363// 2009/02/09 Cosa Add for SD3 requirement
1364#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference
1365#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
1366#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
1367#define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel
1368#define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled
1369#endif
1370#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1371#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8
1372#define EEPROM_USB_Default_PHY_PARAM 0x0
1373#define EEPROM_Default_TSSI 0x0
1374#define EEPROM_Default_TxPwrTkMode 0x0
1375#define EEPROM_Default_TxPowerDiff 0x0
1376#define EEPROM_Default_TxPowerBase 0x0
1377#define EEPROM_Default_ThermalMeter 0x7
1378#define EEPROM_Default_PwDiff 0x4
1379#define EEPROM_Default_CrystalCap 0x5
1380#define EEPROM_Default_TxPower 0x1010
1381#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SU(QFPN68)
1382#define EEPROM_Default_HT2T_TxPwr 0x10
1383#define EEPROM_USB_SN BIT0
1384#define EEPROM_USB_REMOTE_WAKEUP BIT1
1385#define EEPROM_USB_DEVICE_PWR BIT2
1386#define EEPROM_EP_NUMBER (BIT3|BIT4)
1387
1388#define EEPROM_CHANNEL_PLAN_FCC 0x0
1389#define EEPROM_CHANNEL_PLAN_IC 0x1
1390#define EEPROM_CHANNEL_PLAN_ETSI 0x2
1391#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
1392#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
1393#define EEPROM_CHANNEL_PLAN_MKK 0x5
1394#define EEPROM_CHANNEL_PLAN_MKK1 0x6
1395#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
1396#define EEPROM_CHANNEL_PLAN_TELEC 0x8
1397#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
1398#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
1399#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
1400
1401#define EEPROM_CID_DEFAULT 0x0
1402#define EEPROM_CID_ALPHA 0x1
1403#define EEPROM_CID_CAMEO 0X8
1404#define EEPROM_CID_SITECOM 0x9
1405
1406//#define EEPROM_CID_RUNTOP 0x2
1407//#define EEPROM_CID_Senao 0x3
1408//#define EEPROM_CID_TOSHIBA 0x4
1409//#define EEPROM_CID_NetCore 0x5
1410#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
1411#endif
1412
1413//-----------------------------------------------------------------
1414// 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27.
1415//-----------------------------------------------------------------
1416#define FW_DIG_DISABLE 0xfd00cc00
1417#define FW_DIG_ENABLE 0xfd000000
1418#define FW_DIG_HALT 0xfd000001
1419#define FW_DIG_RESUME 0xfd000002
1420#define FW_HIGH_PWR_DISABLE 0xfd000008
1421#define FW_HIGH_PWR_ENABLE 0xfd000009
1422#define FW_TXPWR_TRACK_ENABLE 0xfd000017
1423#define FW_TXPWR_TRACK_DISABLE 0xfd000018
1424#define FW_RA_RESET 0xfd0000af
1425#define FW_RA_ACTIVE 0xfd0000a6
1426#define FW_RA_REFRESH 0xfd0000a0
1427#define FW_RA_ENABLE_BG 0xfd0000ac
1428#define FW_IQK_ENABLE 0xf0000020
1429#define FW_IQK_SUCCESS 0x0000dddd
1430#define FW_IQK_FAIL 0x0000ffff
1431#define FW_OP_FAILURE 0xffffffff
1432#define FW_DM_DISABLE 0xfd00aa00
1433#define FW_BB_RESET_ENABLE 0xff00000d
1434#define FW_BB_RESET_DISABLE 0xff00000e
1435#if 0
1436//----------------------------------------------------------------------------
1437// 8190 EEROM
1438//----------------------------------------------------------------------------
1439#define RTL8190_EEPROM_ID 0x8129
1440//#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
1441
1442#define EEPROM_RFInd_PowerDiff 0x28
1443#define EEPROM_ThermalMeter 0x29
1444#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
1445#define EEPROM_TxPwIndex_CCK 0x2C //0x2C~0x39
1446#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x3A~0x47
1447#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B
1448
1449//The following definition is for eeprom 93c56......modified 20080220
1450#define EEPROM_C56_CrystalCap 0x17 //0x17
1451#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80
1452#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83
1453#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8
1454#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb
1455#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
1456#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChnlPlan,
1457 //0x7D:IC_Ver
1458#define EEPROM_CRC 0x7E //0x7E~0x7F
1459
1460#define EEPROM_Default_LegacyHTTxPowerDiff 0x4
1461#define EEPROM_Default_ThermalMeter 0x77
1462#define EEPROM_Default_AntTxPowerDiff 0x0
1463#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1464#define EEPROM_Default_TxPower 0x1010
1465#define EEPROM_Default_TxPowerLevel 0x10
1466
1467//
1468// Define Different EEPROM type for customer
1469//
1470#define EEPROM_CID_DEFAULT 0x0
1471#define EEPROM_CID_CAMEO 0x1
1472#define EEPROM_CID_RUNTOP 0x2
1473#define EEPROM_CID_Senao 0x3
1474#define EEPROM_CID_TOSHIBA 0x4
1475#define EEPROM_CID_NetCore 0x5
1476#define EEPROM_CID_Nettronix 0x6
1477#define EEPROM_CID_Pronet 0x7
1478
1479#endif
1480
1481//
1482//--------------92SU require delete or move to other place later
1483//
1484
1485
1486
1487//
1488//
1489// 2008/08/06 MH For share the same 92S source/header files, we copy some
1490// definition to pass 92SU compiler. But we must delete thm later.
1491//
1492//
1493
1494//============================================================================
1495// 819xUsb Regsiter offset definition
1496//============================================================================
1497
1498//2 define it temp!!!
1499#define RFPC 0x5F // Rx FIFO Packet Count
1500#define RCR_9356SEL BIT6
1501#define TCR_LRL_OFFSET 0
1502#define TCR_SRL_OFFSET 8
1503#define TCR_MXDMA_OFFSET 21
1504#define TCR_MXDMA_2048 7
1505#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer
1506#define RCR_MXDMA_OFFSET 8
1507#define RCR_FIFO_OFFSET 13
1508#define RCR_OnlyErlPkt BIT31 // Rx Early mode is performed for packet size greater than 1536
1509#define CWR 0xDC // Contention window register
1510#define RetryCTR 0xDE // Retry Count register
1511
1512
1513// For backward compatible for 9xUSB
1514#define LED1Cfg UnusedRegister // LED1 Configuration Register
1515#define LED0Cfg UnusedRegister // LED0 Configuration Register
1516#define GPI UnusedRegister // LED0 Configuration Register
1517#define BRSR UnusedRegister // LED0 Configuration Register
1518#define CPU_GEN UnusedRegister // LED0 Configuration Register
1519#define SIFS UnusedRegister // LED0 Configuration Register
1520
1521//----------------------------------------------------------------------------
1522// 8190 CPU General Register (offset 0x100, 4 byte)
1523//----------------------------------------------------------------------------
1524//#define CPU_CCK_LOOPBACK 0x00030000
1525#define CPU_GEN_SYSTEM_RESET 0x00000001
1526//#define CPU_GEN_FIRMWARE_RESET 0x00000008
1527//#define CPU_GEN_BOOT_RDY 0x00000010
1528//#define CPU_GEN_FIRM_RDY 0x00000020
1529//#define CPU_GEN_PUT_CODE_OK 0x00000080
1530//#define CPU_GEN_BB_RST 0x00000100
1531//#define CPU_GEN_PWR_STB_CPU 0x00000004
1532//#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
1533//#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
1534
1535//----------------------------------------------------------------------------
1536// 8192S EEROM
1537//----------------------------------------------------------------------------
1538
1539//#define RTL8190_EEPROM_ID 0x8129
1540//#define EEPROM_VID 0x08
1541//#define EEPROM_PID 0x0A
1542//#define EEPROM_USB_OPTIONAL 0x0C
1543//#define EEPROM_NODE_ADDRESS_BYTE_0 0x12
1544//
1545//#define EEPROM_TxPowerDiff 0x1F
1546//#define EEPROM_ThermalMeter 0x20
1547//#define EEPROM_PwDiff 0x21 //0x21
1548//#define EEPROM_CrystalCap 0x22 //0x22
1549//
1550//#define EEPROM_TxPwIndex_CCK 0x23 //0x23
1551//#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26
1552#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B
1553#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E
1554#define EEPROM_TxPwIndex_Ver 0x27 //0x27
1555//
1556//#define EEPROM_Default_TxPowerDiff 0x0
1557//#define EEPROM_Default_ThermalMeter 0x7
1558//#define EEPROM_Default_PwDiff 0x4
1559//#define EEPROM_Default_CrystalCap 0x5
1560//#define EEPROM_Default_TxPower 0x1010
1561//#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
1562//#define EEPROM_Version 0x50 // 0x50
1563//#define EEPROM_CustomID 0x52
1564//#define EEPROM_ChannelPlan 0x7c //0x7C
1565//#define EEPROM_IC_VER 0x7d //0x7D
1566//#define EEPROM_CRC 0x7e //0x7E~0x7F
1567//
1568//
1569//#define EEPROM_CID_DEFAULT 0x0
1570//#define EEPROM_CID_CAMEO 0x1
1571//#define EEPROM_CID_RUNTOP 0x2
1572//#define EEPROM_CID_Senao 0x3
1573//#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31
1574//#define EEPROM_CID_NetCore 0x5
1575
1576
1577//
1578//--------------92SU require delete or move to other place later
1579//
1580
1581//============================================================
1582// CCX Related Register
1583//============================================================
1584#define CCX_COMMAND_REG 0x890
1585// CCX Measurement Command Register. 4 Bytes.
1586// Bit[0]: R_CLM_En, 1=enable, 0=disable. Enable or disable "Channel Load
1587// Measurement (CLM)".
1588// Bit[1]: R_NHM_En, 1=enable, 0=disable. Enable or disalbe "Noise Histogram
1589// Measurement (NHM)".
1590// Bit[2~7]: Reserved
1591// Bit[8]: R_CCX_En: 1=enable, 0=disable. Enable or disable CCX function.
1592// Note: After clearing this bit, all the result of all NHM_Result and CLM_
1593// Result are cleared concurrently.
1594// Bit[9]: R_Ignore_CCA: 1=enable, 0=disable. Enable means that treat CCA
1595// period as idle time for NHM.
1596// Bit[10]: R_Ignore_TXON: 1=enable, 0=disable. Enable means that treat TXON
1597// period as idle time for NHM.
1598// Bit[11~31]: Reserved.
1599#define CLM_PERIOD_REG 0x894
1600// CCX Measurement Period Register, in unit of 4us. 2 Bytes.
1601#define NHM_PERIOD_REG 0x896
1602// Noise Histogram Measurement Period Register, in unit of 4us. 2Bytes.
1603#define NHM_THRESHOLD0 0x898 // Noise Histogram Meashorement0
1604#define NHM_THRESHOLD1 0x899 // Noise Histogram Meashorement1
1605#define NHM_THRESHOLD2 0x89A // Noise Histogram Meashorement2
1606#define NHM_THRESHOLD3 0x89B // Noise Histogram Meashorement3
1607#define NHM_THRESHOLD4 0x89C // Noise Histogram Meashorement4
1608#define NHM_THRESHOLD5 0x89D // Noise Histogram Meashorement5
1609#define NHM_THRESHOLD6 0x89E // Noise Histogram Meashorement6
1610#define CLM_RESULT_REG 0x8D0
1611// Channel Load result register. 4 Bytes.
1612// Bit[0~15]: Total measured duration of CLM. The CCA busy fraction is caculate
1613// by CLM_RESULT_REG/CLM_PERIOD_REG.
1614// Bit[16]: Indicate the CLM result is ready.
1615// Bit[17~31]: Reserved.
1616#define NHM_RESULT_REG 0x8D4
1617// Noise Histogram result register. 4 Bytes.
1618// Bit[0~15]: Total measured duration of NHM. If R_Ignore_CCA=1 or
1619// R_Ignore_TXON=1, this value will be less than NHM_PERIOD_REG.
1620// Bit[16]: Indicate the NHM result is ready.
1621// Bit[17~31]: Reserved.
1622#define NHM_RPI_COUNTER0 0x8D8
1623// NHM RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
1624#define NHM_RPI_COUNTER1 0x8D9
1625// NHM RPI counter1, the fraction of signal stren in NHM_THRESH0, NHM_THRESH1
1626#define NHM_RPI_COUNTER2 0x8DA
1627// NHM RPI counter2, the fraction of signal stren in NHM_THRESH2, NHM_THRESH3
1628#define NHM_RPI_COUNTER3 0x8DB
1629// NHM RPI counter3, the fraction of signal stren in NHM_THRESH4, NHM_THRESH5
1630#define NHM_RPI_COUNTER4 0x8DC
1631// NHM RPI counter4, the fraction of signal stren in NHM_THRESH6, NHM_THRESH7
1632#define NHM_RPI_COUNTER5 0x8DD
1633// NHM RPI counter5, the fraction of signal stren in NHM_THRESH8, NHM_THRESH9
1634#define NHM_RPI_COUNTER6 0x8DE
1635// NHM RPI counter6, the fraction of signal stren in NHM_THRESH10, NHM_THRESH11
1636#define NHM_RPI_COUNTER7 0x8DF
1637// NHM RPI counter7, the fraction of signal stren in NHM_THRESH12, NHM_THRESH13
1638
1639#define HAL_RETRY_LIMIT_INFRA 48
1640#define HAL_RETRY_LIMIT_AP_ADHOC 7
1641
1642// HW Readio OFF switch (GPIO BIT)
1643#define HAL_8192S_HW_GPIO_OFF_BIT BIT3
1644#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
1645#define HAL_8192S_HW_GPIO_WPS_BIT BIT4
1646
1647#endif //R8192S_HW
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
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diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c
new file mode 100644
index 00000000000..99a4051a845
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_phy.c
@@ -0,0 +1,5028 @@
1/******************************************************************************
2
3 (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4
5 Module: hal8192sphy.c
6
7 Note: Merge 92SE/SU PHY config as below
8 1. BB register R/W API
9 2. RF register R/W API
10 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
11 3. Power setting API
12 4. Channel switch API
13 5. Initial gain switch API.
14 6. Other BB/MAC/RF API.
15
16 Function: PHY: Extern function, phy: local function
17
18 Export: PHY_FunctionName
19
20 Abbrev: NONE
21
22 History:
23 Data Who Remark
24 08/08/2008 MHC 1. Port from 9x series phycfg.c
25 2. Reorganize code arch and ad description.
26 3. Collect similar function.
27 4. Seperate extern/local API.
28 08/12/2008 MHC We must merge or move USB PHY relative function later.
29 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!)
30 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register
31 area to map with EEPROM/EFUSE tx pwr index.
32
33******************************************************************************/
34#include "r8192U.h"
35#include "r8192U_dm.h"
36#include "r8192S_rtl6052.h"
37
38#ifdef RTL8192SU
39#include "r8192S_hw.h"
40#include "r8192S_phy.h"
41#include "r8192S_phyreg.h"
42#include "r8192SU_HWImg.h"
43//#include "r8192S_FwImgDTM.h"
44#else
45#include "r8192U_hw.h"
46#include "r819xU_phy.h"
47#include "r819xU_phyreg.h"
48#endif
49
50#ifdef ENABLE_DOT11D
51#include "dot11d.h"
52#endif
53
54/*---------------------------Define Local Constant---------------------------*/
55/* Channel switch:The size of command tables for switch channel*/
56#define MAX_PRECMD_CNT 16
57#define MAX_RFDEPENDCMD_CNT 16
58#define MAX_POSTCMD_CNT 16
59#define MAX_DOZE_WAITING_TIMES_9x 64
60
61/*------------------------Define local variable------------------------------*/
62// 2004-05-11
63#ifndef RTL8192SU
64static u32 RF_CHANNEL_TABLE_ZEBRA[]={
65 0,
66 0x085c,//2412 1
67 0x08dc,//2417 2
68 0x095c,//2422 3
69 0x09dc,//2427 4
70 0x0a5c,//2432 5
71 0x0adc,//2437 6
72 0x0b5c,//2442 7
73 0x0bdc,//2447 8
74 0x0c5c,//2452 9
75 0x0cdc,//2457 10
76 0x0d5c,//2462 11
77 0x0ddc,//2467 12
78 0x0e5c,//2472 13
79 //0x0f5c,//2484
80 0x0f72,//2484 //20040810
81};
82#endif
83
84static u32
85phy_CalculateBitShift(u32 BitMask);
86static RT_STATUS
87phy_ConfigMACWithHeaderFile(struct net_device* dev);
88static void
89phy_InitBBRFRegisterDefinition(struct net_device* dev);
90static RT_STATUS
91phy_BB8192S_Config_ParaFile(struct net_device* dev);
92static RT_STATUS
93phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
94static bool
95phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
96void
97SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
98void
99SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
100void
101SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
102static void
103phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
104static bool
105phy_SwChnlStepByStep(
106 struct net_device* dev,
107 u8 channel,
108 u8 *stage,
109 u8 *step,
110 u32 *delay
111 );
112static RT_STATUS
113phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
114#ifdef RTL8192SE
115static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
116static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
117static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
118static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
119#endif
120static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
121static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
122void phy_SetFwCmdIOCallback(struct net_device* dev);
123
124//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
125#ifdef RTL8192SU
126//
127// Description:
128// Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
129//
130// Assumption:
131// - Only use on RTL8192S USB interface.
132// - PASSIVE LEVEL
133//
134// Created by Roger, 2008.09.06.
135//
136//use in phy only
137u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr)
138{
139 struct r8192_priv *priv = ieee80211_priv(dev);
140 u32 ReturnValue = 0xffffffff;
141 u8 PollingCnt = 50;
142 u8 BBWaitCounter = 0;
143
144
145 //
146 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
147 // We have to make sure that previous BB I/O has been done.
148 // 2008.08.20.
149 //
150 while(priv->bChangeBBInProgress)
151 {
152 BBWaitCounter ++;
153 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
154 msleep(1); // 1 ms
155
156 // Wait too long, return FALSE to avoid to be stuck here.
157 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
158 {
159 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
160 return ReturnValue;
161 }
162 }
163
164 priv->bChangeBBInProgress = true;
165
166 read_nic_dword(dev, RegAddr);
167
168 do
169 {// Make sure that access could be done.
170 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
171 break;
172 }while( --PollingCnt );
173
174 if(PollingCnt == 0)
175 {
176 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
177 }
178 else
179 {
180 // Data FW read back.
181 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
182 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
183 }
184
185 priv->bChangeBBInProgress = false;
186
187 return ReturnValue;
188}
189
190
191
192//
193// Description:
194// Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
195//
196// Assumption:
197// - Only use on RTL8192S USB interface.
198// - PASSIVE LEVEL
199//
200// Created by Roger, 2008.09.06.
201//
202//use in phy only
203void
204phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data)
205{
206 struct r8192_priv *priv = ieee80211_priv(dev);
207 u8 BBWaitCounter = 0;
208
209 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
210
211 //
212 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
213 // We have to make sure that previous BB I/O has been done.
214 // 2008.08.20.
215 //
216 while(priv->bChangeBBInProgress)
217 {
218 BBWaitCounter ++;
219 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
220 msleep(1); // 1 ms
221
222 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
223 {
224 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
225 return;
226 }
227 }
228
229 priv->bChangeBBInProgress = true;
230 //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
231 write_nic_dword(dev, RegAddr, Data);
232
233 priv->bChangeBBInProgress = false;
234}
235
236
237
238//
239// Description:
240// RF read by 4181 to make sure that operation could be done in unlimited cycle.
241//
242// Assumption:
243// - Only use on RTL8192S USB interface.
244// - PASSIVE LEVEL
245// - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
246//
247// Created by Roger, 2008.09.06.
248//
249//use in phy only
250u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
251{
252
253 struct r8192_priv *priv = ieee80211_priv(dev);
254 //u32 value = 0, ReturnValue = 0;
255 u32 ReturnValue = 0;
256 //u32 tmplong,tmplong2;
257 u8 PollingCnt = 50;
258 u8 RFWaitCounter = 0;
259
260
261 //
262 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
263 // We have to make sure that previous RF I/O has been done.
264 // 2008.08.20.
265 //
266 while(priv->bChangeRFInProgress)
267 {
268 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
269 //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318
270 down(&priv->rf_sem);
271
272 RFWaitCounter ++;
273 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
274 msleep(1); // 1 ms
275
276 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
277 {
278 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
279 return 0xffffffff;
280 }
281 else
282 {
283 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
284 }
285 }
286
287 priv->bChangeRFInProgress = true;
288 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
289
290
291 Offset &= 0x3f; //RF_Offset= 0x00~0x3F
292
293 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
294 (Offset<<8)| //RF_Offset= 0x00~0x3F
295 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
296
297 do
298 {// Make sure that access could be done.
299 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
300 break;
301 }while( --PollingCnt );
302
303 // Data FW read back.
304 ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
305
306 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
307 //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318
308 up(&priv->rf_sem);
309 priv->bChangeRFInProgress = false;
310
311 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
312
313 return ReturnValue;
314
315}
316
317
318//
319// Description:
320// RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
321//
322// Assumption:
323// - Only use on RTL8192S USB interface.
324// - PASSIVE LEVEL
325// - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
326//
327// Created by Roger, 2008.09.06.
328//
329//use in phy only
330void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAddr,u32 Data)
331{
332
333 struct r8192_priv *priv = ieee80211_priv(dev);
334 u8 PollingCnt = 50;
335 u8 RFWaitCounter = 0;
336
337
338 //
339 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
340 // We have to make sure that previous BB I/O has been done.
341 // 2008.08.20.
342 //
343 while(priv->bChangeRFInProgress)
344 {
345 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
346 //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318
347 down(&priv->rf_sem);
348
349 RFWaitCounter ++;
350 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
351 msleep(1); // 1 ms
352
353 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
354 {
355 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
356 return;
357 }
358 else
359 {
360 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
361 }
362 }
363
364 priv->bChangeRFInProgress = true;
365 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
366
367
368 RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
369
370 write_nic_dword(dev, RF_BB_CMD_DATA, Data);
371 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
372 (RegAddr<<8)| //RF_Offset= 0x00~0x3F
373 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
374
375 do
376 {// Make sure that access could be done.
377 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
378 break;
379 }while( --PollingCnt );
380
381 if(PollingCnt == 0)
382 {
383 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
384 }
385
386 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
387 //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318
388 up(&priv->rf_sem);
389 priv->bChangeRFInProgress = false;
390
391}
392
393#endif
394
395/*---------------------Define local function prototype-----------------------*/
396
397
398/*----------------------------Function Body----------------------------------*/
399//
400// 1. BB register R/W API
401//
402/**
403* Function: PHY_QueryBBReg
404*
405* OverView: Read "sepcific bits" from BB register
406*
407* Input:
408* PADAPTER Adapter,
409* u32 RegAddr, //The target address to be readback
410* u32 BitMask //The target bit position in the target address
411* //to be readback
412* Output: None
413* Return: u32 Data //The readback register value
414* Note: This function is equal to "GetRegSetting" in PHY programming guide
415*/
416//use phy dm core 8225 8256 6052
417//u32 PHY_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask)
418u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
419{
420
421 u32 ReturnValue = 0, OriginalValue, BitShift;
422
423#if (DISABLE_BB_RF == 1)
424 return 0;
425#endif
426
427 RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
428
429 //
430 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
431 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
432 // infinite cycle.
433 // 2008.09.06.
434 //
435//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
436#ifdef RTL8192SU
437 if(IS_BB_REG_OFFSET_92S(RegAddr))
438 {
439 //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
440
441 if((RegAddr & 0x03) != 0)
442 {
443 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
444 return 0;
445 }
446
447 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
448 }
449 else
450#endif
451 {
452 OriginalValue = read_nic_dword(dev, RegAddr);
453 }
454
455 BitShift = phy_CalculateBitShift(BitMask);
456 ReturnValue = (OriginalValue & BitMask) >> BitShift;
457
458 //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
459 RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
460 return (ReturnValue);
461}
462
463/**
464* Function: PHY_SetBBReg
465*
466* OverView: Write "Specific bits" to BB register (page 8~)
467*
468* Input:
469* PADAPTER Adapter,
470* u32 RegAddr, //The target address to be modified
471* u32 BitMask //The target bit position in the target address
472* //to be modified
473* u32 Data //The new register value in the target bit position
474* //of the target address
475*
476* Output: None
477* Return: None
478* Note: This function is equal to "PutRegSetting" in PHY programming guide
479*/
480//use phy dm core 8225 8256
481//void PHY_SetBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask, u32 Data )
482void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
483{
484 u32 OriginalValue, BitShift, NewValue;
485
486#if (DISABLE_BB_RF == 1)
487 return;
488#endif
489
490 RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
491
492 //
493 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
494 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
495 // infinite cycle.
496 // 2008.09.06.
497 //
498//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
499#ifdef RTL8192SU
500 if(IS_BB_REG_OFFSET_92S(RegAddr))
501 {
502 if((RegAddr & 0x03) != 0)
503 {
504 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
505 return;
506 }
507
508 if(BitMask!= bMaskDWord)
509 {//if not "double word" write
510 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
511 BitShift = phy_CalculateBitShift(BitMask);
512 NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
513 phy_SetUsbBBReg(dev, RegAddr, NewValue);
514 }else
515 phy_SetUsbBBReg(dev, RegAddr, Data);
516 }
517 else
518#endif
519 {
520 if(BitMask!= bMaskDWord)
521 {//if not "double word" write
522 OriginalValue = read_nic_dword(dev, RegAddr);
523 BitShift = phy_CalculateBitShift(BitMask);
524 NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
525 write_nic_dword(dev, RegAddr, NewValue);
526 }else
527 write_nic_dword(dev, RegAddr, Data);
528 }
529
530 //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
531
532 return;
533}
534
535
536//
537// 2. RF register R/W API
538//
539/**
540* Function: PHY_QueryRFReg
541*
542* OverView: Query "Specific bits" to RF register (page 8~)
543*
544* Input:
545* PADAPTER Adapter,
546* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
547* u32 RegAddr, //The target address to be read
548* u32 BitMask //The target bit position in the target address
549* //to be read
550*
551* Output: None
552* Return: u32 Readback value
553* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
554*/
555//in dm 8256 and phy
556//u32 PHY_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
557u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
558{
559 u32 Original_Value, Readback_Value, BitShift;//, flags;
560 struct r8192_priv *priv = ieee80211_priv(dev);
561
562#if (DISABLE_BB_RF == 1)
563 return 0;
564#endif
565
566 RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
567
568 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
569 {
570 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
571 return 0;
572 }
573
574 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
575 {
576 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
577 return 0;
578 }
579
580 /* 2008/01/17 MH We get and release spin lock when reading RF register. */
581 //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
582 //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113
583 down(&priv->rf_sem);
584 //
585 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
586 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
587 // infinite cycle.
588 // 2008.09.06.
589 //
590//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
591#ifdef RTL8192SU
592 //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
593 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
594#else
595 if (priv->Rf_Mode == RF_OP_By_FW)
596 {
597 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
598 }
599 else
600 {
601 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
602 }
603#endif
604
605 BitShift = phy_CalculateBitShift(BitMask);
606 Readback_Value = (Original_Value & BitMask) >> BitShift;
607 //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113
608 up(&priv->rf_sem);
609 //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
610
611 //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
612
613 return (Readback_Value);
614}
615
616/**
617* Function: PHY_SetRFReg
618*
619* OverView: Write "Specific bits" to RF register (page 8~)
620*
621* Input:
622* PADAPTER Adapter,
623* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
624* u32 RegAddr, //The target address to be modified
625* u32 BitMask //The target bit position in the target address
626* //to be modified
627* u32 Data //The new register Data in the target bit position
628* //of the target address
629*
630* Output: None
631* Return: None
632* Note: This function is equal to "PutRFRegSetting" in PHY programming guide
633*/
634//use phy 8225 8256
635//void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask,u32 Data )
636void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
637{
638
639 struct r8192_priv *priv = ieee80211_priv(dev);
640 u32 Original_Value, BitShift, New_Value;//, flags;
641#if (DISABLE_BB_RF == 1)
642 return;
643#endif
644
645 RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
646 RegAddr, BitMask, Data, eRFPath);
647
648 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
649 {
650 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
651 return ;
652 }
653 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
654 {
655 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
656 return;
657 }
658
659 /* 2008/01/17 MH We get and release spin lock when writing RF register. */
660 //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
661 //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113
662 down(&priv->rf_sem);
663 //
664 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
665 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
666 // infinite cycle.
667 // 2008.09.06.
668 //
669//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
670#ifdef RTL8192SU
671 //if(RT_USB_CANNOT_IO(Adapter)) return;
672
673 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
674 {
675 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
676 BitShift = phy_CalculateBitShift(BitMask);
677 New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
678 phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
679 }
680 else
681 phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
682#else
683 if (priv->Rf_Mode == RF_OP_By_FW)
684 {
685 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
686 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
687 {
688 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
689 BitShift = phy_CalculateBitShift(BitMask);
690 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
691
692 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
693 }
694 else
695 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
696 }
697 else
698 {
699 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
700 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
701 {
702 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
703 BitShift = phy_CalculateBitShift(BitMask);
704 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
705
706 phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
707 }
708 else
709 phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
710
711 }
712#endif
713 //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
714 //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113
715 up(&priv->rf_sem);
716 //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
717 RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
718 RegAddr, BitMask, Data, eRFPath);
719
720}
721
722#ifdef RTL8192SE
723/*-----------------------------------------------------------------------------
724 * Function: phy_FwRFSerialRead()
725 *
726 * Overview: We support firmware to execute RF-R/W.
727 *
728 * Input: NONE
729 *
730 * Output: NONE
731 *
732 * Return: NONE
733 *
734 * Revised History:
735 * When Who Remark
736 * 01/21/2008 MHC Create Version 0.
737 *
738 *---------------------------------------------------------------------------*/
739//use in phy only
740static u32
741phy_FwRFSerialRead(
742 struct net_device* dev,
743 RF90_RADIO_PATH_E eRFPath,
744 u32 Offset )
745{
746 u32 retValue = 0;
747 //u32 Data = 0;
748 //u8 time = 0;
749#if 0
750 //DbgPrint("FW RF CTRL\n\r");
751 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
752 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
753 much time. This is only for site survey. */
754 // 1. Read operation need not insert data. bit 0-11
755 //Data &= bMask12Bits;
756 // 2. Write RF register address. Bit 12-19
757 Data |= ((Offset&0xFF)<<12);
758 // 3. Write RF path. bit 20-21
759 Data |= ((eRFPath&0x3)<<20);
760 // 4. Set RF read indicator. bit 22=0
761 //Data |= 0x00000;
762 // 5. Trigger Fw to operate the command. bit 31
763 Data |= 0x80000000;
764 // 6. We can not execute read operation if bit 31 is 1.
765 while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
766 {
767 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
768 if (time++ < 100)
769 {
770 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
771 delay_us(10);
772 }
773 else
774 break;
775 }
776 // 7. Execute read operation.
777 PlatformIOWrite4Byte(dev, QPNR, Data);
778 // 8. Check if firmawre send back RF content.
779 while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
780 {
781 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
782 if (time++ < 100)
783 {
784 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
785 delay_us(10);
786 }
787 else
788 return (0);
789 }
790 retValue = PlatformIORead4Byte(dev, RF_DATA);
791#endif
792 return (retValue);
793
794} /* phy_FwRFSerialRead */
795
796/*-----------------------------------------------------------------------------
797 * Function: phy_FwRFSerialWrite()
798 *
799 * Overview: We support firmware to execute RF-R/W.
800 *
801 * Input: NONE
802 *
803 * Output: NONE
804 *
805 * Return: NONE
806 *
807 * Revised History:
808 * When Who Remark
809 * 01/21/2008 MHC Create Version 0.
810 *
811 *---------------------------------------------------------------------------*/
812//use in phy only
813static void
814phy_FwRFSerialWrite(
815 struct net_device* dev,
816 RF90_RADIO_PATH_E eRFPath,
817 u32 Offset,
818 u32 Data )
819{
820#if 0
821 u8 time = 0;
822 DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
823 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
824 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
825 much time. This is only for site survey. */
826
827 // 1. Set driver write bit and 12 bit data. bit 0-11
828 //Data &= bMask12Bits; // Done by uper layer.
829 // 2. Write RF register address. bit 12-19
830 Data |= ((Offset&0xFF)<<12);
831 // 3. Write RF path. bit 20-21
832 Data |= ((eRFPath&0x3)<<20);
833 // 4. Set RF write indicator. bit 22=1
834 Data |= 0x400000;
835 // 5. Trigger Fw to operate the command. bit 31=1
836 Data |= 0x80000000;
837
838 // 6. Write operation. We can not write if bit 31 is 1.
839 while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
840 {
841 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
842 if (time++ < 100)
843 {
844 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
845 delay_us(10);
846 }
847 else
848 break;
849 }
850 // 7. No matter check bit. We always force the write. Because FW will
851 // not accept the command.
852 PlatformIOWrite4Byte(dev, QPNR, Data);
853 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
854 to finish RF write operation. */
855 /* 2008/01/17 MH We support delay in firmware side now. */
856 //delay_us(20);
857#endif
858} /* phy_FwRFSerialWrite */
859
860/**
861* Function: phy_RFSerialRead
862*
863* OverView: Read regster from RF chips
864*
865* Input:
866* PADAPTER Adapter,
867* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
868* u32 Offset, //The target address to be read
869*
870* Output: None
871* Return: u32 reback value
872* Note: Threre are three types of serial operations:
873* 1. Software serial write
874* 2. Hardware LSSI-Low Speed Serial Interface
875* 3. Hardware HSSI-High speed
876* serial write. Driver need to implement (1) and (2).
877* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
878*/
879//use in phy only
880static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
881{
882
883 u32 retValue = 0;
884 struct r8192_priv *priv = ieee80211_priv(dev);
885 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
886 u32 NewOffset;
887 u8 RfPiEnable=0;
888
889
890 //
891 // Make sure RF register offset is correct
892 //
893 Offset &= 0x3f;
894
895 //
896 // Switch page for 8256 RF IC
897 //
898 if( priv->rf_chip == RF_8256 ||
899 priv->rf_chip == RF_8225 ||
900 priv->rf_chip == RF_6052)
901 {
902 //analog to digital off, for protection
903 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
904
905 if(Offset>=31)
906 {
907 priv->RFReadPageCnt[2]++;//cosa add for debug
908 priv->RfReg0Value[eRFPath] |= 0x140;
909
910 // Switch to Reg_Mode2 for Reg31~45
911 rtl8192_setBBreg(dev,
912 pPhyReg->rf3wireOffset,
913 bMaskDWord,
914 (priv->RfReg0Value[eRFPath] << 16) );
915
916 // Modified Offset
917 NewOffset = Offset - 30;
918
919 }else if(Offset>=16)
920 {
921 priv->RFReadPageCnt[1]++;//cosa add for debug
922 priv->RfReg0Value[eRFPath] |= 0x100;
923 priv->RfReg0Value[eRFPath] &= (~0x40);
924
925 // Switch to Reg_Mode1 for Reg16~30
926 rtl8192_setBBreg(dev,
927 pPhyReg->rf3wireOffset,
928 bMaskDWord,
929 (priv->RfReg0Value[eRFPath] << 16) );
930
931 // Modified Offset
932 NewOffset = Offset - 15;
933 }
934 else
935 {
936 priv->RFReadPageCnt[0]++;//cosa add for debug
937 NewOffset = Offset;
938 }
939 }
940 else
941 NewOffset = Offset;
942
943 //
944 // Put desired read address to LSSI control register
945 //
946 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
947
948 //
949 // Issue a posedge trigger
950 //
951 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
952 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
953
954 // TODO: we should not delay such a long time. Ask help from SD3
955 mdelay(1);
956
957 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
958
959 // Switch back to Reg_Mode0;
960 if( priv->rf_chip == RF_8256 ||
961 priv->rf_chip == RF_8225 ||
962 priv->rf_chip == RF_0222D)
963 {
964 if (Offset >= 0x10)
965 {
966 priv->RfReg0Value[eRFPath] &= 0xebf;
967
968 rtl8192_setBBreg(
969 dev,
970 pPhyReg->rf3wireOffset,
971 bMaskDWord,
972 (priv->RfReg0Value[eRFPath] << 16) );
973 }
974
975 //analog to digital on
976 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
977 }
978
979 return retValue;
980}
981
982
983
984/**
985* Function: phy_RFSerialWrite
986*
987* OverView: Write data to RF register (page 8~)
988*
989* Input:
990* PADAPTER Adapter,
991* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
992* u32 Offset, //The target address to be read
993* u32 Data //The new register Data in the target bit position
994* //of the target to be read
995*
996* Output: None
997* Return: None
998* Note: Threre are three types of serial operations:
999* 1. Software serial write
1000* 2. Hardware LSSI-Low Speed Serial Interface
1001* 3. Hardware HSSI-High speed
1002* serial write. Driver need to implement (1) and (2).
1003* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
1004 *
1005 * Note: For RF8256 only
1006 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1007 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1008 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1009 * programming guide" for more details.
1010 * Thus, we define a sub-finction for RTL8526 register address conversion
1011 * ===========================================================
1012 * Register Mode RegCTL[1] RegCTL[0] Note
1013 * (Reg00[12]) (Reg00[10])
1014 * ===========================================================
1015 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1016 * ------------------------------------------------------------------
1017 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1018 * ------------------------------------------------------------------
1019 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1020 * ------------------------------------------------------------------
1021*/
1022////use in phy only
1023static void
1024phy_RFSerialWrite(
1025 struct net_device* dev,
1026 RF90_RADIO_PATH_E eRFPath,
1027 u32 Offset,
1028 u32 Data
1029 )
1030{
1031 u32 DataAndAddr = 0;
1032 struct r8192_priv *priv = ieee80211_priv(dev);
1033 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1034 u32 NewOffset;
1035
1036 Offset &= 0x3f;
1037
1038 // Shadow Update
1039 PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1040
1041
1042 // Switch page for 8256 RF IC
1043 if( priv->rf_chip == RF_8256 ||
1044 priv->rf_chip == RF_8225 ||
1045 priv->rf_chip == RF_0222D)
1046 {
1047 //analog to digital off, for protection
1048 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1049
1050 if(Offset>=31)
1051 {
1052 priv->RFWritePageCnt[2]++;//cosa add for debug
1053 priv->RfReg0Value[eRFPath] |= 0x140;
1054
1055 rtl8192_setBBreg(dev,
1056 pPhyReg->rf3wireOffset,
1057 bMaskDWord,
1058 (priv->RfReg0Value[eRFPath] << 16) );
1059
1060 NewOffset = Offset - 30;
1061
1062 }else if(Offset>=16)
1063 {
1064 priv->RFWritePageCnt[1]++;//cosa add for debug
1065 priv->RfReg0Value[eRFPath] |= 0x100;
1066 priv->RfReg0Value[eRFPath] &= (~0x40);
1067
1068
1069 rtl8192_setBBreg(dev,
1070 pPhyReg->rf3wireOffset,
1071 bMaskDWord,
1072 (priv->RfReg0Value[eRFPath] << 16) );
1073
1074 NewOffset = Offset - 15;
1075 }
1076 else
1077 {
1078 priv->RFWritePageCnt[0]++;//cosa add for debug
1079 NewOffset = Offset;
1080 }
1081 }
1082 else
1083 NewOffset = Offset;
1084
1085 //
1086 // Put write addr in [5:0] and write data in [31:16]
1087 //
1088 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1089
1090 //
1091 // Write Operation
1092 //
1093 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1094
1095
1096 if(Offset==0x0)
1097 priv->RfReg0Value[eRFPath] = Data;
1098
1099 // Switch back to Reg_Mode0;
1100 if( priv->rf_chip == RF_8256 ||
1101 priv->rf_chip == RF_8225 ||
1102 priv->rf_chip == RF_0222D)
1103 {
1104 if (Offset >= 0x10)
1105 {
1106 if(Offset != 0)
1107 {
1108 priv->RfReg0Value[eRFPath] &= 0xebf;
1109 rtl8192_setBBreg(
1110 dev,
1111 pPhyReg->rf3wireOffset,
1112 bMaskDWord,
1113 (priv->RfReg0Value[eRFPath] << 16) );
1114 }
1115 }
1116 //analog to digital on
1117 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1118 }
1119
1120}
1121#else
1122/**
1123* Function: phy_RFSerialRead
1124*
1125* OverView: Read regster from RF chips
1126*
1127* Input:
1128* PADAPTER Adapter,
1129* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
1130* u4Byte Offset, //The target address to be read
1131*
1132* Output: None
1133* Return: u4Byte reback value
1134* Note: Threre are three types of serial operations:
1135* 1. Software serial write
1136* 2. Hardware LSSI-Low Speed Serial Interface
1137* 3. Hardware HSSI-High speed
1138* serial write. Driver need to implement (1) and (2).
1139* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
1140*/
1141#if 0
1142static u32
1143phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
1144{
1145
1146 u32 retValue = 0;
1147 struct r8192_priv *priv = ieee80211_priv(dev);
1148 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1149 u32 NewOffset;
1150 //u32 value = 0;
1151 u32 tmplong,tmplong2;
1152 u32 RfPiEnable=0;
1153#if 0
1154 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1155 return retValue;
1156 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1157 return retValue;
1158#endif
1159 //
1160 // Make sure RF register offset is correct
1161 //
1162 Offset &= 0x3f;
1163
1164 //
1165 // Switch page for 8256 RF IC
1166 //
1167 NewOffset = Offset;
1168
1169 // For 92S LSSI Read RFLSSIRead
1170 // For RF A/B write 0x824/82c(does not work in the future)
1171 // We must use 0x824 for RF A and B to execute read trigger
1172 tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
1173 tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
1174 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
1175
1176 rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
1177 mdelay(1);
1178
1179 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
1180 mdelay(1);
1181
1182 rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
1183 mdelay(1);
1184
1185 if(eRFPath == RF90_PATH_A)
1186 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
1187 else if(eRFPath == RF90_PATH_B)
1188 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
1189
1190 if(RfPiEnable)
1191 { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
1192 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
1193 //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
1194 }
1195 else
1196 { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
1197 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1198 //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
1199 }
1200 //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
1201
1202 return retValue;
1203
1204}
12054
1206
1207
1208/**
1209* Function: phy_RFSerialWrite
1210*
1211* OverView: Write data to RF register (page 8~)
1212*
1213* Input:
1214* PADAPTER Adapter,
1215* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
1216* u4Byte Offset, //The target address to be read
1217* u4Byte Data //The new register Data in the target bit position
1218* //of the target to be read
1219*
1220* Output: None
1221* Return: None
1222* Note: Threre are three types of serial operations:
1223* 1. Software serial write
1224* 2. Hardware LSSI-Low Speed Serial Interface
1225* 3. Hardware HSSI-High speed
1226* serial write. Driver need to implement (1) and (2).
1227* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
1228 *
1229 * Note: For RF8256 only
1230 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1231 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1232 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1233 * programming guide" for more details.
1234 * Thus, we define a sub-finction for RTL8526 register address conversion
1235 * ===========================================================
1236 * Register Mode RegCTL[1] RegCTL[0] Note
1237 * (Reg00[12]) (Reg00[10])
1238 * ===========================================================
1239 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1240 * ------------------------------------------------------------------
1241 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1242 * ------------------------------------------------------------------
1243 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1244 * ------------------------------------------------------------------
1245 *
1246 * 2008/09/02 MH Add 92S RF definition
1247 *
1248 *
1249 *
1250*/
1251static void
1252phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data)
1253{
1254 u32 DataAndAddr = 0;
1255 struct r8192_priv *priv = ieee80211_priv(dev);
1256 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1257 u32 NewOffset;
1258
1259#if 0
1260 //<Roger_TODO> We should check valid regs for RF_6052 case.
1261 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1262 return;
1263 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1264 return;
1265#endif
1266
1267 Offset &= 0x3f;
1268
1269 //
1270 // Shadow Update
1271 //
1272 PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1273
1274 //
1275 // Switch page for 8256 RF IC
1276 //
1277 NewOffset = Offset;
1278
1279 //
1280 // Put write addr in [5:0] and write data in [31:16]
1281 //
1282 //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1283 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
1284
1285 //
1286 // Write Operation
1287 //
1288 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1289 //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
1290
1291}
1292#endif
1293#endif
1294
1295/**
1296* Function: phy_CalculateBitShift
1297*
1298* OverView: Get shifted position of the BitMask
1299*
1300* Input:
1301* u32 BitMask,
1302*
1303* Output: none
1304* Return: u32 Return the shift bit bit position of the mask
1305*/
1306//use in phy only
1307static u32 phy_CalculateBitShift(u32 BitMask)
1308{
1309 u32 i;
1310
1311 for(i=0; i<=31; i++)
1312 {
1313 if ( ((BitMask>>i) & 0x1 ) == 1)
1314 break;
1315 }
1316
1317 return (i);
1318}
1319
1320
1321//
1322// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
1323//
1324/*-----------------------------------------------------------------------------
1325 * Function: PHY_MACConfig8192S
1326 *
1327 * Overview: Condig MAC by header file or parameter file.
1328 *
1329 * Input: NONE
1330 *
1331 * Output: NONE
1332 *
1333 * Return: NONE
1334 *
1335 * Revised History:
1336 * When Who Remark
1337 * 08/12/2008 MHC Create Version 0.
1338 *
1339 *---------------------------------------------------------------------------*/
1340//adapter_start
1341extern bool PHY_MACConfig8192S(struct net_device* dev)
1342{
1343 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1344
1345 //
1346 // Config MAC
1347 //
1348#if RTL8190_Download_Firmware_From_Header
1349 rtStatus = phy_ConfigMACWithHeaderFile(dev);
1350#else
1351 // Not make sure EEPROM, add later
1352 RT_TRACE(COMP_INIT, "Read MACREG.txt\n");
1353 //rtStatus = phy_ConfigMACWithParaFile(dev, RTL819X_PHY_MACREG);// lzm del it temp
1354#endif
1355 return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
1356
1357}
1358
1359//adapter_start
1360extern bool
1361PHY_BBConfig8192S(struct net_device* dev)
1362{
1363 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1364
1365 u8 PathMap = 0, index = 0, rf_num = 0;
1366 struct r8192_priv *priv = ieee80211_priv(dev);
1367 phy_InitBBRFRegisterDefinition(dev);
1368
1369 //
1370 // Config BB and AGC
1371 //
1372 //switch( Adapter->MgntInfo.bRegHwParaFile )
1373 //{
1374 // case 0:
1375 // phy_BB8190_Config_HardCode(dev);
1376 // break;
1377
1378 // case 1:
1379 rtStatus = phy_BB8192S_Config_ParaFile(dev);
1380 // break;
1381
1382 // case 2:
1383 // Partial Modify.
1384 // phy_BB8190_Config_HardCode(dev);
1385 // phy_BB8192S_Config_ParaFile(dev);
1386 // break;
1387
1388 // default:
1389 // phy_BB8190_Config_HardCode(dev);
1390 // break;
1391 //}
1392 PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
1393 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
1394 priv->rf_pathmap = PathMap;
1395 for(index = 0; index<4; index++)
1396 {
1397 if((PathMap>>index)&0x1)
1398 rf_num++;
1399 }
1400
1401 if((priv->rf_type==RF_1T1R && rf_num!=1) ||
1402 (priv->rf_type==RF_1T2R && rf_num!=2) ||
1403 (priv->rf_type==RF_2T2R && rf_num!=2) ||
1404 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
1405 (priv->rf_type==RF_2T4R && rf_num!=4))
1406 {
1407 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
1408 }
1409 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1410}
1411
1412//adapter_start
1413extern bool
1414PHY_RFConfig8192S(struct net_device* dev)
1415{
1416 struct r8192_priv *priv = ieee80211_priv(dev);
1417 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1418
1419 //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
1420
1421 //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
1422 priv->rf_chip = RF_6052;
1423
1424 //
1425 // RF config
1426 //
1427 switch(priv->rf_chip)
1428 {
1429 case RF_8225:
1430 case RF_6052:
1431 rtStatus = PHY_RF6052_Config(dev);
1432 break;
1433
1434 case RF_8256:
1435 //rtStatus = PHY_RF8256_Config(dev);
1436 break;
1437
1438 case RF_8258:
1439 break;
1440
1441 case RF_PSEUDO_11N:
1442 //rtStatus = PHY_RF8225_Config(dev);
1443 break;
1444 default:
1445 break;
1446 }
1447
1448 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1449}
1450
1451
1452// Joseph test: new initialize order!!
1453// Test only!! This part need to be re-organized.
1454// Now it is just for 8256.
1455//use in phy only
1456#ifdef TO_DO_LIST
1457static RT_STATUS
1458phy_BB8190_Config_HardCode(struct net_device* dev)
1459{
1460 //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1461 return RT_STATUS_SUCCESS;
1462}
1463#endif
1464
1465/*-----------------------------------------------------------------------------
1466 * Function: phy_SetBBtoDiffRFWithHeaderFile()
1467 *
1468 * Overview: This function
1469 *
1470 *
1471 * Input: PADAPTER Adapter
1472 * u1Byte ConfigType 0 => PHY_CONFIG
1473 *
1474 * Output: NONE
1475 *
1476 * Return: RT_STATUS_SUCCESS: configuration file exist
1477 * When Who Remark
1478 * 2008/11/10 tynli
1479 * use in phy only
1480 *---------------------------------------------------------------------------*/
1481static RT_STATUS
1482phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
1483{
1484 int i;
1485 struct r8192_priv *priv = ieee80211_priv(dev);
1486 u32* Rtl819XPHY_REGArraytoXTXR_Table;
1487 u16 PHY_REGArraytoXTXRLen;
1488
1489//#if (HAL_CODE_BASE != RTL8192_S)
1490
1491 if(priv->rf_type == RF_1T1R)
1492 {
1493 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
1494 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
1495 }
1496 else if(priv->rf_type == RF_1T2R)
1497 {
1498 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
1499 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
1500 }
1501 //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
1502 //{
1503 // Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
1504 // PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
1505 //}
1506 else
1507 {
1508 return RT_STATUS_FAILURE;
1509 }
1510
1511 if(ConfigType == BaseBand_Config_PHY_REG)
1512 {
1513 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
1514 {
1515 if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
1516 mdelay(50);
1517 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
1518 mdelay(5);
1519 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
1520 mdelay(1);
1521 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
1522 udelay(50);
1523 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
1524 udelay(5);
1525 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
1526 udelay(1);
1527 rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1528 //RT_TRACE(COMP_SEND,
1529 //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
1530 //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1531 }
1532 }
1533 else {
1534 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1535 }
1536//#endif // #if (HAL_CODE_BASE != RTL8192_S)
1537 return RT_STATUS_SUCCESS;
1538}
1539
1540
1541//use in phy only
1542static RT_STATUS
1543phy_BB8192S_Config_ParaFile(struct net_device* dev)
1544{
1545 struct r8192_priv *priv = ieee80211_priv(dev);
1546 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1547 //u8 u2RegValue;
1548 //u16 u4RegValue;
1549 //char szBBRegFile[] = RTL819X_PHY_REG;
1550 //char szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
1551 //char szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1552 //char szAGCTableFile[] = RTL819X_AGC_TAB;
1553 //char szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
1554 //char szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
1555
1556 RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
1557
1558 //
1559 // 1. Read PHY_REG.TXT BB INIT!!
1560 // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
1561 //
1562#if RTL8190_Download_Firmware_From_Header
1563 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1564 priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1565 {
1566 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1567 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1568 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1569 //so we should reconfig BB reg with the right PHY parameters.
1570 rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1571 }
1572 }else
1573 rtStatus = RT_STATUS_FAILURE;
1574#else
1575 RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type);
1576 // No matter what kind of RF we always read PHY_REG.txt. We must copy different
1577 // type of parameter files to phy_reg.txt at first.
1578 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1579 priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1580 {
1581 rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile);
1582 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1583 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1584 //so we should reconfig BB reg with the right PHY parameters.
1585 if(priv->rf_type == RF_1T1R)
1586 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile);
1587 else if(priv->rf_type == RF_1T2R)
1588 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile);
1589 }
1590
1591 }else
1592 rtStatus = RT_STATUS_FAILURE;
1593#endif
1594
1595 if(rtStatus != RT_STATUS_SUCCESS){
1596 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
1597 goto phy_BB8190_Config_ParaFile_Fail;
1598 }
1599
1600 //
1601 // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1602 //
1603 if (priv->AutoloadFailFlag == false)
1604 {
1605#if RTL8190_Download_Firmware_From_Header
1606 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
1607#else
1608 rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile);
1609#endif
1610 }
1611 if(rtStatus != RT_STATUS_SUCCESS){
1612 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
1613 goto phy_BB8190_Config_ParaFile_Fail;
1614 }
1615
1616 //
1617 // 3. BB AGC table Initialization
1618 //
1619#if RTL8190_Download_Firmware_From_Header
1620 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
1621#else
1622 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n");
1623 rtStatus = phy_ConfigBBWithParaFile(Adapter, (char* )&szAGCTableFile);
1624#endif
1625
1626 if(rtStatus != RT_STATUS_SUCCESS){
1627 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
1628 goto phy_BB8190_Config_ParaFile_Fail;
1629 }
1630
1631
1632#if 0 // 2008/08/18 MH Disable for 92SE
1633 if(pHalData->VersionID > VERSION_8190_BD)
1634 {
1635 //if(pHalData->RF_Type == RF_2T4R)
1636 //{
1637 // Antenna gain offset from B/C/D to A
1638 u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 |
1639 pHalData->AntennaTxPwDiff[1]<<4 |
1640 pHalData->AntennaTxPwDiff[0]);
1641 //}
1642 //else
1643 //u4RegValue = 0;
1644
1645 PHY_SetBBReg(dev, rFPGA0_TxGainStage,
1646 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1647
1648 // CrystalCap
1649 // Simulate 8192???
1650 u4RegValue = pHalData->CrystalCap;
1651 PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
1652 // Simulate 8190??
1653 //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
1654 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
1655
1656 }
1657#endif
1658
1659 // Check if the CCK HighPower is turned ON.
1660 // This is used to calculate PWDB.
1661 priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1662
1663
1664phy_BB8190_Config_ParaFile_Fail:
1665 return rtStatus;
1666}
1667
1668/*-----------------------------------------------------------------------------
1669 * Function: phy_ConfigMACWithHeaderFile()
1670 *
1671 * Overview: This function read BB parameters from Header file we gen, and do register
1672 * Read/Write
1673 *
1674 * Input: PADAPTER Adapter
1675 * char* pFileName
1676 *
1677 * Output: NONE
1678 *
1679 * Return: RT_STATUS_SUCCESS: configuration file exist
1680 *
1681 * Note: The format of MACPHY_REG.txt is different from PHY and RF.
1682 * [Register][Mask][Value]
1683 *---------------------------------------------------------------------------*/
1684//use in phy only
1685static RT_STATUS
1686phy_ConfigMACWithHeaderFile(struct net_device* dev)
1687{
1688 u32 i = 0;
1689 u32 ArrayLength = 0;
1690 u32* ptrArray;
1691 //struct r8192_priv *priv = ieee80211_priv(dev);
1692
1693//#if (HAL_CODE_BASE != RTL8192_S)
1694 /*if(Adapter->bInHctTest)
1695 {
1696 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
1697 ArrayLength = MACPHY_ArrayLengthDTM;
1698 ptrArray = Rtl819XMACPHY_ArrayDTM;
1699 }
1700 else if(pHalData->bTXPowerDataReadFromEEPORM)
1701 {
1702// RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
1703// ArrayLength = MACPHY_Array_PGLength;
1704// ptrArray = Rtl819XMACPHY_Array_PG;
1705
1706 }else*/
1707 { //2008.11.06 Modified by tynli.
1708 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
1709 ArrayLength = MAC_2T_ArrayLength;
1710 ptrArray = Rtl819XMAC_Array;
1711 }
1712
1713 /*for(i = 0 ;i < ArrayLength;i=i+3){
1714 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
1715 if(ptrArray[i] == 0x318)
1716 {
1717 ptrArray[i+2] = 0x00000800;
1718 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1719 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1720 }
1721 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1722 }*/
1723 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
1724 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
1725 }
1726//#endif
1727 return RT_STATUS_SUCCESS;
1728}
1729
1730/*-----------------------------------------------------------------------------
1731 * Function: phy_ConfigBBWithHeaderFile()
1732 *
1733 * Overview: This function read BB parameters from general file format, and do register
1734 * Read/Write
1735 *
1736 * Input: PADAPTER Adapter
1737 * u8 ConfigType 0 => PHY_CONFIG
1738 * 1 =>AGC_TAB
1739 *
1740 * Output: NONE
1741 *
1742 * Return: RT_STATUS_SUCCESS: configuration file exist
1743 *
1744 *---------------------------------------------------------------------------*/
1745//use in phy only
1746static RT_STATUS
1747phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1748{
1749 int i;
1750 //u8 ArrayLength;
1751 u32* Rtl819XPHY_REGArray_Table;
1752 u32* Rtl819XAGCTAB_Array_Table;
1753 u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
1754 //struct r8192_priv *priv = ieee80211_priv(dev);
1755//#if (HAL_CODE_BASE != RTL8192_S)
1756 /*if(Adapter->bInHctTest)
1757 {
1758
1759 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1760 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1761
1762 if(pHalData->RF_Type == RF_2T4R)
1763 {
1764 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1765 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1766 }
1767 else if (pHalData->RF_Type == RF_1T2R)
1768 {
1769 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1770 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1771 }
1772
1773 }
1774 else
1775 */
1776 //{
1777 //
1778 // 2008.11.06 Modified by tynli.
1779 //
1780 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1781 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1782 PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1783 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1784 //}
1785
1786 if(ConfigType == BaseBand_Config_PHY_REG)
1787 {
1788 for(i=0;i<PHY_REGArrayLen;i=i+2)
1789 {
1790 if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1791 mdelay(50);
1792 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1793 mdelay(5);
1794 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1795 mdelay(1);
1796 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1797 udelay(50);
1798 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1799 udelay(5);
1800 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1801 udelay(1);
1802 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1803 //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1804
1805 }
1806 }
1807 else if(ConfigType == BaseBand_Config_AGC_TAB){
1808 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1809 {
1810 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1811 }
1812 }
1813//#endif // #if (HAL_CODE_BASE != RTL8192_S)
1814 return RT_STATUS_SUCCESS;
1815}
1816
1817/*-----------------------------------------------------------------------------
1818 * Function: phy_ConfigBBWithPgHeaderFile
1819 *
1820 * Overview: Config PHY_REG_PG array
1821 *
1822 * Input: NONE
1823 *
1824 * Output: NONE
1825 *
1826 * Return: NONE
1827 *
1828 * Revised History:
1829 * When Who Remark
1830 * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
1831 * 11/10/2008 tynli Modify to mew files.
1832 //use in phy only
1833 *---------------------------------------------------------------------------*/
1834static RT_STATUS
1835phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1836{
1837 int i;
1838 //u8 ArrayLength;
1839 u32* Rtl819XPHY_REGArray_Table_PG;
1840 u16 PHY_REGArrayPGLen;
1841 //struct r8192_priv *priv = ieee80211_priv(dev);
1842//#if (HAL_CODE_BASE != RTL8192_S)
1843 // Default: pHalData->RF_Type = RF_2T2R.
1844
1845 PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1846 Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1847
1848 if(ConfigType == BaseBand_Config_PHY_REG)
1849 {
1850 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1851 {
1852 if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1853 mdelay(50);
1854 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1855 mdelay(5);
1856 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1857 mdelay(1);
1858 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1859 udelay(50);
1860 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1861 udelay(5);
1862 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1863 udelay(1);
1864 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1865 //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1866 // Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1867 }
1868 }else{
1869 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1870 }
1871 return RT_STATUS_SUCCESS;
1872
1873} /* phy_ConfigBBWithPgHeaderFile */
1874
1875/*-----------------------------------------------------------------------------
1876 * Function: PHY_ConfigRFWithHeaderFile()
1877 *
1878 * Overview: This function read RF parameters from general file format, and do RF 3-wire
1879 *
1880 * Input: PADAPTER Adapter
1881 * char* pFileName
1882 * RF90_RADIO_PATH_E eRFPath
1883 *
1884 * Output: NONE
1885 *
1886 * Return: RT_STATUS_SUCCESS: configuration file exist
1887 *
1888 * Note: Delay may be required for RF configuration
1889 *---------------------------------------------------------------------------*/
1890//in 8256 phy_RF8256_Config_ParaFile only
1891//RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1892u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1893{
1894
1895 struct r8192_priv *priv = ieee80211_priv(dev);
1896 int i;
1897 //u32* pRFArray;
1898 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1899 u32 *Rtl819XRadioA_Array_Table;
1900 u32 *Rtl819XRadioB_Array_Table;
1901 //u32* Rtl819XRadioC_Array_Table;
1902 //u32* Rtl819XRadioD_Array_Table;
1903 u16 RadioA_ArrayLen,RadioB_ArrayLen;
1904
1905 { //2008.11.06 Modified by tynli
1906 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1907 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1908 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1909 RadioB_ArrayLen = RadioB_ArrayLength;
1910 }
1911
1912 if( priv->rf_type == RF_2T2R_GREEN )
1913 {
1914 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1915 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1916 }
1917 else
1918 {
1919 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1920 RadioB_ArrayLen = RadioB_ArrayLength;
1921 }
1922
1923 rtStatus = RT_STATUS_SUCCESS;
1924
1925 // When initialization, we want the delay function(mdelay(), delay_us()
1926 // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1927 // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1928 // to run at Dispatch level to achive it.
1929 //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1930
1931 switch(eRFPath){
1932 case RF90_PATH_A:
1933 for(i = 0;i<RadioA_ArrayLen; i=i+2){
1934 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1935 { // Deay specific ms. Only RF configuration require delay.
1936//#if (DEV_BUS_TYPE == USB_INTERFACE)
1937#ifdef RTL8192SU
1938 mdelay(1000);
1939#else
1940 mdelay(50);
1941#endif
1942 }
1943 else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1944 mdelay(5);
1945 else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1946 mdelay(1);
1947 else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1948 udelay(50);
1949 //PlatformStallExecution(50);
1950 else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1951 udelay(5);
1952 else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1953 udelay(1);
1954 else
1955 {
1956 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1957 }
1958 }
1959 break;
1960 case RF90_PATH_B:
1961 for(i = 0;i<RadioB_ArrayLen; i=i+2){
1962 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1963 { // Deay specific ms. Only RF configuration require delay.
1964//#if (DEV_BUS_TYPE == USB_INTERFACE)
1965#ifdef RTL8192SU
1966 mdelay(1000);
1967#else
1968 mdelay(50);
1969#endif
1970 }
1971 else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1972 mdelay(5);
1973 else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1974 mdelay(1);
1975 else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1976 udelay(50);
1977 else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1978 udelay(5);
1979 else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1980 udelay(1);
1981 else
1982 {
1983 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1984 }
1985 }
1986 break;
1987 case RF90_PATH_C:
1988 break;
1989 case RF90_PATH_D:
1990 break;
1991 default:
1992 break;
1993 }
1994
1995 return rtStatus;
1996
1997}
1998
1999/*-----------------------------------------------------------------------------
2000 * Function: PHY_CheckBBAndRFOK()
2001 *
2002 * Overview: This function is write register and then readback to make sure whether
2003 * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
2004 *
2005 * Input: PADAPTER Adapter
2006 * HW90_BLOCK_E CheckBlock
2007 * RF90_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
2008 *
2009 * Output: NONE
2010 *
2011 * Return: RT_STATUS_SUCCESS: PHY is OK
2012 *
2013 * Note: This function may be removed in the ASIC
2014 *---------------------------------------------------------------------------*/
2015//in 8256 phy_RF8256_Config_HardCode
2016//but we don't use it temp
2017RT_STATUS
2018PHY_CheckBBAndRFOK(
2019 struct net_device* dev,
2020 HW90_BLOCK_E CheckBlock,
2021 RF90_RADIO_PATH_E eRFPath
2022 )
2023{
2024 //struct r8192_priv *priv = ieee80211_priv(dev);
2025 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2026 u32 i, CheckTimes = 4,ulRegRead = 0;
2027 u32 WriteAddr[4];
2028 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2029
2030 // Initialize register address offset to be checked
2031 WriteAddr[HW90_BLOCK_MAC] = 0x100;
2032 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2033 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2034 WriteAddr[HW90_BLOCK_RF] = 0x3;
2035
2036 for(i=0 ; i < CheckTimes ; i++)
2037 {
2038
2039 //
2040 // Write Data to register and readback
2041 //
2042 switch(CheckBlock)
2043 {
2044 case HW90_BLOCK_MAC:
2045 //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
2046 RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
2047 break;
2048
2049 case HW90_BLOCK_PHY0:
2050 case HW90_BLOCK_PHY1:
2051 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2052 ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2053 break;
2054
2055 case HW90_BLOCK_RF:
2056 // When initialization, we want the delay function(mdelay(), delay_us()
2057 // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
2058 // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
2059 // to run at Dispatch level to achive it.
2060 //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
2061 WriteData[i] &= 0xfff;
2062 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
2063 // TODO: we should not delay for such a long time. Ask SD3
2064 mdelay(10);
2065 ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2066 mdelay(10);
2067 //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
2068 break;
2069
2070 default:
2071 rtStatus = RT_STATUS_FAILURE;
2072 break;
2073 }
2074
2075
2076 //
2077 // Check whether readback data is correct
2078 //
2079 if(ulRegRead != WriteData[i])
2080 {
2081 //RT_TRACE(COMP_FPGA, ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
2082 RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
2083 rtStatus = RT_STATUS_FAILURE;
2084 break;
2085 }
2086 }
2087
2088 return rtStatus;
2089}
2090
2091//no use temp in windows driver
2092#ifdef TO_DO_LIST
2093void
2094PHY_SetRFPowerState8192SUsb(
2095 struct net_device* dev,
2096 RF_POWER_STATE RFPowerState
2097 )
2098{
2099 struct r8192_priv *priv = ieee80211_priv(dev);
2100 bool WaitShutDown = FALSE;
2101 u32 DWordContent;
2102 //RF90_RADIO_PATH_E eRFPath;
2103 u8 eRFPath;
2104 BB_REGISTER_DEFINITION_T *pPhyReg;
2105
2106 if(priv->SetRFPowerStateInProgress == TRUE)
2107 return;
2108
2109 priv->SetRFPowerStateInProgress = TRUE;
2110
2111 // TODO: Emily, 2006.11.21, we should rewrite this function
2112
2113 if(RFPowerState==RF_SHUT_DOWN)
2114 {
2115 RFPowerState=RF_OFF;
2116 WaitShutDown=TRUE;
2117 }
2118
2119
2120 priv->RFPowerState = RFPowerState;
2121 switch( priv->rf_chip )
2122 {
2123 case RF_8225:
2124 case RF_6052:
2125 switch( RFPowerState )
2126 {
2127 case RF_ON:
2128 break;
2129
2130 case RF_SLEEP:
2131 break;
2132
2133 case RF_OFF:
2134 break;
2135 }
2136 break;
2137
2138 case RF_8256:
2139 switch( RFPowerState )
2140 {
2141 case RF_ON:
2142 break;
2143
2144 case RF_SLEEP:
2145 break;
2146
2147 case RF_OFF:
2148 for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
2149 {
2150 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2151 continue;
2152
2153 pPhyReg = &priv->PHYRegDef[eRFPath];
2154 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
2155 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
2156 }
2157 break;
2158 }
2159 break;
2160
2161 case RF_8258:
2162 break;
2163 }// switch( priv->rf_chip )
2164
2165 priv->SetRFPowerStateInProgress = FALSE;
2166}
2167#endif
2168
2169#ifdef RTL8192U
2170//no use temp in windows driver
2171void
2172PHY_UpdateInitialGain(
2173 struct net_device* dev
2174 )
2175{
2176 struct r8192_priv *priv = ieee80211_priv(dev);
2177 //unsigned char *IGTable;
2178 //u8 DIG_CurrentInitialGain = 4;
2179
2180 switch(priv->rf_chip)
2181 {
2182 case RF_8225:
2183 break;
2184 case RF_8256:
2185 break;
2186 case RF_8258:
2187 break;
2188 case RF_PSEUDO_11N:
2189 break;
2190 case RF_6052:
2191 break;
2192 default:
2193 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
2194 break;
2195 }
2196}
2197#endif
2198
2199//YJ,modified,090107
2200void PHY_GetHWRegOriginalValue(struct net_device* dev)
2201{
2202 struct r8192_priv *priv = ieee80211_priv(dev);
2203
2204 // read tx power offset
2205 // Simulate 8192
2206 priv->MCSTxPowerLevelOriginalOffset[0] =
2207 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
2208 priv->MCSTxPowerLevelOriginalOffset[1] =
2209 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
2210 priv->MCSTxPowerLevelOriginalOffset[2] =
2211 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
2212 priv->MCSTxPowerLevelOriginalOffset[3] =
2213 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
2214 priv->MCSTxPowerLevelOriginalOffset[4] =
2215 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
2216 priv->MCSTxPowerLevelOriginalOffset[5] =
2217 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
2218
2219 // Read CCK offset
2220 priv->MCSTxPowerLevelOriginalOffset[6] =
2221 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
2222 RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
2223 priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
2224 priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
2225 priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
2226
2227 // read rx initial gain
2228 priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
2229 priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
2230 priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
2231 priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
2232 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2233 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2234 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2235
2236 // read framesync
2237 priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
2238 priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
2239 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2240 rOFDM0_RxDetector3, priv->framesync);
2241}
2242//YJ,modified,090107,end
2243
2244
2245
2246/**
2247* Function: phy_InitBBRFRegisterDefinition
2248*
2249* OverView: Initialize Register definition offset for Radio Path A/B/C/D
2250*
2251* Input:
2252* PADAPTER Adapter,
2253*
2254* Output: None
2255* Return: None
2256* Note: The initialization value is constant and it should never be changes
2257*/
2258//use in phy only
2259static void phy_InitBBRFRegisterDefinition( struct net_device* dev)
2260{
2261 struct r8192_priv *priv = ieee80211_priv(dev);
2262
2263 // RF Interface Sowrtware Control
2264 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2265 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2266 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2267 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2268
2269 // RF Interface Readback Value
2270 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2271 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2272 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2273 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2274
2275 // RF Interface Output (and Enable)
2276 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2277 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2278 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2279 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2280
2281 // RF Interface (Output and) Enable
2282 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2283 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2284 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2285 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2286
2287 //Addr of LSSI. Wirte RF register by driver
2288 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2289 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2290 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2291 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2292
2293 // RF parameter
2294 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
2295 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2296 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2297 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2298
2299 // Tx AGC Gain Stage (same for all path. Should we remove this?)
2300 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2301 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2302 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2303 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2304
2305 // Tranceiver A~D HSSI Parameter-1
2306 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
2307 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
2308 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
2309 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
2310
2311 // Tranceiver A~D HSSI Parameter-2
2312 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
2313 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
2314 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
2315 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
2316
2317 // RF switch Control
2318 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2319 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2320 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2321 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2322
2323 // AGC control 1
2324 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2325 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2326 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2327 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2328
2329 // AGC control 2
2330 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2331 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2332 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2333 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2334
2335 // RX AFE control 1
2336 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2337 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2338 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2339 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2340
2341 // RX AFE control 1
2342 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2343 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2344 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2345 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2346
2347 // Tx AFE control 1
2348 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2349 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2350 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2351 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2352
2353 // Tx AFE control 2
2354 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2355 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2356 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2357 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2358
2359 // Tranceiver LSSI Readback SI mode
2360 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2361 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2362 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2363 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2364
2365 // Tranceiver LSSI Readback PI mode
2366 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
2367 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
2368 //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
2369 //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
2370
2371}
2372
2373
2374//
2375// Description: Change RF power state.
2376//
2377// Assumption: This function must be executed in re-schdulable context,
2378// ie. PASSIVE_LEVEL.
2379//
2380// 050823, by rcnjko.
2381//not understand it seem's use in init
2382//SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
2383bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
2384{
2385 struct r8192_priv *priv = ieee80211_priv(dev);
2386 bool bResult = FALSE;
2387
2388 RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2389
2390 if(eRFPowerState == priv->ieee80211->eRFPowerState)
2391 {
2392 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2393 return bResult;
2394 }
2395
2396 bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
2397
2398 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
2399
2400 return bResult;
2401}
2402
2403//use in phy only
2404static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
2405{
2406 struct r8192_priv *priv = ieee80211_priv(dev);
2407 bool bResult = TRUE;
2408 //u8 eRFPath;
2409 //u8 i, QueueID;
2410 u8 u1bTmp;
2411
2412 if(priv->SetRFPowerStateInProgress == TRUE)
2413 return FALSE;
2414
2415 priv->SetRFPowerStateInProgress = TRUE;
2416
2417 switch(priv->rf_chip )
2418 {
2419 default:
2420 switch( eRFPowerState )
2421 {
2422 case eRfOn:
2423 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
2424 write_nic_word(dev, CMDR, 0x37FC);
2425 write_nic_byte(dev, PHY_CCA, 0x3);
2426 write_nic_byte(dev, TXPAUSE, 0x00);
2427 write_nic_byte(dev, SPS1_CTRL, 0x64);
2428 break;
2429
2430 //
2431 // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
2432 // By Bruce, 2008-01-16.
2433 //
2434 case eRfSleep:
2435 case eRfOff:
2436 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
2437 break;
2438#ifdef NOT_YET
2439 // Make sure BusyQueue is empty befor turn off RFE pwoer.
2440 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
2441 {
2442 if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
2443 {
2444 QueueID++;
2445 continue;
2446 }
2447 else
2448 {
2449 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
2450 udelay(10);
2451 i++;
2452 }
2453
2454 if(i >= MAX_DOZE_WAITING_TIMES_9x)
2455 {
2456 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
2457 break;
2458 }
2459 }
2460#endif
2461 //
2462 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
2463 // Added by Bruce, 2008-11-22.
2464 //
2465 //==================================================================
2466 // (0) Disable FW BB reset checking
2467 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
2468
2469 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
2470 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
2471 u1bTmp |= BIT0;
2472 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
2473
2474 write_nic_byte(dev, SPS1_CTRL, 0x0);
2475 write_nic_byte(dev, TXPAUSE, 0xFF);
2476
2477 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
2478 write_nic_word(dev, CMDR, 0x77FC);
2479 write_nic_byte(dev, PHY_CCA, 0x0);
2480 udelay(100);
2481
2482 write_nic_word(dev, CMDR, 0x37FC);
2483 udelay(10);
2484
2485 write_nic_word(dev, CMDR, 0x77FC);
2486 udelay(10);
2487
2488 // (3) Reset BB TRX blocks
2489 write_nic_word(dev, CMDR, 0x57FC);
2490 break;
2491
2492 default:
2493 bResult = FALSE;
2494 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
2495 break;
2496 }
2497 break;
2498
2499 }
2500 priv->ieee80211->eRFPowerState = eRFPowerState;
2501#ifdef TO_DO_LIST
2502 if(bResult)
2503 {
2504 // Update current RF state variable.
2505 priv->ieee80211->eRFPowerState = eRFPowerState;
2506
2507 switch(priv->rf_chip )
2508 {
2509 case RF_8256:
2510 switch(priv->ieee80211->eRFPowerState)
2511 {
2512 case eRfOff:
2513 //
2514 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
2515 //
2516 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
2517 {
2518 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
2519 }
2520 else
2521 {
2522 // Turn off LED if RF is not ON.
2523 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
2524 }
2525 break;
2526
2527 case eRfOn:
2528 // Turn on RF we are still linked, which might happen when
2529 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
2530 if( pMgntInfo->bMediaConnect == TRUE )
2531 {
2532 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
2533 }
2534 else
2535 {
2536 // Turn off LED if RF is not ON.
2537 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
2538 }
2539 break;
2540
2541 default:
2542 // do nothing.
2543 break;
2544 }// Switch RF state
2545
2546 break;
2547
2548 default:
2549 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
2550 break;
2551 }// Switch rf_chip
2552 }
2553#endif
2554 priv->SetRFPowerStateInProgress = FALSE;
2555
2556 return bResult;
2557}
2558
2559/*-----------------------------------------------------------------------------
2560 * Function: GetTxPowerLevel8190()
2561 *
2562 * Overview: This function is export to "common" moudule
2563 *
2564 * Input: PADAPTER Adapter
2565 * psByte Power Level
2566 *
2567 * Output: NONE
2568 *
2569 * Return: NONE
2570 *
2571 *---------------------------------------------------------------------------*/
2572 // no use temp
2573 void
2574PHY_GetTxPowerLevel8192S(
2575 struct net_device* dev,
2576 long* powerlevel
2577 )
2578{
2579 struct r8192_priv *priv = ieee80211_priv(dev);
2580 u8 TxPwrLevel = 0;
2581 long TxPwrDbm;
2582 //
2583 // Because the Tx power indexes are different, we report the maximum of them to
2584 // meet the CCX TPC request. By Bruce, 2008-01-31.
2585 //
2586
2587 // CCK
2588 TxPwrLevel = priv->CurrentCckTxPwrIdx;
2589 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
2590
2591 // Legacy OFDM
2592 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
2593
2594 // Compare with Legacy OFDM Tx power.
2595 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2596 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
2597
2598 // HT OFDM
2599 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
2600
2601 // Compare with HT OFDM Tx power.
2602 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2603 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
2604
2605 *powerlevel = TxPwrDbm;
2606}
2607
2608/*-----------------------------------------------------------------------------
2609 * Function: SetTxPowerLevel8190()
2610 *
2611 * Overview: This function is export to "HalCommon" moudule
2612 *
2613 * Input: PADAPTER Adapter
2614 * u1Byte channel
2615 *
2616 * Output: NONE
2617 *
2618 * Return: NONE
2619 * 2008/11/04 MHC We remove EEPROM_93C56.
2620 * We need to move CCX relative code to independet file.
2621* 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
2622 *---------------------------------------------------------------------------*/
2623 void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel)
2624{
2625 struct r8192_priv *priv = ieee80211_priv(dev);
2626 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(dev);
2627 u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
2628 s8 ant_pwr_diff = 0;
2629 u32 u4RegValue;
2630 u8 index = (channel -1);
2631 // 2009/01/22 MH Add for new EEPROM format from SD3
2632 u8 pwrdiff[2] = {0};
2633 u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};
2634 u8 rfpath = 0, rfpathnum = 2;
2635
2636 if(priv->bTXPowerDataReadFromEEPORM == FALSE)
2637 return;
2638
2639 //
2640 // Read predefined TX power index in EEPROM
2641 //
2642// if(priv->epromtype == EPROM_93c46)
2643 {
2644#ifdef EEPROM_OLD_FORMAT_SUPPORT
2645 powerlevel = priv->TxPowerLevelCCK[index];
2646 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[index];
2647#else
2648 //
2649 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2650 // Power must be calculated by the antenna diff.
2651 // So we have to rewrite Antenna gain offset register here.
2652 // Please refer to BB register 0x80c
2653 // 1. For CCK.
2654 // 2. For OFDM 1T or 2T
2655 //
2656
2657 // 1. CCK
2658 powerlevel = priv->RfTxPwrLevelCck[0][index];
2659
2660 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
2661 {
2662 // Read HT 40 OFDM TX power
2663 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
2664 // RF B HT OFDM pwr-RFA HT OFDM pwr
2665 // Only one RF we need not to decide B <-> A pwr diff
2666
2667 // Legacy<->HT pwr diff, we only care about path A.
2668
2669 // We only assume 1T as RF path A
2670 rfpathnum = 1;
2671 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
2672 }
2673 else if (priv->rf_type == RF_2T2R)
2674 {
2675 // Read HT 40 OFDM TX power
2676 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
2677 // RF B HT OFDM pwr-RFA HT OFDM pwr
2678 ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
2679 priv->RfTxPwrLevelOfdm2T[0][index];
2680 // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
2681 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
2682
2683 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
2684 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
2685 //priv->RfTxPwrLevelOfdm2T[1][index],
2686 //priv->RfTxPwrLevelOfdm2T[0][index],
2687 //priv->RfTxPwrLevelOfdm2T[1][index]));
2688
2689 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
2690 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
2691 }
2692
2693 //
2694 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
2695 // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
2696 //
2697 if (priv->EEPROMVersion == 2) // Defined by SD1 Jong
2698 {
2699 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2700 {
2701 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2702 {
2703 // HT 20<->40 pwr diff
2704 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
2705
2706 // Calculate Antenna pwr diff
2707 if (pwrdiff[rfpath] < 8) // 0~+7
2708 {
2709 #if 0//cosa, it doesn't need to add the offset here
2710 if (rfpath == 0)
2711 powerlevelOFDM24G += pwrdiff[rfpath];
2712 #endif
2713 ht20pwr[rfpath] += pwrdiff[rfpath];
2714 }
2715 else // index8-15=-8~-1
2716 {
2717 #if 0//cosa, it doesn't need to add the offset here
2718 if (rfpath == 0)
2719 powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
2720 #endif
2721 ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
2722 }
2723 }
2724
2725 // RF B HT OFDM pwr-RFA HT OFDM pwr
2726 if (priv->rf_type == RF_2T2R)
2727 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2728
2729 //RTPRINT(FPHY, PHY_TXPWR,
2730 //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2731 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2732 }
2733
2734 // Band Edge scheme is enabled for FCC mode
2735 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
2736 {
2737 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2738 {
2739 pwrdiff[rfpath] = 0;
2740 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2741 {
2742 if (channel <= 3)
2743 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
2744 else if (channel >= 9)
2745 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
2746 else
2747 pwrdiff[rfpath] = 0;
2748
2749 ht40pwr[rfpath] -= pwrdiff[rfpath];
2750 }
2751 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2752 {
2753 if (channel == 1)
2754 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2755 else if (channel >= 11)
2756 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2757 else
2758 pwrdiff[rfpath] = 0;
2759
2760 ht20pwr[rfpath] -= pwrdiff[rfpath];
2761 }
2762 #if 0//cosa, it doesn't need to add the offset here
2763 if (rfpath == 0)
2764 powerlevelOFDM24G -= pwrdiff[rfpath];
2765 #endif
2766 }
2767
2768 if (priv->rf_type == RF_2T2R)
2769 {
2770 // HT 20/40 must decide if they need to minus BD pwr offset
2771 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2772 ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2773 else
2774 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2775 }
2776 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2777 {
2778 if (channel <= 1 || channel >= 11)
2779 {
2780 //RTPRINT(FPHY, PHY_TXPWR,
2781 //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2782 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2783 }
2784 }
2785 else
2786 {
2787 if (channel <= 3 || channel >= 9)
2788 {
2789 //RTPRINT(FPHY, PHY_TXPWR,
2790 //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2791 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2792 }
2793 }
2794 }
2795#if 0//cosa, useless
2796 // Read HT/Legacy OFDM diff
2797 legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
2798#endif
2799 }
2800
2801 //Cosa added for protection, the reg rFPGA0_TxGainStage
2802 // range is from 7~-8, index = 0x0~0xf
2803 if(ant_pwr_diff > 7)
2804 ant_pwr_diff = 7;
2805 if(ant_pwr_diff < -8)
2806 ant_pwr_diff = -8;
2807
2808 //RTPRINT(FPHY, PHY_TXPWR,
2809 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2810 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2811
2812 ant_pwr_diff &= 0xf;
2813
2814 // Antenna TX power difference
2815 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2816 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2817 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B
2818
2819 // Antenna gain offset from B/C/D to A
2820 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2821 priv->AntennaTxPwDiff[1]<<4 |
2822 priv->AntennaTxPwDiff[0] );
2823
2824 // Notify Tx power difference for B/C/D to A!!!
2825 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2826#endif
2827 }
2828
2829 //
2830 // CCX 2 S31, AP control of client transmit power:
2831 // 1. We shall not exceed Cell Power Limit as possible as we can.
2832 // 2. Tolerance is +/- 5dB.
2833 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2834 //
2835 // TODO:
2836 // 1. 802.11h power contraint
2837 //
2838 // 071011, by rcnjko.
2839 //
2840#ifdef TODO //WB, 11h has not implemented now.
2841 if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2842 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2843 {
2844 u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2845 u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2846 u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2847
2848 RT_TRACE(COMP_TXAGC,
2849 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2850 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2851 RT_TRACE(COMP_TXAGC,
2852 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2853 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2854
2855 // CCK
2856 if(powerlevel > CckCellPwrIdx)
2857 powerlevel = CckCellPwrIdx;
2858 // Legacy OFDM, HT OFDM
2859 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2860 {
2861 if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2862 {
2863 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2864 }
2865 else
2866 {
2867 powerlevelOFDM24G = 0;
2868 }
2869 }
2870
2871 RT_TRACE(COMP_TXAGC,
2872 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2873 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2874 }
2875#endif
2876
2877 priv->CurrentCckTxPwrIdx = powerlevel;
2878 priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2879
2880 switch(priv->rf_chip)
2881 {
2882 case RF_8225:
2883 //PHY_SetRF8225CckTxPower(dev, powerlevel);
2884 //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2885 break;
2886
2887 case RF_8256:
2888#if 0
2889 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2890 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2891#endif
2892 break;
2893
2894 case RF_6052:
2895 PHY_RF6052SetCckTxPower(dev, powerlevel);
2896 PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2897 break;
2898
2899 case RF_8258:
2900 break;
2901 default:
2902 break;
2903 }
2904
2905}
2906
2907//
2908// Description:
2909// Update transmit power level of all channel supported.
2910//
2911// TODO:
2912// A mode.
2913// By Bruce, 2008-02-04.
2914// no use temp
2915bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2916{
2917 struct r8192_priv *priv = ieee80211_priv(dev);
2918 u8 idx;
2919 u8 rf_path;
2920
2921 // TODO: A mode Tx power.
2922 u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2923 u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2924
2925 if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2926 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2927 else
2928 OfdmTxPwrIdx = 0;
2929
2930 for(idx = 0; idx < 14; idx++)
2931 {
2932 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2933 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2934 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2935 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2936 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2937 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2938
2939 for (rf_path = 0; rf_path < 2; rf_path++)
2940 {
2941 priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2942 priv->RfTxPwrLevelOfdm1T[rf_path][idx] = \
2943 priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2944 }
2945 }
2946
2947 PHY_SetTxPowerLevel8192S(dev, priv->chan);
2948
2949 return TRUE;
2950}
2951
2952/*
2953 Description:
2954 When beacon interval is changed, the values of the
2955 hw registers should be modified.
2956 By tynli, 2008.10.24.
2957
2958*/
2959
2960extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2961{
2962 u32 NewBeaconNum;
2963
2964 NewBeaconNum = BeaconInterval *32 - 64;
2965 //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2966 //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2967 write_nic_dword(dev, WFM3+4, NewBeaconNum);
2968 write_nic_dword(dev, WFM3, 0xB026007C);
2969}
2970
2971//
2972// Description:
2973// Map dBm into Tx power index according to
2974// current HW model, for example, RF and PA, and
2975// current wireless mode.
2976// By Bruce, 2008-01-29.
2977// use in phy only
2978static u8 phy_DbmToTxPwrIdx(
2979 struct net_device* dev,
2980 WIRELESS_MODE WirelessMode,
2981 long PowerInDbm
2982 )
2983{
2984 //struct r8192_priv *priv = ieee80211_priv(dev);
2985 u8 TxPwrIdx = 0;
2986 long Offset = 0;
2987
2988
2989 //
2990 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2991 // 3dbm, and OFDM HT equals to 0dbm repectively.
2992 // Note:
2993 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2994 // By Bruce, 2008-01-29.
2995 //
2996 switch(WirelessMode)
2997 {
2998 case WIRELESS_MODE_B:
2999 Offset = -7;
3000 break;
3001
3002 case WIRELESS_MODE_G:
3003 case WIRELESS_MODE_N_24G:
3004 Offset = -8;
3005 break;
3006 default:
3007 break;
3008 }
3009
3010 if((PowerInDbm - Offset) > 0)
3011 {
3012 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
3013 }
3014 else
3015 {
3016 TxPwrIdx = 0;
3017 }
3018
3019 // Tx Power Index is too large.
3020 if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
3021 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
3022
3023 return TxPwrIdx;
3024}
3025//
3026// Description:
3027// Map Tx power index into dBm according to
3028// current HW model, for example, RF and PA, and
3029// current wireless mode.
3030// By Bruce, 2008-01-29.
3031// use in phy only
3032static long phy_TxPwrIdxToDbm(
3033 struct net_device* dev,
3034 WIRELESS_MODE WirelessMode,
3035 u8 TxPwrIdx
3036 )
3037{
3038 //struct r8192_priv *priv = ieee80211_priv(dev);
3039 long Offset = 0;
3040 long PwrOutDbm = 0;
3041
3042 //
3043 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
3044 // 3dbm, and OFDM HT equals to 0dbm repectively.
3045 // Note:
3046 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
3047 // By Bruce, 2008-01-29.
3048 //
3049 switch(WirelessMode)
3050 {
3051 case WIRELESS_MODE_B:
3052 Offset = -7;
3053 break;
3054
3055 case WIRELESS_MODE_G:
3056 case WIRELESS_MODE_N_24G:
3057 Offset = -8;
3058 break;
3059 default:
3060 break;
3061 }
3062
3063 PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
3064
3065 return PwrOutDbm;
3066}
3067
3068#ifdef TO_DO_LIST
3069extern VOID
3070PHY_ScanOperationBackup8192S(
3071 IN PADAPTER Adapter,
3072 IN u1Byte Operation
3073 )
3074{
3075
3076 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3077 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
3078 u4Byte BitMask;
3079 u1Byte initial_gain;
3080
3081
3082
3083
3084#if(RTL8192S_DISABLE_FW_DM == 0)
3085
3086 if(!Adapter->bDriverStopped)
3087 {
3088 switch(Operation)
3089 {
3090 case SCAN_OPT_BACKUP:
3091 //
3092 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
3093 // and resume both two DMs while scan complete.
3094 // 2008.11.27.
3095 //
3096 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
3097 break;
3098
3099 case SCAN_OPT_RESTORE:
3100 //
3101 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
3102 // recover earlier DIG settings.
3103 // 2008.11.27.
3104 //
3105 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
3106 break;
3107
3108 default:
3109 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
3110 break;
3111 }
3112 }
3113#endif
3114}
3115#endif
3116
3117//nouse temp
3118void PHY_InitialGain8192S(struct net_device* dev,u8 Operation )
3119{
3120
3121 //struct r8192_priv *priv = ieee80211_priv(dev);
3122 //u32 BitMask;
3123 //u8 initial_gain;
3124
3125#if 0 // For 8192s test disable
3126 if(!dev->bDriverStopped)
3127 {
3128 switch(Operation)
3129 {
3130 case IG_Backup:
3131 RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
3132 initial_gain = priv->DefaultInitialGain[0];
3133 BitMask = bMaskByte0;
3134 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3135 PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3136 pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3137 pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3138 pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3139 pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3140 BitMask = bMaskByte2;
3141 pMgntInfo->InitGain_Backup.CCA = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3142
3143 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3144 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3145 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3146 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3147 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3148
3149 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
3150 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3151 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3152 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3153 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3154 break;
3155 case IG_Restore:
3156 RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
3157 BitMask = 0x7f; //Bit0~ Bit6
3158 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3159 PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3160
3161 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
3162 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
3163 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
3164 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
3165 BitMask = (BIT22|BIT23);
3166 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
3167
3168 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3169 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3170 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3171 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3172 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3173
3174 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3175 PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3176 break;
3177 default:
3178 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
3179 break;
3180 }
3181 }
3182#endif
3183}
3184
3185/*-----------------------------------------------------------------------------
3186 * Function: SetBWModeCallback8190Pci()
3187 *
3188 * Overview: Timer callback function for SetSetBWMode
3189 *
3190 * Input: PRT_TIMER pTimer
3191 *
3192 * Output: NONE
3193 *
3194 * Return: NONE
3195 *
3196 * Note: (1) We do not take j mode into consideration now
3197 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3198 * concurrently?
3199 *---------------------------------------------------------------------------*/
3200// use in phy only (in win it's timer)
3201void PHY_SetBWModeCallback8192S(struct net_device *dev)
3202{
3203 struct r8192_priv *priv = ieee80211_priv(dev);
3204 u8 regBwOpMode;
3205
3206 //return;
3207
3208 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3209 //u32 NowL, NowH;
3210 //u8Byte BeginTime, EndTime;
3211 u8 regRRSR_RSC;
3212
3213 RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
3214 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3215
3216 if(priv->rf_chip == RF_PSEUDO_11N)
3217 {
3218 priv->SetBWModeInProgress= FALSE;
3219 return;
3220 }
3221
3222 if(!priv->up)
3223 return;
3224
3225 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3226 //NowL = read_nic_dword(dev, TSFR);
3227 //NowH = read_nic_dword(dev, TSFR+4);
3228 //BeginTime = ((u8Byte)NowH << 32) + NowL;
3229
3230 //3//
3231 //3//<1>Set MAC register
3232 //3//
3233 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3234 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3235
3236 switch(priv->CurrentChannelBW)
3237 {
3238 case HT_CHANNEL_WIDTH_20:
3239 //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3240 // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3241
3242 regBwOpMode |= BW_OPMODE_20MHZ;
3243 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3244 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3245 break;
3246
3247 case HT_CHANNEL_WIDTH_20_40:
3248 //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3249 // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3250
3251 regBwOpMode &= ~BW_OPMODE_20MHZ;
3252 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3253 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3254 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3255 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3256 break;
3257
3258 default:
3259 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
3260 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3261 break;
3262 }
3263
3264 //3//
3265 //3//<2>Set PHY related register
3266 //3//
3267 switch(priv->CurrentChannelBW)
3268 {
3269 /* 20 MHz channel*/
3270 case HT_CHANNEL_WIDTH_20:
3271 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3272 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3273
3274 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3275 // It is set in Tx descriptor for 8192x series
3276 //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3277 //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3278 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3279 #if 0 //LZM 090219
3280 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
3281 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
3282 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
3283 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3284 #endif
3285
3286 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3287 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3288
3289
3290 break;
3291
3292 /* 40 MHz channel*/
3293 case HT_CHANNEL_WIDTH_20_40:
3294 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3295 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3296
3297 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3298 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3299 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3300 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3301 #if 0 //LZM 090219
3302 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3303 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3304 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3305 #endif
3306
3307 // Set Control channel to upper or lower. These settings are required only for 40MHz
3308 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3309 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3310
3311 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3312 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3313 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3314
3315 break;
3316
3317 default:
3318 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
3319 ,priv->CurrentChannelBW);
3320 break;
3321
3322 }
3323 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3324
3325 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3326 //NowL = read_nic_dword(dev, TSFR);
3327 //NowH = read_nic_dword(dev, TSFR+4);
3328 //EndTime = ((u8Byte)NowH << 32) + NowL;
3329 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3330
3331 //3<3>Set RF related register
3332 switch( priv->rf_chip )
3333 {
3334 case RF_8225:
3335 //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3336 break;
3337
3338 case RF_8256:
3339 // Please implement this function in Hal8190PciPhy8256.c
3340 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3341 break;
3342
3343 case RF_8258:
3344 // Please implement this function in Hal8190PciPhy8258.c
3345 // PHY_SetRF8258Bandwidth();
3346 break;
3347
3348 case RF_PSEUDO_11N:
3349 // Do Nothing
3350 break;
3351
3352 case RF_6052:
3353 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3354 break;
3355 default:
3356 printk("Unknown rf_chip: %d\n", priv->rf_chip);
3357 break;
3358 }
3359
3360 priv->SetBWModeInProgress= FALSE;
3361
3362 RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
3363}
3364
3365
3366 /*-----------------------------------------------------------------------------
3367 * Function: SetBWMode8190Pci()
3368 *
3369 * Overview: This function is export to "HalCommon" moudule
3370 *
3371 * Input: PADAPTER Adapter
3372 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3373 *
3374 * Output: NONE
3375 *
3376 * Return: NONE
3377 *
3378 * Note: We do not take j mode into consideration now
3379 *---------------------------------------------------------------------------*/
3380//extern void PHY_SetBWMode8192S( struct net_device* dev,
3381// HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M
3382// HT_EXTCHNL_OFFSET Offset // Upper, Lower, or Don't care
3383void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3384{
3385 struct r8192_priv *priv = ieee80211_priv(dev);
3386 HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
3387
3388
3389 // Modified it for 20/40 mhz switch by guangan 070531
3390
3391 //return;
3392
3393 //if(priv->SwChnlInProgress)
3394// if(pMgntInfo->bScanInProgress)
3395// {
3396// RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
3397// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3398// return;
3399// }
3400
3401// if(priv->SetBWModeInProgress)
3402// {
3403// // Modified it for 20/40 mhz switch by guangan 070531
3404// RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
3405// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3406// PlatformCancelTimer(dev, &priv->SetBWModeTimer);
3407// //return;
3408// }
3409
3410 if(priv->SetBWModeInProgress)
3411 return;
3412
3413 priv->SetBWModeInProgress= TRUE;
3414
3415 priv->CurrentChannelBW = Bandwidth;
3416
3417 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3418 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3419 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3420 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3421 else
3422 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3423
3424#if 0
3425 if(!priv->bDriverStopped)
3426 {
3427#ifdef USE_WORKITEM
3428 PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
3429#else
3430 PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
3431#endif
3432 }
3433#endif
3434 if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
3435 {
3436#ifdef RTL8192SE
3437 PHY_SetBWModeCallback8192S(dev);
3438#elif defined(RTL8192SU)
3439 SetBWModeCallback8192SUsbWorkItem(dev);
3440#endif
3441 }
3442 else
3443 {
3444 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
3445 priv->SetBWModeInProgress= FALSE;
3446 priv->CurrentChannelBW = tmpBW;
3447 }
3448}
3449
3450// use in phy only (in win it's timer)
3451void PHY_SwChnlCallback8192S(struct net_device *dev)
3452{
3453
3454 struct r8192_priv *priv = ieee80211_priv(dev);
3455 u32 delay;
3456 //bool ret;
3457
3458 RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
3459
3460 if(!priv->up)
3461 return;
3462
3463 if(priv->rf_chip == RF_PSEUDO_11N)
3464 {
3465 priv->SwChnlInProgress=FALSE;
3466 return; //return immediately if it is peudo-phy
3467 }
3468
3469 do{
3470 if(!priv->SwChnlInProgress)
3471 break;
3472
3473 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3474 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3475 {
3476 if(delay>0)
3477 {
3478 mdelay(delay);
3479 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3480 //mod_timer(&priv->SwChnlTimer, jiffies + MSECS(delay));
3481 //==>PHY_SwChnlCallback8192S(dev); for 92se
3482 //==>SwChnlCallback8192SUsb(dev) for 92su
3483 }
3484 else
3485 continue;
3486 }
3487 else
3488 {
3489 priv->SwChnlInProgress=FALSE;
3490 break;
3491 }
3492 }while(true);
3493}
3494
3495// Call after initialization
3496//extern void PHY_SwChnl8192S(struct net_device* dev, u8 channel)
3497u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
3498{
3499 struct r8192_priv *priv = ieee80211_priv(dev);
3500 //u8 tmpchannel =channel;
3501 //bool bResult = false;
3502
3503 if(!priv->up)
3504 return false;
3505
3506 if(priv->SwChnlInProgress)
3507 return false;
3508
3509 if(priv->SetBWModeInProgress)
3510 return false;
3511
3512 //--------------------------------------------
3513 switch(priv->ieee80211->mode)
3514 {
3515 case WIRELESS_MODE_A:
3516 case WIRELESS_MODE_N_5G:
3517 if (channel<=14){
3518 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
3519 return false;
3520 }
3521 break;
3522
3523 case WIRELESS_MODE_B:
3524 if (channel>14){
3525 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
3526 return false;
3527 }
3528 break;
3529
3530 case WIRELESS_MODE_G:
3531 case WIRELESS_MODE_N_24G:
3532 if (channel>14){
3533 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
3534 return false;
3535 }
3536 break;
3537
3538 default:
3539 ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
3540 break;
3541 }
3542 //--------------------------------------------
3543
3544 priv->SwChnlInProgress = TRUE;
3545 if( channel == 0)
3546 channel = 1;
3547
3548 priv->chan=channel;
3549
3550 priv->SwChnlStage=0;
3551 priv->SwChnlStep=0;
3552
3553 if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
3554 {
3555#ifdef RTL8192SE
3556 PHY_SwChnlCallback8192S(dev);
3557#elif defined(RTL8192SU)
3558 SwChnlCallback8192SUsbWorkItem(dev);
3559#endif
3560#ifdef TO_DO_LIST
3561 if(bResult)
3562 {
3563 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
3564 }
3565 else
3566 {
3567 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
3568 priv->SwChnlInProgress = false;
3569 priv->CurrentChannel = tmpchannel;
3570 }
3571#endif
3572 }
3573 else
3574 {
3575 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
3576 priv->SwChnlInProgress = false;
3577 //priv->CurrentChannel = tmpchannel;
3578 }
3579 return true;
3580}
3581
3582
3583//
3584// Description:
3585// Switch channel synchronously. Called by SwChnlByDelayHandler.
3586//
3587// Implemented by Bruce, 2008-02-14.
3588// The following procedure is operted according to SwChanlCallback8190Pci().
3589// However, this procedure is performed synchronously which should be running under
3590// passive level.
3591//
3592//not understant it
3593void PHY_SwChnlPhy8192S( // Only called during initialize
3594 struct net_device* dev,
3595 u8 channel
3596 )
3597{
3598 struct r8192_priv *priv = ieee80211_priv(dev);
3599
3600 RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
3601
3602#ifdef TO_DO_LIST
3603 // Cannot IO.
3604 if(RT_CANNOT_IO(dev))
3605 return;
3606#endif
3607
3608 // Channel Switching is in progress.
3609 if(priv->SwChnlInProgress)
3610 return;
3611
3612 //return immediately if it is peudo-phy
3613 if(priv->rf_chip == RF_PSEUDO_11N)
3614 {
3615 priv->SwChnlInProgress=FALSE;
3616 return;
3617 }
3618
3619 priv->SwChnlInProgress = TRUE;
3620 if( channel == 0)
3621 channel = 1;
3622
3623 priv->chan=channel;
3624
3625 priv->SwChnlStage = 0;
3626 priv->SwChnlStep = 0;
3627
3628 phy_FinishSwChnlNow(dev,channel);
3629
3630 priv->SwChnlInProgress = FALSE;
3631}
3632
3633// use in phy only
3634static bool
3635phy_SetSwChnlCmdArray(
3636 SwChnlCmd* CmdTable,
3637 u32 CmdTableIdx,
3638 u32 CmdTableSz,
3639 SwChnlCmdID CmdID,
3640 u32 Para1,
3641 u32 Para2,
3642 u32 msDelay
3643 )
3644{
3645 SwChnlCmd* pCmd;
3646
3647 if(CmdTable == NULL)
3648 {
3649 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3650 return FALSE;
3651 }
3652 if(CmdTableIdx >= CmdTableSz)
3653 {
3654 //RT_ASSERT(FALSE,
3655 // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
3656 //CmdTableIdx, CmdTableSz));
3657 return FALSE;
3658 }
3659
3660 pCmd = CmdTable + CmdTableIdx;
3661 pCmd->CmdID = CmdID;
3662 pCmd->Para1 = Para1;
3663 pCmd->Para2 = Para2;
3664 pCmd->msDelay = msDelay;
3665
3666 return TRUE;
3667}
3668
3669// use in phy only
3670static bool
3671phy_SwChnlStepByStep(
3672 struct net_device* dev,
3673 u8 channel,
3674 u8 *stage,
3675 u8 *step,
3676 u32 *delay
3677 )
3678{
3679 struct r8192_priv *priv = ieee80211_priv(dev);
3680 //PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
3681 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
3682 u32 PreCommonCmdCnt;
3683 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
3684 u32 PostCommonCmdCnt;
3685 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
3686 u32 RfDependCmdCnt;
3687 SwChnlCmd *CurrentCmd = NULL;
3688 u8 eRFPath;
3689
3690 //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
3691 //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
3692 RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3693 //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3694#ifdef ENABLE_DOT11D
3695 if (!IsLegalChannel(priv->ieee80211, channel))
3696 {
3697 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
3698 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
3699 }
3700#endif
3701
3702 //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3703 //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3704
3705 //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
3706 //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3707 //{
3708 // <1> Fill up pre common command.
3709 PreCommonCmdCnt = 0;
3710 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3711 CmdID_SetTxPowerLevel, 0, 0, 0);
3712 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3713 CmdID_End, 0, 0, 0);
3714
3715 // <2> Fill up post common command.
3716 PostCommonCmdCnt = 0;
3717
3718 phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3719 CmdID_End, 0, 0, 0);
3720
3721 // <3> Fill up RF dependent command.
3722 RfDependCmdCnt = 0;
3723 switch( priv->rf_chip )
3724 {
3725 case RF_8225:
3726 if (channel < 1 || channel > 14)
3727 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3728 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3729 // 2008/09/04 MH Change channel.
3730 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3731 CmdID_RF_WriteReg, rRfChannel, channel, 10);
3732 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3733 CmdID_End, 0, 0, 0);
3734 break;
3735
3736 case RF_8256:
3737 if (channel < 1 || channel > 14)
3738 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3739 // TEST!! This is not the table for 8256!!
3740 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3741 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3742 CmdID_RF_WriteReg, rRfChannel, channel, 10);
3743 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3744 CmdID_End, 0, 0, 0);
3745 break;
3746
3747 case RF_6052:
3748 if (channel < 1 || channel > 14)
3749 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3750 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3751 CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3752 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3753 CmdID_End, 0, 0, 0);
3754 break;
3755
3756 case RF_8258:
3757 break;
3758
3759 default:
3760 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3761 return FALSE;
3762 break;
3763 }
3764
3765
3766 do{
3767 switch(*stage)
3768 {
3769 case 0:
3770 CurrentCmd=&PreCommonCmd[*step];
3771 break;
3772 case 1:
3773 CurrentCmd=&RfDependCmd[*step];
3774 break;
3775 case 2:
3776 CurrentCmd=&PostCommonCmd[*step];
3777 break;
3778 }
3779
3780 if(CurrentCmd->CmdID==CmdID_End)
3781 {
3782 if((*stage)==2)
3783 {
3784 return TRUE;
3785 }
3786 else
3787 {
3788 (*stage)++;
3789 (*step)=0;
3790 continue;
3791 }
3792 }
3793
3794 switch(CurrentCmd->CmdID)
3795 {
3796 case CmdID_SetTxPowerLevel:
3797 //if(priv->card_8192_version > VERSION_8190_BD)
3798 PHY_SetTxPowerLevel8192S(dev,channel);
3799 break;
3800 case CmdID_WritePortUlong:
3801 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
3802 break;
3803 case CmdID_WritePortUshort:
3804 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
3805 break;
3806 case CmdID_WritePortUchar:
3807 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
3808 break;
3809 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3810 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3811 {
3812#if (defined RTL8192SE ||defined RTL8192SU )
3813 // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
3814 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
3815 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
3816#else
3817 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
3818#endif
3819 }
3820 break;
3821 default:
3822 break;
3823 }
3824
3825 break;
3826 }while(TRUE);
3827 //cosa }/*for(Number of RF paths)*/
3828
3829 (*delay)=CurrentCmd->msDelay;
3830 (*step)++;
3831 RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3832 return FALSE;
3833}
3834
3835//called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
3836// use in phy only
3837static void
3838phy_FinishSwChnlNow( // We should not call this function directly
3839 struct net_device* dev,
3840 u8 channel
3841 )
3842{
3843 struct r8192_priv *priv = ieee80211_priv(dev);
3844 u32 delay;
3845
3846 while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
3847 {
3848 if(delay>0)
3849 mdelay(delay);
3850 if(!priv->up)
3851 break;
3852 }
3853}
3854
3855
3856/*-----------------------------------------------------------------------------
3857 * Function: PHYCheckIsLegalRfPath8190Pci()
3858 *
3859 * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
3860 * We will return false.
3861 *
3862 * Input: NONE
3863 *
3864 * Output: NONE
3865 *
3866 * Return: NONE
3867 *
3868 * Revised History:
3869 * When Who Remark
3870 * 11/15/2007 MHC Create Version 0.
3871 *
3872 *---------------------------------------------------------------------------*/
3873 //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3874//extern bool
3875//PHY_CheckIsLegalRfPath8192S(
3876// struct net_device* dev,
3877// u32 eRFPath)
3878u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3879{
3880// struct r8192_priv *priv = ieee80211_priv(dev);
3881 bool rtValue = TRUE;
3882
3883 // NOt check RF Path now.!
3884#if 0
3885 if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3886 {
3887 rtValue = FALSE;
3888 }
3889 if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3890 {
3891
3892 }
3893#endif
3894 return rtValue;
3895
3896} /* PHY_CheckIsLegalRfPath8192S */
3897
3898
3899
3900/*-----------------------------------------------------------------------------
3901 * Function: PHY_IQCalibrate8192S()
3902 *
3903 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
3904 * to improve RF EVM!!?
3905 *
3906 * Input: IN PADAPTER pAdapter
3907 *
3908 * Output: NONE
3909 *
3910 * Return: NONE
3911 *
3912 * Revised History:
3913 * When Who Remark
3914 * 10/07/2008 MHC Create. Document from SD3 RFSI Jenyu.
3915 *
3916 *---------------------------------------------------------------------------*/
3917 //called by InitializeAdapter8192SE
3918void
3919PHY_IQCalibrate( struct net_device* dev)
3920{
3921 //struct r8192_priv *priv = ieee80211_priv(dev);
3922 u32 i, reg;
3923 u32 old_value;
3924 long X, Y, TX0[4];
3925 u32 TXA[4];
3926
3927 // 1. Check QFN68 or 64 92S (Read from EEPROM)
3928
3929 //
3930 // 2. QFN 68
3931 //
3932 // For 1T2R IQK only now !!!
3933 for (i = 0; i < 10; i++)
3934 {
3935 // IQK
3936 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3937 //PlatformStallExecution(5);
3938 udelay(5);
3939 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3940 udelay(5);
3941 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3942 udelay(5);
3943 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3944 udelay(5);
3945 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3946 udelay(5);
3947 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3948 udelay(5);
3949 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3950 udelay(5);
3951 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3952 udelay(5);
3953 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3954 udelay(5);
3955 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3956 udelay(5);
3957 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3958 udelay(2000);
3959 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3960 udelay(5);
3961 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3962 udelay(5);
3963 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3964
3965
3966 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3967
3968 // Readback IQK value and rewrite
3969 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3970 {
3971 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3972
3973 // Calibrate init gain for A path for TX0
3974 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3975 TXA[RF90_PATH_A] = (X * old_value)/0x100;
3976 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3977 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3978 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3979 udelay(5);
3980
3981 // Calibrate init gain for C path for TX0
3982 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3983 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3984 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3985 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3986 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3987 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3988 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3989 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3990 udelay(5);
3991
3992 // Calibrate RX A and B for RX0
3993 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3994 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3995 reg = (reg & 0xFFFFFC00) |X;
3996 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3997 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3998 reg = (reg & 0xFFFF03FF) |Y<<10;
3999 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4000 udelay(5);
4001 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4002
4003 // Calibrate init gain for A path for TX1 !!!!!!
4004 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4005 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4006 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4007 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4008 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4009 udelay(5);
4010
4011 // Calibrate init gain for C path for TX1
4012 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4013 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4014 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4015 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4016 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4017 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4018 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4019 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4020 udelay(5);
4021
4022 // Calibrate RX A and B for RX1
4023 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4024 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4025 reg = (reg & 0xFFFFFC00) |X;
4026 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4027
4028 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4029 reg = (reg & 0xFFFF03FF) |Y<<10;
4030 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4031 udelay(5);
4032
4033 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4034 break;
4035 }
4036
4037 }
4038
4039
4040 //
4041 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4042 //
4043
4044
4045}
4046
4047/*-----------------------------------------------------------------------------
4048 * Function: PHY_IQCalibrateBcut()
4049 *
4050 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
4051 * to improve RF EVM!!?
4052 *
4053 * Input: IN PADAPTER pAdapter
4054 *
4055 * Output: NONE
4056 *
4057 * Return: NONE
4058 *
4059 * Revised History:
4060 * When Who Remark
4061 * 11/18/2008 MHC Create. Document from SD3 RFSI Jenyu.
4062 * 92S B-cut QFN 68 pin IQ calibration procedure.doc
4063 *
4064 *---------------------------------------------------------------------------*/
4065extern void PHY_IQCalibrateBcut(struct net_device* dev)
4066{
4067 //struct r8192_priv *priv = ieee80211_priv(dev);
4068 //PMGNT_INFO pMgntInfo = &pAdapter->MgntInfo;
4069 u32 i, reg;
4070 u32 old_value;
4071 long X, Y, TX0[4];
4072 u32 TXA[4];
4073 u32 calibrate_set[13] = {0};
4074 u32 load_value[13];
4075 u8 RfPiEnable=0;
4076
4077 // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
4078
4079 //
4080 // 1. Save e70~ee0 register setting, and load calibration setting
4081 //
4082 /*
4083 0xee0[31:0]=0x3fed92fb;
4084 0xedc[31:0] =0x3fed92fb;
4085 0xe70[31:0] =0x3fed92fb;
4086 0xe74[31:0] =0x3fed92fb;
4087 0xe78[31:0] =0x3fed92fb;
4088 0xe7c[31:0]= 0x3fed92fb;
4089 0xe80[31:0]= 0x3fed92fb;
4090 0xe84[31:0]= 0x3fed92fb;
4091 0xe88[31:0]= 0x3fed92fb;
4092 0xe8c[31:0]= 0x3fed92fb;
4093 0xed0[31:0]= 0x3fed92fb;
4094 0xed4[31:0]= 0x3fed92fb;
4095 0xed8[31:0]= 0x3fed92fb;
4096 */
4097 calibrate_set [0] = 0xee0;
4098 calibrate_set [1] = 0xedc;
4099 calibrate_set [2] = 0xe70;
4100 calibrate_set [3] = 0xe74;
4101 calibrate_set [4] = 0xe78;
4102 calibrate_set [5] = 0xe7c;
4103 calibrate_set [6] = 0xe80;
4104 calibrate_set [7] = 0xe84;
4105 calibrate_set [8] = 0xe88;
4106 calibrate_set [9] = 0xe8c;
4107 calibrate_set [10] = 0xed0;
4108 calibrate_set [11] = 0xed4;
4109 calibrate_set [12] = 0xed8;
4110 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
4111 for (i = 0; i < 13; i++)
4112 {
4113 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
4114 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
4115
4116 }
4117
4118 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
4119
4120 //
4121 // 2. QFN 68
4122 //
4123 // For 1T2R IQK only now !!!
4124 for (i = 0; i < 10; i++)
4125 {
4126 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
4127 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
4128 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
4129 {
4130 //DbgPrint("IQK Switch to PI mode\n");
4131 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
4132 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
4133 }
4134
4135 // IQK
4136 // 2. IQ calibration & LO leakage calibration
4137 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
4138 udelay(5);
4139 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
4140 udelay(5);
4141 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
4142 udelay(5);
4143 //path-A IQ K and LO K gain setting
4144 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
4145 udelay(5);
4146 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
4147 udelay(5);
4148 //set LO calibration
4149 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
4150 udelay(5);
4151 //path-B IQ K and LO K gain setting
4152 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
4153 udelay(5);
4154 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
4155 udelay(5);
4156 //K idac_I & IQ
4157 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4158 udelay(5);
4159 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4160 udelay(5);
4161
4162 // delay 2ms
4163 udelay(2000);
4164
4165 //idac_Q setting
4166 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
4167 udelay(5);
4168 //K idac_Q & IQ
4169 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4170 udelay(5);
4171 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4172
4173 // delay 2ms
4174 udelay(2000);
4175
4176 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
4177 udelay(5);
4178 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
4179 udelay(5);
4180 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
4181
4182 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
4183 {
4184 //DbgPrint("IQK Switch back to SI mode\n");
4185 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
4186 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
4187 }
4188
4189
4190 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
4191
4192 // 3. check fail bit, and fill BB IQ matrix
4193 // Readback IQK value and rewrite
4194 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
4195 {
4196 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
4197
4198 // Calibrate init gain for A path for TX0
4199 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
4200 TXA[RF90_PATH_A] = (X * old_value)/0x100;
4201 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4202 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
4203 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4204 udelay(5);
4205
4206 // Calibrate init gain for C path for TX0
4207 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
4208 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4209 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4210 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
4211 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4212 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
4213 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4214 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
4215 udelay(5);
4216
4217 // Calibrate RX A and B for RX0
4218 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
4219 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
4220 reg = (reg & 0xFFFFFC00) |X;
4221 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4222 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
4223 reg = (reg & 0xFFFF03FF) |Y<<10;
4224 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4225 udelay(5);
4226 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4227
4228 // Calibrate init gain for A path for TX1 !!!!!!
4229 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4230 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4231 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4232 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4233 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4234 udelay(5);
4235
4236 // Calibrate init gain for C path for TX1
4237 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4238 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4239 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4240 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4241 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4242 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4243 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4244 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4245 udelay(5);
4246
4247 // Calibrate RX A and B for RX1
4248 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4249 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4250 reg = (reg & 0xFFFFFC00) |X;
4251 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4252
4253 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4254 reg = (reg & 0xFFFF03FF) |Y<<10;
4255 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4256 udelay(5);
4257
4258 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4259 break;
4260 }
4261
4262 }
4263
4264 //
4265 // 4. Reload e70~ee0 register setting.
4266 //
4267 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
4268 for (i = 0; i < 13; i++)
4269 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
4270
4271
4272 //
4273 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4274 //
4275
4276
4277
4278} // PHY_IQCalibrateBcut
4279
4280
4281//
4282// Move from phycfg.c to gen.c to be code independent later
4283//
4284//-------------------------Move to other DIR later----------------------------*/
4285//#if (DEV_BUS_TYPE == USB_INTERFACE)
4286#ifdef RTL8192SU
4287
4288// use in phy only (in win it's timer)
4289void SwChnlCallback8192SUsb(struct net_device *dev)
4290{
4291
4292 struct r8192_priv *priv = ieee80211_priv(dev);
4293 u32 delay;
4294// bool ret;
4295
4296 RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
4297 %d\n", priv->chan);
4298
4299
4300 if(!priv->up)
4301 return;
4302
4303 if(priv->rf_chip == RF_PSEUDO_11N)
4304 {
4305 priv->SwChnlInProgress=FALSE;
4306 return; //return immediately if it is peudo-phy
4307 }
4308
4309 do{
4310 if(!priv->SwChnlInProgress)
4311 break;
4312
4313 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
4314 {
4315 if(delay>0)
4316 {
4317 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
4318
4319 }
4320 else
4321 continue;
4322 }
4323 else
4324 {
4325 priv->SwChnlInProgress=FALSE;
4326 }
4327 break;
4328 }while(TRUE);
4329}
4330
4331
4332//
4333// Callback routine of the work item for switch channel.
4334//
4335// use in phy only (in win it's work)
4336void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
4337{
4338 struct r8192_priv *priv = ieee80211_priv(dev);
4339
4340 RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
4341#ifdef TO_DO_LIST
4342 if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
4343 {
4344 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
4345
4346 pHalData->SwChnlInProgress = FALSE;
4347 return;
4348 }
4349#endif
4350 phy_FinishSwChnlNow(dev, priv->chan);
4351 priv->SwChnlInProgress = FALSE;
4352
4353 RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
4354}
4355
4356
4357/*-----------------------------------------------------------------------------
4358 * Function: SetBWModeCallback8192SUsb()
4359 *
4360 * Overview: Timer callback function for SetSetBWMode
4361 *
4362 * Input: PRT_TIMER pTimer
4363 *
4364 * Output: NONE
4365 *
4366 * Return: NONE
4367 *
4368 * Note: (1) We do not take j mode into consideration now
4369 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
4370 * concurrently?
4371 *---------------------------------------------------------------------------*/
4372//====>//rtl8192_SetBWMode
4373// use in phy only (in win it's timer)
4374void SetBWModeCallback8192SUsb(struct net_device *dev)
4375{
4376 struct r8192_priv *priv = ieee80211_priv(dev);
4377 u8 regBwOpMode;
4378
4379 // Added it for 20/40 mhz switch time evaluation by guangan 070531
4380 //u32 NowL, NowH;
4381 //u8Byte BeginTime, EndTime;
4382 u8 regRRSR_RSC;
4383
4384 RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
4385 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4386
4387 if(priv->rf_chip == RF_PSEUDO_11N)
4388 {
4389 priv->SetBWModeInProgress= FALSE;
4390 return;
4391 }
4392
4393 if(!priv->up)
4394 return;
4395
4396 // Added it for 20/40 mhz switch time evaluation by guangan 070531
4397 //NowL = read_nic_dword(dev, TSFR);
4398 //NowH = read_nic_dword(dev, TSFR+4);
4399 //BeginTime = ((u8Byte)NowH << 32) + NowL;
4400
4401 //3<1>Set MAC register
4402 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4403 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4404
4405 switch(priv->CurrentChannelBW)
4406 {
4407 case HT_CHANNEL_WIDTH_20:
4408 regBwOpMode |= BW_OPMODE_20MHZ;
4409 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4410 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4411 break;
4412
4413 case HT_CHANNEL_WIDTH_20_40:
4414 regBwOpMode &= ~BW_OPMODE_20MHZ;
4415 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4416 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4417
4418 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4419 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4420 break;
4421
4422 default:
4423 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
4424 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4425 break;
4426 }
4427
4428 //3 <2>Set PHY related register
4429 switch(priv->CurrentChannelBW)
4430 {
4431 case HT_CHANNEL_WIDTH_20:
4432 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4433 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4434 #if 0 //LZM090219
4435 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4436
4437 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4438 //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
4439 //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
4440 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
4441 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4442 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4443 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4444 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4445 #endif
4446
4447 if (priv->card_8192_version >= VERSION_8192S_BCUT)
4448 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4449
4450 break;
4451 case HT_CHANNEL_WIDTH_20_40:
4452 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4453 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4454 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4455 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4456
4457 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4458 //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4459 //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4460 //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4461 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4462
4463 if (priv->card_8192_version >= VERSION_8192S_BCUT)
4464 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4465
4466 break;
4467 default:
4468 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
4469 ,priv->CurrentChannelBW);
4470 break;
4471
4472 }
4473 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4474
4475 // Added it for 20/40 mhz switch time evaluation by guangan 070531
4476 //NowL = read_nic_dword(dev, TSFR);
4477 //NowH = read_nic_dword(dev, TSFR+4);
4478 //EndTime = ((u8Byte)NowH << 32) + NowL;
4479 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
4480
4481#if 1
4482 //3<3>Set RF related register
4483 switch( priv->rf_chip )
4484 {
4485 case RF_8225:
4486 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4487 break;
4488
4489 case RF_8256:
4490 // Please implement this function in Hal8190PciPhy8256.c
4491 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4492 break;
4493
4494 case RF_6052:
4495 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4496 break;
4497
4498 case RF_8258:
4499 // Please implement this function in Hal8190PciPhy8258.c
4500 // PHY_SetRF8258Bandwidth();
4501 break;
4502
4503 case RF_PSEUDO_11N:
4504 // Do Nothing
4505 break;
4506
4507 default:
4508 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4509 break;
4510 }
4511#endif
4512 priv->SetBWModeInProgress= FALSE;
4513
4514 RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
4515}
4516
4517//
4518// Callback routine of the work item for set bandwidth mode.
4519//
4520// use in phy only (in win it's work)
4521void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
4522{
4523 struct r8192_priv *priv = ieee80211_priv(dev);
4524 u8 regBwOpMode;
4525
4526 // Added it for 20/40 mhz switch time evaluation by guangan 070531
4527 //u32 NowL, NowH;
4528 //u8Byte BeginTime, EndTime;
4529 u8 regRRSR_RSC;
4530
4531 RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem() Switch to %s bandwidth\n", \
4532 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4533
4534 if(priv->rf_chip == RF_PSEUDO_11N)
4535 {
4536 priv->SetBWModeInProgress= FALSE;
4537 return;
4538 }
4539
4540 if(!priv->up)
4541 return;
4542
4543 // Added it for 20/40 mhz switch time evaluation by guangan 070531
4544 //NowL = read_nic_dword(dev, TSFR);
4545 //NowH = read_nic_dword(dev, TSFR+4);
4546 //BeginTime = ((u8Byte)NowH << 32) + NowL;
4547
4548 //3<1>Set MAC register
4549 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4550 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4551
4552 switch(priv->CurrentChannelBW)
4553 {
4554 case HT_CHANNEL_WIDTH_20:
4555 regBwOpMode |= BW_OPMODE_20MHZ;
4556 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4557 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4558 break;
4559
4560 case HT_CHANNEL_WIDTH_20_40:
4561 regBwOpMode &= ~BW_OPMODE_20MHZ;
4562 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4563 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4564 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4565 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4566
4567 break;
4568
4569 default:
4570 RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
4571 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4572 break;
4573 }
4574
4575 //3 <2>Set PHY related register
4576 switch(priv->CurrentChannelBW)
4577 {
4578 case HT_CHANNEL_WIDTH_20:
4579 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4580 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4581
4582 #if 0 //LZM 090219
4583 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
4584
4585 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4586 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4587 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4588 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4589 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
4590 #endif
4591
4592 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4593
4594 break;
4595 case HT_CHANNEL_WIDTH_20_40:
4596 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4597 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4598 #if 0 //LZM 090219
4599 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4600
4601 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4602
4603 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4604 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4605 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4606 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4607 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4608 #endif
4609
4610 // Set Control channel to upper or lower. These settings are required only for 40MHz
4611 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4612 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4613
4614 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4615
4616 break;
4617
4618
4619 default:
4620 RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
4621 ,priv->CurrentChannelBW);
4622 break;
4623
4624 }
4625 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4626
4627 //3<3>Set RF related register
4628 switch( priv->rf_chip )
4629 {
4630 case RF_8225:
4631 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4632 break;
4633
4634 case RF_8256:
4635 // Please implement this function in Hal8190PciPhy8256.c
4636 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4637 break;
4638
4639 case RF_6052:
4640 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4641 break;
4642
4643 case RF_8258:
4644 // Please implement this function in Hal8190PciPhy8258.c
4645 // PHY_SetRF8258Bandwidth();
4646 break;
4647
4648 case RF_PSEUDO_11N:
4649 // Do Nothing
4650 break;
4651
4652 default:
4653 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4654 break;
4655 }
4656
4657 priv->SetBWModeInProgress= FALSE;
4658
4659 RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
4660}
4661
4662//--------------------------Move to oter DIR later-------------------------------*/
4663#ifdef RTL8192SU
4664void InitialGain8192S(struct net_device *dev, u8 Operation)
4665{
4666#ifdef TO_DO_LIST
4667 struct r8192_priv *priv = ieee80211_priv(dev);
4668#endif
4669
4670}
4671#endif
4672
4673void InitialGain819xUsb(struct net_device *dev, u8 Operation)
4674{
4675 struct r8192_priv *priv = ieee80211_priv(dev);
4676
4677 priv->InitialGainOperateType = Operation;
4678
4679 if(priv->up)
4680 {
4681 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4682 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
4683 #else
4684 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
4685 schedule_task(&priv->initialgain_operate_wq);
4686 #else
4687 queue_work(priv->priv_wq,&priv->initialgain_operate_wq);
4688 #endif
4689 #endif
4690 }
4691}
4692
4693#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
4694extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
4695{
4696 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4697 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
4698 struct net_device *dev = priv->ieee80211->dev;
4699#else
4700extern void InitialGainOperateWorkItemCallBack(struct net_device *dev)
4701{
4702 struct r8192_priv *priv = ieee80211_priv(dev);
4703#endif
4704#define SCAN_RX_INITIAL_GAIN 0x17
4705#define POWER_DETECTION_TH 0x08
4706 u32 BitMask;
4707 u8 initial_gain;
4708 u8 Operation;
4709
4710 Operation = priv->InitialGainOperateType;
4711
4712 switch(Operation)
4713 {
4714 case IG_Backup:
4715 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
4716 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
4717 BitMask = bMaskByte0;
4718 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4719 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
4720 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
4721 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
4722 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
4723 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
4724 BitMask = bMaskByte2;
4725 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
4726
4727 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4728 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4729 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4730 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4731 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
4732
4733 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
4734 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
4735 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
4736 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
4737 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
4738 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
4739 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
4740 break;
4741 case IG_Restore:
4742 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
4743 BitMask = 0x7f; //Bit0~ Bit6
4744 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4745 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
4746
4747 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
4748 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
4749 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
4750 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
4751 BitMask = bMaskByte2;
4752 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
4753
4754 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4755 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4756 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4757 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4758 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
4759
4760 PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
4761
4762 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4763 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
4764 break;
4765 default:
4766 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
4767 break;
4768 }
4769}
4770
4771#endif // #if (DEV_BUS_TYPE == USB_INTERFACE)
4772
4773//-----------------------------------------------------------------------------
4774// Description:
4775// Schedule workitem to send specific CMD IO to FW.
4776// Added by Roger, 2008.12.03.
4777//
4778//-----------------------------------------------------------------------------
4779bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)
4780{
4781 struct r8192_priv *priv = ieee80211_priv(dev);
4782 u16 FwCmdWaitCounter = 0;
4783
4784 u16 FwCmdWaitLimit = 1000;
4785
4786 //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
4787 if(priv->bInHctTest)
4788 return true;
4789
4790 RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
4791
4792 // Will be done by high power respectively.
4793 if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
4794 {
4795 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
4796 return false;
4797 }
4798
4799#if 1
4800 while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
4801 {
4802 //if(RT_USB_CANNOT_IO(Adapter))
4803 //{
4804 // RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
4805 // return FALSE;
4806 //}
4807
4808 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
4809 return false;
4810 FwCmdWaitCounter ++;
4811 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
4812 udelay(100);
4813 }
4814
4815 if(FwCmdWaitCounter == FwCmdWaitLimit)
4816 {
4817 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
4818 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
4819 //return false;
4820 }
4821#endif
4822 if (priv->SetFwCmdInProgress)
4823 {
4824 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
4825 return false;
4826 }
4827 priv->SetFwCmdInProgress = TRUE;
4828 priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
4829
4830 phy_SetFwCmdIOCallback(dev);
4831 return true;
4832}
4833void ChkFwCmdIoDone(struct net_device* dev)
4834{
4835 u16 PollingCnt = 1000;
4836 u32 tmpValue;
4837
4838 do
4839 {// Make sure that CMD IO has be accepted by FW.
4840#ifdef TO_DO_LIST
4841 if(RT_USB_CANNOT_IO(Adapter))
4842 {
4843 RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
4844 return;
4845 }
4846#endif
4847 udelay(10); // sleep 20us
4848 tmpValue = read_nic_dword(dev, WFM5);
4849 if(tmpValue == 0)
4850 {
4851 RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
4852 break;
4853 }
4854 else
4855 {
4856 RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
4857 }
4858 }while( --PollingCnt );
4859
4860 if(PollingCnt == 0)
4861 {
4862 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
4863 }
4864}
4865// Callback routine of the timer callback for FW Cmd IO.
4866//
4867// Description:
4868// This routine will send specific CMD IO to FW and check whether it is done.
4869//
4870void phy_SetFwCmdIOCallback(struct net_device* dev)
4871{
4872 //struct net_device* dev = (struct net_device*) data;
4873 u32 input;
4874 static u32 ScanRegister;
4875 struct r8192_priv *priv = ieee80211_priv(dev);
4876 if(!priv->up)
4877 {
4878 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
4879 return;
4880 }
4881
4882 RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
4883
4884 switch(priv->CurrentFwCmdIO)
4885 {
4886 case FW_CMD_HIGH_PWR_ENABLE:
4887 if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4888 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
4889 break;
4890
4891 case FW_CMD_HIGH_PWR_DISABLE:
4892 write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
4893 break;
4894
4895 case FW_CMD_DIG_RESUME:
4896 write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4897 break;
4898
4899 case FW_CMD_DIG_HALT:
4900 write_nic_dword(dev, WFM5, FW_DIG_HALT);
4901 break;
4902
4903 //
4904 // <Roger_Notes> The following FW CMD IO was combined into single operation
4905 // (i.e., to prevent number of system workitem out of resource!!).
4906 // 2008.12.04.
4907 //
4908 case FW_CMD_RESUME_DM_BY_SCAN:
4909 RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
4910 if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4911 {
4912 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
4913 ChkFwCmdIoDone(dev);
4914 }
4915 write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4916 break;
4917
4918 case FW_CMD_PAUSE_DM_BY_SCAN:
4919 RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
4920 write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4921 ChkFwCmdIoDone(dev);
4922 write_nic_dword(dev, WFM5, FW_DIG_HALT);
4923 break;
4924
4925 //
4926 // <Roger_Notes> The following FW CMD IO should be checked
4927 // (i.e., workitem schedule timing issue!!).
4928 // 2008.12.04.
4929 //
4930 case FW_CMD_DIG_DISABLE:
4931 RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4932 write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4933 break;
4934
4935 case FW_CMD_DIG_ENABLE:
4936 RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4937 write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4938 break;
4939
4940 case FW_CMD_RA_RESET:
4941 write_nic_dword(dev, WFM5, FW_RA_RESET);
4942 break;
4943
4944 case FW_CMD_RA_ACTIVE:
4945 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4946 break;
4947
4948 case FW_CMD_RA_REFRESH_N:
4949 RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4950 if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4951 input = FW_RA_REFRESH;
4952 else
4953 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4954 write_nic_dword(dev, WFM5, input);
4955 break;
4956 case FW_CMD_RA_REFRESH_BG:
4957 RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4958 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4959 ChkFwCmdIoDone(dev);
4960 write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4961 break;
4962
4963 case FW_CMD_IQK_ENABLE:
4964 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4965 break;
4966
4967 case FW_CMD_TXPWR_TRACK_ENABLE:
4968 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4969 break;
4970
4971 case FW_CMD_TXPWR_TRACK_DISABLE:
4972 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4973 break;
4974
4975 default:
4976 RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4977 break;
4978 }
4979
4980 ChkFwCmdIoDone(dev);
4981
4982 switch(priv->CurrentFwCmdIO)
4983 {
4984 case FW_CMD_HIGH_PWR_DISABLE:
4985 //if(pMgntInfo->bTurboScan)
4986 {
4987 //Lower initial gain
4988 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4989 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4990 // CCA threshold
4991 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4992 // Disable OFDM Part
4993 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4994 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4995 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4996 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4997 }
4998 break;
4999
5000 case FW_CMD_HIGH_PWR_ENABLE:
5001 //if(pMgntInfo->bTurboScan)
5002 {
5003 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
5004 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
5005
5006 // CCA threshold
5007 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
5008 // Enable OFDM Part
5009 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
5010
5011 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
5012 if(ScanRegister != 0){
5013 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
5014 }
5015
5016 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
5017 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
5018 else
5019 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
5020 }
5021 break;
5022 }
5023
5024 priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
5025 RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
5026
5027}
5028
diff --git a/drivers/staging/rtl8192su/r8192S_phy.h b/drivers/staging/rtl8192su/r8192S_phy.h
new file mode 100644
index 00000000000..580a7c6a760
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_phy.h
@@ -0,0 +1,138 @@
1/*****************************************************************************
2 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.
3 *
4 * Module: __INC_HAL8192SPHYCFG_H
5 *
6 *
7 * Note:
8 *
9 *
10 * Export: Constants, macro, functions(API), global variables(None).
11 *
12 * Abbrev:
13 *
14 * History:
15 * Data Who Remark
16 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
17 * 2. Reorganize code architecture.
18 *
19 *****************************************************************************/
20 /* Check to see if the file has been included already. */
21#ifndef _R8192S_PHY_H
22#define _R8192S_PHY_H
23
24
25/*--------------------------Define Parameters-------------------------------*/
26#define LOOP_LIMIT 5
27#define MAX_STALL_TIME 50 //us
28#define AntennaDiversityValue 0x80 //(dev->bSoftwareAntennaDiversity ? 0x00:0x80)
29#define MAX_TXPWR_IDX_NMODE_92S 63
30
31//#define delay_ms(_t) PlatformStallExecution(1000*(_t))
32//#define delay_us(_t) PlatformStallExecution(_t)
33
34/* Channel switch:The size of command tables for switch channel*/
35#define MAX_PRECMD_CNT 16
36#define MAX_RFDEPENDCMD_CNT 16
37#define MAX_POSTCMD_CNT 16
38
39
40/*------------------------------Define structure----------------------------*/
41typedef enum _SwChnlCmdID{
42 CmdID_End,
43 CmdID_SetTxPowerLevel,
44 CmdID_BBRegWrite10,
45 CmdID_WritePortUlong,
46 CmdID_WritePortUshort,
47 CmdID_WritePortUchar,
48 CmdID_RF_WriteReg,
49}SwChnlCmdID;
50
51
52/* 1. Switch channel related */
53typedef struct _SwChnlCmd{
54 SwChnlCmdID CmdID;
55 u32 Para1;
56 u32 Para2;
57 u32 msDelay;
58}__attribute__ ((packed)) SwChnlCmd;
59
60extern u32 rtl819XMACPHY_Array_PG[];
61extern u32 rtl819XPHY_REG_1T2RArray[];
62extern u32 rtl819XAGCTAB_Array[];
63extern u32 rtl819XRadioA_Array[];
64extern u32 rtl819XRadioB_Array[];
65extern u32 rtl819XRadioC_Array[];
66extern u32 rtl819XRadioD_Array[];
67
68typedef enum _HW90_BLOCK{
69 HW90_BLOCK_MAC = 0,
70 HW90_BLOCK_PHY0 = 1,
71 HW90_BLOCK_PHY1 = 2,
72 HW90_BLOCK_RF = 3,
73 HW90_BLOCK_MAXIMUM = 4, // Never use this
74}HW90_BLOCK_E, *PHW90_BLOCK_E;
75
76typedef enum _RF90_RADIO_PATH{
77 RF90_PATH_A = 0, //Radio Path A
78 RF90_PATH_B = 1, //Radio Path B
79 RF90_PATH_C = 2, //Radio Path C
80 RF90_PATH_D = 3, //Radio Path D
81 RF90_PATH_MAX = 4, //Max RF number 90 support
82}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
83
84#define bMaskByte0 0xff
85#define bMaskByte1 0xff00
86#define bMaskByte2 0xff0000
87#define bMaskByte3 0xff000000
88#define bMaskHWord 0xffff0000
89#define bMaskLWord 0x0000ffff
90#define bMaskDWord 0xffffffff
91
92typedef enum _VERSION_8190{
93 // RTL8190
94 VERSION_8190_BD=0x3,
95 VERSION_8190_BE
96}VERSION_8190,*PVERSION_8190;
97
98//
99// BB and RF register read/write
100//
101
102extern u32 rtl8192_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask);
103extern void rtl8192_setBBreg(struct net_device* dev,u32 RegAddr, u32 BitMask,u32 Data);
104extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
105extern void rtl8192_phy_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr,u32 BitMask,u32 Data);
106
107bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
108
109
110/* MAC/BB/RF HAL config */
111extern bool PHY_MACConfig8192S(struct net_device* dev);
112extern bool PHY_BBConfig8192S(struct net_device* dev);
113extern bool PHY_RFConfig8192S(struct net_device* dev);
114
115extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath);
116extern void rtl8192_SetBWMode(struct net_device* dev,HT_CHANNEL_WIDTH ChnlWidth,HT_EXTCHNL_OFFSET Offset );
117extern u8 rtl8192_phy_SwChnl(struct net_device* dev,u8 channel);
118extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev,u32 eRFPath );
119extern void rtl8192_BBConfig(struct net_device* dev);
120extern void PHY_IQCalibrateBcut(struct net_device* dev);
121extern void PHY_IQCalibrate(struct net_device* dev);
122extern void PHY_GetHWRegOriginalValue(struct net_device* dev);
123
124#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
125extern void InitialGainOperateWorkItemCallBack(struct work_struct *work);
126#else
127extern void InitialGainOperateWorkItemCallBack(struct net_device *dev);
128#endif
129void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel);
130void PHY_InitialGain8192S(struct net_device* dev,u8 Operation );
131
132/*--------------------------Exported Function prototype---------------------*/
133bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO);
134extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval);
135void ChkFwCmdIoDone(struct net_device* dev);
136
137#endif // __INC_HAL8192SPHYCFG_H
138
diff --git a/drivers/staging/rtl8192su/r8192S_phyreg.h b/drivers/staging/rtl8192su/r8192S_phyreg.h
new file mode 100644
index 00000000000..96c7cfa9254
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_phyreg.h
@@ -0,0 +1,1033 @@
1/*****************************************************************************
2 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.
3 *
4 * Module: __INC_HAL8192SPHYREG_H
5 *
6 *
7 * Note: 1. Define PMAC/BB register map
8 * 2. Define RF register map
9 * 3. PMAC/BB register bit mask.
10 * 4. RF reg bit mask.
11 * 5. Other BB/RF relative definition.
12 *
13 *
14 * Export: Constants, macro, functions(API), global variables(None).
15 *
16 * Abbrev:
17 *
18 * History:
19 * Data Who Remark
20 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
21 * 2. Reorganize code architecture.
22 * 09/25/2008 MH 1. Add RL6052 register definition
23 *
24 *****************************************************************************/
25#ifndef __INC_HAL8192SPHYREG_H
26#define __INC_HAL8192SPHYREG_H
27
28
29/*--------------------------Define Parameters-------------------------------*/
30
31//============================================================
32// 8192S Regsiter offset definition
33//============================================================
34
35//
36// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
37// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
38// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39// 3. RF register 0x00-2E
40// 4. Bit Mask for BB/RF register
41// 5. Other defintion for BB/RF R/W
42//
43
44
45//
46// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
47// 1. Page1(0x100)
48//
49#define rPMAC_Reset 0x100
50#define rPMAC_TxStart 0x104
51#define rPMAC_TxLegacySIG 0x108
52#define rPMAC_TxHTSIG1 0x10c
53#define rPMAC_TxHTSIG2 0x110
54#define rPMAC_PHYDebug 0x114
55#define rPMAC_TxPacketNum 0x118
56#define rPMAC_TxIdle 0x11c
57#define rPMAC_TxMACHeader0 0x120
58#define rPMAC_TxMACHeader1 0x124
59#define rPMAC_TxMACHeader2 0x128
60#define rPMAC_TxMACHeader3 0x12c
61#define rPMAC_TxMACHeader4 0x130
62#define rPMAC_TxMACHeader5 0x134
63#define rPMAC_TxDataType 0x138
64#define rPMAC_TxRandomSeed 0x13c
65#define rPMAC_CCKPLCPPreamble 0x140
66#define rPMAC_CCKPLCPHeader 0x144
67#define rPMAC_CCKCRC16 0x148
68#define rPMAC_OFDMRxCRC32OK 0x170
69#define rPMAC_OFDMRxCRC32Er 0x174
70#define rPMAC_OFDMRxParityEr 0x178
71#define rPMAC_OFDMRxCRC8Er 0x17c
72#define rPMAC_CCKCRxRC16Er 0x180
73#define rPMAC_CCKCRxRC32Er 0x184
74#define rPMAC_CCKCRxRC32OK 0x188
75#define rPMAC_TxStatus 0x18c
76
77//
78// 2. Page2(0x200)
79//
80// The following two definition are only used for USB interface.
81#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
82#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
83
84//
85// 3. Page8(0x800)
86//
87#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
88
89#define rFPGA0_TxInfo 0x804 // Status report??
90#define rFPGA0_PSDFunction 0x808
91
92#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
93
94#define rFPGA0_RFTiming1 0x810 // Useless now
95#define rFPGA0_RFTiming2 0x814
96//#define rFPGA0_XC_RFTiming 0x818
97//#define rFPGA0_XD_RFTiming 0x81c
98
99#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
100#define rFPGA0_XA_HSSIParameter2 0x824
101#define rFPGA0_XB_HSSIParameter1 0x828
102#define rFPGA0_XB_HSSIParameter2 0x82c
103#define rFPGA0_XC_HSSIParameter1 0x830
104#define rFPGA0_XC_HSSIParameter2 0x834
105#define rFPGA0_XD_HSSIParameter1 0x838
106#define rFPGA0_XD_HSSIParameter2 0x83c
107#define rFPGA0_XA_LSSIParameter 0x840
108#define rFPGA0_XB_LSSIParameter 0x844
109#define rFPGA0_XC_LSSIParameter 0x848
110#define rFPGA0_XD_LSSIParameter 0x84c
111
112#define rFPGA0_RFWakeUpParameter 0x850 // Useless now
113#define rFPGA0_RFSleepUpParameter 0x854
114
115#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
116#define rFPGA0_XCD_SwitchControl 0x85c
117
118#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
119#define rFPGA0_XB_RFInterfaceOE 0x864
120#define rFPGA0_XC_RFInterfaceOE 0x868
121#define rFPGA0_XD_RFInterfaceOE 0x86c
122
123#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
124#define rFPGA0_XCD_RFInterfaceSW 0x874
125
126#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
127#define rFPGA0_XCD_RFParameter 0x87c
128
129#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
130#define rFPGA0_AnalogParameter2 0x884
131#define rFPGA0_AnalogParameter3 0x888 // Useless now
132#define rFPGA0_AnalogParameter4 0x88c
133
134#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
135#define rFPGA0_XB_LSSIReadBack 0x8a4
136#define rFPGA0_XC_LSSIReadBack 0x8a8
137#define rFPGA0_XD_LSSIReadBack 0x8ac
138
139#define rFPGA0_PSDReport 0x8b4 // Useless now
140#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
141#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
142#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
143#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
144
145//
146// 4. Page9(0x900)
147//
148#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
149
150#define rFPGA1_TxBlock 0x904 // Useless now
151#define rFPGA1_DebugSelect 0x908 // Useless now
152#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
153
154//
155// 5. PageA(0xA00)
156//
157// Set Control channel to upper or lower. These settings are required only for 40MHz
158#define rCCK0_System 0xa00
159
160#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
161#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
162
163#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
164#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
165
166#define rCCK0_RxHP 0xa14
167
168#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
169#define rCCK0_DSPParameter2 0xa1c //SQ threshold
170
171#define rCCK0_TxFilter1 0xa20
172#define rCCK0_TxFilter2 0xa24
173#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
174#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
175#define rCCK0_TRSSIReport 0xa50
176#define rCCK0_RxReport 0xa54 //0xa57
177#define rCCK0_FACounterLower 0xa5c //0xa5b
178#define rCCK0_FACounterUpper 0xa58 //0xa5c
179
180//
181// 6. PageC(0xC00)
182//
183#define rOFDM0_LSTF 0xc00
184
185#define rOFDM0_TRxPathEnable 0xc04
186#define rOFDM0_TRMuxPar 0xc08
187#define rOFDM0_TRSWIsolation 0xc0c
188
189#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
190#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
191#define rOFDM0_XBRxAFE 0xc18
192#define rOFDM0_XBRxIQImbalance 0xc1c
193#define rOFDM0_XCRxAFE 0xc20
194#define rOFDM0_XCRxIQImbalance 0xc24
195#define rOFDM0_XDRxAFE 0xc28
196#define rOFDM0_XDRxIQImbalance 0xc2c
197
198#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
199#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
200#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
201#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
202
203#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
204#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
205#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
206#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
207
208#define rOFDM0_XAAGCCore1 0xc50 // DIG
209#define rOFDM0_XAAGCCore2 0xc54
210#define rOFDM0_XBAGCCore1 0xc58
211#define rOFDM0_XBAGCCore2 0xc5c
212#define rOFDM0_XCAGCCore1 0xc60
213#define rOFDM0_XCAGCCore2 0xc64
214#define rOFDM0_XDAGCCore1 0xc68
215#define rOFDM0_XDAGCCore2 0xc6c
216
217#define rOFDM0_AGCParameter1 0xc70
218#define rOFDM0_AGCParameter2 0xc74
219#define rOFDM0_AGCRSSITable 0xc78
220#define rOFDM0_HTSTFAGC 0xc7c
221
222#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
223#define rOFDM0_XATxAFE 0xc84
224#define rOFDM0_XBTxIQImbalance 0xc88
225#define rOFDM0_XBTxAFE 0xc8c
226#define rOFDM0_XCTxIQImbalance 0xc90
227#define rOFDM0_XCTxAFE 0xc94
228#define rOFDM0_XDTxIQImbalance 0xc98
229#define rOFDM0_XDTxAFE 0xc9c
230
231#define rOFDM0_RxHPParameter 0xce0
232#define rOFDM0_TxPseudoNoiseWgt 0xce4
233#define rOFDM0_FrameSync 0xcf0
234#define rOFDM0_DFSReport 0xcf4
235#define rOFDM0_TxCoeff1 0xca4
236#define rOFDM0_TxCoeff2 0xca8
237#define rOFDM0_TxCoeff3 0xcac
238#define rOFDM0_TxCoeff4 0xcb0
239#define rOFDM0_TxCoeff5 0xcb4
240#define rOFDM0_TxCoeff6 0xcb8
241
242
243//
244// 7. PageD(0xD00)
245//
246#define rOFDM1_LSTF 0xd00
247#define rOFDM1_TRxPathEnable 0xd04
248#define rOFDM1_CFO 0xd08 // No setting now
249#define rOFDM1_CSI1 0xd10
250#define rOFDM1_SBD 0xd14
251#define rOFDM1_CSI2 0xd18
252#define rOFDM1_CFOTracking 0xd2c
253#define rOFDM1_TRxMesaure1 0xd34
254#define rOFDM1_IntfDet 0xd3c
255#define rOFDM1_PseudoNoiseStateAB 0xd50
256#define rOFDM1_PseudoNoiseStateCD 0xd54
257#define rOFDM1_RxPseudoNoiseWgt 0xd58
258
259#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
260#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
261#define rOFDM_PHYCounter3 0xda8 //MCS not support
262#define rOFDM_ShortCFOAB 0xdac // No setting now
263#define rOFDM_ShortCFOCD 0xdb0
264#define rOFDM_LongCFOAB 0xdb4
265#define rOFDM_LongCFOCD 0xdb8
266#define rOFDM_TailCFOAB 0xdbc
267#define rOFDM_TailCFOCD 0xdc0
268#define rOFDM_PWMeasure1 0xdc4
269#define rOFDM_PWMeasure2 0xdc8
270#define rOFDM_BWReport 0xdcc
271#define rOFDM_AGCReport 0xdd0
272#define rOFDM_RxSNR 0xdd4
273#define rOFDM_RxEVMCSI 0xdd8
274#define rOFDM_SIGReport 0xddc
275
276
277//
278// 8. PageE(0xE00)
279//
280#define rTxAGC_Rate18_06 0xe00
281#define rTxAGC_Rate54_24 0xe04
282#define rTxAGC_CCK_Mcs32 0xe08
283#define rTxAGC_Mcs03_Mcs00 0xe10
284#define rTxAGC_Mcs07_Mcs04 0xe14
285#define rTxAGC_Mcs11_Mcs08 0xe18
286#define rTxAGC_Mcs15_Mcs12 0xe1c
287
288//
289// 7. RF Register 0x00-0x2E (RF 8256)
290// RF-0222D 0x00-3F
291//
292//Zebra1
293#define rZebra1_HSSIEnable 0x0 // Useless now
294#define rZebra1_TRxEnable1 0x1
295#define rZebra1_TRxEnable2 0x2
296#define rZebra1_AGC 0x4
297#define rZebra1_ChargePump 0x5
298//#if (RTL92SE_FPGA_VERIFY == 1)
299#define rZebra1_Channel 0x7 // RF channel switch
300//#else
301
302//#endif
303#define rZebra1_TxGain 0x8 // Useless now
304#define rZebra1_TxLPF 0x9
305#define rZebra1_RxLPF 0xb
306#define rZebra1_RxHPFCorner 0xc
307
308//Zebra4
309#define rGlobalCtrl 0 // Useless now
310#define rRTL8256_TxLPF 19
311#define rRTL8256_RxLPF 11
312
313//RTL8258
314#define rRTL8258_TxLPF 0x11 // Useless now
315#define rRTL8258_RxLPF 0x13
316#define rRTL8258_RSSILPF 0xa
317
318//
319// RL6052 Register definition
320//
321#define RF_AC 0x00 //
322
323#define RF_IQADJ_G1 0x01 //
324#define RF_IQADJ_G2 0x02 //
325#define RF_POW_TRSW 0x05 //
326
327#define RF_GAIN_RX 0x06 //
328#define RF_GAIN_TX 0x07 //
329
330#define RF_TXM_IDAC 0x08 //
331#define RF_BS_IQGEN 0x0F //
332
333#define RF_MODE1 0x10 //
334#define RF_MODE2 0x11 //
335
336#define RF_RX_AGC_HP 0x12 //
337#define RF_TX_AGC 0x13 //
338#define RF_BIAS 0x14 //
339#define RF_IPA 0x15 //
340#define RF_POW_ABILITY 0x17 //
341#define RF_MODE_AG 0x18 //
342#define rRfChannel 0x18 // RF channel and BW switch
343#define RF_CHNLBW 0x18 // RF channel and BW switch
344#define RF_TOP 0x19 //
345
346#define RF_RX_G1 0x1A //
347#define RF_RX_G2 0x1B //
348
349#define RF_RX_BB2 0x1C //
350#define RF_RX_BB1 0x1D //
351
352#define RF_RCK1 0x1E //
353#define RF_RCK2 0x1F //
354
355#define RF_TX_G1 0x20 //
356#define RF_TX_G2 0x21 //
357#define RF_TX_G3 0x22 //
358
359#define RF_TX_BB1 0x23 //
360
361#define RF_T_METER 0x24 //
362
363#define RF_SYN_G1 0x25 // RF TX Power control
364#define RF_SYN_G2 0x26 // RF TX Power control
365#define RF_SYN_G3 0x27 // RF TX Power control
366#define RF_SYN_G4 0x28 // RF TX Power control
367#define RF_SYN_G5 0x29 // RF TX Power control
368#define RF_SYN_G6 0x2A // RF TX Power control
369#define RF_SYN_G7 0x2B // RF TX Power control
370#define RF_SYN_G8 0x2C // RF TX Power control
371
372#define RF_RCK_OS 0x30 // RF TX PA control
373
374#define RF_TXPA_G1 0x31 // RF TX PA control
375#define RF_TXPA_G2 0x32 // RF TX PA control
376#define RF_TXPA_G3 0x33 // RF TX PA control
377
378//
379//Bit Mask
380//
381// 1. Page1(0x100)
382#define bBBResetB 0x100 // Useless now?
383#define bGlobalResetB 0x200
384#define bOFDMTxStart 0x4
385#define bCCKTxStart 0x8
386#define bCRC32Debug 0x100
387#define bPMACLoopback 0x10
388#define bTxLSIG 0xffffff
389#define bOFDMTxRate 0xf
390#define bOFDMTxReserved 0x10
391#define bOFDMTxLength 0x1ffe0
392#define bOFDMTxParity 0x20000
393#define bTxHTSIG1 0xffffff
394#define bTxHTMCSRate 0x7f
395#define bTxHTBW 0x80
396#define bTxHTLength 0xffff00
397#define bTxHTSIG2 0xffffff
398#define bTxHTSmoothing 0x1
399#define bTxHTSounding 0x2
400#define bTxHTReserved 0x4
401#define bTxHTAggreation 0x8
402#define bTxHTSTBC 0x30
403#define bTxHTAdvanceCoding 0x40
404#define bTxHTShortGI 0x80
405#define bTxHTNumberHT_LTF 0x300
406#define bTxHTCRC8 0x3fc00
407#define bCounterReset 0x10000
408#define bNumOfOFDMTx 0xffff
409#define bNumOfCCKTx 0xffff0000
410#define bTxIdleInterval 0xffff
411#define bOFDMService 0xffff0000
412#define bTxMACHeader 0xffffffff
413#define bTxDataInit 0xff
414#define bTxHTMode 0x100
415#define bTxDataType 0x30000
416#define bTxRandomSeed 0xffffffff
417#define bCCKTxPreamble 0x1
418#define bCCKTxSFD 0xffff0000
419#define bCCKTxSIG 0xff
420#define bCCKTxService 0xff00
421#define bCCKLengthExt 0x8000
422#define bCCKTxLength 0xffff0000
423#define bCCKTxCRC16 0xffff
424#define bCCKTxStatus 0x1
425#define bOFDMTxStatus 0x2
426
427#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
428
429// 2. Page8(0x800)
430#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
431#define bJapanMode 0x2
432#define bCCKTxSC 0x30
433#define bCCKEn 0x1000000
434#define bOFDMEn 0x2000000
435
436#define bOFDMRxADCPhase 0x10000 // Useless now
437#define bOFDMTxDACPhase 0x40000
438#define bXATxAGC 0x3f
439
440#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
441#define bXCTxAGC 0xf000
442#define bXDTxAGC 0xf0000
443
444#define bPAStart 0xf0000000 // Useless now
445#define bTRStart 0x00f00000
446#define bRFStart 0x0000f000
447#define bBBStart 0x000000f0
448#define bBBCCKStart 0x0000000f
449#define bPAEnd 0xf //Reg0x814
450#define bTREnd 0x0f000000
451#define bRFEnd 0x000f0000
452#define bCCAMask 0x000000f0 //T2R
453#define bR2RCCAMask 0x00000f00
454#define bHSSI_R2TDelay 0xf8000000
455#define bHSSI_T2RDelay 0xf80000
456#define bContTxHSSI 0x400 //chane gain at continue Tx
457#define bIGFromCCK 0x200
458#define bAGCAddress 0x3f
459#define bRxHPTx 0x7000
460#define bRxHPT2R 0x38000
461#define bRxHPCCKIni 0xc0000
462#define bAGCTxCode 0xc00000
463#define bAGCRxCode 0x300000
464
465#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
466#define b3WireAddressLength 0x400
467
468#define b3WireRFPowerDown 0x1 // Useless now
469//#define bHWSISelect 0x8
470#define b5GPAPEPolarity 0x40000000
471#define b2GPAPEPolarity 0x80000000
472#define bRFSW_TxDefaultAnt 0x3
473#define bRFSW_TxOptionAnt 0x30
474#define bRFSW_RxDefaultAnt 0x300
475#define bRFSW_RxOptionAnt 0x3000
476#define bRFSI_3WireData 0x1
477#define bRFSI_3WireClock 0x2
478#define bRFSI_3WireLoad 0x4
479#define bRFSI_3WireRW 0x8
480#define bRFSI_3Wire 0xf
481
482#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
483
484#define bRFSI_TRSW 0x20 // Useless now
485#define bRFSI_TRSWB 0x40
486#define bRFSI_ANTSW 0x100
487#define bRFSI_ANTSWB 0x200
488#define bRFSI_PAPE 0x400
489#define bRFSI_PAPE5G 0x800
490#define bBandSelect 0x1
491#define bHTSIG2_GI 0x80
492#define bHTSIG2_Smoothing 0x01
493#define bHTSIG2_Sounding 0x02
494#define bHTSIG2_Aggreaton 0x08
495#define bHTSIG2_STBC 0x30
496#define bHTSIG2_AdvCoding 0x40
497#define bHTSIG2_NumOfHTLTF 0x300
498#define bHTSIG2_CRC8 0x3fc
499#define bHTSIG1_MCS 0x7f
500#define bHTSIG1_BandWidth 0x80
501#define bHTSIG1_HTLength 0xffff
502#define bLSIG_Rate 0xf
503#define bLSIG_Reserved 0x10
504#define bLSIG_Length 0x1fffe
505#define bLSIG_Parity 0x20
506#define bCCKRxPhase 0x4
507#define bLSSIReadAddress 0x7f800000 // T65 RF
508#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
509#define bLSSIReadBackData 0xfffff // T65 RF
510#define bLSSIReadOKFlag 0x1000 // Useless now
511#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
512#define bRegulator0Standby 0x1
513#define bRegulatorPLLStandby 0x2
514#define bRegulator1Standby 0x4
515#define bPLLPowerUp 0x8
516#define bDPLLPowerUp 0x10
517#define bDA10PowerUp 0x20
518#define bAD7PowerUp 0x200
519#define bDA6PowerUp 0x2000
520#define bXtalPowerUp 0x4000
521#define b40MDClkPowerUP 0x8000
522#define bDA6DebugMode 0x20000
523#define bDA6Swing 0x380000
524
525#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
526
527#define b80MClkDelay 0x18000000 // Useless
528#define bAFEWatchDogEnable 0x20000000
529
530#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
531#define bXtalCap23 0x3
532#define bXtalCap92x 0x0f000000
533#define bXtalCap 0x0f000000
534
535#define bIntDifClkEnable 0x400 // Useless
536#define bExtSigClkEnable 0x800
537#define bBandgapMbiasPowerUp 0x10000
538#define bAD11SHGain 0xc0000
539#define bAD11InputRange 0x700000
540#define bAD11OPCurrent 0x3800000
541#define bIPathLoopback 0x4000000
542#define bQPathLoopback 0x8000000
543#define bAFELoopback 0x10000000
544#define bDA10Swing 0x7e0
545#define bDA10Reverse 0x800
546#define bDAClkSource 0x1000
547#define bAD7InputRange 0x6000
548#define bAD7Gain 0x38000
549#define bAD7OutputCMMode 0x40000
550#define bAD7InputCMMode 0x380000
551#define bAD7Current 0xc00000
552#define bRegulatorAdjust 0x7000000
553#define bAD11PowerUpAtTx 0x1
554#define bDA10PSAtTx 0x10
555#define bAD11PowerUpAtRx 0x100
556#define bDA10PSAtRx 0x1000
557#define bCCKRxAGCFormat 0x200
558#define bPSDFFTSamplepPoint 0xc000
559#define bPSDAverageNum 0x3000
560#define bIQPathControl 0xc00
561#define bPSDFreq 0x3ff
562#define bPSDAntennaPath 0x30
563#define bPSDIQSwitch 0x40
564#define bPSDRxTrigger 0x400000
565#define bPSDTxTrigger 0x80000000
566#define bPSDSineToneScale 0x7f000000
567#define bPSDReport 0xffff
568
569// 3. Page9(0x900)
570#define bOFDMTxSC 0x30000000 // Useless
571#define bCCKTxOn 0x1
572#define bOFDMTxOn 0x2
573#define bDebugPage 0xfff //reset debug page and also HWord, LWord
574#define bDebugItem 0xff //reset debug page and LWord
575#define bAntL 0x10
576#define bAntNonHT 0x100
577#define bAntHT1 0x1000
578#define bAntHT2 0x10000
579#define bAntHT1S1 0x100000
580#define bAntNonHTS1 0x1000000
581
582// 4. PageA(0xA00)
583#define bCCKBBMode 0x3 // Useless
584#define bCCKTxPowerSaving 0x80
585#define bCCKRxPowerSaving 0x40
586
587#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
588
589#define bCCKScramble 0x8 // Useless
590#define bCCKAntDiversity 0x8000
591#define bCCKCarrierRecovery 0x4000
592#define bCCKTxRate 0x3000
593#define bCCKDCCancel 0x0800
594#define bCCKISICancel 0x0400
595#define bCCKMatchFilter 0x0200
596#define bCCKEqualizer 0x0100
597#define bCCKPreambleDetect 0x800000
598#define bCCKFastFalseCCA 0x400000
599#define bCCKChEstStart 0x300000
600#define bCCKCCACount 0x080000
601#define bCCKcs_lim 0x070000
602#define bCCKBistMode 0x80000000
603#define bCCKCCAMask 0x40000000
604#define bCCKTxDACPhase 0x4
605#define bCCKRxADCPhase 0x20000000 //r_rx_clk
606#define bCCKr_cp_mode0 0x0100
607#define bCCKTxDCOffset 0xf0
608#define bCCKRxDCOffset 0xf
609#define bCCKCCAMode 0xc000
610#define bCCKFalseCS_lim 0x3f00
611#define bCCKCS_ratio 0xc00000
612#define bCCKCorgBit_sel 0x300000
613#define bCCKPD_lim 0x0f0000
614#define bCCKNewCCA 0x80000000
615#define bCCKRxHPofIG 0x8000
616#define bCCKRxIG 0x7f00
617#define bCCKLNAPolarity 0x800000
618#define bCCKRx1stGain 0x7f0000
619#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
620#define bCCKRxAGCSatLevel 0x1f000000
621#define bCCKRxAGCSatCount 0xe0
622#define bCCKRxRFSettle 0x1f //AGCsamp_dly
623#define bCCKFixedRxAGC 0x8000
624//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
625#define bCCKAntennaPolarity 0x2000
626#define bCCKTxFilterType 0x0c00
627#define bCCKRxAGCReportType 0x0300
628#define bCCKRxDAGCEn 0x80000000
629#define bCCKRxDAGCPeriod 0x20000000
630#define bCCKRxDAGCSatLevel 0x1f000000
631#define bCCKTimingRecovery 0x800000
632#define bCCKTxC0 0x3f0000
633#define bCCKTxC1 0x3f000000
634#define bCCKTxC2 0x3f
635#define bCCKTxC3 0x3f00
636#define bCCKTxC4 0x3f0000
637#define bCCKTxC5 0x3f000000
638#define bCCKTxC6 0x3f
639#define bCCKTxC7 0x3f00
640#define bCCKDebugPort 0xff0000
641#define bCCKDACDebug 0x0f000000
642#define bCCKFalseAlarmEnable 0x8000
643#define bCCKFalseAlarmRead 0x4000
644#define bCCKTRSSI 0x7f
645#define bCCKRxAGCReport 0xfe
646#define bCCKRxReport_AntSel 0x80000000
647#define bCCKRxReport_MFOff 0x40000000
648#define bCCKRxRxReport_SQLoss 0x20000000
649#define bCCKRxReport_Pktloss 0x10000000
650#define bCCKRxReport_Lockedbit 0x08000000
651#define bCCKRxReport_RateError 0x04000000
652#define bCCKRxReport_RxRate 0x03000000
653#define bCCKRxFACounterLower 0xff
654#define bCCKRxFACounterUpper 0xff000000
655#define bCCKRxHPAGCStart 0xe000
656#define bCCKRxHPAGCFinal 0x1c00
657#define bCCKRxFalseAlarmEnable 0x8000
658#define bCCKFACounterFreeze 0x4000
659#define bCCKTxPathSel 0x10000000
660#define bCCKDefaultRxPath 0xc000000
661#define bCCKOptionRxPath 0x3000000
662
663// 5. PageC(0xC00)
664#define bNumOfSTF 0x3 // Useless
665#define bShift_L 0xc0
666#define bGI_TH 0xc
667#define bRxPathA 0x1
668#define bRxPathB 0x2
669#define bRxPathC 0x4
670#define bRxPathD 0x8
671#define bTxPathA 0x1
672#define bTxPathB 0x2
673#define bTxPathC 0x4
674#define bTxPathD 0x8
675#define bTRSSIFreq 0x200
676#define bADCBackoff 0x3000
677#define bDFIRBackoff 0xc000
678#define bTRSSILatchPhase 0x10000
679#define bRxIDCOffset 0xff
680#define bRxQDCOffset 0xff00
681#define bRxDFIRMode 0x1800000
682#define bRxDCNFType 0xe000000
683#define bRXIQImb_A 0x3ff
684#define bRXIQImb_B 0xfc00
685#define bRXIQImb_C 0x3f0000
686#define bRXIQImb_D 0xffc00000
687#define bDC_dc_Notch 0x60000
688#define bRxNBINotch 0x1f000000
689#define bPD_TH 0xf
690#define bPD_TH_Opt2 0xc000
691#define bPWED_TH 0x700
692#define bIfMF_Win_L 0x800
693#define bPD_Option 0x1000
694#define bMF_Win_L 0xe000
695#define bBW_Search_L 0x30000
696#define bwin_enh_L 0xc0000
697#define bBW_TH 0x700000
698#define bED_TH2 0x3800000
699#define bBW_option 0x4000000
700#define bRatio_TH 0x18000000
701#define bWindow_L 0xe0000000
702#define bSBD_Option 0x1
703#define bFrame_TH 0x1c
704#define bFS_Option 0x60
705#define bDC_Slope_check 0x80
706#define bFGuard_Counter_DC_L 0xe00
707#define bFrame_Weight_Short 0x7000
708#define bSub_Tune 0xe00000
709#define bFrame_DC_Length 0xe000000
710#define bSBD_start_offset 0x30000000
711#define bFrame_TH_2 0x7
712#define bFrame_GI2_TH 0x38
713#define bGI2_Sync_en 0x40
714#define bSarch_Short_Early 0x300
715#define bSarch_Short_Late 0xc00
716#define bSarch_GI2_Late 0x70000
717#define bCFOAntSum 0x1
718#define bCFOAcc 0x2
719#define bCFOStartOffset 0xc
720#define bCFOLookBack 0x70
721#define bCFOSumWeight 0x80
722#define bDAGCEnable 0x10000
723#define bTXIQImb_A 0x3ff
724#define bTXIQImb_B 0xfc00
725#define bTXIQImb_C 0x3f0000
726#define bTXIQImb_D 0xffc00000
727#define bTxIDCOffset 0xff
728#define bTxQDCOffset 0xff00
729#define bTxDFIRMode 0x10000
730#define bTxPesudoNoiseOn 0x4000000
731#define bTxPesudoNoise_A 0xff
732#define bTxPesudoNoise_B 0xff00
733#define bTxPesudoNoise_C 0xff0000
734#define bTxPesudoNoise_D 0xff000000
735#define bCCADropOption 0x20000
736#define bCCADropThres 0xfff00000
737#define bEDCCA_H 0xf
738#define bEDCCA_L 0xf0
739#define bLambda_ED 0x300
740#define bRxInitialGain 0x7f
741#define bRxAntDivEn 0x80
742#define bRxAGCAddressForLNA 0x7f00
743#define bRxHighPowerFlow 0x8000
744#define bRxAGCFreezeThres 0xc0000
745#define bRxFreezeStep_AGC1 0x300000
746#define bRxFreezeStep_AGC2 0xc00000
747#define bRxFreezeStep_AGC3 0x3000000
748#define bRxFreezeStep_AGC0 0xc000000
749#define bRxRssi_Cmp_En 0x10000000
750#define bRxQuickAGCEn 0x20000000
751#define bRxAGCFreezeThresMode 0x40000000
752#define bRxOverFlowCheckType 0x80000000
753#define bRxAGCShift 0x7f
754#define bTRSW_Tri_Only 0x80
755#define bPowerThres 0x300
756#define bRxAGCEn 0x1
757#define bRxAGCTogetherEn 0x2
758#define bRxAGCMin 0x4
759#define bRxHP_Ini 0x7
760#define bRxHP_TRLNA 0x70
761#define bRxHP_RSSI 0x700
762#define bRxHP_BBP1 0x7000
763#define bRxHP_BBP2 0x70000
764#define bRxHP_BBP3 0x700000
765#define bRSSI_H 0x7f0000 //the threshold for high power
766#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
767#define bRxSettle_TRSW 0x7
768#define bRxSettle_LNA 0x38
769#define bRxSettle_RSSI 0x1c0
770#define bRxSettle_BBP 0xe00
771#define bRxSettle_RxHP 0x7000
772#define bRxSettle_AntSW_RSSI 0x38000
773#define bRxSettle_AntSW 0xc0000
774#define bRxProcessTime_DAGC 0x300000
775#define bRxSettle_HSSI 0x400000
776#define bRxProcessTime_BBPPW 0x800000
777#define bRxAntennaPowerShift 0x3000000
778#define bRSSITableSelect 0xc000000
779#define bRxHP_Final 0x7000000
780#define bRxHTSettle_BBP 0x7
781#define bRxHTSettle_HSSI 0x8
782#define bRxHTSettle_RxHP 0x70
783#define bRxHTSettle_BBPPW 0x80
784#define bRxHTSettle_Idle 0x300
785#define bRxHTSettle_Reserved 0x1c00
786#define bRxHTRxHPEn 0x8000
787#define bRxHTAGCFreezeThres 0x30000
788#define bRxHTAGCTogetherEn 0x40000
789#define bRxHTAGCMin 0x80000
790#define bRxHTAGCEn 0x100000
791#define bRxHTDAGCEn 0x200000
792#define bRxHTRxHP_BBP 0x1c00000
793#define bRxHTRxHP_Final 0xe0000000
794#define bRxPWRatioTH 0x3
795#define bRxPWRatioEn 0x4
796#define bRxMFHold 0x3800
797#define bRxPD_Delay_TH1 0x38
798#define bRxPD_Delay_TH2 0x1c0
799#define bRxPD_DC_COUNT_MAX 0x600
800//#define bRxMF_Hold 0x3800
801#define bRxPD_Delay_TH 0x8000
802#define bRxProcess_Delay 0xf0000
803#define bRxSearchrange_GI2_Early 0x700000
804#define bRxFrame_Guard_Counter_L 0x3800000
805#define bRxSGI_Guard_L 0xc000000
806#define bRxSGI_Search_L 0x30000000
807#define bRxSGI_TH 0xc0000000
808#define bDFSCnt0 0xff
809#define bDFSCnt1 0xff00
810#define bDFSFlag 0xf0000
811#define bMFWeightSum 0x300000
812#define bMinIdxTH 0x7f000000
813#define bDAFormat 0x40000
814#define bTxChEmuEnable 0x01000000
815#define bTRSWIsolation_A 0x7f
816#define bTRSWIsolation_B 0x7f00
817#define bTRSWIsolation_C 0x7f0000
818#define bTRSWIsolation_D 0x7f000000
819#define bExtLNAGain 0x7c00
820
821// 6. PageE(0xE00)
822#define bSTBCEn 0x4 // Useless
823#define bAntennaMapping 0x10
824#define bNss 0x20
825#define bCFOAntSumD 0x200
826#define bPHYCounterReset 0x8000000
827#define bCFOReportGet 0x4000000
828#define bOFDMContinueTx 0x10000000
829#define bOFDMSingleCarrier 0x20000000
830#define bOFDMSingleTone 0x40000000
831//#define bRxPath1 0x01
832//#define bRxPath2 0x02
833//#define bRxPath3 0x04
834//#define bRxPath4 0x08
835//#define bTxPath1 0x10
836//#define bTxPath2 0x20
837#define bHTDetect 0x100
838#define bCFOEn 0x10000
839#define bCFOValue 0xfff00000
840#define bSigTone_Re 0x3f
841#define bSigTone_Im 0x7f00
842#define bCounter_CCA 0xffff
843#define bCounter_ParityFail 0xffff0000
844#define bCounter_RateIllegal 0xffff
845#define bCounter_CRC8Fail 0xffff0000
846#define bCounter_MCSNoSupport 0xffff
847#define bCounter_FastSync 0xffff
848#define bShortCFO 0xfff
849#define bShortCFOTLength 12 //total
850#define bShortCFOFLength 11 //fraction
851#define bLongCFO 0x7ff
852#define bLongCFOTLength 11
853#define bLongCFOFLength 11
854#define bTailCFO 0x1fff
855#define bTailCFOTLength 13
856#define bTailCFOFLength 12
857#define bmax_en_pwdB 0xffff
858#define bCC_power_dB 0xffff0000
859#define bnoise_pwdB 0xffff
860#define bPowerMeasTLength 10
861#define bPowerMeasFLength 3
862#define bRx_HT_BW 0x1
863#define bRxSC 0x6
864#define bRx_HT 0x8
865#define bNB_intf_det_on 0x1
866#define bIntf_win_len_cfg 0x30
867#define bNB_Intf_TH_cfg 0x1c0
868#define bRFGain 0x3f
869#define bTableSel 0x40
870#define bTRSW 0x80
871#define bRxSNR_A 0xff
872#define bRxSNR_B 0xff00
873#define bRxSNR_C 0xff0000
874#define bRxSNR_D 0xff000000
875#define bSNREVMTLength 8
876#define bSNREVMFLength 1
877#define bCSI1st 0xff
878#define bCSI2nd 0xff00
879#define bRxEVM1st 0xff0000
880#define bRxEVM2nd 0xff000000
881#define bSIGEVM 0xff
882#define bPWDB 0xff00
883#define bSGIEN 0x10000
884
885#define bSFactorQAM1 0xf // Useless
886#define bSFactorQAM2 0xf0
887#define bSFactorQAM3 0xf00
888#define bSFactorQAM4 0xf000
889#define bSFactorQAM5 0xf0000
890#define bSFactorQAM6 0xf0000
891#define bSFactorQAM7 0xf00000
892#define bSFactorQAM8 0xf000000
893#define bSFactorQAM9 0xf0000000
894#define bCSIScheme 0x100000
895
896#define bNoiseLvlTopSet 0x3 // Useless
897#define bChSmooth 0x4
898#define bChSmoothCfg1 0x38
899#define bChSmoothCfg2 0x1c0
900#define bChSmoothCfg3 0xe00
901#define bChSmoothCfg4 0x7000
902#define bMRCMode 0x800000
903#define bTHEVMCfg 0x7000000
904
905#define bLoopFitType 0x1 // Useless
906#define bUpdCFO 0x40
907#define bUpdCFOOffData 0x80
908#define bAdvUpdCFO 0x100
909#define bAdvTimeCtrl 0x800
910#define bUpdClko 0x1000
911#define bFC 0x6000
912#define bTrackingMode 0x8000
913#define bPhCmpEnable 0x10000
914#define bUpdClkoLTF 0x20000
915#define bComChCFO 0x40000
916#define bCSIEstiMode 0x80000
917#define bAdvUpdEqz 0x100000
918#define bUChCfg 0x7000000
919#define bUpdEqz 0x8000000
920
921#define bTxAGCRate18_06 0x7f7f7f7f // Useless
922#define bTxAGCRate54_24 0x7f7f7f7f
923#define bTxAGCRateMCS32 0x7f
924#define bTxAGCRateCCK 0x7f00
925#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
926#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
927#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
928#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
929
930//Rx Pseduo noise
931#define bRxPesudoNoiseOn 0x20000000 // Useless
932#define bRxPesudoNoise_A 0xff
933#define bRxPesudoNoise_B 0xff00
934#define bRxPesudoNoise_C 0xff0000
935#define bRxPesudoNoise_D 0xff000000
936#define bPesudoNoiseState_A 0xffff
937#define bPesudoNoiseState_B 0xffff0000
938#define bPesudoNoiseState_C 0xffff
939#define bPesudoNoiseState_D 0xffff0000
940
941//7. RF Register
942//Zebra1
943#define bZebra1_HSSIEnable 0x8 // Useless
944#define bZebra1_TRxControl 0xc00
945#define bZebra1_TRxGainSetting 0x07f
946#define bZebra1_RxCorner 0xc00
947#define bZebra1_TxChargePump 0x38
948#define bZebra1_RxChargePump 0x7
949#define bZebra1_ChannelNum 0xf80
950#define bZebra1_TxLPFBW 0x400
951#define bZebra1_RxLPFBW 0x600
952
953//Zebra4
954#define bRTL8256RegModeCtrl1 0x100 // Useless
955#define bRTL8256RegModeCtrl0 0x40
956#define bRTL8256_TxLPFBW 0x18
957#define bRTL8256_RxLPFBW 0x600
958
959//RTL8258
960#define bRTL8258_TxLPFBW 0xc // Useless
961#define bRTL8258_RxLPFBW 0xc00
962#define bRTL8258_RSSILPFBW 0xc0
963
964
965//
966// Other Definition
967//
968
969//byte endable for sb_write
970#define bByte0 0x1 // Useless
971#define bByte1 0x2
972#define bByte2 0x4
973#define bByte3 0x8
974#define bWord0 0x3
975#define bWord1 0xc
976#define bDWord 0xf
977
978//for PutRegsetting & GetRegSetting BitMask
979#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
980#define bMaskByte1 0xff00
981#define bMaskByte2 0xff0000
982#define bMaskByte3 0xff000000
983#define bMaskHWord 0xffff0000
984#define bMaskLWord 0x0000ffff
985#define bMaskDWord 0xffffffff
986
987//for PutRFRegsetting & GetRFRegSetting BitMask
988#define bMask12Bits 0xfffff // RF Reg mask bits
989#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
990#define bRFRegOffsetMask 0xfffff
991
992#define bEnable 0x1 // Useless
993#define bDisable 0x0
994
995#define LeftAntenna 0x0 // Useless
996#define RightAntenna 0x1
997
998#define tCheckTxStatus 500 //500ms // Useless
999#define tUpdateRxCounter 100 //100ms
1000
1001#define rateCCK 0 // Useless
1002#define rateOFDM 1
1003#define rateHT 2
1004
1005//define Register-End
1006#define bPMAC_End 0x1ff // Useless
1007#define bFPGAPHY0_End 0x8ff
1008#define bFPGAPHY1_End 0x9ff
1009#define bCCKPHY0_End 0xaff
1010#define bOFDMPHY0_End 0xcff
1011#define bOFDMPHY1_End 0xdff
1012
1013//define max debug item in each debug page
1014//#define bMaxItem_FPGA_PHY0 0x9
1015//#define bMaxItem_FPGA_PHY1 0x3
1016//#define bMaxItem_PHY_11B 0x16
1017//#define bMaxItem_OFDM_PHY0 0x29
1018//#define bMaxItem_OFDM_PHY1 0x0
1019
1020#define bPMACControl 0x0 // Useless
1021#define bWMACControl 0x1
1022#define bWNICControl 0x2
1023
1024#define PathA 0x0 // Useless
1025#define PathB 0x1
1026#define PathC 0x2
1027#define PathD 0x3
1028
1029/*--------------------------Define Parameters-------------------------------*/
1030
1031
1032#endif //__INC_HAL8192SPHYREG_H
1033
diff --git a/drivers/staging/rtl8192su/r8192S_rtl6052.c b/drivers/staging/rtl8192su/r8192S_rtl6052.c
new file mode 100644
index 00000000000..71caf81a6e1
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_rtl6052.c
@@ -0,0 +1,946 @@
1/******************************************************************************
2 *
3 * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4 *
5 * Module: HalRf6052.c ( Source C File)
6 *
7 * Note: Provide RF 6052 series relative API.
8 *
9 * Function:
10 *
11 * Export:
12 *
13 * Abbrev:
14 *
15 * History:
16 * Data Who Remark
17 *
18 * 09/25/2008 MHC Create initial version.
19 * 11/05/2008 MHC Add API for tw power setting.
20 *
21 *
22******************************************************************************/
23#include "r8192U.h"
24#include "r8192S_rtl6052.h"
25
26#ifdef RTL8192SU
27#include "r8192S_hw.h"
28#include "r8192S_phyreg.h"
29#include "r8192S_phy.h"
30#else
31#include "r8192U_hw.h"
32#include "r819xU_phyreg.h"
33#include "r819xU_phy.h"
34#endif
35
36
37/*---------------------------Define Local Constant---------------------------*/
38// Define local structure for debug!!!!!
39typedef struct RF_Shadow_Compare_Map {
40 // Shadow register value
41 u32 Value;
42 // Compare or not flag
43 u8 Compare;
44 // Record If it had ever modified unpredicted
45 u8 ErrorOrNot;
46 // Recorver Flag
47 u8 Recorver;
48 //
49 u8 Driver_Write;
50}RF_SHADOW_T;
51/*---------------------------Define Local Constant---------------------------*/
52
53
54/*------------------------Define global variable-----------------------------*/
55/*------------------------Define global variable-----------------------------*/
56
57
58
59
60/*---------------------Define local function prototype-----------------------*/
61void phy_RF6052_Config_HardCode(struct net_device* dev);
62
63RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev);
64/*---------------------Define local function prototype-----------------------*/
65
66/*------------------------Define function prototype--------------------------*/
67extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate);
68
69/*------------------------Define function prototype--------------------------*/
70
71/*------------------------Define local variable------------------------------*/
72// 2008/11/20 MH For Debug only, RF
73static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM
74/*------------------------Define local variable------------------------------*/
75
76/*------------------------Define function prototype--------------------------*/
77/*-----------------------------------------------------------------------------
78 * Function: RF_ChangeTxPath
79 *
80 * Overview: For RL6052, we must change some RF settign for 1T or 2T.
81 *
82 * Input: u16 DataRate // 0x80-8f, 0x90-9f
83 *
84 * Output: NONE
85 *
86 * Return: NONE
87 *
88 * Revised History:
89 * When Who Remark
90 * 09/25/2008 MHC Create Version 0.
91 * Firmwaer support the utility later.
92 *
93 *---------------------------------------------------------------------------*/
94extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate)
95{
96// We do not support gain table change inACUT now !!!! Delete later !!!
97#if 0//(RTL92SE_FPGA_VERIFY == 0)
98 static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
99 static u4Byte tx_gain_tbl1[6]
100 = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
101 static u4Byte tx_gain_tbl2[6]
102 = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
103 u1Byte i;
104
105 if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
106 {
107 // Set TX SYNC power G2G3 loop filter
108 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
109 RF_TXPA_G2, bMask20Bits, 0x0f000);
110 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
111 RF_TXPA_G3, bMask20Bits, 0xeacf1);
112
113 // Change TX AGC gain table
114 for (i = 0; i < 6; i++)
115 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
116 RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
117
118 // Set PA to high value
119 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
120 RF_TXPA_G2, bMask20Bits, 0x01e39);
121 }
122 else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
123 {
124 // Set TX SYNC power G2G3 loop filter
125 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
126 RF_TXPA_G2, bMask20Bits, 0x04440);
127 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
128 RF_TXPA_G3, bMask20Bits, 0xea4f1);
129
130 // Change TX AGC gain table
131 for (i = 0; i < 6; i++)
132 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
133 RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
134
135 // Set PA low gain
136 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
137 RF_TXPA_G2, bMask20Bits, 0x01e19);
138 }
139#endif
140
141} /* RF_ChangeTxPath */
142
143
144/*-----------------------------------------------------------------------------
145 * Function: PHY_RF6052SetBandwidth()
146 *
147 * Overview: This function is called by SetBWModeCallback8190Pci() only
148 *
149 * Input: PADAPTER Adapter
150 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
151 *
152 * Output: NONE
153 *
154 * Return: NONE
155 *
156 * Note: For RF type 0222D
157 *---------------------------------------------------------------------------*/
158void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
159{
160 //u8 eRFPath;
161 //struct r8192_priv *priv = ieee80211_priv(dev);
162
163
164 //if (priv->card_8192 == NIC_8192SE)
165#ifdef RTL8192SU //YJ,test,090113
166 {
167 switch(Bandwidth)
168 {
169 case HT_CHANNEL_WIDTH_20:
170 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
171 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
172
173 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
174 break;
175 case HT_CHANNEL_WIDTH_20_40:
176 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
177 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
178
179 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
180 break;
181 default:
182 RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
183 break;
184 }
185 }
186// else
187#else
188 {
189 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
190 {
191 switch(Bandwidth)
192 {
193 case HT_CHANNEL_WIDTH_20:
194 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
195 break;
196 case HT_CHANNEL_WIDTH_20_40:
197 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
198 break;
199 default:
200 RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
201 break;
202
203 }
204 }
205 }
206#endif
207}
208
209
210/*-----------------------------------------------------------------------------
211 * Function: PHY_RF6052SetCckTxPower
212 *
213 * Overview:
214 *
215 * Input: NONE
216 *
217 * Output: NONE
218 *
219 * Return: NONE
220 *
221 * Revised History:
222 * When Who Remark
223 * 11/05/2008 MHC Simulate 8192series..
224 *
225 *---------------------------------------------------------------------------*/
226extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel)
227{
228 struct r8192_priv *priv = ieee80211_priv(dev);
229 u32 TxAGC=0;
230
231 if(priv->ieee80211->scanning == 1)
232 TxAGC = 0x3f;
233 else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
234 TxAGC = 0x22;
235 else
236 TxAGC = powerlevel;
237
238 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
239 if(priv->bIgnoreDiffRateTxPowerOffset)
240 TxAGC = powerlevel;
241
242 if(TxAGC > RF6052_MAX_TX_PWR)
243 TxAGC = RF6052_MAX_TX_PWR;
244
245 //printk("CCK PWR= %x\n", TxAGC);
246 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
247
248} /* PHY_RF6052SetCckTxPower */
249
250
251
252/*-----------------------------------------------------------------------------
253 * Function: PHY_RF6052SetOFDMTxPower
254 *
255 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
256 * different channel and read original value in TX power register area from
257 * 0xe00. We increase offset and original value to be correct tx pwr.
258 *
259 * Input: NONE
260 *
261 * Output: NONE
262 *
263 * Return: NONE
264 *
265 * Revised History:
266 * When Who Remark
267 * 11/05/2008 MHC Simulate 8192 series method.
268* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
269 * A/B pwr difference or legacy/HT pwr diff.
270 * 2. We concern with path B legacy/HT OFDM difference.
271 * 01/22/2009 MHC Support new EPRO format from SD3.
272 *---------------------------------------------------------------------------*/
273 #if 1
274extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
275{
276 struct r8192_priv *priv = ieee80211_priv(dev);
277 u32 writeVal, powerBase0, powerBase1;
278 u8 index = 0;
279 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
280 //u8 byte0, byte1, byte2, byte3;
281 u8 Channel = priv->ieee80211->current_network.channel;
282 u8 rfa_pwr[4];
283 u8 rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/;
284 u8 i;
285 u8 rf_pwr_diff = 0;
286 u8 Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0;
287 u8 ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0;
288
289
290 // We only care about the path A for legacy.
291 if (priv->EEPROMVersion != 2)
292 powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
293 else if (priv->EEPROMVersion == 2) // Defined by SD1 Jong
294 {
295 //
296 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
297 //
298 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
299 // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B
300 // legacy OFDM pwr diff. NO BB register to notify HW.
301 powerBase0 = powerlevel + Legacy_pwrdiff;
302 //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff));
303
304 // Band Edge scheme is enabled for FCC mode
305 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
306 {
307 ofdm_bandedge_chnl_low = 1;
308 ofdm_bandedge_chnl_high = 11;
309 #if 0//cosa, Todo: check ofdm 40MHz, when lower and duplicate, the bandedge chnl low=3, high=9
310 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
311 { // Is it the same with the document?
312 if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
313 else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER;
314 else
315 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
316 }
317 #endif
318 BandEdge_Pwrdiff = 0;
319 if (Channel <= ofdm_bandedge_chnl_low)
320 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0];
321 else if (Channel >= ofdm_bandedge_chnl_high)
322 {
323 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1];
324 }
325 powerBase0 -= BandEdge_Pwrdiff;
326 if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high)
327 {
328 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n",
329 //Channel, BandEdge_Pwrdiff));
330 }
331 }
332 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0));
333 }
334 powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
335
336 //MCS rates
337 if(priv->EEPROMVersion == 2)
338 {
339 //Cosa add for new EEPROM content. 02102009
340
341 //Check HT20 to HT40 diff
342 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
343 {
344 // HT 20<->40 pwr diff
345 HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1];
346
347 // Calculate Antenna pwr diff
348 if (HT20_pwrdiff < 8) // 0~+7
349 powerlevel += HT20_pwrdiff;
350 else // index8-15=-8~-1
351 powerlevel -= (16-HT20_pwrdiff);
352
353 //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff));
354 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
355 }
356
357 // Band Edge scheme is enabled for FCC mode
358 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
359 {
360 BandEdge_Pwrdiff = 0;
361 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
362 {
363 if (Channel <= 3)
364 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0];
365 else if (Channel >= 9)
366 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1];
367 if (Channel <= 3 || Channel >= 9)
368 {
369 //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n",
370 //Channel, BandEdge_Pwrdiff));
371 }
372 }
373 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
374 {
375 if (Channel <= 1)
376 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0];
377 else if (Channel >= 11)
378 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1];
379 if (Channel <= 1 || Channel >= 11)
380 {
381 //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n",
382 //Channel, BandEdge_Pwrdiff));
383 }
384 }
385 powerlevel -= BandEdge_Pwrdiff;
386 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
387 }
388 }
389 powerBase1 = powerlevel;
390 powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
391
392 //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1));
393
394 for(index=0; index<6; index++)
395 {
396 //
397 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
398 //
399 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
400 if(priv->bIgnoreDiffRateTxPowerOffset)
401 writeVal = ((index<2)?powerBase0:powerBase1);
402 else
403 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
404
405 //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n",
406 //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal));
407
408 //
409 // If path A and Path B coexist, we must limit Path A tx power.
410 // Protect Path B pwr over or under flow. We need to calculate upper and
411 // lower bound of path A tx power.
412 //
413 if (priv->rf_type == RF_2T2R)
414 {
415 #if 0//cosa, we have only one AntennaTxPwDiff
416 // HT OFDM
417 if (index > 1)
418 {
419 rf_pwr_diff = pHalData->AntennaTxPwDiff[0];
420 }
421 // Legacy OFDM
422 else
423 {
424 rf_pwr_diff = pHalData->AntTxPwDiffLegacy[0];
425 }
426 #endif
427 rf_pwr_diff = priv->AntennaTxPwDiff[0];
428 //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff));
429
430 if (rf_pwr_diff >= 8) // Diff=-8~-1
431 { // Prevent underflow!!
432 rfa_lower_bound = 0x10-rf_pwr_diff;
433 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound));
434 }
435 else if (rf_pwr_diff >= 0) // Diff = 0-7
436 {
437 rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
438 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound));
439 }
440 }
441
442 for (i= 0; i <4; i++)
443 {
444 rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
445 if (rfa_pwr[i] > RF6052_MAX_TX_PWR)
446 rfa_pwr[i] = RF6052_MAX_TX_PWR;
447
448 //
449 // If path A and Path B coexist, we must limit Path A tx power.
450 // Protect Path B pwr over or under flow. We need to calculate upper and
451 // lower bound of path A tx power.
452 //
453 if (priv->rf_type == RF_2T2R)
454 {
455 if (rf_pwr_diff >= 8) // Diff=-8~-1
456 { // Prevent underflow!!
457 if (rfa_pwr[i] <rfa_lower_bound)
458 {
459 //RTPRINT(FPHY, PHY_TXPWR, ("Underflow"));
460 rfa_pwr[i] = rfa_lower_bound;
461 }
462 }
463 else if (rf_pwr_diff >= 1) // Diff = 0-7
464 { // Prevent overflow
465 if (rfa_pwr[i] > rfa_upper_bound)
466 {
467 //RTPRINT(FPHY, PHY_TXPWR, ("Overflow"));
468 rfa_pwr[i] = rfa_upper_bound;
469 }
470 }
471 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i]));
472 }
473
474 }
475
476 //
477 // Add description: PWDB > threshold!!!High power issue!!
478 // We must decrease tx power !! Why is the value ???
479 //
480 if(priv->bDynamicTxHighPower == TRUE)
481 {
482 // For MCS rate
483 if(index > 1)
484 {
485 writeVal = 0x03030303;
486 }
487 // For Legacy rate
488 else
489 {
490 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
491 }
492 //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal));
493 }
494 else
495 {
496 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
497 //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal));
498 }
499
500 //
501 // Write different rate set tx power index.
502 //
503 //if (DCMD_Test_Flag == 0)
504 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
505 }
506
507} /* PHY_RF6052SetOFDMTxPower */
508#else
509extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
510{
511 struct r8192_priv *priv = ieee80211_priv(dev);
512 u32 writeVal, powerBase0, powerBase1;
513 u8 index = 0;
514 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
515 u8 byte0, byte1, byte2, byte3;
516 u8 channel = priv->ieee80211->current_network.channel;
517
518 //Legacy OFDM rates
519 powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
520 powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
521
522 //MCS rates HT OFDM
523 powerBase1 = powerlevel;
524 powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
525
526 //printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1);
527
528 for(index=0; index<6; index++)
529 {
530 //
531 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
532 //
533 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
534
535 //printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal);
536
537 byte0 = (u8)(writeVal & 0x7f);
538 byte1 = (u8)((writeVal & 0x7f00)>>8);
539 byte2 = (u8)((writeVal & 0x7f0000)>>16);
540 byte3 = (u8)((writeVal & 0x7f000000)>>24);
541
542 // Max power index = 0x3F Range = 0-0x3F
543 if(byte0 > RF6052_MAX_TX_PWR)
544 byte0 = RF6052_MAX_TX_PWR;
545 if(byte1 > RF6052_MAX_TX_PWR)
546 byte1 = RF6052_MAX_TX_PWR;
547 if(byte2 > RF6052_MAX_TX_PWR)
548 byte2 = RF6052_MAX_TX_PWR;
549 if(byte3 > RF6052_MAX_TX_PWR)
550 byte3 = RF6052_MAX_TX_PWR;
551
552 //
553 // Add description: PWDB > threshold!!!High power issue!!
554 // We must decrease tx power !! Why is the value ???
555 //
556 if(priv->bDynamicTxHighPower == true)
557 {
558 // For MCS rate
559 if(index > 1)
560 {
561 writeVal = 0x03030303;
562 }
563 // For Legacy rate
564 else
565 {
566 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
567 }
568 }
569 else
570 {
571 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
572 }
573
574 //
575 // Write different rate set tx power index.
576 //
577 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
578 }
579
580} /* PHY_RF6052SetOFDMTxPower */
581#endif
582
583RT_STATUS PHY_RF6052_Config(struct net_device* dev)
584{
585 struct r8192_priv *priv = ieee80211_priv(dev);
586 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
587 //RF90_RADIO_PATH_E eRFPath;
588 //BB_REGISTER_DEFINITION_T *pPhyReg;
589 //u32 OrgStoreRFIntSW[RF90_PATH_D+1];
590
591 //
592 // Initialize general global value
593 //
594 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
595 if(priv->rf_type == RF_1T1R)
596 priv->NumTotalRFPath = 1;
597 else
598 priv->NumTotalRFPath = 2;
599
600 //
601 // Config BB and RF
602 //
603// switch( priv->bRegHwParaFile )
604// {
605// case 0:
606// phy_RF6052_Config_HardCode(dev);
607// break;
608
609// case 1:
610 rtStatus = phy_RF6052_Config_ParaFile(dev);
611// break;
612
613// case 2:
614 // Partial Modify.
615// phy_RF6052_Config_HardCode(dev);
616// phy_RF6052_Config_ParaFile(dev);
617// break;
618
619// default:
620// phy_RF6052_Config_HardCode(dev);
621// break;
622// }
623 return rtStatus;
624
625}
626
627void phy_RF6052_Config_HardCode(struct net_device* dev)
628{
629
630 // Set Default Bandwidth to 20M
631 //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
632
633 // TODO: Set Default Channel to channel one for RTL8225
634
635}
636
637RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev)
638{
639 u32 u4RegValue = 0;
640 //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
641 //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
642 //static s1Byte szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM;
643 u8 eRFPath;
644 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
645 struct r8192_priv *priv = ieee80211_priv(dev);
646 BB_REGISTER_DEFINITION_T *pPhyReg;
647 //u8 eCheckItem;
648
649
650 //3//-----------------------------------------------------------------
651 //3// <2> Initialize RF
652 //3//-----------------------------------------------------------------
653 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
654 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
655 {
656
657 pPhyReg = &priv->PHYRegDef[eRFPath];
658
659 /*----Store original RFENV control type----*/
660 switch(eRFPath)
661 {
662 case RF90_PATH_A:
663 case RF90_PATH_C:
664 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
665 break;
666 case RF90_PATH_B :
667 case RF90_PATH_D:
668 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
669 break;
670 }
671
672 /*----Set RF_ENV enable----*/
673 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
674
675 /*----Set RF_ENV output high----*/
676 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
677
678 /* Set bit number of Address and Data for RF register */
679 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
680 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
681
682
683 /*----Initialize RF fom connfiguration file----*/
684 switch(eRFPath)
685 {
686 case RF90_PATH_A:
687#if RTL8190_Download_Firmware_From_Header
688 rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
689#else
690 rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
691#endif
692 break;
693 case RF90_PATH_B:
694#if RTL8190_Download_Firmware_From_Header
695 rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
696#else
697 if(priv->rf_type == RF_2T2R_GREEN)
698 rtStatus = PHY_ConfigRFWithParaFile(Adapter, (ps1Byte)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath);
699 else
700 rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
701#endif
702 break;
703 case RF90_PATH_C:
704 break;
705 case RF90_PATH_D:
706 break;
707 }
708
709 /*----Restore RFENV control type----*/;
710 switch(eRFPath)
711 {
712 case RF90_PATH_A:
713 case RF90_PATH_C:
714 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
715 break;
716 case RF90_PATH_B :
717 case RF90_PATH_D:
718 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
719 break;
720 }
721
722 if(rtStatus != RT_STATUS_SUCCESS){
723 printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
724 goto phy_RF6052_Config_ParaFile_Fail;
725 }
726
727 }
728
729 RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
730 return rtStatus;
731
732phy_RF6052_Config_ParaFile_Fail:
733 return rtStatus;
734}
735
736
737//
738// ==> RF shadow Operation API Code Section!!!
739//
740/*-----------------------------------------------------------------------------
741 * Function: PHY_RFShadowRead
742 * PHY_RFShadowWrite
743 * PHY_RFShadowCompare
744 * PHY_RFShadowRecorver
745 * PHY_RFShadowCompareAll
746 * PHY_RFShadowRecorverAll
747 * PHY_RFShadowCompareFlagSet
748 * PHY_RFShadowRecorverFlagSet
749 *
750 * Overview: When we set RF register, we must write shadow at first.
751 * When we are running, we must compare shadow abd locate error addr.
752 * Decide to recorver or not.
753 *
754 * Input: NONE
755 *
756 * Output: NONE
757 *
758 * Return: NONE
759 *
760 * Revised History:
761 * When Who Remark
762 * 11/20/2008 MHC Create Version 0.
763 *
764 *---------------------------------------------------------------------------*/
765extern u32 PHY_RFShadowRead(
766 struct net_device * dev,
767 RF90_RADIO_PATH_E eRFPath,
768 u32 Offset)
769{
770 return RF_Shadow[eRFPath][Offset].Value;
771
772} /* PHY_RFShadowRead */
773
774
775extern void PHY_RFShadowWrite(
776 struct net_device * dev,
777 u32 eRFPath,
778 u32 Offset,
779 u32 Data)
780{
781 //RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits);
782 RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
783 RF_Shadow[eRFPath][Offset].Driver_Write = true;
784
785} /* PHY_RFShadowWrite */
786
787
788extern void PHY_RFShadowCompare(
789 struct net_device * dev,
790 RF90_RADIO_PATH_E eRFPath,
791 u32 Offset)
792{
793 u32 reg;
794
795 // Check if we need to check the register
796 if (RF_Shadow[eRFPath][Offset].Compare == true)
797 {
798 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask);
799 // Compare shadow and real rf register for 20bits!!
800 if (RF_Shadow[eRFPath][Offset].Value != reg)
801 {
802 // Locate error position.
803 RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
804 RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg);
805 }
806 }
807
808} /* PHY_RFShadowCompare */
809
810extern void PHY_RFShadowRecorver(
811 struct net_device * dev,
812 RF90_RADIO_PATH_E eRFPath,
813 u32 Offset)
814{
815 // Check if the address is error
816 if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
817 {
818 // Check if we need to recorver the register.
819 if (RF_Shadow[eRFPath][Offset].Recorver == true)
820 {
821 rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value);
822 RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
823 eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
824 }
825 }
826
827} /* PHY_RFShadowRecorver */
828
829
830extern void PHY_RFShadowCompareAll(struct net_device * dev)
831{
832 u32 eRFPath;
833 u32 Offset;
834
835 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
836 {
837 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
838 {
839 PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
840 }
841 }
842
843} /* PHY_RFShadowCompareAll */
844
845
846extern void PHY_RFShadowRecorverAll(struct net_device * dev)
847{
848 u32 eRFPath;
849 u32 Offset;
850
851 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
852 {
853 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
854 {
855 PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
856 }
857 }
858
859} /* PHY_RFShadowRecorverAll */
860
861
862extern void PHY_RFShadowCompareFlagSet(
863 struct net_device * dev,
864 RF90_RADIO_PATH_E eRFPath,
865 u32 Offset,
866 u8 Type)
867{
868 // Set True or False!!!
869 RF_Shadow[eRFPath][Offset].Compare = Type;
870
871} /* PHY_RFShadowCompareFlagSet */
872
873
874extern void PHY_RFShadowRecorverFlagSet(
875 struct net_device * dev,
876 RF90_RADIO_PATH_E eRFPath,
877 u32 Offset,
878 u8 Type)
879{
880 // Set True or False!!!
881 RF_Shadow[eRFPath][Offset].Recorver= Type;
882
883} /* PHY_RFShadowRecorverFlagSet */
884
885
886extern void PHY_RFShadowCompareFlagSetAll(struct net_device * dev)
887{
888 u32 eRFPath;
889 u32 Offset;
890
891 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
892 {
893 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
894 {
895 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
896 if (Offset != 0x26 && Offset != 0x27)
897 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
898 else
899 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
900 }
901 }
902
903} /* PHY_RFShadowCompareFlagSetAll */
904
905
906extern void PHY_RFShadowRecorverFlagSetAll(struct net_device * dev)
907{
908 u32 eRFPath;
909 u32 Offset;
910
911 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
912 {
913 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
914 {
915 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
916 if (Offset != 0x26 && Offset != 0x27)
917 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
918 else
919 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
920 }
921 }
922
923} /* PHY_RFShadowCompareFlagSetAll */
924
925
926
927extern void PHY_RFShadowRefresh(struct net_device * dev)
928{
929 u32 eRFPath;
930 u32 Offset;
931
932 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
933 {
934 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
935 {
936 RF_Shadow[eRFPath][Offset].Value = 0;
937 RF_Shadow[eRFPath][Offset].Compare = false;
938 RF_Shadow[eRFPath][Offset].Recorver = false;
939 RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
940 RF_Shadow[eRFPath][Offset].Driver_Write = false;
941 }
942 }
943
944} /* PHY_RFShadowRead */
945
946/* End of HalRf6052.c */
diff --git a/drivers/staging/rtl8192su/r8192S_rtl6052.h b/drivers/staging/rtl8192su/r8192S_rtl6052.h
new file mode 100644
index 00000000000..916603ceaae
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_rtl6052.h
@@ -0,0 +1,134 @@
1/******************************************************************************
2 *
3 * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4 *
5 * Module: HalRf.h ( Header File)
6 *
7 * Note: Collect every HAL RF type exter API or constant.
8 *
9 * Function:
10 *
11 * Export:
12 *
13 * Abbrev:
14 *
15 * History:
16 * Data Who Remark
17 *
18 * 09/25/2008 MHC Create initial version.
19 *
20 *
21******************************************************************************/
22/* Check to see if the file has been included already. */
23
24
25/*--------------------------Define Parameters-------------------------------*/
26
27//
28// For RF 6052 Series
29//
30#define RF6052_MAX_TX_PWR 0x3F
31#define RF6052_MAX_REG 0x3F
32#define RF6052_MAX_PATH 4
33/*--------------------------Define Parameters-------------------------------*/
34
35
36/*------------------------------Define structure----------------------------*/
37
38/*------------------------------Define structure----------------------------*/
39
40
41/*------------------------Export global variable----------------------------*/
42/*------------------------Export global variable----------------------------*/
43
44/*------------------------Export Marco Definition---------------------------*/
45
46/*------------------------Export Marco Definition---------------------------*/
47
48
49/*--------------------------Exported Function prototype---------------------*/
50//======================================================
51#if 1
52// Function prototypes for HalPhy8225.c
53//1======================================================
54extern void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); //20M or 40M;
55extern void PHY_SetRF8225Bandwidth( struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
56extern bool PHY_RF8225_Config(struct net_device* dev );
57extern void phy_RF8225_Config_HardCode(struct net_device* dev);
58extern bool phy_RF8225_Config_ParaFile(struct net_device* dev);
59extern void PHY_SetRF8225CckTxPower(struct net_device* dev ,u8 powerlevel);
60extern void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel);
61extern void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel);
62extern void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel);
63
64//1======================================================
65// Function prototypes for HalPhy8256.c
66//1======================================================
67extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
68extern void PHY_RF8256_Config(struct net_device* dev);
69extern void phy_RF8256_Config_ParaFile(struct net_device* dev);
70extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel);
71extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel);
72#endif
73
74//
75// RF RL6052 Series API
76//
77extern void RF_ChangeTxPath(struct net_device * dev, u16 DataRate);
78extern void PHY_RF6052SetBandwidth(struct net_device * dev,HT_CHANNEL_WIDTH Bandwidth);
79extern void PHY_RF6052SetCckTxPower(struct net_device * dev, u8 powerlevel);
80extern void PHY_RF6052SetOFDMTxPower(struct net_device * dev, u8 powerlevel);
81extern RT_STATUS PHY_RF6052_Config(struct net_device * dev);
82extern void PHY_RFShadowRefresh( struct net_device * dev);
83extern void PHY_RFShadowWrite( struct net_device* dev, u32 eRFPath, u32 Offset, u32 Data);
84#if 0
85//
86// RF Shadow operation relative API
87//
88extern u32
89PHY_RFShadowRead(
90 struct net_device * dev,
91 RF90_RADIO_PATH_E eRFPath,
92 u32 Offset);
93extern void
94PHY_RFShadowCompare(
95 struct net_device * dev,
96 RF90_RADIO_PATH_E eRFPath,
97 u32 Offset);
98extern void
99PHY_RFShadowRecorver(
100 struct net_device * dev,
101 RF90_RADIO_PATH_E eRFPath,
102 u32 Offset);
103extern void
104PHY_RFShadowCompareAll(
105 struct net_device * dev);
106extern void
107PHY_RFShadowRecorverAll(
108 struct net_device * dev);
109extern void
110PHY_RFShadowCompareFlagSet(
111 struct net_device * dev,
112 RF90_RADIO_PATH_E eRFPath,
113 u32 Offset,
114 u8 Type);
115extern void
116PHY_RFShadowRecorverFlagSet(
117 struct net_device * dev,
118 RF90_RADIO_PATH_E eRFPath,
119 u32 Offset,
120 u8 Type);
121extern void
122PHY_RFShadowCompareFlagSetAll(
123 struct net_device * dev);
124extern void
125PHY_RFShadowRecorverFlagSetAll(
126 struct net_device * dev);
127extern void
128PHY_RFShadowRefresh(
129 struct net_device * dev);
130#endif
131/*--------------------------Exported Function prototype---------------------*/
132
133
134/* End of HalRf.h */
diff --git a/drivers/staging/rtl8192su/r8192S_rtl8225.c b/drivers/staging/rtl8192su/r8192S_rtl8225.c
new file mode 100644
index 00000000000..09465df2def
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_rtl8225.c
@@ -0,0 +1,292 @@
1
2#include "r8192U.h"
3#include "r8192S_hw.h"
4#include "r8192S_phyreg.h"
5#include "r8192S_phy.h"
6#include "r8192S_rtl8225.h"
7
8/*---------------------Define local function prototype-----------------------*/
9void phy_RF8225_Config_HardCode(struct net_device* dev );
10bool phy_RF8225_Config_ParaFile(struct net_device* dev );
11/*---------------------Define local function prototype-----------------------*/
12void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel)
13{
14
15}
16
17
18
19void PHY_SetRF8225CckTxPower( struct net_device* dev , u8 powerlevel)
20{
21
22}
23
24
25// TODO: The following RF 022D related function should be removed to HalPhy0222D.c.
26void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel)
27{
28 //TODO: We should set RF TxPower for RF 0222D here!!
29}
30
31
32
33void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel)
34{
35 //TODO: We should set RF TxPower for RF 0222D here!!
36}
37
38
39/*-----------------------------------------------------------------------------
40 * Function: PHY_SetRF0222DBandwidth()
41 *
42 * Overview: This function is called by SetBWModeCallback8190Pci() only
43 *
44 * Input: PADAPTER Adapter
45 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
46 *
47 * Output: NONE
48 *
49 * Return: NONE
50 *
51 * Note: For RF type 0222D
52 *---------------------------------------------------------------------------*/
53 //just in phy
54void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
55{
56 u8 eRFPath;
57 struct r8192_priv *priv = ieee80211_priv(dev);
58
59
60 //if (IS_HARDWARE_TYPE_8192S(dev))
61 if (1)
62 {
63#ifndef RTL92SE_FPGA_VERIFY
64 switch(Bandwidth)
65 {
66 case HT_CHANNEL_WIDTH_20:
67#ifdef FIB_MODIFICATION
68 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
69#endif
70 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
71 break;
72 case HT_CHANNEL_WIDTH_20_40:
73#ifdef FIB_MODIFICATION
74 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
75#endif
76 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
77 break;
78 default:
79 ;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
80 break;
81 }
82#endif
83 }
84 else
85 {
86 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
87 {
88 switch(Bandwidth)
89 {
90 case HT_CHANNEL_WIDTH_20:
91 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
92 break;
93 case HT_CHANNEL_WIDTH_20_40:
94 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
95 break;
96 default:
97 ;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
98 break;
99
100 }
101 }
102 }
103
104}
105
106// TODO: Aabove RF 022D related function should be removed to HalPhy0222D.c.
107
108/*-----------------------------------------------------------------------------
109 * Function: PHY_SetRF8225Bandwidth()
110 *
111 * Overview: This function is called by SetBWModeCallback8190Pci() only
112 *
113 * Input: PADAPTER Adapter
114 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
115 *
116 * Output: NONE
117 *
118 * Return: NONE
119 *
120 * Note: 8225(zebra1) support 20M only
121 *---------------------------------------------------------------------------*/
122 //just in phy
123void PHY_SetRF8225Bandwidth(struct net_device* dev ,HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
124{
125 u8 eRFPath;
126 struct r8192_priv *priv = ieee80211_priv(dev);
127
128 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
129 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
130 {
131 switch(Bandwidth)
132 {
133 case HT_CHANNEL_WIDTH_20:
134 // TODO: Update the parameters here
135 break;
136 case HT_CHANNEL_WIDTH_20_40:
137 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():8225 does not support 40M mode\n");
138 break;
139 default:
140 RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
141 break;
142
143 }
144 }
145
146}
147
148//just in phy
149bool PHY_RF8225_Config(struct net_device* dev )
150{
151 struct r8192_priv *priv = ieee80211_priv(dev);
152 bool rtStatus = true;
153 //RF90_RADIO_PATH_E eRFPath;
154 //BB_REGISTER_DEFINITION_T *pPhyReg;
155 //u32 OrgStoreRFIntSW[RF90_PATH_D+1];
156
157 //
158 // Initialize general global value
159 //
160 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
161 priv->NumTotalRFPath = 2;
162
163 //
164 // Config BB and RF
165 //
166 //switch( Adapter->MgntInfo.bRegHwParaFile )
167 //{
168 // case 0:
169 // phy_RF8225_Config_HardCode(dev);
170 // break;
171
172 // case 1:
173 // rtStatus = phy_RF8225_Config_ParaFile(dev);
174 // break;
175
176 // case 2:
177 // Partial Modify.
178 phy_RF8225_Config_HardCode(dev);
179 phy_RF8225_Config_ParaFile(dev);
180 // break;
181
182 // default:
183 // phy_RF8225_Config_HardCode(dev);
184 // break;
185 //}
186 return rtStatus;
187
188}
189
190//just in 8225
191void phy_RF8225_Config_HardCode(struct net_device* dev)
192{
193
194 // Set Default Bandwidth to 20M
195 //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
196
197 // TODO: Set Default Channel to channel one for RTL8225
198
199}
200
201//just in 8225
202bool phy_RF8225_Config_ParaFile(struct net_device* dev)
203{
204 u32 u4RegValue = 0;
205 //static char szRadioAFile[] = RTL819X_PHY_RADIO_A;
206 //static char szRadioBFile[] = RTL819X_PHY_RADIO_B;
207 u8 eRFPath;
208 bool rtStatus = true;
209 struct r8192_priv *priv = ieee80211_priv(dev);
210 BB_REGISTER_DEFINITION_T *pPhyReg;
211 //u8 eCheckItem;
212
213#if 1
214 //3//-----------------------------------------------------------------
215 //3// <2> Initialize RF
216 //3//-----------------------------------------------------------------
217 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
218 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
219 {
220
221 pPhyReg = &priv->PHYRegDef[eRFPath];
222
223 /*----Store original RFENV control type----*/
224 switch(eRFPath)
225 {
226 case RF90_PATH_A:
227 case RF90_PATH_C:
228 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
229 break;
230 case RF90_PATH_B :
231 case RF90_PATH_D:
232 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
233 break;
234 }
235
236 /*----Set RF_ENV enable----*/
237 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
238
239 /*----Set RF_ENV output high----*/
240 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
241
242 /* Set bit number of Address and Data for RF register */
243 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
244 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
245
246
247 /*----Initialize RF fom connfiguration file----*/
248 switch(eRFPath)
249 {
250 case RF90_PATH_A:
251 //rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
252 rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
253 break;
254 case RF90_PATH_B:
255 //rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
256 rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
257 break;
258 case RF90_PATH_C:
259 break;
260 case RF90_PATH_D:
261 break;
262 }
263
264 /*----Restore RFENV control type----*/;
265 switch(eRFPath)
266 {
267 case RF90_PATH_A:
268 case RF90_PATH_C:
269 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
270 break;
271 case RF90_PATH_B :
272 case RF90_PATH_D:
273 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
274 break;
275 }
276
277 if(rtStatus == false){
278 //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF8225_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
279 goto phy_RF8225_Config_ParaFile_Fail;
280 }
281
282 }
283
284 //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF8225_Config_ParaFile()\n"));
285 return rtStatus;
286
287phy_RF8225_Config_ParaFile_Fail:
288#endif
289 return rtStatus;
290}
291
292
diff --git a/drivers/staging/rtl8192su/r8192S_rtl8225.h b/drivers/staging/rtl8192su/r8192S_rtl8225.h
new file mode 100644
index 00000000000..8a647284af3
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192S_rtl8225.h
@@ -0,0 +1,30 @@
1/*
2 This is part of the rtl8180-sa2400 driver
3 released under the GPL (See file COPYING for details).
4 Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
5
6 This files contains programming code for the rtl8256
7 radio frontend.
8
9 *Many* thanks to Realtek Corp. for their great support!
10
11*/
12
13#ifndef RTL8225H
14#define RTL8225H
15
16#ifdef RTL8190P
17#define RTL819X_TOTAL_RF_PATH 4 //for 90P
18#else
19#define RTL819X_TOTAL_RF_PATH 2 //for 8192U
20#endif
21extern void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); //20M or 40M;
22extern void PHY_SetRF8225Bandwidth( struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
23extern bool PHY_RF8225_Config(struct net_device* dev );
24extern void phy_RF8225_Config_HardCode(struct net_device* dev);
25extern bool phy_RF8225_Config_ParaFile(struct net_device* dev);
26extern void PHY_SetRF8225CckTxPower(struct net_device* dev ,u8 powerlevel);
27extern void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel);
28extern void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel);
29extern void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel);
30#endif
diff --git a/drivers/staging/rtl8192su/r8192U.h b/drivers/staging/rtl8192su/r8192U.h
new file mode 100644
index 00000000000..a2365587b1c
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U.h
@@ -0,0 +1,2112 @@
1/*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16*/
17
18#ifndef R819xU_H
19#define R819xU_H
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23//#include <linux/config.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/sched.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/netdevice.h>
30//#include <linux/pci.h>
31#include <linux/usb.h>
32#include <linux/etherdevice.h>
33#include <linux/delay.h>
34#include <linux/rtnetlink.h> //for rtnl_lock()
35#include <linux/wireless.h>
36#include <linux/timer.h>
37#include <linux/proc_fs.h> // Necessary because we use the proc fs
38#include <linux/if_arp.h>
39#include <linux/random.h>
40#include <linux/version.h>
41#include <asm/io.h>
42#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
43#include <asm/semaphore.h>
44#endif
45#include "ieee80211.h"
46
47#ifdef RTL8192SU
48#include "r8192S_firmware.h"
49#else
50#include "r819xU_firmware.h"
51#endif
52
53//#define RTL8192U
54#define RTL819xU_MODULE_NAME "rtl819xU"
55//added for HW security, john.0629
56#define FALSE 0
57#define TRUE 1
58#define MAX_KEY_LEN 61
59#define KEY_BUF_SIZE 5
60
61#define BIT0 0x00000001
62#define BIT1 0x00000002
63#define BIT2 0x00000004
64#define BIT3 0x00000008
65#define BIT4 0x00000010
66#define BIT5 0x00000020
67#define BIT6 0x00000040
68#define BIT7 0x00000080
69#define BIT8 0x00000100
70#define BIT9 0x00000200
71#define BIT10 0x00000400
72#define BIT11 0x00000800
73#define BIT12 0x00001000
74#define BIT13 0x00002000
75#define BIT14 0x00004000
76#define BIT15 0x00008000
77#define BIT16 0x00010000
78#define BIT17 0x00020000
79#define BIT18 0x00040000
80#define BIT19 0x00080000
81#define BIT20 0x00100000
82#define BIT21 0x00200000
83#define BIT22 0x00400000
84#define BIT23 0x00800000
85#define BIT24 0x01000000
86#define BIT25 0x02000000
87#define BIT26 0x04000000
88#define BIT27 0x08000000
89#define BIT28 0x10000000
90#define BIT29 0x20000000
91#define BIT30 0x40000000
92#define BIT31 0x80000000
93
94// Rx smooth factor
95#define Rx_Smooth_Factor 20
96#if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
97#define DMESG(x,a...) printk(KERN_INFO RTL819xU_MODULE_NAME ": " x "\n", ## a)
98#define DMESGW(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": WW:" x "\n", ## a)
99#define DMESGE(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": EE:" x "\n", ## a)
100#else
101#define DMESG(x,a...)
102#define DMESGW(x,a...)
103#define DMESGE(x,a...)
104extern u32 rt_global_debug_component;
105#define RT_TRACE(component, x, args...) \
106do { if(rt_global_debug_component & component) \
107 printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
108 ##args);\
109}while(0);
110//----------------------------------------------------------------------
111//// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15.
112////----------------------------------------------------------------------
113#define RX_DESC_SIZE 24
114#define RX_DRV_INFO_SIZE_UNIT 8
115
116#define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
117 (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
118
119#define COMP_TRACE BIT0 // For function call tracing.
120#define COMP_DBG BIT1 // Only for temporary debug message.
121#define COMP_INIT BIT2 // during driver initialization / halt / reset.
122
123
124#define COMP_RECV BIT3 // Reveive part data path.
125#define COMP_SEND BIT4 // Send part path.
126#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
127#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
128#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
129#define COMP_SWBW BIT8 // For bandwidth switch.
130#define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
131#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
132#define COMP_QOS BIT11 // For QoS.
133#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
134#define COMP_LPS BIT13 // For Radio Measurement.
135#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
136#define COMP_PHY BIT15
137#define COMP_CH BIT16 //channel setting debug
138#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
139#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
140#define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
141#define COMP_SEC BIT20 // Event handling
142#define COMP_LED BIT21 // For LED.
143#define COMP_RF BIT22 // For RF.
144//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
145#define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
146//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
147//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
148
149#define COMP_FIRMWARE BIT24 //for firmware downloading
150#define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
151#define COMP_AMSDU BIT26 // For A-MSDU Debugging
152
153#define COMP_SCAN BIT27
154#define COMP_CMD BIT28
155#define COMP_DOWN BIT29 //for rm driver module
156#define COMP_RESET BIT30 //for silent reset
157#define COMP_ERR BIT31 //for error out, always on
158#endif
159
160#define RTL819x_DEBUG
161#ifdef RTL819x_DEBUG
162#define assert(expr) \
163 if (!(expr)) { \
164 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
165 #expr,__FILE__,__FUNCTION__,__LINE__); \
166 }
167//wb added to debug out data buf
168//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
169#define RT_DEBUG_DATA(level, data, datalen) \
170 do{ if ((rt_global_debug_component & (level)) == (level)) \
171 { \
172 int i; \
173 u8* pdata = (u8*) data; \
174 printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
175 for(i=0; i<(int)(datalen); i++) \
176 { \
177 printk("%2x ", pdata[i]); \
178 if ((i+1)%16 == 0) printk("\n"); \
179 } \
180 printk("\n"); \
181 } \
182 } while (0)
183#else
184#define assert(expr) do {} while (0)
185#define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
186#endif /* RTL8169_DEBUG */
187
188//#ifdef RTL8192SU
189 //2TODO: We should define 8192S firmware related macro settings here!!
190 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
191 #define RTL819X_TOTAL_RF_PATH 2
192
193 //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray
194 //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray
195 //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray
196
197 #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
198 #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
199 #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray
200 #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
201 //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array
202 //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array
203 #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array
204 #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array
205
206 //2008.11.06 Add.
207 #define Rtl819XFwImageArray Rtl8192SUFwImgArray
208 #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array
209 #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array
210 #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray
211 #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray
212 #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray
213 #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray
214 #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG
215 #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array
216 #define Rtl819XRadioB_Array Rtl8192SURadioB_Array
217 #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array
218 #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array
219 #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array
220//#endif
221
222//
223// Queue Select Value in TxDesc
224//
225#define QSLT_BK 0x1
226#define QSLT_BE 0x0
227#define QSLT_VI 0x4
228#define QSLT_VO 0x6
229#define QSLT_BEACON 0x10
230#define QSLT_HIGH 0x11
231#define QSLT_MGNT 0x12
232#define QSLT_CMD 0x13
233
234#define DESC90_RATE1M 0x00
235#define DESC90_RATE2M 0x01
236#define DESC90_RATE5_5M 0x02
237#define DESC90_RATE11M 0x03
238#define DESC90_RATE6M 0x04
239#define DESC90_RATE9M 0x05
240#define DESC90_RATE12M 0x06
241#define DESC90_RATE18M 0x07
242#define DESC90_RATE24M 0x08
243#define DESC90_RATE36M 0x09
244#define DESC90_RATE48M 0x0a
245#define DESC90_RATE54M 0x0b
246#define DESC90_RATEMCS0 0x00
247#define DESC90_RATEMCS1 0x01
248#define DESC90_RATEMCS2 0x02
249#define DESC90_RATEMCS3 0x03
250#define DESC90_RATEMCS4 0x04
251#define DESC90_RATEMCS5 0x05
252#define DESC90_RATEMCS6 0x06
253#define DESC90_RATEMCS7 0x07
254#define DESC90_RATEMCS8 0x08
255#define DESC90_RATEMCS9 0x09
256#define DESC90_RATEMCS10 0x0a
257#define DESC90_RATEMCS11 0x0b
258#define DESC90_RATEMCS12 0x0c
259#define DESC90_RATEMCS13 0x0d
260#define DESC90_RATEMCS14 0x0e
261#define DESC90_RATEMCS15 0x0f
262#define DESC90_RATEMCS32 0x20
263
264//#ifdef RTL8192SU
265// CCK Rates, TxHT = 0
266#define DESC92S_RATE1M 0x00
267#define DESC92S_RATE2M 0x01
268#define DESC92S_RATE5_5M 0x02
269#define DESC92S_RATE11M 0x03
270
271// OFDM Rates, TxHT = 0
272#define DESC92S_RATE6M 0x04
273#define DESC92S_RATE9M 0x05
274#define DESC92S_RATE12M 0x06
275#define DESC92S_RATE18M 0x07
276#define DESC92S_RATE24M 0x08
277#define DESC92S_RATE36M 0x09
278#define DESC92S_RATE48M 0x0a
279#define DESC92S_RATE54M 0x0b
280
281// MCS Rates, TxHT = 1
282#define DESC92S_RATEMCS0 0x0c
283#define DESC92S_RATEMCS1 0x0d
284#define DESC92S_RATEMCS2 0x0e
285#define DESC92S_RATEMCS3 0x0f
286#define DESC92S_RATEMCS4 0x10
287#define DESC92S_RATEMCS5 0x11
288#define DESC92S_RATEMCS6 0x12
289#define DESC92S_RATEMCS7 0x13
290#define DESC92S_RATEMCS8 0x14
291#define DESC92S_RATEMCS9 0x15
292#define DESC92S_RATEMCS10 0x16
293#define DESC92S_RATEMCS11 0x17
294#define DESC92S_RATEMCS12 0x18
295#define DESC92S_RATEMCS13 0x19
296#define DESC92S_RATEMCS14 0x1a
297#define DESC92S_RATEMCS15 0x1b
298#define DESC92S_RATEMCS15_SG 0x1c
299#define DESC92S_RATEMCS32 0x20
300//#endif
301
302#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
303
304#define IEEE80211_WATCH_DOG_TIME 2000
305#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
306//for txpowertracking by amy
307#define OFDM_Table_Length 19
308#define CCK_Table_length 12
309
310#ifdef RTL8192SU
311//
312//Tx Descriptor for RLT8192SU(Normal mode)
313//
314typedef struct _tx_desc_819x_usb {
315 // DWORD 0
316 u16 PktSize;//:16;
317 u8 Offset;//:8;
318 u8 Type:2; // Reserved for MAC header Frame Type subfield.
319 u8 LastSeg:1;
320 u8 FirstSeg:1;
321 u8 LINIP:1;
322 u8 AMSDU:1;
323 u8 GF:1;
324 u8 OWN:1;
325
326 // DWORD 1
327 u8 MacID:5;
328 u8 MoreData:1;
329 u8 MOREFRAG:1;
330 u8 PIFS:1;
331 u8 QueueSelect:5;
332 u8 AckPolicy:2;
333 u8 NoACM:1;
334 u8 NonQos:1;
335 u8 KeyID:2;
336 u8 OUI:1;
337 u8 PktType:1;
338 u8 EnDescID:1;
339 u8 SecType:2;
340 u8 HTC:1; //padding0
341 u8 WDS:1; //padding1
342 u8 PktOffset:5; //padding_len (hw)
343 u8 HWPC:1;
344
345 // DWORD 2
346 u32 DataRetryLmt:6;
347 u32 RetryLmtEn:1;
348 u32 TSFL:5;
349 u32 RTSRC:6; // Reserved for HW RTS Retry Count.
350 u32 DATARC:6; // Reserved for HW DATA Retry Count.
351 u32 Rsvd1:5;
352 u32 AllowAggregation:1;
353 u32 BK:1; //Aggregation break.
354 u32 OwnMAC:1;
355
356 // DWORD 3
357 u8 NextHeadPage;//:8;
358 u8 TailPage;//:8;
359 u16 Seq:12;
360 u16 Frag:4;
361
362 // DWORD 4
363 u32 RTSRate:6;
364 u32 DisRTSFB:1;
365 u32 RTSRateFBLmt:4;
366 u32 CTS2Self:1;
367 u32 RTSEn:1;
368 u32 RaBRSRID:3; //Rate adaptive BRSR ID.
369 u32 TxHT:1;
370 u32 TxShort:1;//for data
371 u32 TxBandwidth:1;
372 u32 TxSubCarrier:2;
373 u32 STBC:2;
374 u32 RD:1;
375 u32 RTSHT:1;
376 u32 RTSShort:1;
377 u32 RTSBW:1;
378 u32 RTSSubcarrier:2;
379 u32 RTSSTBC:2;
380 u32 USERATE:1;
381 // DWORD 5
382 u32 PktID:9;
383 u32 TxRate:6;
384 u32 DISFB:1;
385 u32 DataRateFBLmt:5;
386 u32 TxAGC:11;
387
388 // DWORD 6
389 u16 IPChkSum;//:16;
390 u16 TCPChkSum;//:16;
391
392 // DWORD 7
393 //u16 TxBuffSize;//:16;//pcie
394 u16 TxBufferSize;
395 u16 IPHdrOffset:8;
396 u16 Rsvd2:7;
397 u16 TCPEn:1;
398}tx_desc_819x_usb, *ptx_desc_819x_usb;
399typedef struct _tx_status_desc_8192s_usb{
400
401 //DWORD 0
402 u8 TxRate:6;
403 u8 Rsvd1:1;
404 u8 BandWidth:1;
405 u8 RTSRate:6;
406 u8 AGGLS:1;
407 u8 AGG:1;
408 u8 RTSRC:6;
409 u8 DataRC:6;
410 u8 FailCause:2;
411 u8 TxOK:1;
412 u8 Own:1;
413
414 //DWORD 1
415 u16 Seq:12;
416 u8 QueueSel:5;
417 u8 MACID:5;
418 u8 PwrMgt:1;
419 u8 MoreData:1;
420 u8 Rsvd2;
421
422 //DWORD 2
423 u8 RxAGC1;
424 u8 RxAGC2;
425 u8 RxAGC3;
426 u8 RxAGC4;
427}tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
428#else
429/* for rtl819x */
430typedef struct _tx_desc_819x_usb {
431 //DWORD 0
432 u16 PktSize;
433 u8 Offset;
434 u8 Reserved0:3;
435 u8 CmdInit:1;
436 u8 LastSeg:1;
437 u8 FirstSeg:1;
438 u8 LINIP:1;
439 u8 OWN:1;
440
441 //DWORD 1
442 u8 TxFWInfoSize;
443 u8 RATid:3;
444 u8 DISFB:1;
445 u8 USERATE:1;
446 u8 MOREFRAG:1;
447 u8 NoEnc:1;
448 u8 PIFS:1;
449 u8 QueueSelect:5;
450 u8 NoACM:1;
451 u8 Reserved1:2;
452 u8 SecCAMID:5;
453 u8 SecDescAssign:1;
454 u8 SecType:2;
455
456 //DWORD 2
457 u16 TxBufferSize;
458 //u16 Reserved2;
459 u8 ResvForPaddingLen:7;
460 u8 Reserved3:1;
461 u8 Reserved4;
462
463 //DWORD 3, 4, 5
464 u32 Reserved5;
465 u32 Reserved6;
466 u32 Reserved7;
467}tx_desc_819x_usb, *ptx_desc_819x_usb;
468#endif
469
470#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
471typedef struct _tx_desc_819x_usb_aggr_subframe {
472 //DWORD 0
473 u16 PktSize;
474 u8 Offset;
475 u8 TxFWInfoSize;
476
477 //DWORD 1
478 u8 RATid:3;
479 u8 DISFB:1;
480 u8 USERATE:1;
481 u8 MOREFRAG:1;
482 u8 NoEnc:1;
483 u8 PIFS:1;
484 u8 QueueSelect:5;
485 u8 NoACM:1;
486 u8 Reserved1:2;
487 u8 SecCAMID:5;
488 u8 SecDescAssign:1;
489 u8 SecType:2;
490 u8 PacketID:7;
491 u8 OWN:1;
492}tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
493#endif
494
495
496#ifdef RTL8192SU
497//
498//Tx Descriptor for RLT8192SU(Load FW mode)
499//
500typedef struct _tx_desc_cmd_819x_usb{
501 // DWORD 0
502 u16 PktSize;
503 u8 Offset;
504 u8 Rsvd0:4;
505 u8 LINIP:1;
506 u8 Rsvd1:2;
507 u8 OWN:1;
508
509 // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
510 u32 Rsvd2;
511 u32 Rsvd3;
512 u32 Rsvd4;
513 u32 Rsvd5;
514 u32 Rsvd6;
515 u32 Rsvd7;
516
517 // DWORD 7
518 u16 TxBuffSize;//pcie
519 u16 Rsvd8;
520}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
521//
522//H2C Command for RLT8192SU(Host TxCmd)
523//
524typedef struct _tx_h2c_desc_cmd_8192s_usb{
525 // DWORD 0
526 u32 PktSize:16;
527 u32 Offset:8;
528 u32 Rsvd0:7;
529 u32 OWN:1;
530
531 // DWORD 1
532 u32 Rsvd1:8;
533 u32 QSEL:5;
534 u32 Rsvd2:19;
535
536 // DWORD 2
537 u32 Rsvd3;
538
539 // DWORD 3
540 u32 NextHeadPage:8;
541 u32 TailPage:8;
542 u32 Rsvd4:16;
543
544 // DWORD 4, 5, 6, 7
545 u32 Rsvd5;
546 u32 Rsvd6;
547 u32 Rsvd7;
548 u32 Rsvd8;
549}tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
550
551
552typedef struct _tx_h2c_cmd_hdr_8192s_usb{
553 // DWORD 0
554 u32 CmdLen:16;
555 u32 ElementID:8;
556 u32 CmdSeq:8;
557
558 // DWORD 1
559 u32 Rsvd0;
560}tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
561#else
562typedef struct _tx_desc_cmd_819x_usb {
563 //DWORD 0
564 u16 Reserved0;
565 u8 Reserved1;
566 u8 Reserved2:3;
567 u8 CmdInit:1;
568 u8 LastSeg:1;
569 u8 FirstSeg:1;
570 u8 LINIP:1;
571 u8 OWN:1;
572
573 //DOWRD 1
574 //u32 Reserved3;
575 u8 TxFWInfoSize;
576 u8 Reserved3;
577 u8 QueueSelect;
578 u8 Reserved4;
579
580 //DOWRD 2
581 u16 TxBufferSize;
582 u16 Reserved5;
583
584 //DWORD 3,4,5
585 //u32 TxBufferAddr;
586 //u32 NextDescAddress;
587 u32 Reserved6;
588 u32 Reserved7;
589 u32 Reserved8;
590}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
591#endif
592
593#ifdef RTL8192SU
594typedef struct _tx_fwinfo_819x_usb{
595 //DWORD 0
596 u8 TxRate:7;
597 u8 CtsEnable:1;
598 u8 RtsRate:7;
599 u8 RtsEnable:1;
600 u8 TxHT:1;
601 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
602 u8 TxBandwidth:1; // This is used for HT MCS rate only.
603 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
604 u8 STBC:2;
605 u8 AllowAggregation:1;
606 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
607 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
608 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
609 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
610 u8 RtsSTBC:2;
611 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
612
613 //DWORD 1
614 u32 RxMF:2;
615 u32 RxAMD:3;
616 u32 Reserved1:3;
617 u32 TxAGCOffSet:4;//TxAGCOffset:4;
618 u32 TxAGCSign:1;
619 u32 Tx_INFO_RSVD:6;
620 u32 PacketID:13;
621}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
622#else
623typedef struct _tx_fwinfo_819x_usb {
624 //DOWRD 0
625 u8 TxRate:7;
626 u8 CtsEnable:1;
627 u8 RtsRate:7;
628 u8 RtsEnable:1;
629 u8 TxHT:1;
630 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
631 u8 TxBandwidth:1; // This is used for HT MCS rate only.
632 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
633 u8 STBC:2;
634 u8 AllowAggregation:1;
635 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
636 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
637 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
638 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
639 u8 RtsSTBC:2;
640 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
641
642 //DWORD 1
643 u32 RxMF:2;
644 u32 RxAMD:3;
645 u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
646 u32 Reserved1:2;
647 u32 TxAGCOffSet:4;
648 u32 TxAGCSign:1;
649 u32 Tx_INFO_RSVD:6;
650 u32 PacketID:13;
651 //u32 Reserved;
652}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
653#endif
654
655typedef struct rtl8192_rx_info {
656 struct urb *urb;
657 struct net_device *dev;
658 u8 out_pipe;
659}rtl8192_rx_info ;
660
661#ifdef RTL8192SU
662//typedef struct _RX_DESC_STATUS_8192SU{
663typedef struct rx_desc_819x_usb{
664 //DWORD 0
665 u16 Length:14;
666 u16 CRC32:1;
667 u16 ICV:1;
668 u8 RxDrvInfoSize:4;
669 u8 Security:3;
670 u8 Qos:1;
671 u8 Shift:2;
672 u8 PHYStatus:1;
673 u8 SWDec:1;
674 u8 LastSeg:1;
675 u8 FirstSeg:1;
676 u8 EOR:1;
677 u8 Own:1;
678
679 //DWORD 1
680 u16 MACID:5;
681 u16 TID:4;
682 u16 HwRsvd:5;
683 u16 PAGGR:1;
684 u16 FAGGR:1;
685 u8 A1_FIT:4;
686 u8 A2_FIT:4;
687 u8 PAM:1;
688 u8 PWR:1;
689 u8 MoreData:1;
690 u8 MoreFrag:1;
691 u8 Type:2;
692 u8 MC:1;
693 u8 BC:1;
694
695 //DWORD 2
696 u16 Seq:12;
697 u16 Frag:4;
698#ifdef USB_RX_AGGREGATION_SUPPORT
699 u8 UsbAggPktNum;//:8;
700#else
701 u8 NextPktLen;//:8;
702#endif
703 u8 Rsvd0:6;
704 u8 NextIND:1;
705 u8 Rsvd1:1;
706
707 //DWORD 3
708 u8 RxMCS:6;
709 u8 RxHT:1;
710 u8 AMSDU:1;
711 u8 SPLCP:1;
712 u8 BW:1;
713 u8 HTC:1;
714 u8 TCPChkRpt:1;
715 u8 IPChkRpt:1;
716 u8 TCPChkValID:1;
717 u8 HwPCErr:1;
718 u8 HwPCInd:1;
719 u16 IV0;//:16;
720
721 //DWORD 4
722 u32 IV1;
723
724 //DWORD 5
725 u32 TSFL;
726//}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
727}rx_desc_819x_usb, *prx_desc_819x_usb;
728#else
729typedef struct rx_desc_819x_usb{
730 //DOWRD 0
731 u16 Length:14;
732 u16 CRC32:1;
733 u16 ICV:1;
734 u8 RxDrvInfoSize;
735 u8 Shift:2;
736 u8 PHYStatus:1;
737 u8 SWDec:1;
738 //u8 LastSeg:1;
739 //u8 FirstSeg:1;
740 //u8 EOR:1;
741 //u8 OWN:1;
742 u8 Reserved1:4;
743
744 //DWORD 1
745 u32 Reserved2;
746
747 //DWORD 2
748 //u32 Reserved3;
749
750 //DWORD 3
751 //u32 BufferAddress;
752
753}rx_desc_819x_usb, *prx_desc_819x_usb;
754#endif
755
756#ifdef USB_RX_AGGREGATION_SUPPORT
757typedef struct _rx_desc_819x_usb_aggr_subframe{
758 //DOWRD 0
759 u16 Length:14;
760 u16 CRC32:1;
761 u16 ICV:1;
762 u8 Offset;
763 u8 RxDrvInfoSize;
764 //DOWRD 1
765 u8 Shift:2;
766 u8 PHYStatus:1;
767 u8 SWDec:1;
768 u8 Reserved1:4;
769 u8 Reserved2;
770 u16 Reserved3;
771 //DWORD 2
772 //u4Byte Reserved3;
773 //DWORD 3
774 //u4Byte BufferAddress;
775}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
776#endif
777
778#ifdef RTL8192SU
779//
780// Driver info are written to the begining of the RxBuffer
781//
782//typedef struct _RX_DRIVER_INFO_8192S{
783typedef struct rx_drvinfo_819x_usb{
784 //
785 // Driver info contain PHY status and other variabel size info
786 // PHY Status content as below
787 //
788
789 //DWORD 0
790 /*u4Byte gain_0:7;
791 u4Byte trsw_0:1;
792 u4Byte gain_1:7;
793 u4Byte trsw_1:1;
794 u4Byte gain_2:7;
795 u4Byte trsw_2:1;
796 u4Byte gain_3:7;
797 u4Byte trsw_3:1; */
798 u8 gain_trsw[4];
799
800 //DWORD 1
801 /*u4Byte pwdb_all:8;
802 u4Byte cfosho_0:8;
803 u4Byte cfosho_1:8;
804 u4Byte cfosho_2:8;*/
805 u8 pwdb_all;
806 u8 cfosho[4];
807
808 //DWORD 2
809 /*u4Byte cfosho_3:8;
810 u4Byte cfotail_0:8;
811 u4Byte cfotail_1:8;
812 u4Byte cfotail_2:8;*/
813 u8 cfotail[4];
814
815 //DWORD 3
816 /*u4Byte cfotail_3:8;
817 u4Byte rxevm_0:8;
818 u4Byte rxevm_1:8;
819 u4Byte rxsnr_0:8;*/
820 char rxevm[2];
821 char rxsnr[4];
822
823 //DWORD 4
824 /*u4Byte rxsnr_1:8;
825 u4Byte rxsnr_2:8;
826 u4Byte rxsnr_3:8;
827 u4Byte pdsnr_0:8;*/
828 u8 pdsnr[2];
829
830 //DWORD 5
831 /*u4Byte pdsnr_1:8;
832 u4Byte csi_current_0:8;
833 u4Byte csi_current_1:8;
834 u4Byte csi_target_0:8;*/
835 u8 csi_current[2];
836 u8 csi_target[2];
837
838 //DWORD 6
839 /*u4Byte csi_target_1:8;
840 u4Byte sigevm:8;
841 u4Byte max_ex_pwr:8;
842 u4Byte ex_intf_flag:1;
843 u4Byte sgi_en:1;
844 u4Byte rxsc:2;
845 u4Byte reserve:4;*/
846 u8 sigevm;
847 u8 max_ex_pwr;
848 u8 ex_intf_flag:1;
849 u8 sgi_en:1;
850 u8 rxsc:2;
851 u8 reserve:4;
852
853}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
854#else
855typedef struct rx_drvinfo_819x_usb{
856 //DWORD 0
857 u16 Reserved1:12;
858 u16 PartAggr:1;
859 u16 FirstAGGR:1;
860 u16 Reserved2:2;
861
862 u8 RxRate:7;
863 u8 RxHT:1;
864
865 u8 BW:1;
866 u8 SPLCP:1;
867 u8 Reserved3:2;
868 u8 PAM:1;
869 u8 Mcast:1;
870 u8 Bcast:1;
871 u8 Reserved4:1;
872
873 //DWORD 1
874 u32 TSFL;
875
876}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
877#endif
878
879 #define HWSET_MAX_SIZE_92S 128
880#ifdef RTL8192SU
881 #define MAX_802_11_HEADER_LENGTH 40
882 #define MAX_PKT_AGG_NUM 256
883 #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
884#else
885 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
886 #define MAX_PKT_AGG_NUM 64
887 #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
888#endif
889
890#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
891#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
892//#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
893#define ENCRYPTION_MAX_OVERHEAD 128
894#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
895//#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
896#define MAX_FRAGMENT_COUNT 8
897#ifdef RTL8192U
898#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
899#define MAX_TRANSMIT_BUFFER_SIZE 32000
900#else
901#define MAX_TRANSMIT_BUFFER_SIZE 8000
902#endif
903#else
904#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
905#endif
906#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
907#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
908#endif
909#define scrclng 4 // octets for crc32 (FCS, ICV)
910
911typedef enum rf_optype
912{
913 RF_OP_By_SW_3wire = 0,
914 RF_OP_By_FW,
915 RF_OP_MAX
916}rf_op_type;
917/* 8190 Loopback Mode definition */
918typedef enum _rtl819xUsb_loopback{
919 RTL819xU_NO_LOOPBACK = 0,
920 RTL819xU_MAC_LOOPBACK = 1,
921 RTL819xU_DMA_LOOPBACK = 2,
922 RTL819xU_CCK_LOOPBACK = 3,
923}rtl819xUsb_loopback_e;
924
925/* for rtl819x */
926typedef enum _RT_STATUS{
927 RT_STATUS_SUCCESS = 0,
928 RT_STATUS_FAILURE = 1,
929 RT_STATUS_PENDING = 2,
930 RT_STATUS_RESOURCE = 3
931}RT_STATUS,*PRT_STATUS;
932
933//#ifdef RTL8192SU
934typedef enum _RTL8192SUSB_LOOPBACK{
935 RTL8192SU_NO_LOOPBACK = 0,
936 RTL8192SU_MAC_LOOPBACK = 1,
937 RTL8192SU_DMA_LOOPBACK = 2,
938 RTL8192SU_CCK_LOOPBACK = 3,
939}RTL8192SUSB_LOOPBACK_E;
940//#endif
941
942
943#if 0
944/* due to rtl8192 firmware */
945typedef enum _desc_packet_type_e{
946 DESC_PACKET_TYPE_INIT = 0,
947 DESC_PACKET_TYPE_NORMAL = 1,
948}desc_packet_type_e;
949
950typedef enum _firmware_source{
951 FW_SOURCE_IMG_FILE = 0,
952 FW_SOURCE_HEADER_FILE = 1, //from header file
953}firmware_source_e, *pfirmware_source_e;
954
955typedef enum _firmware_status{
956 FW_STATUS_0_INIT = 0,
957 FW_STATUS_1_MOVE_BOOT_CODE = 1,
958 FW_STATUS_2_MOVE_MAIN_CODE = 2,
959 FW_STATUS_3_TURNON_CPU = 3,
960 FW_STATUS_4_MOVE_DATA_CODE = 4,
961 FW_STATUS_5_READY = 5,
962}firmware_status_e;
963
964typedef struct _rt_firmare_seg_container {
965 u16 seg_size;
966 u8 *seg_ptr;
967}fw_seg_container, *pfw_seg_container;
968
969#ifdef RTL8192SU
970//--------------------------------------------------------------------------------
971// 8192S Firmware related
972//--------------------------------------------------------------------------------
973typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
974
975 //--- LONG WORD 0 ----
976 u32 RegulatoryClass;
977 u32 Rfintfs;
978
979 //--- LONG WORD 1 ----
980 u32 ChipVer;
981 u32 HCISel;
982
983 //--- LONG WORD 2 ----
984 u32 IBKMode;
985 u32 Rsvd00;
986
987 //--- LONG WORD 3 ----
988 u32 Rsvd01;
989 u8 Qos_En; // QoS enable
990 u8 En40MHz; // 40MHz BW enable
991 u8 AMSDU2AMPDU_En; //14181 convert AMSDU to AMPDU, 0: disable
992 u8 AMPDU_En; //111n AMPDU/AMSDU enable
993
994 //--- LONG WORD 4 ----
995 u8 rate_control_offload;//FW offloads, 0: driver handles
996 u8 aggregation_offload; // FW offloads, 0: driver handles
997 u8 beacon_offload; //FW offloads, 0: driver handles
998 u8 MLME_offload; // FW offloads, 0: driver handles
999 u8 hwpc_offload; // FW offloads, 0: driver handles
1000 u8 tcp_checksum_offload; //FW offloads, 0: driver handles
1001 u8 tcp_offload; //FW offloads, 0: driver handles
1002 u8 ps_control_offload; //FW offloads, 0: driver handles
1003
1004 //--- LONG WORD 5 ----
1005 u8 WWLAN_Offload; // FW offloads, 0: driver handles
1006 u8 MPMode; // normal mode, 0: MP mode;
1007 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1008 u16 Signature; //0x12: 8712, 0x92: 8192S
1009 u16 Rsvd11;
1010
1011// u32 rsvd1;
1012// u32 wireless_band; //no A-band exists in 8712
1013}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
1014
1015typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
1016
1017 //--- LONG WORD 0 ----
1018 u16 Signature;
1019 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
1020 u32 DMEMSize; //define the size of boot loader
1021
1022
1023 //--- LONG WORD 1 ----
1024 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
1025 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
1026
1027 //--- LONG WORD 2 ----
1028 u32 FW_PRIV_SIZE; //define the size of DMEM variable
1029 u32 Rsvd0;
1030
1031 //--- LONG WORD 3 ----
1032 u32 Rsvd1;
1033 u32 Rsvd2;
1034
1035 RT_8192S_FIRMWARE_PRIV FWPriv;
1036
1037}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
1038
1039#define RT_8192S_FIRMWARE_HDR_SIZE 80
1040
1041typedef enum _FIRMWARE_8192S_STATUS{
1042 FW_STATUS_INIT = 0,
1043 FW_STATUS_LOAD_IMEM = 1,
1044 FW_STATUS_LOAD_EMEM = 2,
1045 FW_STATUS_LOAD_DMEM = 3,
1046 FW_STATUS_READY = 4,
1047}FIRMWARE_8192S_STATUS;
1048
1049#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
1050
1051typedef struct _rt_firmware{
1052 firmware_source_e eFWSource;
1053 PRT_8192S_FIRMWARE_HDR pFwHeader;
1054 FIRMWARE_8192S_STATUS FWStatus;
1055 u8 FwIMEM[64000];
1056 u8 FwEMEM[64000];
1057 u32 FwIMEMLen;
1058 u32 FwEMEMLen;
1059 u8 szFwTmpBuffer[164000];
1060 u16 CmdPacketFragThresold;
1061 //firmware_status_e firmware_status;//in 92u temp FIXLZM
1062 //u16 cmdpacket_frag_thresold;//in 92u temp FIXLZM
1063 //u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];//in 92u temp FIXLZM
1064 //u16 firmware_buf_size;//in 92u temp FIXLZM
1065
1066}rt_firmware, *prt_firmware;
1067#else
1068typedef struct _rt_firmware{
1069 firmware_status_e firmware_status;
1070 u16 cmdpacket_frag_thresold;
1071#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
1072#define MAX_FW_INIT_STEP 3
1073 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
1074 u16 firmware_buf_size[MAX_FW_INIT_STEP];
1075}rt_firmware, *prt_firmware;
1076#endif
1077typedef struct _rt_firmware_info_819xUsb{
1078 u8 sz_info[16];
1079}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
1080#endif
1081
1082//+by amy 080507
1083#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
1084
1085
1086/* Firmware Queue Layout */
1087#define NUM_OF_FIRMWARE_QUEUE 10
1088#define NUM_OF_PAGES_IN_FW 0x100
1089
1090#ifdef USE_ONE_PIPE
1091#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000
1092#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000
1093#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff
1094#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000
1095#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
1096#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
1097#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00
1098#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
1099#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
1100#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
1101#else
1102
1103#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
1104#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
1105#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
1106#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
1107#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
1108#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
1109#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
1110#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
1111#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
1112#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
1113
1114#endif
1115
1116#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
1117#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
1118#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
1119#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
1120#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
1121#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
1122#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
1123#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
1124#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
1125//=================================================================
1126//=================================================================
1127
1128#define EPROM_93c46 0
1129#define EPROM_93c56 1
1130
1131#define DEFAULT_FRAG_THRESHOLD 2342U
1132#define MIN_FRAG_THRESHOLD 256U
1133#define DEFAULT_BEACONINTERVAL 0x64U
1134#define DEFAULT_BEACON_ESSID "Rtl819xU"
1135
1136#define DEFAULT_SSID ""
1137#define DEFAULT_RETRY_RTS 7
1138#define DEFAULT_RETRY_DATA 7
1139#define PRISM_HDR_SIZE 64
1140
1141#define PHY_RSSI_SLID_WIN_MAX 100
1142
1143
1144typedef enum _WIRELESS_MODE {
1145 WIRELESS_MODE_UNKNOWN = 0x00,
1146 WIRELESS_MODE_A = 0x01,
1147 WIRELESS_MODE_B = 0x02,
1148 WIRELESS_MODE_G = 0x04,
1149 WIRELESS_MODE_AUTO = 0x08,
1150 WIRELESS_MODE_N_24G = 0x10,
1151 WIRELESS_MODE_N_5G = 0x20
1152} WIRELESS_MODE;
1153
1154
1155#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
1156
1157typedef struct buffer
1158{
1159 struct buffer *next;
1160 u32 *buf;
1161
1162} buffer;
1163
1164typedef struct rtl_reg_debug{
1165 unsigned int cmd;
1166 struct {
1167 unsigned char type;
1168 unsigned char addr;
1169 unsigned char page;
1170 unsigned char length;
1171 } head;
1172 unsigned char buf[0xff];
1173}rtl_reg_debug;
1174
1175
1176
1177
1178
1179#if 0
1180
1181typedef struct tx_pendingbuf
1182{
1183 struct ieee80211_txb *txb;
1184 short ispending;
1185 short descfrag;
1186} tx_pendigbuf;
1187
1188#endif
1189
1190typedef struct _rt_9x_tx_rate_history {
1191 u32 cck[4];
1192 u32 ofdm[8];
1193 // HT_MCS[0][]: BW=0 SG=0
1194 // HT_MCS[1][]: BW=1 SG=0
1195 // HT_MCS[2][]: BW=0 SG=1
1196 // HT_MCS[3][]: BW=1 SG=1
1197 u32 ht_mcs[4][16];
1198}rt_tx_rahis_t, *prt_tx_rahis_t;
1199typedef struct _RT_SMOOTH_DATA_4RF {
1200 char elements[4][100];//array to store values
1201 u32 index; //index to current array to store
1202 u32 TotalNum; //num of valid elements
1203 u32 TotalVal[4]; //sum of valid elements
1204}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
1205
1206#define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
1207//stats seems messed up, clean it ASAP
1208typedef struct Stats
1209{
1210 unsigned long txrdu;
1211// unsigned long rxrdu;
1212 //unsigned long rxnolast;
1213 //unsigned long rxnodata;
1214// unsigned long rxreset;
1215// unsigned long rxnopointer;
1216 unsigned long rxok;
1217 unsigned long rxframgment;
1218 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
1219 unsigned long rxurberr;
1220 unsigned long rxstaterr;
1221 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
1222 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
1223 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
1224 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
1225 unsigned long numpacket_matchbssid; // debug use only.
1226 unsigned long numpacket_toself; // debug use only.
1227 unsigned long num_process_phyinfo; // debug use only.
1228 unsigned long numqry_phystatus;
1229 unsigned long numqry_phystatusCCK;
1230 unsigned long numqry_phystatusHT;
1231 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
1232 unsigned long txnperr;
1233 unsigned long txnpdrop;
1234 unsigned long txresumed;
1235// unsigned long rxerr;
1236// unsigned long rxoverflow;
1237// unsigned long rxint;
1238 unsigned long txnpokint;
1239// unsigned long txhpokint;
1240// unsigned long txhperr;
1241// unsigned long ints;
1242// unsigned long shints;
1243 unsigned long txoverflow;
1244// unsigned long rxdmafail;
1245// unsigned long txbeacon;
1246// unsigned long txbeaconerr;
1247 unsigned long txlpokint;
1248 unsigned long txlpdrop;
1249 unsigned long txlperr;
1250 unsigned long txbeokint;
1251 unsigned long txbedrop;
1252 unsigned long txbeerr;
1253 unsigned long txbkokint;
1254 unsigned long txbkdrop;
1255 unsigned long txbkerr;
1256 unsigned long txviokint;
1257 unsigned long txvidrop;
1258 unsigned long txvierr;
1259 unsigned long txvookint;
1260 unsigned long txvodrop;
1261 unsigned long txvoerr;
1262 unsigned long txbeaconokint;
1263 unsigned long txbeacondrop;
1264 unsigned long txbeaconerr;
1265 unsigned long txmanageokint;
1266 unsigned long txmanagedrop;
1267 unsigned long txmanageerr;
1268 unsigned long txdatapkt;
1269 unsigned long txfeedback;
1270 unsigned long txfeedbackok;
1271
1272 unsigned long txoktotal;
1273 unsigned long txokbytestotal;
1274 unsigned long txokinperiod;
1275 unsigned long txmulticast;
1276 unsigned long txbytesmulticast;
1277 unsigned long txbroadcast;
1278 unsigned long txbytesbroadcast;
1279 unsigned long txunicast;
1280 unsigned long txbytesunicast;
1281
1282 unsigned long rxoktotal;
1283 unsigned long rxbytesunicast;
1284 unsigned long txfeedbackfail;
1285 unsigned long txerrtotal;
1286 unsigned long txerrbytestotal;
1287 unsigned long txerrmulticast;
1288 unsigned long txerrbroadcast;
1289 unsigned long txerrunicast;
1290 unsigned long txretrycount;
1291 unsigned long txfeedbackretry;
1292 u8 last_packet_rate;
1293 unsigned long slide_signal_strength[100];
1294 unsigned long slide_evm[100];
1295 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
1296 unsigned long slide_evm_total; // For recording sliding window's EVM value
1297 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
1298 long signal_quality;
1299 long last_signal_strength_inpercent;
1300 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
1301 u8 rx_rssi_percentage[4];
1302 u8 rx_evm_percentage[2];
1303 long rxSNRdB[4];
1304 rt_tx_rahis_t txrate;
1305 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
1306 u32 Slide_Beacon_Total; //cosa add for beacon rssi
1307 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
1308
1309 u32 CurrentShowTxate;
1310} Stats;
1311
1312
1313// Bandwidth Offset
1314#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
1315#define HAL_PRIME_CHNL_OFFSET_LOWER 1
1316#define HAL_PRIME_CHNL_OFFSET_UPPER 2
1317
1318//+by amy 080507
1319
1320typedef struct ChnlAccessSetting {
1321 u16 SIFS_Timer;
1322 u16 DIFS_Timer;
1323 u16 SlotTimeTimer;
1324 u16 EIFS_Timer;
1325 u16 CWminIndex;
1326 u16 CWmaxIndex;
1327}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
1328
1329typedef struct _BB_REGISTER_DEFINITION{
1330 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
1331 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
1332 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
1333 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
1334 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
1335 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
1336 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
1337 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
1338 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
1339 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
1340 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
1341 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
1342 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
1343 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
1344 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
1345 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
1346 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
1347 u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
1348}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
1349
1350typedef enum _RT_RF_TYPE_819xU{
1351 RF_TYPE_MIN = 0,
1352 RF_8225,
1353 RF_8256,
1354 RF_8258,
1355 RF_6052=4, // 4 11b/g/n RF
1356 RF_PSEUDO_11N = 5,
1357}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
1358
1359//#ifdef RTL8192SU
1360typedef enum _RF_POWER_STATE{
1361 RF_ON,
1362 RF_SLEEP,
1363 RF_OFF,
1364 RF_SHUT_DOWN,
1365}RF_POWER_STATE, *PRF_POWER_STATE;
1366//#endif
1367
1368typedef struct _rate_adaptive
1369{
1370 u8 rate_adaptive_disabled;
1371 u8 ratr_state;
1372 u16 reserve;
1373
1374 u32 high_rssi_thresh_for_ra;
1375 u32 high2low_rssi_thresh_for_ra;
1376 u8 low2high_rssi_thresh_for_ra40M;
1377 u32 low_rssi_thresh_for_ra40M;
1378 u8 low2high_rssi_thresh_for_ra20M;
1379 u32 low_rssi_thresh_for_ra20M;
1380 u32 upper_rssi_threshold_ratr;
1381 u32 middle_rssi_threshold_ratr;
1382 u32 low_rssi_threshold_ratr;
1383 u32 low_rssi_threshold_ratr_40M;
1384 u32 low_rssi_threshold_ratr_20M;
1385 u8 ping_rssi_enable; //cosa add for test
1386 u32 ping_rssi_ratr; //cosa add for test
1387 u32 ping_rssi_thresh_for_ra;//cosa add for test
1388 u32 last_ratr;
1389
1390} rate_adaptive, *prate_adaptive;
1391
1392#define TxBBGainTableLength 37
1393#define CCKTxBBGainTableLength 23
1394
1395typedef struct _txbbgain_struct
1396{
1397 long txbb_iq_amplifygain;
1398 u32 txbbgain_value;
1399} txbbgain_struct, *ptxbbgain_struct;
1400
1401typedef struct _ccktxbbgain_struct
1402{
1403 //The Value is from a22 to a29 one Byte one time is much Safer
1404 u8 ccktxbb_valuearray[8];
1405} ccktxbbgain_struct,*pccktxbbgain_struct;
1406
1407
1408typedef struct _init_gain
1409{
1410 u8 xaagccore1;
1411 u8 xbagccore1;
1412 u8 xcagccore1;
1413 u8 xdagccore1;
1414 u8 cca;
1415
1416} init_gain, *pinit_gain;
1417//by amy 0606
1418
1419typedef struct _phy_ofdm_rx_status_report_819xusb
1420{
1421 u8 trsw_gain_X[4];
1422 u8 pwdb_all;
1423 u8 cfosho_X[4];
1424 u8 cfotail_X[4];
1425 u8 rxevm_X[2];
1426 u8 rxsnr_X[4];
1427 u8 pdsnr_X[2];
1428 u8 csi_current_X[2];
1429 u8 csi_target_X[2];
1430 u8 sigevm;
1431 u8 max_ex_pwr;
1432 u8 sgi_en;
1433 u8 rxsc_sgien_exflg;
1434}phy_sts_ofdm_819xusb_t;
1435
1436typedef struct _phy_cck_rx_status_report_819xusb
1437{
1438 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1439 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1440 u8 adc_pwdb_X[4];
1441 u8 sq_rpt;
1442 u8 cck_agc_rpt;
1443}phy_sts_cck_819xusb_t;
1444
1445
1446typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1447 u8 reserved:4;
1448 u8 rxsc:2;
1449 u8 sgi_en:1;
1450 u8 ex_intf_flag:1;
1451}phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1452
1453typedef enum _RT_CUSTOMER_ID
1454{
1455 RT_CID_DEFAULT = 0,
1456 RT_CID_8187_ALPHA0 = 1,
1457 RT_CID_8187_SERCOMM_PS = 2,
1458 RT_CID_8187_HW_LED = 3,
1459 RT_CID_8187_NETGEAR = 4,
1460 RT_CID_WHQL = 5,
1461 RT_CID_819x_CAMEO = 6,
1462 RT_CID_819x_RUNTOP = 7,
1463 RT_CID_819x_Senao = 8,
1464 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
1465 RT_CID_819x_Netcore = 10,
1466 RT_CID_Nettronix = 11,
1467 RT_CID_DLINK = 12,
1468 RT_CID_PRONET = 13,
1469}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1470
1471//================================================================================
1472// LED customization.
1473//================================================================================
1474
1475typedef enum _LED_STRATEGY_8190{
1476 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
1477 SW_LED_MODE1, // SW control for PCI Express
1478 SW_LED_MODE2, // SW control for Cameo.
1479 SW_LED_MODE3, // SW contorl for RunTop.
1480 SW_LED_MODE4, // SW control for Netcore
1481 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
1482}LED_STRATEGY_8190, *PLED_STRATEGY_8190;
1483
1484typedef enum _RESET_TYPE {
1485 RESET_TYPE_NORESET = 0x00,
1486 RESET_TYPE_NORMAL = 0x01,
1487 RESET_TYPE_SILENT = 0x02
1488} RESET_TYPE;
1489
1490/* The simple tx command OP code. */
1491typedef enum _tag_TxCmd_Config_Index{
1492 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
1493 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
1494 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
1495 TXCMD_SET_TX_DURATION = 0xFF900003,
1496 TXCMD_SET_RX_RSSI = 0xFF900004,
1497 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
1498 TXCMD_XXXX_CTRL,
1499}DCMD_TXCMD_OP;
1500
1501typedef enum{
1502 NIC_8192U = 1,
1503 NIC_8190P = 2,
1504 NIC_8192E = 3,
1505 NIC_8192SE = 4,
1506 NIC_8192SU = 5,
1507 } nic_t;
1508
1509//definded by WB. Ready to fill handlers for different NIC types.
1510//add handle here when necessary.
1511struct rtl819x_ops{
1512 nic_t nic_type;
1513 void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1514 short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1515 short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1516 void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1517 void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1518 bool (* rtl819x_adapter_start)(struct net_device *dev);
1519 void (* rtl819x_link_change)(struct net_device *dev);
1520 void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1521 void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1522};
1523
1524typedef struct r8192_priv
1525{
1526 struct rtl819x_ops* ops;
1527 struct usb_device *udev;
1528 //added for maintain info from eeprom
1529 short epromtype;
1530 u16 eeprom_vid;
1531 u16 eeprom_pid;
1532 u8 eeprom_CustomerID;
1533 u8 eeprom_SubCustomerID;
1534 u8 eeprom_ChannelPlan;
1535 RT_CUSTOMER_ID CustomerID;
1536 LED_STRATEGY_8190 LedStrategy;
1537 u8 txqueue_to_outpipemap[9];
1538 u8 RtOutPipes[16];
1539 u8 RtInPipes[16];
1540 u8 ep_in_num;
1541 u8 ep_out_num;
1542 u8 ep_num;
1543 int irq;
1544 struct ieee80211_device *ieee80211;
1545
1546 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1547 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1548// short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1549 short enable_gpio0;
1550 enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1551 short hw_plcp_len;
1552 short plcp_preamble_mode;
1553
1554 spinlock_t irq_lock;
1555// spinlock_t irq_th_lock;
1556 spinlock_t tx_lock;
1557 spinlock_t ps_lock;
1558#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
1559 struct semaphore mutex;
1560#else
1561 struct mutex mutex;
1562#endif
1563 spinlock_t rf_lock; //used to lock rf write operation added by wb
1564
1565 u16 irq_mask;
1566// short irq_enabled;
1567// struct net_device *dev; //comment this out.
1568 short chan;
1569 short sens;
1570 short max_sens;
1571
1572
1573 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1574// u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1575// u8 cck_txpwr_base;
1576// u8 ofdm_txpwr_base;
1577// u8 challow[15]; //channels from 1 to 14, 0 not used
1578 short up;
1579 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1580// short prism_hdr;
1581
1582// struct timer_list scan_timer;
1583 /*short scanpending;
1584 short stopscan;*/
1585// spinlock_t scan_lock;
1586// u8 active_probe;
1587 //u8 active_scan_num;
1588 struct semaphore wx_sem;
1589 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1590// short hw_wep;
1591
1592// short digphy;
1593// short antb;
1594// short diversity;
1595// u8 cs_treshold;
1596// short rcr_csense;
1597 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1598 RT_RF_TYPE_819xU rf_chip;
1599
1600// u32 key0[4];
1601 short (*rf_set_sens)(struct net_device *dev,short sens);
1602 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1603 void (*rf_close)(struct net_device *dev);
1604 void (*rf_init)(struct net_device *dev);
1605 //short rate;
1606 short promisc;
1607 /*stats*/
1608 struct Stats stats;
1609 struct iw_statistics wstats;
1610 struct proc_dir_entry *dir_dev;
1611
1612 /*RX stuff*/
1613// u32 *rxring;
1614// u32 *rxringtail;
1615// dma_addr_t rxringdma;
1616 struct urb **rx_urb;
1617 struct urb **rx_cmd_urb;
1618
1619/* modified by davad for Rx process */
1620 struct sk_buff_head rx_queue;
1621 struct sk_buff_head skb_queue;
1622#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
1623 struct tq_struct qos_activate;
1624#else
1625 struct work_struct qos_activate;
1626#endif
1627 short tx_urb_index;
1628 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1629
1630
1631 struct tasklet_struct irq_rx_tasklet;
1632 struct urb *rxurb_task;
1633
1634 //2 Tx Related variables
1635 u16 ShortRetryLimit;
1636 u16 LongRetryLimit;
1637 u32 TransmitConfig;
1638 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1639
1640 u32 LastRxDescTSFHigh;
1641 u32 LastRxDescTSFLow;
1642
1643
1644 //2 Rx Related variables
1645 u16 EarlyRxThreshold;
1646 u32 ReceiveConfig;
1647 u8 AcmControl;
1648
1649 u8 RFProgType;
1650
1651 u8 retry_data;
1652 u8 retry_rts;
1653 u16 rts;
1654
1655 struct ChnlAccessSetting ChannelAccessSetting;
1656#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1657 struct work_struct reset_wq;
1658#else
1659 struct tq_struct reset_wq;
1660#endif
1661
1662/**********************************************************/
1663 //for rtl819xUsb
1664 u16 basic_rate;
1665 u8 short_preamble;
1666 u8 slot_time;
1667 bool bDcut;
1668 bool bCurrentRxAggrEnable;
1669 u8 Rf_Mode; //add for Firmware RF -R/W switch
1670 prt_firmware pFirmware;
1671 rtl819xUsb_loopback_e LoopbackMode;
1672 firmware_source_e firmware_source;
1673 bool usb_error;
1674
1675 u16 EEPROMTxPowerDiff;
1676 u8 EEPROMThermalMeter;
1677 u8 EEPROMPwDiff;
1678 u8 EEPROMCrystalCap;
1679 u8 EEPROM_Def_Ver;
1680 u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1681 u8 EEPROMTxPowerLevelCCK_V1[3];
1682 u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1683 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1684
1685//RTL8192SU
1686 bool bDmDisableProtect;
1687 bool bIgnoreDiffRateTxPowerOffset;
1688
1689#ifdef EEPROM_OLD_FORMAT_SUPPORT
1690 u8 EEPROMTxPowerLevelCCK24G[14]; // CCK 2.4G channel 1~14
1691 //u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1692 //u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1693#else
1694 // For EEPROM TX Power Index like 8190 series
1695 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1696 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1697 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1698 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1699
1700 // F92S new definition
1701 //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1702 u8 RfCckChnlAreaTxPwr[2][3];
1703 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1704 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1705#endif
1706
1707 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1708 bool EepromOrEfuse;
1709 bool bBootFromEfuse; // system boot form EFUSE
1710 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
1711
1712 u8 EEPROMUsbOption;
1713 u8 EEPROMUsbPhyParam[5];
1714 u8 EEPROMTxPwrBase;
1715 u8 EEPROMBoardType;
1716 bool bBootFromEEPROM; // system boot from EEPROM
1717 u8 EEPROMTSSI_A;
1718 u8 EEPROMTSSI_B;
1719 u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B.
1720 u8 EEPROMTxPwrTkMode;
1721
1722 u8 bTXPowerDataReadFromEEPORM;
1723
1724 u8 EEPROMVersion;
1725 u8 EEPROMUsbEndPointNumber;
1726
1727 bool AutoloadFailFlag;
1728 u8 RfTxPwrLevelCck[2][14];
1729 u8 RfTxPwrLevelOfdm1T[2][14];
1730 u8 RfTxPwrLevelOfdm2T[2][14];
1731 // 2009/01/20 MH Add for new EEPROM format.
1732 u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff
1733 u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff
1734 u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel
1735 u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel
1736 u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel
1737 u8 TxPwrbandEdgeFlag; // Band edge enable flag
1738
1739 // L1 and L2 high power threshold.
1740 u8 MidHighPwrTHR_L1;
1741 u8 MidHighPwrTHR_L2;
1742 u8 TxPwrSafetyFlag; // for Tx power safety spec
1743//RTL8192SU
1744
1745/*PHY related*/
1746 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1747 // Read/write are allow for following hardware information variables
1748#ifdef RTL8192SU
1749 u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1750#else
1751 u32 MCSTxPowerLevelOriginalOffset[6];
1752#endif
1753 u32 CCKTxPowerLevelOriginalOffset;
1754 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1755 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1756 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1757 u32 Pwr_Track;
1758 u8 TxPowerDiff;
1759 u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1760 u8 CrystalCap; // CrystalCap.
1761 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1762
1763 u8 CckPwEnl;
1764 // Use to calculate PWBD.
1765 u8 bCckHighPower;
1766 long undecorated_smoothed_pwdb;
1767
1768 //for set channel
1769 u8 SwChnlInProgress;
1770 u8 SwChnlStage;
1771 u8 SwChnlStep;
1772 u8 SetBWModeInProgress;
1773 HT_CHANNEL_WIDTH CurrentChannelBW;
1774 u8 ChannelPlan;
1775 u8 pwrGroupCnt;
1776 // 8190 40MHz mode
1777 //
1778 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1779 // Joseph test for shorten RF configuration time.
1780 // We save RF reg0 in this variable to reduce RF reading.
1781 //
1782 u32 RfReg0Value[4];
1783 u8 NumTotalRFPath;
1784 bool brfpath_rxenable[4];
1785 //RF set related
1786 bool SetRFPowerStateInProgress;
1787//+by amy 080507
1788 struct timer_list watch_dog_timer;
1789
1790//+by amy 080515 for dynamic mechenism
1791 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1792 bool bdynamic_txpower; //bDynamicTxPower
1793 bool bDynamicTxHighPower; // Tx high power state
1794 bool bDynamicTxLowPower; // Tx low power state
1795 bool bLastDTPFlag_High;
1796 bool bLastDTPFlag_Low;
1797
1798 bool bstore_last_dtpflag;
1799 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1800 //Add by amy for Rate Adaptive
1801 rate_adaptive rate_adaptive;
1802 //Add by amy for TX power tracking
1803 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1804 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1805 u8 EEPROMTxPowerTrackEnable;
1806 u8 txpower_count;//For 6 sec do tracking again
1807 bool btxpower_trackingInit;
1808 u8 OFDM_index;
1809 u8 CCK_index;
1810 //2007/09/10 Mars Add CCK TX Power Tracking
1811 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1812 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1813 u8 rfa_txpowertrackingindex;
1814 u8 rfa_txpowertrackingindex_real;
1815 u8 rfa_txpowertracking_default;
1816 u8 rfc_txpowertrackingindex;
1817 u8 rfc_txpowertrackingindex_real;
1818
1819 s8 cck_present_attentuation;
1820 u8 cck_present_attentuation_20Mdefault;
1821 u8 cck_present_attentuation_40Mdefault;
1822 char cck_present_attentuation_difference;
1823 bool btxpower_tracking;
1824 bool bcck_in_ch14;
1825 bool btxpowerdata_readfromEEPORM;
1826 u16 TSSI_13dBm;
1827 //For Backup Initial Gain
1828 init_gain initgain_backup;
1829 u8 DefaultInitialGain[4];
1830 // For EDCA Turbo mode, Added by amy 080515.
1831 bool bis_any_nonbepkts;
1832 bool bcurrent_turbo_EDCA;
1833 bool bis_cur_rdlstate;
1834 struct timer_list fsync_timer;
1835 bool bfsync_processing; // 500ms Fsync timer is active or not
1836 u32 rate_record;
1837 u32 rateCountDiffRecord;
1838 u32 ContiuneDiffCount;
1839 bool bswitch_fsync;
1840
1841 u8 framesync;
1842 u32 framesyncC34;
1843 u8 framesyncMonitor;
1844 //Added by amy 080516 for RX related
1845 u16 nrxAMPDU_size;
1846 u8 nrxAMPDU_aggr_num;
1847
1848 //by amy for gpio
1849 bool bHwRadioOff;
1850
1851 //by amy for reset_count
1852 u32 reset_count;
1853 bool bpbc_pressed;
1854 //by amy for debug
1855 u32 txpower_checkcnt;
1856 u32 txpower_tracking_callback_cnt;
1857 u8 thermal_read_val[40];
1858 u8 thermal_readback_index;
1859 u32 ccktxpower_adjustcnt_not_ch14;
1860 u32 ccktxpower_adjustcnt_ch14;
1861 u8 tx_fwinfo_force_subcarriermode;
1862 u8 tx_fwinfo_force_subcarrierval;
1863 //by amy for silent reset
1864 RESET_TYPE ResetProgress;
1865 bool bForcedSilentReset;
1866 bool bDisableNormalResetCheck;
1867 u16 TxCounter;
1868 u16 RxCounter;
1869 int IrpPendingCount;
1870 bool bResetInProgress;
1871 bool force_reset;
1872 u8 InitialGainOperateType;
1873
1874 u16 SifsTime;
1875
1876 //define work item by amy 080526
1877#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1878
1879#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1880 struct delayed_work update_beacon_wq;
1881 struct delayed_work watch_dog_wq;
1882 struct delayed_work txpower_tracking_wq;
1883 struct delayed_work rfpath_check_wq;
1884 struct delayed_work gpio_change_rf_wq;
1885 struct delayed_work initialgain_operate_wq;
1886#else
1887 struct work_struct update_beacon_wq;
1888 struct work_struct watch_dog_wq;
1889 struct work_struct txpower_tracking_wq;
1890 struct work_struct rfpath_check_wq;
1891 struct work_struct gpio_change_rf_wq;
1892 struct work_struct initialgain_operate_wq;
1893#endif
1894 struct workqueue_struct *priv_wq;
1895#else
1896 /* used for periodly scan */
1897 struct tq_struct update_beacon_wq;
1898 struct tq_struct txpower_tracking_wq;
1899 struct tq_struct rfpath_check_wq;
1900 struct tq_struct watch_dog_wq;
1901 struct tq_struct gpio_change_rf_wq;
1902 struct tq_struct initialgain_operate_wq;
1903#endif
1904//#ifdef RTL8192SU
1905 //lzm add for 8192S
1906 u32 IntrMask;
1907 // RF and BB access related synchronization flags.
1908 bool bChangeBBInProgress; // BaseBand RW is still in progress.
1909 bool bChangeRFInProgress; // RF RW is still in progress.
1910
1911 u32 CCKTxPowerAdjustCntCh14; //debug only
1912 u32 CCKTxPowerAdjustCntNotCh14; //debug only
1913 u32 TXPowerTrackingCallbackCnt; //debug only
1914 u32 TxPowerCheckCnt; //debug only
1915 u32 RFWritePageCnt[3]; //debug only
1916 u32 RFReadPageCnt[3]; //debug only
1917 u8 ThermalReadBackIndex; //debug only
1918 u8 ThermalReadVal[40]; //debug only
1919
1920 // For HCT test, 2005.07.15, by rcnjko.
1921 // not realize true, just define it, set it 0 default, because some func use it
1922 bool bInHctTest;
1923
1924 // The current Tx Power Level
1925 u8 CurrentCckTxPwrIdx;
1926 u8 CurrentOfdm24GTxPwrIdx;
1927
1928 // For pass 92S common phycfg.c compiler
1929 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1930 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1931 u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14
1932 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1933 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1934 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1935
1936 bool bRFSiOrPi;//0=si, 1=pi.
1937 //lzm add for 8192S
1938
1939 bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1940 u8 CurrentFwCmdIO;
1941
1942 u8 MinSpaceCfg;
1943
1944 u16 rf_pathmap;
1945//#endif
1946
1947
1948#ifdef USB_RX_AGGREGATION_SUPPORT
1949 bool bCurrentRxAggrEnable;
1950 bool bForcedUsbRxAggr;
1951 u32 ForcedUsbRxAggrInfo;
1952 u32 LastUsbRxAggrInfoSetting;
1953 u32 RegUsbRxAggrInfo;
1954#endif
1955
1956
1957
1958}r8192_priv;
1959
1960// for rtl8187
1961// now mirging to rtl8187B
1962/*
1963typedef enum{
1964 LOW_PRIORITY = 0x02,
1965 NORM_PRIORITY
1966 } priority_t;
1967*/
1968//for rtl8187B
1969typedef enum{
1970 BULK_PRIORITY = 0x01,
1971 //RSVD0,
1972 //RSVD1,
1973 LOW_PRIORITY,
1974 NORM_PRIORITY,
1975 VO_PRIORITY,
1976 VI_PRIORITY, //0x05
1977 BE_PRIORITY,
1978 BK_PRIORITY,
1979 RSVD2,
1980 RSVD3,
1981 BEACON_PRIORITY, //0x0A
1982 HIGH_PRIORITY,
1983 MANAGE_PRIORITY,
1984 RSVD4,
1985 RSVD5,
1986 UART_PRIORITY //0x0F
1987} priority_t;
1988
1989#if 0
1990typedef enum{
1991 NIC_8192U = 1,
1992 NIC_8190P = 2,
1993 NIC_8192E = 3,
1994 NIC_8192SE = 4,
1995 NIC_8192SU = 5,
1996 } nic_t;
1997#endif
1998
1999#if 0 //defined in Qos.h
2000//typedef u32 AC_CODING;
2001#define AC0_BE 0 // ACI: 0x00 // Best Effort
2002#define AC1_BK 1 // ACI: 0x01 // Background
2003#define AC2_VI 2 // ACI: 0x10 // Video
2004#define AC3_VO 3 // ACI: 0x11 // Voice
2005#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
2006
2007//
2008// ECWmin/ECWmax field.
2009// Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
2010//
2011typedef union _ECW{
2012 u8 charData;
2013 struct
2014 {
2015 u8 ECWmin:4;
2016 u8 ECWmax:4;
2017 }f; // Field
2018}ECW, *PECW;
2019
2020//
2021// ACI/AIFSN Field.
2022// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
2023//
2024typedef union _ACI_AIFSN{
2025 u8 charData;
2026
2027 struct
2028 {
2029 u8 AIFSN:4;
2030 u8 ACM:1;
2031 u8 ACI:2;
2032 u8 Reserved:1;
2033 }f; // Field
2034}ACI_AIFSN, *PACI_AIFSN;
2035
2036//
2037// AC Parameters Record Format.
2038// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
2039//
2040typedef union _AC_PARAM{
2041 u32 longData;
2042 u8 charData[4];
2043
2044 struct
2045 {
2046 ACI_AIFSN AciAifsn;
2047 ECW Ecw;
2048 u16 TXOPLimit;
2049 }f; // Field
2050}AC_PARAM, *PAC_PARAM;
2051
2052#endif
2053#ifdef JOHN_HWSEC
2054struct ssid_thread {
2055 struct net_device *dev;
2056 u8 name[IW_ESSID_MAX_SIZE + 1];
2057};
2058#endif
2059
2060#ifdef RTL8192SU
2061short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2062short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
2063bool FirmwareDownload92S(struct net_device *dev);
2064#else
2065short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2066bool init_firmware(struct net_device *dev);
2067#endif
2068
2069short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
2070short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
2071
2072u32 read_cam(struct net_device *dev, u8 addr);
2073void write_cam(struct net_device *dev, u8 addr, u32 data);
2074
2075u8 read_nic_byte(struct net_device *dev, int x);
2076u8 read_nic_byte_E(struct net_device *dev, int x);
2077u32 read_nic_dword(struct net_device *dev, int x);
2078u16 read_nic_word(struct net_device *dev, int x) ;
2079void write_nic_byte(struct net_device *dev, int x,u8 y);
2080void write_nic_byte_E(struct net_device *dev, int x,u8 y);
2081void write_nic_word(struct net_device *dev, int x,u16 y);
2082void write_nic_dword(struct net_device *dev, int x,u32 y);
2083void force_pci_posting(struct net_device *dev);
2084
2085void rtl8192_rtx_disable(struct net_device *);
2086void rtl8192_rx_enable(struct net_device *);
2087void rtl8192_tx_enable(struct net_device *);
2088
2089void rtl8192_disassociate(struct net_device *dev);
2090//void fix_rx_fifo(struct net_device *dev);
2091void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
2092
2093void rtl8192_set_anaparam(struct net_device *dev,u32 a);
2094void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
2095void rtl8192_update_msr(struct net_device *dev);
2096int rtl8192_down(struct net_device *dev);
2097int rtl8192_up(struct net_device *dev);
2098void rtl8192_commit(struct net_device *dev);
2099void rtl8192_set_chan(struct net_device *dev,short ch);
2100void write_phy(struct net_device *dev, u8 adr, u8 data);
2101void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
2102void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
2103void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
2104void rtl8192_set_rxconf(struct net_device *dev);
2105//short check_nic_enough_desc(struct net_device *dev, priority_t priority);
2106extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
2107void CamResetAllEntry(struct net_device* dev);
2108void EnableHWSecurityConfig8192(struct net_device *dev);
2109void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
2110short rtl8192_is_tx_queue_empty(struct net_device *dev);
2111
2112#endif
diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c
new file mode 100644
index 00000000000..f1423d71449
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_core.c
@@ -0,0 +1,12460 @@
1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8192U
4 *
5 * Based on the r8187 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Jerry chuang <wlanfae@realtek.com>
25 */
26
27#ifndef CONFIG_FORCE_HARD_FLOAT
28double __floatsidf (int i) { return i; }
29unsigned int __fixunsdfsi (double d) { return d; }
30double __adddf3(double a, double b) { return a+b; }
31double __addsf3(float a, float b) { return a+b; }
32double __subdf3(double a, double b) { return a-b; }
33double __extendsfdf2(float a) {return a;}
34#endif
35
36#undef LOOP_TEST
37#undef DUMP_RX
38#undef DUMP_TX
39#undef DEBUG_TX_DESC2
40#undef RX_DONT_PASS_UL
41#undef DEBUG_EPROM
42#undef DEBUG_RX_VERBOSE
43#undef DUMMY_RX
44#undef DEBUG_ZERO_RX
45#undef DEBUG_RX_SKB
46#undef DEBUG_TX_FRAG
47#undef DEBUG_RX_FRAG
48#undef DEBUG_TX_FILLDESC
49#undef DEBUG_TX
50#undef DEBUG_IRQ
51#undef DEBUG_RX
52#undef DEBUG_RXALLOC
53#undef DEBUG_REGISTERS
54#undef DEBUG_RING
55#undef DEBUG_IRQ_TASKLET
56#undef DEBUG_TX_ALLOC
57#undef DEBUG_TX_DESC
58
59#define CONFIG_RTL8192_IO_MAP
60
61#ifdef RTL8192SU
62#include <asm/uaccess.h>
63#include "r8192U.h"
64//#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
65#include "r8180_93cx6.h" /* Card EEPROM */
66#include "r8192U_wx.h"
67
68#include "r8192S_rtl8225.h"
69#include "r8192S_hw.h"
70#include "r8192S_phy.h"
71#include "r8192S_phyreg.h"
72#include "r8192S_Efuse.h"
73
74#include "r819xU_cmdpkt.h"
75#include "r8192U_dm.h"
76//#include "r8192xU_phyreg.h"
77#include <linux/usb.h>
78// FIXME: check if 2.6.7 is ok
79#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7))
80#define usb_kill_urb usb_unlink_urb
81#endif
82
83#ifdef CONFIG_RTL8192_PM
84#include "r8192U_pm.h"
85#endif
86
87#ifdef ENABLE_DOT11D
88#include "dot11d.h"
89#endif
90
91#else
92
93#include <asm/uaccess.h>
94#include "r8192U_hw.h"
95#include "r8192U.h"
96#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
97#include "r8180_93cx6.h" /* Card EEPROM */
98#include "r8192U_wx.h"
99#include "r819xU_phy.h" //added by WB 4.30.2008
100#include "r819xU_phyreg.h"
101#include "r819xU_cmdpkt.h"
102#include "r8192U_dm.h"
103//#include "r8192xU_phyreg.h"
104#include <linux/usb.h>
105// FIXME: check if 2.6.7 is ok
106#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7))
107#define usb_kill_urb usb_unlink_urb
108#endif
109
110#ifdef CONFIG_RTL8192_PM
111#include "r8192U_pm.h"
112#endif
113
114#ifdef ENABLE_DOT11D
115#include "dot11d.h"
116#endif
117
118#endif
119
120
121#ifdef RTL8192SU
122u32 rt_global_debug_component = \
123// COMP_TRACE |
124// COMP_DBG |
125// COMP_INIT |
126// COMP_RECV |
127// COMP_SEND |
128// COMP_IO |
129 COMP_POWER |
130// COMP_EPROM |
131 COMP_SWBW |
132 COMP_POWER_TRACKING |
133 COMP_TURBO |
134 COMP_QOS |
135// COMP_RATE |
136// COMP_RM |
137 COMP_DIG |
138// COMP_EFUSE |
139// COMP_CH |
140// COMP_TXAGC |
141 COMP_HIPWR |
142// COMP_HALDM |
143 COMP_SEC |
144 COMP_LED |
145// COMP_RF |
146// COMP_RXDESC |
147 COMP_FIRMWARE |
148 COMP_HT |
149 COMP_AMSDU |
150 COMP_SCAN |
151// COMP_CMD |
152 COMP_DOWN |
153 COMP_RESET |
154 COMP_ERR; //always open err flags on
155#else
156//set here to open your trace code. //WB
157u32 rt_global_debug_component = \
158 // COMP_INIT |
159// COMP_DBG |
160 // COMP_EPROM |
161// COMP_PHY |
162 // COMP_RF |
163// COMP_FIRMWARE |
164// COMP_CH |
165 // COMP_POWER_TRACKING |
166// COMP_RATE |
167 // COMP_TXAGC |
168 // COMP_TRACE |
169 COMP_DOWN |
170 // COMP_RECV |
171 // COMP_SWBW |
172 COMP_SEC |
173 // COMP_RESET |
174 // COMP_SEND |
175 // COMP_EVENTS |
176 COMP_ERR ; //always open err flags on
177#endif
178
179#define TOTAL_CAM_ENTRY 32
180#define CAM_CONTENT_COUNT 8
181
182static struct usb_device_id rtl8192_usb_id_tbl[] = {
183 /* Realtek */
184 {USB_DEVICE(0x0bda, 0x8192)},
185 {USB_DEVICE(0x0bda, 0x8709)},
186 /* Corega */
187 {USB_DEVICE(0x07aa, 0x0043)},
188 /* Belkin */
189 {USB_DEVICE(0x050d, 0x805E)},
190 /* Sitecom */
191 {USB_DEVICE(0x0df6, 0x0031)},
192 /* EnGenius */
193 {USB_DEVICE(0x1740, 0x9201)},
194 /* Dlink */
195 {USB_DEVICE(0x2001, 0x3301)},
196 /* Zinwell */
197 {USB_DEVICE(0x5a57, 0x0290)},
198 //92SU
199 {USB_DEVICE(0x0bda, 0x8172)},
200 {}
201};
202
203MODULE_LICENSE("GPL");
204#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
205MODULE_VERSION("V 1.1");
206#endif
207MODULE_DEVICE_TABLE(usb, rtl8192_usb_id_tbl);
208MODULE_DESCRIPTION("Linux driver for Realtek RTL8192 USB WiFi cards");
209
210static char* ifname = "wlan%d";
211#if 0
212static int hwseqnum = 0;
213static int hwwep = 0;
214#endif
215static int hwwep = 1; //default use hw. set 0 to use software security
216static int channels = 0x3fff;
217
218
219
220#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9)
221module_param(ifname, charp, S_IRUGO|S_IWUSR );
222//module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
223module_param(hwwep,int, S_IRUGO|S_IWUSR);
224module_param(channels,int, S_IRUGO|S_IWUSR);
225#else
226MODULE_PARM(ifname, "s");
227//MODULE_PARM(hwseqnum,"i");
228MODULE_PARM(hwwep,"i");
229MODULE_PARM(channels,"i");
230#endif
231
232MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default");
233//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
234MODULE_PARM_DESC(hwwep," Try to use hardware security support. ");
235MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
236
237#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
238static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
239 const struct usb_device_id *id);
240static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf);
241#else
242static void *__devinit rtl8192_usb_probe(struct usb_device *udev,unsigned int ifnum,
243 const struct usb_device_id *id);
244static void __devexit rtl8192_usb_disconnect(struct usb_device *udev, void *ptr);
245#endif
246
247
248static struct usb_driver rtl8192_usb_driver = {
249#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 15)
250 .owner = THIS_MODULE,
251#endif
252 .name = RTL819xU_MODULE_NAME, /* Driver name */
253 .id_table = rtl8192_usb_id_tbl, /* PCI_ID table */
254 .probe = rtl8192_usb_probe, /* probe fn */
255 .disconnect = rtl8192_usb_disconnect, /* remove fn */
256#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)
257#ifdef CONFIG_RTL8192_PM
258 .suspend = rtl8192U_suspend, /* PM suspend fn */
259 .resume = rtl8192U_resume, /* PM resume fn */
260#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)
261 .reset_resume = rtl8192U_resume, /* PM reset resume fn */
262#endif
263#else
264 .suspend = NULL, /* PM suspend fn */
265 .resume = NULL, /* PM resume fn */
266#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)
267 .reset_resume = NULL, /* PM reset resume fn */
268#endif
269#endif
270#endif
271};
272
273
274#ifdef RTL8192SU
275static void rtl8192SU_read_eeprom_info(struct net_device *dev);
276short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
277void rtl8192SU_rx_nomal(struct sk_buff* skb);
278void rtl8192SU_rx_cmd(struct sk_buff *skb);
279bool rtl8192SU_adapter_start(struct net_device *dev);
280short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
281void rtl8192SU_link_change(struct net_device *dev);
282void InitialGain8192S(struct net_device *dev,u8 Operation);
283void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
284
285struct rtl819x_ops rtl8192su_ops = {
286 .nic_type = NIC_8192SU,
287 .rtl819x_read_eeprom_info = rtl8192SU_read_eeprom_info,
288 .rtl819x_tx = rtl8192SU_tx,
289 .rtl819x_tx_cmd = rtl8192SU_tx_cmd,
290 .rtl819x_rx_nomal = rtl8192SU_rx_nomal,
291 .rtl819x_rx_cmd = rtl8192SU_rx_cmd,
292 .rtl819x_adapter_start = rtl8192SU_adapter_start,
293 .rtl819x_link_change = rtl8192SU_link_change,
294 .rtl819x_initial_gain = InitialGain8192S,
295 .rtl819x_query_rxdesc_status = rtl8192SU_query_rxdesc_status,
296};
297#else
298static void rtl8192_read_eeprom_info(struct net_device *dev);
299short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
300void rtl8192_rx_nomal(struct sk_buff* skb);
301void rtl8192_rx_cmd(struct sk_buff *skb);
302bool rtl8192_adapter_start(struct net_device *dev);
303short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
304void rtl8192_link_change(struct net_device *dev);
305void InitialGain819xUsb(struct net_device *dev,u8 Operation);
306void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
307
308struct rtl819x_ops rtl8192u_ops = {
309 .nic_type = NIC_8192U,
310 .rtl819x_read_eeprom_info = rtl8192_read_eeprom_info,
311 .rtl819x_tx = rtl8192_tx,
312 .rtl819x_tx_cmd = rtl819xU_tx_cmd,
313 .rtl819x_rx_nomal = rtl8192_rx_nomal,
314 .rtl819x_rx_cmd = rtl8192_rx_cmd,
315 .rtl819x_adapter_start = rtl8192_adapter_start,
316 .rtl819x_link_change = rtl8192_link_change,
317 .rtl819x_initial_gain = InitialGain819xUsb,
318 .rtl819x_query_rxdesc_status = query_rxdesc_status,
319};
320#endif
321
322#ifdef ENABLE_DOT11D
323
324typedef struct _CHANNEL_LIST
325{
326 u8 Channel[32];
327 u8 Len;
328}CHANNEL_LIST, *PCHANNEL_LIST;
329
330static CHANNEL_LIST ChannelPlan[] = {
331 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
332 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
333 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
334 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
335 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
336 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
337 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
338 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
339 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC
340 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC
341 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
342};
343
344static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
345{
346 int i, max_chan=-1, min_chan=-1;
347 struct ieee80211_device* ieee = priv->ieee80211;
348 switch (channel_plan)
349 {
350 case COUNTRY_CODE_FCC:
351 case COUNTRY_CODE_IC:
352 case COUNTRY_CODE_ETSI:
353 case COUNTRY_CODE_SPAIN:
354 case COUNTRY_CODE_FRANCE:
355 case COUNTRY_CODE_MKK:
356 case COUNTRY_CODE_MKK1:
357 case COUNTRY_CODE_ISRAEL:
358 case COUNTRY_CODE_TELEC:
359 case COUNTRY_CODE_MIC:
360 {
361 Dot11d_Init(ieee);
362 ieee->bGlobalDomain = false;
363 //acturally 8225 & 8256 rf chip only support B,G,24N mode
364 if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256) || (priv->rf_chip == RF_6052))
365 {
366 min_chan = 1;
367 max_chan = 14;
368 }
369 else
370 {
371 RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__);
372 }
373 if (ChannelPlan[channel_plan].Len != 0){
374 // Clear old channel map
375 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
376 // Set new channel map
377 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
378 {
379 if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan)
380 break;
381 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
382 }
383 }
384 break;
385 }
386 case COUNTRY_CODE_GLOBAL_DOMAIN:
387 {
388 GET_DOT11D_INFO(ieee)->bEnabled = 0;//this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain settings.
389 Dot11d_Reset(ieee);
390 ieee->bGlobalDomain = true;
391 break;
392 }
393 default:
394 break;
395 }
396 return;
397}
398#endif
399
400#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
401
402#ifdef RTL8192SU
403#define rx_hal_is_cck_rate(_pDesc)\
404 ((_pDesc->RxMCS == DESC92S_RATE1M ||\
405 _pDesc->RxMCS == DESC92S_RATE2M ||\
406 _pDesc->RxMCS == DESC92S_RATE5_5M ||\
407 _pDesc->RxMCS == DESC92S_RATE11M) &&\
408 !_pDesc->RxHT)
409
410#define tx_hal_is_cck_rate(_DataRate)\
411 ( _DataRate == MGN_1M ||\
412 _DataRate == MGN_2M ||\
413 _DataRate == MGN_5_5M ||\
414 _DataRate == MGN_11M )
415
416#else
417#define rx_hal_is_cck_rate(_pdrvinfo)\
418 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
419 _pdrvinfo->RxRate == DESC90_RATE2M ||\
420 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
421 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
422 !_pdrvinfo->RxHT)
423#endif
424
425
426
427void CamResetAllEntry(struct net_device *dev)
428{
429#if 1
430 u32 ulcommand = 0;
431 //2004/02/11 In static WEP, OID_ADD_KEY or OID_ADD_WEP are set before STA associate to AP.
432 // However, ResetKey is called on OID_802_11_INFRASTRUCTURE_MODE and MlmeAssociateRequest
433 // In this condition, Cam can not be reset because upper layer will not set this static key again.
434 //if(Adapter->EncAlgorithm == WEP_Encryption)
435 // return;
436//debug
437 //DbgPrint("========================================\n");
438 //DbgPrint(" Call ResetAllEntry \n");
439 //DbgPrint("========================================\n\n");
440 ulcommand |= BIT31|BIT30;
441 write_nic_dword(dev, RWCAM, ulcommand);
442#else
443 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
444 CAM_mark_invalid(dev, ucIndex);
445 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
446 CAM_empty_entry(dev, ucIndex);
447#endif
448
449}
450
451
452void write_cam(struct net_device *dev, u8 addr, u32 data)
453{
454 write_nic_dword(dev, WCAMI, data);
455 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
456}
457
458u32 read_cam(struct net_device *dev, u8 addr)
459{
460 write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
461 return read_nic_dword(dev, 0xa8);
462}
463
464void write_nic_byte_E(struct net_device *dev, int indx, u8 data)
465{
466 int status;
467 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
468 struct usb_device *udev = priv->udev;
469
470 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
471 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
472 indx|0xfe00, 0, &data, 1, HZ / 2);
473
474 if (status < 0)
475 {
476 printk("write_nic_byte_E TimeOut! status:%d\n", status);
477 }
478}
479
480u8 read_nic_byte_E(struct net_device *dev, int indx)
481{
482 int status;
483 u8 data;
484 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
485 struct usb_device *udev = priv->udev;
486
487 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
488 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
489 indx|0xfe00, 0, &data, 1, HZ / 2);
490
491 if (status < 0)
492 {
493 printk("read_nic_byte_E TimeOut! status:%d\n", status);
494 }
495
496 return data;
497}
498//as 92U has extend page from 4 to 16, so modify functions below.
499void write_nic_byte(struct net_device *dev, int indx, u8 data)
500{
501 int status;
502
503 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
504 struct usb_device *udev = priv->udev;
505
506 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
507 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
508#ifdef RTL8192SU
509 indx, 0, &data, 1, HZ / 2);
510#else
511 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
512#endif
513
514 if (status < 0)
515 {
516 printk("write_nic_byte TimeOut! status:%d\n", status);
517 }
518
519
520}
521
522
523void write_nic_word(struct net_device *dev, int indx, u16 data)
524{
525
526 int status;
527
528 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
529 struct usb_device *udev = priv->udev;
530
531 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
532 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
533#ifdef RTL8192SU
534 indx, 0, &data, 2, HZ / 2);
535#else
536 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
537#endif
538
539 if (status < 0)
540 {
541 printk("write_nic_word TimeOut! status:%d\n", status);
542 }
543
544}
545
546
547void write_nic_dword(struct net_device *dev, int indx, u32 data)
548{
549
550 int status;
551
552 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
553 struct usb_device *udev = priv->udev;
554
555 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
556 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
557#ifdef RTL8192SU
558 indx, 0, &data, 4, HZ / 2);
559#else
560 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
561#endif
562
563
564 if (status < 0)
565 {
566 printk("write_nic_dword TimeOut! status:%d\n", status);
567 }
568
569}
570
571
572
573u8 read_nic_byte(struct net_device *dev, int indx)
574{
575 u8 data;
576 int status;
577 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
578 struct usb_device *udev = priv->udev;
579
580 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
581 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
582#ifdef RTL8192SU
583 indx, 0, &data, 1, HZ / 2);
584#else
585 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2);
586#endif
587
588 if (status < 0)
589 {
590 printk("read_nic_byte TimeOut! status:%d\n", status);
591 }
592
593 return data;
594}
595
596
597
598u16 read_nic_word(struct net_device *dev, int indx)
599{
600 u16 data;
601 int status;
602 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
603 struct usb_device *udev = priv->udev;
604
605 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
606 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
607#ifdef RTL8192SU
608 indx, 0, &data, 2, HZ / 2);
609#else
610 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2);
611#endif
612
613 if (status < 0)
614 {
615 printk("read_nic_word TimeOut! status:%d\n", status);
616 }
617
618
619 return data;
620}
621
622u16 read_nic_word_E(struct net_device *dev, int indx)
623{
624 u16 data;
625 int status;
626 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
627 struct usb_device *udev = priv->udev;
628
629 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
630 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
631 indx|0xfe00, 0, &data, 2, HZ / 2);
632
633 if (status < 0)
634 {
635 printk("read_nic_word TimeOut! status:%d\n", status);
636 }
637
638
639 return data;
640}
641
642u32 read_nic_dword(struct net_device *dev, int indx)
643{
644 u32 data;
645 int status;
646// int result;
647
648 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
649 struct usb_device *udev = priv->udev;
650
651 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
652 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
653#ifdef RTL8192SU
654 indx, 0, &data, 4, HZ / 2);
655#else
656 (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2);
657#endif
658// if(0 != result) {
659// printk(KERN_WARNING "read size of data = %d\, date = %d\n", result, data);
660// }
661
662 if (status < 0)
663 {
664 printk("read_nic_dword TimeOut! status:%d\n", status);
665 if(status == -ENODEV) {
666 priv->usb_error = true;
667 }
668 }
669
670
671
672 return data;
673}
674
675
676//u8 read_phy_cck(struct net_device *dev, u8 adr);
677//u8 read_phy_ofdm(struct net_device *dev, u8 adr);
678/* this might still called in what was the PHY rtl8185/rtl8192 common code
679 * plans are to possibilty turn it again in one common code...
680 */
681inline void force_pci_posting(struct net_device *dev)
682{
683}
684
685
686static struct net_device_stats *rtl8192_stats(struct net_device *dev);
687void rtl8192_commit(struct net_device *dev);
688//void rtl8192_restart(struct net_device *dev);
689#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
690void rtl8192_restart(struct work_struct *work);
691//void rtl8192_rq_tx_ack(struct work_struct *work);
692#else
693 void rtl8192_restart(struct net_device *dev);
694// //void rtl8192_rq_tx_ack(struct net_device *dev);
695 #endif
696
697void watch_dog_timer_callback(unsigned long data);
698
699/****************************************************************************
700 -----------------------------PROCFS STUFF-------------------------
701*****************************************************************************/
702
703static struct proc_dir_entry *rtl8192_proc = NULL;
704
705
706
707static int proc_get_stats_ap(char *page, char **start,
708 off_t offset, int count,
709 int *eof, void *data)
710{
711 struct net_device *dev = data;
712 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
713 struct ieee80211_device *ieee = priv->ieee80211;
714 struct ieee80211_network *target;
715
716 int len = 0;
717
718 list_for_each_entry(target, &ieee->network_list, list) {
719
720 len += snprintf(page + len, count - len,
721 "%s ", target->ssid);
722
723 if(target->wpa_ie_len>0 || target->rsn_ie_len>0){
724 len += snprintf(page + len, count - len,
725 "WPA\n");
726 }
727 else{
728 len += snprintf(page + len, count - len,
729 "non_WPA\n");
730 }
731
732 }
733
734 *eof = 1;
735 return len;
736}
737
738#ifdef RTL8192SU
739static int proc_get_registers(char *page, char **start,
740 off_t offset, int count,
741 int *eof, void *data)
742{
743 struct net_device *dev = data;
744// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
745
746 int len = 0;
747 int i,n,page0,page1,page2;
748
749 int max=0xff;
750 page0 = 0x000;
751 page1 = 0x100;
752 page2 = 0x800;
753
754 /* This dump the current register page */
755 if(!IS_BB_REG_OFFSET_92S(page0)){
756 len += snprintf(page + len, count - len,
757 "\n####################page %x##################\n ", (page0>>8));
758 for(n=0;n<=max;)
759 {
760 len += snprintf(page + len, count - len,
761 "\nD: %2x > ",n);
762 for(i=0;i<16 && n<=max;i++,n++)
763 len += snprintf(page + len, count - len,
764 "%2.2x ",read_nic_byte(dev,(page0|n)));
765 }
766 }else{
767 len += snprintf(page + len, count - len,
768 "\n####################page %x##################\n ", (page0>>8));
769 for(n=0;n<=max;)
770 {
771 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
772 for(i=0;i<4 && n<=max;n+=4,i++)
773 len += snprintf(page + len, count - len,
774 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
775 }
776 }
777 len += snprintf(page + len, count - len,"\n");
778 *eof = 1;
779 return len;
780
781}
782static int proc_get_registers_1(char *page, char **start,
783 off_t offset, int count,
784 int *eof, void *data)
785{
786 struct net_device *dev = data;
787// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
788
789 int len = 0;
790 int i,n,page0;
791
792 int max=0xff;
793 page0 = 0x100;
794
795 /* This dump the current register page */
796 len += snprintf(page + len, count - len,
797 "\n####################page %x##################\n ", (page0>>8));
798 for(n=0;n<=max;)
799 {
800 len += snprintf(page + len, count - len,
801 "\nD: %2x > ",n);
802 for(i=0;i<16 && n<=max;i++,n++)
803 len += snprintf(page + len, count - len,
804 "%2.2x ",read_nic_byte(dev,(page0|n)));
805 }
806 len += snprintf(page + len, count - len,"\n");
807 *eof = 1;
808 return len;
809
810}
811static int proc_get_registers_2(char *page, char **start,
812 off_t offset, int count,
813 int *eof, void *data)
814{
815 struct net_device *dev = data;
816// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
817
818 int len = 0;
819 int i,n,page0;
820
821 int max=0xff;
822 page0 = 0x200;
823
824 /* This dump the current register page */
825 len += snprintf(page + len, count - len,
826 "\n####################page %x##################\n ", (page0>>8));
827 for(n=0;n<=max;)
828 {
829 len += snprintf(page + len, count - len,
830 "\nD: %2x > ",n);
831 for(i=0;i<16 && n<=max;i++,n++)
832 len += snprintf(page + len, count - len,
833 "%2.2x ",read_nic_byte(dev,(page0|n)));
834 }
835 len += snprintf(page + len, count - len,"\n");
836 *eof = 1;
837 return len;
838
839}
840static int proc_get_registers_8(char *page, char **start,
841 off_t offset, int count,
842 int *eof, void *data)
843{
844 struct net_device *dev = data;
845
846 int len = 0;
847 int i,n,page0;
848
849 int max=0xff;
850 page0 = 0x800;
851
852 /* This dump the current register page */
853 len += snprintf(page + len, count - len,
854 "\n####################page %x##################\n ", (page0>>8));
855 for(n=0;n<=max;)
856 {
857 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
858 for(i=0;i<4 && n<=max;n+=4,i++)
859 len += snprintf(page + len, count - len,
860 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
861 }
862 len += snprintf(page + len, count - len,"\n");
863 *eof = 1;
864 return len;
865
866 }
867static int proc_get_registers_9(char *page, char **start,
868 off_t offset, int count,
869 int *eof, void *data)
870{
871 struct net_device *dev = data;
872// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
873
874 int len = 0;
875 int i,n,page0;
876
877 int max=0xff;
878 page0 = 0x900;
879
880 /* This dump the current register page */
881 len += snprintf(page + len, count - len,
882 "\n####################page %x##################\n ", (page0>>8));
883 for(n=0;n<=max;)
884 {
885 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
886 for(i=0;i<4 && n<=max;n+=4,i++)
887 len += snprintf(page + len, count - len,
888 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
889 }
890 len += snprintf(page + len, count - len,"\n");
891 *eof = 1;
892 return len;
893}
894static int proc_get_registers_a(char *page, char **start,
895 off_t offset, int count,
896 int *eof, void *data)
897{
898 struct net_device *dev = data;
899// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
900
901 int len = 0;
902 int i,n,page0;
903
904 int max=0xff;
905 page0 = 0xa00;
906
907 /* This dump the current register page */
908 len += snprintf(page + len, count - len,
909 "\n####################page %x##################\n ", (page0>>8));
910 for(n=0;n<=max;)
911 {
912 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
913 for(i=0;i<4 && n<=max;n+=4,i++)
914 len += snprintf(page + len, count - len,
915 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
916 }
917 len += snprintf(page + len, count - len,"\n");
918 *eof = 1;
919 return len;
920}
921static int proc_get_registers_b(char *page, char **start,
922 off_t offset, int count,
923 int *eof, void *data)
924{
925 struct net_device *dev = data;
926// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
927
928 int len = 0;
929 int i,n,page0;
930
931 int max=0xff;
932 page0 = 0xb00;
933
934 /* This dump the current register page */
935 len += snprintf(page + len, count - len,
936 "\n####################page %x##################\n ", (page0>>8));
937 for(n=0;n<=max;)
938 {
939 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
940 for(i=0;i<4 && n<=max;n+=4,i++)
941 len += snprintf(page + len, count - len,
942 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
943 }
944 len += snprintf(page + len, count - len,"\n");
945 *eof = 1;
946 return len;
947 }
948static int proc_get_registers_c(char *page, char **start,
949 off_t offset, int count,
950 int *eof, void *data)
951{
952 struct net_device *dev = data;
953// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
954
955 int len = 0;
956 int i,n,page0;
957
958 int max=0xff;
959 page0 = 0xc00;
960
961 /* This dump the current register page */
962 len += snprintf(page + len, count - len,
963 "\n####################page %x##################\n ", (page0>>8));
964 for(n=0;n<=max;)
965 {
966 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
967 for(i=0;i<4 && n<=max;n+=4,i++)
968 len += snprintf(page + len, count - len,
969 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
970 }
971 len += snprintf(page + len, count - len,"\n");
972 *eof = 1;
973 return len;
974}
975static int proc_get_registers_d(char *page, char **start,
976 off_t offset, int count,
977 int *eof, void *data)
978{
979 struct net_device *dev = data;
980// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
981
982 int len = 0;
983 int i,n,page0;
984
985 int max=0xff;
986 page0 = 0xd00;
987
988 /* This dump the current register page */
989 len += snprintf(page + len, count - len,
990 "\n####################page %x##################\n ", (page0>>8));
991 for(n=0;n<=max;)
992 {
993 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
994 for(i=0;i<4 && n<=max;n+=4,i++)
995 len += snprintf(page + len, count - len,
996 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
997 }
998 len += snprintf(page + len, count - len,"\n");
999 *eof = 1;
1000 return len;
1001}
1002static int proc_get_registers_e(char *page, char **start,
1003 off_t offset, int count,
1004 int *eof, void *data)
1005{
1006 struct net_device *dev = data;
1007// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1008
1009 int len = 0;
1010 int i,n,page0;
1011
1012 int max=0xff;
1013 page0 = 0xe00;
1014
1015 /* This dump the current register page */
1016 len += snprintf(page + len, count - len,
1017 "\n####################page %x##################\n ", (page0>>8));
1018 for(n=0;n<=max;)
1019 {
1020 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
1021 for(i=0;i<4 && n<=max;n+=4,i++)
1022 len += snprintf(page + len, count - len,
1023 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
1024 }
1025 len += snprintf(page + len, count - len,"\n");
1026 *eof = 1;
1027 return len;
1028}
1029#else
1030static int proc_get_registers(char *page, char **start,
1031 off_t offset, int count,
1032 int *eof, void *data)
1033{
1034 struct net_device *dev = data;
1035// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1036
1037 int len = 0;
1038 int i,n;
1039
1040 int max=0xff;
1041
1042 /* This dump the current register page */
1043len += snprintf(page + len, count - len,
1044 "\n####################page 0##################\n ");
1045
1046 for(n=0;n<=max;)
1047 {
1048 //printk( "\nD: %2x> ", n);
1049 len += snprintf(page + len, count - len,
1050 "\nD: %2x > ",n);
1051
1052 for(i=0;i<16 && n<=max;i++,n++)
1053 len += snprintf(page + len, count - len,
1054 "%2x ",read_nic_byte(dev,0x000|n));
1055
1056 // printk("%2x ",read_nic_byte(dev,n));
1057 }
1058#if 1
1059len += snprintf(page + len, count - len,
1060 "\n####################page 1##################\n ");
1061 for(n=0;n<=max;)
1062 {
1063 //printk( "\nD: %2x> ", n);
1064 len += snprintf(page + len, count - len,
1065 "\nD: %2x > ",n);
1066
1067 for(i=0;i<16 && n<=max;i++,n++)
1068 len += snprintf(page + len, count - len,
1069 "%2x ",read_nic_byte(dev,0x100|n));
1070
1071 // printk("%2x ",read_nic_byte(dev,n));
1072 }
1073len += snprintf(page + len, count - len,
1074 "\n####################page 3##################\n ");
1075 for(n=0;n<=max;)
1076 {
1077 //printk( "\nD: %2x> ", n);
1078 len += snprintf(page + len, count - len,
1079 "\nD: %2x > ",n);
1080
1081 for(i=0;i<16 && n<=max;i++,n++)
1082 len += snprintf(page + len, count - len,
1083 "%2x ",read_nic_byte(dev,0x300|n));
1084
1085 // printk("%2x ",read_nic_byte(dev,n));
1086 }
1087
1088#endif
1089
1090 len += snprintf(page + len, count - len,"\n");
1091 *eof = 1;
1092 return len;
1093
1094}
1095#endif
1096
1097#if 0
1098static int proc_get_cck_reg(char *page, char **start,
1099 off_t offset, int count,
1100 int *eof, void *data)
1101{
1102 struct net_device *dev = data;
1103// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1104
1105 int len = 0;
1106 int i,n;
1107
1108 int max = 0x5F;
1109
1110 /* This dump the current register page */
1111 for(n=0;n<=max;)
1112 {
1113 //printk( "\nD: %2x> ", n);
1114 len += snprintf(page + len, count - len,
1115 "\nD: %2x > ",n);
1116
1117 for(i=0;i<16 && n<=max;i++,n++)
1118 len += snprintf(page + len, count - len,
1119 "%2x ",read_phy_cck(dev,n));
1120
1121 // printk("%2x ",read_nic_byte(dev,n));
1122 }
1123 len += snprintf(page + len, count - len,"\n");
1124
1125
1126 *eof = 1;
1127 return len;
1128}
1129
1130#endif
1131
1132#if 0
1133static int proc_get_ofdm_reg(char *page, char **start,
1134 off_t offset, int count,
1135 int *eof, void *data)
1136{
1137 struct net_device *dev = data;
1138// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1139
1140 int len = 0;
1141 int i,n;
1142
1143 //int max=0xff;
1144 int max = 0x40;
1145
1146 /* This dump the current register page */
1147 for(n=0;n<=max;)
1148 {
1149 //printk( "\nD: %2x> ", n);
1150 len += snprintf(page + len, count - len,
1151 "\nD: %2x > ",n);
1152
1153 for(i=0;i<16 && n<=max;i++,n++)
1154 len += snprintf(page + len, count - len,
1155 "%2x ",read_phy_ofdm(dev,n));
1156
1157 // printk("%2x ",read_nic_byte(dev,n));
1158 }
1159 len += snprintf(page + len, count - len,"\n");
1160
1161
1162
1163 *eof = 1;
1164 return len;
1165}
1166
1167#endif
1168
1169#if 0
1170static int proc_get_stats_hw(char *page, char **start,
1171 off_t offset, int count,
1172 int *eof, void *data)
1173{
1174 struct net_device *dev = data;
1175 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1176
1177 int len = 0;
1178
1179 len += snprintf(page + len, count - len,
1180 "NIC int: %lu\n"
1181 "Total int: %lu\n",
1182 priv->stats.ints,
1183 priv->stats.shints);
1184
1185 *eof = 1;
1186 return len;
1187}
1188#endif
1189
1190static int proc_get_stats_tx(char *page, char **start,
1191 off_t offset, int count,
1192 int *eof, void *data)
1193{
1194 struct net_device *dev = data;
1195 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1196
1197 int len = 0;
1198
1199 len += snprintf(page + len, count - len,
1200 "TX VI priority ok int: %lu\n"
1201 "TX VI priority error int: %lu\n"
1202 "TX VO priority ok int: %lu\n"
1203 "TX VO priority error int: %lu\n"
1204 "TX BE priority ok int: %lu\n"
1205 "TX BE priority error int: %lu\n"
1206 "TX BK priority ok int: %lu\n"
1207 "TX BK priority error int: %lu\n"
1208 "TX MANAGE priority ok int: %lu\n"
1209 "TX MANAGE priority error int: %lu\n"
1210 "TX BEACON priority ok int: %lu\n"
1211 "TX BEACON priority error int: %lu\n"
1212// "TX high priority ok int: %lu\n"
1213// "TX high priority failed error int: %lu\n"
1214 "TX queue resume: %lu\n"
1215 "TX queue stopped?: %d\n"
1216 "TX fifo overflow: %lu\n"
1217// "TX beacon: %lu\n"
1218 "TX VI queue: %d\n"
1219 "TX VO queue: %d\n"
1220 "TX BE queue: %d\n"
1221 "TX BK queue: %d\n"
1222// "TX HW queue: %d\n"
1223 "TX VI dropped: %lu\n"
1224 "TX VO dropped: %lu\n"
1225 "TX BE dropped: %lu\n"
1226 "TX BK dropped: %lu\n"
1227 "TX total data packets %lu\n",
1228// "TX beacon aborted: %lu\n",
1229 priv->stats.txviokint,
1230 priv->stats.txvierr,
1231 priv->stats.txvookint,
1232 priv->stats.txvoerr,
1233 priv->stats.txbeokint,
1234 priv->stats.txbeerr,
1235 priv->stats.txbkokint,
1236 priv->stats.txbkerr,
1237 priv->stats.txmanageokint,
1238 priv->stats.txmanageerr,
1239 priv->stats.txbeaconokint,
1240 priv->stats.txbeaconerr,
1241// priv->stats.txhpokint,
1242// priv->stats.txhperr,
1243 priv->stats.txresumed,
1244 netif_queue_stopped(dev),
1245 priv->stats.txoverflow,
1246// priv->stats.txbeacon,
1247 atomic_read(&(priv->tx_pending[VI_PRIORITY])),
1248 atomic_read(&(priv->tx_pending[VO_PRIORITY])),
1249 atomic_read(&(priv->tx_pending[BE_PRIORITY])),
1250 atomic_read(&(priv->tx_pending[BK_PRIORITY])),
1251// read_nic_byte(dev, TXFIFOCOUNT),
1252 priv->stats.txvidrop,
1253 priv->stats.txvodrop,
1254 priv->stats.txbedrop,
1255 priv->stats.txbkdrop,
1256 priv->stats.txdatapkt
1257// priv->stats.txbeaconerr
1258 );
1259
1260 *eof = 1;
1261 return len;
1262}
1263
1264
1265
1266static int proc_get_stats_rx(char *page, char **start,
1267 off_t offset, int count,
1268 int *eof, void *data)
1269{
1270 struct net_device *dev = data;
1271 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1272
1273 int len = 0;
1274
1275 len += snprintf(page + len, count - len,
1276 "RX packets: %lu\n"
1277 "RX urb status error: %lu\n"
1278 "RX invalid urb error: %lu\n",
1279 priv->stats.rxoktotal,
1280 priv->stats.rxstaterr,
1281 priv->stats.rxurberr);
1282
1283 *eof = 1;
1284 return len;
1285}
1286#if 0
1287#if WIRELESS_EXT >= 12 && WIRELESS_EXT < 17
1288
1289static struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev)
1290{
1291 struct r8192_priv *priv = ieee80211_priv(dev);
1292
1293 return &priv->wstats;
1294}
1295#endif
1296#endif
1297void rtl8192_proc_module_init(void)
1298{
1299 RT_TRACE(COMP_INIT, "Initializing proc filesystem");
1300#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
1301 rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, proc_net);
1302#else
1303 rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, init_net.proc_net);
1304#endif
1305}
1306
1307
1308void rtl8192_proc_module_remove(void)
1309{
1310#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
1311 remove_proc_entry(RTL819xU_MODULE_NAME, proc_net);
1312#else
1313 remove_proc_entry(RTL819xU_MODULE_NAME, init_net.proc_net);
1314#endif
1315}
1316
1317
1318void rtl8192_proc_remove_one(struct net_device *dev)
1319{
1320 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1321
1322
1323 if (priv->dir_dev) {
1324 // remove_proc_entry("stats-hw", priv->dir_dev);
1325 remove_proc_entry("stats-tx", priv->dir_dev);
1326 remove_proc_entry("stats-rx", priv->dir_dev);
1327 // remove_proc_entry("stats-ieee", priv->dir_dev);
1328 remove_proc_entry("stats-ap", priv->dir_dev);
1329 remove_proc_entry("registers", priv->dir_dev);
1330 remove_proc_entry("registers-1", priv->dir_dev);
1331 remove_proc_entry("registers-2", priv->dir_dev);
1332 remove_proc_entry("registers-8", priv->dir_dev);
1333 remove_proc_entry("registers-9", priv->dir_dev);
1334 remove_proc_entry("registers-a", priv->dir_dev);
1335 remove_proc_entry("registers-b", priv->dir_dev);
1336 remove_proc_entry("registers-c", priv->dir_dev);
1337 remove_proc_entry("registers-d", priv->dir_dev);
1338 remove_proc_entry("registers-e", priv->dir_dev);
1339 // remove_proc_entry("cck-registers",priv->dir_dev);
1340 // remove_proc_entry("ofdm-registers",priv->dir_dev);
1341 //remove_proc_entry(dev->name, rtl8192_proc);
1342 remove_proc_entry("wlan0", rtl8192_proc);
1343 priv->dir_dev = NULL;
1344 }
1345}
1346
1347
1348void rtl8192_proc_init_one(struct net_device *dev)
1349{
1350 struct proc_dir_entry *e;
1351 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1352 priv->dir_dev = create_proc_entry(dev->name,
1353 S_IFDIR | S_IRUGO | S_IXUGO,
1354 rtl8192_proc);
1355 if (!priv->dir_dev) {
1356 RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n",
1357 dev->name);
1358 return;
1359 }
1360 #if 0
1361 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
1362 priv->dir_dev, proc_get_stats_hw, dev);
1363
1364 if (!e) {
1365 DMESGE("Unable to initialize "
1366 "/proc/net/rtl8192/%s/stats-hw\n",
1367 dev->name);
1368 }
1369 #endif
1370 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
1371 priv->dir_dev, proc_get_stats_rx, dev);
1372
1373 if (!e) {
1374 RT_TRACE(COMP_ERR,"Unable to initialize "
1375 "/proc/net/rtl8192/%s/stats-rx\n",
1376 dev->name);
1377 }
1378
1379
1380 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
1381 priv->dir_dev, proc_get_stats_tx, dev);
1382
1383 if (!e) {
1384 RT_TRACE(COMP_ERR, "Unable to initialize "
1385 "/proc/net/rtl8192/%s/stats-tx\n",
1386 dev->name);
1387 }
1388 #if 0
1389 e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO,
1390 priv->dir_dev, proc_get_stats_ieee, dev);
1391
1392 if (!e) {
1393 DMESGE("Unable to initialize "
1394 "/proc/net/rtl8192/%s/stats-ieee\n",
1395 dev->name);
1396 }
1397
1398 #endif
1399
1400 e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO,
1401 priv->dir_dev, proc_get_stats_ap, dev);
1402
1403 if (!e) {
1404 RT_TRACE(COMP_ERR, "Unable to initialize "
1405 "/proc/net/rtl8192/%s/stats-ap\n",
1406 dev->name);
1407 }
1408
1409 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
1410 priv->dir_dev, proc_get_registers, dev);
1411 if (!e) {
1412 RT_TRACE(COMP_ERR, "Unable to initialize "
1413 "/proc/net/rtl8192/%s/registers\n",
1414 dev->name);
1415 }
1416#ifdef RTL8192SU
1417 e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO,
1418 priv->dir_dev, proc_get_registers_1, dev);
1419 if (!e) {
1420 RT_TRACE(COMP_ERR, "Unable to initialize "
1421 "/proc/net/rtl8192/%s/registers-1\n",
1422 dev->name);
1423 }
1424 e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO,
1425 priv->dir_dev, proc_get_registers_2, dev);
1426 if (!e) {
1427 RT_TRACE(COMP_ERR, "Unable to initialize "
1428 "/proc/net/rtl8192/%s/registers-2\n",
1429 dev->name);
1430 }
1431 e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO,
1432 priv->dir_dev, proc_get_registers_8, dev);
1433 if (!e) {
1434 RT_TRACE(COMP_ERR, "Unable to initialize "
1435 "/proc/net/rtl8192/%s/registers-8\n",
1436 dev->name);
1437 }
1438 e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO,
1439 priv->dir_dev, proc_get_registers_9, dev);
1440 if (!e) {
1441 RT_TRACE(COMP_ERR, "Unable to initialize "
1442 "/proc/net/rtl8192/%s/registers-9\n",
1443 dev->name);
1444 }
1445 e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO,
1446 priv->dir_dev, proc_get_registers_a, dev);
1447 if (!e) {
1448 RT_TRACE(COMP_ERR, "Unable to initialize "
1449 "/proc/net/rtl8192/%s/registers-a\n",
1450 dev->name);
1451 }
1452 e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO,
1453 priv->dir_dev, proc_get_registers_b, dev);
1454 if (!e) {
1455 RT_TRACE(COMP_ERR, "Unable to initialize "
1456 "/proc/net/rtl8192/%s/registers-b\n",
1457 dev->name);
1458 }
1459 e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO,
1460 priv->dir_dev, proc_get_registers_c, dev);
1461 if (!e) {
1462 RT_TRACE(COMP_ERR, "Unable to initialize "
1463 "/proc/net/rtl8192/%s/registers-c\n",
1464 dev->name);
1465 }
1466 e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO,
1467 priv->dir_dev, proc_get_registers_d, dev);
1468 if (!e) {
1469 RT_TRACE(COMP_ERR, "Unable to initialize "
1470 "/proc/net/rtl8192/%s/registers-d\n",
1471 dev->name);
1472 }
1473 e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO,
1474 priv->dir_dev, proc_get_registers_e, dev);
1475 if (!e) {
1476 RT_TRACE(COMP_ERR, "Unable to initialize "
1477 "/proc/net/rtl8192/%s/registers-e\n",
1478 dev->name);
1479 }
1480#endif
1481#if 0
1482 e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO,
1483 priv->dir_dev, proc_get_cck_reg, dev);
1484 if (!e) {
1485 RT_TRACE(COMP_ERR, "Unable to initialize "
1486 "/proc/net/rtl8192/%s/cck-registers\n",
1487 dev->name);
1488 }
1489
1490 e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO,
1491 priv->dir_dev, proc_get_ofdm_reg, dev);
1492 if (!e) {
1493 RT_TRACE(COMP_ERR, "Unable to initialize "
1494 "/proc/net/rtl8192/%s/ofdm-registers\n",
1495 dev->name);
1496 }
1497#endif
1498}
1499/****************************************************************************
1500 -----------------------------MISC STUFF-------------------------
1501*****************************************************************************/
1502
1503/* this is only for debugging */
1504void print_buffer(u32 *buffer, int len)
1505{
1506 int i;
1507 u8 *buf =(u8*)buffer;
1508
1509 printk("ASCII BUFFER DUMP (len: %x):\n",len);
1510
1511 for(i=0;i<len;i++)
1512 printk("%c",buf[i]);
1513
1514 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
1515
1516 for(i=0;i<len;i++)
1517 printk("%x",buf[i]);
1518
1519 printk("\n");
1520}
1521
1522//short check_nic_enough_desc(struct net_device *dev, priority_t priority)
1523short check_nic_enough_desc(struct net_device *dev,int queue_index)
1524{
1525 struct r8192_priv *priv = ieee80211_priv(dev);
1526 int used = atomic_read(&priv->tx_pending[queue_index]);
1527
1528 return (used < MAX_TX_URB);
1529}
1530
1531void tx_timeout(struct net_device *dev)
1532{
1533 struct r8192_priv *priv = ieee80211_priv(dev);
1534 //rtl8192_commit(dev);
1535
1536#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
1537 schedule_work(&priv->reset_wq);
1538#else
1539 schedule_task(&priv->reset_wq);
1540#endif
1541 //DMESG("TXTIMEOUT");
1542}
1543
1544
1545/* this is only for debug */
1546void dump_eprom(struct net_device *dev)
1547{
1548 int i;
1549 for(i=0; i<63; i++)
1550 RT_TRACE(COMP_EPROM, "EEPROM addr %x : %x", i, eprom_read(dev,i));
1551}
1552
1553/* this is only for debug */
1554void rtl8192_dump_reg(struct net_device *dev)
1555{
1556 int i;
1557 int n;
1558 int max=0x1ff;
1559
1560 RT_TRACE(COMP_PHY, "Dumping NIC register map");
1561
1562 for(n=0;n<=max;)
1563 {
1564 printk( "\nD: %2x> ", n);
1565 for(i=0;i<16 && n<=max;i++,n++)
1566 printk("%2x ",read_nic_byte(dev,n));
1567 }
1568 printk("\n");
1569}
1570
1571/****************************************************************************
1572 ------------------------------HW STUFF---------------------------
1573*****************************************************************************/
1574
1575#if 0
1576void rtl8192_irq_enable(struct net_device *dev)
1577{
1578 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1579 //priv->irq_enabled = 1;
1580/*
1581 write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\
1582 INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\
1583 INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\
1584 INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT);
1585*/
1586 write_nic_word(dev,INTA_MASK, priv->irq_mask);
1587}
1588
1589
1590void rtl8192_irq_disable(struct net_device *dev)
1591{
1592// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1593
1594 write_nic_word(dev,INTA_MASK,0);
1595 force_pci_posting(dev);
1596// priv->irq_enabled = 0;
1597}
1598#endif
1599
1600void rtl8192_set_mode(struct net_device *dev,int mode)
1601{
1602 u8 ecmd;
1603 ecmd=read_nic_byte(dev, EPROM_CMD);
1604 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
1605 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
1606 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
1607 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
1608 write_nic_byte(dev, EPROM_CMD, ecmd);
1609}
1610
1611
1612void rtl8192_update_msr(struct net_device *dev)
1613{
1614 struct r8192_priv *priv = ieee80211_priv(dev);
1615 u8 msr;
1616
1617 msr = read_nic_byte(dev, MSR);
1618 msr &= ~ MSR_LINK_MASK;
1619
1620 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
1621 * msr must be updated if the state is ASSOCIATING.
1622 * this is intentional and make sense for ad-hoc and
1623 * master (see the create BSS/IBSS func)
1624 */
1625 if (priv->ieee80211->state == IEEE80211_LINKED){
1626
1627 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
1628 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
1629 else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1630 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
1631 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
1632 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
1633
1634 }else
1635 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
1636
1637 write_nic_byte(dev, MSR, msr);
1638}
1639
1640void rtl8192_set_chan(struct net_device *dev,short ch)
1641{
1642 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1643// u32 tx;
1644 RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __FUNCTION__, ch);
1645 //printk("=====>%s()====ch:%d\n", __FUNCTION__, ch);
1646 priv->chan=ch;
1647 #if 0
1648 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC ||
1649 priv->ieee80211->iw_mode == IW_MODE_MASTER){
1650
1651 priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED;
1652 priv->ieee80211->master_chan = ch;
1653 rtl8192_update_beacon_ch(dev);
1654 }
1655 #endif
1656
1657 /* this hack should avoid frame TX during channel setting*/
1658
1659
1660// tx = read_nic_dword(dev,TX_CONF);
1661// tx &= ~TX_LOOPBACK_MASK;
1662
1663#ifndef LOOP_TEST
1664// write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<<TX_LOOPBACK_SHIFT));
1665
1666 //need to implement rf set channel here WB
1667
1668 if (priv->rf_set_chan)
1669 priv->rf_set_chan(dev,priv->chan);
1670 mdelay(10);
1671// write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT));
1672#endif
1673}
1674
1675#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
1676static void rtl8192_rx_isr(struct urb *urb, struct pt_regs *regs);
1677#else
1678static void rtl8192_rx_isr(struct urb *urb);
1679#endif
1680//static void rtl8192_rx_isr(struct urb *rx_urb);
1681
1682u32 get_rxpacket_shiftbytes_819xusb(struct ieee80211_rx_stats *pstats)
1683{
1684
1685#ifdef USB_RX_AGGREGATION_SUPPORT
1686 if (pstats->bisrxaggrsubframe)
1687 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1688 + pstats->RxBufShift + 8);
1689 else
1690#endif
1691 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1692 + pstats->RxBufShift);
1693
1694}
1695static int rtl8192_rx_initiate(struct net_device*dev)
1696{
1697 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1698 struct urb *entry;
1699 struct sk_buff *skb;
1700 struct rtl8192_rx_info *info;
1701
1702 /* nomal packet rx procedure */
1703 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB) {
1704 skb = __dev_alloc_skb(RX_URB_SIZE, GFP_KERNEL);
1705 if (!skb)
1706 break;
1707#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1708 entry = usb_alloc_urb(0, GFP_KERNEL);
1709#else
1710 entry = usb_alloc_urb(0);
1711#endif
1712 if (!entry) {
1713 kfree_skb(skb);
1714 break;
1715 }
1716// printk("nomal packet IN request!\n");
1717 usb_fill_bulk_urb(entry, priv->udev,
1718 usb_rcvbulkpipe(priv->udev, 3), skb->tail,
1719 RX_URB_SIZE, rtl8192_rx_isr, skb);
1720 info = (struct rtl8192_rx_info *) skb->cb;
1721 info->urb = entry;
1722 info->dev = dev;
1723 info->out_pipe = 3; //denote rx normal packet queue
1724 skb_queue_tail(&priv->rx_queue, skb);
1725#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1726 usb_submit_urb(entry, GFP_KERNEL);
1727#else
1728 usb_submit_urb(entry);
1729#endif
1730 }
1731
1732 /* command packet rx procedure */
1733 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB + 3) {
1734// printk("command packet IN request!\n");
1735 skb = __dev_alloc_skb(RX_URB_SIZE ,GFP_KERNEL);
1736 if (!skb)
1737 break;
1738#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1739 entry = usb_alloc_urb(0, GFP_KERNEL);
1740#else
1741 entry = usb_alloc_urb(0);
1742#endif
1743 if (!entry) {
1744 kfree_skb(skb);
1745 break;
1746 }
1747 usb_fill_bulk_urb(entry, priv->udev,
1748 usb_rcvbulkpipe(priv->udev, 9), skb->tail,
1749 RX_URB_SIZE, rtl8192_rx_isr, skb);
1750 info = (struct rtl8192_rx_info *) skb->cb;
1751 info->urb = entry;
1752 info->dev = dev;
1753 info->out_pipe = 9; //denote rx cmd packet queue
1754 skb_queue_tail(&priv->rx_queue, skb);
1755#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1756 usb_submit_urb(entry, GFP_KERNEL);
1757#else
1758 usb_submit_urb(entry);
1759#endif
1760 }
1761
1762 return 0;
1763}
1764
1765void rtl8192_set_rxconf(struct net_device *dev)
1766{
1767 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1768 u32 rxconf;
1769
1770 rxconf=read_nic_dword(dev,RCR);
1771 rxconf = rxconf &~ MAC_FILTER_MASK;
1772 rxconf = rxconf | RCR_AMF;
1773 rxconf = rxconf | RCR_ADF;
1774 rxconf = rxconf | RCR_AB;
1775 rxconf = rxconf | RCR_AM;
1776 //rxconf = rxconf | RCR_ACF;
1777
1778 if (dev->flags & IFF_PROMISC) {DMESG ("NIC in promisc mode");}
1779
1780 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1781 dev->flags & IFF_PROMISC){
1782 rxconf = rxconf | RCR_AAP;
1783 } /*else if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
1784 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
1785 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
1786 }*/else{
1787 rxconf = rxconf | RCR_APM;
1788 rxconf = rxconf | RCR_CBSSID;
1789 }
1790
1791
1792 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1793 rxconf = rxconf | RCR_AICV;
1794 rxconf = rxconf | RCR_APWRMGT;
1795 }
1796
1797 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1798 rxconf = rxconf | RCR_ACRC32;
1799
1800
1801 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
1802 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
1803 rxconf = rxconf &~ MAX_RX_DMA_MASK;
1804 rxconf = rxconf | ((u32)7<<RCR_MXDMA_OFFSET);
1805
1806// rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
1807 rxconf = rxconf | RCR_ONLYERLPKT;
1808
1809// rxconf = rxconf &~ RCR_CS_MASK;
1810// rxconf = rxconf | (1<<RCR_CS_SHIFT);
1811
1812 write_nic_dword(dev, RCR, rxconf);
1813
1814 #ifdef DEBUG_RX
1815 DMESG("rxconf: %x %x",rxconf ,read_nic_dword(dev,RCR));
1816 #endif
1817}
1818//wait to be removed
1819void rtl8192_rx_enable(struct net_device *dev)
1820{
1821 //u8 cmd;
1822
1823 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1824
1825 rtl8192_rx_initiate(dev);
1826
1827// rtl8192_set_rxconf(dev);
1828#if 0
1829 if(NIC_8187 == priv->card_8187) {
1830 cmd=read_nic_byte(dev,CMD);
1831 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1832 }
1833 else {
1834 //write_nic_dword(dev, RX_CONF, priv->ReceiveConfig);
1835 }
1836#endif
1837}
1838
1839
1840void rtl8192_tx_enable(struct net_device *dev)
1841{
1842#if 0
1843 u8 cmd;
1844 u8 byte;
1845 u32 txconf;
1846 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1847 //test loopback
1848 // priv->TransmitConfig |= (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1849 if(NIC_8187B == priv->card_8187){
1850 write_nic_dword(dev, TX_CONF, priv->TransmitConfig);
1851 byte = read_nic_byte(dev, MSR);
1852 byte |= MSR_LINK_ENEDCA;
1853 write_nic_byte(dev, MSR, byte);
1854 } else {
1855 byte = read_nic_byte(dev,CW_CONF);
1856 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
1857 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
1858 write_nic_byte(dev, CW_CONF, byte);
1859
1860 byte = read_nic_byte(dev, TX_AGC_CTL);
1861 byte &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
1862 byte &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
1863 byte &= ~(1<<TX_AGC_CTL_FEEDBACK_ANT);
1864 write_nic_byte(dev, TX_AGC_CTL, byte);
1865
1866 txconf= read_nic_dword(dev,TX_CONF);
1867
1868
1869 txconf = txconf &~ TX_LOOPBACK_MASK;
1870
1871#ifndef LOOP_TEST
1872 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
1873#else
1874 txconf = txconf | (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1875#endif
1876 txconf = txconf &~ TCR_SRL_MASK;
1877 txconf = txconf &~ TCR_LRL_MASK;
1878
1879 txconf = txconf | (priv->retry_data<<TX_LRLRETRY_SHIFT); // long
1880 txconf = txconf | (priv->retry_rts<<TX_SRLRETRY_SHIFT); // short
1881
1882 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
1883
1884 txconf = txconf &~ TCR_MXDMA_MASK;
1885 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
1886
1887 txconf = txconf | TCR_DISReqQsize;
1888 txconf = txconf | TCR_DISCW;
1889 txconf = txconf &~ TCR_SWPLCPLEN;
1890
1891 txconf=txconf | (1<<TX_NOICV_SHIFT);
1892
1893 write_nic_dword(dev,TX_CONF,txconf);
1894
1895#ifdef DEBUG_TX
1896 DMESG("txconf: %x %x",txconf,read_nic_dword(dev,TX_CONF));
1897#endif
1898
1899 cmd=read_nic_byte(dev,CMD);
1900 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1901 }
1902#endif
1903}
1904
1905#if 0
1906void rtl8192_beacon_tx_enable(struct net_device *dev)
1907{
1908 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1909 priv->dma_poll_mask &=~(1<<TX_DMA_STOP_BEACON_SHIFT);
1910 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1911 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1912 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1913}
1914
1915
1916void rtl8192_
1917_disable(struct net_device *dev)
1918{
1919 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1920 priv->dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
1921 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1922 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1923 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1924}
1925
1926#endif
1927
1928
1929void rtl8192_rtx_disable(struct net_device *dev)
1930{
1931 u8 cmd;
1932 struct r8192_priv *priv = ieee80211_priv(dev);
1933 struct sk_buff *skb;
1934 struct rtl8192_rx_info *info;
1935
1936 cmd=read_nic_byte(dev,CMDR);
1937 write_nic_byte(dev, CMDR, cmd &~ \
1938 (CR_TE|CR_RE));
1939 force_pci_posting(dev);
1940 mdelay(10);
1941
1942 while ((skb = __skb_dequeue(&priv->rx_queue))) {
1943 info = (struct rtl8192_rx_info *) skb->cb;
1944 if (!info->urb)
1945 continue;
1946
1947 usb_kill_urb(info->urb);
1948 kfree_skb(skb);
1949 }
1950
1951 if (skb_queue_len(&priv->skb_queue)) {
1952 printk(KERN_WARNING "skb_queue not empty\n");
1953 }
1954
1955 skb_queue_purge(&priv->skb_queue);
1956 return;
1957}
1958
1959
1960int alloc_tx_beacon_desc_ring(struct net_device *dev, int count)
1961{
1962 #if 0
1963 int i;
1964 u32 *tmp;
1965 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1966
1967 priv->txbeaconring = (u32*)pci_alloc_consistent(priv->pdev,
1968 sizeof(u32)*8*count,
1969 &priv->txbeaconringdma);
1970 if (!priv->txbeaconring) return -1;
1971 for (tmp=priv->txbeaconring,i=0;i<count;i++){
1972 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1973 /*
1974 *(tmp+2) = (u32)dma_tmp;
1975 *(tmp+3) = bufsize;
1976 */
1977 if(i+1<count)
1978 *(tmp+4) = (u32)priv->txbeaconringdma+((i+1)*8*4);
1979 else
1980 *(tmp+4) = (u32)priv->txbeaconringdma;
1981
1982 tmp=tmp+8;
1983 }
1984 #endif
1985 return 0;
1986}
1987
1988#if 0
1989void rtl8192_reset(struct net_device *dev)
1990{
1991
1992 //struct r8192_priv *priv = ieee80211_priv(dev);
1993 //u8 cr;
1994
1995
1996 /* make sure the analog power is on before
1997 * reset, otherwise reset may fail
1998 */
1999#if 0
2000 if(NIC_8187 == priv->card_8187) {
2001 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
2002 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
2003 rtl8192_irq_disable(dev);
2004 mdelay(200);
2005 write_nic_byte_E(dev,0x18,0x10);
2006 write_nic_byte_E(dev,0x18,0x11);
2007 write_nic_byte_E(dev,0x18,0x00);
2008 mdelay(200);
2009 }
2010#endif
2011 printk("=====>reset?\n");
2012#if 0
2013 cr=read_nic_byte(dev,CMD);
2014 cr = cr & 2;
2015 cr = cr | (1<<CMD_RST_SHIFT);
2016 write_nic_byte(dev,CMD,cr);
2017
2018 force_pci_posting(dev);
2019
2020 mdelay(200);
2021
2022 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
2023 RT_TRACE(COMP_ERR, "Card reset timeout!\n");
2024 else
2025 RT_TRACE(COMP_DOWN, "Card successfully reset\n");
2026#endif
2027#if 0
2028 if(NIC_8187 == priv->card_8187) {
2029
2030 printk("This is RTL8187 Reset procedure\n");
2031 rtl8192_set_mode(dev,EPROM_CMD_LOAD);
2032 force_pci_posting(dev);
2033 mdelay(200);
2034
2035 /* after the eeprom load cycle, make sure we have
2036 * correct anaparams
2037 */
2038 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
2039 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
2040 }
2041 else
2042#endif
2043 printk("This is RTL8187B Reset procedure\n");
2044
2045}
2046#endif
2047inline u16 ieeerate2rtlrate(int rate)
2048{
2049 switch(rate){
2050 case 10:
2051 return 0;
2052 case 20:
2053 return 1;
2054 case 55:
2055 return 2;
2056 case 110:
2057 return 3;
2058 case 60:
2059 return 4;
2060 case 90:
2061 return 5;
2062 case 120:
2063 return 6;
2064 case 180:
2065 return 7;
2066 case 240:
2067 return 8;
2068 case 360:
2069 return 9;
2070 case 480:
2071 return 10;
2072 case 540:
2073 return 11;
2074 default:
2075 return 3;
2076
2077 }
2078}
2079static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540};
2080inline u16 rtl8192_rate2rate(short rate)
2081{
2082 if (rate >11) return 0;
2083 return rtl_rate[rate];
2084}
2085
2086
2087/* The protype of rx_isr has changed since one verion of Linux Kernel */
2088#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
2089static void rtl8192_rx_isr(struct urb *urb, struct pt_regs *regs)
2090#else
2091static void rtl8192_rx_isr(struct urb *urb)
2092#endif
2093{
2094 struct sk_buff *skb = (struct sk_buff *) urb->context;
2095 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
2096 struct net_device *dev = info->dev;
2097 struct r8192_priv *priv = ieee80211_priv(dev);
2098 int out_pipe = info->out_pipe;
2099 int err;
2100 if(!priv->up)
2101 return;
2102 if (unlikely(urb->status)) {
2103 info->urb = NULL;
2104 priv->stats.rxstaterr++;
2105 priv->ieee80211->stats.rx_errors++;
2106 usb_free_urb(urb);
2107 // printk("%s():rx status err\n",__FUNCTION__);
2108 return;
2109 }
2110#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)
2111 skb_unlink(skb, &priv->rx_queue);
2112#else
2113 /*
2114 * __skb_unlink before linux2.6.14 does not use spinlock to protect list head.
2115 * add spinlock function manually. john,2008/12/03
2116 */
2117 {
2118 unsigned long flags;
2119 spin_lock_irqsave(&(priv->rx_queue.lock), flags);
2120 __skb_unlink(skb,&priv->rx_queue);
2121 spin_unlock_irqrestore(&(priv->rx_queue.lock), flags);
2122 }
2123#endif
2124 skb_put(skb, urb->actual_length);
2125
2126 skb_queue_tail(&priv->skb_queue, skb);
2127 tasklet_schedule(&priv->irq_rx_tasklet);
2128
2129 skb = dev_alloc_skb(RX_URB_SIZE);
2130 if (unlikely(!skb)) {
2131 usb_free_urb(urb);
2132 printk("%s():can,t alloc skb\n",__FUNCTION__);
2133 /* TODO check rx queue length and refill *somewhere* */
2134 return;
2135 }
2136
2137 usb_fill_bulk_urb(urb, priv->udev,
2138 usb_rcvbulkpipe(priv->udev, out_pipe), skb->tail,
2139 RX_URB_SIZE, rtl8192_rx_isr, skb);
2140
2141 info = (struct rtl8192_rx_info *) skb->cb;
2142 info->urb = urb;
2143 info->dev = dev;
2144 info->out_pipe = out_pipe;
2145
2146 urb->transfer_buffer = skb->tail;
2147 urb->context = skb;
2148 skb_queue_tail(&priv->rx_queue, skb);
2149#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
2150 err = usb_submit_urb(urb, GFP_ATOMIC);
2151#else
2152 err = usb_submit_urb(urb);
2153#endif
2154 if(err && err != EPERM)
2155 printk("can not submit rxurb, err is %x,URB status is %x\n",err,urb->status);
2156}
2157
2158u32
2159rtl819xusb_rx_command_packet(
2160 struct net_device *dev,
2161 struct ieee80211_rx_stats *pstats
2162 )
2163{
2164 u32 status;
2165
2166 //RT_TRACE(COMP_RECV, DBG_TRACE, ("---> RxCommandPacketHandle819xUsb()\n"));
2167
2168 status = cmpk_message_handle_rx(dev, pstats);
2169 if (status)
2170 {
2171 DMESG("rxcommandpackethandle819xusb: It is a command packet\n");
2172 }
2173 else
2174 {
2175 //RT_TRACE(COMP_RECV, DBG_TRACE, ("RxCommandPacketHandle819xUsb: It is not a command packet\n"));
2176 }
2177
2178 //RT_TRACE(COMP_RECV, DBG_TRACE, ("<--- RxCommandPacketHandle819xUsb()\n"));
2179 return status;
2180}
2181
2182#if 0
2183void rtl8192_tx_queues_stop(struct net_device *dev)
2184{
2185 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2186 u8 dma_poll_mask = (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2187 dma_poll_mask |= (1<<TX_DMA_STOP_HIPRIORITY_SHIFT);
2188 dma_poll_mask |= (1<<TX_DMA_STOP_NORMPRIORITY_SHIFT);
2189 dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
2190
2191 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2192 write_nic_byte(dev,TX_DMA_POLLING,dma_poll_mask);
2193 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2194}
2195#endif
2196
2197void rtl8192_data_hard_stop(struct net_device *dev)
2198{
2199 //FIXME !!
2200 #if 0
2201 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2202 priv->dma_poll_mask |= (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2203 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2204 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2205 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2206 #endif
2207}
2208
2209
2210void rtl8192_data_hard_resume(struct net_device *dev)
2211{
2212 // FIXME !!
2213 #if 0
2214 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2215 priv->dma_poll_mask &= ~(1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
2216 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
2217 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
2218 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
2219 #endif
2220}
2221
2222/* this function TX data frames when the ieee80211 stack requires this.
2223 * It checks also if we need to stop the ieee tx queue, eventually do it
2224 */
2225void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate)
2226{
2227 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2228 int ret;
2229 unsigned long flags;
2230 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2231 u8 queue_index = tcb_desc->queue_index;
2232
2233 /* shall not be referred by command packet */
2234 assert(queue_index != TXCMD_QUEUE);
2235
2236 spin_lock_irqsave(&priv->tx_lock,flags);
2237
2238 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2239// tcb_desc->RATRIndex = 7;
2240// tcb_desc->bTxDisableRateFallBack = 1;
2241// tcb_desc->bTxUseDriverAssingedRate = 1;
2242 tcb_desc->bTxEnableFwCalcDur = 1;
2243 skb_push(skb, priv->ieee80211->tx_headroom);
2244 ret = priv->ops->rtl819x_tx(dev, skb);
2245
2246 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2247 //priv->ieee80211->stats.tx_packets++;
2248
2249 spin_unlock_irqrestore(&priv->tx_lock,flags);
2250
2251// return ret;
2252 return;
2253}
2254
2255/* This is a rough attempt to TX a frame
2256 * This is called by the ieee 80211 stack to TX management frames.
2257 * If the ring is full packet are dropped (for data frame the queue
2258 * is stopped before this can happen).
2259 */
2260int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
2261{
2262 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2263 int ret;
2264 unsigned long flags;
2265 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2266 u8 queue_index = tcb_desc->queue_index;
2267
2268
2269 spin_lock_irqsave(&priv->tx_lock,flags);
2270
2271 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
2272 if(queue_index == TXCMD_QUEUE) {
2273 skb_push(skb, USB_HWDESC_HEADER_LEN);
2274 priv->ops->rtl819x_tx_cmd(dev, skb);
2275 ret = 1;
2276 spin_unlock_irqrestore(&priv->tx_lock,flags);
2277 return ret;
2278 } else {
2279 skb_push(skb, priv->ieee80211->tx_headroom);
2280 ret = priv->ops->rtl819x_tx(dev, skb);
2281 }
2282
2283 spin_unlock_irqrestore(&priv->tx_lock,flags);
2284
2285 return ret;
2286}
2287
2288
2289void rtl8192_try_wake_queue(struct net_device *dev, int pri);
2290
2291#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2292u16 DrvAggr_PaddingAdd(struct net_device *dev, struct sk_buff *skb)
2293{
2294 u16 PaddingNum = 256 - ((skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES) % 256);
2295 return (PaddingNum&0xff);
2296}
2297
2298u8 MRateToHwRate8190Pci(u8 rate);
2299u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc);
2300u8 MapHwQueueToFirmwareQueue(u8 QueueID);
2301struct sk_buff *DrvAggr_Aggregation(struct net_device *dev, struct ieee80211_drv_agg_txb *pSendList)
2302{
2303#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2304 struct ieee80211_device *ieee = netdev_priv(dev);
2305#else
2306 struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv;
2307#endif
2308 struct r8192_priv *priv = ieee80211_priv(dev);
2309 cb_desc *tcb_desc = NULL;
2310 u8 i;
2311 u32 TotalLength;
2312 struct sk_buff *skb;
2313 struct sk_buff *agg_skb;
2314 tx_desc_819x_usb_aggr_subframe *tx_agg_desc = NULL;
2315 tx_fwinfo_819x_usb *tx_fwinfo = NULL;
2316
2317 //
2318 // Local variable initialization.
2319 //
2320 /* first skb initialization */
2321 skb = pSendList->tx_agg_frames[0];
2322 TotalLength = skb->len;
2323
2324 /* Get the total aggregation length including the padding space and
2325 * sub frame header.
2326 */
2327 for(i = 1; i < pSendList->nr_drv_agg_frames; i++) {
2328 TotalLength += DrvAggr_PaddingAdd(dev, skb);
2329 skb = pSendList->tx_agg_frames[i];
2330 TotalLength += (skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES);
2331 }
2332
2333 /* allocate skb to contain the aggregated packets */
2334 agg_skb = dev_alloc_skb(TotalLength + ieee->tx_headroom);
2335 memset(agg_skb->data, 0, agg_skb->len);
2336 skb_reserve(agg_skb, ieee->tx_headroom);
2337
2338// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2339 /* reserve info for first subframe Tx descriptor to be set in the tx function */
2340 skb = pSendList->tx_agg_frames[0];
2341 tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2342 tcb_desc->drv_agg_enable = 1;
2343 tcb_desc->pkt_size = skb->len;
2344 tcb_desc->DrvAggrNum = pSendList->nr_drv_agg_frames;
2345 printk("DrvAggNum = %d\n", tcb_desc->DrvAggrNum);
2346// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2347// printk("========>skb->data ======> \n");
2348// RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len);
2349 memcpy(agg_skb->cb, skb->cb, sizeof(skb->cb));
2350 memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len);
2351
2352 for(i = 1; i < pSendList->nr_drv_agg_frames; i++) {
2353 /* push the next sub frame to be 256 byte aline */
2354 skb_put(agg_skb,DrvAggr_PaddingAdd(dev,skb));
2355
2356 /* Subframe drv Tx descriptor and firmware info setting */
2357 skb = pSendList->tx_agg_frames[i];
2358 tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2359 tx_agg_desc = (tx_desc_819x_usb_aggr_subframe *)agg_skb->tail;
2360 tx_fwinfo = (tx_fwinfo_819x_usb *)(agg_skb->tail + sizeof(tx_desc_819x_usb_aggr_subframe));
2361
2362 memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
2363 /* DWORD 0 */
2364 tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0;
2365 tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
2366 tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
2367 tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc);
2368 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
2369 tx_fwinfo->AllowAggregation = 1;
2370 /* DWORD 1 */
2371 tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
2372 tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
2373 } else {
2374 tx_fwinfo->AllowAggregation = 0;
2375 /* DWORD 1 */
2376 tx_fwinfo->RxMF = 0;
2377 tx_fwinfo->RxAMD = 0;
2378 }
2379
2380 /* Protection mode related */
2381 tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0;
2382 tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0;
2383 tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0;
2384 tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0;
2385 tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
2386 tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0;
2387 tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0;
2388 tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
2389 (tcb_desc->bRTSUseShortGI?1:0);
2390
2391 /* Set Bandwidth and sub-channel settings. */
2392 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2393 {
2394 if(tcb_desc->bPacketBW) {
2395 tx_fwinfo->TxBandwidth = 1;
2396 tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
2397 } else {
2398 tx_fwinfo->TxBandwidth = 0;
2399 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
2400 }
2401 } else {
2402 tx_fwinfo->TxBandwidth = 0;
2403 tx_fwinfo->TxSubCarrier = 0;
2404 }
2405
2406 /* Fill Tx descriptor */
2407 memset(tx_agg_desc, 0, sizeof(tx_desc_819x_usb_aggr_subframe));
2408 /* DWORD 0 */
2409 //tx_agg_desc->LINIP = 0;
2410 //tx_agg_desc->CmdInit = 1;
2411 tx_agg_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
2412 /* already raw data, need not to substract header length */
2413 tx_agg_desc->PktSize = skb->len & 0xffff;
2414
2415 /*DWORD 1*/
2416 tx_agg_desc->SecCAMID= 0;
2417 tx_agg_desc->RATid = tcb_desc->RATRIndex;
2418#if 0
2419 /* Fill security related */
2420 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
2421 {
2422 EncAlg = SecGetEncryptionOverhead(
2423 Adapter,
2424 &EncryptionMPDUHeadOverhead,
2425 &EncryptionMPDUTailOverhead,
2426 NULL,
2427 NULL,
2428 FALSE,
2429 FALSE);
2430 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
2431 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
2432 MPDUOverhead = EncryptionMPDUTailOverhead;
2433 tx_agg_desc->NoEnc = 0;
2434 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_agg_desc->SecCAMID,tx_agg_desc->SecDescAssign,EncAlg));
2435 //CamDumpAll(Adapter);
2436 }
2437 else
2438#endif
2439 {
2440 //MPDUOverhead = 0;
2441 tx_agg_desc->NoEnc = 1;
2442 }
2443#if 0
2444 switch(EncAlg){
2445 case NO_Encryption:
2446 tx_agg_desc->SecType = 0x0;
2447 break;
2448 case WEP40_Encryption:
2449 case WEP104_Encryption:
2450 tx_agg_desc->SecType = 0x1;
2451 break;
2452 case TKIP_Encryption:
2453 tx_agg_desc->SecType = 0x2;
2454 break;
2455 case AESCCMP_Encryption:
2456 tx_agg_desc->SecType = 0x3;
2457 break;
2458 default:
2459 tx_agg_desc->SecType = 0x0;
2460 break;
2461 }
2462#else
2463 tx_agg_desc->SecType = 0x0;
2464#endif
2465
2466 if (tcb_desc->bHwSec) {
2467 switch (priv->ieee80211->pairwise_key_type)
2468 {
2469 case KEY_TYPE_WEP40:
2470 case KEY_TYPE_WEP104:
2471 tx_agg_desc->SecType = 0x1;
2472 tx_agg_desc->NoEnc = 0;
2473 break;
2474 case KEY_TYPE_TKIP:
2475 tx_agg_desc->SecType = 0x2;
2476 tx_agg_desc->NoEnc = 0;
2477 break;
2478 case KEY_TYPE_CCMP:
2479 tx_agg_desc->SecType = 0x3;
2480 tx_agg_desc->NoEnc = 0;
2481 break;
2482 case KEY_TYPE_NA:
2483 tx_agg_desc->SecType = 0x0;
2484 tx_agg_desc->NoEnc = 1;
2485 break;
2486 }
2487 }
2488
2489 tx_agg_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
2490 tx_agg_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);
2491
2492 tx_agg_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
2493 tx_agg_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
2494
2495 tx_agg_desc->OWN = 1;
2496
2497 //DWORD 2
2498 /* According windows driver, it seems that there no need to fill this field */
2499 //tx_agg_desc->TxBufferSize= (u32)(skb->len - USB_HWDESC_HEADER_LEN);
2500
2501 /* to fill next packet */
2502 skb_put(agg_skb,TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES);
2503 memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len);
2504 }
2505
2506 for(i = 0; i < pSendList->nr_drv_agg_frames; i++) {
2507 dev_kfree_skb_any(pSendList->tx_agg_frames[i]);
2508 }
2509
2510 return agg_skb;
2511}
2512
2513/* NOTE:
2514 This function return a list of PTCB which is proper to be aggregate with the input TCB.
2515 If no proper TCB is found to do aggregation, SendList will only contain the input TCB.
2516*/
2517u8 DrvAggr_GetAggregatibleList(struct net_device *dev, struct sk_buff *skb,
2518 struct ieee80211_drv_agg_txb *pSendList)
2519{
2520#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2521 struct ieee80211_device *ieee = netdev_priv(dev);
2522#else
2523 struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv;
2524#endif
2525 PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
2526 u16 nMaxAggrNum = pHTInfo->UsbTxAggrNum;
2527 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2528 u8 QueueID = tcb_desc->queue_index;
2529
2530 do {
2531 pSendList->tx_agg_frames[pSendList->nr_drv_agg_frames++] = skb;
2532 if(pSendList->nr_drv_agg_frames >= nMaxAggrNum) {
2533 break;
2534 }
2535
2536 } while((skb = skb_dequeue(&ieee->skb_drv_aggQ[QueueID])));
2537
2538 RT_TRACE(COMP_AMSDU, "DrvAggr_GetAggregatibleList, nAggrTcbNum = %d \n", pSendList->nr_drv_agg_frames);
2539 return pSendList->nr_drv_agg_frames;
2540}
2541#endif
2542
2543#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
2544static void rtl8192_tx_isr(struct urb *tx_urb, struct pt_regs *reg)
2545#else
2546static void rtl8192_tx_isr(struct urb *tx_urb)
2547#endif
2548{
2549 struct sk_buff *skb = (struct sk_buff*)tx_urb->context;
2550 struct net_device *dev = NULL;
2551 struct r8192_priv *priv = NULL;
2552 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2553 u8 queue_index = tcb_desc->queue_index;
2554// bool bToSend0Byte;
2555// u16 BufLen = skb->len;
2556
2557 memcpy(&dev,(struct net_device*)(skb->cb),sizeof(struct net_device*));
2558 priv = ieee80211_priv(dev);
2559
2560 if(tcb_desc->queue_index != TXCMD_QUEUE) {
2561 if(tx_urb->status == 0) {
2562 // dev->trans_start = jiffies;
2563 // As act as station mode, destion shall be unicast address.
2564 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2565 //priv->ieee80211->stats.tx_packets++;
2566 priv->stats.txoktotal++;
2567 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
2568 priv->stats.txbytesunicast += (skb->len - priv->ieee80211->tx_headroom);
2569 } else {
2570 priv->ieee80211->stats.tx_errors++;
2571 //priv->stats.txmanageerr++;
2572 /* TODO */
2573 }
2574 }
2575
2576 /* free skb and tx_urb */
2577 if(skb != NULL) {
2578 dev_kfree_skb_any(skb);
2579 usb_free_urb(tx_urb);
2580 atomic_dec(&priv->tx_pending[queue_index]);
2581 }
2582
2583#if 0 //we need to send zero byte packet just after 512 byte(64 byte)packet is transmitted, or we will halt. It will greatly reduced available page in FW, and ruin our throughput. WB 2008.08.27
2584 if(BufLen > 0 && ((BufLen % 512 == 0)||(BufLen % 64 == 0))) {
2585 bToSend0Byte = true;
2586 }
2587
2588 bToSend0Byte = false;
2589 //
2590 // Note that, we at most handle 1 MPDU to send here, either
2591 // fragment or MPDU in wait queue.
2592 //
2593 if(!bToSend0Byte)
2594#endif
2595 {
2596 //
2597 // Handle HW Beacon:
2598 // We had transfer our beacon frame to host controler at this moment.
2599 //
2600#if 0
2601 if(tcb_desc->tx_queue == BEACON_QUEUE)
2602 {
2603 priv->bSendingBeacon = FALSE;
2604 }
2605#endif
2606 //
2607 // Caution:
2608 // Handling the wait queue of command packets.
2609 // For Tx command packets, we must not do TCB fragment because it is not handled right now.
2610 // We must cut the packets to match the size of TX_CMD_PKT before we send it.
2611 //
2612 if (queue_index == MGNT_QUEUE){
2613 if (priv->ieee80211->ack_tx_to_ieee){
2614 if (rtl8192_is_tx_queue_empty(dev)){
2615 priv->ieee80211->ack_tx_to_ieee = 0;
2616 ieee80211_ps_tx_ack(priv->ieee80211, 1);
2617 }
2618 }
2619 }
2620 /* Handle MPDU in wait queue. */
2621 if(queue_index != BEACON_QUEUE) {
2622 /* Don't send data frame during scanning.*/
2623 if((skb_queue_len(&priv->ieee80211->skb_waitQ[queue_index]) != 0)&&\
2624 (!(priv->ieee80211->queue_stop))) {
2625 if(NULL != (skb = skb_dequeue(&(priv->ieee80211->skb_waitQ[queue_index]))))
2626 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2627
2628 return; //modified by david to avoid further processing AMSDU
2629 }
2630#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
2631 else if ((skb_queue_len(&priv->ieee80211->skb_drv_aggQ[queue_index])!= 0)&&\
2632 (!(priv->ieee80211->queue_stop))) {
2633 // Tx Driver Aggregation process
2634 /* The driver will aggregation the packets according to the following stets
2635 * 1. check whether there's tx irq available, for it's a completion return
2636 * function, it should contain enough tx irq;
2637 * 2. check pakcet type;
2638 * 3. intialize sendlist, check whether the to-be send packet no greater than 1
2639 * 4. aggregation the packets, and fill firmware info and tx desc to it, etc.
2640 * 5. check whehter the packet could be sent, otherwise just insert to wait head
2641 * */
2642 skb = skb_dequeue(&priv->ieee80211->skb_drv_aggQ[queue_index]);
2643 if(!check_nic_enough_desc(dev, queue_index)) {
2644 skb_queue_head(&(priv->ieee80211->skb_drv_aggQ[queue_index]), skb);
2645 return;
2646 }
2647
2648 {
2649 /*TODO*/
2650 /*
2651 u8* pHeader = skb->data;
2652
2653 if(IsMgntQosData(pHeader) ||
2654 IsMgntQData_Ack(pHeader) ||
2655 IsMgntQData_Poll(pHeader) ||
2656 IsMgntQData_Poll_Ack(pHeader)
2657 )
2658 */
2659 {
2660 struct ieee80211_drv_agg_txb SendList;
2661
2662 memset(&SendList, 0, sizeof(struct ieee80211_drv_agg_txb));
2663 if(DrvAggr_GetAggregatibleList(dev, skb, &SendList) > 1) {
2664 skb = DrvAggr_Aggregation(dev, &SendList);
2665
2666#if 0
2667 printk("=============>to send aggregated packet!\n");
2668 RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb));
2669 printk("\n=================skb->len = %d\n", skb->len);
2670 RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len);
2671#endif
2672 }
2673 }
2674 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2675 }
2676 }
2677#endif
2678 }
2679 }
2680
2681#if 0
2682 else
2683 {
2684 RT_TRACE( COMP_SEND,"HalUsbOutComplete(%d): bToSend0Byte.\n", PipeIndex);
2685
2686 //
2687 // In this case, we don't return skb now.
2688 // It will be returned when the 0-byte request completed.
2689 //
2690
2691 //
2692 // Bulk out an 0-byte padding transfer.
2693 //
2694 HalUsbOut0Byte(pAdapter, PipeIndex, skb);
2695 }
2696
2697#endif
2698}
2699
2700void rtl8192_beacon_stop(struct net_device *dev)
2701{
2702 u8 msr, msrm, msr2;
2703 struct r8192_priv *priv = ieee80211_priv(dev);
2704
2705 msr = read_nic_byte(dev, MSR);
2706 msrm = msr & MSR_LINK_MASK;
2707 msr2 = msr & ~MSR_LINK_MASK;
2708
2709 if(NIC_8192U == priv->card_8192) {
2710 usb_kill_urb(priv->rx_urb[MAX_RX_URB]);
2711 }
2712 if ((msrm == (MSR_LINK_ADHOC<<MSR_LINK_SHIFT) ||
2713 (msrm == (MSR_LINK_MASTER<<MSR_LINK_SHIFT)))){
2714 write_nic_byte(dev, MSR, msr2 | MSR_LINK_NONE);
2715 write_nic_byte(dev, MSR, msr);
2716 }
2717}
2718
2719void rtl8192_config_rate(struct net_device* dev, u16* rate_config)
2720{
2721 struct r8192_priv *priv = ieee80211_priv(dev);
2722 struct ieee80211_network *net;
2723 u8 i=0, basic_rate = 0;
2724 net = & priv->ieee80211->current_network;
2725
2726 for (i=0; i<net->rates_len; i++)
2727 {
2728 basic_rate = net->rates[i]&0x7f;
2729 switch(basic_rate)
2730 {
2731 case MGN_1M: *rate_config |= RRSR_1M; break;
2732 case MGN_2M: *rate_config |= RRSR_2M; break;
2733 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2734 case MGN_11M: *rate_config |= RRSR_11M; break;
2735 case MGN_6M: *rate_config |= RRSR_6M; break;
2736 case MGN_9M: *rate_config |= RRSR_9M; break;
2737 case MGN_12M: *rate_config |= RRSR_12M; break;
2738 case MGN_18M: *rate_config |= RRSR_18M; break;
2739 case MGN_24M: *rate_config |= RRSR_24M; break;
2740 case MGN_36M: *rate_config |= RRSR_36M; break;
2741 case MGN_48M: *rate_config |= RRSR_48M; break;
2742 case MGN_54M: *rate_config |= RRSR_54M; break;
2743 }
2744 }
2745 for (i=0; i<net->rates_ex_len; i++)
2746 {
2747 basic_rate = net->rates_ex[i]&0x7f;
2748 switch(basic_rate)
2749 {
2750 case MGN_1M: *rate_config |= RRSR_1M; break;
2751 case MGN_2M: *rate_config |= RRSR_2M; break;
2752 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2753 case MGN_11M: *rate_config |= RRSR_11M; break;
2754 case MGN_6M: *rate_config |= RRSR_6M; break;
2755 case MGN_9M: *rate_config |= RRSR_9M; break;
2756 case MGN_12M: *rate_config |= RRSR_12M; break;
2757 case MGN_18M: *rate_config |= RRSR_18M; break;
2758 case MGN_24M: *rate_config |= RRSR_24M; break;
2759 case MGN_36M: *rate_config |= RRSR_36M; break;
2760 case MGN_48M: *rate_config |= RRSR_48M; break;
2761 case MGN_54M: *rate_config |= RRSR_54M; break;
2762 }
2763 }
2764}
2765
2766
2767#define SHORT_SLOT_TIME 9
2768#define NON_SHORT_SLOT_TIME 20
2769
2770void rtl8192_update_cap(struct net_device* dev, u16 cap)
2771{
2772 //u32 tmp = 0;
2773 struct r8192_priv *priv = ieee80211_priv(dev);
2774 struct ieee80211_network *net = &priv->ieee80211->current_network;
2775 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
2776
2777 //LZM MOD 090303 HW_VAR_ACK_PREAMBLE
2778#ifdef RTL8192SU
2779 if(0)
2780 {
2781 u8 tmp = 0;
2782 tmp = ((priv->nCur40MhzPrimeSC) << 5);
2783 if (priv->short_preamble)
2784 tmp |= 0x80;
2785 write_nic_byte(dev, RRSR+2, tmp);
2786 }
2787#else
2788 {
2789 u32 tmp = 0;
2790 tmp = priv->basic_rate;
2791 if (priv->short_preamble)
2792 tmp |= BRSR_AckShortPmb;
2793 write_nic_dword(dev, RRSR, tmp);
2794 }
2795#endif
2796
2797 if (net->mode & (IEEE_G|IEEE_N_24G))
2798 {
2799 u8 slot_time = 0;
2800 if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime))
2801 {//short slot time
2802 slot_time = SHORT_SLOT_TIME;
2803 }
2804 else //long slot time
2805 slot_time = NON_SHORT_SLOT_TIME;
2806 priv->slot_time = slot_time;
2807 write_nic_byte(dev, SLOT_TIME, slot_time);
2808 }
2809
2810}
2811void rtl8192_net_update(struct net_device *dev)
2812{
2813
2814 struct r8192_priv *priv = ieee80211_priv(dev);
2815 struct ieee80211_network *net;
2816 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
2817 u16 rate_config = 0;
2818 net = & priv->ieee80211->current_network;
2819
2820 rtl8192_config_rate(dev, &rate_config);
2821 priv->basic_rate = rate_config &= 0x15f;
2822
2823 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
2824 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
2825 //for(i=0;i<ETH_ALEN;i++)
2826 // write_nic_byte(dev,BSSID+i,net->bssid[i]);
2827
2828 rtl8192_update_msr(dev);
2829// rtl8192_update_cap(dev, net->capability);
2830 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
2831 {
2832 write_nic_word(dev, ATIMWND, 2);
2833 write_nic_word(dev, BCN_DMATIME, 1023);
2834 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
2835// write_nic_word(dev, BcnIntTime, 100);
2836 write_nic_word(dev, BCN_DRV_EARLY_INT, 1);
2837 write_nic_byte(dev, BCN_ERR_THRESH, 100);
2838 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
2839 // TODO: BcnIFS may required to be changed on ASIC
2840 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
2841
2842 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
2843 }
2844
2845
2846
2847}
2848
2849//temporary hw beacon is not used any more.
2850//open it when necessary
2851#if 1
2852void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate)
2853{
2854
2855#if 0
2856 struct r8192_priv *priv = ieee80211_priv(dev);
2857 struct sk_buff *skb;
2858 int i = 0;
2859 //u8 cr;
2860
2861 rtl8192_net_update(dev);
2862
2863 skb = ieee80211_get_beacon(priv->ieee80211);
2864 if(!skb){
2865 DMESG("not enought memory for allocating beacon");
2866 return;
2867 }
2868
2869
2870 write_nic_byte(dev, BQREQ, read_nic_byte(dev, BQREQ) | (1<<7));
2871
2872 i=0;
2873 //while(!read_nic_byte(dev,BQREQ & (1<<7)))
2874 while( (read_nic_byte(dev, BQREQ) & (1<<7)) == 0 )
2875 {
2876 msleep_interruptible_rtl(HZ/2);
2877 if(i++ > 10){
2878 DMESGW("get stuck to wait HW beacon to be ready");
2879 return ;
2880 }
2881 }
2882 skb->cb[0] = NORM_PRIORITY;
2883 skb->cb[1] = 0; //morefragment = 0
2884 skb->cb[2] = ieeerate2rtlrate(tx_rate);
2885
2886 rtl8192_tx(dev,skb);
2887
2888#endif
2889}
2890#endif
2891inline u8 rtl8192_IsWirelessBMode(u16 rate)
2892{
2893 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
2894 return 1;
2895 else return 0;
2896}
2897
2898u16 N_DBPSOfRate(u16 DataRate);
2899
2900u16 ComputeTxTime(
2901 u16 FrameLength,
2902 u16 DataRate,
2903 u8 bManagementFrame,
2904 u8 bShortPreamble
2905)
2906{
2907 u16 FrameTime;
2908 u16 N_DBPS;
2909 u16 Ceiling;
2910
2911 if( rtl8192_IsWirelessBMode(DataRate) )
2912 {
2913 if( bManagementFrame || !bShortPreamble || DataRate == 10 )
2914 { // long preamble
2915 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
2916 }
2917 else
2918 { // Short preamble
2919 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
2920 }
2921 if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling
2922 FrameTime ++;
2923 } else { //802.11g DSSS-OFDM PLCP length field calculation.
2924 N_DBPS = N_DBPSOfRate(DataRate);
2925 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
2926 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
2927 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
2928 }
2929 return FrameTime;
2930}
2931
2932u16 N_DBPSOfRate(u16 DataRate)
2933{
2934 u16 N_DBPS = 24;
2935
2936 switch(DataRate)
2937 {
2938 case 60:
2939 N_DBPS = 24;
2940 break;
2941
2942 case 90:
2943 N_DBPS = 36;
2944 break;
2945
2946 case 120:
2947 N_DBPS = 48;
2948 break;
2949
2950 case 180:
2951 N_DBPS = 72;
2952 break;
2953
2954 case 240:
2955 N_DBPS = 96;
2956 break;
2957
2958 case 360:
2959 N_DBPS = 144;
2960 break;
2961
2962 case 480:
2963 N_DBPS = 192;
2964 break;
2965
2966 case 540:
2967 N_DBPS = 216;
2968 break;
2969
2970 default:
2971 break;
2972 }
2973
2974 return N_DBPS;
2975}
2976
2977void rtl819xU_cmd_isr(struct urb *tx_cmd_urb, struct pt_regs *regs)
2978{
2979#if 0
2980 struct net_device *dev = (struct net_device*)tx_cmd_urb->context;
2981 struct r8192_priv *priv = ieee80211_priv(dev);
2982 int last_init_packet = 0;
2983 u8 *ptr_cmd_buf;
2984 u16 cmd_buf_len;
2985
2986 if(tx_cmd_urb->status != 0) {
2987 priv->pFirmware.firmware_seg_index = 0; //only begin transter, should it can be set to 1
2988 }
2989
2990 /* Free the urb and the corresponding buf for common Tx cmd packet, or
2991 * last segment of each firmware img.
2992 */
2993 if((priv->pFirmware.firmware_seg_index == 0) ||(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum)) {
2994 priv->pFirmware.firmware_seg_index = 0;//only begin transter, should it can be set to 1
2995 } else {
2996 /* prepare for last transfer */
2997 /* update some infomation for */
2998 /* last segment of the firmware img need indicate to device */
2999 priv->pFirmware.firmware_seg_index++;
3000 if(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum) {
3001 last_init_packet = 1;
3002 }
3003
3004 cmd_buf_len = priv->pFirmware.firmware_seg_container[priv->pFirmware.firmware_seg_index-1].seg_size;
3005 ptr_cmd_buf = priv->pFfirmware.firmware_seg_container[priv->pFfirmware.firmware_seg_index-1].seg_ptr;
3006 rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT);
3007 }
3008
3009 kfree(tx_cmd_urb->transfer_buffer);
3010#endif
3011 usb_free_urb(tx_cmd_urb);
3012}
3013
3014unsigned int txqueue2outpipe(struct r8192_priv* priv,unsigned int tx_queue) {
3015
3016 if(tx_queue >= 9)
3017 {
3018 RT_TRACE(COMP_ERR,"%s():Unknown queue ID!!!\n",__FUNCTION__);
3019 return 0x04;
3020 }
3021 return priv->txqueue_to_outpipemap[tx_queue];
3022}
3023
3024#ifdef RTL8192SU
3025short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
3026{
3027 struct r8192_priv *priv = ieee80211_priv(dev);
3028 int status;
3029 struct urb *tx_urb;
3030 unsigned int idx_pipe;
3031 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
3032 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3033 u8 queue_index = tcb_desc->queue_index;
3034 u32 PktSize = 0;
3035
3036 //printk("\n %s::::::::::::::::::::::queue_index = %d\n",__FUNCTION__, queue_index);
3037 atomic_inc(&priv->tx_pending[queue_index]);
3038
3039#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3040 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
3041#else
3042 tx_urb = usb_alloc_urb(0);
3043#endif
3044 if(!tx_urb){
3045 dev_kfree_skb(skb);
3046 return -ENOMEM;
3047 }
3048
3049 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
3050
3051 /* Tx descriptor ought to be set according to the skb->cb */
3052 pdesc->LINIP = tcb_desc->bLastIniPkt;
3053 PktSize = (u16)(skb->len - USB_HWDESC_HEADER_LEN);
3054 pdesc->PktSize = PktSize;
3055 //printk("PKTSize = %d %x\n",pdesc->PktSize,pdesc->PktSize);
3056 //----------------------------------------------------------------------------
3057 // Fill up USB_OUT_CONTEXT.
3058 //----------------------------------------------------------------------------
3059 // Get index to out pipe from specified QueueID.
3060 idx_pipe = txqueue2outpipe(priv,queue_index);
3061 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,queue_index,priv->RtOutPipes[idx_pipe]);
3062
3063#ifdef JOHN_DUMP_TXDESC
3064 int i;
3065 printk("Len = %d\n", skb->len);
3066 for (i = 0; i < 8; i++)
3067 printk("%2.2x ", *((u8*)skb->data+i));
3068 printk("\n");
3069#endif
3070
3071 usb_fill_bulk_urb(tx_urb,
3072 priv->udev,
3073 usb_sndbulkpipe(priv->udev,priv->RtOutPipes[idx_pipe]),
3074 skb->data,
3075 skb->len,
3076 rtl8192_tx_isr,
3077 skb);
3078
3079#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3080 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
3081#else
3082 status = usb_submit_urb(tx_urb);
3083#endif
3084
3085 if (!status){
3086 return 0;
3087 }else{
3088 printk("Error TX CMD URB, error %d",
3089 status);
3090 return -1;
3091 }
3092}
3093#else
3094short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
3095{
3096 struct r8192_priv *priv = ieee80211_priv(dev);
3097 //u8 *tx;
3098 int status;
3099 struct urb *tx_urb;
3100 //int urb_buf_len;
3101 unsigned int idx_pipe;
3102 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
3103 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3104 u8 queue_index = tcb_desc->queue_index;
3105
3106 //printk("\n %s::queue_index = %d\n",__FUNCTION__, queue_index);
3107 atomic_inc(&priv->tx_pending[queue_index]);
3108#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3109 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
3110#else
3111 tx_urb = usb_alloc_urb(0);
3112#endif
3113 if(!tx_urb){
3114 dev_kfree_skb(skb);
3115 return -ENOMEM;
3116 }
3117
3118 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
3119 /* Tx descriptor ought to be set according to the skb->cb */
3120 pdesc->FirstSeg = 1;//bFirstSeg;
3121 pdesc->LastSeg = 1;//bLastSeg;
3122 pdesc->CmdInit = tcb_desc->bCmdOrInit;
3123 pdesc->TxBufferSize = tcb_desc->txbuf_size;
3124 pdesc->OWN = 1;
3125 pdesc->LINIP = tcb_desc->bLastIniPkt;
3126
3127 //----------------------------------------------------------------------------
3128 // Fill up USB_OUT_CONTEXT.
3129 //----------------------------------------------------------------------------
3130 // Get index to out pipe from specified QueueID.
3131#ifndef USE_ONE_PIPE
3132 idx_pipe = txqueue2outpipe(priv,queue_index);
3133#else
3134 idx_pipe = 0x04;
3135#endif
3136#ifdef JOHN_DUMP_TXDESC
3137 int i;
3138 printk("<Tx descriptor>--rate %x---",rate);
3139 for (i = 0; i < 8; i++)
3140 printk("%8x ", tx[i]);
3141 printk("\n");
3142#endif
3143 usb_fill_bulk_urb(tx_urb,priv->udev, usb_sndbulkpipe(priv->udev,idx_pipe), \
3144 skb->data, skb->len, rtl8192_tx_isr, skb);
3145
3146#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3147 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
3148#else
3149 status = usb_submit_urb(tx_urb);
3150#endif
3151
3152 if (!status){
3153 return 0;
3154 }else{
3155 DMESGE("Error TX CMD URB, error %d",
3156 status);
3157 return -1;
3158 }
3159}
3160#endif
3161
3162/*
3163 * Mapping Software/Hardware descriptor queue id to "Queue Select Field"
3164 * in TxFwInfo data structure
3165 * 2006.10.30 by Emily
3166 *
3167 * \param QUEUEID Software Queue
3168*/
3169u8 MapHwQueueToFirmwareQueue(u8 QueueID)
3170{
3171 u8 QueueSelect = 0x0; //defualt set to
3172
3173 switch(QueueID) {
3174 case BE_QUEUE:
3175 QueueSelect = QSLT_BE; //or QSelect = pTcb->priority;
3176 break;
3177
3178 case BK_QUEUE:
3179 QueueSelect = QSLT_BK; //or QSelect = pTcb->priority;
3180 break;
3181
3182 case VO_QUEUE:
3183 QueueSelect = QSLT_VO; //or QSelect = pTcb->priority;
3184 break;
3185
3186 case VI_QUEUE:
3187 QueueSelect = QSLT_VI; //or QSelect = pTcb->priority;
3188 break;
3189 case MGNT_QUEUE:
3190 QueueSelect = QSLT_MGNT;
3191 break;
3192
3193 case BEACON_QUEUE:
3194 QueueSelect = QSLT_BEACON;
3195 break;
3196
3197 // TODO: 2006.10.30 mark other queue selection until we verify it is OK
3198 // TODO: Remove Assertions
3199//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502)
3200 case TXCMD_QUEUE:
3201 QueueSelect = QSLT_CMD;
3202 break;
3203//#endif
3204 case HIGH_QUEUE:
3205 QueueSelect = QSLT_HIGH;
3206 break;
3207
3208 default:
3209 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID);
3210 break;
3211 }
3212 return QueueSelect;
3213}
3214
3215#ifdef RTL8192SU
3216u8 MRateToHwRate8190Pci(u8 rate)
3217{
3218 u8 ret = DESC92S_RATE1M;
3219
3220 switch(rate)
3221 {
3222 // CCK and OFDM non-HT rates
3223 case MGN_1M: ret = DESC92S_RATE1M; break;
3224 case MGN_2M: ret = DESC92S_RATE2M; break;
3225 case MGN_5_5M: ret = DESC92S_RATE5_5M; break;
3226 case MGN_11M: ret = DESC92S_RATE11M; break;
3227 case MGN_6M: ret = DESC92S_RATE6M; break;
3228 case MGN_9M: ret = DESC92S_RATE9M; break;
3229 case MGN_12M: ret = DESC92S_RATE12M; break;
3230 case MGN_18M: ret = DESC92S_RATE18M; break;
3231 case MGN_24M: ret = DESC92S_RATE24M; break;
3232 case MGN_36M: ret = DESC92S_RATE36M; break;
3233 case MGN_48M: ret = DESC92S_RATE48M; break;
3234 case MGN_54M: ret = DESC92S_RATE54M; break;
3235
3236 // HT rates since here
3237 case MGN_MCS0: ret = DESC92S_RATEMCS0; break;
3238 case MGN_MCS1: ret = DESC92S_RATEMCS1; break;
3239 case MGN_MCS2: ret = DESC92S_RATEMCS2; break;
3240 case MGN_MCS3: ret = DESC92S_RATEMCS3; break;
3241 case MGN_MCS4: ret = DESC92S_RATEMCS4; break;
3242 case MGN_MCS5: ret = DESC92S_RATEMCS5; break;
3243 case MGN_MCS6: ret = DESC92S_RATEMCS6; break;
3244 case MGN_MCS7: ret = DESC92S_RATEMCS7; break;
3245 case MGN_MCS8: ret = DESC92S_RATEMCS8; break;
3246 case MGN_MCS9: ret = DESC92S_RATEMCS9; break;
3247 case MGN_MCS10: ret = DESC92S_RATEMCS10; break;
3248 case MGN_MCS11: ret = DESC92S_RATEMCS11; break;
3249 case MGN_MCS12: ret = DESC92S_RATEMCS12; break;
3250 case MGN_MCS13: ret = DESC92S_RATEMCS13; break;
3251 case MGN_MCS14: ret = DESC92S_RATEMCS14; break;
3252 case MGN_MCS15: ret = DESC92S_RATEMCS15; break;
3253
3254 // Set the highest SG rate
3255 case MGN_MCS0_SG:
3256 case MGN_MCS1_SG:
3257 case MGN_MCS2_SG:
3258 case MGN_MCS3_SG:
3259 case MGN_MCS4_SG:
3260 case MGN_MCS5_SG:
3261 case MGN_MCS6_SG:
3262 case MGN_MCS7_SG:
3263 case MGN_MCS8_SG:
3264 case MGN_MCS9_SG:
3265 case MGN_MCS10_SG:
3266 case MGN_MCS11_SG:
3267 case MGN_MCS12_SG:
3268 case MGN_MCS13_SG:
3269 case MGN_MCS14_SG:
3270 case MGN_MCS15_SG:
3271 {
3272 ret = DESC92S_RATEMCS15_SG;
3273 break;
3274 }
3275
3276 default: break;
3277 }
3278 return ret;
3279}
3280#else
3281u8 MRateToHwRate8190Pci(u8 rate)
3282{
3283 u8 ret = DESC90_RATE1M;
3284
3285 switch(rate) {
3286 case MGN_1M: ret = DESC90_RATE1M; break;
3287 case MGN_2M: ret = DESC90_RATE2M; break;
3288 case MGN_5_5M: ret = DESC90_RATE5_5M; break;
3289 case MGN_11M: ret = DESC90_RATE11M; break;
3290 case MGN_6M: ret = DESC90_RATE6M; break;
3291 case MGN_9M: ret = DESC90_RATE9M; break;
3292 case MGN_12M: ret = DESC90_RATE12M; break;
3293 case MGN_18M: ret = DESC90_RATE18M; break;
3294 case MGN_24M: ret = DESC90_RATE24M; break;
3295 case MGN_36M: ret = DESC90_RATE36M; break;
3296 case MGN_48M: ret = DESC90_RATE48M; break;
3297 case MGN_54M: ret = DESC90_RATE54M; break;
3298
3299 // HT rate since here
3300 case MGN_MCS0: ret = DESC90_RATEMCS0; break;
3301 case MGN_MCS1: ret = DESC90_RATEMCS1; break;
3302 case MGN_MCS2: ret = DESC90_RATEMCS2; break;
3303 case MGN_MCS3: ret = DESC90_RATEMCS3; break;
3304 case MGN_MCS4: ret = DESC90_RATEMCS4; break;
3305 case MGN_MCS5: ret = DESC90_RATEMCS5; break;
3306 case MGN_MCS6: ret = DESC90_RATEMCS6; break;
3307 case MGN_MCS7: ret = DESC90_RATEMCS7; break;
3308 case MGN_MCS8: ret = DESC90_RATEMCS8; break;
3309 case MGN_MCS9: ret = DESC90_RATEMCS9; break;
3310 case MGN_MCS10: ret = DESC90_RATEMCS10; break;
3311 case MGN_MCS11: ret = DESC90_RATEMCS11; break;
3312 case MGN_MCS12: ret = DESC90_RATEMCS12; break;
3313 case MGN_MCS13: ret = DESC90_RATEMCS13; break;
3314 case MGN_MCS14: ret = DESC90_RATEMCS14; break;
3315 case MGN_MCS15: ret = DESC90_RATEMCS15; break;
3316 case (0x80|0x20): ret = DESC90_RATEMCS32; break;
3317
3318 default: break;
3319 }
3320 return ret;
3321}
3322#endif
3323
3324u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc)
3325{
3326 u8 tmp_Short;
3327
3328 tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0);
3329
3330 if(TxHT==1 && TxRate != DESC90_RATEMCS15)
3331 tmp_Short = 0;
3332
3333 return tmp_Short;
3334}
3335
3336#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
3337static void tx_zero_isr(struct urb *tx_urb, struct pt_regs *reg)
3338#else
3339static void tx_zero_isr(struct urb *tx_urb)
3340#endif
3341{
3342 return;
3343}
3344
3345
3346#ifdef RTL8192SU
3347/*
3348 * The tx procedure is just as following, skb->cb will contain all the following
3349 *information: * priority, morefrag, rate, &dev.
3350 * */
3351 // <Note> Buffer format for 8192S Usb bulk out:
3352//
3353// --------------------------------------------------
3354// | 8192S Usb Tx Desc | 802_11_MAC_header | data |
3355// --------------------------------------------------
3356// | 32 bytes | 24 bytes |0-2318 bytes|
3357// --------------------------------------------------
3358// |<------------ BufferLen ------------------------->|
3359
3360short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb)
3361{
3362 struct r8192_priv *priv = ieee80211_priv(dev);
3363 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3364 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
3365 //tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);//92su del
3366 struct usb_device *udev = priv->udev;
3367 int pend;
3368 int status;
3369 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
3370 //int urb_len;
3371 unsigned int idx_pipe;
3372 u16 MPDUOverhead = 0;
3373 //RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
3374
3375#if 0
3376 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
3377 RT_ENC_ALG EncAlg = NO_Encryption;
3378#endif
3379
3380
3381 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
3382 /* we are locked here so the two atomic_read and inc are executed
3383 * without interleaves * !!! For debug purpose */
3384 if( pend > MAX_TX_URB){
3385 switch (tcb_desc->queue_index) {
3386 case VO_PRIORITY:
3387 priv->stats.txvodrop++;
3388 break;
3389 case VI_PRIORITY:
3390 priv->stats.txvidrop++;
3391 break;
3392 case BE_PRIORITY:
3393 priv->stats.txbedrop++;
3394 break;
3395 default://BK_PRIORITY
3396 priv->stats.txbkdrop++;
3397 break;
3398 }
3399 printk("To discard skb packet!\n");
3400 dev_kfree_skb_any(skb);
3401 return -1;
3402 }
3403
3404#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3405 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
3406#else
3407 tx_urb = usb_alloc_urb(0);
3408#endif
3409 if(!tx_urb){
3410 dev_kfree_skb_any(skb);
3411 return -ENOMEM;
3412 }
3413
3414 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3415
3416
3417#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK
3418 if(IsQoSDataFrame(skb->data))
3419 {
3420 tcb_desc->bAMPDUEnable = TRUE;
3421 tx_desc->NonQos = 0;
3422 }
3423 else
3424 tcb_desc->bAMPDUEnable = FALSE;
3425
3426 tcb_desc->bPacketBW = TRUE;
3427 priv->CurrentChannelBW = HT_CHANNEL_WIDTH_20_40;
3428#endif
3429
3430#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
3431 tx_desc->NonQos = (IsQoSDataFrame(skb->data)==TRUE)? 0:1;
3432#endif
3433
3434 /* Fill Tx descriptor */
3435 //memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
3436
3437 // This part can just fill to the first descriptor of the frame.
3438 /* DWORD 0 */
3439 tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0;
3440
3441#ifdef RTL8192SU_DISABLE_CCK_RATE
3442 if(tx_hal_is_cck_rate(tcb_desc->data_rate))
3443 tcb_desc->data_rate = MGN_6M;
3444#endif
3445
3446 tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
3447 //tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
3448 tx_desc->TxShort = QueryIsShort(tx_desc->TxHT, tx_desc->TxRate, tcb_desc);
3449
3450
3451 // Aggregation related
3452 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
3453 tx_desc->AllowAggregation = 1;
3454 /* DWORD 1 */
3455 //tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
3456 //tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
3457 } else {
3458 tx_desc->AllowAggregation = 0;
3459 /* DWORD 1 */
3460 //tx_fwinfo->RxMF = 0;
3461 //tx_fwinfo->RxAMD = 0;
3462 }
3463
3464 //
3465 // <Roger_Notes> For AMPDU case, we must insert SSN into TX_DESC,
3466 // FW according as this SSN to do necessary packet retry.
3467 // 2008.06.06.
3468 //
3469 {
3470 u8 *pSeq;
3471 u16 Temp;
3472 //pSeq = (u8 *)(VirtualAddress+USB_HWDESC_HEADER_LEN + FRAME_OFFSET_SEQUENCE);
3473 pSeq = (u8 *)(skb->data+USB_HWDESC_HEADER_LEN + 22);
3474 Temp = pSeq[0];
3475 Temp <<= 12;
3476 Temp |= (*(u16 *)pSeq)>>4;
3477 tx_desc->Seq = Temp;
3478 }
3479
3480 /* Protection mode related */
3481 tx_desc->RTSEn = (tcb_desc->bRTSEnable)?1:0;
3482 tx_desc->CTS2Self = (tcb_desc->bCTSEnable)?1:0;
3483 tx_desc->RTSSTBC = (tcb_desc->bRTSSTBC)?1:0;
3484 tx_desc->RTSHT = (tcb_desc->rts_rate&0x80)?1:0;
3485 tx_desc->RTSRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3486 tx_desc->RTSSubcarrier = (tx_desc->RTSHT==0)?(tcb_desc->RTSSC):0;
3487 tx_desc->RTSBW = (tx_desc->RTSHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3488 tx_desc->RTSShort = (tx_desc->RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3489 (tcb_desc->bRTSUseShortGI?1:0);
3490 //LZM 090219
3491 tx_desc->DisRTSFB = 0;
3492 tx_desc->RTSRateFBLmt = 0xf;
3493
3494 // <Roger_EXP> 2008.09.22. We disable RTS rate fallback temporarily.
3495 //tx_desc->DisRTSFB = 0x01;
3496
3497 /* Set Bandwidth and sub-channel settings. */
3498 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3499 {
3500 if(tcb_desc->bPacketBW) {
3501 tx_desc->TxBandwidth = 1;
3502 tx_desc->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3503 } else {
3504 tx_desc->TxBandwidth = 0;
3505 tx_desc->TxSubCarrier = priv->nCur40MhzPrimeSC;
3506 }
3507 } else {
3508 tx_desc->TxBandwidth = 0;
3509 tx_desc->TxSubCarrier = 0;
3510 }
3511
3512#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3513 if (tcb_desc->drv_agg_enable)
3514 {
3515 //tx_desc->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1; //92su del
3516 }
3517#endif
3518
3519 //memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3520 /* DWORD 0 */
3521 tx_desc->LINIP = 0;
3522 //tx_desc->CmdInit = 1; //92su del
3523 tx_desc->Offset = USB_HWDESC_HEADER_LEN;
3524
3525#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3526 if (tcb_desc->drv_agg_enable) {
3527 tx_desc->PktSize = tcb_desc->pkt_size;//FIXLZM
3528 } else
3529#endif
3530 {
3531 tx_desc->PktSize = (skb->len - USB_HWDESC_HEADER_LEN) & 0xffff;
3532 }
3533
3534 /*DWORD 1*/
3535 //tx_desc->SecCAMID= 0;//92su del
3536 tx_desc->RaBRSRID= tcb_desc->RATRIndex;
3537//#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
3538#if 0//LZM 090219
3539 tx_desc->RaBRSRID= 1;
3540#endif
3541
3542#if 0
3543 /* Fill security related */
3544 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3545 {
3546 EncAlg = SecGetEncryptionOverhead(
3547 Adapter,
3548 &EncryptionMPDUHeadOverhead,
3549 &EncryptionMPDUTailOverhead,
3550 NULL,
3551 NULL,
3552 FALSE,
3553 FALSE);
3554 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3555 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3556 MPDUOverhead = EncryptionMPDUTailOverhead;
3557 tx_desc->NoEnc = 0;
3558 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3559 //CamDumpAll(Adapter);
3560 }
3561 else
3562#endif
3563 {
3564 MPDUOverhead = 0;
3565 //tx_desc->NoEnc = 1;//92su del
3566 }
3567#if 0
3568 switch(EncAlg){
3569 case NO_Encryption:
3570 tx_desc->SecType = 0x0;
3571 break;
3572 case WEP40_Encryption:
3573 case WEP104_Encryption:
3574 tx_desc->SecType = 0x1;
3575 break;
3576 case TKIP_Encryption:
3577 tx_desc->SecType = 0x2;
3578 break;
3579 case AESCCMP_Encryption:
3580 tx_desc->SecType = 0x3;
3581 break;
3582 default:
3583 tx_desc->SecType = 0x0;
3584 break;
3585 }
3586#else
3587 tx_desc->SecType = 0x0;
3588#endif
3589 if (tcb_desc->bHwSec)
3590 {
3591 switch (priv->ieee80211->pairwise_key_type)
3592 {
3593 case KEY_TYPE_WEP40:
3594 case KEY_TYPE_WEP104:
3595 tx_desc->SecType = 0x1;
3596 //tx_desc->NoEnc = 0;//92su del
3597 break;
3598 case KEY_TYPE_TKIP:
3599 tx_desc->SecType = 0x2;
3600 //tx_desc->NoEnc = 0;//92su del
3601 break;
3602 case KEY_TYPE_CCMP:
3603 tx_desc->SecType = 0x3;
3604 //tx_desc->NoEnc = 0;//92su del
3605 break;
3606 case KEY_TYPE_NA:
3607 tx_desc->SecType = 0x0;
3608 //tx_desc->NoEnc = 1;//92su del
3609 break;
3610 default:
3611 tx_desc->SecType = 0x0;
3612 //tx_desc->NoEnc = 1;//92su del
3613 break;
3614 }
3615 }
3616
3617 //tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);//92su del
3618
3619
3620 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3621 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3622 tx_desc->DataRateFBLmt = 0x1F;// Alwasy enable all rate fallback range
3623
3624 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3625
3626
3627 /* Fill fields that are required to be initialized in all of the descriptors */
3628 //DWORD 0
3629#if 0
3630 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3631 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3632#else
3633 tx_desc->FirstSeg = 1;
3634 tx_desc->LastSeg = 1;
3635#endif
3636 tx_desc->OWN = 1;
3637
3638#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3639 if (tcb_desc->drv_agg_enable) {
3640 tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb);
3641 } else
3642#endif
3643 {
3644 //DWORD 2
3645 //tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3646 tx_desc->TxBufferSize = (u32)(skb->len);//92su mod FIXLZM
3647 }
3648
3649#if 0
3650 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(1)TxFillDescriptor8192SUsb(): DataRate(%#x)\n", pTcb->DataRate));
3651 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(2)TxFillDescriptor8192SUsb(): bTxUseDriverAssingedRate(%#x)\n", pTcb->bTxUseDriverAssingedRate));
3652 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(3)TxFillDescriptor8192SUsb(): bAMPDUEnable(%d)\n", pTcb->bAMPDUEnable));
3653 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(4)TxFillDescriptor8192SUsb(): bRTSEnable(%d)\n", pTcb->bRTSEnable));
3654 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(5)TxFillDescriptor8192SUsb(): RTSRate(%#x)\n", pTcb->RTSRate));
3655 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(6)TxFillDescriptor8192SUsb(): bCTSEnable(%d)\n", pTcb->bCTSEnable));
3656 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(7)TxFillDescriptor8192SUsb(): bUseShortGI(%d)\n", pTcb->bUseShortGI));
3657 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(8)TxFillDescriptor8192SUsb(): bPacketBW(%d)\n", pTcb->bPacketBW));
3658 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(9)TxFillDescriptor8192SUsb(): CurrentChannelBW(%d)\n", pHalData->CurrentChannelBW));
3659 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(10)TxFillDescriptor8192SUsb(): bTxDisableRateFallBack(%d)\n", pTcb->bTxDisableRateFallBack));
3660 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(11)TxFillDescriptor8192SUsb(): RATRIndex(%d)\n", pTcb->RATRIndex));
3661#endif
3662
3663 /* Get index to out pipe from specified QueueID */
3664 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
3665 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,tcb_desc->queue_index,priv->RtOutPipes[idx_pipe]);
3666
3667 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3668 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3669
3670 /* To submit bulk urb */
3671 usb_fill_bulk_urb(tx_urb,
3672 udev,
3673 usb_sndbulkpipe(udev,priv->RtOutPipes[idx_pipe]),
3674 skb->data,
3675 skb->len, rtl8192_tx_isr, skb);
3676
3677#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3678 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
3679#else
3680 status = usb_submit_urb(tx_urb);
3681#endif
3682 if (!status){
3683//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3684 bool bSend0Byte = false;
3685 u8 zero = 0;
3686 if(udev->speed == USB_SPEED_HIGH)
3687 {
3688 if (skb->len > 0 && skb->len % 512 == 0)
3689 bSend0Byte = true;
3690 }
3691 else
3692 {
3693 if (skb->len > 0 && skb->len % 64 == 0)
3694 bSend0Byte = true;
3695 }
3696 if (bSend0Byte)
3697 {
3698#if 1
3699#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3700 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
3701#else
3702 tx_urb_zero = usb_alloc_urb(0);
3703#endif
3704 if(!tx_urb_zero){
3705 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
3706 return -ENOMEM;
3707 }
3708 usb_fill_bulk_urb(tx_urb_zero,udev,
3709 usb_sndbulkpipe(udev,idx_pipe), &zero,
3710 0, tx_zero_isr, dev);
3711#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3712 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
3713#else
3714 status = usb_submit_urb(tx_urb_zero);
3715#endif
3716 if (status){
3717 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
3718 return -1;
3719 }
3720#endif
3721 }
3722 dev->trans_start = jiffies;
3723 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
3724 return 0;
3725 }else{
3726 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
3727 status);
3728 return -1;
3729 }
3730}
3731#else
3732
3733/*
3734 * The tx procedure is just as following,
3735 * skb->cb will contain all the following information,
3736 * priority, morefrag, rate, &dev.
3737 * */
3738short rtl8192_tx(struct net_device *dev, struct sk_buff* skb)
3739{
3740 struct r8192_priv *priv = ieee80211_priv(dev);
3741 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
3742 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
3743 tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);
3744 struct usb_device *udev = priv->udev;
3745 int pend;
3746 int status;
3747 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
3748 //int urb_len;
3749 unsigned int idx_pipe;
3750// RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
3751#if 0
3752 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
3753 RT_ENC_ALG EncAlg = NO_Encryption;
3754#endif
3755// printk("=============> %s\n", __FUNCTION__);
3756 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
3757 /* we are locked here so the two atomic_read and inc are executed
3758 * without interleaves
3759 * !!! For debug purpose
3760 */
3761 if( pend > MAX_TX_URB){
3762#if 0
3763 switch (tcb_desc->queue_index) {
3764 case VO_PRIORITY:
3765 priv->stats.txvodrop++;
3766 break;
3767 case VI_PRIORITY:
3768 priv->stats.txvidrop++;
3769 break;
3770 case BE_PRIORITY:
3771 priv->stats.txbedrop++;
3772 break;
3773 default://BK_PRIORITY
3774 priv->stats.txbkdrop++;
3775 break;
3776 }
3777#endif
3778 printk("To discard skb packet!\n");
3779 dev_kfree_skb_any(skb);
3780 return -1;
3781 }
3782
3783#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3784 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
3785#else
3786 tx_urb = usb_alloc_urb(0);
3787#endif
3788 if(!tx_urb){
3789 dev_kfree_skb_any(skb);
3790 return -ENOMEM;
3791 }
3792
3793 /* Fill Tx firmware info */
3794 memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
3795 /* DWORD 0 */
3796 tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0;
3797 tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
3798 tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
3799 tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc);
3800 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
3801 tx_fwinfo->AllowAggregation = 1;
3802 /* DWORD 1 */
3803 tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
3804 tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
3805 } else {
3806 tx_fwinfo->AllowAggregation = 0;
3807 /* DWORD 1 */
3808 tx_fwinfo->RxMF = 0;
3809 tx_fwinfo->RxAMD = 0;
3810 }
3811
3812 /* Protection mode related */
3813 tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0;
3814 tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0;
3815 tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0;
3816 tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0;
3817 tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
3818 tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0;
3819 tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0;
3820 tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
3821 (tcb_desc->bRTSUseShortGI?1:0);
3822
3823 /* Set Bandwidth and sub-channel settings. */
3824 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
3825 {
3826 if(tcb_desc->bPacketBW) {
3827 tx_fwinfo->TxBandwidth = 1;
3828 tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
3829 } else {
3830 tx_fwinfo->TxBandwidth = 0;
3831 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
3832 }
3833 } else {
3834 tx_fwinfo->TxBandwidth = 0;
3835 tx_fwinfo->TxSubCarrier = 0;
3836 }
3837
3838#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3839 if (tcb_desc->drv_agg_enable)
3840 {
3841 tx_fwinfo->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1;
3842 }
3843#endif
3844 /* Fill Tx descriptor */
3845 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
3846 /* DWORD 0 */
3847 tx_desc->LINIP = 0;
3848 tx_desc->CmdInit = 1;
3849 tx_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
3850
3851#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3852 if (tcb_desc->drv_agg_enable) {
3853 tx_desc->PktSize = tcb_desc->pkt_size;
3854 } else
3855#endif
3856 {
3857 tx_desc->PktSize = (skb->len - TX_PACKET_SHIFT_BYTES) & 0xffff;
3858 }
3859
3860 /*DWORD 1*/
3861 tx_desc->SecCAMID= 0;
3862 tx_desc->RATid = tcb_desc->RATRIndex;
3863#if 0
3864 /* Fill security related */
3865 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
3866 {
3867 EncAlg = SecGetEncryptionOverhead(
3868 Adapter,
3869 &EncryptionMPDUHeadOverhead,
3870 &EncryptionMPDUTailOverhead,
3871 NULL,
3872 NULL,
3873 FALSE,
3874 FALSE);
3875 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
3876 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
3877 MPDUOverhead = EncryptionMPDUTailOverhead;
3878 tx_desc->NoEnc = 0;
3879 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
3880 //CamDumpAll(Adapter);
3881 }
3882 else
3883#endif
3884 {
3885 //MPDUOverhead = 0;
3886 tx_desc->NoEnc = 1;
3887 }
3888#if 0
3889 switch(EncAlg){
3890 case NO_Encryption:
3891 tx_desc->SecType = 0x0;
3892 break;
3893 case WEP40_Encryption:
3894 case WEP104_Encryption:
3895 tx_desc->SecType = 0x1;
3896 break;
3897 case TKIP_Encryption:
3898 tx_desc->SecType = 0x2;
3899 break;
3900 case AESCCMP_Encryption:
3901 tx_desc->SecType = 0x3;
3902 break;
3903 default:
3904 tx_desc->SecType = 0x0;
3905 break;
3906 }
3907#else
3908 tx_desc->SecType = 0x0;
3909#endif
3910 if (tcb_desc->bHwSec)
3911 {
3912 switch (priv->ieee80211->pairwise_key_type)
3913 {
3914 case KEY_TYPE_WEP40:
3915 case KEY_TYPE_WEP104:
3916 tx_desc->SecType = 0x1;
3917 tx_desc->NoEnc = 0;
3918 break;
3919 case KEY_TYPE_TKIP:
3920 tx_desc->SecType = 0x2;
3921 tx_desc->NoEnc = 0;
3922 break;
3923 case KEY_TYPE_CCMP:
3924 tx_desc->SecType = 0x3;
3925 tx_desc->NoEnc = 0;
3926 break;
3927 case KEY_TYPE_NA:
3928 tx_desc->SecType = 0x0;
3929 tx_desc->NoEnc = 1;
3930 break;
3931 }
3932 }
3933
3934 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
3935 tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);
3936
3937 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
3938 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
3939
3940 /* Fill fields that are required to be initialized in all of the descriptors */
3941 //DWORD 0
3942#if 0
3943 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
3944 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
3945#else
3946 tx_desc->FirstSeg = 1;
3947 tx_desc->LastSeg = 1;
3948#endif
3949 tx_desc->OWN = 1;
3950
3951#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
3952 if (tcb_desc->drv_agg_enable) {
3953 tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb);
3954 } else
3955#endif
3956 {
3957 //DWORD 2
3958 tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
3959 }
3960 /* Get index to out pipe from specified QueueID */
3961#ifndef USE_ONE_PIPE
3962 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
3963#else
3964 idx_pipe = 0x5;
3965#endif
3966
3967 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
3968 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
3969
3970 /* To submit bulk urb */
3971 usb_fill_bulk_urb(tx_urb,udev,
3972 usb_sndbulkpipe(udev,idx_pipe), skb->data,
3973 skb->len, rtl8192_tx_isr, skb);
3974
3975#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3976 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
3977#else
3978 status = usb_submit_urb(tx_urb);
3979#endif
3980 if (!status){
3981//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
3982 bool bSend0Byte = false;
3983 u8 zero = 0;
3984 if(udev->speed == USB_SPEED_HIGH)
3985 {
3986 if (skb->len > 0 && skb->len % 512 == 0)
3987 bSend0Byte = true;
3988 }
3989 else
3990 {
3991 if (skb->len > 0 && skb->len % 64 == 0)
3992 bSend0Byte = true;
3993 }
3994 if (bSend0Byte)
3995 {
3996#if 1
3997#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
3998 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
3999#else
4000 tx_urb_zero = usb_alloc_urb(0);
4001#endif
4002 if(!tx_urb_zero){
4003 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
4004 return -ENOMEM;
4005 }
4006 usb_fill_bulk_urb(tx_urb_zero,udev,
4007 usb_sndbulkpipe(udev,idx_pipe), &zero,
4008 0, tx_zero_isr, dev);
4009#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
4010 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
4011#else
4012 status = usb_submit_urb(tx_urb_zero);
4013#endif
4014 if (status){
4015 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
4016 return -1;
4017 }
4018#endif
4019 }
4020 dev->trans_start = jiffies;
4021 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
4022 return 0;
4023 }else{
4024 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
4025 status);
4026 return -1;
4027 }
4028}
4029#endif
4030
4031#if 0
4032void rtl8192_set_rate(struct net_device *dev)
4033{
4034 int i;
4035 u16 word;
4036 int basic_rate,min_rr_rate,max_rr_rate;
4037
4038// struct r8192_priv *priv = ieee80211_priv(dev);
4039
4040 //if (ieee80211_is_54g(priv->ieee80211->current_network) &&
4041// priv->ieee80211->state == IEEE80211_LINKED){
4042 basic_rate = ieeerate2rtlrate(240);
4043 min_rr_rate = ieeerate2rtlrate(60);
4044 max_rr_rate = ieeerate2rtlrate(240);
4045
4046//
4047// }else{
4048// basic_rate = ieeerate2rtlrate(20);
4049// min_rr_rate = ieeerate2rtlrate(10);
4050// max_rr_rate = ieeerate2rtlrate(110);
4051// }
4052
4053 write_nic_byte(dev, RESP_RATE,
4054 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
4055
4056 //word = read_nic_word(dev, BRSR);
4057 word = read_nic_word(dev, BRSR_8187);
4058 word &= ~BRSR_MBR_8185;
4059
4060
4061 for(i=0;i<=basic_rate;i++)
4062 word |= (1<<i);
4063
4064 //write_nic_word(dev, BRSR, word);
4065 write_nic_word(dev, BRSR_8187, word);
4066 //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE), read_nic_word(dev,BRSR));
4067}
4068#endif
4069
4070
4071#ifdef RTL8192SU
4072void rtl8192SU_net_update(struct net_device *dev)
4073{
4074
4075 struct r8192_priv *priv = ieee80211_priv(dev);
4076 struct ieee80211_device* ieee = priv->ieee80211;
4077 struct ieee80211_network *net = &priv->ieee80211->current_network;
4078 //u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
4079 u16 rate_config = 0;
4080 u32 regTmp = 0;
4081 u8 rateIndex = 0;
4082 u8 retrylimit = 0x30;
4083 u16 cap = net->capability;
4084
4085 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
4086
4087//HW_VAR_BASIC_RATE
4088 //update Basic rate: RR, BRSR
4089 rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg
4090
4091#ifdef RTL8192SU_DISABLE_CCK_RATE
4092 priv->basic_rate = rate_config = rate_config & 0x150; // Disable CCK 11M, 5.5M, 2M, and 1M rates.
4093#else
4094 priv->basic_rate = rate_config = rate_config & 0x15f;
4095#endif
4096
4097 // Set RRSR rate table.
4098 write_nic_byte(dev, RRSR, rate_config&0xff);
4099 write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff);
4100
4101 // Set RTS initial rate
4102 while(rate_config > 0x1)
4103 {
4104 rate_config = (rate_config>> 1);
4105 rateIndex++;
4106 }
4107 write_nic_byte(dev, INIRTSMCS_SEL, rateIndex);
4108//HW_VAR_BASIC_RATE
4109
4110 //set ack preample
4111 regTmp = (priv->nCur40MhzPrimeSC) << 5;
4112 if (priv->short_preamble)
4113 regTmp |= 0x80;
4114 write_nic_byte(dev, RRSR+2, regTmp);
4115
4116 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
4117 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
4118
4119 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
4120 //2008.10.24 added by tynli for beacon changed.
4121 PHY_SetBeaconHwReg( dev, net->beacon_interval);
4122
4123 rtl8192_update_cap(dev, cap);
4124
4125 if (ieee->iw_mode == IW_MODE_ADHOC){
4126 retrylimit = 7;
4127 //we should enable ibss interrupt here, but disable it temporarily
4128 if (0){
4129 priv->irq_mask |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
4130 //rtl8192_irq_disable(dev);
4131 //rtl8192_irq_enable(dev);
4132 }
4133 }
4134 else{
4135 if (0){
4136 priv->irq_mask &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
4137 //rtl8192_irq_disable(dev);
4138 //rtl8192_irq_enable(dev);
4139 }
4140 }
4141
4142 priv->ShortRetryLimit = priv->LongRetryLimit = retrylimit;
4143
4144 write_nic_word(dev, RETRY_LIMIT,
4145 retrylimit << RETRY_LIMIT_SHORT_SHIFT | \
4146 retrylimit << RETRY_LIMIT_LONG_SHIFT);
4147}
4148
4149void rtl8192SU_update_ratr_table(struct net_device* dev)
4150{
4151 struct r8192_priv* priv = ieee80211_priv(dev);
4152 struct ieee80211_device* ieee = priv->ieee80211;
4153 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
4154 //struct ieee80211_network *net = &ieee->current_network;
4155 u32 ratr_value = 0;
4156
4157 u8 rate_index = 0;
4158 int WirelessMode = ieee->mode;
4159 u8 MimoPs = ieee->pHTInfo->PeerMimoPs;
4160
4161 u8 bNMode = 0;
4162
4163 rtl8192_config_rate(dev, (u16*)(&ratr_value));
4164 ratr_value |= (*(u16*)(pMcsRate)) << 12;
4165
4166 //switch (ieee->mode)
4167 switch (WirelessMode)
4168 {
4169 case IEEE_A:
4170 ratr_value &= 0x00000FF0;
4171 break;
4172 case IEEE_B:
4173 ratr_value &= 0x0000000D;
4174 break;
4175 case IEEE_G:
4176 ratr_value &= 0x00000FF5;
4177 break;
4178 case IEEE_N_24G:
4179 case IEEE_N_5G:
4180 {
4181 bNMode = 1;
4182
4183 if (MimoPs == 0) //MIMO_PS_STATIC
4184 {
4185 ratr_value &= 0x0007F005;
4186 }
4187 else
4188 { // MCS rate only => for 11N mode.
4189 u32 ratr_mask;
4190
4191 // 1T2R or 1T1R, Spatial Stream 2 should be disabled
4192 if ( priv->rf_type == RF_1T2R ||
4193 priv->rf_type == RF_1T1R ||
4194 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS) )
4195 ratr_mask = 0x000ff005;
4196 else
4197 ratr_mask = 0x0f0ff005;
4198
4199 if((ieee->pHTInfo->bCurTxBW40MHz) &&
4200 !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ))
4201 ratr_mask |= 0x00000010; // Set 6MBps
4202
4203 // Select rates for rate adaptive mechanism.
4204 ratr_value &= ratr_mask;
4205 }
4206 }
4207 break;
4208 default:
4209 if(0)
4210 {
4211 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
4212 {
4213 ratr_value &= 0x000ff0f5;
4214 }
4215 else
4216 {
4217 ratr_value &= 0x0f0ff0f5;
4218 }
4219 }
4220 //printk("====>%s(), mode is not correct:%x\n", __FUNCTION__, ieee->mode);
4221 break;
4222 }
4223
4224#ifdef RTL8192SU_DISABLE_CCK_RATE
4225 ratr_value &= 0x0FFFFFF0;
4226#else
4227 ratr_value &= 0x0FFFFFFF;
4228#endif
4229
4230 // Get MAX MCS available.
4231 if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) &&
4232 ((ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI40MHz) ||
4233 (!ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI20MHz)))
4234 {
4235 u8 shortGI_rate = 0;
4236 u32 tmp_ratr_value = 0;
4237 ratr_value |= 0x10000000;//???
4238 tmp_ratr_value = (ratr_value>>12);
4239 for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--)
4240 {
4241 if((1<<shortGI_rate) & tmp_ratr_value)
4242 break;
4243 }
4244 shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate);
4245 write_nic_byte(dev, SG_RATE, shortGI_rate);
4246 //printk("==>SG_RATE:%x\n", read_nic_byte(dev, SG_RATE));
4247 }
4248 write_nic_dword(dev, ARFR0+rate_index*4, ratr_value);
4249 printk("=============>ARFR0+rate_index*4:%#x\n", ratr_value);
4250
4251 //2 UFWP
4252 if (ratr_value & 0xfffff000){
4253 //printk("===>set to N mode\n");
4254 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_N);
4255 }
4256 else {
4257 //printk("===>set to B/G mode\n");
4258 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_BG);
4259 }
4260}
4261
4262void rtl8192SU_link_change(struct net_device *dev)
4263{
4264 struct r8192_priv *priv = ieee80211_priv(dev);
4265 struct ieee80211_device* ieee = priv->ieee80211;
4266 //unsigned long flags;
4267 u32 reg = 0;
4268
4269 printk("=====>%s 1\n", __func__);
4270 reg = read_nic_dword(dev, RCR);
4271
4272 if (ieee->state == IEEE80211_LINKED)
4273 {
4274
4275 rtl8192SU_net_update(dev);
4276 rtl8192SU_update_ratr_table(dev);
4277 ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE);
4278 priv->ReceiveConfig = reg |= RCR_CBSSID;
4279
4280 }else{
4281 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
4282
4283 }
4284
4285 write_nic_dword(dev, RCR, reg);
4286 rtl8192_update_msr(dev);
4287
4288 printk("<=====%s 2\n", __func__);
4289}
4290#else
4291extern void rtl8192_update_ratr_table(struct net_device* dev);
4292void rtl8192_link_change(struct net_device *dev)
4293{
4294// int i;
4295
4296 struct r8192_priv *priv = ieee80211_priv(dev);
4297 struct ieee80211_device* ieee = priv->ieee80211;
4298 //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval);
4299 if (ieee->state == IEEE80211_LINKED)
4300 {
4301 rtl8192_net_update(dev);
4302 rtl8192_update_ratr_table(dev);
4303#if 1
4304 //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08
4305 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
4306 EnableHWSecurityConfig8192(dev);
4307#endif
4308 }
4309 /*update timing params*/
4310// RT_TRACE(COMP_CH, "========>%s(), chan:%d\n", __FUNCTION__, priv->chan);
4311// rtl8192_set_chan(dev, priv->chan);
4312 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
4313 {
4314 u32 reg = 0;
4315 reg = read_nic_dword(dev, RCR);
4316 if (priv->ieee80211->state == IEEE80211_LINKED)
4317 priv->ReceiveConfig = reg |= RCR_CBSSID;
4318 else
4319 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
4320 write_nic_dword(dev, RCR, reg);
4321 }
4322
4323// rtl8192_set_rxconf(dev);
4324}
4325#endif
4326
4327static struct ieee80211_qos_parameters def_qos_parameters = {
4328 {3,3,3,3},/* cw_min */
4329 {7,7,7,7},/* cw_max */
4330 {2,2,2,2},/* aifs */
4331 {0,0,0,0},/* flags */
4332 {0,0,0,0} /* tx_op_limit */
4333};
4334
4335
4336#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20)
4337void rtl8192_update_beacon(struct work_struct * work)
4338{
4339 struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
4340 struct net_device *dev = priv->ieee80211->dev;
4341#else
4342void rtl8192_update_beacon(struct net_device *dev)
4343{
4344 struct r8192_priv *priv = ieee80211_priv(dev);
4345#endif
4346 struct ieee80211_device* ieee = priv->ieee80211;
4347 struct ieee80211_network* net = &ieee->current_network;
4348
4349 if (ieee->pHTInfo->bCurrentHTSupport)
4350 HTUpdateSelfAndPeerSetting(ieee, net);
4351 ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime;
4352 // Joseph test for turbo mode with AP
4353 ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode;
4354 rtl8192_update_cap(dev, net->capability);
4355}
4356/*
4357* background support to run QoS activate functionality
4358*/
4359int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO};
4360#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20)
4361void rtl8192_qos_activate(struct work_struct * work)
4362{
4363 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
4364 struct net_device *dev = priv->ieee80211->dev;
4365#else
4366void rtl8192_qos_activate(struct net_device *dev)
4367{
4368 struct r8192_priv *priv = ieee80211_priv(dev);
4369#endif
4370 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
4371 u8 mode = priv->ieee80211->current_network.mode;
4372 //u32 size = sizeof(struct ieee80211_qos_parameters);
4373 u8 u1bAIFS;
4374 u32 u4bAcParam;
4375 int i;
4376
4377 if (priv == NULL)
4378 return;
4379
4380#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
4381 down(&priv->mutex);
4382#else
4383 mutex_lock(&priv->mutex);
4384#endif
4385 if(priv->ieee80211->state != IEEE80211_LINKED)
4386 goto success;
4387 RT_TRACE(COMP_QOS,"qos active process with associate response received\n");
4388 /* It better set slot time at first */
4389 /* For we just support b/g mode at present, let the slot time at 9/20 selection */
4390 /* update the ac parameter to related registers */
4391 for(i = 0; i < QOS_QUEUE_NUM; i++) {
4392 //Mode G/A: slotTimeTimer = 9; Mode B: 20
4393 u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
4394 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
4395 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
4396 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
4397 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
4398
4399 write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
4400 //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4322);
4401 }
4402
4403success:
4404#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
4405 up(&priv->mutex);
4406#else
4407 mutex_unlock(&priv->mutex);
4408#endif
4409}
4410
4411static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv,
4412 int active_network,
4413 struct ieee80211_network *network)
4414{
4415 int ret = 0;
4416 u32 size = sizeof(struct ieee80211_qos_parameters);
4417
4418 if(priv->ieee80211->state !=IEEE80211_LINKED)
4419 return ret;
4420
4421 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
4422 return ret;
4423
4424 if (network->flags & NETWORK_HAS_QOS_MASK) {
4425 if (active_network &&
4426 (network->flags & NETWORK_HAS_QOS_PARAMETERS))
4427 network->qos_data.active = network->qos_data.supported;
4428
4429 if ((network->qos_data.active == 1) && (active_network == 1) &&
4430 (network->flags & NETWORK_HAS_QOS_PARAMETERS) &&
4431 (network->qos_data.old_param_count !=
4432 network->qos_data.param_count)) {
4433 network->qos_data.old_param_count =
4434 network->qos_data.param_count;
4435#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
4436 queue_work(priv->priv_wq, &priv->qos_activate);
4437#else
4438 schedule_task(&priv->qos_activate);
4439#endif
4440 RT_TRACE (COMP_QOS, "QoS parameters change call "
4441 "qos_activate\n");
4442 }
4443 } else {
4444 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4445 &def_qos_parameters, size);
4446
4447 if ((network->qos_data.active == 1) && (active_network == 1)) {
4448#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
4449 queue_work(priv->priv_wq, &priv->qos_activate);
4450#else
4451 schedule_task(&priv->qos_activate);
4452#endif
4453 RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n");
4454 }
4455 network->qos_data.active = 0;
4456 network->qos_data.supported = 0;
4457 }
4458
4459 return 0;
4460}
4461
4462/* handle manage frame frame beacon and probe response */
4463static int rtl8192_handle_beacon(struct net_device * dev,
4464 struct ieee80211_beacon * beacon,
4465 struct ieee80211_network * network)
4466{
4467 struct r8192_priv *priv = ieee80211_priv(dev);
4468
4469 rtl8192_qos_handle_probe_response(priv,1,network);
4470#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4471 queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0);
4472#else
4473#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
4474 schedule_task(&priv->update_beacon_wq);
4475#else
4476 queue_work(priv->priv_wq, &priv->update_beacon_wq);
4477#endif
4478
4479#endif
4480 return 0;
4481
4482}
4483
4484/*
4485* handling the beaconing responses. if we get different QoS setting
4486* off the network from the associated setting, adjust the QoS
4487* setting
4488*/
4489static int rtl8192_qos_association_resp(struct r8192_priv *priv,
4490 struct ieee80211_network *network)
4491{
4492 int ret = 0;
4493 unsigned long flags;
4494 u32 size = sizeof(struct ieee80211_qos_parameters);
4495 int set_qos_param = 0;
4496
4497 if ((priv == NULL) || (network == NULL))
4498 return ret;
4499
4500 if(priv->ieee80211->state !=IEEE80211_LINKED)
4501 return ret;
4502
4503 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
4504 return ret;
4505
4506 spin_lock_irqsave(&priv->ieee80211->lock, flags);
4507 if(network->flags & NETWORK_HAS_QOS_PARAMETERS) {
4508 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4509 &network->qos_data.parameters,\
4510 sizeof(struct ieee80211_qos_parameters));
4511 priv->ieee80211->current_network.qos_data.active = 1;
4512#if 0
4513 if((priv->ieee80211->current_network.qos_data.param_count != \
4514 network->qos_data.param_count))
4515#endif
4516 {
4517 set_qos_param = 1;
4518 /* update qos parameter for current network */
4519 priv->ieee80211->current_network.qos_data.old_param_count = \
4520 priv->ieee80211->current_network.qos_data.param_count;
4521 priv->ieee80211->current_network.qos_data.param_count = \
4522 network->qos_data.param_count;
4523 }
4524 } else {
4525 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
4526 &def_qos_parameters, size);
4527 priv->ieee80211->current_network.qos_data.active = 0;
4528 priv->ieee80211->current_network.qos_data.supported = 0;
4529 set_qos_param = 1;
4530 }
4531
4532 spin_unlock_irqrestore(&priv->ieee80211->lock, flags);
4533
4534 RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active);
4535 if (set_qos_param == 1)
4536#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
4537 queue_work(priv->priv_wq, &priv->qos_activate);
4538#else
4539 schedule_task(&priv->qos_activate);
4540#endif
4541
4542
4543 return ret;
4544}
4545
4546
4547static int rtl8192_handle_assoc_response(struct net_device *dev,
4548 struct ieee80211_assoc_response_frame *resp,
4549 struct ieee80211_network *network)
4550{
4551 struct r8192_priv *priv = ieee80211_priv(dev);
4552 rtl8192_qos_association_resp(priv, network);
4553 return 0;
4554}
4555
4556
4557void rtl8192_update_ratr_table(struct net_device* dev)
4558 // POCTET_STRING posLegacyRate,
4559 // u8* pMcsRate)
4560 // PRT_WLAN_STA pEntry)
4561{
4562 struct r8192_priv* priv = ieee80211_priv(dev);
4563 struct ieee80211_device* ieee = priv->ieee80211;
4564 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
4565 //struct ieee80211_network *net = &ieee->current_network;
4566 u32 ratr_value = 0;
4567 u8 rate_index = 0;
4568 rtl8192_config_rate(dev, (u16*)(&ratr_value));
4569 ratr_value |= (*(u16*)(pMcsRate)) << 12;
4570// switch (net->mode)
4571 switch (ieee->mode)
4572 {
4573 case IEEE_A:
4574 ratr_value &= 0x00000FF0;
4575 break;
4576 case IEEE_B:
4577 ratr_value &= 0x0000000F;
4578 break;
4579 case IEEE_G:
4580 ratr_value &= 0x00000FF7;
4581 break;
4582 case IEEE_N_24G:
4583 case IEEE_N_5G:
4584 if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC
4585 ratr_value &= 0x0007F007;
4586 else{
4587 if (priv->rf_type == RF_1T2R)
4588 ratr_value &= 0x000FF007;
4589 else
4590 ratr_value &= 0x0F81F007;
4591 }
4592 break;
4593 default:
4594 break;
4595 }
4596 ratr_value &= 0x0FFFFFFF;
4597 if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){
4598 ratr_value |= 0x80000000;
4599 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
4600 ratr_value |= 0x80000000;
4601 }
4602 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
4603 write_nic_byte(dev, UFWP, 1);
4604}
4605
4606static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04};
4607static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04};
4608bool GetNmodeSupportBySecCfg8192(struct net_device*dev)
4609{
4610#if 1
4611 struct r8192_priv* priv = ieee80211_priv(dev);
4612 struct ieee80211_device* ieee = priv->ieee80211;
4613 struct ieee80211_network * network = &ieee->current_network;
4614 int wpa_ie_len= ieee->wpa_ie_len;
4615 struct ieee80211_crypt_data* crypt;
4616 int encrypt;
4617#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
4618 return TRUE;
4619#endif
4620
4621 crypt = ieee->crypt[ieee->tx_keyidx];
4622 //we use connecting AP's capability instead of only security config on our driver to distinguish whether it should use N mode or G mode
4623 encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP")));
4624
4625 /* simply judge */
4626 if(encrypt && (wpa_ie_len == 0)) {
4627 /* wep encryption, no N mode setting */
4628 return false;
4629// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) {
4630 } else if((wpa_ie_len != 0)) {
4631 /* parse pairwise key type */
4632 //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP))
4633 if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4))))
4634 return true;
4635 else
4636 return false;
4637 } else {
4638 return true;
4639 }
4640
4641#if 0
4642 //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate.
4643 //We can't force in G mode if Pairwie key is AES and group key is TKIP
4644 if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) ||
4645 (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) ||
4646 (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption))
4647 {
4648 return false;
4649 }
4650 else
4651 return true;
4652#endif
4653 return true;
4654#endif
4655}
4656
4657bool GetHalfNmodeSupportByAPs819xUsb(struct net_device* dev)
4658{
4659 bool Reval;
4660 struct r8192_priv* priv = ieee80211_priv(dev);
4661 struct ieee80211_device* ieee = priv->ieee80211;
4662
4663// Added by Roger, 2008.08.29.
4664#ifdef RTL8192SU
4665 return false;
4666#endif
4667
4668 if(ieee->bHalfWirelessN24GMode == true)
4669 Reval = true;
4670 else
4671 Reval = false;
4672
4673 return Reval;
4674}
4675
4676void rtl8192_refresh_supportrate(struct r8192_priv* priv)
4677{
4678 struct ieee80211_device* ieee = priv->ieee80211;
4679 //we donot consider set support rate for ABG mode, only HT MCS rate is set here.
4680 if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G)
4681 {
4682 memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
4683 //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16);
4684 //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16);
4685 }
4686 else
4687 memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
4688 return;
4689}
4690
4691u8 rtl8192_getSupportedWireleeMode(struct net_device*dev)
4692{
4693 struct r8192_priv *priv = ieee80211_priv(dev);
4694 u8 ret = 0;
4695 switch(priv->rf_chip)
4696 {
4697 case RF_8225:
4698 case RF_8256:
4699 case RF_PSEUDO_11N:
4700 case RF_6052:
4701 ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B);
4702 break;
4703 case RF_8258:
4704 ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G);
4705 break;
4706 default:
4707 ret = WIRELESS_MODE_B;
4708 break;
4709 }
4710 return ret;
4711}
4712void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode)
4713{
4714 struct r8192_priv *priv = ieee80211_priv(dev);
4715 u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev);
4716
4717#if 1
4718 if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0))
4719 {
4720 if(bSupportMode & WIRELESS_MODE_N_24G)
4721 {
4722 wireless_mode = WIRELESS_MODE_N_24G;
4723 }
4724 else if(bSupportMode & WIRELESS_MODE_N_5G)
4725 {
4726 wireless_mode = WIRELESS_MODE_N_5G;
4727 }
4728 else if((bSupportMode & WIRELESS_MODE_A))
4729 {
4730 wireless_mode = WIRELESS_MODE_A;
4731 }
4732 else if((bSupportMode & WIRELESS_MODE_G))
4733 {
4734 wireless_mode = WIRELESS_MODE_G;
4735 }
4736 else if((bSupportMode & WIRELESS_MODE_B))
4737 {
4738 wireless_mode = WIRELESS_MODE_B;
4739 }
4740 else{
4741 RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode);
4742 wireless_mode = WIRELESS_MODE_B;
4743 }
4744 }
4745#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA
4746 ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting );
4747#endif
4748#ifdef RTL8192SU
4749 //LZM 090306 usb crash here, mark it temp
4750 //write_nic_word(dev, SIFS_OFDM, 0x0e0e);
4751#endif
4752 priv->ieee80211->mode = wireless_mode;
4753
4754 if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G))
4755 priv->ieee80211->pHTInfo->bEnableHT = 1;
4756 else
4757 priv->ieee80211->pHTInfo->bEnableHT = 0;
4758 RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode);
4759 rtl8192_refresh_supportrate(priv);
4760#endif
4761
4762}
4763
4764
4765short rtl8192_is_tx_queue_empty(struct net_device *dev)
4766{
4767 int i=0;
4768 struct r8192_priv *priv = ieee80211_priv(dev);
4769 //struct ieee80211_device* ieee = priv->ieee80211;
4770 for (i=0; i<=MGNT_QUEUE; i++)
4771 {
4772 if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) )
4773 continue;
4774 if (atomic_read(&priv->tx_pending[i]))
4775 {
4776 printk("===>tx queue is not empty:%d, %d\n", i, atomic_read(&priv->tx_pending[i]));
4777 return 0;
4778 }
4779 }
4780 return 1;
4781}
4782#if 0
4783void rtl8192_rq_tx_ack(struct net_device *dev)
4784{
4785 struct r8192_priv *priv = ieee80211_priv(dev);
4786 priv->ieee80211->ack_tx_to_ieee = 1;
4787}
4788#endif
4789void rtl8192_hw_sleep_down(struct net_device *dev)
4790{
4791 RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__);
4792#ifdef TODO
4793// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4794#endif
4795}
4796#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
4797void rtl8192_hw_sleep_wq (struct work_struct *work)
4798{
4799// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4800// struct ieee80211_device * ieee = (struct ieee80211_device*)
4801// container_of(work, struct ieee80211_device, watch_dog_wq);
4802 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4803 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
4804 struct net_device *dev = ieee->dev;
4805#else
4806void rtl8192_hw_sleep_wq(struct net_device* dev)
4807{
4808#endif
4809 //printk("=========>%s()\n", __FUNCTION__);
4810 rtl8192_hw_sleep_down(dev);
4811}
4812// printk("dev is %d\n",dev);
4813// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__);
4814void rtl8192_hw_wakeup(struct net_device* dev)
4815{
4816// u32 flags = 0;
4817
4818// spin_lock_irqsave(&priv->ps_lock,flags);
4819 RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__);
4820#ifdef TODO
4821// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
4822#endif
4823 //FIXME: will we send package stored while nic is sleep?
4824// spin_unlock_irqrestore(&priv->ps_lock,flags);
4825}
4826#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
4827void rtl8192_hw_wakeup_wq (struct work_struct *work)
4828{
4829// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
4830// struct ieee80211_device * ieee = (struct ieee80211_device*)
4831// container_of(work, struct ieee80211_device, watch_dog_wq);
4832 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4833 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
4834 struct net_device *dev = ieee->dev;
4835#else
4836void rtl8192_hw_wakeup_wq(struct net_device* dev)
4837{
4838#endif
4839 rtl8192_hw_wakeup(dev);
4840
4841}
4842
4843#define MIN_SLEEP_TIME 50
4844#define MAX_SLEEP_TIME 10000
4845void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl)
4846{
4847
4848 struct r8192_priv *priv = ieee80211_priv(dev);
4849
4850 u32 rb = jiffies;
4851 unsigned long flags;
4852
4853 spin_lock_irqsave(&priv->ps_lock,flags);
4854
4855 /* Writing HW register with 0 equals to disable
4856 * the timer, that is not really what we want
4857 */
4858 tl -= MSECS(4+16+7);
4859
4860 //if(tl == 0) tl = 1;
4861
4862 /* FIXME HACK FIXME HACK */
4863// force_pci_posting(dev);
4864 //mdelay(1);
4865
4866// rb = read_nic_dword(dev, TSFTR);
4867
4868 /* If the interval in witch we are requested to sleep is too
4869 * short then give up and remain awake
4870 */
4871 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
4872 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
4873 spin_unlock_irqrestore(&priv->ps_lock,flags);
4874 printk("too short to sleep\n");
4875 return;
4876 }
4877
4878// write_nic_dword(dev, TimerInt, tl);
4879// rb = read_nic_dword(dev, TSFTR);
4880 {
4881 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
4882 // if (tl<rb)
4883
4884#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
4885 schedule_task(&priv->ieee80211->hw_wakeup_wq);
4886#else
4887 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
4888#endif
4889 }
4890 /* if we suspect the TimerInt is gone beyond tl
4891 * while setting it, then give up
4892 */
4893#if 1
4894 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
4895 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
4896 printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME));
4897 spin_unlock_irqrestore(&priv->ps_lock,flags);
4898 return;
4899 }
4900#endif
4901// if(priv->rf_sleep)
4902// priv->rf_sleep(dev);
4903
4904 //printk("<=========%s()\n", __FUNCTION__);
4905#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
4906 schedule_task(&priv->ieee80211->hw_sleep_wq);
4907#else
4908 queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0);
4909#endif
4910 spin_unlock_irqrestore(&priv->ps_lock,flags);
4911}
4912//init priv variables here. only non_zero value should be initialized here.
4913static void rtl8192_init_priv_variable(struct net_device* dev)
4914{
4915 struct r8192_priv *priv = ieee80211_priv(dev);
4916 u8 i;
4917 priv->card_8192 = NIC_8192U;
4918 priv->chan = 1; //set to channel 1
4919 priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
4920 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4921 priv->ieee80211->ieee_up=0;
4922 priv->retry_rts = DEFAULT_RETRY_RTS;
4923 priv->retry_data = DEFAULT_RETRY_DATA;
4924 priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD;
4925 priv->ieee80211->rate = 110; //11 mbps
4926 priv->ieee80211->short_slot = 1;
4927 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
4928 priv->CckPwEnl = 6;
4929 //for silent reset
4930 priv->IrpPendingCount = 1;
4931 priv->ResetProgress = RESET_TYPE_NORESET;
4932 priv->bForcedSilentReset = 0;
4933 priv->bDisableNormalResetCheck = false;
4934 priv->force_reset = false;
4935
4936 priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
4937 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4938 priv->ieee80211->iw_mode = IW_MODE_INFRA;
4939 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
4940 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
4941 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE |
4942 IEEE_SOFTMAC_BEACONS;//added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE;
4943
4944 priv->ieee80211->active_scan = 1;
4945 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION;
4946 priv->ieee80211->host_encrypt = 1;
4947 priv->ieee80211->host_decrypt = 1;
4948 priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604
4949 priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604
4950 priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit;
4951 priv->ieee80211->set_chan = rtl8192_set_chan;
4952 priv->ieee80211->link_change = priv->ops->rtl819x_link_change;
4953 priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit;
4954 priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop;
4955 priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume;
4956 priv->ieee80211->init_wmmparam_flag = 0;
4957 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
4958 priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc;
4959 priv->ieee80211->tx_headroom = TX_PACKET_SHIFT_BYTES;
4960 priv->ieee80211->qos_support = 1;
4961
4962 //added by WB
4963// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl;
4964 priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode;
4965 priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response;
4966 priv->ieee80211->handle_beacon = rtl8192_handle_beacon;
4967 //for LPS
4968 priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup;
4969// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack;
4970 priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep;
4971 priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty;
4972 //added by david
4973 priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8192;
4974 priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xUsb;
4975 priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode;
4976 //added by amy
4977 priv->ieee80211->InitialGainHandler = priv->ops->rtl819x_initial_gain;
4978 priv->card_type = USB;
4979
4980#ifdef RTL8192SU
4981//1 RTL8192SU/
4982 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
4983 priv->ieee80211->SetFwCmdHandler = HalSetFwCmd8192S;
4984 priv->bRFSiOrPi = 0;//o=si,1=pi;
4985 //lzm add
4986 priv->bInHctTest = false;
4987
4988 priv->MidHighPwrTHR_L1 = 0x3B;
4989 priv->MidHighPwrTHR_L2 = 0x40;
4990
4991 if(priv->bInHctTest)
4992 {
4993 priv->ShortRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4994 priv->LongRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
4995 }
4996 else
4997 {
4998 priv->ShortRetryLimit = HAL_RETRY_LIMIT_INFRA;
4999 priv->LongRetryLimit = HAL_RETRY_LIMIT_INFRA;
5000 }
5001
5002 priv->SetFwCmdInProgress = false; //is set FW CMD in Progress? 92S only
5003 priv->CurrentFwCmdIO = 0;
5004
5005 priv->MinSpaceCfg = 0;
5006
5007 priv->EarlyRxThreshold = 7;
5008 priv->enable_gpio0 = 0;
5009 priv->TransmitConfig =
5010 ((u32)TCR_MXDMA_2048<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
5011 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
5012 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
5013 (false ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
5014 if(priv->bInHctTest)
5015 priv->ReceiveConfig = //priv->CSMethod |
5016 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
5017 RCR_ACF |RCR_APPFCS| //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
5018 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
5019 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
5020 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
5021 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
5022 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
5023 (priv->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
5024 else
5025 priv->ReceiveConfig = //priv->CSMethod |
5026 RCR_AMF | RCR_ADF | RCR_AB |
5027 RCR_AM | RCR_APM |RCR_AAP |RCR_ADD3|RCR_APP_ICV|
5028 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
5029 RCR_APP_MIC | RCR_APPFCS;
5030
5031 // <Roger_EXP> 2008.06.16.
5032 priv->IntrMask = (u16)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \
5033 IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \
5034 IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \
5035 IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
5036
5037//1 End
5038
5039#else
5040
5041#ifdef TO_DO_LIST
5042 if(Adapter->bInHctTest)
5043 {
5044 pHalData->ShortRetryLimit = 7;
5045 pHalData->LongRetryLimit = 7;
5046 }
5047#endif
5048 {
5049 priv->ShortRetryLimit = 0x30;
5050 priv->LongRetryLimit = 0x30;
5051 }
5052 priv->EarlyRxThreshold = 7;
5053 priv->enable_gpio0 = 0;
5054 priv->TransmitConfig =
5055 // TCR_DurProcMode | //for RTL8185B, duration setting by HW
5056 //? TCR_DISReqQsize |
5057 (TCR_MXDMA_2048<<TCR_MXDMA_OFFSET)| // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
5058 (priv->ShortRetryLimit<<TCR_SRL_OFFSET)| // Short retry limit
5059 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
5060 (false ? TCR_SAT: 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
5061#ifdef TO_DO_LIST
5062 if(Adapter->bInHctTest)
5063 pHalData->ReceiveConfig = pHalData->CSMethod |
5064 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
5065 //guangan200710
5066 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
5067 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
5068 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
5069 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
5070 (pHalData->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
5071 (pHalData->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
5072 else
5073
5074#endif
5075 priv->ReceiveConfig =
5076 RCR_AMF | RCR_ADF | //accept management/data
5077 RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
5078 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
5079 //RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
5080 ((u32)7<<RCR_MXDMA_OFFSET)| // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
5081 (priv->EarlyRxThreshold<<RX_FIFO_THRESHOLD_SHIFT) | // Rx FIFO Threshold, 7: No Rx threshold.
5082 (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
5083#endif
5084
5085 priv->AcmControl = 0;
5086 priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware));
5087 if (priv->pFirmware)
5088 memset(priv->pFirmware, 0, sizeof(rt_firmware));
5089
5090 /* rx related queue */
5091 skb_queue_head_init(&priv->rx_queue);
5092 skb_queue_head_init(&priv->skb_queue);
5093
5094 /* Tx related queue */
5095 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
5096 skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]);
5097 }
5098 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
5099 skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]);
5100 }
5101 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
5102 skb_queue_head_init(&priv->ieee80211->skb_drv_aggQ [i]);
5103 }
5104 priv->rf_set_chan = rtl8192_phy_SwChnl;
5105}
5106
5107//init lock here
5108static void rtl8192_init_priv_lock(struct r8192_priv* priv)
5109{
5110 spin_lock_init(&priv->tx_lock);
5111 spin_lock_init(&priv->irq_lock);//added by thomas
5112 //spin_lock_init(&priv->rf_lock);//use rf_sem, or will crash in some OS.
5113 sema_init(&priv->wx_sem,1);
5114 sema_init(&priv->rf_sem,1);
5115 spin_lock_init(&priv->ps_lock);
5116#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
5117 sema_init(&priv->mutex, 1);
5118#else
5119 mutex_init(&priv->mutex);
5120#endif
5121}
5122
5123#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
5124extern void rtl819x_watchdog_wqcallback(struct work_struct *work);
5125#else
5126extern void rtl819x_watchdog_wqcallback(struct net_device *dev);
5127#endif
5128
5129void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
5130//init tasklet and wait_queue here. only 2.6 above kernel is considered
5131#define DRV_NAME "wlan0"
5132static void rtl8192_init_priv_task(struct net_device* dev)
5133{
5134 struct r8192_priv *priv = ieee80211_priv(dev);
5135
5136#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
5137#ifdef PF_SYNCTHREAD
5138 priv->priv_wq = create_workqueue(DRV_NAME,0);
5139#else
5140 priv->priv_wq = create_workqueue(DRV_NAME);
5141#endif
5142#endif
5143
5144#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
5145 INIT_WORK(&priv->reset_wq, rtl8192_restart);
5146
5147 //INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog);
5148 INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback);
5149 INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback);
5150// INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
5151 INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback);
5152 INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon);
5153 INIT_DELAYED_WORK(&priv->initialgain_operate_wq, InitialGainOperateWorkItemCallBack);
5154 //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem);
5155 //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem);
5156 INIT_WORK(&priv->qos_activate, rtl8192_qos_activate);
5157 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq);
5158 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq);
5159
5160#else
5161#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
5162 tq_init(&priv->reset_wq, (void*)rtl8192_restart, dev);
5163 tq_init(&priv->watch_dog_wq, (void*)rtl819x_watchdog_wqcallback, dev);
5164 tq_init(&priv->txpower_tracking_wq, (void*)dm_txpower_trackingcallback, dev);
5165 tq_init(&priv->rfpath_check_wq, (void*)dm_rf_pathcheck_workitemcallback, dev);
5166 tq_init(&priv->update_beacon_wq, (void*)rtl8192_update_beacon, dev);
5167 //tq_init(&priv->SwChnlWorkItem, (void*) rtl8192_SwChnl_WorkItem, dev);
5168 //tq_init(&priv->SetBWModeWorkItem, (void*)rtl8192_SetBWModeWorkItem, dev);
5169 tq_init(&priv->qos_activate, (void *)rtl8192_qos_activate, dev);
5170 tq_init(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev);
5171 tq_init(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev);
5172
5173#else
5174 INIT_WORK(&priv->reset_wq,(void(*)(void*)) rtl8192_restart,dev);
5175 //INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) hal_dm_watchdog,dev);
5176 INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) rtl819x_watchdog_wqcallback,dev);
5177 INIT_WORK(&priv->txpower_tracking_wq, (void(*)(void*)) dm_txpower_trackingcallback,dev);
5178// INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev);
5179 INIT_WORK(&priv->rfpath_check_wq, (void(*)(void*)) dm_rf_pathcheck_workitemcallback,dev);
5180 INIT_WORK(&priv->update_beacon_wq, (void(*)(void*))rtl8192_update_beacon,dev);
5181 INIT_WORK(&priv->initialgain_operate_wq, (void(*)(void*))InitialGainOperateWorkItemCallBack,dev);
5182 //INIT_WORK(&priv->SwChnlWorkItem, (void(*)(void*)) rtl8192_SwChnl_WorkItem, dev);
5183 //INIT_WORK(&priv->SetBWModeWorkItem, (void(*)(void*)) rtl8192_SetBWModeWorkItem, dev);
5184 INIT_WORK(&priv->qos_activate, (void(*)(void *))rtl8192_qos_activate, dev);
5185 INIT_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev);
5186 INIT_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev);
5187#endif
5188#endif
5189
5190 tasklet_init(&priv->irq_rx_tasklet,
5191 (void(*)(unsigned long))rtl8192_irq_rx_tasklet,
5192 (unsigned long)priv);
5193}
5194
5195static void rtl8192_get_eeprom_size(struct net_device* dev)
5196{
5197 u16 curCR = 0;
5198 struct r8192_priv *priv = ieee80211_priv(dev);
5199 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
5200 curCR = read_nic_word_E(dev,EPROM_CMD);
5201 RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);
5202 //whether need I consider BIT5?
5203 priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;
5204 RT_TRACE(COMP_EPROM, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
5205}
5206
5207//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead.
5208static inline u16 endian_swap(u16* data)
5209{
5210 u16 tmp = *data;
5211 *data = (tmp >> 8) | (tmp << 8);
5212 return *data;
5213}
5214
5215#ifdef RTL8192SU
5216u8 rtl8192SU_UsbOptionToEndPointNumber(u8 UsbOption)
5217{
5218 u8 nEndPoint = 0;
5219 switch(UsbOption)
5220 {
5221 case 0:
5222 nEndPoint = 6;
5223 break;
5224 case 1:
5225 nEndPoint = 11;
5226 break;
5227 case 2:
5228 nEndPoint = 4;
5229 break;
5230 default:
5231 RT_TRACE(COMP_INIT, "UsbOptionToEndPointNumber(): Invalid UsbOption(%#x)\n", UsbOption);
5232 break;
5233 }
5234 return nEndPoint;
5235}
5236
5237u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype)
5238{
5239 u8 RFtype = RF_1T2R;
5240
5241 switch(Boardtype)
5242 {
5243 case 0:
5244 RFtype = RF_1T1R;
5245 break;
5246 case 1:
5247 RFtype = RF_1T2R;
5248 break;
5249 case 2:
5250 RFtype = RF_2T2R;
5251 break;
5252 case 3:
5253 RFtype = RF_2T2R_GREEN;
5254 break;
5255 default:
5256 break;
5257 }
5258
5259 return RFtype;
5260}
5261
5262//
5263// Description:
5264// Config HW adapter information into initial value.
5265//
5266// Assumption:
5267// 1. After Auto load fail(i.e, check CR9346 fail)
5268//
5269// Created by Roger, 2008.10.21.
5270//
5271void
5272rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
5273{
5274 struct r8192_priv *priv = ieee80211_priv(dev);
5275 //u16 i,usValue;
5276 //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5277 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
5278 int i;
5279
5280 RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n");
5281
5282 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5283 //PlatformStallExecution(10000);
5284 mdelay(10);
5285 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5286
5287 //RT_ASSERT(priv->AutoloadFailFlag==TRUE, ("ReadAdapterInfo8192SEEPROM(): AutoloadFailFlag !=TRUE\n"));
5288
5289 // Initialize IC Version && Channel Plan
5290 priv->eeprom_vid = 0;
5291 priv->eeprom_pid = 0;
5292 priv->card_8192_version = 0;
5293 priv->eeprom_ChannelPlan = 0;
5294 priv->eeprom_CustomerID = 0;
5295 priv->eeprom_SubCustomerID = 0;
5296 priv->bIgnoreDiffRateTxPowerOffset = false;
5297
5298 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5299 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5300 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5301 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5302 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5303 RT_TRACE(COMP_INIT, "IgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
5304
5305
5306
5307 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5308 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5309
5310 for(i=0; i<5; i++)
5311 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
5312
5313 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("EFUSE USB PHY Param: \n"), priv->EEPROMUsbPhyParam, 5);
5314
5315 {
5316 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5317 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5318 u8 i;
5319
5320 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5321
5322 for(i = 0; i < 6; i++)
5323 dev->dev_addr[i] = sMacAddr[i];
5324 }
5325 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5326 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5327 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5328
5329 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5330 dev->dev_addr[0], dev->dev_addr[1],
5331 dev->dev_addr[2], dev->dev_addr[3],
5332 dev->dev_addr[4], dev->dev_addr[5]);
5333
5334 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5335 priv->rf_type = RF_1T2R; //RF_2T2R
5336 priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
5337 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5338 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5339 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5340 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5341 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5342 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5343
5344
5345#ifdef EEPROM_OLD_FORMAT_SUPPORT
5346 for(i=0; i<6; i++)
5347 {
5348 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5349 }
5350
5351 for(i=0; i<14; i++)
5352 {
5353 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5354 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5355 }
5356
5357 //
5358 // Update HAL variables.
5359 //
5360 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
5361 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
5362 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), priv->TxPowerLevelCCK, 14);
5363 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), priv->TxPowerLevelOFDM24G, 14);
5364#else
5365
5366 for (rf_path = 0; rf_path < 2; rf_path++)
5367 {
5368 for (i = 0; i < 3; i++)
5369 {
5370 // Read CCK RF A & B Tx power
5371 priv->RfCckChnlAreaTxPwr[rf_path][i] =
5372 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
5373 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
5374 (u8)(EEPROM_Default_TxPower & 0xff);
5375 }
5376 }
5377
5378 for (i = 0; i < 3; i++)
5379 {
5380 //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5381 //priv->RfCckChnlAreaTxPwr[rf_path][i]);
5382 //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5383 //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
5384 //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5385 //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
5386 }
5387
5388 // Assign dedicated channel tx power
5389 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5390 {
5391 if (i < 3) // Cjanel 1-3
5392 index = 0;
5393 else if (i < 9) // Channel 4-9
5394 index = 1;
5395 else // Channel 10-14
5396 index = 2;
5397
5398 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
5399 priv->RfTxPwrLevelCck[rf_path][i] =
5400 priv->RfCckChnlAreaTxPwr[rf_path][index];
5401 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
5402 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
5403 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
5404 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
5405 }
5406
5407 for(i=0; i<14; i++)
5408 {
5409 //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
5410 //rf_path, i, priv->RfTxPwrLevelCck[0][i],
5411 //priv->RfTxPwrLevelOfdm1T[0][i] ,
5412 //priv->RfTxPwrLevelOfdm2T[0][i] );
5413 }
5414#endif
5415
5416 //
5417 // Update remained HAL variables.
5418 //
5419 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5420 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;//new
5421 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
5422 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit0~3
5423 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit4~7
5424 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit12~15
5425 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5426 priv->LedStrategy = SW_LED_MODE0;
5427
5428 init_rate_adaptive(dev);
5429
5430 RT_TRACE(COMP_INIT, "<==== ConfigAdapterInfo8192SForAutoLoadFail\n");
5431
5432}
5433
5434#if 0
5435static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
5436{
5437 u16 EEPROMId = 0;
5438 u8 bLoad_From_EEPOM = false;
5439 struct r8192_priv *priv = ieee80211_priv(dev);
5440 u16 tmpValue = 0;
5441 u8 tmpBuffer[30];
5442 int i;
5443
5444 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
5445
5446
5447 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5448 udelay(10000);
5449 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
5450
5451
5452 EEPROMId = eprom_read(dev, 0); //first read EEPROM ID out;
5453 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", EEPROMId);
5454
5455 if (EEPROMId != RTL8190_EEPROM_ID)
5456 {
5457 priv->AutoloadFailFlag = true;
5458 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", EEPROMId, RTL8190_EEPROM_ID);
5459 }
5460 else
5461 {
5462 priv->AutoloadFailFlag = false;
5463 bLoad_From_EEPOM = true;
5464 }
5465
5466 if (bLoad_From_EEPOM)
5467 {
5468 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
5469 priv->eeprom_vid = endian_swap(&tmpValue);
5470 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
5471
5472 // Version ID, Channel plan
5473 tmpValue = eprom_read(dev, (EEPROM_Version>>1));
5474 //pHalData->card_8192_version = (VERSION_8192S)((usValue&0x00ff));
5475 priv->eeprom_ChannelPlan =(tmpValue&0xff00)>>8;
5476 priv->bTXPowerDataReadFromEEPORM = true;
5477
5478 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5479 tmpValue = eprom_read(dev, (u16)(EEPROM_CustomID>>1)) ;
5480 priv->eeprom_CustomerID = (u8)( tmpValue & 0xff);
5481 priv->eeprom_SubCustomerID = (u8)((tmpValue & 0xff00)>>8);
5482 }
5483 else
5484 {
5485 priv->eeprom_vid = 0;
5486 priv->eeprom_pid = 0;
5487 //priv->card_8192_version = VERSION_8192SU_A;
5488 priv->eeprom_ChannelPlan = 0;
5489 priv->eeprom_CustomerID = 0;
5490 priv->eeprom_SubCustomerID = 0;
5491 }
5492 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
5493 //set channelplan from eeprom
5494 priv->ChannelPlan = priv->eeprom_ChannelPlan;// FIXLZM
5495
5496 RT_TRACE(COMP_INIT, "EEPROMId = 0x%4x\n", EEPROMId);
5497 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5498 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5499 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
5500 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5501 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5502 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5503
5504 // Read USB optional function.
5505 if(bLoad_From_EEPOM)
5506 {
5507 tmpValue = eprom_read(dev, (EEPROM_USB_OPTIONAL>>1));
5508 priv->EEPROMUsbOption = (u8)(tmpValue&0xff);
5509 }
5510 else
5511 {
5512 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5513 }
5514
5515 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5516
5517
5518 if (bLoad_From_EEPOM)
5519 {
5520 int i;
5521 for (i=0; i<6; i+=2)
5522 {
5523 u16 tmp = 0;
5524 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
5525 *(u16*)(&dev->dev_addr[i]) = tmp;
5526 }
5527 }
5528 else
5529 {
5530 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5531 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5532 u8 i;
5533
5534 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5535
5536 for(i = 0; i < 6; i++)
5537 dev->dev_addr[i] = sMacAddr[i];
5538
5539 //memcpy(dev->dev_addr, sMacAddr, 6);
5540 //should I set IDR0 here?
5541 }
5542 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5543 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5544 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
5545
5546 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
5547#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
5548 priv->rf_chip = RF_6052;
5549 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5550 //priv->card_8192_version = VERSION_8192SU_A; //Over write for temporally experiment. 2008.10.16. By Roger.
5551#else
5552 priv->rf_chip = RF_8256;
5553#endif
5554
5555 {
5556#if 0
5557 if(bLoad_From_EEPOM)
5558 {
5559 tempval = (ReadEEprom(Adapter, (EEPROM_RFInd_PowerDiff>>1))) & 0xff;
5560 if (tempval&0x80) //RF-indication, bit[7]
5561 pHalData->RF_Type = RF_1T2R;
5562 else
5563 pHalData->RF_Type = RF_2T4R;
5564 }
5565#endif
5566
5567 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
5568 RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff);
5569
5570
5571 //
5572 // Read antenna tx power offset of B/C/D to A from EEPROM
5573 // and read ThermalMeter from EEPROM
5574 //
5575 if(bLoad_From_EEPOM)
5576 {
5577 tmpValue = eprom_read(dev, (EEPROM_PwDiff>>1));
5578 priv->EEPROMPwDiff = tmpValue&0x00ff;
5579 priv->EEPROMThermalMeter = (tmpValue&0xff00)>>8;
5580 }
5581 else
5582 {
5583 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
5584 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5585 }
5586 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
5587 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5588
5589 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5590
5591
5592 // Read CrystalCap from EEPROM
5593 if(bLoad_From_EEPOM)
5594 {
5595 priv->EEPROMCrystalCap =(u8) (((eprom_read(dev, (EEPROM_CrystalCap>>1)))&0xf000)>>12);
5596 }
5597 else
5598 {
5599 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5600 }
5601 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5602
5603
5604 //if(pHalData->EEPROM_Def_Ver == 0) // old eeprom definition
5605 {
5606
5607 //
5608 // Get Tx Power Base.//===>
5609 //
5610 if(bLoad_From_EEPOM)
5611 {
5612 priv->EEPROMTxPwrBase =(u8) ((eprom_read(dev, (EEPROM_TxPowerBase>>1)))&0xff);
5613 }
5614 else
5615 {
5616 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5617 }
5618
5619 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5620
5621 //
5622 // Get CustomerID(Boad Type)
5623 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5624 // Others: Reserved. Default is 0x2: RTL8192SU.
5625 //
5626 if(bLoad_From_EEPOM)
5627 {
5628 tmpValue = eprom_read(dev, (u16) (EEPROM_BoardType>>1));
5629 priv->EEPROMBoardType = (u8)(tmpValue&0xff);
5630 }
5631 else
5632 {
5633 priv->EEPROMBoardType = EEPROM_Default_BoardType;
5634 }
5635
5636 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
5637
5638#ifdef EEPROM_OLD_FORMAT_SUPPORT
5639
5640 //
5641 // Buffer TxPwIdx(i.e., from offset 0x58~0x75, total 30Bytes)
5642 //
5643 if(bLoad_From_EEPOM)
5644 {
5645 for(i = 0; i < 30; i += 2)
5646 {
5647 tmpValue = eprom_read(dev, (u16) ((EEPROM_TxPowerBase+i)>>1));
5648 *((u16 *)(&tmpBuffer[i])) = tmpValue;
5649 }
5650 }
5651
5652 //
5653 // Update CCK, OFDM Tx Power Index from above buffer.
5654 //
5655 if(bLoad_From_EEPOM)
5656 {
5657 for(i=0; i<14; i++)
5658 {
5659 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)tmpBuffer[i+1];
5660 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+15];
5661 }
5662
5663 }
5664 else
5665 {
5666 for(i=0; i<14; i++)
5667 {
5668 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5669 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5670 }
5671 }
5672
5673 for(i=0; i<14; i++)
5674 {
5675 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK24G[i]);
5676 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]);
5677 }
5678#else
5679 // Please add code in the section!!!!
5680 // And merge tx power difference section.
5681#endif
5682
5683 //
5684 // Get TSSI value for each path.
5685 //
5686 if(bLoad_From_EEPOM)
5687 {
5688 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_A)>>1));
5689 priv->EEPROMTSSI_A = (u8)((tmpValue&0xff00)>>8);
5690 }
5691 else
5692 { // Default setting for Empty EEPROM
5693 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5694 }
5695
5696 if(bLoad_From_EEPOM)
5697 {
5698 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_B)>>1));
5699 priv->EEPROMTSSI_B = (u8)(tmpValue&0xff);
5700 priv->EEPROMTxPwrTkMode = (u8)((tmpValue&0xff00)>>8);
5701 }
5702 else
5703 { // Default setting for Empty EEPROM
5704 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5705 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5706 }
5707
5708 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5709 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5710
5711#ifdef EEPROM_OLD_FORMAT_SUPPORT
5712 //
5713 // Get HT 2T Path A and B Power Index.
5714 //
5715 if(bLoad_From_EEPOM)
5716 {
5717 for(i = 0; i < 6; i += 2)
5718 {
5719 tmpValue = eprom_read(dev, (u16) ((EEPROM_HT2T_CH1_A+i)>>1));
5720 *((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = tmpValue;
5721 }
5722 }
5723 else
5724 { // Default setting for Empty EEPROM
5725 for(i=0; i<6; i++)
5726 {
5727 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5728 }
5729 }
5730
5731 for(i=0; i<6; i++)
5732 {
5733 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]);
5734 }
5735#else
5736
5737#endif
5738 }
5739
5740#ifdef EEPROM_OLD_FORMAT_SUPPORT
5741 //
5742 // Update HAL variables.
5743 //
5744 for(i=0; i<14; i++)
5745 {
5746 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
5747 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
5748 }
5749#else
5750
5751#endif
5752 priv->TxPowerDiff = priv->EEPROMPwDiff;
5753 // Antenna B gain offset to antenna A, bit0~3
5754 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
5755 // Antenna C gain offset to antenna A, bit4~7
5756 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
5757 // CrystalCap, bit12~15
5758 priv->CrystalCap = priv->EEPROMCrystalCap;
5759 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5760 // 92U does not enable TX power tracking.
5761 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
5762 }
5763
5764 priv->LedStrategy = SW_LED_MODE0;
5765
5766 if(priv->rf_type == RF_1T2R)
5767 {
5768 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
5769 }
5770 else
5771 {
5772 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
5773 }
5774
5775 // 2008/01/16 MH We can only know RF type in the function. So we have to init
5776 // DIG RATR table again.
5777 init_rate_adaptive(dev);
5778 //we need init DIG RATR table here again.
5779
5780 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
5781 return;
5782}
5783
5784//
5785// Description:
5786// 1. Read HW adapter information by E-Fuse.
5787// 2. Refered from SD1 Richard.
5788//
5789// Assumption:
5790// 1. Boot from E-Fuse and CR9346 regiser has verified.
5791// 2. PASSIVE_LEVEL (USB interface)
5792//
5793// Created by Roger, 2008.10.21.
5794//
5795void
5796rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
5797{
5798 struct r8192_priv *priv = ieee80211_priv(dev);
5799 u16 i,usValue;
5800 u16 EEPROMId;
5801 u8 readbyte;
5802 u8 OFDMTxPwr[14];
5803 u8 CCKTxPwr[14];
5804 u8 HT2T_TxPwr[6];
5805 u8 UsbPhyParam[5];
5806 u8 hwinfo[HWSET_MAX_SIZE_92S];
5807
5808
5809 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SEFuse\n");
5810
5811 //
5812 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
5813 // from suspend mode.
5814 // 2008.10.21.
5815 //
5816 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
5817 //PlatformStallExecution(10000);
5818 mdelay(10);
5819 write_nic_byte(dev, SYS_FUNC_EN+1, 0x40);
5820 write_nic_byte(dev, SYS_FUNC_EN+1, 0x50);
5821
5822 readbyte = read_nic_byte(dev, EFUSE_TEST+3);
5823 write_nic_byte(dev, EFUSE_TEST+3, (readbyte | 0x80));
5824 write_nic_byte(dev, EFUSE_TEST+3, 0x72);
5825 write_nic_byte(dev, EFUSE_CLK, 0x03);
5826
5827 //
5828 // Dump EFUSe at init time for later use
5829 //
5830 // Read EFUSE real map to shadow!!
5831 EFUSE_ShadowMapUpdate(dev);
5832
5833 memcpy(hwinfo, (void*)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
5834 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("MAP \n"), hwinfo, HWSET_MAX_SIZE_92S);
5835
5836 //
5837 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
5838 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
5839 // 2008.10.21.
5840 //
5841 ReadEFuse(dev, 0, 2, (unsigned char*) &EEPROMId);
5842
5843 if( EEPROMId != RTL8190_EEPROM_ID )
5844 {
5845 RT_TRACE(COMP_INIT, "EEPROM ID(%#x) is invalid!!\n", EEPROMId);
5846 priv->AutoloadFailFlag=true;
5847 }
5848 else
5849 {
5850 priv->AutoloadFailFlag=false;
5851 }
5852
5853 // Read IC Version && Channel Plan
5854 if(!priv->AutoloadFailFlag)
5855 {
5856
5857 // VID, PID
5858 ReadEFuse(dev, EEPROM_VID, 2, (unsigned char*) &priv->eeprom_vid);
5859 ReadEFuse(dev, EEPROM_PID, 2, (unsigned char*) &priv->eeprom_pid);
5860
5861 // Version ID, Channel plan
5862 ReadEFuse(dev, EEPROM_Version, 2, (unsigned char*) &usValue);
5863 //pHalData->VersionID = (VERSION_8192S)(usValue&0x00ff);
5864 priv->eeprom_ChannelPlan = (usValue&0xff00>>8);
5865 priv->bTXPowerDataReadFromEEPORM = true;
5866
5867 // Customer ID, 0x00 and 0xff are reserved for Realtek.
5868 ReadEFuse(dev, EEPROM_CustomID, 2, (unsigned char*) &usValue);
5869 priv->eeprom_CustomerID = (u8)( usValue & 0xff);
5870 priv->eeprom_SubCustomerID = (u8)((usValue & 0xff00)>>8);
5871 }
5872 else
5873 {
5874 priv->eeprom_vid = 0;
5875 priv->eeprom_pid = 0;
5876 priv->eeprom_ChannelPlan = 0;
5877 priv->eeprom_CustomerID = 0;
5878 priv->eeprom_SubCustomerID = 0;
5879 }
5880
5881 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
5882 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
5883 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
5884 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
5885 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
5886 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
5887 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
5888
5889
5890 // Read USB optional function.
5891 if(!priv->AutoloadFailFlag)
5892 {
5893 ReadEFuse(dev, EEPROM_USB_OPTIONAL, 1, (unsigned char*) &priv->EEPROMUsbOption);
5894 }
5895 else
5896 {
5897 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
5898 }
5899
5900 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
5901
5902
5903 // Read USB PHY parameters.
5904 if(!priv->AutoloadFailFlag)
5905 {
5906 ReadEFuse(dev, EEPROM_USB_PHY_PARA1, 5, (unsigned char*)UsbPhyParam);
5907 for(i=0; i<5; i++)
5908 {
5909 priv->EEPROMUsbPhyParam[i] = UsbPhyParam[i];
5910 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5911 }
5912 }
5913 else
5914 {
5915 for(i=0; i<5; i++)
5916 {
5917 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
5918 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
5919 }
5920 }
5921
5922
5923 //Read Permanent MAC address
5924 if(!priv->AutoloadFailFlag)
5925 {
5926 u8 macaddr[6] = {0x00, 0xe1, 0x86, 0x4c, 0x92, 0x00};
5927
5928 ReadEFuse(dev, EEPROM_NODE_ADDRESS_BYTE_0, 6, (unsigned char*)macaddr);
5929 for(i=0; i<6; i++)
5930 dev->dev_addr[i] = macaddr[i];
5931 }
5932 else
5933 {//Auto load fail
5934
5935 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
5936 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
5937 u8 i;
5938
5939 //if(!Adapter->bInHctTest)
5940 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
5941
5942 for(i = 0; i < 6; i++)
5943 dev->dev_addr[i] = sMacAddr[i];
5944 }
5945
5946 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
5947 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
5948 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
5949
5950 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
5951 dev->dev_addr[0], dev->dev_addr[1],
5952 dev->dev_addr[2], dev->dev_addr[3],
5953 dev->dev_addr[4], dev->dev_addr[5]);
5954
5955 // 2007/11/15 MH For RTL8192USB we assign as 1T2R now.
5956 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; // default : 1T2R
5957
5958#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
5959 priv->rf_chip = RF_6052;
5960 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5961#else
5962 priv->rf_chip = RF_8256;
5963#endif
5964
5965 {
5966 //
5967 // Read antenna tx power offset of B/C/D to A from EEPROM
5968 // and read ThermalMeter from EEPROM
5969 //
5970 if(!priv->AutoloadFailFlag)
5971 {
5972 ReadEFuse(dev, EEPROM_PwDiff, 2, (unsigned char*) &usValue);
5973 priv->EEPROMPwDiff = usValue&0x00ff;
5974 priv->EEPROMThermalMeter = (usValue&0xff00)>>8;
5975 }
5976 else
5977 {
5978 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
5979 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5980 }
5981
5982 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
5983 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5984
5985 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5986
5987 //
5988 // Read Tx Power gain offset of legacy OFDM to HT rate.
5989 // Read CrystalCap from EEPROM
5990 //
5991 if(!priv->AutoloadFailFlag)
5992 {
5993 ReadEFuse(dev, EEPROM_CrystalCap, 1, (unsigned char*) &usValue);
5994 priv->EEPROMCrystalCap = (u8)((usValue&0xf0)>>4);
5995 }
5996 else
5997 {
5998 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5999 }
6000
6001 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
6002
6003 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
6004 RT_TRACE(COMP_INIT, "TxPowerDiff = %d\n", priv->EEPROMTxPowerDiff);
6005
6006
6007 //
6008 // Get Tx Power Base.
6009 //
6010 if(!priv->AutoloadFailFlag)
6011 {
6012 ReadEFuse(dev, EEPROM_TxPowerBase, 1, (unsigned char*) &priv->EEPROMTxPwrBase );
6013 }
6014 else
6015 {
6016 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
6017 }
6018
6019 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
6020
6021 //
6022 // Get CustomerID(Boad Type)
6023 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
6024 // Others: Reserved. Default is 0x2: RTL8192SU.
6025 //
6026 if(!priv->AutoloadFailFlag)
6027 {
6028 ReadEFuse(dev, EEPROM_BoardType, 1, (unsigned char*) &priv->EEPROMBoardType );
6029 }
6030 else
6031 {
6032 priv->EEPROMBoardType = EEPROM_Default_BoardType;
6033 }
6034
6035 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
6036
6037 //if(pHalData->EEPROM_Def_Ver == 0)
6038 {
6039#ifdef EEPROM_OLD_FORMAT_SUPPORT
6040 //
6041 // Get CCK Tx Power Index.
6042 //
6043 if(!priv->AutoloadFailFlag)
6044 {
6045 ReadEFuse(dev, EEPROM_TxPwIndex_CCK_24G, 14, (unsigned char*)CCKTxPwr);
6046 for(i=0; i<14; i++)
6047 {
6048 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, CCKTxPwr[i]);
6049 priv->EEPROMTxPowerLevelCCK24G[i] = CCKTxPwr[i];
6050 }
6051 }
6052 else
6053 { // Default setting for Empty EEPROM
6054 for(i=0; i<14; i++)
6055 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
6056 }
6057
6058 //
6059 // Get OFDM Tx Power Index.
6060 //
6061 if(!priv->AutoloadFailFlag)
6062 {
6063 ReadEFuse(dev, EEPROM_TxPwIndex_OFDM_24G, 14, (unsigned char*)OFDMTxPwr);
6064 for(i=0; i<14; i++)
6065 {
6066 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, OFDMTxPwr[i]);
6067 priv->EEPROMTxPowerLevelOFDM24G[i] = OFDMTxPwr[i];
6068 }
6069 }
6070 else
6071 { // Default setting for Empty EEPROM
6072 usValue = 0x10;
6073 for(i=0; i<14; i++)
6074 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)usValue;
6075 }
6076#else
6077 // Please add code in the section!!!!
6078 // And merge tx power difference section.
6079#endif
6080
6081 //
6082 // Get TSSI value for each path.
6083 //
6084 if(!priv->AutoloadFailFlag)
6085 {
6086 ReadEFuse(dev, EEPROM_TSSI_A, 2, (unsigned char*)&usValue);
6087 priv->EEPROMTSSI_A = (u8)(usValue&0xff);
6088 priv->EEPROMTSSI_B = (u8)((usValue&0xff00)>>8);
6089 }
6090 else
6091 { // Default setting for Empty EEPROM
6092 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
6093 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
6094 }
6095
6096 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n",
6097 priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
6098
6099 //
6100 // Get Tx Power tracking mode.
6101 //
6102 if(!priv->AutoloadFailFlag)
6103 {
6104 ReadEFuse(dev, EEPROM_TxPwTkMode, 1, (unsigned char*)&priv->EEPROMTxPwrTkMode);
6105 }
6106 else
6107 { // Default setting for Empty EEPROM
6108 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
6109 }
6110
6111 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
6112
6113
6114 // TODO: The following HT 2T Path A and B Power Index should be updated.!! Added by Roger, 2008.20.23.
6115
6116 //
6117 // Get HT 2T Path A and B Power Index.
6118 //
6119 if(!priv->AutoloadFailFlag)
6120 {
6121 ReadEFuse(dev, EEPROM_HT2T_CH1_A, 6, (unsigned char*)HT2T_TxPwr);
6122 for(i=0; i<6; i++)
6123 {
6124 priv->EEPROMHT2T_TxPwr[i] = HT2T_TxPwr[i];
6125 }
6126 }
6127 else
6128 { // Default setting for Empty EEPROM
6129 for(i=0; i<6; i++)
6130 {
6131 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
6132 }
6133 }
6134
6135 for(i=0; i<6; i++)
6136 {
6137 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n",
6138 i, priv->EEPROMHT2T_TxPwr[i]);
6139 }
6140 }
6141
6142#ifdef EEPROM_OLD_FORMAT_SUPPORT
6143 //
6144 // Update HAL variables.
6145 //
6146 for(i=0; i<14; i++)
6147 {
6148 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
6149 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
6150 }
6151#else
6152
6153#endif
6154 priv->TxPowerDiff = priv->EEPROMPwDiff;
6155 // Antenna B gain offset to antenna A, bit0~3
6156 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
6157 // Antenna C gain offset to antenna A, bit4~7
6158 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
6159 // CrystalCap, bit12~15
6160 priv->CrystalCap = priv->EEPROMCrystalCap;
6161 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
6162 // 92U does not enable TX power tracking.
6163 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
6164 }
6165
6166 priv->LedStrategy = SW_LED_MODE0;
6167
6168 init_rate_adaptive(dev);
6169
6170 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SEFuse\n");
6171
6172}
6173#endif
6174
6175//
6176// Description:
6177// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
6178//
6179// Assumption:
6180// 1. CR9346 regiser has verified.
6181// 2. PASSIVE_LEVEL (USB interface)
6182//
6183// Created by Roger, 2008.10.21.
6184//
6185void
6186rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
6187{
6188 struct r8192_priv *priv = ieee80211_priv(dev);
6189 u16 i,usValue;
6190 u8 tmpU1b, tempval;
6191 u16 EEPROMId;
6192 u8 hwinfo[HWSET_MAX_SIZE_92S];
6193 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
6194
6195
6196 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
6197
6198 //
6199 // <Roger_Note> The following operation are prevent Efuse leakage by turn on 2.5V.
6200 // 2008.11.25.
6201 //
6202 tmpU1b = read_nic_byte(dev, EFUSE_TEST+3);
6203 write_nic_byte(dev, EFUSE_TEST+3, tmpU1b|0x80);
6204 //PlatformStallExecution(1000);
6205 mdelay(10);
6206 write_nic_byte(dev, EFUSE_TEST+3, (tmpU1b&(~BIT7)));
6207
6208 // Retrieve Chip version.
6209 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
6210 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
6211
6212 switch(priv->card_8192_version)
6213 {
6214 case 0:
6215 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_ACUT.\n");
6216 break;
6217 case 1:
6218 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_BCUT.\n");
6219 break;
6220 case 2:
6221 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_CCUT.\n");
6222 break;
6223 default:
6224 RT_TRACE(COMP_INIT, "Unknown Chip Version!!\n");
6225 priv->card_8192_version = VERSION_8192S_BCUT;
6226 break;
6227 }
6228
6229 //if (IS_BOOT_FROM_EEPROM(Adapter))
6230 if(priv->EepromOrEfuse)
6231 { // Read frin EEPROM
6232 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
6233 //PlatformStallExecution(10000);
6234 mdelay(10);
6235 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
6236 // Read all Content from EEPROM or EFUSE.
6237 for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2)
6238 {
6239 usValue = eprom_read(dev, (u16) (i>>1));
6240 *((u16*)(&hwinfo[i])) = usValue;
6241 }
6242 }
6243 else if (!(priv->EepromOrEfuse))
6244 { // Read from EFUSE
6245
6246 //
6247 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
6248 // from suspend mode.
6249 // 2008.10.21.
6250 //
6251 //PlatformEFIOWrite1Byte(Adapter, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
6252 //PlatformStallExecution(10000);
6253 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x40);
6254 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x50);
6255
6256 //tmpU1b = PlatformEFIORead1Byte(Adapter, EFUSE_TEST+3);
6257 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, (tmpU1b | 0x80));
6258 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, 0x72);
6259 //PlatformEFIOWrite1Byte(Adapter, EFUSE_CLK, 0x03);
6260
6261 // Read EFUSE real map to shadow.
6262 EFUSE_ShadowMapUpdate(dev);
6263 memcpy(hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
6264 }
6265 else
6266 {
6267 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SUsb(): Invalid boot type!!\n");
6268 }
6269
6270 //YJ,test,090106
6271 //dump_buf(hwinfo,HWSET_MAX_SIZE_92S);
6272 //
6273 // <Roger_Notes> The following are EFUSE/EEPROM independent operations!!
6274 //
6275 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("MAP: \n"), hwinfo, HWSET_MAX_SIZE_92S);
6276
6277 //
6278 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
6279 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
6280 // 2008.10.21.
6281 //
6282 EEPROMId = *((u16 *)&hwinfo[0]);
6283
6284 if( EEPROMId != RTL8190_EEPROM_ID )
6285 {
6286 RT_TRACE(COMP_INIT, "ID(%#x) is invalid!!\n", EEPROMId);
6287 priv->bTXPowerDataReadFromEEPORM = FALSE;
6288 priv->AutoloadFailFlag=TRUE;
6289 }
6290 else
6291 {
6292 priv->AutoloadFailFlag=FALSE;
6293#if RTL8192SU_USE_PARAM_TXPWR
6294 priv->bTXPowerDataReadFromEEPORM = FALSE;
6295#else
6296 priv->bTXPowerDataReadFromEEPORM = TRUE;
6297#endif
6298
6299 }
6300 // Read IC Version && Channel Plan
6301 if(!priv->AutoloadFailFlag)
6302 {
6303 // VID, PID
6304 priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
6305 priv->eeprom_pid = *(u16 *)&hwinfo[EEPROM_PID];
6306 priv->bIgnoreDiffRateTxPowerOffset = false; //cosa for test
6307
6308
6309 // EEPROM Version ID, Channel plan
6310 priv->EEPROMVersion = *(u8 *)&hwinfo[EEPROM_Version];
6311 priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan];
6312
6313 // Customer ID, 0x00 and 0xff are reserved for Realtek.
6314 priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID];
6315 priv->eeprom_SubCustomerID = *(u8 *)&hwinfo[EEPROM_SubCustomID];
6316 }
6317 else
6318 {
6319 //priv->eeprom_vid = 0;
6320 //priv->eeprom_pid = 0;
6321 //priv->EEPROMVersion = 0;
6322 //priv->eeprom_ChannelPlan = 0;
6323 //priv->eeprom_CustomerID = 0;
6324 //priv->eeprom_SubCustomerID = 0;
6325
6326 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
6327 return;
6328 }
6329
6330
6331 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
6332 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
6333 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
6334 RT_TRACE(COMP_INIT, "EEPROM Version ID: 0x%2x\n", priv->EEPROMVersion);
6335 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
6336 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
6337 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
6338 RT_TRACE(COMP_INIT, "bIgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
6339
6340
6341 // Read USB optional function.
6342 if(!priv->AutoloadFailFlag)
6343 {
6344 priv->EEPROMUsbOption = *(u8 *)&hwinfo[EEPROM_USB_OPTIONAL];
6345 }
6346 else
6347 {
6348 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
6349 }
6350
6351
6352 priv->EEPROMUsbEndPointNumber = rtl8192SU_UsbOptionToEndPointNumber((priv->EEPROMUsbOption&EEPROM_EP_NUMBER)>>3);
6353
6354 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
6355 RT_TRACE(COMP_INIT, "EndPoint Number = %#x\n", priv->EEPROMUsbEndPointNumber);
6356
6357#ifdef TO_DO_LIST
6358 //
6359 // Decide CustomerID according to VID/DID or EEPROM
6360 //
6361 switch(pHalData->EEPROMCustomerID)
6362 {
6363 case EEPROM_CID_ALPHA:
6364 pMgntInfo->CustomerID = RT_CID_819x_ALPHA;
6365 break;
6366
6367 case EEPROM_CID_CAMEO:
6368 pMgntInfo->CustomerID = RT_CID_819x_CAMEO;
6369 break;
6370
6371 case EEPROM_CID_SITECOM:
6372 pMgntInfo->CustomerID = RT_CID_819x_Sitecom;
6373 RT_TRACE(COMP_INIT, DBG_LOUD, ("CustomerID = 0x%4x\n", pMgntInfo->CustomerID));
6374
6375 break;
6376
6377 case EEPROM_CID_WHQL:
6378 Adapter->bInHctTest = TRUE;
6379
6380 pMgntInfo->bSupportTurboMode = FALSE;
6381 pMgntInfo->bAutoTurboBy8186 = FALSE;
6382
6383 pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
6384 pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
6385 pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
6386 pMgntInfo->keepAliveLevel = 0;
6387 break;
6388
6389 default:
6390 pMgntInfo->CustomerID = RT_CID_DEFAULT;
6391 break;
6392
6393 }
6394
6395 //
6396 // Led mode
6397 //
6398 switch(pMgntInfo->CustomerID)
6399 {
6400 case RT_CID_DEFAULT:
6401 case RT_CID_819x_ALPHA:
6402 pHalData->LedStrategy = SW_LED_MODE1;
6403 pHalData->bRegUseLed = TRUE;
6404 pHalData->SwLed1.bLedOn = TRUE;
6405 break;
6406 case RT_CID_819x_CAMEO:
6407 pHalData->LedStrategy = SW_LED_MODE1;
6408 pHalData->bRegUseLed = TRUE;
6409 break;
6410
6411 case RT_CID_819x_Sitecom:
6412 pHalData->LedStrategy = SW_LED_MODE2;
6413 pHalData->bRegUseLed = TRUE;
6414 break;
6415
6416 default:
6417 pHalData->LedStrategy = SW_LED_MODE0;
6418 break;
6419 }
6420#endif
6421
6422 // Read USB PHY parameters.
6423 for(i=0; i<5; i++)
6424 priv->EEPROMUsbPhyParam[i] = *(u8 *)&hwinfo[EEPROM_USB_PHY_PARA1+i];
6425
6426 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("USB PHY Param: \n"), pHalData->EEPROMUsbPhyParam, 5);
6427
6428
6429 //Read Permanent MAC address
6430 for(i=0; i<6; i++)
6431 dev->dev_addr[i] = *(u8 *)&hwinfo[EEPROM_NODE_ADDRESS_BYTE_0+i];
6432
6433 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
6434 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
6435 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
6436
6437 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
6438 dev->dev_addr[0], dev->dev_addr[1],
6439 dev->dev_addr[2], dev->dev_addr[3],
6440 dev->dev_addr[4], dev->dev_addr[5]);
6441
6442 //
6443 // Get CustomerID(Boad Type)
6444 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
6445 // Others: Reserved. Default is 0x2: RTL8192SU.
6446 //
6447 //if(!priv->AutoloadFailFlag)
6448 //{
6449 priv->EEPROMBoardType = *(u8 *)&hwinfo[EEPROM_BoardType];
6450 priv->rf_type = rtl8192SU_BoardTypeToRFtype(dev, priv->EEPROMBoardType);
6451 //}
6452 //else
6453 //{
6454 // priv->EEPROMBoardType = EEPROM_Default_BoardType;
6455 // priv->rf_type = RF_1T2R;
6456 //}
6457
6458#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
6459 priv->rf_chip = RF_6052;
6460#else
6461 priv->rf_chip = RF_8256;
6462#endif
6463
6464 priv->rf_chip = RF_6052;//lzm test
6465 RT_TRACE(COMP_INIT, "BoardType = 0x%2x\n", priv->EEPROMBoardType);
6466 RT_TRACE(COMP_INIT, "RF_Type = 0x%2x\n", priv->rf_type);
6467
6468 //
6469 // Read antenna tx power offset of B/C/D to A from EEPROM
6470 // and read ThermalMeter from EEPROM
6471 //
6472 //if(!priv->AutoloadFailFlag)
6473 {
6474 priv->EEPROMTxPowerDiff = *(u8 *)&hwinfo[EEPROM_PwDiff];
6475 priv->EEPROMThermalMeter = *(u8 *)&hwinfo[EEPROM_ThermalMeter];
6476 }
6477 //else
6478 //{
6479 // priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
6480 // priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
6481 //}
6482
6483 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMTxPowerDiff);
6484 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
6485
6486 //
6487 // Read Tx Power gain offset of legacy OFDM to HT rate.
6488 // Read CrystalCap from EEPROM
6489 //
6490 //if(!priv->AutoloadFailFlag)
6491 {
6492 priv->EEPROMCrystalCap = *(u8 *)&hwinfo[EEPROM_CrystalCap];
6493 }
6494 //else
6495 //{
6496 // priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
6497 //}
6498
6499 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
6500
6501 //
6502 // Get Tx Power Base.
6503 //
6504 //if(!priv->AutoloadFailFlag)
6505 {
6506 priv->EEPROMTxPwrBase = *(u8 *)&hwinfo[EEPROM_TxPowerBase];
6507 }
6508 //else
6509 //{
6510 // priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
6511 //}
6512
6513 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
6514
6515
6516 //
6517 // Get TSSI value for each path.
6518 //
6519 //if(!priv->AutoloadFailFlag)
6520 {
6521 priv->EEPROMTSSI_A = *(u8 *)&hwinfo[EEPROM_TSSI_A];
6522 priv->EEPROMTSSI_B = *(u8 *)&hwinfo[EEPROM_TSSI_B];
6523 }
6524 //else
6525 //{ // Default setting for Empty EEPROM
6526 // priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
6527 // priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
6528 //}
6529
6530 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
6531
6532 //
6533 // Get Tx Power tracking mode.
6534 //
6535 //if(!priv->AutoloadFailFlag)
6536 {
6537 priv->EEPROMTxPwrTkMode = *(u8 *)&hwinfo[EEPROM_TxPwTkMode];
6538 }
6539
6540 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
6541
6542
6543#ifdef EEPROM_OLD_FORMAT_SUPPORT
6544
6545 //
6546 // <Roger_Notes> The following settings are EFUSE version dependence.
6547 // So we need to adjust reading offset.
6548 // 2008.11.22.
6549 //
6550 {
6551 //
6552 // Get HT 2T Path A and B Power Index.
6553 //
6554 //if(!priv->AutoloadFailFlag)
6555 {
6556 for(i=0; i<6; i++)
6557 {
6558 priv->EEPROMHT2T_TxPwr[i] = *(u8 *)&hwinfo[EEPROM_HT2T_CH1_A+i];
6559 }
6560 }
6561
6562 //RT_PRINT_DATA(COMP_EFUSE, "HT2T TxPwr: \n"), pHalData->EEPROMHT2T_TxPwr, 6);
6563
6564 //
6565 // Get CCK and OFDM Tx Power Index.
6566 //
6567 //if(!priv->AutoloadFailFlag)
6568 {
6569 for(i=0; i<14; i++)
6570 {
6571 priv->EEPROMTxPowerLevelCCK24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_CCK_24G+i];
6572 priv->EEPROMTxPowerLevelOFDM24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_OFDM_24G+i];
6573 }
6574 }
6575
6576 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("CCK 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelCCK24G, 14);
6577 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("OFDM 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelOFDM24G, 14);
6578
6579 //
6580 // Update HAL variables.
6581 //
6582 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
6583 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
6584 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), pHalData->TxPowerLevelCCK, 14);
6585 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), pHalData->TxPowerLevelOFDM24G, 14);
6586
6587 }
6588#else // Support new version of EFUSE content, 2008.11.22.
6589 {
6590 //
6591 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
6592 // Update CCK, OFDM (1T/2T)Tx Power Index from above buffer.
6593 //
6594
6595 //
6596 // Get Tx Power Level by Channel
6597 //
6598 //if(!priv->AutoloadFailFlag)
6599 {
6600 // Read Tx power of Channel 1 ~ 14 from EFUSE.
6601 // 92S suupport RF A & B
6602 for (rf_path = 0; rf_path < 2; rf_path++)
6603 {
6604 for (i = 0; i < 3; i++)
6605 {
6606 // Read CCK RF A & B Tx power
6607 priv->RfCckChnlAreaTxPwr[rf_path][i] =
6608 hwinfo[EEPROM_TxPwIndex+rf_path*3+i];
6609
6610 // Read OFDM RF A & B Tx power for 1T
6611 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
6612 hwinfo[EEPROM_TxPwIndex+6+rf_path*3+i];
6613
6614 // Read OFDM RF A & B Tx power for 2T
6615 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
6616 hwinfo[EEPROM_TxPwIndex+12+rf_path*3+i];
6617 }
6618 }
6619
6620 }
6621//
6622 // Update Tx Power HAL variables.
6623//
6624 for (rf_path = 0; rf_path < 2; rf_path++)
6625 {
6626 for (i = 0; i < 3; i++)
6627 {
6628 RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
6629 priv->RfCckChnlAreaTxPwr[rf_path][i]);
6630 RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
6631 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
6632 RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
6633 }
6634
6635 // Assign dedicated channel tx power
6636 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
6637 {
6638 if (i < 3) // Cjanel 1-3
6639 index = 0;
6640 else if (i < 9) // Channel 4-9
6641 index = 1;
6642 else // Channel 10-14
6643 index = 2;
6644
6645 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
6646 priv->RfTxPwrLevelCck[rf_path][i] =
6647 priv->RfCckChnlAreaTxPwr[rf_path][index];
6648 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
6649 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
6650 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
6651 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
6652 if (rf_path == 0)
6653 {
6654 priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ;
6655 priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i];
6656 }
6657 }
6658
6659 for(i=0; i<14; i++)
6660 {
6661 RT_TRACE((COMP_INIT),
6662 "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
6663 rf_path, i, priv->RfTxPwrLevelCck[rf_path][i],
6664 priv->RfTxPwrLevelOfdm1T[rf_path][i] ,
6665 priv->RfTxPwrLevelOfdm2T[rf_path][i] );
6666 }
6667 }
6668 }
6669
6670 //
6671 // 2009/02/09 Cosa add for new EEPROM format
6672 //
6673 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
6674 {
6675 // Read tx power difference between HT OFDM 20/40 MHZ
6676 if (i < 3) // Cjanel 1-3
6677 index = 0;
6678 else if (i < 9) // Channel 4-9
6679 index = 1;
6680 else // Channel 10-14
6681 index = 2;
6682
6683 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff;
6684 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF);
6685 priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
6686
6687 // Read OFDM<->HT tx power diff
6688 if (i < 3) // Cjanel 1-3
6689 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF])&0xff;
6690 else if (i < 9) // Channel 4-9
6691 tempval = (*(u8 *)&hwinfo[EEPROM_PwDiff])&0xff;
6692 else // Channel 10-14
6693 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+1])&0xff;
6694
6695 //cosa tempval = (*(u1Byte *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff;
6696 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF);
6697 priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
6698
6699 //
6700 // Read Band Edge tx power offset and check if user enable the ability
6701 //
6702 // HT 40 band edge channel
6703 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE])&0xff;
6704 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6705 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6706 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+1])&0xff;
6707 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6708 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6709 // HT 20 band edge channel
6710 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+2])&0xff;
6711 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6712 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6713 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+3])&0xff;
6714 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6715 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6716 // OFDM band edge channel
6717 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+4])&0xff;
6718 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
6719 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
6720 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+5])&0xff;
6721 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
6722 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
6723
6724 priv->TxPwrbandEdgeFlag = (*(u8 *)&hwinfo[TX_PWR_BAND_EDGE_CHK]);
6725 }
6726
6727 for(i=0; i<14; i++)
6728 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]);
6729 for(i=0; i<14; i++)
6730 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]);
6731 for(i=0; i<14; i++)
6732 RT_TRACE(COMP_INIT, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]);
6733 for(i=0; i<14; i++)
6734 RT_TRACE(COMP_INIT, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]);
6735 RT_TRACE(COMP_INIT, "RF-A HT40 band-edge low/high power diff = 0x%x/0x%x\n",
6736 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0],
6737 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]);
6738 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT40 band-edge low/high power diff = 0x%x/0x%x\n",
6739 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0],
6740 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1]);
6741
6742 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A HT20 band-edge low/high power diff = 0x%x/0x%x\n",
6743 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0],
6744 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]);
6745 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT20 band-edge low/high power diff = 0x%x/0x%x\n",
6746 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0],
6747 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1]);
6748
6749 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A OFDM band-edge low/high power diff = 0x%x/0x%x\n",
6750 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0],
6751 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]);
6752 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B OFDM band-edge low/high power diff = 0x%x/0x%x\n",
6753 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
6754 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
6755 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
6756#endif
6757
6758 //
6759 // Update remained HAL variables.
6760 //
6761 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
6762 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;
6763 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
6764 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit[3:0]
6765 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit[7:4]
6766 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit[15:12]
6767 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f);// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
6768 priv->LedStrategy = SW_LED_MODE0;
6769
6770 init_rate_adaptive(dev);
6771
6772 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
6773
6774 //return RT_STATUS_SUCCESS;
6775}
6776
6777
6778//
6779// Description:
6780// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
6781//
6782// Assumption:
6783// 1. CR9346 regiser has verified.
6784// 2. PASSIVE_LEVEL (USB interface)
6785//
6786// Created by Roger, 2008.10.21.
6787//
6788static void rtl8192SU_read_eeprom_info(struct net_device *dev)
6789{
6790 struct r8192_priv *priv = ieee80211_priv(dev);
6791 u8 tmpU1b;
6792
6793 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
6794
6795 // Retrieve Chip version.
6796 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
6797 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
6798
6799 tmpU1b = read_nic_byte(dev, EPROM_CMD);//CR9346
6800
6801 // To check system boot selection.
6802 if (tmpU1b & CmdEERPOMSEL)
6803 {
6804 RT_TRACE(COMP_INIT, "Boot from EEPROM\n");
6805 priv->EepromOrEfuse = TRUE;
6806 }
6807 else
6808 {
6809 RT_TRACE(COMP_INIT, "Boot from EFUSE\n");
6810 priv->EepromOrEfuse = FALSE;
6811 }
6812
6813 // To check autoload success or not.
6814 if (tmpU1b & CmdEEPROM_En)
6815 {
6816 RT_TRACE(COMP_INIT, "Autoload OK!!\n");
6817 priv->AutoloadFailFlag=FALSE;
6818 rtl8192SU_ReadAdapterInfo8192SUsb(dev);//eeprom or e-fuse
6819 }
6820 else
6821 { // Auto load fail.
6822 RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n");
6823 priv->AutoloadFailFlag=TRUE;
6824 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
6825
6826 //if (IS_BOOT_FROM_EFUSE(Adapter))
6827 if(!priv->EepromOrEfuse)
6828 {
6829 RT_TRACE(COMP_INIT, "Update shadow map for EFuse future use!!\n");
6830 EFUSE_ShadowMapUpdate(dev);
6831 }
6832 }
6833#ifdef TO_DO_LIST
6834 if((priv->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
6835 {
6836 pMgntInfo->ChannelPlan = HalMapChannelPlan8192S(Adapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
6837 pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
6838 }
6839 else
6840 {
6841 pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
6842 }
6843
6844 switch(pMgntInfo->ChannelPlan)
6845 {
6846 case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
6847 {
6848 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
6849
6850 pDot11dInfo->bEnabled = TRUE;
6851 }
6852 RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
6853 break;
6854 }
6855
6856 RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
6857 RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
6858
6859 RT_TRACE(COMP_INIT, DBG_LOUD, ("<==== ReadAdapterInfo8192S\n"));
6860#endif
6861
6862 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
6863
6864 //return RT_STATUS_SUCCESS;
6865}
6866#else
6867static void rtl8192_read_eeprom_info(struct net_device* dev)
6868{
6869 u16 wEPROM_ID = 0;
6870 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x02};
6871 u8 bLoad_From_EEPOM = false;
6872 struct r8192_priv *priv = ieee80211_priv(dev);
6873 u16 tmpValue = 0;
6874 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
6875 wEPROM_ID = eprom_read(dev, 0); //first read EEPROM ID out;
6876 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", wEPROM_ID);
6877
6878 if (wEPROM_ID != RTL8190_EEPROM_ID)
6879 {
6880 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", wEPROM_ID, RTL8190_EEPROM_ID);
6881 }
6882 else
6883 bLoad_From_EEPOM = true;
6884
6885 if (bLoad_From_EEPOM)
6886 {
6887 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
6888 priv->eeprom_vid = endian_swap(&tmpValue);
6889 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
6890 tmpValue = eprom_read(dev, (EEPROM_ChannelPlan>>1));
6891 priv->eeprom_ChannelPlan =((tmpValue&0xff00)>>8);
6892 priv->btxpowerdata_readfromEEPORM = true;
6893 priv->eeprom_CustomerID = eprom_read(dev, (EEPROM_Customer_ID>>1)) >>8;
6894 }
6895 else
6896 {
6897 priv->eeprom_vid = 0;
6898 priv->eeprom_pid = 0;
6899 priv->card_8192_version = VERSION_819xU_B;
6900 priv->eeprom_ChannelPlan = 0;
6901 priv->eeprom_CustomerID = 0;
6902 }
6903 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
6904 //set channelplan from eeprom
6905 priv->ChannelPlan = priv->eeprom_ChannelPlan;
6906 if (bLoad_From_EEPOM)
6907 {
6908 int i;
6909 for (i=0; i<6; i+=2)
6910 {
6911 u16 tmp = 0;
6912 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
6913 *(u16*)(&dev->dev_addr[i]) = tmp;
6914 }
6915 }
6916 else
6917 {
6918 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
6919 //should I set IDR0 here?
6920 }
6921 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
6922 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
6923 priv->rf_chip = RF_8256;
6924
6925 if (priv->card_8192_version == (u8)VERSION_819xU_A)
6926 {
6927 //read Tx power gain offset of legacy OFDM to HT rate
6928 if (bLoad_From_EEPOM)
6929 priv->EEPROMTxPowerDiff = (eprom_read(dev, (EEPROM_TxPowerDiff>>1))&0xff00) >> 8;
6930 else
6931 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPower;
6932 RT_TRACE(COMP_EPROM, "TxPowerDiff:%d\n", priv->EEPROMTxPowerDiff);
6933 //read ThermalMeter from EEPROM
6934 if (bLoad_From_EEPOM)
6935 priv->EEPROMThermalMeter = (u8)(eprom_read(dev, (EEPROM_ThermalMeter>>1))&0x00ff);
6936 else
6937 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
6938 RT_TRACE(COMP_EPROM, "ThermalMeter:%d\n", priv->EEPROMThermalMeter);
6939 //vivi, for tx power track
6940 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
6941 //read antenna tx power offset of B/C/D to A from EEPROM
6942 if (bLoad_From_EEPOM)
6943 priv->EEPROMPwDiff = (eprom_read(dev, (EEPROM_PwDiff>>1))&0x0f00)>>8;
6944 else
6945 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
6946 RT_TRACE(COMP_EPROM, "TxPwDiff:%d\n", priv->EEPROMPwDiff);
6947 // Read CrystalCap from EEPROM
6948 if (bLoad_From_EEPOM)
6949 priv->EEPROMCrystalCap = (eprom_read(dev, (EEPROM_CrystalCap>>1))&0x0f);
6950 else
6951 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
6952 RT_TRACE(COMP_EPROM, "CrystalCap = %d\n", priv->EEPROMCrystalCap);
6953 //get per-channel Tx power level
6954 if (bLoad_From_EEPOM)
6955 priv->EEPROM_Def_Ver = (eprom_read(dev, (EEPROM_TxPwIndex_Ver>>1))&0xff00)>>8;
6956 else
6957 priv->EEPROM_Def_Ver = 1;
6958 RT_TRACE(COMP_EPROM, "EEPROM_DEF_VER:%d\n", priv->EEPROM_Def_Ver);
6959 if (priv->EEPROM_Def_Ver == 0) //old eeprom definition
6960 {
6961 int i;
6962 if (bLoad_From_EEPOM)
6963 priv->EEPROMTxPowerLevelCCK = (eprom_read(dev, (EEPROM_TxPwIndex_CCK>>1))&0xff) >> 8;
6964 else
6965 priv->EEPROMTxPowerLevelCCK = 0x10;
6966 RT_TRACE(COMP_EPROM, "CCK Tx Power Levl: 0x%02x\n", priv->EEPROMTxPowerLevelCCK);
6967 for (i=0; i<3; i++)
6968 {
6969 if (bLoad_From_EEPOM)
6970 {
6971 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G+i)>>1);
6972 if (((EEPROM_TxPwIndex_OFDM_24G+i) % 2) == 0)
6973 tmpValue = tmpValue & 0x00ff;
6974 else
6975 tmpValue = (tmpValue & 0xff00) >> 8;
6976 }
6977 else
6978 tmpValue = 0x10;
6979 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8) tmpValue;
6980 RT_TRACE(COMP_EPROM, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK);
6981 }
6982 }//end if EEPROM_DEF_VER == 0
6983 else if (priv->EEPROM_Def_Ver == 1)
6984 {
6985 if (bLoad_From_EEPOM)
6986 {
6987 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1>>1));
6988 tmpValue = (tmpValue & 0xff00) >> 8;
6989 }
6990 else
6991 tmpValue = 0x10;
6992 priv->EEPROMTxPowerLevelCCK_V1[0] = (u8)tmpValue;
6993
6994 if (bLoad_From_EEPOM)
6995 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1 + 2)>>1);
6996 else
6997 tmpValue = 0x1010;
6998 *((u16*)(&priv->EEPROMTxPowerLevelCCK_V1[1])) = tmpValue;
6999 if (bLoad_From_EEPOM)
7000 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1>>1));
7001 else
7002 tmpValue = 0x1010;
7003 *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[0])) = tmpValue;
7004 if (bLoad_From_EEPOM)
7005 tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1+2)>>1);
7006 else
7007 tmpValue = 0x10;
7008 priv->EEPROMTxPowerLevelOFDM24G[2] = (u8)tmpValue;
7009 }//endif EEPROM_Def_Ver == 1
7010
7011 //update HAL variables
7012 //
7013 {
7014 int i;
7015 for (i=0; i<14; i++)
7016 {
7017 if (i<=3)
7018 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[0];
7019 else if (i>=4 && i<=9)
7020 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[1];
7021 else
7022 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[2];
7023 }
7024
7025 for (i=0; i<14; i++)
7026 {
7027 if (priv->EEPROM_Def_Ver == 0)
7028 {
7029 if (i<=3)
7030 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[0] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
7031 else if (i>=4 && i<=9)
7032 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK;
7033 else
7034 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[2] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]);
7035 }
7036 else if (priv->EEPROM_Def_Ver == 1)
7037 {
7038 if (i<=3)
7039 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[0];
7040 else if (i>=4 && i<=9)
7041 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[1];
7042 else
7043 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[2];
7044 }
7045 }
7046 }//end update HAL variables
7047 priv->TxPowerDiff = priv->EEPROMPwDiff;
7048// Antenna B gain offset to antenna A, bit0~3
7049 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
7050 // Antenna C gain offset to antenna A, bit4~7
7051 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
7052 // CrystalCap, bit12~15
7053 priv->CrystalCap = priv->EEPROMCrystalCap;
7054 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
7055 // 92U does not enable TX power tracking.
7056 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
7057 }//end if VersionID == VERSION_819xU_A
7058
7059//added by vivi, for dlink led, 20080416
7060 switch(priv->eeprom_CustomerID)
7061 {
7062 case EEPROM_CID_RUNTOP:
7063 priv->CustomerID = RT_CID_819x_RUNTOP;
7064 break;
7065
7066 case EEPROM_CID_DLINK:
7067 priv->CustomerID = RT_CID_DLINK;
7068 break;
7069
7070 default:
7071 priv->CustomerID = RT_CID_DEFAULT;
7072 break;
7073
7074 }
7075
7076 switch(priv->CustomerID)
7077 {
7078 case RT_CID_819x_RUNTOP:
7079 priv->LedStrategy = SW_LED_MODE2;
7080 break;
7081
7082 case RT_CID_DLINK:
7083 priv->LedStrategy = SW_LED_MODE4;
7084 break;
7085
7086 default:
7087 priv->LedStrategy = SW_LED_MODE0;
7088 break;
7089
7090 }
7091
7092
7093 if(priv->rf_type == RF_1T2R)
7094 {
7095 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
7096 }
7097 else
7098 {
7099 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
7100 }
7101
7102 // 2008/01/16 MH We can only know RF type in the function. So we have to init
7103 // DIG RATR table again.
7104 init_rate_adaptive(dev);
7105 //we need init DIG RATR table here again.
7106
7107 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
7108 return;
7109}
7110#endif
7111
7112short rtl8192_get_channel_map(struct net_device * dev)
7113{
7114 struct r8192_priv *priv = ieee80211_priv(dev);
7115#ifdef ENABLE_DOT11D
7116 if(priv->ChannelPlan > COUNTRY_CODE_GLOBAL_DOMAIN){
7117 printk("rtl8180_init:Error channel plan! Set to default.\n");
7118 priv->ChannelPlan= 0;
7119 }
7120 RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan);
7121
7122 rtl819x_set_channel_map(priv->ChannelPlan, priv);
7123#else
7124 int ch,i;
7125 //Set Default Channel Plan
7126 if(!channels){
7127 DMESG("No channels, aborting");
7128 return -1;
7129 }
7130 ch=channels;
7131 priv->ChannelPlan= 0;//hikaru
7132 // set channels 1..14 allowed in given locale
7133 for (i=1; i<=14; i++) {
7134 (priv->ieee80211->channel_map)[i] = (u8)(ch & 0x01);
7135 ch >>= 1;
7136 }
7137#endif
7138 return 0;
7139}
7140
7141short rtl8192_init(struct net_device *dev)
7142{
7143
7144 struct r8192_priv *priv = ieee80211_priv(dev);
7145
7146#ifndef RTL8192SU
7147 memset(&(priv->stats),0,sizeof(struct Stats));
7148 memset(priv->txqueue_to_outpipemap,0,9);
7149#ifdef PIPE12
7150 {
7151 int i=0;
7152 u8 queuetopipe[]={3,2,1,0,4,8,7,6,5};
7153 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
7154/* for(i=0;i<9;i++)
7155 printk("%d ",priv->txqueue_to_outpipemap[i]);
7156 printk("\n");*/
7157 }
7158#else
7159 {
7160 u8 queuetopipe[]={3,2,1,0,4,4,0,4,4};
7161 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
7162/* for(i=0;i<9;i++)
7163 printk("%d ",priv->txqueue_to_outpipemap[i]);
7164 printk("\n");*/
7165 }
7166#endif
7167#endif
7168 rtl8192_init_priv_variable(dev);
7169 rtl8192_init_priv_lock(priv);
7170 rtl8192_init_priv_task(dev);
7171 rtl8192_get_eeprom_size(dev);
7172 priv->ops->rtl819x_read_eeprom_info(dev);
7173 rtl8192_get_channel_map(dev);
7174 init_hal_dm(dev);
7175 init_timer(&priv->watch_dog_timer);
7176 priv->watch_dog_timer.data = (unsigned long)dev;
7177 priv->watch_dog_timer.function = watch_dog_timer_callback;
7178
7179 //rtl8192_adapter_start(dev);
7180#ifdef DEBUG_EPROM
7181 dump_eprom(dev);
7182#endif
7183 return 0;
7184}
7185
7186/******************************************************************************
7187 *function: This function actually only set RRSR, RATR and BW_OPMODE registers
7188 * not to do all the hw config as its name says
7189 * input: net_device dev
7190 * output: none
7191 * return: none
7192 * notice: This part need to modified according to the rate set we filtered
7193 * ****************************************************************************/
7194void rtl8192_hwconfig(struct net_device* dev)
7195{
7196 u32 regRATR = 0, regRRSR = 0;
7197 u8 regBwOpMode = 0, regTmp = 0;
7198 struct r8192_priv *priv = ieee80211_priv(dev);
7199
7200// Set RRSR, RATR, and BW_OPMODE registers
7201 //
7202 switch(priv->ieee80211->mode)
7203 {
7204 case WIRELESS_MODE_B:
7205 regBwOpMode = BW_OPMODE_20MHZ;
7206 regRATR = RATE_ALL_CCK;
7207 regRRSR = RATE_ALL_CCK;
7208 break;
7209 case WIRELESS_MODE_A:
7210 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
7211 regRATR = RATE_ALL_OFDM_AG;
7212 regRRSR = RATE_ALL_OFDM_AG;
7213 break;
7214 case WIRELESS_MODE_G:
7215 regBwOpMode = BW_OPMODE_20MHZ;
7216 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7217 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7218 break;
7219 case WIRELESS_MODE_AUTO:
7220#ifdef TO_DO_LIST
7221 if (Adapter->bInHctTest)
7222 {
7223 regBwOpMode = BW_OPMODE_20MHZ;
7224 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7225 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7226 }
7227 else
7228#endif
7229 {
7230 regBwOpMode = BW_OPMODE_20MHZ;
7231 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7232 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7233 }
7234 break;
7235 case WIRELESS_MODE_N_24G:
7236 // It support CCK rate by default.
7237 // CCK rate will be filtered out only when associated AP does not support it.
7238 regBwOpMode = BW_OPMODE_20MHZ;
7239 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7240 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7241 break;
7242 case WIRELESS_MODE_N_5G:
7243 regBwOpMode = BW_OPMODE_5G;
7244 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7245 regRRSR = RATE_ALL_OFDM_AG;
7246 break;
7247 }
7248
7249 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
7250 {
7251 u32 ratr_value = 0;
7252 ratr_value = regRATR;
7253 if (priv->rf_type == RF_1T2R)
7254 {
7255 ratr_value &= ~(RATE_ALL_OFDM_2SS);
7256 }
7257 write_nic_dword(dev, RATR0, ratr_value);
7258 write_nic_byte(dev, UFWP, 1);
7259 }
7260 regTmp = read_nic_byte(dev, 0x313);
7261 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
7262 write_nic_dword(dev, RRSR, regRRSR);
7263
7264 //
7265 // Set Retry Limit here
7266 //
7267 write_nic_word(dev, RETRY_LIMIT,
7268 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \
7269 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
7270 // Set Contention Window here
7271
7272 // Set Tx AGC
7273
7274 // Set Tx Antenna including Feedback control
7275
7276 // Set Auto Rate fallback control
7277
7278
7279}
7280
7281#ifdef RTL8192SU
7282#ifdef USB_RX_AGGREGATION_SUPPORT
7283u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize )
7284{
7285 switch(RxPktSize)
7286 {
7287 case 64: return 0; break;
7288 case 128 : return 1; break;
7289 case 256: return 2; break;
7290 case 512: return 3; break;
7291 case 1024: return 4; break;
7292 default: return 0; // We use 64bytes in defult.
7293 }
7294}
7295#endif
7296
7297//
7298// Description:
7299// Initial HW relted registers.
7300//
7301// Assumption:
7302// Config RTL8192S USB MAC, we should config MAC before download FW.
7303//
7304// 2008.09.03, Added by Roger.
7305//
7306static void rtl8192SU_MacConfigBeforeFwDownloadASIC(struct net_device *dev)
7307{
7308 u8 tmpU1b;// i;
7309// u16 tmpU2b;
7310// u32 tmpU4b;
7311 u8 PollingCnt = 20;
7312
7313 RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownloadASIC()\n");
7314
7315 //2MAC Initialization for power on sequence, Revised by Roger. 2008.09.03.
7316
7317 //
7318 //<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
7319 // MAC I/O to solve FW download fail when system from resume sate.
7320 // 2008.11.04.
7321 //
7322 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7323 if(tmpU1b & 0x80)
7324 {
7325 tmpU1b &= 0x3f;
7326 write_nic_byte(dev, SYS_CLKR+1, tmpU1b);
7327 }
7328 // Clear FW RPWM for FW control LPS. by tynli. 2009.02.23
7329 write_nic_byte(dev, RPWM, 0x0);
7330
7331 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7332 tmpU1b &= 0x73;
7333 write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b);
7334 udelay(1000);
7335
7336 //Revised POS, suggested by SD1 Alex, 2008.09.27.
7337 write_nic_byte(dev, SPS0_CTRL+1, 0x53);
7338 write_nic_byte(dev, SPS0_CTRL, 0x57);
7339
7340 //Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
7341 tmpU1b = read_nic_byte(dev, AFE_MISC);
7342 write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN|AFE_MBEN));
7343
7344 //Enable PLL Power (LDOA15V)
7345 tmpU1b = read_nic_byte(dev, LDOA15_CTRL);
7346 write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN));
7347
7348 //Enable LDOV12D block
7349 tmpU1b = read_nic_byte(dev, LDOV12D_CTRL);
7350 write_nic_byte(dev, LDOV12D_CTRL, (tmpU1b|LDV12_EN));
7351
7352 //mpU1b = read_nic_byte(Adapter, SPS1_CTRL);
7353 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN));
7354
7355 //PlatformSleepUs(2000);
7356
7357 //Enable Switch Regulator Block
7358 //tmpU1b = read_nic_byte(Adapter, SPS1_CTRL);
7359 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN));
7360
7361 //write_nic_dword(Adapter, SPS1_CTRL, 0x00a7b267);
7362
7363 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
7364 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b|0x08));
7365
7366 //Engineer Packet CP test Enable
7367 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7368 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x20));
7369
7370 //Support 64k IMEM, suggested by SD1 Alex.
7371 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
7372 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b& 0x68));
7373
7374 //Enable AFE clock
7375 tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1);
7376 write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b& 0xfb));
7377
7378 //Enable AFE PLL Macro Block
7379 tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL);
7380 write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|0x11));
7381
7382 //Attatch AFE PLL to MACTOP/BB/PCIe Digital
7383 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL);
7384 write_nic_byte(dev, SYS_ISO_CTRL, (tmpU1b&0xEE));
7385
7386 // Switch to 40M clock
7387 write_nic_byte(dev, SYS_CLKR, 0x00);
7388
7389 //SSC Disable
7390 tmpU1b = read_nic_byte(dev, SYS_CLKR);
7391 //write_nic_byte(dev, SYS_CLKR, (tmpU1b&0x5f));
7392 write_nic_byte(dev, SYS_CLKR, (tmpU1b|0xa0));
7393
7394 //Enable MAC clock
7395 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7396 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x18));
7397
7398 //Revised POS, suggested by SD1 Alex, 2008.09.27.
7399 write_nic_byte(dev, PMC_FSM, 0x02);
7400
7401 //Enable Core digital and enable IOREG R/W
7402 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7403 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x08));
7404
7405 //Enable REG_EN
7406 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
7407 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x80));
7408
7409 //Switch the control path to FW
7410 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
7411 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x80)& 0xBF);
7412
7413 write_nic_byte(dev, CMDR, 0xFC);
7414 write_nic_byte(dev, CMDR+1, 0x37);
7415
7416 //Fix the RX FIFO issue(usb error), 970410
7417 tmpU1b = read_nic_byte_E(dev, 0x5c);
7418 write_nic_byte_E(dev, 0x5c, (tmpU1b|BIT7));
7419
7420 //For power save, used this in the bit file after 970621
7421 tmpU1b = read_nic_byte(dev, SYS_CLKR);
7422 write_nic_byte(dev, SYS_CLKR, tmpU1b&(~SYS_CPU_CLKSEL));
7423
7424 // Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
7425 write_nic_byte_E(dev, 0x1c, 0x80);
7426
7427 //
7428 // <Roger_EXP> To make sure that TxDMA can ready to download FW.
7429 // We should reset TxDMA if IMEM RPT was not ready.
7430 // Suggested by SD1 Alex. 2008.10.23.
7431 //
7432 do
7433 {
7434 tmpU1b = read_nic_byte(dev, TCR);
7435 if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
7436 break;
7437 //PlatformStallExecution(5);
7438 udelay(5);
7439 }while(PollingCnt--); // Delay 1ms
7440
7441 if(PollingCnt <= 0 )
7442 {
7443 RT_TRACE(COMP_INIT, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b);
7444 tmpU1b = read_nic_byte(dev, CMDR);
7445 write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN));
7446 udelay(2);
7447 write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN);// Reset TxDMA
7448 }
7449
7450
7451 RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownloadASIC()\n");
7452}
7453#ifdef USB_RX_AGGREGATION_SUPPORT
7454void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value)
7455{
7456 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7457 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;;
7458
7459
7460 //
7461 // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode.
7462 // 2008.10.29
7463 //
7464 if(priv->ieee80211->mode == WIRELESS_MODE_B || priv->ieee80211->mode == WIRELESS_MODE_G)
7465 {// Overwrite current settings to disable Rx Aggregation.
7466 Value = false;
7467 }
7468
7469 // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily
7470 //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter))
7471 // Value = FALSE;
7472
7473 // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph
7474 //if(pHTInfo->bCurrentRT2RTAggregation)
7475 // Value = FALSE;
7476
7477 // The RX aggregation may be enabled/disabled dynamically according current traffic stream.
7478 //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan
7479 if(priv->bCurrentRxAggrEnable != Value)
7480 {
7481 priv->bCurrentRxAggrEnable = Value;
7482 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable);
7483 {
7484 //u8 Setting = ((pu1Byte)(val))[0];
7485 u8 Setting = priv->bCurrentRxAggrEnable
7486 u32 ulValue;
7487
7488 if(Setting==0)
7489 {
7490 //
7491 // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a.
7492 // i.e., disable Rx aggregation.
7493 //
7494 ulValue = 0x0001000a;
7495 }
7496 else
7497 {
7498 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7499 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
7500
7501 if (priv->bForcedUsbRxAggr)
7502 {// Using forced settings.
7503 ulValue = priv->ForcedUsbRxAggrInfo;
7504 }
7505 else
7506 {// Using default settings.
7507
7508 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
7509 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
7510 }
7511 }
7512
7513 write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16));
7514 write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff));
7515
7516 priv->LastUsbRxAggrInfoSetting = ulValue;
7517
7518 RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue);
7519 }
7520 RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF");
7521 }
7522
7523}
7524#endif
7525
7526#ifdef USB_RX_AGGREGATION_SUPPORT
7527void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value)
7528{
7529 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7530 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;;
7531
7532
7533 //
7534 // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode.
7535 // 2008.10.29
7536 //
7537 if((priv->ieee80211->mode & WIRELESS_MODE_B) || (priv->ieee80211->mode & WIRELESS_MODE_G))
7538 {// Overwrite current settings to disable Rx Aggregation.
7539 Value = false;
7540 }
7541
7542 // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily
7543 //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter))
7544 // Value = FALSE;
7545
7546 // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph
7547 //if(pHTInfo->bCurrentRT2RTAggregation)
7548 // Value = FALSE;
7549
7550 // The RX aggregation may be enabled/disabled dynamically according current traffic stream.
7551 //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan
7552 if(priv->bCurrentRxAggrEnable != Value)
7553 {
7554 priv->bCurrentRxAggrEnable = Value;
7555 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable);
7556 {
7557 //u8 Setting = ((pu1Byte)(val))[0];
7558 u8 Setting = priv->bCurrentRxAggrEnable
7559 u32 ulValue;
7560
7561 if(Setting==0)
7562 {
7563 //
7564 // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a.
7565 // i.e., disable Rx aggregation.
7566 //
7567 ulValue = 0x0001000a;
7568 }
7569 else
7570 {
7571 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7572 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
7573
7574 if (priv->bForcedUsbRxAggr)
7575 {// Using forced settings.
7576 ulValue = priv->ForcedUsbRxAggrInfo;
7577 }
7578 else
7579 {// Using default settings.
7580
7581 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
7582 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
7583 }
7584 }
7585
7586 write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16));
7587 write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff));
7588
7589 priv->LastUsbRxAggrInfoSetting = ulValue;
7590
7591 RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue);
7592 }
7593 RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF");
7594 }
7595
7596}
7597
7598u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize )
7599{
7600 switch(RxPktSize)
7601 {
7602 case 64: return 0; break;
7603 case 128 : return 1; break;
7604 case 256: return 2; break;
7605 case 512: return 3; break;
7606 case 1024: return 4; break;
7607 default: return 0; // We use 64bytes in defult.
7608 }
7609}
7610#endif
7611
7612#if 0
7613static void rtl8192SU_SetHwRegAmpduMinSpace(struct net_device *dev, u8 MinSpaceCfg)
7614{
7615 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7616 struct ieee80211_device* ieee = priv->ieee80211;
7617 u8 MinSpacingToSet;
7618 u8 SecMinSpace;
7619
7620#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
7621 MinSpacingToSet = MinSpaceCfg;
7622 if(MinSpacingToSet <= 7)
7623 {
7624 switch(ieee->pairwise_key_type)
7625 {
7626 case KEY_TYPE_NA: SecMinSpace = 0; break;
7627 case KEY_TYPE_CCMP:
7628 case KEY_TYPE_WEP40:
7629 case KEY_TYPE_WEP104:
7630 case KEY_TYPE_TKIP: SecMinSpace = 6; break;
7631 default: SecMinSpace = 7; break;
7632 }
7633
7634 if(MinSpacingToSet < SecMinSpace)
7635 MinSpacingToSet = SecMinSpace;
7636 priv->MinSpaceCfg = ((priv->MinSpaceCfg&0xf8) |MinSpacingToSet);
7637 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
7638 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
7639 }
7640
7641#else
7642 MinSpacingToSet = MinSpaceCfg;
7643 MinSpacingToSet &= 0x07; // We only care about bit[2:0]
7644 priv->MinSpaceCfg |= MinSpacingToSet;
7645 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
7646 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);//FIXLZM
7647#endif
7648}
7649#endif
7650
7651//
7652// Description:
7653// Initial HW relted registers.
7654//
7655// Assumption:
7656// 1. This function is only invoked at driver intialization once.
7657// 2. PASSIVE LEVEL.
7658//
7659// 2008.06.10, Added by Roger.
7660//
7661static void rtl8192SU_MacConfigAfterFwDownload(struct net_device *dev)
7662{
7663 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
7664 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
7665 //u8 tmpU1b, RxPageCfg, i;
7666 u16 tmpU2b;
7667 u8 tmpU1b;//, i;
7668
7669
7670 RT_TRACE(COMP_INIT, "--->MacConfigAfterFwDownload()\n");
7671
7672 // Enable Tx/Rx
7673 tmpU2b = (BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|
7674 FW2HW_EN|RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); //3
7675 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_COMMAND, &tmpU1b );
7676 write_nic_word(dev, CMDR, tmpU2b); //LZM REGISTER COM 090305
7677
7678 // Loopback mode or not
7679 priv->LoopbackMode = RTL8192SU_NO_LOOPBACK; // Set no loopback as default.
7680 if(priv->LoopbackMode == RTL8192SU_NO_LOOPBACK)
7681 tmpU1b = LBK_NORMAL;
7682 else if (priv->LoopbackMode == RTL8192SU_MAC_LOOPBACK )
7683 tmpU1b = LBK_MAC_DLB;
7684 else
7685 RT_TRACE(COMP_INIT, "Serious error: wrong loopback mode setting\n");
7686
7687 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_LBK_MODE, &tmpU1b);
7688 write_nic_byte(dev, LBKMD_SEL, tmpU1b);
7689
7690 // Set RCR
7691 write_nic_dword(dev, RCR, priv->ReceiveConfig);
7692 RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload(): Current RCR settings(%#x)\n", priv->ReceiveConfig);
7693
7694
7695 // Set RQPN
7696 //
7697 // <Roger_Notes> 2008.08.18.
7698 // 6 endpoints:
7699 // (1) Page number on CMDQ is 0x03.
7700 // (2) Page number on BCNQ, HQ and MGTQ is 0.
7701 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
7702 // (4) Page number on PUBQ is 0xdd
7703 //
7704 // 11 endpoints:
7705 // (1) Page number on CMDQ is 0x00.
7706 // (2) Page number on BCNQ is 0x02, HQ and MGTQ are 0x03.
7707 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
7708 // (4) Page number on PUBQ is 0xd8
7709 //
7710 //write_nic_dword(Adapter, 0xa0, 0x07070707); //BKQ, BEQ, VIQ and VOQ
7711 //write_nic_byte(dev, 0xa4, 0x00); // HCCAQ
7712#if 0 //LZM 090219
7713#ifdef USE_SIX_USB_ENDPOINT
7714 //write_nic_dword(Adapter, 0xa5, 0x00000003); //CMDQ, MGTQ, HQ and BCNQ
7715 //write_nic_byte(dev, 0xa9, 0xdd); // PUBQ
7716 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
7717 write_nic_byte(dev, 0xab, tmpU1b|BIT7|BIT6);// reduce to 6 endpoints.
7718#else
7719 write_nic_dword(dev, 0xa5, 0x02030300); //CMDQ, MGTQ, HQ and BCNQ
7720 write_nic_byte(dev, 0xa9, 0xd8); // PUBQ
7721 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
7722 write_nic_byte(dev, 0xab, (tmpU1b&(~BIT6))|BIT7); // Disable reduced endpoint.
7723#endif
7724#endif
7725
7726#ifdef USB_RX_AGGREGATION_SUPPORT
7727 // Size of Tx/Rx packet buffer.
7728 tmpU1b = read_nic_byte(dev, PBP);
7729 RxPageCfg = rtl8192SU_MapRxPageSizeToIdx(priv->ieee80211->pHTInfo.UsbRxPageSize);
7730 write_nic_byte(dev, PBP, tmpU1b|RxPageCfg); // Set page size of Rx packet buffer to 128 bytes.
7731 tmpU1b = read_nic_byte(dev, RXDMA);
7732
7733 write_nic_byte(dev, RXDMA, tmpU1b|RXDMA_AGG_EN); // Rx aggregation enable.
7734 //PlatformIOWrite1Byte(Adapter, RXDMA_AGG_PG_TH, 0x14); // Set page size of RxDMA aggregation threshold, default: 20.
7735 //write_nic_byte(dev, RXDMA_AGG_PG_TH, 0x40); // By Scott's suggestion, 2008.09.30.//92su del
7736 //write_nic_byte(dev, USB_RX_AGG_TIMEOUT, RXDMA_AGG_TIMEOUT_17_4_MS); // Set aggregation time-out to 17ms/4.
7737 rtl8192SU_HalUsbRxAggr8192SUsb(dev, true);
7738#endif
7739
7740 // Fix the RX FIFO issue(USB error), Rivesed by Roger, 2008-06-14
7741 tmpU1b = read_nic_byte_E(dev, 0x5C);
7742 write_nic_byte_E(dev, 0x5C, tmpU1b|BIT7);
7743
7744 //
7745 // Revise USB PHY to solve the issue of Rx payload error, Rivesed by Roger, 2008-04-10
7746 // Suggest by SD1 Alex.
7747 //
7748 // <Roger_Notes> The following operation are ONLY for USB PHY test chip.
7749 // 2008.10.07.
7750 //
7751#if RTL8192SU_USB_PHY_TEST
7752 write_nic_byte(dev, 0x41,0xf4);
7753 write_nic_byte(dev, 0x40,0x00);
7754 write_nic_byte(dev, 0x42,0x00);
7755 write_nic_byte(dev, 0x42,0x01);
7756 write_nic_byte(dev, 0x40,0x0f);
7757 write_nic_byte(dev, 0x42,0x00);
7758 write_nic_byte(dev, 0x42,0x01);
7759#endif
7760
7761#if 0 //LZM 090219
7762 //
7763 // Suggested by SD1 Alex, 2008-06-14.
7764 //
7765 write_nic_byte(dev, TXOP_STALL_CTRL, 0x80);//NAV
7766
7767
7768 //
7769 // Set Data Auto Rate Fallback Retry Count register.
7770 //
7771 write_nic_dword(dev, DARFRC, 0x04010000);
7772 write_nic_dword(dev, DARFRC+4, 0x09070605);
7773 write_nic_dword(dev, RARFRC, 0x04010000);
7774 write_nic_dword(dev, RARFRC+4, 0x09070605);
7775
7776 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
7777 for (i = 0; i < 8; i++)
7778#ifdef RTL8192SU_DISABLE_CCK_RATE
7779 write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
7780#else
7781 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
7782#endif
7783
7784 //
7785 // Set driver info, we only accept PHY status now.
7786 //
7787 //write_nic_byte(dev, RXDRVINFO_SZ, 4);
7788
7789 //
7790 // Aggregation length limit. Revised by Roger. 2008.09.22.
7791 //
7792 write_nic_dword(dev, AGGLEN_LMT_L, 0x66666666); // Long GI
7793 write_nic_byte(dev, AGGLEN_LMT_H, 0x06); // Set AMPDU length to 12Kbytes for ShortGI case.
7794
7795 //
7796 // For Min Spacing configuration.
7797 //
7798 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&Adapter->MgntInfo.MinSpaceCfg));
7799 rtl8192SU_SetHwRegAmpduMinSpace(dev,priv->MinSpaceCfg);
7800#endif
7801
7802 // For EFUSE init configuration.
7803 //if (IS_BOOT_FROM_EFUSE(Adapter)) // We may R/W EFUSE in EFUSE mode
7804 if (priv->bBootFromEfuse)
7805 {
7806 u8 tempval;
7807
7808 tempval = read_nic_byte(dev, SYS_ISO_CTRL+1);
7809 tempval &= 0xFE;
7810 write_nic_byte(dev, SYS_ISO_CTRL+1, tempval);
7811
7812 // Enable LDO 2.5V for write action
7813 //tempval = read_nic_byte(Adapter, EFUSE_TEST+3);
7814 //write_nic_byte(Adapter, EFUSE_TEST+3, (tempval | 0x80));
7815
7816 // Change Efuse Clock for write action
7817 //write_nic_byte(Adapter, EFUSE_CLK, 0x03);
7818
7819 // Change Program timing
7820 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
7821 //printk("!!!!!!!!!!!!!!!!!!!!!%s: write 0x33 with 0x72\n",__FUNCTION__);
7822 RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n");
7823 }
7824
7825
7826 RT_TRACE(COMP_INIT, "<---MacConfigAfterFwDownload()\n");
7827}
7828
7829void rtl8192SU_HwConfigureRTL8192SUsb(struct net_device *dev)
7830{
7831
7832 struct r8192_priv *priv = ieee80211_priv(dev);
7833 u8 regBwOpMode = 0;
7834 u32 regRATR = 0, regRRSR = 0;
7835 u8 regTmp = 0;
7836 u32 i = 0;
7837
7838 //1 This part need to modified according to the rate set we filtered!!
7839 //
7840 // Set RRSR, RATR, and BW_OPMODE registers
7841 //
7842 switch(priv->ieee80211->mode)
7843 {
7844 case WIRELESS_MODE_B:
7845 regBwOpMode = BW_OPMODE_20MHZ;
7846 regRATR = RATE_ALL_CCK;
7847 regRRSR = RATE_ALL_CCK;
7848 break;
7849 case WIRELESS_MODE_A:
7850 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
7851 regRATR = RATE_ALL_OFDM_AG;
7852 regRRSR = RATE_ALL_OFDM_AG;
7853 break;
7854 case WIRELESS_MODE_G:
7855 regBwOpMode = BW_OPMODE_20MHZ;
7856 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7857 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7858 break;
7859 case WIRELESS_MODE_AUTO:
7860 if (priv->bInHctTest)
7861 {
7862 regBwOpMode = BW_OPMODE_20MHZ;
7863 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7864 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7865 }
7866 else
7867 {
7868 regBwOpMode = BW_OPMODE_20MHZ;
7869 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7870 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7871 }
7872 break;
7873 case WIRELESS_MODE_N_24G:
7874 // It support CCK rate by default.
7875 // CCK rate will be filtered out only when associated AP does not support it.
7876 regBwOpMode = BW_OPMODE_20MHZ;
7877 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7878 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
7879 break;
7880 case WIRELESS_MODE_N_5G:
7881 regBwOpMode = BW_OPMODE_5G;
7882 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
7883 regRRSR = RATE_ALL_OFDM_AG;
7884 break;
7885 }
7886
7887 //
7888 // <Roger_Notes> We disable CCK response rate until FIB CCK rate IC's back.
7889 // 2008.09.23.
7890 //
7891 regTmp = read_nic_byte(dev, INIRTSMCS_SEL);
7892#ifdef RTL8192SU_DISABLE_CCK_RATE
7893 regRRSR = ((regRRSR & 0x000ffff0)<<8) | regTmp;
7894#else
7895 regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp;
7896#endif
7897
7898 //
7899 // Update SIFS timing.
7900 //
7901 //priv->SifsTime = 0x0e0e0a0a;
7902 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SIFS, (pu1Byte)&pHalData->SifsTime);
7903 { u8 val[4] = {0x0e, 0x0e, 0x0a, 0x0a};
7904 // SIFS for CCK Data ACK
7905 write_nic_byte(dev, SIFS_CCK, val[0]);
7906 // SIFS for CCK consecutive tx like CTS data!
7907 write_nic_byte(dev, SIFS_CCK+1, val[1]);
7908
7909 // SIFS for OFDM Data ACK
7910 write_nic_byte(dev, SIFS_OFDM, val[2]);
7911 // SIFS for OFDM consecutive tx like CTS data!
7912 write_nic_byte(dev, SIFS_OFDM+1, val[3]);
7913 }
7914
7915 write_nic_dword(dev, INIRTSMCS_SEL, regRRSR);
7916 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
7917
7918 //
7919 // Suggested by SD1 Alex, 2008-06-14.
7920 //
7921 //PlatformEFIOWrite1Byte(Adapter, TXOP_STALL_CTRL, 0x80);//NAV to protect all TXOP.
7922
7923 //
7924 // Set Data Auto Rate Fallback Retry Count register.
7925 //
7926 write_nic_dword(dev, DARFRC, 0x02010000);
7927 write_nic_dword(dev, DARFRC+4, 0x06050403);
7928 write_nic_dword(dev, RARFRC, 0x02010000);
7929 write_nic_dword(dev, RARFRC+4, 0x06050403);
7930
7931 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
7932 for (i = 0; i < 8; i++)
7933#ifdef RTL8192SU_DISABLE_CCK_RATE
7934 write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0);
7935#else
7936 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
7937#endif
7938
7939 //
7940 // Aggregation length limit. Revised by Roger. 2008.09.22.
7941 //
7942 write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); // Set AMPDU length to 12Kbytes for ShortGI case.
7943 write_nic_dword(dev, AGGLEN_LMT_L, 0xddd77442); // Long GI
7944 write_nic_dword(dev, AGGLEN_LMT_L+4, 0xfffdd772);
7945
7946 // Set NAV protection length
7947 write_nic_word(dev, NAV_PROT_LEN, 0x0080);
7948
7949 // Set TXOP stall control for several queue/HI/BCN/MGT/
7950 write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); // NAV Protect next packet.
7951
7952 // Set MSDU lifetime.
7953 write_nic_byte(dev, MLT, 0x8f);
7954
7955 // Set CCK/OFDM SIFS
7956 write_nic_word(dev, SIFS_CCK, 0x0a0a); // CCK SIFS shall always be 10us.
7957 write_nic_word(dev, SIFS_OFDM, 0x0e0e);
7958
7959 write_nic_byte(dev, ACK_TIMEOUT, 0x40);
7960
7961 // CF-END Threshold
7962 write_nic_byte(dev, CFEND_TH, 0xFF);
7963
7964 //
7965 // For Min Spacing configuration.
7966 //
7967 switch(priv->rf_type)
7968 {
7969 case RF_1T2R:
7970 case RF_1T1R:
7971 RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", (priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"));
7972 priv->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
7973 break;
7974 case RF_2T2R:
7975 case RF_2T2R_GREEN:
7976 RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n");
7977 priv->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
7978 break;
7979 }
7980 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
7981
7982 //LZM 090219
7983 //
7984 // For Min Spacing configuration.
7985 //
7986 //priv->MinSpaceCfg = 0x00;
7987 //rtl8192SU_SetHwRegAmpduMinSpace(dev, priv->MinSpaceCfg);
7988}
7989
7990#endif
7991
7992#ifdef RTL8192SU
7993// Description: Initial HW relted registers.
7994//
7995// Assumption: This function is only invoked at driver intialization once.
7996//
7997// 2008.06.10, Added by Roger.
7998bool rtl8192SU_adapter_start(struct net_device *dev)
7999{
8000 struct r8192_priv *priv = ieee80211_priv(dev);
8001 //u32 dwRegRead = 0;
8002 //bool init_status = true;
8003 //u32 ulRegRead;
8004 bool rtStatus = true;
8005 //u8 PipeIndex;
8006 //u8 eRFPath, tmpU1b;
8007 u8 fw_download_times = 1;
8008
8009
8010 RT_TRACE(COMP_INIT, "--->InitializeAdapter8192SUsb()\n");
8011
8012 //pHalData->bGPIOChangeRF = FALSE;
8013
8014
8015 //
8016 // <Roger_Notes> 2008.06.15.
8017 //
8018 // Initialization Steps on RTL8192SU:
8019 // a. MAC initialization prior to sending down firmware code.
8020 // b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
8021 // c. MAC configuration after firmware has been download successfully.
8022 // d. Initialize BB related configurations.
8023 // e. Initialize RF related configurations.
8024 // f. Start to BulkIn transfer.
8025 //
8026
8027 //
8028 //a. MAC initialization prior to send down firmware code.
8029 //
8030start:
8031 rtl8192SU_MacConfigBeforeFwDownloadASIC(dev);
8032
8033 //
8034 //b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
8035 //
8036 rtStatus = FirmwareDownload92S(dev);
8037 if(rtStatus != true)
8038 {
8039 if(fw_download_times == 1){
8040 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed once, Download again!!\n");
8041 fw_download_times = fw_download_times + 1;
8042 goto start;
8043 }else{
8044 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed twice, end!!\n");
8045 goto end;
8046 }
8047 }
8048 //
8049 //c. MAC configuration after firmware has been download successfully.
8050 //
8051 rtl8192SU_MacConfigAfterFwDownload(dev);
8052
8053#if (RTL8192S_DISABLE_FW_DM == 1)
8054 write_nic_dword(dev, WFM5, FW_DM_DISABLE);
8055#endif
8056 //priv->bLbusEnable = TRUE;
8057 //if(priv->RegRfOff == TRUE)
8058 // priv->eRFPowerState = eRfOff;
8059
8060 // Save target channel
8061 // <Roger_Notes> Current Channel will be updated again later.
8062 //priv->CurrentChannel = Channel;
8063 rtStatus = PHY_MACConfig8192S(dev);//===>ok
8064 if(rtStatus != true)
8065 {
8066 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure MAC!!\n");
8067 goto end;
8068 }
8069 if (1){
8070 int i;
8071 for (i=0; i<4; i++)
8072 write_nic_dword(dev,WDCAPARA_ADD[i], 0x5e4322);
8073 write_nic_byte(dev,AcmHwCtrl, 0x01);
8074 }
8075
8076
8077 //
8078 //d. Initialize BB related configurations.
8079 //
8080
8081 rtStatus = PHY_BBConfig8192S(dev);//===>ok
8082 if(rtStatus != true)
8083 {
8084 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure BB!!\n");
8085 goto end;
8086 }
8087
8088 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);//===>ok
8089
8090 //
8091 // e. Initialize RF related configurations.
8092 //
8093 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
8094 priv->Rf_Mode = RF_OP_By_SW_3wire;
8095
8096 // For RF test only from Scott's suggestion
8097 //write_nic_byte(dev, 0x27, 0xDB);
8098 //write_nic_byte(dev, 0x1B, 0x07);
8099
8100
8101 write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB);
8102
8103 // <Roger_Notes> The following IOs are configured for each RF modules.
8104 // Enable RF module and reset RF and SDM module. 2008.11.17.
8105 if(priv->card_8192_version == VERSION_8192S_ACUT)
8106 write_nic_byte(dev, SPS1_CTRL+3, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); // Fix A-Cut bug.
8107 else
8108 write_nic_byte(dev, RF_CTRL, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB));
8109
8110 rtStatus = PHY_RFConfig8192S(dev);//===>ok
8111 if(rtStatus != true)
8112 {
8113 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure RF!!\n");
8114 goto end;
8115 }
8116
8117
8118 // Set CCK and OFDM Block "ON"
8119 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
8120 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
8121
8122 //
8123 // Turn off Radio B while RF type is 1T1R by SD3 Wilsion's request.
8124 // Revised by Roger, 2008.12.18.
8125 //
8126 if(priv->rf_type == RF_1T1R)
8127 {
8128 // This is needed for PHY_REG after 20081219
8129 rtl8192_setBBreg(dev, rFPGA0_RFMOD, 0xff000000, 0x03);
8130 // This is needed for PHY_REG before 20081219
8131 //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x11);
8132 }
8133
8134#if (RTL8192SU_DISABLE_IQK==0)
8135 // For 1T2R IQK only currently.
8136 if (priv->card_8192_version == VERSION_8192S_BCUT)
8137 {
8138 PHY_IQCalibrateBcut(dev);
8139 }
8140 else if (priv->card_8192_version == VERSION_8192S_ACUT)
8141 {
8142 PHY_IQCalibrate(dev);
8143 }
8144#endif
8145
8146 //LZM 090219
8147 // Set CCK and OFDM Block "ON"
8148 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
8149 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
8150
8151
8152 //3//Get hardware version, do it in read eeprom?
8153 //GetHardwareVersion819xUsb(Adapter);
8154
8155 //3//
8156 //3 //Set Hardware
8157 //3//
8158 rtl8192SU_HwConfigureRTL8192SUsb(dev);//==>ok
8159
8160 //
8161 // <Roger_Notes> We set MAC address here if autoload was failed before,
8162 // otherwise IDR0 will NOT contain any value.
8163 //
8164 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
8165 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
8166 if(!priv->bInHctTest)
8167 {
8168 if(priv->ResetProgress == RESET_TYPE_NORESET)
8169 {
8170 //RT_TRACE(COMP_MLME, DBG_LOUD, ("Initializeadapter8192SUsb():RegWirelessMode(%#x) \n", Adapter->RegWirelessMode));
8171 //Adapter->HalFunc.SetWirelessModeHandler(Adapter, Adapter->RegWirelessMode);
8172 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);//===>ok
8173 }
8174 }
8175 else
8176 {
8177 priv->ieee80211->mode = WIRELESS_MODE_G;
8178 rtl8192_SetWirelessMode(dev, WIRELESS_MODE_G);
8179 }
8180
8181 //Security related.
8182 //-----------------------------------------------------------------------------
8183 // Set up security related. 070106, by rcnjko:
8184 // 1. Clear all H/W keys.
8185 // 2. Enable H/W encryption/decryption.
8186 //-----------------------------------------------------------------------------
8187 //CamResetAllEntry(Adapter);
8188 //Adapter->HalFunc.EnableHWSecCfgHandler(Adapter);
8189
8190 //SecClearAllKeys(Adapter);
8191 CamResetAllEntry(dev);
8192 //SecInit(Adapter);
8193 {
8194 u8 SECR_value = 0x0;
8195 SECR_value |= SCR_TxEncEnable;
8196 SECR_value |= SCR_RxDecEnable;
8197 SECR_value |= SCR_NoSKMC;
8198 write_nic_byte(dev, SECR, SECR_value);
8199 }
8200
8201#if 0
8202
8203 if(pHalData->VersionID == VERSION_8192SU_A)
8204 {
8205 // cosa add for tx power level initialization.
8206 GetTxPowerOriginalOffset(Adapter);
8207 SetTxPowerLevel819xUsb(Adapter, Channel);
8208 }
8209#endif
8210
8211
8212#ifdef TO_DO_LIST
8213
8214 //PHY_UpdateInitialGain(dev);
8215
8216 if(priv->RegRfOff == true)
8217 { // User disable RF via registry.
8218 u8 eRFPath = 0;
8219
8220 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RegRfOff ----------\n");
8221 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW);
8222 // Those action will be discard in MgntActSet_RF_State because off the same state
8223 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
8224 rtl8192_setBBreg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
8225 }
8226 else if(priv->RfOffReason > RF_CHANGE_BY_PS)
8227 { // H/W or S/W RF OFF before sleep.
8228 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RfOffReason(%d) ----------\n", priv->RfOffReason);
8229 MgntActSet_RF_State(dev, eRfOff, priv->RfOffReason);
8230 }
8231 else
8232 {
8233 priv->eRFPowerState = eRfOn;
8234 priv->RfOffReason = 0;
8235 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): RF is on ----------\n");
8236 }
8237
8238#endif
8239
8240
8241//
8242// f. Start to BulkIn transfer.
8243//
8244#ifdef TO_DO_LIST
8245
8246#ifndef UNDER_VISTA
8247 {
8248 u8 i;
8249 PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
8250
8251 for(PipeIndex=0; PipeIndex < MAX_RX_QUEUE; PipeIndex++)
8252 {
8253 if (PipeIndex == 0)
8254 {
8255 for(i=0; i<32; i++)
8256 HalUsbInMpdu(Adapter, PipeIndex);
8257 }
8258 else
8259 {
8260 //HalUsbInMpdu(Adapter, PipeIndex);
8261 //HalUsbInMpdu(Adapter, PipeIndex);
8262 //HalUsbInMpdu(Adapter, PipeIndex);
8263 }
8264 }
8265 PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
8266 }
8267#else
8268 // Joseph add to 819X code base for Vista USB platform.
8269 // This part may need to be add to Hal819xU code base. too.
8270 PlatformUsbEnableInPipes(Adapter);
8271#endif
8272
8273 RT_TRACE(COMP_INIT, "HighestOperaRate = %x\n", Adapter->MgntInfo.HighestOperaRate);
8274
8275 PlatformStartWorkItem( &(pHalData->RtUsbCheckForHangWorkItem) );
8276
8277 //
8278 // <Roger_EXP> The following configurations are for ASIC verification temporally.
8279 // 2008.07.10.
8280 //
8281
8282#endif
8283
8284 //
8285 // Read EEPROM TX power index and PHY_REG_PG.txt to capture correct
8286 // TX power index for different rate set.
8287 //
8288 //if(priv->card_8192_version >= VERSION_8192S_ACUT)
8289 {
8290 // Get original hw reg values
8291 PHY_GetHWRegOriginalValue(dev);
8292
8293 // Write correct tx power index//FIXLZM
8294 PHY_SetTxPowerLevel8192S(dev, priv->chan);
8295 }
8296
8297 {
8298 u8 tmpU1b = 0;
8299 // EEPROM R/W workaround
8300 tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG);
8301 write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~GPIOMUX_EN));
8302 }
8303
8304//
8305//<Roger_Notes> 2008.08.19.
8306// We return status here for temporal FPGA verification, 2008.08.19.
8307
8308#ifdef RTL8192SU_FW_IQK
8309 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
8310 ChkFwCmdIoDone(dev);
8311#endif
8312
8313 //
8314 // <Roger_Notes> We enable high power mechanism after NIC initialized.
8315 // 2008.11.27.
8316 //
8317 write_nic_dword(dev, WFM5, FW_RA_RESET);
8318 ChkFwCmdIoDone(dev);
8319 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
8320 ChkFwCmdIoDone(dev);
8321 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
8322 ChkFwCmdIoDone(dev);
8323 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
8324
8325// <Roger_Notes> We return status here for temporal FPGA verification. 2008.05.12.
8326//
8327#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK
8328 //
8329 // To send specific number of packets to verify MAC Lookback mode.
8330 //
8331 //SendRandomTxPkt(Adapter, 0); // Burst mode for verification.
8332 //rtStatus = RT_STATUS_FAILURE;
8333 rtStatus = true;
8334 goto end;
8335#endif
8336
8337// The following IO was for FPGA verification purpose. Added by Roger, 2008.09.11.
8338#if 0
8339 // 2008/08/19 MH From SD1 Jong, we must write some register for true PHY/MAC FPGA.
8340 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x30);
8341 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x30);
8342
8343 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
8344
8345 //write_nic_dword(Adapter, RCR, 0x817FF02F);
8346
8347 write_nic_dword(Adapter, rTxAGC_Mcs15_Mcs12, 0x06060606);
8348#endif
8349end:
8350return rtStatus;
8351}
8352
8353#else
8354
8355//InitializeAdapter and PhyCfg
8356bool rtl8192_adapter_start(struct net_device *dev)
8357{
8358 struct r8192_priv *priv = ieee80211_priv(dev);
8359 u32 dwRegRead = 0;
8360 bool init_status = true;
8361 RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__);
8362 priv->Rf_Mode = RF_OP_By_SW_3wire;
8363 //for ASIC power on sequence
8364 write_nic_byte_E(dev, 0x5f, 0x80);
8365 mdelay(50);
8366 write_nic_byte_E(dev, 0x5f, 0xf0);
8367 write_nic_byte_E(dev, 0x5d, 0x00);
8368 write_nic_byte_E(dev, 0x5e, 0x80);
8369 write_nic_byte(dev, 0x17, 0x37);
8370 mdelay(10);
8371//#ifdef TO_DO_LIST
8372 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
8373 //config CPUReset Register
8374 //Firmware Reset or not?
8375 dwRegRead = read_nic_dword(dev, CPU_GEN);
8376 if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
8377 dwRegRead |= CPU_GEN_SYSTEM_RESET; //do nothing here?
8378 else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
8379 dwRegRead |= CPU_GEN_FIRMWARE_RESET;
8380 else
8381 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
8382
8383 write_nic_dword(dev, CPU_GEN, dwRegRead);
8384 //mdelay(30);
8385 //config BB.
8386 rtl8192_BBConfig(dev);
8387
8388#if 1
8389 //Loopback mode or not
8390 priv->LoopbackMode = RTL819xU_NO_LOOPBACK;
8391// priv->LoopbackMode = RTL819xU_MAC_LOOPBACK;
8392
8393 dwRegRead = read_nic_dword(dev, CPU_GEN);
8394 if (priv->LoopbackMode == RTL819xU_NO_LOOPBACK)
8395 dwRegRead = ((dwRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
8396 else if (priv->LoopbackMode == RTL819xU_MAC_LOOPBACK)
8397 dwRegRead |= CPU_CCK_LOOPBACK;
8398 else
8399 RT_TRACE(COMP_ERR, "Serious error in %s(): wrong loopback mode setting(%d)\n", __FUNCTION__, priv->LoopbackMode);
8400
8401 write_nic_dword(dev, CPU_GEN, dwRegRead);
8402
8403 //after reset cpu, we need wait for a seconds to write in register.
8404 udelay(500);
8405
8406 //xiong add for new bitfile:usb suspend reset pin set to 1. //do we need?
8407 write_nic_byte_E(dev, 0x5f, (read_nic_byte_E(dev, 0x5f)|0x20));
8408
8409 //Set Hardware
8410 rtl8192_hwconfig(dev);
8411
8412 //turn on Tx/Rx
8413 write_nic_byte(dev, CMDR, CR_RE|CR_TE);
8414
8415 //set IDR0 here
8416 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
8417 write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
8418
8419 //set RCR
8420 write_nic_dword(dev, RCR, priv->ReceiveConfig);
8421
8422 //Initialize Number of Reserved Pages in Firmware Queue
8423 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |\
8424 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT | \
8425 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT | \
8426 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
8427 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT |\
8428 NUM_OF_PAGE_IN_FW_QUEUE_CMD << RSVD_FW_QUEUE_PAGE_CMD_SHIFT);
8429 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW| \
8430 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT
8431// | NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT
8432 );
8433 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
8434
8435 //Set AckTimeout
8436 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
8437 write_nic_byte(dev, ACK_TIMEOUT, 0x30);
8438
8439// RT_TRACE(COMP_INIT, "%s():priv->ResetProgress is %d\n", __FUNCTION__,priv->ResetProgress);
8440 if(priv->ResetProgress == RESET_TYPE_NORESET)
8441 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);
8442 if(priv->ResetProgress == RESET_TYPE_NORESET){
8443 CamResetAllEntry(dev);
8444 {
8445 u8 SECR_value = 0x0;
8446 SECR_value |= SCR_TxEncEnable;
8447 SECR_value |= SCR_RxDecEnable;
8448 SECR_value |= SCR_NoSKMC;
8449 write_nic_byte(dev, SECR, SECR_value);
8450 }
8451 }
8452
8453 //Beacon related
8454 write_nic_word(dev, ATIMWND, 2);
8455 write_nic_word(dev, BCN_INTERVAL, 100);
8456
8457 {
8458#define DEFAULT_EDCA 0x005e4332
8459 int i;
8460 for (i=0; i<QOS_QUEUE_NUM; i++)
8461 write_nic_dword(dev, WDCAPARA_ADD[i], DEFAULT_EDCA);
8462 }
8463#ifdef USB_RX_AGGREGATION_SUPPORT
8464 //3 For usb rx firmware aggregation control
8465 if(priv->ResetProgress == RESET_TYPE_NORESET)
8466 {
8467 u32 ulValue;
8468 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
8469 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
8470 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
8471 /*
8472 * If usb rx firmware aggregation is enabled,
8473 * when anyone of three threshold conditions above is reached,
8474 * firmware will send aggregated packet to driver.
8475 */
8476 write_nic_dword(dev, 0x1a8, ulValue);
8477 priv->bCurrentRxAggrEnable = true;
8478 }
8479#endif
8480
8481 rtl8192_phy_configmac(dev);
8482
8483 if (priv->card_8192_version == (u8) VERSION_819xU_A)
8484 {
8485 rtl8192_phy_getTxPower(dev);
8486 rtl8192_phy_setTxPower(dev, priv->chan);
8487 }
8488
8489
8490 priv->usb_error = false;
8491 //Firmware download
8492 init_status = init_firmware(dev);
8493 if(!init_status)
8494 {
8495 RT_TRACE(COMP_ERR,"ERR!!! %s(): Firmware download is failed\n", __FUNCTION__);
8496 return init_status;
8497 }
8498 RT_TRACE(COMP_INIT, "%s():after firmware download\n", __FUNCTION__);
8499 //
8500#ifdef TO_DO_LIST
8501if(Adapter->ResetProgress == RESET_TYPE_NORESET)
8502 {
8503 if(pMgntInfo->RegRfOff == TRUE)
8504 { // User disable RF via registry.
8505 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RegRfOff ----------\n"));
8506 MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
8507 // Those action will be discard in MgntActSet_RF_State because off the same state
8508 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
8509 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
8510 }
8511 else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS)
8512 { // H/W or S/W RF OFF before sleep.
8513 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RfOffReason(%d) ----------\n", pMgntInfo->RfOffReason));
8514 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
8515 }
8516 else
8517 {
8518 pHalData->eRFPowerState = eRfOn;
8519 pMgntInfo->RfOffReason = 0;
8520 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): RF is on ----------\n"));
8521 }
8522 }
8523 else
8524 {
8525 if(pHalData->eRFPowerState == eRfOff)
8526 {
8527 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
8528 // Those action will be discard in MgntActSet_RF_State because off the same state
8529 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
8530 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
8531 }
8532 }
8533#endif
8534 //config RF.
8535 if(priv->ResetProgress == RESET_TYPE_NORESET){
8536 rtl8192_phy_RFConfig(dev);
8537 RT_TRACE(COMP_INIT, "%s():after phy RF config\n", __FUNCTION__);
8538 }
8539
8540
8541 if(priv->ieee80211->FwRWRF)
8542 // We can force firmware to do RF-R/W
8543 priv->Rf_Mode = RF_OP_By_FW;
8544 else
8545 priv->Rf_Mode = RF_OP_By_SW_3wire;
8546
8547
8548 rtl8192_phy_updateInitGain(dev);
8549 /*--set CCK and OFDM Block "ON"--*/
8550 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
8551 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
8552
8553 if(priv->ResetProgress == RESET_TYPE_NORESET)
8554 {
8555 //if D or C cut
8556 u8 tmpvalue = read_nic_byte(dev, 0x301);
8557 if(tmpvalue ==0x03)
8558 {
8559 priv->bDcut = TRUE;
8560 RT_TRACE(COMP_POWER_TRACKING, "D-cut\n");
8561 }
8562 else
8563 {
8564 priv->bDcut = FALSE;
8565 RT_TRACE(COMP_POWER_TRACKING, "C-cut\n");
8566 }
8567 dm_initialize_txpower_tracking(dev);
8568
8569 if(priv->bDcut == TRUE)
8570 {
8571 u32 i, TempCCk;
8572 u32 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
8573 // u32 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
8574 for(i = 0; i<TxBBGainTableLength; i++)
8575 {
8576 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
8577 {
8578 priv->rfa_txpowertrackingindex= (u8)i;
8579 priv->rfa_txpowertrackingindex_real= (u8)i;
8580 priv->rfa_txpowertracking_default= priv->rfa_txpowertrackingindex;
8581 break;
8582 }
8583 }
8584
8585 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
8586
8587 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
8588 {
8589
8590 if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
8591 {
8592 priv->cck_present_attentuation_20Mdefault=(u8) i;
8593 break;
8594 }
8595 }
8596 priv->cck_present_attentuation_40Mdefault= 0;
8597 priv->cck_present_attentuation_difference= 0;
8598 priv->cck_present_attentuation = priv->cck_present_attentuation_20Mdefault;
8599
8600 // pMgntInfo->bTXPowerTracking = FALSE;//TEMPLY DISABLE
8601 }
8602 }
8603 write_nic_byte(dev, 0x87, 0x0);
8604
8605
8606#endif
8607 return init_status;
8608}
8609
8610#endif
8611/* this configures registers for beacon tx and enables it via
8612 * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might
8613 * be used to stop beacon transmission
8614 */
8615#if 0
8616void rtl8192_start_tx_beacon(struct net_device *dev)
8617{
8618 int i;
8619 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8620 u16 word;
8621 DMESG("Enabling beacon TX");
8622 //write_nic_byte(dev, TX_CONF,0xe6);// TX_CONF
8623 //rtl8192_init_beacon(dev);
8624 //set_nic_txring(dev);
8625// rtl8192_prepare_beacon(dev);
8626 rtl8192_irq_disable(dev);
8627// rtl8192_beacon_tx_enable(dev);
8628 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
8629 //write_nic_byte(dev,0x9d,0x20); //DMA Poll
8630 //write_nic_word(dev,0x7a,0);
8631 //write_nic_word(dev,0x7a,0x8000);
8632
8633
8634 word = read_nic_word(dev, BcnItv);
8635 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
8636 write_nic_word(dev, BcnItv, word);
8637
8638 write_nic_word(dev, AtimWnd,
8639 read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd);
8640
8641 word = read_nic_word(dev, BCN_INTR_ITV);
8642 word &= ~BCN_INTR_ITV_MASK;
8643
8644 //word |= priv->ieee80211->beacon_interval *
8645 // ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
8646 // FIXME:FIXME check if correct ^^ worked with 0x3e8;
8647
8648 write_nic_word(dev, BCN_INTR_ITV, word);
8649
8650 //write_nic_word(dev,0x2e,0xe002);
8651 //write_nic_dword(dev,0x30,0xb8c7832e);
8652 for(i=0; i<ETH_ALEN; i++)
8653 write_nic_byte(dev, BSSID+i, priv->ieee80211->beacon_cell_ssid[i]);
8654
8655// rtl8192_update_msr(dev);
8656
8657
8658 //write_nic_byte(dev,CONFIG4,3); /* !!!!!!!!!! */
8659
8660 rtl8192_set_mode(dev, EPROM_CMD_NORMAL);
8661
8662 rtl8192_irq_enable(dev);
8663
8664 /* VV !!!!!!!!!! VV*/
8665 /*
8666 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
8667 write_nic_byte(dev,0x9d,0x00);
8668 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
8669*/
8670}
8671#endif
8672/***************************************************************************
8673 -------------------------------NET STUFF---------------------------
8674***************************************************************************/
8675
8676static struct net_device_stats *rtl8192_stats(struct net_device *dev)
8677{
8678 struct r8192_priv *priv = ieee80211_priv(dev);
8679
8680 return &priv->ieee80211->stats;
8681}
8682
8683bool
8684HalTxCheckStuck819xUsb(
8685 struct net_device *dev
8686 )
8687{
8688 struct r8192_priv *priv = ieee80211_priv(dev);
8689 u16 RegTxCounter = read_nic_word(dev, 0x128);
8690 bool bStuck = FALSE;
8691 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
8692 if(priv->TxCounter==RegTxCounter)
8693 bStuck = TRUE;
8694
8695 priv->TxCounter = RegTxCounter;
8696
8697 return bStuck;
8698}
8699
8700/*
8701* <Assumption: RT_TX_SPINLOCK is acquired.>
8702* First added: 2006.11.19 by emily
8703*/
8704RESET_TYPE
8705TxCheckStuck(struct net_device *dev)
8706{
8707 struct r8192_priv *priv = ieee80211_priv(dev);
8708 u8 QueueID;
8709// PRT_TCB pTcb;
8710// u8 ResetThreshold;
8711 bool bCheckFwTxCnt = false;
8712 //unsigned long flags;
8713
8714 //
8715 // Decide Stuch threshold according to current power save mode
8716 //
8717
8718// RT_TRACE(COMP_RESET, " ==> TxCheckStuck()\n");
8719// PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
8720// spin_lock_irqsave(&priv->ieee80211->lock,flags);
8721 for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++)
8722 {
8723 if(QueueID == TXCMD_QUEUE)
8724 continue;
8725#if 1
8726#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
8727 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_drv_aggQ[QueueID]) == 0))
8728#else
8729 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
8730#endif
8731 continue;
8732#endif
8733
8734 bCheckFwTxCnt = true;
8735 }
8736// PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
8737// spin_unlock_irqrestore(&priv->ieee80211->lock,flags);
8738// RT_TRACE(COMP_RESET,"bCheckFwTxCnt is %d\n",bCheckFwTxCnt);
8739#if 1
8740 if(bCheckFwTxCnt)
8741 {
8742 if(HalTxCheckStuck819xUsb(dev))
8743 {
8744 RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n");
8745 return RESET_TYPE_SILENT;
8746 }
8747 }
8748#endif
8749 return RESET_TYPE_NORESET;
8750}
8751
8752bool
8753HalRxCheckStuck819xUsb(struct net_device *dev)
8754{
8755 u16 RegRxCounter = read_nic_word(dev, 0x130);
8756 struct r8192_priv *priv = ieee80211_priv(dev);
8757 bool bStuck = FALSE;
8758//#ifdef RTL8192SU
8759
8760//#else
8761 static u8 rx_chk_cnt = 0;
8762 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
8763 // If rssi is small, we should check rx for long time because of bad rx.
8764 // or maybe it will continuous silent reset every 2 seconds.
8765 rx_chk_cnt++;
8766 if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
8767 {
8768 rx_chk_cnt = 0; //high rssi, check rx stuck right now.
8769 }
8770 else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
8771 ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
8772 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
8773 {
8774 if(rx_chk_cnt < 2)
8775 {
8776 return bStuck;
8777 }
8778 else
8779 {
8780 rx_chk_cnt = 0;
8781 }
8782 }
8783 else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
8784 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
8785 priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
8786 {
8787 if(rx_chk_cnt < 4)
8788 {
8789 //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
8790 return bStuck;
8791 }
8792 else
8793 {
8794 rx_chk_cnt = 0;
8795 //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
8796 }
8797 }
8798 else
8799 {
8800 if(rx_chk_cnt < 8)
8801 {
8802 //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI);
8803 return bStuck;
8804 }
8805 else
8806 {
8807 rx_chk_cnt = 0;
8808 //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI);
8809 }
8810 }
8811//#endif
8812
8813 if(priv->RxCounter==RegRxCounter)
8814 bStuck = TRUE;
8815
8816 priv->RxCounter = RegRxCounter;
8817
8818 return bStuck;
8819}
8820
8821RESET_TYPE
8822RxCheckStuck(struct net_device *dev)
8823{
8824 struct r8192_priv *priv = ieee80211_priv(dev);
8825 //int i;
8826 bool bRxCheck = FALSE;
8827
8828// RT_TRACE(COMP_RESET," ==> RxCheckStuck()\n");
8829 //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
8830
8831 if(priv->IrpPendingCount > 1)
8832 bRxCheck = TRUE;
8833 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
8834
8835// RT_TRACE(COMP_RESET,"bRxCheck is %d \n",bRxCheck);
8836 if(bRxCheck)
8837 {
8838 if(HalRxCheckStuck819xUsb(dev))
8839 {
8840 RT_TRACE(COMP_RESET, "RxStuck Condition\n");
8841 return RESET_TYPE_SILENT;
8842 }
8843 }
8844 return RESET_TYPE_NORESET;
8845}
8846
8847
8848/**
8849* This function is called by Checkforhang to check whether we should ask OS to reset driver
8850*
8851* \param pAdapter The adapter context for this miniport
8852*
8853* Note:NIC with USB interface sholud not call this function because we cannot scan descriptor
8854* to judge whether there is tx stuck.
8855* Note: This function may be required to be rewrite for Vista OS.
8856* <<<Assumption: Tx spinlock has been acquired >>>
8857*
8858* 8185 and 8185b does not implement this function. This is added by Emily at 2006.11.24
8859*/
8860RESET_TYPE
8861rtl819x_ifcheck_resetornot(struct net_device *dev)
8862{
8863 struct r8192_priv *priv = ieee80211_priv(dev);
8864 RESET_TYPE TxResetType = RESET_TYPE_NORESET;
8865 RESET_TYPE RxResetType = RESET_TYPE_NORESET;
8866 RT_RF_POWER_STATE rfState;
8867
8868#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
8869 return RESET_TYPE_NORESET;
8870#endif
8871
8872 rfState = priv->ieee80211->eRFPowerState;
8873
8874 TxResetType = TxCheckStuck(dev);
8875#if 1
8876 if( rfState != eRfOff ||
8877 /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
8878 (priv->ieee80211->iw_mode != IW_MODE_ADHOC))
8879 {
8880 // If driver is in the status of firmware download failure , driver skips RF initialization and RF is
8881 // in turned off state. Driver should check whether Rx stuck and do silent reset. And
8882 // if driver is in firmware download failure status, driver should initialize RF in the following
8883 // silent reset procedure Emily, 2008.01.21
8884
8885 // Driver should not check RX stuck in IBSS mode because it is required to
8886 // set Check BSSID in order to send beacon, however, if check BSSID is
8887 // set, STA cannot hear any packet a all. Emily, 2008.04.12
8888 RxResetType = RxCheckStuck(dev);
8889 }
8890#endif
8891 if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
8892 return RESET_TYPE_NORMAL;
8893 else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT){
8894 RT_TRACE(COMP_RESET,"%s():silent reset\n",__FUNCTION__);
8895 return RESET_TYPE_SILENT;
8896 }
8897 else
8898 return RESET_TYPE_NORESET;
8899
8900}
8901
8902void rtl8192_cancel_deferred_work(struct r8192_priv* priv);
8903int _rtl8192_up(struct net_device *dev);
8904int rtl8192_close(struct net_device *dev);
8905
8906
8907
8908void
8909CamRestoreAllEntry( struct net_device *dev)
8910{
8911 u8 EntryId = 0;
8912 struct r8192_priv *priv = ieee80211_priv(dev);
8913 u8* MacAddr = priv->ieee80211->current_network.bssid;
8914
8915 static u8 CAM_CONST_ADDR[4][6] = {
8916 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
8917 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
8918 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
8919 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}};
8920 static u8 CAM_CONST_BROAD[] =
8921 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
8922
8923 RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n");
8924
8925
8926 if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)||
8927 (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104))
8928 {
8929
8930 for(EntryId=0; EntryId<4; EntryId++)
8931 {
8932 {
8933 MacAddr = CAM_CONST_ADDR[EntryId];
8934 setKey(dev,
8935 EntryId ,
8936 EntryId,
8937 priv->ieee80211->pairwise_key_type,
8938 MacAddr,
8939 0,
8940 NULL);
8941 }
8942 }
8943
8944 }
8945 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP)
8946 {
8947
8948 {
8949 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8950 setKey(dev,
8951 4,
8952 0,
8953 priv->ieee80211->pairwise_key_type,
8954 (u8*)dev->dev_addr,
8955 0,
8956 NULL);
8957 else
8958 setKey(dev,
8959 4,
8960 0,
8961 priv->ieee80211->pairwise_key_type,
8962 MacAddr,
8963 0,
8964 NULL);
8965 }
8966 }
8967 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP)
8968 {
8969
8970 {
8971 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
8972 setKey(dev,
8973 4,
8974 0,
8975 priv->ieee80211->pairwise_key_type,
8976 (u8*)dev->dev_addr,
8977 0,
8978 NULL);
8979 else
8980 setKey(dev,
8981 4,
8982 0,
8983 priv->ieee80211->pairwise_key_type,
8984 MacAddr,
8985 0,
8986 NULL);
8987 }
8988 }
8989
8990
8991
8992 if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP)
8993 {
8994 MacAddr = CAM_CONST_BROAD;
8995 for(EntryId=1 ; EntryId<4 ; EntryId++)
8996 {
8997 {
8998 setKey(dev,
8999 EntryId,
9000 EntryId,
9001 priv->ieee80211->group_key_type,
9002 MacAddr,
9003 0,
9004 NULL);
9005 }
9006 }
9007 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
9008 setKey(dev,
9009 0,
9010 0,
9011 priv->ieee80211->group_key_type,
9012 CAM_CONST_ADDR[0],
9013 0,
9014 NULL);
9015 }
9016 else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP)
9017 {
9018 MacAddr = CAM_CONST_BROAD;
9019 for(EntryId=1; EntryId<4 ; EntryId++)
9020 {
9021 {
9022 setKey(dev,
9023 EntryId ,
9024 EntryId,
9025 priv->ieee80211->group_key_type,
9026 MacAddr,
9027 0,
9028 NULL);
9029 }
9030 }
9031
9032 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
9033 setKey(dev,
9034 0 ,
9035 0,
9036 priv->ieee80211->group_key_type,
9037 CAM_CONST_ADDR[0],
9038 0,
9039 NULL);
9040 }
9041}
9042//////////////////////////////////////////////////////////////
9043// This function is used to fix Tx/Rx stop bug temporarily.
9044// This function will do "system reset" to NIC when Tx or Rx is stuck.
9045// The method checking Tx/Rx stuck of this function is supported by FW,
9046// which reports Tx and Rx counter to register 0x128 and 0x130.
9047//////////////////////////////////////////////////////////////
9048void
9049rtl819x_ifsilentreset(struct net_device *dev)
9050{
9051 //OCTET_STRING asocpdu;
9052 struct r8192_priv *priv = ieee80211_priv(dev);
9053 u8 reset_times = 0;
9054 int reset_status = 0;
9055 struct ieee80211_device *ieee = priv->ieee80211;
9056
9057
9058 // 2007.07.20. If we need to check CCK stop, please uncomment this line.
9059 //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter);
9060
9061 if(priv->ResetProgress==RESET_TYPE_NORESET)
9062 {
9063RESET_START:
9064
9065 RT_TRACE(COMP_RESET,"=========>Reset progress!! \n");
9066
9067 // Set the variable for reset.
9068 priv->ResetProgress = RESET_TYPE_SILENT;
9069// rtl8192_close(dev);
9070#if 1
9071 down(&priv->wx_sem);
9072 if(priv->up == 0)
9073 {
9074 RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__);
9075 up(&priv->wx_sem);
9076 return ;
9077 }
9078 priv->up = 0;
9079 RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__);
9080// if(!netif_queue_stopped(dev))
9081// netif_stop_queue(dev);
9082
9083 rtl8192_rtx_disable(dev);
9084 rtl8192_cancel_deferred_work(priv);
9085 deinit_hal_dm(dev);
9086 del_timer_sync(&priv->watch_dog_timer);
9087
9088 ieee->sync_scan_hurryup = 1;
9089 if(ieee->state == IEEE80211_LINKED)
9090 {
9091 down(&ieee->wx_sem);
9092 printk("ieee->state is IEEE80211_LINKED\n");
9093 ieee80211_stop_send_beacons(priv->ieee80211);
9094 del_timer_sync(&ieee->associate_timer);
9095 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
9096 cancel_delayed_work(&ieee->associate_retry_wq);
9097 #endif
9098 ieee80211_stop_scan(ieee);
9099 netif_carrier_off(dev);
9100 up(&ieee->wx_sem);
9101 }
9102 else{
9103 printk("ieee->state is NOT LINKED\n");
9104 ieee80211_softmac_stop_protocol(priv->ieee80211); }
9105 up(&priv->wx_sem);
9106 RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__);
9107 //rtl8192_irq_disable(dev);
9108 RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__);
9109 reset_status = _rtl8192_up(dev);
9110
9111 RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__);
9112 if(reset_status == -EAGAIN)
9113 {
9114 if(reset_times < 3)
9115 {
9116 reset_times++;
9117 goto RESET_START;
9118 }
9119 else
9120 {
9121 RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n", __FUNCTION__);
9122 }
9123 }
9124#endif
9125 ieee->is_silent_reset = 1;
9126#if 1
9127 EnableHWSecurityConfig8192(dev);
9128#if 1
9129 if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
9130 {
9131 ieee->set_chan(ieee->dev, ieee->current_network.channel);
9132
9133#if 1
9134#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
9135 queue_work(ieee->wq, &ieee->associate_complete_wq);
9136#else
9137 schedule_task(&ieee->associate_complete_wq);
9138#endif
9139#endif
9140
9141 }
9142 else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC)
9143 {
9144 ieee->set_chan(ieee->dev, ieee->current_network.channel);
9145 ieee->link_change(ieee->dev);
9146
9147 // notify_wx_assoc_event(ieee);
9148
9149 ieee80211_start_send_beacons(ieee);
9150
9151 if (ieee->data_hard_resume)
9152 ieee->data_hard_resume(ieee->dev);
9153 netif_carrier_on(ieee->dev);
9154 }
9155#endif
9156
9157 CamRestoreAllEntry(dev);
9158
9159 priv->ResetProgress = RESET_TYPE_NORESET;
9160 priv->reset_count++;
9161
9162 priv->bForcedSilentReset =false;
9163 priv->bResetInProgress = false;
9164
9165 // For test --> force write UFWP.
9166 write_nic_byte(dev, UFWP, 1);
9167 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
9168#endif
9169 }
9170}
9171
9172void CAM_read_entry(
9173 struct net_device *dev,
9174 u32 iIndex
9175)
9176{
9177 u32 target_command=0;
9178 u32 target_content=0;
9179 u8 entry_i=0;
9180 u32 ulStatus;
9181 s32 i=100;
9182// printk("=======>start read CAM\n");
9183 for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
9184 {
9185 // polling bit, and No Write enable, and address
9186 target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
9187 target_command= target_command | BIT31;
9188
9189 //Check polling bit is clear
9190// mdelay(1);
9191#if 1
9192 while((i--)>=0)
9193 {
9194 ulStatus = read_nic_dword(dev, RWCAM);
9195 if(ulStatus & BIT31){
9196 continue;
9197 }
9198 else{
9199 break;
9200 }
9201 }
9202#endif
9203 write_nic_dword(dev, RWCAM, target_command);
9204 RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command);
9205 // printk("CAM_read_entry(): WRITE A0: %lx \n",target_command);
9206 target_content = read_nic_dword(dev, RCAMO);
9207 RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content);
9208 // printk("CAM_read_entry(): WRITE A8: %lx \n",target_content);
9209 }
9210 printk("\n");
9211}
9212
9213void rtl819x_update_rxcounts(
9214 struct r8192_priv *priv,
9215 u32* TotalRxBcnNum,
9216 u32* TotalRxDataNum
9217)
9218{
9219 u16 SlotIndex;
9220 u8 i;
9221
9222 *TotalRxBcnNum = 0;
9223 *TotalRxDataNum = 0;
9224
9225 SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum);
9226 priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod;
9227 priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod;
9228 for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){
9229 *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i];
9230 *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i];
9231 }
9232}
9233
9234
9235#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
9236extern void rtl819x_watchdog_wqcallback(struct work_struct *work)
9237{
9238 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
9239 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq);
9240 struct net_device *dev = priv->ieee80211->dev;
9241#else
9242extern void rtl819x_watchdog_wqcallback(struct net_device *dev)
9243{
9244 struct r8192_priv *priv = ieee80211_priv(dev);
9245#endif
9246 struct ieee80211_device* ieee = priv->ieee80211;
9247 RESET_TYPE ResetType = RESET_TYPE_NORESET;
9248 static u8 check_reset_cnt=0;
9249 bool bBusyTraffic = false;
9250
9251 if(!priv->up)
9252 return;
9253 hal_dm_watchdog(dev);
9254
9255 {//to get busy traffic condition
9256 if(ieee->state == IEEE80211_LINKED)
9257 {
9258 //windows mod 666 to 100.
9259 //if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 ||
9260 // ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) {
9261 if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 ||
9262 ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) {
9263 bBusyTraffic = true;
9264 }
9265 ieee->LinkDetectInfo.NumRxOkInPeriod = 0;
9266 ieee->LinkDetectInfo.NumTxOkInPeriod = 0;
9267 ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
9268 }
9269 }
9270 //added by amy for AP roaming
9271 {
9272 if(priv->ieee80211->state == IEEE80211_LINKED && priv->ieee80211->iw_mode == IW_MODE_INFRA)
9273 {
9274 u32 TotalRxBcnNum = 0;
9275 u32 TotalRxDataNum = 0;
9276
9277 rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum);
9278 if((TotalRxBcnNum+TotalRxDataNum) == 0)
9279 {
9280 #ifdef TODO
9281 if(rfState == eRfOff)
9282 RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__);
9283 #endif
9284 printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__);
9285 // Dot11d_Reset(dev);
9286 priv->ieee80211->state = IEEE80211_ASSOCIATING;
9287 notify_wx_assoc_event(priv->ieee80211);
9288 RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid);
9289 ieee->is_roaming = true;
9290 priv->ieee80211->link_change(dev);
9291#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
9292 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
9293#else
9294 schedule_task(&priv->ieee80211->associate_procedure_wq);
9295#endif
9296
9297 }
9298 }
9299 priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod=0;
9300 priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod=0;
9301 }
9302// CAM_read_entry(dev,4);
9303 //check if reset the driver
9304 if(check_reset_cnt++ >= 3 && !ieee->is_roaming)
9305 {
9306 ResetType = rtl819x_ifcheck_resetornot(dev);
9307 check_reset_cnt = 3;
9308 //DbgPrint("Start to check silent reset\n");
9309 }
9310 // RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
9311#if 1
9312 if( (priv->force_reset) || (priv->ResetProgress==RESET_TYPE_NORESET &&
9313 (priv->bForcedSilentReset ||
9314 (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT)))) // This is control by OID set in Pomelo
9315 {
9316 RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
9317 rtl819x_ifsilentreset(dev);
9318 }
9319#endif
9320 priv->force_reset = false;
9321 priv->bForcedSilentReset = false;
9322 priv->bResetInProgress = false;
9323 RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n");
9324
9325}
9326
9327void watch_dog_timer_callback(unsigned long data)
9328{
9329 struct r8192_priv *priv = ieee80211_priv((struct net_device *) data);
9330 //printk("===============>watch_dog timer\n");
9331#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
9332 queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq, 0);
9333#else
9334#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
9335 schedule_task(&priv->watch_dog_wq);
9336#else
9337 queue_work(priv->priv_wq,&priv->watch_dog_wq);
9338#endif
9339#endif
9340 mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME));
9341#if 0
9342 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
9343 add_timer(&priv->watch_dog_timer);
9344#endif
9345}
9346int _rtl8192_up(struct net_device *dev)
9347{
9348 struct r8192_priv *priv = ieee80211_priv(dev);
9349 //int i;
9350 int init_status = 0;
9351 priv->up=1;
9352 priv->ieee80211->ieee_up=1;
9353 RT_TRACE(COMP_INIT, "Bringing up iface");
9354 init_status = priv->ops->rtl819x_adapter_start(dev);
9355 if(!init_status)
9356 {
9357 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n", __FUNCTION__);
9358 priv->up=priv->ieee80211->ieee_up = 0;
9359 return -EAGAIN;
9360 }
9361 RT_TRACE(COMP_INIT, "start adapter finished\n");
9362 rtl8192_rx_enable(dev);
9363// rtl8192_tx_enable(dev);
9364 if(priv->ieee80211->state != IEEE80211_LINKED)
9365 ieee80211_softmac_start_protocol(priv->ieee80211);
9366 ieee80211_reset_queue(priv->ieee80211);
9367 watch_dog_timer_callback((unsigned long) dev);
9368 if(!netif_queue_stopped(dev))
9369 netif_start_queue(dev);
9370 else
9371 netif_wake_queue(dev);
9372
9373 /*
9374 * Make sure that drop_unencrypted is initialized as "0"
9375 * No packets will be sent in non-security mode if we had set drop_unencrypted.
9376 * ex, After kill wpa_supplicant process, make the driver up again.
9377 * drop_unencrypted remains as "1", which is set by wpa_supplicant. 2008/12/04.john
9378 */
9379 priv->ieee80211->drop_unencrypted = 0;
9380
9381 return 0;
9382}
9383
9384
9385int rtl8192_open(struct net_device *dev)
9386{
9387 struct r8192_priv *priv = ieee80211_priv(dev);
9388 int ret;
9389 down(&priv->wx_sem);
9390 ret = rtl8192_up(dev);
9391 up(&priv->wx_sem);
9392 return ret;
9393
9394}
9395
9396
9397int rtl8192_up(struct net_device *dev)
9398{
9399 struct r8192_priv *priv = ieee80211_priv(dev);
9400
9401 if (priv->up == 1) return -1;
9402
9403 return _rtl8192_up(dev);
9404}
9405
9406
9407int rtl8192_close(struct net_device *dev)
9408{
9409 struct r8192_priv *priv = ieee80211_priv(dev);
9410 int ret;
9411
9412 down(&priv->wx_sem);
9413
9414 ret = rtl8192_down(dev);
9415
9416 up(&priv->wx_sem);
9417
9418 return ret;
9419
9420}
9421
9422int rtl8192_down(struct net_device *dev)
9423{
9424 struct r8192_priv *priv = ieee80211_priv(dev);
9425 int i;
9426
9427 if (priv->up == 0) return -1;
9428
9429 priv->up=0;
9430 priv->ieee80211->ieee_up = 0;
9431 RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__);
9432/* FIXME */
9433 if (!netif_queue_stopped(dev))
9434 netif_stop_queue(dev);
9435
9436 rtl8192_rtx_disable(dev);
9437 //rtl8192_irq_disable(dev);
9438
9439 /* Tx related queue release */
9440 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9441 skb_queue_purge(&priv->ieee80211->skb_waitQ [i]);
9442 }
9443 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9444 skb_queue_purge(&priv->ieee80211->skb_aggQ [i]);
9445 }
9446
9447 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
9448 skb_queue_purge(&priv->ieee80211->skb_drv_aggQ [i]);
9449 }
9450
9451 //as cancel_delayed_work will del work->timer, so if work is not definedas struct delayed_work, it will corrupt
9452// flush_scheduled_work();
9453 rtl8192_cancel_deferred_work(priv);
9454 deinit_hal_dm(dev);
9455 del_timer_sync(&priv->watch_dog_timer);
9456
9457
9458 ieee80211_softmac_stop_protocol(priv->ieee80211);
9459 memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list));
9460 RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__);
9461
9462 return 0;
9463}
9464
9465
9466void rtl8192_commit(struct net_device *dev)
9467{
9468 struct r8192_priv *priv = ieee80211_priv(dev);
9469 int reset_status = 0;
9470 //u8 reset_times = 0;
9471 if (priv->up == 0) return ;
9472 priv->up = 0;
9473
9474 rtl8192_cancel_deferred_work(priv);
9475 del_timer_sync(&priv->watch_dog_timer);
9476 //cancel_delayed_work(&priv->SwChnlWorkItem);
9477
9478 ieee80211_softmac_stop_protocol(priv->ieee80211);
9479
9480 //rtl8192_irq_disable(dev);
9481 rtl8192_rtx_disable(dev);
9482 reset_status = _rtl8192_up(dev);
9483
9484}
9485
9486/*
9487void rtl8192_restart(struct net_device *dev)
9488{
9489 struct r8192_priv *priv = ieee80211_priv(dev);
9490*/
9491#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
9492void rtl8192_restart(struct work_struct *work)
9493{
9494 struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq);
9495 struct net_device *dev = priv->ieee80211->dev;
9496#else
9497void rtl8192_restart(struct net_device *dev)
9498{
9499
9500 struct r8192_priv *priv = ieee80211_priv(dev);
9501#endif
9502
9503 down(&priv->wx_sem);
9504
9505 rtl8192_commit(dev);
9506
9507 up(&priv->wx_sem);
9508}
9509
9510static void r8192_set_multicast(struct net_device *dev)
9511{
9512 struct r8192_priv *priv = ieee80211_priv(dev);
9513 short promisc;
9514
9515 //down(&priv->wx_sem);
9516
9517 /* FIXME FIXME */
9518
9519 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
9520
9521 if (promisc != priv->promisc)
9522 // rtl8192_commit(dev);
9523
9524 priv->promisc = promisc;
9525
9526 //schedule_work(&priv->reset_wq);
9527 //up(&priv->wx_sem);
9528}
9529
9530
9531int r8192_set_mac_adr(struct net_device *dev, void *mac)
9532{
9533 struct r8192_priv *priv = ieee80211_priv(dev);
9534 struct sockaddr *addr = mac;
9535
9536 down(&priv->wx_sem);
9537
9538 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
9539
9540#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
9541 schedule_work(&priv->reset_wq);
9542#else
9543 schedule_task(&priv->reset_wq);
9544#endif
9545 up(&priv->wx_sem);
9546
9547 return 0;
9548}
9549
9550/* based on ipw2200 driver */
9551int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
9552{
9553 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9554 struct iwreq *wrq = (struct iwreq *)rq;
9555 int ret=-1;
9556 struct ieee80211_device *ieee = priv->ieee80211;
9557 u32 key[4];
9558 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
9559 u8 zero_addr[6] = {0};
9560 struct iw_point *p = &wrq->u.data;
9561 struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer;
9562
9563 down(&priv->wx_sem);
9564
9565
9566 if (p->length < sizeof(struct ieee_param) || !p->pointer){
9567 ret = -EINVAL;
9568 goto out;
9569 }
9570
9571 ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL);
9572 if (ipw == NULL){
9573 ret = -ENOMEM;
9574 goto out;
9575 }
9576 if (copy_from_user(ipw, p->pointer, p->length)) {
9577 kfree(ipw);
9578 ret = -EFAULT;
9579 goto out;
9580 }
9581
9582 switch (cmd) {
9583 case RTL_IOCTL_WPA_SUPPLICANT:
9584 //parse here for HW security
9585 if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION)
9586 {
9587 if (ipw->u.crypt.set_tx)
9588 {
9589 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
9590 ieee->pairwise_key_type = KEY_TYPE_CCMP;
9591 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
9592 ieee->pairwise_key_type = KEY_TYPE_TKIP;
9593 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
9594 {
9595 if (ipw->u.crypt.key_len == 13)
9596 ieee->pairwise_key_type = KEY_TYPE_WEP104;
9597 else if (ipw->u.crypt.key_len == 5)
9598 ieee->pairwise_key_type = KEY_TYPE_WEP40;
9599 }
9600 else
9601 ieee->pairwise_key_type = KEY_TYPE_NA;
9602
9603 if (ieee->pairwise_key_type)
9604 {
9605 // FIXME:these two lines below just to fix ipw interface bug, that is, it will never set mode down to driver. So treat it as ADHOC mode, if no association procedure. WB. 2009.02.04
9606 if (memcmp(ieee->ap_mac_addr, zero_addr, 6) == 0)
9607 ieee->iw_mode = IW_MODE_ADHOC;
9608 memcpy((u8*)key, ipw->u.crypt.key, 16);
9609 EnableHWSecurityConfig8192(dev);
9610 //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching!
9611 //added by WB.
9612 setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
9613 if (ieee->iw_mode == IW_MODE_ADHOC)
9614 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
9615 }
9616 }
9617 else //if (ipw->u.crypt.idx) //group key use idx > 0
9618 {
9619 memcpy((u8*)key, ipw->u.crypt.key, 16);
9620 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
9621 ieee->group_key_type= KEY_TYPE_CCMP;
9622 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
9623 ieee->group_key_type = KEY_TYPE_TKIP;
9624 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
9625 {
9626 if (ipw->u.crypt.key_len == 13)
9627 ieee->group_key_type = KEY_TYPE_WEP104;
9628 else if (ipw->u.crypt.key_len == 5)
9629 ieee->group_key_type = KEY_TYPE_WEP40;
9630 }
9631 else
9632 ieee->group_key_type = KEY_TYPE_NA;
9633
9634 if (ieee->group_key_type)
9635 {
9636 setKey( dev,
9637 ipw->u.crypt.idx,
9638 ipw->u.crypt.idx, //KeyIndex
9639 ieee->group_key_type, //KeyType
9640 broadcast_addr, //MacAddr
9641 0, //DefaultKey
9642 key); //KeyContent
9643 }
9644 }
9645 }
9646#ifdef JOHN_HWSEC_DEBUG
9647 //john's test 0711
9648 printk("@@ wrq->u pointer = ");
9649 for(i=0;i<wrq->u.data.length;i++){
9650 if(i%10==0) printk("\n");
9651 printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] );
9652 }
9653 printk("\n");
9654#endif /*JOHN_HWSEC_DEBUG*/
9655 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
9656 break;
9657
9658 default:
9659 ret = -EOPNOTSUPP;
9660 break;
9661 }
9662 kfree(ipw);
9663 ipw = NULL;
9664out:
9665 up(&priv->wx_sem);
9666 return ret;
9667}
9668
9669#ifdef RTL8192SU
9670u8 rtl8192SU_HwRateToMRate(bool bIsHT, u8 rate,bool bFirstAMPDU)
9671{
9672
9673 u8 ret_rate = 0x02;
9674
9675 if( bFirstAMPDU )
9676 {
9677 if(!bIsHT)
9678 {
9679 switch(rate)
9680 {
9681
9682 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
9683 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
9684 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
9685 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
9686 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
9687 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
9688 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
9689 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
9690 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
9691 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
9692 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
9693 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
9694
9695 default:
9696 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
9697 break;
9698 }
9699 }
9700 else
9701 {
9702 switch(rate)
9703 {
9704
9705 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
9706 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
9707 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
9708 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
9709 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
9710 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
9711 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
9712 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
9713 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
9714 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
9715 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
9716 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
9717 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
9718 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
9719 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
9720 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
9721 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
9722
9723 default:
9724 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
9725 break;
9726 }
9727
9728 }
9729 }
9730 else
9731 {
9732 switch(rate)
9733 {
9734
9735 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
9736 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
9737 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
9738 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
9739 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
9740 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
9741 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
9742 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
9743 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
9744 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
9745 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
9746 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
9747 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
9748 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
9749 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
9750 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
9751 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
9752 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
9753 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
9754 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
9755 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
9756 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
9757 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
9758 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
9759 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
9760 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
9761 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
9762 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
9763 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
9764
9765 default:
9766 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
9767 break;
9768 }
9769 }
9770 return ret_rate;
9771}
9772#endif
9773
9774u8 HwRateToMRate90(bool bIsHT, u8 rate)
9775{
9776 u8 ret_rate = 0xff;
9777
9778 if(!bIsHT) {
9779 switch(rate) {
9780 case DESC90_RATE1M: ret_rate = MGN_1M; break;
9781 case DESC90_RATE2M: ret_rate = MGN_2M; break;
9782 case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break;
9783 case DESC90_RATE11M: ret_rate = MGN_11M; break;
9784 case DESC90_RATE6M: ret_rate = MGN_6M; break;
9785 case DESC90_RATE9M: ret_rate = MGN_9M; break;
9786 case DESC90_RATE12M: ret_rate = MGN_12M; break;
9787 case DESC90_RATE18M: ret_rate = MGN_18M; break;
9788 case DESC90_RATE24M: ret_rate = MGN_24M; break;
9789 case DESC90_RATE36M: ret_rate = MGN_36M; break;
9790 case DESC90_RATE48M: ret_rate = MGN_48M; break;
9791 case DESC90_RATE54M: ret_rate = MGN_54M; break;
9792
9793 default:
9794 ret_rate = 0xff;
9795 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
9796 break;
9797 }
9798
9799 } else {
9800 switch(rate) {
9801 case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break;
9802 case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break;
9803 case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break;
9804 case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break;
9805 case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break;
9806 case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break;
9807 case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break;
9808 case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break;
9809 case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break;
9810 case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break;
9811 case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break;
9812 case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break;
9813 case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break;
9814 case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break;
9815 case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break;
9816 case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break;
9817 case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break;
9818
9819 default:
9820 ret_rate = 0xff;
9821 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT);
9822 break;
9823 }
9824 }
9825
9826 return ret_rate;
9827}
9828
9829/**
9830 * Function: UpdateRxPktTimeStamp
9831 * Overview: Recored down the TSF time stamp when receiving a packet
9832 *
9833 * Input:
9834 * PADAPTER Adapter
9835 * PRT_RFD pRfd,
9836 *
9837 * Output:
9838 * PRT_RFD pRfd
9839 * (pRfd->Status.TimeStampHigh is updated)
9840 * (pRfd->Status.TimeStampLow is updated)
9841 * Return:
9842 * None
9843 */
9844void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats)
9845{
9846 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9847
9848 if(stats->bIsAMPDU && !stats->bFirstMPDU) {
9849 stats->mac_time[0] = priv->LastRxDescTSFLow;
9850 stats->mac_time[1] = priv->LastRxDescTSFHigh;
9851 } else {
9852 priv->LastRxDescTSFLow = stats->mac_time[0];
9853 priv->LastRxDescTSFHigh = stats->mac_time[1];
9854 }
9855}
9856
9857//by amy 080606
9858
9859long rtl819x_translate_todbm(u8 signal_strength_index )// 0-100 index.
9860{
9861 long signal_power; // in dBm.
9862
9863 // Translate to dBm (x=0.5y-95).
9864 signal_power = (long)((signal_strength_index + 1) >> 1);
9865 signal_power -= 95;
9866
9867 return signal_power;
9868}
9869
9870
9871/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
9872 be a local static. Otherwise, it may increase when we return from S3/S4. The
9873 value will be kept in memory or disk. We must delcare the value in adapter
9874 and it will be reinitialized when return from S3/S4. */
9875void rtl8192_process_phyinfo(struct r8192_priv * priv,u8* buffer, struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats)
9876{
9877 bool bcheck = false;
9878 u8 rfpath;
9879 u32 nspatial_stream, tmp_val;
9880 //u8 i;
9881 static u32 slide_rssi_index=0, slide_rssi_statistics=0;
9882 static u32 slide_evm_index=0, slide_evm_statistics=0;
9883 static u32 last_rssi=0, last_evm=0;
9884
9885 static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0;
9886 static u32 last_beacon_adc_pwdb=0;
9887
9888 struct ieee80211_hdr_3addr *hdr;
9889 u16 sc ;
9890 unsigned int frag,seq;
9891 hdr = (struct ieee80211_hdr_3addr *)buffer;
9892 sc = le16_to_cpu(hdr->seq_ctl);
9893 frag = WLAN_GET_SEQ_FRAG(sc);
9894 seq = WLAN_GET_SEQ_SEQ(sc);
9895 //cosa add 04292008 to record the sequence number
9896 pcurrent_stats->Seq_Num = seq;
9897 //
9898 // Check whether we should take the previous packet into accounting
9899 //
9900 if(!pprevious_stats->bIsAMPDU)
9901 {
9902 // if previous packet is not aggregated packet
9903 bcheck = true;
9904 }else
9905 {
9906 #if 0
9907 // if previous packet is aggregated packet, and current packet
9908 // (1) is not AMPDU
9909 // (2) is the first packet of one AMPDU
9910 // that means the previous packet is the last one aggregated packet
9911 if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU)
9912 bcheck = true;
9913 #endif
9914 }
9915
9916
9917 if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX)
9918 {
9919 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
9920 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
9921 priv->stats.slide_rssi_total -= last_rssi;
9922 }
9923 priv->stats.slide_rssi_total += pprevious_stats->SignalStrength;
9924
9925 priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength;
9926 if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
9927 slide_rssi_index = 0;
9928
9929 // <1> Showed on UI for user, in dbm
9930 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
9931 priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val);
9932 pcurrent_stats->rssi = priv->stats.signal_strength;
9933 //
9934 // If the previous packet does not match the criteria, neglect it
9935 //
9936 if(!pprevious_stats->bPacketMatchBSSID)
9937 {
9938 if(!pprevious_stats->bToSelfBA)
9939 return;
9940 }
9941
9942 if(!bcheck)
9943 return;
9944
9945
9946 //rtl8190_process_cck_rxpathsel(priv,pprevious_stats);//only rtl8190 supported
9947
9948 //
9949 // Check RSSI
9950 //
9951 priv->stats.num_process_phyinfo++;
9952
9953 /* record the general signal strength to the sliding window. */
9954
9955
9956 // <2> Showed on UI for engineering
9957 // hardware does not provide rssi information for each rf path in CCK
9958 if(!pprevious_stats->bIsCCK && (pprevious_stats->bPacketToSelf || pprevious_stats->bToSelfBA))
9959 {
9960 for (rfpath = RF90_PATH_A; rfpath < priv->NumTotalRFPath; rfpath++)
9961 {
9962 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath))
9963 continue;
9964
9965 //Fixed by Jacken 2008-03-20
9966 if(priv->stats.rx_rssi_percentage[rfpath] == 0)
9967 {
9968 priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath];
9969 //DbgPrint("MIMO RSSI initialize \n");
9970 }
9971 if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath])
9972 {
9973 priv->stats.rx_rssi_percentage[rfpath] =
9974 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
9975 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
9976 priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1;
9977 }
9978 else
9979 {
9980 priv->stats.rx_rssi_percentage[rfpath] =
9981 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
9982 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
9983 }
9984 RT_TRACE(COMP_DBG,"priv->stats.rx_rssi_percentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] );
9985 }
9986 }
9987
9988
9989 //
9990 // Check PWDB.
9991 //
9992 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
9993 pprevious_stats->bIsCCK? "CCK": "OFDM",
9994 pprevious_stats->RxPWDBAll);
9995
9996 if(pprevious_stats->bPacketBeacon)
9997 {
9998/* record the beacon pwdb to the sliding window. */
9999 if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX)
10000 {
10001 slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX;
10002 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index];
10003 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
10004 //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n",
10005 // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total);
10006 }
10007 priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll;
10008 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll;
10009 //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll);
10010 slide_beacon_adc_pwdb_index++;
10011 if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
10012 slide_beacon_adc_pwdb_index = 0;
10013 pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics;
10014 if(pprevious_stats->RxPWDBAll >= 3)
10015 pprevious_stats->RxPWDBAll -= 3;
10016 }
10017
10018 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
10019 pprevious_stats->bIsCCK? "CCK": "OFDM",
10020 pprevious_stats->RxPWDBAll);
10021
10022
10023 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
10024 {
10025 if(priv->undecorated_smoothed_pwdb < 0) // initialize
10026 {
10027 priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
10028 //DbgPrint("First pwdb initialize \n");
10029 }
10030#if 1
10031 if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
10032 {
10033 priv->undecorated_smoothed_pwdb =
10034 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
10035 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
10036 priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1;
10037 }
10038 else
10039 {
10040 priv->undecorated_smoothed_pwdb =
10041 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
10042 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
10043 }
10044#else
10045 //Fixed by Jacken 2008-03-20
10046 if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB)
10047 {
10048 pHalData->UndecoratedSmoothedPWDB =
10049 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
10050 pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1;
10051 }
10052 else
10053 {
10054 pHalData->UndecoratedSmoothedPWDB =
10055 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
10056 }
10057#endif
10058
10059 }
10060
10061 //
10062 // Check EVM
10063 //
10064 /* record the general EVM to the sliding window. */
10065 if(pprevious_stats->SignalQuality == 0)
10066 {
10067 }
10068 else
10069 {
10070 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){
10071 if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){
10072 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
10073 last_evm = priv->stats.slide_evm[slide_evm_index];
10074 priv->stats.slide_evm_total -= last_evm;
10075 }
10076
10077 priv->stats.slide_evm_total += pprevious_stats->SignalQuality;
10078
10079 priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality;
10080 if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
10081 slide_evm_index = 0;
10082
10083 // <1> Showed on UI for user, in percentage.
10084 tmp_val = priv->stats.slide_evm_total/slide_evm_statistics;
10085 priv->stats.signal_quality = tmp_val;
10086 //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality.
10087 priv->stats.last_signal_strength_inpercent = tmp_val;
10088 }
10089
10090 // <2> Showed on UI for engineering
10091 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
10092 {
10093 for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream
10094 {
10095 if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1)
10096 {
10097 if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize
10098 {
10099 priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream];
10100 }
10101 priv->stats.rx_evm_percentage[nspatial_stream] =
10102 ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) +
10103 (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor);
10104 }
10105 }
10106 }
10107 }
10108
10109
10110}
10111
10112/*-----------------------------------------------------------------------------
10113 * Function: rtl819x_query_rxpwrpercentage()
10114 *
10115 * Overview:
10116 *
10117 * Input: char antpower
10118 *
10119 * Output: NONE
10120 *
10121 * Return: 0-100 percentage
10122 *
10123 * Revised History:
10124 * When Who Remark
10125 * 05/26/2008 amy Create Version 0 porting from windows code.
10126 *
10127 *---------------------------------------------------------------------------*/
10128static u8 rtl819x_query_rxpwrpercentage(
10129 char antpower
10130 )
10131{
10132 if ((antpower <= -100) || (antpower >= 20))
10133 {
10134 return 0;
10135 }
10136 else if (antpower >= 0)
10137 {
10138 return 100;
10139 }
10140 else
10141 {
10142 return (100+antpower);
10143 }
10144
10145} /* QueryRxPwrPercentage */
10146
10147static u8
10148rtl819x_evm_dbtopercentage(
10149 char value
10150 )
10151{
10152 char ret_val;
10153
10154 ret_val = value;
10155
10156 if(ret_val >= 0)
10157 ret_val = 0;
10158 if(ret_val <= -33)
10159 ret_val = -33;
10160 ret_val = 0 - ret_val;
10161 ret_val*=3;
10162 if(ret_val == 99)
10163 ret_val = 100;
10164 return(ret_val);
10165}
10166//
10167// Description:
10168// We want good-looking for signal strength/quality
10169// 2007/7/19 01:09, by cosa.
10170//
10171long
10172rtl819x_signal_scale_mapping(
10173 long currsig
10174 )
10175{
10176 long retsig;
10177
10178 // Step 1. Scale mapping.
10179 if(currsig >= 61 && currsig <= 100)
10180 {
10181 retsig = 90 + ((currsig - 60) / 4);
10182 }
10183 else if(currsig >= 41 && currsig <= 60)
10184 {
10185 retsig = 78 + ((currsig - 40) / 2);
10186 }
10187 else if(currsig >= 31 && currsig <= 40)
10188 {
10189 retsig = 66 + (currsig - 30);
10190 }
10191 else if(currsig >= 21 && currsig <= 30)
10192 {
10193 retsig = 54 + (currsig - 20);
10194 }
10195 else if(currsig >= 5 && currsig <= 20)
10196 {
10197 retsig = 42 + (((currsig - 5) * 2) / 3);
10198 }
10199 else if(currsig == 4)
10200 {
10201 retsig = 36;
10202 }
10203 else if(currsig == 3)
10204 {
10205 retsig = 27;
10206 }
10207 else if(currsig == 2)
10208 {
10209 retsig = 18;
10210 }
10211 else if(currsig == 1)
10212 {
10213 retsig = 9;
10214 }
10215 else
10216 {
10217 retsig = currsig;
10218 }
10219
10220 return retsig;
10221}
10222
10223#ifdef RTL8192SU
10224/*-----------------------------------------------------------------------------
10225 * Function: QueryRxPhyStatus8192S()
10226 *
10227 * Overview:
10228 *
10229 * Input: NONE
10230 *
10231 * Output: NONE
10232 *
10233 * Return: NONE
10234 *
10235 * Revised History:
10236 * When Who Remark
10237 * 06/01/2007 MHC Create Version 0.
10238 * 06/05/2007 MHC Accordign to HW's new data sheet, we add CCK and OFDM
10239 * descriptor definition.
10240 * 07/04/2007 MHC According to Jerry and Bryant's document. We read
10241 * ir_isolation and ext_lna for RF's init value and use
10242 * to compensate RSSI after receiving packets.
10243 * 09/10/2008 MHC Modify name and PHY status field for 92SE.
10244 * 09/19/2008 MHC Add CCK/OFDM SS/SQ for 92S series.
10245 *
10246 *---------------------------------------------------------------------------*/
10247static void rtl8192SU_query_rxphystatus(
10248 struct r8192_priv * priv,
10249 struct ieee80211_rx_stats * pstats,
10250 rx_desc_819x_usb *pDesc,
10251 rx_drvinfo_819x_usb * pdrvinfo,
10252 struct ieee80211_rx_stats * precord_stats,
10253 bool bpacket_match_bssid,
10254 bool bpacket_toself,
10255 bool bPacketBeacon,
10256 bool bToSelfBA
10257 )
10258{
10259 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
10260 //PHY_STS_CCK_8192S_T *pCck_buf;
10261 phy_sts_cck_819xusb_t * pcck_buf;
10262 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
10263 //u8 *prxpkt;
10264 //u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
10265 u8 i, max_spatial_stream, rxsc_sgien_exflg;
10266 char rx_pwr[4], rx_pwr_all=0;
10267 //long rx_avg_pwr = 0;
10268 //char rx_snrX, rx_evmX;
10269 u8 evm, pwdb_all;
10270 u32 RSSI, total_rssi=0;//, total_evm=0;
10271// long signal_strength_index = 0;
10272 u8 is_cck_rate=0;
10273 u8 rf_rx_num = 0;
10274
10275
10276
10277 priv->stats.numqry_phystatus++;
10278
10279 is_cck_rate = rx_hal_is_cck_rate(pDesc);
10280
10281 // Record it for next packet processing
10282 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
10283 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
10284 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
10285 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
10286 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
10287 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
10288
10289#ifndef RTL8192SU
10290 phy_sts_ofdm_819xusb_t* pofdm_buf = NULL;
10291 prxpkt = (u8*)pdrvinfo;
10292
10293 /* Move pointer to the 16th bytes. Phy status start address. */
10294 prxpkt += sizeof(rx_drvinfo_819x_usb);
10295
10296 /* Initial the cck and ofdm buffer pointer */
10297 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
10298 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
10299#endif
10300
10301 pstats->RxMIMOSignalQuality[0] = -1;
10302 pstats->RxMIMOSignalQuality[1] = -1;
10303 precord_stats->RxMIMOSignalQuality[0] = -1;
10304 precord_stats->RxMIMOSignalQuality[1] = -1;
10305
10306 if(is_cck_rate)
10307 {
10308 u8 report;//, tmp_pwdb;
10309 //char cck_adc_pwdb[4];
10310
10311 // CCK Driver info Structure is not the same as OFDM packet.
10312 pcck_buf = (phy_sts_cck_819xusb_t *)pdrvinfo;
10313
10314 //
10315 // (1)Hardware does not provide RSSI for CCK
10316 //
10317
10318 //
10319 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10320 //
10321
10322 priv->stats.numqry_phystatusCCK++;
10323
10324 if(!priv->bCckHighPower)
10325 {
10326 report = pcck_buf->cck_agc_rpt & 0xc0;
10327 report = report>>6;
10328 switch(report)
10329 {
10330 //Fixed by Jacken from Bryant 2008-03-20
10331 //Original value is -38 , -26 , -14 , -2
10332 //Fixed value is -35 , -23 , -11 , 6
10333 case 0x3:
10334 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
10335 break;
10336 case 0x2:
10337 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
10338 break;
10339 case 0x1:
10340 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
10341 break;
10342 case 0x0:
10343 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);//6->8
10344 break;
10345 }
10346 }
10347 else
10348 {
10349 report = pdrvinfo->cfosho[0] & 0x60;
10350 report = report>>5;
10351 switch(report)
10352 {
10353 case 0x3:
10354 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10355 break;
10356 case 0x2:
10357 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
10358 break;
10359 case 0x1:
10360 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10361 break;
10362 case 0x0:
10363 rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;//6->-8
10364 break;
10365 }
10366 }
10367
10368 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);//check it
10369 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10370 //pstats->RecvSignalPower = pwdb_all;
10371 pstats->RecvSignalPower = rx_pwr_all;
10372
10373 //
10374 // (3) Get Signal Quality (EVM)
10375 //
10376 //if(bpacket_match_bssid)
10377 {
10378 u8 sq;
10379
10380 if(pstats->RxPWDBAll > 40)
10381 {
10382 sq = 100;
10383 }else
10384 {
10385 sq = pcck_buf->sq_rpt;
10386
10387 if(pcck_buf->sq_rpt > 64)
10388 sq = 0;
10389 else if (pcck_buf->sq_rpt < 20)
10390 sq = 100;
10391 else
10392 sq = ((64-sq) * 100) / 44;
10393 }
10394 pstats->SignalQuality = precord_stats->SignalQuality = sq;
10395 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
10396 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
10397 }
10398 }
10399 else
10400 {
10401 priv->stats.numqry_phystatusHT++;
10402
10403 // 2008/09/19 MH For 92S debug, RX RF path always enable!!
10404 priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = TRUE;
10405
10406 //
10407 // (1)Get RSSI for HT rate
10408 //
10409 //for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
10410 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
10411 {
10412 // 2008/01/30 MH we will judge RF RX path now.
10413 if (priv->brfpath_rxenable[i])
10414 rf_rx_num++;
10415 //else
10416 // continue;
10417
10418 //if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
10419 // continue;
10420
10421 //Fixed by Jacken from Bryant 2008-03-20
10422 //Original value is 106
10423 //rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
10424 rx_pwr[i] = ((pdrvinfo->gain_trsw[i]&0x3F)*2) - 110;
10425
10426 /* Translate DBM to percentage. */
10427 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); //check ok
10428 total_rssi += RSSI;
10429 RT_TRACE(COMP_RF, "RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI);
10430
10431 //Get Rx snr value in DB
10432 //tmp_rxsnr = pofdm_buf->rxsnr_X[i];
10433 //rx_snrX = (char)(tmp_rxsnr);
10434 //rx_snrX /= 2;
10435 //priv->stats.rxSNRdB[i] = (long)rx_snrX;
10436 priv->stats.rxSNRdB[i] = (long)(pdrvinfo->rxsnr[i]/2);
10437
10438 /* Translate DBM to percentage. */
10439 //RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
10440 //total_rssi += RSSI;
10441
10442 /* Record Signal Strength for next packet */
10443 //if(bpacket_match_bssid)
10444 {
10445 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
10446 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
10447 }
10448 }
10449
10450
10451 //
10452 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10453 //
10454 //Fixed by Jacken from Bryant 2008-03-20
10455 //Original value is 106
10456 //rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
10457 rx_pwr_all = (((pdrvinfo->pwdb_all ) >> 1 )& 0x7f) -106;
10458 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10459
10460 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10461 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
10462 pstats->RecvSignalPower = rx_pwr_all;
10463
10464 //
10465 // (3)EVM of HT rate
10466 //
10467 //if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
10468 // pdrvinfo->RxRate<=DESC90_RATEMCS15)
10469 if(pDesc->RxHT && pDesc->RxMCS>=DESC92S_RATEMCS8 &&
10470 pDesc->RxMCS<=DESC92S_RATEMCS15)
10471 max_spatial_stream = 2; //both spatial stream make sense
10472 else
10473 max_spatial_stream = 1; //only spatial stream 1 makes sense
10474
10475 for(i=0; i<max_spatial_stream; i++)
10476 {
10477 //tmp_rxevm = pofdm_buf->rxevm_X[i];
10478 //rx_evmX = (char)(tmp_rxevm);
10479
10480 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
10481 // fill most significant bit to "zero" when doing shifting operation which may change a negative
10482 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
10483 //rx_evmX /= 2; //dbm
10484
10485 //evm = rtl819x_evm_dbtopercentage(rx_evmX);
10486 evm = rtl819x_evm_dbtopercentage( (pdrvinfo->rxevm[i] /*/ 2*/)); //dbm
10487 RT_TRACE(COMP_RF, "RXRATE=%x RXEVM=%x EVM=%s%d\n", pDesc->RxMCS, pdrvinfo->rxevm[i], "%", evm);
10488#if 0
10489 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100//=====>from here
10490#endif
10491
10492 //if(bpacket_match_bssid)
10493 {
10494 if(i==0) // Fill value in RFD, Get the first spatial stream only
10495 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
10496 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
10497 }
10498 }
10499
10500
10501 /* record rx statistics for debug */
10502 //rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
10503 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
10504 //if(pdrvinfo->BW) //40M channel
10505 if(pDesc->BW) //40M channel
10506 priv->stats.received_bwtype[1+pdrvinfo->rxsc]++;
10507 else //20M channel
10508 priv->stats.received_bwtype[0]++;
10509 }
10510
10511 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
10512 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
10513 if(is_cck_rate)
10514 {
10515 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;//check ok
10516
10517 }
10518 else
10519 {
10520 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
10521 // We can judge RX path number now.
10522 if (rf_rx_num != 0)
10523 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
10524 }
10525}/* QueryRxPhyStatus8192S */
10526#else
10527static void rtl8192_query_rxphystatus(
10528 struct r8192_priv * priv,
10529 struct ieee80211_rx_stats * pstats,
10530 rx_drvinfo_819x_usb * pdrvinfo,
10531 struct ieee80211_rx_stats * precord_stats,
10532 bool bpacket_match_bssid,
10533 bool bpacket_toself,
10534 bool bPacketBeacon,
10535 bool bToSelfBA
10536 )
10537{
10538 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
10539 phy_sts_ofdm_819xusb_t* pofdm_buf;
10540 phy_sts_cck_819xusb_t * pcck_buf;
10541 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
10542 u8 *prxpkt;
10543 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
10544 char rx_pwr[4], rx_pwr_all=0;
10545 //long rx_avg_pwr = 0;
10546 char rx_snrX, rx_evmX;
10547 u8 evm, pwdb_all;
10548 u32 RSSI, total_rssi=0;//, total_evm=0;
10549// long signal_strength_index = 0;
10550 u8 is_cck_rate=0;
10551 u8 rf_rx_num = 0;
10552
10553
10554 priv->stats.numqry_phystatus++;
10555
10556 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
10557
10558 // Record it for next packet processing
10559 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
10560 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
10561 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
10562 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
10563 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
10564 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
10565
10566 prxpkt = (u8*)pdrvinfo;
10567
10568 /* Move pointer to the 16th bytes. Phy status start address. */
10569 prxpkt += sizeof(rx_drvinfo_819x_usb);
10570
10571 /* Initial the cck and ofdm buffer pointer */
10572 pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt;
10573 pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt;
10574
10575 pstats->RxMIMOSignalQuality[0] = -1;
10576 pstats->RxMIMOSignalQuality[1] = -1;
10577 precord_stats->RxMIMOSignalQuality[0] = -1;
10578 precord_stats->RxMIMOSignalQuality[1] = -1;
10579
10580 if(is_cck_rate)
10581 {
10582 //
10583 // (1)Hardware does not provide RSSI for CCK
10584 //
10585
10586 //
10587 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10588 //
10589 u8 report;//, cck_agc_rpt;
10590
10591 priv->stats.numqry_phystatusCCK++;
10592
10593 if(!priv->bCckHighPower)
10594 {
10595 report = pcck_buf->cck_agc_rpt & 0xc0;
10596 report = report>>6;
10597 switch(report)
10598 {
10599 //Fixed by Jacken from Bryant 2008-03-20
10600 //Original value is -38 , -26 , -14 , -2
10601 //Fixed value is -35 , -23 , -11 , 6
10602 case 0x3:
10603 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
10604 break;
10605 case 0x2:
10606 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
10607 break;
10608 case 0x1:
10609 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
10610 break;
10611 case 0x0:
10612 rx_pwr_all = 6 - (pcck_buf->cck_agc_rpt & 0x3e);
10613 break;
10614 }
10615 }
10616 else
10617 {
10618 report = pcck_buf->cck_agc_rpt & 0x60;
10619 report = report>>5;
10620 switch(report)
10621 {
10622 case 0x3:
10623 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10624 break;
10625 case 0x2:
10626 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
10627 break;
10628 case 0x1:
10629 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10630 break;
10631 case 0x0:
10632 rx_pwr_all = 6 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
10633 break;
10634 }
10635 }
10636
10637 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10638 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10639 pstats->RecvSignalPower = pwdb_all;
10640
10641 //
10642 // (3) Get Signal Quality (EVM)
10643 //
10644 //if(bpacket_match_bssid)
10645 {
10646 u8 sq;
10647
10648 if(pstats->RxPWDBAll > 40)
10649 {
10650 sq = 100;
10651 }else
10652 {
10653 sq = pcck_buf->sq_rpt;
10654
10655 if(pcck_buf->sq_rpt > 64)
10656 sq = 0;
10657 else if (pcck_buf->sq_rpt < 20)
10658 sq = 100;
10659 else
10660 sq = ((64-sq) * 100) / 44;
10661 }
10662 pstats->SignalQuality = precord_stats->SignalQuality = sq;
10663 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
10664 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
10665 }
10666 }
10667 else
10668 {
10669 priv->stats.numqry_phystatusHT++;
10670 //
10671 // (1)Get RSSI for HT rate
10672 //
10673 for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
10674 {
10675 // 2008/01/30 MH we will judge RF RX path now.
10676 if (priv->brfpath_rxenable[i])
10677 rf_rx_num++;
10678 else
10679 continue;
10680
10681 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
10682 continue;
10683
10684 //Fixed by Jacken from Bryant 2008-03-20
10685 //Original value is 106
10686 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
10687
10688 //Get Rx snr value in DB
10689 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
10690 rx_snrX = (char)(tmp_rxsnr);
10691 //rx_snrX >>= 1;;
10692 rx_snrX /= 2;
10693 priv->stats.rxSNRdB[i] = (long)rx_snrX;
10694
10695 /* Translate DBM to percentage. */
10696 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
10697 total_rssi += RSSI;
10698
10699 /* Record Signal Strength for next packet */
10700 //if(bpacket_match_bssid)
10701 {
10702 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
10703 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
10704 }
10705 }
10706
10707
10708 //
10709 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
10710 //
10711 //Fixed by Jacken from Bryant 2008-03-20
10712 //Original value is 106
10713 rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
10714 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
10715
10716 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
10717 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
10718
10719 //
10720 // (3)EVM of HT rate
10721 //
10722 if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
10723 pdrvinfo->RxRate<=DESC90_RATEMCS15)
10724 max_spatial_stream = 2; //both spatial stream make sense
10725 else
10726 max_spatial_stream = 1; //only spatial stream 1 makes sense
10727
10728 for(i=0; i<max_spatial_stream; i++)
10729 {
10730 tmp_rxevm = pofdm_buf->rxevm_X[i];
10731 rx_evmX = (char)(tmp_rxevm);
10732
10733 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
10734 // fill most significant bit to "zero" when doing shifting operation which may change a negative
10735 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
10736 rx_evmX /= 2; //dbm
10737
10738 evm = rtl819x_evm_dbtopercentage(rx_evmX);
10739#if 0
10740 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100
10741#endif
10742 //if(bpacket_match_bssid)
10743 {
10744 if(i==0) // Fill value in RFD, Get the first spatial stream only
10745 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
10746 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
10747 }
10748 }
10749
10750
10751 /* record rx statistics for debug */
10752 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
10753 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
10754 if(pdrvinfo->BW) //40M channel
10755 priv->stats.received_bwtype[1+prxsc->rxsc]++;
10756 else //20M channel
10757 priv->stats.received_bwtype[0]++;
10758 }
10759
10760 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
10761 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
10762 if(is_cck_rate)
10763 {
10764 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;
10765
10766 }
10767 else
10768 {
10769 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
10770 // We can judge RX path number now.
10771 if (rf_rx_num != 0)
10772 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
10773 }
10774} /* QueryRxPhyStatus8190Pci */
10775#endif
10776
10777void
10778rtl8192_record_rxdesc_forlateruse(
10779 struct ieee80211_rx_stats * psrc_stats,
10780 struct ieee80211_rx_stats * ptarget_stats
10781)
10782{
10783 ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU;
10784 ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU;
10785 ptarget_stats->Seq_Num = psrc_stats->Seq_Num;
10786}
10787
10788#ifdef RTL8192SU
10789static void rtl8192SU_query_rxphystatus(
10790 struct r8192_priv * priv,
10791 struct ieee80211_rx_stats * pstats,
10792 rx_desc_819x_usb *pDesc,
10793 rx_drvinfo_819x_usb * pdrvinfo,
10794 struct ieee80211_rx_stats * precord_stats,
10795 bool bpacket_match_bssid,
10796 bool bpacket_toself,
10797 bool bPacketBeacon,
10798 bool bToSelfBA
10799 );
10800void rtl8192SU_TranslateRxSignalStuff(struct sk_buff *skb,
10801 struct ieee80211_rx_stats * pstats,
10802 rx_desc_819x_usb *pDesc,
10803 rx_drvinfo_819x_usb *pdrvinfo)
10804{
10805 // TODO: We must only check packet for current MAC address. Not finish
10806 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10807 struct net_device *dev=info->dev;
10808 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10809 bool bpacket_match_bssid, bpacket_toself;
10810 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
10811 static struct ieee80211_rx_stats previous_stats;
10812 struct ieee80211_hdr_3addr *hdr;//by amy
10813 u16 fc,type;
10814
10815 // Get Signal Quality for only RX data queue (but not command queue)
10816
10817 u8* tmp_buf;
10818 //u16 tmp_buf_len = 0;
10819 u8 *praddr;
10820
10821 /* Get MAC frame start address. */
10822 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
10823
10824 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
10825 fc = le16_to_cpu(hdr->frame_ctl);
10826 type = WLAN_FC_GET_TYPE(fc);
10827 praddr = hdr->addr1;
10828
10829 /* Check if the received packet is acceptabe. */
10830 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
10831 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
10832 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
10833 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
10834
10835#if 1//cosa
10836 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
10837 {
10838 bPacketBeacon = true;
10839 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10840 }
10841 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
10842 {
10843 if((eqMacAddr(praddr,dev->dev_addr)))
10844 bToSelfBA = true;
10845 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10846 }
10847
10848#endif
10849
10850
10851 if(bpacket_match_bssid)
10852 {
10853 priv->stats.numpacket_matchbssid++;
10854 }
10855 if(bpacket_toself){
10856 priv->stats.numpacket_toself++;
10857 }
10858 //
10859 // Process PHY information for previous packet (RSSI/PWDB/EVM)
10860 //
10861 // Because phy information is contained in the last packet of AMPDU only, so driver
10862 // should process phy information of previous packet
10863 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
10864 rtl8192SU_query_rxphystatus(priv, pstats, pDesc, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
10865 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
10866
10867}
10868#else
10869void TranslateRxSignalStuff819xUsb(struct sk_buff *skb,
10870 struct ieee80211_rx_stats * pstats,
10871 rx_drvinfo_819x_usb *pdrvinfo)
10872{
10873 // TODO: We must only check packet for current MAC address. Not finish
10874 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
10875 struct net_device *dev=info->dev;
10876 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10877 bool bpacket_match_bssid, bpacket_toself;
10878 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
10879 static struct ieee80211_rx_stats previous_stats;
10880 struct ieee80211_hdr_3addr *hdr;//by amy
10881 u16 fc,type;
10882
10883 // Get Signal Quality for only RX data queue (but not command queue)
10884
10885 u8* tmp_buf;
10886 //u16 tmp_buf_len = 0;
10887 u8 *praddr;
10888
10889 /* Get MAC frame start address. */
10890 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
10891
10892 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
10893 fc = le16_to_cpu(hdr->frame_ctl);
10894 type = WLAN_FC_GET_TYPE(fc);
10895 praddr = hdr->addr1;
10896
10897 /* Check if the received packet is acceptabe. */
10898 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
10899 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
10900 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
10901 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
10902
10903#if 1//cosa
10904 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
10905 {
10906 bPacketBeacon = true;
10907 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10908 }
10909 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
10910 {
10911 if((eqMacAddr(praddr,dev->dev_addr)))
10912 bToSelfBA = true;
10913 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
10914 }
10915
10916#endif
10917
10918
10919 if(bpacket_match_bssid)
10920 {
10921 priv->stats.numpacket_matchbssid++;
10922 }
10923 if(bpacket_toself){
10924 priv->stats.numpacket_toself++;
10925 }
10926 //
10927 // Process PHY information for previous packet (RSSI/PWDB/EVM)
10928 //
10929 // Because phy information is contained in the last packet of AMPDU only, so driver
10930 // should process phy information of previous packet
10931 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
10932 rtl8192_query_rxphystatus(priv, pstats, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
10933 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
10934
10935}
10936#endif
10937
10938/**
10939* Function: UpdateReceivedRateHistogramStatistics
10940* Overview: Recored down the received data rate
10941*
10942* Input:
10943* struct net_device *dev
10944* struct ieee80211_rx_stats *stats
10945*
10946* Output:
10947*
10948* (priv->stats.ReceivedRateHistogram[] is updated)
10949* Return:
10950* None
10951*/
10952void
10953UpdateReceivedRateHistogramStatistics8190(
10954 struct net_device *dev,
10955 struct ieee80211_rx_stats *stats
10956 )
10957{
10958 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
10959 u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV
10960 u32 rateIndex;
10961 u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI
10962
10963
10964 if(stats->bCRC)
10965 rcvType = 2;
10966 else if(stats->bICV)
10967 rcvType = 3;
10968
10969 if(stats->bShortPreamble)
10970 preamble_guardinterval = 1;// short
10971 else
10972 preamble_guardinterval = 0;// long
10973
10974 switch(stats->rate)
10975 {
10976 //
10977 // CCK rate
10978 //
10979 case MGN_1M: rateIndex = 0; break;
10980 case MGN_2M: rateIndex = 1; break;
10981 case MGN_5_5M: rateIndex = 2; break;
10982 case MGN_11M: rateIndex = 3; break;
10983 //
10984 // Legacy OFDM rate
10985 //
10986 case MGN_6M: rateIndex = 4; break;
10987 case MGN_9M: rateIndex = 5; break;
10988 case MGN_12M: rateIndex = 6; break;
10989 case MGN_18M: rateIndex = 7; break;
10990 case MGN_24M: rateIndex = 8; break;
10991 case MGN_36M: rateIndex = 9; break;
10992 case MGN_48M: rateIndex = 10; break;
10993 case MGN_54M: rateIndex = 11; break;
10994 //
10995 // 11n High throughput rate
10996 //
10997 case MGN_MCS0: rateIndex = 12; break;
10998 case MGN_MCS1: rateIndex = 13; break;
10999 case MGN_MCS2: rateIndex = 14; break;
11000 case MGN_MCS3: rateIndex = 15; break;
11001 case MGN_MCS4: rateIndex = 16; break;
11002 case MGN_MCS5: rateIndex = 17; break;
11003 case MGN_MCS6: rateIndex = 18; break;
11004 case MGN_MCS7: rateIndex = 19; break;
11005 case MGN_MCS8: rateIndex = 20; break;
11006 case MGN_MCS9: rateIndex = 21; break;
11007 case MGN_MCS10: rateIndex = 22; break;
11008 case MGN_MCS11: rateIndex = 23; break;
11009 case MGN_MCS12: rateIndex = 24; break;
11010 case MGN_MCS13: rateIndex = 25; break;
11011 case MGN_MCS14: rateIndex = 26; break;
11012 case MGN_MCS15: rateIndex = 27; break;
11013 default: rateIndex = 28; break;
11014 }
11015 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
11016 priv->stats.received_rate_histogram[0][rateIndex]++; //total
11017 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
11018}
11019
11020#ifdef RTL8192SU
11021void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
11022{
11023 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11024 struct net_device *dev=info->dev;
11025 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11026 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11027 rx_drvinfo_819x_usb *driver_info = NULL;
11028
11029 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
11030 //PHAL_DATA_8192SUSB pHalData = GET_HAL_DATA(Adapter);
11031 //pu1Byte pDesc = (pu1Byte)pDescIn;
11032 //PRX_DRIVER_INFO_8192S pDrvInfo;
11033
11034#ifdef USB_RX_AGGREGATION_SUPPORT//FIXLZM
11035 //if (bIsRxAggrSubframe)
11036 rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data;
11037 else
11038#endif
11039 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11040
11041 if(0)
11042 {
11043 int m = 0;
11044 printk("========================");
11045 for(m=0; m<skb->len; m++){
11046 if((m%32) == 0)
11047 printk("\n");
11048 printk("%2x ",((u8*)skb->data)[m]);
11049 }
11050 printk("\n========================\n");
11051
11052 }
11053
11054
11055 //
11056 //Get Rx Descriptor Raw Information
11057 //
11058 stats->Length = desc->Length ;
11059 stats->RxDrvInfoSize = desc->RxDrvInfoSize*RX_DRV_INFO_SIZE_UNIT;
11060 stats->RxBufShift = (desc->Shift)&0x03;
11061 stats->bICV = desc->ICV;
11062 stats->bCRC = desc->CRC32;
11063 stats->bHwError = stats->bCRC|stats->bICV;
11064 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
11065 stats->bIsAMPDU = (desc->AMSDU==1);
11066 stats->bFirstMPDU = (desc->PAGGR==1) && (desc->FAGGR==1);
11067 stats->bShortPreamble = desc->SPLCP;
11068 stats->RxIs40MHzPacket = (desc->BW==1);
11069 stats->TimeStampLow = desc->TSFL;
11070
11071 if((desc->FAGGR==1) || (desc->PAGGR==1))
11072 {// Rx A-MPDU
11073 RT_TRACE(COMP_RXDESC, "FirstAGGR = %d, PartAggr = %d\n", desc->FAGGR, desc->PAGGR);
11074 }
11075//YJ,test,090310
11076if(stats->bHwError)
11077{
11078 if(stats->bICV)
11079 printk("%s: Receive ICV error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
11080 if(stats->bCRC)
11081 printk("%s: Receive CRC error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
11082}
11083
11084 if(IS_UNDER_11N_AES_MODE(priv->ieee80211))
11085 {
11086 // Always received ICV error packets in AES mode.
11087 // This fixed HW later MIC write bug.
11088 if(stats->bICV && !stats->bCRC)
11089 {
11090 stats->bICV = FALSE;
11091 stats->bHwError = FALSE;
11092 }
11093 }
11094
11095 // Transform HwRate to MRate
11096 if(!stats->bHwError)
11097 //stats->DataRate = HwRateToMRate(
11098 // (BOOLEAN)GET_RX_DESC_RXHT(pDesc),
11099 // (u1Byte)GET_RX_DESC_RXMCS(pDesc),
11100 // (BOOLEAN)GET_RX_DESC_PAGGR(pDesc));
11101 stats->rate = rtl8192SU_HwRateToMRate(desc->RxHT, desc->RxMCS, desc->PAGGR);
11102 else
11103 stats->rate = MGN_1M;
11104
11105 //
11106 // Collect Rx rate/AMPDU/TSFL
11107 //
11108 //UpdateRxdRateHistogramStatistics8192S(Adapter, pRfd);
11109 //UpdateRxAMPDUHistogramStatistics8192S(Adapter, pRfd);
11110 //UpdateRxPktTimeStamp8192S(Adapter, pRfd);
11111 UpdateReceivedRateHistogramStatistics8190(dev, stats);
11112 //UpdateRxAMPDUHistogramStatistics8192S(dev, stats); //FIXLZM
11113 UpdateRxPktTimeStamp8190(dev, stats);
11114
11115 //
11116 // Get PHY Status and RSVD parts.
11117 // <Roger_Notes> It only appears on last aggregated packet.
11118 //
11119 if (desc->PHYStatus)
11120 {
11121 //driver_info = (rx_drvinfo_819x_usb *)(skb->data + RX_DESC_SIZE + stats->RxBufShift);
11122 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
11123 stats->RxBufShift);
11124 if(0)
11125 {
11126 int m = 0;
11127 printk("========================\n");
11128 printk("RX_DESC_SIZE:%d, RxBufShift:%d, RxDrvInfoSize:%d\n",
11129 RX_DESC_SIZE, stats->RxBufShift, stats->RxDrvInfoSize);
11130 for(m=0; m<32; m++){
11131 printk("%2x ",((u8*)driver_info)[m]);
11132 }
11133 printk("\n========================\n");
11134
11135 }
11136
11137 }
11138
11139 //YJ,add,090107
11140 skb_pull(skb, sizeof(rx_desc_819x_usb));
11141 //YJ,add,090107,end
11142
11143 //
11144 // Get Total offset of MPDU Frame Body
11145 //
11146 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
11147 {
11148 stats->bShift = 1;
11149 //YJ,add,090107
11150 skb_pull(skb, stats->RxBufShift + stats->RxDrvInfoSize);
11151 //YJ,add,090107,end
11152 }
11153
11154 //
11155 // Get PHY Status and RSVD parts.
11156 // <Roger_Notes> It only appears on last aggregated packet.
11157 //
11158 if (desc->PHYStatus)
11159 {
11160 rtl8192SU_TranslateRxSignalStuff(skb, stats, desc, driver_info);
11161 }
11162}
11163#else
11164void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
11165{
11166 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11167 struct net_device *dev=info->dev;
11168 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11169 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11170 rx_drvinfo_819x_usb *driver_info = NULL;
11171
11172 //
11173 //Get Rx Descriptor Information
11174 //
11175#ifdef USB_RX_AGGREGATION_SUPPORT
11176 if (bIsRxAggrSubframe)
11177 {
11178 rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data;
11179 stats->Length = desc->Length ;
11180 stats->RxDrvInfoSize = desc->RxDrvInfoSize;
11181 stats->RxBufShift = 0; //RxBufShift = 2 in RxDesc, but usb didn't shift bytes in fact.
11182 stats->bICV = desc->ICV;
11183 stats->bCRC = desc->CRC32;
11184 stats->bHwError = stats->bCRC|stats->bICV;
11185 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
11186 } else
11187#endif
11188 {
11189 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11190
11191 stats->Length = desc->Length;
11192 stats->RxDrvInfoSize = desc->RxDrvInfoSize;
11193 stats->RxBufShift = 0;//desc->Shift&0x03;
11194 stats->bICV = desc->ICV;
11195 stats->bCRC = desc->CRC32;
11196 stats->bHwError = stats->bCRC|stats->bICV;
11197 //RTL8190 set this bit to indicate that Hw does not decrypt packet
11198 stats->Decrypted = !desc->SWDec;
11199 }
11200
11201 if((priv->ieee80211->pHTInfo->bCurrentHTSupport == true) && (priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP))
11202 {
11203 stats->bHwError = false;
11204 }
11205 else
11206 {
11207 stats->bHwError = stats->bCRC|stats->bICV;
11208 }
11209
11210 if(stats->Length < 24 || stats->Length > MAX_8192U_RX_SIZE)
11211 stats->bHwError |= 1;
11212 //
11213 //Get Driver Info
11214 //
11215 // TODO: Need to verify it on FGPA platform
11216 //Driver info are written to the RxBuffer following rx desc
11217 if (stats->RxDrvInfoSize != 0) {
11218 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
11219 stats->RxBufShift);
11220 /* unit: 0.5M */
11221 /* TODO */
11222 if(!stats->bHwError){
11223 u8 ret_rate;
11224 ret_rate = HwRateToMRate90(driver_info->RxHT, driver_info->RxRate);
11225 if(ret_rate == 0xff)
11226 {
11227 // Abnormal Case: Receive CRC OK packet with Rx descriptor indicating non supported rate.
11228 // Special Error Handling here, 2008.05.16, by Emily
11229
11230 stats->bHwError = 1;
11231 stats->rate = MGN_1M; //Set 1M rate by default
11232 }else
11233 {
11234 stats->rate = ret_rate;
11235 }
11236 }
11237 else
11238 stats->rate = 0x02;
11239
11240 stats->bShortPreamble = driver_info->SPLCP;
11241
11242
11243 UpdateReceivedRateHistogramStatistics8190(dev, stats);
11244
11245 stats->bIsAMPDU = (driver_info->PartAggr==1);
11246 stats->bFirstMPDU = (driver_info->PartAggr==1) && (driver_info->FirstAGGR==1);
11247#if 0
11248 // TODO: it is debug only. It should be disabled in released driver. 2007.1.12 by Joseph
11249 UpdateRxAMPDUHistogramStatistics8190(Adapter, pRfd);
11250#endif
11251 stats->TimeStampLow = driver_info->TSFL;
11252 // xiong mask it, 070514
11253 //pRfd->Status.TimeStampHigh = PlatformEFIORead4Byte(Adapter, TSFR+4);
11254 // stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
11255
11256 UpdateRxPktTimeStamp8190(dev, stats);
11257
11258 //
11259 // Rx A-MPDU
11260 //
11261 if(driver_info->FirstAGGR==1 || driver_info->PartAggr == 1)
11262 RT_TRACE(COMP_RXDESC, "driver_info->FirstAGGR = %d, driver_info->PartAggr = %d\n",
11263 driver_info->FirstAGGR, driver_info->PartAggr);
11264
11265 }
11266
11267 skb_pull(skb,sizeof(rx_desc_819x_usb));
11268 //
11269 // Get Total offset of MPDU Frame Body
11270 //
11271 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) {
11272 stats->bShift = 1;
11273 skb_pull(skb,stats->RxBufShift + stats->RxDrvInfoSize);
11274 }
11275
11276#ifdef USB_RX_AGGREGATION_SUPPORT
11277 /* for the rx aggregated sub frame, the redundant space truelly contained in the packet */
11278 if(bIsRxAggrSubframe) {
11279 skb_pull(skb, 8);
11280 }
11281#endif
11282 /* for debug 2008.5.29 */
11283#if 0
11284 {
11285 int i;
11286 printk("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
11287 for(i = 0; i < skb->len; i++) {
11288 if(i % 10 == 0) printk("\n");
11289 printk("%02x ", skb->data[i]);
11290 }
11291 printk("\n<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
11292 }
11293#endif
11294
11295 //added by vivi, for MP, 20080108
11296 stats->RxIs40MHzPacket = driver_info->BW;
11297 if(stats->RxDrvInfoSize != 0)
11298 TranslateRxSignalStuff819xUsb(skb, stats, driver_info);
11299
11300}
11301#endif
11302
11303#ifdef RTL8192SU
11304#if 0
11305/*-----------------------------------------------------------------------------
11306 * Function: UpdateRxAMPDUHistogramStatistics8192S
11307 *
11308 * Overview: Recored down the received A-MPDU aggregation size and pkt number
11309 *
11310 * Input: Adapter
11311 *
11312 * Output: Adapter
11313 * (Adapter->RxStats.RxAMPDUSizeHistogram[] is updated)
11314 * (Adapter->RxStats.RxAMPDUNumHistogram[] is updated)
11315 *
11316 * Return: NONE
11317 *
11318 * Revised History:
11319 * When Who Remark
11320 * 09/18/2008 MHC Create Version 0.
11321 *
11322 *---------------------------------------------------------------------------*/
11323static void
11324UpdateRxAMPDUHistogramStatistics8192S(
11325 struct net_device *dev,
11326 struct ieee80211_rx_stats *stats
11327 )
11328{
11329 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
11330 u8 size_index;
11331 u8 num_index;
11332 u16 update_size = 0;
11333 u8 update_num = 0;
11334
11335 if(stats->bIsAMPDU)
11336 {
11337 if(stats->bFirstMPDU)
11338 {
11339 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
11340 {
11341 update_size = stats->nRxAMPDU_Size;
11342 update_num = stats->nRxAMPDU_AggrNum;
11343 }
11344 stats->nRxAMPDU_Size = stats->Length;
11345 stats->nRxAMPDU_AggrNum = 1;
11346 }
11347 else
11348 {
11349 stats->nRxAMPDU_Size += stats->Length;
11350 stats->nRxAMPDU_AggrNum++;
11351 }
11352 }
11353 else
11354 {
11355 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
11356 {
11357 update_size = stats->nRxAMPDU_Size;
11358 update_num = stats->nRxAMPDU_AggrNum;
11359 }
11360 stats->nRxAMPDU_Size = 0;
11361 stats->nRxAMPDU_AggrNum = 0;
11362 }
11363
11364 if(update_size!=0 && update_num!= 0)
11365 {
11366 if(update_size < 4096)
11367 size_index = 0;
11368 else if(update_size < 8192)
11369 size_index = 1;
11370 else if(update_size < 16384)
11371 size_index = 2;
11372 else if(update_size < 32768)
11373 size_index = 3;
11374 else if(update_size < 65536)
11375 size_index = 4;
11376 else
11377 {
11378 RT_TRACE(COMP_RXDESC,
11379 ("UpdateRxAMPDUHistogramStatistics8192S(): A-MPDU too large\n");
11380 }
11381
11382 Adapter->RxStats.RxAMPDUSizeHistogram[size_index]++;
11383
11384 if(update_num < 5)
11385 num_index = 0;
11386 else if(update_num < 10)
11387 num_index = 1;
11388 else if(update_num < 20)
11389 num_index = 2;
11390 else if(update_num < 40)
11391 num_index = 3;
11392 else
11393 num_index = 4;
11394
11395 Adapter->RxStats.RxAMPDUNumHistogram[num_index]++;
11396 }
11397} // UpdateRxAMPDUHistogramStatistics8192S
11398#endif
11399
11400#endif
11401
11402
11403#ifdef RTL8192SU
11404//
11405// Description:
11406// The strarting address of wireless lan header will shift 1 or 2 or 3 or "more" bytes for the following reason :
11407// (1) QoS control : shift 2 bytes
11408// (2) Mesh Network : shift 1 or 3 bytes
11409// (3) RxDriverInfo occupies the front parts of Rx Packets buffer(shift units is in 8Bytes)
11410//
11411// It is because Lextra CPU used by 8186 or 865x series assert exception if the statrting address
11412// of IP header is not double word alignment.
11413// This features is supported in 818xb and 8190 only, but not 818x.
11414//
11415// parameter: PRT_RFD, Pointer of Reeceive frame descriptor which is initialized according to
11416// Rx Descriptor
11417// return value: unsigned int, number of total shifted bytes
11418//
11419// Notes: 2008/06/28, created by Roger
11420//
11421u32 GetRxPacketShiftBytes8192SU(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
11422{
11423 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
11424
11425 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + Status->RxBufShift);
11426}
11427
11428void rtl8192SU_rx_nomal(struct sk_buff* skb)
11429{
11430 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11431 struct net_device *dev=info->dev;
11432 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11433 struct ieee80211_rx_stats stats = {
11434 .signal = 0,
11435 .noise = -98,
11436 .rate = 0,
11437 // .mac_time = jiffies,
11438 .freq = IEEE80211_24GHZ_BAND,
11439 };
11440 u32 rx_pkt_len = 0;
11441 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
11442 bool unicast_packet = false;
11443
11444#ifdef USB_RX_AGGREGATION_SUPPORT
11445 struct sk_buff *agg_skb = NULL;
11446 u32 TotalLength = 0;//Total packet length for all aggregated packets.
11447 u32 TempDWord = 0;
11448 u32 PacketLength = 0;// Per-packet length include size of RxDesc.
11449 u32 PacketOccupiedLendth = 0;
11450 u8 TempByte = 0;
11451 u32 PacketShiftBytes = 0;
11452 rx_desc_819x_usb_aggr_subframe *RxDescr = NULL;
11453 u8 PaddingBytes = 0;
11454 //add just for testing
11455 u8 testing;
11456
11457 u8 TotalAggPkt = 0;
11458 PRT_HIGH_THROUGHPUT pHTInfo =priv-> ieee80211->pHTInfo;
11459 u16 RxPageSize = pHTInfo->UsbRxPageSize;
11460
11461 stats->nTotalAggPkt = 0;
11462 //stats->bIsRxAggrSubframe = FALSE;
11463
11464#endif
11465 //printk("**********skb->len = %d\n", skb->len);
11466 /* 20 is for ps-poll */
11467 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
11468
11469 /* first packet should not contain Rx aggregation header */
11470 rtl8192SU_query_rxdesc_status(skb, &stats, false);
11471 /* TODO */
11472
11473 /* hardware related info */
11474#ifdef USB_RX_AGGREGATION_SUPPORT
11475 TotalAggPkt = stats->nTotalAggPkt;
11476 PacketLength = stats->Length + GetRxPacketShiftBytes8192SU(&stats, false);
11477
11478 agg_skb = skb;
11479 skb = dev_alloc_skb(PacketLength);
11480 memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength);
11481#endif
11482 priv->stats.rxoktotal++; //YJ,test,090108
11483
11484 /* Process the MPDU recevied */
11485 skb_trim(skb, skb->len - 4/*sCrcLng*/);//FIXLZM
11486
11487 rx_pkt_len = skb->len;
11488 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11489 unicast_packet = false;
11490 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11491 //TODO
11492 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11493 //TODO
11494 }else {
11495 /* unicast packet */
11496 unicast_packet = true;
11497 }
11498
11499 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11500 dev_kfree_skb_any(skb);
11501 } else {
11502 // priv->stats.rxoktotal++; //YJ,test,090108
11503 if(unicast_packet) {
11504 priv->stats.rxbytesunicast += rx_pkt_len;
11505 }
11506 }
11507
11508 //up is firs pkt, follow is next and next
11509#ifdef USB_RX_AGGREGATION_SUPPORT
11510 //
11511 // The following operations are for processing Rx aggregated packets.
11512 //
11513 if(TotalAggPkt>0)
11514 TotalAggPkt--;
11515
11516 while ( TotalAggPkt>0 )
11517 {// More aggregated packets need to process.
11518
11519 u8 tmpCRC = 0, tmpICV = 0;
11520
11521 //Page size must align to multiple of 128-Bytes.
11522 if((PacketLength%RxPageSize) != 0)
11523 //PacketLength = ((PacketLength/RxPageSize)+1)*RxPageSize;
11524 PacketLength = ((PacketLength>>7)+1)*RxPageSize; // RxPageSize is 128bytes as default.
11525
11526 // Current total packet occupied length in this buffer.
11527 PacketOccupiedLendth += PacketLength;
11528
11529#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
11530 //if(PacketOccupiedLendth>pContext->BufLenUsed)
11531 if(PacketOccupiedLendth>skb->len)
11532 {
11533 RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): pRtRfdStatus->Length(%#x)!!\n", stats->Length);
11534 RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)!!, BufLenUsed(%#x)\n", PacketOccupiedLendth, stats->BufLenUsed);
11535 break;
11536 }
11537#endif
11538
11539 skb_pull(agg_skb, PacketLength);
11540
11541 //
11542 // Process the MPDU recevied.
11543 //
11544 //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len);
11545 RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data);
11546
11547#if 0//92SU del
11548 tmpCRC = RxDescr->CRC32;
11549 tmpICV = RxDescr->ICV;
11550 memcpy(agg_skb->data, &agg_skb->data[44], 2);
11551 RxDescr->CRC32 = tmpCRC;
11552 RxDescr->ICV = tmpICV;
11553#endif
11554 memset(&stats, 0, sizeof(struct ieee80211_rx_stats));
11555 stats.signal = 0;
11556 stats.noise = -98;
11557 stats.rate = 0;
11558 stats.freq = IEEE80211_24GHZ_BAND;
11559
11560 rtl8192SU_query_rxdesc_status(agg_skb, &stats, true);
11561 //PacketLength = stats.Length;
11562 PacketLength = stats.Length + GetRxPacketShiftBytes8192SU(&stats, true);
11563
11564#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION))
11565 if((PacketOccupiedLendth+PacketLength)>skb->len)
11566 {
11567 RT_TRACE(COMP_RECV, "(2)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)+PacketLength(%#x)!!, BufLenUsed(%#x)\n",
11568 PacketOccupiedLendth, PacketLength, pContext->BufLenUsed);
11569 break;
11570 }
11571#endif
11572
11573 if(PacketLength > agg_skb->len) {
11574 break;
11575 }
11576
11577 /* Process the MPDU recevied */
11578 skb = dev_alloc_skb(PacketLength);
11579 memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength);
11580 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11581
11582 rx_pkt_len = skb->len;
11583 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11584 unicast_packet = false;
11585 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11586 //TODO
11587 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11588 //TODO
11589 }else {
11590 /* unicast packet */
11591 unicast_packet = true;
11592 }
11593 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11594 dev_kfree_skb_any(skb);
11595 } else {
11596 priv->stats.rxoktotal++;
11597 if(unicast_packet) {
11598 priv->stats.rxbytesunicast += rx_pkt_len;
11599 }
11600 }
11601
11602 TotalAggPkt--;
11603
11604 skb_pull(agg_skb, TempDWord);
11605 }
11606
11607 dev_kfree_skb(agg_skb);
11608#endif
11609 }
11610 else
11611 {
11612 priv->stats.rxurberr++;
11613 printk("actual_length:%d\n", skb->len);
11614 dev_kfree_skb_any(skb);
11615 }
11616
11617}
11618#else
11619u32 GetRxPacketShiftBytes819xUsb(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
11620{
11621#ifdef USB_RX_AGGREGATION_SUPPORT
11622 if (bIsRxAggrSubframe)
11623 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize
11624 + Status->RxBufShift + 8);
11625 else
11626#endif
11627 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize
11628 + Status->RxBufShift);
11629}
11630
11631void rtl8192_rx_nomal(struct sk_buff* skb)
11632{
11633 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11634 struct net_device *dev=info->dev;
11635 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11636 struct ieee80211_rx_stats stats = {
11637 .signal = 0,
11638 .noise = -98,
11639 .rate = 0,
11640 // .mac_time = jiffies,
11641 .freq = IEEE80211_24GHZ_BAND,
11642 };
11643 u32 rx_pkt_len = 0;
11644 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
11645 bool unicast_packet = false;
11646#ifdef USB_RX_AGGREGATION_SUPPORT
11647 struct sk_buff *agg_skb = NULL;
11648 u32 TotalLength = 0;
11649 u32 TempDWord = 0;
11650 u32 PacketLength = 0;
11651 u32 PacketOccupiedLendth = 0;
11652 u8 TempByte = 0;
11653 u32 PacketShiftBytes = 0;
11654 rx_desc_819x_usb_aggr_subframe *RxDescr = NULL;
11655 u8 PaddingBytes = 0;
11656 //add just for testing
11657 u8 testing;
11658
11659#endif
11660
11661 /* 20 is for ps-poll */
11662 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
11663#ifdef USB_RX_AGGREGATION_SUPPORT
11664 TempByte = *(skb->data + sizeof(rx_desc_819x_usb));
11665#endif
11666 /* first packet should not contain Rx aggregation header */
11667 query_rxdesc_status(skb, &stats, false);
11668 /* TODO */
11669 /* hardware related info */
11670#ifdef USB_RX_AGGREGATION_SUPPORT
11671 if (TempByte & BIT0) {
11672 agg_skb = skb;
11673 //TotalLength = agg_skb->len - 4; /*sCrcLng*/
11674 TotalLength = stats.Length - 4; /*sCrcLng*/
11675 //RT_TRACE(COMP_RECV, "%s:first aggregated packet!Length=%d\n",__FUNCTION__,TotalLength);
11676 /* though the head pointer has passed this position */
11677 TempDWord = *(u32 *)(agg_skb->data - 4);
11678 PacketLength = (u16)(TempDWord & 0x3FFF); /*sCrcLng*/
11679 skb = dev_alloc_skb(PacketLength);
11680 memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength);
11681 PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, false);
11682 }
11683#endif
11684 /* Process the MPDU recevied */
11685 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11686
11687 rx_pkt_len = skb->len;
11688 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11689 unicast_packet = false;
11690 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11691 //TODO
11692 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11693 //TODO
11694 }else {
11695 /* unicast packet */
11696 unicast_packet = true;
11697 }
11698
11699 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11700 dev_kfree_skb_any(skb);
11701 } else {
11702 priv->stats.rxoktotal++;
11703 if(unicast_packet) {
11704 priv->stats.rxbytesunicast += rx_pkt_len;
11705 }
11706 }
11707#ifdef USB_RX_AGGREGATION_SUPPORT
11708 testing = 1;
11709 // (PipeIndex == 0) && (TempByte & BIT0) => TotalLength > 0.
11710 if (TotalLength > 0) {
11711 PacketOccupiedLendth = PacketLength + (PacketShiftBytes + 8);
11712 if ((PacketOccupiedLendth & 0xFF) != 0)
11713 PacketOccupiedLendth = (PacketOccupiedLendth & 0xFFFFFF00) + 256;
11714 PacketOccupiedLendth -= 8;
11715 TempDWord = PacketOccupiedLendth - PacketShiftBytes; /*- PacketLength */
11716 if (agg_skb->len > TempDWord)
11717 skb_pull(agg_skb, TempDWord);
11718 else
11719 agg_skb->len = 0;
11720
11721 while (agg_skb->len>=GetRxPacketShiftBytes819xUsb(&stats, true)) {
11722 u8 tmpCRC = 0, tmpICV = 0;
11723 //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len);
11724 RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data);
11725 tmpCRC = RxDescr->CRC32;
11726 tmpICV = RxDescr->ICV;
11727 memcpy(agg_skb->data, &agg_skb->data[44], 2);
11728 RxDescr->CRC32 = tmpCRC;
11729 RxDescr->ICV = tmpICV;
11730
11731 memset(&stats, 0, sizeof(struct ieee80211_rx_stats));
11732 stats.signal = 0;
11733 stats.noise = -98;
11734 stats.rate = 0;
11735 stats.freq = IEEE80211_24GHZ_BAND;
11736 query_rxdesc_status(agg_skb, &stats, true);
11737 PacketLength = stats.Length;
11738
11739 if(PacketLength > agg_skb->len) {
11740 break;
11741 }
11742 /* Process the MPDU recevied */
11743 skb = dev_alloc_skb(PacketLength);
11744 memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength);
11745 skb_trim(skb, skb->len - 4/*sCrcLng*/);
11746
11747 rx_pkt_len = skb->len;
11748 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
11749 unicast_packet = false;
11750 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
11751 //TODO
11752 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
11753 //TODO
11754 }else {
11755 /* unicast packet */
11756 unicast_packet = true;
11757 }
11758 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
11759 dev_kfree_skb_any(skb);
11760 } else {
11761 priv->stats.rxoktotal++;
11762 if(unicast_packet) {
11763 priv->stats.rxbytesunicast += rx_pkt_len;
11764 }
11765 }
11766 /* should trim the packet which has been copied to target skb */
11767 skb_pull(agg_skb, PacketLength);
11768 PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, true);
11769 PacketOccupiedLendth = PacketLength + PacketShiftBytes;
11770 if ((PacketOccupiedLendth & 0xFF) != 0) {
11771 PaddingBytes = 256 - (PacketOccupiedLendth & 0xFF);
11772 if (agg_skb->len > PaddingBytes)
11773 skb_pull(agg_skb, PaddingBytes);
11774 else
11775 agg_skb->len = 0;
11776 }
11777 }
11778 dev_kfree_skb(agg_skb);
11779 }
11780#endif
11781 } else {
11782 priv->stats.rxurberr++;
11783 printk("actual_length:%d\n", skb->len);
11784 dev_kfree_skb_any(skb);
11785 }
11786
11787}
11788
11789#endif
11790
11791void
11792rtl819xusb_process_received_packet(
11793 struct net_device *dev,
11794 struct ieee80211_rx_stats *pstats
11795 )
11796{
11797// bool bfreerfd=false, bqueued=false;
11798 u8* frame;
11799 u16 frame_len=0;
11800 struct r8192_priv *priv = ieee80211_priv(dev);
11801// u8 index = 0;
11802// u8 TID = 0;
11803 //u16 seqnum = 0;
11804 //PRX_TS_RECORD pts = NULL;
11805
11806 // Get shifted bytes of Starting address of 802.11 header. 2006.09.28, by Emily
11807 //porting by amy 080508
11808 pstats->virtual_address += get_rxpacket_shiftbytes_819xusb(pstats);
11809 frame = pstats->virtual_address;
11810 frame_len = pstats->packetlength;
11811#ifdef TODO // by amy about HCT
11812 if(!Adapter->bInHctTest)
11813 CountRxErrStatistics(Adapter, pRfd);
11814#endif
11815 {
11816 #ifdef ENABLE_PS //by amy for adding ps function in future
11817 RT_RF_POWER_STATE rtState;
11818 // When RF is off, we should not count the packet for hw/sw synchronize
11819 // reason, ie. there may be a duration while sw switch is changed and hw
11820 // switch is being changed. 2006.12.04, by shien chang.
11821 Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (u8* )(&rtState));
11822 if (rtState == eRfOff)
11823 {
11824 return;
11825 }
11826 #endif
11827 priv->stats.rxframgment++;
11828
11829 }
11830#ifdef TODO
11831 RmMonitorSignalStrength(Adapter, pRfd);
11832#endif
11833 /* 2007/01/16 MH Add RX command packet handle here. */
11834 /* 2007/03/01 MH We have to release RFD and return if rx pkt is cmd pkt. */
11835 if (rtl819xusb_rx_command_packet(dev, pstats))
11836 {
11837 return;
11838 }
11839
11840#ifdef SW_CRC_CHECK
11841 SwCrcCheck();
11842#endif
11843
11844
11845}
11846
11847void query_rx_cmdpkt_desc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats)
11848{
11849// rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11850// struct net_device *dev=info->dev;
11851// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
11852 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
11853// rx_drvinfo_819x_usb *driver_info;
11854
11855 //
11856 //Get Rx Descriptor Information
11857 //
11858 stats->virtual_address = (u8*)skb->data;
11859 stats->Length = desc->Length;
11860 stats->RxDrvInfoSize = 0;
11861 stats->RxBufShift = 0;
11862 stats->packetlength = stats->Length-scrclng;
11863 stats->fraglength = stats->packetlength;
11864 stats->fragoffset = 0;
11865 stats->ntotalfrag = 1;
11866}
11867
11868#ifdef RTL8192SU
11869void rtl8192SU_rx_cmd(struct sk_buff *skb)
11870{
11871 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11872 struct net_device *dev = info->dev;
11873
11874 /* TODO */
11875 struct ieee80211_rx_stats stats = {
11876 .signal = 0,
11877 .noise = -98,
11878 .rate = 0,
11879 // .mac_time = jiffies,
11880 .freq = IEEE80211_24GHZ_BAND,
11881 };
11882
11883 //
11884 // Check buffer length to determine if this is a valid MPDU.
11885 //
11886 if( (skb->len >= sizeof(rx_desc_819x_usb)) && (skb->len <= RX_URB_SIZE) )//&&
11887 //(pHalData->SwChnlInProgress == FALSE))
11888 {
11889 //
11890 // Collection information in Rx descriptor.
11891 //
11892#if 0
11893 pRxDesc = pContext->Buffer;
11894
11895 pRfd->Buffer.VirtualAddress = pContext->Buffer; // 061109, rcnjko, for multi-platform consideration..
11896
11897 pRtRfdStatus->Length = (u2Byte)GET_RX_DESC_PKT_LEN(pRxDesc);
11898 pRtRfdStatus->RxDrvInfoSize = 0;
11899 pRtRfdStatus->RxBufShift = 0;
11900
11901 pRfd->PacketLength = pRfd->Status.Length - sCrcLng;
11902 pRfd->FragLength = pRfd->PacketLength;
11903 pRfd->FragOffset = 0;
11904 pRfd->nTotalFrag = 1;
11905 pRfd->queue_id = PipeIndex;
11906#endif
11907 query_rx_cmdpkt_desc_status(skb,&stats);
11908 // this is to be done by amy 080508 prfd->queue_id = 1;
11909
11910 //
11911 // Process the MPDU recevied.
11912 //
11913 rtl819xusb_process_received_packet(dev,&stats);
11914
11915 dev_kfree_skb_any(skb);
11916 }
11917 else
11918 {
11919 //RTInsertTailListWithCnt(&pAdapter->RfdIdleQueue, &pRfd->List, &pAdapter->NumIdleRfd);
11920 //RT_ASSERT(pAdapter->NumIdleRfd <= pAdapter->NumRfd, ("HalUsbInCommandComplete8192SUsb(): Adapter->NumIdleRfd(%d)\n", pAdapter->NumIdleRfd));
11921 //RT_TRACE(COMP_RECV, DBG_LOUD, ("HalUsbInCommandComplete8192SUsb(): NOT enough Resources!! BufLenUsed(%d), NumIdleRfd(%d)\n",
11922 //pContext->BufLenUsed, pAdapter->NumIdleRfd));
11923 }
11924
11925 //
11926 // Reuse USB_IN_CONTEXT since we had finished processing the
11927 // buffer in USB_IN_CONTEXT.
11928 //
11929 //HalUsbReturnInContext(pAdapter, pContext);
11930
11931 //
11932 // Issue another bulk IN transfer.
11933 //
11934 //HalUsbInMpdu(pAdapter, PipeIndex);
11935
11936 RT_TRACE(COMP_RECV, "<--- HalUsbInCommandComplete8192SUsb()\n");
11937
11938}
11939#else
11940void rtl8192_rx_cmd(struct sk_buff *skb)
11941{
11942 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
11943 struct net_device *dev = info->dev;
11944 //int ret;
11945// struct urb *rx_urb = info->urb;
11946 /* TODO */
11947 struct ieee80211_rx_stats stats = {
11948 .signal = 0,
11949 .noise = -98,
11950 .rate = 0,
11951 // .mac_time = jiffies,
11952 .freq = IEEE80211_24GHZ_BAND,
11953 };
11954
11955 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE))
11956 {
11957
11958 query_rx_cmdpkt_desc_status(skb,&stats);
11959 // this is to be done by amy 080508 prfd->queue_id = 1;
11960
11961
11962 //
11963 // Process the command packet received.
11964 //
11965
11966 rtl819xusb_process_received_packet(dev,&stats);
11967
11968 dev_kfree_skb_any(skb);
11969 }
11970 else
11971 ;
11972
11973
11974#if 0
11975 desc = (u32*)(skb->data);
11976 cmd = (desc[0] >> 30) & 0x03;
11977
11978 if(cmd == 0x00) {//beacon interrupt
11979 //send beacon packet
11980 skb = ieee80211_get_beacon(priv->ieee80211);
11981
11982 if(!skb){
11983 DMESG("not enought memory for allocating beacon");
11984 return;
11985 }
11986 skb->cb[0] = BEACON_PRIORITY;
11987 skb->cb[1] = 0;
11988 skb->cb[2] = ieeerate2rtlrate(priv->ieee80211->basic_rate);
11989 ret = rtl8192_tx(dev, skb);
11990
11991 if( ret != 0 ){
11992 printk(KERN_ALERT "tx beacon packet error : %d !\n", ret);
11993 }
11994 dev_kfree_skb_any(skb);
11995 } else {//0x00
11996 //{ log the device information
11997 // At present, It is not implemented just now.
11998 //}
11999 }
12000#endif
12001}
12002#endif
12003
12004void rtl8192_irq_rx_tasklet(struct r8192_priv *priv)
12005{
12006 struct sk_buff *skb;
12007 struct rtl8192_rx_info *info;
12008
12009 while (NULL != (skb = skb_dequeue(&priv->skb_queue))) {
12010 info = (struct rtl8192_rx_info *)skb->cb;
12011 switch (info->out_pipe) {
12012 /* Nomal packet pipe */
12013 case 3:
12014 //RT_TRACE(COMP_RECV, "normal in-pipe index(%d)\n",info->out_pipe);
12015 priv->IrpPendingCount--;
12016 priv->ops->rtl819x_rx_nomal(skb);
12017 break;
12018
12019 /* Command packet pipe */
12020 case 9:
12021 RT_TRACE(COMP_RECV, "command in-pipe index(%d)\n",\
12022 info->out_pipe);
12023 priv->ops->rtl819x_rx_cmd(skb);
12024 break;
12025
12026 default: /* should never get here! */
12027 RT_TRACE(COMP_ERR, "Unknown in-pipe index(%d)\n",\
12028 info->out_pipe);
12029 dev_kfree_skb(skb);
12030 break;
12031
12032 }
12033 }
12034}
12035
12036
12037
12038/****************************************************************************
12039 ---------------------------- USB_STUFF---------------------------
12040*****************************************************************************/
12041#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12042//LZM Merge from windows HalUsbSetQueuePipeMapping8192SUsb 090319
12043static void HalUsbSetQueuePipeMapping8192SUsb(struct usb_interface *intf, struct net_device *dev)
12044{
12045 struct r8192_priv *priv = ieee80211_priv(dev);
12046 struct usb_host_interface *iface_desc;
12047 struct usb_endpoint_descriptor *endpoint;
12048 u8 i = 0;
12049
12050 priv->ep_in_num = 0;
12051 priv->ep_out_num = 0;
12052 memset(priv->RtOutPipes,0,16);
12053 memset(priv->RtInPipes,0,16);
12054
12055#ifndef USE_ONE_PIPE
12056 iface_desc = intf->cur_altsetting;
12057 priv->ep_num = iface_desc->desc.bNumEndpoints;
12058
12059 for (i = 0; i < priv->ep_num; ++i) {
12060 endpoint = &iface_desc->endpoint[i].desc;
12061#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
12062 if (usb_endpoint_is_bulk_in(endpoint)) {
12063 priv->RtInPipes[priv->ep_in_num] = usb_endpoint_num(endpoint);
12064 priv->ep_in_num ++;
12065 //printk("in_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
12066 } else if (usb_endpoint_is_bulk_out(endpoint)) {
12067 priv->RtOutPipes[priv->ep_out_num] = usb_endpoint_num(endpoint);
12068 priv->ep_out_num ++;
12069 //printk("out_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
12070 }
12071#else
12072 if ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) &&
12073 ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) {
12074 /* we found a bulk in endpoint */
12075 priv->RtInPipes[priv->ep_in_num] = (endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
12076 priv->ep_in_num ++;
12077 } else if (((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) &&
12078 ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) {
12079 /* We found bulk out endpoint */
12080 priv->RtOutPipes[priv->ep_out_num] = endpoint->bEndpointAddress;
12081 priv->ep_out_num ++;
12082 }
12083#endif
12084 }
12085 {
12086 memset(priv->txqueue_to_outpipemap,0,9);
12087 if (priv->ep_num == 6) {
12088 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
12089 u8 queuetopipe[] = {3, 2, 1, 0, 4, 4, 4, 4, 4};
12090
12091 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
12092 } else if (priv->ep_num == 4) {
12093 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
12094 u8 queuetopipe[] = {1, 1, 0, 0, 2, 2, 2, 2, 2};
12095
12096 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
12097 } else if (priv->ep_num > 9) {
12098 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
12099 u8 queuetopipe[] = {3, 2, 1, 0, 4, 8, 7, 6, 5};
12100
12101 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
12102 } else {//use sigle pipe
12103 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
12104 u8 queuetopipe[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
12105 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
12106 }
12107 }
12108 printk("==>ep_num:%d, in_ep_num:%d, out_ep_num:%d\n", priv->ep_num, priv->ep_in_num, priv->ep_out_num);
12109
12110 printk("==>RtInPipes:");
12111 for(i=0; i < priv->ep_in_num; i++)
12112 printk("%d ", priv->RtInPipes[i]);
12113 printk("\n");
12114
12115 printk("==>RtOutPipes:");
12116 for(i=0; i < priv->ep_out_num; i++)
12117 printk("%d ", priv->RtOutPipes[i]);
12118 printk("\n");
12119
12120 printk("==>txqueue_to_outpipemap for BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON:\n");
12121 for(i=0; i < 9; i++)
12122 printk("%d ", priv->txqueue_to_outpipemap[i]);
12123 printk("\n");
12124#else
12125 {
12126 memset(priv->txqueue_to_outpipemap,0,9);
12127 memset(priv->RtOutPipes,4,16);//all use endpoint 4 for out
12128 }
12129#endif
12130
12131 return;
12132}
12133#endif
12134
12135#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12136static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
12137 const struct usb_device_id *id)
12138#else
12139static void * __devinit rtl8192_usb_probe(struct usb_device *udev,
12140 unsigned int ifnum,
12141 const struct usb_device_id *id)
12142#endif
12143{
12144// unsigned long ioaddr = 0;
12145 struct net_device *dev = NULL;
12146 struct r8192_priv *priv= NULL;
12147#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12148 struct usb_device *udev = interface_to_usbdev(intf);
12149#endif
12150 RT_TRACE(COMP_INIT, "Oops: i'm coming\n");
12151
12152 dev = alloc_ieee80211(sizeof(struct r8192_priv));
12153
12154#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
12155 SET_MODULE_OWNER(dev);
12156#endif
12157
12158#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12159 usb_set_intfdata(intf, dev);
12160 SET_NETDEV_DEV(dev, &intf->dev);
12161#endif
12162 priv = ieee80211_priv(dev);
12163#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12164 priv->ieee80211 = netdev_priv(dev);
12165#else
12166 priv->ieee80211 = (struct net_device *)dev->priv;
12167#endif
12168 priv->udev=udev;
12169
12170#ifdef RTL8192SU
12171#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12172 HalUsbSetQueuePipeMapping8192SUsb(intf, dev);
12173#else//use one pipe
12174 {
12175 memset(priv->txqueue_to_outpipemap,0,9);
12176 memset(priv->RtOutPipes,4,16);//all use endpoint 4 for out
12177 }
12178#endif
12179#endif
12180
12181#ifdef RTL8192SU
12182 //printk("===============>NIC 8192SU\n");
12183 priv->ops = &rtl8192su_ops;
12184#else
12185 //printk("===============>NIC 8192U\n");
12186 priv->ops = &rtl8192u_ops;
12187#endif
12188
12189 dev->open = rtl8192_open;
12190 dev->stop = rtl8192_close;
12191 //dev->hard_start_xmit = rtl8192_8023_hard_start_xmit;
12192 dev->tx_timeout = tx_timeout;
12193 //dev->wireless_handlers = &r8192_wx_handlers_def;
12194 dev->do_ioctl = rtl8192_ioctl;
12195 dev->set_multicast_list = r8192_set_multicast;
12196 dev->set_mac_address = r8192_set_mac_adr;
12197 dev->get_stats = rtl8192_stats;
12198
12199 //DMESG("Oops: i'm coming\n");
12200#if WIRELESS_EXT >= 12
12201#if WIRELESS_EXT < 17
12202 dev->get_wireless_stats = r8192_get_wireless_stats;
12203#endif
12204 dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def;
12205#endif
12206 dev->type=ARPHRD_ETHER;
12207
12208 dev->watchdog_timeo = HZ*3; //modified by john, 0805
12209
12210 if (dev_alloc_name(dev, ifname) < 0){
12211 RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
12212 ifname = "wlan%d";
12213 dev_alloc_name(dev, ifname);
12214 }
12215
12216 RT_TRACE(COMP_INIT, "Driver probe completed1\n");
12217#if 1
12218 if(rtl8192_init(dev)!=0){
12219 RT_TRACE(COMP_ERR, "Initialization failed");
12220 goto fail;
12221 }
12222#endif
12223 netif_carrier_off(dev);
12224 netif_stop_queue(dev);
12225
12226 register_netdev(dev);
12227 RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
12228 rtl8192_proc_init_one(dev);
12229
12230
12231 RT_TRACE(COMP_INIT, "Driver probe completed\n");
12232#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
12233 return dev;
12234#else
12235 return 0;
12236#endif
12237
12238
12239fail:
12240 free_ieee80211(dev);
12241
12242 RT_TRACE(COMP_ERR, "wlan driver load failed\n");
12243#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
12244 return NULL;
12245#else
12246 return -ENODEV;
12247#endif
12248
12249}
12250
12251//detach all the work and timer structure declared or inititialize in r8192U_init function.
12252void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
12253{
12254#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
12255 cancel_work_sync(&priv->reset_wq);
12256 cancel_work_sync(&priv->qos_activate);
12257 cancel_delayed_work(&priv->watch_dog_wq);
12258 cancel_delayed_work(&priv->update_beacon_wq);
12259 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
12260 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
12261 //cancel_work_sync(&priv->SetBWModeWorkItem);
12262 //cancel_work_sync(&priv->SwChnlWorkItem);
12263#else
12264#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12265 cancel_delayed_work(&priv->reset_wq);
12266 cancel_delayed_work(&priv->qos_activate);
12267 cancel_delayed_work(&priv->watch_dog_wq);
12268 cancel_delayed_work(&priv->update_beacon_wq);
12269 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
12270 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
12271
12272 //cancel_delayed_work(&priv->SetBWModeWorkItem);
12273 //cancel_delayed_work(&priv->SwChnlWorkItem);
12274#endif
12275#endif
12276
12277}
12278
12279
12280#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12281static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf)
12282#else
12283static void __devexit rtl8192_usb_disconnect(struct usb_device *udev, void *ptr)
12284#endif
12285{
12286#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
12287 struct net_device *dev = usb_get_intfdata(intf);
12288#else
12289 struct net_device *dev = (struct net_device *)ptr;
12290#endif
12291
12292 struct r8192_priv *priv = ieee80211_priv(dev);
12293 if(dev){
12294
12295 unregister_netdev(dev);
12296
12297 RT_TRACE(COMP_DOWN, "=============>wlan driver to be removed\n");
12298 rtl8192_proc_remove_one(dev);
12299
12300 rtl8192_down(dev);
12301 if (priv->pFirmware)
12302 {
12303 vfree(priv->pFirmware);
12304 priv->pFirmware = NULL;
12305 }
12306 // priv->rf_close(dev);
12307// rtl8192_SetRFPowerState(dev, eRfOff);
12308#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
12309 destroy_workqueue(priv->priv_wq);
12310#endif
12311 //rtl8192_irq_disable(dev);
12312 //rtl8192_reset(dev);
12313 mdelay(10);
12314
12315 }
12316 free_ieee80211(dev);
12317 RT_TRACE(COMP_DOWN, "wlan driver removed\n");
12318}
12319
12320static int __init rtl8192_usb_module_init(void)
12321{
12322 printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
12323 printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
12324 RT_TRACE(COMP_INIT, "Initializing module");
12325 RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT);
12326 rtl8192_proc_module_init();
12327 return usb_register(&rtl8192_usb_driver);
12328}
12329
12330
12331static void __exit rtl8192_usb_module_exit(void)
12332{
12333 usb_deregister(&rtl8192_usb_driver);
12334
12335 RT_TRACE(COMP_DOWN, "Exiting");
12336 rtl8192_proc_module_remove();
12337}
12338
12339
12340void rtl8192_try_wake_queue(struct net_device *dev, int pri)
12341{
12342 unsigned long flags;
12343 short enough_desc;
12344 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
12345
12346 spin_lock_irqsave(&priv->tx_lock,flags);
12347 enough_desc = check_nic_enough_desc(dev,pri);
12348 spin_unlock_irqrestore(&priv->tx_lock,flags);
12349
12350 if(enough_desc)
12351 ieee80211_wake_queue(priv->ieee80211);
12352}
12353
12354#if 0
12355void DisableHWSecurityConfig8192SUsb(struct net_device *dev)
12356{
12357 u8 SECR_value = 0x0;
12358 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
12359}
12360#endif
12361
12362void EnableHWSecurityConfig8192(struct net_device *dev)
12363{
12364 u8 SECR_value = 0x0;
12365 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
12366 struct ieee80211_device* ieee = priv->ieee80211;
12367
12368 SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
12369#if 1
12370 if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
12371 {
12372 SECR_value |= SCR_RxUseDK;
12373 SECR_value |= SCR_TxUseDK;
12374 }
12375 else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))
12376 {
12377 SECR_value |= SCR_RxUseDK;
12378 SECR_value |= SCR_TxUseDK;
12379 }
12380#endif
12381 //add HWSec active enable here.
12382//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
12383
12384 ieee->hwsec_active = 1;
12385
12386 if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off
12387 {
12388 ieee->hwsec_active = 0;
12389 SECR_value &= ~SCR_RxDecEnable;
12390 }
12391
12392 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \
12393 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
12394 {
12395 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
12396 }
12397}
12398
12399
12400void setKey( struct net_device *dev,
12401 u8 EntryNo,
12402 u8 KeyIndex,
12403 u16 KeyType,
12404 u8 *MacAddr,
12405 u8 DefaultKey,
12406 u32 *KeyContent )
12407{
12408 u32 TargetCommand = 0;
12409 u32 TargetContent = 0;
12410 u16 usConfig = 0;
12411 u8 i;
12412 if (EntryNo >= TOTAL_CAM_ENTRY)
12413 RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
12414
12415 RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr));
12416
12417 if (DefaultKey)
12418 usConfig |= BIT15 | (KeyType<<2);
12419 else
12420 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
12421// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex;
12422
12423
12424 for(i=0 ; i<CAM_CONTENT_COUNT; i++){
12425 TargetCommand = i+CAM_CONTENT_COUNT*EntryNo;
12426 TargetCommand |= BIT31|BIT16;
12427
12428 if(i==0){//MAC|Config
12429 TargetContent = (u32)(*(MacAddr+0)) << 16|
12430 (u32)(*(MacAddr+1)) << 24|
12431 (u32)usConfig;
12432
12433 write_nic_dword(dev, WCAMI, TargetContent);
12434 write_nic_dword(dev, RWCAM, TargetCommand);
12435 // printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo));
12436 }
12437 else if(i==1){//MAC
12438 TargetContent = (u32)(*(MacAddr+2)) |
12439 (u32)(*(MacAddr+3)) << 8|
12440 (u32)(*(MacAddr+4)) << 16|
12441 (u32)(*(MacAddr+5)) << 24;
12442 write_nic_dword(dev, WCAMI, TargetContent);
12443 write_nic_dword(dev, RWCAM, TargetCommand);
12444 }
12445 else {
12446 //Key Material
12447 if(KeyContent !=NULL){
12448 write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
12449 write_nic_dword(dev, RWCAM, TargetCommand);
12450 }
12451 }
12452 }
12453
12454}
12455
12456/***************************************************************************
12457 ------------------- module init / exit stubs ----------------
12458****************************************************************************/
12459module_init(rtl8192_usb_module_init);
12460module_exit(rtl8192_usb_module_exit);
diff --git a/drivers/staging/rtl8192su/r8192U_dm.c b/drivers/staging/rtl8192su/r8192U_dm.c
new file mode 100644
index 00000000000..304274b886e
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_dm.c
@@ -0,0 +1,4521 @@
1/*++
2Copyright-c Realtek Semiconductor Corp. All rights reserved.
3
4Module Name:
5 r8192U_dm.c
6
7Abstract:
8 HW dynamic mechanism.
9
10Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
14
15--*/
16
17
18#ifdef RTL8192SU
19#include "r8192U.h"
20#include "r8192U_dm.h"
21//#include "r8190_rtl8256.h"
22#include "r819xU_cmdpkt.h"
23#include "r8192S_hw.h"
24#include "r8192S_phy.h"
25#include "r8192S_phyreg.h"
26#else
27#include "r8192U.h"
28#include "r8192U_dm.h"
29#include "r8192U_hw.h"
30#include "r819xU_phy.h"
31#include "r819xU_phyreg.h"
32#include "r8190_rtl8256.h"
33#include "r819xU_cmdpkt.h"
34#endif
35
36/*---------------------------Define Local Constant---------------------------*/
37//
38// Indicate different AP vendor for IOT issue.
39//
40#if 0
41typedef enum _HT_IOT_PEER
42{
43 HT_IOT_PEER_UNKNOWN = 0,
44 HT_IOT_PEER_REALTEK = 1,
45 HT_IOT_PEER_BROADCOM = 2,
46 HT_IOT_PEER_RALINK = 3,
47 HT_IOT_PEER_ATHEROS = 4,
48 HT_IOT_PEER_CISCO = 5,
49 HT_IOT_PEER_MAX = 6
50}HT_IOT_PEER_E, *PHTIOT_PEER_E;
51#endif
52#if 1
53#ifdef RTL8192SU
54 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
55 // UNKNOWN REALTEK_90 /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
56 { 0xa44f, 0x5ea44f, 0x5ea44f, 0xa44f, 0xa44f, 0xa44f, 0xa630, 0xa42b, 0x5e4322, 0x5e4322};
57 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
58 // UNKNOWN REALTEK /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
59 { 0x5ea44f, 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea422, 0x5e4322, 0x3ea44f, 0x5ea42b, 0x5e4322, 0x5e4322};
60
61#else
62
63static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
64 { 0x5e4322, 0x5e4322, 0x5ea44f, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
65static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
66 { 0x5e4322, 0xa44f, 0x5ea44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
67
68#endif
69#endif
70
71#define RTK_UL_EDCA 0xa44f
72#define RTK_DL_EDCA 0x5e4322
73/*---------------------------Define Local Constant---------------------------*/
74
75
76/*------------------------Define global variable-----------------------------*/
77// Debug variable ?
78dig_t dm_digtable;
79// Store current shoftware write register content for MAC PHY.
80u8 dm_shadow[16][256] = {{0}};
81// For Dynamic Rx Path Selection by Signal Strength
82DRxPathSel DM_RxPathSelTable;
83/*------------------------Define global variable-----------------------------*/
84
85
86/*------------------------Define local variable------------------------------*/
87/*------------------------Define local variable------------------------------*/
88
89
90/*--------------------Define export function prototype-----------------------*/
91#ifdef TO_DO_LIST
92static void dm_CheckProtection(struct net_device *dev);
93#endif
94extern void init_hal_dm(struct net_device *dev);
95extern void deinit_hal_dm(struct net_device *dev);
96
97extern void hal_dm_watchdog(struct net_device *dev);
98
99
100extern void init_rate_adaptive(struct net_device *dev);
101#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
102extern void dm_txpower_trackingcallback(struct work_struct *work);
103#else
104extern void dm_txpower_trackingcallback(struct net_device *dev);
105#endif
106
107extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
108extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
109extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
110extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
111 u32 dm_type,
112 u32 dm_value);
113extern void DM_ChangeFsyncSetting(struct net_device *dev,
114 s32 DM_Type,
115 s32 DM_Value);
116extern void dm_force_tx_fw_info(struct net_device *dev,
117 u32 force_type,
118 u32 force_value);
119extern void dm_init_edca_turbo(struct net_device *dev);
120extern void dm_rf_operation_test_callback(unsigned long data);
121#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
122extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
123#else
124extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev);
125#endif
126extern void dm_fsync_timer_callback(unsigned long data);
127#if 0
128extern bool dm_check_lbus_status(struct net_device *dev);
129#endif
130extern void dm_check_fsync(struct net_device *dev);
131extern void dm_shadow_init(struct net_device *dev);
132
133
134/*--------------------Define export function prototype-----------------------*/
135
136
137/*---------------------Define local function prototype-----------------------*/
138// DM --> Rate Adaptive
139static void dm_check_rate_adaptive(struct net_device *dev);
140
141// DM --> Bandwidth switch
142static void dm_init_bandwidth_autoswitch(struct net_device *dev);
143static void dm_bandwidth_autoswitch( struct net_device *dev);
144
145// DM --> TX power control
146//static void dm_initialize_txpower_tracking(struct net_device *dev);
147
148static void dm_check_txpower_tracking(struct net_device *dev);
149
150
151
152//static void dm_txpower_reset_recovery(struct net_device *dev);
153
154
155// DM --> BB init gain restore
156#ifndef RTL8192U
157static void dm_bb_initialgain_restore(struct net_device *dev);
158
159
160// DM --> BB init gain backup
161static void dm_bb_initialgain_backup(struct net_device *dev);
162#endif
163// DM --> Dynamic Init Gain by RSSI
164static void dm_dig_init(struct net_device *dev);
165static void dm_ctrl_initgain_byrssi(struct net_device *dev);
166static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
167static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev);
168static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
169static void dm_initial_gain(struct net_device *dev);
170static void dm_pd_th(struct net_device *dev);
171static void dm_cs_ratio(struct net_device *dev);
172
173static void dm_init_ctstoself(struct net_device *dev);
174// DM --> EDCA turboe mode control
175static void dm_check_edca_turbo(struct net_device *dev);
176
177// DM --> HW RF control
178static void dm_check_rfctrl_gpio(struct net_device *dev);
179
180#ifndef RTL8190P
181//static void dm_gpio_change_rf(struct net_device *dev);
182#endif
183// DM --> Check PBC
184static void dm_check_pbc_gpio(struct net_device *dev);
185
186
187// DM --> Check current RX RF path state
188static void dm_check_rx_path_selection(struct net_device *dev);
189static void dm_init_rxpath_selection(struct net_device *dev);
190static void dm_rxpath_sel_byrssi(struct net_device *dev);
191
192
193// DM --> Fsync for broadcom ap
194static void dm_init_fsync(struct net_device *dev);
195static void dm_deInit_fsync(struct net_device *dev);
196
197//Added by vivi, 20080522
198static void dm_check_txrateandretrycount(struct net_device *dev);
199
200/*---------------------Define local function prototype-----------------------*/
201
202/*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
203static void dm_init_dynamic_txpower(struct net_device *dev);
204static void dm_dynamic_txpower(struct net_device *dev);
205
206
207// DM --> For rate adaptive and DIG, we must send RSSI to firmware
208static void dm_send_rssi_tofw(struct net_device *dev);
209static void dm_ctstoself(struct net_device *dev);
210/*---------------------------Define function prototype------------------------*/
211//================================================================================
212// HW Dynamic mechanism interface.
213//================================================================================
214#ifdef RTL8192SU
215static void dm_CheckAggrPolicy(struct net_device *dev)
216{
217 struct r8192_priv *priv = ieee80211_priv(dev);
218 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
219 //u8 QueueId;
220 //PRT_TCB pTcb;
221 bool bAmsduEnable = false;
222
223 static u8 lastTxOkCnt = 0;
224 static u8 lastRxOkCnt = 0;
225 u8 curTxOkCnt = 0;
226 u8 curRxOkCnt = 0;
227
228 // Determine if A-MSDU policy.
229 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_HYBRID_AGGREGATION)
230 {
231 if(read_nic_byte(dev, INIMCS_SEL) > DESC92S_RATE54M)
232 bAmsduEnable = true;
233 }
234 else if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE)
235 {
236 if(read_nic_byte(dev, INIMCS_SEL) > DESC92S_RATE54M)
237 {
238 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
239 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
240
241 if(curRxOkCnt <= 4*curTxOkCnt)
242 bAmsduEnable = true;
243 }
244 }
245 else
246 {
247 // Do not need to switch aggregation policy.
248 return;
249 }
250
251 // Switch A-MSDU
252 if(bAmsduEnable && !pHTInfo->bCurrent_AMSDU_Support)
253 {
254 pHTInfo->bCurrent_AMSDU_Support = true;
255 }
256 else if(!bAmsduEnable && pHTInfo->bCurrent_AMSDU_Support)
257 {
258#ifdef TO_DO_LIST
259 //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
260 for(QueueId = 0; QueueId < MAX_TX_QUEUE; QueueId++)
261 {
262 while(!RTIsListEmpty(&dev->TcbAggrQueue[QueueId]))
263 {
264 pTcb = (PRT_TCB)RTRemoveHeadList(&dev->TcbAggrQueue[QueueId]);
265 dev->TcbCountInAggrQueue[QueueId]--;
266 PreTransmitTCB(dev, pTcb);
267 }
268 }
269 //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
270 pHTInfo->bCurrent_AMSDU_Support = false;
271#endif
272 }
273
274 // Determine A-MPDU policy
275 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE)
276 {
277 if(!bAmsduEnable)
278 pHTInfo->bCurrentAMPDUEnable = true;
279 }
280
281 // Update local static variables.
282 lastTxOkCnt = priv->stats.txbytesunicast;
283 lastRxOkCnt = priv->stats.rxbytesunicast;
284}
285#endif
286//
287// Description:
288// Prepare SW resource for HW dynamic mechanism.
289//
290// Assumption:
291// This function is only invoked at driver intialization once.
292//
293//
294extern void
295init_hal_dm(struct net_device *dev)
296{
297 struct r8192_priv *priv = ieee80211_priv(dev);
298
299 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
300 priv->undecorated_smoothed_pwdb = -1;
301
302 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
303 dm_init_dynamic_txpower(dev);
304 init_rate_adaptive(dev);
305#ifdef RTL8192SU
306 dm_initialize_txpower_tracking(dev);
307#else
308 //dm_initialize_txpower_tracking(dev);
309#endif
310 dm_dig_init(dev);
311 dm_init_edca_turbo(dev);
312 dm_init_bandwidth_autoswitch(dev);
313 dm_init_fsync(dev);
314 dm_init_rxpath_selection(dev);
315 dm_init_ctstoself(dev);
316
317} // InitHalDm
318
319extern void deinit_hal_dm(struct net_device *dev)
320{
321
322 dm_deInit_fsync(dev);
323
324}
325
326
327#ifdef USB_RX_AGGREGATION_SUPPORT
328void dm_CheckRxAggregation(struct net_device *dev) {
329 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
330 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
331 static unsigned long lastTxOkCnt = 0;
332 static unsigned long lastRxOkCnt = 0;
333 unsigned long curTxOkCnt = 0;
334 unsigned long curRxOkCnt = 0;
335
336/*
337 if (pHalData->bForcedUsbRxAggr) {
338 if (pHalData->ForcedUsbRxAggrInfo == 0) {
339 if (pHalData->bCurrentRxAggrEnable) {
340 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
341 }
342 } else {
343 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
344 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
345 }
346 }
347 return;
348 }
349
350*/
351#ifdef RTL8192SU
352 if (priv->bForcedUsbRxAggr) {
353 if (priv->ForcedUsbRxAggrInfo == 0) {
354 if (priv->bCurrentRxAggrEnable) {
355 //Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
356 write_nic_dword(dev, 0x1a8, 0);
357 priv->bCurrentRxAggrEnable = false;
358 }
359 } else {
360 if (!priv->bCurrentRxAggrEnable || (priv->ForcedUsbRxAggrInfo != priv->LastUsbRxAggrInfoSetting)) {
361 u32 ulValue;
362 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
363 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
364 /*
365 * If usb rx firmware aggregation is enabled,
366 * when anyone of three threshold conditions above is reached,
367 * firmware will send aggregated packet to driver.
368 */
369 write_nic_dword(dev, 0x1a8, ulValue);
370 priv->bCurrentRxAggrEnable = true;
371 }
372 }
373 return;
374 }
375
376 if((priv->ieee80211->mode & WIRELESS_MODE_B) || (priv->ieee80211->mode & WIRELESS_MODE_G))
377 {
378 if (priv->bCurrentRxAggrEnable)
379 {
380 RT_TRACE(COMP_RECV, "dm_CheckRxAggregation() : Disable Rx Aggregation!!\n");
381 write_nic_dword(dev, 0x1a8, 0);
382 priv->bCurrentRxAggrEnable = false;
383 return;
384 }
385 }
386#endif
387
388 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
389 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
390
391 if((curTxOkCnt + curRxOkCnt) < 15000000) {
392 return;
393 }
394
395 if(curTxOkCnt > 4*curRxOkCnt) {
396 if (priv->bCurrentRxAggrEnable) {
397 write_nic_dword(dev, 0x1a8, 0);
398 priv->bCurrentRxAggrEnable = false;
399 }
400 }else{
401 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
402 u32 ulValue;
403 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
404 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
405 /*
406 * If usb rx firmware aggregation is enabled,
407 * when anyone of three threshold conditions above is reached,
408 * firmware will send aggregated packet to driver.
409 */
410 write_nic_dword(dev, 0x1a8, ulValue);
411 priv->bCurrentRxAggrEnable = true;
412 }
413 }
414
415 lastTxOkCnt = priv->stats.txbytesunicast;
416 lastRxOkCnt = priv->stats.rxbytesunicast;
417} // dm_CheckEdcaTurbo
418#endif
419
420
421#ifdef RTL8192SU
422//#if 0
423extern void hal_dm_watchdog(struct net_device *dev)
424{
425 struct r8192_priv *priv = ieee80211_priv(dev);
426
427 if(priv->bInHctTest)
428 return;
429
430
431 dm_check_rfctrl_gpio(dev);
432
433 // Add by hpfan 2008-03-11
434 dm_check_pbc_gpio(dev);
435 dm_check_txrateandretrycount(dev); //moved by tynli
436 dm_check_edca_turbo(dev);
437
438 dm_CheckAggrPolicy(dev);
439
440#ifdef TO_DO_LIST
441 dm_CheckProtection(dev);
442#endif
443
444 // ====================================================
445 // If any dynamic mechanism is ready, put it above this return;
446 // ====================================================
447 //if (IS_HARDWARE_TYPE_8192S(dev))
448 return;
449
450#ifdef USB_RX_AGGREGATION_SUPPORT
451 dm_CheckRxAggregation(dev);
452#endif
453#ifdef TO_DO_LIST
454 if(Adapter->MgntInfo.mActingAsAp)
455 {
456 AP_dm_CheckRateAdaptive(dev);
457 //return;
458 }
459 else
460#endif
461 {
462 dm_check_rate_adaptive(dev);
463 }
464 dm_dynamic_txpower(dev);
465
466 dm_check_txpower_tracking(dev);
467 dm_ctrl_initgain_byrssi(dev);//LZM TMP 090302
468
469 dm_bandwidth_autoswitch(dev);
470
471 dm_check_rx_path_selection(dev);//LZM TMP 090302
472 dm_check_fsync(dev);
473
474 dm_send_rssi_tofw(dev);
475
476 dm_ctstoself(dev);
477
478} //HalDmWatchDog
479#else
480extern void hal_dm_watchdog(struct net_device *dev)
481{
482 //struct r8192_priv *priv = ieee80211_priv(dev);
483
484 //static u8 previous_bssid[6] ={0};
485
486 /*Add by amy 2008/05/15 ,porting from windows code.*/
487 dm_check_rate_adaptive(dev);
488 dm_dynamic_txpower(dev);
489 dm_check_txrateandretrycount(dev);
490 dm_check_txpower_tracking(dev);
491 dm_ctrl_initgain_byrssi(dev);
492 dm_check_edca_turbo(dev);
493 dm_bandwidth_autoswitch(dev);
494 dm_check_rfctrl_gpio(dev);
495 dm_check_rx_path_selection(dev);
496 dm_check_fsync(dev);
497
498 // Add by amy 2008-05-15 porting from windows code.
499 dm_check_pbc_gpio(dev);
500 dm_send_rssi_tofw(dev);
501 dm_ctstoself(dev);
502#ifdef USB_RX_AGGREGATION_SUPPORT
503 dm_CheckRxAggregation(dev);
504#endif
505} //HalDmWatchDog
506#endif
507
508/*
509 * Decide Rate Adaptive Set according to distance (signal strength)
510 * 01/11/2008 MHC Modify input arguments and RATR table level.
511 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
512 * the function after making sure RF_Type.
513 */
514extern void init_rate_adaptive(struct net_device * dev)
515{
516
517 struct r8192_priv *priv = ieee80211_priv(dev);
518 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
519
520 pra->ratr_state = DM_RATR_STA_MAX;
521 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
522 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
523 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
524
525 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
526 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
527 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
528
529 if(priv->CustomerID == RT_CID_819x_Netcore)
530 pra->ping_rssi_enable = 1;
531 else
532 pra->ping_rssi_enable = 0;
533 pra->ping_rssi_thresh_for_ra = 15;
534
535
536 if (priv->rf_type == RF_2T4R)
537 {
538 // 07/10/08 MH Modify for RA smooth scheme.
539 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
540 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
541 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
542 pra->low_rssi_threshold_ratr = 0x8f0ff001;
543 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
544 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
545 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
546 }
547 else if (priv->rf_type == RF_1T2R)
548 {
549 pra->upper_rssi_threshold_ratr = 0x000f0000;
550 pra->middle_rssi_threshold_ratr = 0x000ff000;
551 pra->low_rssi_threshold_ratr = 0x000ff001;
552 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
553 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
554 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
555 }
556
557} // InitRateAdaptive
558
559
560/*-----------------------------------------------------------------------------
561 * Function: dm_check_rate_adaptive()
562 *
563 * Overview:
564 *
565 * Input: NONE
566 *
567 * Output: NONE
568 *
569 * Return: NONE
570 *
571 * Revised History:
572 * When Who Remark
573 * 05/26/08 amy Create version 0 proting from windows code.
574 *
575 *---------------------------------------------------------------------------*/
576static void dm_check_rate_adaptive(struct net_device * dev)
577{
578 struct r8192_priv *priv = ieee80211_priv(dev);
579 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
580 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
581 u32 currentRATR, targetRATR = 0;
582 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
583 bool bshort_gi_enabled = false;
584 static u8 ping_rssi_state=0;
585
586
587 if(!priv->up)
588 {
589 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
590 return;
591 }
592
593 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
594 return;
595
596 // TODO: Only 11n mode is implemented currently,
597 if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
598 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
599 return;
600
601 if( priv->ieee80211->state == IEEE80211_LINKED )
602 {
603 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
604
605 //
606 // Check whether Short GI is enabled
607 //
608 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
609 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
610
611
612 pra->upper_rssi_threshold_ratr =
613 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
614
615 pra->middle_rssi_threshold_ratr =
616 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
617
618 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
619 {
620 pra->low_rssi_threshold_ratr =
621 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
622 }
623 else
624 {
625 pra->low_rssi_threshold_ratr =
626 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
627 }
628 //cosa add for test
629 pra->ping_rssi_ratr =
630 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
631
632 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
633 time to link with AP. We will not change upper/lower threshold. If
634 STA stay in high or low level, we must change two different threshold
635 to prevent jumping frequently. */
636 if (pra->ratr_state == DM_RATR_STA_HIGH)
637 {
638 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
639 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
640 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
641 }
642 else if (pra->ratr_state == DM_RATR_STA_LOW)
643 {
644 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
645 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
646 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
647 }
648 else
649 {
650 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
651 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
652 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
653 }
654
655 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
656 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
657 {
658 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
659 pra->ratr_state = DM_RATR_STA_HIGH;
660 targetRATR = pra->upper_rssi_threshold_ratr;
661 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
662 {
663 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
664 pra->ratr_state = DM_RATR_STA_MIDDLE;
665 targetRATR = pra->middle_rssi_threshold_ratr;
666 }else
667 {
668 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
669 pra->ratr_state = DM_RATR_STA_LOW;
670 targetRATR = pra->low_rssi_threshold_ratr;
671 }
672
673 //cosa add for test
674 if(pra->ping_rssi_enable)
675 {
676 //pHalData->UndecoratedSmoothedPWDB = 19;
677 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
678 {
679 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
680 ping_rssi_state )
681 {
682 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
683 pra->ratr_state = DM_RATR_STA_LOW;
684 targetRATR = pra->ping_rssi_ratr;
685 ping_rssi_state = 1;
686 }
687 //else
688 // DbgPrint("TestRSSI is between the range. \n");
689 }
690 else
691 {
692 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
693 ping_rssi_state = 0;
694 }
695 }
696
697 // 2008.04.01
698#if 1
699 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
700 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
701 targetRATR &= 0xf00fffff;
702#endif
703
704 //
705 // Check whether updating of RATR0 is required
706 //
707 currentRATR = read_nic_dword(dev, RATR0);
708 if( targetRATR != currentRATR )
709 {
710 u32 ratr_value;
711 ratr_value = targetRATR;
712 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
713 if(priv->rf_type == RF_1T2R)
714 {
715 ratr_value &= ~(RATE_ALL_OFDM_2SS);
716 }
717 write_nic_dword(dev, RATR0, ratr_value);
718 write_nic_byte(dev, UFWP, 1);
719
720 pra->last_ratr = targetRATR;
721 }
722
723 }
724 else
725 {
726 pra->ratr_state = DM_RATR_STA_MAX;
727 }
728
729} // dm_CheckRateAdaptive
730
731
732static void dm_init_bandwidth_autoswitch(struct net_device * dev)
733{
734 struct r8192_priv *priv = ieee80211_priv(dev);
735
736 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
737 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
738 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
739 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
740
741} // dm_init_bandwidth_autoswitch
742
743
744static void dm_bandwidth_autoswitch(struct net_device * dev)
745{
746 struct r8192_priv *priv = ieee80211_priv(dev);
747
748 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
749 return;
750 }else{
751 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
752 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
753 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
754 }else{//in force send packets in 20 Mhz in 20/40
755 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
756 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
757
758 }
759 }
760} // dm_BandwidthAutoSwitch
761
762//OFDM default at 0db, index=6.
763static u32 OFDMSwingTable[OFDM_Table_Length] = {
764 0x7f8001fe, // 0, +6db
765 0x71c001c7, // 1, +5db
766 0x65400195, // 2, +4db
767 0x5a400169, // 3, +3db
768 0x50800142, // 4, +2db
769 0x47c0011f, // 5, +1db
770 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature
771 0x390000e4, // 7, -1db
772 0x32c000cb, // 8, -2db
773 0x2d4000b5, // 9, -3db
774 0x288000a2, // 10, -4db
775 0x24000090, // 11, -5db
776 0x20000080, // 12, -6db
777 0x1c800072, // 13, -7db
778 0x19800066, // 14, -8db
779 0x26c0005b, // 15, -9db
780 0x24400051, // 16, -10db
781 0x12000048, // 17, -11db
782 0x10000040 // 18, -12db
783};
784
785static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
786 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
787 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
788 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
789 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
790 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
791 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
792 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
793 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
794 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
795 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
796 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
797 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
798};
799
800static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
801 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
802 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
803 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
804 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
805 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
806 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
807 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
808 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
809 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
810 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
811 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
812 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
813};
814
815static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
816{
817 struct r8192_priv *priv = ieee80211_priv(dev);
818 bool bHighpowerstate, viviflag = FALSE;
819 DCMD_TXCMD_T tx_cmd;
820 u8 powerlevelOFDM24G;
821 int i =0, j = 0, k = 0;
822 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
823 u32 Value;
824 u8 Pwr_Flag;
825 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
826 //RT_STATUS rtStatus = RT_STATUS_SUCCESS;
827#ifdef RTL8192U
828 bool rtStatus = true;
829#endif
830 u32 delta=0;
831
832 write_nic_byte(dev, 0x1ba, 0);
833
834 priv->ieee80211->bdynamic_txpower_enable = false;
835 bHighpowerstate = priv->bDynamicTxHighPower;
836
837 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
838 RF_Type = priv->rf_type;
839 Value = (RF_Type<<8) | powerlevelOFDM24G;
840
841 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
842
843 for(j = 0; j<=30; j++)
844{ //fill tx_cmd
845
846 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
847 tx_cmd.Length = 4;
848 tx_cmd.Value = Value;
849#ifdef RTL8192U
850 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
851 if (rtStatus == false)
852 {
853 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
854 }
855#else
856 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
857 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
858#endif
859 mdelay(1);
860 //DbgPrint("hi, vivi, strange\n");
861 for(i = 0;i <= 30; i++)
862 {
863 Pwr_Flag = read_nic_byte(dev, 0x1ba);
864
865 if (Pwr_Flag == 0)
866 {
867 mdelay(1);
868 continue;
869 }
870#ifdef RTL8190P
871 Avg_TSSI_Meas = read_nic_word(dev, 0x1bc);
872#else
873 Avg_TSSI_Meas = read_nic_word(dev, 0x13c);
874#endif
875 if(Avg_TSSI_Meas == 0)
876 {
877 write_nic_byte(dev, 0x1ba, 0);
878 break;
879 }
880
881 for(k = 0;k < 5; k++)
882 {
883#ifdef RTL8190P
884 tmp_report[k] = read_nic_byte(dev, 0x1d8+k);
885#else
886 if(k !=4)
887 tmp_report[k] = read_nic_byte(dev, 0x134+k);
888 else
889 tmp_report[k] = read_nic_byte(dev, 0x13e);
890#endif
891 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
892 }
893
894 //check if the report value is right
895 for(k = 0;k < 5; k++)
896 {
897 if(tmp_report[k] <= 20)
898 {
899 viviflag =TRUE;
900 break;
901 }
902 }
903 if(viviflag ==TRUE)
904 {
905 write_nic_byte(dev, 0x1ba, 0);
906 viviflag = FALSE;
907 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
908 for(k = 0;k < 5; k++)
909 tmp_report[k] = 0;
910 break;
911 }
912
913 for(k = 0;k < 5; k++)
914 {
915 Avg_TSSI_Meas_from_driver += tmp_report[k];
916 }
917
918 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
919 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
920 TSSI_13dBm = priv->TSSI_13dBm;
921 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
922
923 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
924 // For MacOS-compatible
925 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
926 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
927 else
928 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
929
930 if(delta <= E_FOR_TX_POWER_TRACK)
931 {
932 priv->ieee80211->bdynamic_txpower_enable = TRUE;
933 write_nic_byte(dev, 0x1ba, 0);
934 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
935 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
936 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
937#ifdef RTL8190P
938 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
939 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
940#endif
941 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
942 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
943 return;
944 }
945 else
946 {
947 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
948 {
949 if((priv->rfa_txpowertrackingindex > 0)
950#ifdef RTL8190P
951 &&(priv->rfc_txpowertrackingindex > 0)
952#endif
953 )
954 {
955 priv->rfa_txpowertrackingindex--;
956 if(priv->rfa_txpowertrackingindex_real > 4)
957 {
958 priv->rfa_txpowertrackingindex_real--;
959 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
960 }
961#ifdef RTL8190P
962 priv->rfc_txpowertrackingindex--;
963 if(priv->rfc_txpowertrackingindex_real > 4)
964 {
965 priv->rfc_txpowertrackingindex_real--;
966 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
967 }
968#endif
969 }
970 }
971 else
972 {
973 if((priv->rfa_txpowertrackingindex < 36)
974#ifdef RTL8190P
975 &&(priv->rfc_txpowertrackingindex < 36)
976#endif
977 )
978 {
979 priv->rfa_txpowertrackingindex++;
980 priv->rfa_txpowertrackingindex_real++;
981 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
982
983#ifdef RTL8190P
984 priv->rfc_txpowertrackingindex++;
985 priv->rfc_txpowertrackingindex_real++;
986 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
987#endif
988 }
989 }
990 priv->cck_present_attentuation_difference
991 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
992
993 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
994 priv->cck_present_attentuation
995 = priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
996 else
997 priv->cck_present_attentuation
998 = priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
999
1000 if(priv->cck_present_attentuation > -1&&priv->cck_present_attentuation <23)
1001 {
1002 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1003 {
1004 priv->bcck_in_ch14 = TRUE;
1005 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1006 }
1007 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1008 {
1009 priv->bcck_in_ch14 = FALSE;
1010 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1011 }
1012 else
1013 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1014 }
1015 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
1016 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
1017#ifdef RTL8190P
1018 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
1019 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
1020#endif
1021 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
1022 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
1023
1024 if (priv->cck_present_attentuation_difference <= -12||priv->cck_present_attentuation_difference >= 24)
1025 {
1026 priv->ieee80211->bdynamic_txpower_enable = TRUE;
1027 write_nic_byte(dev, 0x1ba, 0);
1028 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
1029 return;
1030 }
1031
1032
1033 }
1034 write_nic_byte(dev, 0x1ba, 0);
1035 Avg_TSSI_Meas_from_driver = 0;
1036 for(k = 0;k < 5; k++)
1037 tmp_report[k] = 0;
1038 break;
1039 }
1040}
1041 priv->ieee80211->bdynamic_txpower_enable = TRUE;
1042 write_nic_byte(dev, 0x1ba, 0);
1043}
1044
1045static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
1046{
1047#define ThermalMeterVal 9
1048 struct r8192_priv *priv = ieee80211_priv(dev);
1049 u32 tmpRegA, TempCCk;
1050 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
1051 int i =0, CCKSwingNeedUpdate=0;
1052
1053 if(!priv->btxpower_trackingInit)
1054 {
1055 //Query OFDM default setting
1056 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
1057 for(i=0; i<OFDM_Table_Length; i++) //find the index
1058 {
1059 if(tmpRegA == OFDMSwingTable[i])
1060 {
1061 priv->OFDM_index= (u8)i;
1062 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
1063 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
1064 }
1065 }
1066
1067 //Query CCK default setting From 0xa22
1068 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
1069 for(i=0 ; i<CCK_Table_length ; i++)
1070 {
1071 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
1072 {
1073 priv->CCK_index =(u8) i;
1074 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
1075 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
1076 break;
1077 }
1078 }
1079 priv->btxpower_trackingInit = TRUE;
1080 //pHalData->TXPowercount = 0;
1081 return;
1082 }
1083
1084 //==========================
1085 // this is only for test, should be masked
1086#if 0
1087{
1088 //UINT32 eRFPath;
1089 //UINT32 start_rf, end_rf;
1090 UINT32 curr_addr;
1091 //UINT32 reg_addr;
1092 //UINT32 reg_addr_end;
1093 UINT32 reg_value;
1094 //start_rf = RF90_PATH_A;
1095 //end_rf = RF90_PATH_B;//RF90_PATH_MAX;
1096 //reg_addr = 0x0;
1097 //reg_addr_end = 0x2F;
1098
1099 for (curr_addr = 0; curr_addr < 0x2d; curr_addr++)
1100 {
1101 reg_value = PHY_QueryRFReg( Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A,
1102 curr_addr, bMaskDWord);
1103 }
1104
1105 pHalData->TXPowercount = 0;
1106 return;
1107}
1108#endif
1109 //==========================
1110
1111 // read and filter out unreasonable value
1112 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
1113 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
1114 if(tmpRegA < 3 || tmpRegA > 13)
1115 return;
1116 if(tmpRegA >= 12) // if over 12, TP will be bad when high temprature
1117 tmpRegA = 12;
1118 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
1119 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
1120 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
1121
1122 //Get current RF-A temprature index
1123 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temprature
1124 {
1125 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
1126 tmpCCK40Mindex = tmpCCK20Mindex - 6;
1127 if(tmpOFDMindex >= OFDM_Table_Length)
1128 tmpOFDMindex = OFDM_Table_Length-1;
1129 if(tmpCCK20Mindex >= CCK_Table_length)
1130 tmpCCK20Mindex = CCK_Table_length-1;
1131 if(tmpCCK40Mindex >= CCK_Table_length)
1132 tmpCCK40Mindex = CCK_Table_length-1;
1133 }
1134 else
1135 {
1136 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
1137 if(tmpval >= 6) // higher temprature
1138 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
1139 else
1140 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
1141 tmpCCK40Mindex = 0;
1142 }
1143 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
1144 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
1145 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
1146 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
1147 tmpCCKindex = tmpCCK40Mindex;
1148 else
1149 tmpCCKindex = tmpCCK20Mindex;
1150
1151 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1152 {
1153 priv->bcck_in_ch14 = TRUE;
1154 CCKSwingNeedUpdate = 1;
1155 }
1156 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1157 {
1158 priv->bcck_in_ch14 = FALSE;
1159 CCKSwingNeedUpdate = 1;
1160 }
1161
1162 if(priv->CCK_index != tmpCCKindex)
1163 {
1164 priv->CCK_index = tmpCCKindex;
1165 CCKSwingNeedUpdate = 1;
1166 }
1167
1168 if(CCKSwingNeedUpdate)
1169 {
1170 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
1171 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1172 }
1173 if(priv->OFDM_index != tmpOFDMindex)
1174 {
1175 priv->OFDM_index = tmpOFDMindex;
1176 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
1177 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
1178 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
1179 }
1180 priv->txpower_count = 0;
1181}
1182
1183#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1184extern void dm_txpower_trackingcallback(struct work_struct *work)
1185{
1186 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1187 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
1188 struct net_device *dev = priv->ieee80211->dev;
1189#else
1190extern void dm_txpower_trackingcallback(struct net_device *dev)
1191{
1192 struct r8192_priv *priv = ieee80211_priv(dev);
1193#endif
1194
1195#ifdef RTL8190P
1196 dm_TXPowerTrackingCallback_TSSI(dev);
1197#else
1198 if(priv->bDcut == TRUE)
1199 dm_TXPowerTrackingCallback_TSSI(dev);
1200 else
1201 dm_TXPowerTrackingCallback_ThermalMeter(dev);
1202#endif
1203}
1204
1205
1206static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1207{
1208
1209 struct r8192_priv *priv = ieee80211_priv(dev);
1210
1211 //Initial the Tx BB index and mapping value
1212 priv->txbbgain_table[0].txbb_iq_amplifygain = 12;
1213 priv->txbbgain_table[0].txbbgain_value=0x7f8001fe;
1214 priv->txbbgain_table[1].txbb_iq_amplifygain = 11;
1215 priv->txbbgain_table[1].txbbgain_value=0x788001e2;
1216 priv->txbbgain_table[2].txbb_iq_amplifygain = 10;
1217 priv->txbbgain_table[2].txbbgain_value=0x71c001c7;
1218 priv->txbbgain_table[3].txbb_iq_amplifygain = 9;
1219 priv->txbbgain_table[3].txbbgain_value=0x6b8001ae;
1220 priv->txbbgain_table[4].txbb_iq_amplifygain = 8;
1221 priv->txbbgain_table[4].txbbgain_value=0x65400195;
1222 priv->txbbgain_table[5].txbb_iq_amplifygain = 7;
1223 priv->txbbgain_table[5].txbbgain_value=0x5fc0017f;
1224 priv->txbbgain_table[6].txbb_iq_amplifygain = 6;
1225 priv->txbbgain_table[6].txbbgain_value=0x5a400169;
1226 priv->txbbgain_table[7].txbb_iq_amplifygain = 5;
1227 priv->txbbgain_table[7].txbbgain_value=0x55400155;
1228 priv->txbbgain_table[8].txbb_iq_amplifygain = 4;
1229 priv->txbbgain_table[8].txbbgain_value=0x50800142;
1230 priv->txbbgain_table[9].txbb_iq_amplifygain = 3;
1231 priv->txbbgain_table[9].txbbgain_value=0x4c000130;
1232 priv->txbbgain_table[10].txbb_iq_amplifygain = 2;
1233 priv->txbbgain_table[10].txbbgain_value=0x47c0011f;
1234 priv->txbbgain_table[11].txbb_iq_amplifygain = 1;
1235 priv->txbbgain_table[11].txbbgain_value=0x43c0010f;
1236 priv->txbbgain_table[12].txbb_iq_amplifygain = 0;
1237 priv->txbbgain_table[12].txbbgain_value=0x40000100;
1238 priv->txbbgain_table[13].txbb_iq_amplifygain = -1;
1239 priv->txbbgain_table[13].txbbgain_value=0x3c8000f2;
1240 priv->txbbgain_table[14].txbb_iq_amplifygain = -2;
1241 priv->txbbgain_table[14].txbbgain_value=0x390000e4;
1242 priv->txbbgain_table[15].txbb_iq_amplifygain = -3;
1243 priv->txbbgain_table[15].txbbgain_value=0x35c000d7;
1244 priv->txbbgain_table[16].txbb_iq_amplifygain = -4;
1245 priv->txbbgain_table[16].txbbgain_value=0x32c000cb;
1246 priv->txbbgain_table[17].txbb_iq_amplifygain = -5;
1247 priv->txbbgain_table[17].txbbgain_value=0x300000c0;
1248 priv->txbbgain_table[18].txbb_iq_amplifygain = -6;
1249 priv->txbbgain_table[18].txbbgain_value=0x2d4000b5;
1250 priv->txbbgain_table[19].txbb_iq_amplifygain = -7;
1251 priv->txbbgain_table[19].txbbgain_value=0x2ac000ab;
1252 priv->txbbgain_table[20].txbb_iq_amplifygain = -8;
1253 priv->txbbgain_table[20].txbbgain_value=0x288000a2;
1254 priv->txbbgain_table[21].txbb_iq_amplifygain = -9;
1255 priv->txbbgain_table[21].txbbgain_value=0x26000098;
1256 priv->txbbgain_table[22].txbb_iq_amplifygain = -10;
1257 priv->txbbgain_table[22].txbbgain_value=0x24000090;
1258 priv->txbbgain_table[23].txbb_iq_amplifygain = -11;
1259 priv->txbbgain_table[23].txbbgain_value=0x22000088;
1260 priv->txbbgain_table[24].txbb_iq_amplifygain = -12;
1261 priv->txbbgain_table[24].txbbgain_value=0x20000080;
1262 priv->txbbgain_table[25].txbb_iq_amplifygain = -13;
1263 priv->txbbgain_table[25].txbbgain_value=0x1a00006c;
1264 priv->txbbgain_table[26].txbb_iq_amplifygain = -14;
1265 priv->txbbgain_table[26].txbbgain_value=0x1c800072;
1266 priv->txbbgain_table[27].txbb_iq_amplifygain = -15;
1267 priv->txbbgain_table[27].txbbgain_value=0x18000060;
1268 priv->txbbgain_table[28].txbb_iq_amplifygain = -16;
1269 priv->txbbgain_table[28].txbbgain_value=0x19800066;
1270 priv->txbbgain_table[29].txbb_iq_amplifygain = -17;
1271 priv->txbbgain_table[29].txbbgain_value=0x15800056;
1272 priv->txbbgain_table[30].txbb_iq_amplifygain = -18;
1273 priv->txbbgain_table[30].txbbgain_value=0x26c0005b;
1274 priv->txbbgain_table[31].txbb_iq_amplifygain = -19;
1275 priv->txbbgain_table[31].txbbgain_value=0x14400051;
1276 priv->txbbgain_table[32].txbb_iq_amplifygain = -20;
1277 priv->txbbgain_table[32].txbbgain_value=0x24400051;
1278 priv->txbbgain_table[33].txbb_iq_amplifygain = -21;
1279 priv->txbbgain_table[33].txbbgain_value=0x1300004c;
1280 priv->txbbgain_table[34].txbb_iq_amplifygain = -22;
1281 priv->txbbgain_table[34].txbbgain_value=0x12000048;
1282 priv->txbbgain_table[35].txbb_iq_amplifygain = -23;
1283 priv->txbbgain_table[35].txbbgain_value=0x11000044;
1284 priv->txbbgain_table[36].txbb_iq_amplifygain = -24;
1285 priv->txbbgain_table[36].txbbgain_value=0x10000040;
1286
1287 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1288 //This Table is for CH1~CH13
1289 priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
1290 priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
1291 priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
1292 priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
1293 priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
1294 priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
1295 priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
1296 priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
1297
1298 priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
1299 priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
1300 priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
1301 priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
1302 priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
1303 priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
1304 priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
1305 priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
1306
1307 priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
1308 priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
1309 priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
1310 priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
1311 priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
1312 priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
1313 priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
1314 priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
1315
1316 priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
1317 priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
1318 priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
1319 priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
1320 priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
1321 priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
1322 priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
1323 priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
1324
1325 priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
1326 priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
1327 priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
1328 priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
1329 priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
1330 priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
1331 priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
1332 priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
1333
1334 priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
1335 priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
1336 priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
1337 priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
1338 priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
1339 priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
1340 priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
1341 priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
1342
1343 priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
1344 priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
1345 priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
1346 priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
1347 priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
1348 priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
1349 priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
1350 priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
1351
1352 priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
1353 priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
1354 priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
1355 priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
1356 priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
1357 priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
1358 priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
1359 priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
1360
1361 priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
1362 priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
1363 priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
1364 priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
1365 priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
1366 priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
1367 priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
1368 priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
1369
1370 priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
1371 priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
1372 priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
1373 priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
1374 priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
1375 priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
1376 priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
1377 priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
1378
1379 priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
1380 priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
1381 priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
1382 priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
1383 priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
1384 priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
1385 priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
1386 priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
1387
1388 priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
1389 priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
1390 priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
1391 priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
1392 priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
1393 priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
1394 priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
1395 priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
1396
1397 priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
1398 priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
1399 priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
1400 priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
1401 priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
1402 priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
1403 priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
1404 priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
1405
1406 priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
1407 priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
1408 priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
1409 priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
1410 priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
1411 priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
1412 priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
1413 priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
1414
1415 priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
1416 priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
1417 priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
1418 priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
1419 priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
1420 priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
1421 priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
1422 priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
1423
1424 priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
1425 priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
1426 priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
1427 priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
1428 priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
1429 priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
1430 priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1431 priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1432
1433 priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1434 priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1435 priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1436 priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1437 priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1438 priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1439 priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1440 priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1441
1442 priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1443 priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1444 priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1445 priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1446 priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1447 priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1448 priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1449 priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1450
1451 priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1452 priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1453 priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1454 priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1455 priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1456 priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1457 priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1458 priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1459
1460 priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1461 priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1462 priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1463 priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1464 priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1465 priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1466 priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1467 priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1468
1469 priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1470 priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1471 priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1472 priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1473 priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1474 priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1475 priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1476 priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1477
1478 priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1479 priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1480 priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1481 priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1482 priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1483 priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1484 priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1485 priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1486
1487 priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1488 priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1489 priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1490 priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1491 priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1492 priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1493 priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1494 priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1495
1496 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1497 //This Table is for CH14
1498 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1499 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1500 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1501 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1502 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1503 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1504 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1505 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1506
1507 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1508 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1509 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1510 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1511 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1512 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1513 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1514 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1515
1516 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1517 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1518 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1519 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1520 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1521 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1522 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1523 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1524
1525 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1526 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1527 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1528 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1529 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1530 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1531 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1532 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1533
1534 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1535 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1536 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1537 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1538 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1539 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1540 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1541 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1542
1543 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1544 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1545 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1546 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1547 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1548 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1549 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1550 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1551
1552 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1553 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1554 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1555 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1556 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1557 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1558 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1559 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1560
1561 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1562 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1563 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1564 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1565 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1566 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1567 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1568 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1569
1570 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1571 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1572 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1573 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1574 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1575 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1576 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1577 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1578
1579 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1580 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1581 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1582 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1583 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1584 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1585 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1586 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1587
1588 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1589 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1590 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1591 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1592 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1593 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1594 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1595 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1596
1597 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1598 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1599 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1600 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1601 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1602 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1603 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1604 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1605
1606 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1607 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1608 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1609 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1610 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1611 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1612 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1613 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1614
1615 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1616 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1617 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1618 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1619 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1620 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1621 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1622 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1623
1624 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1625 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1626 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1627 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1628 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1629 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1630 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1631 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1632
1633 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1634 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1635 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1636 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1637 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1638 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1639 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1640 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1641
1642 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1643 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1644 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1645 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1646 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1647 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1648 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1649 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1650
1651 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1652 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1653 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1654 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1655 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1656 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1657 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1658 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1659
1660 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1661 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1662 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1663 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1664 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1665 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1666 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1667 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1668
1669 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1670 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1671 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1672 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1673 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1674 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1675 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1676 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1677
1678 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1679 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1680 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1681 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1682 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1683 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1684 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1685 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1686
1687 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1688 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1689 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1690 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1691 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1692 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1693 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1694 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1695
1696 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1697 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1698 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1699 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1700 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1701 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1702 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1703 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1704
1705 priv->btxpower_tracking = TRUE;
1706 priv->txpower_count = 0;
1707 priv->btxpower_trackingInit = FALSE;
1708
1709}
1710
1711#ifndef RTL8192SU
1712static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1713{
1714 struct r8192_priv *priv = ieee80211_priv(dev);
1715
1716 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1717 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1718 // 3-wire by driver cause RF goes into wrong state.
1719 if(priv->ieee80211->FwRWRF)
1720 priv->btxpower_tracking = TRUE;
1721 else
1722 priv->btxpower_tracking = FALSE;
1723 priv->txpower_count = 0;
1724 priv->btxpower_trackingInit = FALSE;
1725}
1726#endif
1727
1728void dm_initialize_txpower_tracking(struct net_device *dev)
1729{
1730#if (defined RTL8190P)
1731 dm_InitializeTXPowerTracking_TSSI(dev);
1732#elif (defined RTL8192SU)
1733 // 2009/01/12 MH Enable for 92S series channel 1-14 CCK tx pwer setting for MP.
1734 //
1735 dm_InitializeTXPowerTracking_TSSI(dev);
1736#else
1737 struct r8192_priv *priv = ieee80211_priv(dev);
1738 if(priv->bDcut == TRUE)
1739 dm_InitializeTXPowerTracking_TSSI(dev);
1740 else
1741 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1742#endif
1743}// dm_InitializeTXPowerTracking
1744
1745
1746static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1747{
1748 struct r8192_priv *priv = ieee80211_priv(dev);
1749 static u32 tx_power_track_counter = 0;
1750
1751 if(!priv->btxpower_tracking)
1752 return;
1753 else
1754 {
1755 if((tx_power_track_counter % 30 == 0)&&(tx_power_track_counter != 0))
1756 {
1757 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1758 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1759 #else
1760 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1761 schedule_task(&priv->txpower_tracking_wq);
1762 #else
1763 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1764 #endif
1765 #endif
1766 }
1767 tx_power_track_counter++;
1768 }
1769
1770}
1771
1772
1773static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1774{
1775 struct r8192_priv *priv = ieee80211_priv(dev);
1776 static u8 TM_Trigger=0;
1777#if 0
1778 u1Byte i;
1779 u4Byte tmpRegA;
1780 for(i=0; i<50; i++)
1781 {
1782 tmpRegA = PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
1783 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1784 //delay_us(100);
1785 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1786 //delay_us(100);
1787 }
1788 DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n");
1789#else
1790 //DbgPrint("dm_CheckTXPowerTracking() \n");
1791 if(!priv->btxpower_tracking)
1792 return;
1793 else
1794 {
1795 if(priv->txpower_count <= 2)
1796 {
1797 priv->txpower_count++;
1798 return;
1799 }
1800 }
1801
1802 if(!TM_Trigger)
1803 {
1804 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1805 //actually write reg0x02 bit1=0, then bit1=1.
1806 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1807#ifdef RTL8192SU
1808 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d);
1809 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f);
1810 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d);
1811 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f);
1812#else
1813 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1814 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1815 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1816 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1817#endif
1818 TM_Trigger = 1;
1819 return;
1820 }
1821 else
1822 {
1823 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1824 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1825 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1826 #else
1827 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1828 schedule_task(&priv->txpower_tracking_wq);
1829 #else
1830 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1831 #endif
1832 #endif
1833 TM_Trigger = 0;
1834 }
1835#endif
1836}
1837
1838
1839static void dm_check_txpower_tracking(struct net_device *dev)
1840{
1841 struct r8192_priv *priv = ieee80211_priv(dev);
1842 //static u32 tx_power_track_counter = 0;
1843
1844#ifdef RTL8190P
1845 dm_CheckTXPowerTracking_TSSI(dev);
1846#else
1847 if(priv->bDcut == TRUE)
1848 dm_CheckTXPowerTracking_TSSI(dev);
1849 else
1850 dm_CheckTXPowerTracking_ThermalMeter(dev);
1851#endif
1852
1853} // dm_CheckTXPowerTracking
1854
1855
1856static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1857{
1858 u32 TempVal;
1859 struct r8192_priv *priv = ieee80211_priv(dev);
1860 //Write 0xa22 0xa23
1861 TempVal = 0;
1862 if(!bInCH14){
1863 //Write 0xa22 0xa23
1864 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1865 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ;
1866
1867 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1868 //Write 0xa24 ~ 0xa27
1869 TempVal = 0;
1870 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1871 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1872 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16 )+
1873 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1874 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1875 //Write 0xa28 0xa29
1876 TempVal = 0;
1877 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1878 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ;
1879
1880 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1881 }
1882 else
1883 {
1884 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1885 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ;
1886
1887 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1888 //Write 0xa24 ~ 0xa27
1889 TempVal = 0;
1890 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1891 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1892 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16 )+
1893 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1894 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1895 //Write 0xa28 0xa29
1896 TempVal = 0;
1897 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1898 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ;
1899
1900 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1901 }
1902
1903
1904}
1905
1906static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1907{
1908 u32 TempVal;
1909 struct r8192_priv *priv = ieee80211_priv(dev);
1910
1911 TempVal = 0;
1912 if(!bInCH14)
1913 {
1914 //Write 0xa22 0xa23
1915 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1916 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1917 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1918 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1919 rCCK0_TxFilter1, TempVal);
1920 //Write 0xa24 ~ 0xa27
1921 TempVal = 0;
1922 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1923 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1924 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1925 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1926 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1927 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1928 rCCK0_TxFilter2, TempVal);
1929 //Write 0xa28 0xa29
1930 TempVal = 0;
1931 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1932 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1933
1934 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1935 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1936 rCCK0_DebugPort, TempVal);
1937 }
1938 else
1939 {
1940// priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1941 //Write 0xa22 0xa23
1942 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1943 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1944
1945 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1946 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1947 rCCK0_TxFilter1, TempVal);
1948 //Write 0xa24 ~ 0xa27
1949 TempVal = 0;
1950 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1951 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1952 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1953 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1954 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1955 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1956 rCCK0_TxFilter2, TempVal);
1957 //Write 0xa28 0xa29
1958 TempVal = 0;
1959 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1960 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1961
1962 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1963 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1964 rCCK0_DebugPort, TempVal);
1965 }
1966}
1967
1968
1969
1970extern void dm_cck_txpower_adjust(
1971 struct net_device *dev,
1972 bool binch14
1973)
1974{ // dm_CCKTxPowerAdjust
1975
1976 struct r8192_priv *priv = ieee80211_priv(dev);
1977#ifdef RTL8190P
1978 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1979#else
1980 if(priv->bDcut == TRUE)
1981 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1982 else
1983 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1984#endif
1985}
1986
1987
1988#ifndef RTL8192U
1989static void dm_txpower_reset_recovery(
1990 struct net_device *dev
1991)
1992{
1993 struct r8192_priv *priv = ieee80211_priv(dev);
1994
1995 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1996 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1997 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1998 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1999 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
2000 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->cck_present_attentuation);
2001 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2002
2003 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
2004 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
2005 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
2006 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
2007
2008} // dm_TXPowerResetRecovery
2009
2010extern void dm_restore_dynamic_mechanism_state(struct net_device *dev)
2011{
2012 struct r8192_priv *priv = ieee80211_priv(dev);
2013 u32 reg_ratr = priv->rate_adaptive.last_ratr;
2014
2015 if(!priv->up)
2016 {
2017 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
2018 return;
2019 }
2020
2021 //
2022 // Restore previous state for rate adaptive
2023 //
2024 if(priv->rate_adaptive.rate_adaptive_disabled)
2025 return;
2026 // TODO: Only 11n mode is implemented currently,
2027 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
2028 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
2029 return;
2030 {
2031 /* 2007/11/15 MH Copy from 8190PCI. */
2032 u32 ratr_value;
2033 ratr_value = reg_ratr;
2034 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
2035 {
2036 ratr_value &=~ (RATE_ALL_OFDM_2SS);
2037 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
2038 }
2039 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
2040 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
2041 write_nic_dword(dev, RATR0, ratr_value);
2042 write_nic_byte(dev, UFWP, 1);
2043#if 0 // Disable old code.
2044 u1Byte index;
2045 u4Byte input_value;
2046 index = (u1Byte)((((pu4Byte)(val))[0]) >> 28);
2047 input_value = (((pu4Byte)(val))[0]) & 0x0fffffff;
2048 // TODO: Correct it. Emily 2007.01.11
2049 PlatformEFIOWrite4Byte(Adapter, RATR0+index*4, input_value);
2050#endif
2051 }
2052 //Resore TX Power Tracking Index
2053 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
2054 dm_txpower_reset_recovery(dev);
2055 }
2056
2057 //
2058 //Restore BB Initial Gain
2059 //
2060 dm_bb_initialgain_restore(dev);
2061
2062} // DM_RestoreDynamicMechanismState
2063
2064static void dm_bb_initialgain_restore(struct net_device *dev)
2065{
2066 struct r8192_priv *priv = ieee80211_priv(dev);
2067 u32 bit_mask = 0x7f; //Bit0~ Bit6
2068
2069 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2070 return;
2071
2072 //Disable Initial Gain
2073 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
2074 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2075 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
2076 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
2077 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
2078 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
2079 bit_mask = bMaskByte2;
2080 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
2081
2082 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2083 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2084 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2085 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2086 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2087 //Enable Initial Gain
2088 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
2089 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2090
2091} // dm_BBInitialGainRestore
2092
2093
2094extern void dm_backup_dynamic_mechanism_state(struct net_device *dev)
2095{
2096 struct r8192_priv *priv = ieee80211_priv(dev);
2097
2098 // Fsync to avoid reset
2099 priv->bswitch_fsync = false;
2100 priv->bfsync_processing = false;
2101 //Backup BB InitialGain
2102 dm_bb_initialgain_backup(dev);
2103
2104} // DM_BackupDynamicMechanismState
2105
2106
2107static void dm_bb_initialgain_backup(struct net_device *dev)
2108{
2109 struct r8192_priv *priv = ieee80211_priv(dev);
2110 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
2111
2112 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2113 return;
2114
2115 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
2116 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2117 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
2118 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2119 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
2120 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
2121 bit_mask = bMaskByte2;
2122 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
2123
2124 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2125 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2126 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2127 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2128 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2129
2130} // dm_BBInitialGainBakcup
2131
2132#endif
2133/*-----------------------------------------------------------------------------
2134 * Function: dm_change_dynamic_initgain_thresh()
2135 *
2136 * Overview:
2137 *
2138 * Input: NONE
2139 *
2140 * Output: NONE
2141 *
2142 * Return: NONE
2143 *
2144 * Revised History:
2145 * When Who Remark
2146 * 05/29/2008 amy Create Version 0 porting from windows code.
2147 *
2148 *---------------------------------------------------------------------------*/
2149extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
2150 u32 dm_type,
2151 u32 dm_value)
2152{
2153#ifdef RTL8192SU
2154 struct r8192_priv *priv = ieee80211_priv(dev);
2155 if(dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2156 priv->MidHighPwrTHR_L2 = (u8)dm_value;
2157 else if(dm_type == DIG_TYPE_THRESH_HIGHPWR_LOW)
2158 priv->MidHighPwrTHR_L1 = (u8)dm_value;
2159 return;
2160#endif
2161 if (dm_type == DIG_TYPE_THRESH_HIGH)
2162 {
2163 dm_digtable.rssi_high_thresh = dm_value;
2164 }
2165 else if (dm_type == DIG_TYPE_THRESH_LOW)
2166 {
2167 dm_digtable.rssi_low_thresh = dm_value;
2168 }
2169 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2170 {
2171 dm_digtable.rssi_high_power_highthresh = dm_value;
2172 }
2173 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2174 {
2175 dm_digtable.rssi_high_power_highthresh = dm_value;
2176 }
2177 else if (dm_type == DIG_TYPE_ENABLE)
2178 {
2179 dm_digtable.dig_state = DM_STA_DIG_MAX;
2180 dm_digtable.dig_enable_flag = true;
2181 }
2182 else if (dm_type == DIG_TYPE_DISABLE)
2183 {
2184 dm_digtable.dig_state = DM_STA_DIG_MAX;
2185 dm_digtable.dig_enable_flag = false;
2186 }
2187 else if (dm_type == DIG_TYPE_DBG_MODE)
2188 {
2189 if(dm_value >= DM_DBG_MAX)
2190 dm_value = DM_DBG_OFF;
2191 dm_digtable.dbg_mode = (u8)dm_value;
2192 }
2193 else if (dm_type == DIG_TYPE_RSSI)
2194 {
2195 if(dm_value > 100)
2196 dm_value = 30;
2197 dm_digtable.rssi_val = (long)dm_value;
2198 }
2199 else if (dm_type == DIG_TYPE_ALGORITHM)
2200 {
2201 if (dm_value >= DIG_ALGO_MAX)
2202 dm_value = DIG_ALGO_BY_FALSE_ALARM;
2203 if(dm_digtable.dig_algorithm != (u8)dm_value)
2204 dm_digtable.dig_algorithm_switch = 1;
2205 dm_digtable.dig_algorithm = (u8)dm_value;
2206 }
2207 else if (dm_type == DIG_TYPE_BACKOFF)
2208 {
2209 if(dm_value > 30)
2210 dm_value = 30;
2211 dm_digtable.backoff_val = (u8)dm_value;
2212 }
2213 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
2214 {
2215 if(dm_value == 0)
2216 dm_value = 0x1;
2217 dm_digtable.rx_gain_range_min = (u8)dm_value;
2218 }
2219 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
2220 {
2221 if(dm_value > 0x50)
2222 dm_value = 0x50;
2223 dm_digtable.rx_gain_range_max = (u8)dm_value;
2224 }
2225} /* DM_ChangeDynamicInitGainThresh */
2226extern void
2227dm_change_fsync_setting(
2228 struct net_device *dev,
2229 s32 DM_Type,
2230 s32 DM_Value)
2231{
2232 struct r8192_priv *priv = ieee80211_priv(dev);
2233
2234 if (DM_Type == 0) // monitor 0xc38 register
2235 {
2236 if(DM_Value > 1)
2237 DM_Value = 1;
2238 priv->framesyncMonitor = (u8)DM_Value;
2239 //DbgPrint("pHalData->framesyncMonitor = %d", pHalData->framesyncMonitor);
2240 }
2241}
2242
2243extern void
2244dm_change_rxpath_selection_setting(
2245 struct net_device *dev,
2246 s32 DM_Type,
2247 s32 DM_Value)
2248{
2249 struct r8192_priv *priv = ieee80211_priv(dev);
2250 prate_adaptive pRA = (prate_adaptive)&(priv->rate_adaptive);
2251
2252
2253 if(DM_Type == 0)
2254 {
2255 if(DM_Value > 1)
2256 DM_Value = 1;
2257 DM_RxPathSelTable.Enable = (u8)DM_Value;
2258 }
2259 else if(DM_Type == 1)
2260 {
2261 if(DM_Value > 1)
2262 DM_Value = 1;
2263 DM_RxPathSelTable.DbgMode = (u8)DM_Value;
2264 }
2265 else if(DM_Type == 2)
2266 {
2267 if(DM_Value > 40)
2268 DM_Value = 40;
2269 DM_RxPathSelTable.SS_TH_low = (u8)DM_Value;
2270 }
2271 else if(DM_Type == 3)
2272 {
2273 if(DM_Value > 25)
2274 DM_Value = 25;
2275 DM_RxPathSelTable.diff_TH = (u8)DM_Value;
2276 }
2277 else if(DM_Type == 4)
2278 {
2279 if(DM_Value >= CCK_Rx_Version_MAX)
2280 DM_Value = CCK_Rx_Version_1;
2281 DM_RxPathSelTable.cck_method= (u8)DM_Value;
2282 }
2283 else if(DM_Type == 10)
2284 {
2285 if(DM_Value > 100)
2286 DM_Value = 50;
2287 DM_RxPathSelTable.rf_rssi[0] = (u8)DM_Value;
2288 }
2289 else if(DM_Type == 11)
2290 {
2291 if(DM_Value > 100)
2292 DM_Value = 50;
2293 DM_RxPathSelTable.rf_rssi[1] = (u8)DM_Value;
2294 }
2295 else if(DM_Type == 12)
2296 {
2297 if(DM_Value > 100)
2298 DM_Value = 50;
2299 DM_RxPathSelTable.rf_rssi[2] = (u8)DM_Value;
2300 }
2301 else if(DM_Type == 13)
2302 {
2303 if(DM_Value > 100)
2304 DM_Value = 50;
2305 DM_RxPathSelTable.rf_rssi[3] = (u8)DM_Value;
2306 }
2307 else if(DM_Type == 20)
2308 {
2309 if(DM_Value > 1)
2310 DM_Value = 1;
2311 pRA->ping_rssi_enable = (u8)DM_Value;
2312 }
2313 else if(DM_Type == 21)
2314 {
2315 if(DM_Value > 30)
2316 DM_Value = 30;
2317 pRA->ping_rssi_thresh_for_ra = DM_Value;
2318 }
2319}
2320
2321#if 0
2322extern void dm_force_tx_fw_info(struct net_device *dev,
2323 u32 force_type,
2324 u32 force_value)
2325{
2326 struct r8192_priv *priv = ieee80211_priv(dev);
2327
2328 if (force_type == 0) // don't force TxSC
2329 {
2330 //DbgPrint("Set Force SubCarrier Off\n");
2331 priv->tx_fwinfo_force_subcarriermode = 0;
2332 }
2333 else if(force_type == 1) //force
2334 {
2335 //DbgPrint("Set Force SubCarrier On\n");
2336 priv->tx_fwinfo_force_subcarriermode = 1;
2337 if(force_value > 3)
2338 force_value = 3;
2339 priv->tx_fwinfo_force_subcarrierval = (u8)force_value;
2340 }
2341}
2342#endif
2343
2344/*-----------------------------------------------------------------------------
2345 * Function: dm_dig_init()
2346 *
2347 * Overview: Set DIG scheme init value.
2348 *
2349 * Input: NONE
2350 *
2351 * Output: NONE
2352 *
2353 * Return: NONE
2354 *
2355 * Revised History:
2356 * When Who Remark
2357 * 05/15/2008 amy Create Version 0 porting from windows code.
2358 *
2359 *---------------------------------------------------------------------------*/
2360static void dm_dig_init(struct net_device *dev)
2361{
2362 struct r8192_priv *priv = ieee80211_priv(dev);
2363 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
2364 dm_digtable.dig_enable_flag = true;
2365 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
2366 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
2367 dm_digtable.dig_algorithm_switch = 0;
2368
2369 /* 2007/10/04 MH Define init gain threshol. */
2370 dm_digtable.dig_state = DM_STA_DIG_MAX;
2371 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2372 dm_digtable.initialgain_lowerbound_state = false;
2373
2374 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
2375 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
2376
2377 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
2378 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
2379
2380 dm_digtable.rssi_val = 50; //for new dig debug rssi value
2381 dm_digtable.backoff_val = DM_DIG_BACKOFF;
2382 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
2383 if(priv->CustomerID == RT_CID_819x_Netcore)
2384 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
2385 else
2386 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
2387
2388} /* dm_dig_init */
2389
2390
2391/*-----------------------------------------------------------------------------
2392 * Function: dm_ctrl_initgain_byrssi()
2393 *
2394 * Overview: Driver must monitor RSSI and notify firmware to change initial
2395 * gain according to different threshold. BB team provide the
2396 * suggested solution.
2397 *
2398 * Input: struct net_device *dev
2399 *
2400 * Output: NONE
2401 *
2402 * Return: NONE
2403 *
2404 * Revised History:
2405 * When Who Remark
2406 * 05/27/2008 amy Create Version 0 porting from windows code.
2407 *---------------------------------------------------------------------------*/
2408static void dm_ctrl_initgain_byrssi(struct net_device *dev)
2409{
2410
2411 if (dm_digtable.dig_enable_flag == false)
2412 return;
2413
2414 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2415 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
2416 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2417 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
2418// ;
2419 else
2420 return;
2421}
2422
2423
2424static void dm_ctrl_initgain_byrssi_by_driverrssi(
2425 struct net_device *dev)
2426{
2427 struct r8192_priv *priv = ieee80211_priv(dev);
2428 u8 i;
2429 static u8 fw_dig=0;
2430
2431 if (dm_digtable.dig_enable_flag == false)
2432 return;
2433
2434 //DbgPrint("Dig by Sw Rssi \n");
2435 if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.
2436 fw_dig = 0;
2437 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
2438 {// FW DIG Off
2439 for(i=0; i<3; i++)
2440 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2441 fw_dig++;
2442 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
2443 }
2444
2445 if(priv->ieee80211->state == IEEE80211_LINKED)
2446 dm_digtable.cur_connect_state = DIG_CONNECT;
2447 else
2448 dm_digtable.cur_connect_state = DIG_DISCONNECT;
2449
2450 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
2451 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2452
2453 if(dm_digtable.dbg_mode == DM_DBG_OFF)
2454 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
2455 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2456 dm_initial_gain(dev);
2457 dm_pd_th(dev);
2458 dm_cs_ratio(dev);
2459 if(dm_digtable.dig_algorithm_switch)
2460 dm_digtable.dig_algorithm_switch = 0;
2461 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
2462
2463} /* dm_CtrlInitGainByRssi */
2464
2465static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2466 struct net_device *dev)
2467{
2468 struct r8192_priv *priv = ieee80211_priv(dev);
2469 static u32 reset_cnt = 0;
2470 u8 i;
2471
2472 if (dm_digtable.dig_enable_flag == false)
2473 return;
2474
2475 if(dm_digtable.dig_algorithm_switch)
2476 {
2477 dm_digtable.dig_state = DM_STA_DIG_MAX;
2478 // Fw DIG On.
2479 for(i=0; i<3; i++)
2480 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2481 dm_digtable.dig_algorithm_switch = 0;
2482 }
2483
2484 if (priv->ieee80211->state != IEEE80211_LINKED)
2485 return;
2486
2487 // For smooth, we can not change DIG state.
2488 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
2489 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
2490 {
2491 return;
2492 }
2493 //DbgPrint("Dig by Fw False Alarm\n");
2494 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2495 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2496 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2497 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2498 /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold
2499 and then execute below step. */
2500 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
2501 {
2502 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2503 will be reset to init value. We must prevent the condition. */
2504 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
2505 (priv->reset_count == reset_cnt))
2506 {
2507 return;
2508 }
2509 else
2510 {
2511 reset_cnt = priv->reset_count;
2512 }
2513
2514 // If DIG is off, DIG high power state must reset.
2515 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2516 dm_digtable.dig_state = DM_STA_DIG_OFF;
2517
2518 // 1.1 DIG Off.
2519 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2520
2521 // 1.2 Set initial gain.
2522 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
2523 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2524 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
2525 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2526
2527 // 1.3 Lower PD_TH for OFDM.
2528 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2529 {
2530 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2531 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2532#ifdef RTL8192SU
2533 rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00);
2534#else
2535 #ifdef RTL8190P
2536 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2537 #else
2538 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2539 #endif
2540#endif
2541 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2542 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2543 */
2544 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2545
2546
2547 //else
2548 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2549 }
2550 else
2551 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2552
2553 // 1.4 Lower CS ratio for CCK.
2554 write_nic_byte(dev, 0xa0a, 0x08);
2555
2556 // 1.5 Higher EDCCA.
2557 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2558 return;
2559
2560 }
2561
2562 /* 2. When RSSI increase, We have to judge if it is larger than a treshold
2563 and then execute below step. */
2564 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
2565 {
2566 u8 reset_flag = 0;
2567
2568 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
2569 (priv->reset_count == reset_cnt))
2570 {
2571 dm_ctrl_initgain_byrssi_highpwr(dev);
2572 return;
2573 }
2574 else
2575 {
2576 if (priv->reset_count != reset_cnt)
2577 reset_flag = 1;
2578
2579 reset_cnt = priv->reset_count;
2580 }
2581
2582 dm_digtable.dig_state = DM_STA_DIG_ON;
2583 //DbgPrint("DIG ON\n\r");
2584
2585 // 2.1 Set initial gain.
2586 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2587 if (reset_flag == 1)
2588 {
2589 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
2590 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2591 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
2592 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2593 }
2594 else
2595 {
2596 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
2597 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2598 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
2599 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2600 }
2601
2602 // 2.2 Higher PD_TH for OFDM.
2603 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2604 {
2605 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2606 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2607 #ifdef RTL8190P
2608 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2609 #else
2610 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2611 #endif
2612 /*
2613 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2614 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2615 */
2616 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2617
2618 //else
2619 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2620 }
2621 else
2622 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2623
2624 // 2.3 Higher CS ratio for CCK.
2625 write_nic_byte(dev, 0xa0a, 0xcd);
2626
2627 // 2.4 Lower EDCCA.
2628 /* 2008/01/11 MH 90/92 series are the same. */
2629 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2630
2631 // 2.5 DIG On.
2632 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2633
2634 }
2635
2636 dm_ctrl_initgain_byrssi_highpwr(dev);
2637
2638} /* dm_CtrlInitGainByRssi */
2639
2640
2641/*-----------------------------------------------------------------------------
2642 * Function: dm_ctrl_initgain_byrssi_highpwr()
2643 *
2644 * Overview:
2645 *
2646 * Input: NONE
2647 *
2648 * Output: NONE
2649 *
2650 * Return: NONE
2651 *
2652 * Revised History:
2653 * When Who Remark
2654 * 05/28/2008 amy Create Version 0 porting from windows code.
2655 *
2656 *---------------------------------------------------------------------------*/
2657static void dm_ctrl_initgain_byrssi_highpwr(
2658 struct net_device * dev)
2659{
2660 struct r8192_priv *priv = ieee80211_priv(dev);
2661 static u32 reset_cnt_highpwr = 0;
2662
2663 // For smooth, we can not change high power DIG state in the range.
2664 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
2665 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
2666 {
2667 return;
2668 }
2669
2670 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2671 it is larger than a treshold and then execute below step. */
2672 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2673 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
2674 {
2675 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
2676 (priv->reset_count == reset_cnt_highpwr))
2677 return;
2678 else
2679 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
2680
2681 // 3.1 Higher PD_TH for OFDM for high power state.
2682 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2683 {
2684#ifdef RTL8192SU
2685 rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x10);
2686#else
2687 #ifdef RTL8190P
2688 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2689 #else
2690 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2691 #endif
2692#endif
2693 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2694 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2695 */
2696
2697 }
2698 else
2699 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2700 }
2701 else
2702 {
2703 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
2704 (priv->reset_count == reset_cnt_highpwr))
2705 return;
2706 else
2707 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
2708
2709 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
2710 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
2711 {
2712 // 3.2 Recover PD_TH for OFDM for normal power region.
2713 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2714 {
2715 #ifdef RTL8190P
2716 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2717 #else
2718 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2719 #endif
2720 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2721 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2722 */
2723
2724 }
2725 else
2726 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2727 }
2728 }
2729
2730 reset_cnt_highpwr = priv->reset_count;
2731
2732} /* dm_CtrlInitGainByRssiHighPwr */
2733
2734
2735static void dm_initial_gain(
2736 struct net_device * dev)
2737{
2738 struct r8192_priv *priv = ieee80211_priv(dev);
2739 u8 initial_gain=0;
2740 static u8 initialized=0, force_write=0;
2741 static u32 reset_cnt=0;
2742
2743 if(dm_digtable.dig_algorithm_switch)
2744 {
2745 initialized = 0;
2746 reset_cnt = 0;
2747 }
2748
2749 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2750 {
2751 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2752 {
2753 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2754 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2755 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2756 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2757 else
2758 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2759 }
2760 else //current state is disconnected
2761 {
2762 if(dm_digtable.cur_ig_value == 0)
2763 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2764 else
2765 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2766 }
2767 }
2768 else // disconnected -> connected or connected -> disconnected
2769 {
2770 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2771 dm_digtable.pre_ig_value = 0;
2772 }
2773 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2774
2775 // if silent reset happened, we should rewrite the values back
2776 if(priv->reset_count != reset_cnt)
2777 {
2778 force_write = 1;
2779 reset_cnt = priv->reset_count;
2780 }
2781
2782 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
2783 force_write = 1;
2784
2785 {
2786 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2787 || !initialized || force_write)
2788 {
2789 initial_gain = (u8)dm_digtable.cur_ig_value;
2790 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2791 // Set initial gain.
2792 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2793 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2794 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2795 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2796 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2797 initialized = 1;
2798 force_write = 0;
2799 }
2800 }
2801}
2802
2803static void dm_pd_th(
2804 struct net_device * dev)
2805{
2806 struct r8192_priv *priv = ieee80211_priv(dev);
2807 static u8 initialized=0, force_write=0;
2808 static u32 reset_cnt = 0;
2809
2810 if(dm_digtable.dig_algorithm_switch)
2811 {
2812 initialized = 0;
2813 reset_cnt = 0;
2814 }
2815
2816 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2817 {
2818 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2819 {
2820 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2821 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2822 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2823 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2824 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2825 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2826 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2827 else
2828 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2829 }
2830 else
2831 {
2832 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2833 }
2834 }
2835 else // disconnected -> connected or connected -> disconnected
2836 {
2837 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2838 }
2839
2840 // if silent reset happened, we should rewrite the values back
2841 if(priv->reset_count != reset_cnt)
2842 {
2843 force_write = 1;
2844 reset_cnt = priv->reset_count;
2845 }
2846
2847 {
2848 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2849 (initialized<=3) || force_write)
2850 {
2851 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2852 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
2853 {
2854 // Lower PD_TH for OFDM.
2855 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2856 {
2857 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2858 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2859#ifdef RTL8192SU
2860 rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00);
2861#else
2862 #ifdef RTL8190P
2863 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2864 #else
2865 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2866 #endif
2867#endif
2868 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2869 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2870 */
2871 }
2872 else
2873 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2874 }
2875 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2876 {
2877 // Higher PD_TH for OFDM.
2878 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2879 {
2880 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2881 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2882 #ifdef RTL8190P
2883 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2884 #else
2885 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2886 #endif
2887 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2888 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2889 */
2890 }
2891 else
2892 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2893 }
2894 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2895 {
2896 // Higher PD_TH for OFDM for high power state.
2897 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2898 {
2899 #ifdef RTL8190P
2900 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2901 #else
2902 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2903 #endif
2904 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2905 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2906 */
2907 }
2908 else
2909 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2910 }
2911 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2912 if(initialized <= 3)
2913 initialized++;
2914 force_write = 0;
2915 }
2916 }
2917}
2918
2919static void dm_cs_ratio(
2920 struct net_device * dev)
2921{
2922 struct r8192_priv *priv = ieee80211_priv(dev);
2923 static u8 initialized=0,force_write=0;
2924 static u32 reset_cnt = 0;
2925
2926 if(dm_digtable.dig_algorithm_switch)
2927 {
2928 initialized = 0;
2929 reset_cnt = 0;
2930 }
2931
2932 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2933 {
2934 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2935 {
2936 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2937 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2938 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2939 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2940 else
2941 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2942 }
2943 else
2944 {
2945 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2946 }
2947 }
2948 else // disconnected -> connected or connected -> disconnected
2949 {
2950 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2951 }
2952
2953 // if silent reset happened, we should rewrite the values back
2954 if(priv->reset_count != reset_cnt)
2955 {
2956 force_write = 1;
2957 reset_cnt = priv->reset_count;
2958 }
2959
2960
2961 {
2962 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2963 !initialized || force_write)
2964 {
2965 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2966 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2967 {
2968 // Lower CS ratio for CCK.
2969 write_nic_byte(dev, 0xa0a, 0x08);
2970 }
2971 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2972 {
2973 // Higher CS ratio for CCK.
2974 write_nic_byte(dev, 0xa0a, 0xcd);
2975 }
2976 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2977 initialized = 1;
2978 force_write = 0;
2979 }
2980 }
2981}
2982
2983extern void dm_init_edca_turbo(struct net_device * dev)
2984{
2985 struct r8192_priv *priv = ieee80211_priv(dev);
2986
2987 priv->bcurrent_turbo_EDCA = false;
2988 priv->ieee80211->bis_any_nonbepkts = false;
2989 priv->bis_cur_rdlstate = false;
2990} // dm_init_edca_turbo
2991
2992#if 1
2993static void dm_check_edca_turbo(
2994 struct net_device * dev)
2995{
2996 struct r8192_priv *priv = ieee80211_priv(dev);
2997 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2998 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2999
3000 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
3001 static unsigned long lastTxOkCnt = 0;
3002 static unsigned long lastRxOkCnt = 0;
3003 unsigned long curTxOkCnt = 0;
3004 unsigned long curRxOkCnt = 0;
3005
3006 //
3007 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
3008 // should follow the settings from QAP. By Bruce, 2007-12-07.
3009 //
3010 #if 1
3011 if(priv->ieee80211->state != IEEE80211_LINKED)
3012 goto dm_CheckEdcaTurbo_EXIT;
3013 #endif
3014 // We do not turn on EDCA turbo mode for some AP that has IOT issue
3015 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
3016 goto dm_CheckEdcaTurbo_EXIT;
3017
3018 {
3019 u8* peername[11] = {"unknown", "realtek", "realtek_92se", "broadcom", "ralink", "atheros", "cisco", "marvell", "92u_softap", "self_softap"};
3020 static int wb_tmp = 0;
3021 if (wb_tmp == 0){
3022 printk("%s():iot peer is %#x:%s, bssid:"MAC_FMT"\n",__FUNCTION__,pHTInfo->IOTPeer,peername[pHTInfo->IOTPeer], MAC_ARG(priv->ieee80211->current_network.bssid));
3023 wb_tmp = 1;
3024 }
3025 }
3026 // Check the status for current condition.
3027 if(!priv->ieee80211->bis_any_nonbepkts)
3028 {
3029 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
3030 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
3031#ifdef RTL8192SU
3032 // Modify EDCA parameters selection bias
3033 // For some APs, use downlink EDCA parameters for uplink+downlink
3034 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)
3035 {
3036 if(curTxOkCnt > 4*curRxOkCnt)
3037 {
3038 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3039 {
3040 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
3041 priv->bis_cur_rdlstate = false;
3042 }
3043 }
3044 else
3045 {
3046 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3047 {
3048 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
3049 priv->bis_cur_rdlstate = true;
3050 }
3051 }
3052 priv->bcurrent_turbo_EDCA = true;
3053 }
3054 else
3055 {
3056 if(curRxOkCnt > 4*curTxOkCnt)
3057 {
3058 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3059 {
3060 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
3061 priv->bis_cur_rdlstate = true;
3062 }
3063 }
3064 else
3065 {
3066 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3067 {
3068 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
3069 priv->bis_cur_rdlstate = false;
3070 }
3071 }
3072 priv->bcurrent_turbo_EDCA = true;
3073 }
3074#else
3075 // For RT-AP, we needs to turn it on when Rx>Tx
3076 if(curRxOkCnt > 4*curTxOkCnt)
3077 {
3078 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
3079 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3080 {
3081 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
3082 priv->bis_cur_rdlstate = true;
3083 }
3084 }
3085 else
3086 {
3087
3088 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
3089 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
3090 {
3091 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
3092 priv->bis_cur_rdlstate = false;
3093 }
3094
3095 }
3096
3097 priv->bcurrent_turbo_EDCA = true;
3098#endif
3099 }
3100 else
3101 {
3102 //
3103 // Turn Off EDCA turbo here.
3104 // Restore original EDCA according to the declaration of AP.
3105 //
3106 if(priv->bcurrent_turbo_EDCA)
3107 {
3108
3109 {
3110 u8 u1bAIFS;
3111 u32 u4bAcParam;
3112 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
3113 u8 mode = priv->ieee80211->mode;
3114
3115 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
3116 dm_init_edca_turbo(dev);
3117 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
3118 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
3119 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
3120 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
3121 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
3122 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
3123 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
3124
3125 // Check ACM bit.
3126 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
3127 {
3128 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
3129
3130 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
3131 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
3132 if( pAciAifsn->f.ACM )
3133 { // ACM bit is 1.
3134 AcmCtrl |= AcmHw_BeqEn;
3135 }
3136 else
3137 { // ACM bit is 0.
3138 AcmCtrl &= (~AcmHw_BeqEn);
3139 }
3140
3141 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
3142 write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
3143 }
3144 }
3145 priv->bcurrent_turbo_EDCA = false;
3146 }
3147 }
3148
3149
3150dm_CheckEdcaTurbo_EXIT:
3151 // Set variables for next time.
3152 priv->ieee80211->bis_any_nonbepkts = false;
3153 lastTxOkCnt = priv->stats.txbytesunicast;
3154 lastRxOkCnt = priv->stats.rxbytesunicast;
3155} // dm_CheckEdcaTurbo
3156#endif
3157
3158extern void DM_CTSToSelfSetting(struct net_device * dev,u32 DM_Type, u32 DM_Value)
3159{
3160 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3161
3162 if (DM_Type == 0) // CTS to self disable/enable
3163 {
3164 if(DM_Value > 1)
3165 DM_Value = 1;
3166 priv->ieee80211->bCTSToSelfEnable = (bool)DM_Value;
3167 //DbgPrint("pMgntInfo->bCTSToSelfEnable = %d\n", pMgntInfo->bCTSToSelfEnable);
3168 }
3169 else if(DM_Type == 1) //CTS to self Th
3170 {
3171 if(DM_Value >= 50)
3172 DM_Value = 50;
3173 priv->ieee80211->CTSToSelfTH = (u8)DM_Value;
3174 //DbgPrint("pMgntInfo->CTSToSelfTH = %d\n", pMgntInfo->CTSToSelfTH);
3175 }
3176}
3177
3178static void dm_init_ctstoself(struct net_device * dev)
3179{
3180 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3181
3182 priv->ieee80211->bCTSToSelfEnable = TRUE;
3183 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
3184}
3185
3186static void dm_ctstoself(struct net_device *dev)
3187{
3188 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3189 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
3190 static unsigned long lastTxOkCnt = 0;
3191 static unsigned long lastRxOkCnt = 0;
3192 unsigned long curTxOkCnt = 0;
3193 unsigned long curRxOkCnt = 0;
3194
3195 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
3196 {
3197 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3198 return;
3199 }
3200 /*
3201 1. Uplink
3202 2. Linksys350/Linksys300N
3203 3. <50 disable, >55 enable
3204 */
3205
3206 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
3207 {
3208 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
3209 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
3210 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
3211 {
3212 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3213 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
3214 }
3215 else //uplink
3216 {
3217 #if 1
3218 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3219 #else
3220 if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self
3221 {
3222 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3223 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
3224 }
3225 else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self
3226 {
3227 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3228 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
3229 }
3230 #endif
3231 }
3232
3233 lastTxOkCnt = priv->stats.txbytesunicast;
3234 lastRxOkCnt = priv->stats.rxbytesunicast;
3235 }
3236}
3237
3238
3239#if 0
3240/*-----------------------------------------------------------------------------
3241 * Function: dm_rf_operation_test_callback()
3242 *
3243 * Overview: Only for RF operation test now.
3244 *
3245 * Input: NONE
3246 *
3247 * Output: NONE
3248 *
3249 * Return: NONE
3250 *
3251 * Revised History:
3252 * When Who Remark
3253 * 05/29/2008 amy Create Version 0 porting from windows code.
3254 *
3255 *---------------------------------------------------------------------------*/
3256extern void dm_rf_operation_test_callback(unsigned long dev)
3257{
3258// struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3259 u8 erfpath;
3260
3261
3262 for(erfpath=0; erfpath<4; erfpath++)
3263 {
3264 //DbgPrint("Set RF-%d\n\r", eRFPath);
3265 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
3266 udelay(100);
3267 }
3268
3269 {
3270 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3271 }
3272
3273 // For test
3274 {
3275 //u8 i;
3276 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3277#if 0
3278 for(i=0; i<50; i++)
3279 {
3280 // Write Test
3281 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
3282 //delay_us(100);
3283 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
3284 //delay_us(100);
3285 PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4d);
3286 //delay_us(100);
3287 PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4f);
3288 //delay_us(100);
3289
3290#if 0
3291 // Read test
3292 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3293 //delay_us(100);
3294 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3295 //delay_us(100);
3296 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3297 //delay_us(100);
3298 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3299 //delay_us(100);
3300 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3301 //delay_us(100);
3302 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3303 //delay_us(100);
3304#endif
3305 }
3306#endif
3307 }
3308
3309} /* DM_RfOperationTestCallBack */
3310#endif
3311
3312/*-----------------------------------------------------------------------------
3313 * Function: dm_check_rfctrl_gpio()
3314 *
3315 * Overview: Copy 8187B template for 9xseries.
3316 *
3317 * Input: NONE
3318 *
3319 * Output: NONE
3320 *
3321 * Return: NONE
3322 *
3323 * Revised History:
3324 * When Who Remark
3325 * 05/28/2008 amy Create Version 0 porting from windows code.
3326 *
3327 *---------------------------------------------------------------------------*/
3328#if 1
3329static void dm_check_rfctrl_gpio(struct net_device * dev)
3330{
3331 //struct r8192_priv *priv = ieee80211_priv(dev);
3332
3333 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
3334 // page 1 register before Lextra bus is enabled cause system fails when resuming
3335 // from S4. 20080218, Emily
3336
3337 // Stop to execute workitem to prevent S3/S4 bug.
3338#ifdef RTL8190P
3339 return;
3340#endif
3341#ifdef RTL8192U
3342 return;
3343#endif
3344#ifdef RTL8192SU
3345 return;
3346#endif
3347#ifdef RTL8192E
3348 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3349 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
3350 #else
3351 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3352 schedule_task(&priv->gpio_change_rf_wq);
3353 #else
3354 queue_work(priv->priv_wq,&priv->gpio_change_rf_wq);
3355 #endif
3356 #endif
3357#endif
3358
3359} /* dm_CheckRfCtrlGPIO */
3360
3361#endif
3362/*-----------------------------------------------------------------------------
3363 * Function: dm_check_pbc_gpio()
3364 *
3365 * Overview: Check if PBC button is pressed.
3366 *
3367 * Input: NONE
3368 *
3369 * Output: NONE
3370 *
3371 * Return: NONE
3372 *
3373 * Revised History:
3374 * When Who Remark
3375 * 05/28/2008 amy Create Version 0 porting from windows code.
3376 *
3377 *---------------------------------------------------------------------------*/
3378static void dm_check_pbc_gpio(struct net_device *dev)
3379{
3380#ifdef RTL8192U
3381 struct r8192_priv *priv = ieee80211_priv(dev);
3382 u8 tmp1byte;
3383
3384
3385 tmp1byte = read_nic_byte(dev,GPI);
3386 if(tmp1byte == 0xff)
3387 return;
3388
3389 if (tmp1byte&BIT6 || tmp1byte&BIT0)
3390 {
3391 // Here we only set bPbcPressed to TRUE
3392 // After trigger PBC, the variable will be set to FALSE
3393 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
3394 priv->bpbc_pressed = true;
3395 }
3396#endif
3397#ifdef RTL8192SU
3398 struct r8192_priv *priv = ieee80211_priv(dev);
3399 u8 tmp1byte;
3400
3401 write_nic_byte(dev, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
3402
3403 tmp1byte = read_nic_byte(dev, GPIO_IO_SEL);
3404 tmp1byte &= ~(HAL_8192S_HW_GPIO_WPS_BIT);
3405 write_nic_byte(dev, GPIO_IO_SEL, tmp1byte);
3406
3407 tmp1byte = read_nic_byte(dev, GPIO_IN);
3408
3409 RT_TRACE(COMP_IO, "CheckPbcGPIO - %x\n", tmp1byte);
3410
3411 // Add by hpfan 2008.07.07 to fix read GPIO error from S3
3412 if (tmp1byte == 0xff)
3413 return ;
3414
3415 if (tmp1byte&HAL_8192S_HW_GPIO_WPS_BIT)
3416 {
3417 // Here we only set bPbcPressed to TRUE
3418 // After trigger PBC, the variable will be set to FALSE
3419 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
3420 priv->bpbc_pressed = true;
3421 }
3422
3423#endif
3424
3425
3426}
3427
3428#ifdef RTL8192E
3429
3430/*-----------------------------------------------------------------------------
3431 * Function: dm_GPIOChangeRF
3432 * Overview: PCI will not support workitem call back HW radio on-off control.
3433 *
3434 * Input: NONE
3435 *
3436 * Output: NONE
3437 *
3438 * Return: NONE
3439 *
3440 * Revised History:
3441 * When Who Remark
3442 * 02/21/2008 MHC Create Version 0.
3443 *
3444 *---------------------------------------------------------------------------*/
3445 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3446extern void dm_gpio_change_rf_callback(struct work_struct *work)
3447{
3448 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3449 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
3450 struct net_device *dev = priv->ieee80211->dev;
3451#else
3452extern void dm_gpio_change_rf_callback(struct net_device *dev)
3453{
3454 struct r8192_priv *priv = ieee80211_priv(dev);
3455#endif
3456 u8 tmp1byte;
3457 RT_RF_POWER_STATE eRfPowerStateToSet;
3458 bool bActuallySet = false;
3459
3460 do{
3461 bActuallySet=false;
3462
3463 if(!priv->up)
3464 {
3465 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
3466 }
3467 else
3468 {
3469 // 0x108 GPIO input register is read only
3470 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
3471 tmp1byte = read_nic_byte(dev,GPI);
3472
3473 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
3474
3475 if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
3476 {
3477 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n");
3478
3479 priv->bHwRadioOff = false;
3480 bActuallySet = true;
3481 }
3482 else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
3483 {
3484 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n");
3485 priv->bHwRadioOff = true;
3486 bActuallySet = true;
3487 }
3488
3489 if(bActuallySet)
3490 {
3491 #ifdef TO_DO
3492 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
3493 //DrvIFIndicateCurrentPhyStatus(pAdapter);
3494 #endif
3495 }
3496 else
3497 {
3498 msleep(2000);
3499 }
3500
3501 }
3502 }while(TRUE)
3503
3504} /* dm_GPIOChangeRF */
3505
3506#endif
3507/*-----------------------------------------------------------------------------
3508 * Function: DM_RFPathCheckWorkItemCallBack()
3509 *
3510 * Overview: Check if Current RF RX path is enabled
3511 *
3512 * Input: NONE
3513 *
3514 * Output: NONE
3515 *
3516 * Return: NONE
3517 *
3518 * Revised History:
3519 * When Who Remark
3520 * 01/30/2008 MHC Create Version 0.
3521 *
3522 *---------------------------------------------------------------------------*/
3523#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3524extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
3525{
3526 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3527 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
3528 struct net_device *dev =priv->ieee80211->dev;
3529#else
3530extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev)
3531{
3532 struct r8192_priv *priv = ieee80211_priv(dev);
3533#endif
3534 //bool bactually_set = false;
3535 u8 rfpath = 0, i;
3536
3537
3538 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
3539 always be the same. We only read 0xc04 now. */
3540 rfpath = read_nic_byte(dev, 0xc04);
3541
3542 // Check Bit 0-3, it means if RF A-D is enabled.
3543 for (i = 0; i < RF90_PATH_MAX; i++)
3544 {
3545 if (rfpath & (0x01<<i))
3546 priv->brfpath_rxenable[i] = 1;
3547 else
3548 priv->brfpath_rxenable[i] = 0;
3549 }
3550 if(!DM_RxPathSelTable.Enable)
3551 return;
3552
3553 dm_rxpath_sel_byrssi(dev);
3554} /* DM_RFPathCheckWorkItemCallBack */
3555
3556static void dm_init_rxpath_selection(struct net_device * dev)
3557{
3558 u8 i;
3559 struct r8192_priv *priv = ieee80211_priv(dev);
3560 DM_RxPathSelTable.Enable = 1; //default enabled
3561 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
3562 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
3563 if(priv->CustomerID == RT_CID_819x_Netcore)
3564 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
3565 else
3566 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
3567 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
3568 DM_RxPathSelTable.disabledRF = 0;
3569 for(i=0; i<4; i++)
3570 {
3571 DM_RxPathSelTable.rf_rssi[i] = 50;
3572 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
3573 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3574 }
3575}
3576
3577static void dm_rxpath_sel_byrssi(struct net_device * dev)
3578{
3579 struct r8192_priv *priv = ieee80211_priv(dev);
3580 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
3581 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
3582 u8 cck_default_Rx=0x2; //RF-C
3583 u8 cck_optional_Rx=0x3;//RF-D
3584 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
3585 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
3586 u8 cur_rf_rssi;
3587 long cur_cck_pwdb;
3588 static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
3589 u8 update_cck_rx_path;
3590
3591 if(priv->rf_type != RF_2T4R)
3592 return;
3593
3594 if(!cck_Rx_Path_initialized)
3595 {
3596 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
3597 cck_Rx_Path_initialized = 1;
3598 }
3599
3600 DM_RxPathSelTable.disabledRF = 0xf;
3601 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
3602
3603 if(priv->ieee80211->mode == WIRELESS_MODE_B)
3604 {
3605 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
3606 //DbgPrint("Pure B mode, use cck rx version2 \n");
3607 }
3608
3609 //decide max/sec/min rssi index
3610 for (i=0; i<RF90_PATH_MAX; i++)
3611 {
3612 if(!DM_RxPathSelTable.DbgMode)
3613 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
3614
3615 if(priv->brfpath_rxenable[i])
3616 {
3617 rf_num++;
3618 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
3619
3620 if(rf_num == 1) // find first enabled rf path and the rssi values
3621 { //initialize, set all rssi index to the same one
3622 max_rssi_index = min_rssi_index = sec_rssi_index = i;
3623 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
3624 }
3625 else if(rf_num == 2)
3626 { // we pick up the max index first, and let sec and min to be the same one
3627 if(cur_rf_rssi >= tmp_max_rssi)
3628 {
3629 tmp_max_rssi = cur_rf_rssi;
3630 max_rssi_index = i;
3631 }
3632 else
3633 {
3634 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
3635 sec_rssi_index = min_rssi_index = i;
3636 }
3637 }
3638 else
3639 {
3640 if(cur_rf_rssi > tmp_max_rssi)
3641 {
3642 tmp_sec_rssi = tmp_max_rssi;
3643 sec_rssi_index = max_rssi_index;
3644 tmp_max_rssi = cur_rf_rssi;
3645 max_rssi_index = i;
3646 }
3647 else if(cur_rf_rssi == tmp_max_rssi)
3648 { // let sec and min point to the different index
3649 tmp_sec_rssi = cur_rf_rssi;
3650 sec_rssi_index = i;
3651 }
3652 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
3653 {
3654 tmp_sec_rssi = cur_rf_rssi;
3655 sec_rssi_index = i;
3656 }
3657 else if(cur_rf_rssi == tmp_sec_rssi)
3658 {
3659 if(tmp_sec_rssi == tmp_min_rssi)
3660 { // let sec and min point to the different index
3661 tmp_sec_rssi = cur_rf_rssi;
3662 sec_rssi_index = i;
3663 }
3664 else
3665 {
3666 // This case we don't need to set any index
3667 }
3668 }
3669 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
3670 {
3671 // This case we don't need to set any index
3672 }
3673 else if(cur_rf_rssi == tmp_min_rssi)
3674 {
3675 if(tmp_sec_rssi == tmp_min_rssi)
3676 { // let sec and min point to the different index
3677 tmp_min_rssi = cur_rf_rssi;
3678 min_rssi_index = i;
3679 }
3680 else
3681 {
3682 // This case we don't need to set any index
3683 }
3684 }
3685 else if(cur_rf_rssi < tmp_min_rssi)
3686 {
3687 tmp_min_rssi = cur_rf_rssi;
3688 min_rssi_index = i;
3689 }
3690 }
3691 }
3692 }
3693
3694 rf_num = 0;
3695 // decide max/sec/min cck pwdb index
3696 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3697 {
3698 for (i=0; i<RF90_PATH_MAX; i++)
3699 {
3700 if(priv->brfpath_rxenable[i])
3701 {
3702 rf_num++;
3703 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
3704
3705 if(rf_num == 1) // find first enabled rf path and the rssi values
3706 { //initialize, set all rssi index to the same one
3707 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
3708 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
3709 }
3710 else if(rf_num == 2)
3711 { // we pick up the max index first, and let sec and min to be the same one
3712 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
3713 {
3714 tmp_cck_max_pwdb = cur_cck_pwdb;
3715 cck_rx_ver2_max_index = i;
3716 }
3717 else
3718 {
3719 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
3720 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
3721 }
3722 }
3723 else
3724 {
3725 if(cur_cck_pwdb > tmp_cck_max_pwdb)
3726 {
3727 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
3728 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
3729 tmp_cck_max_pwdb = cur_cck_pwdb;
3730 cck_rx_ver2_max_index = i;
3731 }
3732 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
3733 { // let sec and min point to the different index
3734 tmp_cck_sec_pwdb = cur_cck_pwdb;
3735 cck_rx_ver2_sec_index = i;
3736 }
3737 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
3738 {
3739 tmp_cck_sec_pwdb = cur_cck_pwdb;
3740 cck_rx_ver2_sec_index = i;
3741 }
3742 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
3743 {
3744 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3745 { // let sec and min point to the different index
3746 tmp_cck_sec_pwdb = cur_cck_pwdb;
3747 cck_rx_ver2_sec_index = i;
3748 }
3749 else
3750 {
3751 // This case we don't need to set any index
3752 }
3753 }
3754 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
3755 {
3756 // This case we don't need to set any index
3757 }
3758 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
3759 {
3760 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3761 { // let sec and min point to the different index
3762 tmp_cck_min_pwdb = cur_cck_pwdb;
3763 cck_rx_ver2_min_index = i;
3764 }
3765 else
3766 {
3767 // This case we don't need to set any index
3768 }
3769 }
3770 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
3771 {
3772 tmp_cck_min_pwdb = cur_cck_pwdb;
3773 cck_rx_ver2_min_index = i;
3774 }
3775 }
3776
3777 }
3778 }
3779 }
3780
3781
3782 // Set CCK Rx path
3783 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
3784 update_cck_rx_path = 0;
3785 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3786 {
3787 cck_default_Rx = cck_rx_ver2_max_index;
3788 cck_optional_Rx = cck_rx_ver2_sec_index;
3789 if(tmp_cck_max_pwdb != -64)
3790 update_cck_rx_path = 1;
3791 }
3792
3793 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
3794 {
3795 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
3796 {
3797 //record the enabled rssi threshold
3798 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
3799 //disable the BB Rx path, OFDM
3800 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
3801 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
3802 disabled_rf_cnt++;
3803 }
3804 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
3805 {
3806 cck_default_Rx = max_rssi_index;
3807 cck_optional_Rx = sec_rssi_index;
3808 if(tmp_max_rssi)
3809 update_cck_rx_path = 1;
3810 }
3811 }
3812
3813 if(update_cck_rx_path)
3814 {
3815 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
3816 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
3817 }
3818
3819 if(DM_RxPathSelTable.disabledRF)
3820 {
3821 for(i=0; i<4; i++)
3822 {
3823 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
3824 {
3825 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
3826 {
3827 //enable the BB Rx path
3828 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3829 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
3830 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
3831 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3832 disabled_rf_cnt--;
3833 }
3834 }
3835 }
3836 }
3837}
3838
3839/*-----------------------------------------------------------------------------
3840 * Function: dm_check_rx_path_selection()
3841 *
3842 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3843 *
3844 * Input: NONE
3845 *
3846 * Output: NONE
3847 *
3848 * Return: NONE
3849 *
3850 * Revised History:
3851 * When Who Remark
3852 * 05/28/2008 amy Create Version 0 porting from windows code.
3853 *
3854 *---------------------------------------------------------------------------*/
3855static void dm_check_rx_path_selection(struct net_device *dev)
3856{
3857 struct r8192_priv *priv = ieee80211_priv(dev);
3858#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3859 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
3860#else
3861#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3862 schedule_task(&priv->rfpath_check_wq);
3863#else
3864 queue_work(priv->priv_wq,&priv->rfpath_check_wq);
3865#endif
3866#endif
3867} /* dm_CheckRxRFPath */
3868
3869
3870static void dm_init_fsync (struct net_device *dev)
3871{
3872 struct r8192_priv *priv = ieee80211_priv(dev);
3873
3874 priv->ieee80211->fsync_time_interval = 500;
3875 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
3876 priv->ieee80211->fsync_rssi_threshold = 30;
3877#ifdef RTL8190P
3878 priv->ieee80211->bfsync_enable = true;
3879#else
3880 priv->ieee80211->bfsync_enable = false;
3881#endif
3882 priv->ieee80211->fsync_multiple_timeinterval = 3;
3883 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
3884 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
3885 priv->ieee80211->fsync_state = Default_Fsync;
3886 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
3887
3888 init_timer(&priv->fsync_timer);
3889 priv->fsync_timer.data = (unsigned long)dev;
3890 priv->fsync_timer.function = dm_fsync_timer_callback;
3891}
3892
3893
3894static void dm_deInit_fsync(struct net_device *dev)
3895{
3896 struct r8192_priv *priv = ieee80211_priv(dev);
3897 del_timer_sync(&priv->fsync_timer);
3898}
3899
3900extern void dm_fsync_timer_callback(unsigned long data)
3901{
3902 struct net_device *dev = (struct net_device *)data;
3903 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
3904 u32 rate_index, rate_count = 0, rate_count_diff=0;
3905 bool bSwitchFromCountDiff = false;
3906 bool bDoubleTimeInterval = false;
3907
3908 if( priv->ieee80211->state == IEEE80211_LINKED &&
3909 priv->ieee80211->bfsync_enable &&
3910 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3911 {
3912 // Count rate 54, MCS [7], [12, 13, 14, 15]
3913 u32 rate_bitmap;
3914 for(rate_index = 0; rate_index <= 27; rate_index++)
3915 {
3916 rate_bitmap = 1 << rate_index;
3917 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
3918 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
3919 }
3920
3921 if(rate_count < priv->rate_record)
3922 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
3923 else
3924 rate_count_diff = rate_count - priv->rate_record;
3925 if(rate_count_diff < priv->rateCountDiffRecord)
3926 {
3927
3928 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
3929 // Contiune count
3930 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
3931 priv->ContiuneDiffCount++;
3932 else
3933 priv->ContiuneDiffCount = 0;
3934
3935 // Contiune count over
3936 if(priv->ContiuneDiffCount >=2)
3937 {
3938 bSwitchFromCountDiff = true;
3939 priv->ContiuneDiffCount = 0;
3940 }
3941 }
3942 else
3943 {
3944 // Stop contiune count
3945 priv->ContiuneDiffCount = 0;
3946 }
3947
3948 //If Count diff <= FsyncRateCountThreshold
3949 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
3950 {
3951 bSwitchFromCountDiff = true;
3952 priv->ContiuneDiffCount = 0;
3953 }
3954 priv->rate_record = rate_count;
3955 priv->rateCountDiffRecord = rate_count_diff;
3956 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3957 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3958 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
3959 {
3960 bDoubleTimeInterval = true;
3961 priv->bswitch_fsync = !priv->bswitch_fsync;
3962 if(priv->bswitch_fsync)
3963 {
3964 #ifdef RTL8190P
3965 write_nic_byte(dev, 0xC36, 0x00);
3966 #else
3967 write_nic_byte(dev,0xC36, 0x1c);
3968 #endif
3969 write_nic_byte(dev, 0xC3e, 0x90);
3970 }
3971 else
3972 {
3973 #ifdef RTL8190P
3974 write_nic_byte(dev, 0xC36, 0x40);
3975 #else
3976 write_nic_byte(dev, 0xC36, 0x5c);
3977 #endif
3978 write_nic_byte(dev, 0xC3e, 0x96);
3979 }
3980 }
3981 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
3982 {
3983 if(priv->bswitch_fsync)
3984 {
3985 priv->bswitch_fsync = false;
3986 #ifdef RTL8190P
3987 write_nic_byte(dev, 0xC36, 0x40);
3988 #else
3989 write_nic_byte(dev, 0xC36, 0x5c);
3990 #endif
3991 write_nic_byte(dev, 0xC3e, 0x96);
3992 }
3993 }
3994 if(bDoubleTimeInterval){
3995 if(timer_pending(&priv->fsync_timer))
3996 del_timer_sync(&priv->fsync_timer);
3997 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
3998 add_timer(&priv->fsync_timer);
3999 }
4000 else{
4001 if(timer_pending(&priv->fsync_timer))
4002 del_timer_sync(&priv->fsync_timer);
4003 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
4004 add_timer(&priv->fsync_timer);
4005 }
4006 }
4007 else
4008 {
4009 // Let Register return to default value;
4010 if(priv->bswitch_fsync)
4011 {
4012 priv->bswitch_fsync = false;
4013 #ifdef RTL8190P
4014 write_nic_byte(dev, 0xC36, 0x40);
4015 #else
4016 write_nic_byte(dev, 0xC36, 0x5c);
4017 #endif
4018 write_nic_byte(dev, 0xC3e, 0x96);
4019 }
4020 priv->ContiuneDiffCount = 0;
4021#ifdef RTL8192SU
4022 rtl8192_setBBreg(dev, rOFDM0_RxDetector2, bMaskDWord, 0x164052cd);
4023#else
4024 #ifdef RTL8190P
4025 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
4026 #else
4027 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
4028 #endif
4029#endif
4030 }
4031 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
4032 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
4033}
4034
4035static void dm_StartHWFsync(struct net_device *dev)
4036{
4037 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
4038 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
4039 write_nic_byte(dev, 0xc3b, 0x41);
4040}
4041
4042static void dm_EndSWFsync(struct net_device *dev)
4043{
4044 struct r8192_priv *priv = ieee80211_priv(dev);
4045
4046 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
4047 del_timer_sync(&(priv->fsync_timer));
4048
4049 // Let Register return to default value;
4050 if(priv->bswitch_fsync)
4051 {
4052 priv->bswitch_fsync = false;
4053
4054 #ifdef RTL8190P
4055 write_nic_byte(dev, 0xC36, 0x40);
4056 #else
4057 write_nic_byte(dev, 0xC36, 0x5c);
4058 #endif
4059
4060 write_nic_byte(dev, 0xC3e, 0x96);
4061 }
4062
4063 priv->ContiuneDiffCount = 0;
4064#ifndef RTL8190P
4065 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
4066#endif
4067
4068}
4069
4070static void dm_StartSWFsync(struct net_device *dev)
4071{
4072 struct r8192_priv *priv = ieee80211_priv(dev);
4073 u32 rateIndex;
4074 u32 rateBitmap;
4075
4076 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
4077 // Initial rate record to zero, start to record.
4078 priv->rate_record = 0;
4079 // Initial contiune diff count to zero, start to record.
4080 priv->ContiuneDiffCount = 0;
4081 priv->rateCountDiffRecord = 0;
4082 priv->bswitch_fsync = false;
4083
4084 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
4085 {
4086 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
4087 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
4088 }
4089 else
4090 {
4091 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
4092 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
4093 }
4094 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
4095 {
4096 rateBitmap = 1 << rateIndex;
4097 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
4098 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
4099 }
4100 if(timer_pending(&priv->fsync_timer))
4101 del_timer_sync(&priv->fsync_timer);
4102 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
4103 add_timer(&priv->fsync_timer);
4104
4105#ifndef RTL8190P
4106 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
4107#endif
4108
4109}
4110
4111static void dm_EndHWFsync(struct net_device *dev)
4112{
4113 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
4114 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
4115 write_nic_byte(dev, 0xc3b, 0x49);
4116
4117}
4118
4119void dm_check_fsync(struct net_device *dev)
4120{
4121#define RegC38_Default 0
4122#define RegC38_NonFsync_Other_AP 1
4123#define RegC38_Fsync_AP_BCM 2
4124 struct r8192_priv *priv = ieee80211_priv(dev);
4125 //u32 framesyncC34;
4126 static u8 reg_c38_State=RegC38_Default;
4127 static u32 reset_cnt=0;
4128
4129 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
4130 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
4131
4132 if( priv->ieee80211->state == IEEE80211_LINKED &&
4133 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
4134 {
4135 if(priv->ieee80211->bfsync_enable == 0)
4136 {
4137 switch(priv->ieee80211->fsync_state)
4138 {
4139 case Default_Fsync:
4140 dm_StartHWFsync(dev);
4141 priv->ieee80211->fsync_state = HW_Fsync;
4142 break;
4143 case SW_Fsync:
4144 dm_EndSWFsync(dev);
4145 dm_StartHWFsync(dev);
4146 priv->ieee80211->fsync_state = HW_Fsync;
4147 break;
4148 case HW_Fsync:
4149 default:
4150 break;
4151 }
4152 }
4153 else
4154 {
4155 switch(priv->ieee80211->fsync_state)
4156 {
4157 case Default_Fsync:
4158 dm_StartSWFsync(dev);
4159 priv->ieee80211->fsync_state = SW_Fsync;
4160 break;
4161 case HW_Fsync:
4162 dm_EndHWFsync(dev);
4163 dm_StartSWFsync(dev);
4164 priv->ieee80211->fsync_state = SW_Fsync;
4165 break;
4166 case SW_Fsync:
4167 default:
4168 break;
4169
4170 }
4171 }
4172 if(priv->framesyncMonitor)
4173 {
4174 if(reg_c38_State != RegC38_Fsync_AP_BCM)
4175 { //For broadcom AP we write different default value
4176 #ifdef RTL8190P
4177 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
4178 #else
4179 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
4180 #endif
4181
4182 reg_c38_State = RegC38_Fsync_AP_BCM;
4183 }
4184 }
4185 }
4186 else
4187 {
4188 switch(priv->ieee80211->fsync_state)
4189 {
4190 case HW_Fsync:
4191 dm_EndHWFsync(dev);
4192 priv->ieee80211->fsync_state = Default_Fsync;
4193 break;
4194 case SW_Fsync:
4195 dm_EndSWFsync(dev);
4196 priv->ieee80211->fsync_state = Default_Fsync;
4197 break;
4198 case Default_Fsync:
4199 default:
4200 break;
4201 }
4202
4203 if(priv->framesyncMonitor)
4204 {
4205 if(priv->ieee80211->state == IEEE80211_LINKED)
4206 {
4207 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
4208 {
4209 if(reg_c38_State != RegC38_NonFsync_Other_AP)
4210 {
4211 #ifdef RTL8190P
4212 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
4213 #else
4214 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
4215 #endif
4216
4217 reg_c38_State = RegC38_NonFsync_Other_AP;
4218 #if 0//cosa
4219 if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
4220 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
4221 else
4222 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
4223 #endif
4224 }
4225 }
4226 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
4227 {
4228 if(reg_c38_State)
4229 {
4230 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4231 reg_c38_State = RegC38_Default;
4232 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
4233 }
4234 }
4235 }
4236 else
4237 {
4238 if(reg_c38_State)
4239 {
4240 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4241 reg_c38_State = RegC38_Default;
4242 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
4243 }
4244 }
4245 }
4246 }
4247 if(priv->framesyncMonitor)
4248 {
4249 if(priv->reset_count != reset_cnt)
4250 { //After silent reset, the reg_c38_State will be returned to default value
4251 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4252 reg_c38_State = RegC38_Default;
4253 reset_cnt = priv->reset_count;
4254 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
4255 }
4256 }
4257 else
4258 {
4259 if(reg_c38_State)
4260 {
4261 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4262 reg_c38_State = RegC38_Default;
4263 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
4264 }
4265 }
4266}
4267
4268#if 0
4269/*-----------------------------------------------------------------------------
4270 * Function: DM_CheckLBusStatus()
4271 *
4272 * Overview: For 9x series, we must make sure LBUS is active for IO.
4273 *
4274 * Input: NONE
4275 *
4276 * Output: NONE
4277 *
4278 * Return: NONE
4279 *
4280 * Revised History:
4281 * When Who Remark
4282 * 02/22/2008 MHC Create Version 0.
4283 *
4284 *---------------------------------------------------------------------------*/
4285extern s1Byte DM_CheckLBusStatus(IN PADAPTER Adapter)
4286{
4287 PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
4288
4289#if (HAL_CODE_BASE & RTL819X)
4290
4291#if (HAL_CODE_BASE == RTL8192)
4292
4293#if( DEV_BUS_TYPE==PCI_INTERFACE)
4294 //return (pMgntInfo->bLbusEnable); // For debug only
4295 return TRUE;
4296#endif
4297
4298#if( DEV_BUS_TYPE==USB_INTERFACE)
4299 return TRUE;
4300#endif
4301
4302#endif // #if (HAL_CODE_BASE == RTL8192)
4303
4304#if (HAL_CODE_BASE == RTL8190)
4305 return TRUE;
4306#endif // #if (HAL_CODE_BASE == RTL8190)
4307
4308#endif // #if (HAL_CODE_BASE & RTL819X)
4309} /* DM_CheckLBusStatus */
4310
4311#endif
4312
4313/*-----------------------------------------------------------------------------
4314 * Function: dm_shadow_init()
4315 *
4316 * Overview: Store all NIC MAC/BB register content.
4317 *
4318 * Input: NONE
4319 *
4320 * Output: NONE
4321 *
4322 * Return: NONE
4323 *
4324 * Revised History:
4325 * When Who Remark
4326 * 05/29/2008 amy Create Version 0 porting from windows code.
4327 *
4328 *---------------------------------------------------------------------------*/
4329extern void dm_shadow_init(struct net_device *dev)
4330{
4331 u8 page;
4332 u16 offset;
4333
4334 for (page = 0; page < 5; page++)
4335 for (offset = 0; offset < 256; offset++)
4336 {
4337 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4338 //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
4339 }
4340
4341 for (page = 8; page < 11; page++)
4342 for (offset = 0; offset < 256; offset++)
4343 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4344
4345 for (page = 12; page < 15; page++)
4346 for (offset = 0; offset < 256; offset++)
4347 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4348
4349} /* dm_shadow_init */
4350
4351/*---------------------------Define function prototype------------------------*/
4352/*-----------------------------------------------------------------------------
4353 * Function: DM_DynamicTxPower()
4354 *
4355 * Overview: Detect Signal strength to control TX Registry
4356 Tx Power Control For Near/Far Range
4357 *
4358 * Input: NONE
4359 *
4360 * Output: NONE
4361 *
4362 * Return: NONE
4363 *
4364 * Revised History:
4365 * When Who Remark
4366 * 03/06/2008 Jacken Create Version 0.
4367 *
4368 *---------------------------------------------------------------------------*/
4369static void dm_init_dynamic_txpower(struct net_device *dev)
4370{
4371 struct r8192_priv *priv = ieee80211_priv(dev);
4372
4373 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
4374 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
4375 priv->bLastDTPFlag_High = false;
4376 priv->bLastDTPFlag_Low = false;
4377 priv->bDynamicTxHighPower = false;
4378 priv->bDynamicTxLowPower = false;
4379}
4380
4381static void dm_dynamic_txpower(struct net_device *dev)
4382{
4383 struct r8192_priv *priv = ieee80211_priv(dev);
4384 unsigned int txhipower_threshhold=0;
4385 unsigned int txlowpower_threshold=0;
4386 if(priv->ieee80211->bdynamic_txpower_enable != true)
4387 {
4388 priv->bDynamicTxHighPower = false;
4389 priv->bDynamicTxLowPower = false;
4390 return;
4391 }
4392 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
4393 if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
4394 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
4395 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
4396 }
4397 else
4398 {
4399 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
4400 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
4401 }
4402
4403// printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
4404 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
4405
4406 if(priv->ieee80211->state == IEEE80211_LINKED)
4407 {
4408 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
4409 {
4410 priv->bDynamicTxHighPower = true;
4411 priv->bDynamicTxLowPower = false;
4412 }
4413 else
4414 {
4415 // high power state check
4416 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
4417 {
4418 priv->bDynamicTxHighPower = false;
4419 }
4420 // low power state check
4421 if(priv->undecorated_smoothed_pwdb < 35)
4422 {
4423 priv->bDynamicTxLowPower = true;
4424 }
4425 else if(priv->undecorated_smoothed_pwdb >= 40)
4426 {
4427 priv->bDynamicTxLowPower = false;
4428 }
4429 }
4430 }
4431 else
4432 {
4433 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
4434 priv->bDynamicTxHighPower = false;
4435 priv->bDynamicTxLowPower = false;
4436 }
4437
4438 if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
4439 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
4440 {
4441 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
4442#ifndef RTL8192SU
4443#if defined(RTL8190P) || defined(RTL8192E)
4444 SetTxPowerLevel8190(Adapter,pHalData->CurrentChannel);
4445#endif
4446
4447#ifdef RTL8192U
4448 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
4449 //pHalData->bStartTxCtrlByTPCNFR = FALSE; //Clear th flag of Set TX Power from Sitesurvey
4450#endif
4451#endif
4452 }
4453 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
4454 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
4455
4456} /* dm_dynamic_txpower */
4457
4458//added by vivi, for read tx rate and retrycount
4459static void dm_check_txrateandretrycount(struct net_device * dev)
4460{
4461 struct r8192_priv *priv = ieee80211_priv(dev);
4462 struct ieee80211_device* ieee = priv->ieee80211;
4463 //for 11n tx rate
4464// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4465#ifdef RTL8192SU
4466 ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, TX_RATE_REG);
4467#else
4468 ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4469#endif
4470 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
4471 //for initial tx rate
4472// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
4473 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
4474 //for tx tx retry count
4475// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4476 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4477}
4478
4479static void dm_send_rssi_tofw(struct net_device *dev)
4480{
4481#ifndef RTL8192SU
4482 DCMD_TXCMD_T tx_cmd;
4483 struct r8192_priv *priv = ieee80211_priv(dev);
4484
4485 // If we test chariot, we should stop the TX command ?
4486 // Because 92E will always silent reset when we send tx command. We use register
4487 // 0x1e0(byte) to botify driver.
4488 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
4489 return;
4490#if 1
4491 tx_cmd.Op = TXCMD_SET_RX_RSSI;
4492 tx_cmd.Length = 4;
4493 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
4494
4495 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
4496 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
4497#endif
4498#endif
4499}
4500
4501#ifdef TO_DO_LIST
4502static void
4503dm_CheckProtection(struct net_device *dev)
4504{
4505 struct r8192_priv *priv = ieee80211_priv(dev);
4506 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
4507 u8 CurRate;
4508
4509 if(priv->ieee80211->pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_FORCED_CTS2SELF))
4510 {
4511 CurRate = read_nic_byte(dev, INIMCS_SEL);
4512 if(CurRate <= DESC92S_RATE11M)
4513 priv->bDmDisableProtect = true;
4514 else
4515 priv->bDmDisableProtect = fasle;
4516 }
4517}
4518#endif
4519
4520/*---------------------------Define function prototype------------------------*/
4521
diff --git a/drivers/staging/rtl8192su/r8192U_dm.h b/drivers/staging/rtl8192su/r8192U_dm.h
new file mode 100644
index 00000000000..1e05d757988
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_dm.h
@@ -0,0 +1,309 @@
1/*****************************************************************************
2 * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
3 *
4 * Module: Hal819xUsbDM.h (RTL8192 Header H File)
5 *
6 *
7 * Note: For dynamic control definition constant structure.
8 *
9 *
10 * Export:
11 *
12 * Abbrev:
13 *
14 * History:
15 * Data Who Remark
16 * 10/04/2007 MHC Create initial version.
17 *
18 *****************************************************************************/
19 /* Check to see if the file has been included already. */
20#ifndef __R8192UDM_H__
21#define __R8192UDM_H__
22
23
24/*--------------------------Define Parameters-------------------------------*/
25#define DM_DIG_THRESH_HIGH 40
26#define DM_DIG_THRESH_LOW 35
27
28#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
29#define DM_DIG_HIGH_PWR_THRESH_LOW 70
30
31#define BW_AUTO_SWITCH_HIGH_LOW 25
32#define BW_AUTO_SWITCH_LOW_HIGH 30
33
34#define DM_check_fsync_time_interval 500
35
36
37#define DM_DIG_BACKOFF 12
38#define DM_DIG_MAX 0x36
39#define DM_DIG_MIN 0x1c
40#define DM_DIG_MIN_Netcore 0x12
41
42#define RxPathSelection_SS_TH_low 30
43#define RxPathSelection_diff_TH 18
44
45#define RateAdaptiveTH_High 50
46#define RateAdaptiveTH_Low_20M 30
47#define RateAdaptiveTH_Low_40M 10
48#define VeryLowRSSI 15
49#define CTSToSelfTHVal 30
50
51//defined by vivi, for tx power track
52#define E_FOR_TX_POWER_TRACK 300
53//Dynamic Tx Power Control Threshold
54#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
55#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
56//added by amy for atheros AP
57#define TX_POWER_ATHEROAP_THRESH_HIGH 78
58#define TX_POWER_ATHEROAP_THRESH_LOW 72
59
60//defined by vivi, for showing on UI
61#define Current_Tx_Rate_Reg 0x1b8
62#define Initial_Tx_Rate_Reg 0x1b9
63#define Tx_Retry_Count_Reg 0x1ac
64#define RegC38_TH 20
65#if 0
66//----------------------------------------------------------------------------
67// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
68//----------------------------------------------------------------------------
69
70//CCK
71#define RATR_1M 0x00000001
72#define RATR_2M 0x00000002
73#define RATR_55M 0x00000004
74#define RATR_11M 0x00000008
75//OFDM
76#define RATR_6M 0x00000010
77#define RATR_9M 0x00000020
78#define RATR_12M 0x00000040
79#define RATR_18M 0x00000080
80#define RATR_24M 0x00000100
81#define RATR_36M 0x00000200
82#define RATR_48M 0x00000400
83#define RATR_54M 0x00000800
84//MCS 1 Spatial Stream
85#define RATR_MCS0 0x00001000
86#define RATR_MCS1 0x00002000
87#define RATR_MCS2 0x00004000
88#define RATR_MCS3 0x00008000
89#define RATR_MCS4 0x00010000
90#define RATR_MCS5 0x00020000
91#define RATR_MCS6 0x00040000
92#define RATR_MCS7 0x00080000
93//MCS 2 Spatial Stream
94#define RATR_MCS8 0x00100000
95#define RATR_MCS9 0x00200000
96#define RATR_MCS10 0x00400000
97#define RATR_MCS11 0x00800000
98#define RATR_MCS12 0x01000000
99#define RATR_MCS13 0x02000000
100#define RATR_MCS14 0x04000000
101#define RATR_MCS15 0x08000000
102// ALL CCK Rate
103#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
104#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
105 |RATR_36M|RATR_48M|RATR_54M
106#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
107 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
108#endif
109/*--------------------------Define Parameters-------------------------------*/
110
111
112/*------------------------------Define structure----------------------------*/
113/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
114typedef struct _dynamic_initial_gain_threshold_
115{
116 u8 dig_enable_flag;
117 u8 dig_algorithm;
118 u8 dbg_mode;
119 u8 dig_algorithm_switch;
120
121 long rssi_low_thresh;
122 long rssi_high_thresh;
123
124 long rssi_high_power_lowthresh;
125 long rssi_high_power_highthresh;
126
127 u8 dig_state;
128 u8 dig_highpwr_state;
129 u8 cur_connect_state;
130 u8 pre_connect_state;
131
132 u8 curpd_thstate;
133 u8 prepd_thstate;
134 u8 curcs_ratio_state;
135 u8 precs_ratio_state;
136
137 u32 pre_ig_value;
138 u32 cur_ig_value;
139
140 u8 backoff_val;
141 u8 rx_gain_range_max;
142 u8 rx_gain_range_min;
143 bool initialgain_lowerbound_state;
144
145 long rssi_val;
146}dig_t;
147
148typedef enum tag_dynamic_init_gain_state_definition
149{
150 DM_STA_DIG_OFF = 0,
151 DM_STA_DIG_ON,
152 DM_STA_DIG_MAX
153}dm_dig_sta_e;
154
155
156/* 2007/10/08 MH Define RATR state. */
157typedef enum tag_dynamic_ratr_state_definition
158{
159 DM_RATR_STA_HIGH = 0,
160 DM_RATR_STA_MIDDLE = 1,
161 DM_RATR_STA_LOW = 2,
162 DM_RATR_STA_MAX
163}dm_ratr_sta_e;
164
165/* 2007/10/11 MH Define DIG operation type. */
166typedef enum tag_dynamic_init_gain_operation_type_definition
167{
168 DIG_TYPE_THRESH_HIGH = 0,
169 DIG_TYPE_THRESH_LOW = 1,
170 DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
171 DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
172 DIG_TYPE_DBG_MODE = 4,
173 DIG_TYPE_RSSI = 5,
174 DIG_TYPE_ALGORITHM = 6,
175 DIG_TYPE_BACKOFF = 7,
176 DIG_TYPE_PWDB_FACTOR = 8,
177 DIG_TYPE_RX_GAIN_MIN = 9,
178 DIG_TYPE_RX_GAIN_MAX = 10,
179 DIG_TYPE_ENABLE = 20,
180 DIG_TYPE_DISABLE = 30,
181 DIG_OP_TYPE_MAX
182}dm_dig_op_e;
183
184typedef enum tag_dig_algorithm_definition
185{
186 DIG_ALGO_BY_FALSE_ALARM = 0,
187 DIG_ALGO_BY_RSSI = 1,
188 DIG_ALGO_MAX
189}dm_dig_alg_e;
190
191typedef enum tag_dig_dbgmode_definition
192{
193 DIG_DBG_OFF = 0,
194 DIG_DBG_ON = 1,
195 DIG_DBG_MAX
196}dm_dig_dbg_e;
197
198typedef enum tag_dig_connect_definition
199{
200 DIG_DISCONNECT = 0,
201 DIG_CONNECT = 1,
202 DIG_CONNECT_MAX
203}dm_dig_connect_e;
204
205typedef enum tag_dig_packetdetection_threshold_definition
206{
207 DIG_PD_AT_LOW_POWER = 0,
208 DIG_PD_AT_NORMAL_POWER = 1,
209 DIG_PD_AT_HIGH_POWER = 2,
210 DIG_PD_MAX
211}dm_dig_pd_th_e;
212
213typedef enum tag_dig_cck_cs_ratio_state_definition
214{
215 DIG_CS_RATIO_LOWER = 0,
216 DIG_CS_RATIO_HIGHER = 1,
217 DIG_CS_MAX
218}dm_dig_cs_ratio_e;
219typedef struct _Dynamic_Rx_Path_Selection_
220{
221 u8 Enable;
222 u8 DbgMode;
223 u8 cck_method;
224 u8 cck_Rx_path;
225
226 u8 SS_TH_low;
227 u8 diff_TH;
228 u8 disabledRF;
229 u8 reserved;
230
231 u8 rf_rssi[4];
232 u8 rf_enable_rssi_th[4];
233 long cck_pwdb_sta[4];
234}DRxPathSel;
235
236typedef enum tag_CCK_Rx_Path_Method_Definition
237{
238 CCK_Rx_Version_1 = 0,
239 CCK_Rx_Version_2= 1,
240 CCK_Rx_Version_MAX
241}DM_CCK_Rx_Path_Method;
242
243typedef enum tag_DM_DbgMode_Definition
244{
245 DM_DBG_OFF = 0,
246 DM_DBG_ON = 1,
247 DM_DBG_MAX
248}DM_DBG_E;
249
250typedef struct tag_Tx_Config_Cmd_Format
251{
252 u32 Op; /* Command packet type. */
253 u32 Length; /* Command packet length. */
254 u32 Value;
255}DCMD_TXCMD_T, *PDCMD_TXCMD_T;
256/*------------------------------Define structure----------------------------*/
257
258
259/*------------------------Export global variable----------------------------*/
260extern dig_t dm_digtable;
261extern u8 dm_shadow[16][256];
262extern DRxPathSel DM_RxPathSelTable;
263/*------------------------Export global variable----------------------------*/
264
265
266/*------------------------Export Marco Definition---------------------------*/
267
268/*------------------------Export Marco Definition---------------------------*/
269
270
271/*--------------------------Exported Function prototype---------------------*/
272extern void init_hal_dm(struct net_device *dev);
273extern void deinit_hal_dm(struct net_device *dev);
274
275extern void hal_dm_watchdog(struct net_device *dev);
276
277extern void init_rate_adaptive(struct net_device *dev);
278#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
279extern void dm_txpower_trackingcallback(struct work_struct *work);
280#else
281extern void dm_txpower_trackingcallback(struct net_device *dev);
282#endif
283extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
284extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
285extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
286 u32 dm_type, u32 dm_value);
287extern void dm_force_tx_fw_info(struct net_device *dev,u32 force_type, u32 force_value);
288extern void dm_init_edca_turbo(struct net_device *dev);
289extern void dm_rf_operation_test_callback(unsigned long data);
290#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
291extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
292#else
293extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev);
294#endif
295extern void dm_fsync_timer_callback(unsigned long data);
296extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
297#if 0
298extern char dm_check_lbus_status(IN PADAPTER Adapter);
299#endif
300extern void dm_shadow_init(struct net_device *dev);
301extern void dm_initialize_txpower_tracking(struct net_device *dev);
302/*--------------------------Exported Function prototype---------------------*/
303
304
305#endif /*__R8192UDM_H__ */
306
307
308/* End of r8192U_dm.h */
309
diff --git a/drivers/staging/rtl8192su/r8192U_hw.h b/drivers/staging/rtl8192su/r8192U_hw.h
new file mode 100644
index 00000000000..f2500e654a7
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_hw.h
@@ -0,0 +1,746 @@
1/*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official Realtek driver.
8 Parts of this driver are based on the rtl8180 driver skeleton
9 from Patric Schenke & Andres Salomon.
10 Parts of this driver are based on the Intel Pro Wireless
11 2100 GPL driver.
12
13 We want to tanks the Authors of those projects
14 and the Ndiswrapper project Authors.
15*/
16
17/* Mariusz Matuszek added full registers definition with Realtek's name */
18
19/* this file contains register definitions for the rtl8187 MAC controller */
20#ifndef R8192_HW
21#define R8192_HW
22
23typedef enum _VERSION_819xU{
24 VERSION_819xU_A, // A-cut
25 VERSION_819xU_B, // B-cut
26 VERSION_819xU_C,// C-cut
27}VERSION_819xU,*PVERSION_819xU;
28//added for different RF type
29typedef enum _RT_RF_TYPE_DEF
30{
31 RF_1T2R = 0,
32 RF_2T4R,
33
34 RF_819X_MAX_TYPE
35}RT_RF_TYPE_DEF;
36
37
38typedef enum _BaseBand_Config_Type{
39 BaseBand_Config_PHY_REG = 0, //Radio Path A
40 BaseBand_Config_AGC_TAB = 1, //Radio Path B
41}BaseBand_Config_Type, *PBaseBand_Config_Type;
42#if 0
43typedef enum _RT_RF_TYPE_819xU{
44 RF_TYPE_MIN = 0,
45 RF_8225,
46 RF_8256,
47 RF_8258,
48 RF_PSEUDO_11N = 4,
49}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
50#endif
51#define RTL8187_REQT_READ 0xc0
52#define RTL8187_REQT_WRITE 0x40
53#define RTL8187_REQ_GET_REGS 0x05
54#define RTL8187_REQ_SET_REGS 0x05
55
56#define MAX_TX_URB 16 //less URB will cause 2.4.31 crash, need to fix it further
57#define MAX_RX_URB 16
58
59#define R8180_MAX_RETRY 255
60//#define MAX_RX_NORMAL_URB 3
61//#define MAX_RX_COMMAND_URB 2
62#define RX_URB_SIZE 9100
63
64#define BB_ANTATTEN_CHAN14 0x0c
65#define BB_ANTENNA_B 0x40
66
67#define BB_HOST_BANG (1<<30)
68#define BB_HOST_BANG_EN (1<<2)
69#define BB_HOST_BANG_CLK (1<<1)
70#define BB_HOST_BANG_RW (1<<3)
71#define BB_HOST_BANG_DATA 1
72
73//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920)
74#define AFR 0x010
75#define AFR_CardBEn (1<<0)
76#define AFR_CLKRUN_SEL (1<<1)
77#define AFR_FuncRegEn (1<<2)
78#define RTL8190_EEPROM_ID 0x8129
79#define EEPROM_VID 0x02
80#define EEPROM_PID 0x04
81#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
82
83#define EEPROM_TxPowerDiff 0x1F
84#define EEPROM_ThermalMeter 0x20
85#define EEPROM_PwDiff 0x21 //0x21
86#define EEPROM_CrystalCap 0x22 //0x22
87
88#define EEPROM_TxPwIndex_CCK 0x23 //0x23
89#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26
90#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B
91#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E
92#define EEPROM_TxPwIndex_Ver 0x27 //0x27
93
94#define EEPROM_Default_TxPowerDiff 0x0
95#define EEPROM_Default_ThermalMeter 0x7
96#define EEPROM_Default_PwDiff 0x4
97#define EEPROM_Default_CrystalCap 0x5
98#define EEPROM_Default_TxPower 0x1010
99#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
100#define EEPROM_ChannelPlan 0x16 //0x7C
101#define EEPROM_IC_VER 0x7d //0x7D
102#define EEPROM_CRC 0x7e //0x7E~0x7F
103
104#define EEPROM_CID_DEFAULT 0x0
105#define EEPROM_CID_CAMEO 0x1
106#define EEPROM_CID_RUNTOP 0x2
107#define EEPROM_CID_Senao 0x3
108#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31
109#define EEPROM_CID_NetCore 0x5
110#define EEPROM_CID_Nettronix 0x6
111#define EEPROM_CID_Pronet 0x7
112#define EEPROM_CID_DLINK 0x8
113
114#define AC_PARAM_TXOP_LIMIT_OFFSET 16
115#define AC_PARAM_ECW_MAX_OFFSET 12
116#define AC_PARAM_ECW_MIN_OFFSET 8
117#define AC_PARAM_AIFS_OFFSET 0
118
119//#endif
120enum _RTL8192Usb_HW {
121
122 PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh
123#define BB_GLOBAL_RESET_BIT 0x1
124 BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register
125 BSSIDR = 0x02E, // BSSID Register
126 CMDR = 0x037, // Command register
127#define CR_RST 0x10
128#define CR_RE 0x08
129#define CR_TE 0x04
130#define CR_MulRW 0x01
131 SIFS = 0x03E, // SIFS register
132 TCR = 0x040, // Transmit Configuration Register
133
134#define TCR_MXDMA_2048 7
135#define TCR_LRL_OFFSET 0
136#define TCR_SRL_OFFSET 8
137#define TCR_MXDMA_OFFSET 21
138#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer
139 RCR = 0x044, // Receive Configuration Register
140#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
141 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
142#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
143#define RX_FIFO_THRESHOLD_SHIFT 13
144#define RX_FIFO_THRESHOLD_128 3
145#define RX_FIFO_THRESHOLD_256 4
146#define RX_FIFO_THRESHOLD_512 5
147#define RX_FIFO_THRESHOLD_1024 6
148#define RX_FIFO_THRESHOLD_NONE 7
149#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
150#define RCR_MXDMA_OFFSET 8
151#define RCR_FIFO_OFFSET 13
152#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
153#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
154#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1
155#define RCR_ENMBID BIT27 // Enable Multiple BssId.
156#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
157#define RCR_CBSSID BIT23 // Accept BSSID match packet
158#define RCR_APWRMGT BIT22 // Accept power management packet
159#define RCR_ADD3 BIT21 // Accept address 3 match packet
160#define RCR_AMF BIT20 // Accept management type frame
161#define RCR_ACF BIT19 // Accept control type frame
162#define RCR_ADF BIT18 // Accept data type frame
163#define RCR_RXFTH BIT13 // Rx FIFO Threshold
164#define RCR_AICV BIT12 // Accept ICV error packet
165#define RCR_ACRC32 BIT5 // Accept CRC32 error packet
166#define RCR_AB BIT3 // Accept broadcast packet
167#define RCR_AM BIT2 // Accept multicast packet
168#define RCR_APM BIT1 // Accept physical match packet
169#define RCR_AAP BIT0 // Accept all unicast packet
170 SLOT_TIME = 0x049, // Slot Time Register
171 ACK_TIMEOUT = 0x04c, // Ack Timeout Register
172 PIFS_TIME = 0x04d, // PIFS time
173 USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock.
174 EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE
175 EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK
176 EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO
177 EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI
178 RFPC = 0x05F, // Rx FIFO Packet Count
179 CWRR = 0x060, // Contention Window Report Register
180 BCN_TCFG = 0x062, // Beacon Time Configuration
181#define BCN_TCFG_CW_SHIFT 8
182#define BCN_TCFG_IFS 0
183 BCN_INTERVAL = 0x070, // Beacon Interval (TU)
184 ATIMWND = 0x072, // ATIM Window Size (TU)
185 BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
186 BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
187 BCN_ERR_THRESH = 0x078, // Beacon Error Threshold
188 RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd
189 WCAMI = 0x0A4, // Software write CAM input content
190 RCAMO = 0x0A8, // Software read/write CAM config
191 SECR = 0x0B0, //Security Configuration Register
192#define SCR_TxUseDK BIT0 //Force Tx Use Default Key
193#define SCR_RxUseDK BIT1 //Force Rx Use Default Key
194#define SCR_TxEncEnable BIT2 //Enable Tx Encryption
195#define SCR_RxDecEnable BIT3 //Enable Rx Decryption
196#define SCR_SKByA2 BIT4 //Search kEY BY A2
197#define SCR_NoSKMC BIT5 //No Key Search for Multicast
198#define SCR_UseDK 0x01
199#define SCR_TxSecEnable 0x02
200#define SCR_RxSecEnable 0x04
201 TPPoll = 0x0fd, // Transmit priority polling register
202 PSR = 0x0ff, // Page Select Register
203#define CPU_CCK_LOOPBACK 0x00030000
204#define CPU_GEN_SYSTEM_RESET 0x00000001
205#define CPU_GEN_FIRMWARE_RESET 0x00000008
206#define CPU_GEN_BOOT_RDY 0x00000010
207#define CPU_GEN_FIRM_RDY 0x00000020
208#define CPU_GEN_PUT_CODE_OK 0x00000080
209#define CPU_GEN_BB_RST 0x00000100
210#define CPU_GEN_PWR_STB_CPU 0x00000004
211#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
212#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
213
214//----------------------------------------------------------------------------
215// 8190 CPU General Register (offset 0x100, 4 byte)
216//----------------------------------------------------------------------------
217#define CPU_CCK_LOOPBACK 0x00030000
218#define CPU_GEN_SYSTEM_RESET 0x00000001
219#define CPU_GEN_FIRMWARE_RESET 0x00000008
220#define CPU_GEN_BOOT_RDY 0x00000010
221#define CPU_GEN_FIRM_RDY 0x00000020
222#define CPU_GEN_PUT_CODE_OK 0x00000080
223#define CPU_GEN_BB_RST 0x00000100
224#define CPU_GEN_PWR_STB_CPU 0x00000004
225#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
226#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
227 CPU_GEN = 0x100, // CPU Reset Register
228 LED1Cfg = 0x154,// LED1 Configuration Register
229 LED0Cfg = 0x155,// LED0 Configuration Register
230
231 AcmAvg = 0x170, // ACM Average Period Register
232 AcmHwCtrl = 0x171, // ACM Hardware Control Register
233//----------------------------------------------------------------------------
234////
235//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
236////----------------------------------------------------------------------------
237//
238#define AcmHw_HwEn BIT0
239#define AcmHw_BeqEn BIT1
240#define AcmHw_ViqEn BIT2
241#define AcmHw_VoqEn BIT3
242#define AcmHw_BeqStatus BIT4
243#define AcmHw_ViqStatus BIT5
244#define AcmHw_VoqStatus BIT6
245
246 AcmFwCtrl = 0x172, // ACM Firmware Control Register
247 AES_11N_FIX = 0x173,
248 VOAdmTime = 0x174, // VO Queue Admitted Time Register
249 VIAdmTime = 0x178, // VI Queue Admitted Time Register
250 BEAdmTime = 0x17C, // BE Queue Admitted Time Register
251 RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
252 RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
253 RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public,
254// QPRR = 0x1E0, // Queue Page Report per TID
255 QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID
256 BQDA = 0x200, // Beacon Queue Descriptor Address
257 HQDA = 0x204, // High Priority Queue Descriptor Address
258 CQDA = 0x208, // Command Queue Descriptor Address
259 MQDA = 0x20C, // Management Queue Descriptor Address
260 HCCAQDA = 0x210, // HCCA Queue Descriptor Address
261 VOQDA = 0x214, // VO Queue Descriptor Address
262 VIQDA = 0x218, // VI Queue Descriptor Address
263 BEQDA = 0x21C, // BE Queue Descriptor Address
264 BKQDA = 0x220, // BK Queue Descriptor Address
265 RCQDA = 0x224, // Receive command Queue Descriptor Address
266 RDQDA = 0x228, // Receive Queue Descriptor Start Address
267
268 MAR0 = 0x240, // Multicast filter.
269 MAR4 = 0x244,
270
271 CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU.
272 CLM_RESULT = 0x251, // CCA Busy fraction register.
273 NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU.
274
275 NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0.
276 NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1.
277 NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2.
278 NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3.
279 NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4.
280 NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5.
281 NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6
282
283 MCTRL = 0x25A, // Measurement Control
284
285 NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
286 NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1].
287 NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2].
288 NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3].
289 NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4].
290 NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5].
291 NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6].
292 NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7].
293#define BW_OPMODE_11J BIT0
294#define BW_OPMODE_5G BIT1
295#define BW_OPMODE_20MHZ BIT2
296 BW_OPMODE = 0x300, // Bandwidth operation mode
297 MSR = 0x303, // Media Status register
298#define MSR_LINK_MASK ((1<<0)|(1<<1))
299#define MSR_LINK_MANAGED 2
300#define MSR_LINK_NONE 0
301#define MSR_LINK_SHIFT 0
302#define MSR_LINK_ADHOC 1
303#define MSR_LINK_MASTER 3
304#define MSR_LINK_ENEDCA (1<<4)
305 RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long
306#define RETRY_LIMIT_SHORT_SHIFT 8
307#define RETRY_LIMIT_LONG_SHIFT 0
308 TSFR = 0x308,
309 RRSR = 0x310, // Response Rate Set
310#define RRSR_RSC_OFFSET 21
311#define RRSR_SHORT_OFFSET 23
312#define RRSR_RSC_DUPLICATE 0x600000
313#define RRSR_RSC_LOWSUBCHNL 0x400000
314#define RRSR_RSC_UPSUBCHANL 0x200000
315#define RRSR_SHORT 0x800000
316#define RRSR_1M BIT0
317#define RRSR_2M BIT1
318#define RRSR_5_5M BIT2
319#define RRSR_11M BIT3
320#define RRSR_6M BIT4
321#define RRSR_9M BIT5
322#define RRSR_12M BIT6
323#define RRSR_18M BIT7
324#define RRSR_24M BIT8
325#define RRSR_36M BIT9
326#define RRSR_48M BIT10
327#define RRSR_54M BIT11
328#define RRSR_MCS0 BIT12
329#define RRSR_MCS1 BIT13
330#define RRSR_MCS2 BIT14
331#define RRSR_MCS3 BIT15
332#define RRSR_MCS4 BIT16
333#define RRSR_MCS5 BIT17
334#define RRSR_MCS6 BIT18
335#define RRSR_MCS7 BIT19
336#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not.
337 RATR0 = 0x320, // Rate Adaptive Table register1
338 UFWP = 0x318,
339 DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI
340//----------------------------------------------------------------------------
341// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
342//----------------------------------------------------------------------------
343//CCK
344#define RATR_1M 0x00000001
345#define RATR_2M 0x00000002
346#define RATR_55M 0x00000004
347#define RATR_11M 0x00000008
348//OFDM
349#define RATR_6M 0x00000010
350#define RATR_9M 0x00000020
351#define RATR_12M 0x00000040
352#define RATR_18M 0x00000080
353#define RATR_24M 0x00000100
354#define RATR_36M 0x00000200
355#define RATR_48M 0x00000400
356#define RATR_54M 0x00000800
357//MCS 1 Spatial Stream
358#define RATR_MCS0 0x00001000
359#define RATR_MCS1 0x00002000
360#define RATR_MCS2 0x00004000
361#define RATR_MCS3 0x00008000
362#define RATR_MCS4 0x00010000
363#define RATR_MCS5 0x00020000
364#define RATR_MCS6 0x00040000
365#define RATR_MCS7 0x00080000
366//MCS 2 Spatial Stream
367#define RATR_MCS8 0x00100000
368#define RATR_MCS9 0x00200000
369#define RATR_MCS10 0x00400000
370#define RATR_MCS11 0x00800000
371#define RATR_MCS12 0x01000000
372#define RATR_MCS13 0x02000000
373#define RATR_MCS14 0x04000000
374#define RATR_MCS15 0x08000000
375// ALL CCK Rate
376#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
377#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
378 |RATR_36M|RATR_48M|RATR_54M
379#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
380 RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7
381#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
382 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
383
384 MCS_TXAGC = 0x340, // MCS AGC
385 CCK_TXAGC = 0x348, // CCK AGC
386// ISR = 0x350, // Interrupt Status Register
387// IMR = 0x354, // Interrupt Mask Register
388// IMR_POLL = 0x360,
389 MacBlkCtrl = 0x403, // Mac block on/off control register
390
391 EPROM_CMD = 0xfe58,
392#define Cmd9346CR_9356SEL (1<<4)
393#define EPROM_CMD_RESERVED_MASK (1<<5)
394#define EPROM_CMD_OPERATING_MODE_SHIFT 6
395#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
396#define EPROM_CMD_CONFIG 0x3
397#define EPROM_CMD_NORMAL 0
398#define EPROM_CMD_LOAD 1
399#define EPROM_CMD_PROGRAM 2
400#define EPROM_CS_SHIFT 3
401#define EPROM_CK_SHIFT 2
402#define EPROM_W_SHIFT 1
403#define EPROM_R_SHIFT 0
404 MAC0 = 0x000,
405 MAC1 = 0x001,
406 MAC2 = 0x002,
407 MAC3 = 0x003,
408 MAC4 = 0x004,
409 MAC5 = 0x005,
410
411#if 0
412/* 0x0006 - 0x0007 - reserved */
413 RXFIFOCOUNT = 0x010,
414 TXFIFOCOUNT = 0x012,
415 BQREQ = 0x013,
416/* 0x0010 - 0x0017 - reserved */
417 TSFTR = 0x018,
418 TLPDA = 0x020,
419 TNPDA = 0x024,
420 THPDA = 0x028,
421 BSSID = 0x02E,
422 RESP_RATE = 0x034,
423 CMD = 0x037,
424#define CMD_RST_SHIFT 4
425#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7))
426#define CMD_RX_ENABLE_SHIFT 3
427#define CMD_TX_ENABLE_SHIFT 2
428#define CR_RST ((1<< 4))
429#define CR_RE ((1<< 3))
430#define CR_TE ((1<< 2))
431#define CR_MulRW ((1<< 0))
432
433 INTA_MASK = 0x03c,
434 INTA = 0x03e,
435#define INTA_TXOVERFLOW (1<<15)
436#define INTA_TIMEOUT (1<<14)
437#define INTA_BEACONTIMEOUT (1<<13)
438#define INTA_ATIM (1<<12)
439#define INTA_BEACONDESCERR (1<<11)
440#define INTA_BEACONDESCOK (1<<10)
441#define INTA_HIPRIORITYDESCERR (1<<9)
442#define INTA_HIPRIORITYDESCOK (1<<8)
443#define INTA_NORMPRIORITYDESCERR (1<<7)
444#define INTA_NORMPRIORITYDESCOK (1<<6)
445#define INTA_RXOVERFLOW (1<<5)
446#define INTA_RXDESCERR (1<<4)
447#define INTA_LOWPRIORITYDESCERR (1<<3)
448#define INTA_LOWPRIORITYDESCOK (1<<2)
449#define INTA_RXCRCERR (1<<1)
450#define INTA_RXOK (1)
451 TX_CONF = 0x040,
452#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
453#define TX_LOOPBACK_SHIFT 17
454#define TX_LOOPBACK_MAC 1
455#define TX_LOOPBACK_BASEBAND 2
456#define TX_LOOPBACK_NONE 0
457#define TX_LOOPBACK_CONTINUE 3
458#define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
459#define TX_LRLRETRY_SHIFT 0
460#define TX_SRLRETRY_SHIFT 8
461#define TX_NOICV_SHIFT 19
462#define TX_NOCRC_SHIFT 16
463#define TCR_DurProcMode ((1<<30))
464#define TCR_DISReqQsize ((1<<28))
465#define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25))
466#define TCR_HWVERID_SHIFT 25
467#define TCR_SWPLCPLEN ((1<<24))
468#define TCR_PLCP_LEN TCR_SAT // rtl8180
469#define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21))
470#define TCR_MXDMA_1024 6
471#define TCR_MXDMA_2048 7
472#define TCR_MXDMA_SHIFT 21
473#define TCR_DISCW ((1<<20))
474#define TCR_ICV ((1<<19))
475#define TCR_LBK ((1<<18)|(1<<17))
476#define TCR_LBK1 ((1<<18))
477#define TCR_LBK0 ((1<<17))
478#define TCR_CRC ((1<<16))
479#define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
480#define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
481#define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185
482 RX_CONF = 0x044,
483#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
484(1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
485#define RX_CHECK_BSSID_SHIFT 23
486#define ACCEPT_PWR_FRAME_SHIFT 22
487#define ACCEPT_MNG_FRAME_SHIFT 20
488#define ACCEPT_CTL_FRAME_SHIFT 19
489#define ACCEPT_DATA_FRAME_SHIFT 18
490#define ACCEPT_ICVERR_FRAME_SHIFT 12
491#define ACCEPT_CRCERR_FRAME_SHIFT 5
492#define ACCEPT_BCAST_FRAME_SHIFT 3
493#define ACCEPT_MCAST_FRAME_SHIFT 2
494#define ACCEPT_ALLMAC_FRAME_SHIFT 0
495#define ACCEPT_NICMAC_FRAME_SHIFT 1
496#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
497#define RX_FIFO_THRESHOLD_SHIFT 13
498#define RX_FIFO_THRESHOLD_128 3
499#define RX_FIFO_THRESHOLD_256 4
500#define RX_FIFO_THRESHOLD_512 5
501#define RX_FIFO_THRESHOLD_1024 6
502#define RX_FIFO_THRESHOLD_NONE 7
503#define RX_AUTORESETPHY_SHIFT 28
504#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
505#define MAX_RX_DMA_2048 7
506#define MAX_RX_DMA_1024 6
507#define MAX_RX_DMA_SHIFT 10
508#define RCR_ONLYERLPKT ((1<<31))
509#define RCR_CS_SHIFT 29
510#define RCR_CS_MASK ((1<<30) | (1<<29))
511#define RCR_ENMARP ((1<<28))
512#define RCR_CBSSID ((1<<23))
513#define RCR_APWRMGT ((1<<22))
514#define RCR_ADD3 ((1<<21))
515#define RCR_AMF ((1<<20))
516#define RCR_ACF ((1<<19))
517#define RCR_ADF ((1<<18))
518#define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13))
519#define RCR_RXFTH2 ((1<<15))
520#define RCR_RXFTH1 ((1<<14))
521#define RCR_RXFTH0 ((1<<13))
522#define RCR_AICV ((1<<12))
523#define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8))
524#define RCR_MXDMA2 ((1<<10))
525#define RCR_MXDMA1 ((1<< 9))
526#define RCR_MXDMA0 ((1<< 8))
527#define RCR_9356SEL ((1<< 6))
528#define RCR_ACRC32 ((1<< 5))
529#define RCR_AB ((1<< 3))
530#define RCR_AM ((1<< 2))
531#define RCR_APM ((1<< 1))
532#define RCR_AAP ((1<< 0))
533 INT_TIMEOUT = 0x048,
534 TX_BEACON_RING_ADDR = 0x04c,
535 EPROM_CMD = 0x58,
536#define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4))
537#define EPROM_CMD_OPERATING_MODE_SHIFT 6
538#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
539#define EPROM_CMD_CONFIG 0x3
540#define EPROM_CMD_NORMAL 0
541#define EPROM_CMD_LOAD 1
542#define EPROM_CMD_PROGRAM 2
543#define EPROM_CS_SHIFT 3
544#define EPROM_CK_SHIFT 2
545#define EPROM_W_SHIFT 1
546#define EPROM_R_SHIFT 0
547 CONFIG0 = 0x051,
548#define CONFIG0_WEP104 ((1<<6))
549#define CONFIG0_LEDGPO_En ((1<<4))
550#define CONFIG0_Aux_Status ((1<<3))
551#define CONFIG0_GL ((1<<1)|(1<<0))
552#define CONFIG0_GL1 ((1<<1))
553#define CONFIG0_GL0 ((1<<0))
554 CONFIG1 = 0x052,
555#define CONFIG1_LEDS ((1<<7)|(1<<6))
556#define CONFIG1_LEDS1 ((1<<7))
557#define CONFIG1_LEDS0 ((1<<6))
558#define CONFIG1_LWACT ((1<<4))
559#define CONFIG1_MEMMAP ((1<<3))
560#define CONFIG1_IOMAP ((1<<2))
561#define CONFIG1_VPD ((1<<1))
562#define CONFIG1_PMEn ((1<<0))
563 CONFIG2 = 0x053,
564#define CONFIG2_LCK ((1<<7))
565#define CONFIG2_ANT ((1<<6))
566#define CONFIG2_DPS ((1<<3))
567#define CONFIG2_PAPE_sign ((1<<2))
568#define CONFIG2_PAPE_time ((1<<1)|(1<<0))
569#define CONFIG2_PAPE_time1 ((1<<1))
570#define CONFIG2_PAPE_time0 ((1<<0))
571 ANA_PARAM = 0x054,
572 CONFIG3 = 0x059,
573#define CONFIG3_GNTSel ((1<<7))
574#define CONFIG3_PARM_En ((1<<6))
575#define CONFIG3_Magic ((1<<5))
576#define CONFIG3_CardB_En ((1<<3))
577#define CONFIG3_CLKRUN_En ((1<<2))
578#define CONFIG3_FuncRegEn ((1<<1))
579#define CONFIG3_FBtbEn ((1<<0))
580#define CONFIG3_CLKRUN_SHIFT 2
581#define CONFIG3_ANAPARAM_W_SHIFT 6
582 CONFIG4 = 0x05a,
583#define CONFIG4_VCOPDN ((1<<7))
584#define CONFIG4_PWROFF ((1<<6))
585#define CONFIG4_PWRMGT ((1<<5))
586#define CONFIG4_LWPME ((1<<4))
587#define CONFIG4_LWPTN ((1<<2))
588#define CONFIG4_RFTYPE ((1<<1)|(1<<0))
589#define CONFIG4_RFTYPE1 ((1<<1))
590#define CONFIG4_RFTYPE0 ((1<<0))
591 TESTR = 0x05b,
592#define TFPC_AC 0x05C
593
594#define SCR 0x05F
595 PGSELECT = 0x05e,
596#define PGSELECT_PG_SHIFT 0
597 SECURITY = 0x05f,
598#define SECURITY_WEP_TX_ENABLE_SHIFT 1
599#define SECURITY_WEP_RX_ENABLE_SHIFT 0
600#define SECURITY_ENCRYP_104 1
601#define SECURITY_ENCRYP_SHIFT 4
602#define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5))
603 ANA_PARAM2 = 0x060,
604 BEACON_INTERVAL = 0x070,
605#define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \
606(1<<6)|(1<<7)|(1<<8)|(1<<9))
607 ATIM_WND = 0x072,
608#define ATIM_WND_MASK (0x01FF)
609 BCN_INTR_ITV = 0x074,
610#define BCN_INTR_ITV_MASK (0x01FF)
611 ATIM_INTR_ITV = 0x076,
612#define ATIM_INTR_ITV_MASK (0x01FF)
613 AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us.
614 PHY_ADR = 0x07c,
615 PHY_READ = 0x07e,
616 RFPinsOutput = 0x080,
617 RFPinsEnable = 0x082,
618
619//Page 0
620 RFPinsSelect = 0x084,
621#define SW_CONTROL_GPIO 0x400
622 RFPinsInput = 0x086,
623 RF_PARA = 0x088,
624 RF_TIMING = 0x08c,
625 GP_ENABLE = 0x090,
626 GPIO = 0x091,
627 TX_AGC_CTL = 0x09c,
628#define TX_AGC_CTL_PER_PACKET_TXAGC 0x01
629#define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0
630#define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1
631#define TX_AGC_CTL_FEEDBACK_ANT 2
632#define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02
633 OFDM_TXAGC = 0x09e,
634 ANTSEL = 0x09f,
635 WPA_CONFIG = 0x0b0,
636 SIFS = 0x0b4,
637 DIFS = 0x0b5,
638 SLOT = 0x0b6,
639 CW_CONF = 0x0bc,
640#define CW_CONF_PERPACKET_RETRY_LIMIT 0x02
641#define CW_CONF_PERPACKET_CW 0x01
642#define CW_CONF_PERPACKET_RETRY_SHIFT 1
643#define CW_CONF_PERPACKET_CW_SHIFT 0
644 CW_VAL = 0x0bd,
645 RATE_FALLBACK = 0x0be,
646#define MAX_RESP_RATE_SHIFT 4
647#define MIN_RESP_RATE_SHIFT 0
648#define RATE_FALLBACK_CTL_ENABLE 0x80
649#define RATE_FALLBACK_CTL_AUTO_STEP0 0x00
650 ACM_CONTROL = 0x0BF, // ACM Control Registe
651//----------------------------------------------------------------------------
652// 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte)
653//----------------------------------------------------------------------------
654#define VOQ_ACM_EN (0x01 << 7) //BIT7
655#define VIQ_ACM_EN (0x01 << 6) //BIT6
656#define BEQ_ACM_EN (0x01 << 5) //BIT5
657#define ACM_HW_EN (0x01 << 4) //BIT4
658#define TXOPSEL (0x01 << 3) //BIT3
659#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time
660#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time
661#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time
662 CONFIG5 = 0x0D8,
663#define CONFIG5_TX_FIFO_OK ((1<<7))
664#define CONFIG5_RX_FIFO_OK ((1<<6))
665#define CONFIG5_CALON ((1<<5))
666#define CONFIG5_EACPI ((1<<2))
667#define CONFIG5_LANWake ((1<<1))
668#define CONFIG5_PME_STS ((1<<0))
669 TX_DMA_POLLING = 0x0d9,
670#define TX_DMA_POLLING_BEACON_SHIFT 7
671#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
672#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
673#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
674#define TX_DMA_STOP_BEACON_SHIFT 3
675#define TX_DMA_STOP_HIPRIORITY_SHIFT 2
676#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1
677#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0
678 CWR = 0x0DC,
679 RetryCTR = 0x0DE,
680 INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3)
681 TID_AC_MAP = 0x0E8, // TID to AC Mapping Register
682 ANA_PARAM3 = 0x0EE,
683
684
685//page 1
686 Wakeup0 = 0x084,
687 Wakeup1 = 0x08C,
688 Wakeup2LD = 0x094,
689 Wakeup2HD = 0x09C,
690 Wakeup3LD = 0x0A4,
691 Wakeup3HD = 0x0AC,
692 Wakeup4LD = 0x0B4,
693 Wakeup4HD = 0x0BC,
694 CRC0 = 0x0C4,
695 CRC1 = 0x0C6,
696 CRC2 = 0x0C8,
697 CRC3 = 0x0CA,
698 CRC4 = 0x0CC,
699/* 0x00CE - 0x00D3 - reserved */
700
701 RFSW_CTRL = 0x272, // 0x272-0x273.
702
703//Reg Diff between rtl8187 and rtl8187B
704/**************************************************************************/
705 BRSR_8187 = 0x02C,
706 BRSR_8187B = 0x034,
707#define BRSR_BPLCP ((1<< 8))
708#define BRSR_MBR ((1<< 1)|(1<< 0))
709#define BRSR_MBR_8185 ((1<< 11)|(1<< 10)|(1<< 9)|(1<< 8)|(1<< 7)|(1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<< 1)|(1<< 0))
710#define BRSR_MBR0 ((1<< 0))
711#define BRSR_MBR1 ((1<< 1))
712
713/**************************************************************************/
714 EIFS_8187 = 0x035,
715 EIFS_8187B = 0x02D,
716
717/**************************************************************************/
718 FER = 0x0F0,
719 FEMR = 0x0F4,
720 FPSR = 0x0F8,
721 FFER = 0x0FC,
722
723 AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record
724 AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record
725 AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record
726 AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record
727 TALLY_SEL = 0x0fc,
728//----------------------------------------------------------------------------
729// 8187B AC_XX_PARAM bits
730//----------------------------------------------------------------------------
731#define AC_PARAM_TXOP_LIMIT_OFFSET 16
732#define AC_PARAM_ECW_MAX_OFFSET 12
733#define AC_PARAM_ECW_MIN_OFFSET 8
734#define AC_PARAM_AIFS_OFFSET 0
735
736#endif
737};
738//----------------------------------------------------------------------------
739// 818xB AnaParm & AnaParm2 Register
740//----------------------------------------------------------------------------
741//#define ANAPARM_ASIC_ON 0x45090658
742//#define ANAPARM2_ASIC_ON 0x727f3f52
743#define GPI 0x108
744#define GPO 0x109
745#define GPE 0x10a
746#endif
diff --git a/drivers/staging/rtl8192su/r8192U_pm.c b/drivers/staging/rtl8192su/r8192U_pm.c
new file mode 100644
index 00000000000..92c95aa3663
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_pm.c
@@ -0,0 +1,77 @@
1/*
2 Power management interface routines.
3 Written by Mariusz Matuszek.
4 This code is currently just a placeholder for later work and
5 does not do anything useful.
6
7 This is part of rtl8180 OpenSource driver.
8 Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
9 Released under the terms of GPL (General Public Licence)
10*/
11
12#ifdef CONFIG_RTL8192_PM
13#include "r8192U.h"
14#include "r8192U_pm.h"
15
16/*****************************************************************************/
17int rtl8192U_save_state (struct pci_dev *dev, u32 state)
18{
19 printk(KERN_NOTICE "r8192U save state call (state %u).\n", state);
20 return(-EAGAIN);
21}
22
23int rtl8192U_suspend(struct usb_interface *intf, pm_message_t state)
24{
25#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
26 struct net_device *dev = usb_get_intfdata(intf);
27#else
28 //struct net_device *dev = (struct net_device *)ptr;
29#endif
30 RT_TRACE(COMP_POWER, "============> r8192U suspend call.\n");
31
32 if(dev) {
33 if (!netif_running(dev)) {
34 printk(KERN_WARNING "netif not running, go out suspend function\n");
35 return 0;
36 }
37
38 dev->stop(dev);
39 mdelay(10);
40
41 netif_device_detach(dev);
42 }
43
44 return 0;
45}
46
47int rtl8192U_resume (struct usb_interface *intf)
48{
49#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
50 struct net_device *dev = usb_get_intfdata(intf);
51#else
52 //struct net_device *dev = (struct net_device *)ptr;
53#endif
54
55 RT_TRACE(COMP_POWER, "================>r8192U resume call.");
56
57 if(dev) {
58 if (!netif_running(dev)){
59 printk(KERN_WARNING "netif not running, go out resume function\n");
60 return 0;
61 }
62
63 netif_device_attach(dev);
64 dev->open(dev);
65 }
66
67 return 0;
68}
69
70int rtl8192U_enable_wake (struct pci_dev *dev, u32 state, int enable)
71{
72 printk(KERN_NOTICE "r8192U enable wake call (state %u, enable %d).\n",
73 state, enable);
74 return(-EAGAIN);
75}
76
77#endif //CONFIG_RTL8192_PM
diff --git a/drivers/staging/rtl8192su/r8192U_pm.h b/drivers/staging/rtl8192su/r8192U_pm.h
new file mode 100644
index 00000000000..ab025d64f5e
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_pm.h
@@ -0,0 +1,27 @@
1/*
2 Power management interface routines.
3 Written by Mariusz Matuszek.
4 This code is currently just a placeholder for later work and
5 does not do anything useful.
6
7 This is part of rtl8180 OpenSource driver.
8 Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
9 Released under the terms of GPL (General Public Licence)
10
11*/
12
13#ifdef CONFIG_RTL8192_PM
14
15#ifndef R8192_PM_H
16#define R8192_PM_H
17
18#include <linux/types.h>
19#include <linux/usb.h>
20
21int rtl8192U_save_tate (struct pci_dev *dev, u32 state);
22int rtl8192U_suspend(struct usb_interface *intf, pm_message_t state);
23int rtl8192U_resume (struct usb_interface *intf);
24int rtl8192U_enable_wake (struct pci_dev *dev, u32 state, int enable);
25
26#endif //R8192U_PM_H
27#endif // CONFIG_RTL8192_PM
diff --git a/drivers/staging/rtl8192su/r8192U_wx.c b/drivers/staging/rtl8192su/r8192U_wx.c
new file mode 100644
index 00000000000..f9eafb16dbb
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_wx.c
@@ -0,0 +1,1350 @@
1/*
2 This file contains wireless extension handlers.
3
4 This is part of rtl8180 OpenSource driver.
5 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
6 Released under the terms of GPL (General Public Licence)
7
8 Parts of this driver are based on the GPL part
9 of the official realtek driver.
10
11 Parts of this driver are based on the rtl8180 driver skeleton
12 from Patric Schenke & Andres Salomon.
13
14 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
15
16 We want to tanks the Authors of those projects and the Ndiswrapper
17 project Authors.
18*/
19
20#ifdef RTL8192SU
21#include <linux/string.h>
22#include "r8192U.h"
23#include "r8192S_hw.h"
24#else
25#include <linux/string.h>
26#include "r8192U.h"
27#include "r8192U_hw.h"
28#endif
29
30#ifdef ENABLE_DOT11D
31#include "dot11d.h"
32#endif
33
34#define RATE_COUNT 12
35u32 rtl8180_rates[] = {1000000,2000000,5500000,11000000,
36 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000};
37
38
39#ifndef ENETDOWN
40#define ENETDOWN 1
41#endif
42
43static int r8192_wx_get_freq(struct net_device *dev,
44 struct iw_request_info *a,
45 union iwreq_data *wrqu, char *b)
46{
47 struct r8192_priv *priv = ieee80211_priv(dev);
48
49 return ieee80211_wx_get_freq(priv->ieee80211,a,wrqu,b);
50}
51
52
53#if 0
54
55static int r8192_wx_set_beaconinterval(struct net_device *dev, struct iw_request_info *aa,
56 union iwreq_data *wrqu, char *b)
57{
58 int *parms = (int *)b;
59 int bi = parms[0];
60
61 struct r8192_priv *priv = ieee80211_priv(dev);
62
63 down(&priv->wx_sem);
64 DMESG("setting beacon interval to %x",bi);
65
66 priv->ieee80211->beacon_interval=bi;
67 rtl8180_commit(dev);
68 up(&priv->wx_sem);
69
70 return 0;
71}
72
73
74static int r8192_wx_set_forceassociate(struct net_device *dev, struct iw_request_info *aa,
75 union iwreq_data *wrqu, char *extra)
76{
77 struct r8192_priv *priv=ieee80211_priv(dev);
78 int *parms = (int *)extra;
79
80 priv->ieee80211->force_associate = (parms[0] > 0);
81
82
83 return 0;
84}
85
86#endif
87static int r8192_wx_get_mode(struct net_device *dev, struct iw_request_info *a,
88 union iwreq_data *wrqu, char *b)
89{
90 struct r8192_priv *priv=ieee80211_priv(dev);
91
92 return ieee80211_wx_get_mode(priv->ieee80211,a,wrqu,b);
93}
94
95
96
97static int r8192_wx_get_rate(struct net_device *dev,
98 struct iw_request_info *info,
99 union iwreq_data *wrqu, char *extra)
100{
101 struct r8192_priv *priv = ieee80211_priv(dev);
102 return ieee80211_wx_get_rate(priv->ieee80211,info,wrqu,extra);
103}
104
105
106
107static int r8192_wx_set_rate(struct net_device *dev,
108 struct iw_request_info *info,
109 union iwreq_data *wrqu, char *extra)
110{
111 int ret;
112 struct r8192_priv *priv = ieee80211_priv(dev);
113
114 down(&priv->wx_sem);
115
116 ret = ieee80211_wx_set_rate(priv->ieee80211,info,wrqu,extra);
117
118 up(&priv->wx_sem);
119
120 return ret;
121}
122
123
124static int r8192_wx_set_rts(struct net_device *dev,
125 struct iw_request_info *info,
126 union iwreq_data *wrqu, char *extra)
127{
128 int ret;
129 struct r8192_priv *priv = ieee80211_priv(dev);
130
131 down(&priv->wx_sem);
132
133 ret = ieee80211_wx_set_rts(priv->ieee80211,info,wrqu,extra);
134
135 up(&priv->wx_sem);
136
137 return ret;
138}
139
140static int r8192_wx_get_rts(struct net_device *dev,
141 struct iw_request_info *info,
142 union iwreq_data *wrqu, char *extra)
143{
144 struct r8192_priv *priv = ieee80211_priv(dev);
145 return ieee80211_wx_get_rts(priv->ieee80211,info,wrqu,extra);
146}
147
148static int r8192_wx_set_power(struct net_device *dev,
149 struct iw_request_info *info,
150 union iwreq_data *wrqu, char *extra)
151{
152 int ret;
153 struct r8192_priv *priv = ieee80211_priv(dev);
154
155 down(&priv->wx_sem);
156
157 ret = ieee80211_wx_set_power(priv->ieee80211,info,wrqu,extra);
158
159 up(&priv->wx_sem);
160
161 return ret;
162}
163
164static int r8192_wx_get_power(struct net_device *dev,
165 struct iw_request_info *info,
166 union iwreq_data *wrqu, char *extra)
167{
168 struct r8192_priv *priv = ieee80211_priv(dev);
169 return ieee80211_wx_get_power(priv->ieee80211,info,wrqu,extra);
170}
171
172#ifdef JOHN_IOCTL
173u16 read_rtl8225(struct net_device *dev, u8 addr);
174void write_rtl8225(struct net_device *dev, u8 adr, u16 data);
175u32 john_read_rtl8225(struct net_device *dev, u8 adr);
176void _write_rtl8225(struct net_device *dev, u8 adr, u16 data);
177
178static int r8192_wx_read_regs(struct net_device *dev,
179 struct iw_request_info *info,
180 union iwreq_data *wrqu, char *extra)
181{
182 struct r8192_priv *priv = ieee80211_priv(dev);
183 u8 addr;
184 u16 data1;
185
186 down(&priv->wx_sem);
187
188
189 get_user(addr,(u8*)wrqu->data.pointer);
190 data1 = read_rtl8225(dev, addr);
191 wrqu->data.length = data1;
192
193 up(&priv->wx_sem);
194 return 0;
195
196}
197
198static int r8192_wx_write_regs(struct net_device *dev,
199 struct iw_request_info *info,
200 union iwreq_data *wrqu, char *extra)
201{
202 struct r8192_priv *priv = ieee80211_priv(dev);
203 u8 addr;
204
205 down(&priv->wx_sem);
206
207 get_user(addr, (u8*)wrqu->data.pointer);
208 write_rtl8225(dev, addr, wrqu->data.length);
209
210 up(&priv->wx_sem);
211 return 0;
212
213}
214
215void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data);
216u8 rtl8187_read_phy(struct net_device *dev,u8 adr, u32 data);
217
218static int r8192_wx_read_bb(struct net_device *dev,
219 struct iw_request_info *info,
220 union iwreq_data *wrqu, char *extra)
221{
222 struct r8192_priv *priv = ieee80211_priv(dev);
223 u8 databb;
224#if 0
225 int i;
226 for(i=0;i<12;i++) printk("%8x\n", read_cam(dev, i) );
227#endif
228
229 down(&priv->wx_sem);
230
231 databb = rtl8187_read_phy(dev, (u8)wrqu->data.length, 0x00000000);
232 wrqu->data.length = databb;
233
234 up(&priv->wx_sem);
235 return 0;
236}
237
238void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data);
239static int r8192_wx_write_bb(struct net_device *dev,
240 struct iw_request_info *info,
241 union iwreq_data *wrqu, char *extra)
242{
243 struct r8192_priv *priv = ieee80211_priv(dev);
244 u8 databb;
245
246 down(&priv->wx_sem);
247
248 get_user(databb, (u8*)wrqu->data.pointer);
249 rtl8187_write_phy(dev, wrqu->data.length, databb);
250
251 up(&priv->wx_sem);
252 return 0;
253
254}
255
256
257static int r8192_wx_write_nicb(struct net_device *dev,
258 struct iw_request_info *info,
259 union iwreq_data *wrqu, char *extra)
260{
261 struct r8192_priv *priv = ieee80211_priv(dev);
262 u32 addr;
263
264 down(&priv->wx_sem);
265
266 get_user(addr, (u32*)wrqu->data.pointer);
267 write_nic_byte(dev, addr, wrqu->data.length);
268
269 up(&priv->wx_sem);
270 return 0;
271
272}
273static int r8192_wx_read_nicb(struct net_device *dev,
274 struct iw_request_info *info,
275 union iwreq_data *wrqu, char *extra)
276{
277 struct r8192_priv *priv = ieee80211_priv(dev);
278 u32 addr;
279 u16 data1;
280
281 down(&priv->wx_sem);
282
283 get_user(addr,(u32*)wrqu->data.pointer);
284 data1 = read_nic_byte(dev, addr);
285 wrqu->data.length = data1;
286
287 up(&priv->wx_sem);
288 return 0;
289}
290
291static int r8192_wx_get_ap_status(struct net_device *dev,
292 struct iw_request_info *info,
293 union iwreq_data *wrqu, char *extra)
294{
295 struct r8192_priv *priv = ieee80211_priv(dev);
296 struct ieee80211_device *ieee = priv->ieee80211;
297 struct ieee80211_network *target;
298 int name_len;
299
300 down(&priv->wx_sem);
301
302 //count the length of input ssid
303 for(name_len=0 ; ((char*)wrqu->data.pointer)[name_len]!='\0' ; name_len++);
304
305 //search for the correspoding info which is received
306 list_for_each_entry(target, &ieee->network_list, list) {
307 if ( (target->ssid_len == name_len) &&
308 (strncmp(target->ssid, (char*)wrqu->data.pointer, name_len)==0)){
309 if(target->wpa_ie_len>0 || target->rsn_ie_len>0 )
310 //set flags=1 to indicate this ap is WPA
311 wrqu->data.flags = 1;
312 else wrqu->data.flags = 0;
313
314
315 break;
316 }
317 }
318
319 up(&priv->wx_sem);
320 return 0;
321}
322
323
324
325#endif
326#if 0
327static int r8192_wx_null(struct net_device *dev,
328 struct iw_request_info *info,
329 union iwreq_data *wrqu, char *extra)
330{
331 return 0;
332}
333#endif
334static int r8192_wx_force_reset(struct net_device *dev,
335 struct iw_request_info *info,
336 union iwreq_data *wrqu, char *extra)
337{
338 struct r8192_priv *priv = ieee80211_priv(dev);
339
340 down(&priv->wx_sem);
341
342 printk("%s(): force reset ! extra is %d\n",__FUNCTION__, *extra);
343 priv->force_reset = *extra;
344 up(&priv->wx_sem);
345 return 0;
346
347}
348
349#ifdef RTL8192SU
350static int r8191su_wx_get_firm_version(struct net_device *dev,
351 struct iw_request_info *info,
352 struct iw_param *wrqu, char *extra)
353{
354 struct r8192_priv *priv = ieee80211_priv(dev);
355 u16 firmware_version;
356
357 down(&priv->wx_sem);
358 firmware_version = priv->pFirmware->FirmwareVersion;
359 wrqu->value = firmware_version;
360 wrqu->fixed = 1;
361
362 up(&priv->wx_sem);
363 return 0;
364}
365#endif
366
367
368
369static int r8192_wx_set_rawtx(struct net_device *dev,
370 struct iw_request_info *info,
371 union iwreq_data *wrqu, char *extra)
372{
373 struct r8192_priv *priv = ieee80211_priv(dev);
374 int ret;
375
376 down(&priv->wx_sem);
377
378 ret = ieee80211_wx_set_rawtx(priv->ieee80211, info, wrqu, extra);
379
380 up(&priv->wx_sem);
381
382 return ret;
383
384}
385
386static int r8192_wx_set_crcmon(struct net_device *dev,
387 struct iw_request_info *info,
388 union iwreq_data *wrqu, char *extra)
389{
390 struct r8192_priv *priv = ieee80211_priv(dev);
391 int *parms = (int *)extra;
392 int enable = (parms[0] > 0);
393 short prev = priv->crcmon;
394
395 down(&priv->wx_sem);
396
397 if(enable)
398 priv->crcmon=1;
399 else
400 priv->crcmon=0;
401
402 DMESG("bad CRC in monitor mode are %s",
403 priv->crcmon ? "accepted" : "rejected");
404
405 if(prev != priv->crcmon && priv->up){
406 //rtl8180_down(dev);
407 //rtl8180_up(dev);
408 }
409
410 up(&priv->wx_sem);
411
412 return 0;
413}
414
415static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a,
416 union iwreq_data *wrqu, char *b)
417{
418 struct r8192_priv *priv = ieee80211_priv(dev);
419 int ret;
420 down(&priv->wx_sem);
421
422 ret = ieee80211_wx_set_mode(priv->ieee80211,a,wrqu,b);
423
424 rtl8192_set_rxconf(dev);
425
426 up(&priv->wx_sem);
427 return ret;
428}
429
430struct iw_range_with_scan_capa
431{
432 /* Informative stuff (to choose between different interface) */
433 __u32 throughput; /* To give an idea... */
434 /* In theory this value should be the maximum benchmarked
435 * TCP/IP throughput, because with most of these devices the
436 * bit rate is meaningless (overhead an co) to estimate how
437 * fast the connection will go and pick the fastest one.
438 * I suggest people to play with Netperf or any benchmark...
439 */
440
441 /* NWID (or domain id) */
442 __u32 min_nwid; /* Minimal NWID we are able to set */
443 __u32 max_nwid; /* Maximal NWID we are able to set */
444
445 /* Old Frequency (backward compat - moved lower ) */
446 __u16 old_num_channels;
447 __u8 old_num_frequency;
448
449 /* Scan capabilities */
450 __u8 scan_capa;
451};
452static int rtl8180_wx_get_range(struct net_device *dev,
453 struct iw_request_info *info,
454 union iwreq_data *wrqu, char *extra)
455{
456 struct iw_range *range = (struct iw_range *)extra;
457 struct iw_range_with_scan_capa* tmp = (struct iw_range_with_scan_capa*)range;
458 struct r8192_priv *priv = ieee80211_priv(dev);
459 u16 val;
460 int i;
461
462 wrqu->data.length = sizeof(*range);
463 memset(range, 0, sizeof(*range));
464
465 /* Let's try to keep this struct in the same order as in
466 * linux/include/wireless.h
467 */
468
469 /* TODO: See what values we can set, and remove the ones we can't
470 * set, or fill them with some default data.
471 */
472
473 /* ~5 Mb/s real (802.11b) */
474 range->throughput = 5 * 1000 * 1000;
475
476 // TODO: Not used in 802.11b?
477// range->min_nwid; /* Minimal NWID we are able to set */
478 // TODO: Not used in 802.11b?
479// range->max_nwid; /* Maximal NWID we are able to set */
480
481 /* Old Frequency (backward compat - moved lower ) */
482// range->old_num_channels;
483// range->old_num_frequency;
484// range->old_freq[6]; /* Filler to keep "version" at the same offset */
485 if(priv->rf_set_sens != NULL)
486 range->sensitivity = priv->max_sens; /* signal level threshold range */
487
488 range->max_qual.qual = 100;
489 /* TODO: Find real max RSSI and stick here */
490 range->max_qual.level = 0;
491 range->max_qual.noise = -98;
492 range->max_qual.updated = 7; /* Updated all three */
493
494 range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */
495 /* TODO: Find real 'good' to 'bad' threshol value for RSSI */
496 range->avg_qual.level = 20 + -98;
497 range->avg_qual.noise = 0;
498 range->avg_qual.updated = 7; /* Updated all three */
499
500 range->num_bitrates = RATE_COUNT;
501
502 for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) {
503 range->bitrate[i] = rtl8180_rates[i];
504 }
505
506 range->min_frag = MIN_FRAG_THRESHOLD;
507 range->max_frag = MAX_FRAG_THRESHOLD;
508
509 range->min_pmp=0;
510 range->max_pmp = 5000000;
511 range->min_pmt = 0;
512 range->max_pmt = 65535*1000;
513 range->pmp_flags = IW_POWER_PERIOD;
514 range->pmt_flags = IW_POWER_TIMEOUT;
515 range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R;
516
517 range->we_version_compiled = WIRELESS_EXT;
518 range->we_version_source = 16;
519
520// range->retry_capa; /* What retry options are supported */
521// range->retry_flags; /* How to decode max/min retry limit */
522// range->r_time_flags; /* How to decode max/min retry life */
523// range->min_retry; /* Minimal number of retries */
524// range->max_retry; /* Maximal number of retries */
525// range->min_r_time; /* Minimal retry lifetime */
526// range->max_r_time; /* Maximal retry lifetime */
527
528
529 for (i = 0, val = 0; i < 14; i++) {
530
531 // Include only legal frequencies for some countries
532#ifdef ENABLE_DOT11D
533 if ((GET_DOT11D_INFO(priv->ieee80211)->channel_map)[i+1]) {
534#else
535 if ((priv->ieee80211->channel_map)[i+1]) {
536#endif
537 range->freq[val].i = i + 1;
538 range->freq[val].m = ieee80211_wlan_frequencies[i] * 100000;
539 range->freq[val].e = 1;
540 val++;
541 } else {
542 // FIXME: do we need to set anything for channels
543 // we don't use ?
544 }
545
546 if (val == IW_MAX_FREQUENCIES)
547 break;
548 }
549 range->num_frequency = val;
550 range->num_channels = val;
551#if WIRELESS_EXT > 17
552 range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2|
553 IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP;
554#endif
555 tmp->scan_capa = 0x01;
556 return 0;
557}
558
559
560static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a,
561 union iwreq_data *wrqu, char *b)
562{
563 struct r8192_priv *priv = ieee80211_priv(dev);
564 struct ieee80211_device* ieee = priv->ieee80211;
565 int ret = 0;
566
567 if(!priv->up) return -ENETDOWN;
568
569 if (priv->ieee80211->LinkDetectInfo.bBusyTraffic == true)
570 return -EAGAIN;
571#if WIRELESS_EXT > 17
572 if (wrqu->data.flags & IW_SCAN_THIS_ESSID)
573 {
574 struct iw_scan_req* req = (struct iw_scan_req*)b;
575 if (req->essid_len)
576 {
577 //printk("==**&*&*&**===>scan set ssid:%s\n", req->essid);
578 ieee->current_network.ssid_len = req->essid_len;
579 memcpy(ieee->current_network.ssid, req->essid, req->essid_len);
580 //printk("=====>network ssid:%s\n", ieee->current_network.ssid);
581 }
582 }
583#endif
584
585 down(&priv->wx_sem);
586 if(priv->ieee80211->state != IEEE80211_LINKED){
587 priv->ieee80211->scanning = 0;
588 ieee80211_softmac_scan_syncro(priv->ieee80211);
589 ret = 0;
590 }
591 else
592 ret = ieee80211_wx_set_scan(priv->ieee80211,a,wrqu,b);
593 up(&priv->wx_sem);
594 return ret;
595}
596
597
598static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a,
599 union iwreq_data *wrqu, char *b)
600{
601
602 int ret;
603 struct r8192_priv *priv = ieee80211_priv(dev);
604
605 if(!priv->up) return -ENETDOWN;
606
607 down(&priv->wx_sem);
608
609 ret = ieee80211_wx_get_scan(priv->ieee80211,a,wrqu,b);
610
611 up(&priv->wx_sem);
612
613 return ret;
614}
615
616static int r8192_wx_set_essid(struct net_device *dev,
617 struct iw_request_info *a,
618 union iwreq_data *wrqu, char *b)
619{
620 struct r8192_priv *priv = ieee80211_priv(dev);
621 int ret;
622 down(&priv->wx_sem);
623
624 ret = ieee80211_wx_set_essid(priv->ieee80211,a,wrqu,b);
625
626 up(&priv->wx_sem);
627
628 return ret;
629}
630
631
632
633
634static int r8192_wx_get_essid(struct net_device *dev,
635 struct iw_request_info *a,
636 union iwreq_data *wrqu, char *b)
637{
638 int ret;
639 struct r8192_priv *priv = ieee80211_priv(dev);
640
641 down(&priv->wx_sem);
642
643 ret = ieee80211_wx_get_essid(priv->ieee80211, a, wrqu, b);
644
645 up(&priv->wx_sem);
646
647 return ret;
648}
649
650
651static int r8192_wx_set_freq(struct net_device *dev, struct iw_request_info *a,
652 union iwreq_data *wrqu, char *b)
653{
654 int ret;
655 struct r8192_priv *priv = ieee80211_priv(dev);
656
657 down(&priv->wx_sem);
658
659 ret = ieee80211_wx_set_freq(priv->ieee80211, a, wrqu, b);
660
661 up(&priv->wx_sem);
662 return ret;
663}
664
665static int r8192_wx_get_name(struct net_device *dev,
666 struct iw_request_info *info,
667 union iwreq_data *wrqu, char *extra)
668{
669 struct r8192_priv *priv = ieee80211_priv(dev);
670 return ieee80211_wx_get_name(priv->ieee80211, info, wrqu, extra);
671}
672
673
674static int r8192_wx_set_frag(struct net_device *dev,
675 struct iw_request_info *info,
676 union iwreq_data *wrqu, char *extra)
677{
678 struct r8192_priv *priv = ieee80211_priv(dev);
679
680 if (wrqu->frag.disabled)
681 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
682 else {
683 if (wrqu->frag.value < MIN_FRAG_THRESHOLD ||
684 wrqu->frag.value > MAX_FRAG_THRESHOLD)
685 return -EINVAL;
686
687 priv->ieee80211->fts = wrqu->frag.value & ~0x1;
688 }
689
690 return 0;
691}
692
693
694static int r8192_wx_get_frag(struct net_device *dev,
695 struct iw_request_info *info,
696 union iwreq_data *wrqu, char *extra)
697{
698 struct r8192_priv *priv = ieee80211_priv(dev);
699
700 wrqu->frag.value = priv->ieee80211->fts;
701 wrqu->frag.fixed = 0; /* no auto select */
702 wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD);
703
704 return 0;
705}
706
707
708static int r8192_wx_set_wap(struct net_device *dev,
709 struct iw_request_info *info,
710 union iwreq_data *awrq,
711 char *extra)
712{
713
714 int ret;
715 struct r8192_priv *priv = ieee80211_priv(dev);
716// struct sockaddr *temp = (struct sockaddr *)awrq;
717 down(&priv->wx_sem);
718
719 ret = ieee80211_wx_set_wap(priv->ieee80211,info,awrq,extra);
720
721 up(&priv->wx_sem);
722
723 return ret;
724
725}
726
727
728static int r8192_wx_get_wap(struct net_device *dev,
729 struct iw_request_info *info,
730 union iwreq_data *wrqu, char *extra)
731{
732 struct r8192_priv *priv = ieee80211_priv(dev);
733
734 return ieee80211_wx_get_wap(priv->ieee80211,info,wrqu,extra);
735}
736
737
738static int r8192_wx_get_enc(struct net_device *dev,
739 struct iw_request_info *info,
740 union iwreq_data *wrqu, char *key)
741{
742 struct r8192_priv *priv = ieee80211_priv(dev);
743
744 return ieee80211_wx_get_encode(priv->ieee80211, info, wrqu, key);
745}
746
747static int r8192_wx_set_enc(struct net_device *dev,
748 struct iw_request_info *info,
749 union iwreq_data *wrqu, char *key)
750{
751 struct r8192_priv *priv = ieee80211_priv(dev);
752 struct ieee80211_device *ieee = priv->ieee80211;
753 int ret;
754
755 //u32 TargetContent;
756 u32 hwkey[4]={0,0,0,0};
757 u8 mask=0xff;
758 u32 key_idx=0;
759 //u8 broadcast_addr[6] ={ 0xff,0xff,0xff,0xff,0xff,0xff};
760 u8 zero_addr[4][6] ={ {0x00,0x00,0x00,0x00,0x00,0x00},
761 {0x00,0x00,0x00,0x00,0x00,0x01},
762 {0x00,0x00,0x00,0x00,0x00,0x02},
763 {0x00,0x00,0x00,0x00,0x00,0x03} };
764 int i;
765
766 if(!priv->up) return -ENETDOWN;
767
768 down(&priv->wx_sem);
769
770 RT_TRACE(COMP_SEC, "Setting SW wep key");
771 ret = ieee80211_wx_set_encode(priv->ieee80211,info,wrqu,key);
772
773 up(&priv->wx_sem);
774
775
776
777 //sometimes, the length is zero while we do not type key value
778 if(wrqu->encoding.length!=0){
779
780 for(i=0 ; i<4 ; i++){
781 hwkey[i] |= key[4*i+0]&mask;
782 if(i==1&&(4*i+1)==wrqu->encoding.length) mask=0x00;
783 if(i==3&&(4*i+1)==wrqu->encoding.length) mask=0x00;
784 hwkey[i] |= (key[4*i+1]&mask)<<8;
785 hwkey[i] |= (key[4*i+2]&mask)<<16;
786 hwkey[i] |= (key[4*i+3]&mask)<<24;
787 }
788
789 #define CONF_WEP40 0x4
790 #define CONF_WEP104 0x14
791
792 switch(wrqu->encoding.flags & IW_ENCODE_INDEX){
793 case 0: key_idx = ieee->tx_keyidx; break;
794 case 1: key_idx = 0; break;
795 case 2: key_idx = 1; break;
796 case 3: key_idx = 2; break;
797 case 4: key_idx = 3; break;
798 default: break;
799 }
800
801 if(wrqu->encoding.length==0x5){
802 ieee->pairwise_key_type = KEY_TYPE_WEP40;
803 EnableHWSecurityConfig8192(dev);
804
805 setKey( dev,
806 key_idx, //EntryNo
807 key_idx, //KeyIndex
808 KEY_TYPE_WEP40, //KeyType
809 zero_addr[key_idx],
810 0, //DefaultKey
811 hwkey); //KeyContent
812
813 }
814
815 else if(wrqu->encoding.length==0xd){
816 ieee->pairwise_key_type = KEY_TYPE_WEP104;
817 EnableHWSecurityConfig8192(dev);
818
819 setKey( dev,
820 key_idx, //EntryNo
821 key_idx, //KeyIndex
822 KEY_TYPE_WEP104, //KeyType
823 zero_addr[key_idx],
824 0, //DefaultKey
825 hwkey); //KeyContent
826
827 }
828 else printk("wrong type in WEP, not WEP40 and WEP104\n");
829
830 }
831
832 return ret;
833}
834
835
836static int r8192_wx_set_scan_type(struct net_device *dev, struct iw_request_info *aa, union
837 iwreq_data *wrqu, char *p){
838
839 struct r8192_priv *priv = ieee80211_priv(dev);
840 int *parms=(int*)p;
841 int mode=parms[0];
842
843 priv->ieee80211->active_scan = mode;
844
845 return 1;
846}
847
848
849
850static int r8192_wx_set_retry(struct net_device *dev,
851 struct iw_request_info *info,
852 union iwreq_data *wrqu, char *extra)
853{
854 struct r8192_priv *priv = ieee80211_priv(dev);
855 int err = 0;
856
857 down(&priv->wx_sem);
858
859 if (wrqu->retry.flags & IW_RETRY_LIFETIME ||
860 wrqu->retry.disabled){
861 err = -EINVAL;
862 goto exit;
863 }
864 if (!(wrqu->retry.flags & IW_RETRY_LIMIT)){
865 err = -EINVAL;
866 goto exit;
867 }
868
869 if(wrqu->retry.value > R8180_MAX_RETRY){
870 err= -EINVAL;
871 goto exit;
872 }
873 if (wrqu->retry.flags & IW_RETRY_MAX) {
874 priv->retry_rts = wrqu->retry.value;
875 DMESG("Setting retry for RTS/CTS data to %d", wrqu->retry.value);
876
877 }else {
878 priv->retry_data = wrqu->retry.value;
879 DMESG("Setting retry for non RTS/CTS data to %d", wrqu->retry.value);
880 }
881
882 /* FIXME !
883 * We might try to write directly the TX config register
884 * or to restart just the (R)TX process.
885 * I'm unsure if whole reset is really needed
886 */
887
888 rtl8192_commit(dev);
889 /*
890 if(priv->up){
891 rtl8180_rtx_disable(dev);
892 rtl8180_rx_enable(dev);
893 rtl8180_tx_enable(dev);
894
895 }
896 */
897exit:
898 up(&priv->wx_sem);
899
900 return err;
901}
902
903static int r8192_wx_get_retry(struct net_device *dev,
904 struct iw_request_info *info,
905 union iwreq_data *wrqu, char *extra)
906{
907 struct r8192_priv *priv = ieee80211_priv(dev);
908
909
910 wrqu->retry.disabled = 0; /* can't be disabled */
911
912 if ((wrqu->retry.flags & IW_RETRY_TYPE) ==
913 IW_RETRY_LIFETIME)
914 return -EINVAL;
915
916 if (wrqu->retry.flags & IW_RETRY_MAX) {
917 wrqu->retry.flags = IW_RETRY_LIMIT | IW_RETRY_MAX;
918 wrqu->retry.value = priv->retry_rts;
919 } else {
920 wrqu->retry.flags = IW_RETRY_LIMIT | IW_RETRY_MIN;
921 wrqu->retry.value = priv->retry_data;
922 }
923 //printk("returning %d",wrqu->retry.value);
924
925
926 return 0;
927}
928
929static int r8192_wx_get_sens(struct net_device *dev,
930 struct iw_request_info *info,
931 union iwreq_data *wrqu, char *extra)
932{
933 struct r8192_priv *priv = ieee80211_priv(dev);
934 if(priv->rf_set_sens == NULL)
935 return -1; /* we have not this support for this radio */
936 wrqu->sens.value = priv->sens;
937 return 0;
938}
939
940
941static int r8192_wx_set_sens(struct net_device *dev,
942 struct iw_request_info *info,
943 union iwreq_data *wrqu, char *extra)
944{
945
946 struct r8192_priv *priv = ieee80211_priv(dev);
947
948 short err = 0;
949 down(&priv->wx_sem);
950 //DMESG("attempt to set sensivity to %ddb",wrqu->sens.value);
951 if(priv->rf_set_sens == NULL) {
952 err= -1; /* we have not this support for this radio */
953 goto exit;
954 }
955 if(priv->rf_set_sens(dev, wrqu->sens.value) == 0)
956 priv->sens = wrqu->sens.value;
957 else
958 err= -EINVAL;
959
960exit:
961 up(&priv->wx_sem);
962
963 return err;
964}
965
966#if (WIRELESS_EXT >= 18)
967#if 0
968static int r8192_wx_get_enc_ext(struct net_device *dev,
969 struct iw_request_info *info,
970 union iwreq_data *wrqu, char *extra)
971{
972 struct r8192_priv *priv = ieee80211_priv(dev);
973 int ret = 0;
974 ret = ieee80211_wx_get_encode_ext(priv->ieee80211, info, wrqu, extra);
975 return ret;
976}
977#endif
978//hw security need to reorganized.
979static int r8192_wx_set_enc_ext(struct net_device *dev,
980 struct iw_request_info *info,
981 union iwreq_data *wrqu, char *extra)
982{
983 int ret=0;
984 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
985 struct r8192_priv *priv = ieee80211_priv(dev);
986 struct ieee80211_device* ieee = priv->ieee80211;
987 //printk("===>%s()\n", __FUNCTION__);
988
989
990 down(&priv->wx_sem);
991 ret = ieee80211_wx_set_encode_ext(priv->ieee80211, info, wrqu, extra);
992
993 {
994 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
995 u8 zero[6] = {0};
996 u32 key[4] = {0};
997 struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
998 struct iw_point *encoding = &wrqu->encoding;
999#if 0
1000 static u8 CAM_CONST_ADDR[4][6] = {
1001 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
1002 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
1003 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
1004 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}};
1005#endif
1006 u8 idx = 0, alg = 0, group = 0;
1007 if ((encoding->flags & IW_ENCODE_DISABLED) ||
1008 ext->alg == IW_ENCODE_ALG_NONE) //none is not allowed to use hwsec WB 2008.07.01
1009 {
1010 ieee->pairwise_key_type = ieee->group_key_type = KEY_TYPE_NA;
1011 CamResetAllEntry(dev);
1012 goto end_hw_sec;
1013 }
1014 alg = (ext->alg == IW_ENCODE_ALG_CCMP)?KEY_TYPE_CCMP:ext->alg; // as IW_ENCODE_ALG_CCMP is defined to be 3 and KEY_TYPE_CCMP is defined to 4;
1015 idx = encoding->flags & IW_ENCODE_INDEX;
1016 if (idx)
1017 idx --;
1018 group = ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY;
1019
1020 if ((!group) || (IW_MODE_ADHOC == ieee->iw_mode) || (alg == KEY_TYPE_WEP40))
1021 {
1022 if ((ext->key_len == 13) && (alg == KEY_TYPE_WEP40) )
1023 alg = KEY_TYPE_WEP104;
1024 ieee->pairwise_key_type = alg;
1025 EnableHWSecurityConfig8192(dev);
1026 }
1027 memcpy((u8*)key, ext->key, 16); //we only get 16 bytes key.why? WB 2008.7.1
1028
1029 if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode !=2) )
1030 {
1031
1032 setKey( dev,
1033 idx,//EntryNo
1034 idx, //KeyIndex
1035 alg, //KeyType
1036 zero, //MacAddr
1037 0, //DefaultKey
1038 key); //KeyContent
1039 }
1040 else if (group)
1041 {
1042 ieee->group_key_type = alg;
1043 setKey( dev,
1044 idx,//EntryNo
1045 idx, //KeyIndex
1046 alg, //KeyType
1047 broadcast_addr, //MacAddr
1048 0, //DefaultKey
1049 key); //KeyContent
1050 }
1051 else //pairwise key
1052 {
1053 setKey( dev,
1054 4,//EntryNo
1055 idx, //KeyIndex
1056 alg, //KeyType
1057 (u8*)ieee->ap_mac_addr, //MacAddr
1058 0, //DefaultKey
1059 key); //KeyContent
1060 }
1061
1062
1063 }
1064
1065end_hw_sec:
1066
1067 up(&priv->wx_sem);
1068#endif
1069 return ret;
1070
1071}
1072static int r8192_wx_set_auth(struct net_device *dev,
1073 struct iw_request_info *info,
1074 union iwreq_data *data, char *extra)
1075{
1076 int ret=0;
1077#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1078 //printk("====>%s()\n", __FUNCTION__);
1079 struct r8192_priv *priv = ieee80211_priv(dev);
1080 down(&priv->wx_sem);
1081 ret = ieee80211_wx_set_auth(priv->ieee80211, info, &(data->param), extra);
1082 up(&priv->wx_sem);
1083#endif
1084 return ret;
1085}
1086
1087static int r8192_wx_set_mlme(struct net_device *dev,
1088 struct iw_request_info *info,
1089 union iwreq_data *wrqu, char *extra)
1090{
1091 //printk("====>%s()\n", __FUNCTION__);
1092
1093 int ret=0;
1094#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1095 struct r8192_priv *priv = ieee80211_priv(dev);
1096 down(&priv->wx_sem);
1097 ret = ieee80211_wx_set_mlme(priv->ieee80211, info, wrqu, extra);
1098
1099 up(&priv->wx_sem);
1100#endif
1101 return ret;
1102}
1103#endif
1104static int r8192_wx_set_gen_ie(struct net_device *dev,
1105 struct iw_request_info *info,
1106 union iwreq_data *data, char *extra)
1107{
1108 //printk("====>%s(), len:%d\n", __FUNCTION__, data->length);
1109 int ret=0;
1110#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1111 struct r8192_priv *priv = ieee80211_priv(dev);
1112 down(&priv->wx_sem);
1113#if 1
1114 ret = ieee80211_wx_set_gen_ie(priv->ieee80211, extra, data->data.length);
1115#endif
1116 up(&priv->wx_sem);
1117 //printk("<======%s(), ret:%d\n", __FUNCTION__, ret);
1118#endif
1119 return ret;
1120
1121
1122}
1123
1124static int dummy(struct net_device *dev, struct iw_request_info *a,
1125 union iwreq_data *wrqu,char *b)
1126{
1127 return -1;
1128}
1129
1130
1131static iw_handler r8192_wx_handlers[] =
1132{
1133 NULL, /* SIOCSIWCOMMIT */
1134 r8192_wx_get_name, /* SIOCGIWNAME */
1135 dummy, /* SIOCSIWNWID */
1136 dummy, /* SIOCGIWNWID */
1137 r8192_wx_set_freq, /* SIOCSIWFREQ */
1138 r8192_wx_get_freq, /* SIOCGIWFREQ */
1139 r8192_wx_set_mode, /* SIOCSIWMODE */
1140 r8192_wx_get_mode, /* SIOCGIWMODE */
1141 r8192_wx_set_sens, /* SIOCSIWSENS */
1142 r8192_wx_get_sens, /* SIOCGIWSENS */
1143 NULL, /* SIOCSIWRANGE */
1144 rtl8180_wx_get_range, /* SIOCGIWRANGE */
1145 NULL, /* SIOCSIWPRIV */
1146 NULL, /* SIOCGIWPRIV */
1147 NULL, /* SIOCSIWSTATS */
1148 NULL, /* SIOCGIWSTATS */
1149 dummy, /* SIOCSIWSPY */
1150 dummy, /* SIOCGIWSPY */
1151 NULL, /* SIOCGIWTHRSPY */
1152 NULL, /* SIOCWIWTHRSPY */
1153 r8192_wx_set_wap, /* SIOCSIWAP */
1154 r8192_wx_get_wap, /* SIOCGIWAP */
1155#if (WIRELESS_EXT >= 18)
1156 r8192_wx_set_mlme, /* MLME-- */
1157#else
1158 NULL,
1159#endif
1160 dummy, /* SIOCGIWAPLIST -- depricated */
1161 r8192_wx_set_scan, /* SIOCSIWSCAN */
1162 r8192_wx_get_scan, /* SIOCGIWSCAN */
1163 r8192_wx_set_essid, /* SIOCSIWESSID */
1164 r8192_wx_get_essid, /* SIOCGIWESSID */
1165 dummy, /* SIOCSIWNICKN */
1166 dummy, /* SIOCGIWNICKN */
1167 NULL, /* -- hole -- */
1168 NULL, /* -- hole -- */
1169 r8192_wx_set_rate, /* SIOCSIWRATE */
1170 r8192_wx_get_rate, /* SIOCGIWRATE */
1171 r8192_wx_set_rts, /* SIOCSIWRTS */
1172 r8192_wx_get_rts, /* SIOCGIWRTS */
1173 r8192_wx_set_frag, /* SIOCSIWFRAG */
1174 r8192_wx_get_frag, /* SIOCGIWFRAG */
1175 dummy, /* SIOCSIWTXPOW */
1176 dummy, /* SIOCGIWTXPOW */
1177 r8192_wx_set_retry, /* SIOCSIWRETRY */
1178 r8192_wx_get_retry, /* SIOCGIWRETRY */
1179 r8192_wx_set_enc, /* SIOCSIWENCODE */
1180 r8192_wx_get_enc, /* SIOCGIWENCODE */
1181 r8192_wx_set_power, /* SIOCSIWPOWER */
1182 r8192_wx_get_power, /* SIOCGIWPOWER */
1183 NULL, /*---hole---*/
1184 NULL, /*---hole---*/
1185 r8192_wx_set_gen_ie,//NULL, /* SIOCSIWGENIE */
1186 NULL, /* SIOCSIWGENIE */
1187
1188#if (WIRELESS_EXT >= 18)
1189 r8192_wx_set_auth,//NULL, /* SIOCSIWAUTH */
1190 NULL,//r8192_wx_get_auth,//NULL, /* SIOCSIWAUTH */
1191 r8192_wx_set_enc_ext, /* SIOCSIWENCODEEXT */
1192 NULL,//r8192_wx_get_enc_ext,//NULL, /* SIOCSIWENCODEEXT */
1193#else
1194 NULL,
1195 NULL,
1196 NULL,
1197 NULL,
1198#endif
1199 NULL, /* SIOCSIWPMKSA */
1200 NULL, /*---hole---*/
1201
1202};
1203
1204
1205static const struct iw_priv_args r8192_private_args[] = {
1206
1207 {
1208 SIOCIWFIRSTPRIV + 0x0,
1209 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "badcrc"
1210 },
1211
1212 {
1213 SIOCIWFIRSTPRIV + 0x1,
1214 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "activescan"
1215
1216 },
1217 {
1218 SIOCIWFIRSTPRIV + 0x2,
1219 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rawtx"
1220 }
1221#ifdef JOHN_IOCTL
1222 ,
1223 {
1224 SIOCIWFIRSTPRIV + 0x3,
1225 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readRF"
1226 }
1227 ,
1228 {
1229 SIOCIWFIRSTPRIV + 0x4,
1230 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeRF"
1231 }
1232 ,
1233 {
1234 SIOCIWFIRSTPRIV + 0x5,
1235 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readBB"
1236 }
1237 ,
1238 {
1239 SIOCIWFIRSTPRIV + 0x6,
1240 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeBB"
1241 }
1242 ,
1243 {
1244 SIOCIWFIRSTPRIV + 0x7,
1245 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readnicb"
1246 }
1247 ,
1248 {
1249 SIOCIWFIRSTPRIV + 0x8,
1250 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writenicb"
1251 }
1252 ,
1253 {
1254 SIOCIWFIRSTPRIV + 0x9,
1255 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo"
1256 }
1257
1258#endif
1259 ,
1260 {
1261 SIOCIWFIRSTPRIV + 0x3,
1262 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset"
1263 }
1264
1265#ifdef RTL8192SU
1266 ,
1267 {
1268 SIOCIWFIRSTPRIV + 0x5,
1269 IW_PRIV_TYPE_NONE, IW_PRIV_TYPE_INT|IW_PRIV_SIZE_FIXED|1,
1270 "firm_ver"
1271 }
1272#endif
1273};
1274
1275
1276static iw_handler r8192_private_handler[] = {
1277// r8192_wx_set_monitor, /* SIOCIWFIRSTPRIV */
1278 r8192_wx_set_crcmon, /*SIOCIWSECONDPRIV*/
1279// r8192_wx_set_forceassociate,
1280// r8192_wx_set_beaconinterval,
1281// r8192_wx_set_monitor_type,
1282 r8192_wx_set_scan_type,
1283 r8192_wx_set_rawtx,
1284#ifdef JOHN_IOCTL
1285 r8192_wx_read_regs,
1286 r8192_wx_write_regs,
1287 r8192_wx_read_bb,
1288 r8192_wx_write_bb,
1289 r8192_wx_read_nicb,
1290 r8192_wx_write_nicb,
1291 r8192_wx_get_ap_status,
1292#endif
1293 r8192_wx_force_reset,
1294 (iw_handler)NULL,
1295#ifdef RTL8192SU
1296 (iw_handler)r8191su_wx_get_firm_version,
1297#endif
1298};
1299
1300//#if WIRELESS_EXT >= 17
1301struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev)
1302{
1303 struct r8192_priv *priv = ieee80211_priv(dev);
1304 struct ieee80211_device* ieee = priv->ieee80211;
1305 struct iw_statistics* wstats = &priv->wstats;
1306 int tmp_level = 0;
1307 int tmp_qual = 0;
1308 int tmp_noise = 0;
1309 if(ieee->state < IEEE80211_LINKED)
1310 {
1311 wstats->qual.qual = 0;
1312 wstats->qual.level = 0;
1313 wstats->qual.noise = 0;
1314#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14))
1315 wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
1316#else
1317 wstats->qual.updated = 0x0f;
1318#endif
1319 return wstats;
1320 }
1321
1322 tmp_level = (&ieee->current_network)->stats.rssi;
1323 tmp_qual = (&ieee->current_network)->stats.signal;
1324 tmp_noise = (&ieee->current_network)->stats.noise;
1325 //printk("level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise);
1326
1327 wstats->qual.level = tmp_level;
1328 wstats->qual.qual = tmp_qual;
1329 wstats->qual.noise = tmp_noise;
1330#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14))
1331 wstats->qual.updated = IW_QUAL_ALL_UPDATED| IW_QUAL_DBM;
1332#else
1333 wstats->qual.updated = 0x0f;
1334#endif
1335 return wstats;
1336}
1337//#endif
1338
1339
1340struct iw_handler_def r8192_wx_handlers_def={
1341 .standard = r8192_wx_handlers,
1342 .num_standard = sizeof(r8192_wx_handlers) / sizeof(iw_handler),
1343 .private = r8192_private_handler,
1344 .num_private = sizeof(r8192_private_handler) / sizeof(iw_handler),
1345 .num_private_args = sizeof(r8192_private_args) / sizeof(struct iw_priv_args),
1346#if WIRELESS_EXT >= 17
1347 .get_wireless_stats = r8192_get_wireless_stats,
1348#endif
1349 .private_args = (struct iw_priv_args *)r8192_private_args,
1350};
diff --git a/drivers/staging/rtl8192su/r8192U_wx.h b/drivers/staging/rtl8192su/r8192U_wx.h
new file mode 100644
index 00000000000..b2f7a571b1c
--- /dev/null
+++ b/drivers/staging/rtl8192su/r8192U_wx.h
@@ -0,0 +1,23 @@
1/*
2 This is part of rtl8180 OpenSource driver - v 0.3
3 Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the official realtek driver
7 Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon
8 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
9
10 We want to tanks the Authors of such projects and the Ndiswrapper project Authors.
11*/
12
13/* this file (will) contains wireless extension handlers*/
14
15#ifndef R8180_WX_H
16#define R8180_WX_H
17//#include <linux/wireless.h>
18//#include "ieee80211.h"
19extern struct iw_handler_def r8192_wx_handlers_def;
20/* Enable the rtl819x_core.c to share this function, david 2008.9.22 */
21extern struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev);
22
23#endif
diff --git a/drivers/staging/rtl8192su/r819xU_HTGen.h b/drivers/staging/rtl8192su/r819xU_HTGen.h
new file mode 100644
index 00000000000..7a60480c4b8
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_HTGen.h
@@ -0,0 +1,22 @@
1//
2// IOT Action for different AP
3//
4typedef enum _HT_IOT_ACTION{
5 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
6 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
7 HT_IOT_ACT_DECLARE_MCS13 = 0x00000004,
8 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000008,
9 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000010,
10 HT_IOT_ACT_CDD_FSYNC = 0x00000020,
11 HT_IOT_ACT_PURE_N_MODE = 0x00000040,
12
13 //LZM ADD 090224
14 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
15 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
16 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
17 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
18 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
19 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
20 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
21}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
22
diff --git a/drivers/staging/rtl8192su/r819xU_HTType.h b/drivers/staging/rtl8192su/r819xU_HTType.h
new file mode 100644
index 00000000000..2994aa0876a
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_HTType.h
@@ -0,0 +1,392 @@
1#ifndef _R819XU_HTTYPE_H_
2#define _R819XU_HTTYPE_H_
3
4
5//------------------------------------------------------------
6// The HT Capability element is present in beacons, association request,
7// reassociation request and probe response frames
8//------------------------------------------------------------
9
10//
11// Operation mode value
12//
13#define HT_OPMODE_NO_PROTECT 0
14#define HT_OPMODE_OPTIONAL 1
15#define HT_OPMODE_40MHZ_PROTECT 2
16#define HT_OPMODE_MIXED 3
17
18//
19// MIMO Power Save Setings
20//
21#define MIMO_PS_STATIC 0
22#define MIMO_PS_DYNAMIC 1
23#define MIMO_PS_NOLIMIT 3
24
25
26//
27// There should be 128 bits to cover all of the MCS rates. However, since
28// 8190 does not support too much rates, one integer is quite enough.
29//
30
31#define sHTCLng 4
32
33
34#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
35#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
36#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
37
38
39typedef enum _HT_MCS_RATE{
40 HT_MCS0 = 0x00000001,
41 HT_MCS1 = 0x00000002,
42 HT_MCS2 = 0x00000004,
43 HT_MCS3 = 0x00000008,
44 HT_MCS4 = 0x00000010,
45 HT_MCS5 = 0x00000020,
46 HT_MCS6 = 0x00000040,
47 HT_MCS7 = 0x00000080,
48 HT_MCS8 = 0x00000100,
49 HT_MCS9 = 0x00000200,
50 HT_MCS10 = 0x00000400,
51 HT_MCS11 = 0x00000800,
52 HT_MCS12 = 0x00001000,
53 HT_MCS13 = 0x00002000,
54 HT_MCS14 = 0x00004000,
55 HT_MCS15 = 0x00008000,
56 // Do not define MCS32 here although 8190 support MCS32
57}HT_MCS_RATE,*PHT_MCS_RATE;
58
59//
60// Represent Channel Width in HT Capabilities
61//
62typedef enum _HT_CHANNEL_WIDTH{
63 HT_CHANNEL_WIDTH_20 = 0,
64 HT_CHANNEL_WIDTH_20_40 = 1,
65}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
66
67//
68// Represent Extention Channel Offset in HT Capabilities
69// This is available only in 40Mhz mode.
70//
71typedef enum _HT_EXTCHNL_OFFSET{
72 HT_EXTCHNL_OFFSET_NO_EXT = 0,
73 HT_EXTCHNL_OFFSET_UPPER = 1,
74 HT_EXTCHNL_OFFSET_NO_DEF = 2,
75 HT_EXTCHNL_OFFSET_LOWER = 3,
76}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
77
78typedef enum _CHNLOP{
79 CHNLOP_NONE = 0, // No Action now
80 CHNLOP_SCAN = 1, // Scan in progress
81 CHNLOP_SWBW = 2, // Bandwidth switching in progress
82 CHNLOP_SWCHNL = 3, // Software Channel switching in progress
83} CHNLOP, *PCHNLOP;
84
85// Determine if the Channel Operation is in progress
86#define CHHLOP_IN_PROGRESS(_pHTInfo) \
87 ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE
88
89
90typedef enum _HT_ACTION{
91 ACT_RECOMMAND_WIDTH = 0,
92 ACT_MIMO_PWR_SAVE = 1,
93 ACT_PSMP = 2,
94 ACT_SET_PCO_PHASE = 3,
95 ACT_MIMO_CHL_MEASURE = 4,
96 ACT_RECIPROCITY_CORRECT = 5,
97 ACT_MIMO_CSI_MATRICS = 6,
98 ACT_MIMO_NOCOMPR_STEER = 7,
99 ACT_MIMO_COMPR_STEER = 8,
100 ACT_ANTENNA_SELECT = 9,
101} HT_ACTION, *PHT_ACTION;
102
103
104/* 2007/06/07 MH Define sub-carrier mode for 40MHZ. */
105typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
106 SC_MODE_DUPLICATE = 0,
107 SC_MODE_LOWER = 1,
108 SC_MODE_UPPER = 2,
109 SC_MODE_FULL40MHZ = 3,
110}HT_BW40_SC_E;
111
112typedef struct _HT_CAPABILITY_ELE{
113
114 //HT capability info
115 u8 AdvCoding:1;
116 u8 ChlWidth:1;
117 u8 MimoPwrSave:2;
118 u8 GreenField:1;
119 u8 ShortGI20Mhz:1;
120 u8 ShortGI40Mhz:1;
121 u8 TxSTBC:1;
122 u8 RxSTBC:2;
123 u8 DelayBA:1;
124 u8 MaxAMSDUSize:1;
125 u8 DssCCk:1;
126 u8 PSMP:1;
127 u8 Rsvd1:1;
128 u8 LSigTxopProtect:1;
129
130 //MAC HT parameters info
131 u8 MaxRxAMPDUFactor:2;
132 u8 MPDUDensity:3;
133 u8 Rsvd2:3;
134
135 //Supported MCS set
136 u8 MCS[16];
137
138
139 //Extended HT Capability Info
140 u16 ExtHTCapInfo;
141
142 //TXBF Capabilities
143 u8 TxBFCap[4];
144
145 //Antenna Selection Capabilities
146 u8 ASCap;
147
148}__attribute__((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE;
149
150//------------------------------------------------------------
151// The HT Information element is present in beacons
152// Only AP is required to include this element
153//------------------------------------------------------------
154
155typedef struct _HT_INFORMATION_ELE{
156 u8 ControlChl;
157
158 u8 ExtChlOffset:2;
159 u8 RecommemdedTxWidth:1;
160 u8 RIFS:1;
161 u8 PSMPAccessOnly:1;
162 u8 SrvIntGranularity:3;
163
164 u8 OptMode:2;
165 u8 NonGFDevPresent:1;
166 u8 Revd1:5;
167 u8 Revd2:8;
168
169 u8 Rsvd3:6;
170 u8 DualBeacon:1;
171 u8 DualCTSProtect:1;
172
173 u8 SecondaryBeacon:1;
174 u8 LSigTxopProtectFull:1;
175 u8 PcoActive:1;
176 u8 PcoPhase:1;
177 u8 Rsvd4:4;
178
179 u8 BasicMSC[16];
180}__attribute__((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE;
181
182//
183// MIMO Power Save control field.
184// This is appear in MIMO Power Save Action Frame
185//
186typedef struct _MIMOPS_CTRL{
187 u8 MimoPsEnable:1;
188 u8 MimoPsMode:1;
189 u8 Reserved:6;
190} MIMOPS_CTRL, *PMIMOPS_CTRL;
191
192typedef enum _HT_SPEC_VER{
193 HT_SPEC_VER_IEEE = 0,
194 HT_SPEC_VER_EWC = 1,
195}HT_SPEC_VER, *PHT_SPEC_VER;
196
197typedef enum _HT_AGGRE_MODE_E{
198 HT_AGG_AUTO = 0,
199 HT_AGG_FORCE_ENABLE = 1,
200 HT_AGG_FORCE_DISABLE = 2,
201}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
202
203//------------------------------------------------------------
204// The Data structure is used to keep HT related variables when card is
205// configured as non-AP STA mode. **Note** Current_xxx should be set
206// to default value in HTInitializeHTInfo()
207//------------------------------------------------------------
208
209typedef struct _RT_HIGH_THROUGHPUT{
210// DECLARE_RT_OBJECT(_RT_HIGH_THROUGHPUT);
211 u8 bEnableHT;
212 u8 bCurrentHTSupport;
213
214 u8 bRegBW40MHz; // Tx 40MHz channel capablity
215 u8 bCurBW40MHz; // Tx 40MHz channel capability
216
217 u8 bRegShortGI40MHz; // Tx Short GI for 40Mhz
218 u8 bCurShortGI40MHz; // Tx Short GI for 40MHz
219
220 u8 bRegShortGI20MHz; // Tx Short GI for 20MHz
221 u8 bCurShortGI20MHz; // Tx Short GI for 20MHz
222
223 u8 bRegSuppCCK; // Tx CCK rate capability
224 u8 bCurSuppCCK; // Tx CCK rate capability
225
226 // 802.11n spec version for "peer"
227 HT_SPEC_VER ePeerHTSpecVer;
228
229
230 // HT related information for "Self"
231 HT_CAPABILITY_ELE SelfHTCap; // This is HT cap element sent to peer STA, which also indicate HT Rx capabilities.
232 HT_INFORMATION_ELE SelfHTInfo; // This is HT info element sent to peer STA, which also indicate HT Rx capabilities.
233
234 // HT related information for "Peer"
235 u8 PeerHTCapBuf[32];
236 u8 PeerHTInfoBuf[32];
237
238
239 // A-MSDU related
240 u8 bAMSDU_Support; // This indicates Tx A-MSDU capability
241 u16 nAMSDU_MaxSize; // This indicates Tx A-MSDU capability
242 u8 bCurrent_AMSDU_Support; // This indicates Tx A-MSDU capability
243 u16 nCurrent_AMSDU_MaxSize; // This indicates Tx A-MSDU capability
244
245
246 // AMPDU related <2006.08.10 Emily>
247 u8 bAMPDUEnable; // This indicate Tx A-MPDU capability
248 u8 bCurrentAMPDUEnable; // This indicate Tx A-MPDU capability
249 u8 AMPDU_Factor; // This indicate Tx A-MPDU capability
250 u8 CurrentAMPDUFactor; // This indicate Tx A-MPDU capability
251 u8 MPDU_Density; // This indicate Tx A-MPDU capability
252 u8 CurrentMPDUDensity; // This indicate Tx A-MPDU capability
253
254 // Forced A-MPDU enable
255 HT_AGGRE_MODE_E ForcedAMPDUMode;
256 u8 ForcedAMPDUFactor;
257 u8 ForcedMPDUDensity;
258
259 // Forced A-MSDU enable
260 HT_AGGRE_MODE_E ForcedAMSDUMode;
261 u16 ForcedAMSDUMaxSize;
262
263 u8 bForcedShortGI;
264
265 u8 CurrentOpMode;
266
267 // MIMO PS related
268 u8 SelfMimoPs;
269 u8 PeerMimoPs;
270
271 // 40MHz Channel Offset settings.
272 HT_EXTCHNL_OFFSET CurSTAExtChnlOffset;
273 u8 bCurTxBW40MHz; // If we use 40 MHz to Tx
274 u8 PeerBandwidth;
275
276 // For Bandwidth Switching
277 u8 bSwBwInProgress;
278 CHNLOP ChnlOp; // software switching channel in progress. By Bruce, 2008-02-15.
279 u8 SwBwStep;
280 //RT_TIMER SwBwTimer;
281 struct timer_list SwBwTimer;
282
283 // For Realtek proprietary A-MPDU factor for aggregation
284 u8 bRegRT2RTAggregation;
285 u8 bCurrentRT2RTAggregation;
286 u8 bCurrentRT2RTLongSlotTime;
287 u8 szRT2RTAggBuffer[10];
288
289 // Rx Reorder control
290 u8 bRegRxReorderEnable;
291 u8 bCurRxReorderEnable;
292 u8 RxReorderWinSize;
293 u8 RxReorderPendingTime;
294 u16 RxReorderDropCounter;
295
296#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
297 u8 UsbTxAggrNum;
298#endif
299#ifdef USB_RX_AGGREGATION_SUPPORT
300 u8 UsbRxFwAggrEn;
301 u8 UsbRxFwAggrPageNum;
302 u8 UsbRxFwAggrPacketNum;
303 u8 UsbRxFwAggrTimeout;
304#endif
305
306 // Add for Broadcom(Linksys) IOT. Joseph
307 u8 bIsPeerBcm;
308
309 // For IOT issue.
310 u32 IOTAction;
311}RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT;
312
313
314//------------------------------------------------------------
315// The Data structure is used to keep HT related variable for "each Sta"
316// when card is configured as "AP mode"
317//------------------------------------------------------------
318
319typedef struct _RT_HTINFO_STA_ENTRY{
320 u8 bEnableHT;
321
322 u8 bSupportCck;
323
324 u16 AMSDU_MaxSize;
325
326 u8 AMPDU_Factor;
327 u8 MPDU_Density;
328
329 u8 HTHighestOperaRate;
330
331 u8 bBw40MHz;
332
333 u8 MimoPs;
334
335 u8 McsRateSet[16];
336
337
338}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY;
339
340
341
342
343
344//------------------------------------------------------------
345// The Data structure is used to keep HT related variable for "each AP"
346// when card is configured as "STA mode"
347//------------------------------------------------------------
348
349typedef struct _BSS_HT{
350
351 u8 bdSupportHT;
352
353 // HT related elements
354 u8 bdHTCapBuf[32];
355 u16 bdHTCapLen;
356 u8 bdHTInfoBuf[32];
357 u16 bdHTInfoLen;
358
359 HT_SPEC_VER bdHTSpecVer;
360 //HT_CAPABILITY_ELE bdHTCapEle;
361 //HT_INFORMATION_ELE bdHTInfoEle;
362
363 u8 bdRT2RTAggregation;
364 u8 bdRT2RTLongSlotTime;
365 bool bdHT1R;
366}BSS_HT, *PBSS_HT;
367
368typedef struct _MIMO_RSSI{
369 u32 EnableAntenna;
370 u32 AntennaA;
371 u32 AntennaB;
372 u32 AntennaC;
373 u32 AntennaD;
374 u32 Average;
375}MIMO_RSSI, *PMIMO_RSSI;
376
377typedef struct _MIMO_EVM{
378 u32 EVM1;
379 u32 EVM2;
380}MIMO_EVM, *PMIMO_EVM;
381
382typedef struct _FALSE_ALARM_STATISTICS{
383 u32 Cnt_Parity_Fail;
384 u32 Cnt_Rate_Illegal;
385 u32 Cnt_Crc8_fail;
386 u32 Cnt_all;
387}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
388
389
390
391#endif //__INC_HTTYPE_H
392
diff --git a/drivers/staging/rtl8192su/r819xU_cmdpkt.c b/drivers/staging/rtl8192su/r819xU_cmdpkt.c
new file mode 100644
index 00000000000..c1149c6f77b
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_cmdpkt.c
@@ -0,0 +1,826 @@
1/******************************************************************************
2
3 (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4
5 Module: r819xusb_cmdpkt.c (RTL8190 TX/RX command packet handler Source C File)
6
7 Note: The module is responsible for handling TX and RX command packet.
8 1. TX : Send set and query configuration command packet.
9 2. RX : Receive tx feedback, beacon state, query configuration
10 command packet.
11
12 Function:
13
14 Export:
15
16 Abbrev:
17
18 History:
19 Data Who Remark
20
21 05/06/2008 amy Create initial version porting from windows driver.
22
23******************************************************************************/
24#include "r8192U.h"
25#include "r819xU_cmdpkt.h"
26/*---------------------------Define Local Constant---------------------------*/
27/* Debug constant*/
28#define CMPK_DEBOUNCE_CNT 1
29/* 2007/10/24 MH Add for printing a range of data. */
30#define CMPK_PRINT(Address)\
31{\
32 unsigned char i;\
33 u32 temp[10];\
34 \
35 memcpy(temp, Address, 40);\
36 for (i = 0; i <40; i+=4)\
37 printk("\r\n %08x", temp[i]);\
38}\
39/*---------------------------Define functions---------------------------------*/
40
41bool
42SendTxCommandPacket(
43 struct net_device *dev,
44 void* pData,
45 u32 DataLen
46 )
47{
48 bool rtStatus = true;
49 struct r8192_priv *priv = ieee80211_priv(dev);
50 struct sk_buff *skb;
51 cb_desc *tcb_desc;
52 unsigned char *ptr_buf;
53 //bool bLastInitPacket = false;
54
55 //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
56
57 //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ)
58 skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + DataLen + 4);
59 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
60 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
61 tcb_desc->queue_index = TXCMD_QUEUE;
62 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_NORMAL;
63 tcb_desc->bLastIniPkt = 0;
64 skb_reserve(skb, USB_HWDESC_HEADER_LEN);
65 ptr_buf = skb_put(skb, DataLen);
66 memset(ptr_buf,0,DataLen);
67 memcpy(ptr_buf,pData,DataLen);
68 tcb_desc->txbuf_size= (u16)DataLen;
69
70 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
71 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
72 (priv->ieee80211->queue_stop) ) {
73 RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n");
74 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
75 } else {
76 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
77 }
78
79 //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
80 return rtStatus;
81}
82
83/*-----------------------------------------------------------------------------
84 * Function: cmpk_message_handle_tx()
85 *
86 * Overview: Driver internal module can call the API to send message to
87 * firmware side. For example, you can send a debug command packet.
88 * Or you can send a request for FW to modify RLX4181 LBUS HW bank.
89 * Otherwise, you can change MAC/PHT/RF register by firmware at
90 * run time. We do not support message more than one segment now.
91 *
92 * Input: NONE
93 *
94 * Output: NONE
95 *
96 * Return: NONE
97 *
98 * Revised History:
99 * When Who Remark
100 * 05/06/2008 amy porting from windows code.
101 *
102 *---------------------------------------------------------------------------*/
103 extern bool cmpk_message_handle_tx(
104 struct net_device *dev,
105 u8* codevirtualaddress,
106 u32 packettype,
107 u32 buffer_len)
108{
109
110 bool rt_status = true;
111#ifdef RTL8192SU
112 return rt_status;
113#else
114#ifdef RTL8192U
115 return rt_status;
116#else
117 struct r8192_priv *priv = ieee80211_priv(dev);
118 u16 frag_threshold;
119 u16 frag_length, frag_offset = 0;
120 //u16 total_size;
121 //int i;
122
123 rt_firmware *pfirmware = priv->pFirmware;
124 struct sk_buff *skb;
125 unsigned char *seg_ptr;
126 cb_desc *tcb_desc;
127 u8 bLastIniPkt;
128
129 firmware_init_param(dev);
130 //Fragmentation might be required
131 frag_threshold = pfirmware->cmdpacket_frag_thresold;
132 do {
133 if((buffer_len - frag_offset) > frag_threshold) {
134 frag_length = frag_threshold ;
135 bLastIniPkt = 0;
136
137 } else {
138 frag_length = buffer_len - frag_offset;
139 bLastIniPkt = 1;
140
141 }
142
143 /* Allocate skb buffer to contain firmware info and tx descriptor info
144 * add 4 to avoid packet appending overflow.
145 * */
146 #ifdef RTL8192U
147 skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
148 #else
149 skb = dev_alloc_skb(frag_length + 4);
150 #endif
151 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
152 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
153 tcb_desc->queue_index = TXCMD_QUEUE;
154 tcb_desc->bCmdOrInit = packettype;
155 tcb_desc->bLastIniPkt = bLastIniPkt;
156
157 #ifdef RTL8192U
158 skb_reserve(skb, USB_HWDESC_HEADER_LEN);
159 #endif
160
161 seg_ptr = skb_put(skb, buffer_len);
162 /*
163 * Transform from little endian to big endian
164 * and pending zero
165 */
166 memcpy(seg_ptr,codevirtualaddress,buffer_len);
167 tcb_desc->txbuf_size= (u16)buffer_len;
168
169
170 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
171 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
172 (priv->ieee80211->queue_stop) ) {
173 RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
174 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
175 } else {
176 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
177 }
178
179 codevirtualaddress += frag_length;
180 frag_offset += frag_length;
181
182 }while(frag_offset < buffer_len);
183
184 return rt_status;
185
186
187#endif
188#endif
189} /* CMPK_Message_Handle_Tx */
190
191/*-----------------------------------------------------------------------------
192 * Function: cmpk_counttxstatistic()
193 *
194 * Overview:
195 *
196 * Input: PADAPTER pAdapter - .
197 * CMPK_TXFB_T *psTx_FB - .
198 *
199 * Output: NONE
200 *
201 * Return: NONE
202 *
203 * Revised History:
204 * When Who Remark
205 * 05/12/2008 amy Create Version 0 porting from windows code.
206 *
207 *---------------------------------------------------------------------------*/
208static void
209cmpk_count_txstatistic(
210 struct net_device *dev,
211 cmpk_txfb_t *pstx_fb)
212{
213 struct r8192_priv *priv = ieee80211_priv(dev);
214#ifdef ENABLE_PS
215 RT_RF_POWER_STATE rtState;
216
217 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
218
219 // When RF is off, we should not count the packet for hw/sw synchronize
220 // reason, ie. there may be a duration while sw switch is changed and hw
221 // switch is being changed. 2006.12.04, by shien chang.
222 if (rtState == eRfOff)
223 {
224 return;
225 }
226#endif
227
228#ifdef TODO
229 if(pAdapter->bInHctTest)
230 return;
231#endif
232 /* We can not know the packet length and transmit type: broadcast or uni
233 or multicast. So the relative statistics must be collected in tx
234 feedback info. */
235 if (pstx_fb->tok)
236 {
237 priv->stats.txfeedbackok++;
238 priv->stats.txoktotal++;
239 priv->stats.txokbytestotal += pstx_fb->pkt_length;
240 priv->stats.txokinperiod++;
241
242 /* We can not make sure broadcast/multicast or unicast mode. */
243 if (pstx_fb->pkt_type == PACKET_MULTICAST)
244 {
245 priv->stats.txmulticast++;
246 priv->stats.txbytesmulticast += pstx_fb->pkt_length;
247 }
248 else if (pstx_fb->pkt_type == PACKET_BROADCAST)
249 {
250 priv->stats.txbroadcast++;
251 priv->stats.txbytesbroadcast += pstx_fb->pkt_length;
252 }
253 else
254 {
255 priv->stats.txunicast++;
256 priv->stats.txbytesunicast += pstx_fb->pkt_length;
257 }
258 }
259 else
260 {
261 priv->stats.txfeedbackfail++;
262 priv->stats.txerrtotal++;
263 priv->stats.txerrbytestotal += pstx_fb->pkt_length;
264
265 /* We can not make sure broadcast/multicast or unicast mode. */
266 if (pstx_fb->pkt_type == PACKET_MULTICAST)
267 {
268 priv->stats.txerrmulticast++;
269 }
270 else if (pstx_fb->pkt_type == PACKET_BROADCAST)
271 {
272 priv->stats.txerrbroadcast++;
273 }
274 else
275 {
276 priv->stats.txerrunicast++;
277 }
278 }
279
280 priv->stats.txretrycount += pstx_fb->retry_cnt;
281 priv->stats.txfeedbackretry += pstx_fb->retry_cnt;
282
283} /* cmpk_CountTxStatistic */
284
285
286
287/*-----------------------------------------------------------------------------
288 * Function: cmpk_handle_tx_feedback()
289 *
290 * Overview: The function is responsible for extract the message inside TX
291 * feedbck message from firmware. It will contain dedicated info in
292 * ws-06-0063-rtl8190-command-packet-specification. Please
293 * refer to chapter "TX Feedback Element". We have to read 20 bytes
294 * in the command packet.
295 *
296 * Input: struct net_device * dev
297 * u8 * pmsg - Msg Ptr of the command packet.
298 *
299 * Output: NONE
300 *
301 * Return: NONE
302 *
303 * Revised History:
304 * When Who Remark
305 * 05/08/2008 amy Create Version 0 porting from windows code.
306 *
307 *---------------------------------------------------------------------------*/
308static void
309cmpk_handle_tx_feedback(
310 struct net_device *dev,
311 u8 * pmsg)
312{
313 struct r8192_priv *priv = ieee80211_priv(dev);
314 cmpk_txfb_t rx_tx_fb; /* */
315
316 priv->stats.txfeedback++;
317
318 /* 0. Display received message. */
319 //cmpk_Display_Message(CMPK_RX_TX_FB_SIZE, pMsg);
320
321 /* 1. Extract TX feedback info from RFD to temp structure buffer. */
322 /* It seems that FW use big endian(MIPS) and DRV use little endian in
323 windows OS. So we have to read the content byte by byte or transfer
324 endian type before copy the message copy. */
325#if 0 // The TX FEEDBACK packet element address
326 //rx_tx_fb.Element_ID = pMsg[0];
327 //rx_tx_fb.Length = pMsg[1];
328 rx_tx_fb.TOK = pMsg[2]>>7;
329 rx_tx_fb.Fail_Reason = (pMsg[2] & 0x70) >> 4;
330 rx_tx_fb.TID = (pMsg[2] & 0x0F);
331 rx_tx_fb.Qos_Pkt = pMsg[3] >> 7;
332 rx_tx_fb.Bandwidth = (pMsg[3] & 0x40) >> 6;
333 rx_tx_fb.Retry_Cnt = pMsg[5];
334 rx_tx_fb.Pkt_ID = (pMsg[6] << 8) | pMsg[7];
335 rx_tx_fb.Seq_Num = (pMsg[8] << 8) | pMsg[9];
336 rx_tx_fb.S_Rate = pMsg[10];
337 rx_tx_fb.F_Rate = pMsg[11];
338 rx_tx_fb.S_RTS_Rate = pMsg[12];
339 rx_tx_fb.F_RTS_Rate = pMsg[13];
340 rx_tx_fb.pkt_length = (pMsg[14] << 8) | pMsg[15];
341#endif
342 /* 2007/07/05 MH Use pointer to transfer structure memory. */
343 //memcpy((UINT8 *)&rx_tx_fb, pMsg, sizeof(CMPK_TXFB_T));
344 memcpy((u8*)&rx_tx_fb, pmsg, sizeof(cmpk_txfb_t));
345 /* 2. Use tx feedback info to count TX statistics. */
346 cmpk_count_txstatistic(dev, &rx_tx_fb);
347#if 0
348 /* 2007/07/11 MH Assign current operate rate. */
349 if (pAdapter->RegWirelessMode == WIRELESS_MODE_A ||
350 pAdapter->RegWirelessMode == WIRELESS_MODE_B ||
351 pAdapter->RegWirelessMode == WIRELESS_MODE_G)
352 {
353 pMgntInfo->CurrentOperaRate = (rx_tx_fb.F_Rate & 0x7F);
354 }
355 else if (pAdapter->RegWirelessMode == WIRELESS_MODE_N_24G ||
356 pAdapter->RegWirelessMode == WIRELESS_MODE_N_5G)
357 {
358 pMgntInfo->HTCurrentOperaRate = (rx_tx_fb.F_Rate & 0x8F);
359 }
360#endif
361 /* 2007/01/17 MH Comment previous method for TX statistic function. */
362 /* Collect info TX feedback packet to fill TCB. */
363 /* We can not know the packet length and transmit type: broadcast or uni
364 or multicast. */
365 //CountTxStatistics( pAdapter, &tcb );
366
367} /* cmpk_Handle_Tx_Feedback */
368
369void
370cmdpkt_beacontimerinterrupt_819xusb(
371 struct net_device *dev
372)
373{
374 struct r8192_priv *priv = ieee80211_priv(dev);
375 u16 tx_rate;
376 {
377 //
378 // 070117, rcnjko: 87B have to S/W beacon for DTM encryption_cmn.
379 //
380 if(priv->ieee80211->current_network.mode == IEEE_A ||
381 priv->ieee80211->current_network.mode == IEEE_N_5G ||
382 (priv->ieee80211->current_network.mode == IEEE_N_24G && (!priv->ieee80211->pHTInfo->bCurSuppCCK)))
383 {
384 tx_rate = 60;
385 DMESG("send beacon frame tx rate is 6Mbpm\n");
386 }
387 else
388 {
389 tx_rate =10;
390 DMESG("send beacon frame tx rate is 1Mbpm\n");
391 }
392
393 rtl819xusb_beacon_tx(dev,tx_rate); // HW Beacon
394
395 }
396
397}
398
399
400
401
402/*-----------------------------------------------------------------------------
403 * Function: cmpk_handle_interrupt_status()
404 *
405 * Overview: The function is responsible for extract the message from
406 * firmware. It will contain dedicated info in
407 * ws-07-0063-v06-rtl819x-command-packet-specification-070315.doc.
408 * Please refer to chapter "Interrupt Status Element".
409 *
410 * Input: struct net_device *dev,
411 * u8* pmsg - Message Pointer of the command packet.
412 *
413 * Output: NONE
414 *
415 * Return: NONE
416 *
417 * Revised History:
418 * When Who Remark
419 * 05/12/2008 amy Add this for rtl8192 porting from windows code.
420 *
421 *---------------------------------------------------------------------------*/
422static void
423cmpk_handle_interrupt_status(
424 struct net_device *dev,
425 u8* pmsg)
426{
427 cmpk_intr_sta_t rx_intr_status; /* */
428 struct r8192_priv *priv = ieee80211_priv(dev);
429
430 DMESG("---> cmpk_Handle_Interrupt_Status()\n");
431
432 /* 0. Display received message. */
433 //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg);
434
435 /* 1. Extract TX feedback info from RFD to temp structure buffer. */
436 /* It seems that FW use big endian(MIPS) and DRV use little endian in
437 windows OS. So we have to read the content byte by byte or transfer
438 endian type before copy the message copy. */
439 //rx_bcn_state.Element_ID = pMsg[0];
440 //rx_bcn_state.Length = pMsg[1];
441 rx_intr_status.length = pmsg[1];
442 if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2))
443 {
444 DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n");
445 return;
446 }
447
448
449 // Statistics of beacon for ad-hoc mode.
450 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC)
451 {
452 //2 maybe need endian transform?
453 rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4));
454 //rx_intr_status.InterruptStatus = N2H4BYTE(*((UINT32 *)(pMsg + 4)));
455
456 DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status);
457
458 if (rx_intr_status.interrupt_status & ISR_TxBcnOk)
459 {
460 priv->ieee80211->bibsscoordinator = true;
461 priv->stats.txbeaconokint++;
462 }
463 else if (rx_intr_status.interrupt_status & ISR_TxBcnErr)
464 {
465 priv->ieee80211->bibsscoordinator = false;
466 priv->stats.txbeaconerr++;
467 }
468
469 if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr)
470 {
471 cmdpkt_beacontimerinterrupt_819xusb(dev);
472 }
473
474 }
475
476 // Other informations in interrupt status we need?
477
478
479 DMESG("<---- cmpk_handle_interrupt_status()\n");
480
481} /* cmpk_handle_interrupt_status */
482
483
484/*-----------------------------------------------------------------------------
485 * Function: cmpk_handle_query_config_rx()
486 *
487 * Overview: The function is responsible for extract the message from
488 * firmware. It will contain dedicated info in
489 * ws-06-0063-rtl8190-command-packet-specification. Please
490 * refer to chapter "Beacon State Element".
491 *
492 * Input: u8 * pmsg - Message Pointer of the command packet.
493 *
494 * Output: NONE
495 *
496 * Return: NONE
497 *
498 * Revised History:
499 * When Who Remark
500 * 05/12/2008 amy Create Version 0 porting from windows code.
501 *
502 *---------------------------------------------------------------------------*/
503static void
504cmpk_handle_query_config_rx(
505 struct net_device *dev,
506 u8* pmsg)
507{
508 cmpk_query_cfg_t rx_query_cfg; /* */
509
510 /* 0. Display received message. */
511 //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg);
512
513 /* 1. Extract TX feedback info from RFD to temp structure buffer. */
514 /* It seems that FW use big endian(MIPS) and DRV use little endian in
515 windows OS. So we have to read the content byte by byte or transfer
516 endian type before copy the message copy. */
517 //rx_query_cfg.Element_ID = pMsg[0];
518 //rx_query_cfg.Length = pMsg[1];
519 rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31;
520 rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5;
521 rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3;
522 rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0;
523 rx_query_cfg.cfg_offset = pmsg[7];
524 rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) |
525 (pmsg[10] << 8) | (pmsg[11] << 0);
526 rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) |
527 (pmsg[14] << 8) | (pmsg[15] << 0);
528
529} /* cmpk_Handle_Query_Config_Rx */
530
531
532/*-----------------------------------------------------------------------------
533 * Function: cmpk_count_tx_status()
534 *
535 * Overview: Count aggregated tx status from firmwar of one type rx command
536 * packet element id = RX_TX_STATUS.
537 *
538 * Input: NONE
539 *
540 * Output: NONE
541 *
542 * Return: NONE
543 *
544 * Revised History:
545 * When Who Remark
546 * 05/12/2008 amy Create Version 0 porting from windows code.
547 *
548 *---------------------------------------------------------------------------*/
549static void cmpk_count_tx_status( struct net_device *dev,
550 cmpk_tx_status_t *pstx_status)
551{
552 struct r8192_priv *priv = ieee80211_priv(dev);
553
554#ifdef ENABLE_PS
555
556 RT_RF_POWER_STATE rtstate;
557
558 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
559
560 // When RF is off, we should not count the packet for hw/sw synchronize
561 // reason, ie. there may be a duration while sw switch is changed and hw
562 // switch is being changed. 2006.12.04, by shien chang.
563 if (rtState == eRfOff)
564 {
565 return;
566 }
567#endif
568
569 priv->stats.txfeedbackok += pstx_status->txok;
570 priv->stats.txoktotal += pstx_status->txok;
571
572 priv->stats.txfeedbackfail += pstx_status->txfail;
573 priv->stats.txerrtotal += pstx_status->txfail;
574
575 priv->stats.txretrycount += pstx_status->txretry;
576 priv->stats.txfeedbackretry += pstx_status->txretry;
577
578 //pAdapter->TxStats.NumTxOkBytesTotal += psTx_FB->pkt_length;
579 //pAdapter->TxStats.NumTxErrBytesTotal += psTx_FB->pkt_length;
580 //pAdapter->MgntInfo.LinkDetectInfo.NumTxOkInPeriod++;
581
582 priv->stats.txmulticast += pstx_status->txmcok;
583 priv->stats.txbroadcast += pstx_status->txbcok;
584 priv->stats.txunicast += pstx_status->txucok;
585
586 priv->stats.txerrmulticast += pstx_status->txmcfail;
587 priv->stats.txerrbroadcast += pstx_status->txbcfail;
588 priv->stats.txerrunicast += pstx_status->txucfail;
589
590 priv->stats.txbytesmulticast += pstx_status->txmclength;
591 priv->stats.txbytesbroadcast += pstx_status->txbclength;
592 priv->stats.txbytesunicast += pstx_status->txuclength;
593
594 priv->stats.last_packet_rate = pstx_status->rate;
595} /* cmpk_CountTxStatus */
596
597
598
599/*-----------------------------------------------------------------------------
600 * Function: cmpk_handle_tx_status()
601 *
602 * Overview: Firmware add a new tx feedback status to reduce rx command
603 * packet buffer operation load.
604 *
605 * Input: NONE
606 *
607 * Output: NONE
608 *
609 * Return: NONE
610 *
611 * Revised History:
612 * When Who Remark
613 * 05/12/2008 amy Create Version 0 porting from windows code.
614 *
615 *---------------------------------------------------------------------------*/
616static void
617cmpk_handle_tx_status(
618 struct net_device *dev,
619 u8* pmsg)
620{
621 cmpk_tx_status_t rx_tx_sts; /* */
622
623 memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(cmpk_tx_status_t));
624 /* 2. Use tx feedback info to count TX statistics. */
625 cmpk_count_tx_status(dev, &rx_tx_sts);
626
627} /* cmpk_Handle_Tx_Status */
628
629
630/*-----------------------------------------------------------------------------
631 * Function: cmpk_handle_tx_rate_history()
632 *
633 * Overview: Firmware add a new tx rate history
634 *
635 * Input: NONE
636 *
637 * Output: NONE
638 *
639 * Return: NONE
640 *
641 * Revised History:
642 * When Who Remark
643 * 05/12/2008 amy Create Version 0 porting from windows code.
644 *
645 *---------------------------------------------------------------------------*/
646static void
647cmpk_handle_tx_rate_history(
648 struct net_device *dev,
649 u8* pmsg)
650{
651 cmpk_tx_rahis_t *ptxrate;
652// RT_RF_POWER_STATE rtState;
653 u8 i, j;
654 u16 length = sizeof(cmpk_tx_rahis_t);
655 u32 *ptemp;
656 struct r8192_priv *priv = ieee80211_priv(dev);
657
658
659#ifdef ENABLE_PS
660 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
661
662 // When RF is off, we should not count the packet for hw/sw synchronize
663 // reason, ie. there may be a duration while sw switch is changed and hw
664 // switch is being changed. 2006.12.04, by shien chang.
665 if (rtState == eRfOff)
666 {
667 return;
668 }
669#endif
670
671 ptemp = (u32 *)pmsg;
672
673 //
674 // Do endian transfer to word alignment(16 bits) for windows system.
675 // You must do different endian transfer for linux and MAC OS
676 //
677 for (i = 0; i < (length/4); i++)
678 {
679 u16 temp1, temp2;
680
681 temp1 = ptemp[i]&0x0000FFFF;
682 temp2 = ptemp[i]>>16;
683 ptemp[i] = (temp1<<16)|temp2;
684 }
685
686 ptxrate = (cmpk_tx_rahis_t *)pmsg;
687
688 if (ptxrate == NULL )
689 {
690 return;
691 }
692
693 for (i = 0; i < 16; i++)
694 {
695 // Collect CCK rate packet num
696 if (i < 4)
697 priv->stats.txrate.cck[i] += ptxrate->cck[i];
698
699 // Collect OFDM rate packet num
700 if (i< 8)
701 priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i];
702
703 for (j = 0; j < 4; j++)
704 priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i];
705 }
706
707} /* cmpk_Handle_Tx_Rate_History */
708
709
710/*-----------------------------------------------------------------------------
711 * Function: cmpk_message_handle_rx()
712 *
713 * Overview: In the function, we will capture different RX command packet
714 * info. Every RX command packet element has different message
715 * length and meaning in content. We only support three type of RX
716 * command packet now. Please refer to document
717 * ws-06-0063-rtl8190-command-packet-specification.
718 *
719 * Input: NONE
720 *
721 * Output: NONE
722 *
723 * Return: NONE
724 *
725 * Revised History:
726 * When Who Remark
727 * 05/06/2008 amy Create Version 0 porting from windows code.
728 *
729 *---------------------------------------------------------------------------*/
730extern u32
731cmpk_message_handle_rx(
732 struct net_device *dev,
733 struct ieee80211_rx_stats *pstats)
734{
735// u32 debug_level = DBG_LOUD;
736 struct r8192_priv *priv = ieee80211_priv(dev);
737 int total_length;
738 u8 cmd_length, exe_cnt = 0;
739 u8 element_id;
740 u8 *pcmd_buff;
741
742 /* 0. Check inpt arguments. If is is a command queue message or pointer is
743 null. */
744 if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL))
745 {
746 /* Print error message. */
747 /*RT_TRACE(COMP_SEND, DebugLevel,
748 ("\n\r[CMPK]-->Err queue id or pointer"));*/
749 return 0; /* This is not a command packet. */
750 }
751
752 /* 1. Read received command packet message length from RFD. */
753 total_length = pstats->Length;
754
755 /* 2. Read virtual address from RFD. */
756 pcmd_buff = pstats->virtual_address;
757
758 /* 3. Read command pakcet element id and length. */
759 element_id = pcmd_buff[0];
760 /*RT_TRACE(COMP_SEND, DebugLevel,
761 ("\n\r[CMPK]-->element ID=%d Len=%d", element_id, total_length));*/
762
763 /* 4. Check every received command packet conent according to different
764 element type. Because FW may aggregate RX command packet to minimize
765 transmit time between DRV and FW.*/
766 // Add a counter to prevent to locked in the loop too long
767 while (total_length > 0 || exe_cnt++ >100)
768 {
769 /* 2007/01/17 MH We support aggregation of different cmd in the same packet. */
770 element_id = pcmd_buff[0];
771
772 switch(element_id)
773 {
774 case RX_TX_FEEDBACK:
775 cmpk_handle_tx_feedback (dev, pcmd_buff);
776 cmd_length = CMPK_RX_TX_FB_SIZE;
777 break;
778
779 case RX_INTERRUPT_STATUS:
780 cmpk_handle_interrupt_status(dev, pcmd_buff);
781 cmd_length = sizeof(cmpk_intr_sta_t);
782 break;
783
784 case BOTH_QUERY_CONFIG:
785 cmpk_handle_query_config_rx(dev, pcmd_buff);
786 cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE;
787 break;
788
789 case RX_TX_STATUS:
790 cmpk_handle_tx_status(dev, pcmd_buff);
791 cmd_length = CMPK_RX_TX_STS_SIZE;
792 break;
793
794 case RX_TX_PER_PKT_FEEDBACK:
795 // You must at lease add a switch case element here,
796 // Otherwise, we will jump to default case.
797 //DbgPrint("CCX Test\r\n");
798 cmd_length = CMPK_RX_TX_FB_SIZE;
799 break;
800
801 case RX_TX_RATE_HISTORY:
802 //DbgPrint(" rx tx rate history\r\n");
803 cmpk_handle_tx_rate_history(dev, pcmd_buff);
804 cmd_length = CMPK_TX_RAHIS_SIZE;
805 break;
806
807 default:
808
809 RT_TRACE(COMP_ERR, "---->cmpk_message_handle_rx():unknow CMD Element\n");
810 return 1; /* This is a command packet. */
811 }
812 // 2007/01/22 MH Display received rx command packet info.
813 //cmpk_Display_Message(cmd_length, pcmd_buff);
814
815 // 2007/01/22 MH Add to display tx statistic.
816 //cmpk_DisplayTxStatistic(pAdapter);
817
818 /* 2007/03/09 MH Collect sidderent cmd element pkt num. */
819 priv->stats.rxcmdpkt[element_id]++;
820
821 total_length -= cmd_length;
822 pcmd_buff += cmd_length;
823 } /* while (total_length > 0) */
824 return 1; /* This is a command packet. */
825
826} /* CMPK_Message_Handle_Rx */
diff --git a/drivers/staging/rtl8192su/r819xU_cmdpkt.h b/drivers/staging/rtl8192su/r819xU_cmdpkt.h
new file mode 100644
index 00000000000..f67af6cfd20
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_cmdpkt.h
@@ -0,0 +1,219 @@
1#ifndef R819XUSB_CMDPKT_H
2#define R819XUSB_CMDPKT_H
3/* Different command packet have dedicated message length and definition. */
4#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) //20
5#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
6#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
7#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)//
8#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)//
9#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
10
11/* 2008/05/08 amy For USB constant. */
12#define ISR_TxBcnOk BIT27 // Transmit Beacon OK
13#define ISR_TxBcnErr BIT26 // Transmit Beacon Error
14#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt
15
16#if 0
17/* Define packet type. */
18typedef enum tag_packet_type
19{
20 PACKET_BROADCAST,
21 PACKET_MULTICAST,
22 PACKET_UNICAST,
23 PACKET_TYPE_MAX
24}cmpk_pkt_type_e;
25#endif
26
27/* Define element ID of command packet. */
28
29/*------------------------------Define structure----------------------------*/
30/* Define different command packet structure. */
31/* 1. RX side: TX feedback packet. */
32typedef struct tag_cmd_pkt_tx_feedback
33{
34 // DWORD 0
35 u8 element_id; /* Command packet type. */
36 u8 length; /* Command packet length. */
37 /* 2007/07/05 MH Change tx feedback info field. */
38 /*------TX Feedback Info Field */
39 u8 TID:4; /* */
40 u8 fail_reason:3; /* */
41 u8 tok:1; /* Transmit ok. */
42 u8 reserve1:4; /* */
43 u8 pkt_type:2; /* */
44 u8 bandwidth:1; /* */
45 u8 qos_pkt:1; /* */
46
47 // DWORD 1
48 u8 reserve2; /* */
49 /*------TX Feedback Info Field */
50 u8 retry_cnt; /* */
51 u16 pkt_id; /* */
52
53 // DWORD 3
54 u16 seq_num; /* */
55 u8 s_rate; /* Start rate. */
56 u8 f_rate; /* Final rate. */
57
58 // DWORD 4
59 u8 s_rts_rate; /* */
60 u8 f_rts_rate; /* */
61 u16 pkt_length; /* */
62
63 // DWORD 5
64 u16 reserve3; /* */
65 u16 duration; /* */
66}cmpk_txfb_t;
67
68/* 2. RX side: Interrupt status packet. It includes Beacon State,
69 Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
70typedef struct tag_cmd_pkt_interrupt_status
71{
72 u8 element_id; /* Command packet type. */
73 u8 length; /* Command packet length. */
74 u16 reserve;
75 u32 interrupt_status; /* Interrupt Status. */
76}cmpk_intr_sta_t;
77
78
79/* 3. TX side: Set configuration packet. */
80typedef struct tag_cmd_pkt_set_configuration
81{
82 u8 element_id; /* Command packet type. */
83 u8 length; /* Command packet length. */
84 u16 reserve1; /* */
85 u8 cfg_reserve1:3;
86 u8 cfg_size:2; /* Configuration info. */
87 u8 cfg_type:2; /* Configuration info. */
88 u8 cfg_action:1; /* Configuration info. */
89 u8 cfg_reserve2; /* Configuration info. */
90 u8 cfg_page:4; /* Configuration info. */
91 u8 cfg_reserve3:4; /* Configuration info. */
92 u8 cfg_offset; /* Configuration info. */
93 u32 value; /* */
94 u32 mask; /* */
95}cmpk_set_cfg_t;
96
97/* 4. Both side : TX/RX query configuraton packet. The query structure is the
98 same as set configuration. */
99#define cmpk_query_cfg_t cmpk_set_cfg_t
100
101/* 5. Multi packet feedback status. */
102typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
103{
104 // For endian transfer --> Driver will not the same as firmware structure.
105 // DW 0
106 u16 reserve1;
107 u8 length; // Command packet length
108 u8 element_id; // Command packet type
109
110 // DW 1
111 u16 txfail; // Tx Fail count
112 u16 txok; // Tx ok count
113
114 // DW 2
115 u16 txmcok; // tx multicast
116 u16 txretry; // Tx Retry count
117
118 // DW 3
119 u16 txucok; // tx unicast
120 u16 txbcok; // tx broadcast
121
122 // DW 4
123 u16 txbcfail; //
124 u16 txmcfail; //
125
126 // DW 5
127 u16 reserve2; //
128 u16 txucfail; //
129
130 // DW 6-8
131 u32 txmclength;
132 u32 txbclength;
133 u32 txuclength;
134
135 // DW 9
136 u16 reserve3_23;
137 u8 reserve3_1;
138 u8 rate;
139}__attribute__((packed)) cmpk_tx_status_t;
140
141/* 6. Debug feedback message. */
142/* 2007/10/23 MH Define RX debug message */
143typedef struct tag_rx_debug_message_feedback
144{
145 // For endian transfer --> for driver
146 // DW 0
147 u16 reserve1;
148 u8 length; // Command packet length
149 u8 element_id; // Command packet type
150
151 // DW 1-??
152 // Variable debug message.
153
154}cmpk_rx_dbginfo_t;
155
156/* 2008/03/20 MH Define transmit rate history. For big endian format. */
157typedef struct tag_tx_rate_history
158{
159 // For endian transfer --> for driver
160 // DW 0
161 u8 element_id; // Command packet type
162 u8 length; // Command packet length
163 u16 reserved1;
164
165 // DW 1-2 CCK rate counter
166 u16 cck[4];
167
168 // DW 3-6
169 u16 ofdm[8];
170
171 // DW 7-14
172 //UINT16 MCS_BW0_SG0[16];
173
174 // DW 15-22
175 //UINT16 MCS_BW1_SG0[16];
176
177 // DW 23-30
178 //UINT16 MCS_BW0_SG1[16];
179
180 // DW 31-38
181 //UINT16 MCS_BW1_SG1[16];
182
183 // DW 7-14 BW=0 SG=0
184 // DW 15-22 BW=1 SG=0
185 // DW 23-30 BW=0 SG=1
186 // DW 31-38 BW=1 SG=1
187 u16 ht_mcs[4][16];
188
189}__attribute__((packed)) cmpk_tx_rahis_t;
190
191typedef enum tag_command_packet_directories
192{
193 RX_TX_FEEDBACK = 0,
194 RX_INTERRUPT_STATUS = 1,
195 TX_SET_CONFIG = 2,
196 BOTH_QUERY_CONFIG = 3,
197 RX_TX_STATUS = 4,
198 RX_DBGINFO_FEEDBACK = 5,
199 RX_TX_PER_PKT_FEEDBACK = 6,
200 RX_TX_RATE_HISTORY = 7,
201 RX_CMD_ELE_MAX
202}cmpk_element_e;
203
204#if 0
205typedef enum _rt_status{
206 RT_STATUS_SUCCESS,
207 RT_STATUS_FAILURE,
208 RT_STATUS_PENDING,
209 RT_STATUS_RESOURCE
210}rt_status,*prt_status;
211#endif
212
213extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
214
215extern u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats);
216extern bool SendTxCommandPacket( struct net_device *dev, void* pData, u32 DataLen);
217
218
219#endif
diff --git a/drivers/staging/rtl8192su/r819xU_firmware.c b/drivers/staging/rtl8192su/r819xU_firmware.c
new file mode 100644
index 00000000000..219f71e8cda
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_firmware.c
@@ -0,0 +1,707 @@
1/**************************************************************************************************
2 * Procedure: Init boot code/firmware code/data session
3 *
4 * Description: This routine will intialize firmware. If any error occurs during the initialization
5 * process, the routine shall terminate immediately and return fail.
6 * NIC driver should call NdisOpenFile only from MiniportInitialize.
7 *
8 * Arguments: The pointer of the adapter
9
10 * Returns:
11 * NDIS_STATUS_FAILURE - the following initialization process should be terminated
12 * NDIS_STATUS_SUCCESS - if firmware initialization process success
13**************************************************************************************************/
14//#include "ieee80211.h"
15#include "r8192U.h"
16#include "r8192U_hw.h"
17#include "r819xU_firmware_img.h"
18#include "r819xU_firmware.h"
19#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
20#include <linux/firmware.h>
21#endif
22void firmware_init_param(struct net_device *dev)
23{
24 struct r8192_priv *priv = ieee80211_priv(dev);
25 rt_firmware *pfirmware = priv->pFirmware;
26
27 pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
28}
29
30/*
31 * segment the img and use the ptr and length to remember info on each segment
32 *
33 */
34bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len)
35{
36 struct r8192_priv *priv = ieee80211_priv(dev);
37 bool rt_status = true;
38 u16 frag_threshold;
39 u16 frag_length, frag_offset = 0;
40 //u16 total_size;
41 int i;
42
43 rt_firmware *pfirmware = priv->pFirmware;
44 struct sk_buff *skb;
45 unsigned char *seg_ptr;
46 cb_desc *tcb_desc;
47 u8 bLastIniPkt;
48
49 firmware_init_param(dev);
50 //Fragmentation might be required
51 frag_threshold = pfirmware->cmdpacket_frag_thresold;
52 do {
53 if((buffer_len - frag_offset) > frag_threshold) {
54 frag_length = frag_threshold ;
55 bLastIniPkt = 0;
56
57 } else {
58 frag_length = buffer_len - frag_offset;
59 bLastIniPkt = 1;
60
61 }
62
63 /* Allocate skb buffer to contain firmware info and tx descriptor info
64 * add 4 to avoid packet appending overflow.
65 * */
66 #ifdef RTL8192U
67 skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4);
68 #else
69 skb = dev_alloc_skb(frag_length + 4);
70 #endif
71 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
72 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
73 tcb_desc->queue_index = TXCMD_QUEUE;
74 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
75 tcb_desc->bLastIniPkt = bLastIniPkt;
76
77 #ifdef RTL8192U
78 skb_reserve(skb, USB_HWDESC_HEADER_LEN);
79 #endif
80 seg_ptr = skb->data;
81 /*
82 * Transform from little endian to big endian
83 * and pending zero
84 */
85 for(i=0 ; i < frag_length; i+=4) {
86 *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0;
87 *seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0;
88 *seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0;
89 *seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0;
90 }
91 tcb_desc->txbuf_size= (u16)i;
92 skb_put(skb, i);
93
94 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
95 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
96 (priv->ieee80211->queue_stop) ) {
97 RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
98 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
99 } else {
100 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
101 }
102
103 code_virtual_address += frag_length;
104 frag_offset += frag_length;
105
106 }while(frag_offset < buffer_len);
107
108 return rt_status;
109
110#if 0
111cmdsend_downloadcode_fail:
112 rt_status = false;
113 RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n");
114 return rt_status;
115#endif
116}
117
118bool
119fwSendNullPacket(
120 struct net_device *dev,
121 u32 Length
122)
123{
124 bool rtStatus = true;
125 struct r8192_priv *priv = ieee80211_priv(dev);
126 struct sk_buff *skb;
127 cb_desc *tcb_desc;
128 unsigned char *ptr_buf;
129 bool bLastInitPacket = false;
130
131 //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
132
133 //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ)
134 skb = dev_alloc_skb(Length+ 4);
135 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
136 tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
137 tcb_desc->queue_index = TXCMD_QUEUE;
138 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
139 tcb_desc->bLastIniPkt = bLastInitPacket;
140 ptr_buf = skb_put(skb, Length);
141 memset(ptr_buf,0,Length);
142 tcb_desc->txbuf_size= (u16)Length;
143
144 if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)||
145 (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\
146 (priv->ieee80211->queue_stop) ) {
147 RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n");
148 skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb);
149 } else {
150 priv->ieee80211->softmac_hard_start_xmit(skb,dev);
151 }
152
153 //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
154 return rtStatus;
155}
156
157#if 0
158/*
159 * Procedure : Download code into IMEM or DMEM
160 * Description: This routine will intialize firmware. If any error occurs during the initialization
161 * process, the routine shall terminate immediately and return fail.
162 * The routine copy virtual address get from opening of file into shared memory
163 * allocated during initialization. If code size larger than a conitneous shared
164 * memory may contain, the code should be divided into several section.
165 * !!!NOTES This finction should only be called during MPInitialization because
166 * A NIC driver should call NdisOpenFile only from MiniportInitialize.
167 * Arguments : The pointer of the adapter
168 * Code address (Virtual address, should fill descriptor with physical address)
169 * Code size
170 * Returns :
171 * RT_STATUS_FAILURE - the following initialization process should be terminated
172 * RT_STATUS_SUCCESS - if firmware initialization process success
173 */
174bool fwsend_download_code(struct net_device *dev)
175{
176 struct r8192_priv *priv = ieee80211_priv(dev);
177 rt_firmware *pfirmware = (rt_firmware*)(&priv->firmware);
178
179 bool rt_status = true;
180 u16 length = 0;
181 u16 offset = 0;
182 u16 frag_threhold;
183 bool last_init_packet = false;
184 u32 check_txcmdwait_queueemptytime = 100000;
185 u16 cmd_buf_len;
186 u8 *ptr_cmd_buf;
187
188 /* reset to 0 for first segment of img download */
189 pfirmware->firmware_seg_index = 1;
190
191 if(pfirmware->firmware_seg_index == pfirmware->firmware_seg_maxnum) {
192 last_init_packet = 1;
193 }
194
195 cmd_buf_len = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_size;
196 ptr_cmd_buf = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_ptr;
197 rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT);
198
199 rt_status = true;
200 return rt_status;
201}
202#endif
203
204//-----------------------------------------------------------------------------
205// Procedure: Check whether main code is download OK. If OK, turn on CPU
206//
207// Description: CPU register locates in different page against general register.
208// Switch to CPU register in the begin and switch back before return
209//
210//
211// Arguments: The pointer of the adapter
212//
213// Returns:
214// NDIS_STATUS_FAILURE - the following initialization process should be terminated
215// NDIS_STATUS_SUCCESS - if firmware initialization process success
216//-----------------------------------------------------------------------------
217bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
218{
219 struct r8192_priv *priv = ieee80211_priv(dev);
220 bool rt_status = true;
221 int check_putcodeOK_time = 200000, check_bootOk_time = 200000;
222 u32 CPU_status = 0;
223
224 /* Check whether put code OK */
225 do {
226 CPU_status = read_nic_dword(dev, CPU_GEN);
227
228 if((CPU_status&CPU_GEN_PUT_CODE_OK) || (priv->usb_error==true))
229 break;
230
231 }while(check_putcodeOK_time--);
232
233 if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) {
234 RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n");
235 goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
236 } else {
237 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n");
238 }
239
240 /* Turn On CPU */
241 CPU_status = read_nic_dword(dev, CPU_GEN);
242 write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
243 mdelay(1000);
244
245 /* Check whether CPU boot OK */
246 do {
247 CPU_status = read_nic_dword(dev, CPU_GEN);
248
249 if((CPU_status&CPU_GEN_BOOT_RDY)||(priv->usb_error == true))
250 break;
251 }while(check_bootOk_time--);
252
253 if(!(CPU_status&CPU_GEN_BOOT_RDY)) {
254 goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
255 } else {
256 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n");
257 }
258
259 return rt_status;
260
261CPUCheckMainCodeOKAndTurnOnCPU_Fail:
262 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
263 rt_status = FALSE;
264 return rt_status;
265}
266
267bool CPUcheck_firmware_ready(struct net_device *dev)
268{
269 struct r8192_priv *priv = ieee80211_priv(dev);
270 bool rt_status = true;
271 int check_time = 200000;
272 u32 CPU_status = 0;
273
274 /* Check Firmware Ready */
275 do {
276 CPU_status = read_nic_dword(dev, CPU_GEN);
277
278 if((CPU_status&CPU_GEN_FIRM_RDY)||(priv->usb_error == true))
279 break;
280
281 }while(check_time--);
282
283 if(!(CPU_status&CPU_GEN_FIRM_RDY))
284 goto CPUCheckFirmwareReady_Fail;
285 else
286 RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n");
287
288 return rt_status;
289
290CPUCheckFirmwareReady_Fail:
291 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
292 rt_status = false;
293 return rt_status;
294
295}
296
297bool init_firmware(struct net_device *dev)
298{
299 struct r8192_priv *priv = ieee80211_priv(dev);
300 bool rt_status = TRUE;
301
302 u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0],
303 &rtl8190_fwmain_array[0],
304 &rtl8190_fwdata_array[0]};
305
306 u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array),
307 sizeof(rtl8190_fwmain_array),
308 sizeof(rtl8190_fwdata_array)};
309 u32 file_length = 0;
310 u8 *mapped_file = NULL;
311 u32 init_step = 0;
312 opt_rst_type_e rst_opt = OPT_SYSTEM_RESET;
313 firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
314
315 rt_firmware *pfirmware = priv->pFirmware;
316 const struct firmware *fw_entry;
317 const char *fw_name[3] = { "RTL8192U/boot.img",
318 "RTL8192U/main.img",
319 "RTL8192U/data.img"};
320 int rc;
321
322 RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n");
323
324 if (pfirmware->firmware_status == FW_STATUS_0_INIT ) {
325 /* it is called by reset */
326 rst_opt = OPT_SYSTEM_RESET;
327 starting_state = FW_INIT_STEP0_BOOT;
328 // TODO: system reset
329
330 }else if(pfirmware->firmware_status == FW_STATUS_5_READY) {
331 /* it is called by Initialize */
332 rst_opt = OPT_FIRMWARE_RESET;
333 starting_state = FW_INIT_STEP2_DATA;
334 }else {
335 RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n");
336 }
337
338 /*
339 * Download boot, main, and data image for System reset.
340 * Download data image for firmware reseta
341 */
342#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
343 priv->firmware_source = FW_SOURCE_HEADER_FILE;
344#else
345 priv->firmware_source = FW_SOURCE_IMG_FILE;
346#endif
347 for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) {
348 /*
349 * Open Image file, and map file to contineous memory if open file success.
350 * or read image file from array. Default load from IMG file
351 */
352 if(rst_opt == OPT_SYSTEM_RESET) {
353 switch(priv->firmware_source) {
354 case FW_SOURCE_IMG_FILE:
355#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
356 if(pfirmware->firmware_buf_size[init_step] == 0) {
357 rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev);
358 if(rc < 0 ) {
359 RT_TRACE(COMP_ERR, "request firmware fail!\n");
360 goto download_firmware_fail;
361 }
362
363 if(fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) {
364 //RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
365 RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!, entry_size = %d, buf_size = %d\n",fw_entry->size,sizeof(pfirmware->firmware_buf[init_step]));
366
367 goto download_firmware_fail;
368 }
369
370 if(init_step != FW_INIT_STEP1_MAIN) {
371 memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size);
372 pfirmware->firmware_buf_size[init_step] = fw_entry->size;
373 } else {
374#ifdef RTL8190P
375 memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size);
376 pfirmware->firmware_buf_size[init_step] = fw_entry->size;
377#else
378 memset(pfirmware->firmware_buf[init_step],0,128);
379 memcpy(&pfirmware->firmware_buf[init_step][128],fw_entry->data,fw_entry->size);
380 mapped_file = pfirmware->firmware_buf[init_step];
381 pfirmware->firmware_buf_size[init_step] = fw_entry->size+128;
382#endif
383 }
384 //pfirmware->firmware_buf_size = file_length;
385
386#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
387 if(rst_opt == OPT_SYSTEM_RESET) {
388 release_firmware(fw_entry);
389 }
390#endif
391 }
392 mapped_file = pfirmware->firmware_buf[init_step];
393 file_length = pfirmware->firmware_buf_size[init_step];
394#endif
395
396 break;
397
398 case FW_SOURCE_HEADER_FILE:
399 mapped_file = firmware_img_buf[init_step];
400 file_length = firmware_img_len[init_step];
401 if(init_step == FW_INIT_STEP2_DATA) {
402 memcpy(pfirmware->firmware_buf[init_step], mapped_file, file_length);
403 pfirmware->firmware_buf_size[init_step] = file_length;
404 }
405 break;
406
407 default:
408 break;
409 }
410
411
412 }else if(rst_opt == OPT_FIRMWARE_RESET ) {
413 /* we only need to download data.img here */
414 mapped_file = pfirmware->firmware_buf[init_step];
415 file_length = pfirmware->firmware_buf_size[init_step];
416 }
417
418 /* Download image file */
419 /* The firmware download process is just as following,
420 * 1. that is each packet will be segmented and inserted to the wait queue.
421 * 2. each packet segment will be put in the skb_buff packet.
422 * 3. each skb_buff packet data content will already include the firmware info
423 * and Tx descriptor info
424 * */
425 rt_status = fw_download_code(dev,mapped_file,file_length);
426
427 if(rt_status != TRUE) {
428 goto download_firmware_fail;
429 }
430
431 switch(init_step) {
432 case FW_INIT_STEP0_BOOT:
433 /* Download boot
434 * initialize command descriptor.
435 * will set polling bit when firmware code is also configured
436 */
437 pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE;
438#ifdef RTL8190P
439 // To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet
440 rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET);
441 if(rt_status != true)
442 {
443 RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n");
444 goto download_firmware_fail;
445 }
446#endif
447 //mdelay(1000);
448 /*
449 * To initialize IMEM, CPU move code from 0x80000080,
450 * hence, we send 0x80 byte packet
451 */
452 break;
453
454 case FW_INIT_STEP1_MAIN:
455 /* Download firmware code. Wait until Boot Ready and Turn on CPU */
456 pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE;
457
458 /* Check Put Code OK and Turn On CPU */
459 rt_status = CPUcheck_maincodeok_turnonCPU(dev);
460 if(rt_status != TRUE) {
461 RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n");
462 goto download_firmware_fail;
463 }
464
465 pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU;
466 break;
467
468 case FW_INIT_STEP2_DATA:
469 /* download initial data code */
470 pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE;
471 mdelay(1);
472
473 rt_status = CPUcheck_firmware_ready(dev);
474 if(rt_status != TRUE) {
475 RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status);
476 goto download_firmware_fail;
477 }
478
479 /* wait until data code is initialized ready.*/
480 pfirmware->firmware_status = FW_STATUS_5_READY;
481 break;
482 }
483 }
484
485 RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n");
486 //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n"));
487
488 return rt_status;
489
490download_firmware_fail:
491 RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__);
492 rt_status = FALSE;
493 return rt_status;
494
495}
496
497#if 0
498/*
499 * Procedure: (1) Transform firmware code from little endian to big endian if required.
500 * (2) Number of bytes in Firmware downloading should be multiple
501 * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required
502 *
503 */
504void CmdAppendZeroAndEndianTransform(
505 u1Byte *pDst,
506 u1Byte *pSrc,
507 u2Byte *pLength)
508{
509
510 u2Byte ulAppendBytes = 0, i;
511 u2Byte ulLength = *pLength;
512
513//test only
514 //memset(pDst, 0xcc, 12);
515
516
517 /* Transform from little endian to big endian */
518//#if DEV_BUS_TYPE==PCI_INTERFACE
519#if 0
520 for( i=0 ; i<(*pLength) ; i+=4)
521 {
522 if((i+3) < (*pLength)) pDst[i+0] = pSrc[i+3];
523 if((i+2) < (*pLength)) pDst[i+1] = pSrc[i+2];
524 if((i+1) < (*pLength)) pDst[i+2] = pSrc[i+1];
525 if((i+0) < (*pLength)) pDst[i+3] = pSrc[i+0];
526 }
527#else
528 pDst += USB_HWDESC_HEADER_LEN;
529 ulLength -= USB_HWDESC_HEADER_LEN;
530
531 for( i=0 ; i<ulLength ; i+=4) {
532 if((i+3) < ulLength) pDst[i+0] = pSrc[i+3];
533 if((i+2) < ulLength) pDst[i+1] = pSrc[i+2];
534 if((i+1) < ulLength) pDst[i+2] = pSrc[i+1];
535 if((i+0) < ulLength) pDst[i+3] = pSrc[i+0];
536
537 }
538#endif
539
540 //1(2) Append Zero
541 if( ((*pLength) % 4) >0)
542 {
543 ulAppendBytes = 4-((*pLength) % 4);
544
545 for(i=0 ; i<ulAppendBytes; i++)
546 pDst[ 4*((*pLength)/4) + i ] = 0x0;
547
548 *pLength += ulAppendBytes;
549 }
550}
551#endif
552
553#if 0
554RT_STATUS
555CmdSendPacket(
556 PADAPTER Adapter,
557 PRT_TCB pTcb,
558 PRT_TX_LOCAL_BUFFER pBuf,
559 u4Byte BufferLen,
560 u4Byte PacketType,
561 BOOLEAN bLastInitPacket
562 )
563{
564 s2Byte i;
565 u1Byte QueueID;
566 u2Byte firstDesc,curDesc = 0;
567 u2Byte FragIndex=0, FragBufferIndex=0;
568
569 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
570
571 CmdInitTCB(Adapter, pTcb, pBuf, BufferLen);
572
573
574 if(CmdCheckFragment(Adapter, pTcb, pBuf))
575 CmdFragmentTCB(Adapter, pTcb);
576 else
577 pTcb->FragLength[0] = (u2Byte)pTcb->BufferList[0].Length;
578
579 QueueID=pTcb->SpecifiedQueueID;
580#if DEV_BUS_TYPE!=USB_INTERFACE
581 firstDesc=curDesc=Adapter->NextTxDescToFill[QueueID];
582#endif
583
584#if DEV_BUS_TYPE!=USB_INTERFACE
585 if(VacancyTxDescNum(Adapter, QueueID) > pTcb->BufferCount)
586#else
587 if(PlatformIsTxQueueAvailable(Adapter, QueueID, pTcb->BufferCount) &&
588 RTIsListEmpty(&Adapter->TcbWaitQueue[QueueID]))
589#endif
590 {
591 pTcb->nDescUsed=0;
592
593 for(i=0 ; i<pTcb->BufferCount ; i++)
594 {
595 Adapter->HalFunc.TxFillCmdDescHandler(
596 Adapter,
597 pTcb,
598 QueueID, //QueueIndex
599 curDesc, //index
600 FragBufferIndex==0, //bFirstSeg
601 FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1), //bLastSeg
602 pTcb->BufferList[i].VirtualAddress, //VirtualAddress
603 pTcb->BufferList[i].PhysicalAddressLow, //PhyAddressLow
604 pTcb->BufferList[i].Length, //BufferLen
605 i!=0, //bSetOwnBit
606 (i==(pTcb->BufferCount-1)) && bLastInitPacket, //bLastInitPacket
607 PacketType, //DescPacketType
608 pTcb->FragLength[FragIndex] //PktLen
609 );
610
611 if(FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1))
612 { // Last segment of the fragment.
613 pTcb->nFragSent++;
614 }
615
616 FragBufferIndex++;
617 if(FragBufferIndex==pTcb->FragBufCount[FragIndex])
618 {
619 FragIndex++;
620 FragBufferIndex=0;
621 }
622
623#if DEV_BUS_TYPE!=USB_INTERFACE
624 curDesc=(curDesc+1)%Adapter->NumTxDesc[QueueID];
625#endif
626 pTcb->nDescUsed++;
627 }
628
629#if DEV_BUS_TYPE!=USB_INTERFACE
630 RTInsertTailList(&Adapter->TcbBusyQueue[QueueID], &pTcb->List);
631 IncrementTxDescToFill(Adapter, QueueID, pTcb->nDescUsed);
632 Adapter->HalFunc.SetTxDescOWNHandler(Adapter, QueueID, firstDesc);
633 // TODO: should call poll use QueueID
634 Adapter->HalFunc.TxPollingHandler(Adapter, TXCMD_QUEUE);
635#endif
636 }
637 else
638#if DEV_BUS_TYPE!=USB_INTERFACE
639 goto CmdSendPacket_Fail;
640#else
641 {
642 pTcb->bLastInitPacket = bLastInitPacket;
643 RTInsertTailList(&Adapter->TcbWaitQueue[pTcb->SpecifiedQueueID], &pTcb->List);
644 }
645#endif
646
647 return rtStatus;
648
649#if DEV_BUS_TYPE!=USB_INTERFACE
650CmdSendPacket_Fail:
651 rtStatus = RT_STATUS_FAILURE;
652 return rtStatus;
653#endif
654
655}
656#endif
657
658
659
660
661#if 0
662RT_STATUS
663FWSendNullPacket(
664 IN PADAPTER Adapter,
665 IN u4Byte Length
666)
667{
668 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
669
670
671 PRT_TCB pTcb;
672 PRT_TX_LOCAL_BUFFER pBuf;
673 BOOLEAN bLastInitPacket = FALSE;
674
675 PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
676
677#if DEV_BUS_TYPE==USB_INTERFACE
678 Length += USB_HWDESC_HEADER_LEN;
679#endif
680
681 //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ)
682 if(MgntGetBuffer(Adapter, &pTcb, &pBuf))
683 {
684 PlatformZeroMemory(pBuf->Buffer.VirtualAddress, Length);
685 rtStatus = CmdSendPacket(Adapter, pTcb, pBuf, Length, DESC_PACKET_TYPE_INIT, bLastInitPacket); //0 : always set LastInitPacket to zero
686//#if HAL_CODE_BASE != RTL8190HW
687// // TODO: for test only
688// ReturnTCB(Adapter, pTcb, RT_STATUS_SUCCESS);
689//#endif
690 if(rtStatus == RT_STATUS_FAILURE)
691 goto CmdSendNullPacket_Fail;
692 }else
693 goto CmdSendNullPacket_Fail;
694
695 PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
696 return rtStatus;
697
698
699CmdSendNullPacket_Fail:
700 PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
701 rtStatus = RT_STATUS_FAILURE;
702 RT_ASSERT(rtStatus == RT_STATUS_SUCCESS, ("CmdSendDownloadCode fail !!\n"));
703 return rtStatus;
704}
705#endif
706
707
diff --git a/drivers/staging/rtl8192su/r819xU_firmware.h b/drivers/staging/rtl8192su/r819xU_firmware.h
new file mode 100644
index 00000000000..10801be014e
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_firmware.h
@@ -0,0 +1,106 @@
1#ifndef __INC_FIRMWARE_H
2#define __INC_FIRMWARE_H
3
4#define RTL8190_CPU_START_OFFSET 0x80
5/* TODO: this definition is TBD */
6//#define USB_HWDESC_HEADER_LEN 0
7
8/* It should be double word alignment */
9//#if DEV_BUS_TYPE==PCI_INTERFACE
10//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
11//#else
12#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
13//#endif
14
15typedef enum _firmware_init_step{
16 FW_INIT_STEP0_BOOT = 0,
17 FW_INIT_STEP1_MAIN = 1,
18 FW_INIT_STEP2_DATA = 2,
19}firmware_init_step_e;
20
21typedef enum _opt_rst_type{
22 OPT_SYSTEM_RESET = 0,
23 OPT_FIRMWARE_RESET = 1,
24}opt_rst_type_e;
25
26/* due to rtl8192 firmware */
27typedef enum _desc_packet_type_e{
28 DESC_PACKET_TYPE_INIT = 0,
29 DESC_PACKET_TYPE_NORMAL = 1,
30}desc_packet_type_e;
31
32typedef enum _firmware_source{
33 FW_SOURCE_IMG_FILE = 0,
34 FW_SOURCE_HEADER_FILE = 1, //from header file
35}firmware_source_e, *pfirmware_source_e;
36
37typedef enum _firmware_status{
38 FW_STATUS_0_INIT = 0,
39 FW_STATUS_1_MOVE_BOOT_CODE = 1,
40 FW_STATUS_2_MOVE_MAIN_CODE = 2,
41 FW_STATUS_3_TURNON_CPU = 3,
42 FW_STATUS_4_MOVE_DATA_CODE = 4,
43 FW_STATUS_5_READY = 5,
44}firmware_status_e;
45
46typedef struct _rt_firmare_seg_container {
47 u16 seg_size;
48 u8 *seg_ptr;
49}fw_seg_container, *pfw_seg_container;
50
51#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
52#define MAX_FW_INIT_STEP 3
53typedef struct _rt_firmware{
54 firmware_status_e firmware_status;
55 u16 cmdpacket_frag_thresold;
56 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
57 u16 firmware_buf_size[MAX_FW_INIT_STEP];
58}rt_firmware, *prt_firmware;
59
60typedef struct _rt_firmware_info_819xUsb{
61 u8 sz_info[16];
62}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
63
64#if 0
65/* CPU related */
66RT_STATUS
67CPUCheckMainCodeOKAndTurnOnCPU(
68 IN PADAPTER Adapter
69 );
70
71RT_STATUS
72CPUCheckFirmwareReady(
73 IN PADAPTER Adapter
74 );
75
76/* Firmware related */
77VOID
78FWInitializeParameters(
79 IN PADAPTER Adapter
80 );
81
82RT_STATUS
83FWSendDownloadCode(
84 IN PADAPTER Adapter,
85 IN pu1Byte CodeVirtualAddrress,
86 IN u4Byte BufferLen
87 );
88
89RT_STATUS
90FWSendNullPacket(
91 IN PADAPTER Adapter,
92 IN u4Byte Length
93 );
94
95RT_STATUS
96CmdSendPacket(
97 PADAPTER Adapter,
98 PRT_TCB pTcb,
99 PRT_TX_LOCAL_BUFFER pBuf,
100 u4Byte BufferLen,
101 u4Byte PacketType,
102 BOOLEAN bLastInitPacket
103 );
104#endif
105#endif
106
diff --git a/drivers/staging/rtl8192su/r819xU_firmware_img.c b/drivers/staging/rtl8192su/r819xU_firmware_img.c
new file mode 100644
index 00000000000..29b656d7d82
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_firmware_img.c
@@ -0,0 +1,3447 @@
1/*Created on 2008/ 7/16, 5:31*/
2#include <linux/types.h>
3
4u8 rtl8190_fwboot_array[] = {
50x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08,
60x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00,
70x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
80x25,0x08,0xb0,0x50,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,
90x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b,
100x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00,
110x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
120x25,0x08,0xb0,0x50,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0,
130x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00,
140x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,
150x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,
160x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,
170x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01,
180x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24,
190x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00,
200x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10,
210x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
220x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,
230x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
240x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10,
250xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x4b,0x84,
260x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,};
27
28u8 rtl8190_fwmain_array[] = {
290x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
300x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
310x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
320x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
330x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
340x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
350x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
360x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
370x40,0x04,0x68,0x00,0x40,0x05,0x70,0x00,0x40,0x06,0x40,0x00,0x0c,0x00,0x12,0x94,
380x00,0x00,0x00,0x00,0x40,0x1a,0x68,0x00,0x33,0x5b,0x00,0x3c,0x17,0x60,0x00,0x09,
390x00,0x00,0x00,0x00,0x40,0x1b,0x60,0x00,0x00,0x00,0x00,0x00,0x03,0x5b,0xd0,0x24,
400x40,0x1a,0x70,0x00,0x03,0x40,0x00,0x08,0x42,0x00,0x00,0x10,0x00,0x00,0x00,0x00,
410x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0xff,0xff,0x8c,0x43,0x00,0x00,
420x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x00,0xd0,
430xac,0x62,0x00,0x00,0x00,0x00,0x20,0x21,0x27,0x85,0x8b,0x60,0x00,0x85,0x18,0x21,
440x24,0x84,0x00,0x01,0x28,0x82,0x00,0x0a,0x14,0x40,0xff,0xfc,0xa0,0x60,0x00,0x00,
450x27,0x82,0x8b,0x6a,0x24,0x04,0x00,0x06,0x24,0x84,0xff,0xff,0xa4,0x40,0x00,0x00,
460x04,0x81,0xff,0xfd,0x24,0x42,0x00,0x02,0x24,0x02,0x00,0x03,0xa3,0x82,0x8b,0x60,
470x24,0x02,0x09,0xc4,0x24,0x03,0x01,0x00,0xa7,0x82,0x8b,0x76,0x24,0x02,0x04,0x00,
480xaf,0x83,0x8b,0x78,0xaf,0x82,0x8b,0x7c,0x24,0x03,0x00,0x0a,0x24,0x02,0x00,0x04,
490x24,0x05,0x00,0x02,0x24,0x04,0x00,0x01,0xa3,0x83,0x8b,0x62,0xa3,0x82,0x8b,0x68,
500x24,0x03,0x00,0x01,0x24,0x02,0x02,0x00,0xa3,0x84,0x8b,0x66,0xa3,0x85,0x8b,0x69,
510xa7,0x82,0x8b,0x6a,0xa7,0x83,0x8b,0x6c,0xa3,0x84,0x8b,0x61,0xa3,0x80,0x8b,0x63,
520xa3,0x80,0x8b,0x64,0xa3,0x80,0x8b,0x65,0xa3,0x85,0x8b,0x67,0x03,0xe0,0x00,0x08,
530x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x01,0x84,
540x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x27,0x84,0x8b,0x88,0x00,0x00,0x10,0x21,
550x24,0x42,0x00,0x01,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,0x28,0x43,0x00,0x03,
560xac,0x80,0xff,0xfc,0xa0,0x80,0x00,0x00,0x14,0x60,0xff,0xf9,0x24,0x84,0x00,0x0c,
570x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
580x34,0x63,0x00,0x20,0x24,0x42,0x01,0xc8,0x3c,0x08,0xb0,0x03,0xac,0x62,0x00,0x00,
590x35,0x08,0x00,0x70,0x8d,0x02,0x00,0x00,0x00,0xa0,0x48,0x21,0x00,0x04,0x26,0x00,
600x00,0x02,0x2a,0x43,0x00,0x06,0x36,0x00,0x00,0x07,0x3e,0x00,0x00,0x02,0x12,0x03,
610x29,0x23,0x00,0x03,0x00,0x04,0x56,0x03,0x00,0x06,0x36,0x03,0x00,0x07,0x3e,0x03,
620x30,0x48,0x00,0x01,0x10,0x60,0x00,0x11,0x30,0xa5,0x00,0x07,0x24,0x02,0x00,0x02,
630x00,0x49,0x10,0x23,0x00,0x45,0x10,0x07,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x66,
640x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x02,0x21,0x43,
650x11,0x00,0x00,0x10,0x00,0x07,0x20,0x0b,0x15,0x20,0x00,0x06,0x24,0x02,0x00,0x01,
660x3c,0x02,0xb0,0x05,0x34,0x42,0x01,0x20,0xa4,0x44,0x00,0x00,0x03,0xe0,0x00,0x08,
670x00,0x00,0x00,0x00,0x11,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,
680x08,0x00,0x00,0x96,0x34,0x42,0x01,0x24,0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x96,
690x34,0x42,0x01,0x22,0x15,0x20,0x00,0x54,0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x03,
700x34,0x42,0x00,0x74,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0x84,
710x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x70,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
720x30,0x6b,0x00,0x08,0x11,0x60,0x00,0x18,0x00,0x09,0x28,0x40,0x00,0x00,0x40,0x21,
730x27,0x85,0x8b,0x80,0x8c,0xa3,0x00,0x00,0x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,
740x00,0x62,0x38,0x23,0x00,0x43,0x10,0x2a,0x10,0x40,0x00,0x3d,0x00,0x00,0x00,0x00,
750xac,0xa7,0x00,0x00,0x25,0x02,0x00,0x01,0x00,0x02,0x16,0x00,0x00,0x02,0x46,0x03,
760x29,0x03,0x00,0x03,0x14,0x60,0xff,0xf3,0x24,0xa5,0x00,0x0c,0x3c,0x03,0xb0,0x03,
770x34,0x63,0x00,0x70,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4b,0x10,0x23,
780xa0,0x62,0x00,0x00,0x00,0x09,0x28,0x40,0x00,0xa9,0x10,0x21,0x00,0x02,0x10,0x80,
790x27,0x83,0x8b,0x88,0x00,0x0a,0x20,0x0b,0x00,0x43,0x18,0x21,0x10,0xc0,0x00,0x05,
800x00,0x00,0x38,0x21,0x80,0x62,0x00,0x01,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,
810x00,0x00,0x00,0x00,0x80,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,
820x00,0xa9,0x10,0x21,0x24,0x07,0x00,0x01,0x00,0xa9,0x10,0x21,0x00,0x02,0x30,0x80,
830x27,0x82,0x8b,0x88,0xa0,0x67,0x00,0x01,0x00,0xc2,0x38,0x21,0x80,0xe3,0x00,0x01,
840x00,0x00,0x00,0x00,0x10,0x60,0x00,0x07,0x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x80,
850x00,0xc3,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x21,
860xac,0x62,0x00,0x00,0x27,0x85,0x8b,0x84,0x27,0x82,0x8b,0x80,0x00,0xc5,0x28,0x21,
870x00,0xc2,0x10,0x21,0x8c,0x43,0x00,0x00,0x8c,0xa4,0x00,0x00,0x00,0x00,0x00,0x00,
880x00,0x64,0x18,0x2a,0x14,0x60,0x00,0x03,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,
890xa0,0xe2,0x00,0x00,0xa0,0xe0,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
900x08,0x00,0x00,0xb9,0xac,0xa0,0x00,0x00,0x11,0x22,0x00,0x08,0x00,0x00,0x00,0x00,
910x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x7c,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
920xaf,0x83,0x8b,0x9c,0x08,0x00,0x00,0xa9,0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x03,
930x34,0x42,0x00,0x78,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0x90,
940x08,0x00,0x00,0xa9,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
950x34,0x63,0x00,0x20,0x24,0x42,0x04,0x18,0x3c,0x05,0xb0,0x03,0xac,0x62,0x00,0x00,
960x34,0xa5,0x00,0x70,0x8c,0xa2,0x00,0x00,0x90,0x84,0x00,0x08,0x3c,0x06,0xb0,0x03,
970x00,0x02,0x16,0x00,0x2c,0x83,0x00,0x03,0x34,0xc6,0x00,0x72,0x24,0x07,0x00,0x01,
980x10,0x60,0x00,0x11,0x00,0x02,0x2f,0xc2,0x90,0xc2,0x00,0x00,0x00,0x00,0x18,0x21,
990x00,0x02,0x16,0x00,0x10,0xa7,0x00,0x09,0x00,0x02,0x16,0x03,0x14,0x80,0x00,0x0c,
1000x30,0x43,0x00,0x03,0x83,0x82,0x8b,0x88,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,
1010x00,0x43,0x10,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x1e,0x03,0x3c,0x02,0xb0,0x03,
1020x34,0x42,0x00,0x72,0xa0,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
1030x30,0x45,0x00,0x05,0x10,0x87,0x00,0x04,0x30,0x43,0x00,0x06,0x93,0x82,0x8b,0xa0,
1040x08,0x00,0x01,0x21,0x00,0x43,0x10,0x21,0x83,0x82,0x8b,0x94,0x00,0x00,0x00,0x00,
1050x00,0x02,0x10,0x40,0x08,0x00,0x01,0x21,0x00,0x45,0x10,0x21,0x10,0x80,0x00,0x05,
1060x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,0x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,
1070x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
1080x3c,0x02,0x80,0x00,0x24,0x42,0x04,0xec,0x3c,0x04,0xb0,0x02,0x34,0x63,0x00,0x20,
1090xac,0x62,0x00,0x00,0x34,0x84,0x00,0x08,0x24,0x02,0x00,0x01,0xaf,0x84,0x8b,0xb0,
1100xa3,0x82,0x8b,0xc0,0xa7,0x80,0x8b,0xb4,0xa7,0x80,0x8b,0xb6,0xaf,0x80,0x8b,0xb8,
1110xaf,0x80,0x8b,0xbc,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
1120x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x05,0x2c,0x3c,0x04,0xb0,0x03,
1130xac,0x62,0x00,0x00,0x34,0x84,0x00,0xac,0x80,0xa2,0x00,0x15,0x8c,0x83,0x00,0x00,
1140x27,0xbd,0xff,0xf0,0x00,0x43,0x10,0x21,0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,
1150x27,0xbd,0x00,0x10,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,
1160x24,0x63,0x05,0x64,0x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00,0xaf,0xb1,0x00,0x14,
1170xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,0x8f,0x90,0x8b,0xb0,0x0c,0x00,0x02,0x9a,
1180x00,0x80,0x88,0x21,0x14,0x40,0x00,0x2a,0x3c,0x02,0x00,0x80,0x16,0x20,0x00,0x02,
1190x34,0x42,0x02,0x01,0x24,0x02,0x02,0x01,0xae,0x02,0x00,0x00,0x97,0x84,0x8b,0xb4,
1200x97,0x82,0x8b,0xb6,0x3c,0x03,0xb0,0x02,0x00,0x83,0x20,0x21,0x24,0x42,0x00,0x04,
1210xa7,0x82,0x8b,0xb6,0xa4,0x82,0x00,0x00,0x8f,0x84,0x8b,0xb8,0x8f,0x82,0x8b,0xb0,
1220x93,0x85,0x8b,0x62,0x24,0x84,0x00,0x01,0x24,0x42,0x00,0x04,0x24,0x03,0x8f,0xff,
1230x3c,0x07,0xb0,0x06,0x3c,0x06,0xb0,0x03,0x00,0x43,0x10,0x24,0x00,0x85,0x28,0x2a,
1240x34,0xe7,0x80,0x18,0xaf,0x82,0x8b,0xb0,0xaf,0x84,0x8b,0xb8,0x10,0xa0,0x00,0x08,
1250x34,0xc6,0x01,0x08,0x8f,0x83,0x8b,0xbc,0x8f,0x84,0x8b,0x7c,0x8c,0xc2,0x00,0x00,
1260x00,0x64,0x18,0x21,0x00,0x43,0x10,0x2b,0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,
1270x8c,0xe2,0x00,0x00,0x3c,0x03,0x0f,0x00,0x3c,0x04,0x04,0x00,0x00,0x43,0x10,0x24,
1280x10,0x44,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x98,0x00,0x00,0x00,0x00,
1290x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
1300x27,0xbd,0xff,0xd8,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x24,0x63,0x06,0x50,
1310xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20,0x8f,0x90,0x8b,0xb0,0xac,0x43,0x00,0x00,
1320xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,
1330x00,0x80,0x88,0x21,0x00,0xa0,0x90,0x21,0x0c,0x00,0x02,0x9a,0x00,0xc0,0x98,0x21,
1340x24,0x07,0x8f,0xff,0x14,0x40,0x00,0x19,0x26,0x03,0x00,0x04,0x24,0x02,0x0e,0x03,
1350xae,0x02,0x00,0x00,0x00,0x67,0x80,0x24,0x26,0x02,0x00,0x04,0xae,0x11,0x00,0x00,
1360x00,0x47,0x80,0x24,0x97,0x86,0x8b,0xb4,0x26,0x03,0x00,0x04,0xae,0x12,0x00,0x00,
1370x00,0x67,0x80,0x24,0xae,0x13,0x00,0x00,0x8f,0x84,0x8b,0xb0,0x3c,0x02,0xb0,0x02,
1380x97,0x85,0x8b,0xb6,0x00,0xc2,0x30,0x21,0x8f,0x82,0x8b,0xb8,0x24,0x84,0x00,0x10,
1390x24,0xa5,0x00,0x10,0x00,0x87,0x20,0x24,0x24,0x42,0x00,0x01,0xa7,0x85,0x8b,0xb6,
1400xaf,0x84,0x8b,0xb0,0xaf,0x82,0x8b,0xb8,0xa4,0xc5,0x00,0x00,0x8f,0xbf,0x00,0x20,
1410x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
1420x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x94,0x82,0x00,0x04,0x00,0x00,0x00,0x00,
1430x30,0x42,0xe0,0x00,0x14,0x40,0x00,0x14,0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x02,
1440x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfc,0x00,0x82,0x28,0x21,0x8c,0xa4,0x00,0x00,
1450x3c,0x02,0x00,0x70,0x8c,0xa6,0x00,0x08,0x00,0x82,0x10,0x21,0x2c,0x43,0x00,0x06,
1460x10,0x60,0x00,0x09,0x3c,0x03,0x80,0x01,0x00,0x02,0x10,0x80,0x24,0x63,0x01,0xe8,
1470x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,
1480x00,0x00,0x00,0x00,0xaf,0x86,0x80,0x14,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
1490x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x8c,0xa4,0x00,0x00,0x0c,0x00,0x17,0xb3,
1500x00,0x00,0x00,0x00,0x08,0x00,0x01,0xde,0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0xaa,
1510x00,0xc0,0x20,0x21,0x08,0x00,0x01,0xde,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
1520x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x82,0x80,0x18,0x3c,0x03,0x00,0x0f,
1530x34,0x63,0x42,0x40,0x00,0x43,0x10,0x21,0x00,0x82,0x20,0x2b,0x10,0x80,0x00,0x09,
1540x24,0x03,0x00,0x05,0x8f,0x82,0x83,0x30,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
1550xaf,0x82,0x83,0x30,0x10,0x43,0x00,0x03,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
1560x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x8c,0x63,0x01,0x08,0x24,0x02,0x00,0x01,
1570xa3,0x82,0x80,0x11,0xaf,0x80,0x83,0x30,0xaf,0x83,0x80,0x18,0x08,0x00,0x01,0xfb,
1580x00,0x00,0x00,0x00,0x30,0x84,0x00,0xff,0x14,0x80,0x00,0x2f,0x00,0x00,0x00,0x00,
1590x8f,0x82,0x80,0x14,0xa3,0x85,0x83,0x63,0x10,0x40,0x00,0x2b,0x2c,0xa2,0x00,0x04,
1600x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xfc,0x2c,0x42,0x00,0x08,
1610x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xf0,0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x6c,
1620x00,0x44,0x10,0x21,0x94,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,
1630x03,0xe0,0x00,0x08,0xa4,0x43,0x00,0x00,0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,
1640x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xe0,0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x06,
1650x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xd0,0x2c,0x42,0x00,0x10,0x10,0x40,0x00,0x09,
1660x24,0xa2,0xff,0xc0,0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x6c,0x00,0x44,0x10,0x21,
1670x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,
1680xa4,0x43,0xff,0xf8,0x2c,0x42,0x00,0x10,0x10,0x40,0x00,0x07,0x00,0x05,0x10,0x40,
1690x27,0x84,0x83,0x6c,0x00,0x44,0x10,0x21,0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,
1700x24,0x63,0x00,0x01,0xa4,0x43,0xff,0xf8,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
1710x8f,0x86,0x8b,0xb0,0x8f,0x82,0x80,0x14,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
1720x10,0x40,0x00,0x2a,0x00,0xc0,0x38,0x21,0x24,0x02,0x00,0x07,0x24,0x03,0xff,0x9c,
1730xa3,0x82,0x83,0x6b,0xa3,0x83,0x83,0x6a,0x27,0x8a,0x83,0x68,0x00,0x00,0x20,0x21,
1740x24,0x09,0x8f,0xff,0x00,0x04,0x10,0x80,0x00,0x4a,0x28,0x21,0x8c,0xa2,0x00,0x00,
1750x24,0xe3,0x00,0x04,0x24,0x88,0x00,0x01,0xac,0xe2,0x00,0x00,0x10,0x80,0x00,0x02,
1760x00,0x69,0x38,0x24,0xac,0xa0,0x00,0x00,0x31,0x04,0x00,0xff,0x2c,0x82,0x00,0x27,
1770x14,0x40,0xff,0xf5,0x00,0x04,0x10,0x80,0x97,0x83,0x8b,0xb6,0x97,0x85,0x8b,0xb4,
1780x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x9c,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,
1790xa7,0x83,0x8b,0xb6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,
1800x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x9c,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,
1810x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xb0,0x10,0xa2,0x00,0x03,
1820x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x98,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,
1830x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x8f,0x86,0x8b,0xb0,
1840x27,0xbd,0xff,0xc8,0x24,0x02,0x00,0x08,0x24,0x03,0x00,0x20,0xaf,0xbf,0x00,0x30,
1850xa3,0xa2,0x00,0x13,0xa3,0xa3,0x00,0x12,0xa7,0xa4,0x00,0x10,0x00,0xc0,0x28,0x21,
1860x27,0xa9,0x00,0x10,0x00,0x00,0x38,0x21,0x24,0x08,0x8f,0xff,0x00,0x07,0x10,0x80,
1870x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,
1880x24,0xa2,0x00,0x04,0x2c,0xe3,0x00,0x08,0xac,0xa4,0x00,0x00,0x14,0x60,0xff,0xf7,
1890x00,0x48,0x28,0x24,0x97,0x83,0x8b,0xb6,0x97,0x85,0x8b,0xb4,0x3c,0x02,0xb0,0x02,
1900x24,0x63,0x00,0x20,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xb6,
1910x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,
1920x24,0xc6,0x00,0x20,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,
1930x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xb0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,
1940x0c,0x00,0x04,0x98,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x30,0x00,0x00,0x00,0x00,
1950x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x93,0x82,0x8b,0xc0,0x00,0x00,0x00,0x00,
1960x10,0x40,0x00,0x11,0x24,0x06,0x00,0x01,0x8f,0x82,0x8b,0xb8,0x3c,0x05,0xb0,0x06,
1970x3c,0x04,0xb0,0x03,0x34,0xa5,0x80,0x18,0x34,0x84,0x01,0x08,0x14,0x40,0x00,0x09,
1980x00,0x00,0x30,0x21,0x97,0x82,0x8b,0xb4,0x8c,0x84,0x00,0x00,0x3c,0x03,0xb0,0x02,
1990x00,0x43,0x10,0x21,0xaf,0x84,0x8b,0xbc,0xa7,0x80,0x8b,0xb6,0xac,0x40,0x00,0x00,
2000xac,0x40,0x00,0x04,0x8c,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,
2010x8f,0x86,0x8b,0xb0,0x8f,0x82,0x8b,0xb8,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
2020x00,0xc0,0x40,0x21,0x14,0x40,0x00,0x0a,0x00,0x40,0x50,0x21,0x00,0x00,0x38,0x21,
2030x27,0x89,0x83,0x38,0x24,0xe2,0x00,0x01,0x00,0x07,0x18,0x80,0x30,0x47,0x00,0xff,
2040x00,0x69,0x18,0x21,0x2c,0xe2,0x00,0x0a,0x14,0x40,0xff,0xfa,0xac,0x60,0x00,0x00,
2050x3c,0x02,0x00,0x80,0x10,0x82,0x00,0x6f,0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x3e,
2060x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x3e,0x90,0xa3,0x00,0x15,
2070x97,0x82,0x83,0x40,0x00,0x03,0x1e,0x00,0x00,0x03,0x1e,0x03,0x00,0x43,0x10,0x21,
2080xa7,0x82,0x83,0x40,0x8c,0xa4,0x00,0x20,0x3c,0x02,0x00,0x60,0x3c,0x03,0x00,0x20,
2090x00,0x82,0x20,0x24,0x10,0x83,0x00,0x54,0x00,0x00,0x00,0x00,0x14,0x80,0x00,0x47,
2100x00,0x00,0x00,0x00,0x97,0x82,0x83,0x44,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
2110xa7,0x82,0x83,0x44,0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x54,0x00,0x00,0x00,0x00,
2120x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x54,0x25,0x42,0x00,0x01,0x28,0x43,0x27,0x10,
2130xaf,0x82,0x8b,0xb8,0x10,0x60,0x00,0x09,0x24,0x02,0x00,0x04,0x93,0x83,0x80,0x11,
2140x24,0x02,0x00,0x01,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x10,
2150x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x24,0x03,0x00,0x28,
2160xa3,0x83,0x83,0x3a,0xa3,0x82,0x83,0x3b,0x90,0xa2,0x00,0x18,0x93,0x83,0x83,0x63,
2170x00,0x00,0x38,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,0xa7,0x82,0x83,0x4e,
2180xa3,0x83,0x83,0x5c,0x27,0x89,0x83,0x38,0x24,0x05,0x8f,0xff,0x00,0x07,0x10,0x80,
2190x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,
2200x25,0x02,0x00,0x04,0x2c,0xe3,0x00,0x0a,0xad,0x04,0x00,0x00,0x14,0x60,0xff,0xf7,
2210x00,0x45,0x40,0x24,0x97,0x83,0x8b,0xb6,0x97,0x85,0x8b,0xb4,0x3c,0x02,0xb0,0x02,
2220x24,0x63,0x00,0x28,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xb6,
2230x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,
2240x24,0xc6,0x00,0x28,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,
2250x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xb0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,
2260x0c,0x00,0x04,0x98,0x00,0x00,0x00,0x00,0x0c,0x00,0x02,0x38,0x00,0x00,0x00,0x00,
2270xa3,0x80,0x80,0x11,0x08,0x00,0x02,0xe7,0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x46,
2280x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x46,0x84,0xa3,0x00,0x06,
2290x8f,0x82,0x83,0x58,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x58,
2300x08,0x00,0x02,0xdf,0x25,0x42,0x00,0x01,0x97,0x82,0x83,0x42,0x00,0x00,0x00,0x00,
2310x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x42,0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x50,
2320x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x50,0x08,0x00,0x02,0xdf,
2330x25,0x42,0x00,0x01,0x97,0x82,0x83,0x3c,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
2340xa7,0x82,0x83,0x3c,0x08,0x00,0x02,0xc7,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd0,
2350xaf,0xbf,0x00,0x28,0x8c,0xa3,0x00,0x20,0x8f,0x8a,0x8b,0xb0,0x3c,0x02,0x00,0x10,
2360x00,0x62,0x10,0x24,0x00,0xa0,0x38,0x21,0x01,0x40,0x48,0x21,0x10,0x40,0x00,0x3d,
2370x00,0x80,0x28,0x21,0x8c,0xe4,0x00,0x1c,0x34,0xa5,0x12,0x06,0xaf,0xa5,0x00,0x10,
2380x8c,0x82,0x00,0x08,0x00,0x03,0x1c,0x42,0x30,0x63,0x00,0x30,0x00,0x02,0x13,0x02,
2390x30,0x42,0x00,0x40,0x00,0x43,0x10,0x25,0x90,0xe6,0x00,0x10,0x90,0xe4,0x00,0x13,
2400x94,0xe8,0x00,0x0c,0x94,0xe3,0x00,0x1a,0x00,0x02,0x16,0x00,0x90,0xe7,0x00,0x12,
2410x00,0xa2,0x28,0x25,0x24,0x02,0x12,0x34,0xa7,0xa2,0x00,0x1c,0x24,0x02,0x56,0x78,
2420xaf,0xa5,0x00,0x10,0xa3,0xa6,0x00,0x18,0xa3,0xa7,0x00,0x1f,0xa7,0xa3,0x00,0x1a,
2430xa3,0xa4,0x00,0x19,0xa7,0xa8,0x00,0x20,0xa7,0xa2,0x00,0x22,0x00,0x00,0x28,0x21,
2440x27,0xa7,0x00,0x10,0x24,0x06,0x8f,0xff,0x00,0x05,0x10,0x80,0x00,0x47,0x10,0x21,
2450x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01,0x30,0x65,0x00,0xff,0x25,0x22,0x00,0x04,
2460x2c,0xa3,0x00,0x05,0xad,0x24,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x46,0x48,0x24,
2470x97,0x83,0x8b,0xb6,0x97,0x85,0x8b,0xb4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x14,
2480x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xb6,0x34,0x84,0x80,0x18,
2490xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x25,0x46,0x00,0x14,
2500x3c,0x03,0x0f,0x00,0x00,0xc2,0x50,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,
2510xaf,0x8a,0x8b,0xb0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x98,
2520x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x28,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
2530x27,0xbd,0x00,0x30,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,
2540x00,0x04,0x22,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x0e,0x04,0x3c,0x03,0xb0,0x00,
2550xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,
2560xaf,0xbf,0x00,0x30,0x00,0x83,0x80,0x21,0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,
2570xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xac,0xa2,0x00,0x00,0x8e,0x09,0x00,0x00,
2580x00,0x00,0x90,0x21,0x26,0x10,0x00,0x08,0x00,0x09,0xa6,0x02,0x12,0x80,0x00,0x13,
2590x00,0x00,0xa8,0x21,0x24,0x13,0x00,0x02,0x3c,0x16,0x00,0xff,0x3c,0x17,0xff,0x00,
2600x8e,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x12,0x02,0x24,0x42,0x00,0x02,
2610x31,0x25,0x00,0xff,0x10,0xb3,0x00,0x76,0x30,0x51,0x00,0xff,0x24,0x02,0x00,0x03,
2620x10,0xa2,0x00,0x18,0x00,0x00,0x00,0x00,0x02,0x51,0x10,0x21,0x30,0x52,0xff,0xff,
2630x02,0x54,0x18,0x2b,0x14,0x60,0xff,0xf2,0x02,0x11,0x80,0x21,0x12,0xa0,0x00,0x0a,
2640x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,0x8c,0x43,0x00,0x00,0x3c,0x04,0x0f,0x00,
2650x3c,0x02,0x04,0x00,0x00,0x64,0x18,0x24,0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,
2660x0c,0x00,0x04,0x98,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,
2670x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
2680x27,0xbd,0x00,0x38,0x8e,0x09,0x00,0x04,0x24,0x15,0x00,0x01,0x8e,0x06,0x00,0x0c,
2690x00,0x09,0x11,0x42,0x00,0x09,0x18,0xc2,0x30,0x48,0x00,0x03,0x00,0x09,0x14,0x02,
2700x30,0x6c,0x00,0x03,0x00,0x09,0x26,0x02,0x11,0x15,0x00,0x45,0x30,0x43,0x00,0x0f,
2710x29,0x02,0x00,0x02,0x14,0x40,0x00,0x26,0x00,0x00,0x00,0x00,0x11,0x13,0x00,0x0f,
2720x00,0x00,0x38,0x21,0x00,0x07,0x22,0x02,0x30,0x84,0xff,0x00,0x3c,0x03,0x00,0xff,
2730x00,0x07,0x2e,0x02,0x00,0x07,0x12,0x00,0x00,0x43,0x10,0x24,0x00,0xa4,0x28,0x25,
2740x00,0xa2,0x28,0x25,0x00,0x07,0x1e,0x00,0x00,0xa3,0x28,0x25,0x0c,0x00,0x01,0x94,
2750x01,0x20,0x20,0x21,0x08,0x00,0x03,0xa7,0x02,0x51,0x10,0x21,0x11,0x95,0x00,0x0f,
2760x00,0x00,0x00,0x00,0x11,0x88,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x80,
2770x27,0x83,0x8b,0x60,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,0x08,0x00,0x03,0xce,
2780x00,0x07,0x22,0x02,0x00,0x04,0x10,0x40,0x27,0x83,0x8b,0x68,0x00,0x43,0x10,0x21,
2790x94,0x47,0x00,0x02,0x08,0x00,0x03,0xce,0x00,0x07,0x22,0x02,0x27,0x82,0x8b,0x60,
2800x00,0x82,0x10,0x21,0x90,0x47,0x00,0x00,0x08,0x00,0x03,0xce,0x00,0x07,0x22,0x02,
2810x15,0x00,0xff,0xdc,0x00,0x00,0x38,0x21,0x10,0x75,0x00,0x05,0x00,0x80,0x38,0x21,
2820x00,0x65,0x18,0x26,0x24,0x82,0x01,0x00,0x00,0x00,0x38,0x21,0x00,0x43,0x38,0x0a,
2830x24,0x02,0x00,0x01,0x11,0x82,0x00,0x0e,0x3c,0x02,0xb0,0x03,0x24,0x02,0x00,0x02,
2840x11,0x82,0x00,0x06,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,
2850x8c,0x47,0x00,0x00,0x08,0x00,0x03,0xce,0x00,0x07,0x22,0x02,0x3c,0x02,0xb0,0x03,
2860x00,0xe2,0x10,0x21,0x94,0x43,0x00,0x00,0x08,0x00,0x03,0xcd,0x30,0x67,0xff,0xff,
2870x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00,0x08,0x00,0x03,0xcd,0x30,0x67,0x00,0xff,
2880x30,0x62,0x00,0x03,0x00,0x02,0x12,0x00,0x11,0x95,0x00,0x07,0x00,0x44,0x38,0x21,
2890x11,0x93,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x03,0xff,0x3c,0x02,0xb0,0x0a,
2900x08,0x00,0x04,0x04,0x3c,0x02,0xb0,0x0a,0x08,0x00,0x04,0x08,0x3c,0x02,0xb0,0x0a,
2910x8e,0x09,0x00,0x04,0x8e,0x02,0x00,0x08,0x8e,0x03,0x00,0x0c,0x00,0x09,0x41,0x42,
2920x00,0x02,0x22,0x02,0x00,0x03,0x3a,0x02,0x30,0x84,0xff,0x00,0x30,0xe7,0xff,0x00,
2930x00,0x02,0x5e,0x02,0x00,0x02,0x32,0x00,0x00,0x03,0x56,0x02,0x00,0x03,0x2a,0x00,
2940x01,0x64,0x58,0x25,0x00,0xd6,0x30,0x24,0x01,0x47,0x50,0x25,0x00,0x02,0x16,0x00,
2950x00,0xb6,0x28,0x24,0x00,0x03,0x1e,0x00,0x01,0x66,0x58,0x25,0x01,0x45,0x50,0x25,
2960x00,0x57,0x10,0x24,0x00,0x77,0x18,0x24,0x01,0x62,0x38,0x25,0x01,0x43,0x30,0x25,
2970x00,0x09,0x10,0xc2,0x00,0x09,0x1c,0x02,0x31,0x08,0x00,0x03,0x30,0x4c,0x00,0x03,
2980x30,0x63,0x00,0x0f,0x00,0x09,0x26,0x02,0x00,0xe0,0x58,0x21,0x15,0x00,0x00,0x28,
2990x00,0xc0,0x50,0x21,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x06,0x00,0x80,0x28,0x21,
3000x24,0x02,0x00,0x03,0x14,0x62,0xff,0x69,0x02,0x51,0x10,0x21,0x24,0x85,0x01,0x00,
3010x24,0x02,0x00,0x01,0x11,0x82,0x00,0x15,0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x0a,
3020x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,
3030x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xac,0x62,0x00,0x00,
3040x08,0x00,0x03,0xa7,0x02,0x51,0x10,0x21,0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,
3050x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,
3060xa4,0x62,0x00,0x00,0x08,0x00,0x03,0xa7,0x02,0x51,0x10,0x21,0x3c,0x03,0xb0,0x03,
3070x00,0xa3,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,
3080x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa6,0xa0,0x62,0x00,0x00,
3090x24,0x02,0x00,0x01,0x11,0x02,0x00,0x21,0x00,0x00,0x00,0x00,0x15,0x13,0xff,0x42,
3100x00,0x00,0x00,0x00,0x11,0x82,0x00,0x17,0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x0b,
3110x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x60,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,
3120x8c,0x82,0x00,0x18,0x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,
3130x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa6,0xac,0x82,0x00,0x18,0x27,0x83,0x8b,0x68,
3140x00,0x04,0x20,0x40,0x00,0x83,0x20,0x21,0x94,0x82,0x00,0x02,0x00,0x06,0x18,0x27,
3150x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa6,
3160xa4,0x82,0x00,0x02,0x27,0x83,0x8b,0x60,0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x00,
3170x00,0x06,0x20,0x27,0x08,0x00,0x04,0x5c,0x00,0xe6,0x28,0x24,0x30,0x62,0x00,0x07,
3180x00,0x02,0x12,0x00,0x11,0x88,0x00,0x0f,0x00,0x44,0x10,0x21,0x11,0x93,0x00,0x07,
3190x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,0x8c,0x62,0x00,0x00,
3200x00,0x06,0x20,0x27,0x08,0x00,0x04,0x49,0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,
3210x00,0x43,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x52,
3220x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,0x08,0x00,0x04,0x7f,0x00,0x43,0x18,0x21,
3230x97,0x85,0x8b,0xb4,0x3c,0x07,0xb0,0x02,0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x00,
3240x00,0xa7,0x28,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x12,0x60,0x24,0x03,0xff,0x80,
3250xac,0x82,0x00,0x00,0xa0,0xa3,0x00,0x07,0x97,0x82,0x8b,0xb6,0x97,0x85,0x8b,0xb4,
3260x3c,0x06,0xb0,0x06,0x30,0x42,0xff,0xf8,0x24,0x42,0x00,0x10,0x00,0xa2,0x10,0x21,
3270x30,0x42,0x0f,0xff,0x24,0x44,0x00,0x08,0x30,0x84,0x0f,0xff,0x00,0x05,0x28,0xc2,
3280x3c,0x03,0x00,0x40,0x00,0xa3,0x28,0x25,0x00,0x87,0x20,0x21,0x34,0xc6,0x80,0x18,
3290xac,0xc5,0x00,0x00,0xaf,0x84,0x8b,0xb0,0xa7,0x82,0x8b,0xb4,0xa7,0x80,0x8b,0xb6,
3300xaf,0x80,0x8b,0xb8,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,
3310x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01,0x00,0xe0,0x48,0x21,0x30,0xc6,0x00,0xff,
3320x8f,0xa7,0x00,0x10,0x10,0x82,0x00,0x07,0x00,0xa0,0x40,0x21,0x24,0x02,0x00,0x03,
3330x10,0x82,0x00,0x03,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
3340x24,0xa8,0x01,0x00,0x3c,0x03,0xb0,0x03,0x24,0x02,0x00,0x01,0x00,0x07,0x20,0x27,
3350x01,0x27,0x28,0x24,0x10,0xc2,0x00,0x14,0x01,0x03,0x18,0x21,0x24,0x02,0x00,0x02,
3360x10,0xc2,0x00,0x09,0x00,0x07,0x50,0x27,0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,
3370x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,
3380x08,0x00,0x04,0xe3,0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,
3390x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,
3400x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
3410x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xa0,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,
3420x00,0x00,0x00,0x00,0x30,0x84,0x00,0x07,0x00,0x04,0x22,0x00,0x30,0xa5,0x00,0xff,
3430x00,0x85,0x28,0x21,0x3c,0x02,0xb0,0x0a,0x00,0xa2,0x40,0x21,0x30,0xc6,0x00,0xff,
3440x24,0x02,0x00,0x01,0x8f,0xa4,0x00,0x10,0x10,0xc2,0x00,0x14,0x24,0x02,0x00,0x02,
3450x00,0x04,0x50,0x27,0x10,0xc2,0x00,0x09,0x00,0xe4,0x48,0x24,0x3c,0x03,0xb0,0x0a,
3460x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,
3470x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x0a,
3480x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,
3490x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00,0x91,0x02,0x00,0x00,
3500x00,0x04,0x18,0x27,0x00,0xe4,0x20,0x24,0x00,0x43,0x10,0x24,0x00,0x44,0x10,0x25,
3510x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x00,0x30,0xa9,0x00,0xff,0x27,0x83,0x8b,0x60,
3520x30,0x85,0x00,0xff,0x24,0x02,0x00,0x01,0x00,0x07,0x50,0x27,0x00,0xc7,0x40,0x24,
3530x11,0x22,0x00,0x17,0x00,0xa3,0x18,0x21,0x00,0x05,0x20,0x40,0x27,0x82,0x8b,0x60,
3540x00,0x05,0x28,0x80,0x27,0x83,0x8b,0x68,0x00,0x83,0x50,0x21,0x00,0xa2,0x20,0x21,
3550x24,0x02,0x00,0x02,0x00,0x07,0x40,0x27,0x11,0x22,0x00,0x07,0x00,0xc7,0x28,0x24,
3560x8c,0x82,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,
3570x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x18,0x95,0x42,0x00,0x02,0x00,0x00,0x00,0x00,
3580x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xa5,0x42,0x00,0x02,
3590x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x48,0x10,0x25,
3600x03,0xe0,0x00,0x08,0xa0,0x62,0x00,0x00,0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00,
3610x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00,0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24,
3620x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25,0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08,
3630x00,0x44,0x10,0x25,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe8,
3640x34,0x63,0x00,0x20,0x24,0x42,0x14,0xe4,0x3c,0x04,0xb0,0x03,0xaf,0xbf,0x00,0x14,
3650xac,0x62,0x00,0x00,0xaf,0xb0,0x00,0x10,0x34,0x84,0x00,0x2c,0x8c,0x83,0x00,0x00,
3660xa7,0x80,0xbb,0xf0,0x00,0x03,0x12,0x02,0x00,0x03,0x2d,0x02,0x30,0x42,0x0f,0xff,
3670xa3,0x83,0xbb,0xf8,0xa7,0x85,0xbb,0xfc,0xa7,0x82,0xbb,0xfa,0xa7,0x80,0xbb,0xf2,
3680xa7,0x80,0xbb,0xf4,0xa7,0x80,0xbb,0xf6,0x0c,0x00,0x06,0xce,0x24,0x04,0x05,0x00,
3690x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,0x0c,0x00,0x06,0xc1,
3700x00,0x40,0x80,0x21,0x3c,0x02,0xf7,0xff,0x34,0x42,0xff,0xff,0x02,0x02,0x80,0x24,
3710x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x05,0x00,0x3c,0x02,0xb0,0x03,
3720x3c,0x03,0xb0,0x03,0x34,0x42,0x01,0x08,0x34,0x63,0x01,0x18,0x8c,0x45,0x00,0x00,
3730x8c,0x64,0x00,0x00,0x3c,0x02,0x00,0x0f,0x3c,0x03,0x00,0x4c,0x30,0x84,0x02,0x00,
3740x34,0x63,0x4b,0x40,0xaf,0x85,0xbc,0x00,0x10,0x80,0x00,0x06,0x34,0x42,0x42,0x40,
3750xaf,0x83,0xbc,0x04,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
3760x27,0xbd,0x00,0x18,0xaf,0x82,0xbc,0x04,0x08,0x00,0x05,0x69,0x00,0x00,0x00,0x00,
3770x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,0x34,0x63,0x00,0x20,
3780x24,0x42,0x15,0xc0,0x30,0x84,0x00,0xff,0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c,
3790xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,
3800xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xac,0x62,0x00,0x00,
3810x10,0x80,0x00,0x1c,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x08,0x00,0x00,0x00,0x00,
3820x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,
3830x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0xa7,0x80,0xbb,0xf0,
3840xa7,0x80,0xbb,0xf2,0xa7,0x80,0xbb,0xf4,0xa7,0x80,0xbb,0xf6,0x0c,0x00,0x06,0xce,
3850x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,
3860x0c,0x00,0x06,0xc1,0x00,0x40,0x80,0x21,0x3c,0x05,0xf7,0xff,0x34,0xa5,0xff,0xff,
3870x02,0x05,0x28,0x24,0x0c,0x00,0x06,0xc1,0x24,0x04,0x05,0x00,0x08,0x00,0x05,0x84,
3880x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xce,0x24,0x04,0x05,0xa0,0x24,0x04,0x05,0xa4,
3890x0c,0x00,0x06,0xce,0x00,0x02,0xbc,0x02,0x24,0x04,0x05,0xa8,0x00,0x02,0xb4,0x02,
3900x0c,0x00,0x06,0xce,0x30,0x55,0xff,0xff,0x00,0x40,0x80,0x21,0x97,0x84,0xbb,0xf0,
3910x97,0x82,0xbb,0xf2,0x97,0x83,0xbb,0xf6,0x02,0xe4,0x20,0x23,0x02,0xa2,0x10,0x23,
3920x00,0x82,0x20,0x21,0x97,0x82,0xbb,0xf4,0x32,0x14,0xff,0xff,0x02,0x83,0x18,0x23,
3930x02,0xc2,0x10,0x23,0x00,0x82,0x20,0x21,0x93,0x82,0xbb,0xf8,0x00,0x83,0x20,0x21,
3940x30,0x84,0xff,0xff,0x00,0x82,0x10,0x2b,0x14,0x40,0x00,0xaa,0x00,0x00,0x00,0x00,
3950x97,0x82,0xbb,0xfc,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x7f,
3960x00,0x00,0x00,0x00,0x97,0x82,0xbb,0xfa,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,
3970x10,0x40,0x00,0x3a,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xce,0x24,0x04,0x04,0x50,
3980x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,0x10,0x40,0x00,0x13,
3990x24,0x02,0x00,0x20,0x12,0x22,0x00,0x17,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,
4000x26,0x31,0x00,0x01,0x00,0x51,0x80,0x25,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xc1,
4010x24,0x04,0x04,0x50,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x04,0x58,
4020x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x04,0x60,0x02,0x00,0x28,0x21,
4030x24,0x04,0x04,0x68,0x0c,0x00,0x06,0xc1,0x00,0x00,0x00,0x00,0xa7,0x97,0xbb,0xf0,
4040xa7,0x95,0xbb,0xf2,0xa7,0x96,0xbb,0xf4,0xa7,0x94,0xbb,0xf6,0x08,0x00,0x05,0x84,
4050x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,
4060x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,
4070x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
4080x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x08,
4090x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,
4100x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xc1,
4110x24,0x04,0x02,0x2c,0x08,0x00,0x05,0xcb,0x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xce,
4120x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20,0x16,0x22,0xff,0xdb,
4130x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,
4140x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xce,
4150x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c,0x0c,0x00,0x06,0xce,0x00,0x02,0x9e,0x02,
4160x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,
4170x14,0x60,0x00,0x1d,0x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,
4180x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,
4190x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xc1,0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,
4200x08,0x00,0x05,0xd9,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x08,
4210x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,
4220x24,0x03,0x00,0x02,0x14,0x43,0xff,0xee,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
4230x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x08,
4240x08,0x00,0x06,0x15,0x3c,0x02,0xff,0xff,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x08,
4250x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,
4260x14,0x43,0xff,0xdf,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,
4270x3c,0x03,0x00,0x80,0x08,0x00,0x06,0x2a,0x00,0x43,0x28,0x25,0x0c,0x00,0x06,0xce,
4280x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,
4290x10,0x40,0xff,0x9a,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x04,0x24,0x02,0xff,0x80,
4300x02,0x02,0x10,0x24,0x08,0x00,0x05,0xcd,0x26,0x31,0x00,0x02,0x0c,0x00,0x06,0xce,
4310x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,
4320x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,
4330x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
4340x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x08,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x2c,
4350x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,
4360x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x44,
4370x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xce,0x24,0x04,0x04,0x50,0x00,0x40,0x80,0x21,
4380x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x1d,0x2e,0x22,0x00,0x21,
4390x14,0x40,0xff,0x72,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x26,0x31,0xff,0xff,
4400x00,0x51,0x80,0x25,0x24,0x04,0x04,0x50,0x0c,0x00,0x06,0xc1,0x02,0x00,0x28,0x21,
4410x24,0x04,0x04,0x58,0x0c,0x00,0x06,0xc1,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x60,
4420x0c,0x00,0x06,0xc1,0x02,0x00,0x28,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xc1,
4430x24,0x04,0x04,0x68,0x24,0x02,0x00,0x20,0x16,0x22,0xff,0x60,0x00,0x00,0x00,0x00,
4440x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,
4450x34,0x42,0x3f,0xff,0x02,0x42,0x10,0x24,0x08,0x00,0x06,0x1b,0x34,0x52,0x80,0x00,
4460x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,
4470x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x58,
4480x24,0x04,0x02,0x5c,0x0c,0x00,0x06,0xce,0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,
4490x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x20,
4500x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,
4510x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,
4520x0c,0x00,0x06,0xc1,0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xc1,
4530x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x68,0x2e,0x22,0x00,0x21,0x0c,0x00,0x06,0xce,
4540x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,
4550x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02,0x14,0x43,0xff,0xec,0x00,0x00,0x00,0x00,
4560x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
4570x0c,0x00,0x06,0xc1,0x24,0x04,0x02,0x08,0x08,0x00,0x06,0x98,0x3c,0x02,0xff,0xff,
4580x0c,0x00,0x06,0xce,0x24,0x04,0x02,0x08,0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,
4590x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,0x14,0x43,0xff,0xdc,0x3c,0x03,0x00,0x80,
4600x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x08,0x00,0x06,0xb0,
4610x00,0x43,0x28,0x25,0x30,0x83,0x00,0x03,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x23,
4620x3c,0x02,0xb0,0x0a,0x00,0x82,0x20,0x21,0xac,0x85,0x00,0x00,0x00,0x00,0x18,0x21,
4630x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x0a,0x14,0x40,0xff,0xfe,0x24,0x63,0x00,0x01,
4640x03,0xe0,0x00,0x08,0x24,0x63,0xff,0xff,0x30,0x86,0x00,0x03,0x00,0x04,0x28,0x40,
4650x3c,0x03,0xb0,0x0a,0x00,0xa6,0x10,0x23,0x00,0x43,0x10,0x21,0x24,0x04,0xff,0xff,
4660xac,0x44,0x10,0x00,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x0a,
4670x14,0x40,0xff,0xfe,0x24,0x63,0x00,0x01,0x24,0x63,0xff,0xff,0x00,0xa6,0x18,0x23,
4680x3c,0x02,0xb0,0x0a,0x00,0x62,0x18,0x21,0x8c,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,
4690x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x1b,0x84,
4700x24,0x03,0x00,0x01,0x34,0xa5,0x00,0x20,0x3c,0x06,0xb0,0x03,0xac,0xa2,0x00,0x00,
4710x34,0xc6,0x01,0x04,0xa0,0x83,0x00,0x48,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
4720xa0,0x80,0x00,0x06,0xa0,0x80,0x00,0x07,0xa0,0x80,0x00,0x08,0xa0,0x80,0x00,0x09,
4730xa0,0x80,0x00,0x0a,0xa0,0x80,0x00,0x11,0xa0,0x80,0x00,0x13,0xa0,0x80,0x00,0x49,
4740x94,0xc2,0x00,0x00,0xac,0x80,0x00,0x00,0xa0,0x80,0x00,0x4e,0x00,0x02,0x14,0x00,
4750x00,0x02,0x14,0x03,0x30,0x43,0x00,0xff,0x30,0x42,0xff,0x00,0xa4,0x82,0x00,0x44,
4760xa4,0x83,0x00,0x46,0xac,0x80,0x00,0x24,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,
4770xac,0x80,0x00,0x30,0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xac,0x80,0x00,0x3c,
4780x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x40,0x84,0x83,0x00,0x0c,0x3c,0x07,0xb0,0x03,
4790x34,0xe7,0x00,0x20,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
4800x27,0x83,0x8f,0xf4,0x00,0x43,0x10,0x21,0x8c,0x48,0x00,0x18,0x3c,0x02,0x80,0x00,
4810x24,0x42,0x1c,0x18,0xac,0xe2,0x00,0x00,0x8d,0x03,0x00,0x08,0x80,0x82,0x00,0x13,
4820x00,0x05,0x2c,0x00,0x00,0x03,0x1e,0x02,0x00,0x02,0x12,0x00,0x30,0x63,0x00,0x7e,
4830x00,0x62,0x18,0x21,0x00,0x65,0x18,0x21,0x3c,0x02,0xc0,0x00,0x3c,0x05,0xb0,0x05,
4840x34,0x42,0x04,0x00,0x24,0x63,0x00,0x01,0x3c,0x07,0xb0,0x05,0x3c,0x08,0xb0,0x05,
4850x34,0xa5,0x04,0x20,0xac,0xa3,0x00,0x00,0x00,0xc2,0x30,0x21,0x34,0xe7,0x04,0x24,
4860x35,0x08,0x02,0x28,0x24,0x02,0x00,0x01,0x24,0x03,0x00,0x20,0xac,0xe6,0x00,0x00,
4870xac,0x82,0x00,0x3c,0x03,0xe0,0x00,0x08,0xa1,0x03,0x00,0x00,0x27,0xbd,0xff,0xa8,
4880x00,0x07,0x60,0x80,0x27,0x82,0xb3,0xf0,0xaf,0xbe,0x00,0x50,0xaf,0xb7,0x00,0x4c,
4890xaf,0xb5,0x00,0x44,0xaf,0xb4,0x00,0x40,0xaf,0xbf,0x00,0x54,0xaf,0xb6,0x00,0x48,
4900xaf,0xb3,0x00,0x3c,0xaf,0xb2,0x00,0x38,0xaf,0xb1,0x00,0x34,0xaf,0xb0,0x00,0x30,
4910x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0xe0,0x70,0x21,0x3c,0x02,0x80,0x00,
4920x94,0x73,0x00,0x14,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x20,0x24,0x42,0x1c,0xac,
4930x3c,0x03,0xb0,0x05,0xac,0xe2,0x00,0x00,0x34,0x63,0x01,0x28,0x90,0x67,0x00,0x00,
4940x00,0x13,0xa8,0xc0,0x02,0xb3,0x18,0x21,0x27,0x82,0x8f,0xf4,0x00,0x03,0x18,0x80,
4950x00,0x62,0x18,0x21,0x00,0x05,0x2c,0x00,0x00,0x07,0x3e,0x00,0x28,0xc2,0x00,0x03,
4960x00,0xc0,0xa0,0x21,0x00,0x80,0x78,0x21,0x00,0x05,0xbc,0x03,0x8c,0x68,0x00,0x18,
4970x02,0xa0,0x58,0x21,0x10,0x40,0x01,0x81,0x00,0x07,0xf6,0x03,0x00,0xde,0x10,0x07,
4980x30,0x5e,0x00,0x01,0x01,0x73,0x10,0x21,0x27,0x83,0x8f,0xf8,0x00,0x02,0x10,0x80,
4990x00,0x43,0x10,0x21,0x80,0x4d,0x00,0x06,0x8d,0x03,0x00,0x00,0x8d,0x02,0x00,0x04,
5000x8d,0x0a,0x00,0x08,0x8d,0x03,0x00,0x0c,0xaf,0xa2,0x00,0x20,0x11,0xa0,0x01,0x71,
5010xaf,0xa3,0x00,0x18,0x27,0x82,0xb3,0xf0,0x01,0x82,0x10,0x21,0x8c,0x44,0x00,0x00,
5020x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04,
5030x14,0x60,0x00,0x12,0x00,0x00,0xb0,0x21,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,
5040x90,0x43,0x00,0x00,0x2a,0x84,0x00,0x04,0x10,0x80,0x01,0x56,0x30,0x65,0x00,0x01,
5050x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x12,0x82,0x00,0x02,0x00,0x00,0x00,0x00,
5060x00,0x00,0x28,0x21,0x14,0xa0,0x00,0x03,0x00,0x00,0x38,0x21,0x13,0xc0,0x00,0x03,
5070x38,0xf6,0x00,0x01,0x24,0x07,0x00,0x01,0x38,0xf6,0x00,0x01,0x01,0x73,0x10,0x21,
5080x00,0x02,0x30,0x80,0x27,0x83,0x90,0x00,0x00,0xc3,0x48,0x21,0x91,0x25,0x00,0x00,
5090x8f,0xa4,0x00,0x20,0x2c,0xa3,0x00,0x04,0x00,0x04,0x11,0xc3,0x30,0x42,0x00,0x01,
5100x00,0x03,0xb0,0x0b,0x12,0xc0,0x00,0xd8,0xaf,0xa2,0x00,0x24,0x93,0x90,0xbb,0xda,
5110x00,0x0a,0x16,0x42,0x30,0x52,0x00,0x3f,0x2e,0x06,0x00,0x0c,0x10,0xc0,0x00,0xc0,
5120x00,0xa0,0x20,0x21,0x2c,0xa2,0x00,0x10,0x14,0x40,0x00,0x04,0x00,0x90,0x10,0x2b,
5130x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x04,0x00,0x90,0x10,0x2b,0x10,0x40,0x00,0x0b,
5140x01,0x73,0x10,0x21,0x27,0x85,0xbb,0x0c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21,
5150x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b,
5160x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x01,0x73,0x10,0x21,0x00,0x02,0x10,0x80,
5170x27,0x83,0x8f,0xf8,0x00,0x43,0x10,0x21,0x31,0xa4,0x00,0x01,0x10,0x80,0x00,0xa5,
5180xa0,0x50,0x00,0x07,0x3c,0x04,0xb0,0x05,0x34,0x84,0x00,0x08,0x24,0x02,0x00,0x01,
5190x3c,0x03,0x80,0x00,0xa1,0xe2,0x00,0x4e,0xac,0x83,0x00,0x00,0x8c,0x85,0x00,0x00,
5200x3c,0x02,0x00,0xf0,0x3c,0x03,0x40,0xf0,0x34,0x42,0xf0,0x00,0x34,0x63,0xf0,0x00,
5210x24,0x17,0x00,0x0e,0x24,0x13,0x01,0x06,0xac,0x82,0x00,0x00,0xac,0x83,0x00,0x00,
5220x27,0x82,0xb3,0xf0,0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x24,0x05,0x00,0x01,
5230xaf,0xa5,0x00,0x1c,0x90,0x62,0x00,0x16,0x00,0x13,0xa8,0xc0,0x32,0x51,0x00,0x02,
5240x34,0x42,0x00,0x04,0xa0,0x62,0x00,0x16,0x8f,0xa3,0x00,0x20,0x8f,0xa4,0x00,0x18,
5250x00,0x03,0x13,0x43,0x00,0x04,0x1a,0x02,0x30,0x47,0x00,0x01,0x12,0x20,0x00,0x04,
5260x30,0x64,0x07,0xff,0x2e,0x03,0x00,0x04,0x32,0x42,0x00,0x33,0x00,0x43,0x90,0x0b,
5270x8f,0xa5,0x00,0x24,0x8f,0xa6,0x00,0x1c,0x00,0x12,0x10,0x40,0x00,0x05,0x19,0xc0,
5280x00,0x47,0x10,0x21,0x00,0x06,0x2a,0x80,0x00,0x43,0x10,0x21,0x00,0x10,0x32,0x00,
5290x00,0x04,0x24,0x80,0x02,0x65,0x28,0x21,0x00,0xa4,0x28,0x21,0x00,0x46,0x10,0x21,
5300x00,0x17,0x1c,0x00,0x3c,0x04,0xc0,0x00,0x00,0x43,0x30,0x21,0x16,0x80,0x00,0x29,
5310x00,0xa4,0x28,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x00,0x3c,0x03,0xb0,0x05,
5320x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x04,0x34,0x84,0x02,0x28,
5330x24,0x02,0x00,0x01,0xac,0x65,0x00,0x00,0xa0,0x82,0x00,0x00,0x3c,0x02,0xb0,0x09,
5340x34,0x42,0x01,0x46,0x90,0x44,0x00,0x00,0x91,0xe3,0x00,0x09,0x30,0x86,0x00,0x01,
5350x02,0x83,0x18,0x26,0x00,0x03,0x30,0x0b,0x14,0xc0,0x00,0x03,0x00,0x00,0x28,0x21,
5360x13,0xc0,0x00,0x03,0x02,0xb3,0x10,0x21,0x24,0x05,0x00,0x01,0x02,0xb3,0x10,0x21,
5370x27,0x83,0x8f,0xf8,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x84,0x48,0x00,0x04,
5380x00,0xa0,0x30,0x21,0x00,0xe0,0x20,0x21,0x02,0x80,0x28,0x21,0x02,0xc0,0x38,0x21,
5390x0c,0x00,0x00,0x72,0xaf,0xa8,0x00,0x10,0x7b,0xbe,0x02,0xbc,0x7b,0xb6,0x02,0x7c,
5400x7b,0xb4,0x02,0x3c,0x7b,0xb2,0x01,0xfc,0x7b,0xb0,0x01,0xbc,0x03,0xe0,0x00,0x08,
5410x27,0xbd,0x00,0x58,0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x3d,0x3c,0x02,0xb0,0x05,
5420x24,0x02,0x00,0x02,0x12,0x82,0x00,0x31,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x03,
5430x12,0x82,0x00,0x25,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,0x12,0x82,0x00,0x19,
5440x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x11,0x12,0x82,0x00,0x0d,0x3c,0x02,0xb0,0x05,
5450x24,0x02,0x00,0x12,0x16,0x82,0xff,0xd1,0x3c,0x02,0xb0,0x05,0x3c,0x03,0xb0,0x05,
5460x34,0x42,0x04,0x20,0x3c,0x04,0xb0,0x05,0x34,0x63,0x04,0x24,0xac,0x46,0x00,0x00,
5470x34,0x84,0x02,0x28,0xac,0x65,0x00,0x00,0x08,0x00,0x07,0xe2,0x24,0x02,0x00,0x20,
5480x34,0x42,0x04,0x40,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,
5490x34,0x63,0x04,0x44,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x40,0x08,0x00,0x07,0xe2,
5500xac,0x65,0x00,0x00,0x34,0x42,0x04,0x28,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,
5510xac,0x46,0x00,0x00,0x34,0x63,0x04,0x2c,0x34,0x84,0x02,0x28,0x24,0x02,0xff,0x80,
5520x08,0x00,0x07,0xe2,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x18,0x3c,0x03,0xb0,0x05,
5530x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x1c,0x34,0x84,0x02,0x28,
5540x24,0x02,0x00,0x08,0x08,0x00,0x07,0xe2,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x10,
5550x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x14,
5560x34,0x84,0x02,0x28,0x24,0x02,0x00,0x04,0x08,0x00,0x07,0xe2,0xac,0x65,0x00,0x00,
5570x34,0x42,0x04,0x08,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,
5580x34,0x63,0x04,0x0c,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x02,0x08,0x00,0x07,0xe2,
5590xac,0x65,0x00,0x00,0x24,0x17,0x00,0x14,0x08,0x00,0x07,0xb4,0x24,0x13,0x01,0x02,
5600x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x0c,0x00,0x90,0x18,0x2b,0x10,0x60,0x00,0x0c,
5610x26,0x02,0x00,0x04,0x27,0x85,0xbb,0x0c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21,
5620x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b,
5630x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x2e,0x06,0x00,0x0c,0x26,0x02,0x00,0x04,
5640x08,0x00,0x07,0x9e,0x00,0x46,0x80,0x0a,0x27,0x82,0xb3,0xf0,0x01,0x82,0x20,0x21,
5650x8c,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0xe2,0x00,0x19,0x00,0x00,0x00,0x00,
5660x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x27,0x82,0x90,0x10,0x00,0xc2,0x10,0x21,
5670x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x14,0x00,0x00,0x00,0x00,
5680x90,0xe3,0x00,0x16,0x27,0x82,0x8f,0xf8,0x00,0xc2,0x10,0x21,0x34,0x63,0x00,0x20,
5690x90,0x50,0x00,0x07,0xa0,0xe3,0x00,0x16,0x8c,0x84,0x00,0x00,0x00,0x0a,0x1e,0x42,
5700x24,0x06,0x00,0x01,0x90,0x82,0x00,0x16,0x30,0x71,0x00,0x02,0x30,0x72,0x00,0x3f,
5710x30,0x42,0x00,0xfb,0x24,0x17,0x00,0x18,0x24,0x13,0x01,0x03,0x24,0x15,0x08,0x18,
5720xaf,0xa6,0x00,0x1c,0x08,0x00,0x07,0xbe,0xa0,0x82,0x00,0x16,0x8d,0x02,0x00,0x04,
5730x00,0x0a,0x1c,0x42,0x30,0x42,0x00,0x10,0x14,0x40,0x00,0x15,0x30,0x72,0x00,0x3f,
5740x81,0x22,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x11,0x30,0x72,0x00,0x3e,
5750x27,0x83,0x90,0x08,0x00,0xc3,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x68,
5760x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,
5770x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x05,0x90,0x43,0x00,0x04,
5780x00,0x00,0x00,0x00,0x00,0x64,0x18,0x24,0x30,0x63,0x00,0x01,0x02,0x43,0x90,0x25,
5790x27,0x85,0xb3,0xf0,0x01,0x85,0x28,0x21,0x8c,0xa6,0x00,0x00,0x01,0x73,0x10,0x21,
5800x27,0x83,0x90,0x00,0x90,0xc4,0x00,0x16,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
5810x30,0x84,0x00,0xdf,0x90,0x50,0x00,0x00,0xa0,0xc4,0x00,0x16,0x80,0xc6,0x00,0x12,
5820x8c,0xa3,0x00,0x00,0x2d,0xc4,0x00,0x02,0xaf,0xa6,0x00,0x1c,0x90,0x62,0x00,0x16,
5830x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfb,0x14,0x80,0x00,0x06,0xa0,0x62,0x00,0x16,
5840x24,0x02,0x00,0x06,0x11,0xc2,0x00,0x03,0x24,0x02,0x00,0x04,0x15,0xc2,0xff,0x0e,
5850x32,0x51,0x00,0x02,0x32,0x51,0x00,0x02,0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x0f,
5860x00,0x11,0x18,0x2b,0x32,0x02,0x00,0x0f,0x34,0x42,0x00,0x10,0x00,0x03,0x19,0x00,
5870x00,0x43,0x18,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xb8,0xa0,0x43,0x00,0x00,
5880x00,0x00,0x20,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x02,0x05,0xaf,0xaf,0x00,0x28,
5890x8f,0xaf,0x00,0x28,0x08,0x00,0x07,0xbe,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0xb9,
5900x32,0x03,0x00,0xff,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x42,0x90,0x62,0x00,0x00,
5910x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0x14,0x40,0xfe,0xaa,0x00,0x00,0x00,0x00,
5920x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x02,0x82,0x10,0x26,0x08,0x00,0x07,0x75,
5930x00,0x02,0x28,0x0b,0x08,0x00,0x07,0x7b,0x00,0x00,0xb0,0x21,0x24,0x02,0x00,0x10,
5940x10,0xc2,0x00,0x08,0x24,0x02,0x00,0x11,0x10,0xc2,0xfe,0x7d,0x00,0x07,0x17,0x83,
5950x24,0x02,0x00,0x12,0x14,0xc2,0xfe,0x7b,0x00,0x07,0x17,0x43,0x08,0x00,0x07,0x55,
5960x30,0x5e,0x00,0x01,0x08,0x00,0x07,0x55,0x00,0x07,0xf7,0xc2,0x00,0x04,0x10,0x40,
5970x27,0x83,0x80,0x1c,0x00,0x43,0x10,0x21,0x00,0x80,0x40,0x21,0x94,0x44,0x00,0x00,
5980x2d,0x07,0x00,0x04,0x24,0xc2,0x00,0x03,0x00,0x47,0x30,0x0a,0x00,0x86,0x00,0x18,
5990x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x23,0x7c,
6000xac,0x62,0x00,0x00,0x2d,0x06,0x00,0x10,0x00,0x00,0x20,0x12,0x00,0x04,0x22,0x42,
6010x24,0x84,0x00,0x01,0x24,0x83,0x00,0xc0,0x10,0xe0,0x00,0x0b,0x24,0x82,0x00,0x60,
6020x00,0x40,0x20,0x21,0x00,0x65,0x20,0x0a,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,
6030x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x00,0x44,0x20,0x04,
6040x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x24,0x85,0x00,0x28,0x24,0x83,0x00,0x24,
6050x31,0x02,0x00,0x08,0x14,0xc0,0xff,0xf4,0x24,0x84,0x00,0x14,0x00,0x60,0x20,0x21,
6060x08,0x00,0x08,0xf6,0x00,0xa2,0x20,0x0b,0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x03,
6070x3c,0x02,0x80,0x00,0xaf,0xb0,0x00,0x10,0x24,0x42,0x24,0x18,0x00,0x80,0x80,0x21,
6080x34,0x63,0x00,0x20,0x3c,0x04,0xb0,0x03,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
6090xaf,0xbf,0x00,0x1c,0x83,0xb1,0x00,0x33,0x83,0xa8,0x00,0x37,0x34,0x84,0x01,0x10,
6100xac,0x62,0x00,0x00,0x2e,0x02,0x00,0x10,0x00,0xe0,0x90,0x21,0x8c,0x87,0x00,0x00,
6110x14,0x40,0x00,0x0c,0x2e,0x02,0x00,0x0c,0x3c,0x02,0x00,0x0f,0x34,0x42,0xf0,0x00,
6120x00,0xe2,0x10,0x24,0x14,0x40,0x00,0x37,0x32,0x02,0x00,0x08,0x32,0x02,0x00,0x07,
6130x27,0x83,0x80,0xcc,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,
6140x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x03,0x02,0x00,0x20,0x21,0x32,0x02,0x00,0x0f,
6150x24,0x44,0x00,0x0c,0x00,0x87,0x10,0x06,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x07,
6160x2c,0x82,0x00,0x0c,0x00,0x04,0x10,0x80,0x27,0x83,0xb4,0x40,0x00,0x43,0x10,0x21,
6170x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x82,0x00,0x0c,0x14,0x40,0x00,0x05,
6180x00,0x05,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21,
6190x24,0x44,0x00,0x04,0x15,0x00,0x00,0x02,0x24,0x06,0x00,0x20,0x24,0x06,0x00,0x0e,
6200x0c,0x00,0x08,0xdf,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0x3c,0x02,0xb0,0x03,
6210x34,0x42,0x01,0x00,0x90,0x43,0x00,0x00,0x2e,0x04,0x00,0x04,0x24,0x02,0x00,0x10,
6220x24,0x05,0x00,0x0a,0x00,0x44,0x28,0x0a,0x30,0x63,0x00,0x01,0x14,0x60,0x00,0x02,
6230x00,0x05,0x10,0x40,0x00,0xa0,0x10,0x21,0x30,0x45,0x00,0xff,0x00,0xc5,0x10,0x21,
6240x24,0x46,0x00,0x46,0x02,0x26,0x18,0x04,0xa6,0x43,0x00,0x00,0x8f,0xbf,0x00,0x1c,
6250x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08,
6260x27,0xbd,0x00,0x20,0x10,0x40,0xff,0xcf,0x2e,0x02,0x00,0x0c,0x32,0x02,0x00,0x07,
6270x27,0x83,0x80,0xc4,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x08,0x00,0x09,0x24,
6280x02,0x04,0x80,0x23,0x27,0xbd,0xff,0xb8,0x00,0x05,0x38,0x80,0x27,0x82,0xb3,0xf0,
6290xaf,0xbe,0x00,0x40,0xaf,0xb6,0x00,0x38,0xaf,0xb3,0x00,0x2c,0xaf,0xbf,0x00,0x44,
6300xaf,0xb7,0x00,0x3c,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xb2,0x00,0x28,
6310xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0x00,0xe2,0x38,0x21,0x8c,0xe6,0x00,0x00,
6320xaf,0xa5,0x00,0x4c,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,
6330x24,0x42,0x25,0x74,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,0xa0,0xc3,0x00,0x12,
6340x8c,0xe5,0x00,0x00,0x94,0xc3,0x00,0x06,0x90,0xa2,0x00,0x16,0xa4,0xc3,0x00,0x14,
6350x27,0x83,0x8f,0xf0,0x34,0x42,0x00,0x08,0xa0,0xa2,0x00,0x16,0x8c,0xe8,0x00,0x00,
6360xaf,0xa4,0x00,0x48,0x27,0x82,0x8f,0xf4,0x95,0x11,0x00,0x14,0x00,0x00,0x00,0x00,
6370x00,0x11,0x98,0xc0,0x02,0x71,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x82,0x10,0x21,
6380x8c,0x52,0x00,0x18,0x00,0x83,0x18,0x21,0x84,0x75,0x00,0x06,0x8e,0x45,0x00,0x08,
6390x8e,0x46,0x00,0x04,0x8e,0x47,0x00,0x04,0x00,0x05,0x1c,0x82,0x00,0x06,0x31,0x42,
6400x27,0x82,0x90,0x00,0x30,0x63,0x00,0x01,0x30,0xc6,0x00,0x01,0x00,0x82,0x20,0x21,
6410xa5,0x15,0x00,0x1a,0x00,0x05,0x14,0x42,0xaf,0xa3,0x00,0x18,0xaf,0xa6,0x00,0x1c,
6420x30,0xe7,0x00,0x10,0x30,0x56,0x00,0x01,0x80,0x97,0x00,0x06,0x14,0xe0,0x00,0x47,
6430x00,0x05,0xf7,0xc2,0x80,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x44,
6440x02,0x71,0x10,0x21,0x93,0x90,0xbb,0xd9,0x00,0x00,0x00,0x00,0x2e,0x02,0x00,0x0c,
6450x14,0x40,0x00,0x06,0x02,0x00,0x20,0x21,0x00,0x16,0x10,0x40,0x00,0x43,0x10,0x21,
6460x00,0x02,0x11,0x00,0x02,0x02,0x10,0x21,0x24,0x44,0x00,0x04,0x02,0x71,0x10,0x21,
6470x00,0x02,0x10,0x80,0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x00,0x80,0x80,0x21,
6480xa0,0x44,0x00,0x03,0xa0,0x44,0x00,0x00,0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,
6490x0c,0x00,0x08,0xdf,0x02,0xa0,0x30,0x21,0x02,0x71,0x18,0x21,0x00,0x03,0x88,0x80,
6500x00,0x40,0xa0,0x21,0x27,0x82,0x90,0x10,0x02,0x22,0x10,0x21,0x8c,0x44,0x00,0x00,
6510x26,0xe3,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x04,0x25,0xc2,
6520x00,0x03,0x18,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x18,0x40,0x03,0xc4,0x20,0x24,
6530x14,0x80,0x00,0x15,0x02,0x43,0x38,0x21,0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x28,
6540x8d,0x03,0x00,0x00,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x48,0x27,0x82,0x8f,0xf8,
6550x02,0x22,0x10,0x21,0x24,0x63,0x00,0x01,0x02,0xa0,0x28,0x21,0xa4,0x54,0x00,0x04,
6560x00,0xc0,0x38,0x21,0x0c,0x00,0x07,0x2b,0xad,0x03,0x00,0x00,0x7b,0xbe,0x02,0x3c,
6570x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,
6580x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x8f,0xa2,0x00,0x1c,0x8f,0xa6,0x00,0x18,
6590x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0x06,
6600xaf,0xa0,0x00,0x14,0x08,0x00,0x09,0xc2,0x02,0x82,0xa0,0x21,0x02,0x71,0x10,0x21,
6610x00,0x02,0x10,0x80,0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,
6620x08,0x00,0x09,0xae,0xa0,0x50,0x00,0x03,0x27,0xbd,0xff,0xb8,0xaf,0xb1,0x00,0x24,
6630x8f,0xb1,0x00,0x5c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
6640x24,0x42,0x27,0x98,0xaf,0xbe,0x00,0x40,0xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38,
6650xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xa5,0x00,0x4c,0x8f,0xb5,0x00,0x58,
6660xaf,0xbf,0x00,0x44,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20,
6670x00,0xe0,0xb0,0x21,0xac,0x62,0x00,0x00,0x00,0x80,0xf0,0x21,0x00,0x00,0xb8,0x21,
6680x16,0x20,0x00,0x2b,0x00,0x00,0xa0,0x21,0x27,0x85,0xb3,0xf0,0x00,0x07,0x10,0x80,
6690x00,0x45,0x10,0x21,0x8c,0x53,0x00,0x00,0x00,0x15,0x18,0x80,0x00,0x65,0x18,0x21,
6700x92,0x62,0x00,0x16,0x8c,0x72,0x00,0x00,0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x2d,
6710x00,0x00,0x00,0x00,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03,
6720x14,0x40,0x00,0x28,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,
6730x14,0x40,0x00,0x18,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x38,0x00,0x00,0x00,0x00,
6740x14,0x40,0x00,0x14,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x3c,0x00,0x00,0x00,0x00,
6750x14,0x40,0x00,0x0f,0x3c,0x03,0xb0,0x09,0x3c,0x05,0xb0,0x05,0x34,0x63,0x01,0x44,
6760x34,0xa5,0x02,0x52,0x94,0x66,0x00,0x00,0x90,0xa2,0x00,0x00,0x8f,0xa3,0x00,0x4c,
6770x00,0x00,0x00,0x00,0x00,0x62,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x04,
6780x30,0xc6,0xff,0xff,0x2c,0xc2,0x00,0x41,0x10,0x40,0x00,0x09,0x24,0x05,0x00,0x14,
6790x02,0x20,0x10,0x21,0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,
6800x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,
6810x0c,0x00,0x07,0x06,0x24,0x06,0x01,0x07,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x28,
6820xa3,0xc2,0x00,0x11,0x10,0xc0,0x00,0x1c,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x17,
6830x00,0xc0,0x88,0x21,0x96,0x54,0x00,0x1a,0x02,0xa0,0xb8,0x21,0x12,0x20,0xff,0xed,
6840x02,0x20,0x10,0x21,0x27,0x83,0xb3,0xf0,0x00,0x17,0x10,0x80,0x00,0x43,0x10,0x21,
6850x8c,0x44,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x28,0x80,0x86,0x00,0x12,
6860x8c,0x62,0x00,0x00,0x00,0x14,0x2c,0x00,0x00,0x05,0x2c,0x03,0x00,0x46,0x10,0x21,
6870x8f,0xa6,0x00,0x4c,0x02,0xe0,0x38,0x21,0x03,0xc0,0x20,0x21,0x0c,0x00,0x07,0x2b,
6880xac,0x62,0x00,0x00,0x08,0x00,0x0a,0x28,0xaf,0xd1,0x00,0x40,0x96,0x74,0x00,0x1a,
6890x08,0x00,0x0a,0x3b,0x02,0xc0,0xb8,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,
6900x8c,0x50,0x00,0x00,0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x11,0x02,0x00,0x28,0x21,
6910x30,0x42,0x00,0xff,0x02,0x00,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x11,
6920xaf,0xa2,0x00,0x18,0x8f,0xa4,0x00,0x18,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0xed,
6930x30,0x50,0x00,0xff,0x12,0x00,0x00,0x18,0x24,0x11,0x00,0x01,0x96,0x63,0x00,0x14,
6940x96,0x44,0x00,0x14,0x27,0x85,0x8f,0xf0,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
6950x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x00,0x04,0x18,0xc0,0x8c,0x46,0x00,0x08,
6960x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x00,0x06,0x17,0x02,
6970x24,0x04,0x00,0xff,0x8c,0x63,0x00,0x08,0x10,0x44,0x00,0xd6,0x00,0x03,0x17,0x02,
6980x10,0x44,0x00,0xd5,0x3c,0x02,0x80,0x00,0x00,0x66,0x18,0x2b,0x24,0x11,0x00,0x02,
6990x24,0x02,0x00,0x01,0x00,0x43,0x88,0x0a,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x5a,
7000x24,0x02,0x00,0x02,0x16,0x22,0xff,0xbd,0x00,0x00,0x00,0x00,0x96,0x49,0x00,0x14,
7010x27,0x82,0x8f,0xf4,0x02,0xa0,0xb8,0x21,0x00,0x09,0x50,0xc0,0x01,0x49,0x18,0x21,
7020x00,0x03,0x40,0x80,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00,
7030x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42,
7040x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,0x14,0x40,0x00,0x41,
7050x30,0x87,0x00,0x01,0x27,0x82,0x90,0x08,0x01,0x02,0x10,0x21,0x80,0x44,0x00,0x00,
7060x27,0x82,0xb5,0x68,0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,
7070x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05,
7080x27,0x84,0xb4,0x90,0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2b,
7090x2c,0x64,0x00,0x0c,0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00,
7100x00,0x62,0x10,0x21,0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xb9,
7110x14,0x80,0x00,0x06,0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,
7120x00,0x02,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,
7130x27,0x83,0x90,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21,
7140xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x24,0x02,0x00,0x08,0x12,0x02,0x00,0x0b,
7150x24,0x02,0x00,0x01,0x00,0x60,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x8d,
7160xaf,0xa2,0x00,0x10,0x30,0x54,0xff,0xff,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,
7170x02,0x02,0x10,0x25,0x08,0x00,0x0a,0x3b,0xa2,0x42,0x00,0x16,0x00,0x60,0x28,0x21,
7180x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x3e,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0a,0xbe,
7190x30,0x54,0xff,0xff,0x08,0x00,0x0a,0xa6,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd,
7200x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0a,0xa6,
7210x24,0x42,0x00,0x04,0x27,0x82,0x90,0x00,0x01,0x02,0x10,0x21,0x90,0x43,0x00,0x00,
7220x08,0x00,0x0a,0xb6,0xa0,0x43,0x00,0x03,0x96,0x69,0x00,0x14,0x02,0xc0,0xb8,0x21,
7230x24,0x0b,0x00,0x01,0x00,0x09,0x10,0xc0,0x00,0x49,0x18,0x21,0x00,0x03,0x40,0x80,
7240x00,0x40,0x50,0x21,0x27,0x82,0x8f,0xf4,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,
7250x00,0x00,0x00,0x00,0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,
7260x00,0x05,0x24,0x42,0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,
7270x10,0x40,0x00,0x0d,0x30,0x87,0x00,0x01,0x27,0x82,0x90,0x08,0x01,0x02,0x10,0x21,
7280x80,0x43,0x00,0x00,0x00,0x00,0x58,0x21,0x00,0x03,0x11,0x00,0x00,0x43,0x10,0x23,
7290x00,0x02,0x10,0x80,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xb5,0x60,
7300x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x04,0x11,0x60,0x00,0x4f,0x00,0x00,0x00,0x00,
7310x01,0x49,0x10,0x21,0x00,0x02,0x20,0x80,0x27,0x85,0x90,0x00,0x00,0x85,0x10,0x21,
7320x80,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x42,0x01,0x49,0x10,0x21,
7330x27,0x82,0x90,0x08,0x00,0x82,0x10,0x21,0x80,0x44,0x00,0x00,0x27,0x82,0xb5,0x68,
7340x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x23,
7350x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05,0x27,0x84,0xb4,0x90,
7360x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2c,0x2c,0x64,0x00,0x0c,
7370x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,
7380x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xb9,0x14,0x80,0x00,0x06,
7390x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,
7400x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,0x27,0x83,0x90,0x00,
7410x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21,0xa0,0x45,0x00,0x03,
7420xa0,0x45,0x00,0x00,0x8f,0xa4,0x00,0x18,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x0c,
7430x00,0x60,0x28,0x21,0x24,0x02,0x00,0x01,0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x8d,
7440xaf,0xa2,0x00,0x10,0x8f,0xa3,0x00,0x18,0x30,0x54,0xff,0xff,0x92,0x62,0x00,0x16,
7450x00,0x00,0x00,0x00,0x00,0x62,0x10,0x25,0x08,0x00,0x0a,0x3b,0xa2,0x62,0x00,0x16,
7460x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x3e,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0b,0x2d,
7470x00,0x00,0x00,0x00,0x08,0x00,0x0b,0x15,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd,
7480x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0b,0x15,
7490x24,0x42,0x00,0x04,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x90,0x43,0x00,0x00,
7500x08,0x00,0x0b,0x25,0xa0,0x43,0x00,0x03,0x27,0x85,0x90,0x00,0x08,0x00,0x0b,0x41,
7510x01,0x49,0x10,0x21,0x3c,0x02,0x80,0x00,0x00,0x62,0x18,0x26,0x08,0x00,0x0a,0x76,
7520x00,0xc2,0x30,0x26,0x12,0x00,0xff,0x2d,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x7b,
7530x24,0x11,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,
7540x24,0x42,0x2d,0x44,0x34,0x63,0x00,0x20,0x3c,0x05,0xb0,0x05,0xaf,0xb3,0x00,0x24,
7550xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x28,0xaf,0xb0,0x00,0x18,
7560xac,0x62,0x00,0x00,0x34,0xa5,0x02,0x42,0x90,0xa2,0x00,0x00,0x00,0x80,0x90,0x21,
7570x24,0x11,0x00,0x10,0x30,0x53,0x00,0xff,0x24,0x02,0x00,0x10,0x12,0x22,0x00,0xcf,
7580x00,0x00,0x18,0x21,0x24,0x02,0x00,0x11,0x12,0x22,0x00,0xc1,0x24,0x02,0x00,0x12,
7590x12,0x22,0x00,0xb4,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0xad,0xae,0x43,0x00,0x40,
7600x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x44,0x00,0x00,0x3c,0x03,0x00,0x02,
7610x34,0x63,0x00,0xff,0x00,0x83,0x80,0x24,0x00,0x10,0x14,0x43,0x10,0x40,0x00,0x05,
7620x00,0x00,0x00,0x00,0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x92,
7630x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x61,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,
7640x10,0x40,0x00,0x04,0x32,0x10,0x00,0xff,0x00,0x10,0x11,0xc3,0x14,0x40,0x00,0x86,
7650x00,0x00,0x00,0x00,0x16,0x00,0x00,0x15,0x02,0x00,0x10,0x21,0x26,0x22,0x00,0x01,
7660x30,0x51,0x00,0xff,0x2e,0x23,0x00,0x13,0x14,0x60,0xff,0xdb,0x24,0x03,0x00,0x02,
7670x12,0x63,0x00,0x73,0x24,0x02,0x00,0x05,0x2a,0x62,0x00,0x03,0x10,0x40,0x00,0x58,
7680x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x62,0x00,0x4b,0x02,0x40,0x20,0x21,
7690x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
7700x30,0x70,0x00,0xff,0x12,0x00,0x00,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x28,
7710x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
7720x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07,0x02,0x40,0x20,0x21,
7730x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xe6,
7740xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x24,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
7750x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xec,0x02,0x00,0x10,0x21,
7760x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x24,0x02,0x00,0x05,0x02,0x40,0x20,0x21,
7770x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xe6,
7780xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x28,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
7790x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xdc,0x02,0x00,0x10,0x21,
7800x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,0x24,0x02,0x00,0x03,0x02,0x40,0x20,0x21,
7810x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xe6,
7820xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x2c,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
7830x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xcc,0x02,0x00,0x10,0x21,
7840x92,0x46,0x00,0x07,0x8e,0x43,0x00,0x30,0x24,0x02,0x00,0x02,0x02,0x40,0x20,0x21,
7850x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xe6,
7860xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x30,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
7870x08,0x00,0x0b,0x97,0x30,0x42,0x00,0xff,0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,
7880x24,0x02,0x00,0x07,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,
7890x0c,0x00,0x09,0xe6,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x90,0xae,0x42,0x00,0x24,
7900x12,0x62,0x00,0x0d,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x08,0x16,0x62,0xff,0xa8,
7910x02,0x40,0x20,0x21,0x92,0x46,0x00,0x07,0x8e,0x42,0x00,0x30,0x24,0x05,0x00,0x03,
7920x24,0x07,0x00,0x01,0xaf,0xa3,0x00,0x10,0x0c,0x00,0x09,0xe6,0xaf,0xa2,0x00,0x14,
7930x08,0x00,0x0b,0x90,0xae,0x42,0x00,0x30,0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,
7940x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,
7950x0c,0x00,0x09,0xe6,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x90,0xae,0x42,0x00,0x2c,
7960x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01,
7970x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xe6,0xaf,0xa3,0x00,0x14,
7980x08,0x00,0x0b,0x90,0xae,0x42,0x00,0x28,0x0c,0x00,0x01,0x59,0x24,0x04,0x00,0x01,
7990x08,0x00,0x0b,0x81,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x30,0xae,0x40,0x00,0x34,
8000x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x84,0x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x61,
8010x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,0x10,0x40,0xff,0x69,0x00,0x00,0x00,0x00,
8020x0c,0x00,0x01,0x59,0x00,0x00,0x20,0x21,0x08,0x00,0x0b,0x79,0x00,0x00,0x00,0x00,
8030x02,0x40,0x20,0x21,0x0c,0x00,0x09,0x5d,0x02,0x20,0x28,0x21,0x08,0x00,0x0b,0x6d,
8040x3c,0x02,0xb0,0x05,0x8e,0x42,0x00,0x3c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x4a,
8050x00,0x00,0x00,0x00,0x8f,0x82,0xb4,0x38,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,
8060x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6a,0xae,0x43,0x00,0x3c,
8070x8e,0x42,0x00,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3d,0x24,0x02,0x00,0x12,
8080x8f,0x82,0xb4,0x34,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,
8090x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6a,0xae,0x43,0x00,0x38,0x8e,0x42,0x00,0x34,
8100x00,0x00,0x00,0x00,0x14,0x40,0xff,0x30,0x24,0x02,0x00,0x11,0x8f,0x82,0xb4,0x30,
8110x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,
8120x08,0x00,0x0b,0x6a,0xae,0x43,0x00,0x34,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
8130x27,0xbd,0xff,0xe0,0x34,0x63,0x00,0x20,0x24,0x42,0x30,0xf8,0x3c,0x08,0xb0,0x03,
8140xaf,0xb1,0x00,0x14,0xac,0x62,0x00,0x00,0x35,0x08,0x01,0x00,0xaf,0xbf,0x00,0x18,
8150xaf,0xb0,0x00,0x10,0x91,0x03,0x00,0x00,0x00,0xa0,0x48,0x21,0x24,0x11,0x00,0x0a,
8160x2c,0xa5,0x00,0x04,0x24,0x02,0x00,0x10,0x00,0x45,0x88,0x0a,0x30,0x63,0x00,0x01,
8170x00,0xc0,0x28,0x21,0x14,0x60,0x00,0x02,0x00,0x11,0x40,0x40,0x02,0x20,0x40,0x21,
8180x84,0x83,0x00,0x0c,0x31,0x11,0x00,0xff,0x01,0x20,0x20,0x21,0x00,0x03,0x10,0xc0,
8190x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x8f,0xf8,0x00,0x43,0x10,0x21,
8200x84,0x43,0x00,0x04,0x24,0x06,0x00,0x0e,0x10,0xe0,0x00,0x06,0x02,0x23,0x80,0x21,
8210x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
8220x27,0xbd,0x00,0x20,0x0c,0x00,0x08,0xdf,0x00,0x00,0x00,0x00,0x02,0x11,0x18,0x21,
8230x08,0x00,0x0c,0x60,0x00,0x62,0x80,0x21,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,
8240xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb5,0x00,0x24,
8250xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x84,0x82,0x00,0x0c,0x3c,0x06,0xb0,0x03,
8260x34,0xc6,0x00,0x20,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,
8270x27,0x82,0x8f,0xf4,0x00,0x62,0x10,0x21,0x8c,0x55,0x00,0x18,0x3c,0x02,0x80,0x00,
8280x24,0x42,0x31,0xa8,0xac,0xc2,0x00,0x00,0x8e,0xb0,0x00,0x08,0x27,0x82,0x8f,0xf8,
8290x00,0x62,0x18,0x21,0x90,0x71,0x00,0x07,0x00,0x10,0x86,0x43,0x32,0x10,0x00,0x01,
8300x00,0xa0,0x38,0x21,0x02,0x00,0x30,0x21,0x00,0xa0,0x98,0x21,0x02,0x20,0x28,0x21,
8310x0c,0x00,0x0c,0x3e,0x00,0x80,0x90,0x21,0x02,0x20,0x20,0x21,0x02,0x00,0x28,0x21,
8320x24,0x06,0x00,0x14,0x0c,0x00,0x08,0xdf,0x00,0x40,0xa0,0x21,0x86,0x43,0x00,0x0c,
8330x3c,0x09,0xb0,0x09,0x3c,0x08,0xb0,0x09,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
8340x00,0x02,0x10,0x80,0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x80,0x43,0x00,0x06,
8350x3c,0x07,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x28,0x62,0x00,0x00,0x24,0x64,0x00,0x03,
8360x00,0x82,0x18,0x0b,0x00,0x03,0x18,0x83,0x3c,0x02,0xb0,0x09,0x00,0x03,0x18,0x80,
8370x34,0x42,0x01,0x02,0x35,0x29,0x01,0x10,0x35,0x08,0x01,0x14,0x34,0xe7,0x01,0x20,
8380x34,0xa5,0x01,0x24,0xa4,0x54,0x00,0x00,0x12,0x60,0x00,0x11,0x02,0xa3,0xa8,0x21,
8390x8e,0xa2,0x00,0x0c,0x8e,0xa3,0x00,0x08,0x00,0x02,0x14,0x00,0x00,0x03,0x1c,0x02,
8400x00,0x43,0x10,0x21,0xad,0x22,0x00,0x00,0x8e,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00,
8410x00,0x03,0x1c,0x02,0xa5,0x03,0x00,0x00,0x8f,0xbf,0x00,0x28,0x7b,0xb4,0x01,0x3c,
8420x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
8430x8e,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0xad,0x22,0x00,0x00,0x8e,0xa4,0x00,0x08,
8440x00,0x00,0x00,0x00,0xa5,0x04,0x00,0x00,0x7a,0xa2,0x00,0x7c,0x00,0x00,0x00,0x00,
8450x00,0x03,0x1c,0x00,0x00,0x02,0x14,0x02,0x00,0x62,0x18,0x21,0xac,0xe3,0x00,0x00,
8460x8e,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x02,0x08,0x00,0x0c,0xb2,
8470xa4,0xa2,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,
8480xaf,0xbf,0x00,0x1c,0xaf,0xb1,0x00,0x14,0x84,0x82,0x00,0x0c,0x00,0x80,0x90,0x21,
8490x3c,0x05,0xb0,0x03,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,
8500x27,0x82,0x8f,0xf4,0x00,0x82,0x10,0x21,0x8c,0x51,0x00,0x18,0x3c,0x02,0x80,0x00,
8510x34,0xa5,0x00,0x20,0x24,0x42,0x33,0x24,0x27,0x83,0x8f,0xf8,0xac,0xa2,0x00,0x00,
8520x00,0x83,0x20,0x21,0x3c,0x02,0xb0,0x03,0x90,0x86,0x00,0x07,0x34,0x42,0x01,0x00,
8530x8e,0x23,0x00,0x08,0x90,0x44,0x00,0x00,0x2c,0xc5,0x00,0x04,0x24,0x02,0x00,0x10,
8540x24,0x10,0x00,0x0a,0x00,0x45,0x80,0x0a,0x00,0x03,0x1e,0x43,0x30,0x84,0x00,0x01,
8550x30,0x65,0x00,0x01,0x14,0x80,0x00,0x02,0x00,0x10,0x10,0x40,0x02,0x00,0x10,0x21,
8560x00,0xc0,0x20,0x21,0x24,0x06,0x00,0x20,0x0c,0x00,0x08,0xdf,0x30,0x50,0x00,0xff,
8570x86,0x44,0x00,0x0c,0x27,0x85,0x90,0x00,0x3c,0x06,0xb0,0x09,0x00,0x04,0x18,0xc0,
8580x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x80,0x64,0x00,0x06,
8590x00,0x50,0x10,0x21,0x34,0xc6,0x01,0x02,0x24,0x85,0x00,0x03,0x28,0x83,0x00,0x00,
8600x00,0xa3,0x20,0x0b,0x00,0x04,0x20,0x83,0x00,0x04,0x20,0x80,0xa4,0xc2,0x00,0x00,
8610x02,0x24,0x20,0x21,0x8c,0x83,0x00,0x04,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x10,
8620xac,0x43,0x00,0x00,0x8c,0x86,0x00,0x08,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x14,
8630xa4,0x46,0x00,0x00,0x8c,0x85,0x00,0x0c,0x8c,0x82,0x00,0x08,0x3c,0x06,0xb0,0x09,
8640x00,0x05,0x2c,0x00,0x00,0x02,0x14,0x02,0x00,0xa2,0x28,0x21,0x34,0xc6,0x01,0x20,
8650xac,0xc5,0x00,0x00,0x8c,0x83,0x00,0x0c,0x3c,0x05,0xb0,0x09,0x34,0xa5,0x01,0x24,
8660x00,0x03,0x1c,0x02,0xa4,0xa3,0x00,0x00,0x92,0x42,0x00,0x0a,0x3c,0x03,0xb0,0x09,
8670x34,0x63,0x01,0x30,0x00,0x02,0x13,0x00,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,
8680xa4,0x62,0x00,0x00,0x86,0x44,0x00,0x0c,0x27,0x83,0x90,0x08,0x8f,0xbf,0x00,0x1c,
8690x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
8700x94,0x44,0x00,0x02,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x3c,0x05,0xb0,0x09,
8710x34,0xa5,0x01,0x32,0xa4,0xa4,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
8720x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0xaf,0xb0,0x00,0x10,
8730x34,0x42,0x00,0x20,0x00,0xa0,0x80,0x21,0x24,0x63,0x34,0xb0,0x00,0x05,0x2c,0x43,
8740xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x10,0xa0,0x00,0x05,
8750x00,0x80,0x88,0x21,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0xb6,
8760x00,0x00,0x00,0x00,0x32,0x10,0x00,0xff,0x12,0x00,0x00,0x4c,0x00,0x00,0x10,0x21,
8770x24,0x02,0x00,0x08,0x12,0x02,0x00,0xa3,0x2a,0x02,0x00,0x09,0x10,0x40,0x00,0x89,
8780x24,0x02,0x00,0x40,0x24,0x04,0x00,0x02,0x12,0x04,0x00,0x79,0x2a,0x02,0x00,0x03,
8790x10,0x40,0x00,0x69,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x02,0x00,0x5a,
8800x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x00,0x08,0x3c,0x03,0x80,0x00,
8810xa2,0x20,0x00,0x4e,0xac,0x43,0x00,0x00,0x82,0x24,0x00,0x11,0x92,0x27,0x00,0x11,
8820x10,0x80,0x00,0x4e,0x00,0x00,0x00,0x00,0x92,0x26,0x00,0x0a,0x24,0x02,0x00,0x12,
8830x10,0x46,0x00,0x09,0x30,0xc2,0x00,0xff,0x27,0x83,0xb3,0xf0,0x00,0x02,0x10,0x80,
8840x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x94,0x83,0x00,0x14,
8850x00,0x00,0x00,0x00,0xa6,0x23,0x00,0x0c,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x40,
8860x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x03,0xa2,0x23,0x00,0x10,
8870x14,0x60,0x00,0x2b,0x30,0x65,0x00,0x01,0x30,0xc2,0x00,0xff,0x27,0x83,0xb3,0xf0,
8880x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x82,0x23,0x00,0x12,
8890x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x30,0x42,0x00,0x01,
8900x00,0x62,0x18,0x21,0x00,0x03,0x26,0x00,0x14,0x80,0x00,0x18,0xa2,0x23,0x00,0x12,
8910x00,0x07,0x16,0x00,0x14,0x40,0x00,0x11,0x24,0x02,0x00,0x01,0x96,0x23,0x00,0x0c,
8920x27,0x84,0x90,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
8930x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x02,0xb0,0x00,
8940x00,0x65,0x18,0x21,0x00,0x62,0x18,0x21,0x90,0x64,0x00,0x00,0x90,0x62,0x00,0x04,
8950xa2,0x20,0x00,0x15,0xa3,0x80,0x8b,0xc4,0x24,0x02,0x00,0x01,0x8f,0xbf,0x00,0x18,
8960x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x0c,0xc9,
8970x02,0x20,0x20,0x21,0x92,0x27,0x00,0x11,0x08,0x00,0x0d,0x79,0x00,0x07,0x16,0x00,
8980x0c,0x00,0x0c,0x6a,0x02,0x20,0x20,0x21,0x86,0x23,0x00,0x0c,0x27,0x84,0x8f,0xf8,
8990x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x20,0x21,
9000x90,0x85,0x00,0x07,0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0xa2,0x25,0x00,0x13,
9010x90,0x83,0x00,0x07,0x08,0x00,0x0d,0x91,0xa0,0x43,0x00,0x02,0x92,0x26,0x00,0x0a,
9020x08,0x00,0x0d,0x5a,0x30,0xc2,0x00,0xff,0x8e,0x22,0x00,0x24,0x00,0x00,0x00,0x00,
9030x10,0x50,0x00,0x07,0xa2,0x20,0x00,0x08,0x24,0x02,0x00,0x07,0xa2,0x22,0x00,0x0a,
9040x92,0x22,0x00,0x27,0xae,0x20,0x00,0x24,0x08,0x00,0x0d,0x4d,0xa2,0x22,0x00,0x04,
9050x08,0x00,0x0d,0xab,0x24,0x02,0x00,0x06,0x16,0x02,0xff,0x9b,0x3c,0x02,0xb0,0x05,
9060x8e,0x23,0x00,0x2c,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x07,0xa2,0x24,0x00,0x08,
9070x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2f,0xae,0x20,0x00,0x2c,
9080x08,0x00,0x0d,0x4d,0xa2,0x22,0x00,0x06,0x08,0x00,0x0d,0xba,0xa2,0x20,0x00,0x0a,
9090x8e,0x22,0x00,0x28,0x24,0x03,0x00,0x01,0x24,0x04,0x00,0x01,0x10,0x44,0x00,0x07,
9100xa2,0x23,0x00,0x08,0x24,0x02,0x00,0x05,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2b,
9110xae,0x20,0x00,0x28,0x08,0x00,0x0d,0x4d,0xa2,0x22,0x00,0x05,0x08,0x00,0x0d,0xc6,
9120x24,0x02,0x00,0x04,0x12,0x02,0x00,0x12,0x2a,0x02,0x00,0x41,0x10,0x40,0x00,0x09,
9130x24,0x02,0x00,0x80,0x24,0x02,0x00,0x20,0x16,0x02,0xff,0x7b,0x3c,0x02,0xb0,0x05,
9140x24,0x02,0x00,0x12,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x4d,
9150xae,0x20,0x00,0x3c,0x16,0x02,0xff,0x74,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,
9160xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x4d,0xae,0x20,0x00,0x34,
9170x24,0x02,0x00,0x11,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x4d,
9180xae,0x20,0x00,0x38,0x8e,0x24,0x00,0x30,0x24,0x02,0x00,0x03,0x24,0x03,0x00,0x01,
9190x10,0x83,0x00,0x07,0xa2,0x22,0x00,0x08,0x24,0x02,0x00,0x02,0xa2,0x22,0x00,0x0a,
9200x92,0x22,0x00,0x33,0xae,0x20,0x00,0x30,0x08,0x00,0x0d,0x4d,0xa2,0x22,0x00,0x07,
9210x08,0x00,0x0d,0xec,0xa2,0x24,0x00,0x0a,0x8f,0x84,0xb4,0x30,0xae,0x20,0x00,0x34,
9220x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x84,0x32,0x10,0x00,0xff,0x08,0x00,0x0d,0x3e,
9230x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x37,0xe4,
9240x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x80,0xa2,0x00,0x15,0x3c,0x06,0xb0,0x05,
9250x10,0x40,0x00,0x0a,0x34,0xc6,0x02,0x54,0x83,0x83,0x8b,0xc4,0x00,0x00,0x00,0x00,
9260xac,0x83,0x00,0x24,0x8c,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,
9270x30,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x28,0x8c,0x82,0x00,0x2c,
9280x3c,0x06,0xb0,0x05,0x34,0xc6,0x04,0x50,0x00,0x02,0x18,0x43,0x30,0x63,0x00,0x01,
9290x10,0x40,0x00,0x04,0x30,0x45,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,
9300xac,0x85,0x00,0x24,0x90,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,
9310x30,0x43,0x00,0x02,0x30,0x42,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,
9320xac,0x82,0x00,0x24,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd8,
9330x34,0x63,0x00,0x20,0x24,0x42,0x38,0x74,0xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x1c,
9340xaf,0xbf,0x00,0x20,0xaf,0xb0,0x00,0x18,0x90,0xa6,0x00,0x0a,0x27,0x83,0xb3,0xf0,
9350x00,0xa0,0x88,0x21,0x00,0x06,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,
9360x80,0xa5,0x00,0x11,0x92,0x03,0x00,0x12,0x10,0xa0,0x00,0x04,0xa2,0x20,0x00,0x15,
9370x24,0x02,0x00,0x12,0x10,0xc2,0x00,0xda,0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x12,
9380x00,0x00,0x00,0x00,0x10,0x40,0x00,0x67,0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x12,
9390xa2,0x00,0x00,0x19,0x86,0x23,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,
9400x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,
9410xa0,0x40,0x00,0x00,0x92,0x03,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0xdf,
9420xa2,0x03,0x00,0x16,0x82,0x02,0x00,0x12,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,
9430x00,0x00,0x00,0x00,0x92,0x23,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x45,
9440x24,0x02,0x00,0x01,0xa2,0x20,0x00,0x04,0x92,0x08,0x00,0x04,0x00,0x00,0x00,0x00,
9450x15,0x00,0x00,0x1e,0x24,0x02,0x00,0x01,0x92,0x07,0x00,0x0a,0xa2,0x02,0x00,0x17,
9460x92,0x02,0x00,0x16,0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xe4,0x10,0x60,0x00,0x03,
9470xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x11,0x00,0x00,0x05,
9480x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,
9490xa2,0x02,0x00,0x16,0x92,0x02,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x08,
9500x00,0x00,0x00,0x00,0x96,0x02,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x02,0x00,0x14,
9510x8f,0xbf,0x00,0x20,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
9520x96,0x02,0x00,0x00,0x08,0x00,0x0e,0x68,0xa6,0x02,0x00,0x14,0x92,0x07,0x00,0x0a,
9530x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x54,
9540xa2,0x00,0x00,0x17,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x8f,0xf0,
9550x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,
9560x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,
9570x8c,0x66,0x00,0x08,0x8c,0x45,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xc3,0x20,0x24,
9580x10,0x80,0x00,0x08,0x00,0xa3,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,
9590x10,0x80,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x54,
9600xa2,0x03,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x88,
9610x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,
9620x24,0x02,0x00,0x03,0x14,0x62,0xff,0xb8,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x4e,
9630xa2,0x20,0x00,0x07,0x08,0x00,0x0e,0x4e,0xa2,0x20,0x00,0x06,0x08,0x00,0x0e,0x4e,
9640xa2,0x20,0x00,0x05,0x82,0x22,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x69,
9650x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x49,0x3c,0x02,0xb0,0x09,0x92,0x25,0x00,0x08,
9660x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x3b,
9670x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
9680x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,
9690xa0,0x83,0x00,0x00,0x86,0x23,0x00,0x0c,0x96,0x26,0x00,0x0c,0x00,0x03,0x10,0xc0,
9700x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,0x27,0x83,0x8f,0xf4,0x00,0xa3,0x18,0x21,
9710x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00,
9720x30,0x42,0x00,0x10,0x10,0x40,0x00,0x18,0x24,0x07,0x00,0x01,0x93,0x82,0x8b,0x61,
9730x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x0a,0x24,0x05,0x00,0x24,
9740x00,0x06,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x84,0x02,0x00,0x20,0x21,
9750x92,0x02,0x00,0x16,0xa2,0x00,0x00,0x12,0x30,0x42,0x00,0xe7,0x08,0x00,0x0e,0x45,
9760xa2,0x02,0x00,0x16,0xf0,0xc5,0x00,0x06,0x00,0x00,0x28,0x12,0x27,0x82,0x8f,0xf0,
9770x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x4b,0x3c,0x04,0x00,0x80,0x96,0x26,0x00,0x0c,
9780x08,0x00,0x0e,0xc5,0x00,0x06,0x2c,0x00,0x27,0x83,0x90,0x00,0x27,0x82,0x90,0x08,
9790x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05,
9800x93,0x82,0x80,0x10,0x00,0x00,0x30,0x21,0x0c,0x00,0x21,0xf5,0xaf,0xa2,0x00,0x10,
9810x96,0x26,0x00,0x0c,0x08,0x00,0x0e,0xbf,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xcd,
9820x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,
9830x24,0x02,0x00,0x80,0x08,0x00,0x0e,0xae,0x00,0xa2,0x10,0x07,0x86,0x26,0x00,0x0c,
9840x3c,0x03,0xb0,0x09,0x34,0x42,0x01,0x72,0x34,0x63,0x01,0x78,0x94,0x47,0x00,0x00,
9850x8c,0x65,0x00,0x00,0x00,0x06,0x10,0xc0,0x00,0x46,0x10,0x21,0x3c,0x04,0xb0,0x09,
9860xae,0x25,0x00,0x1c,0x34,0x84,0x01,0x7c,0x27,0x83,0x8f,0xf4,0x00,0x02,0x10,0x80,
9870x8c,0x85,0x00,0x00,0x00,0x43,0x10,0x21,0x8c,0x43,0x00,0x18,0xae,0x25,0x00,0x20,
9880xa6,0x27,0x00,0x18,0x8c,0x66,0x00,0x08,0x02,0x20,0x20,0x21,0x0c,0x00,0x0f,0x15,
9890x00,0x00,0x28,0x21,0x86,0x25,0x00,0x18,0x8e,0x26,0x00,0x1c,0x8e,0x27,0x00,0x20,
9900x02,0x20,0x20,0x21,0x0c,0x00,0x1c,0x86,0xaf,0xa2,0x00,0x10,0x08,0x00,0x0e,0x45,
9910xa2,0x02,0x00,0x12,0x92,0x22,0x00,0x08,0x08,0x00,0x0e,0x45,0xa2,0x22,0x00,0x09,
9920xa2,0x20,0x00,0x11,0x80,0x82,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,
9930x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xac,0x40,0x00,0x00,0x08,0x00,0x0e,0x45,
9940xa0,0x80,0x00,0x50,0x94,0x8a,0x00,0x0c,0x24,0x03,0x00,0x24,0x00,0x80,0x70,0x21,
9950x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x24,0x42,0x3c,0x54,0xf1,0x43,0x00,0x06,
9960x34,0x84,0x00,0x20,0x00,0x00,0x18,0x12,0x00,0xa0,0x68,0x21,0xac,0x82,0x00,0x00,
9970x27,0x85,0x90,0x00,0x27,0x82,0x8f,0xff,0x27,0xbd,0xff,0xf8,0x00,0x62,0x60,0x21,
9980x00,0x65,0x58,0x21,0x00,0x00,0xc0,0x21,0x11,0xa0,0x00,0xcc,0x00,0x00,0x78,0x21,
9990x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
10000x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x91,0x87,0x00,0x00,0x80,0x48,0x00,0x04,
10010x03,0xa0,0x60,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,
10020x00,0x43,0x10,0x21,0x00,0x02,0x48,0x80,0x27,0x83,0x8f,0xf4,0xa3,0xa7,0x00,0x00,
10030x01,0x23,0x18,0x21,0x8c,0x64,0x00,0x18,0x25,0x02,0xff,0xff,0x00,0x48,0x40,0x0b,
10040x8c,0x83,0x00,0x04,0x2d,0x05,0x00,0x07,0x24,0x02,0x00,0x06,0x30,0x63,0x00,0x08,
10050x14,0x60,0x00,0x35,0x00,0x45,0x40,0x0a,0x93,0xa7,0x00,0x00,0x27,0x82,0x90,0x08,
10060x01,0x22,0x10,0x21,0x30,0xe3,0x00,0xf0,0x38,0x63,0x00,0x50,0x30,0xe5,0x00,0xff,
10070x00,0x05,0x20,0x2b,0x00,0x03,0x18,0x2b,0x00,0x64,0x18,0x24,0x90,0x49,0x00,0x00,
10080x10,0x60,0x00,0x16,0x30,0xe4,0x00,0x0f,0x24,0x02,0x00,0x04,0x10,0xa2,0x00,0x9d,
10090x00,0x00,0x00,0x00,0x11,0xa0,0x00,0x3a,0x2c,0xa2,0x00,0x0c,0x10,0x40,0x00,0x02,
10100x24,0x84,0x00,0x0c,0x00,0xe0,0x20,0x21,0x30,0x84,0x00,0xff,0x00,0x04,0x10,0x40,
10110x27,0x83,0xbb,0x0c,0x00,0x44,0x10,0x21,0x00,0x43,0x10,0x21,0x90,0x47,0x00,0x00,
10120x00,0x00,0x00,0x00,0x2c,0xe3,0x00,0x0c,0xa3,0xa7,0x00,0x00,0x10,0x60,0x00,0x02,
10130x24,0xe2,0x00,0x04,0x00,0xe0,0x10,0x21,0xa3,0xa2,0x00,0x00,0x91,0x65,0x00,0x00,
10140x91,0x82,0x00,0x00,0x30,0xa3,0x00,0xff,0x00,0x62,0x10,0x2b,0x10,0x40,0x00,0x0e,
10150x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0x60,0x20,0x21,0x30,0xa2,0x00,0x0f,
10160x24,0x44,0x00,0x0c,0x00,0x04,0x10,0x40,0x00,0x44,0x20,0x21,0x27,0x83,0xbb,0x0c,
10170x00,0x83,0x18,0x21,0x90,0x62,0x00,0x02,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,
10180x00,0x09,0x11,0x00,0xa1,0x85,0x00,0x00,0x93,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,
10190x27,0xbd,0x00,0x08,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23,
10200x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x27,0x83,0xb4,0x98,0x00,0x43,0x10,0x21,
10210x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x83,0x00,0x0c,0x14,0x60,0x00,0x06,
10220x00,0x80,0x10,0x21,0x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,
10230x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04,0x08,0x00,0x0f,0x76,0xa1,0x82,0x00,0x00,
10240x8f,0x8d,0x81,0x5c,0x00,0x00,0x00,0x00,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,
10250x00,0x00,0x00,0x00,0x10,0x60,0xff,0xd1,0x00,0x00,0x28,0x21,0x00,0x06,0x74,0x82,
10260x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0xe0,0x10,0x21,
10270x30,0xe2,0x00,0x0f,0x24,0x42,0x00,0x0c,0x30,0x44,0x00,0xff,0xa3,0xa2,0x00,0x00,
10280x24,0x02,0x00,0x0c,0x10,0x82,0x00,0x0d,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,
10290x00,0x02,0x10,0x80,0x00,0x04,0x18,0x40,0x00,0x49,0x10,0x23,0x00,0x64,0x18,0x21,
10300x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x27,0x84,0xb4,0x98,0x00,0x44,0x10,0x21,
10310x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xa7,0x00,0x00,0x00,0x0a,0x1c,0x00,
10320x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
10330x27,0x83,0x8f,0xf4,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,
10340x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0x00,0x33,
10350x00,0x06,0x14,0x42,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,
10360x00,0x49,0x10,0x23,0x27,0x83,0xb5,0x68,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
10370x90,0x44,0x00,0x04,0x90,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x00,0x64,0xc0,0x24,
10380x93,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe2,0x00,0x0f,0x10,0x40,0x00,0x0f,
10390x31,0xcf,0x00,0x01,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,
10400x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x8f,0xf0,0x00,0x44,0x10,0x21,
10410x84,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0x28,0x63,0x06,0x41,0x14,0x60,0x00,0x04,
10420x30,0xe2,0x00,0xff,0x24,0x07,0x00,0x0f,0xa3,0xa7,0x00,0x00,0x30,0xe2,0x00,0xff,
10430x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x06,0x00,0xe0,0x10,0x21,0x00,0x18,0x10,0x40,
10440x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x47,0x10,0x21,0x24,0x42,0x00,0x04,
10450xa3,0xa2,0x00,0x00,0x00,0x40,0x38,0x21,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,
10460x24,0xa4,0x00,0x01,0x30,0x85,0xff,0xff,0x00,0xa3,0x18,0x2b,0x14,0x60,0xff,0xad,
10470x30,0xe2,0x00,0xff,0x08,0x00,0x0f,0x63,0x00,0x00,0x00,0x00,0x08,0x00,0x0f,0xc4,
10480x30,0x58,0x00,0x01,0x81,0xc2,0x00,0x48,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x73,
10490x00,0x00,0x00,0x00,0x08,0x00,0x0f,0x51,0x00,0x00,0x00,0x00,0x00,0x0a,0x1c,0x00,
10500x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
10510x00,0x45,0x10,0x21,0x80,0x48,0x00,0x05,0x91,0x67,0x00,0x00,0x08,0x00,0x0f,0x31,
10520x03,0xa0,0x58,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
10530x24,0x42,0x3f,0xf4,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,
10540xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,
10550xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38,
10560xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x84,0x82,0x00,0x0c,0x27,0x93,0x8f,0xf4,
10570x3c,0x05,0xb0,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,
10580x00,0x73,0x10,0x21,0x8c,0x5e,0x00,0x18,0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,
10590x24,0x42,0x40,0x0c,0xac,0xa2,0x00,0x00,0x8f,0xd0,0x00,0x08,0x27,0x95,0x90,0x00,
10600x00,0x75,0x18,0x21,0x00,0x00,0x28,0x21,0x02,0x00,0x30,0x21,0x90,0x71,0x00,0x00,
10610x0c,0x00,0x0f,0x15,0x00,0x80,0xb0,0x21,0x00,0x40,0x90,0x21,0x00,0x10,0x14,0x42,
10620x30,0x54,0x00,0x01,0x02,0x40,0x20,0x21,0x00,0x10,0x14,0x82,0x02,0x80,0x28,0x21,
10630x12,0x51,0x00,0x23,0x00,0x10,0xbf,0xc2,0x86,0xc3,0x00,0x0c,0x30,0x50,0x00,0x01,
10640x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,
10650xa0,0x52,0x00,0x00,0x86,0xc3,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,
10660x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x53,0x30,0x21,0x8c,0xc7,0x00,0x18,
10670x27,0x83,0x8f,0xf0,0x00,0x43,0x10,0x21,0x8c,0xe3,0x00,0x04,0x84,0x46,0x00,0x06,
10680x00,0x03,0x19,0x42,0x0c,0x00,0x08,0xdf,0x30,0x73,0x00,0x01,0x00,0x40,0x88,0x21,
10690x02,0x40,0x20,0x21,0x02,0x80,0x28,0x21,0x16,0xe0,0x00,0x10,0x02,0x00,0x30,0x21,
10700x86,0xc2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,
10710x00,0x03,0x18,0x80,0x27,0x82,0x8f,0xf8,0x00,0x62,0x18,0x21,0xa4,0x71,0x00,0x04,
10720x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,
10730x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x86,0xc3,0x00,0x0c,
10740xaf,0xb3,0x00,0x10,0xaf,0xa0,0x00,0x14,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
10750x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,0x80,0x47,0x00,0x06,0x00,0x00,0x00,0x00,
10760x24,0xe7,0x00,0x02,0x00,0x07,0x17,0xc2,0x00,0xe2,0x38,0x21,0x00,0x07,0x38,0x43,
10770x00,0x07,0x38,0x40,0x0c,0x00,0x09,0x06,0x03,0xc7,0x38,0x21,0x08,0x00,0x10,0x44,
10780x02,0x22,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,
10790x34,0x63,0x00,0x20,0x24,0x42,0x41,0x94,0xaf,0xb2,0x00,0x20,0xac,0x62,0x00,0x00,
10800xaf,0xbf,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,
10810x3c,0x02,0xb0,0x03,0x90,0x83,0x00,0x0a,0x34,0x42,0x01,0x04,0x94,0x45,0x00,0x00,
10820x00,0x03,0x18,0x80,0x27,0x82,0xb3,0xf0,0x00,0x62,0x18,0x21,0x30,0xa6,0xff,0xff,
10830x8c,0x71,0x00,0x00,0x80,0x85,0x00,0x12,0x30,0xc9,0x00,0xff,0x00,0x06,0x32,0x02,
10840xa4,0x86,0x00,0x44,0xa4,0x89,0x00,0x46,0x82,0x22,0x00,0x12,0x00,0x80,0x90,0x21,
10850x10,0xa0,0x00,0x1b,0xa0,0x80,0x00,0x15,0x00,0xc5,0x10,0x2a,0x10,0x40,0x00,0x14,
10860x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x19,0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,
10870x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,
10880x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x80,0x00,0x12,0x92,0x22,0x00,0x16,
10890x00,0x00,0x00,0x00,0x30,0x42,0x00,0xdf,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x28,
10900x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
10910x0c,0x00,0x0f,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x10,0x93,0x00,0x00,0x00,0x00,
10920x28,0x42,0x00,0x02,0x10,0x40,0x01,0x76,0x00,0x00,0x28,0x21,0x94,0x87,0x00,0x0c,
10930x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x21,0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03,
10940x00,0x07,0x24,0x00,0x00,0x04,0x24,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,
10950x00,0x04,0x28,0xc0,0x00,0xa4,0x28,0x21,0x27,0x82,0x90,0x10,0x00,0x03,0x18,0x80,
10960x00,0x62,0x18,0x21,0x00,0x05,0x28,0x80,0x27,0x82,0x8f,0xf8,0x00,0xa2,0x10,0x21,
10970x8c,0x68,0x00,0x00,0x80,0x44,0x00,0x06,0x27,0x82,0x90,0x00,0x00,0x08,0x1d,0x02,
10980x00,0xa2,0x28,0x21,0x38,0x84,0x00,0x00,0x30,0x63,0x00,0x01,0x01,0x24,0x30,0x0b,
10990x80,0xaa,0x00,0x04,0x80,0xa9,0x00,0x05,0x10,0x60,0x00,0x02,0x00,0x08,0x14,0x02,
11000x30,0x46,0x00,0x0f,0x15,0x20,0x00,0x28,0x01,0x49,0x10,0x21,0x15,0x40,0x00,0x11,
11010x30,0xe3,0xff,0xff,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa8,0x00,0xff,
11020x2d,0x02,0x00,0x04,0x10,0x40,0x01,0x46,0x2d,0x02,0x00,0x10,0x3c,0x04,0xb0,0x05,
11030x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x01,0x02,0x10,0x04,
11040x00,0x62,0x18,0x25,0xa0,0x83,0x00,0x00,0x96,0x47,0x00,0x0c,0x00,0x00,0x00,0x00,
11050x30,0xe3,0xff,0xff,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x27,0x84,0x90,0x00,
11060x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,
11070x3c,0x04,0xb0,0x00,0x00,0x65,0x18,0x21,0x00,0x64,0x20,0x21,0x94,0x82,0x00,0x00,
11080x82,0x43,0x00,0x10,0x00,0x02,0x14,0x00,0x14,0x60,0x00,0x06,0x00,0x02,0x3c,0x03,
11090x30,0xe2,0x00,0x04,0x14,0x40,0x00,0x04,0x01,0x49,0x10,0x21,0x34,0xe2,0x08,0x00,
11100xa4,0x82,0x00,0x00,0x01,0x49,0x10,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
11110x00,0x46,0x10,0x2a,0x10,0x40,0x00,0x7c,0x00,0x00,0x00,0x00,0x82,0x42,0x00,0x10,
11120x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x86,0x43,0x00,0x0c,
11130x25,0x44,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
11140x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x04,0x92,0x23,0x00,0x16,
11150x02,0x40,0x20,0x21,0x30,0x63,0x00,0xfb,0x08,0x00,0x10,0x98,0xa2,0x23,0x00,0x16,
11160x86,0x43,0x00,0x0c,0x25,0x24,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
11170x00,0x02,0x10,0x80,0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x05,
11180x86,0x45,0x00,0x0c,0x0c,0x00,0x1f,0x08,0x02,0x20,0x20,0x21,0x10,0x40,0x00,0x5a,
11190x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,
11200x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x4c,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,
11210x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,
11220x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08,
11230x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x33,0x24,0x02,0x00,0x01,
11240xa2,0x40,0x00,0x04,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0c,
11250x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,
11260x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x96,0x22,0x00,0x06,0x08,0x00,0x10,0x93,
11270xa6,0x22,0x00,0x14,0x96,0x22,0x00,0x00,0x08,0x00,0x10,0x93,0xa6,0x22,0x00,0x14,
11280x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
11290x08,0x00,0x11,0x22,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,
11300x27,0x86,0x8f,0xf0,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,
11310x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,
11320x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,
11330x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,
11340x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,
11350x08,0x00,0x11,0x22,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,
11360x08,0x00,0x11,0x45,0x00,0x00,0x00,0x00,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,
11370x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xca,0x00,0x00,0x00,0x00,
11380x08,0x00,0x11,0x1d,0xa2,0x40,0x00,0x07,0x08,0x00,0x11,0x1d,0xa2,0x40,0x00,0x06,
11390x08,0x00,0x11,0x1d,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0xbe,0x3c,0x04,0xb0,0x05,
11400x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,
11410x08,0x00,0x11,0x14,0x00,0xa2,0x10,0x07,0x0c,0x00,0x10,0x03,0x02,0x40,0x20,0x21,
11420x08,0x00,0x10,0x93,0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,
11430x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x99,0x2c,0xc2,0x00,0x10,
11440x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,
11450x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,
11460x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x80,
11470x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x86,0x43,0x00,0x0c,0x27,0x93,0x8f,0xf4,
11480x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,
11490x00,0xb3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,
11500x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x64,0x00,0x00,0x30,0x21,
11510x00,0x07,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
11520x00,0x02,0x10,0x80,0x00,0x53,0x10,0x21,0x8c,0x43,0x00,0x18,0x93,0x82,0x8b,0x61,
11530x8c,0x64,0x00,0x04,0x30,0x42,0x00,0x01,0x00,0x04,0x21,0x42,0x14,0x40,0x00,0x4d,
11540x30,0x90,0x00,0x01,0x00,0x07,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x84,
11550x02,0x20,0x20,0x21,0x96,0x26,0x00,0x06,0x12,0x00,0x00,0x14,0x30,0xc5,0xff,0xff,
11560x02,0x60,0x90,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x02,0x10,0x80,
11570x00,0x52,0x18,0x21,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,
11580x02,0x20,0x20,0x21,0x8c,0x63,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x62,0x00,0x04,
11590x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x0c,0x00,0x1b,0x84,0x30,0x50,0x00,0x01,
11600x96,0x26,0x00,0x06,0x16,0x00,0xff,0xef,0x30,0xc5,0xff,0xff,0x92,0x22,0x00,0x04,
11610x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0d,0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,
11620x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,
11630xa6,0x26,0x00,0x14,0x92,0x22,0x00,0x16,0x08,0x00,0x10,0x92,0x30,0x42,0x00,0xc3,
11640x96,0x22,0x00,0x00,0x08,0x00,0x11,0xb9,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a,
11650x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0xb4,
11660xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x30,0xc5,0xff,0xff,0x00,0x05,0x18,0xc0,
11670x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x27,0x84,0x8f,0xf0,
11680x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x00,0x03,0x18,0x80,0x8c,0x45,0x00,0x08,
11690x00,0x64,0x18,0x21,0x8c,0x64,0x00,0x08,0x3c,0x02,0x80,0x00,0x00,0xa2,0x38,0x24,
11700x10,0xe0,0x00,0x08,0x00,0x82,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,
11710x10,0xe0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xb4,
11720xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xd8,
11730x00,0x00,0x00,0x00,0x24,0x05,0x00,0x24,0xf0,0xe5,0x00,0x06,0x00,0x00,0x28,0x12,
11740x27,0x82,0x8f,0xf0,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x4b,0x00,0x00,0x20,0x21,
11750x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x96,0x00,0x07,0x2c,0x00,0x27,0x83,0x90,0x00,
11760x27,0x82,0x90,0x08,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,
11770x90,0x65,0x00,0x05,0x93,0x82,0x80,0x10,0x24,0x07,0x00,0x01,0x0c,0x00,0x21,0xf5,
11780xaf,0xa2,0x00,0x10,0x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x89,0x00,0x07,0x1c,0x00,
11790x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,
11800x14,0xa2,0xff,0x7d,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0x7a,0xa2,0x40,0x00,0x07,
11810x08,0x00,0x11,0x7a,0xa2,0x40,0x00,0x06,0x08,0x00,0x11,0x7a,0xa2,0x40,0x00,0x05,
11820x14,0x40,0xff,0x71,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
11830x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x11,0x71,0x00,0xa2,0x10,0x07,
11840x14,0x40,0xfe,0xc3,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
11850x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x10,0xcc,0x00,0xa2,0x10,0x07,
11860x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
11870x00,0x02,0x10,0x80,0x27,0x83,0x8f,0xf4,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,
11880x00,0x00,0x00,0x00,0x8c,0xe6,0x00,0x08,0x0c,0x00,0x0f,0x15,0x00,0x00,0x00,0x00,
11890x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x00,0x00,0x30,0x21,0x00,0x00,0x38,0x21,
11900x0c,0x00,0x1c,0x86,0xaf,0xa2,0x00,0x10,0x00,0x02,0x1e,0x00,0x14,0x60,0xfe,0x6b,
11910xa2,0x22,0x00,0x12,0x92,0x43,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x40,
11920x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x92,0x28,0x00,0x04,0x00,0x00,0x00,0x00,
11930x15,0x00,0x00,0x19,0x24,0x02,0x00,0x01,0x92,0x27,0x00,0x0a,0xa2,0x22,0x00,0x17,
11940x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x10,0x00,0x00,0x00,0x00,
11950x96,0x22,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x16,
11960x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xc0,0x10,0x60,0x00,0x03,0xa2,0x22,0x00,0x16,
11970x34,0x42,0x00,0x01,0xa2,0x22,0x00,0x16,0x11,0x00,0xfe,0x50,0x00,0x00,0x00,0x00,
11980x92,0x22,0x00,0x16,0x08,0x00,0x10,0x92,0x34,0x42,0x00,0x02,0x96,0x22,0x00,0x00,
11990x08,0x00,0x12,0x3b,0xa6,0x22,0x00,0x14,0x92,0x27,0x00,0x0a,0x00,0x00,0x00,0x00,
12000x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x34,0xa2,0x20,0x00,0x17,
12010x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,0x27,0x86,0x8f,0xf0,0x00,0x04,0x18,0xc0,
12020x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,
12030x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,
12040x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,
12050x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,
12060x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x34,0xa2,0x23,0x00,0x17,
12070x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x63,0x00,0x00,0x00,0x00,
12080x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,
12090x14,0x62,0xff,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x2e,0xa2,0x40,0x00,0x07,
12100x08,0x00,0x12,0x2e,0xa2,0x40,0x00,0x06,0x08,0x00,0x12,0x2e,0xa2,0x40,0x00,0x05,
12110x3c,0x02,0x80,0x00,0x00,0x82,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0xa2,0x18,0x24,
12120x10,0x60,0x00,0x04,0x00,0x00,0x10,0x21,0x10,0xc0,0x00,0x02,0x24,0x02,0x00,0x01,
12130x00,0xa4,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xfd,
12140x00,0xa4,0x10,0x2b,0x08,0x00,0x12,0x7e,0x00,0x00,0x00,0x00,0x30,0x82,0xff,0xff,
12150x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x27,0x84,0x90,0x00,0x00,0x03,0x18,0x80,
12160x00,0x64,0x18,0x21,0x80,0x66,0x00,0x06,0x00,0x02,0x12,0x00,0x3c,0x03,0xb0,0x00,
12170x00,0x46,0x10,0x21,0x00,0x45,0x10,0x21,0x03,0xe0,0x00,0x08,0x00,0x43,0x10,0x21,
12180x27,0xbd,0xff,0xe0,0x30,0x82,0x00,0x7c,0x30,0x84,0xff,0x00,0xaf,0xbf,0x00,0x1c,
12190xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x14,0x40,0x00,0x41,
12200x00,0x04,0x22,0x03,0x24,0x02,0x00,0x04,0x3c,0x10,0xb0,0x03,0x8e,0x10,0x00,0x00,
12210x10,0x82,0x00,0x32,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x03,0x32,0x02,0x00,0x20,
12220x08,0x00,0x12,0xa4,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x06,
12230x34,0x42,0x80,0x24,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x67,0x00,0xff,
12240x10,0xe0,0x00,0x23,0x00,0x00,0x88,0x21,0x8f,0x85,0x8f,0xd0,0x00,0x40,0x30,0x21,
12250x94,0xa2,0x00,0x08,0x8c,0xc3,0x00,0x00,0x26,0x31,0x00,0x01,0x24,0x42,0x00,0x02,
12260x30,0x42,0x01,0xff,0x34,0x63,0x01,0x00,0x02,0x27,0x20,0x2a,0xa4,0xa2,0x00,0x08,
12270x14,0x80,0xff,0xf7,0xac,0xc3,0x00,0x00,0x84,0xa3,0x00,0x08,0x3c,0x02,0xb0,0x03,
12280x34,0x42,0x00,0x30,0xac,0x43,0x00,0x00,0x27,0x92,0xb3,0xf0,0x24,0x11,0x00,0x12,
12290x8e,0x44,0x00,0x00,0x26,0x31,0xff,0xff,0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,
12300x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04,0x0c,0x00,0x20,0xd0,0x00,0x00,0x00,0x00,
12310x06,0x21,0xff,0xf7,0x24,0x02,0xff,0xdf,0x02,0x02,0x80,0x24,0x3c,0x01,0xb0,0x03,
12320x0c,0x00,0x13,0x18,0xac,0x30,0x00,0x00,0x08,0x00,0x12,0xa4,0x00,0x00,0x00,0x00,
12330x8f,0x85,0x8f,0xd0,0x08,0x00,0x12,0xba,0x00,0x00,0x00,0x00,0x24,0x02,0xff,0x95,
12340x3c,0x03,0xb0,0x03,0x02,0x02,0x80,0x24,0x34,0x63,0x00,0x30,0x3c,0x01,0xb0,0x03,
12350xac,0x30,0x00,0x00,0x0c,0x00,0x12,0xe1,0xac,0x60,0x00,0x00,0x08,0x00,0x12,0xa4,
12360x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x50,0x08,0x00,0x12,0xa4,
12370xac,0x46,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0x84,0x3c,0x0b,0xb0,0x03,
12380xad,0x6a,0x00,0x20,0x3c,0x08,0x80,0x01,0x25,0x08,0x00,0x00,0x3c,0x09,0x80,0x01,
12390x25,0x29,0x03,0x1c,0x11,0x09,0x00,0x10,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,
12400x25,0x4a,0x4b,0xac,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x08,0xb0,0x06,
12410x35,0x08,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,
12420x00,0x00,0x00,0x00,0x31,0x29,0x00,0x01,0x00,0x00,0x00,0x00,0x24,0x01,0x00,0x01,
12430x15,0x21,0xff,0xf2,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0xe8,
12440x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0xb0,0x03,0x8c,0x43,0x00,0x00,
12450x00,0x00,0x00,0x00,0x34,0x63,0x00,0x40,0x00,0x00,0x00,0x00,0xac,0x43,0x00,0x00,
12460x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x14,0x3c,0x0b,0xb0,0x03,
12470xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01,0x24,0x42,0x00,0x00,0x3c,0x03,0x80,0x01,
12480x24,0x63,0x03,0x1c,0x3c,0x04,0xb0,0x00,0x8c,0x85,0x00,0x00,0x00,0x00,0x00,0x00,
12490xac,0x45,0x00,0x00,0x24,0x42,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x43,0x08,0x2a,
12500x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,0x0c,0x00,0x13,0x18,0x00,0x00,0x00,0x00,
12510x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x60,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
12520x3c,0x02,0x80,0x01,0x24,0x42,0x03,0x20,0x3c,0x03,0x80,0x01,0x24,0x63,0x3f,0x14,
12530xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0xac,0x40,0x00,0x08,0xac,0x40,0x00,0x0c,
12540x24,0x42,0x00,0x10,0x00,0x43,0x08,0x2a,0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,
12550x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xa0,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
12560x3c,0x1c,0x80,0x01,0x27,0x9c,0x7f,0xf0,0x27,0x9d,0x8b,0xd0,0x00,0x00,0x00,0x00,
12570x27,0x9d,0x8f,0xb8,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xc4,0x3c,0x0b,0xb0,0x03,
12580xad,0x6a,0x00,0x20,0x40,0x80,0x68,0x00,0x40,0x08,0x60,0x00,0x00,0x00,0x00,0x00,
12590x35,0x08,0xff,0x01,0x40,0x88,0x60,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x15,0x65,
12600x00,0x00,0x00,0x00,0x24,0x84,0xf8,0x00,0x30,0x87,0x00,0x03,0x00,0x04,0x30,0x40,
12610x00,0xc7,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x27,0xbd,0xff,0xe0,0x24,0x03,0xff,0xff,
12620x00,0x82,0x20,0x21,0xaf,0xb1,0x00,0x14,0xac,0x83,0x10,0x00,0xaf,0xbf,0x00,0x18,
12630xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x10,0x00,
12640x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0xc7,0x10,0x23,0x3c,0x03,0xb0,0x0a,
12650x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x0c,0x00,0x13,0x95,0x02,0x20,0x20,0x21,
12660x02,0x11,0x80,0x24,0x00,0x50,0x80,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,
12670x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,
12680xaf,0xb2,0x00,0x18,0x00,0xa0,0x90,0x21,0x24,0x05,0xff,0xff,0xaf,0xb3,0x00,0x1c,
12690xaf,0xbf,0x00,0x20,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x00,0xc0,0x98,0x21,
12700x12,0x45,0x00,0x23,0x24,0x84,0xf8,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x10,0x40,
12710x00,0x40,0x88,0x21,0x00,0x60,0x20,0x21,0x00,0x43,0x10,0x23,0x3c,0x03,0xb0,0x0a,
12720x00,0x43,0x10,0x21,0xac,0x45,0x10,0x00,0x00,0x40,0x18,0x21,0x24,0x05,0x00,0x01,
12730x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x45,0xff,0xfd,0x3c,0x02,0xb0,0x0a,
12740x02,0x24,0x88,0x23,0x02,0x22,0x88,0x21,0x8e,0x30,0x00,0x00,0x0c,0x00,0x13,0x95,
12750x02,0x40,0x20,0x21,0x00,0x12,0x18,0x27,0x02,0x03,0x80,0x24,0x00,0x53,0x10,0x04,
12760x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x24,0x03,0x00,0x01,0x8e,0x22,0x10,0x00,
12770x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20,
12780x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
12790x30,0x82,0x00,0x03,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x23,0x3c,0x04,0xb0,0x0a,
12800x00,0x64,0x18,0x21,0xac,0x66,0x00,0x00,0x24,0x04,0x00,0x01,0x8c,0x62,0x10,0x00,
12810x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x13,0x83,
12820x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x64,0x10,0x06,0x30,0x42,0x00,0x01,
12830x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x20,
12840x14,0x40,0xff,0xf9,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,
12850x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x05,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
12860xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0x00,0x80,0x90,0x21,0x00,0xa0,0x80,0x21,
12870x00,0xc0,0x88,0x21,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
12880x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfc,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0,
12890x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,
12900x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x03,0x3c,0x02,0xc0,0x00,0x00,0x10,0x1c,0x00,
12910x34,0x42,0x04,0x00,0x3c,0x04,0xb0,0x05,0x3c,0x05,0xb0,0x05,0x24,0x63,0x16,0x09,
12920x02,0x22,0x10,0x21,0x34,0x84,0x04,0x20,0x34,0xa5,0x04,0x24,0x3c,0x06,0xb0,0x05,
12930xac,0x83,0x00,0x00,0x24,0x07,0x00,0x01,0xac,0xa2,0x00,0x00,0x34,0xc6,0x02,0x28,
12940x24,0x02,0x00,0x20,0xae,0x47,0x00,0x3c,0x24,0x04,0x08,0x24,0xa0,0xc2,0x00,0x00,
12950x3c,0x05,0x00,0xc0,0xa2,0x47,0x00,0x11,0x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,
12960x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,0x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,
12970x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
12980x27,0xbd,0x00,0x20,0x24,0x02,0x00,0x06,0xac,0x82,0x00,0x0c,0xa0,0x80,0x00,0x50,
12990xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x14,
13000xac,0x80,0x00,0x18,0xac,0x80,0x00,0x1c,0xa4,0x80,0x00,0x20,0xac,0x80,0x00,0x24,
13010xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,0xa0,0x80,0x00,0x30,0xa0,0x80,0x00,0x31,
13020xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xa0,0x80,0x00,0x3c,0xac,0x82,0x00,0x10,
13030xa0,0x80,0x00,0x44,0xac,0x80,0x00,0x48,0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x4c,
13040x3c,0x04,0xb0,0x06,0x34,0x84,0x80,0x00,0x8c,0x83,0x00,0x00,0x3c,0x02,0x12,0x00,
13050x3c,0x05,0xb0,0x03,0x00,0x62,0x18,0x25,0x34,0xa5,0x00,0x8b,0x24,0x02,0xff,0x80,
13060xac,0x83,0x00,0x00,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x00,0x3c,0x04,0xb0,0x03,
13070x34,0x84,0x00,0x0b,0x24,0x02,0x00,0x22,0x3c,0x05,0xb0,0x01,0x3c,0x06,0x45,0x67,
13080x3c,0x0a,0xb0,0x09,0xa0,0x82,0x00,0x00,0x34,0xa5,0x00,0x04,0x34,0xc6,0x89,0xaa,
13090x35,0x4a,0x00,0x04,0x24,0x02,0x01,0x23,0x3c,0x0b,0xb0,0x09,0x3c,0x07,0x01,0x23,
13100x3c,0x0c,0xb0,0x09,0x3c,0x01,0xb0,0x01,0xac,0x20,0x00,0x00,0x27,0xbd,0xff,0xe0,
13110xac,0xa0,0x00,0x00,0x35,0x6b,0x00,0x08,0x3c,0x01,0xb0,0x09,0xac,0x26,0x00,0x00,
13120x34,0xe7,0x45,0x66,0xa5,0x42,0x00,0x00,0x35,0x8c,0x00,0x0c,0x24,0x02,0xcd,0xef,
13130x3c,0x0d,0xb0,0x09,0x3c,0x08,0xcd,0xef,0x3c,0x0e,0xb0,0x09,0xad,0x67,0x00,0x00,
13140xaf,0xb7,0x00,0x1c,0xa5,0x82,0x00,0x00,0xaf,0xb6,0x00,0x18,0xaf,0xb5,0x00,0x14,
13150xaf,0xb4,0x00,0x10,0xaf,0xb3,0x00,0x0c,0xaf,0xb2,0x00,0x08,0xaf,0xb1,0x00,0x04,
13160xaf,0xb0,0x00,0x00,0x35,0xad,0x00,0x10,0x35,0x08,0x01,0x22,0x35,0xce,0x00,0x14,
13170x24,0x02,0x89,0xab,0x3c,0x0f,0xb0,0x09,0x3c,0x09,0x89,0xab,0x3c,0x10,0xb0,0x09,
13180x3c,0x11,0xb0,0x09,0x3c,0x12,0xb0,0x09,0x3c,0x13,0xb0,0x09,0x3c,0x14,0xb0,0x09,
13190x3c,0x15,0xb0,0x09,0x3c,0x16,0xb0,0x09,0x3c,0x17,0xb0,0x09,0xad,0xa8,0x00,0x00,
13200x24,0x03,0xff,0xff,0xa5,0xc2,0x00,0x00,0x35,0xef,0x00,0x18,0x35,0x29,0xcd,0xee,
13210x36,0x10,0x00,0x1c,0x36,0x31,0x00,0x20,0x36,0x52,0x00,0x24,0x36,0x73,0x00,0x28,
13220x36,0x94,0x00,0x2c,0x36,0xb5,0x00,0x30,0x36,0xd6,0x00,0x34,0x36,0xf7,0x00,0x38,
13230x24,0x02,0x45,0x67,0xad,0xe9,0x00,0x00,0xa6,0x02,0x00,0x00,0xae,0x23,0x00,0x00,
13240x8f,0xb0,0x00,0x00,0xa6,0x43,0x00,0x00,0x8f,0xb1,0x00,0x04,0xae,0x63,0x00,0x00,
13250x8f,0xb2,0x00,0x08,0xa6,0x83,0x00,0x00,0x8f,0xb3,0x00,0x0c,0xae,0xa3,0x00,0x00,
13260x8f,0xb4,0x00,0x10,0xa6,0xc3,0x00,0x00,0x8f,0xb5,0x00,0x14,0xae,0xe3,0x00,0x00,
13270x7b,0xb6,0x00,0xfc,0x3c,0x18,0xb0,0x09,0x37,0x18,0x00,0x3c,0xa7,0x03,0x00,0x00,
13280x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
13290x34,0x63,0x00,0x20,0x24,0x42,0x51,0x38,0xac,0x62,0x00,0x00,0x8c,0x83,0x00,0x34,
13300x34,0x02,0xff,0xff,0x00,0x43,0x10,0x2a,0x14,0x40,0x01,0x0b,0x00,0x80,0x30,0x21,
13310x8c,0x84,0x00,0x08,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0xfe,0x00,0x00,0x00,0x00,
13320x8c,0xc2,0x00,0x2c,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x47,0x24,0x02,0x00,0x06,
13330x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
13340x30,0x42,0x00,0xff,0x14,0x40,0x00,0xe4,0xac,0xc2,0x00,0x2c,0x24,0x02,0x00,0x01,
13350x10,0x82,0x00,0xe3,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0xd1,
13360x00,0x00,0x00,0x00,0x8c,0xc7,0x00,0x04,0x24,0x02,0x00,0x02,0x10,0xe2,0x00,0xc7,
13370x00,0x00,0x00,0x00,0x8c,0xc2,0x00,0x14,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x09,
13380x24,0x02,0x00,0x01,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,
13390x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x05,0xac,0xc2,0x00,0x14,
13400x24,0x02,0x00,0x01,0xac,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xc0,0x00,0x14,
13410x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
13420x04,0x61,0x00,0x16,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,
13430x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x10,0x3c,0x02,0xb0,0x05,
13440x34,0x42,0x02,0x42,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0b,
13450x00,0x00,0x00,0x00,0x80,0xc2,0x00,0x50,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x07,
13460x00,0x00,0x00,0x00,0x14,0x80,0x00,0x05,0x24,0x02,0x00,0x0e,0x24,0x03,0x00,0x01,
13470xac,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0xa0,0xc3,0x00,0x50,0x80,0xc2,0x00,0x31,
13480x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,
13490x8c,0x43,0x00,0x00,0x3c,0x04,0xf0,0x00,0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24,
13500x10,0x62,0x00,0x03,0x24,0x02,0x00,0x09,0x03,0xe0,0x00,0x08,0xac,0xc2,0x00,0x00,
13510x8c,0xc2,0x00,0x40,0x00,0x00,0x00,0x00,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
13520x10,0x60,0x00,0x09,0x3c,0x03,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,
13530x8c,0x43,0x00,0x00,0x3c,0x04,0x00,0x02,0x00,0x64,0x18,0x24,0x14,0x60,0xff,0xf2,
13540x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03,0x34,0x63,0x02,0x01,0x90,0x62,0x00,0x00,
13550x00,0x00,0x00,0x00,0x30,0x42,0x00,0x80,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,
13560x8c,0xc3,0x00,0x0c,0x00,0x00,0x00,0x00,0xac,0xc3,0x00,0x10,0x3c,0x02,0xb0,0x03,
13570x90,0x42,0x02,0x01,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0xac,0xc2,0x00,0x0c,
13580x90,0xc3,0x00,0x0f,0x24,0x02,0x00,0x0d,0x3c,0x01,0xb0,0x03,0x08,0x00,0x14,0xa6,
13590xa0,0x23,0x02,0x01,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x80,0x90,0x44,0x00,0x00,
13600x00,0x00,0x00,0x00,0x00,0x04,0x1e,0x00,0x00,0x03,0x1e,0x03,0x10,0x60,0x00,0x15,
13610xa0,0xc4,0x00,0x44,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x0b,0x24,0x02,0x00,0x02,
13620x10,0x62,0x00,0x03,0x24,0x03,0x00,0x0d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
13630x8c,0xc2,0x00,0x0c,0xac,0xc3,0x00,0x00,0x24,0x03,0x00,0x04,0xac,0xc2,0x00,0x10,
13640x03,0xe0,0x00,0x08,0xac,0xc3,0x00,0x0c,0x24,0x02,0x00,0x0d,0xac,0xc2,0x00,0x00,
13650x24,0x03,0x00,0x04,0x24,0x02,0x00,0x06,0xac,0xc3,0x00,0x10,0x03,0xe0,0x00,0x08,
13660xac,0xc2,0x00,0x0c,0x8c,0xc3,0x00,0x38,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x06,
13670x10,0x40,0x00,0x2e,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x02,0x00,
13680x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,
13690x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xe2,0x00,0x06,0x24,0x02,0x00,0x03,
13700x8c,0xa2,0x02,0xbc,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x06,0x3c,0x03,0xb0,0x06,
13710x24,0x02,0x00,0x02,0xac,0xc2,0x00,0x00,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,
13720xac,0xc2,0x00,0x38,0x34,0x63,0x80,0x24,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
13730x30,0x42,0x00,0xff,0x10,0x40,0x00,0x05,0xac,0xc2,0x00,0x18,0x24,0x02,0x00,0x02,
13740xac,0xc2,0x00,0x00,0x08,0x00,0x14,0xfa,0xac,0xc0,0x00,0x18,0x08,0x00,0x14,0xfa,
13750xac,0xc0,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x0b,0xac,0xc2,0x00,0x38,
13760x03,0xe0,0x00,0x08,0xac,0xc3,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xe2,0x00,0x05,
13770x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0c,0xac,0xc2,0x00,0x00,0x08,0x00,0x14,0xfb,
13780x24,0x02,0x00,0x04,0x08,0x00,0x15,0x12,0x24,0x02,0x00,0x03,0xac,0xc0,0x00,0x38,
13790x03,0xe0,0x00,0x08,0xac,0xc0,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xe2,0x00,0x05,
13800x24,0x02,0x00,0x03,0x80,0xc2,0x00,0x30,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x08,
13810x24,0x02,0x00,0x04,0xac,0xc2,0x00,0x00,0x93,0x82,0x86,0x3c,0x00,0x00,0x00,0x00,
13820x14,0x40,0xff,0xd6,0x24,0x02,0x00,0x05,0x03,0xe0,0x00,0x08,0xac,0xc0,0x00,0x38,
13830x08,0x00,0x15,0x22,0xac,0xc0,0x00,0x00,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,
13840x8c,0x43,0x00,0x00,0x3c,0x04,0xf0,0x00,0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24,
13850x10,0x62,0x00,0x03,0x24,0x02,0x00,0x09,0x08,0x00,0x15,0x26,0xac,0xc2,0x00,0x00,
13860x24,0x02,0x00,0x05,0x08,0x00,0x15,0x18,0xac,0xc2,0x00,0x38,0x80,0xc2,0x00,0x30,
13870x00,0x00,0x00,0x00,0x14,0x40,0xff,0x37,0x24,0x02,0x00,0x04,0x08,0x00,0x14,0xa6,
13880x00,0x00,0x00,0x00,0x84,0xc2,0x00,0x20,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x66,
13890x24,0x02,0x00,0x06,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,
13900x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,
13910x14,0x40,0xff,0x24,0xa4,0xc3,0x00,0x20,0x08,0x00,0x14,0xa6,0x24,0x02,0x00,0x06,
13920x8c,0xc2,0x00,0x1c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x57,0x24,0x02,0x00,0x05,
13930x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
13940x30,0x42,0x00,0xff,0x10,0x40,0xff,0x14,0xac,0xc2,0x00,0x1c,0x08,0x00,0x14,0xa6,
13950x24,0x02,0x00,0x05,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
13960x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x47,0x24,0x02,0x00,0x06,
13970x08,0x00,0x14,0x5c,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0a,0x03,0xe0,0x00,0x08,
13980xac,0x82,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb0,0x00,0x10,0x27,0x90,0x86,0x48,
13990xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0x0c,0x00,0x2b,0xe8,
14000xaf,0xb1,0x00,0x14,0xaf,0x90,0x8f,0xd0,0x48,0x02,0x00,0x00,0x0c,0x00,0x13,0xec,
14010x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x4e,0x02,0x00,0x20,0x21,0x0c,0x00,0x00,0x34,
14020x00,0x00,0x00,0x00,0x0c,0x00,0x13,0xf7,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x68,
14030x0c,0x00,0x27,0xc1,0x00,0x00,0x00,0x00,0x93,0x84,0x80,0x10,0x0c,0x00,0x21,0x9a,
14040x00,0x00,0x00,0x00,0x27,0x84,0x89,0x08,0x0c,0x00,0x06,0xe1,0x00,0x00,0x00,0x00,
14050x0c,0x00,0x01,0x3b,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x10,0x0c,0x00,0x13,0xd5,
14060x00,0x00,0x00,0x00,0x27,0x82,0x89,0x3c,0xaf,0x82,0x84,0x50,0x0c,0x00,0x00,0x61,
14070x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x08,0x3c,0x04,0xb0,0x09,
14080x3c,0x05,0xb0,0x09,0x8c,0x66,0x00,0x00,0x34,0x84,0x01,0x68,0x24,0x02,0xc8,0x80,
14090x34,0xa5,0x01,0x40,0x24,0x03,0x00,0x0a,0xa4,0x82,0x00,0x00,0xa4,0xa3,0x00,0x00,
14100x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00,0x8f,0x87,0x84,0x10,0xaf,0x86,0x84,0x08,
14110x34,0x42,0x00,0x20,0xac,0x82,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x58,
14120x8c,0x43,0x00,0x00,0x2c,0xe4,0x00,0x11,0x34,0x63,0x01,0x00,0xac,0x43,0x00,0x00,
14130x10,0x80,0xff,0xfa,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x00,0x07,0x10,0x80,
14140x24,0x63,0x02,0x18,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
14150x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x68,0x0c,0x00,0x26,0xe5,
14160x00,0x00,0x00,0x00,0x27,0x84,0x84,0x10,0x27,0x85,0x86,0x48,0x0c,0x00,0x14,0x4e,
14170x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x07,0x3c,0x03,0xb0,0x06,
14180x90,0x44,0x00,0x00,0x34,0x63,0x80,0x18,0x8c,0x65,0x00,0x00,0x3c,0x02,0xb0,0x03,
14190x34,0x42,0x00,0xec,0x3c,0x03,0xb0,0x03,0x30,0x86,0x00,0xff,0xa0,0x46,0x00,0x00,
14200x00,0x05,0x2f,0x02,0x34,0x63,0x00,0xed,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x2c,
14210xa0,0x65,0x00,0x00,0xa3,0x80,0x81,0x58,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01,
14220x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x87,0x84,0x10,0x8f,0x82,0x84,0x44,
14230x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x44,0x08,0x00,0x15,0x9b,
14240x3c,0x02,0xb0,0x03,0x8f,0x87,0x84,0x10,0x00,0x00,0x00,0x00,0x24,0xe2,0xff,0xfc,
14250x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,0x3c,0x03,0xb0,0x06,0x93,0x82,0x86,0x3c,
14260x00,0x00,0x00,0x00,0x14,0x40,0x00,0x07,0x34,0x63,0x80,0x18,0x27,0x84,0x84,0x68,
14270x0c,0x00,0x27,0x75,0x00,0x00,0x00,0x00,0x8f,0x87,0x84,0x10,0x3c,0x03,0xb0,0x06,
14280x34,0x63,0x80,0x18,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x02,
14290x10,0x40,0xff,0xe6,0x00,0x00,0x00,0x00,0x8f,0x82,0xbc,0x10,0x8f,0x84,0xbc,0x18,
14300x3c,0x05,0xb0,0x01,0x00,0x45,0x10,0x21,0xac,0x44,0x00,0x00,0x8f,0x83,0xbc,0x10,
14310x8f,0x82,0xbc,0x14,0x00,0x65,0x18,0x21,0x08,0x00,0x15,0xc7,0xac,0x62,0x00,0x04,
14320x14,0xa0,0xff,0xd4,0x3c,0x02,0xb0,0x03,0x93,0x83,0x81,0x58,0x34,0x42,0x00,0xee,
14330x24,0x63,0x00,0x01,0x30,0x64,0x00,0xff,0x2c,0x84,0x00,0xf1,0xa0,0x43,0x00,0x00,
14340xa3,0x83,0x81,0x58,0x14,0x80,0xff,0xcc,0x00,0x00,0x00,0x00,0xaf,0x86,0x84,0x24,
14350xa3,0x86,0x86,0x23,0x08,0x00,0x15,0xc1,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x68,
14360x0c,0x00,0x29,0x6e,0x00,0x00,0x00,0x00,0xa3,0x82,0x84,0x41,0x8f,0x82,0x84,0x44,
14370xaf,0x80,0x84,0x10,0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x44,0x08,0x00,0x15,0x9a,
14380x00,0x00,0x38,0x21,0x27,0x84,0x86,0x48,0x0c,0x00,0x19,0x19,0x00,0x00,0x00,0x00,
14390x30,0x42,0x00,0xff,0x14,0x40,0x00,0x05,0x3c,0x03,0xb0,0x05,0xaf,0x80,0x84,0x10,
14400xaf,0x80,0x84,0x14,0x08,0x00,0x15,0xc6,0x00,0x00,0x00,0x00,0x34,0x63,0x04,0x50,
14410x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x3c,
14420x14,0x40,0x00,0x20,0x24,0x02,0x00,0x01,0x8f,0x84,0x84,0x18,0x00,0x00,0x00,0x00,
14430x10,0x82,0x00,0x20,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,
14440x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x24,0x14,0x40,0x00,0x15,
14450x24,0x02,0x00,0x01,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x07,0x00,0x00,0x00,0x00,
14460x24,0x07,0x00,0x03,0x24,0x02,0x00,0x01,0xaf,0x82,0x84,0x14,0xaf,0x87,0x84,0x10,
14470x08,0x00,0x15,0xc6,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,
14480x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,
14490x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x30,0x14,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,
14500x24,0x02,0x00,0x01,0xaf,0x82,0x84,0x14,0xaf,0x80,0x84,0x10,0x08,0x00,0x15,0xc6,
14510x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,
14520x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x2c,0x14,0x40,0xff,0xf5,
14530x24,0x02,0x00,0x01,0x08,0x00,0x16,0x1a,0x3c,0x03,0xb0,0x09,0x27,0x84,0x86,0x48,
14540x0c,0x00,0x1a,0xde,0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x40,0x00,0x00,0x00,0x00,
14550x14,0x40,0xff,0xec,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,
14560x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x3c,
14570x14,0x40,0xff,0xe4,0x24,0x02,0x00,0x02,0x8f,0x84,0x84,0x18,0x24,0x02,0x00,0x01,
14580x10,0x82,0x00,0x12,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x04,0x00,0x00,0x00,0x00,
14590x24,0x07,0x00,0x04,0x08,0x00,0x16,0x26,0x24,0x02,0x00,0x02,0x3c,0x02,0xb0,0x05,
14600x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,
14610x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x30,0x14,0x40,0xff,0xf4,
14620x00,0x00,0x00,0x00,0x08,0x00,0x16,0x35,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,
14630x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,
14640xaf,0x82,0x84,0x2c,0x14,0x40,0xff,0xf7,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0x56,
14650x24,0x02,0x00,0x02,0x27,0x84,0x89,0x08,0x0c,0x00,0x0b,0x51,0x00,0x00,0x00,0x00,
14660x8f,0x83,0x84,0x14,0xaf,0x82,0x84,0x2c,0x38,0x64,0x00,0x02,0x00,0x04,0x18,0x0a,
14670xaf,0x83,0x84,0x14,0x14,0x40,0xff,0xad,0x24,0x07,0x00,0x05,0x8f,0x82,0x89,0x48,
14680xaf,0x80,0x84,0x10,0x10,0x40,0x00,0x02,0x24,0x04,0x00,0x01,0xaf,0x84,0x84,0x18,
14690x93,0x82,0x89,0x56,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x43,0x00,0x00,0x00,0x00,
14700x3c,0x02,0xb0,0x05,0x34,0x42,0x00,0x08,0x8c,0x43,0x00,0x00,0x3c,0x04,0x20,0x00,
14710x00,0x64,0x18,0x24,0x10,0x60,0xff,0x3c,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
14720x34,0x42,0x00,0xa0,0x8c,0x43,0x00,0x00,0x3c,0x04,0x80,0x00,0xaf,0x80,0x89,0x30,
14730x24,0x63,0x00,0x01,0xac,0x43,0x00,0x00,0x3c,0x01,0xb0,0x05,0xac,0x24,0x00,0x08,
14740xaf,0x80,0x89,0x2c,0xaf,0x80,0x89,0x34,0xaf,0x80,0x89,0x38,0xaf,0x80,0x89,0x44,
14750xaf,0x80,0x89,0x3c,0x08,0x00,0x15,0xc6,0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x60,
14760x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x20,0xaf,0x82,0x84,0x2c,
14770x8f,0x85,0x84,0x2c,0x27,0x84,0x89,0x08,0x0c,0x00,0x0d,0x2c,0x00,0x00,0x00,0x00,
14780x00,0x02,0x1e,0x00,0xa3,0x82,0x84,0x40,0xaf,0x80,0x84,0x2c,0x10,0x60,0xff,0x8e,
14790x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,
14800x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,
14810xa7,0x83,0x84,0x30,0x10,0x40,0x00,0x04,0x24,0x04,0x00,0x02,0xaf,0x84,0x84,0x18,
14820x08,0x00,0x16,0x36,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0x27,0x24,0x07,0x00,0x06,
14830x27,0x84,0x84,0x10,0x27,0x85,0x89,0x08,0x0c,0x00,0x0d,0xf9,0x00,0x00,0x00,0x00,
14840x8f,0x82,0x84,0x34,0xaf,0x80,0x84,0x3c,0x14,0x40,0x00,0x19,0x00,0x40,0x18,0x21,
14850x8f,0x82,0x84,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x15,0x24,0x02,0x00,0x02,
14860x8f,0x83,0x84,0x18,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x0b,0x3c,0x02,0x40,0x00,
14870x8f,0x83,0x84,0x14,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x02,0x24,0x07,0x00,0x03,
14880x24,0x07,0x00,0x06,0xaf,0x87,0x84,0x10,0x24,0x04,0x00,0x03,0xaf,0x84,0x84,0x18,
14890x08,0x00,0x15,0xc6,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x14,0x3c,0x01,0xb0,0x05,
14900xac,0x22,0x00,0x00,0xaf,0x80,0x84,0x10,0x08,0x00,0x16,0xcf,0x24,0x04,0x00,0x03,
14910x10,0x60,0x00,0x10,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x10,0x27,0x85,0x89,0x08,
14920x0c,0x00,0x0e,0x1d,0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x14,0x24,0x02,0x00,0x01,
14930xa3,0x80,0x84,0x40,0xaf,0x80,0x84,0x18,0x10,0x62,0x00,0x02,0x24,0x07,0x00,0x03,
14940x24,0x07,0x00,0x04,0xaf,0x87,0x84,0x10,0xaf,0x80,0x84,0x34,0x08,0x00,0x15,0xc6,
14950x00,0x00,0x00,0x00,0x83,0x82,0x84,0x60,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x04,
14960x00,0x00,0x00,0x00,0x27,0x84,0x89,0x08,0x0c,0x00,0x10,0x65,0x00,0x00,0x00,0x00,
14970x8f,0x82,0x84,0x14,0xa3,0x80,0x84,0x40,0xaf,0x80,0x84,0x10,0xaf,0x80,0x84,0x18,
14980x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x14,
14990xaf,0x80,0x84,0x38,0x08,0x00,0x15,0xc6,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x10,
15000x27,0x85,0x89,0x08,0x0c,0x00,0x0e,0x1d,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x14,
15010xa3,0x80,0x84,0x40,0xaf,0x80,0x84,0x10,0xaf,0x80,0x84,0x18,0x14,0x40,0xfe,0xc2,
15020x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x14,0x08,0x00,0x15,0xc6,
15030x00,0x00,0x00,0x00,0x27,0x84,0x89,0x08,0x0c,0x00,0x10,0x65,0x00,0x00,0x00,0x00,
15040x08,0x00,0x16,0xff,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x68,0x0c,0x00,0x2a,0x96,
15050x00,0x00,0x00,0x00,0x08,0x00,0x15,0xfe,0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0x66,
15060x00,0x00,0x00,0x00,0x0c,0x00,0x27,0x56,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x40,
15070x00,0x00,0x00,0x00,0x27,0x84,0x84,0x68,0x0c,0x00,0x27,0x64,0x00,0x00,0x00,0x00,
15080x93,0x83,0xbc,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x2b,0x3c,0x02,0xb0,0x03,
15090x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x83,0xbc,0x00,0x8f,0x82,0xbc,0x04,
15100x00,0x83,0x18,0x23,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x23,0x3c,0x02,0xb0,0x03,
15110x24,0x04,0x05,0xa0,0x34,0x42,0x01,0x18,0x8c,0x42,0x00,0x00,0x0c,0x00,0x06,0xce,
15120x00,0x00,0x00,0x00,0x24,0x04,0x05,0xa4,0x0c,0x00,0x06,0xce,0x00,0x02,0x84,0x02,
15130x30,0x51,0xff,0xff,0x24,0x04,0x05,0xa8,0x00,0x02,0x94,0x02,0x0c,0x00,0x06,0xce,
15140x3a,0x10,0xff,0xff,0x3a,0x31,0xff,0xff,0x30,0x42,0xff,0xff,0x2e,0x10,0x00,0x01,
15150x2e,0x31,0x00,0x01,0x3a,0x52,0xff,0xff,0x02,0x11,0x80,0x25,0x2e,0x52,0x00,0x01,
15160x38,0x42,0xff,0xff,0x02,0x12,0x80,0x25,0x2c,0x42,0x00,0x01,0x02,0x02,0x80,0x25,
15170x16,0x00,0x00,0x02,0x24,0x04,0x00,0x02,0x00,0x00,0x20,0x21,0x0c,0x00,0x05,0x70,
15180x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x43,0x00,0x00,
15190x00,0x00,0x00,0x00,0xaf,0x83,0xbc,0x00,0x0c,0x00,0x01,0xeb,0x00,0x00,0x00,0x00,
15200xaf,0x80,0x84,0x10,0xaf,0x80,0x84,0x44,0x08,0x00,0x15,0x9a,0x00,0x00,0x38,0x21,
15210x27,0x90,0xb3,0xf0,0x24,0x11,0x00,0x12,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,
15220x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
15230x0c,0x00,0x20,0xd0,0x00,0x00,0x00,0x00,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xf6,
15240x26,0x10,0x00,0x04,0xaf,0x80,0x84,0x10,0x08,0x00,0x15,0xc7,0x00,0x00,0x38,0x21,
15250x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x82,0x84,0x08,
15260x00,0x04,0x19,0xc2,0x00,0x02,0x11,0xc2,0x10,0x62,0xff,0xf6,0x00,0x00,0x00,0x00,
15270x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x02,0x90,0x43,0x00,0x00,0x3c,0x12,0xb0,0x05,
15280xaf,0x84,0x84,0x08,0x30,0x63,0x00,0xff,0x00,0x03,0x11,0x40,0x00,0x43,0x10,0x23,
15290x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x99,0x00,0x00,0x00,0x88,0x21,
15300x36,0x52,0x02,0x2c,0x27,0x90,0xb3,0xf0,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,
15310x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x03,0x10,0x40,0x00,0x06,
15320x30,0x62,0x00,0x1c,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0x08,
15330x0c,0x00,0x1e,0xb2,0x02,0x60,0x30,0x21,0x8e,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
15340x30,0x42,0x00,0xff,0x14,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,0x26,0x31,0x00,0x01,
15350x2a,0x22,0x00,0x13,0x14,0x40,0xff,0xec,0x26,0x10,0x00,0x04,0x08,0x00,0x17,0x5d,
15360x00,0x00,0x00,0x00,0x8f,0x84,0x84,0x1c,0x27,0x85,0x89,0x08,0x0c,0x00,0x17,0xd3,
15370x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x1c,0x24,0x02,0x00,0x04,0x14,0x62,0xfe,0xa2,
15380x00,0x00,0x00,0x00,0x08,0x00,0x16,0x27,0x24,0x07,0x00,0x05,0x27,0x84,0x89,0x08,
15390x0c,0x00,0x24,0x8d,0x00,0x00,0x00,0x00,0x24,0x07,0x00,0x05,0xaf,0x87,0x84,0x10,
15400x08,0x00,0x15,0xc7,0x00,0x00,0x00,0x00,0x8f,0x82,0x89,0x3c,0x00,0x00,0x00,0x00,
15410x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x30,0xaf,0x80,0x89,0x3c,
15420x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x84,0x00,0x00,0x00,0x00,0x93,0x82,0x8b,0x61,
15430x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
15440x0c,0x00,0x01,0x59,0x00,0x00,0x20,0x21,0x8f,0x84,0xb4,0x30,0x0c,0x00,0x20,0xd0,
15450x00,0x00,0x00,0x00,0x08,0x00,0x17,0x5d,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x90,
15460x27,0xbd,0xff,0xe8,0x00,0x80,0x18,0x21,0x34,0x42,0x00,0x01,0x27,0x84,0x89,0x08,
15470x10,0x62,0x00,0x05,0xaf,0xbf,0x00,0x10,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,
15480x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x06,0xe1,0x00,0x00,0x00,0x00,
15490x27,0x84,0x86,0x48,0x0c,0x00,0x18,0x4e,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x10,
15500x0c,0x00,0x13,0xd5,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0xba,0x00,0x00,0x00,0x00,
15510x8f,0x82,0x89,0x48,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x18,0x21,
15520x8f,0x82,0x84,0x18,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,
15530x24,0x03,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x27,0xbd,0xff,0xe0,
15540x3c,0x06,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x34,0xc6,0x00,0x5f,
15550xaf,0xbf,0x00,0x18,0x90,0xc3,0x00,0x00,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x5d,
15560x34,0x63,0x00,0x01,0x3c,0x09,0xb0,0x03,0x24,0x02,0x00,0x01,0xa0,0xc3,0x00,0x00,
15570x00,0x80,0x80,0x21,0xa0,0xe2,0x00,0x00,0x00,0xa0,0x88,0x21,0x35,0x29,0x00,0x5e,
15580x00,0xe0,0x40,0x21,0x24,0x04,0x00,0x01,0x91,0x22,0x00,0x00,0x91,0x03,0x00,0x00,
15590x30,0x42,0x00,0x01,0x14,0x83,0x00,0x03,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfa,
15600x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x2c,0x24,0x05,0x0f,0x00,
15610x24,0x02,0x00,0x06,0x12,0x02,0x00,0x08,0x24,0x05,0x00,0x0f,0x3c,0x02,0xb0,0x03,
15620x34,0x42,0x02,0x00,0xa0,0x50,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,
15630x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x04,0x0c,0x04,0x0c,0x00,0x13,0x5b,
15640x24,0x06,0x00,0x0f,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f,0x0c,0x00,0x13,0x5b,
15650x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00,0x0c,0x00,0x13,0x5b,
15660x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x8c,0x24,0x05,0x0f,0x00,0x0c,0x00,0x13,0x5b,
15670x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5b,
15680x24,0x06,0x00,0x02,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5b,
15690x24,0x06,0x00,0x02,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5b,
15700x24,0x06,0x00,0x02,0x24,0x04,0x08,0x3c,0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5b,
15710x24,0x06,0x00,0x02,0x08,0x00,0x17,0xf4,0x3c,0x02,0xb0,0x03,0x24,0x04,0x08,0x8c,
15720x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00,
15730x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x04,0x24,0x04,0x0c,0x04,0x24,0x05,0x00,0x0f,
15740x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x04,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f,
15750x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30,
15760x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30,
15770x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30,
15780x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x02,0x3c,0x05,0x00,0x30,0x24,0x06,0x00,0x03,
15790x0c,0x00,0x13,0x5b,0x24,0x04,0x08,0x3c,0x02,0x20,0x20,0x21,0x24,0x05,0x00,0x14,
15800x0c,0x00,0x13,0xa0,0x24,0x06,0x01,0x07,0x08,0x00,0x17,0xf4,0x3c,0x02,0xb0,0x03,
15810x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
15820x30,0x42,0x00,0x02,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0xa3,0x80,0x81,0x59,
15830x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0xa3,0x82,0x81,0x59,
15840x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
15850x00,0x80,0x70,0x21,0x34,0x63,0x00,0x20,0x24,0x42,0x61,0x38,0x3c,0x04,0xb0,0x03,
15860xac,0x62,0x00,0x00,0x34,0x84,0x00,0x30,0xad,0xc0,0x02,0xbc,0xad,0xc0,0x02,0xb8,
15870x8c,0x83,0x00,0x00,0x24,0x02,0x00,0xff,0xa5,0xc0,0x00,0x0a,0x00,0x00,0x30,0x21,
15880xa7,0x82,0x8f,0xe0,0x27,0x88,0x8f,0xf0,0xa5,0xc3,0x00,0x08,0x3c,0x07,0xb0,0x08,
15890x30,0xc2,0xff,0xff,0x00,0x02,0x20,0xc0,0x24,0xc3,0x00,0x01,0x00,0x82,0x10,0x21,
15900x00,0x60,0x30,0x21,0x00,0x02,0x10,0x80,0x30,0x63,0xff,0xff,0x00,0x48,0x10,0x21,
15910x00,0x87,0x20,0x21,0x28,0xc5,0x00,0xff,0xac,0x83,0x00,0x00,0x14,0xa0,0xff,0xf4,
15920xa4,0x43,0x00,0x00,0x3c,0x02,0xb0,0x08,0x34,0x03,0xff,0xff,0x25,0xc4,0x00,0x0c,
15930x24,0x0a,0x00,0x02,0x34,0x42,0x07,0xf8,0x3c,0x06,0xb0,0x03,0xa7,0x83,0xb3,0xcc,
15940xac,0x43,0x00,0x00,0xaf,0x84,0xb3,0xf0,0x34,0xc6,0x00,0x64,0xa0,0x8a,0x00,0x18,
15950x94,0xc5,0x00,0x00,0x8f,0x82,0xb3,0xf0,0x25,0xc4,0x00,0x30,0x24,0x08,0x00,0x03,
15960x3c,0x03,0xb0,0x03,0xa0,0x45,0x00,0x21,0x34,0x63,0x00,0x66,0xaf,0x84,0xb3,0xf4,
15970xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb3,0xf4,0x25,0xc4,0x00,0x54,
15980x25,0xc7,0x00,0x78,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb3,0xf8,0xa0,0x88,0x00,0x18,
15990x94,0x65,0x00,0x00,0x8f,0x82,0xb3,0xf8,0x25,0xc8,0x00,0x9c,0x24,0x09,0x00,0x01,
16000xa0,0x45,0x00,0x21,0xaf,0x87,0xb3,0xfc,0xa0,0xea,0x00,0x18,0x94,0xc4,0x00,0x00,
16010x8f,0x82,0xb3,0xfc,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x62,0xa0,0x44,0x00,0x21,
16020xaf,0x88,0xb4,0x00,0xa1,0x09,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x00,
16030x25,0xc4,0x00,0xc0,0x3c,0x06,0xb0,0x03,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x04,
16040xa0,0x89,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x04,0x25,0xc4,0x00,0xe4,
16050x34,0xc6,0x00,0x60,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x08,0xa0,0x80,0x00,0x18,
16060x94,0xc5,0x00,0x00,0x8f,0x82,0xb4,0x08,0x25,0xc3,0x01,0x08,0x25,0xc7,0x01,0x2c,
16070xa0,0x45,0x00,0x21,0xaf,0x83,0xb4,0x0c,0xa0,0x60,0x00,0x18,0x94,0xc8,0x00,0x00,
16080x8f,0x82,0xb4,0x0c,0x25,0xc4,0x01,0x50,0x25,0xc5,0x01,0x74,0xa0,0x48,0x00,0x21,
16090x25,0xc6,0x01,0x98,0x25,0xc9,0x01,0xbc,0x25,0xca,0x01,0xe0,0x25,0xcb,0x02,0x04,
16100x25,0xcc,0x02,0x28,0x25,0xcd,0x02,0x4c,0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03,
16110xaf,0x87,0xb4,0x10,0x34,0x63,0x00,0x38,0xa0,0xe0,0x00,0x18,0xaf,0x84,0xb4,0x14,
16120xa0,0x80,0x00,0x18,0xaf,0x85,0xb4,0x18,0xa0,0xa0,0x00,0x18,0xaf,0x86,0xb4,0x1c,
16130xa0,0xc0,0x00,0x18,0xaf,0x89,0xb4,0x20,0xa1,0x20,0x00,0x18,0xaf,0x8a,0xb4,0x24,
16140xa1,0x40,0x00,0x18,0xaf,0x8b,0xb4,0x28,0xa1,0x60,0x00,0x18,0xaf,0x8c,0xb4,0x2c,
16150xa1,0x80,0x00,0x18,0xaf,0x8d,0xb4,0x30,0xa1,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,
16160x8f,0x82,0xb4,0x30,0x25,0xc5,0x02,0x70,0x3c,0x03,0xb0,0x03,0xa0,0x44,0x00,0x21,
16170x24,0x02,0x00,0x11,0xaf,0x85,0xb4,0x34,0x34,0x63,0x00,0x6e,0xa0,0xa2,0x00,0x18,
16180x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x34,0x25,0xc5,0x02,0x94,0x3c,0x03,0xb0,0x03,
16190xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x12,0xaf,0x85,0xb4,0x38,0x34,0x63,0x00,0x6c,
16200xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x38,0x24,0x05,0xff,0xff,
16210x24,0x07,0x00,0x01,0xa0,0x44,0x00,0x21,0x24,0x06,0x00,0x12,0x27,0x84,0xb3,0xf0,
16220x8c,0x82,0x00,0x00,0x24,0xc6,0xff,0xff,0xa0,0x40,0x00,0x04,0x8c,0x83,0x00,0x00,
16230xa4,0x45,0x00,0x00,0xa4,0x45,0x00,0x02,0xa0,0x60,0x00,0x0a,0x8c,0x82,0x00,0x00,
16240xa4,0x65,0x00,0x06,0xa4,0x65,0x00,0x08,0xa0,0x40,0x00,0x10,0x8c,0x83,0x00,0x00,
16250xa4,0x45,0x00,0x0c,0xa4,0x45,0x00,0x0e,0xa0,0x60,0x00,0x12,0x8c,0x82,0x00,0x00,
16260x00,0x00,0x00,0x00,0xa0,0x40,0x00,0x16,0x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x14,
16270xa0,0x67,0x00,0x17,0x8c,0x82,0x00,0x00,0x24,0x84,0x00,0x04,0xa0,0x40,0x00,0x20,
16280x04,0xc1,0xff,0xe7,0xac,0x40,0x00,0x1c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
16290x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x64,0x00,
16300x00,0x05,0x28,0x40,0xac,0x62,0x00,0x00,0x00,0xa6,0x28,0x21,0x2c,0xe2,0x00,0x10,
16310x14,0x80,0x00,0x06,0x00,0x00,0x18,0x21,0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,
16320x00,0xe0,0x18,0x21,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x24,0x02,0x00,0x20,
16330x10,0xe2,0x00,0x06,0x2c,0xe4,0x00,0x10,0x24,0xa2,0x00,0x01,0x10,0x80,0xff,0xf9,
16340x00,0x02,0x11,0x00,0x08,0x00,0x19,0x0d,0x00,0x47,0x18,0x21,0x08,0x00,0x19,0x0d,
16350x24,0xa3,0x00,0x50,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,
16360x34,0x63,0x00,0x20,0x24,0x42,0x64,0x64,0xaf,0xb2,0x00,0x18,0xaf,0xbf,0x00,0x34,
16370xaf,0xbe,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,
16380xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
16390xac,0x62,0x00,0x00,0x8c,0x86,0x02,0xbc,0x00,0x80,0x90,0x21,0x14,0xc0,0x01,0x66,
16400x00,0xc0,0x38,0x21,0x84,0x82,0x00,0x08,0x3c,0x03,0xb0,0x06,0x94,0x84,0x00,0x08,
16410x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x45,0x00,0x00,0x8c,0x43,0x00,0x00,
16420x24,0x84,0x00,0x02,0x30,0x84,0x01,0xff,0x30,0xb1,0xff,0xff,0x00,0x03,0x44,0x02,
16430xa6,0x44,0x00,0x08,0x14,0xe0,0x00,0x08,0x3c,0x03,0xb0,0x06,0x34,0x63,0x80,0x24,
16440x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x42,0x01,0x00,0xac,0x62,0x00,0x00,
16450x8e,0x46,0x02,0xbc,0x00,0x00,0x00,0x00,0x14,0xc0,0x01,0x4c,0x00,0x11,0x98,0xc0,
16460x00,0x11,0x3a,0x00,0x3c,0x04,0xb0,0x00,0x00,0xe4,0x20,0x21,0x8c,0x83,0x00,0x0c,
16470x00,0x11,0x98,0xc0,0x02,0x71,0x10,0x21,0x00,0x03,0x1b,0x82,0x30,0x63,0x00,0x1f,
16480x00,0x02,0x10,0x80,0x27,0x9e,0x8f,0xf4,0x00,0x5e,0x10,0x21,0x00,0x60,0x30,0x21,
16490xac,0x44,0x00,0x18,0xae,0x43,0x02,0xbc,0x14,0xc0,0x00,0x10,0x3c,0x02,0xb0,0x00,
16500x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x27,0x84,0x8f,0xf0,0x00,0x02,0x10,0x80,
16510x00,0x44,0x10,0x21,0x94,0x45,0x00,0x00,0x02,0x71,0x18,0x21,0x00,0x03,0x18,0x80,
16520x00,0x64,0x18,0x21,0x24,0x02,0xff,0xff,0xa4,0x62,0x00,0x02,0xa4,0x68,0x00,0x04,
16530xae,0x51,0x02,0xb8,0xa6,0x45,0x00,0x0a,0x3c,0x02,0xb0,0x00,0x00,0xe2,0x40,0x21,
16540x8d,0x16,0x00,0x00,0x8d,0x14,0x00,0x04,0x02,0x71,0x10,0x21,0x00,0x02,0x38,0x80,
16550x00,0x14,0x1a,0x02,0x27,0x84,0x90,0x00,0x30,0x63,0x00,0x1f,0x24,0x02,0x00,0x10,
16560x00,0xe4,0x20,0x21,0xa6,0x43,0x00,0x06,0x8d,0x10,0x00,0x08,0xa0,0x82,0x00,0x06,
16570x86,0x45,0x00,0x06,0x00,0xfe,0x10,0x21,0x24,0x03,0x00,0x13,0x10,0xa3,0x01,0x15,
16580xac,0x48,0x00,0x18,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,0xa6,0x40,0x00,0x02,
16590x3c,0x02,0xb0,0x03,0x90,0x64,0x00,0x00,0x34,0x42,0x01,0x08,0x8c,0x45,0x00,0x00,
16600x00,0x10,0x1b,0xc2,0x27,0x82,0x8f,0xf0,0x00,0x04,0x20,0x82,0x00,0xe2,0x10,0x21,
16610x30,0x63,0x00,0x01,0xac,0x45,0x00,0x08,0x10,0x60,0x00,0xec,0x30,0x97,0x00,0x01,
16620x00,0x10,0x16,0x82,0x30,0x46,0x00,0x01,0x00,0x10,0x12,0x02,0x00,0x10,0x19,0xc2,
16630x00,0x10,0x26,0x02,0x00,0x10,0x2e,0x42,0x30,0x47,0x00,0x7f,0x24,0x02,0x00,0x01,
16640x30,0x75,0x00,0x01,0x30,0x84,0x00,0x01,0x10,0xc2,0x00,0xd9,0x30,0xa3,0x00,0x01,
16650x0c,0x00,0x19,0x00,0x00,0x60,0x28,0x21,0x02,0x71,0x18,0x21,0x00,0x03,0x18,0x80,
16660x2c,0x46,0x00,0x54,0x27,0x85,0x90,0x00,0x27,0x84,0x8f,0xf8,0x00,0x06,0x10,0x0a,
16670x00,0x65,0x28,0x21,0x26,0xa6,0x00,0x02,0x00,0x64,0x18,0x21,0xa0,0xa2,0x00,0x02,
16680xa0,0x66,0x00,0x06,0xa0,0x62,0x00,0x07,0xa0,0xa2,0x00,0x01,0x02,0x71,0x20,0x21,
16690x00,0x04,0x20,0x80,0x00,0x9e,0x60,0x21,0x8d,0x85,0x00,0x18,0x00,0x10,0x15,0xc2,
16700x30,0x42,0x00,0x01,0x8c,0xa3,0x00,0x0c,0xa6,0x42,0x00,0x00,0x27,0x82,0x90,0x10,
16710x00,0x82,0x50,0x21,0xa6,0x56,0x00,0x04,0x8d,0x45,0x00,0x00,0x00,0x03,0x19,0x42,
16720x3c,0x02,0xff,0xef,0x34,0x42,0xff,0xff,0x30,0x63,0x00,0x01,0x00,0xa2,0x48,0x24,
16730x00,0x03,0x1d,0x00,0x01,0x23,0x48,0x25,0x00,0x09,0x15,0x02,0x26,0xc5,0x00,0x10,
16740x00,0x14,0x19,0x82,0x00,0x14,0x25,0x82,0x00,0x10,0x34,0x02,0x00,0x10,0x3c,0x42,
16750x00,0x10,0x44,0x82,0x30,0x42,0x00,0x01,0x30,0xb5,0xff,0xff,0x30,0xce,0x00,0x01,
16760x30,0xe5,0x00,0x01,0x30,0x6d,0x00,0x01,0x30,0x8b,0x00,0x03,0x32,0x94,0x00,0x07,
16770x31,0x06,0x00,0x01,0xad,0x49,0x00,0x00,0x10,0x40,0x00,0x0b,0x32,0x07,0x00,0x7f,
16780x8d,0x84,0x00,0x18,0x3c,0x03,0xff,0xf0,0x34,0x63,0xff,0xff,0x8c,0x82,0x00,0x0c,
16790x01,0x23,0x18,0x24,0x00,0x02,0x13,0x82,0x30,0x42,0x00,0x0f,0x00,0x02,0x14,0x00,
16800x00,0x62,0x18,0x25,0xad,0x43,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x90,
16810x00,0x00,0x00,0x00,0x15,0xa0,0x00,0x03,0x00,0x00,0x00,0x00,0x15,0x60,0x00,0x81,
16820x24,0x02,0x00,0x01,0x96,0x42,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x04,
16830xa6,0x42,0x00,0x04,0x0c,0x00,0x19,0x00,0x01,0xc0,0x20,0x21,0x02,0x71,0x18,0x21,
16840x00,0x03,0x38,0x80,0x2c,0x45,0x00,0x54,0x27,0x84,0x90,0x00,0x00,0xe4,0x20,0x21,
16850x00,0x05,0x10,0x0a,0xa0,0x82,0x00,0x00,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
16860x96,0x45,0x00,0x04,0x27,0x82,0x8f,0xf0,0x00,0xe2,0x10,0x21,0xa4,0x45,0x00,0x06,
16870x00,0xfe,0x18,0x21,0x92,0x45,0x00,0x01,0x8c,0x66,0x00,0x18,0x27,0x82,0x90,0x10,
16880x00,0xe2,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x85,0x00,0x07,0x94,0xc3,0x00,0x10,
16890x24,0x02,0x00,0x04,0x30,0x63,0x00,0x0f,0x10,0x62,0x00,0x5e,0x24,0xc6,0x00,0x10,
16900x94,0xc3,0x00,0x16,0x27,0x85,0x90,0x08,0x00,0xe5,0x10,0x21,0xa4,0x43,0x00,0x02,
16910x94,0xc2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x4c,
16920x02,0x71,0x20,0x21,0x94,0xc2,0x00,0x00,0x24,0x03,0x00,0xa4,0x30,0x42,0x00,0xff,
16930x10,0x43,0x00,0x47,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x00,0x24,0x03,0x00,0x88,
16940x30,0x42,0x00,0x88,0x10,0x43,0x00,0x3c,0x02,0x71,0x18,0x21,0x27,0x84,0x90,0x10,
16950x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00,0x3c,0x04,0x00,0x80,
16960x00,0x44,0x10,0x25,0xac,0x62,0x00,0x00,0x02,0x71,0x10,0x21,0x00,0x02,0x10,0x80,
16970x00,0x45,0x10,0x21,0xa0,0x54,0x00,0x00,0x92,0x43,0x02,0xbf,0x3c,0x02,0xb0,0x03,
16980x34,0x42,0x00,0xc3,0xa0,0x43,0x00,0x00,0x8e,0x4b,0x02,0xbc,0x00,0x00,0x00,0x00,
16990x11,0x60,0x00,0x1c,0x32,0xa2,0x00,0xff,0x00,0x15,0x1a,0x02,0x30,0x64,0xff,0xff,
17000x38,0x42,0x00,0x00,0x24,0x65,0x00,0x01,0x00,0x82,0x28,0x0a,0x02,0x20,0x30,0x21,
17010x10,0xa0,0x00,0x12,0x00,0x00,0x38,0x21,0x02,0x71,0x10,0x21,0x00,0x02,0x10,0x80,
17020x27,0x83,0x8f,0xf0,0x00,0x43,0x20,0x21,0x24,0xa9,0xff,0xff,0x3c,0x0a,0xb0,0x08,
17030x24,0x0c,0xff,0xff,0x00,0x06,0x10,0xc0,0x00,0x4a,0x10,0x21,0x8c,0x43,0x00,0x00,
17040x24,0xe8,0x00,0x01,0x10,0xe9,0x00,0x0f,0x30,0x63,0x00,0xff,0x31,0x07,0xff,0xff,
17050x00,0xe5,0x10,0x2b,0x14,0x40,0xff,0xf7,0x00,0x60,0x30,0x21,0x25,0x62,0xff,0xff,
17060xae,0x42,0x02,0xbc,0x7b,0xbe,0x01,0xbc,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,
17070x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,
17080x27,0xbd,0x00,0x38,0xa4,0x86,0x00,0x04,0xa4,0x8c,0x00,0x02,0xae,0x51,0x02,0xb8,
17090x08,0x00,0x1a,0x2f,0xa6,0x43,0x00,0x0a,0x94,0xc2,0x00,0x18,0x00,0x00,0x00,0x00,
17100x30,0x42,0x00,0x60,0x10,0x40,0xff,0xc1,0x02,0x71,0x18,0x21,0x02,0x71,0x20,0x21,
17110x27,0x82,0x90,0x10,0x00,0x04,0x20,0x80,0x00,0x82,0x20,0x21,0x8c,0x83,0x00,0x00,
17120x3c,0x02,0xff,0x7f,0x34,0x42,0xff,0xff,0x00,0x62,0x18,0x24,0x08,0x00,0x1a,0x0e,
17130xac,0x83,0x00,0x00,0x27,0x85,0x90,0x08,0x00,0xe5,0x10,0x21,0x08,0x00,0x19,0xf8,
17140xa4,0x40,0x00,0x02,0x11,0x62,0x00,0x07,0x00,0x00,0x00,0x00,0x2d,0x62,0x00,0x02,
17150x14,0x40,0xff,0x80,0x00,0x00,0x00,0x00,0x96,0x42,0x00,0x04,0x08,0x00,0x19,0xd8,
17160x24,0x42,0x00,0x0c,0x96,0x42,0x00,0x04,0x08,0x00,0x19,0xd8,0x24,0x42,0x00,0x08,
17170x16,0xe6,0xff,0x70,0x3c,0x02,0xff,0xfb,0x8d,0x83,0x00,0x18,0x34,0x42,0xff,0xff,
17180x02,0x02,0x10,0x24,0xac,0x62,0x00,0x08,0x08,0x00,0x19,0xd1,0x00,0x00,0x30,0x21,
17190x16,0xe6,0xff,0x27,0x3c,0x02,0xfb,0xff,0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,
17200xad,0x02,0x00,0x08,0x08,0x00,0x19,0x90,0x00,0x00,0x30,0x21,0x93,0x88,0xbb,0x04,
17210x00,0x10,0x1e,0x42,0x00,0x10,0x26,0x82,0x27,0x82,0x8f,0xf8,0x2d,0x05,0x00,0x0c,
17220x00,0xe2,0x48,0x21,0x30,0x63,0x00,0x01,0x30,0x86,0x00,0x01,0x14,0xa0,0x00,0x06,
17230x01,0x00,0x38,0x21,0x00,0x03,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,
17240x01,0x02,0x10,0x21,0x24,0x47,0x00,0x04,0x02,0x71,0x10,0x21,0x00,0x02,0x10,0x80,
17250x27,0x84,0x90,0x00,0x27,0x83,0x8f,0xf8,0x00,0x44,0x20,0x21,0x00,0x43,0x10,0x21,
17260xa1,0x27,0x00,0x07,0xa0,0x40,0x00,0x06,0xa0,0x80,0x00,0x02,0x08,0x00,0x19,0x9f,
17270xa0,0x80,0x00,0x01,0x24,0x02,0x00,0x01,0xa6,0x42,0x00,0x02,0x0c,0x00,0x01,0xc4,
17280x01,0x00,0x20,0x21,0x08,0x00,0x1a,0x35,0x00,0x00,0x00,0x00,0x27,0x9e,0x8f,0xf4,
17290x08,0x00,0x19,0x52,0x00,0x11,0x3a,0x00,0x94,0x91,0x00,0x0a,0x08,0x00,0x19,0x39,
17300x00,0x00,0x00,0x00,0x30,0xa9,0xff,0xff,0x00,0x09,0x18,0xc0,0x00,0x69,0x18,0x21,
17310x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x6a,0x54,0x00,0x03,0x18,0x80,
17320x34,0xc6,0x00,0x20,0x27,0x85,0x90,0x00,0xac,0xc2,0x00,0x00,0x00,0x65,0x18,0x21,
17330x80,0x62,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x32,0x24,0x88,0x00,0x06,
17340x90,0x82,0x00,0x16,0x00,0x80,0x40,0x21,0x34,0x42,0x00,0x02,0x30,0x43,0x00,0x01,
17350x14,0x60,0x00,0x02,0xa0,0x82,0x00,0x16,0xa0,0x80,0x00,0x17,0x95,0x03,0x00,0x02,
17360x00,0x00,0x00,0x00,0x10,0x69,0x00,0x22,0x3c,0x02,0x34,0x34,0x91,0x02,0x00,0x04,
17370x00,0x00,0x00,0x00,0x14,0x40,0x00,0x06,0x00,0x03,0x20,0xc0,0x24,0x02,0x00,0x01,
17380xa1,0x02,0x00,0x04,0xa5,0x09,0x00,0x02,0x03,0xe0,0x00,0x08,0xa5,0x09,0x00,0x00,
17390x00,0x83,0x20,0x21,0x27,0x87,0x8f,0xf0,0x00,0x04,0x20,0x80,0x00,0x87,0x20,0x21,
17400x94,0x83,0x00,0x04,0x3c,0x02,0xb0,0x08,0x3c,0x06,0xb0,0x03,0x00,0x03,0x28,0xc0,
17410x00,0xa3,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x21,0x3c,0x02,0x80,0x01,
17420x24,0x42,0x82,0xe4,0x00,0x67,0x18,0x21,0x34,0xc6,0x00,0x20,0xac,0xc2,0x00,0x00,
17430xa4,0x69,0x00,0x00,0xa4,0x89,0x00,0x02,0xac,0xa9,0x00,0x00,0x91,0x02,0x00,0x04,
17440xa5,0x09,0x00,0x02,0x24,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x04,
17450x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xb0,0x34,0x42,0x34,0x34,0x03,0xe0,0x00,0x08,
17460xac,0x62,0x00,0x00,0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x01,
17470x30,0x43,0x00,0x02,0x14,0x60,0xff,0xd1,0xa0,0x82,0x00,0x16,0x24,0x02,0x00,0x01,
17480x08,0x00,0x1a,0xab,0xa0,0x82,0x00,0x17,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
17490x00,0x80,0x38,0x21,0x84,0x84,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
17500x3c,0x0a,0xb0,0x06,0x34,0x63,0x00,0x20,0x24,0x42,0x6b,0x78,0x3c,0x0b,0xb0,0x08,
17510x27,0x89,0x8f,0xf0,0x34,0x0c,0xff,0xff,0x35,0x4a,0x80,0x20,0x10,0x80,0x00,0x30,
17520xac,0x62,0x00,0x00,0x97,0x82,0x8f,0xe0,0x94,0xe6,0x02,0xba,0x00,0x02,0x18,0xc0,
17530x00,0x6b,0x28,0x21,0xac,0xa6,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x00,0x62,0x18,0x21,
17540x00,0x03,0x18,0x80,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,
17550x00,0x49,0x10,0x21,0x94,0x48,0x00,0x04,0x00,0x69,0x18,0x21,0xa4,0x66,0x00,0x00,
17560x00,0x08,0x28,0xc0,0x00,0xab,0x10,0x21,0xac,0x4c,0x00,0x00,0x8c,0xe4,0x02,0xb8,
17570x27,0x82,0x8f,0xf4,0x00,0xa8,0x28,0x21,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,
17580x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x8c,0x46,0x00,0x18,0x27,0x84,0x90,0x00,
17590x00,0x64,0x18,0x21,0x8c,0xc2,0x00,0x00,0x80,0x67,0x00,0x06,0x00,0x05,0x28,0x80,
17600x30,0x42,0xff,0xff,0x00,0x47,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,
17610x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21,0x3c,0x04,0x00,0x04,0x00,0xa9,0x28,0x21,
17620x00,0x44,0x10,0x25,0xa4,0xac,0x00,0x00,0xad,0x42,0x00,0x00,0xa7,0x88,0x8f,0xe0,
17630x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
17640x84,0xe3,0x00,0x06,0x27,0x82,0xb3,0xf0,0x94,0xe5,0x02,0xba,0x00,0x03,0x18,0x80,
17650x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x0c,0x00,0x1a,0x95,0x00,0x00,0x00,0x00,
17660x08,0x00,0x1b,0x18,0x00,0x00,0x00,0x00,0x94,0x88,0x00,0x00,0x00,0x80,0x58,0x21,
17670x27,0x8a,0x8f,0xf0,0x00,0x08,0x18,0xc0,0x00,0x68,0x18,0x21,0x3c,0x04,0xb0,0x03,
17680x00,0x03,0x18,0x80,0x3c,0x02,0x80,0x00,0x00,0x6a,0x18,0x21,0x34,0x84,0x00,0x20,
17690x24,0x42,0x6c,0x98,0x30,0xa5,0xff,0xff,0xac,0x82,0x00,0x00,0x94,0x67,0x00,0x02,
17700x11,0x05,0x00,0x35,0x24,0x04,0x00,0x01,0x91,0x66,0x00,0x04,0x00,0x00,0x00,0x00,
17710x00,0x86,0x10,0x2a,0x10,0x40,0x00,0x10,0x00,0xc0,0x48,0x21,0x3c,0x0d,0xb0,0x03,
17720x01,0x40,0x60,0x21,0x35,0xad,0x00,0x20,0x10,0xe5,0x00,0x0d,0x24,0x84,0x00,0x01,
17730x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80,0x01,0x20,0x30,0x21,
17740x00,0x4a,0x10,0x21,0x00,0x86,0x18,0x2a,0x00,0xe0,0x40,0x21,0x94,0x47,0x00,0x02,
17750x14,0x60,0xff,0xf5,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,
17760x00,0x08,0x20,0xc0,0x00,0x88,0x20,0x21,0x24,0xc2,0xff,0xff,0x00,0x04,0x20,0x80,
17770xa1,0x62,0x00,0x04,0x00,0x8c,0x20,0x21,0x94,0x83,0x00,0x04,0x00,0x07,0x10,0xc0,
17780x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21,0x00,0x03,0x28,0xc0,
17790x94,0x46,0x00,0x02,0x00,0xa3,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x6c,0x18,0x21,
17800xa4,0x66,0x00,0x00,0xa4,0x86,0x00,0x02,0x95,0x64,0x00,0x02,0x3c,0x03,0xb0,0x08,
17810x3c,0x02,0x80,0x01,0x00,0xa3,0x28,0x21,0x24,0x42,0x82,0xe4,0xad,0xa2,0x00,0x00,
17820x10,0x87,0x00,0x03,0xac,0xa6,0x00,0x00,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,
17830x08,0x00,0x1b,0x66,0xa5,0x68,0x00,0x02,0x91,0x62,0x00,0x04,0xa5,0x67,0x00,0x00,
17840x24,0x42,0xff,0xff,0x30,0x43,0x00,0xff,0x14,0x60,0x00,0x03,0xa1,0x62,0x00,0x04,
17850x24,0x02,0xff,0xff,0xa5,0x62,0x00,0x02,0x91,0x65,0x00,0x04,0x00,0x00,0x00,0x00,
17860x10,0xa0,0xff,0xf1,0x00,0x00,0x00,0x00,0x95,0x66,0x00,0x00,0x34,0x02,0xff,0xff,
17870x14,0xc2,0xff,0xed,0x3c,0x03,0xb0,0x03,0x95,0x64,0x00,0x02,0x3c,0x02,0xee,0xee,
17880x00,0xa2,0x10,0x25,0x34,0x63,0x00,0xbc,0xac,0x62,0x00,0x00,0x10,0x86,0xff,0xe6,
17890xa1,0x60,0x00,0x04,0x24,0x02,0xff,0xff,0x08,0x00,0x1b,0x66,0xa5,0x62,0x00,0x02,
17900x00,0x05,0x40,0xc0,0x01,0x05,0x30,0x21,0x27,0xbd,0xff,0xd8,0x00,0x06,0x30,0x80,
17910x27,0x82,0x8f,0xf4,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,
17920xaf,0xb3,0x00,0x1c,0xaf,0xb0,0x00,0x10,0x00,0xc2,0x10,0x21,0x8c,0x47,0x00,0x18,
17930x00,0xa0,0x90,0x21,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,
17940x24,0x42,0x6e,0x10,0xac,0xa2,0x00,0x00,0x27,0x83,0x90,0x00,0x00,0xc3,0x30,0x21,
17950x8c,0xe2,0x00,0x00,0x80,0xc5,0x00,0x06,0x00,0x80,0x88,0x21,0x30,0x42,0xff,0xff,
17960x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x02,0x00,0x02,0x12,0x02,
17970x24,0x42,0x00,0x01,0x30,0x53,0x00,0xff,0x01,0x12,0x10,0x21,0x00,0x02,0x10,0x80,
17980x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x80,0x44,0x00,0x07,0x00,0x00,0x00,0x00,
17990x10,0x80,0x00,0x4b,0x26,0x24,0x00,0x06,0x32,0x50,0xff,0xff,0x02,0x20,0x20,0x21,
18000x0c,0x00,0x1b,0x26,0x02,0x00,0x28,0x21,0x92,0x22,0x00,0x10,0x00,0x00,0x00,0x00,
18010x14,0x40,0x00,0x2e,0x3c,0x03,0xb0,0x08,0x3c,0x09,0x80,0x01,0x27,0x88,0x8f,0xf0,
18020xa6,0x32,0x00,0x0c,0x00,0x10,0x20,0xc0,0x00,0x90,0x20,0x21,0x00,0x04,0x20,0x80,
18030x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,
18040x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x48,0x10,0x21,
18050x00,0xa3,0x28,0x21,0x25,0x26,0x82,0xe4,0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,
18060xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,
18070x92,0x22,0x00,0x10,0x92,0x23,0x00,0x0a,0xa6,0x32,0x00,0x0e,0x02,0x62,0x10,0x21,
18080x14,0x60,0x00,0x05,0xa2,0x22,0x00,0x10,0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,
18090x30,0x42,0x00,0xfe,0xa2,0x22,0x00,0x16,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,
18100x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,
18110x30,0x42,0x00,0xfd,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,
18120x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x96,0x22,0x00,0x0e,
18130x27,0x88,0x8f,0xf0,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,
18140x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x06,0xb0,0x03,0x3c,0x09,0x80,0x01,
18150x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,
18160x00,0x48,0x10,0x21,0x34,0xc6,0x00,0x20,0x25,0x23,0x82,0xe4,0xac,0xc3,0x00,0x00,
18170xa4,0x50,0x00,0x00,0xac,0xb0,0x00,0x00,0x08,0x00,0x1b,0xb5,0xa4,0x90,0x00,0x02,
18180x08,0x00,0x1b,0xac,0x32,0x50,0xff,0xff,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
18190x24,0x42,0x6f,0xd8,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x90,0x82,0x00,0x04,
18200x97,0xaa,0x00,0x12,0x00,0x80,0x60,0x21,0x30,0xa8,0xff,0xff,0x00,0x4a,0x20,0x23,
18210x34,0x09,0xff,0xff,0x30,0xcf,0xff,0xff,0x30,0xee,0xff,0xff,0x11,0x09,0x00,0x73,
18220xa1,0x84,0x00,0x04,0x00,0x0e,0xc0,0xc0,0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,
18230x03,0x0e,0x20,0x21,0x27,0x8d,0x8f,0xf0,0x00,0x04,0x20,0x80,0x00,0x02,0x10,0x80,
18240x00,0x4d,0x10,0x21,0x00,0x8d,0x20,0x21,0x94,0x86,0x00,0x02,0x94,0x43,0x00,0x04,
18250x3c,0x19,0x80,0x01,0xa4,0x46,0x00,0x02,0x00,0x03,0x28,0xc0,0x00,0xa3,0x18,0x21,
18260x94,0x87,0x00,0x02,0x3c,0x02,0xb0,0x08,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x21,
18270x00,0x6d,0x18,0x21,0x27,0x22,0x82,0xe4,0x3c,0x01,0xb0,0x03,0xac,0x22,0x00,0x20,
18280xa4,0x66,0x00,0x00,0x10,0xe9,0x00,0x57,0xac,0xa6,0x00,0x00,0x01,0xe0,0x30,0x21,
18290x11,0x40,0x00,0x1d,0x00,0x00,0x48,0x21,0x01,0x40,0x38,0x21,0x27,0x8b,0x8f,0xf4,
18300x27,0x8a,0x90,0x00,0x00,0x06,0x40,0xc0,0x01,0x06,0x18,0x21,0x00,0x03,0x18,0x80,
18310x00,0x6b,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x6a,0x18,0x21,0x80,0x65,0x00,0x06,
18320x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,
18330x30,0x44,0x00,0xff,0x00,0x02,0x12,0x02,0x01,0x22,0x18,0x21,0x24,0x62,0x00,0x01,
18340x14,0x80,0x00,0x02,0x30,0x49,0x00,0xff,0x30,0x69,0x00,0xff,0x01,0x06,0x10,0x21,
18350x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x24,0xe7,0xff,0xff,0x94,0x46,0x00,0x02,
18360x14,0xe0,0xff,0xe9,0x00,0x06,0x40,0xc0,0x91,0x82,0x00,0x10,0x00,0x00,0x00,0x00,
18370x14,0x40,0x00,0x20,0x3c,0x06,0xb0,0x03,0xa5,0x8f,0x00,0x0c,0x03,0x0e,0x20,0x21,
18380x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08,
18390x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,
18400x00,0x4d,0x10,0x21,0x00,0xa3,0x28,0x21,0x27,0x26,0x82,0xe4,0x34,0x03,0xff,0xff,
18410x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00,
18420xac,0xa3,0x00,0x00,0x91,0x82,0x00,0x10,0x91,0x83,0x00,0x04,0xa5,0x8e,0x00,0x0e,
18430x01,0x22,0x10,0x21,0x14,0x60,0x00,0x05,0xa1,0x82,0x00,0x10,0x91,0x82,0x00,0x16,
18440x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa1,0x82,0x00,0x16,0x03,0xe0,0x00,0x08,
18450x00,0x00,0x00,0x00,0x95,0x82,0x00,0x0e,0x3c,0x03,0xb0,0x08,0x00,0x02,0x20,0xc0,
18460x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04,
18470x34,0xc6,0x00,0x20,0x27,0x27,0x82,0xe4,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,
18480x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,0x00,0x4d,0x10,0x21,0xac,0xc7,0x00,0x00,
18490xa4,0x8f,0x00,0x02,0xa4,0x4f,0x00,0x00,0xac,0xaf,0x00,0x00,0x08,0x00,0x1c,0x44,
18500x03,0x0e,0x20,0x21,0x08,0x00,0x1c,0x1f,0xa5,0x88,0x00,0x02,0x00,0x0e,0xc0,0xc0,
18510x03,0x0e,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x8d,0x8f,0xf0,0x00,0x4d,0x10,0x21,
18520x94,0x43,0x00,0x02,0x30,0x84,0x00,0xff,0x14,0x80,0x00,0x05,0xa5,0x83,0x00,0x00,
18530x24,0x02,0xff,0xff,0x3c,0x19,0x80,0x01,0x08,0x00,0x1c,0x1f,0xa5,0x82,0x00,0x02,
18540x08,0x00,0x1c,0x1f,0x3c,0x19,0x80,0x01,0x3c,0x08,0xb0,0x03,0x3c,0x02,0x80,0x00,
18550x27,0xbd,0xff,0x78,0x35,0x08,0x00,0x20,0x24,0x42,0x72,0x18,0xaf,0xb2,0x00,0x68,
18560xaf,0xb1,0x00,0x64,0xaf,0xb0,0x00,0x60,0xad,0x02,0x00,0x00,0xaf,0xbf,0x00,0x84,
18570xaf,0xbe,0x00,0x80,0xaf,0xb7,0x00,0x7c,0xaf,0xb6,0x00,0x78,0xaf,0xb5,0x00,0x74,
18580xaf,0xb4,0x00,0x70,0xaf,0xb3,0x00,0x6c,0xaf,0xa4,0x00,0x88,0x90,0x83,0x00,0x0a,
18590x27,0x82,0xb3,0xf0,0xaf,0xa6,0x00,0x90,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,
18600x8c,0x63,0x00,0x00,0xaf,0xa7,0x00,0x94,0x27,0x86,0x8f,0xf4,0xaf,0xa3,0x00,0x1c,
18610x94,0x63,0x00,0x14,0x30,0xb1,0xff,0xff,0x24,0x08,0x00,0x01,0x00,0x03,0x20,0xc0,
18620xaf,0xa3,0x00,0x18,0x00,0x83,0x18,0x21,0xaf,0xa4,0x00,0x54,0x00,0x03,0x18,0x80,
18630x27,0x84,0x90,0x00,0x00,0x64,0x20,0x21,0x80,0x82,0x00,0x06,0x00,0x66,0x18,0x21,
18640x8c,0x66,0x00,0x18,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x8c,0xc4,0x00,0x08,
18650x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0x04,0x2f,0xc2,
18660x00,0x04,0x1c,0x82,0x00,0xc2,0x38,0x21,0x00,0x04,0x24,0x42,0x8f,0xa2,0x00,0x1c,
18670x30,0x63,0x00,0x01,0x30,0x84,0x00,0x01,0xaf,0xa5,0x00,0x3c,0xaf,0xa3,0x00,0x34,
18680xaf,0xa4,0x00,0x38,0xaf,0xa0,0x00,0x40,0xaf,0xa0,0x00,0x44,0xaf,0xa0,0x00,0x50,
18690xaf,0xa8,0x00,0x20,0x80,0x42,0x00,0x12,0x8f,0xb2,0x00,0x18,0xaf,0xa2,0x00,0x28,
18700x8c,0xd0,0x00,0x0c,0x14,0xa0,0x01,0xe4,0x00,0x60,0x30,0x21,0x00,0x10,0x10,0x82,
18710x30,0x45,0x00,0x07,0x10,0xa0,0x00,0x11,0xaf,0xa0,0x00,0x30,0x8f,0xa4,0x00,0x98,
18720x27,0x82,0x80,0x1c,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x21,0x24,0xa2,0x00,0x06,
18730x8f,0xa5,0x00,0x20,0x94,0x64,0x00,0x00,0x00,0x45,0x10,0x04,0x00,0x44,0x00,0x1a,
18740x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12,
18750x24,0x42,0x00,0x20,0x30,0x42,0xff,0xfc,0xaf,0xa2,0x00,0x30,0x8f,0xa3,0x00,0x18,
18760x8f,0xa4,0x00,0x28,0x34,0x02,0xff,0xff,0xaf,0xa0,0x00,0x2c,0xaf,0xa2,0x00,0x48,
18770xaf,0xa3,0x00,0x4c,0x00,0x60,0xf0,0x21,0x00,0x00,0xb8,0x21,0x18,0x80,0x00,0x48,
18780xaf,0xa0,0x00,0x24,0x00,0x11,0x89,0x02,0xaf,0xb1,0x00,0x58,0x00,0x80,0xa8,0x21,
18790x00,0x12,0x10,0xc0,0x00,0x52,0x18,0x21,0x00,0x03,0x80,0x80,0x27,0x85,0x8f,0xf0,
18800x02,0x40,0x20,0x21,0x00,0x40,0xa0,0x21,0x02,0x05,0x10,0x21,0x94,0x56,0x00,0x02,
18810x0c,0x00,0x12,0x87,0x00,0x00,0x28,0x21,0x90,0x42,0x00,0x00,0x24,0x03,0x00,0x08,
18820x30,0x42,0x00,0x0c,0x10,0x43,0x01,0x9e,0x24,0x04,0x00,0x01,0x24,0x02,0x00,0x01,
18830x10,0x82,0x01,0x7c,0x3c,0x02,0xb0,0x03,0x8f,0xa6,0x00,0x88,0x34,0x42,0x01,0x04,
18840x84,0xc5,0x00,0x0c,0x02,0x92,0x18,0x21,0x94,0x46,0x00,0x00,0x00,0x05,0x20,0xc0,
18850x00,0x85,0x20,0x21,0x00,0x03,0x18,0x80,0x27,0x82,0x90,0x00,0x27,0x85,0x8f,0xf8,
18860x00,0x65,0x28,0x21,0x00,0x62,0x18,0x21,0x80,0x71,0x00,0x05,0x80,0x73,0x00,0x04,
18870x8f,0xa3,0x00,0x88,0x30,0xd0,0xff,0xff,0x00,0x10,0x3a,0x03,0x32,0x08,0x00,0xff,
18880x27,0x82,0x90,0x10,0x00,0x04,0x20,0x80,0x80,0xa6,0x00,0x06,0x00,0x82,0x20,0x21,
18890xa4,0x67,0x00,0x44,0xa4,0x68,0x00,0x46,0x8c,0x84,0x00,0x00,0x38,0xc6,0x00,0x00,
18900x01,0x00,0x80,0x21,0x00,0x04,0x15,0x02,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x03,
18910x00,0xe6,0x80,0x0a,0x00,0x04,0x14,0x02,0x30,0x50,0x00,0x0f,0x12,0x20,0x01,0x50,
18920x02,0x40,0x20,0x21,0x02,0x71,0x10,0x21,0x00,0x50,0x10,0x2a,0x14,0x40,0x00,0xed,
18930x02,0x92,0x10,0x21,0x93,0x82,0x8b,0x61,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,
18940x14,0x40,0x00,0xe0,0x02,0x92,0x28,0x21,0x26,0xe2,0x00,0x01,0x30,0x57,0xff,0xff,
18950x02,0x40,0xf0,0x21,0x26,0xb5,0xff,0xff,0x16,0xa0,0xff,0xbd,0x02,0xc0,0x90,0x21,
18960x16,0xe0,0x00,0xd0,0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x98,0x00,0x00,0x00,0x00,
18970x2c,0x62,0x00,0x10,0x10,0x40,0x00,0x2e,0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x24,
18980x00,0x00,0x00,0x00,0x18,0x80,0x00,0x2a,0x24,0x03,0x00,0x01,0x8f,0xa5,0x00,0x1c,
18990x27,0x84,0x8f,0xf4,0x94,0xb2,0x00,0x14,0xa0,0xa3,0x00,0x12,0x8f,0xa6,0x00,0x3c,
19000x00,0x12,0x10,0xc0,0x00,0x52,0x10,0x21,0x00,0x02,0x80,0x80,0x27,0x82,0x90,0x00,
19010x02,0x02,0x10,0x21,0x80,0x43,0x00,0x06,0x02,0x04,0x20,0x21,0x8c,0x85,0x00,0x18,
19020x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,
19030x00,0x03,0x18,0x40,0x14,0xc0,0x00,0x0e,0x00,0xa3,0x38,0x21,0x27,0x82,0x8f,0xf0,
19040x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,0x8f,0xa8,0x00,0x1c,0x24,0x02,0x00,0x01,
19050xa5,0x03,0x00,0x1a,0x7b,0xbe,0x04,0x3c,0x7b,0xb6,0x03,0xfc,0x7b,0xb4,0x03,0xbc,
19060x7b,0xb2,0x03,0x7c,0x7b,0xb0,0x03,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x88,
19070x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,0x8f,0xa6,0x00,0x34,0xaf,0xa0,0x00,0x10,
19080x0c,0x00,0x09,0x06,0xaf,0xa0,0x00,0x14,0x08,0x00,0x1d,0x4b,0x00,0x00,0x00,0x00,
19090x8f,0xa3,0x00,0x44,0x93,0x82,0x81,0x59,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x61,
19100x30,0x69,0x00,0x03,0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x28,0x00,0x00,0x00,0x00,
19110x00,0x85,0x10,0x2a,0x10,0x40,0x00,0x8f,0x00,0x00,0x00,0x00,0x8f,0xa6,0x00,0x1c,
19120x00,0x00,0x00,0x00,0x90,0xc4,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,
19130x00,0xa3,0x10,0x2a,0x10,0x40,0x00,0x87,0x00,0x00,0x00,0x00,0x8f,0xa8,0x00,0x24,
19140x00,0x00,0x00,0x00,0x11,0x00,0x00,0x83,0x00,0x65,0x10,0x23,0x00,0xa8,0x18,0x23,
19150x00,0x62,0x10,0x2a,0x14,0x40,0x00,0x7d,0x30,0x63,0x00,0xff,0x00,0x85,0x10,0x23,
19160x30,0x42,0x00,0xff,0xaf,0xa2,0x00,0x50,0x8f,0xa2,0x00,0x50,0x00,0x00,0x00,0x00,
19170x10,0x40,0x00,0x73,0x00,0x00,0xa8,0x21,0x27,0x8c,0x8f,0xf0,0x3c,0x0b,0x80,0xff,
19180x24,0x10,0x00,0x04,0x27,0x91,0x8f,0xf4,0x35,0x6b,0xff,0xff,0x3c,0x0d,0x7f,0x00,
19190x27,0x8e,0x90,0x00,0x01,0x80,0x78,0x21,0x00,0x12,0x30,0xc0,0x00,0xd2,0x10,0x21,
19200x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21,0x94,0x42,0x00,0x06,0x8f,0xa3,0x00,0x2c,
19210x8f,0xa4,0x00,0x30,0xaf,0xa2,0x00,0x44,0x8f,0xa5,0x00,0x44,0x30,0x49,0x00,0x03,
19220x02,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x00,0xa2,0x10,0x21,0x8f,0xa8,0x00,0x30,
19230x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,0x00,0x64,0x38,0x21,0x01,0x02,0x28,0x23,
19240x00,0x62,0x18,0x21,0x00,0x48,0x10,0x2b,0x10,0x40,0x00,0x52,0x00,0x00,0x20,0x21,
19250x30,0xe7,0xff,0xff,0x30,0xa4,0xff,0xff,0xaf,0xa7,0x00,0x2c,0x00,0xd2,0x10,0x21,
19260x00,0x02,0x10,0x80,0x00,0x51,0x18,0x21,0x8c,0x65,0x00,0x18,0x00,0x04,0x25,0x40,
19270x00,0x8d,0x20,0x24,0x8c,0xa8,0x00,0x04,0x00,0x4e,0x18,0x21,0x00,0x4f,0x50,0x21,
19280x01,0x0b,0x40,0x24,0x01,0x04,0x40,0x25,0xac,0xa8,0x00,0x04,0x8f,0xa4,0x00,0x98,
19290x8f,0xa2,0x00,0x50,0x26,0xb5,0x00,0x01,0xa0,0x64,0x00,0x00,0x8c,0xa4,0x00,0x08,
19300x00,0x00,0x00,0x00,0x04,0x81,0x00,0x0c,0x02,0xa2,0x30,0x2a,0x80,0x62,0x00,0x06,
19310x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,
19320x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0xa2,0x38,0x21,0x8f,0xa5,0x00,0x40,
19330x00,0x00,0x00,0x00,0xa4,0xe5,0x00,0x00,0x95,0x52,0x00,0x02,0x14,0xc0,0xff,0xc7,
19340x00,0x12,0x30,0xc0,0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x50,0x8f,0xa6,0x00,0x1c,
19350x8f,0xa3,0x00,0x2c,0x00,0x85,0x80,0x21,0xa0,0xd0,0x00,0x12,0x00,0x09,0x10,0x23,
19360x30,0x42,0x00,0x03,0x8f,0xa8,0x00,0x88,0x00,0x62,0x10,0x23,0xa4,0xc2,0x00,0x1a,
19370x85,0x03,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
19380x00,0x02,0x10,0x80,0x27,0x83,0x8f,0xf4,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,
19390x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,
19400x14,0x60,0xff,0x74,0x02,0x00,0x10,0x21,0x8f,0xa3,0x00,0x54,0x8f,0xa4,0x00,0x18,
19410x8f,0xa5,0x00,0x24,0x00,0x64,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x08,
19420x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x10,0xa0,0x00,0x03,0x00,0x00,0x30,0x21,
19430x08,0x00,0x1d,0x51,0x02,0x00,0x10,0x21,0x93,0x82,0x80,0x10,0x00,0x00,0x28,0x21,
19440x00,0x00,0x38,0x21,0x0c,0x00,0x21,0xf5,0xaf,0xa2,0x00,0x10,0x08,0x00,0x1d,0x51,
19450x02,0x00,0x10,0x21,0x30,0x63,0xff,0xff,0x08,0x00,0x1d,0xa3,0xaf,0xa3,0x00,0x2c,
19460x8f,0xa8,0x00,0x44,0x08,0x00,0x1d,0xc5,0x31,0x09,0x00,0x03,0x08,0x00,0x1d,0x7e,
19470xaf,0xa3,0x00,0x50,0x8f,0xa6,0x00,0x44,0xaf,0xa0,0x00,0x50,0x08,0x00,0x1d,0xc5,
19480x30,0xc9,0x00,0x03,0x8f,0xa5,0x00,0x48,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,
19490x03,0xc0,0x38,0x21,0x0c,0x00,0x1b,0xf6,0xaf,0xb7,0x00,0x10,0x08,0x00,0x1d,0x2e,
19500x00,0x00,0x00,0x00,0x00,0x05,0x28,0x80,0x27,0x82,0x8f,0xf0,0x00,0xa2,0x28,0x21,
19510x00,0x00,0x20,0x21,0x0c,0x00,0x01,0x4b,0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0x27,
19520x26,0xe2,0x00,0x01,0x00,0x02,0x80,0x80,0x27,0x83,0x90,0x00,0x8f,0xa4,0x00,0x1c,
19530x02,0x03,0x18,0x21,0x26,0x31,0x00,0x01,0x02,0x40,0x28,0x21,0x0c,0x00,0x1f,0x08,
19540xa0,0x71,0x00,0x05,0x14,0x40,0xff,0x13,0x00,0x00,0x00,0x00,0x16,0xe0,0x00,0x4d,
19550x03,0xc0,0x38,0x21,0x8f,0xa4,0x00,0x24,0x8f,0xa5,0x00,0x20,0x24,0x02,0x00,0x01,
19560x24,0x84,0x00,0x01,0xaf,0xb2,0x00,0x48,0xaf,0xb6,0x00,0x4c,0x02,0xc0,0xf0,0x21,
19570x10,0xa2,0x00,0x41,0xaf,0xa4,0x00,0x24,0x27,0x82,0x8f,0xf0,0x02,0x02,0x10,0x21,
19580x94,0x42,0x00,0x06,0x8f,0xa4,0x00,0x30,0xaf,0xa0,0x00,0x20,0xaf,0xa2,0x00,0x44,
19590x30,0x49,0x00,0x03,0x8f,0xa8,0x00,0x44,0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,
19600x01,0x02,0x10,0x21,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,0x00,0x44,0x18,0x2b,
19610x10,0x60,0x00,0x2b,0x00,0x00,0x00,0x00,0x8f,0xa5,0x00,0x2c,0x00,0x82,0x10,0x23,
19620x00,0xa4,0x18,0x21,0x30,0x63,0xff,0xff,0x30,0x44,0xff,0xff,0xaf,0xa3,0x00,0x2c,
19630x02,0x92,0x28,0x21,0x00,0x05,0x28,0x80,0x27,0x82,0x8f,0xf4,0x00,0xa2,0x10,0x21,
19640x8c,0x46,0x00,0x18,0x3c,0x03,0x80,0xff,0x3c,0x02,0x7f,0x00,0x8c,0xc8,0x00,0x04,
19650x00,0x04,0x25,0x40,0x34,0x63,0xff,0xff,0x00,0x82,0x20,0x24,0x01,0x03,0x40,0x24,
19660x01,0x04,0x40,0x25,0xac,0xc8,0x00,0x04,0x8f,0xa8,0x00,0x98,0x27,0x82,0x90,0x00,
19670x00,0xa2,0x10,0x21,0xa0,0x48,0x00,0x00,0x8c,0xc4,0x00,0x08,0x00,0x00,0x00,0x00,
19680x00,0x04,0x27,0xc2,0x10,0x80,0xfe,0xdb,0xaf,0xa4,0x00,0x3c,0x80,0x42,0x00,0x06,
19690x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,
19700x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0xc2,0x38,0x21,0x8f,0xa2,0x00,0x40,
19710x00,0x00,0x00,0x00,0xa4,0xe2,0x00,0x00,0x08,0x00,0x1d,0x2a,0x26,0xb5,0xff,0xff,
19720x8f,0xa6,0x00,0x2c,0x00,0x00,0x20,0x21,0x00,0xc2,0x10,0x21,0x30,0x42,0xff,0xff,
19730x08,0x00,0x1e,0x38,0xaf,0xa2,0x00,0x2c,0x8f,0xa6,0x00,0x1c,0x08,0x00,0x1e,0x22,
19740xa4,0xd2,0x00,0x14,0x8f,0xa5,0x00,0x48,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,
19750x0c,0x00,0x1b,0xf6,0xaf,0xb7,0x00,0x10,0x08,0x00,0x1e,0x19,0x00,0x00,0xb8,0x21,
19760x0c,0x00,0x12,0x87,0x00,0x00,0x28,0x21,0x00,0x40,0x18,0x21,0x94,0x42,0x00,0x00,
19770x00,0x00,0x00,0x00,0x34,0x42,0x08,0x00,0xa4,0x62,0x00,0x00,0x08,0x00,0x1d,0x1e,
19780x02,0x71,0x10,0x21,0x02,0x92,0x18,0x21,0x00,0x03,0x80,0x80,0x27,0x82,0x8f,0xf4,
19790x02,0x02,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,
19800x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x10,0x60,0x00,0x09,0x24,0x06,0x00,0x01,
19810x93,0x82,0x8b,0x61,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x10,0x40,0xfe,0xa2,
19820x3c,0x04,0x00,0x80,0x27,0x85,0x8f,0xf0,0x08,0x00,0x1e,0x09,0x02,0x05,0x28,0x21,
19830x27,0x83,0x90,0x08,0x27,0x82,0x90,0x00,0x02,0x03,0x18,0x21,0x02,0x02,0x10,0x21,
19840x90,0x64,0x00,0x00,0x90,0x45,0x00,0x05,0x93,0x83,0x80,0x10,0x00,0x00,0x38,0x21,
19850x0c,0x00,0x21,0xf5,0xaf,0xa3,0x00,0x10,0x08,0x00,0x1e,0x80,0x00,0x00,0x00,0x00,
19860x27,0x82,0x90,0x08,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x02,0x8f,0xa6,0x00,0x58,
19870x00,0x03,0x19,0x02,0x00,0x66,0x18,0x23,0x30,0x63,0x0f,0xff,0x28,0x62,0x00,0x20,
19880x10,0x40,0x00,0x06,0x28,0x62,0x00,0x40,0x8f,0xa8,0x00,0x90,0x00,0x00,0x00,0x00,
19890x00,0x68,0x10,0x06,0x08,0x00,0x1c,0xf7,0x30,0x44,0x00,0x01,0x10,0x40,0x00,0x04,
19900x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x94,0x08,0x00,0x1e,0xa1,0x00,0x64,0x10,0x06,
19910x08,0x00,0x1c,0xf7,0x00,0x00,0x20,0x21,0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,
19920xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x06,0xaf,0xa8,0x00,0x14,0x30,0x42,0xff,0xff,
19930x08,0x00,0x1c,0xc7,0xaf,0xa2,0x00,0x40,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,
19940x27,0xbd,0xff,0xe0,0x34,0x42,0x00,0x20,0x24,0x63,0x7a,0xc8,0xaf,0xb1,0x00,0x14,
19950xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x0a,
19960x00,0x80,0x80,0x21,0x14,0x40,0x00,0x45,0x00,0x00,0x88,0x21,0x92,0x02,0x00,0x04,
19970x00,0x00,0x00,0x00,0x14,0x40,0x00,0x3c,0x00,0x00,0x00,0x00,0x12,0x20,0x00,0x18,
19980x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x92,0x05,0x00,0x0a,0x30,0x42,0x00,0xfc,
19990x10,0xa0,0x00,0x03,0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,
20000x92,0x04,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x10,0x60,0x00,0x05,
20010x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,
20020xa2,0x02,0x00,0x16,0x10,0x60,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x08,
20030x00,0x00,0x00,0x00,0x96,0x02,0x00,0x00,0xa2,0x00,0x00,0x17,0xa6,0x02,0x00,0x14,
20040x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
20050x14,0x80,0x00,0x05,0x24,0x02,0x00,0x01,0x96,0x03,0x00,0x06,0xa2,0x02,0x00,0x17,
20060x08,0x00,0x1e,0xdc,0xa6,0x03,0x00,0x14,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,
20070x27,0x86,0x8f,0xf0,0x00,0x04,0x10,0xc0,0x00,0x05,0x18,0xc0,0x00,0x44,0x10,0x21,
20080x00,0x65,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,
20090x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x0c,0x00,0x12,0x78,
20100x00,0x00,0x00,0x00,0x30,0x43,0x00,0xff,0x10,0x60,0x00,0x04,0xa2,0x02,0x00,0x17,
20110x96,0x02,0x00,0x06,0x08,0x00,0x1e,0xdc,0xa6,0x02,0x00,0x14,0x96,0x02,0x00,0x00,
20120x08,0x00,0x1e,0xdc,0xa6,0x02,0x00,0x14,0x96,0x05,0x00,0x00,0x0c,0x00,0x1f,0x08,
20130x02,0x00,0x20,0x21,0x08,0x00,0x1e,0xc3,0x02,0x22,0x88,0x21,0x94,0x85,0x00,0x06,
20140x0c,0x00,0x1f,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x1e,0xbf,0x00,0x40,0x88,0x21,
20150x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x7c,0x20,
20160x27,0xbd,0xff,0xf0,0xac,0x62,0x00,0x00,0x00,0x00,0x10,0x21,0x03,0xe0,0x00,0x08,
20170x27,0xbd,0x00,0x10,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
20180x24,0x42,0x7c,0x44,0xac,0x62,0x00,0x00,0x90,0x89,0x00,0x0a,0x00,0x80,0x30,0x21,
20190x11,0x20,0x00,0x05,0x00,0xa0,0x50,0x21,0x90,0x82,0x00,0x17,0x00,0x00,0x00,0x00,
20200x14,0x40,0x00,0x1b,0x00,0x00,0x00,0x00,0x90,0xc7,0x00,0x04,0x00,0x00,0x00,0x00,
20210x10,0xe0,0x00,0x1b,0x00,0x00,0x00,0x00,0x94,0xc8,0x00,0x00,0x27,0x83,0x8f,0xf0,
20220x93,0x85,0x8b,0x60,0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x00,0x02,0x10,0x80,
20230x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08,0x00,0xe5,0x28,0x2b,0x10,0xa0,0x00,0x06,
20240x01,0x44,0x18,0x23,0x8f,0x82,0x8b,0x78,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x2b,
20250x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x10,0xa4,0xc8,0x00,0x14,
20260x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,0x11,0x20,0x00,0x05,0x00,0x00,0x00,0x00,
20270x94,0xc2,0x00,0x06,0x24,0x03,0x00,0x08,0x08,0x00,0x1f,0x34,0xa4,0xc2,0x00,0x14,
20280x08,0x00,0x1f,0x34,0x00,0x00,0x18,0x21,0x27,0xbd,0xff,0xc8,0xaf,0xb5,0x00,0x2c,
20290xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x30,
20300xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0x94,0x91,0x00,0x06,0x00,0x80,0xa0,0x21,
20310x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x00,0x11,0xa8,0xc0,0x34,0x84,0x00,0x20,
20320x24,0x42,0x7c,0xf8,0x02,0xb1,0x48,0x21,0xac,0x82,0x00,0x00,0x00,0x09,0x48,0x80,
20330x24,0x03,0x00,0x01,0x27,0x82,0x90,0x00,0xa2,0x83,0x00,0x12,0x01,0x22,0x10,0x21,
20340x27,0x84,0x8f,0xf4,0x01,0x24,0x20,0x21,0x80,0x48,0x00,0x06,0x8c,0x8a,0x00,0x18,
20350x27,0x83,0x90,0x10,0x01,0x23,0x48,0x21,0x8d,0x24,0x00,0x00,0x25,0x08,0x00,0x02,
20360x8d,0x42,0x00,0x00,0x8d,0x49,0x00,0x04,0x00,0x08,0x17,0xc2,0x8d,0x43,0x00,0x08,
20370x01,0x02,0x40,0x21,0x00,0x04,0x25,0xc2,0x00,0x08,0x40,0x43,0x30,0x84,0x00,0x01,
20380x00,0x03,0x1f,0xc2,0x00,0x08,0x40,0x40,0x00,0xe0,0x80,0x21,0x00,0x64,0x18,0x24,
20390x00,0x09,0x49,0x42,0x01,0x48,0x10,0x21,0x00,0xa0,0x98,0x21,0x00,0xa0,0x20,0x21,
20400x00,0x40,0x38,0x21,0x02,0x00,0x28,0x21,0x14,0x60,0x00,0x19,0x31,0x29,0x00,0x01,
20410x94,0x42,0x00,0x00,0x02,0xb1,0x88,0x21,0x02,0x00,0x28,0x21,0x00,0x11,0x88,0x80,
20420x27,0x90,0x8f,0xf0,0x02,0x30,0x80,0x21,0x96,0x03,0x00,0x06,0x30,0x52,0xff,0xff,
20430x02,0x60,0x20,0x21,0x00,0x60,0x30,0x21,0xa6,0x83,0x00,0x1a,0x27,0x82,0x8f,0xf8,
20440x0c,0x00,0x08,0xdf,0x02,0x22,0x88,0x21,0x00,0x52,0x10,0x21,0x96,0x03,0x00,0x06,
20450xa6,0x22,0x00,0x04,0x8f,0xbf,0x00,0x30,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,
20460x7b,0xb0,0x00,0xfc,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,
20470xaf,0xa9,0x00,0x10,0x0c,0x00,0x09,0x06,0xaf,0xa0,0x00,0x14,0x08,0x00,0x1f,0x72,
20480x02,0xb1,0x88,0x21,0x27,0xbd,0xff,0xc0,0xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,
20490xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,
20500xaf,0xbf,0x00,0x3c,0xaf,0xb4,0x00,0x28,0xaf,0xb2,0x00,0x20,0xaf,0xb0,0x00,0x18,
20510x94,0x90,0x00,0x00,0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x20,0x00,0x10,0x10,0xc0,
20520x00,0x50,0x18,0x21,0x00,0x40,0x88,0x21,0x3c,0x02,0x80,0x00,0x00,0x03,0x48,0x80,
20530x24,0x42,0x7e,0x34,0x00,0x80,0x98,0x21,0x27,0x84,0x90,0x00,0x01,0x24,0x20,0x21,
20540x93,0xb7,0x00,0x53,0xad,0x02,0x00,0x00,0x80,0x83,0x00,0x06,0x27,0x82,0x8f,0xf4,
20550x01,0x22,0x10,0x21,0x8c,0x44,0x00,0x18,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,
20560x8c,0x88,0x00,0x08,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,
20570xaf,0xa7,0x00,0x4c,0x2c,0xa2,0x00,0x10,0x00,0xa0,0xa8,0x21,0x00,0x83,0x50,0x21,
20580x00,0x08,0x47,0xc2,0x00,0xc0,0x58,0x21,0x00,0x00,0xb0,0x21,0x8c,0x92,0x00,0x0c,
20590x14,0x40,0x00,0x13,0x00,0x00,0xf0,0x21,0x92,0x67,0x00,0x04,0x24,0x14,0x00,0x01,
20600x12,0x87,0x00,0x10,0x02,0x30,0x10,0x21,0x27,0x83,0x90,0x08,0x01,0x23,0x18,0x21,
20610x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x60,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,
20620x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
20630x90,0x44,0x00,0x04,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x23,0x00,0x00,0x00,0x00,
20640x02,0x30,0x10,0x21,0x00,0x02,0x80,0x80,0x24,0x04,0x00,0x01,0x27,0x83,0x90,0x10,
20650xa2,0x64,0x00,0x12,0x02,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
20660x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x14,0x40,0x00,0x0e,
20670x02,0xa0,0x20,0x21,0x27,0x82,0x8f,0xf0,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,
20680x00,0x00,0x00,0x00,0xa6,0x63,0x00,0x1a,0x94,0x42,0x00,0x06,0x7b,0xbe,0x01,0xfc,
20690x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,
20700x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x8f,0xa5,0x00,0x4c,0x01,0x60,0x30,0x21,
20710x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x06,0xaf,0xa0,0x00,0x14,
20720x08,0x00,0x1f,0xd9,0x00,0x00,0x00,0x00,0x27,0x83,0x90,0x10,0x01,0x23,0x18,0x21,
20730x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,
20740x01,0x02,0x10,0x24,0x14,0x40,0x00,0xaf,0x00,0xa0,0x20,0x21,0x32,0x4f,0x00,0x03,
20750x00,0x12,0x10,0x82,0x25,0xe3,0x00,0x0d,0x30,0x45,0x00,0x07,0x00,0x74,0x78,0x04,
20760x10,0xa0,0x00,0x0e,0x00,0x00,0x90,0x21,0x27,0x82,0x80,0x1c,0x00,0x15,0x18,0x40,
20770x00,0x62,0x18,0x21,0x94,0x64,0x00,0x00,0x24,0xa2,0x00,0x06,0x00,0x54,0x10,0x04,
20780x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,
20790x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,0x30,0x52,0xff,0xfc,0x02,0x30,0x10,0x21,
20800x27,0x83,0x90,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x03,
20810x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x04,
20820x2c,0x62,0x00,0x19,0x30,0x82,0x00,0x0f,0x24,0x43,0x00,0x0c,0x2c,0x62,0x00,0x19,
20830x10,0x40,0x00,0x19,0x24,0x0e,0x00,0x20,0x24,0x62,0xff,0xe9,0x2c,0x42,0x00,0x02,
20840x14,0x40,0x00,0x15,0x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xeb,0x2c,0x42,0x00,0x02,
20850x14,0x40,0x00,0x11,0x24,0x0e,0x00,0x08,0x24,0x02,0x00,0x14,0x10,0x62,0x00,0x0e,
20860x24,0x0e,0x00,0x02,0x24,0x62,0xff,0xef,0x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,
20870x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xf1,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x06,
20880x24,0x0e,0x00,0x08,0x24,0x62,0xff,0xf3,0x2c,0x42,0x00,0x02,0x24,0x0e,0x00,0x04,
20890x24,0x03,0x00,0x02,0x00,0x62,0x70,0x0a,0x30,0xe2,0x00,0xff,0x00,0x00,0x48,0x21,
20900x00,0x00,0x68,0x21,0x10,0x40,0x00,0x6d,0x00,0x00,0x58,0x21,0x3c,0x14,0x80,0xff,
20910x27,0x99,0x8f,0xf0,0x01,0xf2,0xc0,0x23,0x36,0x94,0xff,0xff,0x01,0xc9,0x10,0x2a,
20920x14,0x40,0x00,0x64,0x24,0x03,0x00,0x04,0x00,0x10,0x28,0xc0,0x00,0xb0,0x10,0x21,
20930x00,0x02,0x10,0x80,0x00,0x59,0x10,0x21,0x94,0x56,0x00,0x06,0x00,0x00,0x00,0x00,
20940x32,0xcc,0x00,0x03,0x00,0x6c,0x10,0x23,0x30,0x42,0x00,0x03,0x02,0xc2,0x10,0x21,
20950x24,0x42,0x00,0x04,0x30,0x51,0xff,0xff,0x02,0x32,0x18,0x2b,0x10,0x60,0x00,0x4d,
20960x01,0xf1,0x10,0x23,0x02,0x51,0x10,0x23,0x01,0x78,0x18,0x2b,0x10,0x60,0x00,0x34,
20970x30,0x44,0xff,0xff,0x29,0x22,0x00,0x40,0x10,0x40,0x00,0x31,0x01,0x72,0x18,0x21,
20980x25,0x22,0x00,0x01,0x00,0x02,0x16,0x00,0x00,0x02,0x4e,0x03,0x00,0xb0,0x10,0x21,
20990x00,0x02,0x30,0x80,0x27,0x82,0x8f,0xf4,0x30,0x6b,0xff,0xff,0x00,0xc2,0x18,0x21,
21000x8c,0x67,0x00,0x18,0x00,0x04,0x25,0x40,0x3c,0x03,0x7f,0x00,0x8c,0xe2,0x00,0x04,
21010x00,0x83,0x20,0x24,0x27,0x83,0x90,0x00,0x00,0x54,0x10,0x24,0x00,0xc3,0x28,0x21,
21020x00,0x44,0x10,0x25,0xac,0xe2,0x00,0x04,0x16,0xe0,0x00,0x02,0xa0,0xb5,0x00,0x00,
21030xa0,0xb5,0x00,0x03,0x27,0x84,0x90,0x10,0x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x00,
21040x8c,0xe8,0x00,0x08,0x00,0x02,0x15,0xc2,0x00,0x08,0x47,0xc2,0x30,0x42,0x00,0x01,
21050x01,0x02,0x10,0x24,0x10,0x40,0x00,0x0a,0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x06,
21060x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,
21070x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,0x00,0xe2,0x50,0x21,0xa5,0x5e,0x00,0x00,
21080x92,0x62,0x00,0x04,0x25,0xad,0x00,0x01,0x27,0x84,0x8f,0xf0,0x00,0xc4,0x18,0x21,
21090x01,0xa2,0x10,0x2a,0x94,0x70,0x00,0x02,0x14,0x40,0xff,0xb8,0x00,0x00,0x00,0x00,
21100x96,0x63,0x00,0x14,0x00,0x0c,0x10,0x23,0xa2,0x69,0x00,0x12,0x30,0x42,0x00,0x03,
21110x01,0x62,0x10,0x23,0x00,0x03,0x80,0xc0,0x8f,0xa5,0x00,0x4c,0x30,0x4b,0xff,0xff,
21120x02,0x03,0x80,0x21,0x27,0x82,0x8f,0xf8,0x00,0x10,0x80,0x80,0xa6,0x6b,0x00,0x1a,
21130x02,0xa0,0x20,0x21,0x01,0x60,0x30,0x21,0x01,0x60,0x88,0x21,0x0c,0x00,0x08,0xdf,
21140x02,0x02,0x80,0x21,0x00,0x5e,0x10,0x21,0xa6,0x02,0x00,0x04,0x08,0x00,0x1f,0xdf,
21150x02,0x20,0x10,0x21,0x01,0x62,0x10,0x2b,0x10,0x40,0xff,0xe9,0x00,0x00,0x20,0x21,
21160x29,0x22,0x00,0x40,0x10,0x40,0xff,0xe6,0x01,0x71,0x18,0x21,0x08,0x00,0x20,0x55,
21170x25,0x22,0x00,0x01,0x08,0x00,0x20,0x84,0x32,0xcc,0x00,0x03,0x08,0x00,0x20,0x84,
21180x00,0x00,0x60,0x21,0x8f,0xa5,0x00,0x4c,0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,
21190x0c,0x00,0x09,0x06,0xaf,0xb4,0x00,0x14,0x92,0x67,0x00,0x04,0x08,0x00,0x1f,0xf7,
21200x30,0x5e,0xff,0xff,0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x20,0x21,
21210x00,0x04,0x20,0x80,0x27,0x82,0x8f,0xf0,0x3c,0x03,0xb0,0x08,0x30,0xa5,0xff,0xff,
21220x00,0x82,0x20,0x21,0x00,0xc3,0x30,0x21,0xac,0xc5,0x00,0x00,0x03,0xe0,0x00,0x08,
21230xa4,0x85,0x00,0x00,0x30,0x84,0xff,0xff,0x00,0x04,0x30,0xc0,0x00,0xc4,0x30,0x21,
21240x27,0x88,0x8f,0xf0,0x00,0x06,0x30,0x80,0x00,0xc8,0x30,0x21,0x94,0xc3,0x00,0x04,
21250x3c,0x02,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x03,0x20,0xc0,0x00,0x83,0x18,0x21,
21260x00,0x03,0x18,0x80,0x00,0x82,0x20,0x21,0x3c,0x02,0x80,0x01,0x30,0xa5,0xff,0xff,
21270x00,0x68,0x18,0x21,0x34,0xe7,0x00,0x20,0x24,0x42,0x82,0xe4,0xac,0xe2,0x00,0x00,
21280xa4,0xc5,0x00,0x02,0xa4,0x65,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x00,
21290x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0x83,0x40,
21300xac,0x43,0x00,0x00,0x90,0x82,0x00,0x10,0x3c,0x08,0xb0,0x03,0x3c,0x09,0xb0,0x06,
21310x27,0x87,0x8f,0xf0,0x3c,0x0d,0xb0,0x08,0x34,0x0e,0xff,0xff,0x35,0x08,0x00,0x62,
21320x00,0x80,0x30,0x21,0x24,0x0c,0xff,0xff,0x10,0x40,0x00,0x2c,0x35,0x29,0x80,0x20,
21330x97,0x82,0x8f,0xe0,0x94,0x85,0x00,0x0c,0x3c,0x0b,0xb0,0x03,0x00,0x02,0x18,0xc0,
21340x00,0x62,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0xa4,0x45,0x00,0x00,
21350x94,0x84,0x00,0x0e,0x00,0x6d,0x18,0x21,0xac,0x65,0x00,0x00,0x00,0x04,0x10,0xc0,
21360x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0x94,0x45,0x00,0x04,
21370x3c,0x0a,0x77,0x77,0x35,0x6b,0x00,0xb4,0x00,0x05,0x10,0xc0,0x00,0x45,0x18,0x21,
21380x00,0x03,0x18,0x80,0x00,0x67,0x18,0x21,0x00,0x4d,0x10,0x21,0xac,0x4e,0x00,0x00,
21390xa4,0x6e,0x00,0x00,0x95,0x04,0x00,0x00,0x90,0xc3,0x00,0x10,0x24,0x02,0x00,0xff,
21400x00,0x44,0x10,0x23,0x00,0x43,0x10,0x2a,0xa7,0x85,0x8f,0xe0,0x10,0x40,0x00,0x04,
21410x35,0x4a,0x88,0x88,0xad,0x6a,0x00,0x00,0x90,0xc3,0x00,0x10,0x00,0x00,0x00,0x00,
21420x30,0x63,0x00,0xff,0x3c,0x02,0x00,0x40,0x00,0x62,0x18,0x25,0xad,0x23,0x00,0x00,
21430xa4,0xcc,0x00,0x0e,0xa4,0xcc,0x00,0x0c,0xa0,0xc0,0x00,0x10,0x03,0xe0,0x00,0x08,
21440x00,0x00,0x00,0x00,0x30,0x84,0xff,0xff,0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,
21450x27,0x89,0x8f,0xf0,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,0x97,0x83,0x8f,0xe0,
21460x94,0x4a,0x00,0x04,0x3c,0x02,0xb0,0x08,0x00,0x03,0x38,0xc0,0x00,0x0a,0x40,0xc0,
21470x00,0xe3,0x18,0x21,0x01,0x0a,0x28,0x21,0x00,0xe2,0x38,0x21,0x01,0x02,0x40,0x21,
21480x00,0x03,0x18,0x80,0x00,0x05,0x28,0x80,0x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x01,
21490x00,0xa9,0x28,0x21,0x00,0x69,0x18,0x21,0x34,0xc6,0x00,0x20,0x34,0x09,0xff,0xff,
21500x24,0x42,0x84,0x34,0xac,0xc2,0x00,0x00,0xa4,0x64,0x00,0x00,0xac,0xe4,0x00,0x00,
21510xa4,0xa9,0x00,0x00,0xad,0x09,0x00,0x00,0xa7,0x8a,0x8f,0xe0,0x03,0xe0,0x00,0x08,
21520x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,
21530x24,0x42,0x84,0xb4,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x01,0x10,
21540x8c,0x82,0x00,0x00,0x97,0x83,0x81,0x60,0x30,0x42,0xff,0xff,0x10,0x62,0x00,0x16,
21550x24,0x0a,0x00,0x01,0xa7,0x82,0x81,0x60,0xaf,0x80,0xb4,0x40,0x00,0x40,0x28,0x21,
21560x24,0x06,0x00,0x01,0x27,0x84,0xb4,0x44,0x25,0x43,0xff,0xff,0x00,0x66,0x10,0x04,
21570x00,0xa2,0x10,0x24,0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x8c,0x83,0xff,0xfc,
21580x00,0x00,0x00,0x00,0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,0x38,0x42,0x00,0x00,
21590x01,0x42,0x18,0x0a,0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x14,0xac,0x83,0x00,0x00,
21600x14,0x40,0xff,0xf1,0x24,0x84,0x00,0x04,0x3c,0x0b,0xb0,0x03,0x00,0x00,0x50,0x21,
21610x3c,0x0c,0x80,0x00,0x27,0x89,0xb4,0x90,0x35,0x6b,0x01,0x20,0x8d,0x68,0x00,0x00,
21620x8d,0x23,0x00,0x04,0x01,0x0c,0x10,0x24,0x00,0x02,0x17,0xc2,0x11,0x03,0x00,0x37,
21630xa1,0x22,0x00,0xdc,0xa1,0x20,0x00,0xd5,0xa1,0x20,0x00,0xd6,0x01,0x20,0x30,0x21,
21640x00,0x00,0x38,0x21,0x00,0x00,0x28,0x21,0x01,0x20,0x20,0x21,0x00,0xa8,0x10,0x06,
21650x30,0x42,0x00,0x01,0x10,0xe0,0x00,0x10,0xa0,0x82,0x00,0x0a,0x90,0x82,0x00,0x07,
21660x00,0x00,0x00,0x00,0x10,0x40,0x00,0x31,0x24,0xa2,0xff,0xff,0xa0,0x82,0x00,0x08,
21670x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09,0x00,0x00,0x00,0x00,
21680x90,0x83,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x40,0x00,0x43,0x10,0x21,
21690x00,0x46,0x10,0x21,0xa0,0x45,0x00,0x09,0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,
21700x10,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x04,0x00,0x00,0x00,0x00,
21710xa0,0xc5,0x00,0xd5,0x24,0x07,0x00,0x01,0xa0,0x85,0x00,0x08,0xa0,0xc5,0x00,0xd6,
21720x24,0xa5,0x00,0x01,0x2c,0xa2,0x00,0x1c,0x14,0x40,0xff,0xe0,0x24,0x84,0x00,0x03,
21730x90,0xc4,0x00,0xd5,0x00,0x00,0x28,0x21,0x00,0xa4,0x10,0x2b,0x10,0x40,0x00,0x0b,
21740x00,0x00,0x00,0x00,0x00,0xc0,0x18,0x21,0xa0,0x64,0x00,0x08,0x90,0xc2,0x00,0xd5,
21750x24,0xa5,0x00,0x01,0xa0,0x62,0x00,0x09,0x90,0xc4,0x00,0xd5,0x00,0x00,0x00,0x00,
21760x00,0xa4,0x10,0x2b,0x14,0x40,0xff,0xf8,0x24,0x63,0x00,0x03,0x25,0x4a,0x00,0x01,
21770x2d,0x42,0x00,0x08,0xad,0x28,0x00,0x04,0x25,0x6b,0x00,0x04,0x14,0x40,0xff,0xbf,
21780x25,0x29,0x00,0xec,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x05,
21790x08,0x00,0x21,0x68,0xa0,0x82,0x00,0x08,0x97,0x85,0x8b,0x6a,0x3c,0x03,0xb0,0x03,
21800x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0x86,0x68,
21810xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x62,0x00,0x00,0x30,0x90,0x00,0xff,
21820x00,0x05,0x28,0x42,0x00,0x00,0x48,0x21,0x27,0x8f,0xb4,0x94,0x00,0x00,0x50,0x21,
21830x00,0x00,0x58,0x21,0x27,0x98,0xb5,0x74,0x27,0x99,0xb5,0x70,0x27,0x8e,0xb5,0x6e,
21840x27,0x8c,0xb4,0x98,0x27,0x8d,0xb4,0xf0,0x27,0x88,0xb5,0x68,0x00,0x0a,0x18,0x80,
21850x01,0x6f,0x10,0x21,0xac,0x40,0x00,0x00,0xac,0x45,0x00,0x58,0x00,0x6e,0x20,0x21,
21860x00,0x78,0x10,0x21,0xa1,0x00,0xff,0xfc,0xad,0x00,0x00,0x00,0xa1,0x00,0x00,0x04,
21870xa1,0x00,0x00,0x05,0xad,0x00,0xff,0xf8,0x00,0x79,0x18,0x21,0x24,0x06,0x00,0x01,
21880x24,0xc6,0xff,0xff,0xa0,0x80,0x00,0x00,0xa4,0x60,0x00,0x00,0xac,0x40,0x00,0x00,
21890x24,0x63,0x00,0x02,0x24,0x42,0x00,0x04,0x04,0xc1,0xff,0xf9,0x24,0x84,0x00,0x01,
21900x00,0x0a,0x10,0x80,0x00,0x4d,0x20,0x21,0x00,0x00,0x30,0x21,0x00,0x4c,0x18,0x21,
21910x27,0x87,0x81,0x64,0x8c,0xe2,0x00,0x00,0x24,0xe7,0x00,0x04,0xac,0x82,0x00,0x00,
21920xa0,0x66,0x00,0x00,0xa0,0x66,0x00,0x01,0x24,0xc6,0x00,0x01,0x28,0xc2,0x00,0x1c,
21930xa0,0x60,0x00,0x02,0x24,0x84,0x00,0x04,0x14,0x40,0xff,0xf6,0x24,0x63,0x00,0x03,
21940x25,0x29,0x00,0x01,0x29,0x22,0x00,0x08,0x25,0x4a,0x00,0x3b,0x25,0x08,0x00,0xec,
21950x14,0x40,0xff,0xd6,0x25,0x6b,0x00,0xec,0xa7,0x80,0x81,0x60,0x00,0x00,0x48,0x21,
21960x27,0x83,0xb4,0x40,0xac,0x69,0x00,0x00,0x25,0x29,0x00,0x01,0x29,0x22,0x00,0x0c,
21970x14,0x40,0xff,0xfc,0x24,0x63,0x00,0x04,0x0c,0x00,0x21,0x2d,0x00,0x00,0x00,0x00,
21980x2e,0x04,0x00,0x14,0x27,0x83,0xb4,0x90,0x24,0x09,0x00,0x07,0x10,0x80,0x00,0x0a,
21990x00,0x00,0x00,0x00,0x90,0x62,0x00,0xd5,0x25,0x29,0xff,0xff,0xa0,0x62,0x00,0x00,
22000x05,0x21,0xff,0xfa,0x24,0x63,0x00,0xec,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
22010x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x90,0x62,0x00,0xd6,0x08,0x00,0x21,0xeb,
22020x25,0x29,0xff,0xff,0x30,0x84,0x00,0xff,0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,
22030x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xb4,0x90,
22040x00,0x43,0x60,0x21,0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x84,0x00,0x20,
22050x24,0x42,0x87,0xd4,0x30,0xc6,0x00,0xff,0x93,0xa9,0x00,0x13,0x30,0xa5,0x00,0xff,
22060x30,0xe7,0x00,0xff,0xac,0x82,0x00,0x00,0x10,0xc0,0x00,0xeb,0x25,0x8f,0x00,0xd0,
22070x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xfc,0x2c,0x43,0x00,0x18,
22080x10,0x60,0x00,0xcf,0x3c,0x03,0x80,0x01,0x00,0x02,0x10,0x80,0x24,0x63,0x02,0x5c,
22090x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,
22100x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x2d,0x10,0x40,0x00,0x14,0x00,0x00,0x00,0x00,
22110x10,0xa0,0x00,0x0f,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x09,
22120x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,
22130x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xd0,0x03,0xe0,0x00,0x08,
22140xad,0x82,0x00,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0xff,0xe0,
22150x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0x00,0x01,0x10,0xa0,0x00,0x0f,
22160x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xf9,0x00,0x00,0x00,0x00,
22170x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x07,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,
22180x14,0xa2,0xff,0xf0,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,
22190x24,0x42,0xff,0xe8,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
22200x08,0x00,0x22,0x23,0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xfc,0x00,0x00,0x00,0x00,
22210x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xe6,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
22220x10,0xa2,0xff,0xf4,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xef,0x00,0x00,0x00,0x00,
22230x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0xff,0xf8,0x2d,0x22,0x00,0x19,
22240x14,0x40,0xff,0xde,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xec,0x00,0x00,0x00,0x00,
22250x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
22260x10,0xa2,0xff,0xe4,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,
22270x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0xff,0xf0,0x2d,0x22,0x00,0x1b,
22280x10,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdc,0x00,0x00,0x00,0x00,
22290x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xc6,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
22300x14,0xa2,0xff,0xce,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,
22310x24,0x42,0xff,0xf4,0x2d,0x22,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00,
22320x10,0xa0,0xff,0xce,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xc9,
22330x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x34,
22340x24,0x02,0x00,0x03,0x2d,0x22,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,
22350x10,0xa0,0xff,0xaf,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xbd,
22360x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xda,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,
22370x14,0xa2,0xff,0x9f,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x25,0x00,0x00,0x00,0x00,
22380x2d,0x22,0x00,0x25,0x10,0x40,0xff,0xc8,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa0,
22390x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,
22400x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x97,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x80,
22410x24,0x02,0x00,0x03,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0xff,0xfc,
22420x2d,0x22,0x00,0x16,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa3,
22430x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8d,0x00,0x00,0x00,0x00,
22440x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x9b,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xa8,
22450x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0x23,0x24,0x42,0xff,0xfa,
22460x10,0xa0,0xff,0x96,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x80,
22470x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x8e,0x00,0x00,0x00,0x00,
22480x08,0x00,0x22,0x48,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x17,0x14,0x40,0xff,0x9e,
22490x00,0x00,0x00,0x00,0x08,0x00,0x22,0x97,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x19,
22500x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x84,0x00,0x00,0x00,0x00,
22510x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x6e,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
22520x10,0xa2,0xff,0x7c,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x89,0x00,0x00,0x00,0x00,
22530x08,0x00,0x22,0x25,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xb4,0x2d,0x22,0x00,0x1b,
22540x2d,0x22,0x00,0x1e,0x10,0x40,0xff,0xde,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x73,
22550x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x5d,0x00,0x00,0x00,0x00,
22560x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x6b,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x88,
22570x00,0x00,0x00,0x00,0x08,0x00,0x22,0x25,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x23,
22580x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x4e,0x00,0x00,0x00,0x00,
22590x08,0x00,0x22,0x4c,0x2d,0x22,0x00,0x25,0x08,0x00,0x22,0x85,0x2d,0x22,0x00,0x27,
22600x10,0xa0,0xff,0x5e,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x48,
22610x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x56,0x24,0x02,0x00,0x03,
22620x14,0xa2,0xff,0x63,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x91,0x00,0x00,0x00,0x00,
22630x2d,0x22,0x00,0x27,0x14,0x40,0xff,0x8e,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x3e,
22640x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x29,0x14,0x40,0xff,0x89,0x00,0x00,0x00,0x00,
22650x08,0x00,0x22,0x2b,0x00,0x00,0x00,0x00,0x91,0x86,0x00,0x00,0x91,0x83,0x00,0xd4,
22660x25,0x8d,0x00,0x5c,0x30,0xc4,0x00,0xff,0x00,0x04,0x10,0x40,0x00,0x44,0x10,0x21,
22670x00,0x04,0x50,0x80,0x01,0x82,0x58,0x21,0x01,0x8a,0x40,0x21,0x25,0x78,0x00,0x08,
22680x10,0x60,0x00,0x37,0x25,0x0e,0x00,0x60,0x2c,0xa2,0x00,0x03,0x14,0x40,0x00,0x25,
22690x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1e,
22700x00,0x00,0x00,0x00,0x27,0x87,0x81,0x64,0x01,0x47,0x10,0x21,0x8c,0x43,0x00,0x00,
22710x00,0x00,0x00,0x00,0xad,0x03,0x00,0x60,0x91,0x62,0x00,0x08,0x00,0x00,0x00,0x00,
22720x00,0x40,0x30,0x21,0xa1,0x82,0x00,0x00,0x30,0xc2,0x00,0xff,0x00,0x02,0x10,0x80,
22730x00,0x47,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x18,0x42,
22740xad,0xa3,0x00,0x00,0x91,0x84,0x00,0x00,0x8d,0xc5,0x00,0x00,0x00,0x04,0x20,0x80,
22750x00,0x87,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x05,0x28,0x40,0x00,0x8c,0x20,0x21,
22760x00,0x03,0x18,0x80,0x00,0xa3,0x10,0x2b,0x00,0x62,0x28,0x0a,0xac,0x85,0x00,0x60,
22770x03,0xe0,0x00,0x08,0xa1,0x80,0x00,0xd4,0x27,0x87,0x81,0x64,0x08,0x00,0x23,0x0e,
22780xa1,0x80,0x00,0xdd,0x27,0x82,0x81,0xd4,0x8d,0x83,0x00,0xd8,0x00,0x82,0x10,0x21,
22790x90,0x44,0x00,0x00,0x24,0x63,0x00,0x01,0x00,0x64,0x20,0x2b,0x14,0x80,0xff,0x0d,
22800xad,0x83,0x00,0xd8,0x8d,0x02,0x00,0x60,0xa1,0x80,0x00,0xd4,0x00,0x02,0x1f,0xc2,
22810x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x03,0xe0,0x00,0x08,0xad,0x82,0x00,0x5c,
22820x10,0xe0,0x00,0x1a,0x24,0x83,0xff,0xfc,0x2c,0x62,0x00,0x18,0x10,0x40,0x01,0x18,
22830x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,0x24,0x63,0x02,0xbc,0x00,0x43,0x10,0x21,
22840x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,
22850x2d,0x22,0x00,0x2d,0x10,0x40,0x00,0x5f,0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x5a,
22860x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x54,0x00,0x00,0x00,0x00,
22870x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x51,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
22880x00,0x00,0x00,0x00,0x24,0x42,0xff,0xd0,0xad,0x82,0x00,0xd0,0x8d,0xe3,0x00,0x00,
22890x8d,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xad,0xa2,0x00,0x00,
22900xad,0xe0,0x00,0x00,0x8d,0xa3,0x00,0x00,0x8d,0xc4,0x00,0x00,0x00,0x00,0x00,0x00,
22910x00,0x83,0x10,0x2a,0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00,0x93,0x05,0x00,0x01,
22920x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x05,0x24,0x02,0x00,0x01,
22930xa1,0x85,0x00,0x00,0xa1,0x82,0x00,0xd4,0x03,0xe0,0x00,0x08,0xad,0x80,0x00,0xd8,
22940x91,0x82,0x00,0xdd,0x24,0x03,0x00,0x01,0x10,0x43,0x00,0x05,0x00,0x00,0x00,0x00,
22950xa1,0x83,0x00,0xd4,0xad,0x80,0x00,0xd8,0x03,0xe0,0x00,0x08,0xa1,0x83,0x00,0xdd,
22960x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43,0xad,0xa2,0x00,0x00,
22970x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64,0x8d,0xc5,0x00,0x00,0x00,0x03,0x18,0x80,
22980x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40,0x00,0x04,0x18,0x80,
22990x00,0xa3,0x10,0x2b,0x00,0x62,0x28,0x0a,0x08,0x00,0x23,0x20,0xad,0xc5,0x00,0x00,
23000x97,0x82,0x8b,0x6c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x2a,0x10,0x40,0xfe,0xb9,
23010x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x15,
23020x00,0x00,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64,0x00,0x03,0x18,0x80,
23030x00,0x62,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x6c,0x18,0x21,0xac,0x64,0x00,0x60,
23040x93,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x10,0x80,0x01,0x82,0x10,0x21,
23050x24,0x4e,0x00,0x60,0xa1,0x85,0x00,0x00,0x8d,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,
23060x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x03,0xe0,0x00,0x08,
23070xad,0xa2,0x00,0x00,0x08,0x00,0x23,0x92,0xa1,0x80,0x00,0xdd,0x8d,0x82,0x00,0xd0,
23080x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xe0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,
23090x24,0x42,0x00,0x01,0x10,0xa0,0x00,0x0d,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
23100x10,0xa2,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xa7,
23110x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xf0,0x00,0x00,0x00,0x00,
23120x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xe8,0x8d,0x82,0x00,0xd0,
23130x08,0x00,0x23,0x4e,0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xfc,0x00,0x00,0x00,0x00,
23140x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xe8,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
23150x10,0xa2,0xff,0x96,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,
23160x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xf8,0x2d,0x22,0x00,0x19,
23170x14,0x40,0xff,0xe0,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xec,0x00,0x00,0x00,0x00,
23180x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xd8,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
23190x10,0xa2,0xff,0x86,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,
23200x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xf0,0x2d,0x22,0x00,0x1b,
23210x10,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdc,0x00,0x00,0x00,0x00,
23220x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xc8,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
23230x14,0xa2,0xff,0xd0,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,
23240x24,0x42,0xff,0xf4,0x2d,0x22,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00,
23250x10,0xa0,0xff,0xce,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x6b,
23260x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xaa,
23270x24,0x02,0x00,0x03,0x2d,0x22,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,
23280x10,0xa0,0xff,0xb1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x5f,
23290x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xda,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,
23300x14,0xa2,0xff,0x56,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x9b,0x00,0x00,0x00,0x00,
23310x2d,0x22,0x00,0x25,0x10,0x40,0xff,0xc8,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa2,
23320x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,
23330x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x99,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xf4,
23340x24,0x02,0x00,0x03,0x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xfc,
23350x2d,0x22,0x00,0x16,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa3,
23360x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8f,0x00,0x00,0x00,0x00,
23370x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x3d,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xa8,
23380x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x23,0x4e,0x24,0x42,0xff,0xfa,
23390x10,0xa0,0xff,0x96,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x82,
23400x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x30,0x00,0x00,0x00,0x00,
23410x08,0x00,0x23,0xbc,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x17,0x14,0x40,0xff,0x9e,
23420x00,0x00,0x00,0x00,0x08,0x00,0x24,0x0b,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x19,
23430x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x84,0x00,0x00,0x00,0x00,
23440x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x70,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
23450x10,0xa2,0xff,0x1e,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x89,0x00,0x00,0x00,0x00,
23460x08,0x00,0x23,0x9b,0x00,0x00,0x00,0x00,0x08,0x00,0x24,0x28,0x2d,0x22,0x00,0x1b,
23470x2d,0x22,0x00,0x1e,0x10,0x40,0xff,0xde,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x73,
23480x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x5f,0x00,0x00,0x00,0x00,
23490x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x0d,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x88,
23500x00,0x00,0x00,0x00,0x08,0x00,0x23,0x9b,0x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x23,
23510x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xc2,0x00,0x00,0x00,0x00,
23520x08,0x00,0x23,0xc0,0x2d,0x22,0x00,0x25,0x08,0x00,0x23,0xf9,0x2d,0x22,0x00,0x27,
23530x10,0xa0,0xff,0x5e,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x4a,
23540x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xfe,0xf8,0x24,0x02,0x00,0x03,
23550x14,0xa2,0xff,0x63,0x00,0x00,0x00,0x00,0x08,0x00,0x24,0x05,0x00,0x00,0x00,0x00,
23560x2d,0x22,0x00,0x27,0x14,0x40,0xff,0x8e,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xb2,
23570x00,0x00,0x00,0x00,0x2d,0x22,0x00,0x29,0x14,0x40,0xff,0x89,0x00,0x00,0x00,0x00,
23580x08,0x00,0x23,0xa1,0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0x3c,0x02,0xb0,0x03,
23590xaf,0xbf,0x00,0x14,0xaf,0xb0,0x00,0x10,0x34,0x42,0x01,0x18,0x3c,0x03,0xb0,0x03,
23600x8c,0x50,0x00,0x00,0x34,0x63,0x01,0x2c,0x90,0x62,0x00,0x00,0x32,0x05,0x00,0x01,
23610xa3,0x82,0x80,0x10,0x14,0xa0,0x00,0x14,0x30,0x44,0x00,0xff,0x32,0x02,0x01,0x00,
23620x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x32,0x02,0x08,0x00,0x10,0x40,0x00,0x02,
23630x24,0x02,0x00,0x01,0xa3,0x82,0xbc,0x08,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
23640x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x05,0x39,0x00,0x00,0x00,0x00,
23650x26,0x02,0xff,0x00,0xa3,0x80,0xbc,0x08,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,
23660x08,0x00,0x24,0x77,0x32,0x02,0x08,0x00,0x0c,0x00,0x21,0x9a,0x00,0x00,0x00,0x00,
23670x26,0x02,0xff,0xff,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x24,0x74,
23680x32,0x02,0x01,0x00,0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,
23690xaf,0xbf,0x00,0x18,0x8c,0x43,0x00,0x00,0x3c,0x02,0x00,0x40,0x24,0x07,0x0f,0xff,
23700x00,0x03,0x33,0x02,0x00,0x03,0x2d,0x02,0x00,0x03,0x43,0x02,0x30,0x69,0x0f,0xff,
23710x00,0x62,0x18,0x24,0x30,0xa5,0x00,0x03,0x30,0xc6,0x00,0xff,0x10,0x60,0x00,0x08,
23720x31,0x08,0x00,0xff,0x01,0x00,0x30,0x21,0x0c,0x00,0x25,0x38,0xaf,0xa9,0x00,0x10,
23730x8f,0xbf,0x00,0x18,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
23740x0c,0x00,0x25,0x8a,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xd4,
23750x08,0x00,0x24,0xa0,0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,0xaf,0xb6,0x00,0x30,
23760xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x3c,
23770xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,
23780xaf,0xb2,0x00,0x20,0x0c,0x00,0x17,0xc8,0x00,0x80,0x80,0x21,0x00,0x00,0xb0,0x21,
23790x00,0x00,0x88,0x21,0x10,0x40,0x00,0x12,0x00,0x00,0x98,0x21,0x3c,0x02,0xb0,0x03,
23800x3c,0x03,0xb0,0x03,0x3c,0x04,0xb0,0x03,0x24,0x05,0x00,0x01,0x34,0x42,0x00,0xbc,
23810x34,0x63,0x00,0xbb,0x34,0x84,0x00,0xba,0xa4,0x40,0x00,0x00,0xa0,0x65,0x00,0x00,
23820xa0,0x85,0x00,0x00,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,
23830x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,
23840x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x47,0x90,0x44,0x00,0x00,0x00,0x10,0x1a,0x02,
23850x3c,0x15,0xfd,0xff,0x30,0x84,0x00,0xff,0xa0,0x50,0x00,0x00,0x30,0x74,0x00,0x0f,
23860xaf,0xa4,0x00,0x10,0x00,0x00,0x90,0x21,0x3c,0x17,0x02,0x00,0x36,0xb5,0xff,0xff,
23870x3c,0x1e,0xb0,0x03,0x0c,0x00,0x06,0xce,0x24,0x04,0x04,0x00,0x00,0x57,0x10,0x25,
23880x00,0x40,0x28,0x21,0x0c,0x00,0x06,0xc1,0x24,0x04,0x04,0x00,0x00,0x00,0x80,0x21,
23890x0c,0x00,0x26,0x52,0x00,0x00,0x00,0x00,0x26,0x03,0x00,0x01,0x30,0x70,0x00,0xff,
23900x10,0x40,0x00,0x47,0x2e,0x03,0x00,0x02,0x14,0x60,0xff,0xf9,0x00,0x00,0x00,0x00,
23910x0c,0x00,0x06,0xce,0x24,0x04,0x04,0x00,0x00,0x55,0x10,0x24,0x00,0x40,0x28,0x21,
23920x0c,0x00,0x06,0xc1,0x24,0x04,0x04,0x00,0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x38,
23930x00,0x00,0x00,0x00,0x12,0x80,0x00,0x36,0x00,0x00,0x00,0x00,0x32,0x22,0x00,0x60,
23940x32,0x23,0x0c,0x00,0x00,0x03,0x1a,0x02,0x3c,0x05,0x00,0x60,0x00,0x02,0x11,0x42,
23950x02,0x25,0x20,0x24,0x00,0x43,0x10,0x25,0x3c,0x03,0x04,0x00,0x02,0x23,0x28,0x24,
23960x00,0x04,0x24,0x42,0x00,0x44,0x10,0x25,0x00,0x05,0x2d,0x02,0x00,0x45,0x88,0x25,
23970x12,0x20,0x00,0x05,0x26,0x42,0x00,0x01,0x26,0xc2,0x00,0x01,0x30,0x56,0x00,0xff,
23980x02,0x71,0x98,0x21,0x26,0x42,0x00,0x01,0x02,0x5e,0x20,0x21,0x30,0x52,0x00,0xff,
23990x2e,0x43,0x00,0x05,0xa0,0x91,0x00,0xd8,0x14,0x60,0xff,0xce,0x3c,0x02,0xb0,0x03,
24000x8f,0xa5,0x00,0x10,0x34,0x42,0x01,0x47,0xa0,0x45,0x00,0x00,0x12,0x60,0x00,0x0e,
24010x3c,0x02,0xb0,0x03,0x12,0xc0,0x00,0x0d,0x34,0x42,0x00,0xbc,0x00,0x13,0x10,0x40,
24020x00,0x53,0x10,0x21,0x00,0x02,0x10,0xc0,0x00,0x53,0x10,0x21,0x00,0x02,0x98,0x80,
24030x02,0x76,0x00,0x1b,0x16,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,
24040x00,0x00,0x98,0x12,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xbc,0x3c,0x03,0xb0,0x03,
24050x3c,0x04,0xb0,0x03,0xa4,0x53,0x00,0x00,0x34,0x63,0x00,0xbb,0x34,0x84,0x00,0xba,
24060x24,0x02,0x00,0x01,0xa0,0x60,0x00,0x00,0x08,0x00,0x24,0xc5,0xa0,0x82,0x00,0x00,
24070x0c,0x00,0x06,0xce,0x24,0x04,0x04,0xfc,0x08,0x00,0x24,0xf3,0x00,0x40,0x88,0x21,
24080x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xbc,0x3c,0x04,0xb0,0x03,0x3c,0x05,0xb0,0x03,
24090xa4,0x60,0x00,0x00,0x34,0x84,0x00,0xbb,0x34,0xa5,0x00,0xba,0x24,0x02,0x00,0x02,
24100x24,0x03,0x00,0x01,0xa0,0x82,0x00,0x00,0x08,0x00,0x24,0xc5,0xa0,0xa3,0x00,0x00,
24110x27,0xbd,0xff,0xd8,0xaf,0xb0,0x00,0x10,0x30,0xd0,0x00,0xff,0x2e,0x02,0x00,0x2e,
24120xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,
24130x30,0xb1,0x00,0xff,0x14,0x40,0x00,0x06,0x00,0x80,0x90,0x21,0x8f,0xbf,0x00,0x20,
24140x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
24150x2e,0x13,0x00,0x10,0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa0,0x24,0x06,0x01,0x07,
24160x12,0x60,0x00,0x38,0x02,0x00,0x30,0x21,0x8f,0xa2,0x00,0x38,0x30,0xc3,0x00,0x3f,
24170x3c,0x04,0xb0,0x09,0x00,0x02,0x14,0x00,0x00,0x43,0x30,0x25,0x34,0x84,0x01,0x60,
24180x90,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x24,0x02,0x00,0x01,
24190x12,0x22,0x00,0x2a,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x24,0x24,0x02,0x00,0x02,
24200x12,0x22,0x00,0x20,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x19,0x00,0x00,0x00,0x00,
24210x16,0x60,0xff,0xe2,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x13,0x2a,0x22,0x00,0x02,
24220x14,0x40,0x00,0x0d,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,
24230x16,0x22,0xff,0xda,0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,
24240x0c,0x00,0x13,0x5b,0x3c,0x06,0x0c,0xb8,0x08,0x00,0x25,0x43,0x00,0x00,0x00,0x00,
24250x08,0x00,0x25,0x6b,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xd0,0x00,0x00,0x00,0x00,
24260x08,0x00,0x25,0x6b,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x6b,0x24,0x04,0x08,0x44,
24270x24,0x04,0x08,0x4c,0x0c,0x00,0x13,0x5b,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0x60,
24280x00,0x00,0x00,0x00,0x08,0x00,0x25,0x79,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xe0,
24290x00,0x00,0x00,0x00,0x08,0x00,0x25,0x79,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x79,
24300x24,0x04,0x08,0x44,0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0xca,0x02,0x20,0x28,0x21,
24310x08,0x00,0x25,0x4e,0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xd8,0x2c,0xc2,0x00,0x2e,
24320xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,
24330xaf,0xb3,0x00,0x1c,0x00,0xc0,0x80,0x21,0x30,0xb1,0x00,0xff,0x00,0x80,0x90,0x21,
24340x14,0x40,0x00,0x07,0x00,0x00,0x18,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,
24350x7b,0xb0,0x00,0xbc,0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
24360x2e,0x13,0x00,0x10,0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa0,0x24,0x06,0x01,0x07,
24370x12,0x60,0x00,0x24,0x02,0x00,0x30,0x21,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,
24380x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x30,0xc5,0x00,0x3f,
24390x0c,0x00,0x26,0x07,0x02,0x20,0x20,0x21,0x16,0x60,0x00,0x0a,0x00,0x40,0x80,0x21,
24400x24,0x02,0x00,0x01,0x12,0x22,0x00,0x15,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0f,
24410x24,0x02,0x00,0x02,0x12,0x22,0x00,0x0b,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x03,
24420x00,0x00,0x00,0x00,0x08,0x00,0x25,0x96,0x02,0x00,0x18,0x21,0x24,0x04,0x08,0x4c,
24430x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5b,0x3c,0x06,0x0c,0xb8,0x08,0x00,0x25,0x96,
24440x02,0x00,0x18,0x21,0x08,0x00,0x25,0xb8,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xf5,
24450x00,0x00,0x00,0x00,0x08,0x00,0x25,0xb8,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0xb8,
24460x24,0x04,0x08,0x44,0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0xca,0x02,0x20,0x28,0x21,
24470x08,0x00,0x25,0xa2,0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xe8,0x2c,0xc2,0x00,0x1f,
24480xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0x00,0xc0,0x80,0x21,0x14,0x40,0x00,0x1d,
24490x30,0xa5,0x00,0xff,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x18,0x28,0xa2,0x00,0x02,
24500x14,0x40,0x00,0x12,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0e,0x24,0x02,0x00,0x03,
24510x10,0xa2,0x00,0x07,0x24,0x04,0x08,0x4c,0x26,0x10,0xff,0xe2,0x02,0x00,0x10,0x21,
24520x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
24530x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5b,0x3c,0x06,0x0d,0xf8,0x08,0x00,0x25,0xdb,
24540x26,0x10,0xff,0xe2,0x08,0x00,0x25,0xe0,0x24,0x04,0x08,0x48,0x14,0xa0,0xff,0xf2,
24550x24,0x04,0x08,0x40,0x08,0x00,0x25,0xe1,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0xe0,
24560x24,0x04,0x08,0x44,0x2c,0xc2,0x00,0x10,0x14,0x40,0xff,0xec,0x24,0x02,0x00,0x01,
24570x10,0xa2,0x00,0x14,0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x0e,0x24,0x02,0x00,0x02,
24580x10,0xa2,0x00,0x0a,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x03,0x24,0x04,0x08,0x4c,
24590x08,0x00,0x25,0xdb,0x26,0x10,0xff,0xf1,0x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5b,
24600x3c,0x06,0x0d,0xb8,0x08,0x00,0x25,0xdb,0x26,0x10,0xff,0xf1,0x08,0x00,0x25,0xfa,
24610x24,0x04,0x08,0x48,0x14,0xa0,0xff,0xf6,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0xfb,
24620x24,0x05,0xff,0xff,0x08,0x00,0x25,0xfa,0x24,0x04,0x08,0x44,0x27,0xbd,0xff,0xe8,
24630x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x39,0xaf,0xbf,0x00,0x10,
24640x28,0x82,0x00,0x02,0x14,0x40,0x00,0x27,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
24650x10,0x82,0x00,0x17,0x00,0xa0,0x30,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x05,
24660x24,0x04,0x08,0x3c,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
24670x27,0xbd,0x00,0x18,0x0c,0x00,0x13,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x3c,
24680x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x3c,
24690x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,0x24,0x04,0x08,0xac,
24700x0c,0x00,0x13,0x3d,0x24,0x05,0x0f,0xff,0x08,0x00,0x26,0x15,0x00,0x00,0x00,0x00,
24710x24,0x04,0x08,0x34,0x0c,0x00,0x13,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x34,
24720x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x34,
24730x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,0x08,0x00,0x26,0x24,
24740x24,0x04,0x08,0xa8,0x14,0x80,0xff,0xdf,0x00,0xa0,0x30,0x21,0x24,0x04,0x08,0x24,
24750x0c,0x00,0x13,0x5b,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,
24760x0c,0x00,0x13,0x5b,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,
24770x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,0x08,0x00,0x26,0x24,0x24,0x04,0x08,0xa0,
24780x00,0xa0,0x30,0x21,0x24,0x04,0x08,0x2c,0x0c,0x00,0x13,0x5b,0x3c,0x05,0x3f,0x00,
24790x24,0x04,0x08,0x2c,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x00,0x00,0x30,0x21,
24800x24,0x04,0x08,0x2c,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5b,0x24,0x06,0x00,0x01,
24810x08,0x00,0x26,0x24,0x24,0x04,0x08,0xa4,0x3c,0x05,0x00,0x14,0x3c,0x02,0xb0,0x05,
24820x34,0x42,0x04,0x20,0x3c,0x06,0xc0,0x00,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,
24830x34,0xa5,0x17,0x09,0xac,0x45,0x00,0x00,0x34,0xc6,0x05,0x07,0x34,0x63,0x04,0x24,
24840x34,0x84,0x02,0x28,0x3c,0x07,0xb0,0x05,0x24,0x02,0x00,0x20,0xac,0x66,0x00,0x00,
24850x34,0xe7,0x04,0x50,0xa0,0x82,0x00,0x00,0x90,0xe2,0x00,0x00,0x00,0x00,0x00,0x00,
24860x30,0x42,0x00,0x03,0x10,0x40,0xff,0xfc,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,
24870x00,0x00,0x00,0x00,0x93,0x85,0x81,0xf1,0x24,0x02,0x00,0x01,0x14,0xa2,0x00,0x51,
24880x00,0x80,0x40,0x21,0x8c,0x89,0x00,0x04,0x3c,0x03,0xb0,0x01,0x01,0x23,0x30,0x21,
24890x8c,0xc2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x08,0x10,0x45,0x00,0x59,
24900x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x24,0x03,0x00,0xb4,0x30,0x44,0x00,0xff,
24910x10,0x83,0x00,0x61,0x24,0x02,0x00,0xc4,0x10,0x82,0x00,0x54,0x24,0x02,0x00,0x94,
24920x10,0x82,0x00,0x45,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x00,0x00,0x00,0x00,
24930x30,0x47,0xff,0xff,0x30,0xe3,0x40,0xff,0x24,0x02,0x40,0x88,0x14,0x62,0x00,0x39,
24940x30,0xe3,0x03,0x00,0x24,0x02,0x03,0x00,0x10,0x62,0x00,0x38,0x00,0x00,0x00,0x00,
24950x94,0xc2,0x00,0x56,0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff,0x30,0xe2,0x00,0x80,
24960x14,0x40,0x00,0x30,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,0x94,0xc3,0x00,0x60,
24970x24,0x02,0x00,0x08,0x14,0x43,0x00,0x3b,0x00,0x00,0x00,0x00,0x90,0xc2,0x00,0x62,
24980x24,0x03,0x00,0x04,0x00,0x02,0x39,0x02,0x10,0xe3,0x00,0x15,0x24,0x02,0x00,0x06,
24990x14,0xe2,0x00,0x34,0x00,0x00,0x00,0x00,0x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x66,
25000x27,0x82,0x89,0x58,0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21,
25010x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25,
25020x24,0x42,0x00,0x5e,0x24,0x03,0xc0,0x00,0x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24,
25030x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00,0x08,0x00,0x26,0xcd,0xad,0x07,0x00,0x10,
25040x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x64,0x27,0x82,0x89,0x58,0x00,0x05,0x28,0x80,
25050x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00,
25060x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x36,0x3c,0x03,0xff,0xff,
25070x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00,
25080xad,0x07,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x50,
25090x08,0x00,0x26,0x8b,0x30,0x47,0xff,0xff,0x8d,0x04,0x01,0xac,0x27,0x83,0x89,0x58,
25100x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff,
25110x00,0x43,0x10,0x24,0x34,0x42,0x00,0x2e,0xac,0x82,0x00,0x00,0x24,0x03,0x00,0x2e,
25120xad,0x03,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x04,0x01,0xac,
25130x27,0x83,0x89,0x58,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,
25140x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x0e,0x24,0x03,0x00,0x0e,
25150x08,0x00,0x26,0xcc,0xac,0x82,0x00,0x00,0x8d,0x04,0x01,0xac,0x27,0x83,0x89,0x58,
25160x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff,
25170x00,0x43,0x10,0x24,0x34,0x42,0x00,0x14,0x24,0x03,0x00,0x14,0x08,0x00,0x26,0xcc,
25180xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xc6,0x00,0xff,
25190x00,0x06,0x48,0x40,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x8b,0xbc,0x20,
25200x27,0x83,0xbc,0x26,0x00,0x4b,0x40,0x21,0x00,0x43,0x10,0x21,0x94,0x47,0x00,0x00,
25210x30,0xa2,0x3f,0xff,0x10,0xe2,0x00,0x29,0x30,0x8a,0xff,0xff,0x95,0x02,0x00,0x02,
25220x24,0x03,0x00,0x01,0x00,0x02,0x11,0x82,0x30,0x42,0x00,0x01,0x10,0x43,0x00,0x18,
25230x00,0x00,0x00,0x00,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4b,0x30,0x21,
25240x94,0xc4,0x00,0x02,0x27,0x83,0xbc,0x26,0x27,0x85,0xbc,0x24,0x00,0x45,0x28,0x21,
25250x30,0x84,0xff,0xdf,0x00,0x43,0x10,0x21,0xa4,0xc4,0x00,0x02,0xa4,0x40,0x00,0x00,
25260xa4,0xa0,0x00,0x00,0x94,0xc3,0x00,0x02,0x3c,0x04,0xb0,0x01,0x01,0x44,0x20,0x21,
25270x30,0x63,0xff,0xbf,0xa4,0xc3,0x00,0x02,0xa0,0xc0,0x00,0x00,0x8c,0x82,0x00,0x04,
25280x24,0x03,0xf0,0xff,0x00,0x43,0x10,0x24,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x04,
25290x24,0x02,0xc0,0x00,0x91,0x04,0x00,0x01,0x00,0xa2,0x10,0x24,0x00,0x47,0x28,0x25,
25300x3c,0x03,0xb0,0x01,0x24,0x02,0x00,0x02,0x14,0x82,0xff,0xe2,0x01,0x43,0x18,0x21,
25310xac,0x65,0x00,0x00,0x08,0x00,0x26,0xfa,0x01,0x26,0x10,0x21,0x08,0x00,0x26,0xfa,
25320x01,0x26,0x10,0x21,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01,0x14,0x62,0x00,0x0d,
25330x3c,0x02,0xb0,0x01,0x8c,0x84,0x00,0x04,0x3c,0x06,0xb0,0x09,0x00,0x82,0x20,0x21,
25340x8c,0x85,0x00,0x08,0x8c,0x83,0x00,0x04,0x3c,0x02,0x01,0x00,0x34,0xc6,0x01,0x00,
25350x00,0x62,0x18,0x24,0x14,0x60,0x00,0x05,0x30,0xa5,0x20,0x00,0x24,0x02,0x00,0x06,
25360xa0,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x09,
25370x10,0xa0,0xff,0xfc,0x34,0x63,0x01,0x00,0x24,0x02,0x00,0x0e,0x08,0x00,0x27,0x2d,
25380xa0,0x62,0x00,0x00,0x3c,0x02,0xb0,0x01,0x30,0xa5,0xff,0xff,0x00,0xa2,0x28,0x21,
25390x8c,0xa3,0x00,0x00,0x3c,0x02,0x10,0x00,0x00,0x80,0x30,0x21,0x00,0x62,0x18,0x24,
25400x8c,0xa2,0x00,0x04,0x10,0x60,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x80,0x00,
25410x10,0x40,0x00,0x13,0x00,0x00,0x00,0x00,0x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00,
25420x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a,
25430x93,0x83,0x81,0xf0,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,
25440x24,0x63,0xff,0xff,0xac,0xc4,0x01,0xa8,0xa3,0x83,0x81,0xf0,0x8c,0xc4,0x01,0xac,
25450x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x26,0x00,0x02,0x10,0x2b,
25460x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73,
25470x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x04,
25480x00,0x00,0x00,0x00,0xa3,0x80,0x81,0xf1,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
25490x24,0x02,0x00,0x01,0xa3,0x82,0x81,0xf1,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
25500x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xa8,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
25510x30,0x62,0x00,0xff,0x00,0x03,0x2e,0x02,0x00,0x02,0x39,0x80,0x2c,0xa2,0x00,0x02,
25520x00,0x03,0x34,0x02,0x10,0x40,0x00,0x05,0x00,0x03,0x1a,0x02,0xa4,0x87,0x01,0xd8,
25530xa0,0x85,0x01,0xd4,0xa0,0x86,0x01,0xd5,0xa0,0x83,0x01,0xd6,0x03,0xe0,0x00,0x08,
25540x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x3c,0x05,0xb0,0x01,0x00,0x80,0x50,0x21,
25550x00,0x45,0x10,0x21,0x8c,0x43,0x00,0x04,0x24,0x02,0x00,0x05,0x00,0x03,0x1a,0x02,
25560x30,0x69,0x00,0x0f,0x11,0x22,0x00,0x0b,0x24,0x02,0x00,0x07,0x11,0x22,0x00,0x09,
25570x24,0x02,0x00,0x0a,0x11,0x22,0x00,0x07,0x24,0x02,0x00,0x0b,0x11,0x22,0x00,0x05,
25580x24,0x02,0x00,0x01,0x93,0x83,0x81,0xf0,0x3c,0x04,0xb0,0x06,0x10,0x62,0x00,0x03,
25590x34,0x84,0x80,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,
25600x00,0x00,0x00,0x00,0x00,0x02,0x17,0x02,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,
25610x8d,0x43,0x01,0xa8,0x27,0x82,0x89,0x58,0x00,0x03,0x18,0x80,0x00,0x6a,0x20,0x21,
25620x8c,0x87,0x00,0xa8,0x00,0x62,0x18,0x21,0x8c,0x68,0x00,0x00,0x00,0xe5,0x28,0x21,
25630x8c,0xa9,0x00,0x00,0x3c,0x02,0xff,0xff,0x27,0x83,0x8a,0x58,0x01,0x22,0x10,0x24,
25640x00,0x48,0x10,0x25,0xac,0xa2,0x00,0x00,0x8d,0x44,0x01,0xa8,0x00,0x07,0x30,0xc2,
25650x3c,0x02,0x00,0x80,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x00,0x06,0x32,0x00,
25660x8c,0xa9,0x00,0x04,0x00,0xc2,0x30,0x25,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00,
25670x01,0x22,0x10,0x25,0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x04,0xaf,0x87,0xbc,0x10,
25680x8c,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x82,0xbc,0x18,0x8c,0xa3,0x00,0x04,
25690x3c,0x01,0xb0,0x07,0xac,0x26,0x80,0x18,0x8d,0x42,0x01,0xa8,0xaf,0x83,0xbc,0x14,
25700x93,0x85,0x81,0xf0,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,
25710x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0xa5,0xff,0xff,
25720x00,0x82,0x20,0x23,0xad,0x44,0x01,0xa8,0xa3,0x85,0x81,0xf0,0x08,0x00,0x27,0x89,
25730x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x01,0x24,0x42,0x9f,0x04,
25740x34,0xa5,0x00,0x20,0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x20,
25750xac,0x82,0x00,0x64,0x3c,0x02,0x80,0x01,0xac,0x83,0x00,0x60,0x00,0x80,0x38,0x21,
25760xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x4c,
25770xac,0x80,0x00,0x50,0xac,0x80,0x00,0x54,0xac,0x80,0x00,0x0c,0xac,0x80,0x00,0x58,
25780xa0,0x80,0x00,0x5c,0x24,0x83,0x00,0x68,0x24,0x42,0xa0,0x14,0x24,0x04,0x00,0x0f,
25790x24,0x84,0xff,0xff,0xac,0x62,0x00,0x00,0x04,0x81,0xff,0xfd,0x24,0x63,0x00,0x04,
25800x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xa8,0xac,0xe0,0x01,0xa8,0xac,0xe0,0x01,0xac,
25810xac,0xe0,0x01,0xb0,0xac,0xe0,0x01,0xb4,0xa0,0xe0,0x01,0xb8,0xa0,0xe0,0x01,0xb9,
25820xa0,0xe0,0x01,0xba,0xa0,0xe0,0x01,0xc0,0xa0,0xe0,0x01,0xc1,0xac,0xe0,0x01,0xc4,
25830xac,0xe0,0x01,0xc8,0xac,0xe0,0x01,0xcc,0xac,0xe0,0x01,0xd0,0x8c,0x44,0x00,0x00,
25840x3c,0x02,0x80,0x01,0x24,0x42,0xa0,0xfc,0x30,0x83,0x00,0xff,0x00,0x03,0x19,0x80,
25850xa4,0xe3,0x01,0xd8,0xac,0xe2,0x00,0x78,0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,
25860x24,0x63,0xa2,0x88,0x24,0x42,0xa1,0xf4,0xac,0xe3,0x00,0x88,0xac,0xe2,0x00,0x98,
25870x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,0x00,0x04,0x2e,0x03,0x00,0x04,0x34,0x03,
25880x24,0x63,0xa3,0x30,0x00,0x04,0x22,0x03,0x24,0x42,0xa4,0x74,0xac,0xe3,0x00,0xa0,
25890xac,0xe2,0x00,0xa4,0xa0,0xe5,0x01,0xd4,0xa0,0xe6,0x01,0xd5,0x03,0xe0,0x00,0x08,
25900xa0,0xe4,0x01,0xd6,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,
25910x24,0x42,0xa0,0x14,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x3c,0x02,0xb0,0x03,
25920x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0x2c,0xac,0x43,0x00,0x00,
25930x8c,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,0x00,0x80,0x28,0x21,
25940x8c,0x82,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,
25950x8c,0x84,0x00,0x10,0x8c,0xa3,0x00,0x14,0x8c,0xa2,0x00,0x04,0x00,0x83,0x20,0x21,
25960x00,0x44,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,0x00,0x02,0x12,0x02,
25970x00,0x43,0x10,0x21,0x00,0x02,0x12,0x00,0x30,0x42,0x3f,0xff,0xac,0xa2,0x00,0x04,
25980xac,0xa0,0x00,0x00,0xac,0xa0,0x00,0x4c,0xac,0xa0,0x00,0x50,0xac,0xa0,0x00,0x54,
25990x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x0c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,
26000x34,0x63,0x00,0x20,0x24,0x42,0xa0,0xa8,0xac,0x62,0x00,0x00,0x8c,0x86,0x00,0x04,
26010x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01,0x00,0xc2,0x10,0x21,0x8c,0x45,0x00,0x00,
26020xac,0x83,0x00,0x4c,0x00,0x05,0x14,0x02,0x30,0xa3,0x3f,0xff,0x30,0x42,0x00,0xff,
26030xac,0x83,0x00,0x10,0xac,0x82,0x00,0x14,0x8c,0x83,0x00,0x14,0xac,0x85,0x00,0x40,
26040x00,0xc3,0x30,0x21,0x03,0xe0,0x00,0x08,0xac,0x86,0x00,0x08,0x3c,0x02,0xb0,0x03,
26050x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0xfc,
26060xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,
26070x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x00,0x80,0x80,0x21,0xae,0x00,0x00,0x00,
26080xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,
26090x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
26100x0c,0x00,0x28,0x2a,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x4c,0xae,0x00,0x00,0x00,
26110x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,
26120x24,0x63,0xa1,0x60,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,
26130x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,
26140x8e,0x03,0x00,0x08,0x3c,0x02,0xb0,0x01,0x8e,0x04,0x00,0x44,0x00,0x62,0x18,0x21,
26150x90,0x65,0x00,0x00,0x24,0x02,0x00,0x01,0xae,0x02,0x00,0x50,0x30,0xa3,0x00,0xff,
26160x00,0x03,0x10,0x82,0x00,0x04,0x23,0x02,0x30,0x84,0x00,0x0f,0x30,0x42,0x00,0x03,
26170x00,0x03,0x19,0x02,0xae,0x04,0x00,0x34,0xae,0x02,0x00,0x2c,0xae,0x03,0x00,0x30,
26180xa2,0x05,0x00,0x48,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
26190x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x2a,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x64,
26200x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
26210x34,0x42,0x00,0x20,0x24,0x63,0xa1,0xf4,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
26220xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16,
26230x00,0x80,0x80,0x21,0x92,0x03,0x00,0x44,0x8e,0x02,0x00,0x40,0x83,0x85,0x8b,0xc4,
26240x92,0x04,0x00,0x41,0x30,0x63,0x00,0x01,0x00,0x02,0x16,0x02,0xae,0x04,0x00,0x14,
26250x00,0x00,0x30,0x21,0xae,0x02,0x00,0x18,0x10,0xa0,0x00,0x04,0xae,0x03,0x00,0x3c,
26260x10,0x60,0x00,0x03,0x24,0x02,0x00,0x01,0x24,0x06,0x00,0x01,0x24,0x02,0x00,0x01,
26270xa3,0x86,0x8b,0xc4,0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,
26280x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x58,0x00,0x00,0x00,0x00,
26290x08,0x00,0x28,0x89,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
26300x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa2,0x88,0xaf,0xb0,0x00,0x10,
26310xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00,
26320x10,0x40,0x00,0x1b,0x00,0x80,0x80,0x21,0x3c,0x02,0xb0,0x03,0x8c,0x42,0x00,0x00,
26330x92,0x04,0x00,0x44,0x8e,0x03,0x00,0x40,0x83,0x86,0x8b,0xc4,0x92,0x05,0x00,0x41,
26340x30,0x42,0x08,0x00,0x30,0x84,0x00,0x01,0x00,0x02,0x12,0xc2,0x00,0x03,0x1e,0x02,
26350x00,0x82,0x20,0x25,0xae,0x05,0x00,0x14,0x00,0x00,0x38,0x21,0xae,0x03,0x00,0x18,
26360x10,0xc0,0x00,0x04,0xae,0x04,0x00,0x3c,0x10,0x80,0x00,0x03,0x24,0x02,0x00,0x01,
26370x24,0x07,0x00,0x01,0x24,0x02,0x00,0x01,0xa3,0x87,0x8b,0xc4,0x8f,0xbf,0x00,0x14,
26380xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
26390x0c,0x00,0x28,0x58,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0xae,0x00,0x00,0x00,0x00,
26400x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,
26410x24,0x63,0xa3,0x30,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,
26420x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x42,0x00,0x80,0x80,0x21,
26430x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,0x3c,0x08,0xb0,0x01,
26440x34,0x42,0x00,0x10,0x00,0x88,0x20,0x21,0x00,0x62,0x18,0x25,0xac,0x83,0x00,0x04,
26450x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x27,0x89,0x89,0x58,0x00,0x48,0x10,0x21,
26460x8c,0x45,0x00,0x00,0x00,0x03,0x18,0x80,0x00,0x69,0x18,0x21,0xac,0x65,0x00,0x00,
26470x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x27,0x87,0x8a,0x58,0x00,0x48,0x10,0x21,
26480x8c,0x45,0x00,0x04,0x00,0x03,0x18,0x80,0x00,0x67,0x18,0x21,0xac,0x65,0x00,0x00,
26490x8e,0x02,0x01,0xac,0x8e,0x06,0x00,0x04,0x02,0x00,0x20,0x21,0x00,0x02,0x10,0x80,
26500x00,0x47,0x38,0x21,0x94,0xe3,0x00,0x02,0x00,0x49,0x10,0x21,0x90,0x45,0x00,0x00,
26510x00,0x03,0x1a,0x00,0x00,0xc8,0x30,0x21,0x00,0xa3,0x28,0x25,0x0c,0x00,0x26,0x69,
26520xa4,0xc5,0x00,0x2e,0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03,
26530x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a,
26540x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23,
26550x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30,
26560x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0,0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01,
26570x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,0xa3,0x82,0x81,0xf0,0x0c,0x00,0x28,0x0b,
26580x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
26590x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0xa2,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0xd8,
26600x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
26610x34,0x42,0x00,0x20,0x24,0x63,0xa4,0x74,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
26620xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x42,
26630x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,
26640x3c,0x08,0xb0,0x01,0x34,0x42,0x00,0x10,0x00,0x88,0x20,0x21,0x00,0x62,0x18,0x25,
26650xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x27,0x89,0x89,0x58,
26660x00,0x48,0x10,0x21,0x8c,0x45,0x00,0x00,0x00,0x03,0x18,0x80,0x00,0x69,0x18,0x21,
26670xac,0x65,0x00,0x00,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x27,0x87,0x8a,0x58,
26680x00,0x48,0x10,0x21,0x8c,0x45,0x00,0x04,0x00,0x03,0x18,0x80,0x00,0x67,0x18,0x21,
26690xac,0x65,0x00,0x00,0x8e,0x02,0x01,0xac,0x8e,0x06,0x00,0x04,0x02,0x00,0x20,0x21,
26700x00,0x02,0x10,0x80,0x00,0x47,0x38,0x21,0x94,0xe3,0x00,0x02,0x00,0x49,0x10,0x21,
26710x90,0x45,0x00,0x00,0x00,0x03,0x1a,0x00,0x00,0xc8,0x30,0x21,0x00,0xa3,0x28,0x25,
26720x0c,0x00,0x26,0x69,0xa4,0xc5,0x00,0x2e,0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04,
26730x3c,0x06,0xb0,0x03,0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40,
26740x00,0xa4,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,
26750x00,0xa2,0x28,0x23,0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8,
26760x34,0xc6,0x00,0x30,0x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0,0x02,0x00,0x20,0x21,
26770x24,0x63,0x00,0x01,0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,0xa3,0x82,0x81,0xf0,
26780x0c,0x00,0x28,0x0b,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
26790x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0xa2,0x00,0x00,0x00,0x00,
26800x08,0x00,0x29,0x29,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
26810x27,0xbd,0xff,0xd8,0x34,0x42,0x00,0x20,0x24,0x63,0xa5,0xb8,0xaf,0xb2,0x00,0x18,
26820xac,0x43,0x00,0x00,0x3c,0x12,0xb0,0x03,0x3c,0x02,0x80,0x01,0xaf,0xb4,0x00,0x20,
26830xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x24,
26840x00,0x80,0x80,0x21,0x24,0x54,0xa0,0x14,0x00,0x00,0x88,0x21,0x3c,0x13,0xb0,0x01,
26850x36,0x52,0x00,0xef,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x06,0x90,0x43,0x00,0x00,
26860x8e,0x04,0x00,0x04,0x92,0x02,0x01,0xbb,0x30,0x69,0x00,0xff,0x00,0x04,0x42,0x02,
26870x10,0x40,0x00,0x1e,0x00,0x00,0x38,0x21,0x8e,0x03,0x01,0xa8,0x3c,0x06,0x28,0x38,
26880x34,0xc6,0x00,0x20,0x24,0x64,0x00,0x3d,0x28,0x82,0x00,0x00,0x24,0x63,0x00,0x7c,
26890x00,0x82,0x18,0x0a,0x00,0x03,0x19,0x83,0x00,0x03,0x19,0x80,0x00,0x83,0x20,0x23,
26900x00,0x04,0x10,0x80,0x00,0x50,0x10,0x21,0x8c,0x45,0x00,0xa8,0xae,0x04,0x01,0xac,
26910xae,0x04,0x01,0xa8,0x00,0xb3,0x18,0x21,0xae,0x05,0x00,0x04,0xac,0x66,0x00,0x00,
26920x8e,0x02,0x00,0x04,0x3c,0x03,0x80,0x00,0x34,0x63,0x4e,0x00,0x00,0x53,0x10,0x21,
26930xac,0x43,0x00,0x04,0xa2,0x00,0x01,0xbb,0x93,0x83,0x81,0xf7,0x00,0x00,0x00,0x00,
26940x24,0x62,0x00,0x01,0xa3,0x82,0x81,0xf7,0xa2,0x43,0x00,0x00,0x01,0x28,0x10,0x23,
26950x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a,
26960x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0x84,0xff,0xff,0x10,0x44,0x00,0x6b,
26970x3c,0x02,0xb0,0x01,0x8e,0x03,0x00,0x04,0x3c,0x04,0x7c,0x00,0x00,0x62,0x18,0x21,
26980x8c,0x65,0x00,0x04,0x34,0x84,0x00,0xf0,0x00,0x00,0x30,0x21,0xae,0x05,0x00,0x44,
26990x00,0xa4,0x20,0x24,0x8c,0x63,0x00,0x00,0x10,0x80,0x00,0x6b,0x3c,0x02,0xff,0xff,
27000x3c,0x09,0xb0,0x03,0x3c,0x05,0x7c,0x00,0x35,0x29,0x00,0x99,0x3c,0x0a,0xb0,0x01,
27010x24,0x08,0x00,0x40,0x34,0xa5,0x00,0xf0,0x3c,0x0b,0xff,0xff,0x3c,0x0c,0x28,0x38,
27020x16,0x20,0x00,0x06,0x24,0xe7,0x00,0x01,0x93,0x82,0x81,0xf6,0x24,0x11,0x00,0x01,
27030x24,0x42,0x00,0x01,0xa1,0x22,0x00,0x00,0xa3,0x82,0x81,0xf6,0x8e,0x02,0x00,0x04,
27040x24,0x06,0x00,0x01,0x24,0x42,0x01,0x00,0x30,0x42,0x3f,0xff,0xae,0x02,0x00,0x04,
27050x00,0x4a,0x10,0x21,0x8c,0x43,0x00,0x04,0x00,0x00,0x00,0x00,0xae,0x03,0x00,0x44,
27060x00,0x65,0x20,0x24,0x8c,0x43,0x00,0x00,0x10,0xe8,0x00,0x2d,0x00,0x00,0x00,0x00,
27070x14,0x80,0xff,0xeb,0x00,0x6b,0x10,0x24,0x14,0x4c,0xff,0xe9,0x24,0x02,0x00,0x01,
27080x10,0xc2,0x00,0x30,0x3c,0x03,0xb0,0x09,0x8e,0x02,0x00,0x44,0x8e,0x04,0x00,0x60,
27090x00,0x02,0x1e,0x42,0x00,0x02,0x12,0x02,0x30,0x42,0x00,0x0f,0x30,0x63,0x00,0x01,
27100xae,0x02,0x00,0x00,0x10,0x44,0x00,0x1a,0xae,0x03,0x00,0x58,0x8e,0x02,0x00,0x64,
27110x8e,0x04,0x00,0x58,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x05,0x00,0x00,0x00,0x00,
27120xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,
27130x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x80,0x00,0x50,0x10,0x21,
27140x8c,0x42,0x00,0x68,0x00,0x00,0x00,0x00,0x10,0x54,0x00,0x06,0x00,0x00,0x00,0x00,
27150x00,0x40,0xf8,0x09,0x02,0x00,0x20,0x21,0x8e,0x04,0x00,0x58,0x8e,0x03,0x00,0x00,
27160x00,0x00,0x00,0x00,0xae,0x03,0x00,0x60,0x08,0x00,0x29,0x81,0xae,0x04,0x00,0x64,
27170x8e,0x02,0x00,0x64,0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xe5,0x00,0x00,0x00,0x00,
27180x7a,0x02,0x0d,0x7c,0x8f,0xbf,0x00,0x24,0x8f,0xb4,0x00,0x20,0x7b,0xb2,0x00,0xfc,
27190x7b,0xb0,0x00,0xbc,0x00,0x43,0x10,0x26,0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,
27200x27,0xbd,0x00,0x28,0x8e,0x04,0x00,0x04,0x34,0x63,0x00,0x06,0x90,0x62,0x00,0x00,
27210x00,0x04,0x42,0x02,0x00,0x48,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,
27220x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,
27230x00,0x82,0x20,0x23,0x14,0x86,0xff,0xc4,0x00,0x00,0x00,0x00,0x8e,0x03,0x00,0x00,
27240x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x03,0x14,0x40,0x00,0x05,0x24,0x02,0x00,0x0d,
27250x10,0x62,0x00,0x03,0x24,0x02,0x00,0x01,0x08,0x00,0x2a,0x04,0xa2,0x02,0x00,0x5c,
27260x08,0x00,0x2a,0x04,0xa2,0x00,0x00,0x5c,0x00,0x62,0x10,0x24,0x3c,0x03,0x28,0x38,
27270x14,0x43,0xff,0x93,0x24,0x02,0x00,0x01,0x08,0x00,0x29,0xdc,0x00,0x00,0x00,0x00,
27280x3c,0x02,0xb0,0x01,0x00,0xa2,0x40,0x21,0x00,0xa0,0x48,0x21,0x8d,0x05,0x00,0x00,
27290x24,0x02,0xc0,0x00,0x00,0x09,0x38,0xc2,0x00,0xa2,0x28,0x24,0x24,0xc2,0xff,0xff,
27300x00,0x07,0x3a,0x00,0x3c,0x0a,0xb0,0x06,0x3c,0x03,0x00,0x80,0x00,0xa6,0x28,0x25,
27310x2c,0x42,0x1f,0xff,0x00,0xe3,0x38,0x25,0x35,0x4a,0x80,0x18,0x10,0x40,0x00,0x0e,
27320xad,0x05,0x00,0x00,0xaf,0x89,0xbc,0x10,0x8d,0x02,0x00,0x00,0x00,0x00,0x00,0x00,
27330xaf,0x82,0xbc,0x18,0x8d,0x03,0x00,0x04,0xad,0x47,0x00,0x00,0xaf,0x83,0xbc,0x14,
27340xac,0x80,0x01,0xd0,0xac,0x80,0x01,0xc4,0xa0,0x80,0x01,0xc0,0xa0,0x80,0x01,0xc1,
27350xac,0x80,0x01,0xc8,0xac,0x80,0x01,0xcc,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
27360x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x8c,0x83,0x01,0xc4,0x00,0x80,0x38,0x21,
27370x90,0x84,0x01,0xc0,0x00,0x03,0x18,0x80,0x00,0x67,0x18,0x21,0x8c,0x65,0x00,0xa8,
27380x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01,0x00,0xa2,0x10,0x21,0x8c,0x42,0x00,0x00,
27390x10,0x83,0x00,0x18,0x00,0x02,0x14,0x02,0x8c,0xe9,0x01,0xcc,0x8c,0xea,0x01,0xc8,
27400x30,0x46,0x00,0xff,0x01,0x2a,0x18,0x21,0x30,0x64,0x00,0xff,0x00,0x03,0x1a,0x02,
27410x24,0x62,0x00,0x01,0x14,0x80,0x00,0x02,0x30,0x48,0x00,0xff,0x30,0x68,0x00,0xff,
27420x90,0xe2,0x01,0xc1,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x23,0x00,0x02,0x12,0x00,
27430x00,0x49,0x10,0x21,0x00,0x4a,0x10,0x21,0x00,0x46,0x30,0x23,0x0c,0x00,0x2a,0x2c,
27440x00,0xe0,0x20,0x21,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
27450x27,0xbd,0x00,0x18,0x8c,0xe6,0x01,0xc8,0x08,0x00,0x2a,0x6b,0x00,0x00,0x00,0x00,
27460x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x14,0xaf,0xb0,0x00,0x10,0x8c,0x82,0x01,0xc4,
27470x90,0x87,0x01,0xc1,0x00,0x80,0x80,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,
27480x8c,0x48,0x00,0xa8,0x3c,0x02,0xb0,0x01,0x00,0x07,0x3a,0x00,0x01,0x02,0x10,0x21,
27490x8c,0x43,0x00,0x00,0x00,0xe5,0x38,0x21,0x00,0xe6,0x38,0x21,0x00,0x03,0x1c,0x02,
27500x30,0x63,0x00,0xff,0x00,0xe3,0x38,0x23,0x01,0x00,0x28,0x21,0x0c,0x00,0x2a,0x2c,
27510x00,0xe0,0x30,0x21,0x8e,0x02,0x01,0xa8,0x8f,0xbf,0x00,0x14,0x24,0x44,0x00,0x01,
27520x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,
27530x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0xae,0x04,0x01,0xa8,0x8f,0xb0,0x00,0x10,
27540x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
27550x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xaa,0x58,0xaf,0xb0,0x00,0x10,
27560xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x90,0x82,0x01,0xd4,0x00,0x00,0x00,0x00,
27570x14,0x40,0x00,0x6a,0x00,0x80,0x80,0x21,0x90,0x82,0x01,0xc0,0x00,0x00,0x00,0x00,
27580x14,0x40,0x00,0x61,0x00,0x00,0x00,0x00,0x8c,0x83,0x01,0xa8,0x8c,0x82,0x01,0xac,
27590x00,0x00,0x00,0x00,0x10,0x62,0x00,0x22,0x00,0x00,0x28,0x21,0x93,0x82,0x81,0xf1,
27600x00,0x03,0x30,0x80,0x00,0xc4,0x18,0x21,0x24,0x04,0x00,0x01,0x8c,0x67,0x00,0xa8,
27610x10,0x44,0x00,0x20,0x3c,0x04,0xb0,0x01,0xaf,0x87,0xbc,0x10,0x00,0xe4,0x20,0x21,
27620x8c,0x86,0x00,0x00,0x00,0x07,0x18,0xc2,0x3c,0x02,0x00,0x80,0xaf,0x86,0xbc,0x18,
27630x8c,0x86,0x00,0x04,0x00,0x03,0x1a,0x00,0x3c,0x05,0xb0,0x06,0x00,0x62,0x18,0x25,
27640x34,0xa5,0x80,0x18,0xac,0xa3,0x00,0x00,0x8e,0x02,0x01,0xa8,0x8e,0x09,0x01,0xac,
27650xaf,0x86,0xbc,0x14,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,
27660x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,
27670x00,0x80,0x30,0x21,0xae,0x04,0x01,0xa8,0x00,0xc9,0x10,0x26,0x00,0x02,0x28,0x2b,
27680x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x00,0xa0,0x10,0x21,0x03,0xe0,0x00,0x08,
27690x27,0xbd,0x00,0x18,0x93,0x82,0x81,0xf0,0x00,0x00,0x00,0x00,0x2c,0x42,0x00,0x02,
27700x14,0x40,0xff,0xf7,0x00,0x00,0x28,0x21,0x3c,0x05,0xb0,0x01,0x00,0xe5,0x28,0x21,
27710x27,0x83,0x89,0x58,0x00,0xc3,0x18,0x21,0x8c,0xa6,0x00,0x00,0x8c,0x64,0x00,0x00,
27720x24,0x02,0xc0,0x00,0x00,0xc2,0x10,0x24,0x00,0x44,0x10,0x25,0xac,0xa2,0x00,0x00,
27730x8e,0x03,0x01,0xa8,0x27,0x84,0x8a,0x58,0x8c,0xa6,0x00,0x04,0x00,0x03,0x18,0x80,
27740x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00,0x3c,0x03,0x80,0x00,0x00,0x07,0x20,0xc2,
27750x00,0xc2,0x10,0x25,0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x04,0xaf,0x87,0xbc,0x10,
27760x8c,0xa6,0x00,0x00,0x3c,0x02,0x00,0x80,0x00,0x04,0x22,0x00,0x3c,0x03,0xb0,0x06,
27770xaf,0x86,0xbc,0x18,0x00,0x82,0x20,0x25,0x34,0x63,0x80,0x18,0x8c,0xa6,0x00,0x04,
27780xac,0x64,0x00,0x00,0x8e,0x02,0x01,0xa8,0xaf,0x86,0xbc,0x14,0x24,0x44,0x00,0x01,
27790x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a,0x93,0x83,0x81,0xf0,
27800x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0x24,0x63,0xff,0xff,
27810xae,0x04,0x01,0xa8,0xa3,0x83,0x81,0xf0,0x8e,0x04,0x01,0xac,0x8e,0x02,0x01,0xa8,
27820x08,0x00,0x2a,0xcb,0x00,0x44,0x10,0x26,0x0c,0x00,0x2a,0x4c,0x00,0x00,0x00,0x00,
27830x7a,0x02,0x0d,0x7c,0x08,0x00,0x2a,0xcb,0x00,0x43,0x10,0x26,0x8c,0x86,0x01,0xa8,
27840x8c,0x89,0x01,0xac,0x00,0x00,0x00,0x00,0x10,0xc9,0x00,0xb4,0x00,0xc0,0x68,0x21,
27850x00,0x06,0x10,0x80,0x27,0x83,0x89,0x58,0x00,0x43,0x18,0x21,0x00,0x44,0x10,0x21,
27860x8c,0x47,0x00,0xa8,0x94,0x65,0x00,0x02,0x3c,0x02,0xb0,0x01,0x00,0xe2,0x10,0x21,
27870x30,0xa5,0x3f,0xff,0xa4,0x45,0x00,0x2c,0x90,0x8a,0x01,0xc0,0x00,0x00,0x00,0x00,
27880x11,0x40,0x00,0x0c,0x00,0x07,0x32,0x02,0x8c,0x83,0x01,0xc4,0x90,0x85,0x01,0xc1,
27890x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0xa8,0x00,0x00,0x00,0x00,
27900x00,0x02,0x12,0x02,0x00,0x45,0x10,0x21,0x30,0x42,0x00,0x3f,0x14,0xc2,0xff,0xde,
27910x00,0x00,0x00,0x00,0x3c,0x04,0xb0,0x01,0x00,0xe4,0x40,0x21,0x8d,0x06,0x00,0x00,
27920x00,0x0d,0x28,0x80,0x00,0x06,0x14,0x02,0x30,0x4b,0x00,0xff,0x00,0xeb,0x70,0x21,
27930x01,0xc4,0x20,0x21,0x90,0x83,0x00,0x00,0x27,0x82,0x89,0x58,0x00,0xa2,0x28,0x21,
27940x8c,0xa4,0x00,0x00,0x00,0x03,0x18,0x82,0x30,0x63,0x00,0x03,0x2c,0x62,0x00,0x02,
27950x14,0x40,0x00,0x66,0x30,0x8c,0x3f,0xff,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x61,
27960x2d,0x82,0x08,0x00,0x15,0x40,0x00,0x36,0x01,0x6c,0x10,0x21,0x01,0x6c,0x18,0x21,
27970x30,0x62,0x00,0xff,0x00,0x02,0x10,0x2b,0x00,0x03,0x1a,0x02,0x3c,0x04,0xb0,0x01,
27980x00,0x62,0x18,0x21,0x00,0xe4,0x20,0x21,0x24,0x02,0x00,0x01,0xa2,0x03,0x01,0xc1,
27990xa0,0x82,0x00,0x08,0x8e,0x06,0x01,0xa8,0x3c,0x03,0xb0,0x00,0x34,0x63,0xff,0xf4,
28000x24,0xc5,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0xc2,0x00,0x40,0x00,0xa4,0x10,0x0a,
28010x01,0xc3,0x18,0x21,0xa4,0x6c,0x00,0x00,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,
28020x92,0x04,0x01,0xc0,0x00,0xa2,0x38,0x23,0x3c,0x03,0xb0,0x03,0xae,0x0b,0x01,0xcc,
28030xae,0x0c,0x01,0xc8,0xae,0x06,0x01,0xc4,0xae,0x07,0x01,0xa8,0x34,0x63,0x01,0x08,
28040x92,0x05,0x01,0xd6,0x8c,0x66,0x00,0x00,0x24,0x84,0x00,0x01,0x30,0x82,0x00,0xff,
28050x00,0x45,0x10,0x2b,0xae,0x06,0x01,0xd0,0x10,0x40,0x00,0x07,0xa2,0x04,0x01,0xc0,
28060x92,0x02,0x01,0xd5,0x92,0x03,0x01,0xc1,0x24,0x42,0xff,0xfc,0x00,0x62,0x18,0x2a,
28070x14,0x60,0x00,0x08,0x00,0x00,0x00,0x00,0x02,0x00,0x20,0x21,0x0c,0x00,0x2a,0x4c,
28080x00,0x00,0x00,0x00,0x8e,0x09,0x01,0xac,0x8e,0x06,0x01,0xa8,0x08,0x00,0x2a,0xcb,
28090x00,0xc9,0x10,0x26,0x8e,0x09,0x01,0xac,0x08,0x00,0x2a,0xca,0x00,0xe0,0x30,0x21,
28100x30,0x43,0x00,0xff,0x92,0x07,0x01,0xc1,0x00,0x02,0x12,0x02,0x30,0x44,0x00,0xff,
28110x38,0x63,0x00,0x00,0x24,0x46,0x00,0x01,0x92,0x05,0x01,0xd5,0x00,0x83,0x30,0x0a,
28120x00,0xc7,0x18,0x21,0x00,0xa3,0x10,0x2a,0x14,0x40,0xff,0xeb,0x00,0x00,0x00,0x00,
28130x24,0xa2,0xff,0xfc,0x00,0x62,0x10,0x2a,0x10,0x40,0x00,0x07,0x01,0x80,0x28,0x21,
28140x92,0x03,0x01,0xd6,0x25,0x42,0x00,0x01,0x00,0x43,0x10,0x2a,0x14,0x40,0x00,0x07,
28150x25,0xa4,0x00,0x01,0x01,0x80,0x28,0x21,0x01,0x60,0x30,0x21,0x0c,0x00,0x2a,0x74,
28160x02,0x00,0x20,0x21,0x08,0x00,0x2b,0x6d,0x00,0x00,0x00,0x00,0x28,0x83,0x00,0x00,
28170x25,0xa2,0x00,0x40,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,
28180x00,0x82,0x20,0x23,0x00,0xc7,0x18,0x21,0x25,0x42,0x00,0x01,0x00,0x80,0x30,0x21,
28190xa2,0x03,0x01,0xc1,0xae,0x0b,0x01,0xcc,0xae,0x0c,0x01,0xc8,0x08,0x00,0x2a,0xc9,
28200xa2,0x02,0x01,0xc0,0x14,0x40,0xff,0x9f,0x00,0x00,0x00,0x00,0x15,0x40,0x00,0x14,
28210x24,0x02,0xc0,0x00,0x00,0xc2,0x10,0x24,0x00,0x4c,0x10,0x25,0xad,0x02,0x00,0x00,
28220xaf,0x87,0xbc,0x10,0x8d,0x05,0x00,0x00,0x00,0x07,0x18,0xc2,0x3c,0x02,0x00,0x80,
28230x00,0x03,0x1a,0x00,0x3c,0x04,0xb0,0x06,0xaf,0x85,0xbc,0x18,0x00,0x62,0x18,0x25,
28240x34,0x84,0x80,0x18,0x8d,0x05,0x00,0x04,0xac,0x83,0x00,0x00,0x8e,0x02,0x01,0xa8,
28250x8e,0x09,0x01,0xac,0xaf,0x85,0xbc,0x14,0x08,0x00,0x2a,0xc2,0x24,0x44,0x00,0x01,
28260x01,0x6c,0x10,0x21,0x30,0x45,0x00,0xff,0x92,0x04,0x01,0xc1,0x00,0x02,0x12,0x02,
28270x30,0x46,0x00,0xff,0x38,0xa5,0x00,0x00,0x24,0x42,0x00,0x01,0x92,0x03,0x01,0xd5,
28280x00,0xc5,0x10,0x0a,0x00,0x82,0x20,0x21,0x00,0x64,0x18,0x2a,0x10,0x60,0xff,0xca,
28290x01,0x80,0x28,0x21,0x08,0x00,0x2b,0x6b,0x02,0x00,0x20,0x21,0x90,0x87,0x01,0xc0,
28300x00,0x00,0x00,0x00,0x10,0xe0,0xff,0x06,0x00,0x00,0x28,0x21,0x3c,0x02,0xb0,0x03,
28310x34,0x42,0x01,0x08,0x94,0x83,0x01,0xd8,0x8c,0x88,0x01,0xd0,0x8c,0x45,0x00,0x00,
28320x01,0x03,0x18,0x21,0x00,0xa3,0x10,0x2b,0x10,0x40,0x00,0x0b,0x2c,0xe2,0x00,0x02,
28330x00,0xa8,0x10,0x2b,0x10,0x40,0xfe,0xf9,0x00,0xc9,0x10,0x26,0x3c,0x02,0x80,0x00,
28340x00,0x62,0x18,0x21,0x00,0xa2,0x10,0x21,0x00,0x43,0x10,0x2b,0x14,0x40,0xfe,0xf3,
28350x00,0xc9,0x10,0x26,0x2c,0xe2,0x00,0x02,0x10,0x40,0xff,0x90,0x00,0x00,0x00,0x00,
28360x24,0x02,0x00,0x01,0x14,0xe2,0xfe,0xed,0x00,0xc9,0x10,0x26,0x3c,0x03,0xb0,0x06,
28370x34,0x63,0x80,0x18,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x02,
28380x14,0x40,0xfe,0xe5,0x00,0x00,0x00,0x00,0x08,0x00,0x2b,0x6b,0x00,0x00,0x00,0x00,
28390x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01,0x34,0xc6,0x00,0x18,
28400x34,0x84,0x00,0x20,0x24,0x42,0xaf,0xa0,0x24,0x03,0xff,0x83,0xac,0x82,0x00,0x00,
28410xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8,0x3c,0x03,0xb0,0x07,
28420x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00,0x90,0x64,0x00,0x00,
28430x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01,0xa0,0x40,0x00,0x00,
28440x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07,0xa3,0xa3,0x00,0x00,
28450xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10,0x24,0x02,0x00,0x06,
28460x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38,0xa0,0xa2,0x00,0x00,
28470x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20,0xa3,0xa4,0x00,0x00,
28480xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xbf,0x20,0xa3,0xa3,0x00,0x00,
28490xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08,
2850};
2851
2852u8 rtl8190_fwdata_array[] ={
28530x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x00,0x08,0x00,
28540x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,0x00,0xab,0x00,0x72,
28550x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x02,0x76,0x01,0x3b,
28560x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f,0x01,0x3b,0x00,0x9e,
28570x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20,0x01,0x2f,0x00,0x98,
28580x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e,0x00,0x98,0x00,0x4c,
28590x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f,0x02,0x39,0x01,0x1c,
28600x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39,0x01,0x1c,0x00,0x8e,
28610x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c,0x01,0x11,0x00,0x89,
28620x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b,0x00,0x89,0x00,0x44,
28630x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e,0x02,0xab,0x02,0xab,
28640x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08,0x04,0x06,0x07,0x08,
28650x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x4c,
28660x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c,0x5f,0x64,0x61,0x74,
28670x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x64,0x45,0x4c,
28680x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,0x00,0x00,0x00,0x00,
28690x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64,
28700x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x70,
28710x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,0x00,0x00,0x00,0x00,
28720x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4f,0x76,0x00,0x00,
28730x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x0b,0x53,
28740x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x2c,
28750x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60,
28760x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x80,
28770x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x9c,
28780x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x01,0xd4,
28790x00,0x00,0x02,0x08,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,
28800x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x6f,0x00,0x00,0x03,0x40,0x00,0x00,0x03,0xa8,
28810x00,0x00,0x04,0x10,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,
28820x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08,
28830x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x74,0x80,0x00,0x07,0x88,
28840x80,0x00,0x07,0x88,0x80,0x00,0x07,0x78,0x80,0x00,0x07,0x78,0x80,0x00,0x07,0x9c,
28850x80,0x00,0x53,0xc4,0x80,0x00,0x54,0x24,0x80,0x00,0x54,0x38,0x80,0x00,0x54,0x5c,
28860x80,0x00,0x54,0x68,0x80,0x00,0x54,0xa8,0x80,0x00,0x56,0xa8,0x80,0x00,0x57,0xec,
28870x80,0x00,0x58,0x14,0x80,0x00,0x59,0x0c,0x80,0x00,0x59,0xc4,0x80,0x00,0x5a,0x6c,
28880x80,0x00,0x5a,0xe0,0x80,0x00,0x5b,0xec,0x80,0x00,0x5c,0x24,0x80,0x00,0x5c,0x38,
28890x80,0x00,0x5c,0x4c,0x80,0x00,0x5d,0x40,0x80,0x00,0x5d,0x80,0x80,0x00,0x5e,0x34,
28900x80,0x00,0x5e,0x5c,0x80,0x00,0x56,0x68,0x80,0x00,0x5e,0x78,0x80,0x00,0x88,0xf8,
28910x80,0x00,0x88,0xf8,0x80,0x00,0x88,0xf8,0x80,0x00,0x89,0x2c,0x80,0x00,0x89,0x6c,
28920x80,0x00,0x89,0xa4,0x80,0x00,0x89,0xd4,0x80,0x00,0x8a,0x10,0x80,0x00,0x8a,0x50,
28930x80,0x00,0x8a,0xb8,0x80,0x00,0x8a,0xcc,0x80,0x00,0x8b,0x08,0x80,0x00,0x8b,0x10,
28940x80,0x00,0x8b,0x4c,0x80,0x00,0x8b,0x60,0x80,0x00,0x8b,0x68,0x80,0x00,0x8b,0x70,
28950x80,0x00,0x8b,0x70,0x80,0x00,0x8b,0x70,0x80,0x00,0x8b,0x70,0x80,0x00,0x8a,0x90,
28960x80,0x00,0x8b,0xa0,0x80,0x00,0x8b,0xb4,0x80,0x00,0x88,0x54,0x80,0x00,0x8e,0xc8,
28970x80,0x00,0x8e,0xc8,0x80,0x00,0x8e,0xc8,0x80,0x00,0x8e,0xfc,0x80,0x00,0x8f,0x3c,
28980x80,0x00,0x8f,0x74,0x80,0x00,0x8f,0xa4,0x80,0x00,0x8f,0xe0,0x80,0x00,0x90,0x20,
28990x80,0x00,0x90,0x88,0x80,0x00,0x90,0x9c,0x80,0x00,0x90,0xd8,0x80,0x00,0x90,0xe0,
29000x80,0x00,0x91,0x1c,0x80,0x00,0x91,0x30,0x80,0x00,0x91,0x38,0x80,0x00,0x91,0x40,
29010x80,0x00,0x91,0x40,0x80,0x00,0x91,0x40,0x80,0x00,0x91,0x40,0x80,0x00,0x90,0x60,
29020x80,0x00,0x91,0x70,0x80,0x00,0x91,0x84,0x80,0x00,0x8d,0x00,};
2903
2904u32 Rtl8192UsbPHY_REGArray[] = {
29050x0, };
2906
2907u32 Rtl8192UsbPHY_REG_1T2RArray[] = {
29080x800,0x00000000,
29090x804,0x00000001,
29100x808,0x0000fc00,
29110x80c,0x0000001c,
29120x810,0x801010aa,
29130x814,0x008514d0,
29140x818,0x00000040,
29150x81c,0x00000000,
29160x820,0x00000004,
29170x824,0x00690000,
29180x828,0x00000004,
29190x82c,0x00e90000,
29200x830,0x00000004,
29210x834,0x00690000,
29220x838,0x00000004,
29230x83c,0x00e90000,
29240x840,0x00000000,
29250x844,0x00000000,
29260x848,0x00000000,
29270x84c,0x00000000,
29280x850,0x00000000,
29290x854,0x00000000,
29300x858,0x65a965a9,
29310x85c,0x65a965a9,
29320x860,0x001f0010,
29330x864,0x007f0010,
29340x868,0x001f0010,
29350x86c,0x007f0010,
29360x870,0x0f100f70,
29370x874,0x0f100f70,
29380x878,0x00000000,
29390x87c,0x00000000,
29400x880,0x6870e36c,
29410x884,0xe3573600,
29420x888,0x4260c340,
29430x88c,0x0000ff00,
29440x890,0x00000000,
29450x894,0xfffffffe,
29460x898,0x4c42382f,
29470x89c,0x00656056,
29480x8b0,0x00000000,
29490x8e0,0x00000000,
29500x8e4,0x00000000,
29510x900,0x00000000,
29520x904,0x00000023,
29530x908,0x00000000,
29540x90c,0x31121311,
29550xa00,0x00d0c7d8,
29560xa04,0x811f0008,
29570xa08,0x80cd8300,
29580xa0c,0x2e62740f,
29590xa10,0x95009b78,
29600xa14,0x11145008,
29610xa18,0x00881117,
29620xa1c,0x89140fa0,
29630xa20,0x1a1b0000,
29640xa24,0x090e1317,
29650xa28,0x00000204,
29660xa2c,0x00000000,
29670xc00,0x00000040,
29680xc04,0x00005433,
29690xc08,0x000000e4,
29700xc0c,0x6c6c6c6c,
29710xc10,0x08800000,
29720xc14,0x40000100,
29730xc18,0x08000000,
29740xc1c,0x40000100,
29750xc20,0x08000000,
29760xc24,0x40000100,
29770xc28,0x08000000,
29780xc2c,0x40000100,
29790xc30,0x6de9ac44,
29800xc34,0x465c52cd,
29810xc38,0x497f5994,
29820xc3c,0x0a969764,
29830xc40,0x1f7c403f,
29840xc44,0x000100b7,
29850xc48,0xec020000,
29860xc4c,0x00000300,
29870xc50,0x69543420,
29880xc54,0x433c0094,
29890xc58,0x69543420,
29900xc5c,0x433c0094,
29910xc60,0x69543420,
29920xc64,0x433c0094,
29930xc68,0x69543420,
29940xc6c,0x433c0094,
29950xc70,0x2c7f000d,
29960xc74,0x0186175b,
29970xc78,0x0000001f,
29980xc7c,0x00b91612,
29990xc80,0x40000100,
30000xc84,0x20000000,
30010xc88,0x40000100,
30020xc8c,0x20200000,
30030xc90,0x40000100,
30040xc94,0x00000000,
30050xc98,0x40000100,
30060xc9c,0x00000000,
30070xca0,0x00492492,
30080xca4,0x00000000,
30090xca8,0x00000000,
30100xcac,0x00000000,
30110xcb0,0x00000000,
30120xcb4,0x00000000,
30130xcb8,0x00000000,
30140xcbc,0x00492492,
30150xcc0,0x00000000,
30160xcc4,0x00000000,
30170xcc8,0x00000000,
30180xccc,0x00000000,
30190xcd0,0x00000000,
30200xcd4,0x00000000,
30210xcd8,0x64b22427,
30220xcdc,0x00766932,
30230xce0,0x00222222,
30240xd00,0x00000750,
30250xd04,0x00000403,
30260xd08,0x0000907f,
30270xd0c,0x00000001,
30280xd10,0xa0633333,
30290xd14,0x33333c63,
30300xd18,0x6a8f5b6b,
30310xd1c,0x00000000,
30320xd20,0x00000000,
30330xd24,0x00000000,
30340xd28,0x00000000,
30350xd2c,0xcc979975,
30360xd30,0x00000000,
30370xd34,0x00000000,
30380xd38,0x00000000,
30390xd3c,0x00027293,
30400xd40,0x00000000,
30410xd44,0x00000000,
30420xd48,0x00000000,
30430xd4c,0x00000000,
30440xd50,0x6437140a,
30450xd54,0x024dbd02,
30460xd58,0x00000000,
30470xd5c,0x04032064,
30480xe00,0x161a1a1a,
30490xe04,0x12121416,
30500xe08,0x00001800,
30510xe0c,0x00000000,
30520xe10,0x161a1a1a,
30530xe14,0x12121416,
30540xe18,0x161a1a1a,
30550xe1c,0x12121416,
3056};
3057
3058u32 Rtl8192UsbRadioA_Array[] = {
30590x019,0x00000003,
30600x000,0x000000bf,
30610x001,0x00000ee0,
30620x002,0x0000004c,
30630x003,0x000007f1,
30640x004,0x00000975,
30650x005,0x00000c58,
30660x006,0x00000ae6,
30670x007,0x000000ca,
30680x008,0x00000e1c,
30690x009,0x000007f0,
30700x00a,0x000009d0,
30710x00b,0x000001ba,
30720x00c,0x00000240,
30730x00e,0x00000020,
30740x00f,0x00000990,
30750x012,0x00000806,
30760x014,0x000005ab,
30770x015,0x00000f80,
30780x016,0x00000020,
30790x017,0x00000597,
30800x018,0x0000050a,
30810x01a,0x00000f80,
30820x01b,0x00000f5e,
30830x01c,0x00000008,
30840x01d,0x00000607,
30850x01e,0x000006cc,
30860x01f,0x00000000,
30870x020,0x000001a5,
30880x01f,0x00000001,
30890x020,0x00000165,
30900x01f,0x00000002,
30910x020,0x000000c6,
30920x01f,0x00000003,
30930x020,0x00000086,
30940x01f,0x00000004,
30950x020,0x00000046,
30960x01f,0x00000005,
30970x020,0x000001e6,
30980x01f,0x00000006,
30990x020,0x000001a6,
31000x01f,0x00000007,
31010x020,0x00000166,
31020x01f,0x00000008,
31030x020,0x000000c7,
31040x01f,0x00000009,
31050x020,0x00000087,
31060x01f,0x0000000a,
31070x020,0x000000f7,
31080x01f,0x0000000b,
31090x020,0x000000d7,
31100x01f,0x0000000c,
31110x020,0x000000b7,
31120x01f,0x0000000d,
31130x020,0x00000097,
31140x01f,0x0000000e,
31150x020,0x00000077,
31160x01f,0x0000000f,
31170x020,0x00000057,
31180x01f,0x00000010,
31190x020,0x00000037,
31200x01f,0x00000011,
31210x020,0x000000fb,
31220x01f,0x00000012,
31230x020,0x000000db,
31240x01f,0x00000013,
31250x020,0x000000bb,
31260x01f,0x00000014,
31270x020,0x000000ff,
31280x01f,0x00000015,
31290x020,0x000000e3,
31300x01f,0x00000016,
31310x020,0x000000c3,
31320x01f,0x00000017,
31330x020,0x000000a3,
31340x01f,0x00000018,
31350x020,0x00000083,
31360x01f,0x00000019,
31370x020,0x00000063,
31380x01f,0x0000001a,
31390x020,0x00000043,
31400x01f,0x0000001b,
31410x020,0x00000023,
31420x01f,0x0000001c,
31430x020,0x00000003,
31440x01f,0x0000001d,
31450x020,0x000001e3,
31460x01f,0x0000001e,
31470x020,0x000001c3,
31480x01f,0x0000001f,
31490x020,0x000001a3,
31500x01f,0x00000020,
31510x020,0x00000183,
31520x01f,0x00000021,
31530x020,0x00000163,
31540x01f,0x00000022,
31550x020,0x00000143,
31560x01f,0x00000023,
31570x020,0x00000123,
31580x01f,0x00000024,
31590x020,0x00000103,
31600x023,0x00000203,
31610x024,0x00000200,
31620x00b,0x000001ba,
31630x02c,0x000003d7,
31640x02d,0x00000ff0,
31650x000,0x00000037,
31660x004,0x00000160,
31670x007,0x00000080,
31680x002,0x0000088d,
31690x0fe,0x00000000,
31700x0fe,0x00000000,
31710x016,0x00000200,
31720x016,0x00000380,
31730x016,0x00000020,
31740x016,0x000001a0,
31750x000,0x000000bf,
31760x00d,0x0000001f,
31770x00d,0x00000c9f,
31780x002,0x0000004d,
31790x000,0x00000cbf,
31800x004,0x00000975,
31810x007,0x00000700,
3182};
3183
3184u32 Rtl8192UsbRadioB_Array[] = {
31850x019,0x00000003,
31860x000,0x000000bf,
31870x001,0x000006e0,
31880x002,0x0000004c,
31890x003,0x000007f1,
31900x004,0x00000975,
31910x005,0x00000c58,
31920x006,0x00000ae6,
31930x007,0x000000ca,
31940x008,0x00000e1c,
31950x000,0x000000b7,
31960x00a,0x00000850,
31970x000,0x000000bf,
31980x00b,0x000001ba,
31990x00c,0x00000240,
32000x00e,0x00000020,
32010x015,0x00000f80,
32020x016,0x00000020,
32030x017,0x00000597,
32040x018,0x0000050a,
32050x01a,0x00000e00,
32060x01b,0x00000f5e,
32070x01d,0x00000607,
32080x01e,0x000006cc,
32090x00b,0x000001ba,
32100x023,0x00000203,
32110x024,0x00000200,
32120x000,0x00000037,
32130x004,0x00000160,
32140x016,0x00000200,
32150x016,0x00000380,
32160x016,0x00000020,
32170x016,0x000001a0,
32180x00d,0x00000ccc,
32190x000,0x000000bf,
32200x002,0x0000004d,
32210x000,0x00000cbf,
32220x004,0x00000975,
32230x007,0x00000700,
3224};
3225
3226u32 Rtl8192UsbRadioC_Array[] = {
32270x0, };
3228
3229u32 Rtl8192UsbRadioD_Array[] = {
32300x0, };
3231
3232u32 Rtl8192UsbMACPHY_Array[] = {
32330x03c,0xffff0000,0x00000f0f,
32340x340,0xffffffff,0x161a1a1a,
32350x344,0xffffffff,0x12121416,
32360x348,0x0000ffff,0x00001818,
32370x12c,0xffffffff,0x04000802,
32380x318,0x00000fff,0x00000100,
3239};
3240
3241u32 Rtl8192UsbMACPHY_Array_PG[] = {
32420x03c,0xffff0000,0x00000f0f,
32430xe00,0xffffffff,0x06090909,
32440xe04,0xffffffff,0x00030306,
32450xe08,0x0000ff00,0x00000000,
32460xe10,0xffffffff,0x0a0c0d0f,
32470xe14,0xffffffff,0x06070809,
32480xe18,0xffffffff,0x0a0c0d0f,
32490xe1c,0xffffffff,0x06070809,
32500x12c,0xffffffff,0x04000802,
32510x318,0x00000fff,0x00000800,
3252};
3253
3254u32 Rtl8192UsbAGCTAB_Array[] = {
32550xc78,0x7d000001,
32560xc78,0x7d010001,
32570xc78,0x7d020001,
32580xc78,0x7d030001,
32590xc78,0x7d040001,
32600xc78,0x7d050001,
32610xc78,0x7c060001,
32620xc78,0x7b070001,
32630xc78,0x7a080001,
32640xc78,0x79090001,
32650xc78,0x780a0001,
32660xc78,0x770b0001,
32670xc78,0x760c0001,
32680xc78,0x750d0001,
32690xc78,0x740e0001,
32700xc78,0x730f0001,
32710xc78,0x72100001,
32720xc78,0x71110001,
32730xc78,0x70120001,
32740xc78,0x6f130001,
32750xc78,0x6e140001,
32760xc78,0x6d150001,
32770xc78,0x6c160001,
32780xc78,0x6b170001,
32790xc78,0x6a180001,
32800xc78,0x69190001,
32810xc78,0x681a0001,
32820xc78,0x671b0001,
32830xc78,0x661c0001,
32840xc78,0x651d0001,
32850xc78,0x641e0001,
32860xc78,0x491f0001,
32870xc78,0x48200001,
32880xc78,0x47210001,
32890xc78,0x46220001,
32900xc78,0x45230001,
32910xc78,0x44240001,
32920xc78,0x43250001,
32930xc78,0x28260001,
32940xc78,0x27270001,
32950xc78,0x26280001,
32960xc78,0x25290001,
32970xc78,0x242a0001,
32980xc78,0x232b0001,
32990xc78,0x222c0001,
33000xc78,0x212d0001,
33010xc78,0x202e0001,
33020xc78,0x0a2f0001,
33030xc78,0x08300001,
33040xc78,0x06310001,
33050xc78,0x05320001,
33060xc78,0x04330001,
33070xc78,0x03340001,
33080xc78,0x02350001,
33090xc78,0x01360001,
33100xc78,0x00370001,
33110xc78,0x00380001,
33120xc78,0x00390001,
33130xc78,0x003a0001,
33140xc78,0x003b0001,
33150xc78,0x003c0001,
33160xc78,0x003d0001,
33170xc78,0x003e0001,
33180xc78,0x003f0001,
33190xc78,0x7d400001,
33200xc78,0x7d410001,
33210xc78,0x7d420001,
33220xc78,0x7d430001,
33230xc78,0x7d440001,
33240xc78,0x7d450001,
33250xc78,0x7c460001,
33260xc78,0x7b470001,
33270xc78,0x7a480001,
33280xc78,0x79490001,
33290xc78,0x784a0001,
33300xc78,0x774b0001,
33310xc78,0x764c0001,
33320xc78,0x754d0001,
33330xc78,0x744e0001,
33340xc78,0x734f0001,
33350xc78,0x72500001,
33360xc78,0x71510001,
33370xc78,0x70520001,
33380xc78,0x6f530001,
33390xc78,0x6e540001,
33400xc78,0x6d550001,
33410xc78,0x6c560001,
33420xc78,0x6b570001,
33430xc78,0x6a580001,
33440xc78,0x69590001,
33450xc78,0x685a0001,
33460xc78,0x675b0001,
33470xc78,0x665c0001,
33480xc78,0x655d0001,
33490xc78,0x645e0001,
33500xc78,0x495f0001,
33510xc78,0x48600001,
33520xc78,0x47610001,
33530xc78,0x46620001,
33540xc78,0x45630001,
33550xc78,0x44640001,
33560xc78,0x43650001,
33570xc78,0x28660001,
33580xc78,0x27670001,
33590xc78,0x26680001,
33600xc78,0x25690001,
33610xc78,0x246a0001,
33620xc78,0x236b0001,
33630xc78,0x226c0001,
33640xc78,0x216d0001,
33650xc78,0x206e0001,
33660xc78,0x0a6f0001,
33670xc78,0x08700001,
33680xc78,0x06710001,
33690xc78,0x05720001,
33700xc78,0x04730001,
33710xc78,0x03740001,
33720xc78,0x02750001,
33730xc78,0x01760001,
33740xc78,0x00770001,
33750xc78,0x00780001,
33760xc78,0x00790001,
33770xc78,0x007a0001,
33780xc78,0x007b0001,
33790xc78,0x007c0001,
33800xc78,0x007d0001,
33810xc78,0x007e0001,
33820xc78,0x007f0001,
33830xc78,0x2e00001e,
33840xc78,0x2e01001e,
33850xc78,0x2e02001e,
33860xc78,0x2e03001e,
33870xc78,0x2e04001e,
33880xc78,0x2e05001e,
33890xc78,0x3006001e,
33900xc78,0x3407001e,
33910xc78,0x3908001e,
33920xc78,0x3c09001e,
33930xc78,0x3f0a001e,
33940xc78,0x420b001e,
33950xc78,0x440c001e,
33960xc78,0x450d001e,
33970xc78,0x460e001e,
33980xc78,0x460f001e,
33990xc78,0x4710001e,
34000xc78,0x4811001e,
34010xc78,0x4912001e,
34020xc78,0x4a13001e,
34030xc78,0x4b14001e,
34040xc78,0x4b15001e,
34050xc78,0x4c16001e,
34060xc78,0x4d17001e,
34070xc78,0x4e18001e,
34080xc78,0x4f19001e,
34090xc78,0x4f1a001e,
34100xc78,0x501b001e,
34110xc78,0x511c001e,
34120xc78,0x521d001e,
34130xc78,0x521e001e,
34140xc78,0x531f001e,
34150xc78,0x5320001e,
34160xc78,0x5421001e,
34170xc78,0x5522001e,
34180xc78,0x5523001e,
34190xc78,0x5624001e,
34200xc78,0x5725001e,
34210xc78,0x5726001e,
34220xc78,0x5827001e,
34230xc78,0x5828001e,
34240xc78,0x5929001e,
34250xc78,0x592a001e,
34260xc78,0x5a2b001e,
34270xc78,0x5b2c001e,
34280xc78,0x5c2d001e,
34290xc78,0x5c2e001e,
34300xc78,0x5d2f001e,
34310xc78,0x5e30001e,
34320xc78,0x5f31001e,
34330xc78,0x6032001e,
34340xc78,0x6033001e,
34350xc78,0x6134001e,
34360xc78,0x6235001e,
34370xc78,0x6336001e,
34380xc78,0x6437001e,
34390xc78,0x6438001e,
34400xc78,0x6539001e,
34410xc78,0x663a001e,
34420xc78,0x673b001e,
34430xc78,0x673c001e,
34440xc78,0x683d001e,
34450xc78,0x693e001e,
34460xc78,0x6a3f001e,
3447};
diff --git a/drivers/staging/rtl8192su/r819xU_firmware_img.h b/drivers/staging/rtl8192su/r819xU_firmware_img.h
new file mode 100644
index 00000000000..d9d9515a1e6
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_firmware_img.h
@@ -0,0 +1,35 @@
1#ifndef IMG_H
2#define IMG_H
3
4#define BOOT_ARR_LEN 344
5#define MAIN_ARR_LEN 45136
6#define DATA_ARR_LEN 796
7#define MACPHY_Array_PGLength 30
8#define PHY_REG_1T2RArrayLength 296
9#define AGCTAB_ArrayLength 384
10#define MACPHY_ArrayLength 18
11
12#define RadioA_ArrayLength 246
13#define RadioB_ArrayLength 78
14#define RadioC_ArrayLength 1
15#define RadioD_ArrayLength 1
16#define PHY_REGArrayLength 1
17
18
19extern u8 rtl8190_fwboot_array[BOOT_ARR_LEN];
20extern u8 rtl8190_fwmain_array[MAIN_ARR_LEN];
21extern u8 rtl8190_fwdata_array[DATA_ARR_LEN];
22
23extern u32 Rtl8192UsbPHY_REGArray[];
24extern u32 Rtl8192UsbPHY_REG_1T2RArray[];
25extern u32 Rtl8192UsbRadioA_Array[];
26extern u32 Rtl8192UsbRadioB_Array[];
27extern u32 Rtl8192UsbRadioC_Array[];
28extern u32 Rtl8192UsbRadioD_Array[];
29extern u32 Rtl8192UsbMACPHY_Array[];
30extern u32 Rtl8192UsbMACPHY_Array_PG[];
31extern u32 Rtl8192UsbAGCTAB_Array[];
32
33
34
35#endif
diff --git a/drivers/staging/rtl8192su/r819xU_phy.c b/drivers/staging/rtl8192su/r819xU_phy.c
new file mode 100644
index 00000000000..00497d313f9
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_phy.c
@@ -0,0 +1,1826 @@
1#include "r8192U.h"
2#include "r8192U_hw.h"
3#include "r819xU_phy.h"
4#include "r819xU_phyreg.h"
5#include "r8190_rtl8256.h"
6#include "r8192U_dm.h"
7#include "r819xU_firmware_img.h"
8
9#ifdef ENABLE_DOT11D
10#include "dot11d.h"
11#endif
12static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
13 0,
14 0x085c, //2412 1
15 0x08dc, //2417 2
16 0x095c, //2422 3
17 0x09dc, //2427 4
18 0x0a5c, //2432 5
19 0x0adc, //2437 6
20 0x0b5c, //2442 7
21 0x0bdc, //2447 8
22 0x0c5c, //2452 9
23 0x0cdc, //2457 10
24 0x0d5c, //2462 11
25 0x0ddc, //2467 12
26 0x0e5c, //2472 13
27 0x0f72, //2484
28};
29
30
31#define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32#define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33#define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34#define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35#define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36#define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37#define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38#define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
39
40/******************************************************************************
41 *function: This function read BB parameters from Header file we gen,
42 * and do register read/write
43 * input: u32 dwBitMask //taget bit pos in the addr to be modified
44 * output: none
45 * return: u32 return the shift bit bit position of the mask
46 * ****************************************************************************/
47u32 rtl8192_CalculateBitShift(u32 dwBitMask)
48{
49 u32 i;
50 for (i=0; i<=31; i++)
51 {
52 if (((dwBitMask>>i)&0x1) == 1)
53 break;
54 }
55 return i;
56}
57/******************************************************************************
58 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
59 * input: none
60 * output: none
61 * return: 0(illegal, false), 1(legal,true)
62 * ***************************************************************************/
63u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
64{
65 u8 ret = 1;
66 struct r8192_priv *priv = ieee80211_priv(dev);
67 if (priv->rf_type == RF_2T4R)
68 ret = 0;
69 else if (priv->rf_type == RF_1T2R)
70 {
71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
72 ret = 1;
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
74 ret = 0;
75 }
76 return ret;
77}
78/******************************************************************************
79 *function: This function set specific bits to BB register
80 * input: net_device dev
81 * u32 dwRegAddr //target addr to be modified
82 * u32 dwBitMask //taget bit pos in the addr to be modified
83 * u32 dwData //value to be write
84 * output: none
85 * return: none
86 * notice:
87 * ****************************************************************************/
88void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
89{
90
91 u32 OriginalValue, BitShift, NewValue;
92
93 if(dwBitMask!= bMaskDWord)
94 {//if not "double word" write
95 OriginalValue = read_nic_dword(dev, dwRegAddr);
96 BitShift = rtl8192_CalculateBitShift(dwBitMask);
97 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
98 write_nic_dword(dev, dwRegAddr, NewValue);
99 }else
100 write_nic_dword(dev, dwRegAddr, dwData);
101 return;
102}
103/******************************************************************************
104 *function: This function reads specific bits from BB register
105 * input: net_device dev
106 * u32 dwRegAddr //target addr to be readback
107 * u32 dwBitMask //taget bit pos in the addr to be readback
108 * output: none
109 * return: u32 Data //the readback register value
110 * notice:
111 * ****************************************************************************/
112u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
113{
114 u32 Ret = 0, OriginalValue, BitShift;
115
116 OriginalValue = read_nic_dword(dev, dwRegAddr);
117 BitShift = rtl8192_CalculateBitShift(dwBitMask);
118 Ret =(OriginalValue & dwBitMask) >> BitShift;
119
120 return (Ret);
121}
122static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset );
123
124static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
125
126/******************************************************************************
127 *function: This function read register from RF chip
128 * input: net_device dev
129 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
130 * u32 Offset //target address to be read
131 * output: none
132 * return: u32 readback value
133 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
134 * ****************************************************************************/
135u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
136{
137 struct r8192_priv *priv = ieee80211_priv(dev);
138 u32 ret = 0;
139 u32 NewOffset = 0;
140 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
141 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
142 //make sure RF register offset is correct
143 Offset &= 0x3f;
144
145 //switch page for 8256 RF IC
146 if (priv->rf_chip == RF_8256)
147 {
148 if (Offset >= 31)
149 {
150 priv->RfReg0Value[eRFPath] |= 0x140;
151 //Switch to Reg_Mode2 for Reg 31-45
152 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
153 //modify offset
154 NewOffset = Offset -30;
155 }
156 else if (Offset >= 16)
157 {
158 priv->RfReg0Value[eRFPath] |= 0x100;
159 priv->RfReg0Value[eRFPath] &= (~0x40);
160 //Switch to Reg_Mode 1 for Reg16-30
161 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
162
163 NewOffset = Offset - 15;
164 }
165 else
166 NewOffset = Offset;
167 }
168 else
169 {
170 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
171 NewOffset = Offset;
172 }
173 //put desired read addr to LSSI control Register
174 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
175 //Issue a posedge trigger
176 //
177 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
178 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
179
180
181 // TODO: we should not delay such a long time. Ask help from SD3
182 msleep(1);
183
184 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
185
186
187 // Switch back to Reg_Mode0;
188 if(priv->rf_chip == RF_8256)
189 {
190 priv->RfReg0Value[eRFPath] &= 0xebf;
191
192 rtl8192_setBBreg(
193 dev,
194 pPhyReg->rf3wireOffset,
195 bMaskDWord,
196 (priv->RfReg0Value[eRFPath] << 16));
197 }
198
199 return ret;
200
201}
202
203/******************************************************************************
204 *function: This function write data to RF register
205 * input: net_device dev
206 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
207 * u32 Offset //target address to be written
208 * u32 Data //The new register data to be written
209 * output: none
210 * return: none
211 * notice: For RF8256 only.
212 ===========================================================
213 *Reg Mode RegCTL[1] RegCTL[0] Note
214 * (Reg00[12]) (Reg00[10])
215 *===========================================================
216 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
217 *------------------------------------------------------------------
218 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
219 *------------------------------------------------------------------
220 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
221 *------------------------------------------------------------------
222 * ****************************************************************************/
223void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
224{
225 struct r8192_priv *priv = ieee80211_priv(dev);
226 u32 DataAndAddr = 0, NewOffset = 0;
227 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
228
229 Offset &= 0x3f;
230 //spin_lock_irqsave(&priv->rf_lock, flags);
231// down(&priv->rf_sem);
232 if (priv->rf_chip == RF_8256)
233 {
234
235 if (Offset >= 31)
236 {
237 priv->RfReg0Value[eRFPath] |= 0x140;
238 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
239 NewOffset = Offset - 30;
240 }
241 else if (Offset >= 16)
242 {
243 priv->RfReg0Value[eRFPath] |= 0x100;
244 priv->RfReg0Value[eRFPath] &= (~0x40);
245 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
246 NewOffset = Offset - 15;
247 }
248 else
249 NewOffset = Offset;
250 }
251 else
252 {
253 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
254 NewOffset = Offset;
255 }
256
257 // Put write addr in [5:0] and write data in [31:16]
258 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
259
260 // Write Operation
261 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
262
263
264 if(Offset==0x0)
265 priv->RfReg0Value[eRFPath] = Data;
266
267 // Switch back to Reg_Mode0;
268 if(priv->rf_chip == RF_8256)
269 {
270 if(Offset != 0)
271 {
272 priv->RfReg0Value[eRFPath] &= 0xebf;
273 rtl8192_setBBreg(
274 dev,
275 pPhyReg->rf3wireOffset,
276 bMaskDWord,
277 (priv->RfReg0Value[eRFPath] << 16));
278 }
279 }
280 //spin_unlock_irqrestore(&priv->rf_lock, flags);
281// up(&priv->rf_sem);
282 return;
283}
284
285/******************************************************************************
286 *function: This function set specific bits to RF register
287 * input: net_device dev
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
289 * u32 RegAddr //target addr to be modified
290 * u32 BitMask //taget bit pos in the addr to be modified
291 * u32 Data //value to be write
292 * output: none
293 * return: none
294 * notice:
295 * ****************************************************************************/
296void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
297{
298 struct r8192_priv *priv = ieee80211_priv(dev);
299 u32 Original_Value, BitShift, New_Value;
300// u8 time = 0;
301
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
303 return;
304
305 if (priv->Rf_Mode == RF_OP_By_FW)
306 {
307 if (BitMask != bMask12Bits) // RF data is 12 bits only
308 {
309 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
310 BitShift = rtl8192_CalculateBitShift(BitMask);
311 New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift);
312
313 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
314 }else
315 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
316
317 udelay(200);
318
319 }
320 else
321 {
322 if (BitMask != bMask12Bits) // RF data is 12 bits only
323 {
324 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
325 BitShift = rtl8192_CalculateBitShift(BitMask);
326 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
327
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
329 }else
330 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
331 }
332 return;
333}
334
335/******************************************************************************
336 *function: This function reads specific bits from RF register
337 * input: net_device dev
338 * u32 RegAddr //target addr to be readback
339 * u32 BitMask //taget bit pos in the addr to be readback
340 * output: none
341 * return: u32 Data //the readback register value
342 * notice:
343 * ****************************************************************************/
344u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
345{
346 u32 Original_Value, Readback_Value, BitShift;
347 struct r8192_priv *priv = ieee80211_priv(dev);
348
349
350 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
351 return 0;
352 if (priv->Rf_Mode == RF_OP_By_FW)
353 {
354 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
355 BitShift = rtl8192_CalculateBitShift(BitMask);
356 Readback_Value = (Original_Value & BitMask) >> BitShift;
357 udelay(200);
358 return (Readback_Value);
359 }
360 else
361 {
362 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
363 BitShift = rtl8192_CalculateBitShift(BitMask);
364 Readback_Value = (Original_Value & BitMask) >> BitShift;
365 return (Readback_Value);
366 }
367}
368/******************************************************************************
369 *function: We support firmware to execute RF-R/W.
370 * input: dev
371 * output: none
372 * return: none
373 * notice:
374 * ***************************************************************************/
375static u32
376phy_FwRFSerialRead(
377 struct net_device* dev,
378 RF90_RADIO_PATH_E eRFPath,
379 u32 Offset )
380{
381 u32 retValue = 0;
382 u32 Data = 0;
383 u8 time = 0;
384 //DbgPrint("FW RF CTRL\n\r");
385 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
386 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
387 much time. This is only for site survey. */
388 // 1. Read operation need not insert data. bit 0-11
389 //Data &= bMask12Bits;
390 // 2. Write RF register address. Bit 12-19
391 Data |= ((Offset&0xFF)<<12);
392 // 3. Write RF path. bit 20-21
393 Data |= ((eRFPath&0x3)<<20);
394 // 4. Set RF read indicator. bit 22=0
395 //Data |= 0x00000;
396 // 5. Trigger Fw to operate the command. bit 31
397 Data |= 0x80000000;
398 // 6. We can not execute read operation if bit 31 is 1.
399 while (read_nic_dword(dev, QPNR)&0x80000000)
400 {
401 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
402 if (time++ < 100)
403 {
404 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
405 udelay(10);
406 }
407 else
408 break;
409 }
410 // 7. Execute read operation.
411 write_nic_dword(dev, QPNR, Data);
412 // 8. Check if firmawre send back RF content.
413 while (read_nic_dword(dev, QPNR)&0x80000000)
414 {
415 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
416 if (time++ < 100)
417 {
418 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
419 udelay(10);
420 }
421 else
422 return (0);
423 }
424 retValue = read_nic_dword(dev, RF_DATA);
425
426 return (retValue);
427
428} /* phy_FwRFSerialRead */
429
430/******************************************************************************
431 *function: We support firmware to execute RF-R/W.
432 * input: dev
433 * output: none
434 * return: none
435 * notice:
436 * ***************************************************************************/
437static void
438phy_FwRFSerialWrite(
439 struct net_device* dev,
440 RF90_RADIO_PATH_E eRFPath,
441 u32 Offset,
442 u32 Data )
443{
444 u8 time = 0;
445
446 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
447 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
448 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
449 much time. This is only for site survey. */
450
451 // 1. Set driver write bit and 12 bit data. bit 0-11
452 //Data &= bMask12Bits; // Done by uper layer.
453 // 2. Write RF register address. bit 12-19
454 Data |= ((Offset&0xFF)<<12);
455 // 3. Write RF path. bit 20-21
456 Data |= ((eRFPath&0x3)<<20);
457 // 4. Set RF write indicator. bit 22=1
458 Data |= 0x400000;
459 // 5. Trigger Fw to operate the command. bit 31=1
460 Data |= 0x80000000;
461
462 // 6. Write operation. We can not write if bit 31 is 1.
463 while (read_nic_dword(dev, QPNR)&0x80000000)
464 {
465 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
466 if (time++ < 100)
467 {
468 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
469 udelay(10);
470 }
471 else
472 break;
473 }
474 // 7. No matter check bit. We always force the write. Because FW will
475 // not accept the command.
476 write_nic_dword(dev, QPNR, Data);
477 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
478 to finish RF write operation. */
479 /* 2008/01/17 MH We support delay in firmware side now. */
480 //delay_us(20);
481
482} /* phy_FwRFSerialWrite */
483
484
485/******************************************************************************
486 *function: This function read BB parameters from Header file we gen,
487 * and do register read/write
488 * input: dev
489 * output: none
490 * return: none
491 * notice: BB parameters may change all the time, so please make
492 * sure it has been synced with the newest.
493 * ***************************************************************************/
494void rtl8192_phy_configmac(struct net_device* dev)
495{
496 u32 dwArrayLen = 0, i;
497 u32* pdwArray = NULL;
498 struct r8192_priv *priv = ieee80211_priv(dev);
499
500 if(priv->btxpowerdata_readfromEEPORM)
501 {
502 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
503 dwArrayLen = MACPHY_Array_PGLength;
504 pdwArray = rtl819XMACPHY_Array_PG;
505
506 }
507 else
508 {
509 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
510 dwArrayLen = MACPHY_ArrayLength;
511 pdwArray = rtl819XMACPHY_Array;
512 }
513 for(i = 0; i<dwArrayLen; i=i+3){
514 if(pdwArray[i] == 0x318)
515 {
516 pdwArray[i+2] = 0x00000800;
517 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
518 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
519 }
520
521 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
522 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
523 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
524 }
525 return;
526
527}
528
529/******************************************************************************
530 *function: This function do dirty work
531 * input: dev
532 * output: none
533 * return: none
534 * notice: BB parameters may change all the time, so please make
535 * sure it has been synced with the newest.
536 * ***************************************************************************/
537
538void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
539{
540 u32 i;
541
542#ifdef TO_DO_LIST
543 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
544 if(Adapter->bInHctTest)
545 {
546 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
547 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
548 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
549 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
550 }
551#endif
552 if (ConfigType == BaseBand_Config_PHY_REG)
553 {
554 for (i=0; i<PHY_REG_1T2RArrayLength; i+=2)
555 {
556 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]);
557 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]);
558 }
559 }
560 else if (ConfigType == BaseBand_Config_AGC_TAB)
561 {
562 for (i=0; i<AGCTAB_ArrayLength; i+=2)
563 {
564 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]);
565 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]);
566 }
567 }
568 return;
569
570
571}
572/******************************************************************************
573 *function: This function initialize Register definition offset for Radio Path
574 * A/B/C/D
575 * input: net_device dev
576 * output: none
577 * return: none
578 * notice: Initialization value here is constant and it should never be changed
579 * ***************************************************************************/
580void rtl8192_InitBBRFRegDef(struct net_device* dev)
581{
582 struct r8192_priv *priv = ieee80211_priv(dev);
583// RF Interface Sowrtware Control
584 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
585 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
586 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
587 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
588
589 // RF Interface Readback Value
590 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
591 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
592 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
593 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
594
595 // RF Interface Output (and Enable)
596 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
597 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
598 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
599 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
600
601 // RF Interface (Output and) Enable
602 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
603 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
604 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
605 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
606
607 //Addr of LSSI. Wirte RF register by driver
608 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
609 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
610 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
611 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
612
613 // RF parameter
614 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
615 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
616 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
617 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
618
619 // Tx AGC Gain Stage (same for all path. Should we remove this?)
620 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
621 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
622 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
623 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
624
625 // Tranceiver A~D HSSI Parameter-1
626 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
627 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
628 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
629 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
630
631 // Tranceiver A~D HSSI Parameter-2
632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
633 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
634 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
635 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
636
637 // RF switch Control
638 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
639 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
640 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
641 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
642
643 // AGC control 1
644 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
645 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
646 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
647 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
648
649 // AGC control 2
650 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
651 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
652 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
653 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
654
655 // RX AFE control 1
656 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
657 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
658 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
659 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
660
661 // RX AFE control 1
662 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
663 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
664 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
665 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
666
667 // Tx AFE control 1
668 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
669 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
670 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
671 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
672
673 // Tx AFE control 2
674 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
675 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
676 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
677 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
678
679 // Tranceiver LSSI Readback
680 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
681 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
682 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
683 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
684
685}
686/******************************************************************************
687 *function: This function is to write register and then readback to make sure whether BB and RF is OK
688 * input: net_device dev
689 * HW90_BLOCK_E CheckBlock
690 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
691 * output: none
692 * return: return whether BB and RF is ok(0:OK; 1:Fail)
693 * notice: This function may be removed in the ASIC
694 * ***************************************************************************/
695u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
696{
697// struct r8192_priv *priv = ieee80211_priv(dev);
698// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
699 u8 ret = 0;
700 u32 i, CheckTimes = 4, dwRegRead = 0;
701 u32 WriteAddr[4];
702 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
703 // Initialize register address offset to be checked
704 WriteAddr[HW90_BLOCK_MAC] = 0x100;
705 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
706 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
707 WriteAddr[HW90_BLOCK_RF] = 0x3;
708 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
709 for(i=0 ; i < CheckTimes ; i++)
710 {
711
712 //
713 // Write Data to register and readback
714 //
715 switch(CheckBlock)
716 {
717 case HW90_BLOCK_MAC:
718 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
719 break;
720
721 case HW90_BLOCK_PHY0:
722 case HW90_BLOCK_PHY1:
723 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
724 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
725 break;
726
727 case HW90_BLOCK_RF:
728 WriteData[i] &= 0xfff;
729 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
730 // TODO: we should not delay for such a long time. Ask SD3
731 msleep(1);
732 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
733 msleep(1);
734 break;
735
736 default:
737 ret = 1;
738 break;
739 }
740
741
742 //
743 // Check whether readback data is correct
744 //
745 if(dwRegRead != WriteData[i])
746 {
747 RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
748 ret = 1;
749 break;
750 }
751 }
752
753 return ret;
754}
755
756
757/******************************************************************************
758 *function: This function initialize BB&RF
759 * input: net_device dev
760 * output: none
761 * return: none
762 * notice: Initialization value may change all the time, so please make
763 * sure it has been synced with the newest.
764 * ***************************************************************************/
765void rtl8192_BB_Config_ParaFile(struct net_device* dev)
766{
767 struct r8192_priv *priv = ieee80211_priv(dev);
768 u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0;
769 u32 dwRegValue = 0;
770 /**************************************
771 //<1>Initialize BaseBand
772 **************************************/
773
774 /*--set BB Global Reset--*/
775 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
776 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
777 mdelay(50);
778 /*---set BB reset Active---*/
779 dwRegValue = read_nic_dword(dev, CPU_GEN);
780 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
781
782 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
783 // TODO: this function should be removed on ASIC , Emily 2007.2.2
784 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
785 {
786 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
787 if(rtStatus != 0)
788 {
789 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
790 return ;
791 }
792 }
793 /*---- Set CCK and OFDM Block "OFF"----*/
794 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
795 /*----BB Register Initilazation----*/
796 //==m==>Set PHY REG From Header<==m==
797 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
798
799 /*----Set BB reset de-Active----*/
800 dwRegValue = read_nic_dword(dev, CPU_GEN);
801 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
802
803 /*----BB AGC table Initialization----*/
804 //==m==>Set PHY REG From Header<==m==
805 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
806
807 /*----Enable XSTAL ----*/
808 write_nic_byte_E(dev, 0x5e, 0x00);
809 if (priv->card_8192_version == (u8)VERSION_819xU_A)
810 {
811 //Antenna gain offset from B/C/D to A
812 dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
813 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
814
815 //XSTALLCap
816 dwRegValue = priv->CrystalCap & 0xf;
817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
818 }
819
820 // Check if the CCK HighPower is turned ON.
821 // This is used to calculate PWDB.
822 priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
823 return;
824}
825/******************************************************************************
826 *function: This function initialize BB&RF
827 * input: net_device dev
828 * output: none
829 * return: none
830 * notice: Initialization value may change all the time, so please make
831 * sure it has been synced with the newest.
832 * ***************************************************************************/
833void rtl8192_BBConfig(struct net_device* dev)
834{
835 rtl8192_InitBBRFRegDef(dev);
836 //config BB&RF. As hardCode based initialization has not been well
837 //implemented, so use file first.FIXME:should implement it for hardcode?
838 rtl8192_BB_Config_ParaFile(dev);
839 return;
840}
841
842/******************************************************************************
843 *function: This function obtains the initialization value of Tx power Level offset
844 * input: net_device dev
845 * output: none
846 * return: none
847 * ***************************************************************************/
848void rtl8192_phy_getTxPower(struct net_device* dev)
849{
850 struct r8192_priv *priv = ieee80211_priv(dev);
851 priv->MCSTxPowerLevelOriginalOffset[0] =
852 read_nic_dword(dev, rTxAGC_Rate18_06);
853 priv->MCSTxPowerLevelOriginalOffset[1] =
854 read_nic_dword(dev, rTxAGC_Rate54_24);
855 priv->MCSTxPowerLevelOriginalOffset[2] =
856 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
857 priv->MCSTxPowerLevelOriginalOffset[3] =
858 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
859 priv->MCSTxPowerLevelOriginalOffset[4] =
860 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
861 priv->MCSTxPowerLevelOriginalOffset[5] =
862 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
863
864 // read rx initial gain
865 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
866 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
867 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
868 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
869 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
870 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
871 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
872
873 // read framesync
874 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
875 priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2);
876 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
877 rOFDM0_RxDetector3, priv->framesync);
878
879 // read SIFS (save the value read fome MACPHY_REG.txt)
880 priv->SifsTime = read_nic_word(dev, SIFS);
881
882 return;
883}
884
885/******************************************************************************
886 *function: This function obtains the initialization value of Tx power Level offset
887 * input: net_device dev
888 * output: none
889 * return: none
890 * ***************************************************************************/
891void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
892{
893 struct r8192_priv *priv = ieee80211_priv(dev);
894 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
895 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
896
897 switch(priv->rf_chip)
898 {
899 case RF_8256:
900 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
901 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
902 break;
903 default:
904// case RF_8225:
905// case RF_8258:
906 RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__);
907 break;
908 }
909 return;
910}
911
912/******************************************************************************
913 *function: This function check Rf chip to do RF config
914 * input: net_device dev
915 * output: none
916 * return: only 8256 is supported
917 * ***************************************************************************/
918void rtl8192_phy_RFConfig(struct net_device* dev)
919{
920 struct r8192_priv *priv = ieee80211_priv(dev);
921
922 switch(priv->rf_chip)
923 {
924 case RF_8256:
925 PHY_RF8256_Config(dev);
926 break;
927 // case RF_8225:
928 // case RF_8258:
929 default:
930 RT_TRACE(COMP_ERR, "error chip id\n");
931 break;
932 }
933 return;
934}
935
936/******************************************************************************
937 *function: This function update Initial gain
938 * input: net_device dev
939 * output: none
940 * return: As Windows has not implemented this, wait for complement
941 * ***************************************************************************/
942void rtl8192_phy_updateInitGain(struct net_device* dev)
943{
944 return;
945}
946
947/******************************************************************************
948 *function: This function read RF parameters from general head file, and do RF 3-wire
949 * input: net_device dev
950 * output: none
951 * return: return code show if RF configuration is successful(0:pass, 1:fail)
952 * Note: Delay may be required for RF configuration
953 * ***************************************************************************/
954u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
955{
956
957 int i;
958 //u32* pRFArray;
959 u8 ret = 0;
960
961 switch(eRFPath){
962 case RF90_PATH_A:
963 for(i = 0;i<RadioA_ArrayLength; i=i+2){
964
965 if(rtl819XRadioA_Array[i] == 0xfe){
966 mdelay(100);
967 continue;
968 }
969 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]);
970 mdelay(1);
971
972 }
973 break;
974 case RF90_PATH_B:
975 for(i = 0;i<RadioB_ArrayLength; i=i+2){
976
977 if(rtl819XRadioB_Array[i] == 0xfe){
978 mdelay(100);
979 continue;
980 }
981 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]);
982 mdelay(1);
983
984 }
985 break;
986 case RF90_PATH_C:
987 for(i = 0;i<RadioC_ArrayLength; i=i+2){
988
989 if(rtl819XRadioC_Array[i] == 0xfe){
990 mdelay(100);
991 continue;
992 }
993 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]);
994 mdelay(1);
995
996 }
997 break;
998 case RF90_PATH_D:
999 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1000
1001 if(rtl819XRadioD_Array[i] == 0xfe){
1002 mdelay(100);
1003 continue;
1004 }
1005 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]);
1006 mdelay(1);
1007
1008 }
1009 break;
1010 default:
1011 break;
1012 }
1013
1014 return ret;;
1015
1016}
1017/******************************************************************************
1018 *function: This function set Tx Power of the channel
1019 * input: struct net_device *dev
1020 * u8 channel
1021 * output: none
1022 * return: none
1023 * Note:
1024 * ***************************************************************************/
1025void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1026{
1027 struct r8192_priv *priv = ieee80211_priv(dev);
1028 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1029 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1030
1031 switch(priv->rf_chip)
1032 {
1033 case RF_8225:
1034#ifdef TO_DO_LIST
1035 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1036 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1037#endif
1038 break;
1039
1040 case RF_8256:
1041 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1042 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1043 break;
1044
1045 case RF_8258:
1046 break;
1047 default:
1048 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
1049 break;
1050 }
1051 return;
1052}
1053
1054/******************************************************************************
1055 *function: This function set RF state on or off
1056 * input: struct net_device *dev
1057 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1058 * output: none
1059 * return: none
1060 * Note:
1061 * ***************************************************************************/
1062bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
1063{
1064 bool bResult = true;
1065// u8 eRFPath;
1066 struct r8192_priv *priv = ieee80211_priv(dev);
1067
1068 if(eRFPowerState == priv->ieee80211->eRFPowerState)
1069 return false;
1070
1071 if(priv->SetRFPowerStateInProgress == true)
1072 return false;
1073
1074 priv->SetRFPowerStateInProgress = true;
1075
1076 switch(priv->rf_chip)
1077 {
1078 case RF_8256:
1079 switch( eRFPowerState )
1080 {
1081 case eRfOn:
1082#if 0
1083 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
1084 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); // 0x88c[4]
1085 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
1086 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x3); // 0xc04[3:0]
1087 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); // 0xd04[3:0]
1088 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x3); // 0x884[14:12]
1089 // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1090 // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2);
1091
1092 //SwChnl(Adapter->ChannelID);
1093#endif
1094 //RF-A, RF-B
1095 //enable RF-Chip A/B
1096 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
1097 //analog to digital on
1098 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1099 //digital to analog on
1100 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
1101 //rx antenna on
1102 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
1103 //rx antenna on
1104 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
1105 //analog to digital part2 on
1106 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
1107
1108 break;
1109
1110 case eRfSleep:
1111
1112 break;
1113
1114 case eRfOff:
1115#if 0
1116 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4]
1117 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); // 0x88c[4]
1118 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
1119 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0); // 0xc04[3:0]
1120 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0); // 0xd04[3:0]
1121 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x0); // 0x884[14:12]
1122 // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1123 // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
1124#endif
1125 //RF-A, RF-B
1126 //disable RF-Chip A/B
1127 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4]
1128 //analog to digital off, for power save
1129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1130 //digital to analog off, for power save
1131 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
1132 //rx antenna off
1133 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
1134 //rx antenna off
1135 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
1136 //analog to digital part2 off, for power save
1137 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
1138
1139 break;
1140
1141 default:
1142 bResult = false;
1143 RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1144 break;
1145 }
1146 break;
1147 default:
1148 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1149 break;
1150 }
1151#ifdef TO_DO_LIST
1152 if(bResult)
1153 {
1154 // Update current RF state variable.
1155 pHalData->eRFPowerState = eRFPowerState;
1156 switch(pHalData->RFChipID )
1157 {
1158 case RF_8256:
1159 switch(pHalData->eRFPowerState)
1160 {
1161 case eRfOff:
1162 //
1163 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1164 //
1165 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1166 {
1167 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1168 }
1169 else
1170 {
1171 // Turn off LED if RF is not ON.
1172 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1173 }
1174 break;
1175
1176 case eRfOn:
1177 // Turn on RF we are still linked, which might happen when
1178 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1179 if( pMgntInfo->bMediaConnect == TRUE )
1180 {
1181 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1182 }
1183 else
1184 {
1185 // Turn off LED if RF is not ON.
1186 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1187 }
1188 break;
1189
1190 default:
1191 // do nothing.
1192 break;
1193 }// Switch RF state
1194 break;
1195
1196 default:
1197 RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n"));
1198 break;
1199 }
1200
1201 }
1202#endif
1203 priv->SetRFPowerStateInProgress = false;
1204
1205 return bResult;
1206}
1207
1208/****************************************************************************************
1209 *function: This function set command table variable(struct SwChnlCmd).
1210 * input: SwChnlCmd* CmdTable //table to be set.
1211 * u32 CmdTableIdx //variable index in table to be set
1212 * u32 CmdTableSz //table size.
1213 * SwChnlCmdID CmdID //command ID to set.
1214 * u32 Para1
1215 * u32 Para2
1216 * u32 msDelay
1217 * output:
1218 * return: true if finished, false otherwise
1219 * Note:
1220 * ************************************************************************************/
1221u8 rtl8192_phy_SetSwChnlCmdArray(
1222 SwChnlCmd* CmdTable,
1223 u32 CmdTableIdx,
1224 u32 CmdTableSz,
1225 SwChnlCmdID CmdID,
1226 u32 Para1,
1227 u32 Para2,
1228 u32 msDelay
1229 )
1230{
1231 SwChnlCmd* pCmd;
1232
1233 if(CmdTable == NULL)
1234 {
1235 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1236 return false;
1237 }
1238 if(CmdTableIdx >= CmdTableSz)
1239 {
1240 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1241 CmdTableIdx, CmdTableSz);
1242 return false;
1243 }
1244
1245 pCmd = CmdTable + CmdTableIdx;
1246 pCmd->CmdID = CmdID;
1247 pCmd->Para1 = Para1;
1248 pCmd->Para2 = Para2;
1249 pCmd->msDelay = msDelay;
1250
1251 return true;
1252}
1253/******************************************************************************
1254 *function: This function set channel step by step
1255 * input: struct net_device *dev
1256 * u8 channel
1257 * u8* stage //3 stages
1258 * u8* step //
1259 * u32* delay //whether need to delay
1260 * output: store new stage, step and delay for next step(combine with function above)
1261 * return: true if finished, false otherwise
1262 * Note: Wait for simpler function to replace it //wb
1263 * ***************************************************************************/
1264u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
1265{
1266 struct r8192_priv *priv = ieee80211_priv(dev);
1267// PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1268 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1269 u32 PreCommonCmdCnt;
1270 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1271 u32 PostCommonCmdCnt;
1272 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1273 u32 RfDependCmdCnt;
1274 SwChnlCmd *CurrentCmd = NULL;
1275 //RF90_RADIO_PATH_E eRFPath;
1276 u8 eRFPath;
1277// u32 RfRetVal;
1278// u8 RetryCnt;
1279
1280 RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1281// RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1282#ifdef ENABLE_DOT11D
1283 if (!IsLegalChannel(priv->ieee80211, channel))
1284 {
1285 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1286 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1287 }
1288#endif
1289//FIXME:need to check whether channel is legal or not here.WB
1290
1291
1292 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1293// for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1294// {
1295// if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1296// continue;
1297 // <1> Fill up pre common command.
1298 PreCommonCmdCnt = 0;
1299 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1300 CmdID_SetTxPowerLevel, 0, 0, 0);
1301 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1302 CmdID_End, 0, 0, 0);
1303
1304 // <2> Fill up post common command.
1305 PostCommonCmdCnt = 0;
1306
1307 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1308 CmdID_End, 0, 0, 0);
1309
1310 // <3> Fill up RF dependent command.
1311 RfDependCmdCnt = 0;
1312 switch( priv->rf_chip )
1313 {
1314 case RF_8225:
1315 if (!(channel >= 1 && channel <= 14))
1316 {
1317 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1318 return true;
1319 }
1320 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1321 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1322 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1323 CmdID_End, 0, 0, 0);
1324 break;
1325
1326 case RF_8256:
1327 // TEST!! This is not the table for 8256!!
1328 if (!(channel >= 1 && channel <= 14))
1329 {
1330 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1331 return true;
1332 }
1333 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1334 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1335 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1336 CmdID_End, 0, 0, 0);
1337 break;
1338
1339 case RF_8258:
1340 break;
1341
1342 default:
1343 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1344 return true;
1345 break;
1346 }
1347
1348
1349 do{
1350 switch(*stage)
1351 {
1352 case 0:
1353 CurrentCmd=&PreCommonCmd[*step];
1354 break;
1355 case 1:
1356 CurrentCmd=&RfDependCmd[*step];
1357 break;
1358 case 2:
1359 CurrentCmd=&PostCommonCmd[*step];
1360 break;
1361 }
1362
1363 if(CurrentCmd->CmdID==CmdID_End)
1364 {
1365 if((*stage)==2)
1366 {
1367 (*delay)=CurrentCmd->msDelay;
1368 return true;
1369 }
1370 else
1371 {
1372 (*stage)++;
1373 (*step)=0;
1374 continue;
1375 }
1376 }
1377
1378 switch(CurrentCmd->CmdID)
1379 {
1380 case CmdID_SetTxPowerLevel:
1381 if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
1382 rtl8192_SetTxPowerLevel(dev,channel);
1383 break;
1384 case CmdID_WritePortUlong:
1385 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
1386 break;
1387 case CmdID_WritePortUshort:
1388 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1389 break;
1390 case CmdID_WritePortUchar:
1391 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1392 break;
1393 case CmdID_RF_WriteReg:
1394 for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++)
1395 {
1396 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
1397 }
1398 break;
1399 default:
1400 break;
1401 }
1402
1403 break;
1404 }while(true);
1405// }/*for(Number of RF paths)*/
1406
1407 (*delay)=CurrentCmd->msDelay;
1408 (*step)++;
1409 return false;
1410}
1411
1412/******************************************************************************
1413 *function: This function does acturally set channel work
1414 * input: struct net_device *dev
1415 * u8 channel
1416 * output: none
1417 * return: noin
1418 * Note: We should not call this function directly
1419 * ***************************************************************************/
1420void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1421{
1422 struct r8192_priv *priv = ieee80211_priv(dev);
1423 u32 delay = 0;
1424
1425 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1426 {
1427 // if(delay>0)
1428 // msleep(delay);//or mdelay? need further consideration
1429 if(!priv->up)
1430 break;
1431 }
1432}
1433/******************************************************************************
1434 *function: Callback routine of the work item for switch channel.
1435 * input:
1436 *
1437 * output: none
1438 * return: noin
1439 * ***************************************************************************/
1440void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1441{
1442
1443 struct r8192_priv *priv = ieee80211_priv(dev);
1444
1445 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan);
1446
1447
1448 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1449
1450 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1451}
1452
1453/******************************************************************************
1454 *function: This function scheduled actural workitem to set channel
1455 * input: net_device dev
1456 * u8 channel //channel to set
1457 * output: none
1458 * return: return code show if workitem is scheduled(1:pass, 0:fail)
1459 * Note: Delay may be required for RF configuration
1460 * ***************************************************************************/
1461u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1462{
1463 struct r8192_priv *priv = ieee80211_priv(dev);
1464 RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress);
1465 if(!priv->up)
1466 return false;
1467 if(priv->SwChnlInProgress)
1468 return false;
1469
1470// if(pHalData->SetBWModeInProgress)
1471// return;
1472if (0) //to test current channel from RF reg 0x7.
1473{
1474 u8 eRFPath;
1475 for(eRFPath = 0; eRFPath < 2; eRFPath++){
1476 printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum));
1477 udelay(10);
1478 }
1479}
1480 //--------------------------------------------
1481 switch(priv->ieee80211->mode)
1482 {
1483 case WIRELESS_MODE_A:
1484 case WIRELESS_MODE_N_5G:
1485 if (channel<=14){
1486 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1487 return false;
1488 }
1489 break;
1490 case WIRELESS_MODE_B:
1491 if (channel>14){
1492 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1493 return false;
1494 }
1495 break;
1496 case WIRELESS_MODE_G:
1497 case WIRELESS_MODE_N_24G:
1498 if (channel>14){
1499 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1500 return false;
1501 }
1502 break;
1503 }
1504 //--------------------------------------------
1505
1506 priv->SwChnlInProgress = true;
1507 if(channel == 0)
1508 channel = 1;
1509
1510 priv->chan=channel;
1511
1512 priv->SwChnlStage=0;
1513 priv->SwChnlStep=0;
1514// schedule_work(&(priv->SwChnlWorkItem));
1515// rtl8192_SwChnl_WorkItem(dev);
1516 if(priv->up) {
1517// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
1518 rtl8192_SwChnl_WorkItem(dev);
1519 }
1520
1521 priv->SwChnlInProgress = false;
1522 return true;
1523}
1524
1525
1526//
1527/******************************************************************************
1528 *function: Callback routine of the work item for set bandwidth mode.
1529 * input: struct net_device *dev
1530 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
1531 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
1532 * output: none
1533 * return: none
1534 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
1535 * test whether current work in the queue or not.//do I?
1536 * ***************************************************************************/
1537void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1538{
1539
1540 struct r8192_priv *priv = ieee80211_priv(dev);
1541 u8 regBwOpMode;
1542
1543 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
1544 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
1545
1546
1547 if(priv->rf_chip == RF_PSEUDO_11N)
1548 {
1549 priv->SetBWModeInProgress= false;
1550 return;
1551 }
1552
1553 //<1>Set MAC register
1554 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1555
1556 switch(priv->CurrentChannelBW)
1557 {
1558 case HT_CHANNEL_WIDTH_20:
1559 regBwOpMode |= BW_OPMODE_20MHZ;
1560 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
1561 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1562 break;
1563
1564 case HT_CHANNEL_WIDTH_20_40:
1565 regBwOpMode &= ~BW_OPMODE_20MHZ;
1566 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
1567 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1568 break;
1569
1570 default:
1571 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1572 break;
1573 }
1574
1575 //<2>Set PHY related register
1576 switch(priv->CurrentChannelBW)
1577 {
1578 case HT_CHANNEL_WIDTH_20:
1579 // Add by Vivi 20071119
1580 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1581 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1582 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1583
1584 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
1585#if 0
1586 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1587 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1588 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1589#endif
1590 priv->cck_present_attentuation =
1591 priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
1592
1593 if(priv->cck_present_attentuation > 22)
1594 priv->cck_present_attentuation= 22;
1595 if(priv->cck_present_attentuation< 0)
1596 priv->cck_present_attentuation = 0;
1597 RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1598
1599 if(priv->chan == 14 && !priv->bcck_in_ch14)
1600 {
1601 priv->bcck_in_ch14 = TRUE;
1602 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1603 }
1604 else if(priv->chan != 14 && priv->bcck_in_ch14)
1605 {
1606 priv->bcck_in_ch14 = FALSE;
1607 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1608 }
1609 else
1610 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1611
1612 break;
1613 case HT_CHANNEL_WIDTH_20_40:
1614 // Add by Vivi 20071119
1615 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1616 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1617 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1618 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1619 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1620#if 0
1621 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
1622 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1623 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1624 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1625#endif
1626 priv->cck_present_attentuation =
1627 priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
1628
1629 if(priv->cck_present_attentuation > 22)
1630 priv->cck_present_attentuation = 22;
1631 if(priv->cck_present_attentuation < 0)
1632 priv->cck_present_attentuation = 0;
1633
1634 RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1635 if(priv->chan == 14 && !priv->bcck_in_ch14)
1636 {
1637 priv->bcck_in_ch14 = true;
1638 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1639 }
1640 else if(priv->chan!= 14 && priv->bcck_in_ch14)
1641 {
1642 priv->bcck_in_ch14 = false;
1643 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1644 }
1645 else
1646 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1647
1648 break;
1649 default:
1650 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1651 break;
1652
1653 }
1654 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
1655
1656#if 1
1657 //<3>Set RF related register
1658 switch( priv->rf_chip )
1659 {
1660 case RF_8225:
1661#ifdef TO_DO_LIST
1662 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1663#endif
1664 break;
1665
1666 case RF_8256:
1667 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1668 break;
1669
1670 case RF_8258:
1671 // PHY_SetRF8258Bandwidth();
1672 break;
1673
1674 case RF_PSEUDO_11N:
1675 // Do Nothing
1676 break;
1677
1678 default:
1679 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1680 break;
1681 }
1682#endif
1683 priv->SetBWModeInProgress= false;
1684
1685 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) );
1686}
1687
1688/******************************************************************************
1689 *function: This function schedules bandwith switch work.
1690 * input: struct net_device *dev
1691 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
1692 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
1693 * output: none
1694 * return: none
1695 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
1696 * test whether current work in the queue or not.//do I?
1697 * ***************************************************************************/
1698void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1699{
1700 struct r8192_priv *priv = ieee80211_priv(dev);
1701
1702 if(priv->SetBWModeInProgress)
1703 return;
1704 priv->SetBWModeInProgress= true;
1705
1706 priv->CurrentChannelBW = Bandwidth;
1707
1708 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
1709 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1710 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
1711 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1712 else
1713 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1714
1715 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
1716 // schedule_work(&(priv->SetBWModeWorkItem));
1717 rtl8192_SetBWModeWorkItem(dev);
1718
1719}
1720
1721void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1722{
1723 struct r8192_priv *priv = ieee80211_priv(dev);
1724
1725 priv->InitialGainOperateType = Operation;
1726
1727 if(priv->up)
1728 {
1729 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1730 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
1731 #else
1732 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1733 schedule_task(&priv->initialgain_operate_wq);
1734 #else
1735 queue_work(priv->priv_wq,&priv->initialgain_operate_wq);
1736 #endif
1737 #endif
1738 }
1739}
1740
1741#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1742extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1743{
1744 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1745 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
1746 struct net_device *dev = priv->ieee80211->dev;
1747#else
1748extern void InitialGainOperateWorkItemCallBack(struct net_device *dev)
1749{
1750 struct r8192_priv *priv = ieee80211_priv(dev);
1751#endif
1752#define SCAN_RX_INITIAL_GAIN 0x17
1753#define POWER_DETECTION_TH 0x08
1754 u32 BitMask;
1755 u8 initial_gain;
1756 u8 Operation;
1757
1758 Operation = priv->InitialGainOperateType;
1759
1760 switch(Operation)
1761 {
1762 case IG_Backup:
1763 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1764 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
1765 BitMask = bMaskByte0;
1766 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1767 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1768 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1769 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1770 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1771 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1772 BitMask = bMaskByte2;
1773 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1774
1775 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1776 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1777 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1778 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1779 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1780
1781 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1782 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1783 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1784 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1785 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1786 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1787 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1788 break;
1789 case IG_Restore:
1790 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1791 BitMask = 0x7f; //Bit0~ Bit6
1792 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1793 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1794
1795 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1796 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1797 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1798 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1799 BitMask = bMaskByte2;
1800 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1801
1802 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1803 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1804 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1805 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1806 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1807
1808#ifdef RTL8190P
1809 SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1810#endif
1811#ifdef RTL8192E
1812 SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1813#endif
1814//#ifdef RTL8192U
1815 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
1816//#endif
1817
1818 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1819 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
1820 break;
1821 default:
1822 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1823 break;
1824 }
1825}
1826
diff --git a/drivers/staging/rtl8192su/r819xU_phy.h b/drivers/staging/rtl8192su/r819xU_phy.h
new file mode 100644
index 00000000000..c165ac1265d
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_phy.h
@@ -0,0 +1,94 @@
1#ifndef _R819XU_PHY_H
2#define _R819XU_PHY_H
3
4/* Channel switch:The size of command tables for switch channel*/
5#define MAX_PRECMD_CNT 16
6#define MAX_RFDEPENDCMD_CNT 16
7#define MAX_POSTCMD_CNT 16
8
9typedef enum _SwChnlCmdID{
10 CmdID_End,
11 CmdID_SetTxPowerLevel,
12 CmdID_BBRegWrite10,
13 CmdID_WritePortUlong,
14 CmdID_WritePortUshort,
15 CmdID_WritePortUchar,
16 CmdID_RF_WriteReg,
17}SwChnlCmdID;
18
19/*--------------------------------Define structure--------------------------------*/
20/* 1. Switch channel related */
21typedef struct _SwChnlCmd{
22 SwChnlCmdID CmdID;
23 u32 Para1;
24 u32 Para2;
25 u32 msDelay;
26}__attribute__ ((packed)) SwChnlCmd;
27
28extern u32 rtl819XMACPHY_Array_PG[];
29extern u32 rtl819XPHY_REG_1T2RArray[];
30extern u32 rtl819XAGCTAB_Array[];
31extern u32 rtl819XRadioA_Array[];
32extern u32 rtl819XRadioB_Array[];
33extern u32 rtl819XRadioC_Array[];
34extern u32 rtl819XRadioD_Array[];
35
36typedef enum _HW90_BLOCK{
37 HW90_BLOCK_MAC = 0,
38 HW90_BLOCK_PHY0 = 1,
39 HW90_BLOCK_PHY1 = 2,
40 HW90_BLOCK_RF = 3,
41 HW90_BLOCK_MAXIMUM = 4, // Never use this
42}HW90_BLOCK_E, *PHW90_BLOCK_E;
43
44typedef enum _RF90_RADIO_PATH{
45 RF90_PATH_A = 0, //Radio Path A
46 RF90_PATH_B = 1, //Radio Path B
47 RF90_PATH_C = 2, //Radio Path C
48 RF90_PATH_D = 3, //Radio Path D
49 RF90_PATH_MAX //Max RF number 92 support
50}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
51
52#define bMaskByte0 0xff
53#define bMaskByte1 0xff00
54#define bMaskByte2 0xff0000
55#define bMaskByte3 0xff000000
56#define bMaskHWord 0xffff0000
57#define bMaskLWord 0x0000ffff
58#define bMaskDWord 0xffffffff
59
60//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
61extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
62extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
63extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
64//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
65//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
66extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
67extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
68extern void rtl8192_phy_configmac(struct net_device* dev);
69extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
70//extern void rtl8192_InitBBRFRegDef(struct net_device* dev);
71extern u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
72//extern void rtl8192_BB_Config_ParaFile(struct net_device* dev);
73extern void rtl8192_BBConfig(struct net_device* dev);
74extern void rtl8192_phy_getTxPower(struct net_device* dev);
75extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
76extern void rtl8192_phy_RFConfig(struct net_device* dev);
77extern void rtl8192_phy_updateInitGain(struct net_device* dev);
78extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath);
79
80extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
81extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
82extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
83void rtl8192_SetBWModeWorkItem(struct net_device *dev);
84extern bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState);
85//added by amy
86extern void InitialGain819xUsb(struct net_device *dev, u8 Operation);
87
88#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
89extern void InitialGainOperateWorkItemCallBack(struct work_struct *work);
90#else
91extern void InitialGainOperateWorkItemCallBack(struct net_device *dev);
92#endif
93
94#endif
diff --git a/drivers/staging/rtl8192su/r819xU_phyreg.h b/drivers/staging/rtl8192su/r819xU_phyreg.h
new file mode 100644
index 00000000000..b62f1a6fb1e
--- /dev/null
+++ b/drivers/staging/rtl8192su/r819xU_phyreg.h
@@ -0,0 +1,871 @@
1#ifndef _R819XU_PHYREG_H
2#define _R819XU_PHYREG_H
3
4
5#define RF_DATA 0x1d4 // FW will write RF data in the register.
6
7//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
8//page 1
9#define rPMAC_Reset 0x100
10#define rPMAC_TxStart 0x104
11#define rPMAC_TxLegacySIG 0x108
12#define rPMAC_TxHTSIG1 0x10c
13#define rPMAC_TxHTSIG2 0x110
14#define rPMAC_PHYDebug 0x114
15#define rPMAC_TxPacketNum 0x118
16#define rPMAC_TxIdle 0x11c
17#define rPMAC_TxMACHeader0 0x120
18#define rPMAC_TxMACHeader1 0x124
19#define rPMAC_TxMACHeader2 0x128
20#define rPMAC_TxMACHeader3 0x12c
21#define rPMAC_TxMACHeader4 0x130
22#define rPMAC_TxMACHeader5 0x134
23#define rPMAC_TxDataType 0x138
24#define rPMAC_TxRandomSeed 0x13c
25#define rPMAC_CCKPLCPPreamble 0x140
26#define rPMAC_CCKPLCPHeader 0x144
27#define rPMAC_CCKCRC16 0x148
28#define rPMAC_OFDMRxCRC32OK 0x170
29#define rPMAC_OFDMRxCRC32Er 0x174
30#define rPMAC_OFDMRxParityEr 0x178
31#define rPMAC_OFDMRxCRC8Er 0x17c
32#define rPMAC_CCKCRxRC16Er 0x180
33#define rPMAC_CCKCRxRC32Er 0x184
34#define rPMAC_CCKCRxRC32OK 0x188
35#define rPMAC_TxStatus 0x18c
36
37//page8
38#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC
39#define rFPGA0_TxInfo 0x804
40#define rFPGA0_PSDFunction 0x808
41#define rFPGA0_TxGainStage 0x80c
42#define rFPGA0_RFTiming1 0x810
43#define rFPGA0_RFTiming2 0x814
44//#define rFPGA0_XC_RFTiming 0x818
45//#define rFPGA0_XD_RFTiming 0x81c
46#define rFPGA0_XA_HSSIParameter1 0x820
47#define rFPGA0_XA_HSSIParameter2 0x824
48#define rFPGA0_XB_HSSIParameter1 0x828
49#define rFPGA0_XB_HSSIParameter2 0x82c
50#define rFPGA0_XC_HSSIParameter1 0x830
51#define rFPGA0_XC_HSSIParameter2 0x834
52#define rFPGA0_XD_HSSIParameter1 0x838
53#define rFPGA0_XD_HSSIParameter2 0x83c
54#define rFPGA0_XA_LSSIParameter 0x840
55#define rFPGA0_XB_LSSIParameter 0x844
56#define rFPGA0_XC_LSSIParameter 0x848
57#define rFPGA0_XD_LSSIParameter 0x84c
58#define rFPGA0_RFWakeUpParameter 0x850
59#define rFPGA0_RFSleepUpParameter 0x854
60#define rFPGA0_XAB_SwitchControl 0x858
61#define rFPGA0_XCD_SwitchControl 0x85c
62#define rFPGA0_XA_RFInterfaceOE 0x860
63#define rFPGA0_XB_RFInterfaceOE 0x864
64#define rFPGA0_XC_RFInterfaceOE 0x868
65#define rFPGA0_XD_RFInterfaceOE 0x86c
66#define rFPGA0_XAB_RFInterfaceSW 0x870
67#define rFPGA0_XCD_RFInterfaceSW 0x874
68#define rFPGA0_XAB_RFParameter 0x878
69#define rFPGA0_XCD_RFParameter 0x87c
70#define rFPGA0_AnalogParameter1 0x880
71#define rFPGA0_AnalogParameter2 0x884
72#define rFPGA0_AnalogParameter3 0x888
73#define rFPGA0_AnalogParameter4 0x88c
74#define rFPGA0_XA_LSSIReadBack 0x8a0
75#define rFPGA0_XB_LSSIReadBack 0x8a4
76#define rFPGA0_XC_LSSIReadBack 0x8a8
77#define rFPGA0_XD_LSSIReadBack 0x8ac
78#define rFPGA0_PSDReport 0x8b4
79#define rFPGA0_XAB_RFInterfaceRB 0x8e0
80#define rFPGA0_XCD_RFInterfaceRB 0x8e4
81
82//page 9
83#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC
84#define rFPGA1_TxBlock 0x904
85#define rFPGA1_DebugSelect 0x908
86#define rFPGA1_TxInfo 0x90c
87
88//page a
89#define rCCK0_System 0xa00
90#define rCCK0_AFESetting 0xa04
91#define rCCK0_CCA 0xa08
92#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level
93#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
94#define rCCK0_RxHP 0xa14
95#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
96#define rCCK0_DSPParameter2 0xa1c //SQ threshold
97#define rCCK0_TxFilter1 0xa20
98#define rCCK0_TxFilter2 0xa24
99#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
100#define rCCK0_FalseAlarmReport 0xa2c //0xa2d
101#define rCCK0_TRSSIReport 0xa50
102#define rCCK0_RxReport 0xa54 //0xa57
103#define rCCK0_FACounterLower 0xa5c //0xa5b
104#define rCCK0_FACounterUpper 0xa58 //0xa5c
105
106//page c
107#define rOFDM0_LSTF 0xc00
108#define rOFDM0_TRxPathEnable 0xc04
109#define rOFDM0_TRMuxPar 0xc08
110#define rOFDM0_TRSWIsolation 0xc0c
111#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
112#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
113#define rOFDM0_XBRxAFE 0xc18
114#define rOFDM0_XBRxIQImbalance 0xc1c
115#define rOFDM0_XCRxAFE 0xc20
116#define rOFDM0_XCRxIQImbalance 0xc24
117#define rOFDM0_XDRxAFE 0xc28
118#define rOFDM0_XDRxIQImbalance 0xc2c
119#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD
120#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
121#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
122#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
123#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
124#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
125#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
126#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
127#define rOFDM0_XAAGCCore1 0xc50
128#define rOFDM0_XAAGCCore2 0xc54
129#define rOFDM0_XBAGCCore1 0xc58
130#define rOFDM0_XBAGCCore2 0xc5c
131#define rOFDM0_XCAGCCore1 0xc60
132#define rOFDM0_XCAGCCore2 0xc64
133#define rOFDM0_XDAGCCore1 0xc68
134#define rOFDM0_XDAGCCore2 0xc6c
135#define rOFDM0_AGCParameter1 0xc70
136#define rOFDM0_AGCParameter2 0xc74
137#define rOFDM0_AGCRSSITable 0xc78
138#define rOFDM0_HTSTFAGC 0xc7c
139#define rOFDM0_XATxIQImbalance 0xc80
140#define rOFDM0_XATxAFE 0xc84
141#define rOFDM0_XBTxIQImbalance 0xc88
142#define rOFDM0_XBTxAFE 0xc8c
143#define rOFDM0_XCTxIQImbalance 0xc90
144#define rOFDM0_XCTxAFE 0xc94
145#define rOFDM0_XDTxIQImbalance 0xc98
146#define rOFDM0_XDTxAFE 0xc9c
147#define rOFDM0_RxHPParameter 0xce0
148#define rOFDM0_TxPseudoNoiseWgt 0xce4
149#define rOFDM0_FrameSync 0xcf0
150#define rOFDM0_DFSReport 0xcf4
151#define rOFDM0_TxCoeff1 0xca4
152#define rOFDM0_TxCoeff2 0xca8
153#define rOFDM0_TxCoeff3 0xcac
154#define rOFDM0_TxCoeff4 0xcb0
155#define rOFDM0_TxCoeff5 0xcb4
156#define rOFDM0_TxCoeff6 0xcb8
157
158
159//page d
160#define rOFDM1_LSTF 0xd00
161#define rOFDM1_TRxPathEnable 0xd04
162#define rOFDM1_CFO 0xd08
163#define rOFDM1_CSI1 0xd10
164#define rOFDM1_SBD 0xd14
165#define rOFDM1_CSI2 0xd18
166#define rOFDM1_CFOTracking 0xd2c
167#define rOFDM1_TRxMesaure1 0xd34
168#define rOFDM1_IntfDet 0xd3c
169#define rOFDM1_PseudoNoiseStateAB 0xd50
170#define rOFDM1_PseudoNoiseStateCD 0xd54
171#define rOFDM1_RxPseudoNoiseWgt 0xd58
172#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
173#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
174#define rOFDM_PHYCounter3 0xda8 //MCS not support
175#define rOFDM_ShortCFOAB 0xdac
176#define rOFDM_ShortCFOCD 0xdb0
177#define rOFDM_LongCFOAB 0xdb4
178#define rOFDM_LongCFOCD 0xdb8
179#define rOFDM_TailCFOAB 0xdbc
180#define rOFDM_TailCFOCD 0xdc0
181#define rOFDM_PWMeasure1 0xdc4
182#define rOFDM_PWMeasure2 0xdc8
183#define rOFDM_BWReport 0xdcc
184#define rOFDM_AGCReport 0xdd0
185#define rOFDM_RxSNR 0xdd4
186#define rOFDM_RxEVMCSI 0xdd8
187#define rOFDM_SIGReport 0xddc
188
189//page e
190#define rTxAGC_Rate18_06 0xe00
191#define rTxAGC_Rate54_24 0xe04
192#define rTxAGC_CCK_Mcs32 0xe08
193#define rTxAGC_Mcs03_Mcs00 0xe10
194#define rTxAGC_Mcs07_Mcs04 0xe14
195#define rTxAGC_Mcs11_Mcs08 0xe18
196#define rTxAGC_Mcs15_Mcs12 0xe1c
197
198
199//RF
200//Zebra1
201#define rZebra1_HSSIEnable 0x0
202#define rZebra1_TRxEnable1 0x1
203#define rZebra1_TRxEnable2 0x2
204#define rZebra1_AGC 0x4
205#define rZebra1_ChargePump 0x5
206#define rZebra1_Channel 0x7
207#define rZebra1_TxGain 0x8
208#define rZebra1_TxLPF 0x9
209#define rZebra1_RxLPF 0xb
210#define rZebra1_RxHPFCorner 0xc
211
212//Zebra4
213#define rGlobalCtrl 0
214#define rRTL8256_TxLPF 19
215#define rRTL8256_RxLPF 11
216
217//RTL8258
218#define rRTL8258_TxLPF 0x11
219#define rRTL8258_RxLPF 0x13
220#define rRTL8258_RSSILPF 0xa
221
222//Bit Mask
223//page-1
224#define bBBResetB 0x100
225#define bGlobalResetB 0x200
226#define bOFDMTxStart 0x4
227#define bCCKTxStart 0x8
228#define bCRC32Debug 0x100
229#define bPMACLoopback 0x10
230#define bTxLSIG 0xffffff
231#define bOFDMTxRate 0xf
232#define bOFDMTxReserved 0x10
233#define bOFDMTxLength 0x1ffe0
234#define bOFDMTxParity 0x20000
235#define bTxHTSIG1 0xffffff
236#define bTxHTMCSRate 0x7f
237#define bTxHTBW 0x80
238#define bTxHTLength 0xffff00
239#define bTxHTSIG2 0xffffff
240#define bTxHTSmoothing 0x1
241#define bTxHTSounding 0x2
242#define bTxHTReserved 0x4
243#define bTxHTAggreation 0x8
244#define bTxHTSTBC 0x30
245#define bTxHTAdvanceCoding 0x40
246#define bTxHTShortGI 0x80
247#define bTxHTNumberHT_LTF 0x300
248#define bTxHTCRC8 0x3fc00
249#define bCounterReset 0x10000
250#define bNumOfOFDMTx 0xffff
251#define bNumOfCCKTx 0xffff0000
252#define bTxIdleInterval 0xffff
253#define bOFDMService 0xffff0000
254#define bTxMACHeader 0xffffffff
255#define bTxDataInit 0xff
256#define bTxHTMode 0x100
257#define bTxDataType 0x30000
258#define bTxRandomSeed 0xffffffff
259#define bCCKTxPreamble 0x1
260#define bCCKTxSFD 0xffff0000
261#define bCCKTxSIG 0xff
262#define bCCKTxService 0xff00
263#define bCCKLengthExt 0x8000
264#define bCCKTxLength 0xffff0000
265#define bCCKTxCRC16 0xffff
266#define bCCKTxStatus 0x1
267#define bOFDMTxStatus 0x2
268
269//page-8
270#define bRFMOD 0x1
271#define bJapanMode 0x2
272#define bCCKTxSC 0x30
273#define bCCKEn 0x1000000
274#define bOFDMEn 0x2000000
275#define bOFDMRxADCPhase 0x10000
276#define bOFDMTxDACPhase 0x40000
277#define bXATxAGC 0x3f
278#define bXBTxAGC 0xf00
279#define bXCTxAGC 0xf000
280#define bXDTxAGC 0xf0000
281#define bPAStart 0xf0000000
282#define bTRStart 0x00f00000
283#define bRFStart 0x0000f000
284#define bBBStart 0x000000f0
285#define bBBCCKStart 0x0000000f
286#define bPAEnd 0xf //Reg0x814
287#define bTREnd 0x0f000000
288#define bRFEnd 0x000f0000
289#define bCCAMask 0x000000f0 //T2R
290#define bR2RCCAMask 0x00000f00
291#define bHSSI_R2TDelay 0xf8000000
292#define bHSSI_T2RDelay 0xf80000
293#define bContTxHSSI 0x400 //chane gain at continue Tx
294#define bIGFromCCK 0x200
295#define bAGCAddress 0x3f
296#define bRxHPTx 0x7000
297#define bRxHPT2R 0x38000
298#define bRxHPCCKIni 0xc0000
299#define bAGCTxCode 0xc00000
300#define bAGCRxCode 0x300000
301#define b3WireDataLength 0x800
302#define b3WireAddressLength 0x400
303#define b3WireRFPowerDown 0x1
304//#define bHWSISelect 0x8
305#define b5GPAPEPolarity 0x40000000
306#define b2GPAPEPolarity 0x80000000
307#define bRFSW_TxDefaultAnt 0x3
308#define bRFSW_TxOptionAnt 0x30
309#define bRFSW_RxDefaultAnt 0x300
310#define bRFSW_RxOptionAnt 0x3000
311#define bRFSI_3WireData 0x1
312#define bRFSI_3WireClock 0x2
313#define bRFSI_3WireLoad 0x4
314#define bRFSI_3WireRW 0x8
315#define bRFSI_3Wire 0xf //3-wire total control
316#define bRFSI_RFENV 0x10
317#define bRFSI_TRSW 0x20
318#define bRFSI_TRSWB 0x40
319#define bRFSI_ANTSW 0x100
320#define bRFSI_ANTSWB 0x200
321#define bRFSI_PAPE 0x400
322#define bRFSI_PAPE5G 0x800
323#define bBandSelect 0x1
324#define bHTSIG2_GI 0x80
325#define bHTSIG2_Smoothing 0x01
326#define bHTSIG2_Sounding 0x02
327#define bHTSIG2_Aggreaton 0x08
328#define bHTSIG2_STBC 0x30
329#define bHTSIG2_AdvCoding 0x40
330#define bHTSIG2_NumOfHTLTF 0x300
331#define bHTSIG2_CRC8 0x3fc
332#define bHTSIG1_MCS 0x7f
333#define bHTSIG1_BandWidth 0x80
334#define bHTSIG1_HTLength 0xffff
335#define bLSIG_Rate 0xf
336#define bLSIG_Reserved 0x10
337#define bLSIG_Length 0x1fffe
338#define bLSIG_Parity 0x20
339#define bCCKRxPhase 0x4
340#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address
341#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
342#define bLSSIReadBackData 0xfff
343#define bLSSIReadOKFlag 0x1000
344#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
345
346#define bRegulator0Standby 0x1
347#define bRegulatorPLLStandby 0x2
348#define bRegulator1Standby 0x4
349#define bPLLPowerUp 0x8
350#define bDPLLPowerUp 0x10
351#define bDA10PowerUp 0x20
352#define bAD7PowerUp 0x200
353#define bDA6PowerUp 0x2000
354#define bXtalPowerUp 0x4000
355#define b40MDClkPowerUP 0x8000
356#define bDA6DebugMode 0x20000
357#define bDA6Swing 0x380000
358#define bADClkPhase 0x4000000
359#define b80MClkDelay 0x18000000
360#define bAFEWatchDogEnable 0x20000000
361#define bXtalCap 0x0f000000
362#define bIntDifClkEnable 0x400
363#define bExtSigClkEnable 0x800
364#define bBandgapMbiasPowerUp 0x10000
365#define bAD11SHGain 0xc0000
366#define bAD11InputRange 0x700000
367#define bAD11OPCurrent 0x3800000
368#define bIPathLoopback 0x4000000
369#define bQPathLoopback 0x8000000
370#define bAFELoopback 0x10000000
371#define bDA10Swing 0x7e0
372#define bDA10Reverse 0x800
373#define bDAClkSource 0x1000
374#define bAD7InputRange 0x6000
375#define bAD7Gain 0x38000
376#define bAD7OutputCMMode 0x40000
377#define bAD7InputCMMode 0x380000
378#define bAD7Current 0xc00000
379#define bRegulatorAdjust 0x7000000
380#define bAD11PowerUpAtTx 0x1
381#define bDA10PSAtTx 0x10
382#define bAD11PowerUpAtRx 0x100
383#define bDA10PSAtRx 0x1000
384
385#define bCCKRxAGCFormat 0x200
386
387#define bPSDFFTSamplepPoint 0xc000
388#define bPSDAverageNum 0x3000
389#define bIQPathControl 0xc00
390#define bPSDFreq 0x3ff
391#define bPSDAntennaPath 0x30
392#define bPSDIQSwitch 0x40
393#define bPSDRxTrigger 0x400000
394#define bPSDTxTrigger 0x80000000
395#define bPSDSineToneScale 0x7f000000
396#define bPSDReport 0xffff
397
398//page-9
399#define bOFDMTxSC 0x30000000
400#define bCCKTxOn 0x1
401#define bOFDMTxOn 0x2
402#define bDebugPage 0xfff //reset debug page and also HWord, LWord
403#define bDebugItem 0xff //reset debug page and LWord
404#define bAntL 0x10
405#define bAntNonHT 0x100
406#define bAntHT1 0x1000
407#define bAntHT2 0x10000
408#define bAntHT1S1 0x100000
409#define bAntNonHTS1 0x1000000
410
411//page-a
412#define bCCKBBMode 0x3
413#define bCCKTxPowerSaving 0x80
414#define bCCKRxPowerSaving 0x40
415#define bCCKSideBand 0x10
416#define bCCKScramble 0x8
417#define bCCKAntDiversity 0x8000
418#define bCCKCarrierRecovery 0x4000
419#define bCCKTxRate 0x3000
420#define bCCKDCCancel 0x0800
421#define bCCKISICancel 0x0400
422#define bCCKMatchFilter 0x0200
423#define bCCKEqualizer 0x0100
424#define bCCKPreambleDetect 0x800000
425#define bCCKFastFalseCCA 0x400000
426#define bCCKChEstStart 0x300000
427#define bCCKCCACount 0x080000
428#define bCCKcs_lim 0x070000
429#define bCCKBistMode 0x80000000
430#define bCCKCCAMask 0x40000000
431#define bCCKTxDACPhase 0x4
432#define bCCKRxADCPhase 0x20000000 //r_rx_clk
433#define bCCKr_cp_mode0 0x0100
434#define bCCKTxDCOffset 0xf0
435#define bCCKRxDCOffset 0xf
436#define bCCKCCAMode 0xc000
437#define bCCKFalseCS_lim 0x3f00
438#define bCCKCS_ratio 0xc00000
439#define bCCKCorgBit_sel 0x300000
440#define bCCKPD_lim 0x0f0000
441#define bCCKNewCCA 0x80000000
442#define bCCKRxHPofIG 0x8000
443#define bCCKRxIG 0x7f00
444#define bCCKLNAPolarity 0x800000
445#define bCCKRx1stGain 0x7f0000
446#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
447#define bCCKRxAGCSatLevel 0x1f000000
448#define bCCKRxAGCSatCount 0xe0
449#define bCCKRxRFSettle 0x1f //AGCsamp_dly
450#define bCCKFixedRxAGC 0x8000
451//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
452#define bCCKAntennaPolarity 0x2000
453#define bCCKTxFilterType 0x0c00
454#define bCCKRxAGCReportType 0x0300
455#define bCCKRxDAGCEn 0x80000000
456#define bCCKRxDAGCPeriod 0x20000000
457#define bCCKRxDAGCSatLevel 0x1f000000
458#define bCCKTimingRecovery 0x800000
459#define bCCKTxC0 0x3f0000
460#define bCCKTxC1 0x3f000000
461#define bCCKTxC2 0x3f
462#define bCCKTxC3 0x3f00
463#define bCCKTxC4 0x3f0000
464#define bCCKTxC5 0x3f000000
465#define bCCKTxC6 0x3f
466#define bCCKTxC7 0x3f00
467#define bCCKDebugPort 0xff0000
468#define bCCKDACDebug 0x0f000000
469#define bCCKFalseAlarmEnable 0x8000
470#define bCCKFalseAlarmRead 0x4000
471#define bCCKTRSSI 0x7f
472#define bCCKRxAGCReport 0xfe
473#define bCCKRxReport_AntSel 0x80000000
474#define bCCKRxReport_MFOff 0x40000000
475#define bCCKRxRxReport_SQLoss 0x20000000
476#define bCCKRxReport_Pktloss 0x10000000
477#define bCCKRxReport_Lockedbit 0x08000000
478#define bCCKRxReport_RateError 0x04000000
479#define bCCKRxReport_RxRate 0x03000000
480#define bCCKRxFACounterLower 0xff
481#define bCCKRxFACounterUpper 0xff000000
482#define bCCKRxHPAGCStart 0xe000
483#define bCCKRxHPAGCFinal 0x1c00
484
485#define bCCKRxFalseAlarmEnable 0x8000
486#define bCCKFACounterFreeze 0x4000
487
488#define bCCKTxPathSel 0x10000000
489#define bCCKDefaultRxPath 0xc000000
490#define bCCKOptionRxPath 0x3000000
491
492//page c
493#define bNumOfSTF 0x3
494#define bShift_L 0xc0
495#define bGI_TH 0xc
496#define bRxPathA 0x1
497#define bRxPathB 0x2
498#define bRxPathC 0x4
499#define bRxPathD 0x8
500#define bTxPathA 0x1
501#define bTxPathB 0x2
502#define bTxPathC 0x4
503#define bTxPathD 0x8
504#define bTRSSIFreq 0x200
505#define bADCBackoff 0x3000
506#define bDFIRBackoff 0xc000
507#define bTRSSILatchPhase 0x10000
508#define bRxIDCOffset 0xff
509#define bRxQDCOffset 0xff00
510#define bRxDFIRMode 0x1800000
511#define bRxDCNFType 0xe000000
512#define bRXIQImb_A 0x3ff
513#define bRXIQImb_B 0xfc00
514#define bRXIQImb_C 0x3f0000
515#define bRXIQImb_D 0xffc00000
516#define bDC_dc_Notch 0x60000
517#define bRxNBINotch 0x1f000000
518#define bPD_TH 0xf
519#define bPD_TH_Opt2 0xc000
520#define bPWED_TH 0x700
521#define bIfMF_Win_L 0x800
522#define bPD_Option 0x1000
523#define bMF_Win_L 0xe000
524#define bBW_Search_L 0x30000
525#define bwin_enh_L 0xc0000
526#define bBW_TH 0x700000
527#define bED_TH2 0x3800000
528#define bBW_option 0x4000000
529#define bRatio_TH 0x18000000
530#define bWindow_L 0xe0000000
531#define bSBD_Option 0x1
532#define bFrame_TH 0x1c
533#define bFS_Option 0x60
534#define bDC_Slope_check 0x80
535#define bFGuard_Counter_DC_L 0xe00
536#define bFrame_Weight_Short 0x7000
537#define bSub_Tune 0xe00000
538#define bFrame_DC_Length 0xe000000
539#define bSBD_start_offset 0x30000000
540#define bFrame_TH_2 0x7
541#define bFrame_GI2_TH 0x38
542#define bGI2_Sync_en 0x40
543#define bSarch_Short_Early 0x300
544#define bSarch_Short_Late 0xc00
545#define bSarch_GI2_Late 0x70000
546#define bCFOAntSum 0x1
547#define bCFOAcc 0x2
548#define bCFOStartOffset 0xc
549#define bCFOLookBack 0x70
550#define bCFOSumWeight 0x80
551#define bDAGCEnable 0x10000
552#define bTXIQImb_A 0x3ff
553#define bTXIQImb_B 0xfc00
554#define bTXIQImb_C 0x3f0000
555#define bTXIQImb_D 0xffc00000
556#define bTxIDCOffset 0xff
557#define bTxQDCOffset 0xff00
558#define bTxDFIRMode 0x10000
559#define bTxPesudoNoiseOn 0x4000000
560#define bTxPesudoNoise_A 0xff
561#define bTxPesudoNoise_B 0xff00
562#define bTxPesudoNoise_C 0xff0000
563#define bTxPesudoNoise_D 0xff000000
564#define bCCADropOption 0x20000
565#define bCCADropThres 0xfff00000
566#define bEDCCA_H 0xf
567#define bEDCCA_L 0xf0
568#define bLambda_ED 0x300
569#define bRxInitialGain 0x7f
570#define bRxAntDivEn 0x80
571#define bRxAGCAddressForLNA 0x7f00
572#define bRxHighPowerFlow 0x8000
573#define bRxAGCFreezeThres 0xc0000
574#define bRxFreezeStep_AGC1 0x300000
575#define bRxFreezeStep_AGC2 0xc00000
576#define bRxFreezeStep_AGC3 0x3000000
577#define bRxFreezeStep_AGC0 0xc000000
578#define bRxRssi_Cmp_En 0x10000000
579#define bRxQuickAGCEn 0x20000000
580#define bRxAGCFreezeThresMode 0x40000000
581#define bRxOverFlowCheckType 0x80000000
582#define bRxAGCShift 0x7f
583#define bTRSW_Tri_Only 0x80
584#define bPowerThres 0x300
585#define bRxAGCEn 0x1
586#define bRxAGCTogetherEn 0x2
587#define bRxAGCMin 0x4
588#define bRxHP_Ini 0x7
589#define bRxHP_TRLNA 0x70
590#define bRxHP_RSSI 0x700
591#define bRxHP_BBP1 0x7000
592#define bRxHP_BBP2 0x70000
593#define bRxHP_BBP3 0x700000
594#define bRSSI_H 0x7f0000 //the threshold for high power
595#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
596#define bRxSettle_TRSW 0x7
597#define bRxSettle_LNA 0x38
598#define bRxSettle_RSSI 0x1c0
599#define bRxSettle_BBP 0xe00
600#define bRxSettle_RxHP 0x7000
601#define bRxSettle_AntSW_RSSI 0x38000
602#define bRxSettle_AntSW 0xc0000
603#define bRxProcessTime_DAGC 0x300000
604#define bRxSettle_HSSI 0x400000
605#define bRxProcessTime_BBPPW 0x800000
606#define bRxAntennaPowerShift 0x3000000
607#define bRSSITableSelect 0xc000000
608#define bRxHP_Final 0x7000000
609#define bRxHTSettle_BBP 0x7
610#define bRxHTSettle_HSSI 0x8
611#define bRxHTSettle_RxHP 0x70
612#define bRxHTSettle_BBPPW 0x80
613#define bRxHTSettle_Idle 0x300
614#define bRxHTSettle_Reserved 0x1c00
615#define bRxHTRxHPEn 0x8000
616#define bRxHTAGCFreezeThres 0x30000
617#define bRxHTAGCTogetherEn 0x40000
618#define bRxHTAGCMin 0x80000
619#define bRxHTAGCEn 0x100000
620#define bRxHTDAGCEn 0x200000
621#define bRxHTRxHP_BBP 0x1c00000
622#define bRxHTRxHP_Final 0xe0000000
623#define bRxPWRatioTH 0x3
624#define bRxPWRatioEn 0x4
625#define bRxMFHold 0x3800
626#define bRxPD_Delay_TH1 0x38
627#define bRxPD_Delay_TH2 0x1c0
628#define bRxPD_DC_COUNT_MAX 0x600
629//#define bRxMF_Hold 0x3800
630#define bRxPD_Delay_TH 0x8000
631#define bRxProcess_Delay 0xf0000
632#define bRxSearchrange_GI2_Early 0x700000
633#define bRxFrame_Guard_Counter_L 0x3800000
634#define bRxSGI_Guard_L 0xc000000
635#define bRxSGI_Search_L 0x30000000
636#define bRxSGI_TH 0xc0000000
637#define bDFSCnt0 0xff
638#define bDFSCnt1 0xff00
639#define bDFSFlag 0xf0000
640
641#define bMFWeightSum 0x300000
642#define bMinIdxTH 0x7f000000
643
644#define bDAFormat 0x40000
645
646#define bTxChEmuEnable 0x01000000
647
648#define bTRSWIsolation_A 0x7f
649#define bTRSWIsolation_B 0x7f00
650#define bTRSWIsolation_C 0x7f0000
651#define bTRSWIsolation_D 0x7f000000
652
653#define bExtLNAGain 0x7c00
654
655//page d
656#define bSTBCEn 0x4
657#define bAntennaMapping 0x10
658#define bNss 0x20
659#define bCFOAntSumD 0x200
660#define bPHYCounterReset 0x8000000
661#define bCFOReportGet 0x4000000
662#define bOFDMContinueTx 0x10000000
663#define bOFDMSingleCarrier 0x20000000
664#define bOFDMSingleTone 0x40000000
665//#define bRxPath1 0x01
666//#define bRxPath2 0x02
667//#define bRxPath3 0x04
668//#define bRxPath4 0x08
669//#define bTxPath1 0x10
670//#define bTxPath2 0x20
671#define bHTDetect 0x100
672#define bCFOEn 0x10000
673#define bCFOValue 0xfff00000
674#define bSigTone_Re 0x3f
675#define bSigTone_Im 0x7f00
676#define bCounter_CCA 0xffff
677#define bCounter_ParityFail 0xffff0000
678#define bCounter_RateIllegal 0xffff
679#define bCounter_CRC8Fail 0xffff0000
680#define bCounter_MCSNoSupport 0xffff
681#define bCounter_FastSync 0xffff
682#define bShortCFO 0xfff
683#define bShortCFOTLength 12 //total
684#define bShortCFOFLength 11 //fraction
685#define bLongCFO 0x7ff
686#define bLongCFOTLength 11
687#define bLongCFOFLength 11
688#define bTailCFO 0x1fff
689#define bTailCFOTLength 13
690#define bTailCFOFLength 12
691
692#define bmax_en_pwdB 0xffff
693#define bCC_power_dB 0xffff0000
694#define bnoise_pwdB 0xffff
695#define bPowerMeasTLength 10
696#define bPowerMeasFLength 3
697#define bRx_HT_BW 0x1
698#define bRxSC 0x6
699#define bRx_HT 0x8
700
701#define bNB_intf_det_on 0x1
702#define bIntf_win_len_cfg 0x30
703#define bNB_Intf_TH_cfg 0x1c0
704
705#define bRFGain 0x3f
706#define bTableSel 0x40
707#define bTRSW 0x80
708
709#define bRxSNR_A 0xff
710#define bRxSNR_B 0xff00
711#define bRxSNR_C 0xff0000
712#define bRxSNR_D 0xff000000
713#define bSNREVMTLength 8
714#define bSNREVMFLength 1
715
716#define bCSI1st 0xff
717#define bCSI2nd 0xff00
718#define bRxEVM1st 0xff0000
719#define bRxEVM2nd 0xff000000
720
721#define bSIGEVM 0xff
722#define bPWDB 0xff00
723#define bSGIEN 0x10000
724
725#define bSFactorQAM1 0xf
726#define bSFactorQAM2 0xf0
727#define bSFactorQAM3 0xf00
728#define bSFactorQAM4 0xf000
729#define bSFactorQAM5 0xf0000
730#define bSFactorQAM6 0xf0000
731#define bSFactorQAM7 0xf00000
732#define bSFactorQAM8 0xf000000
733#define bSFactorQAM9 0xf0000000
734#define bCSIScheme 0x100000
735
736#define bNoiseLvlTopSet 0x3
737#define bChSmooth 0x4
738#define bChSmoothCfg1 0x38
739#define bChSmoothCfg2 0x1c0
740#define bChSmoothCfg3 0xe00
741#define bChSmoothCfg4 0x7000
742#define bMRCMode 0x800000
743#define bTHEVMCfg 0x7000000
744
745#define bLoopFitType 0x1
746#define bUpdCFO 0x40
747#define bUpdCFOOffData 0x80
748#define bAdvUpdCFO 0x100
749#define bAdvTimeCtrl 0x800
750#define bUpdClko 0x1000
751#define bFC 0x6000
752#define bTrackingMode 0x8000
753#define bPhCmpEnable 0x10000
754#define bUpdClkoLTF 0x20000
755#define bComChCFO 0x40000
756#define bCSIEstiMode 0x80000
757#define bAdvUpdEqz 0x100000
758#define bUChCfg 0x7000000
759#define bUpdEqz 0x8000000
760
761//page e
762#define bTxAGCRate18_06 0x7f7f7f7f
763#define bTxAGCRate54_24 0x7f7f7f7f
764#define bTxAGCRateMCS32 0x7f
765#define bTxAGCRateCCK 0x7f00
766#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
767#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
768#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
769#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
770
771
772//Rx Pseduo noise
773#define bRxPesudoNoiseOn 0x20000000
774#define bRxPesudoNoise_A 0xff
775#define bRxPesudoNoise_B 0xff00
776#define bRxPesudoNoise_C 0xff0000
777#define bRxPesudoNoise_D 0xff000000
778#define bPesudoNoiseState_A 0xffff
779#define bPesudoNoiseState_B 0xffff0000
780#define bPesudoNoiseState_C 0xffff
781#define bPesudoNoiseState_D 0xffff0000
782
783//RF
784//Zebra1
785#define bZebra1_HSSIEnable 0x8
786#define bZebra1_TRxControl 0xc00
787#define bZebra1_TRxGainSetting 0x07f
788#define bZebra1_RxCorner 0xc00
789#define bZebra1_TxChargePump 0x38
790#define bZebra1_RxChargePump 0x7
791#define bZebra1_ChannelNum 0xf80
792#define bZebra1_TxLPFBW 0x400
793#define bZebra1_RxLPFBW 0x600
794
795//Zebra4
796#define bRTL8256RegModeCtrl1 0x100
797#define bRTL8256RegModeCtrl0 0x40
798#define bRTL8256_TxLPFBW 0x18
799#define bRTL8256_RxLPFBW 0x600
800
801//RTL8258
802#define bRTL8258_TxLPFBW 0xc
803#define bRTL8258_RxLPFBW 0xc00
804#define bRTL8258_RSSILPFBW 0xc0
805
806//byte endable for sb_write
807#define bByte0 0x1
808#define bByte1 0x2
809#define bByte2 0x4
810#define bByte3 0x8
811#define bWord0 0x3
812#define bWord1 0xc
813#define bDWord 0xf
814
815//for PutRegsetting & GetRegSetting BitMask
816#define bMaskByte0 0xff
817#define bMaskByte1 0xff00
818#define bMaskByte2 0xff0000
819#define bMaskByte3 0xff000000
820#define bMaskHWord 0xffff0000
821#define bMaskLWord 0x0000ffff
822#define bMaskDWord 0xffffffff
823
824//for PutRFRegsetting & GetRFRegSetting BitMask
825#define bMask12Bits 0xfff
826
827#define bEnable 0x1
828#define bDisable 0x0
829
830#define LeftAntenna 0x0
831#define RightAntenna 0x1
832
833#define tCheckTxStatus 500 //500ms
834#define tUpdateRxCounter 100 //100ms
835
836#define rateCCK 0
837#define rateOFDM 1
838#define rateHT 2
839
840//define Register-End
841#define bPMAC_End 0x1ff
842#define bFPGAPHY0_End 0x8ff
843#define bFPGAPHY1_End 0x9ff
844#define bCCKPHY0_End 0xaff
845#define bOFDMPHY0_End 0xcff
846#define bOFDMPHY1_End 0xdff
847
848//define max debug item in each debug page
849//#define bMaxItem_FPGA_PHY0 0x9
850//#define bMaxItem_FPGA_PHY1 0x3
851//#define bMaxItem_PHY_11B 0x16
852//#define bMaxItem_OFDM_PHY0 0x29
853//#define bMaxItem_OFDM_PHY1 0x0
854
855#define bPMACControl 0x0
856#define bWMACControl 0x1
857#define bWNICControl 0x2
858
859#define PathA 0x0
860#define PathB 0x1
861#define PathC 0x2
862#define PathD 0x3
863
864#define rRTL8256RxMixerPole 0xb
865#define bZebraRxMixerPole 0x6
866#define rRTL8256TxBBOPBias 0x9
867#define bRTL8256TxBBOPBias 0x400
868#define rRTL8256TxBBBW 19
869#define bRTL8256TxBBBW 0x18
870
871#endif //__INC_HAL8190PCIPHYREG_H
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 15:21:19 -0400