diff options
Diffstat (limited to 'drivers/staging/rtl8192su/r819xU_phy.c')
-rw-r--r-- | drivers/staging/rtl8192su/r819xU_phy.c | 1826 |
1 files changed, 1826 insertions, 0 deletions
diff --git a/drivers/staging/rtl8192su/r819xU_phy.c b/drivers/staging/rtl8192su/r819xU_phy.c new file mode 100644 index 00000000000..00497d313f9 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_phy.c | |||
@@ -0,0 +1,1826 @@ | |||
1 | #include "r8192U.h" | ||
2 | #include "r8192U_hw.h" | ||
3 | #include "r819xU_phy.h" | ||
4 | #include "r819xU_phyreg.h" | ||
5 | #include "r8190_rtl8256.h" | ||
6 | #include "r8192U_dm.h" | ||
7 | #include "r819xU_firmware_img.h" | ||
8 | |||
9 | #ifdef ENABLE_DOT11D | ||
10 | #include "dot11d.h" | ||
11 | #endif | ||
12 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { | ||
13 | 0, | ||
14 | 0x085c, //2412 1 | ||
15 | 0x08dc, //2417 2 | ||
16 | 0x095c, //2422 3 | ||
17 | 0x09dc, //2427 4 | ||
18 | 0x0a5c, //2432 5 | ||
19 | 0x0adc, //2437 6 | ||
20 | 0x0b5c, //2442 7 | ||
21 | 0x0bdc, //2447 8 | ||
22 | 0x0c5c, //2452 9 | ||
23 | 0x0cdc, //2457 10 | ||
24 | 0x0d5c, //2462 11 | ||
25 | 0x0ddc, //2467 12 | ||
26 | 0x0e5c, //2472 13 | ||
27 | 0x0f72, //2484 | ||
28 | }; | ||
29 | |||
30 | |||
31 | #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray | ||
32 | #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG | ||
33 | #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array | ||
34 | #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array | ||
35 | #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array | ||
36 | #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array | ||
37 | #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array | ||
38 | #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array | ||
39 | |||
40 | /****************************************************************************** | ||
41 | *function: This function read BB parameters from Header file we gen, | ||
42 | * and do register read/write | ||
43 | * input: u32 dwBitMask //taget bit pos in the addr to be modified | ||
44 | * output: none | ||
45 | * return: u32 return the shift bit bit position of the mask | ||
46 | * ****************************************************************************/ | ||
47 | u32 rtl8192_CalculateBitShift(u32 dwBitMask) | ||
48 | { | ||
49 | u32 i; | ||
50 | for (i=0; i<=31; i++) | ||
51 | { | ||
52 | if (((dwBitMask>>i)&0x1) == 1) | ||
53 | break; | ||
54 | } | ||
55 | return i; | ||
56 | } | ||
57 | /****************************************************************************** | ||
58 | *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. | ||
59 | * input: none | ||
60 | * output: none | ||
61 | * return: 0(illegal, false), 1(legal,true) | ||
62 | * ***************************************************************************/ | ||
63 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) | ||
64 | { | ||
65 | u8 ret = 1; | ||
66 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
67 | if (priv->rf_type == RF_2T4R) | ||
68 | ret = 0; | ||
69 | else if (priv->rf_type == RF_1T2R) | ||
70 | { | ||
71 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) | ||
72 | ret = 1; | ||
73 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) | ||
74 | ret = 0; | ||
75 | } | ||
76 | return ret; | ||
77 | } | ||
78 | /****************************************************************************** | ||
79 | *function: This function set specific bits to BB register | ||
80 | * input: net_device dev | ||
81 | * u32 dwRegAddr //target addr to be modified | ||
82 | * u32 dwBitMask //taget bit pos in the addr to be modified | ||
83 | * u32 dwData //value to be write | ||
84 | * output: none | ||
85 | * return: none | ||
86 | * notice: | ||
87 | * ****************************************************************************/ | ||
88 | void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) | ||
89 | { | ||
90 | |||
91 | u32 OriginalValue, BitShift, NewValue; | ||
92 | |||
93 | if(dwBitMask!= bMaskDWord) | ||
94 | {//if not "double word" write | ||
95 | OriginalValue = read_nic_dword(dev, dwRegAddr); | ||
96 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | ||
97 | NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); | ||
98 | write_nic_dword(dev, dwRegAddr, NewValue); | ||
99 | }else | ||
100 | write_nic_dword(dev, dwRegAddr, dwData); | ||
101 | return; | ||
102 | } | ||
103 | /****************************************************************************** | ||
104 | *function: This function reads specific bits from BB register | ||
105 | * input: net_device dev | ||
106 | * u32 dwRegAddr //target addr to be readback | ||
107 | * u32 dwBitMask //taget bit pos in the addr to be readback | ||
108 | * output: none | ||
109 | * return: u32 Data //the readback register value | ||
110 | * notice: | ||
111 | * ****************************************************************************/ | ||
112 | u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) | ||
113 | { | ||
114 | u32 Ret = 0, OriginalValue, BitShift; | ||
115 | |||
116 | OriginalValue = read_nic_dword(dev, dwRegAddr); | ||
117 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | ||
118 | Ret =(OriginalValue & dwBitMask) >> BitShift; | ||
119 | |||
120 | return (Ret); | ||
121 | } | ||
122 | static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset ); | ||
123 | |||
124 | static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); | ||
125 | |||
126 | /****************************************************************************** | ||
127 | *function: This function read register from RF chip | ||
128 | * input: net_device dev | ||
129 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | ||
130 | * u32 Offset //target address to be read | ||
131 | * output: none | ||
132 | * return: u32 readback value | ||
133 | * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. | ||
134 | * ****************************************************************************/ | ||
135 | u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) | ||
136 | { | ||
137 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
138 | u32 ret = 0; | ||
139 | u32 NewOffset = 0; | ||
140 | BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; | ||
141 | rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); | ||
142 | //make sure RF register offset is correct | ||
143 | Offset &= 0x3f; | ||
144 | |||
145 | //switch page for 8256 RF IC | ||
146 | if (priv->rf_chip == RF_8256) | ||
147 | { | ||
148 | if (Offset >= 31) | ||
149 | { | ||
150 | priv->RfReg0Value[eRFPath] |= 0x140; | ||
151 | //Switch to Reg_Mode2 for Reg 31-45 | ||
152 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); | ||
153 | //modify offset | ||
154 | NewOffset = Offset -30; | ||
155 | } | ||
156 | else if (Offset >= 16) | ||
157 | { | ||
158 | priv->RfReg0Value[eRFPath] |= 0x100; | ||
159 | priv->RfReg0Value[eRFPath] &= (~0x40); | ||
160 | //Switch to Reg_Mode 1 for Reg16-30 | ||
161 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); | ||
162 | |||
163 | NewOffset = Offset - 15; | ||
164 | } | ||
165 | else | ||
166 | NewOffset = Offset; | ||
167 | } | ||
168 | else | ||
169 | { | ||
170 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); | ||
171 | NewOffset = Offset; | ||
172 | } | ||
173 | //put desired read addr to LSSI control Register | ||
174 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); | ||
175 | //Issue a posedge trigger | ||
176 | // | ||
177 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); | ||
178 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); | ||
179 | |||
180 | |||
181 | // TODO: we should not delay such a long time. Ask help from SD3 | ||
182 | msleep(1); | ||
183 | |||
184 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); | ||
185 | |||
186 | |||
187 | // Switch back to Reg_Mode0; | ||
188 | if(priv->rf_chip == RF_8256) | ||
189 | { | ||
190 | priv->RfReg0Value[eRFPath] &= 0xebf; | ||
191 | |||
192 | rtl8192_setBBreg( | ||
193 | dev, | ||
194 | pPhyReg->rf3wireOffset, | ||
195 | bMaskDWord, | ||
196 | (priv->RfReg0Value[eRFPath] << 16)); | ||
197 | } | ||
198 | |||
199 | return ret; | ||
200 | |||
201 | } | ||
202 | |||
203 | /****************************************************************************** | ||
204 | *function: This function write data to RF register | ||
205 | * input: net_device dev | ||
206 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | ||
207 | * u32 Offset //target address to be written | ||
208 | * u32 Data //The new register data to be written | ||
209 | * output: none | ||
210 | * return: none | ||
211 | * notice: For RF8256 only. | ||
212 | =========================================================== | ||
213 | *Reg Mode RegCTL[1] RegCTL[0] Note | ||
214 | * (Reg00[12]) (Reg00[10]) | ||
215 | *=========================================================== | ||
216 | *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) | ||
217 | *------------------------------------------------------------------ | ||
218 | *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) | ||
219 | *------------------------------------------------------------------ | ||
220 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) | ||
221 | *------------------------------------------------------------------ | ||
222 | * ****************************************************************************/ | ||
223 | void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) | ||
224 | { | ||
225 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
226 | u32 DataAndAddr = 0, NewOffset = 0; | ||
227 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; | ||
228 | |||
229 | Offset &= 0x3f; | ||
230 | //spin_lock_irqsave(&priv->rf_lock, flags); | ||
231 | // down(&priv->rf_sem); | ||
232 | if (priv->rf_chip == RF_8256) | ||
233 | { | ||
234 | |||
235 | if (Offset >= 31) | ||
236 | { | ||
237 | priv->RfReg0Value[eRFPath] |= 0x140; | ||
238 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); | ||
239 | NewOffset = Offset - 30; | ||
240 | } | ||
241 | else if (Offset >= 16) | ||
242 | { | ||
243 | priv->RfReg0Value[eRFPath] |= 0x100; | ||
244 | priv->RfReg0Value[eRFPath] &= (~0x40); | ||
245 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); | ||
246 | NewOffset = Offset - 15; | ||
247 | } | ||
248 | else | ||
249 | NewOffset = Offset; | ||
250 | } | ||
251 | else | ||
252 | { | ||
253 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); | ||
254 | NewOffset = Offset; | ||
255 | } | ||
256 | |||
257 | // Put write addr in [5:0] and write data in [31:16] | ||
258 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); | ||
259 | |||
260 | // Write Operation | ||
261 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); | ||
262 | |||
263 | |||
264 | if(Offset==0x0) | ||
265 | priv->RfReg0Value[eRFPath] = Data; | ||
266 | |||
267 | // Switch back to Reg_Mode0; | ||
268 | if(priv->rf_chip == RF_8256) | ||
269 | { | ||
270 | if(Offset != 0) | ||
271 | { | ||
272 | priv->RfReg0Value[eRFPath] &= 0xebf; | ||
273 | rtl8192_setBBreg( | ||
274 | dev, | ||
275 | pPhyReg->rf3wireOffset, | ||
276 | bMaskDWord, | ||
277 | (priv->RfReg0Value[eRFPath] << 16)); | ||
278 | } | ||
279 | } | ||
280 | //spin_unlock_irqrestore(&priv->rf_lock, flags); | ||
281 | // up(&priv->rf_sem); | ||
282 | return; | ||
283 | } | ||
284 | |||
285 | /****************************************************************************** | ||
286 | *function: This function set specific bits to RF register | ||
287 | * input: net_device dev | ||
288 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | ||
289 | * u32 RegAddr //target addr to be modified | ||
290 | * u32 BitMask //taget bit pos in the addr to be modified | ||
291 | * u32 Data //value to be write | ||
292 | * output: none | ||
293 | * return: none | ||
294 | * notice: | ||
295 | * ****************************************************************************/ | ||
296 | void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) | ||
297 | { | ||
298 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
299 | u32 Original_Value, BitShift, New_Value; | ||
300 | // u8 time = 0; | ||
301 | |||
302 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | ||
303 | return; | ||
304 | |||
305 | if (priv->Rf_Mode == RF_OP_By_FW) | ||
306 | { | ||
307 | if (BitMask != bMask12Bits) // RF data is 12 bits only | ||
308 | { | ||
309 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); | ||
310 | BitShift = rtl8192_CalculateBitShift(BitMask); | ||
311 | New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift); | ||
312 | |||
313 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); | ||
314 | }else | ||
315 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); | ||
316 | |||
317 | udelay(200); | ||
318 | |||
319 | } | ||
320 | else | ||
321 | { | ||
322 | if (BitMask != bMask12Bits) // RF data is 12 bits only | ||
323 | { | ||
324 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); | ||
325 | BitShift = rtl8192_CalculateBitShift(BitMask); | ||
326 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); | ||
327 | |||
328 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); | ||
329 | }else | ||
330 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); | ||
331 | } | ||
332 | return; | ||
333 | } | ||
334 | |||
335 | /****************************************************************************** | ||
336 | *function: This function reads specific bits from RF register | ||
337 | * input: net_device dev | ||
338 | * u32 RegAddr //target addr to be readback | ||
339 | * u32 BitMask //taget bit pos in the addr to be readback | ||
340 | * output: none | ||
341 | * return: u32 Data //the readback register value | ||
342 | * notice: | ||
343 | * ****************************************************************************/ | ||
344 | u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) | ||
345 | { | ||
346 | u32 Original_Value, Readback_Value, BitShift; | ||
347 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
348 | |||
349 | |||
350 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | ||
351 | return 0; | ||
352 | if (priv->Rf_Mode == RF_OP_By_FW) | ||
353 | { | ||
354 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); | ||
355 | BitShift = rtl8192_CalculateBitShift(BitMask); | ||
356 | Readback_Value = (Original_Value & BitMask) >> BitShift; | ||
357 | udelay(200); | ||
358 | return (Readback_Value); | ||
359 | } | ||
360 | else | ||
361 | { | ||
362 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); | ||
363 | BitShift = rtl8192_CalculateBitShift(BitMask); | ||
364 | Readback_Value = (Original_Value & BitMask) >> BitShift; | ||
365 | return (Readback_Value); | ||
366 | } | ||
367 | } | ||
368 | /****************************************************************************** | ||
369 | *function: We support firmware to execute RF-R/W. | ||
370 | * input: dev | ||
371 | * output: none | ||
372 | * return: none | ||
373 | * notice: | ||
374 | * ***************************************************************************/ | ||
375 | static u32 | ||
376 | phy_FwRFSerialRead( | ||
377 | struct net_device* dev, | ||
378 | RF90_RADIO_PATH_E eRFPath, | ||
379 | u32 Offset ) | ||
380 | { | ||
381 | u32 retValue = 0; | ||
382 | u32 Data = 0; | ||
383 | u8 time = 0; | ||
384 | //DbgPrint("FW RF CTRL\n\r"); | ||
385 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can | ||
386 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste | ||
387 | much time. This is only for site survey. */ | ||
388 | // 1. Read operation need not insert data. bit 0-11 | ||
389 | //Data &= bMask12Bits; | ||
390 | // 2. Write RF register address. Bit 12-19 | ||
391 | Data |= ((Offset&0xFF)<<12); | ||
392 | // 3. Write RF path. bit 20-21 | ||
393 | Data |= ((eRFPath&0x3)<<20); | ||
394 | // 4. Set RF read indicator. bit 22=0 | ||
395 | //Data |= 0x00000; | ||
396 | // 5. Trigger Fw to operate the command. bit 31 | ||
397 | Data |= 0x80000000; | ||
398 | // 6. We can not execute read operation if bit 31 is 1. | ||
399 | while (read_nic_dword(dev, QPNR)&0x80000000) | ||
400 | { | ||
401 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | ||
402 | if (time++ < 100) | ||
403 | { | ||
404 | //DbgPrint("FW not finish RF-R Time=%d\n\r", time); | ||
405 | udelay(10); | ||
406 | } | ||
407 | else | ||
408 | break; | ||
409 | } | ||
410 | // 7. Execute read operation. | ||
411 | write_nic_dword(dev, QPNR, Data); | ||
412 | // 8. Check if firmawre send back RF content. | ||
413 | while (read_nic_dword(dev, QPNR)&0x80000000) | ||
414 | { | ||
415 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | ||
416 | if (time++ < 100) | ||
417 | { | ||
418 | //DbgPrint("FW not finish RF-W Time=%d\n\r", time); | ||
419 | udelay(10); | ||
420 | } | ||
421 | else | ||
422 | return (0); | ||
423 | } | ||
424 | retValue = read_nic_dword(dev, RF_DATA); | ||
425 | |||
426 | return (retValue); | ||
427 | |||
428 | } /* phy_FwRFSerialRead */ | ||
429 | |||
430 | /****************************************************************************** | ||
431 | *function: We support firmware to execute RF-R/W. | ||
432 | * input: dev | ||
433 | * output: none | ||
434 | * return: none | ||
435 | * notice: | ||
436 | * ***************************************************************************/ | ||
437 | static void | ||
438 | phy_FwRFSerialWrite( | ||
439 | struct net_device* dev, | ||
440 | RF90_RADIO_PATH_E eRFPath, | ||
441 | u32 Offset, | ||
442 | u32 Data ) | ||
443 | { | ||
444 | u8 time = 0; | ||
445 | |||
446 | //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); | ||
447 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can | ||
448 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste | ||
449 | much time. This is only for site survey. */ | ||
450 | |||
451 | // 1. Set driver write bit and 12 bit data. bit 0-11 | ||
452 | //Data &= bMask12Bits; // Done by uper layer. | ||
453 | // 2. Write RF register address. bit 12-19 | ||
454 | Data |= ((Offset&0xFF)<<12); | ||
455 | // 3. Write RF path. bit 20-21 | ||
456 | Data |= ((eRFPath&0x3)<<20); | ||
457 | // 4. Set RF write indicator. bit 22=1 | ||
458 | Data |= 0x400000; | ||
459 | // 5. Trigger Fw to operate the command. bit 31=1 | ||
460 | Data |= 0x80000000; | ||
461 | |||
462 | // 6. Write operation. We can not write if bit 31 is 1. | ||
463 | while (read_nic_dword(dev, QPNR)&0x80000000) | ||
464 | { | ||
465 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | ||
466 | if (time++ < 100) | ||
467 | { | ||
468 | //DbgPrint("FW not finish RF-W Time=%d\n\r", time); | ||
469 | udelay(10); | ||
470 | } | ||
471 | else | ||
472 | break; | ||
473 | } | ||
474 | // 7. No matter check bit. We always force the write. Because FW will | ||
475 | // not accept the command. | ||
476 | write_nic_dword(dev, QPNR, Data); | ||
477 | /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware | ||
478 | to finish RF write operation. */ | ||
479 | /* 2008/01/17 MH We support delay in firmware side now. */ | ||
480 | //delay_us(20); | ||
481 | |||
482 | } /* phy_FwRFSerialWrite */ | ||
483 | |||
484 | |||
485 | /****************************************************************************** | ||
486 | *function: This function read BB parameters from Header file we gen, | ||
487 | * and do register read/write | ||
488 | * input: dev | ||
489 | * output: none | ||
490 | * return: none | ||
491 | * notice: BB parameters may change all the time, so please make | ||
492 | * sure it has been synced with the newest. | ||
493 | * ***************************************************************************/ | ||
494 | void rtl8192_phy_configmac(struct net_device* dev) | ||
495 | { | ||
496 | u32 dwArrayLen = 0, i; | ||
497 | u32* pdwArray = NULL; | ||
498 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
499 | |||
500 | if(priv->btxpowerdata_readfromEEPORM) | ||
501 | { | ||
502 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); | ||
503 | dwArrayLen = MACPHY_Array_PGLength; | ||
504 | pdwArray = rtl819XMACPHY_Array_PG; | ||
505 | |||
506 | } | ||
507 | else | ||
508 | { | ||
509 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); | ||
510 | dwArrayLen = MACPHY_ArrayLength; | ||
511 | pdwArray = rtl819XMACPHY_Array; | ||
512 | } | ||
513 | for(i = 0; i<dwArrayLen; i=i+3){ | ||
514 | if(pdwArray[i] == 0x318) | ||
515 | { | ||
516 | pdwArray[i+2] = 0x00000800; | ||
517 | //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", | ||
518 | // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); | ||
519 | } | ||
520 | |||
521 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", | ||
522 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | ||
523 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | ||
524 | } | ||
525 | return; | ||
526 | |||
527 | } | ||
528 | |||
529 | /****************************************************************************** | ||
530 | *function: This function do dirty work | ||
531 | * input: dev | ||
532 | * output: none | ||
533 | * return: none | ||
534 | * notice: BB parameters may change all the time, so please make | ||
535 | * sure it has been synced with the newest. | ||
536 | * ***************************************************************************/ | ||
537 | |||
538 | void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) | ||
539 | { | ||
540 | u32 i; | ||
541 | |||
542 | #ifdef TO_DO_LIST | ||
543 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; | ||
544 | if(Adapter->bInHctTest) | ||
545 | { | ||
546 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; | ||
547 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; | ||
548 | Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; | ||
549 | Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; | ||
550 | } | ||
551 | #endif | ||
552 | if (ConfigType == BaseBand_Config_PHY_REG) | ||
553 | { | ||
554 | for (i=0; i<PHY_REG_1T2RArrayLength; i+=2) | ||
555 | { | ||
556 | rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]); | ||
557 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]); | ||
558 | } | ||
559 | } | ||
560 | else if (ConfigType == BaseBand_Config_AGC_TAB) | ||
561 | { | ||
562 | for (i=0; i<AGCTAB_ArrayLength; i+=2) | ||
563 | { | ||
564 | rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]); | ||
565 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]); | ||
566 | } | ||
567 | } | ||
568 | return; | ||
569 | |||
570 | |||
571 | } | ||
572 | /****************************************************************************** | ||
573 | *function: This function initialize Register definition offset for Radio Path | ||
574 | * A/B/C/D | ||
575 | * input: net_device dev | ||
576 | * output: none | ||
577 | * return: none | ||
578 | * notice: Initialization value here is constant and it should never be changed | ||
579 | * ***************************************************************************/ | ||
580 | void rtl8192_InitBBRFRegDef(struct net_device* dev) | ||
581 | { | ||
582 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
583 | // RF Interface Sowrtware Control | ||
584 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 | ||
585 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) | ||
586 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 | ||
587 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) | ||
588 | |||
589 | // RF Interface Readback Value | ||
590 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 | ||
591 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) | ||
592 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 | ||
593 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) | ||
594 | |||
595 | // RF Interface Output (and Enable) | ||
596 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 | ||
597 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 | ||
598 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 | ||
599 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C | ||
600 | |||
601 | // RF Interface (Output and) Enable | ||
602 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) | ||
603 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) | ||
604 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) | ||
605 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) | ||
606 | |||
607 | //Addr of LSSI. Wirte RF register by driver | ||
608 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter | ||
609 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; | ||
610 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; | ||
611 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; | ||
612 | |||
613 | // RF parameter | ||
614 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select | ||
615 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; | ||
616 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; | ||
617 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; | ||
618 | |||
619 | // Tx AGC Gain Stage (same for all path. Should we remove this?) | ||
620 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | ||
621 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | ||
622 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | ||
623 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | ||
624 | |||
625 | // Tranceiver A~D HSSI Parameter-1 | ||
626 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 | ||
627 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 | ||
628 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 | ||
629 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 | ||
630 | |||
631 | // Tranceiver A~D HSSI Parameter-2 | ||
632 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 | ||
633 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 | ||
634 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 | ||
635 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 | ||
636 | |||
637 | // RF switch Control | ||
638 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control | ||
639 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; | ||
640 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; | ||
641 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; | ||
642 | |||
643 | // AGC control 1 | ||
644 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; | ||
645 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | ||
646 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; | ||
647 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; | ||
648 | |||
649 | // AGC control 2 | ||
650 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; | ||
651 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | ||
652 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; | ||
653 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; | ||
654 | |||
655 | // RX AFE control 1 | ||
656 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; | ||
657 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | ||
658 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; | ||
659 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; | ||
660 | |||
661 | // RX AFE control 1 | ||
662 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; | ||
663 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | ||
664 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; | ||
665 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; | ||
666 | |||
667 | // Tx AFE control 1 | ||
668 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; | ||
669 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | ||
670 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; | ||
671 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; | ||
672 | |||
673 | // Tx AFE control 2 | ||
674 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; | ||
675 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | ||
676 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; | ||
677 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; | ||
678 | |||
679 | // Tranceiver LSSI Readback | ||
680 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; | ||
681 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | ||
682 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; | ||
683 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; | ||
684 | |||
685 | } | ||
686 | /****************************************************************************** | ||
687 | *function: This function is to write register and then readback to make sure whether BB and RF is OK | ||
688 | * input: net_device dev | ||
689 | * HW90_BLOCK_E CheckBlock | ||
690 | * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF | ||
691 | * output: none | ||
692 | * return: return whether BB and RF is ok(0:OK; 1:Fail) | ||
693 | * notice: This function may be removed in the ASIC | ||
694 | * ***************************************************************************/ | ||
695 | u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) | ||
696 | { | ||
697 | // struct r8192_priv *priv = ieee80211_priv(dev); | ||
698 | // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; | ||
699 | u8 ret = 0; | ||
700 | u32 i, CheckTimes = 4, dwRegRead = 0; | ||
701 | u32 WriteAddr[4]; | ||
702 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; | ||
703 | // Initialize register address offset to be checked | ||
704 | WriteAddr[HW90_BLOCK_MAC] = 0x100; | ||
705 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; | ||
706 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; | ||
707 | WriteAddr[HW90_BLOCK_RF] = 0x3; | ||
708 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); | ||
709 | for(i=0 ; i < CheckTimes ; i++) | ||
710 | { | ||
711 | |||
712 | // | ||
713 | // Write Data to register and readback | ||
714 | // | ||
715 | switch(CheckBlock) | ||
716 | { | ||
717 | case HW90_BLOCK_MAC: | ||
718 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); | ||
719 | break; | ||
720 | |||
721 | case HW90_BLOCK_PHY0: | ||
722 | case HW90_BLOCK_PHY1: | ||
723 | write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); | ||
724 | dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); | ||
725 | break; | ||
726 | |||
727 | case HW90_BLOCK_RF: | ||
728 | WriteData[i] &= 0xfff; | ||
729 | rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); | ||
730 | // TODO: we should not delay for such a long time. Ask SD3 | ||
731 | msleep(1); | ||
732 | dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); | ||
733 | msleep(1); | ||
734 | break; | ||
735 | |||
736 | default: | ||
737 | ret = 1; | ||
738 | break; | ||
739 | } | ||
740 | |||
741 | |||
742 | // | ||
743 | // Check whether readback data is correct | ||
744 | // | ||
745 | if(dwRegRead != WriteData[i]) | ||
746 | { | ||
747 | RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); | ||
748 | ret = 1; | ||
749 | break; | ||
750 | } | ||
751 | } | ||
752 | |||
753 | return ret; | ||
754 | } | ||
755 | |||
756 | |||
757 | /****************************************************************************** | ||
758 | *function: This function initialize BB&RF | ||
759 | * input: net_device dev | ||
760 | * output: none | ||
761 | * return: none | ||
762 | * notice: Initialization value may change all the time, so please make | ||
763 | * sure it has been synced with the newest. | ||
764 | * ***************************************************************************/ | ||
765 | void rtl8192_BB_Config_ParaFile(struct net_device* dev) | ||
766 | { | ||
767 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
768 | u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0; | ||
769 | u32 dwRegValue = 0; | ||
770 | /************************************** | ||
771 | //<1>Initialize BaseBand | ||
772 | **************************************/ | ||
773 | |||
774 | /*--set BB Global Reset--*/ | ||
775 | bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); | ||
776 | write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); | ||
777 | mdelay(50); | ||
778 | /*---set BB reset Active---*/ | ||
779 | dwRegValue = read_nic_dword(dev, CPU_GEN); | ||
780 | write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); | ||
781 | |||
782 | /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ | ||
783 | // TODO: this function should be removed on ASIC , Emily 2007.2.2 | ||
784 | for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) | ||
785 | { | ||
786 | rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path | ||
787 | if(rtStatus != 0) | ||
788 | { | ||
789 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); | ||
790 | return ; | ||
791 | } | ||
792 | } | ||
793 | /*---- Set CCK and OFDM Block "OFF"----*/ | ||
794 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); | ||
795 | /*----BB Register Initilazation----*/ | ||
796 | //==m==>Set PHY REG From Header<==m== | ||
797 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); | ||
798 | |||
799 | /*----Set BB reset de-Active----*/ | ||
800 | dwRegValue = read_nic_dword(dev, CPU_GEN); | ||
801 | write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); | ||
802 | |||
803 | /*----BB AGC table Initialization----*/ | ||
804 | //==m==>Set PHY REG From Header<==m== | ||
805 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); | ||
806 | |||
807 | /*----Enable XSTAL ----*/ | ||
808 | write_nic_byte_E(dev, 0x5e, 0x00); | ||
809 | if (priv->card_8192_version == (u8)VERSION_819xU_A) | ||
810 | { | ||
811 | //Antenna gain offset from B/C/D to A | ||
812 | dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); | ||
813 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue); | ||
814 | |||
815 | //XSTALLCap | ||
816 | dwRegValue = priv->CrystalCap & 0xf; | ||
817 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); | ||
818 | } | ||
819 | |||
820 | // Check if the CCK HighPower is turned ON. | ||
821 | // This is used to calculate PWDB. | ||
822 | priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); | ||
823 | return; | ||
824 | } | ||
825 | /****************************************************************************** | ||
826 | *function: This function initialize BB&RF | ||
827 | * input: net_device dev | ||
828 | * output: none | ||
829 | * return: none | ||
830 | * notice: Initialization value may change all the time, so please make | ||
831 | * sure it has been synced with the newest. | ||
832 | * ***************************************************************************/ | ||
833 | void rtl8192_BBConfig(struct net_device* dev) | ||
834 | { | ||
835 | rtl8192_InitBBRFRegDef(dev); | ||
836 | //config BB&RF. As hardCode based initialization has not been well | ||
837 | //implemented, so use file first.FIXME:should implement it for hardcode? | ||
838 | rtl8192_BB_Config_ParaFile(dev); | ||
839 | return; | ||
840 | } | ||
841 | |||
842 | /****************************************************************************** | ||
843 | *function: This function obtains the initialization value of Tx power Level offset | ||
844 | * input: net_device dev | ||
845 | * output: none | ||
846 | * return: none | ||
847 | * ***************************************************************************/ | ||
848 | void rtl8192_phy_getTxPower(struct net_device* dev) | ||
849 | { | ||
850 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
851 | priv->MCSTxPowerLevelOriginalOffset[0] = | ||
852 | read_nic_dword(dev, rTxAGC_Rate18_06); | ||
853 | priv->MCSTxPowerLevelOriginalOffset[1] = | ||
854 | read_nic_dword(dev, rTxAGC_Rate54_24); | ||
855 | priv->MCSTxPowerLevelOriginalOffset[2] = | ||
856 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); | ||
857 | priv->MCSTxPowerLevelOriginalOffset[3] = | ||
858 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); | ||
859 | priv->MCSTxPowerLevelOriginalOffset[4] = | ||
860 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); | ||
861 | priv->MCSTxPowerLevelOriginalOffset[5] = | ||
862 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); | ||
863 | |||
864 | // read rx initial gain | ||
865 | priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); | ||
866 | priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); | ||
867 | priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); | ||
868 | priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); | ||
869 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", | ||
870 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], | ||
871 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); | ||
872 | |||
873 | // read framesync | ||
874 | priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); | ||
875 | priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2); | ||
876 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", | ||
877 | rOFDM0_RxDetector3, priv->framesync); | ||
878 | |||
879 | // read SIFS (save the value read fome MACPHY_REG.txt) | ||
880 | priv->SifsTime = read_nic_word(dev, SIFS); | ||
881 | |||
882 | return; | ||
883 | } | ||
884 | |||
885 | /****************************************************************************** | ||
886 | *function: This function obtains the initialization value of Tx power Level offset | ||
887 | * input: net_device dev | ||
888 | * output: none | ||
889 | * return: none | ||
890 | * ***************************************************************************/ | ||
891 | void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) | ||
892 | { | ||
893 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
894 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | ||
895 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | ||
896 | |||
897 | switch(priv->rf_chip) | ||
898 | { | ||
899 | case RF_8256: | ||
900 | PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement | ||
901 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | ||
902 | break; | ||
903 | default: | ||
904 | // case RF_8225: | ||
905 | // case RF_8258: | ||
906 | RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__); | ||
907 | break; | ||
908 | } | ||
909 | return; | ||
910 | } | ||
911 | |||
912 | /****************************************************************************** | ||
913 | *function: This function check Rf chip to do RF config | ||
914 | * input: net_device dev | ||
915 | * output: none | ||
916 | * return: only 8256 is supported | ||
917 | * ***************************************************************************/ | ||
918 | void rtl8192_phy_RFConfig(struct net_device* dev) | ||
919 | { | ||
920 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
921 | |||
922 | switch(priv->rf_chip) | ||
923 | { | ||
924 | case RF_8256: | ||
925 | PHY_RF8256_Config(dev); | ||
926 | break; | ||
927 | // case RF_8225: | ||
928 | // case RF_8258: | ||
929 | default: | ||
930 | RT_TRACE(COMP_ERR, "error chip id\n"); | ||
931 | break; | ||
932 | } | ||
933 | return; | ||
934 | } | ||
935 | |||
936 | /****************************************************************************** | ||
937 | *function: This function update Initial gain | ||
938 | * input: net_device dev | ||
939 | * output: none | ||
940 | * return: As Windows has not implemented this, wait for complement | ||
941 | * ***************************************************************************/ | ||
942 | void rtl8192_phy_updateInitGain(struct net_device* dev) | ||
943 | { | ||
944 | return; | ||
945 | } | ||
946 | |||
947 | /****************************************************************************** | ||
948 | *function: This function read RF parameters from general head file, and do RF 3-wire | ||
949 | * input: net_device dev | ||
950 | * output: none | ||
951 | * return: return code show if RF configuration is successful(0:pass, 1:fail) | ||
952 | * Note: Delay may be required for RF configuration | ||
953 | * ***************************************************************************/ | ||
954 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) | ||
955 | { | ||
956 | |||
957 | int i; | ||
958 | //u32* pRFArray; | ||
959 | u8 ret = 0; | ||
960 | |||
961 | switch(eRFPath){ | ||
962 | case RF90_PATH_A: | ||
963 | for(i = 0;i<RadioA_ArrayLength; i=i+2){ | ||
964 | |||
965 | if(rtl819XRadioA_Array[i] == 0xfe){ | ||
966 | mdelay(100); | ||
967 | continue; | ||
968 | } | ||
969 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]); | ||
970 | mdelay(1); | ||
971 | |||
972 | } | ||
973 | break; | ||
974 | case RF90_PATH_B: | ||
975 | for(i = 0;i<RadioB_ArrayLength; i=i+2){ | ||
976 | |||
977 | if(rtl819XRadioB_Array[i] == 0xfe){ | ||
978 | mdelay(100); | ||
979 | continue; | ||
980 | } | ||
981 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]); | ||
982 | mdelay(1); | ||
983 | |||
984 | } | ||
985 | break; | ||
986 | case RF90_PATH_C: | ||
987 | for(i = 0;i<RadioC_ArrayLength; i=i+2){ | ||
988 | |||
989 | if(rtl819XRadioC_Array[i] == 0xfe){ | ||
990 | mdelay(100); | ||
991 | continue; | ||
992 | } | ||
993 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]); | ||
994 | mdelay(1); | ||
995 | |||
996 | } | ||
997 | break; | ||
998 | case RF90_PATH_D: | ||
999 | for(i = 0;i<RadioD_ArrayLength; i=i+2){ | ||
1000 | |||
1001 | if(rtl819XRadioD_Array[i] == 0xfe){ | ||
1002 | mdelay(100); | ||
1003 | continue; | ||
1004 | } | ||
1005 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]); | ||
1006 | mdelay(1); | ||
1007 | |||
1008 | } | ||
1009 | break; | ||
1010 | default: | ||
1011 | break; | ||
1012 | } | ||
1013 | |||
1014 | return ret;; | ||
1015 | |||
1016 | } | ||
1017 | /****************************************************************************** | ||
1018 | *function: This function set Tx Power of the channel | ||
1019 | * input: struct net_device *dev | ||
1020 | * u8 channel | ||
1021 | * output: none | ||
1022 | * return: none | ||
1023 | * Note: | ||
1024 | * ***************************************************************************/ | ||
1025 | void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) | ||
1026 | { | ||
1027 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1028 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | ||
1029 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | ||
1030 | |||
1031 | switch(priv->rf_chip) | ||
1032 | { | ||
1033 | case RF_8225: | ||
1034 | #ifdef TO_DO_LIST | ||
1035 | PHY_SetRF8225CckTxPower(Adapter, powerlevel); | ||
1036 | PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); | ||
1037 | #endif | ||
1038 | break; | ||
1039 | |||
1040 | case RF_8256: | ||
1041 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | ||
1042 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | ||
1043 | break; | ||
1044 | |||
1045 | case RF_8258: | ||
1046 | break; | ||
1047 | default: | ||
1048 | RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); | ||
1049 | break; | ||
1050 | } | ||
1051 | return; | ||
1052 | } | ||
1053 | |||
1054 | /****************************************************************************** | ||
1055 | *function: This function set RF state on or off | ||
1056 | * input: struct net_device *dev | ||
1057 | * RT_RF_POWER_STATE eRFPowerState //Power State to set | ||
1058 | * output: none | ||
1059 | * return: none | ||
1060 | * Note: | ||
1061 | * ***************************************************************************/ | ||
1062 | bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) | ||
1063 | { | ||
1064 | bool bResult = true; | ||
1065 | // u8 eRFPath; | ||
1066 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1067 | |||
1068 | if(eRFPowerState == priv->ieee80211->eRFPowerState) | ||
1069 | return false; | ||
1070 | |||
1071 | if(priv->SetRFPowerStateInProgress == true) | ||
1072 | return false; | ||
1073 | |||
1074 | priv->SetRFPowerStateInProgress = true; | ||
1075 | |||
1076 | switch(priv->rf_chip) | ||
1077 | { | ||
1078 | case RF_8256: | ||
1079 | switch( eRFPowerState ) | ||
1080 | { | ||
1081 | case eRfOn: | ||
1082 | #if 0 | ||
1083 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] | ||
1084 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); // 0x88c[4] | ||
1085 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] | ||
1086 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x3); // 0xc04[3:0] | ||
1087 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); // 0xd04[3:0] | ||
1088 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x3); // 0x884[14:12] | ||
1089 | // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) | ||
1090 | // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); | ||
1091 | |||
1092 | //SwChnl(Adapter->ChannelID); | ||
1093 | #endif | ||
1094 | //RF-A, RF-B | ||
1095 | //enable RF-Chip A/B | ||
1096 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] | ||
1097 | //analog to digital on | ||
1098 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] | ||
1099 | //digital to analog on | ||
1100 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] | ||
1101 | //rx antenna on | ||
1102 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] | ||
1103 | //rx antenna on | ||
1104 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] | ||
1105 | //analog to digital part2 on | ||
1106 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] | ||
1107 | |||
1108 | break; | ||
1109 | |||
1110 | case eRfSleep: | ||
1111 | |||
1112 | break; | ||
1113 | |||
1114 | case eRfOff: | ||
1115 | #if 0 | ||
1116 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] | ||
1117 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); // 0x88c[4] | ||
1118 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] | ||
1119 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0); // 0xc04[3:0] | ||
1120 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0); // 0xd04[3:0] | ||
1121 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x0); // 0x884[14:12] | ||
1122 | // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) | ||
1123 | // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); | ||
1124 | #endif | ||
1125 | //RF-A, RF-B | ||
1126 | //disable RF-Chip A/B | ||
1127 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] | ||
1128 | //analog to digital off, for power save | ||
1129 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] | ||
1130 | //digital to analog off, for power save | ||
1131 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] | ||
1132 | //rx antenna off | ||
1133 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] | ||
1134 | //rx antenna off | ||
1135 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] | ||
1136 | //analog to digital part2 off, for power save | ||
1137 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] | ||
1138 | |||
1139 | break; | ||
1140 | |||
1141 | default: | ||
1142 | bResult = false; | ||
1143 | RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState); | ||
1144 | break; | ||
1145 | } | ||
1146 | break; | ||
1147 | default: | ||
1148 | RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); | ||
1149 | break; | ||
1150 | } | ||
1151 | #ifdef TO_DO_LIST | ||
1152 | if(bResult) | ||
1153 | { | ||
1154 | // Update current RF state variable. | ||
1155 | pHalData->eRFPowerState = eRFPowerState; | ||
1156 | switch(pHalData->RFChipID ) | ||
1157 | { | ||
1158 | case RF_8256: | ||
1159 | switch(pHalData->eRFPowerState) | ||
1160 | { | ||
1161 | case eRfOff: | ||
1162 | // | ||
1163 | //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 | ||
1164 | // | ||
1165 | if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) | ||
1166 | { | ||
1167 | Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); | ||
1168 | } | ||
1169 | else | ||
1170 | { | ||
1171 | // Turn off LED if RF is not ON. | ||
1172 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); | ||
1173 | } | ||
1174 | break; | ||
1175 | |||
1176 | case eRfOn: | ||
1177 | // Turn on RF we are still linked, which might happen when | ||
1178 | // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. | ||
1179 | if( pMgntInfo->bMediaConnect == TRUE ) | ||
1180 | { | ||
1181 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); | ||
1182 | } | ||
1183 | else | ||
1184 | { | ||
1185 | // Turn off LED if RF is not ON. | ||
1186 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); | ||
1187 | } | ||
1188 | break; | ||
1189 | |||
1190 | default: | ||
1191 | // do nothing. | ||
1192 | break; | ||
1193 | }// Switch RF state | ||
1194 | break; | ||
1195 | |||
1196 | default: | ||
1197 | RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n")); | ||
1198 | break; | ||
1199 | } | ||
1200 | |||
1201 | } | ||
1202 | #endif | ||
1203 | priv->SetRFPowerStateInProgress = false; | ||
1204 | |||
1205 | return bResult; | ||
1206 | } | ||
1207 | |||
1208 | /**************************************************************************************** | ||
1209 | *function: This function set command table variable(struct SwChnlCmd). | ||
1210 | * input: SwChnlCmd* CmdTable //table to be set. | ||
1211 | * u32 CmdTableIdx //variable index in table to be set | ||
1212 | * u32 CmdTableSz //table size. | ||
1213 | * SwChnlCmdID CmdID //command ID to set. | ||
1214 | * u32 Para1 | ||
1215 | * u32 Para2 | ||
1216 | * u32 msDelay | ||
1217 | * output: | ||
1218 | * return: true if finished, false otherwise | ||
1219 | * Note: | ||
1220 | * ************************************************************************************/ | ||
1221 | u8 rtl8192_phy_SetSwChnlCmdArray( | ||
1222 | SwChnlCmd* CmdTable, | ||
1223 | u32 CmdTableIdx, | ||
1224 | u32 CmdTableSz, | ||
1225 | SwChnlCmdID CmdID, | ||
1226 | u32 Para1, | ||
1227 | u32 Para2, | ||
1228 | u32 msDelay | ||
1229 | ) | ||
1230 | { | ||
1231 | SwChnlCmd* pCmd; | ||
1232 | |||
1233 | if(CmdTable == NULL) | ||
1234 | { | ||
1235 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); | ||
1236 | return false; | ||
1237 | } | ||
1238 | if(CmdTableIdx >= CmdTableSz) | ||
1239 | { | ||
1240 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", | ||
1241 | CmdTableIdx, CmdTableSz); | ||
1242 | return false; | ||
1243 | } | ||
1244 | |||
1245 | pCmd = CmdTable + CmdTableIdx; | ||
1246 | pCmd->CmdID = CmdID; | ||
1247 | pCmd->Para1 = Para1; | ||
1248 | pCmd->Para2 = Para2; | ||
1249 | pCmd->msDelay = msDelay; | ||
1250 | |||
1251 | return true; | ||
1252 | } | ||
1253 | /****************************************************************************** | ||
1254 | *function: This function set channel step by step | ||
1255 | * input: struct net_device *dev | ||
1256 | * u8 channel | ||
1257 | * u8* stage //3 stages | ||
1258 | * u8* step // | ||
1259 | * u32* delay //whether need to delay | ||
1260 | * output: store new stage, step and delay for next step(combine with function above) | ||
1261 | * return: true if finished, false otherwise | ||
1262 | * Note: Wait for simpler function to replace it //wb | ||
1263 | * ***************************************************************************/ | ||
1264 | u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) | ||
1265 | { | ||
1266 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1267 | // PCHANNEL_ACCESS_SETTING pChnlAccessSetting; | ||
1268 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; | ||
1269 | u32 PreCommonCmdCnt; | ||
1270 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; | ||
1271 | u32 PostCommonCmdCnt; | ||
1272 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; | ||
1273 | u32 RfDependCmdCnt; | ||
1274 | SwChnlCmd *CurrentCmd = NULL; | ||
1275 | //RF90_RADIO_PATH_E eRFPath; | ||
1276 | u8 eRFPath; | ||
1277 | // u32 RfRetVal; | ||
1278 | // u8 RetryCnt; | ||
1279 | |||
1280 | RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); | ||
1281 | // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); | ||
1282 | #ifdef ENABLE_DOT11D | ||
1283 | if (!IsLegalChannel(priv->ieee80211, channel)) | ||
1284 | { | ||
1285 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); | ||
1286 | return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. | ||
1287 | } | ||
1288 | #endif | ||
1289 | //FIXME:need to check whether channel is legal or not here.WB | ||
1290 | |||
1291 | |||
1292 | //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) | ||
1293 | // for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) | ||
1294 | // { | ||
1295 | // if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | ||
1296 | // continue; | ||
1297 | // <1> Fill up pre common command. | ||
1298 | PreCommonCmdCnt = 0; | ||
1299 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, | ||
1300 | CmdID_SetTxPowerLevel, 0, 0, 0); | ||
1301 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, | ||
1302 | CmdID_End, 0, 0, 0); | ||
1303 | |||
1304 | // <2> Fill up post common command. | ||
1305 | PostCommonCmdCnt = 0; | ||
1306 | |||
1307 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, | ||
1308 | CmdID_End, 0, 0, 0); | ||
1309 | |||
1310 | // <3> Fill up RF dependent command. | ||
1311 | RfDependCmdCnt = 0; | ||
1312 | switch( priv->rf_chip ) | ||
1313 | { | ||
1314 | case RF_8225: | ||
1315 | if (!(channel >= 1 && channel <= 14)) | ||
1316 | { | ||
1317 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); | ||
1318 | return true; | ||
1319 | } | ||
1320 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | ||
1321 | CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); | ||
1322 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | ||
1323 | CmdID_End, 0, 0, 0); | ||
1324 | break; | ||
1325 | |||
1326 | case RF_8256: | ||
1327 | // TEST!! This is not the table for 8256!! | ||
1328 | if (!(channel >= 1 && channel <= 14)) | ||
1329 | { | ||
1330 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); | ||
1331 | return true; | ||
1332 | } | ||
1333 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | ||
1334 | CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); | ||
1335 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | ||
1336 | CmdID_End, 0, 0, 0); | ||
1337 | break; | ||
1338 | |||
1339 | case RF_8258: | ||
1340 | break; | ||
1341 | |||
1342 | default: | ||
1343 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | ||
1344 | return true; | ||
1345 | break; | ||
1346 | } | ||
1347 | |||
1348 | |||
1349 | do{ | ||
1350 | switch(*stage) | ||
1351 | { | ||
1352 | case 0: | ||
1353 | CurrentCmd=&PreCommonCmd[*step]; | ||
1354 | break; | ||
1355 | case 1: | ||
1356 | CurrentCmd=&RfDependCmd[*step]; | ||
1357 | break; | ||
1358 | case 2: | ||
1359 | CurrentCmd=&PostCommonCmd[*step]; | ||
1360 | break; | ||
1361 | } | ||
1362 | |||
1363 | if(CurrentCmd->CmdID==CmdID_End) | ||
1364 | { | ||
1365 | if((*stage)==2) | ||
1366 | { | ||
1367 | (*delay)=CurrentCmd->msDelay; | ||
1368 | return true; | ||
1369 | } | ||
1370 | else | ||
1371 | { | ||
1372 | (*stage)++; | ||
1373 | (*step)=0; | ||
1374 | continue; | ||
1375 | } | ||
1376 | } | ||
1377 | |||
1378 | switch(CurrentCmd->CmdID) | ||
1379 | { | ||
1380 | case CmdID_SetTxPowerLevel: | ||
1381 | if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later! | ||
1382 | rtl8192_SetTxPowerLevel(dev,channel); | ||
1383 | break; | ||
1384 | case CmdID_WritePortUlong: | ||
1385 | write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); | ||
1386 | break; | ||
1387 | case CmdID_WritePortUshort: | ||
1388 | write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); | ||
1389 | break; | ||
1390 | case CmdID_WritePortUchar: | ||
1391 | write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); | ||
1392 | break; | ||
1393 | case CmdID_RF_WriteReg: | ||
1394 | for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) | ||
1395 | { | ||
1396 | rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); | ||
1397 | } | ||
1398 | break; | ||
1399 | default: | ||
1400 | break; | ||
1401 | } | ||
1402 | |||
1403 | break; | ||
1404 | }while(true); | ||
1405 | // }/*for(Number of RF paths)*/ | ||
1406 | |||
1407 | (*delay)=CurrentCmd->msDelay; | ||
1408 | (*step)++; | ||
1409 | return false; | ||
1410 | } | ||
1411 | |||
1412 | /****************************************************************************** | ||
1413 | *function: This function does acturally set channel work | ||
1414 | * input: struct net_device *dev | ||
1415 | * u8 channel | ||
1416 | * output: none | ||
1417 | * return: noin | ||
1418 | * Note: We should not call this function directly | ||
1419 | * ***************************************************************************/ | ||
1420 | void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) | ||
1421 | { | ||
1422 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1423 | u32 delay = 0; | ||
1424 | |||
1425 | while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) | ||
1426 | { | ||
1427 | // if(delay>0) | ||
1428 | // msleep(delay);//or mdelay? need further consideration | ||
1429 | if(!priv->up) | ||
1430 | break; | ||
1431 | } | ||
1432 | } | ||
1433 | /****************************************************************************** | ||
1434 | *function: Callback routine of the work item for switch channel. | ||
1435 | * input: | ||
1436 | * | ||
1437 | * output: none | ||
1438 | * return: noin | ||
1439 | * ***************************************************************************/ | ||
1440 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) | ||
1441 | { | ||
1442 | |||
1443 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1444 | |||
1445 | RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan); | ||
1446 | |||
1447 | |||
1448 | rtl8192_phy_FinishSwChnlNow(dev , priv->chan); | ||
1449 | |||
1450 | RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); | ||
1451 | } | ||
1452 | |||
1453 | /****************************************************************************** | ||
1454 | *function: This function scheduled actural workitem to set channel | ||
1455 | * input: net_device dev | ||
1456 | * u8 channel //channel to set | ||
1457 | * output: none | ||
1458 | * return: return code show if workitem is scheduled(1:pass, 0:fail) | ||
1459 | * Note: Delay may be required for RF configuration | ||
1460 | * ***************************************************************************/ | ||
1461 | u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) | ||
1462 | { | ||
1463 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1464 | RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress); | ||
1465 | if(!priv->up) | ||
1466 | return false; | ||
1467 | if(priv->SwChnlInProgress) | ||
1468 | return false; | ||
1469 | |||
1470 | // if(pHalData->SetBWModeInProgress) | ||
1471 | // return; | ||
1472 | if (0) //to test current channel from RF reg 0x7. | ||
1473 | { | ||
1474 | u8 eRFPath; | ||
1475 | for(eRFPath = 0; eRFPath < 2; eRFPath++){ | ||
1476 | printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum)); | ||
1477 | udelay(10); | ||
1478 | } | ||
1479 | } | ||
1480 | //-------------------------------------------- | ||
1481 | switch(priv->ieee80211->mode) | ||
1482 | { | ||
1483 | case WIRELESS_MODE_A: | ||
1484 | case WIRELESS_MODE_N_5G: | ||
1485 | if (channel<=14){ | ||
1486 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); | ||
1487 | return false; | ||
1488 | } | ||
1489 | break; | ||
1490 | case WIRELESS_MODE_B: | ||
1491 | if (channel>14){ | ||
1492 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); | ||
1493 | return false; | ||
1494 | } | ||
1495 | break; | ||
1496 | case WIRELESS_MODE_G: | ||
1497 | case WIRELESS_MODE_N_24G: | ||
1498 | if (channel>14){ | ||
1499 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); | ||
1500 | return false; | ||
1501 | } | ||
1502 | break; | ||
1503 | } | ||
1504 | //-------------------------------------------- | ||
1505 | |||
1506 | priv->SwChnlInProgress = true; | ||
1507 | if(channel == 0) | ||
1508 | channel = 1; | ||
1509 | |||
1510 | priv->chan=channel; | ||
1511 | |||
1512 | priv->SwChnlStage=0; | ||
1513 | priv->SwChnlStep=0; | ||
1514 | // schedule_work(&(priv->SwChnlWorkItem)); | ||
1515 | // rtl8192_SwChnl_WorkItem(dev); | ||
1516 | if(priv->up) { | ||
1517 | // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); | ||
1518 | rtl8192_SwChnl_WorkItem(dev); | ||
1519 | } | ||
1520 | |||
1521 | priv->SwChnlInProgress = false; | ||
1522 | return true; | ||
1523 | } | ||
1524 | |||
1525 | |||
1526 | // | ||
1527 | /****************************************************************************** | ||
1528 | *function: Callback routine of the work item for set bandwidth mode. | ||
1529 | * input: struct net_device *dev | ||
1530 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M | ||
1531 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care | ||
1532 | * output: none | ||
1533 | * return: none | ||
1534 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can | ||
1535 | * test whether current work in the queue or not.//do I? | ||
1536 | * ***************************************************************************/ | ||
1537 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) | ||
1538 | { | ||
1539 | |||
1540 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1541 | u8 regBwOpMode; | ||
1542 | |||
1543 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ | ||
1544 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") | ||
1545 | |||
1546 | |||
1547 | if(priv->rf_chip == RF_PSEUDO_11N) | ||
1548 | { | ||
1549 | priv->SetBWModeInProgress= false; | ||
1550 | return; | ||
1551 | } | ||
1552 | |||
1553 | //<1>Set MAC register | ||
1554 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); | ||
1555 | |||
1556 | switch(priv->CurrentChannelBW) | ||
1557 | { | ||
1558 | case HT_CHANNEL_WIDTH_20: | ||
1559 | regBwOpMode |= BW_OPMODE_20MHZ; | ||
1560 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works | ||
1561 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | ||
1562 | break; | ||
1563 | |||
1564 | case HT_CHANNEL_WIDTH_20_40: | ||
1565 | regBwOpMode &= ~BW_OPMODE_20MHZ; | ||
1566 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works | ||
1567 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | ||
1568 | break; | ||
1569 | |||
1570 | default: | ||
1571 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); | ||
1572 | break; | ||
1573 | } | ||
1574 | |||
1575 | //<2>Set PHY related register | ||
1576 | switch(priv->CurrentChannelBW) | ||
1577 | { | ||
1578 | case HT_CHANNEL_WIDTH_20: | ||
1579 | // Add by Vivi 20071119 | ||
1580 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); | ||
1581 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); | ||
1582 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); | ||
1583 | |||
1584 | // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 | ||
1585 | #if 0 | ||
1586 | write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); | ||
1587 | write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); | ||
1588 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); | ||
1589 | #endif | ||
1590 | priv->cck_present_attentuation = | ||
1591 | priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; | ||
1592 | |||
1593 | if(priv->cck_present_attentuation > 22) | ||
1594 | priv->cck_present_attentuation= 22; | ||
1595 | if(priv->cck_present_attentuation< 0) | ||
1596 | priv->cck_present_attentuation = 0; | ||
1597 | RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); | ||
1598 | |||
1599 | if(priv->chan == 14 && !priv->bcck_in_ch14) | ||
1600 | { | ||
1601 | priv->bcck_in_ch14 = TRUE; | ||
1602 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1603 | } | ||
1604 | else if(priv->chan != 14 && priv->bcck_in_ch14) | ||
1605 | { | ||
1606 | priv->bcck_in_ch14 = FALSE; | ||
1607 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1608 | } | ||
1609 | else | ||
1610 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1611 | |||
1612 | break; | ||
1613 | case HT_CHANNEL_WIDTH_20_40: | ||
1614 | // Add by Vivi 20071119 | ||
1615 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); | ||
1616 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); | ||
1617 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); | ||
1618 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); | ||
1619 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); | ||
1620 | #if 0 | ||
1621 | // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 | ||
1622 | write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); | ||
1623 | write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); | ||
1624 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); | ||
1625 | #endif | ||
1626 | priv->cck_present_attentuation = | ||
1627 | priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; | ||
1628 | |||
1629 | if(priv->cck_present_attentuation > 22) | ||
1630 | priv->cck_present_attentuation = 22; | ||
1631 | if(priv->cck_present_attentuation < 0) | ||
1632 | priv->cck_present_attentuation = 0; | ||
1633 | |||
1634 | RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); | ||
1635 | if(priv->chan == 14 && !priv->bcck_in_ch14) | ||
1636 | { | ||
1637 | priv->bcck_in_ch14 = true; | ||
1638 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1639 | } | ||
1640 | else if(priv->chan!= 14 && priv->bcck_in_ch14) | ||
1641 | { | ||
1642 | priv->bcck_in_ch14 = false; | ||
1643 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1644 | } | ||
1645 | else | ||
1646 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); | ||
1647 | |||
1648 | break; | ||
1649 | default: | ||
1650 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); | ||
1651 | break; | ||
1652 | |||
1653 | } | ||
1654 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 | ||
1655 | |||
1656 | #if 1 | ||
1657 | //<3>Set RF related register | ||
1658 | switch( priv->rf_chip ) | ||
1659 | { | ||
1660 | case RF_8225: | ||
1661 | #ifdef TO_DO_LIST | ||
1662 | PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); | ||
1663 | #endif | ||
1664 | break; | ||
1665 | |||
1666 | case RF_8256: | ||
1667 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); | ||
1668 | break; | ||
1669 | |||
1670 | case RF_8258: | ||
1671 | // PHY_SetRF8258Bandwidth(); | ||
1672 | break; | ||
1673 | |||
1674 | case RF_PSEUDO_11N: | ||
1675 | // Do Nothing | ||
1676 | break; | ||
1677 | |||
1678 | default: | ||
1679 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | ||
1680 | break; | ||
1681 | } | ||
1682 | #endif | ||
1683 | priv->SetBWModeInProgress= false; | ||
1684 | |||
1685 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) ); | ||
1686 | } | ||
1687 | |||
1688 | /****************************************************************************** | ||
1689 | *function: This function schedules bandwith switch work. | ||
1690 | * input: struct net_device *dev | ||
1691 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M | ||
1692 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care | ||
1693 | * output: none | ||
1694 | * return: none | ||
1695 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can | ||
1696 | * test whether current work in the queue or not.//do I? | ||
1697 | * ***************************************************************************/ | ||
1698 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) | ||
1699 | { | ||
1700 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1701 | |||
1702 | if(priv->SetBWModeInProgress) | ||
1703 | return; | ||
1704 | priv->SetBWModeInProgress= true; | ||
1705 | |||
1706 | priv->CurrentChannelBW = Bandwidth; | ||
1707 | |||
1708 | if(Offset==HT_EXTCHNL_OFFSET_LOWER) | ||
1709 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; | ||
1710 | else if(Offset==HT_EXTCHNL_OFFSET_UPPER) | ||
1711 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; | ||
1712 | else | ||
1713 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; | ||
1714 | |||
1715 | //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); | ||
1716 | // schedule_work(&(priv->SetBWModeWorkItem)); | ||
1717 | rtl8192_SetBWModeWorkItem(dev); | ||
1718 | |||
1719 | } | ||
1720 | |||
1721 | void InitialGain819xUsb(struct net_device *dev, u8 Operation) | ||
1722 | { | ||
1723 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1724 | |||
1725 | priv->InitialGainOperateType = Operation; | ||
1726 | |||
1727 | if(priv->up) | ||
1728 | { | ||
1729 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) | ||
1730 | queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); | ||
1731 | #else | ||
1732 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) | ||
1733 | schedule_task(&priv->initialgain_operate_wq); | ||
1734 | #else | ||
1735 | queue_work(priv->priv_wq,&priv->initialgain_operate_wq); | ||
1736 | #endif | ||
1737 | #endif | ||
1738 | } | ||
1739 | } | ||
1740 | |||
1741 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) | ||
1742 | extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) | ||
1743 | { | ||
1744 | struct delayed_work *dwork = container_of(work,struct delayed_work,work); | ||
1745 | struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); | ||
1746 | struct net_device *dev = priv->ieee80211->dev; | ||
1747 | #else | ||
1748 | extern void InitialGainOperateWorkItemCallBack(struct net_device *dev) | ||
1749 | { | ||
1750 | struct r8192_priv *priv = ieee80211_priv(dev); | ||
1751 | #endif | ||
1752 | #define SCAN_RX_INITIAL_GAIN 0x17 | ||
1753 | #define POWER_DETECTION_TH 0x08 | ||
1754 | u32 BitMask; | ||
1755 | u8 initial_gain; | ||
1756 | u8 Operation; | ||
1757 | |||
1758 | Operation = priv->InitialGainOperateType; | ||
1759 | |||
1760 | switch(Operation) | ||
1761 | { | ||
1762 | case IG_Backup: | ||
1763 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); | ||
1764 | initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// | ||
1765 | BitMask = bMaskByte0; | ||
1766 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | ||
1767 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF | ||
1768 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); | ||
1769 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); | ||
1770 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); | ||
1771 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); | ||
1772 | BitMask = bMaskByte2; | ||
1773 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); | ||
1774 | |||
1775 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); | ||
1776 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); | ||
1777 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); | ||
1778 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); | ||
1779 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); | ||
1780 | |||
1781 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); | ||
1782 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); | ||
1783 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); | ||
1784 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); | ||
1785 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); | ||
1786 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); | ||
1787 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); | ||
1788 | break; | ||
1789 | case IG_Restore: | ||
1790 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); | ||
1791 | BitMask = 0x7f; //Bit0~ Bit6 | ||
1792 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | ||
1793 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF | ||
1794 | |||
1795 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); | ||
1796 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); | ||
1797 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); | ||
1798 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); | ||
1799 | BitMask = bMaskByte2; | ||
1800 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); | ||
1801 | |||
1802 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); | ||
1803 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); | ||
1804 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); | ||
1805 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); | ||
1806 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); | ||
1807 | |||
1808 | #ifdef RTL8190P | ||
1809 | SetTxPowerLevel8190(Adapter,priv->CurrentChannel); | ||
1810 | #endif | ||
1811 | #ifdef RTL8192E | ||
1812 | SetTxPowerLevel8190(Adapter,priv->CurrentChannel); | ||
1813 | #endif | ||
1814 | //#ifdef RTL8192U | ||
1815 | rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); | ||
1816 | //#endif | ||
1817 | |||
1818 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | ||
1819 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON | ||
1820 | break; | ||
1821 | default: | ||
1822 | RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); | ||
1823 | break; | ||
1824 | } | ||
1825 | } | ||
1826 | |||