diff options
author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-12-11 15:23:14 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-12-11 15:23:14 -0500 |
commit | 52b81c89e564cdde8f2b4ccd0e314f04f8f23ab9 (patch) | |
tree | a748b608d37aed19749ab3b815b03e4806fed561 /drivers/staging/rt2860/rtmp_chip.h | |
parent | 0f65bec15b2184dcf98dbdbf03187057de842eb5 (diff) |
Staging: rt28x0: run *.h files through Lindent
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rt2860/rtmp_chip.h')
-rw-r--r-- | drivers/staging/rt2860/rtmp_chip.h | 164 |
1 files changed, 79 insertions, 85 deletions
diff --git a/drivers/staging/rt2860/rtmp_chip.h b/drivers/staging/rt2860/rtmp_chip.h index 1098a8547d9..7fa73e65b29 100644 --- a/drivers/staging/rt2860/rtmp_chip.h +++ b/drivers/staging/rt2860/rtmp_chip.h | |||
@@ -73,7 +73,7 @@ | |||
73 | #define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27)) | 73 | #define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27)) |
74 | 74 | ||
75 | #define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd)) | 75 | #define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd)) |
76 | //#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200) | 76 | //#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200) |
77 | 77 | ||
78 | /* RT3572, 3592, 3562, 3062 share the same MAC version */ | 78 | /* RT3572, 3592, 3562, 3062 share the same MAC version */ |
79 | #define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000) | 79 | #define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000) |
@@ -103,15 +103,12 @@ | |||
103 | 103 | ||
104 | #define RETRY_LIMIT 10 | 104 | #define RETRY_LIMIT 10 |
105 | 105 | ||
106 | |||
107 | |||
108 | // ------------------------------------------------------ | 106 | // ------------------------------------------------------ |
109 | // BBP & RF definition | 107 | // BBP & RF definition |
110 | // ------------------------------------------------------ | 108 | // ------------------------------------------------------ |
111 | #define BUSY 1 | 109 | #define BUSY 1 |
112 | #define IDLE 0 | 110 | #define IDLE 0 |
113 | 111 | ||
114 | |||
115 | //------------------------------------------------------------------------- | 112 | //------------------------------------------------------------------------- |
116 | // EEPROM definition | 113 | // EEPROM definition |
117 | //------------------------------------------------------------------------- | 114 | //------------------------------------------------------------------------- |
@@ -126,11 +123,11 @@ | |||
126 | #define EEPROM_EWDS_OPCODE 0x10 | 123 | #define EEPROM_EWDS_OPCODE 0x10 |
127 | #define EEPROM_EWEN_OPCODE 0x13 | 124 | #define EEPROM_EWEN_OPCODE 0x13 |
128 | 125 | ||
129 | #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs | 126 | #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs |
130 | #define NUM_EEPROM_TX_G_PARMS 7 | 127 | #define NUM_EEPROM_TX_G_PARMS 7 |
131 | #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID | 128 | #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID |
132 | #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID | 129 | #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID |
133 | #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID | 130 | #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID |
134 | #define EEPROM_G_TX_PWR_OFFSET 0x52 | 131 | #define EEPROM_G_TX_PWR_OFFSET 0x52 |
135 | #define EEPROM_G_TX2_PWR_OFFSET 0x60 | 132 | #define EEPROM_G_TX2_PWR_OFFSET 0x60 |
136 | #define EEPROM_LED1_OFFSET 0x3c | 133 | #define EEPROM_LED1_OFFSET 0x3c |
@@ -150,24 +147,22 @@ | |||
150 | #define EEPROM_A_TX2_PWR_OFFSET 0xa6 | 147 | #define EEPROM_A_TX2_PWR_OFFSET 0xa6 |
151 | //#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j | 148 | //#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j |
152 | //#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe | 149 | //#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe |
153 | //#define EEPROM_TSSI_REF_OFFSET 0x54 | 150 | //#define EEPROM_TSSI_REF_OFFSET 0x54 |
154 | //#define EEPROM_TSSI_DELTA_OFFSET 0x24 | 151 | //#define EEPROM_TSSI_DELTA_OFFSET 0x24 |
155 | //#define EEPROM_CCK_TX_PWR_OFFSET 0x62 | 152 | //#define EEPROM_CCK_TX_PWR_OFFSET 0x62 |
156 | //#define EEPROM_CALIBRATE_OFFSET 0x7c | 153 | //#define EEPROM_CALIBRATE_OFFSET 0x7c |
157 | #define EEPROM_VERSION_OFFSET 0x02 | 154 | #define EEPROM_VERSION_OFFSET 0x02 |
158 | #define EEPROM_FREQ_OFFSET 0x3a | 155 | #define EEPROM_FREQ_OFFSET 0x3a |
159 | #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power. | 156 | #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power. |
160 | #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ. | 157 | #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ. |
161 | #define VALID_EEPROM_VERSION 1 | 158 | #define VALID_EEPROM_VERSION 1 |
162 | 159 | ||
163 | |||
164 | /* | 160 | /* |
165 | * EEPROM operation related marcos | 161 | * EEPROM operation related marcos |
166 | */ | 162 | */ |
167 | #define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \ | 163 | #define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \ |
168 | (_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value)) | 164 | (_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value)) |
169 | 165 | ||
170 | |||
171 | // ------------------------------------------------------------------- | 166 | // ------------------------------------------------------------------- |
172 | // E2PROM data layout | 167 | // E2PROM data layout |
173 | // ------------------------------------------------------------------- | 168 | // ------------------------------------------------------------------- |
@@ -175,90 +170,89 @@ | |||
175 | // | 170 | // |
176 | // MCU_LEDCS: MCU LED Control Setting. | 171 | // MCU_LEDCS: MCU LED Control Setting. |
177 | // | 172 | // |
178 | typedef union _MCU_LEDCS_STRUC { | 173 | typedef union _MCU_LEDCS_STRUC { |
179 | struct { | 174 | struct { |
180 | UCHAR LedMode:7; | 175 | UCHAR LedMode:7; |
181 | UCHAR Polarity:1; | 176 | UCHAR Polarity:1; |
182 | } field; | 177 | } field; |
183 | UCHAR word; | 178 | UCHAR word; |
184 | } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC; | 179 | } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC; |
185 | 180 | ||
186 | |||
187 | // | 181 | // |
188 | // EEPROM antenna select format | 182 | // EEPROM antenna select format |
189 | // | 183 | // |
190 | typedef union _EEPROM_ANTENNA_STRUC { | 184 | typedef union _EEPROM_ANTENNA_STRUC { |
191 | struct { | 185 | struct { |
192 | USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R | 186 | USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R |
193 | USHORT TxPath:4; // 1: 1T, 2: 2T | 187 | USHORT TxPath:4; // 1: 1T, 2: 2T |
194 | USHORT RfIcType:4; // see E2PROM document | 188 | USHORT RfIcType:4; // see E2PROM document |
195 | USHORT Rsv:4; | 189 | USHORT Rsv:4; |
196 | } field; | 190 | } field; |
197 | USHORT word; | 191 | USHORT word; |
198 | } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC; | 192 | } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC; |
199 | 193 | ||
200 | typedef union _EEPROM_NIC_CINFIG2_STRUC { | 194 | typedef union _EEPROM_NIC_CINFIG2_STRUC { |
201 | struct { | 195 | struct { |
202 | USHORT HardwareRadioControl:1; // 1:enable, 0:disable | 196 | USHORT HardwareRadioControl:1; // 1:enable, 0:disable |
203 | USHORT DynamicTxAgcControl:1; // | 197 | USHORT DynamicTxAgcControl:1; // |
204 | USHORT ExternalLNAForG:1; // | 198 | USHORT ExternalLNAForG:1; // |
205 | USHORT ExternalLNAForA:1; // external LNA enable for 2.4G | 199 | USHORT ExternalLNAForA:1; // external LNA enable for 2.4G |
206 | USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable | 200 | USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable |
207 | USHORT BW40MSidebandForG:1; | 201 | USHORT BW40MSidebandForG:1; |
208 | USHORT BW40MSidebandForA:1; | 202 | USHORT BW40MSidebandForA:1; |
209 | USHORT EnableWPSPBC:1; // WPS PBC Control bit | 203 | USHORT EnableWPSPBC:1; // WPS PBC Control bit |
210 | USHORT BW40MAvailForG:1; // 0:enable, 1:disable | 204 | USHORT BW40MAvailForG:1; // 0:enable, 1:disable |
211 | USHORT BW40MAvailForA:1; // 0:enable, 1:disable | 205 | USHORT BW40MAvailForA:1; // 0:enable, 1:disable |
212 | USHORT Rsv1:1; // must be 0 | 206 | USHORT Rsv1:1; // must be 0 |
213 | USHORT AntDiversity:1; // Antenna diversity | 207 | USHORT AntDiversity:1; // Antenna diversity |
214 | USHORT Rsv2:3; // must be 0 | 208 | USHORT Rsv2:3; // must be 0 |
215 | USHORT DACTestBit:1; // control if driver should patch the DAC issue | 209 | USHORT DACTestBit:1; // control if driver should patch the DAC issue |
216 | } field; | 210 | } field; |
217 | USHORT word; | 211 | USHORT word; |
218 | } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC; | 212 | } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC; |
219 | 213 | ||
220 | // | 214 | // |
221 | // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36) | 215 | // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36) |
222 | // | 216 | // |
223 | typedef union _EEPROM_TX_PWR_STRUC { | 217 | typedef union _EEPROM_TX_PWR_STRUC { |
224 | struct { | 218 | struct { |
225 | CHAR Byte0; // Low Byte | 219 | CHAR Byte0; // Low Byte |
226 | CHAR Byte1; // High Byte | 220 | CHAR Byte1; // High Byte |
227 | } field; | 221 | } field; |
228 | USHORT word; | 222 | USHORT word; |
229 | } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC; | 223 | } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC; |
230 | 224 | ||
231 | typedef union _EEPROM_VERSION_STRUC { | 225 | typedef union _EEPROM_VERSION_STRUC { |
232 | struct { | 226 | struct { |
233 | UCHAR FaeReleaseNumber; // Low Byte | 227 | UCHAR FaeReleaseNumber; // Low Byte |
234 | UCHAR Version; // High Byte | 228 | UCHAR Version; // High Byte |
235 | } field; | 229 | } field; |
236 | USHORT word; | 230 | USHORT word; |
237 | } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC; | 231 | } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC; |
238 | 232 | ||
239 | typedef union _EEPROM_LED_STRUC { | 233 | typedef union _EEPROM_LED_STRUC { |
240 | struct { | 234 | struct { |
241 | USHORT PolarityRDY_G:1; // Polarity RDY_G setting. | 235 | USHORT PolarityRDY_G:1; // Polarity RDY_G setting. |
242 | USHORT PolarityRDY_A:1; // Polarity RDY_A setting. | 236 | USHORT PolarityRDY_A:1; // Polarity RDY_A setting. |
243 | USHORT PolarityACT:1; // Polarity ACT setting. | 237 | USHORT PolarityACT:1; // Polarity ACT setting. |
244 | USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting. | 238 | USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting. |
245 | USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting. | 239 | USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting. |
246 | USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting. | 240 | USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting. |
247 | USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting. | 241 | USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting. |
248 | USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting. | 242 | USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting. |
249 | USHORT LedMode:5; // Led mode. | 243 | USHORT LedMode:5; // Led mode. |
250 | USHORT Rsvd:3; // Reserved | 244 | USHORT Rsvd:3; // Reserved |
251 | } field; | 245 | } field; |
252 | USHORT word; | 246 | USHORT word; |
253 | } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC; | 247 | } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC; |
254 | 248 | ||
255 | typedef union _EEPROM_TXPOWER_DELTA_STRUC { | 249 | typedef union _EEPROM_TXPOWER_DELTA_STRUC { |
256 | struct { | 250 | struct { |
257 | UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4) | 251 | UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4) |
258 | UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value | 252 | UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value |
259 | UCHAR TxPowerEnable:1;// Enable | 253 | UCHAR TxPowerEnable:1; // Enable |
260 | } field; | 254 | } field; |
261 | UCHAR value; | 255 | UCHAR value; |
262 | } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC; | 256 | } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC; |
263 | 257 | ||
264 | #endif // __RTMP_CHIP_H__ // | 258 | #endif // __RTMP_CHIP_H__ // |