Added missing tegra files.HEADmaster

3 files changed, 3746 insertions, 0 deletions

diff --git a/drivers/spi/spi-stmp.c b/drivers/spi/spi-stmp.c
new file mode 100644
index 00000000000..fadff76eb7e
--- /dev/null
+++ b/drivers/spi/spi-stmp.c
@@ -0,0 +1,679 @@
+/*
+ * Freescale STMP378X SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+
+#include <mach/platform.h>
+#include <mach/stmp3xxx.h>
+#include <mach/dma.h>
+#include <mach/regs-ssp.h>
+#include <mach/regs-apbh.h>
+
+
+/* 0 means DMA mode(recommended, default), !0 - PIO mode */
+static int pio;
+static int clock;
+
+/* default timeout for busy waits is 2 seconds */
+#define STMP_SPI_TIMEOUT        (2 * HZ)
+
+struct stmp_spi {
+        int             id;
+
+        void *  __iomem regs;   /* vaddr of the control registers */
+
+        int             irq, err_irq;
+        u32             dma;
+        struct stmp3xxx_dma_descriptor d;
+
+        u32             speed_khz;
+        u32             saved_timings;
+        u32             divider;
+
+        struct clk      *clk;
+        struct device   *master_dev;
+
+        struct work_struct work;
+        struct workqueue_struct *workqueue;
+
+        /* lock protects queue access */
+        spinlock_t lock;
+        struct list_head queue;
+
+        struct completion done;
+};
+
+#define busy_wait(cond)                                                 \
+        ({                                                              \
+        unsigned long end_jiffies = jiffies + STMP_SPI_TIMEOUT;         \
+        bool succeeded = false;                                         \
+        do {                                                            \
+                if (cond) {                                             \
+                        succeeded = true;                               \
+                        break;                                          \
+                }                                                       \
+                cpu_relax();                                            \
+        } while (time_before(jiffies, end_jiffies));                    \
+        succeeded;                                                      \
+        })
+
+/**
+ * stmp_spi_init_hw
+ * Initialize the SSP port
+ */
+static int stmp_spi_init_hw(struct stmp_spi *ss)
+{
+        int err = 0;
+        void *pins = ss->master_dev->platform_data;
+
+        err = stmp3xxx_request_pin_group(pins, dev_name(ss->master_dev));
+        if (err)
+                goto out;
+
+        ss->clk = clk_get(NULL, "ssp");
+        if (IS_ERR(ss->clk)) {
+                err = PTR_ERR(ss->clk);
+                goto out_free_pins;
+        }
+        clk_enable(ss->clk);
+
+        stmp3xxx_reset_block(ss->regs, false);
+        stmp3xxx_dma_reset_channel(ss->dma);
+
+        return 0;
+
+out_free_pins:
+        stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
+out:
+        return err;
+}
+
+static void stmp_spi_release_hw(struct stmp_spi *ss)
+{
+        void *pins = ss->master_dev->platform_data;
+
+        if (ss->clk && !IS_ERR(ss->clk)) {
+                clk_disable(ss->clk);
+                clk_put(ss->clk);
+        }
+        stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
+}
+
+static int stmp_spi_setup_transfer(struct spi_device *spi,
+                struct spi_transfer *t)
+{
+        u8 bits_per_word;
+        u32 hz;
+        struct stmp_spi *ss = spi_master_get_devdata(spi->master);
+        u16 rate;
+
+        bits_per_word = spi->bits_per_word;
+        if (t && t->bits_per_word)
+                bits_per_word = t->bits_per_word;
+
+        /*
+         * Calculate speed:
+         *      - by default, use maximum speed from ssp clk
+         *      - if device overrides it, use it
+         *      - if transfer specifies other speed, use transfer's one
+         */
+        hz = 1000 * ss->speed_khz / ss->divider;
+        if (spi->max_speed_hz)
+                hz = min(hz, spi->max_speed_hz);
+        if (t && t->speed_hz)
+                hz = min(hz, t->speed_hz);
+
+        if (hz == 0) {
+                dev_err(&spi->dev, "Cannot continue with zero clock\n");
+                return -EINVAL;
+        }
+
+        if (bits_per_word != 8) {
+                dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+                        __func__, bits_per_word);
+                return -EINVAL;
+        }
+
+        dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %uHz/%d = %uHz\n",
+                hz, ss->speed_khz, ss->divider,
+                ss->speed_khz * 1000 / ss->divider);
+
+        if (ss->speed_khz * 1000 / ss->divider < hz) {
+                dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
+                        __func__, hz);
+                return -EINVAL;
+        }
+
+        rate = 1000 * ss->speed_khz/ss->divider/hz;
+
+        writel(BF(ss->divider, SSP_TIMING_CLOCK_DIVIDE)         |
+               BF(rate - 1, SSP_TIMING_CLOCK_RATE),
+               HW_SSP_TIMING + ss->regs);
+
+        writel(BF(1 /* mode SPI */, SSP_CTRL1_SSP_MODE)         |
+               BF(4 /* 8 bits   */, SSP_CTRL1_WORD_LENGTH)      |
+               ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+               ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
+               (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE),
+               ss->regs + HW_SSP_CTRL1);
+
+        return 0;
+}
+
+static int stmp_spi_setup(struct spi_device *spi)
+{
+        /* spi_setup() does basic checks,
+         * stmp_spi_setup_transfer() does more later
+         */
+        if (spi->bits_per_word != 8) {
+                dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+                        __func__, spi->bits_per_word);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static inline u32 stmp_spi_cs(unsigned cs)
+{
+        return  ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
+                ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
+}
+
+static int stmp_spi_txrx_dma(struct stmp_spi *ss, int cs,
+                unsigned char *buf, dma_addr_t dma_buf, int len,
+                int first, int last, bool write)
+{
+        u32 c0 = 0;
+        dma_addr_t spi_buf_dma = dma_buf;
+        int status = 0;
+        enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+        c0 |= (first ? BM_SSP_CTRL0_LOCK_CS : 0);
+        c0 |= (last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
+        c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
+        c0 |= BM_SSP_CTRL0_DATA_XFER;