diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
commit | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch) | |
tree | a8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/spi | |
parent | 406089d01562f1e2bf9f089fd7637009ebaad589 (diff) |
Patched in Tegra support.
Diffstat (limited to 'drivers/spi')
61 files changed, 2427 insertions, 10261 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2e188e1127e..8f7ee0e1ee4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
@@ -74,7 +74,7 @@ config SPI_ATMEL | |||
74 | This selects a driver for the Atmel SPI Controller, present on | 74 | This selects a driver for the Atmel SPI Controller, present on |
75 | many AT32 (AVR32) and AT91 (ARM) chips. | 75 | many AT32 (AVR32) and AT91 (ARM) chips. |
76 | 76 | ||
77 | config SPI_BFIN5XX | 77 | config SPI_BFIN |
78 | tristate "SPI controller driver for ADI Blackfin5xx" | 78 | tristate "SPI controller driver for ADI Blackfin5xx" |
79 | depends on BLACKFIN | 79 | depends on BLACKFIN |
80 | help | 80 | help |
@@ -87,18 +87,12 @@ config SPI_BFIN_SPORT | |||
87 | Enable support for a SPI bus via the Blackfin SPORT peripheral. | 87 | Enable support for a SPI bus via the Blackfin SPORT peripheral. |
88 | 88 | ||
89 | config SPI_AU1550 | 89 | config SPI_AU1550 |
90 | tristate "Au1550/Au1200/Au1300 SPI Controller" | 90 | tristate "Au1550/Au12x0 SPI Controller" |
91 | depends on MIPS_ALCHEMY && EXPERIMENTAL | 91 | depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL |
92 | select SPI_BITBANG | 92 | select SPI_BITBANG |
93 | help | 93 | help |
94 | If you say yes to this option, support will be included for the | 94 | If you say yes to this option, support will be included for the |
95 | PSC SPI controller found on Au1550, Au1200 and Au1300 series. | 95 | Au1550 SPI controller (may also work with Au1200,Au1210,Au1250). |
96 | |||
97 | config SPI_BCM63XX | ||
98 | tristate "Broadcom BCM63xx SPI controller" | ||
99 | depends on BCM63XX | ||
100 | help | ||
101 | Enable support for the SPI controller on the Broadcom BCM63xx SoCs. | ||
102 | 96 | ||
103 | config SPI_BITBANG | 97 | config SPI_BITBANG |
104 | tristate "Utilities for Bitbanging SPI masters" | 98 | tristate "Utilities for Bitbanging SPI masters" |
@@ -123,25 +117,17 @@ config SPI_BUTTERFLY | |||
123 | inexpensive battery powered microcontroller evaluation board. | 117 | inexpensive battery powered microcontroller evaluation board. |
124 | This same cable can be used to flash new firmware. | 118 | This same cable can be used to flash new firmware. |
125 | 119 | ||
126 | config SPI_CLPS711X | ||
127 | tristate "CLPS711X host SPI controller" | ||
128 | depends on ARCH_CLPS711X | ||
129 | help | ||
130 | This enables dedicated general purpose SPI/Microwire1-compatible | ||
131 | master mode interface (SSI1) for CLPS711X-based CPUs. | ||
132 | |||
133 | config SPI_COLDFIRE_QSPI | 120 | config SPI_COLDFIRE_QSPI |
134 | tristate "Freescale Coldfire QSPI controller" | 121 | tristate "Freescale Coldfire QSPI controller" |
135 | depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) | 122 | depends on (M520x || M523x || M5249 || M527x || M528x || M532x) |
136 | help | 123 | help |
137 | This enables support for the Coldfire QSPI controller in master | 124 | This enables support for the Coldfire QSPI controller in master |
138 | mode. | 125 | mode. |
139 | 126 | ||
140 | config SPI_DAVINCI | 127 | config SPI_DAVINCI |
141 | tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller" | 128 | tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller" |
142 | depends on ARCH_DAVINCI | 129 | depends on SPI_MASTER && ARCH_DAVINCI |
143 | select SPI_BITBANG | 130 | select SPI_BITBANG |
144 | select TI_EDMA | ||
145 | help | 131 | help |
146 | SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. | 132 | SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. |
147 | 133 | ||
@@ -152,15 +138,6 @@ config SPI_EP93XX | |||
152 | This enables using the Cirrus EP93xx SPI controller in master | 138 | This enables using the Cirrus EP93xx SPI controller in master |
153 | mode. | 139 | mode. |
154 | 140 | ||
155 | config SPI_FALCON | ||
156 | tristate "Falcon SPI controller support" | ||
157 | depends on SOC_FALCON | ||
158 | help | ||
159 | The external bus unit (EBU) found on the FALC-ON SoC has SPI | ||
160 | emulation that is designed for serial flash access. This driver | ||
161 | has only been tested with m25p80 type chips. The hardware has no | ||
162 | support for other types of SPI peripherals. | ||
163 | |||
164 | config SPI_GPIO | 141 | config SPI_GPIO |
165 | tristate "GPIO-based bitbanging SPI Master" | 142 | tristate "GPIO-based bitbanging SPI Master" |
166 | depends on GENERIC_GPIO | 143 | depends on GENERIC_GPIO |
@@ -197,7 +174,8 @@ config SPI_LM70_LLP | |||
197 | 174 | ||
198 | config SPI_MPC52xx | 175 | config SPI_MPC52xx |
199 | tristate "Freescale MPC52xx SPI (non-PSC) controller support" | 176 | tristate "Freescale MPC52xx SPI (non-PSC) controller support" |
200 | depends on PPC_MPC52xx | 177 | depends on PPC_MPC52xx && SPI |
178 | select SPI_MASTER_OF | ||
201 | help | 179 | help |
202 | This drivers supports the MPC52xx SPI controller in master SPI | 180 | This drivers supports the MPC52xx SPI controller in master SPI |
203 | mode. | 181 | mode. |
@@ -211,7 +189,7 @@ config SPI_MPC52xx_PSC | |||
211 | 189 | ||
212 | config SPI_MPC512x_PSC | 190 | config SPI_MPC512x_PSC |
213 | tristate "Freescale MPC512x PSC SPI controller" | 191 | tristate "Freescale MPC512x PSC SPI controller" |
214 | depends on PPC_MPC512x | 192 | depends on SPI_MASTER && PPC_MPC512x |
215 | help | 193 | help |
216 | This enables using the Freescale MPC5121 Programmable Serial | 194 | This enables using the Freescale MPC5121 Programmable Serial |
217 | Controller in SPI master mode. | 195 | Controller in SPI master mode. |
@@ -221,7 +199,7 @@ config SPI_FSL_LIB | |||
221 | depends on FSL_SOC | 199 | depends on FSL_SOC |
222 | 200 | ||
223 | config SPI_FSL_SPI | 201 | config SPI_FSL_SPI |
224 | bool "Freescale SPI controller" | 202 | tristate "Freescale SPI controller" |
225 | depends on FSL_SOC | 203 | depends on FSL_SOC |
226 | select SPI_FSL_LIB | 204 | select SPI_FSL_LIB |
227 | help | 205 | help |
@@ -230,7 +208,7 @@ config SPI_FSL_SPI | |||
230 | MPC8569 uses the controller in QE mode, MPC8610 in cpu mode. | 208 | MPC8569 uses the controller in QE mode, MPC8610 in cpu mode. |
231 | 209 | ||
232 | config SPI_FSL_ESPI | 210 | config SPI_FSL_ESPI |
233 | bool "Freescale eSPI controller" | 211 | tristate "Freescale eSPI controller" |
234 | depends on FSL_SOC | 212 | depends on FSL_SOC |
235 | select SPI_FSL_LIB | 213 | select SPI_FSL_LIB |
236 | help | 214 | help |
@@ -245,13 +223,6 @@ config SPI_OC_TINY | |||
245 | help | 223 | help |
246 | This is the driver for OpenCores tiny SPI master controller. | 224 | This is the driver for OpenCores tiny SPI master controller. |
247 | 225 | ||
248 | config SPI_OCTEON | ||
249 | tristate "Cavium OCTEON SPI controller" | ||
250 | depends on CPU_CAVIUM_OCTEON | ||
251 | help | ||
252 | SPI host driver for the hardware found on some Cavium OCTEON | ||
253 | SOCs. | ||
254 | |||
255 | config SPI_OMAP_UWIRE | 226 | config SPI_OMAP_UWIRE |
256 | tristate "OMAP1 MicroWire" | 227 | tristate "OMAP1 MicroWire" |
257 | depends on ARCH_OMAP1 | 228 | depends on ARCH_OMAP1 |
@@ -268,7 +239,7 @@ config SPI_OMAP24XX | |||
268 | 239 | ||
269 | config SPI_OMAP_100K | 240 | config SPI_OMAP_100K |
270 | tristate "OMAP SPI 100K" | 241 | tristate "OMAP SPI 100K" |
271 | depends on ARCH_OMAP850 || ARCH_OMAP730 | 242 | depends on SPI_MASTER && (ARCH_OMAP850 || ARCH_OMAP730) |
272 | help | 243 | help |
273 | OMAP SPI 100K master controller for omap7xx boards. | 244 | OMAP SPI 100K master controller for omap7xx boards. |
274 | 245 | ||
@@ -292,7 +263,7 @@ config SPI_PL022 | |||
292 | 263 | ||
293 | config SPI_PPC4xx | 264 | config SPI_PPC4xx |
294 | tristate "PPC4xx SPI Controller" | 265 | tristate "PPC4xx SPI Controller" |
295 | depends on PPC32 && 4xx | 266 | depends on PPC32 && 4xx && SPI_MASTER |
296 | select SPI_BITBANG | 267 | select SPI_BITBANG |
297 | help | 268 | help |
298 | This selects a driver for the PPC4xx SPI Controller. | 269 | This selects a driver for the PPC4xx SPI Controller. |
@@ -309,15 +280,9 @@ config SPI_PXA2XX | |||
309 | config SPI_PXA2XX_PCI | 280 | config SPI_PXA2XX_PCI |
310 | def_bool SPI_PXA2XX && X86_32 && PCI | 281 | def_bool SPI_PXA2XX && X86_32 && PCI |
311 | 282 | ||
312 | config SPI_RSPI | ||
313 | tristate "Renesas RSPI controller" | ||
314 | depends on SUPERH | ||
315 | help | ||
316 | SPI driver for Renesas RSPI blocks. | ||
317 | |||
318 | config SPI_S3C24XX | 283 | config SPI_S3C24XX |
319 | tristate "Samsung S3C24XX series SPI" | 284 | tristate "Samsung S3C24XX series SPI" |
320 | depends on ARCH_S3C24XX && EXPERIMENTAL | 285 | depends on ARCH_S3C2410 && EXPERIMENTAL |
321 | select SPI_BITBANG | 286 | select SPI_BITBANG |
322 | help | 287 | help |
323 | SPI driver for Samsung S3C24XX series ARM SoCs | 288 | SPI driver for Samsung S3C24XX series ARM SoCs |
@@ -335,23 +300,17 @@ config SPI_S3C24XX_FIQ | |||
335 | 300 | ||
336 | config SPI_S3C64XX | 301 | config SPI_S3C64XX |
337 | tristate "Samsung S3C64XX series type SPI" | 302 | tristate "Samsung S3C64XX series type SPI" |
338 | depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS) | 303 | depends on (ARCH_S3C64XX || ARCH_S5P64X0) |
339 | select S3C64XX_DMA if ARCH_S3C64XX | 304 | select S3C64XX_DMA if ARCH_S3C64XX |
340 | help | 305 | help |
341 | SPI driver for Samsung S3C64XX and newer SoCs. | 306 | SPI driver for Samsung S3C64XX and newer SoCs. |
342 | 307 | ||
343 | config SPI_SC18IS602 | ||
344 | tristate "NXP SC18IS602/602B/603 I2C to SPI bridge" | ||
345 | depends on I2C | ||
346 | help | ||
347 | SPI driver for NXP SC18IS602/602B/603 I2C to SPI bridge. | ||
348 | |||
349 | config SPI_SH_MSIOF | 308 | config SPI_SH_MSIOF |
350 | tristate "SuperH MSIOF SPI controller" | 309 | tristate "SuperH MSIOF SPI controller" |
351 | depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK | 310 | depends on SUPERH && HAVE_CLK |
352 | select SPI_BITBANG | 311 | select SPI_BITBANG |
353 | help | 312 | help |
354 | SPI driver for SuperH and SH Mobile MSIOF blocks. | 313 | SPI driver for SuperH MSIOF blocks. |
355 | 314 | ||
356 | config SPI_SH | 315 | config SPI_SH |
357 | tristate "SuperH SPI controller" | 316 | tristate "SuperH SPI controller" |
@@ -366,39 +325,28 @@ config SPI_SH_SCI | |||
366 | help | 325 | help |
367 | SPI driver for SuperH SCI blocks. | 326 | SPI driver for SuperH SCI blocks. |
368 | 327 | ||
369 | config SPI_SH_HSPI | 328 | config SPI_STMP3XXX |
370 | tristate "SuperH HSPI controller" | 329 | tristate "Freescale STMP37xx/378x SPI/SSP controller" |
371 | depends on ARCH_SHMOBILE | 330 | depends on ARCH_STMP3XXX && SPI_MASTER |
372 | help | ||
373 | SPI driver for SuperH HSPI blocks. | ||
374 | |||
375 | config SPI_SIRF | ||
376 | tristate "CSR SiRFprimaII SPI controller" | ||
377 | depends on ARCH_PRIMA2 | ||
378 | select SPI_BITBANG | ||
379 | help | ||
380 | SPI driver for CSR SiRFprimaII SoCs | ||
381 | |||
382 | config SPI_MXS | ||
383 | tristate "Freescale MXS SPI controller" | ||
384 | depends on ARCH_MXS | ||
385 | select STMP_DEVICE | ||
386 | help | 331 | help |
387 | SPI driver for Freescale MXS devices. | 332 | SPI driver for Freescale STMP37xx/378x SoC SSP interface |
388 | 333 | ||
389 | config SPI_TEGRA20_SFLASH | 334 | config SPI_TEGRA |
390 | tristate "Nvidia Tegra20 Serial flash Controller" | 335 | tristate "Nvidia Tegra SPI controller" |
391 | depends on ARCH_TEGRA | 336 | depends on ARCH_TEGRA |
337 | select TEGRA_SYSTEM_DMA | ||
392 | help | 338 | help |
393 | SPI driver for Nvidia Tegra20 Serial flash Controller interface. | 339 | SPI driver for NVidia Tegra SoCs |
394 | The main usecase of this controller is to use spi flash as boot | ||
395 | device. | ||
396 | 340 | ||
397 | config SPI_TEGRA20_SLINK | 341 | config SPI_SLAVE_TEGRA |
398 | tristate "Nvidia Tegra20/Tegra30 SLINK Controller" | 342 | tristate "Nvidia Tegra SPI slave controller" |
399 | depends on ARCH_TEGRA && TEGRA20_APB_DMA | 343 | depends on ARCH_TEGRA |
344 | select TEGRA_SYSTEM_DMA | ||
345 | default n | ||
400 | help | 346 | help |
401 | SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. | 347 | SPI Slave driver for NVidia Tegra SoCs. |
348 | Say yes if slave spi functionality is required from the tegra spi controller. | ||
349 | The interface is same as the master spi. | ||
402 | 350 | ||
403 | config SPI_TI_SSP | 351 | config SPI_TI_SSP |
404 | tristate "TI Sequencer Serial Port - SPI Support" | 352 | tristate "TI Sequencer Serial Port - SPI Support" |
@@ -408,14 +356,14 @@ config SPI_TI_SSP | |||
408 | serial port. | 356 | serial port. |
409 | 357 | ||
410 | config SPI_TOPCLIFF_PCH | 358 | config SPI_TOPCLIFF_PCH |
411 | tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" | 359 | tristate "Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI controller" |
412 | depends on PCI | 360 | depends on PCI |
413 | help | 361 | help |
414 | SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus | 362 | SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus |
415 | used in some x86 embedded processors. | 363 | used in some x86 embedded processors. |
416 | 364 | ||
417 | This driver also supports the ML7213/ML7223/ML7831, a companion chip | 365 | This driver also supports the ML7213, a companion chip for the |
418 | for the Atom E6xx series and compatible with the Intel EG20T PCH. | 366 | Atom E6xx series and compatible with the Intel EG20T PCH. |
419 | 367 | ||
420 | config SPI_TXX9 | 368 | config SPI_TXX9 |
421 | tristate "Toshiba TXx9 SPI controller" | 369 | tristate "Toshiba TXx9 SPI controller" |
@@ -423,13 +371,6 @@ config SPI_TXX9 | |||
423 | help | 371 | help |
424 | SPI driver for Toshiba TXx9 MIPS SoCs | 372 | SPI driver for Toshiba TXx9 MIPS SoCs |
425 | 373 | ||
426 | config SPI_XCOMM | ||
427 | tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver" | ||
428 | depends on I2C | ||
429 | help | ||
430 | Support for the SPI-I2C bridge found on the Analog Devices | ||
431 | AD-FMCOMMS1-EBZ board. | ||
432 | |||
433 | config SPI_XILINX | 374 | config SPI_XILINX |
434 | tristate "Xilinx SPI controller common module" | 375 | tristate "Xilinx SPI controller common module" |
435 | depends on HAS_IOMEM && EXPERIMENTAL | 376 | depends on HAS_IOMEM && EXPERIMENTAL |
@@ -455,6 +396,7 @@ config SPI_NUC900 | |||
455 | 396 | ||
456 | config SPI_DESIGNWARE | 397 | config SPI_DESIGNWARE |
457 | tristate "DesignWare SPI controller core support" | 398 | tristate "DesignWare SPI controller core support" |
399 | depends on SPI_MASTER | ||
458 | help | 400 | help |
459 | general driver for SPI controller core from DesignWare | 401 | general driver for SPI controller core from DesignWare |
460 | 402 | ||
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64e970ba261..430f8200108 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile | |||
@@ -1,6 +1,7 @@ | |||
1 | # | 1 | # |
2 | # Makefile for kernel SPI drivers. | 2 | # Makefile for kernel SPI drivers. |
3 | # | 3 | # |
4 | GCOV_PROFILE := y | ||
4 | 5 | ||
5 | ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG | 6 | ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG |
6 | 7 | ||
@@ -14,12 +15,10 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o | |||
14 | obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o | 15 | obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o |
15 | obj-$(CONFIG_SPI_ATH79) += spi-ath79.o | 16 | obj-$(CONFIG_SPI_ATH79) += spi-ath79.o |
16 | obj-$(CONFIG_SPI_AU1550) += spi-au1550.o | 17 | obj-$(CONFIG_SPI_AU1550) += spi-au1550.o |
17 | obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o | 18 | obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o |
18 | obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o | ||
19 | obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o | 19 | obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o |
20 | obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o | 20 | obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o |
21 | obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o | 21 | obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o |
22 | obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o | ||
23 | obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o | 22 | obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o |
24 | obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o | 23 | obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o |
25 | obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o | 24 | obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o |
@@ -27,7 +26,6 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o | |||
27 | obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o | 26 | obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o |
28 | spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o | 27 | spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o |
29 | obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o | 28 | obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o |
30 | obj-$(CONFIG_SPI_FALCON) += spi-falcon.o | ||
31 | obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o | 29 | obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o |
32 | obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o | 30 | obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o |
33 | obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o | 31 | obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o |
@@ -37,10 +35,8 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o | |||
37 | obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o | 35 | obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o |
38 | obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o | 36 | obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o |
39 | obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o | 37 | obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o |
40 | obj-$(CONFIG_SPI_MXS) += spi-mxs.o | ||
41 | obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o | 38 | obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o |
42 | obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o | 39 | obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o |
43 | obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o | ||
44 | obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o | 40 | obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o |
45 | obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o | 41 | obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o |
46 | obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o | 42 | obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o |
@@ -49,22 +45,19 @@ obj-$(CONFIG_SPI_PL022) += spi-pl022.o | |||
49 | obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o | 45 | obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o |
50 | obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o | 46 | obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o |
51 | obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o | 47 | obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o |
52 | obj-$(CONFIG_SPI_RSPI) += spi-rspi.o | ||
53 | obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o | 48 | obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o |
54 | spi-s3c24xx-hw-y := spi-s3c24xx.o | 49 | spi-s3c24xx-hw-y := spi-s3c24xx.o |
55 | spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o | 50 | spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o |
56 | obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o | 51 | obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o |
57 | obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o | ||
58 | obj-$(CONFIG_SPI_SH) += spi-sh.o | 52 | obj-$(CONFIG_SPI_SH) += spi-sh.o |
59 | obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o | ||
60 | obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o | 53 | obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o |
61 | obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o | 54 | obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o |
62 | obj-$(CONFIG_SPI_SIRF) += spi-sirf.o | 55 | obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o |
63 | obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o | 56 | obj-$(CONFIG_SPI_TEGRA) += spi-tegra.o |
64 | obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o | 57 | obj-$(CONFIG_SPI_SLAVE_TEGRA) += spi_slave_tegra.o |
65 | obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o | 58 | obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o |
66 | obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o | 59 | obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o |
67 | obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o | 60 | obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o |
68 | obj-$(CONFIG_SPI_TXX9) += spi-txx9.o | 61 | obj-$(CONFIG_SPI_TXX9) += spi-txx9.o |
69 | obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o | ||
70 | obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o | 62 | obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o |
63 | |||
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c index 5e7314ac51e..4813a63ce6f 100644 --- a/drivers/spi/spi-altera.c +++ b/drivers/spi/spi-altera.c | |||
@@ -16,7 +16,6 @@ | |||
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | ||
20 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
21 | #include <linux/spi/spi.h> | 20 | #include <linux/spi/spi.h> |
22 | #include <linux/spi/spi_bitbang.h> | 21 | #include <linux/spi/spi_bitbang.h> |
@@ -215,7 +214,7 @@ static irqreturn_t altera_spi_irq(int irq, void *dev) | |||
215 | return IRQ_HANDLED; | 214 | return IRQ_HANDLED; |
216 | } | 215 | } |
217 | 216 | ||
218 | static int altera_spi_probe(struct platform_device *pdev) | 217 | static int __devinit altera_spi_probe(struct platform_device *pdev) |
219 | { | 218 | { |
220 | struct altera_spi_platform_data *platp = pdev->dev.platform_data; | 219 | struct altera_spi_platform_data *platp = pdev->dev.platform_data; |
221 | struct altera_spi *hw; | 220 | struct altera_spi *hw; |
@@ -290,7 +289,7 @@ exit: | |||
290 | return err; | 289 | return err; |
291 | } | 290 | } |
292 | 291 | ||
293 | static int altera_spi_remove(struct platform_device *dev) | 292 | static int __devexit altera_spi_remove(struct platform_device *dev) |
294 | { | 293 | { |
295 | struct altera_spi *hw = platform_get_drvdata(dev); | 294 | struct altera_spi *hw = platform_get_drvdata(dev); |
296 | struct spi_master *master = hw->bitbang.master; | 295 | struct spi_master *master = hw->bitbang.master; |
@@ -307,19 +306,32 @@ static const struct of_device_id altera_spi_match[] = { | |||
307 | {}, | 306 | {}, |
308 | }; | 307 | }; |
309 | MODULE_DEVICE_TABLE(of, altera_spi_match); | 308 | MODULE_DEVICE_TABLE(of, altera_spi_match); |
309 | #else /* CONFIG_OF */ | ||
310 | #define altera_spi_match NULL | ||
310 | #endif /* CONFIG_OF */ | 311 | #endif /* CONFIG_OF */ |
311 | 312 | ||
312 | static struct platform_driver altera_spi_driver = { | 313 | static struct platform_driver altera_spi_driver = { |
313 | .probe = altera_spi_probe, | 314 | .probe = altera_spi_probe, |
314 | .remove = altera_spi_remove, | 315 | .remove = __devexit_p(altera_spi_remove), |
315 | .driver = { | 316 | .driver = { |
316 | .name = DRV_NAME, | 317 | .name = DRV_NAME, |
317 | .owner = THIS_MODULE, | 318 | .owner = THIS_MODULE, |
318 | .pm = NULL, | 319 | .pm = NULL, |
319 | .of_match_table = of_match_ptr(altera_spi_match), | 320 | .of_match_table = altera_spi_match, |
320 | }, | 321 | }, |
321 | }; | 322 | }; |
322 | module_platform_driver(altera_spi_driver); | 323 | |
324 | static int __init altera_spi_init(void) | ||
325 | { | ||
326 | return platform_driver_register(&altera_spi_driver); | ||
327 | } | ||
328 | module_init(altera_spi_init); | ||
329 | |||
330 | static void __exit altera_spi_exit(void) | ||
331 | { | ||
332 | platform_driver_unregister(&altera_spi_driver); | ||
333 | } | ||
334 | module_exit(altera_spi_exit); | ||
323 | 335 | ||
324 | MODULE_DESCRIPTION("Altera SPI driver"); | 336 | MODULE_DESCRIPTION("Altera SPI driver"); |
325 | MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); | 337 | MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); |
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c index 9a5d7791c5f..03019bf5a5e 100644 --- a/drivers/spi/spi-ath79.c +++ b/drivers/spi/spi-ath79.c | |||
@@ -13,7 +13,6 @@ | |||
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> | ||
17 | #include <linux/init.h> | 16 | #include <linux/init.h> |
18 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
19 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
@@ -192,7 +191,7 @@ static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, | |||
192 | return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); | 191 | return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); |
193 | } | 192 | } |
194 | 193 | ||
195 | static int ath79_spi_probe(struct platform_device *pdev) | 194 | static __devinit int ath79_spi_probe(struct platform_device *pdev) |
196 | { | 195 | { |
197 | struct spi_master *master; | 196 | struct spi_master *master; |
198 | struct ath79_spi *sp; | 197 | struct ath79_spi *sp; |
@@ -216,6 +215,9 @@ static int ath79_spi_probe(struct platform_device *pdev) | |||
216 | if (pdata) { | 215 | if (pdata) { |
217 | master->bus_num = pdata->bus_num; | 216 | master->bus_num = pdata->bus_num; |
218 | master->num_chipselect = pdata->num_chipselect; | 217 | master->num_chipselect = pdata->num_chipselect; |
218 | } else { | ||
219 | master->bus_num = -1; | ||
220 | master->num_chipselect = 1; | ||
219 | } | 221 | } |
220 | 222 | ||
221 | sp->bitbang.master = spi_master_get(master); | 223 | sp->bitbang.master = spi_master_get(master); |
@@ -251,7 +253,7 @@ err_put_master: | |||
251 | return ret; | 253 | return ret; |
252 | } | 254 | } |
253 | 255 | ||
254 | static int ath79_spi_remove(struct platform_device *pdev) | 256 | static __devexit int ath79_spi_remove(struct platform_device *pdev) |
255 | { | 257 | { |
256 | struct ath79_spi *sp = platform_get_drvdata(pdev); | 258 | struct ath79_spi *sp = platform_get_drvdata(pdev); |
257 | 259 | ||
@@ -265,13 +267,24 @@ static int ath79_spi_remove(struct platform_device *pdev) | |||
265 | 267 | ||
266 | static struct platform_driver ath79_spi_driver = { | 268 | static struct platform_driver ath79_spi_driver = { |
267 | .probe = ath79_spi_probe, | 269 | .probe = ath79_spi_probe, |
268 | .remove = ath79_spi_remove, | 270 | .remove = __devexit_p(ath79_spi_remove), |
269 | .driver = { | 271 | .driver = { |
270 | .name = DRV_NAME, | 272 | .name = DRV_NAME, |
271 | .owner = THIS_MODULE, | 273 | .owner = THIS_MODULE, |
272 | }, | 274 | }, |
273 | }; | 275 | }; |
274 | module_platform_driver(ath79_spi_driver); | 276 | |
277 | static __init int ath79_spi_init(void) | ||
278 | { | ||
279 | return platform_driver_register(&ath79_spi_driver); | ||
280 | } | ||
281 | module_init(ath79_spi_init); | ||
282 | |||
283 | static __exit void ath79_spi_exit(void) | ||
284 | { | ||
285 | platform_driver_unregister(&ath79_spi_driver); | ||
286 | } | ||
287 | module_exit(ath79_spi_exit); | ||
275 | 288 | ||
276 | MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); | 289 | MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); |
277 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); | 290 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index ab34497bcfe..82dee9a6c0d 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c | |||
@@ -19,11 +19,10 @@ | |||
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
20 | #include <linux/spi/spi.h> | 20 | #include <linux/spi/spi.h> |
21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
22 | #include <linux/platform_data/atmel.h> | ||
23 | #include <linux/of.h> | ||
24 | 22 | ||
25 | #include <asm/io.h> | 23 | #include <asm/io.h> |
26 | #include <asm/gpio.h> | 24 | #include <mach/board.h> |
25 | #include <mach/gpio.h> | ||
27 | #include <mach/cpu.h> | 26 | #include <mach/cpu.h> |
28 | 27 | ||
29 | /* SPI register offsets */ | 28 | /* SPI register offsets */ |
@@ -769,10 +768,6 @@ static int atmel_spi_setup(struct spi_device *spi) | |||
769 | 768 | ||
770 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | 769 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ |
771 | npcs_pin = (unsigned int)spi->controller_data; | 770 | npcs_pin = (unsigned int)spi->controller_data; |
772 | |||
773 | if (gpio_is_valid(spi->cs_gpio)) | ||
774 | npcs_pin = spi->cs_gpio; | ||
775 | |||
776 | asd = spi->controller_state; | 771 | asd = spi->controller_state; |
777 | if (!asd) { | 772 | if (!asd) { |
778 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | 773 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); |
@@ -912,7 +907,7 @@ static void atmel_spi_cleanup(struct spi_device *spi) | |||
912 | 907 | ||
913 | /*-------------------------------------------------------------------------*/ | 908 | /*-------------------------------------------------------------------------*/ |
914 | 909 | ||
915 | static int atmel_spi_probe(struct platform_device *pdev) | 910 | static int __init atmel_spi_probe(struct platform_device *pdev) |
916 | { | 911 | { |
917 | struct resource *regs; | 912 | struct resource *regs; |
918 | int irq; | 913 | int irq; |
@@ -942,9 +937,8 @@ static int atmel_spi_probe(struct platform_device *pdev) | |||
942 | /* the spi->mode bits understood by this driver: */ | 937 | /* the spi->mode bits understood by this driver: */ |
943 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 938 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
944 | 939 | ||
945 | master->dev.of_node = pdev->dev.of_node; | ||
946 | master->bus_num = pdev->id; | 940 | master->bus_num = pdev->id; |
947 | master->num_chipselect = master->dev.of_node ? 0 : 4; | 941 | master->num_chipselect = 4; |
948 | master->setup = atmel_spi_setup; | 942 | master->setup = atmel_spi_setup; |
949 | master->transfer = atmel_spi_transfer; | 943 | master->transfer = atmel_spi_transfer; |
950 | master->cleanup = atmel_spi_cleanup; | 944 | master->cleanup = atmel_spi_cleanup; |
@@ -1009,7 +1003,7 @@ out_free: | |||
1009 | return ret; | 1003 | return ret; |
1010 | } | 1004 | } |
1011 | 1005 | ||
1012 | static int atmel_spi_remove(struct platform_device *pdev) | 1006 | static int __exit atmel_spi_remove(struct platform_device *pdev) |
1013 | { | 1007 | { |
1014 | struct spi_master *master = platform_get_drvdata(pdev); | 1008 | struct spi_master *master = platform_get_drvdata(pdev); |
1015 | struct atmel_spi *as = spi_master_get_devdata(master); | 1009 | struct atmel_spi *as = spi_master_get_devdata(master); |
@@ -1070,27 +1064,28 @@ static int atmel_spi_resume(struct platform_device *pdev) | |||
1070 | #define atmel_spi_resume NULL | 1064 | #define atmel_spi_resume NULL |
1071 | #endif | 1065 | #endif |
1072 | 1066 | ||
1073 | #if defined(CONFIG_OF) | ||
1074 | static const struct of_device_id atmel_spi_dt_ids[] = { | ||
1075 | { .compatible = "atmel,at91rm9200-spi" }, | ||
1076 | { /* sentinel */ } | ||
1077 | }; | ||
1078 | |||
1079 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); | ||
1080 | #endif | ||
1081 | 1067 | ||
1082 | static struct platform_driver atmel_spi_driver = { | 1068 | static struct platform_driver atmel_spi_driver = { |
1083 | .driver = { | 1069 | .driver = { |
1084 | .name = "atmel_spi", | 1070 | .name = "atmel_spi", |
1085 | .owner = THIS_MODULE, | 1071 | .owner = THIS_MODULE, |
1086 | .of_match_table = of_match_ptr(atmel_spi_dt_ids), | ||
1087 | }, | 1072 | }, |
1088 | .suspend = atmel_spi_suspend, | 1073 | .suspend = atmel_spi_suspend, |
1089 | .resume = atmel_spi_resume, | 1074 | .resume = atmel_spi_resume, |
1090 | .probe = atmel_spi_probe, | ||
1091 | .remove = __exit_p(atmel_spi_remove), | 1075 | .remove = __exit_p(atmel_spi_remove), |
1092 | }; | 1076 | }; |
1093 | module_platform_driver(atmel_spi_driver); | 1077 | |
1078 | static int __init atmel_spi_init(void) | ||
1079 | { | ||
1080 | return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe); | ||
1081 | } | ||
1082 | module_init(atmel_spi_init); | ||
1083 | |||
1084 | static void __exit atmel_spi_exit(void) | ||
1085 | { | ||
1086 | platform_driver_unregister(&atmel_spi_driver); | ||
1087 | } | ||
1088 | module_exit(atmel_spi_exit); | ||
1094 | 1089 | ||
1095 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | 1090 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); |
1096 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); | 1091 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c index 4de66d1cfe5..bddee5f516b 100644 --- a/drivers/spi/spi-au1550.c +++ b/drivers/spi/spi-au1550.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
26 | #include <linux/slab.h> | 26 | #include <linux/slab.h> |
27 | #include <linux/errno.h> | 27 | #include <linux/errno.h> |
28 | #include <linux/module.h> | ||
29 | #include <linux/device.h> | 28 | #include <linux/device.h> |
30 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
31 | #include <linux/resource.h> | 30 | #include <linux/resource.h> |
@@ -475,7 +474,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) | |||
475 | /* | 474 | /* |
476 | * due to an spi error we consider transfer as done, | 475 | * due to an spi error we consider transfer as done, |
477 | * so mask all events until before next transfer start | 476 | * so mask all events until before next transfer start |
478 | * and stop the possibly running dma immediately | 477 | * and stop the possibly running dma immediatelly |
479 | */ | 478 | */ |
480 | au1550_spi_mask_ack_all(hw); | 479 | au1550_spi_mask_ack_all(hw); |
481 | au1xxx_dbdma_stop(hw->dma_rx_ch); | 480 | au1xxx_dbdma_stop(hw->dma_rx_ch); |
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c deleted file mode 100644 index f44ab550853..00000000000 --- a/drivers/spi/spi-bcm63xx.c +++ /dev/null | |||
@@ -1,526 +0,0 @@ | |||
1 | /* | ||
2 | * Broadcom BCM63xx SPI controller support | ||
3 | * | ||
4 | * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> | ||
5 | * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License | ||
9 | * as published by the Free Software Foundation; either version 2 | ||
10 | * of the License, or (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the | ||
19 | * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
20 | */ | ||
21 | |||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/init.h> | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/io.h> | ||
26 | #include <linux/module.h> | ||
27 | #include <linux/platform_device.h> | ||
28 | #include <linux/delay.h> | ||
29 | #include <linux/interrupt.h> | ||
30 | #include <linux/spi/spi.h> | ||
31 | #include <linux/completion.h> | ||
32 | #include <linux/err.h> | ||
33 | #include <linux/workqueue.h> | ||
34 | #include <linux/pm_runtime.h> | ||
35 | |||
36 | #include <bcm63xx_dev_spi.h> | ||
37 | |||
38 | #define PFX KBUILD_MODNAME | ||
39 | |||
40 | struct bcm63xx_spi { | ||
41 | struct completion done; | ||
42 | |||
43 | void __iomem *regs; | ||
44 | int irq; | ||
45 | |||
46 | /* Platform data */ | ||
47 | u32 speed_hz; | ||
48 | unsigned fifo_size; | ||
49 | unsigned int msg_type_shift; | ||
50 | unsigned int msg_ctl_width; | ||
51 | |||
52 | /* Data buffers */ | ||
53 | const unsigned char *tx_ptr; | ||
54 | unsigned char *rx_ptr; | ||
55 | |||
56 | /* data iomem */ | ||
57 | u8 __iomem *tx_io; | ||
58 | const u8 __iomem *rx_io; | ||
59 | |||
60 | int remaining_bytes; | ||
61 | |||
62 | struct clk *clk; | ||
63 | struct platform_device *pdev; | ||
64 | }; | ||
65 | |||
66 | static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, | ||
67 | unsigned int offset) | ||
68 | { | ||
69 | return bcm_readb(bs->regs + bcm63xx_spireg(offset)); | ||
70 | } | ||
71 | |||
72 | static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, | ||
73 | unsigned int offset) | ||
74 | { | ||
75 | return bcm_readw(bs->regs + bcm63xx_spireg(offset)); | ||
76 | } | ||
77 | |||
78 | static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, | ||
79 | u8 value, unsigned int offset) | ||
80 | { | ||
81 | bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); | ||
82 | } | ||
83 | |||
84 | static inline void bcm_spi_writew(struct bcm63xx_spi *bs, | ||
85 | u16 value, unsigned int offset) | ||
86 | { | ||
87 | bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); | ||
88 | } | ||
89 | |||
90 | static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { | ||
91 | { 20000000, SPI_CLK_20MHZ }, | ||
92 | { 12500000, SPI_CLK_12_50MHZ }, | ||
93 | { 6250000, SPI_CLK_6_250MHZ }, | ||
94 | { 3125000, SPI_CLK_3_125MHZ }, | ||
95 | { 1563000, SPI_CLK_1_563MHZ }, | ||
96 | { 781000, SPI_CLK_0_781MHZ }, | ||
97 | { 391000, SPI_CLK_0_391MHZ } | ||
98 | }; | ||
99 | |||
100 | static int bcm63xx_spi_check_transfer(struct spi_device *spi, | ||
101 | struct spi_transfer *t) | ||
102 | { | ||
103 | u8 bits_per_word; | ||
104 | |||
105 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; | ||
106 | if (bits_per_word != 8) { | ||
107 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", | ||
108 | __func__, bits_per_word); | ||
109 | return -EINVAL; | ||
110 | } | ||
111 | |||
112 | if (spi->chip_select > spi->master->num_chipselect) { | ||
113 | dev_err(&spi->dev, "%s, unsupported slave %d\n", | ||
114 | __func__, spi->chip_select); | ||
115 | return -EINVAL; | ||
116 | } | ||
117 | |||
118 | return 0; | ||
119 | } | ||
120 | |||
121 | static void bcm63xx_spi_setup_transfer(struct spi_device *spi, | ||
122 | struct spi_transfer *t) | ||
123 | { | ||
124 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | ||
125 | u32 hz; | ||
126 | u8 clk_cfg, reg; | ||
127 | int i; | ||
128 | |||
129 | hz = (t) ? t->speed_hz : spi->max_speed_hz; | ||
130 | |||
131 | /* Find the closest clock configuration */ | ||
132 | for (i = 0; i < SPI_CLK_MASK; i++) { | ||
133 | if (hz >= bcm63xx_spi_freq_table[i][0]) { | ||
134 | clk_cfg = bcm63xx_spi_freq_table[i][1]; | ||
135 | break; | ||
136 | } | ||
137 | } | ||
138 | |||
139 | /* No matching configuration found, default to lowest */ | ||
140 | if (i == SPI_CLK_MASK) | ||
141 | clk_cfg = SPI_CLK_0_391MHZ; | ||
142 | |||
143 | /* clear existing clock configuration bits of the register */ | ||
144 | reg = bcm_spi_readb(bs, SPI_CLK_CFG); | ||
145 | reg &= ~SPI_CLK_MASK; | ||
146 | reg |= clk_cfg; | ||
147 | |||
148 | bcm_spi_writeb(bs, reg, SPI_CLK_CFG); | ||
149 | dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", | ||
150 | clk_cfg, hz); | ||
151 | } | ||
152 | |||
153 | /* the spi->mode bits understood by this driver: */ | ||
154 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | ||
155 | |||
156 | static int bcm63xx_spi_setup(struct spi_device *spi) | ||
157 | { | ||
158 | struct bcm63xx_spi *bs; | ||
159 | int ret; | ||
160 | |||
161 | bs = spi_master_get_devdata(spi->master); | ||
162 | |||
163 | if (!spi->bits_per_word) | ||
164 | spi->bits_per_word = 8; | ||
165 | |||
166 | if (spi->mode & ~MODEBITS) { | ||
167 | dev_err(&spi->dev, "%s, unsupported mode bits %x\n", | ||
168 | __func__, spi->mode & ~MODEBITS); | ||
169 | return -EINVAL; | ||
170 | } | ||
171 | |||
172 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", | ||
173 | __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); | ||
174 | |||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | /* Fill the TX FIFO with as many bytes as possible */ | ||
179 | static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) | ||
180 | { | ||
181 | u8 size; | ||
182 | |||
183 | /* Fill the Tx FIFO with as many bytes as possible */ | ||
184 | size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes : | ||
185 | bs->fifo_size; | ||
186 | memcpy_toio(bs->tx_io, bs->tx_ptr, size); | ||
187 | bs->remaining_bytes -= size; | ||
188 | } | ||
189 | |||
190 | static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, | ||
191 | struct spi_transfer *t) | ||
192 | { | ||
193 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | ||
194 | u16 msg_ctl; | ||
195 | u16 cmd; | ||
196 | |||
197 | /* Disable the CMD_DONE interrupt */ | ||
198 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | ||
199 | |||
200 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | ||
201 | t->tx_buf, t->rx_buf, t->len); | ||
202 | |||
203 | /* Transmitter is inhibited */ | ||
204 | bs->tx_ptr = t->tx_buf; | ||
205 | bs->rx_ptr = t->rx_buf; | ||
206 | |||
207 | if (t->tx_buf) { | ||
208 | bs->remaining_bytes = t->len; | ||
209 | bcm63xx_spi_fill_tx_fifo(bs); | ||
210 | } | ||
211 | |||
212 | init_completion(&bs->done); | ||
213 | |||
214 | /* Fill in the Message control register */ | ||
215 | msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); | ||
216 | |||
217 | if (t->rx_buf && t->tx_buf) | ||
218 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); | ||
219 | else if (t->rx_buf) | ||
220 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); | ||
221 | else if (t->tx_buf) | ||
222 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); | ||
223 | |||
224 | switch (bs->msg_ctl_width) { | ||
225 | case 8: | ||
226 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); | ||
227 | break; | ||
228 | case 16: | ||
229 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); | ||
230 | break; | ||
231 | } | ||
232 | |||
233 | /* Issue the transfer */ | ||
234 | cmd = SPI_CMD_START_IMMEDIATE; | ||
235 | cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); | ||
236 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); | ||
237 | bcm_spi_writew(bs, cmd, SPI_CMD); | ||
238 | |||
239 | /* Enable the CMD_DONE interrupt */ | ||
240 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); | ||
241 | |||
242 | return t->len - bs->remaining_bytes; | ||
243 | } | ||
244 | |||
245 | static int bcm63xx_spi_prepare_transfer(struct spi_master *master) | ||
246 | { | ||
247 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
248 | |||
249 | pm_runtime_get_sync(&bs->pdev->dev); | ||
250 | |||
251 | return 0; | ||
252 | } | ||
253 | |||
254 | static int bcm63xx_spi_unprepare_transfer(struct spi_master *master) | ||
255 | { | ||
256 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
257 | |||
258 | pm_runtime_put(&bs->pdev->dev); | ||
259 | |||
260 | return 0; | ||
261 | } | ||
262 | |||
263 | static int bcm63xx_spi_transfer_one(struct spi_master *master, | ||
264 | struct spi_message *m) | ||
265 | { | ||
266 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
267 | struct spi_transfer *t; | ||
268 | struct spi_device *spi = m->spi; | ||
269 | int status = 0; | ||
270 | unsigned int timeout = 0; | ||
271 | |||
272 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
273 | unsigned int len = t->len; | ||
274 | u8 rx_tail; | ||
275 | |||
276 | status = bcm63xx_spi_check_transfer(spi, t); | ||
277 | if (status < 0) | ||
278 | goto exit; | ||
279 | |||
280 | /* configure adapter for a new transfer */ | ||
281 | bcm63xx_spi_setup_transfer(spi, t); | ||
282 | |||
283 | while (len) { | ||
284 | /* send the data */ | ||
285 | len -= bcm63xx_txrx_bufs(spi, t); | ||
286 | |||
287 | timeout = wait_for_completion_timeout(&bs->done, HZ); | ||
288 | if (!timeout) { | ||
289 | status = -ETIMEDOUT; | ||
290 | goto exit; | ||
291 | } | ||
292 | |||
293 | /* read out all data */ | ||
294 | rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); | ||
295 | |||
296 | /* Read out all the data */ | ||
297 | if (rx_tail) | ||
298 | memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); | ||
299 | } | ||
300 | |||
301 | m->actual_length += t->len; | ||
302 | } | ||
303 | exit: | ||
304 | m->status = status; | ||
305 | spi_finalize_current_message(master); | ||
306 | |||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | /* This driver supports single master mode only. Hence | ||
311 | * CMD_DONE is the only interrupt we care about | ||
312 | */ | ||
313 | static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) | ||
314 | { | ||
315 | struct spi_master *master = (struct spi_master *)dev_id; | ||
316 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
317 | u8 intr; | ||
318 | |||
319 | /* Read interupts and clear them immediately */ | ||
320 | intr = bcm_spi_readb(bs, SPI_INT_STATUS); | ||
321 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | ||
322 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | ||
323 | |||
324 | /* A transfer completed */ | ||
325 | if (intr & SPI_INTR_CMD_DONE) | ||
326 | complete(&bs->done); | ||
327 | |||
328 | return IRQ_HANDLED; | ||
329 | } | ||
330 | |||
331 | |||
332 | static int bcm63xx_spi_probe(struct platform_device *pdev) | ||
333 | { | ||
334 | struct resource *r; | ||
335 | struct device *dev = &pdev->dev; | ||
336 | struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; | ||
337 | int irq; | ||
338 | struct spi_master *master; | ||
339 | struct clk *clk; | ||
340 | struct bcm63xx_spi *bs; | ||
341 | int ret; | ||
342 | |||
343 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
344 | if (!r) { | ||
345 | dev_err(dev, "no iomem\n"); | ||
346 | ret = -ENXIO; | ||
347 | goto out; | ||
348 | } | ||
349 | |||
350 | irq = platform_get_irq(pdev, 0); | ||
351 | if (irq < 0) { | ||
352 | dev_err(dev, "no irq\n"); | ||
353 | ret = -ENXIO; | ||
354 | goto out; | ||
355 | } | ||
356 | |||
357 | clk = clk_get(dev, "spi"); | ||
358 | if (IS_ERR(clk)) { | ||
359 | dev_err(dev, "no clock for device\n"); | ||
360 | ret = PTR_ERR(clk); | ||
361 | goto out; | ||
362 | } | ||
363 | |||
364 | master = spi_alloc_master(dev, sizeof(*bs)); | ||
365 | if (!master) { | ||
366 | dev_err(dev, "out of memory\n"); | ||
367 | ret = -ENOMEM; | ||
368 | goto out_clk; | ||
369 | } | ||
370 | |||
371 | bs = spi_master_get_devdata(master); | ||
372 | |||
373 | platform_set_drvdata(pdev, master); | ||
374 | bs->pdev = pdev; | ||
375 | |||
376 | if (!devm_request_mem_region(&pdev->dev, r->start, | ||
377 | resource_size(r), PFX)) { | ||
378 | dev_err(dev, "iomem request failed\n"); | ||
379 | ret = -ENXIO; | ||
380 | goto out_err; | ||
381 | } | ||
382 | |||
383 | bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, | ||
384 | resource_size(r)); | ||
385 | if (!bs->regs) { | ||
386 | dev_err(dev, "unable to ioremap regs\n"); | ||
387 | ret = -ENOMEM; | ||
388 | goto out_err; | ||
389 | } | ||
390 | |||
391 | bs->irq = irq; | ||
392 | bs->clk = clk; | ||
393 | bs->fifo_size = pdata->fifo_size; | ||
394 | |||
395 | ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, | ||
396 | pdev->name, master); | ||
397 | if (ret) { | ||
398 | dev_err(dev, "unable to request irq\n"); | ||
399 | goto out_err; | ||
400 | } | ||
401 | |||
402 | master->bus_num = pdata->bus_num; | ||
403 | master->num_chipselect = pdata->num_chipselect; | ||
404 | master->setup = bcm63xx_spi_setup; | ||
405 | master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer; | ||
406 | master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer; | ||
407 | master->transfer_one_message = bcm63xx_spi_transfer_one; | ||
408 | master->mode_bits = MODEBITS; | ||
409 | bs->speed_hz = pdata->speed_hz; | ||
410 | bs->msg_type_shift = pdata->msg_type_shift; | ||
411 | bs->msg_ctl_width = pdata->msg_ctl_width; | ||
412 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); | ||
413 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); | ||
414 | |||
415 | switch (bs->msg_ctl_width) { | ||
416 | case 8: | ||
417 | case 16: | ||
418 | break; | ||
419 | default: | ||
420 | dev_err(dev, "unsupported MSG_CTL width: %d\n", | ||
421 | bs->msg_ctl_width); | ||
422 | goto out_clk_disable; | ||
423 | } | ||
424 | |||
425 | /* Initialize hardware */ | ||
426 | clk_enable(bs->clk); | ||
427 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | ||
428 | |||
429 | /* register and we are done */ | ||
430 | ret = spi_register_master(master); | ||
431 | if (ret) { | ||
432 | dev_err(dev, "spi register failed\n"); | ||
433 | goto out_clk_disable; | ||
434 | } | ||
435 | |||
436 | dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", | ||
437 | r->start, irq, bs->fifo_size); | ||
438 | |||
439 | return 0; | ||
440 | |||
441 | out_clk_disable: | ||
442 | clk_disable(clk); | ||
443 | out_err: | ||
444 | platform_set_drvdata(pdev, NULL); | ||
445 | spi_master_put(master); | ||
446 | out_clk: | ||
447 | clk_put(clk); | ||
448 | out: | ||
449 | return ret; | ||
450 | } | ||
451 | |||
452 | static int bcm63xx_spi_remove(struct platform_device *pdev) | ||
453 | { | ||
454 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | ||
455 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
456 | |||
457 | spi_unregister_master(master); | ||
458 | |||
459 | /* reset spi block */ | ||
460 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | ||
461 | |||
462 | /* HW shutdown */ | ||
463 | clk_disable(bs->clk); | ||
464 | clk_put(bs->clk); | ||
465 | |||
466 | platform_set_drvdata(pdev, 0); | ||
467 | |||
468 | spi_master_put(master); | ||
469 | |||
470 | return 0; | ||
471 | } | ||
472 | |||
473 | #ifdef CONFIG_PM | ||
474 | static int bcm63xx_spi_suspend(struct device *dev) | ||
475 | { | ||
476 | struct spi_master *master = | ||
477 | platform_get_drvdata(to_platform_device(dev)); | ||
478 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
479 | |||
480 | spi_master_suspend(master); | ||
481 | |||
482 | clk_disable(bs->clk); | ||
483 | |||
484 | return 0; | ||
485 | } | ||
486 | |||
487 | static int bcm63xx_spi_resume(struct device *dev) | ||
488 | { | ||
489 | struct spi_master *master = | ||
490 | platform_get_drvdata(to_platform_device(dev)); | ||
491 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | ||
492 | |||
493 | clk_enable(bs->clk); | ||
494 | |||
495 | spi_master_resume(master); | ||
496 | |||
497 | return 0; | ||
498 | } | ||
499 | |||
500 | static const struct dev_pm_ops bcm63xx_spi_pm_ops = { | ||
501 | .suspend = bcm63xx_spi_suspend, | ||
502 | .resume = bcm63xx_spi_resume, | ||
503 | }; | ||
504 | |||
505 | #define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) | ||
506 | #else | ||
507 | #define BCM63XX_SPI_PM_OPS NULL | ||
508 | #endif | ||
509 | |||
510 | static struct platform_driver bcm63xx_spi_driver = { | ||
511 | .driver = { | ||
512 | .name = "bcm63xx-spi", | ||
513 | .owner = THIS_MODULE, | ||
514 | .pm = BCM63XX_SPI_PM_OPS, | ||
515 | }, | ||
516 | .probe = bcm63xx_spi_probe, | ||
517 | .remove = bcm63xx_spi_remove, | ||
518 | }; | ||
519 | |||
520 | module_platform_driver(bcm63xx_spi_driver); | ||
521 | |||
522 | MODULE_ALIAS("platform:bcm63xx_spi"); | ||
523 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | ||
524 | MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); | ||
525 | MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); | ||
526 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c index ac7ffca7ba4..e557ff617b1 100644 --- a/drivers/spi/spi-bfin-sport.c +++ b/drivers/spi/spi-bfin-sport.c | |||
@@ -252,15 +252,19 @@ static void | |||
252 | bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data) | 252 | bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data) |
253 | { | 253 | { |
254 | struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; | 254 | struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; |
255 | unsigned int bits = (drv_data->ops == &bfin_sport_transfer_ops_u8 ? 7 : 15); | ||
255 | 256 | ||
256 | bfin_sport_spi_disable(drv_data); | 257 | bfin_sport_spi_disable(drv_data); |
257 | dev_dbg(drv_data->dev, "restoring spi ctl state\n"); | 258 | dev_dbg(drv_data->dev, "restoring spi ctl state\n"); |
258 | 259 | ||
259 | bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); | 260 | bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); |
261 | bfin_write(&drv_data->regs->tcr2, bits); | ||
260 | bfin_write(&drv_data->regs->tclkdiv, chip->baud); | 262 | bfin_write(&drv_data->regs->tclkdiv, chip->baud); |
263 | bfin_write(&drv_data->regs->tfsdiv, bits); | ||
261 | SSYNC(); | 264 | SSYNC(); |
262 | 265 | ||
263 | bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); | 266 | bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); |
267 | bfin_write(&drv_data->regs->rcr2, bits); | ||
264 | SSYNC(); | 268 | SSYNC(); |
265 | 269 | ||
266 | bfin_sport_spi_cs_active(chip); | 270 | bfin_sport_spi_cs_active(chip); |
@@ -416,15 +420,11 @@ bfin_sport_spi_pump_transfers(unsigned long data) | |||
416 | drv_data->cs_change = transfer->cs_change; | 420 | drv_data->cs_change = transfer->cs_change; |
417 | 421 | ||
418 | /* Bits per word setup */ | 422 | /* Bits per word setup */ |
419 | bits_per_word = transfer->bits_per_word ? : | 423 | bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; |
420 | message->spi->bits_per_word ? : 8; | 424 | if (bits_per_word == 8) |
421 | if (bits_per_word % 16 == 0) | ||
422 | drv_data->ops = &bfin_sport_transfer_ops_u16; | ||
423 | else | ||
424 | drv_data->ops = &bfin_sport_transfer_ops_u8; | 425 | drv_data->ops = &bfin_sport_transfer_ops_u8; |
425 | bfin_write(&drv_data->regs->tcr2, bits_per_word - 1); | 426 | else |
426 | bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1); | 427 | drv_data->ops = &bfin_sport_transfer_ops_u16; |
427 | bfin_write(&drv_data->regs->rcr2, bits_per_word - 1); | ||
428 | 428 | ||
429 | drv_data->state = RUNNING_STATE; | 429 | drv_data->state = RUNNING_STATE; |
430 | 430 | ||
@@ -467,7 +467,7 @@ bfin_sport_spi_pump_transfers(unsigned long data) | |||
467 | dev_dbg(drv_data->dev, "IO write error!\n"); | 467 | dev_dbg(drv_data->dev, "IO write error!\n"); |
468 | drv_data->state = ERROR_STATE; | 468 | drv_data->state = ERROR_STATE; |
469 | } else { | 469 | } else { |
470 | /* Update total byte transferred */ | 470 | /* Update total byte transfered */ |
471 | message->actual_length += transfer->len; | 471 | message->actual_length += transfer->len; |
472 | /* Move to next transfer of this msg */ | 472 | /* Move to next transfer of this msg */ |
473 | drv_data->state = bfin_sport_spi_next_transfer(drv_data); | 473 | drv_data->state = bfin_sport_spi_next_transfer(drv_data); |
@@ -598,12 +598,11 @@ bfin_sport_spi_setup(struct spi_device *spi) | |||
598 | } | 598 | } |
599 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | 599 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
600 | chip->idle_tx_val = chip_info->idle_tx_val; | 600 | chip->idle_tx_val = chip_info->idle_tx_val; |
601 | spi->bits_per_word = chip_info->bits_per_word; | ||
601 | } | 602 | } |
602 | } | 603 | } |
603 | 604 | ||
604 | if (spi->bits_per_word % 8) { | 605 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) { |
605 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | ||
606 | spi->bits_per_word); | ||
607 | ret = -EINVAL; | 606 | ret = -EINVAL; |
608 | goto error; | 607 | goto error; |
609 | } | 608 | } |
@@ -755,7 +754,8 @@ bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data *drv_data) | |||
755 | return 0; | 754 | return 0; |
756 | } | 755 | } |
757 | 756 | ||
758 | static int bfin_sport_spi_probe(struct platform_device *pdev) | 757 | static int __devinit |
758 | bfin_sport_spi_probe(struct platform_device *pdev) | ||
759 | { | 759 | { |
760 | struct device *dev = &pdev->dev; | 760 | struct device *dev = &pdev->dev; |
761 | struct bfin5xx_spi_master *platform_info; | 761 | struct bfin5xx_spi_master *platform_info; |
@@ -862,7 +862,8 @@ static int bfin_sport_spi_probe(struct platform_device *pdev) | |||
862 | } | 862 | } |
863 | 863 | ||
864 | /* stop hardware and remove the driver */ | 864 | /* stop hardware and remove the driver */ |
865 | static int bfin_sport_spi_remove(struct platform_device *pdev) | 865 | static int __devexit |
866 | bfin_sport_spi_remove(struct platform_device *pdev) | ||
866 | { | 867 | { |
867 | struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev); | 868 | struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev); |
868 | int status = 0; | 869 | int status = 0; |
@@ -933,8 +934,19 @@ static struct platform_driver bfin_sport_spi_driver = { | |||
933 | .owner = THIS_MODULE, | 934 | .owner = THIS_MODULE, |
934 | }, | 935 | }, |
935 | .probe = bfin_sport_spi_probe, | 936 | .probe = bfin_sport_spi_probe, |
936 | .remove = bfin_sport_spi_remove, | 937 | .remove = __devexit_p(bfin_sport_spi_remove), |
937 | .suspend = bfin_sport_spi_suspend, | 938 | .suspend = bfin_sport_spi_suspend, |
938 | .resume = bfin_sport_spi_resume, | 939 | .resume = bfin_sport_spi_resume, |
939 | }; | 940 | }; |
940 | module_platform_driver(bfin_sport_spi_driver); | 941 | |
942 | static int __init bfin_sport_spi_init(void) | ||
943 | { | ||
944 | return platform_driver_register(&bfin_sport_spi_driver); | ||
945 | } | ||
946 | module_init(bfin_sport_spi_init); | ||
947 | |||
948 | static void __exit bfin_sport_spi_exit(void) | ||
949 | { | ||
950 | platform_driver_unregister(&bfin_sport_spi_driver); | ||
951 | } | ||
952 | module_exit(bfin_sport_spi_exit); | ||
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c index 0429d833f75..b8d25f2b703 100644 --- a/drivers/spi/spi-bfin5xx.c +++ b/drivers/spi/spi-bfin5xx.c | |||
@@ -396,7 +396,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
396 | /* last read */ | 396 | /* last read */ |
397 | if (drv_data->rx) { | 397 | if (drv_data->rx) { |
398 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | 398 | dev_dbg(&drv_data->pdev->dev, "last read\n"); |
399 | if (!(n_bytes % 2)) { | 399 | if (n_bytes % 2) { |
400 | u16 *buf = (u16 *)drv_data->rx; | 400 | u16 *buf = (u16 *)drv_data->rx; |
401 | for (loop = 0; loop < n_bytes / 2; loop++) | 401 | for (loop = 0; loop < n_bytes / 2; loop++) |
402 | *buf++ = bfin_read(&drv_data->regs->rdbr); | 402 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
@@ -424,7 +424,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
424 | if (drv_data->rx && drv_data->tx) { | 424 | if (drv_data->rx && drv_data->tx) { |
425 | /* duplex */ | 425 | /* duplex */ |
426 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | 426 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); |
427 | if (!(n_bytes % 2)) { | 427 | if (n_bytes % 2) { |
428 | u16 *buf = (u16 *)drv_data->rx; | 428 | u16 *buf = (u16 *)drv_data->rx; |
429 | u16 *buf2 = (u16 *)drv_data->tx; | 429 | u16 *buf2 = (u16 *)drv_data->tx; |
430 | for (loop = 0; loop < n_bytes / 2; loop++) { | 430 | for (loop = 0; loop < n_bytes / 2; loop++) { |
@@ -442,7 +442,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
442 | } else if (drv_data->rx) { | 442 | } else if (drv_data->rx) { |
443 | /* read */ | 443 | /* read */ |
444 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | 444 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); |
445 | if (!(n_bytes % 2)) { | 445 | if (n_bytes % 2) { |
446 | u16 *buf = (u16 *)drv_data->rx; | 446 | u16 *buf = (u16 *)drv_data->rx; |
447 | for (loop = 0; loop < n_bytes / 2; loop++) { | 447 | for (loop = 0; loop < n_bytes / 2; loop++) { |
448 | *buf++ = bfin_read(&drv_data->regs->rdbr); | 448 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
@@ -458,7 +458,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
458 | } else if (drv_data->tx) { | 458 | } else if (drv_data->tx) { |
459 | /* write */ | 459 | /* write */ |
460 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | 460 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); |
461 | if (!(n_bytes % 2)) { | 461 | if (n_bytes % 2) { |
462 | u16 *buf = (u16 *)drv_data->tx; | 462 | u16 *buf = (u16 *)drv_data->tx; |
463 | for (loop = 0; loop < n_bytes / 2; loop++) { | 463 | for (loop = 0; loop < n_bytes / 2; loop++) { |
464 | bfin_read(&drv_data->regs->rdbr); | 464 | bfin_read(&drv_data->regs->rdbr); |
@@ -587,7 +587,6 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
587 | if (message->state == DONE_STATE) { | 587 | if (message->state == DONE_STATE) { |
588 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); | 588 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
589 | message->status = 0; | 589 | message->status = 0; |
590 | bfin_spi_flush(drv_data); | ||
591 | bfin_spi_giveback(drv_data); | 590 | bfin_spi_giveback(drv_data); |
592 | return; | 591 | return; |
593 | } | 592 | } |
@@ -871,10 +870,8 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
871 | message->actual_length += drv_data->len_in_bytes; | 870 | message->actual_length += drv_data->len_in_bytes; |
872 | /* Move to next transfer of this msg */ | 871 | /* Move to next transfer of this msg */ |
873 | message->state = bfin_spi_next_transfer(drv_data); | 872 | message->state = bfin_spi_next_transfer(drv_data); |
874 | if (drv_data->cs_change && message->state != DONE_STATE) { | 873 | if (drv_data->cs_change) |
875 | bfin_spi_flush(drv_data); | ||
876 | bfin_spi_cs_deactive(drv_data, chip); | 874 | bfin_spi_cs_deactive(drv_data, chip); |
877 | } | ||
878 | } | 875 | } |
879 | 876 | ||
880 | /* Schedule next transfer tasklet */ | 877 | /* Schedule next transfer tasklet */ |
@@ -1029,6 +1026,7 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
1029 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | 1026 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
1030 | chip->idle_tx_val = chip_info->idle_tx_val; | 1027 | chip->idle_tx_val = chip_info->idle_tx_val; |
1031 | chip->pio_interrupt = chip_info->pio_interrupt; | 1028 | chip->pio_interrupt = chip_info->pio_interrupt; |
1029 | spi->bits_per_word = chip_info->bits_per_word; | ||
1032 | } else { | 1030 | } else { |
1033 | /* force a default base state */ | 1031 | /* force a default base state */ |
1034 | chip->ctl_reg &= bfin_ctl_reg; | 1032 | chip->ctl_reg &= bfin_ctl_reg; |
@@ -1100,7 +1098,7 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
1100 | 1098 | ||
1101 | if (chip->pio_interrupt && !drv_data->irq_requested) { | 1099 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1102 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | 1100 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, |
1103 | 0, "BFIN_SPI", drv_data); | 1101 | IRQF_DISABLED, "BFIN_SPI", drv_data); |
1104 | if (ret) { | 1102 | if (ret) { |
1105 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | 1103 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); |
1106 | goto error; | 1104 | goto error; |
@@ -1387,7 +1385,7 @@ out_error_get_res: | |||
1387 | } | 1385 | } |
1388 | 1386 | ||
1389 | /* stop hardware and remove the driver */ | 1387 | /* stop hardware and remove the driver */ |
1390 | static int bfin_spi_remove(struct platform_device *pdev) | 1388 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
1391 | { | 1389 | { |
1392 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); | 1390 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
1393 | int status = 0; | 1391 | int status = 0; |
@@ -1477,7 +1475,7 @@ static struct platform_driver bfin_spi_driver = { | |||
1477 | }, | 1475 | }, |
1478 | .suspend = bfin_spi_suspend, | 1476 | .suspend = bfin_spi_suspend, |
1479 | .resume = bfin_spi_resume, | 1477 | .resume = bfin_spi_resume, |
1480 | .remove = bfin_spi_remove, | 1478 | .remove = __devexit_p(bfin_spi_remove), |
1481 | }; | 1479 | }; |
1482 | 1480 | ||
1483 | static int __init bfin_spi_init(void) | 1481 | static int __init bfin_spi_init(void) |
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c index 8b3d8efafd3..02d57fbba29 100644 --- a/drivers/spi/spi-bitbang.c +++ b/drivers/spi/spi-bitbang.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
21 | #include <linux/workqueue.h> | 21 | #include <linux/workqueue.h> |
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | #include <linux/module.h> | ||
24 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
25 | #include <linux/errno.h> | 24 | #include <linux/errno.h> |
26 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
@@ -260,11 +259,11 @@ static void bitbang_work(struct work_struct *work) | |||
260 | struct spi_bitbang *bitbang = | 259 | struct spi_bitbang *bitbang = |
261 | container_of(work, struct spi_bitbang, work); | 260 | container_of(work, struct spi_bitbang, work); |
262 | unsigned long flags; | 261 | unsigned long flags; |
263 | struct spi_message *m, *_m; | ||
264 | 262 | ||
265 | spin_lock_irqsave(&bitbang->lock, flags); | 263 | spin_lock_irqsave(&bitbang->lock, flags); |
266 | bitbang->busy = 1; | 264 | bitbang->busy = 1; |
267 | list_for_each_entry_safe(m, _m, &bitbang->queue, queue) { | 265 | while (!list_empty(&bitbang->queue)) { |
266 | struct spi_message *m; | ||
268 | struct spi_device *spi; | 267 | struct spi_device *spi; |
269 | unsigned nsecs; | 268 | unsigned nsecs; |
270 | struct spi_transfer *t = NULL; | 269 | struct spi_transfer *t = NULL; |
@@ -273,7 +272,9 @@ static void bitbang_work(struct work_struct *work) | |||
273 | int status; | 272 | int status; |
274 | int do_setup = -1; | 273 | int do_setup = -1; |
275 | 274 | ||
276 | list_del(&m->queue); | 275 | m = container_of(bitbang->queue.next, struct spi_message, |
276 | queue); | ||
277 | list_del_init(&m->queue); | ||
277 | spin_unlock_irqrestore(&bitbang->lock, flags); | 278 | spin_unlock_irqrestore(&bitbang->lock, flags); |
278 | 279 | ||
279 | /* FIXME this is made-up ... the correct value is known to | 280 | /* FIXME this is made-up ... the correct value is known to |
@@ -344,14 +345,17 @@ static void bitbang_work(struct work_struct *work) | |||
344 | if (t->delay_usecs) | 345 | if (t->delay_usecs) |
345 | udelay(t->delay_usecs); | 346 | udelay(t->delay_usecs); |
346 | 347 | ||
347 | if (cs_change && !list_is_last(&t->transfer_list, &m->transfers)) { | 348 | if (!cs_change) |
348 | /* sometimes a short mid-message deselect of the chip | 349 | continue; |
349 | * may be needed to terminate a mode or command | 350 | if (t->transfer_list.next == &m->transfers) |
350 | */ | 351 | break; |
351 | ndelay(nsecs); | 352 | |
352 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | 353 | /* sometimes a short mid-message deselect of the chip |
353 | ndelay(nsecs); | 354 | * may be needed to terminate a mode or command |
354 | } | 355 | */ |
356 | ndelay(nsecs); | ||
357 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | ||
358 | ndelay(nsecs); | ||
355 | } | 359 | } |
356 | 360 | ||
357 | m->status = status; | 361 | m->status = status; |
diff --git a/drivers/spi/spi-butterfly.c b/drivers/spi/spi-butterfly.c index 5ed08e53743..9f907ec52de 100644 --- a/drivers/spi/spi-butterfly.c +++ b/drivers/spi/spi-butterfly.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/module.h> | ||
24 | #include <linux/device.h> | 23 | #include <linux/device.h> |
25 | #include <linux/parport.h> | 24 | #include <linux/parport.h> |
26 | 25 | ||
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c deleted file mode 100644 index 1366c4620d5..00000000000 --- a/drivers/spi/spi-clps711x.c +++ /dev/null | |||
@@ -1,296 +0,0 @@ | |||
1 | /* | ||
2 | * CLPS711X SPI bus driver | ||
3 | * | ||
4 | * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #include <linux/io.h> | ||
13 | #include <linux/clk.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/gpio.h> | ||
16 | #include <linux/delay.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/spi/spi.h> | ||
21 | #include <linux/platform_data/spi-clps711x.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | |||
25 | #define DRIVER_NAME "spi-clps711x" | ||
26 | |||
27 | struct spi_clps711x_data { | ||
28 | struct completion done; | ||
29 | |||
30 | struct clk *spi_clk; | ||
31 | u32 max_speed_hz; | ||
32 | |||
33 | u8 *tx_buf; | ||
34 | u8 *rx_buf; | ||
35 | int count; | ||
36 | int len; | ||
37 | |||
38 | int chipselect[0]; | ||
39 | }; | ||
40 | |||
41 | static int spi_clps711x_setup(struct spi_device *spi) | ||
42 | { | ||
43 | struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master); | ||
44 | |||
45 | if (spi->bits_per_word != 8) { | ||
46 | dev_err(&spi->dev, "Unsupported master bus width %i\n", | ||
47 | spi->bits_per_word); | ||
48 | return -EINVAL; | ||
49 | } | ||
50 | |||
51 | /* We are expect that SPI-device is not selected */ | ||
52 | gpio_direction_output(hw->chipselect[spi->chip_select], | ||
53 | !(spi->mode & SPI_CS_HIGH)); | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | static void spi_clps711x_setup_mode(struct spi_device *spi) | ||
59 | { | ||
60 | /* Setup edge for transfer */ | ||
61 | if (spi->mode & SPI_CPHA) | ||
62 | clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3); | ||
63 | else | ||
64 | clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3); | ||
65 | } | ||
66 | |||
67 | static int spi_clps711x_setup_xfer(struct spi_device *spi, | ||
68 | struct spi_transfer *xfer) | ||
69 | { | ||
70 | u32 speed = xfer->speed_hz ? : spi->max_speed_hz; | ||
71 | u8 bpw = xfer->bits_per_word ? : spi->bits_per_word; | ||
72 | struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master); | ||
73 | |||
74 | if (bpw != 8) { | ||
75 | dev_err(&spi->dev, "Unsupported master bus width %i\n", bpw); | ||
76 | return -EINVAL; | ||
77 | } | ||
78 | |||
79 | /* Setup SPI frequency divider */ | ||
80 | if (!speed || (speed >= hw->max_speed_hz)) | ||
81 | clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | | ||
82 | SYSCON1_ADCKSEL(3), SYSCON1); | ||
83 | else if (speed >= (hw->max_speed_hz / 2)) | ||
84 | clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | | ||
85 | SYSCON1_ADCKSEL(2), SYSCON1); | ||
86 | else if (speed >= (hw->max_speed_hz / 8)) | ||
87 | clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | | ||
88 | SYSCON1_ADCKSEL(1), SYSCON1); | ||
89 | else | ||
90 | clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | | ||
91 | SYSCON1_ADCKSEL(0), SYSCON1); | ||
92 | |||
93 | return 0; | ||
94 | } | ||
95 | |||
96 | static int spi_clps711x_transfer_one_message(struct spi_master *master, | ||
97 | struct spi_message *msg) | ||
98 | { | ||
99 | struct spi_clps711x_data *hw = spi_master_get_devdata(master); | ||
100 | struct spi_transfer *xfer; | ||
101 | int status = 0, cs = hw->chipselect[msg->spi->chip_select]; | ||
102 | u32 data; | ||
103 | |||
104 | spi_clps711x_setup_mode(msg->spi); | ||
105 | |||
106 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
107 | if (spi_clps711x_setup_xfer(msg->spi, xfer)) { | ||
108 | status = -EINVAL; | ||
109 | goto out_xfr; | ||
110 | } | ||
111 | |||
112 | gpio_set_value(cs, !!(msg->spi->mode & SPI_CS_HIGH)); | ||
113 | |||
114 | INIT_COMPLETION(hw->done); | ||
115 | |||
116 | hw->count = 0; | ||
117 | hw->len = xfer->len; | ||
118 | hw->tx_buf = (u8 *)xfer->tx_buf; | ||
119 | hw->rx_buf = (u8 *)xfer->rx_buf; | ||
120 | |||
121 | /* Initiate transfer */ | ||
122 | data = hw->tx_buf ? hw->tx_buf[hw->count] : 0; | ||
123 | clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO); | ||
124 | |||
125 | wait_for_completion(&hw->done); | ||
126 | |||
127 | if (xfer->delay_usecs) | ||
128 | udelay(xfer->delay_usecs); | ||
129 | |||
130 | if (xfer->cs_change || | ||
131 | list_is_last(&xfer->transfer_list, &msg->transfers)) | ||
132 | gpio_set_value(cs, !(msg->spi->mode & SPI_CS_HIGH)); | ||
133 | |||
134 | msg->actual_length += xfer->len; | ||
135 | } | ||
136 | |||
137 | out_xfr: | ||
138 | msg->status = status; | ||
139 | spi_finalize_current_message(master); | ||
140 | |||
141 | return 0; | ||
142 | } | ||
143 | |||
144 | static irqreturn_t spi_clps711x_isr(int irq, void *dev_id) | ||
145 | { | ||
146 | struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id; | ||
147 | u32 data; | ||
148 | |||
149 | /* Handle RX */ | ||
150 | data = clps_readb(SYNCIO); | ||
151 | if (hw->rx_buf) | ||
152 | hw->rx_buf[hw->count] = (u8)data; | ||
153 | |||
154 | hw->count++; | ||
155 | |||
156 | /* Handle TX */ | ||
157 | if (hw->count < hw->len) { | ||
158 | data = hw->tx_buf ? hw->tx_buf[hw->count] : 0; | ||
159 | clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO); | ||
160 | } else | ||
161 | complete(&hw->done); | ||
162 | |||
163 | return IRQ_HANDLED; | ||
164 | } | ||
165 | |||
166 | static int spi_clps711x_probe(struct platform_device *pdev) | ||
167 | { | ||
168 | int i, ret; | ||
169 | struct spi_master *master; | ||
170 | struct spi_clps711x_data *hw; | ||
171 | struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev); | ||
172 | |||
173 | if (!pdata) { | ||
174 | dev_err(&pdev->dev, "No platform data supplied\n"); | ||
175 | return -EINVAL; | ||
176 | } | ||
177 | |||
178 | if (pdata->num_chipselect < 1) { | ||
179 | dev_err(&pdev->dev, "At least one CS must be defined\n"); | ||
180 | return -EINVAL; | ||
181 | } | ||
182 | |||
183 | master = spi_alloc_master(&pdev->dev, | ||
184 | sizeof(struct spi_clps711x_data) + | ||
185 | sizeof(int) * pdata->num_chipselect); | ||
186 | if (!master) { | ||
187 | dev_err(&pdev->dev, "SPI allocating memory error\n"); | ||
188 | return -ENOMEM; | ||
189 | } | ||
190 | |||
191 | master->bus_num = pdev->id; | ||
192 | master->mode_bits = SPI_CPHA | SPI_CS_HIGH; | ||
193 | master->num_chipselect = pdata->num_chipselect; | ||
194 | master->setup = spi_clps711x_setup; | ||
195 | master->transfer_one_message = spi_clps711x_transfer_one_message; | ||
196 | |||
197 | hw = spi_master_get_devdata(master); | ||
198 | |||
199 | for (i = 0; i < master->num_chipselect; i++) { | ||
200 | hw->chipselect[i] = pdata->chipselect[i]; | ||
201 | if (!gpio_is_valid(hw->chipselect[i])) { | ||
202 | dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i); | ||
203 | ret = -EINVAL; | ||
204 | goto err_out; | ||
205 | } | ||
206 | if (gpio_request(hw->chipselect[i], DRIVER_NAME)) { | ||
207 | dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); | ||
208 | ret = -EINVAL; | ||
209 | goto err_out; | ||
210 | } | ||
211 | } | ||
212 | |||
213 | hw->spi_clk = devm_clk_get(&pdev->dev, "spi"); | ||
214 | if (IS_ERR(hw->spi_clk)) { | ||
215 | dev_err(&pdev->dev, "Can't get clocks\n"); | ||
216 | ret = PTR_ERR(hw->spi_clk); | ||
217 | goto err_out; | ||
218 | } | ||
219 | hw->max_speed_hz = clk_get_rate(hw->spi_clk); | ||
220 | |||
221 | init_completion(&hw->done); | ||
222 | platform_set_drvdata(pdev, master); | ||
223 | |||
224 | /* Disable extended mode due hardware problems */ | ||
225 | clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3); | ||
226 | |||
227 | /* Clear possible pending interrupt */ | ||
228 | clps_readl(SYNCIO); | ||
229 | |||
230 | ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0, | ||
231 | dev_name(&pdev->dev), hw); | ||
232 | if (ret) { | ||
233 | dev_err(&pdev->dev, "Can't request IRQ\n"); | ||
234 | clk_put(hw->spi_clk); | ||
235 | goto clk_out; | ||
236 | } | ||
237 | |||
238 | ret = spi_register_master(master); | ||
239 | if (!ret) { | ||
240 | dev_info(&pdev->dev, | ||
241 | "SPI bus driver initialized. Master clock %u Hz\n", | ||
242 | hw->max_speed_hz); | ||
243 | return 0; | ||
244 | } | ||
245 | |||
246 | dev_err(&pdev->dev, "Failed to register master\n"); | ||
247 | devm_free_irq(&pdev->dev, IRQ_SSEOTI, hw); | ||
248 | |||
249 | clk_out: | ||
250 | devm_clk_put(&pdev->dev, hw->spi_clk); | ||
251 | |||
252 | err_out: | ||
253 | while (--i >= 0) | ||
254 | if (gpio_is_valid(hw->chipselect[i])) | ||
255 | gpio_free(hw->chipselect[i]); | ||
256 | |||
257 | platform_set_drvdata(pdev, NULL); | ||
258 | spi_master_put(master); | ||
259 | kfree(master); | ||
260 | |||
261 | return ret; | ||
262 | } | ||
263 | |||
264 | static int spi_clps711x_remove(struct platform_device *pdev) | ||
265 | { | ||
266 | int i; | ||
267 | struct spi_master *master = platform_get_drvdata(pdev); | ||
268 | struct spi_clps711x_data *hw = spi_master_get_devdata(master); | ||
269 | |||
270 | devm_free_irq(&pdev->dev, IRQ_SSEOTI, hw); | ||
271 | |||
272 | for (i = 0; i < master->num_chipselect; i++) | ||
273 | if (gpio_is_valid(hw->chipselect[i])) | ||
274 | gpio_free(hw->chipselect[i]); | ||
275 | |||
276 | devm_clk_put(&pdev->dev, hw->spi_clk); | ||
277 | platform_set_drvdata(pdev, NULL); | ||
278 | spi_unregister_master(master); | ||
279 | kfree(master); | ||
280 | |||
281 | return 0; | ||
282 | } | ||
283 | |||
284 | static struct platform_driver clps711x_spi_driver = { | ||
285 | .driver = { | ||
286 | .name = DRIVER_NAME, | ||
287 | .owner = THIS_MODULE, | ||
288 | }, | ||
289 | .probe = spi_clps711x_probe, | ||
290 | .remove = spi_clps711x_remove, | ||
291 | }; | ||
292 | module_platform_driver(clps711x_spi_driver); | ||
293 | |||
294 | MODULE_LICENSE("GPL"); | ||
295 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); | ||
296 | MODULE_DESCRIPTION("CLPS711X SPI bus driver"); | ||
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c index 58466b810da..ae2cd1c1fda 100644 --- a/drivers/spi/spi-coldfire-qspi.c +++ b/drivers/spi/spi-coldfire-qspi.c | |||
@@ -25,12 +25,12 @@ | |||
25 | #include <linux/errno.h> | 25 | #include <linux/errno.h> |
26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
27 | #include <linux/sched.h> | 27 | #include <linux/sched.h> |
28 | #include <linux/workqueue.h> | ||
28 | #include <linux/delay.h> | 29 | #include <linux/delay.h> |
29 | #include <linux/io.h> | 30 | #include <linux/io.h> |
30 | #include <linux/clk.h> | 31 | #include <linux/clk.h> |
31 | #include <linux/err.h> | 32 | #include <linux/err.h> |
32 | #include <linux/spi/spi.h> | 33 | #include <linux/spi/spi.h> |
33 | #include <linux/pm_runtime.h> | ||
34 | 34 | ||
35 | #include <asm/coldfire.h> | 35 | #include <asm/coldfire.h> |
36 | #include <asm/mcfsim.h> | 36 | #include <asm/mcfsim.h> |
@@ -78,7 +78,10 @@ struct mcfqspi { | |||
78 | 78 | ||
79 | wait_queue_head_t waitq; | 79 | wait_queue_head_t waitq; |
80 | 80 | ||
81 | struct device *dev; | 81 | struct work_struct work; |
82 | struct workqueue_struct *workq; | ||
83 | spinlock_t lock; | ||
84 | struct list_head msgq; | ||
82 | }; | 85 | }; |
83 | 86 | ||
84 | static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) | 87 | static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) |
@@ -300,80 +303,120 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, | |||
300 | } | 303 | } |
301 | } | 304 | } |
302 | 305 | ||
303 | static int mcfqspi_transfer_one_message(struct spi_master *master, | 306 | static void mcfqspi_work(struct work_struct *work) |
304 | struct spi_message *msg) | ||
305 | { | 307 | { |
306 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | 308 | struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work); |
307 | struct spi_device *spi = msg->spi; | 309 | unsigned long flags; |
308 | struct spi_transfer *t; | 310 | |
309 | int status = 0; | 311 | spin_lock_irqsave(&mcfqspi->lock, flags); |
310 | 312 | while (!list_empty(&mcfqspi->msgq)) { | |
311 | list_for_each_entry(t, &msg->transfers, transfer_list) { | 313 | struct spi_message *msg; |
312 | bool cs_high = spi->mode & SPI_CS_HIGH; | 314 | struct spi_device *spi; |
313 | u16 qmr = MCFQSPI_QMR_MSTR; | 315 | struct spi_transfer *xfer; |
314 | 316 | int status = 0; | |
315 | if (t->bits_per_word) | 317 | |
316 | qmr |= t->bits_per_word << 10; | 318 | msg = container_of(mcfqspi->msgq.next, struct spi_message, |
317 | else | 319 | queue); |
318 | qmr |= spi->bits_per_word << 10; | 320 | |
319 | if (spi->mode & SPI_CPHA) | 321 | list_del_init(&msg->queue); |
320 | qmr |= MCFQSPI_QMR_CPHA; | 322 | spin_unlock_irqrestore(&mcfqspi->lock, flags); |
321 | if (spi->mode & SPI_CPOL) | 323 | |
322 | qmr |= MCFQSPI_QMR_CPOL; | 324 | spi = msg->spi; |
323 | if (t->speed_hz) | 325 | |
324 | qmr |= mcfqspi_qmr_baud(t->speed_hz); | 326 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
325 | else | 327 | bool cs_high = spi->mode & SPI_CS_HIGH; |
326 | qmr |= mcfqspi_qmr_baud(spi->max_speed_hz); | 328 | u16 qmr = MCFQSPI_QMR_MSTR; |
327 | mcfqspi_wr_qmr(mcfqspi, qmr); | 329 | |
328 | 330 | if (xfer->bits_per_word) | |
329 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); | 331 | qmr |= xfer->bits_per_word << 10; |
330 | 332 | else | |
331 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); | 333 | qmr |= spi->bits_per_word << 10; |
332 | if ((t->bits_per_word ? t->bits_per_word : | 334 | if (spi->mode & SPI_CPHA) |
333 | spi->bits_per_word) == 8) | 335 | qmr |= MCFQSPI_QMR_CPHA; |
334 | mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, | 336 | if (spi->mode & SPI_CPOL) |
335 | t->rx_buf); | 337 | qmr |= MCFQSPI_QMR_CPOL; |
336 | else | 338 | if (xfer->speed_hz) |
337 | mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf, | 339 | qmr |= mcfqspi_qmr_baud(xfer->speed_hz); |
338 | t->rx_buf); | 340 | else |
339 | mcfqspi_wr_qir(mcfqspi, 0); | 341 | qmr |= mcfqspi_qmr_baud(spi->max_speed_hz); |
340 | 342 | mcfqspi_wr_qmr(mcfqspi, qmr); | |
341 | if (t->delay_usecs) | 343 | |
342 | udelay(t->delay_usecs); | 344 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); |
343 | if (t->cs_change) { | 345 | |
344 | if (!list_is_last(&t->transfer_list, &msg->transfers)) | 346 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); |
345 | mcfqspi_cs_deselect(mcfqspi, spi->chip_select, | 347 | if ((xfer->bits_per_word ? xfer->bits_per_word : |
346 | cs_high); | 348 | spi->bits_per_word) == 8) |
347 | } else { | 349 | mcfqspi_transfer_msg8(mcfqspi, xfer->len, |
348 | if (list_is_last(&t->transfer_list, &msg->transfers)) | 350 | xfer->tx_buf, |
349 | mcfqspi_cs_deselect(mcfqspi, spi->chip_select, | 351 | xfer->rx_buf); |
350 | cs_high); | 352 | else |
353 | mcfqspi_transfer_msg16(mcfqspi, xfer->len / 2, | ||
354 | xfer->tx_buf, | ||
355 | xfer->rx_buf); | ||
356 | mcfqspi_wr_qir(mcfqspi, 0); | ||
357 | |||
358 | if (xfer->delay_usecs) | ||
359 | udelay(xfer->delay_usecs); | ||
360 | if (xfer->cs_change) { | ||
361 | if (!list_is_last(&xfer->transfer_list, | ||
362 | &msg->transfers)) | ||
363 | mcfqspi_cs_deselect(mcfqspi, | ||
364 | spi->chip_select, | ||
365 | cs_high); | ||
366 | } else { | ||
367 | if (list_is_last(&xfer->transfer_list, | ||
368 | &msg->transfers)) | ||
369 | mcfqspi_cs_deselect(mcfqspi, | ||
370 | spi->chip_select, | ||
371 | cs_high); | ||
372 | } | ||
373 | msg->actual_length += xfer->len; | ||
351 | } | 374 | } |
352 | msg->actual_length += t->len; | 375 | msg->status = status; |
353 | } | 376 | msg->complete(msg->context); |
354 | msg->status = status; | ||
355 | spi_finalize_current_message(master); | ||
356 | |||
357 | return status; | ||
358 | 377 | ||
378 | spin_lock_irqsave(&mcfqspi->lock, flags); | ||
379 | } | ||
380 | spin_unlock_irqrestore(&mcfqspi->lock, flags); | ||
359 | } | 381 | } |
360 | 382 | ||
361 | static int mcfqspi_prepare_transfer_hw(struct spi_master *master) | 383 | static int mcfqspi_transfer(struct spi_device *spi, struct spi_message *msg) |
362 | { | ||
363 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | ||
364 | |||
365 | pm_runtime_get_sync(mcfqspi->dev); | ||
366 | |||
367 | return 0; | ||
368 | } | ||
369 | |||
370 | static int mcfqspi_unprepare_transfer_hw(struct spi_master *master) | ||
371 | { | 384 | { |
372 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | 385 | struct mcfqspi *mcfqspi; |
386 | struct spi_transfer *xfer; | ||
387 | unsigned long flags; | ||
388 | |||
389 | mcfqspi = spi_master_get_devdata(spi->master); | ||
390 | |||
391 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
392 | if (xfer->bits_per_word && ((xfer->bits_per_word < 8) | ||
393 | || (xfer->bits_per_word > 16))) { | ||
394 | dev_dbg(&spi->dev, | ||
395 | "%d bits per word is not supported\n", | ||
396 | xfer->bits_per_word); | ||
397 | goto fail; | ||
398 | } | ||
399 | if (xfer->speed_hz) { | ||
400 | u32 real_speed = MCFQSPI_BUSCLK / | ||
401 | mcfqspi_qmr_baud(xfer->speed_hz); | ||
402 | if (real_speed != xfer->speed_hz) | ||
403 | dev_dbg(&spi->dev, | ||
404 | "using speed %d instead of %d\n", | ||
405 | real_speed, xfer->speed_hz); | ||
406 | } | ||
407 | } | ||
408 | msg->status = -EINPROGRESS; | ||
409 | msg->actual_length = 0; | ||
373 | 410 | ||
374 | pm_runtime_put_sync(mcfqspi->dev); | 411 | spin_lock_irqsave(&mcfqspi->lock, flags); |
412 | list_add_tail(&msg->queue, &mcfqspi->msgq); | ||
413 | queue_work(mcfqspi->workq, &mcfqspi->work); | ||
414 | spin_unlock_irqrestore(&mcfqspi->lock, flags); | ||
375 | 415 | ||
376 | return 0; | 416 | return 0; |
417 | fail: | ||
418 | msg->status = -EINVAL; | ||
419 | return -EINVAL; | ||
377 | } | 420 | } |
378 | 421 | ||
379 | static int mcfqspi_setup(struct spi_device *spi) | 422 | static int mcfqspi_setup(struct spi_device *spi) |
@@ -401,7 +444,7 @@ static int mcfqspi_setup(struct spi_device *spi) | |||
401 | return 0; | 444 | return 0; |
402 | } | 445 | } |
403 | 446 | ||
404 | static int mcfqspi_probe(struct platform_device *pdev) | 447 | static int __devinit mcfqspi_probe(struct platform_device *pdev) |
405 | { | 448 | { |
406 | struct spi_master *master; | 449 | struct spi_master *master; |
407 | struct mcfqspi *mcfqspi; | 450 | struct mcfqspi *mcfqspi; |
@@ -444,7 +487,7 @@ static int mcfqspi_probe(struct platform_device *pdev) | |||
444 | goto fail2; | 487 | goto fail2; |
445 | } | 488 | } |
446 | 489 | ||
447 | status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0, | 490 | status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, IRQF_DISABLED, |
448 | pdev->name, mcfqspi); | 491 | pdev->name, mcfqspi); |
449 | if (status) { | 492 | if (status) { |
450 | dev_dbg(&pdev->dev, "request_irq failed\n"); | 493 | dev_dbg(&pdev->dev, "request_irq failed\n"); |
@@ -459,10 +502,21 @@ static int mcfqspi_probe(struct platform_device *pdev) | |||
459 | } | 502 | } |
460 | clk_enable(mcfqspi->clk); | 503 | clk_enable(mcfqspi->clk); |
461 | 504 | ||
505 | mcfqspi->workq = create_singlethread_workqueue(dev_name(master->dev.parent)); | ||
506 | if (!mcfqspi->workq) { | ||
507 | dev_dbg(&pdev->dev, "create_workqueue failed\n"); | ||
508 | status = -ENOMEM; | ||
509 | goto fail4; | ||
510 | } | ||
511 | INIT_WORK(&mcfqspi->work, mcfqspi_work); | ||
512 | spin_lock_init(&mcfqspi->lock); | ||
513 | INIT_LIST_HEAD(&mcfqspi->msgq); | ||
514 | init_waitqueue_head(&mcfqspi->waitq); | ||
515 | |||
462 | pdata = pdev->dev.platform_data; | 516 | pdata = pdev->dev.platform_data; |
463 | if (!pdata) { | 517 | if (!pdata) { |
464 | dev_dbg(&pdev->dev, "platform data is missing\n"); | 518 | dev_dbg(&pdev->dev, "platform data is missing\n"); |
465 | goto fail4; | 519 | goto fail5; |
466 | } | 520 | } |
467 | master->bus_num = pdata->bus_num; | 521 | master->bus_num = pdata->bus_num; |
468 | master->num_chipselect = pdata->num_chipselect; | 522 | master->num_chipselect = pdata->num_chipselect; |
@@ -471,33 +525,28 @@ static int mcfqspi_probe(struct platform_device *pdev) | |||
471 | status = mcfqspi_cs_setup(mcfqspi); | 525 | status = mcfqspi_cs_setup(mcfqspi); |
472 | if (status) { | 526 | if (status) { |
473 | dev_dbg(&pdev->dev, "error initializing cs_control\n"); | 527 | dev_dbg(&pdev->dev, "error initializing cs_control\n"); |
474 | goto fail4; | 528 | goto fail5; |
475 | } | 529 | } |
476 | 530 | ||
477 | init_waitqueue_head(&mcfqspi->waitq); | ||
478 | mcfqspi->dev = &pdev->dev; | ||
479 | |||
480 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; | 531 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; |
481 | master->setup = mcfqspi_setup; | 532 | master->setup = mcfqspi_setup; |
482 | master->transfer_one_message = mcfqspi_transfer_one_message; | 533 | master->transfer = mcfqspi_transfer; |
483 | master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw; | ||
484 | master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw; | ||
485 | 534 | ||
486 | platform_set_drvdata(pdev, master); | 535 | platform_set_drvdata(pdev, master); |
487 | 536 | ||
488 | status = spi_register_master(master); | 537 | status = spi_register_master(master); |
489 | if (status) { | 538 | if (status) { |
490 | dev_dbg(&pdev->dev, "spi_register_master failed\n"); | 539 | dev_dbg(&pdev->dev, "spi_register_master failed\n"); |
491 | goto fail5; | 540 | goto fail6; |
492 | } | 541 | } |
493 | pm_runtime_enable(mcfqspi->dev); | ||
494 | |||
495 | dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); | 542 | dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); |
496 | 543 | ||
497 | return 0; | 544 | return 0; |
498 | 545 | ||
499 | fail5: | 546 | fail6: |
500 | mcfqspi_cs_teardown(mcfqspi); | 547 | mcfqspi_cs_teardown(mcfqspi); |
548 | fail5: | ||
549 | destroy_workqueue(mcfqspi->workq); | ||
501 | fail4: | 550 | fail4: |
502 | clk_disable(mcfqspi->clk); | 551 | clk_disable(mcfqspi->clk); |
503 | clk_put(mcfqspi->clk); | 552 | clk_put(mcfqspi->clk); |
@@ -515,56 +564,32 @@ fail0: | |||
515 | return status; | 564 | return status; |
516 | } | 565 | } |
517 | 566 | ||
518 | static int mcfqspi_remove(struct platform_device *pdev) | 567 | static int __devexit mcfqspi_remove(struct platform_device *pdev) |
519 | { | 568 | { |
520 | struct spi_master *master = platform_get_drvdata(pdev); | 569 | struct spi_master *master = platform_get_drvdata(pdev); |
521 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | 570 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); |
522 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 571 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
523 | 572 | ||
524 | pm_runtime_disable(mcfqspi->dev); | ||
525 | /* disable the hardware (set the baud rate to 0) */ | 573 | /* disable the hardware (set the baud rate to 0) */ |
526 | mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); | 574 | mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); |
527 | 575 | ||
528 | platform_set_drvdata(pdev, NULL); | 576 | platform_set_drvdata(pdev, NULL); |
529 | mcfqspi_cs_teardown(mcfqspi); | 577 | mcfqspi_cs_teardown(mcfqspi); |
578 | destroy_workqueue(mcfqspi->workq); | ||
530 | clk_disable(mcfqspi->clk); | 579 | clk_disable(mcfqspi->clk); |
531 | clk_put(mcfqspi->clk); | 580 | clk_put(mcfqspi->clk); |
532 | free_irq(mcfqspi->irq, mcfqspi); | 581 | free_irq(mcfqspi->irq, mcfqspi); |
533 | iounmap(mcfqspi->iobase); | 582 | iounmap(mcfqspi->iobase); |
534 | release_mem_region(res->start, resource_size(res)); | 583 | release_mem_region(res->start, resource_size(res)); |
535 | spi_unregister_master(master); | 584 | spi_unregister_master(master); |
585 | spi_master_put(master); | ||
536 | 586 | ||
537 | return 0; | 587 | return 0; |
538 | } | 588 | } |
539 | 589 | ||
540 | #ifdef CONFIG_PM_SLEEP | 590 | #ifdef CONFIG_PM |
541 | static int mcfqspi_suspend(struct device *dev) | ||
542 | { | ||
543 | struct spi_master *master = dev_get_drvdata(dev); | ||
544 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | ||
545 | |||
546 | spi_master_suspend(master); | ||
547 | |||
548 | clk_disable(mcfqspi->clk); | ||
549 | |||
550 | return 0; | ||
551 | } | ||
552 | |||
553 | static int mcfqspi_resume(struct device *dev) | ||
554 | { | ||
555 | struct spi_master *master = dev_get_drvdata(dev); | ||
556 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | ||
557 | |||
558 | spi_master_resume(master); | ||
559 | |||
560 | clk_enable(mcfqspi->clk); | ||
561 | |||
562 | return 0; | ||
563 | } | ||
564 | #endif | ||
565 | 591 | ||
566 | #ifdef CONFIG_PM_RUNTIME | 592 | static int mcfqspi_suspend(struct device *dev) |
567 | static int mcfqspi_runtime_suspend(struct device *dev) | ||
568 | { | 593 | { |
569 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); | 594 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); |
570 | 595 | ||
@@ -573,7 +598,7 @@ static int mcfqspi_runtime_suspend(struct device *dev) | |||
573 | return 0; | 598 | return 0; |
574 | } | 599 | } |
575 | 600 | ||
576 | static int mcfqspi_runtime_resume(struct device *dev) | 601 | static int mcfqspi_resume(struct device *dev) |
577 | { | 602 | { |
578 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); | 603 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); |
579 | 604 | ||
@@ -581,22 +606,35 @@ static int mcfqspi_runtime_resume(struct device *dev) | |||
581 | 606 | ||
582 | return 0; | 607 | return 0; |
583 | } | 608 | } |
584 | #endif | ||
585 | 609 | ||
586 | static const struct dev_pm_ops mcfqspi_pm = { | 610 | static struct dev_pm_ops mcfqspi_dev_pm_ops = { |
587 | SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume) | 611 | .suspend = mcfqspi_suspend, |
588 | SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume, | 612 | .resume = mcfqspi_resume, |
589 | NULL) | ||
590 | }; | 613 | }; |
591 | 614 | ||
615 | #define MCFQSPI_DEV_PM_OPS (&mcfqspi_dev_pm_ops) | ||
616 | #else | ||
617 | #define MCFQSPI_DEV_PM_OPS NULL | ||
618 | #endif | ||
619 | |||
592 | static struct platform_driver mcfqspi_driver = { | 620 | static struct platform_driver mcfqspi_driver = { |
593 | .driver.name = DRIVER_NAME, | 621 | .driver.name = DRIVER_NAME, |
594 | .driver.owner = THIS_MODULE, | 622 | .driver.owner = THIS_MODULE, |
595 | .driver.pm = &mcfqspi_pm, | 623 | .driver.pm = MCFQSPI_DEV_PM_OPS, |
596 | .probe = mcfqspi_probe, | 624 | .remove = __devexit_p(mcfqspi_remove), |
597 | .remove = mcfqspi_remove, | ||
598 | }; | 625 | }; |
599 | module_platform_driver(mcfqspi_driver); | 626 | |
627 | static int __init mcfqspi_init(void) | ||
628 | { | ||
629 | return platform_driver_probe(&mcfqspi_driver, mcfqspi_probe); | ||
630 | } | ||
631 | module_init(mcfqspi_init); | ||
632 | |||
633 | static void __exit mcfqspi_exit(void) | ||
634 | { | ||
635 | platform_driver_unregister(&mcfqspi_driver); | ||
636 | } | ||
637 | module_exit(mcfqspi_exit); | ||
600 | 638 | ||
601 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); | 639 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); |
602 | MODULE_DESCRIPTION("Coldfire QSPI Controller Driver"); | 640 | MODULE_DESCRIPTION("Coldfire QSPI Controller Driver"); |
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 13661e129d9..1f0ed8005c9 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c | |||
@@ -25,14 +25,13 @@ | |||
25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
26 | #include <linux/err.h> | 26 | #include <linux/err.h> |
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | #include <linux/dmaengine.h> | ||
29 | #include <linux/dma-mapping.h> | 28 | #include <linux/dma-mapping.h> |
30 | #include <linux/edma.h> | ||
31 | #include <linux/spi/spi.h> | 29 | #include <linux/spi/spi.h> |
32 | #include <linux/spi/spi_bitbang.h> | 30 | #include <linux/spi/spi_bitbang.h> |
33 | #include <linux/slab.h> | 31 | #include <linux/slab.h> |
34 | 32 | ||
35 | #include <linux/platform_data/spi-davinci.h> | 33 | #include <mach/spi.h> |
34 | #include <mach/edma.h> | ||
36 | 35 | ||
37 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | 36 | #define SPI_NO_RESOURCE ((resource_size_t)-1) |
38 | 37 | ||
@@ -114,6 +113,14 @@ | |||
114 | #define SPIDEF 0x4c | 113 | #define SPIDEF 0x4c |
115 | #define SPIFMT0 0x50 | 114 | #define SPIFMT0 0x50 |
116 | 115 | ||
116 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | ||
117 | struct davinci_spi_dma { | ||
118 | int tx_channel; | ||
119 | int rx_channel; | ||
120 | int dummy_param_slot; | ||
121 | enum dma_event_q eventq; | ||
122 | }; | ||
123 | |||
117 | /* SPI Controller driver's private data. */ | 124 | /* SPI Controller driver's private data. */ |
118 | struct davinci_spi { | 125 | struct davinci_spi { |
119 | struct spi_bitbang bitbang; | 126 | struct spi_bitbang bitbang; |
@@ -127,14 +134,11 @@ struct davinci_spi { | |||
127 | 134 | ||
128 | const void *tx; | 135 | const void *tx; |
129 | void *rx; | 136 | void *rx; |
137 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) | ||
138 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; | ||
130 | int rcount; | 139 | int rcount; |
131 | int wcount; | 140 | int wcount; |
132 | 141 | struct davinci_spi_dma dma; | |
133 | struct dma_chan *dma_rx; | ||
134 | struct dma_chan *dma_tx; | ||
135 | int dma_rx_chnum; | ||
136 | int dma_tx_chnum; | ||
137 | |||
138 | struct davinci_spi_platform_data *pdata; | 142 | struct davinci_spi_platform_data *pdata; |
139 | 143 | ||
140 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | 144 | void (*get_rx)(u32 rx_data, struct davinci_spi *); |
@@ -492,23 +496,21 @@ out: | |||
492 | return errors; | 496 | return errors; |
493 | } | 497 | } |
494 | 498 | ||
495 | static void davinci_spi_dma_rx_callback(void *data) | 499 | static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) |
496 | { | 500 | { |
497 | struct davinci_spi *dspi = (struct davinci_spi *)data; | 501 | struct davinci_spi *dspi = data; |
498 | 502 | struct davinci_spi_dma *dma = &dspi->dma; | |
499 | dspi->rcount = 0; | ||
500 | |||
501 | if (!dspi->wcount && !dspi->rcount) | ||
502 | complete(&dspi->done); | ||
503 | } | ||
504 | 503 | ||
505 | static void davinci_spi_dma_tx_callback(void *data) | 504 | edma_stop(lch); |
506 | { | ||
507 | struct davinci_spi *dspi = (struct davinci_spi *)data; | ||
508 | 505 | ||
509 | dspi->wcount = 0; | 506 | if (status == DMA_COMPLETE) { |
507 | if (lch == dma->rx_channel) | ||
508 | dspi->rcount = 0; | ||
509 | if (lch == dma->tx_channel) | ||
510 | dspi->wcount = 0; | ||
511 | } | ||
510 | 512 | ||
511 | if (!dspi->wcount && !dspi->rcount) | 513 | if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) |
512 | complete(&dspi->done); | 514 | complete(&dspi->done); |
513 | } | 515 | } |
514 | 516 | ||
@@ -524,20 +526,20 @@ static void davinci_spi_dma_tx_callback(void *data) | |||
524 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | 526 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
525 | { | 527 | { |
526 | struct davinci_spi *dspi; | 528 | struct davinci_spi *dspi; |
527 | int data_type, ret = -ENOMEM; | 529 | int data_type, ret; |
528 | u32 tx_data, spidat1; | 530 | u32 tx_data, spidat1; |
529 | u32 errors = 0; | 531 | u32 errors = 0; |
530 | struct davinci_spi_config *spicfg; | 532 | struct davinci_spi_config *spicfg; |
531 | struct davinci_spi_platform_data *pdata; | 533 | struct davinci_spi_platform_data *pdata; |
532 | unsigned uninitialized_var(rx_buf_count); | 534 | unsigned uninitialized_var(rx_buf_count); |
533 | void *dummy_buf = NULL; | 535 | struct device *sdev; |
534 | struct scatterlist sg_rx, sg_tx; | ||
535 | 536 | ||
536 | dspi = spi_master_get_devdata(spi->master); | 537 | dspi = spi_master_get_devdata(spi->master); |
537 | pdata = dspi->pdata; | 538 | pdata = dspi->pdata; |
538 | spicfg = (struct davinci_spi_config *)spi->controller_data; | 539 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
539 | if (!spicfg) | 540 | if (!spicfg) |
540 | spicfg = &davinci_spi_default_cfg; | 541 | spicfg = &davinci_spi_default_cfg; |
542 | sdev = dspi->bitbang.master->dev.parent; | ||
541 | 543 | ||
542 | /* convert len to words based on bits_per_word */ | 544 | /* convert len to words based on bits_per_word */ |
543 | data_type = dspi->bytes_per_word[spi->chip_select]; | 545 | data_type = dspi->bytes_per_word[spi->chip_select]; |
@@ -565,83 +567,112 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
565 | spidat1 |= tx_data & 0xFFFF; | 567 | spidat1 |= tx_data & 0xFFFF; |
566 | iowrite32(spidat1, dspi->base + SPIDAT1); | 568 | iowrite32(spidat1, dspi->base + SPIDAT1); |
567 | } else { | 569 | } else { |
568 | struct dma_slave_config dma_rx_conf = { | 570 | struct davinci_spi_dma *dma; |
569 | .direction = DMA_DEV_TO_MEM, | 571 | unsigned long tx_reg, rx_reg; |
570 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | 572 | struct edmacc_param param; |
571 | .src_addr_width = data_type, | 573 | void *rx_buf; |
572 | .src_maxburst = 1, | 574 | int b, c; |
573 | }; | 575 | |
574 | struct dma_slave_config dma_tx_conf = { | 576 | dma = &dspi->dma; |
575 | .direction = DMA_MEM_TO_DEV, | 577 | |
576 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | 578 | tx_reg = (unsigned long)dspi->pbase + SPIDAT1; |
577 | .dst_addr_width = data_type, | 579 | rx_reg = (unsigned long)dspi->pbase + SPIBUF; |
578 | .dst_maxburst = 1, | 580 | |
579 | }; | 581 | /* |
580 | struct dma_async_tx_descriptor *rxdesc; | 582 | * Transmit DMA setup |
581 | struct dma_async_tx_descriptor *txdesc; | 583 | * |
582 | void *buf; | 584 | * If there is transmit data, map the transmit buffer, set it |
583 | 585 | * as the source of data and set the source B index to data | |
584 | dummy_buf = kzalloc(t->len, GFP_KERNEL); | 586 | * size. If there is no transmit data, set the transmit register |
585 | if (!dummy_buf) | 587 | * as the source of data, and set the source B index to zero. |
586 | goto err_alloc_dummy_buf; | 588 | * |
587 | 589 | * The destination is always the transmit register itself. And | |
588 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | 590 | * the destination never increments. |
589 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | 591 | */ |
590 | 592 | ||
591 | sg_init_table(&sg_rx, 1); | 593 | if (t->tx_buf) { |
592 | if (!t->rx_buf) | 594 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, |
593 | buf = dummy_buf; | 595 | t->len, DMA_TO_DEVICE); |
594 | else | 596 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
595 | buf = t->rx_buf; | 597 | dev_dbg(sdev, "Unable to DMA map %d bytes" |
596 | t->rx_dma = dma_map_single(&spi->dev, buf, | 598 | "TX buffer\n", t->len); |
597 | t->len, DMA_FROM_DEVICE); | 599 | return -ENOMEM; |
598 | if (!t->rx_dma) { | 600 | } |
599 | ret = -EFAULT; | ||
600 | goto err_rx_map; | ||
601 | } | 601 | } |
602 | sg_dma_address(&sg_rx) = t->rx_dma; | ||
603 | sg_dma_len(&sg_rx) = t->len; | ||
604 | 602 | ||
605 | sg_init_table(&sg_tx, 1); | 603 | /* |
606 | if (!t->tx_buf) | 604 | * If number of words is greater than 65535, then we need |
607 | buf = dummy_buf; | 605 | * to configure a 3 dimension transfer. Use the BCNTRLD |
606 | * feature to allow for transfers that aren't even multiples | ||
607 | * of 65535 (or any other possible b size) by first transferring | ||
608 | * the remainder amount then grabbing the next N blocks of | ||
609 | * 65535 words. | ||
610 | */ | ||
611 | |||
612 | c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ | ||
613 | b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ | ||
614 | if (b) | ||
615 | c++; | ||
608 | else | 616 | else |
609 | buf = (void *)t->tx_buf; | 617 | b = SZ_64K - 1; |
610 | t->tx_dma = dma_map_single(&spi->dev, buf, | 618 | |
611 | t->len, DMA_FROM_DEVICE); | 619 | param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); |
612 | if (!t->tx_dma) { | 620 | param.src = t->tx_buf ? t->tx_dma : tx_reg; |
613 | ret = -EFAULT; | 621 | param.a_b_cnt = b << 16 | data_type; |
614 | goto err_tx_map; | 622 | param.dst = tx_reg; |
623 | param.src_dst_bidx = t->tx_buf ? data_type : 0; | ||
624 | param.link_bcntrld = 0xffffffff; | ||
625 | param.src_dst_cidx = t->tx_buf ? data_type : 0; | ||
626 | param.ccnt = c; | ||
627 | edma_write_slot(dma->tx_channel, ¶m); | ||
628 | edma_link(dma->tx_channel, dma->dummy_param_slot); | ||
629 | |||
630 | /* | ||
631 | * Receive DMA setup | ||
632 | * | ||
633 | * If there is receive buffer, use it to receive data. If there | ||
634 | * is none provided, use a temporary receive buffer. Set the | ||
635 | * destination B index to 0 so effectively only one byte is used | ||
636 | * in the temporary buffer (address does not increment). | ||
637 | * | ||
638 | * The source of receive data is the receive data register. The | ||
639 | * source address never increments. | ||
640 | */ | ||
641 | |||
642 | if (t->rx_buf) { | ||
643 | rx_buf = t->rx_buf; | ||
644 | rx_buf_count = t->len; | ||
645 | } else { | ||
646 | rx_buf = dspi->rx_tmp_buf; | ||
647 | rx_buf_count = sizeof(dspi->rx_tmp_buf); | ||
615 | } | 648 | } |
616 | sg_dma_address(&sg_tx) = t->tx_dma; | ||
617 | sg_dma_len(&sg_tx) = t->len; | ||
618 | |||
619 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, | ||
620 | &sg_rx, 1, DMA_DEV_TO_MEM, | ||
621 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
622 | if (!rxdesc) | ||
623 | goto err_desc; | ||
624 | |||
625 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, | ||
626 | &sg_tx, 1, DMA_MEM_TO_DEV, | ||
627 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
628 | if (!txdesc) | ||
629 | goto err_desc; | ||
630 | |||
631 | rxdesc->callback = davinci_spi_dma_rx_callback; | ||
632 | rxdesc->callback_param = (void *)dspi; | ||
633 | txdesc->callback = davinci_spi_dma_tx_callback; | ||
634 | txdesc->callback_param = (void *)dspi; | ||
635 | 649 | ||
636 | if (pdata->cshold_bug) | 650 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, |
637 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); | 651 | DMA_FROM_DEVICE); |
652 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | ||
653 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | ||
654 | rx_buf_count); | ||
655 | if (t->tx_buf) | ||
656 | dma_unmap_single(NULL, t->tx_dma, t->len, | ||
657 | DMA_TO_DEVICE); | ||
658 | return -ENOMEM; | ||
659 | } | ||
638 | 660 | ||
639 | dmaengine_submit(rxdesc); | 661 | param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); |
640 | dmaengine_submit(txdesc); | 662 | param.src = rx_reg; |
663 | param.a_b_cnt = b << 16 | data_type; | ||
664 | param.dst = t->rx_dma; | ||
665 | param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; | ||
666 | param.link_bcntrld = 0xffffffff; | ||
667 | param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16; | ||
668 | param.ccnt = c; | ||
669 | edma_write_slot(dma->rx_channel, ¶m); | ||
641 | 670 | ||
642 | dma_async_issue_pending(dspi->dma_rx); | 671 | if (pdata->cshold_bug) |
643 | dma_async_issue_pending(dspi->dma_tx); | 672 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
644 | 673 | ||
674 | edma_start(dma->rx_channel); | ||
675 | edma_start(dma->tx_channel); | ||
645 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); | 676 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
646 | } | 677 | } |
647 | 678 | ||
@@ -659,13 +690,15 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
659 | 690 | ||
660 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); | 691 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
661 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { | 692 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
662 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); | ||
663 | 693 | ||
664 | dma_unmap_single(&spi->dev, t->rx_dma, | 694 | if (t->tx_buf) |
665 | t->len, DMA_FROM_DEVICE); | 695 | dma_unmap_single(NULL, t->tx_dma, t->len, |
666 | dma_unmap_single(&spi->dev, t->tx_dma, | 696 | DMA_TO_DEVICE); |
667 | t->len, DMA_TO_DEVICE); | 697 | |
668 | kfree(dummy_buf); | 698 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, |
699 | DMA_FROM_DEVICE); | ||
700 | |||
701 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); | ||
669 | } | 702 | } |
670 | 703 | ||
671 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | 704 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
@@ -683,20 +716,11 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
683 | } | 716 | } |
684 | 717 | ||
685 | if (dspi->rcount != 0 || dspi->wcount != 0) { | 718 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
686 | dev_err(&spi->dev, "SPI data transfer error\n"); | 719 | dev_err(sdev, "SPI data transfer error\n"); |
687 | return -EIO; | 720 | return -EIO; |
688 | } | 721 | } |
689 | 722 | ||
690 | return t->len; | 723 | return t->len; |
691 | |||
692 | err_desc: | ||
693 | dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); | ||
694 | err_tx_map: | ||
695 | dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); | ||
696 | err_rx_map: | ||
697 | kfree(dummy_buf); | ||
698 | err_alloc_dummy_buf: | ||
699 | return ret; | ||
700 | } | 724 | } |
701 | 725 | ||
702 | /** | 726 | /** |
@@ -727,33 +751,39 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *data) | |||
727 | 751 | ||
728 | static int davinci_spi_request_dma(struct davinci_spi *dspi) | 752 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
729 | { | 753 | { |
730 | dma_cap_mask_t mask; | ||
731 | struct device *sdev = dspi->bitbang.master->dev.parent; | ||
732 | int r; | 754 | int r; |
755 | struct davinci_spi_dma *dma = &dspi->dma; | ||
733 | 756 | ||
734 | dma_cap_zero(mask); | 757 | r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, |
735 | dma_cap_set(DMA_SLAVE, mask); | 758 | dma->eventq); |
736 | 759 | if (r < 0) { | |
737 | dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, | 760 | pr_err("Unable to request DMA channel for SPI RX\n"); |
738 | &dspi->dma_rx_chnum); | 761 | r = -EAGAIN; |
739 | if (!dspi->dma_rx) { | ||
740 | dev_err(sdev, "request RX DMA channel failed\n"); | ||
741 | r = -ENODEV; | ||
742 | goto rx_dma_failed; | 762 | goto rx_dma_failed; |
743 | } | 763 | } |
744 | 764 | ||
745 | dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, | 765 | r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, |
746 | &dspi->dma_tx_chnum); | 766 | dma->eventq); |
747 | if (!dspi->dma_tx) { | 767 | if (r < 0) { |
748 | dev_err(sdev, "request TX DMA channel failed\n"); | 768 | pr_err("Unable to request DMA channel for SPI TX\n"); |
749 | r = -ENODEV; | 769 | r = -EAGAIN; |
750 | goto tx_dma_failed; | 770 | goto tx_dma_failed; |
751 | } | 771 | } |
752 | 772 | ||
753 | return 0; | 773 | r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); |
774 | if (r < 0) { | ||
775 | pr_err("Unable to request SPI TX DMA param slot\n"); | ||
776 | r = -EAGAIN; | ||
777 | goto param_failed; | ||
778 | } | ||
779 | dma->dummy_param_slot = r; | ||
780 | edma_link(dma->dummy_param_slot, dma->dummy_param_slot); | ||
754 | 781 | ||
782 | return 0; | ||
783 | param_failed: | ||
784 | edma_free_channel(dma->tx_channel); | ||
755 | tx_dma_failed: | 785 | tx_dma_failed: |
756 | dma_release_channel(dspi->dma_rx); | 786 | edma_free_channel(dma->rx_channel); |
757 | rx_dma_failed: | 787 | rx_dma_failed: |
758 | return r; | 788 | return r; |
759 | } | 789 | } |
@@ -868,8 +898,9 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
868 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; | 898 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
869 | if (dma_rx_chan != SPI_NO_RESOURCE && | 899 | if (dma_rx_chan != SPI_NO_RESOURCE && |
870 | dma_tx_chan != SPI_NO_RESOURCE) { | 900 | dma_tx_chan != SPI_NO_RESOURCE) { |
871 | dspi->dma_rx_chnum = dma_rx_chan; | 901 | dspi->dma.rx_channel = dma_rx_chan; |
872 | dspi->dma_tx_chnum = dma_tx_chan; | 902 | dspi->dma.tx_channel = dma_tx_chan; |
903 | dspi->dma.eventq = pdata->dma_event_q; | ||
873 | 904 | ||
874 | ret = davinci_spi_request_dma(dspi); | 905 | ret = davinci_spi_request_dma(dspi); |
875 | if (ret) | 906 | if (ret) |
@@ -924,8 +955,9 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
924 | return ret; | 955 | return ret; |
925 | 956 | ||
926 | free_dma: | 957 | free_dma: |
927 | dma_release_channel(dspi->dma_rx); | 958 | edma_free_channel(dspi->dma.tx_channel); |
928 | dma_release_channel(dspi->dma_tx); | 959 | edma_free_channel(dspi->dma.rx_channel); |
960 | edma_free_slot(dspi->dma.dummy_param_slot); | ||
929 | free_clk: | 961 | free_clk: |
930 | clk_disable(dspi->clk); | 962 | clk_disable(dspi->clk); |
931 | clk_put(dspi->clk); | 963 | clk_put(dspi->clk); |
@@ -952,7 +984,7 @@ err: | |||
952 | * It will also call spi_bitbang_stop to destroy the work queue which was | 984 | * It will also call spi_bitbang_stop to destroy the work queue which was |
953 | * created by spi_bitbang_start. | 985 | * created by spi_bitbang_start. |
954 | */ | 986 | */ |
955 | static int davinci_spi_remove(struct platform_device *pdev) | 987 | static int __exit davinci_spi_remove(struct platform_device *pdev) |
956 | { | 988 | { |
957 | struct davinci_spi *dspi; | 989 | struct davinci_spi *dspi; |
958 | struct spi_master *master; | 990 | struct spi_master *master; |
@@ -979,10 +1011,20 @@ static struct platform_driver davinci_spi_driver = { | |||
979 | .name = "spi_davinci", | 1011 | .name = "spi_davinci", |
980 | .owner = THIS_MODULE, | 1012 | .owner = THIS_MODULE, |
981 | }, | 1013 | }, |
982 | .probe = davinci_spi_probe, | 1014 | .remove = __exit_p(davinci_spi_remove), |
983 | .remove = davinci_spi_remove, | ||
984 | }; | 1015 | }; |
985 | module_platform_driver(davinci_spi_driver); | 1016 | |
1017 | static int __init davinci_spi_init(void) | ||
1018 | { | ||
1019 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | ||
1020 | } | ||
1021 | module_init(davinci_spi_init); | ||
1022 | |||
1023 | static void __exit davinci_spi_exit(void) | ||
1024 | { | ||
1025 | platform_driver_unregister(&davinci_spi_driver); | ||
1026 | } | ||
1027 | module_exit(davinci_spi_exit); | ||
986 | 1028 | ||
987 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | 1029 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); |
988 | MODULE_LICENSE("GPL"); | 1030 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index b9f0192758d..130e55537db 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | #include <linux/slab.h> | 23 | #include <linux/slab.h> |
24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
25 | #include <linux/types.h> | ||
26 | 25 | ||
27 | #include "spi-dw.h" | 26 | #include "spi-dw.h" |
28 | 27 | ||
@@ -117,13 +116,13 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) | |||
117 | /* 1. setup DMA related registers */ | 116 | /* 1. setup DMA related registers */ |
118 | if (cs_change) { | 117 | if (cs_change) { |
119 | spi_enable_chip(dws, 0); | 118 | spi_enable_chip(dws, 0); |
120 | dw_writew(dws, DW_SPI_DMARDLR, 0xf); | 119 | dw_writew(dws, dmardlr, 0xf); |
121 | dw_writew(dws, DW_SPI_DMATDLR, 0x10); | 120 | dw_writew(dws, dmatdlr, 0x10); |
122 | if (dws->tx_dma) | 121 | if (dws->tx_dma) |
123 | dma_ctrl |= 0x2; | 122 | dma_ctrl |= 0x2; |
124 | if (dws->rx_dma) | 123 | if (dws->rx_dma) |
125 | dma_ctrl |= 0x1; | 124 | dma_ctrl |= 0x1; |
126 | dw_writew(dws, DW_SPI_DMACR, dma_ctrl); | 125 | dw_writew(dws, dmacr, dma_ctrl); |
127 | spi_enable_chip(dws, 1); | 126 | spi_enable_chip(dws, 1); |
128 | } | 127 | } |
129 | 128 | ||
@@ -132,12 +131,11 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) | |||
132 | rxchan = dws->rxchan; | 131 | rxchan = dws->rxchan; |
133 | 132 | ||
134 | /* 2. Prepare the TX dma transfer */ | 133 | /* 2. Prepare the TX dma transfer */ |
135 | txconf.direction = DMA_MEM_TO_DEV; | 134 | txconf.direction = DMA_TO_DEVICE; |
136 | txconf.dst_addr = dws->dma_addr; | 135 | txconf.dst_addr = dws->dma_addr; |
137 | txconf.dst_maxburst = LNW_DMA_MSIZE_16; | 136 | txconf.dst_maxburst = LNW_DMA_MSIZE_16; |
138 | txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | 137 | txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
139 | txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | 138 | txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
140 | txconf.device_fc = false; | ||
141 | 139 | ||
142 | txchan->device->device_control(txchan, DMA_SLAVE_CONFIG, | 140 | txchan->device->device_control(txchan, DMA_SLAVE_CONFIG, |
143 | (unsigned long) &txconf); | 141 | (unsigned long) &txconf); |
@@ -146,21 +144,20 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) | |||
146 | dws->tx_sgl.dma_address = dws->tx_dma; | 144 | dws->tx_sgl.dma_address = dws->tx_dma; |
147 | dws->tx_sgl.length = dws->len; | 145 | dws->tx_sgl.length = dws->len; |
148 | 146 | ||
149 | txdesc = dmaengine_prep_slave_sg(txchan, | 147 | txdesc = txchan->device->device_prep_slave_sg(txchan, |
150 | &dws->tx_sgl, | 148 | &dws->tx_sgl, |
151 | 1, | 149 | 1, |
152 | DMA_MEM_TO_DEV, | 150 | DMA_TO_DEVICE, |
153 | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP); | 151 | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP); |
154 | txdesc->callback = dw_spi_dma_done; | 152 | txdesc->callback = dw_spi_dma_done; |
155 | txdesc->callback_param = dws; | 153 | txdesc->callback_param = dws; |
156 | 154 | ||
157 | /* 3. Prepare the RX dma transfer */ | 155 | /* 3. Prepare the RX dma transfer */ |
158 | rxconf.direction = DMA_DEV_TO_MEM; | 156 | rxconf.direction = DMA_FROM_DEVICE; |
159 | rxconf.src_addr = dws->dma_addr; | 157 | rxconf.src_addr = dws->dma_addr; |
160 | rxconf.src_maxburst = LNW_DMA_MSIZE_16; | 158 | rxconf.src_maxburst = LNW_DMA_MSIZE_16; |
161 | rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | 159 | rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
162 | rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | 160 | rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
163 | rxconf.device_fc = false; | ||
164 | 161 | ||
165 | rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG, | 162 | rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG, |
166 | (unsigned long) &rxconf); | 163 | (unsigned long) &rxconf); |
@@ -169,10 +166,10 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) | |||
169 | dws->rx_sgl.dma_address = dws->rx_dma; | 166 | dws->rx_sgl.dma_address = dws->rx_dma; |
170 | dws->rx_sgl.length = dws->len; | 167 | dws->rx_sgl.length = dws->len; |
171 | 168 | ||
172 | rxdesc = dmaengine_prep_slave_sg(rxchan, | 169 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, |
173 | &dws->rx_sgl, | 170 | &dws->rx_sgl, |
174 | 1, | 171 | 1, |
175 | DMA_DEV_TO_MEM, | 172 | DMA_FROM_DEVICE, |
176 | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP); | 173 | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP); |
177 | rxdesc->callback = dw_spi_dma_done; | 174 | rxdesc->callback = dw_spi_dma_done; |
178 | rxdesc->callback_param = dws; | 175 | rxdesc->callback_param = dws; |
@@ -203,8 +200,7 @@ static struct dw_spi_dma_ops mid_dma_ops = { | |||
203 | 200 | ||
204 | int dw_spi_mid_init(struct dw_spi *dws) | 201 | int dw_spi_mid_init(struct dw_spi *dws) |
205 | { | 202 | { |
206 | void __iomem *clk_reg; | 203 | u32 *clk_reg, clk_cdiv; |
207 | u32 clk_cdiv; | ||
208 | 204 | ||
209 | clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16); | 205 | clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16); |
210 | if (!clk_reg) | 206 | if (!clk_reg) |
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 4a6d5c9057a..34eb66501db 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/slab.h> | 15 | #include <linux/slab.h> |
16 | #include <linux/spi/spi.h> | 16 | #include <linux/spi/spi.h> |
17 | #include <linux/scatterlist.h> | 17 | #include <linux/scatterlist.h> |
18 | #include <linux/module.h> | ||
19 | 18 | ||
20 | #include "spi-dw.h" | 19 | #include "spi-dw.h" |
21 | 20 | ||
@@ -26,7 +25,7 @@ struct dw_spi_mmio { | |||
26 | struct clk *clk; | 25 | struct clk *clk; |
27 | }; | 26 | }; |
28 | 27 | ||
29 | static int dw_spi_mmio_probe(struct platform_device *pdev) | 28 | static int __devinit dw_spi_mmio_probe(struct platform_device *pdev) |
30 | { | 29 | { |
31 | struct dw_spi_mmio *dwsmmio; | 30 | struct dw_spi_mmio *dwsmmio; |
32 | struct dw_spi *dws; | 31 | struct dw_spi *dws; |
@@ -106,7 +105,7 @@ err_end: | |||
106 | return ret; | 105 | return ret; |
107 | } | 106 | } |
108 | 107 | ||
109 | static int dw_spi_mmio_remove(struct platform_device *pdev) | 108 | static int __devexit dw_spi_mmio_remove(struct platform_device *pdev) |
110 | { | 109 | { |
111 | struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); | 110 | struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); |
112 | struct resource *mem; | 111 | struct resource *mem; |
@@ -128,14 +127,24 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) | |||
128 | } | 127 | } |
129 | 128 | ||
130 | static struct platform_driver dw_spi_mmio_driver = { | 129 | static struct platform_driver dw_spi_mmio_driver = { |
131 | .probe = dw_spi_mmio_probe, | 130 | .remove = __devexit_p(dw_spi_mmio_remove), |
132 | .remove = dw_spi_mmio_remove, | ||
133 | .driver = { | 131 | .driver = { |
134 | .name = DRIVER_NAME, | 132 | .name = DRIVER_NAME, |
135 | .owner = THIS_MODULE, | 133 | .owner = THIS_MODULE, |
136 | }, | 134 | }, |
137 | }; | 135 | }; |
138 | module_platform_driver(dw_spi_mmio_driver); | 136 | |
137 | static int __init dw_spi_mmio_init(void) | ||
138 | { | ||
139 | return platform_driver_probe(&dw_spi_mmio_driver, dw_spi_mmio_probe); | ||
140 | } | ||
141 | module_init(dw_spi_mmio_init); | ||
142 | |||
143 | static void __exit dw_spi_mmio_exit(void) | ||
144 | { | ||
145 | platform_driver_unregister(&dw_spi_mmio_driver); | ||
146 | } | ||
147 | module_exit(dw_spi_mmio_exit); | ||
139 | 148 | ||
140 | MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>"); | 149 | MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>"); |
141 | MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core"); | 150 | MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core"); |
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c index 6055c8d9fdd..c5f37f03ac8 100644 --- a/drivers/spi/spi-dw-pci.c +++ b/drivers/spi/spi-dw-pci.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/pci.h> | 21 | #include <linux/pci.h> |
22 | #include <linux/slab.h> | 22 | #include <linux/slab.h> |
23 | #include <linux/spi/spi.h> | 23 | #include <linux/spi/spi.h> |
24 | #include <linux/module.h> | ||
25 | 24 | ||
26 | #include "spi-dw.h" | 25 | #include "spi-dw.h" |
27 | 26 | ||
@@ -32,7 +31,7 @@ struct dw_spi_pci { | |||
32 | struct dw_spi dws; | 31 | struct dw_spi dws; |
33 | }; | 32 | }; |
34 | 33 | ||
35 | static int spi_pci_probe(struct pci_dev *pdev, | 34 | static int __devinit spi_pci_probe(struct pci_dev *pdev, |
36 | const struct pci_device_id *ent) | 35 | const struct pci_device_id *ent) |
37 | { | 36 | { |
38 | struct dw_spi_pci *dwpci; | 37 | struct dw_spi_pci *dwpci; |
@@ -105,7 +104,7 @@ err_disable: | |||
105 | return ret; | 104 | return ret; |
106 | } | 105 | } |
107 | 106 | ||
108 | static void spi_pci_remove(struct pci_dev *pdev) | 107 | static void __devexit spi_pci_remove(struct pci_dev *pdev) |
109 | { | 108 | { |
110 | struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); | 109 | struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); |
111 | 110 | ||
@@ -149,7 +148,7 @@ static int spi_resume(struct pci_dev *pdev) | |||
149 | #define spi_resume NULL | 148 | #define spi_resume NULL |
150 | #endif | 149 | #endif |
151 | 150 | ||
152 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { | 151 | static const struct pci_device_id pci_ids[] __devinitdata = { |
153 | /* Intel MID platform SPI controller 0 */ | 152 | /* Intel MID platform SPI controller 0 */ |
154 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) }, | 153 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) }, |
155 | {}, | 154 | {}, |
@@ -159,12 +158,23 @@ static struct pci_driver dw_spi_driver = { | |||
159 | .name = DRIVER_NAME, | 158 | .name = DRIVER_NAME, |
160 | .id_table = pci_ids, | 159 | .id_table = pci_ids, |
161 | .probe = spi_pci_probe, | 160 | .probe = spi_pci_probe, |
162 | .remove = spi_pci_remove, | 161 | .remove = __devexit_p(spi_pci_remove), |
163 | .suspend = spi_suspend, | 162 | .suspend = spi_suspend, |
164 | .resume = spi_resume, | 163 | .resume = spi_resume, |
165 | }; | 164 | }; |
166 | 165 | ||
167 | module_pci_driver(dw_spi_driver); | 166 | static int __init mrst_spi_init(void) |
167 | { | ||
168 | return pci_register_driver(&dw_spi_driver); | ||
169 | } | ||
170 | |||
171 | static void __exit mrst_spi_exit(void) | ||
172 | { | ||
173 | pci_unregister_driver(&dw_spi_driver); | ||
174 | } | ||
175 | |||
176 | module_init(mrst_spi_init); | ||
177 | module_exit(mrst_spi_exit); | ||
168 | 178 | ||
169 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | 179 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); |
170 | MODULE_DESCRIPTION("PCI interface driver for DW SPI Core"); | 180 | MODULE_DESCRIPTION("PCI interface driver for DW SPI Core"); |
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index c1abc06899e..857cd30b44b 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c | |||
@@ -19,7 +19,6 @@ | |||
19 | 19 | ||
20 | #include <linux/dma-mapping.h> | 20 | #include <linux/dma-mapping.h> |
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | #include <linux/module.h> | ||
23 | #include <linux/highmem.h> | 22 | #include <linux/highmem.h> |
24 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
25 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
@@ -63,6 +62,12 @@ struct chip_data { | |||
63 | }; | 62 | }; |
64 | 63 | ||
65 | #ifdef CONFIG_DEBUG_FS | 64 | #ifdef CONFIG_DEBUG_FS |
65 | static int spi_show_regs_open(struct inode *inode, struct file *file) | ||
66 | { | ||
67 | file->private_data = inode->i_private; | ||
68 | return 0; | ||
69 | } | ||
70 | |||
66 | #define SPI_REGS_BUFSIZE 1024 | 71 | #define SPI_REGS_BUFSIZE 1024 |
67 | static ssize_t spi_show_regs(struct file *file, char __user *user_buf, | 72 | static ssize_t spi_show_regs(struct file *file, char __user *user_buf, |
68 | size_t count, loff_t *ppos) | 73 | size_t count, loff_t *ppos) |
@@ -83,35 +88,35 @@ static ssize_t spi_show_regs(struct file *file, char __user *user_buf, | |||
83 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 88 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
84 | "=================================\n"); | 89 | "=================================\n"); |
85 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 90 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
86 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); | 91 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0)); |
87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 92 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
88 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); | 93 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1)); |
89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 94 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
90 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); | 95 | "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr)); |
91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 96 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
92 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); | 97 | "SER: \t\t0x%08x\n", dw_readl(dws, ser)); |
93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 98 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
94 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); | 99 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr)); |
95 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 100 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
96 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); | 101 | "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr)); |
97 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 102 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
98 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); | 103 | "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr)); |
99 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 104 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
100 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); | 105 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr)); |
101 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 106 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
102 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); | 107 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr)); |
103 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 108 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
104 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); | 109 | "SR: \t\t0x%08x\n", dw_readl(dws, sr)); |
105 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 110 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
106 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); | 111 | "IMR: \t\t0x%08x\n", dw_readl(dws, imr)); |
107 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 112 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
108 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); | 113 | "ISR: \t\t0x%08x\n", dw_readl(dws, isr)); |
109 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 114 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
110 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); | 115 | "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr)); |
111 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 116 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
112 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); | 117 | "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr)); |
113 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 118 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
114 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); | 119 | "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr)); |
115 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | 120 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
116 | "=================================\n"); | 121 | "=================================\n"); |
117 | 122 | ||
@@ -122,7 +127,7 @@ static ssize_t spi_show_regs(struct file *file, char __user *user_buf, | |||
122 | 127 | ||
123 | static const struct file_operations mrst_spi_regs_ops = { | 128 | static const struct file_operations mrst_spi_regs_ops = { |
124 | .owner = THIS_MODULE, | 129 | .owner = THIS_MODULE, |
125 | .open = simple_open, | 130 | .open = spi_show_regs_open, |
126 | .read = spi_show_regs, | 131 | .read = spi_show_regs, |
127 | .llseek = default_llseek, | 132 | .llseek = default_llseek, |
128 | }; | 133 | }; |
@@ -161,7 +166,7 @@ static inline u32 tx_max(struct dw_spi *dws) | |||
161 | u32 tx_left, tx_room, rxtx_gap; | 166 | u32 tx_left, tx_room, rxtx_gap; |
162 | 167 | ||
163 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | 168 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; |
164 | tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR); | 169 | tx_room = dws->fifo_len - dw_readw(dws, txflr); |
165 | 170 | ||
166 | /* | 171 | /* |
167 | * Another concern is about the tx/rx mismatch, we | 172 | * Another concern is about the tx/rx mismatch, we |
@@ -182,7 +187,7 @@ static inline u32 rx_max(struct dw_spi *dws) | |||
182 | { | 187 | { |
183 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | 188 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; |
184 | 189 | ||
185 | return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR)); | 190 | return min(rx_left, (u32)dw_readw(dws, rxflr)); |
186 | } | 191 | } |
187 | 192 | ||
188 | static void dw_writer(struct dw_spi *dws) | 193 | static void dw_writer(struct dw_spi *dws) |
@@ -198,7 +203,7 @@ static void dw_writer(struct dw_spi *dws) | |||
198 | else | 203 | else |
199 | txw = *(u16 *)(dws->tx); | 204 | txw = *(u16 *)(dws->tx); |
200 | } | 205 | } |
201 | dw_writew(dws, DW_SPI_DR, txw); | 206 | dw_writew(dws, dr, txw); |
202 | dws->tx += dws->n_bytes; | 207 | dws->tx += dws->n_bytes; |
203 | } | 208 | } |
204 | } | 209 | } |
@@ -209,7 +214,7 @@ static void dw_reader(struct dw_spi *dws) | |||
209 | u16 rxw; | 214 | u16 rxw; |
210 | 215 | ||
211 | while (max--) { | 216 | while (max--) { |
212 | rxw = dw_readw(dws, DW_SPI_DR); | 217 | rxw = dw_readw(dws, dr); |
213 | /* Care rx only if the transfer's original "rx" is not null */ | 218 | /* Care rx only if the transfer's original "rx" is not null */ |
214 | if (dws->rx_end - dws->len) { | 219 | if (dws->rx_end - dws->len) { |
215 | if (dws->n_bytes == 1) | 220 | if (dws->n_bytes == 1) |
@@ -317,13 +322,13 @@ EXPORT_SYMBOL_GPL(dw_spi_xfer_done); | |||
317 | 322 | ||
318 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) | 323 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
319 | { | 324 | { |
320 | u16 irq_status = dw_readw(dws, DW_SPI_ISR); | 325 | u16 irq_status = dw_readw(dws, isr); |
321 | 326 | ||
322 | /* Error handling */ | 327 | /* Error handling */ |
323 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | 328 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { |
324 | dw_readw(dws, DW_SPI_TXOICR); | 329 | dw_readw(dws, txoicr); |
325 | dw_readw(dws, DW_SPI_RXOICR); | 330 | dw_readw(dws, rxoicr); |
326 | dw_readw(dws, DW_SPI_RXUICR); | 331 | dw_readw(dws, rxuicr); |
327 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); | 332 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
328 | return IRQ_HANDLED; | 333 | return IRQ_HANDLED; |
329 | } | 334 | } |
@@ -347,7 +352,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws) | |||
347 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | 352 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) |
348 | { | 353 | { |
349 | struct dw_spi *dws = dev_id; | 354 | struct dw_spi *dws = dev_id; |
350 | u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f; | 355 | u16 irq_status = dw_readw(dws, isr) & 0x3f; |
351 | 356 | ||
352 | if (!irq_status) | 357 | if (!irq_status) |
353 | return IRQ_NONE; | 358 | return IRQ_NONE; |
@@ -515,11 +520,11 @@ static void pump_transfers(unsigned long data) | |||
515 | * 2. clk_div is changed | 520 | * 2. clk_div is changed |
516 | * 3. control value changes | 521 | * 3. control value changes |
517 | */ | 522 | */ |
518 | if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) { | 523 | if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) { |
519 | spi_enable_chip(dws, 0); | 524 | spi_enable_chip(dws, 0); |
520 | 525 | ||
521 | if (dw_readw(dws, DW_SPI_CTRL0) != cr0) | 526 | if (dw_readw(dws, ctrl0) != cr0) |
522 | dw_writew(dws, DW_SPI_CTRL0, cr0); | 527 | dw_writew(dws, ctrl0, cr0); |
523 | 528 | ||
524 | spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); | 529 | spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); |
525 | spi_chip_sel(dws, spi->chip_select); | 530 | spi_chip_sel(dws, spi->chip_select); |
@@ -529,7 +534,7 @@ static void pump_transfers(unsigned long data) | |||
529 | if (imask) | 534 | if (imask) |
530 | spi_umask_intr(dws, imask); | 535 | spi_umask_intr(dws, imask); |
531 | if (txint_level) | 536 | if (txint_level) |
532 | dw_writew(dws, DW_SPI_TXFLTR, txint_level); | 537 | dw_writew(dws, txfltr, txint_level); |
533 | 538 | ||
534 | spi_enable_chip(dws, 1); | 539 | spi_enable_chip(dws, 1); |
535 | if (cs_change) | 540 | if (cs_change) |
@@ -696,7 +701,7 @@ static void dw_spi_cleanup(struct spi_device *spi) | |||
696 | kfree(chip); | 701 | kfree(chip); |
697 | } | 702 | } |
698 | 703 | ||
699 | static int init_queue(struct dw_spi *dws) | 704 | static int __devinit init_queue(struct dw_spi *dws) |
700 | { | 705 | { |
701 | INIT_LIST_HEAD(&dws->queue); | 706 | INIT_LIST_HEAD(&dws->queue); |
702 | spin_lock_init(&dws->lock); | 707 | spin_lock_init(&dws->lock); |
@@ -785,17 +790,17 @@ static void spi_hw_init(struct dw_spi *dws) | |||
785 | if (!dws->fifo_len) { | 790 | if (!dws->fifo_len) { |
786 | u32 fifo; | 791 | u32 fifo; |
787 | for (fifo = 2; fifo <= 257; fifo++) { | 792 | for (fifo = 2; fifo <= 257; fifo++) { |
788 | dw_writew(dws, DW_SPI_TXFLTR, fifo); | 793 | dw_writew(dws, txfltr, fifo); |
789 | if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) | 794 | if (fifo != dw_readw(dws, txfltr)) |
790 | break; | 795 | break; |
791 | } | 796 | } |
792 | 797 | ||
793 | dws->fifo_len = (fifo == 257) ? 0 : fifo; | 798 | dws->fifo_len = (fifo == 257) ? 0 : fifo; |
794 | dw_writew(dws, DW_SPI_TXFLTR, 0); | 799 | dw_writew(dws, txfltr, 0); |
795 | } | 800 | } |
796 | } | 801 | } |
797 | 802 | ||
798 | int dw_spi_add_host(struct dw_spi *dws) | 803 | int __devinit dw_spi_add_host(struct dw_spi *dws) |
799 | { | 804 | { |
800 | struct spi_master *master; | 805 | struct spi_master *master; |
801 | int ret; | 806 | int ret; |
@@ -877,7 +882,7 @@ exit: | |||
877 | } | 882 | } |
878 | EXPORT_SYMBOL_GPL(dw_spi_add_host); | 883 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
879 | 884 | ||
880 | void dw_spi_remove_host(struct dw_spi *dws) | 885 | void __devexit dw_spi_remove_host(struct dw_spi *dws) |
881 | { | 886 | { |
882 | int status = 0; | 887 | int status = 0; |
883 | 888 | ||
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9c57c078031..8b7b07bf6c3 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h | |||
@@ -4,33 +4,6 @@ | |||
4 | #include <linux/io.h> | 4 | #include <linux/io.h> |
5 | #include <linux/scatterlist.h> | 5 | #include <linux/scatterlist.h> |
6 | 6 | ||
7 | /* Register offsets */ | ||
8 | #define DW_SPI_CTRL0 0x00 | ||
9 | #define DW_SPI_CTRL1 0x04 | ||
10 | #define DW_SPI_SSIENR 0x08 | ||
11 | #define DW_SPI_MWCR 0x0c | ||
12 | #define DW_SPI_SER 0x10 | ||
13 | #define DW_SPI_BAUDR 0x14 | ||
14 | #define DW_SPI_TXFLTR 0x18 | ||
15 | #define DW_SPI_RXFLTR 0x1c | ||
16 | #define DW_SPI_TXFLR 0x20 | ||
17 | #define DW_SPI_RXFLR 0x24 | ||
18 | #define DW_SPI_SR 0x28 | ||
19 | #define DW_SPI_IMR 0x2c | ||
20 | #define DW_SPI_ISR 0x30 | ||
21 | #define DW_SPI_RISR 0x34 | ||
22 | #define DW_SPI_TXOICR 0x38 | ||
23 | #define DW_SPI_RXOICR 0x3c | ||
24 | #define DW_SPI_RXUICR 0x40 | ||
25 | #define DW_SPI_MSTICR 0x44 | ||
26 | #define DW_SPI_ICR 0x48 | ||
27 | #define DW_SPI_DMACR 0x4c | ||
28 | #define DW_SPI_DMATDLR 0x50 | ||
29 | #define DW_SPI_DMARDLR 0x54 | ||
30 | #define DW_SPI_IDR 0x58 | ||
31 | #define DW_SPI_VERSION 0x5c | ||
32 | #define DW_SPI_DR 0x60 | ||
33 | |||
34 | /* Bit fields in CTRLR0 */ | 7 | /* Bit fields in CTRLR0 */ |
35 | #define SPI_DFS_OFFSET 0 | 8 | #define SPI_DFS_OFFSET 0 |
36 | 9 | ||
@@ -82,6 +55,35 @@ enum dw_ssi_type { | |||
82 | SSI_NS_MICROWIRE, | 55 | SSI_NS_MICROWIRE, |
83 | }; | 56 | }; |
84 | 57 | ||
58 | struct dw_spi_reg { | ||
59 | u32 ctrl0; | ||
60 | u32 ctrl1; | ||
61 | u32 ssienr; | ||
62 | u32 mwcr; | ||
63 | u32 ser; | ||
64 | u32 baudr; | ||
65 | u32 txfltr; | ||
66 | u32 rxfltr; | ||
67 | u32 txflr; | ||
68 | u32 rxflr; | ||
69 | u32 sr; | ||
70 | u32 imr; | ||
71 | u32 isr; | ||
72 | u32 risr; | ||
73 | u32 txoicr; | ||
74 | u32 rxoicr; | ||
75 | u32 rxuicr; | ||
76 | u32 msticr; | ||
77 | u32 icr; | ||
78 | u32 dmacr; | ||
79 | u32 dmatdlr; | ||
80 | u32 dmardlr; | ||
81 | u32 idr; | ||
82 | u32 version; | ||
83 | u32 dr; /* Currently oper as 32 bits, | ||
84 | though only low 16 bits matters */ | ||
85 | } __packed; | ||
86 | |||
85 | struct dw_spi; | 87 | struct dw_spi; |
86 | struct dw_spi_dma_ops { | 88 | struct dw_spi_dma_ops { |
87 | int (*dma_init)(struct dw_spi *dws); | 89 | int (*dma_init)(struct dw_spi *dws); |
@@ -159,34 +161,23 @@ struct dw_spi { | |||
159 | #endif | 161 | #endif |
160 | }; | 162 | }; |
161 | 163 | ||
162 | static inline u32 dw_readl(struct dw_spi *dws, u32 offset) | 164 | #define dw_readl(dw, name) \ |
163 | { | 165 | __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name)) |
164 | return __raw_readl(dws->regs + offset); | 166 | #define dw_writel(dw, name, val) \ |
165 | } | 167 | __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name)) |
166 | 168 | #define dw_readw(dw, name) \ | |
167 | static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) | 169 | __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name)) |
168 | { | 170 | #define dw_writew(dw, name, val) \ |
169 | __raw_writel(val, dws->regs + offset); | 171 | __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name)) |
170 | } | ||
171 | |||
172 | static inline u16 dw_readw(struct dw_spi *dws, u32 offset) | ||
173 | { | ||
174 | return __raw_readw(dws->regs + offset); | ||
175 | } | ||
176 | |||
177 | static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) | ||
178 | { | ||
179 | __raw_writew(val, dws->regs + offset); | ||
180 | } | ||
181 | 172 | ||
182 | static inline void spi_enable_chip(struct dw_spi *dws, int enable) | 173 | static inline void spi_enable_chip(struct dw_spi *dws, int enable) |
183 | { | 174 | { |
184 | dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); | 175 | dw_writel(dws, ssienr, (enable ? 1 : 0)); |
185 | } | 176 | } |
186 | 177 | ||
187 | static inline void spi_set_clk(struct dw_spi *dws, u16 div) | 178 | static inline void spi_set_clk(struct dw_spi *dws, u16 div) |
188 | { | 179 | { |
189 | dw_writel(dws, DW_SPI_BAUDR, div); | 180 | dw_writel(dws, baudr, div); |
190 | } | 181 | } |
191 | 182 | ||
192 | static inline void spi_chip_sel(struct dw_spi *dws, u16 cs) | 183 | static inline void spi_chip_sel(struct dw_spi *dws, u16 cs) |
@@ -197,7 +188,7 @@ static inline void spi_chip_sel(struct dw_spi *dws, u16 cs) | |||
197 | if (dws->cs_control) | 188 | if (dws->cs_control) |
198 | dws->cs_control(1); | 189 | dws->cs_control(1); |
199 | 190 | ||
200 | dw_writel(dws, DW_SPI_SER, 1 << cs); | 191 | dw_writel(dws, ser, 1 << cs); |
201 | } | 192 | } |
202 | 193 | ||
203 | /* Disable IRQ bits */ | 194 | /* Disable IRQ bits */ |
@@ -205,8 +196,8 @@ static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) | |||
205 | { | 196 | { |
206 | u32 new_mask; | 197 | u32 new_mask; |
207 | 198 | ||
208 | new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; | 199 | new_mask = dw_readl(dws, imr) & ~mask; |
209 | dw_writel(dws, DW_SPI_IMR, new_mask); | 200 | dw_writel(dws, imr, new_mask); |
210 | } | 201 | } |
211 | 202 | ||
212 | /* Enable IRQ bits */ | 203 | /* Enable IRQ bits */ |
@@ -214,8 +205,8 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) | |||
214 | { | 205 | { |
215 | u32 new_mask; | 206 | u32 new_mask; |
216 | 207 | ||
217 | new_mask = dw_readl(dws, DW_SPI_IMR) | mask; | 208 | new_mask = dw_readl(dws, imr) | mask; |
218 | dw_writel(dws, DW_SPI_IMR, new_mask); | 209 | dw_writel(dws, imr, new_mask); |
219 | } | 210 | } |
220 | 211 | ||
221 | /* | 212 | /* |
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index acb1e1935c5..1cf645479bf 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c | |||
@@ -24,15 +24,14 @@ | |||
24 | #include <linux/dmaengine.h> | 24 | #include <linux/dmaengine.h> |
25 | #include <linux/bitops.h> | 25 | #include <linux/bitops.h> |
26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> | ||
28 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
29 | #include <linux/workqueue.h> | 28 | #include <linux/workqueue.h> |
30 | #include <linux/sched.h> | 29 | #include <linux/sched.h> |
31 | #include <linux/scatterlist.h> | 30 | #include <linux/scatterlist.h> |
32 | #include <linux/spi/spi.h> | 31 | #include <linux/spi/spi.h> |
33 | 32 | ||
34 | #include <linux/platform_data/dma-ep93xx.h> | 33 | #include <mach/dma.h> |
35 | #include <linux/platform_data/spi-ep93xx.h> | 34 | #include <mach/ep93xx_spi.h> |
36 | 35 | ||
37 | #define SSPCR0 0x0000 | 36 | #define SSPCR0 0x0000 |
38 | #define SSPCR0_MODE_SHIFT 6 | 37 | #define SSPCR0_MODE_SHIFT 6 |
@@ -76,6 +75,7 @@ | |||
76 | * @clk: clock for the controller | 75 | * @clk: clock for the controller |
77 | * @regs_base: pointer to ioremap()'d registers | 76 | * @regs_base: pointer to ioremap()'d registers |
78 | * @sspdr_phys: physical address of the SSPDR register | 77 | * @sspdr_phys: physical address of the SSPDR register |
78 | * @irq: IRQ number used by the driver | ||
79 | * @min_rate: minimum clock rate (in Hz) supported by the controller | 79 | * @min_rate: minimum clock rate (in Hz) supported by the controller |
80 | * @max_rate: maximum clock rate (in Hz) supported by the controller | 80 | * @max_rate: maximum clock rate (in Hz) supported by the controller |
81 | * @running: is the queue running | 81 | * @running: is the queue running |
@@ -113,6 +113,7 @@ struct ep93xx_spi { | |||
113 | struct clk *clk; | 113 | struct clk *clk; |
114 | void __iomem *regs_base; | 114 | void __iomem *regs_base; |
115 | unsigned long sspdr_phys; | 115 | unsigned long sspdr_phys; |
116 | int irq; | ||
116 | unsigned long min_rate; | 117 | unsigned long min_rate; |
117 | unsigned long max_rate; | 118 | unsigned long max_rate; |
118 | bool running; | 119 | bool running; |
@@ -543,7 +544,7 @@ static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) | |||
543 | * in case of failure. | 544 | * in case of failure. |
544 | */ | 545 | */ |
545 | static struct dma_async_tx_descriptor * | 546 | static struct dma_async_tx_descriptor * |
546 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) | 547 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir) |
547 | { | 548 | { |
548 | struct spi_transfer *t = espi->current_msg->state; | 549 | struct spi_transfer *t = espi->current_msg->state; |
549 | struct dma_async_tx_descriptor *txd; | 550 | struct dma_async_tx_descriptor *txd; |
@@ -564,7 +565,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) | |||
564 | memset(&conf, 0, sizeof(conf)); | 565 | memset(&conf, 0, sizeof(conf)); |
565 | conf.direction = dir; | 566 | conf.direction = dir; |
566 | 567 | ||
567 | if (dir == DMA_DEV_TO_MEM) { | 568 | if (dir == DMA_FROM_DEVICE) { |
568 | chan = espi->dma_rx; | 569 | chan = espi->dma_rx; |
569 | buf = t->rx_buf; | 570 | buf = t->rx_buf; |
570 | sgt = &espi->rx_sgt; | 571 | sgt = &espi->rx_sgt; |
@@ -628,7 +629,8 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) | |||
628 | if (!nents) | 629 | if (!nents) |
629 | return ERR_PTR(-ENOMEM); | 630 | return ERR_PTR(-ENOMEM); |
630 | 631 | ||
631 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); | 632 | txd = chan->device->device_prep_slave_sg(chan, sgt->sgl, nents, |
633 | dir, DMA_CTRL_ACK); | ||
632 | if (!txd) { | 634 | if (!txd) { |
633 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | 635 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); |
634 | return ERR_PTR(-ENOMEM); | 636 | return ERR_PTR(-ENOMEM); |
@@ -645,12 +647,12 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) | |||
645 | * unmapped. | 647 | * unmapped. |
646 | */ | 648 | */ |
647 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, | 649 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, |
648 | enum dma_transfer_direction dir) | 650 | enum dma_data_direction dir) |
649 | { | 651 | { |
650 | struct dma_chan *chan; | 652 | struct dma_chan *chan; |
651 | struct sg_table *sgt; | 653 | struct sg_table *sgt; |
652 | 654 | ||
653 | if (dir == DMA_DEV_TO_MEM) { | 655 | if (dir == DMA_FROM_DEVICE) { |
654 | chan = espi->dma_rx; | 656 | chan = espi->dma_rx; |
655 | sgt = &espi->rx_sgt; | 657 | sgt = &espi->rx_sgt; |
656 | } else { | 658 | } else { |
@@ -671,16 +673,16 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |||
671 | struct spi_message *msg = espi->current_msg; | 673 | struct spi_message *msg = espi->current_msg; |
672 | struct dma_async_tx_descriptor *rxd, *txd; | 674 | struct dma_async_tx_descriptor *rxd, *txd; |
673 | 675 | ||
674 | rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); | 676 | rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE); |
675 | if (IS_ERR(rxd)) { | 677 | if (IS_ERR(rxd)) { |
676 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); | 678 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); |
677 | msg->status = PTR_ERR(rxd); | 679 | msg->status = PTR_ERR(rxd); |
678 | return; | 680 | return; |
679 | } | 681 | } |
680 | 682 | ||
681 | txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); | 683 | txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE); |
682 | if (IS_ERR(txd)) { | 684 | if (IS_ERR(txd)) { |
683 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | 685 | ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); |
684 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); | 686 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); |
685 | msg->status = PTR_ERR(txd); | 687 | msg->status = PTR_ERR(txd); |
686 | return; | 688 | return; |
@@ -699,8 +701,8 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |||
699 | 701 | ||
700 | wait_for_completion(&espi->wait); | 702 | wait_for_completion(&espi->wait); |
701 | 703 | ||
702 | ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); | 704 | ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE); |
703 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | 705 | ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); |
704 | } | 706 | } |
705 | 707 | ||
706 | /** | 708 | /** |
@@ -976,7 +978,7 @@ static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |||
976 | dma_cap_set(DMA_SLAVE, mask); | 978 | dma_cap_set(DMA_SLAVE, mask); |
977 | 979 | ||
978 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | 980 | espi->dma_rx_data.port = EP93XX_DMA_SSP; |
979 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; | 981 | espi->dma_rx_data.direction = DMA_FROM_DEVICE; |
980 | espi->dma_rx_data.name = "ep93xx-spi-rx"; | 982 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
981 | 983 | ||
982 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | 984 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, |
@@ -987,7 +989,7 @@ static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |||
987 | } | 989 | } |
988 | 990 | ||
989 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | 991 | espi->dma_tx_data.port = EP93XX_DMA_SSP; |
990 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; | 992 | espi->dma_tx_data.direction = DMA_TO_DEVICE; |
991 | espi->dma_tx_data.name = "ep93xx-spi-tx"; | 993 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
992 | 994 | ||
993 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | 995 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, |
@@ -1023,13 +1025,12 @@ static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |||
1023 | free_page((unsigned long)espi->zeropage); | 1025 | free_page((unsigned long)espi->zeropage); |
1024 | } | 1026 | } |
1025 | 1027 | ||
1026 | static int ep93xx_spi_probe(struct platform_device *pdev) | 1028 | static int __init ep93xx_spi_probe(struct platform_device *pdev) |
1027 | { | 1029 | { |
1028 | struct spi_master *master; | 1030 | struct spi_master *master; |
1029 | struct ep93xx_spi_info *info; | 1031 | struct ep93xx_spi_info *info; |
1030 | struct ep93xx_spi *espi; | 1032 | struct ep93xx_spi *espi; |
1031 | struct resource *res; | 1033 | struct resource *res; |
1032 | int irq; | ||
1033 | int error; | 1034 | int error; |
1034 | 1035 | ||
1035 | info = pdev->dev.platform_data; | 1036 | info = pdev->dev.platform_data; |
@@ -1069,8 +1070,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev) | |||
1069 | espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); | 1070 | espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); |
1070 | espi->pdev = pdev; | 1071 | espi->pdev = pdev; |
1071 | 1072 | ||
1072 | irq = platform_get_irq(pdev, 0); | 1073 | espi->irq = platform_get_irq(pdev, 0); |
1073 | if (irq < 0) { | 1074 | if (espi->irq < 0) { |
1074 | error = -EBUSY; | 1075 | error = -EBUSY; |
1075 | dev_err(&pdev->dev, "failed to get irq resources\n"); | 1076 | dev_err(&pdev->dev, "failed to get irq resources\n"); |
1076 | goto fail_put_clock; | 1077 | goto fail_put_clock; |
@@ -1083,20 +1084,26 @@ static int ep93xx_spi_probe(struct platform_device *pdev) | |||
1083 | goto fail_put_clock; | 1084 | goto fail_put_clock; |
1084 | } | 1085 | } |
1085 | 1086 | ||
1086 | espi->sspdr_phys = res->start + SSPDR; | 1087 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
1088 | if (!res) { | ||
1089 | dev_err(&pdev->dev, "unable to request iomem resources\n"); | ||
1090 | error = -EBUSY; | ||
1091 | goto fail_put_clock; | ||
1092 | } | ||
1087 | 1093 | ||
1088 | espi->regs_base = devm_request_and_ioremap(&pdev->dev, res); | 1094 | espi->sspdr_phys = res->start + SSPDR; |
1095 | espi->regs_base = ioremap(res->start, resource_size(res)); | ||
1089 | if (!espi->regs_base) { | 1096 | if (!espi->regs_base) { |
1090 | dev_err(&pdev->dev, "failed to map resources\n"); | 1097 | dev_err(&pdev->dev, "failed to map resources\n"); |
1091 | error = -ENODEV; | 1098 | error = -ENODEV; |
1092 | goto fail_put_clock; | 1099 | goto fail_free_mem; |
1093 | } | 1100 | } |
1094 | 1101 | ||
1095 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, | 1102 | error = request_irq(espi->irq, ep93xx_spi_interrupt, 0, |
1096 | 0, "ep93xx-spi", espi); | 1103 | "ep93xx-spi", espi); |
1097 | if (error) { | 1104 | if (error) { |
1098 | dev_err(&pdev->dev, "failed to request irq\n"); | 1105 | dev_err(&pdev->dev, "failed to request irq\n"); |
1099 | goto fail_put_clock; | 1106 | goto fail_unmap_regs; |
1100 | } | 1107 | } |
1101 | 1108 | ||
1102 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) | 1109 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
@@ -1121,7 +1128,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev) | |||
1121 | } | 1128 | } |
1122 | 1129 | ||
1123 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | 1130 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", |
1124 | (unsigned long)res->start, irq); | 1131 | (unsigned long)res->start, espi->irq); |
1125 | 1132 | ||
1126 | return 0; | 1133 | return 0; |
1127 | 1134 | ||
@@ -1129,6 +1136,11 @@ fail_free_queue: | |||
1129 | destroy_workqueue(espi->wq); | 1136 | destroy_workqueue(espi->wq); |
1130 | fail_free_dma: | 1137 | fail_free_dma: |
1131 | ep93xx_spi_release_dma(espi); | 1138 | ep93xx_spi_release_dma(espi); |
1139 | free_irq(espi->irq, espi); | ||
1140 | fail_unmap_regs: | ||
1141 | iounmap(espi->regs_base); | ||
1142 | fail_free_mem: | ||
1143 | release_mem_region(res->start, resource_size(res)); | ||
1132 | fail_put_clock: | 1144 | fail_put_clock: |
1133 | clk_put(espi->clk); | 1145 | clk_put(espi->clk); |
1134 | fail_release_master: | 1146 | fail_release_master: |
@@ -1138,10 +1150,11 @@ fail_release_master: | |||
1138 | return error; | 1150 | return error; |
1139 | } | 1151 | } |
1140 | 1152 | ||
1141 | static int ep93xx_spi_remove(struct platform_device *pdev) | 1153 | static int __exit ep93xx_spi_remove(struct platform_device *pdev) |
1142 | { | 1154 | { |
1143 | struct spi_master *master = platform_get_drvdata(pdev); | 1155 | struct spi_master *master = platform_get_drvdata(pdev); |
1144 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | 1156 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
1157 | struct resource *res; | ||
1145 | 1158 | ||
1146 | spin_lock_irq(&espi->lock); | 1159 | spin_lock_irq(&espi->lock); |
1147 | espi->running = false; | 1160 | espi->running = false; |
@@ -1167,6 +1180,10 @@ static int ep93xx_spi_remove(struct platform_device *pdev) | |||
1167 | spin_unlock_irq(&espi->lock); | 1180 | spin_unlock_irq(&espi->lock); |
1168 | 1181 | ||
1169 | ep93xx_spi_release_dma(espi); | 1182 | ep93xx_spi_release_dma(espi); |
1183 | free_irq(espi->irq, espi); | ||
1184 | iounmap(espi->regs_base); | ||
1185 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1186 | release_mem_region(res->start, resource_size(res)); | ||
1170 | clk_put(espi->clk); | 1187 | clk_put(espi->clk); |
1171 | platform_set_drvdata(pdev, NULL); | 1188 | platform_set_drvdata(pdev, NULL); |
1172 | 1189 | ||
@@ -1179,10 +1196,20 @@ static struct platform_driver ep93xx_spi_driver = { | |||
1179 | .name = "ep93xx-spi", | 1196 | .name = "ep93xx-spi", |
1180 | .owner = THIS_MODULE, | 1197 | .owner = THIS_MODULE, |
1181 | }, | 1198 | }, |
1182 | .probe = ep93xx_spi_probe, | 1199 | .remove = __exit_p(ep93xx_spi_remove), |
1183 | .remove = ep93xx_spi_remove, | ||
1184 | }; | 1200 | }; |
1185 | module_platform_driver(ep93xx_spi_driver); | 1201 | |
1202 | static int __init ep93xx_spi_init(void) | ||
1203 | { | ||
1204 | return platform_driver_probe(&ep93xx_spi_driver, ep93xx_spi_probe); | ||
1205 | } | ||
1206 | module_init(ep93xx_spi_init); | ||
1207 | |||
1208 | static void __exit ep93xx_spi_exit(void) | ||
1209 | { | ||
1210 | platform_driver_unregister(&ep93xx_spi_driver); | ||
1211 | } | ||
1212 | module_exit(ep93xx_spi_exit); | ||
1186 | 1213 | ||
1187 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | 1214 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); |
1188 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | 1215 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); |
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c deleted file mode 100644 index 6a6f62ec284..00000000000 --- a/drivers/spi/spi-falcon.c +++ /dev/null | |||
@@ -1,469 +0,0 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or modify it | ||
3 | * under the terms of the GNU General Public License version 2 as published | ||
4 | * by the Free Software Foundation. | ||
5 | * | ||
6 | * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> | ||
7 | */ | ||
8 | |||
9 | #include <linux/module.h> | ||
10 | #include <linux/device.h> | ||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/spi/spi.h> | ||
13 | #include <linux/delay.h> | ||
14 | #include <linux/workqueue.h> | ||
15 | #include <linux/of.h> | ||
16 | #include <linux/of_platform.h> | ||
17 | |||
18 | #include <lantiq_soc.h> | ||
19 | |||
20 | #define DRV_NAME "sflash-falcon" | ||
21 | |||
22 | #define FALCON_SPI_XFER_BEGIN (1 << 0) | ||
23 | #define FALCON_SPI_XFER_END (1 << 1) | ||
24 | |||
25 | /* Bus Read Configuration Register0 */ | ||
26 | #define BUSRCON0 0x00000010 | ||
27 | /* Bus Write Configuration Register0 */ | ||
28 | #define BUSWCON0 0x00000018 | ||
29 | /* Serial Flash Configuration Register */ | ||
30 | #define SFCON 0x00000080 | ||
31 | /* Serial Flash Time Register */ | ||
32 | #define SFTIME 0x00000084 | ||
33 | /* Serial Flash Status Register */ | ||
34 | #define SFSTAT 0x00000088 | ||
35 | /* Serial Flash Command Register */ | ||
36 | #define SFCMD 0x0000008C | ||
37 | /* Serial Flash Address Register */ | ||
38 | #define SFADDR 0x00000090 | ||
39 | /* Serial Flash Data Register */ | ||
40 | #define SFDATA 0x00000094 | ||
41 | /* Serial Flash I/O Control Register */ | ||
42 | #define SFIO 0x00000098 | ||
43 | /* EBU Clock Control Register */ | ||
44 | #define EBUCC 0x000000C4 | ||
45 | |||
46 | /* Dummy Phase Length */ | ||
47 | #define SFCMD_DUMLEN_OFFSET 16 | ||
48 | #define SFCMD_DUMLEN_MASK 0x000F0000 | ||
49 | /* Chip Select */ | ||
50 | #define SFCMD_CS_OFFSET 24 | ||
51 | #define SFCMD_CS_MASK 0x07000000 | ||
52 | /* field offset */ | ||
53 | #define SFCMD_ALEN_OFFSET 20 | ||
54 | #define SFCMD_ALEN_MASK 0x00700000 | ||
55 | /* SCK Rise-edge Position */ | ||
56 | #define SFTIME_SCKR_POS_OFFSET 8 | ||
57 | #define SFTIME_SCKR_POS_MASK 0x00000F00 | ||
58 | /* SCK Period */ | ||
59 | #define SFTIME_SCK_PER_OFFSET 0 | ||
60 | #define SFTIME_SCK_PER_MASK 0x0000000F | ||
61 | /* SCK Fall-edge Position */ | ||
62 | #define SFTIME_SCKF_POS_OFFSET 12 | ||
63 | #define SFTIME_SCKF_POS_MASK 0x0000F000 | ||
64 | /* Device Size */ | ||
65 | #define SFCON_DEV_SIZE_A23_0 0x03000000 | ||
66 | #define SFCON_DEV_SIZE_MASK 0x0F000000 | ||
67 | /* Read Data Position */ | ||
68 | #define SFTIME_RD_POS_MASK 0x000F0000 | ||
69 | /* Data Output */ | ||
70 | #define SFIO_UNUSED_WD_MASK 0x0000000F | ||
71 | /* Command Opcode mask */ | ||
72 | #define SFCMD_OPC_MASK 0x000000FF | ||
73 | /* dlen bytes of data to write */ | ||
74 | #define SFCMD_DIR_WRITE 0x00000100 | ||
75 | /* Data Length offset */ | ||
76 | #define SFCMD_DLEN_OFFSET 9 | ||
77 | /* Command Error */ | ||
78 | #define SFSTAT_CMD_ERR 0x20000000 | ||
79 | /* Access Command Pending */ | ||
80 | #define SFSTAT_CMD_PEND 0x00400000 | ||
81 | /* Frequency set to 100MHz. */ | ||
82 | #define EBUCC_EBUDIV_SELF100 0x00000001 | ||
83 | /* Serial Flash */ | ||
84 | #define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 | ||
85 | /* 8-bit multiplexed */ | ||
86 | #define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 | ||
87 | /* Serial Flash */ | ||
88 | #define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 | ||
89 | /* Chip Select after opcode */ | ||
90 | #define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 | ||
91 | |||
92 | #define CLOCK_100M 100000000 | ||
93 | #define CLOCK_50M 50000000 | ||
94 | |||
95 | struct falcon_sflash { | ||
96 | u32 sfcmd; /* for caching of opcode, direction, ... */ | ||
97 | struct spi_master *master; | ||
98 | }; | ||
99 | |||
100 | int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t, | ||
101 | unsigned long flags) | ||
102 | { | ||
103 | struct device *dev = &spi->dev; | ||
104 | struct falcon_sflash *priv = spi_master_get_devdata(spi->master); | ||
105 | const u8 *txp = t->tx_buf; | ||
106 | u8 *rxp = t->rx_buf; | ||
107 | unsigned int bytelen = ((8 * t->len + 7) / 8); | ||
108 | unsigned int len, alen, dumlen; | ||
109 | u32 val; | ||
110 | enum { | ||
111 | state_init, | ||
112 | state_command_prepare, | ||
113 | state_write, | ||
114 | state_read, | ||
115 | state_disable_cs, | ||
116 | state_end | ||
117 | } state = state_init; | ||
118 | |||
119 | do { | ||
120 | switch (state) { | ||
121 | case state_init: /* detect phase of upper layer sequence */ | ||
122 | { | ||
123 | /* initial write ? */ | ||
124 | if (flags & FALCON_SPI_XFER_BEGIN) { | ||
125 | if (!txp) { | ||
126 | dev_err(dev, | ||
127 | "BEGIN without tx data!\n"); | ||
128 | return -ENODATA; | ||
129 | } | ||
130 | /* | ||
131 | * Prepare the parts of the sfcmd register, | ||
132 | * which should not change during a sequence! | ||
133 | * Only exception are the length fields, | ||
134 | * especially alen and dumlen. | ||
135 | */ | ||
136 | |||
137 | priv->sfcmd = ((spi->chip_select | ||
138 | << SFCMD_CS_OFFSET) | ||
139 | & SFCMD_CS_MASK); | ||
140 | priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED; | ||
141 | priv->sfcmd |= *txp; | ||
142 | txp++; | ||
143 | bytelen--; | ||
144 | if (bytelen) { | ||
145 | /* | ||
146 | * more data: | ||
147 | * maybe address and/or dummy | ||
148 | */ | ||
149 | state = state_command_prepare; | ||
150 | break; | ||
151 | } else { | ||
152 | dev_dbg(dev, "write cmd %02X\n", | ||
153 | priv->sfcmd & SFCMD_OPC_MASK); | ||
154 | } | ||
155 | } | ||
156 | /* continued write ? */ | ||
157 | if (txp && bytelen) { | ||
158 | state = state_write; | ||
159 | break; | ||
160 | } | ||
161 | /* read data? */ | ||
162 | if (rxp && bytelen) { | ||
163 | state = state_read; | ||
164 | break; | ||
165 | } | ||
166 | /* end of sequence? */ | ||
167 | if (flags & FALCON_SPI_XFER_END) | ||
168 | state = state_disable_cs; | ||
169 | else | ||
170 | state = state_end; | ||
171 | break; | ||
172 | } | ||
173 | /* collect tx data for address and dummy phase */ | ||
174 | case state_command_prepare: | ||
175 | { | ||
176 | /* txp is valid, already checked */ | ||
177 | val = 0; | ||
178 | alen = 0; | ||
179 | dumlen = 0; | ||
180 | while (bytelen > 0) { | ||
181 | if (alen < 3) { | ||
182 | val = (val << 8) | (*txp++); | ||
183 | alen++; | ||
184 | } else if ((dumlen < 15) && (*txp == 0)) { | ||
185 | /* | ||
186 | * assume dummy bytes are set to 0 | ||
187 | * from upper layer | ||
188 | */ | ||
189 | dumlen++; | ||
190 | txp++; | ||
191 | } else { | ||
192 | break; | ||
193 | } | ||
194 | bytelen--; | ||
195 | } | ||
196 | priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK); | ||
197 | priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) | | ||
198 | (dumlen << SFCMD_DUMLEN_OFFSET); | ||
199 | if (alen > 0) | ||
200 | ltq_ebu_w32(val, SFADDR); | ||
201 | |||
202 | dev_dbg(dev, "wr %02X, alen=%d (addr=%06X) dlen=%d\n", | ||
203 | priv->sfcmd & SFCMD_OPC_MASK, | ||
204 | alen, val, dumlen); | ||
205 | |||
206 | if (bytelen > 0) { | ||
207 | /* continue with write */ | ||
208 | state = state_write; | ||
209 | } else if (flags & FALCON_SPI_XFER_END) { | ||
210 | /* end of sequence? */ | ||
211 | state = state_disable_cs; | ||
212 | } else { | ||
213 | /* | ||
214 | * go to end and expect another | ||
215 | * call (read or write) | ||
216 | */ | ||
217 | state = state_end; | ||
218 | } | ||
219 | break; | ||
220 | } | ||
221 | case state_write: | ||
222 | { | ||
223 | /* txp still valid */ | ||
224 | priv->sfcmd |= SFCMD_DIR_WRITE; | ||
225 | len = 0; | ||
226 | val = 0; | ||
227 | do { | ||
228 | if (bytelen--) | ||
229 | val |= (*txp++) << (8 * len++); | ||
230 | if ((flags & FALCON_SPI_XFER_END) | ||
231 | && (bytelen == 0)) { | ||
232 | priv->sfcmd &= | ||
233 | ~SFCMD_KEEP_CS_KEEP_SELECTED; | ||
234 | } | ||
235 | if ((len == 4) || (bytelen == 0)) { | ||
236 | ltq_ebu_w32(val, SFDATA); | ||
237 | ltq_ebu_w32(priv->sfcmd | ||
238 | | (len<<SFCMD_DLEN_OFFSET), | ||
239 | SFCMD); | ||
240 | len = 0; | ||
241 | val = 0; | ||
242 | priv->sfcmd &= ~(SFCMD_ALEN_MASK | ||
243 | | SFCMD_DUMLEN_MASK); | ||
244 | } | ||
245 | } while (bytelen); | ||
246 | state = state_end; | ||
247 | break; | ||
248 | } | ||
249 | case state_read: | ||
250 | { | ||
251 | /* read data */ | ||
252 | priv->sfcmd &= ~SFCMD_DIR_WRITE; | ||
253 | do { | ||
254 | if ((flags & FALCON_SPI_XFER_END) | ||
255 | && (bytelen <= 4)) { | ||
256 | priv->sfcmd &= | ||
257 | ~SFCMD_KEEP_CS_KEEP_SELECTED; | ||
258 | } | ||
259 | len = (bytelen > 4) ? 4 : bytelen; | ||
260 | bytelen -= len; | ||
261 | ltq_ebu_w32(priv->sfcmd | ||
262 | | (len << SFCMD_DLEN_OFFSET), SFCMD); | ||
263 | priv->sfcmd &= ~(SFCMD_ALEN_MASK | ||
264 | | SFCMD_DUMLEN_MASK); | ||
265 | do { | ||
266 | val = ltq_ebu_r32(SFSTAT); | ||
267 | if (val & SFSTAT_CMD_ERR) { | ||
268 | /* reset error status */ | ||
269 | dev_err(dev, "SFSTAT: CMD_ERR"); | ||
270 | dev_err(dev, " (%x)\n", val); | ||
271 | ltq_ebu_w32(SFSTAT_CMD_ERR, | ||
272 | SFSTAT); | ||
273 | return -EBADE; | ||
274 | } | ||
275 | } while (val & SFSTAT_CMD_PEND); | ||
276 | val = ltq_ebu_r32(SFDATA); | ||
277 | do { | ||
278 | *rxp = (val & 0xFF); | ||
279 | rxp++; | ||
280 | val >>= 8; | ||
281 | len--; | ||
282 | } while (len); | ||
283 | } while (bytelen); | ||
284 | state = state_end; | ||
285 | break; | ||
286 | } | ||
287 | case state_disable_cs: | ||
288 | { | ||
289 | priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED; | ||
290 | ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET), | ||
291 | SFCMD); | ||
292 | val = ltq_ebu_r32(SFSTAT); | ||
293 | if (val & SFSTAT_CMD_ERR) { | ||
294 | /* reset error status */ | ||
295 | dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val); | ||
296 | ltq_ebu_w32(SFSTAT_CMD_ERR, SFSTAT); | ||
297 | return -EBADE; | ||
298 | } | ||
299 | state = state_end; | ||
300 | break; | ||
301 | } | ||
302 | case state_end: | ||
303 | break; | ||
304 | } | ||
305 | } while (state != state_end); | ||
306 | |||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | static int falcon_sflash_setup(struct spi_device *spi) | ||
311 | { | ||
312 | unsigned int i; | ||
313 | unsigned long flags; | ||
314 | |||
315 | if (spi->chip_select > 0) | ||
316 | return -ENODEV; | ||
317 | |||
318 | spin_lock_irqsave(&ebu_lock, flags); | ||
319 | |||
320 | if (spi->max_speed_hz >= CLOCK_100M) { | ||
321 | /* set EBU clock to 100 MHz */ | ||
322 | ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, EBUCC); | ||
323 | i = 1; /* divider */ | ||
324 | } else { | ||
325 | /* set EBU clock to 50 MHz */ | ||
326 | ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, EBUCC); | ||
327 | |||
328 | /* search for suitable divider */ | ||
329 | for (i = 1; i < 7; i++) { | ||
330 | if (CLOCK_50M / i <= spi->max_speed_hz) | ||
331 | break; | ||
332 | } | ||
333 | } | ||
334 | |||
335 | /* setup period of serial clock */ | ||
336 | ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK | ||
337 | | SFTIME_SCKR_POS_MASK | ||
338 | | SFTIME_SCK_PER_MASK, | ||
339 | (i << SFTIME_SCKR_POS_OFFSET) | ||
340 | | (i << (SFTIME_SCK_PER_OFFSET + 1)), | ||
341 | SFTIME); | ||
342 | |||
343 | /* | ||
344 | * set some bits of unused_wd, to not trigger HOLD/WP | ||
345 | * signals on non QUAD flashes | ||
346 | */ | ||
347 | ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), SFIO); | ||
348 | |||
349 | ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX, | ||
350 | BUSRCON0); | ||
351 | ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, BUSWCON0); | ||
352 | /* set address wrap around to maximum for 24-bit addresses */ | ||
353 | ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, SFCON); | ||
354 | |||
355 | spin_unlock_irqrestore(&ebu_lock, flags); | ||
356 | |||
357 | return 0; | ||
358 | } | ||
359 | |||
360 | static int falcon_sflash_prepare_xfer(struct spi_master *master) | ||
361 | { | ||
362 | return 0; | ||
363 | } | ||
364 | |||
365 | static int falcon_sflash_unprepare_xfer(struct spi_master *master) | ||
366 | { | ||
367 | return 0; | ||
368 | } | ||
369 | |||
370 | static int falcon_sflash_xfer_one(struct spi_master *master, | ||
371 | struct spi_message *m) | ||
372 | { | ||
373 | struct falcon_sflash *priv = spi_master_get_devdata(master); | ||
374 | struct spi_transfer *t; | ||
375 | unsigned long spi_flags; | ||
376 | unsigned long flags; | ||
377 | int ret = 0; | ||
378 | |||
379 | priv->sfcmd = 0; | ||
380 | m->actual_length = 0; | ||
381 | |||
382 | spi_flags = FALCON_SPI_XFER_BEGIN; | ||
383 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
384 | if (list_is_last(&t->transfer_list, &m->transfers)) | ||
385 | spi_flags |= FALCON_SPI_XFER_END; | ||
386 | |||
387 | spin_lock_irqsave(&ebu_lock, flags); | ||
388 | ret = falcon_sflash_xfer(m->spi, t, spi_flags); | ||
389 | spin_unlock_irqrestore(&ebu_lock, flags); | ||
390 | |||
391 | if (ret) | ||
392 | break; | ||
393 | |||
394 | m->actual_length += t->len; | ||
395 | |||
396 | WARN_ON(t->delay_usecs || t->cs_change); | ||
397 | spi_flags = 0; | ||
398 | } | ||
399 | |||
400 | m->status = ret; | ||
401 | m->complete(m->context); | ||
402 | |||
403 | return 0; | ||
404 | } | ||
405 | |||
406 | static int falcon_sflash_probe(struct platform_device *pdev) | ||
407 | { | ||
408 | struct falcon_sflash *priv; | ||
409 | struct spi_master *master; | ||
410 | int ret; | ||
411 | |||
412 | if (ltq_boot_select() != BS_SPI) { | ||
413 | dev_err(&pdev->dev, "invalid bootstrap options\n"); | ||
414 | return -ENODEV; | ||
415 | } | ||
416 | |||
417 | master = spi_alloc_master(&pdev->dev, sizeof(*priv)); | ||
418 | if (!master) | ||
419 | return -ENOMEM; | ||
420 | |||
421 | priv = spi_master_get_devdata(master); | ||
422 | priv->master = master; | ||
423 | |||
424 | master->mode_bits = SPI_MODE_3; | ||
425 | master->num_chipselect = 1; | ||
426 | master->bus_num = -1; | ||
427 | master->setup = falcon_sflash_setup; | ||
428 | master->prepare_transfer_hardware = falcon_sflash_prepare_xfer; | ||
429 | master->transfer_one_message = falcon_sflash_xfer_one; | ||
430 | master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer; | ||
431 | master->dev.of_node = pdev->dev.of_node; | ||
432 | |||
433 | platform_set_drvdata(pdev, priv); | ||
434 | |||
435 | ret = spi_register_master(master); | ||
436 | if (ret) | ||
437 | spi_master_put(master); | ||
438 | return ret; | ||
439 | } | ||
440 | |||
441 | static int falcon_sflash_remove(struct platform_device *pdev) | ||
442 | { | ||
443 | struct falcon_sflash *priv = platform_get_drvdata(pdev); | ||
444 | |||
445 | spi_unregister_master(priv->master); | ||
446 | |||
447 | return 0; | ||
448 | } | ||
449 | |||
450 | static const struct of_device_id falcon_sflash_match[] = { | ||
451 | { .compatible = "lantiq,sflash-falcon" }, | ||
452 | {}, | ||
453 | }; | ||
454 | MODULE_DEVICE_TABLE(of, falcon_sflash_match); | ||
455 | |||
456 | static struct platform_driver falcon_sflash_driver = { | ||
457 | .probe = falcon_sflash_probe, | ||
458 | .remove = falcon_sflash_remove, | ||
459 | .driver = { | ||
460 | .name = DRV_NAME, | ||
461 | .owner = THIS_MODULE, | ||
462 | .of_match_table = falcon_sflash_match, | ||
463 | } | ||
464 | }; | ||
465 | |||
466 | module_platform_driver(falcon_sflash_driver); | ||
467 | |||
468 | MODULE_LICENSE("GPL"); | ||
469 | MODULE_DESCRIPTION("Lantiq Falcon SPI/SFLASH controller driver"); | ||
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index 24610ca8955..54e499d5f92 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/mm.h> | 17 | #include <linux/mm.h> |
18 | #include <linux/of.h> | 18 | #include <linux/of.h> |
19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
20 | #include <linux/of_spi.h> | ||
20 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
21 | #include <linux/err.h> | 22 | #include <linux/err.h> |
22 | #include <sysdev/fsl_soc.h> | 23 | #include <sysdev/fsl_soc.h> |
@@ -179,20 +180,18 @@ static int fsl_espi_setup_transfer(struct spi_device *spi, | |||
179 | 180 | ||
180 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | 181 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
181 | cs->hw_mode |= CSMODE_DIV16; | 182 | cs->hw_mode |= CSMODE_DIV16; |
182 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); | 183 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
183 | 184 | ||
184 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " | 185 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " |
185 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | 186 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
186 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); | 187 | hz, mpc8xxx_spi->spibrg / 1024); |
187 | if (pm > 33) | 188 | if (pm > 16) |
188 | pm = 33; | 189 | pm = 16; |
189 | } else { | 190 | } else { |
190 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); | 191 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
191 | } | 192 | } |
192 | if (pm) | 193 | if (pm) |
193 | pm--; | 194 | pm--; |
194 | if (pm < 2) | ||
195 | pm = 2; | ||
196 | 195 | ||
197 | cs->hw_mode |= CSMODE_PM(pm); | 196 | cs->hw_mode |= CSMODE_PM(pm); |
198 | 197 | ||
@@ -587,7 +586,7 @@ static void fsl_espi_remove(struct mpc8xxx_spi *mspi) | |||
587 | iounmap(mspi->reg_base); | 586 | iounmap(mspi->reg_base); |
588 | } | 587 | } |
589 | 588 | ||
590 | static struct spi_master * fsl_espi_probe(struct device *dev, | 589 | static struct spi_master * __devinit fsl_espi_probe(struct device *dev, |
591 | struct resource *mem, unsigned int irq) | 590 | struct resource *mem, unsigned int irq) |
592 | { | 591 | { |
593 | struct fsl_spi_platform_data *pdata = dev->platform_data; | 592 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
@@ -686,7 +685,7 @@ static int of_fsl_espi_get_chipselects(struct device *dev) | |||
686 | return 0; | 685 | return 0; |
687 | } | 686 | } |
688 | 687 | ||
689 | static int of_fsl_espi_probe(struct platform_device *ofdev) | 688 | static int __devinit of_fsl_espi_probe(struct platform_device *ofdev) |
690 | { | 689 | { |
691 | struct device *dev = &ofdev->dev; | 690 | struct device *dev = &ofdev->dev; |
692 | struct device_node *np = ofdev->dev.of_node; | 691 | struct device_node *np = ofdev->dev.of_node; |
@@ -725,7 +724,7 @@ err: | |||
725 | return ret; | 724 | return ret; |
726 | } | 725 | } |
727 | 726 | ||
728 | static int of_fsl_espi_remove(struct platform_device *dev) | 727 | static int __devexit of_fsl_espi_remove(struct platform_device *dev) |
729 | { | 728 | { |
730 | return mpc8xxx_spi_remove(&dev->dev); | 729 | return mpc8xxx_spi_remove(&dev->dev); |
731 | } | 730 | } |
@@ -743,9 +742,20 @@ static struct platform_driver fsl_espi_driver = { | |||
743 | .of_match_table = of_fsl_espi_match, | 742 | .of_match_table = of_fsl_espi_match, |
744 | }, | 743 | }, |
745 | .probe = of_fsl_espi_probe, | 744 | .probe = of_fsl_espi_probe, |
746 | .remove = of_fsl_espi_remove, | 745 | .remove = __devexit_p(of_fsl_espi_remove), |
747 | }; | 746 | }; |
748 | module_platform_driver(fsl_espi_driver); | 747 | |
748 | static int __init fsl_espi_init(void) | ||
749 | { | ||
750 | return platform_driver_register(&fsl_espi_driver); | ||
751 | } | ||
752 | module_init(fsl_espi_init); | ||
753 | |||
754 | static void __exit fsl_espi_exit(void) | ||
755 | { | ||
756 | platform_driver_unregister(&fsl_espi_driver); | ||
757 | } | ||
758 | module_exit(fsl_espi_exit); | ||
749 | 759 | ||
750 | MODULE_AUTHOR("Mingkai Hu"); | 760 | MODULE_AUTHOR("Mingkai Hu"); |
751 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | 761 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); |
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c index 8ade675a04f..2674fad7f68 100644 --- a/drivers/spi/spi-fsl-lib.c +++ b/drivers/spi/spi-fsl-lib.c | |||
@@ -22,7 +22,7 @@ | |||
22 | #include <linux/dma-mapping.h> | 22 | #include <linux/dma-mapping.h> |
23 | #include <linux/mm.h> | 23 | #include <linux/mm.h> |
24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
25 | #include <linux/spi/spi.h> | 25 | #include <linux/of_spi.h> |
26 | #include <sysdev/fsl_soc.h> | 26 | #include <sysdev/fsl_soc.h> |
27 | 27 | ||
28 | #include "spi-fsl-lib.h" | 28 | #include "spi-fsl-lib.h" |
@@ -169,7 +169,7 @@ err: | |||
169 | return ret; | 169 | return ret; |
170 | } | 170 | } |
171 | 171 | ||
172 | int mpc8xxx_spi_remove(struct device *dev) | 172 | int __devexit mpc8xxx_spi_remove(struct device *dev) |
173 | { | 173 | { |
174 | struct mpc8xxx_spi *mpc8xxx_spi; | 174 | struct mpc8xxx_spi *mpc8xxx_spi; |
175 | struct spi_master *master; | 175 | struct spi_master *master; |
@@ -189,7 +189,7 @@ int mpc8xxx_spi_remove(struct device *dev) | |||
189 | return 0; | 189 | return 0; |
190 | } | 190 | } |
191 | 191 | ||
192 | int of_mpc8xxx_spi_probe(struct platform_device *ofdev) | 192 | int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev) |
193 | { | 193 | { |
194 | struct device *dev = &ofdev->dev; | 194 | struct device *dev = &ofdev->dev; |
195 | struct device_node *np = ofdev->dev.of_node; | 195 | struct device_node *np = ofdev->dev.of_node; |
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 1a7f6359d99..24cacff5778 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c | |||
@@ -139,12 +139,10 @@ static void fsl_spi_change_mode(struct spi_device *spi) | |||
139 | static void fsl_spi_chipselect(struct spi_device *spi, int value) | 139 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
140 | { | 140 | { |
141 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | 141 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
142 | struct fsl_spi_platform_data *pdata; | 142 | struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; |
143 | bool pol = spi->mode & SPI_CS_HIGH; | 143 | bool pol = spi->mode & SPI_CS_HIGH; |
144 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | 144 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
145 | 145 | ||
146 | pdata = spi->dev.parent->parent->platform_data; | ||
147 | |||
148 | if (value == BITBANG_CS_INACTIVE) { | 146 | if (value == BITBANG_CS_INACTIVE) { |
149 | if (pdata->cs_control) | 147 | if (pdata->cs_control) |
150 | pdata->cs_control(spi, !pol); | 148 | pdata->cs_control(spi, !pol); |
@@ -843,7 +841,7 @@ static void fsl_spi_remove(struct mpc8xxx_spi *mspi) | |||
843 | fsl_spi_cpm_free(mspi); | 841 | fsl_spi_cpm_free(mspi); |
844 | } | 842 | } |
845 | 843 | ||
846 | static struct spi_master * fsl_spi_probe(struct device *dev, | 844 | static struct spi_master * __devinit fsl_spi_probe(struct device *dev, |
847 | struct resource *mem, unsigned int irq) | 845 | struct resource *mem, unsigned int irq) |
848 | { | 846 | { |
849 | struct fsl_spi_platform_data *pdata = dev->platform_data; | 847 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
@@ -933,7 +931,7 @@ err: | |||
933 | 931 | ||
934 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) | 932 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
935 | { | 933 | { |
936 | struct device *dev = spi->dev.parent->parent; | 934 | struct device *dev = spi->dev.parent; |
937 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); | 935 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
938 | u16 cs = spi->chip_select; | 936 | u16 cs = spi->chip_select; |
939 | int gpio = pinfo->gpios[cs]; | 937 | int gpio = pinfo->gpios[cs]; |
@@ -1041,7 +1039,7 @@ static int of_fsl_spi_free_chipselects(struct device *dev) | |||
1041 | return 0; | 1039 | return 0; |
1042 | } | 1040 | } |
1043 | 1041 | ||
1044 | static int of_fsl_spi_probe(struct platform_device *ofdev) | 1042 | static int __devinit of_fsl_spi_probe(struct platform_device *ofdev) |
1045 | { | 1043 | { |
1046 | struct device *dev = &ofdev->dev; | 1044 | struct device *dev = &ofdev->dev; |
1047 | struct device_node *np = ofdev->dev.of_node; | 1045 | struct device_node *np = ofdev->dev.of_node; |
@@ -1081,7 +1079,7 @@ err: | |||
1081 | return ret; | 1079 | return ret; |
1082 | } | 1080 | } |
1083 | 1081 | ||
1084 | static int of_fsl_spi_remove(struct platform_device *ofdev) | 1082 | static int __devexit of_fsl_spi_remove(struct platform_device *ofdev) |
1085 | { | 1083 | { |
1086 | int ret; | 1084 | int ret; |
1087 | 1085 | ||
@@ -1105,7 +1103,7 @@ static struct platform_driver of_fsl_spi_driver = { | |||
1105 | .of_match_table = of_fsl_spi_match, | 1103 | .of_match_table = of_fsl_spi_match, |
1106 | }, | 1104 | }, |
1107 | .probe = of_fsl_spi_probe, | 1105 | .probe = of_fsl_spi_probe, |
1108 | .remove = of_fsl_spi_remove, | 1106 | .remove = __devexit_p(of_fsl_spi_remove), |
1109 | }; | 1107 | }; |
1110 | 1108 | ||
1111 | #ifdef CONFIG_MPC832x_RDB | 1109 | #ifdef CONFIG_MPC832x_RDB |
@@ -1116,7 +1114,7 @@ static struct platform_driver of_fsl_spi_driver = { | |||
1116 | * tree can work with OpenFirmware driver. But for now we support old trees | 1114 | * tree can work with OpenFirmware driver. But for now we support old trees |
1117 | * as well. | 1115 | * as well. |
1118 | */ | 1116 | */ |
1119 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) | 1117 | static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
1120 | { | 1118 | { |
1121 | struct resource *mem; | 1119 | struct resource *mem; |
1122 | int irq; | 1120 | int irq; |
@@ -1139,7 +1137,7 @@ static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) | |||
1139 | return 0; | 1137 | return 0; |
1140 | } | 1138 | } |
1141 | 1139 | ||
1142 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) | 1140 | static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
1143 | { | 1141 | { |
1144 | return mpc8xxx_spi_remove(&pdev->dev); | 1142 | return mpc8xxx_spi_remove(&pdev->dev); |
1145 | } | 1143 | } |
@@ -1147,7 +1145,7 @@ static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) | |||
1147 | MODULE_ALIAS("platform:mpc8xxx_spi"); | 1145 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
1148 | static struct platform_driver mpc8xxx_spi_driver = { | 1146 | static struct platform_driver mpc8xxx_spi_driver = { |
1149 | .probe = plat_mpc8xxx_spi_probe, | 1147 | .probe = plat_mpc8xxx_spi_probe, |
1150 | .remove = plat_mpc8xxx_spi_remove, | 1148 | .remove = __devexit_p(plat_mpc8xxx_spi_remove), |
1151 | .driver = { | 1149 | .driver = { |
1152 | .name = "mpc8xxx_spi", | 1150 | .name = "mpc8xxx_spi", |
1153 | .owner = THIS_MODULE, | 1151 | .owner = THIS_MODULE, |
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index c7cf0b7a069..0e88ab74549 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c | |||
@@ -18,12 +18,9 @@ | |||
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
19 | */ | 19 | */ |
20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> | ||
22 | #include <linux/init.h> | 21 | #include <linux/init.h> |
23 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
24 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
25 | #include <linux/of_device.h> | ||
26 | #include <linux/of_gpio.h> | ||
27 | 24 | ||
28 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | 26 | #include <linux/spi/spi_bitbang.h> |
@@ -48,7 +45,6 @@ struct spi_gpio { | |||
48 | struct spi_bitbang bitbang; | 45 | struct spi_bitbang bitbang; |
49 | struct spi_gpio_platform_data pdata; | 46 | struct spi_gpio_platform_data pdata; |
50 | struct platform_device *pdev; | 47 | struct platform_device *pdev; |
51 | int cs_gpios[0]; | ||
52 | }; | 48 | }; |
53 | 49 | ||
54 | /*----------------------------------------------------------------------*/ | 50 | /*----------------------------------------------------------------------*/ |
@@ -92,21 +88,15 @@ struct spi_gpio { | |||
92 | 88 | ||
93 | /*----------------------------------------------------------------------*/ | 89 | /*----------------------------------------------------------------------*/ |
94 | 90 | ||
95 | static inline struct spi_gpio * __pure | 91 | static inline const struct spi_gpio_platform_data * __pure |
96 | spi_to_spi_gpio(const struct spi_device *spi) | 92 | spi_to_pdata(const struct spi_device *spi) |
97 | { | 93 | { |
98 | const struct spi_bitbang *bang; | 94 | const struct spi_bitbang *bang; |
99 | struct spi_gpio *spi_gpio; | 95 | const struct spi_gpio *spi_gpio; |
100 | 96 | ||
101 | bang = spi_master_get_devdata(spi->master); | 97 | bang = spi_master_get_devdata(spi->master); |
102 | spi_gpio = container_of(bang, struct spi_gpio, bitbang); | 98 | spi_gpio = container_of(bang, struct spi_gpio, bitbang); |
103 | return spi_gpio; | 99 | return &spi_gpio->pdata; |
104 | } | ||
105 | |||
106 | static inline struct spi_gpio_platform_data * __pure | ||
107 | spi_to_pdata(const struct spi_device *spi) | ||
108 | { | ||
109 | return &spi_to_spi_gpio(spi)->pdata; | ||
110 | } | 100 | } |
111 | 101 | ||
112 | /* this is #defined to avoid unused-variable warnings when inlining */ | 102 | /* this is #defined to avoid unused-variable warnings when inlining */ |
@@ -219,8 +209,7 @@ static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi, | |||
219 | 209 | ||
220 | static void spi_gpio_chipselect(struct spi_device *spi, int is_active) | 210 | static void spi_gpio_chipselect(struct spi_device *spi, int is_active) |
221 | { | 211 | { |
222 | struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); | 212 | unsigned long cs = (unsigned long) spi->controller_data; |
223 | unsigned int cs = spi_gpio->cs_gpios[spi->chip_select]; | ||
224 | 213 | ||
225 | /* set initial clock polarity */ | 214 | /* set initial clock polarity */ |
226 | if (is_active) | 215 | if (is_active) |
@@ -234,42 +223,22 @@ static void spi_gpio_chipselect(struct spi_device *spi, int is_active) | |||
234 | 223 | ||
235 | static int spi_gpio_setup(struct spi_device *spi) | 224 | static int spi_gpio_setup(struct spi_device *spi) |
236 | { | 225 | { |
237 | unsigned int cs; | 226 | unsigned long cs = (unsigned long) spi->controller_data; |
238 | int status = 0; | 227 | int status = 0; |
239 | struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); | ||
240 | struct device_node *np = spi->master->dev.of_node; | ||
241 | 228 | ||
242 | if (spi->bits_per_word > 32) | 229 | if (spi->bits_per_word > 32) |
243 | return -EINVAL; | 230 | return -EINVAL; |
244 | 231 | ||
245 | if (np) { | ||
246 | /* | ||
247 | * In DT environments, the CS GPIOs have already been | ||
248 | * initialized from the "cs-gpios" property of the node. | ||
249 | */ | ||
250 | cs = spi_gpio->cs_gpios[spi->chip_select]; | ||
251 | } else { | ||
252 | /* | ||
253 | * ... otherwise, take it from spi->controller_data | ||
254 | */ | ||
255 | cs = (unsigned int) spi->controller_data; | ||
256 | } | ||
257 | |||
258 | if (!spi->controller_state) { | 232 | if (!spi->controller_state) { |
259 | if (cs != SPI_GPIO_NO_CHIPSELECT) { | 233 | if (cs != SPI_GPIO_NO_CHIPSELECT) { |
260 | status = gpio_request(cs, dev_name(&spi->dev)); | 234 | status = gpio_request(cs, dev_name(&spi->dev)); |
261 | if (status) | 235 | if (status) |
262 | return status; | 236 | return status; |
263 | status = gpio_direction_output(cs, | 237 | status = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); |
264 | !(spi->mode & SPI_CS_HIGH)); | ||
265 | } | 238 | } |
266 | } | 239 | } |
267 | if (!status) { | 240 | if (!status) |
268 | status = spi_bitbang_setup(spi); | 241 | status = spi_bitbang_setup(spi); |
269 | /* in case it was initialized from static board data */ | ||
270 | spi_gpio->cs_gpios[spi->chip_select] = cs; | ||
271 | } | ||
272 | |||
273 | if (status) { | 242 | if (status) { |
274 | if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT) | 243 | if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT) |
275 | gpio_free(cs); | 244 | gpio_free(cs); |
@@ -279,15 +248,14 @@ static int spi_gpio_setup(struct spi_device *spi) | |||
279 | 248 | ||
280 | static void spi_gpio_cleanup(struct spi_device *spi) | 249 | static void spi_gpio_cleanup(struct spi_device *spi) |
281 | { | 250 | { |
282 | struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); | 251 | unsigned long cs = (unsigned long) spi->controller_data; |
283 | unsigned int cs = spi_gpio->cs_gpios[spi->chip_select]; | ||
284 | 252 | ||
285 | if (cs != SPI_GPIO_NO_CHIPSELECT) | 253 | if (cs != SPI_GPIO_NO_CHIPSELECT) |
286 | gpio_free(cs); | 254 | gpio_free(cs); |
287 | spi_bitbang_cleanup(spi); | 255 | spi_bitbang_cleanup(spi); |
288 | } | 256 | } |
289 | 257 | ||
290 | static int spi_gpio_alloc(unsigned pin, const char *label, bool is_in) | 258 | static int __init spi_gpio_alloc(unsigned pin, const char *label, bool is_in) |
291 | { | 259 | { |
292 | int value; | 260 | int value; |
293 | 261 | ||
@@ -301,8 +269,9 @@ static int spi_gpio_alloc(unsigned pin, const char *label, bool is_in) | |||
301 | return value; | 269 | return value; |
302 | } | 270 | } |
303 | 271 | ||
304 | static int spi_gpio_request(struct spi_gpio_platform_data *pdata, | 272 | static int __init |
305 | const char *label, u16 *res_flags) | 273 | spi_gpio_request(struct spi_gpio_platform_data *pdata, const char *label, |
274 | u16 *res_flags) | ||
306 | { | 275 | { |
307 | int value; | 276 | int value; |
308 | 277 | ||
@@ -342,69 +311,13 @@ done: | |||
342 | return value; | 311 | return value; |
343 | } | 312 | } |
344 | 313 | ||
345 | #ifdef CONFIG_OF | 314 | static int __init spi_gpio_probe(struct platform_device *pdev) |
346 | static struct of_device_id spi_gpio_dt_ids[] = { | ||
347 | { .compatible = "spi-gpio" }, | ||
348 | {} | ||
349 | }; | ||
350 | MODULE_DEVICE_TABLE(of, spi_gpio_dt_ids); | ||
351 | |||
352 | static int spi_gpio_probe_dt(struct platform_device *pdev) | ||
353 | { | ||
354 | int ret; | ||
355 | u32 tmp; | ||
356 | struct spi_gpio_platform_data *pdata; | ||
357 | struct device_node *np = pdev->dev.of_node; | ||
358 | const struct of_device_id *of_id = | ||
359 | of_match_device(spi_gpio_dt_ids, &pdev->dev); | ||
360 | |||
361 | if (!of_id) | ||
362 | return 0; | ||
363 | |||
364 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
365 | if (!pdata) | ||
366 | return -ENOMEM; | ||
367 | |||
368 | pdata->sck = of_get_named_gpio(np, "gpio-sck", 0); | ||
369 | pdata->miso = of_get_named_gpio(np, "gpio-miso", 0); | ||
370 | pdata->mosi = of_get_named_gpio(np, "gpio-mosi", 0); | ||
371 | |||
372 | ret = of_property_read_u32(np, "num-chipselects", &tmp); | ||
373 | if (ret < 0) { | ||
374 | dev_err(&pdev->dev, "num-chipselects property not found\n"); | ||
375 | goto error_free; | ||
376 | } | ||
377 | |||
378 | pdata->num_chipselect = tmp; | ||
379 | pdev->dev.platform_data = pdata; | ||
380 | |||
381 | return 1; | ||
382 | |||
383 | error_free: | ||
384 | devm_kfree(&pdev->dev, pdata); | ||
385 | return ret; | ||
386 | } | ||
387 | #else | ||
388 | static inline int spi_gpio_probe_dt(struct platform_device *pdev) | ||
389 | { | ||
390 | return 0; | ||
391 | } | ||
392 | #endif | ||
393 | |||
394 | static int spi_gpio_probe(struct platform_device *pdev) | ||
395 | { | 315 | { |
396 | int status; | 316 | int status; |
397 | struct spi_master *master; | 317 | struct spi_master *master; |
398 | struct spi_gpio *spi_gpio; | 318 | struct spi_gpio *spi_gpio; |
399 | struct spi_gpio_platform_data *pdata; | 319 | struct spi_gpio_platform_data *pdata; |
400 | u16 master_flags = 0; | 320 | u16 master_flags = 0; |
401 | bool use_of = 0; | ||
402 | |||
403 | status = spi_gpio_probe_dt(pdev); | ||
404 | if (status < 0) | ||
405 | return status; | ||
406 | if (status > 0) | ||
407 | use_of = 1; | ||
408 | 321 | ||
409 | pdata = pdev->dev.platform_data; | 322 | pdata = pdev->dev.platform_data; |
410 | #ifdef GENERIC_BITBANG | 323 | #ifdef GENERIC_BITBANG |
@@ -416,8 +329,7 @@ static int spi_gpio_probe(struct platform_device *pdev) | |||
416 | if (status < 0) | 329 | if (status < 0) |
417 | return status; | 330 | return status; |
418 | 331 | ||
419 | master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) + | 332 | master = spi_alloc_master(&pdev->dev, sizeof *spi_gpio); |
420 | (sizeof(int) * SPI_N_CHIPSEL)); | ||
421 | if (!master) { | 333 | if (!master) { |
422 | status = -ENOMEM; | 334 | status = -ENOMEM; |
423 | goto gpio_free; | 335 | goto gpio_free; |
@@ -434,23 +346,6 @@ static int spi_gpio_probe(struct platform_device *pdev) | |||
434 | master->num_chipselect = SPI_N_CHIPSEL; | 346 | master->num_chipselect = SPI_N_CHIPSEL; |
435 | master->setup = spi_gpio_setup; | 347 | master->setup = spi_gpio_setup; |
436 | master->cleanup = spi_gpio_cleanup; | 348 | master->cleanup = spi_gpio_cleanup; |
437 | #ifdef CONFIG_OF | ||
438 | master->dev.of_node = pdev->dev.of_node; | ||
439 | |||
440 | if (use_of) { | ||
441 | int i; | ||
442 | struct device_node *np = pdev->dev.of_node; | ||
443 | |||
444 | /* | ||
445 | * In DT environments, take the CS GPIO from the "cs-gpios" | ||
446 | * property of the node. | ||
447 | */ | ||
448 | |||
449 | for (i = 0; i < SPI_N_CHIPSEL; i++) | ||
450 | spi_gpio->cs_gpios[i] = | ||
451 | of_get_named_gpio(np, "cs-gpios", i); | ||
452 | } | ||
453 | #endif | ||
454 | 349 | ||
455 | spi_gpio->bitbang.master = spi_master_get(master); | 350 | spi_gpio->bitbang.master = spi_master_get(master); |
456 | spi_gpio->bitbang.chipselect = spi_gpio_chipselect; | 351 | spi_gpio->bitbang.chipselect = spi_gpio_chipselect; |
@@ -484,7 +379,7 @@ gpio_free: | |||
484 | return status; | 379 | return status; |
485 | } | 380 | } |
486 | 381 | ||
487 | static int spi_gpio_remove(struct platform_device *pdev) | 382 | static int __exit spi_gpio_remove(struct platform_device *pdev) |
488 | { | 383 | { |
489 | struct spi_gpio *spi_gpio; | 384 | struct spi_gpio *spi_gpio; |
490 | struct spi_gpio_platform_data *pdata; | 385 | struct spi_gpio_platform_data *pdata; |
@@ -511,15 +406,23 @@ static int spi_gpio_remove(struct platform_device *pdev) | |||
511 | MODULE_ALIAS("platform:" DRIVER_NAME); | 406 | MODULE_ALIAS("platform:" DRIVER_NAME); |
512 | 407 | ||
513 | static struct platform_driver spi_gpio_driver = { | 408 | static struct platform_driver spi_gpio_driver = { |
514 | .driver = { | 409 | .driver.name = DRIVER_NAME, |
515 | .name = DRIVER_NAME, | 410 | .driver.owner = THIS_MODULE, |
516 | .owner = THIS_MODULE, | 411 | .remove = __exit_p(spi_gpio_remove), |
517 | .of_match_table = of_match_ptr(spi_gpio_dt_ids), | ||
518 | }, | ||
519 | .probe = spi_gpio_probe, | ||
520 | .remove = spi_gpio_remove, | ||
521 | }; | 412 | }; |
522 | module_platform_driver(spi_gpio_driver); | 413 | |
414 | static int __init spi_gpio_init(void) | ||
415 | { | ||
416 | return platform_driver_probe(&spi_gpio_driver, spi_gpio_probe); | ||
417 | } | ||
418 | module_init(spi_gpio_init); | ||
419 | |||
420 | static void __exit spi_gpio_exit(void) | ||
421 | { | ||
422 | platform_driver_unregister(&spi_gpio_driver); | ||
423 | } | ||
424 | module_exit(spi_gpio_exit); | ||
425 | |||
523 | 426 | ||
524 | MODULE_DESCRIPTION("SPI master driver using generic bitbanged GPIO "); | 427 | MODULE_DESCRIPTION("SPI master driver using generic bitbanged GPIO "); |
525 | MODULE_AUTHOR("David Brownell"); | 428 | MODULE_AUTHOR("David Brownell"); |
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 904913290aa..fa594d604ac 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c | |||
@@ -37,9 +37,8 @@ | |||
37 | #include <linux/of.h> | 37 | #include <linux/of.h> |
38 | #include <linux/of_device.h> | 38 | #include <linux/of_device.h> |
39 | #include <linux/of_gpio.h> | 39 | #include <linux/of_gpio.h> |
40 | #include <linux/pinctrl/consumer.h> | ||
41 | 40 | ||
42 | #include <linux/platform_data/spi-imx.h> | 41 | #include <mach/spi.h> |
43 | 42 | ||
44 | #define DRIVER_NAME "spi_imx" | 43 | #define DRIVER_NAME "spi_imx" |
45 | 44 | ||
@@ -84,10 +83,9 @@ struct spi_imx_data { | |||
84 | struct spi_bitbang bitbang; | 83 | struct spi_bitbang bitbang; |
85 | 84 | ||
86 | struct completion xfer_done; | 85 | struct completion xfer_done; |
87 | void __iomem *base; | 86 | void *base; |
88 | int irq; | 87 | int irq; |
89 | struct clk *clk_per; | 88 | struct clk *clk; |
90 | struct clk *clk_ipg; | ||
91 | unsigned long spi_clk; | 89 | unsigned long spi_clk; |
92 | 90 | ||
93 | unsigned int count; | 91 | unsigned int count; |
@@ -97,7 +95,7 @@ struct spi_imx_data { | |||
97 | const void *tx_buf; | 95 | const void *tx_buf; |
98 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | 96 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
99 | 97 | ||
100 | const struct spi_imx_devtype_data *devtype_data; | 98 | struct spi_imx_devtype_data *devtype_data; |
101 | int chipselect[0]; | 99 | int chipselect[0]; |
102 | }; | 100 | }; |
103 | 101 | ||
@@ -197,7 +195,6 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin, | |||
197 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | 195 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) |
198 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | 196 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) |
199 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | 197 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) |
200 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) | ||
201 | 198 | ||
202 | #define MX51_ECSPI_INT 0x10 | 199 | #define MX51_ECSPI_INT 0x10 |
203 | #define MX51_ECSPI_INT_TEEN (1 << 0) | 200 | #define MX51_ECSPI_INT_TEEN (1 << 0) |
@@ -288,10 +285,9 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, | |||
288 | if (config->mode & SPI_CPHA) | 285 | if (config->mode & SPI_CPHA) |
289 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); | 286 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
290 | 287 | ||
291 | if (config->mode & SPI_CPOL) { | 288 | if (config->mode & SPI_CPOL) |
292 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); | 289 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
293 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); | 290 | |
294 | } | ||
295 | if (config->mode & SPI_CS_HIGH) | 291 | if (config->mode & SPI_CS_HIGH) |
296 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); | 292 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
297 | 293 | ||
@@ -628,7 +624,7 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active) | |||
628 | int active = is_active != BITBANG_CS_INACTIVE; | 624 | int active = is_active != BITBANG_CS_INACTIVE; |
629 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | 625 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
630 | 626 | ||
631 | if (!gpio_is_valid(gpio)) | 627 | if (gpio < 0) |
632 | return; | 628 | return; |
633 | 629 | ||
634 | gpio_set_value(gpio, dev_is_lowactive ^ active); | 630 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
@@ -690,6 +686,8 @@ static int spi_imx_setupxfer(struct spi_device *spi, | |||
690 | config.speed_hz = spi->max_speed_hz; | 686 | config.speed_hz = spi->max_speed_hz; |
691 | if (!config.bpw) | 687 | if (!config.bpw) |
692 | config.bpw = spi->bits_per_word; | 688 | config.bpw = spi->bits_per_word; |
689 | if (!config.speed_hz) | ||
690 | config.speed_hz = spi->max_speed_hz; | ||
693 | 691 | ||
694 | /* Initialize the functions for transfer */ | 692 | /* Initialize the functions for transfer */ |
695 | if (config.bpw <= 8) { | 693 | if (config.bpw <= 8) { |
@@ -738,7 +736,7 @@ static int spi_imx_setup(struct spi_device *spi) | |||
738 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, | 736 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
739 | spi->mode, spi->bits_per_word, spi->max_speed_hz); | 737 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
740 | 738 | ||
741 | if (gpio_is_valid(gpio)) | 739 | if (gpio >= 0) |
742 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | 740 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
743 | 741 | ||
744 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); | 742 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
@@ -750,7 +748,7 @@ static void spi_imx_cleanup(struct spi_device *spi) | |||
750 | { | 748 | { |
751 | } | 749 | } |
752 | 750 | ||
753 | static int spi_imx_probe(struct platform_device *pdev) | 751 | static int __devinit spi_imx_probe(struct platform_device *pdev) |
754 | { | 752 | { |
755 | struct device_node *np = pdev->dev.of_node; | 753 | struct device_node *np = pdev->dev.of_node; |
756 | const struct of_device_id *of_id = | 754 | const struct of_device_id *of_id = |
@@ -760,7 +758,6 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
760 | struct spi_master *master; | 758 | struct spi_master *master; |
761 | struct spi_imx_data *spi_imx; | 759 | struct spi_imx_data *spi_imx; |
762 | struct resource *res; | 760 | struct resource *res; |
763 | struct pinctrl *pinctrl; | ||
764 | int i, ret, num_cs; | 761 | int i, ret, num_cs; |
765 | 762 | ||
766 | if (!np && !mxc_platform_info) { | 763 | if (!np && !mxc_platform_info) { |
@@ -769,12 +766,8 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
769 | } | 766 | } |
770 | 767 | ||
771 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); | 768 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); |
772 | if (ret < 0) { | 769 | if (ret < 0) |
773 | if (mxc_platform_info) | 770 | num_cs = mxc_platform_info->num_chipselect; |
774 | num_cs = mxc_platform_info->num_chipselect; | ||
775 | else | ||
776 | return ret; | ||
777 | } | ||
778 | 771 | ||
779 | master = spi_alloc_master(&pdev->dev, | 772 | master = spi_alloc_master(&pdev->dev, |
780 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); | 773 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); |
@@ -791,17 +784,22 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
791 | 784 | ||
792 | for (i = 0; i < master->num_chipselect; i++) { | 785 | for (i = 0; i < master->num_chipselect; i++) { |
793 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); | 786 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
794 | if (!gpio_is_valid(cs_gpio) && mxc_platform_info) | 787 | if (cs_gpio < 0) |
795 | cs_gpio = mxc_platform_info->chipselect[i]; | 788 | cs_gpio = mxc_platform_info->chipselect[i]; |
796 | 789 | ||
797 | spi_imx->chipselect[i] = cs_gpio; | 790 | spi_imx->chipselect[i] = cs_gpio; |
798 | if (!gpio_is_valid(cs_gpio)) | 791 | if (cs_gpio < 0) |
799 | continue; | 792 | continue; |
800 | 793 | ||
801 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); | 794 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
802 | if (ret) { | 795 | if (ret) { |
796 | while (i > 0) { | ||
797 | i--; | ||
798 | if (spi_imx->chipselect[i] >= 0) | ||
799 | gpio_free(spi_imx->chipselect[i]); | ||
800 | } | ||
803 | dev_err(&pdev->dev, "can't get cs gpios\n"); | 801 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
804 | goto out_gpio_free; | 802 | goto out_master_put; |
805 | } | 803 | } |
806 | } | 804 | } |
807 | 805 | ||
@@ -848,28 +846,15 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
848 | goto out_iounmap; | 846 | goto out_iounmap; |
849 | } | 847 | } |
850 | 848 | ||
851 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | 849 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
852 | if (IS_ERR(pinctrl)) { | 850 | if (IS_ERR(spi_imx->clk)) { |
853 | ret = PTR_ERR(pinctrl); | 851 | dev_err(&pdev->dev, "unable to get clock\n"); |
854 | goto out_free_irq; | 852 | ret = PTR_ERR(spi_imx->clk); |
855 | } | ||
856 | |||
857 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); | ||
858 | if (IS_ERR(spi_imx->clk_ipg)) { | ||
859 | ret = PTR_ERR(spi_imx->clk_ipg); | ||
860 | goto out_free_irq; | ||
861 | } | ||
862 | |||
863 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); | ||
864 | if (IS_ERR(spi_imx->clk_per)) { | ||
865 | ret = PTR_ERR(spi_imx->clk_per); | ||
866 | goto out_free_irq; | 853 | goto out_free_irq; |
867 | } | 854 | } |
868 | 855 | ||
869 | clk_prepare_enable(spi_imx->clk_per); | 856 | clk_enable(spi_imx->clk); |
870 | clk_prepare_enable(spi_imx->clk_ipg); | 857 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); |
871 | |||
872 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | ||
873 | 858 | ||
874 | spi_imx->devtype_data->reset(spi_imx); | 859 | spi_imx->devtype_data->reset(spi_imx); |
875 | 860 | ||
@@ -887,8 +872,8 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
887 | return ret; | 872 | return ret; |
888 | 873 | ||
889 | out_clk_put: | 874 | out_clk_put: |
890 | clk_disable_unprepare(spi_imx->clk_per); | 875 | clk_disable(spi_imx->clk); |
891 | clk_disable_unprepare(spi_imx->clk_ipg); | 876 | clk_put(spi_imx->clk); |
892 | out_free_irq: | 877 | out_free_irq: |
893 | free_irq(spi_imx->irq, spi_imx); | 878 | free_irq(spi_imx->irq, spi_imx); |
894 | out_iounmap: | 879 | out_iounmap: |
@@ -896,17 +881,17 @@ out_iounmap: | |||
896 | out_release_mem: | 881 | out_release_mem: |
897 | release_mem_region(res->start, resource_size(res)); | 882 | release_mem_region(res->start, resource_size(res)); |
898 | out_gpio_free: | 883 | out_gpio_free: |
899 | while (--i >= 0) { | 884 | for (i = 0; i < master->num_chipselect; i++) |
900 | if (gpio_is_valid(spi_imx->chipselect[i])) | 885 | if (spi_imx->chipselect[i] >= 0) |
901 | gpio_free(spi_imx->chipselect[i]); | 886 | gpio_free(spi_imx->chipselect[i]); |
902 | } | 887 | out_master_put: |
903 | spi_master_put(master); | 888 | spi_master_put(master); |
904 | kfree(master); | 889 | kfree(master); |
905 | platform_set_drvdata(pdev, NULL); | 890 | platform_set_drvdata(pdev, NULL); |
906 | return ret; | 891 | return ret; |
907 | } | 892 | } |
908 | 893 | ||
909 | static int spi_imx_remove(struct platform_device *pdev) | 894 | static int __devexit spi_imx_remove(struct platform_device *pdev) |
910 | { | 895 | { |
911 | struct spi_master *master = platform_get_drvdata(pdev); | 896 | struct spi_master *master = platform_get_drvdata(pdev); |
912 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 897 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -916,13 +901,13 @@ static int spi_imx_remove(struct platform_device *pdev) | |||
916 | spi_bitbang_stop(&spi_imx->bitbang); | 901 | spi_bitbang_stop(&spi_imx->bitbang); |
917 | 902 | ||
918 | writel(0, spi_imx->base + MXC_CSPICTRL); | 903 | writel(0, spi_imx->base + MXC_CSPICTRL); |
919 | clk_disable_unprepare(spi_imx->clk_per); | 904 | clk_disable(spi_imx->clk); |
920 | clk_disable_unprepare(spi_imx->clk_ipg); | 905 | clk_put(spi_imx->clk); |
921 | free_irq(spi_imx->irq, spi_imx); | 906 | free_irq(spi_imx->irq, spi_imx); |
922 | iounmap(spi_imx->base); | 907 | iounmap(spi_imx->base); |
923 | 908 | ||
924 | for (i = 0; i < master->num_chipselect; i++) | 909 | for (i = 0; i < master->num_chipselect; i++) |
925 | if (gpio_is_valid(spi_imx->chipselect[i])) | 910 | if (spi_imx->chipselect[i] >= 0) |
926 | gpio_free(spi_imx->chipselect[i]); | 911 | gpio_free(spi_imx->chipselect[i]); |
927 | 912 | ||
928 | spi_master_put(master); | 913 | spi_master_put(master); |
@@ -942,9 +927,21 @@ static struct platform_driver spi_imx_driver = { | |||
942 | }, | 927 | }, |
943 | .id_table = spi_imx_devtype, | 928 | .id_table = spi_imx_devtype, |
944 | .probe = spi_imx_probe, | 929 | .probe = spi_imx_probe, |
945 | .remove = spi_imx_remove, | 930 | .remove = __devexit_p(spi_imx_remove), |
946 | }; | 931 | }; |
947 | module_platform_driver(spi_imx_driver); | 932 | |
933 | static int __init spi_imx_init(void) | ||
934 | { | ||
935 | return platform_driver_register(&spi_imx_driver); | ||
936 | } | ||
937 | |||
938 | static void __exit spi_imx_exit(void) | ||
939 | { | ||
940 | platform_driver_unregister(&spi_imx_driver); | ||
941 | } | ||
942 | |||
943 | module_init(spi_imx_init); | ||
944 | module_exit(spi_imx_exit); | ||
948 | 945 | ||
949 | MODULE_DESCRIPTION("SPI Master Controller driver"); | 946 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
950 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | 947 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
diff --git a/drivers/spi/spi-lm70llp.c b/drivers/spi/spi-lm70llp.c index 0759b5db988..933eb9d9ddd 100644 --- a/drivers/spi/spi-lm70llp.c +++ b/drivers/spi/spi-lm70llp.c | |||
@@ -219,6 +219,9 @@ static void spi_lm70llp_attach(struct parport *p) | |||
219 | } | 219 | } |
220 | pp = spi_master_get_devdata(master); | 220 | pp = spi_master_get_devdata(master); |
221 | 221 | ||
222 | master->bus_num = -1; /* dynamic alloc of a bus number */ | ||
223 | master->num_chipselect = 1; | ||
224 | |||
222 | /* | 225 | /* |
223 | * SPI and bitbang hookup. | 226 | * SPI and bitbang hookup. |
224 | */ | 227 | */ |
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c index cb3a3106bd4..6a5b4238fb6 100644 --- a/drivers/spi/spi-mpc512x-psc.c +++ b/drivers/spi/spi-mpc512x-psc.c | |||
@@ -406,7 +406,7 @@ static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) | |||
406 | } | 406 | } |
407 | 407 | ||
408 | /* bus_num is used only for the case dev->platform_data == NULL */ | 408 | /* bus_num is used only for the case dev->platform_data == NULL */ |
409 | static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, | 409 | static int __devinit mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, |
410 | u32 size, unsigned int irq, | 410 | u32 size, unsigned int irq, |
411 | s16 bus_num) | 411 | s16 bus_num) |
412 | { | 412 | { |
@@ -492,9 +492,9 @@ free_master: | |||
492 | return ret; | 492 | return ret; |
493 | } | 493 | } |
494 | 494 | ||
495 | static int mpc512x_psc_spi_do_remove(struct device *dev) | 495 | static int __devexit mpc512x_psc_spi_do_remove(struct device *dev) |
496 | { | 496 | { |
497 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); | 497 | struct spi_master *master = dev_get_drvdata(dev); |
498 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); | 498 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); |
499 | 499 | ||
500 | flush_workqueue(mps->workqueue); | 500 | flush_workqueue(mps->workqueue); |
@@ -503,12 +503,11 @@ static int mpc512x_psc_spi_do_remove(struct device *dev) | |||
503 | free_irq(mps->irq, mps); | 503 | free_irq(mps->irq, mps); |
504 | if (mps->psc) | 504 | if (mps->psc) |
505 | iounmap(mps->psc); | 505 | iounmap(mps->psc); |
506 | spi_master_put(master); | ||
507 | 506 | ||
508 | return 0; | 507 | return 0; |
509 | } | 508 | } |
510 | 509 | ||
511 | static int mpc512x_psc_spi_of_probe(struct platform_device *op) | 510 | static int __devinit mpc512x_psc_spi_of_probe(struct platform_device *op) |
512 | { | 511 | { |
513 | const u32 *regaddr_p; | 512 | const u32 *regaddr_p; |
514 | u64 regaddr64, size64; | 513 | u64 regaddr64, size64; |
@@ -539,7 +538,7 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op) | |||
539 | irq_of_parse_and_map(op->dev.of_node, 0), id); | 538 | irq_of_parse_and_map(op->dev.of_node, 0), id); |
540 | } | 539 | } |
541 | 540 | ||
542 | static int mpc512x_psc_spi_of_remove(struct platform_device *op) | 541 | static int __devexit mpc512x_psc_spi_of_remove(struct platform_device *op) |
543 | { | 542 | { |
544 | return mpc512x_psc_spi_do_remove(&op->dev); | 543 | return mpc512x_psc_spi_do_remove(&op->dev); |
545 | } | 544 | } |
@@ -553,14 +552,25 @@ MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); | |||
553 | 552 | ||
554 | static struct platform_driver mpc512x_psc_spi_of_driver = { | 553 | static struct platform_driver mpc512x_psc_spi_of_driver = { |
555 | .probe = mpc512x_psc_spi_of_probe, | 554 | .probe = mpc512x_psc_spi_of_probe, |
556 | .remove = mpc512x_psc_spi_of_remove, | 555 | .remove = __devexit_p(mpc512x_psc_spi_of_remove), |
557 | .driver = { | 556 | .driver = { |
558 | .name = "mpc512x-psc-spi", | 557 | .name = "mpc512x-psc-spi", |
559 | .owner = THIS_MODULE, | 558 | .owner = THIS_MODULE, |
560 | .of_match_table = mpc512x_psc_spi_of_match, | 559 | .of_match_table = mpc512x_psc_spi_of_match, |
561 | }, | 560 | }, |
562 | }; | 561 | }; |
563 | module_platform_driver(mpc512x_psc_spi_of_driver); | 562 | |
563 | static int __init mpc512x_psc_spi_init(void) | ||
564 | { | ||
565 | return platform_driver_register(&mpc512x_psc_spi_of_driver); | ||
566 | } | ||
567 | module_init(mpc512x_psc_spi_init); | ||
568 | |||
569 | static void __exit mpc512x_psc_spi_exit(void) | ||
570 | { | ||
571 | platform_driver_unregister(&mpc512x_psc_spi_of_driver); | ||
572 | } | ||
573 | module_exit(mpc512x_psc_spi_exit); | ||
564 | 574 | ||
565 | MODULE_AUTHOR("John Rigby"); | 575 | MODULE_AUTHOR("John Rigby"); |
566 | MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); | 576 | MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); |
diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c index 291120b37db..e30baf0852a 100644 --- a/drivers/spi/spi-mpc52xx-psc.c +++ b/drivers/spi/spi-mpc52xx-psc.c | |||
@@ -363,7 +363,7 @@ static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) | |||
363 | } | 363 | } |
364 | 364 | ||
365 | /* bus_num is used only for the case dev->platform_data == NULL */ | 365 | /* bus_num is used only for the case dev->platform_data == NULL */ |
366 | static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, | 366 | static int __devinit mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, |
367 | u32 size, unsigned int irq, s16 bus_num) | 367 | u32 size, unsigned int irq, s16 bus_num) |
368 | { | 368 | { |
369 | struct fsl_spi_platform_data *pdata = dev->platform_data; | 369 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
@@ -450,7 +450,7 @@ free_master: | |||
450 | return ret; | 450 | return ret; |
451 | } | 451 | } |
452 | 452 | ||
453 | static int mpc52xx_psc_spi_of_probe(struct platform_device *op) | 453 | static int __devinit mpc52xx_psc_spi_of_probe(struct platform_device *op) |
454 | { | 454 | { |
455 | const u32 *regaddr_p; | 455 | const u32 *regaddr_p; |
456 | u64 regaddr64, size64; | 456 | u64 regaddr64, size64; |
@@ -479,9 +479,9 @@ static int mpc52xx_psc_spi_of_probe(struct platform_device *op) | |||
479 | irq_of_parse_and_map(op->dev.of_node, 0), id); | 479 | irq_of_parse_and_map(op->dev.of_node, 0), id); |
480 | } | 480 | } |
481 | 481 | ||
482 | static int mpc52xx_psc_spi_of_remove(struct platform_device *op) | 482 | static int __devexit mpc52xx_psc_spi_of_remove(struct platform_device *op) |
483 | { | 483 | { |
484 | struct spi_master *master = spi_master_get(dev_get_drvdata(&op->dev)); | 484 | struct spi_master *master = dev_get_drvdata(&op->dev); |
485 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); | 485 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); |
486 | 486 | ||
487 | flush_workqueue(mps->workqueue); | 487 | flush_workqueue(mps->workqueue); |
@@ -490,7 +490,6 @@ static int mpc52xx_psc_spi_of_remove(struct platform_device *op) | |||
490 | free_irq(mps->irq, mps); | 490 | free_irq(mps->irq, mps); |
491 | if (mps->psc) | 491 | if (mps->psc) |
492 | iounmap(mps->psc); | 492 | iounmap(mps->psc); |
493 | spi_master_put(master); | ||
494 | 493 | ||
495 | return 0; | 494 | return 0; |
496 | } | 495 | } |
@@ -505,14 +504,25 @@ MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match); | |||
505 | 504 | ||
506 | static struct platform_driver mpc52xx_psc_spi_of_driver = { | 505 | static struct platform_driver mpc52xx_psc_spi_of_driver = { |
507 | .probe = mpc52xx_psc_spi_of_probe, | 506 | .probe = mpc52xx_psc_spi_of_probe, |
508 | .remove = mpc52xx_psc_spi_of_remove, | 507 | .remove = __devexit_p(mpc52xx_psc_spi_of_remove), |
509 | .driver = { | 508 | .driver = { |
510 | .name = "mpc52xx-psc-spi", | 509 | .name = "mpc52xx-psc-spi", |
511 | .owner = THIS_MODULE, | 510 | .owner = THIS_MODULE, |
512 | .of_match_table = mpc52xx_psc_spi_of_match, | 511 | .of_match_table = mpc52xx_psc_spi_of_match, |
513 | }, | 512 | }, |
514 | }; | 513 | }; |
515 | module_platform_driver(mpc52xx_psc_spi_of_driver); | 514 | |
515 | static int __init mpc52xx_psc_spi_init(void) | ||
516 | { | ||
517 | return platform_driver_register(&mpc52xx_psc_spi_of_driver); | ||
518 | } | ||
519 | module_init(mpc52xx_psc_spi_init); | ||
520 | |||
521 | static void __exit mpc52xx_psc_spi_exit(void) | ||
522 | { | ||
523 | platform_driver_unregister(&mpc52xx_psc_spi_of_driver); | ||
524 | } | ||
525 | module_exit(mpc52xx_psc_spi_exit); | ||
516 | 526 | ||
517 | MODULE_AUTHOR("Dragos Carp"); | 527 | MODULE_AUTHOR("Dragos Carp"); |
518 | MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); | 528 | MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); |
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c index 29f77056eed..015a974bed7 100644 --- a/drivers/spi/spi-mpc52xx.c +++ b/drivers/spi/spi-mpc52xx.c | |||
@@ -390,7 +390,7 @@ static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) | |||
390 | /* | 390 | /* |
391 | * OF Platform Bus Binding | 391 | * OF Platform Bus Binding |
392 | */ | 392 | */ |
393 | static int mpc52xx_spi_probe(struct platform_device *op) | 393 | static int __devinit mpc52xx_spi_probe(struct platform_device *op) |
394 | { | 394 | { |
395 | struct spi_master *master; | 395 | struct spi_master *master; |
396 | struct mpc52xx_spi *ms; | 396 | struct mpc52xx_spi *ms; |
@@ -433,6 +433,7 @@ static int mpc52xx_spi_probe(struct platform_device *op) | |||
433 | goto err_alloc; | 433 | goto err_alloc; |
434 | } | 434 | } |
435 | 435 | ||
436 | master->bus_num = -1; | ||
436 | master->setup = mpc52xx_spi_setup; | 437 | master->setup = mpc52xx_spi_setup; |
437 | master->transfer = mpc52xx_spi_transfer; | 438 | master->transfer = mpc52xx_spi_transfer; |
438 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | 439 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
@@ -454,7 +455,7 @@ static int mpc52xx_spi_probe(struct platform_device *op) | |||
454 | GFP_KERNEL); | 455 | GFP_KERNEL); |
455 | if (!ms->gpio_cs) { | 456 | if (!ms->gpio_cs) { |
456 | rc = -ENOMEM; | 457 | rc = -ENOMEM; |
457 | goto err_alloc_gpio; | 458 | goto err_alloc; |
458 | } | 459 | } |
459 | 460 | ||
460 | for (i = 0; i < ms->gpio_cs_count; i++) { | 461 | for (i = 0; i < ms->gpio_cs_count; i++) { |
@@ -478,6 +479,8 @@ static int mpc52xx_spi_probe(struct platform_device *op) | |||
478 | gpio_direction_output(gpio_cs, 1); | 479 | gpio_direction_output(gpio_cs, 1); |
479 | ms->gpio_cs[i] = gpio_cs; | 480 | ms->gpio_cs[i] = gpio_cs; |
480 | } | 481 | } |
482 | } else { | ||
483 | master->num_chipselect = 1; | ||
481 | } | 484 | } |
482 | 485 | ||
483 | spin_lock_init(&ms->lock); | 486 | spin_lock_init(&ms->lock); |
@@ -514,22 +517,21 @@ static int mpc52xx_spi_probe(struct platform_device *op) | |||
514 | 517 | ||
515 | err_register: | 518 | err_register: |
516 | dev_err(&ms->master->dev, "initialization failed\n"); | 519 | dev_err(&ms->master->dev, "initialization failed\n"); |
520 | spi_master_put(master); | ||
517 | err_gpio: | 521 | err_gpio: |
518 | while (i-- > 0) | 522 | while (i-- > 0) |
519 | gpio_free(ms->gpio_cs[i]); | 523 | gpio_free(ms->gpio_cs[i]); |
520 | 524 | ||
521 | kfree(ms->gpio_cs); | 525 | kfree(ms->gpio_cs); |
522 | err_alloc_gpio: | ||
523 | spi_master_put(master); | ||
524 | err_alloc: | 526 | err_alloc: |
525 | err_init: | 527 | err_init: |
526 | iounmap(regs); | 528 | iounmap(regs); |
527 | return rc; | 529 | return rc; |
528 | } | 530 | } |
529 | 531 | ||
530 | static int mpc52xx_spi_remove(struct platform_device *op) | 532 | static int __devexit mpc52xx_spi_remove(struct platform_device *op) |
531 | { | 533 | { |
532 | struct spi_master *master = spi_master_get(dev_get_drvdata(&op->dev)); | 534 | struct spi_master *master = dev_get_drvdata(&op->dev); |
533 | struct mpc52xx_spi *ms = spi_master_get_devdata(master); | 535 | struct mpc52xx_spi *ms = spi_master_get_devdata(master); |
534 | int i; | 536 | int i; |
535 | 537 | ||
@@ -541,13 +543,13 @@ static int mpc52xx_spi_remove(struct platform_device *op) | |||
541 | 543 | ||
542 | kfree(ms->gpio_cs); | 544 | kfree(ms->gpio_cs); |
543 | spi_unregister_master(master); | 545 | spi_unregister_master(master); |
544 | iounmap(ms->regs); | ||
545 | spi_master_put(master); | 546 | spi_master_put(master); |
547 | iounmap(ms->regs); | ||
546 | 548 | ||
547 | return 0; | 549 | return 0; |
548 | } | 550 | } |
549 | 551 | ||
550 | static const struct of_device_id mpc52xx_spi_match[] = { | 552 | static const struct of_device_id mpc52xx_spi_match[] __devinitconst = { |
551 | { .compatible = "fsl,mpc5200-spi", }, | 553 | { .compatible = "fsl,mpc5200-spi", }, |
552 | {} | 554 | {} |
553 | }; | 555 | }; |
@@ -560,6 +562,18 @@ static struct platform_driver mpc52xx_spi_of_driver = { | |||
560 | .of_match_table = mpc52xx_spi_match, | 562 | .of_match_table = mpc52xx_spi_match, |
561 | }, | 563 | }, |
562 | .probe = mpc52xx_spi_probe, | 564 | .probe = mpc52xx_spi_probe, |
563 | .remove = mpc52xx_spi_remove, | 565 | .remove = __devexit_p(mpc52xx_spi_remove), |
564 | }; | 566 | }; |
565 | module_platform_driver(mpc52xx_spi_of_driver); | 567 | |
568 | static int __init mpc52xx_spi_init(void) | ||
569 | { | ||
570 | return platform_driver_register(&mpc52xx_spi_of_driver); | ||
571 | } | ||
572 | module_init(mpc52xx_spi_init); | ||
573 | |||
574 | static void __exit mpc52xx_spi_exit(void) | ||
575 | { | ||
576 | platform_driver_unregister(&mpc52xx_spi_of_driver); | ||
577 | } | ||
578 | module_exit(mpc52xx_spi_exit); | ||
579 | |||
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c deleted file mode 100644 index a3ede249d05..00000000000 --- a/drivers/spi/spi-mxs.c +++ /dev/null | |||
@@ -1,675 +0,0 @@ | |||
1 | /* | ||
2 | * Freescale MXS SPI master driver | ||
3 | * | ||
4 | * Copyright 2012 DENX Software Engineering, GmbH. | ||
5 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
6 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | ||
7 | * | ||
8 | * Rework and transition to new API by: | ||
9 | * Marek Vasut <marex@denx.de> | ||
10 | * | ||
11 | * Based on previous attempt by: | ||
12 | * Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | * | ||
14 | * Based on code from U-Boot bootloader by: | ||
15 | * Marek Vasut <marex@denx.de> | ||
16 | * | ||
17 | * Based on spi-stmp.c, which is: | ||
18 | * Author: Dmitry Pervushin <dimka@embeddedalley.com> | ||
19 | * | ||
20 | * This program is free software; you can redistribute it and/or modify | ||
21 | * it under the terms of the GNU General Public License as published by | ||
22 | * the Free Software Foundation; either version 2 of the License, or | ||
23 | * (at your option) any later version. | ||
24 | * | ||
25 | * This program is distributed in the hope that it will be useful, | ||
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
28 | * GNU General Public License for more details. | ||
29 | */ | ||
30 | |||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/init.h> | ||
33 | #include <linux/ioport.h> | ||
34 | #include <linux/of.h> | ||
35 | #include <linux/of_device.h> | ||
36 | #include <linux/of_gpio.h> | ||
37 | #include <linux/platform_device.h> | ||
38 | #include <linux/delay.h> | ||
39 | #include <linux/interrupt.h> | ||
40 | #include <linux/dma-mapping.h> | ||
41 | #include <linux/dmaengine.h> | ||
42 | #include <linux/highmem.h> | ||
43 | #include <linux/clk.h> | ||
44 | #include <linux/err.h> | ||
45 | #include <linux/completion.h> | ||
46 | #include <linux/gpio.h> | ||
47 | #include <linux/regulator/consumer.h> | ||
48 | #include <linux/module.h> | ||
49 | #include <linux/pinctrl/consumer.h> | ||
50 | #include <linux/stmp_device.h> | ||
51 | #include <linux/spi/spi.h> | ||
52 | #include <linux/spi/mxs-spi.h> | ||
53 | |||
54 | #define DRIVER_NAME "mxs-spi" | ||
55 | |||
56 | /* Use 10S timeout for very long transfers, it should suffice. */ | ||
57 | #define SSP_TIMEOUT 10000 | ||
58 | |||
59 | #define SG_MAXLEN 0xff00 | ||
60 | |||
61 | struct mxs_spi { | ||
62 | struct mxs_ssp ssp; | ||
63 | struct completion c; | ||
64 | }; | ||
65 | |||
66 | static int mxs_spi_setup_transfer(struct spi_device *dev, | ||
67 | struct spi_transfer *t) | ||
68 | { | ||
69 | struct mxs_spi *spi = spi_master_get_devdata(dev->master); | ||
70 | struct mxs_ssp *ssp = &spi->ssp; | ||
71 | uint8_t bits_per_word; | ||
72 | uint32_t hz = 0; | ||
73 | |||
74 | bits_per_word = dev->bits_per_word; | ||
75 | if (t && t->bits_per_word) | ||
76 | bits_per_word = t->bits_per_word; | ||
77 | |||
78 | if (bits_per_word != 8) { | ||
79 | dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n", | ||
80 | __func__, bits_per_word); | ||
81 | return -EINVAL; | ||
82 | } | ||
83 | |||
84 | hz = dev->max_speed_hz; | ||
85 | if (t && t->speed_hz) | ||
86 | hz = min(hz, t->speed_hz); | ||
87 | if (hz == 0) { | ||
88 | dev_err(&dev->dev, "Cannot continue with zero clock\n"); | ||
89 | return -EINVAL; | ||
90 | } | ||
91 | |||
92 | mxs_ssp_set_clk_rate(ssp, hz); | ||
93 | |||
94 | writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | | ||
95 | BF_SSP_CTRL1_WORD_LENGTH | ||
96 | (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | | ||
97 | ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | | ||
98 | ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), | ||
99 | ssp->base + HW_SSP_CTRL1(ssp)); | ||
100 | |||
101 | writel(0x0, ssp->base + HW_SSP_CMD0); | ||
102 | writel(0x0, ssp->base + HW_SSP_CMD1); | ||
103 | |||
104 | return 0; | ||
105 | } | ||
106 | |||
107 | static int mxs_spi_setup(struct spi_device *dev) | ||
108 | { | ||
109 | int err = 0; | ||
110 | |||
111 | if (!dev->bits_per_word) | ||
112 | dev->bits_per_word = 8; | ||
113 | |||
114 | if (dev->mode & ~(SPI_CPOL | SPI_CPHA)) | ||
115 | return -EINVAL; | ||
116 | |||
117 | err = mxs_spi_setup_transfer(dev, NULL); | ||
118 | if (err) { | ||
119 | dev_err(&dev->dev, | ||
120 | "Failed to setup transfer, error = %d\n", err); | ||
121 | } | ||
122 | |||
123 | return err; | ||
124 | } | ||
125 | |||
126 | static uint32_t mxs_spi_cs_to_reg(unsigned cs) | ||
127 | { | ||
128 | uint32_t select = 0; | ||
129 | |||
130 | /* | ||
131 | * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 | ||
132 | * | ||
133 | * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ | ||
134 | * in HW_SSP_CTRL0 register do have multiple usage, please refer to | ||
135 | * the datasheet for further details. In SPI mode, they are used to | ||
136 | * toggle the chip-select lines (nCS pins). | ||
137 | */ | ||
138 | if (cs & 1) | ||
139 | select |= BM_SSP_CTRL0_WAIT_FOR_CMD; | ||
140 | if (cs & 2) | ||
141 | select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; | ||
142 | |||
143 | return select; | ||
144 | } | ||
145 | |||
146 | static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) | ||
147 | { | ||
148 | const uint32_t mask = | ||
149 | BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ; | ||
150 | uint32_t select; | ||
151 | struct mxs_ssp *ssp = &spi->ssp; | ||
152 | |||
153 | writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | ||
154 | select = mxs_spi_cs_to_reg(cs); | ||
155 | writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
156 | } | ||
157 | |||
158 | static inline void mxs_spi_enable(struct mxs_spi *spi) | ||
159 | { | ||
160 | struct mxs_ssp *ssp = &spi->ssp; | ||
161 | |||
162 | writel(BM_SSP_CTRL0_LOCK_CS, | ||
163 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
164 | writel(BM_SSP_CTRL0_IGNORE_CRC, | ||
165 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | ||
166 | } | ||
167 | |||
168 | static inline void mxs_spi_disable(struct mxs_spi *spi) | ||
169 | { | ||
170 | struct mxs_ssp *ssp = &spi->ssp; | ||
171 | |||
172 | writel(BM_SSP_CTRL0_LOCK_CS, | ||
173 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | ||
174 | writel(BM_SSP_CTRL0_IGNORE_CRC, | ||
175 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
176 | } | ||
177 | |||
178 | static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) | ||
179 | { | ||
180 | const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); | ||
181 | struct mxs_ssp *ssp = &spi->ssp; | ||
182 | uint32_t reg; | ||
183 | |||
184 | do { | ||
185 | reg = readl_relaxed(ssp->base + offset); | ||
186 | |||
187 | if (!set) | ||
188 | reg = ~reg; | ||
189 | |||
190 | reg &= mask; | ||
191 | |||
192 | if (reg == mask) | ||
193 | return 0; | ||
194 | } while (time_before(jiffies, timeout)); | ||
195 | |||
196 | return -ETIMEDOUT; | ||
197 | } | ||
198 | |||
199 | static void mxs_ssp_dma_irq_callback(void *param) | ||
200 | { | ||
201 | struct mxs_spi *spi = param; | ||
202 | complete(&spi->c); | ||
203 | } | ||
204 | |||
205 | static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) | ||
206 | { | ||
207 | struct mxs_ssp *ssp = dev_id; | ||
208 | dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", | ||
209 | __func__, __LINE__, | ||
210 | readl(ssp->base + HW_SSP_CTRL1(ssp)), | ||
211 | readl(ssp->base + HW_SSP_STATUS(ssp))); | ||
212 | return IRQ_HANDLED; | ||
213 | } | ||
214 | |||
215 | static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, | ||
216 | unsigned char *buf, int len, | ||
217 | int *first, int *last, int write) | ||
218 | { | ||
219 | struct mxs_ssp *ssp = &spi->ssp; | ||
220 | struct dma_async_tx_descriptor *desc = NULL; | ||
221 | const bool vmalloced_buf = is_vmalloc_addr(buf); | ||
222 | const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN; | ||
223 | const int sgs = DIV_ROUND_UP(len, desc_len); | ||
224 | int sg_count; | ||
225 | int min, ret; | ||
226 | uint32_t ctrl0; | ||
227 | struct page *vm_page; | ||
228 | void *sg_buf; | ||
229 | struct { | ||
230 | uint32_t pio[4]; | ||
231 | struct scatterlist sg; | ||
232 | } *dma_xfer; | ||
233 | |||
234 | if (!len) | ||
235 | return -EINVAL; | ||
236 | |||
237 | dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL); | ||
238 | if (!dma_xfer) | ||
239 | return -ENOMEM; | ||
240 | |||
241 | INIT_COMPLETION(spi->c); | ||
242 | |||
243 | ctrl0 = readl(ssp->base + HW_SSP_CTRL0); | ||
244 | ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); | ||
245 | |||
246 | if (*first) | ||
247 | ctrl0 |= BM_SSP_CTRL0_LOCK_CS; | ||
248 | if (!write) | ||
249 | ctrl0 |= BM_SSP_CTRL0_READ; | ||
250 | |||
251 | /* Queue the DMA data transfer. */ | ||
252 | for (sg_count = 0; sg_count < sgs; sg_count++) { | ||
253 | min = min(len, desc_len); | ||
254 | |||
255 | /* Prepare the transfer descriptor. */ | ||
256 | if ((sg_count + 1 == sgs) && *last) | ||
257 | ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; | ||
258 | |||
259 | if (ssp->devid == IMX23_SSP) | ||
260 | ctrl0 |= min; | ||
261 | |||
262 | dma_xfer[sg_count].pio[0] = ctrl0; | ||
263 | dma_xfer[sg_count].pio[3] = min; | ||
264 | |||
265 | if (vmalloced_buf) { | ||
266 | vm_page = vmalloc_to_page(buf); | ||
267 | if (!vm_page) { | ||
268 | ret = -ENOMEM; | ||
269 | goto err_vmalloc; | ||
270 | } | ||
271 | sg_buf = page_address(vm_page) + | ||
272 | ((size_t)buf & ~PAGE_MASK); | ||
273 | } else { | ||
274 | sg_buf = buf; | ||
275 | } | ||
276 | |||
277 | sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min); | ||
278 | ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | ||
279 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | ||
280 | |||
281 | len -= min; | ||
282 | buf += min; | ||
283 | |||
284 | /* Queue the PIO register write transfer. */ | ||
285 | desc = dmaengine_prep_slave_sg(ssp->dmach, | ||
286 | (struct scatterlist *)dma_xfer[sg_count].pio, | ||
287 | (ssp->devid == IMX23_SSP) ? 1 : 4, | ||
288 | DMA_TRANS_NONE, | ||
289 | sg_count ? DMA_PREP_INTERRUPT : 0); | ||
290 | if (!desc) { | ||
291 | dev_err(ssp->dev, | ||
292 | "Failed to get PIO reg. write descriptor.\n"); | ||
293 | ret = -EINVAL; | ||
294 | goto err_mapped; | ||
295 | } | ||
296 | |||
297 | desc = dmaengine_prep_slave_sg(ssp->dmach, | ||
298 | &dma_xfer[sg_count].sg, 1, | ||
299 | write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | ||
300 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
301 | |||
302 | if (!desc) { | ||
303 | dev_err(ssp->dev, | ||
304 | "Failed to get DMA data write descriptor.\n"); | ||
305 | ret = -EINVAL; | ||
306 | goto err_mapped; | ||
307 | } | ||
308 | } | ||
309 | |||
310 | /* | ||
311 | * The last descriptor must have this callback, | ||
312 | * to finish the DMA transaction. | ||
313 | */ | ||
314 | desc->callback = mxs_ssp_dma_irq_callback; | ||
315 | desc->callback_param = spi; | ||
316 | |||
317 | /* Start the transfer. */ | ||
318 | dmaengine_submit(desc); | ||
319 | dma_async_issue_pending(ssp->dmach); | ||
320 | |||
321 | ret = wait_for_completion_timeout(&spi->c, | ||
322 | msecs_to_jiffies(SSP_TIMEOUT)); | ||
323 | if (!ret) { | ||
324 | dev_err(ssp->dev, "DMA transfer timeout\n"); | ||
325 | ret = -ETIMEDOUT; | ||
326 | dmaengine_terminate_all(ssp->dmach); | ||
327 | goto err_vmalloc; | ||
328 | } | ||
329 | |||
330 | ret = 0; | ||
331 | |||
332 | err_vmalloc: | ||
333 | while (--sg_count >= 0) { | ||
334 | err_mapped: | ||
335 | dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | ||
336 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | ||
337 | } | ||
338 | |||
339 | kfree(dma_xfer); | ||
340 | |||
341 | return ret; | ||
342 | } | ||
343 | |||
344 | static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs, | ||
345 | unsigned char *buf, int len, | ||
346 | int *first, int *last, int write) | ||
347 | { | ||
348 | struct mxs_ssp *ssp = &spi->ssp; | ||
349 | |||
350 | if (*first) | ||
351 | mxs_spi_enable(spi); | ||
352 | |||
353 | mxs_spi_set_cs(spi, cs); | ||
354 | |||
355 | while (len--) { | ||
356 | if (*last && len == 0) | ||
357 | mxs_spi_disable(spi); | ||
358 | |||
359 | if (ssp->devid == IMX23_SSP) { | ||
360 | writel(BM_SSP_CTRL0_XFER_COUNT, | ||
361 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | ||
362 | writel(1, | ||
363 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
364 | } else { | ||
365 | writel(1, ssp->base + HW_SSP_XFER_SIZE); | ||
366 | } | ||
367 | |||
368 | if (write) | ||
369 | writel(BM_SSP_CTRL0_READ, | ||
370 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | ||
371 | else | ||
372 | writel(BM_SSP_CTRL0_READ, | ||
373 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
374 | |||
375 | writel(BM_SSP_CTRL0_RUN, | ||
376 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
377 | |||
378 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) | ||
379 | return -ETIMEDOUT; | ||
380 | |||
381 | if (write) | ||
382 | writel(*buf, ssp->base + HW_SSP_DATA(ssp)); | ||
383 | |||
384 | writel(BM_SSP_CTRL0_DATA_XFER, | ||
385 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | ||
386 | |||
387 | if (!write) { | ||
388 | if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), | ||
389 | BM_SSP_STATUS_FIFO_EMPTY, 0)) | ||
390 | return -ETIMEDOUT; | ||
391 | |||
392 | *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); | ||
393 | } | ||
394 | |||
395 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) | ||
396 | return -ETIMEDOUT; | ||
397 | |||
398 | buf++; | ||
399 | } | ||
400 | |||
401 | if (len <= 0) | ||
402 | return 0; | ||
403 | |||
404 | return -ETIMEDOUT; | ||
405 | } | ||
406 | |||
407 | static int mxs_spi_transfer_one(struct spi_master *master, | ||
408 | struct spi_message *m) | ||
409 | { | ||
410 | struct mxs_spi *spi = spi_master_get_devdata(master); | ||
411 | struct mxs_ssp *ssp = &spi->ssp; | ||
412 | int first, last; | ||
413 | struct spi_transfer *t, *tmp_t; | ||
414 | int status = 0; | ||
415 | int cs; | ||
416 | |||
417 | first = last = 0; | ||
418 | |||
419 | cs = m->spi->chip_select; | ||
420 | |||
421 | list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { | ||
422 | |||
423 | status = mxs_spi_setup_transfer(m->spi, t); | ||
424 | if (status) | ||
425 | break; | ||
426 | |||
427 | if (&t->transfer_list == m->transfers.next) | ||
428 | first = 1; | ||
429 | if (&t->transfer_list == m->transfers.prev) | ||
430 | last = 1; | ||
431 | if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) { | ||
432 | dev_err(ssp->dev, | ||
433 | "Cannot send and receive simultaneously\n"); | ||
434 | status = -EINVAL; | ||
435 | break; | ||
436 | } | ||
437 | |||
438 | /* | ||
439 | * Small blocks can be transfered via PIO. | ||
440 | * Measured by empiric means: | ||
441 | * | ||
442 | * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1 | ||
443 | * | ||
444 | * DMA only: 2.164808 seconds, 473.0KB/s | ||
445 | * Combined: 1.676276 seconds, 610.9KB/s | ||
446 | */ | ||
447 | if (t->len < 32) { | ||
448 | writel(BM_SSP_CTRL1_DMA_ENABLE, | ||
449 | ssp->base + HW_SSP_CTRL1(ssp) + | ||
450 | STMP_OFFSET_REG_CLR); | ||
451 | |||
452 | if (t->tx_buf) | ||
453 | status = mxs_spi_txrx_pio(spi, cs, | ||
454 | (void *)t->tx_buf, | ||
455 | t->len, &first, &last, 1); | ||
456 | if (t->rx_buf) | ||
457 | status = mxs_spi_txrx_pio(spi, cs, | ||
458 | t->rx_buf, t->len, | ||
459 | &first, &last, 0); | ||
460 | } else { | ||
461 | writel(BM_SSP_CTRL1_DMA_ENABLE, | ||
462 | ssp->base + HW_SSP_CTRL1(ssp) + | ||
463 | STMP_OFFSET_REG_SET); | ||
464 | |||
465 | if (t->tx_buf) | ||
466 | status = mxs_spi_txrx_dma(spi, cs, | ||
467 | (void *)t->tx_buf, t->len, | ||
468 | &first, &last, 1); | ||
469 | if (t->rx_buf) | ||
470 | status = mxs_spi_txrx_dma(spi, cs, | ||
471 | t->rx_buf, t->len, | ||
472 | &first, &last, 0); | ||
473 | } | ||
474 | |||
475 | if (status) { | ||
476 | stmp_reset_block(ssp->base); | ||
477 | break; | ||
478 | } | ||
479 | |||
480 | m->actual_length += t->len; | ||
481 | first = last = 0; | ||
482 | } | ||
483 | |||
484 | m->status = status; | ||
485 | spi_finalize_current_message(master); | ||
486 | |||
487 | return status; | ||
488 | } | ||
489 | |||
490 | static bool mxs_ssp_dma_filter(struct dma_chan *chan, void *param) | ||
491 | { | ||
492 | struct mxs_ssp *ssp = param; | ||
493 | |||
494 | if (!mxs_dma_is_apbh(chan)) | ||
495 | return false; | ||
496 | |||
497 | if (chan->chan_id != ssp->dma_channel) | ||
498 | return false; | ||
499 | |||
500 | chan->private = &ssp->dma_data; | ||
501 | |||
502 | return true; | ||
503 | } | ||
504 | |||
505 | static const struct of_device_id mxs_spi_dt_ids[] = { | ||
506 | { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, | ||
507 | { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, | ||
508 | { /* sentinel */ } | ||
509 | }; | ||
510 | MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); | ||
511 | |||
512 | static int mxs_spi_probe(struct platform_device *pdev) | ||
513 | { | ||
514 | const struct of_device_id *of_id = | ||
515 | of_match_device(mxs_spi_dt_ids, &pdev->dev); | ||
516 | struct device_node *np = pdev->dev.of_node; | ||
517 | struct spi_master *master; | ||
518 | struct mxs_spi *spi; | ||
519 | struct mxs_ssp *ssp; | ||
520 | struct resource *iores, *dmares; | ||
521 | struct pinctrl *pinctrl; | ||
522 | struct clk *clk; | ||
523 | void __iomem *base; | ||
524 | int devid, dma_channel, clk_freq; | ||
525 | int ret = 0, irq_err, irq_dma; | ||
526 | dma_cap_mask_t mask; | ||
527 | |||
528 | /* | ||
529 | * Default clock speed for the SPI core. 160MHz seems to | ||
530 | * work reasonably well with most SPI flashes, so use this | ||
531 | * as a default. Override with "clock-frequency" DT prop. | ||
532 | */ | ||
533 | const int clk_freq_default = 160000000; | ||
534 | |||
535 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
536 | irq_err = platform_get_irq(pdev, 0); | ||
537 | irq_dma = platform_get_irq(pdev, 1); | ||
538 | if (!iores || irq_err < 0 || irq_dma < 0) | ||
539 | return -EINVAL; | ||
540 | |||
541 | base = devm_request_and_ioremap(&pdev->dev, iores); | ||
542 | if (!base) | ||
543 | return -EADDRNOTAVAIL; | ||
544 | |||
545 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
546 | if (IS_ERR(pinctrl)) | ||
547 | return PTR_ERR(pinctrl); | ||
548 | |||
549 | clk = devm_clk_get(&pdev->dev, NULL); | ||
550 | if (IS_ERR(clk)) | ||
551 | return PTR_ERR(clk); | ||
552 | |||
553 | if (np) { | ||
554 | devid = (enum mxs_ssp_id) of_id->data; | ||
555 | /* | ||
556 | * TODO: This is a temporary solution and should be changed | ||
557 | * to use generic DMA binding later when the helpers get in. | ||
558 | */ | ||
559 | ret = of_property_read_u32(np, "fsl,ssp-dma-channel", | ||
560 | &dma_channel); | ||
561 | if (ret) { | ||
562 | dev_err(&pdev->dev, | ||
563 | "Failed to get DMA channel\n"); | ||
564 | return -EINVAL; | ||
565 | } | ||
566 | |||
567 | ret = of_property_read_u32(np, "clock-frequency", | ||
568 | &clk_freq); | ||
569 | if (ret) | ||
570 | clk_freq = clk_freq_default; | ||
571 | } else { | ||
572 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); | ||
573 | if (!dmares) | ||
574 | return -EINVAL; | ||
575 | devid = pdev->id_entry->driver_data; | ||
576 | dma_channel = dmares->start; | ||
577 | clk_freq = clk_freq_default; | ||
578 | } | ||
579 | |||
580 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); | ||
581 | if (!master) | ||
582 | return -ENOMEM; | ||
583 | |||
584 | master->transfer_one_message = mxs_spi_transfer_one; | ||
585 | master->setup = mxs_spi_setup; | ||
586 | master->mode_bits = SPI_CPOL | SPI_CPHA; | ||
587 | master->num_chipselect = 3; | ||
588 | master->dev.of_node = np; | ||
589 | master->flags = SPI_MASTER_HALF_DUPLEX; | ||
590 | |||
591 | spi = spi_master_get_devdata(master); | ||
592 | ssp = &spi->ssp; | ||
593 | ssp->dev = &pdev->dev; | ||
594 | ssp->clk = clk; | ||
595 | ssp->base = base; | ||
596 | ssp->devid = devid; | ||
597 | ssp->dma_channel = dma_channel; | ||
598 | |||
599 | init_completion(&spi->c); | ||
600 | |||
601 | ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, | ||
602 | DRIVER_NAME, ssp); | ||
603 | if (ret) | ||
604 | goto out_master_free; | ||
605 | |||
606 | dma_cap_zero(mask); | ||
607 | dma_cap_set(DMA_SLAVE, mask); | ||
608 | ssp->dma_data.chan_irq = irq_dma; | ||
609 | ssp->dmach = dma_request_channel(mask, mxs_ssp_dma_filter, ssp); | ||
610 | if (!ssp->dmach) { | ||
611 | dev_err(ssp->dev, "Failed to request DMA\n"); | ||
612 | goto out_master_free; | ||
613 | } | ||
614 | |||
615 | clk_prepare_enable(ssp->clk); | ||
616 | clk_set_rate(ssp->clk, clk_freq); | ||
617 | ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; | ||
618 | |||
619 | stmp_reset_block(ssp->base); | ||
620 | |||
621 | platform_set_drvdata(pdev, master); | ||
622 | |||
623 | ret = spi_register_master(master); | ||
624 | if (ret) { | ||
625 | dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); | ||
626 | goto out_free_dma; | ||
627 | } | ||
628 | |||
629 | return 0; | ||
630 | |||
631 | out_free_dma: | ||
632 | dma_release_channel(ssp->dmach); | ||
633 | clk_disable_unprepare(ssp->clk); | ||
634 | out_master_free: | ||
635 | spi_master_put(master); | ||
636 | return ret; | ||
637 | } | ||
638 | |||
639 | static int mxs_spi_remove(struct platform_device *pdev) | ||
640 | { | ||
641 | struct spi_master *master; | ||
642 | struct mxs_spi *spi; | ||
643 | struct mxs_ssp *ssp; | ||
644 | |||
645 | master = spi_master_get(platform_get_drvdata(pdev)); | ||
646 | spi = spi_master_get_devdata(master); | ||
647 | ssp = &spi->ssp; | ||
648 | |||
649 | spi_unregister_master(master); | ||
650 | |||
651 | dma_release_channel(ssp->dmach); | ||
652 | |||
653 | clk_disable_unprepare(ssp->clk); | ||
654 | |||
655 | spi_master_put(master); | ||
656 | |||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | static struct platform_driver mxs_spi_driver = { | ||
661 | .probe = mxs_spi_probe, | ||
662 | .remove = mxs_spi_remove, | ||
663 | .driver = { | ||
664 | .name = DRIVER_NAME, | ||
665 | .owner = THIS_MODULE, | ||
666 | .of_match_table = mxs_spi_dt_ids, | ||
667 | }, | ||
668 | }; | ||
669 | |||
670 | module_platform_driver(mxs_spi_driver); | ||
671 | |||
672 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | ||
673 | MODULE_DESCRIPTION("MXS SPI master driver"); | ||
674 | MODULE_LICENSE("GPL"); | ||
675 | MODULE_ALIAS("platform:mxs-spi"); | ||
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c index b3f9ec83ef7..c0a6ce81f9c 100644 --- a/drivers/spi/spi-nuc900.c +++ b/drivers/spi/spi-nuc900.c | |||
@@ -8,7 +8,6 @@ | |||
8 | * | 8 | * |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/module.h> | ||
12 | #include <linux/init.h> | 11 | #include <linux/init.h> |
13 | #include <linux/spinlock.h> | 12 | #include <linux/spinlock.h> |
14 | #include <linux/workqueue.h> | 13 | #include <linux/workqueue.h> |
@@ -26,7 +25,7 @@ | |||
26 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
27 | #include <linux/spi/spi_bitbang.h> | 26 | #include <linux/spi/spi_bitbang.h> |
28 | 27 | ||
29 | #include <linux/platform_data/spi-nuc900.h> | 28 | #include <mach/nuc900_spi.h> |
30 | 29 | ||
31 | /* usi registers offset */ | 30 | /* usi registers offset */ |
32 | #define USI_CNT 0x00 | 31 | #define USI_CNT 0x00 |
@@ -346,7 +345,7 @@ static void nuc900_init_spi(struct nuc900_spi *hw) | |||
346 | nuc900_enable_int(hw); | 345 | nuc900_enable_int(hw); |
347 | } | 346 | } |
348 | 347 | ||
349 | static int nuc900_spi_probe(struct platform_device *pdev) | 348 | static int __devinit nuc900_spi_probe(struct platform_device *pdev) |
350 | { | 349 | { |
351 | struct nuc900_spi *hw; | 350 | struct nuc900_spi *hw; |
352 | struct spi_master *master; | 351 | struct spi_master *master; |
@@ -360,6 +359,8 @@ static int nuc900_spi_probe(struct platform_device *pdev) | |||
360 | } | 359 | } |
361 | 360 | ||
362 | hw = spi_master_get_devdata(master); | 361 | hw = spi_master_get_devdata(master); |
362 | memset(hw, 0, sizeof(struct nuc900_spi)); | ||
363 | |||
363 | hw->master = spi_master_get(master); | 364 | hw->master = spi_master_get(master); |
364 | hw->pdata = pdev->dev.platform_data; | 365 | hw->pdata = pdev->dev.platform_data; |
365 | hw->dev = &pdev->dev; | 366 | hw->dev = &pdev->dev; |
@@ -425,7 +426,7 @@ static int nuc900_spi_probe(struct platform_device *pdev) | |||
425 | goto err_clk; | 426 | goto err_clk; |
426 | } | 427 | } |
427 | 428 | ||
428 | mfp_set_groupg(&pdev->dev, NULL); | 429 | mfp_set_groupg(&pdev->dev); |
429 | nuc900_init_spi(hw); | 430 | nuc900_init_spi(hw); |
430 | 431 | ||
431 | err = spi_bitbang_start(&hw->bitbang); | 432 | err = spi_bitbang_start(&hw->bitbang); |
@@ -453,7 +454,7 @@ err_nomem: | |||
453 | return err; | 454 | return err; |
454 | } | 455 | } |
455 | 456 | ||
456 | static int nuc900_spi_remove(struct platform_device *dev) | 457 | static int __devexit nuc900_spi_remove(struct platform_device *dev) |
457 | { | 458 | { |
458 | struct nuc900_spi *hw = platform_get_drvdata(dev); | 459 | struct nuc900_spi *hw = platform_get_drvdata(dev); |
459 | 460 | ||
@@ -477,13 +478,25 @@ static int nuc900_spi_remove(struct platform_device *dev) | |||
477 | 478 | ||
478 | static struct platform_driver nuc900_spi_driver = { | 479 | static struct platform_driver nuc900_spi_driver = { |
479 | .probe = nuc900_spi_probe, | 480 | .probe = nuc900_spi_probe, |
480 | .remove = nuc900_spi_remove, | 481 | .remove = __devexit_p(nuc900_spi_remove), |
481 | .driver = { | 482 | .driver = { |
482 | .name = "nuc900-spi", | 483 | .name = "nuc900-spi", |
483 | .owner = THIS_MODULE, | 484 | .owner = THIS_MODULE, |
484 | }, | 485 | }, |
485 | }; | 486 | }; |
486 | module_platform_driver(nuc900_spi_driver); | 487 | |
488 | static int __init nuc900_spi_init(void) | ||
489 | { | ||
490 | return platform_driver_register(&nuc900_spi_driver); | ||
491 | } | ||
492 | |||
493 | static void __exit nuc900_spi_exit(void) | ||
494 | { | ||
495 | platform_driver_unregister(&nuc900_spi_driver); | ||
496 | } | ||
497 | |||
498 | module_init(nuc900_spi_init); | ||
499 | module_exit(nuc900_spi_exit); | ||
487 | 500 | ||
488 | MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>"); | 501 | MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>"); |
489 | MODULE_DESCRIPTION("nuc900 spi driver!"); | 502 | MODULE_DESCRIPTION("nuc900 spi driver!"); |
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c index 432e66ec308..f1bde66cea1 100644 --- a/drivers/spi/spi-oc-tiny.c +++ b/drivers/spi/spi-oc-tiny.c | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
20 | #include <linux/errno.h> | 20 | #include <linux/errno.h> |
21 | #include <linux/module.h> | ||
22 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
23 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
24 | #include <linux/spi/spi_bitbang.h> | 23 | #include <linux/spi/spi_bitbang.h> |
@@ -129,7 +128,7 @@ static int tiny_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
129 | unsigned int i; | 128 | unsigned int i; |
130 | 129 | ||
131 | if (hw->irq >= 0) { | 130 | if (hw->irq >= 0) { |
132 | /* use interrupt driven data transfer */ | 131 | /* use intrrupt driven data transfer */ |
133 | hw->len = t->len; | 132 | hw->len = t->len; |
134 | hw->txp = t->tx_buf; | 133 | hw->txp = t->tx_buf; |
135 | hw->rxp = t->rx_buf; | 134 | hw->rxp = t->rx_buf; |
@@ -243,7 +242,7 @@ static irqreturn_t tiny_spi_irq(int irq, void *dev) | |||
243 | #ifdef CONFIG_OF | 242 | #ifdef CONFIG_OF |
244 | #include <linux/of_gpio.h> | 243 | #include <linux/of_gpio.h> |
245 | 244 | ||
246 | static int tiny_spi_of_probe(struct platform_device *pdev) | 245 | static int __devinit tiny_spi_of_probe(struct platform_device *pdev) |
247 | { | 246 | { |
248 | struct tiny_spi *hw = platform_get_drvdata(pdev); | 247 | struct tiny_spi *hw = platform_get_drvdata(pdev); |
249 | struct device_node *np = pdev->dev.of_node; | 248 | struct device_node *np = pdev->dev.of_node; |
@@ -277,13 +276,13 @@ static int tiny_spi_of_probe(struct platform_device *pdev) | |||
277 | return 0; | 276 | return 0; |
278 | } | 277 | } |
279 | #else /* !CONFIG_OF */ | 278 | #else /* !CONFIG_OF */ |
280 | static int tiny_spi_of_probe(struct platform_device *pdev) | 279 | static int __devinit tiny_spi_of_probe(struct platform_device *pdev) |
281 | { | 280 | { |
282 | return 0; | 281 | return 0; |
283 | } | 282 | } |
284 | #endif /* CONFIG_OF */ | 283 | #endif /* CONFIG_OF */ |
285 | 284 | ||
286 | static int tiny_spi_probe(struct platform_device *pdev) | 285 | static int __devinit tiny_spi_probe(struct platform_device *pdev) |
287 | { | 286 | { |
288 | struct tiny_spi_platform_data *platp = pdev->dev.platform_data; | 287 | struct tiny_spi_platform_data *platp = pdev->dev.platform_data; |
289 | struct tiny_spi *hw; | 288 | struct tiny_spi *hw; |
@@ -373,7 +372,7 @@ exit: | |||
373 | return err; | 372 | return err; |
374 | } | 373 | } |
375 | 374 | ||
376 | static int tiny_spi_remove(struct platform_device *pdev) | 375 | static int __devexit tiny_spi_remove(struct platform_device *pdev) |
377 | { | 376 | { |
378 | struct tiny_spi *hw = platform_get_drvdata(pdev); | 377 | struct tiny_spi *hw = platform_get_drvdata(pdev); |
379 | struct spi_master *master = hw->bitbang.master; | 378 | struct spi_master *master = hw->bitbang.master; |
@@ -399,7 +398,7 @@ MODULE_DEVICE_TABLE(of, tiny_spi_match); | |||
399 | 398 | ||
400 | static struct platform_driver tiny_spi_driver = { | 399 | static struct platform_driver tiny_spi_driver = { |
401 | .probe = tiny_spi_probe, | 400 | .probe = tiny_spi_probe, |
402 | .remove = tiny_spi_remove, | 401 | .remove = __devexit_p(tiny_spi_remove), |
403 | .driver = { | 402 | .driver = { |
404 | .name = DRV_NAME, | 403 | .name = DRV_NAME, |
405 | .owner = THIS_MODULE, | 404 | .owner = THIS_MODULE, |
@@ -407,7 +406,18 @@ static struct platform_driver tiny_spi_driver = { | |||
407 | .of_match_table = tiny_spi_match, | 406 | .of_match_table = tiny_spi_match, |
408 | }, | 407 | }, |
409 | }; | 408 | }; |
410 | module_platform_driver(tiny_spi_driver); | 409 | |
410 | static int __init tiny_spi_init(void) | ||
411 | { | ||
412 | return platform_driver_register(&tiny_spi_driver); | ||
413 | } | ||
414 | module_init(tiny_spi_init); | ||
415 | |||
416 | static void __exit tiny_spi_exit(void) | ||
417 | { | ||
418 | platform_driver_unregister(&tiny_spi_driver); | ||
419 | } | ||
420 | module_exit(tiny_spi_exit); | ||
411 | 421 | ||
412 | MODULE_DESCRIPTION("OpenCores tiny SPI driver"); | 422 | MODULE_DESCRIPTION("OpenCores tiny SPI driver"); |
413 | MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); | 423 | MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); |
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c deleted file mode 100644 index 24daf964a40..00000000000 --- a/drivers/spi/spi-octeon.c +++ /dev/null | |||
@@ -1,362 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2011, 2012 Cavium, Inc. | ||
7 | */ | ||
8 | |||
9 | #include <linux/platform_device.h> | ||
10 | #include <linux/interrupt.h> | ||
11 | #include <linux/spi/spi.h> | ||
12 | #include <linux/module.h> | ||
13 | #include <linux/delay.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/of.h> | ||
17 | |||
18 | #include <asm/octeon/octeon.h> | ||
19 | #include <asm/octeon/cvmx-mpi-defs.h> | ||
20 | |||
21 | #define OCTEON_SPI_CFG 0 | ||
22 | #define OCTEON_SPI_STS 0x08 | ||
23 | #define OCTEON_SPI_TX 0x10 | ||
24 | #define OCTEON_SPI_DAT0 0x80 | ||
25 | |||
26 | #define OCTEON_SPI_MAX_BYTES 9 | ||
27 | |||
28 | #define OCTEON_SPI_MAX_CLOCK_HZ 16000000 | ||
29 | |||
30 | struct octeon_spi { | ||
31 | struct spi_master *my_master; | ||
32 | u64 register_base; | ||
33 | u64 last_cfg; | ||
34 | u64 cs_enax; | ||
35 | }; | ||
36 | |||
37 | struct octeon_spi_setup { | ||
38 | u32 max_speed_hz; | ||
39 | u8 chip_select; | ||
40 | u8 mode; | ||
41 | u8 bits_per_word; | ||
42 | }; | ||
43 | |||
44 | static void octeon_spi_wait_ready(struct octeon_spi *p) | ||
45 | { | ||
46 | union cvmx_mpi_sts mpi_sts; | ||
47 | unsigned int loops = 0; | ||
48 | |||
49 | do { | ||
50 | if (loops++) | ||
51 | __delay(500); | ||
52 | mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS); | ||
53 | } while (mpi_sts.s.busy); | ||
54 | } | ||
55 | |||
56 | static int octeon_spi_do_transfer(struct octeon_spi *p, | ||
57 | struct spi_message *msg, | ||
58 | struct spi_transfer *xfer, | ||
59 | bool last_xfer) | ||
60 | { | ||
61 | union cvmx_mpi_cfg mpi_cfg; | ||
62 | union cvmx_mpi_tx mpi_tx; | ||
63 | unsigned int clkdiv; | ||
64 | unsigned int speed_hz; | ||
65 | int mode; | ||
66 | bool cpha, cpol; | ||
67 | int bits_per_word; | ||
68 | const u8 *tx_buf; | ||
69 | u8 *rx_buf; | ||
70 | int len; | ||
71 | int i; | ||
72 | |||
73 | struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi); | ||
74 | |||
75 | speed_hz = msg_setup->max_speed_hz; | ||
76 | mode = msg_setup->mode; | ||
77 | cpha = mode & SPI_CPHA; | ||
78 | cpol = mode & SPI_CPOL; | ||
79 | bits_per_word = msg_setup->bits_per_word; | ||
80 | |||
81 | if (xfer->speed_hz) | ||
82 | speed_hz = xfer->speed_hz; | ||
83 | if (xfer->bits_per_word) | ||
84 | bits_per_word = xfer->bits_per_word; | ||
85 | |||
86 | if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ) | ||
87 | speed_hz = OCTEON_SPI_MAX_CLOCK_HZ; | ||
88 | |||
89 | clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz); | ||
90 | |||
91 | mpi_cfg.u64 = 0; | ||
92 | |||
93 | mpi_cfg.s.clkdiv = clkdiv; | ||
94 | mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0; | ||
95 | mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0; | ||
96 | mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0; | ||
97 | mpi_cfg.s.idlelo = cpha != cpol; | ||
98 | mpi_cfg.s.cslate = cpha ? 1 : 0; | ||
99 | mpi_cfg.s.enable = 1; | ||
100 | |||
101 | if (msg_setup->chip_select < 4) | ||
102 | p->cs_enax |= 1ull << (12 + msg_setup->chip_select); | ||
103 | mpi_cfg.u64 |= p->cs_enax; | ||
104 | |||
105 | if (mpi_cfg.u64 != p->last_cfg) { | ||
106 | p->last_cfg = mpi_cfg.u64; | ||
107 | cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64); | ||
108 | } | ||
109 | tx_buf = xfer->tx_buf; | ||
110 | rx_buf = xfer->rx_buf; | ||
111 | len = xfer->len; | ||
112 | while (len > OCTEON_SPI_MAX_BYTES) { | ||
113 | for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { | ||
114 | u8 d; | ||
115 | if (tx_buf) | ||
116 | d = *tx_buf++; | ||
117 | else | ||
118 | d = 0; | ||
119 | cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); | ||
120 | } | ||
121 | mpi_tx.u64 = 0; | ||
122 | mpi_tx.s.csid = msg_setup->chip_select; | ||
123 | mpi_tx.s.leavecs = 1; | ||
124 | mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; | ||
125 | mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; | ||
126 | cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); | ||
127 | |||
128 | octeon_spi_wait_ready(p); | ||
129 | if (rx_buf) | ||
130 | for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { | ||
131 | u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); | ||
132 | *rx_buf++ = (u8)v; | ||
133 | } | ||
134 | len -= OCTEON_SPI_MAX_BYTES; | ||
135 | } | ||
136 | |||
137 | for (i = 0; i < len; i++) { | ||
138 | u8 d; | ||
139 | if (tx_buf) | ||
140 | d = *tx_buf++; | ||
141 | else | ||
142 | d = 0; | ||
143 | cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); | ||
144 | } | ||
145 | |||
146 | mpi_tx.u64 = 0; | ||
147 | mpi_tx.s.csid = msg_setup->chip_select; | ||
148 | if (last_xfer) | ||
149 | mpi_tx.s.leavecs = xfer->cs_change; | ||
150 | else | ||
151 | mpi_tx.s.leavecs = !xfer->cs_change; | ||
152 | mpi_tx.s.txnum = tx_buf ? len : 0; | ||
153 | mpi_tx.s.totnum = len; | ||
154 | cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); | ||
155 | |||
156 | octeon_spi_wait_ready(p); | ||
157 | if (rx_buf) | ||
158 | for (i = 0; i < len; i++) { | ||
159 | u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); | ||
160 | *rx_buf++ = (u8)v; | ||
161 | } | ||
162 | |||
163 | if (xfer->delay_usecs) | ||
164 | udelay(xfer->delay_usecs); | ||
165 | |||
166 | return xfer->len; | ||
167 | } | ||
168 | |||
169 | static int octeon_spi_validate_bpw(struct spi_device *spi, u32 speed) | ||
170 | { | ||
171 | switch (speed) { | ||
172 | case 8: | ||
173 | break; | ||
174 | default: | ||
175 | dev_err(&spi->dev, "Error: %d bits per word not supported\n", | ||
176 | speed); | ||
177 | return -EINVAL; | ||
178 | } | ||
179 | return 0; | ||
180 | } | ||
181 | |||
182 | static int octeon_spi_transfer_one_message(struct spi_master *master, | ||
183 | struct spi_message *msg) | ||
184 | { | ||
185 | struct octeon_spi *p = spi_master_get_devdata(master); | ||
186 | unsigned int total_len = 0; | ||
187 | int status = 0; | ||
188 | struct spi_transfer *xfer; | ||
189 | |||
190 | /* | ||
191 | * We better have set the configuration via a call to .setup | ||
192 | * before we get here. | ||
193 | */ | ||
194 | if (spi_get_ctldata(msg->spi) == NULL) { | ||
195 | status = -EINVAL; | ||
196 | goto err; | ||
197 | } | ||
198 | |||
199 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
200 | if (xfer->bits_per_word) { | ||
201 | status = octeon_spi_validate_bpw(msg->spi, | ||
202 | xfer->bits_per_word); | ||
203 | if (status) | ||
204 | goto err; | ||
205 | } | ||
206 | } | ||
207 | |||
208 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
209 | bool last_xfer = &xfer->transfer_list == msg->transfers.prev; | ||
210 | int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); | ||
211 | if (r < 0) { | ||
212 | status = r; | ||
213 | goto err; | ||
214 | } | ||
215 | total_len += r; | ||
216 | } | ||
217 | err: | ||
218 | msg->status = status; | ||
219 | msg->actual_length = total_len; | ||
220 | spi_finalize_current_message(master); | ||
221 | return status; | ||
222 | } | ||
223 | |||
224 | static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi) | ||
225 | { | ||
226 | struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL); | ||
227 | if (!setup) | ||
228 | return NULL; | ||
229 | |||
230 | setup->max_speed_hz = spi->max_speed_hz; | ||
231 | setup->chip_select = spi->chip_select; | ||
232 | setup->mode = spi->mode; | ||
233 | setup->bits_per_word = spi->bits_per_word; | ||
234 | return setup; | ||
235 | } | ||
236 | |||
237 | static int octeon_spi_setup(struct spi_device *spi) | ||
238 | { | ||
239 | int r; | ||
240 | struct octeon_spi_setup *new_setup; | ||
241 | struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); | ||
242 | |||
243 | r = octeon_spi_validate_bpw(spi, spi->bits_per_word); | ||
244 | if (r) | ||
245 | return r; | ||
246 | |||
247 | new_setup = octeon_spi_new_setup(spi); | ||
248 | if (!new_setup) | ||
249 | return -ENOMEM; | ||
250 | |||
251 | spi_set_ctldata(spi, new_setup); | ||
252 | kfree(old_setup); | ||
253 | |||
254 | return 0; | ||
255 | } | ||
256 | |||
257 | static void octeon_spi_cleanup(struct spi_device *spi) | ||
258 | { | ||
259 | struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); | ||
260 | spi_set_ctldata(spi, NULL); | ||
261 | kfree(old_setup); | ||
262 | } | ||
263 | |||
264 | static int octeon_spi_nop_transfer_hardware(struct spi_master *master) | ||
265 | { | ||
266 | return 0; | ||
267 | } | ||
268 | |||
269 | static int octeon_spi_probe(struct platform_device *pdev) | ||
270 | { | ||
271 | |||
272 | struct resource *res_mem; | ||
273 | struct spi_master *master; | ||
274 | struct octeon_spi *p; | ||
275 | int err = -ENOENT; | ||
276 | |||
277 | master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi)); | ||
278 | if (!master) | ||
279 | return -ENOMEM; | ||
280 | p = spi_master_get_devdata(master); | ||
281 | platform_set_drvdata(pdev, p); | ||
282 | p->my_master = master; | ||
283 | |||
284 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
285 | |||
286 | if (res_mem == NULL) { | ||
287 | dev_err(&pdev->dev, "found no memory resource\n"); | ||
288 | err = -ENXIO; | ||
289 | goto fail; | ||
290 | } | ||
291 | if (!devm_request_mem_region(&pdev->dev, res_mem->start, | ||
292 | resource_size(res_mem), res_mem->name)) { | ||
293 | dev_err(&pdev->dev, "request_mem_region failed\n"); | ||
294 | goto fail; | ||
295 | } | ||
296 | p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, | ||
297 | resource_size(res_mem)); | ||
298 | |||
299 | /* Dynamic bus numbering */ | ||
300 | master->bus_num = -1; | ||
301 | master->num_chipselect = 4; | ||
302 | master->mode_bits = SPI_CPHA | | ||
303 | SPI_CPOL | | ||
304 | SPI_CS_HIGH | | ||
305 | SPI_LSB_FIRST | | ||
306 | SPI_3WIRE; | ||
307 | |||
308 | master->setup = octeon_spi_setup; | ||
309 | master->cleanup = octeon_spi_cleanup; | ||
310 | master->prepare_transfer_hardware = octeon_spi_nop_transfer_hardware; | ||
311 | master->transfer_one_message = octeon_spi_transfer_one_message; | ||
312 | master->unprepare_transfer_hardware = octeon_spi_nop_transfer_hardware; | ||
313 | |||
314 | master->dev.of_node = pdev->dev.of_node; | ||
315 | err = spi_register_master(master); | ||
316 | if (err) { | ||
317 | dev_err(&pdev->dev, "register master failed: %d\n", err); | ||
318 | goto fail; | ||
319 | } | ||
320 | |||
321 | dev_info(&pdev->dev, "OCTEON SPI bus driver\n"); | ||
322 | |||
323 | return 0; | ||
324 | fail: | ||
325 | spi_master_put(master); | ||
326 | return err; | ||
327 | } | ||
328 | |||
329 | static int octeon_spi_remove(struct platform_device *pdev) | ||
330 | { | ||
331 | struct octeon_spi *p = platform_get_drvdata(pdev); | ||
332 | u64 register_base = p->register_base; | ||
333 | |||
334 | spi_unregister_master(p->my_master); | ||
335 | |||
336 | /* Clear the CSENA* and put everything in a known state. */ | ||
337 | cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0); | ||
338 | |||
339 | return 0; | ||
340 | } | ||
341 | |||
342 | static struct of_device_id octeon_spi_match[] = { | ||
343 | { .compatible = "cavium,octeon-3010-spi", }, | ||
344 | {}, | ||
345 | }; | ||
346 | MODULE_DEVICE_TABLE(of, octeon_spi_match); | ||
347 | |||
348 | static struct platform_driver octeon_spi_driver = { | ||
349 | .driver = { | ||
350 | .name = "spi-octeon", | ||
351 | .owner = THIS_MODULE, | ||
352 | .of_match_table = octeon_spi_match, | ||
353 | }, | ||
354 | .probe = octeon_spi_probe, | ||
355 | .remove = octeon_spi_remove, | ||
356 | }; | ||
357 | |||
358 | module_platform_driver(octeon_spi_driver); | ||
359 | |||
360 | MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver"); | ||
361 | MODULE_AUTHOR("David Daney"); | ||
362 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c index 3aef7fa7d5b..9bd1c92ad96 100644 --- a/drivers/spi/spi-omap-100k.c +++ b/drivers/spi/spi-omap-100k.c | |||
@@ -37,6 +37,8 @@ | |||
37 | 37 | ||
38 | #include <linux/spi/spi.h> | 38 | #include <linux/spi/spi.h> |
39 | 39 | ||
40 | #include <plat/clock.h> | ||
41 | |||
40 | #define OMAP1_SPI100K_MAX_FREQ 48000000 | 42 | #define OMAP1_SPI100K_MAX_FREQ 48000000 |
41 | 43 | ||
42 | #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12) | 44 | #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12) |
@@ -486,7 +488,7 @@ static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k) | |||
486 | return 0; | 488 | return 0; |
487 | } | 489 | } |
488 | 490 | ||
489 | static int omap1_spi100k_probe(struct platform_device *pdev) | 491 | static int __devinit omap1_spi100k_probe(struct platform_device *pdev) |
490 | { | 492 | { |
491 | struct spi_master *master; | 493 | struct spi_master *master; |
492 | struct omap1_spi100k *spi100k; | 494 | struct omap1_spi100k *spi100k; |
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c index 0a94d9dc9c3..00a8e9d7dbe 100644 --- a/drivers/spi/spi-omap-uwire.c +++ b/drivers/spi/spi-omap-uwire.c | |||
@@ -45,16 +45,15 @@ | |||
45 | 45 | ||
46 | #include <linux/spi/spi.h> | 46 | #include <linux/spi/spi.h> |
47 | #include <linux/spi/spi_bitbang.h> | 47 | #include <linux/spi/spi_bitbang.h> |
48 | #include <linux/module.h> | ||
49 | 48 | ||
49 | #include <asm/system.h> | ||
50 | #include <asm/irq.h> | 50 | #include <asm/irq.h> |
51 | #include <mach/hardware.h> | 51 | #include <mach/hardware.h> |
52 | #include <asm/io.h> | 52 | #include <asm/io.h> |
53 | #include <asm/mach-types.h> | 53 | #include <asm/mach-types.h> |
54 | 54 | ||
55 | #include <mach/mux.h> | 55 | #include <plat/mux.h> |
56 | 56 | #include <plat/omap7xx.h> /* OMAP7XX_IO_CONF registers */ | |
57 | #include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */ | ||
58 | 57 | ||
59 | 58 | ||
60 | /* FIXME address is now a platform device resource, | 59 | /* FIXME address is now a platform device resource, |
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index b610f522ca4..322be7aea8b 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c | |||
@@ -28,24 +28,23 @@ | |||
28 | #include <linux/device.h> | 28 | #include <linux/device.h> |
29 | #include <linux/delay.h> | 29 | #include <linux/delay.h> |
30 | #include <linux/dma-mapping.h> | 30 | #include <linux/dma-mapping.h> |
31 | #include <linux/dmaengine.h> | ||
32 | #include <linux/omap-dma.h> | ||
33 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | 32 | #include <linux/err.h> |
35 | #include <linux/clk.h> | 33 | #include <linux/clk.h> |
36 | #include <linux/io.h> | 34 | #include <linux/io.h> |
37 | #include <linux/slab.h> | 35 | #include <linux/slab.h> |
38 | #include <linux/pm_runtime.h> | 36 | #include <linux/pm_runtime.h> |
39 | #include <linux/of.h> | ||
40 | #include <linux/of_device.h> | ||
41 | #include <linux/pinctrl/consumer.h> | ||
42 | 37 | ||
43 | #include <linux/spi/spi.h> | 38 | #include <linux/spi/spi.h> |
44 | 39 | ||
45 | #include <linux/platform_data/spi-omap2-mcspi.h> | 40 | #include <plat/dma.h> |
41 | #include <plat/clock.h> | ||
42 | #include <plat/mcspi.h> | ||
46 | 43 | ||
47 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | 44 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
48 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 | 45 | |
46 | /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */ | ||
47 | #define OMAP2_MCSPI_MAX_CTRL 4 | ||
49 | 48 | ||
50 | #define OMAP2_MCSPI_REVISION 0x00 | 49 | #define OMAP2_MCSPI_REVISION 0x00 |
51 | #define OMAP2_MCSPI_SYSSTATUS 0x14 | 50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
@@ -94,8 +93,8 @@ | |||
94 | 93 | ||
95 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | 94 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
96 | struct omap2_mcspi_dma { | 95 | struct omap2_mcspi_dma { |
97 | struct dma_chan *dma_tx; | 96 | int dma_tx_channel; |
98 | struct dma_chan *dma_rx; | 97 | int dma_rx_channel; |
99 | 98 | ||
100 | int dma_tx_sync_dev; | 99 | int dma_tx_sync_dev; |
101 | int dma_rx_sync_dev; | 100 | int dma_rx_sync_dev; |
@@ -110,26 +109,18 @@ struct omap2_mcspi_dma { | |||
110 | #define DMA_MIN_BYTES 160 | 109 | #define DMA_MIN_BYTES 160 |
111 | 110 | ||
112 | 111 | ||
113 | /* | ||
114 | * Used for context save and restore, structure members to be updated whenever | ||
115 | * corresponding registers are modified. | ||
116 | */ | ||
117 | struct omap2_mcspi_regs { | ||
118 | u32 modulctrl; | ||
119 | u32 wakeupenable; | ||
120 | struct list_head cs; | ||
121 | }; | ||
122 | |||
123 | struct omap2_mcspi { | 112 | struct omap2_mcspi { |
113 | struct work_struct work; | ||
114 | /* lock protects queue and registers */ | ||
115 | spinlock_t lock; | ||
116 | struct list_head msg_queue; | ||
124 | struct spi_master *master; | 117 | struct spi_master *master; |
125 | /* Virtual base address of the controller */ | 118 | /* Virtual base address of the controller */ |
126 | void __iomem *base; | 119 | void __iomem *base; |
127 | unsigned long phys; | 120 | unsigned long phys; |
128 | /* SPI1 has 4 channels, while SPI2 has 2 */ | 121 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
129 | struct omap2_mcspi_dma *dma_channels; | 122 | struct omap2_mcspi_dma *dma_channels; |
130 | struct device *dev; | 123 | struct device *dev; |
131 | struct omap2_mcspi_regs ctx; | ||
132 | unsigned int pin_dir:1; | ||
133 | }; | 124 | }; |
134 | 125 | ||
135 | struct omap2_mcspi_cs { | 126 | struct omap2_mcspi_cs { |
@@ -141,6 +132,26 @@ struct omap2_mcspi_cs { | |||
141 | u32 chconf0; | 132 | u32 chconf0; |
142 | }; | 133 | }; |
143 | 134 | ||
135 | /* used for context save and restore, structure members to be updated whenever | ||
136 | * corresponding registers are modified. | ||
137 | */ | ||
138 | struct omap2_mcspi_regs { | ||
139 | u32 modulctrl; | ||
140 | u32 wakeupenable; | ||
141 | struct list_head cs; | ||
142 | }; | ||
143 | |||
144 | static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL]; | ||
145 | |||
146 | static struct workqueue_struct *omap2_mcspi_wq; | ||
147 | |||
148 | #define MOD_REG_BIT(val, mask, set) do { \ | ||
149 | if (set) \ | ||
150 | val |= mask; \ | ||
151 | else \ | ||
152 | val &= ~mask; \ | ||
153 | } while (0) | ||
154 | |||
144 | static inline void mcspi_write_reg(struct spi_master *master, | 155 | static inline void mcspi_write_reg(struct spi_master *master, |
145 | int idx, u32 val) | 156 | int idx, u32 val) |
146 | { | 157 | { |
@@ -199,11 +210,7 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi, | |||
199 | else | 210 | else |
200 | rw = OMAP2_MCSPI_CHCONF_DMAW; | 211 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
201 | 212 | ||
202 | if (enable) | 213 | MOD_REG_BIT(l, rw, enable); |
203 | l |= rw; | ||
204 | else | ||
205 | l &= ~rw; | ||
206 | |||
207 | mcspi_write_chconf0(spi, l); | 214 | mcspi_write_chconf0(spi, l); |
208 | } | 215 | } |
209 | 216 | ||
@@ -222,61 +229,51 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |||
222 | u32 l; | 229 | u32 l; |
223 | 230 | ||
224 | l = mcspi_cached_chconf0(spi); | 231 | l = mcspi_cached_chconf0(spi); |
225 | if (cs_active) | 232 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
226 | l |= OMAP2_MCSPI_CHCONF_FORCE; | ||
227 | else | ||
228 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | ||
229 | |||
230 | mcspi_write_chconf0(spi, l); | 233 | mcspi_write_chconf0(spi, l); |
231 | } | 234 | } |
232 | 235 | ||
233 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | 236 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
234 | { | 237 | { |
235 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | ||
236 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | ||
237 | u32 l; | 238 | u32 l; |
238 | 239 | ||
239 | /* | 240 | /* setup when switching from (reset default) slave mode |
240 | * Setup when switching from (reset default) slave mode | ||
241 | * to single-channel master mode | 241 | * to single-channel master mode |
242 | */ | 242 | */ |
243 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | 243 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
244 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); | 244 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
245 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | 245 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
246 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); | ||
246 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); | 247 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
247 | 248 | ||
248 | ctx->modulctrl = l; | 249 | omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l; |
249 | } | 250 | } |
250 | 251 | ||
251 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | 252 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
252 | { | 253 | { |
253 | struct spi_master *spi_cntrl = mcspi->master; | 254 | struct spi_master *spi_cntrl; |
254 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | 255 | struct omap2_mcspi_cs *cs; |
255 | struct omap2_mcspi_cs *cs; | 256 | spi_cntrl = mcspi->master; |
256 | 257 | ||
257 | /* McSPI: context restore */ | 258 | /* McSPI: context restore */ |
258 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); | 259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, |
259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | 260 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); |
261 | |||
262 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, | ||
263 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); | ||
260 | 264 | ||
261 | list_for_each_entry(cs, &ctx->cs, node) | 265 | list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs, |
266 | node) | ||
262 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 267 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
263 | } | 268 | } |
264 | 269 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) | |
265 | static int omap2_prepare_transfer(struct spi_master *master) | ||
266 | { | 270 | { |
267 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | 271 | pm_runtime_put_sync(mcspi->dev); |
268 | |||
269 | pm_runtime_get_sync(mcspi->dev); | ||
270 | return 0; | ||
271 | } | 272 | } |
272 | 273 | ||
273 | static int omap2_unprepare_transfer(struct spi_master *master) | 274 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
274 | { | 275 | { |
275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | 276 | return pm_runtime_get_sync(mcspi->dev); |
276 | |||
277 | pm_runtime_mark_last_busy(mcspi->dev); | ||
278 | pm_runtime_put_autosuspend(mcspi->dev); | ||
279 | return 0; | ||
280 | } | 277 | } |
281 | 278 | ||
282 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) | 279 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
@@ -292,227 +289,95 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) | |||
292 | return 0; | 289 | return 0; |
293 | } | 290 | } |
294 | 291 | ||
295 | static void omap2_mcspi_rx_callback(void *data) | 292 | static unsigned |
296 | { | 293 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
297 | struct spi_device *spi = data; | ||
298 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | ||
299 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | ||
300 | |||
301 | complete(&mcspi_dma->dma_rx_completion); | ||
302 | |||
303 | /* We must disable the DMA RX request */ | ||
304 | omap2_mcspi_set_dma_req(spi, 1, 0); | ||
305 | } | ||
306 | |||
307 | static void omap2_mcspi_tx_callback(void *data) | ||
308 | { | ||
309 | struct spi_device *spi = data; | ||
310 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | ||
311 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | ||
312 | |||
313 | complete(&mcspi_dma->dma_tx_completion); | ||
314 | |||
315 | /* We must disable the DMA TX request */ | ||
316 | omap2_mcspi_set_dma_req(spi, 0, 0); | ||
317 | } | ||
318 | |||
319 | static void omap2_mcspi_tx_dma(struct spi_device *spi, | ||
320 | struct spi_transfer *xfer, | ||
321 | struct dma_slave_config cfg) | ||
322 | { | 294 | { |
323 | struct omap2_mcspi *mcspi; | 295 | struct omap2_mcspi *mcspi; |
296 | struct omap2_mcspi_cs *cs = spi->controller_state; | ||
324 | struct omap2_mcspi_dma *mcspi_dma; | 297 | struct omap2_mcspi_dma *mcspi_dma; |
325 | unsigned int count; | 298 | unsigned int count, c; |
299 | unsigned long base, tx_reg, rx_reg; | ||
300 | int word_len, data_type, element_count; | ||
301 | int elements = 0; | ||
302 | u32 l; | ||
303 | u8 * rx; | ||
304 | const u8 * tx; | ||
305 | void __iomem *chstat_reg; | ||
326 | 306 | ||
327 | mcspi = spi_master_get_devdata(spi->master); | 307 | mcspi = spi_master_get_devdata(spi->master); |
328 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 308 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
329 | count = xfer->len; | 309 | l = mcspi_cached_chconf0(spi); |
330 | |||
331 | if (mcspi_dma->dma_tx) { | ||
332 | struct dma_async_tx_descriptor *tx; | ||
333 | struct scatterlist sg; | ||
334 | |||
335 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | ||
336 | |||
337 | sg_init_table(&sg, 1); | ||
338 | sg_dma_address(&sg) = xfer->tx_dma; | ||
339 | sg_dma_len(&sg) = xfer->len; | ||
340 | |||
341 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | ||
342 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
343 | if (tx) { | ||
344 | tx->callback = omap2_mcspi_tx_callback; | ||
345 | tx->callback_param = spi; | ||
346 | dmaengine_submit(tx); | ||
347 | } else { | ||
348 | /* FIXME: fall back to PIO? */ | ||
349 | } | ||
350 | } | ||
351 | dma_async_issue_pending(mcspi_dma->dma_tx); | ||
352 | omap2_mcspi_set_dma_req(spi, 0, 1); | ||
353 | 310 | ||
354 | } | 311 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
355 | 312 | ||
356 | static unsigned | ||
357 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | ||
358 | struct dma_slave_config cfg, | ||
359 | unsigned es) | ||
360 | { | ||
361 | struct omap2_mcspi *mcspi; | ||
362 | struct omap2_mcspi_dma *mcspi_dma; | ||
363 | unsigned int count; | ||
364 | u32 l; | ||
365 | int elements = 0; | ||
366 | int word_len, element_count; | ||
367 | struct omap2_mcspi_cs *cs = spi->controller_state; | ||
368 | mcspi = spi_master_get_devdata(spi->master); | ||
369 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | ||
370 | count = xfer->len; | 313 | count = xfer->len; |
314 | c = count; | ||
371 | word_len = cs->word_len; | 315 | word_len = cs->word_len; |
372 | l = mcspi_cached_chconf0(spi); | ||
373 | 316 | ||
374 | if (word_len <= 8) | 317 | base = cs->phys; |
318 | tx_reg = base + OMAP2_MCSPI_TX0; | ||
319 | rx_reg = base + OMAP2_MCSPI_RX0; | ||
320 | rx = xfer->rx_buf; | ||
321 | tx = xfer->tx_buf; | ||
322 | |||
323 | if (word_len <= 8) { | ||
324 | data_type = OMAP_DMA_DATA_TYPE_S8; | ||
375 | element_count = count; | 325 | element_count = count; |
376 | else if (word_len <= 16) | 326 | } else if (word_len <= 16) { |
327 | data_type = OMAP_DMA_DATA_TYPE_S16; | ||
377 | element_count = count >> 1; | 328 | element_count = count >> 1; |
378 | else /* word_len <= 32 */ | 329 | } else /* word_len <= 32 */ { |
330 | data_type = OMAP_DMA_DATA_TYPE_S32; | ||
379 | element_count = count >> 2; | 331 | element_count = count >> 2; |
380 | |||
381 | if (mcspi_dma->dma_rx) { | ||
382 | struct dma_async_tx_descriptor *tx; | ||
383 | struct scatterlist sg; | ||
384 | size_t len = xfer->len - es; | ||
385 | |||
386 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | ||
387 | |||
388 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | ||
389 | len -= es; | ||
390 | |||
391 | sg_init_table(&sg, 1); | ||
392 | sg_dma_address(&sg) = xfer->rx_dma; | ||
393 | sg_dma_len(&sg) = len; | ||
394 | |||
395 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | ||
396 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | | ||
397 | DMA_CTRL_ACK); | ||
398 | if (tx) { | ||
399 | tx->callback = omap2_mcspi_rx_callback; | ||
400 | tx->callback_param = spi; | ||
401 | dmaengine_submit(tx); | ||
402 | } else { | ||
403 | /* FIXME: fall back to PIO? */ | ||
404 | } | ||
405 | } | 332 | } |
406 | 333 | ||
407 | dma_async_issue_pending(mcspi_dma->dma_rx); | 334 | if (tx != NULL) { |
408 | omap2_mcspi_set_dma_req(spi, 1, 1); | 335 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
409 | 336 | data_type, element_count, 1, | |
410 | wait_for_completion(&mcspi_dma->dma_rx_completion); | 337 | OMAP_DMA_SYNC_ELEMENT, |
411 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | 338 | mcspi_dma->dma_tx_sync_dev, 0); |
412 | DMA_FROM_DEVICE); | 339 | |
413 | omap2_mcspi_set_enable(spi, 0); | 340 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
414 | 341 | OMAP_DMA_AMODE_CONSTANT, | |
415 | elements = element_count - 1; | 342 | tx_reg, 0, 0); |
416 | 343 | ||
417 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { | 344 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
418 | elements--; | 345 | OMAP_DMA_AMODE_POST_INC, |
419 | 346 | xfer->tx_dma, 0, 0); | |
420 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | ||
421 | & OMAP2_MCSPI_CHSTAT_RXS)) { | ||
422 | u32 w; | ||
423 | |||
424 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | ||
425 | if (word_len <= 8) | ||
426 | ((u8 *)xfer->rx_buf)[elements++] = w; | ||
427 | else if (word_len <= 16) | ||
428 | ((u16 *)xfer->rx_buf)[elements++] = w; | ||
429 | else /* word_len <= 32 */ | ||
430 | ((u32 *)xfer->rx_buf)[elements++] = w; | ||
431 | } else { | ||
432 | dev_err(&spi->dev, "DMA RX penultimate word empty"); | ||
433 | count -= (word_len <= 8) ? 2 : | ||
434 | (word_len <= 16) ? 4 : | ||
435 | /* word_len <= 32 */ 8; | ||
436 | omap2_mcspi_set_enable(spi, 1); | ||
437 | return count; | ||
438 | } | ||
439 | } | ||
440 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | ||
441 | & OMAP2_MCSPI_CHSTAT_RXS)) { | ||
442 | u32 w; | ||
443 | |||
444 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | ||
445 | if (word_len <= 8) | ||
446 | ((u8 *)xfer->rx_buf)[elements] = w; | ||
447 | else if (word_len <= 16) | ||
448 | ((u16 *)xfer->rx_buf)[elements] = w; | ||
449 | else /* word_len <= 32 */ | ||
450 | ((u32 *)xfer->rx_buf)[elements] = w; | ||
451 | } else { | ||
452 | dev_err(&spi->dev, "DMA RX last word empty"); | ||
453 | count -= (word_len <= 8) ? 1 : | ||
454 | (word_len <= 16) ? 2 : | ||
455 | /* word_len <= 32 */ 4; | ||
456 | } | 347 | } |
457 | omap2_mcspi_set_enable(spi, 1); | ||
458 | return count; | ||
459 | } | ||
460 | 348 | ||
461 | static unsigned | 349 | if (rx != NULL) { |
462 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | 350 | elements = element_count - 1; |
463 | { | 351 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
464 | struct omap2_mcspi *mcspi; | 352 | elements--; |
465 | struct omap2_mcspi_cs *cs = spi->controller_state; | ||
466 | struct omap2_mcspi_dma *mcspi_dma; | ||
467 | unsigned int count; | ||
468 | u32 l; | ||
469 | u8 *rx; | ||
470 | const u8 *tx; | ||
471 | struct dma_slave_config cfg; | ||
472 | enum dma_slave_buswidth width; | ||
473 | unsigned es; | ||
474 | void __iomem *chstat_reg; | ||
475 | 353 | ||
476 | mcspi = spi_master_get_devdata(spi->master); | 354 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
477 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 355 | data_type, elements, 1, |
478 | l = mcspi_cached_chconf0(spi); | 356 | OMAP_DMA_SYNC_ELEMENT, |
357 | mcspi_dma->dma_rx_sync_dev, 1); | ||
479 | 358 | ||
359 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, | ||
360 | OMAP_DMA_AMODE_CONSTANT, | ||
361 | rx_reg, 0, 0); | ||
480 | 362 | ||
481 | if (cs->word_len <= 8) { | 363 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
482 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | 364 | OMAP_DMA_AMODE_POST_INC, |
483 | es = 1; | 365 | xfer->rx_dma, 0, 0); |
484 | } else if (cs->word_len <= 16) { | ||
485 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | ||
486 | es = 2; | ||
487 | } else { | ||
488 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
489 | es = 4; | ||
490 | } | 366 | } |
491 | 367 | ||
492 | memset(&cfg, 0, sizeof(cfg)); | 368 | if (tx != NULL) { |
493 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | 369 | omap_start_dma(mcspi_dma->dma_tx_channel); |
494 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | 370 | omap2_mcspi_set_dma_req(spi, 0, 1); |
495 | cfg.src_addr_width = width; | 371 | } |
496 | cfg.dst_addr_width = width; | ||
497 | cfg.src_maxburst = 1; | ||
498 | cfg.dst_maxburst = 1; | ||
499 | |||
500 | rx = xfer->rx_buf; | ||
501 | tx = xfer->tx_buf; | ||
502 | |||
503 | count = xfer->len; | ||
504 | |||
505 | if (tx != NULL) | ||
506 | omap2_mcspi_tx_dma(spi, xfer, cfg); | ||
507 | 372 | ||
508 | if (rx != NULL) | 373 | if (rx != NULL) { |
509 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); | 374 | omap_start_dma(mcspi_dma->dma_rx_channel); |
375 | omap2_mcspi_set_dma_req(spi, 1, 1); | ||
376 | } | ||
510 | 377 | ||
511 | if (tx != NULL) { | 378 | if (tx != NULL) { |
512 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; | ||
513 | wait_for_completion(&mcspi_dma->dma_tx_completion); | 379 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
514 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | 380 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
515 | DMA_TO_DEVICE); | ||
516 | 381 | ||
517 | /* for TX_ONLY mode, be sure all words have shifted out */ | 382 | /* for TX_ONLY mode, be sure all words have shifted out */ |
518 | if (rx == NULL) { | 383 | if (rx == NULL) { |
@@ -524,6 +389,55 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |||
524 | dev_err(&spi->dev, "EOT timed out\n"); | 389 | dev_err(&spi->dev, "EOT timed out\n"); |
525 | } | 390 | } |
526 | } | 391 | } |
392 | |||
393 | if (rx != NULL) { | ||
394 | wait_for_completion(&mcspi_dma->dma_rx_completion); | ||
395 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); | ||
396 | omap2_mcspi_set_enable(spi, 0); | ||
397 | |||
398 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { | ||
399 | |||
400 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | ||
401 | & OMAP2_MCSPI_CHSTAT_RXS)) { | ||
402 | u32 w; | ||
403 | |||
404 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | ||
405 | if (word_len <= 8) | ||
406 | ((u8 *)xfer->rx_buf)[elements++] = w; | ||
407 | else if (word_len <= 16) | ||
408 | ((u16 *)xfer->rx_buf)[elements++] = w; | ||
409 | else /* word_len <= 32 */ | ||
410 | ((u32 *)xfer->rx_buf)[elements++] = w; | ||
411 | } else { | ||
412 | dev_err(&spi->dev, | ||
413 | "DMA RX penultimate word empty"); | ||
414 | count -= (word_len <= 8) ? 2 : | ||
415 | (word_len <= 16) ? 4 : | ||
416 | /* word_len <= 32 */ 8; | ||
417 | omap2_mcspi_set_enable(spi, 1); | ||
418 | return count; | ||
419 | } | ||
420 | } | ||
421 | |||
422 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | ||
423 | & OMAP2_MCSPI_CHSTAT_RXS)) { | ||
424 | u32 w; | ||
425 | |||
426 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | ||
427 | if (word_len <= 8) | ||
428 | ((u8 *)xfer->rx_buf)[elements] = w; | ||
429 | else if (word_len <= 16) | ||
430 | ((u16 *)xfer->rx_buf)[elements] = w; | ||
431 | else /* word_len <= 32 */ | ||
432 | ((u32 *)xfer->rx_buf)[elements] = w; | ||
433 | } else { | ||
434 | dev_err(&spi->dev, "DMA RX last word empty"); | ||
435 | count -= (word_len <= 8) ? 1 : | ||
436 | (word_len <= 16) ? 2 : | ||
437 | /* word_len <= 32 */ 4; | ||
438 | } | ||
439 | omap2_mcspi_set_enable(spi, 1); | ||
440 | } | ||
527 | return count; | 441 | return count; |
528 | } | 442 | } |
529 | 443 | ||
@@ -761,15 +675,8 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |||
761 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | 675 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
762 | * REVISIT: this controller could support SPI_3WIRE mode. | 676 | * REVISIT: this controller could support SPI_3WIRE mode. |
763 | */ | 677 | */ |
764 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { | 678 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
765 | l &= ~OMAP2_MCSPI_CHCONF_IS; | 679 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
766 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | ||
767 | l |= OMAP2_MCSPI_CHCONF_DPE0; | ||
768 | } else { | ||
769 | l |= OMAP2_MCSPI_CHCONF_IS; | ||
770 | l |= OMAP2_MCSPI_CHCONF_DPE1; | ||
771 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | ||
772 | } | ||
773 | 680 | ||
774 | /* wordlength */ | 681 | /* wordlength */ |
775 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | 682 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
@@ -805,46 +712,71 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |||
805 | return 0; | 712 | return 0; |
806 | } | 713 | } |
807 | 714 | ||
715 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) | ||
716 | { | ||
717 | struct spi_device *spi = data; | ||
718 | struct omap2_mcspi *mcspi; | ||
719 | struct omap2_mcspi_dma *mcspi_dma; | ||
720 | |||
721 | mcspi = spi_master_get_devdata(spi->master); | ||
722 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); | ||
723 | |||
724 | complete(&mcspi_dma->dma_rx_completion); | ||
725 | |||
726 | /* We must disable the DMA RX request */ | ||
727 | omap2_mcspi_set_dma_req(spi, 1, 0); | ||
728 | } | ||
729 | |||
730 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) | ||
731 | { | ||
732 | struct spi_device *spi = data; | ||
733 | struct omap2_mcspi *mcspi; | ||
734 | struct omap2_mcspi_dma *mcspi_dma; | ||
735 | |||
736 | mcspi = spi_master_get_devdata(spi->master); | ||
737 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); | ||
738 | |||
739 | complete(&mcspi_dma->dma_tx_completion); | ||
740 | |||
741 | /* We must disable the DMA TX request */ | ||
742 | omap2_mcspi_set_dma_req(spi, 0, 0); | ||
743 | } | ||
744 | |||
808 | static int omap2_mcspi_request_dma(struct spi_device *spi) | 745 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
809 | { | 746 | { |
810 | struct spi_master *master = spi->master; | 747 | struct spi_master *master = spi->master; |
811 | struct omap2_mcspi *mcspi; | 748 | struct omap2_mcspi *mcspi; |
812 | struct omap2_mcspi_dma *mcspi_dma; | 749 | struct omap2_mcspi_dma *mcspi_dma; |
813 | dma_cap_mask_t mask; | ||
814 | unsigned sig; | ||
815 | 750 | ||
816 | mcspi = spi_master_get_devdata(master); | 751 | mcspi = spi_master_get_devdata(master); |
817 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | 752 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
818 | 753 | ||
819 | init_completion(&mcspi_dma->dma_rx_completion); | 754 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
820 | init_completion(&mcspi_dma->dma_tx_completion); | 755 | omap2_mcspi_dma_rx_callback, spi, |
821 | 756 | &mcspi_dma->dma_rx_channel)) { | |
822 | dma_cap_zero(mask); | 757 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
823 | dma_cap_set(DMA_SLAVE, mask); | ||
824 | sig = mcspi_dma->dma_rx_sync_dev; | ||
825 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | ||
826 | if (!mcspi_dma->dma_rx) { | ||
827 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); | ||
828 | return -EAGAIN; | 758 | return -EAGAIN; |
829 | } | 759 | } |
830 | 760 | ||
831 | sig = mcspi_dma->dma_tx_sync_dev; | 761 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
832 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | 762 | omap2_mcspi_dma_tx_callback, spi, |
833 | if (!mcspi_dma->dma_tx) { | 763 | &mcspi_dma->dma_tx_channel)) { |
834 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); | 764 | omap_free_dma(mcspi_dma->dma_rx_channel); |
835 | dma_release_channel(mcspi_dma->dma_rx); | 765 | mcspi_dma->dma_rx_channel = -1; |
836 | mcspi_dma->dma_rx = NULL; | 766 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
837 | return -EAGAIN; | 767 | return -EAGAIN; |
838 | } | 768 | } |
839 | 769 | ||
770 | init_completion(&mcspi_dma->dma_rx_completion); | ||
771 | init_completion(&mcspi_dma->dma_tx_completion); | ||
772 | |||
840 | return 0; | 773 | return 0; |
841 | } | 774 | } |
842 | 775 | ||
843 | static int omap2_mcspi_setup(struct spi_device *spi) | 776 | static int omap2_mcspi_setup(struct spi_device *spi) |
844 | { | 777 | { |
845 | int ret; | 778 | int ret; |
846 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | 779 | struct omap2_mcspi *mcspi; |
847 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | ||
848 | struct omap2_mcspi_dma *mcspi_dma; | 780 | struct omap2_mcspi_dma *mcspi_dma; |
849 | struct omap2_mcspi_cs *cs = spi->controller_state; | 781 | struct omap2_mcspi_cs *cs = spi->controller_state; |
850 | 782 | ||
@@ -854,6 +786,7 @@ static int omap2_mcspi_setup(struct spi_device *spi) | |||
854 | return -EINVAL; | 786 | return -EINVAL; |
855 | } | 787 | } |
856 | 788 | ||
789 | mcspi = spi_master_get_devdata(spi->master); | ||
857 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 790 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
858 | 791 | ||
859 | if (!cs) { | 792 | if (!cs) { |
@@ -865,22 +798,23 @@ static int omap2_mcspi_setup(struct spi_device *spi) | |||
865 | cs->chconf0 = 0; | 798 | cs->chconf0 = 0; |
866 | spi->controller_state = cs; | 799 | spi->controller_state = cs; |
867 | /* Link this to context save list */ | 800 | /* Link this to context save list */ |
868 | list_add_tail(&cs->node, &ctx->cs); | 801 | list_add_tail(&cs->node, |
802 | &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs); | ||
869 | } | 803 | } |
870 | 804 | ||
871 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { | 805 | if (mcspi_dma->dma_rx_channel == -1 |
806 | || mcspi_dma->dma_tx_channel == -1) { | ||
872 | ret = omap2_mcspi_request_dma(spi); | 807 | ret = omap2_mcspi_request_dma(spi); |
873 | if (ret < 0) | 808 | if (ret < 0) |
874 | return ret; | 809 | return ret; |
875 | } | 810 | } |
876 | 811 | ||
877 | ret = pm_runtime_get_sync(mcspi->dev); | 812 | ret = omap2_mcspi_enable_clocks(mcspi); |
878 | if (ret < 0) | 813 | if (ret < 0) |
879 | return ret; | 814 | return ret; |
880 | 815 | ||
881 | ret = omap2_mcspi_setup_transfer(spi, NULL); | 816 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
882 | pm_runtime_mark_last_busy(mcspi->dev); | 817 | omap2_mcspi_disable_clocks(mcspi); |
883 | pm_runtime_put_autosuspend(mcspi->dev); | ||
884 | 818 | ||
885 | return ret; | 819 | return ret; |
886 | } | 820 | } |
@@ -898,139 +832,161 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) | |||
898 | cs = spi->controller_state; | 832 | cs = spi->controller_state; |
899 | list_del(&cs->node); | 833 | list_del(&cs->node); |
900 | 834 | ||
901 | kfree(cs); | 835 | kfree(spi->controller_state); |
902 | } | 836 | } |
903 | 837 | ||
904 | if (spi->chip_select < spi->master->num_chipselect) { | 838 | if (spi->chip_select < spi->master->num_chipselect) { |
905 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 839 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
906 | 840 | ||
907 | if (mcspi_dma->dma_rx) { | 841 | if (mcspi_dma->dma_rx_channel != -1) { |
908 | dma_release_channel(mcspi_dma->dma_rx); | 842 | omap_free_dma(mcspi_dma->dma_rx_channel); |
909 | mcspi_dma->dma_rx = NULL; | 843 | mcspi_dma->dma_rx_channel = -1; |
910 | } | 844 | } |
911 | if (mcspi_dma->dma_tx) { | 845 | if (mcspi_dma->dma_tx_channel != -1) { |
912 | dma_release_channel(mcspi_dma->dma_tx); | 846 | omap_free_dma(mcspi_dma->dma_tx_channel); |
913 | mcspi_dma->dma_tx = NULL; | 847 | mcspi_dma->dma_tx_channel = -1; |
914 | } | 848 | } |
915 | } | 849 | } |
916 | } | 850 | } |
917 | 851 | ||
918 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | 852 | static void omap2_mcspi_work(struct work_struct *work) |
919 | { | 853 | { |
854 | struct omap2_mcspi *mcspi; | ||
855 | |||
856 | mcspi = container_of(work, struct omap2_mcspi, work); | ||
857 | |||
858 | if (omap2_mcspi_enable_clocks(mcspi) < 0) | ||
859 | return; | ||
860 | |||
861 | spin_lock_irq(&mcspi->lock); | ||
920 | 862 | ||
921 | /* We only enable one channel at a time -- the one whose message is | 863 | /* We only enable one channel at a time -- the one whose message is |
922 | * -- although this controller would gladly | 864 | * at the head of the queue -- although this controller would gladly |
923 | * arbitrate among multiple channels. This corresponds to "single | 865 | * arbitrate among multiple channels. This corresponds to "single |
924 | * channel" master mode. As a side effect, we need to manage the | 866 | * channel" master mode. As a side effect, we need to manage the |
925 | * chipselect with the FORCE bit ... CS != channel enable. | 867 | * chipselect with the FORCE bit ... CS != channel enable. |
926 | */ | 868 | */ |
869 | while (!list_empty(&mcspi->msg_queue)) { | ||
870 | struct spi_message *m; | ||
871 | struct spi_device *spi; | ||
872 | struct spi_transfer *t = NULL; | ||
873 | int cs_active = 0; | ||
874 | struct omap2_mcspi_cs *cs; | ||
875 | struct omap2_mcspi_device_config *cd; | ||
876 | int par_override = 0; | ||
877 | int status = 0; | ||
878 | u32 chconf; | ||
879 | |||
880 | m = container_of(mcspi->msg_queue.next, struct spi_message, | ||
881 | queue); | ||
882 | |||
883 | list_del_init(&m->queue); | ||
884 | spin_unlock_irq(&mcspi->lock); | ||
885 | |||
886 | spi = m->spi; | ||
887 | cs = spi->controller_state; | ||
888 | cd = spi->controller_data; | ||
927 | 889 | ||
928 | struct spi_device *spi; | 890 | omap2_mcspi_set_enable(spi, 1); |
929 | struct spi_transfer *t = NULL; | 891 | list_for_each_entry(t, &m->transfers, transfer_list) { |
930 | int cs_active = 0; | 892 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
931 | struct omap2_mcspi_cs *cs; | 893 | status = -EINVAL; |
932 | struct omap2_mcspi_device_config *cd; | ||
933 | int par_override = 0; | ||
934 | int status = 0; | ||
935 | u32 chconf; | ||
936 | |||
937 | spi = m->spi; | ||
938 | cs = spi->controller_state; | ||
939 | cd = spi->controller_data; | ||
940 | |||
941 | omap2_mcspi_set_enable(spi, 1); | ||
942 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
943 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | ||
944 | status = -EINVAL; | ||
945 | break; | ||
946 | } | ||
947 | if (par_override || t->speed_hz || t->bits_per_word) { | ||
948 | par_override = 1; | ||
949 | status = omap2_mcspi_setup_transfer(spi, t); | ||
950 | if (status < 0) | ||
951 | break; | 894 | break; |
952 | if (!t->speed_hz && !t->bits_per_word) | 895 | } |
953 | par_override = 0; | 896 | if (par_override || t->speed_hz || t->bits_per_word) { |
954 | } | 897 | par_override = 1; |
898 | status = omap2_mcspi_setup_transfer(spi, t); | ||
899 | if (status < 0) | ||
900 | break; | ||
901 | if (!t->speed_hz && !t->bits_per_word) | ||
902 | par_override = 0; | ||
903 | } | ||
955 | 904 | ||
956 | if (!cs_active) { | 905 | if (!cs_active) { |
957 | omap2_mcspi_force_cs(spi, 1); | 906 | omap2_mcspi_force_cs(spi, 1); |
958 | cs_active = 1; | 907 | cs_active = 1; |
959 | } | 908 | } |
960 | 909 | ||
961 | chconf = mcspi_cached_chconf0(spi); | 910 | chconf = mcspi_cached_chconf0(spi); |
962 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | 911 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
963 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | 912 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
964 | 913 | ||
965 | if (t->tx_buf == NULL) | 914 | if (t->tx_buf == NULL) |
966 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | 915 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
967 | else if (t->rx_buf == NULL) | 916 | else if (t->rx_buf == NULL) |
968 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | 917 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
918 | |||
919 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | ||
920 | /* Turbo mode is for more than one word */ | ||
921 | if (t->len > ((cs->word_len + 7) >> 3)) | ||
922 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | ||
923 | } | ||
969 | 924 | ||
970 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | 925 | mcspi_write_chconf0(spi, chconf); |
971 | /* Turbo mode is for more than one word */ | ||
972 | if (t->len > ((cs->word_len + 7) >> 3)) | ||
973 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | ||
974 | } | ||
975 | 926 | ||
976 | mcspi_write_chconf0(spi, chconf); | 927 | if (t->len) { |
928 | unsigned count; | ||
977 | 929 | ||
978 | if (t->len) { | 930 | /* RX_ONLY mode needs dummy data in TX reg */ |
979 | unsigned count; | 931 | if (t->tx_buf == NULL) |
932 | __raw_writel(0, cs->base | ||
933 | + OMAP2_MCSPI_TX0); | ||
980 | 934 | ||
981 | /* RX_ONLY mode needs dummy data in TX reg */ | 935 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
982 | if (t->tx_buf == NULL) | 936 | count = omap2_mcspi_txrx_dma(spi, t); |
983 | __raw_writel(0, cs->base | 937 | else |
984 | + OMAP2_MCSPI_TX0); | 938 | count = omap2_mcspi_txrx_pio(spi, t); |
939 | m->actual_length += count; | ||
940 | |||
941 | if (count != t->len) { | ||
942 | status = -EIO; | ||
943 | break; | ||
944 | } | ||
945 | } | ||
985 | 946 | ||
986 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) | 947 | if (t->delay_usecs) |
987 | count = omap2_mcspi_txrx_dma(spi, t); | 948 | udelay(t->delay_usecs); |
988 | else | ||
989 | count = omap2_mcspi_txrx_pio(spi, t); | ||
990 | m->actual_length += count; | ||
991 | 949 | ||
992 | if (count != t->len) { | 950 | /* ignore the "leave it on after last xfer" hint */ |
993 | status = -EIO; | 951 | if (t->cs_change) { |
994 | break; | 952 | omap2_mcspi_force_cs(spi, 0); |
953 | cs_active = 0; | ||
995 | } | 954 | } |
996 | } | 955 | } |
997 | 956 | ||
998 | if (t->delay_usecs) | 957 | /* Restore defaults if they were overriden */ |
999 | udelay(t->delay_usecs); | 958 | if (par_override) { |
959 | par_override = 0; | ||
960 | status = omap2_mcspi_setup_transfer(spi, NULL); | ||
961 | } | ||
1000 | 962 | ||
1001 | /* ignore the "leave it on after last xfer" hint */ | 963 | if (cs_active) |
1002 | if (t->cs_change) { | ||
1003 | omap2_mcspi_force_cs(spi, 0); | 964 | omap2_mcspi_force_cs(spi, 0); |
1004 | cs_active = 0; | ||
1005 | } | ||
1006 | } | ||
1007 | /* Restore defaults if they were overriden */ | ||
1008 | if (par_override) { | ||
1009 | par_override = 0; | ||
1010 | status = omap2_mcspi_setup_transfer(spi, NULL); | ||
1011 | } | ||
1012 | 965 | ||
1013 | if (cs_active) | 966 | omap2_mcspi_set_enable(spi, 0); |
1014 | omap2_mcspi_force_cs(spi, 0); | ||
1015 | 967 | ||
1016 | omap2_mcspi_set_enable(spi, 0); | 968 | m->status = status; |
969 | m->complete(m->context); | ||
1017 | 970 | ||
1018 | m->status = status; | 971 | spin_lock_irq(&mcspi->lock); |
972 | } | ||
1019 | 973 | ||
974 | spin_unlock_irq(&mcspi->lock); | ||
975 | |||
976 | omap2_mcspi_disable_clocks(mcspi); | ||
1020 | } | 977 | } |
1021 | 978 | ||
1022 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, | 979 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) |
1023 | struct spi_message *m) | ||
1024 | { | 980 | { |
1025 | struct omap2_mcspi *mcspi; | 981 | struct omap2_mcspi *mcspi; |
982 | unsigned long flags; | ||
1026 | struct spi_transfer *t; | 983 | struct spi_transfer *t; |
1027 | 984 | ||
1028 | mcspi = spi_master_get_devdata(master); | ||
1029 | m->actual_length = 0; | 985 | m->actual_length = 0; |
1030 | m->status = 0; | 986 | m->status = 0; |
1031 | 987 | ||
1032 | /* reject invalid messages and transfers */ | 988 | /* reject invalid messages and transfers */ |
1033 | if (list_empty(&m->transfers)) | 989 | if (list_empty(&m->transfers) || !m->complete) |
1034 | return -EINVAL; | 990 | return -EINVAL; |
1035 | list_for_each_entry(t, &m->transfers, transfer_list) { | 991 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1036 | const void *tx_buf = t->tx_buf; | 992 | const void *tx_buf = t->tx_buf; |
@@ -1042,7 +998,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, | |||
1042 | || (t->bits_per_word && | 998 | || (t->bits_per_word && |
1043 | ( t->bits_per_word < 4 | 999 | ( t->bits_per_word < 4 |
1044 | || t->bits_per_word > 32))) { | 1000 | || t->bits_per_word > 32))) { |
1045 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | 1001 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
1046 | t->speed_hz, | 1002 | t->speed_hz, |
1047 | len, | 1003 | len, |
1048 | tx_buf ? "tx" : "", | 1004 | tx_buf ? "tx" : "", |
@@ -1051,7 +1007,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, | |||
1051 | return -EINVAL; | 1007 | return -EINVAL; |
1052 | } | 1008 | } |
1053 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { | 1009 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
1054 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", | 1010 | dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n", |
1055 | t->speed_hz, | 1011 | t->speed_hz, |
1056 | OMAP2_MCSPI_MAX_FREQ >> 15); | 1012 | OMAP2_MCSPI_MAX_FREQ >> 15); |
1057 | return -EINVAL; | 1013 | return -EINVAL; |
@@ -1061,50 +1017,54 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, | |||
1061 | continue; | 1017 | continue; |
1062 | 1018 | ||
1063 | if (tx_buf != NULL) { | 1019 | if (tx_buf != NULL) { |
1064 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, | 1020 | t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf, |
1065 | len, DMA_TO_DEVICE); | 1021 | len, DMA_TO_DEVICE); |
1066 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { | 1022 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
1067 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | 1023 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1068 | 'T', len); | 1024 | 'T', len); |
1069 | return -EINVAL; | 1025 | return -EINVAL; |
1070 | } | 1026 | } |
1071 | } | 1027 | } |
1072 | if (rx_buf != NULL) { | 1028 | if (rx_buf != NULL) { |
1073 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, | 1029 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len, |
1074 | DMA_FROM_DEVICE); | 1030 | DMA_FROM_DEVICE); |
1075 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { | 1031 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
1076 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | 1032 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1077 | 'R', len); | 1033 | 'R', len); |
1078 | if (tx_buf != NULL) | 1034 | if (tx_buf != NULL) |
1079 | dma_unmap_single(mcspi->dev, t->tx_dma, | 1035 | dma_unmap_single(&spi->dev, t->tx_dma, |
1080 | len, DMA_TO_DEVICE); | 1036 | len, DMA_TO_DEVICE); |
1081 | return -EINVAL; | 1037 | return -EINVAL; |
1082 | } | 1038 | } |
1083 | } | 1039 | } |
1084 | } | 1040 | } |
1085 | 1041 | ||
1086 | omap2_mcspi_work(mcspi, m); | 1042 | mcspi = spi_master_get_devdata(spi->master); |
1087 | spi_finalize_current_message(master); | 1043 | |
1044 | spin_lock_irqsave(&mcspi->lock, flags); | ||
1045 | list_add_tail(&m->queue, &mcspi->msg_queue); | ||
1046 | queue_work(omap2_mcspi_wq, &mcspi->work); | ||
1047 | spin_unlock_irqrestore(&mcspi->lock, flags); | ||
1048 | |||
1088 | return 0; | 1049 | return 0; |
1089 | } | 1050 | } |
1090 | 1051 | ||
1091 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) | 1052 | static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
1092 | { | 1053 | { |
1093 | struct spi_master *master = mcspi->master; | 1054 | struct spi_master *master = mcspi->master; |
1094 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | 1055 | u32 tmp; |
1095 | int ret = 0; | 1056 | int ret = 0; |
1096 | 1057 | ||
1097 | ret = pm_runtime_get_sync(mcspi->dev); | 1058 | ret = omap2_mcspi_enable_clocks(mcspi); |
1098 | if (ret < 0) | 1059 | if (ret < 0) |
1099 | return ret; | 1060 | return ret; |
1100 | 1061 | ||
1101 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, | 1062 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
1102 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | 1063 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); |
1103 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | 1064 | omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp; |
1104 | 1065 | ||
1105 | omap2_mcspi_set_master_mode(master); | 1066 | omap2_mcspi_set_master_mode(master); |
1106 | pm_runtime_mark_last_busy(mcspi->dev); | 1067 | omap2_mcspi_disable_clocks(mcspi); |
1107 | pm_runtime_put_autosuspend(mcspi->dev); | ||
1108 | return 0; | 1068 | return 0; |
1109 | } | 1069 | } |
1110 | 1070 | ||
@@ -1120,39 +1080,14 @@ static int omap_mcspi_runtime_resume(struct device *dev) | |||
1120 | return 0; | 1080 | return 0; |
1121 | } | 1081 | } |
1122 | 1082 | ||
1123 | static struct omap2_mcspi_platform_config omap2_pdata = { | ||
1124 | .regs_offset = 0, | ||
1125 | }; | ||
1126 | |||
1127 | static struct omap2_mcspi_platform_config omap4_pdata = { | ||
1128 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | ||
1129 | }; | ||
1130 | |||
1131 | static const struct of_device_id omap_mcspi_of_match[] = { | ||
1132 | { | ||
1133 | .compatible = "ti,omap2-mcspi", | ||
1134 | .data = &omap2_pdata, | ||
1135 | }, | ||
1136 | { | ||
1137 | .compatible = "ti,omap4-mcspi", | ||
1138 | .data = &omap4_pdata, | ||
1139 | }, | ||
1140 | { }, | ||
1141 | }; | ||
1142 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | ||
1143 | 1083 | ||
1144 | static int omap2_mcspi_probe(struct platform_device *pdev) | 1084 | static int __init omap2_mcspi_probe(struct platform_device *pdev) |
1145 | { | 1085 | { |
1146 | struct spi_master *master; | 1086 | struct spi_master *master; |
1147 | const struct omap2_mcspi_platform_config *pdata; | 1087 | struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; |
1148 | struct omap2_mcspi *mcspi; | 1088 | struct omap2_mcspi *mcspi; |
1149 | struct resource *r; | 1089 | struct resource *r; |
1150 | int status = 0, i; | 1090 | int status = 0, i; |
1151 | u32 regs_offset = 0; | ||
1152 | static int bus_num = 1; | ||
1153 | struct device_node *node = pdev->dev.of_node; | ||
1154 | const struct of_device_id *match; | ||
1155 | struct pinctrl *pinctrl; | ||
1156 | 1091 | ||
1157 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | 1092 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
1158 | if (master == NULL) { | 1093 | if (master == NULL) { |
@@ -1163,64 +1098,54 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1163 | /* the spi->mode bits understood by this driver: */ | 1098 | /* the spi->mode bits understood by this driver: */ |
1164 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 1099 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1165 | 1100 | ||
1101 | if (pdev->id != -1) | ||
1102 | master->bus_num = pdev->id; | ||
1103 | |||
1166 | master->setup = omap2_mcspi_setup; | 1104 | master->setup = omap2_mcspi_setup; |
1167 | master->prepare_transfer_hardware = omap2_prepare_transfer; | 1105 | master->transfer = omap2_mcspi_transfer; |
1168 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; | ||
1169 | master->transfer_one_message = omap2_mcspi_transfer_one_message; | ||
1170 | master->cleanup = omap2_mcspi_cleanup; | 1106 | master->cleanup = omap2_mcspi_cleanup; |
1171 | master->dev.of_node = node; | 1107 | master->num_chipselect = pdata->num_cs; |
1172 | 1108 | ||
1173 | dev_set_drvdata(&pdev->dev, master); | 1109 | dev_set_drvdata(&pdev->dev, master); |
1174 | 1110 | ||
1175 | mcspi = spi_master_get_devdata(master); | 1111 | mcspi = spi_master_get_devdata(master); |
1176 | mcspi->master = master; | 1112 | mcspi->master = master; |
1177 | 1113 | ||
1178 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); | ||
1179 | if (match) { | ||
1180 | u32 num_cs = 1; /* default number of chipselect */ | ||
1181 | pdata = match->data; | ||
1182 | |||
1183 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | ||
1184 | master->num_chipselect = num_cs; | ||
1185 | master->bus_num = bus_num++; | ||
1186 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) | ||
1187 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | ||
1188 | } else { | ||
1189 | pdata = pdev->dev.platform_data; | ||
1190 | master->num_chipselect = pdata->num_cs; | ||
1191 | if (pdev->id != -1) | ||
1192 | master->bus_num = pdev->id; | ||
1193 | mcspi->pin_dir = pdata->pin_dir; | ||
1194 | } | ||
1195 | regs_offset = pdata->regs_offset; | ||
1196 | |||
1197 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1114 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1198 | if (r == NULL) { | 1115 | if (r == NULL) { |
1199 | status = -ENODEV; | 1116 | status = -ENODEV; |
1200 | goto free_master; | 1117 | goto err1; |
1201 | } | 1118 | } |
1202 | 1119 | ||
1203 | r->start += regs_offset; | 1120 | r->start += pdata->regs_offset; |
1204 | r->end += regs_offset; | 1121 | r->end += pdata->regs_offset; |
1205 | mcspi->phys = r->start; | 1122 | mcspi->phys = r->start; |
1123 | if (!request_mem_region(r->start, resource_size(r), | ||
1124 | dev_name(&pdev->dev))) { | ||
1125 | status = -EBUSY; | ||
1126 | goto err1; | ||
1127 | } | ||
1206 | 1128 | ||
1207 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); | 1129 | mcspi->base = ioremap(r->start, resource_size(r)); |
1208 | if (!mcspi->base) { | 1130 | if (!mcspi->base) { |
1209 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | 1131 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
1210 | status = -ENOMEM; | 1132 | status = -ENOMEM; |
1211 | goto free_master; | 1133 | goto err2; |
1212 | } | 1134 | } |
1213 | 1135 | ||
1214 | mcspi->dev = &pdev->dev; | 1136 | mcspi->dev = &pdev->dev; |
1137 | INIT_WORK(&mcspi->work, omap2_mcspi_work); | ||
1215 | 1138 | ||
1216 | INIT_LIST_HEAD(&mcspi->ctx.cs); | 1139 | spin_lock_init(&mcspi->lock); |
1140 | INIT_LIST_HEAD(&mcspi->msg_queue); | ||
1141 | INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); | ||
1217 | 1142 | ||
1218 | mcspi->dma_channels = kcalloc(master->num_chipselect, | 1143 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1219 | sizeof(struct omap2_mcspi_dma), | 1144 | sizeof(struct omap2_mcspi_dma), |
1220 | GFP_KERNEL); | 1145 | GFP_KERNEL); |
1221 | 1146 | ||
1222 | if (mcspi->dma_channels == NULL) | 1147 | if (mcspi->dma_channels == NULL) |
1223 | goto free_master; | 1148 | goto err2; |
1224 | 1149 | ||
1225 | for (i = 0; i < master->num_chipselect; i++) { | 1150 | for (i = 0; i < master->num_chipselect; i++) { |
1226 | char dma_ch_name[14]; | 1151 | char dma_ch_name[14]; |
@@ -1235,6 +1160,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1235 | break; | 1160 | break; |
1236 | } | 1161 | } |
1237 | 1162 | ||
1163 | mcspi->dma_channels[i].dma_rx_channel = -1; | ||
1238 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; | 1164 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1239 | sprintf(dma_ch_name, "tx%d", i); | 1165 | sprintf(dma_ch_name, "tx%d", i); |
1240 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | 1166 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
@@ -1245,53 +1171,51 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1245 | break; | 1171 | break; |
1246 | } | 1172 | } |
1247 | 1173 | ||
1174 | mcspi->dma_channels[i].dma_tx_channel = -1; | ||
1248 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; | 1175 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
1249 | } | 1176 | } |
1250 | 1177 | ||
1251 | if (status < 0) | ||
1252 | goto dma_chnl_free; | ||
1253 | |||
1254 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
1255 | if (IS_ERR(pinctrl)) | ||
1256 | dev_warn(&pdev->dev, | ||
1257 | "pins are not configured from the driver\n"); | ||
1258 | |||
1259 | pm_runtime_use_autosuspend(&pdev->dev); | ||
1260 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | ||
1261 | pm_runtime_enable(&pdev->dev); | 1178 | pm_runtime_enable(&pdev->dev); |
1262 | 1179 | ||
1263 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | 1180 | if (status || omap2_mcspi_master_setup(mcspi) < 0) |
1264 | goto disable_pm; | 1181 | goto err3; |
1265 | 1182 | ||
1266 | status = spi_register_master(master); | 1183 | status = spi_register_master(master); |
1267 | if (status < 0) | 1184 | if (status < 0) |
1268 | goto disable_pm; | 1185 | goto err4; |
1269 | 1186 | ||
1270 | return status; | 1187 | return status; |
1271 | 1188 | ||
1272 | disable_pm: | 1189 | err4: |
1273 | pm_runtime_disable(&pdev->dev); | ||
1274 | dma_chnl_free: | ||
1275 | kfree(mcspi->dma_channels); | ||
1276 | free_master: | ||
1277 | spi_master_put(master); | 1190 | spi_master_put(master); |
1191 | err3: | ||
1192 | kfree(mcspi->dma_channels); | ||
1193 | err2: | ||
1194 | release_mem_region(r->start, resource_size(r)); | ||
1195 | iounmap(mcspi->base); | ||
1196 | err1: | ||
1278 | return status; | 1197 | return status; |
1279 | } | 1198 | } |
1280 | 1199 | ||
1281 | static int omap2_mcspi_remove(struct platform_device *pdev) | 1200 | static int __exit omap2_mcspi_remove(struct platform_device *pdev) |
1282 | { | 1201 | { |
1283 | struct spi_master *master; | 1202 | struct spi_master *master; |
1284 | struct omap2_mcspi *mcspi; | 1203 | struct omap2_mcspi *mcspi; |
1285 | struct omap2_mcspi_dma *dma_channels; | 1204 | struct omap2_mcspi_dma *dma_channels; |
1205 | struct resource *r; | ||
1206 | void __iomem *base; | ||
1286 | 1207 | ||
1287 | master = dev_get_drvdata(&pdev->dev); | 1208 | master = dev_get_drvdata(&pdev->dev); |
1288 | mcspi = spi_master_get_devdata(master); | 1209 | mcspi = spi_master_get_devdata(master); |
1289 | dma_channels = mcspi->dma_channels; | 1210 | dma_channels = mcspi->dma_channels; |
1290 | 1211 | ||
1291 | pm_runtime_put_sync(mcspi->dev); | 1212 | omap2_mcspi_disable_clocks(mcspi); |
1292 | pm_runtime_disable(&pdev->dev); | 1213 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1214 | release_mem_region(r->start, resource_size(r)); | ||
1293 | 1215 | ||
1216 | base = mcspi->base; | ||
1294 | spi_unregister_master(master); | 1217 | spi_unregister_master(master); |
1218 | iounmap(base); | ||
1295 | kfree(dma_channels); | 1219 | kfree(dma_channels); |
1296 | 1220 | ||
1297 | return 0; | 1221 | return 0; |
@@ -1310,24 +1234,24 @@ static int omap2_mcspi_resume(struct device *dev) | |||
1310 | { | 1234 | { |
1311 | struct spi_master *master = dev_get_drvdata(dev); | 1235 | struct spi_master *master = dev_get_drvdata(dev); |
1312 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | 1236 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
1313 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | 1237 | struct omap2_mcspi_cs *cs; |
1314 | struct omap2_mcspi_cs *cs; | ||
1315 | 1238 | ||
1316 | pm_runtime_get_sync(mcspi->dev); | 1239 | omap2_mcspi_enable_clocks(mcspi); |
1317 | list_for_each_entry(cs, &ctx->cs, node) { | 1240 | list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs, |
1241 | node) { | ||
1318 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { | 1242 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
1243 | |||
1319 | /* | 1244 | /* |
1320 | * We need to toggle CS state for OMAP take this | 1245 | * We need to toggle CS state for OMAP take this |
1321 | * change in account. | 1246 | * change in account. |
1322 | */ | 1247 | */ |
1323 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; | 1248 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); |
1324 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 1249 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1325 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | 1250 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); |
1326 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 1251 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1327 | } | 1252 | } |
1328 | } | 1253 | } |
1329 | pm_runtime_mark_last_busy(mcspi->dev); | 1254 | omap2_mcspi_disable_clocks(mcspi); |
1330 | pm_runtime_put_autosuspend(mcspi->dev); | ||
1331 | return 0; | 1255 | return 0; |
1332 | } | 1256 | } |
1333 | #else | 1257 | #else |
@@ -1343,12 +1267,28 @@ static struct platform_driver omap2_mcspi_driver = { | |||
1343 | .driver = { | 1267 | .driver = { |
1344 | .name = "omap2_mcspi", | 1268 | .name = "omap2_mcspi", |
1345 | .owner = THIS_MODULE, | 1269 | .owner = THIS_MODULE, |
1346 | .pm = &omap2_mcspi_pm_ops, | 1270 | .pm = &omap2_mcspi_pm_ops |
1347 | .of_match_table = omap_mcspi_of_match, | ||
1348 | }, | 1271 | }, |
1349 | .probe = omap2_mcspi_probe, | 1272 | .remove = __exit_p(omap2_mcspi_remove), |
1350 | .remove = omap2_mcspi_remove, | ||
1351 | }; | 1273 | }; |
1352 | 1274 | ||
1353 | module_platform_driver(omap2_mcspi_driver); | 1275 | |
1276 | static int __init omap2_mcspi_init(void) | ||
1277 | { | ||
1278 | omap2_mcspi_wq = create_singlethread_workqueue( | ||
1279 | omap2_mcspi_driver.driver.name); | ||
1280 | if (omap2_mcspi_wq == NULL) | ||
1281 | return -1; | ||
1282 | return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe); | ||
1283 | } | ||
1284 | subsys_initcall(omap2_mcspi_init); | ||
1285 | |||
1286 | static void __exit omap2_mcspi_exit(void) | ||
1287 | { | ||
1288 | platform_driver_unregister(&omap2_mcspi_driver); | ||
1289 | |||
1290 | destroy_workqueue(omap2_mcspi_wq); | ||
1291 | } | ||
1292 | module_exit(omap2_mcspi_exit); | ||
1293 | |||
1354 | MODULE_LICENSE("GPL"); | 1294 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index b7e718254b1..9421a390a5e 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c | |||
@@ -16,9 +16,7 @@ | |||
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/spi/spi.h> | 18 | #include <linux/spi/spi.h> |
19 | #include <linux/module.h> | 19 | #include <linux/spi/orion_spi.h> |
20 | #include <linux/of.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <asm/unaligned.h> | 20 | #include <asm/unaligned.h> |
23 | 21 | ||
24 | #define DRIVER_NAME "orion_spi" | 22 | #define DRIVER_NAME "orion_spi" |
@@ -32,21 +30,25 @@ | |||
32 | #define ORION_SPI_DATA_IN_REG 0x0c | 30 | #define ORION_SPI_DATA_IN_REG 0x0c |
33 | #define ORION_SPI_INT_CAUSE_REG 0x10 | 31 | #define ORION_SPI_INT_CAUSE_REG 0x10 |
34 | 32 | ||
35 | #define ORION_SPI_MODE_CPOL (1 << 11) | ||
36 | #define ORION_SPI_MODE_CPHA (1 << 12) | ||
37 | #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) | 33 | #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) |
38 | #define ORION_SPI_CLK_PRESCALE_MASK 0x1F | 34 | #define ORION_SPI_CLK_PRESCALE_MASK 0x1F |
39 | #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ | ||
40 | ORION_SPI_MODE_CPHA) | ||
41 | 35 | ||
42 | struct orion_spi { | 36 | struct orion_spi { |
37 | struct work_struct work; | ||
38 | |||
39 | /* Lock access to transfer list. */ | ||
40 | spinlock_t lock; | ||
41 | |||
42 | struct list_head msg_queue; | ||
43 | struct spi_master *master; | 43 | struct spi_master *master; |
44 | void __iomem *base; | 44 | void __iomem *base; |
45 | unsigned int max_speed; | 45 | unsigned int max_speed; |
46 | unsigned int min_speed; | 46 | unsigned int min_speed; |
47 | struct clk *clk; | 47 | struct orion_spi_info *spi_info; |
48 | }; | 48 | }; |
49 | 49 | ||
50 | static struct workqueue_struct *orion_spi_wq; | ||
51 | |||
50 | static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) | 52 | static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
51 | { | 53 | { |
52 | return orion_spi->base + reg; | 54 | return orion_spi->base + reg; |
@@ -101,7 +103,7 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) | |||
101 | 103 | ||
102 | orion_spi = spi_master_get_devdata(spi->master); | 104 | orion_spi = spi_master_get_devdata(spi->master); |
103 | 105 | ||
104 | tclk_hz = clk_get_rate(orion_spi->clk); | 106 | tclk_hz = orion_spi->spi_info->tclk; |
105 | 107 | ||
106 | /* | 108 | /* |
107 | * the supported rates are: 4,6,8...30 | 109 | * the supported rates are: 4,6,8...30 |
@@ -127,23 +129,6 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) | |||
127 | return 0; | 129 | return 0; |
128 | } | 130 | } |
129 | 131 | ||
130 | static void | ||
131 | orion_spi_mode_set(struct spi_device *spi) | ||
132 | { | ||
133 | u32 reg; | ||
134 | struct orion_spi *orion_spi; | ||
135 | |||
136 | orion_spi = spi_master_get_devdata(spi->master); | ||
137 | |||
138 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | ||
139 | reg &= ~ORION_SPI_MODE_MASK; | ||
140 | if (spi->mode & SPI_CPOL) | ||
141 | reg |= ORION_SPI_MODE_CPOL; | ||
142 | if (spi->mode & SPI_CPHA) | ||
143 | reg |= ORION_SPI_MODE_CPHA; | ||
144 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | ||
145 | } | ||
146 | |||
147 | /* | 132 | /* |
148 | * called only when no transfer is active on the bus | 133 | * called only when no transfer is active on the bus |
149 | */ | 134 | */ |
@@ -163,8 +148,6 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |||
163 | if ((t != NULL) && t->bits_per_word) | 148 | if ((t != NULL) && t->bits_per_word) |
164 | bits_per_word = t->bits_per_word; | 149 | bits_per_word = t->bits_per_word; |
165 | 150 | ||
166 | orion_spi_mode_set(spi); | ||
167 | |||
168 | rc = orion_spi_baudrate_set(spi, speed); | 151 | rc = orion_spi_baudrate_set(spi, speed); |
169 | if (rc) | 152 | if (rc) |
170 | return rc; | 153 | return rc; |
@@ -292,78 +275,73 @@ out: | |||
292 | } | 275 | } |
293 | 276 | ||
294 | 277 | ||
295 | static int orion_spi_transfer_one_message(struct spi_master *master, | 278 | static void orion_spi_work(struct work_struct *work) |
296 | struct spi_message *m) | ||
297 | { | 279 | { |
298 | struct orion_spi *orion_spi = spi_master_get_devdata(master); | 280 | struct orion_spi *orion_spi = |
299 | struct spi_device *spi = m->spi; | 281 | container_of(work, struct orion_spi, work); |
300 | struct spi_transfer *t = NULL; | ||
301 | int par_override = 0; | ||
302 | int status = 0; | ||
303 | int cs_active = 0; | ||
304 | 282 | ||
305 | /* Load defaults */ | 283 | spin_lock_irq(&orion_spi->lock); |
306 | status = orion_spi_setup_transfer(spi, NULL); | 284 | while (!list_empty(&orion_spi->msg_queue)) { |
285 | struct spi_message *m; | ||
286 | struct spi_device *spi; | ||
287 | struct spi_transfer *t = NULL; | ||
288 | int par_override = 0; | ||
289 | int status = 0; | ||
290 | int cs_active = 0; | ||
307 | 291 | ||
308 | if (status < 0) | 292 | m = container_of(orion_spi->msg_queue.next, struct spi_message, |
309 | goto msg_done; | 293 | queue); |
310 | 294 | ||
311 | list_for_each_entry(t, &m->transfers, transfer_list) { | 295 | list_del_init(&m->queue); |
312 | /* make sure buffer length is even when working in 16 | 296 | spin_unlock_irq(&orion_spi->lock); |
313 | * bit mode*/ | ||
314 | if ((t->bits_per_word == 16) && (t->len & 1)) { | ||
315 | dev_err(&spi->dev, | ||
316 | "message rejected : " | ||
317 | "odd data length %d while in 16 bit mode\n", | ||
318 | t->len); | ||
319 | status = -EIO; | ||
320 | goto msg_done; | ||
321 | } | ||
322 | 297 | ||
323 | if (t->speed_hz && t->speed_hz < orion_spi->min_speed) { | 298 | spi = m->spi; |
324 | dev_err(&spi->dev, | ||
325 | "message rejected : " | ||
326 | "device min speed (%d Hz) exceeds " | ||
327 | "required transfer speed (%d Hz)\n", | ||
328 | orion_spi->min_speed, t->speed_hz); | ||
329 | status = -EIO; | ||
330 | goto msg_done; | ||
331 | } | ||
332 | 299 | ||
333 | if (par_override || t->speed_hz || t->bits_per_word) { | 300 | /* Load defaults */ |
334 | par_override = 1; | 301 | status = orion_spi_setup_transfer(spi, NULL); |
335 | status = orion_spi_setup_transfer(spi, t); | ||
336 | if (status < 0) | ||
337 | break; | ||
338 | if (!t->speed_hz && !t->bits_per_word) | ||
339 | par_override = 0; | ||
340 | } | ||
341 | 302 | ||
342 | if (!cs_active) { | 303 | if (status < 0) |
343 | orion_spi_set_cs(orion_spi, 1); | 304 | goto msg_done; |
344 | cs_active = 1; | ||
345 | } | ||
346 | |||
347 | if (t->len) | ||
348 | m->actual_length += orion_spi_write_read(spi, t); | ||
349 | |||
350 | if (t->delay_usecs) | ||
351 | udelay(t->delay_usecs); | ||
352 | 305 | ||
353 | if (t->cs_change) { | 306 | list_for_each_entry(t, &m->transfers, transfer_list) { |
354 | orion_spi_set_cs(orion_spi, 0); | 307 | if (par_override || t->speed_hz || t->bits_per_word) { |
355 | cs_active = 0; | 308 | par_override = 1; |
309 | status = orion_spi_setup_transfer(spi, t); | ||
310 | if (status < 0) | ||
311 | break; | ||
312 | if (!t->speed_hz && !t->bits_per_word) | ||
313 | par_override = 0; | ||
314 | } | ||
315 | |||
316 | if (!cs_active) { | ||
317 | orion_spi_set_cs(orion_spi, 1); | ||
318 | cs_active = 1; | ||
319 | } | ||
320 | |||
321 | if (t->len) | ||
322 | m->actual_length += | ||
323 | orion_spi_write_read(spi, t); | ||
324 | |||
325 | if (t->delay_usecs) | ||
326 | udelay(t->delay_usecs); | ||
327 | |||
328 | if (t->cs_change) { | ||
329 | orion_spi_set_cs(orion_spi, 0); | ||
330 | cs_active = 0; | ||
331 | } | ||
356 | } | 332 | } |
357 | } | ||
358 | 333 | ||
359 | msg_done: | 334 | msg_done: |
360 | if (cs_active) | 335 | if (cs_active) |
361 | orion_spi_set_cs(orion_spi, 0); | 336 | orion_spi_set_cs(orion_spi, 0); |
362 | 337 | ||
363 | m->status = status; | 338 | m->status = status; |
364 | spi_finalize_current_message(master); | 339 | m->complete(m->context); |
365 | 340 | ||
366 | return 0; | 341 | spin_lock_irq(&orion_spi->lock); |
342 | } | ||
343 | |||
344 | spin_unlock_irq(&orion_spi->lock); | ||
367 | } | 345 | } |
368 | 346 | ||
369 | static int __init orion_spi_reset(struct orion_spi *orion_spi) | 347 | static int __init orion_spi_reset(struct orion_spi *orion_spi) |
@@ -380,6 +358,11 @@ static int orion_spi_setup(struct spi_device *spi) | |||
380 | 358 | ||
381 | orion_spi = spi_master_get_devdata(spi->master); | 359 | orion_spi = spi_master_get_devdata(spi->master); |
382 | 360 | ||
361 | /* Fix ac timing if required. */ | ||
362 | if (orion_spi->spi_info->enable_clock_fix) | ||
363 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | ||
364 | (1 << 14)); | ||
365 | |||
383 | if ((spi->max_speed_hz == 0) | 366 | if ((spi->max_speed_hz == 0) |
384 | || (spi->max_speed_hz > orion_spi->max_speed)) | 367 | || (spi->max_speed_hz > orion_spi->max_speed)) |
385 | spi->max_speed_hz = orion_spi->max_speed; | 368 | spi->max_speed_hz = orion_spi->max_speed; |
@@ -396,15 +379,84 @@ static int orion_spi_setup(struct spi_device *spi) | |||
396 | return 0; | 379 | return 0; |
397 | } | 380 | } |
398 | 381 | ||
382 | static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m) | ||
383 | { | ||
384 | struct orion_spi *orion_spi; | ||
385 | struct spi_transfer *t = NULL; | ||
386 | unsigned long flags; | ||
387 | |||
388 | m->actual_length = 0; | ||
389 | m->status = 0; | ||
390 | |||
391 | /* reject invalid messages and transfers */ | ||
392 | if (list_empty(&m->transfers) || !m->complete) | ||
393 | return -EINVAL; | ||
394 | |||
395 | orion_spi = spi_master_get_devdata(spi->master); | ||
396 | |||
397 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
398 | unsigned int bits_per_word = spi->bits_per_word; | ||
399 | |||
400 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | ||
401 | dev_err(&spi->dev, | ||
402 | "message rejected : " | ||
403 | "invalid transfer data buffers\n"); | ||
404 | goto msg_rejected; | ||
405 | } | ||
406 | |||
407 | if (t->bits_per_word) | ||
408 | bits_per_word = t->bits_per_word; | ||
409 | |||
410 | if ((bits_per_word != 8) && (bits_per_word != 16)) { | ||
411 | dev_err(&spi->dev, | ||
412 | "message rejected : " | ||
413 | "invalid transfer bits_per_word (%d bits)\n", | ||
414 | bits_per_word); | ||
415 | goto msg_rejected; | ||
416 | } | ||
417 | /*make sure buffer length is even when working in 16 bit mode*/ | ||
418 | if ((t->bits_per_word == 16) && (t->len & 1)) { | ||
419 | dev_err(&spi->dev, | ||
420 | "message rejected : " | ||
421 | "odd data length (%d) while in 16 bit mode\n", | ||
422 | t->len); | ||
423 | goto msg_rejected; | ||
424 | } | ||
425 | |||
426 | if (t->speed_hz && t->speed_hz < orion_spi->min_speed) { | ||
427 | dev_err(&spi->dev, | ||
428 | "message rejected : " | ||
429 | "device min speed (%d Hz) exceeds " | ||
430 | "required transfer speed (%d Hz)\n", | ||
431 | orion_spi->min_speed, t->speed_hz); | ||
432 | goto msg_rejected; | ||
433 | } | ||
434 | } | ||
435 | |||
436 | |||
437 | spin_lock_irqsave(&orion_spi->lock, flags); | ||
438 | list_add_tail(&m->queue, &orion_spi->msg_queue); | ||
439 | queue_work(orion_spi_wq, &orion_spi->work); | ||
440 | spin_unlock_irqrestore(&orion_spi->lock, flags); | ||
441 | |||
442 | return 0; | ||
443 | msg_rejected: | ||
444 | /* Message rejected and not queued */ | ||
445 | m->status = -EINVAL; | ||
446 | if (m->complete) | ||
447 | m->complete(m->context); | ||
448 | return -EINVAL; | ||
449 | } | ||
450 | |||
399 | static int __init orion_spi_probe(struct platform_device *pdev) | 451 | static int __init orion_spi_probe(struct platform_device *pdev) |
400 | { | 452 | { |
401 | struct spi_master *master; | 453 | struct spi_master *master; |
402 | struct orion_spi *spi; | 454 | struct orion_spi *spi; |
403 | struct resource *r; | 455 | struct resource *r; |
404 | unsigned long tclk_hz; | 456 | struct orion_spi_info *spi_info; |
405 | int status = 0; | 457 | int status = 0; |
406 | const u32 *iprop; | 458 | |
407 | int size; | 459 | spi_info = pdev->dev.platform_data; |
408 | 460 | ||
409 | master = spi_alloc_master(&pdev->dev, sizeof *spi); | 461 | master = spi_alloc_master(&pdev->dev, sizeof *spi); |
410 | if (master == NULL) { | 462 | if (master == NULL) { |
@@ -414,54 +466,44 @@ static int __init orion_spi_probe(struct platform_device *pdev) | |||
414 | 466 | ||
415 | if (pdev->id != -1) | 467 | if (pdev->id != -1) |
416 | master->bus_num = pdev->id; | 468 | master->bus_num = pdev->id; |
417 | if (pdev->dev.of_node) { | ||
418 | iprop = of_get_property(pdev->dev.of_node, "cell-index", | ||
419 | &size); | ||
420 | if (iprop && size == sizeof(*iprop)) | ||
421 | master->bus_num = *iprop; | ||
422 | } | ||
423 | 469 | ||
424 | /* we support only mode 0, and no options */ | 470 | /* we support only mode 0, and no options */ |
425 | master->mode_bits = SPI_CPHA | SPI_CPOL; | 471 | master->mode_bits = 0; |
426 | 472 | ||
427 | master->setup = orion_spi_setup; | 473 | master->setup = orion_spi_setup; |
428 | master->transfer_one_message = orion_spi_transfer_one_message; | 474 | master->transfer = orion_spi_transfer; |
429 | master->num_chipselect = ORION_NUM_CHIPSELECTS; | 475 | master->num_chipselect = ORION_NUM_CHIPSELECTS; |
430 | 476 | ||
431 | dev_set_drvdata(&pdev->dev, master); | 477 | dev_set_drvdata(&pdev->dev, master); |
432 | 478 | ||
433 | spi = spi_master_get_devdata(master); | 479 | spi = spi_master_get_devdata(master); |
434 | spi->master = master; | 480 | spi->master = master; |
481 | spi->spi_info = spi_info; | ||
435 | 482 | ||
436 | spi->clk = clk_get(&pdev->dev, NULL); | 483 | spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4); |
437 | if (IS_ERR(spi->clk)) { | 484 | spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30); |
438 | status = PTR_ERR(spi->clk); | ||
439 | goto out; | ||
440 | } | ||
441 | |||
442 | clk_prepare(spi->clk); | ||
443 | clk_enable(spi->clk); | ||
444 | tclk_hz = clk_get_rate(spi->clk); | ||
445 | spi->max_speed = DIV_ROUND_UP(tclk_hz, 4); | ||
446 | spi->min_speed = DIV_ROUND_UP(tclk_hz, 30); | ||
447 | 485 | ||
448 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 486 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
449 | if (r == NULL) { | 487 | if (r == NULL) { |
450 | status = -ENODEV; | 488 | status = -ENODEV; |
451 | goto out_rel_clk; | 489 | goto out; |
452 | } | 490 | } |
453 | 491 | ||
454 | if (!request_mem_region(r->start, resource_size(r), | 492 | if (!request_mem_region(r->start, resource_size(r), |
455 | dev_name(&pdev->dev))) { | 493 | dev_name(&pdev->dev))) { |
456 | status = -EBUSY; | 494 | status = -EBUSY; |
457 | goto out_rel_clk; | 495 | goto out; |
458 | } | 496 | } |
459 | spi->base = ioremap(r->start, SZ_1K); | 497 | spi->base = ioremap(r->start, SZ_1K); |
460 | 498 | ||
499 | INIT_WORK(&spi->work, orion_spi_work); | ||
500 | |||
501 | spin_lock_init(&spi->lock); | ||
502 | INIT_LIST_HEAD(&spi->msg_queue); | ||
503 | |||
461 | if (orion_spi_reset(spi) < 0) | 504 | if (orion_spi_reset(spi) < 0) |
462 | goto out_rel_mem; | 505 | goto out_rel_mem; |
463 | 506 | ||
464 | master->dev.of_node = pdev->dev.of_node; | ||
465 | status = spi_register_master(master); | 507 | status = spi_register_master(master); |
466 | if (status < 0) | 508 | if (status < 0) |
467 | goto out_rel_mem; | 509 | goto out_rel_mem; |
@@ -470,9 +512,7 @@ static int __init orion_spi_probe(struct platform_device *pdev) | |||
470 | 512 | ||
471 | out_rel_mem: | 513 | out_rel_mem: |
472 | release_mem_region(r->start, resource_size(r)); | 514 | release_mem_region(r->start, resource_size(r)); |
473 | out_rel_clk: | 515 | |
474 | clk_disable_unprepare(spi->clk); | ||
475 | clk_put(spi->clk); | ||
476 | out: | 516 | out: |
477 | spi_master_put(master); | 517 | spi_master_put(master); |
478 | return status; | 518 | return status; |
@@ -482,14 +522,13 @@ out: | |||
482 | static int __exit orion_spi_remove(struct platform_device *pdev) | 522 | static int __exit orion_spi_remove(struct platform_device *pdev) |
483 | { | 523 | { |
484 | struct spi_master *master; | 524 | struct spi_master *master; |
485 | struct resource *r; | ||
486 | struct orion_spi *spi; | 525 | struct orion_spi *spi; |
526 | struct resource *r; | ||
487 | 527 | ||
488 | master = dev_get_drvdata(&pdev->dev); | 528 | master = dev_get_drvdata(&pdev->dev); |
489 | spi = spi_master_get_devdata(master); | 529 | spi = spi_master_get_devdata(master); |
490 | 530 | ||
491 | clk_disable_unprepare(spi->clk); | 531 | cancel_work_sync(&spi->work); |
492 | clk_put(spi->clk); | ||
493 | 532 | ||
494 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 533 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
495 | release_mem_region(r->start, resource_size(r)); | 534 | release_mem_region(r->start, resource_size(r)); |
@@ -501,30 +540,31 @@ static int __exit orion_spi_remove(struct platform_device *pdev) | |||
501 | 540 | ||
502 | MODULE_ALIAS("platform:" DRIVER_NAME); | 541 | MODULE_ALIAS("platform:" DRIVER_NAME); |
503 | 542 | ||
504 | static const struct of_device_id orion_spi_of_match_table[] = { | ||
505 | { .compatible = "marvell,orion-spi", }, | ||
506 | {} | ||
507 | }; | ||
508 | MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); | ||
509 | |||
510 | static struct platform_driver orion_spi_driver = { | 543 | static struct platform_driver orion_spi_driver = { |
511 | .driver = { | 544 | .driver = { |
512 | .name = DRIVER_NAME, | 545 | .name = DRIVER_NAME, |
513 | .owner = THIS_MODULE, | 546 | .owner = THIS_MODULE, |
514 | .of_match_table = of_match_ptr(orion_spi_of_match_table), | ||
515 | }, | 547 | }, |
516 | .remove = __exit_p(orion_spi_remove), | 548 | .remove = __exit_p(orion_spi_remove), |
517 | }; | 549 | }; |
518 | 550 | ||
519 | static int __init orion_spi_init(void) | 551 | static int __init orion_spi_init(void) |
520 | { | 552 | { |
553 | orion_spi_wq = create_singlethread_workqueue( | ||
554 | orion_spi_driver.driver.name); | ||
555 | if (orion_spi_wq == NULL) | ||
556 | return -ENOMEM; | ||
557 | |||
521 | return platform_driver_probe(&orion_spi_driver, orion_spi_probe); | 558 | return platform_driver_probe(&orion_spi_driver, orion_spi_probe); |
522 | } | 559 | } |
523 | module_init(orion_spi_init); | 560 | module_init(orion_spi_init); |
524 | 561 | ||
525 | static void __exit orion_spi_exit(void) | 562 | static void __exit orion_spi_exit(void) |
526 | { | 563 | { |
564 | flush_workqueue(orion_spi_wq); | ||
527 | platform_driver_unregister(&orion_spi_driver); | 565 | platform_driver_unregister(&orion_spi_driver); |
566 | |||
567 | destroy_workqueue(orion_spi_wq); | ||
528 | } | 568 | } |
529 | module_exit(orion_spi_exit); | 569 | module_exit(orion_spi_exit); |
530 | 570 | ||
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index b0fe393c882..730b4a37b82 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. | 2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
3 | * | 3 | * |
4 | * Copyright (C) 2008-2012 ST-Ericsson AB | 4 | * Copyright (C) 2008-2009 ST-Ericsson AB |
5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. | 5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
6 | * | 6 | * |
7 | * Author: Linus Walleij <linus.walleij@stericsson.com> | 7 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
@@ -29,6 +29,7 @@ | |||
29 | #include <linux/errno.h> | 29 | #include <linux/errno.h> |
30 | #include <linux/interrupt.h> | 30 | #include <linux/interrupt.h> |
31 | #include <linux/spi/spi.h> | 31 | #include <linux/spi/spi.h> |
32 | #include <linux/workqueue.h> | ||
32 | #include <linux/delay.h> | 33 | #include <linux/delay.h> |
33 | #include <linux/clk.h> | 34 | #include <linux/clk.h> |
34 | #include <linux/err.h> | 35 | #include <linux/err.h> |
@@ -40,9 +41,6 @@ | |||
40 | #include <linux/dma-mapping.h> | 41 | #include <linux/dma-mapping.h> |
41 | #include <linux/scatterlist.h> | 42 | #include <linux/scatterlist.h> |
42 | #include <linux/pm_runtime.h> | 43 | #include <linux/pm_runtime.h> |
43 | #include <linux/gpio.h> | ||
44 | #include <linux/of_gpio.h> | ||
45 | #include <linux/pinctrl/consumer.h> | ||
46 | 44 | ||
47 | /* | 45 | /* |
48 | * This macro is used to define some register default values. | 46 | * This macro is used to define some register default values. |
@@ -115,6 +113,7 @@ | |||
115 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | 113 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) |
116 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | 114 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) |
117 | 115 | ||
116 | |||
118 | /* | 117 | /* |
119 | * SSP Control Register 0 - SSP_CR1 | 118 | * SSP Control Register 0 - SSP_CR1 |
120 | */ | 119 | */ |
@@ -284,6 +283,7 @@ | |||
284 | 283 | ||
285 | #define SPI_POLLING_TIMEOUT 1000 | 284 | #define SPI_POLLING_TIMEOUT 1000 |
286 | 285 | ||
286 | |||
287 | /* | 287 | /* |
288 | * The type of reading going on on this chip | 288 | * The type of reading going on on this chip |
289 | */ | 289 | */ |
@@ -332,21 +332,16 @@ struct vendor_data { | |||
332 | * @clk: outgoing clock "SPICLK" for the SPI bus | 332 | * @clk: outgoing clock "SPICLK" for the SPI bus |
333 | * @master: SPI framework hookup | 333 | * @master: SPI framework hookup |
334 | * @master_info: controller-specific data from machine setup | 334 | * @master_info: controller-specific data from machine setup |
335 | * @kworker: thread struct for message pump | 335 | * @workqueue: a workqueue on which any spi_message request is queued |
336 | * @kworker_task: pointer to task for message pump kworker thread | 336 | * @pump_messages: work struct for scheduling work to the workqueue |
337 | * @pump_messages: work struct for scheduling work to the message pump | ||
338 | * @queue_lock: spinlock to syncronise access to message queue | 337 | * @queue_lock: spinlock to syncronise access to message queue |
339 | * @queue: message queue | 338 | * @queue: message queue |
340 | * @busy: message pump is busy | 339 | * @busy: workqueue is busy |
341 | * @running: message pump is running | 340 | * @running: workqueue is running |
342 | * @pump_transfers: Tasklet used in Interrupt Transfer mode | 341 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
343 | * @cur_msg: Pointer to current spi_message being processed | 342 | * @cur_msg: Pointer to current spi_message being processed |
344 | * @cur_transfer: Pointer to current spi_transfer | 343 | * @cur_transfer: Pointer to current spi_transfer |
345 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | 344 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
346 | * @next_msg_cs_active: the next message in the queue has been examined | ||
347 | * and it was found that it uses the same chip select as the previous | ||
348 | * message, so we left it active after the previous transfer, and it's | ||
349 | * active already. | ||
350 | * @tx: current position in TX buffer to be read | 345 | * @tx: current position in TX buffer to be read |
351 | * @tx_end: end position in TX buffer to be read | 346 | * @tx_end: end position in TX buffer to be read |
352 | * @rx: current position in RX buffer to be written | 347 | * @rx: current position in RX buffer to be written |
@@ -359,8 +354,6 @@ struct vendor_data { | |||
359 | * @sgt_rx: scattertable for the RX transfer | 354 | * @sgt_rx: scattertable for the RX transfer |
360 | * @sgt_tx: scattertable for the TX transfer | 355 | * @sgt_tx: scattertable for the TX transfer |
361 | * @dummypage: a dummy page used for driving data on the bus with DMA | 356 | * @dummypage: a dummy page used for driving data on the bus with DMA |
362 | * @cur_cs: current chip select (gpio) | ||
363 | * @chipselects: list of chipselects (gpios) | ||
364 | */ | 357 | */ |
365 | struct pl022 { | 358 | struct pl022 { |
366 | struct amba_device *adev; | 359 | struct amba_device *adev; |
@@ -368,19 +361,20 @@ struct pl022 { | |||
368 | resource_size_t phybase; | 361 | resource_size_t phybase; |
369 | void __iomem *virtbase; | 362 | void __iomem *virtbase; |
370 | struct clk *clk; | 363 | struct clk *clk; |
371 | /* Two optional pin states - default & sleep */ | ||
372 | struct pinctrl *pinctrl; | ||
373 | struct pinctrl_state *pins_default; | ||
374 | struct pinctrl_state *pins_idle; | ||
375 | struct pinctrl_state *pins_sleep; | ||
376 | struct spi_master *master; | 364 | struct spi_master *master; |
377 | struct pl022_ssp_controller *master_info; | 365 | struct pl022_ssp_controller *master_info; |
378 | /* Message per-transfer pump */ | 366 | /* Driver message queue */ |
367 | struct workqueue_struct *workqueue; | ||
368 | struct work_struct pump_messages; | ||
369 | spinlock_t queue_lock; | ||
370 | struct list_head queue; | ||
371 | bool busy; | ||
372 | bool running; | ||
373 | /* Message transfer pump */ | ||
379 | struct tasklet_struct pump_transfers; | 374 | struct tasklet_struct pump_transfers; |
380 | struct spi_message *cur_msg; | 375 | struct spi_message *cur_msg; |
381 | struct spi_transfer *cur_transfer; | 376 | struct spi_transfer *cur_transfer; |
382 | struct chip_data *cur_chip; | 377 | struct chip_data *cur_chip; |
383 | bool next_msg_cs_active; | ||
384 | void *tx; | 378 | void *tx; |
385 | void *tx_end; | 379 | void *tx_end; |
386 | void *rx; | 380 | void *rx; |
@@ -397,10 +391,7 @@ struct pl022 { | |||
397 | struct sg_table sgt_rx; | 391 | struct sg_table sgt_rx; |
398 | struct sg_table sgt_tx; | 392 | struct sg_table sgt_tx; |
399 | char *dummypage; | 393 | char *dummypage; |
400 | bool dma_running; | ||
401 | #endif | 394 | #endif |
402 | int cur_cs; | ||
403 | int *chipselects; | ||
404 | }; | 395 | }; |
405 | 396 | ||
406 | /** | 397 | /** |
@@ -445,14 +436,6 @@ static void null_cs_control(u32 command) | |||
445 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | 436 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); |
446 | } | 437 | } |
447 | 438 | ||
448 | static void pl022_cs_control(struct pl022 *pl022, u32 command) | ||
449 | { | ||
450 | if (gpio_is_valid(pl022->cur_cs)) | ||
451 | gpio_set_value(pl022->cur_cs, command); | ||
452 | else | ||
453 | pl022->cur_chip->cs_control(command); | ||
454 | } | ||
455 | |||
456 | /** | 439 | /** |
457 | * giveback - current spi_message is over, schedule next message and call | 440 | * giveback - current spi_message is over, schedule next message and call |
458 | * callback of this message. Assumes that caller already | 441 | * callback of this message. Assumes that caller already |
@@ -462,9 +445,25 @@ static void pl022_cs_control(struct pl022 *pl022, u32 command) | |||
462 | static void giveback(struct pl022 *pl022) | 445 | static void giveback(struct pl022 *pl022) |
463 | { | 446 | { |
464 | struct spi_transfer *last_transfer; | 447 | struct spi_transfer *last_transfer; |
465 | pl022->next_msg_cs_active = false; | 448 | unsigned long flags; |
449 | struct spi_message *msg; | ||
450 | void (*curr_cs_control) (u32 command); | ||
451 | |||
452 | /* | ||
453 | * This local reference to the chip select function | ||
454 | * is needed because we set curr_chip to NULL | ||
455 | * as a step toward termininating the message. | ||
456 | */ | ||
457 | curr_cs_control = pl022->cur_chip->cs_control; | ||
458 | spin_lock_irqsave(&pl022->queue_lock, flags); | ||
459 | msg = pl022->cur_msg; | ||
460 | pl022->cur_msg = NULL; | ||
461 | pl022->cur_transfer = NULL; | ||
462 | pl022->cur_chip = NULL; | ||
463 | queue_work(pl022->workqueue, &pl022->pump_messages); | ||
464 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
466 | 465 | ||
467 | last_transfer = list_entry(pl022->cur_msg->transfers.prev, | 466 | last_transfer = list_entry(msg->transfers.prev, |
468 | struct spi_transfer, | 467 | struct spi_transfer, |
469 | transfer_list); | 468 | transfer_list); |
470 | 469 | ||
@@ -476,44 +475,50 @@ static void giveback(struct pl022 *pl022) | |||
476 | */ | 475 | */ |
477 | udelay(last_transfer->delay_usecs); | 476 | udelay(last_transfer->delay_usecs); |
478 | 477 | ||
479 | if (!last_transfer->cs_change) { | 478 | /* |
479 | * Drop chip select UNLESS cs_change is true or we are returning | ||
480 | * a message with an error, or next message is for another chip | ||
481 | */ | ||
482 | if (!last_transfer->cs_change) | ||
483 | curr_cs_control(SSP_CHIP_DESELECT); | ||
484 | else { | ||
480 | struct spi_message *next_msg; | 485 | struct spi_message *next_msg; |
481 | 486 | ||
482 | /* | 487 | /* Holding of cs was hinted, but we need to make sure |
483 | * cs_change was not set. We can keep the chip select | 488 | * the next message is for the same chip. Don't waste |
484 | * enabled if there is message in the queue and it is | 489 | * time with the following tests unless this was hinted. |
485 | * for the same spi device. | ||
486 | * | 490 | * |
487 | * We cannot postpone this until pump_messages, because | 491 | * We cannot postpone this until pump_messages, because |
488 | * after calling msg->complete (below) the driver that | 492 | * after calling msg->complete (below) the driver that |
489 | * sent the current message could be unloaded, which | 493 | * sent the current message could be unloaded, which |
490 | * could invalidate the cs_control() callback... | 494 | * could invalidate the cs_control() callback... |
491 | */ | 495 | */ |
492 | /* get a pointer to the next message, if any */ | ||
493 | next_msg = spi_get_next_queued_message(pl022->master); | ||
494 | 496 | ||
495 | /* | 497 | /* get a pointer to the next message, if any */ |
496 | * see if the next and current messages point | 498 | spin_lock_irqsave(&pl022->queue_lock, flags); |
497 | * to the same spi device. | 499 | if (list_empty(&pl022->queue)) |
498 | */ | ||
499 | if (next_msg && next_msg->spi != pl022->cur_msg->spi) | ||
500 | next_msg = NULL; | 500 | next_msg = NULL; |
501 | if (!next_msg || pl022->cur_msg->state == STATE_ERROR) | ||
502 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | ||
503 | else | 501 | else |
504 | pl022->next_msg_cs_active = true; | 502 | next_msg = list_entry(pl022->queue.next, |
503 | struct spi_message, queue); | ||
504 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
505 | 505 | ||
506 | /* see if the next and current messages point | ||
507 | * to the same chip | ||
508 | */ | ||
509 | if (next_msg && next_msg->spi != msg->spi) | ||
510 | next_msg = NULL; | ||
511 | if (!next_msg || msg->state == STATE_ERROR) | ||
512 | curr_cs_control(SSP_CHIP_DESELECT); | ||
506 | } | 513 | } |
507 | 514 | msg->state = NULL; | |
508 | pl022->cur_msg = NULL; | 515 | if (msg->complete) |
509 | pl022->cur_transfer = NULL; | 516 | msg->complete(msg->context); |
510 | pl022->cur_chip = NULL; | 517 | /* This message is completed, so let's turn off the clocks & power */ |
511 | spi_finalize_current_message(pl022->master); | 518 | clk_disable(pl022->clk); |
512 | 519 | amba_pclk_disable(pl022->adev); | |
513 | /* disable the SPI/SSP operation */ | 520 | amba_vcore_disable(pl022->adev); |
514 | writew((readw(SSP_CR1(pl022->virtbase)) & | 521 | pm_runtime_put(&pl022->adev->dev); |
515 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | ||
516 | |||
517 | } | 522 | } |
518 | 523 | ||
519 | /** | 524 | /** |
@@ -747,6 +752,7 @@ static void readwriter(struct pl022 *pl022) | |||
747 | */ | 752 | */ |
748 | } | 753 | } |
749 | 754 | ||
755 | |||
750 | /** | 756 | /** |
751 | * next_transfer - Move to the Next transfer in the current spi message | 757 | * next_transfer - Move to the Next transfer in the current spi message |
752 | * @pl022: SSP driver private data structure | 758 | * @pl022: SSP driver private data structure |
@@ -838,7 +844,8 @@ static void dma_callback(void *data) | |||
838 | /* Update total bytes transferred */ | 844 | /* Update total bytes transferred */ |
839 | msg->actual_length += pl022->cur_transfer->len; | 845 | msg->actual_length += pl022->cur_transfer->len; |
840 | if (pl022->cur_transfer->cs_change) | 846 | if (pl022->cur_transfer->cs_change) |
841 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | 847 | pl022->cur_chip-> |
848 | cs_control(SSP_CHIP_DESELECT); | ||
842 | 849 | ||
843 | /* Move to next transfer */ | 850 | /* Move to next transfer */ |
844 | msg->state = next_transfer(pl022); | 851 | msg->state = next_transfer(pl022); |
@@ -903,13 +910,11 @@ static int configure_dma(struct pl022 *pl022) | |||
903 | { | 910 | { |
904 | struct dma_slave_config rx_conf = { | 911 | struct dma_slave_config rx_conf = { |
905 | .src_addr = SSP_DR(pl022->phybase), | 912 | .src_addr = SSP_DR(pl022->phybase), |
906 | .direction = DMA_DEV_TO_MEM, | 913 | .direction = DMA_FROM_DEVICE, |
907 | .device_fc = false, | ||
908 | }; | 914 | }; |
909 | struct dma_slave_config tx_conf = { | 915 | struct dma_slave_config tx_conf = { |
910 | .dst_addr = SSP_DR(pl022->phybase), | 916 | .dst_addr = SSP_DR(pl022->phybase), |
911 | .direction = DMA_MEM_TO_DEV, | 917 | .direction = DMA_TO_DEVICE, |
912 | .device_fc = false, | ||
913 | }; | 918 | }; |
914 | unsigned int pages; | 919 | unsigned int pages; |
915 | int ret; | 920 | int ret; |
@@ -1014,14 +1019,14 @@ static int configure_dma(struct pl022 *pl022) | |||
1014 | dmaengine_slave_config(txchan, &tx_conf); | 1019 | dmaengine_slave_config(txchan, &tx_conf); |
1015 | 1020 | ||
1016 | /* Create sglists for the transfers */ | 1021 | /* Create sglists for the transfers */ |
1017 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); | 1022 | pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; |
1018 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); | 1023 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
1019 | 1024 | ||
1020 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); | 1025 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); |
1021 | if (ret) | 1026 | if (ret) |
1022 | goto err_alloc_rx_sg; | 1027 | goto err_alloc_rx_sg; |
1023 | 1028 | ||
1024 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); | 1029 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); |
1025 | if (ret) | 1030 | if (ret) |
1026 | goto err_alloc_tx_sg; | 1031 | goto err_alloc_tx_sg; |
1027 | 1032 | ||
@@ -1043,18 +1048,18 @@ static int configure_dma(struct pl022 *pl022) | |||
1043 | goto err_tx_sgmap; | 1048 | goto err_tx_sgmap; |
1044 | 1049 | ||
1045 | /* Send both scatterlists */ | 1050 | /* Send both scatterlists */ |
1046 | rxdesc = dmaengine_prep_slave_sg(rxchan, | 1051 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, |
1047 | pl022->sgt_rx.sgl, | 1052 | pl022->sgt_rx.sgl, |
1048 | rx_sglen, | 1053 | rx_sglen, |
1049 | DMA_DEV_TO_MEM, | 1054 | DMA_FROM_DEVICE, |
1050 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 1055 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1051 | if (!rxdesc) | 1056 | if (!rxdesc) |
1052 | goto err_rxdesc; | 1057 | goto err_rxdesc; |
1053 | 1058 | ||
1054 | txdesc = dmaengine_prep_slave_sg(txchan, | 1059 | txdesc = txchan->device->device_prep_slave_sg(txchan, |
1055 | pl022->sgt_tx.sgl, | 1060 | pl022->sgt_tx.sgl, |
1056 | tx_sglen, | 1061 | tx_sglen, |
1057 | DMA_MEM_TO_DEV, | 1062 | DMA_TO_DEVICE, |
1058 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 1063 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1059 | if (!txdesc) | 1064 | if (!txdesc) |
1060 | goto err_txdesc; | 1065 | goto err_txdesc; |
@@ -1068,7 +1073,6 @@ static int configure_dma(struct pl022 *pl022) | |||
1068 | dmaengine_submit(txdesc); | 1073 | dmaengine_submit(txdesc); |
1069 | dma_async_issue_pending(rxchan); | 1074 | dma_async_issue_pending(rxchan); |
1070 | dma_async_issue_pending(txchan); | 1075 | dma_async_issue_pending(txchan); |
1071 | pl022->dma_running = true; | ||
1072 | 1076 | ||
1073 | return 0; | 1077 | return 0; |
1074 | 1078 | ||
@@ -1089,7 +1093,7 @@ err_alloc_rx_sg: | |||
1089 | return -ENOMEM; | 1093 | return -ENOMEM; |
1090 | } | 1094 | } |
1091 | 1095 | ||
1092 | static int pl022_dma_probe(struct pl022 *pl022) | 1096 | static int __init pl022_dma_probe(struct pl022 *pl022) |
1093 | { | 1097 | { |
1094 | dma_cap_mask_t mask; | 1098 | dma_cap_mask_t mask; |
1095 | 1099 | ||
@@ -1147,12 +1151,11 @@ static void terminate_dma(struct pl022 *pl022) | |||
1147 | dmaengine_terminate_all(rxchan); | 1151 | dmaengine_terminate_all(rxchan); |
1148 | dmaengine_terminate_all(txchan); | 1152 | dmaengine_terminate_all(txchan); |
1149 | unmap_free_dma_scatter(pl022); | 1153 | unmap_free_dma_scatter(pl022); |
1150 | pl022->dma_running = false; | ||
1151 | } | 1154 | } |
1152 | 1155 | ||
1153 | static void pl022_dma_remove(struct pl022 *pl022) | 1156 | static void pl022_dma_remove(struct pl022 *pl022) |
1154 | { | 1157 | { |
1155 | if (pl022->dma_running) | 1158 | if (pl022->busy) |
1156 | terminate_dma(pl022); | 1159 | terminate_dma(pl022); |
1157 | if (pl022->dma_tx_channel) | 1160 | if (pl022->dma_tx_channel) |
1158 | dma_release_channel(pl022->dma_tx_channel); | 1161 | dma_release_channel(pl022->dma_tx_channel); |
@@ -1247,9 +1250,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |||
1247 | 1250 | ||
1248 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { | 1251 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { |
1249 | flag = 1; | 1252 | flag = 1; |
1250 | /* Disable Transmit interrupt, enable receive interrupt */ | 1253 | /* Disable Transmit interrupt */ |
1251 | writew((readw(SSP_IMSC(pl022->virtbase)) & | 1254 | writew(readw(SSP_IMSC(pl022->virtbase)) & |
1252 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, | 1255 | (~SSP_IMSC_MASK_TXIM), |
1253 | SSP_IMSC(pl022->virtbase)); | 1256 | SSP_IMSC(pl022->virtbase)); |
1254 | } | 1257 | } |
1255 | 1258 | ||
@@ -1271,7 +1274,8 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |||
1271 | /* Update total bytes transferred */ | 1274 | /* Update total bytes transferred */ |
1272 | msg->actual_length += pl022->cur_transfer->len; | 1275 | msg->actual_length += pl022->cur_transfer->len; |
1273 | if (pl022->cur_transfer->cs_change) | 1276 | if (pl022->cur_transfer->cs_change) |
1274 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | 1277 | pl022->cur_chip-> |
1278 | cs_control(SSP_CHIP_DESELECT); | ||
1275 | /* Move to next transfer */ | 1279 | /* Move to next transfer */ |
1276 | msg->state = next_transfer(pl022); | 1280 | msg->state = next_transfer(pl022); |
1277 | tasklet_schedule(&pl022->pump_transfers); | 1281 | tasklet_schedule(&pl022->pump_transfers); |
@@ -1354,9 +1358,9 @@ static void pump_transfers(unsigned long data) | |||
1354 | */ | 1358 | */ |
1355 | udelay(previous->delay_usecs); | 1359 | udelay(previous->delay_usecs); |
1356 | 1360 | ||
1357 | /* Reselect chip select only if cs_change was requested */ | 1361 | /* Drop chip select only if cs_change is requested */ |
1358 | if (previous->cs_change) | 1362 | if (previous->cs_change) |
1359 | pl022_cs_control(pl022, SSP_CHIP_SELECT); | 1363 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1360 | } else { | 1364 | } else { |
1361 | /* STATE_START */ | 1365 | /* STATE_START */ |
1362 | message->state = STATE_RUNNING; | 1366 | message->state = STATE_RUNNING; |
@@ -1381,22 +1385,15 @@ static void pump_transfers(unsigned long data) | |||
1381 | } | 1385 | } |
1382 | 1386 | ||
1383 | err_config_dma: | 1387 | err_config_dma: |
1384 | /* enable all interrupts except RX */ | 1388 | writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
1385 | writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); | ||
1386 | } | 1389 | } |
1387 | 1390 | ||
1388 | static void do_interrupt_dma_transfer(struct pl022 *pl022) | 1391 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
1389 | { | 1392 | { |
1390 | /* | 1393 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
1391 | * Default is to enable all interrupts except RX - | ||
1392 | * this will be enabled once TX is complete | ||
1393 | */ | ||
1394 | u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; | ||
1395 | |||
1396 | /* Enable target chip, if not already active */ | ||
1397 | if (!pl022->next_msg_cs_active) | ||
1398 | pl022_cs_control(pl022, SSP_CHIP_SELECT); | ||
1399 | 1394 | ||
1395 | /* Enable target chip */ | ||
1396 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | ||
1400 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { | 1397 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
1401 | /* Error path */ | 1398 | /* Error path */ |
1402 | pl022->cur_msg->state = STATE_ERROR; | 1399 | pl022->cur_msg->state = STATE_ERROR; |
@@ -1447,12 +1444,11 @@ static void do_polling_transfer(struct pl022 *pl022) | |||
1447 | if (previous->delay_usecs) | 1444 | if (previous->delay_usecs) |
1448 | udelay(previous->delay_usecs); | 1445 | udelay(previous->delay_usecs); |
1449 | if (previous->cs_change) | 1446 | if (previous->cs_change) |
1450 | pl022_cs_control(pl022, SSP_CHIP_SELECT); | 1447 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1451 | } else { | 1448 | } else { |
1452 | /* STATE_START */ | 1449 | /* STATE_START */ |
1453 | message->state = STATE_RUNNING; | 1450 | message->state = STATE_RUNNING; |
1454 | if (!pl022->next_msg_cs_active) | 1451 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1455 | pl022_cs_control(pl022, SSP_CHIP_SELECT); | ||
1456 | } | 1452 | } |
1457 | 1453 | ||
1458 | /* Configuration Changing Per Transfer */ | 1454 | /* Configuration Changing Per Transfer */ |
@@ -1484,7 +1480,7 @@ static void do_polling_transfer(struct pl022 *pl022) | |||
1484 | /* Update total byte transferred */ | 1480 | /* Update total byte transferred */ |
1485 | message->actual_length += pl022->cur_transfer->len; | 1481 | message->actual_length += pl022->cur_transfer->len; |
1486 | if (pl022->cur_transfer->cs_change) | 1482 | if (pl022->cur_transfer->cs_change) |
1487 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); | 1483 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); |
1488 | /* Move to next transfer */ | 1484 | /* Move to next transfer */ |
1489 | message->state = next_transfer(pl022); | 1485 | message->state = next_transfer(pl022); |
1490 | } | 1486 | } |
@@ -1499,22 +1495,59 @@ out: | |||
1499 | return; | 1495 | return; |
1500 | } | 1496 | } |
1501 | 1497 | ||
1502 | static int pl022_transfer_one_message(struct spi_master *master, | 1498 | /** |
1503 | struct spi_message *msg) | 1499 | * pump_messages - Workqueue function which processes spi message queue |
1500 | * @data: pointer to private data of SSP driver | ||
1501 | * | ||
1502 | * This function checks if there is any spi message in the queue that | ||
1503 | * needs processing and delegate control to appropriate function | ||
1504 | * do_polling_transfer()/do_interrupt_dma_transfer() | ||
1505 | * based on the kind of the transfer | ||
1506 | * | ||
1507 | */ | ||
1508 | static void pump_messages(struct work_struct *work) | ||
1504 | { | 1509 | { |
1505 | struct pl022 *pl022 = spi_master_get_devdata(master); | 1510 | struct pl022 *pl022 = |
1511 | container_of(work, struct pl022, pump_messages); | ||
1512 | unsigned long flags; | ||
1513 | |||
1514 | /* Lock queue and check for queue work */ | ||
1515 | spin_lock_irqsave(&pl022->queue_lock, flags); | ||
1516 | if (list_empty(&pl022->queue) || !pl022->running) { | ||
1517 | pl022->busy = false; | ||
1518 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1519 | return; | ||
1520 | } | ||
1521 | /* Make sure we are not already running a message */ | ||
1522 | if (pl022->cur_msg) { | ||
1523 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1524 | return; | ||
1525 | } | ||
1526 | /* Extract head of queue */ | ||
1527 | pl022->cur_msg = | ||
1528 | list_entry(pl022->queue.next, struct spi_message, queue); | ||
1506 | 1529 | ||
1507 | /* Initial message state */ | 1530 | list_del_init(&pl022->cur_msg->queue); |
1508 | pl022->cur_msg = msg; | 1531 | pl022->busy = true; |
1509 | msg->state = STATE_START; | 1532 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1510 | 1533 | ||
1511 | pl022->cur_transfer = list_entry(msg->transfers.next, | 1534 | /* Initial message state */ |
1512 | struct spi_transfer, transfer_list); | 1535 | pl022->cur_msg->state = STATE_START; |
1536 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, | ||
1537 | struct spi_transfer, | ||
1538 | transfer_list); | ||
1513 | 1539 | ||
1514 | /* Setup the SPI using the per chip configuration */ | 1540 | /* Setup the SPI using the per chip configuration */ |
1515 | pl022->cur_chip = spi_get_ctldata(msg->spi); | 1541 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); |
1516 | pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; | 1542 | /* |
1517 | 1543 | * We enable the core voltage and clocks here, then the clocks | |
1544 | * and core will be disabled when giveback() is called in each method | ||
1545 | * (poll/interrupt/DMA) | ||
1546 | */ | ||
1547 | pm_runtime_get_sync(&pl022->adev->dev); | ||
1548 | amba_vcore_enable(pl022->adev); | ||
1549 | amba_pclk_enable(pl022->adev); | ||
1550 | clk_enable(pl022->clk); | ||
1518 | restore_state(pl022); | 1551 | restore_state(pl022); |
1519 | flush(pl022); | 1552 | flush(pl022); |
1520 | 1553 | ||
@@ -1522,37 +1555,97 @@ static int pl022_transfer_one_message(struct spi_master *master, | |||
1522 | do_polling_transfer(pl022); | 1555 | do_polling_transfer(pl022); |
1523 | else | 1556 | else |
1524 | do_interrupt_dma_transfer(pl022); | 1557 | do_interrupt_dma_transfer(pl022); |
1558 | } | ||
1559 | |||
1560 | |||
1561 | static int __init init_queue(struct pl022 *pl022) | ||
1562 | { | ||
1563 | INIT_LIST_HEAD(&pl022->queue); | ||
1564 | spin_lock_init(&pl022->queue_lock); | ||
1565 | |||
1566 | pl022->running = false; | ||
1567 | pl022->busy = false; | ||
1568 | |||
1569 | tasklet_init(&pl022->pump_transfers, | ||
1570 | pump_transfers, (unsigned long)pl022); | ||
1571 | |||
1572 | INIT_WORK(&pl022->pump_messages, pump_messages); | ||
1573 | pl022->workqueue = create_singlethread_workqueue( | ||
1574 | dev_name(pl022->master->dev.parent)); | ||
1575 | if (pl022->workqueue == NULL) | ||
1576 | return -EBUSY; | ||
1525 | 1577 | ||
1526 | return 0; | 1578 | return 0; |
1527 | } | 1579 | } |
1528 | 1580 | ||
1529 | static int pl022_prepare_transfer_hardware(struct spi_master *master) | 1581 | |
1582 | static int start_queue(struct pl022 *pl022) | ||
1530 | { | 1583 | { |
1531 | struct pl022 *pl022 = spi_master_get_devdata(master); | 1584 | unsigned long flags; |
1585 | |||
1586 | spin_lock_irqsave(&pl022->queue_lock, flags); | ||
1587 | |||
1588 | if (pl022->running || pl022->busy) { | ||
1589 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1590 | return -EBUSY; | ||
1591 | } | ||
1592 | |||
1593 | pl022->running = true; | ||
1594 | pl022->cur_msg = NULL; | ||
1595 | pl022->cur_transfer = NULL; | ||
1596 | pl022->cur_chip = NULL; | ||
1597 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1598 | |||
1599 | queue_work(pl022->workqueue, &pl022->pump_messages); | ||
1532 | 1600 | ||
1533 | /* | ||
1534 | * Just make sure we have all we need to run the transfer by syncing | ||
1535 | * with the runtime PM framework. | ||
1536 | */ | ||
1537 | pm_runtime_get_sync(&pl022->adev->dev); | ||
1538 | return 0; | 1601 | return 0; |
1539 | } | 1602 | } |
1540 | 1603 | ||
1541 | static int pl022_unprepare_transfer_hardware(struct spi_master *master) | 1604 | |
1605 | static int stop_queue(struct pl022 *pl022) | ||
1542 | { | 1606 | { |
1543 | struct pl022 *pl022 = spi_master_get_devdata(master); | 1607 | unsigned long flags; |
1608 | unsigned limit = 500; | ||
1609 | int status = 0; | ||
1544 | 1610 | ||
1545 | /* nothing more to do - disable spi/ssp and power off */ | 1611 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1546 | writew((readw(SSP_CR1(pl022->virtbase)) & | ||
1547 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | ||
1548 | 1612 | ||
1549 | if (pl022->master_info->autosuspend_delay > 0) { | 1613 | /* This is a bit lame, but is optimized for the common execution path. |
1550 | pm_runtime_mark_last_busy(&pl022->adev->dev); | 1614 | * A wait_queue on the pl022->busy could be used, but then the common |
1551 | pm_runtime_put_autosuspend(&pl022->adev->dev); | 1615 | * execution path (pump_messages) would be required to call wake_up or |
1552 | } else { | 1616 | * friends on every SPI message. Do this instead */ |
1553 | pm_runtime_put(&pl022->adev->dev); | 1617 | while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { |
1618 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1619 | msleep(10); | ||
1620 | spin_lock_irqsave(&pl022->queue_lock, flags); | ||
1554 | } | 1621 | } |
1555 | 1622 | ||
1623 | if (!list_empty(&pl022->queue) || pl022->busy) | ||
1624 | status = -EBUSY; | ||
1625 | else | ||
1626 | pl022->running = false; | ||
1627 | |||
1628 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1629 | |||
1630 | return status; | ||
1631 | } | ||
1632 | |||
1633 | static int destroy_queue(struct pl022 *pl022) | ||
1634 | { | ||
1635 | int status; | ||
1636 | |||
1637 | status = stop_queue(pl022); | ||
1638 | /* we are unloading the module or failing to load (only two calls | ||
1639 | * to this routine), and neither call can handle a return value. | ||
1640 | * However, destroy_workqueue calls flush_workqueue, and that will | ||
1641 | * block until all work is done. If the reason that stop_queue | ||
1642 | * timed out is that the work will never finish, then it does no | ||
1643 | * good to call destroy_workqueue, so return anyway. */ | ||
1644 | if (status != 0) | ||
1645 | return status; | ||
1646 | |||
1647 | destroy_workqueue(pl022->workqueue); | ||
1648 | |||
1556 | return 0; | 1649 | return 0; |
1557 | } | 1650 | } |
1558 | 1651 | ||
@@ -1672,87 +1765,103 @@ static int verify_controller_parameters(struct pl022 *pl022, | |||
1672 | return 0; | 1765 | return 0; |
1673 | } | 1766 | } |
1674 | 1767 | ||
1675 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) | 1768 | /** |
1769 | * pl022_transfer - transfer function registered to SPI master framework | ||
1770 | * @spi: spi device which is requesting transfer | ||
1771 | * @msg: spi message which is to handled is queued to driver queue | ||
1772 | * | ||
1773 | * This function is registered to the SPI framework for this SPI master | ||
1774 | * controller. It will queue the spi_message in the queue of driver if | ||
1775 | * the queue is not stopped and return. | ||
1776 | */ | ||
1777 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) | ||
1676 | { | 1778 | { |
1677 | return rate / (cpsdvsr * (1 + scr)); | 1779 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
1780 | unsigned long flags; | ||
1781 | |||
1782 | spin_lock_irqsave(&pl022->queue_lock, flags); | ||
1783 | |||
1784 | if (!pl022->running) { | ||
1785 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1786 | return -ESHUTDOWN; | ||
1787 | } | ||
1788 | msg->actual_length = 0; | ||
1789 | msg->status = -EINPROGRESS; | ||
1790 | msg->state = STATE_START; | ||
1791 | |||
1792 | list_add_tail(&msg->queue, &pl022->queue); | ||
1793 | if (pl022->running && !pl022->busy) | ||
1794 | queue_work(pl022->workqueue, &pl022->pump_messages); | ||
1795 | |||
1796 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | ||
1797 | return 0; | ||
1678 | } | 1798 | } |
1679 | 1799 | ||
1680 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct | 1800 | static int calculate_effective_freq(struct pl022 *pl022, |
1681 | ssp_clock_params * clk_freq) | 1801 | int freq, |
1802 | struct ssp_clock_params *clk_freq) | ||
1682 | { | 1803 | { |
1683 | /* Lets calculate the frequency parameters */ | 1804 | /* Lets calculate the frequency parameters */ |
1684 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; | 1805 | u16 cpsdvsr = 2; |
1685 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, | 1806 | u16 scr = 0; |
1686 | best_scr = 0, tmp, found = 0; | 1807 | bool freq_found = false; |
1808 | u32 rate; | ||
1809 | u32 max_tclk; | ||
1810 | u32 min_tclk; | ||
1687 | 1811 | ||
1688 | rate = clk_get_rate(pl022->clk); | 1812 | rate = clk_get_rate(pl022->clk); |
1689 | /* cpsdvscr = 2 & scr 0 */ | 1813 | /* cpsdvscr = 2 & scr 0 */ |
1690 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); | 1814 | max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); |
1691 | /* cpsdvsr = 254 & scr = 255 */ | 1815 | /* cpsdvsr = 254 & scr = 255 */ |
1692 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); | 1816 | min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); |
1693 | 1817 | ||
1694 | if (freq > max_tclk) | 1818 | if ((freq <= max_tclk) && (freq >= min_tclk)) { |
1695 | dev_warn(&pl022->adev->dev, | 1819 | while (cpsdvsr <= CPSDVR_MAX && !freq_found) { |
1696 | "Max speed that can be programmed is %d Hz, you requested %d\n", | 1820 | while (scr <= SCR_MAX && !freq_found) { |
1697 | max_tclk, freq); | 1821 | if ((rate / |
1698 | 1822 | (cpsdvsr * (1 + scr))) > freq) | |
1699 | if (freq < min_tclk) { | 1823 | scr += 1; |
1700 | dev_err(&pl022->adev->dev, | 1824 | else { |
1701 | "Requested frequency: %d Hz is less than minimum possible %d Hz\n", | 1825 | /* |
1702 | freq, min_tclk); | 1826 | * This bool is made true when |
1703 | return -EINVAL; | 1827 | * effective frequency >= |
1704 | } | 1828 | * target frequency is found |
1705 | 1829 | */ | |
1706 | /* | 1830 | freq_found = true; |
1707 | * best_freq will give closest possible available rate (<= requested | 1831 | if ((rate / |
1708 | * freq) for all values of scr & cpsdvsr. | 1832 | (cpsdvsr * (1 + scr))) != freq) { |
1709 | */ | 1833 | if (scr == SCR_MIN) { |
1710 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { | 1834 | cpsdvsr -= 2; |
1711 | while (scr <= SCR_MAX) { | 1835 | scr = SCR_MAX; |
1712 | tmp = spi_rate(rate, cpsdvsr, scr); | 1836 | } else |
1713 | 1837 | scr -= 1; | |
1714 | if (tmp > freq) { | 1838 | } |
1715 | /* we need lower freq */ | 1839 | } |
1716 | scr++; | ||
1717 | continue; | ||
1718 | } | 1840 | } |
1719 | 1841 | if (!freq_found) { | |
1720 | /* | 1842 | cpsdvsr += 2; |
1721 | * If found exact value, mark found and break. | 1843 | scr = SCR_MIN; |
1722 | * If found more closer value, update and break. | ||
1723 | */ | ||
1724 | if (tmp > best_freq) { | ||
1725 | best_freq = tmp; | ||
1726 | best_cpsdvsr = cpsdvsr; | ||
1727 | best_scr = scr; | ||
1728 | |||
1729 | if (tmp == freq) | ||
1730 | found = 1; | ||
1731 | } | 1844 | } |
1732 | /* | ||
1733 | * increased scr will give lower rates, which are not | ||
1734 | * required | ||
1735 | */ | ||
1736 | break; | ||
1737 | } | 1845 | } |
1738 | cpsdvsr += 2; | 1846 | if (cpsdvsr != 0) { |
1739 | scr = SCR_MIN; | 1847 | dev_dbg(&pl022->adev->dev, |
1848 | "SSP Effective Frequency is %u\n", | ||
1849 | (rate / (cpsdvsr * (1 + scr)))); | ||
1850 | clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); | ||
1851 | clk_freq->scr = (u8) (scr & 0xFF); | ||
1852 | dev_dbg(&pl022->adev->dev, | ||
1853 | "SSP cpsdvsr = %d, scr = %d\n", | ||
1854 | clk_freq->cpsdvsr, clk_freq->scr); | ||
1855 | } | ||
1856 | } else { | ||
1857 | dev_err(&pl022->adev->dev, | ||
1858 | "controller data is incorrect: out of range frequency"); | ||
1859 | return -EINVAL; | ||
1740 | } | 1860 | } |
1741 | |||
1742 | WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", | ||
1743 | freq); | ||
1744 | |||
1745 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); | ||
1746 | clk_freq->scr = (u8) (best_scr & 0xFF); | ||
1747 | dev_dbg(&pl022->adev->dev, | ||
1748 | "SSP Target Frequency is: %u, Effective Frequency is %u\n", | ||
1749 | freq, best_freq); | ||
1750 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", | ||
1751 | clk_freq->cpsdvsr, clk_freq->scr); | ||
1752 | |||
1753 | return 0; | 1861 | return 0; |
1754 | } | 1862 | } |
1755 | 1863 | ||
1864 | |||
1756 | /* | 1865 | /* |
1757 | * A piece of default chip info unless the platform | 1866 | * A piece of default chip info unless the platform |
1758 | * supplies it. | 1867 | * supplies it. |
@@ -1770,6 +1879,7 @@ static const struct pl022_config_chip pl022_default_chip_info = { | |||
1770 | .cs_control = null_cs_control, | 1879 | .cs_control = null_cs_control, |
1771 | }; | 1880 | }; |
1772 | 1881 | ||
1882 | |||
1773 | /** | 1883 | /** |
1774 | * pl022_setup - setup function registered to SPI master framework | 1884 | * pl022_setup - setup function registered to SPI master framework |
1775 | * @spi: spi device which is requesting setup | 1885 | * @spi: spi device which is requesting setup |
@@ -1785,14 +1895,12 @@ static const struct pl022_config_chip pl022_default_chip_info = { | |||
1785 | static int pl022_setup(struct spi_device *spi) | 1895 | static int pl022_setup(struct spi_device *spi) |
1786 | { | 1896 | { |
1787 | struct pl022_config_chip const *chip_info; | 1897 | struct pl022_config_chip const *chip_info; |
1788 | struct pl022_config_chip chip_info_dt; | ||
1789 | struct chip_data *chip; | 1898 | struct chip_data *chip; |
1790 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; | 1899 | struct ssp_clock_params clk_freq = {0, }; |
1791 | int status = 0; | 1900 | int status = 0; |
1792 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | 1901 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
1793 | unsigned int bits = spi->bits_per_word; | 1902 | unsigned int bits = spi->bits_per_word; |
1794 | u32 tmp; | 1903 | u32 tmp; |
1795 | struct device_node *np = spi->dev.of_node; | ||
1796 | 1904 | ||
1797 | if (!spi->max_speed_hz) | 1905 | if (!spi->max_speed_hz) |
1798 | return -EINVAL; | 1906 | return -EINVAL; |
@@ -1815,32 +1923,10 @@ static int pl022_setup(struct spi_device *spi) | |||
1815 | chip_info = spi->controller_data; | 1923 | chip_info = spi->controller_data; |
1816 | 1924 | ||
1817 | if (chip_info == NULL) { | 1925 | if (chip_info == NULL) { |
1818 | if (np) { | 1926 | chip_info = &pl022_default_chip_info; |
1819 | chip_info_dt = pl022_default_chip_info; | 1927 | /* spi_board_info.controller_data not is supplied */ |
1820 | 1928 | dev_dbg(&spi->dev, | |
1821 | chip_info_dt.hierarchy = SSP_MASTER; | 1929 | "using default controller_data settings\n"); |
1822 | of_property_read_u32(np, "pl022,interface", | ||
1823 | &chip_info_dt.iface); | ||
1824 | of_property_read_u32(np, "pl022,com-mode", | ||
1825 | &chip_info_dt.com_mode); | ||
1826 | of_property_read_u32(np, "pl022,rx-level-trig", | ||
1827 | &chip_info_dt.rx_lev_trig); | ||
1828 | of_property_read_u32(np, "pl022,tx-level-trig", | ||
1829 | &chip_info_dt.tx_lev_trig); | ||
1830 | of_property_read_u32(np, "pl022,ctrl-len", | ||
1831 | &chip_info_dt.ctrl_len); | ||
1832 | of_property_read_u32(np, "pl022,wait-state", | ||
1833 | &chip_info_dt.wait_state); | ||
1834 | of_property_read_u32(np, "pl022,duplex", | ||
1835 | &chip_info_dt.duplex); | ||
1836 | |||
1837 | chip_info = &chip_info_dt; | ||
1838 | } else { | ||
1839 | chip_info = &pl022_default_chip_info; | ||
1840 | /* spi_board_info.controller_data not is supplied */ | ||
1841 | dev_dbg(&spi->dev, | ||
1842 | "using default controller_data settings\n"); | ||
1843 | } | ||
1844 | } else | 1930 | } else |
1845 | dev_dbg(&spi->dev, | 1931 | dev_dbg(&spi->dev, |
1846 | "using user supplied controller_data settings\n"); | 1932 | "using user supplied controller_data settings\n"); |
@@ -1870,6 +1956,7 @@ static int pl022_setup(struct spi_device *spi) | |||
1870 | goto err_config_params; | 1956 | goto err_config_params; |
1871 | } | 1957 | } |
1872 | 1958 | ||
1959 | |||
1873 | status = verify_controller_parameters(pl022, chip_info); | 1960 | status = verify_controller_parameters(pl022, chip_info); |
1874 | if (status) { | 1961 | if (status) { |
1875 | dev_err(&spi->dev, "controller data is incorrect"); | 1962 | dev_err(&spi->dev, "controller data is incorrect"); |
@@ -1883,18 +1970,14 @@ static int pl022_setup(struct spi_device *spi) | |||
1883 | chip->xfer_type = chip_info->com_mode; | 1970 | chip->xfer_type = chip_info->com_mode; |
1884 | if (!chip_info->cs_control) { | 1971 | if (!chip_info->cs_control) { |
1885 | chip->cs_control = null_cs_control; | 1972 | chip->cs_control = null_cs_control; |
1886 | if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) | 1973 | dev_warn(&spi->dev, |
1887 | dev_warn(&spi->dev, | 1974 | "chip select function is NULL for this chip\n"); |
1888 | "invalid chip select\n"); | ||
1889 | } else | 1975 | } else |
1890 | chip->cs_control = chip_info->cs_control; | 1976 | chip->cs_control = chip_info->cs_control; |
1891 | 1977 | ||
1892 | /* Check bits per word with vendor specific range */ | 1978 | if (bits <= 3) { |
1893 | if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { | 1979 | /* PL022 doesn't support less than 4-bits */ |
1894 | status = -ENOTSUPP; | 1980 | status = -ENOTSUPP; |
1895 | dev_err(&spi->dev, "illegal data size for this controller!\n"); | ||
1896 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", | ||
1897 | pl022->vendor->max_bpw); | ||
1898 | goto err_config_params; | 1981 | goto err_config_params; |
1899 | } else if (bits <= 8) { | 1982 | } else if (bits <= 8) { |
1900 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | 1983 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); |
@@ -1907,10 +1990,20 @@ static int pl022_setup(struct spi_device *spi) | |||
1907 | chip->read = READING_U16; | 1990 | chip->read = READING_U16; |
1908 | chip->write = WRITING_U16; | 1991 | chip->write = WRITING_U16; |
1909 | } else { | 1992 | } else { |
1910 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); | 1993 | if (pl022->vendor->max_bpw >= 32) { |
1911 | chip->n_bytes = 4; | 1994 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
1912 | chip->read = READING_U32; | 1995 | chip->n_bytes = 4; |
1913 | chip->write = WRITING_U32; | 1996 | chip->read = READING_U32; |
1997 | chip->write = WRITING_U32; | ||
1998 | } else { | ||
1999 | dev_err(&spi->dev, | ||
2000 | "illegal data size for this controller!\n"); | ||
2001 | dev_err(&spi->dev, | ||
2002 | "a standard pl022 can only handle " | ||
2003 | "1 <= n <= 16 bit words\n"); | ||
2004 | status = -ENOTSUPP; | ||
2005 | goto err_config_params; | ||
2006 | } | ||
1914 | } | 2007 | } |
1915 | 2008 | ||
1916 | /* Now Initialize all register settings required for this chip */ | 2009 | /* Now Initialize all register settings required for this chip */ |
@@ -2003,8 +2096,7 @@ static int pl022_setup(struct spi_device *spi) | |||
2003 | } | 2096 | } |
2004 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); | 2097 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
2005 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | 2098 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); |
2006 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, | 2099 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); |
2007 | 3); | ||
2008 | 2100 | ||
2009 | /* Save controller_state */ | 2101 | /* Save controller_state */ |
2010 | spi_set_ctldata(spi, chip); | 2102 | spi_set_ctldata(spi, chip); |
@@ -2030,65 +2122,30 @@ static void pl022_cleanup(struct spi_device *spi) | |||
2030 | kfree(chip); | 2122 | kfree(chip); |
2031 | } | 2123 | } |
2032 | 2124 | ||
2033 | static struct pl022_ssp_controller * | ||
2034 | pl022_platform_data_dt_get(struct device *dev) | ||
2035 | { | ||
2036 | struct device_node *np = dev->of_node; | ||
2037 | struct pl022_ssp_controller *pd; | ||
2038 | u32 tmp; | ||
2039 | |||
2040 | if (!np) { | ||
2041 | dev_err(dev, "no dt node defined\n"); | ||
2042 | return NULL; | ||
2043 | } | ||
2044 | |||
2045 | pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); | ||
2046 | if (!pd) { | ||
2047 | dev_err(dev, "cannot allocate platform data memory\n"); | ||
2048 | return NULL; | ||
2049 | } | ||
2050 | |||
2051 | pd->bus_id = -1; | ||
2052 | of_property_read_u32(np, "num-cs", &tmp); | ||
2053 | pd->num_chipselect = tmp; | ||
2054 | of_property_read_u32(np, "pl022,autosuspend-delay", | ||
2055 | &pd->autosuspend_delay); | ||
2056 | pd->rt = of_property_read_bool(np, "pl022,rt"); | ||
2057 | |||
2058 | return pd; | ||
2059 | } | ||
2060 | 2125 | ||
2061 | static int pl022_probe(struct amba_device *adev, const struct amba_id *id) | 2126 | static int __devinit |
2127 | pl022_probe(struct amba_device *adev, const struct amba_id *id) | ||
2062 | { | 2128 | { |
2063 | struct device *dev = &adev->dev; | 2129 | struct device *dev = &adev->dev; |
2064 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; | 2130 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; |
2065 | struct spi_master *master; | 2131 | struct spi_master *master; |
2066 | struct pl022 *pl022 = NULL; /*Data for this driver */ | 2132 | struct pl022 *pl022 = NULL; /*Data for this driver */ |
2067 | struct device_node *np = adev->dev.of_node; | 2133 | int status = 0; |
2068 | int status = 0, i, num_cs; | ||
2069 | 2134 | ||
2070 | dev_info(&adev->dev, | 2135 | dev_info(&adev->dev, |
2071 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | 2136 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); |
2072 | if (!platform_info && IS_ENABLED(CONFIG_OF)) | 2137 | if (platform_info == NULL) { |
2073 | platform_info = pl022_platform_data_dt_get(dev); | 2138 | dev_err(&adev->dev, "probe - no platform data supplied\n"); |
2074 | 2139 | status = -ENODEV; | |
2075 | if (!platform_info) { | 2140 | goto err_no_pdata; |
2076 | dev_err(dev, "probe: no platform data defined\n"); | ||
2077 | return -ENODEV; | ||
2078 | } | ||
2079 | |||
2080 | if (platform_info->num_chipselect) { | ||
2081 | num_cs = platform_info->num_chipselect; | ||
2082 | } else { | ||
2083 | dev_err(dev, "probe: no chip select defined\n"); | ||
2084 | return -ENODEV; | ||
2085 | } | 2141 | } |
2086 | 2142 | ||
2087 | /* Allocate master with space for data */ | 2143 | /* Allocate master with space for data */ |
2088 | master = spi_alloc_master(dev, sizeof(struct pl022)); | 2144 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
2089 | if (master == NULL) { | 2145 | if (master == NULL) { |
2090 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | 2146 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); |
2091 | return -ENOMEM; | 2147 | status = -ENOMEM; |
2148 | goto err_no_master; | ||
2092 | } | 2149 | } |
2093 | 2150 | ||
2094 | pl022 = spi_master_get_devdata(master); | 2151 | pl022 = spi_master_get_devdata(master); |
@@ -2096,76 +2153,16 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) | |||
2096 | pl022->master_info = platform_info; | 2153 | pl022->master_info = platform_info; |
2097 | pl022->adev = adev; | 2154 | pl022->adev = adev; |
2098 | pl022->vendor = id->data; | 2155 | pl022->vendor = id->data; |
2099 | pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), | ||
2100 | GFP_KERNEL); | ||
2101 | |||
2102 | pl022->pinctrl = devm_pinctrl_get(dev); | ||
2103 | if (IS_ERR(pl022->pinctrl)) { | ||
2104 | status = PTR_ERR(pl022->pinctrl); | ||
2105 | goto err_no_pinctrl; | ||
2106 | } | ||
2107 | |||
2108 | pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl, | ||
2109 | PINCTRL_STATE_DEFAULT); | ||
2110 | /* enable pins to be muxed in and configured */ | ||
2111 | if (!IS_ERR(pl022->pins_default)) { | ||
2112 | status = pinctrl_select_state(pl022->pinctrl, | ||
2113 | pl022->pins_default); | ||
2114 | if (status) | ||
2115 | dev_err(dev, "could not set default pins\n"); | ||
2116 | } else | ||
2117 | dev_err(dev, "could not get default pinstate\n"); | ||
2118 | |||
2119 | pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl, | ||
2120 | PINCTRL_STATE_IDLE); | ||
2121 | if (IS_ERR(pl022->pins_idle)) | ||
2122 | dev_dbg(dev, "could not get idle pinstate\n"); | ||
2123 | |||
2124 | pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl, | ||
2125 | PINCTRL_STATE_SLEEP); | ||
2126 | if (IS_ERR(pl022->pins_sleep)) | ||
2127 | dev_dbg(dev, "could not get sleep pinstate\n"); | ||
2128 | 2156 | ||
2129 | /* | 2157 | /* |
2130 | * Bus Number Which has been Assigned to this SSP controller | 2158 | * Bus Number Which has been Assigned to this SSP controller |
2131 | * on this board | 2159 | * on this board |
2132 | */ | 2160 | */ |
2133 | master->bus_num = platform_info->bus_id; | 2161 | master->bus_num = platform_info->bus_id; |
2134 | master->num_chipselect = num_cs; | 2162 | master->num_chipselect = platform_info->num_chipselect; |
2135 | master->cleanup = pl022_cleanup; | 2163 | master->cleanup = pl022_cleanup; |
2136 | master->setup = pl022_setup; | 2164 | master->setup = pl022_setup; |
2137 | master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; | 2165 | master->transfer = pl022_transfer; |
2138 | master->transfer_one_message = pl022_transfer_one_message; | ||
2139 | master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; | ||
2140 | master->rt = platform_info->rt; | ||
2141 | master->dev.of_node = dev->of_node; | ||
2142 | |||
2143 | if (platform_info->num_chipselect && platform_info->chipselects) { | ||
2144 | for (i = 0; i < num_cs; i++) | ||
2145 | pl022->chipselects[i] = platform_info->chipselects[i]; | ||
2146 | } else if (IS_ENABLED(CONFIG_OF)) { | ||
2147 | for (i = 0; i < num_cs; i++) { | ||
2148 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); | ||
2149 | |||
2150 | if (cs_gpio == -EPROBE_DEFER) { | ||
2151 | status = -EPROBE_DEFER; | ||
2152 | goto err_no_gpio; | ||
2153 | } | ||
2154 | |||
2155 | pl022->chipselects[i] = cs_gpio; | ||
2156 | |||
2157 | if (gpio_is_valid(cs_gpio)) { | ||
2158 | if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) | ||
2159 | dev_err(&adev->dev, | ||
2160 | "could not request %d gpio\n", | ||
2161 | cs_gpio); | ||
2162 | else if (gpio_direction_output(cs_gpio, 1)) | ||
2163 | dev_err(&adev->dev, | ||
2164 | "could set gpio %d as output\n", | ||
2165 | cs_gpio); | ||
2166 | } | ||
2167 | } | ||
2168 | } | ||
2169 | 2166 | ||
2170 | /* | 2167 | /* |
2171 | * Supports mode 0-3, loopback, and active low CS. Transfers are | 2168 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
@@ -2182,45 +2179,30 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) | |||
2182 | goto err_no_ioregion; | 2179 | goto err_no_ioregion; |
2183 | 2180 | ||
2184 | pl022->phybase = adev->res.start; | 2181 | pl022->phybase = adev->res.start; |
2185 | pl022->virtbase = devm_ioremap(dev, adev->res.start, | 2182 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2186 | resource_size(&adev->res)); | ||
2187 | if (pl022->virtbase == NULL) { | 2183 | if (pl022->virtbase == NULL) { |
2188 | status = -ENOMEM; | 2184 | status = -ENOMEM; |
2189 | goto err_no_ioremap; | 2185 | goto err_no_ioremap; |
2190 | } | 2186 | } |
2191 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", | 2187 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", |
2192 | adev->res.start, pl022->virtbase); | 2188 | adev->res.start, pl022->virtbase); |
2189 | pm_runtime_enable(dev); | ||
2190 | pm_runtime_resume(dev); | ||
2193 | 2191 | ||
2194 | pl022->clk = devm_clk_get(&adev->dev, NULL); | 2192 | pl022->clk = clk_get(&adev->dev, NULL); |
2195 | if (IS_ERR(pl022->clk)) { | 2193 | if (IS_ERR(pl022->clk)) { |
2196 | status = PTR_ERR(pl022->clk); | 2194 | status = PTR_ERR(pl022->clk); |
2197 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | 2195 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); |
2198 | goto err_no_clk; | 2196 | goto err_no_clk; |
2199 | } | 2197 | } |
2200 | 2198 | ||
2201 | status = clk_prepare(pl022->clk); | ||
2202 | if (status) { | ||
2203 | dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); | ||
2204 | goto err_clk_prep; | ||
2205 | } | ||
2206 | |||
2207 | status = clk_enable(pl022->clk); | ||
2208 | if (status) { | ||
2209 | dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); | ||
2210 | goto err_no_clk_en; | ||
2211 | } | ||
2212 | |||
2213 | /* Initialize transfer pump */ | ||
2214 | tasklet_init(&pl022->pump_transfers, pump_transfers, | ||
2215 | (unsigned long)pl022); | ||
2216 | |||
2217 | /* Disable SSP */ | 2199 | /* Disable SSP */ |
2218 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), | 2200 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2219 | SSP_CR1(pl022->virtbase)); | 2201 | SSP_CR1(pl022->virtbase)); |
2220 | load_ssp_default_config(pl022); | 2202 | load_ssp_default_config(pl022); |
2221 | 2203 | ||
2222 | status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, | 2204 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", |
2223 | 0, "pl022", pl022); | 2205 | pl022); |
2224 | if (status < 0) { | 2206 | if (status < 0) { |
2225 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | 2207 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); |
2226 | goto err_no_irq; | 2208 | goto err_no_irq; |
@@ -2233,6 +2215,17 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) | |||
2233 | platform_info->enable_dma = 0; | 2215 | platform_info->enable_dma = 0; |
2234 | } | 2216 | } |
2235 | 2217 | ||
2218 | /* Initialize and start queue */ | ||
2219 | status = init_queue(pl022); | ||
2220 | if (status != 0) { | ||
2221 | dev_err(&adev->dev, "probe - problem initializing queue\n"); | ||
2222 | goto err_init_queue; | ||
2223 | } | ||
2224 | status = start_queue(pl022); | ||
2225 | if (status != 0) { | ||
2226 | dev_err(&adev->dev, "probe - problem starting queue\n"); | ||
2227 | goto err_start_queue; | ||
2228 | } | ||
2236 | /* Register with the SPI framework */ | 2229 | /* Register with the SPI framework */ |
2237 | amba_set_drvdata(adev, pl022); | 2230 | amba_set_drvdata(adev, pl022); |
2238 | status = spi_register_master(master); | 2231 | status = spi_register_master(master); |
@@ -2242,39 +2235,35 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) | |||
2242 | goto err_spi_register; | 2235 | goto err_spi_register; |
2243 | } | 2236 | } |
2244 | dev_dbg(dev, "probe succeeded\n"); | 2237 | dev_dbg(dev, "probe succeeded\n"); |
2245 | 2238 | /* | |
2246 | /* let runtime pm put suspend */ | 2239 | * Disable the silicon block pclk and any voltage domain and just |
2247 | if (platform_info->autosuspend_delay > 0) { | 2240 | * power it up and clock it when it's needed |
2248 | dev_info(&adev->dev, | 2241 | */ |
2249 | "will use autosuspend for runtime pm, delay %dms\n", | 2242 | amba_pclk_disable(adev); |
2250 | platform_info->autosuspend_delay); | 2243 | amba_vcore_disable(adev); |
2251 | pm_runtime_set_autosuspend_delay(dev, | ||
2252 | platform_info->autosuspend_delay); | ||
2253 | pm_runtime_use_autosuspend(dev); | ||
2254 | } | ||
2255 | pm_runtime_put(dev); | ||
2256 | |||
2257 | return 0; | 2244 | return 0; |
2258 | 2245 | ||
2259 | err_spi_register: | 2246 | err_spi_register: |
2260 | if (platform_info->enable_dma) | 2247 | err_start_queue: |
2261 | pl022_dma_remove(pl022); | 2248 | err_init_queue: |
2249 | destroy_queue(pl022); | ||
2250 | pl022_dma_remove(pl022); | ||
2251 | free_irq(adev->irq[0], pl022); | ||
2252 | pm_runtime_disable(&adev->dev); | ||
2262 | err_no_irq: | 2253 | err_no_irq: |
2263 | clk_disable(pl022->clk); | 2254 | clk_put(pl022->clk); |
2264 | err_no_clk_en: | ||
2265 | clk_unprepare(pl022->clk); | ||
2266 | err_clk_prep: | ||
2267 | err_no_clk: | 2255 | err_no_clk: |
2256 | iounmap(pl022->virtbase); | ||
2268 | err_no_ioremap: | 2257 | err_no_ioremap: |
2269 | amba_release_regions(adev); | 2258 | amba_release_regions(adev); |
2270 | err_no_ioregion: | 2259 | err_no_ioregion: |
2271 | err_no_gpio: | ||
2272 | err_no_pinctrl: | ||
2273 | spi_master_put(master); | 2260 | spi_master_put(master); |
2261 | err_no_master: | ||
2262 | err_no_pdata: | ||
2274 | return status; | 2263 | return status; |
2275 | } | 2264 | } |
2276 | 2265 | ||
2277 | static int | 2266 | static int __devexit |
2278 | pl022_remove(struct amba_device *adev) | 2267 | pl022_remove(struct amba_device *adev) |
2279 | { | 2268 | { |
2280 | struct pl022 *pl022 = amba_get_drvdata(adev); | 2269 | struct pl022 *pl022 = amba_get_drvdata(adev); |
@@ -2282,137 +2271,63 @@ pl022_remove(struct amba_device *adev) | |||
2282 | if (!pl022) | 2271 | if (!pl022) |
2283 | return 0; | 2272 | return 0; |
2284 | 2273 | ||
2285 | /* | 2274 | /* Remove the queue */ |
2286 | * undo pm_runtime_put() in probe. I assume that we're not | 2275 | if (destroy_queue(pl022) != 0) |
2287 | * accessing the primecell here. | 2276 | dev_err(&adev->dev, "queue remove failed\n"); |
2288 | */ | ||
2289 | pm_runtime_get_noresume(&adev->dev); | ||
2290 | |||
2291 | load_ssp_default_config(pl022); | 2277 | load_ssp_default_config(pl022); |
2292 | if (pl022->master_info->enable_dma) | 2278 | pl022_dma_remove(pl022); |
2293 | pl022_dma_remove(pl022); | 2279 | free_irq(adev->irq[0], pl022); |
2294 | |||
2295 | clk_disable(pl022->clk); | 2280 | clk_disable(pl022->clk); |
2296 | clk_unprepare(pl022->clk); | 2281 | clk_put(pl022->clk); |
2282 | iounmap(pl022->virtbase); | ||
2297 | amba_release_regions(adev); | 2283 | amba_release_regions(adev); |
2298 | tasklet_disable(&pl022->pump_transfers); | 2284 | tasklet_disable(&pl022->pump_transfers); |
2299 | spi_unregister_master(pl022->master); | 2285 | spi_unregister_master(pl022->master); |
2286 | spi_master_put(pl022->master); | ||
2300 | amba_set_drvdata(adev, NULL); | 2287 | amba_set_drvdata(adev, NULL); |
2301 | return 0; | 2288 | return 0; |
2302 | } | 2289 | } |
2303 | 2290 | ||
2304 | #if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) | 2291 | #ifdef CONFIG_PM |
2305 | /* | 2292 | static int pl022_suspend(struct amba_device *adev, pm_message_t state) |
2306 | * These two functions are used from both suspend/resume and | ||
2307 | * the runtime counterparts to handle external resources like | ||
2308 | * clocks, pins and regulators when going to sleep. | ||
2309 | */ | ||
2310 | static void pl022_suspend_resources(struct pl022 *pl022, bool runtime) | ||
2311 | { | 2293 | { |
2312 | int ret; | 2294 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2313 | struct pinctrl_state *pins_state; | 2295 | int status = 0; |
2314 | |||
2315 | clk_disable(pl022->clk); | ||
2316 | |||
2317 | pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep; | ||
2318 | /* Optionally let pins go into sleep states */ | ||
2319 | if (!IS_ERR(pins_state)) { | ||
2320 | ret = pinctrl_select_state(pl022->pinctrl, pins_state); | ||
2321 | if (ret) | ||
2322 | dev_err(&pl022->adev->dev, "could not set %s pins\n", | ||
2323 | runtime ? "idle" : "sleep"); | ||
2324 | } | ||
2325 | } | ||
2326 | |||
2327 | static void pl022_resume_resources(struct pl022 *pl022, bool runtime) | ||
2328 | { | ||
2329 | int ret; | ||
2330 | |||
2331 | /* Optionaly enable pins to be muxed in and configured */ | ||
2332 | /* First go to the default state */ | ||
2333 | if (!IS_ERR(pl022->pins_default)) { | ||
2334 | ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default); | ||
2335 | if (ret) | ||
2336 | dev_err(&pl022->adev->dev, | ||
2337 | "could not set default pins\n"); | ||
2338 | } | ||
2339 | |||
2340 | if (!runtime) { | ||
2341 | /* Then let's idle the pins until the next transfer happens */ | ||
2342 | if (!IS_ERR(pl022->pins_idle)) { | ||
2343 | ret = pinctrl_select_state(pl022->pinctrl, | ||
2344 | pl022->pins_idle); | ||
2345 | if (ret) | ||
2346 | dev_err(&pl022->adev->dev, | ||
2347 | "could not set idle pins\n"); | ||
2348 | } | ||
2349 | } | ||
2350 | |||
2351 | clk_enable(pl022->clk); | ||
2352 | } | ||
2353 | #endif | ||
2354 | |||
2355 | #ifdef CONFIG_SUSPEND | ||
2356 | static int pl022_suspend(struct device *dev) | ||
2357 | { | ||
2358 | struct pl022 *pl022 = dev_get_drvdata(dev); | ||
2359 | int ret; | ||
2360 | 2296 | ||
2361 | ret = spi_master_suspend(pl022->master); | 2297 | status = stop_queue(pl022); |
2362 | if (ret) { | 2298 | if (status) { |
2363 | dev_warn(dev, "cannot suspend master\n"); | 2299 | dev_warn(&adev->dev, "suspend cannot stop queue\n"); |
2364 | return ret; | 2300 | return status; |
2365 | } | 2301 | } |
2366 | 2302 | ||
2367 | pm_runtime_get_sync(dev); | 2303 | amba_vcore_enable(adev); |
2368 | pl022_suspend_resources(pl022, false); | 2304 | amba_pclk_enable(adev); |
2369 | 2305 | load_ssp_default_config(pl022); | |
2370 | dev_dbg(dev, "suspended\n"); | 2306 | amba_pclk_disable(adev); |
2307 | amba_vcore_disable(adev); | ||
2308 | dev_dbg(&adev->dev, "suspended\n"); | ||
2371 | return 0; | 2309 | return 0; |
2372 | } | 2310 | } |
2373 | 2311 | ||
2374 | static int pl022_resume(struct device *dev) | 2312 | static int pl022_resume(struct amba_device *adev) |
2375 | { | 2313 | { |
2376 | struct pl022 *pl022 = dev_get_drvdata(dev); | 2314 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2377 | int ret; | 2315 | int status = 0; |
2378 | |||
2379 | pl022_resume_resources(pl022, false); | ||
2380 | pm_runtime_put(dev); | ||
2381 | 2316 | ||
2382 | /* Start the queue running */ | 2317 | /* Start the queue running */ |
2383 | ret = spi_master_resume(pl022->master); | 2318 | status = start_queue(pl022); |
2384 | if (ret) | 2319 | if (status) |
2385 | dev_err(dev, "problem starting queue (%d)\n", ret); | 2320 | dev_err(&adev->dev, "problem starting queue (%d)\n", status); |
2386 | else | 2321 | else |
2387 | dev_dbg(dev, "resumed\n"); | 2322 | dev_dbg(&adev->dev, "resumed\n"); |
2388 | 2323 | ||
2389 | return ret; | 2324 | return status; |
2390 | } | 2325 | } |
2326 | #else | ||
2327 | #define pl022_suspend NULL | ||
2328 | #define pl022_resume NULL | ||
2391 | #endif /* CONFIG_PM */ | 2329 | #endif /* CONFIG_PM */ |
2392 | 2330 | ||
2393 | #ifdef CONFIG_PM_RUNTIME | ||
2394 | static int pl022_runtime_suspend(struct device *dev) | ||
2395 | { | ||
2396 | struct pl022 *pl022 = dev_get_drvdata(dev); | ||
2397 | |||
2398 | pl022_suspend_resources(pl022, true); | ||
2399 | return 0; | ||
2400 | } | ||
2401 | |||
2402 | static int pl022_runtime_resume(struct device *dev) | ||
2403 | { | ||
2404 | struct pl022 *pl022 = dev_get_drvdata(dev); | ||
2405 | |||
2406 | pl022_resume_resources(pl022, true); | ||
2407 | return 0; | ||
2408 | } | ||
2409 | #endif | ||
2410 | |||
2411 | static const struct dev_pm_ops pl022_dev_pm_ops = { | ||
2412 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) | ||
2413 | SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) | ||
2414 | }; | ||
2415 | |||
2416 | static struct vendor_data vendor_arm = { | 2331 | static struct vendor_data vendor_arm = { |
2417 | .fifodepth = 8, | 2332 | .fifodepth = 8, |
2418 | .max_bpw = 16, | 2333 | .max_bpw = 16, |
@@ -2422,6 +2337,7 @@ static struct vendor_data vendor_arm = { | |||
2422 | .loopback = true, | 2337 | .loopback = true, |
2423 | }; | 2338 | }; |
2424 | 2339 | ||
2340 | |||
2425 | static struct vendor_data vendor_st = { | 2341 | static struct vendor_data vendor_st = { |
2426 | .fifodepth = 32, | 2342 | .fifodepth = 32, |
2427 | .max_bpw = 32, | 2343 | .max_bpw = 32, |
@@ -2440,6 +2356,15 @@ static struct vendor_data vendor_st_pl023 = { | |||
2440 | .loopback = false, | 2356 | .loopback = false, |
2441 | }; | 2357 | }; |
2442 | 2358 | ||
2359 | static struct vendor_data vendor_db5500_pl023 = { | ||
2360 | .fifodepth = 32, | ||
2361 | .max_bpw = 32, | ||
2362 | .unidir = false, | ||
2363 | .extended_cr = true, | ||
2364 | .pl023 = true, | ||
2365 | .loopback = true, | ||
2366 | }; | ||
2367 | |||
2443 | static struct amba_id pl022_ids[] = { | 2368 | static struct amba_id pl022_ids[] = { |
2444 | { | 2369 | { |
2445 | /* | 2370 | /* |
@@ -2467,35 +2392,42 @@ static struct amba_id pl022_ids[] = { | |||
2467 | * and 32 locations deep TX/RX FIFO but no extended | 2392 | * and 32 locations deep TX/RX FIFO but no extended |
2468 | * CR0/CR1 register | 2393 | * CR0/CR1 register |
2469 | */ | 2394 | */ |
2470 | .id = 0x00080023, | 2395 | .id = 0x00080023, |
2396 | .mask = 0xffffffff, | ||
2397 | .data = &vendor_st_pl023, | ||
2398 | }, | ||
2399 | { | ||
2400 | .id = 0x10080023, | ||
2471 | .mask = 0xffffffff, | 2401 | .mask = 0xffffffff, |
2472 | .data = &vendor_st_pl023, | 2402 | .data = &vendor_db5500_pl023, |
2473 | }, | 2403 | }, |
2474 | { 0, 0 }, | 2404 | { 0, 0 }, |
2475 | }; | 2405 | }; |
2476 | 2406 | ||
2477 | MODULE_DEVICE_TABLE(amba, pl022_ids); | ||
2478 | |||
2479 | static struct amba_driver pl022_driver = { | 2407 | static struct amba_driver pl022_driver = { |
2480 | .drv = { | 2408 | .drv = { |
2481 | .name = "ssp-pl022", | 2409 | .name = "ssp-pl022", |
2482 | .pm = &pl022_dev_pm_ops, | ||
2483 | }, | 2410 | }, |
2484 | .id_table = pl022_ids, | 2411 | .id_table = pl022_ids, |
2485 | .probe = pl022_probe, | 2412 | .probe = pl022_probe, |
2486 | .remove = pl022_remove, | 2413 | .remove = __devexit_p(pl022_remove), |
2414 | .suspend = pl022_suspend, | ||
2415 | .resume = pl022_resume, | ||
2487 | }; | 2416 | }; |
2488 | 2417 | ||
2418 | |||
2489 | static int __init pl022_init(void) | 2419 | static int __init pl022_init(void) |
2490 | { | 2420 | { |
2491 | return amba_driver_register(&pl022_driver); | 2421 | return amba_driver_register(&pl022_driver); |
2492 | } | 2422 | } |
2423 | |||
2493 | subsys_initcall(pl022_init); | 2424 | subsys_initcall(pl022_init); |
2494 | 2425 | ||
2495 | static void __exit pl022_exit(void) | 2426 | static void __exit pl022_exit(void) |
2496 | { | 2427 | { |
2497 | amba_driver_unregister(&pl022_driver); | 2428 | amba_driver_unregister(&pl022_driver); |
2498 | } | 2429 | } |
2430 | |||
2499 | module_exit(pl022_exit); | 2431 | module_exit(pl022_exit); |
2500 | 2432 | ||
2501 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | 2433 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c index 7a85f22b647..b267fd901e5 100644 --- a/drivers/spi/spi-ppc4xx.c +++ b/drivers/spi/spi-ppc4xx.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <linux/errno.h> | 30 | #include <linux/errno.h> |
31 | #include <linux/wait.h> | 31 | #include <linux/wait.h> |
32 | #include <linux/of_platform.h> | 32 | #include <linux/of_platform.h> |
33 | #include <linux/of_spi.h> | ||
33 | #include <linux/of_gpio.h> | 34 | #include <linux/of_gpio.h> |
34 | #include <linux/interrupt.h> | 35 | #include <linux/interrupt.h> |
35 | #include <linux/delay.h> | 36 | #include <linux/delay.h> |
@@ -101,7 +102,7 @@ struct spi_ppc4xx_regs { | |||
101 | u8 dummy; | 102 | u8 dummy; |
102 | /* | 103 | /* |
103 | * Clock divisor modulus register | 104 | * Clock divisor modulus register |
104 | * This uses the following formula: | 105 | * This uses the follwing formula: |
105 | * SCPClkOut = OPBCLK/(4(CDM + 1)) | 106 | * SCPClkOut = OPBCLK/(4(CDM + 1)) |
106 | * or | 107 | * or |
107 | * CDM = (OPBCLK/4*SCPClkOut) - 1 | 108 | * CDM = (OPBCLK/4*SCPClkOut) - 1 |
@@ -201,7 +202,7 @@ static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |||
201 | return -EINVAL; | 202 | return -EINVAL; |
202 | } | 203 | } |
203 | 204 | ||
204 | /* Write new configuration */ | 205 | /* Write new configration */ |
205 | out_8(&hw->regs->mode, cs->mode); | 206 | out_8(&hw->regs->mode, cs->mode); |
206 | 207 | ||
207 | /* Set the clock */ | 208 | /* Set the clock */ |
@@ -466,6 +467,9 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op) | |||
466 | bbp->master->setup = spi_ppc4xx_setup; | 467 | bbp->master->setup = spi_ppc4xx_setup; |
467 | bbp->master->cleanup = spi_ppc4xx_cleanup; | 468 | bbp->master->cleanup = spi_ppc4xx_cleanup; |
468 | 469 | ||
470 | /* Allocate bus num dynamically. */ | ||
471 | bbp->master->bus_num = -1; | ||
472 | |||
469 | /* the spi->mode bits understood by this driver: */ | 473 | /* the spi->mode bits understood by this driver: */ |
470 | bbp->master->mode_bits = | 474 | bbp->master->mode_bits = |
471 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; | 475 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; |
@@ -510,7 +514,7 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op) | |||
510 | /* Request IRQ */ | 514 | /* Request IRQ */ |
511 | hw->irqnum = irq_of_parse_and_map(np, 0); | 515 | hw->irqnum = irq_of_parse_and_map(np, 0); |
512 | ret = request_irq(hw->irqnum, spi_ppc4xx_int, | 516 | ret = request_irq(hw->irqnum, spi_ppc4xx_int, |
513 | 0, "spi_ppc4xx_of", (void *)hw); | 517 | IRQF_DISABLED, "spi_ppc4xx_of", (void *)hw); |
514 | if (ret) { | 518 | if (ret) { |
515 | dev_err(dev, "unable to allocate interrupt\n"); | 519 | dev_err(dev, "unable to allocate interrupt\n"); |
516 | goto free_gpios; | 520 | goto free_gpios; |
@@ -590,7 +594,18 @@ static struct platform_driver spi_ppc4xx_of_driver = { | |||
590 | .of_match_table = spi_ppc4xx_of_match, | 594 | .of_match_table = spi_ppc4xx_of_match, |
591 | }, | 595 | }, |
592 | }; | 596 | }; |
593 | module_platform_driver(spi_ppc4xx_of_driver); | 597 | |
598 | static int __init spi_ppc4xx_init(void) | ||
599 | { | ||
600 | return platform_driver_register(&spi_ppc4xx_of_driver); | ||
601 | } | ||
602 | module_init(spi_ppc4xx_init); | ||
603 | |||
604 | static void __exit spi_ppc4xx_exit(void) | ||
605 | { | ||
606 | platform_driver_unregister(&spi_ppc4xx_of_driver); | ||
607 | } | ||
608 | module_exit(spi_ppc4xx_exit); | ||
594 | 609 | ||
595 | MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); | 610 | MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); |
596 | MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); | 611 | MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); |
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index cf95587eefd..378e504f89e 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c | |||
@@ -5,7 +5,6 @@ | |||
5 | #include <linux/pci.h> | 5 | #include <linux/pci.h> |
6 | #include <linux/platform_device.h> | 6 | #include <linux/platform_device.h> |
7 | #include <linux/of_device.h> | 7 | #include <linux/of_device.h> |
8 | #include <linux/module.h> | ||
9 | #include <linux/spi/pxa2xx_spi.h> | 8 | #include <linux/spi/pxa2xx_spi.h> |
10 | 9 | ||
11 | struct ce4100_info { | 10 | struct ce4100_info { |
@@ -51,7 +50,7 @@ void pxa_ssp_free(struct ssp_device *ssp) | |||
51 | } | 50 | } |
52 | EXPORT_SYMBOL_GPL(pxa_ssp_free); | 51 | EXPORT_SYMBOL_GPL(pxa_ssp_free); |
53 | 52 | ||
54 | static int ce4100_spi_probe(struct pci_dev *dev, | 53 | static int __devinit ce4100_spi_probe(struct pci_dev *dev, |
55 | const struct pci_device_id *ent) | 54 | const struct pci_device_id *ent) |
56 | { | 55 | { |
57 | int ret; | 56 | int ret; |
@@ -129,7 +128,7 @@ err_nomem: | |||
129 | return ret; | 128 | return ret; |
130 | } | 129 | } |
131 | 130 | ||
132 | static void ce4100_spi_remove(struct pci_dev *dev) | 131 | static void __devexit ce4100_spi_remove(struct pci_dev *dev) |
133 | { | 132 | { |
134 | struct ce4100_info *spi_info; | 133 | struct ce4100_info *spi_info; |
135 | struct ssp_device *ssp; | 134 | struct ssp_device *ssp; |
@@ -151,7 +150,7 @@ static void ce4100_spi_remove(struct pci_dev *dev) | |||
151 | kfree(spi_info); | 150 | kfree(spi_info); |
152 | } | 151 | } |
153 | 152 | ||
154 | static DEFINE_PCI_DEVICE_TABLE(ce4100_spi_devices) = { | 153 | static struct pci_device_id ce4100_spi_devices[] __devinitdata = { |
155 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) }, | 154 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) }, |
156 | { }, | 155 | { }, |
157 | }; | 156 | }; |
@@ -161,10 +160,20 @@ static struct pci_driver ce4100_spi_driver = { | |||
161 | .name = "ce4100_spi", | 160 | .name = "ce4100_spi", |
162 | .id_table = ce4100_spi_devices, | 161 | .id_table = ce4100_spi_devices, |
163 | .probe = ce4100_spi_probe, | 162 | .probe = ce4100_spi_probe, |
164 | .remove = ce4100_spi_remove, | 163 | .remove = __devexit_p(ce4100_spi_remove), |
165 | }; | 164 | }; |
166 | 165 | ||
167 | module_pci_driver(ce4100_spi_driver); | 166 | static int __init ce4100_spi_init(void) |
167 | { | ||
168 | return pci_register_driver(&ce4100_spi_driver); | ||
169 | } | ||
170 | module_init(ce4100_spi_init); | ||
171 | |||
172 | static void __exit ce4100_spi_exit(void) | ||
173 | { | ||
174 | pci_unregister_driver(&ce4100_spi_driver); | ||
175 | } | ||
176 | module_exit(ce4100_spi_exit); | ||
168 | 177 | ||
169 | MODULE_DESCRIPTION("CE4100 PCI-SPI glue code for PXA's driver"); | 178 | MODULE_DESCRIPTION("CE4100 PCI-SPI glue code for PXA's driver"); |
170 | MODULE_LICENSE("GPL v2"); | 179 | MODULE_LICENSE("GPL v2"); |
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 5c8c4f5883c..dc25bee8d33 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c | |||
@@ -1438,7 +1438,7 @@ static void cleanup(struct spi_device *spi) | |||
1438 | kfree(chip); | 1438 | kfree(chip); |
1439 | } | 1439 | } |
1440 | 1440 | ||
1441 | static int init_queue(struct driver_data *drv_data) | 1441 | static int __devinit init_queue(struct driver_data *drv_data) |
1442 | { | 1442 | { |
1443 | INIT_LIST_HEAD(&drv_data->queue); | 1443 | INIT_LIST_HEAD(&drv_data->queue); |
1444 | spin_lock_init(&drv_data->lock); | 1444 | spin_lock_init(&drv_data->lock); |
@@ -1526,7 +1526,7 @@ static int destroy_queue(struct driver_data *drv_data) | |||
1526 | return 0; | 1526 | return 0; |
1527 | } | 1527 | } |
1528 | 1528 | ||
1529 | static int pxa2xx_spi_probe(struct platform_device *pdev) | 1529 | static int __devinit pxa2xx_spi_probe(struct platform_device *pdev) |
1530 | { | 1530 | { |
1531 | struct device *dev = &pdev->dev; | 1531 | struct device *dev = &pdev->dev; |
1532 | struct pxa2xx_spi_master *platform_info; | 1532 | struct pxa2xx_spi_master *platform_info; |
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c deleted file mode 100644 index 902f2fb902d..00000000000 --- a/drivers/spi/spi-rspi.c +++ /dev/null | |||
@@ -1,841 +0,0 @@ | |||
1 | /* | ||
2 | * SH RSPI driver | ||
3 | * | ||
4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
5 | * | ||
6 | * Based on spi-sh.c: | ||
7 | * Copyright (C) 2011 Renesas Solutions Corp. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; version 2 of the License. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #include <linux/module.h> | ||
25 | #include <linux/kernel.h> | ||
26 | #include <linux/sched.h> | ||
27 | #include <linux/errno.h> | ||
28 | #include <linux/list.h> | ||
29 | #include <linux/workqueue.h> | ||
30 | #include <linux/interrupt.h> | ||
31 | #include <linux/platform_device.h> | ||
32 | #include <linux/io.h> | ||
33 | #include <linux/clk.h> | ||
34 | #include <linux/dmaengine.h> | ||
35 | #include <linux/dma-mapping.h> | ||
36 | #include <linux/sh_dma.h> | ||
37 | #include <linux/spi/spi.h> | ||
38 | #include <linux/spi/rspi.h> | ||
39 | |||
40 | #define RSPI_SPCR 0x00 | ||
41 | #define RSPI_SSLP 0x01 | ||
42 | #define RSPI_SPPCR 0x02 | ||
43 | #define RSPI_SPSR 0x03 | ||
44 | #define RSPI_SPDR 0x04 | ||
45 | #define RSPI_SPSCR 0x08 | ||
46 | #define RSPI_SPSSR 0x09 | ||
47 | #define RSPI_SPBR 0x0a | ||
48 | #define RSPI_SPDCR 0x0b | ||
49 | #define RSPI_SPCKD 0x0c | ||
50 | #define RSPI_SSLND 0x0d | ||
51 | #define RSPI_SPND 0x0e | ||
52 | #define RSPI_SPCR2 0x0f | ||
53 | #define RSPI_SPCMD0 0x10 | ||
54 | #define RSPI_SPCMD1 0x12 | ||
55 | #define RSPI_SPCMD2 0x14 | ||
56 | #define RSPI_SPCMD3 0x16 | ||
57 | #define RSPI_SPCMD4 0x18 | ||
58 | #define RSPI_SPCMD5 0x1a | ||
59 | #define RSPI_SPCMD6 0x1c | ||
60 | #define RSPI_SPCMD7 0x1e | ||
61 | |||
62 | /* SPCR */ | ||
63 | #define SPCR_SPRIE 0x80 | ||
64 | #define SPCR_SPE 0x40 | ||
65 | #define SPCR_SPTIE 0x20 | ||
66 | #define SPCR_SPEIE 0x10 | ||
67 | #define SPCR_MSTR 0x08 | ||
68 | #define SPCR_MODFEN 0x04 | ||
69 | #define SPCR_TXMD 0x02 | ||
70 | #define SPCR_SPMS 0x01 | ||
71 | |||
72 | /* SSLP */ | ||
73 | #define SSLP_SSL1P 0x02 | ||
74 | #define SSLP_SSL0P 0x01 | ||
75 | |||
76 | /* SPPCR */ | ||
77 | #define SPPCR_MOIFE 0x20 | ||
78 | #define SPPCR_MOIFV 0x10 | ||
79 | #define SPPCR_SPOM 0x04 | ||
80 | #define SPPCR_SPLP2 0x02 | ||
81 | #define SPPCR_SPLP 0x01 | ||
82 | |||
83 | /* SPSR */ | ||
84 | #define SPSR_SPRF 0x80 | ||
85 | #define SPSR_SPTEF 0x20 | ||
86 | #define SPSR_PERF 0x08 | ||
87 | #define SPSR_MODF 0x04 | ||
88 | #define SPSR_IDLNF 0x02 | ||
89 | #define SPSR_OVRF 0x01 | ||
90 | |||
91 | /* SPSCR */ | ||
92 | #define SPSCR_SPSLN_MASK 0x07 | ||
93 | |||
94 | /* SPSSR */ | ||
95 | #define SPSSR_SPECM_MASK 0x70 | ||
96 | #define SPSSR_SPCP_MASK 0x07 | ||
97 | |||
98 | /* SPDCR */ | ||
99 | #define SPDCR_SPLW 0x20 | ||
100 | #define SPDCR_SPRDTD 0x10 | ||
101 | #define SPDCR_SLSEL1 0x08 | ||
102 | #define SPDCR_SLSEL0 0x04 | ||
103 | #define SPDCR_SLSEL_MASK 0x0c | ||
104 | #define SPDCR_SPFC1 0x02 | ||
105 | #define SPDCR_SPFC0 0x01 | ||
106 | |||
107 | /* SPCKD */ | ||
108 | #define SPCKD_SCKDL_MASK 0x07 | ||
109 | |||
110 | /* SSLND */ | ||
111 | #define SSLND_SLNDL_MASK 0x07 | ||
112 | |||
113 | /* SPND */ | ||
114 | #define SPND_SPNDL_MASK 0x07 | ||
115 | |||
116 | /* SPCR2 */ | ||
117 | #define SPCR2_PTE 0x08 | ||
118 | #define SPCR2_SPIE 0x04 | ||
119 | #define SPCR2_SPOE 0x02 | ||
120 | #define SPCR2_SPPE 0x01 | ||
121 | |||
122 | /* SPCMDn */ | ||
123 | #define SPCMD_SCKDEN 0x8000 | ||
124 | #define SPCMD_SLNDEN 0x4000 | ||
125 | #define SPCMD_SPNDEN 0x2000 | ||
126 | #define SPCMD_LSBF 0x1000 | ||
127 | #define SPCMD_SPB_MASK 0x0f00 | ||
128 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) | ||
129 | #define SPCMD_SPB_20BIT 0x0000 | ||
130 | #define SPCMD_SPB_24BIT 0x0100 | ||
131 | #define SPCMD_SPB_32BIT 0x0200 | ||
132 | #define SPCMD_SSLKP 0x0080 | ||
133 | #define SPCMD_SSLA_MASK 0x0030 | ||
134 | #define SPCMD_BRDV_MASK 0x000c | ||
135 | #define SPCMD_CPOL 0x0002 | ||
136 | #define SPCMD_CPHA 0x0001 | ||
137 | |||
138 | struct rspi_data { | ||
139 | void __iomem *addr; | ||
140 | u32 max_speed_hz; | ||
141 | struct spi_master *master; | ||
142 | struct list_head queue; | ||
143 | struct work_struct ws; | ||
144 | wait_queue_head_t wait; | ||
145 | spinlock_t lock; | ||
146 | struct clk *clk; | ||
147 | unsigned char spsr; | ||
148 | |||
149 | /* for dmaengine */ | ||
150 | struct dma_chan *chan_tx; | ||
151 | struct dma_chan *chan_rx; | ||
152 | int irq; | ||
153 | |||
154 | unsigned dma_width_16bit:1; | ||
155 | unsigned dma_callbacked:1; | ||
156 | }; | ||
157 | |||
158 | static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset) | ||
159 | { | ||
160 | iowrite8(data, rspi->addr + offset); | ||
161 | } | ||
162 | |||
163 | static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset) | ||
164 | { | ||
165 | iowrite16(data, rspi->addr + offset); | ||
166 | } | ||
167 | |||
168 | static u8 rspi_read8(struct rspi_data *rspi, u16 offset) | ||
169 | { | ||
170 | return ioread8(rspi->addr + offset); | ||
171 | } | ||
172 | |||
173 | static u16 rspi_read16(struct rspi_data *rspi, u16 offset) | ||
174 | { | ||
175 | return ioread16(rspi->addr + offset); | ||
176 | } | ||
177 | |||
178 | static unsigned char rspi_calc_spbr(struct rspi_data *rspi) | ||
179 | { | ||
180 | int tmp; | ||
181 | unsigned char spbr; | ||
182 | |||
183 | tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | ||
184 | spbr = clamp(tmp, 0, 255); | ||
185 | |||
186 | return spbr; | ||
187 | } | ||
188 | |||
189 | static void rspi_enable_irq(struct rspi_data *rspi, u8 enable) | ||
190 | { | ||
191 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | ||
192 | } | ||
193 | |||
194 | static void rspi_disable_irq(struct rspi_data *rspi, u8 disable) | ||
195 | { | ||
196 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | ||
197 | } | ||
198 | |||
199 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | ||
200 | u8 enable_bit) | ||
201 | { | ||
202 | int ret; | ||
203 | |||
204 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | ||
205 | rspi_enable_irq(rspi, enable_bit); | ||
206 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | ||
207 | if (ret == 0 && !(rspi->spsr & wait_mask)) | ||
208 | return -ETIMEDOUT; | ||
209 | |||
210 | return 0; | ||
211 | } | ||
212 | |||
213 | static void rspi_assert_ssl(struct rspi_data *rspi) | ||
214 | { | ||
215 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); | ||
216 | } | ||
217 | |||
218 | static void rspi_negate_ssl(struct rspi_data *rspi) | ||
219 | { | ||
220 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); | ||
221 | } | ||
222 | |||
223 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) | ||
224 | { | ||
225 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ | ||
226 | rspi_write8(rspi, 0x00, RSPI_SPPCR); | ||
227 | |||
228 | /* Sets transfer bit rate */ | ||
229 | rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR); | ||
230 | |||
231 | /* Sets number of frames to be used: 1 frame */ | ||
232 | rspi_write8(rspi, 0x00, RSPI_SPDCR); | ||
233 | |||
234 | /* Sets RSPCK, SSL, next-access delay value */ | ||
235 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | ||
236 | rspi_write8(rspi, 0x00, RSPI_SSLND); | ||
237 | rspi_write8(rspi, 0x00, RSPI_SPND); | ||
238 | |||
239 | /* Sets parity, interrupt mask */ | ||
240 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | ||
241 | |||
242 | /* Sets SPCMD */ | ||
243 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, | ||
244 | RSPI_SPCMD0); | ||
245 | |||
246 | /* Sets RSPI mode */ | ||
247 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | ||
248 | |||
249 | return 0; | ||
250 | } | ||
251 | |||
252 | static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, | ||
253 | struct spi_transfer *t) | ||
254 | { | ||
255 | int remain = t->len; | ||
256 | u8 *data; | ||
257 | |||
258 | data = (u8 *)t->tx_buf; | ||
259 | while (remain > 0) { | ||
260 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, | ||
261 | RSPI_SPCR); | ||
262 | |||
263 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | ||
264 | dev_err(&rspi->master->dev, | ||
265 | "%s: tx empty timeout\n", __func__); | ||
266 | return -ETIMEDOUT; | ||
267 | } | ||
268 | |||
269 | rspi_write16(rspi, *data, RSPI_SPDR); | ||
270 | data++; | ||
271 | remain--; | ||
272 | } | ||
273 | |||
274 | /* Waiting for the last transmition */ | ||
275 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | ||
276 | |||
277 | return 0; | ||
278 | } | ||
279 | |||
280 | static void rspi_dma_complete(void *arg) | ||
281 | { | ||
282 | struct rspi_data *rspi = arg; | ||
283 | |||
284 | rspi->dma_callbacked = 1; | ||
285 | wake_up_interruptible(&rspi->wait); | ||
286 | } | ||
287 | |||
288 | static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len, | ||
289 | struct dma_chan *chan, | ||
290 | enum dma_transfer_direction dir) | ||
291 | { | ||
292 | sg_init_table(sg, 1); | ||
293 | sg_set_buf(sg, buf, len); | ||
294 | sg_dma_len(sg) = len; | ||
295 | return dma_map_sg(chan->device->dev, sg, 1, dir); | ||
296 | } | ||
297 | |||
298 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | ||
299 | enum dma_transfer_direction dir) | ||
300 | { | ||
301 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | ||
302 | } | ||
303 | |||
304 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | ||
305 | { | ||
306 | u16 *dst = buf; | ||
307 | const u8 *src = data; | ||
308 | |||
309 | while (len) { | ||
310 | *dst++ = (u16)(*src++); | ||
311 | len--; | ||
312 | } | ||
313 | } | ||
314 | |||
315 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | ||
316 | { | ||
317 | u8 *dst = buf; | ||
318 | const u16 *src = data; | ||
319 | |||
320 | while (len) { | ||
321 | *dst++ = (u8)*src++; | ||
322 | len--; | ||
323 | } | ||
324 | } | ||
325 | |||
326 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | ||
327 | { | ||
328 | struct scatterlist sg; | ||
329 | void *buf = NULL; | ||
330 | struct dma_async_tx_descriptor *desc; | ||
331 | unsigned len; | ||
332 | int ret = 0; | ||
333 | |||
334 | if (rspi->dma_width_16bit) { | ||
335 | /* | ||
336 | * If DMAC bus width is 16-bit, the driver allocates a dummy | ||
337 | * buffer. And, the driver converts original data into the | ||
338 | * DMAC data as the following format: | ||
339 | * original data: 1st byte, 2nd byte ... | ||
340 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | ||
341 | */ | ||
342 | len = t->len * 2; | ||
343 | buf = kmalloc(len, GFP_KERNEL); | ||
344 | if (!buf) | ||
345 | return -ENOMEM; | ||
346 | rspi_memory_to_8bit(buf, t->tx_buf, t->len); | ||
347 | } else { | ||
348 | len = t->len; | ||
349 | buf = (void *)t->tx_buf; | ||
350 | } | ||
351 | |||
352 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | ||
353 | ret = -EFAULT; | ||
354 | goto end_nomap; | ||
355 | } | ||
356 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | ||
357 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
358 | if (!desc) { | ||
359 | ret = -EIO; | ||
360 | goto end; | ||
361 | } | ||
362 | |||
363 | /* | ||
364 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | ||
365 | * called. So, this driver disables the IRQ while DMA transfer. | ||
366 | */ | ||
367 | disable_irq(rspi->irq); | ||
368 | |||
369 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | ||
370 | rspi_enable_irq(rspi, SPCR_SPTIE); | ||
371 | rspi->dma_callbacked = 0; | ||
372 | |||
373 | desc->callback = rspi_dma_complete; | ||
374 | desc->callback_param = rspi; | ||
375 | dmaengine_submit(desc); | ||
376 | dma_async_issue_pending(rspi->chan_tx); | ||
377 | |||
378 | ret = wait_event_interruptible_timeout(rspi->wait, | ||
379 | rspi->dma_callbacked, HZ); | ||
380 | if (ret > 0 && rspi->dma_callbacked) | ||
381 | ret = 0; | ||
382 | else if (!ret) | ||
383 | ret = -ETIMEDOUT; | ||
384 | rspi_disable_irq(rspi, SPCR_SPTIE); | ||
385 | |||
386 | enable_irq(rspi->irq); | ||
387 | |||
388 | end: | ||
389 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | ||
390 | end_nomap: | ||
391 | if (rspi->dma_width_16bit) | ||
392 | kfree(buf); | ||
393 | |||
394 | return ret; | ||
395 | } | ||
396 | |||
397 | static void rspi_receive_init(struct rspi_data *rspi) | ||
398 | { | ||
399 | unsigned char spsr; | ||
400 | |||
401 | spsr = rspi_read8(rspi, RSPI_SPSR); | ||
402 | if (spsr & SPSR_SPRF) | ||
403 | rspi_read16(rspi, RSPI_SPDR); /* dummy read */ | ||
404 | if (spsr & SPSR_OVRF) | ||
405 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | ||
406 | RSPI_SPCR); | ||
407 | } | ||
408 | |||
409 | static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, | ||
410 | struct spi_transfer *t) | ||
411 | { | ||
412 | int remain = t->len; | ||
413 | u8 *data; | ||
414 | |||
415 | rspi_receive_init(rspi); | ||
416 | |||
417 | data = (u8 *)t->rx_buf; | ||
418 | while (remain > 0) { | ||
419 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, | ||
420 | RSPI_SPCR); | ||
421 | |||
422 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | ||
423 | dev_err(&rspi->master->dev, | ||
424 | "%s: tx empty timeout\n", __func__); | ||
425 | return -ETIMEDOUT; | ||
426 | } | ||
427 | /* dummy write for generate clock */ | ||
428 | rspi_write16(rspi, 0x00, RSPI_SPDR); | ||
429 | |||
430 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | ||
431 | dev_err(&rspi->master->dev, | ||
432 | "%s: receive timeout\n", __func__); | ||
433 | return -ETIMEDOUT; | ||
434 | } | ||
435 | /* SPDR allows 16 or 32-bit access only */ | ||
436 | *data = (u8)rspi_read16(rspi, RSPI_SPDR); | ||
437 | |||
438 | data++; | ||
439 | remain--; | ||
440 | } | ||
441 | |||
442 | return 0; | ||
443 | } | ||
444 | |||
445 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) | ||
446 | { | ||
447 | struct scatterlist sg, sg_dummy; | ||
448 | void *dummy = NULL, *rx_buf = NULL; | ||
449 | struct dma_async_tx_descriptor *desc, *desc_dummy; | ||
450 | unsigned len; | ||
451 | int ret = 0; | ||
452 | |||
453 | if (rspi->dma_width_16bit) { | ||
454 | /* | ||
455 | * If DMAC bus width is 16-bit, the driver allocates a dummy | ||
456 | * buffer. And, finally the driver converts the DMAC data into | ||
457 | * actual data as the following format: | ||
458 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | ||
459 | * actual data: 1st byte, 2nd byte ... | ||
460 | */ | ||
461 | len = t->len * 2; | ||
462 | rx_buf = kmalloc(len, GFP_KERNEL); | ||
463 | if (!rx_buf) | ||
464 | return -ENOMEM; | ||
465 | } else { | ||
466 | len = t->len; | ||
467 | rx_buf = t->rx_buf; | ||
468 | } | ||
469 | |||
470 | /* prepare dummy transfer to generate SPI clocks */ | ||
471 | dummy = kzalloc(len, GFP_KERNEL); | ||
472 | if (!dummy) { | ||
473 | ret = -ENOMEM; | ||
474 | goto end_nomap; | ||
475 | } | ||
476 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | ||
477 | DMA_TO_DEVICE)) { | ||
478 | ret = -EFAULT; | ||
479 | goto end_nomap; | ||
480 | } | ||
481 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | ||
482 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
483 | if (!desc_dummy) { | ||
484 | ret = -EIO; | ||
485 | goto end_dummy_mapped; | ||
486 | } | ||
487 | |||
488 | /* prepare receive transfer */ | ||
489 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | ||
490 | DMA_FROM_DEVICE)) { | ||
491 | ret = -EFAULT; | ||
492 | goto end_dummy_mapped; | ||
493 | |||
494 | } | ||
495 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | ||
496 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
497 | if (!desc) { | ||
498 | ret = -EIO; | ||
499 | goto end; | ||
500 | } | ||
501 | |||
502 | rspi_receive_init(rspi); | ||
503 | |||
504 | /* | ||
505 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | ||
506 | * called. So, this driver disables the IRQ while DMA transfer. | ||
507 | */ | ||
508 | disable_irq(rspi->irq); | ||
509 | |||
510 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | ||
511 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | ||
512 | rspi->dma_callbacked = 0; | ||
513 | |||
514 | desc->callback = rspi_dma_complete; | ||
515 | desc->callback_param = rspi; | ||
516 | dmaengine_submit(desc); | ||
517 | dma_async_issue_pending(rspi->chan_rx); | ||
518 | |||
519 | desc_dummy->callback = NULL; /* No callback */ | ||
520 | dmaengine_submit(desc_dummy); | ||
521 | dma_async_issue_pending(rspi->chan_tx); | ||
522 | |||
523 | ret = wait_event_interruptible_timeout(rspi->wait, | ||
524 | rspi->dma_callbacked, HZ); | ||
525 | if (ret > 0 && rspi->dma_callbacked) | ||
526 | ret = 0; | ||
527 | else if (!ret) | ||
528 | ret = -ETIMEDOUT; | ||
529 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | ||
530 | |||
531 | enable_irq(rspi->irq); | ||
532 | |||
533 | end: | ||
534 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | ||
535 | end_dummy_mapped: | ||
536 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | ||
537 | end_nomap: | ||
538 | if (rspi->dma_width_16bit) { | ||
539 | if (!ret) | ||
540 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | ||
541 | kfree(rx_buf); | ||
542 | } | ||
543 | kfree(dummy); | ||
544 | |||
545 | return ret; | ||
546 | } | ||
547 | |||
548 | static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t) | ||
549 | { | ||
550 | if (t->tx_buf && rspi->chan_tx) | ||
551 | return 1; | ||
552 | /* If the module receives data by DMAC, it also needs TX DMAC */ | ||
553 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | ||
554 | return 1; | ||
555 | |||
556 | return 0; | ||
557 | } | ||
558 | |||
559 | static void rspi_work(struct work_struct *work) | ||
560 | { | ||
561 | struct rspi_data *rspi = container_of(work, struct rspi_data, ws); | ||
562 | struct spi_message *mesg; | ||
563 | struct spi_transfer *t; | ||
564 | unsigned long flags; | ||
565 | int ret; | ||
566 | |||
567 | spin_lock_irqsave(&rspi->lock, flags); | ||
568 | while (!list_empty(&rspi->queue)) { | ||
569 | mesg = list_entry(rspi->queue.next, struct spi_message, queue); | ||
570 | list_del_init(&mesg->queue); | ||
571 | spin_unlock_irqrestore(&rspi->lock, flags); | ||
572 | |||
573 | rspi_assert_ssl(rspi); | ||
574 | |||
575 | list_for_each_entry(t, &mesg->transfers, transfer_list) { | ||
576 | if (t->tx_buf) { | ||
577 | if (rspi_is_dma(rspi, t)) | ||
578 | ret = rspi_send_dma(rspi, t); | ||
579 | else | ||
580 | ret = rspi_send_pio(rspi, mesg, t); | ||
581 | if (ret < 0) | ||
582 | goto error; | ||
583 | } | ||
584 | if (t->rx_buf) { | ||
585 | if (rspi_is_dma(rspi, t)) | ||
586 | ret = rspi_receive_dma(rspi, t); | ||
587 | else | ||
588 | ret = rspi_receive_pio(rspi, mesg, t); | ||
589 | if (ret < 0) | ||
590 | goto error; | ||
591 | } | ||
592 | mesg->actual_length += t->len; | ||
593 | } | ||
594 | rspi_negate_ssl(rspi); | ||
595 | |||
596 | mesg->status = 0; | ||
597 | mesg->complete(mesg->context); | ||
598 | |||
599 | spin_lock_irqsave(&rspi->lock, flags); | ||
600 | } | ||
601 | |||
602 | return; | ||
603 | |||
604 | error: | ||
605 | mesg->status = ret; | ||
606 | mesg->complete(mesg->context); | ||
607 | } | ||
608 | |||
609 | static int rspi_setup(struct spi_device *spi) | ||
610 | { | ||
611 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | ||
612 | |||
613 | if (!spi->bits_per_word) | ||
614 | spi->bits_per_word = 8; | ||
615 | rspi->max_speed_hz = spi->max_speed_hz; | ||
616 | |||
617 | rspi_set_config_register(rspi, 8); | ||
618 | |||
619 | return 0; | ||
620 | } | ||
621 | |||
622 | static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) | ||
623 | { | ||
624 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | ||
625 | unsigned long flags; | ||
626 | |||
627 | mesg->actual_length = 0; | ||
628 | mesg->status = -EINPROGRESS; | ||
629 | |||
630 | spin_lock_irqsave(&rspi->lock, flags); | ||
631 | list_add_tail(&mesg->queue, &rspi->queue); | ||
632 | schedule_work(&rspi->ws); | ||
633 | spin_unlock_irqrestore(&rspi->lock, flags); | ||
634 | |||
635 | return 0; | ||
636 | } | ||
637 | |||
638 | static void rspi_cleanup(struct spi_device *spi) | ||
639 | { | ||
640 | } | ||
641 | |||
642 | static irqreturn_t rspi_irq(int irq, void *_sr) | ||
643 | { | ||
644 | struct rspi_data *rspi = (struct rspi_data *)_sr; | ||
645 | unsigned long spsr; | ||
646 | irqreturn_t ret = IRQ_NONE; | ||
647 | unsigned char disable_irq = 0; | ||
648 | |||
649 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | ||
650 | if (spsr & SPSR_SPRF) | ||
651 | disable_irq |= SPCR_SPRIE; | ||
652 | if (spsr & SPSR_SPTEF) | ||
653 | disable_irq |= SPCR_SPTIE; | ||
654 | |||
655 | if (disable_irq) { | ||
656 | ret = IRQ_HANDLED; | ||
657 | rspi_disable_irq(rspi, disable_irq); | ||
658 | wake_up(&rspi->wait); | ||
659 | } | ||
660 | |||
661 | return ret; | ||
662 | } | ||
663 | |||
664 | static int rspi_request_dma(struct rspi_data *rspi, | ||
665 | struct platform_device *pdev) | ||
666 | { | ||
667 | struct rspi_plat_data *rspi_pd = pdev->dev.platform_data; | ||
668 | dma_cap_mask_t mask; | ||
669 | struct dma_slave_config cfg; | ||
670 | int ret; | ||
671 | |||
672 | if (!rspi_pd) | ||
673 | return 0; /* The driver assumes no error. */ | ||
674 | |||
675 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | ||
676 | |||
677 | /* If the module receives data by DMAC, it also needs TX DMAC */ | ||
678 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | ||
679 | dma_cap_zero(mask); | ||
680 | dma_cap_set(DMA_SLAVE, mask); | ||
681 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, | ||
682 | (void *)rspi_pd->dma_rx_id); | ||
683 | if (rspi->chan_rx) { | ||
684 | cfg.slave_id = rspi_pd->dma_rx_id; | ||
685 | cfg.direction = DMA_DEV_TO_MEM; | ||
686 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); | ||
687 | if (!ret) | ||
688 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | ||
689 | else | ||
690 | return ret; | ||
691 | } | ||
692 | } | ||
693 | if (rspi_pd->dma_tx_id) { | ||
694 | dma_cap_zero(mask); | ||
695 | dma_cap_set(DMA_SLAVE, mask); | ||
696 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, | ||
697 | (void *)rspi_pd->dma_tx_id); | ||
698 | if (rspi->chan_tx) { | ||
699 | cfg.slave_id = rspi_pd->dma_tx_id; | ||
700 | cfg.direction = DMA_MEM_TO_DEV; | ||
701 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); | ||
702 | if (!ret) | ||
703 | dev_info(&pdev->dev, "Use DMA when tx\n"); | ||
704 | else | ||
705 | return ret; | ||
706 | } | ||
707 | } | ||
708 | |||
709 | return 0; | ||
710 | } | ||
711 | |||
712 | static void rspi_release_dma(struct rspi_data *rspi) | ||
713 | { | ||
714 | if (rspi->chan_tx) | ||
715 | dma_release_channel(rspi->chan_tx); | ||
716 | if (rspi->chan_rx) | ||
717 | dma_release_channel(rspi->chan_rx); | ||
718 | } | ||
719 | |||
720 | static int rspi_remove(struct platform_device *pdev) | ||
721 | { | ||
722 | struct rspi_data *rspi = dev_get_drvdata(&pdev->dev); | ||
723 | |||
724 | spi_unregister_master(rspi->master); | ||
725 | rspi_release_dma(rspi); | ||
726 | free_irq(platform_get_irq(pdev, 0), rspi); | ||
727 | clk_put(rspi->clk); | ||
728 | iounmap(rspi->addr); | ||
729 | spi_master_put(rspi->master); | ||
730 | |||
731 | return 0; | ||
732 | } | ||
733 | |||
734 | static int rspi_probe(struct platform_device *pdev) | ||
735 | { | ||
736 | struct resource *res; | ||
737 | struct spi_master *master; | ||
738 | struct rspi_data *rspi; | ||
739 | int ret, irq; | ||
740 | char clk_name[16]; | ||
741 | |||
742 | /* get base addr */ | ||
743 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
744 | if (unlikely(res == NULL)) { | ||
745 | dev_err(&pdev->dev, "invalid resource\n"); | ||
746 | return -EINVAL; | ||
747 | } | ||
748 | |||
749 | irq = platform_get_irq(pdev, 0); | ||
750 | if (irq < 0) { | ||
751 | dev_err(&pdev->dev, "platform_get_irq error\n"); | ||
752 | return -ENODEV; | ||
753 | } | ||
754 | |||
755 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); | ||
756 | if (master == NULL) { | ||
757 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | ||
758 | return -ENOMEM; | ||
759 | } | ||
760 | |||
761 | rspi = spi_master_get_devdata(master); | ||
762 | dev_set_drvdata(&pdev->dev, rspi); | ||
763 | |||
764 | rspi->master = master; | ||
765 | rspi->addr = ioremap(res->start, resource_size(res)); | ||
766 | if (rspi->addr == NULL) { | ||
767 | dev_err(&pdev->dev, "ioremap error.\n"); | ||
768 | ret = -ENOMEM; | ||
769 | goto error1; | ||
770 | } | ||
771 | |||
772 | snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id); | ||
773 | rspi->clk = clk_get(&pdev->dev, clk_name); | ||
774 | if (IS_ERR(rspi->clk)) { | ||
775 | dev_err(&pdev->dev, "cannot get clock\n"); | ||
776 | ret = PTR_ERR(rspi->clk); | ||
777 | goto error2; | ||
778 | } | ||
779 | clk_enable(rspi->clk); | ||
780 | |||
781 | INIT_LIST_HEAD(&rspi->queue); | ||
782 | spin_lock_init(&rspi->lock); | ||
783 | INIT_WORK(&rspi->ws, rspi_work); | ||
784 | init_waitqueue_head(&rspi->wait); | ||
785 | |||
786 | master->num_chipselect = 2; | ||
787 | master->bus_num = pdev->id; | ||
788 | master->setup = rspi_setup; | ||
789 | master->transfer = rspi_transfer; | ||
790 | master->cleanup = rspi_cleanup; | ||
791 | |||
792 | ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); | ||
793 | if (ret < 0) { | ||
794 | dev_err(&pdev->dev, "request_irq error\n"); | ||
795 | goto error3; | ||
796 | } | ||
797 | |||
798 | rspi->irq = irq; | ||
799 | ret = rspi_request_dma(rspi, pdev); | ||
800 | if (ret < 0) { | ||
801 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | ||
802 | goto error4; | ||
803 | } | ||
804 | |||
805 | ret = spi_register_master(master); | ||
806 | if (ret < 0) { | ||
807 | dev_err(&pdev->dev, "spi_register_master error.\n"); | ||
808 | goto error4; | ||
809 | } | ||
810 | |||
811 | dev_info(&pdev->dev, "probed\n"); | ||
812 | |||
813 | return 0; | ||
814 | |||
815 | error4: | ||
816 | rspi_release_dma(rspi); | ||
817 | free_irq(irq, rspi); | ||
818 | error3: | ||
819 | clk_put(rspi->clk); | ||
820 | error2: | ||
821 | iounmap(rspi->addr); | ||
822 | error1: | ||
823 | spi_master_put(master); | ||
824 | |||
825 | return ret; | ||
826 | } | ||
827 | |||
828 | static struct platform_driver rspi_driver = { | ||
829 | .probe = rspi_probe, | ||
830 | .remove = rspi_remove, | ||
831 | .driver = { | ||
832 | .name = "rspi", | ||
833 | .owner = THIS_MODULE, | ||
834 | }, | ||
835 | }; | ||
836 | module_platform_driver(rspi_driver); | ||
837 | |||
838 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | ||
839 | MODULE_LICENSE("GPL v2"); | ||
840 | MODULE_AUTHOR("Yoshihiro Shimoda"); | ||
841 | MODULE_ALIAS("platform:rspi"); | ||
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c index 02d64603fcc..1996ac57ef9 100644 --- a/drivers/spi/spi-s3c24xx.c +++ b/drivers/spi/spi-s3c24xx.c | |||
@@ -24,10 +24,9 @@ | |||
24 | 24 | ||
25 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
26 | #include <linux/spi/spi_bitbang.h> | 26 | #include <linux/spi/spi_bitbang.h> |
27 | #include <linux/spi/s3c24xx.h> | ||
28 | #include <linux/module.h> | ||
29 | 27 | ||
30 | #include <plat/regs-spi.h> | 28 | #include <plat/regs-spi.h> |
29 | #include <mach/spi.h> | ||
31 | 30 | ||
32 | #include <plat/fiq.h> | 31 | #include <plat/fiq.h> |
33 | #include <asm/fiq.h> | 32 | #include <asm/fiq.h> |
@@ -506,7 +505,7 @@ static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) | |||
506 | } | 505 | } |
507 | } | 506 | } |
508 | 507 | ||
509 | static int s3c24xx_spi_probe(struct platform_device *pdev) | 508 | static int __init s3c24xx_spi_probe(struct platform_device *pdev) |
510 | { | 509 | { |
511 | struct s3c2410_spi_info *pdata; | 510 | struct s3c2410_spi_info *pdata; |
512 | struct s3c24xx_spi *hw; | 511 | struct s3c24xx_spi *hw; |
@@ -611,7 +610,6 @@ static int s3c24xx_spi_probe(struct platform_device *pdev) | |||
611 | if (!pdata->set_cs) { | 610 | if (!pdata->set_cs) { |
612 | if (pdata->pin_cs < 0) { | 611 | if (pdata->pin_cs < 0) { |
613 | dev_err(&pdev->dev, "No chipselect pin\n"); | 612 | dev_err(&pdev->dev, "No chipselect pin\n"); |
614 | err = -EINVAL; | ||
615 | goto err_register; | 613 | goto err_register; |
616 | } | 614 | } |
617 | 615 | ||
@@ -663,7 +661,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev) | |||
663 | return err; | 661 | return err; |
664 | } | 662 | } |
665 | 663 | ||
666 | static int s3c24xx_spi_remove(struct platform_device *dev) | 664 | static int __exit s3c24xx_spi_remove(struct platform_device *dev) |
667 | { | 665 | { |
668 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | 666 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); |
669 | 667 | ||
@@ -721,15 +719,26 @@ static const struct dev_pm_ops s3c24xx_spi_pmops = { | |||
721 | 719 | ||
722 | MODULE_ALIAS("platform:s3c2410-spi"); | 720 | MODULE_ALIAS("platform:s3c2410-spi"); |
723 | static struct platform_driver s3c24xx_spi_driver = { | 721 | static struct platform_driver s3c24xx_spi_driver = { |
724 | .probe = s3c24xx_spi_probe, | 722 | .remove = __exit_p(s3c24xx_spi_remove), |
725 | .remove = s3c24xx_spi_remove, | ||
726 | .driver = { | 723 | .driver = { |
727 | .name = "s3c2410-spi", | 724 | .name = "s3c2410-spi", |
728 | .owner = THIS_MODULE, | 725 | .owner = THIS_MODULE, |
729 | .pm = S3C24XX_SPI_PMOPS, | 726 | .pm = S3C24XX_SPI_PMOPS, |
730 | }, | 727 | }, |
731 | }; | 728 | }; |
732 | module_platform_driver(s3c24xx_spi_driver); | 729 | |
730 | static int __init s3c24xx_spi_init(void) | ||
731 | { | ||
732 | return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe); | ||
733 | } | ||
734 | |||
735 | static void __exit s3c24xx_spi_exit(void) | ||
736 | { | ||
737 | platform_driver_unregister(&s3c24xx_spi_driver); | ||
738 | } | ||
739 | |||
740 | module_init(s3c24xx_spi_init); | ||
741 | module_exit(s3c24xx_spi_exit); | ||
733 | 742 | ||
734 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | 743 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); |
735 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | 744 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); |
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index ad93231a803..595dacc7645 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c | |||
@@ -20,21 +20,14 @@ | |||
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/module.h> | 21 | #include <linux/module.h> |
22 | #include <linux/workqueue.h> | 22 | #include <linux/workqueue.h> |
23 | #include <linux/interrupt.h> | ||
24 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
25 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
26 | #include <linux/dma-mapping.h> | 25 | #include <linux/dma-mapping.h> |
27 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
28 | #include <linux/pm_runtime.h> | ||
29 | #include <linux/spi/spi.h> | 27 | #include <linux/spi/spi.h> |
30 | #include <linux/gpio.h> | ||
31 | #include <linux/of.h> | ||
32 | #include <linux/of_gpio.h> | ||
33 | 28 | ||
34 | #include <mach/dma.h> | 29 | #include <mach/dma.h> |
35 | #include <linux/platform_data/spi-s3c64xx.h> | 30 | #include <plat/s3c64xx-spi.h> |
36 | |||
37 | #define MAX_SPI_PORTS 3 | ||
38 | 31 | ||
39 | /* Registers and bit-fields */ | 32 | /* Registers and bit-fields */ |
40 | 33 | ||
@@ -79,6 +72,11 @@ | |||
79 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | 72 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) |
80 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | 73 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) |
81 | 74 | ||
75 | #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) | ||
76 | |||
77 | #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ | ||
78 | (c)->regs + S3C64XX_SPI_SLAVE_SEL) | ||
79 | |||
82 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) | 80 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
83 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | 81 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
84 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | 82 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
@@ -113,12 +111,13 @@ | |||
113 | 111 | ||
114 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | 112 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
115 | 113 | ||
116 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) | 114 | #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ |
117 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | 115 | (((i)->fifo_lvl_mask + 1))) \ |
118 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | 116 | ? 1 : 0) |
119 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | 117 | |
120 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | 118 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) |
121 | FIFO_LVL_MASK(i)) | 119 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) |
120 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) | ||
122 | 121 | ||
123 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | 122 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
124 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | 123 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
@@ -127,45 +126,20 @@ | |||
127 | 126 | ||
128 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | 127 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
129 | 128 | ||
129 | #define SUSPND (1<<0) | ||
130 | #define SPIBUSY (1<<1) | ||
130 | #define RXBUSY (1<<2) | 131 | #define RXBUSY (1<<2) |
131 | #define TXBUSY (1<<3) | 132 | #define TXBUSY (1<<3) |
132 | 133 | ||
133 | struct s3c64xx_spi_dma_data { | ||
134 | unsigned ch; | ||
135 | enum dma_transfer_direction direction; | ||
136 | enum dma_ch dmach; | ||
137 | struct property *dma_prop; | ||
138 | }; | ||
139 | |||
140 | /** | ||
141 | * struct s3c64xx_spi_info - SPI Controller hardware info | ||
142 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | ||
143 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | ||
144 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | ||
145 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | ||
146 | * @clk_from_cmu: True, if the controller does not include a clock mux and | ||
147 | * prescaler unit. | ||
148 | * | ||
149 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | ||
150 | * differ in some aspects such as the size of the fifo and spi bus clock | ||
151 | * setup. Such differences are specified to the driver using this structure | ||
152 | * which is provided as driver data to the driver. | ||
153 | */ | ||
154 | struct s3c64xx_spi_port_config { | ||
155 | int fifo_lvl_mask[MAX_SPI_PORTS]; | ||
156 | int rx_lvl_offset; | ||
157 | int tx_st_done; | ||
158 | bool high_speed; | ||
159 | bool clk_from_cmu; | ||
160 | }; | ||
161 | |||
162 | /** | 134 | /** |
163 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | 135 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
164 | * @clk: Pointer to the spi clock. | 136 | * @clk: Pointer to the spi clock. |
165 | * @src_clk: Pointer to the clock used to generate SPI signals. | 137 | * @src_clk: Pointer to the clock used to generate SPI signals. |
166 | * @master: Pointer to the SPI Protocol master. | 138 | * @master: Pointer to the SPI Protocol master. |
139 | * @workqueue: Work queue for the SPI xfer requests. | ||
167 | * @cntrlr_info: Platform specific data for the controller this driver manages. | 140 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
168 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | 141 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. |
142 | * @work: Work | ||
169 | * @queue: To log SPI xfer requests. | 143 | * @queue: To log SPI xfer requests. |
170 | * @lock: Controller specific lock. | 144 | * @lock: Controller specific lock. |
171 | * @state: Set of FLAGS to indicate status. | 145 | * @state: Set of FLAGS to indicate status. |
@@ -173,7 +147,6 @@ struct s3c64xx_spi_port_config { | |||
173 | * @tx_dmach: Controller's DMA channel for Tx. | 147 | * @tx_dmach: Controller's DMA channel for Tx. |
174 | * @sfr_start: BUS address of SPI controller regs. | 148 | * @sfr_start: BUS address of SPI controller regs. |
175 | * @regs: Pointer to ioremap'ed controller registers. | 149 | * @regs: Pointer to ioremap'ed controller registers. |
176 | * @irq: interrupt | ||
177 | * @xfer_completion: To indicate completion of xfer task. | 150 | * @xfer_completion: To indicate completion of xfer task. |
178 | * @cur_mode: Stores the active configuration of the controller. | 151 | * @cur_mode: Stores the active configuration of the controller. |
179 | * @cur_bpw: Stores the active bits per word settings. | 152 | * @cur_bpw: Stores the active bits per word settings. |
@@ -185,21 +158,19 @@ struct s3c64xx_spi_driver_data { | |||
185 | struct clk *src_clk; | 158 | struct clk *src_clk; |
186 | struct platform_device *pdev; | 159 | struct platform_device *pdev; |
187 | struct spi_master *master; | 160 | struct spi_master *master; |
161 | struct workqueue_struct *workqueue; | ||
188 | struct s3c64xx_spi_info *cntrlr_info; | 162 | struct s3c64xx_spi_info *cntrlr_info; |
189 | struct spi_device *tgl_spi; | 163 | struct spi_device *tgl_spi; |
164 | struct work_struct work; | ||
190 | struct list_head queue; | 165 | struct list_head queue; |
191 | spinlock_t lock; | 166 | spinlock_t lock; |
167 | enum dma_ch rx_dmach; | ||
168 | enum dma_ch tx_dmach; | ||
192 | unsigned long sfr_start; | 169 | unsigned long sfr_start; |
193 | struct completion xfer_completion; | 170 | struct completion xfer_completion; |
194 | unsigned state; | 171 | unsigned state; |
195 | unsigned cur_mode, cur_bpw; | 172 | unsigned cur_mode, cur_bpw; |
196 | unsigned cur_speed; | 173 | unsigned cur_speed; |
197 | struct s3c64xx_spi_dma_data rx_dma; | ||
198 | struct s3c64xx_spi_dma_data tx_dma; | ||
199 | struct samsung_dma_ops *ops; | ||
200 | struct s3c64xx_spi_port_config *port_conf; | ||
201 | unsigned int port_id; | ||
202 | unsigned long gpios[4]; | ||
203 | }; | 174 | }; |
204 | 175 | ||
205 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { | 176 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { |
@@ -208,6 +179,7 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = { | |||
208 | 179 | ||
209 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | 180 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
210 | { | 181 | { |
182 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
211 | void __iomem *regs = sdd->regs; | 183 | void __iomem *regs = sdd->regs; |
212 | unsigned long loops; | 184 | unsigned long loops; |
213 | u32 val; | 185 | u32 val; |
@@ -215,10 +187,6 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |||
215 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | 187 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
216 | 188 | ||
217 | val = readl(regs + S3C64XX_SPI_CH_CFG); | 189 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
218 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | ||
219 | writel(val, regs + S3C64XX_SPI_CH_CFG); | ||
220 | |||
221 | val = readl(regs + S3C64XX_SPI_CH_CFG); | ||
222 | val |= S3C64XX_SPI_CH_SW_RST; | 190 | val |= S3C64XX_SPI_CH_SW_RST; |
223 | val &= ~S3C64XX_SPI_CH_HS_EN; | 191 | val &= ~S3C64XX_SPI_CH_HS_EN; |
224 | writel(val, regs + S3C64XX_SPI_CH_CFG); | 192 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
@@ -227,7 +195,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |||
227 | loops = msecs_to_loops(1); | 195 | loops = msecs_to_loops(1); |
228 | do { | 196 | do { |
229 | val = readl(regs + S3C64XX_SPI_STATUS); | 197 | val = readl(regs + S3C64XX_SPI_STATUS); |
230 | } while (TX_FIFO_LVL(val, sdd) && loops--); | 198 | } while (TX_FIFO_LVL(val, sci) && loops--); |
231 | 199 | ||
232 | if (loops == 0) | 200 | if (loops == 0) |
233 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | 201 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); |
@@ -236,7 +204,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |||
236 | loops = msecs_to_loops(1); | 204 | loops = msecs_to_loops(1); |
237 | do { | 205 | do { |
238 | val = readl(regs + S3C64XX_SPI_STATUS); | 206 | val = readl(regs + S3C64XX_SPI_STATUS); |
239 | if (RX_FIFO_LVL(val, sdd)) | 207 | if (RX_FIFO_LVL(val, sci)) |
240 | readl(regs + S3C64XX_SPI_RX_DATA); | 208 | readl(regs + S3C64XX_SPI_RX_DATA); |
241 | else | 209 | else |
242 | break; | 210 | break; |
@@ -252,91 +220,17 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |||
252 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | 220 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
253 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | 221 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
254 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | 222 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
255 | } | ||
256 | |||
257 | static void s3c64xx_spi_dmacb(void *data) | ||
258 | { | ||
259 | struct s3c64xx_spi_driver_data *sdd; | ||
260 | struct s3c64xx_spi_dma_data *dma = data; | ||
261 | unsigned long flags; | ||
262 | |||
263 | if (dma->direction == DMA_DEV_TO_MEM) | ||
264 | sdd = container_of(data, | ||
265 | struct s3c64xx_spi_driver_data, rx_dma); | ||
266 | else | ||
267 | sdd = container_of(data, | ||
268 | struct s3c64xx_spi_driver_data, tx_dma); | ||
269 | |||
270 | spin_lock_irqsave(&sdd->lock, flags); | ||
271 | |||
272 | if (dma->direction == DMA_DEV_TO_MEM) { | ||
273 | sdd->state &= ~RXBUSY; | ||
274 | if (!(sdd->state & TXBUSY)) | ||
275 | complete(&sdd->xfer_completion); | ||
276 | } else { | ||
277 | sdd->state &= ~TXBUSY; | ||
278 | if (!(sdd->state & RXBUSY)) | ||
279 | complete(&sdd->xfer_completion); | ||
280 | } | ||
281 | |||
282 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
283 | } | ||
284 | |||
285 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, | ||
286 | unsigned len, dma_addr_t buf) | ||
287 | { | ||
288 | struct s3c64xx_spi_driver_data *sdd; | ||
289 | struct samsung_dma_prep info; | ||
290 | struct samsung_dma_config config; | ||
291 | |||
292 | if (dma->direction == DMA_DEV_TO_MEM) { | ||
293 | sdd = container_of((void *)dma, | ||
294 | struct s3c64xx_spi_driver_data, rx_dma); | ||
295 | config.direction = sdd->rx_dma.direction; | ||
296 | config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | ||
297 | config.width = sdd->cur_bpw / 8; | ||
298 | sdd->ops->config(sdd->rx_dma.ch, &config); | ||
299 | } else { | ||
300 | sdd = container_of((void *)dma, | ||
301 | struct s3c64xx_spi_driver_data, tx_dma); | ||
302 | config.direction = sdd->tx_dma.direction; | ||
303 | config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | ||
304 | config.width = sdd->cur_bpw / 8; | ||
305 | sdd->ops->config(sdd->tx_dma.ch, &config); | ||
306 | } | ||
307 | 223 | ||
308 | info.cap = DMA_SLAVE; | 224 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
309 | info.len = len; | 225 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
310 | info.fp = s3c64xx_spi_dmacb; | 226 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
311 | info.fp_param = dma; | ||
312 | info.direction = dma->direction; | ||
313 | info.buf = buf; | ||
314 | |||
315 | sdd->ops->prepare(dma->ch, &info); | ||
316 | sdd->ops->trigger(dma->ch); | ||
317 | } | ||
318 | |||
319 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) | ||
320 | { | ||
321 | struct samsung_dma_req req; | ||
322 | |||
323 | sdd->ops = samsung_dma_get_ops(); | ||
324 | |||
325 | req.cap = DMA_SLAVE; | ||
326 | req.client = &s3c64xx_spi_dma_client; | ||
327 | |||
328 | req.dt_dmach_prop = sdd->rx_dma.dma_prop; | ||
329 | sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req); | ||
330 | req.dt_dmach_prop = sdd->tx_dma.dma_prop; | ||
331 | sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req); | ||
332 | |||
333 | return 1; | ||
334 | } | 227 | } |
335 | 228 | ||
336 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, | 229 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
337 | struct spi_device *spi, | 230 | struct spi_device *spi, |
338 | struct spi_transfer *xfer, int dma_mode) | 231 | struct spi_transfer *xfer, int dma_mode) |
339 | { | 232 | { |
233 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
340 | void __iomem *regs = sdd->regs; | 234 | void __iomem *regs = sdd->regs; |
341 | u32 modecfg, chcfg; | 235 | u32 modecfg, chcfg; |
342 | 236 | ||
@@ -364,7 +258,10 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, | |||
364 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | 258 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
365 | if (dma_mode) { | 259 | if (dma_mode) { |
366 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | 260 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
367 | prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); | 261 | s3c2410_dma_config(sdd->tx_dmach, sdd->cur_bpw / 8); |
262 | s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd, | ||
263 | xfer->tx_dma, xfer->len); | ||
264 | s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START); | ||
368 | } else { | 265 | } else { |
369 | switch (sdd->cur_bpw) { | 266 | switch (sdd->cur_bpw) { |
370 | case 32: | 267 | case 32: |
@@ -386,7 +283,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, | |||
386 | if (xfer->rx_buf != NULL) { | 283 | if (xfer->rx_buf != NULL) { |
387 | sdd->state |= RXBUSY; | 284 | sdd->state |= RXBUSY; |
388 | 285 | ||
389 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL | 286 | if (sci->high_speed && sdd->cur_speed >= 30000000UL |
390 | && !(sdd->cur_mode & SPI_CPHA)) | 287 | && !(sdd->cur_mode & SPI_CPHA)) |
391 | chcfg |= S3C64XX_SPI_CH_HS_EN; | 288 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
392 | 289 | ||
@@ -396,7 +293,10 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, | |||
396 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | 293 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
397 | | S3C64XX_SPI_PACKET_CNT_EN, | 294 | | S3C64XX_SPI_PACKET_CNT_EN, |
398 | regs + S3C64XX_SPI_PACKET_CNT); | 295 | regs + S3C64XX_SPI_PACKET_CNT); |
399 | prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); | 296 | s3c2410_dma_config(sdd->rx_dmach, sdd->cur_bpw / 8); |
297 | s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd, | ||
298 | xfer->rx_dma, xfer->len); | ||
299 | s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START); | ||
400 | } | 300 | } |
401 | } | 301 | } |
402 | 302 | ||
@@ -413,19 +313,20 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, | |||
413 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ | 313 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ |
414 | /* Deselect the last toggled device */ | 314 | /* Deselect the last toggled device */ |
415 | cs = sdd->tgl_spi->controller_data; | 315 | cs = sdd->tgl_spi->controller_data; |
416 | gpio_set_value(cs->line, | 316 | cs->set_level(cs->line, |
417 | spi->mode & SPI_CS_HIGH ? 0 : 1); | 317 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
418 | } | 318 | } |
419 | sdd->tgl_spi = NULL; | 319 | sdd->tgl_spi = NULL; |
420 | } | 320 | } |
421 | 321 | ||
422 | cs = spi->controller_data; | 322 | cs = spi->controller_data; |
423 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); | 323 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); |
424 | } | 324 | } |
425 | 325 | ||
426 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, | 326 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, |
427 | struct spi_transfer *xfer, int dma_mode) | 327 | struct spi_transfer *xfer, int dma_mode) |
428 | { | 328 | { |
329 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
429 | void __iomem *regs = sdd->regs; | 330 | void __iomem *regs = sdd->regs; |
430 | unsigned long val; | 331 | unsigned long val; |
431 | int ms; | 332 | int ms; |
@@ -442,7 +343,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, | |||
442 | val = msecs_to_loops(ms); | 343 | val = msecs_to_loops(ms); |
443 | do { | 344 | do { |
444 | status = readl(regs + S3C64XX_SPI_STATUS); | 345 | status = readl(regs + S3C64XX_SPI_STATUS); |
445 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | 346 | } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); |
446 | } | 347 | } |
447 | 348 | ||
448 | if (!val) | 349 | if (!val) |
@@ -461,8 +362,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, | |||
461 | if (xfer->rx_buf == NULL) { | 362 | if (xfer->rx_buf == NULL) { |
462 | val = msecs_to_loops(10); | 363 | val = msecs_to_loops(10); |
463 | status = readl(regs + S3C64XX_SPI_STATUS); | 364 | status = readl(regs + S3C64XX_SPI_STATUS); |
464 | while ((TX_FIFO_LVL(status, sdd) | 365 | while ((TX_FIFO_LVL(status, sci) |
465 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | 366 | || !S3C64XX_SPI_ST_TX_DONE(status, sci)) |
466 | && --val) { | 367 | && --val) { |
467 | cpu_relax(); | 368 | cpu_relax(); |
468 | status = readl(regs + S3C64XX_SPI_STATUS); | 369 | status = readl(regs + S3C64XX_SPI_STATUS); |
@@ -506,17 +407,18 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, | |||
506 | if (sdd->tgl_spi == spi) | 407 | if (sdd->tgl_spi == spi) |
507 | sdd->tgl_spi = NULL; | 408 | sdd->tgl_spi = NULL; |
508 | 409 | ||
509 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); | 410 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); |
510 | } | 411 | } |
511 | 412 | ||
512 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) | 413 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
513 | { | 414 | { |
415 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
514 | void __iomem *regs = sdd->regs; | 416 | void __iomem *regs = sdd->regs; |
515 | u32 val; | 417 | u32 val; |
516 | 418 | ||
517 | /* Disable Clock */ | 419 | /* Disable Clock */ |
518 | if (sdd->port_conf->clk_from_cmu) { | 420 | if (sci->clk_from_cmu) { |
519 | clk_disable_unprepare(sdd->src_clk); | 421 | clk_disable(sdd->src_clk); |
520 | } else { | 422 | } else { |
521 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | 423 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
522 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | 424 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
@@ -559,12 +461,12 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) | |||
559 | 461 | ||
560 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | 462 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
561 | 463 | ||
562 | if (sdd->port_conf->clk_from_cmu) { | 464 | if (sci->clk_from_cmu) { |
563 | /* Configure Clock */ | 465 | /* Configure Clock */ |
564 | /* There is half-multiplier before the SPI */ | 466 | /* There is half-multiplier before the SPI */ |
565 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); | 467 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
566 | /* Enable Clock */ | 468 | /* Enable Clock */ |
567 | clk_prepare_enable(sdd->src_clk); | 469 | clk_enable(sdd->src_clk); |
568 | } else { | 470 | } else { |
569 | /* Configure Clock */ | 471 | /* Configure Clock */ |
570 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | 472 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
@@ -580,11 +482,52 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) | |||
580 | } | 482 | } |
581 | } | 483 | } |
582 | 484 | ||
485 | static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, | ||
486 | int size, enum s3c2410_dma_buffresult res) | ||
487 | { | ||
488 | struct s3c64xx_spi_driver_data *sdd = buf_id; | ||
489 | unsigned long flags; | ||
490 | |||
491 | spin_lock_irqsave(&sdd->lock, flags); | ||
492 | |||
493 | if (res == S3C2410_RES_OK) | ||
494 | sdd->state &= ~RXBUSY; | ||
495 | else | ||
496 | dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size); | ||
497 | |||
498 | /* If the other done */ | ||
499 | if (!(sdd->state & TXBUSY)) | ||
500 | complete(&sdd->xfer_completion); | ||
501 | |||
502 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
503 | } | ||
504 | |||
505 | static void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id, | ||
506 | int size, enum s3c2410_dma_buffresult res) | ||
507 | { | ||
508 | struct s3c64xx_spi_driver_data *sdd = buf_id; | ||
509 | unsigned long flags; | ||
510 | |||
511 | spin_lock_irqsave(&sdd->lock, flags); | ||
512 | |||
513 | if (res == S3C2410_RES_OK) | ||
514 | sdd->state &= ~TXBUSY; | ||
515 | else | ||
516 | dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size); | ||
517 | |||
518 | /* If the other done */ | ||
519 | if (!(sdd->state & RXBUSY)) | ||
520 | complete(&sdd->xfer_completion); | ||
521 | |||
522 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
523 | } | ||
524 | |||
583 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) | 525 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
584 | 526 | ||
585 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, | 527 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, |
586 | struct spi_message *msg) | 528 | struct spi_message *msg) |
587 | { | 529 | { |
530 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
588 | struct device *dev = &sdd->pdev->dev; | 531 | struct device *dev = &sdd->pdev->dev; |
589 | struct spi_transfer *xfer; | 532 | struct spi_transfer *xfer; |
590 | 533 | ||
@@ -600,7 +543,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, | |||
600 | /* Map until end or first fail */ | 543 | /* Map until end or first fail */ |
601 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | 544 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
602 | 545 | ||
603 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) | 546 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) |
604 | continue; | 547 | continue; |
605 | 548 | ||
606 | if (xfer->tx_buf != NULL) { | 549 | if (xfer->tx_buf != NULL) { |
@@ -634,6 +577,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, | |||
634 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, | 577 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, |
635 | struct spi_message *msg) | 578 | struct spi_message *msg) |
636 | { | 579 | { |
580 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | ||
637 | struct device *dev = &sdd->pdev->dev; | 581 | struct device *dev = &sdd->pdev->dev; |
638 | struct spi_transfer *xfer; | 582 | struct spi_transfer *xfer; |
639 | 583 | ||
@@ -642,7 +586,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, | |||
642 | 586 | ||
643 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | 587 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
644 | 588 | ||
645 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) | 589 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) |
646 | continue; | 590 | continue; |
647 | 591 | ||
648 | if (xfer->rx_buf != NULL | 592 | if (xfer->rx_buf != NULL |
@@ -657,10 +601,10 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, | |||
657 | } | 601 | } |
658 | } | 602 | } |
659 | 603 | ||
660 | static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | 604 | static void handle_msg(struct s3c64xx_spi_driver_data *sdd, |
661 | struct spi_message *msg) | 605 | struct spi_message *msg) |
662 | { | 606 | { |
663 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | 607 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
664 | struct spi_device *spi = msg->spi; | 608 | struct spi_device *spi = msg->spi; |
665 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | 609 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
666 | struct spi_transfer *xfer; | 610 | struct spi_transfer *xfer; |
@@ -715,7 +659,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
715 | } | 659 | } |
716 | 660 | ||
717 | /* Polling method for xfers not bigger than FIFO capacity */ | 661 | /* Polling method for xfers not bigger than FIFO capacity */ |
718 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) | 662 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) |
719 | use_dma = 0; | 663 | use_dma = 0; |
720 | else | 664 | else |
721 | use_dma = 1; | 665 | use_dma = 1; |
@@ -732,15 +676,14 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
732 | enable_cs(sdd, spi); | 676 | enable_cs(sdd, spi); |
733 | 677 | ||
734 | /* Start the signals */ | 678 | /* Start the signals */ |
735 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | 679 | S3C64XX_SPI_ACT(sdd); |
736 | 680 | ||
737 | spin_unlock_irqrestore(&sdd->lock, flags); | 681 | spin_unlock_irqrestore(&sdd->lock, flags); |
738 | 682 | ||
739 | status = wait_for_xfer(sdd, xfer, use_dma); | 683 | status = wait_for_xfer(sdd, xfer, use_dma); |
740 | 684 | ||
741 | /* Quiese the signals */ | 685 | /* Quiese the signals */ |
742 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, | 686 | S3C64XX_SPI_DEACT(sdd); |
743 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | ||
744 | 687 | ||
745 | if (status) { | 688 | if (status) { |
746 | dev_err(&spi->dev, "I/O Error: " | 689 | dev_err(&spi->dev, "I/O Error: " |
@@ -753,10 +696,12 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
753 | if (use_dma) { | 696 | if (use_dma) { |
754 | if (xfer->tx_buf != NULL | 697 | if (xfer->tx_buf != NULL |
755 | && (sdd->state & TXBUSY)) | 698 | && (sdd->state & TXBUSY)) |
756 | sdd->ops->stop(sdd->tx_dma.ch); | 699 | s3c2410_dma_ctrl(sdd->tx_dmach, |
700 | S3C2410_DMAOP_FLUSH); | ||
757 | if (xfer->rx_buf != NULL | 701 | if (xfer->rx_buf != NULL |
758 | && (sdd->state & RXBUSY)) | 702 | && (sdd->state & RXBUSY)) |
759 | sdd->ops->stop(sdd->rx_dma.ch); | 703 | s3c2410_dma_ctrl(sdd->rx_dmach, |
704 | S3C2410_DMAOP_FLUSH); | ||
760 | } | 705 | } |
761 | 706 | ||
762 | goto out; | 707 | goto out; |
@@ -771,6 +716,8 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
771 | if (list_is_last(&xfer->transfer_list, | 716 | if (list_is_last(&xfer->transfer_list, |
772 | &msg->transfers)) | 717 | &msg->transfers)) |
773 | cs_toggle = 1; | 718 | cs_toggle = 1; |
719 | else | ||
720 | disable_cs(sdd, spi); | ||
774 | } | 721 | } |
775 | 722 | ||
776 | msg->actual_length += xfer->len; | 723 | msg->actual_length += xfer->len; |
@@ -788,78 +735,99 @@ out: | |||
788 | 735 | ||
789 | msg->status = status; | 736 | msg->status = status; |
790 | 737 | ||
791 | spi_finalize_current_message(master); | 738 | if (msg->complete) |
739 | msg->complete(msg->context); | ||
740 | } | ||
792 | 741 | ||
793 | return 0; | 742 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) |
743 | { | ||
744 | if (s3c2410_dma_request(sdd->rx_dmach, | ||
745 | &s3c64xx_spi_dma_client, NULL) < 0) { | ||
746 | dev_err(&sdd->pdev->dev, "cannot get RxDMA\n"); | ||
747 | return 0; | ||
748 | } | ||
749 | s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb); | ||
750 | s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW, | ||
751 | sdd->sfr_start + S3C64XX_SPI_RX_DATA); | ||
752 | |||
753 | if (s3c2410_dma_request(sdd->tx_dmach, | ||
754 | &s3c64xx_spi_dma_client, NULL) < 0) { | ||
755 | dev_err(&sdd->pdev->dev, "cannot get TxDMA\n"); | ||
756 | s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client); | ||
757 | return 0; | ||
758 | } | ||
759 | s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb); | ||
760 | s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM, | ||
761 | sdd->sfr_start + S3C64XX_SPI_TX_DATA); | ||
762 | |||
763 | return 1; | ||
794 | } | 764 | } |
795 | 765 | ||
796 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) | 766 | static void s3c64xx_spi_work(struct work_struct *work) |
797 | { | 767 | { |
798 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | 768 | struct s3c64xx_spi_driver_data *sdd = container_of(work, |
769 | struct s3c64xx_spi_driver_data, work); | ||
770 | unsigned long flags; | ||
799 | 771 | ||
800 | /* Acquire DMA channels */ | 772 | /* Acquire DMA channels */ |
801 | while (!acquire_dma(sdd)) | 773 | while (!acquire_dma(sdd)) |
802 | msleep(10); | 774 | msleep(10); |
803 | 775 | ||
804 | pm_runtime_get_sync(&sdd->pdev->dev); | 776 | spin_lock_irqsave(&sdd->lock, flags); |
805 | 777 | ||
806 | return 0; | 778 | while (!list_empty(&sdd->queue) |
807 | } | 779 | && !(sdd->state & SUSPND)) { |
808 | 780 | ||
809 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | 781 | struct spi_message *msg; |
810 | { | ||
811 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | ||
812 | 782 | ||
813 | /* Free DMA channels */ | 783 | msg = container_of(sdd->queue.next, struct spi_message, queue); |
814 | sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client); | ||
815 | sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client); | ||
816 | 784 | ||
817 | pm_runtime_put(&sdd->pdev->dev); | 785 | list_del_init(&msg->queue); |
818 | 786 | ||
819 | return 0; | 787 | /* Set Xfer busy flag */ |
788 | sdd->state |= SPIBUSY; | ||
789 | |||
790 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
791 | |||
792 | handle_msg(sdd, msg); | ||
793 | |||
794 | spin_lock_irqsave(&sdd->lock, flags); | ||
795 | |||
796 | sdd->state &= ~SPIBUSY; | ||
797 | } | ||
798 | |||
799 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
800 | |||
801 | /* Free DMA channels */ | ||
802 | s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client); | ||
803 | s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client); | ||
820 | } | 804 | } |
821 | 805 | ||
822 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( | 806 | static int s3c64xx_spi_transfer(struct spi_device *spi, |
823 | struct s3c64xx_spi_driver_data *sdd, | 807 | struct spi_message *msg) |
824 | struct spi_device *spi) | ||
825 | { | 808 | { |
826 | struct s3c64xx_spi_csinfo *cs; | 809 | struct s3c64xx_spi_driver_data *sdd; |
827 | struct device_node *slave_np, *data_np = NULL; | 810 | unsigned long flags; |
828 | u32 fb_delay = 0; | ||
829 | 811 | ||
830 | slave_np = spi->dev.of_node; | 812 | sdd = spi_master_get_devdata(spi->master); |
831 | if (!slave_np) { | ||
832 | dev_err(&spi->dev, "device node not found\n"); | ||
833 | return ERR_PTR(-EINVAL); | ||
834 | } | ||
835 | 813 | ||
836 | data_np = of_get_child_by_name(slave_np, "controller-data"); | 814 | spin_lock_irqsave(&sdd->lock, flags); |
837 | if (!data_np) { | ||
838 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | ||
839 | return ERR_PTR(-EINVAL); | ||
840 | } | ||
841 | 815 | ||
842 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | 816 | if (sdd->state & SUSPND) { |
843 | if (!cs) { | 817 | spin_unlock_irqrestore(&sdd->lock, flags); |
844 | dev_err(&spi->dev, "could not allocate memory for controller" | 818 | return -ESHUTDOWN; |
845 | " data\n"); | ||
846 | of_node_put(data_np); | ||
847 | return ERR_PTR(-ENOMEM); | ||
848 | } | 819 | } |
849 | 820 | ||
850 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); | 821 | msg->status = -EINPROGRESS; |
851 | if (!gpio_is_valid(cs->line)) { | 822 | msg->actual_length = 0; |
852 | dev_err(&spi->dev, "chip select gpio is not specified or " | 823 | |
853 | "invalid\n"); | 824 | list_add_tail(&msg->queue, &sdd->queue); |
854 | kfree(cs); | 825 | |
855 | of_node_put(data_np); | 826 | queue_work(sdd->workqueue, &sdd->work); |
856 | return ERR_PTR(-EINVAL); | 827 | |
857 | } | 828 | spin_unlock_irqrestore(&sdd->lock, flags); |
858 | 829 | ||
859 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); | 830 | return 0; |
860 | cs->fb_delay = fb_delay; | ||
861 | of_node_put(data_np); | ||
862 | return cs; | ||
863 | } | 831 | } |
864 | 832 | ||
865 | /* | 833 | /* |
@@ -875,31 +843,14 @@ static int s3c64xx_spi_setup(struct spi_device *spi) | |||
875 | struct s3c64xx_spi_info *sci; | 843 | struct s3c64xx_spi_info *sci; |
876 | struct spi_message *msg; | 844 | struct spi_message *msg; |
877 | unsigned long flags; | 845 | unsigned long flags; |
878 | int err; | 846 | int err = 0; |
879 | 847 | ||
880 | sdd = spi_master_get_devdata(spi->master); | 848 | if (cs == NULL || cs->set_level == NULL) { |
881 | if (!cs && spi->dev.of_node) { | ||
882 | cs = s3c64xx_get_slave_ctrldata(sdd, spi); | ||
883 | spi->controller_data = cs; | ||
884 | } | ||
885 | |||
886 | if (IS_ERR_OR_NULL(cs)) { | ||
887 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); | 849 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
888 | return -ENODEV; | 850 | return -ENODEV; |
889 | } | 851 | } |
890 | 852 | ||
891 | if (!spi_get_ctldata(spi)) { | 853 | sdd = spi_master_get_devdata(spi->master); |
892 | err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, | ||
893 | dev_name(&spi->dev)); | ||
894 | if (err) { | ||
895 | dev_err(&spi->dev, | ||
896 | "Failed to get /CS gpio [%d]: %d\n", | ||
897 | cs->line, err); | ||
898 | goto err_gpio_req; | ||
899 | } | ||
900 | spi_set_ctldata(spi, cs); | ||
901 | } | ||
902 | |||
903 | sci = sdd->cntrlr_info; | 854 | sci = sdd->cntrlr_info; |
904 | 855 | ||
905 | spin_lock_irqsave(&sdd->lock, flags); | 856 | spin_lock_irqsave(&sdd->lock, flags); |
@@ -910,11 +861,17 @@ static int s3c64xx_spi_setup(struct spi_device *spi) | |||
910 | dev_err(&spi->dev, | 861 | dev_err(&spi->dev, |
911 | "setup: attempt while mssg in queue!\n"); | 862 | "setup: attempt while mssg in queue!\n"); |
912 | spin_unlock_irqrestore(&sdd->lock, flags); | 863 | spin_unlock_irqrestore(&sdd->lock, flags); |
913 | err = -EBUSY; | 864 | return -EBUSY; |
914 | goto err_msgq; | ||
915 | } | 865 | } |
916 | } | 866 | } |
917 | 867 | ||
868 | if (sdd->state & SUSPND) { | ||
869 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
870 | dev_err(&spi->dev, | ||
871 | "setup: SPI-%d not active!\n", spi->master->bus_num); | ||
872 | return -ESHUTDOWN; | ||
873 | } | ||
874 | |||
918 | spin_unlock_irqrestore(&sdd->lock, flags); | 875 | spin_unlock_irqrestore(&sdd->lock, flags); |
919 | 876 | ||
920 | if (spi->bits_per_word != 8 | 877 | if (spi->bits_per_word != 8 |
@@ -926,10 +883,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) | |||
926 | goto setup_exit; | 883 | goto setup_exit; |
927 | } | 884 | } |
928 | 885 | ||
929 | pm_runtime_get_sync(&sdd->pdev->dev); | ||
930 | |||
931 | /* Check if we can provide the requested rate */ | 886 | /* Check if we can provide the requested rate */ |
932 | if (!sdd->port_conf->clk_from_cmu) { | 887 | if (!sci->clk_from_cmu) { |
933 | u32 psr, speed; | 888 | u32 psr, speed; |
934 | 889 | ||
935 | /* Max possible */ | 890 | /* Max possible */ |
@@ -954,72 +909,20 @@ static int s3c64xx_spi_setup(struct spi_device *spi) | |||
954 | } | 909 | } |
955 | 910 | ||
956 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | 911 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
957 | if (spi->max_speed_hz >= speed) { | 912 | if (spi->max_speed_hz >= speed) |
958 | spi->max_speed_hz = speed; | 913 | spi->max_speed_hz = speed; |
959 | } else { | 914 | else |
960 | err = -EINVAL; | 915 | err = -EINVAL; |
961 | goto setup_exit; | ||
962 | } | ||
963 | } | 916 | } |
964 | 917 | ||
965 | pm_runtime_put(&sdd->pdev->dev); | ||
966 | disable_cs(sdd, spi); | ||
967 | return 0; | ||
968 | |||
969 | setup_exit: | 918 | setup_exit: |
919 | |||
970 | /* setup() returns with device de-selected */ | 920 | /* setup() returns with device de-selected */ |
971 | disable_cs(sdd, spi); | 921 | disable_cs(sdd, spi); |
972 | 922 | ||
973 | err_msgq: | ||
974 | gpio_free(cs->line); | ||
975 | spi_set_ctldata(spi, NULL); | ||
976 | |||
977 | err_gpio_req: | ||
978 | if (spi->dev.of_node) | ||
979 | kfree(cs); | ||
980 | |||
981 | return err; | 923 | return err; |
982 | } | 924 | } |
983 | 925 | ||
984 | static void s3c64xx_spi_cleanup(struct spi_device *spi) | ||
985 | { | ||
986 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | ||
987 | |||
988 | if (cs) { | ||
989 | gpio_free(cs->line); | ||
990 | if (spi->dev.of_node) | ||
991 | kfree(cs); | ||
992 | } | ||
993 | spi_set_ctldata(spi, NULL); | ||
994 | } | ||
995 | |||
996 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) | ||
997 | { | ||
998 | struct s3c64xx_spi_driver_data *sdd = data; | ||
999 | struct spi_master *spi = sdd->master; | ||
1000 | unsigned int val; | ||
1001 | |||
1002 | val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR); | ||
1003 | |||
1004 | val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR | | ||
1005 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | ||
1006 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | ||
1007 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | ||
1008 | |||
1009 | writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR); | ||
1010 | |||
1011 | if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR) | ||
1012 | dev_err(&spi->dev, "RX overrun\n"); | ||
1013 | if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR) | ||
1014 | dev_err(&spi->dev, "RX underrun\n"); | ||
1015 | if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR) | ||
1016 | dev_err(&spi->dev, "TX overrun\n"); | ||
1017 | if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR) | ||
1018 | dev_err(&spi->dev, "TX underrun\n"); | ||
1019 | |||
1020 | return IRQ_HANDLED; | ||
1021 | } | ||
1022 | |||
1023 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) | 926 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
1024 | { | 927 | { |
1025 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | 928 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
@@ -1028,12 +931,12 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) | |||
1028 | 931 | ||
1029 | sdd->cur_speed = 0; | 932 | sdd->cur_speed = 0; |
1030 | 933 | ||
1031 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | 934 | S3C64XX_SPI_DEACT(sdd); |
1032 | 935 | ||
1033 | /* Disable Interrupts - we use Polling if not DMA mode */ | 936 | /* Disable Interrupts - we use Polling if not DMA mode */ |
1034 | writel(0, regs + S3C64XX_SPI_INT_EN); | 937 | writel(0, regs + S3C64XX_SPI_INT_EN); |
1035 | 938 | ||
1036 | if (!sdd->port_conf->clk_from_cmu) | 939 | if (!sci->clk_from_cmu) |
1037 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, | 940 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
1038 | regs + S3C64XX_SPI_CLK_CFG); | 941 | regs + S3C64XX_SPI_CLK_CFG); |
1039 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | 942 | writel(0, regs + S3C64XX_SPI_MODE_CFG); |
@@ -1054,165 +957,44 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) | |||
1054 | flush_fifo(sdd); | 957 | flush_fifo(sdd); |
1055 | } | 958 | } |
1056 | 959 | ||
1057 | static int s3c64xx_spi_get_dmares( | 960 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) |
1058 | struct s3c64xx_spi_driver_data *sdd, bool tx) | ||
1059 | { | ||
1060 | struct platform_device *pdev = sdd->pdev; | ||
1061 | struct s3c64xx_spi_dma_data *dma_data; | ||
1062 | struct property *prop; | ||
1063 | struct resource *res; | ||
1064 | char prop_name[15], *chan_str; | ||
1065 | |||
1066 | if (tx) { | ||
1067 | dma_data = &sdd->tx_dma; | ||
1068 | dma_data->direction = DMA_MEM_TO_DEV; | ||
1069 | chan_str = "tx"; | ||
1070 | } else { | ||
1071 | dma_data = &sdd->rx_dma; | ||
1072 | dma_data->direction = DMA_DEV_TO_MEM; | ||
1073 | chan_str = "rx"; | ||
1074 | } | ||
1075 | |||
1076 | if (!sdd->pdev->dev.of_node) { | ||
1077 | res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1); | ||
1078 | if (!res) { | ||
1079 | dev_err(&pdev->dev, "Unable to get SPI-%s dma " | ||
1080 | "resource\n", chan_str); | ||
1081 | return -ENXIO; | ||
1082 | } | ||
1083 | dma_data->dmach = res->start; | ||
1084 | return 0; | ||
1085 | } | ||
1086 | |||
1087 | sprintf(prop_name, "%s-dma-channel", chan_str); | ||
1088 | prop = of_find_property(pdev->dev.of_node, prop_name, NULL); | ||
1089 | if (!prop) { | ||
1090 | dev_err(&pdev->dev, "%s dma channel property not specified\n", | ||
1091 | chan_str); | ||
1092 | return -ENXIO; | ||
1093 | } | ||
1094 | |||
1095 | dma_data->dmach = DMACH_DT_PROP; | ||
1096 | dma_data->dma_prop = prop; | ||
1097 | return 0; | ||
1098 | } | ||
1099 | |||
1100 | #ifdef CONFIG_OF | ||
1101 | static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) | ||
1102 | { | ||
1103 | struct device *dev = &sdd->pdev->dev; | ||
1104 | int idx, gpio, ret; | ||
1105 | |||
1106 | /* find gpios for mosi, miso and clock lines */ | ||
1107 | for (idx = 0; idx < 3; idx++) { | ||
1108 | gpio = of_get_gpio(dev->of_node, idx); | ||
1109 | if (!gpio_is_valid(gpio)) { | ||
1110 | dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio); | ||
1111 | goto free_gpio; | ||
1112 | } | ||
1113 | sdd->gpios[idx] = gpio; | ||
1114 | ret = gpio_request(gpio, "spi-bus"); | ||
1115 | if (ret) { | ||
1116 | dev_err(dev, "gpio [%d] request failed: %d\n", | ||
1117 | gpio, ret); | ||
1118 | goto free_gpio; | ||
1119 | } | ||
1120 | } | ||
1121 | return 0; | ||
1122 | |||
1123 | free_gpio: | ||
1124 | while (--idx >= 0) | ||
1125 | gpio_free(sdd->gpios[idx]); | ||
1126 | return -EINVAL; | ||
1127 | } | ||
1128 | |||
1129 | static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) | ||
1130 | { | ||
1131 | unsigned int idx; | ||
1132 | for (idx = 0; idx < 3; idx++) | ||
1133 | gpio_free(sdd->gpios[idx]); | ||
1134 | } | ||
1135 | |||
1136 | static struct s3c64xx_spi_info * s3c64xx_spi_parse_dt( | ||
1137 | struct device *dev) | ||
1138 | { | 961 | { |
962 | struct resource *mem_res, *dmatx_res, *dmarx_res; | ||
963 | struct s3c64xx_spi_driver_data *sdd; | ||
1139 | struct s3c64xx_spi_info *sci; | 964 | struct s3c64xx_spi_info *sci; |
1140 | u32 temp; | 965 | struct spi_master *master; |
1141 | 966 | int ret; | |
1142 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | ||
1143 | if (!sci) { | ||
1144 | dev_err(dev, "memory allocation for spi_info failed\n"); | ||
1145 | return ERR_PTR(-ENOMEM); | ||
1146 | } | ||
1147 | 967 | ||
1148 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | 968 | if (pdev->id < 0) { |
1149 | dev_warn(dev, "spi bus clock parent not specified, using " | 969 | dev_err(&pdev->dev, |
1150 | "clock at index 0 as parent\n"); | 970 | "Invalid platform device id-%d\n", pdev->id); |
1151 | sci->src_clk_nr = 0; | 971 | return -ENODEV; |
1152 | } else { | ||
1153 | sci->src_clk_nr = temp; | ||
1154 | } | 972 | } |
1155 | 973 | ||
1156 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | 974 | if (pdev->dev.platform_data == NULL) { |
1157 | dev_warn(dev, "number of chip select lines not specified, " | 975 | dev_err(&pdev->dev, "platform_data missing!\n"); |
1158 | "assuming 1 chip select line\n"); | 976 | return -ENODEV; |
1159 | sci->num_cs = 1; | ||
1160 | } else { | ||
1161 | sci->num_cs = temp; | ||
1162 | } | 977 | } |
1163 | 978 | ||
1164 | return sci; | 979 | sci = pdev->dev.platform_data; |
1165 | } | 980 | if (!sci->src_clk_name) { |
1166 | #else | 981 | dev_err(&pdev->dev, |
1167 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | 982 | "Board init must call s3c64xx_spi_set_info()\n"); |
1168 | { | 983 | return -EINVAL; |
1169 | return dev->platform_data; | ||
1170 | } | ||
1171 | |||
1172 | static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) | ||
1173 | { | ||
1174 | return -EINVAL; | ||
1175 | } | ||
1176 | |||
1177 | static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) | ||
1178 | { | ||
1179 | } | ||
1180 | #endif | ||
1181 | |||
1182 | static const struct of_device_id s3c64xx_spi_dt_match[]; | ||
1183 | |||
1184 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( | ||
1185 | struct platform_device *pdev) | ||
1186 | { | ||
1187 | #ifdef CONFIG_OF | ||
1188 | if (pdev->dev.of_node) { | ||
1189 | const struct of_device_id *match; | ||
1190 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | ||
1191 | return (struct s3c64xx_spi_port_config *)match->data; | ||
1192 | } | 984 | } |
1193 | #endif | ||
1194 | return (struct s3c64xx_spi_port_config *) | ||
1195 | platform_get_device_id(pdev)->driver_data; | ||
1196 | } | ||
1197 | 985 | ||
1198 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) | 986 | /* Check for availability of necessary resource */ |
1199 | { | ||
1200 | struct resource *mem_res; | ||
1201 | struct s3c64xx_spi_driver_data *sdd; | ||
1202 | struct s3c64xx_spi_info *sci = pdev->dev.platform_data; | ||
1203 | struct spi_master *master; | ||
1204 | int ret, irq; | ||
1205 | char clk_name[16]; | ||
1206 | 987 | ||
1207 | if (!sci && pdev->dev.of_node) { | 988 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1208 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | 989 | if (dmatx_res == NULL) { |
1209 | if (IS_ERR(sci)) | 990 | dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); |
1210 | return PTR_ERR(sci); | 991 | return -ENXIO; |
1211 | } | 992 | } |
1212 | 993 | ||
1213 | if (!sci) { | 994 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
1214 | dev_err(&pdev->dev, "platform_data missing!\n"); | 995 | if (dmarx_res == NULL) { |
1215 | return -ENODEV; | 996 | dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); |
997 | return -ENXIO; | ||
1216 | } | 998 | } |
1217 | 999 | ||
1218 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1000 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -1221,12 +1003,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1221 | return -ENXIO; | 1003 | return -ENXIO; |
1222 | } | 1004 | } |
1223 | 1005 | ||
1224 | irq = platform_get_irq(pdev, 0); | ||
1225 | if (irq < 0) { | ||
1226 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | ||
1227 | return irq; | ||
1228 | } | ||
1229 | |||
1230 | master = spi_alloc_master(&pdev->dev, | 1006 | master = spi_alloc_master(&pdev->dev, |
1231 | sizeof(struct s3c64xx_spi_driver_data)); | 1007 | sizeof(struct s3c64xx_spi_driver_data)); |
1232 | if (master == NULL) { | 1008 | if (master == NULL) { |
@@ -1237,56 +1013,38 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1237 | platform_set_drvdata(pdev, master); | 1013 | platform_set_drvdata(pdev, master); |
1238 | 1014 | ||
1239 | sdd = spi_master_get_devdata(master); | 1015 | sdd = spi_master_get_devdata(master); |
1240 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); | ||
1241 | sdd->master = master; | 1016 | sdd->master = master; |
1242 | sdd->cntrlr_info = sci; | 1017 | sdd->cntrlr_info = sci; |
1243 | sdd->pdev = pdev; | 1018 | sdd->pdev = pdev; |
1244 | sdd->sfr_start = mem_res->start; | 1019 | sdd->sfr_start = mem_res->start; |
1245 | if (pdev->dev.of_node) { | 1020 | sdd->tx_dmach = dmatx_res->start; |
1246 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | 1021 | sdd->rx_dmach = dmarx_res->start; |
1247 | if (ret < 0) { | ||
1248 | dev_err(&pdev->dev, "failed to get alias id, " | ||
1249 | "errno %d\n", ret); | ||
1250 | goto err0; | ||
1251 | } | ||
1252 | sdd->port_id = ret; | ||
1253 | } else { | ||
1254 | sdd->port_id = pdev->id; | ||
1255 | } | ||
1256 | 1022 | ||
1257 | sdd->cur_bpw = 8; | 1023 | sdd->cur_bpw = 8; |
1258 | 1024 | ||
1259 | ret = s3c64xx_spi_get_dmares(sdd, true); | 1025 | master->bus_num = pdev->id; |
1260 | if (ret) | ||
1261 | goto err0; | ||
1262 | |||
1263 | ret = s3c64xx_spi_get_dmares(sdd, false); | ||
1264 | if (ret) | ||
1265 | goto err0; | ||
1266 | |||
1267 | master->dev.of_node = pdev->dev.of_node; | ||
1268 | master->bus_num = sdd->port_id; | ||
1269 | master->setup = s3c64xx_spi_setup; | 1026 | master->setup = s3c64xx_spi_setup; |
1270 | master->cleanup = s3c64xx_spi_cleanup; | 1027 | master->transfer = s3c64xx_spi_transfer; |
1271 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; | ||
1272 | master->transfer_one_message = s3c64xx_spi_transfer_one_message; | ||
1273 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; | ||
1274 | master->num_chipselect = sci->num_cs; | 1028 | master->num_chipselect = sci->num_cs; |
1275 | master->dma_alignment = 8; | 1029 | master->dma_alignment = 8; |
1276 | /* the spi->mode bits understood by this driver: */ | 1030 | /* the spi->mode bits understood by this driver: */ |
1277 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 1031 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1278 | 1032 | ||
1279 | sdd->regs = devm_request_and_ioremap(&pdev->dev, mem_res); | 1033 | if (request_mem_region(mem_res->start, |
1034 | resource_size(mem_res), pdev->name) == NULL) { | ||
1035 | dev_err(&pdev->dev, "Req mem region failed\n"); | ||
1036 | ret = -ENXIO; | ||
1037 | goto err0; | ||
1038 | } | ||
1039 | |||
1040 | sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); | ||
1280 | if (sdd->regs == NULL) { | 1041 | if (sdd->regs == NULL) { |
1281 | dev_err(&pdev->dev, "Unable to remap IO\n"); | 1042 | dev_err(&pdev->dev, "Unable to remap IO\n"); |
1282 | ret = -ENXIO; | 1043 | ret = -ENXIO; |
1283 | goto err1; | 1044 | goto err1; |
1284 | } | 1045 | } |
1285 | 1046 | ||
1286 | if (!sci->cfg_gpio && pdev->dev.of_node) { | 1047 | if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { |
1287 | if (s3c64xx_spi_parse_dt_gpio(sdd)) | ||
1288 | return -EBUSY; | ||
1289 | } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { | ||
1290 | dev_err(&pdev->dev, "Unable to config gpio\n"); | 1048 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1291 | ret = -EBUSY; | 1049 | ret = -EBUSY; |
1292 | goto err2; | 1050 | goto err2; |
@@ -1300,45 +1058,43 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1300 | goto err3; | 1058 | goto err3; |
1301 | } | 1059 | } |
1302 | 1060 | ||
1303 | if (clk_prepare_enable(sdd->clk)) { | 1061 | if (clk_enable(sdd->clk)) { |
1304 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); | 1062 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
1305 | ret = -EBUSY; | 1063 | ret = -EBUSY; |
1306 | goto err4; | 1064 | goto err4; |
1307 | } | 1065 | } |
1308 | 1066 | ||
1309 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); | 1067 | sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); |
1310 | sdd->src_clk = clk_get(&pdev->dev, clk_name); | ||
1311 | if (IS_ERR(sdd->src_clk)) { | 1068 | if (IS_ERR(sdd->src_clk)) { |
1312 | dev_err(&pdev->dev, | 1069 | dev_err(&pdev->dev, |
1313 | "Unable to acquire clock '%s'\n", clk_name); | 1070 | "Unable to acquire clock '%s'\n", sci->src_clk_name); |
1314 | ret = PTR_ERR(sdd->src_clk); | 1071 | ret = PTR_ERR(sdd->src_clk); |
1315 | goto err5; | 1072 | goto err5; |
1316 | } | 1073 | } |
1317 | 1074 | ||
1318 | if (clk_prepare_enable(sdd->src_clk)) { | 1075 | if (clk_enable(sdd->src_clk)) { |
1319 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); | 1076 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", |
1077 | sci->src_clk_name); | ||
1320 | ret = -EBUSY; | 1078 | ret = -EBUSY; |
1321 | goto err6; | 1079 | goto err6; |
1322 | } | 1080 | } |
1323 | 1081 | ||
1082 | sdd->workqueue = create_singlethread_workqueue( | ||
1083 | dev_name(master->dev.parent)); | ||
1084 | if (sdd->workqueue == NULL) { | ||
1085 | dev_err(&pdev->dev, "Unable to create workqueue\n"); | ||
1086 | ret = -ENOMEM; | ||
1087 | goto err7; | ||
1088 | } | ||
1089 | |||
1324 | /* Setup Deufult Mode */ | 1090 | /* Setup Deufult Mode */ |
1325 | s3c64xx_spi_hwinit(sdd, sdd->port_id); | 1091 | s3c64xx_spi_hwinit(sdd, pdev->id); |
1326 | 1092 | ||
1327 | spin_lock_init(&sdd->lock); | 1093 | spin_lock_init(&sdd->lock); |
1328 | init_completion(&sdd->xfer_completion); | 1094 | init_completion(&sdd->xfer_completion); |
1095 | INIT_WORK(&sdd->work, s3c64xx_spi_work); | ||
1329 | INIT_LIST_HEAD(&sdd->queue); | 1096 | INIT_LIST_HEAD(&sdd->queue); |
1330 | 1097 | ||
1331 | ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd); | ||
1332 | if (ret != 0) { | ||
1333 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | ||
1334 | irq, ret); | ||
1335 | goto err7; | ||
1336 | } | ||
1337 | |||
1338 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | ||
1339 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | ||
1340 | sdd->regs + S3C64XX_SPI_INT_EN); | ||
1341 | |||
1342 | if (spi_register_master(master)) { | 1098 | if (spi_register_master(master)) { |
1343 | dev_err(&pdev->dev, "cannot register SPI master\n"); | 1099 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
1344 | ret = -EBUSY; | 1100 | ret = -EBUSY; |
@@ -1347,30 +1103,28 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1347 | 1103 | ||
1348 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " | 1104 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " |
1349 | "with %d Slaves attached\n", | 1105 | "with %d Slaves attached\n", |
1350 | sdd->port_id, master->num_chipselect); | 1106 | pdev->id, master->num_chipselect); |
1351 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", | 1107 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", |
1352 | mem_res->end, mem_res->start, | 1108 | mem_res->end, mem_res->start, |
1353 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); | 1109 | sdd->rx_dmach, sdd->tx_dmach); |
1354 | |||
1355 | pm_runtime_enable(&pdev->dev); | ||
1356 | 1110 | ||
1357 | return 0; | 1111 | return 0; |
1358 | 1112 | ||
1359 | err8: | 1113 | err8: |
1360 | free_irq(irq, sdd); | 1114 | destroy_workqueue(sdd->workqueue); |
1361 | err7: | 1115 | err7: |
1362 | clk_disable_unprepare(sdd->src_clk); | 1116 | clk_disable(sdd->src_clk); |
1363 | err6: | 1117 | err6: |
1364 | clk_put(sdd->src_clk); | 1118 | clk_put(sdd->src_clk); |
1365 | err5: | 1119 | err5: |
1366 | clk_disable_unprepare(sdd->clk); | 1120 | clk_disable(sdd->clk); |
1367 | err4: | 1121 | err4: |
1368 | clk_put(sdd->clk); | 1122 | clk_put(sdd->clk); |
1369 | err3: | 1123 | err3: |
1370 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) | ||
1371 | s3c64xx_spi_dt_gpio_free(sdd); | ||
1372 | err2: | 1124 | err2: |
1125 | iounmap((void *) sdd->regs); | ||
1373 | err1: | 1126 | err1: |
1127 | release_mem_region(mem_res->start, resource_size(mem_res)); | ||
1374 | err0: | 1128 | err0: |
1375 | platform_set_drvdata(pdev, NULL); | 1129 | platform_set_drvdata(pdev, NULL); |
1376 | spi_master_put(master); | 1130 | spi_master_put(master); |
@@ -1382,23 +1136,31 @@ static int s3c64xx_spi_remove(struct platform_device *pdev) | |||
1382 | { | 1136 | { |
1383 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | 1137 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
1384 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | 1138 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1139 | struct resource *mem_res; | ||
1140 | unsigned long flags; | ||
1385 | 1141 | ||
1386 | pm_runtime_disable(&pdev->dev); | 1142 | spin_lock_irqsave(&sdd->lock, flags); |
1143 | sdd->state |= SUSPND; | ||
1144 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
1387 | 1145 | ||
1388 | spi_unregister_master(master); | 1146 | while (sdd->state & SPIBUSY) |
1147 | msleep(10); | ||
1389 | 1148 | ||
1390 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); | 1149 | spi_unregister_master(master); |
1391 | 1150 | ||
1392 | free_irq(platform_get_irq(pdev, 0), sdd); | 1151 | destroy_workqueue(sdd->workqueue); |
1393 | 1152 | ||
1394 | clk_disable_unprepare(sdd->src_clk); | 1153 | clk_disable(sdd->src_clk); |
1395 | clk_put(sdd->src_clk); | 1154 | clk_put(sdd->src_clk); |
1396 | 1155 | ||
1397 | clk_disable_unprepare(sdd->clk); | 1156 | clk_disable(sdd->clk); |
1398 | clk_put(sdd->clk); | 1157 | clk_put(sdd->clk); |
1399 | 1158 | ||
1400 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) | 1159 | iounmap((void *) sdd->regs); |
1401 | s3c64xx_spi_dt_gpio_free(sdd); | 1160 | |
1161 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1162 | if (mem_res != NULL) | ||
1163 | release_mem_region(mem_res->start, resource_size(mem_res)); | ||
1402 | 1164 | ||
1403 | platform_set_drvdata(pdev, NULL); | 1165 | platform_set_drvdata(pdev, NULL); |
1404 | spi_master_put(master); | 1166 | spi_master_put(master); |
@@ -1407,161 +1169,62 @@ static int s3c64xx_spi_remove(struct platform_device *pdev) | |||
1407 | } | 1169 | } |
1408 | 1170 | ||
1409 | #ifdef CONFIG_PM | 1171 | #ifdef CONFIG_PM |
1410 | static int s3c64xx_spi_suspend(struct device *dev) | 1172 | static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state) |
1411 | { | 1173 | { |
1412 | struct spi_master *master = dev_get_drvdata(dev); | 1174 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
1413 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | 1175 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1176 | unsigned long flags; | ||
1414 | 1177 | ||
1415 | spi_master_suspend(master); | 1178 | spin_lock_irqsave(&sdd->lock, flags); |
1179 | sdd->state |= SUSPND; | ||
1180 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
1416 | 1181 | ||
1417 | /* Disable the clock */ | 1182 | while (sdd->state & SPIBUSY) |
1418 | clk_disable_unprepare(sdd->src_clk); | 1183 | msleep(10); |
1419 | clk_disable_unprepare(sdd->clk); | ||
1420 | 1184 | ||
1421 | if (!sdd->cntrlr_info->cfg_gpio && dev->of_node) | 1185 | /* Disable the clock */ |
1422 | s3c64xx_spi_dt_gpio_free(sdd); | 1186 | clk_disable(sdd->src_clk); |
1187 | clk_disable(sdd->clk); | ||
1423 | 1188 | ||
1424 | sdd->cur_speed = 0; /* Output Clock is stopped */ | 1189 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
1425 | 1190 | ||
1426 | return 0; | 1191 | return 0; |
1427 | } | 1192 | } |
1428 | 1193 | ||
1429 | static int s3c64xx_spi_resume(struct device *dev) | 1194 | static int s3c64xx_spi_resume(struct platform_device *pdev) |
1430 | { | 1195 | { |
1431 | struct spi_master *master = dev_get_drvdata(dev); | 1196 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
1432 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | 1197 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1433 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; | 1198 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
1199 | unsigned long flags; | ||
1434 | 1200 | ||
1435 | if (!sci->cfg_gpio && dev->of_node) | 1201 | sci->cfg_gpio(pdev); |
1436 | s3c64xx_spi_parse_dt_gpio(sdd); | ||
1437 | else | ||
1438 | sci->cfg_gpio(); | ||
1439 | 1202 | ||
1440 | /* Enable the clock */ | 1203 | /* Enable the clock */ |
1441 | clk_prepare_enable(sdd->src_clk); | 1204 | clk_enable(sdd->src_clk); |
1442 | clk_prepare_enable(sdd->clk); | 1205 | clk_enable(sdd->clk); |
1443 | 1206 | ||
1444 | s3c64xx_spi_hwinit(sdd, sdd->port_id); | 1207 | s3c64xx_spi_hwinit(sdd, pdev->id); |
1445 | 1208 | ||
1446 | spi_master_resume(master); | 1209 | spin_lock_irqsave(&sdd->lock, flags); |
1210 | sdd->state &= ~SUSPND; | ||
1211 | spin_unlock_irqrestore(&sdd->lock, flags); | ||
1447 | 1212 | ||
1448 | return 0; | 1213 | return 0; |
1449 | } | 1214 | } |
1215 | #else | ||
1216 | #define s3c64xx_spi_suspend NULL | ||
1217 | #define s3c64xx_spi_resume NULL | ||
1450 | #endif /* CONFIG_PM */ | 1218 | #endif /* CONFIG_PM */ |
1451 | 1219 | ||
1452 | #ifdef CONFIG_PM_RUNTIME | ||
1453 | static int s3c64xx_spi_runtime_suspend(struct device *dev) | ||
1454 | { | ||
1455 | struct spi_master *master = dev_get_drvdata(dev); | ||
1456 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | ||
1457 | |||
1458 | clk_disable_unprepare(sdd->clk); | ||
1459 | clk_disable_unprepare(sdd->src_clk); | ||
1460 | |||
1461 | return 0; | ||
1462 | } | ||
1463 | |||
1464 | static int s3c64xx_spi_runtime_resume(struct device *dev) | ||
1465 | { | ||
1466 | struct spi_master *master = dev_get_drvdata(dev); | ||
1467 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | ||
1468 | |||
1469 | clk_prepare_enable(sdd->src_clk); | ||
1470 | clk_prepare_enable(sdd->clk); | ||
1471 | |||
1472 | return 0; | ||
1473 | } | ||
1474 | #endif /* CONFIG_PM_RUNTIME */ | ||
1475 | |||
1476 | static const struct dev_pm_ops s3c64xx_spi_pm = { | ||
1477 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | ||
1478 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, | ||
1479 | s3c64xx_spi_runtime_resume, NULL) | ||
1480 | }; | ||
1481 | |||
1482 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { | ||
1483 | .fifo_lvl_mask = { 0x7f }, | ||
1484 | .rx_lvl_offset = 13, | ||
1485 | .tx_st_done = 21, | ||
1486 | .high_speed = true, | ||
1487 | }; | ||
1488 | |||
1489 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { | ||
1490 | .fifo_lvl_mask = { 0x7f, 0x7F }, | ||
1491 | .rx_lvl_offset = 13, | ||
1492 | .tx_st_done = 21, | ||
1493 | }; | ||
1494 | |||
1495 | static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { | ||
1496 | .fifo_lvl_mask = { 0x1ff, 0x7F }, | ||
1497 | .rx_lvl_offset = 15, | ||
1498 | .tx_st_done = 25, | ||
1499 | }; | ||
1500 | |||
1501 | static struct s3c64xx_spi_port_config s5pc100_spi_port_config = { | ||
1502 | .fifo_lvl_mask = { 0x7f, 0x7F }, | ||
1503 | .rx_lvl_offset = 13, | ||
1504 | .tx_st_done = 21, | ||
1505 | .high_speed = true, | ||
1506 | }; | ||
1507 | |||
1508 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { | ||
1509 | .fifo_lvl_mask = { 0x1ff, 0x7F }, | ||
1510 | .rx_lvl_offset = 15, | ||
1511 | .tx_st_done = 25, | ||
1512 | .high_speed = true, | ||
1513 | }; | ||
1514 | |||
1515 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { | ||
1516 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, | ||
1517 | .rx_lvl_offset = 15, | ||
1518 | .tx_st_done = 25, | ||
1519 | .high_speed = true, | ||
1520 | .clk_from_cmu = true, | ||
1521 | }; | ||
1522 | |||
1523 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { | ||
1524 | { | ||
1525 | .name = "s3c2443-spi", | ||
1526 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | ||
1527 | }, { | ||
1528 | .name = "s3c6410-spi", | ||
1529 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | ||
1530 | }, { | ||
1531 | .name = "s5p64x0-spi", | ||
1532 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, | ||
1533 | }, { | ||
1534 | .name = "s5pc100-spi", | ||
1535 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, | ||
1536 | }, { | ||
1537 | .name = "s5pv210-spi", | ||
1538 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, | ||
1539 | }, { | ||
1540 | .name = "exynos4210-spi", | ||
1541 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, | ||
1542 | }, | ||
1543 | { }, | ||
1544 | }; | ||
1545 | |||
1546 | #ifdef CONFIG_OF | ||
1547 | static const struct of_device_id s3c64xx_spi_dt_match[] = { | ||
1548 | { .compatible = "samsung,exynos4210-spi", | ||
1549 | .data = (void *)&exynos4_spi_port_config, | ||
1550 | }, | ||
1551 | { }, | ||
1552 | }; | ||
1553 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | ||
1554 | #endif /* CONFIG_OF */ | ||
1555 | |||
1556 | static struct platform_driver s3c64xx_spi_driver = { | 1220 | static struct platform_driver s3c64xx_spi_driver = { |
1557 | .driver = { | 1221 | .driver = { |
1558 | .name = "s3c64xx-spi", | 1222 | .name = "s3c64xx-spi", |
1559 | .owner = THIS_MODULE, | 1223 | .owner = THIS_MODULE, |
1560 | .pm = &s3c64xx_spi_pm, | ||
1561 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), | ||
1562 | }, | 1224 | }, |
1563 | .remove = s3c64xx_spi_remove, | 1225 | .remove = s3c64xx_spi_remove, |
1564 | .id_table = s3c64xx_spi_driver_ids, | 1226 | .suspend = s3c64xx_spi_suspend, |
1227 | .resume = s3c64xx_spi_resume, | ||
1565 | }; | 1228 | }; |
1566 | MODULE_ALIAS("platform:s3c64xx-spi"); | 1229 | MODULE_ALIAS("platform:s3c64xx-spi"); |
1567 | 1230 | ||
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c deleted file mode 100644 index 9eda21d739c..00000000000 --- a/drivers/spi/spi-sc18is602.c +++ /dev/null | |||
@@ -1,364 +0,0 @@ | |||
1 | /* | ||
2 | * NXP SC18IS602/603 SPI driver | ||
3 | * | ||
4 | * Copyright (C) Guenter Roeck <linux@roeck-us.net> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/err.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/spi/spi.h> | ||
25 | #include <linux/i2c.h> | ||
26 | #include <linux/delay.h> | ||
27 | #include <linux/pm_runtime.h> | ||
28 | #include <linux/of.h> | ||
29 | #include <linux/platform_data/sc18is602.h> | ||
30 | |||
31 | enum chips { sc18is602, sc18is602b, sc18is603 }; | ||
32 | |||
33 | #define SC18IS602_BUFSIZ 200 | ||
34 | #define SC18IS602_CLOCK 7372000 | ||
35 | |||
36 | #define SC18IS602_MODE_CPHA BIT(2) | ||
37 | #define SC18IS602_MODE_CPOL BIT(3) | ||
38 | #define SC18IS602_MODE_LSB_FIRST BIT(5) | ||
39 | #define SC18IS602_MODE_CLOCK_DIV_4 0x0 | ||
40 | #define SC18IS602_MODE_CLOCK_DIV_16 0x1 | ||
41 | #define SC18IS602_MODE_CLOCK_DIV_64 0x2 | ||
42 | #define SC18IS602_MODE_CLOCK_DIV_128 0x3 | ||
43 | |||
44 | struct sc18is602 { | ||
45 | struct spi_master *master; | ||
46 | struct device *dev; | ||
47 | u8 ctrl; | ||
48 | u32 freq; | ||
49 | u32 speed; | ||
50 | |||
51 | /* I2C data */ | ||
52 | struct i2c_client *client; | ||
53 | enum chips id; | ||
54 | u8 buffer[SC18IS602_BUFSIZ + 1]; | ||
55 | int tlen; /* Data queued for tx in buffer */ | ||
56 | int rindex; /* Receive data index in buffer */ | ||
57 | }; | ||
58 | |||
59 | static int sc18is602_wait_ready(struct sc18is602 *hw, int len) | ||
60 | { | ||
61 | int i, err; | ||
62 | int usecs = 1000000 * len / hw->speed + 1; | ||
63 | u8 dummy[1]; | ||
64 | |||
65 | for (i = 0; i < 10; i++) { | ||
66 | err = i2c_master_recv(hw->client, dummy, 1); | ||
67 | if (err >= 0) | ||
68 | return 0; | ||
69 | usleep_range(usecs, usecs * 2); | ||
70 | } | ||
71 | return -ETIMEDOUT; | ||
72 | } | ||
73 | |||
74 | static int sc18is602_txrx(struct sc18is602 *hw, struct spi_message *msg, | ||
75 | struct spi_transfer *t, bool do_transfer) | ||
76 | { | ||
77 | unsigned int len = t->len; | ||
78 | int ret; | ||
79 | |||
80 | if (hw->tlen == 0) { | ||
81 | /* First byte (I2C command) is chip select */ | ||
82 | hw->buffer[0] = 1 << msg->spi->chip_select; | ||
83 | hw->tlen = 1; | ||
84 | hw->rindex = 0; | ||
85 | } | ||
86 | /* | ||
87 | * We can not immediately send data to the chip, since each I2C message | ||
88 | * resembles a full SPI message (from CS active to CS inactive). | ||
89 | * Enqueue messages up to the first read or until do_transfer is true. | ||
90 | */ | ||
91 | if (t->tx_buf) { | ||
92 | memcpy(&hw->buffer[hw->tlen], t->tx_buf, len); | ||
93 | hw->tlen += len; | ||
94 | if (t->rx_buf) | ||
95 | do_transfer = true; | ||
96 | else | ||
97 | hw->rindex = hw->tlen - 1; | ||
98 | } else if (t->rx_buf) { | ||
99 | /* | ||
100 | * For receive-only transfers we still need to perform a dummy | ||
101 | * write to receive data from the SPI chip. | ||
102 | * Read data starts at the end of transmit data (minus 1 to | ||
103 | * account for CS). | ||
104 | */ | ||
105 | hw->rindex = hw->tlen - 1; | ||
106 | memset(&hw->buffer[hw->tlen], 0, len); | ||
107 | hw->tlen += len; | ||
108 | do_transfer = true; | ||
109 | } | ||
110 | |||
111 | if (do_transfer && hw->tlen > 1) { | ||
112 | ret = sc18is602_wait_ready(hw, SC18IS602_BUFSIZ); | ||
113 | if (ret < 0) | ||
114 | return ret; | ||
115 | ret = i2c_master_send(hw->client, hw->buffer, hw->tlen); | ||
116 | if (ret < 0) | ||
117 | return ret; | ||
118 | if (ret != hw->tlen) | ||
119 | return -EIO; | ||
120 | |||
121 | if (t->rx_buf) { | ||
122 | int rlen = hw->rindex + len; | ||
123 | |||
124 | ret = sc18is602_wait_ready(hw, hw->tlen); | ||
125 | if (ret < 0) | ||
126 | return ret; | ||
127 | ret = i2c_master_recv(hw->client, hw->buffer, rlen); | ||
128 | if (ret < 0) | ||
129 | return ret; | ||
130 | if (ret != rlen) | ||
131 | return -EIO; | ||
132 | memcpy(t->rx_buf, &hw->buffer[hw->rindex], len); | ||
133 | } | ||
134 | hw->tlen = 0; | ||
135 | } | ||
136 | return len; | ||
137 | } | ||
138 | |||
139 | static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode) | ||
140 | { | ||
141 | u8 ctrl = 0; | ||
142 | int ret; | ||
143 | |||
144 | if (mode & SPI_CPHA) | ||
145 | ctrl |= SC18IS602_MODE_CPHA; | ||
146 | if (mode & SPI_CPOL) | ||
147 | ctrl |= SC18IS602_MODE_CPOL; | ||
148 | if (mode & SPI_LSB_FIRST) | ||
149 | ctrl |= SC18IS602_MODE_LSB_FIRST; | ||
150 | |||
151 | /* Find the closest clock speed */ | ||
152 | if (hz >= hw->freq / 4) { | ||
153 | ctrl |= SC18IS602_MODE_CLOCK_DIV_4; | ||
154 | hw->speed = hw->freq / 4; | ||
155 | } else if (hz >= hw->freq / 16) { | ||
156 | ctrl |= SC18IS602_MODE_CLOCK_DIV_16; | ||
157 | hw->speed = hw->freq / 16; | ||
158 | } else if (hz >= hw->freq / 64) { | ||
159 | ctrl |= SC18IS602_MODE_CLOCK_DIV_64; | ||
160 | hw->speed = hw->freq / 64; | ||
161 | } else { | ||
162 | ctrl |= SC18IS602_MODE_CLOCK_DIV_128; | ||
163 | hw->speed = hw->freq / 128; | ||
164 | } | ||
165 | |||
166 | /* | ||
167 | * Don't do anything if the control value did not change. The initial | ||
168 | * value of 0xff for hw->ctrl ensures that the correct mode will be set | ||
169 | * with the first call to this function. | ||
170 | */ | ||
171 | if (ctrl == hw->ctrl) | ||
172 | return 0; | ||
173 | |||
174 | ret = i2c_smbus_write_byte_data(hw->client, 0xf0, ctrl); | ||
175 | if (ret < 0) | ||
176 | return ret; | ||
177 | |||
178 | hw->ctrl = ctrl; | ||
179 | |||
180 | return 0; | ||
181 | } | ||
182 | |||
183 | static int sc18is602_check_transfer(struct spi_device *spi, | ||
184 | struct spi_transfer *t, int tlen) | ||
185 | { | ||
186 | int bpw; | ||
187 | uint32_t hz; | ||
188 | |||
189 | if (t && t->len + tlen > SC18IS602_BUFSIZ) | ||
190 | return -EINVAL; | ||
191 | |||
192 | bpw = spi->bits_per_word; | ||
193 | if (t && t->bits_per_word) | ||
194 | bpw = t->bits_per_word; | ||
195 | if (bpw != 8) | ||
196 | return -EINVAL; | ||
197 | |||
198 | hz = spi->max_speed_hz; | ||
199 | if (t && t->speed_hz) | ||
200 | hz = t->speed_hz; | ||
201 | if (hz == 0) | ||
202 | return -EINVAL; | ||
203 | |||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | static int sc18is602_transfer_one(struct spi_master *master, | ||
208 | struct spi_message *m) | ||
209 | { | ||
210 | struct sc18is602 *hw = spi_master_get_devdata(master); | ||
211 | struct spi_device *spi = m->spi; | ||
212 | struct spi_transfer *t; | ||
213 | int status = 0; | ||
214 | |||
215 | /* SC18IS602 does not support CS2 */ | ||
216 | if (hw->id == sc18is602 && spi->chip_select == 2) { | ||
217 | status = -ENXIO; | ||
218 | goto error; | ||
219 | } | ||
220 | |||
221 | hw->tlen = 0; | ||
222 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
223 | u32 hz = t->speed_hz ? : spi->max_speed_hz; | ||
224 | bool do_transfer; | ||
225 | |||
226 | status = sc18is602_check_transfer(spi, t, hw->tlen); | ||
227 | if (status < 0) | ||
228 | break; | ||
229 | |||
230 | status = sc18is602_setup_transfer(hw, hz, spi->mode); | ||
231 | if (status < 0) | ||
232 | break; | ||
233 | |||
234 | do_transfer = t->cs_change || list_is_last(&t->transfer_list, | ||
235 | &m->transfers); | ||
236 | |||
237 | if (t->len) { | ||
238 | status = sc18is602_txrx(hw, m, t, do_transfer); | ||
239 | if (status < 0) | ||
240 | break; | ||
241 | m->actual_length += status; | ||
242 | } | ||
243 | status = 0; | ||
244 | |||
245 | if (t->delay_usecs) | ||
246 | udelay(t->delay_usecs); | ||
247 | } | ||
248 | error: | ||
249 | m->status = status; | ||
250 | spi_finalize_current_message(master); | ||
251 | |||
252 | return status; | ||
253 | } | ||
254 | |||
255 | static int sc18is602_setup(struct spi_device *spi) | ||
256 | { | ||
257 | if (!spi->bits_per_word) | ||
258 | spi->bits_per_word = 8; | ||
259 | |||
260 | if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) | ||
261 | return -EINVAL; | ||
262 | |||
263 | return sc18is602_check_transfer(spi, NULL, 0); | ||
264 | } | ||
265 | |||
266 | static int sc18is602_probe(struct i2c_client *client, | ||
267 | const struct i2c_device_id *id) | ||
268 | { | ||
269 | struct device *dev = &client->dev; | ||
270 | struct device_node *np = dev->of_node; | ||
271 | struct sc18is602_platform_data *pdata = dev_get_platdata(dev); | ||
272 | struct sc18is602 *hw; | ||
273 | struct spi_master *master; | ||
274 | int error; | ||
275 | |||
276 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | | ||
277 | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) | ||
278 | return -EINVAL; | ||
279 | |||
280 | master = spi_alloc_master(dev, sizeof(struct sc18is602)); | ||
281 | if (!master) | ||
282 | return -ENOMEM; | ||
283 | |||
284 | hw = spi_master_get_devdata(master); | ||
285 | i2c_set_clientdata(client, hw); | ||
286 | |||
287 | hw->master = master; | ||
288 | hw->client = client; | ||
289 | hw->dev = dev; | ||
290 | hw->ctrl = 0xff; | ||
291 | |||
292 | hw->id = id->driver_data; | ||
293 | |||
294 | switch (hw->id) { | ||
295 | case sc18is602: | ||
296 | case sc18is602b: | ||
297 | master->num_chipselect = 4; | ||
298 | hw->freq = SC18IS602_CLOCK; | ||
299 | break; | ||
300 | case sc18is603: | ||
301 | master->num_chipselect = 2; | ||
302 | if (pdata) { | ||
303 | hw->freq = pdata->clock_frequency; | ||
304 | } else { | ||
305 | const __be32 *val; | ||
306 | int len; | ||
307 | |||
308 | val = of_get_property(np, "clock-frequency", &len); | ||
309 | if (val && len >= sizeof(__be32)) | ||
310 | hw->freq = be32_to_cpup(val); | ||
311 | } | ||
312 | if (!hw->freq) | ||
313 | hw->freq = SC18IS602_CLOCK; | ||
314 | break; | ||
315 | } | ||
316 | master->bus_num = client->adapter->nr; | ||
317 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; | ||
318 | master->setup = sc18is602_setup; | ||
319 | master->transfer_one_message = sc18is602_transfer_one; | ||
320 | master->dev.of_node = np; | ||
321 | |||
322 | error = spi_register_master(master); | ||
323 | if (error) | ||
324 | goto error_reg; | ||
325 | |||
326 | return 0; | ||
327 | |||
328 | error_reg: | ||
329 | spi_master_put(master); | ||
330 | return error; | ||
331 | } | ||
332 | |||
333 | static int sc18is602_remove(struct i2c_client *client) | ||
334 | { | ||
335 | struct sc18is602 *hw = i2c_get_clientdata(client); | ||
336 | struct spi_master *master = hw->master; | ||
337 | |||
338 | spi_unregister_master(master); | ||
339 | |||
340 | return 0; | ||
341 | } | ||
342 | |||
343 | static const struct i2c_device_id sc18is602_id[] = { | ||
344 | { "sc18is602", sc18is602 }, | ||
345 | { "sc18is602b", sc18is602b }, | ||
346 | { "sc18is603", sc18is603 }, | ||
347 | { } | ||
348 | }; | ||
349 | MODULE_DEVICE_TABLE(i2c, sc18is602_id); | ||
350 | |||
351 | static struct i2c_driver sc18is602_driver = { | ||
352 | .driver = { | ||
353 | .name = "sc18is602", | ||
354 | }, | ||
355 | .probe = sc18is602_probe, | ||
356 | .remove = sc18is602_remove, | ||
357 | .id_table = sc18is602_id, | ||
358 | }; | ||
359 | |||
360 | module_i2c_driver(sc18is602_driver); | ||
361 | |||
362 | MODULE_DESCRIPTION("SC18IC602/603 SPI Master Driver"); | ||
363 | MODULE_AUTHOR("Guenter Roeck"); | ||
364 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c deleted file mode 100644 index 60cfae51c71..00000000000 --- a/drivers/spi/spi-sh-hspi.c +++ /dev/null | |||
@@ -1,367 +0,0 @@ | |||
1 | /* | ||
2 | * SuperH HSPI bus driver | ||
3 | * | ||
4 | * Copyright (C) 2011 Kuninori Morimoto | ||
5 | * | ||
6 | * Based on spi-sh.c: | ||
7 | * Based on pxa2xx_spi.c: | ||
8 | * Copyright (C) 2011 Renesas Solutions Corp. | ||
9 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; version 2 of the License. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #include <linux/clk.h> | ||
27 | #include <linux/module.h> | ||
28 | #include <linux/kernel.h> | ||
29 | #include <linux/timer.h> | ||
30 | #include <linux/delay.h> | ||
31 | #include <linux/list.h> | ||
32 | #include <linux/interrupt.h> | ||
33 | #include <linux/platform_device.h> | ||
34 | #include <linux/pm_runtime.h> | ||
35 | #include <linux/io.h> | ||
36 | #include <linux/spi/spi.h> | ||
37 | #include <linux/spi/sh_hspi.h> | ||
38 | |||
39 | #define SPCR 0x00 | ||
40 | #define SPSR 0x04 | ||
41 | #define SPSCR 0x08 | ||
42 | #define SPTBR 0x0C | ||
43 | #define SPRBR 0x10 | ||
44 | #define SPCR2 0x14 | ||
45 | |||
46 | /* SPSR */ | ||
47 | #define RXFL (1 << 2) | ||
48 | |||
49 | #define hspi2info(h) (h->dev->platform_data) | ||
50 | |||
51 | struct hspi_priv { | ||
52 | void __iomem *addr; | ||
53 | struct spi_master *master; | ||
54 | struct device *dev; | ||
55 | struct clk *clk; | ||
56 | }; | ||
57 | |||
58 | /* | ||
59 | * basic function | ||
60 | */ | ||
61 | static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) | ||
62 | { | ||
63 | iowrite32(val, hspi->addr + reg); | ||
64 | } | ||
65 | |||
66 | static u32 hspi_read(struct hspi_priv *hspi, int reg) | ||
67 | { | ||
68 | return ioread32(hspi->addr + reg); | ||
69 | } | ||
70 | |||
71 | static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set) | ||
72 | { | ||
73 | u32 val = hspi_read(hspi, reg); | ||
74 | |||
75 | val &= ~mask; | ||
76 | val |= set & mask; | ||
77 | |||
78 | hspi_write(hspi, reg, val); | ||
79 | } | ||
80 | |||
81 | /* | ||
82 | * transfer function | ||
83 | */ | ||
84 | static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) | ||
85 | { | ||
86 | int t = 256; | ||
87 | |||
88 | while (t--) { | ||
89 | if ((mask & hspi_read(hspi, SPSR)) == val) | ||
90 | return 0; | ||
91 | |||
92 | msleep(20); | ||
93 | } | ||
94 | |||
95 | dev_err(hspi->dev, "timeout\n"); | ||
96 | return -ETIMEDOUT; | ||
97 | } | ||
98 | |||
99 | /* | ||
100 | * spi master function | ||
101 | */ | ||
102 | static int hspi_prepare_transfer(struct spi_master *master) | ||
103 | { | ||
104 | struct hspi_priv *hspi = spi_master_get_devdata(master); | ||
105 | |||
106 | pm_runtime_get_sync(hspi->dev); | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | static int hspi_unprepare_transfer(struct spi_master *master) | ||
111 | { | ||
112 | struct hspi_priv *hspi = spi_master_get_devdata(master); | ||
113 | |||
114 | pm_runtime_put_sync(hspi->dev); | ||
115 | return 0; | ||
116 | } | ||
117 | |||
118 | #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0) | ||
119 | #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1) | ||
120 | static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi) | ||
121 | { | ||
122 | hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6); | ||
123 | } | ||
124 | |||
125 | static void hspi_hw_setup(struct hspi_priv *hspi, | ||
126 | struct spi_message *msg, | ||
127 | struct spi_transfer *t) | ||
128 | { | ||
129 | struct spi_device *spi = msg->spi; | ||
130 | struct device *dev = hspi->dev; | ||
131 | u32 target_rate; | ||
132 | u32 spcr, idiv_clk; | ||
133 | u32 rate, best_rate, min, tmp; | ||
134 | |||
135 | target_rate = t ? t->speed_hz : 0; | ||
136 | if (!target_rate) | ||
137 | target_rate = spi->max_speed_hz; | ||
138 | |||
139 | /* | ||
140 | * find best IDIV/CLKCx settings | ||
141 | */ | ||
142 | min = ~0; | ||
143 | best_rate = 0; | ||
144 | spcr = 0; | ||
145 | for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) { | ||
146 | rate = clk_get_rate(hspi->clk); | ||
147 | |||
148 | /* IDIV calculation */ | ||
149 | if (idiv_clk & (1 << 5)) | ||
150 | rate /= 128; | ||
151 | else | ||
152 | rate /= 16; | ||
153 | |||
154 | /* CLKCx calculation */ | ||
155 | rate /= (((idiv_clk & 0x1F) + 1) * 2) ; | ||
156 | |||
157 | /* save best settings */ | ||
158 | tmp = abs(target_rate - rate); | ||
159 | if (tmp < min) { | ||
160 | min = tmp; | ||
161 | spcr = idiv_clk; | ||
162 | best_rate = rate; | ||
163 | } | ||
164 | } | ||
165 | |||
166 | if (spi->mode & SPI_CPHA) | ||
167 | spcr |= 1 << 7; | ||
168 | if (spi->mode & SPI_CPOL) | ||
169 | spcr |= 1 << 6; | ||
170 | |||
171 | dev_dbg(dev, "speed %d/%d\n", target_rate, best_rate); | ||
172 | |||
173 | hspi_write(hspi, SPCR, spcr); | ||
174 | hspi_write(hspi, SPSR, 0x0); | ||
175 | hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */ | ||
176 | } | ||
177 | |||
178 | static int hspi_transfer_one_message(struct spi_master *master, | ||
179 | struct spi_message *msg) | ||
180 | { | ||
181 | struct hspi_priv *hspi = spi_master_get_devdata(master); | ||
182 | struct spi_transfer *t; | ||
183 | u32 tx; | ||
184 | u32 rx; | ||
185 | int ret, i; | ||
186 | unsigned int cs_change; | ||
187 | const int nsecs = 50; | ||
188 | |||
189 | dev_dbg(hspi->dev, "%s\n", __func__); | ||
190 | |||
191 | cs_change = 1; | ||
192 | ret = 0; | ||
193 | list_for_each_entry(t, &msg->transfers, transfer_list) { | ||
194 | |||
195 | if (cs_change) { | ||
196 | hspi_hw_setup(hspi, msg, t); | ||
197 | hspi_hw_cs_enable(hspi); | ||
198 | ndelay(nsecs); | ||
199 | } | ||
200 | cs_change = t->cs_change; | ||
201 | |||
202 | for (i = 0; i < t->len; i++) { | ||
203 | |||
204 | /* wait remains */ | ||
205 | ret = hspi_status_check_timeout(hspi, 0x1, 0); | ||
206 | if (ret < 0) | ||
207 | break; | ||
208 | |||
209 | tx = 0; | ||
210 | if (t->tx_buf) | ||
211 | tx = (u32)((u8 *)t->tx_buf)[i]; | ||
212 | |||
213 | hspi_write(hspi, SPTBR, tx); | ||
214 | |||
215 | /* wait recive */ | ||
216 | ret = hspi_status_check_timeout(hspi, 0x4, 0x4); | ||
217 | if (ret < 0) | ||
218 | break; | ||
219 | |||
220 | rx = hspi_read(hspi, SPRBR); | ||
221 | if (t->rx_buf) | ||
222 | ((u8 *)t->rx_buf)[i] = (u8)rx; | ||
223 | |||
224 | } | ||
225 | |||
226 | msg->actual_length += t->len; | ||
227 | |||
228 | if (t->delay_usecs) | ||
229 | udelay(t->delay_usecs); | ||
230 | |||
231 | if (cs_change) { | ||
232 | ndelay(nsecs); | ||
233 | hspi_hw_cs_disable(hspi); | ||
234 | ndelay(nsecs); | ||
235 | } | ||
236 | } | ||
237 | |||
238 | msg->status = ret; | ||
239 | if (!cs_change) { | ||
240 | ndelay(nsecs); | ||
241 | hspi_hw_cs_disable(hspi); | ||
242 | } | ||
243 | spi_finalize_current_message(master); | ||
244 | |||
245 | return ret; | ||
246 | } | ||
247 | |||
248 | static int hspi_setup(struct spi_device *spi) | ||
249 | { | ||
250 | struct hspi_priv *hspi = spi_master_get_devdata(spi->master); | ||
251 | struct device *dev = hspi->dev; | ||
252 | |||
253 | if (8 != spi->bits_per_word) { | ||
254 | dev_err(dev, "bits_per_word should be 8\n"); | ||
255 | return -EIO; | ||
256 | } | ||
257 | |||
258 | dev_dbg(dev, "%s setup\n", spi->modalias); | ||
259 | |||
260 | return 0; | ||
261 | } | ||
262 | |||
263 | static void hspi_cleanup(struct spi_device *spi) | ||
264 | { | ||
265 | struct hspi_priv *hspi = spi_master_get_devdata(spi->master); | ||
266 | struct device *dev = hspi->dev; | ||
267 | |||
268 | dev_dbg(dev, "%s cleanup\n", spi->modalias); | ||
269 | } | ||
270 | |||
271 | static int hspi_probe(struct platform_device *pdev) | ||
272 | { | ||
273 | struct resource *res; | ||
274 | struct spi_master *master; | ||
275 | struct hspi_priv *hspi; | ||
276 | struct clk *clk; | ||
277 | int ret; | ||
278 | |||
279 | /* get base addr */ | ||
280 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
281 | if (!res) { | ||
282 | dev_err(&pdev->dev, "invalid resource\n"); | ||
283 | return -EINVAL; | ||
284 | } | ||
285 | |||
286 | master = spi_alloc_master(&pdev->dev, sizeof(*hspi)); | ||
287 | if (!master) { | ||
288 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | ||
289 | return -ENOMEM; | ||
290 | } | ||
291 | |||
292 | clk = clk_get(NULL, "shyway_clk"); | ||
293 | if (IS_ERR(clk)) { | ||
294 | dev_err(&pdev->dev, "shyway_clk is required\n"); | ||
295 | ret = -EINVAL; | ||
296 | goto error0; | ||
297 | } | ||
298 | |||
299 | hspi = spi_master_get_devdata(master); | ||
300 | dev_set_drvdata(&pdev->dev, hspi); | ||
301 | |||
302 | /* init hspi */ | ||
303 | hspi->master = master; | ||
304 | hspi->dev = &pdev->dev; | ||
305 | hspi->clk = clk; | ||
306 | hspi->addr = devm_ioremap(hspi->dev, | ||
307 | res->start, resource_size(res)); | ||
308 | if (!hspi->addr) { | ||
309 | dev_err(&pdev->dev, "ioremap error.\n"); | ||
310 | ret = -ENOMEM; | ||
311 | goto error1; | ||
312 | } | ||
313 | |||
314 | master->num_chipselect = 1; | ||
315 | master->bus_num = pdev->id; | ||
316 | master->setup = hspi_setup; | ||
317 | master->cleanup = hspi_cleanup; | ||
318 | master->mode_bits = SPI_CPOL | SPI_CPHA; | ||
319 | master->prepare_transfer_hardware = hspi_prepare_transfer; | ||
320 | master->transfer_one_message = hspi_transfer_one_message; | ||
321 | master->unprepare_transfer_hardware = hspi_unprepare_transfer; | ||
322 | ret = spi_register_master(master); | ||
323 | if (ret < 0) { | ||
324 | dev_err(&pdev->dev, "spi_register_master error.\n"); | ||
325 | goto error1; | ||
326 | } | ||
327 | |||
328 | pm_runtime_enable(&pdev->dev); | ||
329 | |||
330 | dev_info(&pdev->dev, "probed\n"); | ||
331 | |||
332 | return 0; | ||
333 | |||
334 | error1: | ||
335 | clk_put(clk); | ||
336 | error0: | ||
337 | spi_master_put(master); | ||
338 | |||
339 | return ret; | ||
340 | } | ||
341 | |||
342 | static int hspi_remove(struct platform_device *pdev) | ||
343 | { | ||
344 | struct hspi_priv *hspi = dev_get_drvdata(&pdev->dev); | ||
345 | |||
346 | pm_runtime_disable(&pdev->dev); | ||
347 | |||
348 | clk_put(hspi->clk); | ||
349 | spi_unregister_master(hspi->master); | ||
350 | |||
351 | return 0; | ||
352 | } | ||
353 | |||
354 | static struct platform_driver hspi_driver = { | ||
355 | .probe = hspi_probe, | ||
356 | .remove = hspi_remove, | ||
357 | .driver = { | ||
358 | .name = "sh-hspi", | ||
359 | .owner = THIS_MODULE, | ||
360 | }, | ||
361 | }; | ||
362 | module_platform_driver(hspi_driver); | ||
363 | |||
364 | MODULE_DESCRIPTION("SuperH HSPI bus driver"); | ||
365 | MODULE_LICENSE("GPL"); | ||
366 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); | ||
367 | MODULE_ALIAS("platform:sh_spi"); | ||
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 96358d0eabb..e00d94b2225 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c | |||
@@ -19,7 +19,6 @@ | |||
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> | ||
23 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
24 | #include <linux/pm_runtime.h> | 23 | #include <linux/pm_runtime.h> |
25 | 24 | ||
@@ -597,6 +596,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) | |||
597 | struct resource *r; | 596 | struct resource *r; |
598 | struct spi_master *master; | 597 | struct spi_master *master; |
599 | struct sh_msiof_spi_priv *p; | 598 | struct sh_msiof_spi_priv *p; |
599 | char clk_name[16]; | ||
600 | int i; | 600 | int i; |
601 | int ret; | 601 | int ret; |
602 | 602 | ||
@@ -613,9 +613,10 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) | |||
613 | p->info = pdev->dev.platform_data; | 613 | p->info = pdev->dev.platform_data; |
614 | init_completion(&p->done); | 614 | init_completion(&p->done); |
615 | 615 | ||
616 | p->clk = clk_get(&pdev->dev, NULL); | 616 | snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id); |
617 | p->clk = clk_get(&pdev->dev, clk_name); | ||
617 | if (IS_ERR(p->clk)) { | 618 | if (IS_ERR(p->clk)) { |
618 | dev_err(&pdev->dev, "cannot get clock\n"); | 619 | dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); |
619 | ret = PTR_ERR(p->clk); | 620 | ret = PTR_ERR(p->clk); |
620 | goto err1; | 621 | goto err1; |
621 | } | 622 | } |
@@ -634,7 +635,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) | |||
634 | goto err2; | 635 | goto err2; |
635 | } | 636 | } |
636 | 637 | ||
637 | ret = request_irq(i, sh_msiof_spi_irq, 0, | 638 | ret = request_irq(i, sh_msiof_spi_irq, IRQF_DISABLED, |
638 | dev_name(&pdev->dev), p); | 639 | dev_name(&pdev->dev), p); |
639 | if (ret) { | 640 | if (ret) { |
640 | dev_err(&pdev->dev, "unable to request irq\n"); | 641 | dev_err(&pdev->dev, "unable to request irq\n"); |
@@ -729,7 +730,18 @@ static struct platform_driver sh_msiof_spi_drv = { | |||
729 | .pm = &sh_msiof_spi_dev_pm_ops, | 730 | .pm = &sh_msiof_spi_dev_pm_ops, |
730 | }, | 731 | }, |
731 | }; | 732 | }; |
732 | module_platform_driver(sh_msiof_spi_drv); | 733 | |
734 | static int __init sh_msiof_spi_init(void) | ||
735 | { | ||
736 | return platform_driver_register(&sh_msiof_spi_drv); | ||
737 | } | ||
738 | module_init(sh_msiof_spi_init); | ||
739 | |||
740 | static void __exit sh_msiof_spi_exit(void) | ||
741 | { | ||
742 | platform_driver_unregister(&sh_msiof_spi_drv); | ||
743 | } | ||
744 | module_exit(sh_msiof_spi_exit); | ||
733 | 745 | ||
734 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | 746 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); |
735 | MODULE_AUTHOR("Magnus Damm"); | 747 | MODULE_AUTHOR("Magnus Damm"); |
diff --git a/drivers/spi/spi-sh-sci.c b/drivers/spi/spi-sh-sci.c index 097e506042b..e7779c09f6e 100644 --- a/drivers/spi/spi-sh-sci.c +++ b/drivers/spi/spi-sh-sci.c | |||
@@ -22,7 +22,6 @@ | |||
22 | 22 | ||
23 | #include <linux/spi/spi.h> | 23 | #include <linux/spi/spi.h> |
24 | #include <linux/spi/spi_bitbang.h> | 24 | #include <linux/spi/spi_bitbang.h> |
25 | #include <linux/module.h> | ||
26 | 25 | ||
27 | #include <asm/spi.h> | 26 | #include <asm/spi.h> |
28 | #include <asm/io.h> | 27 | #include <asm/io.h> |
@@ -187,7 +186,18 @@ static struct platform_driver sh_sci_spi_drv = { | |||
187 | .owner = THIS_MODULE, | 186 | .owner = THIS_MODULE, |
188 | }, | 187 | }, |
189 | }; | 188 | }; |
190 | module_platform_driver(sh_sci_spi_drv); | 189 | |
190 | static int __init sh_sci_spi_init(void) | ||
191 | { | ||
192 | return platform_driver_register(&sh_sci_spi_drv); | ||
193 | } | ||
194 | module_init(sh_sci_spi_init); | ||
195 | |||
196 | static void __exit sh_sci_spi_exit(void) | ||
197 | { | ||
198 | platform_driver_unregister(&sh_sci_spi_drv); | ||
199 | } | ||
200 | module_exit(sh_sci_spi_exit); | ||
191 | 201 | ||
192 | MODULE_DESCRIPTION("SH SCI SPI Driver"); | 202 | MODULE_DESCRIPTION("SH SCI SPI Driver"); |
193 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); | 203 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); |
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c index 3c3600a994b..9eedd71ad89 100644 --- a/drivers/spi/spi-sh.c +++ b/drivers/spi/spi-sh.c | |||
@@ -92,26 +92,17 @@ struct spi_sh_data { | |||
92 | unsigned long cr1; | 92 | unsigned long cr1; |
93 | wait_queue_head_t wait; | 93 | wait_queue_head_t wait; |
94 | spinlock_t lock; | 94 | spinlock_t lock; |
95 | int width; | ||
96 | }; | 95 | }; |
97 | 96 | ||
98 | static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, | 97 | static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, |
99 | unsigned long offset) | 98 | unsigned long offset) |
100 | { | 99 | { |
101 | if (ss->width == 8) | 100 | writel(data, ss->addr + offset); |
102 | iowrite8(data, ss->addr + (offset >> 2)); | ||
103 | else if (ss->width == 32) | ||
104 | iowrite32(data, ss->addr + offset); | ||
105 | } | 101 | } |
106 | 102 | ||
107 | static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) | 103 | static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) |
108 | { | 104 | { |
109 | if (ss->width == 8) | 105 | return readl(ss->addr + offset); |
110 | return ioread8(ss->addr + (offset >> 2)); | ||
111 | else if (ss->width == 32) | ||
112 | return ioread32(ss->addr + offset); | ||
113 | else | ||
114 | return 0; | ||
115 | } | 106 | } |
116 | 107 | ||
117 | static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, | 108 | static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, |
@@ -432,7 +423,7 @@ static irqreturn_t spi_sh_irq(int irq, void *_ss) | |||
432 | return IRQ_HANDLED; | 423 | return IRQ_HANDLED; |
433 | } | 424 | } |
434 | 425 | ||
435 | static int spi_sh_remove(struct platform_device *pdev) | 426 | static int __devexit spi_sh_remove(struct platform_device *pdev) |
436 | { | 427 | { |
437 | struct spi_sh_data *ss = dev_get_drvdata(&pdev->dev); | 428 | struct spi_sh_data *ss = dev_get_drvdata(&pdev->dev); |
438 | 429 | ||
@@ -444,7 +435,7 @@ static int spi_sh_remove(struct platform_device *pdev) | |||
444 | return 0; | 435 | return 0; |
445 | } | 436 | } |
446 | 437 | ||
447 | static int spi_sh_probe(struct platform_device *pdev) | 438 | static int __devinit spi_sh_probe(struct platform_device *pdev) |
448 | { | 439 | { |
449 | struct resource *res; | 440 | struct resource *res; |
450 | struct spi_master *master; | 441 | struct spi_master *master; |
@@ -473,18 +464,6 @@ static int spi_sh_probe(struct platform_device *pdev) | |||
473 | ss = spi_master_get_devdata(master); | 464 | ss = spi_master_get_devdata(master); |
474 | dev_set_drvdata(&pdev->dev, ss); | 465 | dev_set_drvdata(&pdev->dev, ss); |
475 | 466 | ||
476 | switch (res->flags & IORESOURCE_MEM_TYPE_MASK) { | ||
477 | case IORESOURCE_MEM_8BIT: | ||
478 | ss->width = 8; | ||
479 | break; | ||
480 | case IORESOURCE_MEM_32BIT: | ||
481 | ss->width = 32; | ||
482 | break; | ||
483 | default: | ||
484 | dev_err(&pdev->dev, "No support width\n"); | ||
485 | ret = -ENODEV; | ||
486 | goto error1; | ||
487 | } | ||
488 | ss->irq = irq; | 467 | ss->irq = irq; |
489 | ss->master = master; | 468 | ss->master = master; |
490 | ss->addr = ioremap(res->start, resource_size(res)); | 469 | ss->addr = ioremap(res->start, resource_size(res)); |
@@ -505,7 +484,7 @@ static int spi_sh_probe(struct platform_device *pdev) | |||
505 | goto error2; | 484 | goto error2; |
506 | } | 485 | } |
507 | 486 | ||
508 | ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss); | 487 | ret = request_irq(irq, spi_sh_irq, IRQF_DISABLED, "spi_sh", ss); |
509 | if (ret < 0) { | 488 | if (ret < 0) { |
510 | dev_err(&pdev->dev, "request_irq error\n"); | 489 | dev_err(&pdev->dev, "request_irq error\n"); |
511 | goto error3; | 490 | goto error3; |
@@ -539,13 +518,24 @@ static int spi_sh_probe(struct platform_device *pdev) | |||
539 | 518 | ||
540 | static struct platform_driver spi_sh_driver = { | 519 | static struct platform_driver spi_sh_driver = { |
541 | .probe = spi_sh_probe, | 520 | .probe = spi_sh_probe, |
542 | .remove = spi_sh_remove, | 521 | .remove = __devexit_p(spi_sh_remove), |
543 | .driver = { | 522 | .driver = { |
544 | .name = "sh_spi", | 523 | .name = "sh_spi", |
545 | .owner = THIS_MODULE, | 524 | .owner = THIS_MODULE, |
546 | }, | 525 | }, |
547 | }; | 526 | }; |
548 | module_platform_driver(spi_sh_driver); | 527 | |
528 | static int __init spi_sh_init(void) | ||
529 | { | ||
530 | return platform_driver_register(&spi_sh_driver); | ||
531 | } | ||
532 | module_init(spi_sh_init); | ||
533 | |||
534 | static void __exit spi_sh_exit(void) | ||
535 | { | ||
536 | platform_driver_unregister(&spi_sh_driver); | ||
537 | } | ||
538 | module_exit(spi_sh_exit); | ||
549 | 539 | ||
550 | MODULE_DESCRIPTION("SH SPI bus driver"); | 540 | MODULE_DESCRIPTION("SH SPI bus driver"); |
551 | MODULE_LICENSE("GPL"); | 541 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c deleted file mode 100644 index e0f43a512e8..00000000000 --- a/drivers/spi/spi-sirf.c +++ /dev/null | |||
@@ -1,683 +0,0 @@ | |||
1 | /* | ||
2 | * SPI bus driver for CSR SiRFprimaII | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #include <linux/module.h> | ||
10 | #include <linux/kernel.h> | ||
11 | #include <linux/slab.h> | ||
12 | #include <linux/clk.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/of.h> | ||
16 | #include <linux/bitops.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/of_gpio.h> | ||
20 | #include <linux/spi/spi.h> | ||
21 | #include <linux/spi/spi_bitbang.h> | ||
22 | #include <linux/pinctrl/consumer.h> | ||
23 | |||
24 | #define DRIVER_NAME "sirfsoc_spi" | ||
25 | |||
26 | #define SIRFSOC_SPI_CTRL 0x0000 | ||
27 | #define SIRFSOC_SPI_CMD 0x0004 | ||
28 | #define SIRFSOC_SPI_TX_RX_EN 0x0008 | ||
29 | #define SIRFSOC_SPI_INT_EN 0x000C | ||
30 | #define SIRFSOC_SPI_INT_STATUS 0x0010 | ||
31 | #define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100 | ||
32 | #define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104 | ||
33 | #define SIRFSOC_SPI_TXFIFO_CTRL 0x0108 | ||
34 | #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C | ||
35 | #define SIRFSOC_SPI_TXFIFO_OP 0x0110 | ||
36 | #define SIRFSOC_SPI_TXFIFO_STATUS 0x0114 | ||
37 | #define SIRFSOC_SPI_TXFIFO_DATA 0x0118 | ||
38 | #define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120 | ||
39 | #define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124 | ||
40 | #define SIRFSOC_SPI_RXFIFO_CTRL 0x0128 | ||
41 | #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C | ||
42 | #define SIRFSOC_SPI_RXFIFO_OP 0x0130 | ||
43 | #define SIRFSOC_SPI_RXFIFO_STATUS 0x0134 | ||
44 | #define SIRFSOC_SPI_RXFIFO_DATA 0x0138 | ||
45 | #define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144 | ||
46 | |||
47 | /* SPI CTRL register defines */ | ||
48 | #define SIRFSOC_SPI_SLV_MODE BIT(16) | ||
49 | #define SIRFSOC_SPI_CMD_MODE BIT(17) | ||
50 | #define SIRFSOC_SPI_CS_IO_OUT BIT(18) | ||
51 | #define SIRFSOC_SPI_CS_IO_MODE BIT(19) | ||
52 | #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20) | ||
53 | #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21) | ||
54 | #define SIRFSOC_SPI_TRAN_MSB BIT(22) | ||
55 | #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23) | ||
56 | #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24) | ||
57 | #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25) | ||
58 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26) | ||
59 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26) | ||
60 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26) | ||
61 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26) | ||
62 | #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28) | ||
63 | #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30) | ||
64 | #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31) | ||
65 | |||
66 | /* Interrupt Enable */ | ||
67 | #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0) | ||
68 | #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1) | ||
69 | #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2) | ||
70 | #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3) | ||
71 | #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4) | ||
72 | #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5) | ||
73 | #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6) | ||
74 | #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7) | ||
75 | #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8) | ||
76 | #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) | ||
77 | #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) | ||
78 | |||
79 | #define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF | ||
80 | |||
81 | /* Interrupt status */ | ||
82 | #define SIRFSOC_SPI_RX_DONE BIT(0) | ||
83 | #define SIRFSOC_SPI_TX_DONE BIT(1) | ||
84 | #define SIRFSOC_SPI_RX_OFLOW BIT(2) | ||
85 | #define SIRFSOC_SPI_TX_UFLOW BIT(3) | ||
86 | #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) | ||
87 | #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) | ||
88 | #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) | ||
89 | #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9) | ||
90 | #define SIRFSOC_SPI_FRM_END BIT(10) | ||
91 | |||
92 | /* TX RX enable */ | ||
93 | #define SIRFSOC_SPI_RX_EN BIT(0) | ||
94 | #define SIRFSOC_SPI_TX_EN BIT(1) | ||
95 | #define SIRFSOC_SPI_CMD_TX_EN BIT(2) | ||
96 | |||
97 | #define SIRFSOC_SPI_IO_MODE_SEL BIT(0) | ||
98 | #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2) | ||
99 | |||
100 | /* FIFO OPs */ | ||
101 | #define SIRFSOC_SPI_FIFO_RESET BIT(0) | ||
102 | #define SIRFSOC_SPI_FIFO_START BIT(1) | ||
103 | |||
104 | /* FIFO CTRL */ | ||
105 | #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0) | ||
106 | #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0) | ||
107 | #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0) | ||
108 | |||
109 | /* FIFO Status */ | ||
110 | #define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF | ||
111 | #define SIRFSOC_SPI_FIFO_FULL BIT(8) | ||
112 | #define SIRFSOC_SPI_FIFO_EMPTY BIT(9) | ||
113 | |||
114 | /* 256 bytes rx/tx FIFO */ | ||
115 | #define SIRFSOC_SPI_FIFO_SIZE 256 | ||
116 | #define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024) | ||
117 | |||
118 | #define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F) | ||
119 | #define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10) | ||
120 | #define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20) | ||
121 | #define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2) | ||
122 | |||
123 | struct sirfsoc_spi { | ||
124 | struct spi_bitbang bitbang; | ||
125 | struct completion done; | ||
126 | |||
127 | void __iomem *base; | ||
128 | u32 ctrl_freq; /* SPI controller clock speed */ | ||
129 | struct clk *clk; | ||
130 | struct pinctrl *p; | ||
131 | |||
132 | /* rx & tx bufs from the spi_transfer */ | ||
133 | const void *tx; | ||
134 | void *rx; | ||
135 | |||
136 | /* place received word into rx buffer */ | ||
137 | void (*rx_word) (struct sirfsoc_spi *); | ||
138 | /* get word from tx buffer for sending */ | ||
139 | void (*tx_word) (struct sirfsoc_spi *); | ||
140 | |||
141 | /* number of words left to be tranmitted/received */ | ||
142 | unsigned int left_tx_cnt; | ||
143 | unsigned int left_rx_cnt; | ||
144 | |||
145 | /* tasklet to push tx msg into FIFO */ | ||
146 | struct tasklet_struct tasklet_tx; | ||
147 | |||
148 | int chipselect[0]; | ||
149 | }; | ||
150 | |||
151 | static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) | ||
152 | { | ||
153 | u32 data; | ||
154 | u8 *rx = sspi->rx; | ||
155 | |||
156 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | ||
157 | |||
158 | if (rx) { | ||
159 | *rx++ = (u8) data; | ||
160 | sspi->rx = rx; | ||
161 | } | ||
162 | |||
163 | sspi->left_rx_cnt--; | ||
164 | } | ||
165 | |||
166 | static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) | ||
167 | { | ||
168 | u32 data = 0; | ||
169 | const u8 *tx = sspi->tx; | ||
170 | |||
171 | if (tx) { | ||
172 | data = *tx++; | ||
173 | sspi->tx = tx; | ||
174 | } | ||
175 | |||
176 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | ||
177 | sspi->left_tx_cnt--; | ||
178 | } | ||
179 | |||
180 | static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) | ||
181 | { | ||
182 | u32 data; | ||
183 | u16 *rx = sspi->rx; | ||
184 | |||
185 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | ||
186 | |||
187 | if (rx) { | ||
188 | *rx++ = (u16) data; | ||
189 | sspi->rx = rx; | ||
190 | } | ||
191 | |||
192 | sspi->left_rx_cnt--; | ||
193 | } | ||
194 | |||
195 | static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) | ||
196 | { | ||
197 | u32 data = 0; | ||
198 | const u16 *tx = sspi->tx; | ||
199 | |||
200 | if (tx) { | ||
201 | data = *tx++; | ||
202 | sspi->tx = tx; | ||
203 | } | ||
204 | |||
205 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | ||
206 | sspi->left_tx_cnt--; | ||
207 | } | ||
208 | |||
209 | static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) | ||
210 | { | ||
211 | u32 data; | ||
212 | u32 *rx = sspi->rx; | ||
213 | |||
214 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | ||
215 | |||
216 | if (rx) { | ||
217 | *rx++ = (u32) data; | ||
218 | sspi->rx = rx; | ||
219 | } | ||
220 | |||
221 | sspi->left_rx_cnt--; | ||
222 | |||
223 | } | ||
224 | |||
225 | static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) | ||
226 | { | ||
227 | u32 data = 0; | ||
228 | const u32 *tx = sspi->tx; | ||
229 | |||
230 | if (tx) { | ||
231 | data = *tx++; | ||
232 | sspi->tx = tx; | ||
233 | } | ||
234 | |||
235 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | ||
236 | sspi->left_tx_cnt--; | ||
237 | } | ||
238 | |||
239 | static void spi_sirfsoc_tasklet_tx(unsigned long arg) | ||
240 | { | ||
241 | struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg; | ||
242 | |||
243 | /* Fill Tx FIFO while there are left words to be transmitted */ | ||
244 | while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) & | ||
245 | SIRFSOC_SPI_FIFO_FULL)) && | ||
246 | sspi->left_tx_cnt) | ||
247 | sspi->tx_word(sspi); | ||
248 | } | ||
249 | |||
250 | static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) | ||
251 | { | ||
252 | struct sirfsoc_spi *sspi = dev_id; | ||
253 | u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); | ||
254 | |||
255 | writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); | ||
256 | |||
257 | /* Error Conditions */ | ||
258 | if (spi_stat & SIRFSOC_SPI_RX_OFLOW || | ||
259 | spi_stat & SIRFSOC_SPI_TX_UFLOW) { | ||
260 | complete(&sspi->done); | ||
261 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); | ||
262 | } | ||
263 | |||
264 | if (spi_stat & SIRFSOC_SPI_FRM_END) { | ||
265 | while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS) | ||
266 | & SIRFSOC_SPI_FIFO_EMPTY)) && | ||
267 | sspi->left_rx_cnt) | ||
268 | sspi->rx_word(sspi); | ||
269 | |||
270 | /* Received all words */ | ||
271 | if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) { | ||
272 | complete(&sspi->done); | ||
273 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); | ||
274 | } | ||
275 | } | ||
276 | |||
277 | if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH || | ||
278 | spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH || | ||
279 | spi_stat & SIRFSOC_SPI_RX_FIFO_FULL || | ||
280 | spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY) | ||
281 | tasklet_schedule(&sspi->tasklet_tx); | ||
282 | |||
283 | return IRQ_HANDLED; | ||
284 | } | ||
285 | |||
286 | static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) | ||
287 | { | ||
288 | struct sirfsoc_spi *sspi; | ||
289 | int timeout = t->len * 10; | ||
290 | sspi = spi_master_get_devdata(spi->master); | ||
291 | |||
292 | sspi->tx = t->tx_buf; | ||
293 | sspi->rx = t->rx_buf; | ||
294 | sspi->left_tx_cnt = sspi->left_rx_cnt = t->len; | ||
295 | INIT_COMPLETION(sspi->done); | ||
296 | |||
297 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); | ||
298 | |||
299 | if (t->len == 1) { | ||
300 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | | ||
301 | SIRFSOC_SPI_ENA_AUTO_CLR, | ||
302 | sspi->base + SIRFSOC_SPI_CTRL); | ||
303 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | ||
304 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | ||
305 | } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) { | ||
306 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | | ||
307 | SIRFSOC_SPI_MUL_DAT_MODE | | ||
308 | SIRFSOC_SPI_ENA_AUTO_CLR, | ||
309 | sspi->base + SIRFSOC_SPI_CTRL); | ||
310 | writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | ||
311 | writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | ||
312 | } else { | ||
313 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL), | ||
314 | sspi->base + SIRFSOC_SPI_CTRL); | ||
315 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | ||
316 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | ||
317 | } | ||
318 | |||
319 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
320 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
321 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
322 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
323 | |||
324 | /* Send the first word to trigger the whole tx/rx process */ | ||
325 | sspi->tx_word(sspi); | ||
326 | |||
327 | writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN | | ||
328 | SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN | | ||
329 | SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN | | ||
330 | SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN); | ||
331 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN); | ||
332 | |||
333 | if (wait_for_completion_timeout(&sspi->done, timeout) == 0) | ||
334 | dev_err(&spi->dev, "transfer timeout\n"); | ||
335 | |||
336 | /* TX, RX FIFO stop */ | ||
337 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
338 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
339 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); | ||
340 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); | ||
341 | |||
342 | return t->len - sspi->left_rx_cnt; | ||
343 | } | ||
344 | |||
345 | static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) | ||
346 | { | ||
347 | struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); | ||
348 | |||
349 | if (sspi->chipselect[spi->chip_select] == 0) { | ||
350 | u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); | ||
351 | regval |= SIRFSOC_SPI_CS_IO_OUT; | ||
352 | switch (value) { | ||
353 | case BITBANG_CS_ACTIVE: | ||
354 | if (spi->mode & SPI_CS_HIGH) | ||
355 | regval |= SIRFSOC_SPI_CS_IO_OUT; | ||
356 | else | ||
357 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | ||
358 | break; | ||
359 | case BITBANG_CS_INACTIVE: | ||
360 | if (spi->mode & SPI_CS_HIGH) | ||
361 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | ||
362 | else | ||
363 | regval |= SIRFSOC_SPI_CS_IO_OUT; | ||
364 | break; | ||
365 | } | ||
366 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); | ||
367 | } else { | ||
368 | int gpio = sspi->chipselect[spi->chip_select]; | ||
369 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | ||
370 | } | ||
371 | } | ||
372 | |||
373 | static int | ||
374 | spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | ||
375 | { | ||
376 | struct sirfsoc_spi *sspi; | ||
377 | u8 bits_per_word = 0; | ||
378 | int hz = 0; | ||
379 | u32 regval; | ||
380 | u32 txfifo_ctrl, rxfifo_ctrl; | ||
381 | u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; | ||
382 | |||
383 | sspi = spi_master_get_devdata(spi->master); | ||
384 | |||
385 | bits_per_word = t && t->bits_per_word ? t->bits_per_word : | ||
386 | spi->bits_per_word; | ||
387 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; | ||
388 | |||
389 | /* Enable IO mode for RX, TX */ | ||
390 | writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); | ||
391 | writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); | ||
392 | regval = (sspi->ctrl_freq / (2 * hz)) - 1; | ||
393 | |||
394 | if (regval > 0xFFFF || regval < 0) { | ||
395 | dev_err(&spi->dev, "Speed %d not supported\n", hz); | ||
396 | return -EINVAL; | ||
397 | } | ||
398 | |||
399 | switch (bits_per_word) { | ||
400 | case 8: | ||
401 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; | ||
402 | sspi->rx_word = spi_sirfsoc_rx_word_u8; | ||
403 | sspi->tx_word = spi_sirfsoc_tx_word_u8; | ||
404 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
405 | SIRFSOC_SPI_FIFO_WIDTH_BYTE; | ||
406 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
407 | SIRFSOC_SPI_FIFO_WIDTH_BYTE; | ||
408 | break; | ||
409 | case 12: | ||
410 | case 16: | ||
411 | regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 : | ||
412 | SIRFSOC_SPI_TRAN_DAT_FORMAT_16; | ||
413 | sspi->rx_word = spi_sirfsoc_rx_word_u16; | ||
414 | sspi->tx_word = spi_sirfsoc_tx_word_u16; | ||
415 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
416 | SIRFSOC_SPI_FIFO_WIDTH_WORD; | ||
417 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
418 | SIRFSOC_SPI_FIFO_WIDTH_WORD; | ||
419 | break; | ||
420 | case 32: | ||
421 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; | ||
422 | sspi->rx_word = spi_sirfsoc_rx_word_u32; | ||
423 | sspi->tx_word = spi_sirfsoc_tx_word_u32; | ||
424 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
425 | SIRFSOC_SPI_FIFO_WIDTH_DWORD; | ||
426 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | ||
427 | SIRFSOC_SPI_FIFO_WIDTH_DWORD; | ||
428 | break; | ||
429 | default: | ||
430 | dev_err(&spi->dev, "Bits per word %d not supported\n", | ||
431 | bits_per_word); | ||
432 | return -EINVAL; | ||
433 | } | ||
434 | |||
435 | if (!(spi->mode & SPI_CS_HIGH)) | ||
436 | regval |= SIRFSOC_SPI_CS_IDLE_STAT; | ||
437 | if (!(spi->mode & SPI_LSB_FIRST)) | ||
438 | regval |= SIRFSOC_SPI_TRAN_MSB; | ||
439 | if (spi->mode & SPI_CPOL) | ||
440 | regval |= SIRFSOC_SPI_CLK_IDLE_STAT; | ||
441 | |||
442 | /* | ||
443 | * Data should be driven at least 1/2 cycle before the fetch edge to make | ||
444 | * sure that data gets stable at the fetch edge. | ||
445 | */ | ||
446 | if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || | ||
447 | (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) | ||
448 | regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; | ||
449 | else | ||
450 | regval |= SIRFSOC_SPI_DRV_POS_EDGE; | ||
451 | |||
452 | writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) | | ||
453 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | ||
454 | SIRFSOC_SPI_FIFO_HC(2), | ||
455 | sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK); | ||
456 | writel(SIRFSOC_SPI_FIFO_SC(2) | | ||
457 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | ||
458 | SIRFSOC_SPI_FIFO_HC(fifo_size - 2), | ||
459 | sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK); | ||
460 | writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); | ||
461 | writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); | ||
462 | |||
463 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); | ||
464 | return 0; | ||
465 | } | ||
466 | |||
467 | static int spi_sirfsoc_setup(struct spi_device *spi) | ||
468 | { | ||
469 | struct sirfsoc_spi *sspi; | ||
470 | |||
471 | if (!spi->max_speed_hz) | ||
472 | return -EINVAL; | ||
473 | |||
474 | sspi = spi_master_get_devdata(spi->master); | ||
475 | |||
476 | if (!spi->bits_per_word) | ||
477 | spi->bits_per_word = 8; | ||
478 | |||
479 | return spi_sirfsoc_setup_transfer(spi, NULL); | ||
480 | } | ||
481 | |||
482 | static int spi_sirfsoc_probe(struct platform_device *pdev) | ||
483 | { | ||
484 | struct sirfsoc_spi *sspi; | ||
485 | struct spi_master *master; | ||
486 | struct resource *mem_res; | ||
487 | int num_cs, cs_gpio, irq; | ||
488 | int i; | ||
489 | int ret; | ||
490 | |||
491 | ret = of_property_read_u32(pdev->dev.of_node, | ||
492 | "sirf,spi-num-chipselects", &num_cs); | ||
493 | if (ret < 0) { | ||
494 | dev_err(&pdev->dev, "Unable to get chip select number\n"); | ||
495 | goto err_cs; | ||
496 | } | ||
497 | |||
498 | master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs); | ||
499 | if (!master) { | ||
500 | dev_err(&pdev->dev, "Unable to allocate SPI master\n"); | ||
501 | return -ENOMEM; | ||
502 | } | ||
503 | platform_set_drvdata(pdev, master); | ||
504 | sspi = spi_master_get_devdata(master); | ||
505 | |||
506 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
507 | if (!mem_res) { | ||
508 | dev_err(&pdev->dev, "Unable to get IO resource\n"); | ||
509 | ret = -ENODEV; | ||
510 | goto free_master; | ||
511 | } | ||
512 | master->num_chipselect = num_cs; | ||
513 | |||
514 | for (i = 0; i < master->num_chipselect; i++) { | ||
515 | cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i); | ||
516 | if (cs_gpio < 0) { | ||
517 | dev_err(&pdev->dev, "can't get cs gpio from DT\n"); | ||
518 | ret = -ENODEV; | ||
519 | goto free_master; | ||
520 | } | ||
521 | |||
522 | sspi->chipselect[i] = cs_gpio; | ||
523 | if (cs_gpio == 0) | ||
524 | continue; /* use cs from spi controller */ | ||
525 | |||
526 | ret = gpio_request(cs_gpio, DRIVER_NAME); | ||
527 | if (ret) { | ||
528 | while (i > 0) { | ||
529 | i--; | ||
530 | if (sspi->chipselect[i] > 0) | ||
531 | gpio_free(sspi->chipselect[i]); | ||
532 | } | ||
533 | dev_err(&pdev->dev, "fail to request cs gpios\n"); | ||
534 | goto free_master; | ||
535 | } | ||
536 | } | ||
537 | |||
538 | sspi->base = devm_request_and_ioremap(&pdev->dev, mem_res); | ||
539 | if (!sspi->base) { | ||
540 | dev_err(&pdev->dev, "IO remap failed!\n"); | ||
541 | ret = -ENOMEM; | ||
542 | goto free_master; | ||
543 | } | ||
544 | |||
545 | irq = platform_get_irq(pdev, 0); | ||
546 | if (irq < 0) { | ||
547 | ret = -ENXIO; | ||
548 | goto free_master; | ||
549 | } | ||
550 | ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, | ||
551 | DRIVER_NAME, sspi); | ||
552 | if (ret) | ||
553 | goto free_master; | ||
554 | |||
555 | sspi->bitbang.master = spi_master_get(master); | ||
556 | sspi->bitbang.chipselect = spi_sirfsoc_chipselect; | ||
557 | sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; | ||
558 | sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; | ||
559 | sspi->bitbang.master->setup = spi_sirfsoc_setup; | ||
560 | master->bus_num = pdev->id; | ||
561 | sspi->bitbang.master->dev.of_node = pdev->dev.of_node; | ||
562 | |||
563 | sspi->p = pinctrl_get_select_default(&pdev->dev); | ||
564 | ret = IS_ERR(sspi->p); | ||
565 | if (ret) | ||
566 | goto free_master; | ||
567 | |||
568 | sspi->clk = clk_get(&pdev->dev, NULL); | ||
569 | if (IS_ERR(sspi->clk)) { | ||
570 | ret = -EINVAL; | ||
571 | goto free_pin; | ||
572 | } | ||
573 | clk_enable(sspi->clk); | ||
574 | sspi->ctrl_freq = clk_get_rate(sspi->clk); | ||
575 | |||
576 | init_completion(&sspi->done); | ||
577 | |||
578 | tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx, | ||
579 | (unsigned long)sspi); | ||
580 | |||
581 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
582 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
583 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
584 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
585 | /* We are not using dummy delay between command and data */ | ||
586 | writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL); | ||
587 | |||
588 | ret = spi_bitbang_start(&sspi->bitbang); | ||
589 | if (ret) | ||
590 | goto free_clk; | ||
591 | |||
592 | dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num); | ||
593 | |||
594 | return 0; | ||
595 | |||
596 | free_clk: | ||
597 | clk_disable(sspi->clk); | ||
598 | clk_put(sspi->clk); | ||
599 | free_pin: | ||
600 | pinctrl_put(sspi->p); | ||
601 | free_master: | ||
602 | spi_master_put(master); | ||
603 | err_cs: | ||
604 | return ret; | ||
605 | } | ||
606 | |||
607 | static int spi_sirfsoc_remove(struct platform_device *pdev) | ||
608 | { | ||
609 | struct spi_master *master; | ||
610 | struct sirfsoc_spi *sspi; | ||
611 | int i; | ||
612 | |||
613 | master = platform_get_drvdata(pdev); | ||
614 | sspi = spi_master_get_devdata(master); | ||
615 | |||
616 | spi_bitbang_stop(&sspi->bitbang); | ||
617 | for (i = 0; i < master->num_chipselect; i++) { | ||
618 | if (sspi->chipselect[i] > 0) | ||
619 | gpio_free(sspi->chipselect[i]); | ||
620 | } | ||
621 | clk_disable(sspi->clk); | ||
622 | clk_put(sspi->clk); | ||
623 | pinctrl_put(sspi->p); | ||
624 | spi_master_put(master); | ||
625 | return 0; | ||
626 | } | ||
627 | |||
628 | #ifdef CONFIG_PM | ||
629 | static int spi_sirfsoc_suspend(struct device *dev) | ||
630 | { | ||
631 | struct platform_device *pdev = to_platform_device(dev); | ||
632 | struct spi_master *master = platform_get_drvdata(pdev); | ||
633 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); | ||
634 | |||
635 | clk_disable(sspi->clk); | ||
636 | return 0; | ||
637 | } | ||
638 | |||
639 | static int spi_sirfsoc_resume(struct device *dev) | ||
640 | { | ||
641 | struct platform_device *pdev = to_platform_device(dev); | ||
642 | struct spi_master *master = platform_get_drvdata(pdev); | ||
643 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); | ||
644 | |||
645 | clk_enable(sspi->clk); | ||
646 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
647 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
648 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | ||
649 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | ||
650 | |||
651 | return 0; | ||
652 | } | ||
653 | |||
654 | static const struct dev_pm_ops spi_sirfsoc_pm_ops = { | ||
655 | .suspend = spi_sirfsoc_suspend, | ||
656 | .resume = spi_sirfsoc_resume, | ||
657 | }; | ||
658 | #endif | ||
659 | |||
660 | static const struct of_device_id spi_sirfsoc_of_match[] = { | ||
661 | { .compatible = "sirf,prima2-spi", }, | ||
662 | {} | ||
663 | }; | ||
664 | MODULE_DEVICE_TABLE(of, sirfsoc_spi_of_match); | ||
665 | |||
666 | static struct platform_driver spi_sirfsoc_driver = { | ||
667 | .driver = { | ||
668 | .name = DRIVER_NAME, | ||
669 | .owner = THIS_MODULE, | ||
670 | #ifdef CONFIG_PM | ||
671 | .pm = &spi_sirfsoc_pm_ops, | ||
672 | #endif | ||
673 | .of_match_table = spi_sirfsoc_of_match, | ||
674 | }, | ||
675 | .probe = spi_sirfsoc_probe, | ||
676 | .remove = spi_sirfsoc_remove, | ||
677 | }; | ||
678 | module_platform_driver(spi_sirfsoc_driver); | ||
679 | |||
680 | MODULE_DESCRIPTION("SiRF SoC SPI master driver"); | ||
681 | MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, " | ||
682 | "Barry Song <Baohua.Song@csr.com>"); | ||
683 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c deleted file mode 100644 index 448a8cc71df..00000000000 --- a/drivers/spi/spi-tegra20-sflash.c +++ /dev/null | |||
@@ -1,665 +0,0 @@ | |||
1 | /* | ||
2 | * SPI driver for Nvidia's Tegra20 Serial Flash Controller. | ||
3 | * | ||
4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Author: Laxman Dewangan <ldewangan@nvidia.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms and conditions of the GNU General Public License, | ||
10 | * version 2, as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
19 | */ | ||
20 | |||
21 | #include <linux/clk.h> | ||
22 | #include <linux/completion.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/err.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/kernel.h> | ||
29 | #include <linux/kthread.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <linux/platform_device.h> | ||
32 | #include <linux/pm_runtime.h> | ||
33 | #include <linux/of.h> | ||
34 | #include <linux/of_device.h> | ||
35 | #include <linux/spi/spi.h> | ||
36 | #include <linux/spi/spi-tegra.h> | ||
37 | #include <mach/clk.h> | ||
38 | |||
39 | #define SPI_COMMAND 0x000 | ||
40 | #define SPI_GO BIT(30) | ||
41 | #define SPI_M_S BIT(28) | ||
42 | #define SPI_ACTIVE_SCLK_MASK (0x3 << 26) | ||
43 | #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26) | ||
44 | #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26) | ||
45 | #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26) | ||
46 | #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26) | ||
47 | |||
48 | #define SPI_CK_SDA_FALLING (1 << 21) | ||
49 | #define SPI_CK_SDA_RISING (0 << 21) | ||
50 | #define SPI_CK_SDA_MASK (1 << 21) | ||
51 | #define SPI_ACTIVE_SDA (0x3 << 18) | ||
52 | #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18) | ||
53 | #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18) | ||
54 | #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18) | ||
55 | #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18) | ||
56 | |||
57 | #define SPI_CS_POL_INVERT BIT(16) | ||
58 | #define SPI_TX_EN BIT(15) | ||
59 | #define SPI_RX_EN BIT(14) | ||
60 | #define SPI_CS_VAL_HIGH BIT(13) | ||
61 | #define SPI_CS_VAL_LOW 0x0 | ||
62 | #define SPI_CS_SW BIT(12) | ||
63 | #define SPI_CS_HW 0x0 | ||
64 | #define SPI_CS_DELAY_MASK (7 << 9) | ||
65 | #define SPI_CS3_EN BIT(8) | ||
66 | #define SPI_CS2_EN BIT(7) | ||
67 | #define SPI_CS1_EN BIT(6) | ||
68 | #define SPI_CS0_EN BIT(5) | ||
69 | |||
70 | #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \ | ||
71 | SPI_CS1_EN | SPI_CS0_EN) | ||
72 | #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) | ||
73 | |||
74 | #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK) | ||
75 | |||
76 | #define SPI_STATUS 0x004 | ||
77 | #define SPI_BSY BIT(31) | ||
78 | #define SPI_RDY BIT(30) | ||
79 | #define SPI_TXF_FLUSH BIT(29) | ||
80 | #define SPI_RXF_FLUSH BIT(28) | ||
81 | #define SPI_RX_UNF BIT(27) | ||
82 | #define SPI_TX_OVF BIT(26) | ||
83 | #define SPI_RXF_EMPTY BIT(25) | ||
84 | #define SPI_RXF_FULL BIT(24) | ||
85 | #define SPI_TXF_EMPTY BIT(23) | ||
86 | #define SPI_TXF_FULL BIT(22) | ||
87 | #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1) | ||
88 | |||
89 | #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF) | ||
90 | #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY) | ||
91 | |||
92 | #define SPI_RX_CMP 0x8 | ||
93 | #define SPI_DMA_CTL 0x0C | ||
94 | #define SPI_DMA_EN BIT(31) | ||
95 | #define SPI_IE_RXC BIT(27) | ||
96 | #define SPI_IE_TXC BIT(26) | ||
97 | #define SPI_PACKED BIT(20) | ||
98 | #define SPI_RX_TRIG_MASK (0x3 << 18) | ||
99 | #define SPI_RX_TRIG_1W (0x0 << 18) | ||
100 | #define SPI_RX_TRIG_4W (0x1 << 18) | ||
101 | #define SPI_TX_TRIG_MASK (0x3 << 16) | ||
102 | #define SPI_TX_TRIG_1W (0x0 << 16) | ||
103 | #define SPI_TX_TRIG_4W (0x1 << 16) | ||
104 | #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF); | ||
105 | |||
106 | #define SPI_TX_FIFO 0x10 | ||
107 | #define SPI_RX_FIFO 0x20 | ||
108 | |||
109 | #define DATA_DIR_TX (1 << 0) | ||
110 | #define DATA_DIR_RX (1 << 1) | ||
111 | |||
112 | #define MAX_CHIP_SELECT 4 | ||
113 | #define SPI_FIFO_DEPTH 4 | ||
114 | #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) | ||
115 | |||
116 | struct tegra_sflash_data { | ||
117 | struct device *dev; | ||
118 | struct spi_master *master; | ||
119 | spinlock_t lock; | ||
120 | |||
121 | struct clk *clk; | ||
122 | void __iomem *base; | ||
123 | unsigned irq; | ||
124 | u32 spi_max_frequency; | ||
125 | u32 cur_speed; | ||
126 | |||
127 | struct spi_device *cur_spi; | ||
128 | unsigned cur_pos; | ||
129 | unsigned cur_len; | ||
130 | unsigned bytes_per_word; | ||
131 | unsigned cur_direction; | ||
132 | unsigned curr_xfer_words; | ||
133 | |||
134 | unsigned cur_rx_pos; | ||
135 | unsigned cur_tx_pos; | ||
136 | |||
137 | u32 tx_status; | ||
138 | u32 rx_status; | ||
139 | u32 status_reg; | ||
140 | |||
141 | u32 def_command_reg; | ||
142 | u32 command_reg; | ||
143 | u32 dma_control_reg; | ||
144 | |||
145 | struct completion xfer_completion; | ||
146 | struct spi_transfer *curr_xfer; | ||
147 | }; | ||
148 | |||
149 | static int tegra_sflash_runtime_suspend(struct device *dev); | ||
150 | static int tegra_sflash_runtime_resume(struct device *dev); | ||
151 | |||
152 | static inline unsigned long tegra_sflash_readl(struct tegra_sflash_data *tsd, | ||
153 | unsigned long reg) | ||
154 | { | ||
155 | return readl(tsd->base + reg); | ||
156 | } | ||
157 | |||
158 | static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd, | ||
159 | unsigned long val, unsigned long reg) | ||
160 | { | ||
161 | writel(val, tsd->base + reg); | ||
162 | } | ||
163 | |||
164 | static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd) | ||
165 | { | ||
166 | /* Write 1 to clear status register */ | ||
167 | tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS); | ||
168 | } | ||
169 | |||
170 | static unsigned tegra_sflash_calculate_curr_xfer_param( | ||
171 | struct spi_device *spi, struct tegra_sflash_data *tsd, | ||
172 | struct spi_transfer *t) | ||
173 | { | ||
174 | unsigned remain_len = t->len - tsd->cur_pos; | ||
175 | unsigned max_word; | ||
176 | |||
177 | tsd->bytes_per_word = (t->bits_per_word - 1) / 8 + 1; | ||
178 | max_word = remain_len / tsd->bytes_per_word; | ||
179 | if (max_word > SPI_FIFO_DEPTH) | ||
180 | max_word = SPI_FIFO_DEPTH; | ||
181 | tsd->curr_xfer_words = max_word; | ||
182 | return max_word; | ||
183 | } | ||
184 | |||
185 | static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf( | ||
186 | struct tegra_sflash_data *tsd, struct spi_transfer *t) | ||
187 | { | ||
188 | unsigned nbytes; | ||
189 | unsigned long status; | ||
190 | unsigned max_n_32bit = tsd->curr_xfer_words; | ||
191 | u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos; | ||
192 | |||
193 | if (max_n_32bit > SPI_FIFO_DEPTH) | ||
194 | max_n_32bit = SPI_FIFO_DEPTH; | ||
195 | nbytes = max_n_32bit * tsd->bytes_per_word; | ||
196 | |||
197 | status = tegra_sflash_readl(tsd, SPI_STATUS); | ||
198 | while (!(status & SPI_TXF_FULL)) { | ||
199 | int i; | ||
200 | unsigned int x = 0; | ||
201 | |||
202 | for (i = 0; nbytes && (i < tsd->bytes_per_word); | ||
203 | i++, nbytes--) | ||
204 | x |= ((*tx_buf++) << i*8); | ||
205 | tegra_sflash_writel(tsd, x, SPI_TX_FIFO); | ||
206 | if (!nbytes) | ||
207 | break; | ||
208 | |||
209 | status = tegra_sflash_readl(tsd, SPI_STATUS); | ||
210 | } | ||
211 | tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word; | ||
212 | return max_n_32bit; | ||
213 | } | ||
214 | |||
215 | static int tegra_sflash_read_rx_fifo_to_client_rxbuf( | ||
216 | struct tegra_sflash_data *tsd, struct spi_transfer *t) | ||
217 | { | ||
218 | unsigned long status; | ||
219 | unsigned int read_words = 0; | ||
220 | u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos; | ||
221 | |||
222 | status = tegra_sflash_readl(tsd, SPI_STATUS); | ||
223 | while (!(status & SPI_RXF_EMPTY)) { | ||
224 | int i; | ||
225 | unsigned long x; | ||
226 | |||
227 | x = tegra_sflash_readl(tsd, SPI_RX_FIFO); | ||
228 | for (i = 0; (i < tsd->bytes_per_word); i++) | ||
229 | *rx_buf++ = (x >> (i*8)) & 0xFF; | ||
230 | read_words++; | ||
231 | status = tegra_sflash_readl(tsd, SPI_STATUS); | ||
232 | } | ||
233 | tsd->cur_rx_pos += read_words * tsd->bytes_per_word; | ||
234 | return 0; | ||
235 | } | ||
236 | |||
237 | static int tegra_sflash_start_cpu_based_transfer( | ||
238 | struct tegra_sflash_data *tsd, struct spi_transfer *t) | ||
239 | { | ||
240 | unsigned long val = 0; | ||
241 | unsigned cur_words; | ||
242 | |||
243 | if (tsd->cur_direction & DATA_DIR_TX) | ||
244 | val |= SPI_IE_TXC; | ||
245 | |||
246 | if (tsd->cur_direction & DATA_DIR_RX) | ||
247 | val |= SPI_IE_RXC; | ||
248 | |||
249 | tegra_sflash_writel(tsd, val, SPI_DMA_CTL); | ||
250 | tsd->dma_control_reg = val; | ||
251 | |||
252 | if (tsd->cur_direction & DATA_DIR_TX) | ||
253 | cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t); | ||
254 | else | ||
255 | cur_words = tsd->curr_xfer_words; | ||
256 | val |= SPI_DMA_BLK_COUNT(cur_words); | ||
257 | tegra_sflash_writel(tsd, val, SPI_DMA_CTL); | ||
258 | tsd->dma_control_reg = val; | ||
259 | val |= SPI_DMA_EN; | ||
260 | tegra_sflash_writel(tsd, val, SPI_DMA_CTL); | ||
261 | return 0; | ||
262 | } | ||
263 | |||
264 | static int tegra_sflash_start_transfer_one(struct spi_device *spi, | ||
265 | struct spi_transfer *t, bool is_first_of_msg, | ||
266 | bool is_single_xfer) | ||
267 | { | ||
268 | struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); | ||
269 | u32 speed; | ||
270 | unsigned long command; | ||
271 | |||
272 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | ||
273 | if (!speed) | ||
274 | speed = tsd->spi_max_frequency; | ||
275 | if (speed != tsd->cur_speed) { | ||
276 | clk_set_rate(tsd->clk, speed); | ||
277 | tsd->cur_speed = speed; | ||
278 | } | ||
279 | |||
280 | tsd->cur_spi = spi; | ||
281 | tsd->cur_pos = 0; | ||
282 | tsd->cur_rx_pos = 0; | ||
283 | tsd->cur_tx_pos = 0; | ||
284 | tsd->curr_xfer = t; | ||
285 | tegra_sflash_calculate_curr_xfer_param(spi, tsd, t); | ||
286 | if (is_first_of_msg) { | ||
287 | command = tsd->def_command_reg; | ||
288 | command |= SPI_BIT_LENGTH(t->bits_per_word - 1); | ||
289 | command |= SPI_CS_VAL_HIGH; | ||
290 | |||
291 | command &= ~SPI_MODES; | ||
292 | if (spi->mode & SPI_CPHA) | ||
293 | command |= SPI_CK_SDA_FALLING; | ||
294 | |||
295 | if (spi->mode & SPI_CPOL) | ||
296 | command |= SPI_ACTIVE_SCLK_DRIVE_HIGH; | ||
297 | else | ||
298 | command |= SPI_ACTIVE_SCLK_DRIVE_LOW; | ||
299 | command |= SPI_CS0_EN << spi->chip_select; | ||
300 | } else { | ||
301 | command = tsd->command_reg; | ||
302 | command &= ~SPI_BIT_LENGTH(~0); | ||
303 | command |= SPI_BIT_LENGTH(t->bits_per_word - 1); | ||
304 | command &= ~(SPI_RX_EN | SPI_TX_EN); | ||
305 | } | ||
306 | |||
307 | tsd->cur_direction = 0; | ||
308 | if (t->rx_buf) { | ||
309 | command |= SPI_RX_EN; | ||
310 | tsd->cur_direction |= DATA_DIR_RX; | ||
311 | } | ||
312 | if (t->tx_buf) { | ||
313 | command |= SPI_TX_EN; | ||
314 | tsd->cur_direction |= DATA_DIR_TX; | ||
315 | } | ||
316 | tegra_sflash_writel(tsd, command, SPI_COMMAND); | ||
317 | tsd->command_reg = command; | ||
318 | |||
319 | return tegra_sflash_start_cpu_based_transfer(tsd, t); | ||
320 | } | ||
321 | |||
322 | static int tegra_sflash_transfer_one_message(struct spi_master *master, | ||
323 | struct spi_message *msg) | ||
324 | { | ||
325 | bool is_first_msg = true; | ||
326 | int single_xfer; | ||
327 | struct tegra_sflash_data *tsd = spi_master_get_devdata(master); | ||
328 | struct spi_transfer *xfer; | ||
329 | struct spi_device *spi = msg->spi; | ||
330 | int ret; | ||
331 | |||
332 | ret = pm_runtime_get_sync(tsd->dev); | ||
333 | if (ret < 0) { | ||
334 | dev_err(tsd->dev, "pm_runtime_get() failed, err = %d\n", ret); | ||
335 | return ret; | ||
336 | } | ||
337 | |||
338 | msg->status = 0; | ||
339 | msg->actual_length = 0; | ||
340 | single_xfer = list_is_singular(&msg->transfers); | ||
341 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
342 | INIT_COMPLETION(tsd->xfer_completion); | ||
343 | ret = tegra_sflash_start_transfer_one(spi, xfer, | ||
344 | is_first_msg, single_xfer); | ||
345 | if (ret < 0) { | ||
346 | dev_err(tsd->dev, | ||
347 | "spi can not start transfer, err %d\n", ret); | ||
348 | goto exit; | ||
349 | } | ||
350 | is_first_msg = false; | ||
351 | ret = wait_for_completion_timeout(&tsd->xfer_completion, | ||
352 | SPI_DMA_TIMEOUT); | ||
353 | if (WARN_ON(ret == 0)) { | ||
354 | dev_err(tsd->dev, | ||
355 | "spi trasfer timeout, err %d\n", ret); | ||
356 | ret = -EIO; | ||
357 | goto exit; | ||
358 | } | ||
359 | |||
360 | if (tsd->tx_status || tsd->rx_status) { | ||
361 | dev_err(tsd->dev, "Error in Transfer\n"); | ||
362 | ret = -EIO; | ||
363 | goto exit; | ||
364 | } | ||
365 | msg->actual_length += xfer->len; | ||
366 | if (xfer->cs_change && xfer->delay_usecs) { | ||
367 | tegra_sflash_writel(tsd, tsd->def_command_reg, | ||
368 | SPI_COMMAND); | ||
369 | udelay(xfer->delay_usecs); | ||
370 | } | ||
371 | } | ||
372 | ret = 0; | ||
373 | exit: | ||
374 | tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); | ||
375 | msg->status = ret; | ||
376 | spi_finalize_current_message(master); | ||
377 | pm_runtime_put(tsd->dev); | ||
378 | return ret; | ||
379 | } | ||
380 | |||
381 | static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd) | ||
382 | { | ||
383 | struct spi_transfer *t = tsd->curr_xfer; | ||
384 | unsigned long flags; | ||
385 | |||
386 | spin_lock_irqsave(&tsd->lock, flags); | ||
387 | if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) { | ||
388 | dev_err(tsd->dev, | ||
389 | "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg); | ||
390 | dev_err(tsd->dev, | ||
391 | "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, | ||
392 | tsd->dma_control_reg); | ||
393 | tegra_periph_reset_assert(tsd->clk); | ||
394 | udelay(2); | ||
395 | tegra_periph_reset_deassert(tsd->clk); | ||
396 | complete(&tsd->xfer_completion); | ||
397 | goto exit; | ||
398 | } | ||
399 | |||
400 | if (tsd->cur_direction & DATA_DIR_RX) | ||
401 | tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t); | ||
402 | |||
403 | if (tsd->cur_direction & DATA_DIR_TX) | ||
404 | tsd->cur_pos = tsd->cur_tx_pos; | ||
405 | else | ||
406 | tsd->cur_pos = tsd->cur_rx_pos; | ||
407 | |||
408 | if (tsd->cur_pos == t->len) { | ||
409 | complete(&tsd->xfer_completion); | ||
410 | goto exit; | ||
411 | } | ||
412 | |||
413 | tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t); | ||
414 | tegra_sflash_start_cpu_based_transfer(tsd, t); | ||
415 | exit: | ||
416 | spin_unlock_irqrestore(&tsd->lock, flags); | ||
417 | return IRQ_HANDLED; | ||
418 | } | ||
419 | |||
420 | static irqreturn_t tegra_sflash_isr(int irq, void *context_data) | ||
421 | { | ||
422 | struct tegra_sflash_data *tsd = context_data; | ||
423 | |||
424 | tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS); | ||
425 | if (tsd->cur_direction & DATA_DIR_TX) | ||
426 | tsd->tx_status = tsd->status_reg & SPI_TX_OVF; | ||
427 | |||
428 | if (tsd->cur_direction & DATA_DIR_RX) | ||
429 | tsd->rx_status = tsd->status_reg & SPI_RX_UNF; | ||
430 | tegra_sflash_clear_status(tsd); | ||
431 | |||
432 | return handle_cpu_based_xfer(tsd); | ||
433 | } | ||
434 | |||
435 | static struct tegra_spi_platform_data *tegra_sflash_parse_dt( | ||
436 | struct platform_device *pdev) | ||
437 | { | ||
438 | struct tegra_spi_platform_data *pdata; | ||
439 | struct device_node *np = pdev->dev.of_node; | ||
440 | u32 max_freq; | ||
441 | |||
442 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
443 | if (!pdata) { | ||
444 | dev_err(&pdev->dev, "Memory alloc for pdata failed\n"); | ||
445 | return NULL; | ||
446 | } | ||
447 | |||
448 | if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) | ||
449 | pdata->spi_max_frequency = max_freq; | ||
450 | |||
451 | return pdata; | ||
452 | } | ||
453 | |||
454 | static struct of_device_id tegra_sflash_of_match[] = { | ||
455 | { .compatible = "nvidia,tegra20-sflash", }, | ||
456 | {} | ||
457 | }; | ||
458 | MODULE_DEVICE_TABLE(of, tegra_sflash_of_match); | ||
459 | |||
460 | static int tegra_sflash_probe(struct platform_device *pdev) | ||
461 | { | ||
462 | struct spi_master *master; | ||
463 | struct tegra_sflash_data *tsd; | ||
464 | struct resource *r; | ||
465 | struct tegra_spi_platform_data *pdata = pdev->dev.platform_data; | ||
466 | int ret; | ||
467 | const struct of_device_id *match; | ||
468 | |||
469 | match = of_match_device(of_match_ptr(tegra_sflash_of_match), | ||
470 | &pdev->dev); | ||
471 | if (!match) { | ||
472 | dev_err(&pdev->dev, "Error: No device match found\n"); | ||
473 | return -ENODEV; | ||
474 | } | ||
475 | |||
476 | if (!pdata && pdev->dev.of_node) | ||
477 | pdata = tegra_sflash_parse_dt(pdev); | ||
478 | |||
479 | if (!pdata) { | ||
480 | dev_err(&pdev->dev, "No platform data, exiting\n"); | ||
481 | return -ENODEV; | ||
482 | } | ||
483 | |||
484 | if (!pdata->spi_max_frequency) | ||
485 | pdata->spi_max_frequency = 25000000; /* 25MHz */ | ||
486 | |||
487 | master = spi_alloc_master(&pdev->dev, sizeof(*tsd)); | ||
488 | if (!master) { | ||
489 | dev_err(&pdev->dev, "master allocation failed\n"); | ||
490 | return -ENOMEM; | ||
491 | } | ||
492 | |||
493 | /* the spi->mode bits understood by this driver: */ | ||
494 | master->mode_bits = SPI_CPOL | SPI_CPHA; | ||
495 | master->transfer_one_message = tegra_sflash_transfer_one_message; | ||
496 | master->num_chipselect = MAX_CHIP_SELECT; | ||
497 | master->bus_num = -1; | ||
498 | |||
499 | dev_set_drvdata(&pdev->dev, master); | ||
500 | tsd = spi_master_get_devdata(master); | ||
501 | tsd->master = master; | ||
502 | tsd->dev = &pdev->dev; | ||
503 | spin_lock_init(&tsd->lock); | ||
504 | |||
505 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
506 | if (!r) { | ||
507 | dev_err(&pdev->dev, "No IO memory resource\n"); | ||
508 | ret = -ENODEV; | ||
509 | goto exit_free_master; | ||
510 | } | ||
511 | tsd->base = devm_request_and_ioremap(&pdev->dev, r); | ||
512 | if (!tsd->base) { | ||
513 | dev_err(&pdev->dev, | ||
514 | "Cannot request memregion/iomap dma address\n"); | ||
515 | ret = -EADDRNOTAVAIL; | ||
516 | goto exit_free_master; | ||
517 | } | ||
518 | |||
519 | tsd->irq = platform_get_irq(pdev, 0); | ||
520 | ret = request_irq(tsd->irq, tegra_sflash_isr, 0, | ||
521 | dev_name(&pdev->dev), tsd); | ||
522 | if (ret < 0) { | ||
523 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", | ||
524 | tsd->irq); | ||
525 | goto exit_free_master; | ||
526 | } | ||
527 | |||
528 | tsd->clk = devm_clk_get(&pdev->dev, "spi"); | ||
529 | if (IS_ERR(tsd->clk)) { | ||
530 | dev_err(&pdev->dev, "can not get clock\n"); | ||
531 | ret = PTR_ERR(tsd->clk); | ||
532 | goto exit_free_irq; | ||
533 | } | ||
534 | |||
535 | tsd->spi_max_frequency = pdata->spi_max_frequency; | ||
536 | init_completion(&tsd->xfer_completion); | ||
537 | pm_runtime_enable(&pdev->dev); | ||
538 | if (!pm_runtime_enabled(&pdev->dev)) { | ||
539 | ret = tegra_sflash_runtime_resume(&pdev->dev); | ||
540 | if (ret) | ||
541 | goto exit_pm_disable; | ||
542 | } | ||
543 | |||
544 | ret = pm_runtime_get_sync(&pdev->dev); | ||
545 | if (ret < 0) { | ||
546 | dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); | ||
547 | goto exit_pm_disable; | ||
548 | } | ||
549 | |||
550 | /* Reset controller */ | ||
551 | tegra_periph_reset_assert(tsd->clk); | ||
552 | udelay(2); | ||
553 | tegra_periph_reset_deassert(tsd->clk); | ||
554 | |||
555 | tsd->def_command_reg = SPI_M_S | SPI_CS_SW; | ||
556 | tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); | ||
557 | pm_runtime_put(&pdev->dev); | ||
558 | |||
559 | master->dev.of_node = pdev->dev.of_node; | ||
560 | ret = spi_register_master(master); | ||
561 | if (ret < 0) { | ||
562 | dev_err(&pdev->dev, "can not register to master err %d\n", ret); | ||
563 | goto exit_pm_disable; | ||
564 | } | ||
565 | return ret; | ||
566 | |||
567 | exit_pm_disable: | ||
568 | pm_runtime_disable(&pdev->dev); | ||
569 | if (!pm_runtime_status_suspended(&pdev->dev)) | ||
570 | tegra_sflash_runtime_suspend(&pdev->dev); | ||
571 | exit_free_irq: | ||
572 | free_irq(tsd->irq, tsd); | ||
573 | exit_free_master: | ||
574 | spi_master_put(master); | ||
575 | return ret; | ||
576 | } | ||
577 | |||
578 | static int tegra_sflash_remove(struct platform_device *pdev) | ||
579 | { | ||
580 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | ||
581 | struct tegra_sflash_data *tsd = spi_master_get_devdata(master); | ||
582 | |||
583 | free_irq(tsd->irq, tsd); | ||
584 | spi_unregister_master(master); | ||
585 | |||
586 | pm_runtime_disable(&pdev->dev); | ||
587 | if (!pm_runtime_status_suspended(&pdev->dev)) | ||
588 | tegra_sflash_runtime_suspend(&pdev->dev); | ||
589 | |||
590 | return 0; | ||
591 | } | ||
592 | |||
593 | #ifdef CONFIG_PM_SLEEP | ||
594 | static int tegra_sflash_suspend(struct device *dev) | ||
595 | { | ||
596 | struct spi_master *master = dev_get_drvdata(dev); | ||
597 | |||
598 | return spi_master_suspend(master); | ||
599 | } | ||
600 | |||
601 | static int tegra_sflash_resume(struct device *dev) | ||
602 | { | ||
603 | struct spi_master *master = dev_get_drvdata(dev); | ||
604 | struct tegra_sflash_data *tsd = spi_master_get_devdata(master); | ||
605 | int ret; | ||
606 | |||
607 | ret = pm_runtime_get_sync(dev); | ||
608 | if (ret < 0) { | ||
609 | dev_err(dev, "pm runtime failed, e = %d\n", ret); | ||
610 | return ret; | ||
611 | } | ||
612 | tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND); | ||
613 | pm_runtime_put(dev); | ||
614 | |||
615 | return spi_master_resume(master); | ||
616 | } | ||
617 | #endif | ||
618 | |||
619 | static int tegra_sflash_runtime_suspend(struct device *dev) | ||
620 | { | ||
621 | struct spi_master *master = dev_get_drvdata(dev); | ||
622 | struct tegra_sflash_data *tsd = spi_master_get_devdata(master); | ||
623 | |||
624 | /* Flush all write which are in PPSB queue by reading back */ | ||
625 | tegra_sflash_readl(tsd, SPI_COMMAND); | ||
626 | |||
627 | clk_disable_unprepare(tsd->clk); | ||
628 | return 0; | ||
629 | } | ||
630 | |||
631 | static int tegra_sflash_runtime_resume(struct device *dev) | ||
632 | { | ||
633 | struct spi_master *master = dev_get_drvdata(dev); | ||
634 | struct tegra_sflash_data *tsd = spi_master_get_devdata(master); | ||
635 | int ret; | ||
636 | |||
637 | ret = clk_prepare_enable(tsd->clk); | ||
638 | if (ret < 0) { | ||
639 | dev_err(tsd->dev, "clk_prepare failed: %d\n", ret); | ||
640 | return ret; | ||
641 | } | ||
642 | return 0; | ||
643 | } | ||
644 | |||
645 | static const struct dev_pm_ops slink_pm_ops = { | ||
646 | SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend, | ||
647 | tegra_sflash_runtime_resume, NULL) | ||
648 | SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume) | ||
649 | }; | ||
650 | static struct platform_driver tegra_sflash_driver = { | ||
651 | .driver = { | ||
652 | .name = "spi-tegra-sflash", | ||
653 | .owner = THIS_MODULE, | ||
654 | .pm = &slink_pm_ops, | ||
655 | .of_match_table = of_match_ptr(tegra_sflash_of_match), | ||
656 | }, | ||
657 | .probe = tegra_sflash_probe, | ||
658 | .remove = tegra_sflash_remove, | ||
659 | }; | ||
660 | module_platform_driver(tegra_sflash_driver); | ||
661 | |||
662 | MODULE_ALIAS("platform:spi-tegra-sflash"); | ||
663 | MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver"); | ||
664 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | ||
665 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c deleted file mode 100644 index 651167f2e0a..00000000000 --- a/drivers/spi/spi-tegra20-slink.c +++ /dev/null | |||
@@ -1,1358 +0,0 @@ | |||
1 | /* | ||
2 | * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. | ||
3 | * | ||
4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/completion.h> | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/dmaengine.h> | ||
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/dmapool.h> | ||
25 | #include <linux/err.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/interrupt.h> | ||
28 | #include <linux/io.h> | ||
29 | #include <linux/kernel.h> | ||
30 | #include <linux/kthread.h> | ||
31 | #include <linux/module.h> | ||
32 | #include <linux/platform_device.h> | ||
33 | #include <linux/pm_runtime.h> | ||
34 | #include <linux/of.h> | ||
35 | #include <linux/of_device.h> | ||
36 | #include <linux/spi/spi.h> | ||
37 | #include <linux/spi/spi-tegra.h> | ||
38 | #include <mach/clk.h> | ||
39 | |||
40 | #define SLINK_COMMAND 0x000 | ||
41 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | ||
42 | #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) | ||
43 | #define SLINK_BOTH_EN (1 << 10) | ||
44 | #define SLINK_CS_SW (1 << 11) | ||
45 | #define SLINK_CS_VALUE (1 << 12) | ||
46 | #define SLINK_CS_POLARITY (1 << 13) | ||
47 | #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) | ||
48 | #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) | ||
49 | #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) | ||
50 | #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) | ||
51 | #define SLINK_IDLE_SDA_MASK (3 << 16) | ||
52 | #define SLINK_CS_POLARITY1 (1 << 20) | ||
53 | #define SLINK_CK_SDA (1 << 21) | ||
54 | #define SLINK_CS_POLARITY2 (1 << 22) | ||
55 | #define SLINK_CS_POLARITY3 (1 << 23) | ||
56 | #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) | ||
57 | #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) | ||
58 | #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) | ||
59 | #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) | ||
60 | #define SLINK_IDLE_SCLK_MASK (3 << 24) | ||
61 | #define SLINK_M_S (1 << 28) | ||
62 | #define SLINK_WAIT (1 << 29) | ||
63 | #define SLINK_GO (1 << 30) | ||
64 | #define SLINK_ENB (1 << 31) | ||
65 | |||
66 | #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) | ||
67 | |||
68 | #define SLINK_COMMAND2 0x004 | ||
69 | #define SLINK_LSBFE (1 << 0) | ||
70 | #define SLINK_SSOE (1 << 1) | ||
71 | #define SLINK_SPIE (1 << 4) | ||
72 | #define SLINK_BIDIROE (1 << 6) | ||
73 | #define SLINK_MODFEN (1 << 7) | ||
74 | #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) | ||
75 | #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) | ||
76 | #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) | ||
77 | #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) | ||
78 | #define SLINK_FIFO_REFILLS_0 (0 << 22) | ||
79 | #define SLINK_FIFO_REFILLS_1 (1 << 22) | ||
80 | #define SLINK_FIFO_REFILLS_2 (2 << 22) | ||
81 | #define SLINK_FIFO_REFILLS_3 (3 << 22) | ||
82 | #define SLINK_FIFO_REFILLS_MASK (3 << 22) | ||
83 | #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) | ||
84 | #define SLINK_SPC0 (1 << 29) | ||
85 | #define SLINK_TXEN (1 << 30) | ||
86 | #define SLINK_RXEN (1 << 31) | ||
87 | |||
88 | #define SLINK_STATUS 0x008 | ||
89 | #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) | ||
90 | #define SLINK_WORD(val) (((val) >> 5) & 0x1f) | ||
91 | #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) | ||
92 | #define SLINK_MODF (1 << 16) | ||
93 | #define SLINK_RX_UNF (1 << 18) | ||
94 | #define SLINK_TX_OVF (1 << 19) | ||
95 | #define SLINK_TX_FULL (1 << 20) | ||
96 | #define SLINK_TX_EMPTY (1 << 21) | ||
97 | #define SLINK_RX_FULL (1 << 22) | ||
98 | #define SLINK_RX_EMPTY (1 << 23) | ||
99 | #define SLINK_TX_UNF (1 << 24) | ||
100 | #define SLINK_RX_OVF (1 << 25) | ||
101 | #define SLINK_TX_FLUSH (1 << 26) | ||
102 | #define SLINK_RX_FLUSH (1 << 27) | ||
103 | #define SLINK_SCLK (1 << 28) | ||
104 | #define SLINK_ERR (1 << 29) | ||
105 | #define SLINK_RDY (1 << 30) | ||
106 | #define SLINK_BSY (1 << 31) | ||
107 | #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ | ||
108 | SLINK_TX_UNF | SLINK_RX_OVF) | ||
109 | |||
110 | #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) | ||
111 | |||
112 | #define SLINK_MAS_DATA 0x010 | ||
113 | #define SLINK_SLAVE_DATA 0x014 | ||
114 | |||
115 | #define SLINK_DMA_CTL 0x018 | ||
116 | #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) | ||
117 | #define SLINK_TX_TRIG_1 (0 << 16) | ||
118 | #define SLINK_TX_TRIG_4 (1 << 16) | ||
119 | #define SLINK_TX_TRIG_8 (2 << 16) | ||
120 | #define SLINK_TX_TRIG_16 (3 << 16) | ||
121 | #define SLINK_TX_TRIG_MASK (3 << 16) | ||
122 | #define SLINK_RX_TRIG_1 (0 << 18) | ||
123 | #define SLINK_RX_TRIG_4 (1 << 18) | ||
124 | #define SLINK_RX_TRIG_8 (2 << 18) | ||
125 | #define SLINK_RX_TRIG_16 (3 << 18) | ||
126 | #define SLINK_RX_TRIG_MASK (3 << 18) | ||
127 | #define SLINK_PACKED (1 << 20) | ||
128 | #define SLINK_PACK_SIZE_4 (0 << 21) | ||
129 | #define SLINK_PACK_SIZE_8 (1 << 21) | ||
130 | #define SLINK_PACK_SIZE_16 (2 << 21) | ||
131 | #define SLINK_PACK_SIZE_32 (3 << 21) | ||
132 | #define SLINK_PACK_SIZE_MASK (3 << 21) | ||
133 | #define SLINK_IE_TXC (1 << 26) | ||
134 | #define SLINK_IE_RXC (1 << 27) | ||
135 | #define SLINK_DMA_EN (1 << 31) | ||
136 | |||
137 | #define SLINK_STATUS2 0x01c | ||
138 | #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) | ||
139 | #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) | ||
140 | #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) | ||
141 | |||
142 | #define SLINK_TX_FIFO 0x100 | ||
143 | #define SLINK_RX_FIFO 0x180 | ||
144 | |||
145 | #define DATA_DIR_TX (1 << 0) | ||
146 | #define DATA_DIR_RX (1 << 1) | ||
147 | |||
148 | #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) | ||
149 | |||
150 | #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) | ||
151 | #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) | ||
152 | #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) | ||
153 | |||
154 | #define SLINK_STATUS2_RESET \ | ||
155 | (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) | ||
156 | |||
157 | #define MAX_CHIP_SELECT 4 | ||
158 | #define SLINK_FIFO_DEPTH 32 | ||
159 | |||
160 | struct tegra_slink_chip_data { | ||
161 | bool cs_hold_time; | ||
162 | }; | ||
163 | |||
164 | struct tegra_slink_data { | ||
165 | struct device *dev; | ||
166 | struct spi_master *master; | ||
167 | const struct tegra_slink_chip_data *chip_data; | ||
168 | spinlock_t lock; | ||
169 | |||
170 | struct clk *clk; | ||
171 | void __iomem *base; | ||
172 | phys_addr_t phys; | ||
173 | unsigned irq; | ||
174 | int dma_req_sel; | ||
175 | u32 spi_max_frequency; | ||
176 | u32 cur_speed; | ||
177 | |||
178 | struct spi_device *cur_spi; | ||
179 | unsigned cur_pos; | ||
180 | unsigned cur_len; | ||
181 | unsigned words_per_32bit; | ||
182 | unsigned bytes_per_word; | ||
183 | unsigned curr_dma_words; | ||
184 | unsigned cur_direction; | ||
185 | |||
186 | unsigned cur_rx_pos; | ||
187 | unsigned cur_tx_pos; | ||
188 | |||
189 | unsigned dma_buf_size; | ||
190 | unsigned max_buf_size; | ||
191 | bool is_curr_dma_xfer; | ||
192 | bool is_hw_based_cs; | ||
193 | |||
194 | struct completion rx_dma_complete; | ||
195 | struct completion tx_dma_complete; | ||
196 | |||
197 | u32 tx_status; | ||
198 | u32 rx_status; | ||
199 | u32 status_reg; | ||
200 | bool is_packed; | ||
201 | unsigned long packed_size; | ||
202 | |||
203 | u32 command_reg; | ||
204 | u32 command2_reg; | ||
205 | u32 dma_control_reg; | ||
206 | u32 def_command_reg; | ||
207 | u32 def_command2_reg; | ||
208 | |||
209 | struct completion xfer_completion; | ||
210 | struct spi_transfer *curr_xfer; | ||
211 | struct dma_chan *rx_dma_chan; | ||
212 | u32 *rx_dma_buf; | ||
213 | dma_addr_t rx_dma_phys; | ||
214 | struct dma_async_tx_descriptor *rx_dma_desc; | ||
215 | |||
216 | struct dma_chan *tx_dma_chan; | ||
217 | u32 *tx_dma_buf; | ||
218 | dma_addr_t tx_dma_phys; | ||
219 | struct dma_async_tx_descriptor *tx_dma_desc; | ||
220 | }; | ||
221 | |||
222 | static int tegra_slink_runtime_suspend(struct device *dev); | ||
223 | static int tegra_slink_runtime_resume(struct device *dev); | ||
224 | |||
225 | static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi, | ||
226 | unsigned long reg) | ||
227 | { | ||
228 | return readl(tspi->base + reg); | ||
229 | } | ||
230 | |||
231 | static inline void tegra_slink_writel(struct tegra_slink_data *tspi, | ||
232 | unsigned long val, unsigned long reg) | ||
233 | { | ||
234 | writel(val, tspi->base + reg); | ||
235 | |||
236 | /* Read back register to make sure that register writes completed */ | ||
237 | if (reg != SLINK_TX_FIFO) | ||
238 | readl(tspi->base + SLINK_MAS_DATA); | ||
239 | } | ||
240 | |||
241 | static void tegra_slink_clear_status(struct tegra_slink_data *tspi) | ||
242 | { | ||
243 | unsigned long val; | ||
244 | unsigned long val_write = 0; | ||
245 | |||
246 | val = tegra_slink_readl(tspi, SLINK_STATUS); | ||
247 | |||
248 | /* Write 1 to clear status register */ | ||
249 | val_write = SLINK_RDY | SLINK_FIFO_ERROR; | ||
250 | tegra_slink_writel(tspi, val_write, SLINK_STATUS); | ||
251 | } | ||
252 | |||
253 | static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi, | ||
254 | struct spi_transfer *t) | ||
255 | { | ||
256 | unsigned long val; | ||
257 | |||
258 | switch (tspi->bytes_per_word) { | ||
259 | case 0: | ||
260 | val = SLINK_PACK_SIZE_4; | ||
261 | break; | ||
262 | case 1: | ||
263 | val = SLINK_PACK_SIZE_8; | ||
264 | break; | ||
265 | case 2: | ||
266 | val = SLINK_PACK_SIZE_16; | ||
267 | break; | ||
268 | case 4: | ||
269 | val = SLINK_PACK_SIZE_32; | ||
270 | break; | ||
271 | default: | ||
272 | val = 0; | ||
273 | } | ||
274 | return val; | ||
275 | } | ||
276 | |||
277 | static unsigned tegra_slink_calculate_curr_xfer_param( | ||
278 | struct spi_device *spi, struct tegra_slink_data *tspi, | ||
279 | struct spi_transfer *t) | ||
280 | { | ||
281 | unsigned remain_len = t->len - tspi->cur_pos; | ||
282 | unsigned max_word; | ||
283 | unsigned bits_per_word ; | ||
284 | unsigned max_len; | ||
285 | unsigned total_fifo_words; | ||
286 | |||
287 | bits_per_word = t->bits_per_word ? t->bits_per_word : | ||
288 | spi->bits_per_word; | ||
289 | tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1; | ||
290 | |||
291 | if (bits_per_word == 8 || bits_per_word == 16) { | ||
292 | tspi->is_packed = 1; | ||
293 | tspi->words_per_32bit = 32/bits_per_word; | ||
294 | } else { | ||
295 | tspi->is_packed = 0; | ||
296 | tspi->words_per_32bit = 1; | ||
297 | } | ||
298 | tspi->packed_size = tegra_slink_get_packed_size(tspi, t); | ||
299 | |||
300 | if (tspi->is_packed) { | ||
301 | max_len = min(remain_len, tspi->max_buf_size); | ||
302 | tspi->curr_dma_words = max_len/tspi->bytes_per_word; | ||
303 | total_fifo_words = max_len/4; | ||
304 | } else { | ||
305 | max_word = (remain_len - 1) / tspi->bytes_per_word + 1; | ||
306 | max_word = min(max_word, tspi->max_buf_size/4); | ||
307 | tspi->curr_dma_words = max_word; | ||
308 | total_fifo_words = max_word; | ||
309 | } | ||
310 | return total_fifo_words; | ||
311 | } | ||
312 | |||
313 | static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( | ||
314 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
315 | { | ||
316 | unsigned nbytes; | ||
317 | unsigned tx_empty_count; | ||
318 | unsigned long fifo_status; | ||
319 | unsigned max_n_32bit; | ||
320 | unsigned i, count; | ||
321 | unsigned long x; | ||
322 | unsigned int written_words; | ||
323 | unsigned fifo_words_left; | ||
324 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | ||
325 | |||
326 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | ||
327 | tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); | ||
328 | |||
329 | if (tspi->is_packed) { | ||
330 | fifo_words_left = tx_empty_count * tspi->words_per_32bit; | ||
331 | written_words = min(fifo_words_left, tspi->curr_dma_words); | ||
332 | nbytes = written_words * tspi->bytes_per_word; | ||
333 | max_n_32bit = DIV_ROUND_UP(nbytes, 4); | ||
334 | for (count = 0; count < max_n_32bit; count++) { | ||
335 | x = 0; | ||
336 | for (i = 0; (i < 4) && nbytes; i++, nbytes--) | ||
337 | x |= (*tx_buf++) << (i*8); | ||
338 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); | ||
339 | } | ||
340 | } else { | ||
341 | max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); | ||
342 | written_words = max_n_32bit; | ||
343 | nbytes = written_words * tspi->bytes_per_word; | ||
344 | for (count = 0; count < max_n_32bit; count++) { | ||
345 | x = 0; | ||
346 | for (i = 0; nbytes && (i < tspi->bytes_per_word); | ||
347 | i++, nbytes--) | ||
348 | x |= ((*tx_buf++) << i*8); | ||
349 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); | ||
350 | } | ||
351 | } | ||
352 | tspi->cur_tx_pos += written_words * tspi->bytes_per_word; | ||
353 | return written_words; | ||
354 | } | ||
355 | |||
356 | static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( | ||
357 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
358 | { | ||
359 | unsigned rx_full_count; | ||
360 | unsigned long fifo_status; | ||
361 | unsigned i, count; | ||
362 | unsigned long x; | ||
363 | unsigned int read_words = 0; | ||
364 | unsigned len; | ||
365 | u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; | ||
366 | |||
367 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | ||
368 | rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); | ||
369 | if (tspi->is_packed) { | ||
370 | len = tspi->curr_dma_words * tspi->bytes_per_word; | ||
371 | for (count = 0; count < rx_full_count; count++) { | ||
372 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); | ||
373 | for (i = 0; len && (i < 4); i++, len--) | ||
374 | *rx_buf++ = (x >> i*8) & 0xFF; | ||
375 | } | ||
376 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | ||
377 | read_words += tspi->curr_dma_words; | ||
378 | } else { | ||
379 | unsigned int bits_per_word; | ||
380 | |||
381 | bits_per_word = t->bits_per_word ? t->bits_per_word : | ||
382 | tspi->cur_spi->bits_per_word; | ||
383 | for (count = 0; count < rx_full_count; count++) { | ||
384 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); | ||
385 | for (i = 0; (i < tspi->bytes_per_word); i++) | ||
386 | *rx_buf++ = (x >> (i*8)) & 0xFF; | ||
387 | } | ||
388 | tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; | ||
389 | read_words += rx_full_count; | ||
390 | } | ||
391 | return read_words; | ||
392 | } | ||
393 | |||
394 | static void tegra_slink_copy_client_txbuf_to_spi_txbuf( | ||
395 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
396 | { | ||
397 | unsigned len; | ||
398 | |||
399 | /* Make the dma buffer to read by cpu */ | ||
400 | dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, | ||
401 | tspi->dma_buf_size, DMA_TO_DEVICE); | ||
402 | |||
403 | if (tspi->is_packed) { | ||
404 | len = tspi->curr_dma_words * tspi->bytes_per_word; | ||
405 | memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); | ||
406 | } else { | ||
407 | unsigned int i; | ||
408 | unsigned int count; | ||
409 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | ||
410 | unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; | ||
411 | unsigned int x; | ||
412 | |||
413 | for (count = 0; count < tspi->curr_dma_words; count++) { | ||
414 | x = 0; | ||
415 | for (i = 0; consume && (i < tspi->bytes_per_word); | ||
416 | i++, consume--) | ||
417 | x |= ((*tx_buf++) << i * 8); | ||
418 | tspi->tx_dma_buf[count] = x; | ||
419 | } | ||
420 | } | ||
421 | tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | ||
422 | |||
423 | /* Make the dma buffer to read by dma */ | ||
424 | dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, | ||
425 | tspi->dma_buf_size, DMA_TO_DEVICE); | ||
426 | } | ||
427 | |||
428 | static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( | ||
429 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
430 | { | ||
431 | unsigned len; | ||
432 | |||
433 | /* Make the dma buffer to read by cpu */ | ||
434 | dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, | ||
435 | tspi->dma_buf_size, DMA_FROM_DEVICE); | ||
436 | |||
437 | if (tspi->is_packed) { | ||
438 | len = tspi->curr_dma_words * tspi->bytes_per_word; | ||
439 | memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); | ||
440 | } else { | ||
441 | unsigned int i; | ||
442 | unsigned int count; | ||
443 | unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; | ||
444 | unsigned int x; | ||
445 | unsigned int rx_mask, bits_per_word; | ||
446 | |||
447 | bits_per_word = t->bits_per_word ? t->bits_per_word : | ||
448 | tspi->cur_spi->bits_per_word; | ||
449 | rx_mask = (1 << bits_per_word) - 1; | ||
450 | for (count = 0; count < tspi->curr_dma_words; count++) { | ||
451 | x = tspi->rx_dma_buf[count]; | ||
452 | x &= rx_mask; | ||
453 | for (i = 0; (i < tspi->bytes_per_word); i++) | ||
454 | *rx_buf++ = (x >> (i*8)) & 0xFF; | ||
455 | } | ||
456 | } | ||
457 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | ||
458 | |||
459 | /* Make the dma buffer to read by dma */ | ||
460 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | ||
461 | tspi->dma_buf_size, DMA_FROM_DEVICE); | ||
462 | } | ||
463 | |||
464 | static void tegra_slink_dma_complete(void *args) | ||
465 | { | ||
466 | struct completion *dma_complete = args; | ||
467 | |||
468 | complete(dma_complete); | ||
469 | } | ||
470 | |||
471 | static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) | ||
472 | { | ||
473 | INIT_COMPLETION(tspi->tx_dma_complete); | ||
474 | tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, | ||
475 | tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, | ||
476 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
477 | if (!tspi->tx_dma_desc) { | ||
478 | dev_err(tspi->dev, "Not able to get desc for Tx\n"); | ||
479 | return -EIO; | ||
480 | } | ||
481 | |||
482 | tspi->tx_dma_desc->callback = tegra_slink_dma_complete; | ||
483 | tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; | ||
484 | |||
485 | dmaengine_submit(tspi->tx_dma_desc); | ||
486 | dma_async_issue_pending(tspi->tx_dma_chan); | ||
487 | return 0; | ||
488 | } | ||
489 | |||
490 | static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) | ||
491 | { | ||
492 | INIT_COMPLETION(tspi->rx_dma_complete); | ||
493 | tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, | ||
494 | tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, | ||
495 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
496 | if (!tspi->rx_dma_desc) { | ||
497 | dev_err(tspi->dev, "Not able to get desc for Rx\n"); | ||
498 | return -EIO; | ||
499 | } | ||
500 | |||
501 | tspi->rx_dma_desc->callback = tegra_slink_dma_complete; | ||
502 | tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; | ||
503 | |||
504 | dmaengine_submit(tspi->rx_dma_desc); | ||
505 | dma_async_issue_pending(tspi->rx_dma_chan); | ||
506 | return 0; | ||
507 | } | ||
508 | |||
509 | static int tegra_slink_start_dma_based_transfer( | ||
510 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
511 | { | ||
512 | unsigned long val; | ||
513 | unsigned long test_val; | ||
514 | unsigned int len; | ||
515 | int ret = 0; | ||
516 | unsigned long status; | ||
517 | |||
518 | /* Make sure that Rx and Tx fifo are empty */ | ||
519 | status = tegra_slink_readl(tspi, SLINK_STATUS); | ||
520 | if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { | ||
521 | dev_err(tspi->dev, | ||
522 | "Rx/Tx fifo are not empty status 0x%08lx\n", status); | ||
523 | return -EIO; | ||
524 | } | ||
525 | |||
526 | val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); | ||
527 | val |= tspi->packed_size; | ||
528 | if (tspi->is_packed) | ||
529 | len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, | ||
530 | 4) * 4; | ||
531 | else | ||
532 | len = tspi->curr_dma_words * 4; | ||
533 | |||
534 | /* Set attention level based on length of transfer */ | ||
535 | if (len & 0xF) | ||
536 | val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; | ||
537 | else if (((len) >> 4) & 0x1) | ||
538 | val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; | ||
539 | else | ||
540 | val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; | ||
541 | |||
542 | if (tspi->cur_direction & DATA_DIR_TX) | ||
543 | val |= SLINK_IE_TXC; | ||
544 | |||
545 | if (tspi->cur_direction & DATA_DIR_RX) | ||
546 | val |= SLINK_IE_RXC; | ||
547 | |||
548 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
549 | tspi->dma_control_reg = val; | ||
550 | |||
551 | if (tspi->cur_direction & DATA_DIR_TX) { | ||
552 | tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); | ||
553 | wmb(); | ||
554 | ret = tegra_slink_start_tx_dma(tspi, len); | ||
555 | if (ret < 0) { | ||
556 | dev_err(tspi->dev, | ||
557 | "Starting tx dma failed, err %d\n", ret); | ||
558 | return ret; | ||
559 | } | ||
560 | |||
561 | /* Wait for tx fifo to be fill before starting slink */ | ||
562 | test_val = tegra_slink_readl(tspi, SLINK_STATUS); | ||
563 | while (!(test_val & SLINK_TX_FULL)) | ||
564 | test_val = tegra_slink_readl(tspi, SLINK_STATUS); | ||
565 | } | ||
566 | |||
567 | if (tspi->cur_direction & DATA_DIR_RX) { | ||
568 | /* Make the dma buffer to read by dma */ | ||
569 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | ||
570 | tspi->dma_buf_size, DMA_FROM_DEVICE); | ||
571 | |||
572 | ret = tegra_slink_start_rx_dma(tspi, len); | ||
573 | if (ret < 0) { | ||
574 | dev_err(tspi->dev, | ||
575 | "Starting rx dma failed, err %d\n", ret); | ||
576 | if (tspi->cur_direction & DATA_DIR_TX) | ||
577 | dmaengine_terminate_all(tspi->tx_dma_chan); | ||
578 | return ret; | ||
579 | } | ||
580 | } | ||
581 | tspi->is_curr_dma_xfer = true; | ||
582 | if (tspi->is_packed) { | ||
583 | val |= SLINK_PACKED; | ||
584 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
585 | /* HW need small delay after settign Packed mode */ | ||
586 | udelay(1); | ||
587 | } | ||
588 | tspi->dma_control_reg = val; | ||
589 | |||
590 | val |= SLINK_DMA_EN; | ||
591 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
592 | return ret; | ||
593 | } | ||
594 | |||
595 | static int tegra_slink_start_cpu_based_transfer( | ||
596 | struct tegra_slink_data *tspi, struct spi_transfer *t) | ||
597 | { | ||
598 | unsigned long val; | ||
599 | unsigned cur_words; | ||
600 | |||
601 | val = tspi->packed_size; | ||
602 | if (tspi->cur_direction & DATA_DIR_TX) | ||
603 | val |= SLINK_IE_TXC; | ||
604 | |||
605 | if (tspi->cur_direction & DATA_DIR_RX) | ||
606 | val |= SLINK_IE_RXC; | ||
607 | |||
608 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
609 | tspi->dma_control_reg = val; | ||
610 | |||
611 | if (tspi->cur_direction & DATA_DIR_TX) | ||
612 | cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); | ||
613 | else | ||
614 | cur_words = tspi->curr_dma_words; | ||
615 | val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); | ||
616 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
617 | tspi->dma_control_reg = val; | ||
618 | |||
619 | tspi->is_curr_dma_xfer = false; | ||
620 | if (tspi->is_packed) { | ||
621 | val |= SLINK_PACKED; | ||
622 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
623 | udelay(1); | ||
624 | wmb(); | ||
625 | } | ||
626 | tspi->dma_control_reg = val; | ||
627 | val |= SLINK_DMA_EN; | ||
628 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | ||
629 | return 0; | ||
630 | } | ||
631 | |||
632 | static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, | ||
633 | bool dma_to_memory) | ||
634 | { | ||
635 | struct dma_chan *dma_chan; | ||
636 | u32 *dma_buf; | ||
637 | dma_addr_t dma_phys; | ||
638 | int ret; | ||
639 | struct dma_slave_config dma_sconfig; | ||
640 | dma_cap_mask_t mask; | ||
641 | |||
642 | dma_cap_zero(mask); | ||
643 | dma_cap_set(DMA_SLAVE, mask); | ||
644 | dma_chan = dma_request_channel(mask, NULL, NULL); | ||
645 | if (!dma_chan) { | ||
646 | dev_err(tspi->dev, | ||
647 | "Dma channel is not available, will try later\n"); | ||
648 | return -EPROBE_DEFER; | ||
649 | } | ||
650 | |||
651 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, | ||
652 | &dma_phys, GFP_KERNEL); | ||
653 | if (!dma_buf) { | ||
654 | dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); | ||
655 | dma_release_channel(dma_chan); | ||
656 | return -ENOMEM; | ||
657 | } | ||
658 | |||
659 | dma_sconfig.slave_id = tspi->dma_req_sel; | ||
660 | if (dma_to_memory) { | ||
661 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; | ||
662 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
663 | dma_sconfig.src_maxburst = 0; | ||
664 | } else { | ||
665 | dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; | ||
666 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
667 | dma_sconfig.dst_maxburst = 0; | ||
668 | } | ||
669 | |||
670 | ret = dmaengine_slave_config(dma_chan, &dma_sconfig); | ||
671 | if (ret) | ||
672 | goto scrub; | ||
673 | if (dma_to_memory) { | ||
674 | tspi->rx_dma_chan = dma_chan; | ||
675 | tspi->rx_dma_buf = dma_buf; | ||
676 | tspi->rx_dma_phys = dma_phys; | ||
677 | } else { | ||
678 | tspi->tx_dma_chan = dma_chan; | ||
679 | tspi->tx_dma_buf = dma_buf; | ||
680 | tspi->tx_dma_phys = dma_phys; | ||
681 | } | ||
682 | return 0; | ||
683 | |||
684 | scrub: | ||
685 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | ||
686 | dma_release_channel(dma_chan); | ||
687 | return ret; | ||
688 | } | ||
689 | |||
690 | static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, | ||
691 | bool dma_to_memory) | ||
692 | { | ||
693 | u32 *dma_buf; | ||
694 | dma_addr_t dma_phys; | ||
695 | struct dma_chan *dma_chan; | ||
696 | |||
697 | if (dma_to_memory) { | ||
698 | dma_buf = tspi->rx_dma_buf; | ||
699 | dma_chan = tspi->rx_dma_chan; | ||
700 | dma_phys = tspi->rx_dma_phys; | ||
701 | tspi->rx_dma_chan = NULL; | ||
702 | tspi->rx_dma_buf = NULL; | ||
703 | } else { | ||
704 | dma_buf = tspi->tx_dma_buf; | ||
705 | dma_chan = tspi->tx_dma_chan; | ||
706 | dma_phys = tspi->tx_dma_phys; | ||
707 | tspi->tx_dma_buf = NULL; | ||
708 | tspi->tx_dma_chan = NULL; | ||
709 | } | ||
710 | if (!dma_chan) | ||
711 | return; | ||
712 | |||
713 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | ||
714 | dma_release_channel(dma_chan); | ||
715 | } | ||
716 | |||
717 | static int tegra_slink_start_transfer_one(struct spi_device *spi, | ||
718 | struct spi_transfer *t, bool is_first_of_msg, | ||
719 | bool is_single_xfer) | ||
720 | { | ||
721 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); | ||
722 | u32 speed; | ||
723 | u8 bits_per_word; | ||
724 | unsigned total_fifo_words; | ||
725 | int ret; | ||
726 | struct tegra_spi_device_controller_data *cdata = spi->controller_data; | ||
727 | unsigned long command; | ||
728 | unsigned long command2; | ||
729 | |||
730 | bits_per_word = t->bits_per_word; | ||
731 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | ||
732 | if (!speed) | ||
733 | speed = tspi->spi_max_frequency; | ||
734 | if (speed != tspi->cur_speed) { | ||
735 | clk_set_rate(tspi->clk, speed * 4); | ||
736 | tspi->cur_speed = speed; | ||
737 | } | ||
738 | |||
739 | tspi->cur_spi = spi; | ||
740 | tspi->cur_pos = 0; | ||
741 | tspi->cur_rx_pos = 0; | ||
742 | tspi->cur_tx_pos = 0; | ||
743 | tspi->curr_xfer = t; | ||
744 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); | ||
745 | |||
746 | if (is_first_of_msg) { | ||
747 | tegra_slink_clear_status(tspi); | ||
748 | |||
749 | command = tspi->def_command_reg; | ||
750 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); | ||
751 | |||
752 | command2 = tspi->def_command2_reg; | ||
753 | command2 |= SLINK_SS_EN_CS(spi->chip_select); | ||
754 | |||
755 | /* possibly use the hw based chip select */ | ||
756 | tspi->is_hw_based_cs = false; | ||
757 | if (cdata && cdata->is_hw_based_cs && is_single_xfer && | ||
758 | ((tspi->curr_dma_words * tspi->bytes_per_word) == | ||
759 | (t->len - tspi->cur_pos))) { | ||
760 | int setup_count; | ||
761 | int sts2; | ||
762 | |||
763 | setup_count = cdata->cs_setup_clk_count >> 1; | ||
764 | setup_count = max(setup_count, 3); | ||
765 | command2 |= SLINK_SS_SETUP(setup_count); | ||
766 | if (tspi->chip_data->cs_hold_time) { | ||
767 | int hold_count; | ||
768 | |||
769 | hold_count = cdata->cs_hold_clk_count; | ||
770 | hold_count = max(hold_count, 0xF); | ||
771 | sts2 = tegra_slink_readl(tspi, SLINK_STATUS2); | ||
772 | sts2 &= ~SLINK_SS_HOLD_TIME(0xF); | ||
773 | sts2 |= SLINK_SS_HOLD_TIME(hold_count); | ||
774 | tegra_slink_writel(tspi, sts2, SLINK_STATUS2); | ||
775 | } | ||
776 | tspi->is_hw_based_cs = true; | ||
777 | } | ||
778 | |||
779 | if (tspi->is_hw_based_cs) | ||
780 | command &= ~SLINK_CS_SW; | ||
781 | else | ||
782 | command |= SLINK_CS_SW | SLINK_CS_VALUE; | ||
783 | |||
784 | command &= ~SLINK_MODES; | ||
785 | if (spi->mode & SPI_CPHA) | ||
786 | command |= SLINK_CK_SDA; | ||
787 | |||
788 | if (spi->mode & SPI_CPOL) | ||
789 | command |= SLINK_IDLE_SCLK_DRIVE_HIGH; | ||
790 | else | ||
791 | command |= SLINK_IDLE_SCLK_DRIVE_LOW; | ||
792 | } else { | ||
793 | command = tspi->command_reg; | ||
794 | command &= ~SLINK_BIT_LENGTH(~0); | ||
795 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); | ||
796 | |||
797 | command2 = tspi->command2_reg; | ||
798 | command2 &= ~(SLINK_RXEN | SLINK_TXEN); | ||
799 | } | ||
800 | |||
801 | tegra_slink_writel(tspi, command, SLINK_COMMAND); | ||
802 | tspi->command_reg = command; | ||
803 | |||
804 | tspi->cur_direction = 0; | ||
805 | if (t->rx_buf) { | ||
806 | command2 |= SLINK_RXEN; | ||
807 | tspi->cur_direction |= DATA_DIR_RX; | ||
808 | } | ||
809 | if (t->tx_buf) { | ||
810 | command2 |= SLINK_TXEN; | ||
811 | tspi->cur_direction |= DATA_DIR_TX; | ||
812 | } | ||
813 | tegra_slink_writel(tspi, command2, SLINK_COMMAND2); | ||
814 | tspi->command2_reg = command2; | ||
815 | |||
816 | if (total_fifo_words > SLINK_FIFO_DEPTH) | ||
817 | ret = tegra_slink_start_dma_based_transfer(tspi, t); | ||
818 | else | ||
819 | ret = tegra_slink_start_cpu_based_transfer(tspi, t); | ||
820 | return ret; | ||
821 | } | ||
822 | |||
823 | static int tegra_slink_setup(struct spi_device *spi) | ||
824 | { | ||
825 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); | ||
826 | unsigned long val; | ||
827 | unsigned long flags; | ||
828 | int ret; | ||
829 | unsigned int cs_pol_bit[MAX_CHIP_SELECT] = { | ||
830 | SLINK_CS_POLARITY, | ||
831 | SLINK_CS_POLARITY1, | ||
832 | SLINK_CS_POLARITY2, | ||
833 | SLINK_CS_POLARITY3, | ||
834 | }; | ||
835 | |||
836 | dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", | ||
837 | spi->bits_per_word, | ||
838 | spi->mode & SPI_CPOL ? "" : "~", | ||
839 | spi->mode & SPI_CPHA ? "" : "~", | ||
840 | spi->max_speed_hz); | ||
841 | |||
842 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); | ||
843 | |||
844 | ret = pm_runtime_get_sync(tspi->dev); | ||
845 | if (ret < 0) { | ||
846 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); | ||
847 | return ret; | ||
848 | } | ||
849 | |||
850 | spin_lock_irqsave(&tspi->lock, flags); | ||
851 | val = tspi->def_command_reg; | ||
852 | if (spi->mode & SPI_CS_HIGH) | ||
853 | val |= cs_pol_bit[spi->chip_select]; | ||
854 | else | ||
855 | val &= ~cs_pol_bit[spi->chip_select]; | ||
856 | tspi->def_command_reg = val; | ||
857 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | ||
858 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
859 | |||
860 | pm_runtime_put(tspi->dev); | ||
861 | return 0; | ||
862 | } | ||
863 | |||
864 | static int tegra_slink_prepare_transfer(struct spi_master *master) | ||
865 | { | ||
866 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
867 | |||
868 | return pm_runtime_get_sync(tspi->dev); | ||
869 | } | ||
870 | |||
871 | static int tegra_slink_unprepare_transfer(struct spi_master *master) | ||
872 | { | ||
873 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
874 | |||
875 | pm_runtime_put(tspi->dev); | ||
876 | return 0; | ||
877 | } | ||
878 | |||
879 | static int tegra_slink_transfer_one_message(struct spi_master *master, | ||
880 | struct spi_message *msg) | ||
881 | { | ||
882 | bool is_first_msg = true; | ||
883 | int single_xfer; | ||
884 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
885 | struct spi_transfer *xfer; | ||
886 | struct spi_device *spi = msg->spi; | ||
887 | int ret; | ||
888 | |||
889 | msg->status = 0; | ||
890 | msg->actual_length = 0; | ||
891 | single_xfer = list_is_singular(&msg->transfers); | ||
892 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | ||
893 | INIT_COMPLETION(tspi->xfer_completion); | ||
894 | ret = tegra_slink_start_transfer_one(spi, xfer, | ||
895 | is_first_msg, single_xfer); | ||
896 | if (ret < 0) { | ||
897 | dev_err(tspi->dev, | ||
898 | "spi can not start transfer, err %d\n", ret); | ||
899 | goto exit; | ||
900 | } | ||
901 | is_first_msg = false; | ||
902 | ret = wait_for_completion_timeout(&tspi->xfer_completion, | ||
903 | SLINK_DMA_TIMEOUT); | ||
904 | if (WARN_ON(ret == 0)) { | ||
905 | dev_err(tspi->dev, | ||
906 | "spi trasfer timeout, err %d\n", ret); | ||
907 | ret = -EIO; | ||
908 | goto exit; | ||
909 | } | ||
910 | |||
911 | if (tspi->tx_status || tspi->rx_status) { | ||
912 | dev_err(tspi->dev, "Error in Transfer\n"); | ||
913 | ret = -EIO; | ||
914 | goto exit; | ||
915 | } | ||
916 | msg->actual_length += xfer->len; | ||
917 | if (xfer->cs_change && xfer->delay_usecs) { | ||
918 | tegra_slink_writel(tspi, tspi->def_command_reg, | ||
919 | SLINK_COMMAND); | ||
920 | udelay(xfer->delay_usecs); | ||
921 | } | ||
922 | } | ||
923 | ret = 0; | ||
924 | exit: | ||
925 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | ||
926 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | ||
927 | msg->status = ret; | ||
928 | spi_finalize_current_message(master); | ||
929 | return ret; | ||
930 | } | ||
931 | |||
932 | static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) | ||
933 | { | ||
934 | struct spi_transfer *t = tspi->curr_xfer; | ||
935 | unsigned long flags; | ||
936 | |||
937 | spin_lock_irqsave(&tspi->lock, flags); | ||
938 | if (tspi->tx_status || tspi->rx_status || | ||
939 | (tspi->status_reg & SLINK_BSY)) { | ||
940 | dev_err(tspi->dev, | ||
941 | "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); | ||
942 | dev_err(tspi->dev, | ||
943 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | ||
944 | tspi->command2_reg, tspi->dma_control_reg); | ||
945 | tegra_periph_reset_assert(tspi->clk); | ||
946 | udelay(2); | ||
947 | tegra_periph_reset_deassert(tspi->clk); | ||
948 | complete(&tspi->xfer_completion); | ||
949 | goto exit; | ||
950 | } | ||
951 | |||
952 | if (tspi->cur_direction & DATA_DIR_RX) | ||
953 | tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); | ||
954 | |||
955 | if (tspi->cur_direction & DATA_DIR_TX) | ||
956 | tspi->cur_pos = tspi->cur_tx_pos; | ||
957 | else | ||
958 | tspi->cur_pos = tspi->cur_rx_pos; | ||
959 | |||
960 | if (tspi->cur_pos == t->len) { | ||
961 | complete(&tspi->xfer_completion); | ||
962 | goto exit; | ||
963 | } | ||
964 | |||
965 | tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); | ||
966 | tegra_slink_start_cpu_based_transfer(tspi, t); | ||
967 | exit: | ||
968 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
969 | return IRQ_HANDLED; | ||
970 | } | ||
971 | |||
972 | static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) | ||
973 | { | ||
974 | struct spi_transfer *t = tspi->curr_xfer; | ||
975 | long wait_status; | ||
976 | int err = 0; | ||
977 | unsigned total_fifo_words; | ||
978 | unsigned long flags; | ||
979 | |||
980 | /* Abort dmas if any error */ | ||
981 | if (tspi->cur_direction & DATA_DIR_TX) { | ||
982 | if (tspi->tx_status) { | ||
983 | dmaengine_terminate_all(tspi->tx_dma_chan); | ||
984 | err += 1; | ||
985 | } else { | ||
986 | wait_status = wait_for_completion_interruptible_timeout( | ||
987 | &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); | ||
988 | if (wait_status <= 0) { | ||
989 | dmaengine_terminate_all(tspi->tx_dma_chan); | ||
990 | dev_err(tspi->dev, "TxDma Xfer failed\n"); | ||
991 | err += 1; | ||
992 | } | ||
993 | } | ||
994 | } | ||
995 | |||
996 | if (tspi->cur_direction & DATA_DIR_RX) { | ||
997 | if (tspi->rx_status) { | ||
998 | dmaengine_terminate_all(tspi->rx_dma_chan); | ||
999 | err += 2; | ||
1000 | } else { | ||
1001 | wait_status = wait_for_completion_interruptible_timeout( | ||
1002 | &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); | ||
1003 | if (wait_status <= 0) { | ||
1004 | dmaengine_terminate_all(tspi->rx_dma_chan); | ||
1005 | dev_err(tspi->dev, "RxDma Xfer failed\n"); | ||
1006 | err += 2; | ||
1007 | } | ||
1008 | } | ||
1009 | } | ||
1010 | |||
1011 | spin_lock_irqsave(&tspi->lock, flags); | ||
1012 | if (err) { | ||
1013 | dev_err(tspi->dev, | ||
1014 | "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); | ||
1015 | dev_err(tspi->dev, | ||
1016 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | ||
1017 | tspi->command2_reg, tspi->dma_control_reg); | ||
1018 | tegra_periph_reset_assert(tspi->clk); | ||
1019 | udelay(2); | ||
1020 | tegra_periph_reset_deassert(tspi->clk); | ||
1021 | complete(&tspi->xfer_completion); | ||
1022 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
1023 | return IRQ_HANDLED; | ||
1024 | } | ||
1025 | |||
1026 | if (tspi->cur_direction & DATA_DIR_RX) | ||
1027 | tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); | ||
1028 | |||
1029 | if (tspi->cur_direction & DATA_DIR_TX) | ||
1030 | tspi->cur_pos = tspi->cur_tx_pos; | ||
1031 | else | ||
1032 | tspi->cur_pos = tspi->cur_rx_pos; | ||
1033 | |||
1034 | if (tspi->cur_pos == t->len) { | ||
1035 | complete(&tspi->xfer_completion); | ||
1036 | goto exit; | ||
1037 | } | ||
1038 | |||
1039 | /* Continue transfer in current message */ | ||
1040 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, | ||
1041 | tspi, t); | ||
1042 | if (total_fifo_words > SLINK_FIFO_DEPTH) | ||
1043 | err = tegra_slink_start_dma_based_transfer(tspi, t); | ||
1044 | else | ||
1045 | err = tegra_slink_start_cpu_based_transfer(tspi, t); | ||
1046 | |||
1047 | exit: | ||
1048 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
1049 | return IRQ_HANDLED; | ||
1050 | } | ||
1051 | |||
1052 | static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) | ||
1053 | { | ||
1054 | struct tegra_slink_data *tspi = context_data; | ||
1055 | |||
1056 | if (!tspi->is_curr_dma_xfer) | ||
1057 | return handle_cpu_based_xfer(tspi); | ||
1058 | return handle_dma_based_xfer(tspi); | ||
1059 | } | ||
1060 | |||
1061 | static irqreturn_t tegra_slink_isr(int irq, void *context_data) | ||
1062 | { | ||
1063 | struct tegra_slink_data *tspi = context_data; | ||
1064 | |||
1065 | tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); | ||
1066 | if (tspi->cur_direction & DATA_DIR_TX) | ||
1067 | tspi->tx_status = tspi->status_reg & | ||
1068 | (SLINK_TX_OVF | SLINK_TX_UNF); | ||
1069 | |||
1070 | if (tspi->cur_direction & DATA_DIR_RX) | ||
1071 | tspi->rx_status = tspi->status_reg & | ||
1072 | (SLINK_RX_OVF | SLINK_RX_UNF); | ||
1073 | tegra_slink_clear_status(tspi); | ||
1074 | |||
1075 | return IRQ_WAKE_THREAD; | ||
1076 | } | ||
1077 | |||
1078 | static struct tegra_spi_platform_data *tegra_slink_parse_dt( | ||
1079 | struct platform_device *pdev) | ||
1080 | { | ||
1081 | struct tegra_spi_platform_data *pdata; | ||
1082 | const unsigned int *prop; | ||
1083 | struct device_node *np = pdev->dev.of_node; | ||
1084 | u32 of_dma[2]; | ||
1085 | |||
1086 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
1087 | if (!pdata) { | ||
1088 | dev_err(&pdev->dev, "Memory alloc for pdata failed\n"); | ||
1089 | return NULL; | ||
1090 | } | ||
1091 | |||
1092 | if (of_property_read_u32_array(np, "nvidia,dma-request-selector", | ||
1093 | of_dma, 2) >= 0) | ||
1094 | pdata->dma_req_sel = of_dma[1]; | ||
1095 | |||
1096 | prop = of_get_property(np, "spi-max-frequency", NULL); | ||
1097 | if (prop) | ||
1098 | pdata->spi_max_frequency = be32_to_cpup(prop); | ||
1099 | |||
1100 | return pdata; | ||
1101 | } | ||
1102 | |||
1103 | const struct tegra_slink_chip_data tegra30_spi_cdata = { | ||
1104 | .cs_hold_time = true, | ||
1105 | }; | ||
1106 | |||
1107 | const struct tegra_slink_chip_data tegra20_spi_cdata = { | ||
1108 | .cs_hold_time = false, | ||
1109 | }; | ||
1110 | |||
1111 | static struct of_device_id tegra_slink_of_match[] = { | ||
1112 | { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, | ||
1113 | { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, | ||
1114 | {} | ||
1115 | }; | ||
1116 | MODULE_DEVICE_TABLE(of, tegra_slink_of_match); | ||
1117 | |||
1118 | static int tegra_slink_probe(struct platform_device *pdev) | ||
1119 | { | ||
1120 | struct spi_master *master; | ||
1121 | struct tegra_slink_data *tspi; | ||
1122 | struct resource *r; | ||
1123 | struct tegra_spi_platform_data *pdata = pdev->dev.platform_data; | ||
1124 | int ret, spi_irq; | ||
1125 | const struct tegra_slink_chip_data *cdata = NULL; | ||
1126 | const struct of_device_id *match; | ||
1127 | |||
1128 | match = of_match_device(of_match_ptr(tegra_slink_of_match), &pdev->dev); | ||
1129 | if (!match) { | ||
1130 | dev_err(&pdev->dev, "Error: No device match found\n"); | ||
1131 | return -ENODEV; | ||
1132 | } | ||
1133 | cdata = match->data; | ||
1134 | if (!pdata && pdev->dev.of_node) | ||
1135 | pdata = tegra_slink_parse_dt(pdev); | ||
1136 | |||
1137 | if (!pdata) { | ||
1138 | dev_err(&pdev->dev, "No platform data, exiting\n"); | ||
1139 | return -ENODEV; | ||
1140 | } | ||
1141 | |||
1142 | if (!pdata->spi_max_frequency) | ||
1143 | pdata->spi_max_frequency = 25000000; /* 25MHz */ | ||
1144 | |||
1145 | master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); | ||
1146 | if (!master) { | ||
1147 | dev_err(&pdev->dev, "master allocation failed\n"); | ||
1148 | return -ENOMEM; | ||
1149 | } | ||
1150 | |||
1151 | /* the spi->mode bits understood by this driver: */ | ||
1152 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | ||
1153 | master->setup = tegra_slink_setup; | ||
1154 | master->prepare_transfer_hardware = tegra_slink_prepare_transfer; | ||
1155 | master->transfer_one_message = tegra_slink_transfer_one_message; | ||
1156 | master->unprepare_transfer_hardware = tegra_slink_unprepare_transfer; | ||
1157 | master->num_chipselect = MAX_CHIP_SELECT; | ||
1158 | master->bus_num = -1; | ||
1159 | |||
1160 | dev_set_drvdata(&pdev->dev, master); | ||
1161 | tspi = spi_master_get_devdata(master); | ||
1162 | tspi->master = master; | ||
1163 | tspi->dma_req_sel = pdata->dma_req_sel; | ||
1164 | tspi->dev = &pdev->dev; | ||
1165 | tspi->chip_data = cdata; | ||
1166 | spin_lock_init(&tspi->lock); | ||
1167 | |||
1168 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1169 | if (!r) { | ||
1170 | dev_err(&pdev->dev, "No IO memory resource\n"); | ||
1171 | ret = -ENODEV; | ||
1172 | goto exit_free_master; | ||
1173 | } | ||
1174 | tspi->phys = r->start; | ||
1175 | tspi->base = devm_request_and_ioremap(&pdev->dev, r); | ||
1176 | if (!tspi->base) { | ||
1177 | dev_err(&pdev->dev, | ||
1178 | "Cannot request memregion/iomap dma address\n"); | ||
1179 | ret = -EADDRNOTAVAIL; | ||
1180 | goto exit_free_master; | ||
1181 | } | ||
1182 | |||
1183 | spi_irq = platform_get_irq(pdev, 0); | ||
1184 | tspi->irq = spi_irq; | ||
1185 | ret = request_threaded_irq(tspi->irq, tegra_slink_isr, | ||
1186 | tegra_slink_isr_thread, IRQF_ONESHOT, | ||
1187 | dev_name(&pdev->dev), tspi); | ||
1188 | if (ret < 0) { | ||
1189 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", | ||
1190 | tspi->irq); | ||
1191 | goto exit_free_master; | ||
1192 | } | ||
1193 | |||
1194 | tspi->clk = devm_clk_get(&pdev->dev, "slink"); | ||
1195 | if (IS_ERR(tspi->clk)) { | ||
1196 | dev_err(&pdev->dev, "can not get clock\n"); | ||
1197 | ret = PTR_ERR(tspi->clk); | ||
1198 | goto exit_free_irq; | ||
1199 | } | ||
1200 | |||
1201 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; | ||
1202 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | ||
1203 | tspi->spi_max_frequency = pdata->spi_max_frequency; | ||
1204 | |||
1205 | if (pdata->dma_req_sel) { | ||
1206 | ret = tegra_slink_init_dma_param(tspi, true); | ||
1207 | if (ret < 0) { | ||
1208 | dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); | ||
1209 | goto exit_free_irq; | ||
1210 | } | ||
1211 | |||
1212 | ret = tegra_slink_init_dma_param(tspi, false); | ||
1213 | if (ret < 0) { | ||
1214 | dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret); | ||
1215 | goto exit_rx_dma_free; | ||
1216 | } | ||
1217 | tspi->max_buf_size = tspi->dma_buf_size; | ||
1218 | init_completion(&tspi->tx_dma_complete); | ||
1219 | init_completion(&tspi->rx_dma_complete); | ||
1220 | } | ||
1221 | |||
1222 | init_completion(&tspi->xfer_completion); | ||
1223 | |||
1224 | pm_runtime_enable(&pdev->dev); | ||
1225 | if (!pm_runtime_enabled(&pdev->dev)) { | ||
1226 | ret = tegra_slink_runtime_resume(&pdev->dev); | ||
1227 | if (ret) | ||
1228 | goto exit_pm_disable; | ||
1229 | } | ||
1230 | |||
1231 | ret = pm_runtime_get_sync(&pdev->dev); | ||
1232 | if (ret < 0) { | ||
1233 | dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); | ||
1234 | goto exit_pm_disable; | ||
1235 | } | ||
1236 | tspi->def_command_reg = SLINK_M_S; | ||
1237 | tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; | ||
1238 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | ||
1239 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | ||
1240 | pm_runtime_put(&pdev->dev); | ||
1241 | |||
1242 | master->dev.of_node = pdev->dev.of_node; | ||
1243 | ret = spi_register_master(master); | ||
1244 | if (ret < 0) { | ||
1245 | dev_err(&pdev->dev, "can not register to master err %d\n", ret); | ||
1246 | goto exit_pm_disable; | ||
1247 | } | ||
1248 | return ret; | ||
1249 | |||
1250 | exit_pm_disable: | ||
1251 | pm_runtime_disable(&pdev->dev); | ||
1252 | if (!pm_runtime_status_suspended(&pdev->dev)) | ||
1253 | tegra_slink_runtime_suspend(&pdev->dev); | ||
1254 | tegra_slink_deinit_dma_param(tspi, false); | ||
1255 | exit_rx_dma_free: | ||
1256 | tegra_slink_deinit_dma_param(tspi, true); | ||
1257 | exit_free_irq: | ||
1258 | free_irq(spi_irq, tspi); | ||
1259 | exit_free_master: | ||
1260 | spi_master_put(master); | ||
1261 | return ret; | ||
1262 | } | ||
1263 | |||
1264 | static int tegra_slink_remove(struct platform_device *pdev) | ||
1265 | { | ||
1266 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | ||
1267 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
1268 | |||
1269 | free_irq(tspi->irq, tspi); | ||
1270 | spi_unregister_master(master); | ||
1271 | |||
1272 | if (tspi->tx_dma_chan) | ||
1273 | tegra_slink_deinit_dma_param(tspi, false); | ||
1274 | |||
1275 | if (tspi->rx_dma_chan) | ||
1276 | tegra_slink_deinit_dma_param(tspi, true); | ||
1277 | |||
1278 | pm_runtime_disable(&pdev->dev); | ||
1279 | if (!pm_runtime_status_suspended(&pdev->dev)) | ||
1280 | tegra_slink_runtime_suspend(&pdev->dev); | ||
1281 | |||
1282 | return 0; | ||
1283 | } | ||
1284 | |||
1285 | #ifdef CONFIG_PM_SLEEP | ||
1286 | static int tegra_slink_suspend(struct device *dev) | ||
1287 | { | ||
1288 | struct spi_master *master = dev_get_drvdata(dev); | ||
1289 | |||
1290 | return spi_master_suspend(master); | ||
1291 | } | ||
1292 | |||
1293 | static int tegra_slink_resume(struct device *dev) | ||
1294 | { | ||
1295 | struct spi_master *master = dev_get_drvdata(dev); | ||
1296 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
1297 | int ret; | ||
1298 | |||
1299 | ret = pm_runtime_get_sync(dev); | ||
1300 | if (ret < 0) { | ||
1301 | dev_err(dev, "pm runtime failed, e = %d\n", ret); | ||
1302 | return ret; | ||
1303 | } | ||
1304 | tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); | ||
1305 | tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); | ||
1306 | pm_runtime_put(dev); | ||
1307 | |||
1308 | return spi_master_resume(master); | ||
1309 | } | ||
1310 | #endif | ||
1311 | |||
1312 | static int tegra_slink_runtime_suspend(struct device *dev) | ||
1313 | { | ||
1314 | struct spi_master *master = dev_get_drvdata(dev); | ||
1315 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
1316 | |||
1317 | /* Flush all write which are in PPSB queue by reading back */ | ||
1318 | tegra_slink_readl(tspi, SLINK_MAS_DATA); | ||
1319 | |||
1320 | clk_disable_unprepare(tspi->clk); | ||
1321 | return 0; | ||
1322 | } | ||
1323 | |||
1324 | static int tegra_slink_runtime_resume(struct device *dev) | ||
1325 | { | ||
1326 | struct spi_master *master = dev_get_drvdata(dev); | ||
1327 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | ||
1328 | int ret; | ||
1329 | |||
1330 | ret = clk_prepare_enable(tspi->clk); | ||
1331 | if (ret < 0) { | ||
1332 | dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); | ||
1333 | return ret; | ||
1334 | } | ||
1335 | return 0; | ||
1336 | } | ||
1337 | |||
1338 | static const struct dev_pm_ops slink_pm_ops = { | ||
1339 | SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, | ||
1340 | tegra_slink_runtime_resume, NULL) | ||
1341 | SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) | ||
1342 | }; | ||
1343 | static struct platform_driver tegra_slink_driver = { | ||
1344 | .driver = { | ||
1345 | .name = "spi-tegra-slink", | ||
1346 | .owner = THIS_MODULE, | ||
1347 | .pm = &slink_pm_ops, | ||
1348 | .of_match_table = of_match_ptr(tegra_slink_of_match), | ||
1349 | }, | ||
1350 | .probe = tegra_slink_probe, | ||
1351 | .remove = tegra_slink_remove, | ||
1352 | }; | ||
1353 | module_platform_driver(tegra_slink_driver); | ||
1354 | |||
1355 | MODULE_ALIAS("platform:spi-tegra-slink"); | ||
1356 | MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); | ||
1357 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | ||
1358 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/spi/spi-ti-ssp.c b/drivers/spi/spi-ti-ssp.c index 46992cab65f..ee22795c797 100644 --- a/drivers/spi/spi-ti-ssp.c +++ b/drivers/spi/spi-ti-ssp.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/err.h> | 22 | #include <linux/err.h> |
23 | #include <linux/completion.h> | 23 | #include <linux/completion.h> |
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <linux/module.h> | ||
26 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
27 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
28 | #include <linux/mfd/ti_ssp.h> | 27 | #include <linux/mfd/ti_ssp.h> |
@@ -289,7 +288,7 @@ error_unlock: | |||
289 | return error; | 288 | return error; |
290 | } | 289 | } |
291 | 290 | ||
292 | static int ti_ssp_spi_probe(struct platform_device *pdev) | 291 | static int __devinit ti_ssp_spi_probe(struct platform_device *pdev) |
293 | { | 292 | { |
294 | const struct ti_ssp_spi_data *pdata; | 293 | const struct ti_ssp_spi_data *pdata; |
295 | struct ti_ssp_spi *hw; | 294 | struct ti_ssp_spi *hw; |
@@ -357,7 +356,7 @@ error_wq: | |||
357 | return error; | 356 | return error; |
358 | } | 357 | } |
359 | 358 | ||
360 | static int ti_ssp_spi_remove(struct platform_device *pdev) | 359 | static int __devexit ti_ssp_spi_remove(struct platform_device *pdev) |
361 | { | 360 | { |
362 | struct ti_ssp_spi *hw = platform_get_drvdata(pdev); | 361 | struct ti_ssp_spi *hw = platform_get_drvdata(pdev); |
363 | int error; | 362 | int error; |
@@ -378,13 +377,24 @@ static int ti_ssp_spi_remove(struct platform_device *pdev) | |||
378 | 377 | ||
379 | static struct platform_driver ti_ssp_spi_driver = { | 378 | static struct platform_driver ti_ssp_spi_driver = { |
380 | .probe = ti_ssp_spi_probe, | 379 | .probe = ti_ssp_spi_probe, |
381 | .remove = ti_ssp_spi_remove, | 380 | .remove = __devexit_p(ti_ssp_spi_remove), |
382 | .driver = { | 381 | .driver = { |
383 | .name = "ti-ssp-spi", | 382 | .name = "ti-ssp-spi", |
384 | .owner = THIS_MODULE, | 383 | .owner = THIS_MODULE, |
385 | }, | 384 | }, |
386 | }; | 385 | }; |
387 | module_platform_driver(ti_ssp_spi_driver); | 386 | |
387 | static int __init ti_ssp_spi_init(void) | ||
388 | { | ||
389 | return platform_driver_register(&ti_ssp_spi_driver); | ||
390 | } | ||
391 | module_init(ti_ssp_spi_init); | ||
392 | |||
393 | static void __exit ti_ssp_spi_exit(void) | ||
394 | { | ||
395 | platform_driver_unregister(&ti_ssp_spi_driver); | ||
396 | } | ||
397 | module_exit(ti_ssp_spi_exit); | ||
388 | 398 | ||
389 | MODULE_DESCRIPTION("SSP SPI Master"); | 399 | MODULE_DESCRIPTION("SSP SPI Master"); |
390 | MODULE_AUTHOR("Cyril Chemparathy"); | 400 | MODULE_AUTHOR("Cyril Chemparathy"); |
diff --git a/drivers/spi/spi-tle62x0.c b/drivers/spi/spi-tle62x0.c index 6b0874d782e..940e73d1cf0 100644 --- a/drivers/spi/spi-tle62x0.c +++ b/drivers/spi/spi-tle62x0.c | |||
@@ -11,7 +11,6 @@ | |||
11 | 11 | ||
12 | #include <linux/device.h> | 12 | #include <linux/device.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> | ||
15 | #include <linux/slab.h> | 14 | #include <linux/slab.h> |
16 | 15 | ||
17 | #include <linux/spi/spi.h> | 16 | #include <linux/spi/spi.h> |
@@ -240,7 +239,7 @@ static int to_gpio_num(struct device_attribute *attr) | |||
240 | return -1; | 239 | return -1; |
241 | } | 240 | } |
242 | 241 | ||
243 | static int tle62x0_probe(struct spi_device *spi) | 242 | static int __devinit tle62x0_probe(struct spi_device *spi) |
244 | { | 243 | { |
245 | struct tle62x0_state *st; | 244 | struct tle62x0_state *st; |
246 | struct tle62x0_pdata *pdata; | 245 | struct tle62x0_pdata *pdata; |
@@ -294,7 +293,7 @@ static int tle62x0_probe(struct spi_device *spi) | |||
294 | return ret; | 293 | return ret; |
295 | } | 294 | } |
296 | 295 | ||
297 | static int tle62x0_remove(struct spi_device *spi) | 296 | static int __devexit tle62x0_remove(struct spi_device *spi) |
298 | { | 297 | { |
299 | struct tle62x0_state *st = spi_get_drvdata(spi); | 298 | struct tle62x0_state *st = spi_get_drvdata(spi); |
300 | int ptr; | 299 | int ptr; |
@@ -313,10 +312,21 @@ static struct spi_driver tle62x0_driver = { | |||
313 | .owner = THIS_MODULE, | 312 | .owner = THIS_MODULE, |
314 | }, | 313 | }, |
315 | .probe = tle62x0_probe, | 314 | .probe = tle62x0_probe, |
316 | .remove = tle62x0_remove, | 315 | .remove = __devexit_p(tle62x0_remove), |
317 | }; | 316 | }; |
318 | 317 | ||
319 | module_spi_driver(tle62x0_driver); | 318 | static __init int tle62x0_init(void) |
319 | { | ||
320 | return spi_register_driver(&tle62x0_driver); | ||
321 | } | ||
322 | |||
323 | static __exit void tle62x0_exit(void) | ||
324 | { | ||
325 | spi_unregister_driver(&tle62x0_driver); | ||
326 | } | ||
327 | |||
328 | module_init(tle62x0_init); | ||
329 | module_exit(tle62x0_exit); | ||
320 | 330 | ||
321 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | 331 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
322 | MODULE_DESCRIPTION("TLE62x0 SPI driver"); | 332 | MODULE_DESCRIPTION("TLE62x0 SPI driver"); |
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index f756481b0fe..6a80749391d 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * SPI bus driver for the Topcliff PCH used by Intel SoCs | 2 | * SPI bus driver for the Topcliff PCH used by Intel SoCs |
3 | * | 3 | * |
4 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. | 4 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
@@ -95,18 +95,16 @@ | |||
95 | #define PCH_CLOCK_HZ 50000000 | 95 | #define PCH_CLOCK_HZ 50000000 |
96 | #define PCH_MAX_SPBR 1023 | 96 | #define PCH_MAX_SPBR 1023 |
97 | 97 | ||
98 | /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ | 98 | /* Definition for ML7213 by OKI SEMICONDUCTOR */ |
99 | #define PCI_VENDOR_ID_ROHM 0x10DB | 99 | #define PCI_VENDOR_ID_ROHM 0x10DB |
100 | #define PCI_DEVICE_ID_ML7213_SPI 0x802c | 100 | #define PCI_DEVICE_ID_ML7213_SPI 0x802c |
101 | #define PCI_DEVICE_ID_ML7223_SPI 0x800F | 101 | #define PCI_DEVICE_ID_ML7223_SPI 0x800F |
102 | #define PCI_DEVICE_ID_ML7831_SPI 0x8816 | ||
103 | 102 | ||
104 | /* | 103 | /* |
105 | * Set the number of SPI instance max | 104 | * Set the number of SPI instance max |
106 | * Intel EG20T PCH : 1ch | 105 | * Intel EG20T PCH : 1ch |
107 | * LAPIS Semiconductor ML7213 IOH : 2ch | 106 | * OKI SEMICONDUCTOR ML7213 IOH : 2ch |
108 | * LAPIS Semiconductor ML7223 IOH : 1ch | 107 | * OKI SEMICONDUCTOR ML7223 IOH : 1ch |
109 | * LAPIS Semiconductor ML7831 IOH : 1ch | ||
110 | */ | 108 | */ |
111 | #define PCH_SPI_MAX_DEV 2 | 109 | #define PCH_SPI_MAX_DEV 2 |
112 | 110 | ||
@@ -196,7 +194,6 @@ struct pch_spi_data { | |||
196 | struct pch_spi_dma_ctrl dma; | 194 | struct pch_spi_dma_ctrl dma; |
197 | int use_dma; | 195 | int use_dma; |
198 | u8 irq_reg_sts; | 196 | u8 irq_reg_sts; |
199 | int save_total_len; | ||
200 | }; | 197 | }; |
201 | 198 | ||
202 | /** | 199 | /** |
@@ -217,11 +214,10 @@ struct pch_pd_dev_save { | |||
217 | struct pch_spi_board_data *board_dat; | 214 | struct pch_spi_board_data *board_dat; |
218 | }; | 215 | }; |
219 | 216 | ||
220 | static DEFINE_PCI_DEVICE_TABLE(pch_spi_pcidev_id) = { | 217 | static struct pci_device_id pch_spi_pcidev_id[] = { |
221 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, | 218 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, |
222 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, | 219 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, |
223 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, | 220 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, |
224 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, | ||
225 | { } | 221 | { } |
226 | }; | 222 | }; |
227 | 223 | ||
@@ -319,23 +315,22 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, | |||
319 | data->tx_index = tx_index; | 315 | data->tx_index = tx_index; |
320 | data->rx_index = rx_index; | 316 | data->rx_index = rx_index; |
321 | 317 | ||
322 | /* if transfer complete interrupt */ | 318 | } |
323 | if (reg_spsr_val & SPSR_FI_BIT) { | 319 | |
324 | if ((tx_index == bpw_len) && (rx_index == tx_index)) { | 320 | /* if transfer complete interrupt */ |
325 | /* disable interrupts */ | 321 | if (reg_spsr_val & SPSR_FI_BIT) { |
326 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, | 322 | if ((tx_index == bpw_len) && (rx_index == tx_index)) { |
327 | PCH_ALL); | 323 | /* disable interrupts */ |
328 | 324 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); | |
329 | /* transfer is completed; | 325 | |
330 | inform pch_spi_process_messages */ | 326 | /* transfer is completed; |
331 | data->transfer_complete = true; | 327 | inform pch_spi_process_messages */ |
332 | data->transfer_active = false; | 328 | data->transfer_complete = true; |
333 | wake_up(&data->wait); | 329 | data->transfer_active = false; |
334 | } else { | 330 | wake_up(&data->wait); |
335 | dev_err(&data->master->dev, | 331 | } else { |
336 | "%s : Transfer is not completed", | 332 | dev_err(&data->master->dev, |
337 | __func__); | 333 | "%s : Transfer is not completed", __func__); |
338 | } | ||
339 | } | 334 | } |
340 | } | 335 | } |
341 | } | 336 | } |
@@ -505,7 +500,7 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) | |||
505 | } | 500 | } |
506 | 501 | ||
507 | if (unlikely(pspi->max_speed_hz == 0)) { | 502 | if (unlikely(pspi->max_speed_hz == 0)) { |
508 | dev_err(&pspi->dev, "%s pch_spi_transfer maxspeed=%d\n", | 503 | dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n", |
509 | __func__, pspi->max_speed_hz); | 504 | __func__, pspi->max_speed_hz); |
510 | retval = -EINVAL; | 505 | retval = -EINVAL; |
511 | goto err_out; | 506 | goto err_out; |
@@ -824,13 +819,11 @@ static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) | |||
824 | rx_dma_buf = data->dma.rx_buf_virt; | 819 | rx_dma_buf = data->dma.rx_buf_virt; |
825 | for (j = 0; j < data->bpw_len; j++) | 820 | for (j = 0; j < data->bpw_len; j++) |
826 | *rx_buf++ = *rx_dma_buf++ & 0xFF; | 821 | *rx_buf++ = *rx_dma_buf++ & 0xFF; |
827 | data->cur_trans->rx_buf = rx_buf; | ||
828 | } else { | 822 | } else { |
829 | rx_sbuf = data->cur_trans->rx_buf; | 823 | rx_sbuf = data->cur_trans->rx_buf; |
830 | rx_dma_sbuf = data->dma.rx_buf_virt; | 824 | rx_dma_sbuf = data->dma.rx_buf_virt; |
831 | for (j = 0; j < data->bpw_len; j++) | 825 | for (j = 0; j < data->bpw_len; j++) |
832 | *rx_sbuf++ = *rx_dma_sbuf++; | 826 | *rx_sbuf++ = *rx_dma_sbuf++; |
833 | data->cur_trans->rx_buf = rx_sbuf; | ||
834 | } | 827 | } |
835 | } | 828 | } |
836 | 829 | ||
@@ -856,9 +849,6 @@ static int pch_spi_start_transfer(struct pch_spi_data *data) | |||
856 | rtn = wait_event_interruptible_timeout(data->wait, | 849 | rtn = wait_event_interruptible_timeout(data->wait, |
857 | data->transfer_complete, | 850 | data->transfer_complete, |
858 | msecs_to_jiffies(2 * HZ)); | 851 | msecs_to_jiffies(2 * HZ)); |
859 | if (!rtn) | ||
860 | dev_err(&data->master->dev, | ||
861 | "%s wait-event timeout\n", __func__); | ||
862 | 852 | ||
863 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, | 853 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, |
864 | DMA_FROM_DEVICE); | 854 | DMA_FROM_DEVICE); |
@@ -930,8 +920,7 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) | |||
930 | dma_cap_set(DMA_SLAVE, mask); | 920 | dma_cap_set(DMA_SLAVE, mask); |
931 | 921 | ||
932 | /* Get DMA's dev information */ | 922 | /* Get DMA's dev information */ |
933 | dma_dev = pci_get_bus_and_slot(data->board_dat->pdev->bus->number, | 923 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0)); |
934 | PCI_DEVFN(12, 0)); | ||
935 | 924 | ||
936 | /* Set Tx DMA */ | 925 | /* Set Tx DMA */ |
937 | param = &dma->param_tx; | 926 | param = &dma->param_tx; |
@@ -995,7 +984,6 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
995 | int i; | 984 | int i; |
996 | int size; | 985 | int size; |
997 | int rem; | 986 | int rem; |
998 | int head; | ||
999 | unsigned long flags; | 987 | unsigned long flags; |
1000 | struct pch_spi_dma_ctrl *dma; | 988 | struct pch_spi_dma_ctrl *dma; |
1001 | 989 | ||
@@ -1024,11 +1012,6 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1024 | } | 1012 | } |
1025 | data->bpw_len = data->cur_trans->len / (*bpw / 8); | 1013 | data->bpw_len = data->cur_trans->len / (*bpw / 8); |
1026 | 1014 | ||
1027 | if (data->bpw_len > PCH_BUF_SIZE) { | ||
1028 | data->bpw_len = PCH_BUF_SIZE; | ||
1029 | data->cur_trans->len -= PCH_BUF_SIZE; | ||
1030 | } | ||
1031 | |||
1032 | /* copy Tx Data */ | 1015 | /* copy Tx Data */ |
1033 | if (data->cur_trans->tx_buf != NULL) { | 1016 | if (data->cur_trans->tx_buf != NULL) { |
1034 | if (*bpw == 8) { | 1017 | if (*bpw == 8) { |
@@ -1043,17 +1026,10 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1043 | *tx_dma_sbuf++ = *tx_sbuf++; | 1026 | *tx_dma_sbuf++ = *tx_sbuf++; |
1044 | } | 1027 | } |
1045 | } | 1028 | } |
1046 | |||
1047 | /* Calculate Rx parameter for DMA transmitting */ | ||
1048 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { | 1029 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { |
1049 | if (data->bpw_len % PCH_DMA_TRANS_SIZE) { | 1030 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; |
1050 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; | ||
1051 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE; | ||
1052 | } else { | ||
1053 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; | ||
1054 | rem = PCH_DMA_TRANS_SIZE; | ||
1055 | } | ||
1056 | size = PCH_DMA_TRANS_SIZE; | 1031 | size = PCH_DMA_TRANS_SIZE; |
1032 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE; | ||
1057 | } else { | 1033 | } else { |
1058 | num = 1; | 1034 | num = 1; |
1059 | size = data->bpw_len; | 1035 | size = data->bpw_len; |
@@ -1099,8 +1075,8 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1099 | sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; | 1075 | sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; |
1100 | } | 1076 | } |
1101 | sg = dma->sg_rx_p; | 1077 | sg = dma->sg_rx_p; |
1102 | desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg, | 1078 | desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg, |
1103 | num, DMA_DEV_TO_MEM, | 1079 | num, DMA_FROM_DEVICE, |
1104 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 1080 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1105 | if (!desc_rx) { | 1081 | if (!desc_rx) { |
1106 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", | 1082 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", |
@@ -1113,23 +1089,15 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1113 | dma->nent = num; | 1089 | dma->nent = num; |
1114 | dma->desc_rx = desc_rx; | 1090 | dma->desc_rx = desc_rx; |
1115 | 1091 | ||
1116 | /* Calculate Tx parameter for DMA transmitting */ | 1092 | /* TX */ |
1117 | if (data->bpw_len > PCH_MAX_FIFO_DEPTH) { | 1093 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { |
1118 | head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE; | 1094 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; |
1119 | if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) { | ||
1120 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; | ||
1121 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head; | ||
1122 | } else { | ||
1123 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; | ||
1124 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE + | ||
1125 | PCH_DMA_TRANS_SIZE - head; | ||
1126 | } | ||
1127 | size = PCH_DMA_TRANS_SIZE; | 1095 | size = PCH_DMA_TRANS_SIZE; |
1096 | rem = 16; | ||
1128 | } else { | 1097 | } else { |
1129 | num = 1; | 1098 | num = 1; |
1130 | size = data->bpw_len; | 1099 | size = data->bpw_len; |
1131 | rem = data->bpw_len; | 1100 | rem = data->bpw_len; |
1132 | head = 0; | ||
1133 | } | 1101 | } |
1134 | 1102 | ||
1135 | dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); | 1103 | dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
@@ -1139,17 +1107,11 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1139 | for (i = 0; i < num; i++, sg++) { | 1107 | for (i = 0; i < num; i++, sg++) { |
1140 | if (i == 0) { | 1108 | if (i == 0) { |
1141 | sg->offset = 0; | 1109 | sg->offset = 0; |
1142 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head, | ||
1143 | sg->offset); | ||
1144 | sg_dma_len(sg) = size + head; | ||
1145 | } else if (i == (num - 1)) { | ||
1146 | sg->offset = head + size * i; | ||
1147 | sg->offset = sg->offset * (*bpw / 8); | ||
1148 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, | 1110 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, |
1149 | sg->offset); | 1111 | sg->offset); |
1150 | sg_dma_len(sg) = rem; | 1112 | sg_dma_len(sg) = rem; |
1151 | } else { | 1113 | } else { |
1152 | sg->offset = head + size * i; | 1114 | sg->offset = rem + size * (i - 1); |
1153 | sg->offset = sg->offset * (*bpw / 8); | 1115 | sg->offset = sg->offset * (*bpw / 8); |
1154 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, | 1116 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, |
1155 | sg->offset); | 1117 | sg->offset); |
@@ -1158,8 +1120,8 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |||
1158 | sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; | 1120 | sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; |
1159 | } | 1121 | } |
1160 | sg = dma->sg_tx_p; | 1122 | sg = dma->sg_tx_p; |
1161 | desc_tx = dmaengine_prep_slave_sg(dma->chan_tx, | 1123 | desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx, |
1162 | sg, num, DMA_MEM_TO_DEV, | 1124 | sg, num, DMA_TO_DEVICE, |
1163 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 1125 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1164 | if (!desc_tx) { | 1126 | if (!desc_tx) { |
1165 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", | 1127 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", |
@@ -1237,7 +1199,6 @@ static void pch_spi_process_messages(struct work_struct *pwork) | |||
1237 | data->current_msg->spi->bits_per_word); | 1199 | data->current_msg->spi->bits_per_word); |
1238 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); | 1200 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); |
1239 | do { | 1201 | do { |
1240 | int cnt; | ||
1241 | /* If we are already processing a message get the next | 1202 | /* If we are already processing a message get the next |
1242 | transfer structure from the message otherwise retrieve | 1203 | transfer structure from the message otherwise retrieve |
1243 | the 1st transfer request from the message. */ | 1204 | the 1st transfer request from the message. */ |
@@ -1257,28 +1218,11 @@ static void pch_spi_process_messages(struct work_struct *pwork) | |||
1257 | } | 1218 | } |
1258 | spin_unlock(&data->lock); | 1219 | spin_unlock(&data->lock); |
1259 | 1220 | ||
1260 | if (!data->cur_trans->len) | ||
1261 | goto out; | ||
1262 | cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1; | ||
1263 | data->save_total_len = data->cur_trans->len; | ||
1264 | if (data->use_dma) { | 1221 | if (data->use_dma) { |
1265 | int i; | 1222 | pch_spi_handle_dma(data, &bpw); |
1266 | char *save_rx_buf = data->cur_trans->rx_buf; | 1223 | if (!pch_spi_start_transfer(data)) |
1267 | for (i = 0; i < cnt; i ++) { | 1224 | goto out; |
1268 | pch_spi_handle_dma(data, &bpw); | 1225 | pch_spi_copy_rx_data_for_dma(data, bpw); |
1269 | if (!pch_spi_start_transfer(data)) { | ||
1270 | data->transfer_complete = true; | ||
1271 | data->current_msg->status = -EIO; | ||
1272 | data->current_msg->complete | ||
1273 | (data->current_msg->context); | ||
1274 | data->bcurrent_msg_processing = false; | ||
1275 | data->current_msg = NULL; | ||
1276 | data->cur_trans = NULL; | ||
1277 | goto out; | ||
1278 | } | ||
1279 | pch_spi_copy_rx_data_for_dma(data, bpw); | ||
1280 | } | ||
1281 | data->cur_trans->rx_buf = save_rx_buf; | ||
1282 | } else { | 1226 | } else { |
1283 | pch_spi_set_tx(data, &bpw); | 1227 | pch_spi_set_tx(data, &bpw); |
1284 | pch_spi_set_ir(data); | 1228 | pch_spi_set_ir(data); |
@@ -1289,7 +1233,6 @@ static void pch_spi_process_messages(struct work_struct *pwork) | |||
1289 | data->pkt_tx_buff = NULL; | 1233 | data->pkt_tx_buff = NULL; |
1290 | } | 1234 | } |
1291 | /* increment message count */ | 1235 | /* increment message count */ |
1292 | data->cur_trans->len = data->save_total_len; | ||
1293 | data->current_msg->actual_length += data->cur_trans->len; | 1236 | data->current_msg->actual_length += data->cur_trans->len; |
1294 | 1237 | ||
1295 | dev_dbg(&data->master->dev, | 1238 | dev_dbg(&data->master->dev, |
@@ -1401,7 +1344,7 @@ static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, | |||
1401 | PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); | 1344 | PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); |
1402 | } | 1345 | } |
1403 | 1346 | ||
1404 | static int pch_spi_pd_probe(struct platform_device *plat_dev) | 1347 | static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) |
1405 | { | 1348 | { |
1406 | int ret; | 1349 | int ret; |
1407 | struct spi_master *master; | 1350 | struct spi_master *master; |
@@ -1438,10 +1381,10 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev) | |||
1438 | plat_dev->id, data->io_remap_addr); | 1381 | plat_dev->id, data->io_remap_addr); |
1439 | 1382 | ||
1440 | /* initialize members of SPI master */ | 1383 | /* initialize members of SPI master */ |
1384 | master->bus_num = -1; | ||
1441 | master->num_chipselect = PCH_MAX_CS; | 1385 | master->num_chipselect = PCH_MAX_CS; |
1442 | master->setup = pch_spi_setup; | 1386 | master->setup = pch_spi_setup; |
1443 | master->transfer = pch_spi_transfer; | 1387 | master->transfer = pch_spi_transfer; |
1444 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | ||
1445 | 1388 | ||
1446 | data->board_dat = board_dat; | 1389 | data->board_dat = board_dat; |
1447 | data->plat_dev = plat_dev; | 1390 | data->plat_dev = plat_dev; |
@@ -1498,7 +1441,7 @@ err_pci_iomap: | |||
1498 | return ret; | 1441 | return ret; |
1499 | } | 1442 | } |
1500 | 1443 | ||
1501 | static int pch_spi_pd_remove(struct platform_device *plat_dev) | 1444 | static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev) |
1502 | { | 1445 | { |
1503 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); | 1446 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
1504 | struct pch_spi_data *data = platform_get_drvdata(plat_dev); | 1447 | struct pch_spi_data *data = platform_get_drvdata(plat_dev); |
@@ -1536,6 +1479,8 @@ static int pch_spi_pd_remove(struct platform_device *plat_dev) | |||
1536 | 1479 | ||
1537 | pci_iounmap(board_dat->pdev, data->io_remap_addr); | 1480 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
1538 | spi_unregister_master(data->master); | 1481 | spi_unregister_master(data->master); |
1482 | spi_master_put(data->master); | ||
1483 | platform_set_drvdata(plat_dev, NULL); | ||
1539 | 1484 | ||
1540 | return 0; | 1485 | return 0; |
1541 | } | 1486 | } |
@@ -1619,12 +1564,12 @@ static struct platform_driver pch_spi_pd_driver = { | |||
1619 | .owner = THIS_MODULE, | 1564 | .owner = THIS_MODULE, |
1620 | }, | 1565 | }, |
1621 | .probe = pch_spi_pd_probe, | 1566 | .probe = pch_spi_pd_probe, |
1622 | .remove = pch_spi_pd_remove, | 1567 | .remove = __devexit_p(pch_spi_pd_remove), |
1623 | .suspend = pch_spi_pd_suspend, | 1568 | .suspend = pch_spi_pd_suspend, |
1624 | .resume = pch_spi_pd_resume | 1569 | .resume = pch_spi_pd_resume |
1625 | }; | 1570 | }; |
1626 | 1571 | ||
1627 | static int pch_spi_probe(struct pci_dev *pdev, | 1572 | static int __devinit pch_spi_probe(struct pci_dev *pdev, |
1628 | const struct pci_device_id *id) | 1573 | const struct pci_device_id *id) |
1629 | { | 1574 | { |
1630 | struct pch_spi_board_data *board_dat; | 1575 | struct pch_spi_board_data *board_dat; |
@@ -1705,7 +1650,7 @@ err_no_mem: | |||
1705 | return retval; | 1650 | return retval; |
1706 | } | 1651 | } |
1707 | 1652 | ||
1708 | static void pch_spi_remove(struct pci_dev *pdev) | 1653 | static void __devexit pch_spi_remove(struct pci_dev *pdev) |
1709 | { | 1654 | { |
1710 | int i; | 1655 | int i; |
1711 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); | 1656 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
@@ -1772,7 +1717,7 @@ static int pch_spi_resume(struct pci_dev *pdev) | |||
1772 | 1717 | ||
1773 | #endif | 1718 | #endif |
1774 | 1719 | ||
1775 | static struct pci_driver pch_spi_pcidev_driver = { | 1720 | static struct pci_driver pch_spi_pcidev = { |
1776 | .name = "pch_spi", | 1721 | .name = "pch_spi", |
1777 | .id_table = pch_spi_pcidev_id, | 1722 | .id_table = pch_spi_pcidev_id, |
1778 | .probe = pch_spi_probe, | 1723 | .probe = pch_spi_probe, |
@@ -1788,7 +1733,7 @@ static int __init pch_spi_init(void) | |||
1788 | if (ret) | 1733 | if (ret) |
1789 | return ret; | 1734 | return ret; |
1790 | 1735 | ||
1791 | ret = pci_register_driver(&pch_spi_pcidev_driver); | 1736 | ret = pci_register_driver(&pch_spi_pcidev); |
1792 | if (ret) | 1737 | if (ret) |
1793 | return ret; | 1738 | return ret; |
1794 | 1739 | ||
@@ -1798,7 +1743,7 @@ module_init(pch_spi_init); | |||
1798 | 1743 | ||
1799 | static void __exit pch_spi_exit(void) | 1744 | static void __exit pch_spi_exit(void) |
1800 | { | 1745 | { |
1801 | pci_unregister_driver(&pch_spi_pcidev_driver); | 1746 | pci_unregister_driver(&pch_spi_pcidev); |
1802 | platform_driver_unregister(&pch_spi_pd_driver); | 1747 | platform_driver_unregister(&pch_spi_pd_driver); |
1803 | } | 1748 | } |
1804 | module_exit(pch_spi_exit); | 1749 | module_exit(pch_spi_exit); |
@@ -1808,4 +1753,4 @@ MODULE_PARM_DESC(use_dma, | |||
1808 | "to use DMA for data transfers pass 1 else 0; default 1"); | 1753 | "to use DMA for data transfers pass 1 else 0; default 1"); |
1809 | 1754 | ||
1810 | MODULE_LICENSE("GPL"); | 1755 | MODULE_LICENSE("GPL"); |
1811 | MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); | 1756 | MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver"); |
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c index d5a3cbb646c..f0a2ab0428a 100644 --- a/drivers/spi/spi-txx9.c +++ b/drivers/spi/spi-txx9.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <linux/err.h> | 25 | #include <linux/err.h> |
26 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
28 | #include <linux/module.h> | ||
29 | #include <asm/gpio.h> | 28 | #include <asm/gpio.h> |
30 | 29 | ||
31 | 30 | ||
diff --git a/drivers/spi/spi-xcomm.c b/drivers/spi/spi-xcomm.c deleted file mode 100644 index 4d3ec8b9f47..00000000000 --- a/drivers/spi/spi-xcomm.c +++ /dev/null | |||
@@ -1,276 +0,0 @@ | |||
1 | /* | ||
2 | * Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver | ||
3 | * | ||
4 | * Copyright 2012 Analog Devices Inc. | ||
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | ||
6 | * | ||
7 | * Licensed under the GPL-2 or later. | ||
8 | */ | ||
9 | |||
10 | #include <linux/kernel.h> | ||
11 | #include <linux/init.h> | ||
12 | #include <linux/module.h> | ||
13 | #include <linux/delay.h> | ||
14 | #include <linux/i2c.h> | ||
15 | #include <linux/spi/spi.h> | ||
16 | #include <asm/unaligned.h> | ||
17 | |||
18 | #define SPI_XCOMM_SETTINGS_LEN_OFFSET 10 | ||
19 | #define SPI_XCOMM_SETTINGS_3WIRE BIT(6) | ||
20 | #define SPI_XCOMM_SETTINGS_CS_HIGH BIT(5) | ||
21 | #define SPI_XCOMM_SETTINGS_SAMPLE_END BIT(4) | ||
22 | #define SPI_XCOMM_SETTINGS_CPHA BIT(3) | ||
23 | #define SPI_XCOMM_SETTINGS_CPOL BIT(2) | ||
24 | #define SPI_XCOMM_SETTINGS_CLOCK_DIV_MASK 0x3 | ||
25 | #define SPI_XCOMM_SETTINGS_CLOCK_DIV_64 0x2 | ||
26 | #define SPI_XCOMM_SETTINGS_CLOCK_DIV_16 0x1 | ||
27 | #define SPI_XCOMM_SETTINGS_CLOCK_DIV_4 0x0 | ||
28 | |||
29 | #define SPI_XCOMM_CMD_UPDATE_CONFIG 0x03 | ||
30 | #define SPI_XCOMM_CMD_WRITE 0x04 | ||
31 | |||
32 | #define SPI_XCOMM_CLOCK 48000000 | ||
33 | |||
34 | struct spi_xcomm { | ||
35 | struct i2c_client *i2c; | ||
36 | |||
37 | uint16_t settings; | ||
38 | uint16_t chipselect; | ||
39 | |||
40 | unsigned int current_speed; | ||
41 | |||
42 | uint8_t buf[63]; | ||
43 | }; | ||
44 | |||
45 | static int spi_xcomm_sync_config(struct spi_xcomm *spi_xcomm, unsigned int len) | ||
46 | { | ||
47 | uint16_t settings; | ||
48 | uint8_t *buf = spi_xcomm->buf; | ||
49 | |||
50 | settings = spi_xcomm->settings; | ||
51 | settings |= len << SPI_XCOMM_SETTINGS_LEN_OFFSET; | ||
52 | |||
53 | buf[0] = SPI_XCOMM_CMD_UPDATE_CONFIG; | ||
54 | put_unaligned_be16(settings, &buf[1]); | ||
55 | put_unaligned_be16(spi_xcomm->chipselect, &buf[3]); | ||
56 | |||
57 | return i2c_master_send(spi_xcomm->i2c, buf, 5); | ||
58 | } | ||
59 | |||
60 | static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm, | ||
61 | struct spi_device *spi, int is_active) | ||
62 | { | ||
63 | unsigned long cs = spi->chip_select; | ||
64 | uint16_t chipselect = spi_xcomm->chipselect; | ||
65 | |||
66 | if (is_active) | ||
67 | chipselect |= BIT(cs); | ||
68 | else | ||
69 | chipselect &= ~BIT(cs); | ||
70 | |||
71 | spi_xcomm->chipselect = chipselect; | ||
72 | } | ||
73 | |||
74 | static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm, | ||
75 | struct spi_device *spi, struct spi_transfer *t, unsigned int *settings) | ||
76 | { | ||
77 | unsigned int speed; | ||
78 | |||
79 | if ((t->bits_per_word && t->bits_per_word != 8) || t->len > 62) | ||
80 | return -EINVAL; | ||
81 | |||
82 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | ||
83 | |||
84 | if (speed != spi_xcomm->current_speed) { | ||
85 | unsigned int divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, speed); | ||
86 | if (divider >= 64) | ||
87 | *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_64; | ||
88 | else if (divider >= 16) | ||
89 | *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_16; | ||
90 | else | ||
91 | *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_4; | ||
92 | |||
93 | spi_xcomm->current_speed = speed; | ||
94 | } | ||
95 | |||
96 | if (spi->mode & SPI_CPOL) | ||
97 | *settings |= SPI_XCOMM_SETTINGS_CPOL; | ||
98 | else | ||
99 | *settings &= ~SPI_XCOMM_SETTINGS_CPOL; | ||
100 | |||
101 | if (spi->mode & SPI_CPHA) | ||
102 | *settings &= ~SPI_XCOMM_SETTINGS_CPHA; | ||
103 | else | ||
104 | *settings |= SPI_XCOMM_SETTINGS_CPHA; | ||
105 | |||
106 | if (spi->mode & SPI_3WIRE) | ||
107 | *settings |= SPI_XCOMM_SETTINGS_3WIRE; | ||
108 | else | ||
109 | *settings &= ~SPI_XCOMM_SETTINGS_3WIRE; | ||
110 | |||
111 | return 0; | ||
112 | } | ||
113 | |||
114 | static int spi_xcomm_txrx_bufs(struct spi_xcomm *spi_xcomm, | ||
115 | struct spi_device *spi, struct spi_transfer *t) | ||
116 | { | ||
117 | int ret; | ||
118 | |||
119 | if (t->tx_buf) { | ||
120 | spi_xcomm->buf[0] = SPI_XCOMM_CMD_WRITE; | ||
121 | memcpy(spi_xcomm->buf + 1, t->tx_buf, t->len); | ||
122 | |||
123 | ret = i2c_master_send(spi_xcomm->i2c, spi_xcomm->buf, t->len + 1); | ||
124 | if (ret < 0) | ||
125 | return ret; | ||
126 | else if (ret != t->len + 1) | ||
127 | return -EIO; | ||
128 | } else if (t->rx_buf) { | ||
129 | ret = i2c_master_recv(spi_xcomm->i2c, t->rx_buf, t->len); | ||
130 | if (ret < 0) | ||
131 | return ret; | ||
132 | else if (ret != t->len) | ||
133 | return -EIO; | ||
134 | } | ||
135 | |||
136 | return t->len; | ||
137 | } | ||
138 | |||
139 | static int spi_xcomm_transfer_one(struct spi_master *master, | ||
140 | struct spi_message *msg) | ||
141 | { | ||
142 | struct spi_xcomm *spi_xcomm = spi_master_get_devdata(master); | ||
143 | unsigned int settings = spi_xcomm->settings; | ||
144 | struct spi_device *spi = msg->spi; | ||
145 | unsigned cs_change = 0; | ||
146 | struct spi_transfer *t; | ||
147 | bool is_first = true; | ||
148 | int status = 0; | ||
149 | bool is_last; | ||
150 | |||
151 | is_first = true; | ||
152 | |||
153 | spi_xcomm_chipselect(spi_xcomm, spi, true); | ||
154 | |||
155 | list_for_each_entry(t, &msg->transfers, transfer_list) { | ||
156 | |||
157 | if (!t->tx_buf && !t->rx_buf && t->len) { | ||
158 | status = -EINVAL; | ||
159 | break; | ||
160 | } | ||
161 | |||
162 | status = spi_xcomm_setup_transfer(spi_xcomm, spi, t, &settings); | ||
163 | if (status < 0) | ||
164 | break; | ||
165 | |||
166 | is_last = list_is_last(&t->transfer_list, &msg->transfers); | ||
167 | cs_change = t->cs_change; | ||
168 | |||
169 | if (cs_change ^ is_last) | ||
170 | settings |= BIT(5); | ||
171 | else | ||
172 | settings &= ~BIT(5); | ||
173 | |||
174 | if (t->rx_buf) { | ||
175 | spi_xcomm->settings = settings; | ||
176 | status = spi_xcomm_sync_config(spi_xcomm, t->len); | ||
177 | if (status < 0) | ||
178 | break; | ||
179 | } else if (settings != spi_xcomm->settings || is_first) { | ||
180 | spi_xcomm->settings = settings; | ||
181 | status = spi_xcomm_sync_config(spi_xcomm, 0); | ||
182 | if (status < 0) | ||
183 | break; | ||
184 | } | ||
185 | |||
186 | if (t->len) { | ||
187 | status = spi_xcomm_txrx_bufs(spi_xcomm, spi, t); | ||
188 | |||
189 | if (status < 0) | ||
190 | break; | ||
191 | |||
192 | if (status > 0) | ||
193 | msg->actual_length += status; | ||
194 | } | ||
195 | status = 0; | ||
196 | |||
197 | if (t->delay_usecs) | ||
198 | udelay(t->delay_usecs); | ||
199 | |||
200 | is_first = false; | ||
201 | } | ||
202 | |||
203 | if (status != 0 || !cs_change) | ||
204 | spi_xcomm_chipselect(spi_xcomm, spi, false); | ||
205 | |||
206 | msg->status = status; | ||
207 | spi_finalize_current_message(master); | ||
208 | |||
209 | return status; | ||
210 | } | ||
211 | |||
212 | static int spi_xcomm_setup(struct spi_device *spi) | ||
213 | { | ||
214 | if (spi->bits_per_word != 8) | ||
215 | return -EINVAL; | ||
216 | |||
217 | return 0; | ||
218 | } | ||
219 | |||
220 | static int spi_xcomm_probe(struct i2c_client *i2c, | ||
221 | const struct i2c_device_id *id) | ||
222 | { | ||
223 | struct spi_xcomm *spi_xcomm; | ||
224 | struct spi_master *master; | ||
225 | int ret; | ||
226 | |||
227 | master = spi_alloc_master(&i2c->dev, sizeof(*spi_xcomm)); | ||
228 | if (!master) | ||
229 | return -ENOMEM; | ||
230 | |||
231 | spi_xcomm = spi_master_get_devdata(master); | ||
232 | spi_xcomm->i2c = i2c; | ||
233 | |||
234 | master->num_chipselect = 16; | ||
235 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_3WIRE; | ||
236 | master->flags = SPI_MASTER_HALF_DUPLEX; | ||
237 | master->setup = spi_xcomm_setup; | ||
238 | master->transfer_one_message = spi_xcomm_transfer_one; | ||
239 | master->dev.of_node = i2c->dev.of_node; | ||
240 | i2c_set_clientdata(i2c, master); | ||
241 | |||
242 | ret = spi_register_master(master); | ||
243 | if (ret < 0) | ||
244 | spi_master_put(master); | ||
245 | |||
246 | return ret; | ||
247 | } | ||
248 | |||
249 | static int spi_xcomm_remove(struct i2c_client *i2c) | ||
250 | { | ||
251 | struct spi_master *master = i2c_get_clientdata(i2c); | ||
252 | |||
253 | spi_unregister_master(master); | ||
254 | |||
255 | return 0; | ||
256 | } | ||
257 | |||
258 | static const struct i2c_device_id spi_xcomm_ids[] = { | ||
259 | { "spi-xcomm" }, | ||
260 | { }, | ||
261 | }; | ||
262 | |||
263 | static struct i2c_driver spi_xcomm_driver = { | ||
264 | .driver = { | ||
265 | .name = "spi-xcomm", | ||
266 | .owner = THIS_MODULE, | ||
267 | }, | ||
268 | .id_table = spi_xcomm_ids, | ||
269 | .probe = spi_xcomm_probe, | ||
270 | .remove = spi_xcomm_remove, | ||
271 | }; | ||
272 | module_i2c_driver(spi_xcomm_driver); | ||
273 | |||
274 | MODULE_LICENSE("GPL"); | ||
275 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | ||
276 | MODULE_DESCRIPTION("Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver"); | ||
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index e1d76960742..4d2c75df886 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c | |||
@@ -462,7 +462,7 @@ void xilinx_spi_deinit(struct spi_master *master) | |||
462 | } | 462 | } |
463 | EXPORT_SYMBOL(xilinx_spi_deinit); | 463 | EXPORT_SYMBOL(xilinx_spi_deinit); |
464 | 464 | ||
465 | static int xilinx_spi_probe(struct platform_device *dev) | 465 | static int __devinit xilinx_spi_probe(struct platform_device *dev) |
466 | { | 466 | { |
467 | struct xspi_platform_data *pdata; | 467 | struct xspi_platform_data *pdata; |
468 | struct resource *r; | 468 | struct resource *r; |
@@ -518,7 +518,7 @@ static int xilinx_spi_probe(struct platform_device *dev) | |||
518 | return 0; | 518 | return 0; |
519 | } | 519 | } |
520 | 520 | ||
521 | static int xilinx_spi_remove(struct platform_device *dev) | 521 | static int __devexit xilinx_spi_remove(struct platform_device *dev) |
522 | { | 522 | { |
523 | xilinx_spi_deinit(platform_get_drvdata(dev)); | 523 | xilinx_spi_deinit(platform_get_drvdata(dev)); |
524 | platform_set_drvdata(dev, 0); | 524 | platform_set_drvdata(dev, 0); |
@@ -531,14 +531,25 @@ MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |||
531 | 531 | ||
532 | static struct platform_driver xilinx_spi_driver = { | 532 | static struct platform_driver xilinx_spi_driver = { |
533 | .probe = xilinx_spi_probe, | 533 | .probe = xilinx_spi_probe, |
534 | .remove = xilinx_spi_remove, | 534 | .remove = __devexit_p(xilinx_spi_remove), |
535 | .driver = { | 535 | .driver = { |
536 | .name = XILINX_SPI_NAME, | 536 | .name = XILINX_SPI_NAME, |
537 | .owner = THIS_MODULE, | 537 | .owner = THIS_MODULE, |
538 | .of_match_table = xilinx_spi_of_match, | 538 | .of_match_table = xilinx_spi_of_match, |
539 | }, | 539 | }, |
540 | }; | 540 | }; |
541 | module_platform_driver(xilinx_spi_driver); | 541 | |
542 | static int __init xilinx_spi_pltfm_init(void) | ||
543 | { | ||
544 | return platform_driver_register(&xilinx_spi_driver); | ||
545 | } | ||
546 | module_init(xilinx_spi_pltfm_init); | ||
547 | |||
548 | static void __exit xilinx_spi_pltfm_exit(void) | ||
549 | { | ||
550 | platform_driver_unregister(&xilinx_spi_driver); | ||
551 | } | ||
552 | module_exit(xilinx_spi_pltfm_exit); | ||
542 | 553 | ||
543 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | 554 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
544 | MODULE_DESCRIPTION("Xilinx SPI driver"); | 555 | MODULE_DESCRIPTION("Xilinx SPI driver"); |
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 19ee901577d..4d1b9f517ce 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c | |||
@@ -2,7 +2,6 @@ | |||
2 | * SPI init/core code | 2 | * SPI init/core code |
3 | * | 3 | * |
4 | * Copyright (C) 2005 David Brownell | 4 | * Copyright (C) 2005 David Brownell |
5 | * Copyright (C) 2008 Secret Lab Technologies Ltd. | ||
6 | * | 5 | * |
7 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
@@ -20,24 +19,16 @@ | |||
20 | */ | 19 | */ |
21 | 20 | ||
22 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
23 | #include <linux/kmod.h> | ||
24 | #include <linux/device.h> | 22 | #include <linux/device.h> |
25 | #include <linux/init.h> | 23 | #include <linux/init.h> |
26 | #include <linux/cache.h> | 24 | #include <linux/cache.h> |
27 | #include <linux/mutex.h> | 25 | #include <linux/mutex.h> |
28 | #include <linux/of_device.h> | 26 | #include <linux/of_device.h> |
29 | #include <linux/of_irq.h> | ||
30 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
31 | #include <linux/mod_devicetable.h> | 28 | #include <linux/mod_devicetable.h> |
32 | #include <linux/spi/spi.h> | 29 | #include <linux/spi/spi.h> |
33 | #include <linux/of_gpio.h> | 30 | #include <linux/of_spi.h> |
34 | #include <linux/pm_runtime.h> | 31 | #include <linux/pm_runtime.h> |
35 | #include <linux/export.h> | ||
36 | #include <linux/sched.h> | ||
37 | #include <linux/delay.h> | ||
38 | #include <linux/kthread.h> | ||
39 | #include <linux/ioport.h> | ||
40 | #include <linux/acpi.h> | ||
41 | 32 | ||
42 | static void spidev_release(struct device *dev) | 33 | static void spidev_release(struct device *dev) |
43 | { | 34 | { |
@@ -56,7 +47,7 @@ modalias_show(struct device *dev, struct device_attribute *a, char *buf) | |||
56 | { | 47 | { |
57 | const struct spi_device *spi = to_spi_device(dev); | 48 | const struct spi_device *spi = to_spi_device(dev); |
58 | 49 | ||
59 | return sprintf(buf, "%s%s\n", SPI_MODULE_PREFIX, spi->modalias); | 50 | return sprintf(buf, "%s\n", spi->modalias); |
60 | } | 51 | } |
61 | 52 | ||
62 | static struct device_attribute spi_dev_attrs[] = { | 53 | static struct device_attribute spi_dev_attrs[] = { |
@@ -96,10 +87,6 @@ static int spi_match_device(struct device *dev, struct device_driver *drv) | |||
96 | if (of_driver_match_device(dev, drv)) | 87 | if (of_driver_match_device(dev, drv)) |
97 | return 1; | 88 | return 1; |
98 | 89 | ||
99 | /* Then try ACPI */ | ||
100 | if (acpi_driver_match_device(dev, drv)) | ||
101 | return 1; | ||
102 | |||
103 | if (sdrv->id_table) | 90 | if (sdrv->id_table) |
104 | return !!spi_match_id(sdrv->id_table, spi); | 91 | return !!spi_match_id(sdrv->id_table, spi); |
105 | 92 | ||
@@ -331,10 +318,9 @@ struct spi_device *spi_alloc_device(struct spi_master *master) | |||
331 | } | 318 | } |
332 | 319 | ||
333 | spi->master = master; | 320 | spi->master = master; |
334 | spi->dev.parent = &master->dev; | 321 | spi->dev.parent = dev; |
335 | spi->dev.bus = &spi_bus_type; | 322 | spi->dev.bus = &spi_bus_type; |
336 | spi->dev.release = spidev_release; | 323 | spi->dev.release = spidev_release; |
337 | spi->cs_gpio = -EINVAL; | ||
338 | device_initialize(&spi->dev); | 324 | device_initialize(&spi->dev); |
339 | return spi; | 325 | return spi; |
340 | } | 326 | } |
@@ -352,16 +338,15 @@ EXPORT_SYMBOL_GPL(spi_alloc_device); | |||
352 | int spi_add_device(struct spi_device *spi) | 338 | int spi_add_device(struct spi_device *spi) |
353 | { | 339 | { |
354 | static DEFINE_MUTEX(spi_add_lock); | 340 | static DEFINE_MUTEX(spi_add_lock); |
355 | struct spi_master *master = spi->master; | 341 | struct device *dev = spi->master->dev.parent; |
356 | struct device *dev = master->dev.parent; | ||
357 | struct device *d; | 342 | struct device *d; |
358 | int status; | 343 | int status; |
359 | 344 | ||
360 | /* Chipselects are numbered 0..max; validate. */ | 345 | /* Chipselects are numbered 0..max; validate. */ |
361 | if (spi->chip_select >= master->num_chipselect) { | 346 | if (spi->chip_select >= spi->master->num_chipselect) { |
362 | dev_err(dev, "cs%d >= max %d\n", | 347 | dev_err(dev, "cs%d >= max %d\n", |
363 | spi->chip_select, | 348 | spi->chip_select, |
364 | master->num_chipselect); | 349 | spi->master->num_chipselect); |
365 | return -EINVAL; | 350 | return -EINVAL; |
366 | } | 351 | } |
367 | 352 | ||
@@ -385,9 +370,6 @@ int spi_add_device(struct spi_device *spi) | |||
385 | goto done; | 370 | goto done; |
386 | } | 371 | } |
387 | 372 | ||
388 | if (master->cs_gpios) | ||
389 | spi->cs_gpio = master->cs_gpios[spi->chip_select]; | ||
390 | |||
391 | /* Drivers may modify this initial i/o setup, but will | 373 | /* Drivers may modify this initial i/o setup, but will |
392 | * normally rely on the device being setup. Devices | 374 | * normally rely on the device being setup. Devices |
393 | * using SPI_CS_HIGH can't coexist well otherwise... | 375 | * using SPI_CS_HIGH can't coexist well otherwise... |
@@ -498,7 +480,8 @@ static void spi_match_master_to_boardinfo(struct spi_master *master, | |||
498 | * The board info passed can safely be __initdata ... but be careful of | 480 | * The board info passed can safely be __initdata ... but be careful of |
499 | * any embedded pointers (platform_data, etc), they're copied as-is. | 481 | * any embedded pointers (platform_data, etc), they're copied as-is. |
500 | */ | 482 | */ |
501 | int spi_register_board_info(struct spi_board_info const *info, unsigned n) | 483 | int __init |
484 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | ||
502 | { | 485 | { |
503 | struct boardinfo *bi; | 486 | struct boardinfo *bi; |
504 | int i; | 487 | int i; |
@@ -523,481 +506,6 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) | |||
523 | 506 | ||
524 | /*-------------------------------------------------------------------------*/ | 507 | /*-------------------------------------------------------------------------*/ |
525 | 508 | ||
526 | /** | ||
527 | * spi_pump_messages - kthread work function which processes spi message queue | ||
528 | * @work: pointer to kthread work struct contained in the master struct | ||
529 | * | ||
530 | * This function checks if there is any spi message in the queue that | ||
531 | * needs processing and if so call out to the driver to initialize hardware | ||
532 | * and transfer each message. | ||
533 | * | ||
534 | */ | ||
535 | static void spi_pump_messages(struct kthread_work *work) | ||
536 | { | ||
537 | struct spi_master *master = | ||
538 | container_of(work, struct spi_master, pump_messages); | ||
539 | unsigned long flags; | ||
540 | bool was_busy = false; | ||
541 | int ret; | ||
542 | |||
543 | /* Lock queue and check for queue work */ | ||
544 | spin_lock_irqsave(&master->queue_lock, flags); | ||
545 | if (list_empty(&master->queue) || !master->running) { | ||
546 | if (master->busy && master->unprepare_transfer_hardware) { | ||
547 | ret = master->unprepare_transfer_hardware(master); | ||
548 | if (ret) { | ||
549 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
550 | dev_err(&master->dev, | ||
551 | "failed to unprepare transfer hardware\n"); | ||
552 | return; | ||
553 | } | ||
554 | } | ||
555 | master->busy = false; | ||
556 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
557 | return; | ||
558 | } | ||
559 | |||
560 | /* Make sure we are not already running a message */ | ||
561 | if (master->cur_msg) { | ||
562 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
563 | return; | ||
564 | } | ||
565 | /* Extract head of queue */ | ||
566 | master->cur_msg = | ||
567 | list_entry(master->queue.next, struct spi_message, queue); | ||
568 | |||
569 | list_del_init(&master->cur_msg->queue); | ||
570 | if (master->busy) | ||
571 | was_busy = true; | ||
572 | else | ||
573 | master->busy = true; | ||
574 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
575 | |||
576 | if (!was_busy && master->prepare_transfer_hardware) { | ||
577 | ret = master->prepare_transfer_hardware(master); | ||
578 | if (ret) { | ||
579 | dev_err(&master->dev, | ||
580 | "failed to prepare transfer hardware\n"); | ||
581 | return; | ||
582 | } | ||
583 | } | ||
584 | |||
585 | ret = master->transfer_one_message(master, master->cur_msg); | ||
586 | if (ret) { | ||
587 | dev_err(&master->dev, | ||
588 | "failed to transfer one message from queue\n"); | ||
589 | return; | ||
590 | } | ||
591 | } | ||
592 | |||
593 | static int spi_init_queue(struct spi_master *master) | ||
594 | { | ||
595 | struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; | ||
596 | |||
597 | INIT_LIST_HEAD(&master->queue); | ||
598 | spin_lock_init(&master->queue_lock); | ||
599 | |||
600 | master->running = false; | ||
601 | master->busy = false; | ||
602 | |||
603 | init_kthread_worker(&master->kworker); | ||
604 | master->kworker_task = kthread_run(kthread_worker_fn, | ||
605 | &master->kworker, | ||
606 | dev_name(&master->dev)); | ||
607 | if (IS_ERR(master->kworker_task)) { | ||
608 | dev_err(&master->dev, "failed to create message pump task\n"); | ||
609 | return -ENOMEM; | ||
610 | } | ||
611 | init_kthread_work(&master->pump_messages, spi_pump_messages); | ||
612 | |||
613 | /* | ||
614 | * Master config will indicate if this controller should run the | ||
615 | * message pump with high (realtime) priority to reduce the transfer | ||
616 | * latency on the bus by minimising the delay between a transfer | ||
617 | * request and the scheduling of the message pump thread. Without this | ||
618 | * setting the message pump thread will remain at default priority. | ||
619 | */ | ||
620 | if (master->rt) { | ||
621 | dev_info(&master->dev, | ||
622 | "will run message pump with realtime priority\n"); | ||
623 | sched_setscheduler(master->kworker_task, SCHED_FIFO, ¶m); | ||
624 | } | ||
625 | |||
626 | return 0; | ||
627 | } | ||
628 | |||
629 | /** | ||
630 | * spi_get_next_queued_message() - called by driver to check for queued | ||
631 | * messages | ||
632 | * @master: the master to check for queued messages | ||
633 | * | ||
634 | * If there are more messages in the queue, the next message is returned from | ||
635 | * this call. | ||
636 | */ | ||
637 | struct spi_message *spi_get_next_queued_message(struct spi_master *master) | ||
638 | { | ||
639 | struct spi_message *next; | ||
640 | unsigned long flags; | ||
641 | |||
642 | /* get a pointer to the next message, if any */ | ||
643 | spin_lock_irqsave(&master->queue_lock, flags); | ||
644 | if (list_empty(&master->queue)) | ||
645 | next = NULL; | ||
646 | else | ||
647 | next = list_entry(master->queue.next, | ||
648 | struct spi_message, queue); | ||
649 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
650 | |||
651 | return next; | ||
652 | } | ||
653 | EXPORT_SYMBOL_GPL(spi_get_next_queued_message); | ||
654 | |||
655 | /** | ||
656 | * spi_finalize_current_message() - the current message is complete | ||
657 | * @master: the master to return the message to | ||
658 | * | ||
659 | * Called by the driver to notify the core that the message in the front of the | ||
660 | * queue is complete and can be removed from the queue. | ||
661 | */ | ||
662 | void spi_finalize_current_message(struct spi_master *master) | ||
663 | { | ||
664 | struct spi_message *mesg; | ||
665 | unsigned long flags; | ||
666 | |||
667 | spin_lock_irqsave(&master->queue_lock, flags); | ||
668 | mesg = master->cur_msg; | ||
669 | master->cur_msg = NULL; | ||
670 | |||
671 | queue_kthread_work(&master->kworker, &master->pump_messages); | ||
672 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
673 | |||
674 | mesg->state = NULL; | ||
675 | if (mesg->complete) | ||
676 | mesg->complete(mesg->context); | ||
677 | } | ||
678 | EXPORT_SYMBOL_GPL(spi_finalize_current_message); | ||
679 | |||
680 | static int spi_start_queue(struct spi_master *master) | ||
681 | { | ||
682 | unsigned long flags; | ||
683 | |||
684 | spin_lock_irqsave(&master->queue_lock, flags); | ||
685 | |||
686 | if (master->running || master->busy) { | ||
687 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
688 | return -EBUSY; | ||
689 | } | ||
690 | |||
691 | master->running = true; | ||
692 | master->cur_msg = NULL; | ||
693 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
694 | |||
695 | queue_kthread_work(&master->kworker, &master->pump_messages); | ||
696 | |||
697 | return 0; | ||
698 | } | ||
699 | |||
700 | static int spi_stop_queue(struct spi_master *master) | ||
701 | { | ||
702 | unsigned long flags; | ||
703 | unsigned limit = 500; | ||
704 | int ret = 0; | ||
705 | |||
706 | spin_lock_irqsave(&master->queue_lock, flags); | ||
707 | |||
708 | /* | ||
709 | * This is a bit lame, but is optimized for the common execution path. | ||
710 | * A wait_queue on the master->busy could be used, but then the common | ||
711 | * execution path (pump_messages) would be required to call wake_up or | ||
712 | * friends on every SPI message. Do this instead. | ||
713 | */ | ||
714 | while ((!list_empty(&master->queue) || master->busy) && limit--) { | ||
715 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
716 | msleep(10); | ||
717 | spin_lock_irqsave(&master->queue_lock, flags); | ||
718 | } | ||
719 | |||
720 | if (!list_empty(&master->queue) || master->busy) | ||
721 | ret = -EBUSY; | ||
722 | else | ||
723 | master->running = false; | ||
724 | |||
725 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
726 | |||
727 | if (ret) { | ||
728 | dev_warn(&master->dev, | ||
729 | "could not stop message queue\n"); | ||
730 | return ret; | ||
731 | } | ||
732 | return ret; | ||
733 | } | ||
734 | |||
735 | static int spi_destroy_queue(struct spi_master *master) | ||
736 | { | ||
737 | int ret; | ||
738 | |||
739 | ret = spi_stop_queue(master); | ||
740 | |||
741 | /* | ||
742 | * flush_kthread_worker will block until all work is done. | ||
743 | * If the reason that stop_queue timed out is that the work will never | ||
744 | * finish, then it does no good to call flush/stop thread, so | ||
745 | * return anyway. | ||
746 | */ | ||
747 | if (ret) { | ||
748 | dev_err(&master->dev, "problem destroying queue\n"); | ||
749 | return ret; | ||
750 | } | ||
751 | |||
752 | flush_kthread_worker(&master->kworker); | ||
753 | kthread_stop(master->kworker_task); | ||
754 | |||
755 | return 0; | ||
756 | } | ||
757 | |||
758 | /** | ||
759 | * spi_queued_transfer - transfer function for queued transfers | ||
760 | * @spi: spi device which is requesting transfer | ||
761 | * @msg: spi message which is to handled is queued to driver queue | ||
762 | */ | ||
763 | static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg) | ||
764 | { | ||
765 | struct spi_master *master = spi->master; | ||
766 | unsigned long flags; | ||
767 | |||
768 | spin_lock_irqsave(&master->queue_lock, flags); | ||
769 | |||
770 | if (!master->running) { | ||
771 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
772 | return -ESHUTDOWN; | ||
773 | } | ||
774 | msg->actual_length = 0; | ||
775 | msg->status = -EINPROGRESS; | ||
776 | |||
777 | list_add_tail(&msg->queue, &master->queue); | ||
778 | if (master->running && !master->busy) | ||
779 | queue_kthread_work(&master->kworker, &master->pump_messages); | ||
780 | |||
781 | spin_unlock_irqrestore(&master->queue_lock, flags); | ||
782 | return 0; | ||
783 | } | ||
784 | |||
785 | static int spi_master_initialize_queue(struct spi_master *master) | ||
786 | { | ||
787 | int ret; | ||
788 | |||
789 | master->queued = true; | ||
790 | master->transfer = spi_queued_transfer; | ||
791 | |||
792 | /* Initialize and start queue */ | ||
793 | ret = spi_init_queue(master); | ||
794 | if (ret) { | ||
795 | dev_err(&master->dev, "problem initializing queue\n"); | ||
796 | goto err_init_queue; | ||
797 | } | ||
798 | ret = spi_start_queue(master); | ||
799 | if (ret) { | ||
800 | dev_err(&master->dev, "problem starting queue\n"); | ||
801 | goto err_start_queue; | ||
802 | } | ||
803 | |||
804 | return 0; | ||
805 | |||
806 | err_start_queue: | ||
807 | err_init_queue: | ||
808 | spi_destroy_queue(master); | ||
809 | return ret; | ||
810 | } | ||
811 | |||
812 | /*-------------------------------------------------------------------------*/ | ||
813 | |||
814 | #if defined(CONFIG_OF) | ||
815 | /** | ||
816 | * of_register_spi_devices() - Register child devices onto the SPI bus | ||
817 | * @master: Pointer to spi_master device | ||
818 | * | ||
819 | * Registers an spi_device for each child node of master node which has a 'reg' | ||
820 | * property. | ||
821 | */ | ||
822 | static void of_register_spi_devices(struct spi_master *master) | ||
823 | { | ||
824 | struct spi_device *spi; | ||
825 | struct device_node *nc; | ||
826 | const __be32 *prop; | ||
827 | char modalias[SPI_NAME_SIZE + 4]; | ||
828 | int rc; | ||
829 | int len; | ||
830 | |||
831 | if (!master->dev.of_node) | ||
832 | return; | ||
833 | |||
834 | for_each_available_child_of_node(master->dev.of_node, nc) { | ||
835 | /* Alloc an spi_device */ | ||
836 | spi = spi_alloc_device(master); | ||
837 | if (!spi) { | ||
838 | dev_err(&master->dev, "spi_device alloc error for %s\n", | ||
839 | nc->full_name); | ||
840 | spi_dev_put(spi); | ||
841 | continue; | ||
842 | } | ||
843 | |||
844 | /* Select device driver */ | ||
845 | if (of_modalias_node(nc, spi->modalias, | ||
846 | sizeof(spi->modalias)) < 0) { | ||
847 | dev_err(&master->dev, "cannot find modalias for %s\n", | ||
848 | nc->full_name); | ||
849 | spi_dev_put(spi); | ||
850 | continue; | ||
851 | } | ||
852 | |||
853 | /* Device address */ | ||
854 | prop = of_get_property(nc, "reg", &len); | ||
855 | if (!prop || len < sizeof(*prop)) { | ||
856 | dev_err(&master->dev, "%s has no 'reg' property\n", | ||
857 | nc->full_name); | ||
858 | spi_dev_put(spi); | ||
859 | continue; | ||
860 | } | ||
861 | spi->chip_select = be32_to_cpup(prop); | ||
862 | |||
863 | /* Mode (clock phase/polarity/etc.) */ | ||
864 | if (of_find_property(nc, "spi-cpha", NULL)) | ||
865 | spi->mode |= SPI_CPHA; | ||
866 | if (of_find_property(nc, "spi-cpol", NULL)) | ||
867 | spi->mode |= SPI_CPOL; | ||
868 | if (of_find_property(nc, "spi-cs-high", NULL)) | ||
869 | spi->mode |= SPI_CS_HIGH; | ||
870 | if (of_find_property(nc, "spi-3wire", NULL)) | ||
871 | spi->mode |= SPI_3WIRE; | ||
872 | |||
873 | /* Device speed */ | ||
874 | prop = of_get_property(nc, "spi-max-frequency", &len); | ||
875 | if (!prop || len < sizeof(*prop)) { | ||
876 | dev_err(&master->dev, "%s has no 'spi-max-frequency' property\n", | ||
877 | nc->full_name); | ||
878 | spi_dev_put(spi); | ||
879 | continue; | ||
880 | } | ||
881 | spi->max_speed_hz = be32_to_cpup(prop); | ||
882 | |||
883 | /* IRQ */ | ||
884 | spi->irq = irq_of_parse_and_map(nc, 0); | ||
885 | |||
886 | /* Store a pointer to the node in the device structure */ | ||
887 | of_node_get(nc); | ||
888 | spi->dev.of_node = nc; | ||
889 | |||
890 | /* Register the new device */ | ||
891 | snprintf(modalias, sizeof(modalias), "%s%s", SPI_MODULE_PREFIX, | ||
892 | spi->modalias); | ||
893 | request_module(modalias); | ||
894 | rc = spi_add_device(spi); | ||
895 | if (rc) { | ||
896 | dev_err(&master->dev, "spi_device register error %s\n", | ||
897 | nc->full_name); | ||
898 | spi_dev_put(spi); | ||
899 | } | ||
900 | |||
901 | } | ||
902 | } | ||
903 | #else | ||
904 | static void of_register_spi_devices(struct spi_master *master) { } | ||
905 | #endif | ||
906 | |||
907 | #ifdef CONFIG_ACPI | ||
908 | static int acpi_spi_add_resource(struct acpi_resource *ares, void *data) | ||
909 | { | ||
910 | struct spi_device *spi = data; | ||
911 | |||
912 | if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) { | ||
913 | struct acpi_resource_spi_serialbus *sb; | ||
914 | |||
915 | sb = &ares->data.spi_serial_bus; | ||
916 | if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_SPI) { | ||
917 | spi->chip_select = sb->device_selection; | ||
918 | spi->max_speed_hz = sb->connection_speed; | ||
919 | |||
920 | if (sb->clock_phase == ACPI_SPI_SECOND_PHASE) | ||
921 | spi->mode |= SPI_CPHA; | ||
922 | if (sb->clock_polarity == ACPI_SPI_START_HIGH) | ||
923 | spi->mode |= SPI_CPOL; | ||
924 | if (sb->device_polarity == ACPI_SPI_ACTIVE_HIGH) | ||
925 | spi->mode |= SPI_CS_HIGH; | ||
926 | } | ||
927 | } else if (spi->irq < 0) { | ||
928 | struct resource r; | ||
929 | |||
930 | if (acpi_dev_resource_interrupt(ares, 0, &r)) | ||
931 | spi->irq = r.start; | ||
932 | } | ||
933 | |||
934 | /* Always tell the ACPI core to skip this resource */ | ||
935 | return 1; | ||
936 | } | ||
937 | |||
938 | static acpi_status acpi_spi_add_device(acpi_handle handle, u32 level, | ||
939 | void *data, void **return_value) | ||
940 | { | ||
941 | struct spi_master *master = data; | ||
942 | struct list_head resource_list; | ||
943 | struct acpi_device *adev; | ||
944 | struct spi_device *spi; | ||
945 | int ret; | ||
946 | |||
947 | if (acpi_bus_get_device(handle, &adev)) | ||
948 | return AE_OK; | ||
949 | if (acpi_bus_get_status(adev) || !adev->status.present) | ||
950 | return AE_OK; | ||
951 | |||
952 | spi = spi_alloc_device(master); | ||
953 | if (!spi) { | ||
954 | dev_err(&master->dev, "failed to allocate SPI device for %s\n", | ||
955 | dev_name(&adev->dev)); | ||
956 | return AE_NO_MEMORY; | ||
957 | } | ||
958 | |||
959 | ACPI_HANDLE_SET(&spi->dev, handle); | ||
960 | spi->irq = -1; | ||
961 | |||
962 | INIT_LIST_HEAD(&resource_list); | ||
963 | ret = acpi_dev_get_resources(adev, &resource_list, | ||
964 | acpi_spi_add_resource, spi); | ||
965 | acpi_dev_free_resource_list(&resource_list); | ||
966 | |||
967 | if (ret < 0 || !spi->max_speed_hz) { | ||
968 | spi_dev_put(spi); | ||
969 | return AE_OK; | ||
970 | } | ||
971 | |||
972 | strlcpy(spi->modalias, dev_name(&adev->dev), sizeof(spi->modalias)); | ||
973 | if (spi_add_device(spi)) { | ||
974 | dev_err(&master->dev, "failed to add SPI device %s from ACPI\n", | ||
975 | dev_name(&adev->dev)); | ||
976 | spi_dev_put(spi); | ||
977 | } | ||
978 | |||
979 | return AE_OK; | ||
980 | } | ||
981 | |||
982 | static void acpi_register_spi_devices(struct spi_master *master) | ||
983 | { | ||
984 | acpi_status status; | ||
985 | acpi_handle handle; | ||
986 | |||
987 | handle = ACPI_HANDLE(&master->dev); | ||
988 | if (!handle) | ||
989 | return; | ||
990 | |||
991 | status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, | ||
992 | acpi_spi_add_device, NULL, | ||
993 | master, NULL); | ||
994 | if (ACPI_FAILURE(status)) | ||
995 | dev_warn(&master->dev, "failed to enumerate SPI slaves\n"); | ||
996 | } | ||
997 | #else | ||
998 | static inline void acpi_register_spi_devices(struct spi_master *master) {} | ||
999 | #endif /* CONFIG_ACPI */ | ||
1000 | |||
1001 | static void spi_master_release(struct device *dev) | 509 | static void spi_master_release(struct device *dev) |
1002 | { | 510 | { |
1003 | struct spi_master *master; | 511 | struct spi_master *master; |
@@ -1013,7 +521,6 @@ static struct class spi_master_class = { | |||
1013 | }; | 521 | }; |
1014 | 522 | ||
1015 | 523 | ||
1016 | |||
1017 | /** | 524 | /** |
1018 | * spi_alloc_master - allocate SPI master controller | 525 | * spi_alloc_master - allocate SPI master controller |
1019 | * @dev: the controller, possibly using the platform_bus | 526 | * @dev: the controller, possibly using the platform_bus |
@@ -1031,8 +538,7 @@ static struct class spi_master_class = { | |||
1031 | * | 538 | * |
1032 | * The caller is responsible for assigning the bus number and initializing | 539 | * The caller is responsible for assigning the bus number and initializing |
1033 | * the master's methods before calling spi_register_master(); and (after errors | 540 | * the master's methods before calling spi_register_master(); and (after errors |
1034 | * adding the device) calling spi_master_put() and kfree() to prevent a memory | 541 | * adding the device) calling spi_master_put() to prevent a memory leak. |
1035 | * leak. | ||
1036 | */ | 542 | */ |
1037 | struct spi_master *spi_alloc_master(struct device *dev, unsigned size) | 543 | struct spi_master *spi_alloc_master(struct device *dev, unsigned size) |
1038 | { | 544 | { |
@@ -1046,8 +552,6 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size) | |||
1046 | return NULL; | 552 | return NULL; |
1047 | 553 | ||
1048 | device_initialize(&master->dev); | 554 | device_initialize(&master->dev); |
1049 | master->bus_num = -1; | ||
1050 | master->num_chipselect = 1; | ||
1051 | master->dev.class = &spi_master_class; | 555 | master->dev.class = &spi_master_class; |
1052 | master->dev.parent = get_device(dev); | 556 | master->dev.parent = get_device(dev); |
1053 | spi_master_set_devdata(master, &master[1]); | 557 | spi_master_set_devdata(master, &master[1]); |
@@ -1056,44 +560,6 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size) | |||
1056 | } | 560 | } |
1057 | EXPORT_SYMBOL_GPL(spi_alloc_master); | 561 | EXPORT_SYMBOL_GPL(spi_alloc_master); |
1058 | 562 | ||
1059 | #ifdef CONFIG_OF | ||
1060 | static int of_spi_register_master(struct spi_master *master) | ||
1061 | { | ||
1062 | u16 nb; | ||
1063 | int i, *cs; | ||
1064 | struct device_node *np = master->dev.of_node; | ||
1065 | |||
1066 | if (!np) | ||
1067 | return 0; | ||
1068 | |||
1069 | nb = of_gpio_named_count(np, "cs-gpios"); | ||
1070 | master->num_chipselect = max(nb, master->num_chipselect); | ||
1071 | |||
1072 | if (nb < 1) | ||
1073 | return 0; | ||
1074 | |||
1075 | cs = devm_kzalloc(&master->dev, | ||
1076 | sizeof(int) * master->num_chipselect, | ||
1077 | GFP_KERNEL); | ||
1078 | master->cs_gpios = cs; | ||
1079 | |||
1080 | if (!master->cs_gpios) | ||
1081 | return -ENOMEM; | ||
1082 | |||
1083 | memset(cs, -EINVAL, master->num_chipselect); | ||
1084 | |||
1085 | for (i = 0; i < nb; i++) | ||
1086 | cs[i] = of_get_named_gpio(np, "cs-gpios", i); | ||
1087 | |||
1088 | return 0; | ||
1089 | } | ||
1090 | #else | ||
1091 | static int of_spi_register_master(struct spi_master *master) | ||
1092 | { | ||
1093 | return 0; | ||
1094 | } | ||
1095 | #endif | ||
1096 | |||
1097 | /** | 563 | /** |
1098 | * spi_register_master - register SPI master controller | 564 | * spi_register_master - register SPI master controller |
1099 | * @master: initialized master, originally from spi_alloc_master() | 565 | * @master: initialized master, originally from spi_alloc_master() |
@@ -1125,10 +591,6 @@ int spi_register_master(struct spi_master *master) | |||
1125 | if (!dev) | 591 | if (!dev) |
1126 | return -ENODEV; | 592 | return -ENODEV; |
1127 | 593 | ||
1128 | status = of_spi_register_master(master); | ||
1129 | if (status) | ||
1130 | return status; | ||
1131 | |||
1132 | /* even if it's just one always-selected device, there must | 594 | /* even if it's just one always-selected device, there must |
1133 | * be at least one chipselect | 595 | * be at least one chipselect |
1134 | */ | 596 | */ |
@@ -1158,31 +620,22 @@ int spi_register_master(struct spi_master *master) | |||
1158 | dev_dbg(dev, "registered master %s%s\n", dev_name(&master->dev), | 620 | dev_dbg(dev, "registered master %s%s\n", dev_name(&master->dev), |
1159 | dynamic ? " (dynamic)" : ""); | 621 | dynamic ? " (dynamic)" : ""); |
1160 | 622 | ||
1161 | /* If we're using a queued driver, start the queue */ | ||
1162 | if (master->transfer) | ||
1163 | dev_info(dev, "master is unqueued, this is deprecated\n"); | ||
1164 | else { | ||
1165 | status = spi_master_initialize_queue(master); | ||
1166 | if (status) { | ||
1167 | device_unregister(&master->dev); | ||
1168 | goto done; | ||
1169 | } | ||
1170 | } | ||
1171 | |||
1172 | mutex_lock(&board_lock); | 623 | mutex_lock(&board_lock); |
1173 | list_add_tail(&master->list, &spi_master_list); | 624 | list_add_tail(&master->list, &spi_master_list); |
1174 | list_for_each_entry(bi, &board_list, list) | 625 | list_for_each_entry(bi, &board_list, list) |
1175 | spi_match_master_to_boardinfo(master, &bi->board_info); | 626 | spi_match_master_to_boardinfo(master, &bi->board_info); |
1176 | mutex_unlock(&board_lock); | 627 | mutex_unlock(&board_lock); |
1177 | 628 | ||
1178 | /* Register devices from the device tree and ACPI */ | 629 | status = 0; |
630 | |||
631 | /* Register devices from the device tree */ | ||
1179 | of_register_spi_devices(master); | 632 | of_register_spi_devices(master); |
1180 | acpi_register_spi_devices(master); | ||
1181 | done: | 633 | done: |
1182 | return status; | 634 | return status; |
1183 | } | 635 | } |
1184 | EXPORT_SYMBOL_GPL(spi_register_master); | 636 | EXPORT_SYMBOL_GPL(spi_register_master); |
1185 | 637 | ||
638 | |||
1186 | static int __unregister(struct device *dev, void *null) | 639 | static int __unregister(struct device *dev, void *null) |
1187 | { | 640 | { |
1188 | spi_unregister_device(to_spi_device(dev)); | 641 | spi_unregister_device(to_spi_device(dev)); |
@@ -1203,11 +656,6 @@ void spi_unregister_master(struct spi_master *master) | |||
1203 | { | 656 | { |
1204 | int dummy; | 657 | int dummy; |
1205 | 658 | ||
1206 | if (master->queued) { | ||
1207 | if (spi_destroy_queue(master)) | ||
1208 | dev_err(&master->dev, "queue remove failed\n"); | ||
1209 | } | ||
1210 | |||
1211 | mutex_lock(&board_lock); | 659 | mutex_lock(&board_lock); |
1212 | list_del(&master->list); | 660 | list_del(&master->list); |
1213 | mutex_unlock(&board_lock); | 661 | mutex_unlock(&board_lock); |
@@ -1217,37 +665,6 @@ void spi_unregister_master(struct spi_master *master) | |||
1217 | } | 665 | } |
1218 | EXPORT_SYMBOL_GPL(spi_unregister_master); | 666 | EXPORT_SYMBOL_GPL(spi_unregister_master); |
1219 | 667 | ||
1220 | int spi_master_suspend(struct spi_master *master) | ||
1221 | { | ||
1222 | int ret; | ||
1223 | |||
1224 | /* Basically no-ops for non-queued masters */ | ||
1225 | if (!master->queued) | ||
1226 | return 0; | ||
1227 | |||
1228 | ret = spi_stop_queue(master); | ||
1229 | if (ret) | ||
1230 | dev_err(&master->dev, "queue stop failed\n"); | ||
1231 | |||
1232 | return ret; | ||
1233 | } | ||
1234 | EXPORT_SYMBOL_GPL(spi_master_suspend); | ||
1235 | |||
1236 | int spi_master_resume(struct spi_master *master) | ||
1237 | { | ||
1238 | int ret; | ||
1239 | |||
1240 | if (!master->queued) | ||
1241 | return 0; | ||
1242 | |||
1243 | ret = spi_start_queue(master); | ||
1244 | if (ret) | ||
1245 | dev_err(&master->dev, "queue restart failed\n"); | ||
1246 | |||
1247 | return ret; | ||
1248 | } | ||
1249 | EXPORT_SYMBOL_GPL(spi_master_resume); | ||
1250 | |||
1251 | static int __spi_master_match(struct device *dev, void *data) | 668 | static int __spi_master_match(struct device *dev, void *data) |
1252 | { | 669 | { |
1253 | struct spi_master *m; | 670 | struct spi_master *m; |
@@ -1309,7 +726,7 @@ EXPORT_SYMBOL_GPL(spi_busnum_to_master); | |||
1309 | int spi_setup(struct spi_device *spi) | 726 | int spi_setup(struct spi_device *spi) |
1310 | { | 727 | { |
1311 | unsigned bad_bits; | 728 | unsigned bad_bits; |
1312 | int status = 0; | 729 | int status; |
1313 | 730 | ||
1314 | /* help drivers fail *cleanly* when they need options | 731 | /* help drivers fail *cleanly* when they need options |
1315 | * that aren't supported with their current master | 732 | * that aren't supported with their current master |
@@ -1324,8 +741,7 @@ int spi_setup(struct spi_device *spi) | |||
1324 | if (!spi->bits_per_word) | 741 | if (!spi->bits_per_word) |
1325 | spi->bits_per_word = 8; | 742 | spi->bits_per_word = 8; |
1326 | 743 | ||
1327 | if (spi->master->setup) | 744 | status = spi->master->setup(spi); |
1328 | status = spi->master->setup(spi); | ||
1329 | 745 | ||
1330 | dev_dbg(&spi->dev, "setup mode %d, %s%s%s%s" | 746 | dev_dbg(&spi->dev, "setup mode %d, %s%s%s%s" |
1331 | "%u bits/w, %u Hz max --> %d\n", | 747 | "%u bits/w, %u Hz max --> %d\n", |
@@ -1344,7 +760,6 @@ EXPORT_SYMBOL_GPL(spi_setup); | |||
1344 | static int __spi_async(struct spi_device *spi, struct spi_message *message) | 760 | static int __spi_async(struct spi_device *spi, struct spi_message *message) |
1345 | { | 761 | { |
1346 | struct spi_master *master = spi->master; | 762 | struct spi_master *master = spi->master; |
1347 | struct spi_transfer *xfer; | ||
1348 | 763 | ||
1349 | /* Half-duplex links include original MicroWire, and ones with | 764 | /* Half-duplex links include original MicroWire, and ones with |
1350 | * only one data pin like SPI_3WIRE (switches direction) or where | 765 | * only one data pin like SPI_3WIRE (switches direction) or where |
@@ -1353,6 +768,7 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message) | |||
1353 | */ | 768 | */ |
1354 | if ((master->flags & SPI_MASTER_HALF_DUPLEX) | 769 | if ((master->flags & SPI_MASTER_HALF_DUPLEX) |
1355 | || (spi->mode & SPI_3WIRE)) { | 770 | || (spi->mode & SPI_3WIRE)) { |
771 | struct spi_transfer *xfer; | ||
1356 | unsigned flags = master->flags; | 772 | unsigned flags = master->flags; |
1357 | 773 | ||
1358 | list_for_each_entry(xfer, &message->transfers, transfer_list) { | 774 | list_for_each_entry(xfer, &message->transfers, transfer_list) { |
@@ -1365,15 +781,6 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message) | |||
1365 | } | 781 | } |
1366 | } | 782 | } |
1367 | 783 | ||
1368 | /** | ||
1369 | * Set transfer bits_per_word as spi device default if it is not | ||
1370 | * set for this transfer. | ||
1371 | */ | ||
1372 | list_for_each_entry(xfer, &message->transfers, transfer_list) { | ||
1373 | if (!xfer->bits_per_word) | ||
1374 | xfer->bits_per_word = spi->bits_per_word; | ||
1375 | } | ||
1376 | |||
1377 | message->spi = spi; | 784 | message->spi = spi; |
1378 | message->status = -EINPROGRESS; | 785 | message->status = -EINPROGRESS; |
1379 | return master->transfer(spi, message); | 786 | return master->transfer(spi, message); |
@@ -1650,18 +1057,12 @@ int spi_write_then_read(struct spi_device *spi, | |||
1650 | struct spi_transfer x[2]; | 1057 | struct spi_transfer x[2]; |
1651 | u8 *local_buf; | 1058 | u8 *local_buf; |
1652 | 1059 | ||
1653 | /* Use preallocated DMA-safe buffer if we can. We can't avoid | 1060 | /* Use preallocated DMA-safe buffer. We can't avoid copying here, |
1654 | * copying here, (as a pure convenience thing), but we can | 1061 | * (as a pure convenience thing), but we can keep heap costs |
1655 | * keep heap costs out of the hot path unless someone else is | 1062 | * out of the hot path ... |
1656 | * using the pre-allocated buffer or the transfer is too large. | ||
1657 | */ | 1063 | */ |
1658 | if ((n_tx + n_rx) > SPI_BUFSIZ || !mutex_trylock(&lock)) { | 1064 | if ((n_tx + n_rx) > SPI_BUFSIZ) |
1659 | local_buf = kmalloc(max((unsigned)SPI_BUFSIZ, n_tx + n_rx), GFP_KERNEL); | 1065 | return -EINVAL; |
1660 | if (!local_buf) | ||
1661 | return -ENOMEM; | ||
1662 | } else { | ||
1663 | local_buf = buf; | ||
1664 | } | ||
1665 | 1066 | ||
1666 | spi_message_init(&message); | 1067 | spi_message_init(&message); |
1667 | memset(x, 0, sizeof x); | 1068 | memset(x, 0, sizeof x); |
@@ -1674,6 +1075,14 @@ int spi_write_then_read(struct spi_device *spi, | |||
1674 | spi_message_add_tail(&x[1], &message); | 1075 | spi_message_add_tail(&x[1], &message); |
1675 | } | 1076 | } |
1676 | 1077 | ||
1078 | /* ... unless someone else is using the pre-allocated buffer */ | ||
1079 | if (!mutex_trylock(&lock)) { | ||
1080 | local_buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL); | ||
1081 | if (!local_buf) | ||
1082 | return -ENOMEM; | ||
1083 | } else | ||
1084 | local_buf = buf; | ||
1085 | |||
1677 | memcpy(local_buf, txbuf, n_tx); | 1086 | memcpy(local_buf, txbuf, n_tx); |
1678 | x[0].tx_buf = local_buf; | 1087 | x[0].tx_buf = local_buf; |
1679 | x[1].rx_buf = local_buf + n_tx; | 1088 | x[1].rx_buf = local_buf + n_tx; |
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 2e0655dbe07..830adbed1d7 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c | |||
@@ -31,8 +31,6 @@ | |||
31 | #include <linux/mutex.h> | 31 | #include <linux/mutex.h> |
32 | #include <linux/slab.h> | 32 | #include <linux/slab.h> |
33 | #include <linux/compat.h> | 33 | #include <linux/compat.h> |
34 | #include <linux/of.h> | ||
35 | #include <linux/of_device.h> | ||
36 | 34 | ||
37 | #include <linux/spi/spi.h> | 35 | #include <linux/spi/spi.h> |
38 | #include <linux/spi/spidev.h> | 36 | #include <linux/spi/spidev.h> |
@@ -573,7 +571,7 @@ static struct class *spidev_class; | |||
573 | 571 | ||
574 | /*-------------------------------------------------------------------------*/ | 572 | /*-------------------------------------------------------------------------*/ |
575 | 573 | ||
576 | static int spidev_probe(struct spi_device *spi) | 574 | static int __devinit spidev_probe(struct spi_device *spi) |
577 | { | 575 | { |
578 | struct spidev_data *spidev; | 576 | struct spidev_data *spidev; |
579 | int status; | 577 | int status; |
@@ -622,7 +620,7 @@ static int spidev_probe(struct spi_device *spi) | |||
622 | return status; | 620 | return status; |
623 | } | 621 | } |
624 | 622 | ||
625 | static int spidev_remove(struct spi_device *spi) | 623 | static int __devexit spidev_remove(struct spi_device *spi) |
626 | { | 624 | { |
627 | struct spidev_data *spidev = spi_get_drvdata(spi); | 625 | struct spidev_data *spidev = spi_get_drvdata(spi); |
628 | 626 | ||
@@ -644,21 +642,13 @@ static int spidev_remove(struct spi_device *spi) | |||
644 | return 0; | 642 | return 0; |
645 | } | 643 | } |
646 | 644 | ||
647 | static const struct of_device_id spidev_dt_ids[] = { | ||
648 | { .compatible = "rohm,dh2228fv" }, | ||
649 | {}, | ||
650 | }; | ||
651 | |||
652 | MODULE_DEVICE_TABLE(of, spidev_dt_ids); | ||
653 | |||
654 | static struct spi_driver spidev_spi_driver = { | 645 | static struct spi_driver spidev_spi_driver = { |
655 | .driver = { | 646 | .driver = { |
656 | .name = "spidev", | 647 | .name = "spidev", |
657 | .owner = THIS_MODULE, | 648 | .owner = THIS_MODULE, |
658 | .of_match_table = of_match_ptr(spidev_dt_ids), | ||
659 | }, | 649 | }, |
660 | .probe = spidev_probe, | 650 | .probe = spidev_probe, |
661 | .remove = spidev_remove, | 651 | .remove = __devexit_p(spidev_remove), |
662 | 652 | ||
663 | /* NOTE: suspend/resume methods are not necessary here. | 653 | /* NOTE: suspend/resume methods are not necessary here. |
664 | * We don't do anything except pass the requests to/from | 654 | * We don't do anything except pass the requests to/from |