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authorJohn W. Linville <linville@tuxdriver.com>2010-11-24 16:49:20 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-11-24 16:49:20 -0500
commit51cce8a590c4696d62bfacc63378d1036084cef7 (patch)
treedc24485bdff37ca6a83c69e93ffdbe5c5807b59d /drivers/net/wireless/ath/ath9k
parent2fe66ec242d3f76e3b0101f36419e7e5405bcff3 (diff)
parent4f8559383c41262b50dc758e2e310f257ce6a14d (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Diffstat (limited to 'drivers/net/wireless/ath/ath9k')
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c79
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c27
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c2634
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h27
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c28
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c51
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h42
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c20
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c17
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c61
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c38
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_hst.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_hst.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c20
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h41
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c30
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c42
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c29
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.h6
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h14
-rw-r--r--drivers/net/wireless/ath/ath9k/virtual.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c631
32 files changed, 3283 insertions, 640 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 63ccb39cdcd..29a045da184 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -834,10 +834,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
834{ 834{
835 int i; 835 int i;
836 836
837 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 837 static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
838 const int coarseHigh[] = { -14, -14, -14, -14, -12 }; 838 static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
839 const int coarseLow[] = { -64, -64, -64, -64, -70 }; 839 static const int coarseLow[] = { -64, -64, -64, -64, -70 };
840 const int firpwr[] = { -78, -78, -78, -78, -80 }; 840 static const int firpwr[] = { -78, -78, -78, -78, -80 };
841 841
842 for (i = 0; i < 5; i++) { 842 for (i = 0; i < 5; i++) {
843 ah->totalSizeDesired[i] = totalSizeDesired[i]; 843 ah->totalSizeDesired[i] = totalSizeDesired[i];
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index c83a22cfbe1..06e34d293dc 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -244,13 +244,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
244 int upper, lower, cur_vit_mask; 244 int upper, lower, cur_vit_mask;
245 int tmp, new; 245 int tmp, new;
246 int i; 246 int i;
247 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 247 static int pilot_mask_reg[4] = {
248 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 248 AR_PHY_TIMING7, AR_PHY_TIMING8,
249 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
249 }; 250 };
250 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 251 static int chan_mask_reg[4] = {
251 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 252 AR_PHY_TIMING9, AR_PHY_TIMING10,
253 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
252 }; 254 };
253 int inc[4] = { 0, 100, 0, 0 }; 255 static int inc[4] = { 0, 100, 0, 0 };
254 256
255 int8_t mask_m[123]; 257 int8_t mask_m[123];
256 int8_t mask_p[123]; 258 int8_t mask_p[123];
@@ -1084,12 +1086,12 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1084 break; 1086 break;
1085 } 1087 }
1086 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1088 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1087 const int m1ThreshLow[] = { 127, 50 }; 1089 static const int m1ThreshLow[] = { 127, 50 };
1088 const int m2ThreshLow[] = { 127, 40 }; 1090 static const int m2ThreshLow[] = { 127, 40 };
1089 const int m1Thresh[] = { 127, 0x4d }; 1091 static const int m1Thresh[] = { 127, 0x4d };
1090 const int m2Thresh[] = { 127, 0x40 }; 1092 static const int m2Thresh[] = { 127, 0x40 };
1091 const int m2CountThr[] = { 31, 16 }; 1093 static const int m2CountThr[] = { 31, 16 };
1092 const int m2CountThrLow[] = { 63, 48 }; 1094 static const int m2CountThrLow[] = { 63, 48 };
1093 u32 on = param ? 1 : 0; 1095 u32 on = param ? 1 : 0;
1094 1096
1095 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1097 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
@@ -1141,7 +1143,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1141 break; 1143 break;
1142 } 1144 }
1143 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{ 1145 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1144 const int weakSigThrCck[] = { 8, 6 }; 1146 static const int weakSigThrCck[] = { 8, 6 };
1145 u32 high = param ? 1 : 0; 1147 u32 high = param ? 1 : 0;
1146 1148
1147 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, 1149 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
@@ -1157,7 +1159,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1157 break; 1159 break;
1158 } 1160 }
1159 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1161 case ATH9K_ANI_FIRSTEP_LEVEL:{
1160 const int firstep[] = { 0, 4, 8 }; 1162 static const int firstep[] = { 0, 4, 8 };
1161 u32 level = param; 1163 u32 level = param;
1162 1164
1163 if (level >= ARRAY_SIZE(firstep)) { 1165 if (level >= ARRAY_SIZE(firstep)) {
@@ -1178,7 +1180,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1178 break; 1180 break;
1179 } 1181 }
1180 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1182 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1181 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 1183 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1182 u32 level = param; 1184 u32 level = param;
1183 1185
1184 if (level >= ARRAY_SIZE(cycpwrThr1)) { 1186 if (level >= ARRAY_SIZE(cycpwrThr1)) {
@@ -1579,10 +1581,55 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1579 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1581 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1580} 1582}
1581 1583
1584static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1585 struct ath_hw_radar_conf *conf)
1586{
1587 u32 radar_0 = 0, radar_1 = 0;
1588
1589 if (!conf) {
1590 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1591 return;
1592 }
1593
1594 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1595 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1596 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1597 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1598 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1599 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1600
1601 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1602 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1603 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1604 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1605 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1606
1607 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1608 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1609 if (conf->ext_channel)
1610 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1611 else
1612 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1613}
1614
1615static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1616{
1617 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1618
1619 conf->fir_power = -33;
1620 conf->radar_rssi = 20;
1621 conf->pulse_height = 10;
1622 conf->pulse_rssi = 24;
1623 conf->pulse_inband = 15;
1624 conf->pulse_maxlen = 255;
1625 conf->pulse_inband_step = 12;
1626 conf->radar_inband = 8;
1627}
1628
1582void ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1629void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1583{ 1630{
1584 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1631 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1585 const u32 ar5416_cca_regs[6] = { 1632 static const u32 ar5416_cca_regs[6] = {
1586 AR_PHY_CCA, 1633 AR_PHY_CCA,
1587 AR_PHY_CH1_CCA, 1634 AR_PHY_CH1_CCA,
1588 AR_PHY_CH2_CCA, 1635 AR_PHY_CH2_CCA,
@@ -1609,6 +1656,7 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1609 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1656 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1610 priv_ops->set_diversity = ar5008_set_diversity; 1657 priv_ops->set_diversity = ar5008_set_diversity;
1611 priv_ops->do_getnf = ar5008_hw_do_getnf; 1658 priv_ops->do_getnf = ar5008_hw_do_getnf;
1659 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1612 1660
1613 if (modparam_force_new_ani) { 1661 if (modparam_force_new_ani) {
1614 priv_ops->ani_control = ar5008_hw_ani_control_new; 1662 priv_ops->ani_control = ar5008_hw_ani_control_new;
@@ -1624,5 +1672,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1624 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1672 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1625 1673
1626 ar5008_hw_set_nf_limits(ah); 1674 ar5008_hw_set_nf_limits(ah);
1675 ar5008_hw_set_radar_conf(ah);
1627 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1676 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1628} 1677}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index 3fb97fdc124..7ae66a889f5 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -175,13 +175,15 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
175 int upper, lower, cur_vit_mask; 175 int upper, lower, cur_vit_mask;
176 int tmp, newVal; 176 int tmp, newVal;
177 int i; 177 int i;
178 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 178 static const int pilot_mask_reg[4] = {
179 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 179 AR_PHY_TIMING7, AR_PHY_TIMING8,
180 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
180 }; 181 };
181 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 182 static const int chan_mask_reg[4] = {
182 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 183 AR_PHY_TIMING9, AR_PHY_TIMING10,
184 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
183 }; 185 };
184 int inc[4] = { 0, 100, 0, 0 }; 186 static const int inc[4] = { 0, 100, 0, 0 };
185 struct chan_centers centers; 187 struct chan_centers centers;
186 188
187 int8_t mask_m[123]; 189 int8_t mask_m[123];
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 9e6edffe0bd..4c94c9ed5f8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -196,7 +196,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
196 u32 qCoffDenom, iCoffDenom; 196 u32 qCoffDenom, iCoffDenom;
197 int32_t qCoff, iCoff; 197 int32_t qCoff, iCoff;
198 int iqCorrNeg, i; 198 int iqCorrNeg, i;
199 const u_int32_t offset_array[3] = { 199 static const u_int32_t offset_array[3] = {
200 AR_PHY_RX_IQCAL_CORR_B0, 200 AR_PHY_RX_IQCAL_CORR_B0,
201 AR_PHY_RX_IQCAL_CORR_B1, 201 AR_PHY_RX_IQCAL_CORR_B1,
202 AR_PHY_RX_IQCAL_CORR_B2, 202 AR_PHY_RX_IQCAL_CORR_B2,
@@ -603,22 +603,22 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
603static void ar9003_hw_tx_iq_cal(struct ath_hw *ah) 603static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
604{ 604{
605 struct ath_common *common = ath9k_hw_common(ah); 605 struct ath_common *common = ath9k_hw_common(ah);
606 const u32 txiqcal_status[AR9300_MAX_CHAINS] = { 606 static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
607 AR_PHY_TX_IQCAL_STATUS_B0, 607 AR_PHY_TX_IQCAL_STATUS_B0,
608 AR_PHY_TX_IQCAL_STATUS_B1, 608 AR_PHY_TX_IQCAL_STATUS_B1,
609 AR_PHY_TX_IQCAL_STATUS_B2, 609 AR_PHY_TX_IQCAL_STATUS_B2,
610 }; 610 };
611 const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = { 611 static const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
612 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, 612 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
613 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, 613 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
614 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2, 614 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
615 }; 615 };
616 const u32 rx_corr[AR9300_MAX_CHAINS] = { 616 static const u32 rx_corr[AR9300_MAX_CHAINS] = {
617 AR_PHY_RX_IQCAL_CORR_B0, 617 AR_PHY_RX_IQCAL_CORR_B0,
618 AR_PHY_RX_IQCAL_CORR_B1, 618 AR_PHY_RX_IQCAL_CORR_B1,
619 AR_PHY_RX_IQCAL_CORR_B2, 619 AR_PHY_RX_IQCAL_CORR_B2,
620 }; 620 };
621 const u_int32_t chan_info_tab[] = { 621 static const u_int32_t chan_info_tab[] = {
622 AR_PHY_CHAN_INFO_TAB_0, 622 AR_PHY_CHAN_INFO_TAB_0,
623 AR_PHY_CHAN_INFO_TAB_1, 623 AR_PHY_CHAN_INFO_TAB_1,
624 AR_PHY_CHAN_INFO_TAB_2, 624 AR_PHY_CHAN_INFO_TAB_2,
@@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
718 struct ath9k_channel *chan) 718 struct ath9k_channel *chan)
719{ 719{
720 struct ath_common *common = ath9k_hw_common(ah); 720 struct ath_common *common = ath9k_hw_common(ah);
721 int val;
721 722
722 /* 723 val = REG_READ(ah, AR_ENT_OTP);
723 * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before 724 ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
724 * running AGC/TxIQ cals 725
725 */ 726 if (val & AR_ENT_OTP_CHAIN2_DISABLE)
726 ar9003_hw_set_chain_masks(ah, 0x7, 0x7); 727 ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
728 else
729 /*
730 * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
731 * mode before running AGC/TxIQ cals
732 */
733 ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
727 734
728 /* Do Tx IQ Calibration */ 735 /* Do Tx IQ Calibration */
729 ar9003_hw_tx_iq_cal(ah); 736 ar9003_hw_tx_iq_cal(ah);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a88fe0d6142..3161a5901a7 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -22,12 +22,14 @@
22#define COMP_CKSUM_LEN 2 22#define COMP_CKSUM_LEN 2
23 23
24#define AR_CH0_TOP (0x00016288) 24#define AR_CH0_TOP (0x00016288)
25#define AR_CH0_TOP_XPABIASLVL (0x3) 25#define AR_CH0_TOP_XPABIASLVL (0x300)
26#define AR_CH0_TOP_XPABIASLVL_S (8) 26#define AR_CH0_TOP_XPABIASLVL_S (8)
27 27
28#define AR_CH0_THERM (0x00016290) 28#define AR_CH0_THERM (0x00016290)
29#define AR_CH0_THERM_SPARE (0x3f) 29#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30#define AR_CH0_THERM_SPARE_S (0) 30#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31#define AR_CH0_THERM_XPASHORT2GND 0x4
32#define AR_CH0_THERM_XPASHORT2GND_S 2
31 33
32#define AR_SWITCH_TABLE_COM_ALL (0xffff) 34#define AR_SWITCH_TABLE_COM_ALL (0xffff)
33#define AR_SWITCH_TABLE_COM_ALL_S (0) 35#define AR_SWITCH_TABLE_COM_ALL_S (0)
@@ -55,6 +57,8 @@
55#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 57#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
56#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 58#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
57 59
60static int ar9003_hw_power_interpolate(int32_t x,
61 int32_t *px, int32_t *py, u_int16_t np);
58static const struct ar9300_eeprom ar9300_default = { 62static const struct ar9300_eeprom ar9300_default = {
59 .eepromVersion = 2, 63 .eepromVersion = 2,
60 .templateVersion = 2, 64 .templateVersion = 2,
@@ -144,13 +148,16 @@ static const struct ar9300_eeprom ar9300_default = {
144 .txEndToRxOn = 0x2, 148 .txEndToRxOn = 0x2,
145 .txFrameToXpaOn = 0xe, 149 .txFrameToXpaOn = 0xe,
146 .thresh62 = 28, 150 .thresh62 = 28,
147 .papdRateMaskHt20 = LE32(0x80c080), 151 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
148 .papdRateMaskHt40 = LE32(0x80c080), 152 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
149 .futureModal = { 153 .futureModal = {
150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
151 0, 0, 0, 0, 0, 0, 0, 0
152 }, 155 },
153 }, 156 },
157 .base_ext1 = {
158 .ant_div_control = 0,
159 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
160 },
154 .calFreqPier2G = { 161 .calFreqPier2G = {
155 FREQ2FBIN(2412, 1), 162 FREQ2FBIN(2412, 1),
156 FREQ2FBIN(2437, 1), 163 FREQ2FBIN(2437, 1),
@@ -285,8 +292,7 @@ static const struct ar9300_eeprom ar9300_default = {
285 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 292 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
286 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 293 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
287 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 294 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
288 /* Data[11].ctlEdges[3].bChannel */ 295 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
289 FREQ2FBIN(2462, 1),
290 } 296 }
291 }, 297 },
292 .ctlPowerData_2G = { 298 .ctlPowerData_2G = {
@@ -304,6 +310,7 @@ static const struct ar9300_eeprom ar9300_default = {
304 310
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 311 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
306 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, 312 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
313 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
307 }, 314 },
308 .modalHeader5G = { 315 .modalHeader5G = {
309 /* 4 idle,t1,t2,b (4 bits per setting) */ 316 /* 4 idle,t1,t2,b (4 bits per setting) */
@@ -343,13 +350,20 @@ static const struct ar9300_eeprom ar9300_default = {
343 .txEndToRxOn = 0x2, 350 .txEndToRxOn = 0x2,
344 .txFrameToXpaOn = 0xe, 351 .txFrameToXpaOn = 0xe,
345 .thresh62 = 28, 352 .thresh62 = 28,
346 .papdRateMaskHt20 = LE32(0xf0e0e0), 353 .papdRateMaskHt20 = LE32(0x0c80c080),
347 .papdRateMaskHt40 = LE32(0xf0e0e0), 354 .papdRateMaskHt40 = LE32(0x0080c080),
348 .futureModal = { 355 .futureModal = {
349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
350 0, 0, 0, 0, 0, 0, 0, 0
351 }, 357 },
352 }, 358 },
359 .base_ext2 = {
360 .tempSlopeLow = 0,
361 .tempSlopeHigh = 0,
362 .xatten1DBLow = {0, 0, 0},
363 .xatten1MarginLow = {0, 0, 0},
364 .xatten1DBHigh = {0, 0, 0},
365 .xatten1MarginHigh = {0, 0, 0}
366 },
353 .calFreqPier5G = { 367 .calFreqPier5G = {
354 FREQ2FBIN(5180, 0), 368 FREQ2FBIN(5180, 0),
355 FREQ2FBIN(5220, 0), 369 FREQ2FBIN(5220, 0),
@@ -623,6 +637,2338 @@ static const struct ar9300_eeprom ar9300_default = {
623 } 637 }
624}; 638};
625 639
640static const struct ar9300_eeprom ar9300_x113 = {
641 .eepromVersion = 2,
642 .templateVersion = 6,
643 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
644 .custData = {"x113-023-f0000"},
645 .baseEepHeader = {
646 .regDmn = { LE16(0), LE16(0x1f) },
647 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
648 .opCapFlags = {
649 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
650 .eepMisc = 0,
651 },
652 .rfSilent = 0,
653 .blueToothOptions = 0,
654 .deviceCap = 0,
655 .deviceType = 5, /* takes lower byte in eeprom location */
656 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
657 .params_for_tuning_caps = {0, 0},
658 .featureEnable = 0x0d,
659 /*
660 * bit0 - enable tx temp comp - disabled
661 * bit1 - enable tx volt comp - disabled
662 * bit2 - enable fastClock - enabled
663 * bit3 - enable doubling - enabled
664 * bit4 - enable internal regulator - disabled
665 * bit5 - enable pa predistortion - disabled
666 */
667 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
668 .eepromWriteEnableGpio = 6,
669 .wlanDisableGpio = 0,
670 .wlanLedGpio = 8,
671 .rxBandSelectGpio = 0xff,
672 .txrxgain = 0x21,
673 .swreg = 0,
674 },
675 .modalHeader2G = {
676 /* ar9300_modal_eep_header 2g */
677 /* 4 idle,t1,t2,b(4 bits per setting) */
678 .antCtrlCommon = LE32(0x110),
679 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
680 .antCtrlCommon2 = LE32(0x44444),
681
682 /*
683 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
684 * rx1, rx12, b (2 bits each)
685 */
686 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
687
688 /*
689 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
690 * for ar9280 (0xa20c/b20c 5:0)
691 */
692 .xatten1DB = {0, 0, 0},
693
694 /*
695 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
696 * for ar9280 (0xa20c/b20c 16:12
697 */
698 .xatten1Margin = {0, 0, 0},
699 .tempSlope = 25,
700 .voltSlope = 0,
701
702 /*
703 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
704 * channels in usual fbin coding format
705 */
706 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
707
708 /*
709 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
710 * if the register is per chain
711 */
712 .noiseFloorThreshCh = {-1, 0, 0},
713 .ob = {1, 1, 1},/* 3 chain */
714 .db_stage2 = {1, 1, 1}, /* 3 chain */
715 .db_stage3 = {0, 0, 0},
716 .db_stage4 = {0, 0, 0},
717 .xpaBiasLvl = 0,
718 .txFrameToDataStart = 0x0e,
719 .txFrameToPaOn = 0x0e,
720 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
721 .antennaGain = 0,
722 .switchSettling = 0x2c,
723 .adcDesiredSize = -30,
724 .txEndToXpaOff = 0,
725 .txEndToRxOn = 0x2,
726 .txFrameToXpaOn = 0xe,
727 .thresh62 = 28,
728 .papdRateMaskHt20 = LE32(0x0c80c080),
729 .papdRateMaskHt40 = LE32(0x0080c080),
730 .futureModal = {
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
732 },
733 },
734 .base_ext1 = {
735 .ant_div_control = 0,
736 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
737 },
738 .calFreqPier2G = {
739 FREQ2FBIN(2412, 1),
740 FREQ2FBIN(2437, 1),
741 FREQ2FBIN(2472, 1),
742 },
743 /* ar9300_cal_data_per_freq_op_loop 2g */
744 .calPierData2G = {
745 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
746 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
747 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
748 },
749 .calTarget_freqbin_Cck = {
750 FREQ2FBIN(2412, 1),
751 FREQ2FBIN(2472, 1),
752 },
753 .calTarget_freqbin_2G = {
754 FREQ2FBIN(2412, 1),
755 FREQ2FBIN(2437, 1),
756 FREQ2FBIN(2472, 1)
757 },
758 .calTarget_freqbin_2GHT20 = {
759 FREQ2FBIN(2412, 1),
760 FREQ2FBIN(2437, 1),
761 FREQ2FBIN(2472, 1)
762 },
763 .calTarget_freqbin_2GHT40 = {
764 FREQ2FBIN(2412, 1),
765 FREQ2FBIN(2437, 1),
766 FREQ2FBIN(2472, 1)
767 },
768 .calTargetPowerCck = {
769 /* 1L-5L,5S,11L,11S */
770 { {34, 34, 34, 34} },
771 { {34, 34, 34, 34} },
772 },
773 .calTargetPower2G = {
774 /* 6-24,36,48,54 */
775 { {34, 34, 32, 32} },
776 { {34, 34, 32, 32} },
777 { {34, 34, 32, 32} },
778 },
779 .calTargetPower2GHT20 = {
780 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
781 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
782 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
783 },
784 .calTargetPower2GHT40 = {
785 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
786 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
787 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
788 },
789 .ctlIndex_2G = {
790 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
791 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
792 },
793 .ctl_freqbin_2G = {
794 {
795 FREQ2FBIN(2412, 1),
796 FREQ2FBIN(2417, 1),
797 FREQ2FBIN(2457, 1),
798 FREQ2FBIN(2462, 1)
799 },
800 {
801 FREQ2FBIN(2412, 1),
802 FREQ2FBIN(2417, 1),
803 FREQ2FBIN(2462, 1),
804 0xFF,
805 },
806
807 {
808 FREQ2FBIN(2412, 1),
809 FREQ2FBIN(2417, 1),
810 FREQ2FBIN(2462, 1),
811 0xFF,
812 },
813 {
814 FREQ2FBIN(2422, 1),
815 FREQ2FBIN(2427, 1),
816 FREQ2FBIN(2447, 1),
817 FREQ2FBIN(2452, 1)
818 },
819
820 {
821 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
822 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
823 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
824 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
825 },
826
827 {
828 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
829 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
831 0,
832 },
833
834 {
835 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
837 FREQ2FBIN(2472, 1),
838 0,
839 },
840
841 {
842 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
843 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
844 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
845 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
846 },
847
848 {
849 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
850 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
851 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
852 },
853
854 {
855 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
856 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
857 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
858 0
859 },
860
861 {
862 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
863 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
864 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
865 0
866 },
867
868 {
869 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
870 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
871 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
872 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
873 }
874 },
875 .ctlPowerData_2G = {
876 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
877 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
878 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
879
880 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
881 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
882 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
883
884 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
885 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
886 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
887
888 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
889 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
890 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
891 },
892 .modalHeader5G = {
893 /* 4 idle,t1,t2,b (4 bits per setting) */
894 .antCtrlCommon = LE32(0x220),
895 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
896 .antCtrlCommon2 = LE32(0x11111),
897 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
898 .antCtrlChain = {
899 LE16(0x150), LE16(0x150), LE16(0x150),
900 },
901 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
902 .xatten1DB = {0, 0, 0},
903
904 /*
905 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
906 * for merlin (0xa20c/b20c 16:12
907 */
908 .xatten1Margin = {0, 0, 0},
909 .tempSlope = 68,
910 .voltSlope = 0,
911 /* spurChans spur channels in usual fbin coding format */
912 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
913 /* noiseFloorThreshCh Check if the register is per chain */
914 .noiseFloorThreshCh = {-1, 0, 0},
915 .ob = {3, 3, 3}, /* 3 chain */
916 .db_stage2 = {3, 3, 3}, /* 3 chain */
917 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
918 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
919 .xpaBiasLvl = 0,
920 .txFrameToDataStart = 0x0e,
921 .txFrameToPaOn = 0x0e,
922 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
923 .antennaGain = 0,
924 .switchSettling = 0x2d,
925 .adcDesiredSize = -30,
926 .txEndToXpaOff = 0,
927 .txEndToRxOn = 0x2,
928 .txFrameToXpaOn = 0xe,
929 .thresh62 = 28,
930 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
931 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
932 .futureModal = {
933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
934 },
935 },
936 .base_ext2 = {
937 .tempSlopeLow = 72,
938 .tempSlopeHigh = 105,
939 .xatten1DBLow = {0, 0, 0},
940 .xatten1MarginLow = {0, 0, 0},
941 .xatten1DBHigh = {0, 0, 0},
942 .xatten1MarginHigh = {0, 0, 0}
943 },
944 .calFreqPier5G = {
945 FREQ2FBIN(5180, 0),
946 FREQ2FBIN(5240, 0),
947 FREQ2FBIN(5320, 0),
948 FREQ2FBIN(5400, 0),
949 FREQ2FBIN(5500, 0),
950 FREQ2FBIN(5600, 0),
951 FREQ2FBIN(5745, 0),
952 FREQ2FBIN(5785, 0)
953 },
954 .calPierData5G = {
955 {
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 },
965 {
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 {0, 0, 0, 0, 0},
972 {0, 0, 0, 0, 0},
973 {0, 0, 0, 0, 0},
974 },
975 {
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 {0, 0, 0, 0, 0},
980 {0, 0, 0, 0, 0},
981 {0, 0, 0, 0, 0},
982 {0, 0, 0, 0, 0},
983 {0, 0, 0, 0, 0},
984 },
985
986 },
987 .calTarget_freqbin_5G = {
988 FREQ2FBIN(5180, 0),
989 FREQ2FBIN(5220, 0),
990 FREQ2FBIN(5320, 0),
991 FREQ2FBIN(5400, 0),
992 FREQ2FBIN(5500, 0),
993 FREQ2FBIN(5600, 0),
994 FREQ2FBIN(5745, 0),
995 FREQ2FBIN(5785, 0)
996 },
997 .calTarget_freqbin_5GHT20 = {
998 FREQ2FBIN(5180, 0),
999 FREQ2FBIN(5240, 0),
1000 FREQ2FBIN(5320, 0),
1001 FREQ2FBIN(5400, 0),
1002 FREQ2FBIN(5500, 0),
1003 FREQ2FBIN(5700, 0),
1004 FREQ2FBIN(5745, 0),
1005 FREQ2FBIN(5825, 0)
1006 },
1007 .calTarget_freqbin_5GHT40 = {
1008 FREQ2FBIN(5190, 0),
1009 FREQ2FBIN(5230, 0),
1010 FREQ2FBIN(5320, 0),
1011 FREQ2FBIN(5410, 0),
1012 FREQ2FBIN(5510, 0),
1013 FREQ2FBIN(5670, 0),
1014 FREQ2FBIN(5755, 0),
1015 FREQ2FBIN(5825, 0)
1016 },
1017 .calTargetPower5G = {
1018 /* 6-24,36,48,54 */
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1027 },
1028 .calTargetPower5GHT20 = {
1029 /*
1030 * 0_8_16,1-3_9-11_17-19,
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1032 */
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1040 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1041 },
1042 .calTargetPower5GHT40 = {
1043 /*
1044 * 0_8_16,1-3_9-11_17-19,
1045 * 4,5,6,7,12,13,14,15,20,21,22,23
1046 */
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1054 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1055 },
1056 .ctlIndex_5G = {
1057 0x10, 0x16, 0x18, 0x40, 0x46,
1058 0x48, 0x30, 0x36, 0x38
1059 },
1060 .ctl_freqbin_5G = {
1061 {
1062 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1063 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1064 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1065 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1066 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1067 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1068 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1069 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1070 },
1071 {
1072 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1074 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1075 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1076 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1077 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1079 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1080 },
1081
1082 {
1083 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1084 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1085 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1086 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1087 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1088 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1089 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1090 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1091 },
1092
1093 {
1094 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1095 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1096 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1097 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1098 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1099 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1100 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1101 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1102 },
1103
1104 {
1105 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1107 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1108 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1110 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1111 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1112 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1113 },
1114
1115 {
1116 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1117 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1118 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1119 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1120 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1121 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1122 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1123 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1124 },
1125
1126 {
1127 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1128 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1129 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1130 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1131 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1132 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1133 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1134 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1135 },
1136
1137 {
1138 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1140 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1141 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1142 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1143 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1145 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1146 },
1147
1148 {
1149 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1150 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1151 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1152 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1153 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1154 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1155 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1156 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1157 }
1158 },
1159 .ctlPowerData_5G = {
1160 {
1161 {
1162 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1163 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1164 }
1165 },
1166 {
1167 {
1168 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1169 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1170 }
1171 },
1172 {
1173 {
1174 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1175 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1176 }
1177 },
1178 {
1179 {
1180 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1181 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1182 }
1183 },
1184 {
1185 {
1186 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1187 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1188 }
1189 },
1190 {
1191 {
1192 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1193 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1194 }
1195 },
1196 {
1197 {
1198 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1199 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1200 }
1201 },
1202 {
1203 {
1204 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1205 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1206 }
1207 },
1208 {
1209 {
1210 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1211 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1212 }
1213 },
1214 }
1215};
1216
1217
1218static const struct ar9300_eeprom ar9300_h112 = {
1219 .eepromVersion = 2,
1220 .templateVersion = 3,
1221 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1222 .custData = {"h112-241-f0000"},
1223 .baseEepHeader = {
1224 .regDmn = { LE16(0), LE16(0x1f) },
1225 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1226 .opCapFlags = {
1227 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1228 .eepMisc = 0,
1229 },
1230 .rfSilent = 0,
1231 .blueToothOptions = 0,
1232 .deviceCap = 0,
1233 .deviceType = 5, /* takes lower byte in eeprom location */
1234 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1235 .params_for_tuning_caps = {0, 0},
1236 .featureEnable = 0x0d,
1237 /*
1238 * bit0 - enable tx temp comp - disabled
1239 * bit1 - enable tx volt comp - disabled
1240 * bit2 - enable fastClock - enabled
1241 * bit3 - enable doubling - enabled
1242 * bit4 - enable internal regulator - disabled
1243 * bit5 - enable pa predistortion - disabled
1244 */
1245 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1246 .eepromWriteEnableGpio = 6,
1247 .wlanDisableGpio = 0,
1248 .wlanLedGpio = 8,
1249 .rxBandSelectGpio = 0xff,
1250 .txrxgain = 0x10,
1251 .swreg = 0,
1252 },
1253 .modalHeader2G = {
1254 /* ar9300_modal_eep_header 2g */
1255 /* 4 idle,t1,t2,b(4 bits per setting) */
1256 .antCtrlCommon = LE32(0x110),
1257 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1258 .antCtrlCommon2 = LE32(0x44444),
1259
1260 /*
1261 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1262 * rx1, rx12, b (2 bits each)
1263 */
1264 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1265
1266 /*
1267 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1268 * for ar9280 (0xa20c/b20c 5:0)
1269 */
1270 .xatten1DB = {0, 0, 0},
1271
1272 /*
1273 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1274 * for ar9280 (0xa20c/b20c 16:12
1275 */
1276 .xatten1Margin = {0, 0, 0},
1277 .tempSlope = 25,
1278 .voltSlope = 0,
1279
1280 /*
1281 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1282 * channels in usual fbin coding format
1283 */
1284 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1285
1286 /*
1287 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1288 * if the register is per chain
1289 */
1290 .noiseFloorThreshCh = {-1, 0, 0},
1291 .ob = {1, 1, 1},/* 3 chain */
1292 .db_stage2 = {1, 1, 1}, /* 3 chain */
1293 .db_stage3 = {0, 0, 0},
1294 .db_stage4 = {0, 0, 0},
1295 .xpaBiasLvl = 0,
1296 .txFrameToDataStart = 0x0e,
1297 .txFrameToPaOn = 0x0e,
1298 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1299 .antennaGain = 0,
1300 .switchSettling = 0x2c,
1301 .adcDesiredSize = -30,
1302 .txEndToXpaOff = 0,
1303 .txEndToRxOn = 0x2,
1304 .txFrameToXpaOn = 0xe,
1305 .thresh62 = 28,
1306 .papdRateMaskHt20 = LE32(0x80c080),
1307 .papdRateMaskHt40 = LE32(0x80c080),
1308 .futureModal = {
1309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1310 },
1311 },
1312 .base_ext1 = {
1313 .ant_div_control = 0,
1314 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1315 },
1316 .calFreqPier2G = {
1317 FREQ2FBIN(2412, 1),
1318 FREQ2FBIN(2437, 1),
1319 FREQ2FBIN(2472, 1),
1320 },
1321 /* ar9300_cal_data_per_freq_op_loop 2g */
1322 .calPierData2G = {
1323 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1325 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1326 },
1327 .calTarget_freqbin_Cck = {
1328 FREQ2FBIN(2412, 1),
1329 FREQ2FBIN(2484, 1),
1330 },
1331 .calTarget_freqbin_2G = {
1332 FREQ2FBIN(2412, 1),
1333 FREQ2FBIN(2437, 1),
1334 FREQ2FBIN(2472, 1)
1335 },
1336 .calTarget_freqbin_2GHT20 = {
1337 FREQ2FBIN(2412, 1),
1338 FREQ2FBIN(2437, 1),
1339 FREQ2FBIN(2472, 1)
1340 },
1341 .calTarget_freqbin_2GHT40 = {
1342 FREQ2FBIN(2412, 1),
1343 FREQ2FBIN(2437, 1),
1344 FREQ2FBIN(2472, 1)
1345 },
1346 .calTargetPowerCck = {
1347 /* 1L-5L,5S,11L,11S */
1348 { {34, 34, 34, 34} },
1349 { {34, 34, 34, 34} },
1350 },
1351 .calTargetPower2G = {
1352 /* 6-24,36,48,54 */
1353 { {34, 34, 32, 32} },
1354 { {34, 34, 32, 32} },
1355 { {34, 34, 32, 32} },
1356 },
1357 .calTargetPower2GHT20 = {
1358 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1360 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1361 },
1362 .calTargetPower2GHT40 = {
1363 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1365 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1366 },
1367 .ctlIndex_2G = {
1368 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1369 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1370 },
1371 .ctl_freqbin_2G = {
1372 {
1373 FREQ2FBIN(2412, 1),
1374 FREQ2FBIN(2417, 1),
1375 FREQ2FBIN(2457, 1),
1376 FREQ2FBIN(2462, 1)
1377 },
1378 {
1379 FREQ2FBIN(2412, 1),
1380 FREQ2FBIN(2417, 1),
1381 FREQ2FBIN(2462, 1),
1382 0xFF,
1383 },
1384
1385 {
1386 FREQ2FBIN(2412, 1),
1387 FREQ2FBIN(2417, 1),
1388 FREQ2FBIN(2462, 1),
1389 0xFF,
1390 },
1391 {
1392 FREQ2FBIN(2422, 1),
1393 FREQ2FBIN(2427, 1),
1394 FREQ2FBIN(2447, 1),
1395 FREQ2FBIN(2452, 1)
1396 },
1397
1398 {
1399 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1402 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1403 },
1404
1405 {
1406 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409 0,
1410 },
1411
1412 {
1413 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 FREQ2FBIN(2472, 1),
1416 0,
1417 },
1418
1419 {
1420 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424 },
1425
1426 {
1427 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1430 },
1431
1432 {
1433 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1436 0
1437 },
1438
1439 {
1440 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1443 0
1444 },
1445
1446 {
1447 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1448 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1449 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1450 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1451 }
1452 },
1453 .ctlPowerData_2G = {
1454 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1455 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1457
1458 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1459 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1461
1462 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1463 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1464 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1465
1466 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1467 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1468 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1469 },
1470 .modalHeader5G = {
1471 /* 4 idle,t1,t2,b (4 bits per setting) */
1472 .antCtrlCommon = LE32(0x220),
1473 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1474 .antCtrlCommon2 = LE32(0x44444),
1475 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1476 .antCtrlChain = {
1477 LE16(0x150), LE16(0x150), LE16(0x150),
1478 },
1479 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1480 .xatten1DB = {0, 0, 0},
1481
1482 /*
1483 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1484 * for merlin (0xa20c/b20c 16:12
1485 */
1486 .xatten1Margin = {0, 0, 0},
1487 .tempSlope = 45,
1488 .voltSlope = 0,
1489 /* spurChans spur channels in usual fbin coding format */
1490 .spurChans = {0, 0, 0, 0, 0},
1491 /* noiseFloorThreshCh Check if the register is per chain */
1492 .noiseFloorThreshCh = {-1, 0, 0},
1493 .ob = {3, 3, 3}, /* 3 chain */
1494 .db_stage2 = {3, 3, 3}, /* 3 chain */
1495 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1496 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1497 .xpaBiasLvl = 0,
1498 .txFrameToDataStart = 0x0e,
1499 .txFrameToPaOn = 0x0e,
1500 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1501 .antennaGain = 0,
1502 .switchSettling = 0x2d,
1503 .adcDesiredSize = -30,
1504 .txEndToXpaOff = 0,
1505 .txEndToRxOn = 0x2,
1506 .txFrameToXpaOn = 0xe,
1507 .thresh62 = 28,
1508 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1509 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1510 .futureModal = {
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1512 },
1513 },
1514 .base_ext2 = {
1515 .tempSlopeLow = 40,
1516 .tempSlopeHigh = 50,
1517 .xatten1DBLow = {0, 0, 0},
1518 .xatten1MarginLow = {0, 0, 0},
1519 .xatten1DBHigh = {0, 0, 0},
1520 .xatten1MarginHigh = {0, 0, 0}
1521 },
1522 .calFreqPier5G = {
1523 FREQ2FBIN(5180, 0),
1524 FREQ2FBIN(5220, 0),
1525 FREQ2FBIN(5320, 0),
1526 FREQ2FBIN(5400, 0),
1527 FREQ2FBIN(5500, 0),
1528 FREQ2FBIN(5600, 0),
1529 FREQ2FBIN(5700, 0),
1530 FREQ2FBIN(5825, 0)
1531 },
1532 .calPierData5G = {
1533 {
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 },
1543 {
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 {0, 0, 0, 0, 0},
1550 {0, 0, 0, 0, 0},
1551 {0, 0, 0, 0, 0},
1552 },
1553 {
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 {0, 0, 0, 0, 0},
1558 {0, 0, 0, 0, 0},
1559 {0, 0, 0, 0, 0},
1560 {0, 0, 0, 0, 0},
1561 {0, 0, 0, 0, 0},
1562 },
1563
1564 },
1565 .calTarget_freqbin_5G = {
1566 FREQ2FBIN(5180, 0),
1567 FREQ2FBIN(5240, 0),
1568 FREQ2FBIN(5320, 0),
1569 FREQ2FBIN(5400, 0),
1570 FREQ2FBIN(5500, 0),
1571 FREQ2FBIN(5600, 0),
1572 FREQ2FBIN(5700, 0),
1573 FREQ2FBIN(5825, 0)
1574 },
1575 .calTarget_freqbin_5GHT20 = {
1576 FREQ2FBIN(5180, 0),
1577 FREQ2FBIN(5240, 0),
1578 FREQ2FBIN(5320, 0),
1579 FREQ2FBIN(5400, 0),
1580 FREQ2FBIN(5500, 0),
1581 FREQ2FBIN(5700, 0),
1582 FREQ2FBIN(5745, 0),
1583 FREQ2FBIN(5825, 0)
1584 },
1585 .calTarget_freqbin_5GHT40 = {
1586 FREQ2FBIN(5180, 0),
1587 FREQ2FBIN(5240, 0),
1588 FREQ2FBIN(5320, 0),
1589 FREQ2FBIN(5400, 0),
1590 FREQ2FBIN(5500, 0),
1591 FREQ2FBIN(5700, 0),
1592 FREQ2FBIN(5745, 0),
1593 FREQ2FBIN(5825, 0)
1594 },
1595 .calTargetPower5G = {
1596 /* 6-24,36,48,54 */
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1605 },
1606 .calTargetPower5GHT20 = {
1607 /*
1608 * 0_8_16,1-3_9-11_17-19,
1609 * 4,5,6,7,12,13,14,15,20,21,22,23
1610 */
1611 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1612 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1613 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1614 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1615 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1616 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1617 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1618 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1619 },
1620 .calTargetPower5GHT40 = {
1621 /*
1622 * 0_8_16,1-3_9-11_17-19,
1623 * 4,5,6,7,12,13,14,15,20,21,22,23
1624 */
1625 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1626 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1627 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1628 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1629 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1630 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1631 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1632 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1633 },
1634 .ctlIndex_5G = {
1635 0x10, 0x16, 0x18, 0x40, 0x46,
1636 0x48, 0x30, 0x36, 0x38
1637 },
1638 .ctl_freqbin_5G = {
1639 {
1640 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1641 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1642 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1643 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1644 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1645 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1646 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1647 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1648 },
1649 {
1650 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1651 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1652 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1653 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1654 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1655 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1656 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1657 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1658 },
1659
1660 {
1661 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1662 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1663 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1664 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1665 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1666 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1667 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1668 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1669 },
1670
1671 {
1672 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1673 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1674 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1675 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1676 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1677 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1678 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1679 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1680 },
1681
1682 {
1683 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1684 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1685 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1686 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1687 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1688 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1689 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1690 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1691 },
1692
1693 {
1694 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1695 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1696 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1697 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1698 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1699 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1700 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1701 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1702 },
1703
1704 {
1705 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1706 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1707 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1708 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1709 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1710 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1711 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1712 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1713 },
1714
1715 {
1716 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1718 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1719 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1720 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1721 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1723 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1724 },
1725
1726 {
1727 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1728 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1729 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1730 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1731 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1732 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1733 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1734 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1735 }
1736 },
1737 .ctlPowerData_5G = {
1738 {
1739 {
1740 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1741 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1742 }
1743 },
1744 {
1745 {
1746 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1747 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1748 }
1749 },
1750 {
1751 {
1752 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1753 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1754 }
1755 },
1756 {
1757 {
1758 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1759 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1760 }
1761 },
1762 {
1763 {
1764 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1765 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1766 }
1767 },
1768 {
1769 {
1770 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1771 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1772 }
1773 },
1774 {
1775 {
1776 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1777 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1778 }
1779 },
1780 {
1781 {
1782 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1783 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1784 }
1785 },
1786 {
1787 {
1788 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1789 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1790 }
1791 },
1792 }
1793};
1794
1795
1796static const struct ar9300_eeprom ar9300_x112 = {
1797 .eepromVersion = 2,
1798 .templateVersion = 5,
1799 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1800 .custData = {"x112-041-f0000"},
1801 .baseEepHeader = {
1802 .regDmn = { LE16(0), LE16(0x1f) },
1803 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1804 .opCapFlags = {
1805 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1806 .eepMisc = 0,
1807 },
1808 .rfSilent = 0,
1809 .blueToothOptions = 0,
1810 .deviceCap = 0,
1811 .deviceType = 5, /* takes lower byte in eeprom location */
1812 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1813 .params_for_tuning_caps = {0, 0},
1814 .featureEnable = 0x0d,
1815 /*
1816 * bit0 - enable tx temp comp - disabled
1817 * bit1 - enable tx volt comp - disabled
1818 * bit2 - enable fastclock - enabled
1819 * bit3 - enable doubling - enabled
1820 * bit4 - enable internal regulator - disabled
1821 * bit5 - enable pa predistortion - disabled
1822 */
1823 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1824 .eepromWriteEnableGpio = 6,
1825 .wlanDisableGpio = 0,
1826 .wlanLedGpio = 8,
1827 .rxBandSelectGpio = 0xff,
1828 .txrxgain = 0x0,
1829 .swreg = 0,
1830 },
1831 .modalHeader2G = {
1832 /* ar9300_modal_eep_header 2g */
1833 /* 4 idle,t1,t2,b(4 bits per setting) */
1834 .antCtrlCommon = LE32(0x110),
1835 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1836 .antCtrlCommon2 = LE32(0x22222),
1837
1838 /*
1839 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1840 * rx1, rx12, b (2 bits each)
1841 */
1842 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1843
1844 /*
1845 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1846 * for ar9280 (0xa20c/b20c 5:0)
1847 */
1848 .xatten1DB = {0x1b, 0x1b, 0x1b},
1849
1850 /*
1851 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1852 * for ar9280 (0xa20c/b20c 16:12
1853 */
1854 .xatten1Margin = {0x15, 0x15, 0x15},
1855 .tempSlope = 50,
1856 .voltSlope = 0,
1857
1858 /*
1859 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1860 * channels in usual fbin coding format
1861 */
1862 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1863
1864 /*
1865 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1866 * if the register is per chain
1867 */
1868 .noiseFloorThreshCh = {-1, 0, 0},
1869 .ob = {1, 1, 1},/* 3 chain */
1870 .db_stage2 = {1, 1, 1}, /* 3 chain */
1871 .db_stage3 = {0, 0, 0},
1872 .db_stage4 = {0, 0, 0},
1873 .xpaBiasLvl = 0,
1874 .txFrameToDataStart = 0x0e,
1875 .txFrameToPaOn = 0x0e,
1876 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1877 .antennaGain = 0,
1878 .switchSettling = 0x2c,
1879 .adcDesiredSize = -30,
1880 .txEndToXpaOff = 0,
1881 .txEndToRxOn = 0x2,
1882 .txFrameToXpaOn = 0xe,
1883 .thresh62 = 28,
1884 .papdRateMaskHt20 = LE32(0x0c80c080),
1885 .papdRateMaskHt40 = LE32(0x0080c080),
1886 .futureModal = {
1887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1888 },
1889 },
1890 .base_ext1 = {
1891 .ant_div_control = 0,
1892 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1893 },
1894 .calFreqPier2G = {
1895 FREQ2FBIN(2412, 1),
1896 FREQ2FBIN(2437, 1),
1897 FREQ2FBIN(2472, 1),
1898 },
1899 /* ar9300_cal_data_per_freq_op_loop 2g */
1900 .calPierData2G = {
1901 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1903 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1904 },
1905 .calTarget_freqbin_Cck = {
1906 FREQ2FBIN(2412, 1),
1907 FREQ2FBIN(2472, 1),
1908 },
1909 .calTarget_freqbin_2G = {
1910 FREQ2FBIN(2412, 1),
1911 FREQ2FBIN(2437, 1),
1912 FREQ2FBIN(2472, 1)
1913 },
1914 .calTarget_freqbin_2GHT20 = {
1915 FREQ2FBIN(2412, 1),
1916 FREQ2FBIN(2437, 1),
1917 FREQ2FBIN(2472, 1)
1918 },
1919 .calTarget_freqbin_2GHT40 = {
1920 FREQ2FBIN(2412, 1),
1921 FREQ2FBIN(2437, 1),
1922 FREQ2FBIN(2472, 1)
1923 },
1924 .calTargetPowerCck = {
1925 /* 1L-5L,5S,11L,11s */
1926 { {38, 38, 38, 38} },
1927 { {38, 38, 38, 38} },
1928 },
1929 .calTargetPower2G = {
1930 /* 6-24,36,48,54 */
1931 { {38, 38, 36, 34} },
1932 { {38, 38, 36, 34} },
1933 { {38, 38, 34, 32} },
1934 },
1935 .calTargetPower2GHT20 = {
1936 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1938 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1939 },
1940 .calTargetPower2GHT40 = {
1941 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1943 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1944 },
1945 .ctlIndex_2G = {
1946 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1947 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1948 },
1949 .ctl_freqbin_2G = {
1950 {
1951 FREQ2FBIN(2412, 1),
1952 FREQ2FBIN(2417, 1),
1953 FREQ2FBIN(2457, 1),
1954 FREQ2FBIN(2462, 1)
1955 },
1956 {
1957 FREQ2FBIN(2412, 1),
1958 FREQ2FBIN(2417, 1),
1959 FREQ2FBIN(2462, 1),
1960 0xFF,
1961 },
1962
1963 {
1964 FREQ2FBIN(2412, 1),
1965 FREQ2FBIN(2417, 1),
1966 FREQ2FBIN(2462, 1),
1967 0xFF,
1968 },
1969 {
1970 FREQ2FBIN(2422, 1),
1971 FREQ2FBIN(2427, 1),
1972 FREQ2FBIN(2447, 1),
1973 FREQ2FBIN(2452, 1)
1974 },
1975
1976 {
1977 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1981 },
1982
1983 {
1984 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987 0,
1988 },
1989
1990 {
1991 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993 FREQ2FBIN(2472, 1),
1994 0,
1995 },
1996
1997 {
1998 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1999 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2000 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2001 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2002 },
2003
2004 {
2005 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2008 },
2009
2010 {
2011 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2014 0
2015 },
2016
2017 {
2018 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2021 0
2022 },
2023
2024 {
2025 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2026 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2027 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2028 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2029 }
2030 },
2031 .ctlPowerData_2G = {
2032 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2033 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2035
2036 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2037 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2039
2040 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2041 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2042 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2043
2044 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2045 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2046 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2047 },
2048 .modalHeader5G = {
2049 /* 4 idle,t1,t2,b (4 bits per setting) */
2050 .antCtrlCommon = LE32(0x110),
2051 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2052 .antCtrlCommon2 = LE32(0x22222),
2053 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2054 .antCtrlChain = {
2055 LE16(0x0), LE16(0x0), LE16(0x0),
2056 },
2057 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058 .xatten1DB = {0x13, 0x19, 0x17},
2059
2060 /*
2061 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2062 * for merlin (0xa20c/b20c 16:12
2063 */
2064 .xatten1Margin = {0x19, 0x19, 0x19},
2065 .tempSlope = 70,
2066 .voltSlope = 15,
2067 /* spurChans spur channels in usual fbin coding format */
2068 .spurChans = {0, 0, 0, 0, 0},
2069 /* noiseFloorThreshch check if the register is per chain */
2070 .noiseFloorThreshCh = {-1, 0, 0},
2071 .ob = {3, 3, 3}, /* 3 chain */
2072 .db_stage2 = {3, 3, 3}, /* 3 chain */
2073 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2074 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2075 .xpaBiasLvl = 0,
2076 .txFrameToDataStart = 0x0e,
2077 .txFrameToPaOn = 0x0e,
2078 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2079 .antennaGain = 0,
2080 .switchSettling = 0x2d,
2081 .adcDesiredSize = -30,
2082 .txEndToXpaOff = 0,
2083 .txEndToRxOn = 0x2,
2084 .txFrameToXpaOn = 0xe,
2085 .thresh62 = 28,
2086 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2087 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2088 .futureModal = {
2089 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2090 },
2091 },
2092 .base_ext2 = {
2093 .tempSlopeLow = 72,
2094 .tempSlopeHigh = 105,
2095 .xatten1DBLow = {0x10, 0x14, 0x10},
2096 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2097 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2098 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2099 },
2100 .calFreqPier5G = {
2101 FREQ2FBIN(5180, 0),
2102 FREQ2FBIN(5220, 0),
2103 FREQ2FBIN(5320, 0),
2104 FREQ2FBIN(5400, 0),
2105 FREQ2FBIN(5500, 0),
2106 FREQ2FBIN(5600, 0),
2107 FREQ2FBIN(5700, 0),
2108 FREQ2FBIN(5785, 0)
2109 },
2110 .calPierData5G = {
2111 {
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 {0, 0, 0, 0, 0},
2119 {0, 0, 0, 0, 0},
2120 },
2121 {
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 {0, 0, 0, 0, 0},
2128 {0, 0, 0, 0, 0},
2129 {0, 0, 0, 0, 0},
2130 },
2131 {
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 {0, 0, 0, 0, 0},
2136 {0, 0, 0, 0, 0},
2137 {0, 0, 0, 0, 0},
2138 {0, 0, 0, 0, 0},
2139 {0, 0, 0, 0, 0},
2140 },
2141
2142 },
2143 .calTarget_freqbin_5G = {
2144 FREQ2FBIN(5180, 0),
2145 FREQ2FBIN(5220, 0),
2146 FREQ2FBIN(5320, 0),
2147 FREQ2FBIN(5400, 0),
2148 FREQ2FBIN(5500, 0),
2149 FREQ2FBIN(5600, 0),
2150 FREQ2FBIN(5725, 0),
2151 FREQ2FBIN(5825, 0)
2152 },
2153 .calTarget_freqbin_5GHT20 = {
2154 FREQ2FBIN(5180, 0),
2155 FREQ2FBIN(5220, 0),
2156 FREQ2FBIN(5320, 0),
2157 FREQ2FBIN(5400, 0),
2158 FREQ2FBIN(5500, 0),
2159 FREQ2FBIN(5600, 0),
2160 FREQ2FBIN(5725, 0),
2161 FREQ2FBIN(5825, 0)
2162 },
2163 .calTarget_freqbin_5GHT40 = {
2164 FREQ2FBIN(5180, 0),
2165 FREQ2FBIN(5220, 0),
2166 FREQ2FBIN(5320, 0),
2167 FREQ2FBIN(5400, 0),
2168 FREQ2FBIN(5500, 0),
2169 FREQ2FBIN(5600, 0),
2170 FREQ2FBIN(5725, 0),
2171 FREQ2FBIN(5825, 0)
2172 },
2173 .calTargetPower5G = {
2174 /* 6-24,36,48,54 */
2175 { {32, 32, 28, 26} },
2176 { {32, 32, 28, 26} },
2177 { {32, 32, 28, 26} },
2178 { {32, 32, 26, 24} },
2179 { {32, 32, 26, 24} },
2180 { {32, 32, 24, 22} },
2181 { {30, 30, 24, 22} },
2182 { {30, 30, 24, 22} },
2183 },
2184 .calTargetPower5GHT20 = {
2185 /*
2186 * 0_8_16,1-3_9-11_17-19,
2187 * 4,5,6,7,12,13,14,15,20,21,22,23
2188 */
2189 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2191 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2193 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2194 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2195 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2196 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2197 },
2198 .calTargetPower5GHT40 = {
2199 /*
2200 * 0_8_16,1-3_9-11_17-19,
2201 * 4,5,6,7,12,13,14,15,20,21,22,23
2202 */
2203 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2205 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2206 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2207 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2208 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2210 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2211 },
2212 .ctlIndex_5G = {
2213 0x10, 0x16, 0x18, 0x40, 0x46,
2214 0x48, 0x30, 0x36, 0x38
2215 },
2216 .ctl_freqbin_5G = {
2217 {
2218 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2219 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2221 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2223 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2224 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2225 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2226 },
2227 {
2228 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2231 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2232 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2233 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2234 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2235 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2236 },
2237
2238 {
2239 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2241 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2242 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2243 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2244 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2245 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2246 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2247 },
2248
2249 {
2250 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2253 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2254 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2256 /* Data[3].ctledges[6].bchannel */ 0xFF,
2257 /* Data[3].ctledges[7].bchannel */ 0xFF,
2258 },
2259
2260 {
2261 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2264 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2265 /* Data[4].ctledges[4].bchannel */ 0xFF,
2266 /* Data[4].ctledges[5].bchannel */ 0xFF,
2267 /* Data[4].ctledges[6].bchannel */ 0xFF,
2268 /* Data[4].ctledges[7].bchannel */ 0xFF,
2269 },
2270
2271 {
2272 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2274 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2275 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2277 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[5].ctledges[6].bchannel */ 0xFF,
2279 /* Data[5].ctledges[7].bchannel */ 0xFF
2280 },
2281
2282 {
2283 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2284 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2285 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2286 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2287 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2288 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2289 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2290 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2291 },
2292
2293 {
2294 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2296 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2297 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2298 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2299 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2301 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2302 },
2303
2304 {
2305 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2306 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2307 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2308 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2309 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2310 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2311 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2312 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2313 }
2314 },
2315 .ctlPowerData_5G = {
2316 {
2317 {
2318 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2319 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2320 }
2321 },
2322 {
2323 {
2324 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2325 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2326 }
2327 },
2328 {
2329 {
2330 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2331 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2332 }
2333 },
2334 {
2335 {
2336 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2337 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2338 }
2339 },
2340 {
2341 {
2342 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2343 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2344 }
2345 },
2346 {
2347 {
2348 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2349 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2350 }
2351 },
2352 {
2353 {
2354 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2355 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2356 }
2357 },
2358 {
2359 {
2360 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2361 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2362 }
2363 },
2364 {
2365 {
2366 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2367 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2368 }
2369 },
2370 }
2371};
2372
2373static const struct ar9300_eeprom ar9300_h116 = {
2374 .eepromVersion = 2,
2375 .templateVersion = 4,
2376 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2377 .custData = {"h116-041-f0000"},
2378 .baseEepHeader = {
2379 .regDmn = { LE16(0), LE16(0x1f) },
2380 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2381 .opCapFlags = {
2382 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2383 .eepMisc = 0,
2384 },
2385 .rfSilent = 0,
2386 .blueToothOptions = 0,
2387 .deviceCap = 0,
2388 .deviceType = 5, /* takes lower byte in eeprom location */
2389 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2390 .params_for_tuning_caps = {0, 0},
2391 .featureEnable = 0x0d,
2392 /*
2393 * bit0 - enable tx temp comp - disabled
2394 * bit1 - enable tx volt comp - disabled
2395 * bit2 - enable fastClock - enabled
2396 * bit3 - enable doubling - enabled
2397 * bit4 - enable internal regulator - disabled
2398 * bit5 - enable pa predistortion - disabled
2399 */
2400 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2401 .eepromWriteEnableGpio = 6,
2402 .wlanDisableGpio = 0,
2403 .wlanLedGpio = 8,
2404 .rxBandSelectGpio = 0xff,
2405 .txrxgain = 0x10,
2406 .swreg = 0,
2407 },
2408 .modalHeader2G = {
2409 /* ar9300_modal_eep_header 2g */
2410 /* 4 idle,t1,t2,b(4 bits per setting) */
2411 .antCtrlCommon = LE32(0x110),
2412 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2413 .antCtrlCommon2 = LE32(0x44444),
2414
2415 /*
2416 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2417 * rx1, rx12, b (2 bits each)
2418 */
2419 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2420
2421 /*
2422 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2423 * for ar9280 (0xa20c/b20c 5:0)
2424 */
2425 .xatten1DB = {0x1f, 0x1f, 0x1f},
2426
2427 /*
2428 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2429 * for ar9280 (0xa20c/b20c 16:12
2430 */
2431 .xatten1Margin = {0x12, 0x12, 0x12},
2432 .tempSlope = 25,
2433 .voltSlope = 0,
2434
2435 /*
2436 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2437 * channels in usual fbin coding format
2438 */
2439 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2440
2441 /*
2442 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2443 * if the register is per chain
2444 */
2445 .noiseFloorThreshCh = {-1, 0, 0},
2446 .ob = {1, 1, 1},/* 3 chain */
2447 .db_stage2 = {1, 1, 1}, /* 3 chain */
2448 .db_stage3 = {0, 0, 0},
2449 .db_stage4 = {0, 0, 0},
2450 .xpaBiasLvl = 0,
2451 .txFrameToDataStart = 0x0e,
2452 .txFrameToPaOn = 0x0e,
2453 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2454 .antennaGain = 0,
2455 .switchSettling = 0x2c,
2456 .adcDesiredSize = -30,
2457 .txEndToXpaOff = 0,
2458 .txEndToRxOn = 0x2,
2459 .txFrameToXpaOn = 0xe,
2460 .thresh62 = 28,
2461 .papdRateMaskHt20 = LE32(0x0c80C080),
2462 .papdRateMaskHt40 = LE32(0x0080C080),
2463 .futureModal = {
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465 },
2466 },
2467 .base_ext1 = {
2468 .ant_div_control = 0,
2469 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2470 },
2471 .calFreqPier2G = {
2472 FREQ2FBIN(2412, 1),
2473 FREQ2FBIN(2437, 1),
2474 FREQ2FBIN(2472, 1),
2475 },
2476 /* ar9300_cal_data_per_freq_op_loop 2g */
2477 .calPierData2G = {
2478 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2480 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2481 },
2482 .calTarget_freqbin_Cck = {
2483 FREQ2FBIN(2412, 1),
2484 FREQ2FBIN(2472, 1),
2485 },
2486 .calTarget_freqbin_2G = {
2487 FREQ2FBIN(2412, 1),
2488 FREQ2FBIN(2437, 1),
2489 FREQ2FBIN(2472, 1)
2490 },
2491 .calTarget_freqbin_2GHT20 = {
2492 FREQ2FBIN(2412, 1),
2493 FREQ2FBIN(2437, 1),
2494 FREQ2FBIN(2472, 1)
2495 },
2496 .calTarget_freqbin_2GHT40 = {
2497 FREQ2FBIN(2412, 1),
2498 FREQ2FBIN(2437, 1),
2499 FREQ2FBIN(2472, 1)
2500 },
2501 .calTargetPowerCck = {
2502 /* 1L-5L,5S,11L,11S */
2503 { {34, 34, 34, 34} },
2504 { {34, 34, 34, 34} },
2505 },
2506 .calTargetPower2G = {
2507 /* 6-24,36,48,54 */
2508 { {34, 34, 32, 32} },
2509 { {34, 34, 32, 32} },
2510 { {34, 34, 32, 32} },
2511 },
2512 .calTargetPower2GHT20 = {
2513 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2515 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2516 },
2517 .calTargetPower2GHT40 = {
2518 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2520 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2521 },
2522 .ctlIndex_2G = {
2523 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2524 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2525 },
2526 .ctl_freqbin_2G = {
2527 {
2528 FREQ2FBIN(2412, 1),
2529 FREQ2FBIN(2417, 1),
2530 FREQ2FBIN(2457, 1),
2531 FREQ2FBIN(2462, 1)
2532 },
2533 {
2534 FREQ2FBIN(2412, 1),
2535 FREQ2FBIN(2417, 1),
2536 FREQ2FBIN(2462, 1),
2537 0xFF,
2538 },
2539
2540 {
2541 FREQ2FBIN(2412, 1),
2542 FREQ2FBIN(2417, 1),
2543 FREQ2FBIN(2462, 1),
2544 0xFF,
2545 },
2546 {
2547 FREQ2FBIN(2422, 1),
2548 FREQ2FBIN(2427, 1),
2549 FREQ2FBIN(2447, 1),
2550 FREQ2FBIN(2452, 1)
2551 },
2552
2553 {
2554 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2555 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2556 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2557 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2558 },
2559
2560 {
2561 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564 0,
2565 },
2566
2567 {
2568 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570 FREQ2FBIN(2472, 1),
2571 0,
2572 },
2573
2574 {
2575 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2576 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2577 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2578 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2579 },
2580
2581 {
2582 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2585 },
2586
2587 {
2588 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2591 0
2592 },
2593
2594 {
2595 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2598 0
2599 },
2600
2601 {
2602 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2603 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2604 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2605 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2606 }
2607 },
2608 .ctlPowerData_2G = {
2609 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2610 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2612
2613 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2614 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2616
2617 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2618 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2619 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2620
2621 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2622 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2623 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2624 },
2625 .modalHeader5G = {
2626 /* 4 idle,t1,t2,b (4 bits per setting) */
2627 .antCtrlCommon = LE32(0x220),
2628 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2629 .antCtrlCommon2 = LE32(0x44444),
2630 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2631 .antCtrlChain = {
2632 LE16(0x150), LE16(0x150), LE16(0x150),
2633 },
2634 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2635 .xatten1DB = {0x19, 0x19, 0x19},
2636
2637 /*
2638 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2639 * for merlin (0xa20c/b20c 16:12
2640 */
2641 .xatten1Margin = {0x14, 0x14, 0x14},
2642 .tempSlope = 70,
2643 .voltSlope = 0,
2644 /* spurChans spur channels in usual fbin coding format */
2645 .spurChans = {0, 0, 0, 0, 0},
2646 /* noiseFloorThreshCh Check if the register is per chain */
2647 .noiseFloorThreshCh = {-1, 0, 0},
2648 .ob = {3, 3, 3}, /* 3 chain */
2649 .db_stage2 = {3, 3, 3}, /* 3 chain */
2650 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2651 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2652 .xpaBiasLvl = 0,
2653 .txFrameToDataStart = 0x0e,
2654 .txFrameToPaOn = 0x0e,
2655 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2656 .antennaGain = 0,
2657 .switchSettling = 0x2d,
2658 .adcDesiredSize = -30,
2659 .txEndToXpaOff = 0,
2660 .txEndToRxOn = 0x2,
2661 .txFrameToXpaOn = 0xe,
2662 .thresh62 = 28,
2663 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2664 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2665 .futureModal = {
2666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667 },
2668 },
2669 .base_ext2 = {
2670 .tempSlopeLow = 35,
2671 .tempSlopeHigh = 50,
2672 .xatten1DBLow = {0, 0, 0},
2673 .xatten1MarginLow = {0, 0, 0},
2674 .xatten1DBHigh = {0, 0, 0},
2675 .xatten1MarginHigh = {0, 0, 0}
2676 },
2677 .calFreqPier5G = {
2678 FREQ2FBIN(5180, 0),
2679 FREQ2FBIN(5220, 0),
2680 FREQ2FBIN(5320, 0),
2681 FREQ2FBIN(5400, 0),
2682 FREQ2FBIN(5500, 0),
2683 FREQ2FBIN(5600, 0),
2684 FREQ2FBIN(5700, 0),
2685 FREQ2FBIN(5785, 0)
2686 },
2687 .calPierData5G = {
2688 {
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 {0, 0, 0, 0, 0},
2696 {0, 0, 0, 0, 0},
2697 },
2698 {
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 {0, 0, 0, 0, 0},
2706 {0, 0, 0, 0, 0},
2707 },
2708 {
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 {0, 0, 0, 0, 0},
2713 {0, 0, 0, 0, 0},
2714 {0, 0, 0, 0, 0},
2715 {0, 0, 0, 0, 0},
2716 {0, 0, 0, 0, 0},
2717 },
2718
2719 },
2720 .calTarget_freqbin_5G = {
2721 FREQ2FBIN(5180, 0),
2722 FREQ2FBIN(5240, 0),
2723 FREQ2FBIN(5320, 0),
2724 FREQ2FBIN(5400, 0),
2725 FREQ2FBIN(5500, 0),
2726 FREQ2FBIN(5600, 0),
2727 FREQ2FBIN(5700, 0),
2728 FREQ2FBIN(5825, 0)
2729 },
2730 .calTarget_freqbin_5GHT20 = {
2731 FREQ2FBIN(5180, 0),
2732 FREQ2FBIN(5240, 0),
2733 FREQ2FBIN(5320, 0),
2734 FREQ2FBIN(5400, 0),
2735 FREQ2FBIN(5500, 0),
2736 FREQ2FBIN(5700, 0),
2737 FREQ2FBIN(5745, 0),
2738 FREQ2FBIN(5825, 0)
2739 },
2740 .calTarget_freqbin_5GHT40 = {
2741 FREQ2FBIN(5180, 0),
2742 FREQ2FBIN(5240, 0),
2743 FREQ2FBIN(5320, 0),
2744 FREQ2FBIN(5400, 0),
2745 FREQ2FBIN(5500, 0),
2746 FREQ2FBIN(5700, 0),
2747 FREQ2FBIN(5745, 0),
2748 FREQ2FBIN(5825, 0)
2749 },
2750 .calTargetPower5G = {
2751 /* 6-24,36,48,54 */
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2760 },
2761 .calTargetPower5GHT20 = {
2762 /*
2763 * 0_8_16,1-3_9-11_17-19,
2764 * 4,5,6,7,12,13,14,15,20,21,22,23
2765 */
2766 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2767 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2768 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2769 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2770 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2771 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2772 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2773 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2774 },
2775 .calTargetPower5GHT40 = {
2776 /*
2777 * 0_8_16,1-3_9-11_17-19,
2778 * 4,5,6,7,12,13,14,15,20,21,22,23
2779 */
2780 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2781 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2782 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2783 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2784 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2785 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2786 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2787 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2788 },
2789 .ctlIndex_5G = {
2790 0x10, 0x16, 0x18, 0x40, 0x46,
2791 0x48, 0x30, 0x36, 0x38
2792 },
2793 .ctl_freqbin_5G = {
2794 {
2795 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2797 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2798 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2799 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2800 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2802 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2803 },
2804 {
2805 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2807 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2808 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2809 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2810 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2812 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2813 },
2814
2815 {
2816 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2817 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2818 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2819 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2820 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2821 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2822 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2823 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2824 },
2825
2826 {
2827 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2829 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2830 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2831 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2832 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2833 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2834 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2835 },
2836
2837 {
2838 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2840 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2841 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2842 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2843 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2844 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2845 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2846 },
2847
2848 {
2849 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2850 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2851 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2852 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2853 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2854 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2855 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2856 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2857 },
2858
2859 {
2860 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2862 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2863 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2864 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2865 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2866 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2867 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2868 },
2869
2870 {
2871 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2872 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2873 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2874 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2875 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2876 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2877 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2878 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2879 },
2880
2881 {
2882 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2883 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2884 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2885 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2886 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2887 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2888 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2889 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2890 }
2891 },
2892 .ctlPowerData_5G = {
2893 {
2894 {
2895 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2896 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2897 }
2898 },
2899 {
2900 {
2901 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2902 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2903 }
2904 },
2905 {
2906 {
2907 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2908 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2909 }
2910 },
2911 {
2912 {
2913 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2914 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2915 }
2916 },
2917 {
2918 {
2919 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2920 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2921 }
2922 },
2923 {
2924 {
2925 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2926 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2927 }
2928 },
2929 {
2930 {
2931 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2932 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2933 }
2934 },
2935 {
2936 {
2937 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2938 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2939 }
2940 },
2941 {
2942 {
2943 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2944 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2945 }
2946 },
2947 }
2948};
2949
2950
2951static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2952 &ar9300_default,
2953 &ar9300_x112,
2954 &ar9300_h116,
2955 &ar9300_h112,
2956 &ar9300_x113,
2957};
2958
2959static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2960{
2961#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2962 int it;
2963
2964 for (it = 0; it < N_LOOP; it++)
2965 if (ar9300_eep_templates[it]->templateVersion == id)
2966 return ar9300_eep_templates[it];
2967 return NULL;
2968#undef N_LOOP
2969}
2970
2971
626static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 2972static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
627{ 2973{
628 if (fbin == AR9300_BCHAN_UNUSED) 2974 if (fbin == AR9300_BCHAN_UNUSED)
@@ -636,6 +2982,16 @@ static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
636 return 0; 2982 return 0;
637} 2983}
638 2984
2985static int interpolate(int x, int xa, int xb, int ya, int yb)
2986{
2987 int bf, factor, plus;
2988
2989 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2990 factor = bf / 2;
2991 plus = bf % 2;
2992 return ya + factor + plus;
2993}
2994
639static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, 2995static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
640 enum eeprom_param param) 2996 enum eeprom_param param)
641{ 2997{
@@ -748,6 +3104,36 @@ error:
748 return false; 3104 return false;
749} 3105}
750 3106
3107static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3108{
3109 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3110
3111 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3112 AR9300_OTP_STATUS_VALID, 1000))
3113 return false;
3114
3115 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3116 return true;
3117}
3118
3119static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3120 int count)
3121{
3122 u32 data;
3123 int i;
3124
3125 for (i = 0; i < count; i++) {
3126 int offset = 8 * ((address - i) % 4);
3127 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3128 return false;
3129
3130 buffer[i] = (data >> offset) & 0xff;
3131 }
3132
3133 return true;
3134}
3135
3136
751static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, 3137static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
752 int *length, int *major, int *minor) 3138 int *length, int *major, int *minor)
753{ 3139{
@@ -824,6 +3210,7 @@ static int ar9300_compress_decision(struct ath_hw *ah,
824{ 3210{
825 struct ath_common *common = ath9k_hw_common(ah); 3211 struct ath_common *common = ath9k_hw_common(ah);
826 u8 *dptr; 3212 u8 *dptr;
3213 const struct ar9300_eeprom *eep = NULL;
827 3214
828 switch (code) { 3215 switch (code) {
829 case _CompressNone: 3216 case _CompressNone:
@@ -841,13 +3228,14 @@ static int ar9300_compress_decision(struct ath_hw *ah,
841 if (reference == 0) { 3228 if (reference == 0) {
842 dptr = mptr; 3229 dptr = mptr;
843 } else { 3230 } else {
844 if (reference != 2) { 3231 eep = ar9003_eeprom_struct_find_by_id(reference);
3232 if (eep == NULL) {
845 ath_print(common, ATH_DBG_EEPROM, 3233 ath_print(common, ATH_DBG_EEPROM,
846 "cant find reference eeprom" 3234 "cant find reference eeprom"
847 "struct %d\n", reference); 3235 "struct %d\n", reference);
848 return -1; 3236 return -1;
849 } 3237 }
850 memcpy(mptr, &ar9300_default, mdata_size); 3238 memcpy(mptr, eep, mdata_size);
851 } 3239 }
852 ath_print(common, ATH_DBG_EEPROM, 3240 ath_print(common, ATH_DBG_EEPROM,
853 "restore eeprom %d: block, reference %d," 3241 "restore eeprom %d: block, reference %d,"
@@ -863,6 +3251,38 @@ static int ar9300_compress_decision(struct ath_hw *ah,
863 return 0; 3251 return 0;
864} 3252}
865 3253
3254typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3255 int count);
3256
3257static bool ar9300_check_header(void *data)
3258{
3259 u32 *word = data;
3260 return !(*word == 0 || *word == ~0);
3261}
3262
3263static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3264 int base_addr)
3265{
3266 u8 header[4];
3267
3268 if (!read(ah, base_addr, header, 4))
3269 return false;
3270
3271 return ar9300_check_header(header);
3272}
3273
3274static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3275 int mdata_size)
3276{
3277 struct ath_common *common = ath9k_hw_common(ah);
3278 u16 *data = (u16 *) mptr;
3279 int i;
3280
3281 for (i = 0; i < mdata_size / 2; i++, data++)
3282 ath9k_hw_nvram_read(common, i, data);
3283
3284 return 0;
3285}
866/* 3286/*
867 * Read the configuration data from the eeprom. 3287 * Read the configuration data from the eeprom.
868 * The data can be put in any specified memory buffer. 3288 * The data can be put in any specified memory buffer.
@@ -883,6 +3303,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
883 int it; 3303 int it;
884 u16 checksum, mchecksum; 3304 u16 checksum, mchecksum;
885 struct ath_common *common = ath9k_hw_common(ah); 3305 struct ath_common *common = ath9k_hw_common(ah);
3306 eeprom_read_op read;
3307
3308 if (ath9k_hw_use_flash(ah))
3309 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
886 3310
887 word = kzalloc(2048, GFP_KERNEL); 3311 word = kzalloc(2048, GFP_KERNEL);
888 if (!word) 3312 if (!word)
@@ -890,14 +3314,42 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
890 3314
891 memcpy(mptr, &ar9300_default, mdata_size); 3315 memcpy(mptr, &ar9300_default, mdata_size);
892 3316
3317 read = ar9300_read_eeprom;
3318 cptr = AR9300_BASE_ADDR;
3319 ath_print(common, ATH_DBG_EEPROM,
3320 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3321 if (ar9300_check_eeprom_header(ah, read, cptr))
3322 goto found;
3323
3324 cptr = AR9300_BASE_ADDR_512;
3325 ath_print(common, ATH_DBG_EEPROM,
3326 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3327 if (ar9300_check_eeprom_header(ah, read, cptr))
3328 goto found;
3329
3330 read = ar9300_read_otp;
893 cptr = AR9300_BASE_ADDR; 3331 cptr = AR9300_BASE_ADDR;
3332 ath_print(common, ATH_DBG_EEPROM,
3333 "Trying OTP accesss at Address 0x%04x\n", cptr);
3334 if (ar9300_check_eeprom_header(ah, read, cptr))
3335 goto found;
3336
3337 cptr = AR9300_BASE_ADDR_512;
3338 ath_print(common, ATH_DBG_EEPROM,
3339 "Trying OTP accesss at Address 0x%04x\n", cptr);
3340 if (ar9300_check_eeprom_header(ah, read, cptr))
3341 goto found;
3342
3343 goto fail;
3344
3345found:
3346 ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data");
3347
894 for (it = 0; it < MSTATE; it++) { 3348 for (it = 0; it < MSTATE; it++) {
895 if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN)) 3349 if (!read(ah, cptr, word, COMP_HDR_LEN))
896 goto fail; 3350 goto fail;
897 3351
898 if ((word[0] == 0 && word[1] == 0 && word[2] == 0 && 3352 if (!ar9300_check_header(word))
899 word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
900 && word[2] == 0xff && word[3] == 0xff))
901 break; 3353 break;
902 3354
903 ar9300_comp_hdr_unpack(word, &code, &reference, 3355 ar9300_comp_hdr_unpack(word, &code, &reference,
@@ -914,8 +3366,7 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
914 } 3366 }
915 3367
916 osize = length; 3368 osize = length;
917 ar9300_read_eeprom(ah, cptr, word, 3369 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
918 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
919 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); 3370 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
920 mchecksum = word[COMP_HDR_LEN + osize] | 3371 mchecksum = word[COMP_HDR_LEN + osize] |
921 (word[COMP_HDR_LEN + osize + 1] << 8); 3372 (word[COMP_HDR_LEN + osize + 1] << 8);
@@ -992,9 +3443,9 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
992static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 3443static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
993{ 3444{
994 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); 3445 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
995 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3)); 3446 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
996 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE, 3447 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
997 ((bias >> 2) & 0x3)); 3448 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
998} 3449}
999 3450
1000static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) 3451static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@ -1097,6 +3548,82 @@ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
1097 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); 3548 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
1098} 3549}
1099 3550
3551static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3552 struct ath9k_channel *chan)
3553{
3554 int f[3], t[3];
3555 u16 value;
3556 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3557
3558 if (chain >= 0 && chain < 3) {
3559 if (IS_CHAN_2GHZ(chan))
3560 return eep->modalHeader2G.xatten1DB[chain];
3561 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3562 t[0] = eep->base_ext2.xatten1DBLow[chain];
3563 f[0] = 5180;
3564 t[1] = eep->modalHeader5G.xatten1DB[chain];
3565 f[1] = 5500;
3566 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3567 f[2] = 5785;
3568 value = ar9003_hw_power_interpolate((s32) chan->channel,
3569 f, t, 3);
3570 return value;
3571 } else
3572 return eep->modalHeader5G.xatten1DB[chain];
3573 }
3574
3575 return 0;
3576}
3577
3578
3579static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3580 struct ath9k_channel *chan)
3581{
3582 int f[3], t[3];
3583 u16 value;
3584 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3585
3586 if (chain >= 0 && chain < 3) {
3587 if (IS_CHAN_2GHZ(chan))
3588 return eep->modalHeader2G.xatten1Margin[chain];
3589 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3590 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3591 f[0] = 5180;
3592 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3593 f[1] = 5500;
3594 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3595 f[2] = 5785;
3596 value = ar9003_hw_power_interpolate((s32) chan->channel,
3597 f, t, 3);
3598 return value;
3599 } else
3600 return eep->modalHeader5G.xatten1Margin[chain];
3601 }
3602
3603 return 0;
3604}
3605
3606static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3607{
3608 int i;
3609 u16 value;
3610 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3611 AR_PHY_EXT_ATTEN_CTL_1,
3612 AR_PHY_EXT_ATTEN_CTL_2,
3613 };
3614
3615 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3616 for (i = 0; i < 3; i++) {
3617 value = ar9003_hw_atten_chain_get(ah, i, chan);
3618 REG_RMW_FIELD(ah, ext_atten_reg[i],
3619 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3620
3621 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3622 REG_RMW_FIELD(ah, ext_atten_reg[i],
3623 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3624 }
3625}
3626
1100static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 3627static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
1101{ 3628{
1102 int internal_regulator = 3629 int internal_regulator =
@@ -1128,6 +3655,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
1128 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); 3655 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
1129 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); 3656 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
1130 ar9003_hw_drive_strength_apply(ah); 3657 ar9003_hw_drive_strength_apply(ah);
3658 ar9003_hw_atten_apply(ah, chan);
1131 ar9003_hw_internal_regulator_apply(ah); 3659 ar9003_hw_internal_regulator_apply(ah);
1132} 3660}
1133 3661
@@ -1189,7 +3717,7 @@ static int ar9003_hw_power_interpolate(int32_t x,
1189 if (hx == lx) 3717 if (hx == lx)
1190 y = ly; 3718 y = ly;
1191 else /* interpolate */ 3719 else /* interpolate */
1192 y = ly + (((x - lx) * (hy - ly)) / (hx - lx)); 3720 y = interpolate(x, lx, hx, ly, hy);
1193 } else /* only low is good, use it */ 3721 } else /* only low is good, use it */
1194 y = ly; 3722 y = ly;
1195 } else if (hhave) /* only high is good, use it */ 3723 } else if (hhave) /* only high is good, use it */
@@ -1637,6 +4165,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
1637{ 4165{
1638 int tempSlope = 0; 4166 int tempSlope = 0;
1639 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4167 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4168 int f[3], t[3];
1640 4169
1641 REG_RMW(ah, AR_PHY_TPC_11_B0, 4170 REG_RMW(ah, AR_PHY_TPC_11_B0,
1642 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4171 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
@@ -1665,7 +4194,16 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
1665 */ 4194 */
1666 if (frequency < 4000) 4195 if (frequency < 4000)
1667 tempSlope = eep->modalHeader2G.tempSlope; 4196 tempSlope = eep->modalHeader2G.tempSlope;
1668 else 4197 else if (eep->base_ext2.tempSlopeLow != 0) {
4198 t[0] = eep->base_ext2.tempSlopeLow;
4199 f[0] = 5180;
4200 t[1] = eep->modalHeader5G.tempSlope;
4201 f[1] = 5500;
4202 t[2] = eep->base_ext2.tempSlopeHigh;
4203 f[2] = 5785;
4204 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4205 f, t, 3);
4206 } else
1669 tempSlope = eep->modalHeader5G.tempSlope; 4207 tempSlope = eep->modalHeader5G.tempSlope;
1670 4208
1671 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); 4209 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
@@ -1769,25 +4307,23 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
1769 /* so is the high frequency, interpolate */ 4307 /* so is the high frequency, interpolate */
1770 if (hfrequency[ichain] - frequency < 1000) { 4308 if (hfrequency[ichain] - frequency < 1000) {
1771 4309
1772 correction[ichain] = lcorrection[ichain] + 4310 correction[ichain] = interpolate(frequency,
1773 (((frequency - lfrequency[ichain]) * 4311 lfrequency[ichain],
1774 (hcorrection[ichain] - 4312 hfrequency[ichain],
1775 lcorrection[ichain])) / 4313 lcorrection[ichain],
1776 (hfrequency[ichain] - lfrequency[ichain])); 4314 hcorrection[ichain]);
1777 4315
1778 temperature[ichain] = ltemperature[ichain] + 4316 temperature[ichain] = interpolate(frequency,
1779 (((frequency - lfrequency[ichain]) * 4317 lfrequency[ichain],
1780 (htemperature[ichain] - 4318 hfrequency[ichain],
1781 ltemperature[ichain])) / 4319 ltemperature[ichain],
1782 (hfrequency[ichain] - lfrequency[ichain])); 4320 htemperature[ichain]);
1783 4321
1784 voltage[ichain] = 4322 voltage[ichain] = interpolate(frequency,
1785 lvoltage[ichain] + 4323 lfrequency[ichain],
1786 (((frequency - 4324 hfrequency[ichain],
1787 lfrequency[ichain]) * (hvoltage[ichain] - 4325 lvoltage[ichain],
1788 lvoltage[ichain])) 4326 hvoltage[ichain]);
1789 / (hfrequency[ichain] -
1790 lfrequency[ichain]));
1791 } 4327 }
1792 /* only low is good, use it */ 4328 /* only low is good, use it */
1793 else { 4329 else {
@@ -1919,14 +4455,16 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
1919 int i; 4455 int i;
1920 int16_t twiceLargestAntenna; 4456 int16_t twiceLargestAntenna;
1921 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 4457 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1922 u16 ctlModesFor11a[] = { 4458 static const u16 ctlModesFor11a[] = {
1923 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 4459 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1924 }; 4460 };
1925 u16 ctlModesFor11g[] = { 4461 static const u16 ctlModesFor11g[] = {
1926 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, 4462 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
1927 CTL_11G_EXT, CTL_2GHT40 4463 CTL_11G_EXT, CTL_2GHT40
1928 }; 4464 };
1929 u16 numCtlModes, *pCtlMode, ctlMode, freq; 4465 u16 numCtlModes;
4466 const u16 *pCtlMode;
4467 u16 ctlMode, freq;
1930 struct chan_centers centers; 4468 struct chan_centers centers;
1931 u8 *ctlIndex; 4469 u8 *ctlIndex;
1932 u8 ctlNum; 4470 u8 ctlNum;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 3c533bb983c..57f64dbbcd8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -79,6 +79,15 @@
79#define FIXED_CCA_THRESHOLD 15 79#define FIXED_CCA_THRESHOLD 15
80 80
81#define AR9300_BASE_ADDR 0x3ff 81#define AR9300_BASE_ADDR 0x3ff
82#define AR9300_BASE_ADDR_512 0x1ff
83
84#define AR9300_OTP_BASE 0x14000
85#define AR9300_OTP_STATUS 0x15f18
86#define AR9300_OTP_STATUS_TYPE 0x7
87#define AR9300_OTP_STATUS_VALID 0x4
88#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
89#define AR9300_OTP_STATUS_SM_BUSY 0x1
90#define AR9300_OTP_READ_DATA 0x15f1c
82 91
83enum targetPowerHTRates { 92enum targetPowerHTRates {
84 HT_TARGET_RATE_0_8_16, 93 HT_TARGET_RATE_0_8_16,
@@ -236,7 +245,7 @@ struct ar9300_modal_eep_header {
236 u8 thresh62; 245 u8 thresh62;
237 __le32 papdRateMaskHt20; 246 __le32 papdRateMaskHt20;
238 __le32 papdRateMaskHt40; 247 __le32 papdRateMaskHt40;
239 u8 futureModal[24]; 248 u8 futureModal[10];
240} __packed; 249} __packed;
241 250
242struct ar9300_cal_data_per_freq_op_loop { 251struct ar9300_cal_data_per_freq_op_loop {
@@ -274,6 +283,20 @@ struct cal_ctl_data_5g {
274 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G]; 283 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
275} __packed; 284} __packed;
276 285
286struct ar9300_BaseExtension_1 {
287 u8 ant_div_control;
288 u8 future[13];
289} __packed;
290
291struct ar9300_BaseExtension_2 {
292 int8_t tempSlopeLow;
293 int8_t tempSlopeHigh;
294 u8 xatten1DBLow[AR9300_MAX_CHAINS];
295 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
296 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
297 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
298} __packed;
299
277struct ar9300_eeprom { 300struct ar9300_eeprom {
278 u8 eepromVersion; 301 u8 eepromVersion;
279 u8 templateVersion; 302 u8 templateVersion;
@@ -283,6 +306,7 @@ struct ar9300_eeprom {
283 struct ar9300_base_eep_hdr baseEepHeader; 306 struct ar9300_base_eep_hdr baseEepHeader;
284 307
285 struct ar9300_modal_eep_header modalHeader2G; 308 struct ar9300_modal_eep_header modalHeader2G;
309 struct ar9300_BaseExtension_1 base_ext1;
286 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 310 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
287 struct ar9300_cal_data_per_freq_op_loop 311 struct ar9300_cal_data_per_freq_op_loop
288 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 312 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
@@ -302,6 +326,7 @@ struct ar9300_eeprom {
302 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; 326 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
303 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; 327 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
304 struct ar9300_modal_eep_header modalHeader5G; 328 struct ar9300_modal_eep_header modalHeader5G;
329 struct ar9300_BaseExtension_2 base_ext2;
305 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 330 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
306 struct ar9300_cal_data_per_freq_op_loop 331 struct ar9300_cal_data_per_freq_op_loop
307 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 332 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 10c812e353a..f5896aa3000 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -410,12 +410,36 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
410static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 410static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
411 u32 aggrLen) 411 u32 aggrLen)
412{ 412{
413#define FIRST_DESC_NDELIMS 60
413 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 414 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
414 415
415 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 416 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
416 417
417 ads->ctl17 &= ~AR_AggrLen; 418 if (ah->ent_mode & AR_ENT_OTP_MPSD) {
418 ads->ctl17 |= SM(aggrLen, AR_AggrLen); 419 u32 ctl17, ndelim;
420 /*
421 * Add delimiter when using RTS/CTS with aggregation
422 * and non enterprise AR9003 card
423 */
424 ctl17 = ads->ctl17;
425 ndelim = MS(ctl17, AR_PadDelim);
426
427 if (ndelim < FIRST_DESC_NDELIMS) {
428 aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
429 ndelim = FIRST_DESC_NDELIMS;
430 }
431
432 ctl17 &= ~AR_AggrLen;
433 ctl17 |= SM(aggrLen, AR_AggrLen);
434
435 ctl17 &= ~AR_PadDelim;
436 ctl17 |= SM(ndelim, AR_PadDelim);
437
438 ads->ctl17 = ctl17;
439 } else {
440 ads->ctl17 &= ~AR_AggrLen;
441 ads->ctl17 |= SM(aggrLen, AR_AggrLen);
442 }
419} 443}
420 444
421static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 445static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 716db414c25..850bc9866c1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -32,12 +32,12 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
32{ 32{
33 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 33 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
34 struct ar9300_modal_eep_header *hdr; 34 struct ar9300_modal_eep_header *hdr;
35 const u32 ctrl0[3] = { 35 static const u32 ctrl0[3] = {
36 AR_PHY_PAPRD_CTRL0_B0, 36 AR_PHY_PAPRD_CTRL0_B0,
37 AR_PHY_PAPRD_CTRL0_B1, 37 AR_PHY_PAPRD_CTRL0_B1,
38 AR_PHY_PAPRD_CTRL0_B2 38 AR_PHY_PAPRD_CTRL0_B2
39 }; 39 };
40 const u32 ctrl1[3] = { 40 static const u32 ctrl1[3] = {
41 AR_PHY_PAPRD_CTRL1_B0, 41 AR_PHY_PAPRD_CTRL1_B0,
42 AR_PHY_PAPRD_CTRL1_B1, 42 AR_PHY_PAPRD_CTRL1_B1,
43 AR_PHY_PAPRD_CTRL1_B2 43 AR_PHY_PAPRD_CTRL1_B2
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 44c5454b2ad..656d8ce251a 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -128,7 +128,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
128static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 128static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
129 struct ath9k_channel *chan) 129 struct ath9k_channel *chan)
130{ 130{
131 u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 131 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
132 int cur_bb_spur, negative = 0, cck_spur_freq; 132 int cur_bb_spur, negative = 0, cck_spur_freq;
133 int i; 133 int i;
134 134
@@ -1113,10 +1113,55 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1113 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1113 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1114} 1114}
1115 1115
1116static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1117 struct ath_hw_radar_conf *conf)
1118{
1119 u32 radar_0 = 0, radar_1 = 0;
1120
1121 if (!conf) {
1122 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1123 return;
1124 }
1125
1126 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1127 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1128 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1129 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1130 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1131 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1132
1133 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1134 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1135 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1136 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1137 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1138
1139 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1140 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1141 if (conf->ext_channel)
1142 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1143 else
1144 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1145}
1146
1147static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1148{
1149 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1150
1151 conf->fir_power = -28;
1152 conf->radar_rssi = 0;
1153 conf->pulse_height = 10;
1154 conf->pulse_rssi = 24;
1155 conf->pulse_inband = 8;
1156 conf->pulse_maxlen = 255;
1157 conf->pulse_inband_step = 12;
1158 conf->radar_inband = 8;
1159}
1160
1116void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1161void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1117{ 1162{
1118 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1163 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1119 const u32 ar9300_cca_regs[6] = { 1164 static const u32 ar9300_cca_regs[6] = {
1120 AR_PHY_CCA_0, 1165 AR_PHY_CCA_0,
1121 AR_PHY_CCA_1, 1166 AR_PHY_CCA_1,
1122 AR_PHY_CCA_2, 1167 AR_PHY_CCA_2,
@@ -1141,8 +1186,10 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1141 priv_ops->ani_control = ar9003_hw_ani_control; 1186 priv_ops->ani_control = ar9003_hw_ani_control;
1142 priv_ops->do_getnf = ar9003_hw_do_getnf; 1187 priv_ops->do_getnf = ar9003_hw_do_getnf;
1143 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1188 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1189 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1144 1190
1145 ar9003_hw_set_nf_limits(ah); 1191 ar9003_hw_set_nf_limits(ah);
1192 ar9003_hw_set_radar_conf(ah);
1146 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1193 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1147} 1194}
1148 1195
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index b3180935875..6f90acc5cca 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -86,33 +86,19 @@ struct ath_config {
86/** 86/**
87 * enum buffer_type - Buffer type flags 87 * enum buffer_type - Buffer type flags
88 * 88 *
89 * @BUF_HT: Send this buffer using HT capabilities
90 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
91 * @BUF_AGGR: Indicates whether the buffer can be aggregated 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
92 * (used in aggregation scheduling) 91 * (used in aggregation scheduling)
93 * @BUF_RETRY: Indicates whether the buffer is retried
94 * @BUF_XRETRY: To denote excessive retries of the buffer 92 * @BUF_XRETRY: To denote excessive retries of the buffer
95 */ 93 */
96enum buffer_type { 94enum buffer_type {
97 BUF_HT = BIT(1),
98 BUF_AMPDU = BIT(2), 95 BUF_AMPDU = BIT(2),
99 BUF_AGGR = BIT(3), 96 BUF_AGGR = BIT(3),
100 BUF_RETRY = BIT(4),
101 BUF_XRETRY = BIT(5), 97 BUF_XRETRY = BIT(5),
102}; 98};
103 99
104#define bf_nframes bf_state.bfs_nframes
105#define bf_al bf_state.bfs_al
106#define bf_frmlen bf_state.bfs_frmlen
107#define bf_retries bf_state.bfs_retries
108#define bf_seqno bf_state.bfs_seqno
109#define bf_tidno bf_state.bfs_tidno
110#define bf_keyix bf_state.bfs_keyix
111#define bf_keytype bf_state.bfs_keytype
112#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
113#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 100#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
114#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 101#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
115#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
116#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 102#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
117 103
118#define ATH_TXSTATUS_RING_SIZE 64 104#define ATH_TXSTATUS_RING_SIZE 64
@@ -177,8 +163,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
177 163
178/* returns delimiter padding required given the packet length */ 164/* returns delimiter padding required given the packet length */
179#define ATH_AGGR_GET_NDELIM(_len) \ 165#define ATH_AGGR_GET_NDELIM(_len) \
180 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ 166 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
181 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) 167 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
182 168
183#define BAW_WITHIN(_start, _bawsz, _seqno) \ 169#define BAW_WITHIN(_start, _bawsz, _seqno) \
184 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 170 ((((_seqno) - (_start)) & 4095) < (_bawsz))
@@ -217,18 +203,18 @@ struct ath_atx_ac {
217 struct list_head tid_q; 203 struct list_head tid_q;
218}; 204};
219 205
206struct ath_frame_info {
207 int framelen;
208 u32 keyix;
209 enum ath9k_key_type keytype;
210 u8 retries;
211 u16 seqno;
212};
213
220struct ath_buf_state { 214struct ath_buf_state {
221 int bfs_nframes;
222 u16 bfs_al;
223 u16 bfs_frmlen;
224 int bfs_seqno;
225 int bfs_tidno;
226 int bfs_retries;
227 u8 bf_type; 215 u8 bf_type;
228 u8 bfs_paprd; 216 u8 bfs_paprd;
229 unsigned long bfs_paprd_timestamp; 217 enum ath9k_internal_frame_type bfs_ftype;
230 u32 bfs_keyix;
231 enum ath9k_key_type bfs_keytype;
232}; 218};
233 219
234struct ath_buf { 220struct ath_buf {
@@ -241,7 +227,6 @@ struct ath_buf {
241 dma_addr_t bf_daddr; /* physical addr of desc */ 227 dma_addr_t bf_daddr; /* physical addr of desc */
242 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 228 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
243 bool bf_stale; 229 bool bf_stale;
244 bool bf_tx_aborted;
245 u16 bf_flags; 230 u16 bf_flags;
246 struct ath_buf_state bf_state; 231 struct ath_buf_state bf_state;
247 struct ath_wiphy *aphy; 232 struct ath_wiphy *aphy;
@@ -278,6 +263,7 @@ struct ath_node {
278 263
279struct ath_tx_control { 264struct ath_tx_control {
280 struct ath_txq *txq; 265 struct ath_txq *txq;
266 struct ath_node *an;
281 int if_id; 267 int if_id;
282 enum ath9k_internal_frame_type frame_type; 268 enum ath9k_internal_frame_type frame_type;
283 u8 paprd; 269 u8 paprd;
@@ -338,7 +324,6 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
338 struct ath_tx_control *txctl); 324 struct ath_tx_control *txctl);
339void ath_tx_tasklet(struct ath_softc *sc); 325void ath_tx_tasklet(struct ath_softc *sc);
340void ath_tx_edma_tasklet(struct ath_softc *sc); 326void ath_tx_edma_tasklet(struct ath_softc *sc);
341void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
342int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 327int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
343 u16 tid, u16 *ssn); 328 u16 tid, u16 *ssn);
344void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 329void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
@@ -603,6 +588,7 @@ struct ath_softc {
603 struct work_struct paprd_work; 588 struct work_struct paprd_work;
604 struct work_struct hw_check_work; 589 struct work_struct hw_check_work;
605 struct completion paprd_complete; 590 struct completion paprd_complete;
591 bool paprd_pending;
606 592
607 u32 intrstatus; 593 u32 intrstatus;
608 u32 sc_flags; /* SC_OP_* */ 594 u32 sc_flags; /* SC_OP_* */
@@ -712,7 +698,7 @@ void ath9k_ps_restore(struct ath_softc *sc);
712void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 698void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
713int ath9k_wiphy_add(struct ath_softc *sc); 699int ath9k_wiphy_add(struct ath_softc *sc);
714int ath9k_wiphy_del(struct ath_wiphy *aphy); 700int ath9k_wiphy_del(struct ath_wiphy *aphy);
715void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); 701void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
716int ath9k_wiphy_pause(struct ath_wiphy *aphy); 702int ath9k_wiphy_pause(struct ath_wiphy *aphy);
717int ath9k_wiphy_unpause(struct ath_wiphy *aphy); 703int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
718int ath9k_wiphy_select(struct ath_wiphy *aphy); 704int ath9k_wiphy_select(struct ath_wiphy *aphy);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 2377376c8d4..30724a4e8bb 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -109,6 +109,25 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
109 series, 4, 0); 109 series, 4, 0);
110} 110}
111 111
112static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
113{
114 struct ath_wiphy *aphy = hw->priv;
115 struct ath_softc *sc = aphy->sc;
116 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
117 struct ath_tx_control txctl;
118
119 memset(&txctl, 0, sizeof(struct ath_tx_control));
120 txctl.txq = sc->beacon.cabq;
121
122 ath_print(common, ATH_DBG_XMIT,
123 "transmitting CABQ packet, skb: %p\n", skb);
124
125 if (ath_tx_start(hw, skb, &txctl) != 0) {
126 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
127 dev_kfree_skb_any(skb);
128 }
129}
130
112static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, 131static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
113 struct ieee80211_vif *vif) 132 struct ieee80211_vif *vif)
114{ 133{
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index c40c534c666..c2481b3ac7e 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -534,7 +534,9 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
534 u16 twiceMinEdgePower; 534 u16 twiceMinEdgePower;
535 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 535 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
536 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 536 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
537 u16 numCtlModes, *pCtlMode, ctlMode, freq; 537 u16 numCtlModes;
538 const u16 *pCtlMode;
539 u16 ctlMode, freq;
538 struct chan_centers centers; 540 struct chan_centers centers;
539 struct cal_ctl_data_4k *rep; 541 struct cal_ctl_data_4k *rep;
540 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 542 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
@@ -550,10 +552,10 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
550 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 552 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
551 0, {0, 0, 0, 0} 553 0, {0, 0, 0, 0}
552 }; 554 };
553 u16 ctlModesFor11g[] = 555 static const u16 ctlModesFor11g[] = {
554 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, 556 CTL_11B, CTL_11G, CTL_2GHT20,
555 CTL_2GHT40 557 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
556 }; 558 };
557 559
558 ath9k_hw_get_channel_centers(ah, chan, &centers); 560 ath9k_hw_get_channel_centers(ah, chan, &centers);
559 561
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 3ad1de253c8..bcb9ed39c04 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -37,10 +37,10 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
37 int addr, eep_start_loc; 37 int addr, eep_start_loc;
38 eep_data = (u16 *)eep; 38 eep_data = (u16 *)eep;
39 39
40 if (AR9287_HTC_DEVID(ah)) 40 if (!common->driver_info)
41 eep_start_loc = AR9287_HTC_EEP_START_LOC;
42 else
43 eep_start_loc = AR9287_EEP_START_LOC; 41 eep_start_loc = AR9287_EEP_START_LOC;
42 else
43 eep_start_loc = AR9287_HTC_EEP_START_LOC;
44 44
45 if (!ath9k_hw_use_flash(ah)) { 45 if (!ath9k_hw_use_flash(ah)) {
46 ath_print(common, ATH_DBG_EEPROM, 46 ath_print(common, ATH_DBG_EEPROM,
@@ -626,13 +626,13 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
626 struct cal_target_power_ht targetPowerHt20, 626 struct cal_target_power_ht targetPowerHt20,
627 targetPowerHt40 = {0, {0, 0, 0, 0} }; 627 targetPowerHt40 = {0, {0, 0, 0, 0} };
628 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 628 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
629 u16 ctlModesFor11g[] = {CTL_11B, 629 static const u16 ctlModesFor11g[] = {
630 CTL_11G, 630 CTL_11B, CTL_11G, CTL_2GHT20,
631 CTL_2GHT20, 631 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
632 CTL_11B_EXT, 632 };
633 CTL_11G_EXT, 633 u16 numCtlModes = 0;
634 CTL_2GHT40}; 634 const u16 *pCtlMode = NULL;
635 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq; 635 u16 ctlMode, freq;
636 struct chan_centers centers; 636 struct chan_centers centers;
637 int tx_chainmask; 637 int tx_chainmask;
638 u16 twiceMinEdgePower; 638 u16 twiceMinEdgePower;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index a819ddc9fdb..e94216e1e10 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -1021,13 +1021,16 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1021 0, {0, 0, 0, 0} 1021 0, {0, 0, 0, 0}
1022 }; 1022 };
1023 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 1023 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1024 u16 ctlModesFor11a[] = 1024 static const u16 ctlModesFor11a[] = {
1025 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; 1025 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1026 u16 ctlModesFor11g[] = 1026 };
1027 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, 1027 static const u16 ctlModesFor11g[] = {
1028 CTL_2GHT40 1028 CTL_11B, CTL_11G, CTL_2GHT20,
1029 }; 1029 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1030 u16 numCtlModes, *pCtlMode, ctlMode, freq; 1030 };
1031 u16 numCtlModes;
1032 const u16 *pCtlMode;
1033 u16 ctlMode, freq;
1031 struct chan_centers centers; 1034 struct chan_centers centers;
1032 int tx_chainmask; 1035 int tx_chainmask;
1033 u16 twiceMinEdgePower; 1036 u16 twiceMinEdgePower;
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index dfb6560dab9..ae842dbf9b5 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -28,10 +28,16 @@ MODULE_FIRMWARE(FIRMWARE_AR9271);
28static struct usb_device_id ath9k_hif_usb_ids[] = { 28static struct usb_device_id ath9k_hif_usb_ids[] = {
29 { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */ 29 { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */
30 { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */ 30 { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */
31 { USB_DEVICE(0x0cf3, 0x7010) }, /* Atheros */ 31 { USB_DEVICE(0x0cf3, 0x7010),
32 { USB_DEVICE(0x0cf3, 0x7015) }, /* Atheros */ 32 .driver_info = AR7010_DEVICE },
33 /* Atheros */
34 { USB_DEVICE(0x0cf3, 0x7015),
35 .driver_info = AR7010_DEVICE | AR9287_DEVICE },
36 /* Atheros */
33 { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */ 37 { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */
34 { USB_DEVICE(0x0846, 0x9018) }, /* Netgear WNDA3200 */ 38 { USB_DEVICE(0x0846, 0x9018),
39 .driver_info = AR7010_DEVICE },
40 /* Netgear WNDA3200 */
35 { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */ 41 { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */
36 { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */ 42 { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */
37 { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */ 43 { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */
@@ -40,9 +46,13 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
40 { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */ 46 { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */
41 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */ 47 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
42 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */ 48 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
43 { USB_DEVICE(0x083A, 0xA704) }, /* SMC Networks */ 49 { USB_DEVICE(0x083A, 0xA704),
50 .driver_info = AR7010_DEVICE },
51 /* SMC Networks */
44 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */ 52 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
45 { USB_DEVICE(0x1668, 0x1200) }, /* Verizon */ 53 { USB_DEVICE(0x1668, 0x1200),
54 .driver_info = AR7010_DEVICE | AR9287_DEVICE },
55 /* Verizon */
46 { }, 56 { },
47}; 57};
48 58
@@ -776,7 +786,8 @@ static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
776 ath9k_hif_usb_dealloc_rx_urbs(hif_dev); 786 ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
777} 787}
778 788
779static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev) 789static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
790 u32 drv_info)
780{ 791{
781 int transfer, err; 792 int transfer, err;
782 const void *data = hif_dev->firmware->data; 793 const void *data = hif_dev->firmware->data;
@@ -807,18 +818,10 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
807 } 818 }
808 kfree(buf); 819 kfree(buf);
809 820
810 switch (hif_dev->device_id) { 821 if (drv_info & AR7010_DEVICE)
811 case 0x7010:
812 case 0x7015:
813 case 0x9018:
814 case 0xA704:
815 case 0x1200:
816 firm_offset = AR7010_FIRMWARE_TEXT; 822 firm_offset = AR7010_FIRMWARE_TEXT;
817 break; 823 else
818 default:
819 firm_offset = AR9271_FIRMWARE_TEXT; 824 firm_offset = AR9271_FIRMWARE_TEXT;
820 break;
821 }
822 825
823 /* 826 /*
824 * Issue FW download complete command to firmware. 827 * Issue FW download complete command to firmware.
@@ -836,7 +839,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
836 return 0; 839 return 0;
837} 840}
838 841
839static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev) 842static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
840{ 843{
841 int ret, idx; 844 int ret, idx;
842 struct usb_host_interface *alt = &hif_dev->interface->altsetting[0]; 845 struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
@@ -852,7 +855,7 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
852 } 855 }
853 856
854 /* Download firmware */ 857 /* Download firmware */
855 ret = ath9k_hif_usb_download_fw(hif_dev); 858 ret = ath9k_hif_usb_download_fw(hif_dev, drv_info);
856 if (ret) { 859 if (ret) {
857 dev_err(&hif_dev->udev->dev, 860 dev_err(&hif_dev->udev->dev,
858 "ath9k_htc: Firmware - %s download failed\n", 861 "ath9k_htc: Firmware - %s download failed\n",
@@ -931,23 +934,15 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
931 934
932 /* Find out which firmware to load */ 935 /* Find out which firmware to load */
933 936
934 switch(hif_dev->device_id) { 937 if (id->driver_info & AR7010_DEVICE)
935 case 0x7010:
936 case 0x7015:
937 case 0x9018:
938 case 0xA704:
939 case 0x1200:
940 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202) 938 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202)
941 hif_dev->fw_name = FIRMWARE_AR7010_1_1; 939 hif_dev->fw_name = FIRMWARE_AR7010_1_1;
942 else 940 else
943 hif_dev->fw_name = FIRMWARE_AR7010; 941 hif_dev->fw_name = FIRMWARE_AR7010;
944 break; 942 else
945 default:
946 hif_dev->fw_name = FIRMWARE_AR9271; 943 hif_dev->fw_name = FIRMWARE_AR9271;
947 break;
948 }
949 944
950 ret = ath9k_hif_usb_dev_init(hif_dev); 945 ret = ath9k_hif_usb_dev_init(hif_dev, id->driver_info);
951 if (ret) { 946 if (ret) {
952 ret = -EINVAL; 947 ret = -EINVAL;
953 goto err_hif_init_usb; 948 goto err_hif_init_usb;
@@ -955,7 +950,7 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
955 950
956 ret = ath9k_htc_hw_init(hif_dev->htc_handle, 951 ret = ath9k_htc_hw_init(hif_dev->htc_handle,
957 &hif_dev->udev->dev, hif_dev->device_id, 952 &hif_dev->udev->dev, hif_dev->device_id,
958 hif_dev->udev->product); 953 hif_dev->udev->product, id->driver_info);
959 if (ret) { 954 if (ret) {
960 ret = -EINVAL; 955 ret = -EINVAL;
961 goto err_htc_hw_init; 956 goto err_htc_hw_init;
@@ -1033,6 +1028,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
1033{ 1028{
1034 struct hif_device_usb *hif_dev = 1029 struct hif_device_usb *hif_dev =
1035 (struct hif_device_usb *) usb_get_intfdata(interface); 1030 (struct hif_device_usb *) usb_get_intfdata(interface);
1031 struct htc_target *htc_handle = hif_dev->htc_handle;
1036 int ret; 1032 int ret;
1037 1033
1038 ret = ath9k_hif_usb_alloc_urbs(hif_dev); 1034 ret = ath9k_hif_usb_alloc_urbs(hif_dev);
@@ -1040,7 +1036,8 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
1040 return ret; 1036 return ret;
1041 1037
1042 if (hif_dev->firmware) { 1038 if (hif_dev->firmware) {
1043 ret = ath9k_hif_usb_download_fw(hif_dev); 1039 ret = ath9k_hif_usb_download_fw(hif_dev,
1040 htc_handle->drv_priv->ah->common.driver_info);
1044 if (ret) 1041 if (ret)
1045 goto fail_resume; 1042 goto fail_resume;
1046 } else { 1043 } else {
@@ -1050,7 +1047,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
1050 1047
1051 mdelay(100); 1048 mdelay(100);
1052 1049
1053 ret = ath9k_htc_resume(hif_dev->htc_handle); 1050 ret = ath9k_htc_resume(htc_handle);
1054 1051
1055 if (ret) 1052 if (ret)
1056 goto fail_resume; 1053 goto fail_resume;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 75ecf6a30d2..afe39a91190 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -368,7 +368,7 @@ struct ath9k_htc_priv {
368 u16 seq_no; 368 u16 seq_no;
369 u32 bmiss_cnt; 369 u32 bmiss_cnt;
370 370
371 struct ath9k_hw_cal_data caldata[38]; 371 struct ath9k_hw_cal_data caldata[ATH9K_NUM_CHANNELS];
372 372
373 spinlock_t beacon_lock; 373 spinlock_t beacon_lock;
374 374
@@ -461,7 +461,7 @@ void ath9k_init_leds(struct ath9k_htc_priv *priv);
461void ath9k_deinit_leds(struct ath9k_htc_priv *priv); 461void ath9k_deinit_leds(struct ath9k_htc_priv *priv);
462 462
463int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 463int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
464 u16 devid, char *product); 464 u16 devid, char *product, u32 drv_info);
465void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug); 465void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug);
466#ifdef CONFIG_PM 466#ifdef CONFIG_PM
467int ath9k_htc_resume(struct htc_target *htc_handle); 467int ath9k_htc_resume(struct htc_target *htc_handle);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 7c8a38d0456..071d0c97474 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -181,7 +181,8 @@ static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
181 return htc_connect_service(priv->htc, &req, ep_id); 181 return htc_connect_service(priv->htc, &req, ep_id);
182} 182}
183 183
184static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid) 184static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
185 u32 drv_info)
185{ 186{
186 int ret; 187 int ret;
187 188
@@ -245,17 +246,10 @@ static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
245 * the HIF layer, shouldn't matter much. 246 * the HIF layer, shouldn't matter much.
246 */ 247 */
247 248
248 switch(devid) { 249 if (drv_info & AR7010_DEVICE)
249 case 0x7010:
250 case 0x7015:
251 case 0x9018:
252 case 0xA704:
253 case 0x1200:
254 priv->htc->credits = 45; 250 priv->htc->credits = 45;
255 break; 251 else
256 default:
257 priv->htc->credits = 33; 252 priv->htc->credits = 33;
258 }
259 253
260 ret = htc_init(priv->htc); 254 ret = htc_init(priv->htc);
261 if (ret) 255 if (ret)
@@ -308,7 +302,7 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
308 struct ath_hw *ah = (struct ath_hw *) hw_priv; 302 struct ath_hw *ah = (struct ath_hw *) hw_priv;
309 struct ath_common *common = ath9k_hw_common(ah); 303 struct ath_common *common = ath9k_hw_common(ah);
310 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 304 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
311 __be32 buf[2] = { 305 const __be32 buf[2] = {
312 cpu_to_be32(reg_offset), 306 cpu_to_be32(reg_offset),
313 cpu_to_be32(val), 307 cpu_to_be32(val),
314 }; 308 };
@@ -627,7 +621,8 @@ static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
627} 621}
628 622
629static int ath9k_init_priv(struct ath9k_htc_priv *priv, 623static int ath9k_init_priv(struct ath9k_htc_priv *priv,
630 u16 devid, char *product) 624 u16 devid, char *product,
625 u32 drv_info)
631{ 626{
632 struct ath_hw *ah = NULL; 627 struct ath_hw *ah = NULL;
633 struct ath_common *common; 628 struct ath_common *common;
@@ -641,6 +636,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
641 636
642 ah->hw_version.devid = devid; 637 ah->hw_version.devid = devid;
643 ah->hw_version.subsysid = 0; /* FIXME */ 638 ah->hw_version.subsysid = 0; /* FIXME */
639 ah->ah_flags |= AH_USE_EEPROM;
644 priv->ah = ah; 640 priv->ah = ah;
645 641
646 common = ath9k_hw_common(ah); 642 common = ath9k_hw_common(ah);
@@ -650,6 +646,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
650 common->hw = priv->hw; 646 common->hw = priv->hw;
651 common->priv = priv; 647 common->priv = priv;
652 common->debug_mask = ath9k_debug; 648 common->debug_mask = ath9k_debug;
649 common->driver_info = drv_info;
653 650
654 spin_lock_init(&priv->wmi->wmi_lock); 651 spin_lock_init(&priv->wmi->wmi_lock);
655 spin_lock_init(&priv->beacon_lock); 652 spin_lock_init(&priv->beacon_lock);
@@ -762,7 +759,7 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
762} 759}
763 760
764static int ath9k_init_device(struct ath9k_htc_priv *priv, 761static int ath9k_init_device(struct ath9k_htc_priv *priv,
765 u16 devid, char *product) 762 u16 devid, char *product, u32 drv_info)
766{ 763{
767 struct ieee80211_hw *hw = priv->hw; 764 struct ieee80211_hw *hw = priv->hw;
768 struct ath_common *common; 765 struct ath_common *common;
@@ -771,7 +768,7 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv,
771 struct ath_regulatory *reg; 768 struct ath_regulatory *reg;
772 769
773 /* Bring up device */ 770 /* Bring up device */
774 error = ath9k_init_priv(priv, devid, product); 771 error = ath9k_init_priv(priv, devid, product, drv_info);
775 if (error != 0) 772 if (error != 0)
776 goto err_init; 773 goto err_init;
777 774
@@ -829,7 +826,7 @@ err_init:
829} 826}
830 827
831int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 828int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
832 u16 devid, char *product) 829 u16 devid, char *product, u32 drv_info)
833{ 830{
834 struct ieee80211_hw *hw; 831 struct ieee80211_hw *hw;
835 struct ath9k_htc_priv *priv; 832 struct ath9k_htc_priv *priv;
@@ -856,14 +853,14 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
856 goto err_free; 853 goto err_free;
857 } 854 }
858 855
859 ret = ath9k_init_htc_services(priv, devid); 856 ret = ath9k_init_htc_services(priv, devid, drv_info);
860 if (ret) 857 if (ret)
861 goto err_init; 858 goto err_init;
862 859
863 /* The device may have been unplugged earlier. */ 860 /* The device may have been unplugged earlier. */
864 priv->op_flags &= ~OP_UNPLUGGED; 861 priv->op_flags &= ~OP_UNPLUGGED;
865 862
866 ret = ath9k_init_device(priv, devid, product); 863 ret = ath9k_init_device(priv, devid, product, drv_info);
867 if (ret) 864 if (ret)
868 goto err_init; 865 goto err_init;
869 866
@@ -893,14 +890,15 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
893#ifdef CONFIG_PM 890#ifdef CONFIG_PM
894int ath9k_htc_resume(struct htc_target *htc_handle) 891int ath9k_htc_resume(struct htc_target *htc_handle)
895{ 892{
893 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
896 int ret; 894 int ret;
897 895
898 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv); 896 ret = ath9k_htc_wait_for_target(priv);
899 if (ret) 897 if (ret)
900 return ret; 898 return ret;
901 899
902 ret = ath9k_init_htc_services(htc_handle->drv_priv, 900 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
903 htc_handle->drv_priv->ah->hw_version.devid); 901 priv->ah->common.driver_info);
904 return ret; 902 return ret;
905} 903}
906#endif 904#endif
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index 861ec926930..c41ab8c3016 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -462,9 +462,10 @@ void ath9k_htc_hw_free(struct htc_target *htc)
462} 462}
463 463
464int ath9k_htc_hw_init(struct htc_target *target, 464int ath9k_htc_hw_init(struct htc_target *target,
465 struct device *dev, u16 devid, char *product) 465 struct device *dev, u16 devid,
466 char *product, u32 drv_info)
466{ 467{
467 if (ath9k_htc_probe_device(target, dev, devid, product)) { 468 if (ath9k_htc_probe_device(target, dev, devid, product, drv_info)) {
468 printk(KERN_ERR "Failed to initialize the device\n"); 469 printk(KERN_ERR "Failed to initialize the device\n");
469 return -ENODEV; 470 return -ENODEV;
470 } 471 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.h b/drivers/net/wireless/ath/ath9k/htc_hst.h
index 07b6509d589..6fc1b21faa5 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.h
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.h
@@ -239,7 +239,8 @@ struct htc_target *ath9k_htc_hw_alloc(void *hif_handle,
239 struct device *dev); 239 struct device *dev);
240void ath9k_htc_hw_free(struct htc_target *htc); 240void ath9k_htc_hw_free(struct htc_target *htc);
241int ath9k_htc_hw_init(struct htc_target *target, 241int ath9k_htc_hw_init(struct htc_target *target,
242 struct device *dev, u16 devid, char *product); 242 struct device *dev, u16 devid, char *product,
243 u32 drv_info);
243void ath9k_htc_hw_deinit(struct htc_target *target, bool hot_unplug); 244void ath9k_htc_hw_deinit(struct htc_target *target, bool hot_unplug);
244 245
245#endif /* HTC_HST_H */ 246#endif /* HTC_HST_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 5fb1bf33faa..ce9e59f4cd3 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -310,10 +310,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
310 struct ath_common *common = ath9k_hw_common(ah); 310 struct ath_common *common = ath9k_hw_common(ah);
311 u32 regAddr[2] = { AR_STA_ID0 }; 311 u32 regAddr[2] = { AR_STA_ID0 };
312 u32 regHold[2]; 312 u32 regHold[2];
313 u32 patternData[4] = { 0x55555555, 313 static const u32 patternData[4] = {
314 0xaaaaaaaa, 314 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
315 0x66666666, 315 };
316 0x99999999 };
317 int i, j, loop_max; 316 int i, j, loop_max;
318 317
319 if (!AR_SREV_9300_20_OR_LATER(ah)) { 318 if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -419,10 +418,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
419 ah->hw_version.magic = AR5416_MAGIC; 418 ah->hw_version.magic = AR5416_MAGIC;
420 ah->hw_version.subvendorid = 0; 419 ah->hw_version.subvendorid = 0;
421 420
422 ah->ah_flags = 0;
423 if (!AR_SREV_9100(ah))
424 ah->ah_flags = AH_USE_EEPROM;
425
426 ah->atim_window = 0; 421 ah->atim_window = 0;
427 ah->sta_id1_defaults = 422 ah->sta_id1_defaults =
428 AR_STA_ID1_CRPT_MIC_ENABLE | 423 AR_STA_ID1_CRPT_MIC_ENABLE |
@@ -440,7 +435,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
440 u32 sum; 435 u32 sum;
441 int i; 436 int i;
442 u16 eeval; 437 u16 eeval;
443 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 438 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
444 439
445 sum = 0; 440 sum = 0;
446 for (i = 0; i < 3; i++) { 441 for (i = 0; i < 3; i++) {
@@ -1833,6 +1828,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1833 1828
1834 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1829 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1835 1830
1831 /* enable key search for every frame in an aggregate */
1832 if (AR_SREV_9300_20_OR_LATER(ah))
1833 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1834
1836 pCap->low_2ghz_chan = 2312; 1835 pCap->low_2ghz_chan = 2312;
1837 pCap->high_2ghz_chan = 2732; 1836 pCap->high_2ghz_chan = 2732;
1838 1837
@@ -1963,6 +1962,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1963 if (AR_SREV_9300_20_OR_LATER(ah)) 1962 if (AR_SREV_9300_20_OR_LATER(ah))
1964 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 1963 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1965 1964
1965 if (AR_SREV_9300_20_OR_LATER(ah))
1966 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1967
1966 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 1968 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1967 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 1969 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1968 1970
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index e29c7122f46..cc8f3b9af71 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -485,6 +485,40 @@ struct ath_hw_antcomb_conf {
485}; 485};
486 486
487/** 487/**
488 * struct ath_hw_radar_conf - radar detection initialization parameters
489 *
490 * @pulse_inband: threshold for checking the ratio of in-band power
491 * to total power for short radar pulses (half dB steps)
492 * @pulse_inband_step: threshold for checking an in-band power to total
493 * power ratio increase for short radar pulses (half dB steps)
494 * @pulse_height: threshold for detecting the beginning of a short
495 * radar pulse (dB step)
496 * @pulse_rssi: threshold for detecting if a short radar pulse is
497 * gone (dB step)
498 * @pulse_maxlen: maximum pulse length (0.8 us steps)
499 *
500 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
501 * @radar_inband: threshold for checking the ratio of in-band power
502 * to total power for long radar pulses (half dB steps)
503 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
504 *
505 * @ext_channel: enable extension channel radar detection
506 */
507struct ath_hw_radar_conf {
508 unsigned int pulse_inband;
509 unsigned int pulse_inband_step;
510 unsigned int pulse_height;
511 unsigned int pulse_rssi;
512 unsigned int pulse_maxlen;
513
514 unsigned int radar_rssi;
515 unsigned int radar_inband;
516 int fir_power;
517
518 bool ext_channel;
519};
520
521/**
488 * struct ath_hw_private_ops - callbacks used internally by hardware code 522 * struct ath_hw_private_ops - callbacks used internally by hardware code
489 * 523 *
490 * This structure contains private callbacks designed to only be used internally 524 * This structure contains private callbacks designed to only be used internally
@@ -549,6 +583,8 @@ struct ath_hw_private_ops {
549 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 583 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
550 int param); 584 int param);
551 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 585 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
586 void (*set_radar_params)(struct ath_hw *ah,
587 struct ath_hw_radar_conf *conf);
552 588
553 /* ANI */ 589 /* ANI */
554 void (*ani_cache_ini_regs)(struct ath_hw *ah); 590 void (*ani_cache_ini_regs)(struct ath_hw *ah);
@@ -747,6 +783,8 @@ struct ath_hw {
747 u8 txchainmask; 783 u8 txchainmask;
748 u8 rxchainmask; 784 u8 rxchainmask;
749 785
786 struct ath_hw_radar_conf radar_conf;
787
750 u32 originalGain[22]; 788 u32 originalGain[22];
751 int initPDADC; 789 int initPDADC;
752 int PDADCdelta; 790 int PDADCdelta;
@@ -804,6 +842,9 @@ struct ath_hw {
804 * this register when in sleep states. 842 * this register when in sleep states.
805 */ 843 */
806 u32 WARegVal; 844 u32 WARegVal;
845
846 /* Enterprise mode cap */
847 u32 ent_mode;
807}; 848};
808 849
809static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 850static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 5c26818d79e..7eef1faee66 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -533,6 +533,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
533 ah->hw_version.subsysid = subsysid; 533 ah->hw_version.subsysid = subsysid;
534 sc->sc_ah = ah; 534 sc->sc_ah = ah;
535 535
536 if (!sc->dev->platform_data)
537 ah->ah_flags |= AH_USE_EEPROM;
538
536 common = ath9k_hw_common(ah); 539 common = ath9k_hw_common(ah);
537 common->ops = &ath9k_common_ops; 540 common->ops = &ath9k_common_ops;
538 common->bus_ops = bus_ops; 541 common->bus_ops = bus_ops;
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 65b1ee2a979..b04b37b1124 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -766,14 +766,6 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
766} 766}
767EXPORT_SYMBOL(ath9k_hw_startpcureceive); 767EXPORT_SYMBOL(ath9k_hw_startpcureceive);
768 768
769void ath9k_hw_stoppcurecv(struct ath_hw *ah)
770{
771 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
772
773 ath9k_hw_disable_mib_counters(ah);
774}
775EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
776
777void ath9k_hw_abortpcurecv(struct ath_hw *ah) 769void ath9k_hw_abortpcurecv(struct ath_hw *ah)
778{ 770{
779 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); 771 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 22907e21cc4..7512f97e8f4 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -691,7 +691,6 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
691bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 691bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
692void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 692void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
693void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning); 693void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
694void ath9k_hw_stoppcurecv(struct ath_hw *ah);
695void ath9k_hw_abortpcurecv(struct ath_hw *ah); 694void ath9k_hw_abortpcurecv(struct ath_hw *ah);
696bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 695bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
697int ath9k_hw_beaconq_setup(struct ath_hw *ah); 696int ath9k_hw_beaconq_setup(struct ath_hw *ah);
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index f8c811af312..50bdb5db23b 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -380,6 +380,7 @@ void ath_paprd_calibrate(struct work_struct *work)
380 } 380 }
381 381
382 init_completion(&sc->paprd_complete); 382 init_completion(&sc->paprd_complete);
383 sc->paprd_pending = true;
383 ar9003_paprd_setup_gain_table(ah, chain); 384 ar9003_paprd_setup_gain_table(ah, chain);
384 txctl.paprd = BIT(chain); 385 txctl.paprd = BIT(chain);
385 if (ath_tx_start(hw, skb, &txctl) != 0) 386 if (ath_tx_start(hw, skb, &txctl) != 0)
@@ -387,6 +388,7 @@ void ath_paprd_calibrate(struct work_struct *work)
387 388
388 time_left = wait_for_completion_timeout(&sc->paprd_complete, 389 time_left = wait_for_completion_timeout(&sc->paprd_complete,
389 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 390 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
391 sc->paprd_pending = false;
390 if (!time_left) { 392 if (!time_left) {
391 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 393 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
392 "Timeout waiting for paprd training on " 394 "Timeout waiting for paprd training on "
@@ -1193,12 +1195,10 @@ mutex_unlock:
1193static int ath9k_tx(struct ieee80211_hw *hw, 1195static int ath9k_tx(struct ieee80211_hw *hw,
1194 struct sk_buff *skb) 1196 struct sk_buff *skb)
1195{ 1197{
1196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1197 struct ath_wiphy *aphy = hw->priv; 1198 struct ath_wiphy *aphy = hw->priv;
1198 struct ath_softc *sc = aphy->sc; 1199 struct ath_softc *sc = aphy->sc;
1199 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1200 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1200 struct ath_tx_control txctl; 1201 struct ath_tx_control txctl;
1201 int padpos, padsize;
1202 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1202 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1203 1203
1204 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 1204 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
@@ -1249,29 +1249,6 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1249 } 1249 }
1250 1250
1251 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1251 memset(&txctl, 0, sizeof(struct ath_tx_control));
1252
1253 /*
1254 * As a temporary workaround, assign seq# here; this will likely need
1255 * to be cleaned up to work better with Beacon transmission and virtual
1256 * BSSes.
1257 */
1258 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1259 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1260 sc->tx.seq_no += 0x10;
1261 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1262 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1263 }
1264
1265 /* Add the padding after the header if this is not already done */
1266 padpos = ath9k_cmn_padpos(hdr->frame_control);
1267 padsize = padpos & 3;
1268 if (padsize && skb->len>padpos) {
1269 if (skb_headroom(skb) < padsize)
1270 return -1;
1271 skb_push(skb, padsize);
1272 memmove(skb->data, skb->data + padsize, padpos);
1273 }
1274
1275 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 1252 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1276 1253
1277 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1254 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
@@ -2015,6 +1992,9 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2015 case IEEE80211_AMPDU_RX_STOP: 1992 case IEEE80211_AMPDU_RX_STOP:
2016 break; 1993 break;
2017 case IEEE80211_AMPDU_TX_START: 1994 case IEEE80211_AMPDU_TX_START:
1995 if (!(sc->sc_flags & SC_OP_TXAGGR))
1996 return -EOPNOTSUPP;
1997
2018 ath9k_ps_wakeup(sc); 1998 ath9k_ps_wakeup(sc);
2019 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1999 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2020 if (!ret) 2000 if (!ret)
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 6605bc2c203..09f69a9617f 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/nl80211.h> 17#include <linux/nl80211.h>
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/ath9k_platform.h>
19#include "ath9k.h" 20#include "ath9k.h"
20 21
21static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 22static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
@@ -53,21 +54,36 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
53 54
54static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 55static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
55{ 56{
56 struct ath_hw *ah = (struct ath_hw *) common->ah; 57 struct ath_softc *sc = (struct ath_softc *) common->priv;
57 58 struct ath9k_platform_data *pdata = sc->dev->platform_data;
58 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 59
59 60 if (pdata) {
60 if (!ath9k_hw_wait(ah, 61 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
61 AR_EEPROM_STATUS_DATA, 62 ath_print(common, ATH_DBG_FATAL,
62 AR_EEPROM_STATUS_DATA_BUSY | 63 "%s: eeprom read failed, offset %08x "
63 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 64 "is out of range\n",
64 AH_WAIT_TIMEOUT)) { 65 __func__, off);
65 return false; 66 }
67
68 *data = pdata->eeprom_data[off];
69 } else {
70 struct ath_hw *ah = (struct ath_hw *) common->ah;
71
72 common->ops->read(ah, AR5416_EEPROM_OFFSET +
73 (off << AR5416_EEPROM_S));
74
75 if (!ath9k_hw_wait(ah,
76 AR_EEPROM_STATUS_DATA,
77 AR_EEPROM_STATUS_DATA_BUSY |
78 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
79 AH_WAIT_TIMEOUT)) {
80 return false;
81 }
82
83 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
84 AR_EEPROM_STATUS_DATA_VAL);
66 } 85 }
67 86
68 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
69 AR_EEPROM_STATUS_DATA_VAL);
70
71 return true; 87 return true;
72} 88}
73 89
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 85c8e9310ca..3e6ea3bc3d8 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -864,7 +864,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
864 bool state_change = false; 864 bool state_change = false;
865 int count, n_bad_frames; 865 int count, n_bad_frames;
866 u8 last_per; 866 u8 last_per;
867 static u32 nretry_to_per_lookup[10] = { 867 static const u32 nretry_to_per_lookup[10] = {
868 100 * 0 / 1, 868 100 * 0 / 1,
869 100 * 1 / 4, 869 100 * 1 / 4,
870 100 * 1 / 2, 870 100 * 1 / 2,
@@ -1087,13 +1087,13 @@ static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
1087 struct ieee80211_tx_rate *rate) 1087 struct ieee80211_tx_rate *rate)
1088{ 1088{
1089 int rix = 0, i = 0; 1089 int rix = 0, i = 0;
1090 int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 }; 1090 static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
1091 1091
1092 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 1092 if (!(rate->flags & IEEE80211_TX_RC_MCS))
1093 return rate->idx; 1093 return rate->idx;
1094 1094
1095 while (rate->idx > mcs_rix_off[i] && 1095 while (rate->idx > mcs_rix_off[i] &&
1096 i < sizeof(mcs_rix_off)/sizeof(int)) { 1096 i < ARRAY_SIZE(mcs_rix_off)) {
1097 rix++; i++; 1097 rix++; i++;
1098 } 1098 }
1099 1099
@@ -1354,23 +1354,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1354 tx_info->status.ampdu_len = 1; 1354 tx_info->status.ampdu_len = 1;
1355 } 1355 }
1356 1356
1357 /* 1357 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
1358 * If an underrun error is seen assume it as an excessive retry only
1359 * if max frame trigger level has been reached (2 KB for singel stream,
1360 * and 4 KB for dual stream). Adjust the long retry as if the frame was
1361 * tried hw->max_rate_tries times to affect how ratectrl updates PER for
1362 * the failed rate. In case of congestion on the bus penalizing these
1363 * type of underruns should help hardware actually transmit new frames
1364 * successfully by eventually preferring slower rates. This itself
1365 * should also alleviate congestion on the bus.
1366 */
1367 if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
1368 (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
1369 tx_status = 1;
1370 is_underrun = 1;
1371 }
1372
1373 if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
1374 tx_status = 1; 1358 tx_status = 1;
1375 1359
1376 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status, 1360 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
@@ -1379,7 +1363,8 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1379 /* Check if aggregation has to be enabled for this tid */ 1363 /* Check if aggregation has to be enabled for this tid */
1380 if (conf_is_ht(&sc->hw->conf) && 1364 if (conf_is_ht(&sc->hw->conf) &&
1381 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1365 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1382 if (ieee80211_is_data_qos(fc)) { 1366 if (ieee80211_is_data_qos(fc) &&
1367 skb_get_queue_mapping(skb) != IEEE80211_AC_VO) {
1383 u8 *qc, tid; 1368 u8 *qc, tid;
1384 struct ath_node *an; 1369 struct ath_node *an;
1385 1370
@@ -1596,8 +1581,6 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1596 return NULL; 1581 return NULL;
1597 } 1582 }
1598 1583
1599 rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
1600
1601 return rate_priv; 1584 return rate_priv;
1602} 1585}
1603 1586
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 2f46a2266ba..31a004cb60a 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -215,7 +215,6 @@ struct ath_rate_priv {
215 u32 per_down_time; 215 u32 per_down_time;
216 u32 probe_interval; 216 u32 probe_interval;
217 u32 prev_data_rix; 217 u32 prev_data_rix;
218 u32 tx_triglevel_max;
219 struct ath_rateset neg_rates; 218 struct ath_rateset neg_rates;
220 struct ath_rateset neg_ht_rates; 219 struct ath_rateset neg_ht_rates;
221 struct ath_rate_softc *asc; 220 struct ath_rate_softc *asc;
@@ -225,11 +224,6 @@ struct ath_rate_priv {
225 struct ath_rc_stats rcstats[RATE_TABLE_SIZE]; 224 struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
226}; 225};
227 226
228#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
229#define ATH_TX_INFO_FRAME_TYPE_PAUSE (1 << 1)
230#define ATH_TX_INFO_XRETRY (1 << 3)
231#define ATH_TX_INFO_UNDERRUN (1 << 4)
232
233enum ath9k_internal_frame_type { 227enum ath9k_internal_frame_type {
234 ATH9K_IFT_NOT_INTERNAL, 228 ATH9K_IFT_NOT_INTERNAL,
235 ATH9K_IFT_PAUSE, 229 ATH9K_IFT_PAUSE,
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index c5c80764a94..262c81595f6 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -518,7 +518,7 @@ bool ath_stoprecv(struct ath_softc *sc)
518 bool stopped; 518 bool stopped;
519 519
520 spin_lock_bh(&sc->rx.rxbuflock); 520 spin_lock_bh(&sc->rx.rxbuflock);
521 ath9k_hw_stoppcurecv(ah); 521 ath9k_hw_abortpcurecv(ah);
522 ath9k_hw_setrxfilter(ah, 0); 522 ath9k_hw_setrxfilter(ah, 0);
523 stopped = ath9k_hw_stopdmarecv(ah); 523 stopped = ath9k_hw_stopdmarecv(ah);
524 524
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index dddf579aacf..a597cc8d864 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -864,15 +864,7 @@
864 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 864 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
865 865
866#define AR_DEVID_7010(_ah) \ 866#define AR_DEVID_7010(_ah) \
867 (((_ah)->hw_version.devid == 0x7010) || \ 867 ((_ah)->common.driver_info & AR7010_DEVICE)
868 ((_ah)->hw_version.devid == 0x7015) || \
869 ((_ah)->hw_version.devid == 0x9018) || \
870 ((_ah)->hw_version.devid == 0xA704) || \
871 ((_ah)->hw_version.devid == 0x1200))
872
873#define AR9287_HTC_DEVID(_ah) \
874 (((_ah)->hw_version.devid == 0x7015) || \
875 ((_ah)->hw_version.devid == 0x1200))
876 868
877#define AR_RADIO_SREV_MAJOR 0xf0 869#define AR_RADIO_SREV_MAJOR 0xf0
878#define AR_RAD5133_SREV_MAJOR 0xc0 870#define AR_RAD5133_SREV_MAJOR 0xc0
@@ -1072,6 +1064,9 @@ enum {
1072#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 1064#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
1073#define AR_INTR_PRIO_SYNC_MASK 0x40cc 1065#define AR_INTR_PRIO_SYNC_MASK 0x40cc
1074#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 1066#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
1067#define AR_ENT_OTP 0x40d8
1068#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1069#define AR_ENT_OTP_MPSD 0x00800000
1075 1070
1076#define AR_RTC_9300_PLL_DIV 0x000003ff 1071#define AR_RTC_9300_PLL_DIV 0x000003ff
1077#define AR_RTC_9300_PLL_DIV_S 0 1072#define AR_RTC_9300_PLL_DIV_S 0
@@ -1572,6 +1567,7 @@ enum {
1572#define AR_PCU_TBTT_PROTECT 0x00200000 1567#define AR_PCU_TBTT_PROTECT 0x00200000
1573#define AR_PCU_CLEAR_VMF 0x01000000 1568#define AR_PCU_CLEAR_VMF 0x01000000
1574#define AR_PCU_CLEAR_BA_VALID 0x04000000 1569#define AR_PCU_CLEAR_BA_VALID 0x04000000
1570#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
1575 1571
1576#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1572#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1577#define AR_PCU_BT_ANT_PREVENT_RX_S 20 1573#define AR_PCU_BT_ANT_PREVENT_RX_S 20
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index 4008f51d34c..d5442c3745c 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -305,13 +305,12 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
305 * ath9k version of ieee80211_tx_status() for TX frames that are generated 305 * ath9k version of ieee80211_tx_status() for TX frames that are generated
306 * internally in the driver. 306 * internally in the driver.
307 */ 307 */
308void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 308void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype)
309{ 309{
310 struct ath_wiphy *aphy = hw->priv; 310 struct ath_wiphy *aphy = hw->priv;
311 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 311 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
312 312
313 if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) && 313 if (ftype == ATH9K_IFT_PAUSE && aphy->state == ATH_WIPHY_PAUSING) {
314 aphy->state == ATH_WIPHY_PAUSING) {
315 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) { 314 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
316 printk(KERN_DEBUG "ath9k: %s: no ACK for pause " 315 printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
317 "frame\n", wiphy_name(hw->wiphy)); 316 "frame\n", wiphy_name(hw->wiphy));
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 6380bbd82d4..495432ec85a 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -48,19 +48,17 @@ static u16 bits_per_symbol[][2] = {
48 48
49#define IS_HT_RATE(_rate) ((_rate) & 0x80) 49#define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 50
51static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 51static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid, 52 struct ath_atx_tid *tid,
53 struct list_head *bf_head); 53 struct list_head *bf_head);
54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q, 55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar); 56 struct ath_tx_status *ts, int txok, int sendbar);
57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head); 58 struct list_head *head);
59static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); 59static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int txok);
62static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, 60static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
63 int nbad, int txok, bool update_rc); 61 int nframes, int nbad, int txok, bool update_rc);
64static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno); 63 int seqno);
66 64
@@ -140,12 +138,21 @@ unlock:
140 spin_unlock_bh(&txq->axq_lock); 138 spin_unlock_bh(&txq->axq_lock);
141} 139}
142 140
141static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142{
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
147}
148
143static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 149static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
144{ 150{
145 struct ath_txq *txq = tid->ac->txq; 151 struct ath_txq *txq = tid->ac->txq;
146 struct ath_buf *bf; 152 struct ath_buf *bf;
147 struct list_head bf_head; 153 struct list_head bf_head;
148 struct ath_tx_status ts; 154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
149 156
150 INIT_LIST_HEAD(&bf_head); 157 INIT_LIST_HEAD(&bf_head);
151 158
@@ -156,12 +163,15 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
157 list_move_tail(&bf->list, &bf_head); 164 list_move_tail(&bf->list, &bf_head);
158 165
159 if (bf_isretried(bf)) { 166 spin_unlock_bh(&txq->axq_lock);
160 ath_tx_update_baw(sc, tid, bf->bf_seqno); 167 fi = get_frame_info(bf->bf_mpdu);
168 if (fi->retries) {
169 ath_tx_update_baw(sc, tid, fi->seqno);
161 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
162 } else { 171 } else {
163 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 172 ath_tx_send_normal(sc, txq, tid, &bf_head);
164 } 173 }
174 spin_lock_bh(&txq->axq_lock);
165 } 175 }
166 176
167 spin_unlock_bh(&txq->axq_lock); 177 spin_unlock_bh(&txq->axq_lock);
@@ -184,14 +194,11 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
184} 194}
185 195
186static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 196static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
187 struct ath_buf *bf) 197 u16 seqno)
188{ 198{
189 int index, cindex; 199 int index, cindex;
190 200
191 if (bf_isretried(bf)) 201 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 return;
193
194 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
195 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
196 __set_bit(cindex, tid->tx_buf); 203 __set_bit(cindex, tid->tx_buf);
197 204
@@ -215,6 +222,7 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
215 struct ath_buf *bf; 222 struct ath_buf *bf;
216 struct list_head bf_head; 223 struct list_head bf_head;
217 struct ath_tx_status ts; 224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
218 226
219 memset(&ts, 0, sizeof(ts)); 227 memset(&ts, 0, sizeof(ts));
220 INIT_LIST_HEAD(&bf_head); 228 INIT_LIST_HEAD(&bf_head);
@@ -226,8 +234,9 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
226 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
227 list_move_tail(&bf->list, &bf_head); 235 list_move_tail(&bf->list, &bf_head);
228 236
229 if (bf_isretried(bf)) 237 fi = get_frame_info(bf->bf_mpdu);
230 ath_tx_update_baw(sc, tid, bf->bf_seqno); 238 if (fi->retries)
239 ath_tx_update_baw(sc, tid, fi->seqno);
231 240
232 spin_unlock(&txq->axq_lock); 241 spin_unlock(&txq->axq_lock);
233 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
@@ -239,16 +248,15 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
239} 248}
240 249
241static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 250static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
242 struct ath_buf *bf) 251 struct sk_buff *skb)
243{ 252{
244 struct sk_buff *skb; 253 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
245 struct ieee80211_hdr *hdr; 254 struct ieee80211_hdr *hdr;
246 255
247 bf->bf_state.bf_type |= BUF_RETRY;
248 bf->bf_retries++;
249 TX_STAT_INC(txq->axq_qnum, a_retries); 256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (tx_info->control.rates[4].count++ > 0)
258 return;
250 259
251 skb = bf->bf_mpdu;
252 hdr = (struct ieee80211_hdr *)skb->data; 260 hdr = (struct ieee80211_hdr *)skb->data;
253 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
254} 262}
@@ -298,9 +306,41 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
298 return tbf; 306 return tbf;
299} 307}
300 308
309static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
310 struct ath_tx_status *ts, int txok,
311 int *nframes, int *nbad)
312{
313 struct ath_frame_info *fi;
314 u16 seq_st = 0;
315 u32 ba[WME_BA_BMP_SIZE >> 5];
316 int ba_index;
317 int isaggr = 0;
318
319 *nbad = 0;
320 *nframes = 0;
321
322 isaggr = bf_isaggr(bf);
323 if (isaggr) {
324 seq_st = ts->ts_seqnum;
325 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
326 }
327
328 while (bf) {
329 fi = get_frame_info(bf->bf_mpdu);
330 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
331
332 (*nframes)++;
333 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
334 (*nbad)++;
335
336 bf = bf->bf_next;
337 }
338}
339
340
301static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 341static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
302 struct ath_buf *bf, struct list_head *bf_q, 342 struct ath_buf *bf, struct list_head *bf_q,
303 struct ath_tx_status *ts, int txok) 343 struct ath_tx_status *ts, int txok, bool retry)
304{ 344{
305 struct ath_node *an = NULL; 345 struct ath_node *an = NULL;
306 struct sk_buff *skb; 346 struct sk_buff *skb;
@@ -316,7 +356,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
316 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 356 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
317 bool rc_update = true; 357 bool rc_update = true;
318 struct ieee80211_tx_rate rates[4]; 358 struct ieee80211_tx_rate rates[4];
359 struct ath_frame_info *fi;
319 int nframes; 360 int nframes;
361 u8 tidno;
320 362
321 skb = bf->bf_mpdu; 363 skb = bf->bf_mpdu;
322 hdr = (struct ieee80211_hdr *)skb->data; 364 hdr = (struct ieee80211_hdr *)skb->data;
@@ -325,7 +367,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
325 hw = bf->aphy->hw; 367 hw = bf->aphy->hw;
326 368
327 memcpy(rates, tx_info->control.rates, sizeof(rates)); 369 memcpy(rates, tx_info->control.rates, sizeof(rates));
328 nframes = bf->bf_nframes;
329 370
330 rcu_read_lock(); 371 rcu_read_lock();
331 372
@@ -342,7 +383,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
342 !bf->bf_stale || bf_next != NULL) 383 !bf->bf_stale || bf_next != NULL)
343 list_move_tail(&bf->list, &bf_head); 384 list_move_tail(&bf->list, &bf_head);
344 385
345 ath_tx_rc_status(bf, ts, 1, 0, false); 386 ath_tx_rc_status(bf, ts, 1, 1, 0, false);
346 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 387 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
347 0, 0); 388 0, 0);
348 389
@@ -352,14 +393,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
352 } 393 }
353 394
354 an = (struct ath_node *)sta->drv_priv; 395 an = (struct ath_node *)sta->drv_priv;
355 tid = ATH_AN_2_TID(an, bf->bf_tidno); 396 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
397 tid = ATH_AN_2_TID(an, tidno);
356 398
357 /* 399 /*
358 * The hardware occasionally sends a tx status for the wrong TID. 400 * The hardware occasionally sends a tx status for the wrong TID.
359 * In this case, the BA status cannot be considered valid and all 401 * In this case, the BA status cannot be considered valid and all
360 * subframes need to be retransmitted 402 * subframes need to be retransmitted
361 */ 403 */
362 if (bf->bf_tidno != ts->tid) 404 if (tidno != ts->tid)
363 txok = false; 405 txok = false;
364 406
365 isaggr = bf_isaggr(bf); 407 isaggr = bf_isaggr(bf);
@@ -385,15 +427,16 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
385 INIT_LIST_HEAD(&bf_pending); 427 INIT_LIST_HEAD(&bf_pending);
386 INIT_LIST_HEAD(&bf_head); 428 INIT_LIST_HEAD(&bf_head);
387 429
388 nbad = ath_tx_num_badfrms(sc, bf, ts, txok); 430 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
389 while (bf) { 431 while (bf) {
390 txfail = txpending = 0; 432 txfail = txpending = 0;
391 bf_next = bf->bf_next; 433 bf_next = bf->bf_next;
392 434
393 skb = bf->bf_mpdu; 435 skb = bf->bf_mpdu;
394 tx_info = IEEE80211_SKB_CB(skb); 436 tx_info = IEEE80211_SKB_CB(skb);
437 fi = get_frame_info(skb);
395 438
396 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { 439 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
397 /* transmit completion, subframe is 440 /* transmit completion, subframe is
398 * acked by block ack */ 441 * acked by block ack */
399 acked_cnt++; 442 acked_cnt++;
@@ -401,10 +444,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
401 /* transmit completion */ 444 /* transmit completion */
402 acked_cnt++; 445 acked_cnt++;
403 } else { 446 } else {
404 if (!(tid->state & AGGR_CLEANUP) && 447 if (!(tid->state & AGGR_CLEANUP) && retry) {
405 !bf_last->bf_tx_aborted) { 448 if (fi->retries < ATH_MAX_SW_RETRIES) {
406 if (bf->bf_retries < ATH_MAX_SW_RETRIES) { 449 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
407 ath_tx_set_retry(sc, txq, bf);
408 txpending = 1; 450 txpending = 1;
409 } else { 451 } else {
410 bf->bf_state.bf_type |= BUF_XRETRY; 452 bf->bf_state.bf_type |= BUF_XRETRY;
@@ -442,16 +484,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
442 * block-ack window 484 * block-ack window
443 */ 485 */
444 spin_lock_bh(&txq->axq_lock); 486 spin_lock_bh(&txq->axq_lock);
445 ath_tx_update_baw(sc, tid, bf->bf_seqno); 487 ath_tx_update_baw(sc, tid, fi->seqno);
446 spin_unlock_bh(&txq->axq_lock); 488 spin_unlock_bh(&txq->axq_lock);
447 489
448 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 490 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
449 memcpy(tx_info->control.rates, rates, sizeof(rates)); 491 memcpy(tx_info->control.rates, rates, sizeof(rates));
450 bf->bf_nframes = nframes; 492 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
451 ath_tx_rc_status(bf, ts, nbad, txok, true);
452 rc_update = false; 493 rc_update = false;
453 } else { 494 } else {
454 ath_tx_rc_status(bf, ts, nbad, txok, false); 495 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
455 } 496 }
456 497
457 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 498 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
@@ -470,14 +511,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
470 */ 511 */
471 if (!tbf) { 512 if (!tbf) {
472 spin_lock_bh(&txq->axq_lock); 513 spin_lock_bh(&txq->axq_lock);
473 ath_tx_update_baw(sc, tid, 514 ath_tx_update_baw(sc, tid, fi->seqno);
474 bf->bf_seqno);
475 spin_unlock_bh(&txq->axq_lock); 515 spin_unlock_bh(&txq->axq_lock);
476 516
477 bf->bf_state.bf_type |= 517 bf->bf_state.bf_type |=
478 BUF_XRETRY; 518 BUF_XRETRY;
479 ath_tx_rc_status(bf, ts, nbad, 519 ath_tx_rc_status(bf, ts, nframes,
480 0, false); 520 nbad, 0, false);
481 ath_tx_complete_buf(sc, bf, txq, 521 ath_tx_complete_buf(sc, bf, txq,
482 &bf_head, 522 &bf_head,
483 ts, 0, 0); 523 ts, 0, 0);
@@ -611,6 +651,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
611 u16 minlen; 651 u16 minlen;
612 u8 flags, rix; 652 u8 flags, rix;
613 int width, streams, half_gi, ndelim, mindelim; 653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
614 655
615 /* Select standard number of delimiters based on frame length alone */ 656 /* Select standard number of delimiters based on frame length alone */
616 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
@@ -621,7 +662,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
621 * TODO - this could be improved to be dependent on the rate. 662 * TODO - this could be improved to be dependent on the rate.
622 * The hardware can keep up at lower rates, but not higher rates 663 * The hardware can keep up at lower rates, but not higher rates
623 */ 664 */
624 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) 665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
625 ndelim += ATH_AGGR_ENCRYPTDELIM; 666 ndelim += ATH_AGGR_ENCRYPTDELIM;
626 667
627 /* 668 /*
@@ -665,7 +706,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
665static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 706static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
666 struct ath_txq *txq, 707 struct ath_txq *txq,
667 struct ath_atx_tid *tid, 708 struct ath_atx_tid *tid,
668 struct list_head *bf_q) 709 struct list_head *bf_q,
710 int *aggr_len)
669{ 711{
670#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 712#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
671 struct ath_buf *bf, *bf_first, *bf_prev = NULL; 713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
@@ -674,14 +716,16 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
674 al_delta, h_baw = tid->baw_size / 2; 716 al_delta, h_baw = tid->baw_size / 2;
675 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
676 struct ieee80211_tx_info *tx_info; 718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
677 720
678 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); 721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
679 722
680 do { 723 do {
681 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
682 726
683 /* do not step over block-ack window */ 727 /* do not step over block-ack window */
684 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { 728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
685 status = ATH_AGGR_BAW_CLOSED; 729 status = ATH_AGGR_BAW_CLOSED;
686 break; 730 break;
687 } 731 }
@@ -692,7 +736,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
692 } 736 }
693 737
694 /* do not exceed aggregation limit */ 738 /* do not exceed aggregation limit */
695 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; 739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
696 740
697 if (nframes && 741 if (nframes &&
698 (aggr_limit < (al + bpad + al_delta + prev_al))) { 742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
@@ -719,14 +763,15 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
719 * Get the delimiters needed to meet the MPDU 763 * Get the delimiters needed to meet the MPDU
720 * density for this node. 764 * density for this node.
721 */ 765 */
722 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); 766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
723 bpad = PADBYTES(al_delta) + (ndelim << 2); 767 bpad = PADBYTES(al_delta) + (ndelim << 2);
724 768
725 bf->bf_next = NULL; 769 bf->bf_next = NULL;
726 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); 770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
727 771
728 /* link buffers of this frame to the aggregate */ 772 /* link buffers of this frame to the aggregate */
729 ath_tx_addto_baw(sc, tid, bf); 773 if (!fi->retries)
774 ath_tx_addto_baw(sc, tid, fi->seqno);
730 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); 775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
731 list_move_tail(&bf->list, bf_q); 776 list_move_tail(&bf->list, bf_q);
732 if (bf_prev) { 777 if (bf_prev) {
@@ -738,8 +783,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
738 783
739 } while (!list_empty(&tid->buf_q)); 784 } while (!list_empty(&tid->buf_q));
740 785
741 bf_first->bf_al = al; 786 *aggr_len = al;
742 bf_first->bf_nframes = nframes;
743 787
744 return status; 788 return status;
745#undef PADBYTES 789#undef PADBYTES
@@ -750,7 +794,9 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
750{ 794{
751 struct ath_buf *bf; 795 struct ath_buf *bf;
752 enum ATH_AGGR_STATUS status; 796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
753 struct list_head bf_q; 798 struct list_head bf_q;
799 int aggr_len;
754 800
755 do { 801 do {
756 if (list_empty(&tid->buf_q)) 802 if (list_empty(&tid->buf_q))
@@ -758,7 +804,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
758 804
759 INIT_LIST_HEAD(&bf_q); 805 INIT_LIST_HEAD(&bf_q);
760 806
761 status = ath_tx_form_aggr(sc, txq, tid, &bf_q); 807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
762 808
763 /* 809 /*
764 * no frames picked up to be aggregated; 810 * no frames picked up to be aggregated;
@@ -771,18 +817,20 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
771 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
772 818
773 /* if only one frame, send as non-aggregate */ 819 /* if only one frame, send as non-aggregate */
774 if (bf->bf_nframes == 1) { 820 if (bf == bf->bf_lastbf) {
821 fi = get_frame_info(bf->bf_mpdu);
822
775 bf->bf_state.bf_type &= ~BUF_AGGR; 823 bf->bf_state.bf_type &= ~BUF_AGGR;
776 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); 824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
777 ath_buf_set_rate(sc, bf); 825 ath_buf_set_rate(sc, bf, fi->framelen);
778 ath_tx_txqaddbuf(sc, txq, &bf_q); 826 ath_tx_txqaddbuf(sc, txq, &bf_q);
779 continue; 827 continue;
780 } 828 }
781 829
782 /* setup first desc of aggregate */ 830 /* setup first desc of aggregate */
783 bf->bf_state.bf_type |= BUF_AGGR; 831 bf->bf_state.bf_type |= BUF_AGGR;
784 ath_buf_set_rate(sc, bf); 832 ath_buf_set_rate(sc, bf, aggr_len);
785 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); 833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
786 834
787 /* anchor last desc of aggregate */ 835 /* anchor last desc of aggregate */
788 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
@@ -1067,8 +1115,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1067 } 1115 }
1068 1116
1069 lastbf = bf->bf_lastbf; 1117 lastbf = bf->bf_lastbf;
1070 if (!retry_tx)
1071 lastbf->bf_tx_aborted = true;
1072 1118
1073 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1119 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1074 list_cut_position(&bf_head, 1120 list_cut_position(&bf_head,
@@ -1085,7 +1131,8 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1085 spin_unlock_bh(&txq->axq_lock); 1131 spin_unlock_bh(&txq->axq_lock);
1086 1132
1087 if (bf_isampdu(bf)) 1133 if (bf_isampdu(bf))
1088 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0); 1134 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1135 retry_tx);
1089 else 1136 else
1090 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 1137 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1091 } 1138 }
@@ -1106,7 +1153,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1106 1153
1107 if (bf_isampdu(bf)) 1154 if (bf_isampdu(bf))
1108 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 1155 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1109 &ts, 0); 1156 &ts, 0, retry_tx);
1110 else 1157 else
1111 ath_tx_complete_buf(sc, bf, txq, &bf_head, 1158 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1112 &ts, 0, 0); 1159 &ts, 0, 0);
@@ -1284,12 +1331,11 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1284} 1331}
1285 1332
1286static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1333static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1287 struct list_head *bf_head, 1334 struct ath_buf *bf, struct ath_tx_control *txctl)
1288 struct ath_tx_control *txctl)
1289{ 1335{
1290 struct ath_buf *bf; 1336 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1337 struct list_head bf_head;
1291 1338
1292 bf = list_first_entry(bf_head, struct ath_buf, list);
1293 bf->bf_state.bf_type |= BUF_AMPDU; 1339 bf->bf_state.bf_type |= BUF_AMPDU;
1294 TX_STAT_INC(txctl->txq->axq_qnum, a_queued); 1340 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1295 1341
@@ -1301,56 +1347,47 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1301 * - h/w queue depth exceeds low water mark 1347 * - h/w queue depth exceeds low water mark
1302 */ 1348 */
1303 if (!list_empty(&tid->buf_q) || tid->paused || 1349 if (!list_empty(&tid->buf_q) || tid->paused ||
1304 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || 1350 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1305 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { 1351 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1306 /* 1352 /*
1307 * Add this frame to software queue for scheduling later 1353 * Add this frame to software queue for scheduling later
1308 * for aggregation. 1354 * for aggregation.
1309 */ 1355 */
1310 list_move_tail(&bf->list, &tid->buf_q); 1356 list_add_tail(&bf->list, &tid->buf_q);
1311 ath_tx_queue_tid(txctl->txq, tid); 1357 ath_tx_queue_tid(txctl->txq, tid);
1312 return; 1358 return;
1313 } 1359 }
1314 1360
1361 INIT_LIST_HEAD(&bf_head);
1362 list_add(&bf->list, &bf_head);
1363
1315 /* Add sub-frame to BAW */ 1364 /* Add sub-frame to BAW */
1316 ath_tx_addto_baw(sc, tid, bf); 1365 if (!fi->retries)
1366 ath_tx_addto_baw(sc, tid, fi->seqno);
1317 1367
1318 /* Queue to h/w without aggregation */ 1368 /* Queue to h/w without aggregation */
1319 bf->bf_nframes = 1;
1320 bf->bf_lastbf = bf; 1369 bf->bf_lastbf = bf;
1321 ath_buf_set_rate(sc, bf); 1370 ath_buf_set_rate(sc, bf, fi->framelen);
1322 ath_tx_txqaddbuf(sc, txctl->txq, bf_head); 1371 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1323} 1372}
1324 1373
1325static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 1374static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1326 struct ath_atx_tid *tid, 1375 struct ath_atx_tid *tid,
1327 struct list_head *bf_head) 1376 struct list_head *bf_head)
1328{ 1377{
1378 struct ath_frame_info *fi;
1329 struct ath_buf *bf; 1379 struct ath_buf *bf;
1330 1380
1331 bf = list_first_entry(bf_head, struct ath_buf, list); 1381 bf = list_first_entry(bf_head, struct ath_buf, list);
1332 bf->bf_state.bf_type &= ~BUF_AMPDU; 1382 bf->bf_state.bf_type &= ~BUF_AMPDU;
1333 1383
1334 /* update starting sequence number for subsequent ADDBA request */ 1384 /* update starting sequence number for subsequent ADDBA request */
1335 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 1385 if (tid)
1336 1386 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1337 bf->bf_nframes = 1;
1338 bf->bf_lastbf = bf;
1339 ath_buf_set_rate(sc, bf);
1340 ath_tx_txqaddbuf(sc, txq, bf_head);
1341 TX_STAT_INC(txq->axq_qnum, queued);
1342}
1343
1344static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1345 struct list_head *bf_head)
1346{
1347 struct ath_buf *bf;
1348
1349 bf = list_first_entry(bf_head, struct ath_buf, list);
1350 1387
1351 bf->bf_lastbf = bf; 1388 bf->bf_lastbf = bf;
1352 bf->bf_nframes = 1; 1389 fi = get_frame_info(bf->bf_mpdu);
1353 ath_buf_set_rate(sc, bf); 1390 ath_buf_set_rate(sc, bf, fi->framelen);
1354 ath_tx_txqaddbuf(sc, txq, bf_head); 1391 ath_tx_txqaddbuf(sc, txq, bf_head);
1355 TX_STAT_INC(txq->axq_qnum, queued); 1392 TX_STAT_INC(txq->axq_qnum, queued);
1356} 1393}
@@ -1378,40 +1415,52 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1378 return htype; 1415 return htype;
1379} 1416}
1380 1417
1381static void assign_aggr_tid_seqno(struct sk_buff *skb, 1418static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1382 struct ath_buf *bf) 1419 int framelen)
1383{ 1420{
1421 struct ath_wiphy *aphy = hw->priv;
1422 struct ath_softc *sc = aphy->sc;
1384 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1423 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1424 struct ieee80211_sta *sta = tx_info->control.sta;
1425 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1385 struct ieee80211_hdr *hdr; 1426 struct ieee80211_hdr *hdr;
1427 struct ath_frame_info *fi = get_frame_info(skb);
1386 struct ath_node *an; 1428 struct ath_node *an;
1387 struct ath_atx_tid *tid; 1429 struct ath_atx_tid *tid;
1388 __le16 fc; 1430 enum ath9k_key_type keytype;
1389 u8 *qc; 1431 u16 seqno = 0;
1432 u8 tidno;
1390 1433
1391 if (!tx_info->control.sta) 1434 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1392 return;
1393 1435
1394 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1395 hdr = (struct ieee80211_hdr *)skb->data; 1436 hdr = (struct ieee80211_hdr *)skb->data;
1396 fc = hdr->frame_control; 1437 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1438 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1397 1439
1398 if (ieee80211_is_data_qos(fc)) { 1440 an = (struct ath_node *) sta->drv_priv;
1399 qc = ieee80211_get_qos_ctl(hdr); 1441 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1400 bf->bf_tidno = qc[0] & 0xf; 1442
1443 /*
1444 * Override seqno set by upper layer with the one
1445 * in tx aggregation state.
1446 */
1447 tid = ATH_AN_2_TID(an, tidno);
1448 seqno = tid->seq_next;
1449 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1450 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1401 } 1451 }
1402 1452
1403 /* 1453 memset(fi, 0, sizeof(*fi));
1404 * For HT capable stations, we save tidno for later use. 1454 if (hw_key)
1405 * We also override seqno set by upper layer with the one 1455 fi->keyix = hw_key->hw_key_idx;
1406 * in tx aggregation state. 1456 else
1407 */ 1457 fi->keyix = ATH9K_TXKEYIX_INVALID;
1408 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1458 fi->keytype = keytype;
1409 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 1459 fi->framelen = framelen;
1410 bf->bf_seqno = tid->seq_next; 1460 fi->seqno = seqno;
1411 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1412} 1461}
1413 1462
1414static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc) 1463static int setup_tx_flags(struct sk_buff *skb)
1415{ 1464{
1416 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1465 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1417 int flags = 0; 1466 int flags = 0;
@@ -1422,7 +1471,7 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1422 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1471 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1423 flags |= ATH9K_TXDESC_NOACK; 1472 flags |= ATH9K_TXDESC_NOACK;
1424 1473
1425 if (use_ldpc) 1474 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1426 flags |= ATH9K_TXDESC_LDPC; 1475 flags |= ATH9K_TXDESC_LDPC;
1427 1476
1428 return flags; 1477 return flags;
@@ -1434,13 +1483,11 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1434 * width - 0 for 20 MHz, 1 for 40 MHz 1483 * width - 0 for 20 MHz, 1 for 40 MHz
1435 * half_gi - to use 4us v/s 3.6 us for symbol time 1484 * half_gi - to use 4us v/s 3.6 us for symbol time
1436 */ 1485 */
1437static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 1486static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1438 int width, int half_gi, bool shortPreamble) 1487 int width, int half_gi, bool shortPreamble)
1439{ 1488{
1440 u32 nbits, nsymbits, duration, nsymbols; 1489 u32 nbits, nsymbits, duration, nsymbols;
1441 int streams, pktlen; 1490 int streams;
1442
1443 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1444 1491
1445 /* find number of symbols: PLCP + data */ 1492 /* find number of symbols: PLCP + data */
1446 streams = HT_RC_2_STREAMS(rix); 1493 streams = HT_RC_2_STREAMS(rix);
@@ -1459,7 +1506,7 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1459 return duration; 1506 return duration;
1460} 1507}
1461 1508
1462static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1509static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1463{ 1510{
1464 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1511 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1465 struct ath9k_11n_rate_series series[4]; 1512 struct ath9k_11n_rate_series series[4];
@@ -1522,7 +1569,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1522 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1569 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1523 /* MCS rates */ 1570 /* MCS rates */
1524 series[i].Rate = rix | 0x80; 1571 series[i].Rate = rix | 0x80;
1525 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1572 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1526 is_40, is_sgi, is_sp); 1573 is_40, is_sgi, is_sp);
1527 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1574 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1528 series[i].RateFlags |= ATH9K_RATESERIES_STBC; 1575 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
@@ -1546,11 +1593,11 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1546 } 1593 }
1547 1594
1548 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1595 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1549 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp); 1596 phy, rate->bitrate * 100, len, rix, is_sp);
1550 } 1597 }
1551 1598
1552 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1599 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1553 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) 1600 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1554 flags &= ~ATH9K_TXDESC_RTSENA; 1601 flags &= ~ATH9K_TXDESC_RTSENA;
1555 1602
1556 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1603 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
@@ -1567,67 +1614,29 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1567 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); 1614 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1568} 1615}
1569 1616
1570static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, 1617static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1571 struct sk_buff *skb, 1618 struct ath_txq *txq,
1572 struct ath_tx_control *txctl) 1619 struct sk_buff *skb)
1573{ 1620{
1574 struct ath_wiphy *aphy = hw->priv; 1621 struct ath_wiphy *aphy = hw->priv;
1575 struct ath_softc *sc = aphy->sc; 1622 struct ath_softc *sc = aphy->sc;
1576 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1623 struct ath_hw *ah = sc->sc_ah;
1577 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1578 int hdrlen; 1625 struct ath_frame_info *fi = get_frame_info(skb);
1579 __le16 fc; 1626 struct ath_buf *bf;
1580 int padpos, padsize; 1627 struct ath_desc *ds;
1581 bool use_ldpc = false; 1628 int frm_type;
1582 1629
1583 tx_info->pad[0] = 0; 1630 bf = ath_tx_get_buffer(sc);
1584 switch (txctl->frame_type) { 1631 if (!bf) {
1585 case ATH9K_IFT_NOT_INTERNAL: 1632 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1586 break; 1633 return NULL;
1587 case ATH9K_IFT_PAUSE:
1588 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1589 /* fall through */
1590 case ATH9K_IFT_UNPAUSE:
1591 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1592 break;
1593 } 1634 }
1594 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1595 fc = hdr->frame_control;
1596 1635
1597 ATH_TXBUF_RESET(bf); 1636 ATH_TXBUF_RESET(bf);
1598 1637
1599 bf->aphy = aphy; 1638 bf->aphy = aphy;
1600 bf->bf_frmlen = skb->len + FCS_LEN; 1639 bf->bf_flags = setup_tx_flags(skb);
1601 /* Remove the padding size from bf_frmlen, if any */
1602 padpos = ath9k_cmn_padpos(hdr->frame_control);
1603 padsize = padpos & 3;
1604 if (padsize && skb->len>padpos+padsize) {
1605 bf->bf_frmlen -= padsize;
1606 }
1607
1608 if (!txctl->paprd && conf_is_ht(&hw->conf)) {
1609 bf->bf_state.bf_type |= BUF_HT;
1610 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1611 use_ldpc = true;
1612 }
1613
1614 bf->bf_state.bfs_paprd = txctl->paprd;
1615 if (txctl->paprd)
1616 bf->bf_state.bfs_paprd_timestamp = jiffies;
1617 bf->bf_flags = setup_tx_flags(skb, use_ldpc);
1618
1619 bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1620 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1621 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1622 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1623 } else {
1624 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1625 }
1626
1627 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1628 (sc->sc_flags & SC_OP_TXAGGR))
1629 assign_aggr_tid_seqno(skb, bf);
1630
1631 bf->bf_mpdu = skb; 1640 bf->bf_mpdu = skb;
1632 1641
1633 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 1642 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
@@ -1637,40 +1646,17 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1637 bf->bf_buf_addr = 0; 1646 bf->bf_buf_addr = 0;
1638 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 1647 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1639 "dma_mapping_error() on TX\n"); 1648 "dma_mapping_error() on TX\n");
1640 return -ENOMEM; 1649 ath_tx_return_buffer(sc, bf);
1650 return NULL;
1641 } 1651 }
1642 1652
1643 bf->bf_tx_aborted = false;
1644
1645 return 0;
1646}
1647
1648/* FIXME: tx power */
1649static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1650 struct ath_tx_control *txctl)
1651{
1652 struct sk_buff *skb = bf->bf_mpdu;
1653 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1654 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1655 struct ath_node *an = NULL;
1656 struct list_head bf_head;
1657 struct ath_desc *ds;
1658 struct ath_atx_tid *tid;
1659 struct ath_hw *ah = sc->sc_ah;
1660 int frm_type;
1661 __le16 fc;
1662
1663 frm_type = get_hw_packet_type(skb); 1653 frm_type = get_hw_packet_type(skb);
1664 fc = hdr->frame_control;
1665
1666 INIT_LIST_HEAD(&bf_head);
1667 list_add_tail(&bf->list, &bf_head);
1668 1654
1669 ds = bf->bf_desc; 1655 ds = bf->bf_desc;
1670 ath9k_hw_set_desc_link(ah, ds, 0); 1656 ath9k_hw_set_desc_link(ah, ds, 0);
1671 1657
1672 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, 1658 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1673 bf->bf_keyix, bf->bf_keytype, bf->bf_flags); 1659 fi->keyix, fi->keytype, bf->bf_flags);
1674 1660
1675 ath9k_hw_filltxdesc(ah, ds, 1661 ath9k_hw_filltxdesc(ah, ds,
1676 skb->len, /* segment length */ 1662 skb->len, /* segment length */
@@ -1678,43 +1664,50 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1678 true, /* last segment */ 1664 true, /* last segment */
1679 ds, /* first descriptor */ 1665 ds, /* first descriptor */
1680 bf->bf_buf_addr, 1666 bf->bf_buf_addr,
1681 txctl->txq->axq_qnum); 1667 txq->axq_qnum);
1682 1668
1683 if (bf->bf_state.bfs_paprd)
1684 ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
1685 1669
1686 spin_lock_bh(&txctl->txq->axq_lock); 1670 return bf;
1671}
1687 1672
1688 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && 1673/* FIXME: tx power */
1689 tx_info->control.sta) { 1674static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1690 an = (struct ath_node *)tx_info->control.sta->drv_priv; 1675 struct ath_tx_control *txctl)
1691 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1676{
1677 struct sk_buff *skb = bf->bf_mpdu;
1678 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1679 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1680 struct list_head bf_head;
1681 struct ath_atx_tid *tid;
1682 u8 tidno;
1692 1683
1693 if (!ieee80211_is_data_qos(fc)) { 1684 spin_lock_bh(&txctl->txq->axq_lock);
1694 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1685
1695 goto tx_done; 1686 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && txctl->an) {
1696 } 1687 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1688 IEEE80211_QOS_CTL_TID_MASK;
1689 tid = ATH_AN_2_TID(txctl->an, tidno);
1697 1690
1698 WARN_ON(tid->ac->txq != txctl->txq); 1691 WARN_ON(tid->ac->txq != txctl->txq);
1699 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1692 /*
1700 /* 1693 * Try aggregation if it's a unicast data frame
1701 * Try aggregation if it's a unicast data frame 1694 * and the destination is HT capable.
1702 * and the destination is HT capable. 1695 */
1703 */ 1696 ath_tx_send_ampdu(sc, tid, bf, txctl);
1704 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1705 } else {
1706 /*
1707 * Send this frame as regular when ADDBA
1708 * exchange is neither complete nor pending.
1709 */
1710 ath_tx_send_ht_normal(sc, txctl->txq,
1711 tid, &bf_head);
1712 }
1713 } else { 1697 } else {
1714 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1698 INIT_LIST_HEAD(&bf_head);
1699 list_add_tail(&bf->list, &bf_head);
1700
1701 bf->bf_state.bfs_ftype = txctl->frame_type;
1702 bf->bf_state.bfs_paprd = txctl->paprd;
1703
1704 if (bf->bf_state.bfs_paprd)
1705 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1706 bf->bf_state.bfs_paprd);
1707
1708 ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
1715 } 1709 }
1716 1710
1717tx_done:
1718 spin_unlock_bh(&txctl->txq->axq_lock); 1711 spin_unlock_bh(&txctl->txq->axq_lock);
1719} 1712}
1720 1713
@@ -1722,65 +1715,20 @@ tx_done:
1722int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1715int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1723 struct ath_tx_control *txctl) 1716 struct ath_tx_control *txctl)
1724{ 1717{
1718 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1719 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1720 struct ieee80211_sta *sta = info->control.sta;
1725 struct ath_wiphy *aphy = hw->priv; 1721 struct ath_wiphy *aphy = hw->priv;
1726 struct ath_softc *sc = aphy->sc; 1722 struct ath_softc *sc = aphy->sc;
1727 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1728 struct ath_txq *txq = txctl->txq; 1723 struct ath_txq *txq = txctl->txq;
1729 struct ath_buf *bf; 1724 struct ath_buf *bf;
1730 int q, r;
1731
1732 bf = ath_tx_get_buffer(sc);
1733 if (!bf) {
1734 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1735 return -1;
1736 }
1737
1738 q = skb_get_queue_mapping(skb);
1739 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1740 if (unlikely(r)) {
1741 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1742
1743 /* upon ath_tx_processq() this TX queue will be resumed, we
1744 * guarantee this will happen by knowing beforehand that
1745 * we will at least have to run TX completionon one buffer
1746 * on the queue */
1747 spin_lock_bh(&txq->axq_lock);
1748 if (txq == sc->tx.txq_map[q] && !txq->stopped &&
1749 txq->axq_depth > 1) {
1750 ath_mac80211_stop_queue(sc, q);
1751 txq->stopped = 1;
1752 }
1753 spin_unlock_bh(&txq->axq_lock);
1754
1755 ath_tx_return_buffer(sc, bf);
1756
1757 return r;
1758 }
1759
1760 spin_lock_bh(&txq->axq_lock);
1761 if (txq == sc->tx.txq_map[q] &&
1762 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1763 ath_mac80211_stop_queue(sc, q);
1764 txq->stopped = 1;
1765 }
1766 spin_unlock_bh(&txq->axq_lock);
1767
1768 ath_tx_start_dma(sc, bf, txctl);
1769
1770 return 0;
1771}
1772
1773void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1774{
1775 struct ath_wiphy *aphy = hw->priv;
1776 struct ath_softc *sc = aphy->sc;
1777 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1778 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1779 int padpos, padsize; 1725 int padpos, padsize;
1780 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1726 int frmlen = skb->len + FCS_LEN;
1781 struct ath_tx_control txctl; 1727 int q;
1782 1728
1783 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1729 txctl->an = (struct ath_node *)sta->drv_priv;
1730 if (info->control.hw_key)
1731 frmlen += info->control.hw_key->icv_len;
1784 1732
1785 /* 1733 /*
1786 * As a temporary workaround, assign seq# here; this will likely need 1734 * As a temporary workaround, assign seq# here; this will likely need
@@ -1797,30 +1745,37 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1797 /* Add the padding after the header if this is not already done */ 1745 /* Add the padding after the header if this is not already done */
1798 padpos = ath9k_cmn_padpos(hdr->frame_control); 1746 padpos = ath9k_cmn_padpos(hdr->frame_control);
1799 padsize = padpos & 3; 1747 padsize = padpos & 3;
1800 if (padsize && skb->len>padpos) { 1748 if (padsize && skb->len > padpos) {
1801 if (skb_headroom(skb) < padsize) { 1749 if (skb_headroom(skb) < padsize)
1802 ath_print(common, ATH_DBG_XMIT, 1750 return -ENOMEM;
1803 "TX CABQ padding failed\n"); 1751
1804 dev_kfree_skb_any(skb);
1805 return;
1806 }
1807 skb_push(skb, padsize); 1752 skb_push(skb, padsize);
1808 memmove(skb->data, skb->data + padsize, padpos); 1753 memmove(skb->data, skb->data + padsize, padpos);
1809 } 1754 }
1810 1755
1811 txctl.txq = sc->beacon.cabq; 1756 setup_frame_info(hw, skb, frmlen);
1812 1757
1813 ath_print(common, ATH_DBG_XMIT, 1758 /*
1814 "transmitting CABQ packet, skb: %p\n", skb); 1759 * At this point, the vif, hw_key and sta pointers in the tx control
1760 * info are no longer valid (overwritten by the ath_frame_info data.
1761 */
1815 1762
1816 if (ath_tx_start(hw, skb, &txctl) != 0) { 1763 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1817 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); 1764 if (unlikely(!bf))
1818 goto exit; 1765 return -ENOMEM;
1766
1767 q = skb_get_queue_mapping(skb);
1768 spin_lock_bh(&txq->axq_lock);
1769 if (txq == sc->tx.txq_map[q] &&
1770 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1771 ath_mac80211_stop_queue(sc, q);
1772 txq->stopped = 1;
1819 } 1773 }
1774 spin_unlock_bh(&txq->axq_lock);
1820 1775
1821 return; 1776 ath_tx_start_dma(sc, bf, txctl);
1822exit: 1777
1823 dev_kfree_skb_any(skb); 1778 return 0;
1824} 1779}
1825 1780
1826/*****************/ 1781/*****************/
@@ -1828,7 +1783,7 @@ exit:
1828/*****************/ 1783/*****************/
1829 1784
1830static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1785static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1831 struct ath_wiphy *aphy, int tx_flags, 1786 struct ath_wiphy *aphy, int tx_flags, int ftype,
1832 struct ath_txq *txq) 1787 struct ath_txq *txq)
1833{ 1788{
1834 struct ieee80211_hw *hw = sc->hw; 1789 struct ieee80211_hw *hw = sc->hw;
@@ -1872,8 +1827,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1872 PS_WAIT_FOR_TX_ACK)); 1827 PS_WAIT_FOR_TX_ACK));
1873 } 1828 }
1874 1829
1875 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL)) 1830 if (unlikely(ftype))
1876 ath9k_tx_status(hw, skb); 1831 ath9k_tx_status(hw, skb, ftype);
1877 else { 1832 else {
1878 q = skb_get_queue_mapping(skb); 1833 q = skb_get_queue_mapping(skb);
1879 if (txq == sc->tx.txq_map[q]) { 1834 if (txq == sc->tx.txq_map[q]) {
@@ -1909,15 +1864,14 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1909 bf->bf_buf_addr = 0; 1864 bf->bf_buf_addr = 0;
1910 1865
1911 if (bf->bf_state.bfs_paprd) { 1866 if (bf->bf_state.bfs_paprd) {
1912 if (time_after(jiffies, 1867 if (!sc->paprd_pending)
1913 bf->bf_state.bfs_paprd_timestamp +
1914 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1915 dev_kfree_skb_any(skb); 1868 dev_kfree_skb_any(skb);
1916 else 1869 else
1917 complete(&sc->paprd_complete); 1870 complete(&sc->paprd_complete);
1918 } else { 1871 } else {
1919 ath_debug_stat_tx(sc, bf, ts); 1872 ath_debug_stat_tx(sc, bf, ts);
1920 ath_tx_complete(sc, skb, bf->aphy, tx_flags, txq); 1873 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1874 bf->bf_state.bfs_ftype, txq);
1921 } 1875 }
1922 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 1876 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1923 * accidentally reference it later. 1877 * accidentally reference it later.
@@ -1932,42 +1886,15 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1932 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 1886 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1933} 1887}
1934 1888
1935static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1936 struct ath_tx_status *ts, int txok)
1937{
1938 u16 seq_st = 0;
1939 u32 ba[WME_BA_BMP_SIZE >> 5];
1940 int ba_index;
1941 int nbad = 0;
1942 int isaggr = 0;
1943
1944 if (bf->bf_lastbf->bf_tx_aborted)
1945 return 0;
1946
1947 isaggr = bf_isaggr(bf);
1948 if (isaggr) {
1949 seq_st = ts->ts_seqnum;
1950 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
1951 }
1952
1953 while (bf) {
1954 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1955 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1956 nbad++;
1957
1958 bf = bf->bf_next;
1959 }
1960
1961 return nbad;
1962}
1963
1964static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, 1889static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1965 int nbad, int txok, bool update_rc) 1890 int nframes, int nbad, int txok, bool update_rc)
1966{ 1891{
1967 struct sk_buff *skb = bf->bf_mpdu; 1892 struct sk_buff *skb = bf->bf_mpdu;
1968 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1893 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1969 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1894 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1970 struct ieee80211_hw *hw = bf->aphy->hw; 1895 struct ieee80211_hw *hw = bf->aphy->hw;
1896 struct ath_softc *sc = bf->aphy->sc;
1897 struct ath_hw *ah = sc->sc_ah;
1971 u8 i, tx_rateindex; 1898 u8 i, tx_rateindex;
1972 1899
1973 if (txok) 1900 if (txok)
@@ -1981,22 +1908,32 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1981 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) { 1908 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1982 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 1909 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1983 1910
1984 BUG_ON(nbad > bf->bf_nframes); 1911 BUG_ON(nbad > nframes);
1985 1912
1986 tx_info->status.ampdu_len = bf->bf_nframes; 1913 tx_info->status.ampdu_len = nframes;
1987 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad; 1914 tx_info->status.ampdu_ack_len = nframes - nbad;
1988 } 1915 }
1989 1916
1990 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 1917 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1991 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1918 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1992 if (ieee80211_is_data(hdr->frame_control)) { 1919 /*
1993 if (ts->ts_flags & 1920 * If an underrun error is seen assume it as an excessive
1994 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN)) 1921 * retry only if max frame trigger level has been reached
1995 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN; 1922 * (2 KB for single stream, and 4 KB for dual stream).
1996 if ((ts->ts_status & ATH9K_TXERR_XRETRY) || 1923 * Adjust the long retry as if the frame was tried
1997 (ts->ts_status & ATH9K_TXERR_FIFO)) 1924 * hw->max_rate_tries times to affect how rate control updates
1998 tx_info->pad[0] |= ATH_TX_INFO_XRETRY; 1925 * PER for the failed rate.
1999 } 1926 * In case of congestion on the bus penalizing this type of
1927 * underruns should help hardware actually transmit new frames
1928 * successfully by eventually preferring slower rates.
1929 * This itself should also alleviate congestion on the bus.
1930 */
1931 if (ieee80211_is_data(hdr->frame_control) &&
1932 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1933 ATH9K_TX_DELIM_UNDERRUN)) &&
1934 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1935 tx_info->status.rates[tx_rateindex].count =
1936 hw->max_rate_tries;
2000 } 1937 }
2001 1938
2002 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 1939 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
@@ -2103,13 +2040,14 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2103 */ 2040 */
2104 if (ts.ts_status & ATH9K_TXERR_XRETRY) 2041 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2105 bf->bf_state.bf_type |= BUF_XRETRY; 2042 bf->bf_state.bf_type |= BUF_XRETRY;
2106 ath_tx_rc_status(bf, &ts, txok ? 0 : 1, txok, true); 2043 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
2107 } 2044 }
2108 2045
2109 qnum = skb_get_queue_mapping(bf->bf_mpdu); 2046 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2110 2047
2111 if (bf_isampdu(bf)) 2048 if (bf_isampdu(bf))
2112 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok); 2049 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2050 true);
2113 else 2051 else
2114 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0); 2052 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2115 2053
@@ -2225,13 +2163,14 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2225 if (!bf_isampdu(bf)) { 2163 if (!bf_isampdu(bf)) {
2226 if (txs.ts_status & ATH9K_TXERR_XRETRY) 2164 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2227 bf->bf_state.bf_type |= BUF_XRETRY; 2165 bf->bf_state.bf_type |= BUF_XRETRY;
2228 ath_tx_rc_status(bf, &txs, txok ? 0 : 1, txok, true); 2166 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
2229 } 2167 }
2230 2168
2231 qnum = skb_get_queue_mapping(bf->bf_mpdu); 2169 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2232 2170
2233 if (bf_isampdu(bf)) 2171 if (bf_isampdu(bf))
2234 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok); 2172 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2173 txok, true);
2235 else 2174 else
2236 ath_tx_complete_buf(sc, bf, txq, &bf_head, 2175 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2237 &txs, txok, 0); 2176 &txs, txok, 0);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 08:36:41 -0400