diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
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committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/mtd/devices/tegra_nand.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'drivers/mtd/devices/tegra_nand.h')
-rw-r--r-- | drivers/mtd/devices/tegra_nand.h | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/drivers/mtd/devices/tegra_nand.h b/drivers/mtd/devices/tegra_nand.h new file mode 100644 index 00000000000..339d6cc7330 --- /dev/null +++ b/drivers/mtd/devices/tegra_nand.h | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * drivers/mtd/devices/tegra_nand.h | ||
3 | * | ||
4 | * Copyright (C) 2010 Google, Inc. | ||
5 | * Author: Dima Zavin <dima@android.com> | ||
6 | * Colin Cross <ccross@android.com> | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #ifndef __MTD_DEV_TEGRA_NAND_H | ||
20 | #define __MTD_DEV_TEGRA_NAND_H | ||
21 | |||
22 | #include <mach/io.h> | ||
23 | |||
24 | #define __BITMASK0(len) ((1 << (len)) - 1) | ||
25 | #define __BITMASK(start, len) (__BITMASK0(len) << (start)) | ||
26 | #define REG_BIT(bit) (1 << (bit)) | ||
27 | #define REG_FIELD(val, start, len) (((val) & __BITMASK0(len)) << (start)) | ||
28 | #define REG_FIELD_MASK(start, len) (~(__BITMASK((start), (len)))) | ||
29 | #define REG_GET_FIELD(val, start, len) (((val) >> (start)) & __BITMASK0(len)) | ||
30 | |||
31 | /* tegra nand registers... */ | ||
32 | #define TEGRA_NAND_PHYS 0x70008000 | ||
33 | #define TEGRA_NAND_BASE IO_TO_VIRT(TEGRA_NAND_PHYS) | ||
34 | #define COMMAND_REG (TEGRA_NAND_BASE + 0x00) | ||
35 | #define STATUS_REG (TEGRA_NAND_BASE + 0x04) | ||
36 | #define ISR_REG (TEGRA_NAND_BASE + 0x08) | ||
37 | #define IER_REG (TEGRA_NAND_BASE + 0x0c) | ||
38 | #define CONFIG_REG (TEGRA_NAND_BASE + 0x10) | ||
39 | #define TIMING_REG (TEGRA_NAND_BASE + 0x14) | ||
40 | #define RESP_REG (TEGRA_NAND_BASE + 0x18) | ||
41 | #define TIMING2_REG (TEGRA_NAND_BASE + 0x1c) | ||
42 | #define CMD_REG1 (TEGRA_NAND_BASE + 0x20) | ||
43 | #define CMD_REG2 (TEGRA_NAND_BASE + 0x24) | ||
44 | #define ADDR_REG1 (TEGRA_NAND_BASE + 0x28) | ||
45 | #define ADDR_REG2 (TEGRA_NAND_BASE + 0x2c) | ||
46 | #define DMA_MST_CTRL_REG (TEGRA_NAND_BASE + 0x30) | ||
47 | #define DMA_CFG_A_REG (TEGRA_NAND_BASE + 0x34) | ||
48 | #define DMA_CFG_B_REG (TEGRA_NAND_BASE + 0x38) | ||
49 | #define FIFO_CTRL_REG (TEGRA_NAND_BASE + 0x3c) | ||
50 | #define DATA_BLOCK_PTR_REG (TEGRA_NAND_BASE + 0x40) | ||
51 | #define TAG_PTR_REG (TEGRA_NAND_BASE + 0x44) | ||
52 | #define ECC_PTR_REG (TEGRA_NAND_BASE + 0x48) | ||
53 | #define DEC_STATUS_REG (TEGRA_NAND_BASE + 0x4c) | ||
54 | #define HWSTATUS_CMD_REG (TEGRA_NAND_BASE + 0x50) | ||
55 | #define HWSTATUS_MASK_REG (TEGRA_NAND_BASE + 0x54) | ||
56 | #define LL_CONFIG_REG (TEGRA_NAND_BASE + 0x58) | ||
57 | #define LL_PTR_REG (TEGRA_NAND_BASE + 0x5c) | ||
58 | #define LL_STATUS_REG (TEGRA_NAND_BASE + 0x60) | ||
59 | |||
60 | /* nand_command bits */ | ||
61 | #define COMMAND_GO REG_BIT(31) | ||
62 | #define COMMAND_CLE REG_BIT(30) | ||
63 | #define COMMAND_ALE REG_BIT(29) | ||
64 | #define COMMAND_PIO REG_BIT(28) | ||
65 | #define COMMAND_TX REG_BIT(27) | ||
66 | #define COMMAND_RX REG_BIT(26) | ||
67 | #define COMMAND_SEC_CMD REG_BIT(25) | ||
68 | #define COMMAND_AFT_DAT REG_BIT(24) | ||
69 | #define COMMAND_TRANS_SIZE(val) REG_FIELD((val), 20, 4) | ||
70 | #define COMMAND_A_VALID REG_BIT(19) | ||
71 | #define COMMAND_B_VALID REG_BIT(18) | ||
72 | #define COMMAND_RD_STATUS_CHK REG_BIT(17) | ||
73 | #define COMMAND_RBSY_CHK REG_BIT(16) | ||
74 | #define COMMAND_CE(val) REG_BIT(8 + ((val) & 0x7)) | ||
75 | #define COMMAND_CLE_BYTE_SIZE(val) REG_FIELD((val), 4, 2) | ||
76 | #define COMMAND_ALE_BYTE_SIZE(val) REG_FIELD((val), 0, 4) | ||
77 | |||
78 | /* nand isr bits */ | ||
79 | #define ISR_UND REG_BIT(7) | ||
80 | #define ISR_OVR REG_BIT(6) | ||
81 | #define ISR_CMD_DONE REG_BIT(5) | ||
82 | #define ISR_ECC_ERR REG_BIT(4) | ||
83 | |||
84 | /* nand ier bits */ | ||
85 | #define IER_ERR_TRIG_VAL(val) REG_FIELD((val), 16, 4) | ||
86 | #define IER_UND REG_BIT(7) | ||
87 | #define IER_OVR REG_BIT(6) | ||
88 | #define IER_CMD_DONE REG_BIT(5) | ||
89 | #define IER_ECC_ERR REG_BIT(4) | ||
90 | #define IER_GIE REG_BIT(0) | ||
91 | |||
92 | /* nand config bits */ | ||
93 | #define CONFIG_HW_ECC REG_BIT(31) | ||
94 | #define CONFIG_ECC_SEL REG_BIT(30) | ||
95 | #define CONFIG_HW_ERR_CORRECTION REG_BIT(29) | ||
96 | #define CONFIG_PIPELINE_EN REG_BIT(28) | ||
97 | #define CONFIG_ECC_EN_TAG REG_BIT(27) | ||
98 | #define CONFIG_TVALUE(val) REG_FIELD((val), 24, 2) | ||
99 | #define CONFIG_SKIP_SPARE REG_BIT(23) | ||
100 | #define CONFIG_COM_BSY REG_BIT(22) | ||
101 | #define CONFIG_BUS_WIDTH REG_BIT(21) | ||
102 | #define CONFIG_EDO_MODE REG_BIT(19) | ||
103 | #define CONFIG_PAGE_SIZE_SEL(val) REG_FIELD((val), 16, 3) | ||
104 | #define CONFIG_SKIP_SPARE_SEL(val) REG_FIELD((val), 14, 2) | ||
105 | #define CONFIG_TAG_BYTE_SIZE(val) REG_FIELD((val), 0, 8) | ||
106 | |||
107 | /* nand timing bits */ | ||
108 | #define TIMING_TRP_RESP(val) REG_FIELD((val), 28, 4) | ||
109 | #define TIMING_TWB(val) REG_FIELD((val), 24, 4) | ||
110 | #define TIMING_TCR_TAR_TRR(val) REG_FIELD((val), 20, 4) | ||
111 | #define TIMING_TWHR(val) REG_FIELD((val), 16, 4) | ||
112 | #define TIMING_TCS(val) REG_FIELD((val), 14, 2) | ||
113 | #define TIMING_TWH(val) REG_FIELD((val), 12, 2) | ||
114 | #define TIMING_TWP(val) REG_FIELD((val), 8, 4) | ||
115 | #define TIMING_TRH(val) REG_FIELD((val), 4, 2) | ||
116 | #define TIMING_TRP(val) REG_FIELD((val), 0, 4) | ||
117 | |||
118 | /* nand timing2 bits */ | ||
119 | #define TIMING2_TADL(val) REG_FIELD((val), 0, 4) | ||
120 | |||
121 | /* nand dma_mst_ctrl bits */ | ||
122 | #define DMA_CTRL_DMA_GO REG_BIT(31) | ||
123 | #define DMA_CTRL_DIR REG_BIT(30) | ||
124 | #define DMA_CTRL_DMA_PERF_EN REG_BIT(29) | ||
125 | #define DMA_CTRL_IE_DMA_DONE REG_BIT(28) | ||
126 | #define DMA_CTRL_REUSE_BUFFER REG_BIT(27) | ||
127 | #define DMA_CTRL_BURST_SIZE(val) REG_FIELD((val), 24, 3) | ||
128 | #define DMA_CTRL_IS_DMA_DONE REG_BIT(20) | ||
129 | #define DMA_CTRL_DMA_EN_A REG_BIT(2) | ||
130 | #define DMA_CTRL_DMA_EN_B REG_BIT(1) | ||
131 | |||
132 | /* nand dma_cfg_a/cfg_b bits */ | ||
133 | #define DMA_CFG_BLOCK_SIZE(val) REG_FIELD((val), 0, 16) | ||
134 | |||
135 | /* nand dec_status bits */ | ||
136 | #define DEC_STATUS_ERR_PAGE_NUM(val) REG_GET_FIELD((val), 24, 8) | ||
137 | #define DEC_STATUS_ERR_CNT(val) REG_GET_FIELD((val), 16, 8) | ||
138 | #define DEC_STATUS_ECC_FAIL_A REG_BIT(1) | ||
139 | #define DEC_STATUS_ECC_FAIL_B REG_BIT(0) | ||
140 | |||
141 | /* nand hwstatus_mask bits */ | ||
142 | #define HWSTATUS_RDSTATUS_MASK(val) REG_FIELD((val), 24, 8) | ||
143 | #define HWSTATUS_RDSTATUS_EXP_VAL(val) REG_FIELD((val), 16, 8) | ||
144 | #define HWSTATUS_RBSY_MASK(val) REG_FIELD((val), 8, 8) | ||
145 | #define HWSTATUS_RBSY_EXP_VAL(val) REG_FIELD((val), 0, 8) | ||
146 | |||
147 | #endif | ||
148 | |||